[
  {
    "path": ".gitignore",
    "content": "# build directories\nbuild*/\nbin*/\n\n# test directories\ntest_priv/\n"
  },
  {
    "path": ".vscode/settings.json",
    "content": "{\n    \"files.associations\": {\n        \"system_dspic33ep128gs804.h\": \"c\"\n    }\n}"
  },
  {
    "path": "3rd_party/CMSIS/Include/cmsis_armcc.h",
    "content": "/**************************************************************************//**\n * @file     cmsis_armcc.h\n * @brief    CMSIS compiler ARMCC (Arm Compiler 5) header file\n * @version  V5.1.0\n * @date     08. May 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef __CMSIS_ARMCC_H\n#define __CMSIS_ARMCC_H\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)\n  #error \"Please use Arm Compiler Toolchain V4.0.677 or later!\"\n#endif\n\n/* CMSIS compiler control architecture macros */\n#if ((defined (__TARGET_ARCH_6_M  ) && (__TARGET_ARCH_6_M   == 1)) || \\\n     (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M  == 1))   )\n  #define __ARM_ARCH_6M__           1\n#endif\n\n#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M  == 1))\n  #define __ARM_ARCH_7M__           1\n#endif\n\n#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))\n  #define __ARM_ARCH_7EM__          1\n#endif\n\n  /* __ARM_ARCH_8M_BASE__  not applicable */\n  /* __ARM_ARCH_8M_MAIN__  not applicable */\n\n/* CMSIS compiler control DSP macros */\n#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )\n  #define __ARM_FEATURE_DSP         1\n#endif\n\n/* CMSIS compiler specific defines */\n#ifndef   __ASM\n  #define __ASM                                  __asm\n#endif\n#ifndef   __INLINE\n  #define __INLINE                               __inline\n#endif\n#ifndef   __STATIC_INLINE\n  #define __STATIC_INLINE                        static __inline\n#endif\n#ifndef   __STATIC_FORCEINLINE\n  #define __STATIC_FORCEINLINE                   static __forceinline\n#endif\n#ifndef   __NO_RETURN\n  #define __NO_RETURN                            __declspec(noreturn)\n#endif\n#ifndef   __USED\n  #define __USED                                 __attribute__((used))\n#endif\n#ifndef   __WEAK\n  #define __WEAK                                 __attribute__((weak))\n#endif\n#ifndef   __PACKED\n  #define __PACKED                               __attribute__((packed))\n#endif\n#ifndef   __PACKED_STRUCT\n  #define __PACKED_STRUCT                        __packed struct\n#endif\n#ifndef   __PACKED_UNION\n  #define __PACKED_UNION                         __packed union\n#endif\n#ifndef   __UNALIGNED_UINT32        /* deprecated */\n  #define __UNALIGNED_UINT32(x)                  (*((__packed uint32_t *)(x)))\n#endif\n#ifndef   __UNALIGNED_UINT16_WRITE\n  #define __UNALIGNED_UINT16_WRITE(addr, val)    ((*((__packed uint16_t *)(addr))) = (val))\n#endif\n#ifndef   __UNALIGNED_UINT16_READ\n  #define __UNALIGNED_UINT16_READ(addr)          (*((const __packed uint16_t *)(addr)))\n#endif\n#ifndef   __UNALIGNED_UINT32_WRITE\n  #define __UNALIGNED_UINT32_WRITE(addr, val)    ((*((__packed uint32_t *)(addr))) = (val))\n#endif\n#ifndef   __UNALIGNED_UINT32_READ\n  #define __UNALIGNED_UINT32_READ(addr)          (*((const __packed uint32_t *)(addr)))\n#endif\n#ifndef   __ALIGNED\n  #define __ALIGNED(x)                           __attribute__((aligned(x)))\n#endif\n#ifndef   __RESTRICT\n  #define __RESTRICT                             __restrict\n#endif\n#ifndef   __COMPILER_BARRIER\n  #define __COMPILER_BARRIER()                   __memory_changed()\n#endif\n\n/* #########################  Startup and Lowlevel Init  ######################## */\n\n#ifndef __PROGRAM_START\n#define __PROGRAM_START           __main\n#endif\n\n#ifndef __INITIAL_SP\n#define __INITIAL_SP              Image$$ARM_LIB_STACK$$ZI$$Limit\n#endif\n\n#ifndef __STACK_LIMIT\n#define __STACK_LIMIT             Image$$ARM_LIB_STACK$$ZI$$Base\n#endif\n\n#ifndef __VECTOR_TABLE\n#define __VECTOR_TABLE            __Vectors\n#endif\n\n#ifndef __VECTOR_TABLE_ATTRIBUTE\n#define __VECTOR_TABLE_ATTRIBUTE  __attribute((used, section(\"RESET\")))\n#endif\n\n/* ###########################  Core Function Access  ########################### */\n/** \\ingroup  CMSIS_Core_FunctionInterface\n    \\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\n  @{\n */\n\n/**\n  \\brief   Enable IRQ Interrupts\n  \\details Enables IRQ interrupts by clearing the I-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n/* intrinsic void __enable_irq();     */\n\n\n/**\n  \\brief   Disable IRQ Interrupts\n  \\details Disables IRQ interrupts by setting the I-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n/* intrinsic void __disable_irq();    */\n\n/**\n  \\brief   Get Control Register\n  \\details Returns the content of the Control Register.\n  \\return               Control Register value\n */\n__STATIC_INLINE uint32_t __get_CONTROL(void)\n{\n  register uint32_t __regControl         __ASM(\"control\");\n  return(__regControl);\n}\n\n\n/**\n  \\brief   Set Control Register\n  \\details Writes the given value to the Control Register.\n  \\param [in]    control  Control Register value to set\n */\n__STATIC_INLINE void __set_CONTROL(uint32_t control)\n{\n  register uint32_t __regControl         __ASM(\"control\");\n  __regControl = control;\n}\n\n\n/**\n  \\brief   Get IPSR Register\n  \\details Returns the content of the IPSR Register.\n  \\return               IPSR Register value\n */\n__STATIC_INLINE uint32_t __get_IPSR(void)\n{\n  register uint32_t __regIPSR          __ASM(\"ipsr\");\n  return(__regIPSR);\n}\n\n\n/**\n  \\brief   Get APSR Register\n  \\details Returns the content of the APSR Register.\n  \\return               APSR Register value\n */\n__STATIC_INLINE uint32_t __get_APSR(void)\n{\n  register uint32_t __regAPSR          __ASM(\"apsr\");\n  return(__regAPSR);\n}\n\n\n/**\n  \\brief   Get xPSR Register\n  \\details Returns the content of the xPSR Register.\n  \\return               xPSR Register value\n */\n__STATIC_INLINE uint32_t __get_xPSR(void)\n{\n  register uint32_t __regXPSR          __ASM(\"xpsr\");\n  return(__regXPSR);\n}\n\n\n/**\n  \\brief   Get Process Stack Pointer\n  \\details Returns the current value of the Process Stack Pointer (PSP).\n  \\return               PSP Register value\n */\n__STATIC_INLINE uint32_t __get_PSP(void)\n{\n  register uint32_t __regProcessStackPointer  __ASM(\"psp\");\n  return(__regProcessStackPointer);\n}\n\n\n/**\n  \\brief   Set Process Stack Pointer\n  \\details Assigns the given value to the Process Stack Pointer (PSP).\n  \\param [in]    topOfProcStack  Process Stack Pointer value to set\n */\n__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)\n{\n  register uint32_t __regProcessStackPointer  __ASM(\"psp\");\n  __regProcessStackPointer = topOfProcStack;\n}\n\n\n/**\n  \\brief   Get Main Stack Pointer\n  \\details Returns the current value of the Main Stack Pointer (MSP).\n  \\return               MSP Register value\n */\n__STATIC_INLINE uint32_t __get_MSP(void)\n{\n  register uint32_t __regMainStackPointer     __ASM(\"msp\");\n  return(__regMainStackPointer);\n}\n\n\n/**\n  \\brief   Set Main Stack Pointer\n  \\details Assigns the given value to the Main Stack Pointer (MSP).\n  \\param [in]    topOfMainStack  Main Stack Pointer value to set\n */\n__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)\n{\n  register uint32_t __regMainStackPointer     __ASM(\"msp\");\n  __regMainStackPointer = topOfMainStack;\n}\n\n\n/**\n  \\brief   Get Priority Mask\n  \\details Returns the current state of the priority mask bit from the Priority Mask Register.\n  \\return               Priority Mask value\n */\n__STATIC_INLINE uint32_t __get_PRIMASK(void)\n{\n  register uint32_t __regPriMask         __ASM(\"primask\");\n  return(__regPriMask);\n}\n\n\n/**\n  \\brief   Set Priority Mask\n  \\details Assigns the given value to the Priority Mask Register.\n  \\param [in]    priMask  Priority Mask\n */\n__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)\n{\n  register uint32_t __regPriMask         __ASM(\"primask\");\n  __regPriMask = (priMask);\n}\n\n\n#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \\\n     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )\n\n/**\n  \\brief   Enable FIQ\n  \\details Enables FIQ interrupts by clearing the F-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n#define __enable_fault_irq                __enable_fiq\n\n\n/**\n  \\brief   Disable FIQ\n  \\details Disables FIQ interrupts by setting the F-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n#define __disable_fault_irq               __disable_fiq\n\n\n/**\n  \\brief   Get Base Priority\n  \\details Returns the current value of the Base Priority register.\n  \\return               Base Priority register value\n */\n__STATIC_INLINE uint32_t  __get_BASEPRI(void)\n{\n  register uint32_t __regBasePri         __ASM(\"basepri\");\n  return(__regBasePri);\n}\n\n\n/**\n  \\brief   Set Base Priority\n  \\details Assigns the given value to the Base Priority register.\n  \\param [in]    basePri  Base Priority value to set\n */\n__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)\n{\n  register uint32_t __regBasePri         __ASM(\"basepri\");\n  __regBasePri = (basePri & 0xFFU);\n}\n\n\n/**\n  \\brief   Set Base Priority with condition\n  \\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\n           or the new value increases the BASEPRI priority level.\n  \\param [in]    basePri  Base Priority value to set\n */\n__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)\n{\n  register uint32_t __regBasePriMax      __ASM(\"basepri_max\");\n  __regBasePriMax = (basePri & 0xFFU);\n}\n\n\n/**\n  \\brief   Get Fault Mask\n  \\details Returns the current value of the Fault Mask register.\n  \\return               Fault Mask register value\n */\n__STATIC_INLINE uint32_t __get_FAULTMASK(void)\n{\n  register uint32_t __regFaultMask       __ASM(\"faultmask\");\n  return(__regFaultMask);\n}\n\n\n/**\n  \\brief   Set Fault Mask\n  \\details Assigns the given value to the Fault Mask register.\n  \\param [in]    faultMask  Fault Mask value to set\n */\n__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)\n{\n  register uint32_t __regFaultMask       __ASM(\"faultmask\");\n  __regFaultMask = (faultMask & (uint32_t)1U);\n}\n\n#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \\\n           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */\n\n\n/**\n  \\brief   Get FPSCR\n  \\details Returns the current value of the Floating Point Status/Control register.\n  \\return               Floating Point Status/Control register value\n */\n__STATIC_INLINE uint32_t __get_FPSCR(void)\n{\n#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\\n     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )\n  register uint32_t __regfpscr         __ASM(\"fpscr\");\n  return(__regfpscr);\n#else\n   return(0U);\n#endif\n}\n\n\n/**\n  \\brief   Set FPSCR\n  \\details Assigns the given value to the Floating Point Status/Control register.\n  \\param [in]    fpscr  Floating Point Status/Control value to set\n */\n__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)\n{\n#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\\n     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )\n  register uint32_t __regfpscr         __ASM(\"fpscr\");\n  __regfpscr = (fpscr);\n#else\n  (void)fpscr;\n#endif\n}\n\n\n/*@} end of CMSIS_Core_RegAccFunctions */\n\n\n/* ##########################  Core Instruction Access  ######################### */\n/** \\defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\n  Access to dedicated instructions\n  @{\n*/\n\n/**\n  \\brief   No Operation\n  \\details No Operation does nothing. This instruction can be used for code alignment purposes.\n */\n#define __NOP                             __nop\n\n\n/**\n  \\brief   Wait For Interrupt\n  \\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\n */\n#define __WFI                             __wfi\n\n\n/**\n  \\brief   Wait For Event\n  \\details Wait For Event is a hint instruction that permits the processor to enter\n           a low-power state until one of a number of events occurs.\n */\n#define __WFE                             __wfe\n\n\n/**\n  \\brief   Send Event\n  \\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\n */\n#define __SEV                             __sev\n\n\n/**\n  \\brief   Instruction Synchronization Barrier\n  \\details Instruction Synchronization Barrier flushes the pipeline in the processor,\n           so that all instructions following the ISB are fetched from cache or memory,\n           after the instruction has been completed.\n */\n#define __ISB() do {\\\n                   __schedule_barrier();\\\n                   __isb(0xF);\\\n                   __schedule_barrier();\\\n                } while (0U)\n\n/**\n  \\brief   Data Synchronization Barrier\n  \\details Acts as a special kind of Data Memory Barrier.\n           It completes when all explicit memory accesses before this instruction complete.\n */\n#define __DSB() do {\\\n                   __schedule_barrier();\\\n                   __dsb(0xF);\\\n                   __schedule_barrier();\\\n                } while (0U)\n\n/**\n  \\brief   Data Memory Barrier\n  \\details Ensures the apparent order of the explicit memory operations before\n           and after the instruction, without ensuring their completion.\n */\n#define __DMB() do {\\\n                   __schedule_barrier();\\\n                   __dmb(0xF);\\\n                   __schedule_barrier();\\\n                } while (0U)\n\n\n/**\n  \\brief   Reverse byte order (32 bit)\n  \\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n#define __REV                             __rev\n\n\n/**\n  \\brief   Reverse byte order (16 bit)\n  \\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n#ifndef __NO_EMBEDDED_ASM\n__attribute__((section(\".rev16_text\"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)\n{\n  rev16 r0, r0\n  bx lr\n}\n#endif\n\n\n/**\n  \\brief   Reverse byte order (16 bit)\n  \\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n#ifndef __NO_EMBEDDED_ASM\n__attribute__((section(\".revsh_text\"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)\n{\n  revsh r0, r0\n  bx lr\n}\n#endif\n\n\n/**\n  \\brief   Rotate Right in unsigned value (32 bit)\n  \\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\n  \\param [in]    op1  Value to rotate\n  \\param [in]    op2  Number of Bits to rotate\n  \\return               Rotated value\n */\n#define __ROR                             __ror\n\n\n/**\n  \\brief   Breakpoint\n  \\details Causes the processor to enter Debug state.\n           Debug tools can use this to investigate system state when the instruction at a particular address is reached.\n  \\param [in]    value  is ignored by the processor.\n                 If required, a debugger can use it to store additional information about the breakpoint.\n */\n#define __BKPT(value)                       __breakpoint(value)\n\n\n/**\n  \\brief   Reverse bit order of value\n  \\details Reverses the bit order of the given value.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \\\n     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )\n  #define __RBIT                          __rbit\n#else\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)\n{\n  uint32_t result;\n  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */\n\n  result = value;                      /* r will be reversed bits of v; first get LSB of v */\n  for (value >>= 1U; value != 0U; value >>= 1U)\n  {\n    result <<= 1U;\n    result |= value & 1U;\n    s--;\n  }\n  result <<= s;                        /* shift when v's highest bits are zero */\n  return result;\n}\n#endif\n\n\n/**\n  \\brief   Count leading zeros\n  \\details Counts the number of leading zeros of a data value.\n  \\param [in]  value  Value to count the leading zeros\n  \\return             number of leading zeros in value\n */\n#define __CLZ                             __clz\n\n\n#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \\\n     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )\n\n/**\n  \\brief   LDR Exclusive (8 bit)\n  \\details Executes a exclusive LDR instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\n  #define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))\n#else\n  #define __LDREXB(ptr)          _Pragma(\"push\") _Pragma(\"diag_suppress 3731\") ((uint8_t ) __ldrex(ptr))  _Pragma(\"pop\")\n#endif\n\n\n/**\n  \\brief   LDR Exclusive (16 bit)\n  \\details Executes a exclusive LDR instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\n  #define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))\n#else\n  #define __LDREXH(ptr)          _Pragma(\"push\") _Pragma(\"diag_suppress 3731\") ((uint16_t) __ldrex(ptr))  _Pragma(\"pop\")\n#endif\n\n\n/**\n  \\brief   LDR Exclusive (32 bit)\n  \\details Executes a exclusive LDR instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\n  #define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))\n#else\n  #define __LDREXW(ptr)          _Pragma(\"push\") _Pragma(\"diag_suppress 3731\") ((uint32_t ) __ldrex(ptr))  _Pragma(\"pop\")\n#endif\n\n\n/**\n  \\brief   STR Exclusive (8 bit)\n  \\details Executes a exclusive STR instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\n  #define __STREXB(value, ptr)                                                 __strex(value, ptr)\n#else\n  #define __STREXB(value, ptr)   _Pragma(\"push\") _Pragma(\"diag_suppress 3731\") __strex(value, ptr)        _Pragma(\"pop\")\n#endif\n\n\n/**\n  \\brief   STR Exclusive (16 bit)\n  \\details Executes a exclusive STR instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\n  #define __STREXH(value, ptr)                                                 __strex(value, ptr)\n#else\n  #define __STREXH(value, ptr)   _Pragma(\"push\") _Pragma(\"diag_suppress 3731\") __strex(value, ptr)        _Pragma(\"pop\")\n#endif\n\n\n/**\n  \\brief   STR Exclusive (32 bit)\n  \\details Executes a exclusive STR instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\n  #define __STREXW(value, ptr)                                                 __strex(value, ptr)\n#else\n  #define __STREXW(value, ptr)   _Pragma(\"push\") _Pragma(\"diag_suppress 3731\") __strex(value, ptr)        _Pragma(\"pop\")\n#endif\n\n\n/**\n  \\brief   Remove the exclusive lock\n  \\details Removes the exclusive lock which is created by LDREX.\n */\n#define __CLREX                           __clrex\n\n\n/**\n  \\brief   Signed Saturate\n  \\details Saturates a signed value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (1..32)\n  \\return             Saturated value\n */\n#define __SSAT                            __ssat\n\n\n/**\n  \\brief   Unsigned Saturate\n  \\details Saturates an unsigned value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (0..31)\n  \\return             Saturated value\n */\n#define __USAT                            __usat\n\n\n/**\n  \\brief   Rotate Right with Extend (32 bit)\n  \\details Moves each bit of a bitstring right by one bit.\n           The carry input is shifted in at the left end of the bitstring.\n  \\param [in]    value  Value to rotate\n  \\return               Rotated value\n */\n#ifndef __NO_EMBEDDED_ASM\n__attribute__((section(\".rrx_text\"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)\n{\n  rrx r0, r0\n  bx lr\n}\n#endif\n\n\n/**\n  \\brief   LDRT Unprivileged (8 bit)\n  \\details Executes a Unprivileged LDRT instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))\n\n\n/**\n  \\brief   LDRT Unprivileged (16 bit)\n  \\details Executes a Unprivileged LDRT instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))\n\n\n/**\n  \\brief   LDRT Unprivileged (32 bit)\n  \\details Executes a Unprivileged LDRT instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))\n\n\n/**\n  \\brief   STRT Unprivileged (8 bit)\n  \\details Executes a Unprivileged STRT instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n#define __STRBT(value, ptr)               __strt(value, ptr)\n\n\n/**\n  \\brief   STRT Unprivileged (16 bit)\n  \\details Executes a Unprivileged STRT instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n#define __STRHT(value, ptr)               __strt(value, ptr)\n\n\n/**\n  \\brief   STRT Unprivileged (32 bit)\n  \\details Executes a Unprivileged STRT instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n#define __STRT(value, ptr)                __strt(value, ptr)\n\n#else  /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \\\n           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */\n\n/**\n  \\brief   Signed Saturate\n  \\details Saturates a signed value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (1..32)\n  \\return             Saturated value\n */\n__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)\n{\n  if ((sat >= 1U) && (sat <= 32U))\n  {\n    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);\n    const int32_t min = -1 - max ;\n    if (val > max)\n    {\n      return max;\n    }\n    else if (val < min)\n    {\n      return min;\n    }\n  }\n  return val;\n}\n\n/**\n  \\brief   Unsigned Saturate\n  \\details Saturates an unsigned value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (0..31)\n  \\return             Saturated value\n */\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)\n{\n  if (sat <= 31U)\n  {\n    const uint32_t max = ((1U << sat) - 1U);\n    if (val > (int32_t)max)\n    {\n      return max;\n    }\n    else if (val < 0)\n    {\n      return 0U;\n    }\n  }\n  return (uint32_t)val;\n}\n\n#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \\\n           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */\n\n/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\n\n\n/* ###################  Compiler specific Intrinsics  ########################### */\n/** \\defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\n  Access to dedicated SIMD instructions\n  @{\n*/\n\n#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )\n\n#define __SADD8                           __sadd8\n#define __QADD8                           __qadd8\n#define __SHADD8                          __shadd8\n#define __UADD8                           __uadd8\n#define __UQADD8                          __uqadd8\n#define __UHADD8                          __uhadd8\n#define __SSUB8                           __ssub8\n#define __QSUB8                           __qsub8\n#define __SHSUB8                          __shsub8\n#define __USUB8                           __usub8\n#define __UQSUB8                          __uqsub8\n#define __UHSUB8                          __uhsub8\n#define __SADD16                          __sadd16\n#define __QADD16                          __qadd16\n#define __SHADD16                         __shadd16\n#define __UADD16                          __uadd16\n#define __UQADD16                         __uqadd16\n#define __UHADD16                         __uhadd16\n#define __SSUB16                          __ssub16\n#define __QSUB16                          __qsub16\n#define __SHSUB16                         __shsub16\n#define __USUB16                          __usub16\n#define __UQSUB16                         __uqsub16\n#define __UHSUB16                         __uhsub16\n#define __SASX                            __sasx\n#define __QASX                            __qasx\n#define __SHASX                           __shasx\n#define __UASX                            __uasx\n#define __UQASX                           __uqasx\n#define __UHASX                           __uhasx\n#define __SSAX                            __ssax\n#define __QSAX                            __qsax\n#define __SHSAX                           __shsax\n#define __USAX                            __usax\n#define __UQSAX                           __uqsax\n#define __UHSAX                           __uhsax\n#define __USAD8                           __usad8\n#define __USADA8                          __usada8\n#define __SSAT16                          __ssat16\n#define __USAT16                          __usat16\n#define __UXTB16                          __uxtb16\n#define __UXTAB16                         __uxtab16\n#define __SXTB16                          __sxtb16\n#define __SXTAB16                         __sxtab16\n#define __SMUAD                           __smuad\n#define __SMUADX                          __smuadx\n#define __SMLAD                           __smlad\n#define __SMLADX                          __smladx\n#define __SMLALD                          __smlald\n#define __SMLALDX                         __smlaldx\n#define __SMUSD                           __smusd\n#define __SMUSDX                          __smusdx\n#define __SMLSD                           __smlsd\n#define __SMLSDX                          __smlsdx\n#define __SMLSLD                          __smlsld\n#define __SMLSLDX                         __smlsldx\n#define __SEL                             __sel\n#define __QADD                            __qadd\n#define __QSUB                            __qsub\n\n#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \\\n                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )\n\n#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \\\n                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )\n\n#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \\\n                                                      ((int64_t)(ARG3) << 32U)     ) >> 32U))\n\n#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */\n/*@} end of group CMSIS_SIMD_intrinsics */\n\n\n#endif /* __CMSIS_ARMCC_H */\n"
  },
  {
    "path": "3rd_party/CMSIS/Include/cmsis_armclang.h",
    "content": "/**************************************************************************//**\n * @file     cmsis_armclang.h\n * @brief    CMSIS compiler armclang (Arm Compiler 6) header file\n * @version  V5.2.0\n * @date     08. May 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */\n\n#ifndef __CMSIS_ARMCLANG_H\n#define __CMSIS_ARMCLANG_H\n\n#pragma clang system_header   /* treat file as system include file */\n\n#ifndef __ARM_COMPAT_H\n#include <arm_compat.h>    /* Compatibility header for Arm Compiler 5 intrinsics */\n#endif\n\n/* CMSIS compiler specific defines */\n#ifndef   __ASM\n  #define __ASM                                  __asm\n#endif\n#ifndef   __INLINE\n  #define __INLINE                               __inline\n#endif\n#ifndef   __STATIC_INLINE\n  #define __STATIC_INLINE                        static __inline\n#endif\n#ifndef   __STATIC_FORCEINLINE\n  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static __inline\n#endif\n#ifndef   __NO_RETURN\n  #define __NO_RETURN                            __attribute__((__noreturn__))\n#endif\n#ifndef   __USED\n  #define __USED                                 __attribute__((used))\n#endif\n#ifndef   __WEAK\n  #define __WEAK                                 __attribute__((weak))\n#endif\n#ifndef   __PACKED\n  #define __PACKED                               __attribute__((packed, aligned(1)))\n#endif\n#ifndef   __PACKED_STRUCT\n  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))\n#endif\n#ifndef   __PACKED_UNION\n  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))\n#endif\n#ifndef   __UNALIGNED_UINT32        /* deprecated */\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wpacked\"\n/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */\n  struct __attribute__((packed)) T_UINT32 { uint32_t v; };\n  #pragma clang diagnostic pop\n  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)\n#endif\n#ifndef   __UNALIGNED_UINT16_WRITE\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wpacked\"\n/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */\n  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\n  #pragma clang diagnostic pop\n  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))\n#endif\n#ifndef   __UNALIGNED_UINT16_READ\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wpacked\"\n/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */\n  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\n  #pragma clang diagnostic pop\n  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)\n#endif\n#ifndef   __UNALIGNED_UINT32_WRITE\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wpacked\"\n/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */\n  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\n  #pragma clang diagnostic pop\n  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\n#endif\n#ifndef   __UNALIGNED_UINT32_READ\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wpacked\"\n/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */\n  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\n  #pragma clang diagnostic pop\n  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)\n#endif\n#ifndef   __ALIGNED\n  #define __ALIGNED(x)                           __attribute__((aligned(x)))\n#endif\n#ifndef   __RESTRICT\n  #define __RESTRICT                             __restrict\n#endif\n#ifndef   __COMPILER_BARRIER\n  #define __COMPILER_BARRIER()                   __ASM volatile(\"\":::\"memory\")\n#endif\n\n/* #########################  Startup and Lowlevel Init  ######################## */\n\n#ifndef __PROGRAM_START\n#define __PROGRAM_START           __main\n#endif\n\n#ifndef __INITIAL_SP\n#define __INITIAL_SP              Image$$ARM_LIB_STACK$$ZI$$Limit\n#endif\n\n#ifndef __STACK_LIMIT\n#define __STACK_LIMIT             Image$$ARM_LIB_STACK$$ZI$$Base\n#endif\n\n#ifndef __VECTOR_TABLE\n#define __VECTOR_TABLE            __Vectors\n#endif\n\n#ifndef __VECTOR_TABLE_ATTRIBUTE\n#define __VECTOR_TABLE_ATTRIBUTE  __attribute((used, section(\"RESET\")))\n#endif\n\n/* ###########################  Core Function Access  ########################### */\n/** \\ingroup  CMSIS_Core_FunctionInterface\n    \\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\n  @{\n */\n\n/**\n  \\brief   Enable IRQ Interrupts\n  \\details Enables IRQ interrupts by clearing the I-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n/* intrinsic void __enable_irq();  see arm_compat.h */\n\n\n/**\n  \\brief   Disable IRQ Interrupts\n  \\details Disables IRQ interrupts by setting the I-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n/* intrinsic void __disable_irq();  see arm_compat.h */\n\n\n/**\n  \\brief   Get Control Register\n  \\details Returns the content of the Control Register.\n  \\return               Control Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, control\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Control Register (non-secure)\n  \\details Returns the content of the non-secure Control Register when in secure mode.\n  \\return               non-secure Control Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, control_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Control Register\n  \\details Writes the given value to the Control Register.\n  \\param [in]    control  Control Register value to set\n */\n__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)\n{\n  __ASM volatile (\"MSR control, %0\" : : \"r\" (control) : \"memory\");\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Control Register (non-secure)\n  \\details Writes the given value to the non-secure Control Register when in secure state.\n  \\param [in]    control  Control Register value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)\n{\n  __ASM volatile (\"MSR control_ns, %0\" : : \"r\" (control) : \"memory\");\n}\n#endif\n\n\n/**\n  \\brief   Get IPSR Register\n  \\details Returns the content of the IPSR Register.\n  \\return               IPSR Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_IPSR(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, ipsr\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Get APSR Register\n  \\details Returns the content of the APSR Register.\n  \\return               APSR Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_APSR(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, apsr\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Get xPSR Register\n  \\details Returns the content of the xPSR Register.\n  \\return               xPSR Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_xPSR(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, xpsr\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Get Process Stack Pointer\n  \\details Returns the current value of the Process Stack Pointer (PSP).\n  \\return               PSP Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_PSP(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, psp\"  : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Process Stack Pointer (non-secure)\n  \\details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.\n  \\return               PSP Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, psp_ns\"  : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Process Stack Pointer\n  \\details Assigns the given value to the Process Stack Pointer (PSP).\n  \\param [in]    topOfProcStack  Process Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)\n{\n  __ASM volatile (\"MSR psp, %0\" : : \"r\" (topOfProcStack) : );\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Process Stack Pointer (non-secure)\n  \\details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.\n  \\param [in]    topOfProcStack  Process Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)\n{\n  __ASM volatile (\"MSR psp_ns, %0\" : : \"r\" (topOfProcStack) : );\n}\n#endif\n\n\n/**\n  \\brief   Get Main Stack Pointer\n  \\details Returns the current value of the Main Stack Pointer (MSP).\n  \\return               MSP Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_MSP(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, msp\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Main Stack Pointer (non-secure)\n  \\details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.\n  \\return               MSP Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, msp_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Main Stack Pointer\n  \\details Assigns the given value to the Main Stack Pointer (MSP).\n  \\param [in]    topOfMainStack  Main Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)\n{\n  __ASM volatile (\"MSR msp, %0\" : : \"r\" (topOfMainStack) : );\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Main Stack Pointer (non-secure)\n  \\details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.\n  \\param [in]    topOfMainStack  Main Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)\n{\n  __ASM volatile (\"MSR msp_ns, %0\" : : \"r\" (topOfMainStack) : );\n}\n#endif\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Stack Pointer (non-secure)\n  \\details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.\n  \\return               SP Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, sp_ns\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Set Stack Pointer (non-secure)\n  \\details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.\n  \\param [in]    topOfStack  Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)\n{\n  __ASM volatile (\"MSR sp_ns, %0\" : : \"r\" (topOfStack) : );\n}\n#endif\n\n\n/**\n  \\brief   Get Priority Mask\n  \\details Returns the current state of the priority mask bit from the Priority Mask Register.\n  \\return               Priority Mask value\n */\n__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, primask\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Priority Mask (non-secure)\n  \\details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.\n  \\return               Priority Mask value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, primask_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Priority Mask\n  \\details Assigns the given value to the Priority Mask Register.\n  \\param [in]    priMask  Priority Mask\n */\n__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)\n{\n  __ASM volatile (\"MSR primask, %0\" : : \"r\" (priMask) : \"memory\");\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Priority Mask (non-secure)\n  \\details Assigns the given value to the non-secure Priority Mask Register when in secure state.\n  \\param [in]    priMask  Priority Mask\n */\n__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)\n{\n  __ASM volatile (\"MSR primask_ns, %0\" : : \"r\" (priMask) : \"memory\");\n}\n#endif\n\n\n#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )\n/**\n  \\brief   Enable FIQ\n  \\details Enables FIQ interrupts by clearing the F-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n#define __enable_fault_irq                __enable_fiq   /* see arm_compat.h */\n\n\n/**\n  \\brief   Disable FIQ\n  \\details Disables FIQ interrupts by setting the F-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n#define __disable_fault_irq               __disable_fiq   /* see arm_compat.h */\n\n\n/**\n  \\brief   Get Base Priority\n  \\details Returns the current value of the Base Priority register.\n  \\return               Base Priority register value\n */\n__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, basepri\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Base Priority (non-secure)\n  \\details Returns the current value of the non-secure Base Priority register when in secure state.\n  \\return               Base Priority register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, basepri_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Base Priority\n  \\details Assigns the given value to the Base Priority register.\n  \\param [in]    basePri  Base Priority value to set\n */\n__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)\n{\n  __ASM volatile (\"MSR basepri, %0\" : : \"r\" (basePri) : \"memory\");\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Base Priority (non-secure)\n  \\details Assigns the given value to the non-secure Base Priority register when in secure state.\n  \\param [in]    basePri  Base Priority value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)\n{\n  __ASM volatile (\"MSR basepri_ns, %0\" : : \"r\" (basePri) : \"memory\");\n}\n#endif\n\n\n/**\n  \\brief   Set Base Priority with condition\n  \\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\n           or the new value increases the BASEPRI priority level.\n  \\param [in]    basePri  Base Priority value to set\n */\n__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)\n{\n  __ASM volatile (\"MSR basepri_max, %0\" : : \"r\" (basePri) : \"memory\");\n}\n\n\n/**\n  \\brief   Get Fault Mask\n  \\details Returns the current value of the Fault Mask register.\n  \\return               Fault Mask register value\n */\n__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, faultmask\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Fault Mask (non-secure)\n  \\details Returns the current value of the non-secure Fault Mask register when in secure state.\n  \\return               Fault Mask register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, faultmask_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Fault Mask\n  \\details Assigns the given value to the Fault Mask register.\n  \\param [in]    faultMask  Fault Mask value to set\n */\n__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)\n{\n  __ASM volatile (\"MSR faultmask, %0\" : : \"r\" (faultMask) : \"memory\");\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Fault Mask (non-secure)\n  \\details Assigns the given value to the non-secure Fault Mask register when in secure state.\n  \\param [in]    faultMask  Fault Mask value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)\n{\n  __ASM volatile (\"MSR faultmask_ns, %0\" : : \"r\" (faultMask) : \"memory\");\n}\n#endif\n\n#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */\n\n\n#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\n\n/**\n  \\brief   Get Process Stack Pointer Limit\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always in non-secure\n  mode.\n\n  \\details Returns the current value of the Process Stack Pointer Limit (PSPLIM).\n  \\return               PSPLIM Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n    // without main extensions, the non-secure PSPLIM is RAZ/WI\n  return 0U;\n#else\n  uint32_t result;\n  __ASM volatile (\"MRS %0, psplim\"  : \"=r\" (result) );\n  return result;\n#endif\n}\n\n#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Process Stack Pointer Limit (non-secure)\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always in non-secure\n  mode.\n\n  \\details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\n  \\return               PSPLIM Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\n  // without main extensions, the non-secure PSPLIM is RAZ/WI\n  return 0U;\n#else\n  uint32_t result;\n  __ASM volatile (\"MRS %0, psplim_ns\"  : \"=r\" (result) );\n  return result;\n#endif\n}\n#endif\n\n\n/**\n  \\brief   Set Process Stack Pointer Limit\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence the write is silently ignored in non-secure\n  mode.\n\n  \\details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).\n  \\param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set\n */\n__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n  // without main extensions, the non-secure PSPLIM is RAZ/WI\n  (void)ProcStackPtrLimit;\n#else\n  __ASM volatile (\"MSR psplim, %0\" : : \"r\" (ProcStackPtrLimit));\n#endif\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))\n/**\n  \\brief   Set Process Stack Pointer (non-secure)\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence the write is silently ignored in non-secure\n  mode.\n\n  \\details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\n  \\param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\n  // without main extensions, the non-secure PSPLIM is RAZ/WI\n  (void)ProcStackPtrLimit;\n#else\n  __ASM volatile (\"MSR psplim_ns, %0\\n\" : : \"r\" (ProcStackPtrLimit));\n#endif\n}\n#endif\n\n\n/**\n  \\brief   Get Main Stack Pointer Limit\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always.\n\n  \\details Returns the current value of the Main Stack Pointer Limit (MSPLIM).\n  \\return               MSPLIM Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n  // without main extensions, the non-secure MSPLIM is RAZ/WI\n  return 0U;\n#else\n  uint32_t result;\n  __ASM volatile (\"MRS %0, msplim\" : \"=r\" (result) );\n  return result;\n#endif\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))\n/**\n  \\brief   Get Main Stack Pointer Limit (non-secure)\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always.\n\n  \\details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.\n  \\return               MSPLIM Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\n  // without main extensions, the non-secure MSPLIM is RAZ/WI\n  return 0U;\n#else\n  uint32_t result;\n  __ASM volatile (\"MRS %0, msplim_ns\" : \"=r\" (result) );\n  return result;\n#endif\n}\n#endif\n\n\n/**\n  \\brief   Set Main Stack Pointer Limit\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence the write is silently ignored.\n\n  \\details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).\n  \\param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set\n */\n__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n  // without main extensions, the non-secure MSPLIM is RAZ/WI\n  (void)MainStackPtrLimit;\n#else\n  __ASM volatile (\"MSR msplim, %0\" : : \"r\" (MainStackPtrLimit));\n#endif\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))\n/**\n  \\brief   Set Main Stack Pointer Limit (non-secure)\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence the write is silently ignored.\n\n  \\details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.\n  \\param [in]    MainStackPtrLimit  Main Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\n  // without main extensions, the non-secure MSPLIM is RAZ/WI\n  (void)MainStackPtrLimit;\n#else\n  __ASM volatile (\"MSR msplim_ns, %0\" : : \"r\" (MainStackPtrLimit));\n#endif\n}\n#endif\n\n#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */\n\n/**\n  \\brief   Get FPSCR\n  \\details Returns the current value of the Floating Point Status/Control register.\n  \\return               Floating Point Status/Control register value\n */\n#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\\n     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )\n#define __get_FPSCR      (uint32_t)__builtin_arm_get_fpscr\n#else\n#define __get_FPSCR()      ((uint32_t)0U)\n#endif\n\n/**\n  \\brief   Set FPSCR\n  \\details Assigns the given value to the Floating Point Status/Control register.\n  \\param [in]    fpscr  Floating Point Status/Control value to set\n */\n#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\\n     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )\n#define __set_FPSCR      __builtin_arm_set_fpscr\n#else\n#define __set_FPSCR(x)      ((void)(x))\n#endif\n\n\n/*@} end of CMSIS_Core_RegAccFunctions */\n\n\n/* ##########################  Core Instruction Access  ######################### */\n/** \\defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\n  Access to dedicated instructions\n  @{\n*/\n\n/* Define macros for porting to both thumb1 and thumb2.\n * For thumb1, use low register (r0-r7), specified by constraint \"l\"\n * Otherwise, use general registers, specified by constraint \"r\" */\n#if defined (__thumb__) && !defined (__thumb2__)\n#define __CMSIS_GCC_OUT_REG(r) \"=l\" (r)\n#define __CMSIS_GCC_RW_REG(r) \"+l\" (r)\n#define __CMSIS_GCC_USE_REG(r) \"l\" (r)\n#else\n#define __CMSIS_GCC_OUT_REG(r) \"=r\" (r)\n#define __CMSIS_GCC_RW_REG(r) \"+r\" (r)\n#define __CMSIS_GCC_USE_REG(r) \"r\" (r)\n#endif\n\n/**\n  \\brief   No Operation\n  \\details No Operation does nothing. This instruction can be used for code alignment purposes.\n */\n#define __NOP          __builtin_arm_nop\n\n/**\n  \\brief   Wait For Interrupt\n  \\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\n */\n#define __WFI          __builtin_arm_wfi\n\n\n/**\n  \\brief   Wait For Event\n  \\details Wait For Event is a hint instruction that permits the processor to enter\n           a low-power state until one of a number of events occurs.\n */\n#define __WFE          __builtin_arm_wfe\n\n\n/**\n  \\brief   Send Event\n  \\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\n */\n#define __SEV          __builtin_arm_sev\n\n\n/**\n  \\brief   Instruction Synchronization Barrier\n  \\details Instruction Synchronization Barrier flushes the pipeline in the processor,\n           so that all instructions following the ISB are fetched from cache or memory,\n           after the instruction has been completed.\n */\n#define __ISB()        __builtin_arm_isb(0xF)\n\n/**\n  \\brief   Data Synchronization Barrier\n  \\details Acts as a special kind of Data Memory Barrier.\n           It completes when all explicit memory accesses before this instruction complete.\n */\n#define __DSB()        __builtin_arm_dsb(0xF)\n\n\n/**\n  \\brief   Data Memory Barrier\n  \\details Ensures the apparent order of the explicit memory operations before\n           and after the instruction, without ensuring their completion.\n */\n#define __DMB()        __builtin_arm_dmb(0xF)\n\n\n/**\n  \\brief   Reverse byte order (32 bit)\n  \\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n#define __REV(value)   __builtin_bswap32(value)\n\n\n/**\n  \\brief   Reverse byte order (16 bit)\n  \\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n#define __REV16(value) __ROR(__REV(value), 16)\n\n\n/**\n  \\brief   Reverse byte order (16 bit)\n  \\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n#define __REVSH(value) (int16_t)__builtin_bswap16(value)\n\n\n/**\n  \\brief   Rotate Right in unsigned value (32 bit)\n  \\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\n  \\param [in]    op1  Value to rotate\n  \\param [in]    op2  Number of Bits to rotate\n  \\return               Rotated value\n */\n__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\n{\n  op2 %= 32U;\n  if (op2 == 0U)\n  {\n    return op1;\n  }\n  return (op1 >> op2) | (op1 << (32U - op2));\n}\n\n\n/**\n  \\brief   Breakpoint\n  \\details Causes the processor to enter Debug state.\n           Debug tools can use this to investigate system state when the instruction at a particular address is reached.\n  \\param [in]    value  is ignored by the processor.\n                 If required, a debugger can use it to store additional information about the breakpoint.\n */\n#define __BKPT(value)     __ASM volatile (\"bkpt \"#value)\n\n\n/**\n  \\brief   Reverse bit order of value\n  \\details Reverses the bit order of the given value.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n#define __RBIT            __builtin_arm_rbit\n\n/**\n  \\brief   Count leading zeros\n  \\details Counts the number of leading zeros of a data value.\n  \\param [in]  value  Value to count the leading zeros\n  \\return             number of leading zeros in value\n */\n__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)\n{\n  /* Even though __builtin_clz produces a CLZ instruction on ARM, formally\n     __builtin_clz(0) is undefined behaviour, so handle this case specially.\n     This guarantees ARM-compatible results if happening to compile on a non-ARM\n     target, and ensures the compiler doesn't decide to activate any\n     optimisations using the logic \"value was passed to __builtin_clz, so it\n     is non-zero\".\n     ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a\n     single CLZ instruction.\n   */\n  if (value == 0U)\n  {\n    return 32U;\n  }\n  return __builtin_clz(value);\n}\n\n\n#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\n/**\n  \\brief   LDR Exclusive (8 bit)\n  \\details Executes a exclusive LDR instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n#define __LDREXB        (uint8_t)__builtin_arm_ldrex\n\n\n/**\n  \\brief   LDR Exclusive (16 bit)\n  \\details Executes a exclusive LDR instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n#define __LDREXH        (uint16_t)__builtin_arm_ldrex\n\n\n/**\n  \\brief   LDR Exclusive (32 bit)\n  \\details Executes a exclusive LDR instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n#define __LDREXW        (uint32_t)__builtin_arm_ldrex\n\n\n/**\n  \\brief   STR Exclusive (8 bit)\n  \\details Executes a exclusive STR instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#define __STREXB        (uint32_t)__builtin_arm_strex\n\n\n/**\n  \\brief   STR Exclusive (16 bit)\n  \\details Executes a exclusive STR instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#define __STREXH        (uint32_t)__builtin_arm_strex\n\n\n/**\n  \\brief   STR Exclusive (32 bit)\n  \\details Executes a exclusive STR instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#define __STREXW        (uint32_t)__builtin_arm_strex\n\n\n/**\n  \\brief   Remove the exclusive lock\n  \\details Removes the exclusive lock which is created by LDREX.\n */\n#define __CLREX             __builtin_arm_clrex\n\n#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */\n\n\n#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )\n\n/**\n  \\brief   Signed Saturate\n  \\details Saturates a signed value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (1..32)\n  \\return             Saturated value\n */\n#define __SSAT             __builtin_arm_ssat\n\n\n/**\n  \\brief   Unsigned Saturate\n  \\details Saturates an unsigned value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (0..31)\n  \\return             Saturated value\n */\n#define __USAT             __builtin_arm_usat\n\n\n/**\n  \\brief   Rotate Right with Extend (32 bit)\n  \\details Moves each bit of a bitstring right by one bit.\n           The carry input is shifted in at the left end of the bitstring.\n  \\param [in]    value  Value to rotate\n  \\return               Rotated value\n */\n__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)\n{\n  uint32_t result;\n\n  __ASM volatile (\"rrx %0, %1\" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\n  return(result);\n}\n\n\n/**\n  \\brief   LDRT Unprivileged (8 bit)\n  \\details Executes a Unprivileged LDRT instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ldrbt %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n  return ((uint8_t) result);    /* Add explicit type cast here */\n}\n\n\n/**\n  \\brief   LDRT Unprivileged (16 bit)\n  \\details Executes a Unprivileged LDRT instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ldrht %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n  return ((uint16_t) result);    /* Add explicit type cast here */\n}\n\n\n/**\n  \\brief   LDRT Unprivileged (32 bit)\n  \\details Executes a Unprivileged LDRT instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ldrt %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n  return(result);\n}\n\n\n/**\n  \\brief   STRT Unprivileged (8 bit)\n  \\details Executes a Unprivileged STRT instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)\n{\n  __ASM volatile (\"strbt %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   STRT Unprivileged (16 bit)\n  \\details Executes a Unprivileged STRT instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)\n{\n  __ASM volatile (\"strht %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   STRT Unprivileged (32 bit)\n  \\details Executes a Unprivileged STRT instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)\n{\n  __ASM volatile (\"strt %1, %0\" : \"=Q\" (*ptr) : \"r\" (value) );\n}\n\n#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */\n\n/**\n  \\brief   Signed Saturate\n  \\details Saturates a signed value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (1..32)\n  \\return             Saturated value\n */\n__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)\n{\n  if ((sat >= 1U) && (sat <= 32U))\n  {\n    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);\n    const int32_t min = -1 - max ;\n    if (val > max)\n    {\n      return max;\n    }\n    else if (val < min)\n    {\n      return min;\n    }\n  }\n  return val;\n}\n\n/**\n  \\brief   Unsigned Saturate\n  \\details Saturates an unsigned value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (0..31)\n  \\return             Saturated value\n */\n__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)\n{\n  if (sat <= 31U)\n  {\n    const uint32_t max = ((1U << sat) - 1U);\n    if (val > (int32_t)max)\n    {\n      return max;\n    }\n    else if (val < 0)\n    {\n      return 0U;\n    }\n  }\n  return (uint32_t)val;\n}\n\n#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */\n\n\n#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\n/**\n  \\brief   Load-Acquire (8 bit)\n  \\details Executes a LDAB instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ldab %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n  return ((uint8_t) result);\n}\n\n\n/**\n  \\brief   Load-Acquire (16 bit)\n  \\details Executes a LDAH instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ldah %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n  return ((uint16_t) result);\n}\n\n\n/**\n  \\brief   Load-Acquire (32 bit)\n  \\details Executes a LDA instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)\n{\n  uint32_t result;\n\n  __ASM volatile (\"lda %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n  return(result);\n}\n\n\n/**\n  \\brief   Store-Release (8 bit)\n  \\details Executes a STLB instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)\n{\n  __ASM volatile (\"stlb %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   Store-Release (16 bit)\n  \\details Executes a STLH instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)\n{\n  __ASM volatile (\"stlh %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   Store-Release (32 bit)\n  \\details Executes a STL instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)\n{\n  __ASM volatile (\"stl %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   Load-Acquire Exclusive (8 bit)\n  \\details Executes a LDAB exclusive instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n#define     __LDAEXB                 (uint8_t)__builtin_arm_ldaex\n\n\n/**\n  \\brief   Load-Acquire Exclusive (16 bit)\n  \\details Executes a LDAH exclusive instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n#define     __LDAEXH                 (uint16_t)__builtin_arm_ldaex\n\n\n/**\n  \\brief   Load-Acquire Exclusive (32 bit)\n  \\details Executes a LDA exclusive instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n#define     __LDAEX                  (uint32_t)__builtin_arm_ldaex\n\n\n/**\n  \\brief   Store-Release Exclusive (8 bit)\n  \\details Executes a STLB exclusive instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#define     __STLEXB                 (uint32_t)__builtin_arm_stlex\n\n\n/**\n  \\brief   Store-Release Exclusive (16 bit)\n  \\details Executes a STLH exclusive instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#define     __STLEXH                 (uint32_t)__builtin_arm_stlex\n\n\n/**\n  \\brief   Store-Release Exclusive (32 bit)\n  \\details Executes a STL exclusive instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#define     __STLEX                  (uint32_t)__builtin_arm_stlex\n\n#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */\n\n/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\n\n\n/* ###################  Compiler specific Intrinsics  ########################### */\n/** \\defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\n  Access to dedicated SIMD instructions\n  @{\n*/\n\n#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))\n\n#define     __SADD8                 __builtin_arm_sadd8\n#define     __QADD8                 __builtin_arm_qadd8\n#define     __SHADD8                __builtin_arm_shadd8\n#define     __UADD8                 __builtin_arm_uadd8\n#define     __UQADD8                __builtin_arm_uqadd8\n#define     __UHADD8                __builtin_arm_uhadd8\n#define     __SSUB8                 __builtin_arm_ssub8\n#define     __QSUB8                 __builtin_arm_qsub8\n#define     __SHSUB8                __builtin_arm_shsub8\n#define     __USUB8                 __builtin_arm_usub8\n#define     __UQSUB8                __builtin_arm_uqsub8\n#define     __UHSUB8                __builtin_arm_uhsub8\n#define     __SADD16                __builtin_arm_sadd16\n#define     __QADD16                __builtin_arm_qadd16\n#define     __SHADD16               __builtin_arm_shadd16\n#define     __UADD16                __builtin_arm_uadd16\n#define     __UQADD16               __builtin_arm_uqadd16\n#define     __UHADD16               __builtin_arm_uhadd16\n#define     __SSUB16                __builtin_arm_ssub16\n#define     __QSUB16                __builtin_arm_qsub16\n#define     __SHSUB16               __builtin_arm_shsub16\n#define     __USUB16                __builtin_arm_usub16\n#define     __UQSUB16               __builtin_arm_uqsub16\n#define     __UHSUB16               __builtin_arm_uhsub16\n#define     __SASX                  __builtin_arm_sasx\n#define     __QASX                  __builtin_arm_qasx\n#define     __SHASX                 __builtin_arm_shasx\n#define     __UASX                  __builtin_arm_uasx\n#define     __UQASX                 __builtin_arm_uqasx\n#define     __UHASX                 __builtin_arm_uhasx\n#define     __SSAX                  __builtin_arm_ssax\n#define     __QSAX                  __builtin_arm_qsax\n#define     __SHSAX                 __builtin_arm_shsax\n#define     __USAX                  __builtin_arm_usax\n#define     __UQSAX                 __builtin_arm_uqsax\n#define     __UHSAX                 __builtin_arm_uhsax\n#define     __USAD8                 __builtin_arm_usad8\n#define     __USADA8                __builtin_arm_usada8\n#define     __SSAT16                __builtin_arm_ssat16\n#define     __USAT16                __builtin_arm_usat16\n#define     __UXTB16                __builtin_arm_uxtb16\n#define     __UXTAB16               __builtin_arm_uxtab16\n#define     __SXTB16                __builtin_arm_sxtb16\n#define     __SXTAB16               __builtin_arm_sxtab16\n#define     __SMUAD                 __builtin_arm_smuad\n#define     __SMUADX                __builtin_arm_smuadx\n#define     __SMLAD                 __builtin_arm_smlad\n#define     __SMLADX                __builtin_arm_smladx\n#define     __SMLALD                __builtin_arm_smlald\n#define     __SMLALDX               __builtin_arm_smlaldx\n#define     __SMUSD                 __builtin_arm_smusd\n#define     __SMUSDX                __builtin_arm_smusdx\n#define     __SMLSD                 __builtin_arm_smlsd\n#define     __SMLSDX                __builtin_arm_smlsdx\n#define     __SMLSLD                __builtin_arm_smlsld\n#define     __SMLSLDX               __builtin_arm_smlsldx\n#define     __SEL                   __builtin_arm_sel\n#define     __QADD                  __builtin_arm_qadd\n#define     __QSUB                  __builtin_arm_qsub\n\n#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \\\n                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )\n\n#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \\\n                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )\n\n__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)\n{\n  int32_t result;\n\n  __ASM volatile (\"smmla %0, %1, %2, %3\" : \"=r\" (result): \"r\"  (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n#endif /* (__ARM_FEATURE_DSP == 1) */\n/*@} end of group CMSIS_SIMD_intrinsics */\n\n\n#endif /* __CMSIS_ARMCLANG_H */\n"
  },
  {
    "path": "3rd_party/CMSIS/Include/cmsis_armclang_ltm.h",
    "content": "/**************************************************************************//**\n * @file     cmsis_armclang_ltm.h\n * @brief    CMSIS compiler armclang (Arm Compiler 6) header file\n * @version  V1.2.0\n * @date     08. May 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2018-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */\n\n#ifndef __CMSIS_ARMCLANG_H\n#define __CMSIS_ARMCLANG_H\n\n#pragma clang system_header   /* treat file as system include file */\n\n#ifndef __ARM_COMPAT_H\n#include <arm_compat.h>    /* Compatibility header for Arm Compiler 5 intrinsics */\n#endif\n\n/* CMSIS compiler specific defines */\n#ifndef   __ASM\n  #define __ASM                                  __asm\n#endif\n#ifndef   __INLINE\n  #define __INLINE                               __inline\n#endif\n#ifndef   __STATIC_INLINE\n  #define __STATIC_INLINE                        static __inline\n#endif\n#ifndef   __STATIC_FORCEINLINE\n  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static __inline\n#endif\n#ifndef   __NO_RETURN\n  #define __NO_RETURN                            __attribute__((__noreturn__))\n#endif\n#ifndef   __USED\n  #define __USED                                 __attribute__((used))\n#endif\n#ifndef   __WEAK\n  #define __WEAK                                 __attribute__((weak))\n#endif\n#ifndef   __PACKED\n  #define __PACKED                               __attribute__((packed, aligned(1)))\n#endif\n#ifndef   __PACKED_STRUCT\n  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))\n#endif\n#ifndef   __PACKED_UNION\n  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))\n#endif\n#ifndef   __UNALIGNED_UINT32        /* deprecated */\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wpacked\"\n/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */\n  struct __attribute__((packed)) T_UINT32 { uint32_t v; };\n  #pragma clang diagnostic pop\n  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)\n#endif\n#ifndef   __UNALIGNED_UINT16_WRITE\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wpacked\"\n/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */\n  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\n  #pragma clang diagnostic pop\n  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))\n#endif\n#ifndef   __UNALIGNED_UINT16_READ\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wpacked\"\n/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */\n  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\n  #pragma clang diagnostic pop\n  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)\n#endif\n#ifndef   __UNALIGNED_UINT32_WRITE\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wpacked\"\n/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */\n  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\n  #pragma clang diagnostic pop\n  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\n#endif\n#ifndef   __UNALIGNED_UINT32_READ\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wpacked\"\n/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */\n  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\n  #pragma clang diagnostic pop\n  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)\n#endif\n#ifndef   __ALIGNED\n  #define __ALIGNED(x)                           __attribute__((aligned(x)))\n#endif\n#ifndef   __RESTRICT\n  #define __RESTRICT                             __restrict\n#endif\n#ifndef   __COMPILER_BARRIER\n  #define __COMPILER_BARRIER()                   __ASM volatile(\"\":::\"memory\")\n#endif\n\n/* #########################  Startup and Lowlevel Init  ######################## */\n\n#ifndef __PROGRAM_START\n#define __PROGRAM_START           __main\n#endif\n\n#ifndef __INITIAL_SP\n#define __INITIAL_SP              Image$$ARM_LIB_STACK$$ZI$$Limit\n#endif\n\n#ifndef __STACK_LIMIT\n#define __STACK_LIMIT             Image$$ARM_LIB_STACK$$ZI$$Base\n#endif\n\n#ifndef __VECTOR_TABLE\n#define __VECTOR_TABLE            __Vectors\n#endif\n\n#ifndef __VECTOR_TABLE_ATTRIBUTE\n#define __VECTOR_TABLE_ATTRIBUTE  __attribute((used, section(\"RESET\")))\n#endif\n\n\n/* ###########################  Core Function Access  ########################### */\n/** \\ingroup  CMSIS_Core_FunctionInterface\n    \\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\n  @{\n */\n\n/**\n  \\brief   Enable IRQ Interrupts\n  \\details Enables IRQ interrupts by clearing the I-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n/* intrinsic void __enable_irq();  see arm_compat.h */\n\n\n/**\n  \\brief   Disable IRQ Interrupts\n  \\details Disables IRQ interrupts by setting the I-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n/* intrinsic void __disable_irq();  see arm_compat.h */\n\n\n/**\n  \\brief   Get Control Register\n  \\details Returns the content of the Control Register.\n  \\return               Control Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, control\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Control Register (non-secure)\n  \\details Returns the content of the non-secure Control Register when in secure mode.\n  \\return               non-secure Control Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, control_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Control Register\n  \\details Writes the given value to the Control Register.\n  \\param [in]    control  Control Register value to set\n */\n__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)\n{\n  __ASM volatile (\"MSR control, %0\" : : \"r\" (control) : \"memory\");\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Control Register (non-secure)\n  \\details Writes the given value to the non-secure Control Register when in secure state.\n  \\param [in]    control  Control Register value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)\n{\n  __ASM volatile (\"MSR control_ns, %0\" : : \"r\" (control) : \"memory\");\n}\n#endif\n\n\n/**\n  \\brief   Get IPSR Register\n  \\details Returns the content of the IPSR Register.\n  \\return               IPSR Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_IPSR(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, ipsr\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Get APSR Register\n  \\details Returns the content of the APSR Register.\n  \\return               APSR Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_APSR(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, apsr\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Get xPSR Register\n  \\details Returns the content of the xPSR Register.\n  \\return               xPSR Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_xPSR(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, xpsr\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Get Process Stack Pointer\n  \\details Returns the current value of the Process Stack Pointer (PSP).\n  \\return               PSP Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_PSP(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, psp\"  : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Process Stack Pointer (non-secure)\n  \\details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.\n  \\return               PSP Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, psp_ns\"  : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Process Stack Pointer\n  \\details Assigns the given value to the Process Stack Pointer (PSP).\n  \\param [in]    topOfProcStack  Process Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)\n{\n  __ASM volatile (\"MSR psp, %0\" : : \"r\" (topOfProcStack) : );\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Process Stack Pointer (non-secure)\n  \\details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.\n  \\param [in]    topOfProcStack  Process Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)\n{\n  __ASM volatile (\"MSR psp_ns, %0\" : : \"r\" (topOfProcStack) : );\n}\n#endif\n\n\n/**\n  \\brief   Get Main Stack Pointer\n  \\details Returns the current value of the Main Stack Pointer (MSP).\n  \\return               MSP Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_MSP(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, msp\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Main Stack Pointer (non-secure)\n  \\details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.\n  \\return               MSP Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, msp_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Main Stack Pointer\n  \\details Assigns the given value to the Main Stack Pointer (MSP).\n  \\param [in]    topOfMainStack  Main Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)\n{\n  __ASM volatile (\"MSR msp, %0\" : : \"r\" (topOfMainStack) : );\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Main Stack Pointer (non-secure)\n  \\details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.\n  \\param [in]    topOfMainStack  Main Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)\n{\n  __ASM volatile (\"MSR msp_ns, %0\" : : \"r\" (topOfMainStack) : );\n}\n#endif\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Stack Pointer (non-secure)\n  \\details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.\n  \\return               SP Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, sp_ns\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Set Stack Pointer (non-secure)\n  \\details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.\n  \\param [in]    topOfStack  Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)\n{\n  __ASM volatile (\"MSR sp_ns, %0\" : : \"r\" (topOfStack) : );\n}\n#endif\n\n\n/**\n  \\brief   Get Priority Mask\n  \\details Returns the current state of the priority mask bit from the Priority Mask Register.\n  \\return               Priority Mask value\n */\n__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, primask\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Priority Mask (non-secure)\n  \\details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.\n  \\return               Priority Mask value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, primask_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Priority Mask\n  \\details Assigns the given value to the Priority Mask Register.\n  \\param [in]    priMask  Priority Mask\n */\n__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)\n{\n  __ASM volatile (\"MSR primask, %0\" : : \"r\" (priMask) : \"memory\");\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Priority Mask (non-secure)\n  \\details Assigns the given value to the non-secure Priority Mask Register when in secure state.\n  \\param [in]    priMask  Priority Mask\n */\n__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)\n{\n  __ASM volatile (\"MSR primask_ns, %0\" : : \"r\" (priMask) : \"memory\");\n}\n#endif\n\n\n#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )\n/**\n  \\brief   Enable FIQ\n  \\details Enables FIQ interrupts by clearing the F-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n#define __enable_fault_irq                __enable_fiq   /* see arm_compat.h */\n\n\n/**\n  \\brief   Disable FIQ\n  \\details Disables FIQ interrupts by setting the F-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n#define __disable_fault_irq               __disable_fiq   /* see arm_compat.h */\n\n\n/**\n  \\brief   Get Base Priority\n  \\details Returns the current value of the Base Priority register.\n  \\return               Base Priority register value\n */\n__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, basepri\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Base Priority (non-secure)\n  \\details Returns the current value of the non-secure Base Priority register when in secure state.\n  \\return               Base Priority register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, basepri_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Base Priority\n  \\details Assigns the given value to the Base Priority register.\n  \\param [in]    basePri  Base Priority value to set\n */\n__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)\n{\n  __ASM volatile (\"MSR basepri, %0\" : : \"r\" (basePri) : \"memory\");\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Base Priority (non-secure)\n  \\details Assigns the given value to the non-secure Base Priority register when in secure state.\n  \\param [in]    basePri  Base Priority value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)\n{\n  __ASM volatile (\"MSR basepri_ns, %0\" : : \"r\" (basePri) : \"memory\");\n}\n#endif\n\n\n/**\n  \\brief   Set Base Priority with condition\n  \\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\n           or the new value increases the BASEPRI priority level.\n  \\param [in]    basePri  Base Priority value to set\n */\n__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)\n{\n  __ASM volatile (\"MSR basepri_max, %0\" : : \"r\" (basePri) : \"memory\");\n}\n\n\n/**\n  \\brief   Get Fault Mask\n  \\details Returns the current value of the Fault Mask register.\n  \\return               Fault Mask register value\n */\n__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, faultmask\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Fault Mask (non-secure)\n  \\details Returns the current value of the non-secure Fault Mask register when in secure state.\n  \\return               Fault Mask register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, faultmask_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Fault Mask\n  \\details Assigns the given value to the Fault Mask register.\n  \\param [in]    faultMask  Fault Mask value to set\n */\n__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)\n{\n  __ASM volatile (\"MSR faultmask, %0\" : : \"r\" (faultMask) : \"memory\");\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Fault Mask (non-secure)\n  \\details Assigns the given value to the non-secure Fault Mask register when in secure state.\n  \\param [in]    faultMask  Fault Mask value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)\n{\n  __ASM volatile (\"MSR faultmask_ns, %0\" : : \"r\" (faultMask) : \"memory\");\n}\n#endif\n\n#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */\n\n\n#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\n\n/**\n  \\brief   Get Process Stack Pointer Limit\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always in non-secure\n  mode.\n\n  \\details Returns the current value of the Process Stack Pointer Limit (PSPLIM).\n  \\return               PSPLIM Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n    // without main extensions, the non-secure PSPLIM is RAZ/WI\n  return 0U;\n#else\n  uint32_t result;\n  __ASM volatile (\"MRS %0, psplim\"  : \"=r\" (result) );\n  return result;\n#endif\n}\n\n#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Process Stack Pointer Limit (non-secure)\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always in non-secure\n  mode.\n\n  \\details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\n  \\return               PSPLIM Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\n  // without main extensions, the non-secure PSPLIM is RAZ/WI\n  return 0U;\n#else\n  uint32_t result;\n  __ASM volatile (\"MRS %0, psplim_ns\"  : \"=r\" (result) );\n  return result;\n#endif\n}\n#endif\n\n\n/**\n  \\brief   Set Process Stack Pointer Limit\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence the write is silently ignored in non-secure\n  mode.\n\n  \\details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).\n  \\param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set\n */\n__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n  // without main extensions, the non-secure PSPLIM is RAZ/WI\n  (void)ProcStackPtrLimit;\n#else\n  __ASM volatile (\"MSR psplim, %0\" : : \"r\" (ProcStackPtrLimit));\n#endif\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))\n/**\n  \\brief   Set Process Stack Pointer (non-secure)\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence the write is silently ignored in non-secure\n  mode.\n\n  \\details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\n  \\param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\n  // without main extensions, the non-secure PSPLIM is RAZ/WI\n  (void)ProcStackPtrLimit;\n#else\n  __ASM volatile (\"MSR psplim_ns, %0\\n\" : : \"r\" (ProcStackPtrLimit));\n#endif\n}\n#endif\n\n\n/**\n  \\brief   Get Main Stack Pointer Limit\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always.\n\n  \\details Returns the current value of the Main Stack Pointer Limit (MSPLIM).\n  \\return               MSPLIM Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n  // without main extensions, the non-secure MSPLIM is RAZ/WI\n  return 0U;\n#else\n  uint32_t result;\n  __ASM volatile (\"MRS %0, msplim\" : \"=r\" (result) );\n  return result;\n#endif\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))\n/**\n  \\brief   Get Main Stack Pointer Limit (non-secure)\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always.\n\n  \\details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.\n  \\return               MSPLIM Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\n  // without main extensions, the non-secure MSPLIM is RAZ/WI\n  return 0U;\n#else\n  uint32_t result;\n  __ASM volatile (\"MRS %0, msplim_ns\" : \"=r\" (result) );\n  return result;\n#endif\n}\n#endif\n\n\n/**\n  \\brief   Set Main Stack Pointer Limit\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence the write is silently ignored.\n\n  \\details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).\n  \\param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set\n */\n__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n  // without main extensions, the non-secure MSPLIM is RAZ/WI\n  (void)MainStackPtrLimit;\n#else\n  __ASM volatile (\"MSR msplim, %0\" : : \"r\" (MainStackPtrLimit));\n#endif\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))\n/**\n  \\brief   Set Main Stack Pointer Limit (non-secure)\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence the write is silently ignored.\n\n  \\details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.\n  \\param [in]    MainStackPtrLimit  Main Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\n  // without main extensions, the non-secure MSPLIM is RAZ/WI\n  (void)MainStackPtrLimit;\n#else\n  __ASM volatile (\"MSR msplim_ns, %0\" : : \"r\" (MainStackPtrLimit));\n#endif\n}\n#endif\n\n#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */\n\n/**\n  \\brief   Get FPSCR\n  \\details Returns the current value of the Floating Point Status/Control register.\n  \\return               Floating Point Status/Control register value\n */\n#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\\n     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )\n#define __get_FPSCR      (uint32_t)__builtin_arm_get_fpscr\n#else\n#define __get_FPSCR()      ((uint32_t)0U)\n#endif\n\n/**\n  \\brief   Set FPSCR\n  \\details Assigns the given value to the Floating Point Status/Control register.\n  \\param [in]    fpscr  Floating Point Status/Control value to set\n */\n#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\\n     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )\n#define __set_FPSCR      __builtin_arm_set_fpscr\n#else\n#define __set_FPSCR(x)      ((void)(x))\n#endif\n\n\n/*@} end of CMSIS_Core_RegAccFunctions */\n\n\n/* ##########################  Core Instruction Access  ######################### */\n/** \\defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\n  Access to dedicated instructions\n  @{\n*/\n\n/* Define macros for porting to both thumb1 and thumb2.\n * For thumb1, use low register (r0-r7), specified by constraint \"l\"\n * Otherwise, use general registers, specified by constraint \"r\" */\n#if defined (__thumb__) && !defined (__thumb2__)\n#define __CMSIS_GCC_OUT_REG(r) \"=l\" (r)\n#define __CMSIS_GCC_USE_REG(r) \"l\" (r)\n#else\n#define __CMSIS_GCC_OUT_REG(r) \"=r\" (r)\n#define __CMSIS_GCC_USE_REG(r) \"r\" (r)\n#endif\n\n/**\n  \\brief   No Operation\n  \\details No Operation does nothing. This instruction can be used for code alignment purposes.\n */\n#define __NOP          __builtin_arm_nop\n\n/**\n  \\brief   Wait For Interrupt\n  \\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\n */\n#define __WFI          __builtin_arm_wfi\n\n\n/**\n  \\brief   Wait For Event\n  \\details Wait For Event is a hint instruction that permits the processor to enter\n           a low-power state until one of a number of events occurs.\n */\n#define __WFE          __builtin_arm_wfe\n\n\n/**\n  \\brief   Send Event\n  \\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\n */\n#define __SEV          __builtin_arm_sev\n\n\n/**\n  \\brief   Instruction Synchronization Barrier\n  \\details Instruction Synchronization Barrier flushes the pipeline in the processor,\n           so that all instructions following the ISB are fetched from cache or memory,\n           after the instruction has been completed.\n */\n#define __ISB()        __builtin_arm_isb(0xF)\n\n/**\n  \\brief   Data Synchronization Barrier\n  \\details Acts as a special kind of Data Memory Barrier.\n           It completes when all explicit memory accesses before this instruction complete.\n */\n#define __DSB()        __builtin_arm_dsb(0xF)\n\n\n/**\n  \\brief   Data Memory Barrier\n  \\details Ensures the apparent order of the explicit memory operations before\n           and after the instruction, without ensuring their completion.\n */\n#define __DMB()        __builtin_arm_dmb(0xF)\n\n\n/**\n  \\brief   Reverse byte order (32 bit)\n  \\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n#define __REV(value)   __builtin_bswap32(value)\n\n\n/**\n  \\brief   Reverse byte order (16 bit)\n  \\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n#define __REV16(value) __ROR(__REV(value), 16)\n\n\n/**\n  \\brief   Reverse byte order (16 bit)\n  \\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n#define __REVSH(value) (int16_t)__builtin_bswap16(value)\n\n\n/**\n  \\brief   Rotate Right in unsigned value (32 bit)\n  \\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\n  \\param [in]    op1  Value to rotate\n  \\param [in]    op2  Number of Bits to rotate\n  \\return               Rotated value\n */\n__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\n{\n  op2 %= 32U;\n  if (op2 == 0U)\n  {\n    return op1;\n  }\n  return (op1 >> op2) | (op1 << (32U - op2));\n}\n\n\n/**\n  \\brief   Breakpoint\n  \\details Causes the processor to enter Debug state.\n           Debug tools can use this to investigate system state when the instruction at a particular address is reached.\n  \\param [in]    value  is ignored by the processor.\n                 If required, a debugger can use it to store additional information about the breakpoint.\n */\n#define __BKPT(value)     __ASM volatile (\"bkpt \"#value)\n\n\n/**\n  \\brief   Reverse bit order of value\n  \\details Reverses the bit order of the given value.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n#define __RBIT            __builtin_arm_rbit\n\n/**\n  \\brief   Count leading zeros\n  \\details Counts the number of leading zeros of a data value.\n  \\param [in]  value  Value to count the leading zeros\n  \\return             number of leading zeros in value\n */\n__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)\n{\n  /* Even though __builtin_clz produces a CLZ instruction on ARM, formally\n     __builtin_clz(0) is undefined behaviour, so handle this case specially.\n     This guarantees ARM-compatible results if happening to compile on a non-ARM\n     target, and ensures the compiler doesn't decide to activate any\n     optimisations using the logic \"value was passed to __builtin_clz, so it\n     is non-zero\".\n     ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a\n     single CLZ instruction.\n   */\n  if (value == 0U)\n  {\n    return 32U;\n  }\n  return __builtin_clz(value);\n}\n\n\n#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\n/**\n  \\brief   LDR Exclusive (8 bit)\n  \\details Executes a exclusive LDR instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n#define __LDREXB        (uint8_t)__builtin_arm_ldrex\n\n\n/**\n  \\brief   LDR Exclusive (16 bit)\n  \\details Executes a exclusive LDR instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n#define __LDREXH        (uint16_t)__builtin_arm_ldrex\n\n\n/**\n  \\brief   LDR Exclusive (32 bit)\n  \\details Executes a exclusive LDR instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n#define __LDREXW        (uint32_t)__builtin_arm_ldrex\n\n\n/**\n  \\brief   STR Exclusive (8 bit)\n  \\details Executes a exclusive STR instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#define __STREXB        (uint32_t)__builtin_arm_strex\n\n\n/**\n  \\brief   STR Exclusive (16 bit)\n  \\details Executes a exclusive STR instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#define __STREXH        (uint32_t)__builtin_arm_strex\n\n\n/**\n  \\brief   STR Exclusive (32 bit)\n  \\details Executes a exclusive STR instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#define __STREXW        (uint32_t)__builtin_arm_strex\n\n\n/**\n  \\brief   Remove the exclusive lock\n  \\details Removes the exclusive lock which is created by LDREX.\n */\n#define __CLREX             __builtin_arm_clrex\n\n#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */\n\n\n#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )\n\n/**\n  \\brief   Signed Saturate\n  \\details Saturates a signed value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (1..32)\n  \\return             Saturated value\n */\n#define __SSAT             __builtin_arm_ssat\n\n\n/**\n  \\brief   Unsigned Saturate\n  \\details Saturates an unsigned value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (0..31)\n  \\return             Saturated value\n */\n#define __USAT             __builtin_arm_usat\n\n\n/**\n  \\brief   Rotate Right with Extend (32 bit)\n  \\details Moves each bit of a bitstring right by one bit.\n           The carry input is shifted in at the left end of the bitstring.\n  \\param [in]    value  Value to rotate\n  \\return               Rotated value\n */\n__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)\n{\n  uint32_t result;\n\n  __ASM volatile (\"rrx %0, %1\" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\n  return(result);\n}\n\n\n/**\n  \\brief   LDRT Unprivileged (8 bit)\n  \\details Executes a Unprivileged LDRT instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ldrbt %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n  return ((uint8_t) result);    /* Add explicit type cast here */\n}\n\n\n/**\n  \\brief   LDRT Unprivileged (16 bit)\n  \\details Executes a Unprivileged LDRT instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ldrht %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n  return ((uint16_t) result);    /* Add explicit type cast here */\n}\n\n\n/**\n  \\brief   LDRT Unprivileged (32 bit)\n  \\details Executes a Unprivileged LDRT instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ldrt %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n  return(result);\n}\n\n\n/**\n  \\brief   STRT Unprivileged (8 bit)\n  \\details Executes a Unprivileged STRT instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)\n{\n  __ASM volatile (\"strbt %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   STRT Unprivileged (16 bit)\n  \\details Executes a Unprivileged STRT instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)\n{\n  __ASM volatile (\"strht %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   STRT Unprivileged (32 bit)\n  \\details Executes a Unprivileged STRT instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)\n{\n  __ASM volatile (\"strt %1, %0\" : \"=Q\" (*ptr) : \"r\" (value) );\n}\n\n#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */\n\n/**\n  \\brief   Signed Saturate\n  \\details Saturates a signed value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (1..32)\n  \\return             Saturated value\n */\n__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)\n{\n  if ((sat >= 1U) && (sat <= 32U))\n  {\n    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);\n    const int32_t min = -1 - max ;\n    if (val > max)\n    {\n      return max;\n    }\n    else if (val < min)\n    {\n      return min;\n    }\n  }\n  return val;\n}\n\n/**\n  \\brief   Unsigned Saturate\n  \\details Saturates an unsigned value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (0..31)\n  \\return             Saturated value\n */\n__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)\n{\n  if (sat <= 31U)\n  {\n    const uint32_t max = ((1U << sat) - 1U);\n    if (val > (int32_t)max)\n    {\n      return max;\n    }\n    else if (val < 0)\n    {\n      return 0U;\n    }\n  }\n  return (uint32_t)val;\n}\n\n#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */\n\n\n#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\n/**\n  \\brief   Load-Acquire (8 bit)\n  \\details Executes a LDAB instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ldab %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n  return ((uint8_t) result);\n}\n\n\n/**\n  \\brief   Load-Acquire (16 bit)\n  \\details Executes a LDAH instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ldah %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n  return ((uint16_t) result);\n}\n\n\n/**\n  \\brief   Load-Acquire (32 bit)\n  \\details Executes a LDA instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)\n{\n  uint32_t result;\n\n  __ASM volatile (\"lda %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n  return(result);\n}\n\n\n/**\n  \\brief   Store-Release (8 bit)\n  \\details Executes a STLB instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)\n{\n  __ASM volatile (\"stlb %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   Store-Release (16 bit)\n  \\details Executes a STLH instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)\n{\n  __ASM volatile (\"stlh %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   Store-Release (32 bit)\n  \\details Executes a STL instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)\n{\n  __ASM volatile (\"stl %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   Load-Acquire Exclusive (8 bit)\n  \\details Executes a LDAB exclusive instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n#define     __LDAEXB                 (uint8_t)__builtin_arm_ldaex\n\n\n/**\n  \\brief   Load-Acquire Exclusive (16 bit)\n  \\details Executes a LDAH exclusive instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n#define     __LDAEXH                 (uint16_t)__builtin_arm_ldaex\n\n\n/**\n  \\brief   Load-Acquire Exclusive (32 bit)\n  \\details Executes a LDA exclusive instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n#define     __LDAEX                  (uint32_t)__builtin_arm_ldaex\n\n\n/**\n  \\brief   Store-Release Exclusive (8 bit)\n  \\details Executes a STLB exclusive instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#define     __STLEXB                 (uint32_t)__builtin_arm_stlex\n\n\n/**\n  \\brief   Store-Release Exclusive (16 bit)\n  \\details Executes a STLH exclusive instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#define     __STLEXH                 (uint32_t)__builtin_arm_stlex\n\n\n/**\n  \\brief   Store-Release Exclusive (32 bit)\n  \\details Executes a STL exclusive instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#define     __STLEX                  (uint32_t)__builtin_arm_stlex\n\n#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */\n\n/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\n\n\n/* ###################  Compiler specific Intrinsics  ########################### */\n/** \\defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\n  Access to dedicated SIMD instructions\n  @{\n*/\n\n#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))\n\n__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n\n__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ssub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n\n__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ssub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ssax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usad8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usada8 %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n#define __SSAT16(ARG1,ARG2) \\\n({                          \\\n  int32_t __RES, __ARG1 = (ARG1); \\\n  __ASM (\"ssat16 %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) ); \\\n  __RES; \\\n })\n\n#define __USAT16(ARG1,ARG2) \\\n({                          \\\n  uint32_t __RES, __ARG1 = (ARG1); \\\n  __ASM (\"usat16 %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) ); \\\n  __RES; \\\n })\n\n__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uxtb16 %0, %1\" : \"=r\" (result) : \"r\" (op1));\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uxtab16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sxtb16 %0, %1\" : \"=r\" (result) : \"r\" (op1));\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sxtab16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smuad %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smuadx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smlad %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smladx %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)\n{\n  union llreg_u{\n    uint32_t w32[2];\n    uint64_t w64;\n  } llr;\n  llr.w64 = acc;\n\n#ifndef __ARMEB__   /* Little endian */\n  __ASM volatile (\"smlald %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\n#else               /* Big endian */\n  __ASM volatile (\"smlald %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\n#endif\n\n  return(llr.w64);\n}\n\n__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)\n{\n  union llreg_u{\n    uint32_t w32[2];\n    uint64_t w64;\n  } llr;\n  llr.w64 = acc;\n\n#ifndef __ARMEB__   /* Little endian */\n  __ASM volatile (\"smlaldx %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\n#else               /* Big endian */\n  __ASM volatile (\"smlaldx %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\n#endif\n\n  return(llr.w64);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smusd %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smusdx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smlsd %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smlsdx %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)\n{\n  union llreg_u{\n    uint32_t w32[2];\n    uint64_t w64;\n  } llr;\n  llr.w64 = acc;\n\n#ifndef __ARMEB__   /* Little endian */\n  __ASM volatile (\"smlsld %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\n#else               /* Big endian */\n  __ASM volatile (\"smlsld %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\n#endif\n\n  return(llr.w64);\n}\n\n__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)\n{\n  union llreg_u{\n    uint32_t w32[2];\n    uint64_t w64;\n  } llr;\n  llr.w64 = acc;\n\n#ifndef __ARMEB__   /* Little endian */\n  __ASM volatile (\"smlsldx %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\n#else               /* Big endian */\n  __ASM volatile (\"smlsldx %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\n#endif\n\n  return(llr.w64);\n}\n\n__STATIC_FORCEINLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sel %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE  int32_t __QADD( int32_t op1,  int32_t op2)\n{\n  int32_t result;\n\n  __ASM volatile (\"qadd %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)\n{\n  int32_t result;\n\n  __ASM volatile (\"qsub %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \\\n                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )\n\n#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \\\n                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )\n\n__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)\n{\n  int32_t result;\n\n  __ASM volatile (\"smmla %0, %1, %2, %3\" : \"=r\" (result): \"r\"  (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n#endif /* (__ARM_FEATURE_DSP == 1) */\n/*@} end of group CMSIS_SIMD_intrinsics */\n\n\n#endif /* __CMSIS_ARMCLANG_H */\n"
  },
  {
    "path": "3rd_party/CMSIS/Include/cmsis_ccs.h",
    "content": "//*****************************************************************************\n//\n// Copyright (C) 2012 - 2017 Texas Instruments Incorporated - http://www.ti.com/\n//\n// Redistribution and use in source and binary forms, with or without\n// modification, are permitted provided that the following conditions\n// are met:\n//\n//  Redistributions of source code must retain the above copyright\n//  notice, this list of conditions and the following disclaimer.\n//\n//  Redistributions in binary form must reproduce the above copyright\n//  notice, this list of conditions and the following disclaimer in the\n//  documentation and/or other materials provided with the\n//  distribution.\n//\n//  Neither the name of Texas Instruments Incorporated nor the names of\n//  its contributors may be used to endorse or promote products derived\n//  from this software without specific prior written permission.\n//\n// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n// \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n//\n// MSP432 Family CMSIS Definitions\n//\n//****************************************************************************\n\n#ifndef CMSIS_CCS_H_\n#define CMSIS_CCS_H_\n\n//*****************************************************************************\n// CMSIS-compatible instruction calls\n//*****************************************************************************\n\n//\n//     v5e, v6, Cortex-M3, Cortex-M4, Cortex-R4, and Cortex-A8 compiler intrinsics\n//\n#define __CLZ       _norm\n#define __SXTB      _sxtb\n#define __SXTH      _sxth\n#define __UXTB      _uxtb\n#define __UXTH      _uxth\n\n//  CCS supports intrinsics to take advantage of the shift operand left/right\n//      before saturation extension of SSAT, but CMSIS does not take advantage\n//      of those, so tell the compiler to use a sat & shift left with a shift\n//      value of 0 whenever it encounters an SSAT\n#define __SSAT(VAL, BITPOS) \\\n    _ssatl(VAL , 0, BITPOS)\n\n//\n//  Only define M4 based intrinsics if we're not using an M4\n//\n#if defined (__TI_TMS470_V7M4__)\n\n//\n//  Add definitions for enable and disable interrupts\n//\n#if defined (__TI_COMPILER_VERSION__)\n\n#if (__TI_COMPILER_VERSION__ >= 5002000)\n\n#define __enable_irq _enable_IRQ\n#define __disable_irq _disable_IRQ\n\n// No Operation\n#define __NOP __nop\n// Data Synchronization Barrier\n#define __DSB _dsb\n\n#define __ISB _isb\n\n#define __WFI() __asm(\"  wfi\")\n\n#elif (__TI_COMPILER_VERSION__ >= 4009000)\n\n#define __enable_fault_irq _enable_interrupts\n#define __disable_fault_irq _disable_interrupts\n\n// No Operation\n__attribute__( ( always_inline ) ) static inline void __nop(void)\n{\n    __asm(\"  nop\");\n}\n\n__attribute__( ( always_inline ) ) static inline void __NOP(void)\n{\n    __asm(\"  nop\");\n}\n\n// Data Synchronization Barrier\n__attribute__( ( always_inline ) ) static inline void __DSB(void)\n{\n    __asm(\"  dsb\");\n}\n\n__attribute__( ( always_inline ) ) static inline void __ISB(void)\n{\n    __asm(\"  isb\");\n}\n\n__attribute__( ( always_inline ) ) static inline void __WFI(void)\n{\n    __asm(\"  wfi\");\n}\n\n#endif /*__TI_COMPILER_VERSION__ version*/\n\n#endif /*__TI_COMPILER_VERSION__*/\n\n//\n//    V5E, V6, Cortex-M4, Cortex-R4, and Cortex-A8 compiler intrinsics\n//\n#define __ROR __ror\n#define __SXTB16(src) _sxtb16((src),0)\n#define __QADD      _sadd\n#define __QDADD     _sdadd\n#define __QDSUB     _sdsub\n#define __SMLABB    _smlabb\n#define __SMLABT    _smlabt\n#define __SMLALBB   _smlalbb\n#define __SMLALBT   _smlalbt\n#define __SMLALTB   _smlaltb\n#define __SMLALTT   _smlaltt\n#define __SMLATB    _smlatb\n#define __SMLATT    _smlatt\n#define __SMLAWB    _smlawb\n#define __SMLAWT    _smlawt\n\n#define __SMULBB    _smulbb\n#define __SMULBT    _smulbt\n#define __SMULTB    _smultb\n#define __SMULTT    _smultt\n#define __SMULWB    _smulwb\n#define __SMULWT    _smulwt\n#define __QSUB      _ssub\n#define __SUBC      _subc\n\n//\n//    v6, Cortex-M4, Cortex-R4, and Cortex-A8 compiler intrinsics\n//\n#define __SHASX     _shaddsubx\n#define __SHSAX     _shsubaddx\n#define __PKHBT     _pkhbt\n#define __PKHTB     _pkhtb\n#define __QADD16    _qadd16\n#define __QADD8     _qadd8\n#define __QSUB16    _qsub16\n#define __QSUB8     _qsub8\n#define __QASX      _saddsubx\n#define __QSAX      _qsubaddx\n#define __SADD16    _sadd16\n#define __SADD8     _sadd8\n#define __SASX      _saddsubx\n#define __SEL       _sel\n#define __SHADD16   _shadd16\n#define __SHADD8    _shadd8\n#define __SHSUB16   _shsub16\n#define __SHSUB8    _shsub8\n#define __SMLAD     _smlad\n#define __SMLADX    _smladx\n#define __SMLALD(src1, src2, accumulator) _smlald(accumulator, src1, src2)\n#define __SMLALDX   _smlaldx\n#define __SMLSD     _smlsd\n#define __SMLSDX    _smlsdx\n#define __SMLSLD    _smlsld\n#define __SMLSLDX   _smlsldx\n#define __SMMLA     _smmla\n#define __SMMLAR    _smmlar\n#define __SMMLS     _smmls\n#define __SMMLSR    _smmlsr\n#define __SMMUL     _smmul\n#define __SMMULR    _smmulr\n#define __SMUAD     _smuad\n#define __SMUADX    _smuadx\n#define __SMUSD     _smusd\n#define __SMUSDX    _smusdx\n#define __SSAT16    _ssat16\n#define __SSUB16    _ssub16\n#define __SSUB8     _ssub8\n#define __SSAX      _ssubaddx\n#define __SXTAB     _sxtab\n#define __SXTAB16   _sxtab16\n#define __SXTAH     _sxtah\n#define __UMAAL     _umaal\n#define __UADD16    _uadd16\n#define __UADD8     _uadd8\n#define __UHADD16   _uhadd16\n#define __UHADD8    _uhadd8\n#define __UASX      _uaddsubx\n#define __UHSUB16   _uhsub16\n#define __UHSUB8    _uhsub8\n#define __UQADD16   _uqadd16\n#define __UQADD8    _uqadd8\n#define __UQASX     _uqaddsubx\n#define __UQSUB16   _uqsub16\n#define __UQSUB8    _uqsub8\n#define __UQSAX     _uqsubaddx\n#define __USAD8     _usad8\n#define __USAT16    _usat16\n#define __USUB16    _usub16\n#define __USUB8     _usub8\n#define __USAX      _usubaddx\n#define __UXTAB     _uxtab\n#define __UXTAB16   _uxtab16\n#define __UXTAH     _uxtah\n#define __UXTB16    _uxtb16\n#endif /*__TI_TMS470_V7M4__*/\n\n#endif /*CMSIS_CCS_H_*/\n"
  },
  {
    "path": "3rd_party/CMSIS/Include/cmsis_compiler.h",
    "content": "/**************************************************************************//**\n * @file     cmsis_compiler.h\n * @brief    CMSIS compiler generic header file\n * @version  V5.1.0\n * @date     09. October 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef __CMSIS_COMPILER_H\n#define __CMSIS_COMPILER_H\n\n#include <stdint.h>\n\n/*\n * Arm Compiler 4/5\n */\n#if   defined ( __CC_ARM )\n  #include \"cmsis_armcc.h\"\n\n\n/*\n * Arm Compiler 6.6 LTM (armclang)\n */\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)\n  #include \"cmsis_armclang_ltm.h\"\n\n  /*\n * Arm Compiler above 6.10.1 (armclang)\n */\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)\n  #include \"cmsis_armclang.h\"\n\n\n/*\n * GNU Compiler\n */\n#elif defined ( __GNUC__ )\n  #include \"cmsis_gcc.h\"\n\n\n/*\n * IAR Compiler\n */\n#elif defined ( __ICCARM__ )\n  #include <cmsis_iccarm.h>\n\n\n/*\n * TI Arm Compiler\n */\n#elif defined ( __TI_ARM__ )\n  #include <cmsis_ccs.h>\n\n  #ifndef   __ASM\n    #define __ASM                                  __asm\n  #endif\n  #ifndef   __INLINE\n    #define __INLINE                               inline\n  #endif\n  #ifndef   __STATIC_INLINE\n    #define __STATIC_INLINE                        static inline\n  #endif\n  #ifndef   __STATIC_FORCEINLINE\n    #define __STATIC_FORCEINLINE                   __STATIC_INLINE\n  #endif\n  #ifndef   __NO_RETURN\n    #define __NO_RETURN                            __attribute__((noreturn))\n  #endif\n  #ifndef   __USED\n    #define __USED                                 __attribute__((used))\n  #endif\n  #ifndef   __WEAK\n    #define __WEAK                                 __attribute__((weak))\n  #endif\n  #ifndef   __PACKED\n    #define __PACKED                               __attribute__((packed))\n  #endif\n  #ifndef   __PACKED_STRUCT\n    #define __PACKED_STRUCT                        struct __attribute__((packed))\n  #endif\n  #ifndef   __PACKED_UNION\n    #define __PACKED_UNION                         union __attribute__((packed))\n  #endif\n  #ifndef   __UNALIGNED_UINT32        /* deprecated */\n    struct __attribute__((packed)) T_UINT32 { uint32_t v; };\n    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)\n  #endif\n  #ifndef   __UNALIGNED_UINT16_WRITE\n    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\n    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))\n  #endif\n  #ifndef   __UNALIGNED_UINT16_READ\n    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\n    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)\n  #endif\n  #ifndef   __UNALIGNED_UINT32_WRITE\n    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\n    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\n  #endif\n  #ifndef   __UNALIGNED_UINT32_READ\n    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\n    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)\n  #endif\n  #ifndef   __ALIGNED\n    #define __ALIGNED(x)                           __attribute__((aligned(x)))\n  #endif\n  #ifndef   __RESTRICT\n    #define __RESTRICT                             __restrict\n  #endif\n  #ifndef   __COMPILER_BARRIER\n    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.\n    #define __COMPILER_BARRIER()                   (void)0\n  #endif\n\n\n/*\n * TASKING Compiler\n */\n#elif defined ( __TASKING__ )\n  /*\n   * The CMSIS functions have been implemented as intrinsics in the compiler.\n   * Please use \"carm -?i\" to get an up to date list of all intrinsics,\n   * Including the CMSIS ones.\n   */\n\n  #ifndef   __ASM\n    #define __ASM                                  __asm\n  #endif\n  #ifndef   __INLINE\n    #define __INLINE                               inline\n  #endif\n  #ifndef   __STATIC_INLINE\n    #define __STATIC_INLINE                        static inline\n  #endif\n  #ifndef   __STATIC_FORCEINLINE\n    #define __STATIC_FORCEINLINE                   __STATIC_INLINE\n  #endif\n  #ifndef   __NO_RETURN\n    #define __NO_RETURN                            __attribute__((noreturn))\n  #endif\n  #ifndef   __USED\n    #define __USED                                 __attribute__((used))\n  #endif\n  #ifndef   __WEAK\n    #define __WEAK                                 __attribute__((weak))\n  #endif\n  #ifndef   __PACKED\n    #define __PACKED                               __packed__\n  #endif\n  #ifndef   __PACKED_STRUCT\n    #define __PACKED_STRUCT                        struct __packed__\n  #endif\n  #ifndef   __PACKED_UNION\n    #define __PACKED_UNION                         union __packed__\n  #endif\n  #ifndef   __UNALIGNED_UINT32        /* deprecated */\n    struct __packed__ T_UINT32 { uint32_t v; };\n    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)\n  #endif\n  #ifndef   __UNALIGNED_UINT16_WRITE\n    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\n    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))\n  #endif\n  #ifndef   __UNALIGNED_UINT16_READ\n    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\n    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)\n  #endif\n  #ifndef   __UNALIGNED_UINT32_WRITE\n    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\n    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\n  #endif\n  #ifndef   __UNALIGNED_UINT32_READ\n    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\n    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)\n  #endif\n  #ifndef   __ALIGNED\n    #define __ALIGNED(x)              __align(x)\n  #endif\n  #ifndef   __RESTRICT\n    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.\n    #define __RESTRICT\n  #endif\n  #ifndef   __COMPILER_BARRIER\n    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.\n    #define __COMPILER_BARRIER()                   (void)0\n  #endif\n\n\n/*\n * COSMIC Compiler\n */\n#elif defined ( __CSMC__ )\n   #include <cmsis_csm.h>\n\n #ifndef   __ASM\n    #define __ASM                                  _asm\n  #endif\n  #ifndef   __INLINE\n    #define __INLINE                               inline\n  #endif\n  #ifndef   __STATIC_INLINE\n    #define __STATIC_INLINE                        static inline\n  #endif\n  #ifndef   __STATIC_FORCEINLINE\n    #define __STATIC_FORCEINLINE                   __STATIC_INLINE\n  #endif\n  #ifndef   __NO_RETURN\n    // NO RETURN is automatically detected hence no warning here\n    #define __NO_RETURN\n  #endif\n  #ifndef   __USED\n    #warning No compiler specific solution for __USED. __USED is ignored.\n    #define __USED\n  #endif\n  #ifndef   __WEAK\n    #define __WEAK                                 __weak\n  #endif\n  #ifndef   __PACKED\n    #define __PACKED                               @packed\n  #endif\n  #ifndef   __PACKED_STRUCT\n    #define __PACKED_STRUCT                        @packed struct\n  #endif\n  #ifndef   __PACKED_UNION\n    #define __PACKED_UNION                         @packed union\n  #endif\n  #ifndef   __UNALIGNED_UINT32        /* deprecated */\n    @packed struct T_UINT32 { uint32_t v; };\n    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)\n  #endif\n  #ifndef   __UNALIGNED_UINT16_WRITE\n    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\n    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))\n  #endif\n  #ifndef   __UNALIGNED_UINT16_READ\n    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\n    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)\n  #endif\n  #ifndef   __UNALIGNED_UINT32_WRITE\n    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\n    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\n  #endif\n  #ifndef   __UNALIGNED_UINT32_READ\n    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\n    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)\n  #endif\n  #ifndef   __ALIGNED\n    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.\n    #define __ALIGNED(x)\n  #endif\n  #ifndef   __RESTRICT\n    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.\n    #define __RESTRICT\n  #endif\n  #ifndef   __COMPILER_BARRIER\n    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.\n    #define __COMPILER_BARRIER()                   (void)0\n  #endif\n\n\n#else\n  #error Unknown compiler.\n#endif\n\n\n#endif /* __CMSIS_COMPILER_H */\n\n"
  },
  {
    "path": "3rd_party/CMSIS/Include/cmsis_gcc.h",
    "content": "/**************************************************************************//**\n * @file     cmsis_gcc.h\n * @brief    CMSIS compiler GCC header file\n * @version  V5.2.0\n * @date     08. May 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef __CMSIS_GCC_H\n#define __CMSIS_GCC_H\n\n/* ignore some GCC warnings */\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wsign-conversion\"\n#pragma GCC diagnostic ignored \"-Wconversion\"\n#pragma GCC diagnostic ignored \"-Wunused-parameter\"\n\n/* Fallback for __has_builtin */\n#ifndef __has_builtin\n  #define __has_builtin(x) (0)\n#endif\n\n/* CMSIS compiler specific defines */\n#ifndef   __ASM\n  #define __ASM                                  __asm\n#endif\n#ifndef   __INLINE\n  #define __INLINE                               inline\n#endif\n#ifndef   __STATIC_INLINE\n  #define __STATIC_INLINE                        static inline\n#endif\n#ifndef   __STATIC_FORCEINLINE\n  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline\n#endif\n#ifndef   __NO_RETURN\n  #define __NO_RETURN                            __attribute__((__noreturn__))\n#endif\n#ifndef   __USED\n  #define __USED                                 __attribute__((used))\n#endif\n#ifndef   __WEAK\n  #define __WEAK                                 __attribute__((weak))\n#endif\n#ifndef   __PACKED\n  #define __PACKED                               __attribute__((packed, aligned(1)))\n#endif\n#ifndef   __PACKED_STRUCT\n  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))\n#endif\n#ifndef   __PACKED_UNION\n  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))\n#endif\n#ifndef   __UNALIGNED_UINT32        /* deprecated */\n  #pragma GCC diagnostic push\n  #pragma GCC diagnostic ignored \"-Wpacked\"\n  #pragma GCC diagnostic ignored \"-Wattributes\"\n  struct __attribute__((packed)) T_UINT32 { uint32_t v; };\n  #pragma GCC diagnostic pop\n  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)\n#endif\n#ifndef   __UNALIGNED_UINT16_WRITE\n  #pragma GCC diagnostic push\n  #pragma GCC diagnostic ignored \"-Wpacked\"\n  #pragma GCC diagnostic ignored \"-Wattributes\"\n  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\n  #pragma GCC diagnostic pop\n  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))\n#endif\n#ifndef   __UNALIGNED_UINT16_READ\n  #pragma GCC diagnostic push\n  #pragma GCC diagnostic ignored \"-Wpacked\"\n  #pragma GCC diagnostic ignored \"-Wattributes\"\n  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\n  #pragma GCC diagnostic pop\n  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)\n#endif\n#ifndef   __UNALIGNED_UINT32_WRITE\n  #pragma GCC diagnostic push\n  #pragma GCC diagnostic ignored \"-Wpacked\"\n  #pragma GCC diagnostic ignored \"-Wattributes\"\n  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\n  #pragma GCC diagnostic pop\n  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\n#endif\n#ifndef   __UNALIGNED_UINT32_READ\n  #pragma GCC diagnostic push\n  #pragma GCC diagnostic ignored \"-Wpacked\"\n  #pragma GCC diagnostic ignored \"-Wattributes\"\n  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\n  #pragma GCC diagnostic pop\n  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)\n#endif\n#ifndef   __ALIGNED\n  #define __ALIGNED(x)                           __attribute__((aligned(x)))\n#endif\n#ifndef   __RESTRICT\n  #define __RESTRICT                             __restrict\n#endif\n#ifndef   __COMPILER_BARRIER\n  #define __COMPILER_BARRIER()                   __ASM volatile(\"\":::\"memory\")\n#endif\n\n/* #########################  Startup and Lowlevel Init  ######################## */\n\n#ifndef __PROGRAM_START\n\n/**\n  \\brief   Initializes data and bss sections\n  \\details This default implementations initialized all data and additional bss\n           sections relying on .copy.table and .zero.table specified properly\n           in the used linker script.\n\n */\n__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)\n{\n  extern void _start(void) __NO_RETURN;\n\n  typedef struct {\n    uint32_t const* src;\n    uint32_t* dest;\n    uint32_t  wlen;\n  } __copy_table_t;\n\n  typedef struct {\n    uint32_t* dest;\n    uint32_t  wlen;\n  } __zero_table_t;\n\n  extern const __copy_table_t __copy_table_start__;\n  extern const __copy_table_t __copy_table_end__;\n  extern const __zero_table_t __zero_table_start__;\n  extern const __zero_table_t __zero_table_end__;\n\n  for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) {\n    for(uint32_t i=0u; i<pTable->wlen; ++i) {\n      pTable->dest[i] = pTable->src[i];\n    }\n  }\n\n  for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) {\n    for(uint32_t i=0u; i<pTable->wlen; ++i) {\n      pTable->dest[i] = 0u;\n    }\n  }\n\n  _start();\n}\n\n#define __PROGRAM_START           __cmsis_start\n#endif\n\n#ifndef __INITIAL_SP\n#define __INITIAL_SP              __StackTop\n#endif\n\n#ifndef __STACK_LIMIT\n#define __STACK_LIMIT             __StackLimit\n#endif\n\n#ifndef __VECTOR_TABLE\n#define __VECTOR_TABLE            __Vectors\n#endif\n\n#ifndef __VECTOR_TABLE_ATTRIBUTE\n#define __VECTOR_TABLE_ATTRIBUTE  __attribute((used, section(\".vectors\")))\n#endif\n\n/* ###########################  Core Function Access  ########################### */\n/** \\ingroup  CMSIS_Core_FunctionInterface\n    \\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\n  @{\n */\n\n/**\n  \\brief   Enable IRQ Interrupts\n  \\details Enables IRQ interrupts by clearing the I-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n__STATIC_FORCEINLINE void __enable_irq(void)\n{\n  __ASM volatile (\"cpsie i\" : : : \"memory\");\n}\n\n\n/**\n  \\brief   Disable IRQ Interrupts\n  \\details Disables IRQ interrupts by setting the I-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n__STATIC_FORCEINLINE void __disable_irq(void)\n{\n  __ASM volatile (\"cpsid i\" : : : \"memory\");\n}\n\n\n/**\n  \\brief   Get Control Register\n  \\details Returns the content of the Control Register.\n  \\return               Control Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, control\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Control Register (non-secure)\n  \\details Returns the content of the non-secure Control Register when in secure mode.\n  \\return               non-secure Control Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, control_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Control Register\n  \\details Writes the given value to the Control Register.\n  \\param [in]    control  Control Register value to set\n */\n__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)\n{\n  __ASM volatile (\"MSR control, %0\" : : \"r\" (control) : \"memory\");\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Control Register (non-secure)\n  \\details Writes the given value to the non-secure Control Register when in secure state.\n  \\param [in]    control  Control Register value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)\n{\n  __ASM volatile (\"MSR control_ns, %0\" : : \"r\" (control) : \"memory\");\n}\n#endif\n\n\n/**\n  \\brief   Get IPSR Register\n  \\details Returns the content of the IPSR Register.\n  \\return               IPSR Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_IPSR(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, ipsr\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Get APSR Register\n  \\details Returns the content of the APSR Register.\n  \\return               APSR Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_APSR(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, apsr\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Get xPSR Register\n  \\details Returns the content of the xPSR Register.\n  \\return               xPSR Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_xPSR(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, xpsr\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Get Process Stack Pointer\n  \\details Returns the current value of the Process Stack Pointer (PSP).\n  \\return               PSP Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_PSP(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, psp\"  : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Process Stack Pointer (non-secure)\n  \\details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.\n  \\return               PSP Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, psp_ns\"  : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Process Stack Pointer\n  \\details Assigns the given value to the Process Stack Pointer (PSP).\n  \\param [in]    topOfProcStack  Process Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)\n{\n  __ASM volatile (\"MSR psp, %0\" : : \"r\" (topOfProcStack) : );\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Process Stack Pointer (non-secure)\n  \\details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.\n  \\param [in]    topOfProcStack  Process Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)\n{\n  __ASM volatile (\"MSR psp_ns, %0\" : : \"r\" (topOfProcStack) : );\n}\n#endif\n\n\n/**\n  \\brief   Get Main Stack Pointer\n  \\details Returns the current value of the Main Stack Pointer (MSP).\n  \\return               MSP Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_MSP(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, msp\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Main Stack Pointer (non-secure)\n  \\details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.\n  \\return               MSP Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, msp_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Main Stack Pointer\n  \\details Assigns the given value to the Main Stack Pointer (MSP).\n  \\param [in]    topOfMainStack  Main Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)\n{\n  __ASM volatile (\"MSR msp, %0\" : : \"r\" (topOfMainStack) : );\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Main Stack Pointer (non-secure)\n  \\details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.\n  \\param [in]    topOfMainStack  Main Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)\n{\n  __ASM volatile (\"MSR msp_ns, %0\" : : \"r\" (topOfMainStack) : );\n}\n#endif\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Stack Pointer (non-secure)\n  \\details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.\n  \\return               SP Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, sp_ns\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Set Stack Pointer (non-secure)\n  \\details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.\n  \\param [in]    topOfStack  Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)\n{\n  __ASM volatile (\"MSR sp_ns, %0\" : : \"r\" (topOfStack) : );\n}\n#endif\n\n\n/**\n  \\brief   Get Priority Mask\n  \\details Returns the current state of the priority mask bit from the Priority Mask Register.\n  \\return               Priority Mask value\n */\n__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, primask\" : \"=r\" (result) :: \"memory\");\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Priority Mask (non-secure)\n  \\details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.\n  \\return               Priority Mask value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, primask_ns\" : \"=r\" (result) :: \"memory\");\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Priority Mask\n  \\details Assigns the given value to the Priority Mask Register.\n  \\param [in]    priMask  Priority Mask\n */\n__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)\n{\n  __ASM volatile (\"MSR primask, %0\" : : \"r\" (priMask) : \"memory\");\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Priority Mask (non-secure)\n  \\details Assigns the given value to the non-secure Priority Mask Register when in secure state.\n  \\param [in]    priMask  Priority Mask\n */\n__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)\n{\n  __ASM volatile (\"MSR primask_ns, %0\" : : \"r\" (priMask) : \"memory\");\n}\n#endif\n\n\n#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )\n/**\n  \\brief   Enable FIQ\n  \\details Enables FIQ interrupts by clearing the F-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n__STATIC_FORCEINLINE void __enable_fault_irq(void)\n{\n  __ASM volatile (\"cpsie f\" : : : \"memory\");\n}\n\n\n/**\n  \\brief   Disable FIQ\n  \\details Disables FIQ interrupts by setting the F-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n__STATIC_FORCEINLINE void __disable_fault_irq(void)\n{\n  __ASM volatile (\"cpsid f\" : : : \"memory\");\n}\n\n\n/**\n  \\brief   Get Base Priority\n  \\details Returns the current value of the Base Priority register.\n  \\return               Base Priority register value\n */\n__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, basepri\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Base Priority (non-secure)\n  \\details Returns the current value of the non-secure Base Priority register when in secure state.\n  \\return               Base Priority register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, basepri_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Base Priority\n  \\details Assigns the given value to the Base Priority register.\n  \\param [in]    basePri  Base Priority value to set\n */\n__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)\n{\n  __ASM volatile (\"MSR basepri, %0\" : : \"r\" (basePri) : \"memory\");\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Base Priority (non-secure)\n  \\details Assigns the given value to the non-secure Base Priority register when in secure state.\n  \\param [in]    basePri  Base Priority value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)\n{\n  __ASM volatile (\"MSR basepri_ns, %0\" : : \"r\" (basePri) : \"memory\");\n}\n#endif\n\n\n/**\n  \\brief   Set Base Priority with condition\n  \\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\n           or the new value increases the BASEPRI priority level.\n  \\param [in]    basePri  Base Priority value to set\n */\n__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)\n{\n  __ASM volatile (\"MSR basepri_max, %0\" : : \"r\" (basePri) : \"memory\");\n}\n\n\n/**\n  \\brief   Get Fault Mask\n  \\details Returns the current value of the Fault Mask register.\n  \\return               Fault Mask register value\n */\n__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, faultmask\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Fault Mask (non-secure)\n  \\details Returns the current value of the non-secure Fault Mask register when in secure state.\n  \\return               Fault Mask register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, faultmask_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Fault Mask\n  \\details Assigns the given value to the Fault Mask register.\n  \\param [in]    faultMask  Fault Mask value to set\n */\n__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)\n{\n  __ASM volatile (\"MSR faultmask, %0\" : : \"r\" (faultMask) : \"memory\");\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Fault Mask (non-secure)\n  \\details Assigns the given value to the non-secure Fault Mask register when in secure state.\n  \\param [in]    faultMask  Fault Mask value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)\n{\n  __ASM volatile (\"MSR faultmask_ns, %0\" : : \"r\" (faultMask) : \"memory\");\n}\n#endif\n\n#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */\n\n\n#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\n\n/**\n  \\brief   Get Process Stack Pointer Limit\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always in non-secure\n  mode.\n\n  \\details Returns the current value of the Process Stack Pointer Limit (PSPLIM).\n  \\return               PSPLIM Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n    // without main extensions, the non-secure PSPLIM is RAZ/WI\n  return 0U;\n#else\n  uint32_t result;\n  __ASM volatile (\"MRS %0, psplim\"  : \"=r\" (result) );\n  return result;\n#endif\n}\n\n#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Process Stack Pointer Limit (non-secure)\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always.\n\n  \\details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\n  \\return               PSPLIM Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\n  // without main extensions, the non-secure PSPLIM is RAZ/WI\n  return 0U;\n#else\n  uint32_t result;\n  __ASM volatile (\"MRS %0, psplim_ns\"  : \"=r\" (result) );\n  return result;\n#endif\n}\n#endif\n\n\n/**\n  \\brief   Set Process Stack Pointer Limit\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence the write is silently ignored in non-secure\n  mode.\n\n  \\details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).\n  \\param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set\n */\n__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n  // without main extensions, the non-secure PSPLIM is RAZ/WI\n  (void)ProcStackPtrLimit;\n#else\n  __ASM volatile (\"MSR psplim, %0\" : : \"r\" (ProcStackPtrLimit));\n#endif\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))\n/**\n  \\brief   Set Process Stack Pointer (non-secure)\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence the write is silently ignored.\n\n  \\details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\n  \\param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\n  // without main extensions, the non-secure PSPLIM is RAZ/WI\n  (void)ProcStackPtrLimit;\n#else\n  __ASM volatile (\"MSR psplim_ns, %0\\n\" : : \"r\" (ProcStackPtrLimit));\n#endif\n}\n#endif\n\n\n/**\n  \\brief   Get Main Stack Pointer Limit\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always in non-secure\n  mode.\n\n  \\details Returns the current value of the Main Stack Pointer Limit (MSPLIM).\n  \\return               MSPLIM Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n  // without main extensions, the non-secure MSPLIM is RAZ/WI\n  return 0U;\n#else\n  uint32_t result;\n  __ASM volatile (\"MRS %0, msplim\" : \"=r\" (result) );\n  return result;\n#endif\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))\n/**\n  \\brief   Get Main Stack Pointer Limit (non-secure)\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always.\n\n  \\details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.\n  \\return               MSPLIM Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\n  // without main extensions, the non-secure MSPLIM is RAZ/WI\n  return 0U;\n#else\n  uint32_t result;\n  __ASM volatile (\"MRS %0, msplim_ns\" : \"=r\" (result) );\n  return result;\n#endif\n}\n#endif\n\n\n/**\n  \\brief   Set Main Stack Pointer Limit\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence the write is silently ignored in non-secure\n  mode.\n\n  \\details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).\n  \\param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set\n */\n__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n  // without main extensions, the non-secure MSPLIM is RAZ/WI\n  (void)MainStackPtrLimit;\n#else\n  __ASM volatile (\"MSR msplim, %0\" : : \"r\" (MainStackPtrLimit));\n#endif\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))\n/**\n  \\brief   Set Main Stack Pointer Limit (non-secure)\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence the write is silently ignored.\n\n  \\details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.\n  \\param [in]    MainStackPtrLimit  Main Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\n  // without main extensions, the non-secure MSPLIM is RAZ/WI\n  (void)MainStackPtrLimit;\n#else\n  __ASM volatile (\"MSR msplim_ns, %0\" : : \"r\" (MainStackPtrLimit));\n#endif\n}\n#endif\n\n#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */\n\n\n/**\n  \\brief   Get FPSCR\n  \\details Returns the current value of the Floating Point Status/Control register.\n  \\return               Floating Point Status/Control register value\n */\n__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)\n{\n#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\\n     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )\n#if __has_builtin(__builtin_arm_get_fpscr)\n// Re-enable using built-in when GCC has been fixed\n// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)\n  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */\n  return __builtin_arm_get_fpscr();\n#else\n  uint32_t result;\n\n  __ASM volatile (\"VMRS %0, fpscr\" : \"=r\" (result) );\n  return(result);\n#endif\n#else\n  return(0U);\n#endif\n}\n\n\n/**\n  \\brief   Set FPSCR\n  \\details Assigns the given value to the Floating Point Status/Control register.\n  \\param [in]    fpscr  Floating Point Status/Control value to set\n */\n__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)\n{\n#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\\n     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )\n#if __has_builtin(__builtin_arm_set_fpscr)\n// Re-enable using built-in when GCC has been fixed\n// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)\n  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */\n  __builtin_arm_set_fpscr(fpscr);\n#else\n  __ASM volatile (\"VMSR fpscr, %0\" : : \"r\" (fpscr) : \"vfpcc\", \"memory\");\n#endif\n#else\n  (void)fpscr;\n#endif\n}\n\n\n/*@} end of CMSIS_Core_RegAccFunctions */\n\n\n/* ##########################  Core Instruction Access  ######################### */\n/** \\defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\n  Access to dedicated instructions\n  @{\n*/\n\n/* Define macros for porting to both thumb1 and thumb2.\n * For thumb1, use low register (r0-r7), specified by constraint \"l\"\n * Otherwise, use general registers, specified by constraint \"r\" */\n#if defined (__thumb__) && !defined (__thumb2__)\n#define __CMSIS_GCC_OUT_REG(r) \"=l\" (r)\n#define __CMSIS_GCC_RW_REG(r) \"+l\" (r)\n#define __CMSIS_GCC_USE_REG(r) \"l\" (r)\n#else\n#define __CMSIS_GCC_OUT_REG(r) \"=r\" (r)\n#define __CMSIS_GCC_RW_REG(r) \"+r\" (r)\n#define __CMSIS_GCC_USE_REG(r) \"r\" (r)\n#endif\n\n/**\n  \\brief   No Operation\n  \\details No Operation does nothing. This instruction can be used for code alignment purposes.\n */\n#define __NOP()                             __ASM volatile (\"nop\")\n\n/**\n  \\brief   Wait For Interrupt\n  \\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\n */\n#define __WFI()                             __ASM volatile (\"wfi\")\n\n\n/**\n  \\brief   Wait For Event\n  \\details Wait For Event is a hint instruction that permits the processor to enter\n           a low-power state until one of a number of events occurs.\n */\n#define __WFE()                             __ASM volatile (\"wfe\")\n\n\n/**\n  \\brief   Send Event\n  \\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\n */\n#define __SEV()                             __ASM volatile (\"sev\")\n\n\n/**\n  \\brief   Instruction Synchronization Barrier\n  \\details Instruction Synchronization Barrier flushes the pipeline in the processor,\n           so that all instructions following the ISB are fetched from cache or memory,\n           after the instruction has been completed.\n */\n__STATIC_FORCEINLINE void __ISB(void)\n{\n  __ASM volatile (\"isb 0xF\":::\"memory\");\n}\n\n\n/**\n  \\brief   Data Synchronization Barrier\n  \\details Acts as a special kind of Data Memory Barrier.\n           It completes when all explicit memory accesses before this instruction complete.\n */\n__STATIC_FORCEINLINE void __DSB(void)\n{\n  __ASM volatile (\"dsb 0xF\":::\"memory\");\n}\n\n\n/**\n  \\brief   Data Memory Barrier\n  \\details Ensures the apparent order of the explicit memory operations before\n           and after the instruction, without ensuring their completion.\n */\n__STATIC_FORCEINLINE void __DMB(void)\n{\n  __ASM volatile (\"dmb 0xF\":::\"memory\");\n}\n\n\n/**\n  \\brief   Reverse byte order (32 bit)\n  \\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)\n{\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)\n  return __builtin_bswap32(value);\n#else\n  uint32_t result;\n\n  __ASM volatile (\"rev %0, %1\" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\n  return result;\n#endif\n}\n\n\n/**\n  \\brief   Reverse byte order (16 bit)\n  \\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)\n{\n  uint32_t result;\n\n  __ASM volatile (\"rev16 %0, %1\" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\n  return result;\n}\n\n\n/**\n  \\brief   Reverse byte order (16 bit)\n  \\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)\n{\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\n  return (int16_t)__builtin_bswap16(value);\n#else\n  int16_t result;\n\n  __ASM volatile (\"revsh %0, %1\" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\n  return result;\n#endif\n}\n\n\n/**\n  \\brief   Rotate Right in unsigned value (32 bit)\n  \\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\n  \\param [in]    op1  Value to rotate\n  \\param [in]    op2  Number of Bits to rotate\n  \\return               Rotated value\n */\n__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\n{\n  op2 %= 32U;\n  if (op2 == 0U)\n  {\n    return op1;\n  }\n  return (op1 >> op2) | (op1 << (32U - op2));\n}\n\n\n/**\n  \\brief   Breakpoint\n  \\details Causes the processor to enter Debug state.\n           Debug tools can use this to investigate system state when the instruction at a particular address is reached.\n  \\param [in]    value  is ignored by the processor.\n                 If required, a debugger can use it to store additional information about the breakpoint.\n */\n#define __BKPT(value)                       __ASM volatile (\"bkpt \"#value)\n\n\n/**\n  \\brief   Reverse bit order of value\n  \\details Reverses the bit order of the given value.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)\n{\n  uint32_t result;\n\n#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )\n   __ASM volatile (\"rbit %0, %1\" : \"=r\" (result) : \"r\" (value) );\n#else\n  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */\n\n  result = value;                      /* r will be reversed bits of v; first get LSB of v */\n  for (value >>= 1U; value != 0U; value >>= 1U)\n  {\n    result <<= 1U;\n    result |= value & 1U;\n    s--;\n  }\n  result <<= s;                        /* shift when v's highest bits are zero */\n#endif\n  return result;\n}\n\n\n/**\n  \\brief   Count leading zeros\n  \\details Counts the number of leading zeros of a data value.\n  \\param [in]  value  Value to count the leading zeros\n  \\return             number of leading zeros in value\n */\n__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)\n{\n  /* Even though __builtin_clz produces a CLZ instruction on ARM, formally\n     __builtin_clz(0) is undefined behaviour, so handle this case specially.\n     This guarantees ARM-compatible results if happening to compile on a non-ARM\n     target, and ensures the compiler doesn't decide to activate any\n     optimisations using the logic \"value was passed to __builtin_clz, so it\n     is non-zero\".\n     ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a\n     single CLZ instruction.\n   */\n  if (value == 0U)\n  {\n    return 32U;\n  }\n  return __builtin_clz(value);\n}\n\n\n#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\n/**\n  \\brief   LDR Exclusive (8 bit)\n  \\details Executes a exclusive LDR instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)\n{\n    uint32_t result;\n\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\n   __ASM volatile (\"ldrexb %0, %1\" : \"=r\" (result) : \"Q\" (*addr) );\n#else\n    /* Prior to GCC 4.8, \"Q\" will be expanded to [rx, #0] which is not\n       accepted by assembler. So has to use following less efficient pattern.\n    */\n   __ASM volatile (\"ldrexb %0, [%1]\" : \"=r\" (result) : \"r\" (addr) : \"memory\" );\n#endif\n   return ((uint8_t) result);    /* Add explicit type cast here */\n}\n\n\n/**\n  \\brief   LDR Exclusive (16 bit)\n  \\details Executes a exclusive LDR instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)\n{\n    uint32_t result;\n\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\n   __ASM volatile (\"ldrexh %0, %1\" : \"=r\" (result) : \"Q\" (*addr) );\n#else\n    /* Prior to GCC 4.8, \"Q\" will be expanded to [rx, #0] which is not\n       accepted by assembler. So has to use following less efficient pattern.\n    */\n   __ASM volatile (\"ldrexh %0, [%1]\" : \"=r\" (result) : \"r\" (addr) : \"memory\" );\n#endif\n   return ((uint16_t) result);    /* Add explicit type cast here */\n}\n\n\n/**\n  \\brief   LDR Exclusive (32 bit)\n  \\details Executes a exclusive LDR instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"ldrex %0, %1\" : \"=r\" (result) : \"Q\" (*addr) );\n   return(result);\n}\n\n\n/**\n  \\brief   STR Exclusive (8 bit)\n  \\details Executes a exclusive STR instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)\n{\n   uint32_t result;\n\n   __ASM volatile (\"strexb %0, %2, %1\" : \"=&r\" (result), \"=Q\" (*addr) : \"r\" ((uint32_t)value) );\n   return(result);\n}\n\n\n/**\n  \\brief   STR Exclusive (16 bit)\n  \\details Executes a exclusive STR instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)\n{\n   uint32_t result;\n\n   __ASM volatile (\"strexh %0, %2, %1\" : \"=&r\" (result), \"=Q\" (*addr) : \"r\" ((uint32_t)value) );\n   return(result);\n}\n\n\n/**\n  \\brief   STR Exclusive (32 bit)\n  \\details Executes a exclusive STR instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)\n{\n   uint32_t result;\n\n   __ASM volatile (\"strex %0, %2, %1\" : \"=&r\" (result), \"=Q\" (*addr) : \"r\" (value) );\n   return(result);\n}\n\n\n/**\n  \\brief   Remove the exclusive lock\n  \\details Removes the exclusive lock which is created by LDREX.\n */\n__STATIC_FORCEINLINE void __CLREX(void)\n{\n  __ASM volatile (\"clrex\" ::: \"memory\");\n}\n\n#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */\n\n\n#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )\n/**\n  \\brief   Signed Saturate\n  \\details Saturates a signed value.\n  \\param [in]  ARG1  Value to be saturated\n  \\param [in]  ARG2  Bit position to saturate to (1..32)\n  \\return             Saturated value\n */\n#define __SSAT(ARG1,ARG2) \\\n__extension__ \\\n({                          \\\n  int32_t __RES, __ARG1 = (ARG1); \\\n  __ASM (\"ssat %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) ); \\\n  __RES; \\\n })\n\n\n/**\n  \\brief   Unsigned Saturate\n  \\details Saturates an unsigned value.\n  \\param [in]  ARG1  Value to be saturated\n  \\param [in]  ARG2  Bit position to saturate to (0..31)\n  \\return             Saturated value\n */\n#define __USAT(ARG1,ARG2) \\\n __extension__ \\\n({                          \\\n  uint32_t __RES, __ARG1 = (ARG1); \\\n  __ASM (\"usat %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) ); \\\n  __RES; \\\n })\n\n\n/**\n  \\brief   Rotate Right with Extend (32 bit)\n  \\details Moves each bit of a bitstring right by one bit.\n           The carry input is shifted in at the left end of the bitstring.\n  \\param [in]    value  Value to rotate\n  \\return               Rotated value\n */\n__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)\n{\n  uint32_t result;\n\n  __ASM volatile (\"rrx %0, %1\" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\n  return(result);\n}\n\n\n/**\n  \\brief   LDRT Unprivileged (8 bit)\n  \\details Executes a Unprivileged LDRT instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)\n{\n    uint32_t result;\n\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\n   __ASM volatile (\"ldrbt %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n#else\n    /* Prior to GCC 4.8, \"Q\" will be expanded to [rx, #0] which is not\n       accepted by assembler. So has to use following less efficient pattern.\n    */\n   __ASM volatile (\"ldrbt %0, [%1]\" : \"=r\" (result) : \"r\" (ptr) : \"memory\" );\n#endif\n   return ((uint8_t) result);    /* Add explicit type cast here */\n}\n\n\n/**\n  \\brief   LDRT Unprivileged (16 bit)\n  \\details Executes a Unprivileged LDRT instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)\n{\n    uint32_t result;\n\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\n   __ASM volatile (\"ldrht %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n#else\n    /* Prior to GCC 4.8, \"Q\" will be expanded to [rx, #0] which is not\n       accepted by assembler. So has to use following less efficient pattern.\n    */\n   __ASM volatile (\"ldrht %0, [%1]\" : \"=r\" (result) : \"r\" (ptr) : \"memory\" );\n#endif\n   return ((uint16_t) result);    /* Add explicit type cast here */\n}\n\n\n/**\n  \\brief   LDRT Unprivileged (32 bit)\n  \\details Executes a Unprivileged LDRT instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"ldrt %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n   return(result);\n}\n\n\n/**\n  \\brief   STRT Unprivileged (8 bit)\n  \\details Executes a Unprivileged STRT instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)\n{\n   __ASM volatile (\"strbt %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   STRT Unprivileged (16 bit)\n  \\details Executes a Unprivileged STRT instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)\n{\n   __ASM volatile (\"strht %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   STRT Unprivileged (32 bit)\n  \\details Executes a Unprivileged STRT instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)\n{\n   __ASM volatile (\"strt %1, %0\" : \"=Q\" (*ptr) : \"r\" (value) );\n}\n\n#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */\n\n/**\n  \\brief   Signed Saturate\n  \\details Saturates a signed value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (1..32)\n  \\return             Saturated value\n */\n__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)\n{\n  if ((sat >= 1U) && (sat <= 32U))\n  {\n    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);\n    const int32_t min = -1 - max ;\n    if (val > max)\n    {\n      return max;\n    }\n    else if (val < min)\n    {\n      return min;\n    }\n  }\n  return val;\n}\n\n/**\n  \\brief   Unsigned Saturate\n  \\details Saturates an unsigned value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (0..31)\n  \\return             Saturated value\n */\n__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)\n{\n  if (sat <= 31U)\n  {\n    const uint32_t max = ((1U << sat) - 1U);\n    if (val > (int32_t)max)\n    {\n      return max;\n    }\n    else if (val < 0)\n    {\n      return 0U;\n    }\n  }\n  return (uint32_t)val;\n}\n\n#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */\n\n\n#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\n/**\n  \\brief   Load-Acquire (8 bit)\n  \\details Executes a LDAB instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"ldab %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n   return ((uint8_t) result);\n}\n\n\n/**\n  \\brief   Load-Acquire (16 bit)\n  \\details Executes a LDAH instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"ldah %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n   return ((uint16_t) result);\n}\n\n\n/**\n  \\brief   Load-Acquire (32 bit)\n  \\details Executes a LDA instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"lda %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n   return(result);\n}\n\n\n/**\n  \\brief   Store-Release (8 bit)\n  \\details Executes a STLB instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)\n{\n   __ASM volatile (\"stlb %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   Store-Release (16 bit)\n  \\details Executes a STLH instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)\n{\n   __ASM volatile (\"stlh %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   Store-Release (32 bit)\n  \\details Executes a STL instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)\n{\n   __ASM volatile (\"stl %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   Load-Acquire Exclusive (8 bit)\n  \\details Executes a LDAB exclusive instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"ldaexb %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n   return ((uint8_t) result);\n}\n\n\n/**\n  \\brief   Load-Acquire Exclusive (16 bit)\n  \\details Executes a LDAH exclusive instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"ldaexh %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n   return ((uint16_t) result);\n}\n\n\n/**\n  \\brief   Load-Acquire Exclusive (32 bit)\n  \\details Executes a LDA exclusive instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"ldaex %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n   return(result);\n}\n\n\n/**\n  \\brief   Store-Release Exclusive (8 bit)\n  \\details Executes a STLB exclusive instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)\n{\n   uint32_t result;\n\n   __ASM volatile (\"stlexb %0, %2, %1\" : \"=&r\" (result), \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n   return(result);\n}\n\n\n/**\n  \\brief   Store-Release Exclusive (16 bit)\n  \\details Executes a STLH exclusive instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)\n{\n   uint32_t result;\n\n   __ASM volatile (\"stlexh %0, %2, %1\" : \"=&r\" (result), \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n   return(result);\n}\n\n\n/**\n  \\brief   Store-Release Exclusive (32 bit)\n  \\details Executes a STL exclusive instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)\n{\n   uint32_t result;\n\n   __ASM volatile (\"stlex %0, %2, %1\" : \"=&r\" (result), \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n   return(result);\n}\n\n#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */\n\n/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\n\n\n/* ###################  Compiler specific Intrinsics  ########################### */\n/** \\defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\n  Access to dedicated SIMD instructions\n  @{\n*/\n\n#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))\n\n__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n\n__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ssub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n\n__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ssub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ssax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usad8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usada8 %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n#define __SSAT16(ARG1,ARG2) \\\n({                          \\\n  int32_t __RES, __ARG1 = (ARG1); \\\n  __ASM (\"ssat16 %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) ); \\\n  __RES; \\\n })\n\n#define __USAT16(ARG1,ARG2) \\\n({                          \\\n  uint32_t __RES, __ARG1 = (ARG1); \\\n  __ASM (\"usat16 %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) ); \\\n  __RES; \\\n })\n\n__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uxtb16 %0, %1\" : \"=r\" (result) : \"r\" (op1));\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uxtab16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sxtb16 %0, %1\" : \"=r\" (result) : \"r\" (op1));\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sxtab16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smuad %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smuadx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smlad %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smladx %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)\n{\n  union llreg_u{\n    uint32_t w32[2];\n    uint64_t w64;\n  } llr;\n  llr.w64 = acc;\n\n#ifndef __ARMEB__   /* Little endian */\n  __ASM volatile (\"smlald %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\n#else               /* Big endian */\n  __ASM volatile (\"smlald %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\n#endif\n\n  return(llr.w64);\n}\n\n__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)\n{\n  union llreg_u{\n    uint32_t w32[2];\n    uint64_t w64;\n  } llr;\n  llr.w64 = acc;\n\n#ifndef __ARMEB__   /* Little endian */\n  __ASM volatile (\"smlaldx %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\n#else               /* Big endian */\n  __ASM volatile (\"smlaldx %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\n#endif\n\n  return(llr.w64);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smusd %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smusdx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smlsd %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smlsdx %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)\n{\n  union llreg_u{\n    uint32_t w32[2];\n    uint64_t w64;\n  } llr;\n  llr.w64 = acc;\n\n#ifndef __ARMEB__   /* Little endian */\n  __ASM volatile (\"smlsld %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\n#else               /* Big endian */\n  __ASM volatile (\"smlsld %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\n#endif\n\n  return(llr.w64);\n}\n\n__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)\n{\n  union llreg_u{\n    uint32_t w32[2];\n    uint64_t w64;\n  } llr;\n  llr.w64 = acc;\n\n#ifndef __ARMEB__   /* Little endian */\n  __ASM volatile (\"smlsldx %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\n#else               /* Big endian */\n  __ASM volatile (\"smlsldx %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\n#endif\n\n  return(llr.w64);\n}\n\n__STATIC_FORCEINLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sel %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE  int32_t __QADD( int32_t op1,  int32_t op2)\n{\n  int32_t result;\n\n  __ASM volatile (\"qadd %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)\n{\n  int32_t result;\n\n  __ASM volatile (\"qsub %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n#if 0\n#define __PKHBT(ARG1,ARG2,ARG3) \\\n({                          \\\n  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\\n  __ASM (\"pkhbt %0, %1, %2, lsl %3\" : \"=r\" (__RES) :  \"r\" (__ARG1), \"r\" (__ARG2), \"I\" (ARG3)  ); \\\n  __RES; \\\n })\n\n#define __PKHTB(ARG1,ARG2,ARG3) \\\n({                          \\\n  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\\n  if (ARG3 == 0) \\\n    __ASM (\"pkhtb %0, %1, %2\" : \"=r\" (__RES) :  \"r\" (__ARG1), \"r\" (__ARG2)  ); \\\n  else \\\n    __ASM (\"pkhtb %0, %1, %2, asr %3\" : \"=r\" (__RES) :  \"r\" (__ARG1), \"r\" (__ARG2), \"I\" (ARG3)  ); \\\n  __RES; \\\n })\n#endif\n\n#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \\\n                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )\n\n#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \\\n                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )\n\n__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)\n{\n int32_t result;\n\n __ASM volatile (\"smmla %0, %1, %2, %3\" : \"=r\" (result): \"r\"  (op1), \"r\" (op2), \"r\" (op3) );\n return(result);\n}\n\n#endif /* (__ARM_FEATURE_DSP == 1) */\n/*@} end of group CMSIS_SIMD_intrinsics */\n\n\n#pragma GCC diagnostic pop\n\n#endif /* __CMSIS_GCC_H */\n"
  },
  {
    "path": "3rd_party/CMSIS/Include/cmsis_iccarm.h",
    "content": "/**************************************************************************//**\n * @file     cmsis_iccarm.h\n * @brief    CMSIS compiler ICCARM (IAR Compiler for Arm) header file\n * @version  V5.1.0\n * @date     08. May 2019\n ******************************************************************************/\n\n//------------------------------------------------------------------------------\n//\n// Copyright (c) 2017-2019 IAR Systems\n// Copyright (c) 2017-2019 Arm Limited. All rights reserved.\n//\n// Licensed under the Apache License, Version 2.0 (the \"License\")\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//     http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n//\n//------------------------------------------------------------------------------\n\n\n#ifndef __CMSIS_ICCARM_H__\n#define __CMSIS_ICCARM_H__\n\n#ifndef __ICCARM__\n  #error This file should only be compiled by ICCARM\n#endif\n\n#pragma system_include\n\n#define __IAR_FT _Pragma(\"inline=forced\") __intrinsic\n\n#if (__VER__ >= 8000000)\n  #define __ICCARM_V8 1\n#else\n  #define __ICCARM_V8 0\n#endif\n\n#ifndef __ALIGNED\n  #if __ICCARM_V8\n    #define __ALIGNED(x) __attribute__((aligned(x)))\n  #elif (__VER__ >= 7080000)\n    /* Needs IAR language extensions */\n    #define __ALIGNED(x) __attribute__((aligned(x)))\n  #else\n    #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.\n    #define __ALIGNED(x)\n  #endif\n#endif\n\n\n/* Define compiler macros for CPU architecture, used in CMSIS 5.\n */\n#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__\n/* Macros already defined */\n#else\n  #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)\n    #define __ARM_ARCH_8M_MAIN__ 1\n  #elif defined(__ARM8M_BASELINE__)\n    #define __ARM_ARCH_8M_BASE__ 1\n  #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'\n    #if __ARM_ARCH == 6\n      #define __ARM_ARCH_6M__ 1\n    #elif __ARM_ARCH == 7\n      #if __ARM_FEATURE_DSP\n        #define __ARM_ARCH_7EM__ 1\n      #else\n        #define __ARM_ARCH_7M__ 1\n      #endif\n    #endif /* __ARM_ARCH */\n  #endif /* __ARM_ARCH_PROFILE == 'M' */\n#endif\n\n/* Alternativ core deduction for older ICCARM's */\n#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \\\n    !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)\n  #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)\n    #define __ARM_ARCH_6M__ 1\n  #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)\n    #define __ARM_ARCH_7M__ 1\n  #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)\n    #define __ARM_ARCH_7EM__  1\n  #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)\n    #define __ARM_ARCH_8M_BASE__ 1\n  #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)\n    #define __ARM_ARCH_8M_MAIN__ 1\n  #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)\n    #define __ARM_ARCH_8M_MAIN__ 1\n  #else\n    #error \"Unknown target.\"\n  #endif\n#endif\n\n\n\n#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1\n  #define __IAR_M0_FAMILY  1\n#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1\n  #define __IAR_M0_FAMILY  1\n#else\n  #define __IAR_M0_FAMILY  0\n#endif\n\n\n#ifndef __ASM\n  #define __ASM __asm\n#endif\n\n#ifndef   __COMPILER_BARRIER\n  #define __COMPILER_BARRIER() __ASM volatile(\"\":::\"memory\")\n#endif\n\n#ifndef __INLINE\n  #define __INLINE inline\n#endif\n\n#ifndef   __NO_RETURN\n  #if __ICCARM_V8\n    #define __NO_RETURN __attribute__((__noreturn__))\n  #else\n    #define __NO_RETURN _Pragma(\"object_attribute=__noreturn\")\n  #endif\n#endif\n\n#ifndef   __PACKED\n  #if __ICCARM_V8\n    #define __PACKED __attribute__((packed, aligned(1)))\n  #else\n    /* Needs IAR language extensions */\n    #define __PACKED __packed\n  #endif\n#endif\n\n#ifndef   __PACKED_STRUCT\n  #if __ICCARM_V8\n    #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))\n  #else\n    /* Needs IAR language extensions */\n    #define __PACKED_STRUCT __packed struct\n  #endif\n#endif\n\n#ifndef   __PACKED_UNION\n  #if __ICCARM_V8\n    #define __PACKED_UNION union __attribute__((packed, aligned(1)))\n  #else\n    /* Needs IAR language extensions */\n    #define __PACKED_UNION __packed union\n  #endif\n#endif\n\n#ifndef   __RESTRICT\n  #if __ICCARM_V8\n    #define __RESTRICT            __restrict\n  #else\n    /* Needs IAR language extensions */\n    #define __RESTRICT            restrict\n  #endif\n#endif\n\n#ifndef   __STATIC_INLINE\n  #define __STATIC_INLINE       static inline\n#endif\n\n#ifndef   __FORCEINLINE\n  #define __FORCEINLINE         _Pragma(\"inline=forced\")\n#endif\n\n#ifndef   __STATIC_FORCEINLINE\n  #define __STATIC_FORCEINLINE  __FORCEINLINE __STATIC_INLINE\n#endif\n\n#ifndef __UNALIGNED_UINT16_READ\n#pragma language=save\n#pragma language=extended\n__IAR_FT uint16_t __iar_uint16_read(void const *ptr)\n{\n  return *(__packed uint16_t*)(ptr);\n}\n#pragma language=restore\n#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)\n#endif\n\n\n#ifndef __UNALIGNED_UINT16_WRITE\n#pragma language=save\n#pragma language=extended\n__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)\n{\n  *(__packed uint16_t*)(ptr) = val;;\n}\n#pragma language=restore\n#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)\n#endif\n\n#ifndef __UNALIGNED_UINT32_READ\n#pragma language=save\n#pragma language=extended\n__IAR_FT uint32_t __iar_uint32_read(void const *ptr)\n{\n  return *(__packed uint32_t*)(ptr);\n}\n#pragma language=restore\n#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)\n#endif\n\n#ifndef __UNALIGNED_UINT32_WRITE\n#pragma language=save\n#pragma language=extended\n__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)\n{\n  *(__packed uint32_t*)(ptr) = val;;\n}\n#pragma language=restore\n#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)\n#endif\n\n#ifndef __UNALIGNED_UINT32   /* deprecated */\n#pragma language=save\n#pragma language=extended\n__packed struct  __iar_u32 { uint32_t v; };\n#pragma language=restore\n#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)\n#endif\n\n#ifndef   __USED\n  #if __ICCARM_V8\n    #define __USED __attribute__((used))\n  #else\n    #define __USED _Pragma(\"__root\")\n  #endif\n#endif\n\n#ifndef   __WEAK\n  #if __ICCARM_V8\n    #define __WEAK __attribute__((weak))\n  #else\n    #define __WEAK _Pragma(\"__weak\")\n  #endif\n#endif\n\n#ifndef __PROGRAM_START\n#define __PROGRAM_START           __iar_program_start\n#endif\n\n#ifndef __INITIAL_SP\n#define __INITIAL_SP              CSTACK$$Limit\n#endif\n\n#ifndef __STACK_LIMIT\n#define __STACK_LIMIT             CSTACK$$Base\n#endif\n\n#ifndef __VECTOR_TABLE\n#define __VECTOR_TABLE            __vector_table\n#endif\n\n#ifndef __VECTOR_TABLE_ATTRIBUTE\n#define __VECTOR_TABLE_ATTRIBUTE  @\".intvec\"\n#endif\n\n#ifndef __ICCARM_INTRINSICS_VERSION__\n  #define __ICCARM_INTRINSICS_VERSION__  0\n#endif\n\n#if __ICCARM_INTRINSICS_VERSION__ == 2\n\n  #if defined(__CLZ)\n    #undef __CLZ\n  #endif\n  #if defined(__REVSH)\n    #undef __REVSH\n  #endif\n  #if defined(__RBIT)\n    #undef __RBIT\n  #endif\n  #if defined(__SSAT)\n    #undef __SSAT\n  #endif\n  #if defined(__USAT)\n    #undef __USAT\n  #endif\n\n  #include \"iccarm_builtin.h\"\n\n  #define __disable_fault_irq __iar_builtin_disable_fiq\n  #define __disable_irq       __iar_builtin_disable_interrupt\n  #define __enable_fault_irq  __iar_builtin_enable_fiq\n  #define __enable_irq        __iar_builtin_enable_interrupt\n  #define __arm_rsr           __iar_builtin_rsr\n  #define __arm_wsr           __iar_builtin_wsr\n\n\n  #define __get_APSR()                (__arm_rsr(\"APSR\"))\n  #define __get_BASEPRI()             (__arm_rsr(\"BASEPRI\"))\n  #define __get_CONTROL()             (__arm_rsr(\"CONTROL\"))\n  #define __get_FAULTMASK()           (__arm_rsr(\"FAULTMASK\"))\n\n  #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\\n       (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )\n    #define __get_FPSCR()             (__arm_rsr(\"FPSCR\"))\n    #define __set_FPSCR(VALUE)        (__arm_wsr(\"FPSCR\", (VALUE)))\n  #else\n    #define __get_FPSCR()             ( 0 )\n    #define __set_FPSCR(VALUE)        ((void)VALUE)\n  #endif\n\n  #define __get_IPSR()                (__arm_rsr(\"IPSR\"))\n  #define __get_MSP()                 (__arm_rsr(\"MSP\"))\n  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n    // without main extensions, the non-secure MSPLIM is RAZ/WI\n    #define __get_MSPLIM()            (0U)\n  #else\n    #define __get_MSPLIM()            (__arm_rsr(\"MSPLIM\"))\n  #endif\n  #define __get_PRIMASK()             (__arm_rsr(\"PRIMASK\"))\n  #define __get_PSP()                 (__arm_rsr(\"PSP\"))\n\n  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n    // without main extensions, the non-secure PSPLIM is RAZ/WI\n    #define __get_PSPLIM()            (0U)\n  #else\n    #define __get_PSPLIM()            (__arm_rsr(\"PSPLIM\"))\n  #endif\n\n  #define __get_xPSR()                (__arm_rsr(\"xPSR\"))\n\n  #define __set_BASEPRI(VALUE)        (__arm_wsr(\"BASEPRI\", (VALUE)))\n  #define __set_BASEPRI_MAX(VALUE)    (__arm_wsr(\"BASEPRI_MAX\", (VALUE)))\n  #define __set_CONTROL(VALUE)        (__arm_wsr(\"CONTROL\", (VALUE)))\n  #define __set_FAULTMASK(VALUE)      (__arm_wsr(\"FAULTMASK\", (VALUE)))\n  #define __set_MSP(VALUE)            (__arm_wsr(\"MSP\", (VALUE)))\n\n  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n    // without main extensions, the non-secure MSPLIM is RAZ/WI\n    #define __set_MSPLIM(VALUE)       ((void)(VALUE))\n  #else\n    #define __set_MSPLIM(VALUE)       (__arm_wsr(\"MSPLIM\", (VALUE)))\n  #endif\n  #define __set_PRIMASK(VALUE)        (__arm_wsr(\"PRIMASK\", (VALUE)))\n  #define __set_PSP(VALUE)            (__arm_wsr(\"PSP\", (VALUE)))\n  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n    // without main extensions, the non-secure PSPLIM is RAZ/WI\n    #define __set_PSPLIM(VALUE)       ((void)(VALUE))\n  #else\n    #define __set_PSPLIM(VALUE)       (__arm_wsr(\"PSPLIM\", (VALUE)))\n  #endif\n\n  #define __TZ_get_CONTROL_NS()       (__arm_rsr(\"CONTROL_NS\"))\n  #define __TZ_set_CONTROL_NS(VALUE)  (__arm_wsr(\"CONTROL_NS\", (VALUE)))\n  #define __TZ_get_PSP_NS()           (__arm_rsr(\"PSP_NS\"))\n  #define __TZ_set_PSP_NS(VALUE)      (__arm_wsr(\"PSP_NS\", (VALUE)))\n  #define __TZ_get_MSP_NS()           (__arm_rsr(\"MSP_NS\"))\n  #define __TZ_set_MSP_NS(VALUE)      (__arm_wsr(\"MSP_NS\", (VALUE)))\n  #define __TZ_get_SP_NS()            (__arm_rsr(\"SP_NS\"))\n  #define __TZ_set_SP_NS(VALUE)       (__arm_wsr(\"SP_NS\", (VALUE)))\n  #define __TZ_get_PRIMASK_NS()       (__arm_rsr(\"PRIMASK_NS\"))\n  #define __TZ_set_PRIMASK_NS(VALUE)  (__arm_wsr(\"PRIMASK_NS\", (VALUE)))\n  #define __TZ_get_BASEPRI_NS()       (__arm_rsr(\"BASEPRI_NS\"))\n  #define __TZ_set_BASEPRI_NS(VALUE)  (__arm_wsr(\"BASEPRI_NS\", (VALUE)))\n  #define __TZ_get_FAULTMASK_NS()     (__arm_rsr(\"FAULTMASK_NS\"))\n  #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr(\"FAULTMASK_NS\", (VALUE)))\n\n  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n    // without main extensions, the non-secure PSPLIM is RAZ/WI\n    #define __TZ_get_PSPLIM_NS()      (0U)\n    #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))\n  #else\n    #define __TZ_get_PSPLIM_NS()      (__arm_rsr(\"PSPLIM_NS\"))\n    #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr(\"PSPLIM_NS\", (VALUE)))\n  #endif\n\n  #define __TZ_get_MSPLIM_NS()        (__arm_rsr(\"MSPLIM_NS\"))\n  #define __TZ_set_MSPLIM_NS(VALUE)   (__arm_wsr(\"MSPLIM_NS\", (VALUE)))\n\n  #define __NOP     __iar_builtin_no_operation\n\n  #define __CLZ     __iar_builtin_CLZ\n  #define __CLREX   __iar_builtin_CLREX\n\n  #define __DMB     __iar_builtin_DMB\n  #define __DSB     __iar_builtin_DSB\n  #define __ISB     __iar_builtin_ISB\n\n  #define __LDREXB  __iar_builtin_LDREXB\n  #define __LDREXH  __iar_builtin_LDREXH\n  #define __LDREXW  __iar_builtin_LDREX\n\n  #define __RBIT    __iar_builtin_RBIT\n  #define __REV     __iar_builtin_REV\n  #define __REV16   __iar_builtin_REV16\n\n  __IAR_FT int16_t __REVSH(int16_t val)\n  {\n    return (int16_t) __iar_builtin_REVSH(val);\n  }\n\n  #define __ROR     __iar_builtin_ROR\n  #define __RRX     __iar_builtin_RRX\n\n  #define __SEV     __iar_builtin_SEV\n\n  #if !__IAR_M0_FAMILY\n    #define __SSAT    __iar_builtin_SSAT\n  #endif\n\n  #define __STREXB  __iar_builtin_STREXB\n  #define __STREXH  __iar_builtin_STREXH\n  #define __STREXW  __iar_builtin_STREX\n\n  #if !__IAR_M0_FAMILY\n    #define __USAT    __iar_builtin_USAT\n  #endif\n\n  #define __WFE     __iar_builtin_WFE\n  #define __WFI     __iar_builtin_WFI\n\n  #if __ARM_MEDIA__\n    #define __SADD8   __iar_builtin_SADD8\n    #define __QADD8   __iar_builtin_QADD8\n    #define __SHADD8  __iar_builtin_SHADD8\n    #define __UADD8   __iar_builtin_UADD8\n    #define __UQADD8  __iar_builtin_UQADD8\n    #define __UHADD8  __iar_builtin_UHADD8\n    #define __SSUB8   __iar_builtin_SSUB8\n    #define __QSUB8   __iar_builtin_QSUB8\n    #define __SHSUB8  __iar_builtin_SHSUB8\n    #define __USUB8   __iar_builtin_USUB8\n    #define __UQSUB8  __iar_builtin_UQSUB8\n    #define __UHSUB8  __iar_builtin_UHSUB8\n    #define __SADD16  __iar_builtin_SADD16\n    #define __QADD16  __iar_builtin_QADD16\n    #define __SHADD16 __iar_builtin_SHADD16\n    #define __UADD16  __iar_builtin_UADD16\n    #define __UQADD16 __iar_builtin_UQADD16\n    #define __UHADD16 __iar_builtin_UHADD16\n    #define __SSUB16  __iar_builtin_SSUB16\n    #define __QSUB16  __iar_builtin_QSUB16\n    #define __SHSUB16 __iar_builtin_SHSUB16\n    #define __USUB16  __iar_builtin_USUB16\n    #define __UQSUB16 __iar_builtin_UQSUB16\n    #define __UHSUB16 __iar_builtin_UHSUB16\n    #define __SASX    __iar_builtin_SASX\n    #define __QASX    __iar_builtin_QASX\n    #define __SHASX   __iar_builtin_SHASX\n    #define __UASX    __iar_builtin_UASX\n    #define __UQASX   __iar_builtin_UQASX\n    #define __UHASX   __iar_builtin_UHASX\n    #define __SSAX    __iar_builtin_SSAX\n    #define __QSAX    __iar_builtin_QSAX\n    #define __SHSAX   __iar_builtin_SHSAX\n    #define __USAX    __iar_builtin_USAX\n    #define __UQSAX   __iar_builtin_UQSAX\n    #define __UHSAX   __iar_builtin_UHSAX\n    #define __USAD8   __iar_builtin_USAD8\n    #define __USADA8  __iar_builtin_USADA8\n    #define __SSAT16  __iar_builtin_SSAT16\n    #define __USAT16  __iar_builtin_USAT16\n    #define __UXTB16  __iar_builtin_UXTB16\n    #define __UXTAB16 __iar_builtin_UXTAB16\n    #define __SXTB16  __iar_builtin_SXTB16\n    #define __SXTAB16 __iar_builtin_SXTAB16\n    #define __SMUAD   __iar_builtin_SMUAD\n    #define __SMUADX  __iar_builtin_SMUADX\n    #define __SMMLA   __iar_builtin_SMMLA\n    #define __SMLAD   __iar_builtin_SMLAD\n    #define __SMLADX  __iar_builtin_SMLADX\n    #define __SMLALD  __iar_builtin_SMLALD\n    #define __SMLALDX __iar_builtin_SMLALDX\n    #define __SMUSD   __iar_builtin_SMUSD\n    #define __SMUSDX  __iar_builtin_SMUSDX\n    #define __SMLSD   __iar_builtin_SMLSD\n    #define __SMLSDX  __iar_builtin_SMLSDX\n    #define __SMLSLD  __iar_builtin_SMLSLD\n    #define __SMLSLDX __iar_builtin_SMLSLDX\n    #define __SEL     __iar_builtin_SEL\n    #define __QADD    __iar_builtin_QADD\n    #define __QSUB    __iar_builtin_QSUB\n    #define __PKHBT   __iar_builtin_PKHBT\n    #define __PKHTB   __iar_builtin_PKHTB\n  #endif\n\n#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */\n\n  #if __IAR_M0_FAMILY\n   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */\n    #define __CLZ  __cmsis_iar_clz_not_active\n    #define __SSAT __cmsis_iar_ssat_not_active\n    #define __USAT __cmsis_iar_usat_not_active\n    #define __RBIT __cmsis_iar_rbit_not_active\n    #define __get_APSR  __cmsis_iar_get_APSR_not_active\n  #endif\n\n\n  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\\n         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))\n    #define __get_FPSCR __cmsis_iar_get_FPSR_not_active\n    #define __set_FPSCR __cmsis_iar_set_FPSR_not_active\n  #endif\n\n  #ifdef __INTRINSICS_INCLUDED\n  #error intrinsics.h is already included previously!\n  #endif\n\n  #include <intrinsics.h>\n\n  #if __IAR_M0_FAMILY\n   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */\n    #undef __CLZ\n    #undef __SSAT\n    #undef __USAT\n    #undef __RBIT\n    #undef __get_APSR\n\n    __STATIC_INLINE uint8_t __CLZ(uint32_t data)\n    {\n      if (data == 0U) { return 32U; }\n\n      uint32_t count = 0U;\n      uint32_t mask = 0x80000000U;\n\n      while ((data & mask) == 0U)\n      {\n        count += 1U;\n        mask = mask >> 1U;\n      }\n      return count;\n    }\n\n    __STATIC_INLINE uint32_t __RBIT(uint32_t v)\n    {\n      uint8_t sc = 31U;\n      uint32_t r = v;\n      for (v >>= 1U; v; v >>= 1U)\n      {\n        r <<= 1U;\n        r |= v & 1U;\n        sc--;\n      }\n      return (r << sc);\n    }\n\n    __STATIC_INLINE  uint32_t __get_APSR(void)\n    {\n      uint32_t res;\n      __asm(\"MRS      %0,APSR\" : \"=r\" (res));\n      return res;\n    }\n\n  #endif\n\n  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\\n         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))\n    #undef __get_FPSCR\n    #undef __set_FPSCR\n    #define __get_FPSCR()       (0)\n    #define __set_FPSCR(VALUE)  ((void)VALUE)\n  #endif\n\n  #pragma diag_suppress=Pe940\n  #pragma diag_suppress=Pe177\n\n  #define __enable_irq    __enable_interrupt\n  #define __disable_irq   __disable_interrupt\n  #define __NOP           __no_operation\n\n  #define __get_xPSR      __get_PSR\n\n  #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)\n\n    __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)\n    {\n      return __LDREX((unsigned long *)ptr);\n    }\n\n    __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)\n    {\n      return __STREX(value, (unsigned long *)ptr);\n    }\n  #endif\n\n\n  /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */\n  #if (__CORTEX_M >= 0x03)\n\n    __IAR_FT uint32_t __RRX(uint32_t value)\n    {\n      uint32_t result;\n      __ASM(\"RRX      %0, %1\" : \"=r\"(result) : \"r\" (value) : \"cc\");\n      return(result);\n    }\n\n    __IAR_FT void __set_BASEPRI_MAX(uint32_t value)\n    {\n      __asm volatile(\"MSR      BASEPRI_MAX,%0\"::\"r\" (value));\n    }\n\n\n    #define __enable_fault_irq  __enable_fiq\n    #define __disable_fault_irq __disable_fiq\n\n\n  #endif /* (__CORTEX_M >= 0x03) */\n\n  __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)\n  {\n    return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));\n  }\n\n  #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n       (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\n\n   __IAR_FT uint32_t __get_MSPLIM(void)\n    {\n      uint32_t res;\n    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))\n      // without main extensions, the non-secure MSPLIM is RAZ/WI\n      res = 0U;\n    #else\n      __asm volatile(\"MRS      %0,MSPLIM\" : \"=r\" (res));\n    #endif\n      return res;\n    }\n\n    __IAR_FT void   __set_MSPLIM(uint32_t value)\n    {\n    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))\n      // without main extensions, the non-secure MSPLIM is RAZ/WI\n      (void)value;\n    #else\n      __asm volatile(\"MSR      MSPLIM,%0\" :: \"r\" (value));\n    #endif\n    }\n\n    __IAR_FT uint32_t __get_PSPLIM(void)\n    {\n      uint32_t res;\n    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))\n      // without main extensions, the non-secure PSPLIM is RAZ/WI\n      res = 0U;\n    #else\n      __asm volatile(\"MRS      %0,PSPLIM\" : \"=r\" (res));\n    #endif\n      return res;\n    }\n\n    __IAR_FT void   __set_PSPLIM(uint32_t value)\n    {\n    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))\n      // without main extensions, the non-secure PSPLIM is RAZ/WI\n      (void)value;\n    #else\n      __asm volatile(\"MSR      PSPLIM,%0\" :: \"r\" (value));\n    #endif\n    }\n\n    __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)\n    {\n      uint32_t res;\n      __asm volatile(\"MRS      %0,CONTROL_NS\" : \"=r\" (res));\n      return res;\n    }\n\n    __IAR_FT void   __TZ_set_CONTROL_NS(uint32_t value)\n    {\n      __asm volatile(\"MSR      CONTROL_NS,%0\" :: \"r\" (value));\n    }\n\n    __IAR_FT uint32_t   __TZ_get_PSP_NS(void)\n    {\n      uint32_t res;\n      __asm volatile(\"MRS      %0,PSP_NS\" : \"=r\" (res));\n      return res;\n    }\n\n    __IAR_FT void   __TZ_set_PSP_NS(uint32_t value)\n    {\n      __asm volatile(\"MSR      PSP_NS,%0\" :: \"r\" (value));\n    }\n\n    __IAR_FT uint32_t   __TZ_get_MSP_NS(void)\n    {\n      uint32_t res;\n      __asm volatile(\"MRS      %0,MSP_NS\" : \"=r\" (res));\n      return res;\n    }\n\n    __IAR_FT void   __TZ_set_MSP_NS(uint32_t value)\n    {\n      __asm volatile(\"MSR      MSP_NS,%0\" :: \"r\" (value));\n    }\n\n    __IAR_FT uint32_t   __TZ_get_SP_NS(void)\n    {\n      uint32_t res;\n      __asm volatile(\"MRS      %0,SP_NS\" : \"=r\" (res));\n      return res;\n    }\n    __IAR_FT void   __TZ_set_SP_NS(uint32_t value)\n    {\n      __asm volatile(\"MSR      SP_NS,%0\" :: \"r\" (value));\n    }\n\n    __IAR_FT uint32_t   __TZ_get_PRIMASK_NS(void)\n    {\n      uint32_t res;\n      __asm volatile(\"MRS      %0,PRIMASK_NS\" : \"=r\" (res));\n      return res;\n    }\n\n    __IAR_FT void   __TZ_set_PRIMASK_NS(uint32_t value)\n    {\n      __asm volatile(\"MSR      PRIMASK_NS,%0\" :: \"r\" (value));\n    }\n\n    __IAR_FT uint32_t   __TZ_get_BASEPRI_NS(void)\n    {\n      uint32_t res;\n      __asm volatile(\"MRS      %0,BASEPRI_NS\" : \"=r\" (res));\n      return res;\n    }\n\n    __IAR_FT void   __TZ_set_BASEPRI_NS(uint32_t value)\n    {\n      __asm volatile(\"MSR      BASEPRI_NS,%0\" :: \"r\" (value));\n    }\n\n    __IAR_FT uint32_t   __TZ_get_FAULTMASK_NS(void)\n    {\n      uint32_t res;\n      __asm volatile(\"MRS      %0,FAULTMASK_NS\" : \"=r\" (res));\n      return res;\n    }\n\n    __IAR_FT void   __TZ_set_FAULTMASK_NS(uint32_t value)\n    {\n      __asm volatile(\"MSR      FAULTMASK_NS,%0\" :: \"r\" (value));\n    }\n\n    __IAR_FT uint32_t   __TZ_get_PSPLIM_NS(void)\n    {\n      uint32_t res;\n    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))\n      // without main extensions, the non-secure PSPLIM is RAZ/WI\n      res = 0U;\n    #else\n      __asm volatile(\"MRS      %0,PSPLIM_NS\" : \"=r\" (res));\n    #endif\n      return res;\n    }\n\n    __IAR_FT void   __TZ_set_PSPLIM_NS(uint32_t value)\n    {\n    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))\n      // without main extensions, the non-secure PSPLIM is RAZ/WI\n      (void)value;\n    #else\n      __asm volatile(\"MSR      PSPLIM_NS,%0\" :: \"r\" (value));\n    #endif\n    }\n\n    __IAR_FT uint32_t   __TZ_get_MSPLIM_NS(void)\n    {\n      uint32_t res;\n      __asm volatile(\"MRS      %0,MSPLIM_NS\" : \"=r\" (res));\n      return res;\n    }\n\n    __IAR_FT void   __TZ_set_MSPLIM_NS(uint32_t value)\n    {\n      __asm volatile(\"MSR      MSPLIM_NS,%0\" :: \"r\" (value));\n    }\n\n  #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */\n\n#endif   /* __ICCARM_INTRINSICS_VERSION__ == 2 */\n\n#define __BKPT(value)    __asm volatile (\"BKPT     %0\" : : \"i\"(value))\n\n#if __IAR_M0_FAMILY\n  __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)\n  {\n    if ((sat >= 1U) && (sat <= 32U))\n    {\n      const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);\n      const int32_t min = -1 - max ;\n      if (val > max)\n      {\n        return max;\n      }\n      else if (val < min)\n      {\n        return min;\n      }\n    }\n    return val;\n  }\n\n  __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)\n  {\n    if (sat <= 31U)\n    {\n      const uint32_t max = ((1U << sat) - 1U);\n      if (val > (int32_t)max)\n      {\n        return max;\n      }\n      else if (val < 0)\n      {\n        return 0U;\n      }\n    }\n    return (uint32_t)val;\n  }\n#endif\n\n#if (__CORTEX_M >= 0x03)   /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */\n\n  __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)\n  {\n    uint32_t res;\n    __ASM(\"LDRBT %0, [%1]\" : \"=r\" (res) : \"r\" (addr) : \"memory\");\n    return ((uint8_t)res);\n  }\n\n  __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)\n  {\n    uint32_t res;\n    __ASM(\"LDRHT %0, [%1]\" : \"=r\" (res) : \"r\" (addr) : \"memory\");\n    return ((uint16_t)res);\n  }\n\n  __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)\n  {\n    uint32_t res;\n    __ASM(\"LDRT %0, [%1]\" : \"=r\" (res) : \"r\" (addr) : \"memory\");\n    return res;\n  }\n\n  __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)\n  {\n    __ASM(\"STRBT %1, [%0]\" : : \"r\" (addr), \"r\" ((uint32_t)value) : \"memory\");\n  }\n\n  __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)\n  {\n    __ASM(\"STRHT %1, [%0]\" : : \"r\" (addr), \"r\" ((uint32_t)value) : \"memory\");\n  }\n\n  __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)\n  {\n    __ASM(\"STRT %1, [%0]\" : : \"r\" (addr), \"r\" (value) : \"memory\");\n  }\n\n#endif /* (__CORTEX_M >= 0x03) */\n\n#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\n\n\n  __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)\n  {\n    uint32_t res;\n    __ASM volatile (\"LDAB %0, [%1]\" : \"=r\" (res) : \"r\" (ptr) : \"memory\");\n    return ((uint8_t)res);\n  }\n\n  __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)\n  {\n    uint32_t res;\n    __ASM volatile (\"LDAH %0, [%1]\" : \"=r\" (res) : \"r\" (ptr) : \"memory\");\n    return ((uint16_t)res);\n  }\n\n  __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)\n  {\n    uint32_t res;\n    __ASM volatile (\"LDA %0, [%1]\" : \"=r\" (res) : \"r\" (ptr) : \"memory\");\n    return res;\n  }\n\n  __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)\n  {\n    __ASM volatile (\"STLB %1, [%0]\" :: \"r\" (ptr), \"r\" (value) : \"memory\");\n  }\n\n  __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)\n  {\n    __ASM volatile (\"STLH %1, [%0]\" :: \"r\" (ptr), \"r\" (value) : \"memory\");\n  }\n\n  __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)\n  {\n    __ASM volatile (\"STL %1, [%0]\" :: \"r\" (ptr), \"r\" (value) : \"memory\");\n  }\n\n  __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)\n  {\n    uint32_t res;\n    __ASM volatile (\"LDAEXB %0, [%1]\" : \"=r\" (res) : \"r\" (ptr) : \"memory\");\n    return ((uint8_t)res);\n  }\n\n  __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)\n  {\n    uint32_t res;\n    __ASM volatile (\"LDAEXH %0, [%1]\" : \"=r\" (res) : \"r\" (ptr) : \"memory\");\n    return ((uint16_t)res);\n  }\n\n  __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)\n  {\n    uint32_t res;\n    __ASM volatile (\"LDAEX %0, [%1]\" : \"=r\" (res) : \"r\" (ptr) : \"memory\");\n    return res;\n  }\n\n  __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)\n  {\n    uint32_t res;\n    __ASM volatile (\"STLEXB %0, %2, [%1]\" : \"=r\" (res) : \"r\" (ptr), \"r\" (value) : \"memory\");\n    return res;\n  }\n\n  __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)\n  {\n    uint32_t res;\n    __ASM volatile (\"STLEXH %0, %2, [%1]\" : \"=r\" (res) : \"r\" (ptr), \"r\" (value) : \"memory\");\n    return res;\n  }\n\n  __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)\n  {\n    uint32_t res;\n    __ASM volatile (\"STLEX %0, %2, [%1]\" : \"=r\" (res) : \"r\" (ptr), \"r\" (value) : \"memory\");\n    return res;\n  }\n\n#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */\n\n#undef __IAR_FT\n#undef __IAR_M0_FAMILY\n#undef __ICCARM_V8\n\n#pragma diag_default=Pe940\n#pragma diag_default=Pe177\n\n#endif /* __CMSIS_ICCARM_H__ */\n"
  },
  {
    "path": "3rd_party/CMSIS/Include/cmsis_version.h",
    "content": "/**************************************************************************//**\n * @file     cmsis_version.h\n * @brief    CMSIS Core(M) Version definitions\n * @version  V5.0.3\n * @date     24. June 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CMSIS_VERSION_H\n#define __CMSIS_VERSION_H\n\n/*  CMSIS Version definitions */\n#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */\n#define __CM_CMSIS_VERSION_SUB   ( 3U)                                      /*!< [15:0]  CMSIS Core(M) sub version */\n#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \\\n                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */\n#endif\n"
  },
  {
    "path": "3rd_party/CMSIS/Include/core_armv81mml.h",
    "content": "/**************************************************************************//**\n * @file     core_armv81mml.h\n * @brief    CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File\n * @version  V1.0.0\n * @date     15. March 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2018-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CORE_ARMV81MML_H_GENERIC\n#define __CORE_ARMV81MML_H_GENERIC\n\n#include <stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup Cortex_ARMV81MML\n  @{\n */\n\n#include \"cmsis_version.h\"\n\n#define __ARM_ARCH_8M_MAIN__    1  // patching for now\n/*  CMSIS ARMV81MML definitions */\n#define __ARMv81MML_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \\deprecated [31:16] CMSIS HAL main version */\n#define __ARMv81MML_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \\deprecated [15:0]  CMSIS HAL sub version */\n#define __ARMv81MML_CMSIS_VERSION       ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \\\n                                         __ARMv81MML_CMSIS_VERSION_SUB           )  /*!< \\deprecated CMSIS HAL version number */\n\n#define __CORTEX_M                     (81U)                                       /*!< Cortex-M Core */\n\n/** __FPU_USED indicates whether an FPU is used or not.\n    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\n*/\n#if defined ( __CC_ARM )\n  #if defined __TARGET_FPU_VFP\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined(__ARM_FEATURE_DSP)\n    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED         0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined __ARM_FP\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #warning \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined(__ARM_FEATURE_DSP)\n    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED         0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined(__ARM_FEATURE_DSP)\n    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED         0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined __ARMVFP__\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined(__ARM_FEATURE_DSP)\n    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED         0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined ( __TI_ARM__ )\n  #if defined __TI_VFP_SUPPORT__\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined __FPU_VFP__\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_ARMV81MML_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_ARMV81MML_H_DEPENDANT\n#define __CORE_ARMV81MML_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __ARMv81MML_REV\n    #define __ARMv81MML_REV               0x0000U\n    #warning \"__ARMv81MML_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __FPU_PRESENT\n    #define __FPU_PRESENT             0U\n    #warning \"__FPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __MPU_PRESENT\n    #define __MPU_PRESENT             0U\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __SAUREGION_PRESENT\n    #define __SAUREGION_PRESENT       0U\n    #warning \"__SAUREGION_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __DSP_PRESENT\n    #define __DSP_PRESENT             0U\n    #warning \"__DSP_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          3U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/*@} end of group ARMv81MML */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core SCB Register\n  - Core SysTick Register\n  - Core Debug Register\n  - Core MPU Register\n  - Core SAU Register\n  - Core FPU Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for Cortex-M processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */\n    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\n    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */\n#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */\n\n#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */\n#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */\n    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\n    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\n    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */\n#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */\n\n#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */\n#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */\n#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */\n    uint32_t FPCA:1;                     /*!< bit:      2  Floating-point context active */\n    uint32_t SFPA:1;                     /*!< bit:      3  Secure floating-point active */\n    uint32_t _reserved1:28;              /*!< bit:  4..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */\n#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */\n\n#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */\n#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */\n\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\n#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\n\n/*@} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[16U];\n  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RSERVED1[16U];\n  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[16U];\n  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[16U];\n  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\n        uint32_t RESERVED4[16U];\n  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */\n        uint32_t RESERVED5[16U];\n  __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */\n        uint32_t RESERVED6[580U];\n  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */\n}  NVIC_Type;\n\n/* Software Triggered Interrupt Register Definitions */\n#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */\n#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */\n\n/*@} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */\n  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */\n  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */\n  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */\n  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */\n  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */\n  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */\n  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */\n  __IM  uint32_t ID_ADR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */\n  __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */\n  __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */\n  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */\n  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */\n  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */\n  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */\n  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */\n  __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */\n        uint32_t RESERVED3[92U];\n  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */\n        uint32_t RESERVED4[15U];\n  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */\n  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */\n  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */\n        uint32_t RESERVED5[1U];\n  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */\n        uint32_t RESERVED6[1U];\n  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */\n  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */\n  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */\n  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */\n  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */\n  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */\n  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */\n  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */\n        uint32_t RESERVED7[6U];\n  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */\n  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */\n  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */\n  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */\n  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */\n        uint32_t RESERVED8[1U];\n  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */\n} SCB_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */\n#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */\n\n#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */\n#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */\n\n#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */\n#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */\n#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\n#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n/* SCB Vector Table Offset Register Definitions */\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\n#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */\n#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */\n\n#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */\n#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */\n\n#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */\n#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */\n\n#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */\n#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */\n#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */\n#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */\n\n#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */\n#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */\n\n#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */\n#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */\n\n#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */\n#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */\n\n#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\n#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\n\n#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\n#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\n#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */\n#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */\n\n#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */\n#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */\n\n#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */\n#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */\n\n#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */\n#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */\n\n#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */\n#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */\n\n#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */\n#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */\n\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */\n#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */\n\n#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */\n#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */\n\n#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */\n#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */\n\n#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\n#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\n\n#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\n#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\n\n#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */\n#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */\n\n#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\n#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\n\n#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */\n#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */\n\n#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */\n#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */\n\n#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */\n#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */\n\n#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */\n#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */\n\n#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */\n#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */\n\n#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */\n#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */\n\n/* SCB Configurable Fault Status Register Definitions */\n#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */\n#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */\n\n#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */\n#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */\n\n#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */\n#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\n\n/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */\n#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */\n\n#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */\n#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */\n\n#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */\n#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */\n\n#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\n#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\n\n#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */\n#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\n\n#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */\n#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\n\n/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */\n#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */\n\n#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */\n#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */\n\n#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */\n#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */\n\n#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */\n#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */\n\n#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */\n#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\n\n#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */\n#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */\n\n#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */\n#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */\n\n/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */\n#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\n\n#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */\n#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */\n\n#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */\n#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */\n\n#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */\n#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */\n\n#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */\n#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */\n\n#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */\n#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */\n\n#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\n#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\n\n/* SCB Hard Fault Status Register Definitions */\n#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */\n#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */\n\n#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */\n#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */\n\n#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */\n#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */\n\n/* SCB Debug Fault Status Register Definitions */\n#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */\n#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */\n\n#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */\n#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */\n\n#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */\n#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */\n\n#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */\n#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */\n\n#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */\n#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */\n\n/* SCB Non-Secure Access Control Register Definitions */\n#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */\n#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */\n\n#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */\n#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */\n\n#define SCB_NSACR_CPn_Pos                   0U                                            /*!< SCB NSACR: CPn Position */\n#define SCB_NSACR_CPn_Msk                  (1UL /*<< SCB_NSACR_CPn_Pos*/)                 /*!< SCB NSACR: CPn Mask */\n\n/* SCB Cache Level ID Register Definitions */\n#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */\n#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */\n\n#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */\n#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */\n\n/* SCB Cache Type Register Definitions */\n#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */\n#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */\n\n#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */\n#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */\n\n#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */\n#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */\n\n#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */\n#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */\n\n#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */\n#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */\n\n/* SCB Cache Size ID Register Definitions */\n#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */\n#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */\n\n#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */\n#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */\n\n#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */\n#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */\n\n#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */\n#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */\n\n#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */\n#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */\n\n#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */\n#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */\n\n#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */\n#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */\n\n/* SCB Cache Size Selection Register Definitions */\n#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */\n#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */\n\n#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */\n#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */\n\n/* SCB Software Triggered Interrupt Register Definitions */\n#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */\n#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */\n\n/* SCB D-Cache Invalidate by Set-way Register Definitions */\n#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */\n#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */\n\n#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */\n#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */\n\n/* SCB D-Cache Clean by Set-way Register Definitions */\n#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */\n#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */\n\n#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */\n#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */\n\n/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */\n#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */\n#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */\n\n#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */\n#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */\n\n/* Instruction Tightly-Coupled Memory Control Register Definitions */\n#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */\n#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */\n\n#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */\n#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */\n\n#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */\n#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */\n\n#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */\n#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */\n\n/* Data Tightly-Coupled Memory Control Register Definitions */\n#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */\n#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */\n\n#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */\n#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */\n\n#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */\n#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */\n\n#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */\n#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */\n\n/* AHBP Control Register Definitions */\n#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */\n#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */\n\n#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */\n#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */\n\n/* L1 Cache Control Register Definitions */\n#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */\n#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */\n\n#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */\n#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */\n\n#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */\n#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */\n\n/* AHBS Control Register Definitions */\n#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */\n#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */\n\n#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */\n#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */\n\n#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/\n#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */\n\n/* Auxiliary Bus Fault Status Register Definitions */\n#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/\n#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */\n\n#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/\n#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */\n\n#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/\n#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */\n\n#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/\n#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */\n\n#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/\n#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */\n\n#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/\n#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */\n\n/*@} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\n  \\brief    Type definitions for the System Control and ID Register not in the SCB\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control and ID Register not in the SCB.\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1U];\n  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */\n  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\n  __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */\n} SCnSCB_Type;\n\n/* Interrupt Controller Type Register Definitions */\n#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */\n#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */\n\n/*@} end of group CMSIS_SCnotSCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/*@} end of group CMSIS_SysTick */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)\n  \\brief    Type definitions for the Instrumentation Trace Macrocell (ITM)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).\n */\ntypedef struct\n{\n  __OM  union\n  {\n    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */\n    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */\n    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */\n  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */\n        uint32_t RESERVED0[864U];\n  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */\n        uint32_t RESERVED1[15U];\n  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */\n        uint32_t RESERVED2[15U];\n  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */\n        uint32_t RESERVED3[29U];\n  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */\n  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */\n  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */\n        uint32_t RESERVED4[43U];\n  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */\n        uint32_t RESERVED5[1U];\n  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */\n        uint32_t RESERVED6[4U];\n  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */\n  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */\n  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */\n  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */\n  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */\n  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */\n  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */\n  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */\n  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */\n  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */\n  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */\n  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */\n} ITM_Type;\n\n/* ITM Stimulus Port Register Definitions */\n#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */\n#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */\n\n#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */\n#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */\n\n/* ITM Trace Privilege Register Definitions */\n#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */\n#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */\n\n/* ITM Trace Control Register Definitions */\n#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */\n#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */\n\n#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */\n#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */\n\n#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */\n#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */\n\n#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */\n#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */\n\n#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */\n#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */\n\n#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */\n#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */\n\n#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */\n#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */\n\n#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */\n#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */\n\n#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */\n#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */\n\n#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */\n#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */\n\n/* ITM Integration Write Register Definitions */\n#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */\n#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */\n\n/* ITM Integration Read Register Definitions */\n#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */\n#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */\n\n/* ITM Integration Mode Control Register Definitions */\n#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */\n#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */\n\n/* ITM Lock Status Register Definitions */\n#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */\n#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */\n\n#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */\n#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */\n\n#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */\n#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */\n\n/*@}*/ /* end of group CMSIS_ITM */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\n  \\brief    Type definitions for the Data Watchpoint and Trace (DWT)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\n  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */\n  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */\n  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */\n  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */\n  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */\n  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */\n  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\n  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\n        uint32_t RESERVED1[1U];\n  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\n        uint32_t RESERVED2[1U];\n  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\n        uint32_t RESERVED3[1U];\n  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\n        uint32_t RESERVED4[1U];\n  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\n        uint32_t RESERVED5[1U];\n  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\n        uint32_t RESERVED6[1U];\n  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\n        uint32_t RESERVED7[1U];\n  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\n        uint32_t RESERVED8[1U];\n  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */\n        uint32_t RESERVED9[1U];\n  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */\n        uint32_t RESERVED10[1U];\n  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */\n        uint32_t RESERVED11[1U];\n  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */\n        uint32_t RESERVED12[1U];\n  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */\n        uint32_t RESERVED13[1U];\n  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */\n        uint32_t RESERVED14[1U];\n  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */\n        uint32_t RESERVED15[1U];\n  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */\n        uint32_t RESERVED16[1U];\n  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */\n        uint32_t RESERVED17[1U];\n  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */\n        uint32_t RESERVED18[1U];\n  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */\n        uint32_t RESERVED19[1U];\n  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */\n        uint32_t RESERVED20[1U];\n  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */\n        uint32_t RESERVED21[1U];\n  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */\n        uint32_t RESERVED22[1U];\n  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */\n        uint32_t RESERVED23[1U];\n  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */\n        uint32_t RESERVED24[1U];\n  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */\n        uint32_t RESERVED25[1U];\n  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */\n        uint32_t RESERVED26[1U];\n  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */\n        uint32_t RESERVED27[1U];\n  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */\n        uint32_t RESERVED28[1U];\n  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */\n        uint32_t RESERVED29[1U];\n  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */\n        uint32_t RESERVED30[1U];\n  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */\n        uint32_t RESERVED31[1U];\n  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */\n        uint32_t RESERVED32[934U];\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */\n        uint32_t RESERVED33[1U];\n  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */\n} DWT_Type;\n\n/* DWT Control Register Definitions */\n#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\n#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\n\n#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\n#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\n\n#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\n#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\n\n#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\n#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\n\n#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\n#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\n\n#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */\n#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */\n\n#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */\n#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */\n\n#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */\n#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */\n\n#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */\n#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */\n\n#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */\n#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */\n\n#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */\n#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */\n\n#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */\n#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */\n\n#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */\n#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */\n\n#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */\n#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */\n\n#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */\n#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */\n\n#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */\n#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */\n\n#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */\n#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */\n\n#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */\n#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */\n\n#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */\n#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */\n\n/* DWT CPI Count Register Definitions */\n#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */\n#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */\n\n/* DWT Exception Overhead Count Register Definitions */\n#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */\n#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */\n\n/* DWT Sleep Count Register Definitions */\n#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */\n#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */\n\n/* DWT LSU Count Register Definitions */\n#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */\n#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */\n\n/* DWT Folded-instruction Count Register Definitions */\n#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */\n#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */\n\n/* DWT Comparator Function Register Definitions */\n#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */\n#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */\n\n#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\n#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\n\n#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\n#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\n\n#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */\n#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */\n\n#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */\n#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */\n\n/*@}*/ /* end of group CMSIS_DWT */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_TPI     Trace Port Interface (TPI)\n  \\brief    Type definitions for the Trace Port Interface (TPI)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Trace Port Interface Register (TPI).\n */\ntypedef struct\n{\n  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Sizes Register */\n  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Sizes Register */\n        uint32_t RESERVED0[2U];\n  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\n        uint32_t RESERVED1[55U];\n  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\n        uint32_t RESERVED2[131U];\n  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\n  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\n  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */\n        uint32_t RESERVED3[759U];\n  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */\n  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */\n  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */\n        uint32_t RESERVED4[1U];\n  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */\n  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */\n  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */\n        uint32_t RESERVED5[39U];\n  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */\n  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */\n        uint32_t RESERVED7[8U];\n  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */\n  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */\n} TPI_Type;\n\n/* TPI Asynchronous Clock Prescaler Register Definitions */\n#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */\n#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */\n\n/* TPI Selected Pin Protocol Register Definitions */\n#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\n#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\n\n/* TPI Formatter and Flush Status Register Definitions */\n#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\n#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\n\n#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\n#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\n\n#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\n#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\n\n#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\n#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\n\n/* TPI Formatter and Flush Control Register Definitions */\n#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\n#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\n\n#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\n#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\n\n/* TPI TRIGGER Register Definitions */\n#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */\n#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */\n\n/* TPI Integration ETM Data Register Definitions (FIFO0) */\n#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */\n#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */\n\n#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */\n#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */\n\n#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */\n#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */\n\n#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */\n#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */\n\n#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */\n#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */\n\n#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */\n#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */\n\n#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */\n#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */\n\n/* TPI ITATBCTR2 Register Definitions */\n#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */\n#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */\n\n/* TPI Integration ITM Data Register Definitions (FIFO1) */\n#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */\n#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */\n\n#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */\n#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */\n\n#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */\n#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */\n\n#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */\n#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */\n\n#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */\n#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */\n\n#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */\n#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */\n\n#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */\n#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */\n\n/* TPI ITATBCTR0 Register Definitions */\n#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */\n#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */\n\n/* TPI Integration Mode Control Register Definitions */\n#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */\n#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */\n\n/* TPI DEVID Register Definitions */\n#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\n#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\n\n#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\n#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\n\n#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\n#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\n\n#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */\n#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */\n\n#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */\n#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */\n\n#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */\n#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */\n\n/* TPI DEVTYPE Register Definitions */\n#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */\n#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\n\n#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */\n#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\n\n/*@}*/ /* end of group CMSIS_TPI */\n\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\n */\ntypedef struct\n{\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\n  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */\n  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */\n  __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */\n  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */\n  __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */\n  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */\n  __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */\n        uint32_t RESERVED0[1];\n  union {\n  __IOM uint32_t MAIR[2];\n  struct {\n  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */\n  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */\n  };\n  };\n} MPU_Type;\n\n#define MPU_TYPE_RALIASES                  4U\n\n/* MPU Type Register Definitions */\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\n\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\n\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\n\n/* MPU Control Register Definitions */\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\n\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\n\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\n\n/* MPU Region Number Register Definitions */\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\n\n/* MPU Region Base Address Register Definitions */\n#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */\n#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */\n\n#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */\n#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */\n\n#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */\n#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */\n\n#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */\n#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */\n\n/* MPU Region Limit Address Register Definitions */\n#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */\n#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */\n\n#define MPU_RLAR_PXN_Pos                    4U                                            /*!< MPU RLAR: PXN Position */\n#define MPU_RLAR_PXN_Msk                   (0x1UL << MPU_RLAR_PXN_Pos)                    /*!< MPU RLAR: PXN Mask */\n\n#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */\n#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */\n\n#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */\n#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */\n\n/* MPU Memory Attribute Indirection Register 0 Definitions */\n#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */\n#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */\n\n#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */\n#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */\n\n#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */\n#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */\n\n#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */\n#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */\n\n/* MPU Memory Attribute Indirection Register 1 Definitions */\n#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */\n#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */\n\n#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */\n#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */\n\n#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */\n#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */\n\n#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */\n#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */\n\n/*@} end of group CMSIS_MPU */\n#endif\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SAU     Security Attribution Unit (SAU)\n  \\brief    Type definitions for the Security Attribution Unit (SAU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Security Attribution Unit (SAU).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */\n  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */\n#else\n        uint32_t RESERVED0[3];\n#endif\n  __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */\n  __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */\n} SAU_Type;\n\n/* SAU Control Register Definitions */\n#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */\n#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */\n\n#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */\n#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */\n\n/* SAU Type Register Definitions */\n#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */\n#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */\n\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n/* SAU Region Number Register Definitions */\n#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */\n#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */\n\n/* SAU Region Base Address Register Definitions */\n#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */\n#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */\n\n/* SAU Region Limit Address Register Definitions */\n#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */\n#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */\n\n#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */\n#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */\n\n#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */\n#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */\n\n#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\n\n/* Secure Fault Status Register Definitions */\n#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */\n#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */\n\n#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */\n#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */\n\n#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */\n#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */\n\n#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */\n#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */\n\n#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */\n#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */\n\n#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */\n#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */\n\n#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */\n#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */\n\n#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */\n#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */\n\n/*@} end of group CMSIS_SAU */\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_FPU     Floating Point Unit (FPU)\n  \\brief    Type definitions for the Floating Point Unit (FPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Floating Point Unit (FPU).\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1U];\n  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */\n  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */\n  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */\n  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */\n  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */\n} FPU_Type;\n\n/* Floating-Point Context Control Register Definitions */\n#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */\n#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */\n\n#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */\n#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */\n\n#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */\n#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */\n\n#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */\n#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */\n\n#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */\n#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */\n\n#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */\n#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */\n\n#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */\n#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */\n\n#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */\n#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */\n\n#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */\n#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */\n\n#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */\n#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */\n\n#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */\n#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */\n\n#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */\n#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */\n\n#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */\n#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */\n\n#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */\n#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */\n\n#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */\n#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */\n\n#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */\n#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */\n\n#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */\n#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */\n\n/* Floating-Point Context Address Register Definitions */\n#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */\n#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */\n\n/* Floating-Point Default Status Control Register Definitions */\n#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */\n#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */\n\n#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */\n#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */\n\n#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */\n#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */\n\n#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */\n#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */\n\n/* Media and FP Feature Register 0 Definitions */\n#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */\n#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */\n\n#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */\n#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */\n\n#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */\n#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */\n\n#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */\n#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */\n\n#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */\n#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */\n\n#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */\n#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */\n\n#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */\n#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */\n\n#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */\n#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */\n\n/* Media and FP Feature Register 1 Definitions */\n#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */\n#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */\n\n#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */\n#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */\n\n#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */\n#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */\n\n#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */\n#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */\n\n/*@} end of group CMSIS_FPU */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\n  \\brief    Type definitions for the Core Debug Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Core Debug Register (CoreDebug).\n */\ntypedef struct\n{\n  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\n  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\n  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\n  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\n        uint32_t RESERVED4[1U];\n  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */\n  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */\n} CoreDebug_Type;\n\n/* Debug Halting Control and Status Register Definitions */\n#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */\n#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\n\n#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */\n#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */\n\n#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */\n#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\n\n#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\n#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\n\n#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */\n#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\n\n#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */\n#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\n\n#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */\n#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\n\n#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */\n#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\n\n#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\n#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\n\n#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */\n#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\n\n#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */\n#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\n\n#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */\n#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\n\n#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */\n#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\n\n/* Debug Core Register Selector Register Definitions */\n#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */\n#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\n\n#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */\n#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */\n\n/* Debug Exception and Monitor Control Register Definitions */\n#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */\n#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */\n\n#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */\n#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */\n\n#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */\n#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */\n\n#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */\n#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */\n\n#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */\n#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */\n\n#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */\n#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\n\n#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */\n#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */\n\n#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */\n#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */\n\n#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */\n#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */\n\n#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */\n#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */\n\n#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */\n#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\n\n#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */\n#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */\n\n#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */\n#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */\n\n/* Debug Authentication Control Register Definitions */\n#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */\n#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */\n\n#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */\n#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */\n\n#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */\n#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */\n\n#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */\n#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */\n\n/* Debug Security Control and Status Register Definitions */\n#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */\n#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */\n\n#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */\n#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */\n\n#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */\n#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */\n\n/*@} end of group CMSIS_CoreDebug */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n/*@} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Core Hardware */\n  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */\n  #define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */\n  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */\n  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */\n  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */\n  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */\n  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */\n  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */\n\n  #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */\n  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */\n  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */\n  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */\n  #define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */\n  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */\n  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */\n  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */\n\n  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */\n    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */\n  #endif\n\n  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */\n    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */\n  #endif\n\n  #define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */\n  #define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */\n  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */\n  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */\n  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */\n  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */\n\n  #define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */\n  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */\n  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */\n  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */\n  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */\n\n  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */\n    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */\n  #endif\n\n  #define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */\n  #define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */\n\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n/*@} */\n\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Debug Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n#ifdef CMSIS_NVIC_VIRTUAL\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\n  #endif\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\n  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\n  #define NVIC_GetActive              __NVIC_GetActive\n  #define NVIC_SetPriority            __NVIC_SetPriority\n  #define NVIC_GetPriority            __NVIC_GetPriority\n  #define NVIC_SystemReset            __NVIC_SystemReset\n#endif /* CMSIS_NVIC_VIRTUAL */\n\n#ifdef CMSIS_VECTAB_VIRTUAL\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\n  #endif\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetVector              __NVIC_SetVector\n  #define NVIC_GetVector              __NVIC_GetVector\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\n\n#define NVIC_USER_IRQ_OFFSET          16\n\n\n\n/**\n  \\brief   Set Priority Grouping\n  \\details Sets the priority grouping field using the required unlock sequence.\n           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\n           Only values from 0..7 are used.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]      PriorityGroup  Priority grouping field.\n */\n__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\n{\n  uint32_t reg_value;\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\n\n  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */\n  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\n  reg_value  =  (reg_value                                   |\n                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */\n  SCB->AIRCR =  reg_value;\n}\n\n\n/**\n  \\brief   Get Priority Grouping\n  \\details Reads the priority grouping field from the NVIC Interrupt Controller.\n  \\return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\n{\n  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\n}\n\n\n/**\n  \\brief   Enable Interrupt\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __DSB();\n    __ISB();\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt\n  \\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Get Interrupt Target State\n  \\details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n  \\return             1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Target State\n  \\details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n                      1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Clear Interrupt Target State\n  \\details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n                      1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every processor exception.\n */\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n  else\n  {\n    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Encode Priority\n  \\details Encodes the priority for an interrupt with the given priority group,\n           preemptive priority value, and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\n */\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  return (\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\n         );\n}\n\n\n/**\n  \\brief   Decode Priority\n  \\details Decodes an interrupt priority value with a given priority group to\n           preemptive priority value and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\n */\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\n}\n\n\n/**\n  \\brief   Set Interrupt Vector\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n           VTOR must been relocated to SRAM before.\n  \\param [in]   IRQn      Interrupt number\n  \\param [in]   vector    Address of interrupt handler function\n */\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\n  __DSB();\n}\n\n\n/**\n  \\brief   Get Interrupt Vector\n  \\details Reads an interrupt vector from interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn      Interrupt number.\n  \\return                 Address of interrupt handler function\n */\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |\n                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\n                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Set Priority Grouping (non-secure)\n  \\details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.\n           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\n           Only values from 0..7 are used.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]      PriorityGroup  Priority grouping field.\n */\n__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)\n{\n  uint32_t reg_value;\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\n\n  reg_value  =  SCB_NS->AIRCR;                                                   /* read old register configuration    */\n  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */\n  reg_value  =  (reg_value                                   |\n                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */\n  SCB_NS->AIRCR =  reg_value;\n}\n\n\n/**\n  \\brief   Get Priority Grouping (non-secure)\n  \\details Reads the priority grouping field from the non-secure NVIC when in secure state.\n  \\return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)\n{\n  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\n}\n\n\n/**\n  \\brief   Enable Interrupt (non-secure)\n  \\details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status (non-secure)\n  \\details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt (non-secure)\n  \\details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt (non-secure)\n  \\details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt (non-secure)\n  \\details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt (non-secure)\n  \\details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt (non-secure)\n  \\details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Priority (non-secure)\n  \\details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every non-secure processor exception.\n */\n__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n  else\n  {\n    SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority (non-secure)\n  \\details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */\n\n/*@} end of CMSIS_Core_NVICFunctions */\n\n/* ##########################  MPU functions  #################################### */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n\n#include \"mpu_armv8.h\"\n\n#endif\n\n/* ##########################  FPU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\n  \\brief    Function that provides FPU type.\n  @{\n */\n\n/**\n  \\brief   get FPU type\n  \\details returns the FPU type\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n */\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\n{\n  uint32_t mvfr0;\n\n  mvfr0 = FPU->MVFR0;\n  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)\n  {\n    return 2U;           /* Double + Single precision FPU */\n  }\n  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)\n  {\n    return 1U;           /* Single precision FPU */\n  }\n  else\n  {\n    return 0U;           /* No FPU */\n  }\n}\n\n\n/*@} end of CMSIS_Core_FpuFunctions */\n\n\n\n/* ##########################   SAU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SAUFunctions SAU Functions\n  \\brief    Functions that configure the SAU.\n  @{\n */\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n\n/**\n  \\brief   Enable SAU\n  \\details Enables the Security Attribution Unit (SAU).\n */\n__STATIC_INLINE void TZ_SAU_Enable(void)\n{\n    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);\n}\n\n\n\n/**\n  \\brief   Disable SAU\n  \\details Disables the Security Attribution Unit (SAU).\n */\n__STATIC_INLINE void TZ_SAU_Disable(void)\n{\n    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);\n}\n\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n/*@} end of CMSIS_Core_SAUFunctions */\n\n\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   System Tick Configuration (non-secure)\n  \\details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n\n */\n__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                         /* Reload value impossible */\n  }\n\n  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */\n  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */\n  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                      SysTick_CTRL_TICKINT_Msk   |\n                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                           /* Function successful */\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n#endif\n\n/*@} end of CMSIS_Core_SysTickFunctions */\n\n\n\n/* ##################################### Debug In/Output function ########################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_core_DebugFunctions ITM Functions\n  \\brief    Functions that access the ITM debug interface.\n  @{\n */\n\nextern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */\n#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \\ref ITM_RxBuffer is ready for next character. */\n\n\n/**\n  \\brief   ITM Send Character\n  \\details Transmits a character via the ITM channel 0, and\n           \\li Just returns when no debugger is connected that has booked the output.\n           \\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\n  \\param [in]     ch  Character to transmit.\n  \\returns            Character to transmit.\n */\n__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\n{\n  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */\n      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */\n  {\n    while (ITM->PORT[0U].u32 == 0UL)\n    {\n      __NOP();\n    }\n    ITM->PORT[0U].u8 = (uint8_t)ch;\n  }\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Receive Character\n  \\details Inputs a character via the external variable \\ref ITM_RxBuffer.\n  \\return             Received character.\n  \\return         -1  No character pending.\n */\n__STATIC_INLINE int32_t ITM_ReceiveChar (void)\n{\n  int32_t ch = -1;                           /* no character available */\n\n  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\n  {\n    ch = ITM_RxBuffer;\n    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */\n  }\n\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Check Character\n  \\details Checks whether a character is pending for reading in the variable \\ref ITM_RxBuffer.\n  \\return          0  No character available.\n  \\return          1  Character available.\n */\n__STATIC_INLINE int32_t ITM_CheckChar (void)\n{\n\n  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\n  {\n    return (0);                              /* no character available */\n  }\n  else\n  {\n    return (1);                              /*    character available */\n  }\n}\n\n/*@} end of CMSIS_core_DebugFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_ARMV81MML_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n"
  },
  {
    "path": "3rd_party/CMSIS/Include/core_armv8mbl.h",
    "content": "/**************************************************************************//**\n * @file     core_armv8mbl.h\n * @brief    CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File\n * @version  V5.0.8\n * @date     12. November 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CORE_ARMV8MBL_H_GENERIC\n#define __CORE_ARMV8MBL_H_GENERIC\n\n#include <stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup Cortex_ARMv8MBL\n  @{\n */\n\n#include \"cmsis_version.h\"\n\n/*  CMSIS definitions */\n#define __ARMv8MBL_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \\deprecated [31:16] CMSIS HAL main version */\n#define __ARMv8MBL_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \\deprecated [15:0]  CMSIS HAL sub version */\n#define __ARMv8MBL_CMSIS_VERSION       ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \\\n                                         __ARMv8MBL_CMSIS_VERSION_SUB           )  /*!< \\deprecated CMSIS HAL version number */\n\n#define __CORTEX_M                     ( 2U)                                            /*!< Cortex-M Core */\n\n/** __FPU_USED indicates whether an FPU is used or not.\n    This core does not support an FPU at all\n*/\n#define __FPU_USED       0U\n\n#if defined ( __CC_ARM )\n  #if defined __TARGET_FPU_VFP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined __ARM_FP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined __ARMVFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TI_ARM__ )\n  #if defined __TI_VFP_SUPPORT__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined __FPU_VFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_ARMV8MBL_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_ARMV8MBL_H_DEPENDANT\n#define __CORE_ARMV8MBL_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __ARMv8MBL_REV\n    #define __ARMv8MBL_REV               0x0000U\n    #warning \"__ARMv8MBL_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __FPU_PRESENT\n    #define __FPU_PRESENT             0U\n    #warning \"__FPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __MPU_PRESENT\n    #define __MPU_PRESENT             0U\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __SAUREGION_PRESENT\n    #define __SAUREGION_PRESENT       0U\n    #warning \"__SAUREGION_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __VTOR_PRESENT\n    #define __VTOR_PRESENT            0U\n    #warning \"__VTOR_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          2U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __ETM_PRESENT\n    #define __ETM_PRESENT             0U\n    #warning \"__ETM_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __MTB_PRESENT\n    #define __MTB_PRESENT             0U\n    #warning \"__MTB_PRESENT not defined in device header file; using default!\"\n  #endif\n\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/*@} end of group ARMv8MBL */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core SCB Register\n  - Core SysTick Register\n  - Core Debug Register\n  - Core MPU Register\n  - Core SAU Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for Cortex-M processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\n    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */\n    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\n#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\n\n/*@} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[16U];\n  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RSERVED1[16U];\n  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[16U];\n  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[16U];\n  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\n        uint32_t RESERVED4[16U];\n  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */\n        uint32_t RESERVED5[16U];\n  __IOM uint32_t IPR[124U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */\n}  NVIC_Type;\n\n/*@} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\n#else\n        uint32_t RESERVED0;\n#endif\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n        uint32_t RESERVED1;\n  __IOM uint32_t SHPR[2U];               /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n} SCB_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */\n#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */\n\n#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */\n#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */\n\n#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */\n#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */\n#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\n#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n/* SCB Vector Table Offset Register Definitions */\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\n#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\n#endif\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */\n#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */\n\n#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */\n#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */\n\n#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */\n#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */\n#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */\n#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */\n\n#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */\n#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */\n\n#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */\n#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */\n\n#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */\n#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */\n\n#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\n#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\n\n#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\n#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\n#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */\n#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */\n\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\n#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\n\n#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\n#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\n\n#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\n#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\n\n#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */\n#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */\n\n#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */\n#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */\n\n/*@} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/*@} end of group CMSIS_SysTick */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\n  \\brief    Type definitions for the Data Watchpoint and Trace (DWT)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\n        uint32_t RESERVED0[6U];\n  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\n  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\n        uint32_t RESERVED1[1U];\n  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\n        uint32_t RESERVED2[1U];\n  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\n        uint32_t RESERVED3[1U];\n  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\n        uint32_t RESERVED4[1U];\n  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\n        uint32_t RESERVED5[1U];\n  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\n        uint32_t RESERVED6[1U];\n  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\n        uint32_t RESERVED7[1U];\n  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\n        uint32_t RESERVED8[1U];\n  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */\n        uint32_t RESERVED9[1U];\n  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */\n        uint32_t RESERVED10[1U];\n  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */\n        uint32_t RESERVED11[1U];\n  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */\n        uint32_t RESERVED12[1U];\n  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */\n        uint32_t RESERVED13[1U];\n  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */\n        uint32_t RESERVED14[1U];\n  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */\n        uint32_t RESERVED15[1U];\n  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */\n        uint32_t RESERVED16[1U];\n  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */\n        uint32_t RESERVED17[1U];\n  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */\n        uint32_t RESERVED18[1U];\n  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */\n        uint32_t RESERVED19[1U];\n  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */\n        uint32_t RESERVED20[1U];\n  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */\n        uint32_t RESERVED21[1U];\n  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */\n        uint32_t RESERVED22[1U];\n  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */\n        uint32_t RESERVED23[1U];\n  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */\n        uint32_t RESERVED24[1U];\n  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */\n        uint32_t RESERVED25[1U];\n  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */\n        uint32_t RESERVED26[1U];\n  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */\n        uint32_t RESERVED27[1U];\n  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */\n        uint32_t RESERVED28[1U];\n  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */\n        uint32_t RESERVED29[1U];\n  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */\n        uint32_t RESERVED30[1U];\n  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */\n        uint32_t RESERVED31[1U];\n  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */\n} DWT_Type;\n\n/* DWT Control Register Definitions */\n#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\n#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\n\n#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\n#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\n\n#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\n#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\n\n#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\n#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\n\n#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\n#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\n\n/* DWT Comparator Function Register Definitions */\n#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */\n#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */\n\n#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\n#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\n\n#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\n#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\n\n#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */\n#define DWT_FUNCTION_ACTION_Msk            (0x3UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */\n\n#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */\n#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */\n\n/*@}*/ /* end of group CMSIS_DWT */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_TPI     Trace Port Interface (TPI)\n  \\brief    Type definitions for the Trace Port Interface (TPI)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Trace Port Interface Register (TPI).\n */\ntypedef struct\n{\n  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Sizes Register */\n  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Sizes Register */\n        uint32_t RESERVED0[2U];\n  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\n        uint32_t RESERVED1[55U];\n  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\n        uint32_t RESERVED2[131U];\n  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\n  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\n  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */\n        uint32_t RESERVED3[809U];\n  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  Software Lock Access Register */\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  Software Lock Status Register */\n        uint32_t RESERVED4[4U];\n  __IM  uint32_t TYPE;                   /*!< Offset: 0xFC8 (R/ )  Device Identifier Register */\n  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Register */\n} TPI_Type;\n\n/* TPI Asynchronous Clock Prescaler Register Definitions */\n#define TPI_ACPR_SWOSCALER_Pos              0U                                         /*!< TPI ACPR: SWOSCALER Position */\n#define TPI_ACPR_SWOSCALER_Msk             (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)    /*!< TPI ACPR: SWOSCALER Mask */\n\n/* TPI Selected Pin Protocol Register Definitions */\n#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\n#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\n\n/* TPI Formatter and Flush Status Register Definitions */\n#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\n#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\n\n#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\n#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\n\n#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\n#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\n\n#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\n#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\n\n/* TPI Formatter and Flush Control Register Definitions */\n#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\n#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\n\n#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */\n#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */\n\n#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\n#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\n\n/* TPI Periodic Synchronization Control Register Definitions */\n#define TPI_PSCR_PSCount_Pos                0U                                         /*!< TPI PSCR: PSCount Position */\n#define TPI_PSCR_PSCount_Msk               (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)        /*!< TPI PSCR: TPSCount Mask */\n\n/* TPI Software Lock Status Register Definitions */\n#define TPI_LSR_nTT_Pos                     1U                                         /*!< TPI LSR: Not thirty-two bit. Position */\n#define TPI_LSR_nTT_Msk                    (0x1UL << TPI_LSR_nTT_Pos)                  /*!< TPI LSR: Not thirty-two bit. Mask */\n\n#define TPI_LSR_SLK_Pos                     1U                                         /*!< TPI LSR: Software Lock status Position */\n#define TPI_LSR_SLK_Msk                    (0x1UL << TPI_LSR_SLK_Pos)                  /*!< TPI LSR: Software Lock status Mask */\n\n#define TPI_LSR_SLI_Pos                     0U                                         /*!< TPI LSR: Software Lock implemented Position */\n#define TPI_LSR_SLI_Msk                    (0x1UL /*<< TPI_LSR_SLI_Pos*/)              /*!< TPI LSR: Software Lock implemented Mask */\n\n/* TPI DEVID Register Definitions */\n#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\n#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\n\n#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\n#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\n\n#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\n#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\n\n#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFO depth Position */\n#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFO depth Mask */\n\n/* TPI DEVTYPE Register Definitions */\n#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */\n#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\n\n#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */\n#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\n\n/*@}*/ /* end of group CMSIS_TPI */\n\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\n */\ntypedef struct\n{\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\n  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */\n        uint32_t RESERVED0[7U];\n  union {\n  __IOM uint32_t MAIR[2];\n  struct {\n  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */\n  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */\n  };\n  };\n} MPU_Type;\n\n#define MPU_TYPE_RALIASES                  1U\n\n/* MPU Type Register Definitions */\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\n\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\n\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\n\n/* MPU Control Register Definitions */\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\n\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\n\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\n\n/* MPU Region Number Register Definitions */\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\n\n/* MPU Region Base Address Register Definitions */\n#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */\n#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */\n\n#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */\n#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */\n\n#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */\n#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */\n\n#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */\n#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */\n\n/* MPU Region Limit Address Register Definitions */\n#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */\n#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */\n\n#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */\n#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */\n\n#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: EN Position */\n#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: EN Mask */\n\n/* MPU Memory Attribute Indirection Register 0 Definitions */\n#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */\n#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */\n\n#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */\n#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */\n\n#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */\n#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */\n\n#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */\n#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */\n\n/* MPU Memory Attribute Indirection Register 1 Definitions */\n#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */\n#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */\n\n#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */\n#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */\n\n#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */\n#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */\n\n#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */\n#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */\n\n/*@} end of group CMSIS_MPU */\n#endif\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SAU     Security Attribution Unit (SAU)\n  \\brief    Type definitions for the Security Attribution Unit (SAU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Security Attribution Unit (SAU).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */\n  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */\n#endif\n} SAU_Type;\n\n/* SAU Control Register Definitions */\n#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */\n#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */\n\n#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */\n#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */\n\n/* SAU Type Register Definitions */\n#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */\n#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */\n\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n/* SAU Region Number Register Definitions */\n#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */\n#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */\n\n/* SAU Region Base Address Register Definitions */\n#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */\n#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */\n\n/* SAU Region Limit Address Register Definitions */\n#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */\n#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */\n\n#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */\n#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */\n\n#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */\n#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */\n\n#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\n\n/*@} end of group CMSIS_SAU */\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\n  \\brief    Type definitions for the Core Debug Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Core Debug Register (CoreDebug).\n */\ntypedef struct\n{\n  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\n  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\n  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\n  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\n        uint32_t RESERVED4[1U];\n  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */\n  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */\n} CoreDebug_Type;\n\n/* Debug Halting Control and Status Register Definitions */\n#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */\n#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\n\n#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */\n#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */\n\n#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */\n#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\n\n#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\n#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\n\n#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */\n#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\n\n#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */\n#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\n\n#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */\n#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\n\n#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */\n#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\n\n#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */\n#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\n\n#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */\n#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\n\n#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */\n#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\n\n#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */\n#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\n\n/* Debug Core Register Selector Register Definitions */\n#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */\n#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\n\n#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */\n#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */\n\n/* Debug Exception and Monitor Control Register */\n#define CoreDebug_DEMCR_DWTENA_Pos         24U                                            /*!< CoreDebug DEMCR: DWTENA Position */\n#define CoreDebug_DEMCR_DWTENA_Msk         (1UL << CoreDebug_DEMCR_DWTENA_Pos)            /*!< CoreDebug DEMCR: DWTENA Mask */\n\n#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */\n#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\n\n#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */\n#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */\n\n/* Debug Authentication Control Register Definitions */\n#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */\n#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */\n\n#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */\n#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */\n\n#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */\n#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */\n\n#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */\n#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */\n\n/* Debug Security Control and Status Register Definitions */\n#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */\n#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */\n\n#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */\n#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */\n\n#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */\n#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */\n\n/*@} end of group CMSIS_CoreDebug */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n/*@} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Core Hardware */\n  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */\n  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */\n  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */\n  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */\n  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */\n  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */\n  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */\n\n\n  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */\n  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */\n  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */\n  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */\n  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */\n  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */\n\n  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */\n    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */\n  #endif\n\n  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */\n    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */\n  #endif\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */\n  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */\n  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */\n  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */\n  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */\n\n  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */\n  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */\n  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */\n  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */\n\n  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */\n    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */\n  #endif\n\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n/*@} */\n\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n#ifdef CMSIS_NVIC_VIRTUAL\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\n  #endif\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\n  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\n  #define NVIC_GetActive              __NVIC_GetActive\n  #define NVIC_SetPriority            __NVIC_SetPriority\n  #define NVIC_GetPriority            __NVIC_GetPriority\n  #define NVIC_SystemReset            __NVIC_SystemReset\n#endif /* CMSIS_NVIC_VIRTUAL */\n\n#ifdef CMSIS_VECTAB_VIRTUAL\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\n  #endif\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetVector              __NVIC_SetVector\n  #define NVIC_GetVector              __NVIC_GetVector\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\n\n#define NVIC_USER_IRQ_OFFSET          16\n\n\n/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */\n\n/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */\n#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */\n\n/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */\n#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */\n#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */\n#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */\n#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */\n#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */\n#define EXC_RETURN_SPSEL           (0x00000004UL)     /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP           */\n#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */\n\n/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */\n#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */\n#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */\n#else\n#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */\n#endif\n\n\n/* Interrupt Priorities are WORD accessible only under Armv6-M                  */\n/* The following MACROS handle generation of the register offset and byte masks */\n#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)\n#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )\n#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )\n\n#define __NVIC_SetPriorityGrouping(X) (void)(X)\n#define __NVIC_GetPriorityGrouping()  (0U)\n\n/**\n  \\brief   Enable Interrupt\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    __COMPILER_BARRIER();\n    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __COMPILER_BARRIER();\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __DSB();\n    __ISB();\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt\n  \\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Get Interrupt Target State\n  \\details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n  \\return             1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Target State\n  \\details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n                      1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Clear Interrupt Target State\n  \\details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n                      1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every processor exception.\n */\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n  else\n  {\n    SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Encode Priority\n  \\details Encodes the priority for an interrupt with the given priority group,\n           preemptive priority value, and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\n */\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  return (\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\n         );\n}\n\n\n/**\n  \\brief   Decode Priority\n  \\details Decodes an interrupt priority value with a given priority group to\n           preemptive priority value and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\n */\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\n}\n\n\n/**\n  \\brief   Set Interrupt Vector\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n           VTOR must been relocated to SRAM before.\n           If VTOR is not present address 0 must be mapped to SRAM.\n  \\param [in]   IRQn      Interrupt number\n  \\param [in]   vector    Address of interrupt handler function\n */\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\n{\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n#else\n  uint32_t *vectors = (uint32_t *)0x0U;\n#endif\n  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\n  __DSB();\n}\n\n\n/**\n  \\brief   Get Interrupt Vector\n  \\details Reads an interrupt vector from interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn      Interrupt number.\n  \\return                 Address of interrupt handler function\n */\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\n{\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n#else\n  uint32_t *vectors = (uint32_t *)0x0U;\n#endif\n  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                 SCB_AIRCR_SYSRESETREQ_Msk);\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Enable Interrupt (non-secure)\n  \\details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status (non-secure)\n  \\details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt (non-secure)\n  \\details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt (non-secure)\n  \\details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt (non-secure)\n  \\details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt (non-secure)\n  \\details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt (non-secure)\n  \\details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Priority (non-secure)\n  \\details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every non-secure processor exception.\n */\n__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n  else\n  {\n    SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority (non-secure)\n  \\details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */\n\n/*@} end of CMSIS_Core_NVICFunctions */\n\n/* ##########################  MPU functions  #################################### */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n\n#include \"mpu_armv8.h\"\n\n#endif\n\n/* ##########################  FPU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\n  \\brief    Function that provides FPU type.\n  @{\n */\n\n/**\n  \\brief   get FPU type\n  \\details returns the FPU type\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n */\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\n{\n    return 0U;           /* No FPU */\n}\n\n\n/*@} end of CMSIS_Core_FpuFunctions */\n\n\n\n/* ##########################   SAU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SAUFunctions SAU Functions\n  \\brief    Functions that configure the SAU.\n  @{\n */\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n\n/**\n  \\brief   Enable SAU\n  \\details Enables the Security Attribution Unit (SAU).\n */\n__STATIC_INLINE void TZ_SAU_Enable(void)\n{\n    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);\n}\n\n\n\n/**\n  \\brief   Disable SAU\n  \\details Disables the Security Attribution Unit (SAU).\n */\n__STATIC_INLINE void TZ_SAU_Disable(void)\n{\n    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);\n}\n\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n/*@} end of CMSIS_Core_SAUFunctions */\n\n\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   System Tick Configuration (non-secure)\n  \\details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n\n */\n__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                         /* Reload value impossible */\n  }\n\n  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */\n  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */\n  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                      SysTick_CTRL_TICKINT_Msk   |\n                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                           /* Function successful */\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n#endif\n\n/*@} end of CMSIS_Core_SysTickFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_ARMV8MBL_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n"
  },
  {
    "path": "3rd_party/CMSIS/Include/core_armv8mml.h",
    "content": "/**************************************************************************//**\n * @file     core_armv8mml.h\n * @brief    CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File\n * @version  V5.1.0\n * @date     12. September 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CORE_ARMV8MML_H_GENERIC\n#define __CORE_ARMV8MML_H_GENERIC\n\n#include <stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup Cortex_ARMv8MML\n  @{\n */\n\n#include \"cmsis_version.h\"\n\n/*  CMSIS Armv8MML definitions */\n#define __ARMv8MML_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \\deprecated [31:16] CMSIS HAL main version */\n#define __ARMv8MML_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \\deprecated [15:0]  CMSIS HAL sub version */\n#define __ARMv8MML_CMSIS_VERSION       ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \\\n                                         __ARMv8MML_CMSIS_VERSION_SUB           )  /*!< \\deprecated CMSIS HAL version number */\n\n#define __CORTEX_M                     (81U)                                       /*!< Cortex-M Core */\n\n/** __FPU_USED indicates whether an FPU is used or not.\n    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\n*/\n#if defined ( __CC_ARM )\n  #if defined __TARGET_FPU_VFP\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined(__ARM_FEATURE_DSP)\n    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED         0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined __ARM_FP\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #warning \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined(__ARM_FEATURE_DSP)\n    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED         0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined(__ARM_FEATURE_DSP)\n    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED         0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined __ARMVFP__\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined(__ARM_FEATURE_DSP)\n    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED         0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined ( __TI_ARM__ )\n  #if defined __TI_VFP_SUPPORT__\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined __FPU_VFP__\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_ARMV8MML_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_ARMV8MML_H_DEPENDANT\n#define __CORE_ARMV8MML_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __ARMv8MML_REV\n    #define __ARMv8MML_REV               0x0000U\n    #warning \"__ARMv8MML_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __FPU_PRESENT\n    #define __FPU_PRESENT             0U\n    #warning \"__FPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __MPU_PRESENT\n    #define __MPU_PRESENT             0U\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __SAUREGION_PRESENT\n    #define __SAUREGION_PRESENT       0U\n    #warning \"__SAUREGION_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __DSP_PRESENT\n    #define __DSP_PRESENT             0U\n    #warning \"__DSP_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          3U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/*@} end of group ARMv8MML */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core SCB Register\n  - Core SysTick Register\n  - Core Debug Register\n  - Core MPU Register\n  - Core SAU Register\n  - Core FPU Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for Cortex-M processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */\n    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\n    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */\n#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */\n\n#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */\n#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */\n    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\n    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\n    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */\n#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */\n\n#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */\n#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */\n#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */\n    uint32_t FPCA:1;                     /*!< bit:      2  Floating-point context active */\n    uint32_t SFPA:1;                     /*!< bit:      3  Secure floating-point active */\n    uint32_t _reserved1:28;              /*!< bit:  4..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */\n#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */\n\n#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */\n#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */\n\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\n#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\n\n/*@} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[16U];\n  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RSERVED1[16U];\n  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[16U];\n  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[16U];\n  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\n        uint32_t RESERVED4[16U];\n  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */\n        uint32_t RESERVED5[16U];\n  __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */\n        uint32_t RESERVED6[580U];\n  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */\n}  NVIC_Type;\n\n/* Software Triggered Interrupt Register Definitions */\n#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */\n#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */\n\n/*@} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */\n  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */\n  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */\n  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */\n  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */\n  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */\n  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */\n  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */\n  __IM  uint32_t ID_ADR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */\n  __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */\n  __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */\n  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */\n  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */\n  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */\n  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */\n  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */\n  __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */\n        uint32_t RESERVED3[92U];\n  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */\n        uint32_t RESERVED4[15U];\n  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */\n  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */\n  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */\n        uint32_t RESERVED5[1U];\n  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */\n        uint32_t RESERVED6[1U];\n  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */\n  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */\n  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */\n  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */\n  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */\n  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */\n  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */\n  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */\n} SCB_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */\n#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */\n\n#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */\n#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */\n\n#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */\n#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */\n#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\n#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n/* SCB Vector Table Offset Register Definitions */\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\n#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */\n#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */\n\n#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */\n#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */\n\n#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */\n#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */\n\n#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */\n#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */\n#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */\n#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */\n\n#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */\n#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */\n\n#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */\n#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */\n\n#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */\n#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */\n\n#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\n#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\n\n#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\n#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\n#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */\n#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */\n\n#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */\n#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */\n\n#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */\n#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */\n\n#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */\n#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */\n\n#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */\n#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */\n\n#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */\n#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */\n\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */\n#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */\n\n#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */\n#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */\n\n#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */\n#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */\n\n#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\n#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\n\n#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\n#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\n\n#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */\n#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */\n\n#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\n#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\n\n#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */\n#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */\n\n#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */\n#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */\n\n#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */\n#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */\n\n#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */\n#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */\n\n#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */\n#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */\n\n#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */\n#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */\n\n/* SCB Configurable Fault Status Register Definitions */\n#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */\n#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */\n\n#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */\n#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */\n\n#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */\n#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\n\n/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */\n#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */\n\n#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */\n#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */\n\n#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */\n#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */\n\n#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\n#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\n\n#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */\n#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\n\n#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */\n#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\n\n/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */\n#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */\n\n#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */\n#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */\n\n#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */\n#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */\n\n#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */\n#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */\n\n#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */\n#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\n\n#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */\n#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */\n\n#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */\n#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */\n\n/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */\n#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\n\n#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */\n#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */\n\n#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */\n#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */\n\n#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */\n#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */\n\n#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */\n#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */\n\n#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */\n#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */\n\n#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\n#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\n\n/* SCB Hard Fault Status Register Definitions */\n#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */\n#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */\n\n#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */\n#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */\n\n#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */\n#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */\n\n/* SCB Debug Fault Status Register Definitions */\n#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */\n#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */\n\n#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */\n#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */\n\n#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */\n#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */\n\n#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */\n#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */\n\n#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */\n#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */\n\n/* SCB Non-Secure Access Control Register Definitions */\n#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */\n#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */\n\n#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */\n#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */\n\n#define SCB_NSACR_CPn_Pos                   0U                                            /*!< SCB NSACR: CPn Position */\n#define SCB_NSACR_CPn_Msk                  (1UL /*<< SCB_NSACR_CPn_Pos*/)                 /*!< SCB NSACR: CPn Mask */\n\n/* SCB Cache Level ID Register Definitions */\n#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */\n#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */\n\n#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */\n#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */\n\n/* SCB Cache Type Register Definitions */\n#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */\n#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */\n\n#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */\n#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */\n\n#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */\n#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */\n\n#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */\n#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */\n\n#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */\n#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */\n\n/* SCB Cache Size ID Register Definitions */\n#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */\n#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */\n\n#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */\n#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */\n\n#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */\n#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */\n\n#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */\n#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */\n\n#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */\n#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */\n\n#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */\n#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */\n\n#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */\n#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */\n\n/* SCB Cache Size Selection Register Definitions */\n#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */\n#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */\n\n#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */\n#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */\n\n/* SCB Software Triggered Interrupt Register Definitions */\n#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */\n#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */\n\n/* SCB D-Cache Invalidate by Set-way Register Definitions */\n#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */\n#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */\n\n#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */\n#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */\n\n/* SCB D-Cache Clean by Set-way Register Definitions */\n#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */\n#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */\n\n#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */\n#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */\n\n/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */\n#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */\n#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */\n\n#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */\n#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */\n\n/*@} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\n  \\brief    Type definitions for the System Control and ID Register not in the SCB\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control and ID Register not in the SCB.\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1U];\n  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */\n  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\n  __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */\n} SCnSCB_Type;\n\n/* Interrupt Controller Type Register Definitions */\n#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */\n#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */\n\n/*@} end of group CMSIS_SCnotSCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/*@} end of group CMSIS_SysTick */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)\n  \\brief    Type definitions for the Instrumentation Trace Macrocell (ITM)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).\n */\ntypedef struct\n{\n  __OM  union\n  {\n    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */\n    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */\n    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */\n  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */\n        uint32_t RESERVED0[864U];\n  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */\n        uint32_t RESERVED1[15U];\n  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */\n        uint32_t RESERVED2[15U];\n  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */\n        uint32_t RESERVED3[32U];\n        uint32_t RESERVED4[43U];\n  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */\n        uint32_t RESERVED5[1U];\n  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */\n        uint32_t RESERVED6[4U];\n  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */\n  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */\n  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */\n  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */\n  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */\n  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */\n  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */\n  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */\n  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */\n  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */\n  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */\n  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */\n} ITM_Type;\n\n/* ITM Stimulus Port Register Definitions */\n#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */\n#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */\n\n#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */\n#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */\n\n/* ITM Trace Privilege Register Definitions */\n#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */\n#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */\n\n/* ITM Trace Control Register Definitions */\n#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */\n#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */\n\n#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */\n#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */\n\n#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */\n#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */\n\n#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */\n#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */\n\n#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */\n#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */\n\n#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */\n#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */\n\n#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */\n#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */\n\n#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */\n#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */\n\n#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */\n#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */\n\n#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */\n#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */\n\n/* ITM Lock Status Register Definitions */\n#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */\n#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */\n\n#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */\n#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */\n\n#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */\n#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */\n\n/*@}*/ /* end of group CMSIS_ITM */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\n  \\brief    Type definitions for the Data Watchpoint and Trace (DWT)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\n  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */\n  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */\n  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */\n  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */\n  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */\n  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */\n  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\n  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\n        uint32_t RESERVED1[1U];\n  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\n        uint32_t RESERVED2[1U];\n  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\n        uint32_t RESERVED3[1U];\n  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\n        uint32_t RESERVED4[1U];\n  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\n        uint32_t RESERVED5[1U];\n  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\n        uint32_t RESERVED6[1U];\n  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\n        uint32_t RESERVED7[1U];\n  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\n        uint32_t RESERVED8[1U];\n  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */\n        uint32_t RESERVED9[1U];\n  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */\n        uint32_t RESERVED10[1U];\n  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */\n        uint32_t RESERVED11[1U];\n  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */\n        uint32_t RESERVED12[1U];\n  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */\n        uint32_t RESERVED13[1U];\n  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */\n        uint32_t RESERVED14[1U];\n  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */\n        uint32_t RESERVED15[1U];\n  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */\n        uint32_t RESERVED16[1U];\n  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */\n        uint32_t RESERVED17[1U];\n  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */\n        uint32_t RESERVED18[1U];\n  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */\n        uint32_t RESERVED19[1U];\n  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */\n        uint32_t RESERVED20[1U];\n  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */\n        uint32_t RESERVED21[1U];\n  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */\n        uint32_t RESERVED22[1U];\n  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */\n        uint32_t RESERVED23[1U];\n  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */\n        uint32_t RESERVED24[1U];\n  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */\n        uint32_t RESERVED25[1U];\n  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */\n        uint32_t RESERVED26[1U];\n  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */\n        uint32_t RESERVED27[1U];\n  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */\n        uint32_t RESERVED28[1U];\n  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */\n        uint32_t RESERVED29[1U];\n  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */\n        uint32_t RESERVED30[1U];\n  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */\n        uint32_t RESERVED31[1U];\n  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */\n        uint32_t RESERVED32[934U];\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */\n        uint32_t RESERVED33[1U];\n  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */\n} DWT_Type;\n\n/* DWT Control Register Definitions */\n#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\n#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\n\n#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\n#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\n\n#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\n#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\n\n#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\n#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\n\n#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\n#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\n\n#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */\n#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */\n\n#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */\n#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */\n\n#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */\n#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */\n\n#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */\n#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */\n\n#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */\n#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */\n\n#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */\n#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */\n\n#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */\n#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */\n\n#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */\n#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */\n\n#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */\n#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */\n\n#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */\n#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */\n\n#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */\n#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */\n\n#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */\n#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */\n\n#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */\n#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */\n\n#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */\n#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */\n\n/* DWT CPI Count Register Definitions */\n#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */\n#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */\n\n/* DWT Exception Overhead Count Register Definitions */\n#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */\n#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */\n\n/* DWT Sleep Count Register Definitions */\n#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */\n#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */\n\n/* DWT LSU Count Register Definitions */\n#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */\n#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */\n\n/* DWT Folded-instruction Count Register Definitions */\n#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */\n#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */\n\n/* DWT Comparator Function Register Definitions */\n#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */\n#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */\n\n#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\n#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\n\n#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\n#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\n\n#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */\n#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */\n\n#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */\n#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */\n\n/*@}*/ /* end of group CMSIS_DWT */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_TPI     Trace Port Interface (TPI)\n  \\brief    Type definitions for the Trace Port Interface (TPI)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Trace Port Interface Register (TPI).\n */\ntypedef struct\n{\n  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Sizes Register */\n  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Sizes Register */\n        uint32_t RESERVED0[2U];\n  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\n        uint32_t RESERVED1[55U];\n  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\n        uint32_t RESERVED2[131U];\n  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\n  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\n  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */\n        uint32_t RESERVED3[809U];\n  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  Software Lock Access Register */\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  Software Lock Status Register */\n        uint32_t RESERVED4[4U];\n  __IM  uint32_t TYPE;                   /*!< Offset: 0xFC8 (R/ )  Device Identifier Register */\n  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Register */\n} TPI_Type;\n\n/* TPI Asynchronous Clock Prescaler Register Definitions */\n#define TPI_ACPR_SWOSCALER_Pos              0U                                         /*!< TPI ACPR: SWOSCALER Position */\n#define TPI_ACPR_SWOSCALER_Msk             (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)    /*!< TPI ACPR: SWOSCALER Mask */\n\n/* TPI Selected Pin Protocol Register Definitions */\n#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\n#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\n\n/* TPI Formatter and Flush Status Register Definitions */\n#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\n#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\n\n#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\n#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\n\n#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\n#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\n\n#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\n#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\n\n/* TPI Formatter and Flush Control Register Definitions */\n#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\n#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\n\n#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */\n#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */\n\n#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\n#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\n\n/* TPI Periodic Synchronization Control Register Definitions */\n#define TPI_PSCR_PSCount_Pos                0U                                         /*!< TPI PSCR: PSCount Position */\n#define TPI_PSCR_PSCount_Msk               (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)        /*!< TPI PSCR: TPSCount Mask */\n\n/* TPI Software Lock Status Register Definitions */\n#define TPI_LSR_nTT_Pos                     1U                                         /*!< TPI LSR: Not thirty-two bit. Position */\n#define TPI_LSR_nTT_Msk                    (0x1UL << TPI_LSR_nTT_Pos)                  /*!< TPI LSR: Not thirty-two bit. Mask */\n\n#define TPI_LSR_SLK_Pos                     1U                                         /*!< TPI LSR: Software Lock status Position */\n#define TPI_LSR_SLK_Msk                    (0x1UL << TPI_LSR_SLK_Pos)                  /*!< TPI LSR: Software Lock status Mask */\n\n#define TPI_LSR_SLI_Pos                     0U                                         /*!< TPI LSR: Software Lock implemented Position */\n#define TPI_LSR_SLI_Msk                    (0x1UL /*<< TPI_LSR_SLI_Pos*/)              /*!< TPI LSR: Software Lock implemented Mask */\n\n/* TPI DEVID Register Definitions */\n#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\n#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\n\n#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\n#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\n\n#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\n#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\n\n#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFO depth Position */\n#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFO depth Mask */\n\n/* TPI DEVTYPE Register Definitions */\n#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */\n#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\n\n#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */\n#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\n\n/*@}*/ /* end of group CMSIS_TPI */\n\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\n */\ntypedef struct\n{\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\n  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */\n  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */\n  __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */\n  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */\n  __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */\n  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */\n  __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */\n        uint32_t RESERVED0[1];\n  union {\n  __IOM uint32_t MAIR[2];\n  struct {\n  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */\n  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */\n  };\n  };\n} MPU_Type;\n\n#define MPU_TYPE_RALIASES                  4U\n\n/* MPU Type Register Definitions */\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\n\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\n\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\n\n/* MPU Control Register Definitions */\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\n\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\n\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\n\n/* MPU Region Number Register Definitions */\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\n\n/* MPU Region Base Address Register Definitions */\n#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */\n#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */\n\n#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */\n#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */\n\n#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */\n#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */\n\n#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */\n#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */\n\n/* MPU Region Limit Address Register Definitions */\n#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */\n#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */\n\n#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */\n#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */\n\n#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */\n#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */\n\n/* MPU Memory Attribute Indirection Register 0 Definitions */\n#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */\n#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */\n\n#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */\n#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */\n\n#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */\n#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */\n\n#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */\n#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */\n\n/* MPU Memory Attribute Indirection Register 1 Definitions */\n#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */\n#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */\n\n#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */\n#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */\n\n#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */\n#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */\n\n#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */\n#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */\n\n/*@} end of group CMSIS_MPU */\n#endif\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SAU     Security Attribution Unit (SAU)\n  \\brief    Type definitions for the Security Attribution Unit (SAU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Security Attribution Unit (SAU).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */\n  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */\n#else\n        uint32_t RESERVED0[3];\n#endif\n  __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */\n  __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */\n} SAU_Type;\n\n/* SAU Control Register Definitions */\n#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */\n#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */\n\n#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */\n#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */\n\n/* SAU Type Register Definitions */\n#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */\n#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */\n\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n/* SAU Region Number Register Definitions */\n#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */\n#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */\n\n/* SAU Region Base Address Register Definitions */\n#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */\n#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */\n\n/* SAU Region Limit Address Register Definitions */\n#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */\n#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */\n\n#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */\n#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */\n\n#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */\n#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */\n\n#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\n\n/* Secure Fault Status Register Definitions */\n#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */\n#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */\n\n#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */\n#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */\n\n#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */\n#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */\n\n#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */\n#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */\n\n#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */\n#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */\n\n#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */\n#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */\n\n#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */\n#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */\n\n#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */\n#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */\n\n/*@} end of group CMSIS_SAU */\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_FPU     Floating Point Unit (FPU)\n  \\brief    Type definitions for the Floating Point Unit (FPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Floating Point Unit (FPU).\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1U];\n  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */\n  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */\n  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */\n  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */\n  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */\n} FPU_Type;\n\n/* Floating-Point Context Control Register Definitions */\n#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */\n#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */\n\n#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */\n#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */\n\n#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */\n#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */\n\n#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */\n#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */\n\n#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */\n#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */\n\n#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */\n#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */\n\n#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */\n#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */\n\n#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */\n#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */\n\n#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */\n#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */\n\n#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */\n#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */\n\n#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */\n#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */\n\n#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */\n#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */\n\n#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */\n#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */\n\n#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */\n#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */\n\n#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */\n#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */\n\n#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */\n#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */\n\n#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */\n#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */\n\n/* Floating-Point Context Address Register Definitions */\n#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */\n#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */\n\n/* Floating-Point Default Status Control Register Definitions */\n#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */\n#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */\n\n#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */\n#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */\n\n#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */\n#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */\n\n#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */\n#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */\n\n/* Media and FP Feature Register 0 Definitions */\n#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */\n#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */\n\n#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */\n#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */\n\n#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */\n#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */\n\n#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */\n#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */\n\n#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */\n#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */\n\n#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */\n#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */\n\n#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */\n#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */\n\n#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */\n#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */\n\n/* Media and FP Feature Register 1 Definitions */\n#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */\n#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */\n\n#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */\n#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */\n\n#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */\n#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */\n\n#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */\n#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */\n\n/*@} end of group CMSIS_FPU */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\n  \\brief    Type definitions for the Core Debug Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Core Debug Register (CoreDebug).\n */\ntypedef struct\n{\n  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\n  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\n  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\n  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\n        uint32_t RESERVED4[1U];\n  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */\n  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */\n} CoreDebug_Type;\n\n/* Debug Halting Control and Status Register Definitions */\n#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */\n#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\n\n#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */\n#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */\n\n#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */\n#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\n\n#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\n#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\n\n#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */\n#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\n\n#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */\n#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\n\n#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */\n#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\n\n#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */\n#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\n\n#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\n#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\n\n#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */\n#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\n\n#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */\n#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\n\n#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */\n#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\n\n#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */\n#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\n\n/* Debug Core Register Selector Register Definitions */\n#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */\n#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\n\n#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */\n#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */\n\n/* Debug Exception and Monitor Control Register Definitions */\n#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */\n#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */\n\n#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */\n#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */\n\n#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */\n#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */\n\n#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */\n#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */\n\n#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */\n#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */\n\n#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */\n#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\n\n#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */\n#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */\n\n#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */\n#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */\n\n#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */\n#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */\n\n#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */\n#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */\n\n#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */\n#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\n\n#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */\n#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */\n\n#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */\n#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */\n\n/* Debug Authentication Control Register Definitions */\n#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */\n#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */\n\n#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */\n#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */\n\n#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */\n#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */\n\n#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */\n#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */\n\n/* Debug Security Control and Status Register Definitions */\n#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */\n#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */\n\n#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */\n#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */\n\n#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */\n#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */\n\n/*@} end of group CMSIS_CoreDebug */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n/*@} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Core Hardware */\n  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */\n  #define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */\n  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */\n  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */\n  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */\n  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */\n  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */\n  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */\n\n  #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */\n  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */\n  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */\n  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */\n  #define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */\n  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */\n  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */\n  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */\n\n  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */\n    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */\n  #endif\n\n  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */\n    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */\n  #endif\n\n  #define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */\n  #define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */\n  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */\n  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */\n  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */\n  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */\n\n  #define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */\n  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */\n  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */\n  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */\n  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */\n\n  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */\n    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */\n  #endif\n\n  #define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */\n  #define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */\n\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n/*@} */\n\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Debug Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n#ifdef CMSIS_NVIC_VIRTUAL\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\n  #endif\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\n  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\n  #define NVIC_GetActive              __NVIC_GetActive\n  #define NVIC_SetPriority            __NVIC_SetPriority\n  #define NVIC_GetPriority            __NVIC_GetPriority\n  #define NVIC_SystemReset            __NVIC_SystemReset\n#endif /* CMSIS_NVIC_VIRTUAL */\n\n#ifdef CMSIS_VECTAB_VIRTUAL\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\n  #endif\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetVector              __NVIC_SetVector\n  #define NVIC_GetVector              __NVIC_GetVector\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\n\n#define NVIC_USER_IRQ_OFFSET          16\n\n\n/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */\n\n/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */\n#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */\n\n/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */\n#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */\n#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */\n#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */\n#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */\n#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */\n#define EXC_RETURN_SPSEL           (0x00000004UL)     /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP           */\n#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */\n\n/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */\n#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */\n#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */\n#else\n#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */\n#endif\n\n\n/**\n  \\brief   Set Priority Grouping\n  \\details Sets the priority grouping field using the required unlock sequence.\n           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\n           Only values from 0..7 are used.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]      PriorityGroup  Priority grouping field.\n */\n__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\n{\n  uint32_t reg_value;\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\n\n  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */\n  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\n  reg_value  =  (reg_value                                   |\n                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */\n  SCB->AIRCR =  reg_value;\n}\n\n\n/**\n  \\brief   Get Priority Grouping\n  \\details Reads the priority grouping field from the NVIC Interrupt Controller.\n  \\return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\n{\n  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\n}\n\n\n/**\n  \\brief   Enable Interrupt\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    __COMPILER_BARRIER();\n    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __COMPILER_BARRIER();\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __DSB();\n    __ISB();\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt\n  \\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Get Interrupt Target State\n  \\details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n  \\return             1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Target State\n  \\details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n                      1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Clear Interrupt Target State\n  \\details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n                      1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every processor exception.\n */\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n  else\n  {\n    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Encode Priority\n  \\details Encodes the priority for an interrupt with the given priority group,\n           preemptive priority value, and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\n */\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  return (\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\n         );\n}\n\n\n/**\n  \\brief   Decode Priority\n  \\details Decodes an interrupt priority value with a given priority group to\n           preemptive priority value and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\n */\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\n}\n\n\n/**\n  \\brief   Set Interrupt Vector\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n           VTOR must been relocated to SRAM before.\n  \\param [in]   IRQn      Interrupt number\n  \\param [in]   vector    Address of interrupt handler function\n */\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\n  __DSB();\n}\n\n\n/**\n  \\brief   Get Interrupt Vector\n  \\details Reads an interrupt vector from interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn      Interrupt number.\n  \\return                 Address of interrupt handler function\n */\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |\n                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\n                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Set Priority Grouping (non-secure)\n  \\details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.\n           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\n           Only values from 0..7 are used.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]      PriorityGroup  Priority grouping field.\n */\n__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)\n{\n  uint32_t reg_value;\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\n\n  reg_value  =  SCB_NS->AIRCR;                                                   /* read old register configuration    */\n  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */\n  reg_value  =  (reg_value                                   |\n                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)                      );              /* Insert write key and priority group */\n  SCB_NS->AIRCR =  reg_value;\n}\n\n\n/**\n  \\brief   Get Priority Grouping (non-secure)\n  \\details Reads the priority grouping field from the non-secure NVIC when in secure state.\n  \\return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)\n{\n  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\n}\n\n\n/**\n  \\brief   Enable Interrupt (non-secure)\n  \\details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status (non-secure)\n  \\details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt (non-secure)\n  \\details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt (non-secure)\n  \\details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt (non-secure)\n  \\details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt (non-secure)\n  \\details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt (non-secure)\n  \\details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Priority (non-secure)\n  \\details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every non-secure processor exception.\n */\n__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n  else\n  {\n    SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority (non-secure)\n  \\details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */\n\n/*@} end of CMSIS_Core_NVICFunctions */\n\n/* ##########################  MPU functions  #################################### */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n\n#include \"mpu_armv8.h\"\n\n#endif\n\n/* ##########################  FPU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\n  \\brief    Function that provides FPU type.\n  @{\n */\n\n/**\n  \\brief   get FPU type\n  \\details returns the FPU type\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n */\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\n{\n  uint32_t mvfr0;\n\n  mvfr0 = FPU->MVFR0;\n  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)\n  {\n    return 2U;           /* Double + Single precision FPU */\n  }\n  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)\n  {\n    return 1U;           /* Single precision FPU */\n  }\n  else\n  {\n    return 0U;           /* No FPU */\n  }\n}\n\n\n/*@} end of CMSIS_Core_FpuFunctions */\n\n\n\n/* ##########################   SAU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SAUFunctions SAU Functions\n  \\brief    Functions that configure the SAU.\n  @{\n */\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n\n/**\n  \\brief   Enable SAU\n  \\details Enables the Security Attribution Unit (SAU).\n */\n__STATIC_INLINE void TZ_SAU_Enable(void)\n{\n    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);\n}\n\n\n\n/**\n  \\brief   Disable SAU\n  \\details Disables the Security Attribution Unit (SAU).\n */\n__STATIC_INLINE void TZ_SAU_Disable(void)\n{\n    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);\n}\n\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n/*@} end of CMSIS_Core_SAUFunctions */\n\n\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   System Tick Configuration (non-secure)\n  \\details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n\n */\n__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                         /* Reload value impossible */\n  }\n\n  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */\n  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */\n  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                      SysTick_CTRL_TICKINT_Msk   |\n                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                           /* Function successful */\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n#endif\n\n/*@} end of CMSIS_Core_SysTickFunctions */\n\n\n\n/* ##################################### Debug In/Output function ########################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_core_DebugFunctions ITM Functions\n  \\brief    Functions that access the ITM debug interface.\n  @{\n */\n\nextern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */\n#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \\ref ITM_RxBuffer is ready for next character. */\n\n\n/**\n  \\brief   ITM Send Character\n  \\details Transmits a character via the ITM channel 0, and\n           \\li Just returns when no debugger is connected that has booked the output.\n           \\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\n  \\param [in]     ch  Character to transmit.\n  \\returns            Character to transmit.\n */\n__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\n{\n  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */\n      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */\n  {\n    while (ITM->PORT[0U].u32 == 0UL)\n    {\n      __NOP();\n    }\n    ITM->PORT[0U].u8 = (uint8_t)ch;\n  }\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Receive Character\n  \\details Inputs a character via the external variable \\ref ITM_RxBuffer.\n  \\return             Received character.\n  \\return         -1  No character pending.\n */\n__STATIC_INLINE int32_t ITM_ReceiveChar (void)\n{\n  int32_t ch = -1;                           /* no character available */\n\n  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\n  {\n    ch = ITM_RxBuffer;\n    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */\n  }\n\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Check Character\n  \\details Checks whether a character is pending for reading in the variable \\ref ITM_RxBuffer.\n  \\return          0  No character available.\n  \\return          1  Character available.\n */\n__STATIC_INLINE int32_t ITM_CheckChar (void)\n{\n\n  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\n  {\n    return (0);                              /* no character available */\n  }\n  else\n  {\n    return (1);                              /*    character available */\n  }\n}\n\n/*@} end of CMSIS_core_DebugFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_ARMV8MML_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n"
  },
  {
    "path": "3rd_party/CMSIS/Include/core_cm0.h",
    "content": "/**************************************************************************//**\n * @file     core_cm0.h\n * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File\n * @version  V5.0.6\n * @date     13. March 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CORE_CM0_H_GENERIC\n#define __CORE_CM0_H_GENERIC\n\n#include <stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup Cortex_M0\n  @{\n */\n\n#include \"cmsis_version.h\"\n\n/*  CMSIS CM0 definitions */\n#define __CM0_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \\deprecated [31:16] CMSIS HAL main version */\n#define __CM0_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \\deprecated [15:0]  CMSIS HAL sub version */\n#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16U) | \\\n                                    __CM0_CMSIS_VERSION_SUB           )  /*!< \\deprecated CMSIS HAL version number */\n\n#define __CORTEX_M                (0U)                                   /*!< Cortex-M Core */\n\n/** __FPU_USED indicates whether an FPU is used or not.\n    This core does not support an FPU at all\n*/\n#define __FPU_USED       0U\n\n#if defined ( __CC_ARM )\n  #if defined __TARGET_FPU_VFP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined __ARM_FP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined __ARMVFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TI_ARM__ )\n  #if defined __TI_VFP_SUPPORT__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined __FPU_VFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM0_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_CM0_H_DEPENDANT\n#define __CORE_CM0_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __CM0_REV\n    #define __CM0_REV               0x0000U\n    #warning \"__CM0_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          2U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/*@} end of group Cortex_M0 */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core SCB Register\n  - Core SysTick Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for Cortex-M processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\n    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\n    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n/*@} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[31U];\n  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RESERVED1[31U];\n  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[31U];\n  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[31U];\n        uint32_t RESERVED4[64U];\n  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */\n}  NVIC_Type;\n\n/*@} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n        uint32_t RESERVED0;\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n        uint32_t RESERVED1;\n  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n} SCB_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\n#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\n#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n/*@} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/*@} end of group CMSIS_SysTick */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\n  \\brief    Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.\n            Therefore they are not covered by the Cortex-M0 header file.\n  @{\n */\n/*@} end of group CMSIS_CoreDebug */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n/*@} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Core Hardware */\n#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\n#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\n#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\n#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\n\n#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\n#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\n#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\n\n\n/*@} */\n\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n#ifdef CMSIS_NVIC_VIRTUAL\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\n  #endif\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\n  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\n/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0 */\n  #define NVIC_SetPriority            __NVIC_SetPriority\n  #define NVIC_GetPriority            __NVIC_GetPriority\n  #define NVIC_SystemReset            __NVIC_SystemReset\n#endif /* CMSIS_NVIC_VIRTUAL */\n\n#ifdef CMSIS_VECTAB_VIRTUAL\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\n  #endif\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetVector              __NVIC_SetVector\n  #define NVIC_GetVector              __NVIC_GetVector\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\n\n#define NVIC_USER_IRQ_OFFSET          16\n\n\n/* The following EXC_RETURN values are saved the LR on exception entry */\n#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */\n#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */\n#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */\n\n\n/* Interrupt Priorities are WORD accessible only under Armv6-M                  */\n/* The following MACROS handle generation of the register offset and byte masks */\n#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)\n#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )\n#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )\n\n#define __NVIC_SetPriorityGrouping(X) (void)(X)\n#define __NVIC_GetPriorityGrouping()  (0U)\n\n/**\n  \\brief   Enable Interrupt\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    __COMPILER_BARRIER();\n    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __COMPILER_BARRIER();\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __DSB();\n    __ISB();\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every processor exception.\n */\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n  else\n  {\n    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Encode Priority\n  \\details Encodes the priority for an interrupt with the given priority group,\n           preemptive priority value, and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\n */\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  return (\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\n         );\n}\n\n\n/**\n  \\brief   Decode Priority\n  \\details Decodes an interrupt priority value with a given priority group to\n           preemptive priority value and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\n */\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\n}\n\n\n\n/**\n  \\brief   Set Interrupt Vector\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n           Address 0 must be mapped to SRAM.\n  \\param [in]   IRQn      Interrupt number\n  \\param [in]   vector    Address of interrupt handler function\n */\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\n{\n  uint32_t vectors = 0x0U;\n  (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector;\n  /* ARM Application Note 321 states that the M0 does not require the architectural barrier */\n}\n\n\n/**\n  \\brief   Get Interrupt Vector\n  \\details Reads an interrupt vector from interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn      Interrupt number.\n  \\return                 Address of interrupt handler function\n */\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\n{\n  uint32_t vectors = 0x0U;\n  return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4));\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                 SCB_AIRCR_SYSRESETREQ_Msk);\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n/*@} end of CMSIS_Core_NVICFunctions */\n\n\n/* ##########################  FPU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\n  \\brief    Function that provides FPU type.\n  @{\n */\n\n/**\n  \\brief   get FPU type\n  \\details returns the FPU type\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n */\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\n{\n    return 0U;           /* No FPU */\n}\n\n\n/*@} end of CMSIS_Core_FpuFunctions */\n\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#endif\n\n/*@} end of CMSIS_Core_SysTickFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM0_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n"
  },
  {
    "path": "3rd_party/CMSIS/Include/core_cm0plus.h",
    "content": "/**************************************************************************//**\n * @file     core_cm0plus.h\n * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File\n * @version  V5.0.7\n * @date     13. March 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CORE_CM0PLUS_H_GENERIC\n#define __CORE_CM0PLUS_H_GENERIC\n\n#include <stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup Cortex-M0+\n  @{\n */\n\n#include \"cmsis_version.h\"\n\n/*  CMSIS CM0+ definitions */\n#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)                  /*!< \\deprecated [31:16] CMSIS HAL main version */\n#define __CM0PLUS_CMSIS_VERSION_SUB  (__CM_CMSIS_VERSION_SUB)                   /*!< \\deprecated [15:0]  CMSIS HAL sub version */\n#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \\\n                                       __CM0PLUS_CMSIS_VERSION_SUB           )  /*!< \\deprecated CMSIS HAL version number */\n\n#define __CORTEX_M                   (0U)                                       /*!< Cortex-M Core */\n\n/** __FPU_USED indicates whether an FPU is used or not.\n    This core does not support an FPU at all\n*/\n#define __FPU_USED       0U\n\n#if defined ( __CC_ARM )\n  #if defined __TARGET_FPU_VFP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined __ARM_FP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined __ARMVFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TI_ARM__ )\n  #if defined __TI_VFP_SUPPORT__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined __FPU_VFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM0PLUS_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_CM0PLUS_H_DEPENDANT\n#define __CORE_CM0PLUS_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __CM0PLUS_REV\n    #define __CM0PLUS_REV             0x0000U\n    #warning \"__CM0PLUS_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __MPU_PRESENT\n    #define __MPU_PRESENT             0U\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __VTOR_PRESENT\n    #define __VTOR_PRESENT            0U\n    #warning \"__VTOR_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          2U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/*@} end of group Cortex-M0+ */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core SCB Register\n  - Core SysTick Register\n  - Core MPU Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for Cortex-M processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\n    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\n    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\n#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\n\n/*@} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[31U];\n  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RESERVED1[31U];\n  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[31U];\n  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[31U];\n        uint32_t RESERVED4[64U];\n  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */\n}  NVIC_Type;\n\n/*@} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\n#else\n        uint32_t RESERVED0;\n#endif\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n        uint32_t RESERVED1;\n  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n} SCB_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\n#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_VTOR_TBLOFF_Pos                 8U                                            /*!< SCB VTOR: TBLOFF Position */\n#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */\n#endif\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\n#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n/*@} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/*@} end of group CMSIS_SysTick */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\n */\ntypedef struct\n{\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\n  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */\n} MPU_Type;\n\n#define MPU_TYPE_RALIASES                  1U\n\n/* MPU Type Register Definitions */\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\n\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\n\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\n\n/* MPU Control Register Definitions */\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\n\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\n\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\n\n/* MPU Region Number Register Definitions */\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\n\n/* MPU Region Base Address Register Definitions */\n#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */\n#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */\n\n#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */\n#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */\n\n#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */\n#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */\n\n/* MPU Region Attribute and Size Register Definitions */\n#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */\n#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */\n\n#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */\n#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */\n\n#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */\n#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */\n\n#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */\n#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */\n\n#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */\n#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */\n\n#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */\n#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */\n\n#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */\n#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */\n\n#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */\n#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */\n\n#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */\n#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */\n\n#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */\n#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */\n\n/*@} end of group CMSIS_MPU */\n#endif\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\n  \\brief    Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.\n            Therefore they are not covered by the Cortex-M0+ header file.\n  @{\n */\n/*@} end of group CMSIS_CoreDebug */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n/*@} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Core Hardware */\n#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\n#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\n#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\n#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\n\n#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\n#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\n#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */\n  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */\n#endif\n\n/*@} */\n\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n#ifdef CMSIS_NVIC_VIRTUAL\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\n  #endif\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\n  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\n/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0+ */\n  #define NVIC_SetPriority            __NVIC_SetPriority\n  #define NVIC_GetPriority            __NVIC_GetPriority\n  #define NVIC_SystemReset            __NVIC_SystemReset\n#endif /* CMSIS_NVIC_VIRTUAL */\n\n#ifdef CMSIS_VECTAB_VIRTUAL\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\n  #endif\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetVector              __NVIC_SetVector\n  #define NVIC_GetVector              __NVIC_GetVector\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\n\n#define NVIC_USER_IRQ_OFFSET          16\n\n\n/* The following EXC_RETURN values are saved the LR on exception entry */\n#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */\n#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */\n#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */\n\n\n/* Interrupt Priorities are WORD accessible only under Armv6-M                  */\n/* The following MACROS handle generation of the register offset and byte masks */\n#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)\n#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )\n#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )\n\n#define __NVIC_SetPriorityGrouping(X) (void)(X)\n#define __NVIC_GetPriorityGrouping()  (0U)\n\n/**\n  \\brief   Enable Interrupt\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    __COMPILER_BARRIER();\n    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __COMPILER_BARRIER();\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __DSB();\n    __ISB();\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every processor exception.\n */\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n  else\n  {\n    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Encode Priority\n  \\details Encodes the priority for an interrupt with the given priority group,\n           preemptive priority value, and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\n */\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  return (\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\n         );\n}\n\n\n/**\n  \\brief   Decode Priority\n  \\details Decodes an interrupt priority value with a given priority group to\n           preemptive priority value and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\n */\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\n}\n\n\n/**\n  \\brief   Set Interrupt Vector\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n           VTOR must been relocated to SRAM before.\n           If VTOR is not present address 0 must be mapped to SRAM.\n  \\param [in]   IRQn      Interrupt number\n  \\param [in]   vector    Address of interrupt handler function\n */\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\n{\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  uint32_t vectors = SCB->VTOR;\n#else\n  uint32_t vectors = 0x0U;\n#endif\n  (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector;\n  /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */\n}\n\n\n/**\n  \\brief   Get Interrupt Vector\n  \\details Reads an interrupt vector from interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn      Interrupt number.\n  \\return                 Address of interrupt handler function\n */\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\n{\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  uint32_t vectors = SCB->VTOR;\n#else\n  uint32_t vectors = 0x0U;\n#endif\n  return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4));\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                 SCB_AIRCR_SYSRESETREQ_Msk);\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n/*@} end of CMSIS_Core_NVICFunctions */\n\n/* ##########################  MPU functions  #################################### */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n\n#include \"mpu_armv7.h\"\n\n#endif\n\n/* ##########################  FPU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\n  \\brief    Function that provides FPU type.\n  @{\n */\n\n/**\n  \\brief   get FPU type\n  \\details returns the FPU type\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n */\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\n{\n    return 0U;           /* No FPU */\n}\n\n\n/*@} end of CMSIS_Core_FpuFunctions */\n\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#endif\n\n/*@} end of CMSIS_Core_SysTickFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM0PLUS_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n"
  },
  {
    "path": "3rd_party/CMSIS/Include/core_cm1.h",
    "content": "/**************************************************************************//**\n * @file     core_cm1.h\n * @brief    CMSIS Cortex-M1 Core Peripheral Access Layer Header File\n * @version  V1.0.1\n * @date     12. November 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CORE_CM1_H_GENERIC\n#define __CORE_CM1_H_GENERIC\n\n#include <stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup Cortex_M1\n  @{\n */\n\n#include \"cmsis_version.h\"\n\n/*  CMSIS CM1 definitions */\n#define __CM1_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \\deprecated [31:16] CMSIS HAL main version */\n#define __CM1_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \\deprecated [15:0]  CMSIS HAL sub version */\n#define __CM1_CMSIS_VERSION       ((__CM1_CMSIS_VERSION_MAIN << 16U) | \\\n                                    __CM1_CMSIS_VERSION_SUB           )  /*!< \\deprecated CMSIS HAL version number */\n\n#define __CORTEX_M                (1U)                                   /*!< Cortex-M Core */\n\n/** __FPU_USED indicates whether an FPU is used or not.\n    This core does not support an FPU at all\n*/\n#define __FPU_USED       0U\n\n#if defined ( __CC_ARM )\n  #if defined __TARGET_FPU_VFP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined __ARM_FP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined __ARMVFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TI_ARM__ )\n  #if defined __TI_VFP_SUPPORT__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined __FPU_VFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM1_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_CM1_H_DEPENDANT\n#define __CORE_CM1_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __CM1_REV\n    #define __CM1_REV               0x0100U\n    #warning \"__CM1_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          2U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/*@} end of group Cortex_M1 */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core SCB Register\n  - Core SysTick Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for Cortex-M processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\n    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\n    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n/*@} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[31U];\n  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RSERVED1[31U];\n  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[31U];\n  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[31U];\n        uint32_t RESERVED4[64U];\n  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */\n}  NVIC_Type;\n\n/*@} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n        uint32_t RESERVED0;\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n        uint32_t RESERVED1;\n  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n} SCB_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\n#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\n#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n/*@} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\n  \\brief    Type definitions for the System Control and ID Register not in the SCB\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control and ID Register not in the SCB.\n */\ntypedef struct\n{\n        uint32_t RESERVED0[2U];\n  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\n} SCnSCB_Type;\n\n/* Auxiliary Control Register Definitions */\n#define SCnSCB_ACTLR_ITCMUAEN_Pos            4U                                        /*!< ACTLR: Instruction TCM Upper Alias Enable Position */\n#define SCnSCB_ACTLR_ITCMUAEN_Msk           (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos)         /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */\n\n#define SCnSCB_ACTLR_ITCMLAEN_Pos            3U                                        /*!< ACTLR: Instruction TCM Lower Alias Enable Position */\n#define SCnSCB_ACTLR_ITCMLAEN_Msk           (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos)         /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */\n\n/*@} end of group CMSIS_SCnotSCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/*@} end of group CMSIS_SysTick */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\n  \\brief    Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.\n            Therefore they are not covered by the Cortex-M1 header file.\n  @{\n */\n/*@} end of group CMSIS_CoreDebug */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n/*@} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Core Hardware */\n#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\n#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\n#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\n#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\n\n#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */\n#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\n#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\n#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\n\n\n/*@} */\n\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n#ifdef CMSIS_NVIC_VIRTUAL\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\n  #endif\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\n  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\n/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M1 */\n  #define NVIC_SetPriority            __NVIC_SetPriority\n  #define NVIC_GetPriority            __NVIC_GetPriority\n  #define NVIC_SystemReset            __NVIC_SystemReset\n#endif /* CMSIS_NVIC_VIRTUAL */\n\n#ifdef CMSIS_VECTAB_VIRTUAL\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\n  #endif\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetVector              __NVIC_SetVector\n  #define NVIC_GetVector              __NVIC_GetVector\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\n\n#define NVIC_USER_IRQ_OFFSET          16\n\n\n/* The following EXC_RETURN values are saved the LR on exception entry */\n#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */\n#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */\n#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */\n\n\n/* Interrupt Priorities are WORD accessible only under Armv6-M                  */\n/* The following MACROS handle generation of the register offset and byte masks */\n#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)\n#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )\n#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )\n\n#define __NVIC_SetPriorityGrouping(X) (void)(X)\n#define __NVIC_GetPriorityGrouping()  (0U)\n\n/**\n  \\brief   Enable Interrupt\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    __COMPILER_BARRIER();\n    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __COMPILER_BARRIER();\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __DSB();\n    __ISB();\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every processor exception.\n */\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n  else\n  {\n    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Encode Priority\n  \\details Encodes the priority for an interrupt with the given priority group,\n           preemptive priority value, and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\n */\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  return (\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\n         );\n}\n\n\n/**\n  \\brief   Decode Priority\n  \\details Decodes an interrupt priority value with a given priority group to\n           preemptive priority value and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\n */\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\n}\n\n\n\n/**\n  \\brief   Set Interrupt Vector\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n           Address 0 must be mapped to SRAM.\n  \\param [in]   IRQn      Interrupt number\n  \\param [in]   vector    Address of interrupt handler function\n */\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\n{\n  uint32_t *vectors = (uint32_t *)0x0U;\n  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\n  /* ARM Application Note 321 states that the M1 does not require the architectural barrier */\n}\n\n\n/**\n  \\brief   Get Interrupt Vector\n  \\details Reads an interrupt vector from interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn      Interrupt number.\n  \\return                 Address of interrupt handler function\n */\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\n{\n  uint32_t *vectors = (uint32_t *)0x0U;\n  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                 SCB_AIRCR_SYSRESETREQ_Msk);\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n/*@} end of CMSIS_Core_NVICFunctions */\n\n\n/* ##########################  FPU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\n  \\brief    Function that provides FPU type.\n  @{\n */\n\n/**\n  \\brief   get FPU type\n  \\details returns the FPU type\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n */\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\n{\n    return 0U;           /* No FPU */\n}\n\n\n/*@} end of CMSIS_Core_FpuFunctions */\n\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#endif\n\n/*@} end of CMSIS_Core_SysTickFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM1_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n"
  },
  {
    "path": "3rd_party/CMSIS/Include/core_cm23.h",
    "content": "/**************************************************************************//**\n * @file     core_cm23.h\n * @brief    CMSIS Cortex-M23 Core Peripheral Access Layer Header File\n * @version  V5.0.8\n * @date     12. November 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CORE_CM23_H_GENERIC\n#define __CORE_CM23_H_GENERIC\n\n#include <stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup Cortex_M23\n  @{\n */\n\n#include \"cmsis_version.h\"\n\n/*  CMSIS definitions */\n#define __CM23_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \\deprecated [31:16] CMSIS HAL main version */\n#define __CM23_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \\deprecated [15:0]  CMSIS HAL sub version */\n#define __CM23_CMSIS_VERSION       ((__CM23_CMSIS_VERSION_MAIN << 16U) | \\\n                                     __CM23_CMSIS_VERSION_SUB           )      /*!< \\deprecated CMSIS HAL version number */\n\n#define __CORTEX_M                 (23U)                                       /*!< Cortex-M Core */\n\n/** __FPU_USED indicates whether an FPU is used or not.\n    This core does not support an FPU at all\n*/\n#define __FPU_USED       0U\n\n#if defined ( __CC_ARM )\n  #if defined __TARGET_FPU_VFP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined __ARM_FP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined __ARMVFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TI_ARM__ )\n  #if defined __TI_VFP_SUPPORT__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined __FPU_VFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM23_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_CM23_H_DEPENDANT\n#define __CORE_CM23_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __CM23_REV\n    #define __CM23_REV                0x0000U\n    #warning \"__CM23_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __FPU_PRESENT\n    #define __FPU_PRESENT             0U\n    #warning \"__FPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __MPU_PRESENT\n    #define __MPU_PRESENT             0U\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __SAUREGION_PRESENT\n    #define __SAUREGION_PRESENT       0U\n    #warning \"__SAUREGION_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __VTOR_PRESENT\n    #define __VTOR_PRESENT            0U\n    #warning \"__VTOR_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          2U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __ETM_PRESENT\n    #define __ETM_PRESENT             0U\n    #warning \"__ETM_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __MTB_PRESENT\n    #define __MTB_PRESENT             0U\n    #warning \"__MTB_PRESENT not defined in device header file; using default!\"\n  #endif\n\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/*@} end of group Cortex_M23 */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core SCB Register\n  - Core SysTick Register\n  - Core Debug Register\n  - Core MPU Register\n  - Core SAU Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for Cortex-M processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\n    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */\n    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\n#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\n\n/*@} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[16U];\n  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RSERVED1[16U];\n  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[16U];\n  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[16U];\n  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\n        uint32_t RESERVED4[16U];\n  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */\n        uint32_t RESERVED5[16U];\n  __IOM uint32_t IPR[124U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */\n}  NVIC_Type;\n\n/*@} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\n#else\n        uint32_t RESERVED0;\n#endif\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n        uint32_t RESERVED1;\n  __IOM uint32_t SHPR[2U];               /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n} SCB_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */\n#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */\n\n#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */\n#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */\n\n#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */\n#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */\n#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\n#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n/* SCB Vector Table Offset Register Definitions */\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\n#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\n#endif\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */\n#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */\n\n#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */\n#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */\n\n#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */\n#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */\n#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */\n#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */\n\n#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */\n#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */\n\n#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */\n#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */\n\n#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */\n#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */\n\n#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\n#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\n\n#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\n#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\n#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */\n#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */\n\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\n#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\n\n#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\n#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\n\n#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\n#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\n\n#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */\n#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */\n\n#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */\n#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */\n\n/*@} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/*@} end of group CMSIS_SysTick */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\n  \\brief    Type definitions for the Data Watchpoint and Trace (DWT)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\n        uint32_t RESERVED0[6U];\n  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\n  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\n        uint32_t RESERVED1[1U];\n  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\n        uint32_t RESERVED2[1U];\n  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\n        uint32_t RESERVED3[1U];\n  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\n        uint32_t RESERVED4[1U];\n  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\n        uint32_t RESERVED5[1U];\n  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\n        uint32_t RESERVED6[1U];\n  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\n        uint32_t RESERVED7[1U];\n  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\n        uint32_t RESERVED8[1U];\n  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */\n        uint32_t RESERVED9[1U];\n  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */\n        uint32_t RESERVED10[1U];\n  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */\n        uint32_t RESERVED11[1U];\n  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */\n        uint32_t RESERVED12[1U];\n  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */\n        uint32_t RESERVED13[1U];\n  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */\n        uint32_t RESERVED14[1U];\n  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */\n        uint32_t RESERVED15[1U];\n  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */\n        uint32_t RESERVED16[1U];\n  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */\n        uint32_t RESERVED17[1U];\n  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */\n        uint32_t RESERVED18[1U];\n  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */\n        uint32_t RESERVED19[1U];\n  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */\n        uint32_t RESERVED20[1U];\n  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */\n        uint32_t RESERVED21[1U];\n  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */\n        uint32_t RESERVED22[1U];\n  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */\n        uint32_t RESERVED23[1U];\n  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */\n        uint32_t RESERVED24[1U];\n  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */\n        uint32_t RESERVED25[1U];\n  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */\n        uint32_t RESERVED26[1U];\n  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */\n        uint32_t RESERVED27[1U];\n  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */\n        uint32_t RESERVED28[1U];\n  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */\n        uint32_t RESERVED29[1U];\n  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */\n        uint32_t RESERVED30[1U];\n  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */\n        uint32_t RESERVED31[1U];\n  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */\n} DWT_Type;\n\n/* DWT Control Register Definitions */\n#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\n#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\n\n#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\n#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\n\n#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\n#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\n\n#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\n#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\n\n#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\n#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\n\n/* DWT Comparator Function Register Definitions */\n#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */\n#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */\n\n#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\n#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\n\n#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\n#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\n\n#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */\n#define DWT_FUNCTION_ACTION_Msk            (0x3UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */\n\n#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */\n#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */\n\n/*@}*/ /* end of group CMSIS_DWT */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_TPI     Trace Port Interface (TPI)\n  \\brief    Type definitions for the Trace Port Interface (TPI)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Trace Port Interface Register (TPI).\n */\ntypedef struct\n{\n  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */\n  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */\n        uint32_t RESERVED0[2U];\n  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\n        uint32_t RESERVED1[55U];\n  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\n        uint32_t RESERVED2[131U];\n  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\n  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\n  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */\n        uint32_t RESERVED3[759U];\n  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */\n  __IM  uint32_t ITFTTD0;                /*!< Offset: 0xEEC (R/ )  Integration Test FIFO Test Data 0 Register */\n  __IOM uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/W)  Integration Test ATB Control Register 2 */\n        uint32_t RESERVED4[1U];\n  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  Integration Test ATB Control Register 0 */\n  __IM  uint32_t ITFTTD1;                /*!< Offset: 0xEFC (R/ )  Integration Test FIFO Test Data 1 Register */\n  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */\n        uint32_t RESERVED5[39U];\n  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */\n  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */\n        uint32_t RESERVED7[8U];\n  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  Device Configuration Register */\n  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Identifier Register */\n} TPI_Type;\n\n/* TPI Asynchronous Clock Prescaler Register Definitions */\n#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */\n#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */\n\n/* TPI Selected Pin Protocol Register Definitions */\n#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\n#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\n\n/* TPI Formatter and Flush Status Register Definitions */\n#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\n#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\n\n#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\n#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\n\n#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\n#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\n\n#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\n#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\n\n/* TPI Formatter and Flush Control Register Definitions */\n#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\n#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\n\n#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */\n#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */\n\n#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\n#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\n\n/* TPI TRIGGER Register Definitions */\n#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */\n#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */\n\n/* TPI Integration Test FIFO Test Data 0 Register Definitions */\n#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */\n#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */\n\n#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */\n#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */\n\n#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */\n#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */\n\n#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */\n#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */\n\n#define TPI_ITFTTD0_ATB_IF1_data2_Pos      16U                                         /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */\n#define TPI_ITFTTD0_ATB_IF1_data2_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */\n\n#define TPI_ITFTTD0_ATB_IF1_data1_Pos       8U                                         /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */\n#define TPI_ITFTTD0_ATB_IF1_data1_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */\n\n#define TPI_ITFTTD0_ATB_IF1_data0_Pos       0U                                          /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */\n#define TPI_ITFTTD0_ATB_IF1_data0_Msk      (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */\n\n/* TPI Integration Test ATB Control Register 2 Register Definitions */\n#define TPI_ITATBCTR2_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID2S Position */\n#define TPI_ITATBCTR2_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)      /*!< TPI ITATBCTR2: AFVALID2SS Mask */\n\n#define TPI_ITATBCTR2_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID1S Position */\n#define TPI_ITATBCTR2_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)      /*!< TPI ITATBCTR2: AFVALID1SS Mask */\n\n#define TPI_ITATBCTR2_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY2S Position */\n#define TPI_ITATBCTR2_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY2S Mask */\n\n#define TPI_ITATBCTR2_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY1S Position */\n#define TPI_ITATBCTR2_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY1S Mask */\n\n/* TPI Integration Test FIFO Test Data 1 Register Definitions */\n#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */\n#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */\n\n#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */\n#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */\n\n#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */\n#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */\n\n#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */\n#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */\n\n#define TPI_ITFTTD1_ATB_IF2_data2_Pos      16U                                         /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */\n#define TPI_ITFTTD1_ATB_IF2_data2_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */\n\n#define TPI_ITFTTD1_ATB_IF2_data1_Pos       8U                                         /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */\n#define TPI_ITFTTD1_ATB_IF2_data1_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */\n\n#define TPI_ITFTTD1_ATB_IF2_data0_Pos       0U                                          /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */\n#define TPI_ITFTTD1_ATB_IF2_data0_Msk      (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */\n\n/* TPI Integration Test ATB Control Register 0 Definitions */\n#define TPI_ITATBCTR0_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID2S Position */\n#define TPI_ITATBCTR0_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)      /*!< TPI ITATBCTR0: AFVALID2SS Mask */\n\n#define TPI_ITATBCTR0_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID1S Position */\n#define TPI_ITATBCTR0_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)      /*!< TPI ITATBCTR0: AFVALID1SS Mask */\n\n#define TPI_ITATBCTR0_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY2S Position */\n#define TPI_ITATBCTR0_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY2S Mask */\n\n#define TPI_ITATBCTR0_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY1S Position */\n#define TPI_ITATBCTR0_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY1S Mask */\n\n/* TPI Integration Mode Control Register Definitions */\n#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */\n#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */\n\n/* TPI DEVID Register Definitions */\n#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\n#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\n\n#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\n#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\n\n#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\n#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\n\n#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFOSZ Position */\n#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFOSZ Mask */\n\n#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */\n#define TPI_DEVID_NrTraceInput_Msk         (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */\n\n/* TPI DEVTYPE Register Definitions */\n#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */\n#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\n\n#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */\n#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\n\n/*@}*/ /* end of group CMSIS_TPI */\n\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\n */\ntypedef struct\n{\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\n  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */\n        uint32_t RESERVED0[7U];\n  union {\n  __IOM uint32_t MAIR[2];\n  struct {\n  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */\n  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */\n  };\n  };\n} MPU_Type;\n\n#define MPU_TYPE_RALIASES                  1U\n\n/* MPU Type Register Definitions */\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\n\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\n\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\n\n/* MPU Control Register Definitions */\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\n\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\n\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\n\n/* MPU Region Number Register Definitions */\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\n\n/* MPU Region Base Address Register Definitions */\n#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */\n#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */\n\n#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */\n#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */\n\n#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */\n#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */\n\n#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */\n#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */\n\n/* MPU Region Limit Address Register Definitions */\n#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */\n#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */\n\n#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */\n#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */\n\n#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: EN Position */\n#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: EN Mask */\n\n/* MPU Memory Attribute Indirection Register 0 Definitions */\n#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */\n#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */\n\n#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */\n#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */\n\n#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */\n#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */\n\n#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */\n#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */\n\n/* MPU Memory Attribute Indirection Register 1 Definitions */\n#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */\n#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */\n\n#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */\n#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */\n\n#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */\n#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */\n\n#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */\n#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */\n\n/*@} end of group CMSIS_MPU */\n#endif\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SAU     Security Attribution Unit (SAU)\n  \\brief    Type definitions for the Security Attribution Unit (SAU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Security Attribution Unit (SAU).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */\n  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */\n#endif\n} SAU_Type;\n\n/* SAU Control Register Definitions */\n#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */\n#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */\n\n#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */\n#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */\n\n/* SAU Type Register Definitions */\n#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */\n#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */\n\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n/* SAU Region Number Register Definitions */\n#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */\n#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */\n\n/* SAU Region Base Address Register Definitions */\n#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */\n#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */\n\n/* SAU Region Limit Address Register Definitions */\n#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */\n#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */\n\n#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */\n#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */\n\n#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */\n#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */\n\n#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\n\n/*@} end of group CMSIS_SAU */\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\n  \\brief    Type definitions for the Core Debug Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Core Debug Register (CoreDebug).\n */\ntypedef struct\n{\n  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\n  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\n  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\n  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\n        uint32_t RESERVED4[1U];\n  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */\n  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */\n} CoreDebug_Type;\n\n/* Debug Halting Control and Status Register Definitions */\n#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */\n#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\n\n#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */\n#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */\n\n#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */\n#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\n\n#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\n#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\n\n#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */\n#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\n\n#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */\n#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\n\n#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */\n#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\n\n#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */\n#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\n\n#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */\n#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\n\n#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */\n#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\n\n#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */\n#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\n\n#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */\n#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\n\n/* Debug Core Register Selector Register Definitions */\n#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */\n#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\n\n#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */\n#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */\n\n/* Debug Exception and Monitor Control Register */\n#define CoreDebug_DEMCR_DWTENA_Pos         24U                                            /*!< CoreDebug DEMCR: DWTENA Position */\n#define CoreDebug_DEMCR_DWTENA_Msk         (1UL << CoreDebug_DEMCR_DWTENA_Pos)            /*!< CoreDebug DEMCR: DWTENA Mask */\n\n#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */\n#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\n\n#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */\n#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */\n\n/* Debug Authentication Control Register Definitions */\n#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */\n#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */\n\n#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */\n#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */\n\n#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */\n#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */\n\n#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */\n#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */\n\n/* Debug Security Control and Status Register Definitions */\n#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */\n#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */\n\n#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */\n#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */\n\n#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */\n#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */\n\n/*@} end of group CMSIS_CoreDebug */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n/*@} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Core Hardware */\n  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */\n  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */\n  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */\n  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */\n  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */\n  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */\n  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */\n\n\n  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */\n  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */\n  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */\n  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */\n  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */\n  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */\n\n  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */\n    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */\n  #endif\n\n  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */\n    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */\n  #endif\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */\n  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */\n  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */\n  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */\n  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */\n\n  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */\n  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */\n  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */\n  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */\n\n  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */\n    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */\n  #endif\n\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n/*@} */\n\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n#ifdef CMSIS_NVIC_VIRTUAL\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\n  #endif\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\n#else\n/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for Cortex-M23 */\n/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for Cortex-M23 */\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\n  #define NVIC_GetActive              __NVIC_GetActive\n  #define NVIC_SetPriority            __NVIC_SetPriority\n  #define NVIC_GetPriority            __NVIC_GetPriority\n  #define NVIC_SystemReset            __NVIC_SystemReset\n#endif /* CMSIS_NVIC_VIRTUAL */\n\n#ifdef CMSIS_VECTAB_VIRTUAL\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\n  #endif\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetVector              __NVIC_SetVector\n  #define NVIC_GetVector              __NVIC_GetVector\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\n\n#define NVIC_USER_IRQ_OFFSET          16\n\n\n/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */\n\n/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */\n#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */\n\n/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */\n#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */\n#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */\n#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */\n#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */\n#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */\n#define EXC_RETURN_SPSEL           (0x00000004UL)     /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP           */\n#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */\n\n/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */\n#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */\n#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */\n#else\n#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */\n#endif\n\n\n/* Interrupt Priorities are WORD accessible only under Armv6-M                  */\n/* The following MACROS handle generation of the register offset and byte masks */\n#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)\n#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )\n#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )\n\n#define __NVIC_SetPriorityGrouping(X) (void)(X)\n#define __NVIC_GetPriorityGrouping()  (0U)\n\n/**\n  \\brief   Enable Interrupt\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    __COMPILER_BARRIER();\n    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __COMPILER_BARRIER();\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __DSB();\n    __ISB();\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt\n  \\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Get Interrupt Target State\n  \\details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n  \\return             1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Target State\n  \\details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n                      1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Clear Interrupt Target State\n  \\details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n                      1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every processor exception.\n */\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n  else\n  {\n    SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Encode Priority\n  \\details Encodes the priority for an interrupt with the given priority group,\n           preemptive priority value, and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\n */\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  return (\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\n         );\n}\n\n\n/**\n  \\brief   Decode Priority\n  \\details Decodes an interrupt priority value with a given priority group to\n           preemptive priority value and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\n */\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\n}\n\n\n/**\n  \\brief   Set Interrupt Vector\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n           VTOR must been relocated to SRAM before.\n           If VTOR is not present address 0 must be mapped to SRAM.\n  \\param [in]   IRQn      Interrupt number\n  \\param [in]   vector    Address of interrupt handler function\n */\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\n{\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n#else\n  uint32_t *vectors = (uint32_t *)0x0U;\n#endif\n  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\n  __DSB();\n}\n\n\n/**\n  \\brief   Get Interrupt Vector\n  \\details Reads an interrupt vector from interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn      Interrupt number.\n  \\return                 Address of interrupt handler function\n */\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\n{\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n#else\n  uint32_t *vectors = (uint32_t *)0x0U;\n#endif\n  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                 SCB_AIRCR_SYSRESETREQ_Msk);\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Enable Interrupt (non-secure)\n  \\details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status (non-secure)\n  \\details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt (non-secure)\n  \\details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt (non-secure)\n  \\details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt (non-secure)\n  \\details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt (non-secure)\n  \\details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt (non-secure)\n  \\details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Priority (non-secure)\n  \\details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every non-secure processor exception.\n */\n__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n  else\n  {\n    SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority (non-secure)\n  \\details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */\n\n/*@} end of CMSIS_Core_NVICFunctions */\n\n/* ##########################  MPU functions  #################################### */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n\n#include \"mpu_armv8.h\"\n\n#endif\n\n/* ##########################  FPU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\n  \\brief    Function that provides FPU type.\n  @{\n */\n\n/**\n  \\brief   get FPU type\n  \\details returns the FPU type\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n */\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\n{\n    return 0U;           /* No FPU */\n}\n\n\n/*@} end of CMSIS_Core_FpuFunctions */\n\n\n\n/* ##########################   SAU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SAUFunctions SAU Functions\n  \\brief    Functions that configure the SAU.\n  @{\n */\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n\n/**\n  \\brief   Enable SAU\n  \\details Enables the Security Attribution Unit (SAU).\n */\n__STATIC_INLINE void TZ_SAU_Enable(void)\n{\n    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);\n}\n\n\n\n/**\n  \\brief   Disable SAU\n  \\details Disables the Security Attribution Unit (SAU).\n */\n__STATIC_INLINE void TZ_SAU_Disable(void)\n{\n    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);\n}\n\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n/*@} end of CMSIS_Core_SAUFunctions */\n\n\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   System Tick Configuration (non-secure)\n  \\details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n\n */\n__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                         /* Reload value impossible */\n  }\n\n  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */\n  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */\n  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                      SysTick_CTRL_TICKINT_Msk   |\n                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                           /* Function successful */\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n#endif\n\n/*@} end of CMSIS_Core_SysTickFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM23_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n"
  },
  {
    "path": "3rd_party/CMSIS/Include/core_cm3.h",
    "content": "/**************************************************************************//**\n * @file     core_cm3.h\n * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File\n * @version  V5.1.0\n * @date     13. March 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CORE_CM3_H_GENERIC\n#define __CORE_CM3_H_GENERIC\n\n#include <stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup Cortex_M3\n  @{\n */\n\n#include \"cmsis_version.h\"\n\n/*  CMSIS CM3 definitions */\n#define __CM3_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \\deprecated [31:16] CMSIS HAL main version */\n#define __CM3_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \\deprecated [15:0]  CMSIS HAL sub version */\n#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16U) | \\\n                                    __CM3_CMSIS_VERSION_SUB           )  /*!< \\deprecated CMSIS HAL version number */\n\n#define __CORTEX_M                (3U)                                   /*!< Cortex-M Core */\n\n/** __FPU_USED indicates whether an FPU is used or not.\n    This core does not support an FPU at all\n*/\n#define __FPU_USED       0U\n\n#if defined ( __CC_ARM )\n  #if defined __TARGET_FPU_VFP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined __ARM_FP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined __ARMVFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TI_ARM__ )\n  #if defined __TI_VFP_SUPPORT__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined __FPU_VFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM3_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_CM3_H_DEPENDANT\n#define __CORE_CM3_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __CM3_REV\n    #define __CM3_REV               0x0200U\n    #warning \"__CM3_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __MPU_PRESENT\n    #define __MPU_PRESENT             0U\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          3U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/*@} end of group Cortex_M3 */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core SCB Register\n  - Core SysTick Register\n  - Core Debug Register\n  - Core MPU Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for Cortex-M processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */\n#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */\n    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */\n    uint32_t _reserved1:8;               /*!< bit: 16..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit */\n    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */\n#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */\n\n#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */\n#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */\n#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\n    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\n#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\n\n/*@} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[24U];\n  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RESERVED1[24U];\n  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[24U];\n  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[24U];\n  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\n        uint32_t RESERVED4[56U];\n  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */\n        uint32_t RESERVED5[644U];\n  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */\n}  NVIC_Type;\n\n/* Software Triggered Interrupt Register Definitions */\n#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */\n#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */\n\n/*@} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */\n  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */\n  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */\n  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */\n  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */\n  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */\n  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */\n  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */\n  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */\n  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */\n  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */\n        uint32_t RESERVED0[5U];\n  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */\n} SCB_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\n#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\n#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n/* SCB Vector Table Offset Register Definitions */\n#if defined (__CM3_REV) && (__CM3_REV < 0x0201U)                   /* core r2p1 */\n#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */\n#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */\n\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\n#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */\n#else\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\n#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\n#endif\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */\n#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */\n#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\n#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\n\n#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\n#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\n\n#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\n#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\n#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\n\n#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */\n#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */\n#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */\n\n#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */\n#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */\n\n#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */\n#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */\n\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */\n#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */\n\n#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */\n#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */\n\n#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */\n#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */\n\n#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\n#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\n\n#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\n#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\n\n#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */\n#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */\n\n#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\n#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\n\n#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */\n#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */\n\n#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */\n#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */\n\n#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */\n#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */\n\n/* SCB Configurable Fault Status Register Definitions */\n#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */\n#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */\n\n#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */\n#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */\n\n#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */\n#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\n\n/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */\n#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */\n\n#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */\n#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */\n\n#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\n#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\n\n#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */\n#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\n\n#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */\n#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\n\n/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */\n#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */\n\n#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */\n#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */\n\n#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */\n#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */\n\n#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */\n#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\n\n#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */\n#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */\n\n#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */\n#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */\n\n/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */\n#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\n\n#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */\n#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */\n\n#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */\n#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */\n\n#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */\n#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */\n\n#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */\n#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */\n\n#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\n#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\n\n/* SCB Hard Fault Status Register Definitions */\n#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */\n#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */\n\n#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */\n#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */\n\n#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */\n#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */\n\n/* SCB Debug Fault Status Register Definitions */\n#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */\n#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */\n\n#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */\n#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */\n\n#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */\n#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */\n\n#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */\n#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */\n\n#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */\n#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */\n\n/*@} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\n  \\brief    Type definitions for the System Control and ID Register not in the SCB\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control and ID Register not in the SCB.\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1U];\n  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */\n#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)\n  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\n#else\n        uint32_t RESERVED1[1U];\n#endif\n} SCnSCB_Type;\n\n/* Interrupt Controller Type Register Definitions */\n#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */\n#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */\n\n/* Auxiliary Control Register Definitions */\n#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)\n#define SCnSCB_ACTLR_DISOOFP_Pos            9U                                         /*!< ACTLR: DISOOFP Position */\n#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */\n\n#define SCnSCB_ACTLR_DISFPCA_Pos            8U                                         /*!< ACTLR: DISFPCA Position */\n#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */\n\n#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */\n#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */\n\n#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */\n#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */\n\n#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */\n#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */\n#endif\n\n/*@} end of group CMSIS_SCnotSCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/*@} end of group CMSIS_SysTick */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)\n  \\brief    Type definitions for the Instrumentation Trace Macrocell (ITM)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).\n */\ntypedef struct\n{\n  __OM  union\n  {\n    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */\n    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */\n    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */\n  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */\n        uint32_t RESERVED0[864U];\n  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */\n        uint32_t RESERVED1[15U];\n  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */\n        uint32_t RESERVED2[15U];\n  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */\n        uint32_t RESERVED3[32U];\n        uint32_t RESERVED4[43U];\n  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */\n        uint32_t RESERVED5[6U];\n  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */\n  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */\n  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */\n  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */\n  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */\n  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */\n  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */\n  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */\n  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */\n  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */\n  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */\n  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */\n} ITM_Type;\n\n/* ITM Trace Privilege Register Definitions */\n#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */\n#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */\n\n/* ITM Trace Control Register Definitions */\n#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */\n#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */\n\n#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */\n#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */\n\n#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */\n#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */\n\n#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */\n#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */\n\n#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */\n#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */\n\n#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */\n#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */\n\n#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */\n#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */\n\n#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */\n#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */\n\n#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */\n#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */\n\n/* ITM Lock Status Register Definitions */\n#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */\n#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */\n\n#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */\n#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */\n\n#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */\n#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */\n\n/*@}*/ /* end of group CMSIS_ITM */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\n  \\brief    Type definitions for the Data Watchpoint and Trace (DWT)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\n  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */\n  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */\n  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */\n  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */\n  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */\n  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */\n  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\n  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\n  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */\n  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\n        uint32_t RESERVED0[1U];\n  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\n  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */\n  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\n        uint32_t RESERVED1[1U];\n  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\n  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */\n  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\n        uint32_t RESERVED2[1U];\n  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\n  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */\n  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\n} DWT_Type;\n\n/* DWT Control Register Definitions */\n#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\n#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\n\n#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\n#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\n\n#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\n#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\n\n#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\n#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\n\n#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\n#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\n\n#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */\n#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */\n\n#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */\n#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */\n\n#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */\n#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */\n\n#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */\n#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */\n\n#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */\n#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */\n\n#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */\n#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */\n\n#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */\n#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */\n\n#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */\n#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */\n\n#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */\n#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */\n\n#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */\n#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */\n\n#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */\n#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */\n\n#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */\n#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */\n\n#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */\n#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */\n\n/* DWT CPI Count Register Definitions */\n#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */\n#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */\n\n/* DWT Exception Overhead Count Register Definitions */\n#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */\n#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */\n\n/* DWT Sleep Count Register Definitions */\n#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */\n#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */\n\n/* DWT LSU Count Register Definitions */\n#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */\n#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */\n\n/* DWT Folded-instruction Count Register Definitions */\n#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */\n#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */\n\n/* DWT Comparator Mask Register Definitions */\n#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */\n#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */\n\n/* DWT Comparator Function Register Definitions */\n#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\n#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\n\n#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */\n#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */\n\n#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */\n#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */\n\n#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\n#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\n\n#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */\n#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */\n\n#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */\n#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */\n\n#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */\n#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */\n\n#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */\n#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */\n\n#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */\n#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */\n\n/*@}*/ /* end of group CMSIS_DWT */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_TPI     Trace Port Interface (TPI)\n  \\brief    Type definitions for the Trace Port Interface (TPI)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Trace Port Interface Register (TPI).\n */\ntypedef struct\n{\n  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */\n  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */\n        uint32_t RESERVED0[2U];\n  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\n        uint32_t RESERVED1[55U];\n  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\n        uint32_t RESERVED2[131U];\n  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\n  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\n  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */\n        uint32_t RESERVED3[759U];\n  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */\n  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */\n  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */\n        uint32_t RESERVED4[1U];\n  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */\n  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */\n  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */\n        uint32_t RESERVED5[39U];\n  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */\n  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */\n        uint32_t RESERVED7[8U];\n  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */\n  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */\n} TPI_Type;\n\n/* TPI Asynchronous Clock Prescaler Register Definitions */\n#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */\n#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */\n\n/* TPI Selected Pin Protocol Register Definitions */\n#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\n#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\n\n/* TPI Formatter and Flush Status Register Definitions */\n#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\n#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\n\n#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\n#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\n\n#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\n#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\n\n#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\n#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\n\n/* TPI Formatter and Flush Control Register Definitions */\n#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\n#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\n\n#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\n#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\n\n/* TPI TRIGGER Register Definitions */\n#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */\n#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */\n\n/* TPI Integration ETM Data Register Definitions (FIFO0) */\n#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */\n#define TPI_FIFO0_ITM_ATVALID_Msk          (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */\n\n#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */\n#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */\n\n#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */\n#define TPI_FIFO0_ETM_ATVALID_Msk          (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */\n\n#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */\n#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */\n\n#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */\n#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */\n\n#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */\n#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */\n\n#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */\n#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */\n\n/* TPI ITATBCTR2 Register Definitions */\n#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */\n#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */\n\n#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */\n#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */\n\n/* TPI Integration ITM Data Register Definitions (FIFO1) */\n#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */\n#define TPI_FIFO1_ITM_ATVALID_Msk          (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */\n\n#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */\n#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */\n\n#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */\n#define TPI_FIFO1_ETM_ATVALID_Msk          (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */\n\n#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */\n#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */\n\n#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */\n#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */\n\n#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */\n#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */\n\n#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */\n#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */\n\n/* TPI ITATBCTR0 Register Definitions */\n#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */\n#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */\n\n#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */\n#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */\n\n/* TPI Integration Mode Control Register Definitions */\n#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */\n#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */\n\n/* TPI DEVID Register Definitions */\n#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\n#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\n\n#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\n#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\n\n#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\n#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\n\n#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */\n#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */\n\n#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */\n#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */\n\n#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */\n#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */\n\n/* TPI DEVTYPE Register Definitions */\n#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */\n#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\n\n#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */\n#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\n\n/*@}*/ /* end of group CMSIS_TPI */\n\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\n */\ntypedef struct\n{\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\n  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */\n  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */\n  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */\n  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */\n  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */\n  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */\n  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */\n} MPU_Type;\n\n#define MPU_TYPE_RALIASES                  4U\n\n/* MPU Type Register Definitions */\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\n\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\n\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\n\n/* MPU Control Register Definitions */\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\n\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\n\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\n\n/* MPU Region Number Register Definitions */\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\n\n/* MPU Region Base Address Register Definitions */\n#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */\n#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */\n\n#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */\n#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */\n\n#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */\n#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */\n\n/* MPU Region Attribute and Size Register Definitions */\n#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */\n#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */\n\n#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */\n#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */\n\n#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */\n#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */\n\n#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */\n#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */\n\n#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */\n#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */\n\n#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */\n#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */\n\n#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */\n#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */\n\n#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */\n#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */\n\n#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */\n#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */\n\n#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */\n#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */\n\n/*@} end of group CMSIS_MPU */\n#endif\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\n  \\brief    Type definitions for the Core Debug Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Core Debug Register (CoreDebug).\n */\ntypedef struct\n{\n  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\n  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\n  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\n  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\n} CoreDebug_Type;\n\n/* Debug Halting Control and Status Register Definitions */\n#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */\n#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\n\n#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */\n#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\n\n#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\n#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\n\n#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */\n#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\n\n#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */\n#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\n\n#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */\n#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\n\n#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */\n#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\n\n#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\n#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\n\n#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */\n#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\n\n#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */\n#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\n\n#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */\n#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\n\n#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */\n#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\n\n/* Debug Core Register Selector Register Definitions */\n#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */\n#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\n\n#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */\n#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */\n\n/* Debug Exception and Monitor Control Register Definitions */\n#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */\n#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */\n\n#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */\n#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */\n\n#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */\n#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */\n\n#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */\n#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */\n\n#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */\n#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */\n\n#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */\n#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\n\n#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */\n#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */\n\n#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */\n#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */\n\n#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */\n#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */\n\n#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */\n#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */\n\n#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */\n#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\n\n#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */\n#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */\n\n#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */\n#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */\n\n/*@} end of group CMSIS_CoreDebug */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n/*@} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Core Hardware */\n#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\n#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */\n#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */\n#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */\n#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */\n#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\n#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\n#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\n\n#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */\n#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\n#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\n#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\n#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */\n#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */\n#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */\n#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */\n  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */\n#endif\n\n/*@} */\n\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Debug Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n#ifdef CMSIS_NVIC_VIRTUAL\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\n  #endif\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\n  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\n  #define NVIC_GetActive              __NVIC_GetActive\n  #define NVIC_SetPriority            __NVIC_SetPriority\n  #define NVIC_GetPriority            __NVIC_GetPriority\n  #define NVIC_SystemReset            __NVIC_SystemReset\n#endif /* CMSIS_NVIC_VIRTUAL */\n\n#ifdef CMSIS_VECTAB_VIRTUAL\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n   #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\n  #endif\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetVector              __NVIC_SetVector\n  #define NVIC_GetVector              __NVIC_GetVector\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\n\n#define NVIC_USER_IRQ_OFFSET          16\n\n\n/* The following EXC_RETURN values are saved the LR on exception entry */\n#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */\n#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */\n#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */\n\n\n/**\n  \\brief   Set Priority Grouping\n  \\details Sets the priority grouping field using the required unlock sequence.\n           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\n           Only values from 0..7 are used.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]      PriorityGroup  Priority grouping field.\n */\n__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\n{\n  uint32_t reg_value;\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\n\n  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */\n  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\n  reg_value  =  (reg_value                                   |\n                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) );               /* Insert write key and priority group */\n  SCB->AIRCR =  reg_value;\n}\n\n\n/**\n  \\brief   Get Priority Grouping\n  \\details Reads the priority grouping field from the NVIC Interrupt Controller.\n  \\return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\n{\n  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\n}\n\n\n/**\n  \\brief   Enable Interrupt\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    __COMPILER_BARRIER();\n    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __COMPILER_BARRIER();\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __DSB();\n    __ISB();\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt\n  \\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every processor exception.\n */\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n  else\n  {\n    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Encode Priority\n  \\details Encodes the priority for an interrupt with the given priority group,\n           preemptive priority value, and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\n */\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  return (\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\n         );\n}\n\n\n/**\n  \\brief   Decode Priority\n  \\details Decodes an interrupt priority value with a given priority group to\n           preemptive priority value and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\n */\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\n}\n\n\n/**\n  \\brief   Set Interrupt Vector\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n           VTOR must been relocated to SRAM before.\n  \\param [in]   IRQn      Interrupt number\n  \\param [in]   vector    Address of interrupt handler function\n */\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\n{\n  uint32_t vectors = (uint32_t )SCB->VTOR;\n  (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector;\n  /* ARM Application Note 321 states that the M3 does not require the architectural barrier */\n}\n\n\n/**\n  \\brief   Get Interrupt Vector\n  \\details Reads an interrupt vector from interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn      Interrupt number.\n  \\return                 Address of interrupt handler function\n */\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\n{\n  uint32_t vectors = (uint32_t )SCB->VTOR;\n  return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4));\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |\n                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\n                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n/*@} end of CMSIS_Core_NVICFunctions */\n\n/* ##########################  MPU functions  #################################### */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n\n#include \"mpu_armv7.h\"\n\n#endif\n\n\n/* ##########################  FPU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\n  \\brief    Function that provides FPU type.\n  @{\n */\n\n/**\n  \\brief   get FPU type\n  \\details returns the FPU type\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n */\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\n{\n    return 0U;           /* No FPU */\n}\n\n\n/*@} end of CMSIS_Core_FpuFunctions */\n\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#endif\n\n/*@} end of CMSIS_Core_SysTickFunctions */\n\n\n\n/* ##################################### Debug In/Output function ########################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_core_DebugFunctions ITM Functions\n  \\brief    Functions that access the ITM debug interface.\n  @{\n */\n\nextern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */\n#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \\ref ITM_RxBuffer is ready for next character. */\n\n\n/**\n  \\brief   ITM Send Character\n  \\details Transmits a character via the ITM channel 0, and\n           \\li Just returns when no debugger is connected that has booked the output.\n           \\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\n  \\param [in]     ch  Character to transmit.\n  \\returns            Character to transmit.\n */\n__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\n{\n  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */\n      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */\n  {\n    while (ITM->PORT[0U].u32 == 0UL)\n    {\n      __NOP();\n    }\n    ITM->PORT[0U].u8 = (uint8_t)ch;\n  }\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Receive Character\n  \\details Inputs a character via the external variable \\ref ITM_RxBuffer.\n  \\return             Received character.\n  \\return         -1  No character pending.\n */\n__STATIC_INLINE int32_t ITM_ReceiveChar (void)\n{\n  int32_t ch = -1;                           /* no character available */\n\n  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\n  {\n    ch = ITM_RxBuffer;\n    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */\n  }\n\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Check Character\n  \\details Checks whether a character is pending for reading in the variable \\ref ITM_RxBuffer.\n  \\return          0  No character available.\n  \\return          1  Character available.\n */\n__STATIC_INLINE int32_t ITM_CheckChar (void)\n{\n\n  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\n  {\n    return (0);                              /* no character available */\n  }\n  else\n  {\n    return (1);                              /*    character available */\n  }\n}\n\n/*@} end of CMSIS_core_DebugFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM3_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n"
  },
  {
    "path": "3rd_party/CMSIS/Include/core_cm33.h",
    "content": "/**************************************************************************//**\n * @file     core_cm33.h\n * @brief    CMSIS Cortex-M33 Core Peripheral Access Layer Header File\n * @version  V5.1.0\n * @date     12. November 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CORE_CM33_H_GENERIC\n#define __CORE_CM33_H_GENERIC\n\n#include <stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup Cortex_M33\n  @{\n */\n\n#include \"cmsis_version.h\"\n\n/*  CMSIS CM33 definitions */\n#define __CM33_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \\deprecated [31:16] CMSIS HAL main version */\n#define __CM33_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \\deprecated [15:0]  CMSIS HAL sub version */\n#define __CM33_CMSIS_VERSION       ((__CM33_CMSIS_VERSION_MAIN << 16U) | \\\n                                     __CM33_CMSIS_VERSION_SUB           )      /*!< \\deprecated CMSIS HAL version number */\n\n#define __CORTEX_M                 (33U)                                       /*!< Cortex-M Core */\n\n/** __FPU_USED indicates whether an FPU is used or not.\n    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\n*/\n#if defined ( __CC_ARM )\n  #if defined (__TARGET_FPU_VFP)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)\n    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED         0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined (__ARM_FP)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #warning \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)\n    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED         0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)\n    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED         0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined (__ARMVFP__)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)\n    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED         0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined ( __TI_ARM__ )\n  #if defined (__TI_VFP_SUPPORT__)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined (__FPU_VFP__)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM33_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_CM33_H_DEPENDANT\n#define __CORE_CM33_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __CM33_REV\n    #define __CM33_REV                0x0000U\n    #warning \"__CM33_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __FPU_PRESENT\n    #define __FPU_PRESENT             0U\n    #warning \"__FPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __MPU_PRESENT\n    #define __MPU_PRESENT             0U\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __SAUREGION_PRESENT\n    #define __SAUREGION_PRESENT       0U\n    #warning \"__SAUREGION_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __DSP_PRESENT\n    #define __DSP_PRESENT             0U\n    #warning \"__DSP_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          3U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/*@} end of group Cortex_M33 */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core SCB Register\n  - Core SysTick Register\n  - Core Debug Register\n  - Core MPU Register\n  - Core SAU Register\n  - Core FPU Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for Cortex-M processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */\n    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\n    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */\n#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */\n\n#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */\n#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */\n    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\n    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\n    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */\n#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */\n\n#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */\n#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */\n#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */\n    uint32_t FPCA:1;                     /*!< bit:      2  Floating-point context active */\n    uint32_t SFPA:1;                     /*!< bit:      3  Secure floating-point active */\n    uint32_t _reserved1:28;              /*!< bit:  4..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */\n#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */\n\n#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */\n#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */\n\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\n#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\n\n/*@} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[16U];\n  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RSERVED1[16U];\n  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[16U];\n  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[16U];\n  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\n        uint32_t RESERVED4[16U];\n  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */\n        uint32_t RESERVED5[16U];\n  __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */\n        uint32_t RESERVED6[580U];\n  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */\n}  NVIC_Type;\n\n/* Software Triggered Interrupt Register Definitions */\n#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */\n#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */\n\n/*@} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */\n  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */\n  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */\n  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */\n  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */\n  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */\n  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */\n  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */\n  __IM  uint32_t ID_ADR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */\n  __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */\n  __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */\n  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */\n  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */\n  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */\n  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */\n  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */\n  __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */\n        uint32_t RESERVED3[92U];\n  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */\n        uint32_t RESERVED4[15U];\n  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */\n  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */\n  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */\n        uint32_t RESERVED5[1U];\n  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */\n        uint32_t RESERVED6[1U];\n  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */\n  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */\n  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */\n  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */\n  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */\n  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */\n  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */\n  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */\n} SCB_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */\n#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */\n\n#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */\n#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */\n\n#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */\n#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */\n#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\n#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n/* SCB Vector Table Offset Register Definitions */\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\n#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */\n#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */\n\n#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */\n#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */\n\n#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */\n#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */\n\n#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */\n#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */\n#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */\n#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */\n\n#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */\n#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */\n\n#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */\n#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */\n\n#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */\n#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */\n\n#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\n#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\n\n#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\n#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\n#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */\n#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */\n\n#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */\n#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */\n\n#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */\n#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */\n\n#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */\n#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */\n\n#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */\n#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */\n\n#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */\n#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */\n\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */\n#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */\n\n#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */\n#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */\n\n#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */\n#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */\n\n#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\n#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\n\n#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\n#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\n\n#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */\n#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */\n\n#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\n#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\n\n#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */\n#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */\n\n#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */\n#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */\n\n#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */\n#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */\n\n#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */\n#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */\n\n#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */\n#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */\n\n#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */\n#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */\n\n/* SCB Configurable Fault Status Register Definitions */\n#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */\n#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */\n\n#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */\n#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */\n\n#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */\n#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\n\n/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */\n#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */\n\n#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */\n#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */\n\n#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */\n#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */\n\n#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\n#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\n\n#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */\n#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\n\n#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */\n#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\n\n/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */\n#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */\n\n#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */\n#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */\n\n#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */\n#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */\n\n#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */\n#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */\n\n#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */\n#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\n\n#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */\n#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */\n\n#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */\n#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */\n\n/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */\n#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\n\n#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */\n#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */\n\n#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */\n#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */\n\n#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */\n#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */\n\n#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */\n#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */\n\n#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */\n#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */\n\n#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\n#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\n\n/* SCB Hard Fault Status Register Definitions */\n#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */\n#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */\n\n#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */\n#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */\n\n#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */\n#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */\n\n/* SCB Debug Fault Status Register Definitions */\n#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */\n#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */\n\n#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */\n#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */\n\n#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */\n#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */\n\n#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */\n#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */\n\n#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */\n#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */\n\n/* SCB Non-Secure Access Control Register Definitions */\n#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */\n#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */\n\n#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */\n#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */\n\n#define SCB_NSACR_CPn_Pos                   0U                                            /*!< SCB NSACR: CPn Position */\n#define SCB_NSACR_CPn_Msk                  (1UL /*<< SCB_NSACR_CPn_Pos*/)                 /*!< SCB NSACR: CPn Mask */\n\n/* SCB Cache Level ID Register Definitions */\n#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */\n#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */\n\n#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */\n#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */\n\n/* SCB Cache Type Register Definitions */\n#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */\n#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */\n\n#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */\n#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */\n\n#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */\n#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */\n\n#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */\n#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */\n\n#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */\n#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */\n\n/* SCB Cache Size ID Register Definitions */\n#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */\n#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */\n\n#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */\n#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */\n\n#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */\n#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */\n\n#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */\n#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */\n\n#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */\n#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */\n\n#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */\n#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */\n\n#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */\n#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */\n\n/* SCB Cache Size Selection Register Definitions */\n#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */\n#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */\n\n#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */\n#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */\n\n/* SCB Software Triggered Interrupt Register Definitions */\n#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */\n#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */\n\n/* SCB D-Cache Invalidate by Set-way Register Definitions */\n#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */\n#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */\n\n#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */\n#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */\n\n/* SCB D-Cache Clean by Set-way Register Definitions */\n#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */\n#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */\n\n#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */\n#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */\n\n/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */\n#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */\n#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */\n\n#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */\n#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */\n\n/*@} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\n  \\brief    Type definitions for the System Control and ID Register not in the SCB\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control and ID Register not in the SCB.\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1U];\n  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */\n  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\n  __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */\n} SCnSCB_Type;\n\n/* Interrupt Controller Type Register Definitions */\n#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */\n#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */\n\n/*@} end of group CMSIS_SCnotSCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/*@} end of group CMSIS_SysTick */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)\n  \\brief    Type definitions for the Instrumentation Trace Macrocell (ITM)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).\n */\ntypedef struct\n{\n  __OM  union\n  {\n    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */\n    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */\n    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */\n  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */\n        uint32_t RESERVED0[864U];\n  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */\n        uint32_t RESERVED1[15U];\n  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */\n        uint32_t RESERVED2[15U];\n  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */\n        uint32_t RESERVED3[32U];\n        uint32_t RESERVED4[43U];\n  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */\n        uint32_t RESERVED5[1U];\n  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */\n        uint32_t RESERVED6[4U];\n  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */\n  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */\n  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */\n  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */\n  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */\n  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */\n  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */\n  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */\n  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */\n  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */\n  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */\n  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */\n} ITM_Type;\n\n/* ITM Stimulus Port Register Definitions */\n#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */\n#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */\n\n#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */\n#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */\n\n/* ITM Trace Privilege Register Definitions */\n#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */\n#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */\n\n/* ITM Trace Control Register Definitions */\n#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */\n#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */\n\n#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */\n#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */\n\n#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */\n#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */\n\n#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */\n#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */\n\n#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */\n#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */\n\n#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */\n#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */\n\n#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */\n#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */\n\n#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */\n#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */\n\n#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */\n#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */\n\n#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */\n#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */\n\n/* ITM Lock Status Register Definitions */\n#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */\n#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */\n\n#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */\n#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */\n\n#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */\n#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */\n\n/*@}*/ /* end of group CMSIS_ITM */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\n  \\brief    Type definitions for the Data Watchpoint and Trace (DWT)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\n  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */\n  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */\n  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */\n  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */\n  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */\n  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */\n  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\n  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\n        uint32_t RESERVED1[1U];\n  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\n        uint32_t RESERVED2[1U];\n  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\n        uint32_t RESERVED3[1U];\n  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\n        uint32_t RESERVED4[1U];\n  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\n        uint32_t RESERVED5[1U];\n  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\n        uint32_t RESERVED6[1U];\n  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\n        uint32_t RESERVED7[1U];\n  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\n        uint32_t RESERVED8[1U];\n  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */\n        uint32_t RESERVED9[1U];\n  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */\n        uint32_t RESERVED10[1U];\n  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */\n        uint32_t RESERVED11[1U];\n  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */\n        uint32_t RESERVED12[1U];\n  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */\n        uint32_t RESERVED13[1U];\n  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */\n        uint32_t RESERVED14[1U];\n  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */\n        uint32_t RESERVED15[1U];\n  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */\n        uint32_t RESERVED16[1U];\n  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */\n        uint32_t RESERVED17[1U];\n  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */\n        uint32_t RESERVED18[1U];\n  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */\n        uint32_t RESERVED19[1U];\n  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */\n        uint32_t RESERVED20[1U];\n  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */\n        uint32_t RESERVED21[1U];\n  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */\n        uint32_t RESERVED22[1U];\n  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */\n        uint32_t RESERVED23[1U];\n  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */\n        uint32_t RESERVED24[1U];\n  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */\n        uint32_t RESERVED25[1U];\n  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */\n        uint32_t RESERVED26[1U];\n  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */\n        uint32_t RESERVED27[1U];\n  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */\n        uint32_t RESERVED28[1U];\n  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */\n        uint32_t RESERVED29[1U];\n  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */\n        uint32_t RESERVED30[1U];\n  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */\n        uint32_t RESERVED31[1U];\n  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */\n        uint32_t RESERVED32[934U];\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */\n        uint32_t RESERVED33[1U];\n  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */\n} DWT_Type;\n\n/* DWT Control Register Definitions */\n#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\n#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\n\n#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\n#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\n\n#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\n#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\n\n#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\n#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\n\n#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\n#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\n\n#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */\n#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */\n\n#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */\n#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */\n\n#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */\n#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */\n\n#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */\n#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */\n\n#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */\n#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */\n\n#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */\n#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */\n\n#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */\n#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */\n\n#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */\n#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */\n\n#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */\n#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */\n\n#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */\n#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */\n\n#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */\n#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */\n\n#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */\n#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */\n\n#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */\n#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */\n\n#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */\n#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */\n\n/* DWT CPI Count Register Definitions */\n#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */\n#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */\n\n/* DWT Exception Overhead Count Register Definitions */\n#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */\n#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */\n\n/* DWT Sleep Count Register Definitions */\n#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */\n#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */\n\n/* DWT LSU Count Register Definitions */\n#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */\n#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */\n\n/* DWT Folded-instruction Count Register Definitions */\n#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */\n#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */\n\n/* DWT Comparator Function Register Definitions */\n#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */\n#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */\n\n#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\n#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\n\n#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\n#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\n\n#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */\n#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */\n\n#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */\n#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */\n\n/*@}*/ /* end of group CMSIS_DWT */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_TPI     Trace Port Interface (TPI)\n  \\brief    Type definitions for the Trace Port Interface (TPI)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Trace Port Interface Register (TPI).\n */\ntypedef struct\n{\n  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */\n  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */\n        uint32_t RESERVED0[2U];\n  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\n        uint32_t RESERVED1[55U];\n  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\n        uint32_t RESERVED2[131U];\n  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\n  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\n  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */\n        uint32_t RESERVED3[759U];\n  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */\n  __IM  uint32_t ITFTTD0;                /*!< Offset: 0xEEC (R/ )  Integration Test FIFO Test Data 0 Register */\n  __IOM uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/W)  Integration Test ATB Control Register 2 */\n        uint32_t RESERVED4[1U];\n  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  Integration Test ATB Control Register 0 */\n  __IM  uint32_t ITFTTD1;                /*!< Offset: 0xEFC (R/ )  Integration Test FIFO Test Data 1 Register */\n  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */\n        uint32_t RESERVED5[39U];\n  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */\n  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */\n        uint32_t RESERVED7[8U];\n  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  Device Configuration Register */\n  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Identifier Register */\n} TPI_Type;\n\n/* TPI Asynchronous Clock Prescaler Register Definitions */\n#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */\n#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */\n\n/* TPI Selected Pin Protocol Register Definitions */\n#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\n#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\n\n/* TPI Formatter and Flush Status Register Definitions */\n#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\n#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\n\n#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\n#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\n\n#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\n#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\n\n#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\n#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\n\n/* TPI Formatter and Flush Control Register Definitions */\n#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\n#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\n\n#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */\n#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */\n\n#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\n#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\n\n/* TPI TRIGGER Register Definitions */\n#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */\n#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */\n\n/* TPI Integration Test FIFO Test Data 0 Register Definitions */\n#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */\n#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */\n\n#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */\n#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */\n\n#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */\n#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */\n\n#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */\n#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */\n\n#define TPI_ITFTTD0_ATB_IF1_data2_Pos      16U                                         /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */\n#define TPI_ITFTTD0_ATB_IF1_data2_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */\n\n#define TPI_ITFTTD0_ATB_IF1_data1_Pos       8U                                         /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */\n#define TPI_ITFTTD0_ATB_IF1_data1_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */\n\n#define TPI_ITFTTD0_ATB_IF1_data0_Pos       0U                                          /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */\n#define TPI_ITFTTD0_ATB_IF1_data0_Msk      (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */\n\n/* TPI Integration Test ATB Control Register 2 Register Definitions */\n#define TPI_ITATBCTR2_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID2S Position */\n#define TPI_ITATBCTR2_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)      /*!< TPI ITATBCTR2: AFVALID2SS Mask */\n\n#define TPI_ITATBCTR2_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID1S Position */\n#define TPI_ITATBCTR2_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)      /*!< TPI ITATBCTR2: AFVALID1SS Mask */\n\n#define TPI_ITATBCTR2_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY2S Position */\n#define TPI_ITATBCTR2_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY2S Mask */\n\n#define TPI_ITATBCTR2_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY1S Position */\n#define TPI_ITATBCTR2_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY1S Mask */\n\n/* TPI Integration Test FIFO Test Data 1 Register Definitions */\n#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */\n#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */\n\n#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */\n#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */\n\n#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */\n#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */\n\n#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */\n#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */\n\n#define TPI_ITFTTD1_ATB_IF2_data2_Pos      16U                                         /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */\n#define TPI_ITFTTD1_ATB_IF2_data2_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */\n\n#define TPI_ITFTTD1_ATB_IF2_data1_Pos       8U                                         /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */\n#define TPI_ITFTTD1_ATB_IF2_data1_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */\n\n#define TPI_ITFTTD1_ATB_IF2_data0_Pos       0U                                          /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */\n#define TPI_ITFTTD1_ATB_IF2_data0_Msk      (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */\n\n/* TPI Integration Test ATB Control Register 0 Definitions */\n#define TPI_ITATBCTR0_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID2S Position */\n#define TPI_ITATBCTR0_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)      /*!< TPI ITATBCTR0: AFVALID2SS Mask */\n\n#define TPI_ITATBCTR0_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID1S Position */\n#define TPI_ITATBCTR0_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)      /*!< TPI ITATBCTR0: AFVALID1SS Mask */\n\n#define TPI_ITATBCTR0_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY2S Position */\n#define TPI_ITATBCTR0_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY2S Mask */\n\n#define TPI_ITATBCTR0_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY1S Position */\n#define TPI_ITATBCTR0_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY1S Mask */\n\n/* TPI Integration Mode Control Register Definitions */\n#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */\n#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */\n\n/* TPI DEVID Register Definitions */\n#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\n#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\n\n#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\n#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\n\n#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\n#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\n\n#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFOSZ Position */\n#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFOSZ Mask */\n\n#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */\n#define TPI_DEVID_NrTraceInput_Msk         (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */\n\n/* TPI DEVTYPE Register Definitions */\n#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */\n#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\n\n#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */\n#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\n\n/*@}*/ /* end of group CMSIS_TPI */\n\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\n */\ntypedef struct\n{\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\n  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */\n  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */\n  __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */\n  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */\n  __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */\n  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */\n  __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */\n        uint32_t RESERVED0[1];\n  union {\n  __IOM uint32_t MAIR[2];\n  struct {\n  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */\n  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */\n  };\n  };\n} MPU_Type;\n\n#define MPU_TYPE_RALIASES                  4U\n\n/* MPU Type Register Definitions */\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\n\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\n\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\n\n/* MPU Control Register Definitions */\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\n\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\n\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\n\n/* MPU Region Number Register Definitions */\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\n\n/* MPU Region Base Address Register Definitions */\n#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */\n#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */\n\n#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */\n#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */\n\n#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */\n#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */\n\n#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */\n#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */\n\n/* MPU Region Limit Address Register Definitions */\n#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */\n#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */\n\n#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */\n#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */\n\n#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */\n#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */\n\n/* MPU Memory Attribute Indirection Register 0 Definitions */\n#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */\n#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */\n\n#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */\n#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */\n\n#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */\n#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */\n\n#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */\n#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */\n\n/* MPU Memory Attribute Indirection Register 1 Definitions */\n#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */\n#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */\n\n#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */\n#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */\n\n#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */\n#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */\n\n#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */\n#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */\n\n/*@} end of group CMSIS_MPU */\n#endif\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SAU     Security Attribution Unit (SAU)\n  \\brief    Type definitions for the Security Attribution Unit (SAU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Security Attribution Unit (SAU).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */\n  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */\n#else\n        uint32_t RESERVED0[3];\n#endif\n  __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */\n  __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */\n} SAU_Type;\n\n/* SAU Control Register Definitions */\n#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */\n#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */\n\n#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */\n#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */\n\n/* SAU Type Register Definitions */\n#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */\n#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */\n\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n/* SAU Region Number Register Definitions */\n#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */\n#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */\n\n/* SAU Region Base Address Register Definitions */\n#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */\n#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */\n\n/* SAU Region Limit Address Register Definitions */\n#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */\n#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */\n\n#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */\n#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */\n\n#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */\n#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */\n\n#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\n\n/* Secure Fault Status Register Definitions */\n#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */\n#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */\n\n#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */\n#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */\n\n#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */\n#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */\n\n#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */\n#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */\n\n#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */\n#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */\n\n#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */\n#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */\n\n#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */\n#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */\n\n#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */\n#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */\n\n/*@} end of group CMSIS_SAU */\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_FPU     Floating Point Unit (FPU)\n  \\brief    Type definitions for the Floating Point Unit (FPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Floating Point Unit (FPU).\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1U];\n  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */\n  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */\n  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */\n  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */\n  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */\n} FPU_Type;\n\n/* Floating-Point Context Control Register Definitions */\n#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */\n#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */\n\n#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */\n#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */\n\n#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */\n#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */\n\n#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */\n#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */\n\n#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */\n#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */\n\n#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */\n#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */\n\n#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */\n#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */\n\n#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */\n#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */\n\n#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */\n#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */\n\n#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */\n#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */\n\n#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */\n#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */\n\n#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */\n#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */\n\n#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */\n#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */\n\n#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */\n#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */\n\n#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */\n#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */\n\n#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */\n#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */\n\n#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */\n#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */\n\n/* Floating-Point Context Address Register Definitions */\n#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */\n#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */\n\n/* Floating-Point Default Status Control Register Definitions */\n#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */\n#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */\n\n#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */\n#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */\n\n#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */\n#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */\n\n#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */\n#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */\n\n/* Media and FP Feature Register 0 Definitions */\n#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */\n#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */\n\n#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */\n#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */\n\n#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */\n#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */\n\n#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */\n#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */\n\n#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */\n#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */\n\n#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */\n#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */\n\n#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */\n#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */\n\n#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */\n#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */\n\n/* Media and FP Feature Register 1 Definitions */\n#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */\n#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */\n\n#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */\n#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */\n\n#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */\n#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */\n\n#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */\n#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */\n\n/*@} end of group CMSIS_FPU */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\n  \\brief    Type definitions for the Core Debug Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Core Debug Register (CoreDebug).\n */\ntypedef struct\n{\n  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\n  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\n  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\n  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\n        uint32_t RESERVED4[1U];\n  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */\n  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */\n} CoreDebug_Type;\n\n/* Debug Halting Control and Status Register Definitions */\n#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */\n#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\n\n#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */\n#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */\n\n#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */\n#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\n\n#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\n#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\n\n#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */\n#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\n\n#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */\n#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\n\n#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */\n#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\n\n#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */\n#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\n\n#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\n#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\n\n#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */\n#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\n\n#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */\n#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\n\n#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */\n#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\n\n#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */\n#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\n\n/* Debug Core Register Selector Register Definitions */\n#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */\n#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\n\n#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */\n#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */\n\n/* Debug Exception and Monitor Control Register Definitions */\n#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */\n#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */\n\n#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */\n#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */\n\n#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */\n#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */\n\n#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */\n#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */\n\n#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */\n#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */\n\n#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */\n#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\n\n#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */\n#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */\n\n#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */\n#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */\n\n#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */\n#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */\n\n#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */\n#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */\n\n#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */\n#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\n\n#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */\n#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */\n\n#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */\n#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */\n\n/* Debug Authentication Control Register Definitions */\n#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */\n#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */\n\n#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */\n#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */\n\n#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */\n#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */\n\n#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */\n#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */\n\n/* Debug Security Control and Status Register Definitions */\n#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */\n#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */\n\n#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */\n#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */\n\n#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */\n#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */\n\n/*@} end of group CMSIS_CoreDebug */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n/*@} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Core Hardware */\n  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */\n  #define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */\n  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */\n  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */\n  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */\n  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */\n  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */\n  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */\n\n  #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */\n  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */\n  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */\n  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */\n  #define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */\n  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */\n  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */\n  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */\n\n  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */\n    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */\n  #endif\n\n  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */\n    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */\n  #endif\n\n  #define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */\n  #define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */\n  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */\n  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */\n  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */\n  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */\n\n  #define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */\n  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */\n  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */\n  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */\n  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */\n\n  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */\n    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */\n  #endif\n\n  #define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */\n  #define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */\n\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n/*@} */\n\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Debug Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n#ifdef CMSIS_NVIC_VIRTUAL\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\n  #endif\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\n  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\n  #define NVIC_GetActive              __NVIC_GetActive\n  #define NVIC_SetPriority            __NVIC_SetPriority\n  #define NVIC_GetPriority            __NVIC_GetPriority\n  #define NVIC_SystemReset            __NVIC_SystemReset\n#endif /* CMSIS_NVIC_VIRTUAL */\n\n#ifdef CMSIS_VECTAB_VIRTUAL\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\n  #endif\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetVector              __NVIC_SetVector\n  #define NVIC_GetVector              __NVIC_GetVector\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\n\n#define NVIC_USER_IRQ_OFFSET          16\n\n\n/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */\n\n/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */\n#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */\n\n/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */\n#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */\n#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */\n#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */\n#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */\n#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */\n#define EXC_RETURN_SPSEL           (0x00000004UL)     /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP           */\n#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */\n\n/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */\n#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */\n#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */\n#else\n#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */\n#endif\n\n\n/**\n  \\brief   Set Priority Grouping\n  \\details Sets the priority grouping field using the required unlock sequence.\n           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\n           Only values from 0..7 are used.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]      PriorityGroup  Priority grouping field.\n */\n__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\n{\n  uint32_t reg_value;\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\n\n  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */\n  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\n  reg_value  =  (reg_value                                   |\n                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */\n  SCB->AIRCR =  reg_value;\n}\n\n\n/**\n  \\brief   Get Priority Grouping\n  \\details Reads the priority grouping field from the NVIC Interrupt Controller.\n  \\return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\n{\n  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\n}\n\n\n/**\n  \\brief   Enable Interrupt\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    __COMPILER_BARRIER();\n    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __COMPILER_BARRIER();\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __DSB();\n    __ISB();\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt\n  \\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Get Interrupt Target State\n  \\details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n  \\return             1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Target State\n  \\details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n                      1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Clear Interrupt Target State\n  \\details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n                      1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every processor exception.\n */\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n  else\n  {\n    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Encode Priority\n  \\details Encodes the priority for an interrupt with the given priority group,\n           preemptive priority value, and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\n */\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  return (\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\n         );\n}\n\n\n/**\n  \\brief   Decode Priority\n  \\details Decodes an interrupt priority value with a given priority group to\n           preemptive priority value and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\n */\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\n}\n\n\n/**\n  \\brief   Set Interrupt Vector\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n           VTOR must been relocated to SRAM before.\n  \\param [in]   IRQn      Interrupt number\n  \\param [in]   vector    Address of interrupt handler function\n */\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\n  __DSB();\n}\n\n\n/**\n  \\brief   Get Interrupt Vector\n  \\details Reads an interrupt vector from interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn      Interrupt number.\n  \\return                 Address of interrupt handler function\n */\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |\n                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\n                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Set Priority Grouping (non-secure)\n  \\details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.\n           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\n           Only values from 0..7 are used.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]      PriorityGroup  Priority grouping field.\n */\n__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)\n{\n  uint32_t reg_value;\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\n\n  reg_value  =  SCB_NS->AIRCR;                                                /* read old register configuration    */\n  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\n  reg_value  =  (reg_value                                   |\n                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */\n  SCB_NS->AIRCR =  reg_value;\n}\n\n\n/**\n  \\brief   Get Priority Grouping (non-secure)\n  \\details Reads the priority grouping field from the non-secure NVIC when in secure state.\n  \\return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)\n{\n  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\n}\n\n\n/**\n  \\brief   Enable Interrupt (non-secure)\n  \\details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status (non-secure)\n  \\details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt (non-secure)\n  \\details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt (non-secure)\n  \\details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt (non-secure)\n  \\details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt (non-secure)\n  \\details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt (non-secure)\n  \\details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Priority (non-secure)\n  \\details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every non-secure processor exception.\n */\n__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n  else\n  {\n    SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority (non-secure)\n  \\details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */\n\n/*@} end of CMSIS_Core_NVICFunctions */\n\n/* ##########################  MPU functions  #################################### */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n\n#include \"mpu_armv8.h\"\n\n#endif\n\n/* ##########################  FPU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\n  \\brief    Function that provides FPU type.\n  @{\n */\n\n/**\n  \\brief   get FPU type\n  \\details returns the FPU type\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n */\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\n{\n  uint32_t mvfr0;\n\n  mvfr0 = FPU->MVFR0;\n  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)\n  {\n    return 2U;           /* Double + Single precision FPU */\n  }\n  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)\n  {\n    return 1U;           /* Single precision FPU */\n  }\n  else\n  {\n    return 0U;           /* No FPU */\n  }\n}\n\n\n/*@} end of CMSIS_Core_FpuFunctions */\n\n\n\n/* ##########################   SAU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SAUFunctions SAU Functions\n  \\brief    Functions that configure the SAU.\n  @{\n */\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n\n/**\n  \\brief   Enable SAU\n  \\details Enables the Security Attribution Unit (SAU).\n */\n__STATIC_INLINE void TZ_SAU_Enable(void)\n{\n    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);\n}\n\n\n\n/**\n  \\brief   Disable SAU\n  \\details Disables the Security Attribution Unit (SAU).\n */\n__STATIC_INLINE void TZ_SAU_Disable(void)\n{\n    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);\n}\n\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n/*@} end of CMSIS_Core_SAUFunctions */\n\n\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   System Tick Configuration (non-secure)\n  \\details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n\n */\n__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                         /* Reload value impossible */\n  }\n\n  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */\n  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */\n  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                      SysTick_CTRL_TICKINT_Msk   |\n                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                           /* Function successful */\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n#endif\n\n/*@} end of CMSIS_Core_SysTickFunctions */\n\n\n\n/* ##################################### Debug In/Output function ########################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_core_DebugFunctions ITM Functions\n  \\brief    Functions that access the ITM debug interface.\n  @{\n */\n\nextern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */\n#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \\ref ITM_RxBuffer is ready for next character. */\n\n\n/**\n  \\brief   ITM Send Character\n  \\details Transmits a character via the ITM channel 0, and\n           \\li Just returns when no debugger is connected that has booked the output.\n           \\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\n  \\param [in]     ch  Character to transmit.\n  \\returns            Character to transmit.\n */\n__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\n{\n  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */\n      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */\n  {\n    while (ITM->PORT[0U].u32 == 0UL)\n    {\n      __NOP();\n    }\n    ITM->PORT[0U].u8 = (uint8_t)ch;\n  }\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Receive Character\n  \\details Inputs a character via the external variable \\ref ITM_RxBuffer.\n  \\return             Received character.\n  \\return         -1  No character pending.\n */\n__STATIC_INLINE int32_t ITM_ReceiveChar (void)\n{\n  int32_t ch = -1;                           /* no character available */\n\n  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\n  {\n    ch = ITM_RxBuffer;\n    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */\n  }\n\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Check Character\n  \\details Checks whether a character is pending for reading in the variable \\ref ITM_RxBuffer.\n  \\return          0  No character available.\n  \\return          1  Character available.\n */\n__STATIC_INLINE int32_t ITM_CheckChar (void)\n{\n\n  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\n  {\n    return (0);                              /* no character available */\n  }\n  else\n  {\n    return (1);                              /*    character available */\n  }\n}\n\n/*@} end of CMSIS_core_DebugFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM33_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n"
  },
  {
    "path": "3rd_party/CMSIS/Include/core_cm35p.h",
    "content": "/**************************************************************************//**\n * @file     core_cm35p.h\n * @brief    CMSIS Cortex-M35P Core Peripheral Access Layer Header File\n * @version  V1.0.0\n * @date     12. November 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CORE_CM35P_H_GENERIC\n#define __CORE_CM35P_H_GENERIC\n\n#include <stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup Cortex_M35P\n  @{\n */\n\n#include \"cmsis_version.h\"\n\n/*  CMSIS CM35P definitions */\n#define __CM35P_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                  /*!< \\deprecated [31:16] CMSIS HAL main version */\n#define __CM35P_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                   /*!< \\deprecated [15:0]  CMSIS HAL sub version */\n#define __CM35P_CMSIS_VERSION       ((__CM35P_CMSIS_VERSION_MAIN << 16U) | \\\n                                      __CM35P_CMSIS_VERSION_SUB           )    /*!< \\deprecated CMSIS HAL version number */\n\n#define __CORTEX_M                 (35U)                                       /*!< Cortex-M Core */\n\n/** __FPU_USED indicates whether an FPU is used or not.\n    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\n*/\n#if defined ( __CC_ARM )\n  #if defined (__TARGET_FPU_VFP)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)\n    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED         0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined (__ARM_FP)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #warning \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)\n    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED         0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)\n    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED         0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined (__ARMVFP__)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)\n    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED         0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined ( __TI_ARM__ )\n  #if defined (__TI_VFP_SUPPORT__)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined (__FPU_VFP__)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM35P_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_CM35P_H_DEPENDANT\n#define __CORE_CM35P_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __CM35P_REV\n    #define __CM35P_REV               0x0000U\n    #warning \"__CM35P_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __FPU_PRESENT\n    #define __FPU_PRESENT             0U\n    #warning \"__FPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __MPU_PRESENT\n    #define __MPU_PRESENT             0U\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __SAUREGION_PRESENT\n    #define __SAUREGION_PRESENT       0U\n    #warning \"__SAUREGION_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __DSP_PRESENT\n    #define __DSP_PRESENT             0U\n    #warning \"__DSP_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          3U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/*@} end of group Cortex_M35P */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core SCB Register\n  - Core SysTick Register\n  - Core Debug Register\n  - Core MPU Register\n  - Core SAU Register\n  - Core FPU Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for Cortex-M processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */\n    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\n    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */\n#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */\n\n#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */\n#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */\n    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\n    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\n    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */\n#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */\n\n#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */\n#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */\n#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */\n    uint32_t FPCA:1;                     /*!< bit:      2  Floating-point context active */\n    uint32_t SFPA:1;                     /*!< bit:      3  Secure floating-point active */\n    uint32_t _reserved1:28;              /*!< bit:  4..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */\n#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */\n\n#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */\n#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */\n\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\n#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\n\n/*@} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[16U];\n  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RSERVED1[16U];\n  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[16U];\n  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[16U];\n  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\n        uint32_t RESERVED4[16U];\n  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */\n        uint32_t RESERVED5[16U];\n  __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */\n        uint32_t RESERVED6[580U];\n  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */\n}  NVIC_Type;\n\n/* Software Triggered Interrupt Register Definitions */\n#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */\n#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */\n\n/*@} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */\n  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */\n  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */\n  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */\n  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */\n  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */\n  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */\n  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */\n  __IM  uint32_t ID_ADR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */\n  __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */\n  __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */\n  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */\n  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */\n  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */\n  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */\n  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */\n  __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */\n        uint32_t RESERVED3[92U];\n  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */\n        uint32_t RESERVED4[15U];\n  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */\n  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */\n  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */\n        uint32_t RESERVED5[1U];\n  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */\n        uint32_t RESERVED6[1U];\n  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */\n  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */\n  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */\n  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */\n  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */\n  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */\n  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */\n  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */\n} SCB_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */\n#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */\n\n#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */\n#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */\n\n#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */\n#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */\n#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\n#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n/* SCB Vector Table Offset Register Definitions */\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\n#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */\n#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */\n\n#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */\n#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */\n\n#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */\n#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */\n\n#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */\n#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */\n#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */\n#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */\n\n#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */\n#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */\n\n#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */\n#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */\n\n#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */\n#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */\n\n#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\n#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\n\n#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\n#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\n#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */\n#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */\n\n#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */\n#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */\n\n#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */\n#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */\n\n#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */\n#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */\n\n#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */\n#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */\n\n#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */\n#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */\n\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */\n#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */\n\n#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */\n#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */\n\n#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */\n#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */\n\n#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\n#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\n\n#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\n#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\n\n#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */\n#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */\n\n#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\n#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\n\n#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */\n#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */\n\n#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */\n#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */\n\n#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */\n#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */\n\n#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */\n#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */\n\n#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */\n#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */\n\n#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */\n#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */\n\n/* SCB Configurable Fault Status Register Definitions */\n#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */\n#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */\n\n#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */\n#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */\n\n#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */\n#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\n\n/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */\n#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */\n\n#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */\n#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */\n\n#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */\n#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */\n\n#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\n#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\n\n#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */\n#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\n\n#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */\n#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\n\n/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */\n#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */\n\n#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */\n#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */\n\n#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */\n#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */\n\n#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */\n#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */\n\n#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */\n#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\n\n#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */\n#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */\n\n#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */\n#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */\n\n/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */\n#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\n\n#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */\n#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */\n\n#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */\n#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */\n\n#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */\n#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */\n\n#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */\n#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */\n\n#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */\n#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */\n\n#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\n#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\n\n/* SCB Hard Fault Status Register Definitions */\n#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */\n#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */\n\n#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */\n#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */\n\n#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */\n#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */\n\n/* SCB Debug Fault Status Register Definitions */\n#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */\n#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */\n\n#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */\n#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */\n\n#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */\n#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */\n\n#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */\n#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */\n\n#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */\n#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */\n\n/* SCB Non-Secure Access Control Register Definitions */\n#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */\n#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */\n\n#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */\n#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */\n\n#define SCB_NSACR_CPn_Pos                   0U                                            /*!< SCB NSACR: CPn Position */\n#define SCB_NSACR_CPn_Msk                  (1UL /*<< SCB_NSACR_CPn_Pos*/)                 /*!< SCB NSACR: CPn Mask */\n\n/* SCB Cache Level ID Register Definitions */\n#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */\n#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */\n\n#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */\n#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */\n\n/* SCB Cache Type Register Definitions */\n#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */\n#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */\n\n#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */\n#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */\n\n#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */\n#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */\n\n#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */\n#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */\n\n#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */\n#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */\n\n/* SCB Cache Size ID Register Definitions */\n#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */\n#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */\n\n#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */\n#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */\n\n#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */\n#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */\n\n#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */\n#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */\n\n#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */\n#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */\n\n#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */\n#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */\n\n#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */\n#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */\n\n/* SCB Cache Size Selection Register Definitions */\n#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */\n#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */\n\n#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */\n#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */\n\n/* SCB Software Triggered Interrupt Register Definitions */\n#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */\n#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */\n\n/* SCB D-Cache Invalidate by Set-way Register Definitions */\n#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */\n#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */\n\n#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */\n#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */\n\n/* SCB D-Cache Clean by Set-way Register Definitions */\n#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */\n#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */\n\n#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */\n#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */\n\n/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */\n#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */\n#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */\n\n#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */\n#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */\n\n/*@} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\n  \\brief    Type definitions for the System Control and ID Register not in the SCB\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control and ID Register not in the SCB.\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1U];\n  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */\n  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\n  __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */\n} SCnSCB_Type;\n\n/* Interrupt Controller Type Register Definitions */\n#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */\n#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */\n\n/*@} end of group CMSIS_SCnotSCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/*@} end of group CMSIS_SysTick */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)\n  \\brief    Type definitions for the Instrumentation Trace Macrocell (ITM)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).\n */\ntypedef struct\n{\n  __OM  union\n  {\n    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */\n    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */\n    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */\n  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */\n        uint32_t RESERVED0[864U];\n  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */\n        uint32_t RESERVED1[15U];\n  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */\n        uint32_t RESERVED2[15U];\n  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */\n        uint32_t RESERVED3[32U];\n        uint32_t RESERVED4[43U];\n  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */\n        uint32_t RESERVED5[1U];\n  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */\n        uint32_t RESERVED6[4U];\n  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */\n  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */\n  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */\n  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */\n  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */\n  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */\n  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */\n  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */\n  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */\n  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */\n  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */\n  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */\n} ITM_Type;\n\n/* ITM Stimulus Port Register Definitions */\n#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */\n#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */\n\n#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */\n#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */\n\n/* ITM Trace Privilege Register Definitions */\n#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */\n#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */\n\n/* ITM Trace Control Register Definitions */\n#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */\n#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */\n\n#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */\n#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */\n\n#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */\n#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */\n\n#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */\n#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */\n\n#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */\n#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */\n\n#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */\n#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */\n\n#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */\n#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */\n\n#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */\n#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */\n\n#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */\n#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */\n\n#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */\n#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */\n\n/* ITM Lock Status Register Definitions */\n#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */\n#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */\n\n#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */\n#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */\n\n#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */\n#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */\n\n/*@}*/ /* end of group CMSIS_ITM */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\n  \\brief    Type definitions for the Data Watchpoint and Trace (DWT)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\n  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */\n  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */\n  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */\n  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */\n  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */\n  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */\n  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\n  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\n        uint32_t RESERVED1[1U];\n  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\n        uint32_t RESERVED2[1U];\n  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\n        uint32_t RESERVED3[1U];\n  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\n        uint32_t RESERVED4[1U];\n  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\n        uint32_t RESERVED5[1U];\n  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\n        uint32_t RESERVED6[1U];\n  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\n        uint32_t RESERVED7[1U];\n  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\n        uint32_t RESERVED8[1U];\n  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */\n        uint32_t RESERVED9[1U];\n  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */\n        uint32_t RESERVED10[1U];\n  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */\n        uint32_t RESERVED11[1U];\n  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */\n        uint32_t RESERVED12[1U];\n  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */\n        uint32_t RESERVED13[1U];\n  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */\n        uint32_t RESERVED14[1U];\n  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */\n        uint32_t RESERVED15[1U];\n  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */\n        uint32_t RESERVED16[1U];\n  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */\n        uint32_t RESERVED17[1U];\n  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */\n        uint32_t RESERVED18[1U];\n  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */\n        uint32_t RESERVED19[1U];\n  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */\n        uint32_t RESERVED20[1U];\n  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */\n        uint32_t RESERVED21[1U];\n  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */\n        uint32_t RESERVED22[1U];\n  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */\n        uint32_t RESERVED23[1U];\n  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */\n        uint32_t RESERVED24[1U];\n  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */\n        uint32_t RESERVED25[1U];\n  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */\n        uint32_t RESERVED26[1U];\n  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */\n        uint32_t RESERVED27[1U];\n  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */\n        uint32_t RESERVED28[1U];\n  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */\n        uint32_t RESERVED29[1U];\n  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */\n        uint32_t RESERVED30[1U];\n  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */\n        uint32_t RESERVED31[1U];\n  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */\n        uint32_t RESERVED32[934U];\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */\n        uint32_t RESERVED33[1U];\n  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */\n} DWT_Type;\n\n/* DWT Control Register Definitions */\n#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\n#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\n\n#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\n#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\n\n#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\n#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\n\n#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\n#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\n\n#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\n#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\n\n#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */\n#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */\n\n#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */\n#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */\n\n#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */\n#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */\n\n#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */\n#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */\n\n#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */\n#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */\n\n#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */\n#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */\n\n#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */\n#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */\n\n#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */\n#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */\n\n#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */\n#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */\n\n#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */\n#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */\n\n#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */\n#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */\n\n#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */\n#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */\n\n#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */\n#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */\n\n#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */\n#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */\n\n/* DWT CPI Count Register Definitions */\n#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */\n#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */\n\n/* DWT Exception Overhead Count Register Definitions */\n#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */\n#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */\n\n/* DWT Sleep Count Register Definitions */\n#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */\n#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */\n\n/* DWT LSU Count Register Definitions */\n#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */\n#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */\n\n/* DWT Folded-instruction Count Register Definitions */\n#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */\n#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */\n\n/* DWT Comparator Function Register Definitions */\n#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */\n#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */\n\n#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\n#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\n\n#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\n#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\n\n#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */\n#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */\n\n#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */\n#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */\n\n/*@}*/ /* end of group CMSIS_DWT */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_TPI     Trace Port Interface (TPI)\n  \\brief    Type definitions for the Trace Port Interface (TPI)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Trace Port Interface Register (TPI).\n */\ntypedef struct\n{\n  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */\n  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */\n        uint32_t RESERVED0[2U];\n  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\n        uint32_t RESERVED1[55U];\n  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\n        uint32_t RESERVED2[131U];\n  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\n  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\n  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */\n        uint32_t RESERVED3[759U];\n  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */\n  __IM  uint32_t ITFTTD0;                /*!< Offset: 0xEEC (R/ )  Integration Test FIFO Test Data 0 Register */\n  __IOM uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/W)  Integration Test ATB Control Register 2 */\n        uint32_t RESERVED4[1U];\n  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  Integration Test ATB Control Register 0 */\n  __IM  uint32_t ITFTTD1;                /*!< Offset: 0xEFC (R/ )  Integration Test FIFO Test Data 1 Register */\n  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */\n        uint32_t RESERVED5[39U];\n  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */\n  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */\n        uint32_t RESERVED7[8U];\n  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  Device Configuration Register */\n  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Identifier Register */\n} TPI_Type;\n\n/* TPI Asynchronous Clock Prescaler Register Definitions */\n#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */\n#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */\n\n/* TPI Selected Pin Protocol Register Definitions */\n#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\n#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\n\n/* TPI Formatter and Flush Status Register Definitions */\n#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\n#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\n\n#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\n#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\n\n#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\n#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\n\n#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\n#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\n\n/* TPI Formatter and Flush Control Register Definitions */\n#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\n#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\n\n#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */\n#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */\n\n#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\n#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\n\n/* TPI TRIGGER Register Definitions */\n#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */\n#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */\n\n/* TPI Integration Test FIFO Test Data 0 Register Definitions */\n#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */\n#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */\n\n#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */\n#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */\n\n#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */\n#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */\n\n#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */\n#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */\n\n#define TPI_ITFTTD0_ATB_IF1_data2_Pos      16U                                         /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */\n#define TPI_ITFTTD0_ATB_IF1_data2_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */\n\n#define TPI_ITFTTD0_ATB_IF1_data1_Pos       8U                                         /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */\n#define TPI_ITFTTD0_ATB_IF1_data1_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */\n\n#define TPI_ITFTTD0_ATB_IF1_data0_Pos       0U                                          /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */\n#define TPI_ITFTTD0_ATB_IF1_data0_Msk      (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */\n\n/* TPI Integration Test ATB Control Register 2 Register Definitions */\n#define TPI_ITATBCTR2_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID2S Position */\n#define TPI_ITATBCTR2_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)      /*!< TPI ITATBCTR2: AFVALID2SS Mask */\n\n#define TPI_ITATBCTR2_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID1S Position */\n#define TPI_ITATBCTR2_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)      /*!< TPI ITATBCTR2: AFVALID1SS Mask */\n\n#define TPI_ITATBCTR2_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY2S Position */\n#define TPI_ITATBCTR2_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY2S Mask */\n\n#define TPI_ITATBCTR2_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY1S Position */\n#define TPI_ITATBCTR2_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY1S Mask */\n\n/* TPI Integration Test FIFO Test Data 1 Register Definitions */\n#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */\n#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */\n\n#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */\n#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */\n\n#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */\n#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */\n\n#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */\n#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */\n\n#define TPI_ITFTTD1_ATB_IF2_data2_Pos      16U                                         /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */\n#define TPI_ITFTTD1_ATB_IF2_data2_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */\n\n#define TPI_ITFTTD1_ATB_IF2_data1_Pos       8U                                         /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */\n#define TPI_ITFTTD1_ATB_IF2_data1_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */\n\n#define TPI_ITFTTD1_ATB_IF2_data0_Pos       0U                                          /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */\n#define TPI_ITFTTD1_ATB_IF2_data0_Msk      (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */\n\n/* TPI Integration Test ATB Control Register 0 Definitions */\n#define TPI_ITATBCTR0_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID2S Position */\n#define TPI_ITATBCTR0_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)      /*!< TPI ITATBCTR0: AFVALID2SS Mask */\n\n#define TPI_ITATBCTR0_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID1S Position */\n#define TPI_ITATBCTR0_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)      /*!< TPI ITATBCTR0: AFVALID1SS Mask */\n\n#define TPI_ITATBCTR0_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY2S Position */\n#define TPI_ITATBCTR0_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY2S Mask */\n\n#define TPI_ITATBCTR0_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY1S Position */\n#define TPI_ITATBCTR0_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY1S Mask */\n\n/* TPI Integration Mode Control Register Definitions */\n#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */\n#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */\n\n/* TPI DEVID Register Definitions */\n#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\n#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\n\n#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\n#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\n\n#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\n#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\n\n#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFOSZ Position */\n#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFOSZ Mask */\n\n#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */\n#define TPI_DEVID_NrTraceInput_Msk         (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */\n\n/* TPI DEVTYPE Register Definitions */\n#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */\n#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\n\n#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */\n#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\n\n/*@}*/ /* end of group CMSIS_TPI */\n\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\n */\ntypedef struct\n{\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\n  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */\n  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */\n  __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */\n  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */\n  __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */\n  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */\n  __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */\n        uint32_t RESERVED0[1];\n  union {\n  __IOM uint32_t MAIR[2];\n  struct {\n  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */\n  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */\n  };\n  };\n} MPU_Type;\n\n#define MPU_TYPE_RALIASES                  4U\n\n/* MPU Type Register Definitions */\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\n\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\n\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\n\n/* MPU Control Register Definitions */\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\n\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\n\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\n\n/* MPU Region Number Register Definitions */\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\n\n/* MPU Region Base Address Register Definitions */\n#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */\n#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */\n\n#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */\n#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */\n\n#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */\n#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */\n\n#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */\n#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */\n\n/* MPU Region Limit Address Register Definitions */\n#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */\n#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */\n\n#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */\n#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */\n\n#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */\n#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */\n\n/* MPU Memory Attribute Indirection Register 0 Definitions */\n#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */\n#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */\n\n#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */\n#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */\n\n#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */\n#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */\n\n#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */\n#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */\n\n/* MPU Memory Attribute Indirection Register 1 Definitions */\n#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */\n#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */\n\n#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */\n#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */\n\n#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */\n#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */\n\n#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */\n#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */\n\n/*@} end of group CMSIS_MPU */\n#endif\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SAU     Security Attribution Unit (SAU)\n  \\brief    Type definitions for the Security Attribution Unit (SAU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Security Attribution Unit (SAU).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */\n  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */\n#else\n        uint32_t RESERVED0[3];\n#endif\n  __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */\n  __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */\n} SAU_Type;\n\n/* SAU Control Register Definitions */\n#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */\n#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */\n\n#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */\n#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */\n\n/* SAU Type Register Definitions */\n#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */\n#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */\n\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n/* SAU Region Number Register Definitions */\n#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */\n#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */\n\n/* SAU Region Base Address Register Definitions */\n#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */\n#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */\n\n/* SAU Region Limit Address Register Definitions */\n#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */\n#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */\n\n#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */\n#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */\n\n#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */\n#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */\n\n#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\n\n/* Secure Fault Status Register Definitions */\n#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */\n#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */\n\n#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */\n#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */\n\n#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */\n#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */\n\n#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */\n#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */\n\n#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */\n#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */\n\n#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */\n#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */\n\n#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */\n#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */\n\n#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */\n#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */\n\n/*@} end of group CMSIS_SAU */\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_FPU     Floating Point Unit (FPU)\n  \\brief    Type definitions for the Floating Point Unit (FPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Floating Point Unit (FPU).\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1U];\n  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */\n  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */\n  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */\n  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */\n  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */\n} FPU_Type;\n\n/* Floating-Point Context Control Register Definitions */\n#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */\n#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */\n\n#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */\n#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */\n\n#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */\n#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */\n\n#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */\n#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */\n\n#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */\n#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */\n\n#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */\n#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */\n\n#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */\n#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */\n\n#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */\n#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */\n\n#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */\n#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */\n\n#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */\n#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */\n\n#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */\n#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */\n\n#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */\n#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */\n\n#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */\n#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */\n\n#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */\n#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */\n\n#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */\n#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */\n\n#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */\n#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */\n\n#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */\n#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */\n\n/* Floating-Point Context Address Register Definitions */\n#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */\n#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */\n\n/* Floating-Point Default Status Control Register Definitions */\n#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */\n#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */\n\n#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */\n#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */\n\n#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */\n#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */\n\n#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */\n#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */\n\n/* Media and FP Feature Register 0 Definitions */\n#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */\n#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */\n\n#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */\n#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */\n\n#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */\n#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */\n\n#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */\n#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */\n\n#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */\n#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */\n\n#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */\n#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */\n\n#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */\n#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */\n\n#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */\n#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */\n\n/* Media and FP Feature Register 1 Definitions */\n#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */\n#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */\n\n#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */\n#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */\n\n#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */\n#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */\n\n#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */\n#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */\n\n/*@} end of group CMSIS_FPU */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\n  \\brief    Type definitions for the Core Debug Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Core Debug Register (CoreDebug).\n */\ntypedef struct\n{\n  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\n  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\n  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\n  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\n        uint32_t RESERVED4[1U];\n  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */\n  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */\n} CoreDebug_Type;\n\n/* Debug Halting Control and Status Register Definitions */\n#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */\n#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\n\n#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */\n#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */\n\n#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */\n#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\n\n#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\n#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\n\n#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */\n#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\n\n#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */\n#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\n\n#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */\n#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\n\n#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */\n#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\n\n#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\n#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\n\n#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */\n#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\n\n#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */\n#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\n\n#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */\n#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\n\n#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */\n#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\n\n/* Debug Core Register Selector Register Definitions */\n#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */\n#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\n\n#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */\n#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */\n\n/* Debug Exception and Monitor Control Register Definitions */\n#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */\n#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */\n\n#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */\n#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */\n\n#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */\n#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */\n\n#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */\n#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */\n\n#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */\n#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */\n\n#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */\n#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\n\n#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */\n#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */\n\n#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */\n#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */\n\n#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */\n#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */\n\n#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */\n#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */\n\n#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */\n#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\n\n#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */\n#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */\n\n#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */\n#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */\n\n/* Debug Authentication Control Register Definitions */\n#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */\n#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */\n\n#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */\n#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */\n\n#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */\n#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */\n\n#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */\n#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */\n\n/* Debug Security Control and Status Register Definitions */\n#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */\n#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */\n\n#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */\n#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */\n\n#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */\n#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */\n\n/*@} end of group CMSIS_CoreDebug */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n/*@} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Core Hardware */\n  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */\n  #define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */\n  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */\n  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */\n  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */\n  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */\n  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */\n  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */\n\n  #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */\n  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */\n  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */\n  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */\n  #define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */\n  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */\n  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */\n  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */\n\n  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */\n    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */\n  #endif\n\n  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */\n    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */\n  #endif\n\n  #define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */\n  #define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */\n  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */\n  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */\n  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */\n  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */\n\n  #define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */\n  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */\n  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */\n  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */\n  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */\n\n  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */\n    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */\n  #endif\n\n  #define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */\n  #define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */\n\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n/*@} */\n\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Debug Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n#ifdef CMSIS_NVIC_VIRTUAL\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\n  #endif\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\n  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\n  #define NVIC_GetActive              __NVIC_GetActive\n  #define NVIC_SetPriority            __NVIC_SetPriority\n  #define NVIC_GetPriority            __NVIC_GetPriority\n  #define NVIC_SystemReset            __NVIC_SystemReset\n#endif /* CMSIS_NVIC_VIRTUAL */\n\n#ifdef CMSIS_VECTAB_VIRTUAL\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\n  #endif\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetVector              __NVIC_SetVector\n  #define NVIC_GetVector              __NVIC_GetVector\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\n\n#define NVIC_USER_IRQ_OFFSET          16\n\n\n/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */\n\n/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */\n#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */\n\n/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */\n#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */\n#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */\n#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */\n#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */\n#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */\n#define EXC_RETURN_SPSEL           (0x00000004UL)     /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP           */\n#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */\n\n/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */\n#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */\n#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */\n#else\n#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */\n#endif\n\n\n/**\n  \\brief   Set Priority Grouping\n  \\details Sets the priority grouping field using the required unlock sequence.\n           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\n           Only values from 0..7 are used.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]      PriorityGroup  Priority grouping field.\n */\n__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\n{\n  uint32_t reg_value;\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\n\n  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */\n  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\n  reg_value  =  (reg_value                                   |\n                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */\n  SCB->AIRCR =  reg_value;\n}\n\n\n/**\n  \\brief   Get Priority Grouping\n  \\details Reads the priority grouping field from the NVIC Interrupt Controller.\n  \\return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\n{\n  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\n}\n\n\n/**\n  \\brief   Enable Interrupt\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    __COMPILER_BARRIER();\n    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __COMPILER_BARRIER();\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __DSB();\n    __ISB();\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt\n  \\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Get Interrupt Target State\n  \\details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n  \\return             1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Target State\n  \\details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n                      1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Clear Interrupt Target State\n  \\details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n                      1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every processor exception.\n */\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n  else\n  {\n    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Encode Priority\n  \\details Encodes the priority for an interrupt with the given priority group,\n           preemptive priority value, and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\n */\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  return (\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\n         );\n}\n\n\n/**\n  \\brief   Decode Priority\n  \\details Decodes an interrupt priority value with a given priority group to\n           preemptive priority value and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\n */\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\n}\n\n\n/**\n  \\brief   Set Interrupt Vector\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n           VTOR must been relocated to SRAM before.\n  \\param [in]   IRQn      Interrupt number\n  \\param [in]   vector    Address of interrupt handler function\n */\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\n  __DSB();\n}\n\n\n/**\n  \\brief   Get Interrupt Vector\n  \\details Reads an interrupt vector from interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn      Interrupt number.\n  \\return                 Address of interrupt handler function\n */\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |\n                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\n                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Set Priority Grouping (non-secure)\n  \\details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.\n           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\n           Only values from 0..7 are used.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]      PriorityGroup  Priority grouping field.\n */\n__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)\n{\n  uint32_t reg_value;\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\n\n  reg_value  =  SCB_NS->AIRCR;                                                /* read old register configuration    */\n  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\n  reg_value  =  (reg_value                                   |\n                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */\n  SCB_NS->AIRCR =  reg_value;\n}\n\n\n/**\n  \\brief   Get Priority Grouping (non-secure)\n  \\details Reads the priority grouping field from the non-secure NVIC when in secure state.\n  \\return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)\n{\n  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\n}\n\n\n/**\n  \\brief   Enable Interrupt (non-secure)\n  \\details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status (non-secure)\n  \\details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt (non-secure)\n  \\details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt (non-secure)\n  \\details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt (non-secure)\n  \\details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt (non-secure)\n  \\details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt (non-secure)\n  \\details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Priority (non-secure)\n  \\details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every non-secure processor exception.\n */\n__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n  else\n  {\n    SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority (non-secure)\n  \\details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */\n\n/*@} end of CMSIS_Core_NVICFunctions */\n\n/* ##########################  MPU functions  #################################### */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n\n#include \"mpu_armv8.h\"\n\n#endif\n\n/* ##########################  FPU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\n  \\brief    Function that provides FPU type.\n  @{\n */\n\n/**\n  \\brief   get FPU type\n  \\details returns the FPU type\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n */\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\n{\n  uint32_t mvfr0;\n\n  mvfr0 = FPU->MVFR0;\n  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)\n  {\n    return 2U;           /* Double + Single precision FPU */\n  }\n  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)\n  {\n    return 1U;           /* Single precision FPU */\n  }\n  else\n  {\n    return 0U;           /* No FPU */\n  }\n}\n\n\n/*@} end of CMSIS_Core_FpuFunctions */\n\n\n\n/* ##########################   SAU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SAUFunctions SAU Functions\n  \\brief    Functions that configure the SAU.\n  @{\n */\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n\n/**\n  \\brief   Enable SAU\n  \\details Enables the Security Attribution Unit (SAU).\n */\n__STATIC_INLINE void TZ_SAU_Enable(void)\n{\n    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);\n}\n\n\n\n/**\n  \\brief   Disable SAU\n  \\details Disables the Security Attribution Unit (SAU).\n */\n__STATIC_INLINE void TZ_SAU_Disable(void)\n{\n    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);\n}\n\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n/*@} end of CMSIS_Core_SAUFunctions */\n\n\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   System Tick Configuration (non-secure)\n  \\details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n\n */\n__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                         /* Reload value impossible */\n  }\n\n  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */\n  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */\n  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                      SysTick_CTRL_TICKINT_Msk   |\n                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                           /* Function successful */\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n#endif\n\n/*@} end of CMSIS_Core_SysTickFunctions */\n\n\n\n/* ##################################### Debug In/Output function ########################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_core_DebugFunctions ITM Functions\n  \\brief    Functions that access the ITM debug interface.\n  @{\n */\n\nextern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */\n#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \\ref ITM_RxBuffer is ready for next character. */\n\n\n/**\n  \\brief   ITM Send Character\n  \\details Transmits a character via the ITM channel 0, and\n           \\li Just returns when no debugger is connected that has booked the output.\n           \\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\n  \\param [in]     ch  Character to transmit.\n  \\returns            Character to transmit.\n */\n__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\n{\n  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */\n      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */\n  {\n    while (ITM->PORT[0U].u32 == 0UL)\n    {\n      __NOP();\n    }\n    ITM->PORT[0U].u8 = (uint8_t)ch;\n  }\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Receive Character\n  \\details Inputs a character via the external variable \\ref ITM_RxBuffer.\n  \\return             Received character.\n  \\return         -1  No character pending.\n */\n__STATIC_INLINE int32_t ITM_ReceiveChar (void)\n{\n  int32_t ch = -1;                           /* no character available */\n\n  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\n  {\n    ch = ITM_RxBuffer;\n    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */\n  }\n\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Check Character\n  \\details Checks whether a character is pending for reading in the variable \\ref ITM_RxBuffer.\n  \\return          0  No character available.\n  \\return          1  Character available.\n */\n__STATIC_INLINE int32_t ITM_CheckChar (void)\n{\n\n  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\n  {\n    return (0);                              /* no character available */\n  }\n  else\n  {\n    return (1);                              /*    character available */\n  }\n}\n\n/*@} end of CMSIS_core_DebugFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM35P_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n"
  },
  {
    "path": "3rd_party/CMSIS/Include/core_cm4.h",
    "content": "/**************************************************************************//**\n * @file     core_cm4.h\n * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File\n * @version  V5.1.0\n * @date     13. March 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CORE_CM4_H_GENERIC\n#define __CORE_CM4_H_GENERIC\n\n#include <stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup Cortex_M4\n  @{\n */\n\n#include \"cmsis_version.h\"\n\n/* CMSIS CM4 definitions */\n#define __CM4_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \\deprecated [31:16] CMSIS HAL main version */\n#define __CM4_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \\deprecated [15:0]  CMSIS HAL sub version */\n#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16U) | \\\n                                    __CM4_CMSIS_VERSION_SUB           )  /*!< \\deprecated CMSIS HAL version number */\n\n#define __CORTEX_M                (4U)                                   /*!< Cortex-M Core */\n\n/** __FPU_USED indicates whether an FPU is used or not.\n    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\n*/\n#if defined ( __CC_ARM )\n  #if defined __TARGET_FPU_VFP\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined __ARM_FP\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #warning \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined __ARMVFP__\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __TI_ARM__ )\n  #if defined __TI_VFP_SUPPORT__\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined __FPU_VFP__\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM4_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_CM4_H_DEPENDANT\n#define __CORE_CM4_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __CM4_REV\n    #define __CM4_REV               0x0000U\n    #warning \"__CM4_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __FPU_PRESENT\n    #define __FPU_PRESENT             0U\n    #warning \"__FPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __MPU_PRESENT\n    #define __MPU_PRESENT             0U\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          3U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/*@} end of group Cortex_M4 */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core SCB Register\n  - Core SysTick Register\n  - Core Debug Register\n  - Core MPU Register\n  - Core FPU Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for Cortex-M processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */\n    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\n    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */\n#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */\n\n#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */\n#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */\n    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */\n    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\n    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit */\n    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */\n#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */\n\n#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */\n#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */\n#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */\n\n#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */\n#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\n    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */\n    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */\n#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */\n\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\n#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\n\n/*@} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[24U];\n  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RESERVED1[24U];\n  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[24U];\n  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[24U];\n  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\n        uint32_t RESERVED4[56U];\n  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */\n        uint32_t RESERVED5[644U];\n  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */\n}  NVIC_Type;\n\n/* Software Triggered Interrupt Register Definitions */\n#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */\n#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */\n\n/*@} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */\n  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */\n  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */\n  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */\n  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */\n  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */\n  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */\n  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */\n  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */\n  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */\n  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */\n        uint32_t RESERVED0[5U];\n  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */\n} SCB_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\n#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\n#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n/* SCB Vector Table Offset Register Definitions */\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\n#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */\n#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */\n#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\n#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\n\n#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\n#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\n\n#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\n#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\n#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\n\n#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */\n#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */\n#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */\n\n#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */\n#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */\n\n#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */\n#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */\n\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */\n#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */\n\n#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */\n#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */\n\n#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */\n#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */\n\n#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\n#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\n\n#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\n#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\n\n#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */\n#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */\n\n#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\n#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\n\n#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */\n#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */\n\n#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */\n#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */\n\n#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */\n#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */\n\n/* SCB Configurable Fault Status Register Definitions */\n#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */\n#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */\n\n#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */\n#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */\n\n#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */\n#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\n\n/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */\n#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */\n\n#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */\n#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */\n\n#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */\n#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */\n\n#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\n#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\n\n#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */\n#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\n\n#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */\n#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\n\n/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */\n#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */\n\n#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */\n#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */\n\n#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */\n#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */\n\n#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */\n#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */\n\n#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */\n#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\n\n#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */\n#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */\n\n#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */\n#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */\n\n/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */\n#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\n\n#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */\n#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */\n\n#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */\n#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */\n\n#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */\n#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */\n\n#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */\n#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */\n\n#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\n#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\n\n/* SCB Hard Fault Status Register Definitions */\n#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */\n#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */\n\n#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */\n#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */\n\n#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */\n#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */\n\n/* SCB Debug Fault Status Register Definitions */\n#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */\n#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */\n\n#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */\n#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */\n\n#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */\n#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */\n\n#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */\n#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */\n\n#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */\n#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */\n\n/*@} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\n  \\brief    Type definitions for the System Control and ID Register not in the SCB\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control and ID Register not in the SCB.\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1U];\n  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */\n  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\n} SCnSCB_Type;\n\n/* Interrupt Controller Type Register Definitions */\n#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */\n#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */\n\n/* Auxiliary Control Register Definitions */\n#define SCnSCB_ACTLR_DISOOFP_Pos            9U                                         /*!< ACTLR: DISOOFP Position */\n#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */\n\n#define SCnSCB_ACTLR_DISFPCA_Pos            8U                                         /*!< ACTLR: DISFPCA Position */\n#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */\n\n#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */\n#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */\n\n#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */\n#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */\n\n#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */\n#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */\n\n/*@} end of group CMSIS_SCnotSCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/*@} end of group CMSIS_SysTick */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)\n  \\brief    Type definitions for the Instrumentation Trace Macrocell (ITM)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).\n */\ntypedef struct\n{\n  __OM  union\n  {\n    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */\n    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */\n    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */\n  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */\n        uint32_t RESERVED0[864U];\n  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */\n        uint32_t RESERVED1[15U];\n  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */\n        uint32_t RESERVED2[15U];\n  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */\n        uint32_t RESERVED3[32U];\n        uint32_t RESERVED4[43U];\n  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */\n        uint32_t RESERVED5[6U];\n  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */\n  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */\n  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */\n  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */\n  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */\n  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */\n  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */\n  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */\n  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */\n  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */\n  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */\n  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */\n} ITM_Type;\n\n/* ITM Trace Privilege Register Definitions */\n#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */\n#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */\n\n/* ITM Trace Control Register Definitions */\n#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */\n#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */\n\n#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */\n#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */\n\n#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */\n#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */\n\n#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */\n#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */\n\n#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */\n#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */\n\n#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */\n#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */\n\n#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */\n#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */\n\n#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */\n#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */\n\n#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */\n#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */\n\n/* ITM Lock Status Register Definitions */\n#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */\n#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */\n\n#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */\n#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */\n\n#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */\n#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */\n\n/*@}*/ /* end of group CMSIS_ITM */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\n  \\brief    Type definitions for the Data Watchpoint and Trace (DWT)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\n  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */\n  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */\n  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */\n  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */\n  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */\n  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */\n  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\n  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\n  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */\n  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\n        uint32_t RESERVED0[1U];\n  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\n  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */\n  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\n        uint32_t RESERVED1[1U];\n  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\n  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */\n  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\n        uint32_t RESERVED2[1U];\n  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\n  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */\n  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\n} DWT_Type;\n\n/* DWT Control Register Definitions */\n#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\n#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\n\n#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\n#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\n\n#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\n#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\n\n#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\n#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\n\n#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\n#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\n\n#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */\n#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */\n\n#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */\n#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */\n\n#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */\n#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */\n\n#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */\n#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */\n\n#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */\n#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */\n\n#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */\n#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */\n\n#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */\n#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */\n\n#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */\n#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */\n\n#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */\n#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */\n\n#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */\n#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */\n\n#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */\n#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */\n\n#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */\n#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */\n\n#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */\n#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */\n\n/* DWT CPI Count Register Definitions */\n#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */\n#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */\n\n/* DWT Exception Overhead Count Register Definitions */\n#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */\n#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */\n\n/* DWT Sleep Count Register Definitions */\n#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */\n#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */\n\n/* DWT LSU Count Register Definitions */\n#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */\n#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */\n\n/* DWT Folded-instruction Count Register Definitions */\n#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */\n#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */\n\n/* DWT Comparator Mask Register Definitions */\n#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */\n#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */\n\n/* DWT Comparator Function Register Definitions */\n#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\n#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\n\n#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */\n#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */\n\n#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */\n#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */\n\n#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\n#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\n\n#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */\n#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */\n\n#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */\n#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */\n\n#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */\n#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */\n\n#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */\n#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */\n\n#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */\n#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */\n\n/*@}*/ /* end of group CMSIS_DWT */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_TPI     Trace Port Interface (TPI)\n  \\brief    Type definitions for the Trace Port Interface (TPI)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Trace Port Interface Register (TPI).\n */\ntypedef struct\n{\n  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */\n  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */\n        uint32_t RESERVED0[2U];\n  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\n        uint32_t RESERVED1[55U];\n  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\n        uint32_t RESERVED2[131U];\n  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\n  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\n  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */\n        uint32_t RESERVED3[759U];\n  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */\n  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */\n  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */\n        uint32_t RESERVED4[1U];\n  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */\n  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */\n  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */\n        uint32_t RESERVED5[39U];\n  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */\n  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */\n        uint32_t RESERVED7[8U];\n  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */\n  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */\n} TPI_Type;\n\n/* TPI Asynchronous Clock Prescaler Register Definitions */\n#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */\n#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */\n\n/* TPI Selected Pin Protocol Register Definitions */\n#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\n#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\n\n/* TPI Formatter and Flush Status Register Definitions */\n#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\n#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\n\n#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\n#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\n\n#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\n#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\n\n#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\n#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\n\n/* TPI Formatter and Flush Control Register Definitions */\n#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\n#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\n\n#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\n#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\n\n/* TPI TRIGGER Register Definitions */\n#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */\n#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */\n\n/* TPI Integration ETM Data Register Definitions (FIFO0) */\n#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */\n#define TPI_FIFO0_ITM_ATVALID_Msk          (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */\n\n#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */\n#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */\n\n#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */\n#define TPI_FIFO0_ETM_ATVALID_Msk          (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */\n\n#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */\n#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */\n\n#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */\n#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */\n\n#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */\n#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */\n\n#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */\n#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */\n\n/* TPI ITATBCTR2 Register Definitions */\n#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */\n#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */\n\n#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */\n#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */\n\n/* TPI Integration ITM Data Register Definitions (FIFO1) */\n#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */\n#define TPI_FIFO1_ITM_ATVALID_Msk          (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */\n\n#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */\n#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */\n\n#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */\n#define TPI_FIFO1_ETM_ATVALID_Msk          (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */\n\n#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */\n#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */\n\n#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */\n#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */\n\n#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */\n#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */\n\n#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */\n#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */\n\n/* TPI ITATBCTR0 Register Definitions */\n#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */\n#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */\n\n#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */\n#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */\n\n/* TPI Integration Mode Control Register Definitions */\n#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */\n#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */\n\n/* TPI DEVID Register Definitions */\n#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\n#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\n\n#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\n#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\n\n#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\n#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\n\n#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */\n#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */\n\n#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */\n#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */\n\n#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */\n#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */\n\n/* TPI DEVTYPE Register Definitions */\n#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */\n#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\n\n#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */\n#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\n\n/*@}*/ /* end of group CMSIS_TPI */\n\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\n */\ntypedef struct\n{\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\n  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */\n  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */\n  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */\n  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */\n  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */\n  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */\n  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */\n} MPU_Type;\n\n#define MPU_TYPE_RALIASES                  4U\n\n/* MPU Type Register Definitions */\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\n\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\n\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\n\n/* MPU Control Register Definitions */\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\n\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\n\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\n\n/* MPU Region Number Register Definitions */\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\n\n/* MPU Region Base Address Register Definitions */\n#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */\n#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */\n\n#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */\n#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */\n\n#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */\n#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */\n\n/* MPU Region Attribute and Size Register Definitions */\n#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */\n#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */\n\n#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */\n#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */\n\n#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */\n#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */\n\n#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */\n#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */\n\n#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */\n#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */\n\n#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */\n#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */\n\n#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */\n#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */\n\n#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */\n#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */\n\n#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */\n#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */\n\n#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */\n#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */\n\n/*@} end of group CMSIS_MPU */\n#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_FPU     Floating Point Unit (FPU)\n  \\brief    Type definitions for the Floating Point Unit (FPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Floating Point Unit (FPU).\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1U];\n  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */\n  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */\n  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */\n  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */\n  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */\n  __IM  uint32_t MVFR2;                  /*!< Offset: 0x018 (R/ )  Media and FP Feature Register 2 */\n} FPU_Type;\n\n/* Floating-Point Context Control Register Definitions */\n#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */\n#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */\n\n#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */\n#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */\n\n#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */\n#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */\n\n#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */\n#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */\n\n#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */\n#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */\n\n#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */\n#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */\n\n#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */\n#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */\n\n#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */\n#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */\n\n#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */\n#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */\n\n/* Floating-Point Context Address Register Definitions */\n#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */\n#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */\n\n/* Floating-Point Default Status Control Register Definitions */\n#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */\n#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */\n\n#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */\n#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */\n\n#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */\n#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */\n\n#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */\n#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */\n\n/* Media and FP Feature Register 0 Definitions */\n#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */\n#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */\n\n#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */\n#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */\n\n#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */\n#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */\n\n#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */\n#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */\n\n#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */\n#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */\n\n#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */\n#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */\n\n#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */\n#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */\n\n#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */\n#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */\n\n/* Media and FP Feature Register 1 Definitions */\n#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */\n#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */\n\n#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */\n#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */\n\n#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */\n#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */\n\n#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */\n#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */\n\n/* Media and FP Feature Register 2 Definitions */\n\n#define FPU_MVFR2_VFP_Misc_Pos              4U                                            /*!< MVFR2: VFP Misc bits Position */\n#define FPU_MVFR2_VFP_Misc_Msk             (0xFUL << FPU_MVFR2_VFP_Misc_Pos)              /*!< MVFR2: VFP Misc bits Mask */\n\n/*@} end of group CMSIS_FPU */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\n  \\brief    Type definitions for the Core Debug Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Core Debug Register (CoreDebug).\n */\ntypedef struct\n{\n  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\n  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\n  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\n  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\n} CoreDebug_Type;\n\n/* Debug Halting Control and Status Register Definitions */\n#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */\n#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\n\n#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */\n#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\n\n#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\n#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\n\n#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */\n#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\n\n#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */\n#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\n\n#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */\n#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\n\n#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */\n#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\n\n#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\n#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\n\n#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */\n#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\n\n#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */\n#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\n\n#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */\n#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\n\n#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */\n#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\n\n/* Debug Core Register Selector Register Definitions */\n#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */\n#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\n\n#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */\n#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */\n\n/* Debug Exception and Monitor Control Register Definitions */\n#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */\n#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */\n\n#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */\n#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */\n\n#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */\n#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */\n\n#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */\n#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */\n\n#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */\n#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */\n\n#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */\n#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\n\n#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */\n#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */\n\n#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */\n#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */\n\n#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */\n#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */\n\n#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */\n#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */\n\n#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */\n#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\n\n#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */\n#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */\n\n#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */\n#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */\n\n/*@} end of group CMSIS_CoreDebug */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n/*@} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Core Hardware */\n#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\n#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */\n#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */\n#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */\n#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */\n#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\n#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\n#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\n\n#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */\n#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\n#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\n#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\n#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */\n#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */\n#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */\n#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */\n  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */\n#endif\n\n#define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */\n#define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */\n\n/*@} */\n\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Debug Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n#ifdef CMSIS_NVIC_VIRTUAL\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\n  #endif\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\n  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\n  #define NVIC_GetActive              __NVIC_GetActive\n  #define NVIC_SetPriority            __NVIC_SetPriority\n  #define NVIC_GetPriority            __NVIC_GetPriority\n  #define NVIC_SystemReset            __NVIC_SystemReset\n#endif /* CMSIS_NVIC_VIRTUAL */\n\n#ifdef CMSIS_VECTAB_VIRTUAL\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\n  #endif\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetVector              __NVIC_SetVector\n  #define NVIC_GetVector              __NVIC_GetVector\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\n\n#define NVIC_USER_IRQ_OFFSET          16\n\n\n/* The following EXC_RETURN values are saved the LR on exception entry */\n#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */\n#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */\n#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */\n#define EXC_RETURN_HANDLER_FPU     (0xFFFFFFE1UL)     /* return to Handler mode, uses MSP after return, restore floating-point state */\n#define EXC_RETURN_THREAD_MSP_FPU  (0xFFFFFFE9UL)     /* return to Thread mode, uses MSP after return, restore floating-point state  */\n#define EXC_RETURN_THREAD_PSP_FPU  (0xFFFFFFEDUL)     /* return to Thread mode, uses PSP after return, restore floating-point state  */\n\n\n/**\n  \\brief   Set Priority Grouping\n  \\details Sets the priority grouping field using the required unlock sequence.\n           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\n           Only values from 0..7 are used.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]      PriorityGroup  Priority grouping field.\n */\n__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\n{\n  uint32_t reg_value;\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\n\n  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */\n  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\n  reg_value  =  (reg_value                                   |\n                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */\n  SCB->AIRCR =  reg_value;\n}\n\n\n/**\n  \\brief   Get Priority Grouping\n  \\details Reads the priority grouping field from the NVIC Interrupt Controller.\n  \\return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\n{\n  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\n}\n\n\n/**\n  \\brief   Enable Interrupt\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    __COMPILER_BARRIER();\n    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __COMPILER_BARRIER();\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __DSB();\n    __ISB();\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt\n  \\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every processor exception.\n */\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n  else\n  {\n    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Encode Priority\n  \\details Encodes the priority for an interrupt with the given priority group,\n           preemptive priority value, and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\n */\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  return (\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\n         );\n}\n\n\n/**\n  \\brief   Decode Priority\n  \\details Decodes an interrupt priority value with a given priority group to\n           preemptive priority value and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\n */\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\n}\n\n\n/**\n  \\brief   Set Interrupt Vector\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n           VTOR must been relocated to SRAM before.\n  \\param [in]   IRQn      Interrupt number\n  \\param [in]   vector    Address of interrupt handler function\n */\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\n{\n  uint32_t vectors = (uint32_t )SCB->VTOR;\n  (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector;\n  /* ARM Application Note 321 states that the M4 does not require the architectural barrier */\n}\n\n\n/**\n  \\brief   Get Interrupt Vector\n  \\details Reads an interrupt vector from interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn      Interrupt number.\n  \\return                 Address of interrupt handler function\n */\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\n{\n  uint32_t vectors = (uint32_t )SCB->VTOR;\n  return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4));\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |\n                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\n                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n/*@} end of CMSIS_Core_NVICFunctions */\n\n\n/* ##########################  MPU functions  #################################### */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n\n#include \"mpu_armv7.h\"\n\n#endif\n\n\n/* ##########################  FPU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\n  \\brief    Function that provides FPU type.\n  @{\n */\n\n/**\n  \\brief   get FPU type\n  \\details returns the FPU type\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n */\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\n{\n  uint32_t mvfr0;\n\n  mvfr0 = FPU->MVFR0;\n  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)\n  {\n    return 1U;           /* Single precision FPU */\n  }\n  else\n  {\n    return 0U;           /* No FPU */\n  }\n}\n\n\n/*@} end of CMSIS_Core_FpuFunctions */\n\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#endif\n\n/*@} end of CMSIS_Core_SysTickFunctions */\n\n\n\n/* ##################################### Debug In/Output function ########################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_core_DebugFunctions ITM Functions\n  \\brief    Functions that access the ITM debug interface.\n  @{\n */\n\nextern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */\n#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \\ref ITM_RxBuffer is ready for next character. */\n\n\n/**\n  \\brief   ITM Send Character\n  \\details Transmits a character via the ITM channel 0, and\n           \\li Just returns when no debugger is connected that has booked the output.\n           \\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\n  \\param [in]     ch  Character to transmit.\n  \\returns            Character to transmit.\n */\n__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\n{\n  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */\n      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */\n  {\n    while (ITM->PORT[0U].u32 == 0UL)\n    {\n      __NOP();\n    }\n    ITM->PORT[0U].u8 = (uint8_t)ch;\n  }\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Receive Character\n  \\details Inputs a character via the external variable \\ref ITM_RxBuffer.\n  \\return             Received character.\n  \\return         -1  No character pending.\n */\n__STATIC_INLINE int32_t ITM_ReceiveChar (void)\n{\n  int32_t ch = -1;                           /* no character available */\n\n  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\n  {\n    ch = ITM_RxBuffer;\n    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */\n  }\n\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Check Character\n  \\details Checks whether a character is pending for reading in the variable \\ref ITM_RxBuffer.\n  \\return          0  No character available.\n  \\return          1  Character available.\n */\n__STATIC_INLINE int32_t ITM_CheckChar (void)\n{\n\n  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\n  {\n    return (0);                              /* no character available */\n  }\n  else\n  {\n    return (1);                              /*    character available */\n  }\n}\n\n/*@} end of CMSIS_core_DebugFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM4_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n"
  },
  {
    "path": "3rd_party/CMSIS/Include/core_cm7.h",
    "content": "/**************************************************************************//**\n * @file     core_cm7.h\n * @brief    CMSIS Cortex-M7 Core Peripheral Access Layer Header File\n * @version  V5.1.1\n * @date     28. March 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CORE_CM7_H_GENERIC\n#define __CORE_CM7_H_GENERIC\n\n#include <stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup Cortex_M7\n  @{\n */\n\n#include \"cmsis_version.h\"\n\n/* CMSIS CM7 definitions */\n#define __CM7_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                  /*!< \\deprecated [31:16] CMSIS HAL main version */\n#define __CM7_CMSIS_VERSION_SUB   ( __CM_CMSIS_VERSION_SUB)                  /*!< \\deprecated [15:0]  CMSIS HAL sub version */\n#define __CM7_CMSIS_VERSION       ((__CM7_CMSIS_VERSION_MAIN << 16U) | \\\n                                    __CM7_CMSIS_VERSION_SUB           )      /*!< \\deprecated CMSIS HAL version number */\n\n#define __CORTEX_M                (7U)                                       /*!< Cortex-M Core */\n\n/** __FPU_USED indicates whether an FPU is used or not.\n    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\n*/\n#if defined ( __CC_ARM )\n  #if defined __TARGET_FPU_VFP\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined __ARM_FP\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #warning \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined __ARMVFP__\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __TI_ARM__ )\n  #if defined __TI_VFP_SUPPORT__\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined __FPU_VFP__\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM7_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_CM7_H_DEPENDANT\n#define __CORE_CM7_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __CM7_REV\n    #define __CM7_REV               0x0000U\n    #warning \"__CM7_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __FPU_PRESENT\n    #define __FPU_PRESENT             0U\n    #warning \"__FPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __MPU_PRESENT\n    #define __MPU_PRESENT             0U\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __ICACHE_PRESENT\n    #define __ICACHE_PRESENT          0U\n    #warning \"__ICACHE_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __DCACHE_PRESENT\n    #define __DCACHE_PRESENT          0U\n    #warning \"__DCACHE_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __DTCM_PRESENT\n    #define __DTCM_PRESENT            0U\n    #warning \"__DTCM_PRESENT        not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          3U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/*@} end of group Cortex_M7 */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core SCB Register\n  - Core SysTick Register\n  - Core Debug Register\n  - Core MPU Register\n  - Core FPU Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for Cortex-M processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */\n    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\n    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */\n#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */\n\n#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */\n#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */\n    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */\n    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\n    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit */\n    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */\n#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */\n\n#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */\n#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */\n#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */\n\n#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */\n#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\n    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */\n    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */\n#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */\n\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\n#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\n\n/*@} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[24U];\n  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RESERVED1[24U];\n  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[24U];\n  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[24U];\n  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\n        uint32_t RESERVED4[56U];\n  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */\n        uint32_t RESERVED5[644U];\n  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */\n}  NVIC_Type;\n\n/* Software Triggered Interrupt Register Definitions */\n#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */\n#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */\n\n/*@} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */\n  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */\n  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */\n  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */\n  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */\n  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */\n  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */\n  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */\n  __IM  uint32_t ID_AFR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */\n  __IM  uint32_t ID_MFR[4U];             /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */\n  __IM  uint32_t ID_ISAR[5U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */\n        uint32_t RESERVED0[1U];\n  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */\n  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */\n  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */\n  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */\n  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */\n        uint32_t RESERVED3[93U];\n  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */\n        uint32_t RESERVED4[15U];\n  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */\n  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */\n  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */\n        uint32_t RESERVED5[1U];\n  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */\n        uint32_t RESERVED6[1U];\n  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */\n  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */\n  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */\n  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */\n  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */\n  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */\n  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */\n  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */\n        uint32_t RESERVED7[6U];\n  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */\n  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */\n  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */\n  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */\n  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */\n        uint32_t RESERVED8[1U];\n  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */\n} SCB_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\n#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\n#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n/* SCB Vector Table Offset Register Definitions */\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\n#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */\n#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */\n#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_BP_Pos                      18U                                           /*!< SCB CCR: Branch prediction enable bit Position */\n#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: Branch prediction enable bit Mask */\n\n#define SCB_CCR_IC_Pos                      17U                                           /*!< SCB CCR: Instruction cache enable bit Position */\n#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: Instruction cache enable bit Mask */\n\n#define SCB_CCR_DC_Pos                      16U                                           /*!< SCB CCR: Cache enable bit Position */\n#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: Cache enable bit Mask */\n\n#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\n#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\n\n#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\n#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\n\n#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\n#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\n#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\n\n#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */\n#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */\n#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */\n\n#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */\n#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */\n\n#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */\n#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */\n\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */\n#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */\n\n#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */\n#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */\n\n#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */\n#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */\n\n#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\n#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\n\n#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\n#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\n\n#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */\n#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */\n\n#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\n#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\n\n#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */\n#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */\n\n#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */\n#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */\n\n#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */\n#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */\n\n/* SCB Configurable Fault Status Register Definitions */\n#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */\n#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */\n\n#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */\n#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */\n\n#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */\n#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\n\n/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */\n#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */\n\n#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */\n#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */\n\n#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */\n#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */\n\n#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\n#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\n\n#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */\n#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\n\n#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */\n#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\n\n/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */\n#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */\n\n#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */\n#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */\n\n#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */\n#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */\n\n#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */\n#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */\n\n#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */\n#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\n\n#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */\n#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */\n\n#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */\n#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */\n\n/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */\n#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\n\n#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */\n#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */\n\n#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */\n#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */\n\n#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */\n#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */\n\n#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */\n#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */\n\n#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\n#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\n\n/* SCB Hard Fault Status Register Definitions */\n#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */\n#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */\n\n#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */\n#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */\n\n#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */\n#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */\n\n/* SCB Debug Fault Status Register Definitions */\n#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */\n#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */\n\n#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */\n#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */\n\n#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */\n#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */\n\n#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */\n#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */\n\n#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */\n#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */\n\n/* SCB Cache Level ID Register Definitions */\n#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */\n#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */\n\n#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */\n#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */\n\n/* SCB Cache Type Register Definitions */\n#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */\n#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */\n\n#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */\n#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */\n\n#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */\n#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */\n\n#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */\n#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */\n\n#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */\n#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */\n\n/* SCB Cache Size ID Register Definitions */\n#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */\n#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */\n\n#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */\n#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */\n\n#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */\n#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */\n\n#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */\n#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */\n\n#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */\n#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */\n\n#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */\n#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */\n\n#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */\n#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */\n\n/* SCB Cache Size Selection Register Definitions */\n#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */\n#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */\n\n#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */\n#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */\n\n/* SCB Software Triggered Interrupt Register Definitions */\n#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */\n#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */\n\n/* SCB D-Cache Invalidate by Set-way Register Definitions */\n#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */\n#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */\n\n#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */\n#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */\n\n/* SCB D-Cache Clean by Set-way Register Definitions */\n#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */\n#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */\n\n#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */\n#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */\n\n/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */\n#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */\n#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */\n\n#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */\n#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */\n\n/* Instruction Tightly-Coupled Memory Control Register Definitions */\n#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */\n#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */\n\n#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */\n#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */\n\n#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */\n#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */\n\n#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */\n#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */\n\n/* Data Tightly-Coupled Memory Control Register Definitions */\n#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */\n#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */\n\n#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */\n#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */\n\n#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */\n#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */\n\n#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */\n#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */\n\n/* AHBP Control Register Definitions */\n#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */\n#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */\n\n#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */\n#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */\n\n/* L1 Cache Control Register Definitions */\n#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */\n#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */\n\n#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */\n#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */\n\n#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */\n#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */\n\n/* AHBS Control Register Definitions */\n#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */\n#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */\n\n#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */\n#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */\n\n#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/\n#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */\n\n/* Auxiliary Bus Fault Status Register Definitions */\n#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/\n#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */\n\n#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/\n#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */\n\n#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/\n#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */\n\n#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/\n#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */\n\n#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/\n#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */\n\n#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/\n#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */\n\n/*@} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\n  \\brief    Type definitions for the System Control and ID Register not in the SCB\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control and ID Register not in the SCB.\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1U];\n  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */\n  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\n} SCnSCB_Type;\n\n/* Interrupt Controller Type Register Definitions */\n#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */\n#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */\n\n/* Auxiliary Control Register Definitions */\n#define SCnSCB_ACTLR_DISDYNADD_Pos         26U                                         /*!< ACTLR: DISDYNADD Position */\n#define SCnSCB_ACTLR_DISDYNADD_Msk         (1UL << SCnSCB_ACTLR_DISDYNADD_Pos)         /*!< ACTLR: DISDYNADD Mask */\n\n#define SCnSCB_ACTLR_DISISSCH1_Pos         21U                                         /*!< ACTLR: DISISSCH1 Position */\n#define SCnSCB_ACTLR_DISISSCH1_Msk         (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos)      /*!< ACTLR: DISISSCH1 Mask */\n\n#define SCnSCB_ACTLR_DISDI_Pos             16U                                         /*!< ACTLR: DISDI Position */\n#define SCnSCB_ACTLR_DISDI_Msk             (0x1FUL << SCnSCB_ACTLR_DISDI_Pos)          /*!< ACTLR: DISDI Mask */\n\n#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos     15U                                         /*!< ACTLR: DISCRITAXIRUR Position */\n#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk     (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos)     /*!< ACTLR: DISCRITAXIRUR Mask */\n\n#define SCnSCB_ACTLR_DISBTACALLOC_Pos      14U                                         /*!< ACTLR: DISBTACALLOC Position */\n#define SCnSCB_ACTLR_DISBTACALLOC_Msk      (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos)      /*!< ACTLR: DISBTACALLOC Mask */\n\n#define SCnSCB_ACTLR_DISBTACREAD_Pos       13U                                         /*!< ACTLR: DISBTACREAD Position */\n#define SCnSCB_ACTLR_DISBTACREAD_Msk       (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos)       /*!< ACTLR: DISBTACREAD Mask */\n\n#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos    12U                                         /*!< ACTLR: DISITMATBFLUSH Position */\n#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk    (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos)    /*!< ACTLR: DISITMATBFLUSH Mask */\n\n#define SCnSCB_ACTLR_DISRAMODE_Pos         11U                                         /*!< ACTLR: DISRAMODE Position */\n#define SCnSCB_ACTLR_DISRAMODE_Msk         (1UL << SCnSCB_ACTLR_DISRAMODE_Pos)         /*!< ACTLR: DISRAMODE Mask */\n\n#define SCnSCB_ACTLR_FPEXCODIS_Pos         10U                                         /*!< ACTLR: FPEXCODIS Position */\n#define SCnSCB_ACTLR_FPEXCODIS_Msk         (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos)         /*!< ACTLR: FPEXCODIS Mask */\n\n#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */\n#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */\n\n#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */\n#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */\n\n/*@} end of group CMSIS_SCnotSCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/*@} end of group CMSIS_SysTick */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)\n  \\brief    Type definitions for the Instrumentation Trace Macrocell (ITM)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).\n */\ntypedef struct\n{\n  __OM  union\n  {\n    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */\n    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */\n    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */\n  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */\n        uint32_t RESERVED0[864U];\n  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */\n        uint32_t RESERVED1[15U];\n  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */\n        uint32_t RESERVED2[15U];\n  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */\n        uint32_t RESERVED3[32U];\n        uint32_t RESERVED4[43U];\n  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */\n        uint32_t RESERVED5[6U];\n  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */\n  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */\n  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */\n  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */\n  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */\n  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */\n  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */\n  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */\n  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */\n  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */\n  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */\n  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */\n} ITM_Type;\n\n/* ITM Trace Privilege Register Definitions */\n#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */\n#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */\n\n/* ITM Trace Control Register Definitions */\n#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */\n#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */\n\n#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */\n#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */\n\n#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */\n#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */\n\n#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */\n#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */\n\n#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */\n#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */\n\n#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */\n#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */\n\n#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */\n#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */\n\n#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */\n#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */\n\n#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */\n#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */\n\n/* ITM Lock Status Register Definitions */\n#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */\n#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */\n\n#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */\n#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */\n\n#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */\n#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */\n\n/*@}*/ /* end of group CMSIS_ITM */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\n  \\brief    Type definitions for the Data Watchpoint and Trace (DWT)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\n  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */\n  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */\n  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */\n  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */\n  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */\n  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */\n  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\n  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\n  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */\n  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\n        uint32_t RESERVED0[1U];\n  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\n  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */\n  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\n        uint32_t RESERVED1[1U];\n  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\n  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */\n  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\n        uint32_t RESERVED2[1U];\n  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\n  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */\n  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\n        uint32_t RESERVED3[981U];\n  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 (  W)  Lock Access Register */\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */\n} DWT_Type;\n\n/* DWT Control Register Definitions */\n#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\n#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\n\n#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\n#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\n\n#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\n#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\n\n#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\n#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\n\n#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\n#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\n\n#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */\n#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */\n\n#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */\n#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */\n\n#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */\n#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */\n\n#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */\n#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */\n\n#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */\n#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */\n\n#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */\n#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */\n\n#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */\n#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */\n\n#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */\n#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */\n\n#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */\n#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */\n\n#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */\n#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */\n\n#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */\n#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */\n\n#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */\n#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */\n\n#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */\n#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */\n\n/* DWT CPI Count Register Definitions */\n#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */\n#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */\n\n/* DWT Exception Overhead Count Register Definitions */\n#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */\n#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */\n\n/* DWT Sleep Count Register Definitions */\n#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */\n#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */\n\n/* DWT LSU Count Register Definitions */\n#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */\n#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */\n\n/* DWT Folded-instruction Count Register Definitions */\n#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */\n#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */\n\n/* DWT Comparator Mask Register Definitions */\n#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */\n#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */\n\n/* DWT Comparator Function Register Definitions */\n#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\n#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\n\n#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */\n#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */\n\n#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */\n#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */\n\n#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\n#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\n\n#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */\n#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */\n\n#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */\n#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */\n\n#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */\n#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */\n\n#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */\n#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */\n\n#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */\n#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */\n\n/*@}*/ /* end of group CMSIS_DWT */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_TPI     Trace Port Interface (TPI)\n  \\brief    Type definitions for the Trace Port Interface (TPI)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Trace Port Interface Register (TPI).\n */\ntypedef struct\n{\n  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */\n  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */\n        uint32_t RESERVED0[2U];\n  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\n        uint32_t RESERVED1[55U];\n  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\n        uint32_t RESERVED2[131U];\n  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\n  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\n  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */\n        uint32_t RESERVED3[759U];\n  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */\n  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */\n  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */\n        uint32_t RESERVED4[1U];\n  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */\n  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */\n  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */\n        uint32_t RESERVED5[39U];\n  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */\n  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */\n        uint32_t RESERVED7[8U];\n  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */\n  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */\n} TPI_Type;\n\n/* TPI Asynchronous Clock Prescaler Register Definitions */\n#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */\n#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */\n\n/* TPI Selected Pin Protocol Register Definitions */\n#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\n#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\n\n/* TPI Formatter and Flush Status Register Definitions */\n#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\n#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\n\n#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\n#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\n\n#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\n#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\n\n#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\n#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\n\n/* TPI Formatter and Flush Control Register Definitions */\n#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\n#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\n\n#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\n#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\n\n/* TPI TRIGGER Register Definitions */\n#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */\n#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */\n\n/* TPI Integration ETM Data Register Definitions (FIFO0) */\n#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */\n#define TPI_FIFO0_ITM_ATVALID_Msk          (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */\n\n#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */\n#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */\n\n#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */\n#define TPI_FIFO0_ETM_ATVALID_Msk          (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */\n\n#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */\n#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */\n\n#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */\n#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */\n\n#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */\n#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */\n\n#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */\n#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */\n\n/* TPI ITATBCTR2 Register Definitions */\n#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */\n#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */\n\n#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */\n#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */\n\n/* TPI Integration ITM Data Register Definitions (FIFO1) */\n#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */\n#define TPI_FIFO1_ITM_ATVALID_Msk          (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */\n\n#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */\n#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */\n\n#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */\n#define TPI_FIFO1_ETM_ATVALID_Msk          (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */\n\n#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */\n#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */\n\n#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */\n#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */\n\n#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */\n#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */\n\n#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */\n#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */\n\n/* TPI ITATBCTR0 Register Definitions */\n#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */\n#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */\n\n#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */\n#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */\n\n/* TPI Integration Mode Control Register Definitions */\n#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */\n#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */\n\n/* TPI DEVID Register Definitions */\n#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\n#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\n\n#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\n#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\n\n#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\n#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\n\n#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */\n#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */\n\n#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */\n#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */\n\n#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */\n#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */\n\n/* TPI DEVTYPE Register Definitions */\n#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */\n#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\n\n#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */\n#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\n\n/*@}*/ /* end of group CMSIS_TPI */\n\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\n */\ntypedef struct\n{\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\n  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */\n  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */\n  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */\n  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */\n  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */\n  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */\n  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */\n} MPU_Type;\n\n#define MPU_TYPE_RALIASES                  4U\n\n/* MPU Type Register Definitions */\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\n\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\n\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\n\n/* MPU Control Register Definitions */\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\n\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\n\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\n\n/* MPU Region Number Register Definitions */\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\n\n/* MPU Region Base Address Register Definitions */\n#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */\n#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */\n\n#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */\n#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */\n\n#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */\n#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */\n\n/* MPU Region Attribute and Size Register Definitions */\n#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */\n#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */\n\n#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */\n#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */\n\n#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */\n#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */\n\n#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */\n#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */\n\n#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */\n#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */\n\n#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */\n#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */\n\n#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */\n#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */\n\n#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */\n#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */\n\n#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */\n#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */\n\n#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */\n#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */\n\n/*@} end of group CMSIS_MPU */\n#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_FPU     Floating Point Unit (FPU)\n  \\brief    Type definitions for the Floating Point Unit (FPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Floating Point Unit (FPU).\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1U];\n  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */\n  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */\n  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */\n  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */\n  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */\n  __IM  uint32_t MVFR2;                  /*!< Offset: 0x018 (R/ )  Media and FP Feature Register 2 */\n} FPU_Type;\n\n/* Floating-Point Context Control Register Definitions */\n#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */\n#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */\n\n#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */\n#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */\n\n#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */\n#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */\n\n#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */\n#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */\n\n#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */\n#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */\n\n#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */\n#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */\n\n#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */\n#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */\n\n#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */\n#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */\n\n#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */\n#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */\n\n/* Floating-Point Context Address Register Definitions */\n#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */\n#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */\n\n/* Floating-Point Default Status Control Register Definitions */\n#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */\n#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */\n\n#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */\n#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */\n\n#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */\n#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */\n\n#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */\n#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */\n\n/* Media and FP Feature Register 0 Definitions */\n#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */\n#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */\n\n#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */\n#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */\n\n#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */\n#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */\n\n#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */\n#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */\n\n#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */\n#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */\n\n#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */\n#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */\n\n#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */\n#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */\n\n#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */\n#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */\n\n/* Media and FP Feature Register 1 Definitions */\n#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */\n#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */\n\n#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */\n#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */\n\n#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */\n#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */\n\n#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */\n#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */\n\n/* Media and FP Feature Register 2 Definitions */\n\n#define FPU_MVFR2_VFP_Misc_Pos              4U                                            /*!< MVFR2: VFP Misc bits Position */\n#define FPU_MVFR2_VFP_Misc_Msk             (0xFUL << FPU_MVFR2_VFP_Misc_Pos)              /*!< MVFR2: VFP Misc bits Mask */\n\n/*@} end of group CMSIS_FPU */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\n  \\brief    Type definitions for the Core Debug Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Core Debug Register (CoreDebug).\n */\ntypedef struct\n{\n  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\n  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\n  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\n  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\n} CoreDebug_Type;\n\n/* Debug Halting Control and Status Register Definitions */\n#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */\n#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\n\n#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */\n#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\n\n#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\n#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\n\n#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */\n#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\n\n#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */\n#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\n\n#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */\n#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\n\n#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */\n#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\n\n#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\n#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\n\n#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */\n#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\n\n#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */\n#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\n\n#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */\n#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\n\n#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */\n#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\n\n/* Debug Core Register Selector Register Definitions */\n#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */\n#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\n\n#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */\n#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */\n\n/* Debug Exception and Monitor Control Register Definitions */\n#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */\n#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */\n\n#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */\n#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */\n\n#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */\n#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */\n\n#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */\n#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */\n\n#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */\n#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */\n\n#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */\n#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\n\n#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */\n#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */\n\n#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */\n#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */\n\n#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */\n#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */\n\n#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */\n#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */\n\n#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */\n#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\n\n#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */\n#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */\n\n#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */\n#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */\n\n/*@} end of group CMSIS_CoreDebug */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n/*@} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Core Hardware */\n#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\n#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */\n#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */\n#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */\n#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */\n#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\n#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\n#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\n\n#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */\n#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\n#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\n#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\n#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */\n#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */\n#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */\n#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */\n  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */\n#endif\n\n#define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */\n#define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */\n\n/*@} */\n\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Debug Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n#ifdef CMSIS_NVIC_VIRTUAL\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\n  #endif\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\n  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\n  #define NVIC_GetActive              __NVIC_GetActive\n  #define NVIC_SetPriority            __NVIC_SetPriority\n  #define NVIC_GetPriority            __NVIC_GetPriority\n  #define NVIC_SystemReset            __NVIC_SystemReset\n#endif /* CMSIS_NVIC_VIRTUAL */\n\n#ifdef CMSIS_VECTAB_VIRTUAL\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\n  #endif\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetVector              __NVIC_SetVector\n  #define NVIC_GetVector              __NVIC_GetVector\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\n\n#define NVIC_USER_IRQ_OFFSET          16\n\n\n/* The following EXC_RETURN values are saved the LR on exception entry */\n#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */\n#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */\n#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */\n#define EXC_RETURN_HANDLER_FPU     (0xFFFFFFE1UL)     /* return to Handler mode, uses MSP after return, restore floating-point state */\n#define EXC_RETURN_THREAD_MSP_FPU  (0xFFFFFFE9UL)     /* return to Thread mode, uses MSP after return, restore floating-point state  */\n#define EXC_RETURN_THREAD_PSP_FPU  (0xFFFFFFEDUL)     /* return to Thread mode, uses PSP after return, restore floating-point state  */\n\n\n/**\n  \\brief   Set Priority Grouping\n  \\details Sets the priority grouping field using the required unlock sequence.\n           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\n           Only values from 0..7 are used.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]      PriorityGroup  Priority grouping field.\n */\n__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\n{\n  uint32_t reg_value;\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\n\n  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */\n  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\n  reg_value  =  (reg_value                                   |\n                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */\n  SCB->AIRCR =  reg_value;\n}\n\n\n/**\n  \\brief   Get Priority Grouping\n  \\details Reads the priority grouping field from the NVIC Interrupt Controller.\n  \\return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\n{\n  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\n}\n\n\n/**\n  \\brief   Enable Interrupt\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    __COMPILER_BARRIER();\n    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __COMPILER_BARRIER();\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __DSB();\n    __ISB();\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt\n  \\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every processor exception.\n */\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->IP[((uint32_t)IRQn)]                = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n  else\n  {\n    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]                >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Encode Priority\n  \\details Encodes the priority for an interrupt with the given priority group,\n           preemptive priority value, and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\n */\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  return (\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\n         );\n}\n\n\n/**\n  \\brief   Decode Priority\n  \\details Decodes an interrupt priority value with a given priority group to\n           preemptive priority value and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\n */\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\n}\n\n\n/**\n  \\brief   Set Interrupt Vector\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n           VTOR must been relocated to SRAM before.\n  \\param [in]   IRQn      Interrupt number\n  \\param [in]   vector    Address of interrupt handler function\n */\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\n{\n  uint32_t vectors = (uint32_t )SCB->VTOR;\n  (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector;\n  __DSB();\n}\n\n\n/**\n  \\brief   Get Interrupt Vector\n  \\details Reads an interrupt vector from interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn      Interrupt number.\n  \\return                 Address of interrupt handler function\n */\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\n{\n  uint32_t vectors = (uint32_t )SCB->VTOR;\n  return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4));\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |\n                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\n                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n/*@} end of CMSIS_Core_NVICFunctions */\n\n\n/* ##########################  MPU functions  #################################### */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n\n#include \"mpu_armv7.h\"\n\n#endif\n\n\n/* ##########################  FPU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\n  \\brief    Function that provides FPU type.\n  @{\n */\n\n/**\n  \\brief   get FPU type\n  \\details returns the FPU type\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n */\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\n{\n  uint32_t mvfr0;\n\n  mvfr0 = SCB->MVFR0;\n  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)\n  {\n    return 2U;           /* Double + Single precision FPU */\n  }\n  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)\n  {\n    return 1U;           /* Single precision FPU */\n  }\n  else\n  {\n    return 0U;           /* No FPU */\n  }\n}\n\n/*@} end of CMSIS_Core_FpuFunctions */\n\n\n\n/* ##########################  Cache functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_CacheFunctions Cache Functions\n  \\brief    Functions that configure Instruction and Data cache.\n  @{\n */\n\n/* Cache Size ID Register Macros */\n#define CCSIDR_WAYS(x)         (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)\n#define CCSIDR_SETS(x)         (((x) & SCB_CCSIDR_NUMSETS_Msk      ) >> SCB_CCSIDR_NUMSETS_Pos      )\n\n#define __SCB_DCACHE_LINE_SIZE  32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */\n#define __SCB_ICACHE_LINE_SIZE  32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */\n\n/**\n  \\brief   Enable I-Cache\n  \\details Turns on I-Cache\n  */\n__STATIC_FORCEINLINE void SCB_EnableICache (void)\n{\n  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)\n    if (SCB->CCR & SCB_CCR_IC_Msk) return;  /* return if ICache is already enabled */\n\n    __DSB();\n    __ISB();\n    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */\n    __DSB();\n    __ISB();\n    SCB->CCR |=  (uint32_t)SCB_CCR_IC_Msk;  /* enable I-Cache */\n    __DSB();\n    __ISB();\n  #endif\n}\n\n\n/**\n  \\brief   Disable I-Cache\n  \\details Turns off I-Cache\n  */\n__STATIC_FORCEINLINE void SCB_DisableICache (void)\n{\n  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)\n    __DSB();\n    __ISB();\n    SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk;  /* disable I-Cache */\n    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */\n    __DSB();\n    __ISB();\n  #endif\n}\n\n\n/**\n  \\brief   Invalidate I-Cache\n  \\details Invalidates I-Cache\n  */\n__STATIC_FORCEINLINE void SCB_InvalidateICache (void)\n{\n  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)\n    __DSB();\n    __ISB();\n    SCB->ICIALLU = 0UL;\n    __DSB();\n    __ISB();\n  #endif\n}\n\n\n/**\n  \\brief   I-Cache Invalidate by address\n  \\details Invalidates I-Cache for the given address.\n           I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.\n           I-Cache memory blocks which are part of given address + given size are invalidated.\n  \\param[in]   addr    address\n  \\param[in]   isize   size of memory block (in number of bytes)\n*/\n__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize)\n{\n  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)\n    if ( isize > 0 ) {\n       int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U));\n      uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */;\n\n      __DSB();\n\n      do {\n        SCB->ICIMVAU = op_addr;             /* register accepts only 32byte aligned values, only bits 31..5 are valid */\n        op_addr += __SCB_ICACHE_LINE_SIZE;\n        op_size -= __SCB_ICACHE_LINE_SIZE;\n      } while ( op_size > 0 );\n\n      __DSB();\n      __ISB();\n    }\n  #endif\n}\n\n\n/**\n  \\brief   Enable D-Cache\n  \\details Turns on D-Cache\n  */\n__STATIC_FORCEINLINE void SCB_EnableDCache (void)\n{\n  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\n    uint32_t ccsidr;\n    uint32_t sets;\n    uint32_t ways;\n\n    if (SCB->CCR & SCB_CCR_DC_Msk) return;  /* return if DCache is already enabled */\n\n    SCB->CSSELR = 0U;                       /* select Level 1 data cache */\n    __DSB();\n\n    ccsidr = SCB->CCSIDR;\n\n                                            /* invalidate D-Cache */\n    sets = (uint32_t)(CCSIDR_SETS(ccsidr));\n    do {\n      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\n      do {\n        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |\n                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );\n        #if defined ( __CC_ARM )\n          __schedule_barrier();\n        #endif\n      } while (ways-- != 0U);\n    } while(sets-- != 0U);\n    __DSB();\n\n    SCB->CCR |=  (uint32_t)SCB_CCR_DC_Msk;  /* enable D-Cache */\n\n    __DSB();\n    __ISB();\n  #endif\n}\n\n\n/**\n  \\brief   Disable D-Cache\n  \\details Turns off D-Cache\n  */\n__STATIC_FORCEINLINE void SCB_DisableDCache (void)\n{\n  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\n    uint32_t ccsidr;\n    uint32_t sets;\n    uint32_t ways;\n\n    SCB->CSSELR = 0U;                       /* select Level 1 data cache */\n    __DSB();\n\n    SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk;  /* disable D-Cache */\n    __DSB();\n\n    ccsidr = SCB->CCSIDR;\n\n                                            /* clean & invalidate D-Cache */\n    sets = (uint32_t)(CCSIDR_SETS(ccsidr));\n    do {\n      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\n      do {\n        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |\n                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );\n        #if defined ( __CC_ARM )\n          __schedule_barrier();\n        #endif\n      } while (ways-- != 0U);\n    } while(sets-- != 0U);\n\n    __DSB();\n    __ISB();\n  #endif\n}\n\n\n/**\n  \\brief   Invalidate D-Cache\n  \\details Invalidates D-Cache\n  */\n__STATIC_FORCEINLINE void SCB_InvalidateDCache (void)\n{\n  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\n    uint32_t ccsidr;\n    uint32_t sets;\n    uint32_t ways;\n\n    SCB->CSSELR = 0U;                       /* select Level 1 data cache */\n    __DSB();\n\n    ccsidr = SCB->CCSIDR;\n\n                                            /* invalidate D-Cache */\n    sets = (uint32_t)(CCSIDR_SETS(ccsidr));\n    do {\n      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\n      do {\n        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |\n                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );\n        #if defined ( __CC_ARM )\n          __schedule_barrier();\n        #endif\n      } while (ways-- != 0U);\n    } while(sets-- != 0U);\n\n    __DSB();\n    __ISB();\n  #endif\n}\n\n\n/**\n  \\brief   Clean D-Cache\n  \\details Cleans D-Cache\n  */\n__STATIC_FORCEINLINE void SCB_CleanDCache (void)\n{\n  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\n    uint32_t ccsidr;\n    uint32_t sets;\n    uint32_t ways;\n\n    SCB->CSSELR = 0U;                       /* select Level 1 data cache */\n    __DSB();\n\n    ccsidr = SCB->CCSIDR;\n\n                                            /* clean D-Cache */\n    sets = (uint32_t)(CCSIDR_SETS(ccsidr));\n    do {\n      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\n      do {\n        SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |\n                      ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk)  );\n        #if defined ( __CC_ARM )\n          __schedule_barrier();\n        #endif\n      } while (ways-- != 0U);\n    } while(sets-- != 0U);\n\n    __DSB();\n    __ISB();\n  #endif\n}\n\n\n/**\n  \\brief   Clean & Invalidate D-Cache\n  \\details Cleans and Invalidates D-Cache\n  */\n__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void)\n{\n  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\n    uint32_t ccsidr;\n    uint32_t sets;\n    uint32_t ways;\n\n    SCB->CSSELR = 0U;                       /* select Level 1 data cache */\n    __DSB();\n\n    ccsidr = SCB->CCSIDR;\n\n                                            /* clean & invalidate D-Cache */\n    sets = (uint32_t)(CCSIDR_SETS(ccsidr));\n    do {\n      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\n      do {\n        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |\n                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );\n        #if defined ( __CC_ARM )\n          __schedule_barrier();\n        #endif\n      } while (ways-- != 0U);\n    } while(sets-- != 0U);\n\n    __DSB();\n    __ISB();\n  #endif\n}\n\n\n/**\n  \\brief   D-Cache Invalidate by address\n  \\details Invalidates D-Cache for the given address.\n           D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.\n           D-Cache memory blocks which are part of given address + given size are invalidated.\n  \\param[in]   addr    address\n  \\param[in]   dsize   size of memory block (in number of bytes)\n*/\n__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize)\n{\n  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\n    if ( dsize > 0 ) {\n       int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));\n      uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;\n\n      __DSB();\n\n      do {\n        SCB->DCIMVAC = op_addr;             /* register accepts only 32byte aligned values, only bits 31..5 are valid */\n        op_addr += __SCB_DCACHE_LINE_SIZE;\n        op_size -= __SCB_DCACHE_LINE_SIZE;\n      } while ( op_size > 0 );\n\n      __DSB();\n      __ISB();\n    }\n  #endif\n}\n\n\n/**\n  \\brief   D-Cache Clean by address\n  \\details Cleans D-Cache for the given address\n           D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity.\n           D-Cache memory blocks which are part of given address + given size are cleaned.\n  \\param[in]   addr    address\n  \\param[in]   dsize   size of memory block (in number of bytes)\n*/\n__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)\n{\n  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\n    if ( dsize > 0 ) {\n       int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));\n      uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;\n\n      __DSB();\n\n      do {\n        SCB->DCCMVAC = op_addr;             /* register accepts only 32byte aligned values, only bits 31..5 are valid */\n        op_addr += __SCB_DCACHE_LINE_SIZE;\n        op_size -= __SCB_DCACHE_LINE_SIZE;\n      } while ( op_size > 0 );\n\n      __DSB();\n      __ISB();\n    }\n  #endif\n}\n\n\n/**\n  \\brief   D-Cache Clean and Invalidate by address\n  \\details Cleans and invalidates D_Cache for the given address\n           D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity.\n           D-Cache memory blocks which are part of given address + given size are cleaned and invalidated.\n  \\param[in]   addr    address (aligned to 32-byte boundary)\n  \\param[in]   dsize   size of memory block (in number of bytes)\n*/\n__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)\n{\n  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\n    if ( dsize > 0 ) {\n       int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));\n      uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;\n\n      __DSB();\n\n      do {\n        SCB->DCCIMVAC = op_addr;            /* register accepts only 32byte aligned values, only bits 31..5 are valid */\n        op_addr +=          __SCB_DCACHE_LINE_SIZE;\n        op_size -=          __SCB_DCACHE_LINE_SIZE;\n      } while ( op_size > 0 );\n\n      __DSB();\n      __ISB();\n    }\n  #endif\n}\n\n/*@} end of CMSIS_Core_CacheFunctions */\n\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#endif\n\n/*@} end of CMSIS_Core_SysTickFunctions */\n\n\n\n/* ##################################### Debug In/Output function ########################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_core_DebugFunctions ITM Functions\n  \\brief    Functions that access the ITM debug interface.\n  @{\n */\n\nextern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */\n#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \\ref ITM_RxBuffer is ready for next character. */\n\n\n/**\n  \\brief   ITM Send Character\n  \\details Transmits a character via the ITM channel 0, and\n           \\li Just returns when no debugger is connected that has booked the output.\n           \\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\n  \\param [in]     ch  Character to transmit.\n  \\returns            Character to transmit.\n */\n__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\n{\n  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */\n      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */\n  {\n    while (ITM->PORT[0U].u32 == 0UL)\n    {\n      __NOP();\n    }\n    ITM->PORT[0U].u8 = (uint8_t)ch;\n  }\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Receive Character\n  \\details Inputs a character via the external variable \\ref ITM_RxBuffer.\n  \\return             Received character.\n  \\return         -1  No character pending.\n */\n__STATIC_INLINE int32_t ITM_ReceiveChar (void)\n{\n  int32_t ch = -1;                           /* no character available */\n\n  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\n  {\n    ch = ITM_RxBuffer;\n    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */\n  }\n\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Check Character\n  \\details Checks whether a character is pending for reading in the variable \\ref ITM_RxBuffer.\n  \\return          0  No character available.\n  \\return          1  Character available.\n */\n__STATIC_INLINE int32_t ITM_CheckChar (void)\n{\n\n  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\n  {\n    return (0);                              /* no character available */\n  }\n  else\n  {\n    return (1);                              /*    character available */\n  }\n}\n\n/*@} end of CMSIS_core_DebugFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM7_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n"
  },
  {
    "path": "3rd_party/CMSIS/Include/core_sc000.h",
    "content": "/**************************************************************************//**\n * @file     core_sc000.h\n * @brief    CMSIS SC000 Core Peripheral Access Layer Header File\n * @version  V5.0.6\n * @date     12. November 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CORE_SC000_H_GENERIC\n#define __CORE_SC000_H_GENERIC\n\n#include <stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup SC000\n  @{\n */\n\n#include \"cmsis_version.h\"\n\n/*  CMSIS SC000 definitions */\n#define __SC000_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                /*!< \\deprecated [31:16] CMSIS HAL main version */\n#define __SC000_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                 /*!< \\deprecated [15:0]  CMSIS HAL sub version */\n#define __SC000_CMSIS_VERSION       ((__SC000_CMSIS_VERSION_MAIN << 16U) | \\\n                                      __SC000_CMSIS_VERSION_SUB           )  /*!< \\deprecated CMSIS HAL version number */\n\n#define __CORTEX_SC                 (000U)                                   /*!< Cortex secure core */\n\n/** __FPU_USED indicates whether an FPU is used or not.\n    This core does not support an FPU at all\n*/\n#define __FPU_USED       0U\n\n#if defined ( __CC_ARM )\n  #if defined __TARGET_FPU_VFP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined __ARM_FP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined __ARMVFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TI_ARM__ )\n  #if defined __TI_VFP_SUPPORT__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined __FPU_VFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_SC000_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_SC000_H_DEPENDANT\n#define __CORE_SC000_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __SC000_REV\n    #define __SC000_REV             0x0000U\n    #warning \"__SC000_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __MPU_PRESENT\n    #define __MPU_PRESENT             0U\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          2U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/*@} end of group SC000 */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core SCB Register\n  - Core SysTick Register\n  - Core MPU Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for Cortex-M processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\n    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\n    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n/*@} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[31U];\n  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RSERVED1[31U];\n  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[31U];\n  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[31U];\n        uint32_t RESERVED4[64U];\n  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */\n}  NVIC_Type;\n\n/*@} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n        uint32_t RESERVED0[1U];\n  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n        uint32_t RESERVED1[154U];\n  __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */\n} SCB_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\n#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\n#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\n#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n/*@} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\n  \\brief    Type definitions for the System Control and ID Register not in the SCB\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control and ID Register not in the SCB.\n */\ntypedef struct\n{\n        uint32_t RESERVED0[2U];\n  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\n} SCnSCB_Type;\n\n/* Auxiliary Control Register Definitions */\n#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */\n#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */\n\n/*@} end of group CMSIS_SCnotSCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/*@} end of group CMSIS_SysTick */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\n */\ntypedef struct\n{\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\n  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */\n} MPU_Type;\n\n/* MPU Type Register Definitions */\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\n\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\n\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\n\n/* MPU Control Register Definitions */\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\n\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\n\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\n\n/* MPU Region Number Register Definitions */\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\n\n/* MPU Region Base Address Register Definitions */\n#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */\n#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */\n\n#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */\n#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */\n\n#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */\n#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */\n\n/* MPU Region Attribute and Size Register Definitions */\n#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */\n#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */\n\n#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */\n#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */\n\n#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */\n#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */\n\n#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */\n#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */\n\n#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */\n#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */\n\n#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */\n#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */\n\n#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */\n#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */\n\n#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */\n#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */\n\n#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */\n#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */\n\n#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */\n#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */\n\n/*@} end of group CMSIS_MPU */\n#endif\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\n  \\brief    SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.\n            Therefore they are not covered by the SC000 header file.\n  @{\n */\n/*@} end of group CMSIS_CoreDebug */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n/*@} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Core Hardware */\n#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\n#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\n#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\n#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\n\n#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */\n#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\n#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\n#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */\n  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */\n#endif\n\n/*@} */\n\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n#ifdef CMSIS_NVIC_VIRTUAL\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\n  #endif\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\n#else\n/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for SC000 */\n/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for SC000 */\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\n/*#define NVIC_GetActive              __NVIC_GetActive             not available for SC000 */\n  #define NVIC_SetPriority            __NVIC_SetPriority\n  #define NVIC_GetPriority            __NVIC_GetPriority\n  #define NVIC_SystemReset            __NVIC_SystemReset\n#endif /* CMSIS_NVIC_VIRTUAL */\n\n#ifdef CMSIS_VECTAB_VIRTUAL\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\n  #endif\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetVector              __NVIC_SetVector\n  #define NVIC_GetVector              __NVIC_GetVector\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\n\n#define NVIC_USER_IRQ_OFFSET          16\n\n\n/* The following EXC_RETURN values are saved the LR on exception entry */\n#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */\n#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */\n#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */\n\n\n/* Interrupt Priorities are WORD accessible only under Armv6-M                  */\n/* The following MACROS handle generation of the register offset and byte masks */\n#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)\n#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )\n#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )\n\n\n/**\n  \\brief   Enable Interrupt\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    __COMPILER_BARRIER();\n    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __COMPILER_BARRIER();\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __DSB();\n    __ISB();\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every processor exception.\n */\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n  else\n  {\n    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Vector\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n           VTOR must been relocated to SRAM before.\n  \\param [in]   IRQn      Interrupt number\n  \\param [in]   vector    Address of interrupt handler function\n */\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\n  /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */\n}\n\n\n/**\n  \\brief   Get Interrupt Vector\n  \\details Reads an interrupt vector from interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn      Interrupt number.\n  \\return                 Address of interrupt handler function\n */\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                 SCB_AIRCR_SYSRESETREQ_Msk);\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n/*@} end of CMSIS_Core_NVICFunctions */\n\n\n/* ##########################  FPU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\n  \\brief    Function that provides FPU type.\n  @{\n */\n\n/**\n  \\brief   get FPU type\n  \\details returns the FPU type\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n */\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\n{\n    return 0U;           /* No FPU */\n}\n\n\n/*@} end of CMSIS_Core_FpuFunctions */\n\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#endif\n\n/*@} end of CMSIS_Core_SysTickFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_SC000_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n"
  },
  {
    "path": "3rd_party/CMSIS/Include/core_sc300.h",
    "content": "/**************************************************************************//**\n * @file     core_sc300.h\n * @brief    CMSIS SC300 Core Peripheral Access Layer Header File\n * @version  V5.0.8\n * @date     31. May 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CORE_SC300_H_GENERIC\n#define __CORE_SC300_H_GENERIC\n\n#include <stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup SC3000\n  @{\n */\n\n#include \"cmsis_version.h\"\n\n/*  CMSIS SC300 definitions */\n#define __SC300_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                /*!< \\deprecated [31:16] CMSIS HAL main version */\n#define __SC300_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                 /*!< \\deprecated [15:0]  CMSIS HAL sub version */\n#define __SC300_CMSIS_VERSION       ((__SC300_CMSIS_VERSION_MAIN << 16U) | \\\n                                      __SC300_CMSIS_VERSION_SUB           )  /*!< \\deprecated CMSIS HAL version number */\n\n#define __CORTEX_SC                 (300U)                                   /*!< Cortex secure core */\n\n/** __FPU_USED indicates whether an FPU is used or not.\n    This core does not support an FPU at all\n*/\n#define __FPU_USED       0U\n\n#if defined ( __CC_ARM )\n  #if defined __TARGET_FPU_VFP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined __ARM_FP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined __ARMVFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TI_ARM__ )\n  #if defined __TI_VFP_SUPPORT__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined __FPU_VFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_SC300_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_SC300_H_DEPENDANT\n#define __CORE_SC300_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __SC300_REV\n    #define __SC300_REV               0x0000U\n    #warning \"__SC300_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __MPU_PRESENT\n    #define __MPU_PRESENT             0U\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          3U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/*@} end of group SC300 */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core SCB Register\n  - Core SysTick Register\n  - Core Debug Register\n  - Core MPU Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for Cortex-M processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */\n#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */\n    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */\n    uint32_t _reserved1:8;               /*!< bit: 16..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit */\n    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */\n#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */\n\n#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */\n#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */\n#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\n    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\n#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\n\n/*@} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[24U];\n  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RESERVED1[24U];\n  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[24U];\n  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[24U];\n  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\n        uint32_t RESERVED4[56U];\n  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */\n        uint32_t RESERVED5[644U];\n  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */\n}  NVIC_Type;\n\n/* Software Triggered Interrupt Register Definitions */\n#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */\n#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */\n\n/*@} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */\n  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */\n  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */\n  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */\n  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */\n  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */\n  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */\n  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */\n  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */\n  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */\n  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */\n        uint32_t RESERVED0[5U];\n  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */\n        uint32_t RESERVED1[129U];\n  __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */\n} SCB_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\n#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\n#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n/* SCB Vector Table Offset Register Definitions */\n#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */\n#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */\n\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\n#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */\n#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */\n#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\n#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\n\n#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\n#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\n\n#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\n#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\n#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\n\n#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */\n#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */\n#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */\n\n#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */\n#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */\n\n#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */\n#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */\n\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */\n#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */\n\n#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */\n#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */\n\n#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */\n#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */\n\n#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\n#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\n\n#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\n#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\n\n#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */\n#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */\n\n#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\n#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\n\n#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */\n#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */\n\n#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */\n#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */\n\n#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */\n#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */\n\n/* SCB Configurable Fault Status Register Definitions */\n#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */\n#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */\n\n#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */\n#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */\n\n#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */\n#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\n\n/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */\n#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */\n\n#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */\n#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */\n\n#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\n#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\n\n#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */\n#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\n\n#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */\n#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\n\n/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */\n#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */\n\n#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */\n#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */\n\n#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */\n#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */\n\n#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */\n#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\n\n#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */\n#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */\n\n#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */\n#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */\n\n/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */\n#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\n\n#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */\n#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */\n\n#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */\n#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */\n\n#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */\n#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */\n\n#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */\n#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */\n\n#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\n#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\n\n/* SCB Hard Fault Status Register Definitions */\n#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */\n#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */\n\n#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */\n#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */\n\n#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */\n#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */\n\n/* SCB Debug Fault Status Register Definitions */\n#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */\n#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */\n\n#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */\n#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */\n\n#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */\n#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */\n\n#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */\n#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */\n\n#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */\n#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */\n\n/*@} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\n  \\brief    Type definitions for the System Control and ID Register not in the SCB\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control and ID Register not in the SCB.\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1U];\n  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */\n  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\n} SCnSCB_Type;\n\n/* Interrupt Controller Type Register Definitions */\n#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */\n#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */\n\n/* Auxiliary Control Register Definitions */\n#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */\n#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */\n\n#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */\n#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */\n\n#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */\n#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */\n\n/*@} end of group CMSIS_SCnotSCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/*@} end of group CMSIS_SysTick */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)\n  \\brief    Type definitions for the Instrumentation Trace Macrocell (ITM)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).\n */\ntypedef struct\n{\n  __OM  union\n  {\n    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */\n    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */\n    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */\n  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */\n        uint32_t RESERVED0[864U];\n  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */\n        uint32_t RESERVED1[15U];\n  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */\n        uint32_t RESERVED2[15U];\n  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */\n        uint32_t RESERVED3[32U];\n        uint32_t RESERVED4[43U];\n  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */\n        uint32_t RESERVED5[6U];\n  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */\n  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */\n  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */\n  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */\n  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */\n  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */\n  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */\n  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */\n  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */\n  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */\n  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */\n  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */\n} ITM_Type;\n\n/* ITM Trace Privilege Register Definitions */\n#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */\n#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */\n\n/* ITM Trace Control Register Definitions */\n#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */\n#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */\n\n#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */\n#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */\n\n#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */\n#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */\n\n#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */\n#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */\n\n#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */\n#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */\n\n#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */\n#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */\n\n#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */\n#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */\n\n#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */\n#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */\n\n#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */\n#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */\n\n/* ITM Lock Status Register Definitions */\n#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */\n#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */\n\n#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */\n#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */\n\n#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */\n#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */\n\n/*@}*/ /* end of group CMSIS_ITM */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\n  \\brief    Type definitions for the Data Watchpoint and Trace (DWT)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\n  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */\n  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */\n  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */\n  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */\n  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */\n  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */\n  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\n  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\n  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */\n  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\n        uint32_t RESERVED0[1U];\n  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\n  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */\n  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\n        uint32_t RESERVED1[1U];\n  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\n  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */\n  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\n        uint32_t RESERVED2[1U];\n  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\n  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */\n  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\n} DWT_Type;\n\n/* DWT Control Register Definitions */\n#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\n#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\n\n#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\n#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\n\n#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\n#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\n\n#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\n#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\n\n#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\n#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\n\n#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */\n#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */\n\n#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */\n#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */\n\n#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */\n#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */\n\n#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */\n#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */\n\n#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */\n#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */\n\n#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */\n#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */\n\n#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */\n#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */\n\n#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */\n#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */\n\n#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */\n#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */\n\n#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */\n#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */\n\n#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */\n#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */\n\n#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */\n#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */\n\n#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */\n#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */\n\n/* DWT CPI Count Register Definitions */\n#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */\n#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */\n\n/* DWT Exception Overhead Count Register Definitions */\n#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */\n#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */\n\n/* DWT Sleep Count Register Definitions */\n#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */\n#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */\n\n/* DWT LSU Count Register Definitions */\n#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */\n#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */\n\n/* DWT Folded-instruction Count Register Definitions */\n#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */\n#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */\n\n/* DWT Comparator Mask Register Definitions */\n#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */\n#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */\n\n/* DWT Comparator Function Register Definitions */\n#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\n#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\n\n#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */\n#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */\n\n#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */\n#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */\n\n#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\n#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\n\n#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */\n#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */\n\n#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */\n#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */\n\n#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */\n#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */\n\n#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */\n#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */\n\n#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */\n#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */\n\n/*@}*/ /* end of group CMSIS_DWT */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_TPI     Trace Port Interface (TPI)\n  \\brief    Type definitions for the Trace Port Interface (TPI)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Trace Port Interface Register (TPI).\n */\ntypedef struct\n{\n  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */\n  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */\n        uint32_t RESERVED0[2U];\n  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\n        uint32_t RESERVED1[55U];\n  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\n        uint32_t RESERVED2[131U];\n  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\n  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\n  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */\n        uint32_t RESERVED3[759U];\n  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */\n  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */\n  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */\n        uint32_t RESERVED4[1U];\n  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */\n  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */\n  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */\n        uint32_t RESERVED5[39U];\n  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */\n  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */\n        uint32_t RESERVED7[8U];\n  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */\n  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */\n} TPI_Type;\n\n/* TPI Asynchronous Clock Prescaler Register Definitions */\n#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */\n#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */\n\n/* TPI Selected Pin Protocol Register Definitions */\n#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\n#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\n\n/* TPI Formatter and Flush Status Register Definitions */\n#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\n#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\n\n#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\n#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\n\n#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\n#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\n\n#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\n#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\n\n/* TPI Formatter and Flush Control Register Definitions */\n#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\n#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\n\n#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\n#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\n\n/* TPI TRIGGER Register Definitions */\n#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */\n#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */\n\n/* TPI Integration ETM Data Register Definitions (FIFO0) */\n#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */\n#define TPI_FIFO0_ITM_ATVALID_Msk          (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */\n\n#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */\n#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */\n\n#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */\n#define TPI_FIFO0_ETM_ATVALID_Msk          (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */\n\n#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */\n#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */\n\n#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */\n#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */\n\n#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */\n#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */\n\n#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */\n#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */\n\n/* TPI ITATBCTR2 Register Definitions */\n#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */\n#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */\n\n#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */\n#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */\n\n/* TPI Integration ITM Data Register Definitions (FIFO1) */\n#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */\n#define TPI_FIFO1_ITM_ATVALID_Msk          (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */\n\n#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */\n#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */\n\n#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */\n#define TPI_FIFO1_ETM_ATVALID_Msk          (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */\n\n#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */\n#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */\n\n#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */\n#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */\n\n#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */\n#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */\n\n#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */\n#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */\n\n/* TPI ITATBCTR0 Register Definitions */\n#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */\n#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */\n\n#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */\n#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */\n\n/* TPI Integration Mode Control Register Definitions */\n#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */\n#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */\n\n/* TPI DEVID Register Definitions */\n#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\n#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\n\n#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\n#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\n\n#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\n#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\n\n#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */\n#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */\n\n#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */\n#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */\n\n#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */\n#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */\n\n/* TPI DEVTYPE Register Definitions */\n#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */\n#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\n\n#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */\n#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\n\n/*@}*/ /* end of group CMSIS_TPI */\n\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\n */\ntypedef struct\n{\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\n  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */\n  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */\n  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */\n  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */\n  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */\n  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */\n  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */\n} MPU_Type;\n\n/* MPU Type Register Definitions */\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\n\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\n\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\n\n/* MPU Control Register Definitions */\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\n\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\n\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\n\n/* MPU Region Number Register Definitions */\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\n\n/* MPU Region Base Address Register Definitions */\n#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */\n#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */\n\n#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */\n#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */\n\n#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */\n#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */\n\n/* MPU Region Attribute and Size Register Definitions */\n#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */\n#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */\n\n#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */\n#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */\n\n#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */\n#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */\n\n#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */\n#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */\n\n#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */\n#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */\n\n#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */\n#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */\n\n#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */\n#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */\n\n#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */\n#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */\n\n#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */\n#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */\n\n#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */\n#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */\n\n/*@} end of group CMSIS_MPU */\n#endif\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\n  \\brief    Type definitions for the Core Debug Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Core Debug Register (CoreDebug).\n */\ntypedef struct\n{\n  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\n  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\n  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\n  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\n} CoreDebug_Type;\n\n/* Debug Halting Control and Status Register Definitions */\n#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */\n#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\n\n#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */\n#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\n\n#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\n#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\n\n#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */\n#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\n\n#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */\n#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\n\n#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */\n#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\n\n#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */\n#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\n\n#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\n#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\n\n#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */\n#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\n\n#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */\n#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\n\n#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */\n#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\n\n#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */\n#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\n\n/* Debug Core Register Selector Register Definitions */\n#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */\n#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\n\n#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */\n#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */\n\n/* Debug Exception and Monitor Control Register Definitions */\n#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */\n#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */\n\n#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */\n#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */\n\n#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */\n#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */\n\n#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */\n#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */\n\n#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */\n#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */\n\n#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */\n#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\n\n#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */\n#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */\n\n#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */\n#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */\n\n#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */\n#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */\n\n#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */\n#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */\n\n#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */\n#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\n\n#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */\n#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */\n\n#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */\n#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */\n\n/*@} end of group CMSIS_CoreDebug */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n/*@} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Core Hardware */\n#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\n#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */\n#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */\n#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */\n#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */\n#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\n#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\n#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\n\n#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */\n#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\n#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\n#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\n#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */\n#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */\n#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */\n#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */\n  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */\n#endif\n\n/*@} */\n\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Debug Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n#ifdef CMSIS_NVIC_VIRTUAL\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\n  #endif\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\n  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\n  #define NVIC_GetActive              __NVIC_GetActive\n  #define NVIC_SetPriority            __NVIC_SetPriority\n  #define NVIC_GetPriority            __NVIC_GetPriority\n  #define NVIC_SystemReset            __NVIC_SystemReset\n#endif /* CMSIS_NVIC_VIRTUAL */\n\n#ifdef CMSIS_VECTAB_VIRTUAL\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\n  #endif\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetVector              __NVIC_SetVector\n  #define NVIC_GetVector              __NVIC_GetVector\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\n\n#define NVIC_USER_IRQ_OFFSET          16\n\n\n/* The following EXC_RETURN values are saved the LR on exception entry */\n#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */\n#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */\n#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */\n\n\n/**\n  \\brief   Set Priority Grouping\n  \\details Sets the priority grouping field using the required unlock sequence.\n           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\n           Only values from 0..7 are used.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]      PriorityGroup  Priority grouping field.\n */\n__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\n{\n  uint32_t reg_value;\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\n\n  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */\n  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\n  reg_value  =  (reg_value                                   |\n                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */\n  SCB->AIRCR =  reg_value;\n}\n\n\n/**\n  \\brief   Get Priority Grouping\n  \\details Reads the priority grouping field from the NVIC Interrupt Controller.\n  \\return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\n{\n  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\n}\n\n\n/**\n  \\brief   Enable Interrupt\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    __COMPILER_BARRIER();\n    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __COMPILER_BARRIER();\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __DSB();\n    __ISB();\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt\n  \\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every processor exception.\n */\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n  else\n  {\n    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Encode Priority\n  \\details Encodes the priority for an interrupt with the given priority group,\n           preemptive priority value, and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\n */\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  return (\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\n         );\n}\n\n\n/**\n  \\brief   Decode Priority\n  \\details Decodes an interrupt priority value with a given priority group to\n           preemptive priority value and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\n */\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\n}\n\n\n/**\n  \\brief   Set Interrupt Vector\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n           VTOR must been relocated to SRAM before.\n  \\param [in]   IRQn      Interrupt number\n  \\param [in]   vector    Address of interrupt handler function\n */\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\n{\n  uint32_t vectors = (uint32_t )SCB->VTOR;\n  (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector;\n  /* ARM Application Note 321 states that the M3 does not require the architectural barrier */\n}\n\n\n/**\n  \\brief   Get Interrupt Vector\n  \\details Reads an interrupt vector from interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn      Interrupt number.\n  \\return                 Address of interrupt handler function\n */\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\n{\n  uint32_t vectors = (uint32_t )SCB->VTOR;\n  return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4));\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |\n                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\n                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n/*@} end of CMSIS_Core_NVICFunctions */\n\n\n/* ##########################  FPU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\n  \\brief    Function that provides FPU type.\n  @{\n */\n\n/**\n  \\brief   get FPU type\n  \\details returns the FPU type\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n */\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\n{\n    return 0U;           /* No FPU */\n}\n\n\n/*@} end of CMSIS_Core_FpuFunctions */\n\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#endif\n\n/*@} end of CMSIS_Core_SysTickFunctions */\n\n\n\n/* ##################################### Debug In/Output function ########################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_core_DebugFunctions ITM Functions\n  \\brief    Functions that access the ITM debug interface.\n  @{\n */\n\nextern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */\n#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \\ref ITM_RxBuffer is ready for next character. */\n\n\n/**\n  \\brief   ITM Send Character\n  \\details Transmits a character via the ITM channel 0, and\n           \\li Just returns when no debugger is connected that has booked the output.\n           \\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\n  \\param [in]     ch  Character to transmit.\n  \\returns            Character to transmit.\n */\n__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\n{\n  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */\n      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */\n  {\n    while (ITM->PORT[0U].u32 == 0UL)\n    {\n      __NOP();\n    }\n    ITM->PORT[0U].u8 = (uint8_t)ch;\n  }\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Receive Character\n  \\details Inputs a character via the external variable \\ref ITM_RxBuffer.\n  \\return             Received character.\n  \\return         -1  No character pending.\n */\n__STATIC_INLINE int32_t ITM_ReceiveChar (void)\n{\n  int32_t ch = -1;                           /* no character available */\n\n  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\n  {\n    ch = ITM_RxBuffer;\n    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */\n  }\n\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Check Character\n  \\details Checks whether a character is pending for reading in the variable \\ref ITM_RxBuffer.\n  \\return          0  No character available.\n  \\return          1  Character available.\n */\n__STATIC_INLINE int32_t ITM_CheckChar (void)\n{\n\n  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\n  {\n    return (0);                              /* no character available */\n  }\n  else\n  {\n    return (1);                              /*    character available */\n  }\n}\n\n/*@} end of CMSIS_core_DebugFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_SC300_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n"
  },
  {
    "path": "3rd_party/CMSIS/Include/mpu_armv7.h",
    "content": "/******************************************************************************\n * @file     mpu_armv7.h\n * @brief    CMSIS MPU API for Armv7-M MPU\n * @version  V5.1.0\n * @date     08. March 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2017-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header    /* treat file as system include file */\n#endif\n\n#ifndef ARM_MPU_ARMV7_H\n#define ARM_MPU_ARMV7_H\n\n#define ARM_MPU_REGION_SIZE_32B      ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes\n#define ARM_MPU_REGION_SIZE_64B      ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes\n#define ARM_MPU_REGION_SIZE_128B     ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes\n#define ARM_MPU_REGION_SIZE_256B     ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes\n#define ARM_MPU_REGION_SIZE_512B     ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes\n#define ARM_MPU_REGION_SIZE_1KB      ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte\n#define ARM_MPU_REGION_SIZE_2KB      ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes\n#define ARM_MPU_REGION_SIZE_4KB      ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes\n#define ARM_MPU_REGION_SIZE_8KB      ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes\n#define ARM_MPU_REGION_SIZE_16KB     ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes\n#define ARM_MPU_REGION_SIZE_32KB     ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes\n#define ARM_MPU_REGION_SIZE_64KB     ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes\n#define ARM_MPU_REGION_SIZE_128KB    ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes\n#define ARM_MPU_REGION_SIZE_256KB    ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes\n#define ARM_MPU_REGION_SIZE_512KB    ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes\n#define ARM_MPU_REGION_SIZE_1MB      ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte\n#define ARM_MPU_REGION_SIZE_2MB      ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes\n#define ARM_MPU_REGION_SIZE_4MB      ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes\n#define ARM_MPU_REGION_SIZE_8MB      ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes\n#define ARM_MPU_REGION_SIZE_16MB     ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes\n#define ARM_MPU_REGION_SIZE_32MB     ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes\n#define ARM_MPU_REGION_SIZE_64MB     ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes\n#define ARM_MPU_REGION_SIZE_128MB    ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes\n#define ARM_MPU_REGION_SIZE_256MB    ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes\n#define ARM_MPU_REGION_SIZE_512MB    ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes\n#define ARM_MPU_REGION_SIZE_1GB      ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte\n#define ARM_MPU_REGION_SIZE_2GB      ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes\n#define ARM_MPU_REGION_SIZE_4GB      ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes\n\n#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access\n#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only\n#define ARM_MPU_AP_URO  2U ///!< MPU Access Permission unprivileged access read-only\n#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access\n#define ARM_MPU_AP_PRO  5U ///!< MPU Access Permission privileged access read-only\n#define ARM_MPU_AP_RO   6U ///!< MPU Access Permission read-only access\n\n/** MPU Region Base Address Register Value\n*\n* \\param Region The region to be configured, number 0 to 15.\n* \\param BaseAddress The base address for the region.\n*/\n#define ARM_MPU_RBAR(Region, BaseAddress) \\\n  (((BaseAddress) & MPU_RBAR_ADDR_Msk) |  \\\n   ((Region) & MPU_RBAR_REGION_Msk)    |  \\\n   (MPU_RBAR_VALID_Msk))\n\n/**\n* MPU Memory Access Attributes\n*\n* \\param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.\n* \\param IsShareable       Region is shareable between multiple bus masters.\n* \\param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.\n* \\param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.\n*/\n#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable)   \\\n  ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk)                  | \\\n   (((IsShareable)  << MPU_RASR_S_Pos)   & MPU_RASR_S_Msk)                    | \\\n   (((IsCacheable)  << MPU_RASR_C_Pos)   & MPU_RASR_C_Msk)                    | \\\n   (((IsBufferable) << MPU_RASR_B_Pos)   & MPU_RASR_B_Msk))\n\n/**\n* MPU Region Attribute and Size Register Value\n*\n* \\param DisableExec       Instruction access disable bit, 1= disable instruction fetches.\n* \\param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.\n* \\param AccessAttributes  Memory access attribution, see \\ref ARM_MPU_ACCESS_.\n* \\param SubRegionDisable  Sub-region disable field.\n* \\param Size              Region size of the region to be configured, for example 4K, 8K.\n*/\n#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size)    \\\n  ((((DisableExec)      << MPU_RASR_XN_Pos)   & MPU_RASR_XN_Msk)                                  | \\\n   (((AccessPermission) << MPU_RASR_AP_Pos)   & MPU_RASR_AP_Msk)                                  | \\\n   (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \\\n   (((SubRegionDisable) << MPU_RASR_SRD_Pos)  & MPU_RASR_SRD_Msk)                                 | \\\n   (((Size)             << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk)                                | \\\n   (((MPU_RASR_ENABLE_Msk))))\n\n/**\n* MPU Region Attribute and Size Register Value\n*\n* \\param DisableExec       Instruction access disable bit, 1= disable instruction fetches.\n* \\param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.\n* \\param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.\n* \\param IsShareable       Region is shareable between multiple bus masters.\n* \\param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.\n* \\param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.\n* \\param SubRegionDisable  Sub-region disable field.\n* \\param Size              Region size of the region to be configured, for example 4K, 8K.\n*/\n#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \\\n  ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)\n\n/**\n* MPU Memory Access Attribute for strongly ordered memory.\n*  - TEX: 000b\n*  - Shareable\n*  - Non-cacheable\n*  - Non-bufferable\n*/\n#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)\n\n/**\n* MPU Memory Access Attribute for device memory.\n*  - TEX: 000b (if shareable) or 010b (if non-shareable)\n*  - Shareable or non-shareable\n*  - Non-cacheable\n*  - Bufferable (if shareable) or non-bufferable (if non-shareable)\n*\n* \\param IsShareable Configures the device memory as shareable or non-shareable.\n*/\n#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))\n\n/**\n* MPU Memory Access Attribute for normal memory.\n*  - TEX: 1BBb (reflecting outer cacheability rules)\n*  - Shareable or non-shareable\n*  - Cacheable or non-cacheable (reflecting inner cacheability rules)\n*  - Bufferable or non-bufferable (reflecting inner cacheability rules)\n*\n* \\param OuterCp Configures the outer cache policy.\n* \\param InnerCp Configures the inner cache policy.\n* \\param IsShareable Configures the memory as shareable or non-shareable.\n*/\n#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))\n\n/**\n* MPU Memory Access Attribute non-cacheable policy.\n*/\n#define ARM_MPU_CACHEP_NOCACHE 0U\n\n/**\n* MPU Memory Access Attribute write-back, write and read allocate policy.\n*/\n#define ARM_MPU_CACHEP_WB_WRA 1U\n\n/**\n* MPU Memory Access Attribute write-through, no write allocate policy.\n*/\n#define ARM_MPU_CACHEP_WT_NWA 2U\n\n/**\n* MPU Memory Access Attribute write-back, no write allocate policy.\n*/\n#define ARM_MPU_CACHEP_WB_NWA 3U\n\n\n/**\n* Struct for a single MPU Region\n*/\ntypedef struct {\n  uint32_t RBAR; //!< The region base address register value (RBAR)\n  uint32_t RASR; //!< The region attribute and size register value (RASR) \\ref MPU_RASR\n} ARM_MPU_Region_t;\n\n/** Enable the MPU.\n* \\param MPU_Control Default access permissions for unconfigured regions.\n*/\n__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)\n{\n  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;\n#ifdef SCB_SHCSR_MEMFAULTENA_Msk\n  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;\n#endif\n  __DSB();\n  __ISB();\n}\n\n/** Disable the MPU.\n*/\n__STATIC_INLINE void ARM_MPU_Disable(void)\n{\n  __DMB();\n#ifdef SCB_SHCSR_MEMFAULTENA_Msk\n  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;\n#endif\n  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;\n}\n\n/** Clear and disable the given MPU region.\n* \\param rnr Region number to be cleared.\n*/\n__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)\n{\n  MPU->RNR = rnr;\n  MPU->RASR = 0U;\n}\n\n/** Configure an MPU region.\n* \\param rbar Value for RBAR register.\n* \\param rsar Value for RSAR register.\n*/\n__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)\n{\n  MPU->RBAR = rbar;\n  MPU->RASR = rasr;\n}\n\n/** Configure the given MPU region.\n* \\param rnr Region number to be configured.\n* \\param rbar Value for RBAR register.\n* \\param rsar Value for RSAR register.\n*/\n__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)\n{\n  MPU->RNR = rnr;\n  MPU->RBAR = rbar;\n  MPU->RASR = rasr;\n}\n\n/** Memcopy with strictly ordered memory access, e.g. for register targets.\n* \\param dst Destination data is copied to.\n* \\param src Source data is copied from.\n* \\param len Amount of data words to be copied.\n*/\n__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)\n{\n  uint32_t i;\n  for (i = 0U; i < len; ++i)\n  {\n    dst[i] = src[i];\n  }\n}\n\n/** Load the given number of MPU regions from a table.\n* \\param table Pointer to the MPU configuration table.\n* \\param cnt Amount of regions to be configured.\n*/\n__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)\n{\n  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;\n  while (cnt > MPU_TYPE_RALIASES) {\n    ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);\n    table += MPU_TYPE_RALIASES;\n    cnt -= MPU_TYPE_RALIASES;\n  }\n  ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);\n}\n\n#endif\n"
  },
  {
    "path": "3rd_party/CMSIS/Include/mpu_armv8.h",
    "content": "/******************************************************************************\n * @file     mpu_armv8.h\n * @brief    CMSIS MPU API for Armv8-M and Armv8.1-M MPU\n * @version  V5.1.0\n * @date     08. March 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2017-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header    /* treat file as system include file */\n#endif\n\n#ifndef ARM_MPU_ARMV8_H\n#define ARM_MPU_ARMV8_H\n\n/** \\brief Attribute for device memory (outer only) */\n#define ARM_MPU_ATTR_DEVICE                           ( 0U )\n\n/** \\brief Attribute for non-cacheable, normal memory */\n#define ARM_MPU_ATTR_NON_CACHEABLE                    ( 4U )\n\n/** \\brief Attribute for normal memory (outer and inner)\n* \\param NT Non-Transient: Set to 1 for non-transient data.\n* \\param WB Write-Back: Set to 1 to use write-back update policy.\n* \\param RA Read Allocation: Set to 1 to use cache allocation on read miss.\n* \\param WA Write Allocation: Set to 1 to use cache allocation on write miss.\n*/\n#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \\\n  (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))\n\n/** \\brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */\n#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)\n\n/** \\brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */\n#define ARM_MPU_ATTR_DEVICE_nGnRE  (1U)\n\n/** \\brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */\n#define ARM_MPU_ATTR_DEVICE_nGRE   (2U)\n\n/** \\brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */\n#define ARM_MPU_ATTR_DEVICE_GRE    (3U)\n\n/** \\brief Memory Attribute\n* \\param O Outer memory attributes\n* \\param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes\n*/\n#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))\n\n/** \\brief Normal memory non-shareable  */\n#define ARM_MPU_SH_NON   (0U)\n\n/** \\brief Normal memory outer shareable  */\n#define ARM_MPU_SH_OUTER (2U)\n\n/** \\brief Normal memory inner shareable  */\n#define ARM_MPU_SH_INNER (3U)\n\n/** \\brief Memory access permissions\n* \\param RO Read-Only: Set to 1 for read-only memory.\n* \\param NP Non-Privileged: Set to 1 for non-privileged memory.\n*/\n#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))\n\n/** \\brief Region Base Address Register value\n* \\param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.\n* \\param SH Defines the Shareability domain for this memory region.\n* \\param RO Read-Only: Set to 1 for a read-only memory region.\n* \\param NP Non-Privileged: Set to 1 for a non-privileged memory region.\n* \\oaram XN eXecute Never: Set to 1 for a non-executable memory region.\n*/\n#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \\\n  ((BASE & MPU_RBAR_BASE_Msk) | \\\n  ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \\\n  ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \\\n  ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))\n\n/** \\brief Region Limit Address Register value\n* \\param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.\n* \\param IDX The attribute index to be associated with this memory region.\n*/\n#define ARM_MPU_RLAR(LIMIT, IDX) \\\n  ((LIMIT & MPU_RLAR_LIMIT_Msk) | \\\n  ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \\\n  (MPU_RLAR_EN_Msk))\n\n#if defined(MPU_RLAR_PXN_Pos)\n\n/** \\brief Region Limit Address Register with PXN value\n* \\param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.\n* \\param PXN Privileged execute never. Defines whether code can be executed from this privileged region.\n* \\param IDX The attribute index to be associated with this memory region.\n*/\n#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \\\n  ((LIMIT & MPU_RLAR_LIMIT_Msk) | \\\n  ((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \\\n  ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \\\n  (MPU_RLAR_EN_Msk))\n\n#endif\n\n/**\n* Struct for a single MPU Region\n*/\ntypedef struct {\n  uint32_t RBAR;                   /*!< Region Base Address Register value */\n  uint32_t RLAR;                   /*!< Region Limit Address Register value */\n} ARM_MPU_Region_t;\n\n/** Enable the MPU.\n* \\param MPU_Control Default access permissions for unconfigured regions.\n*/\n__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)\n{\n  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;\n#ifdef SCB_SHCSR_MEMFAULTENA_Msk\n  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;\n#endif\n  __DSB();\n  __ISB();\n}\n\n/** Disable the MPU.\n*/\n__STATIC_INLINE void ARM_MPU_Disable(void)\n{\n  __DMB();\n#ifdef SCB_SHCSR_MEMFAULTENA_Msk\n  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;\n#endif\n  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;\n}\n\n#ifdef MPU_NS\n/** Enable the Non-secure MPU.\n* \\param MPU_Control Default access permissions for unconfigured regions.\n*/\n__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)\n{\n  MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;\n#ifdef SCB_SHCSR_MEMFAULTENA_Msk\n  SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;\n#endif\n  __DSB();\n  __ISB();\n}\n\n/** Disable the Non-secure MPU.\n*/\n__STATIC_INLINE void ARM_MPU_Disable_NS(void)\n{\n  __DMB();\n#ifdef SCB_SHCSR_MEMFAULTENA_Msk\n  SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;\n#endif\n  MPU_NS->CTRL  &= ~MPU_CTRL_ENABLE_Msk;\n}\n#endif\n\n/** Set the memory attribute encoding to the given MPU.\n* \\param mpu Pointer to the MPU to be configured.\n* \\param idx The attribute index to be set [0-7]\n* \\param attr The attribute value to be set.\n*/\n__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)\n{\n  const uint8_t reg = idx / 4U;\n  const uint32_t pos = ((idx % 4U) * 8U);\n  const uint32_t mask = 0xFFU << pos;\n\n  if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {\n    return; // invalid index\n  }\n\n  mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));\n}\n\n/** Set the memory attribute encoding.\n* \\param idx The attribute index to be set [0-7]\n* \\param attr The attribute value to be set.\n*/\n__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)\n{\n  ARM_MPU_SetMemAttrEx(MPU, idx, attr);\n}\n\n#ifdef MPU_NS\n/** Set the memory attribute encoding to the Non-secure MPU.\n* \\param idx The attribute index to be set [0-7]\n* \\param attr The attribute value to be set.\n*/\n__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)\n{\n  ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);\n}\n#endif\n\n/** Clear and disable the given MPU region of the given MPU.\n* \\param mpu Pointer to MPU to be used.\n* \\param rnr Region number to be cleared.\n*/\n__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)\n{\n  mpu->RNR = rnr;\n  mpu->RLAR = 0U;\n}\n\n/** Clear and disable the given MPU region.\n* \\param rnr Region number to be cleared.\n*/\n__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)\n{\n  ARM_MPU_ClrRegionEx(MPU, rnr);\n}\n\n#ifdef MPU_NS\n/** Clear and disable the given Non-secure MPU region.\n* \\param rnr Region number to be cleared.\n*/\n__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)\n{\n  ARM_MPU_ClrRegionEx(MPU_NS, rnr);\n}\n#endif\n\n/** Configure the given MPU region of the given MPU.\n* \\param mpu Pointer to MPU to be used.\n* \\param rnr Region number to be configured.\n* \\param rbar Value for RBAR register.\n* \\param rlar Value for RLAR register.\n*/\n__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)\n{\n  mpu->RNR = rnr;\n  mpu->RBAR = rbar;\n  mpu->RLAR = rlar;\n}\n\n/** Configure the given MPU region.\n* \\param rnr Region number to be configured.\n* \\param rbar Value for RBAR register.\n* \\param rlar Value for RLAR register.\n*/\n__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)\n{\n  ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);\n}\n\n#ifdef MPU_NS\n/** Configure the given Non-secure MPU region.\n* \\param rnr Region number to be configured.\n* \\param rbar Value for RBAR register.\n* \\param rlar Value for RLAR register.\n*/\n__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)\n{\n  ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);\n}\n#endif\n\n/** Memcopy with strictly ordered memory access, e.g. for register targets.\n* \\param dst Destination data is copied to.\n* \\param src Source data is copied from.\n* \\param len Amount of data words to be copied.\n*/\n__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)\n{\n  uint32_t i;\n  for (i = 0U; i < len; ++i)\n  {\n    dst[i] = src[i];\n  }\n}\n\n/** Load the given number of MPU regions from a table to the given MPU.\n* \\param mpu Pointer to the MPU registers to be used.\n* \\param rnr First region number to be configured.\n* \\param table Pointer to the MPU configuration table.\n* \\param cnt Amount of regions to be configured.\n*/\n__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)\n{\n  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;\n  if (cnt == 1U) {\n    mpu->RNR = rnr;\n    ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);\n  } else {\n    uint32_t rnrBase   = rnr & ~(MPU_TYPE_RALIASES-1U);\n    uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;\n\n    mpu->RNR = rnrBase;\n    while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {\n      uint32_t c = MPU_TYPE_RALIASES - rnrOffset;\n      ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);\n      table += c;\n      cnt -= c;\n      rnrOffset = 0U;\n      rnrBase += MPU_TYPE_RALIASES;\n      mpu->RNR = rnrBase;\n    }\n\n    ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);\n  }\n}\n\n/** Load the given number of MPU regions from a table.\n* \\param rnr First region number to be configured.\n* \\param table Pointer to the MPU configuration table.\n* \\param cnt Amount of regions to be configured.\n*/\n__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)\n{\n  ARM_MPU_LoadEx(MPU, rnr, table, cnt);\n}\n\n#ifdef MPU_NS\n/** Load the given number of MPU regions from a table to the Non-secure MPU.\n* \\param rnr First region number to be configured.\n* \\param table Pointer to the MPU configuration table.\n* \\param cnt Amount of regions to be configured.\n*/\n__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)\n{\n  ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);\n}\n#endif\n\n#endif\n\n"
  },
  {
    "path": "3rd_party/CMSIS/Include/tz_context.h",
    "content": "/******************************************************************************\n * @file     tz_context.h\n * @brief    Context Management for Armv8-M TrustZone\n * @version  V1.0.1\n * @date     10. January 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2017-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef TZ_CONTEXT_H\n#define TZ_CONTEXT_H\n\n#include <stdint.h>\n\n#ifndef TZ_MODULEID_T\n#define TZ_MODULEID_T\n/// \\details Data type that identifies secure software modules called by a process.\ntypedef uint32_t TZ_ModuleId_t;\n#endif\n\n/// \\details TZ Memory ID identifies an allocated memory slot.\ntypedef uint32_t TZ_MemoryId_t;\n\n/// Initialize secure context memory system\n/// \\return execution status (1: success, 0: error)\nuint32_t TZ_InitContextSystem_S (void);\n\n/// Allocate context memory for calling secure software modules in TrustZone\n/// \\param[in]  module   identifies software modules called from non-secure mode\n/// \\return value != 0 id TrustZone memory slot identifier\n/// \\return value 0    no memory available or internal error\nTZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);\n\n/// Free context memory that was previously allocated with \\ref TZ_AllocModuleContext_S\n/// \\param[in]  id  TrustZone memory slot identifier\n/// \\return execution status (1: success, 0: error)\nuint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);\n\n/// Load secure context (called on RTOS thread context switch)\n/// \\param[in]  id  TrustZone memory slot identifier\n/// \\return execution status (1: success, 0: error)\nuint32_t TZ_LoadContext_S (TZ_MemoryId_t id);\n\n/// Store secure context (called on RTOS thread context switch)\n/// \\param[in]  id  TrustZone memory slot identifier\n/// \\return execution status (1: success, 0: error)\nuint32_t TZ_StoreContext_S (TZ_MemoryId_t id);\n\n#endif  // TZ_CONTEXT_H\n"
  },
  {
    "path": "3rd_party/CMSIS/LICENSE.txt",
    "content": "                                 Apache License\n                           Version 2.0, January 2004\n                        http://www.apache.org/licenses/\n\n   TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION\n\n   1. Definitions.\n\n      \"License\" shall mean the terms and conditions for use, reproduction,\n      and distribution as defined by Sections 1 through 9 of this document.\n\n      \"Licensor\" shall mean the copyright owner or entity authorized by\n      the copyright owner that is granting the License.\n\n      \"Legal Entity\" shall mean the union of the acting entity and all\n      other entities that control, are controlled by, or are under common\n      control with that entity. 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  },
  {
    "path": "3rd_party/CMSIS/README.txt",
    "content": "About CMSIS\n===========\nThis folder contains the Cortex Microcontroller Software Interface Standard\nCMSIS 5.6.0 (https://github.com/ARM-software/CMSIS_5/releases/tag/5.6.0).\n\nCMSIS provides a single standard across all Cortex-M processor series vendors.\nIt enables code re-use and code sharing across software projects and reduces\ntime-to-market for new embedded applications.\n\n\nLicensing\n=========\nCMSIS-5 is released under the terms of the Apache License Version 2.0\nincluded in the file LICENSE.txt.\n\n\nComplete Downloads\n==================\nTo reduce the size of the distribution, this CMSIS folder contains only the\nInclude sub-directory. The complete CMSIS-5 is available at:\n\nhttps://github.com/ARM-software/CMSIS_5\n\n"
  },
  {
    "path": "3rd_party/ek-tm4c123gxl/README.txt",
    "content": "This directory contains the support code for the EK-TM4C123GXL board\n(TivaC LauchPad).\n\nThe sub-directories contain code that is specific to the particular\nARM toolchains, such as ARM (MDK-ARM), GCC, and IAR.\n\n\nCMSIS-Compliant Device Files\n============================\nThe code also includes the CMSIS-compliant interface to the TM4C123GH6PM\nMCU files:\n\nTM4C123GH6PM.h\nsystem_TM4C123GH6PM.h\nsystem_TM4C123GH6PM.c\narm\\startup_TM4C123GH6PM.s\ngcc\\startup_TM4C123GH6PM.c\niar\\startup_TM4C123GH6PM.s\n\n\nAdjusting the CPU Clock Speed\n-----------------------------\nThe current setting is to run at 50MHz from PLL, but the CPU clock speed\ncan be modified by editing the file system_TM4C123GH6PM.c.\n"
  },
  {
    "path": "3rd_party/ek-tm4c123gxl/TM4C123GH6PM.h",
    "content": "/*****************************************************************************\n* Modified from the original as follows:\n* - defined TARGET_IS_BLIZZARD_RA1 for compatibility with the TI library\n* - in GPIOA_Type struct replaced first __I RESERVED0[255] with\n*   __IO uint32_t DATA_Bits[255] to access the individual GPIOA bits.\n* - added options for the ARMCC v6 compiler (CLANG)\n*\n* Quantum Leaps on 2018-01-31\n* https://www.state-machine.com\n*****************************************************************************/\n\n/****************************************************************************************************//**\n * @file     TM4C123GH6PM.h\n *\n * @brief    CMSIS Cortex-M4 Peripheral Access Layer Header File for\n *           TM4C123GH6PM from Texas Instruments.\n *\n * @version  V12591\n * @date     19. February 2014\n *\n * @note     Generated with SVDConv V2.79v\n *           from CMSIS SVD File 'TM4C123GH6PM.svd.xml' Version 12591,\n *\n * @par\n *           Software License Agreement\n *\n *           Texas Instruments (TI) is supplying this software for use solely and\n *           exclusively on TI's microcontroller products. The software is owned by\n *           TI and/or its suppliers, and is protected under applicable copyright\n *           laws. You may not combine this software with \"viral\" open-source\n *           software in order to form a larger program.\n *\n *           THIS SOFTWARE IS PROVIDED \"AS IS\" AND WITH ALL FAULTS.\n *           NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT\n *           NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n *           A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY\n *           CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL\n *           DAMAGES, FOR ANY REASON WHATSOEVER.\n *\n *\n *\n *******************************************************************************************************/\n\n\n\n/** @addtogroup Texas Instruments\n  * @{\n  */\n\n/** @addtogroup TM4C123GH6PM\n  * @{\n  */\n\n#ifndef TM4C123GH6PM_H\n#define TM4C123GH6PM_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* -------------------------  Interrupt Number Definition  ------------------------ */\n\ntypedef enum {\n/* -------------------  Cortex-M4 Processor Exceptions Numbers  ------------------- */\n  Reset_IRQn                    = -15,              /*!<   1  Reset Vector, invoked on Power up and warm reset                 */\n  NonMaskableInt_IRQn           = -14,              /*!<   2  Non maskable Interrupt, cannot be stopped or preempted           */\n  HardFault_IRQn                = -13,              /*!<   3  Hard Fault, all classes of Fault                                 */\n  MemoryManagement_IRQn         = -12,              /*!<   4  Memory Management, MPU mismatch, including Access Violation\n                                                         and No Match                                                          */\n  BusFault_IRQn                 = -11,              /*!<   5  Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory\n                                                         related Fault                                                         */\n  UsageFault_IRQn               = -10,              /*!<   6  Usage Fault, i.e. Undef Instruction, Illegal State Transition    */\n  SVCall_IRQn                   =  -5,              /*!<  11  System Service Call via SVC instruction                          */\n  DebugMonitor_IRQn             =  -4,              /*!<  12  Debug Monitor                                                    */\n  PendSV_IRQn                   =  -2,              /*!<  14  Pendable request for system service                              */\n  SysTick_IRQn                  =  -1,              /*!<  15  System Tick Timer                                                */\n/* -------------------  TM4C123GH6PM Specific Interrupt Numbers  ------------------ */\n  GPIOA_IRQn                    =   0,              /*!<   0  GPIOA                                                            */\n  GPIOB_IRQn                    =   1,              /*!<   1  GPIOB                                                            */\n  GPIOC_IRQn                    =   2,              /*!<   2  GPIOC                                                            */\n  GPIOD_IRQn                    =   3,              /*!<   3  GPIOD                                                            */\n  GPIOE_IRQn                    =   4,              /*!<   4  GPIOE                                                            */\n  UART0_IRQn                    =   5,              /*!<   5  UART0                                                            */\n  UART1_IRQn                    =   6,              /*!<   6  UART1                                                            */\n  SSI0_IRQn                     =   7,              /*!<   7  SSI0                                                             */\n  I2C0_IRQn                     =   8,              /*!<   8  I2C0                                                             */\n  PWM0_FAULT_IRQn               =   9,              /*!<   9  PWM0_FAULT                                                       */\n  PWM0_0_IRQn                   =  10,              /*!<  10  PWM0_0                                                           */\n  PWM0_1_IRQn                   =  11,              /*!<  11  PWM0_1                                                           */\n  PWM0_2_IRQn                   =  12,              /*!<  12  PWM0_2                                                           */\n  QEI0_IRQn                     =  13,              /*!<  13  QEI0                                                             */\n  ADC0SS0_IRQn                  =  14,              /*!<  14  ADC0SS0                                                          */\n  ADC0SS1_IRQn                  =  15,              /*!<  15  ADC0SS1                                                          */\n  ADC0SS2_IRQn                  =  16,              /*!<  16  ADC0SS2                                                          */\n  ADC0SS3_IRQn                  =  17,              /*!<  17  ADC0SS3                                                          */\n  WATCHDOG0_IRQn                =  18,              /*!<  18  WATCHDOG0                                                        */\n  TIMER0A_IRQn                  =  19,              /*!<  19  TIMER0A                                                          */\n  TIMER0B_IRQn                  =  20,              /*!<  20  TIMER0B                                                          */\n  TIMER1A_IRQn                  =  21,              /*!<  21  TIMER1A                                                          */\n  TIMER1B_IRQn                  =  22,              /*!<  22  TIMER1B                                                          */\n  TIMER2A_IRQn                  =  23,              /*!<  23  TIMER2A                                                          */\n  TIMER2B_IRQn                  =  24,              /*!<  24  TIMER2B                                                          */\n  COMP0_IRQn                    =  25,              /*!<  25  COMP0                                                            */\n  COMP1_IRQn                    =  26,              /*!<  26  COMP1                                                            */\n  SYSCTL_IRQn                   =  28,              /*!<  28  SYSCTL                                                           */\n  FLASH_CTRL_IRQn               =  29,              /*!<  29  FLASH_CTRL                                                       */\n  GPIOF_IRQn                    =  30,              /*!<  30  GPIOF                                                            */\n  UART2_IRQn                    =  33,              /*!<  33  UART2                                                            */\n  SSI1_IRQn                     =  34,              /*!<  34  SSI1                                                             */\n  TIMER3A_IRQn                  =  35,              /*!<  35  TIMER3A                                                          */\n  TIMER3B_IRQn                  =  36,              /*!<  36  TIMER3B                                                          */\n  I2C1_IRQn                     =  37,              /*!<  37  I2C1                                                             */\n  QEI1_IRQn                     =  38,              /*!<  38  QEI1                                                             */\n  CAN0_IRQn                     =  39,              /*!<  39  CAN0                                                             */\n  CAN1_IRQn                     =  40,              /*!<  40  CAN1                                                             */\n  HIB_IRQn                      =  43,              /*!<  43  HIB                                                              */\n  USB0_IRQn                     =  44,              /*!<  44  USB0                                                             */\n  PWM0_3_IRQn                   =  45,              /*!<  45  PWM0_3                                                           */\n  UDMA_IRQn                     =  46,              /*!<  46  UDMA                                                             */\n  UDMAERR_IRQn                  =  47,              /*!<  47  UDMAERR                                                          */\n  ADC1SS0_IRQn                  =  48,              /*!<  48  ADC1SS0                                                          */\n  ADC1SS1_IRQn                  =  49,              /*!<  49  ADC1SS1                                                          */\n  ADC1SS2_IRQn                  =  50,              /*!<  50  ADC1SS2                                                          */\n  ADC1SS3_IRQn                  =  51,              /*!<  51  ADC1SS3                                                          */\n  SSI2_IRQn                     =  57,              /*!<  57  SSI2                                                             */\n  SSI3_IRQn                     =  58,              /*!<  58  SSI3                                                             */\n  UART3_IRQn                    =  59,              /*!<  59  UART3                                                            */\n  UART4_IRQn                    =  60,              /*!<  60  UART4                                                            */\n  UART5_IRQn                    =  61,              /*!<  61  UART5                                                            */\n  UART6_IRQn                    =  62,              /*!<  62  UART6                                                            */\n  UART7_IRQn                    =  63,              /*!<  63  UART7                                                            */\n  I2C2_IRQn                     =  68,              /*!<  68  I2C2                                                             */\n  I2C3_IRQn                     =  69,              /*!<  69  I2C3                                                             */\n  TIMER4A_IRQn                  =  70,              /*!<  70  TIMER4A                                                          */\n  TIMER4B_IRQn                  =  71,              /*!<  71  TIMER4B                                                          */\n  TIMER5A_IRQn                  =  92,              /*!<  92  TIMER5A                                                          */\n  TIMER5B_IRQn                  =  93,              /*!<  93  TIMER5B                                                          */\n  WTIMER0A_IRQn                 =  94,              /*!<  94  WTIMER0A                                                         */\n  WTIMER0B_IRQn                 =  95,              /*!<  95  WTIMER0B                                                         */\n  WTIMER1A_IRQn                 =  96,              /*!<  96  WTIMER1A                                                         */\n  WTIMER1B_IRQn                 =  97,              /*!<  97  WTIMER1B                                                         */\n  WTIMER2A_IRQn                 =  98,              /*!<  98  WTIMER2A                                                         */\n  WTIMER2B_IRQn                 =  99,              /*!<  99  WTIMER2B                                                         */\n  WTIMER3A_IRQn                 = 100,              /*!< 100  WTIMER3A                                                         */\n  WTIMER3B_IRQn                 = 101,              /*!< 101  WTIMER3B                                                         */\n  WTIMER4A_IRQn                 = 102,              /*!< 102  WTIMER4A                                                         */\n  WTIMER4B_IRQn                 = 103,              /*!< 103  WTIMER4B                                                         */\n  WTIMER5A_IRQn                 = 104,              /*!< 104  WTIMER5A                                                         */\n  WTIMER5B_IRQn                 = 105,              /*!< 105  WTIMER5B                                                         */\n  SYSEXC_IRQn                   = 106,              /*!< 106  SYSEXC                                                           */\n  PWM1_0_IRQn                   = 134,              /*!< 134  PWM1_0                                                           */\n  PWM1_1_IRQn                   = 135,              /*!< 135  PWM1_1                                                           */\n  PWM1_2_IRQn                   = 136,              /*!< 136  PWM1_2                                                           */\n  PWM1_3_IRQn                   = 137,              /*!< 137  PWM1_3                                                           */\n  PWM1_FAULT_IRQn               = 138               /*!< 138  PWM1_FAULT                                                       */\n} IRQn_Type;\n\n/*\n * ===========================================================================\n * ---------- Interrupt Handler Prototypes -----------------------------------\n * ===========================================================================\n */\nvoid NMI_Handler(void);\nvoid HardFault_Handler(void);\nvoid MemManage_Handler(void);\nvoid BusFault_Handler(void);\nvoid UsageFault_Handler(void);\nvoid HardFault_Handler(void);\n\nvoid SVC_Handler(void);\nvoid DebugMon_Handler(void);\nvoid PendSV_Handler(void);\nvoid SysTick_Handler(void);\n\nvoid GPIOPortA_IRQHandler(void);\nvoid GPIOPortB_IRQHandler(void);\nvoid GPIOPortC_IRQHandler(void);\nvoid GPIOPortD_IRQHandler(void);\nvoid GPIOPortE_IRQHandler(void);\nvoid UART0_IRQHandler(void);\nvoid UART1_IRQHandler(void);\nvoid SSI0_IRQHandler(void);\nvoid I2C0_IRQHandler(void);\nvoid PWMFault_IRQHandler(void);\nvoid PWMGen0_IRQHandler(void);\nvoid PWMGen1_IRQHandler(void);\nvoid PWMGen2_IRQHandler(void);\nvoid QEI0_IRQHandler(void);\nvoid ADCSeq0_IRQHandler(void);\nvoid ADCSeq1_IRQHandler(void);\nvoid ADCSeq2_IRQHandler(void);\nvoid ADCSeq3_IRQHandler(void);\nvoid Watchdog_IRQHandler(void);\nvoid Timer0A_IRQHandler(void);\nvoid Timer0B_IRQHandler(void);\nvoid Timer1A_IRQHandler(void);\nvoid Timer1B_IRQHandler(void);\nvoid Timer2A_IRQHandler(void);\nvoid Timer2B_IRQHandler(void);\nvoid Comp0_IRQHandler(void);\nvoid Comp1_IRQHandler(void);\nvoid Comp2_IRQHandler(void);\nvoid SysCtrl_IRQHandler(void);\nvoid FlashCtrl_IRQHandler(void);\nvoid GPIOPortF_IRQHandler(void);\nvoid GPIOPortG_IRQHandler(void);\nvoid GPIOPortH_IRQHandler(void);\nvoid UART2_IRQHandler(void);\nvoid SSI1_IRQHandler(void);\nvoid Timer3A_IRQHandler(void);\nvoid Timer3B_IRQHandler(void);\nvoid I2C1_IRQHandler(void);\nvoid QEI1_IRQHandler(void);\nvoid CAN0_IRQHandler(void);\nvoid CAN1_IRQHandler(void);\nvoid CAN2_IRQHandler(void);\nvoid Hibernate_IRQHandler(void);\nvoid USB0_IRQHandler(void);\nvoid PWMGen3_IRQHandler(void);\nvoid uDMAST_IRQHandler(void);\nvoid uDMAError_IRQHandler(void);\nvoid ADC1Seq0_IRQHandler(void);\nvoid ADC1Seq1_IRQHandler(void);\nvoid ADC1Seq2_IRQHandler(void);\nvoid ADC1Seq3_IRQHandler(void);\nvoid I2S0_IRQHandler(void);\nvoid EBI0_IRQHandler(void);\nvoid GPIOPortJ_IRQHandler(void);\nvoid GPIOPortK_IRQHandler(void);\nvoid GPIOPortL_IRQHandler(void);\nvoid SSI2_IRQHandler(void);\nvoid SSI3_IRQHandler(void);\nvoid UART3_IRQHandler(void);\nvoid UART4_IRQHandler(void);\nvoid UART5_IRQHandler(void);\nvoid UART6_IRQHandler(void);\nvoid UART7_IRQHandler(void);\nvoid I2C2_IRQHandler(void);\nvoid I2C3_IRQHandler(void);\nvoid Timer4A_IRQHandler(void);\nvoid Timer4B_IRQHandler(void);\nvoid Timer5A_IRQHandler(void);\nvoid Timer5B_IRQHandler(void);\nvoid WideTimer0A_IRQHandler(void);\nvoid WideTimer0B_IRQHandler(void);\nvoid WideTimer1A_IRQHandler(void);\nvoid WideTimer1B_IRQHandler(void);\nvoid WideTimer2A_IRQHandler(void);\nvoid WideTimer2B_IRQHandler(void);\nvoid WideTimer3A_IRQHandler(void);\nvoid WideTimer3B_IRQHandler(void);\nvoid WideTimer4A_IRQHandler(void);\nvoid WideTimer4B_IRQHandler(void);\nvoid WideTimer5A_IRQHandler(void);\nvoid WideTimer5B_IRQHandler(void);\nvoid FPU_IRQHandler(void);\nvoid PECI0_IRQHandler(void);\nvoid LPC0_IRQHandler(void);\nvoid I2C4_IRQHandler(void);\nvoid I2C5_IRQHandler(void);\nvoid GPIOPortM_IRQHandler(void);\nvoid GPIOPortN_IRQHandler(void);\nvoid QEI2_IRQHandler(void);\nvoid Fan0_IRQHandler(void);\nvoid GPIOPortP0_IRQHandler(void);\nvoid GPIOPortP1_IRQHandler(void);\nvoid GPIOPortP2_IRQHandler(void);\nvoid GPIOPortP3_IRQHandler(void);\nvoid GPIOPortP4_IRQHandler(void);\nvoid GPIOPortP5_IRQHandler(void);\nvoid GPIOPortP6_IRQHandler(void);\nvoid GPIOPortP7_IRQHandler(void);\nvoid GPIOPortQ0_IRQHandler(void);\nvoid GPIOPortQ1_IRQHandler(void);\nvoid GPIOPortQ2_IRQHandler(void);\nvoid GPIOPortQ3_IRQHandler(void);\nvoid GPIOPortQ4_IRQHandler(void);\nvoid GPIOPortQ5_IRQHandler(void);\nvoid GPIOPortQ6_IRQHandler(void);\nvoid GPIOPortQ7_IRQHandler(void);\nvoid GPIOPortR_IRQHandler(void);\nvoid GPIOPortS_IRQHandler(void);\nvoid PWM1Gen0_IRQHandler(void);\nvoid PWM1Gen1_IRQHandler(void);\nvoid PWM1Gen2_IRQHandler(void);\nvoid PWM1Gen3_IRQHandler(void);\nvoid PWM1Fault_IRQHandler(void);\n\n\n/** @addtogroup Configuration_of_CMSIS\n  * @{\n  */\n\n\n/* ================================================================================ */\n/* ================      Processor and Core Peripheral Section     ================ */\n/* ================================================================================ */\n\n/* ----------------Configuration of the Cortex-M4 Processor and Core Peripherals---------------- */\n#define __CM4_REV                 0x0102            /*!< Cortex-M4 Core Revision                                               */\n#define __MPU_PRESENT                  1            /*!< MPU present or not                                                    */\n#define __NVIC_PRIO_BITS               3            /*!< Number of Bits used for Priority Levels                               */\n#define __Vendor_SysTickConfig         0            /*!< Set to 1 if different SysTick Config is used                          */\n#define __FPU_PRESENT                  1            /*!< FPU present or not                                                    */\n#define TARGET_IS_BLIZZARD_RA1         1            /*!< Class of device (for TI library)                                      */\n/** @} */ /* End of group Configuration_of_CMSIS */\n\n#ifdef __cplusplus\n}\n#endif\n\n#include \"core_cm4.h\"                               /*!< Cortex-M4 processor and core peripherals                              */\n#include \"system_TM4C123GH6PM.h\"                    /*!< TM4C123GH6PM System                                                   */\n\n\n/* ================================================================================ */\n/* ================       Device Specific Peripheral Section       ================ */\n/* ================================================================================ */\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/** @addtogroup Device_Peripheral_Registers\n  * @{\n  */\n\n\n/* -------------------  Start of section using anonymous unions  ------------------ */\n#if defined(__CC_ARM)\n  #pragma push\n  #pragma anon_unions\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  /* anonymous unions are enabled by default */\n#elif defined(__ICCARM__)\n  #pragma language=extended\n#elif defined(__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined(__TMS470__)\n/* anonymous unions are enabled by default */\n#elif defined(__TASKING__)\n  #pragma warning 586\n#else\n  #warning Not supported compiler type\n#endif\n\n\n\n/* ================================================================================ */\n/* ================                    WATCHDOG0                   ================ */\n/* ================================================================================ */\n\n\n/**\n  * @brief Register map for WATCHDOG0 peripheral (WATCHDOG0)\n  */\n\ntypedef struct {                                    /*!< WATCHDOG0 Structure                                                   */\n  __IO uint32_t  LOAD;                              /*!< Watchdog Load                                                         */\n  __IO uint32_t  VALUE;                             /*!< Watchdog Value                                                        */\n  __IO uint32_t  CTL;                               /*!< Watchdog Control                                                      */\n  __O  uint32_t  ICR;                               /*!< Watchdog Interrupt Clear                                              */\n  __IO uint32_t  RIS;                               /*!< Watchdog Raw Interrupt Status                                         */\n  __IO uint32_t  MIS;                               /*!< Watchdog Masked Interrupt Status                                      */\n  __I  uint32_t  RESERVED0[256];\n  __IO uint32_t  TEST;                              /*!< Watchdog Test                                                         */\n  __I  uint32_t  RESERVED1[505];\n  __IO uint32_t  LOCK;                              /*!< Watchdog Lock                                                         */\n} WATCHDOG0_Type;\n\n\n/* ================================================================================ */\n/* ================                      GPIOA                     ================ */\n/* ================================================================================ */\n\n\n/**\n  * @brief Register map for GPIOA peripheral (GPIOA)\n  */\n\ntypedef struct {                                    /*!< GPIOA Structure                                                       */\n  __IO uint32_t  DATA_Bits[255];                    /*!< GPIO bit combinations                                                 */\n  __IO uint32_t  DATA;                              /*!< GPIO Data                                                             */\n  __IO uint32_t  DIR;                               /*!< GPIO Direction                                                        */\n  __IO uint32_t  IS;                                /*!< GPIO Interrupt Sense                                                  */\n  __IO uint32_t  IBE;                               /*!< GPIO Interrupt Both Edges                                             */\n  __IO uint32_t  IEV;                               /*!< GPIO Interrupt Event                                                  */\n  __IO uint32_t  IM;                                /*!< GPIO Interrupt Mask                                                   */\n  __IO uint32_t  RIS;                               /*!< GPIO Raw Interrupt Status                                             */\n  __IO uint32_t  MIS;                               /*!< GPIO Masked Interrupt Status                                          */\n  __O  uint32_t  ICR;                               /*!< GPIO Interrupt Clear                                                  */\n  __IO uint32_t  AFSEL;                             /*!< GPIO Alternate Function Select                                        */\n  __I  uint32_t  RESERVED1[55];\n  __IO uint32_t  DR2R;                              /*!< GPIO 2-mA Drive Select                                                */\n  __IO uint32_t  DR4R;                              /*!< GPIO 4-mA Drive Select                                                */\n  __IO uint32_t  DR8R;                              /*!< GPIO 8-mA Drive Select                                                */\n  __IO uint32_t  ODR;                               /*!< GPIO Open Drain Select                                                */\n  __IO uint32_t  PUR;                               /*!< GPIO Pull-Up Select                                                   */\n  __IO uint32_t  PDR;                               /*!< GPIO Pull-Down Select                                                 */\n  __IO uint32_t  SLR;                               /*!< GPIO Slew Rate Control Select                                         */\n  __IO uint32_t  DEN;                               /*!< GPIO Digital Enable                                                   */\n  __IO uint32_t  LOCK;                              /*!< GPIO Lock                                                             */\n  __I  uint32_t  CR;                                /*!< GPIO Commit                                                           */\n  __IO uint32_t  AMSEL;                             /*!< GPIO Analog Mode Select                                               */\n  __IO uint32_t  PCTL;                              /*!< GPIO Port Control                                                     */\n  __IO uint32_t  ADCCTL;                            /*!< GPIO ADC Control                                                      */\n  __IO uint32_t  DMACTL;                            /*!< GPIO DMA Control                                                      */\n} GPIOA_Type;\n\n\n/* ================================================================================ */\n/* ================                      SSI0                      ================ */\n/* ================================================================================ */\n\n\n/**\n  * @brief Register map for SSI0 peripheral (SSI0)\n  */\n\ntypedef struct {                                    /*!< SSI0 Structure                                                        */\n  __IO uint32_t  CR0;                               /*!< SSI Control 0                                                         */\n  __IO uint32_t  CR1;                               /*!< SSI Control 1                                                         */\n  __IO uint32_t  DR;                                /*!< SSI Data                                                              */\n  __IO uint32_t  SR;                                /*!< SSI Status                                                            */\n  __IO uint32_t  CPSR;                              /*!< SSI Clock Prescale                                                    */\n  __IO uint32_t  IM;                                /*!< SSI Interrupt Mask                                                    */\n  __IO uint32_t  RIS;                               /*!< SSI Raw Interrupt Status                                              */\n  __IO uint32_t  MIS;                               /*!< SSI Masked Interrupt Status                                           */\n  __O  uint32_t  ICR;                               /*!< SSI Interrupt Clear                                                   */\n  __IO uint32_t  DMACTL;                            /*!< SSI DMA Control                                                       */\n  __I  uint32_t  RESERVED0[1000];\n  __IO uint32_t  CC;                                /*!< SSI Clock Configuration                                               */\n} SSI0_Type;\n\n\n/* ================================================================================ */\n/* ================                      UART0                     ================ */\n/* ================================================================================ */\n\n\n/**\n  * @brief Register map for UART0 peripheral (UART0)\n  */\n\ntypedef struct {                                    /*!< UART0 Structure                                                       */\n  __IO uint32_t  DR;                                /*!< UART Data                                                             */\n\n  union {\n    __IO uint32_t  ECR_UART_ALT;                    /*!< UART Receive Status/Error Clear                                       */\n    __IO uint32_t  RSR;                             /*!< UART Receive Status/Error Clear                                       */\n  };\n  __I  uint32_t  RESERVED0[4];\n  __IO uint32_t  FR;                                /*!< UART Flag                                                             */\n  __I  uint32_t  RESERVED1;\n  __IO uint32_t  ILPR;                              /*!< UART IrDA Low-Power Register                                          */\n  __IO uint32_t  IBRD;                              /*!< UART Integer Baud-Rate Divisor                                        */\n  __IO uint32_t  FBRD;                              /*!< UART Fractional Baud-Rate Divisor                                     */\n  __IO uint32_t  LCRH;                              /*!< UART Line Control                                                     */\n  __IO uint32_t  CTL;                               /*!< UART Control                                                          */\n  __IO uint32_t  IFLS;                              /*!< UART Interrupt FIFO Level Select                                      */\n  __IO uint32_t  IM;                                /*!< UART Interrupt Mask                                                   */\n  __IO uint32_t  RIS;                               /*!< UART Raw Interrupt Status                                             */\n  __IO uint32_t  MIS;                               /*!< UART Masked Interrupt Status                                          */\n  __O  uint32_t  ICR;                               /*!< UART Interrupt Clear                                                  */\n  __IO uint32_t  DMACTL;                            /*!< UART DMA Control                                                      */\n  __I  uint32_t  RESERVED2[22];\n  __IO uint32_t  _9BITADDR;                         /*!< UART 9-Bit Self Address                                               */\n  __IO uint32_t  _9BITAMASK;                        /*!< UART 9-Bit Self Address Mask                                          */\n  __I  uint32_t  RESERVED3[965];\n  __IO uint32_t  PP;                                /*!< UART Peripheral Properties                                            */\n  __I  uint32_t  RESERVED4;\n  __IO uint32_t  CC;                                /*!< UART Clock Configuration                                              */\n} UART0_Type;\n\n\n/* ================================================================================ */\n/* ================                      I2C0                      ================ */\n/* ================================================================================ */\n\n\n/**\n  * @brief Register map for I2C0 peripheral (I2C0)\n  */\n\ntypedef struct {                                    /*!< I2C0 Structure                                                        */\n  __IO uint32_t  MSA;                               /*!< I2C Master Slave Address                                              */\n\n  union {\n    __IO uint32_t  MCS_I2C0_ALT;                    /*!< I2C Master Control/Status                                             */\n    __IO uint32_t  MCS;                             /*!< I2C Master Control/Status                                             */\n  };\n  __IO uint32_t  MDR;                               /*!< I2C Master Data                                                       */\n  __IO uint32_t  MTPR;                              /*!< I2C Master Timer Period                                               */\n  __IO uint32_t  MIMR;                              /*!< I2C Master Interrupt Mask                                             */\n  __IO uint32_t  MRIS;                              /*!< I2C Master Raw Interrupt Status                                       */\n  __IO uint32_t  MMIS;                              /*!< I2C Master Masked Interrupt Status                                    */\n  __O  uint32_t  MICR;                              /*!< I2C Master Interrupt Clear                                            */\n  __IO uint32_t  MCR;                               /*!< I2C Master Configuration                                              */\n  __IO uint32_t  MCLKOCNT;                          /*!< I2C Master Clock Low Timeout Count                                    */\n  __I  uint32_t  RESERVED0;\n  __IO uint32_t  MBMON;                             /*!< I2C Master Bus Monitor                                                */\n  __I  uint32_t  RESERVED1[2];\n  __IO uint32_t  MCR2;                              /*!< I2C Master Configuration 2                                            */\n  __I  uint32_t  RESERVED2[497];\n  __IO uint32_t  SOAR;                              /*!< I2C Slave Own Address                                                 */\n\n  union {\n    __IO uint32_t  SCSR_I2C0_ALT;                   /*!< I2C Slave Control/Status                                              */\n    __IO uint32_t  SCSR;                            /*!< I2C Slave Control/Status                                              */\n  };\n  __IO uint32_t  SDR;                               /*!< I2C Slave Data                                                        */\n  __IO uint32_t  SIMR;                              /*!< I2C Slave Interrupt Mask                                              */\n  __IO uint32_t  SRIS;                              /*!< I2C Slave Raw Interrupt Status                                        */\n  __IO uint32_t  SMIS;                              /*!< I2C Slave Masked Interrupt Status                                     */\n  __O  uint32_t  SICR;                              /*!< I2C Slave Interrupt Clear                                             */\n  __IO uint32_t  SOAR2;                             /*!< I2C Slave Own Address 2                                               */\n  __IO uint32_t  SACKCTL;                           /*!< I2C Slave ACK Control                                                 */\n  __I  uint32_t  RESERVED3[487];\n  __IO uint32_t  PP;                                /*!< I2C Peripheral Properties                                             */\n  __IO uint32_t  PC;                                /*!< I2C Peripheral Configuration                                          */\n} I2C0_Type;\n\n\n/* ================================================================================ */\n/* ================                      PWM0                      ================ */\n/* ================================================================================ */\n\n\n/**\n  * @brief Register map for PWM0 peripheral (PWM0)\n  */\n\ntypedef struct {                                    /*!< PWM0 Structure                                                        */\n  __IO uint32_t  CTL;                               /*!< PWM Master Control                                                    */\n  __IO uint32_t  SYNC;                              /*!< PWM Time Base Sync                                                    */\n  __IO uint32_t  ENABLE;                            /*!< PWM Output Enable                                                     */\n  __IO uint32_t  INVERT;                            /*!< PWM Output Inversion                                                  */\n  __IO uint32_t  FAULT;                             /*!< PWM Output Fault                                                      */\n  __IO uint32_t  INTEN;                             /*!< PWM Interrupt Enable                                                  */\n  __IO uint32_t  RIS;                               /*!< PWM Raw Interrupt Status                                              */\n  __IO uint32_t  ISC;                               /*!< PWM Interrupt Status and Clear                                        */\n  __IO uint32_t  STATUS;                            /*!< PWM Status                                                            */\n  __IO uint32_t  FAULTVAL;                          /*!< PWM Fault Condition Value                                             */\n  __IO uint32_t  ENUPD;                             /*!< PWM Enable Update                                                     */\n  __I  uint32_t  RESERVED0[5];\n  __IO uint32_t  _0_CTL;                            /*!< PWM0 Control                                                          */\n  __IO uint32_t  _0_INTEN;                          /*!< PWM0 Interrupt and Trigger Enable                                     */\n  __IO uint32_t  _0_RIS;                            /*!< PWM0 Raw Interrupt Status                                             */\n  __IO uint32_t  _0_ISC;                            /*!< PWM0 Interrupt Status and Clear                                       */\n  __IO uint32_t  _0_LOAD;                           /*!< PWM0 Load                                                             */\n  __IO uint32_t  _0_COUNT;                          /*!< PWM0 Counter                                                          */\n  __IO uint32_t  _0_CMPA;                           /*!< PWM0 Compare A                                                        */\n  __IO uint32_t  _0_CMPB;                           /*!< PWM0 Compare B                                                        */\n  __IO uint32_t  _0_GENA;                           /*!< PWM0 Generator A Control                                              */\n  __IO uint32_t  _0_GENB;                           /*!< PWM0 Generator B Control                                              */\n  __IO uint32_t  _0_DBCTL;                          /*!< PWM0 Dead-Band Control                                                */\n  __IO uint32_t  _0_DBRISE;                         /*!< PWM0 Dead-Band Rising-Edge Delay                                      */\n  __IO uint32_t  _0_DBFALL;                         /*!< PWM0 Dead-Band Falling-Edge-Delay                                     */\n  __IO uint32_t  _0_FLTSRC0;                        /*!< PWM0 Fault Source 0                                                   */\n  __IO uint32_t  _0_FLTSRC1;                        /*!< PWM0 Fault Source 1                                                   */\n  __IO uint32_t  _0_MINFLTPER;                      /*!< PWM0 Minimum Fault Period                                             */\n  __IO uint32_t  _1_CTL;                            /*!< PWM1 Control                                                          */\n  __IO uint32_t  _1_INTEN;                          /*!< PWM1 Interrupt and Trigger Enable                                     */\n  __IO uint32_t  _1_RIS;                            /*!< PWM1 Raw Interrupt Status                                             */\n  __IO uint32_t  _1_ISC;                            /*!< PWM1 Interrupt Status and Clear                                       */\n  __IO uint32_t  _1_LOAD;                           /*!< PWM1 Load                                                             */\n  __IO uint32_t  _1_COUNT;                          /*!< PWM1 Counter                                                          */\n  __IO uint32_t  _1_CMPA;                           /*!< PWM1 Compare A                                                        */\n  __IO uint32_t  _1_CMPB;                           /*!< PWM1 Compare B                                                        */\n  __IO uint32_t  _1_GENA;                           /*!< PWM1 Generator A Control                                              */\n  __IO uint32_t  _1_GENB;                           /*!< PWM1 Generator B Control                                              */\n  __IO uint32_t  _1_DBCTL;                          /*!< PWM1 Dead-Band Control                                                */\n  __IO uint32_t  _1_DBRISE;                         /*!< PWM1 Dead-Band Rising-Edge Delay                                      */\n  __IO uint32_t  _1_DBFALL;                         /*!< PWM1 Dead-Band Falling-Edge-Delay                                     */\n  __IO uint32_t  _1_FLTSRC0;                        /*!< PWM1 Fault Source 0                                                   */\n  __IO uint32_t  _1_FLTSRC1;                        /*!< PWM1 Fault Source 1                                                   */\n  __IO uint32_t  _1_MINFLTPER;                      /*!< PWM1 Minimum Fault Period                                             */\n  __IO uint32_t  _2_CTL;                            /*!< PWM2 Control                                                          */\n  __IO uint32_t  _2_INTEN;                          /*!< PWM2 Interrupt and Trigger Enable                                     */\n  __IO uint32_t  _2_RIS;                            /*!< PWM2 Raw Interrupt Status                                             */\n  __IO uint32_t  _2_ISC;                            /*!< PWM2 Interrupt Status and Clear                                       */\n  __IO uint32_t  _2_LOAD;                           /*!< PWM2 Load                                                             */\n  __IO uint32_t  _2_COUNT;                          /*!< PWM2 Counter                                                          */\n  __IO uint32_t  _2_CMPA;                           /*!< PWM2 Compare A                                                        */\n  __IO uint32_t  _2_CMPB;                           /*!< PWM2 Compare B                                                        */\n  __IO uint32_t  _2_GENA;                           /*!< PWM2 Generator A Control                                              */\n  __IO uint32_t  _2_GENB;                           /*!< PWM2 Generator B Control                                              */\n  __IO uint32_t  _2_DBCTL;                          /*!< PWM2 Dead-Band Control                                                */\n  __IO uint32_t  _2_DBRISE;                         /*!< PWM2 Dead-Band Rising-Edge Delay                                      */\n  __IO uint32_t  _2_DBFALL;                         /*!< PWM2 Dead-Band Falling-Edge-Delay                                     */\n  __IO uint32_t  _2_FLTSRC0;                        /*!< PWM2 Fault Source 0                                                   */\n  __IO uint32_t  _2_FLTSRC1;                        /*!< PWM2 Fault Source 1                                                   */\n  __IO uint32_t  _2_MINFLTPER;                      /*!< PWM2 Minimum Fault Period                                             */\n  __IO uint32_t  _3_CTL;                            /*!< PWM3 Control                                                          */\n  __IO uint32_t  _3_INTEN;                          /*!< PWM3 Interrupt and Trigger Enable                                     */\n  __IO uint32_t  _3_RIS;                            /*!< PWM3 Raw Interrupt Status                                             */\n  __IO uint32_t  _3_ISC;                            /*!< PWM3 Interrupt Status and Clear                                       */\n  __IO uint32_t  _3_LOAD;                           /*!< PWM3 Load                                                             */\n  __IO uint32_t  _3_COUNT;                          /*!< PWM3 Counter                                                          */\n  __IO uint32_t  _3_CMPA;                           /*!< PWM3 Compare A                                                        */\n  __IO uint32_t  _3_CMPB;                           /*!< PWM3 Compare B                                                        */\n  __IO uint32_t  _3_GENA;                           /*!< PWM3 Generator A Control                                              */\n  __IO uint32_t  _3_GENB;                           /*!< PWM3 Generator B Control                                              */\n  __IO uint32_t  _3_DBCTL;                          /*!< PWM3 Dead-Band Control                                                */\n  __IO uint32_t  _3_DBRISE;                         /*!< PWM3 Dead-Band Rising-Edge Delay                                      */\n  __IO uint32_t  _3_DBFALL;                         /*!< PWM3 Dead-Band Falling-Edge-Delay                                     */\n  __IO uint32_t  _3_FLTSRC0;                        /*!< PWM3 Fault Source 0                                                   */\n  __IO uint32_t  _3_FLTSRC1;                        /*!< PWM3 Fault Source 1                                                   */\n  __IO uint32_t  _3_MINFLTPER;                      /*!< PWM3 Minimum Fault Period                                             */\n  __I  uint32_t  RESERVED1[432];\n  __IO uint32_t  _0_FLTSEN;                         /*!< PWM0 Fault Pin Logic Sense                                            */\n  __I  uint32_t  _0_FLTSTAT0;                       /*!< PWM0 Fault Status 0                                                   */\n  __I  uint32_t  _0_FLTSTAT1;                       /*!< PWM0 Fault Status 1                                                   */\n  __I  uint32_t  RESERVED2[29];\n  __IO uint32_t  _1_FLTSEN;                         /*!< PWM1 Fault Pin Logic Sense                                            */\n  __I  uint32_t  _1_FLTSTAT0;                       /*!< PWM1 Fault Status 0                                                   */\n  __I  uint32_t  _1_FLTSTAT1;                       /*!< PWM1 Fault Status 1                                                   */\n  __I  uint32_t  RESERVED3[30];\n  __I  uint32_t  _2_FLTSTAT0;                       /*!< PWM2 Fault Status 0                                                   */\n  __I  uint32_t  _2_FLTSTAT1;                       /*!< PWM2 Fault Status 1                                                   */\n  __I  uint32_t  RESERVED4[30];\n  __I  uint32_t  _3_FLTSTAT0;                       /*!< PWM3 Fault Status 0                                                   */\n  __I  uint32_t  _3_FLTSTAT1;                       /*!< PWM3 Fault Status 1                                                   */\n  __I  uint32_t  RESERVED5[397];\n  __IO uint32_t  PP;                                /*!< PWM Peripheral Properties                                             */\n} PWM0_Type;\n\n\n/* ================================================================================ */\n/* ================                      QEI0                      ================ */\n/* ================================================================================ */\n\n\n/**\n  * @brief Register map for QEI0 peripheral (QEI0)\n  */\n\ntypedef struct {                                    /*!< QEI0 Structure                                                        */\n  __IO uint32_t  CTL;                               /*!< QEI Control                                                           */\n  __IO uint32_t  STAT;                              /*!< QEI Status                                                            */\n  __IO uint32_t  POS;                               /*!< QEI Position                                                          */\n  __IO uint32_t  MAXPOS;                            /*!< QEI Maximum Position                                                  */\n  __IO uint32_t  LOAD;                              /*!< QEI Timer Load                                                        */\n  __IO uint32_t  TIME;                              /*!< QEI Timer                                                             */\n  __IO uint32_t  COUNT;                             /*!< QEI Velocity Counter                                                  */\n  __IO uint32_t  SPEED;                             /*!< QEI Velocity                                                          */\n  __IO uint32_t  INTEN;                             /*!< QEI Interrupt Enable                                                  */\n  __IO uint32_t  RIS;                               /*!< QEI Raw Interrupt Status                                              */\n  __IO uint32_t  ISC;                               /*!< QEI Interrupt Status and Clear                                        */\n} QEI0_Type;\n\n\n/* ================================================================================ */\n/* ================                     TIMER0                     ================ */\n/* ================================================================================ */\n\n\n/**\n  * @brief Register map for TIMER0 peripheral (TIMER0)\n  */\n\ntypedef struct {                                    /*!< TIMER0 Structure                                                      */\n  __IO uint32_t  CFG;                               /*!< GPTM Configuration                                                    */\n  __IO uint32_t  TAMR;                              /*!< GPTM Timer A Mode                                                     */\n  __IO uint32_t  TBMR;                              /*!< GPTM Timer B Mode                                                     */\n  __IO uint32_t  CTL;                               /*!< GPTM Control                                                          */\n  __IO uint32_t  SYNC;                              /*!< GPTM Synchronize                                                      */\n  __I  uint32_t  RESERVED0;\n  __IO uint32_t  IMR;                               /*!< GPTM Interrupt Mask                                                   */\n  __IO uint32_t  RIS;                               /*!< GPTM Raw Interrupt Status                                             */\n  __IO uint32_t  MIS;                               /*!< GPTM Masked Interrupt Status                                          */\n  __O  uint32_t  ICR;                               /*!< GPTM Interrupt Clear                                                  */\n  __IO uint32_t  TAILR;                             /*!< GPTM Timer A Interval Load                                            */\n  __IO uint32_t  TBILR;                             /*!< GPTM Timer B Interval Load                                            */\n  __IO uint32_t  TAMATCHR;                          /*!< GPTM Timer A Match                                                    */\n  __IO uint32_t  TBMATCHR;                          /*!< GPTM Timer B Match                                                    */\n  __IO uint32_t  TAPR;                              /*!< GPTM Timer A Prescale                                                 */\n  __IO uint32_t  TBPR;                              /*!< GPTM Timer B Prescale                                                 */\n  __IO uint32_t  TAPMR;                             /*!< GPTM TimerA Prescale Match                                            */\n  __IO uint32_t  TBPMR;                             /*!< GPTM TimerB Prescale Match                                            */\n  __IO uint32_t  TAR;                               /*!< GPTM Timer A                                                          */\n  __IO uint32_t  TBR;                               /*!< GPTM Timer B                                                          */\n  __IO uint32_t  TAV;                               /*!< GPTM Timer A Value                                                    */\n  __IO uint32_t  TBV;                               /*!< GPTM Timer B Value                                                    */\n  __IO uint32_t  RTCPD;                             /*!< GPTM RTC Predivide                                                    */\n  __IO uint32_t  TAPS;                              /*!< GPTM Timer A Prescale Snapshot                                        */\n  __IO uint32_t  TBPS;                              /*!< GPTM Timer B Prescale Snapshot                                        */\n  __IO uint32_t  TAPV;                              /*!< GPTM Timer A Prescale Value                                           */\n  __IO uint32_t  TBPV;                              /*!< GPTM Timer B Prescale Value                                           */\n  __I  uint32_t  RESERVED1[981];\n  __IO uint32_t  PP;                                /*!< GPTM Peripheral Properties                                            */\n} TIMER0_Type;\n\n\n/* ================================================================================ */\n/* ================                     WTIMER0                    ================ */\n/* ================================================================================ */\n\n\n/**\n  * @brief Register map for WTIMER0 peripheral (WTIMER0)\n  */\n\ntypedef struct {                                    /*!< WTIMER0 Structure                                                     */\n  __IO uint32_t  CFG;                               /*!< GPTM Configuration                                                    */\n  __IO uint32_t  TAMR;                              /*!< GPTM Timer A Mode                                                     */\n  __IO uint32_t  TBMR;                              /*!< GPTM Timer B Mode                                                     */\n  __IO uint32_t  CTL;                               /*!< GPTM Control                                                          */\n  __IO uint32_t  SYNC;                              /*!< GPTM Synchronize                                                      */\n  __I  uint32_t  RESERVED0;\n  __IO uint32_t  IMR;                               /*!< GPTM Interrupt Mask                                                   */\n  __IO uint32_t  RIS;                               /*!< GPTM Raw Interrupt Status                                             */\n  __IO uint32_t  MIS;                               /*!< GPTM Masked Interrupt Status                                          */\n  __O  uint32_t  ICR;                               /*!< GPTM Interrupt Clear                                                  */\n  __IO uint32_t  TAILR;                             /*!< GPTM Timer A Interval Load                                            */\n  __IO uint32_t  TBILR;                             /*!< GPTM Timer B Interval Load                                            */\n  __IO uint32_t  TAMATCHR;                          /*!< GPTM Timer A Match                                                    */\n  __IO uint32_t  TBMATCHR;                          /*!< GPTM Timer B Match                                                    */\n  __IO uint32_t  TAPR;                              /*!< GPTM Timer A Prescale                                                 */\n  __IO uint32_t  TBPR;                              /*!< GPTM Timer B Prescale                                                 */\n  __IO uint32_t  TAPMR;                             /*!< GPTM TimerA Prescale Match                                            */\n  __IO uint32_t  TBPMR;                             /*!< GPTM TimerB Prescale Match                                            */\n  __IO uint32_t  TAR;                               /*!< GPTM Timer A                                                          */\n  __IO uint32_t  TBR;                               /*!< GPTM Timer B                                                          */\n  __IO uint32_t  TAV;                               /*!< GPTM Timer A Value                                                    */\n  __IO uint32_t  TBV;                               /*!< GPTM Timer B Value                                                    */\n  __IO uint32_t  RTCPD;                             /*!< GPTM RTC Predivide                                                    */\n  __IO uint32_t  TAPS;                              /*!< GPTM Timer A Prescale Snapshot                                        */\n  __IO uint32_t  TBPS;                              /*!< GPTM Timer B Prescale Snapshot                                        */\n  __IO uint32_t  TAPV;                              /*!< GPTM Timer A Prescale Value                                           */\n  __IO uint32_t  TBPV;                              /*!< GPTM Timer B Prescale Value                                           */\n  __I  uint32_t  RESERVED1[981];\n  __IO uint32_t  PP;                                /*!< GPTM Peripheral Properties                                            */\n} WTIMER0_Type;\n\n\n/* ================================================================================ */\n/* ================                      ADC0                      ================ */\n/* ================================================================================ */\n\n\n/**\n  * @brief Register map for ADC0 peripheral (ADC0)\n  */\n\ntypedef struct {                                    /*!< ADC0 Structure                                                        */\n  __IO uint32_t  ACTSS;                             /*!< ADC Active Sample Sequencer                                           */\n  __IO uint32_t  RIS;                               /*!< ADC Raw Interrupt Status                                              */\n  __IO uint32_t  IM;                                /*!< ADC Interrupt Mask                                                    */\n  __IO uint32_t  ISC;                               /*!< ADC Interrupt Status and Clear                                        */\n  __IO uint32_t  OSTAT;                             /*!< ADC Overflow Status                                                   */\n  __IO uint32_t  EMUX;                              /*!< ADC Event Multiplexer Select                                          */\n  __IO uint32_t  USTAT;                             /*!< ADC Underflow Status                                                  */\n  __IO uint32_t  TSSEL;                             /*!< ADC Trigger Source Select                                             */\n  __IO uint32_t  SSPRI;                             /*!< ADC Sample Sequencer Priority                                         */\n  __IO uint32_t  SPC;                               /*!< ADC Sample Phase Control                                              */\n  __IO uint32_t  PSSI;                              /*!< ADC Processor Sample Sequence Initiate                                */\n  __I  uint32_t  RESERVED0;\n  __IO uint32_t  SAC;                               /*!< ADC Sample Averaging Control                                          */\n  __IO uint32_t  DCISC;                             /*!< ADC Digital Comparator Interrupt Status and Clear                     */\n  __IO uint32_t  CTL;                               /*!< ADC Control                                                           */\n  __I  uint32_t  RESERVED1;\n  __IO uint32_t  SSMUX0;                            /*!< ADC Sample Sequence Input Multiplexer Select 0                        */\n  __IO uint32_t  SSCTL0;                            /*!< ADC Sample Sequence Control 0                                         */\n  __IO uint32_t  SSFIFO0;                           /*!< ADC Sample Sequence Result FIFO 0                                     */\n  __IO uint32_t  SSFSTAT0;                          /*!< ADC Sample Sequence FIFO 0 Status                                     */\n  __IO uint32_t  SSOP0;                             /*!< ADC Sample Sequence 0 Operation                                       */\n  __IO uint32_t  SSDC0;                             /*!< ADC Sample Sequence 0 Digital Comparator Select                       */\n  __I  uint32_t  RESERVED2[2];\n  __IO uint32_t  SSMUX1;                            /*!< ADC Sample Sequence Input Multiplexer Select 1                        */\n  __IO uint32_t  SSCTL1;                            /*!< ADC Sample Sequence Control 1                                         */\n  __IO uint32_t  SSFIFO1;                           /*!< ADC Sample Sequence Result FIFO 1                                     */\n  __IO uint32_t  SSFSTAT1;                          /*!< ADC Sample Sequence FIFO 1 Status                                     */\n  __IO uint32_t  SSOP1;                             /*!< ADC Sample Sequence 1 Operation                                       */\n  __IO uint32_t  SSDC1;                             /*!< ADC Sample Sequence 1 Digital Comparator Select                       */\n  __I  uint32_t  RESERVED3[2];\n  __IO uint32_t  SSMUX2;                            /*!< ADC Sample Sequence Input Multiplexer Select 2                        */\n  __IO uint32_t  SSCTL2;                            /*!< ADC Sample Sequence Control 2                                         */\n  __IO uint32_t  SSFIFO2;                           /*!< ADC Sample Sequence Result FIFO 2                                     */\n  __IO uint32_t  SSFSTAT2;                          /*!< ADC Sample Sequence FIFO 2 Status                                     */\n  __IO uint32_t  SSOP2;                             /*!< ADC Sample Sequence 2 Operation                                       */\n  __IO uint32_t  SSDC2;                             /*!< ADC Sample Sequence 2 Digital Comparator Select                       */\n  __I  uint32_t  RESERVED4[2];\n  __IO uint32_t  SSMUX3;                            /*!< ADC Sample Sequence Input Multiplexer Select 3                        */\n  __IO uint32_t  SSCTL3;                            /*!< ADC Sample Sequence Control 3                                         */\n  __IO uint32_t  SSFIFO3;                           /*!< ADC Sample Sequence Result FIFO 3                                     */\n  __IO uint32_t  SSFSTAT3;                          /*!< ADC Sample Sequence FIFO 3 Status                                     */\n  __IO uint32_t  SSOP3;                             /*!< ADC Sample Sequence 3 Operation                                       */\n  __IO uint32_t  SSDC3;                             /*!< ADC Sample Sequence 3 Digital Comparator Select                       */\n  __I  uint32_t  RESERVED5[786];\n  __O  uint32_t  DCRIC;                             /*!< ADC Digital Comparator Reset Initial Conditions                       */\n  __I  uint32_t  RESERVED6[63];\n  __IO uint32_t  DCCTL0;                            /*!< ADC Digital Comparator Control 0                                      */\n  __IO uint32_t  DCCTL1;                            /*!< ADC Digital Comparator Control 1                                      */\n  __IO uint32_t  DCCTL2;                            /*!< ADC Digital Comparator Control 2                                      */\n  __IO uint32_t  DCCTL3;                            /*!< ADC Digital Comparator Control 3                                      */\n  __IO uint32_t  DCCTL4;                            /*!< ADC Digital Comparator Control 4                                      */\n  __IO uint32_t  DCCTL5;                            /*!< ADC Digital Comparator Control 5                                      */\n  __IO uint32_t  DCCTL6;                            /*!< ADC Digital Comparator Control 6                                      */\n  __IO uint32_t  DCCTL7;                            /*!< ADC Digital Comparator Control 7                                      */\n  __I  uint32_t  RESERVED7[8];\n  __IO uint32_t  DCCMP0;                            /*!< ADC Digital Comparator Range 0                                        */\n  __IO uint32_t  DCCMP1;                            /*!< ADC Digital Comparator Range 1                                        */\n  __IO uint32_t  DCCMP2;                            /*!< ADC Digital Comparator Range 2                                        */\n  __IO uint32_t  DCCMP3;                            /*!< ADC Digital Comparator Range 3                                        */\n  __IO uint32_t  DCCMP4;                            /*!< ADC Digital Comparator Range 4                                        */\n  __IO uint32_t  DCCMP5;                            /*!< ADC Digital Comparator Range 5                                        */\n  __IO uint32_t  DCCMP6;                            /*!< ADC Digital Comparator Range 6                                        */\n  __IO uint32_t  DCCMP7;                            /*!< ADC Digital Comparator Range 7                                        */\n  __I  uint32_t  RESERVED8[88];\n  __IO uint32_t  PP;                                /*!< ADC Peripheral Properties                                             */\n  __IO uint32_t  PC;                                /*!< ADC Peripheral Configuration                                          */\n  __IO uint32_t  CC;                                /*!< ADC Clock Configuration                                               */\n} ADC0_Type;\n\n\n/* ================================================================================ */\n/* ================                      COMP                      ================ */\n/* ================================================================================ */\n\n\n/**\n  * @brief Register map for COMP peripheral (COMP)\n  */\n\ntypedef struct {                                    /*!< COMP Structure                                                        */\n  __IO uint32_t  ACMIS;                             /*!< Analog Comparator Masked Interrupt Status                             */\n  __IO uint32_t  ACRIS;                             /*!< Analog Comparator Raw Interrupt Status                                */\n  __IO uint32_t  ACINTEN;                           /*!< Analog Comparator Interrupt Enable                                    */\n  __I  uint32_t  RESERVED0;\n  __IO uint32_t  ACREFCTL;                          /*!< Analog Comparator Reference Voltage Control                           */\n  __I  uint32_t  RESERVED1[3];\n  __IO uint32_t  ACSTAT0;                           /*!< Analog Comparator Status 0                                            */\n  __IO uint32_t  ACCTL0;                            /*!< Analog Comparator Control 0                                           */\n  __I  uint32_t  RESERVED2[6];\n  __IO uint32_t  ACSTAT1;                           /*!< Analog Comparator Status 1                                            */\n  __IO uint32_t  ACCTL1;                            /*!< Analog Comparator Control 1                                           */\n  __I  uint32_t  RESERVED3[990];\n  __IO uint32_t  PP;                                /*!< Analog Comparator Peripheral Properties                               */\n} COMP_Type;\n\n\n/* ================================================================================ */\n/* ================                      CAN0                      ================ */\n/* ================================================================================ */\n\n\n/**\n  * @brief Register map for CAN0 peripheral (CAN0)\n  */\n\ntypedef struct {                                    /*!< CAN0 Structure                                                        */\n  __IO uint32_t  CTL;                               /*!< CAN Control                                                           */\n  __IO uint32_t  STS;                               /*!< CAN Status                                                            */\n  __IO uint32_t  ERR;                               /*!< CAN Error Counter                                                     */\n  __IO uint32_t  BIT;                               /*!< CAN Bit Timing                                                        */\n  __IO uint32_t  INT;                               /*!< CAN Interrupt                                                         */\n  __IO uint32_t  TST;                               /*!< CAN Test                                                              */\n  __IO uint32_t  BRPE;                              /*!< CAN Baud Rate Prescaler Extension                                     */\n  __I  uint32_t  RESERVED0;\n  __IO uint32_t  IF1CRQ;                            /*!< CAN IF1 Command Request                                               */\n\n  union {\n    __IO uint32_t  IF1CMSK_CAN0_ALT;                /*!< CAN IF1 Command Mask                                                  */\n    __IO uint32_t  IF1CMSK;                         /*!< CAN IF1 Command Mask                                                  */\n  };\n  __IO uint32_t  IF1MSK1;                           /*!< CAN IF1 Mask 1                                                        */\n  __IO uint32_t  IF1MSK2;                           /*!< CAN IF1 Mask 2                                                        */\n  __IO uint32_t  IF1ARB1;                           /*!< CAN IF1 Arbitration 1                                                 */\n  __IO uint32_t  IF1ARB2;                           /*!< CAN IF1 Arbitration 2                                                 */\n  __IO uint32_t  IF1MCTL;                           /*!< CAN IF1 Message Control                                               */\n  __IO uint32_t  IF1DA1;                            /*!< CAN IF1 Data A1                                                       */\n  __IO uint32_t  IF1DA2;                            /*!< CAN IF1 Data A2                                                       */\n  __IO uint32_t  IF1DB1;                            /*!< CAN IF1 Data B1                                                       */\n  __IO uint32_t  IF1DB2;                            /*!< CAN IF1 Data B2                                                       */\n  __I  uint32_t  RESERVED1[13];\n  __IO uint32_t  IF2CRQ;                            /*!< CAN IF2 Command Request                                               */\n\n  union {\n    __IO uint32_t  IF2CMSK_CAN0_ALT;                /*!< CAN IF2 Command Mask                                                  */\n    __IO uint32_t  IF2CMSK;                         /*!< CAN IF2 Command Mask                                                  */\n  };\n  __IO uint32_t  IF2MSK1;                           /*!< CAN IF2 Mask 1                                                        */\n  __IO uint32_t  IF2MSK2;                           /*!< CAN IF2 Mask 2                                                        */\n  __IO uint32_t  IF2ARB1;                           /*!< CAN IF2 Arbitration 1                                                 */\n  __IO uint32_t  IF2ARB2;                           /*!< CAN IF2 Arbitration 2                                                 */\n  __IO uint32_t  IF2MCTL;                           /*!< CAN IF2 Message Control                                               */\n  __IO uint32_t  IF2DA1;                            /*!< CAN IF2 Data A1                                                       */\n  __IO uint32_t  IF2DA2;                            /*!< CAN IF2 Data A2                                                       */\n  __IO uint32_t  IF2DB1;                            /*!< CAN IF2 Data B1                                                       */\n  __IO uint32_t  IF2DB2;                            /*!< CAN IF2 Data B2                                                       */\n  __I  uint32_t  RESERVED2[21];\n  __IO uint32_t  TXRQ1;                             /*!< CAN Transmission Request 1                                            */\n  __IO uint32_t  TXRQ2;                             /*!< CAN Transmission Request 2                                            */\n  __I  uint32_t  RESERVED3[6];\n  __IO uint32_t  NWDA1;                             /*!< CAN New Data 1                                                        */\n  __IO uint32_t  NWDA2;                             /*!< CAN New Data 2                                                        */\n  __I  uint32_t  RESERVED4[6];\n  __IO uint32_t  MSG1INT;                           /*!< CAN Message 1 Interrupt Pending                                       */\n  __IO uint32_t  MSG2INT;                           /*!< CAN Message 2 Interrupt Pending                                       */\n  __I  uint32_t  RESERVED5[6];\n  __IO uint32_t  MSG1VAL;                           /*!< CAN Message 1 Valid                                                   */\n  __IO uint32_t  MSG2VAL;                           /*!< CAN Message 2 Valid                                                   */\n} CAN0_Type;\n\n\n/* ================================================================================ */\n/* ================                      USB0                      ================ */\n/* ================================================================================ */\n\n\n/**\n  * @brief Register map for USB0 peripheral (USB0)\n  */\n\ntypedef struct {                                    /*!< USB0 Structure                                                        */\n  __IO uint8_t   FADDR;                             /*!< USB Device Functional Address                                         */\n  __IO uint8_t   POWER;                             /*!< USB Power                                                             */\n  __IO uint16_t  TXIS;                              /*!< USB Transmit Interrupt Status                                         */\n  __IO uint16_t  RXIS;                              /*!< USB Receive Interrupt Status                                          */\n  __IO uint16_t  TXIE;                              /*!< USB Transmit Interrupt Enable                                         */\n  __IO uint16_t  RXIE;                              /*!< USB Receive Interrupt Enable                                          */\n\n  union {\n    __IO uint8_t   IS_USB0_ALT;                     /*!< USB General Interrupt Status                                          */\n    __IO uint8_t   IS;                              /*!< USB General Interrupt Status                                          */\n  };\n\n  union {\n    __IO uint8_t   IE_USB0_ALT;                     /*!< USB Interrupt Enable                                                  */\n    __IO uint8_t   IE;                              /*!< USB Interrupt Enable                                                  */\n  };\n  __IO uint16_t  FRAME;                             /*!< USB Frame Value                                                       */\n  __IO uint8_t   EPIDX;                             /*!< USB Endpoint Index                                                    */\n  __IO uint8_t   TEST;                              /*!< USB Test Mode                                                         */\n  __I  uint32_t  RESERVED0[4];\n  __IO uint32_t  FIFO0;                             /*!< USB FIFO Endpoint 0                                                   */\n  __IO uint32_t  FIFO1;                             /*!< USB FIFO Endpoint 1                                                   */\n  __IO uint32_t  FIFO2;                             /*!< USB FIFO Endpoint 2                                                   */\n  __IO uint32_t  FIFO3;                             /*!< USB FIFO Endpoint 3                                                   */\n  __IO uint32_t  FIFO4;                             /*!< USB FIFO Endpoint 4                                                   */\n  __IO uint32_t  FIFO5;                             /*!< USB FIFO Endpoint 5                                                   */\n  __IO uint32_t  FIFO6;                             /*!< USB FIFO Endpoint 6                                                   */\n  __IO uint32_t  FIFO7;                             /*!< USB FIFO Endpoint 7                                                   */\n  __I  uint32_t  RESERVED1[8];\n  __IO uint8_t   DEVCTL;                            /*!< USB Device Control                                                    */\n  __I  uint8_t   RESERVED2[1];\n  __IO uint8_t   TXFIFOSZ;                          /*!< USB Transmit Dynamic FIFO Sizing                                      */\n  __IO uint8_t   RXFIFOSZ;                          /*!< USB Receive Dynamic FIFO Sizing                                       */\n  __IO uint16_t  TXFIFOADD;                         /*!< USB Transmit FIFO Start Address                                       */\n  __IO uint16_t  RXFIFOADD;                         /*!< USB Receive FIFO Start Address                                        */\n  __I  uint32_t  RESERVED3[4];\n  __I  uint16_t  RESERVED4;\n  __IO uint8_t   CONTIM;                            /*!< USB Connect Timing                                                    */\n  __IO uint8_t   VPLEN;                             /*!< USB OTG VBUS Pulse Timing                                             */\n  __I  uint8_t   RESERVED5[1];\n  __IO uint8_t   FSEOF;                             /*!< USB Full-Speed Last Transaction to End of Frame Timing                */\n  __IO uint8_t   LSEOF;                             /*!< USB Low-Speed Last Transaction to End of Frame Timing                 */\n  __I  uint8_t   RESERVED6[1];\n  __IO uint8_t   TXFUNCADDR0;                       /*!< USB Transmit Functional Address Endpoint 0                            */\n  __I  uint8_t   RESERVED7[1];\n  __IO uint8_t   TXHUBADDR0;                        /*!< USB Transmit Hub Address Endpoint 0                                   */\n  __IO uint8_t   TXHUBPORT0;                        /*!< USB Transmit Hub Port Endpoint 0                                      */\n  __I  uint32_t  RESERVED8;\n  __IO uint8_t   TXFUNCADDR1;                       /*!< USB Transmit Functional Address Endpoint 1                            */\n  __I  uint8_t   RESERVED9[1];\n  __IO uint8_t   TXHUBADDR1;                        /*!< USB Transmit Hub Address Endpoint 1                                   */\n  __IO uint8_t   TXHUBPORT1;                        /*!< USB Transmit Hub Port Endpoint 1                                      */\n  __IO uint8_t   RXFUNCADDR1;                       /*!< USB Receive Functional Address Endpoint 1                             */\n  __I  uint8_t   RESERVED10[1];\n  __IO uint8_t   RXHUBADDR1;                        /*!< USB Receive Hub Address Endpoint 1                                    */\n  __IO uint8_t   RXHUBPORT1;                        /*!< USB Receive Hub Port Endpoint 1                                       */\n  __IO uint8_t   TXFUNCADDR2;                       /*!< USB Transmit Functional Address Endpoint 2                            */\n  __I  uint8_t   RESERVED11[1];\n  __IO uint8_t   TXHUBADDR2;                        /*!< USB Transmit Hub Address Endpoint 2                                   */\n  __IO uint8_t   TXHUBPORT2;                        /*!< USB Transmit Hub Port Endpoint 2                                      */\n  __IO uint8_t   RXFUNCADDR2;                       /*!< USB Receive Functional Address Endpoint 2                             */\n  __I  uint8_t   RESERVED12[1];\n  __IO uint8_t   RXHUBADDR2;                        /*!< USB Receive Hub Address Endpoint 2                                    */\n  __IO uint8_t   RXHUBPORT2;                        /*!< USB Receive Hub Port Endpoint 2                                       */\n  __IO uint8_t   TXFUNCADDR3;                       /*!< USB Transmit Functional Address Endpoint 3                            */\n  __I  uint8_t   RESERVED13[1];\n  __IO uint8_t   TXHUBADDR3;                        /*!< USB Transmit Hub Address Endpoint 3                                   */\n  __IO uint8_t   TXHUBPORT3;                        /*!< USB Transmit Hub Port Endpoint 3                                      */\n  __IO uint8_t   RXFUNCADDR3;                       /*!< USB Receive Functional Address Endpoint 3                             */\n  __I  uint8_t   RESERVED14[1];\n  __IO uint8_t   RXHUBADDR3;                        /*!< USB Receive Hub Address Endpoint 3                                    */\n  __IO uint8_t   RXHUBPORT3;                        /*!< USB Receive Hub Port Endpoint 3                                       */\n  __IO uint8_t   TXFUNCADDR4;                       /*!< USB Transmit Functional Address Endpoint 4                            */\n  __I  uint8_t   RESERVED15[1];\n  __IO uint8_t   TXHUBADDR4;                        /*!< USB Transmit Hub Address Endpoint 4                                   */\n  __IO uint8_t   TXHUBPORT4;                        /*!< USB Transmit Hub Port Endpoint 4                                      */\n  __IO uint8_t   RXFUNCADDR4;                       /*!< USB Receive Functional Address Endpoint 4                             */\n  __I  uint8_t   RESERVED16[1];\n  __IO uint8_t   RXHUBADDR4;                        /*!< USB Receive Hub Address Endpoint 4                                    */\n  __IO uint8_t   RXHUBPORT4;                        /*!< USB Receive Hub Port Endpoint 4                                       */\n  __IO uint8_t   TXFUNCADDR5;                       /*!< USB Transmit Functional Address Endpoint 5                            */\n  __I  uint8_t   RESERVED17[1];\n  __IO uint8_t   TXHUBADDR5;                        /*!< USB Transmit Hub Address Endpoint 5                                   */\n  __IO uint8_t   TXHUBPORT5;                        /*!< USB Transmit Hub Port Endpoint 5                                      */\n  __IO uint8_t   RXFUNCADDR5;                       /*!< USB Receive Functional Address Endpoint 5                             */\n  __I  uint8_t   RESERVED18[1];\n  __IO uint8_t   RXHUBADDR5;                        /*!< USB Receive Hub Address Endpoint 5                                    */\n  __IO uint8_t   RXHUBPORT5;                        /*!< USB Receive Hub Port Endpoint 5                                       */\n  __IO uint8_t   TXFUNCADDR6;                       /*!< USB Transmit Functional Address Endpoint 6                            */\n  __I  uint8_t   RESERVED19[1];\n  __IO uint8_t   TXHUBADDR6;                        /*!< USB Transmit Hub Address Endpoint 6                                   */\n  __IO uint8_t   TXHUBPORT6;                        /*!< USB Transmit Hub Port Endpoint 6                                      */\n  __IO uint8_t   RXFUNCADDR6;                       /*!< USB Receive Functional Address Endpoint 6                             */\n  __I  uint8_t   RESERVED20[1];\n  __IO uint8_t   RXHUBADDR6;                        /*!< USB Receive Hub Address Endpoint 6                                    */\n  __IO uint8_t   RXHUBPORT6;                        /*!< USB Receive Hub Port Endpoint 6                                       */\n  __IO uint8_t   TXFUNCADDR7;                       /*!< USB Transmit Functional Address Endpoint 7                            */\n  __I  uint8_t   RESERVED21[1];\n  __IO uint8_t   TXHUBADDR7;                        /*!< USB Transmit Hub Address Endpoint 7                                   */\n  __IO uint8_t   TXHUBPORT7;                        /*!< USB Transmit Hub Port Endpoint 7                                      */\n  __IO uint8_t   RXFUNCADDR7;                       /*!< USB Receive Functional Address Endpoint 7                             */\n  __I  uint8_t   RESERVED22[1];\n  __IO uint8_t   RXHUBADDR7;                        /*!< USB Receive Hub Address Endpoint 7                                    */\n  __IO uint8_t   RXHUBPORT7;                        /*!< USB Receive Hub Port Endpoint 7                                       */\n  __I  uint32_t  RESERVED23[16];\n  __I  uint16_t  RESERVED24;\n\n  union {\n    __O  uint8_t   CSRL0_USB0_ALT;                  /*!< USB Control and Status Endpoint 0 Low                                 */\n    __O  uint8_t   CSRL0;                           /*!< USB Control and Status Endpoint 0 Low                                 */\n  };\n  __O  uint8_t   CSRH0;                             /*!< USB Control and Status Endpoint 0 High                                */\n  __I  uint16_t  RESERVED25[3];\n  __IO uint8_t   COUNT0;                            /*!< USB Receive Byte Count Endpoint 0                                     */\n  __I  uint8_t   RESERVED26[1];\n  __IO uint8_t   TYPE0;                             /*!< USB Type Endpoint 0                                                   */\n  __IO uint8_t   NAKLMT;                            /*!< USB NAK Limit                                                         */\n  __I  uint32_t  RESERVED27;\n  __IO uint16_t  TXMAXP1;                           /*!< USB Maximum Transmit Data Endpoint 1                                  */\n\n  union {\n    __IO uint8_t   TXCSRL1_USB0_ALT;                /*!< USB Transmit Control and Status Endpoint 1 Low                        */\n    __IO uint8_t   TXCSRL1;                         /*!< USB Transmit Control and Status Endpoint 1 Low                        */\n  };\n  __IO uint8_t   TXCSRH1;                           /*!< USB Transmit Control and Status Endpoint 1 High                       */\n  __IO uint16_t  RXMAXP1;                           /*!< USB Maximum Receive Data Endpoint 1                                   */\n\n  union {\n    __IO uint8_t   RXCSRL1_USB0_ALT;                /*!< USB Receive Control and Status Endpoint 1 Low                         */\n    __IO uint8_t   RXCSRL1;                         /*!< USB Receive Control and Status Endpoint 1 Low                         */\n  };\n\n  union {\n    __IO uint8_t   RXCSRH1_USB0_ALT;                /*!< USB Receive Control and Status Endpoint 1 High                        */\n    __IO uint8_t   RXCSRH1;                         /*!< USB Receive Control and Status Endpoint 1 High                        */\n  };\n  __IO uint16_t  RXCOUNT1;                          /*!< USB Receive Byte Count Endpoint 1                                     */\n  __IO uint8_t   TXTYPE1;                           /*!< USB Host Transmit Configure Type Endpoint 1                           */\n\n  union {\n    __IO uint8_t   TXINTERVAL1_USB0_ALT;            /*!< USB Host Transmit Interval Endpoint 1                                 */\n    __IO uint8_t   TXINTERVAL1;                     /*!< USB Host Transmit Interval Endpoint 1                                 */\n  };\n  __IO uint8_t   RXTYPE1;                           /*!< USB Host Configure Receive Type Endpoint 1                            */\n\n  union {\n    __IO uint8_t   RXINTERVAL1_USB0_ALT;            /*!< USB Host Receive Polling Interval Endpoint 1                          */\n    __IO uint8_t   RXINTERVAL1;                     /*!< USB Host Receive Polling Interval Endpoint 1                          */\n  };\n  __I  uint16_t  RESERVED28;\n  __IO uint16_t  TXMAXP2;                           /*!< USB Maximum Transmit Data Endpoint 2                                  */\n\n  union {\n    __IO uint8_t   TXCSRL2_USB0_ALT;                /*!< USB Transmit Control and Status Endpoint 2 Low                        */\n    __IO uint8_t   TXCSRL2;                         /*!< USB Transmit Control and Status Endpoint 2 Low                        */\n  };\n  __IO uint8_t   TXCSRH2;                           /*!< USB Transmit Control and Status Endpoint 2 High                       */\n  __IO uint16_t  RXMAXP2;                           /*!< USB Maximum Receive Data Endpoint 2                                   */\n\n  union {\n    __IO uint8_t   RXCSRL2_USB0_ALT;                /*!< USB Receive Control and Status Endpoint 2 Low                         */\n    __IO uint8_t   RXCSRL2;                         /*!< USB Receive Control and Status Endpoint 2 Low                         */\n  };\n\n  union {\n    __IO uint8_t   RXCSRH2_USB0_ALT;                /*!< USB Receive Control and Status Endpoint 2 High                        */\n    __IO uint8_t   RXCSRH2;                         /*!< USB Receive Control and Status Endpoint 2 High                        */\n  };\n  __IO uint16_t  RXCOUNT2;                          /*!< USB Receive Byte Count Endpoint 2                                     */\n  __IO uint8_t   TXTYPE2;                           /*!< USB Host Transmit Configure Type Endpoint 2                           */\n\n  union {\n    __IO uint8_t   TXINTERVAL2_USB0_ALT;            /*!< USB Host Transmit Interval Endpoint 2                                 */\n    __IO uint8_t   TXINTERVAL2;                     /*!< USB Host Transmit Interval Endpoint 2                                 */\n  };\n  __IO uint8_t   RXTYPE2;                           /*!< USB Host Configure Receive Type Endpoint 2                            */\n\n  union {\n    __IO uint8_t   RXINTERVAL2_USB0_ALT;            /*!< USB Host Receive Polling Interval Endpoint 2                          */\n    __IO uint8_t   RXINTERVAL2;                     /*!< USB Host Receive Polling Interval Endpoint 2                          */\n  };\n  __I  uint16_t  RESERVED29;\n  __IO uint16_t  TXMAXP3;                           /*!< USB Maximum Transmit Data Endpoint 3                                  */\n\n  union {\n    __IO uint8_t   TXCSRL3_USB0_ALT;                /*!< USB Transmit Control and Status Endpoint 3 Low                        */\n    __IO uint8_t   TXCSRL3;                         /*!< USB Transmit Control and Status Endpoint 3 Low                        */\n  };\n  __IO uint8_t   TXCSRH3;                           /*!< USB Transmit Control and Status Endpoint 3 High                       */\n  __IO uint16_t  RXMAXP3;                           /*!< USB Maximum Receive Data Endpoint 3                                   */\n\n  union {\n    __IO uint8_t   RXCSRL3_USB0_ALT;                /*!< USB Receive Control and Status Endpoint 3 Low                         */\n    __IO uint8_t   RXCSRL3;                         /*!< USB Receive Control and Status Endpoint 3 Low                         */\n  };\n\n  union {\n    __IO uint8_t   RXCSRH3_USB0_ALT;                /*!< USB Receive Control and Status Endpoint 3 High                        */\n    __IO uint8_t   RXCSRH3;                         /*!< USB Receive Control and Status Endpoint 3 High                        */\n  };\n  __IO uint16_t  RXCOUNT3;                          /*!< USB Receive Byte Count Endpoint 3                                     */\n  __IO uint8_t   TXTYPE3;                           /*!< USB Host Transmit Configure Type Endpoint 3                           */\n\n  union {\n    __IO uint8_t   TXINTERVAL3_USB0_ALT;            /*!< USB Host Transmit Interval Endpoint 3                                 */\n    __IO uint8_t   TXINTERVAL3;                     /*!< USB Host Transmit Interval Endpoint 3                                 */\n  };\n  __IO uint8_t   RXTYPE3;                           /*!< USB Host Configure Receive Type Endpoint 3                            */\n\n  union {\n    __IO uint8_t   RXINTERVAL3_USB0_ALT;            /*!< USB Host Receive Polling Interval Endpoint 3                          */\n    __IO uint8_t   RXINTERVAL3;                     /*!< USB Host Receive Polling Interval Endpoint 3                          */\n  };\n  __I  uint16_t  RESERVED30;\n  __IO uint16_t  TXMAXP4;                           /*!< USB Maximum Transmit Data Endpoint 4                                  */\n\n  union {\n    __IO uint8_t   TXCSRL4_USB0_ALT;                /*!< USB Transmit Control and Status Endpoint 4 Low                        */\n    __IO uint8_t   TXCSRL4;                         /*!< USB Transmit Control and Status Endpoint 4 Low                        */\n  };\n  __IO uint8_t   TXCSRH4;                           /*!< USB Transmit Control and Status Endpoint 4 High                       */\n  __IO uint16_t  RXMAXP4;                           /*!< USB Maximum Receive Data Endpoint 4                                   */\n\n  union {\n    __IO uint8_t   RXCSRL4_USB0_ALT;                /*!< USB Receive Control and Status Endpoint 4 Low                         */\n    __IO uint8_t   RXCSRL4;                         /*!< USB Receive Control and Status Endpoint 4 Low                         */\n  };\n\n  union {\n    __IO uint8_t   RXCSRH4_USB0_ALT;                /*!< USB Receive Control and Status Endpoint 4 High                        */\n    __IO uint8_t   RXCSRH4;                         /*!< USB Receive Control and Status Endpoint 4 High                        */\n  };\n  __IO uint16_t  RXCOUNT4;                          /*!< USB Receive Byte Count Endpoint 4                                     */\n  __IO uint8_t   TXTYPE4;                           /*!< USB Host Transmit Configure Type Endpoint 4                           */\n\n  union {\n    __IO uint8_t   TXINTERVAL4_USB0_ALT;            /*!< USB Host Transmit Interval Endpoint 4                                 */\n    __IO uint8_t   TXINTERVAL4;                     /*!< USB Host Transmit Interval Endpoint 4                                 */\n  };\n  __IO uint8_t   RXTYPE4;                           /*!< USB Host Configure Receive Type Endpoint 4                            */\n\n  union {\n    __IO uint8_t   RXINTERVAL4_USB0_ALT;            /*!< USB Host Receive Polling Interval Endpoint 4                          */\n    __IO uint8_t   RXINTERVAL4;                     /*!< USB Host Receive Polling Interval Endpoint 4                          */\n  };\n  __I  uint16_t  RESERVED31;\n  __IO uint16_t  TXMAXP5;                           /*!< USB Maximum Transmit Data Endpoint 5                                  */\n\n  union {\n    __IO uint8_t   TXCSRL5_USB0_ALT;                /*!< USB Transmit Control and Status Endpoint 5 Low                        */\n    __IO uint8_t   TXCSRL5;                         /*!< USB Transmit Control and Status Endpoint 5 Low                        */\n  };\n  __IO uint8_t   TXCSRH5;                           /*!< USB Transmit Control and Status Endpoint 5 High                       */\n  __IO uint16_t  RXMAXP5;                           /*!< USB Maximum Receive Data Endpoint 5                                   */\n\n  union {\n    __IO uint8_t   RXCSRL5_USB0_ALT;                /*!< USB Receive Control and Status Endpoint 5 Low                         */\n    __IO uint8_t   RXCSRL5;                         /*!< USB Receive Control and Status Endpoint 5 Low                         */\n  };\n\n  union {\n    __IO uint8_t   RXCSRH5_USB0_ALT;                /*!< USB Receive Control and Status Endpoint 5 High                        */\n    __IO uint8_t   RXCSRH5;                         /*!< USB Receive Control and Status Endpoint 5 High                        */\n  };\n  __IO uint16_t  RXCOUNT5;                          /*!< USB Receive Byte Count Endpoint 5                                     */\n  __IO uint8_t   TXTYPE5;                           /*!< USB Host Transmit Configure Type Endpoint 5                           */\n\n  union {\n    __IO uint8_t   TXINTERVAL5_USB0_ALT;            /*!< USB Host Transmit Interval Endpoint 5                                 */\n    __IO uint8_t   TXINTERVAL5;                     /*!< USB Host Transmit Interval Endpoint 5                                 */\n  };\n  __IO uint8_t   RXTYPE5;                           /*!< USB Host Configure Receive Type Endpoint 5                            */\n\n  union {\n    __IO uint8_t   RXINTERVAL5_USB0_ALT;            /*!< USB Host Receive Polling Interval Endpoint 5                          */\n    __IO uint8_t   RXINTERVAL5;                     /*!< USB Host Receive Polling Interval Endpoint 5                          */\n  };\n  __I  uint16_t  RESERVED32;\n  __IO uint16_t  TXMAXP6;                           /*!< USB Maximum Transmit Data Endpoint 6                                  */\n\n  union {\n    __IO uint8_t   TXCSRL6_USB0_ALT;                /*!< USB Transmit Control and Status Endpoint 6 Low                        */\n    __IO uint8_t   TXCSRL6;                         /*!< USB Transmit Control and Status Endpoint 6 Low                        */\n  };\n  __IO uint8_t   TXCSRH6;                           /*!< USB Transmit Control and Status Endpoint 6 High                       */\n  __IO uint16_t  RXMAXP6;                           /*!< USB Maximum Receive Data Endpoint 6                                   */\n\n  union {\n    __IO uint8_t   RXCSRL6_USB0_ALT;                /*!< USB Receive Control and Status Endpoint 6 Low                         */\n    __IO uint8_t   RXCSRL6;                         /*!< USB Receive Control and Status Endpoint 6 Low                         */\n  };\n\n  union {\n    __IO uint8_t   RXCSRH6_USB0_ALT;                /*!< USB Receive Control and Status Endpoint 6 High                        */\n    __IO uint8_t   RXCSRH6;                         /*!< USB Receive Control and Status Endpoint 6 High                        */\n  };\n  __IO uint16_t  RXCOUNT6;                          /*!< USB Receive Byte Count Endpoint 6                                     */\n  __IO uint8_t   TXTYPE6;                           /*!< USB Host Transmit Configure Type Endpoint 6                           */\n\n  union {\n    __IO uint8_t   TXINTERVAL6_USB0_ALT;            /*!< USB Host Transmit Interval Endpoint 6                                 */\n    __IO uint8_t   TXINTERVAL6;                     /*!< USB Host Transmit Interval Endpoint 6                                 */\n  };\n  __IO uint8_t   RXTYPE6;                           /*!< USB Host Configure Receive Type Endpoint 6                            */\n\n  union {\n    __IO uint8_t   RXINTERVAL6_USB0_ALT;            /*!< USB Host Receive Polling Interval Endpoint 6                          */\n    __IO uint8_t   RXINTERVAL6;                     /*!< USB Host Receive Polling Interval Endpoint 6                          */\n  };\n  __I  uint16_t  RESERVED33;\n  __IO uint16_t  TXMAXP7;                           /*!< USB Maximum Transmit Data Endpoint 7                                  */\n\n  union {\n    __IO uint8_t   TXCSRL7_USB0_ALT;                /*!< USB Transmit Control and Status Endpoint 7 Low                        */\n    __IO uint8_t   TXCSRL7;                         /*!< USB Transmit Control and Status Endpoint 7 Low                        */\n  };\n  __IO uint8_t   TXCSRH7;                           /*!< USB Transmit Control and Status Endpoint 7 High                       */\n  __IO uint16_t  RXMAXP7;                           /*!< USB Maximum Receive Data Endpoint 7                                   */\n\n  union {\n    __IO uint8_t   RXCSRL7_USB0_ALT;                /*!< USB Receive Control and Status Endpoint 7 Low                         */\n    __IO uint8_t   RXCSRL7;                         /*!< USB Receive Control and Status Endpoint 7 Low                         */\n  };\n\n  union {\n    __IO uint8_t   RXCSRH7_USB0_ALT;                /*!< USB Receive Control and Status Endpoint 7 High                        */\n    __IO uint8_t   RXCSRH7;                         /*!< USB Receive Control and Status Endpoint 7 High                        */\n  };\n  __IO uint16_t  RXCOUNT7;                          /*!< USB Receive Byte Count Endpoint 7                                     */\n  __IO uint8_t   TXTYPE7;                           /*!< USB Host Transmit Configure Type Endpoint 7                           */\n\n  union {\n    __IO uint8_t   TXINTERVAL7_USB0_ALT;            /*!< USB Host Transmit Interval Endpoint 7                                 */\n    __IO uint8_t   TXINTERVAL7;                     /*!< USB Host Transmit Interval Endpoint 7                                 */\n  };\n  __IO uint8_t   RXTYPE7;                           /*!< USB Host Configure Receive Type Endpoint 7                            */\n\n  union {\n    __IO uint8_t   RXINTERVAL7_USB0_ALT;            /*!< USB Host Receive Polling Interval Endpoint 7                          */\n    __IO uint8_t   RXINTERVAL7;                     /*!< USB Host Receive Polling Interval Endpoint 7                          */\n  };\n  __I  uint16_t  RESERVED34[195];\n  __IO uint16_t  RQPKTCOUNT1;                       /*!< USB Request Packet Count in Block Transfer Endpoint 1                 */\n  __I  uint16_t  RESERVED35;\n  __IO uint16_t  RQPKTCOUNT2;                       /*!< USB Request Packet Count in Block Transfer Endpoint 2                 */\n  __I  uint16_t  RESERVED36;\n  __IO uint16_t  RQPKTCOUNT3;                       /*!< USB Request Packet Count in Block Transfer Endpoint 3                 */\n  __I  uint16_t  RESERVED37;\n  __IO uint16_t  RQPKTCOUNT4;                       /*!< USB Request Packet Count in Block Transfer Endpoint 4                 */\n  __I  uint16_t  RESERVED38;\n  __IO uint16_t  RQPKTCOUNT5;                       /*!< USB Request Packet Count in Block Transfer Endpoint 5                 */\n  __I  uint16_t  RESERVED39;\n  __IO uint16_t  RQPKTCOUNT6;                       /*!< USB Request Packet Count in Block Transfer Endpoint 6                 */\n  __I  uint16_t  RESERVED40;\n  __IO uint16_t  RQPKTCOUNT7;                       /*!< USB Request Packet Count in Block Transfer Endpoint 7                 */\n  __I  uint16_t  RESERVED41[17];\n  __IO uint16_t  RXDPKTBUFDIS;                      /*!< USB Receive Double Packet Buffer Disable                              */\n  __IO uint16_t  TXDPKTBUFDIS;                      /*!< USB Transmit Double Packet Buffer Disable                             */\n  __I  uint32_t  RESERVED42[47];\n  __IO uint32_t  EPC;                               /*!< USB External Power Control                                            */\n  __IO uint32_t  EPCRIS;                            /*!< USB External Power Control Raw Interrupt Status                       */\n  __IO uint32_t  EPCIM;                             /*!< USB External Power Control Interrupt Mask                             */\n  __IO uint32_t  EPCISC;                            /*!< USB External Power Control Interrupt Status and Clear                 */\n  __IO uint32_t  DRRIS;                             /*!< USB Device RESUME Raw Interrupt Status                                */\n  __IO uint32_t  DRIM;                              /*!< USB Device RESUME Interrupt Mask                                      */\n  __O  uint32_t  DRISC;                             /*!< USB Device RESUME Interrupt Status and Clear                          */\n  __IO uint32_t  GPCS;                              /*!< USB General-Purpose Control and Status                                */\n  __I  uint32_t  RESERVED43[4];\n  __IO uint32_t  VDC;                               /*!< USB VBUS Droop Control                                                */\n  __IO uint32_t  VDCRIS;                            /*!< USB VBUS Droop Control Raw Interrupt Status                           */\n  __IO uint32_t  VDCIM;                             /*!< USB VBUS Droop Control Interrupt Mask                                 */\n  __IO uint32_t  VDCISC;                            /*!< USB VBUS Droop Control Interrupt Status and Clear                     */\n  __I  uint32_t  RESERVED44;\n  __IO uint32_t  IDVRIS;                            /*!< USB ID Valid Detect Raw Interrupt Status                              */\n  __IO uint32_t  IDVIM;                             /*!< USB ID Valid Detect Interrupt Mask                                    */\n  __IO uint32_t  IDVISC;                            /*!< USB ID Valid Detect Interrupt Status and Clear                        */\n  __IO uint32_t  DMASEL;                            /*!< USB DMA Select                                                        */\n  __I  uint32_t  RESERVED45[731];\n  __IO uint32_t  PP;                                /*!< USB Peripheral Properties                                             */\n} USB0_Type;\n\n\n/* ================================================================================ */\n/* ================                     EEPROM                     ================ */\n/* ================================================================================ */\n\n\n/**\n  * @brief Register map for EEPROM peripheral (EEPROM)\n  */\n\ntypedef struct {                                    /*!< EEPROM Structure                                                      */\n  __IO uint32_t  EESIZE;                            /*!< EEPROM Size Information                                               */\n  __IO uint32_t  EEBLOCK;                           /*!< EEPROM Current Block                                                  */\n  __IO uint32_t  EEOFFSET;                          /*!< EEPROM Current Offset                                                 */\n  __I  uint32_t  RESERVED0;\n  __IO uint32_t  EERDWR;                            /*!< EEPROM Read-Write                                                     */\n  __IO uint32_t  EERDWRINC;                         /*!< EEPROM Read-Write with Increment                                      */\n  __IO uint32_t  EEDONE;                            /*!< EEPROM Done Status                                                    */\n  __IO uint32_t  EESUPP;                            /*!< EEPROM Support Control and Status                                     */\n  __IO uint32_t  EEUNLOCK;                          /*!< EEPROM Unlock                                                         */\n  __I  uint32_t  RESERVED1[3];\n  __IO uint32_t  EEPROT;                            /*!< EEPROM Protection                                                     */\n  __IO uint32_t  EEPASS0;                           /*!< EEPROM Password                                                       */\n  __IO uint32_t  EEPASS1;                           /*!< EEPROM Password                                                       */\n  __IO uint32_t  EEPASS2;                           /*!< EEPROM Password                                                       */\n  __IO uint32_t  EEINT;                             /*!< EEPROM Interrupt                                                      */\n  __I  uint32_t  RESERVED2[3];\n  __IO uint32_t  EEHIDE;                            /*!< EEPROM Block Hide                                                     */\n  __I  uint32_t  RESERVED3[11];\n  __IO uint32_t  EEDBGME;                           /*!< EEPROM Debug Mass Erase                                               */\n  __I  uint32_t  RESERVED4[975];\n  __IO uint32_t  PP;                                /*!< EEPROM Peripheral Properties                                          */\n} EEPROM_Type;\n\n\n/* ================================================================================ */\n/* ================                     SYSEXC                     ================ */\n/* ================================================================================ */\n\n\n/**\n  * @brief Register map for SYSEXC peripheral (SYSEXC)\n  */\n\ntypedef struct {                                    /*!< SYSEXC Structure                                                      */\n  __IO uint32_t  RIS;                               /*!< System Exception Raw Interrupt Status                                 */\n  __IO uint32_t  IM;                                /*!< System Exception Interrupt Mask                                       */\n  __IO uint32_t  MIS;                               /*!< System Exception Masked Interrupt Status                              */\n  __O  uint32_t  IC;                                /*!< System Exception Interrupt Clear                                      */\n} SYSEXC_Type;\n\n\n/* ================================================================================ */\n/* ================                       HIB                      ================ */\n/* ================================================================================ */\n\n\n/**\n  * @brief Register map for HIB peripheral (HIB)\n  */\n\ntypedef struct {                                    /*!< HIB Structure                                                         */\n  __IO uint32_t  RTCC;                              /*!< Hibernation RTC Counter                                               */\n  __IO uint32_t  RTCM0;                             /*!< Hibernation RTC Match 0                                               */\n  __I  uint32_t  RESERVED0;\n  __IO uint32_t  RTCLD;                             /*!< Hibernation RTC Load                                                  */\n  __IO uint32_t  CTL;                               /*!< Hibernation Control                                                   */\n  __IO uint32_t  IM;                                /*!< Hibernation Interrupt Mask                                            */\n  __IO uint32_t  RIS;                               /*!< Hibernation Raw Interrupt Status                                      */\n  __IO uint32_t  MIS;                               /*!< Hibernation Masked Interrupt Status                                   */\n  __IO uint32_t  IC;                                /*!< Hibernation Interrupt Clear                                           */\n  __IO uint32_t  RTCT;                              /*!< Hibernation RTC Trim                                                  */\n  __IO uint32_t  RTCSS;                             /*!< Hibernation RTC Sub Seconds                                           */\n  __I  uint32_t  RESERVED1;\n  __IO uint32_t  DATA;                              /*!< Hibernation Data                                                      */\n} HIB_Type;\n\n\n/* ================================================================================ */\n/* ================                   FLASH_CTRL                   ================ */\n/* ================================================================================ */\n\n\n/**\n  * @brief Register map for FLASH_CTRL peripheral (FLASH_CTRL)\n  */\n\ntypedef struct {                                    /*!< FLASH_CTRL Structure                                                  */\n  __IO uint32_t  FMA;                               /*!< Flash Memory Address                                                  */\n  __IO uint32_t  FMD;                               /*!< Flash Memory Data                                                     */\n  __IO uint32_t  FMC;                               /*!< Flash Memory Control                                                  */\n  __IO uint32_t  FCRIS;                             /*!< Flash Controller Raw Interrupt Status                                 */\n  __IO uint32_t  FCIM;                              /*!< Flash Controller Interrupt Mask                                       */\n  __IO uint32_t  FCMISC;                            /*!< Flash Controller Masked Interrupt Status and Clear                    */\n  __I  uint32_t  RESERVED0[2];\n  __IO uint32_t  FMC2;                              /*!< Flash Memory Control 2                                                */\n  __I  uint32_t  RESERVED1[3];\n  __IO uint32_t  FWBVAL;                            /*!< Flash Write Buffer Valid                                              */\n  __I  uint32_t  RESERVED2[51];\n  __IO uint32_t  FWBN;                              /*!< Flash Write Buffer n                                                  */\n  __I  uint32_t  RESERVED3[943];\n  __IO uint32_t  FSIZE;                             /*!< Flash Size                                                            */\n  __IO uint32_t  SSIZE;                             /*!< SRAM Size                                                             */\n  __I  uint32_t  RESERVED4;\n\n  union {\n    __IO uint32_t  ROMSWMAP_FLASH_CTRL_ALT;         /*!< ROM Software Map                                                      */\n    __IO uint32_t  ROMSWMAP;                        /*!< ROM Software Map                                                      */\n  };\n  __I  uint32_t  RESERVED5[72];\n  __IO uint32_t  RMCTL;                             /*!< ROM Control                                                           */\n  __I  uint32_t  RESERVED6[55];\n  __IO uint32_t  BOOTCFG;                           /*!< Boot Configuration                                                    */\n  __I  uint32_t  RESERVED7[3];\n  __IO uint32_t  USERREG0;                          /*!< User Register 0                                                       */\n  __IO uint32_t  USERREG1;                          /*!< User Register 1                                                       */\n  __IO uint32_t  USERREG2;                          /*!< User Register 2                                                       */\n  __IO uint32_t  USERREG3;                          /*!< User Register 3                                                       */\n  __I  uint32_t  RESERVED8[4];\n  __IO uint32_t  FMPRE0;                            /*!< Flash Memory Protection Read Enable 0                                 */\n  __IO uint32_t  FMPRE1;                            /*!< Flash Memory Protection Read Enable 1                                 */\n  __IO uint32_t  FMPRE2;                            /*!< Flash Memory Protection Read Enable 2                                 */\n  __IO uint32_t  FMPRE3;                            /*!< Flash Memory Protection Read Enable 3                                 */\n  __I  uint32_t  RESERVED9[124];\n  __IO uint32_t  FMPPE0;                            /*!< Flash Memory Protection Program Enable 0                              */\n  __IO uint32_t  FMPPE1;                            /*!< Flash Memory Protection Program Enable 1                              */\n  __IO uint32_t  FMPPE2;                            /*!< Flash Memory Protection Program Enable 2                              */\n  __IO uint32_t  FMPPE3;                            /*!< Flash Memory Protection Program Enable 3                              */\n} FLASH_CTRL_Type;\n\n\n/* ================================================================================ */\n/* ================                     SYSCTL                     ================ */\n/* ================================================================================ */\n\n\n/**\n  * @brief Register map for SYSCTL peripheral (SYSCTL)\n  */\n\ntypedef struct {                                    /*!< SYSCTL Structure                                                      */\n  __IO uint32_t  DID0;                              /*!< Device Identification 0                                               */\n  __IO uint32_t  DID1;                              /*!< Device Identification 1                                               */\n  __IO uint32_t  DC0;                               /*!< Device Capabilities 0                                                 */\n  __I  uint32_t  RESERVED0;\n  __IO uint32_t  DC1;                               /*!< Device Capabilities 1                                                 */\n  __IO uint32_t  DC2;                               /*!< Device Capabilities 2                                                 */\n  __IO uint32_t  DC3;                               /*!< Device Capabilities 3                                                 */\n  __IO uint32_t  DC4;                               /*!< Device Capabilities 4                                                 */\n  __IO uint32_t  DC5;                               /*!< Device Capabilities 5                                                 */\n  __IO uint32_t  DC6;                               /*!< Device Capabilities 6                                                 */\n  __IO uint32_t  DC7;                               /*!< Device Capabilities 7                                                 */\n  __IO uint32_t  DC8;                               /*!< Device Capabilities 8                                                 */\n  __IO uint32_t  PBORCTL;                           /*!< Brown-Out Reset Control                                               */\n  __I  uint32_t  RESERVED1[3];\n  __IO uint32_t  SRCR0;                             /*!< Software Reset Control 0                                              */\n  __IO uint32_t  SRCR1;                             /*!< Software Reset Control 1                                              */\n  __IO uint32_t  SRCR2;                             /*!< Software Reset Control 2                                              */\n  __I  uint32_t  RESERVED2;\n  __IO uint32_t  RIS;                               /*!< Raw Interrupt Status                                                  */\n  __IO uint32_t  IMC;                               /*!< Interrupt Mask Control                                                */\n  __IO uint32_t  MISC;                              /*!< Masked Interrupt Status and Clear                                     */\n  __IO uint32_t  RESC;                              /*!< Reset Cause                                                           */\n  __IO uint32_t  RCC;                               /*!< Run-Mode Clock Configuration                                          */\n  __I  uint32_t  RESERVED3[2];\n  __IO uint32_t  GPIOHBCTL;                         /*!< GPIO High-Performance Bus Control                                     */\n  __IO uint32_t  RCC2;                              /*!< Run-Mode Clock Configuration 2                                        */\n  __I  uint32_t  RESERVED4[2];\n  __IO uint32_t  MOSCCTL;                           /*!< Main Oscillator Control                                               */\n  __I  uint32_t  RESERVED5[32];\n  __IO uint32_t  RCGC0;                             /*!< Run Mode Clock Gating Control Register 0                              */\n  __IO uint32_t  RCGC1;                             /*!< Run Mode Clock Gating Control Register 1                              */\n  __IO uint32_t  RCGC2;                             /*!< Run Mode Clock Gating Control Register 2                              */\n  __I  uint32_t  RESERVED6;\n  __IO uint32_t  SCGC0;                             /*!< Sleep Mode Clock Gating Control Register 0                            */\n  __IO uint32_t  SCGC1;                             /*!< Sleep Mode Clock Gating Control Register 1                            */\n  __IO uint32_t  SCGC2;                             /*!< Sleep Mode Clock Gating Control Register 2                            */\n  __I  uint32_t  RESERVED7;\n  __IO uint32_t  DCGC0;                             /*!< Deep Sleep Mode Clock Gating Control Register 0                       */\n  __IO uint32_t  DCGC1;                             /*!< Deep-Sleep Mode Clock Gating Control Register 1                       */\n  __IO uint32_t  DCGC2;                             /*!< Deep Sleep Mode Clock Gating Control Register 2                       */\n  __I  uint32_t  RESERVED8[6];\n  __IO uint32_t  DSLPCLKCFG;                        /*!< Deep Sleep Clock Configuration                                        */\n  __I  uint32_t  RESERVED9;\n  __IO uint32_t  SYSPROP;                           /*!< System Properties                                                     */\n  __IO uint32_t  PIOSCCAL;                          /*!< Precision Internal Oscillator Calibration                             */\n  __IO uint32_t  PIOSCSTAT;                         /*!< Precision Internal Oscillator Statistics                              */\n  __I  uint32_t  RESERVED10[2];\n  __IO uint32_t  PLLFREQ0;                          /*!< PLL Frequency 0                                                       */\n  __IO uint32_t  PLLFREQ1;                          /*!< PLL Frequency 1                                                       */\n  __IO uint32_t  PLLSTAT;                           /*!< PLL Status                                                            */\n  __I  uint32_t  RESERVED11[7];\n  __IO uint32_t  SLPPWRCFG;                         /*!< Sleep Power Configuration                                             */\n  __IO uint32_t  DSLPPWRCFG;                        /*!< Deep-Sleep Power Configuration                                        */\n  __IO uint32_t  DC9;                               /*!< Device Capabilities 9                                                 */\n  __I  uint32_t  RESERVED12[3];\n  __IO uint32_t  NVMSTAT;                           /*!< Non-Volatile Memory Information                                       */\n  __I  uint32_t  RESERVED13[4];\n  __IO uint32_t  LDOSPCTL;                          /*!< LDO Sleep Power Control                                               */\n  __I  uint32_t  RESERVED14;\n  __IO uint32_t  LDODPCTL;                          /*!< LDO Deep-Sleep Power Control                                          */\n  __I  uint32_t  RESERVED15[80];\n  __IO uint32_t  PPWD;                              /*!< Watchdog Timer Peripheral Present                                     */\n  __IO uint32_t  PPTIMER;                           /*!< 16/32-Bit General-Purpose Timer Peripheral Present                    */\n  __IO uint32_t  PPGPIO;                            /*!< General-Purpose Input/Output Peripheral Present                       */\n  __IO uint32_t  PPDMA;                             /*!< Micro Direct Memory Access Peripheral Present                         */\n  __I  uint32_t  RESERVED16;\n  __IO uint32_t  PPHIB;                             /*!< Hibernation Peripheral Present                                        */\n  __IO uint32_t  PPUART;                            /*!< Universal Asynchronous Receiver/Transmitter Peripheral Present        */\n  __IO uint32_t  PPSSI;                             /*!< Synchronous Serial Interface Peripheral Present                       */\n  __IO uint32_t  PPI2C;                             /*!< Inter-Integrated Circuit Peripheral Present                           */\n  __I  uint32_t  RESERVED17;\n  __IO uint32_t  PPUSB;                             /*!< Universal Serial Bus Peripheral Present                               */\n  __I  uint32_t  RESERVED18[2];\n  __IO uint32_t  PPCAN;                             /*!< Controller Area Network Peripheral Present                            */\n  __IO uint32_t  PPADC;                             /*!< Analog-to-Digital Converter Peripheral Present                        */\n  __IO uint32_t  PPACMP;                            /*!< Analog Comparator Peripheral Present                                  */\n  __IO uint32_t  PPPWM;                             /*!< Pulse Width Modulator Peripheral Present                              */\n  __IO uint32_t  PPQEI;                             /*!< Quadrature Encoder Interface Peripheral Present                       */\n  __I  uint32_t  RESERVED19[4];\n  __IO uint32_t  PPEEPROM;                          /*!< EEPROM Peripheral Present                                             */\n  __IO uint32_t  PPWTIMER;                          /*!< 32/64-Bit Wide General-Purpose Timer Peripheral Present               */\n  __I  uint32_t  RESERVED20[104];\n  __IO uint32_t  SRWD;                              /*!< Watchdog Timer Software Reset                                         */\n  __IO uint32_t  SRTIMER;                           /*!< 16/32-Bit General-Purpose Timer Software Reset                        */\n  __IO uint32_t  SRGPIO;                            /*!< General-Purpose Input/Output Software Reset                           */\n  __IO uint32_t  SRDMA;                             /*!< Micro Direct Memory Access Software Reset                             */\n  __I  uint32_t  RESERVED21;\n  __IO uint32_t  SRHIB;                             /*!< Hibernation Software Reset                                            */\n  __IO uint32_t  SRUART;                            /*!< Universal Asynchronous Receiver/Transmitter Software Reset            */\n  __IO uint32_t  SRSSI;                             /*!< Synchronous Serial Interface Software Reset                           */\n  __IO uint32_t  SRI2C;                             /*!< Inter-Integrated Circuit Software Reset                               */\n  __I  uint32_t  RESERVED22;\n  __IO uint32_t  SRUSB;                             /*!< Universal Serial Bus Software Reset                                   */\n  __I  uint32_t  RESERVED23[2];\n  __IO uint32_t  SRCAN;                             /*!< Controller Area Network Software Reset                                */\n  __IO uint32_t  SRADC;                             /*!< Analog-to-Digital Converter Software Reset                            */\n  __IO uint32_t  SRACMP;                            /*!< Analog Comparator Software Reset                                      */\n  __IO uint32_t  SRPWM;                             /*!< Pulse Width Modulator Software Reset                                  */\n  __IO uint32_t  SRQEI;                             /*!< Quadrature Encoder Interface Software Reset                           */\n  __I  uint32_t  RESERVED24[4];\n  __IO uint32_t  SREEPROM;                          /*!< EEPROM Software Reset                                                 */\n  __IO uint32_t  SRWTIMER;                          /*!< 32/64-Bit Wide General-Purpose Timer Software Reset                   */\n  __I  uint32_t  RESERVED25[40];\n  __IO uint32_t  RCGCWD;                            /*!< Watchdog Timer Run Mode Clock Gating Control                          */\n  __IO uint32_t  RCGCTIMER;                         /*!< 16/32-Bit General-Purpose Timer Run Mode Clock Gating Control         */\n  __IO uint32_t  RCGCGPIO;                          /*!< General-Purpose Input/Output Run Mode Clock Gating Control            */\n  __IO uint32_t  RCGCDMA;                           /*!< Micro Direct Memory Access Run Mode Clock Gating Control              */\n  __I  uint32_t  RESERVED26;\n  __IO uint32_t  RCGCHIB;                           /*!< Hibernation Run Mode Clock Gating Control                             */\n  __IO uint32_t  RCGCUART;                          /*!< Universal Asynchronous Receiver/Transmitter Run Mode Clock Gating\n                                                         Control                                                               */\n  __IO uint32_t  RCGCSSI;                           /*!< Synchronous Serial Interface Run Mode Clock Gating Control            */\n  __IO uint32_t  RCGCI2C;                           /*!< Inter-Integrated Circuit Run Mode Clock Gating Control                */\n  __I  uint32_t  RESERVED27;\n  __IO uint32_t  RCGCUSB;                           /*!< Universal Serial Bus Run Mode Clock Gating Control                    */\n  __I  uint32_t  RESERVED28[2];\n  __IO uint32_t  RCGCCAN;                           /*!< Controller Area Network Run Mode Clock Gating Control                 */\n  __IO uint32_t  RCGCADC;                           /*!< Analog-to-Digital Converter Run Mode Clock Gating Control             */\n  __IO uint32_t  RCGCACMP;                          /*!< Analog Comparator Run Mode Clock Gating Control                       */\n  __IO uint32_t  RCGCPWM;                           /*!< Pulse Width Modulator Run Mode Clock Gating Control                   */\n  __IO uint32_t  RCGCQEI;                           /*!< Quadrature Encoder Interface Run Mode Clock Gating Control            */\n  __I  uint32_t  RESERVED29[4];\n  __IO uint32_t  RCGCEEPROM;                        /*!< EEPROM Run Mode Clock Gating Control                                  */\n  __IO uint32_t  RCGCWTIMER;                        /*!< 32/64-Bit Wide General-Purpose Timer Run Mode Clock Gating Control    */\n  __I  uint32_t  RESERVED30[40];\n  __IO uint32_t  SCGCWD;                            /*!< Watchdog Timer Sleep Mode Clock Gating Control                        */\n  __IO uint32_t  SCGCTIMER;                         /*!< 16/32-Bit General-Purpose Timer Sleep Mode Clock Gating Control       */\n  __IO uint32_t  SCGCGPIO;                          /*!< General-Purpose Input/Output Sleep Mode Clock Gating Control          */\n  __IO uint32_t  SCGCDMA;                           /*!< Micro Direct Memory Access Sleep Mode Clock Gating Control            */\n  __I  uint32_t  RESERVED31;\n  __IO uint32_t  SCGCHIB;                           /*!< Hibernation Sleep Mode Clock Gating Control                           */\n  __IO uint32_t  SCGCUART;                          /*!< Universal Asynchronous Receiver/Transmitter Sleep Mode Clock\n                                                         Gating Control                                                        */\n  __IO uint32_t  SCGCSSI;                           /*!< Synchronous Serial Interface Sleep Mode Clock Gating Control          */\n  __IO uint32_t  SCGCI2C;                           /*!< Inter-Integrated Circuit Sleep Mode Clock Gating Control              */\n  __I  uint32_t  RESERVED32;\n  __IO uint32_t  SCGCUSB;                           /*!< Universal Serial Bus Sleep Mode Clock Gating Control                  */\n  __I  uint32_t  RESERVED33[2];\n  __IO uint32_t  SCGCCAN;                           /*!< Controller Area Network Sleep Mode Clock Gating Control               */\n  __IO uint32_t  SCGCADC;                           /*!< Analog-to-Digital Converter Sleep Mode Clock Gating Control           */\n  __IO uint32_t  SCGCACMP;                          /*!< Analog Comparator Sleep Mode Clock Gating Control                     */\n  __IO uint32_t  SCGCPWM;                           /*!< Pulse Width Modulator Sleep Mode Clock Gating Control                 */\n  __IO uint32_t  SCGCQEI;                           /*!< Quadrature Encoder Interface Sleep Mode Clock Gating Control          */\n  __I  uint32_t  RESERVED34[4];\n  __IO uint32_t  SCGCEEPROM;                        /*!< EEPROM Sleep Mode Clock Gating Control                                */\n  __IO uint32_t  SCGCWTIMER;                        /*!< 32/64-Bit Wide General-Purpose Timer Sleep Mode Clock Gating\n                                                         Control                                                               */\n  __I  uint32_t  RESERVED35[40];\n  __IO uint32_t  DCGCWD;                            /*!< Watchdog Timer Deep-Sleep Mode Clock Gating Control                   */\n  __IO uint32_t  DCGCTIMER;                         /*!< 16/32-Bit General-Purpose Timer Deep-Sleep Mode Clock Gating\n                                                         Control                                                               */\n  __IO uint32_t  DCGCGPIO;                          /*!< General-Purpose Input/Output Deep-Sleep Mode Clock Gating Control     */\n  __IO uint32_t  DCGCDMA;                           /*!< Micro Direct Memory Access Deep-Sleep Mode Clock Gating Control       */\n  __I  uint32_t  RESERVED36;\n  __IO uint32_t  DCGCHIB;                           /*!< Hibernation Deep-Sleep Mode Clock Gating Control                      */\n  __IO uint32_t  DCGCUART;                          /*!< Universal Asynchronous Receiver/Transmitter Deep-Sleep Mode\n                                                         Clock Gating Control                                                  */\n  __IO uint32_t  DCGCSSI;                           /*!< Synchronous Serial Interface Deep-Sleep Mode Clock Gating Control     */\n  __IO uint32_t  DCGCI2C;                           /*!< Inter-Integrated Circuit Deep-Sleep Mode Clock Gating Control         */\n  __I  uint32_t  RESERVED37;\n  __IO uint32_t  DCGCUSB;                           /*!< Universal Serial Bus Deep-Sleep Mode Clock Gating Control             */\n  __I  uint32_t  RESERVED38[2];\n  __IO uint32_t  DCGCCAN;                           /*!< Controller Area Network Deep-Sleep Mode Clock Gating Control          */\n  __IO uint32_t  DCGCADC;                           /*!< Analog-to-Digital Converter Deep-Sleep Mode Clock Gating Control      */\n  __IO uint32_t  DCGCACMP;                          /*!< Analog Comparator Deep-Sleep Mode Clock Gating Control                */\n  __IO uint32_t  DCGCPWM;                           /*!< Pulse Width Modulator Deep-Sleep Mode Clock Gating Control            */\n  __IO uint32_t  DCGCQEI;                           /*!< Quadrature Encoder Interface Deep-Sleep Mode Clock Gating Control     */\n  __I  uint32_t  RESERVED39[4];\n  __IO uint32_t  DCGCEEPROM;                        /*!< EEPROM Deep-Sleep Mode Clock Gating Control                           */\n  __IO uint32_t  DCGCWTIMER;                        /*!< 32/64-Bit Wide General-Purpose Timer Deep-Sleep Mode Clock Gating\n                                                         Control                                                               */\n  __I  uint32_t  RESERVED40[104];\n  __IO uint32_t  PRWD;                              /*!< Watchdog Timer Peripheral Ready                                       */\n  __IO uint32_t  PRTIMER;                           /*!< 16/32-Bit General-Purpose Timer Peripheral Ready                      */\n  __IO uint32_t  PRGPIO;                            /*!< General-Purpose Input/Output Peripheral Ready                         */\n  __IO uint32_t  PRDMA;                             /*!< Micro Direct Memory Access Peripheral Ready                           */\n  __I  uint32_t  RESERVED41;\n  __IO uint32_t  PRHIB;                             /*!< Hibernation Peripheral Ready                                          */\n  __IO uint32_t  PRUART;                            /*!< Universal Asynchronous Receiver/Transmitter Peripheral Ready          */\n  __IO uint32_t  PRSSI;                             /*!< Synchronous Serial Interface Peripheral Ready                         */\n  __IO uint32_t  PRI2C;                             /*!< Inter-Integrated Circuit Peripheral Ready                             */\n  __I  uint32_t  RESERVED42;\n  __IO uint32_t  PRUSB;                             /*!< Universal Serial Bus Peripheral Ready                                 */\n  __I  uint32_t  RESERVED43[2];\n  __IO uint32_t  PRCAN;                             /*!< Controller Area Network Peripheral Ready                              */\n  __IO uint32_t  PRADC;                             /*!< Analog-to-Digital Converter Peripheral Ready                          */\n  __IO uint32_t  PRACMP;                            /*!< Analog Comparator Peripheral Ready                                    */\n  __IO uint32_t  PRPWM;                             /*!< Pulse Width Modulator Peripheral Ready                                */\n  __IO uint32_t  PRQEI;                             /*!< Quadrature Encoder Interface Peripheral Ready                         */\n  __I  uint32_t  RESERVED44[4];\n  __IO uint32_t  PREEPROM;                          /*!< EEPROM Peripheral Ready                                               */\n  __IO uint32_t  PRWTIMER;                          /*!< 32/64-Bit Wide General-Purpose Timer Peripheral Ready                 */\n} SYSCTL_Type;\n\n\n/* ================================================================================ */\n/* ================                      UDMA                      ================ */\n/* ================================================================================ */\n\n\n/**\n  * @brief Register map for UDMA peripheral (UDMA)\n  */\n\ntypedef struct {                                    /*!< UDMA Structure                                                        */\n  __IO uint32_t  STAT;                              /*!< DMA Status                                                            */\n  __O  uint32_t  CFG;                               /*!< DMA Configuration                                                     */\n  __IO uint32_t  CTLBASE;                           /*!< DMA Channel Control Base Pointer                                      */\n  __IO uint32_t  ALTBASE;                           /*!< DMA Alternate Channel Control Base Pointer                            */\n  __IO uint32_t  WAITSTAT;                          /*!< DMA Channel Wait-on-Request Status                                    */\n  __O  uint32_t  SWREQ;                             /*!< DMA Channel Software Request                                          */\n  __IO uint32_t  USEBURSTSET;                       /*!< DMA Channel Useburst Set                                              */\n  __O  uint32_t  USEBURSTCLR;                       /*!< DMA Channel Useburst Clear                                            */\n  __IO uint32_t  REQMASKSET;                        /*!< DMA Channel Request Mask Set                                          */\n  __O  uint32_t  REQMASKCLR;                        /*!< DMA Channel Request Mask Clear                                        */\n  __IO uint32_t  ENASET;                            /*!< DMA Channel Enable Set                                                */\n  __O  uint32_t  ENACLR;                            /*!< DMA Channel Enable Clear                                              */\n  __IO uint32_t  ALTSET;                            /*!< DMA Channel Primary Alternate Set                                     */\n  __O  uint32_t  ALTCLR;                            /*!< DMA Channel Primary Alternate Clear                                   */\n  __IO uint32_t  PRIOSET;                           /*!< DMA Channel Priority Set                                              */\n  __O  uint32_t  PRIOCLR;                           /*!< DMA Channel Priority Clear                                            */\n  __I  uint32_t  RESERVED0[3];\n  __IO uint32_t  ERRCLR;                            /*!< DMA Bus Error Clear                                                   */\n  __I  uint32_t  RESERVED1[300];\n  __IO uint32_t  CHASGN;                            /*!< DMA Channel Assignment                                                */\n  __IO uint32_t  CHIS;                              /*!< DMA Channel Interrupt Status                                          */\n  __I  uint32_t  RESERVED2[2];\n  __IO uint32_t  CHMAP0;                            /*!< DMA Channel Map Select 0                                              */\n  __IO uint32_t  CHMAP1;                            /*!< DMA Channel Map Select 1                                              */\n  __IO uint32_t  CHMAP2;                            /*!< DMA Channel Map Select 2                                              */\n  __IO uint32_t  CHMAP3;                            /*!< DMA Channel Map Select 3                                              */\n} UDMA_Type;\n\n\n/* --------------------  End of section using anonymous unions  ------------------- */\n#if defined(__CC_ARM)\n  #pragma pop\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  /* anonymous unions are enabled by default */\n#elif defined(__ICCARM__)\n  /* leave anonymous unions enabled */\n#elif defined(__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined(__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined(__TASKING__)\n  #pragma warning restore\n#else\n  #warning Not supported compiler type\n#endif\n\n\n\n\n/* ================================================================================ */\n/* ================              Peripheral memory map             ================ */\n/* ================================================================================ */\n\n#define WATCHDOG0_BASE                  0x40000000UL\n#define WATCHDOG1_BASE                  0x40001000UL\n#define GPIOA_BASE                      0x40004000UL\n#define GPIOB_BASE                      0x40005000UL\n#define GPIOC_BASE                      0x40006000UL\n#define GPIOD_BASE                      0x40007000UL\n#define SSI0_BASE                       0x40008000UL\n#define SSI1_BASE                       0x40009000UL\n#define SSI2_BASE                       0x4000A000UL\n#define SSI3_BASE                       0x4000B000UL\n#define UART0_BASE                      0x4000C000UL\n#define UART1_BASE                      0x4000D000UL\n#define UART2_BASE                      0x4000E000UL\n#define UART3_BASE                      0x4000F000UL\n#define UART4_BASE                      0x40010000UL\n#define UART5_BASE                      0x40011000UL\n#define UART6_BASE                      0x40012000UL\n#define UART7_BASE                      0x40013000UL\n#define I2C0_BASE                       0x40020000UL\n#define I2C1_BASE                       0x40021000UL\n#define I2C2_BASE                       0x40022000UL\n#define I2C3_BASE                       0x40023000UL\n#define GPIOE_BASE                      0x40024000UL\n#define GPIOF_BASE                      0x40025000UL\n#define PWM0_BASE                       0x40028000UL\n#define PWM1_BASE                       0x40029000UL\n#define QEI0_BASE                       0x4002C000UL\n#define QEI1_BASE                       0x4002D000UL\n#define TIMER0_BASE                     0x40030000UL\n#define TIMER1_BASE                     0x40031000UL\n#define TIMER2_BASE                     0x40032000UL\n#define TIMER3_BASE                     0x40033000UL\n#define TIMER4_BASE                     0x40034000UL\n#define TIMER5_BASE                     0x40035000UL\n#define WTIMER0_BASE                    0x40036000UL\n#define WTIMER1_BASE                    0x40037000UL\n#define ADC0_BASE                       0x40038000UL\n#define ADC1_BASE                       0x40039000UL\n#define COMP_BASE                       0x4003C000UL\n#define CAN0_BASE                       0x40040000UL\n#define CAN1_BASE                       0x40041000UL\n#define WTIMER2_BASE                    0x4004C000UL\n#define WTIMER3_BASE                    0x4004D000UL\n#define WTIMER4_BASE                    0x4004E000UL\n#define WTIMER5_BASE                    0x4004F000UL\n#define USB0_BASE                       0x40050000UL\n#define GPIOA_AHB_BASE                  0x40058000UL\n#define GPIOB_AHB_BASE                  0x40059000UL\n#define GPIOC_AHB_BASE                  0x4005A000UL\n#define GPIOD_AHB_BASE                  0x4005B000UL\n#define GPIOE_AHB_BASE                  0x4005C000UL\n#define GPIOF_AHB_BASE                  0x4005D000UL\n#define EEPROM_BASE                     0x400AF000UL\n#define SYSEXC_BASE                     0x400F9000UL\n#define HIB_BASE                        0x400FC000UL\n#define FLASH_CTRL_BASE                 0x400FD000UL\n#define SYSCTL_BASE                     0x400FE000UL\n#define UDMA_BASE                       0x400FF000UL\n\n\n/* ================================================================================ */\n/* ================             Peripheral declaration             ================ */\n/* ================================================================================ */\n\n#define WATCHDOG0                       ((WATCHDOG0_Type          *) WATCHDOG0_BASE)\n#define WATCHDOG1                       ((WATCHDOG0_Type          *) WATCHDOG1_BASE)\n#define GPIOA                           ((GPIOA_Type              *) GPIOA_BASE)\n#define GPIOB                           ((GPIOA_Type              *) GPIOB_BASE)\n#define GPIOC                           ((GPIOA_Type              *) GPIOC_BASE)\n#define GPIOD                           ((GPIOA_Type              *) GPIOD_BASE)\n#define SSI0                            ((SSI0_Type               *) SSI0_BASE)\n#define SSI1                            ((SSI0_Type               *) SSI1_BASE)\n#define SSI2                            ((SSI0_Type               *) SSI2_BASE)\n#define SSI3                            ((SSI0_Type               *) SSI3_BASE)\n#define UART0                           ((UART0_Type              *) UART0_BASE)\n#define UART1                           ((UART0_Type              *) UART1_BASE)\n#define UART2                           ((UART0_Type              *) UART2_BASE)\n#define UART3                           ((UART0_Type              *) UART3_BASE)\n#define UART4                           ((UART0_Type              *) UART4_BASE)\n#define UART5                           ((UART0_Type              *) UART5_BASE)\n#define UART6                           ((UART0_Type              *) UART6_BASE)\n#define UART7                           ((UART0_Type              *) UART7_BASE)\n#define I2C0                            ((I2C0_Type               *) I2C0_BASE)\n#define I2C1                            ((I2C0_Type               *) I2C1_BASE)\n#define I2C2                            ((I2C0_Type               *) I2C2_BASE)\n#define I2C3                            ((I2C0_Type               *) I2C3_BASE)\n#define GPIOE                           ((GPIOA_Type              *) GPIOE_BASE)\n#define GPIOF                           ((GPIOA_Type              *) GPIOF_BASE)\n#define PWM0                            ((PWM0_Type               *) PWM0_BASE)\n#define PWM1                            ((PWM0_Type               *) PWM1_BASE)\n#define QEI0                            ((QEI0_Type               *) QEI0_BASE)\n#define QEI1                            ((QEI0_Type               *) QEI1_BASE)\n#define TIMER0                          ((TIMER0_Type             *) TIMER0_BASE)\n#define TIMER1                          ((TIMER0_Type             *) TIMER1_BASE)\n#define TIMER2                          ((TIMER0_Type             *) TIMER2_BASE)\n#define TIMER3                          ((TIMER0_Type             *) TIMER3_BASE)\n#define TIMER4                          ((TIMER0_Type             *) TIMER4_BASE)\n#define TIMER5                          ((TIMER0_Type             *) TIMER5_BASE)\n#define WTIMER0                         ((WTIMER0_Type            *) WTIMER0_BASE)\n#define WTIMER1                         ((TIMER0_Type             *) WTIMER1_BASE)\n#define ADC0                            ((ADC0_Type               *) ADC0_BASE)\n#define ADC1                            ((ADC0_Type               *) ADC1_BASE)\n#define COMP                            ((COMP_Type               *) COMP_BASE)\n#define CAN0                            ((CAN0_Type               *) CAN0_BASE)\n#define CAN1                            ((CAN0_Type               *) CAN1_BASE)\n#define WTIMER2                         ((TIMER0_Type             *) WTIMER2_BASE)\n#define WTIMER3                         ((TIMER0_Type             *) WTIMER3_BASE)\n#define WTIMER4                         ((TIMER0_Type             *) WTIMER4_BASE)\n#define WTIMER5                         ((TIMER0_Type             *) WTIMER5_BASE)\n#define USB0                            ((USB0_Type               *) USB0_BASE)\n#define GPIOA_AHB                       ((GPIOA_Type              *) GPIOA_AHB_BASE)\n#define GPIOB_AHB                       ((GPIOA_Type              *) GPIOB_AHB_BASE)\n#define GPIOC_AHB                       ((GPIOA_Type              *) GPIOC_AHB_BASE)\n#define GPIOD_AHB                       ((GPIOA_Type              *) GPIOD_AHB_BASE)\n#define GPIOE_AHB                       ((GPIOA_Type              *) GPIOE_AHB_BASE)\n#define GPIOF_AHB                       ((GPIOA_Type              *) GPIOF_AHB_BASE)\n#define EEPROM                          ((EEPROM_Type             *) EEPROM_BASE)\n#define SYSEXC                          ((SYSEXC_Type             *) SYSEXC_BASE)\n#define HIB                             ((HIB_Type                *) HIB_BASE)\n#define FLASH_CTRL                      ((FLASH_CTRL_Type         *) FLASH_CTRL_BASE)\n#define SYSCTL                          ((SYSCTL_Type             *) SYSCTL_BASE)\n#define UDMA                            ((UDMA_Type               *) UDMA_BASE)\n\n\n/** @} */ /* End of group Device_Peripheral_Registers */\n/** @} */ /* End of group TM4C123GH6PM */\n/** @} */ /* End of group Texas Instruments */\n\n#ifdef __cplusplus\n}\n#endif\n\n\n#endif  /* TM4C123GH6PM_H */\n\n"
  },
  {
    "path": "3rd_party/ek-tm4c123gxl/arm/startup_TM4C123GH6PM.s",
    "content": ";/***************************************************************************/\n; * @file     startup_TM4C123GH6PM.s for ARM-KEIL ARM assembler\n; * @brief    CMSIS Cortex-M4F Core Device Startup File for TM4C123GH6PM\n; * @version  CMSIS 5.9.0\n; * @date     1 Feb 2023\n; *\n; * Modified by Quantum Leaps:\n; * - Added relocating of the Vector Table to free up the 256B region at 0x0\n; *   for NULL-pointer protection by the MPU.\n; * - Modified all exception handlers to branch to assert_failed()\n; *   instead of locking up the CPU inside an endless loop.\n; *\n; * @description\n; * Created from the CMSIS template for the specified device\n; * Quantum Leaps, www.state-machine.com\n; *\n; * @note\n; * The symbols Stack_Size and Heap_Size should be provided on the command-\n; * line options to the assembler, for example as:\n; *     --pd \"Stack_Size SETA 1024\" --pd \"Heap_Size SETA 0\"\n\n\n;******************************************************************************\n; Allocate space for the stack.\n;\n        AREA    STACK, NOINIT, READWRITE, ALIGN=3\n__stack_base\nStackMem\n        SPACE   Stack_Size    ; provided in command-line option, for example:\n                              ; --pd \"Stack_Size SETA 512\"\n__stack_limit\n__initial_sp\n\n;******************************************************************************\n; Allocate space for the heap.\n;\n        AREA    HEAP, NOINIT, READWRITE, ALIGN=3\n__heap_base\nHeapMem\n        SPACE   Heap_Size     ; provided in command-line option, for example:\n                              ; --pd \"Heap_Size SETA 0\"\n__heap_limit\n\n; Indicate that the code in this file preserves 8-byte alignment of the stack.\n        PRESERVE8\n\n;******************************************************************************\n; The vector table.\n;\n; Place code into the reset code section.\n        AREA   RESET, DATA, READONLY, ALIGN=8\n        EXPORT  __Vectors\n        EXPORT  __Vectors_End\n        EXPORT  __Vectors_Size\n\n__Vectors\n    ; Initial Vector Table before relocation\n        DCD     __initial_sp                ; Top of Stack\n        DCD     Reset_Handler               ; Reset Handler\n        DCD     NMI_Handler                 ; NMI Handler\n        DCD     HardFault_Handler           ; Hard Fault Handler\n        DCD     MemManage_Handler           ; MPU fault handler\n        DCD     BusFault_Handler            ; Bus fault handler\n        DCD     UsageFault_Handler          ; Usage fault handler\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     SVC_Handler                 ; SVCall handler\n        DCD     DebugMon_Handler            ; Debug Monitor handler\n        DCD     Default_Handler             ; Reserved\n        DCD     PendSV_Handler              ; PendSV handler\n        DCD     SysTick_Handler             ; SysTick handler\n        ALIGN  256  ; Extend the initial Vector Table to the 256B boundary\n\n    ; Relocated Vector Table beyond the 256B region around address 0.\n    ; That region is used for NULL-pointer protection by the MPU.\n__relocated_vector_table\n        DCD     __initial_sp                ; Top of Stack\n        DCD     Reset_Handler               ; Reset Handler\n        DCD     NMI_Handler                 ; NMI Handler\n        DCD     HardFault_Handler           ; Hard Fault Handler\n        DCD     MemManage_Handler           ; MPU fault handler\n        DCD     BusFault_Handler            ; Bus fault handler\n        DCD     UsageFault_Handler          ; Usage fault handler\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     SVC_Handler                 ; SVCall handler\n        DCD     DebugMon_Handler            ; Debug Monitor handler\n        DCD     Default_Handler             ; Reserved\n        DCD     PendSV_Handler              ; PendSV handler\n        DCD     SysTick_Handler             ; SysTick handler\n\n        ; IRQ handlers...\n        DCD     GPIOPortA_IRQHandler        ; GPIO Port A\n        DCD     GPIOPortB_IRQHandler        ; GPIO Port B\n        DCD     GPIOPortC_IRQHandler        ; GPIO Port C\n        DCD     GPIOPortD_IRQHandler        ; GPIO Port D\n        DCD     GPIOPortE_IRQHandler        ; GPIO Port E\n        DCD     UART0_IRQHandler            ; UART0 Rx and Tx\n        DCD     UART1_IRQHandler            ; UART1 Rx and Tx\n        DCD     SSI0_IRQHandler             ; SSI0 Rx and Tx\n        DCD     I2C0_IRQHandler             ; I2C0 Master and Slave\n        DCD     PWMFault_IRQHandler         ; PWM Fault\n        DCD     PWMGen0_IRQHandler          ; PWM Generator 0\n        DCD     PWMGen1_IRQHandler          ; PWM Generator 1\n        DCD     PWMGen2_IRQHandler          ; PWM Generator 2\n        DCD     QEI0_IRQHandler             ; Quadrature Encoder 0\n        DCD     ADCSeq0_IRQHandler          ; ADC Sequence 0\n        DCD     ADCSeq1_IRQHandler          ; ADC Sequence 1\n        DCD     ADCSeq2_IRQHandler          ; ADC Sequence 2\n        DCD     ADCSeq3_IRQHandler          ; ADC Sequence 3\n        DCD     Watchdog_IRQHandler         ; Watchdog timer\n        DCD     Timer0A_IRQHandler          ; Timer 0 subtimer A\n        DCD     Timer0B_IRQHandler          ; Timer 0 subtimer B\n        DCD     Timer1A_IRQHandler          ; Timer 1 subtimer A\n        DCD     Timer1B_IRQHandler          ; Timer 1 subtimer B\n        DCD     Timer2A_IRQHandler          ; Timer 2 subtimer A\n        DCD     Timer2B_IRQHandler          ; Timer 2 subtimer B\n        DCD     Comp0_IRQHandler            ; Analog Comparator 0\n        DCD     Comp1_IRQHandler            ; Analog Comparator 1\n        DCD     Comp2_IRQHandler            ; Analog Comparator 2\n        DCD     SysCtrl_IRQHandler          ; System Control (PLL, OSC, BO)\n        DCD     FlashCtrl_IRQHandler        ; FLASH Control\n        DCD     GPIOPortF_IRQHandler        ; GPIO Port F\n        DCD     GPIOPortG_IRQHandler        ; GPIO Port G\n        DCD     GPIOPortH_IRQHandler        ; GPIO Port H\n        DCD     UART2_IRQHandler            ; UART2 Rx and Tx\n        DCD     SSI1_IRQHandler             ; SSI1 Rx and Tx\n        DCD     Timer3A_IRQHandler          ; Timer 3 subtimer A\n        DCD     Timer3B_IRQHandler          ; Timer 3 subtimer B\n        DCD     I2C1_IRQHandler             ; I2C1 Master and Slave\n        DCD     QEI1_IRQHandler             ; Quadrature Encoder 1\n        DCD     CAN0_IRQHandler             ; CAN0\n        DCD     CAN1_IRQHandler             ; CAN1\n        DCD     CAN2_IRQHandler             ; CAN2\n        DCD     Default_Handler             ; Reserved\n        DCD     Hibernate_IRQHandler        ; Hibernate\n        DCD     USB0_IRQHandler             ; USB0\n        DCD     PWMGen3_IRQHandler          ; PWM Generator 3\n        DCD     uDMAST_IRQHandler           ; uDMA Software Transfer\n        DCD     uDMAError_IRQHandler        ; uDMA Error\n        DCD     ADC1Seq0_IRQHandler         ; ADC1 Sequence 0\n        DCD     ADC1Seq1_IRQHandler         ; ADC1 Sequence 1\n        DCD     ADC1Seq2_IRQHandler         ; ADC1 Sequence 2\n        DCD     ADC1Seq3_IRQHandler         ; ADC1 Sequence 3\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     GPIOPortJ_IRQHandler        ; GPIO Port J\n        DCD     GPIOPortK_IRQHandler        ; GPIO Port K\n        DCD     GPIOPortL_IRQHandler        ; GPIO Port L\n        DCD     SSI2_IRQHandler             ; SSI2 Rx and Tx\n        DCD     SSI3_IRQHandler             ; SSI3 Rx and Tx\n        DCD     UART3_IRQHandler            ; UART3 Rx and Tx\n        DCD     UART4_IRQHandler            ; UART4 Rx and Tx\n        DCD     UART5_IRQHandler            ; UART5 Rx and Tx\n        DCD     UART6_IRQHandler            ; UART6 Rx and Tx\n        DCD     UART7_IRQHandler            ; UART7 Rx and Tx\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     I2C2_IRQHandler             ; I2C2 Master and Slave\n        DCD     I2C3_IRQHandler             ; I2C3 Master and Slave\n        DCD     Timer4A_IRQHandler          ; Timer 4 subtimer A\n        DCD     Timer4B_IRQHandler          ; Timer 4 subtimer B\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Timer5A_IRQHandler          ; Timer 5 subtimer A\n        DCD     Timer5B_IRQHandler          ; Timer 5 subtimer B\n        DCD     WideTimer0A_IRQHandler      ; Wide Timer 0 subtimer A\n        DCD     WideTimer0B_IRQHandler      ; Wide Timer 0 subtimer B\n        DCD     WideTimer1A_IRQHandler      ; Wide Timer 1 subtimer A\n        DCD     WideTimer1B_IRQHandler      ; Wide Timer 1 subtimer B\n        DCD     WideTimer2A_IRQHandler      ; Wide Timer 2 subtimer A\n        DCD     WideTimer2B_IRQHandler      ; Wide Timer 2 subtimer B\n        DCD     WideTimer3A_IRQHandler      ; Wide Timer 3 subtimer A\n        DCD     WideTimer3B_IRQHandler      ; Wide Timer 3 subtimer B\n        DCD     WideTimer4A_IRQHandler      ; Wide Timer 4 subtimer A\n        DCD     WideTimer4B_IRQHandler      ; Wide Timer 4 subtimer B\n        DCD     WideTimer5A_IRQHandler      ; Wide Timer 5 subtimer A\n        DCD     WideTimer5B_IRQHandler      ; Wide Timer 5 subtimer B\n        DCD     FPU_IRQHandler              ; FPU\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     I2C4_IRQHandler             ; I2C4 Master and Slave\n        DCD     I2C5_IRQHandler             ; I2C5 Master and Slave\n        DCD     GPIOPortM_IRQHandler        ; GPIO Port M\n        DCD     GPIOPortN_IRQHandler        ; GPIO Port N\n        DCD     QEI2_IRQHandler             ; Quadrature Encoder 2\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     GPIOPortP0_IRQHandler       ; GPIO Port P (Summary or P0)\n        DCD     GPIOPortP1_IRQHandler       ; GPIO Port P1\n        DCD     GPIOPortP2_IRQHandler       ; GPIO Port P2\n        DCD     GPIOPortP3_IRQHandler       ; GPIO Port P3\n        DCD     GPIOPortP4_IRQHandler       ; GPIO Port P4\n        DCD     GPIOPortP5_IRQHandler       ; GPIO Port P5\n        DCD     GPIOPortP6_IRQHandler       ; GPIO Port P6\n        DCD     GPIOPortP7_IRQHandler       ; GPIO Port P7\n        DCD     GPIOPortQ0_IRQHandler       ; GPIO Port Q (Summary or Q0)\n        DCD     GPIOPortQ1_IRQHandler       ; GPIO Port Q1\n        DCD     GPIOPortQ2_IRQHandler       ; GPIO Port Q2\n        DCD     GPIOPortQ3_IRQHandler       ; GPIO Port Q3\n        DCD     GPIOPortQ4_IRQHandler       ; GPIO Port Q4\n        DCD     GPIOPortQ5_IRQHandler       ; GPIO Port Q5\n        DCD     GPIOPortQ6_IRQHandler       ; GPIO Port Q6\n        DCD     GPIOPortQ7_IRQHandler       ; GPIO Port Q7\n        DCD     GPIOPortR_IRQHandler        ; GPIO Port R\n        DCD     GPIOPortS_IRQHandler        ; GPIO Port S\n        DCD     PWM1Gen0_IRQHandler         ; PWM 1 Generator 0\n        DCD     PWM1Gen1_IRQHandler         ; PWM 1 Generator 1\n        DCD     PWM1Gen2_IRQHandler         ; PWM 1 Generator 2\n        DCD     PWM1Gen3_IRQHandler         ; PWM 1 Generator 3\n        DCD     PWM1Fault_IRQHandler        ; PWM 1 Fault\n\n__Vectors_End\n\n__Vectors_Size  EQU   __Vectors_End - __Vectors\n\n\n;******************************************************************************\n; This is the code for exception handlers.\n;\n        AREA    |.text|, CODE, READONLY\n\n;******************************************************************************\n; This is the code that gets called when the processor first starts execution\n; following a reset event.\n;\nReset_Handler   PROC\n        EXPORT  Reset_Handler  [WEAK]\n        IMPORT  SystemInit\n        IMPORT  __main\n        IMPORT  assert_failed\n\n        ; relocate the Vector Table\n        LDR     r0,=0xE000ED08  ; System Control Block/Vector Table Offset Reg\n        LDR     r1,=__relocated_vector_table\n        STR     r1,[r0]         ; SCB->VTOR := __relocated_vector_table\n\n        LDR     r0,=SystemInit  ; CMSIS system initialization\n        BLX     r0\n\n        ; Call the C library enty point that handles startup. This will copy\n        ; the .data section initializers from flash to SRAM and zero fill the\n        ; .bss section.\n        ; NOTE: The __main function clears the C stack as well\n        LDR     r0,=__main\n        BX      r0\n\n        ; __main calls the main() function, which should not return,\n        ; but just in case jump to assert_failed() if main returns.\n        LDR     r0,=str_EXIT\n        MOVS    r1,#1\n        LDR     r2,=__initial_sp  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_EXIT\n        DCB     \"EXIT\"\n        ALIGN\n        ENDP\n\n;******************************************************************************\nNMI_Handler     PROC\n        EXPORT  NMI_Handler     [WEAK]\n        IMPORT  assert_failed\n        LDR     r0,=str_NMI\n        MOVS    r1,#1\n        LDR     r2,=__initial_sp  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_NMI\n        DCB     \"NMI\"\n        ALIGN\n        ENDP\n\n;******************************************************************************\nHardFault_Handler PROC\n        EXPORT  HardFault_Handler [WEAK]\n        IMPORT  assert_failed\n        LDR     r0,=str_HardFault\n        MOVS    r1,#1\n        LDR     r2,=__initial_sp  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_HardFault\n        DCB     \"HardFault\"\n        ALIGN\n        ENDP\n\n;******************************************************************************\nMemManage_Handler PROC\n        EXPORT  MemManage_Handler     [WEAK]\n        IMPORT  assert_failed\n        LDR     r0,=str_MemManage\n        MOVS    r1,#1\n        LDR     r2,=__initial_sp  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_MemManage\n        DCB     \"MemManage\"\n        ALIGN\n        ENDP\n\n;******************************************************************************\nBusFault_Handler PROC\n        EXPORT  BusFault_Handler     [WEAK]\n        IMPORT  assert_failed\n        LDR     r0,=str_BusFault\n        MOVS    r1,#1\n        LDR     r2,=__initial_sp  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_BusFault\n        DCB     \"BusFault\"\n        ALIGN\n        ENDP\n\n;******************************************************************************\nUsageFault_Handler PROC\n        EXPORT  UsageFault_Handler   [WEAK]\n        IMPORT  assert_failed\n        LDR     r0,=str_UsageFault\n        MOVS    r1,#1\n        LDR     r2,=__initial_sp  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_UsageFault\n        DCB     \"UsageFault\"\n        ALIGN\n        ENDP\n\n\n;******************************************************************************\n;\n; Weak non-fault handlers...\n;\n\n;******************************************************************************\nSVC_Handler PROC\n        EXPORT  SVC_Handler   [WEAK]\n        IMPORT  assert_failed\n        LDR     r0,=str_SVC\n        MOVS    r1,#1\n        LDR     r2,=__initial_sp  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_SVC\n        DCB     \"SVC\"\n        ALIGN\n        ENDP\n\n;******************************************************************************\nDebugMon_Handler PROC\n        EXPORT  DebugMon_Handler     [WEAK]\n        IMPORT  assert_failed\n        LDR     r0,=str_DebugMon\n        MOVS    r1,#1\n        LDR     r2,=__initial_sp  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_DebugMon\n        DCB     \"DebugMon\"\n        ALIGN\n        ENDP\n\n;******************************************************************************\nPendSV_Handler PROC\n        EXPORT  PendSV_Handler       [WEAK]\n        IMPORT  assert_failed\n        LDR     r0,=str_PendSV\n        MOVS    r1,#1\n        LDR     r2,=__initial_sp  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_PendSV\n        DCB     \"PendSV\"\n        ALIGN\n        ENDP\n\n;******************************************************************************\nSysTick_Handler PROC\n        EXPORT  SysTick_Handler     [WEAK]\n        IMPORT  assert_failed\n        LDR     r0,=str_SysTick\n        MOVS    r1,#1\n        LDR     r2,=__initial_sp  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_SysTick\n        DCB     \"SysTick\"\n        ALIGN\n        ENDP\n\n;******************************************************************************\nDefault_Handler PROC\n        EXPORT  GPIOPortA_IRQHandler       [WEAK]\n        EXPORT  GPIOPortB_IRQHandler       [WEAK]\n        EXPORT  GPIOPortC_IRQHandler       [WEAK]\n        EXPORT  GPIOPortD_IRQHandler       [WEAK]\n        EXPORT  GPIOPortE_IRQHandler       [WEAK]\n        EXPORT  UART0_IRQHandler           [WEAK]\n        EXPORT  UART1_IRQHandler           [WEAK]\n        EXPORT  SSI0_IRQHandler            [WEAK]\n        EXPORT  I2C0_IRQHandler            [WEAK]\n        EXPORT  PWMFault_IRQHandler        [WEAK]\n        EXPORT  PWMGen0_IRQHandler         [WEAK]\n        EXPORT  PWMGen1_IRQHandler         [WEAK]\n        EXPORT  PWMGen2_IRQHandler         [WEAK]\n        EXPORT  QEI0_IRQHandler            [WEAK]\n        EXPORT  ADCSeq0_IRQHandler         [WEAK]\n        EXPORT  ADCSeq1_IRQHandler         [WEAK]\n        EXPORT  ADCSeq2_IRQHandler         [WEAK]\n        EXPORT  ADCSeq3_IRQHandler         [WEAK]\n        EXPORT  Watchdog_IRQHandler        [WEAK]\n        EXPORT  Timer0A_IRQHandler         [WEAK]\n        EXPORT  Timer0B_IRQHandler         [WEAK]\n        EXPORT  Timer1A_IRQHandler         [WEAK]\n        EXPORT  Timer1B_IRQHandler         [WEAK]\n        EXPORT  Timer2A_IRQHandler         [WEAK]\n        EXPORT  Timer2B_IRQHandler         [WEAK]\n        EXPORT  Comp0_IRQHandler           [WEAK]\n        EXPORT  Comp1_IRQHandler           [WEAK]\n        EXPORT  Comp2_IRQHandler           [WEAK]\n        EXPORT  SysCtrl_IRQHandler         [WEAK]\n        EXPORT  FlashCtrl_IRQHandler       [WEAK]\n        EXPORT  GPIOPortF_IRQHandler       [WEAK]\n        EXPORT  GPIOPortG_IRQHandler       [WEAK]\n        EXPORT  GPIOPortH_IRQHandler       [WEAK]\n        EXPORT  UART2_IRQHandler           [WEAK]\n        EXPORT  SSI1_IRQHandler            [WEAK]\n        EXPORT  Timer3A_IRQHandler         [WEAK]\n        EXPORT  Timer3B_IRQHandler         [WEAK]\n        EXPORT  I2C1_IRQHandler            [WEAK]\n        EXPORT  QEI1_IRQHandler            [WEAK]\n        EXPORT  CAN0_IRQHandler            [WEAK]\n        EXPORT  CAN1_IRQHandler            [WEAK]\n        EXPORT  CAN2_IRQHandler            [WEAK]\n        EXPORT  Hibernate_IRQHandler       [WEAK]\n        EXPORT  USB0_IRQHandler            [WEAK]\n        EXPORT  PWMGen3_IRQHandler         [WEAK]\n        EXPORT  uDMAST_IRQHandler          [WEAK]\n        EXPORT  uDMAError_IRQHandler       [WEAK]\n        EXPORT  ADC1Seq0_IRQHandler        [WEAK]\n        EXPORT  ADC1Seq1_IRQHandler        [WEAK]\n        EXPORT  ADC1Seq2_IRQHandler        [WEAK]\n        EXPORT  ADC1Seq3_IRQHandler        [WEAK]\n        EXPORT  GPIOPortJ_IRQHandler       [WEAK]\n        EXPORT  GPIOPortK_IRQHandler       [WEAK]\n        EXPORT  GPIOPortL_IRQHandler       [WEAK]\n        EXPORT  SSI2_IRQHandler            [WEAK]\n        EXPORT  SSI3_IRQHandler            [WEAK]\n        EXPORT  UART3_IRQHandler           [WEAK]\n        EXPORT  UART4_IRQHandler           [WEAK]\n        EXPORT  UART5_IRQHandler           [WEAK]\n        EXPORT  UART6_IRQHandler           [WEAK]\n        EXPORT  UART7_IRQHandler           [WEAK]\n        EXPORT  I2C2_IRQHandler            [WEAK]\n        EXPORT  I2C3_IRQHandler            [WEAK]\n        EXPORT  Timer4A_IRQHandler         [WEAK]\n        EXPORT  Timer4B_IRQHandler         [WEAK]\n        EXPORT  Timer5A_IRQHandler         [WEAK]\n        EXPORT  Timer5B_IRQHandler         [WEAK]\n        EXPORT  WideTimer0A_IRQHandler     [WEAK]\n        EXPORT  WideTimer0B_IRQHandler     [WEAK]\n        EXPORT  WideTimer1A_IRQHandler     [WEAK]\n        EXPORT  WideTimer1B_IRQHandler     [WEAK]\n        EXPORT  WideTimer2A_IRQHandler     [WEAK]\n        EXPORT  WideTimer2B_IRQHandler     [WEAK]\n        EXPORT  WideTimer3A_IRQHandler     [WEAK]\n        EXPORT  WideTimer3B_IRQHandler     [WEAK]\n        EXPORT  WideTimer4A_IRQHandler     [WEAK]\n        EXPORT  WideTimer4B_IRQHandler     [WEAK]\n        EXPORT  WideTimer5A_IRQHandler     [WEAK]\n        EXPORT  WideTimer5B_IRQHandler     [WEAK]\n        EXPORT  FPU_IRQHandler             [WEAK]\n        EXPORT  I2C4_IRQHandler            [WEAK]\n        EXPORT  I2C5_IRQHandler            [WEAK]\n        EXPORT  GPIOPortM_IRQHandler       [WEAK]\n        EXPORT  GPIOPortN_IRQHandler       [WEAK]\n        EXPORT  QEI2_IRQHandler            [WEAK]\n        EXPORT  GPIOPortP0_IRQHandler      [WEAK]\n        EXPORT  GPIOPortP1_IRQHandler      [WEAK]\n        EXPORT  GPIOPortP2_IRQHandler      [WEAK]\n        EXPORT  GPIOPortP3_IRQHandler      [WEAK]\n        EXPORT  GPIOPortP4_IRQHandler      [WEAK]\n        EXPORT  GPIOPortP5_IRQHandler      [WEAK]\n        EXPORT  GPIOPortP6_IRQHandler      [WEAK]\n        EXPORT  GPIOPortP7_IRQHandler      [WEAK]\n        EXPORT  GPIOPortQ0_IRQHandler      [WEAK]\n        EXPORT  GPIOPortQ1_IRQHandler      [WEAK]\n        EXPORT  GPIOPortQ2_IRQHandler      [WEAK]\n        EXPORT  GPIOPortQ3_IRQHandler      [WEAK]\n        EXPORT  GPIOPortQ4_IRQHandler      [WEAK]\n        EXPORT  GPIOPortQ5_IRQHandler      [WEAK]\n        EXPORT  GPIOPortQ6_IRQHandler      [WEAK]\n        EXPORT  GPIOPortQ7_IRQHandler      [WEAK]\n        EXPORT  GPIOPortR_IRQHandler       [WEAK]\n        EXPORT  GPIOPortS_IRQHandler       [WEAK]\n        EXPORT  PWM1Gen0_IRQHandler        [WEAK]\n        EXPORT  PWM1Gen1_IRQHandler        [WEAK]\n        EXPORT  PWM1Gen2_IRQHandler        [WEAK]\n        EXPORT  PWM1Gen3_IRQHandler        [WEAK]\n        EXPORT  PWM1Fault_IRQHandler       [WEAK]\n\nGPIOPortA_IRQHandler\nGPIOPortB_IRQHandler\nGPIOPortC_IRQHandler\nGPIOPortD_IRQHandler\nGPIOPortE_IRQHandler\nUART0_IRQHandler\nUART1_IRQHandler\nSSI0_IRQHandler\nI2C0_IRQHandler\nPWMFault_IRQHandler\nPWMGen0_IRQHandler\nPWMGen1_IRQHandler\nPWMGen2_IRQHandler\nQEI0_IRQHandler\nADCSeq0_IRQHandler\nADCSeq1_IRQHandler\nADCSeq2_IRQHandler\nADCSeq3_IRQHandler\nWatchdog_IRQHandler\nTimer0A_IRQHandler\nTimer0B_IRQHandler\nTimer1A_IRQHandler\nTimer1B_IRQHandler\nTimer2A_IRQHandler\nTimer2B_IRQHandler\nComp0_IRQHandler\nComp1_IRQHandler\nComp2_IRQHandler\nSysCtrl_IRQHandler\nFlashCtrl_IRQHandler\nGPIOPortF_IRQHandler\nGPIOPortG_IRQHandler\nGPIOPortH_IRQHandler\nUART2_IRQHandler\nSSI1_IRQHandler\nTimer3A_IRQHandler\nTimer3B_IRQHandler\nI2C1_IRQHandler\nQEI1_IRQHandler\nCAN0_IRQHandler\nCAN1_IRQHandler\nCAN2_IRQHandler\nHibernate_IRQHandler\nUSB0_IRQHandler\nPWMGen3_IRQHandler\nuDMAST_IRQHandler\nuDMAError_IRQHandler\nADC1Seq0_IRQHandler\nADC1Seq1_IRQHandler\nADC1Seq2_IRQHandler\nADC1Seq3_IRQHandler\nGPIOPortJ_IRQHandler\nGPIOPortK_IRQHandler\nGPIOPortL_IRQHandler\nSSI2_IRQHandler\nSSI3_IRQHandler\nUART3_IRQHandler\nUART4_IRQHandler\nUART5_IRQHandler\nUART6_IRQHandler\nUART7_IRQHandler\nI2C2_IRQHandler\nI2C3_IRQHandler\nTimer4A_IRQHandler\nTimer4B_IRQHandler\nTimer5A_IRQHandler\nTimer5B_IRQHandler\nWideTimer0A_IRQHandler\nWideTimer0B_IRQHandler\nWideTimer1A_IRQHandler\nWideTimer1B_IRQHandler\nWideTimer2A_IRQHandler\nWideTimer2B_IRQHandler\nWideTimer3A_IRQHandler\nWideTimer3B_IRQHandler\nWideTimer4A_IRQHandler\nWideTimer4B_IRQHandler\nWideTimer5A_IRQHandler\nWideTimer5B_IRQHandler\nFPU_IRQHandler\nI2C4_IRQHandler\nI2C5_IRQHandler\nGPIOPortM_IRQHandler\nGPIOPortN_IRQHandler\nQEI2_IRQHandler\nGPIOPortP0_IRQHandler\nGPIOPortP1_IRQHandler\nGPIOPortP2_IRQHandler\nGPIOPortP3_IRQHandler\nGPIOPortP4_IRQHandler\nGPIOPortP5_IRQHandler\nGPIOPortP6_IRQHandler\nGPIOPortP7_IRQHandler\nGPIOPortQ0_IRQHandler\nGPIOPortQ1_IRQHandler\nGPIOPortQ2_IRQHandler\nGPIOPortQ3_IRQHandler\nGPIOPortQ4_IRQHandler\nGPIOPortQ5_IRQHandler\nGPIOPortQ6_IRQHandler\nGPIOPortQ7_IRQHandler\nGPIOPortR_IRQHandler\nGPIOPortS_IRQHandler\nPWM1Gen0_IRQHandler\nPWM1Gen1_IRQHandler\nPWM1Gen2_IRQHandler\nPWM1Gen3_IRQHandler\nPWM1Fault_IRQHandler\n        IMPORT  assert_failed\n        LDR     r0,=str_Undefined\n        MOVS    r1,#1\n        LDR     r2,=__initial_sp  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_Undefined\n        DCB     \"Undefined\"\n        ALIGN\n        ENDP\n\n        ALIGN               ; make sure the end of this section is aligned\n\n;******************************************************************************\n; The function expected of the C library startup code for defining the stack\n; and heap memory locations.  For the C library version of the startup code,\n; provide this function so that the C library initialization code can find out\n; the location of the stack and heap.\n;\n    IF :DEF: __MICROLIB\n        EXPORT  __initial_sp\n        EXPORT  __stack_limit\n        EXPORT  __heap_base\n        EXPORT  __heap_limit\n    ELSE\n        IMPORT  __use_two_region_memory\n        EXPORT  __user_initial_stackheap\n\n__user_initial_stackheap PROC\n        LDR     R0, =__heap_base\n        LDR     R1, =__stack_limit\n        LDR     R2, =__heap_limit\n        LDR     R3, =__stack_base\n        BX      LR\n        ENDP\n    ENDIF\n        ALIGN               ; make sure the end of this section is aligned\n\n    END                     ; end of module\n\n"
  },
  {
    "path": "3rd_party/ek-tm4c123gxl/gnu/ek-tm4c123gxl.ld",
    "content": "/*****************************************************************************\n* Product: Linker script for EK-TM4C123GXL, GNU-ARM linker\n* Last Updated for Version: 5.9.8\n* Date of the Last Update:  2017-09-13\n*\n*                    Q u a n t u m     L e a P s\n*                    ---------------------------\n*                    innovating embedded systems\n*\n* Copyright (C) Quantum Leaps, LLC. All rights reserved.\n*\n*****************************************************************************/\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nENTRY(Reset_Handler) /* entry Point */\n\nMEMORY { /* memory map of Tiva TM4C123GH6PM */\n    ROM (rx)  : ORIGIN = 0x00000000, LENGTH = 256K\n    RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K\n}\n\n/* The size of the stack used by the application. NOTE: you need to adjust  */\nSTACK_SIZE = 2048;\n\n/* The size of the heap used by the application. NOTE: you need to adjust   */\nHEAP_SIZE = 0;\n\nSECTIONS {\n\n    .isr_vector : {        /* the vector table goes FIRST into ROM */\n        KEEP(*(.isr_vector)) /* vector table */\n        . = ALIGN(4);\n    } >ROM\n\n    .text : {              /* code and constants */\n        . = ALIGN(4);\n        *(.text)           /* .text sections (code) */\n        *(.text*)          /* .text* sections (code) */\n        *(.rodata)         /* .rodata sections (constants, strings, etc.) */\n        *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */\n\n        KEEP (*(.init))\n        KEEP (*(.fini))\n\n        . = ALIGN(4);\n    } >ROM\n\n    .preinit_array : {\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP (*(.preinit_array*))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n    } >ROM\n\n    .init_array : {\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array*))\n        PROVIDE_HIDDEN (__init_array_end = .);\n    } >ROM\n\n    .fini_array : {\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP (*(.fini_array*))\n        KEEP (*(SORT(.fini_array.*)))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n    } >ROM\n\n    _etext = .;            /* global symbols at end of code */\n\n    .stack : {\n        __stack_start__ = .;\n        . = . + STACK_SIZE;\n        . = ALIGN(4);\n        __stack_end__ = .;\n    } >RAM\n\n    .data :  AT (_etext) {\n        __data_load = LOADADDR (.data);\n        __data_start = .;\n        *(.data)           /* .data sections */\n        *(.data*)          /* .data* sections */\n        . = ALIGN(4);\n        __data_end__ = .;\n        _edata = __data_end__;\n    } >RAM\n\n    .bss : {\n        __bss_start__ = .;\n        *(.bss)\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = .;         /* define a global symbol at bss end */\n        __bss_end__ = .;\n    } >RAM\n\n    __exidx_start = .;\n    .ARM.exidx   : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } >RAM\n    __exidx_end = .;\n\n    PROVIDE ( end = _ebss );\n    PROVIDE ( _end = _ebss );\n    PROVIDE ( __end__ = _ebss );\n\n    .heap : {\n        __heap_start__ = .;\n        . = . + HEAP_SIZE;\n        . = ALIGN(4);\n        __heap_end__ = .;\n    } >RAM\n\n    /* Remove information from the standard libraries */\n    /DISCARD/ : {\n        libc.a ( * )\n        libm.a ( * )\n        libgcc.a ( * )\n    }\n}\n"
  },
  {
    "path": "3rd_party/ek-tm4c123gxl/gnu/startup_TM4C123GH6PM.c",
    "content": "/* File: startup_TM4C123GH6PM.c for GNU-ARM\n * Purpose: startup file for TM4C123GH6PM Cortex-M4 device.\n *          Should be used with GCC 'GNU Tools ARM Embedded'\n * Version: CMSIS 5.0.1\n * Date: 2017-09-13\n *\n * Modified by Quantum Leaps:\n * - Added relocating of the Vector Table to free up the 256B region at 0x0\n *   for NULL-pointer protection by the MPU.\n * - Modified all exception handlers to branch to assert_failed()\n *   instead of locking up the CPU inside an endless loop.\n *\n * Created from the CMSIS template for the specified device\n * Quantum Leaps, www.state-machine.com\n *\n * NOTE:\n * The function assert_failed defined at the end of this file defines\n * the error/assertion handling policy for the application and might\n * need to be customized for each project. This function is defined in\n * assembly to re-set the stack pointer, in case it is corrupted by the\n * time assert_failed is called.\n */\n\n/* start and end of stack defined in the linker script ---------------------*/\n/*extern int __stack_start__;*/\nextern int __stack_end__;\n\n/* Weak prototypes for error handlers --------------------------------------*/\n/**\n* \\note\n* The function assert_failed defined at the end of this file defines\n* the error/assertion handling policy for the application and might\n* need to be customized for each project. This function is defined in\n* assembly to avoid accessing the stack, which might be corrupted by\n* the time assert_failed is called.\n*/\n__attribute__ ((naked, noreturn))\nvoid assert_failed(char const *module, int loc);\n\n/* Function prototypes -----------------------------------------------------*/\nvoid Default_Handler(void);  /* Default empty handler */\nvoid Reset_Handler(void);    /* Reset Handler */\nvoid SystemInit(void);       /* CMSIS system initialization */\n\n/*----------------------------------------------------------------------------\n* weak aliases for each Exception handler to the Default_Handler.\n* Any function with the same name will override these definitions.\n*/\n/* Cortex-M Processor fault exceptions... */\nvoid NMI_Handler           (void) __attribute__ ((weak));\nvoid HardFault_Handler     (void) __attribute__ ((weak));\nvoid MemManage_Handler     (void) __attribute__ ((weak));\nvoid BusFault_Handler      (void) __attribute__ ((weak));\nvoid UsageFault_Handler    (void) __attribute__ ((weak));\n\n/* Cortex-M Processor non-fault exceptions... */\nvoid SVC_Handler           (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n/* external interrupts...   */\nvoid GPIOPortA_IRQHandler  (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid GPIOPortB_IRQHandler  (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid GPIOPortC_IRQHandler  (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid GPIOPortD_IRQHandler  (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid GPIOPortE_IRQHandler  (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UART0_IRQHandler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UART1_IRQHandler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SSI0_IRQHandler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid I2C0_IRQHandler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PWMFault_IRQHandler   (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PWMGen0_IRQHandler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PWMGen1_IRQHandler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PWMGen2_IRQHandler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid QEI0_IRQHandler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid ADCSeq0_IRQHandler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid ADCSeq1_IRQHandler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid ADCSeq2_IRQHandler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid ADCSeq3_IRQHandler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Watchdog_IRQHandler   (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Timer0A_IRQHandler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Timer0B_IRQHandler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Timer1A_IRQHandler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Timer1B_IRQHandler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Timer2A_IRQHandler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Timer2B_IRQHandler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Comp0_IRQHandler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Comp1_IRQHandler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Comp2_IRQHandler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysCtrl_IRQHandler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid FlashCtrl_IRQHandler  (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid GPIOPortF_IRQHandler  (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid GPIOPortG_IRQHandler  (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid GPIOPortH_IRQHandler  (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UART2_IRQHandler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SSI1_IRQHandler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Timer3A_IRQHandler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Timer3B_IRQHandler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid I2C1_IRQHandler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid QEI1_IRQHandler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid CAN0_IRQHandler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid CAN1_IRQHandler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid CAN2_IRQHandler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Hibernate_IRQHandler  (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid USB0_IRQHandler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PWMGen3_IRQHandler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid uDMAST_IRQHandler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid uDMAError_IRQHandler  (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid ADC1Seq0_IRQHandler   (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid ADC1Seq1_IRQHandler   (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid ADC1Seq2_IRQHandler   (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid ADC1Seq3_IRQHandler   (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid GPIOPortJ_IRQHandler  (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid GPIOPortK_IRQHandler  (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid GPIOPortL_IRQHandler  (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SSI2_IRQHandler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SSI3_IRQHandler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UART3_IRQHandler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UART4_IRQHandler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UART5_IRQHandler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UART6_IRQHandler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UART7_IRQHandler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid I2C2_IRQHandler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid I2C3_IRQHandler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Timer4A_IRQHandler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Timer4B_IRQHandler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Timer5A_IRQHandler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Timer5B_IRQHandler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid WideTimer0A_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid WideTimer0B_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid WideTimer1A_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid WideTimer1B_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid WideTimer2A_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid WideTimer2B_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid WideTimer3A_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid WideTimer3B_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid WideTimer4A_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid WideTimer4B_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid WideTimer5A_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid WideTimer5B_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid FPU_IRQHandler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid I2C4_IRQHandler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid I2C5_IRQHandler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid GPIOPortM_IRQHandler  (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid GPIOPortN_IRQHandler  (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid QEI2_IRQHandler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid GPIOPortP0_IRQHandler (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid GPIOPortP1_IRQHandler (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid GPIOPortP2_IRQHandler (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid GPIOPortP3_IRQHandler (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid GPIOPortP4_IRQHandler (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid GPIOPortP5_IRQHandler (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid GPIOPortP6_IRQHandler (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid GPIOPortP7_IRQHandler (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid GPIOPortQ0_IRQHandler (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid GPIOPortQ1_IRQHandler (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid GPIOPortQ2_IRQHandler (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid GPIOPortQ3_IRQHandler (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid GPIOPortQ4_IRQHandler (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid GPIOPortQ5_IRQHandler (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid GPIOPortQ6_IRQHandler (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid GPIOPortQ7_IRQHandler (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid GPIOPortR_IRQHandler  (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid GPIOPortS_IRQHandler  (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PWM1Gen0_IRQHandler   (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PWM1Gen1_IRQHandler   (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PWM1Gen2_IRQHandler   (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PWM1Gen3_IRQHandler   (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PWM1Fault_IRQHandler  (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*..........................................................................*/\n__attribute__ ((section(\".isr_vector\")))\nint const g_pfnVectors[] = {\n    /* Initial Vector Table before relocation */\n    (int)&__stack_end__,          /* Top of Stack                    */\n    (int)&Reset_Handler,          /* Reset Handler                   */\n    (int)&NMI_Handler,            /* NMI Handler                     */\n    (int)&HardFault_Handler,      /* Hard Fault Handler              */\n    (int)&MemManage_Handler,      /* The MPU fault handler           */\n    (int)&BusFault_Handler,       /* The bus fault handler           */\n    (int)&UsageFault_Handler,     /* The usage fault handler         */\n    (int)&Default_Handler,        /* Reserved                        */\n    (int)&Default_Handler,        /* Reserved                        */\n    (int)&Default_Handler,        /* Reserved                        */\n    (int)&Default_Handler,        /* Reserved                        */\n    (int)&SVC_Handler,            /* SVCall handler                  */\n    (int)&DebugMon_Handler,       /* Debug monitor handler           */\n    (int)&Default_Handler,        /* Reserved                        */\n    (int)&PendSV_Handler,         /* The PendSV handler              */\n    (int)&SysTick_Handler,        /* The SysTick handler             */\n    /* pad the initial VT to the total size of 256B */\n    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n\n    /* Relocated Vector Table beyond the 256B region around address 0.\n    * That region is used for NULL-pointer protection by the MPU.\n    */\n    (int)&__stack_end__,          /* Top of Stack                    */\n    (int)&Reset_Handler,          /* Reset Handler                   */\n    (int)&NMI_Handler,            /* NMI Handler                     */\n    (int)&HardFault_Handler,      /* Hard Fault Handler              */\n    (int)&MemManage_Handler,      /* The MPU fault handler           */\n    (int)&BusFault_Handler,       /* The bus fault handler           */\n    (int)&UsageFault_Handler,     /* The usage fault handler         */\n    (int)&Default_Handler,        /* Reserved                        */\n    (int)&Default_Handler,        /* Reserved                        */\n    (int)&Default_Handler,        /* Reserved                        */\n    (int)&Default_Handler,        /* Reserved                        */\n    (int)&SVC_Handler,            /* SVCall handler                  */\n    (int)&DebugMon_Handler,       /* Debug monitor handler           */\n    (int)&Default_Handler,        /* Reserved                        */\n    (int)&PendSV_Handler,         /* The PendSV handler              */\n    (int)&SysTick_Handler,        /* The SysTick handler             */\n\n    /*IRQ handlers... */\n    (int)&GPIOPortA_IRQHandler,   /* GPIO Port A                     */\n    (int)&GPIOPortB_IRQHandler,   /* GPIO Port B                     */\n    (int)&GPIOPortC_IRQHandler,   /* GPIO Port C                     */\n    (int)&GPIOPortD_IRQHandler,   /* GPIO Port D                     */\n    (int)&GPIOPortE_IRQHandler,   /* GPIO Port E                     */\n    (int)&UART0_IRQHandler,       /* UART0 Rx and Tx                 */\n    (int)&UART1_IRQHandler,       /* UART1 Rx and Tx                 */\n    (int)&SSI0_IRQHandler,        /* SSI0 Rx and Tx                  */\n    (int)&I2C0_IRQHandler,        /* I2C0 Master and Slave           */\n    (int)&PWMFault_IRQHandler,    /* PWM Fault                       */\n    (int)&PWMGen0_IRQHandler,     /* PWM Generator 0                 */\n    (int)&PWMGen1_IRQHandler,     /* PWM Generator 1                 */\n    (int)&PWMGen2_IRQHandler,     /* PWM Generator 2                 */\n    (int)&QEI0_IRQHandler,        /* Quadrature Encoder 0            */\n    (int)&ADCSeq0_IRQHandler,     /* ADC Sequence 0                  */\n    (int)&ADCSeq1_IRQHandler,     /* ADC Sequence 1                  */\n    (int)&ADCSeq2_IRQHandler,     /* ADC Sequence 2                  */\n    (int)&ADCSeq3_IRQHandler,     /* ADC Sequence 3                  */\n    (int)&Watchdog_IRQHandler,    /* Watchdog timer                  */\n    (int)&Timer0A_IRQHandler,     /* Timer 0 subtimer A              */\n    (int)&Timer0B_IRQHandler,     /* Timer 0 subtimer B              */\n    (int)&Timer1A_IRQHandler,     /* Timer 1 subtimer A              */\n    (int)&Timer1B_IRQHandler,     /* Timer 1 subtimer B              */\n    (int)&Timer2A_IRQHandler,     /* Timer 2 subtimer A              */\n    (int)&Timer2B_IRQHandler,     /* Timer 2 subtimer B              */\n    (int)&Comp0_IRQHandler,       /* Analog Comparator 0             */\n    (int)&Comp1_IRQHandler,       /* Analog Comparator 1             */\n    (int)&Comp2_IRQHandler,       /* Analog Comparator 2             */\n    (int)&SysCtrl_IRQHandler,     /* System Control (PLL, OSC, BO)   */\n    (int)&FlashCtrl_IRQHandler,   /* FLASH Control                   */\n    (int)&GPIOPortF_IRQHandler,   /* GPIO Port F                     */\n    (int)&GPIOPortG_IRQHandler,   /* GPIO Port G                     */\n    (int)&GPIOPortH_IRQHandler,   /* GPIO Port H                     */\n    (int)&UART2_IRQHandler,       /* UART2 Rx and Tx                 */\n    (int)&SSI1_IRQHandler,        /* SSI1 Rx and Tx                  */\n    (int)&Timer3A_IRQHandler,     /* Timer 3 subtimer A              */\n    (int)&Timer3B_IRQHandler,     /* Timer 3 subtimer B              */\n    (int)&I2C1_IRQHandler,        /* I2C1 Master and Slave           */\n    (int)&QEI1_IRQHandler,        /* Quadrature Encoder 1            */\n    (int)&CAN0_IRQHandler,        /* CAN0                            */\n    (int)&CAN1_IRQHandler,        /* CAN1                            */\n    (int)&CAN2_IRQHandler,        /* CAN2                            */\n    (int)&Default_Handler,        /* Reserved                        */\n    (int)&Hibernate_IRQHandler,   /* Hibernate                       */\n    (int)&USB0_IRQHandler,        /* USB0                            */\n    (int)&PWMGen3_IRQHandler,     /* PWM Generator 3                 */\n    (int)&uDMAST_IRQHandler,      /* uDMA Software Transfer          */\n    (int)&uDMAError_IRQHandler,   /* uDMA Error                      */\n    (int)&ADC1Seq0_IRQHandler,    /* ADC1 Sequence 0                 */\n    (int)&ADC1Seq1_IRQHandler,    /* ADC1 Sequence 1                 */\n    (int)&ADC1Seq2_IRQHandler,    /* ADC1 Sequence 2                 */\n    (int)&ADC1Seq3_IRQHandler,    /* ADC1 Sequence 3                 */\n    (int)&Default_Handler,        /* Reserved                        */\n    (int)&Default_Handler,        /* Reserved                        */\n    (int)&GPIOPortJ_IRQHandler,   /* GPIO Port J                     */\n    (int)&GPIOPortK_IRQHandler,   /* GPIO Port K                     */\n    (int)&GPIOPortL_IRQHandler,   /* GPIO Port L                     */\n    (int)&SSI2_IRQHandler,        /* SSI2 Rx and Tx                  */\n    (int)&SSI3_IRQHandler,        /* SSI3 Rx and Tx                  */\n    (int)&UART3_IRQHandler,       /* UART3 Rx and Tx                 */\n    (int)&UART4_IRQHandler,       /* UART4 Rx and Tx                 */\n    (int)&UART5_IRQHandler,       /* UART5 Rx and Tx                 */\n    (int)&UART6_IRQHandler,       /* UART6 Rx and Tx                 */\n    (int)&UART7_IRQHandler,       /* UART7 Rx and Tx                 */\n    (int)&Default_Handler,        /* Reserved                        */\n    (int)&Default_Handler,        /* Reserved                        */\n    (int)&Default_Handler,        /* Reserved                        */\n     (int)&Default_Handler,        /* Reserved                        */\n    (int)&I2C2_IRQHandler,        /* I2C2 Master and Slave           */\n    (int)&I2C3_IRQHandler,        /* I2C3 Master and Slave           */\n    (int)&Timer4A_IRQHandler,     /* Timer 4 subtimer A              */\n    (int)&Timer4B_IRQHandler,     /* Timer 4 subtimer B              */\n    (int)&Default_Handler,        /* Reserved                        */\n    (int)&Default_Handler,        /* Reserved                        */\n    (int)&Default_Handler,        /* Reserved                        */\n    (int)&Default_Handler,        /* Reserved                        */\n    (int)&Default_Handler,        /* Reserved                        */\n    (int)&Default_Handler,        /* Reserved                        */\n    (int)&Default_Handler,        /* Reserved                        */\n    (int)&Default_Handler,        /* Reserved                        */\n    (int)&Default_Handler,        /* Reserved                        */\n    (int)&Default_Handler,        /* Reserved                        */\n    (int)&Default_Handler,        /* Reserved                        */\n    (int)&Default_Handler,        /* Reserved                        */\n    (int)&Default_Handler,        /* Reserved                        */\n    (int)&Default_Handler,        /* Reserved                        */\n    (int)&Default_Handler,        /* Reserved                        */\n    (int)&Default_Handler,        /* Reserved                        */\n    (int)&Default_Handler,        /* Reserved                        */\n    (int)&Default_Handler,        /* Reserved                        */\n    (int)&Default_Handler,        /* Reserved                        */\n    (int)&Default_Handler,        /* Reserved                        */\n    (int)&Timer5A_IRQHandler,     /* Timer 5 subtimer A              */\n    (int)&Timer5B_IRQHandler,     /* Timer 5 subtimer B              */\n    (int)&WideTimer0A_IRQHandler, /* Wide Timer 0 subtimer A         */\n    (int)&WideTimer0B_IRQHandler, /* Wide Timer 0 subtimer B         */\n    (int)&WideTimer1A_IRQHandler, /* Wide Timer 1 subtimer A         */\n    (int)&WideTimer1B_IRQHandler, /* Wide Timer 1 subtimer B         */\n    (int)&WideTimer2A_IRQHandler, /* Wide Timer 2 subtimer A         */\n    (int)&WideTimer2B_IRQHandler, /* Wide Timer 2 subtimer B         */\n    (int)&WideTimer3A_IRQHandler, /* Wide Timer 3 subtimer A         */\n    (int)&WideTimer3B_IRQHandler, /* Wide Timer 3 subtimer B         */\n    (int)&WideTimer4A_IRQHandler, /* Wide Timer 4 subtimer A         */\n    (int)&WideTimer4B_IRQHandler, /* Wide Timer 4 subtimer B         */\n    (int)&WideTimer5A_IRQHandler, /* Wide Timer 5 subtimer A         */\n    (int)&WideTimer5B_IRQHandler, /* Wide Timer 5 subtimer B         */\n    (int)&FPU_IRQHandler,         /* FPU                             */\n    (int)&Default_Handler,        /* Reserved                        */\n    (int)&Default_Handler,        /* Reserved                        */\n    (int)&I2C4_IRQHandler,        /* I2C4 Master and Slave           */\n    (int)&I2C5_IRQHandler,        /* I2C5 Master and Slave           */\n    (int)&GPIOPortM_IRQHandler,   /* GPIO Port M                     */\n    (int)&GPIOPortN_IRQHandler,   /* GPIO Port N                     */\n    (int)&QEI2_IRQHandler,        /* Quadrature Encoder 2            */\n    (int)&Default_Handler,        /* Reserved                        */\n    (int)&Default_Handler,        /* Reserved                        */\n    (int)&GPIOPortP0_IRQHandler,  /* GPIO Port P (Summary or P0)     */\n    (int)&GPIOPortP1_IRQHandler,  /* GPIO Port P1                    */\n    (int)&GPIOPortP2_IRQHandler,  /* GPIO Port P2                    */\n    (int)&GPIOPortP3_IRQHandler,  /* GPIO Port P3                    */\n    (int)&GPIOPortP4_IRQHandler,  /* GPIO Port P4                    */\n    (int)&GPIOPortP5_IRQHandler,  /* GPIO Port P5                    */\n    (int)&GPIOPortP6_IRQHandler,  /* GPIO Port P6                    */\n    (int)&GPIOPortP7_IRQHandler,  /* GPIO Port P7                    */\n    (int)&GPIOPortQ0_IRQHandler,  /* GPIO Port Q (Summary or Q0)     */\n    (int)&GPIOPortQ1_IRQHandler,  /* GPIO Port Q1                    */\n    (int)&GPIOPortQ2_IRQHandler,  /* GPIO Port Q2                    */\n    (int)&GPIOPortQ3_IRQHandler,  /* GPIO Port Q3                    */\n    (int)&GPIOPortQ4_IRQHandler,  /* GPIO Port Q4                    */\n    (int)&GPIOPortQ5_IRQHandler,  /* GPIO Port Q5                    */\n    (int)&GPIOPortQ6_IRQHandler,  /* GPIO Port Q6                    */\n    (int)&GPIOPortQ7_IRQHandler,  /* GPIO Port Q7                    */\n    (int)&GPIOPortR_IRQHandler,   /* GPIO Port R                     */\n    (int)&GPIOPortS_IRQHandler,   /* GPIO Port S                     */\n    (int)&PWM1Gen0_IRQHandler,    /* PWM 1 Generator 0               */\n    (int)&PWM1Gen1_IRQHandler,    /* PWM 1 Generator 1               */\n    (int)&PWM1Gen2_IRQHandler,    /* PWM 1 Generator 2               */\n    (int)&PWM1Gen3_IRQHandler,    /* PWM 1 Generator 3               */\n    (int)&PWM1Fault_IRQHandler,   /* PWM 1 Fault                     */\n};\n\n\n/* reset handler -----------------------------------------------------------*/\n__attribute__((naked)) void Reset_Handler(void);\nvoid Reset_Handler(void) {\n    extern int main(void);\n    extern int __libc_init_array(void);\n    extern unsigned __data_start;  /* start of .data in the linker script */\n    extern unsigned __data_end__;  /* end of .data in the linker script */\n    extern unsigned const __data_load; /* initialization values for .data  */\n    extern unsigned __bss_start__; /* start of .bss in the linker script */\n    extern unsigned __bss_end__;   /* end of .bss in the linker script */\n    extern void software_init_hook(void) __attribute__((weak));\n\n    /* relocate the Vector Table to leave room for the NULL-pointer region\n    * System Control Block/Vector Table Offset Reg := relocated Vector Table\n    */\n    *(int const * volatile *)0xE000ED08 = &g_pfnVectors[256/sizeof(int)];\n\n    SystemInit(); /* CMSIS system initialization */\n\n    /* copy the data segment initializers from flash to RAM... */\n    unsigned const *src = &__data_load;\n    unsigned *dst;\n    for (dst = &__data_start; dst < &__data_end__; ++dst, ++src) {\n        *dst = *src;\n    }\n\n    /* zero fill the .bss segment in RAM... */\n    for (dst = &__bss_start__; dst < &__bss_end__; ++dst) {\n        *dst = 0;\n    }\n\n    /* init hook provided? */\n    if (&software_init_hook != (void (*)(void))(0)) {\n        /* give control to the RTOS */\n        software_init_hook(); /* this will also call __libc_init_array */\n    }\n    else {\n        /* call all static constructors in C++ (harmless in C programs) */\n        __libc_init_array();\n        (void)main(); /* application's entry point; should never return! */\n    }\n\n    /* the previous code should not return, but assert just in case... */\n    assert_failed(\"Reset_Handler\", 1U);\n}\n\n\n/* fault exception handlers ------------------------------------------------*/\n__attribute__((naked)) void NMI_Handler(void);\nvoid NMI_Handler(void) {\n    /* reset the SP to the initial value in case of stack overflow */\n    __asm volatile (\"  MOV  sp,%0\" : : \"r\" (&__stack_end__));\n    assert_failed(\"NMI_Handler\", 1U);\n}\n/*..........................................................................*/\n__attribute__((naked)) void HardFault_Handler(void);\nvoid HardFault_Handler(void) {\n    /* reset the SP to the initial value in case of stack overflow */\n    __asm volatile (\"  MOV  sp,%0\" : : \"r\" (&__stack_end__));\n    assert_failed(\"HardFault_Handler\", 1U);\n}\n/*..........................................................................*/\n__attribute__((naked)) void MemManage_Handler(void);\nvoid MemManage_Handler(void) {\n    /* reset the SP to the initial value in case of stack overflow */\n    __asm volatile (\"  MOV  sp,%0\" : : \"r\" (&__stack_end__));\n    assert_failed(\"MemManage_Handler\", 1U);\n}\n/*..........................................................................*/\n__attribute__((naked)) void BusFault_Handler(void);\nvoid BusFault_Handler(void) {\n    /* reset the SP to the initial value in case of stack overflow */\n    __asm volatile (\"  MOV  sp,%0\" : : \"r\" (&__stack_end__));\n    assert_failed(\"MemManage_Handler\", 1U);\n}\n/*..........................................................................*/\n__attribute__((naked)) void UsageFault_Handler(void);\nvoid UsageFault_Handler(void) {\n    /* reset the SP to the initial value in case of stack overflow */\n    __asm volatile (\"  MOV  sp,%0\" : : \"r\" (&__stack_end__));\n    assert_failed(\"BusFault_Handler\", 1U);\n}\n/*..........................................................................*/\n__attribute__((naked)) void Default_Handler(void);\nvoid Default_Handler(void) {\n    /* reset the SP to the initial value in case of stack overflow */\n    __asm volatile (\"  MOV  sp,%0\" : : \"r\" (&__stack_end__));\n    assert_failed(\"Default_Handler\", 1U);\n}\n"
  },
  {
    "path": "3rd_party/ek-tm4c123gxl/gpio.h",
    "content": "//============================================================================*\n//\n// gpio.h - Defines and Macros for GPIO API.\n//\n// Copyright (c) 2005-2015 Texas Instruments Incorporated.  All rights reserved.\n// Software License Agreement\n//\n//   Redistribution and use in source and binary forms, with or without\n//   modification, are permitted provided that the following conditions\n//   are met:\n//\n//   Redistributions of source code must retain the above copyright\n//   notice, this list of conditions and the following disclaimer.\n//\n//   Redistributions in binary form must reproduce the above copyright\n//   notice, this list of conditions and the following disclaimer in the\n//   documentation and/or other materials provided with the\n//   distribution.\n//\n//   Neither the name of Texas Instruments Incorporated nor the names of\n//   its contributors may be used to endorse or promote products derived\n//   from this software without specific prior written permission.\n//\n// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n// \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n//\n// This is part of revision 2.1.2.111 of the Tiva Peripheral Driver Library.\n//\n//============================================================================*\n\n#ifndef __DRIVERLIB_GPIO_H__\n#define __DRIVERLIB_GPIO_H__\n\n//============================================================================*\n//\n// If building with a C++ compiler, make all of the definitions in this header\n// have a C binding.\n//\n//============================================================================*\n#ifdef __cplusplus\nextern \"C\"\n{\n#endif\n\n//============================================================================*\n//\n// The following values define the bit field for the ui8Pins argument to\n// several of the APIs.\n//\n//============================================================================*\n#define GPIO_PIN_0              0x00000001  // GPIO pin 0\n#define GPIO_PIN_1              0x00000002  // GPIO pin 1\n#define GPIO_PIN_2              0x00000004  // GPIO pin 2\n#define GPIO_PIN_3              0x00000008  // GPIO pin 3\n#define GPIO_PIN_4              0x00000010  // GPIO pin 4\n#define GPIO_PIN_5              0x00000020  // GPIO pin 5\n#define GPIO_PIN_6              0x00000040  // GPIO pin 6\n#define GPIO_PIN_7              0x00000080  // GPIO pin 7\n\n//============================================================================*\n//\n// Values that can be passed to GPIODirModeSet as the ui32PinIO parameter, and\n// returned from GPIODirModeGet.\n//\n//============================================================================*\n#define GPIO_DIR_MODE_IN        0x00000000  // Pin is a GPIO input\n#define GPIO_DIR_MODE_OUT       0x00000001  // Pin is a GPIO output\n#define GPIO_DIR_MODE_HW        0x00000002  // Pin is a peripheral function\n\n//============================================================================*\n//\n// Values that can be passed to GPIOIntTypeSet as the ui32IntType parameter,\n// and returned from GPIOIntTypeGet.\n//\n//============================================================================*\n#define GPIO_FALLING_EDGE       0x00000000  // Interrupt on falling edge\n#define GPIO_RISING_EDGE        0x00000004  // Interrupt on rising edge\n#define GPIO_BOTH_EDGES         0x00000001  // Interrupt on both edges\n#define GPIO_LOW_LEVEL          0x00000002  // Interrupt on low level\n#define GPIO_HIGH_LEVEL         0x00000006  // Interrupt on high level\n#define GPIO_DISCRETE_INT       0x00010000  // Interrupt for individual pins\n\n//============================================================================*\n//\n// Values that can be passed to GPIOPadConfigSet as the ui32Strength parameter,\n// and returned by GPIOPadConfigGet in the *pui32Strength parameter.\n//\n//============================================================================*\n#define GPIO_STRENGTH_2MA       0x00000001  // 2mA drive strength\n#define GPIO_STRENGTH_4MA       0x00000002  // 4mA drive strength\n#define GPIO_STRENGTH_6MA       0x00000065  // 6mA drive strength\n#define GPIO_STRENGTH_8MA       0x00000066  // 8mA drive strength\n#define GPIO_STRENGTH_8MA_SC    0x0000006E  // 8mA drive with slew rate control\n#define GPIO_STRENGTH_10MA      0x00000075  // 10mA drive strength\n#define GPIO_STRENGTH_12MA      0x00000077  // 12mA drive strength\n\n//============================================================================*\n//\n// Values that can be passed to GPIOPadConfigSet as the ui32PadType parameter,\n// and returned by GPIOPadConfigGet in the *pui32PadType parameter.\n//\n//============================================================================*\n#define GPIO_PIN_TYPE_STD       0x00000008  // Push-pull\n#define GPIO_PIN_TYPE_STD_WPU   0x0000000A  // Push-pull with weak pull-up\n#define GPIO_PIN_TYPE_STD_WPD   0x0000000C  // Push-pull with weak pull-down\n#define GPIO_PIN_TYPE_OD        0x00000009  // Open-drain\n#define GPIO_PIN_TYPE_ANALOG    0x00000000  // Analog comparator\n#define GPIO_PIN_TYPE_WAKE_HIGH 0x00000208  // Hibernate wake, high\n#define GPIO_PIN_TYPE_WAKE_LOW  0x00000108  // Hibernate wake, low\n\n//============================================================================*\n//\n// Values that can be passed to GPIOIntEnable() and GPIOIntDisable() functions\n// in the ui32IntFlags parameter.\n//\n//============================================================================*\n#define GPIO_INT_PIN_0          0x00000001\n#define GPIO_INT_PIN_1          0x00000002\n#define GPIO_INT_PIN_2          0x00000004\n#define GPIO_INT_PIN_3          0x00000008\n#define GPIO_INT_PIN_4          0x00000010\n#define GPIO_INT_PIN_5          0x00000020\n#define GPIO_INT_PIN_6          0x00000040\n#define GPIO_INT_PIN_7          0x00000080\n#define GPIO_INT_DMA            0x00000100\n\n//============================================================================*\n//\n// Prototypes for the APIs.\n//\n//============================================================================*\nextern void GPIODirModeSet(uint32_t ui32Port, uint8_t ui8Pins,\n                           uint32_t ui32PinIO);\nextern uint32_t GPIODirModeGet(uint32_t ui32Port, uint8_t ui8Pin);\nextern void GPIOIntTypeSet(uint32_t ui32Port, uint8_t ui8Pins,\n                           uint32_t ui32IntType);\nextern uint32_t GPIOIntTypeGet(uint32_t ui32Port, uint8_t ui8Pin);\nextern void GPIOPadConfigSet(uint32_t ui32Port, uint8_t ui8Pins,\n                             uint32_t ui32Strength, uint32_t ui32PadType);\nextern void GPIOPadConfigGet(uint32_t ui32Port, uint8_t ui8Pin,\n                             uint32_t *pui32Strength, uint32_t *pui32PadType);\nextern void GPIOIntEnable(uint32_t ui32Port, uint32_t ui32IntFlags);\nextern void GPIOIntDisable(uint32_t ui32Port, uint32_t ui32IntFlags);\nextern uint32_t GPIOIntStatus(uint32_t ui32Port, bool bMasked);\nextern void GPIOIntClear(uint32_t ui32Port, uint32_t ui32IntFlags);\nextern void GPIOIntRegister(uint32_t ui32Port, void (*pfnIntHandler)(void));\nextern void GPIOIntUnregister(uint32_t ui32Port);\nextern int32_t GPIOPinRead(uint32_t ui32Port, uint8_t ui8Pins);\nextern void GPIOPinWrite(uint32_t ui32Port, uint8_t ui8Pins, uint8_t ui8Val);\nextern void GPIOPinConfigure(uint32_t ui32PinConfig);\nextern void GPIOPinTypeADC(uint32_t ui32Port, uint8_t ui8Pins);\nextern void GPIOPinTypeCAN(uint32_t ui32Port, uint8_t ui8Pins);\nextern void GPIOPinTypeComparator(uint32_t ui32Port, uint8_t ui8Pins);\nextern void GPIOPinTypeComparatorOutput(uint32_t ui32Port, uint8_t ui8Pins);\nextern void GPIOPinTypeDIVSCLK(uint32_t ui32Port, uint8_t ui8Pins);\nextern void GPIOPinTypeEPI(uint32_t ui32Port, uint8_t ui8Pins);\nextern void GPIOPinTypeEthernetLED(uint32_t ui32Port, uint8_t ui8Pins);\nextern void GPIOPinTypeEthernetMII(uint32_t ui32Port, uint8_t ui8Pins);\nextern void GPIOPinTypeGPIOInput(uint32_t ui32Port, uint8_t ui8Pins);\nextern void GPIOPinTypeGPIOOutput(uint32_t ui32Port, uint8_t ui8Pins);\nextern void GPIOPinTypeGPIOOutputOD(uint32_t ui32Port, uint8_t ui8Pins);\nextern void GPIOPinTypeHibernateRTCCLK(uint32_t ui32Port, uint8_t ui8Pins);\nextern void GPIOPinTypeI2C(uint32_t ui32Port, uint8_t ui8Pins);\nextern void GPIOPinTypeI2CSCL(uint32_t ui32Port, uint8_t ui8Pins);\nextern void GPIOPinTypeLCD(uint32_t ui32Port, uint8_t ui8Pins);\nextern void GPIOPinTypeOneWire(uint32_t ui32Port, uint8_t ui8Pins);\nextern void GPIOPinTypePWM(uint32_t ui32Port, uint8_t ui8Pins);\nextern void GPIOPinTypeQEI(uint32_t ui32Port, uint8_t ui8Pins);\nextern void GPIOPinTypeSSI(uint32_t ui32Port, uint8_t ui8Pins);\nextern void GPIOPinTypeTimer(uint32_t ui32Port, uint8_t ui8Pins);\nextern void GPIOPinTypeTrace(uint32_t ui32Port, uint8_t ui8Pins);\nextern void GPIOPinTypeUART(uint32_t ui32Port, uint8_t ui8Pins);\nextern void GPIOPinTypeUSBAnalog(uint32_t ui32Port, uint8_t ui8Pins);\nextern void GPIOPinTypeUSBDigital(uint32_t ui32Port, uint8_t ui8Pins);\nextern void GPIOPinTypeWakeHigh(uint32_t ui32Port, uint8_t ui8Pins);\nextern void GPIOPinTypeWakeLow(uint32_t ui32Port, uint8_t ui8Pins);\nextern uint32_t GPIOPinWakeStatus(uint32_t ui32Port);\nextern void GPIODMATriggerEnable(uint32_t ui32Port, uint8_t ui8Pins);\nextern void GPIODMATriggerDisable(uint32_t ui32Port, uint8_t ui8Pins);\nextern void GPIOADCTriggerEnable(uint32_t ui32Port, uint8_t ui8Pins);\nextern void GPIOADCTriggerDisable(uint32_t ui32Port, uint8_t ui8Pins);\n\n//============================================================================*\n//\n// Mark the end of the C bindings section for C++ compilers.\n//\n//============================================================================*\n#ifdef __cplusplus\n}\n#endif\n\n#endif // __DRIVERLIB_GPIO_H__\n"
  },
  {
    "path": "3rd_party/ek-tm4c123gxl/iar/startup_TM4C123GH6PM.s",
    "content": ";/***************************************************************************/\n; * @file     startup_TM4C123GH6PM.s for IAR ARM assembler\n; * @brief    CMSIS Cortex-M4F Core Device Startup File for TM4C123GH6PM\n; * @version  CMSIS 5.9.0\n; * @date     1 Feb 2023\n; *\n; * Modified by Quantum Leaps:\n; * - Added relocating of the Vector Table to free up the 256B region at 0x0\n; *   for NULL-pointer protection by the MPU.\n; * - Modified all exception handlers to branch to assert_failed()\n; *   instead of locking up the CPU inside an endless loop.\n; *\n; * @description\n; * Created from the CMSIS template for the specified device\n; * Quantum Leaps, www.state-machine.com\n; *\n\n        MODULE  ?cstartup\n\n        ; Forward declaration of sections.\n        SECTION CSTACK:DATA:NOROOT(3)\n\n        SECTION .intvec:CODE:NOROOT(8)\n\n        PUBLIC  __vector_table\n        PUBLIC  __Vectors\n        PUBLIC  __Vectors_End\n        PUBLIC  __Vectors_Size\n\n;******************************************************************************\n; The vector table.\n;\n        DATA\n__vector_table\n    ; Initial Vector Table before relocation\n        DCD     sfe(CSTACK)\n        DCD     Reset_Handler               ; Reset Handler\n        DCD     NMI_Handler                 ; NMI Handler\n        DCD     HardFault_Handler           ; Hard Fault Handler\n        DCD     MemManage_Handler           ; MPU fault handler\n        DCD     BusFault_Handler            ; Bus fault handler\n        DCD     UsageFault_Handler          ; Usage fault handler\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     SVC_Handler                 ; SVCall handler\n        DCD     DebugMon_Handler            ; Debug Monitor handler\n        DCD     Default_Handler             ; Reserved\n        DCD     PendSV_Handler              ; PendSV handler\n        DCD     SysTick_Handler             ; SysTick handler\n        ALIGNROM 8   ; Extend the initial Vector Table to the 2^8==256B\n\n    ; Relocated Vector Table beyond the 256B region around address 0.\n    ; That region is used for NULL-pointer protection by the MPU.\n__relocated_vector_table\n        DCD     sfe(CSTACK)\n        DCD     Reset_Handler               ; Reset Handler\n        DCD     NMI_Handler                 ; NMI Handler\n        DCD     HardFault_Handler           ; Hard Fault Handler\n        DCD     MemManage_Handler           ; MPU fault handler\n        DCD     BusFault_Handler            ; Bus fault handler\n        DCD     UsageFault_Handler          ; Usage fault handler\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     SVC_Handler                 ; SVCall handler\n        DCD     DebugMon_Handler            ; Debug Monitor handler\n        DCD     Default_Handler             ; Reserved\n        DCD     PendSV_Handler              ; PendSV handler\n        DCD     SysTick_Handler             ; SysTick handler\n\n        ; IRQ handlers...\n        DCD     GPIOPortA_IRQHandler        ; GPIO Port A\n        DCD     GPIOPortB_IRQHandler        ; GPIO Port B\n        DCD     GPIOPortC_IRQHandler        ; GPIO Port C\n        DCD     GPIOPortD_IRQHandler        ; GPIO Port D\n        DCD     GPIOPortE_IRQHandler        ; GPIO Port E\n        DCD     UART0_IRQHandler            ; UART0 Rx and Tx\n        DCD     UART1_IRQHandler            ; UART1 Rx and Tx\n        DCD     SSI0_IRQHandler             ; SSI0 Rx and Tx\n        DCD     I2C0_IRQHandler             ; I2C0 Master and Slave\n        DCD     PWMFault_IRQHandler         ; PWM Fault\n        DCD     PWMGen0_IRQHandler          ; PWM Generator 0\n        DCD     PWMGen1_IRQHandler          ; PWM Generator 1\n        DCD     PWMGen2_IRQHandler          ; PWM Generator 2\n        DCD     QEI0_IRQHandler             ; Quadrature Encoder 0\n        DCD     ADCSeq0_IRQHandler          ; ADC Sequence 0\n        DCD     ADCSeq1_IRQHandler          ; ADC Sequence 1\n        DCD     ADCSeq2_IRQHandler          ; ADC Sequence 2\n        DCD     ADCSeq3_IRQHandler          ; ADC Sequence 3\n        DCD     Watchdog_IRQHandler         ; Watchdog timer\n        DCD     Timer0A_IRQHandler          ; Timer 0 subtimer A\n        DCD     Timer0B_IRQHandler          ; Timer 0 subtimer B\n        DCD     Timer1A_IRQHandler          ; Timer 1 subtimer A\n        DCD     Timer1B_IRQHandler          ; Timer 1 subtimer B\n        DCD     Timer2A_IRQHandler          ; Timer 2 subtimer A\n        DCD     Timer2B_IRQHandler          ; Timer 2 subtimer B\n        DCD     Comp0_IRQHandler            ; Analog Comparator 0\n        DCD     Comp1_IRQHandler            ; Analog Comparator 1\n        DCD     Comp2_IRQHandler            ; Analog Comparator 2\n        DCD     SysCtrl_IRQHandler          ; System Control (PLL, OSC, BO)\n        DCD     FlashCtrl_IRQHandler        ; FLASH Control\n        DCD     GPIOPortF_IRQHandler        ; GPIO Port F\n        DCD     GPIOPortG_IRQHandler        ; GPIO Port G\n        DCD     GPIOPortH_IRQHandler        ; GPIO Port H\n        DCD     UART2_IRQHandler            ; UART2 Rx and Tx\n        DCD     SSI1_IRQHandler             ; SSI1 Rx and Tx\n        DCD     Timer3A_IRQHandler          ; Timer 3 subtimer A\n        DCD     Timer3B_IRQHandler          ; Timer 3 subtimer B\n        DCD     I2C1_IRQHandler             ; I2C1 Master and Slave\n        DCD     QEI1_IRQHandler             ; Quadrature Encoder 1\n        DCD     CAN0_IRQHandler             ; CAN0\n        DCD     CAN1_IRQHandler             ; CAN1\n        DCD     CAN2_IRQHandler             ; CAN2\n        DCD     Default_Handler             ; Reserved\n        DCD     Hibernate_IRQHandler        ; Hibernate\n        DCD     USB0_IRQHandler             ; USB0\n        DCD     PWMGen3_IRQHandler          ; PWM Generator 3\n        DCD     uDMAST_IRQHandler           ; uDMA Software Transfer\n        DCD     uDMAError_IRQHandler        ; uDMA Error\n        DCD     ADC1Seq0_IRQHandler         ; ADC1 Sequence 0\n        DCD     ADC1Seq1_IRQHandler         ; ADC1 Sequence 1\n        DCD     ADC1Seq2_IRQHandler         ; ADC1 Sequence 2\n        DCD     ADC1Seq3_IRQHandler         ; ADC1 Sequence 3\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     GPIOPortJ_IRQHandler        ; GPIO Port J\n        DCD     GPIOPortK_IRQHandler        ; GPIO Port K\n        DCD     GPIOPortL_IRQHandler        ; GPIO Port L\n        DCD     SSI2_IRQHandler             ; SSI2 Rx and Tx\n        DCD     SSI3_IRQHandler             ; SSI3 Rx and Tx\n        DCD     UART3_IRQHandler            ; UART3 Rx and Tx\n        DCD     UART4_IRQHandler            ; UART4 Rx and Tx\n        DCD     UART5_IRQHandler            ; UART5 Rx and Tx\n        DCD     UART6_IRQHandler            ; UART6 Rx and Tx\n        DCD     UART7_IRQHandler            ; UART7 Rx and Tx\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     I2C2_IRQHandler             ; I2C2 Master and Slave\n        DCD     I2C3_IRQHandler             ; I2C3 Master and Slave\n        DCD     Timer4A_IRQHandler          ; Timer 4 subtimer A\n        DCD     Timer4B_IRQHandler          ; Timer 4 subtimer B\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Timer5A_IRQHandler          ; Timer 5 subtimer A\n        DCD     Timer5B_IRQHandler          ; Timer 5 subtimer B\n        DCD     WideTimer0A_IRQHandler      ; Wide Timer 0 subtimer A\n        DCD     WideTimer0B_IRQHandler      ; Wide Timer 0 subtimer B\n        DCD     WideTimer1A_IRQHandler      ; Wide Timer 1 subtimer A\n        DCD     WideTimer1B_IRQHandler      ; Wide Timer 1 subtimer B\n        DCD     WideTimer2A_IRQHandler      ; Wide Timer 2 subtimer A\n        DCD     WideTimer2B_IRQHandler      ; Wide Timer 2 subtimer B\n        DCD     WideTimer3A_IRQHandler      ; Wide Timer 3 subtimer A\n        DCD     WideTimer3B_IRQHandler      ; Wide Timer 3 subtimer B\n        DCD     WideTimer4A_IRQHandler      ; Wide Timer 4 subtimer A\n        DCD     WideTimer4B_IRQHandler      ; Wide Timer 4 subtimer B\n        DCD     WideTimer5A_IRQHandler      ; Wide Timer 5 subtimer A\n        DCD     WideTimer5B_IRQHandler      ; Wide Timer 5 subtimer B\n        DCD     FPU_IRQHandler              ; FPU\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     I2C4_IRQHandler             ; I2C4 Master and Slave\n        DCD     I2C5_IRQHandler             ; I2C5 Master and Slave\n        DCD     GPIOPortM_IRQHandler        ; GPIO Port M\n        DCD     GPIOPortN_IRQHandler        ; GPIO Port N\n        DCD     QEI2_IRQHandler             ; Quadrature Encoder 2\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     GPIOPortP0_IRQHandler       ; GPIO Port P (Summary or P0)\n        DCD     GPIOPortP1_IRQHandler       ; GPIO Port P1\n        DCD     GPIOPortP2_IRQHandler       ; GPIO Port P2\n        DCD     GPIOPortP3_IRQHandler       ; GPIO Port P3\n        DCD     GPIOPortP4_IRQHandler       ; GPIO Port P4\n        DCD     GPIOPortP5_IRQHandler       ; GPIO Port P5\n        DCD     GPIOPortP6_IRQHandler       ; GPIO Port P6\n        DCD     GPIOPortP7_IRQHandler       ; GPIO Port P7\n        DCD     GPIOPortQ0_IRQHandler       ; GPIO Port Q (Summary or Q0)\n        DCD     GPIOPortQ1_IRQHandler       ; GPIO Port Q1\n        DCD     GPIOPortQ2_IRQHandler       ; GPIO Port Q2\n        DCD     GPIOPortQ3_IRQHandler       ; GPIO Port Q3\n        DCD     GPIOPortQ4_IRQHandler       ; GPIO Port Q4\n        DCD     GPIOPortQ5_IRQHandler       ; GPIO Port Q5\n        DCD     GPIOPortQ6_IRQHandler       ; GPIO Port Q6\n        DCD     GPIOPortQ7_IRQHandler       ; GPIO Port Q7\n        DCD     GPIOPortR_IRQHandler        ; GPIO Port R\n        DCD     GPIOPortS_IRQHandler        ; GPIO Port S\n        DCD     PWM1Gen0_IRQHandler         ; PWM 1 Generator 0\n        DCD     PWM1Gen1_IRQHandler         ; PWM 1 Generator 1\n        DCD     PWM1Gen2_IRQHandler         ; PWM 1 Generator 2\n        DCD     PWM1Gen3_IRQHandler         ; PWM 1 Generator 3\n        DCD     PWM1Fault_IRQHandler        ; PWM 1 Fault\n\n__Vectors_End\n\n__Vectors       EQU   __vector_table\n__Vectors_Size  EQU   __Vectors_End - __Vectors\n\n\n;******************************************************************************\n; This is the code for exception handlers.\n;\n        SECTION .text:CODE:REORDER:NOROOT(2)\n\n;******************************************************************************\n; This is the code that gets called when theessor first starts execution\n; following a reset event.\n;\n        PUBWEAK Reset_Handler\n        EXTERN  SystemInit\n        EXTERN  __iar_program_start\n        EXTERN  assert_failed\n\nReset_Handler\n        ; relocate the Vector Table\n        LDR     r0,=0xE000ED08  ; System Control Block/Vector Table Offset Reg\n        LDR     r1,=__relocated_vector_table\n        STR     r1,[r0]         ; SCB->VTOR := __relocated_vector_table\n\n        LDR     r0,=SystemInit  ; CMSIS system initialization\n        BLX     r0\n\n        ; pre-fill the CSTACK with 0xDEADBEEF...................\n        LDR     r0,=0xDEADBEEF\n        MOV     r1,r0\n        LDR     r2,=sfb(CSTACK)\n        LDR     r3,=sfe(CSTACK)\nReset_stackInit_fill:\n        STMIA   r2!,{r0,r1}\n        CMP     r2,r3\n        BLT.N   Reset_stackInit_fill\n\n        LDR     r0,=__iar_program_start ; IAR startup code\n        BLX     r0\n\n        ; __iar_program_start calls the main() function, which should not return,\n        ; but just in case jump to assert_failed() if main returns.\n        LDR     r0,=str_EXIT\n        MOVS    r1,#1\n        LDR     r2,=sfe(CSTACK)  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_EXIT\n        DCB     \"EXIT\"\n        ALIGNROM 2\n\n;******************************************************************************\n        PUBWEAK NMI_Handler\nNMI_Handler\n        LDR     r0,=str_NMI\n        MOVS    r1,#1\n        LDR     r2,=sfe(CSTACK)  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_NMI\n        DCB     \"NMI\"\n        ALIGNROM 2\n\n;******************************************************************************\n        PUBWEAK HardFault_Handler\nHardFault_Handler\n        LDR     r0,=str_HardFault\n        MOVS    r1,#1\n        LDR     r2,=sfe(CSTACK)  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_HardFault\n        DCB     \"HardFault\"\n        ALIGNROM 2\n\n;******************************************************************************\n        PUBWEAK MemManage_Handler\nMemManage_Handler\n        LDR     r0,=str_MemManage\n        MOVS    r1,#1\n        LDR     r2,=sfe(CSTACK)  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_MemManage\n        DCB     \"MemManage\"\n        ALIGNROM 2\n\n;******************************************************************************\n        PUBWEAK BusFault_Handler\nBusFault_Handler\n        LDR     r0,=str_BusFault\n        MOVS    r1,#1\n        LDR     r2,=sfe(CSTACK)  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_BusFault\n        DCB     \"BusFault\"\n        ALIGNROM 2\n\n;******************************************************************************\n        PUBWEAK UsageFault_Handler\nUsageFault_Handler\n        LDR     r0,=str_UsageFault\n        MOVS    r1,#1\n        LDR     r2,=sfe(CSTACK)  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_UsageFault\n        DCB     \"UsageFault\"\n        ALIGNROM 2\n\n;******************************************************************************\n;\n; Weak non-fault handlers...\n;\n\n;******************************************************************************\n        PUBWEAK SVC_Handler\nSVC_Handler\n        LDR     r0,=str_SVC\n        MOVS    r1,#1\n        LDR     r2,=sfe(CSTACK)  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_SVC\n        DCB     \"SVC\"\n        ALIGNROM 2\n\n;******************************************************************************\n        PUBWEAK DebugMon_Handler\nDebugMon_Handler\n        LDR     r0,=str_DebugMon\n        MOVS    r1,#1\n        LDR     r2,=sfe(CSTACK)  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_DebugMon\n        DCB     \"DebugMon\"\n        ALIGNROM 2\n\n;******************************************************************************\n        PUBWEAK PendSV_Handler\nPendSV_Handler\n        LDR     r0,=str_PendSV\n        MOVS    r1,#1\n        LDR     r2,=sfe(CSTACK)  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_PendSV\n        DCB     \"PendSV\"\n        ALIGNROM 2\n\n;******************************************************************************\n        PUBWEAK SysTick_Handler\nSysTick_Handler\n        LDR     r0,=str_SysTick\n        MOVS    r1,#1\n        LDR     r2,=sfe(CSTACK)  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_SysTick\n        DCB     \"SysTick\"\n        ALIGNROM 2\n\n;******************************************************************************\n; Weak IRQ handlers...\n;\n        PUBWEAK  Default_Handler\n        PUBWEAK  GPIOPortA_IRQHandler\n        PUBWEAK  GPIOPortB_IRQHandler\n        PUBWEAK  GPIOPortC_IRQHandler\n        PUBWEAK  GPIOPortD_IRQHandler\n        PUBWEAK  GPIOPortE_IRQHandler\n        PUBWEAK  UART0_IRQHandler\n        PUBWEAK  UART1_IRQHandler\n        PUBWEAK  SSI0_IRQHandler\n        PUBWEAK  I2C0_IRQHandler\n        PUBWEAK  PWMFault_IRQHandler\n        PUBWEAK  PWMGen0_IRQHandler\n        PUBWEAK  PWMGen1_IRQHandler\n        PUBWEAK  PWMGen2_IRQHandler\n        PUBWEAK  QEI0_IRQHandler\n        PUBWEAK  ADCSeq0_IRQHandler\n        PUBWEAK  ADCSeq1_IRQHandler\n        PUBWEAK  ADCSeq2_IRQHandler\n        PUBWEAK  ADCSeq3_IRQHandler\n        PUBWEAK  Watchdog_IRQHandler\n        PUBWEAK  Timer0A_IRQHandler\n        PUBWEAK  Timer0B_IRQHandler\n        PUBWEAK  Timer1A_IRQHandler\n        PUBWEAK  Timer1B_IRQHandler\n        PUBWEAK  Timer2A_IRQHandler\n        PUBWEAK  Timer2B_IRQHandler\n        PUBWEAK  Comp0_IRQHandler\n        PUBWEAK  Comp1_IRQHandler\n        PUBWEAK  Comp2_IRQHandler\n        PUBWEAK  SysCtrl_IRQHandler\n        PUBWEAK  FlashCtrl_IRQHandler\n        PUBWEAK  GPIOPortF_IRQHandler\n        PUBWEAK  GPIOPortG_IRQHandler\n        PUBWEAK  GPIOPortH_IRQHandler\n        PUBWEAK  UART2_IRQHandler\n        PUBWEAK  SSI1_IRQHandler\n        PUBWEAK  Timer3A_IRQHandler\n        PUBWEAK  Timer3B_IRQHandler\n        PUBWEAK  I2C1_IRQHandler\n        PUBWEAK  QEI1_IRQHandler\n        PUBWEAK  CAN0_IRQHandler\n        PUBWEAK  CAN1_IRQHandler\n        PUBWEAK  CAN2_IRQHandler\n        PUBWEAK  Hibernate_IRQHandler\n        PUBWEAK  USB0_IRQHandler\n        PUBWEAK  PWMGen3_IRQHandler\n        PUBWEAK  uDMAST_IRQHandler\n        PUBWEAK  uDMAError_IRQHandler\n        PUBWEAK  ADC1Seq0_IRQHandler\n        PUBWEAK  ADC1Seq1_IRQHandler\n        PUBWEAK  ADC1Seq2_IRQHandler\n        PUBWEAK  ADC1Seq3_IRQHandler\n        PUBWEAK  GPIOPortJ_IRQHandler\n        PUBWEAK  GPIOPortK_IRQHandler\n        PUBWEAK  GPIOPortL_IRQHandler\n        PUBWEAK  SSI2_IRQHandler\n        PUBWEAK  SSI3_IRQHandler\n        PUBWEAK  UART3_IRQHandler\n        PUBWEAK  UART4_IRQHandler\n        PUBWEAK  UART5_IRQHandler\n        PUBWEAK  UART6_IRQHandler\n        PUBWEAK  UART7_IRQHandler\n        PUBWEAK  I2C2_IRQHandler\n        PUBWEAK  I2C3_IRQHandler\n        PUBWEAK  Timer4A_IRQHandler\n        PUBWEAK  Timer4B_IRQHandler\n        PUBWEAK  Timer5A_IRQHandler\n        PUBWEAK  Timer5B_IRQHandler\n        PUBWEAK  WideTimer0A_IRQHandler\n        PUBWEAK  WideTimer0B_IRQHandler\n        PUBWEAK  WideTimer1A_IRQHandler\n        PUBWEAK  WideTimer1B_IRQHandler\n        PUBWEAK  WideTimer2A_IRQHandler\n        PUBWEAK  WideTimer2B_IRQHandler\n        PUBWEAK  WideTimer3A_IRQHandler\n        PUBWEAK  WideTimer3B_IRQHandler\n        PUBWEAK  WideTimer4A_IRQHandler\n        PUBWEAK  WideTimer4B_IRQHandler\n        PUBWEAK  WideTimer5A_IRQHandler\n        PUBWEAK  WideTimer5B_IRQHandler\n        PUBWEAK  FPU_IRQHandler\n        PUBWEAK  I2C4_IRQHandler\n        PUBWEAK  I2C5_IRQHandler\n        PUBWEAK  GPIOPortM_IRQHandler\n        PUBWEAK  GPIOPortN_IRQHandler\n        PUBWEAK  QEI2_IRQHandler\n        PUBWEAK  GPIOPortP0_IRQHandler\n        PUBWEAK  GPIOPortP1_IRQHandler\n        PUBWEAK  GPIOPortP2_IRQHandler\n        PUBWEAK  GPIOPortP3_IRQHandler\n        PUBWEAK  GPIOPortP4_IRQHandler\n        PUBWEAK  GPIOPortP5_IRQHandler\n        PUBWEAK  GPIOPortP6_IRQHandler\n        PUBWEAK  GPIOPortP7_IRQHandler\n        PUBWEAK  GPIOPortQ0_IRQHandler\n        PUBWEAK  GPIOPortQ1_IRQHandler\n        PUBWEAK  GPIOPortQ2_IRQHandler\n        PUBWEAK  GPIOPortQ3_IRQHandler\n        PUBWEAK  GPIOPortQ4_IRQHandler\n        PUBWEAK  GPIOPortQ5_IRQHandler\n        PUBWEAK  GPIOPortQ6_IRQHandler\n        PUBWEAK  GPIOPortQ7_IRQHandler\n        PUBWEAK  GPIOPortR_IRQHandler\n        PUBWEAK  GPIOPortS_IRQHandler\n        PUBWEAK  PWM1Gen0_IRQHandler\n        PUBWEAK  PWM1Gen1_IRQHandler\n        PUBWEAK  PWM1Gen2_IRQHandler\n        PUBWEAK  PWM1Gen3_IRQHandler\n        PUBWEAK  PWM1Fault_IRQHandler\n\nDefault_Handler\nGPIOPortA_IRQHandler\nGPIOPortB_IRQHandler\nGPIOPortC_IRQHandler\nGPIOPortD_IRQHandler\nGPIOPortE_IRQHandler\nUART0_IRQHandler\nUART1_IRQHandler\nSSI0_IRQHandler\nI2C0_IRQHandler\nPWMFault_IRQHandler\nPWMGen0_IRQHandler\nPWMGen1_IRQHandler\nPWMGen2_IRQHandler\nQEI0_IRQHandler\nADCSeq0_IRQHandler\nADCSeq1_IRQHandler\nADCSeq2_IRQHandler\nADCSeq3_IRQHandler\nWatchdog_IRQHandler\nTimer0A_IRQHandler\nTimer0B_IRQHandler\nTimer1A_IRQHandler\nTimer1B_IRQHandler\nTimer2A_IRQHandler\nTimer2B_IRQHandler\nComp0_IRQHandler\nComp1_IRQHandler\nComp2_IRQHandler\nSysCtrl_IRQHandler\nFlashCtrl_IRQHandler\nGPIOPortF_IRQHandler\nGPIOPortG_IRQHandler\nGPIOPortH_IRQHandler\nUART2_IRQHandler\nSSI1_IRQHandler\nTimer3A_IRQHandler\nTimer3B_IRQHandler\nI2C1_IRQHandler\nQEI1_IRQHandler\nCAN0_IRQHandler\nCAN1_IRQHandler\nCAN2_IRQHandler\nHibernate_IRQHandler\nUSB0_IRQHandler\nPWMGen3_IRQHandler\nuDMAST_IRQHandler\nuDMAError_IRQHandler\nADC1Seq0_IRQHandler\nADC1Seq1_IRQHandler\nADC1Seq2_IRQHandler\nADC1Seq3_IRQHandler\nGPIOPortJ_IRQHandler\nGPIOPortK_IRQHandler\nGPIOPortL_IRQHandler\nSSI2_IRQHandler\nSSI3_IRQHandler\nUART3_IRQHandler\nUART4_IRQHandler\nUART5_IRQHandler\nUART6_IRQHandler\nUART7_IRQHandler\nI2C2_IRQHandler\nI2C3_IRQHandler\nTimer4A_IRQHandler\nTimer4B_IRQHandler\nTimer5A_IRQHandler\nTimer5B_IRQHandler\nWideTimer0A_IRQHandler\nWideTimer0B_IRQHandler\nWideTimer1A_IRQHandler\nWideTimer1B_IRQHandler\nWideTimer2A_IRQHandler\nWideTimer2B_IRQHandler\nWideTimer3A_IRQHandler\nWideTimer3B_IRQHandler\nWideTimer4A_IRQHandler\nWideTimer4B_IRQHandler\nWideTimer5A_IRQHandler\nWideTimer5B_IRQHandler\nFPU_IRQHandler\nI2C4_IRQHandler\nI2C5_IRQHandler\nGPIOPortM_IRQHandler\nGPIOPortN_IRQHandler\nQEI2_IRQHandler\nGPIOPortP0_IRQHandler\nGPIOPortP1_IRQHandler\nGPIOPortP2_IRQHandler\nGPIOPortP3_IRQHandler\nGPIOPortP4_IRQHandler\nGPIOPortP5_IRQHandler\nGPIOPortP6_IRQHandler\nGPIOPortP7_IRQHandler\nGPIOPortQ0_IRQHandler\nGPIOPortQ1_IRQHandler\nGPIOPortQ2_IRQHandler\nGPIOPortQ3_IRQHandler\nGPIOPortQ4_IRQHandler\nGPIOPortQ5_IRQHandler\nGPIOPortQ6_IRQHandler\nGPIOPortQ7_IRQHandler\nGPIOPortR_IRQHandler\nGPIOPortS_IRQHandler\nPWM1Gen0_IRQHandler\nPWM1Gen1_IRQHandler\nPWM1Gen2_IRQHandler\nPWM1Gen3_IRQHandler\nPWM1Fault_IRQHandler\n        LDR     r0,=str_Undefined\n        MOVS    r1,#1\n        LDR     r2,=sfe(CSTACK)  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_Undefined\n        DCB     \"Undefined\"\n        ALIGNROM 2\n\n        END                     ; end of module\n\n"
  },
  {
    "path": "3rd_party/ek-tm4c123gxl/rom.h",
    "content": "//============================================================================*\n//\n// rom.h - Macros to facilitate calling functions in the ROM.\n//\n// Copyright (c) 2007-2015 Texas Instruments Incorporated.  All rights reserved.\n// Software License Agreement\n//\n//   Redistribution and use in source and binary forms, with or without\n//   modification, are permitted provided that the following conditions\n//   are met:\n//\n//   Redistributions of source code must retain the above copyright\n//   notice, this list of conditions and the following disclaimer.\n//\n//   Redistributions in binary form must reproduce the above copyright\n//   notice, this list of conditions and the following disclaimer in the\n//   documentation and/or other materials provided with the\n//   distribution.\n//\n//   Neither the name of Texas Instruments Incorporated nor the names of\n//   its contributors may be used to endorse or promote products derived\n//   from this software without specific prior written permission.\n//\n// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n// \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n//\n// This is part of revision 2.1.2.111 of the Tiva Peripheral Driver Library.\n//\n//============================================================================*\n\n#ifndef __DRIVERLIB_ROM_H__\n#define __DRIVERLIB_ROM_H__\n\n#ifndef DEPRECATED\n//============================================================================*\n//\n// ROM selection labels changed between TivaWare 2.0.1 and 2.1.  The following\n// labels are intended to ensure backwards compatibility for applications\n// which have not yet been updated to use the replacement labels.\n//\n//============================================================================*\n#ifdef TARGET_IS_SNOWFLAKE_RA0\n#define TARGET_IS_TM4C129_RA0\n#endif\n#ifdef TARGET_IS_SNOWFLAKE_RA1\n#define TARGET_IS_TM4C129_RA1\n#endif\n#ifdef TARGET_IS_SNOWFLAKE_RA2\n#define TARGET_IS_TM4C129_RA2\n#endif\n#ifdef TARGET_IS_BLIZZARD_RA1\n#define TARGET_IS_TM4C123_RA1\n#endif\n#ifdef TARGET_IS_BLIZZARD_RA2\n#define TARGET_IS_TM4C123_RA2\n#endif\n#ifdef TARGET_IS_BLIZZARD_RA3\n#define TARGET_IS_TM4C123_RA3\n#endif\n#ifdef TARGET_IS_BLIZZARD_RB0\n#define TARGET_IS_TM4C123_RB0\n#endif\n#ifdef TARGET_IS_BLIZZARD_RB1\n#define TARGET_IS_TM4C123_RB1\n#endif\n#endif\n\n//============================================================================*\n//\n// Pointers to the main API tables.\n//\n//============================================================================*\n#define ROM_APITABLE            ((uint32_t *)0x01000010)\n#define ROM_VERSION             (ROM_APITABLE[0])\n#define ROM_UARTTABLE           ((uint32_t *)(ROM_APITABLE[1]))\n#define ROM_SSITABLE            ((uint32_t *)(ROM_APITABLE[2]))\n#define ROM_I2CTABLE            ((uint32_t *)(ROM_APITABLE[3]))\n#define ROM_GPIOTABLE           ((uint32_t *)(ROM_APITABLE[4]))\n#define ROM_ADCTABLE            ((uint32_t *)(ROM_APITABLE[5]))\n#define ROM_COMPARATORTABLE     ((uint32_t *)(ROM_APITABLE[6]))\n#define ROM_FLASHTABLE          ((uint32_t *)(ROM_APITABLE[7]))\n#define ROM_PWMTABLE            ((uint32_t *)(ROM_APITABLE[8]))\n#define ROM_QEITABLE            ((uint32_t *)(ROM_APITABLE[9]))\n#define ROM_SYSTICKTABLE        ((uint32_t *)(ROM_APITABLE[10]))\n#define ROM_TIMERTABLE          ((uint32_t *)(ROM_APITABLE[11]))\n#define ROM_WATCHDOGTABLE       ((uint32_t *)(ROM_APITABLE[12]))\n#define ROM_SYSCTLTABLE         ((uint32_t *)(ROM_APITABLE[13]))\n#define ROM_INTERRUPTTABLE      ((uint32_t *)(ROM_APITABLE[14]))\n#define ROM_USBTABLE            ((uint32_t *)(ROM_APITABLE[16]))\n#define ROM_UDMATABLE           ((uint32_t *)(ROM_APITABLE[17]))\n#define ROM_CANTABLE            ((uint32_t *)(ROM_APITABLE[18]))\n#define ROM_HIBERNATETABLE      ((uint32_t *)(ROM_APITABLE[19]))\n#define ROM_MPUTABLE            ((uint32_t *)(ROM_APITABLE[20]))\n#define ROM_SOFTWARETABLE       ((uint32_t *)(ROM_APITABLE[21]))\n#define ROM_EPITABLE            ((uint32_t *)(ROM_APITABLE[23]))\n#define ROM_EEPROMTABLE         ((uint32_t *)(ROM_APITABLE[24]))\n#define ROM_FPUTABLE            ((uint32_t *)(ROM_APITABLE[26]))\n#define ROM_SMBUSTABLE          ((uint32_t *)(ROM_APITABLE[29]))\n#define ROM_SYSEXCTABLE         ((uint32_t *)(ROM_APITABLE[30]))\n#define ROM_ONEWIRETABLE        ((uint32_t *)(ROM_APITABLE[34]))\n#define ROM_SPIFLASHTABLE       ((uint32_t *)(ROM_APITABLE[38]))\n#define ROM_LCDTABLE            ((uint32_t *)(ROM_APITABLE[41]))\n#define ROM_EMACTABLE           ((uint32_t *)(ROM_APITABLE[42]))\n#define ROM_AESTABLE            ((uint32_t *)(ROM_APITABLE[43]))\n#define ROM_CRCTABLE            ((uint32_t *)(ROM_APITABLE[44]))\n#define ROM_DESTABLE            ((uint32_t *)(ROM_APITABLE[45]))\n#define ROM_SHAMD5TABLE         ((uint32_t *)(ROM_APITABLE[46]))\n\n//============================================================================*\n//\n// Macros for calling ROM functions in the ADC API.\n//\n//============================================================================*\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_ADCSequenceDataGet                                                \\\n        ((int32_t (*)(uint32_t ui32Base,                                      \\\n                      uint32_t ui32SequenceNum,                               \\\n                      uint32_t *pui32Buffer))ROM_ADCTABLE[0])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_ADCIntDisable                                                     \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32SequenceNum))ROM_ADCTABLE[1])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_ADCIntEnable                                                      \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32SequenceNum))ROM_ADCTABLE[2])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_ADCIntStatus                                                      \\\n        ((uint32_t (*)(uint32_t ui32Base,                                     \\\n                       uint32_t ui32SequenceNum,                              \\\n                       bool bMasked))ROM_ADCTABLE[3])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_ADCIntClear                                                       \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32SequenceNum))ROM_ADCTABLE[4])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_ADCSequenceEnable                                                 \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32SequenceNum))ROM_ADCTABLE[5])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_ADCSequenceDisable                                                \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32SequenceNum))ROM_ADCTABLE[6])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_ADCSequenceConfigure                                              \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32SequenceNum,                                  \\\n                   uint32_t ui32Trigger,                                      \\\n                   uint32_t ui32Priority))ROM_ADCTABLE[7])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_ADCSequenceStepConfigure                                          \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32SequenceNum,                                  \\\n                   uint32_t ui32Step,                                         \\\n                   uint32_t ui32Config))ROM_ADCTABLE[8])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_ADCSequenceOverflow                                               \\\n        ((int32_t (*)(uint32_t ui32Base,                                      \\\n                      uint32_t ui32SequenceNum))ROM_ADCTABLE[9])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_ADCSequenceOverflowClear                                          \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32SequenceNum))ROM_ADCTABLE[10])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_ADCSequenceUnderflow                                              \\\n        ((int32_t (*)(uint32_t ui32Base,                                      \\\n                      uint32_t ui32SequenceNum))ROM_ADCTABLE[11])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_ADCSequenceUnderflowClear                                         \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32SequenceNum))ROM_ADCTABLE[12])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_ADCProcessorTrigger                                               \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32SequenceNum))ROM_ADCTABLE[13])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_ADCHardwareOversampleConfigure                                    \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Factor))ROM_ADCTABLE[14])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_ADCComparatorConfigure                                            \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Comp,                                         \\\n                   uint32_t ui32Config))ROM_ADCTABLE[15])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_ADCComparatorRegionSet                                            \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Comp,                                         \\\n                   uint32_t ui32LowRef,                                       \\\n                   uint32_t ui32HighRef))ROM_ADCTABLE[16])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_ADCComparatorReset                                                \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Comp,                                         \\\n                   bool bTrigger,                                             \\\n                   bool bInterrupt))ROM_ADCTABLE[17])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_ADCComparatorIntDisable                                           \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32SequenceNum))ROM_ADCTABLE[18])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_ADCComparatorIntEnable                                            \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32SequenceNum))ROM_ADCTABLE[19])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_ADCComparatorIntStatus                                            \\\n        ((uint32_t (*)(uint32_t ui32Base))ROM_ADCTABLE[20])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_ADCComparatorIntClear                                             \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Status))ROM_ADCTABLE[21])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_ADCReferenceSet                                                   \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Ref))ROM_ADCTABLE[22])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_ADCReferenceGet                                                   \\\n        ((uint32_t (*)(uint32_t ui32Base))ROM_ADCTABLE[23])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_ADCPhaseDelaySet                                                  \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Phase))ROM_ADCTABLE[24])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_ADCPhaseDelayGet                                                  \\\n        ((uint32_t (*)(uint32_t ui32Base))ROM_ADCTABLE[25])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_ADCIntDisableEx                                                   \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32IntFlags))ROM_ADCTABLE[29])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_ADCIntEnableEx                                                    \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32IntFlags))ROM_ADCTABLE[30])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_ADCIntStatusEx                                                    \\\n        ((uint32_t (*)(uint32_t ui32Base,                                     \\\n                       bool bMasked))ROM_ADCTABLE[31])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_ADCSequenceDMAEnable                                              \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32SequenceNum))ROM_ADCTABLE[32])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_ADCSequenceDMADisable                                             \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32SequenceNum))ROM_ADCTABLE[33])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_ADCBusy                                                           \\\n        ((bool (*)(uint32_t ui32Base))ROM_ADCTABLE[34])\n#endif\n\n//============================================================================*\n//\n// Macros for calling ROM functions in the AES API.\n//\n//============================================================================*\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_AESIntStatus                                                      \\\n        ((uint32_t (*)(uint32_t ui32Base,                                     \\\n                       bool bMasked))ROM_AESTABLE[0])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_AESAuthLengthSet                                                  \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Length))ROM_AESTABLE[1])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_AESConfigSet                                                      \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Config))ROM_AESTABLE[2])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_AESDataAuth                                                       \\\n        ((bool (*)(uint32_t ui32Base,                                         \\\n                   uint32_t *pui32Src,                                        \\\n                   uint32_t ui32Length,                                       \\\n                   uint32_t *pui32Tag))ROM_AESTABLE[3])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_AESDataProcess                                                    \\\n        ((bool (*)(uint32_t ui32Base,                                         \\\n                   uint32_t *pui32Src,                                        \\\n                   uint32_t *pui32Dest,                                       \\\n                   uint32_t ui32Length))ROM_AESTABLE[4])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_AESDataProcessAuth                                                \\\n        ((bool (*)(uint32_t ui32Base,                                         \\\n                   uint32_t *pui32Src,                                        \\\n                   uint32_t *pui32Dest,                                       \\\n                   uint32_t ui32Length,                                       \\\n                   uint32_t *pui32AuthSrc,                                    \\\n                   uint32_t ui32AuthLength,                                   \\\n                   uint32_t *pui32Tag))ROM_AESTABLE[5])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_AESDataRead                                                       \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t *pui32Dest))ROM_AESTABLE[6])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_AESDataReadNonBlocking                                            \\\n        ((bool (*)(uint32_t ui32Base,                                         \\\n                   uint32_t *pui32Dest))ROM_AESTABLE[7])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_AESDataWrite                                                      \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t *pui32Src))ROM_AESTABLE[8])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_AESDataWriteNonBlocking                                           \\\n        ((bool (*)(uint32_t ui32Base,                                         \\\n                   uint32_t *pui32Src))ROM_AESTABLE[9])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_AESDMADisable                                                     \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Flags))ROM_AESTABLE[10])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_AESDMAEnable                                                      \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Flags))ROM_AESTABLE[11])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_AESIntClear                                                       \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32IntFlags))ROM_AESTABLE[12])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_AESIntDisable                                                     \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32IntFlags))ROM_AESTABLE[13])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_AESIntEnable                                                      \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32IntFlags))ROM_AESTABLE[14])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_AESIVSet                                                          \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t *pui32IVdata))ROM_AESTABLE[15])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_AESKey1Set                                                        \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t *pui32Key,                                        \\\n                   uint32_t ui32Keysize))ROM_AESTABLE[16])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_AESKey2Set                                                        \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t *pui32Key,                                        \\\n                   uint32_t ui32Keysize))ROM_AESTABLE[17])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_AESKey3Set                                                        \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t *pui32Key))ROM_AESTABLE[18])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_AESLengthSet                                                      \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint64_t ui64Length))ROM_AESTABLE[19])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_AESReset                                                          \\\n        ((void (*)(uint32_t ui32Base))ROM_AESTABLE[20])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_AESTagRead                                                        \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t *pui32TagData))ROM_AESTABLE[21])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_AESIVRead                                                         \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t *pui32IVdata))ROM_AESTABLE[22])\n#endif\n\n//============================================================================*\n//\n// Macros for calling ROM functions in the CAN API.\n//\n//============================================================================*\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_CANIntClear                                                       \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32IntClr))ROM_CANTABLE[0])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_CANInit                                                           \\\n        ((void (*)(uint32_t ui32Base))ROM_CANTABLE[1])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_CANEnable                                                         \\\n        ((void (*)(uint32_t ui32Base))ROM_CANTABLE[2])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_CANDisable                                                        \\\n        ((void (*)(uint32_t ui32Base))ROM_CANTABLE[3])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_CANBitTimingSet                                                   \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   tCANBitClkParms *psClkParms))ROM_CANTABLE[4])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_CANBitTimingGet                                                   \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   tCANBitClkParms *psClkParms))ROM_CANTABLE[5])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_CANMessageSet                                                     \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32ObjID,                                        \\\n                   tCANMsgObject *psMsgObject,                                \\\n                   tMsgObjType eMsgType))ROM_CANTABLE[6])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_CANMessageGet                                                     \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32ObjID,                                        \\\n                   tCANMsgObject *psMsgObject,                                \\\n                   bool bClrPendingInt))ROM_CANTABLE[7])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_CANStatusGet                                                      \\\n        ((uint32_t (*)(uint32_t ui32Base,                                     \\\n                       tCANStsReg eStatusReg))ROM_CANTABLE[8])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_CANMessageClear                                                   \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32ObjID))ROM_CANTABLE[9])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_CANIntEnable                                                      \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32IntFlags))ROM_CANTABLE[10])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_CANIntDisable                                                     \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32IntFlags))ROM_CANTABLE[11])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_CANIntStatus                                                      \\\n        ((uint32_t (*)(uint32_t ui32Base,                                     \\\n                       tCANIntStsReg eIntStsReg))ROM_CANTABLE[12])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_CANRetryGet                                                       \\\n        ((bool (*)(uint32_t ui32Base))ROM_CANTABLE[13])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_CANRetrySet                                                       \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   bool bAutoRetry))ROM_CANTABLE[14])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_CANErrCntrGet                                                     \\\n        ((bool (*)(uint32_t ui32Base,                                         \\\n                   uint32_t *pui32RxCount,                                    \\\n                   uint32_t *pui32TxCount))ROM_CANTABLE[15])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_CANBitRateSet                                                     \\\n        ((uint32_t (*)(uint32_t ui32Base,                                     \\\n                       uint32_t ui32SourceClock,                              \\\n                       uint32_t ui32BitRate))ROM_CANTABLE[16])\n#endif\n\n//============================================================================*\n//\n// Macros for calling ROM functions in the Comparator API.\n//\n//============================================================================*\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_ComparatorIntClear                                                \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Comp))ROM_COMPARATORTABLE[0])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_ComparatorConfigure                                               \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Comp,                                         \\\n                   uint32_t ui32Config))ROM_COMPARATORTABLE[1])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_ComparatorRefSet                                                  \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Ref))ROM_COMPARATORTABLE[2])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_ComparatorValueGet                                                \\\n        ((bool (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Comp))ROM_COMPARATORTABLE[3])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_ComparatorIntEnable                                               \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Comp))ROM_COMPARATORTABLE[4])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_ComparatorIntDisable                                              \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Comp))ROM_COMPARATORTABLE[5])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_ComparatorIntStatus                                               \\\n        ((bool (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Comp,                                         \\\n                   bool bMasked))ROM_COMPARATORTABLE[6])\n#endif\n\n//============================================================================*\n//\n// Macros for calling ROM functions in the CRC API.\n//\n//============================================================================*\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_CRCConfigSet                                                      \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32CRCConfig))ROM_CRCTABLE[0])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_CRCDataProcess                                                    \\\n        ((uint32_t (*)(uint32_t ui32Base,                                     \\\n                       uint32_t *pui32DataIn,                                 \\\n                       uint32_t ui32DataLength,                               \\\n                       bool bPPResult))ROM_CRCTABLE[1])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_CRCDataWrite                                                      \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Data))ROM_CRCTABLE[2])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_CRCResultRead                                                     \\\n        ((uint32_t (*)(uint32_t ui32Base,                                     \\\n                       bool bPPResult))ROM_CRCTABLE[3])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_CRCSeedSet                                                        \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Seed))ROM_CRCTABLE[4])\n#endif\n\n//============================================================================*\n//\n// Macros for calling ROM functions in the DES API.\n//\n//============================================================================*\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_DESIntStatus                                                      \\\n        ((uint32_t (*)(uint32_t ui32Base,                                     \\\n                       bool bMasked))ROM_DESTABLE[0])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_DESConfigSet                                                      \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Config))ROM_DESTABLE[1])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_DESDataRead                                                       \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t *pui32Dest))ROM_DESTABLE[2])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_DESDataReadNonBlocking                                            \\\n        ((bool (*)(uint32_t ui32Base,                                         \\\n                   uint32_t *pui32Dest))ROM_DESTABLE[3])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_DESDataProcess                                                    \\\n        ((bool (*)(uint32_t ui32Base,                                         \\\n                   uint32_t *pui32Src,                                        \\\n                   uint32_t *pui32Dest,                                       \\\n                   uint32_t ui32Length))ROM_DESTABLE[4])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_DESDataWrite                                                      \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t *pui32Src))ROM_DESTABLE[5])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_DESDataWriteNonBlocking                                           \\\n        ((bool (*)(uint32_t ui32Base,                                         \\\n                   uint32_t *pui32Src))ROM_DESTABLE[6])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_DESDMADisable                                                     \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Flags))ROM_DESTABLE[7])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_DESDMAEnable                                                      \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Flags))ROM_DESTABLE[8])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_DESIntClear                                                       \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32IntFlags))ROM_DESTABLE[9])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_DESIntDisable                                                     \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32IntFlags))ROM_DESTABLE[10])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_DESIntEnable                                                      \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32IntFlags))ROM_DESTABLE[11])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_DESIVSet                                                          \\\n        ((bool (*)(uint32_t ui32Base,                                         \\\n                   uint32_t *pui32IVdata))ROM_DESTABLE[12])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_DESKeySet                                                         \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t *pui32Key))ROM_DESTABLE[13])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_DESLengthSet                                                      \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Length))ROM_DESTABLE[14])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_DESReset                                                          \\\n        ((void (*)(uint32_t ui32Base))ROM_DESTABLE[15])\n#endif\n\n//============================================================================*\n//\n// Macros for calling ROM functions in the EEPROM API.\n//\n//============================================================================*\n#if defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EEPROMRead                                                        \\\n        ((void (*)(uint32_t *pui32Data,                                       \\\n                   uint32_t ui32Address,                                      \\\n                   uint32_t ui32Count))ROM_EEPROMTABLE[0])\n#endif\n#if defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EEPROMBlockCountGet                                               \\\n        ((uint32_t (*)(void))ROM_EEPROMTABLE[1])\n#endif\n#if defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EEPROMBlockHide                                                   \\\n        ((void (*)(uint32_t ui32Block))ROM_EEPROMTABLE[2])\n#endif\n#if defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EEPROMBlockLock                                                   \\\n        ((uint32_t (*)(uint32_t ui32Block))ROM_EEPROMTABLE[3])\n#endif\n#if defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EEPROMBlockPasswordSet                                            \\\n        ((uint32_t (*)(uint32_t ui32Block,                                    \\\n                       uint32_t *pui32Password,                               \\\n                       uint32_t ui32Count))ROM_EEPROMTABLE[4])\n#endif\n#if defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EEPROMBlockProtectGet                                             \\\n        ((uint32_t (*)(uint32_t ui32Block))ROM_EEPROMTABLE[5])\n#endif\n#if defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EEPROMBlockProtectSet                                             \\\n        ((uint32_t (*)(uint32_t ui32Block,                                    \\\n                       uint32_t ui32Protect))ROM_EEPROMTABLE[6])\n#endif\n#if defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EEPROMBlockUnlock                                                 \\\n        ((uint32_t (*)(uint32_t ui32Block,                                    \\\n                       uint32_t *pui32Password,                               \\\n                       uint32_t ui32Count))ROM_EEPROMTABLE[7])\n#endif\n#if defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EEPROMIntClear                                                    \\\n        ((void (*)(uint32_t ui32IntFlags))ROM_EEPROMTABLE[8])\n#endif\n#if defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EEPROMIntDisable                                                  \\\n        ((void (*)(uint32_t ui32IntFlags))ROM_EEPROMTABLE[9])\n#endif\n#if defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EEPROMIntEnable                                                   \\\n        ((void (*)(uint32_t ui32IntFlags))ROM_EEPROMTABLE[10])\n#endif\n#if defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EEPROMIntStatus                                                   \\\n        ((uint32_t (*)(bool bMasked))ROM_EEPROMTABLE[11])\n#endif\n#if defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1)\n#define ROM_EEPROMMassErase                                                   \\\n        ((uint32_t (*)(void))ROM_EEPROMTABLE[12])\n#endif\n#if defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EEPROMProgram                                                     \\\n        ((uint32_t (*)(uint32_t *pui32Data,                                   \\\n                       uint32_t ui32Address,                                  \\\n                       uint32_t ui32Count))ROM_EEPROMTABLE[13])\n#endif\n#if defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EEPROMProgramNonBlocking                                          \\\n        ((uint32_t (*)(uint32_t ui32Data,                                     \\\n                       uint32_t ui32Address))ROM_EEPROMTABLE[14])\n#endif\n#if defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EEPROMSizeGet                                                     \\\n        ((uint32_t (*)(void))ROM_EEPROMTABLE[15])\n#endif\n#if defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EEPROMStatusGet                                                   \\\n        ((uint32_t (*)(void))ROM_EEPROMTABLE[16])\n#endif\n#if defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EEPROMInit                                                        \\\n        ((uint32_t (*)(void))ROM_EEPROMTABLE[17])\n#endif\n\n//============================================================================*\n//\n// Macros for calling ROM functions in the EPI API.\n//\n//============================================================================*\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EPIIntStatus                                                      \\\n        ((uint32_t (*)(uint32_t ui32Base,                                     \\\n                       bool bMasked))ROM_EPITABLE[0])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EPIModeSet                                                        \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Mode))ROM_EPITABLE[1])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EPIDividerSet                                                     \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Divider))ROM_EPITABLE[2])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EPIConfigSDRAMSet                                                 \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Config,                                       \\\n                   uint32_t ui32Refresh))ROM_EPITABLE[3])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EPIConfigGPModeSet                                                \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Config,                                       \\\n                   uint32_t ui32FrameCount,                                   \\\n                   uint32_t ui32MaxWait))ROM_EPITABLE[4])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EPIConfigHB8Set                                                   \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Config,                                       \\\n                   uint32_t ui32MaxWait))ROM_EPITABLE[5])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EPIConfigHB16Set                                                  \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Config,                                       \\\n                   uint32_t ui32MaxWait))ROM_EPITABLE[6])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EPIAddressMapSet                                                  \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Map))ROM_EPITABLE[7])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EPINonBlockingReadConfigure                                       \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Channel,                                      \\\n                   uint32_t ui32DataSize,                                     \\\n                   uint32_t ui32Address))ROM_EPITABLE[8])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EPINonBlockingReadStart                                           \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Channel,                                      \\\n                   uint32_t ui32Count))ROM_EPITABLE[9])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EPINonBlockingReadStop                                            \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Channel))ROM_EPITABLE[10])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EPINonBlockingReadCount                                           \\\n        ((uint32_t (*)(uint32_t ui32Base,                                     \\\n                       uint32_t ui32Channel))ROM_EPITABLE[11])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EPINonBlockingReadAvail                                           \\\n        ((uint32_t (*)(uint32_t ui32Base))ROM_EPITABLE[12])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EPINonBlockingReadGet32                                           \\\n        ((uint32_t (*)(uint32_t ui32Base,                                     \\\n                       uint32_t ui32Count,                                    \\\n                       uint32_t *pui32Buf))ROM_EPITABLE[13])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EPINonBlockingReadGet16                                           \\\n        ((uint32_t (*)(uint32_t ui32Base,                                     \\\n                       uint32_t ui32Count,                                    \\\n                       uint16_t *pui16Buf))ROM_EPITABLE[14])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EPINonBlockingReadGet8                                            \\\n        ((uint32_t (*)(uint32_t ui32Base,                                     \\\n                       uint32_t ui32Count,                                    \\\n                       uint8_t *pui8Buf))ROM_EPITABLE[15])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EPIFIFOConfig                                                     \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Config))ROM_EPITABLE[16])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EPIWriteFIFOCountGet                                              \\\n        ((uint32_t (*)(uint32_t ui32Base))ROM_EPITABLE[17])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EPIIntEnable                                                      \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32IntFlags))ROM_EPITABLE[18])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EPIIntDisable                                                     \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32IntFlags))ROM_EPITABLE[19])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EPIIntErrorStatus                                                 \\\n        ((uint32_t (*)(uint32_t ui32Base))ROM_EPITABLE[20])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EPIIntErrorClear                                                  \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32ErrFlags))ROM_EPITABLE[21])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EPIDividerCSSet                                                   \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32CS,                                           \\\n                   uint32_t ui32Divider))ROM_EPITABLE[22])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EPIDMATxCount                                                     \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Count))ROM_EPITABLE[23])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EPIConfigHB8CSSet                                                 \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32CS,                                           \\\n                   uint32_t ui32Config))ROM_EPITABLE[24])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EPIConfigHB16CSSet                                                \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32CS,                                           \\\n                   uint32_t ui32Config))ROM_EPITABLE[25])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EPIConfigHB8TimingSet                                             \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32CS,                                           \\\n                   uint32_t ui32Config))ROM_EPITABLE[26])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EPIConfigHB16TimingSet                                            \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32CS,                                           \\\n                   uint32_t ui32Config))ROM_EPITABLE[27])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EPIPSRAMConfigRegSet                                              \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32CS,                                           \\\n                   uint32_t ui32CR))ROM_EPITABLE[28])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EPIPSRAMConfigRegRead                                             \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32CS))ROM_EPITABLE[29])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EPIPSRAMConfigRegGetNonBlocking                                   \\\n        ((bool (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32CS,                                           \\\n                   uint32_t *pui32CR))ROM_EPITABLE[30])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EPIPSRAMConfigRegGet                                              \\\n        ((uint32_t (*)(uint32_t ui32Base,                                     \\\n                       uint32_t ui32CS))ROM_EPITABLE[31])\n#endif\n\n//============================================================================*\n//\n// Macros for calling ROM functions in the EMAC API.\n//\n//============================================================================*\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACIntStatus                                                     \\\n        ((uint32_t (*)(uint32_t ui32Base,                                     \\\n                       bool bMasked))ROM_EMACTABLE[0])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACAddrGet                                                       \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Index,                                        \\\n                   uint8_t *pui8MACAddr))ROM_EMACTABLE[1])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACAddrSet                                                       \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Index,                                        \\\n                   const uint8_t *pui8MACAddr))ROM_EMACTABLE[2])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACConfigGet                                                     \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t *pui32Config,                                     \\\n                   uint32_t *pui32Mode,                                       \\\n                   uint32_t *pui32RxMaxFrameSize))ROM_EMACTABLE[3])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACConfigSet                                                     \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Config,                                       \\\n                   uint32_t ui32ModeFlags,                                    \\\n                   uint32_t ui32RxMaxFrameSize))ROM_EMACTABLE[4])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACDMAStateGet                                                   \\\n        ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[5])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACFrameFilterGet                                                \\\n        ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[6])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACFrameFilterSet                                                \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32FilterOpts))ROM_EMACTABLE[7])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACInit                                                          \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32SysClk,                                       \\\n                   uint32_t ui32BusConfig,                                    \\\n                   uint32_t ui32RxBurst,                                      \\\n                   uint32_t ui32TxBurst,                                      \\\n                   uint32_t ui32DescSkipSize))ROM_EMACTABLE[8])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACIntClear                                                      \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32IntFlags))ROM_EMACTABLE[9])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACIntDisable                                                    \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32IntFlags))ROM_EMACTABLE[10])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACIntEnable                                                     \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32IntFlags))ROM_EMACTABLE[11])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACPHYConfigSet                                                  \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Config))ROM_EMACTABLE[12])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACPHYPowerOff                                                   \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint8_t ui8PhyAddr))ROM_EMACTABLE[13])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACPHYPowerOn                                                    \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint8_t ui8PhyAddr))ROM_EMACTABLE[14])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACPHYRead                                                       \\\n        ((uint16_t (*)(uint32_t ui32Base,                                     \\\n                        uint8_t ui8PhyAddr,                                   \\\n                       uint8_t ui8RegAddr))ROM_EMACTABLE[15])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACPHYWrite                                                      \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint8_t ui8PhyAddr,                                        \\\n                   uint8_t ui8RegAddr,                                        \\\n                   uint16_t ui16Data))ROM_EMACTABLE[16])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACReset                                                         \\\n        ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[17])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACRxDisable                                                     \\\n        ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[18])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACRxDMACurrentBufferGet                                         \\\n        ((uint8_t * (*)(uint32_t ui32Base))ROM_EMACTABLE[19])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACRxDMACurrentDescriptorGet                                     \\\n        ((tEMACDMADescriptor * (*)(uint32_t ui32Base))ROM_EMACTABLE[20])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACRxDMADescriptorListGet                                        \\\n        ((tEMACDMADescriptor * (*)(uint32_t ui32Base))ROM_EMACTABLE[21])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACRxDMADescriptorListSet                                        \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   tEMACDMADescriptor *pDescriptor))ROM_EMACTABLE[22])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACRxDMAPollDemand                                               \\\n        ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[23])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACRxEnable                                                      \\\n        ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[24])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACRxWatchdogTimerSet                                            \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint8_t ui8Timeout))ROM_EMACTABLE[25])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACStatusGet                                                     \\\n        ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[26])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACTxDisable                                                     \\\n        ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[27])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACTxDMACurrentBufferGet                                         \\\n        ((uint8_t * (*)(uint32_t ui32Base))ROM_EMACTABLE[28])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACTxDMACurrentDescriptorGet                                     \\\n        ((tEMACDMADescriptor * (*)(uint32_t ui32Base))ROM_EMACTABLE[29])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACTxDMADescriptorListGet                                        \\\n        ((tEMACDMADescriptor * (*)(uint32_t ui32Base))ROM_EMACTABLE[30])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACTxDMADescriptorListSet                                        \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   tEMACDMADescriptor *pDescriptor))ROM_EMACTABLE[31])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACTxDMAPollDemand                                               \\\n        ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[32])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACTxEnable                                                      \\\n        ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[33])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACTxFlush                                                       \\\n        ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[34])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACAddrFilterGet                                                 \\\n        ((uint32_t (*)(uint32_t ui32Base,                                     \\\n                       uint32_t ui32Index))ROM_EMACTABLE[35])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACAddrFilterSet                                                 \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Index,                                        \\\n                   uint32_t ui32Config))ROM_EMACTABLE[36])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACHashFilterBitCalculate                                        \\\n        ((uint32_t (*)(uint8_t *pui8MACAddr))ROM_EMACTABLE[37])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACHashFilterGet                                                 \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t *pui32HashHi,                                     \\\n                   uint32_t *pui32HashLo))ROM_EMACTABLE[38])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACHashFilterSet                                                 \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32HashHi,                                       \\\n                   uint32_t ui32HashLo))ROM_EMACTABLE[39])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACNumAddrGet                                                    \\\n        ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[40])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACPHYExtendedRead                                               \\\n        ((uint16_t (*)(uint32_t ui32Base,                                     \\\n                       uint8_t ui8PhyAddr,                                    \\\n                       uint16_t ui16RegAddr))ROM_EMACTABLE[41])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACPHYExtendedWrite                                              \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint8_t ui8PhyAddr,                                        \\\n                   uint16_t ui16RegAddr,                                      \\\n                   uint16_t ui16Data))ROM_EMACTABLE[42])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACPowerManagementControlGet                                     \\\n        ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[43])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACPowerManagementControlSet                                     \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Flags))ROM_EMACTABLE[44])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACPowerManagementStatusGet                                      \\\n        ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[45])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACRemoteWakeUpFrameFilterGet                                    \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   tEMACWakeUpFrameFilter *pFilter))ROM_EMACTABLE[46])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACRemoteWakeUpFrameFilterSet                                    \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   const tEMACWakeUpFrameFilter *pFilter))ROM_EMACTABLE[47])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACTimestampAddendSet                                            \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Seconds))ROM_EMACTABLE[48])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACTimestampConfigGet                                            \\\n        ((uint32_t (*)(uint32_t ui32Base,                                     \\\n                       uint32_t *pui32SubSecondInc))ROM_EMACTABLE[49])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACTimestampConfigSet                                            \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Config,                                       \\\n                   uint32_t ui32SubSecondInc))ROM_EMACTABLE[50])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACTimestampDisable                                              \\\n        ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[51])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACTimestampEnable                                               \\\n        ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[52])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACTimestampIntStatus                                            \\\n        ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[53])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACTimestampPPSCommand                                           \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint8_t ui8Cmd))ROM_EMACTABLE[54])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACTimestampPPSCommandModeSet                                    \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Config))ROM_EMACTABLE[55])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACTimestampPPSPeriodSet                                         \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Period,                                       \\\n                   uint32_t ui32Width))ROM_EMACTABLE[56])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACTimestampPPSSimpleModeSet                                     \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32FreqConfig))ROM_EMACTABLE[57])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACTimestampSysTimeGet                                           \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t *pui32Seconds,                                    \\\n                   uint32_t *pui32SubSeconds))ROM_EMACTABLE[58])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACTimestampSysTimeSet                                           \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Seconds,                                      \\\n                   uint32_t ui32SubSeconds))ROM_EMACTABLE[59])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACTimestampSysTimeUpdate                                        \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Seconds,                                      \\\n                   uint32_t ui32SubSeconds,                                   \\\n                   bool bInc))ROM_EMACTABLE[60])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACTimestampTargetIntDisable                                     \\\n        ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[61])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACTimestampTargetIntEnable                                      \\\n        ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[62])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACTimestampTargetSet                                            \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Seconds,                                      \\\n                   uint32_t ui32Nanoseconds))ROM_EMACTABLE[63])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACVLANHashFilterBitCalculate                                    \\\n        ((uint32_t (*)(uint16_t ui16Tag))ROM_EMACTABLE[64])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACVLANHashFilterGet                                             \\\n        ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[65])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACVLANHashFilterSet                                             \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Hash))ROM_EMACTABLE[66])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACVLANRxConfigGet                                               \\\n        ((uint32_t (*)(uint32_t ui32Base,                                     \\\n                       uint16_t *pui16Tag))ROM_EMACTABLE[67])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACVLANRxConfigSet                                               \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint16_t ui16Tag,                                          \\\n                   uint32_t ui32Config))ROM_EMACTABLE[68])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACVLANTxConfigGet                                               \\\n        ((uint32_t (*)(uint32_t ui32Base,                                     \\\n                       uint16_t *pui16Tag))ROM_EMACTABLE[69])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_EMACVLANTxConfigSet                                               \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint16_t ui16Tag,                                          \\\n                   uint32_t ui32Config))ROM_EMACTABLE[70])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_UpdateEMAC                                                        \\\n        ((void (*)(uint32_t ui32Clock))ROM_EMACTABLE[71])\n#endif\n\n//============================================================================*\n//\n// Macros for calling ROM functions in the Flash API.\n//\n//============================================================================*\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_FlashProgram                                                      \\\n        ((int32_t (*)(uint32_t *pui32Data,                                    \\\n                      uint32_t ui32Address,                                   \\\n                      uint32_t ui32Count))ROM_FLASHTABLE[0])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_FlashErase                                                        \\\n        ((int32_t (*)(uint32_t ui32Address))ROM_FLASHTABLE[3])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_FlashProtectGet                                                   \\\n        ((tFlashProtection (*)(uint32_t ui32Address))ROM_FLASHTABLE[4])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_FlashProtectSet                                                   \\\n        ((int32_t (*)(uint32_t ui32Address,                                   \\\n                      tFlashProtection eProtect))ROM_FLASHTABLE[5])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_FlashProtectSave                                                  \\\n        ((int32_t (*)(void))ROM_FLASHTABLE[6])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_FlashUserGet                                                      \\\n        ((int32_t (*)(uint32_t *pui32User0,                                   \\\n                      uint32_t *pui32User1))ROM_FLASHTABLE[7])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_FlashUserSet                                                      \\\n        ((int32_t (*)(uint32_t ui32User0,                                     \\\n                      uint32_t ui32User1))ROM_FLASHTABLE[8])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_FlashUserSave                                                     \\\n        ((int32_t (*)(void))ROM_FLASHTABLE[9])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_FlashIntEnable                                                    \\\n        ((void (*)(uint32_t ui32IntFlags))ROM_FLASHTABLE[10])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_FlashIntDisable                                                   \\\n        ((void (*)(uint32_t ui32IntFlags))ROM_FLASHTABLE[11])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_FlashIntStatus                                                    \\\n        ((uint32_t (*)(bool bMasked))ROM_FLASHTABLE[12])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_FlashIntClear                                                     \\\n        ((void (*)(uint32_t ui32IntFlags))ROM_FLASHTABLE[13])\n#endif\n\n//============================================================================*\n//\n// Macros for calling ROM functions in the FPU API.\n//\n//============================================================================*\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_FPUEnable                                                         \\\n        ((void (*)(void))ROM_FPUTABLE[0])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_FPUDisable                                                        \\\n        ((void (*)(void))ROM_FPUTABLE[1])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_FPUFlushToZeroModeSet                                             \\\n        ((void (*)(uint32_t ui32Mode))ROM_FPUTABLE[2])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_FPUHalfPrecisionModeSet                                           \\\n        ((void (*)(uint32_t ui32Mode))ROM_FPUTABLE[3])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_FPULazyStackingEnable                                             \\\n        ((void (*)(void))ROM_FPUTABLE[4])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_FPUNaNModeSet                                                     \\\n        ((void (*)(uint32_t ui32Mode))ROM_FPUTABLE[5])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_FPURoundingModeSet                                                \\\n        ((void (*)(uint32_t ui32Mode))ROM_FPUTABLE[6])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_FPUStackingDisable                                                \\\n        ((void (*)(void))ROM_FPUTABLE[7])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_FPUStackingEnable                                                 \\\n        ((void (*)(void))ROM_FPUTABLE[8])\n#endif\n\n//============================================================================*\n//\n// Macros for calling ROM functions in the GPIO API.\n//\n//============================================================================*\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_GPIOPinWrite                                                      \\\n        ((void (*)(uint32_t ui32Port,                                         \\\n                   uint8_t ui8Pins,                                           \\\n                   uint8_t ui8Val))ROM_GPIOTABLE[0])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_GPIODirModeSet                                                    \\\n        ((void (*)(uint32_t ui32Port,                                         \\\n                   uint8_t ui8Pins,                                           \\\n                   uint32_t ui32PinIO))ROM_GPIOTABLE[1])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_GPIODirModeGet                                                    \\\n        ((uint32_t (*)(uint32_t ui32Port,                                     \\\n                       uint8_t ui8Pin))ROM_GPIOTABLE[2])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_GPIOIntTypeSet                                                    \\\n        ((void (*)(uint32_t ui32Port,                                         \\\n                   uint8_t ui8Pins,                                           \\\n                   uint32_t ui32IntType))ROM_GPIOTABLE[3])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_GPIOIntTypeGet                                                    \\\n        ((uint32_t (*)(uint32_t ui32Port,                                     \\\n                       uint8_t ui8Pin))ROM_GPIOTABLE[4])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2)\n#define ROM_GPIOPadConfigSet                                                  \\\n        ((void (*)(uint32_t ui32Port,                                         \\\n                   uint8_t ui8Pins,                                           \\\n                   uint32_t ui32Strength,                                     \\\n                   uint32_t ui32PadType))ROM_GPIOTABLE[5])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_GPIOPadConfigGet                                                  \\\n        ((void (*)(uint32_t ui32Port,                                         \\\n                   uint8_t ui8Pin,                                            \\\n                   uint32_t *pui32Strength,                                   \\\n                   uint32_t *pui32PadType))ROM_GPIOTABLE[6])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_GPIOPinRead                                                       \\\n        ((int32_t (*)(uint32_t ui32Port,                                      \\\n                      uint8_t ui8Pins))ROM_GPIOTABLE[11])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2)\n#define ROM_GPIOPinTypeCAN                                                    \\\n        ((void (*)(uint32_t ui32Port,                                         \\\n                   uint8_t ui8Pins))ROM_GPIOTABLE[12])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_GPIOPinTypeComparator                                             \\\n        ((void (*)(uint32_t ui32Port,                                         \\\n                   uint8_t ui8Pins))ROM_GPIOTABLE[13])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_GPIOPinTypeGPIOInput                                              \\\n        ((void (*)(uint32_t ui32Port,                                         \\\n                   uint8_t ui8Pins))ROM_GPIOTABLE[14])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_GPIOPinTypeGPIOOutput                                             \\\n        ((void (*)(uint32_t ui32Port,                                         \\\n                   uint8_t ui8Pins))ROM_GPIOTABLE[15])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_GPIOPinTypeI2C                                                    \\\n        ((void (*)(uint32_t ui32Port,                                         \\\n                   uint8_t ui8Pins))ROM_GPIOTABLE[16])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_GPIOPinTypePWM                                                    \\\n        ((void (*)(uint32_t ui32Port,                                         \\\n                   uint8_t ui8Pins))ROM_GPIOTABLE[17])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_GPIOPinTypeQEI                                                    \\\n        ((void (*)(uint32_t ui32Port,                                         \\\n                   uint8_t ui8Pins))ROM_GPIOTABLE[18])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_GPIOPinTypeSSI                                                    \\\n        ((void (*)(uint32_t ui32Port,                                         \\\n                   uint8_t ui8Pins))ROM_GPIOTABLE[19])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_GPIOPinTypeTimer                                                  \\\n        ((void (*)(uint32_t ui32Port,                                         \\\n                   uint8_t ui8Pins))ROM_GPIOTABLE[20])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_GPIOPinTypeUART                                                   \\\n        ((void (*)(uint32_t ui32Port,                                         \\\n                   uint8_t ui8Pins))ROM_GPIOTABLE[21])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_GPIOPinTypeGPIOOutputOD                                           \\\n        ((void (*)(uint32_t ui32Port,                                         \\\n                   uint8_t ui8Pins))ROM_GPIOTABLE[22])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_GPIOPinTypeADC                                                    \\\n        ((void (*)(uint32_t ui32Port,                                         \\\n                   uint8_t ui8Pins))ROM_GPIOTABLE[23])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_GPIOPinTypeUSBDigital                                             \\\n        ((void (*)(uint32_t ui32Port,                                         \\\n                   uint8_t ui8Pins))ROM_GPIOTABLE[24])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_GPIOPinConfigure                                                  \\\n        ((void (*)(uint32_t ui32PinConfig))ROM_GPIOTABLE[26])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_GPIOPinTypeUSBAnalog                                              \\\n        ((void (*)(uint32_t ui32Port,                                         \\\n                   uint8_t ui8Pins))ROM_GPIOTABLE[28])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_GPIODMATriggerEnable                                              \\\n        ((void (*)(uint32_t ui32Port,                                         \\\n                   uint8_t ui8Pins))ROM_GPIOTABLE[31])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_GPIODMATriggerDisable                                             \\\n        ((void (*)(uint32_t ui32Port,                                         \\\n                   uint8_t ui8Pins))ROM_GPIOTABLE[32])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_GPIOADCTriggerEnable                                              \\\n        ((void (*)(uint32_t ui32Port,                                         \\\n                   uint8_t ui8Pins))ROM_GPIOTABLE[33])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_GPIOADCTriggerDisable                                             \\\n        ((void (*)(uint32_t ui32Port,                                         \\\n                   uint8_t ui8Pins))ROM_GPIOTABLE[34])\n#endif\n#if defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_GPIOPinTypeI2CSCL                                                 \\\n        ((void (*)(uint32_t ui32Port,                                         \\\n                   uint8_t ui8Pins))ROM_GPIOTABLE[39])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_GPIOPinTypeOneWire                                                \\\n        ((void (*)(uint32_t ui32Port,                                         \\\n                   uint8_t ui8Pins))ROM_GPIOTABLE[44])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_GPIOPinTypeWakeHigh                                               \\\n        ((void (*)(uint32_t ui32Port,                                         \\\n                   uint8_t ui8Pins))ROM_GPIOTABLE[48])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_GPIOPinTypeWakeLow                                                \\\n        ((void (*)(uint32_t ui32Port,                                         \\\n                   uint8_t ui8Pins))ROM_GPIOTABLE[49])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_GPIOIntClear                                                      \\\n        ((void (*)(uint32_t ui32Port,                                         \\\n                   uint32_t ui32IntFlags))ROM_GPIOTABLE[51])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_GPIOIntDisable                                                    \\\n        ((void (*)(uint32_t ui32Port,                                         \\\n                   uint32_t ui32IntFlags))ROM_GPIOTABLE[52])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_GPIOIntEnable                                                     \\\n        ((void (*)(uint32_t ui32Port,                                         \\\n                   uint32_t ui32IntFlags))ROM_GPIOTABLE[53])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_GPIOIntStatus                                                     \\\n        ((uint32_t (*)(uint32_t ui32Port,                                     \\\n                       bool bMasked))ROM_GPIOTABLE[54])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_GPIOPinWakeStatus                                                 \\\n        ((uint32_t (*)(uint32_t ui32Port))ROM_GPIOTABLE[55])\n#endif\n\n//============================================================================*\n//\n// Macros for calling ROM functions in the Hibernate API.\n//\n//============================================================================*\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_HibernateIntClear                                                 \\\n        ((void (*)(uint32_t ui32IntFlags))ROM_HIBERNATETABLE[0])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_HibernateEnableExpClk                                             \\\n        ((void (*)(uint32_t ui32HibClk))ROM_HIBERNATETABLE[1])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_HibernateDisable                                                  \\\n        ((void (*)(void))ROM_HIBERNATETABLE[2])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_HibernateRTCEnable                                                \\\n        ((void (*)(void))ROM_HIBERNATETABLE[4])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_HibernateRTCDisable                                               \\\n        ((void (*)(void))ROM_HIBERNATETABLE[5])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_HibernateWakeSet                                                  \\\n        ((void (*)(uint32_t ui32WakeFlags))ROM_HIBERNATETABLE[6])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_HibernateWakeGet                                                  \\\n        ((uint32_t (*)(void))ROM_HIBERNATETABLE[7])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_HibernateLowBatSet                                                \\\n        ((void (*)(uint32_t ui32LowBatFlags))ROM_HIBERNATETABLE[8])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_HibernateLowBatGet                                                \\\n        ((uint32_t (*)(void))ROM_HIBERNATETABLE[9])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_HibernateRTCSet                                                   \\\n        ((void (*)(uint32_t ui32RTCValue))ROM_HIBERNATETABLE[10])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_HibernateRTCGet                                                   \\\n        ((uint32_t (*)(void))ROM_HIBERNATETABLE[11])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_HibernateRTCTrimSet                                               \\\n        ((void (*)(uint32_t ui32Trim))ROM_HIBERNATETABLE[16])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_HibernateRTCTrimGet                                               \\\n        ((uint32_t (*)(void))ROM_HIBERNATETABLE[17])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_HibernateDataSet                                                  \\\n        ((void (*)(uint32_t *pui32Data,                                       \\\n                   uint32_t ui32Count))ROM_HIBERNATETABLE[18])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_HibernateDataGet                                                  \\\n        ((void (*)(uint32_t *pui32Data,                                       \\\n                   uint32_t ui32Count))ROM_HIBERNATETABLE[19])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_HibernateRequest                                                  \\\n        ((void (*)(void))ROM_HIBERNATETABLE[20])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_HibernateIntEnable                                                \\\n        ((void (*)(uint32_t ui32IntFlags))ROM_HIBERNATETABLE[21])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_HibernateIntDisable                                               \\\n        ((void (*)(uint32_t ui32IntFlags))ROM_HIBERNATETABLE[22])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_HibernateIntStatus                                                \\\n        ((uint32_t (*)(bool bMasked))ROM_HIBERNATETABLE[23])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_HibernateIsActive                                                 \\\n        ((uint32_t (*)(void))ROM_HIBERNATETABLE[24])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_HibernateRTCSSGet                                                 \\\n        ((uint32_t (*)(void))ROM_HIBERNATETABLE[27])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_HibernateClockConfig                                              \\\n        ((void (*)(uint32_t ui32Config))ROM_HIBERNATETABLE[28])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_HibernateBatCheckStart                                            \\\n        ((void (*)(void))ROM_HIBERNATETABLE[29])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_HibernateBatCheckDone                                             \\\n        ((uint32_t (*)(void))ROM_HIBERNATETABLE[30])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_HibernateGPIORetentionEnable                                      \\\n        ((void (*)(void))ROM_HIBERNATETABLE[31])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_HibernateGPIORetentionDisable                                     \\\n        ((void (*)(void))ROM_HIBERNATETABLE[32])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_HibernateGPIORetentionGet                                         \\\n        ((bool (*)(void))ROM_HIBERNATETABLE[33])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_HibernateCounterMode                                              \\\n        ((void (*)(uint32_t ui32Config))ROM_HIBERNATETABLE[34])\n#endif\n#if defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_HibernateCalendarSet                                              \\\n        ((void (*)(struct tm *psTime))ROM_HIBERNATETABLE[35])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_HibernateCalendarGet                                              \\\n        ((int (*)(struct tm *psTime))ROM_HIBERNATETABLE[36])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_HibernateCalendarMatchSet                                         \\\n        ((void (*)(uint32_t ui32Index,                                        \\\n                   struct tm *psTime))ROM_HIBERNATETABLE[37])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_HibernateCalendarMatchGet                                         \\\n        ((void (*)(uint32_t ui32Index,                                        \\\n                   struct tm *psTime))ROM_HIBERNATETABLE[38])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_HibernateTamperDisable                                            \\\n        ((void (*)(void))ROM_HIBERNATETABLE[39])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_HibernateTamperEnable                                             \\\n        ((void (*)(void))ROM_HIBERNATETABLE[40])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_HibernateTamperEventsClear                                        \\\n        ((void (*)(void))ROM_HIBERNATETABLE[41])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_HibernateTamperEventsConfig                                       \\\n        ((void (*)(uint32_t ui32Config))ROM_HIBERNATETABLE[42])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_HibernateTamperEventsGet                                          \\\n        ((bool (*)(uint32_t ui32Index,                                        \\\n                   uint32_t *pui32RTC,                                        \\\n                   uint32_t *pui32Event))ROM_HIBERNATETABLE[43])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_HibernateTamperExtOscValid                                        \\\n        ((bool (*)(void))ROM_HIBERNATETABLE[44])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_HibernateTamperExtOscRecover                                      \\\n        ((void (*)(void))ROM_HIBERNATETABLE[45])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_HibernateTamperIODisable                                          \\\n        ((void (*)(uint32_t ui32Input))ROM_HIBERNATETABLE[46])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_HibernateTamperIOEnable                                           \\\n        ((void (*)(uint32_t ui32Input,                                        \\\n                   uint32_t ui32Config))ROM_HIBERNATETABLE[47])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_HibernateTamperStatusGet                                          \\\n        ((uint32_t (*)(void))ROM_HIBERNATETABLE[48])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_HibernateRTCMatchGet                                              \\\n        ((uint32_t (*)(uint32_t ui32Match))ROM_HIBERNATETABLE[49])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_HibernateRTCMatchSet                                              \\\n        ((void (*)(uint32_t ui32Match,                                        \\\n                   uint32_t ui32Value))ROM_HIBERNATETABLE[50])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_HibernateRTCSSMatchGet                                            \\\n        ((uint32_t (*)(uint32_t ui32Match))ROM_HIBERNATETABLE[51])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_HibernateRTCSSMatchSet                                            \\\n        ((void (*)(uint32_t ui32Match,                                        \\\n                   uint32_t ui32Value))ROM_HIBERNATETABLE[52])\n#endif\n\n//============================================================================*\n//\n// Macros for calling ROM functions in the I2C API.\n//\n//============================================================================*\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_I2CMasterDataPut                                                  \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint8_t ui8Data))ROM_I2CTABLE[0])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_I2CMasterInitExpClk                                               \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32I2CClk,                                       \\\n                   bool bFast))ROM_I2CTABLE[1])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_I2CSlaveInit                                                      \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint8_t ui8SlaveAddr))ROM_I2CTABLE[2])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_I2CMasterEnable                                                   \\\n        ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[3])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_I2CSlaveEnable                                                    \\\n        ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[4])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_I2CMasterDisable                                                  \\\n        ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[5])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_I2CSlaveDisable                                                   \\\n        ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[6])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_I2CMasterIntEnable                                                \\\n        ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[7])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_I2CSlaveIntEnable                                                 \\\n        ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[8])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_I2CMasterIntDisable                                               \\\n        ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[9])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_I2CSlaveIntDisable                                                \\\n        ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[10])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_I2CMasterIntStatus                                                \\\n        ((bool (*)(uint32_t ui32Base,                                         \\\n                   bool bMasked))ROM_I2CTABLE[11])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_I2CSlaveIntStatus                                                 \\\n        ((bool (*)(uint32_t ui32Base,                                         \\\n                   bool bMasked))ROM_I2CTABLE[12])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_I2CMasterIntClear                                                 \\\n        ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[13])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_I2CSlaveIntClear                                                  \\\n        ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[14])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_I2CMasterSlaveAddrSet                                             \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint8_t ui8SlaveAddr,                                      \\\n                   bool bReceive))ROM_I2CTABLE[15])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_I2CMasterBusy                                                     \\\n        ((bool (*)(uint32_t ui32Base))ROM_I2CTABLE[16])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_I2CMasterBusBusy                                                  \\\n        ((bool (*)(uint32_t ui32Base))ROM_I2CTABLE[17])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_I2CMasterControl                                                  \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Cmd))ROM_I2CTABLE[18])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_I2CMasterErr                                                      \\\n        ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[19])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_I2CMasterDataGet                                                  \\\n        ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[20])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_I2CSlaveStatus                                                    \\\n        ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[21])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_I2CSlaveDataPut                                                   \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint8_t ui8Data))ROM_I2CTABLE[22])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_I2CSlaveDataGet                                                   \\\n        ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[23])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_UpdateI2C                                                         \\\n        ((void (*)(void))ROM_I2CTABLE[24])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_I2CSlaveIntEnableEx                                               \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32IntFlags))ROM_I2CTABLE[25])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_I2CSlaveIntDisableEx                                              \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32IntFlags))ROM_I2CTABLE[26])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_I2CSlaveIntStatusEx                                               \\\n        ((uint32_t (*)(uint32_t ui32Base,                                     \\\n                       bool bMasked))ROM_I2CTABLE[27])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_I2CSlaveIntClearEx                                                \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32IntFlags))ROM_I2CTABLE[28])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_I2CMasterIntEnableEx                                              \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32IntFlags))ROM_I2CTABLE[29])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_I2CMasterIntDisableEx                                             \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32IntFlags))ROM_I2CTABLE[30])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_I2CMasterIntStatusEx                                              \\\n        ((uint32_t (*)(uint32_t ui32Base,                                     \\\n                       bool bMasked))ROM_I2CTABLE[31])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_I2CMasterIntClearEx                                               \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32IntFlags))ROM_I2CTABLE[32])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_I2CMasterTimeoutSet                                               \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Value))ROM_I2CTABLE[33])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_I2CSlaveACKOverride                                               \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   bool bEnable))ROM_I2CTABLE[34])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_I2CSlaveACKValueSet                                               \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   bool bACK))ROM_I2CTABLE[35])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_I2CSlaveAddressSet                                                \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint8_t ui8AddrNum,                                        \\\n                   uint8_t ui8SlaveAddr))ROM_I2CTABLE[37])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_I2CMasterLineStateGet                                             \\\n        ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[38])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_I2CTxFIFOConfigSet                                                \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Config))ROM_I2CTABLE[39])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_I2CTxFIFOFlush                                                    \\\n        ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[40])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_I2CRxFIFOConfigSet                                                \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Config))ROM_I2CTABLE[41])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_I2CRxFIFOFlush                                                    \\\n        ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[42])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_I2CFIFOStatus                                                     \\\n        ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[43])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_I2CFIFODataPut                                                    \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint8_t ui8Data))ROM_I2CTABLE[44])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_I2CFIFODataPutNonBlocking                                         \\\n        ((uint32_t (*)(uint32_t ui32Base,                                     \\\n                       uint8_t ui8Data))ROM_I2CTABLE[45])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_I2CFIFODataGet                                                    \\\n        ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[46])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_I2CFIFODataGetNonBlocking                                         \\\n        ((uint32_t (*)(uint32_t ui32Base,                                     \\\n                       uint8_t *pui8Data))ROM_I2CTABLE[47])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_I2CMasterBurstLengthSet                                           \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint8_t ui8Length))ROM_I2CTABLE[48])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_I2CMasterBurstCountGet                                            \\\n        ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[49])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_I2CSlaveFIFODisable                                               \\\n        ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[50])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_I2CSlaveFIFOEnable                                                \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Config))ROM_I2CTABLE[51])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_I2CMasterGlitchFilterConfigSet                                    \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Config))ROM_I2CTABLE[54])\n#endif\n\n//============================================================================*\n//\n// Macros for calling ROM functions in the Interrupt API.\n//\n//============================================================================*\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_IntEnable                                                         \\\n        ((void (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[0])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_IntMasterEnable                                                   \\\n        ((bool (*)(void))ROM_INTERRUPTTABLE[1])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_IntMasterDisable                                                  \\\n        ((bool (*)(void))ROM_INTERRUPTTABLE[2])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_IntDisable                                                        \\\n        ((void (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[3])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_IntPriorityGroupingSet                                            \\\n        ((void (*)(uint32_t ui32Bits))ROM_INTERRUPTTABLE[4])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_IntPriorityGroupingGet                                            \\\n        ((uint32_t (*)(void))ROM_INTERRUPTTABLE[5])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_IntPrioritySet                                                    \\\n        ((void (*)(uint32_t ui32Interrupt,                                    \\\n                   uint8_t ui8Priority))ROM_INTERRUPTTABLE[6])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_IntPriorityGet                                                    \\\n        ((int32_t (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[7])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_IntPendSet                                                        \\\n        ((void (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[8])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_IntPendClear                                                      \\\n        ((void (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[9])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_IntPriorityMaskSet                                                \\\n        ((void (*)(uint32_t ui32PriorityMask))ROM_INTERRUPTTABLE[10])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_IntPriorityMaskGet                                                \\\n        ((uint32_t (*)(void))ROM_INTERRUPTTABLE[11])\n#endif\n#if defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_IntIsEnabled                                                      \\\n        ((uint32_t (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[12])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_IntTrigger                                                        \\\n        ((void (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[13])\n#endif\n\n//============================================================================*\n//\n// Macros for calling ROM functions in the LCD API.\n//\n//============================================================================*\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_LCDIntStatus                                                      \\\n        ((uint32_t (*)(uint32_t ui32Base,                                     \\\n                       bool bMasked))ROM_LCDTABLE[0])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_LCDClockReset                                                     \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Clocks))ROM_LCDTABLE[1])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_LCDDMAConfigSet                                                   \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Config))ROM_LCDTABLE[2])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_LCDIDDCommandWrite                                                \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32CS,                                           \\\n                   uint16_t ui16Cmd))ROM_LCDTABLE[3])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_LCDIDDConfigSet                                                   \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Config))ROM_LCDTABLE[4])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_LCDIDDDataRead                                                    \\\n        ((uint16_t (*)(uint32_t ui32Base,                                     \\\n                       uint32_t ui32CS))ROM_LCDTABLE[5])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_LCDIDDDataWrite                                                   \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32CS,                                           \\\n                   uint16_t ui16Data))ROM_LCDTABLE[6])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_LCDIDDDMADisable                                                  \\\n        ((void (*)(uint32_t ui32Base))ROM_LCDTABLE[7])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_LCDIDDDMAWrite                                                    \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32CS,                                           \\\n                   const uint32_t *pui32Data,                                 \\\n                   uint32_t ui32Count))ROM_LCDTABLE[8])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_LCDIDDIndexedRead                                                 \\\n        ((uint16_t (*)(uint32_t ui32Base,                                     \\\n                       uint32_t ui32CS,                                       \\\n                       uint16_t ui16Addr))ROM_LCDTABLE[9])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_LCDIDDIndexedWrite                                                \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32CS,                                           \\\n                   uint16_t ui16Addr,                                         \\\n                   uint16_t ui16Data))ROM_LCDTABLE[10])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_LCDIDDStatusRead                                                  \\\n        ((uint16_t (*)(uint32_t ui32Base,                                     \\\n                       uint32_t ui32CS))ROM_LCDTABLE[11])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_LCDIDDTimingSet                                                   \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32CS,                                           \\\n                   const tLCDIDDTiming *pTiming))ROM_LCDTABLE[12])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_LCDIntClear                                                       \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32IntFlags))ROM_LCDTABLE[13])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_LCDIntDisable                                                     \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32IntFlags))ROM_LCDTABLE[14])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_LCDIntEnable                                                      \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32IntFlags))ROM_LCDTABLE[15])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_LCDModeSet                                                        \\\n        ((uint32_t (*)(uint32_t ui32Base,                                     \\\n                       uint8_t ui8Mode,                                       \\\n                       uint32_t ui32PixClk,                                   \\\n                       uint32_t ui32SysClk))ROM_LCDTABLE[16])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_LCDRasterACBiasIntCountSet                                        \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint8_t ui8Count))ROM_LCDTABLE[17])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_LCDRasterConfigSet                                                \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Config,                                       \\\n                   uint8_t ui8PalLoadDelay))ROM_LCDTABLE[18])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_LCDRasterDisable                                                  \\\n        ((void (*)(uint32_t ui32Base))ROM_LCDTABLE[19])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_LCDRasterEnable                                                   \\\n        ((void (*)(uint32_t ui32Base))ROM_LCDTABLE[20])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_LCDRasterFrameBufferSet                                           \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint8_t ui8Buffer,                                         \\\n                   uint32_t *pui32Addr,                                       \\\n                   uint32_t ui32NumBytes))ROM_LCDTABLE[21])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_LCDRasterPaletteSet                                               \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Type,                                         \\\n                   uint32_t *pui32PalAddr,                                    \\\n                   const uint32_t *pui32SrcColors,                            \\\n                   uint32_t ui32Start,                                        \\\n                   uint32_t ui32Count))ROM_LCDTABLE[22])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_LCDRasterSubPanelConfigSet                                        \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Flags,                                        \\\n                   uint32_t ui32BottomLines,                                  \\\n                   uint32_t ui32DefaultPixel))ROM_LCDTABLE[23])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_LCDRasterSubPanelDisable                                          \\\n        ((void (*)(uint32_t ui32Base))ROM_LCDTABLE[24])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_LCDRasterSubPanelEnable                                           \\\n        ((void (*)(uint32_t ui32Base))ROM_LCDTABLE[25])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_LCDRasterTimingSet                                                \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   const tLCDRasterTiming *pTiming))ROM_LCDTABLE[26])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_LCDRasterEnabled                                                  \\\n        ((bool (*)(uint32_t ui32Base))ROM_LCDTABLE[27])\n#endif\n\n//============================================================================*\n//\n// Macros for calling ROM functions in the MPU API.\n//\n//============================================================================*\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_MPUEnable                                                         \\\n        ((void (*)(uint32_t ui32MPUConfig))ROM_MPUTABLE[0])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_MPUDisable                                                        \\\n        ((void (*)(void))ROM_MPUTABLE[1])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_MPURegionCountGet                                                 \\\n        ((uint32_t (*)(void))ROM_MPUTABLE[2])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_MPURegionEnable                                                   \\\n        ((void (*)(uint32_t ui32Region))ROM_MPUTABLE[3])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_MPURegionDisable                                                  \\\n        ((void (*)(uint32_t ui32Region))ROM_MPUTABLE[4])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_MPURegionSet                                                      \\\n        ((void (*)(uint32_t ui32Region,                                       \\\n                   uint32_t ui32Addr,                                         \\\n                   uint32_t ui32Flags))ROM_MPUTABLE[5])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_MPURegionGet                                                      \\\n        ((void (*)(uint32_t ui32Region,                                       \\\n                   uint32_t *pui32Addr,                                       \\\n                   uint32_t *pui32Flags))ROM_MPUTABLE[6])\n#endif\n\n//============================================================================*\n//\n// Macros for calling ROM functions in the OneWire API.\n//\n//============================================================================*\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_OneWireIntStatus                                                  \\\n        ((uint32_t (*)(uint32_t ui32Base,                                     \\\n                       bool bMasked))ROM_ONEWIRETABLE[0])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_OneWireBusReset                                                   \\\n        ((void (*)(uint32_t ui32Base))ROM_ONEWIRETABLE[1])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_OneWireBusStatus                                                  \\\n        ((uint32_t (*)(uint32_t ui32Base))ROM_ONEWIRETABLE[2])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_OneWireDataGet                                                    \\\n        ((void (*)(uint32_t u3i2Base,                                         \\\n                   uint32_t *pui32Data))ROM_ONEWIRETABLE[3])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_OneWireDataGetNonBlocking                                         \\\n        ((bool (*)(uint32_t ui32Base,                                         \\\n                   uint32_t *pui32Data))ROM_ONEWIRETABLE[4])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_OneWireInit                                                       \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32InitFlags))ROM_ONEWIRETABLE[5])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_OneWireIntClear                                                   \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32IntFlags))ROM_ONEWIRETABLE[6])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_OneWireIntDisable                                                 \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32IntFlags))ROM_ONEWIRETABLE[7])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_OneWireIntEnable                                                  \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32IntFlags))ROM_ONEWIRETABLE[8])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_OneWireTransaction                                                \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32OpFlags,                                      \\\n                   uint32_t ui32Data,                                         \\\n                   uint32_t ui32BitCnt))ROM_ONEWIRETABLE[9])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_OneWireDMADisable                                                 \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32DMAFlags))ROM_ONEWIRETABLE[10])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_OneWireDMAEnable                                                  \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32DMAFlags))ROM_ONEWIRETABLE[11])\n#endif\n\n//============================================================================*\n//\n// Macros for calling ROM functions in the PWM API.\n//\n//============================================================================*\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_PWMPulseWidthSet                                                  \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32PWMOut,                                       \\\n                   uint32_t ui32Width))ROM_PWMTABLE[0])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_PWMGenConfigure                                                   \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Gen,                                          \\\n                   uint32_t ui32Config))ROM_PWMTABLE[1])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_PWMGenPeriodSet                                                   \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Gen,                                          \\\n                   uint32_t ui32Period))ROM_PWMTABLE[2])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_PWMGenPeriodGet                                                   \\\n        ((uint32_t (*)(uint32_t ui32Base,                                     \\\n                       uint32_t ui32Gen))ROM_PWMTABLE[3])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_PWMGenEnable                                                      \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Gen))ROM_PWMTABLE[4])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_PWMGenDisable                                                     \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Gen))ROM_PWMTABLE[5])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_PWMPulseWidthGet                                                  \\\n        ((uint32_t (*)(uint32_t ui32Base,                                     \\\n                       uint32_t ui32PWMOut))ROM_PWMTABLE[6])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_PWMDeadBandEnable                                                 \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Gen,                                          \\\n                   uint16_t ui16Rise,                                         \\\n                   uint16_t ui16Fall))ROM_PWMTABLE[7])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_PWMDeadBandDisable                                                \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Gen))ROM_PWMTABLE[8])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_PWMSyncUpdate                                                     \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32GenBits))ROM_PWMTABLE[9])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_PWMSyncTimeBase                                                   \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32GenBits))ROM_PWMTABLE[10])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_PWMOutputState                                                    \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32PWMOutBits,                                   \\\n                   bool bEnable))ROM_PWMTABLE[11])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_PWMOutputInvert                                                   \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32PWMOutBits,                                   \\\n                   bool bInvert))ROM_PWMTABLE[12])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_PWMOutputFault                                                    \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32PWMOutBits,                                   \\\n                   bool bFaultSuppress))ROM_PWMTABLE[13])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_PWMGenIntTrigEnable                                               \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Gen,                                          \\\n                   uint32_t ui32IntTrig))ROM_PWMTABLE[14])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_PWMGenIntTrigDisable                                              \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Gen,                                          \\\n                   uint32_t ui32IntTrig))ROM_PWMTABLE[15])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_PWMGenIntStatus                                                   \\\n        ((uint32_t (*)(uint32_t ui32Base,                                     \\\n                       uint32_t ui32Gen,                                      \\\n                       bool bMasked))ROM_PWMTABLE[16])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_PWMGenIntClear                                                    \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Gen,                                          \\\n                   uint32_t ui32Ints))ROM_PWMTABLE[17])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_PWMIntEnable                                                      \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32GenFault))ROM_PWMTABLE[18])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_PWMIntDisable                                                     \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32GenFault))ROM_PWMTABLE[19])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_PWMFaultIntClear                                                  \\\n        ((void (*)(uint32_t ui32Base))ROM_PWMTABLE[20])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_PWMIntStatus                                                      \\\n        ((uint32_t (*)(uint32_t ui32Base,                                     \\\n                       bool bMasked))ROM_PWMTABLE[21])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_PWMOutputFaultLevel                                               \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32PWMOutBits,                                   \\\n                   bool bDriveHigh))ROM_PWMTABLE[22])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_PWMFaultIntClearExt                                               \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32FaultInts))ROM_PWMTABLE[23])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_PWMGenFaultConfigure                                              \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Gen,                                          \\\n                   uint32_t ui32MinFaultPeriod,                               \\\n                   uint32_t ui32FaultSenses))ROM_PWMTABLE[24])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_PWMGenFaultTriggerSet                                             \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Gen,                                          \\\n                   uint32_t ui32Group,                                        \\\n                   uint32_t ui32FaultTriggers))ROM_PWMTABLE[25])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_PWMGenFaultTriggerGet                                             \\\n        ((uint32_t (*)(uint32_t ui32Base,                                     \\\n                       uint32_t ui32Gen,                                      \\\n                       uint32_t ui32Group))ROM_PWMTABLE[26])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_PWMGenFaultStatus                                                 \\\n        ((uint32_t (*)(uint32_t ui32Base,                                     \\\n                       uint32_t ui32Gen,                                      \\\n                       uint32_t ui32Group))ROM_PWMTABLE[27])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_PWMGenFaultClear                                                  \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Gen,                                          \\\n                   uint32_t ui32Group,                                        \\\n                   uint32_t ui32FaultTriggers))ROM_PWMTABLE[28])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_PWMClockSet                                                       \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Config))ROM_PWMTABLE[29])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_PWMClockGet                                                       \\\n        ((uint32_t (*)(uint32_t ui32Base))ROM_PWMTABLE[30])\n#endif\n#if defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_PWMOutputUpdateMode                                               \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32PWMOutBits,                                   \\\n                   uint32_t ui32Mode))ROM_PWMTABLE[31])\n#endif\n\n//============================================================================*\n//\n// Macros for calling ROM functions in the QEI API.\n//\n//============================================================================*\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_QEIPositionGet                                                    \\\n        ((uint32_t (*)(uint32_t ui32Base))ROM_QEITABLE[0])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_QEIEnable                                                         \\\n        ((void (*)(uint32_t ui32Base))ROM_QEITABLE[1])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_QEIDisable                                                        \\\n        ((void (*)(uint32_t ui32Base))ROM_QEITABLE[2])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_QEIConfigure                                                      \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Config,                                       \\\n                   uint32_t ui32MaxPosition))ROM_QEITABLE[3])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_QEIPositionSet                                                    \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Position))ROM_QEITABLE[4])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_QEIDirectionGet                                                   \\\n        ((int32_t (*)(uint32_t ui32Base))ROM_QEITABLE[5])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_QEIErrorGet                                                       \\\n        ((bool (*)(uint32_t ui32Base))ROM_QEITABLE[6])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_QEIVelocityEnable                                                 \\\n        ((void (*)(uint32_t ui32Base))ROM_QEITABLE[7])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_QEIVelocityDisable                                                \\\n        ((void (*)(uint32_t ui32Base))ROM_QEITABLE[8])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_QEIVelocityConfigure                                              \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32PreDiv,                                       \\\n                   uint32_t ui32Period))ROM_QEITABLE[9])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_QEIVelocityGet                                                    \\\n        ((uint32_t (*)(uint32_t ui32Base))ROM_QEITABLE[10])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_QEIIntEnable                                                      \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32IntFlags))ROM_QEITABLE[11])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_QEIIntDisable                                                     \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32IntFlags))ROM_QEITABLE[12])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_QEIIntStatus                                                      \\\n        ((uint32_t (*)(uint32_t ui32Base,                                     \\\n                       bool bMasked))ROM_QEITABLE[13])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_QEIIntClear                                                       \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32IntFlags))ROM_QEITABLE[14])\n#endif\n\n//============================================================================*\n//\n// Macros for calling ROM functions in the SHAMD5 API.\n//\n//============================================================================*\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SHAMD5IntStatus                                                   \\\n        ((uint32_t (*)(uint32_t ui32Base,                                     \\\n                       bool bMasked))ROM_SHAMD5TABLE[0])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SHAMD5ConfigSet                                                   \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Mode))ROM_SHAMD5TABLE[1])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SHAMD5DataProcess                                                 \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t *pui32DataSrc,                                    \\\n                   uint32_t ui32DataLength,                                   \\\n                   uint32_t *pui32HashResult))ROM_SHAMD5TABLE[2])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SHAMD5DataWrite                                                   \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t *pui32Src))ROM_SHAMD5TABLE[3])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SHAMD5DataWriteNonBlocking                                        \\\n        ((bool (*)(uint32_t ui32Base,                                         \\\n                   uint32_t *pui32Src))ROM_SHAMD5TABLE[4])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SHAMD5DMADisable                                                  \\\n        ((void (*)(uint32_t ui32Base))ROM_SHAMD5TABLE[5])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SHAMD5DMAEnable                                                   \\\n        ((void (*)(uint32_t ui32Base))ROM_SHAMD5TABLE[6])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SHAMD5HashLengthSet                                               \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Length))ROM_SHAMD5TABLE[7])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SHAMD5HMACKeySet                                                  \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t *pui32Src))ROM_SHAMD5TABLE[8])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SHAMD5HMACPPKeyGenerate                                           \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t *pui32Key,                                        \\\n                   uint32_t *pui32PPKey))ROM_SHAMD5TABLE[9])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SHAMD5HMACPPKeySet                                                \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t *pui32Src))ROM_SHAMD5TABLE[10])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SHAMD5HMACProcess                                                 \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t *pui32DataSrc,                                    \\\n                   uint32_t ui32DataLength,                                   \\\n                   uint32_t *pui32HashResult))ROM_SHAMD5TABLE[11])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SHAMD5IntClear                                                    \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32IntFlags))ROM_SHAMD5TABLE[12])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SHAMD5IntDisable                                                  \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32IntFlags))ROM_SHAMD5TABLE[13])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SHAMD5IntEnable                                                   \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32IntFlags))ROM_SHAMD5TABLE[14])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SHAMD5Reset                                                       \\\n        ((void (*)(uint32_t ui32Base))ROM_SHAMD5TABLE[15])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SHAMD5ResultRead                                                  \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t *pui32Dest))ROM_SHAMD5TABLE[16])\n#endif\n\n//============================================================================*\n//\n// Macros for calling ROM functions in the SMBus API.\n//\n//============================================================================*\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SMBusMasterIntProcess                                             \\\n        ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[0])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SMBusARPDisable                                                   \\\n        ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[1])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SMBusARPEnable                                                    \\\n        ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[2])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SMBusARPUDIDPacketDecode                                          \\\n        ((void (*)(tSMBusUDID *pUDID,                                         \\\n                   uint8_t *pui8Address,                                      \\\n                   uint8_t *pui8Data))ROM_SMBUSTABLE[3])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SMBusARPUDIDPacketEncode                                          \\\n        ((void (*)(tSMBusUDID *pUDID,                                         \\\n                   uint8_t ui8Address,                                        \\\n                   uint8_t *pui8Data))ROM_SMBUSTABLE[4])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SMBusMasterARPAssignAddress                                       \\\n        ((tSMBusStatus (*)(tSMBus *psSMBus,                                   \\\n                           uint8_t *pui8Data))ROM_SMBUSTABLE[5])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SMBusMasterARPGetUDIDDir                                          \\\n        ((tSMBusStatus (*)(tSMBus *psSMBus,                                   \\\n                           uint8_t ui8TargetAddress,                          \\\n                           uint8_t *pui8Data))ROM_SMBUSTABLE[6])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SMBusMasterARPGetUDIDGen                                          \\\n        ((tSMBusStatus (*)(tSMBus *psSMBus,                                   \\\n                           uint8_t *pui8Data))ROM_SMBUSTABLE[7])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SMBusMasterARPNotifyMaster                                        \\\n        ((tSMBusStatus (*)(tSMBus *psSMBus,                                   \\\n                           uint8_t *pui8Data))ROM_SMBUSTABLE[8])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SMBusMasterARPPrepareToARP                                        \\\n        ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[9])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SMBusMasterARPResetDeviceDir                                      \\\n        ((tSMBusStatus (*)(tSMBus *psSMBus,                                   \\\n                           uint8_t ui8TargetAddress))ROM_SMBUSTABLE[10])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SMBusMasterARPResetDeviceGen                                      \\\n        ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[11])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SMBusMasterBlockProcessCall                                       \\\n        ((tSMBusStatus (*)(tSMBus *psSMBus,                                   \\\n                           uint8_t ui8TargetAddress,                          \\\n                           uint8_t ui8Command,                                \\\n                           uint8_t *pui8TxData,                               \\\n                           uint8_t ui8TxSize,                                 \\\n                           uint8_t *pui8RxData))ROM_SMBUSTABLE[12])\n#endif\n#if defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SMBusMasterBlockRead                                              \\\n        ((tSMBusStatus (*)(tSMBus *psSMBus,                                   \\\n                           uint8_t ui8TargetAddress,                          \\\n                           uint8_t ui8Command,                                \\\n                           uint8_t *pui8Data))ROM_SMBUSTABLE[13])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SMBusMasterBlockWrite                                             \\\n        ((tSMBusStatus (*)(tSMBus *psSMBus,                                   \\\n                           uint8_t ui8TargetAddress,                          \\\n                           uint8_t ui8Command,                                \\\n                           uint8_t *pui8Data,                                 \\\n                           uint8_t ui8Size))ROM_SMBUSTABLE[14])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SMBusMasterByteReceive                                            \\\n        ((tSMBusStatus (*)(tSMBus *psSMBus,                                   \\\n                           uint8_t ui8TargetAddress,                          \\\n                           uint8_t *pui8Data))ROM_SMBUSTABLE[15])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SMBusMasterByteSend                                               \\\n        ((tSMBusStatus (*)(tSMBus *psSMBus,                                   \\\n                           uint8_t ui8TargetAddress,                          \\\n                           uint8_t ui8Data))ROM_SMBUSTABLE[16])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SMBusMasterByteWordRead                                           \\\n        ((tSMBusStatus (*)(tSMBus *psSMBus,                                   \\\n                           uint8_t ui8TargetAddress,                          \\\n                           uint8_t ui8Command,                                \\\n                           uint8_t *pui8Data,                                 \\\n                           uint8_t ui8Size))ROM_SMBUSTABLE[17])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SMBusMasterByteWordWrite                                          \\\n        ((tSMBusStatus (*)(tSMBus *psSMBus,                                   \\\n                           uint8_t ui8TargetAddress,                          \\\n                           uint8_t ui8Command,                                \\\n                           uint8_t *pui8Data,                                 \\\n                           uint8_t ui8Size))ROM_SMBUSTABLE[18])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SMBusMasterHostNotify                                             \\\n        ((tSMBusStatus (*)(tSMBus *psSMBus,                                   \\\n                           uint8_t ui8OwnSlaveAddress,                        \\\n                           uint8_t *pui8Data))ROM_SMBUSTABLE[19])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SMBusMasterI2CRead                                                \\\n        ((tSMBusStatus (*)(tSMBus *psSMBus,                                   \\\n                           uint8_t ui8TargetAddress,                          \\\n                           uint8_t *pui8Data,                                 \\\n                           uint8_t ui8Size))ROM_SMBUSTABLE[20])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SMBusMasterI2CWrite                                               \\\n        ((tSMBusStatus (*)(tSMBus *psSMBus,                                   \\\n                           uint8_t ui8TargetAddress,                          \\\n                           uint8_t *pui8Data,                                 \\\n                           uint8_t ui8Size))ROM_SMBUSTABLE[21])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SMBusMasterI2CWriteRead                                           \\\n        ((tSMBusStatus (*)(tSMBus *psSMBus,                                   \\\n                           uint8_t ui8TargetAddress,                          \\\n                           uint8_t *pui8TxData,                               \\\n                           uint8_t ui8TxSize,                                 \\\n                           uint8_t *pui8RxData,                               \\\n                           uint8_t ui8RxSize))ROM_SMBUSTABLE[22])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SMBusMasterInit                                                   \\\n        ((void (*)(tSMBus *psSMBus,                                           \\\n                   uint32_t ui32I2CBase,                                      \\\n                   uint32_t ui32SMBusClock))ROM_SMBUSTABLE[23])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SMBusMasterIntEnable                                              \\\n        ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[24])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SMBusMasterProcessCall                                            \\\n        ((tSMBusStatus (*)(tSMBus *psSMBus,                                   \\\n                           uint8_t ui8TargetAddress,                          \\\n                           uint8_t ui8Command,                                \\\n                           uint8_t *pui8TxData,                               \\\n                           uint8_t *pui8RxData))ROM_SMBUSTABLE[25])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SMBusMasterQuickCommand                                           \\\n        ((tSMBusStatus (*)(tSMBus *psSMBus,                                   \\\n                           uint8_t ui8TargetAddress,                          \\\n                           bool bData))ROM_SMBUSTABLE[26])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SMBusPECDisable                                                   \\\n        ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[27])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SMBusPECEnable                                                    \\\n        ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[28])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SMBusRxPacketSizeGet                                              \\\n        ((uint8_t (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[29])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SMBusSlaveACKSend                                                 \\\n        ((void (*)(tSMBus *psSMBus,                                           \\\n                   bool bACK))ROM_SMBUSTABLE[30])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SMBusSlaveAddressSet                                              \\\n        ((void (*)(tSMBus *psSMBus,                                           \\\n                   uint8_t ui8AddressNum,                                     \\\n                   uint8_t ui8SlaveAddress))ROM_SMBUSTABLE[31])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SMBusSlaveARPFlagARGet                                            \\\n        ((bool (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[32])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SMBusSlaveARPFlagARSet                                            \\\n        ((void (*)(tSMBus *psSMBus,                                           \\\n                   bool bValue))ROM_SMBUSTABLE[33])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SMBusSlaveARPFlagAVGet                                            \\\n        ((bool (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[34])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SMBusSlaveARPFlagAVSet                                            \\\n        ((void (*)(tSMBus *psSMBus,                                           \\\n                   bool bValue))ROM_SMBUSTABLE[35])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SMBusSlaveBlockTransferDisable                                    \\\n        ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[36])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SMBusSlaveBlockTransferEnable                                     \\\n        ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[37])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SMBusSlaveCommandGet                                              \\\n        ((uint8_t (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[38])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SMBusSlaveI2CDisable                                              \\\n        ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[39])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SMBusSlaveI2CEnable                                               \\\n        ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[40])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SMBusSlaveInit                                                    \\\n        ((void (*)(tSMBus *psSMBus,                                           \\\n                   uint32_t ui32I2CBase))ROM_SMBUSTABLE[41])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SMBusSlaveIntAddressGet                                           \\\n        ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[42])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SMBusSlaveIntEnable                                               \\\n        ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[43])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SMBusSlaveIntProcess                                              \\\n        ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[44])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SMBusSlaveManualACKDisable                                        \\\n        ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[45])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SMBusSlaveManualACKEnable                                         \\\n        ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[46])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SMBusSlaveManualACKStatusGet                                      \\\n        ((bool (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[47])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SMBusSlaveProcessCallDisable                                      \\\n        ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[48])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SMBusSlaveProcessCallEnable                                       \\\n        ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[49])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SMBusSlaveRxBufferSet                                             \\\n        ((void (*)(tSMBus *psSMBus,                                           \\\n                   uint8_t *pui8Data,                                         \\\n                   uint8_t ui8Size))ROM_SMBUSTABLE[50])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SMBusSlaveTransferInit                                            \\\n        ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[51])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SMBusSlaveTxBufferSet                                             \\\n        ((void (*)(tSMBus *psSMBus,                                           \\\n                   uint8_t *pui8Data,                                         \\\n                   uint8_t ui8Size))ROM_SMBUSTABLE[52])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SMBusSlaveUDIDSet                                                 \\\n        ((void (*)(tSMBus *psSMBus,                                           \\\n                   tSMBusUDID *pUDID))ROM_SMBUSTABLE[53])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SMBusStatusGet                                                    \\\n        ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[54])\n#endif\n#if defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SMBusSlaveDataSend                                                \\\n        ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[55])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SMBusFIFOEnable                                                   \\\n        ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[56])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SMBusFIFODisable                                                  \\\n        ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[57])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SMBusDMAEnable                                                    \\\n        ((void (*)(tSMBus *psSMBus,                                           \\\n                   uint8_t ui8TxChannel,                                      \\\n                   uint8_t ui8RxChannel))ROM_SMBUSTABLE[58])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SMBusDMADisable                                                   \\\n        ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[59])\n#endif\n\n//============================================================================*\n//\n// Macros for calling ROM functions in the SPIFlash API.\n//\n//============================================================================*\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SPIFlashIntHandler                                                \\\n        ((uint32_t (*)(tSPIFlashState *pState))ROM_SPIFLASHTABLE[0])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SPIFlashInit                                                      \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Clock,                                        \\\n                   uint32_t ui32BitRate))ROM_SPIFLASHTABLE[1])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SPIFlashWriteStatus                                               \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint8_t ui8Status))ROM_SPIFLASHTABLE[2])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SPIFlashPageProgram                                               \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Addr,                                         \\\n                   const uint8_t *pui8Data,                                   \\\n                   uint32_t ui32Count))ROM_SPIFLASHTABLE[3])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SPIFlashPageProgramNonBlocking                                    \\\n        ((void (*)(tSPIFlashState *pState,                                    \\\n                   uint32_t ui32Base,                                         \\\n                   uint32_t ui32Addr,                                         \\\n                   const uint8_t *pui8Data,                                   \\\n                   uint32_t ui32Count,                                        \\\n                   bool bUseDMA,                                              \\\n                   uint32_t ui32TxChannel))ROM_SPIFLASHTABLE[4])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SPIFlashRead                                                      \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Addr,                                         \\\n                   uint8_t *pui8Data,                                         \\\n                   uint32_t ui32Count))ROM_SPIFLASHTABLE[5])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SPIFlashReadNonBlocking                                           \\\n        ((void (*)(tSPIFlashState *pState,                                    \\\n                   uint32_t ui32Base,                                         \\\n                   uint32_t ui32Addr,                                         \\\n                   uint8_t *pui8Data,                                         \\\n                   uint32_t ui32Count,                                        \\\n                   bool bUseDMA,                                              \\\n                   uint32_t ui32TxChannel,                                    \\\n                   uint32_t ui32RxChannel))ROM_SPIFLASHTABLE[6])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SPIFlashWriteDisable                                              \\\n        ((void (*)(uint32_t ui32Base))ROM_SPIFLASHTABLE[7])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SPIFlashReadStatus                                                \\\n        ((uint8_t (*)(uint32_t ui32Base))ROM_SPIFLASHTABLE[8])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SPIFlashWriteEnable                                               \\\n        ((void (*)(uint32_t ui32Base))ROM_SPIFLASHTABLE[9])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SPIFlashFastRead                                                  \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Addr,                                         \\\n                   uint8_t *pui8Data,                                         \\\n                   uint32_t ui32Count))ROM_SPIFLASHTABLE[10])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SPIFlashFastReadNonBlocking                                       \\\n        ((void (*)(tSPIFlashState *pState,                                    \\\n                   uint32_t ui32Base,                                         \\\n                   uint32_t ui32Addr,                                         \\\n                   uint8_t *pui8Data,                                         \\\n                   uint32_t ui32Count,                                        \\\n                   bool bUseDMA,                                              \\\n                   uint32_t ui32TxChannel,                                    \\\n                   uint32_t ui32RxChannel))ROM_SPIFLASHTABLE[11])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SPIFlashSectorErase                                               \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Addr))ROM_SPIFLASHTABLE[12])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SPIFlashDualRead                                                  \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Addr,                                         \\\n                   uint8_t *pui8Data,                                         \\\n                   uint32_t ui32Count))ROM_SPIFLASHTABLE[13])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SPIFlashDualReadNonBlocking                                       \\\n        ((void (*)(tSPIFlashState *pState,                                    \\\n                   uint32_t ui32Base,                                         \\\n                   uint32_t ui32Addr,                                         \\\n                   uint8_t *pui8Data,                                         \\\n                   uint32_t ui32Count,                                        \\\n                   bool bUseDMA,                                              \\\n                   uint32_t ui32TxChannel,                                    \\\n                   uint32_t ui32RxChannel))ROM_SPIFLASHTABLE[14])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SPIFlashBlockErase32                                              \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Addr))ROM_SPIFLASHTABLE[15])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SPIFlashQuadRead                                                  \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Addr,                                         \\\n                   uint8_t *pui8Data,                                         \\\n                   uint32_t ui32Count))ROM_SPIFLASHTABLE[16])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SPIFlashQuadReadNonBlocking                                       \\\n        ((void (*)(tSPIFlashState *pState,                                    \\\n                   uint32_t ui32Base,                                         \\\n                   uint32_t ui32Addr,                                         \\\n                   uint8_t *pui8Data,                                         \\\n                   uint32_t ui32Count,                                        \\\n                   bool bUseDMA,                                              \\\n                   uint32_t ui32TxChannel,                                    \\\n                   uint32_t ui32RxChannel))ROM_SPIFLASHTABLE[17])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SPIFlashReadID                                                    \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint8_t *pui8ManufacturerID,                               \\\n                   uint16_t *pui16DeviceID))ROM_SPIFLASHTABLE[18])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SPIFlashChipErase                                                 \\\n        ((void (*)(uint32_t ui32Base))ROM_SPIFLASHTABLE[19])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SPIFlashBlockErase64                                              \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Addr))ROM_SPIFLASHTABLE[20])\n#endif\n\n//============================================================================*\n//\n// Macros for calling ROM functions in the SSI API.\n//\n//============================================================================*\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SSIDataPut                                                        \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Data))ROM_SSITABLE[0])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SSIConfigSetExpClk                                                \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32SSIClk,                                       \\\n                   uint32_t ui32Protocol,                                     \\\n                   uint32_t ui32Mode,                                         \\\n                   uint32_t ui32BitRate,                                      \\\n                   uint32_t ui32DataWidth))ROM_SSITABLE[1])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SSIEnable                                                         \\\n        ((void (*)(uint32_t ui32Base))ROM_SSITABLE[2])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SSIDisable                                                        \\\n        ((void (*)(uint32_t ui32Base))ROM_SSITABLE[3])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SSIIntEnable                                                      \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32IntFlags))ROM_SSITABLE[4])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SSIIntDisable                                                     \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32IntFlags))ROM_SSITABLE[5])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SSIIntStatus                                                      \\\n        ((uint32_t (*)(uint32_t ui32Base,                                     \\\n                       bool bMasked))ROM_SSITABLE[6])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SSIIntClear                                                       \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32IntFlags))ROM_SSITABLE[7])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SSIDataPutNonBlocking                                             \\\n        ((int32_t (*)(uint32_t ui32Base,                                      \\\n                      uint32_t ui32Data))ROM_SSITABLE[8])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SSIDataGet                                                        \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t *pui32Data))ROM_SSITABLE[9])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SSIDataGetNonBlocking                                             \\\n        ((int32_t (*)(uint32_t ui32Base,                                      \\\n                      uint32_t *pui32Data))ROM_SSITABLE[10])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_UpdateSSI                                                         \\\n        ((void (*)(void))ROM_SSITABLE[11])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SSIDMAEnable                                                      \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32DMAFlags))ROM_SSITABLE[12])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SSIDMADisable                                                     \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32DMAFlags))ROM_SSITABLE[13])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SSIBusy                                                           \\\n        ((bool (*)(uint32_t ui32Base))ROM_SSITABLE[14])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SSIClockSourceGet                                                 \\\n        ((uint32_t (*)(uint32_t ui32Base))ROM_SSITABLE[15])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SSIClockSourceSet                                                 \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Source))ROM_SSITABLE[16])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SSIAdvModeSet                                                     \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Mode))ROM_SSITABLE[17])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SSIAdvDataPutFrameEnd                                             \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Data))ROM_SSITABLE[18])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SSIAdvDataPutFrameEndNonBlocking                                  \\\n        ((int32_t (*)(uint32_t ui32Base,                                      \\\n                      uint32_t ui32Data))ROM_SSITABLE[19])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SSIAdvFrameHoldEnable                                             \\\n        ((void (*)(uint32_t ui32Base))ROM_SSITABLE[20])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SSIAdvFrameHoldDisable                                            \\\n        ((void (*)(uint32_t ui32Base))ROM_SSITABLE[21])\n#endif\n\n//============================================================================*\n//\n// Macros for calling ROM functions in the SysCtl API.\n//\n//============================================================================*\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SysCtlSleep                                                       \\\n        ((void (*)(void))ROM_SYSCTLTABLE[0])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SysCtlSRAMSizeGet                                                 \\\n        ((uint32_t (*)(void))ROM_SYSCTLTABLE[1])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SysCtlFlashSizeGet                                                \\\n        ((uint32_t (*)(void))ROM_SYSCTLTABLE[2])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SysCtlPeripheralPresent                                           \\\n        ((bool (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[4])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SysCtlPeripheralReset                                             \\\n        ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[5])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SysCtlPeripheralEnable                                            \\\n        ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[6])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SysCtlPeripheralDisable                                           \\\n        ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[7])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SysCtlPeripheralSleepEnable                                       \\\n        ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[8])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SysCtlPeripheralSleepDisable                                      \\\n        ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[9])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SysCtlPeripheralDeepSleepEnable                                   \\\n        ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[10])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SysCtlPeripheralDeepSleepDisable                                  \\\n        ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[11])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SysCtlPeripheralClockGating                                       \\\n        ((void (*)(bool bEnable))ROM_SYSCTLTABLE[12])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SysCtlIntEnable                                                   \\\n        ((void (*)(uint32_t ui32Ints))ROM_SYSCTLTABLE[13])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SysCtlIntDisable                                                  \\\n        ((void (*)(uint32_t ui32Ints))ROM_SYSCTLTABLE[14])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SysCtlIntClear                                                    \\\n        ((void (*)(uint32_t ui32Ints))ROM_SYSCTLTABLE[15])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SysCtlIntStatus                                                   \\\n        ((uint32_t (*)(bool bMasked))ROM_SYSCTLTABLE[16])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SysCtlReset                                                       \\\n        ((void (*)(void))ROM_SYSCTLTABLE[19])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SysCtlDeepSleep                                                   \\\n        ((void (*)(void))ROM_SYSCTLTABLE[20])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SysCtlResetCauseGet                                               \\\n        ((uint32_t (*)(void))ROM_SYSCTLTABLE[21])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SysCtlResetCauseClear                                             \\\n        ((void (*)(uint32_t ui32Causes))ROM_SYSCTLTABLE[22])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2)\n#define ROM_SysCtlClockSet                                                    \\\n        ((void (*)(uint32_t ui32Config))ROM_SYSCTLTABLE[23])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2)\n#define ROM_SysCtlClockGet                                                    \\\n        ((uint32_t (*)(void))ROM_SYSCTLTABLE[24])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2)\n#define ROM_SysCtlPWMClockSet                                                 \\\n        ((void (*)(uint32_t ui32Config))ROM_SYSCTLTABLE[25])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2)\n#define ROM_SysCtlPWMClockGet                                                 \\\n        ((uint32_t (*)(void))ROM_SYSCTLTABLE[26])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2)\n#define ROM_SysCtlUSBPLLEnable                                                \\\n        ((void (*)(void))ROM_SYSCTLTABLE[31])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2)\n#define ROM_SysCtlUSBPLLDisable                                               \\\n        ((void (*)(void))ROM_SYSCTLTABLE[32])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SysCtlDelay                                                       \\\n        ((void (*)(uint32_t ui32Count))ROM_SYSCTLTABLE[34])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SysCtlPeripheralReady                                             \\\n        ((bool (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[35])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SysCtlPeripheralPowerOn                                           \\\n        ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[36])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SysCtlPeripheralPowerOff                                          \\\n        ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[37])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SysCtlMOSCConfigSet                                               \\\n        ((void (*)(uint32_t ui32Config))ROM_SYSCTLTABLE[44])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SysCtlPIOSCCalibrate                                              \\\n        ((uint32_t (*)(uint32_t ui32Type))ROM_SYSCTLTABLE[45])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2)\n#define ROM_SysCtlDeepSleepClockSet                                           \\\n        ((void (*)(uint32_t ui32Config))ROM_SYSCTLTABLE[46])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SysCtlDeepSleepClockConfigSet                                     \\\n        ((void (*)(uint32_t ui32Div,                                          \\\n                   uint32_t ui32Config))ROM_SYSCTLTABLE[47])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SysCtlClockFreqSet                                                \\\n        ((uint32_t (*)(uint32_t ui32Config,                                   \\\n                       uint32_t ui32SysClock))ROM_SYSCTLTABLE[48])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SysCtlResetBehaviorSet                                            \\\n        ((void (*)(uint32_t ui32Behavior))ROM_SYSCTLTABLE[51])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SysCtlResetBehaviorGet                                            \\\n        ((uint32_t (*)(void))ROM_SYSCTLTABLE[52])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SysCtlFlashSectorSizeGet                                          \\\n        ((uint32_t (*)(void))ROM_SYSCTLTABLE[54])\n#endif\n#if defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SysCtlVoltageEventConfig                                          \\\n        ((void (*)(uint32_t ui32Config))ROM_SYSCTLTABLE[55])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SysCtlVoltageEventStatus                                          \\\n        ((uint32_t (*)(void))ROM_SYSCTLTABLE[56])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SysCtlVoltageEventClear                                           \\\n        ((void (*)(uint32_t ui32Status))ROM_SYSCTLTABLE[57])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SysCtlNMIStatus                                                   \\\n        ((uint32_t (*)(void))ROM_SYSCTLTABLE[58])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SysCtlNMIClear                                                    \\\n        ((void (*)(uint32_t ui32Status))ROM_SYSCTLTABLE[59])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SysCtlClockOutConfig                                              \\\n        ((void (*)(uint32_t ui32Config,                                       \\\n                   uint32_t ui32Div))ROM_SYSCTLTABLE[60])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SysCtlAltClkConfig                                                \\\n        ((void (*)(uint32_t ui32Config))ROM_SYSCTLTABLE[61])\n#endif\n\n//============================================================================*\n//\n// Macros for calling ROM functions in the SysExc API.\n//\n//============================================================================*\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SysExcIntStatus                                                   \\\n        ((uint32_t (*)(bool bMasked))ROM_SYSEXCTABLE[0])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SysExcIntClear                                                    \\\n        ((void (*)(uint32_t ui32IntFlags))ROM_SYSEXCTABLE[1])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SysExcIntDisable                                                  \\\n        ((void (*)(uint32_t ui32IntFlags))ROM_SYSEXCTABLE[2])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SysExcIntEnable                                                   \\\n        ((void (*)(uint32_t ui32IntFlags))ROM_SYSEXCTABLE[3])\n#endif\n\n//============================================================================*\n//\n// Macros for calling ROM functions in the SysTick API.\n//\n//============================================================================*\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SysTickValueGet                                                   \\\n        ((uint32_t (*)(void))ROM_SYSTICKTABLE[0])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SysTickEnable                                                     \\\n        ((void (*)(void))ROM_SYSTICKTABLE[1])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SysTickDisable                                                    \\\n        ((void (*)(void))ROM_SYSTICKTABLE[2])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SysTickIntEnable                                                  \\\n        ((void (*)(void))ROM_SYSTICKTABLE[3])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SysTickIntDisable                                                 \\\n        ((void (*)(void))ROM_SYSTICKTABLE[4])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SysTickPeriodSet                                                  \\\n        ((void (*)(uint32_t ui32Period))ROM_SYSTICKTABLE[5])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_SysTickPeriodGet                                                  \\\n        ((uint32_t (*)(void))ROM_SYSTICKTABLE[6])\n#endif\n\n//============================================================================*\n//\n// Macros for calling ROM functions in the Timer API.\n//\n//============================================================================*\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_TimerIntClear                                                     \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32IntFlags))ROM_TIMERTABLE[0])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_TimerEnable                                                       \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Timer))ROM_TIMERTABLE[1])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_TimerDisable                                                      \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Timer))ROM_TIMERTABLE[2])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_TimerConfigure                                                    \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Config))ROM_TIMERTABLE[3])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_TimerControlLevel                                                 \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Timer,                                        \\\n                   bool bInvert))ROM_TIMERTABLE[4])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1)\n#define ROM_TimerControlTrigger                                               \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Timer,                                        \\\n                   bool bEnable))ROM_TIMERTABLE[5])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_TimerControlEvent                                                 \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Timer,                                        \\\n                   uint32_t ui32Event))ROM_TIMERTABLE[6])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_TimerControlStall                                                 \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Timer,                                        \\\n                   bool bStall))ROM_TIMERTABLE[7])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_TimerRTCEnable                                                    \\\n        ((void (*)(uint32_t ui32Base))ROM_TIMERTABLE[8])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_TimerRTCDisable                                                   \\\n        ((void (*)(uint32_t ui32Base))ROM_TIMERTABLE[9])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_TimerPrescaleSet                                                  \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Timer,                                        \\\n                   uint32_t ui32Value))ROM_TIMERTABLE[10])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_TimerPrescaleGet                                                  \\\n        ((uint32_t (*)(uint32_t ui32Base,                                     \\\n                       uint32_t ui32Timer))ROM_TIMERTABLE[11])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_TimerPrescaleMatchSet                                             \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Timer,                                        \\\n                   uint32_t ui32Value))ROM_TIMERTABLE[12])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_TimerPrescaleMatchGet                                             \\\n        ((uint32_t (*)(uint32_t ui32Base,                                     \\\n                       uint32_t ui32Timer))ROM_TIMERTABLE[13])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_TimerLoadSet                                                      \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Timer,                                        \\\n                   uint32_t ui32Value))ROM_TIMERTABLE[14])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_TimerLoadGet                                                      \\\n        ((uint32_t (*)(uint32_t ui32Base,                                     \\\n                       uint32_t ui32Timer))ROM_TIMERTABLE[15])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_TimerValueGet                                                     \\\n        ((uint32_t (*)(uint32_t ui32Base,                                     \\\n                       uint32_t ui32Timer))ROM_TIMERTABLE[16])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_TimerMatchSet                                                     \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Timer,                                        \\\n                   uint32_t ui32Value))ROM_TIMERTABLE[17])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_TimerMatchGet                                                     \\\n        ((uint32_t (*)(uint32_t ui32Base,                                     \\\n                       uint32_t ui32Timer))ROM_TIMERTABLE[18])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_TimerIntEnable                                                    \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32IntFlags))ROM_TIMERTABLE[19])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_TimerIntDisable                                                   \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32IntFlags))ROM_TIMERTABLE[20])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_TimerIntStatus                                                    \\\n        ((uint32_t (*)(uint32_t ui32Base,                                     \\\n                       bool bMasked))ROM_TIMERTABLE[21])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_TimerControlWaitOnTrigger                                         \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Timer,                                        \\\n                   bool bWait))ROM_TIMERTABLE[22])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2)\n#define ROM_TimerLoadSet64                                                    \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint64_t ui64Value))ROM_TIMERTABLE[23])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2)\n#define ROM_TimerLoadGet64                                                    \\\n        ((uint64_t (*)(uint32_t ui32Base))ROM_TIMERTABLE[24])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2)\n#define ROM_TimerValueGet64                                                   \\\n        ((uint64_t (*)(uint32_t ui32Base))ROM_TIMERTABLE[25])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2)\n#define ROM_TimerMatchSet64                                                   \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint64_t ui64Value))ROM_TIMERTABLE[26])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2)\n#define ROM_TimerMatchGet64                                                   \\\n        ((uint64_t (*)(uint32_t ui32Base))ROM_TIMERTABLE[27])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_TimerClockSourceGet                                               \\\n        ((uint32_t (*)(uint32_t ui32Base))ROM_TIMERTABLE[28])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_TimerClockSourceSet                                               \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Source))ROM_TIMERTABLE[29])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_TimerADCEventGet                                                  \\\n        ((uint32_t (*)(uint32_t ui32Base))ROM_TIMERTABLE[30])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_TimerADCEventSet                                                  \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32ADCEvent))ROM_TIMERTABLE[31])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_TimerDMAEventGet                                                  \\\n        ((uint32_t (*)(uint32_t ui32Base))ROM_TIMERTABLE[32])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_TimerDMAEventSet                                                  \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32DMAEvent))ROM_TIMERTABLE[33])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_TimerSynchronize                                                  \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Timers))ROM_TIMERTABLE[34])\n#endif\n\n//============================================================================*\n//\n// Macros for calling ROM functions in the UART API.\n//\n//============================================================================*\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_UARTCharPut                                                       \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   unsigned char ucData))ROM_UARTTABLE[0])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_UARTParityModeSet                                                 \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Parity))ROM_UARTTABLE[1])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_UARTParityModeGet                                                 \\\n        ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[2])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_UARTFIFOLevelSet                                                  \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32TxLevel,                                      \\\n                   uint32_t ui32RxLevel))ROM_UARTTABLE[3])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_UARTFIFOLevelGet                                                  \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t *pui32TxLevel,                                    \\\n                   uint32_t *pui32RxLevel))ROM_UARTTABLE[4])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_UARTConfigSetExpClk                                               \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32UARTClk,                                      \\\n                   uint32_t ui32Baud,                                         \\\n                   uint32_t ui32Config))ROM_UARTTABLE[5])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_UARTConfigGetExpClk                                               \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32UARTClk,                                      \\\n                   uint32_t *pui32Baud,                                       \\\n                   uint32_t *pui32Config))ROM_UARTTABLE[6])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_UARTEnable                                                        \\\n        ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[7])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_UARTDisable                                                       \\\n        ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[8])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_UARTEnableSIR                                                     \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   bool bLowPower))ROM_UARTTABLE[9])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_UARTDisableSIR                                                    \\\n        ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[10])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_UARTCharsAvail                                                    \\\n        ((bool (*)(uint32_t ui32Base))ROM_UARTTABLE[11])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_UARTSpaceAvail                                                    \\\n        ((bool (*)(uint32_t ui32Base))ROM_UARTTABLE[12])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_UARTCharGetNonBlocking                                            \\\n        ((int32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[13])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_UARTCharGet                                                       \\\n        ((int32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[14])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_UARTCharPutNonBlocking                                            \\\n        ((bool (*)(uint32_t ui32Base,                                         \\\n                   unsigned char ucData))ROM_UARTTABLE[15])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_UARTBreakCtl                                                      \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   bool bBreakState))ROM_UARTTABLE[16])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_UARTIntEnable                                                     \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32IntFlags))ROM_UARTTABLE[17])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_UARTIntDisable                                                    \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32IntFlags))ROM_UARTTABLE[18])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_UARTIntStatus                                                     \\\n        ((uint32_t (*)(uint32_t ui32Base,                                     \\\n                       bool bMasked))ROM_UARTTABLE[19])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_UARTIntClear                                                      \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32IntFlags))ROM_UARTTABLE[20])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_UpdateUART                                                        \\\n        ((void (*)(void))ROM_UARTTABLE[21])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_UARTDMAEnable                                                     \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32DMAFlags))ROM_UARTTABLE[22])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_UARTDMADisable                                                    \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32DMAFlags))ROM_UARTTABLE[23])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_UARTFIFOEnable                                                    \\\n        ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[24])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_UARTFIFODisable                                                   \\\n        ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[25])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_UARTBusy                                                          \\\n        ((bool (*)(uint32_t ui32Base))ROM_UARTTABLE[26])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_UARTTxIntModeSet                                                  \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Mode))ROM_UARTTABLE[27])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_UARTTxIntModeGet                                                  \\\n        ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[28])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_UARTRxErrorGet                                                    \\\n        ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[29])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_UARTRxErrorClear                                                  \\\n        ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[30])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_UARTClockSourceSet                                                \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Source))ROM_UARTTABLE[31])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_UARTClockSourceGet                                                \\\n        ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[32])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_UART9BitEnable                                                    \\\n        ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[33])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_UART9BitDisable                                                   \\\n        ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[34])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_UART9BitAddrSet                                                   \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint8_t ui8Addr,                                           \\\n                   uint8_t ui8Mask))ROM_UARTTABLE[35])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_UART9BitAddrSend                                                  \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint8_t ui8Addr))ROM_UARTTABLE[36])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_UARTSmartCardDisable                                              \\\n        ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[37])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_UARTSmartCardEnable                                               \\\n        ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[38])\n#endif\n#if defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_UARTModemControlClear                                             \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Control))ROM_UARTTABLE[39])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_UARTModemControlGet                                               \\\n        ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[40])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_UARTModemControlSet                                               \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Control))ROM_UARTTABLE[41])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_UARTModemStatusGet                                                \\\n        ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[42])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_UARTFlowControlGet                                                \\\n        ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[43])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_UARTFlowControlSet                                                \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Mode))ROM_UARTTABLE[44])\n#endif\n\n//============================================================================*\n//\n// Macros for calling ROM functions in the uDMA API.\n//\n//============================================================================*\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_uDMAChannelTransferSet                                            \\\n        ((void (*)(uint32_t ui32ChannelStructIndex,                           \\\n                   uint32_t ui32Mode,                                         \\\n                   void *pvSrcAddr,                                           \\\n                   void *pvDstAddr,                                           \\\n                   uint32_t ui32TransferSize))ROM_UDMATABLE[0])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_uDMAEnable                                                        \\\n        ((void (*)(void))ROM_UDMATABLE[1])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_uDMADisable                                                       \\\n        ((void (*)(void))ROM_UDMATABLE[2])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_uDMAErrorStatusGet                                                \\\n        ((uint32_t (*)(void))ROM_UDMATABLE[3])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_uDMAErrorStatusClear                                              \\\n        ((void (*)(void))ROM_UDMATABLE[4])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_uDMAChannelEnable                                                 \\\n        ((void (*)(uint32_t ui32ChannelNum))ROM_UDMATABLE[5])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_uDMAChannelDisable                                                \\\n        ((void (*)(uint32_t ui32ChannelNum))ROM_UDMATABLE[6])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_uDMAChannelIsEnabled                                              \\\n        ((bool (*)(uint32_t ui32ChannelNum))ROM_UDMATABLE[7])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_uDMAControlBaseSet                                                \\\n        ((void (*)(void *pControlTable))ROM_UDMATABLE[8])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_uDMAControlBaseGet                                                \\\n        ((void * (*)(void))ROM_UDMATABLE[9])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_uDMAChannelRequest                                                \\\n        ((void (*)(uint32_t ui32ChannelNum))ROM_UDMATABLE[10])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_uDMAChannelAttributeEnable                                        \\\n        ((void (*)(uint32_t ui32ChannelNum,                                   \\\n                   uint32_t ui32Attr))ROM_UDMATABLE[11])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_uDMAChannelAttributeDisable                                       \\\n        ((void (*)(uint32_t ui32ChannelNum,                                   \\\n                   uint32_t ui32Attr))ROM_UDMATABLE[12])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_uDMAChannelAttributeGet                                           \\\n        ((uint32_t (*)(uint32_t ui32ChannelNum))ROM_UDMATABLE[13])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_uDMAChannelControlSet                                             \\\n        ((void (*)(uint32_t ui32ChannelStructIndex,                           \\\n                   uint32_t ui32Control))ROM_UDMATABLE[14])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_uDMAChannelSizeGet                                                \\\n        ((uint32_t (*)(uint32_t ui32ChannelStructIndex))ROM_UDMATABLE[15])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_uDMAChannelModeGet                                                \\\n        ((uint32_t (*)(uint32_t ui32ChannelStructIndex))ROM_UDMATABLE[16])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_uDMAChannelSelectSecondary                                        \\\n        ((void (*)(uint32_t ui32SecPeriphs))ROM_UDMATABLE[17])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_uDMAChannelSelectDefault                                          \\\n        ((void (*)(uint32_t ui32DefPeriphs))ROM_UDMATABLE[18])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_uDMAIntStatus                                                     \\\n        ((uint32_t (*)(void))ROM_UDMATABLE[19])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_uDMAIntClear                                                      \\\n        ((void (*)(uint32_t ui32ChanMask))ROM_UDMATABLE[20])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_uDMAControlAlternateBaseGet                                       \\\n        ((void * (*)(void))ROM_UDMATABLE[21])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_uDMAChannelScatterGatherSet                                       \\\n        ((void (*)(uint32_t ui32ChannelNum,                                   \\\n                   uint32_t ui32TaskCount,                                    \\\n                   void *pvTaskList,                                          \\\n                   uint32_t ui32IsPeriphSG))ROM_UDMATABLE[22])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_uDMAChannelAssign                                                 \\\n        ((void (*)(uint32_t ui32Mapping))ROM_UDMATABLE[23])\n#endif\n\n//============================================================================*\n//\n// Macros for calling ROM functions in the USB API.\n//\n//============================================================================*\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBDevAddrGet                                                     \\\n        ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[1])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBDevAddrSet                                                     \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Address))ROM_USBTABLE[2])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBDevConnect                                                     \\\n        ((void (*)(uint32_t ui32Base))ROM_USBTABLE[3])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBDevDisconnect                                                  \\\n        ((void (*)(uint32_t ui32Base))ROM_USBTABLE[4])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBDevEndpointConfigSet                                           \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Endpoint,                                     \\\n                   uint32_t ui32MaxPacketSize,                                \\\n                   uint32_t ui32Flags))ROM_USBTABLE[5])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBDevEndpointDataAck                                             \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Endpoint,                                     \\\n                   bool bIsLastPacket))ROM_USBTABLE[6])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBDevEndpointStall                                               \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Endpoint,                                     \\\n                   uint32_t ui32Flags))ROM_USBTABLE[7])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBDevEndpointStallClear                                          \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Endpoint,                                     \\\n                   uint32_t ui32Flags))ROM_USBTABLE[8])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBDevEndpointStatusClear                                         \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Endpoint,                                     \\\n                   uint32_t ui32Flags))ROM_USBTABLE[9])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBEndpointDataGet                                                \\\n        ((int32_t (*)(uint32_t ui32Base,                                      \\\n                      uint32_t ui32Endpoint,                                  \\\n                      uint8_t *pui8Data,                                      \\\n                      uint32_t *pui32Size))ROM_USBTABLE[10])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBEndpointDataPut                                                \\\n        ((int32_t (*)(uint32_t ui32Base,                                      \\\n                      uint32_t ui32Endpoint,                                  \\\n                      uint8_t *pui8Data,                                      \\\n                      uint32_t ui32Size))ROM_USBTABLE[11])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBEndpointDataSend                                               \\\n        ((int32_t (*)(uint32_t ui32Base,                                      \\\n                      uint32_t ui32Endpoint,                                  \\\n                      uint32_t ui32TransType))ROM_USBTABLE[12])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBEndpointDataToggleClear                                        \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Endpoint,                                     \\\n                   uint32_t ui32Flags))ROM_USBTABLE[13])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBEndpointStatus                                                 \\\n        ((uint32_t (*)(uint32_t ui32Base,                                     \\\n                       uint32_t ui32Endpoint))ROM_USBTABLE[14])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBFIFOAddrGet                                                    \\\n        ((uint32_t (*)(uint32_t ui32Base,                                     \\\n                       uint32_t ui32Endpoint))ROM_USBTABLE[15])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBFIFOConfigGet                                                  \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Endpoint,                                     \\\n                   uint32_t *pui32FIFOAddress,                                \\\n                   uint32_t *pui32FIFOSize,                                   \\\n                   uint32_t ui32Flags))ROM_USBTABLE[16])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBFIFOConfigSet                                                  \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Endpoint,                                     \\\n                   uint32_t ui32FIFOAddress,                                  \\\n                   uint32_t ui32FIFOSize,                                     \\\n                   uint32_t ui32Flags))ROM_USBTABLE[17])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBFIFOFlush                                                      \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Endpoint,                                     \\\n                   uint32_t ui32Flags))ROM_USBTABLE[18])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBFrameNumberGet                                                 \\\n        ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[19])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBHostAddrGet                                                    \\\n        ((uint32_t (*)(uint32_t ui32Base,                                     \\\n                       uint32_t ui32Endpoint,                                 \\\n                       uint32_t ui32Flags))ROM_USBTABLE[20])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBHostAddrSet                                                    \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Endpoint,                                     \\\n                   uint32_t ui32Addr,                                         \\\n                   uint32_t ui32Flags))ROM_USBTABLE[21])\n#endif\n#if defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBHostEndpointConfig                                             \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Endpoint,                                     \\\n                   uint32_t ui32MaxPacketSize,                                \\\n                   uint32_t ui32NAKPollInterval,                              \\\n                   uint32_t ui32TargetEndpoint,                               \\\n                   uint32_t ui32Flags))ROM_USBTABLE[22])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBHostEndpointDataAck                                            \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Endpoint))ROM_USBTABLE[23])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBHostEndpointDataToggle                                         \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Endpoint,                                     \\\n                   bool bDataToggle,                                          \\\n                   uint32_t ui32Flags))ROM_USBTABLE[24])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBHostEndpointStatusClear                                        \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Endpoint,                                     \\\n                   uint32_t ui32Flags))ROM_USBTABLE[25])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBHostHubAddrGet                                                 \\\n        ((uint32_t (*)(uint32_t ui32Base,                                     \\\n                       uint32_t ui32Endpoint,                                 \\\n                       uint32_t ui32Flags))ROM_USBTABLE[26])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBHostHubAddrSet                                                 \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Endpoint,                                     \\\n                   uint32_t ui32Addr,                                         \\\n                   uint32_t ui32Flags))ROM_USBTABLE[27])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBHostPwrDisable                                                 \\\n        ((void (*)(uint32_t ui32Base))ROM_USBTABLE[28])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBHostPwrEnable                                                  \\\n        ((void (*)(uint32_t ui32Base))ROM_USBTABLE[29])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBHostPwrConfig                                                  \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Flags))ROM_USBTABLE[30])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBHostPwrFaultDisable                                            \\\n        ((void (*)(uint32_t ui32Base))ROM_USBTABLE[31])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBHostPwrFaultEnable                                             \\\n        ((void (*)(uint32_t ui32Base))ROM_USBTABLE[32])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBHostRequestIN                                                  \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Endpoint))ROM_USBTABLE[33])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBHostRequestStatus                                              \\\n        ((void (*)(uint32_t ui32Base))ROM_USBTABLE[34])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBHostReset                                                      \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   bool bStart))ROM_USBTABLE[35])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBHostResume                                                     \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   bool bStart))ROM_USBTABLE[36])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBHostSpeedGet                                                   \\\n        ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[37])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBHostSuspend                                                    \\\n        ((void (*)(uint32_t ui32Base))ROM_USBTABLE[38])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBDevEndpointConfigGet                                           \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Endpoint,                                     \\\n                   uint32_t *pui32MaxPacketSize,                              \\\n                   uint32_t *pui32Flags))ROM_USBTABLE[41])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBEndpointDMAEnable                                              \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Endpoint,                                     \\\n                   uint32_t ui32Flags))ROM_USBTABLE[42])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBEndpointDMADisable                                             \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Endpoint,                                     \\\n                   uint32_t ui32Flags))ROM_USBTABLE[43])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBEndpointDataAvail                                              \\\n        ((uint32_t (*)(uint32_t ui32Base,                                     \\\n                       uint32_t ui32Endpoint))ROM_USBTABLE[44])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBModeGet                                                        \\\n        ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[46])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBEndpointDMAChannel                                             \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Endpoint,                                     \\\n                   uint32_t ui32Channel))ROM_USBTABLE[47])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBIntDisableControl                                              \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32IntFlags))ROM_USBTABLE[48])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBIntEnableControl                                               \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32IntFlags))ROM_USBTABLE[49])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBIntStatusControl                                               \\\n        ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[50])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBIntDisableEndpoint                                             \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32IntFlags))ROM_USBTABLE[51])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBIntEnableEndpoint                                              \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32IntFlags))ROM_USBTABLE[52])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBIntStatusEndpoint                                              \\\n        ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[53])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBHostMode                                                       \\\n        ((void (*)(uint32_t ui32Base))ROM_USBTABLE[54])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBDevMode                                                        \\\n        ((void (*)(uint32_t ui32Base))ROM_USBTABLE[55])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBPHYPowerOff                                                    \\\n        ((void (*)(uint32_t ui32Base))ROM_USBTABLE[56])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBPHYPowerOn                                                     \\\n        ((void (*)(uint32_t ui32Base))ROM_USBTABLE[57])\n#endif\n#if defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_UpdateUSB                                                         \\\n        ((void (*)(uint8_t *pui8DescriptorInfo))ROM_USBTABLE[58])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBOTGMode                                                        \\\n        ((void (*)(uint32_t ui32Base))ROM_USBTABLE[59])\n#endif\n#if defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBHostRequestINClear                                             \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Endpoint))ROM_USBTABLE[60])\n#endif\n#if defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBNumEndpointsGet                                                \\\n        ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[61])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBClockDisable                                                   \\\n        ((void (*)(uint32_t ui32Base))ROM_USBTABLE[62])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBClockEnable                                                    \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Div,                                          \\\n                   uint32_t ui32Flags))ROM_USBTABLE[63])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBControllerVersion                                              \\\n        ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[64])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBDevLPMConfig                                                   \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Config))ROM_USBTABLE[65])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBDevLPMDisable                                                  \\\n        ((void (*)(uint32_t ui32Base))ROM_USBTABLE[66])\n#endif\n#if defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBDevLPMEnable                                                   \\\n        ((void (*)(uint32_t ui32Base))ROM_USBTABLE[67])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBDevLPMRemoteWake                                               \\\n        ((void (*)(uint32_t ui32Base))ROM_USBTABLE[68])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBDevSpeedGet                                                    \\\n        ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[69])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBDMAChannelAddressGet                                           \\\n        ((void * (*)(uint32_t ui32Base,                                       \\\n                     uint32_t ui32Channel))ROM_USBTABLE[70])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBDMAChannelAddressSet                                           \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Channel,                                      \\\n                   void *pvAddress))ROM_USBTABLE[71])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBDMAChannelConfigSet                                            \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Channel,                                      \\\n                   uint32_t ui32Endpoint,                                     \\\n                   uint32_t ui32Config))ROM_USBTABLE[72])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBDMAChannelDisable                                              \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Channel))ROM_USBTABLE[73])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBDMAChannelEnable                                               \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Channel))ROM_USBTABLE[74])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBDMAChannelIntDisable                                           \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Channel))ROM_USBTABLE[75])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBDMAChannelIntEnable                                            \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Channel))ROM_USBTABLE[76])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBDMAChannelCountGet                                             \\\n        ((uint32_t (*)(uint32_t ui32Base,                                     \\\n                       uint32_t ui32Channel))ROM_USBTABLE[77])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBDMAChannelCountSet                                             \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Count,                                        \\\n                   uint32_t ui32Channel))ROM_USBTABLE[78])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBDMAChannelIntStatus                                            \\\n        ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[79])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBDMAChannelStatus                                               \\\n        ((uint32_t (*)(uint32_t ui32Base,                                     \\\n                       uint32_t ui32Channel))ROM_USBTABLE[80])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBDMAChannelStatusClear                                          \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Channel,                                      \\\n                   uint32_t ui32Status))ROM_USBTABLE[81])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBHighSpeed                                                      \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   bool bEnable))ROM_USBTABLE[82])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBHostEndpointPing                                               \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Endpoint,                                     \\\n                   bool bEnable))ROM_USBTABLE[83])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBHostEndpointSpeed                                              \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Endpoint,                                     \\\n                   uint32_t ui32Flags))ROM_USBTABLE[84])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBHostLPMConfig                                                  \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32ResumeTime,                                   \\\n                   uint32_t ui32Config))ROM_USBTABLE[85])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBHostLPMResume                                                  \\\n        ((void (*)(uint32_t ui32Base))ROM_USBTABLE[86])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBHostLPMSend                                                    \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Address,                                      \\\n                   uint32_t uiEndpoint))ROM_USBTABLE[87])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBLPMIntDisable                                                  \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Ints))ROM_USBTABLE[88])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBLPMIntEnable                                                   \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Ints))ROM_USBTABLE[89])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBLPMIntStatus                                                   \\\n        ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[90])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBLPMLinkStateGet                                                \\\n        ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[91])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBEndpointPacketCountSet                                         \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Endpoint,                                     \\\n                   uint32_t ui32Count))ROM_USBTABLE[92])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBULPIConfig                                                     \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Config))ROM_USBTABLE[93])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBULPIDisable                                                    \\\n        ((void (*)(uint32_t ui32Base))ROM_USBTABLE[94])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBULPIEnable                                                     \\\n        ((void (*)(uint32_t ui32Base))ROM_USBTABLE[95])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBULPIRegRead                                                    \\\n        ((uint8_t (*)(uint32_t ui32Base,                                      \\\n                      uint8_t ui8Reg))ROM_USBTABLE[96])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBULPIRegWrite                                                   \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint8_t ui8Reg,                                            \\\n                   uint8_t ui8Data))ROM_USBTABLE[97])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBOTGSessionRequest                                              \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   bool bStart))ROM_USBTABLE[98])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBDMANumChannels                                                 \\\n        ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[99])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBEndpointDMAConfigSet                                           \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Endpoint,                                     \\\n                   uint32_t ui32Config))ROM_USBTABLE[100])\n#endif\n#if defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBLPMRemoteWakeEnabled                                           \\\n        ((bool (*)(uint32_t ui32Base))ROM_USBTABLE[102])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_USBModeConfig                                                     \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Mode))ROM_USBTABLE[103])\n#endif\n\n//============================================================================*\n//\n// Macros for calling ROM functions in the Watchdog API.\n//\n//============================================================================*\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_WatchdogIntClear                                                  \\\n        ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[0])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_WatchdogRunning                                                   \\\n        ((bool (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[1])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_WatchdogEnable                                                    \\\n        ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[2])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_WatchdogResetEnable                                               \\\n        ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[3])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_WatchdogResetDisable                                              \\\n        ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[4])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_WatchdogLock                                                      \\\n        ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[5])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_WatchdogUnlock                                                    \\\n        ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[6])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_WatchdogLockState                                                 \\\n        ((bool (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[7])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_WatchdogReloadSet                                                 \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32LoadVal))ROM_WATCHDOGTABLE[8])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_WatchdogReloadGet                                                 \\\n        ((uint32_t (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[9])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_WatchdogValueGet                                                  \\\n        ((uint32_t (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[10])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_WatchdogIntEnable                                                 \\\n        ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[11])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_WatchdogIntStatus                                                 \\\n        ((uint32_t (*)(uint32_t ui32Base,                                     \\\n                       bool bMasked))ROM_WATCHDOGTABLE[12])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_WatchdogStallEnable                                               \\\n        ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[13])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_WatchdogStallDisable                                              \\\n        ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[14])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_WatchdogIntTypeSet                                                \\\n        ((void (*)(uint32_t ui32Base,                                         \\\n                   uint32_t ui32Type))ROM_WATCHDOGTABLE[15])\n#endif\n\n//============================================================================*\n//\n// Macros for calling ROM functions in the Software API.\n//\n//============================================================================*\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_Crc16Array                                                        \\\n        ((uint16_t (*)(uint32_t ui32WordLen,                                  \\\n                       const uint32_t *pui32Data))ROM_SOFTWARETABLE[1])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_Crc16Array3                                                       \\\n        ((void (*)(uint32_t ui32WordLen,                                      \\\n                   const uint32_t *pui32Data,                                 \\\n                   uint16_t *pui16Crc3))ROM_SOFTWARETABLE[2])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_Crc16                                                             \\\n        ((uint16_t (*)(uint16_t ui16Crc,                                      \\\n                       const uint8_t *pui8Data,                               \\\n                       uint32_t ui32Count))ROM_SOFTWARETABLE[3])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_Crc8CCITT                                                         \\\n        ((uint8_t (*)(uint8_t ui8Crc,                                         \\\n                      const uint8_t *pui8Data,                                \\\n                      uint32_t ui32Count))ROM_SOFTWARETABLE[4])\n#endif\n#if defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_Crc32                                                             \\\n        ((uint32_t (*)(uint32_t ui32Crc,                                      \\\n                       const uint8_t *pui8Data,                               \\\n                       uint32_t ui32Count))ROM_SOFTWARETABLE[5])\n#endif\n#if defined(TARGET_IS_TM4C123_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RA3) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB1) ||                                         \\\n    defined(TARGET_IS_TM4C123_RB2) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA0) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA1) ||                                         \\\n    defined(TARGET_IS_TM4C129_RA2)\n#define ROM_pvAESTable                                                        \\\n        ((void *)&(ROM_SOFTWARETABLE[7]))\n#endif\n\n#endif // __DRIVERLIB_ROM_H__\n"
  },
  {
    "path": "3rd_party/ek-tm4c123gxl/sysctl.h",
    "content": "//============================================================================*\n//\n// sysctl.h - Prototypes for the system control driver.\n//\n// Copyright (c) 2005-2012 Texas Instruments Incorporated.  All rights reserved.\n// Software License Agreement\n//\n//   Redistribution and use in source and binary forms, with or without\n//   modification, are permitted provided that the following conditions\n//   are met:\n//\n//   Redistributions of source code must retain the above copyright\n//   notice, this list of conditions and the following disclaimer.\n//\n//   Redistributions in binary form must reproduce the above copyright\n//   notice, this list of conditions and the following disclaimer in the\n//   documentation and/or other materials provided with the\n//   distribution.\n//\n//   Neither the name of Texas Instruments Incorporated nor the names of\n//   its contributors may be used to endorse or promote products derived\n//   from this software without specific prior written permission.\n//\n// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n// \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n//\n// This is part of revision 9453 of the Stellaris Peripheral Driver Library.\n//\n//============================================================================*\n\n#ifndef __SYSCTL_H__\n#define __SYSCTL_H__\n\n//============================================================================*\n//\n// If building with a C++ compiler, make all of the definitions in this header\n// have a C binding.\n//\n//============================================================================*\n#ifdef __cplusplus\nextern \"C\"\n{\n#endif\n\ntypedef unsigned char tBoolean;\n\n//============================================================================*\n//\n// The following are values that can be passed to the\n// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(),\n// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the\n// ulPeripheral parameter.  The peripherals in the fourth group (upper nibble\n// is 3) can only be used with the SysCtlPeripheralPresent() API.\n//\n//============================================================================*\n#ifndef DEPRECATED\n#define SYSCTL_PERIPH_WDOG      0x00000008  // Watchdog\n#endif\n#define SYSCTL_PERIPH_WDOG0     0x00000008  // Watchdog 0\n#define SYSCTL_PERIPH_HIBERNATE 0x00000040  // Hibernation module\n#ifndef DEPRECATED\n#define SYSCTL_PERIPH_ADC       0x00100001  // ADC\n#endif\n#define SYSCTL_PERIPH_ADC0      0x00100001  // ADC0\n#define SYSCTL_PERIPH_ADC1      0x00100002  // ADC1\n#ifndef DEPRECATED\n#define SYSCTL_PERIPH_PWM       0x00100010  // PWM\n#endif\n#define SYSCTL_PERIPH_PWM0      0x00100010  // PWM\n#define SYSCTL_PERIPH_CAN0      0x00100100  // CAN 0\n#define SYSCTL_PERIPH_CAN1      0x00100200  // CAN 1\n#define SYSCTL_PERIPH_CAN2      0x00100400  // CAN 2\n#define SYSCTL_PERIPH_WDOG1     0x00101000  // Watchdog 1\n#define SYSCTL_PERIPH_UART0     0x10000001  // UART 0\n#define SYSCTL_PERIPH_UART1     0x10000002  // UART 1\n#define SYSCTL_PERIPH_UART2     0x10000004  // UART 2\n#ifndef DEPRECATED\n#define SYSCTL_PERIPH_SSI       0x10000010  // SSI\n#endif\n#define SYSCTL_PERIPH_SSI0      0x10000010  // SSI 0\n#define SYSCTL_PERIPH_SSI1      0x10000020  // SSI 1\n#ifndef DEPRECATED\n#define SYSCTL_PERIPH_QEI       0x10000100  // QEI\n#endif\n#define SYSCTL_PERIPH_QEI0      0x10000100  // QEI 0\n#define SYSCTL_PERIPH_QEI1      0x10000200  // QEI 1\n#ifndef DEPRECATED\n#define SYSCTL_PERIPH_I2C       0x10001000  // I2C\n#endif\n#define SYSCTL_PERIPH_I2C0      0x10001000  // I2C 0\n#define SYSCTL_PERIPH_I2C1      0x10004000  // I2C 1\n#define SYSCTL_PERIPH_TIMER0    0x10100001  // Timer 0\n#define SYSCTL_PERIPH_TIMER1    0x10100002  // Timer 1\n#define SYSCTL_PERIPH_TIMER2    0x10100004  // Timer 2\n#define SYSCTL_PERIPH_TIMER3    0x10100008  // Timer 3\n#define SYSCTL_PERIPH_COMP0     0x10100100  // Analog comparator 0\n#define SYSCTL_PERIPH_COMP1     0x10100200  // Analog comparator 1\n#define SYSCTL_PERIPH_COMP2     0x10100400  // Analog comparator 2\n#define SYSCTL_PERIPH_I2S0      0x10101000  // I2S0\n#define SYSCTL_PERIPH_EPI0      0x10104000  // EPI0\n#define SYSCTL_PERIPH_GPIOA     0x20000001  // GPIO A\n#define SYSCTL_PERIPH_GPIOB     0x20000002  // GPIO B\n#define SYSCTL_PERIPH_GPIOC     0x20000004  // GPIO C\n#define SYSCTL_PERIPH_GPIOD     0x20000008  // GPIO D\n#define SYSCTL_PERIPH_GPIOE     0x20000010  // GPIO E\n#define SYSCTL_PERIPH_GPIOF     0x20000020  // GPIO F\n#define SYSCTL_PERIPH_GPIOG     0x20000040  // GPIO G\n#define SYSCTL_PERIPH_GPIOH     0x20000080  // GPIO H\n#define SYSCTL_PERIPH_GPIOJ     0x20000100  // GPIO J\n#define SYSCTL_PERIPH_UDMA      0x20002000  // uDMA\n#define SYSCTL_PERIPH_USB0      0x20100001  // USB0\n#define SYSCTL_PERIPH_ETH       0x20105000  // Ethernet\n#define SYSCTL_PERIPH_IEEE1588  0x20100100  // IEEE1588\n#define SYSCTL_PERIPH_PLL       0x30000010  // PLL\n#define SYSCTL_PERIPH_TEMP      0x30000020  // Temperature sensor\n#define SYSCTL_PERIPH_MPU       0x30000080  // Cortex M3 MPU\n#define SYSCTL_PERIPH2_ADC0     0xf0003800  // ADC 0\n#define SYSCTL_PERIPH2_ADC1     0xf0003801  // ADC 1\n#define SYSCTL_PERIPH2_CAN0     0xf0003400  // CAN 0\n#define SYSCTL_PERIPH2_CAN1     0xf0003401  // CAN 1\n#define SYSCTL_PERIPH2_CAN2     0xf0003402  // CAN 2\n#define SYSCTL_PERIPH2_COMP0    0xf0003c00  // Analog comparator 0\n#define SYSCTL_PERIPH_EEPROM0   0xf0005800  // EEPROM 0\n#define SYSCTL_PERIPH2_EPI0     0xf0001000  // EPI0\n#define SYSCTL_PERIPH2_ETH      0xf0002c00  // ETH\n#define SYSCTL_PERIPH_FAN0      0xf0005400  // FAN 0\n#define SYSCTL_PERIPH2_GPIOA    0xf0000800  // GPIO A\n#define SYSCTL_PERIPH2_GPIOB    0xf0000801  // GPIO B\n#define SYSCTL_PERIPH2_GPIOC    0xf0000802  // GPIO C\n#define SYSCTL_PERIPH2_GPIOD    0xf0000803  // GPIO D\n#define SYSCTL_PERIPH2_GPIOE    0xf0000804  // GPIO E\n#define SYSCTL_PERIPH2_GPIOF    0xf0000805  // GPIO F\n#define SYSCTL_PERIPH2_GPIOG    0xf0000806  // GPIO G\n#define SYSCTL_PERIPH2_GPIOH    0xf0000807  // GPIO H\n#define SYSCTL_PERIPH2_GPIOJ    0xf0000808  // GPIO J\n#define SYSCTL_PERIPH_GPIOK     0xf0000809  // GPIO K\n#define SYSCTL_PERIPH_GPIOL     0xf000080a  // GPIO L\n#define SYSCTL_PERIPH_GPIOM     0xf000080b  // GPIO M\n#define SYSCTL_PERIPH_GPION     0xf000080c  // GPIO N\n#define SYSCTL_PERIPH_GPIOP     0xf000080d  // GPIO P\n#define SYSCTL_PERIPH_GPIOQ     0xf000080e  // GPIO Q\n#define SYSCTL_PERIPH_GPIOR     0xf000080f  // GPIO R\n#define SYSCTL_PERIPH_GPIOS     0xf0000810  // GPIO S\n#define SYSCTL_PERIPH2_HIB      0xf0001400  // Hibernation module\n#define SYSCTL_PERIPH2_I2C0     0xf0002000  // I2C 0\n#define SYSCTL_PERIPH2_I2C1     0xf0002001  // I2C 1\n#define SYSCTL_PERIPH_I2C2      0xf0002002  // I2C 2\n#define SYSCTL_PERIPH_I2C3      0xf0002003  // I2C 3\n#define SYSCTL_PERIPH_I2C4      0xf0002004  // I2C 4\n#define SYSCTL_PERIPH_I2C5      0xf0002005  // I2C 5\n#define SYSCTL_PERIPH2_I2S0     0xf0002400  // I2S0\n#define SYSCTL_PERIPH_LPC0      0xf0004800  // LPC 0\n#define SYSCTL_PERIPH_PECI0     0xf0005000  // PECI 0\n#define SYSCTL_PERIPH2_PWM0     0xf0004000  // PWM 0\n#define SYSCTL_PERIPH_PWM1      0xf0004001  // PWM 1\n#define SYSCTL_PERIPH2_QEI0     0xf0004400  // QEI 0\n#define SYSCTL_PERIPH2_QEI1     0xf0004401  // QEI 1\n#define SYSCTL_PERIPH2_SSI0     0xf0001c00  // SSI 0\n#define SYSCTL_PERIPH2_SSI1     0xf0001c01  // SSI 1\n#define SYSCTL_PERIPH_SSI2      0xf0001c02  // SSI 2\n#define SYSCTL_PERIPH_SSI3      0xf0001c03  // SSI 3\n#define SYSCTL_PERIPH2_TIMER0   0xf0000400  // Timer 0\n#define SYSCTL_PERIPH2_TIMER1   0xf0000401  // Timer 1\n#define SYSCTL_PERIPH2_TIMER2   0xf0000402  // Timer 2\n#define SYSCTL_PERIPH2_TIMER3   0xf0000403  // Timer 3\n#define SYSCTL_PERIPH_TIMER4    0xf0000404  // Timer 4\n#define SYSCTL_PERIPH_TIMER5    0xf0000405  // Timer 5\n#define SYSCTL_PERIPH_WTIMER0   0xf0005c00  // Wide Timer 0\n#define SYSCTL_PERIPH_WTIMER1   0xf0005c01  // Wide Timer 1\n#define SYSCTL_PERIPH_WTIMER2   0xf0005c02  // Wide Timer 2\n#define SYSCTL_PERIPH_WTIMER3   0xf0005c03  // Wide Timer 3\n#define SYSCTL_PERIPH_WTIMER4   0xf0005c04  // Wide Timer 4\n#define SYSCTL_PERIPH_WTIMER5   0xf0005c05  // Wide Timer 5\n#define SYSCTL_PERIPH2_UART0    0xf0001800  // UART 0\n#define SYSCTL_PERIPH2_UART1    0xf0001801  // UART 1\n#define SYSCTL_PERIPH2_UART2    0xf0001802  // UART 2\n#define SYSCTL_PERIPH_UART3     0xf0001803  // UART 3\n#define SYSCTL_PERIPH_UART4     0xf0001804  // UART 4\n#define SYSCTL_PERIPH_UART5     0xf0001805  // UART 5\n#define SYSCTL_PERIPH_UART6     0xf0001806  // UART 6\n#define SYSCTL_PERIPH_UART7     0xf0001807  // UART 7\n#define SYSCTL_PERIPH2_UDMA     0xf0000c00  // uDMA\n#define SYSCTL_PERIPH2_USB0     0xf0002800  // USB 0\n#define SYSCTL_PERIPH2_WDOG0    0xf0000000  // Watchdog 0\n#define SYSCTL_PERIPH2_WDOG1    0xf0000001  // Watchdog 1\n#define SYSCTL_PERIPH2_HIBERNATE \\\n                                0xf0001400  // Hibernate\n\n//============================================================================*\n//\n// The following are values that can be passed to the SysCtlPinPresent() API\n// as the ulPin parameter.\n//\n//============================================================================*\n#define SYSCTL_PIN_PWM0         0x00000001  // PWM0 pin\n#define SYSCTL_PIN_PWM1         0x00000002  // PWM1 pin\n#define SYSCTL_PIN_PWM2         0x00000004  // PWM2 pin\n#define SYSCTL_PIN_PWM3         0x00000008  // PWM3 pin\n#define SYSCTL_PIN_PWM4         0x00000010  // PWM4 pin\n#define SYSCTL_PIN_PWM5         0x00000020  // PWM5 pin\n#define SYSCTL_PIN_PWM6         0x00000040  // PWM6 pin\n#define SYSCTL_PIN_PWM7         0x00000080  // PWM7 pin\n#define SYSCTL_PIN_C0MINUS      0x00000040  // C0- pin\n#define SYSCTL_PIN_C0PLUS       0x00000080  // C0+ pin\n#define SYSCTL_PIN_C0O          0x00000100  // C0o pin\n#define SYSCTL_PIN_C1MINUS      0x00000200  // C1- pin\n#define SYSCTL_PIN_C1PLUS       0x00000400  // C1+ pin\n#define SYSCTL_PIN_C1O          0x00000800  // C1o pin\n#define SYSCTL_PIN_C2MINUS      0x00001000  // C2- pin\n#define SYSCTL_PIN_C2PLUS       0x00002000  // C2+ pin\n#define SYSCTL_PIN_C2O          0x00004000  // C2o pin\n#define SYSCTL_PIN_MC_FAULT0    0x00008000  // MC0 Fault pin\n#define SYSCTL_PIN_ADC0         0x00010000  // ADC0 pin\n#define SYSCTL_PIN_ADC1         0x00020000  // ADC1 pin\n#define SYSCTL_PIN_ADC2         0x00040000  // ADC2 pin\n#define SYSCTL_PIN_ADC3         0x00080000  // ADC3 pin\n#define SYSCTL_PIN_ADC4         0x00100000  // ADC4 pin\n#define SYSCTL_PIN_ADC5         0x00200000  // ADC5 pin\n#define SYSCTL_PIN_ADC6         0x00400000  // ADC6 pin\n#define SYSCTL_PIN_ADC7         0x00800000  // ADC7 pin\n#define SYSCTL_PIN_CCP0         0x01000000  // CCP0 pin\n#define SYSCTL_PIN_CCP1         0x02000000  // CCP1 pin\n#define SYSCTL_PIN_CCP2         0x04000000  // CCP2 pin\n#define SYSCTL_PIN_CCP3         0x08000000  // CCP3 pin\n#define SYSCTL_PIN_CCP4         0x10000000  // CCP4 pin\n#define SYSCTL_PIN_CCP5         0x20000000  // CCP5 pin\n#define SYSCTL_PIN_32KHZ        0x80000000  // 32kHz pin\n\n//============================================================================*\n//\n// The following are values that can be passed to the SysCtlLDOSet() API as\n// the ulVoltage value, or returned by the SysCtlLDOGet() API.\n//\n//============================================================================*\n#define SYSCTL_LDO_2_25V        0x00000005  // LDO output of 2.25V\n#define SYSCTL_LDO_2_30V        0x00000004  // LDO output of 2.30V\n#define SYSCTL_LDO_2_35V        0x00000003  // LDO output of 2.35V\n#define SYSCTL_LDO_2_40V        0x00000002  // LDO output of 2.40V\n#define SYSCTL_LDO_2_45V        0x00000001  // LDO output of 2.45V\n#define SYSCTL_LDO_2_50V        0x00000000  // LDO output of 2.50V\n#define SYSCTL_LDO_2_55V        0x0000001f  // LDO output of 2.55V\n#define SYSCTL_LDO_2_60V        0x0000001e  // LDO output of 2.60V\n#define SYSCTL_LDO_2_65V        0x0000001d  // LDO output of 2.65V\n#define SYSCTL_LDO_2_70V        0x0000001c  // LDO output of 2.70V\n#define SYSCTL_LDO_2_75V        0x0000001b  // LDO output of 2.75V\n\n//============================================================================*\n//\n// The following are values that can be passed to the SysCtlLDOConfigSet() API.\n//\n//============================================================================*\n#define SYSCTL_LDOCFG_ARST      0x00000001  // Allow LDO failure to reset\n#define SYSCTL_LDOCFG_NORST     0x00000000  // Do not reset on LDO failure\n\n//============================================================================*\n//\n// The following are values that can be passed to the SysCtlIntEnable(),\n// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask\n// by the SysCtlIntStatus() API.\n//\n//============================================================================*\n#define SYSCTL_INT_MOSC_PUP     0x00000100  // MOSC power-up interrupt\n#define SYSCTL_INT_USBPLL_LOCK  0x00000080  // USB PLL lock interrupt\n#define SYSCTL_INT_PLL_LOCK     0x00000040  // PLL lock interrupt\n#define SYSCTL_INT_CUR_LIMIT    0x00000020  // Current limit interrupt\n#define SYSCTL_INT_IOSC_FAIL    0x00000010  // Internal oscillator failure int\n#define SYSCTL_INT_MOSC_FAIL    0x00000008  // Main oscillator failure int\n#define SYSCTL_INT_POR          0x00000004  // Power on reset interrupt\n#define SYSCTL_INT_BOR          0x00000002  // Brown out interrupt\n#define SYSCTL_INT_PLL_FAIL     0x00000001  // PLL failure interrupt\n\n//============================================================================*\n//\n// The following are values that can be passed to the SysCtlResetCauseClear()\n// API or returned by the SysCtlResetCauseGet() API.\n//\n//============================================================================*\n#define SYSCTL_CAUSE_LDO        0x00000020  // LDO power not OK reset\n#define SYSCTL_CAUSE_WDOG1      0x00000020  // Watchdog 1 reset\n#define SYSCTL_CAUSE_SW         0x00000010  // Software reset\n#define SYSCTL_CAUSE_WDOG0      0x00000008  // Watchdog 0 reset\n#define SYSCTL_CAUSE_WDOG       0x00000008  // Watchdog reset\n#define SYSCTL_CAUSE_BOR        0x00000004  // Brown-out reset\n#define SYSCTL_CAUSE_POR        0x00000002  // Power on reset\n#define SYSCTL_CAUSE_EXT        0x00000001  // External reset\n\n//============================================================================*\n//\n// The following are values that can be passed to the SysCtlBrownOutConfigSet()\n// API as the ulConfig parameter.\n//\n//============================================================================*\n#define SYSCTL_BOR_RESET        0x00000002  // Reset instead of interrupting\n#define SYSCTL_BOR_RESAMPLE     0x00000001  // Resample BOR before asserting\n\n//============================================================================*\n//\n// The following are values that can be passed to the SysCtlPWMClockSet() API\n// as the ulConfig parameter, and can be returned by the SysCtlPWMClockGet()\n// API.\n//\n//============================================================================*\n#define SYSCTL_PWMDIV_1         0x00000000  // PWM clock is processor clock /1\n#define SYSCTL_PWMDIV_2         0x00100000  // PWM clock is processor clock /2\n#define SYSCTL_PWMDIV_4         0x00120000  // PWM clock is processor clock /4\n#define SYSCTL_PWMDIV_8         0x00140000  // PWM clock is processor clock /8\n#define SYSCTL_PWMDIV_16        0x00160000  // PWM clock is processor clock /16\n#define SYSCTL_PWMDIV_32        0x00180000  // PWM clock is processor clock /32\n#define SYSCTL_PWMDIV_64        0x001A0000  // PWM clock is processor clock /64\n\n//============================================================================*\n//\n// The following are values that can be passed to the SysCtlADCSpeedSet() API\n// as the ulSpeed parameter, and can be returned by the SyCtlADCSpeedGet()\n// API.\n//\n//============================================================================*\n#define SYSCTL_ADCSPEED_1MSPS   0x00000F00  // 1,000,000 samples per second\n#define SYSCTL_ADCSPEED_500KSPS 0x00000A00  // 500,000 samples per second\n#define SYSCTL_ADCSPEED_250KSPS 0x00000500  // 250,000 samples per second\n#define SYSCTL_ADCSPEED_125KSPS 0x00000000  // 125,000 samples per second\n\n//============================================================================*\n//\n// The following are values that can be passed to the SysCtlClockSet() API as\n// the ulConfig parameter.\n//\n//============================================================================*\n#define SYSCTL_SYSDIV_1         0x07800000  // Processor clock is osc/pll /1\n#define SYSCTL_SYSDIV_2         0x00C00000  // Processor clock is osc/pll /2\n#define SYSCTL_SYSDIV_3         0x01400000  // Processor clock is osc/pll /3\n#define SYSCTL_SYSDIV_4         0x01C00000  // Processor clock is osc/pll /4\n#define SYSCTL_SYSDIV_5         0x02400000  // Processor clock is osc/pll /5\n#define SYSCTL_SYSDIV_6         0x02C00000  // Processor clock is osc/pll /6\n#define SYSCTL_SYSDIV_7         0x03400000  // Processor clock is osc/pll /7\n#define SYSCTL_SYSDIV_8         0x03C00000  // Processor clock is osc/pll /8\n#define SYSCTL_SYSDIV_9         0x04400000  // Processor clock is osc/pll /9\n#define SYSCTL_SYSDIV_10        0x04C00000  // Processor clock is osc/pll /10\n#define SYSCTL_SYSDIV_11        0x05400000  // Processor clock is osc/pll /11\n#define SYSCTL_SYSDIV_12        0x05C00000  // Processor clock is osc/pll /12\n#define SYSCTL_SYSDIV_13        0x06400000  // Processor clock is osc/pll /13\n#define SYSCTL_SYSDIV_14        0x06C00000  // Processor clock is osc/pll /14\n#define SYSCTL_SYSDIV_15        0x07400000  // Processor clock is osc/pll /15\n#define SYSCTL_SYSDIV_16        0x07C00000  // Processor clock is osc/pll /16\n#define SYSCTL_SYSDIV_17        0x88400000  // Processor clock is osc/pll /17\n#define SYSCTL_SYSDIV_18        0x88C00000  // Processor clock is osc/pll /18\n#define SYSCTL_SYSDIV_19        0x89400000  // Processor clock is osc/pll /19\n#define SYSCTL_SYSDIV_20        0x89C00000  // Processor clock is osc/pll /20\n#define SYSCTL_SYSDIV_21        0x8A400000  // Processor clock is osc/pll /21\n#define SYSCTL_SYSDIV_22        0x8AC00000  // Processor clock is osc/pll /22\n#define SYSCTL_SYSDIV_23        0x8B400000  // Processor clock is osc/pll /23\n#define SYSCTL_SYSDIV_24        0x8BC00000  // Processor clock is osc/pll /24\n#define SYSCTL_SYSDIV_25        0x8C400000  // Processor clock is osc/pll /25\n#define SYSCTL_SYSDIV_26        0x8CC00000  // Processor clock is osc/pll /26\n#define SYSCTL_SYSDIV_27        0x8D400000  // Processor clock is osc/pll /27\n#define SYSCTL_SYSDIV_28        0x8DC00000  // Processor clock is osc/pll /28\n#define SYSCTL_SYSDIV_29        0x8E400000  // Processor clock is osc/pll /29\n#define SYSCTL_SYSDIV_30        0x8EC00000  // Processor clock is osc/pll /30\n#define SYSCTL_SYSDIV_31        0x8F400000  // Processor clock is osc/pll /31\n#define SYSCTL_SYSDIV_32        0x8FC00000  // Processor clock is osc/pll /32\n#define SYSCTL_SYSDIV_33        0x90400000  // Processor clock is osc/pll /33\n#define SYSCTL_SYSDIV_34        0x90C00000  // Processor clock is osc/pll /34\n#define SYSCTL_SYSDIV_35        0x91400000  // Processor clock is osc/pll /35\n#define SYSCTL_SYSDIV_36        0x91C00000  // Processor clock is osc/pll /36\n#define SYSCTL_SYSDIV_37        0x92400000  // Processor clock is osc/pll /37\n#define SYSCTL_SYSDIV_38        0x92C00000  // Processor clock is osc/pll /38\n#define SYSCTL_SYSDIV_39        0x93400000  // Processor clock is osc/pll /39\n#define SYSCTL_SYSDIV_40        0x93C00000  // Processor clock is osc/pll /40\n#define SYSCTL_SYSDIV_41        0x94400000  // Processor clock is osc/pll /41\n#define SYSCTL_SYSDIV_42        0x94C00000  // Processor clock is osc/pll /42\n#define SYSCTL_SYSDIV_43        0x95400000  // Processor clock is osc/pll /43\n#define SYSCTL_SYSDIV_44        0x95C00000  // Processor clock is osc/pll /44\n#define SYSCTL_SYSDIV_45        0x96400000  // Processor clock is osc/pll /45\n#define SYSCTL_SYSDIV_46        0x96C00000  // Processor clock is osc/pll /46\n#define SYSCTL_SYSDIV_47        0x97400000  // Processor clock is osc/pll /47\n#define SYSCTL_SYSDIV_48        0x97C00000  // Processor clock is osc/pll /48\n#define SYSCTL_SYSDIV_49        0x98400000  // Processor clock is osc/pll /49\n#define SYSCTL_SYSDIV_50        0x98C00000  // Processor clock is osc/pll /50\n#define SYSCTL_SYSDIV_51        0x99400000  // Processor clock is osc/pll /51\n#define SYSCTL_SYSDIV_52        0x99C00000  // Processor clock is osc/pll /52\n#define SYSCTL_SYSDIV_53        0x9A400000  // Processor clock is osc/pll /53\n#define SYSCTL_SYSDIV_54        0x9AC00000  // Processor clock is osc/pll /54\n#define SYSCTL_SYSDIV_55        0x9B400000  // Processor clock is osc/pll /55\n#define SYSCTL_SYSDIV_56        0x9BC00000  // Processor clock is osc/pll /56\n#define SYSCTL_SYSDIV_57        0x9C400000  // Processor clock is osc/pll /57\n#define SYSCTL_SYSDIV_58        0x9CC00000  // Processor clock is osc/pll /58\n#define SYSCTL_SYSDIV_59        0x9D400000  // Processor clock is osc/pll /59\n#define SYSCTL_SYSDIV_60        0x9DC00000  // Processor clock is osc/pll /60\n#define SYSCTL_SYSDIV_61        0x9E400000  // Processor clock is osc/pll /61\n#define SYSCTL_SYSDIV_62        0x9EC00000  // Processor clock is osc/pll /62\n#define SYSCTL_SYSDIV_63        0x9F400000  // Processor clock is osc/pll /63\n#define SYSCTL_SYSDIV_64        0x9FC00000  // Processor clock is osc/pll /64\n#define SYSCTL_SYSDIV_2_5       0xC1000000  // Processor clock is pll / 2.5\n#define SYSCTL_SYSDIV_3_5       0xC1800000  // Processor clock is pll / 3.5\n#define SYSCTL_SYSDIV_4_5       0xC2000000  // Processor clock is pll / 4.5\n#define SYSCTL_SYSDIV_5_5       0xC2800000  // Processor clock is pll / 5.5\n#define SYSCTL_SYSDIV_6_5       0xC3000000  // Processor clock is pll / 6.5\n#define SYSCTL_SYSDIV_7_5       0xC3800000  // Processor clock is pll / 7.5\n#define SYSCTL_SYSDIV_8_5       0xC4000000  // Processor clock is pll / 8.5\n#define SYSCTL_SYSDIV_9_5       0xC4800000  // Processor clock is pll / 9.5\n#define SYSCTL_SYSDIV_10_5      0xC5000000  // Processor clock is pll / 10.5\n#define SYSCTL_SYSDIV_11_5      0xC5800000  // Processor clock is pll / 11.5\n#define SYSCTL_SYSDIV_12_5      0xC6000000  // Processor clock is pll / 12.5\n#define SYSCTL_SYSDIV_13_5      0xC6800000  // Processor clock is pll / 13.5\n#define SYSCTL_SYSDIV_14_5      0xC7000000  // Processor clock is pll / 14.5\n#define SYSCTL_SYSDIV_15_5      0xC7800000  // Processor clock is pll / 15.5\n#define SYSCTL_SYSDIV_16_5      0xC8000000  // Processor clock is pll / 16.5\n#define SYSCTL_SYSDIV_17_5      0xC8800000  // Processor clock is pll / 17.5\n#define SYSCTL_SYSDIV_18_5      0xC9000000  // Processor clock is pll / 18.5\n#define SYSCTL_SYSDIV_19_5      0xC9800000  // Processor clock is pll / 19.5\n#define SYSCTL_SYSDIV_20_5      0xCA000000  // Processor clock is pll / 20.5\n#define SYSCTL_SYSDIV_21_5      0xCA800000  // Processor clock is pll / 21.5\n#define SYSCTL_SYSDIV_22_5      0xCB000000  // Processor clock is pll / 22.5\n#define SYSCTL_SYSDIV_23_5      0xCB800000  // Processor clock is pll / 23.5\n#define SYSCTL_SYSDIV_24_5      0xCC000000  // Processor clock is pll / 24.5\n#define SYSCTL_SYSDIV_25_5      0xCC800000  // Processor clock is pll / 25.5\n#define SYSCTL_SYSDIV_26_5      0xCD000000  // Processor clock is pll / 26.5\n#define SYSCTL_SYSDIV_27_5      0xCD800000  // Processor clock is pll / 27.5\n#define SYSCTL_SYSDIV_28_5      0xCE000000  // Processor clock is pll / 28.5\n#define SYSCTL_SYSDIV_29_5      0xCE800000  // Processor clock is pll / 29.5\n#define SYSCTL_SYSDIV_30_5      0xCF000000  // Processor clock is pll / 30.5\n#define SYSCTL_SYSDIV_31_5      0xCF800000  // Processor clock is pll / 31.5\n#define SYSCTL_SYSDIV_32_5      0xD0000000  // Processor clock is pll / 32.5\n#define SYSCTL_SYSDIV_33_5      0xD0800000  // Processor clock is pll / 33.5\n#define SYSCTL_SYSDIV_34_5      0xD1000000  // Processor clock is pll / 34.5\n#define SYSCTL_SYSDIV_35_5      0xD1800000  // Processor clock is pll / 35.5\n#define SYSCTL_SYSDIV_36_5      0xD2000000  // Processor clock is pll / 36.5\n#define SYSCTL_SYSDIV_37_5      0xD2800000  // Processor clock is pll / 37.5\n#define SYSCTL_SYSDIV_38_5      0xD3000000  // Processor clock is pll / 38.5\n#define SYSCTL_SYSDIV_39_5      0xD3800000  // Processor clock is pll / 39.5\n#define SYSCTL_SYSDIV_40_5      0xD4000000  // Processor clock is pll / 40.5\n#define SYSCTL_SYSDIV_41_5      0xD4800000  // Processor clock is pll / 41.5\n#define SYSCTL_SYSDIV_42_5      0xD5000000  // Processor clock is pll / 42.5\n#define SYSCTL_SYSDIV_43_5      0xD5800000  // Processor clock is pll / 43.5\n#define SYSCTL_SYSDIV_44_5      0xD6000000  // Processor clock is pll / 44.5\n#define SYSCTL_SYSDIV_45_5      0xD6800000  // Processor clock is pll / 45.5\n#define SYSCTL_SYSDIV_46_5      0xD7000000  // Processor clock is pll / 46.5\n#define SYSCTL_SYSDIV_47_5      0xD7800000  // Processor clock is pll / 47.5\n#define SYSCTL_SYSDIV_48_5      0xD8000000  // Processor clock is pll / 48.5\n#define SYSCTL_SYSDIV_49_5      0xD8800000  // Processor clock is pll / 49.5\n#define SYSCTL_SYSDIV_50_5      0xD9000000  // Processor clock is pll / 50.5\n#define SYSCTL_SYSDIV_51_5      0xD9800000  // Processor clock is pll / 51.5\n#define SYSCTL_SYSDIV_52_5      0xDA000000  // Processor clock is pll / 52.5\n#define SYSCTL_SYSDIV_53_5      0xDA800000  // Processor clock is pll / 53.5\n#define SYSCTL_SYSDIV_54_5      0xDB000000  // Processor clock is pll / 54.5\n#define SYSCTL_SYSDIV_55_5      0xDB800000  // Processor clock is pll / 55.5\n#define SYSCTL_SYSDIV_56_5      0xDC000000  // Processor clock is pll / 56.5\n#define SYSCTL_SYSDIV_57_5      0xDC800000  // Processor clock is pll / 57.5\n#define SYSCTL_SYSDIV_58_5      0xDD000000  // Processor clock is pll / 58.5\n#define SYSCTL_SYSDIV_59_5      0xDD800000  // Processor clock is pll / 59.5\n#define SYSCTL_SYSDIV_60_5      0xDE000000  // Processor clock is pll / 60.5\n#define SYSCTL_SYSDIV_61_5      0xDE800000  // Processor clock is pll / 61.5\n#define SYSCTL_SYSDIV_62_5      0xDF000000  // Processor clock is pll / 62.5\n#define SYSCTL_SYSDIV_63_5      0xDF800000  // Processor clock is pll / 63.5\n#define SYSCTL_USE_PLL          0x00000000  // System clock is the PLL clock\n#define SYSCTL_USE_OSC          0x00003800  // System clock is the osc clock\n#define SYSCTL_XTAL_1MHZ        0x00000000  // External crystal is 1MHz\n#define SYSCTL_XTAL_1_84MHZ     0x00000040  // External crystal is 1.8432MHz\n#define SYSCTL_XTAL_2MHZ        0x00000080  // External crystal is 2MHz\n#define SYSCTL_XTAL_2_45MHZ     0x000000C0  // External crystal is 2.4576MHz\n#define SYSCTL_XTAL_3_57MHZ     0x00000100  // External crystal is 3.579545MHz\n#define SYSCTL_XTAL_3_68MHZ     0x00000140  // External crystal is 3.6864MHz\n#define SYSCTL_XTAL_4MHZ        0x00000180  // External crystal is 4MHz\n#define SYSCTL_XTAL_4_09MHZ     0x000001C0  // External crystal is 4.096MHz\n#define SYSCTL_XTAL_4_91MHZ     0x00000200  // External crystal is 4.9152MHz\n#define SYSCTL_XTAL_5MHZ        0x00000240  // External crystal is 5MHz\n#define SYSCTL_XTAL_5_12MHZ     0x00000280  // External crystal is 5.12MHz\n#define SYSCTL_XTAL_6MHZ        0x000002C0  // External crystal is 6MHz\n#define SYSCTL_XTAL_6_14MHZ     0x00000300  // External crystal is 6.144MHz\n#define SYSCTL_XTAL_7_37MHZ     0x00000340  // External crystal is 7.3728MHz\n#define SYSCTL_XTAL_8MHZ        0x00000380  // External crystal is 8MHz\n#define SYSCTL_XTAL_8_19MHZ     0x000003C0  // External crystal is 8.192MHz\n#define SYSCTL_XTAL_10MHZ       0x00000400  // External crystal is 10 MHz\n#define SYSCTL_XTAL_12MHZ       0x00000440  // External crystal is 12 MHz\n#define SYSCTL_XTAL_12_2MHZ     0x00000480  // External crystal is 12.288 MHz\n#define SYSCTL_XTAL_13_5MHZ     0x000004C0  // External crystal is 13.56 MHz\n#define SYSCTL_XTAL_14_3MHZ     0x00000500  // External crystal is 14.31818 MHz\n#define SYSCTL_XTAL_16MHZ       0x00000540  // External crystal is 16 MHz\n#define SYSCTL_XTAL_16_3MHZ     0x00000580  // External crystal is 16.384 MHz\n#define SYSCTL_XTAL_18MHZ       0x000005C0  // External crystal is 18.0 MHz\n#define SYSCTL_XTAL_20MHZ       0x00000600  // External crystal is 20.0 MHz\n#define SYSCTL_XTAL_24MHZ       0x00000640  // External crystal is 24.0 MHz\n#define SYSCTL_XTAL_25MHZ       0x00000680  // External crystal is 25.0 MHz\n#define SYSCTL_OSC_MAIN         0x00000000  // Osc source is main osc\n#define SYSCTL_OSC_INT          0x00000010  // Osc source is int. osc\n#define SYSCTL_OSC_INT4         0x00000020  // Osc source is int. osc /4\n#define SYSCTL_OSC_INT30        0x00000030  // Osc source is int. 30 KHz\n#define SYSCTL_OSC_EXT4_19      0x80000028  // Osc source is ext. 4.19 MHz\n#define SYSCTL_OSC_EXT32        0x80000038  // Osc source is ext. 32 KHz\n#define SYSCTL_INT_OSC_DIS      0x00000002  // Disable internal oscillator\n#define SYSCTL_MAIN_OSC_DIS     0x00000001  // Disable main oscillator\n\n//============================================================================*\n//\n// The following are values that can be passed to the SysCtlDeepSleepClockSet()\n// API as the ulConfig parameter.\n//\n//============================================================================*\n#define SYSCTL_DSLP_DIV_1       0x00000000  // Deep-sleep clock is osc /1\n#define SYSCTL_DSLP_DIV_2       0x00800000  // Deep-sleep clock is osc /2\n#define SYSCTL_DSLP_DIV_3       0x01000000  // Deep-sleep clock is osc /3\n#define SYSCTL_DSLP_DIV_4       0x01800000  // Deep-sleep clock is osc /4\n#define SYSCTL_DSLP_DIV_5       0x02000000  // Deep-sleep clock is osc /5\n#define SYSCTL_DSLP_DIV_6       0x02800000  // Deep-sleep clock is osc /6\n#define SYSCTL_DSLP_DIV_7       0x03000000  // Deep-sleep clock is osc /7\n#define SYSCTL_DSLP_DIV_8       0x03800000  // Deep-sleep clock is osc /8\n#define SYSCTL_DSLP_DIV_9       0x04000000  // Deep-sleep clock is osc /9\n#define SYSCTL_DSLP_DIV_10      0x04800000  // Deep-sleep clock is osc /10\n#define SYSCTL_DSLP_DIV_11      0x05000000  // Deep-sleep clock is osc /11\n#define SYSCTL_DSLP_DIV_12      0x05800000  // Deep-sleep clock is osc /12\n#define SYSCTL_DSLP_DIV_13      0x06000000  // Deep-sleep clock is osc /13\n#define SYSCTL_DSLP_DIV_14      0x06800000  // Deep-sleep clock is osc /14\n#define SYSCTL_DSLP_DIV_15      0x07000000  // Deep-sleep clock is osc /15\n#define SYSCTL_DSLP_DIV_16      0x07800000  // Deep-sleep clock is osc /16\n#define SYSCTL_DSLP_DIV_17      0x08000000  // Deep-sleep clock is osc /17\n#define SYSCTL_DSLP_DIV_18      0x08800000  // Deep-sleep clock is osc /18\n#define SYSCTL_DSLP_DIV_19      0x09000000  // Deep-sleep clock is osc /19\n#define SYSCTL_DSLP_DIV_20      0x09800000  // Deep-sleep clock is osc /20\n#define SYSCTL_DSLP_DIV_21      0x0A000000  // Deep-sleep clock is osc /21\n#define SYSCTL_DSLP_DIV_22      0x0A800000  // Deep-sleep clock is osc /22\n#define SYSCTL_DSLP_DIV_23      0x0B000000  // Deep-sleep clock is osc /23\n#define SYSCTL_DSLP_DIV_24      0x0B800000  // Deep-sleep clock is osc /24\n#define SYSCTL_DSLP_DIV_25      0x0C000000  // Deep-sleep clock is osc /25\n#define SYSCTL_DSLP_DIV_26      0x0C800000  // Deep-sleep clock is osc /26\n#define SYSCTL_DSLP_DIV_27      0x0D000000  // Deep-sleep clock is osc /27\n#define SYSCTL_DSLP_DIV_28      0x0D800000  // Deep-sleep clock is osc /28\n#define SYSCTL_DSLP_DIV_29      0x0E000000  // Deep-sleep clock is osc /29\n#define SYSCTL_DSLP_DIV_30      0x0E800000  // Deep-sleep clock is osc /30\n#define SYSCTL_DSLP_DIV_31      0x0F000000  // Deep-sleep clock is osc /31\n#define SYSCTL_DSLP_DIV_32      0x0F800000  // Deep-sleep clock is osc /32\n#define SYSCTL_DSLP_DIV_33      0x10000000  // Deep-sleep clock is osc /33\n#define SYSCTL_DSLP_DIV_34      0x10800000  // Deep-sleep clock is osc /34\n#define SYSCTL_DSLP_DIV_35      0x11000000  // Deep-sleep clock is osc /35\n#define SYSCTL_DSLP_DIV_36      0x11800000  // Deep-sleep clock is osc /36\n#define SYSCTL_DSLP_DIV_37      0x12000000  // Deep-sleep clock is osc /37\n#define SYSCTL_DSLP_DIV_38      0x12800000  // Deep-sleep clock is osc /38\n#define SYSCTL_DSLP_DIV_39      0x13000000  // Deep-sleep clock is osc /39\n#define SYSCTL_DSLP_DIV_40      0x13800000  // Deep-sleep clock is osc /40\n#define SYSCTL_DSLP_DIV_41      0x14000000  // Deep-sleep clock is osc /41\n#define SYSCTL_DSLP_DIV_42      0x14800000  // Deep-sleep clock is osc /42\n#define SYSCTL_DSLP_DIV_43      0x15000000  // Deep-sleep clock is osc /43\n#define SYSCTL_DSLP_DIV_44      0x15800000  // Deep-sleep clock is osc /44\n#define SYSCTL_DSLP_DIV_45      0x16000000  // Deep-sleep clock is osc /45\n#define SYSCTL_DSLP_DIV_46      0x16800000  // Deep-sleep clock is osc /46\n#define SYSCTL_DSLP_DIV_47      0x17000000  // Deep-sleep clock is osc /47\n#define SYSCTL_DSLP_DIV_48      0x17800000  // Deep-sleep clock is osc /48\n#define SYSCTL_DSLP_DIV_49      0x18000000  // Deep-sleep clock is osc /49\n#define SYSCTL_DSLP_DIV_50      0x18800000  // Deep-sleep clock is osc /50\n#define SYSCTL_DSLP_DIV_51      0x19000000  // Deep-sleep clock is osc /51\n#define SYSCTL_DSLP_DIV_52      0x19800000  // Deep-sleep clock is osc /52\n#define SYSCTL_DSLP_DIV_53      0x1A000000  // Deep-sleep clock is osc /53\n#define SYSCTL_DSLP_DIV_54      0x1A800000  // Deep-sleep clock is osc /54\n#define SYSCTL_DSLP_DIV_55      0x1B000000  // Deep-sleep clock is osc /55\n#define SYSCTL_DSLP_DIV_56      0x1B800000  // Deep-sleep clock is osc /56\n#define SYSCTL_DSLP_DIV_57      0x1C000000  // Deep-sleep clock is osc /57\n#define SYSCTL_DSLP_DIV_58      0x1C800000  // Deep-sleep clock is osc /58\n#define SYSCTL_DSLP_DIV_59      0x1D000000  // Deep-sleep clock is osc /59\n#define SYSCTL_DSLP_DIV_60      0x1D800000  // Deep-sleep clock is osc /60\n#define SYSCTL_DSLP_DIV_61      0x1E000000  // Deep-sleep clock is osc /61\n#define SYSCTL_DSLP_DIV_62      0x1E800000  // Deep-sleep clock is osc /62\n#define SYSCTL_DSLP_DIV_63      0x1F000000  // Deep-sleep clock is osc /63\n#define SYSCTL_DSLP_DIV_64      0x1F800000  // Deep-sleep clock is osc /64\n#define SYSCTL_DSLP_OSC_MAIN    0x00000000  // Osc source is main osc\n#define SYSCTL_DSLP_OSC_INT     0x00000010  // Osc source is int. osc\n#define SYSCTL_DSLP_OSC_INT30   0x00000030  // Osc source is int. 30 KHz\n#define SYSCTL_DSLP_OSC_EXT32   0x00000070  // Osc source is ext. 32 KHz\n#define SYSCTL_DSLP_PIOSC_PD    0x00000002  // Power down PIOSC in deep-sleep\n\n//============================================================================*\n//\n// Prototypes for the APIs.\n//\n//============================================================================*\nextern unsigned long SysCtlSRAMSizeGet(void);\nextern unsigned long SysCtlFlashSizeGet(void);\nextern tBoolean SysCtlPinPresent(unsigned long ulPin);\nextern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral);\nextern tBoolean SysCtlPeripheralReady(unsigned long ulPeripheral);\nextern void SysCtlPeripheralPowerOn(unsigned long ulPeripheral);\nextern void SysCtlPeripheralPowerOff(unsigned long ulPeripheral);\nextern void SysCtlPeripheralReset(unsigned long ulPeripheral);\nextern void SysCtlPeripheralEnable(unsigned long ulPeripheral);\nextern void SysCtlPeripheralDisable(unsigned long ulPeripheral);\nextern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral);\nextern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral);\nextern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral);\nextern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral);\nextern void SysCtlPeripheralClockGating(tBoolean bEnable);\nextern void SysCtlIntRegister(void (*pfnHandler)(void));\nextern void SysCtlIntUnregister(void);\nextern void SysCtlIntEnable(unsigned long ulInts);\nextern void SysCtlIntDisable(unsigned long ulInts);\nextern void SysCtlIntClear(unsigned long ulInts);\nextern unsigned long SysCtlIntStatus(tBoolean bMasked);\nextern void SysCtlLDOSet(unsigned long ulVoltage);\nextern unsigned long SysCtlLDOGet(void);\nextern void SysCtlLDOConfigSet(unsigned long ulConfig);\nextern void SysCtlReset(void);\nextern void SysCtlSleep(void);\nextern void SysCtlDeepSleep(void);\nextern unsigned long SysCtlResetCauseGet(void);\nextern void SysCtlResetCauseClear(unsigned long ulCauses);\nextern void SysCtlBrownOutConfigSet(unsigned long ulConfig,\n                                    unsigned long ulDelay);\nextern void SysCtlDelay(unsigned long ulCount);\nextern void SysCtlMOSCConfigSet(unsigned long ulConfig);\nextern unsigned long SysCtlPIOSCCalibrate(unsigned long ulType);\nextern void SysCtlClockSet(unsigned long ulConfig);\nextern unsigned long SysCtlClockGet(void);\nextern void SysCtlDeepSleepClockSet(unsigned long ulConfig);\nextern void SysCtlPWMClockSet(unsigned long ulConfig);\nextern unsigned long SysCtlPWMClockGet(void);\nextern void SysCtlADCSpeedSet(unsigned long ulSpeed);\nextern unsigned long SysCtlADCSpeedGet(void);\nextern void SysCtlIOSCVerificationSet(tBoolean bEnable);\nextern void SysCtlMOSCVerificationSet(tBoolean bEnable);\nextern void SysCtlPLLVerificationSet(tBoolean bEnable);\nextern void SysCtlClkVerificationClear(void);\nextern void SysCtlGPIOAHBEnable(unsigned long ulGPIOPeripheral);\nextern void SysCtlGPIOAHBDisable(unsigned long ulGPIOPeripheral);\nextern void SysCtlUSBPLLEnable(void);\nextern void SysCtlUSBPLLDisable(void);\nextern unsigned long SysCtlI2SMClkSet(unsigned long ulInputClock,\n                                      unsigned long ulMClk);\n\n//============================================================================*\n//\n// Mark the end of the C bindings section for C++ compilers.\n//\n//============================================================================*\n#ifdef __cplusplus\n}\n#endif\n\n#endif // __SYSCTL_H__\n"
  },
  {
    "path": "3rd_party/ek-tm4c123gxl/system_TM4C123GH6PM.c",
    "content": "/**************************************************************************//**\n * @file     system_TM4C123GH6PM.c\n * @brief    CMSIS Device System Source File for\n *           Texas Instruments TIVA TM4C123 Device Series\n * @version  V1.00\n * @date     27. March 2013\n *\n * @note\n *                                                             modified by Keil\n ******************************************************************************/\n\n#include <stdint.h>\n#include \"TM4C123GH6PM.h\"\n\n\n/*----------------------------------------------------------------------------\n  DEFINES\n *----------------------------------------------------------------------------*/\n//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------\n//\n// This file can be used by the Keil uVision configuration wizard to set\n// the following system clock configuration values.  Or the value of the\n// macros can be directly edited below if not using the uVision configuration\n// wizard.\n//\n//--------------------- Clock Configuration ----------------------------------\n//\n//  <e> Clock Configuration\n//          <i> Uncheck this box to skip the clock configuration.\n//\n// The following controls whether the system clock is configured in the\n// SystemInit() function.  If it is defined to be 1 then the system clock\n// will be configured according to the macros in the rest of this file.\n// If it is defined to be 0, then the system clock configuration is bypassed.\n//\n#define CLOCK_SETUP 1\n\n//********************************* RCC ***************************************\n//\n//  <h> Run-Mode Clock Configuration (RCC)\n\n//      <o> SYSDIV: System Clock Divisor <2-16>\n//          <i> Specifies the divisor used to generate the system clock from\n//          <i> either the PLL output of 200 MHz, or the chosen oscillator.\n//\n// The following value is the system clock divisor.  This will be applied if\n// USESYSDIV (see below) is enabled.  The valid range of dividers is 2-16.\n//\n#define CFG_RCC_SYSDIV 4\n\n//      <q> USESYSDIV: Enable System Clock Divider\n//          <i> Check this box to use the System Clock Divider\n//\n// The following controls whether the system clock divider is used.  If the\n// value is 1, then the system clock divider is used, and the value of the\n// system divider is defined by SYSDIV (see above).  If the value is 0, then\n// the system clock divider is not used.\n//\n#define CFG_RCC_USESYSDIV 1\n\n//      <q> USEPWMDIV: Enable PWM Clock Divider\n//          <i> Check this box to use the PWM Clock Divider\n//\n// The following controls whether the PWM clock divider is used.  If the\n// value is 1, then the PWM clock divider is used, and the value of the\n// PWM divider is defined by PWMDIV (see below).  If the value is 0, then\n// the PWM clock divider is not used.\n//\n#define CFG_RCC_USEPWMDIV 1\n\n//      <o> PWMDIV: PWM Unit Clock Divisor\n//              <0=> 0: SysClk / 2\n//              <1=> 1: SysClk / 4\n//              <2=> 2: SysClk / 8\n//              <3=> 3: SysClk / 16\n//              <4=> 4: SysClk / 32\n//              <5=> 5: SysClk / 64\n//              <6=> 6: SysClk / 64\n//              <7=> 7: SysClk / 64 (default)\n//          <i> Specifies the divisor used to generate the PWM time base,\n//          <i> from the System Clock\n//\n// The following value determines the PWM clock divider.  It is used if\n// USEPWMDIV is enabled (see above).  Otherwise the PWM clock is the same as\n// the system clock.  The value of the divider is determined by the table\n// above.\n//\n#define CFG_RCC_PWMDIV 7\n\n//      <q> PWRDN: PLL Power Down\n//          <i> Check this box to disable the PLL.  You must also choose\n//          <i> PLL Bypass.\n//\n// If the following value is 1, then the PLL is powered down.  Keep this value\n// as 1 if you do not need to use the PLL.  In this case, BYPASS (see below)\n// must also be set to 1.  If you are using the PLL, then this value must be\n// set to 0.\n//\n#define CFG_RCC_PWRDN 0\n\n//      <q> BYPASS: PLL Bypass\n//          <i> Check this box to not use the PLL for the System Clock\n//\n// Set the following value to 1 to bypass the PLL and not use it for the\n// system clock.  You must set this to 1 if PWRDN (above) is set to 1.  Set\n// this to 0 if you are using the PLL.\n//\n#define CFG_RCC_BYPASS 0\n\n//      <o> XTAL: Crystal Value\n//              < 0=>  0: 1.0000 MHz  (can not be used with PLL)\n//              < 1=>  1: 1.8432 MHz  (can not be used with PLL)\n//              < 2=>  2: 2.0000 MHz  (can not be used with PLL)\n//              < 3=>  3: 2.4576 MHz  (can not be used with PLL)\n//              < 4=>  4: 3.579545 MHz\n//              < 5=>  5: 3.6864 MHz\n//              < 6=>  6: 4.0000 MHz\n//              < 7=>  7: 4.096 MHz\n//              < 8=>  8: 4.9152 MHz\n//              < 9=>  9: 5.0000 MHz\n//              <10=> 10: 5.12 MHz\n//              <11=> 11: 6.0000 MHz (default)\n//              <12=> 12: 6.144 MHz\n//              <13=> 13: 7.3728 MHz\n//              <14=> 14: 8.0000 MHz\n//              <15=> 15: 8.192 MHz\n//              <16=> 16: 10.0 MHz\n//              <17=> 17: 12.0 MHz\n//              <18=> 18: 12.288 MHz\n//              <19=> 19: 13.56 MHz\n//              <20=> 20: 14.31818 MHz\n//              <21=> 21: 16.0 MHz\n//              <22=> 22: 16.384 MHz\n//          <i> This is the crystal frequency used for the main oscillator\n//\n// This value defines the crystal frequency for the main oscillator, according\n// to the table in the comments above.  If an external crystal is used, then\n// this value must be set to match the value of the crystal.\n//\n#define CFG_RCC_XTAL 21\n\n//      <o> OSCSRC: Oscillator Source\n//              <0=> 0: MOSC Main oscillator\n//              <1=> 1: IOSC Internal oscillator (default)\n//              <2=> 2: IOSC/4 Internal oscillator / 4 (this is necessary if used as input to PLL)\n//              <3=> 3: 30kHz 30-KHz internal oscillator\n//          <i> Chooses the oscillator that is used for the system clock,\n//          <i> or the PLL input.\n//\n// The following value chooses the oscillator source according to the table in\n// the comments above.\n//\n#define CFG_RCC_OSCSRC 0\n\n//      <q> IOSCDIS: Internal Oscillator Disable\n//          <i> Check this box to turn off the internal oscillator\n//\n// Set the following value to 1 to turn off the internal oscillator.  This\n// value can be set to 1 if you are not using the internal oscillator.\n//\n#define CFG_RCC_IOSCDIS 1\n\n//      <q> MOSCDIS: Main Oscillator Disable\n//          <i> Check this box to turn off the main oscillator\n//\n// Set the following value to 1 to turn off the main oscillator.  This\n// value can be set to 1 if you are not using the main oscillator.\n//\n#define CFG_RCC_MOSCDIS 0\n\n//  </h>\n\n//********************************* RCC2 **************************************\n//\n//   <h> Run-Mode Clock Configuration 2 (RCC2)\n\n//      <q> USERCC2: Use RCC2\n//          <i> Check this box to override some fields in RCC.  RCC2 provides\n//          <i> more bits for the system clock divider, and provides an\n//          <i> additional oscillator source.  If you do not need these\n//          <i> additional features, then leave this box unchecked.\n//\n// Set the following value to 1 to use the RCC2 register.  The RCC2 register\n// overrides some of the fields in the RCC register if it is used.\n//\n#define CFG_RCC2_USERCC2 0\n\n//      <o> SYSDIV2: System Clock Divisor <2-64>\n//          <i> Specifies the divisor used to generate the system clock from\n//          <i> either the PLL output of 200 MHz, or the oscillator.\n//\n// The following value is the system clock divisor.  This will be applied if\n// USESYSDIV in RCC is enabled.  The valid range of dividers is 2-64.\n//\n#define CFG_RCC_SYSDIV2 4\n\n//      <q> PWRDN2: Power Down PLL\n//          <i> Check this box to disable the PLL.  You must also choose\n//          <i> PLL Bypass.\n//\n// If the following value is 1, then the PLL is powered down.  Keep this value\n// as 1 if you do not need to use the PLL.  In this case, BYPASS2 (see below)\n// must also be set to 1.  If you are using the PLL, then this value must be\n// set to 0.\n//\n#define CFG_RCC_PWRDN2 0\n\n//      <q> BYPASS2: Bypass PLL\n//          <i> Check this box to not use the PLL for the System Clock\n//\n// Set the following value to 1 to bypass the PLL and not use it for the\n// system clock.  You must set this to 1 if PWRDN2 (above) is set to 1.  Set\n// this to 0 if you are using the PLL.\n//\n#define CFG_RCC_BYPASS2 0\n\n//      <o> OSCSRC2: Oscillator Source\n//              <0=> 0: MOSC Main oscillator\n//              <1=> 1: IOSC Internal oscillator (default)\n//              <2=> 2: IOSC/4 Internal oscillator / 4 (this is necessary if used as input to PLL)\n//              <3=> 3: 30kHz 30-kHz internal oscillator\n//              <7=> 7: 32kHz 32.768-kHz external oscillator\n//          <i> The oscillator that is used for the system clock, or the PLL input.\n//\n// The following value chooses the oscillator source according to the table in\n// the comments above.\n//\n#define CFG_RCC_OSCSRC2 0\n\n//  </h>\n//\n//  </e>\n\n//-------- <<< end of configuration section >>> ------------------------------\n\n//\n// The following macros are used to program the RCC and RCC2 registers in\n// the SystemInit() function.  Edit the macros above to change these values.\n//\n#define RCC_Val                                                               \\\n(                                                                             \\\n    ((CFG_RCC_SYSDIV - 1)   << 23) |                                          \\\n    (CFG_RCC_USESYSDIV      << 22) |                                          \\\n    (CFG_RCC_USEPWMDIV      << 20) |                                          \\\n    (CFG_RCC_PWMDIV         << 17) |                                          \\\n    (CFG_RCC_PWRDN          << 13) |                                          \\\n    (CFG_RCC_BYPASS         << 11) |                                          \\\n    (CFG_RCC_XTAL           << 6)  |                                          \\\n    (CFG_RCC_OSCSRC         << 4)  |                                          \\\n    (CFG_RCC_IOSCDIS        << 1)  |                                          \\\n    (CFG_RCC_MOSCDIS        << 1)\\\n)\n\n#define RCC2_Val                                                              \\\n(                                                                             \\\n    (CFG_RCC2_USERCC2      << 31) |                                           \\\n    ((CFG_RCC_SYSDIV2 - 1)  << 23) |                                          \\\n    (CFG_RCC_PWRDN2         << 13) |                                          \\\n    (CFG_RCC_BYPASS2        << 11) |                                          \\\n    (CFG_RCC_OSCSRC2        << 4)\\\n)\n\n\n/*----------------------------------------------------------------------------\n  Define clocks\n *----------------------------------------------------------------------------*/\n#define XTALM       (16000000UL)            /* Main         oscillator freq */\n#define XTALI       (12000000UL)            /* Internal     oscillator freq */\n#define XTAL30K     (   30000UL)            /* Internal 30K oscillator freq */\n#define XTAL32K     (   32768UL)            /* external 32K oscillator freq */\n\n#define PLL_CLK    (400000000UL)\n#define ADC_CLK     (PLL_CLK/25)\n#define CAN_CLK     (PLL_CLK/50)\n\n /* Determine clock frequency according to clock register values */\n  #if (RCC2_Val & (1UL<<31))                              /* is rcc2 used ? */\n    #if (RCC2_Val & (1UL<<11))                           /* check BYPASS */\n              #if   (((RCC2_Val>>4) & 0x07) == 0x0)\n                #if   (((RCC_Val>>6) & 0x1F) == 0x0)\n                      #define __CORE_CLK_PRE  1000000UL\n                #elif (((RCC_Val>>6) & 0x1F) == 0x1)\n                      #define __CORE_CLK_PRE  1843200UL\n                #elif (((RCC_Val>>6) & 0x1F) == 0x2)\n                      #define __CORE_CLK_PRE  2000000UL\n                #elif (((RCC_Val>>6) & 0x1F) == 0x3)\n                      #define __CORE_CLK_PRE  2457600UL\n                #elif (((RCC_Val>>6) & 0x1F) == 0x4)\n                      #define __CORE_CLK_PRE  3579545UL\n                #elif (((RCC_Val>>6) & 0x1F) == 0x5)\n                      #define __CORE_CLK_PRE  3686400UL\n                #elif (((RCC_Val>>6) & 0x1F) == 0x6)\n                      #define __CORE_CLK_PRE  4000000UL\n                #elif (((RCC_Val>>6) & 0x1F) == 0x7)\n                      #define __CORE_CLK_PRE  4096000UL\n                #elif (((RCC_Val>>6) & 0x1F) == 0x8)\n                      #define __CORE_CLK_PRE  4915200UL\n                #elif (((RCC_Val>>6) & 0x1F) == 0x9)\n                      #define __CORE_CLK_PRE  5000000UL\n                #elif (((RCC_Val>>6) & 0x1F) == 0xA)\n                      #define __CORE_CLK_PRE  5120000UL\n                #elif (((RCC_Val>>6) & 0x1F) == 0xB)\n                      #define __CORE_CLK_PRE  6000000UL\n                #elif (((RCC_Val>>6) & 0x1F) == 0xC)\n                      #define __CORE_CLK_PRE  6144000UL\n                #elif (((RCC_Val>>6) & 0x1F) == 0xD)\n                      #define __CORE_CLK_PRE  7372800UL\n                #elif (((RCC_Val>>6) & 0x1F) == 0xE)\n                      #define __CORE_CLK_PRE  8000000UL\n                #elif (((RCC_Val>>6) & 0x1F) == 0xF)\n                      #define __CORE_CLK_PRE  8192000UL\n                #elif (((RCC_Val>>6) & 0x1F) == 0x10)\n                      #define __CORE_CLK_PRE  10000000UL\n                #elif (((RCC_Val>>6) & 0x1F) == 0x11)\n                      #define __CORE_CLK_PRE  12000000UL\n                #elif (((RCC_Val>>6) & 0x1F) == 0x12)\n                      #define __CORE_CLK_PRE  12288000UL\n                #elif (((RCC_Val>>6) & 0x1F) == 0x13)\n                      #define __CORE_CLK_PRE  13560000UL\n                #elif (((RCC_Val>>6) & 0x1F) == 0x14)\n                      #define __CORE_CLK_PRE  14318180UL\n                #elif (((RCC_Val>>6) & 0x1F) == 0x15)\n                      #define __CORE_CLK_PRE  16000000UL\n                #else\n                      #define __CORE_CLK_PRE  16384000UL\n                #endif\n              #elif (((RCC2_Val>>4) & 0x07) == 0x1)\n                  #define __CORE_CLK_PRE  XTALI\n              #elif (((RCC2_Val>>4) & 0x07) == 0x2)\n                  #define __CORE_CLK_PRE  (XTALI/4)\n              #else\n                  #define __CORE_CLK_PRE  XTAL30K\n              #endif\n    #else\n      #define __CORE_CLK_PRE   PLL_CLK\n    #endif\n    #if (RCC_Val & (1UL<<22))                            /* check USESYSDIV */\n      #if (RCC2_Val & (1UL<<11))\n        #define __CORE_CLK  (__CORE_CLK_PRE / (((RCC2_Val>>23) & (0x3F)) + 1))\n      #else\n        #define __CORE_CLK  (__CORE_CLK_PRE / (((RCC2_Val>>23) & (0x3F)) + 1) / 2)\n      #endif\n    #else\n      #define __CORE_CLK  __CORE_CLK_PRE\n    #endif\n  #else\n    #if (RCC_Val & (1UL<<11))                           /* check BYPASS */\n              #if   (((RCC_Val>>4) & 0x03) == 0x0)\n                #if   (((RCC_Val>>6) & 0x1F) == 0x0)\n                      #define __CORE_CLK_PRE  1000000UL\n                #elif (((RCC_Val>>6) & 0x1F) == 0x1)\n                      #define __CORE_CLK_PRE  1843200UL\n                #elif (((RCC_Val>>6) & 0x1F) == 0x2)\n                      #define __CORE_CLK_PRE  2000000UL\n                #elif (((RCC_Val>>6) & 0x1F) == 0x3)\n                      #define __CORE_CLK_PRE  2457600UL\n                #elif (((RCC_Val>>6) & 0x1F) == 0x4)\n                      #define __CORE_CLK_PRE  3579545UL\n                #elif (((RCC_Val>>6) & 0x1F) == 0x5)\n                      #define __CORE_CLK_PRE  3686400UL\n                #elif (((RCC_Val>>6) & 0x1F) == 0x6)\n                      #define __CORE_CLK_PRE  4000000UL\n                #elif (((RCC_Val>>6) & 0x1F) == 0x7)\n                      #define __CORE_CLK_PRE  4096000UL\n                #elif (((RCC_Val>>6) & 0x1F) == 0x8)\n                      #define __CORE_CLK_PRE  4915200UL\n                #elif (((RCC_Val>>6) & 0x1F) == 0x9)\n                      #define __CORE_CLK_PRE  5000000UL\n                #elif (((RCC_Val>>6) & 0x1F) == 0xA)\n                      #define __CORE_CLK_PRE  5120000UL\n                #elif (((RCC_Val>>6) & 0x1F) == 0xB)\n                      #define __CORE_CLK_PRE  6000000UL\n                #elif (((RCC_Val>>6) & 0x1F) == 0xC)\n                      #define __CORE_CLK_PRE  6144000UL\n                #elif (((RCC_Val>>6) & 0x1F) == 0xD)\n                      #define __CORE_CLK_PRE  7372800UL\n                #elif (((RCC_Val>>6) & 0x1F) == 0xE)\n                      #define __CORE_CLK_PRE  8000000UL\n                #elif (((RCC_Val>>6) & 0x1F) == 0xF)\n                      #define __CORE_CLK_PRE  8192000UL\n                #elif (((RCC_Val>>6) & 0x1F) == 0x10)\n                      #define __CORE_CLK_PRE  10000000UL\n                #elif (((RCC_Val>>6) & 0x1F) == 0x11)\n                      #define __CORE_CLK_PRE  12000000UL\n                #elif (((RCC_Val>>6) & 0x1F) == 0x12)\n                      #define __CORE_CLK_PRE  12288000UL\n                #elif (((RCC_Val>>6) & 0x1F) == 0x13)\n                      #define __CORE_CLK_PRE  13560000UL\n                #elif (((RCC_Val>>6) & 0x1F) == 0x14)\n                      #define __CORE_CLK_PRE  14318180UL\n                #elif (((RCC_Val>>6) & 0x1F) == 0x15)\n                      #define __CORE_CLK_PRE  16000000UL\n                #else\n                      #define __CORE_CLK_PRE  16384000UL\n                #endif\n              #elif (((RCC_Val>>4) & 0x03) == 0x1)\n                  #define __CORE_CLK_PRE  XTALI\n              #elif (((RCC_Val>>4) & 0x03) == 0x2)\n                  #define __CORE_CLK_PRE  (XTALI/4)\n              #else\n                  #define __CORE_CLK_PRE  XTAL30K\n              #endif\n    #else\n      #define __CORE_CLK_PRE   PLL_CLK\n    #endif\n    #if (RCC_Val & (1UL<<22))                            /* check USESYSDIV */\n      #if (RCC_Val & (1UL<<11))                          /* check BYPASS */\n        #define __CORE_CLK  (__CORE_CLK_PRE / (((RCC_Val>>23) & (0x0F)) + 1))\n      #else\n        #define __CORE_CLK  (__CORE_CLK_PRE / (((RCC_Val>>23) & (0x0F)) + 1) / 2)\n      #endif\n    #else\n      #define __CORE_CLK  __CORE_CLK_PRE\n    #endif\n  #endif\n\n\n/*----------------------------------------------------------------------------\n  Clock Variable definitions\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = __CORE_CLK;  /*!< System Clock Frequency (Core Clock)*/\n\n\n/*----------------------------------------------------------------------------\n  Clock functions\n *----------------------------------------------------------------------------*/\n\n/*----------------------------------------------------------------------------\n  Get the OSC clock\n *----------------------------------------------------------------------------*/\nstatic uint32_t getOscClk (uint32_t xtal, uint32_t oscSrc) {\n  uint32_t oscClk = XTALI;\n\n  switch (oscSrc) {                      /* switch OSCSRC */\n    case 0:                              /* MOSC Main oscillator */\n      switch (xtal) {                    /* switch XTAL */\n        case 0x0:\n          oscClk = 1000000UL;\n          break;\n        case 0x1:\n          oscClk = 1843200UL;\n          break;\n        case 0x2:\n          oscClk = 2000000UL;\n          break;\n        case 0x3:\n          oscClk = 2457600UL;\n          break;\n        case 0x4:\n          oscClk = 3579545UL;\n          break;\n        case 0x5:\n          oscClk = 3686400UL;\n          break;\n        case 0x6:\n          oscClk = 4000000UL;\n          break;\n        case 0x7:\n          oscClk = 4096000UL;\n          break;\n        case 0x8:\n          oscClk = 4915200UL;\n          break;\n        case 0x9:\n          oscClk = 5000000UL;\n          break;\n        case 0xA:\n          oscClk = 5120000UL;\n          break;\n        case 0xB:\n          oscClk = 6000000UL;\n          break;\n        case 0xC:\n          oscClk = 6144000UL;\n          break;\n        case 0xD:\n          oscClk = 7372800UL;\n          break;\n        case 0xE:\n          oscClk = 8000000UL;\n          break;\n        case 0xF:\n          oscClk = 8192000UL;\n          break;\n        case 0x10:\n          oscClk = 10000000UL;\n          break;\n        case 0x11:\n          oscClk = 12000000UL;\n          break;\n        case 0x12:\n          oscClk = 12288000UL;\n          break;\n        case 0x13:\n          oscClk = 13560000UL;\n          break;\n        case 0x14:\n          oscClk = 14318180UL;\n          break;\n        case 0x15:\n          oscClk = 16000000UL;\n          break;\n        case 0x16:\n          oscClk = 16384000UL;\n          break;\n       }\n      break;\n    case 1:                         /* IOSC Internal oscillator */\n      oscClk = XTALI;\n      break;\n    case 2:                         /* IOSC/4 Internal oscillator/4 */\n      oscClk = XTALI/4;\n      break;\n    case 3:                         /* 30kHz internal oscillator  */\n      oscClk = XTAL30K;\n      break;\n  }\n\n  return oscClk;\n}\n\nvoid SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */\n{\n    uint32_t rcc, rcc2;\n\n    /* Determine clock frequency according to clock register values */\n    rcc  = SYSCTL->RCC;\n    rcc2 = SYSCTL->RCC2;\n\n  //if (rcc2 & SYSCTL_RCC2_USERCC2)\n    if (rcc2 & (1UL<<31)) {                             /* is rcc2 is used ? */\n  //  if (rcc2 & SYSCTL_RCC2_BYPASS2)\n      if (rcc2 & (1UL<<11)) {                           /* check BYPASS */\n        SystemCoreClock = getOscClk (((rcc>>6) & 0x0F),((rcc2>>4) & 0x07));\n      } else {\n        SystemCoreClock = PLL_CLK;\n      }\n      if (rcc & (1UL<<22)) {                            /* check USESYSDIV */\n        if (rcc2 & (1UL<<11)) {\n          SystemCoreClock = SystemCoreClock / (((rcc2>>23) & (0x3F)) + 1);\n        } else {\n          SystemCoreClock = SystemCoreClock / (((rcc2>>23) & (0x3F)) + 1) / 2;\n        }\n      }\n    } else {\n  //    if (RCC_Val & (1UL<<11)) {                            /* check BYPASS */\n      if (rcc & (1UL<<11)) {                            /* check BYPASS */ /* Simulation does not work at this point */\n        SystemCoreClock = getOscClk (((rcc>>6) & 0x1F),((rcc>>4) & 0x03));\n      } else {\n        SystemCoreClock = PLL_CLK;\n      }\n  //  if (rcc & SYSCTL_RCC_USE_SYSDIV)\n      if (rcc & (1UL<<22)) {                            /* check USESYSDIV */\n  //    if (rcc2 & SYSCTL_RCC_BYPASS)\n        if (rcc & (1UL<<11)) {                          /* check BYPASS */ /* Simulation does not work at this point */\n  //      if (RCC_Val & (1UL<<11)) {                          /* check BYPASS */\n          SystemCoreClock = SystemCoreClock / (((rcc>>23) & (0x0F)) + 1);\n        } else {\n          SystemCoreClock = SystemCoreClock / (((rcc>>23) & (0x0F)) + 1) / 2;\n        }\n      }\n    }\n}\n\n/**\n * Initialize the system\n *\n * @param  none\n * @return none\n *\n * @brief  Setup the microcontroller system.\n *         Initialize the System.\n */\nvoid SystemInit (void)\n{\n#if(CLOCK_SETUP)\n    volatile uint32_t i;\n#endif\n\n  /* FPU settings ------------------------------------------------------------*/\n  #if (__FPU_USED == 1)\n    SCB->CPACR |= ((3UL << 10*2) |                 /* set CP10 Full Access */\n                   (3UL << 11*2)  );               /* set CP11 Full Access */\n  #endif\n\n#if(CLOCK_SETUP)\n    SYSCTL->RCC2 = 0x07802810;    /* set default value */\n    SYSCTL->RCC  = 0x078E3AD1;    /* set default value */\n\n    SYSCTL->RCC  = (RCC_Val  | (1UL<<11) | (1UL<<13)) & ~(1UL<<22); /* set value with BYPASS, PWRDN set, USESYSDIV reset */\n    SYSCTL->RCC2 = (RCC2_Val | (1UL<<11) | (1UL<<13));              /* set value with BYPASS, PWRDN set */\n    for (i = 0; i < 1000; i++);   /* wait a while */\n\n    SYSCTL->RCC  = (RCC_Val  | (1UL<<11)) & ~(1UL<<22);             /* set value with BYPASS, USESYSDIV reset */\n    SYSCTL->RCC2 = (RCC2_Val | (1UL<<11));                          /* set value with BYPASS */\n    for (i = 0; i < 1000; i++);   /* wait a while */\n\n    SYSCTL->RCC  = (RCC_Val  | (1<<11));                            /* set value with BYPASS */\n\n    if ( (((RCC_Val  & (1UL<<13)) == 0) && ((RCC2_Val & (1UL<<31)) == 0)) ||\n         (((RCC2_Val & (1UL<<13)) == 0) && ((RCC2_Val & (1UL<<31)) != 0))   ) {\n      while ((SYSCTL->RIS & (1UL<<6)) != (1UL<<6));                 /* wait until PLL is locked */\n    }\n\n    SYSCTL->RCC  = (RCC_Val);                                       /* set value */\n    SYSCTL->RCC2 = (RCC2_Val);                                      /* set value */\n    for (i = 0; i < 10000; i++);   /* wait a while */\n\n#endif\n}\n"
  },
  {
    "path": "3rd_party/ek-tm4c123gxl/system_TM4C123GH6PM.h",
    "content": "/**************************************************************************//**\n * @file     system_TM4C123GH6PM.h\n * @brief    CMSIS Cortex-M4 Device Peripheral Access Layer Header File for\n *           TI Tiva TM4C123 Class Devices\n * @version  V3.1\n * @date     15. May 2013\n *\n * @note\n * Copyright (C) 2010-2011 ARM Limited. All rights reserved.\n *\n * @par\n * ARM Limited (ARM) is supplying this software for use with Cortex-M\n * processor based microcontrollers.  This file can be freely distributed\n * within development tools that are supporting such ARM based processors.\n *\n * @par\n * THIS SOFTWARE IS PROVIDED \"AS IS\".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\n ******************************************************************************/\n\n\n#ifndef SYSTEM_TM4C123_H\n#define SYSTEM_TM4C123_H\n\n#include <stdint.h>\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\nextern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */\n\n\n/**\n * Initialize the system\n *\n * @param  none\n * @return none\n *\n * @brief  Setup the microcontroller system.\n *         Initialize the System and update the SystemCoreClock variable.\n */\nextern void SystemInit (void);\n\n/**\n * Update SystemCoreClock variable\n *\n * @param  none\n * @return none\n *\n * @brief  Updates the SystemCoreClock with current core Clock\n *         retrieved from cpu registers.\n */\nextern void SystemCoreClockUpdate (void);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* SYSTEM_TM4C123_H */\n"
  },
  {
    "path": "3rd_party/nucleo-c031c6/README.txt",
    "content": "This directory contains embedded code for the STM32 NUCLEO-C031C6\nboard. This code is then used to build ET tests for this board.\nSee also the examples/ directory, make_nucleo-l152re makefiles.\n"
  },
  {
    "path": "3rd_party/nucleo-c031c6/arm/startup_stm32c031xx.s",
    "content": ";/***************************************************************************/\n; * @file     startup_stm32c031xx.s for ARM-KEIL ARM assembler\n; * @brief    CMSIS Cortex-M0+ Core Device Startup File for STM32C031xx\n; * @version  CMSIS 5.9.0\n; * @date     1 Feb 2023\n; *\n; * Modified by Quantum Leaps:\n; * - Added relocating of the Vector Table to free up the 256B region at 0x0\n; *   for NULL-pointer protection by the MPU.\n; * - Modified all exception handlers to branch to assert_failed()\n; *   instead of locking up the CPU inside an endless loop.\n; *\n; * @description\n; * Created from the CMSIS template for the specified device\n; * Quantum Leaps, www.state-machine.com\n; *\n; * @note\n; * The symbols Stack_Size and Heap_Size should be provided on the command-\n; * line options to the assembler, for example as:\n; *     --pd \"Stack_Size SETA 1024\" --pd \"Heap_Size SETA 0\"\n\n\n;******************************************************************************\n; Allocate space for the stack.\n;\n        AREA    STACK, NOINIT, READWRITE, ALIGN=3\n__stack_base\nStackMem\n        SPACE   Stack_Size    ; provided in command-line option, for example:\n                              ; --pd \"Stack_Size SETA 512\"\n__stack_limit\n__initial_sp\n\n;******************************************************************************\n; Allocate space for the heap.\n;\n        AREA    HEAP, NOINIT, READWRITE, ALIGN=3\n__heap_base\nHeapMem\n        SPACE   Heap_Size     ; provided in command-line option, for example:\n                              ; --pd \"Heap_Size SETA 0\"\n__heap_limit\n\n; Indicate that the code in this file preserves 8-byte alignment of the stack.\n        PRESERVE8\n\n;******************************************************************************\n; The vector table.\n;\n; Place code into the reset code section.\n        AREA   RESET, DATA, READONLY, ALIGN=8\n        EXPORT  __Vectors\n        EXPORT  __Vectors_End\n        EXPORT  __Vectors_Size\n\n__Vectors\n    ; Initial Vector Table before relocation\n        DCD     __initial_sp                ; Top of Stack\n        DCD     Reset_Handler               ; Reset Handler\n        DCD     NMI_Handler                 ; NMI Handler\n        DCD     HardFault_Handler           ; Hard Fault Handler\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     SVC_Handler                 ; SVCall handler\n        DCD     DebugMon_Handler            ; Debug Monitor handler\n        DCD     Default_Handler             ; Reserved\n        DCD     PendSV_Handler              ; PendSV handler\n        DCD     SysTick_Handler             ; SysTick handler\n\n        ; IRQ handlers...\n        DCD     WWDG_IRQHandler             ; [ 0] Window Watchdog\n        DCD     Reserved1_IRQHandler        ; [ 1] Reserved\n        DCD     RTC_IRQHandler              ; [ 2] RTC through EXTI Line\n        DCD     FLASH_IRQHandler            ; [ 3] FLASH\n        DCD     RCC_IRQHandler              ; [ 4] RCC\n        DCD     EXTI0_1_IRQHandler          ; [ 5] EXTI Line 0 and 1\n        DCD     EXTI2_3_IRQHandler          ; [ 6] EXTI Line 2 and 3\n        DCD     EXTI4_15_IRQHandler         ; [ 7] EXTI Line 4 to 15\n        DCD     Reserved8_IRQHandler        ; [ 8] Reserved\n        DCD     DMA1_Channel1_IRQHandler    ; [ 9] DMA1 Channel 1\n        DCD     DMA1_Channel2_3_IRQHandler  ; [10] DMA1 Channel 2 and Channel 3\n        DCD     DMAMUX1_IRQHandler          ; [11] DMAMUX\n        DCD     ADC1_IRQHandler             ; [12] ADC1\n        DCD     TIM1_BRK_UP_TRG_COM_IRQHandler ; [13] TIM1 Break, Update, Trigger and Commutation\n        DCD     TIM1_CC_IRQHandler          ; [14] TIM1 Capture Compare\n        DCD     Reserved15_IRQHandler       ; [15] Reserved\n        DCD     TIM3_IRQHandler             ; [16] TIM3\n        DCD     Reserved17_IRQHandler       ; [17] Reserved\n        DCD     Reserved18_IRQHandler       ; [18] Reserved\n        DCD     TIM14_IRQHandler            ; [19] TIM14\n        DCD     Reserved20_IRQHandler       ; [20] Reserved\n        DCD     TIM16_IRQHandler            ; [21] TIM16\n        DCD     TIM17_IRQHandler            ; [22] TIM17\n        DCD     I2C1_IRQHandler             ; [23] I2C1\n        DCD     Reserved24_IRQHandler       ; [24] Reserved\n        DCD     SPI1_IRQHandler             ; [25] SPI1\n        DCD     Reserved26_IRQHandler       ; [26] Reserved\n        DCD     USART1_IRQHandler           ; [27] USART1\n        DCD     USART2_IRQHandler           ; [28] USART2\n        DCD     Reserved29_IRQHandler       ; [29] Reserved\n        DCD     Reserved30_IRQHandler       ; [30] Reserved\n        DCD     Reserved31_IRQHandler       ; [31] Reserved\n\n__Vectors_End\n\n__Vectors_Size  EQU   __Vectors_End - __Vectors\n\n\n;******************************************************************************\n; This is the code for exception handlers.\n;\n        AREA    |.text|, CODE, READONLY\n\n;******************************************************************************\n; This is the code that gets called when the processor first starts execution\n; following a reset event.\n;\nReset_Handler   PROC\n        EXPORT  Reset_Handler  [WEAK]\n        IMPORT  SystemInit\n        IMPORT  __main\n        IMPORT  assert_failed\n\n        LDR     r0,=SystemInit  ; CMSIS system initialization\n        BLX     r0\n\n        ; Call the C library enty point that handles startup. This will copy\n        ; the .data section initializers from flash to SRAM and zero fill the\n        ; .bss section.\n        ; NOTE: The __main function clears the C stack as well\n        LDR     r0,=__main\n        BX      r0\n\n        ; __main calls the main() function, which should not return,\n        ; but just in case jump to assert_failed() if main returns.\n        LDR     r0,=str_EXIT\n        MOVS    r1,#1\n        LDR     r2,=__initial_sp  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_EXIT\n        DCB     \"EXIT\"\n        ALIGN\n        ENDP\n\n;******************************************************************************\nNMI_Handler     PROC\n        EXPORT  NMI_Handler     [WEAK]\n        IMPORT  assert_failed\n        LDR     r0,=str_NMI\n        MOVS    r1,#1\n        LDR     r2,=__initial_sp  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_NMI\n        DCB     \"NMI\"\n        ALIGN\n        ENDP\n\n;******************************************************************************\nHardFault_Handler PROC\n        EXPORT  HardFault_Handler [WEAK]\n        IMPORT  assert_failed\n        LDR     r0,=str_HardFault\n        MOVS    r1,#1\n        LDR     r2,=__initial_sp  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_HardFault\n        DCB     \"HardFault\"\n        ALIGN\n        ENDP\n\n\n\n;******************************************************************************\n;\n; Weak non-fault handlers...\n;\n\n;******************************************************************************\nSVC_Handler PROC\n        EXPORT  SVC_Handler   [WEAK]\n        IMPORT  assert_failed\n        LDR     r0,=str_SVC\n        MOVS    r1,#1\n        LDR     r2,=__initial_sp  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_SVC\n        DCB     \"SVC\"\n        ALIGN\n        ENDP\n\n;******************************************************************************\nDebugMon_Handler PROC\n        EXPORT  DebugMon_Handler     [WEAK]\n        IMPORT  assert_failed\n        LDR     r0,=str_DebugMon\n        MOVS    r1,#1\n        LDR     r2,=__initial_sp  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_DebugMon\n        DCB     \"DebugMon\"\n        ALIGN\n        ENDP\n\n;******************************************************************************\nPendSV_Handler PROC\n        EXPORT  PendSV_Handler       [WEAK]\n        IMPORT  assert_failed\n        LDR     r0,=str_PendSV\n        MOVS    r1,#1\n        LDR     r2,=__initial_sp  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_PendSV\n        DCB     \"PendSV\"\n        ALIGN\n        ENDP\n\n;******************************************************************************\nSysTick_Handler PROC\n        EXPORT  SysTick_Handler     [WEAK]\n        IMPORT  assert_failed\n        LDR     r0,=str_SysTick\n        MOVS    r1,#1\n        LDR     r2,=__initial_sp  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_SysTick\n        DCB     \"SysTick\"\n        ALIGN\n        ENDP\n\n;******************************************************************************\nDefault_Handler PROC\n        EXPORT  WWDG_IRQHandler                [WEAK]\n        EXPORT  RTC_IRQHandler                 [WEAK]\n        EXPORT  FLASH_IRQHandler               [WEAK]\n        EXPORT  RCC_IRQHandler                 [WEAK]\n        EXPORT  EXTI0_1_IRQHandler             [WEAK]\n        EXPORT  EXTI2_3_IRQHandler             [WEAK]\n        EXPORT  EXTI4_15_IRQHandler            [WEAK]\n        EXPORT  DMA1_Channel1_IRQHandler       [WEAK]\n        EXPORT  DMA1_Channel2_3_IRQHandler     [WEAK]\n        EXPORT  DMAMUX1_IRQHandler             [WEAK]\n        EXPORT  ADC1_IRQHandler                [WEAK]\n        EXPORT  TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]\n        EXPORT  TIM1_CC_IRQHandler             [WEAK]\n        EXPORT  TIM3_IRQHandler                [WEAK]\n        EXPORT  TIM14_IRQHandler               [WEAK]\n        EXPORT  TIM16_IRQHandler               [WEAK]\n        EXPORT  TIM17_IRQHandler               [WEAK]\n        EXPORT  I2C1_IRQHandler                [WEAK]\n        EXPORT  SPI1_IRQHandler                [WEAK]\n        EXPORT  USART1_IRQHandler              [WEAK]\n        EXPORT  USART2_IRQHandler              [WEAK]\n        EXPORT  Reserved1_IRQHandler           [WEAK]\n        EXPORT  Reserved8_IRQHandler           [WEAK]\n        EXPORT  Reserved15_IRQHandler          [WEAK]\n        EXPORT  Reserved17_IRQHandler          [WEAK]\n        EXPORT  Reserved18_IRQHandler          [WEAK]\n        EXPORT  Reserved20_IRQHandler          [WEAK]\n        EXPORT  Reserved24_IRQHandler          [WEAK]\n        EXPORT  Reserved26_IRQHandler          [WEAK]\n        EXPORT  Reserved29_IRQHandler          [WEAK]\n        EXPORT  Reserved30_IRQHandler          [WEAK]\n        EXPORT  Reserved31_IRQHandler          [WEAK]\n\nWWDG_IRQHandler\nRTC_IRQHandler\nFLASH_IRQHandler\nRCC_IRQHandler\nEXTI0_1_IRQHandler\nEXTI2_3_IRQHandler\nEXTI4_15_IRQHandler\nDMA1_Channel1_IRQHandler\nDMA1_Channel2_3_IRQHandler\nDMAMUX1_IRQHandler\nADC1_IRQHandler\nTIM1_BRK_UP_TRG_COM_IRQHandler\nTIM1_CC_IRQHandler\nTIM3_IRQHandler\nTIM14_IRQHandler\nTIM16_IRQHandler\nTIM17_IRQHandler\nI2C1_IRQHandler\nSPI1_IRQHandler\nUSART1_IRQHandler\nUSART2_IRQHandler\nReserved1_IRQHandler\nReserved8_IRQHandler\nReserved15_IRQHandler\nReserved17_IRQHandler\nReserved18_IRQHandler\nReserved20_IRQHandler\nReserved24_IRQHandler\nReserved26_IRQHandler\nReserved29_IRQHandler\nReserved30_IRQHandler\nReserved31_IRQHandler\n        LDR     r0,=str_Undefined\n        MOVS    r1,#1\n        LDR     r2,=__initial_sp  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_Undefined\n        DCB     \"Undefined\"\n        ALIGN\n        ENDP\n\n        ALIGN               ; make sure the end of this section is aligned\n\n;******************************************************************************\n; The function expected of the C library startup code for defining the stack\n; and heap memory locations.  For the C library version of the startup code,\n; provide this function so that the C library initialization code can find out\n; the location of the stack and heap.\n;\n    IF :DEF: __MICROLIB\n        EXPORT  __initial_sp\n        EXPORT  __stack_limit\n        EXPORT  __heap_base\n        EXPORT  __heap_limit\n    ELSE\n        IMPORT  __use_two_region_memory\n        EXPORT  __user_initial_stackheap\n\n__user_initial_stackheap PROC\n        LDR     R0, =__heap_base\n        LDR     R1, =__stack_limit\n        LDR     R2, =__heap_limit\n        LDR     R3, =__stack_base\n        BX      LR\n        ENDP\n    ENDIF\n        ALIGN               ; make sure the end of this section is aligned\n\n    END                     ; end of module\n\n"
  },
  {
    "path": "3rd_party/nucleo-c031c6/gnu/nucleo-c031c6.ld",
    "content": "/*****************************************************************************\n* Linker script for for STM32C031C6, GNU-ARM linker\n*\n*                    Q u a n t u m  L e a P s\n*                    ------------------------\n*                    Modern Embedded Software\n*\n* Copyright (C) 2005 Quantum Leaps, LLC <state-machine.com>.\n*\n* SPDX-License-Identifier: GPL-3.0-or-later OR LicenseRef-QL-commercial\n*\n* This software is dual-licensed under the terms of the open source GNU\n* General Public License version 3 (or any later version), or alternatively,\n* under the terms of one of the closed source Quantum Leaps commercial\n* licenses.\n*\n* The terms of the open source GNU General Public License version 3\n* can be found at: <www.gnu.org/licenses/gpl-3.0>\n*\n* The terms of the closed source Quantum Leaps commercial licenses\n* can be found at: <www.state-machine.com/licensing>\n*\n* Redistributions in source code must retain this top-level comment block.\n* Plagiarizing this software to sidestep the license obligations is illegal.\n*\n* Contact information:\n* <www.state-machine.com/licensing>\n* <info@state-machine.com>\n*****************************************************************************/\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nENTRY(Reset_Handler) /* entry Point */\n\nMEMORY { /* memory map of STM32C031C6 */\n    ROM (rx)  : ORIGIN = 0x08000000, LENGTH = 32K\n    RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 12K\n}\n\n/* The size of the stack used by the application. NOTE: you need to adjust  */\nSTACK_SIZE = 2048;\n\n/* The size of the heap used by the application. NOTE: you need to adjust   */\nHEAP_SIZE = 0;\n\nSECTIONS {\n\n    .isr_vector : {        /* the vector table goes FIRST into ROM */\n        KEEP(*(.isr_vector)) /* vector table */\n        . = ALIGN(4);\n    } >ROM\n\n    .text : {              /* code and constants */\n        . = ALIGN(4);\n        *(.text)           /* .text sections (code) */\n        *(.text*)          /* .text* sections (code) */\n        *(.rodata)         /* .rodata sections (constants, strings, etc.) */\n        *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */\n\n        KEEP (*(.init))\n        KEEP (*(.fini))\n\n        . = ALIGN(4);\n    } >ROM\n\n    .preinit_array : {\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP (*(.preinit_array*))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n    } >ROM\n\n    .init_array : {\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array*))\n        PROVIDE_HIDDEN (__init_array_end = .);\n    } >ROM\n\n    .fini_array : {\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP (*(.fini_array*))\n        KEEP (*(SORT(.fini_array.*)))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n    } >ROM\n\n    _etext = .;            /* global symbols at end of code */\n\n    .stack : {\n        __stack_start__ = .;\n        . = . + STACK_SIZE;\n        . = ALIGN(4);\n        __stack_end__ = .;\n    } >RAM\n\n    .data :  AT (_etext) {\n        __data_load = LOADADDR (.data);\n        __data_start = .;\n        *(.data)           /* .data sections */\n        *(.data*)          /* .data* sections */\n        . = ALIGN(4);\n        __data_end__ = .;\n        _edata = __data_end__;\n    } >RAM\n\n    .bss : {\n        __bss_start__ = .;\n        *(.bss)\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = .;         /* define a global symbol at bss end */\n        __bss_end__ = .;\n    } >RAM\n\n    __exidx_start = .;\n    .ARM.exidx   : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } >RAM\n    __exidx_end = .;\n\n    PROVIDE ( end = _ebss );\n    PROVIDE ( _end = _ebss );\n    PROVIDE ( __end__ = _ebss );\n\n    .heap : {\n        __heap_start__ = .;\n        . = . + HEAP_SIZE;\n        . = ALIGN(4);\n        __heap_end__ = .;\n    } >RAM\n\n    /* Remove information from the standard libraries */\n    /DISCARD/ : {\n        libc.a ( * )\n        libm.a ( * )\n        libgcc.a ( * )\n    }\n}\n"
  },
  {
    "path": "3rd_party/nucleo-c031c6/gnu/startup_stm32c031xx.c",
    "content": "/* File: startup_stm32c031xx.c for GNU-ARM\n * Purpose: startup file for STM32C031xx Cortex-M0+ device.\n *          Should be used with GCC 'GNU Tools ARM Embedded'\n * Version: CMSIS 5.0.1\n * Date: 2017-09-13\n *\n * Modified by Quantum Leaps:\n * - Added relocating of the Vector Table to free up the 256B region at 0x0\n *   for NULL-pointer protection by the MPU.\n * - Modified all exception handlers to branch to assert_failed()\n *   instead of locking up the CPU inside an endless loop.\n *\n * Created from the CMSIS template for the specified device\n * Quantum Leaps, www.state-machine.com\n *\n * NOTE:\n * The function assert_failed defined at the end of this file defines\n * the error/assertion handling policy for the application and might\n * need to be customized for each project. This function is defined in\n * assembly to re-set the stack pointer, in case it is corrupted by the\n * time assert_failed is called.\n */\n\n/* start and end of stack defined in the linker script ---------------------*/\n/*extern int __stack_start__;*/\nextern int __stack_end__;\n\n/* Weak prototypes for error handlers --------------------------------------*/\n/**\n* \\note\n* The function assert_failed defined at the end of this file defines\n* the error/assertion handling policy for the application and might\n* need to be customized for each project. This function is defined in\n* assembly to avoid accessing the stack, which might be corrupted by\n* the time assert_failed is called.\n*/\n__attribute__ ((naked, noreturn))\nvoid assert_failed(char const *module, int loc);\n\n/* Function prototypes -----------------------------------------------------*/\nvoid Default_Handler(void);  /* Default empty handler */\nvoid Reset_Handler(void);    /* Reset Handler */\nvoid SystemInit(void);       /* CMSIS system initialization */\n\n/*----------------------------------------------------------------------------\n* weak aliases for each Exception handler to the Default_Handler.\n* Any function with the same name will override these definitions.\n*/\n/* Cortex-M Processor fault exceptions... */\nvoid NMI_Handler           (void) __attribute__ ((weak));\nvoid HardFault_Handler     (void) __attribute__ ((weak));\nvoid MemManage_Handler     (void) __attribute__ ((weak));\nvoid BusFault_Handler      (void) __attribute__ ((weak));\nvoid UsageFault_Handler    (void) __attribute__ ((weak));\n\n/* Cortex-M Processor non-fault exceptions... */\nvoid SVC_Handler           (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n/* external interrupts...   */\nvoid WWDG_IRQHandler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Reserved1_IRQHandler  (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid RTC_IRQHandler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid FLASH_IRQHandler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid RCC_IRQHandler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid EXTI0_1_IRQHandler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid EXTI2_3_IRQHandler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid EXTI4_15_IRQHandler   (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Reserved8_IRQHandler  (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DMA1_Channel1_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DMA1_Channel2_3_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DMAMUX1_IRQHandler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid ADC1_IRQHandler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid TIM1_BRK_UP_TRG_COM_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid TIM1_CC_IRQHandler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Reserved15_IRQHandler (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid TIM3_IRQHandler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Reserved17_IRQHandler (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Reserved18_IRQHandler (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid TIM14_IRQHandler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Reserved20_IRQHandler (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid TIM16_IRQHandler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid TIM17_IRQHandler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid I2C1_IRQHandler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Reserved24_IRQHandler (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SPI1_IRQHandler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Reserved26_IRQHandler (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid USART1_IRQHandler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid USART2_IRQHandler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Reserved29_IRQHandler (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Reserved30_IRQHandler (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Reserved31_IRQHandler (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n/*..........................................................................*/\n__attribute__ ((section(\".isr_vector\")))\nint const g_pfnVectors[] = {\n    (int)&__stack_end__,          /* Top of Stack                   */\n    (int)&Reset_Handler,          /* Reset Handler                  */\n    (int)&NMI_Handler,            /* NMI Handler                    */\n    (int)&HardFault_Handler,      /* Hard Fault Handler             */\n    (int)&Default_Handler,        /* Reserved                       */\n    (int)&Default_Handler,        /* Reserved                       */\n    (int)&Default_Handler,        /* Reserved                       */\n    (int)&Default_Handler,        /* Reserved                       */\n    (int)&Default_Handler,        /* Reserved                       */\n    (int)&Default_Handler,        /* Reserved                       */\n    (int)&Default_Handler,        /* Reserved                       */\n    (int)&SVC_Handler,            /* SVCall handler                 */\n    (int)&DebugMon_Handler,       /* Debug monitor handler          */\n    (int)&Default_Handler,        /* Reserved                       */\n    (int)&PendSV_Handler,         /* The PendSV handler             */\n    (int)&SysTick_Handler,        /* The SysTick handler            */\n\n    /*IRQ handlers... */\n    (int)&WWDG_IRQHandler,        /* [ 0] Window Watchdog           */\n    (int)&Reserved1_IRQHandler,   /* [ 1] Reserved                  */\n    (int)&RTC_IRQHandler,         /* [ 2] RTC through EXTI Line     */\n    (int)&FLASH_IRQHandler,       /* [ 3] FLASH                     */\n    (int)&RCC_IRQHandler,         /* [ 4] RCC                       */\n    (int)&EXTI0_1_IRQHandler,     /* [ 5] EXTI Line 0 and 1         */\n    (int)&EXTI2_3_IRQHandler,     /* [ 6] EXTI Line 2 and 3         */\n    (int)&EXTI4_15_IRQHandler,    /* [ 7] EXTI Line 4 to 15         */\n    (int)&Reserved8_IRQHandler,   /* [ 8] Reserved                  */\n    (int)&DMA1_Channel1_IRQHandler,/* [ 9] DMA1 Channel 1           */\n    (int)&DMA1_Channel2_3_IRQHandler,/* [10] DMA1 Channel 2 and Channel 3 */\n    (int)&DMAMUX1_IRQHandler,     /* [11] DMAMUX                    */\n    (int)&ADC1_IRQHandler,        /* [12] ADC1                      */\n    (int)&TIM1_BRK_UP_TRG_COM_IRQHandler,/* [13] TIM1 Break,Update,Trigger & Comm */\n    (int)&TIM1_CC_IRQHandler,     /* [14] TIM1 Capture Compare      */\n    (int)&Reserved15_IRQHandler,  /* [15] Reserved                  */\n    (int)&TIM3_IRQHandler,        /* [16] TIM3                      */\n    (int)&Reserved17_IRQHandler,  /* [17] Reserved                  */\n    (int)&Reserved18_IRQHandler,  /* [18] Reserved                  */\n    (int)&TIM14_IRQHandler,       /* [19] TIM14                     */\n    (int)&Reserved20_IRQHandler,  /* [20] Reserved                  */\n    (int)&TIM16_IRQHandler,       /* [21] TIM16                     */\n    (int)&TIM17_IRQHandler,       /* [22] TIM17                     */\n    (int)&I2C1_IRQHandler,        /* [23] I2C1                      */\n    (int)&Reserved24_IRQHandler,  /* [24] Reserved                  */\n    (int)&SPI1_IRQHandler,        /* [25] SPI1                      */\n    (int)&Reserved26_IRQHandler,  /* [26] Reserved                  */\n    (int)&USART1_IRQHandler,      /* [27] USART1                    */\n    (int)&USART2_IRQHandler,      /* [28] USART2                    */\n    (int)&Reserved29_IRQHandler,  /* [29] Reserved                  */\n    (int)&Reserved30_IRQHandler,  /* [30] Reserved                  */\n    (int)&Reserved31_IRQHandler,  /* [31] Reserved                  */\n};\n\n\n/* reset handler -----------------------------------------------------------*/\n__attribute__((naked)) void Reset_Handler(void);\nvoid Reset_Handler(void) {\n    extern int main(void);\n    extern int __libc_init_array(void);\n    extern unsigned __data_start;  /* start of .data in the linker script */\n    extern unsigned __data_end__;  /* end of .data in the linker script */\n    extern unsigned const __data_load; /* initialization values for .data  */\n    extern unsigned __bss_start__; /* start of .bss in the linker script */\n    extern unsigned __bss_end__;   /* end of .bss in the linker script */\n    extern void software_init_hook(void) __attribute__((weak));\n\n    SystemInit(); /* CMSIS system initialization */\n\n    /* copy the data segment initializers from flash to RAM... */\n    unsigned const *src = &__data_load;\n    unsigned *dst;\n    for (dst = &__data_start; dst < &__data_end__; ++dst, ++src) {\n        *dst = *src;\n    }\n\n    /* zero fill the .bss segment in RAM... */\n    for (dst = &__bss_start__; dst < &__bss_end__; ++dst) {\n        *dst = 0;\n    }\n\n    /* init hook provided? */\n    if (&software_init_hook != (void (*)(void))(0)) {\n        /* give control to the RTOS */\n        software_init_hook(); /* this will also call __libc_init_array */\n    }\n    else {\n        /* call all static constructors in C++ (harmless in C programs) */\n        __libc_init_array();\n        (void)main(); /* application's entry point; should never return! */\n    }\n\n    /* the previous code should not return, but assert just in case... */\n    assert_failed(\"Reset_Handler\", 1U);\n}\n\n\n/* fault exception handlers ------------------------------------------------*/\n__attribute__((naked)) void NMI_Handler(void);\nvoid NMI_Handler(void) {\n    /* reset the SP to the initial value in case of stack overflow */\n    __asm volatile (\"  MOV  sp,%0\" : : \"r\" (&__stack_end__));\n    assert_failed(\"NMI_Handler\", 1U);\n}\n/*..........................................................................*/\n__attribute__((naked)) void HardFault_Handler(void);\nvoid HardFault_Handler(void) {\n    /* reset the SP to the initial value in case of stack overflow */\n    __asm volatile (\"  MOV  sp,%0\" : : \"r\" (&__stack_end__));\n    assert_failed(\"HardFault_Handler\", 1U);\n}\n/*..........................................................................*/\n__attribute__((naked)) void Default_Handler(void);\nvoid Default_Handler(void) {\n    /* reset the SP to the initial value in case of stack overflow */\n    __asm volatile (\"  MOV  sp,%0\" : : \"r\" (&__stack_end__));\n    assert_failed(\"Default_Handler\", 1U);\n}\n"
  },
  {
    "path": "3rd_party/nucleo-c031c6/iar/startup_stm32c031xx.s",
    "content": ";/***************************************************************************/\n; * @file     startup_stm32c031xx.s for IAR ARM assembler\n; * @brief    CMSIS Cortex-M0+ Core Device Startup File for STM32C031xx\n; * @version  CMSIS 5.9.0\n; * @date     1 Feb 2023\n; *\n; * Modified by Quantum Leaps:\n; * - Added relocating of the Vector Table to free up the 256B region at 0x0\n; *   for NULL-pointer protection by the MPU.\n; * - Modified all exception handlers to branch to assert_failed()\n; *   instead of locking up the CPU inside an endless loop.\n; *\n; * @description\n; * Created from the CMSIS template for the specified device\n; * Quantum Leaps, www.state-machine.com\n; *\n\n        MODULE  ?cstartup\n\n        ; Forward declaration of sections.\n        SECTION CSTACK:DATA:NOROOT(3)\n\n        SECTION .intvec:CODE:NOROOT(8)\n\n        PUBLIC  __vector_table\n        PUBLIC  __Vectors\n        PUBLIC  __Vectors_End\n        PUBLIC  __Vectors_Size\n\n;******************************************************************************\n; The vector table.\n;\n        DATA\n__vector_table\n    ; Initial Vector Table before relocation\n        DCD     sfe(CSTACK)\n        DCD     Reset_Handler               ; Reset Handler\n        DCD     NMI_Handler                 ; NMI Handler\n        DCD     HardFault_Handler           ; Hard Fault Handler\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     SVC_Handler                 ; SVCall handler\n        DCD     DebugMon_Handler            ; Debug Monitor handler\n        DCD     Default_Handler             ; Reserved\n        DCD     PendSV_Handler              ; PendSV handler\n        DCD     SysTick_Handler             ; SysTick handler\n\n        ; IRQ handlers...\n        DCD     WWDG_IRQHandler             ; [ 0] Window Watchdog\n        DCD     Reserved1_IRQHandler        ; [ 1] Reserved\n        DCD     RTC_IRQHandler              ; [ 2] RTC through EXTI Line\n        DCD     FLASH_IRQHandler            ; [ 3] FLASH\n        DCD     RCC_IRQHandler              ; [ 4] RCC\n        DCD     EXTI0_1_IRQHandler          ; [ 5] EXTI Line 0 and 1\n        DCD     EXTI2_3_IRQHandler          ; [ 6] EXTI Line 2 and 3\n        DCD     EXTI4_15_IRQHandler         ; [ 7] EXTI Line 4 to 15\n        DCD     Reserved8_IRQHandler        ; [ 8] Reserved\n        DCD     DMA1_Channel1_IRQHandler    ; [ 9] DMA1 Channel 1\n        DCD     DMA1_Channel2_3_IRQHandler  ; [10] DMA1 Channel 2 and Channel 3\n        DCD     DMAMUX1_IRQHandler          ; [11] DMAMUX\n        DCD     ADC1_IRQHandler             ; [12] ADC1\n        DCD     TIM1_BRK_UP_TRG_COM_IRQHandler ; [13] TIM1 Break, Update, Trigger and Commutation\n        DCD     TIM1_CC_IRQHandler          ; [14] TIM1 Capture Compare\n        DCD     Reserved15_IRQHandler       ; [15] Reserved\n        DCD     TIM3_IRQHandler             ; [16] TIM3\n        DCD     Reserved17_IRQHandler       ; [17] Reserved\n        DCD     Reserved18_IRQHandler       ; [18] Reserved\n        DCD     TIM14_IRQHandler            ; [19] TIM14\n        DCD     Reserved20_IRQHandler       ; [20] Reserved\n        DCD     TIM16_IRQHandler            ; [21] TIM16\n        DCD     TIM17_IRQHandler            ; [22] TIM17\n        DCD     I2C1_IRQHandler             ; [23] I2C1\n        DCD     Reserved24_IRQHandler       ; [24] Reserved\n        DCD     SPI1_IRQHandler             ; [25] SPI1\n        DCD     Reserved26_IRQHandler       ; [26] Reserved\n        DCD     USART1_IRQHandler           ; [27] USART1\n        DCD     USART2_IRQHandler           ; [28] USART2\n        DCD     Reserved29_IRQHandler       ; [29] Reserved\n        DCD     Reserved30_IRQHandler       ; [30] Reserved\n        DCD     Reserved31_IRQHandler       ; [31] Reserved\n\n__Vectors_End\n\n__Vectors       EQU   __vector_table\n__Vectors_Size  EQU   __Vectors_End - __Vectors\n\n\n;******************************************************************************\n; This is the code for exception handlers.\n;\n        SECTION .text:CODE:REORDER:NOROOT(2)\n\n;******************************************************************************\n; This is the code that gets called when theessor first starts execution\n; following a reset event.\n;\n        PUBWEAK Reset_Handler\n        EXTERN  SystemInit\n        EXTERN  __iar_program_start\n        EXTERN  assert_failed\n\nReset_Handler\n        LDR     r0,=SystemInit  ; CMSIS system initialization\n        BLX     r0\n\n        ; pre-fill the CSTACK with 0xDEADBEEF...................\n        LDR     r0,=0xDEADBEEF\n        MOV     r1,r0\n        LDR     r2,=sfb(CSTACK)\n        LDR     r3,=sfe(CSTACK)\nReset_stackInit_fill:\n        STMIA   r2!,{r0,r1}\n        CMP     r2,r3\n        BLT.N   Reset_stackInit_fill\n\n        LDR     r0,=__iar_program_start ; IAR startup code\n        BLX     r0\n\n        ; __iar_program_start calls the main() function, which should not return,\n        ; but just in case jump to assert_failed() if main returns.\n        LDR     r0,=str_EXIT\n        MOVS    r1,#1\n        LDR     r2,=sfe(CSTACK)  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_EXIT\n        DCB     \"EXIT\"\n        ALIGNROM 2\n\n;******************************************************************************\n        PUBWEAK NMI_Handler\nNMI_Handler\n        LDR     r0,=str_NMI\n        MOVS    r1,#1\n        LDR     r2,=sfe(CSTACK)  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_NMI\n        DCB     \"NMI\"\n        ALIGNROM 2\n\n;******************************************************************************\n        PUBWEAK HardFault_Handler\nHardFault_Handler\n        LDR     r0,=str_HardFault\n        MOVS    r1,#1\n        LDR     r2,=sfe(CSTACK)  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_HardFault\n        DCB     \"HardFault\"\n        ALIGNROM 2\n\n\n;******************************************************************************\n;\n; Weak non-fault handlers...\n;\n\n;******************************************************************************\n        PUBWEAK SVC_Handler\nSVC_Handler\n        LDR     r0,=str_SVC\n        MOVS    r1,#1\n        LDR     r2,=sfe(CSTACK)  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_SVC\n        DCB     \"SVC\"\n        ALIGNROM 2\n\n;******************************************************************************\n        PUBWEAK DebugMon_Handler\nDebugMon_Handler\n        LDR     r0,=str_DebugMon\n        MOVS    r1,#1\n        LDR     r2,=sfe(CSTACK)  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_DebugMon\n        DCB     \"DebugMon\"\n        ALIGNROM 2\n\n;******************************************************************************\n        PUBWEAK PendSV_Handler\nPendSV_Handler\n        LDR     r0,=str_PendSV\n        MOVS    r1,#1\n        LDR     r2,=sfe(CSTACK)  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_PendSV\n        DCB     \"PendSV\"\n        ALIGNROM 2\n\n;******************************************************************************\n        PUBWEAK SysTick_Handler\nSysTick_Handler\n        LDR     r0,=str_SysTick\n        MOVS    r1,#1\n        LDR     r2,=sfe(CSTACK)  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_SysTick\n        DCB     \"SysTick\"\n        ALIGNROM 2\n\n;******************************************************************************\n; Weak IRQ handlers...\n;\n        PUBWEAK  Default_Handler\n        PUBWEAK  WWDG_IRQHandler\n        PUBWEAK  RTC_IRQHandler\n        PUBWEAK  FLASH_IRQHandler\n        PUBWEAK  RCC_IRQHandler\n        PUBWEAK  EXTI0_1_IRQHandler\n        PUBWEAK  EXTI2_3_IRQHandler\n        PUBWEAK  EXTI4_15_IRQHandler\n        PUBWEAK  DMA1_Channel1_IRQHandler\n        PUBWEAK  DMA1_Channel2_3_IRQHandler\n        PUBWEAK  DMAMUX1_IRQHandler\n        PUBWEAK  ADC1_IRQHandler\n        PUBWEAK  TIM1_BRK_UP_TRG_COM_IRQHandler\n        PUBWEAK  TIM1_CC_IRQHandler\n        PUBWEAK  TIM3_IRQHandler\n        PUBWEAK  TIM14_IRQHandler\n        PUBWEAK  TIM16_IRQHandler\n        PUBWEAK  TIM17_IRQHandler\n        PUBWEAK  I2C1_IRQHandler\n        PUBWEAK  SPI1_IRQHandler\n        PUBWEAK  USART1_IRQHandler\n        PUBWEAK  USART2_IRQHandler\n        PUBWEAK  Reserved1_IRQHandler\n        PUBWEAK  Reserved8_IRQHandler\n        PUBWEAK  Reserved15_IRQHandler\n        PUBWEAK  Reserved17_IRQHandler\n        PUBWEAK  Reserved18_IRQHandler\n        PUBWEAK  Reserved20_IRQHandler\n        PUBWEAK  Reserved24_IRQHandler\n        PUBWEAK  Reserved26_IRQHandler\n        PUBWEAK  Reserved29_IRQHandler\n        PUBWEAK  Reserved30_IRQHandler\n        PUBWEAK  Reserved31_IRQHandler\n\nDefault_Handler\nWWDG_IRQHandler\nRTC_IRQHandler\nFLASH_IRQHandler\nRCC_IRQHandler\nEXTI0_1_IRQHandler\nEXTI2_3_IRQHandler\nEXTI4_15_IRQHandler\nDMA1_Channel1_IRQHandler\nDMA1_Channel2_3_IRQHandler\nDMAMUX1_IRQHandler\nADC1_IRQHandler\nTIM1_BRK_UP_TRG_COM_IRQHandler\nTIM1_CC_IRQHandler\nTIM3_IRQHandler\nTIM14_IRQHandler\nTIM16_IRQHandler\nTIM17_IRQHandler\nI2C1_IRQHandler\nSPI1_IRQHandler\nUSART1_IRQHandler\nUSART2_IRQHandler\nReserved1_IRQHandler\nReserved8_IRQHandler\nReserved15_IRQHandler\nReserved17_IRQHandler\nReserved18_IRQHandler\nReserved20_IRQHandler\nReserved24_IRQHandler\nReserved26_IRQHandler\nReserved29_IRQHandler\nReserved30_IRQHandler\nReserved31_IRQHandler\n        LDR     r0,=str_Undefined\n        MOVS    r1,#1\n        LDR     r2,=sfe(CSTACK)  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_Undefined\n        DCB     \"Undefined\"\n        ALIGNROM 2\n\n        END                     ; end of module\n\n"
  },
  {
    "path": "3rd_party/nucleo-c031c6/stm32c031xx.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32c031xx.h\n  * @author  MCD Application Team\n  * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.\n  *          This file contains all the peripheral register's definitions, bits\n  *          definitions and memory mapping for stm32c031xx devices.\n  *\n  *          This file contains:\n  *           - Data structures and the address mapping for all peripherals\n  *           - Peripheral's registers declarations and bits definition\n  *           - Macros to access peripheral's registers hardware\n  *\n  ******************************************************************************\n  * @attention\n  *\n  * Copyright (c) 2022 STMicroelectronics.\n  * All rights reserved.\n  *\n  * This software is licensed under terms that can be found in the LICENSE file\n  * in the root directory of this software component.\n  * If no LICENSE file comes with this software, it is provided AS-IS.\n  *\n  ******************************************************************************\n  */\n\n/** @addtogroup CMSIS_Device\n  * @{\n  */\n\n/** @addtogroup stm32c031xx\n  * @{\n  */\n\n#ifndef STM32C031xx_H\n#define STM32C031xx_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif /* __cplusplus */\n\n/** @addtogroup Configuration_section_for_CMSIS\n  * @{\n  */\n\n/**\n  * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals\n   */\n#define __CM0PLUS_REV             0 /*!< Core Revision r0p0                            */\n#define __MPU_PRESENT             1 /*!< STM32C0xx  provides an MPU                    */\n#define __VTOR_PRESENT            1 /*!< Vector  Table  Register supported             */\n#define __NVIC_PRIO_BITS          2 /*!< STM32C0xx uses 2 Bits for the Priority Levels */\n#define __Vendor_SysTickConfig    0 /*!< Set to 1 if different SysTick Config is used  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup Peripheral_interrupt_number_definition\n  * @{\n  */\n\n/**\n * @brief stm32c031xx Interrupt Number Definition, according to the selected device\n *        in @ref Library_configuration_section\n */\n\n/*!< Interrupt Number Definition */\ntypedef enum\n{\n/******  Cortex-M0+ Processor Exceptions Numbers ***************************************************************/\n  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */\n  HardFault_IRQn              = -13,    /*!< 3 Cortex-M Hard Fault Interrupt                                   */\n  SVC_IRQn                    = -5,     /*!< 11 Cortex-M SV Call Interrupt                                     */\n  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M Pend SV Interrupt                                     */\n  SysTick_IRQn                = -1,     /*!< 15 Cortex-M System Tick Interrupt                                 */\n/******  STM32C0xxxx specific Interrupt Numbers ****************************************************************/\n  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */\n  RTC_IRQn                    = 2,      /*!< RTC interrupt through the EXTI line 19 & 21                       */\n  FLASH_IRQn                  = 3,      /*!< FLASH global Interrupt                                            */\n  RCC_IRQn                    = 4,      /*!< RCC global Interrupt                                              */\n  EXTI0_1_IRQn                = 5,      /*!< EXTI 0 and 1 Interrupts                                           */\n  EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupts                                      */\n  EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupts                                      */\n  DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                          */\n  DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupts                           */\n  DMAMUX1_IRQn                = 11,     /*!< DMAMUX Interrupts                                                 */\n  ADC1_IRQn                   = 12,     /*!< ADC1 Interrupts                                                   */\n  TIM1_BRK_UP_TRG_COM_IRQn    = 13,     /*!< TIM1 Break, Update, Trigger and Commutation Interrupts            */\n  TIM1_CC_IRQn                = 14,     /*!< TIM1 Capture Compare Interrupt                                    */\n  TIM3_IRQn                   = 16,     /*!< TIM3 global Interrupt                                             */\n  TIM14_IRQn                  = 19,     /*!< TIM14 global Interrupt                                            */\n  TIM16_IRQn                  = 21,     /*!< TIM16 global Interrupt                                            */\n  TIM17_IRQn                  = 22,     /*!< TIM17 global Interrupt                                            */\n  I2C1_IRQn                   = 23,     /*!< I2C1 Interrupt  (combined with EXTI 23)                           */\n  SPI1_IRQn                   = 25,     /*!< SPI1 Interrupt                                                    */\n  USART1_IRQn                 = 27,     /*!< USART1 Interrupt                                                  */\n  USART2_IRQn                 = 28,     /*!< USART2 Interrupt                                                  */\n} IRQn_Type;\n\n/**\n  * @}\n  */\n\n#include \"core_cm0plus.h\"               /* Cortex-M0+ processor and core peripherals */\n#include \"system_stm32c0xx.h\"\n#include <stdint.h>\n\n/** @addtogroup Peripheral_registers_structures\n  * @{\n  */\n\n/**\n  * @brief Analog to Digital Converter\n  */\ntypedef struct\n{\n  __IO uint32_t ISR;          /*!< ADC interrupt and status register,             Address offset: 0x00 */\n  __IO uint32_t IER;          /*!< ADC interrupt enable register,                 Address offset: 0x04 */\n  __IO uint32_t CR;           /*!< ADC control register,                          Address offset: 0x08 */\n  __IO uint32_t CFGR1;        /*!< ADC configuration register 1,                  Address offset: 0x0C */\n  __IO uint32_t CFGR2;        /*!< ADC configuration register 2,                  Address offset: 0x10 */\n  __IO uint32_t SMPR;         /*!< ADC sampling time register,                    Address offset: 0x14 */\n       uint32_t RESERVED1;    /*!< Reserved,                                                      0x18 */\n       uint32_t RESERVED2;    /*!< Reserved,                                                      0x1C */\n  __IO uint32_t TR1;          /*!< ADC analog watchdog 1 threshold register,      Address offset: 0x20 */\n  __IO uint32_t TR2;          /*!< ADC analog watchdog 2 threshold register,      Address offset: 0x24 */\n  __IO uint32_t CHSELR;       /*!< ADC group regular sequencer register,          Address offset: 0x28 */\n  __IO uint32_t TR3;          /*!< ADC analog watchdog 3 threshold register,      Address offset: 0x2C */\n       uint32_t RESERVED3[4]; /*!< Reserved,                                               0x30 - 0x3C */\n  __IO uint32_t DR;           /*!< ADC group regular data register,               Address offset: 0x40 */\n       uint32_t RESERVED4[23];/*!< Reserved,                                               0x44 - 0x9C */\n  __IO uint32_t AWD2CR;       /*!< ADC analog watchdog 2 configuration register,  Address offset: 0xA0 */\n  __IO uint32_t AWD3CR;       /*!< ADC analog watchdog 3 configuration register,  Address offset: 0xA4 */\n       uint32_t RESERVED5[3]; /*!< Reserved,                                               0xA8 - 0xB0 */\n  __IO uint32_t CALFACT;      /*!< ADC Calibration factor register,               Address offset: 0xB4 */\n} ADC_TypeDef;\n\ntypedef struct\n{\n  __IO uint32_t CCR;          /*!< ADC common configuration register,             Address offset: ADC1 base address + 0x308 */\n} ADC_Common_TypeDef;\n\n\n/**\n  * @brief CRC calculation unit\n  */\ntypedef struct\n{\n  __IO uint32_t DR;             /*!< CRC Data register,                         Address offset: 0x00 */\n  __IO uint32_t IDR;            /*!< CRC Independent data register,             Address offset: 0x04 */\n  __IO uint32_t CR;             /*!< CRC Control register,                      Address offset: 0x08 */\n       uint32_t RESERVED1;      /*!< Reserved,                                                  0x0C */\n  __IO uint32_t INIT;           /*!< Initial CRC value register,                Address offset: 0x10 */\n  __IO uint32_t POL;            /*!< CRC polynomial register,                   Address offset: 0x14 */\n} CRC_TypeDef;\n\n\n/**\n  * @brief Debug MCU\n  */\ntypedef struct\n{\n  __IO uint32_t IDCODE;      /*!< MCU device ID code,              Address offset: 0x00 */\n  __IO uint32_t CR;          /*!< Debug configuration register,    Address offset: 0x04 */\n  __IO uint32_t APBFZ1;      /*!< Debug APB freeze register 1,     Address offset: 0x08 */\n  __IO uint32_t APBFZ2;      /*!< Debug APB freeze register 2,     Address offset: 0x0C */\n} DBG_TypeDef;\n\n/**\n  * @brief DMA Controller\n  */\ntypedef struct\n{\n  __IO uint32_t CCR;         /*!< DMA channel x configuration register        */\n  __IO uint32_t CNDTR;       /*!< DMA channel x number of data register       */\n  __IO uint32_t CPAR;        /*!< DMA channel x peripheral address register   */\n  __IO uint32_t CMAR;        /*!< DMA channel x memory address register       */\n} DMA_Channel_TypeDef;\n\ntypedef struct\n{\n  __IO uint32_t ISR;         /*!< DMA interrupt status register,                 Address offset: 0x00 */\n  __IO uint32_t IFCR;        /*!< DMA interrupt flag clear register,             Address offset: 0x04 */\n} DMA_TypeDef;\n\n/**\n  * @brief DMA Multiplexer\n  */\ntypedef struct\n{\n  __IO uint32_t   CCR;       /*!< DMA Multiplexer Channel x Control Register    Address offset: 0x0004 * (channel x) */\n}DMAMUX_Channel_TypeDef;\n\ntypedef struct\n{\n  __IO uint32_t   CSR;       /*!< DMA Channel Status Register                    Address offset: 0x0080   */\n  __IO uint32_t   CFR;       /*!< DMA Channel Clear Flag Register                Address offset: 0x0084   */\n}DMAMUX_ChannelStatus_TypeDef;\n\ntypedef struct\n{\n  __IO uint32_t   RGCR;        /*!< DMA Request Generator x Control Register     Address offset: 0x0100 + 0x0004 * (Req Gen x) */\n}DMAMUX_RequestGen_TypeDef;\n\ntypedef struct\n{\n  __IO uint32_t   RGSR;        /*!< DMA Request Generator Status Register        Address offset: 0x0140   */\n  __IO uint32_t   RGCFR;       /*!< DMA Request Generator Clear Flag Register    Address offset: 0x0144   */\n}DMAMUX_RequestGenStatus_TypeDef;\n\n/**\n  * @brief Asynch Interrupt/Event Controller (EXTI)\n  */\ntypedef struct\n{\n  __IO uint32_t RTSR1;          /*!< EXTI Rising Trigger Selection Register 1,        Address offset:   0x00 */\n  __IO uint32_t FTSR1;          /*!< EXTI Falling Trigger Selection Register 1,       Address offset:   0x04 */\n  __IO uint32_t SWIER1;         /*!< EXTI Software Interrupt event Register 1,        Address offset:   0x08 */\n  __IO uint32_t RPR1;           /*!< EXTI Rising Pending Register 1,                  Address offset:   0x0C */\n  __IO uint32_t FPR1;           /*!< EXTI Falling Pending Register 1,                 Address offset:   0x10 */\n       uint32_t RESERVED1[3];   /*!< Reserved 1,                                                0x14 -- 0x1C */\n       uint32_t RESERVED2[5];   /*!< Reserved 2,                                                0x20 -- 0x30 */\n       uint32_t RESERVED3[11];  /*!< Reserved 3,                                                0x34 -- 0x5C */\n  __IO uint32_t EXTICR[4];      /*!< EXTI External Interrupt Configuration Register,            0x60 -- 0x6C */\n       uint32_t RESERVED4[4];   /*!< Reserved 4,                                                0x70 -- 0x7C */\n  __IO uint32_t IMR1;           /*!< EXTI Interrupt Mask Register 1,                  Address offset:   0x80 */\n  __IO uint32_t EMR1;           /*!< EXTI Event Mask Register 1,                      Address offset:   0x84 */\n} EXTI_TypeDef;\n\n/**\n  * @brief FLASH Registers\n  */\ntypedef struct\n{\n  __IO uint32_t ACR;          /*!< FLASH Access Control register,                     Address offset: 0x00 */\n       uint32_t RESERVED1;    /*!< Reserved1,                                         Address offset: 0x04 */\n  __IO uint32_t KEYR;         /*!< FLASH Key register,                                Address offset: 0x08 */\n  __IO uint32_t OPTKEYR;      /*!< FLASH Option Key register,                         Address offset: 0x0C */\n  __IO uint32_t SR;           /*!< FLASH Status register,                             Address offset: 0x10 */\n  __IO uint32_t CR;           /*!< FLASH Control register,                            Address offset: 0x14 */\n  __IO uint32_t ECCR;         /*!< FLASH ECC register,                                Address offset: 0x18 */\n       uint32_t RESERVED2;    /*!< Reserved2,                                         Address offset: 0x1C */\n  __IO uint32_t OPTR;         /*!< FLASH Option register,                             Address offset: 0x20 */\n  __IO uint32_t PCROP1ASR;    /*!< FLASH Bank PCROP area A Start address register,    Address offset: 0x24 */\n  __IO uint32_t PCROP1AER;    /*!< FLASH Bank PCROP area A End address register,      Address offset: 0x28 */\n  __IO uint32_t WRP1AR;       /*!< FLASH Bank WRP area A address register,            Address offset: 0x2C */\n  __IO uint32_t WRP1BR;       /*!< FLASH Bank WRP area B address register,            Address offset: 0x30 */\n  __IO uint32_t PCROP1BSR;    /*!< FLASH Bank PCROP area B Start address register,    Address offset: 0x34 */\n  __IO uint32_t PCROP1BER;    /*!< FLASH Bank PCROP area B End address register,      Address offset: 0x38 */\n       uint32_t RESERVED3[17];/*!< Reserved3,                                         Address offset: 0x3C */\n  __IO uint32_t SECR;         /*!< FLASH security register ,                          Address offset: 0x80 */\n} FLASH_TypeDef;\n\n/**\n  * @brief General Purpose I/O\n  */\ntypedef struct\n{\n  __IO uint32_t MODER;       /*!< GPIO port mode register,               Address offset: 0x00      */\n  __IO uint32_t OTYPER;      /*!< GPIO port output type register,        Address offset: 0x04      */\n  __IO uint32_t OSPEEDR;     /*!< GPIO port output speed register,       Address offset: 0x08      */\n  __IO uint32_t PUPDR;       /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */\n  __IO uint32_t IDR;         /*!< GPIO port input data register,         Address offset: 0x10      */\n  __IO uint32_t ODR;         /*!< GPIO port output data register,        Address offset: 0x14      */\n  __IO uint32_t BSRR;        /*!< GPIO port bit set/reset  register,     Address offset: 0x18      */\n  __IO uint32_t LCKR;        /*!< GPIO port configuration lock register, Address offset: 0x1C      */\n  __IO uint32_t AFR[2];      /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */\n  __IO uint32_t BRR;         /*!< GPIO Bit Reset register,               Address offset: 0x28      */\n} GPIO_TypeDef;\n\n\n/**\n  * @brief Inter-integrated Circuit Interface\n  */\ntypedef struct\n{\n  __IO uint32_t CR1;         /*!< I2C Control register 1,            Address offset: 0x00 */\n  __IO uint32_t CR2;         /*!< I2C Control register 2,            Address offset: 0x04 */\n  __IO uint32_t OAR1;        /*!< I2C Own address 1 register,        Address offset: 0x08 */\n  __IO uint32_t OAR2;        /*!< I2C Own address 2 register,        Address offset: 0x0C */\n  __IO uint32_t TIMINGR;     /*!< I2C Timing register,               Address offset: 0x10 */\n  __IO uint32_t TIMEOUTR;    /*!< I2C Timeout register,              Address offset: 0x14 */\n  __IO uint32_t ISR;         /*!< I2C Interrupt and status register, Address offset: 0x18 */\n  __IO uint32_t ICR;         /*!< I2C Interrupt clear register,      Address offset: 0x1C */\n  __IO uint32_t PECR;        /*!< I2C PEC register,                  Address offset: 0x20 */\n  __IO uint32_t RXDR;        /*!< I2C Receive data register,         Address offset: 0x24 */\n  __IO uint32_t TXDR;        /*!< I2C Transmit data register,        Address offset: 0x28 */\n} I2C_TypeDef;\n\n/**\n  * @brief Independent WATCHDOG\n  */\ntypedef struct\n{\n  __IO uint32_t KR;          /*!< IWDG Key register,       Address offset: 0x00 */\n  __IO uint32_t PR;          /*!< IWDG Prescaler register, Address offset: 0x04 */\n  __IO uint32_t RLR;         /*!< IWDG Reload register,    Address offset: 0x08 */\n  __IO uint32_t SR;          /*!< IWDG Status register,    Address offset: 0x0C */\n  __IO uint32_t WINR;        /*!< IWDG Window register,    Address offset: 0x10 */\n} IWDG_TypeDef;\n\n\n/**\n  * @brief Power Control\n  */\ntypedef struct\n{\n  __IO uint32_t CR1;            /*!< PWR Power Control Register 1,                     Address offset: 0x00 */\n       uint32_t RESERVED1;      /*!< Reserved,                                         Address offset: 0x04 */\n  __IO uint32_t CR3;            /*!< PWR Power Control Register 3,                     Address offset: 0x08 */\n  __IO uint32_t CR4;            /*!< PWR Power Control Register 4,                     Address offset: 0x0C */\n  __IO uint32_t SR1;            /*!< PWR Power Status Register 1,                      Address offset: 0x10 */\n  __IO uint32_t SR2;            /*!< PWR Power Status Register 2,                      Address offset: 0x14 */\n  __IO uint32_t SCR;            /*!< PWR Power Status Clear Register,                  Address offset: 0x18 */\n       uint32_t RESERVED2;      /*!< Reserved,                                         Address offset: 0x1C */\n  __IO uint32_t PUCRA;          /*!< PWR Pull-Up Control Register of port A,           Address offset: 0x20 */\n  __IO uint32_t PDCRA;          /*!< PWR Pull-Down Control Register of port A,         Address offset: 0x24 */\n  __IO uint32_t PUCRB;          /*!< PWR Pull-Up Control Register of port B,           Address offset: 0x28 */\n  __IO uint32_t PDCRB;          /*!< PWR Pull-Down Control Register of port B,         Address offset: 0x2C */\n  __IO uint32_t PUCRC;          /*!< PWR Pull-Up Control Register of port C,           Address offset: 0x30 */\n  __IO uint32_t PDCRC;          /*!< PWR Pull-Down Control Register of port C,         Address offset: 0x34 */\n  __IO uint32_t PUCRD;          /*!< PWR Pull-Up Control Register of port D,           Address offset: 0x38 */\n  __IO uint32_t PDCRD;          /*!< PWR Pull-Down Control Register of port D,         Address offset: 0x3C */\n       uint32_t RESERVED5;      /*!< Reserved,                                         Address offset: 0x40 */\n       uint32_t RESERVED6;      /*!< Reserved,                                         Address offset: 0x44 */\n  __IO uint32_t PUCRF;          /*!< PWR Pull-Up Control Register of port F,           Address offset: 0x48 */\n  __IO uint32_t PDCRF;          /*!< PWR Pull-Down Control Register of port F,         Address offset: 0x4C */\n       uint32_t RESERVED7[8];   /*!< Reserved,                                         Address offset: 0x50 */\n  __IO uint32_t BKPREG1;        /*!< Backup register 1,                                Address offset: 0x70 */\n  __IO uint32_t BKPREG2;        /*!< Backup register 2,                                Address offset: 0x74 */\n  __IO uint32_t BKPREG3;        /*!< Backup register 3,                                Address offset: 0x78 */\n  __IO uint32_t BKPREG4;        /*!< Backup register 4,                                Address offset: 0x7C */\n} PWR_TypeDef;\n\n/**\n  * @brief Reset and Clock Control\n  */\ntypedef struct\n{\n  __IO uint32_t CR;             /*!< RCC Clock Sources Control Register,                                     Address offset: 0x00 */\n  __IO uint32_t ICSCR;          /*!< RCC Internal Clock Sources Calibration Register,                        Address offset: 0x04 */\n  __IO uint32_t CFGR;           /*!< RCC Regulated Domain Clocks Configuration Register,                     Address offset: 0x08 */\n       uint32_t RESERVED0[3];   /*!< Reserved,                                                               Address offset: 0x0C -- 0x14 */\n  __IO uint32_t CIER;           /*!< RCC Clock Interrupt Enable Register,                                    Address offset: 0x18 */\n  __IO uint32_t CIFR;           /*!< RCC Clock Interrupt Flag Register,                                      Address offset: 0x1C */\n  __IO uint32_t CICR;           /*!< RCC Clock Interrupt Clear Register,                                     Address offset: 0x20 */\n  __IO uint32_t IOPRSTR;        /*!< RCC IO port reset register,                                             Address offset: 0x24 */\n  __IO uint32_t AHBRSTR;        /*!< RCC AHB peripherals reset register,                                     Address offset: 0x28 */\n  __IO uint32_t APBRSTR1;       /*!< RCC APB peripherals reset register 1,                                   Address offset: 0x2C */\n  __IO uint32_t APBRSTR2;       /*!< RCC APB peripherals reset register 2,                                   Address offset: 0x30 */\n  __IO uint32_t IOPENR;         /*!< RCC IO port enable register,                                            Address offset: 0x34 */\n  __IO uint32_t AHBENR;         /*!< RCC AHB peripherals clock enable register,                              Address offset: 0x38 */\n  __IO uint32_t APBENR1;        /*!< RCC APB peripherals clock enable register1,                             Address offset: 0x3C */\n  __IO uint32_t APBENR2;        /*!< RCC APB peripherals clock enable register2,                             Address offset: 0x40 */\n  __IO uint32_t IOPSMENR;       /*!< RCC IO port clocks enable in sleep mode register,                       Address offset: 0x44 */\n  __IO uint32_t AHBSMENR;       /*!< RCC AHB peripheral clocks enable in sleep mode register,                Address offset: 0x48 */\n  __IO uint32_t APBSMENR1;      /*!< RCC APB peripheral clocks enable in sleep mode register1,               Address offset: 0x4C */\n  __IO uint32_t APBSMENR2;      /*!< RCC APB peripheral clocks enable in sleep mode register2,               Address offset: 0x50 */\n  __IO uint32_t CCIPR;          /*!< RCC Peripherals Independent Clocks Configuration Register,              Address offset: 0x54 */\n  __IO uint32_t RESERVED2;      /*!< Reserved,                                                               Address offset: 0x58 */\n  __IO uint32_t CSR1;           /*!< RCC Control and status Register 1,                                      Address offset: 0x5C */\n  __IO uint32_t CSR2;           /*!< RCC Control and status Register 2,                                      Address offset: 0x60 */\n} RCC_TypeDef;\n\n/**\n  * @brief Real-Time Clock\n  */\ntypedef struct\n{\n  __IO uint32_t TR;          /*!< RTC time register,                                         Address offset: 0x00 */\n  __IO uint32_t DR;          /*!< RTC date register,                                         Address offset: 0x04 */\n  __IO uint32_t SSR;         /*!< RTC sub second register,                                   Address offset: 0x08 */\n  __IO uint32_t ICSR;        /*!< RTC initialization control and status register,            Address offset: 0x0C */\n  __IO uint32_t PRER;        /*!< RTC prescaler register,                                    Address offset: 0x10 */\n       uint32_t RESERVED0;   /*!< Reserved                                                   Address offset: 0x14 */\n  __IO uint32_t CR;          /*!< RTC control register,                                      Address offset: 0x18 */\n       uint32_t RESERVED1;   /*!< Reserved                                                   Address offset: 0x1C */\n       uint32_t RESERVED2;   /*!< Reserved                                                   Address offset: 0x20 */\n  __IO uint32_t WPR;         /*!< RTC write protection register,                             Address offset: 0x24 */\n  __IO uint32_t CALR;        /*!< RTC calibration register,                                  Address offset: 0x28 */\n  __IO uint32_t SHIFTR;      /*!< RTC shift control register,                                Address offset: 0x2C */\n  __IO uint32_t TSTR;        /*!< RTC time stamp time register,                              Address offset: 0x30 */\n  __IO uint32_t TSDR;        /*!< RTC time stamp date register,                              Address offset: 0x34 */\n  __IO uint32_t TSSSR;       /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */\n       uint32_t RESERVED3;   /*!< Reserved                                                   Address offset: 0x1C */\n  __IO uint32_t ALRMAR;      /*!< RTC alarm A register,                                      Address offset: 0x40 */\n  __IO uint32_t ALRMASSR;    /*!< RTC alarm A sub second register,                           Address offset: 0x44 */\n       uint32_t RESERVED4;   /*!< Reserved                                                   Address offset: 0x48 */\n       uint32_t RESERVED5;   /*!< Reserved                                                   Address offset: 0x4C */\n  __IO uint32_t SR;          /*!< RTC Status register,                                       Address offset: 0x50 */\n  __IO uint32_t MISR;        /*!< RTC Masked Interrupt Status register,                      Address offset: 0x54 */\n       uint32_t RESERVED6;   /*!< Reserved                                                   Address offset: 0x58 */\n  __IO uint32_t SCR;         /*!< RTC Status Clear register,                                 Address offset: 0x5C */\n} RTC_TypeDef;\n\n  /**\n  * @brief Serial Peripheral Interface\n  */\ntypedef struct\n{\n  __IO uint32_t CR1;      /*!< SPI Control register 1 (not used in I2S mode),       Address offset: 0x00 */\n  __IO uint32_t CR2;      /*!< SPI Control register 2,                              Address offset: 0x04 */\n  __IO uint32_t SR;       /*!< SPI Status register,                                 Address offset: 0x08 */\n  __IO uint32_t DR;       /*!< SPI data register,                                   Address offset: 0x0C */\n  __IO uint32_t CRCPR;    /*!< SPI CRC polynomial register (not used in I2S mode),  Address offset: 0x10 */\n  __IO uint32_t RXCRCR;   /*!< SPI Rx CRC register (not used in I2S mode),          Address offset: 0x14 */\n  __IO uint32_t TXCRCR;   /*!< SPI Tx CRC register (not used in I2S mode),          Address offset: 0x18 */\n  __IO uint32_t I2SCFGR;  /*!< SPI_I2S configuration register,                      Address offset: 0x1C */\n  __IO uint32_t I2SPR;    /*!< SPI_I2S prescaler register,                          Address offset: 0x20 */\n} SPI_TypeDef;\n\n/**\n  * @brief System configuration controller\n  */\ntypedef struct\n{\n  __IO uint32_t CFGR1;          /*!< SYSCFG configuration register 1,                   Address offset: 0x00 */\n       uint32_t RESERVED0[5];   /*!< Reserved,                                                   0x04 --0x14 */\n  __IO uint32_t CFGR2;          /*!< SYSCFG configuration register 2,                   Address offset: 0x18 */\n       uint32_t RESERVED1[8];   /*!< Reserved                                                    0x1C --0x38 */\n  __IO uint32_t CFGR3;          /*!< SYSCFG configuration register 3,                   Address offset: 0x3C */\n       uint32_t RESERVED2[16];  /*!< Reserved                                                    0x40 --0x7C */  \n  __IO uint32_t IT_LINE_SR[32]; /*!< SYSCFG configuration IT_LINE register,             Address offset: 0x80 */\n} SYSCFG_TypeDef;\n\n/**\n  * @brief TIM\n  */\ntypedef struct\n{\n  __IO uint32_t CR1;         /*!< TIM control register 1,                   Address offset: 0x00 */\n  __IO uint32_t CR2;         /*!< TIM control register 2,                   Address offset: 0x04 */\n  __IO uint32_t SMCR;        /*!< TIM slave mode control register,          Address offset: 0x08 */\n  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C */\n  __IO uint32_t SR;          /*!< TIM status register,                      Address offset: 0x10 */\n  __IO uint32_t EGR;         /*!< TIM event generation register,            Address offset: 0x14 */\n  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1,      Address offset: 0x18 */\n  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2,      Address offset: 0x1C */\n  __IO uint32_t CCER;        /*!< TIM capture/compare enable register,      Address offset: 0x20 */\n  __IO uint32_t CNT;         /*!< TIM counter register,                     Address offset: 0x24 */\n  __IO uint32_t PSC;         /*!< TIM prescaler register,                   Address offset: 0x28 */\n  __IO uint32_t ARR;         /*!< TIM auto-reload register,                 Address offset: 0x2C */\n  __IO uint32_t RCR;         /*!< TIM repetition counter register,          Address offset: 0x30 */\n  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,           Address offset: 0x34 */\n  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,           Address offset: 0x38 */\n  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,           Address offset: 0x3C */\n  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,           Address offset: 0x40 */\n  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,         Address offset: 0x44 */\n  __IO uint32_t DCR;         /*!< TIM DMA control register,                 Address offset: 0x48 */\n  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,        Address offset: 0x4C */\n  __IO uint32_t OR1;         /*!< TIM option register,                      Address offset: 0x50 */\n  __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */\n  __IO uint32_t CCR5;        /*!< TIM capture/compare register5,            Address offset: 0x58 */\n  __IO uint32_t CCR6;        /*!< TIM capture/compare register6,            Address offset: 0x5C */\n  __IO uint32_t AF1;         /*!< TIM alternate function register 1,        Address offset: 0x60 */\n  __IO uint32_t AF2;         /*!< TIM alternate function register 2,        Address offset: 0x64 */\n  __IO uint32_t TISEL;       /*!< TIM Input Selection register,             Address offset: 0x68 */\n} TIM_TypeDef;\n\n/**\n  * @brief Universal Synchronous Asynchronous Receiver Transmitter\n  */\ntypedef struct\n{\n  __IO uint32_t CR1;         /*!< USART Control register 1,                 Address offset: 0x00  */\n  __IO uint32_t CR2;         /*!< USART Control register 2,                 Address offset: 0x04  */\n  __IO uint32_t CR3;         /*!< USART Control register 3,                 Address offset: 0x08  */\n  __IO uint32_t BRR;         /*!< USART Baud rate register,                 Address offset: 0x0C  */\n  __IO uint32_t GTPR;        /*!< USART Guard time and prescaler register,  Address offset: 0x10  */\n  __IO uint32_t RTOR;        /*!< USART Receiver Time Out register,         Address offset: 0x14  */\n  __IO uint32_t RQR;         /*!< USART Request register,                   Address offset: 0x18  */\n  __IO uint32_t ISR;         /*!< USART Interrupt and status register,      Address offset: 0x1C  */\n  __IO uint32_t ICR;         /*!< USART Interrupt flag Clear register,      Address offset: 0x20  */\n  __IO uint32_t RDR;         /*!< USART Receive Data register,              Address offset: 0x24  */\n  __IO uint32_t TDR;         /*!< USART Transmit Data register,             Address offset: 0x28  */\n  __IO uint32_t PRESC;       /*!< USART Prescaler register,                 Address offset: 0x2C  */\n\n} USART_TypeDef;\n\n/**\n  * @brief Window WATCHDOG\n  */\ntypedef struct\n{\n  __IO uint32_t CR;          /*!< WWDG Control register,       Address offset: 0x00 */\n  __IO uint32_t CFR;         /*!< WWDG Configuration register, Address offset: 0x04 */\n  __IO uint32_t SR;          /*!< WWDG Status register,        Address offset: 0x08 */\n} WWDG_TypeDef;\n\n\n/** @addtogroup Peripheral_memory_map\n  * @{\n  */\n#define FLASH_BASE            (0x08000000UL)  /*!< FLASH base address */\n#define SRAM_BASE             (0x20000000UL)  /*!< SRAM base address */\n#define PERIPH_BASE           (0x40000000UL)  /*!< Peripheral base address */\n#define IOPORT_BASE           (0x50000000UL)  /*!< IOPORT base address */\n\n#define SRAM_SIZE_MAX         (0x00003000UL)  /*!< maximum SRAM size (up to 12 KBytes) */\n/*!< Peripheral memory map */\n#define APBPERIPH_BASE        (PERIPH_BASE)\n#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000UL)\n\n/*!< APB peripherals */\n\n#define TIM3_BASE             (APBPERIPH_BASE + 0x00000400UL)\n#define TIM14_BASE            (APBPERIPH_BASE + 0x00002000UL)\n#define RTC_BASE              (APBPERIPH_BASE + 0x00002800UL)\n#define WWDG_BASE             (APBPERIPH_BASE + 0x00002C00UL)\n#define IWDG_BASE             (APBPERIPH_BASE + 0x00003000UL)\n#define USART2_BASE           (APBPERIPH_BASE + 0x00004400UL)\n#define I2C1_BASE             (APBPERIPH_BASE + 0x00005400UL)\n#define PWR_BASE              (APBPERIPH_BASE + 0x00007000UL)\n#define SYSCFG_BASE           (APBPERIPH_BASE + 0x00010000UL)\n#define ADC1_BASE             (APBPERIPH_BASE + 0x00012400UL)\n#define ADC1_COMMON_BASE      (APBPERIPH_BASE + 0x00012708UL)\n#define ADC_BASE              (ADC1_COMMON_BASE) /* Kept for legacy purpose */\n#define TIM1_BASE             (APBPERIPH_BASE + 0x00012C00UL)\n#define SPI1_BASE             (APBPERIPH_BASE + 0x00013000UL)\n#define USART1_BASE           (APBPERIPH_BASE + 0x00013800UL)\n#define TIM16_BASE            (APBPERIPH_BASE + 0x00014400UL)\n#define TIM17_BASE            (APBPERIPH_BASE + 0x00014800UL)\n#define DBG_BASE              (APBPERIPH_BASE + 0x00015800UL)\n\n\n/*!< AHB peripherals */\n#define DMA1_BASE             (AHBPERIPH_BASE)\n#define DMAMUX1_BASE          (AHBPERIPH_BASE + 0x00000800UL)\n#define RCC_BASE              (AHBPERIPH_BASE + 0x00001000UL)\n#define EXTI_BASE             (AHBPERIPH_BASE + 0x00001800UL)\n#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000UL)\n#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000UL)\n\n\n#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008UL)\n#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001CUL)\n#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030UL)\n\n\n#define DMAMUX1_Channel0_BASE    (DMAMUX1_BASE)\n#define DMAMUX1_Channel1_BASE    (DMAMUX1_BASE + 0x00000004UL)\n#define DMAMUX1_Channel2_BASE    (DMAMUX1_BASE + 0x00000008UL)\n\n#define DMAMUX1_RequestGenerator0_BASE  (DMAMUX1_BASE + 0x00000100UL)\n#define DMAMUX1_RequestGenerator1_BASE  (DMAMUX1_BASE + 0x00000104UL)\n#define DMAMUX1_RequestGenerator2_BASE  (DMAMUX1_BASE + 0x00000108UL)\n\n#define DMAMUX1_ChannelStatus_BASE      (DMAMUX1_BASE + 0x00000080UL)\n#define DMAMUX1_RequestGenStatus_BASE   (DMAMUX1_BASE + 0x00000140UL)\n#define DMAMUX1_IdRegisters_BASE        (DMAMUX1_BASE + 0x000003EC)\n\n/*!< IOPORT */\n#define GPIOA_BASE            (IOPORT_BASE + 0x00000000UL)\n#define GPIOB_BASE            (IOPORT_BASE + 0x00000400UL)\n#define GPIOC_BASE            (IOPORT_BASE + 0x00000800UL)\n#define GPIOD_BASE            (IOPORT_BASE + 0x00000C00UL)\n#define GPIOF_BASE            (IOPORT_BASE + 0x00001400UL)\n\n/*!< Device Electronic Signature */\n#define PACKAGE_BASE          (0x1FFF7500UL)        /*!< Package data register base address     */\n#define UID_BASE              (0x1FFF7550UL)        /*!< Unique device ID register base address */\n#define FLASHSIZE_BASE        (0x1FFF75A0UL)        /*!< Flash size data register base address  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup Peripheral_declaration\n  * @{\n  */\n#define TIM3                ((TIM_TypeDef *) TIM3_BASE)\n#define TIM14               ((TIM_TypeDef *) TIM14_BASE)\n#define RTC                 ((RTC_TypeDef *) RTC_BASE)\n#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)\n#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)\n#define USART2              ((USART_TypeDef *) USART2_BASE)\n#define I2C1                ((I2C_TypeDef *) I2C1_BASE)\n#define PWR                 ((PWR_TypeDef *) PWR_BASE)\n#define RCC                 ((RCC_TypeDef *) RCC_BASE)\n#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)\n#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)\n#define TIM1                ((TIM_TypeDef *) TIM1_BASE)\n#define SPI1                ((SPI_TypeDef *) SPI1_BASE)\n#define USART1              ((USART_TypeDef *) USART1_BASE)\n#define TIM16               ((TIM_TypeDef *) TIM16_BASE)\n#define TIM17               ((TIM_TypeDef *) TIM17_BASE)\n#define DMA1                ((DMA_TypeDef *) DMA1_BASE)\n#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)\n#define CRC                 ((CRC_TypeDef *) CRC_BASE)\n#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)\n#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)\n#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)\n#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)\n#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)\n#define ADC1                ((ADC_TypeDef *) ADC1_BASE)\n#define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)\n#define ADC                 (ADC1_COMMON) /* Kept for legacy purpose */\n\n\n#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)\n#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)\n#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)\n\n#define DMAMUX1                ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)\n#define DMAMUX1_Channel0       ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)\n#define DMAMUX1_Channel1       ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)\n#define DMAMUX1_Channel2       ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)\n\n\n#define DMAMUX1_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)\n#define DMAMUX1_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)\n#define DMAMUX1_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)\n\n#define DMAMUX1_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)\n#define DMAMUX1_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)\n#define DMAMUX1_IdRegisters        ((DMAMUX_IdRegisters_TypeDef *) DMAMUX1_IdRegisters_BASE)\n\n#define DBG              ((DBG_TypeDef *) DBG_BASE)\n\n/**\n  * @}\n  */\n\n/** @addtogroup Exported_constants\n  * @{\n  */\n\n  /** @addtogroup Peripheral_Registers_Bits_Definition\n  * @{\n  */\n\n/******************************************************************************/\n/*                         Peripheral Registers Bits Definition               */\n/******************************************************************************/\n\n/******************************************************************************/\n/*                                                                            */\n/*                      Analog to Digital Converter (ADC)                     */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for ADC_ISR register  *******************/\n#define ADC_ISR_ADRDY_Pos              (0U)\n#define ADC_ISR_ADRDY_Msk              (0x1UL << ADC_ISR_ADRDY_Pos)            /*!< 0x00000001 */\n#define ADC_ISR_ADRDY                  ADC_ISR_ADRDY_Msk                       /*!< ADC ready flag */\n#define ADC_ISR_EOSMP_Pos              (1U)\n#define ADC_ISR_EOSMP_Msk              (0x1UL << ADC_ISR_EOSMP_Pos)            /*!< 0x00000002 */\n#define ADC_ISR_EOSMP                  ADC_ISR_EOSMP_Msk                       /*!< ADC group regular end of sampling flag */\n#define ADC_ISR_EOC_Pos                (2U)\n#define ADC_ISR_EOC_Msk                (0x1UL << ADC_ISR_EOC_Pos)              /*!< 0x00000004 */\n#define ADC_ISR_EOC                    ADC_ISR_EOC_Msk                         /*!< ADC group regular end of unitary conversion flag */\n#define ADC_ISR_EOS_Pos                (3U)\n#define ADC_ISR_EOS_Msk                (0x1UL << ADC_ISR_EOS_Pos)              /*!< 0x00000008 */\n#define ADC_ISR_EOS                    ADC_ISR_EOS_Msk                         /*!< ADC group regular end of sequence conversions flag */\n#define ADC_ISR_OVR_Pos                (4U)\n#define ADC_ISR_OVR_Msk                (0x1UL << ADC_ISR_OVR_Pos)              /*!< 0x00000010 */\n#define ADC_ISR_OVR                    ADC_ISR_OVR_Msk                         /*!< ADC group regular overrun flag */\n#define ADC_ISR_AWD1_Pos               (7U)\n#define ADC_ISR_AWD1_Msk               (0x1UL << ADC_ISR_AWD1_Pos)             /*!< 0x00000080 */\n#define ADC_ISR_AWD1                   ADC_ISR_AWD1_Msk                        /*!< ADC analog watchdog 1 flag */\n#define ADC_ISR_AWD2_Pos               (8U)\n#define ADC_ISR_AWD2_Msk               (0x1UL << ADC_ISR_AWD2_Pos)             /*!< 0x00000100 */\n#define ADC_ISR_AWD2                   ADC_ISR_AWD2_Msk                        /*!< ADC analog watchdog 2 flag */\n#define ADC_ISR_AWD3_Pos               (9U)\n#define ADC_ISR_AWD3_Msk               (0x1UL << ADC_ISR_AWD3_Pos)             /*!< 0x00000200 */\n#define ADC_ISR_AWD3                   ADC_ISR_AWD3_Msk                        /*!< ADC analog watchdog 3 flag */\n#define ADC_ISR_EOCAL_Pos              (11U)\n#define ADC_ISR_EOCAL_Msk              (0x1UL << ADC_ISR_EOCAL_Pos)            /*!< 0x00000800 */\n#define ADC_ISR_EOCAL                  ADC_ISR_EOCAL_Msk                       /*!< ADC end of calibration flag */\n#define ADC_ISR_CCRDY_Pos              (13U)\n#define ADC_ISR_CCRDY_Msk              (0x1UL << ADC_ISR_CCRDY_Pos)            /*!< 0x00002000 */\n#define ADC_ISR_CCRDY                  ADC_ISR_CCRDY_Msk                       /*!< ADC channel configuration ready flag */\n\n/* Legacy defines */\n#define ADC_ISR_EOSEQ           (ADC_ISR_EOS)\n\n/********************  Bit definition for ADC_IER register  *******************/\n#define ADC_IER_ADRDYIE_Pos            (0U)\n#define ADC_IER_ADRDYIE_Msk            (0x1UL << ADC_IER_ADRDYIE_Pos)          /*!< 0x00000001 */\n#define ADC_IER_ADRDYIE                ADC_IER_ADRDYIE_Msk                     /*!< ADC ready interrupt */\n#define ADC_IER_EOSMPIE_Pos            (1U)\n#define ADC_IER_EOSMPIE_Msk            (0x1UL << ADC_IER_EOSMPIE_Pos)          /*!< 0x00000002 */\n#define ADC_IER_EOSMPIE                ADC_IER_EOSMPIE_Msk                     /*!< ADC group regular end of sampling interrupt */\n#define ADC_IER_EOCIE_Pos              (2U)\n#define ADC_IER_EOCIE_Msk              (0x1UL << ADC_IER_EOCIE_Pos)            /*!< 0x00000004 */\n#define ADC_IER_EOCIE                  ADC_IER_EOCIE_Msk                       /*!< ADC group regular end of unitary conversion interrupt */\n#define ADC_IER_EOSIE_Pos              (3U)\n#define ADC_IER_EOSIE_Msk              (0x1UL << ADC_IER_EOSIE_Pos)            /*!< 0x00000008 */\n#define ADC_IER_EOSIE                  ADC_IER_EOSIE_Msk                       /*!< ADC group regular end of sequence conversions interrupt */\n#define ADC_IER_OVRIE_Pos              (4U)\n#define ADC_IER_OVRIE_Msk              (0x1UL << ADC_IER_OVRIE_Pos)            /*!< 0x00000010 */\n#define ADC_IER_OVRIE                  ADC_IER_OVRIE_Msk                       /*!< ADC group regular overrun interrupt */\n#define ADC_IER_AWD1IE_Pos             (7U)\n#define ADC_IER_AWD1IE_Msk             (0x1UL << ADC_IER_AWD1IE_Pos)           /*!< 0x00000080 */\n#define ADC_IER_AWD1IE                 ADC_IER_AWD1IE_Msk                      /*!< ADC analog watchdog 1 interrupt */\n#define ADC_IER_AWD2IE_Pos             (8U)\n#define ADC_IER_AWD2IE_Msk             (0x1UL << ADC_IER_AWD2IE_Pos)           /*!< 0x00000100 */\n#define ADC_IER_AWD2IE                 ADC_IER_AWD2IE_Msk                      /*!< ADC analog watchdog 2 interrupt */\n#define ADC_IER_AWD3IE_Pos             (9U)\n#define ADC_IER_AWD3IE_Msk             (0x1UL << ADC_IER_AWD3IE_Pos)           /*!< 0x00000200 */\n#define ADC_IER_AWD3IE                 ADC_IER_AWD3IE_Msk                      /*!< ADC analog watchdog 3 interrupt */\n#define ADC_IER_EOCALIE_Pos            (11U)\n#define ADC_IER_EOCALIE_Msk            (0x1UL << ADC_IER_EOCALIE_Pos)          /*!< 0x00000800 */\n#define ADC_IER_EOCALIE                ADC_IER_EOCALIE_Msk                     /*!< ADC end of calibration interrupt */\n#define ADC_IER_CCRDYIE_Pos            (13U)\n#define ADC_IER_CCRDYIE_Msk            (0x1UL << ADC_IER_CCRDYIE_Pos)          /*!< 0x00002000 */\n#define ADC_IER_CCRDYIE                ADC_IER_CCRDYIE_Msk                     /*!< ADC channel configuration ready interrupt */\n\n/* Legacy defines */\n#define ADC_IER_EOSEQIE           (ADC_IER_EOSIE)\n\n/********************  Bit definition for ADC_CR register  ********************/\n#define ADC_CR_ADEN_Pos                (0U)\n#define ADC_CR_ADEN_Msk                (0x1UL << ADC_CR_ADEN_Pos)              /*!< 0x00000001 */\n#define ADC_CR_ADEN                    ADC_CR_ADEN_Msk                         /*!< ADC enable */\n#define ADC_CR_ADDIS_Pos               (1U)\n#define ADC_CR_ADDIS_Msk               (0x1UL << ADC_CR_ADDIS_Pos)             /*!< 0x00000002 */\n#define ADC_CR_ADDIS                   ADC_CR_ADDIS_Msk                        /*!< ADC disable */\n#define ADC_CR_ADSTART_Pos             (2U)\n#define ADC_CR_ADSTART_Msk             (0x1UL << ADC_CR_ADSTART_Pos)           /*!< 0x00000004 */\n#define ADC_CR_ADSTART                 ADC_CR_ADSTART_Msk                      /*!< ADC group regular conversion start */\n#define ADC_CR_ADSTP_Pos               (4U)\n#define ADC_CR_ADSTP_Msk               (0x1UL << ADC_CR_ADSTP_Pos)             /*!< 0x00000010 */\n#define ADC_CR_ADSTP                   ADC_CR_ADSTP_Msk                        /*!< ADC group regular conversion stop */\n#define ADC_CR_ADVREGEN_Pos            (28U)\n#define ADC_CR_ADVREGEN_Msk            (0x1UL << ADC_CR_ADVREGEN_Pos)          /*!< 0x10000000 */\n#define ADC_CR_ADVREGEN                ADC_CR_ADVREGEN_Msk                     /*!< ADC voltage regulator enable */\n#define ADC_CR_ADCAL_Pos               (31U)\n#define ADC_CR_ADCAL_Msk               (0x1UL << ADC_CR_ADCAL_Pos)             /*!< 0x80000000 */\n#define ADC_CR_ADCAL                   ADC_CR_ADCAL_Msk                        /*!< ADC calibration */\n\n/********************  Bit definition for ADC_CFGR1 register  *****************/\n#define ADC_CFGR1_DMAEN_Pos            (0U)\n#define ADC_CFGR1_DMAEN_Msk            (0x1UL << ADC_CFGR1_DMAEN_Pos)          /*!< 0x00000001 */\n#define ADC_CFGR1_DMAEN                ADC_CFGR1_DMAEN_Msk                     /*!< ADC DMA transfer enable */\n#define ADC_CFGR1_DMACFG_Pos           (1U)\n#define ADC_CFGR1_DMACFG_Msk           (0x1UL << ADC_CFGR1_DMACFG_Pos)         /*!< 0x00000002 */\n#define ADC_CFGR1_DMACFG               ADC_CFGR1_DMACFG_Msk                    /*!< ADC DMA transfer configuration */\n\n#define ADC_CFGR1_SCANDIR_Pos          (2U)\n#define ADC_CFGR1_SCANDIR_Msk          (0x1UL << ADC_CFGR1_SCANDIR_Pos)        /*!< 0x00000004 */\n#define ADC_CFGR1_SCANDIR              ADC_CFGR1_SCANDIR_Msk                   /*!< ADC group regular sequencer scan direction */\n\n#define ADC_CFGR1_RES_Pos              (3U)\n#define ADC_CFGR1_RES_Msk              (0x3UL << ADC_CFGR1_RES_Pos)            /*!< 0x00000018 */\n#define ADC_CFGR1_RES                  ADC_CFGR1_RES_Msk                       /*!< ADC data resolution */\n#define ADC_CFGR1_RES_0                (0x1U << ADC_CFGR1_RES_Pos)             /*!< 0x00000008 */\n#define ADC_CFGR1_RES_1                (0x2U << ADC_CFGR1_RES_Pos)             /*!< 0x00000010 */\n\n#define ADC_CFGR1_ALIGN_Pos            (5U)\n#define ADC_CFGR1_ALIGN_Msk            (0x1UL << ADC_CFGR1_ALIGN_Pos)          /*!< 0x00000020 */\n#define ADC_CFGR1_ALIGN                ADC_CFGR1_ALIGN_Msk                     /*!< ADC data alignment */\n\n#define ADC_CFGR1_EXTSEL_Pos           (6U)\n#define ADC_CFGR1_EXTSEL_Msk           (0x7UL << ADC_CFGR1_EXTSEL_Pos)         /*!< 0x000001C0 */\n#define ADC_CFGR1_EXTSEL               ADC_CFGR1_EXTSEL_Msk                    /*!< ADC group regular external trigger source */\n#define ADC_CFGR1_EXTSEL_0             (0x1UL << ADC_CFGR1_EXTSEL_Pos)         /*!< 0x00000040 */\n#define ADC_CFGR1_EXTSEL_1             (0x2UL << ADC_CFGR1_EXTSEL_Pos)         /*!< 0x00000080 */\n#define ADC_CFGR1_EXTSEL_2             (0x4UL << ADC_CFGR1_EXTSEL_Pos)         /*!< 0x00000100 */\n\n#define ADC_CFGR1_EXTEN_Pos            (10U)\n#define ADC_CFGR1_EXTEN_Msk            (0x3UL << ADC_CFGR1_EXTEN_Pos)          /*!< 0x00000C00 */\n#define ADC_CFGR1_EXTEN                ADC_CFGR1_EXTEN_Msk                     /*!< ADC group regular external trigger polarity */\n#define ADC_CFGR1_EXTEN_0              (0x1UL << ADC_CFGR1_EXTEN_Pos)          /*!< 0x00000400 */\n#define ADC_CFGR1_EXTEN_1              (0x2UL << ADC_CFGR1_EXTEN_Pos)          /*!< 0x00000800 */\n\n#define ADC_CFGR1_OVRMOD_Pos           (12U)\n#define ADC_CFGR1_OVRMOD_Msk           (0x1UL << ADC_CFGR1_OVRMOD_Pos)         /*!< 0x00001000 */\n#define ADC_CFGR1_OVRMOD               ADC_CFGR1_OVRMOD_Msk                    /*!< ADC group regular overrun configuration */\n#define ADC_CFGR1_CONT_Pos             (13U)\n#define ADC_CFGR1_CONT_Msk             (0x1UL << ADC_CFGR1_CONT_Pos)           /*!< 0x00002000 */\n#define ADC_CFGR1_CONT                 ADC_CFGR1_CONT_Msk                      /*!< ADC group regular continuous conversion mode */\n#define ADC_CFGR1_WAIT_Pos             (14U)\n#define ADC_CFGR1_WAIT_Msk             (0x1UL << ADC_CFGR1_WAIT_Pos)           /*!< 0x00004000 */\n#define ADC_CFGR1_WAIT                 ADC_CFGR1_WAIT_Msk                      /*!< ADC low power auto wait */\n#define ADC_CFGR1_AUTOFF_Pos           (15U)\n#define ADC_CFGR1_AUTOFF_Msk           (0x1UL << ADC_CFGR1_AUTOFF_Pos)         /*!< 0x00008000 */\n#define ADC_CFGR1_AUTOFF               ADC_CFGR1_AUTOFF_Msk                    /*!< ADC low power auto power off */\n#define ADC_CFGR1_DISCEN_Pos           (16U)\n#define ADC_CFGR1_DISCEN_Msk           (0x1UL << ADC_CFGR1_DISCEN_Pos)         /*!< 0x00010000 */\n#define ADC_CFGR1_DISCEN               ADC_CFGR1_DISCEN_Msk                    /*!< ADC group regular sequencer discontinuous mode */\n#define ADC_CFGR1_CHSELRMOD_Pos        (21U)\n#define ADC_CFGR1_CHSELRMOD_Msk        (0x1UL << ADC_CFGR1_CHSELRMOD_Pos)      /*!< 0x00200000 */\n#define ADC_CFGR1_CHSELRMOD            ADC_CFGR1_CHSELRMOD_Msk                 /*!< ADC group regular sequencer mode */\n\n#define ADC_CFGR1_AWD1SGL_Pos          (22U)\n#define ADC_CFGR1_AWD1SGL_Msk          (0x1UL << ADC_CFGR1_AWD1SGL_Pos)        /*!< 0x00400000 */\n#define ADC_CFGR1_AWD1SGL              ADC_CFGR1_AWD1SGL_Msk                   /*!< ADC analog watchdog 1 monitoring a single channel or all channels */\n#define ADC_CFGR1_AWD1EN_Pos           (23U)\n#define ADC_CFGR1_AWD1EN_Msk           (0x1UL << ADC_CFGR1_AWD1EN_Pos)         /*!< 0x00800000 */\n#define ADC_CFGR1_AWD1EN               ADC_CFGR1_AWD1EN_Msk                    /*!< ADC analog watchdog 1 enable on scope ADC group regular */\n\n#define ADC_CFGR1_AWD1CH_Pos           (26U)\n#define ADC_CFGR1_AWD1CH_Msk           (0x1FUL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x7C000000 */\n#define ADC_CFGR1_AWD1CH               ADC_CFGR1_AWD1CH_Msk                    /*!< ADC analog watchdog 1 monitored channel selection */\n#define ADC_CFGR1_AWD1CH_0             (0x01UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x04000000 */\n#define ADC_CFGR1_AWD1CH_1             (0x02UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x08000000 */\n#define ADC_CFGR1_AWD1CH_2             (0x04UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x10000000 */\n#define ADC_CFGR1_AWD1CH_3             (0x08UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x20000000 */\n#define ADC_CFGR1_AWD1CH_4             (0x10UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x40000000 */\n\n/* Legacy defines */\n#define ADC_CFGR1_AUTDLY          (ADC_CFGR1_WAIT)\n\n/********************  Bit definition for ADC_CFGR2 register  *****************/\n#define ADC_CFGR2_OVSE_Pos             (0U)\n#define ADC_CFGR2_OVSE_Msk             (0x1UL << ADC_CFGR2_OVSE_Pos)           /*!< 0x00000001 */\n#define ADC_CFGR2_OVSE                 ADC_CFGR2_OVSE_Msk                      /*!< ADC oversampler enable on scope ADC group regular */\n\n#define ADC_CFGR2_OVSR_Pos             (2U)\n#define ADC_CFGR2_OVSR_Msk             (0x7UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x0000001C */\n#define ADC_CFGR2_OVSR                 ADC_CFGR2_OVSR_Msk                      /*!< ADC oversampling ratio */\n#define ADC_CFGR2_OVSR_0               (0x1UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000004 */\n#define ADC_CFGR2_OVSR_1               (0x2UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000008 */\n#define ADC_CFGR2_OVSR_2               (0x4UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000010 */\n\n#define ADC_CFGR2_OVSS_Pos             (5U)\n#define ADC_CFGR2_OVSS_Msk             (0xFUL << ADC_CFGR2_OVSS_Pos)           /*!< 0x000001E0 */\n#define ADC_CFGR2_OVSS                 ADC_CFGR2_OVSS_Msk                      /*!< ADC oversampling shift */\n#define ADC_CFGR2_OVSS_0               (0x1UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000020 */\n#define ADC_CFGR2_OVSS_1               (0x2UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000040 */\n#define ADC_CFGR2_OVSS_2               (0x4UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000080 */\n#define ADC_CFGR2_OVSS_3               (0x8UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000100 */\n\n#define ADC_CFGR2_TOVS_Pos             (9U)\n#define ADC_CFGR2_TOVS_Msk             (0x1UL << ADC_CFGR2_TOVS_Pos)           /*!< 0x00000200 */\n#define ADC_CFGR2_TOVS                 ADC_CFGR2_TOVS_Msk                      /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */\n\n#define ADC_CFGR2_LFTRIG_Pos           (29U)\n#define ADC_CFGR2_LFTRIG_Msk           (0x1UL << ADC_CFGR2_LFTRIG_Pos)         /*!< 0x20000000 */\n#define ADC_CFGR2_LFTRIG               ADC_CFGR2_LFTRIG_Msk                    /*!< ADC low frequency trigger mode */\n\n#define ADC_CFGR2_CKMODE_Pos           (30U)\n#define ADC_CFGR2_CKMODE_Msk           (0x3UL << ADC_CFGR2_CKMODE_Pos)         /*!< 0xC0000000 */\n#define ADC_CFGR2_CKMODE               ADC_CFGR2_CKMODE_Msk                    /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */\n#define ADC_CFGR2_CKMODE_1             (0x2UL << ADC_CFGR2_CKMODE_Pos)         /*!< 0x80000000 */\n#define ADC_CFGR2_CKMODE_0             (0x1UL << ADC_CFGR2_CKMODE_Pos)         /*!< 0x40000000 */\n\n/********************  Bit definition for ADC_SMPR register  ******************/\n#define ADC_SMPR_SMP1_Pos              (0U)\n#define ADC_SMPR_SMP1_Msk              (0x7UL << ADC_SMPR_SMP1_Pos)            /*!< 0x00000007 */\n#define ADC_SMPR_SMP1                  ADC_SMPR_SMP1_Msk                       /*!< ADC group of channels sampling time 1 */\n#define ADC_SMPR_SMP1_0                (0x1UL << ADC_SMPR_SMP1_Pos)            /*!< 0x00000001 */\n#define ADC_SMPR_SMP1_1                (0x2UL << ADC_SMPR_SMP1_Pos)            /*!< 0x00000002 */\n#define ADC_SMPR_SMP1_2                (0x4UL << ADC_SMPR_SMP1_Pos)            /*!< 0x00000004 */\n\n#define ADC_SMPR_SMP2_Pos              (4U)\n#define ADC_SMPR_SMP2_Msk              (0x7UL << ADC_SMPR_SMP2_Pos)            /*!< 0x00000070 */\n#define ADC_SMPR_SMP2                  ADC_SMPR_SMP2_Msk                       /*!< ADC group of channels sampling time 2 */\n#define ADC_SMPR_SMP2_0                (0x1UL << ADC_SMPR_SMP2_Pos)            /*!< 0x00000010 */\n#define ADC_SMPR_SMP2_1                (0x2UL << ADC_SMPR_SMP2_Pos)            /*!< 0x00000020 */\n#define ADC_SMPR_SMP2_2                (0x4UL << ADC_SMPR_SMP2_Pos)            /*!< 0x00000040 */\n\n#define ADC_SMPR_SMPSEL_Pos            (8U)\n#define ADC_SMPR_SMPSEL_Msk            (0x7FFFFUL << ADC_SMPR_SMPSEL_Pos)      /*!< 0x07FFFF00 */\n#define ADC_SMPR_SMPSEL                ADC_SMPR_SMPSEL_Msk                     /*!< ADC all channels sampling time selection */\n#define ADC_SMPR_SMPSEL0_Pos           (8U)\n#define ADC_SMPR_SMPSEL0_Msk           (0x1UL << ADC_SMPR_SMPSEL0_Pos)         /*!< 0x00000100 */\n#define ADC_SMPR_SMPSEL0               ADC_SMPR_SMPSEL0_Msk                    /*!< ADC channel 0 sampling time selection */\n#define ADC_SMPR_SMPSEL1_Pos           (9U)\n#define ADC_SMPR_SMPSEL1_Msk           (0x1UL << ADC_SMPR_SMPSEL1_Pos)         /*!< 0x00000200 */\n#define ADC_SMPR_SMPSEL1               ADC_SMPR_SMPSEL1_Msk                    /*!< ADC channel 1 sampling time selection */\n#define ADC_SMPR_SMPSEL2_Pos           (10U)\n#define ADC_SMPR_SMPSEL2_Msk           (0x1UL << ADC_SMPR_SMPSEL2_Pos)         /*!< 0x00000400 */\n#define ADC_SMPR_SMPSEL2               ADC_SMPR_SMPSEL2_Msk                    /*!< ADC channel 2 sampling time selection */\n#define ADC_SMPR_SMPSEL3_Pos           (11U)\n#define ADC_SMPR_SMPSEL3_Msk           (0x1UL << ADC_SMPR_SMPSEL3_Pos)         /*!< 0x00000800 */\n#define ADC_SMPR_SMPSEL3               ADC_SMPR_SMPSEL3_Msk                    /*!< ADC channel 3 sampling time selection */\n#define ADC_SMPR_SMPSEL4_Pos           (12U)\n#define ADC_SMPR_SMPSEL4_Msk           (0x1UL << ADC_SMPR_SMPSEL4_Pos)         /*!< 0x00001000 */\n#define ADC_SMPR_SMPSEL4               ADC_SMPR_SMPSEL4_Msk                    /*!< ADC channel 4 sampling time selection */\n#define ADC_SMPR_SMPSEL5_Pos           (13U)\n#define ADC_SMPR_SMPSEL5_Msk           (0x1UL << ADC_SMPR_SMPSEL5_Pos)         /*!< 0x00002000 */\n#define ADC_SMPR_SMPSEL5               ADC_SMPR_SMPSEL5_Msk                    /*!< ADC channel 5 sampling time selection */\n#define ADC_SMPR_SMPSEL6_Pos           (14U)\n#define ADC_SMPR_SMPSEL6_Msk           (0x1UL << ADC_SMPR_SMPSEL6_Pos)         /*!< 0x00004000 */\n#define ADC_SMPR_SMPSEL6               ADC_SMPR_SMPSEL6_Msk                    /*!< ADC channel 6 sampling time selection */\n#define ADC_SMPR_SMPSEL7_Pos           (15U)\n#define ADC_SMPR_SMPSEL7_Msk           (0x1UL << ADC_SMPR_SMPSEL7_Pos)         /*!< 0x00008000 */\n#define ADC_SMPR_SMPSEL7               ADC_SMPR_SMPSEL7_Msk                    /*!< ADC channel 7 sampling time selection */\n#define ADC_SMPR_SMPSEL8_Pos           (16U)\n#define ADC_SMPR_SMPSEL8_Msk           (0x1UL << ADC_SMPR_SMPSEL8_Pos)         /*!< 0x00010000 */\n#define ADC_SMPR_SMPSEL8               ADC_SMPR_SMPSEL8_Msk                    /*!< ADC channel 8 sampling time selection */\n#define ADC_SMPR_SMPSEL9_Pos           (17U)\n#define ADC_SMPR_SMPSEL9_Msk           (0x1UL << ADC_SMPR_SMPSEL9_Pos)         /*!< 0x00020000 */\n#define ADC_SMPR_SMPSEL9               ADC_SMPR_SMPSEL9_Msk                    /*!< ADC channel 9 sampling time selection */\n#define ADC_SMPR_SMPSEL10_Pos          (18U)\n#define ADC_SMPR_SMPSEL10_Msk          (0x1UL << ADC_SMPR_SMPSEL10_Pos)        /*!< 0x00040000 */\n#define ADC_SMPR_SMPSEL10              ADC_SMPR_SMPSEL10_Msk                   /*!< ADC channel 10 sampling time selection */\n#define ADC_SMPR_SMPSEL11_Pos          (19U)\n#define ADC_SMPR_SMPSEL11_Msk          (0x1UL << ADC_SMPR_SMPSEL11_Pos)        /*!< 0x00080000 */\n#define ADC_SMPR_SMPSEL11              ADC_SMPR_SMPSEL11_Msk                   /*!< ADC channel 11 sampling time selection */\n#define ADC_SMPR_SMPSEL12_Pos          (20U)\n#define ADC_SMPR_SMPSEL12_Msk          (0x1UL << ADC_SMPR_SMPSEL12_Pos)        /*!< 0x00100000 */\n#define ADC_SMPR_SMPSEL12              ADC_SMPR_SMPSEL12_Msk                   /*!< ADC channel 12 sampling time selection */\n#define ADC_SMPR_SMPSEL13_Pos          (21U)\n#define ADC_SMPR_SMPSEL13_Msk          (0x1UL << ADC_SMPR_SMPSEL13_Pos)        /*!< 0x00200000 */\n#define ADC_SMPR_SMPSEL13              ADC_SMPR_SMPSEL13_Msk                   /*!< ADC channel 13 sampling time selection */\n#define ADC_SMPR_SMPSEL14_Pos          (22U)\n#define ADC_SMPR_SMPSEL14_Msk          (0x1UL << ADC_SMPR_SMPSEL14_Pos)        /*!< 0x00400000 */\n#define ADC_SMPR_SMPSEL14              ADC_SMPR_SMPSEL14_Msk                   /*!< ADC channel 14 sampling time selection */\n#define ADC_SMPR_SMPSEL15_Pos          (23U)\n#define ADC_SMPR_SMPSEL15_Msk          (0x1UL << ADC_SMPR_SMPSEL15_Pos)        /*!< 0x00800000 */\n#define ADC_SMPR_SMPSEL15              ADC_SMPR_SMPSEL15_Msk                   /*!< ADC channel 15 sampling time selection */\n#define ADC_SMPR_SMPSEL16_Pos          (24U)\n#define ADC_SMPR_SMPSEL16_Msk          (0x1UL << ADC_SMPR_SMPSEL16_Pos)        /*!< 0x01000000 */\n#define ADC_SMPR_SMPSEL16              ADC_SMPR_SMPSEL16_Msk                   /*!< ADC channel 16 sampling time selection */\n#define ADC_SMPR_SMPSEL17_Pos          (25U)\n#define ADC_SMPR_SMPSEL17_Msk          (0x1UL << ADC_SMPR_SMPSEL17_Pos)        /*!< 0x02000000 */\n#define ADC_SMPR_SMPSEL17              ADC_SMPR_SMPSEL17_Msk                   /*!< ADC channel 17 sampling time selection */\n#define ADC_SMPR_SMPSEL18_Pos          (26U)\n#define ADC_SMPR_SMPSEL18_Msk          (0x1UL << ADC_SMPR_SMPSEL18_Pos)        /*!< 0x04000000 */\n#define ADC_SMPR_SMPSEL18              ADC_SMPR_SMPSEL18_Msk                   /*!< ADC channel 18 sampling time selection */\n\n/********************  Bit definition for ADC_TR1 register  *******************/\n#define ADC_TR1_LT1_Pos                (0U)\n#define ADC_TR1_LT1_Msk                (0xFFFUL << ADC_TR1_LT1_Pos)            /*!< 0x00000FFF */\n#define ADC_TR1_LT1                    ADC_TR1_LT1_Msk                         /*!< ADC analog watchdog 1 threshold low */\n#define ADC_TR1_LT1_0                  (0x001UL << ADC_TR1_LT1_Pos)            /*!< 0x00000001 */\n#define ADC_TR1_LT1_1                  (0x002UL << ADC_TR1_LT1_Pos)            /*!< 0x00000002 */\n#define ADC_TR1_LT1_2                  (0x004UL << ADC_TR1_LT1_Pos)            /*!< 0x00000004 */\n#define ADC_TR1_LT1_3                  (0x008UL << ADC_TR1_LT1_Pos)            /*!< 0x00000008 */\n#define ADC_TR1_LT1_4                  (0x010UL << ADC_TR1_LT1_Pos)            /*!< 0x00000010 */\n#define ADC_TR1_LT1_5                  (0x020UL << ADC_TR1_LT1_Pos)            /*!< 0x00000020 */\n#define ADC_TR1_LT1_6                  (0x040UL << ADC_TR1_LT1_Pos)            /*!< 0x00000040 */\n#define ADC_TR1_LT1_7                  (0x080UL << ADC_TR1_LT1_Pos)            /*!< 0x00000080 */\n#define ADC_TR1_LT1_8                  (0x100UL << ADC_TR1_LT1_Pos)            /*!< 0x00000100 */\n#define ADC_TR1_LT1_9                  (0x200UL << ADC_TR1_LT1_Pos)            /*!< 0x00000200 */\n#define ADC_TR1_LT1_10                 (0x400UL << ADC_TR1_LT1_Pos)            /*!< 0x00000400 */\n#define ADC_TR1_LT1_11                 (0x800UL << ADC_TR1_LT1_Pos)            /*!< 0x00000800 */\n\n#define ADC_TR1_HT1_Pos                (16U)\n#define ADC_TR1_HT1_Msk                (0xFFFUL << ADC_TR1_HT1_Pos)            /*!< 0x0FFF0000 */\n#define ADC_TR1_HT1                    ADC_TR1_HT1_Msk                         /*!< ADC Analog watchdog 1 threshold high */\n#define ADC_TR1_HT1_0                  (0x001UL << ADC_TR1_HT1_Pos)            /*!< 0x00010000 */\n#define ADC_TR1_HT1_1                  (0x002UL << ADC_TR1_HT1_Pos)            /*!< 0x00020000 */\n#define ADC_TR1_HT1_2                  (0x004UL << ADC_TR1_HT1_Pos)            /*!< 0x00040000 */\n#define ADC_TR1_HT1_3                  (0x008UL << ADC_TR1_HT1_Pos)            /*!< 0x00080000 */\n#define ADC_TR1_HT1_4                  (0x010UL << ADC_TR1_HT1_Pos)            /*!< 0x00100000 */\n#define ADC_TR1_HT1_5                  (0x020UL << ADC_TR1_HT1_Pos)            /*!< 0x00200000 */\n#define ADC_TR1_HT1_6                  (0x040UL << ADC_TR1_HT1_Pos)            /*!< 0x00400000 */\n#define ADC_TR1_HT1_7                  (0x080UL << ADC_TR1_HT1_Pos)            /*!< 0x00800000 */\n#define ADC_TR1_HT1_8                  (0x100UL << ADC_TR1_HT1_Pos)            /*!< 0x01000000 */\n#define ADC_TR1_HT1_9                  (0x200UL << ADC_TR1_HT1_Pos)            /*!< 0x02000000 */\n#define ADC_TR1_HT1_10                 (0x400UL << ADC_TR1_HT1_Pos)            /*!< 0x04000000 */\n#define ADC_TR1_HT1_11                 (0x800UL << ADC_TR1_HT1_Pos)            /*!< 0x08000000 */\n\n/********************  Bit definition for ADC_TR2 register  *******************/\n#define ADC_TR2_LT2_Pos                (0U)\n#define ADC_TR2_LT2_Msk                (0xFFFUL << ADC_TR2_LT2_Pos)            /*!< 0x00000FFF */\n#define ADC_TR2_LT2                    ADC_TR2_LT2_Msk                         /*!< ADC analog watchdog 2 threshold low */\n#define ADC_TR2_LT2_0                  (0x001UL << ADC_TR2_LT2_Pos)            /*!< 0x00000001 */\n#define ADC_TR2_LT2_1                  (0x002UL << ADC_TR2_LT2_Pos)            /*!< 0x00000002 */\n#define ADC_TR2_LT2_2                  (0x004UL << ADC_TR2_LT2_Pos)            /*!< 0x00000004 */\n#define ADC_TR2_LT2_3                  (0x008UL << ADC_TR2_LT2_Pos)            /*!< 0x00000008 */\n#define ADC_TR2_LT2_4                  (0x010UL << ADC_TR2_LT2_Pos)            /*!< 0x00000010 */\n#define ADC_TR2_LT2_5                  (0x020UL << ADC_TR2_LT2_Pos)            /*!< 0x00000020 */\n#define ADC_TR2_LT2_6                  (0x040UL << ADC_TR2_LT2_Pos)            /*!< 0x00000040 */\n#define ADC_TR2_LT2_7                  (0x080UL << ADC_TR2_LT2_Pos)            /*!< 0x00000080 */\n#define ADC_TR2_LT2_8                  (0x100UL << ADC_TR2_LT2_Pos)            /*!< 0x00000100 */\n#define ADC_TR2_LT2_9                  (0x200UL << ADC_TR2_LT2_Pos)            /*!< 0x00000200 */\n#define ADC_TR2_LT2_10                 (0x400UL << ADC_TR2_LT2_Pos)            /*!< 0x00000400 */\n#define ADC_TR2_LT2_11                 (0x800UL << ADC_TR2_LT2_Pos)            /*!< 0x00000800 */\n\n#define ADC_TR2_HT2_Pos                (16U)\n#define ADC_TR2_HT2_Msk                (0xFFFUL << ADC_TR2_HT2_Pos)            /*!< 0x0FFF0000 */\n#define ADC_TR2_HT2                    ADC_TR2_HT2_Msk                         /*!< ADC analog watchdog 2 threshold high */\n#define ADC_TR2_HT2_0                  (0x001UL << ADC_TR2_HT2_Pos)            /*!< 0x00010000 */\n#define ADC_TR2_HT2_1                  (0x002UL << ADC_TR2_HT2_Pos)            /*!< 0x00020000 */\n#define ADC_TR2_HT2_2                  (0x004UL << ADC_TR2_HT2_Pos)            /*!< 0x00040000 */\n#define ADC_TR2_HT2_3                  (0x008UL << ADC_TR2_HT2_Pos)            /*!< 0x00080000 */\n#define ADC_TR2_HT2_4                  (0x010UL << ADC_TR2_HT2_Pos)            /*!< 0x00100000 */\n#define ADC_TR2_HT2_5                  (0x020UL << ADC_TR2_HT2_Pos)            /*!< 0x00200000 */\n#define ADC_TR2_HT2_6                  (0x040UL << ADC_TR2_HT2_Pos)            /*!< 0x00400000 */\n#define ADC_TR2_HT2_7                  (0x080UL << ADC_TR2_HT2_Pos)            /*!< 0x00800000 */\n#define ADC_TR2_HT2_8                  (0x100UL << ADC_TR2_HT2_Pos)            /*!< 0x01000000 */\n#define ADC_TR2_HT2_9                  (0x200UL << ADC_TR2_HT2_Pos)            /*!< 0x02000000 */\n#define ADC_TR2_HT2_10                 (0x400UL << ADC_TR2_HT2_Pos)            /*!< 0x04000000 */\n#define ADC_TR2_HT2_11                 (0x800UL << ADC_TR2_HT2_Pos)            /*!< 0x08000000 */\n\n/********************  Bit definition for ADC_CHSELR register  ****************/\n#define ADC_CHSELR_CHSEL_Pos           (0U)\n#define ADC_CHSELR_CHSEL_Msk           (0x7FFFFFUL << ADC_CHSELR_CHSEL_Pos)    /*!< 0x0007FFFFF */\n#define ADC_CHSELR_CHSEL               ADC_CHSELR_CHSEL_Msk                    /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */\n#define ADC_CHSELR_CHSEL22_Pos         (22U)\n#define ADC_CHSELR_CHSEL22_Msk         (0x1UL << ADC_CHSELR_CHSEL22_Pos)       /*!< 0x00400000 */\n#define ADC_CHSELR_CHSEL22             ADC_CHSELR_CHSEL22_Msk                  /*!< ADC group regular sequencer channel 22, available when ADC_CFGR1_CHSELRMOD is reset */\n#define ADC_CHSELR_CHSEL21_Pos         (21U)\n#define ADC_CHSELR_CHSEL21_Msk         (0x1UL << ADC_CHSELR_CHSEL21_Pos)       /*!< 0x00200000 */\n#define ADC_CHSELR_CHSEL21             ADC_CHSELR_CHSEL21_Msk                  /*!< ADC group regular sequencer channel 21, available when ADC_CFGR1_CHSELRMOD is reset */\n#define ADC_CHSELR_CHSEL20_Pos         (20U)\n#define ADC_CHSELR_CHSEL20_Msk         (0x1UL << ADC_CHSELR_CHSEL20_Pos)       /*!< 0x00100000 */\n#define ADC_CHSELR_CHSEL20             ADC_CHSELR_CHSEL20_Msk                  /*!< ADC group regular sequencer channel 20, available when ADC_CFGR1_CHSELRMOD is reset */\n#define ADC_CHSELR_CHSEL19_Pos         (19U)\n#define ADC_CHSELR_CHSEL19_Msk         (0x1UL << ADC_CHSELR_CHSEL19_Pos)       /*!< 0x00080000 */\n#define ADC_CHSELR_CHSEL19             ADC_CHSELR_CHSEL19_Msk                  /*!< ADC group regular sequencer channel 19, available when ADC_CFGR1_CHSELRMOD is reset */\n#define ADC_CHSELR_CHSEL18_Pos         (18U)\n#define ADC_CHSELR_CHSEL18_Msk         (0x1UL << ADC_CHSELR_CHSEL18_Pos)       /*!< 0x00040000 */\n#define ADC_CHSELR_CHSEL18             ADC_CHSELR_CHSEL18_Msk                  /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */\n#define ADC_CHSELR_CHSEL17_Pos         (17U)\n#define ADC_CHSELR_CHSEL17_Msk         (0x1UL << ADC_CHSELR_CHSEL17_Pos)       /*!< 0x00020000 */\n#define ADC_CHSELR_CHSEL17             ADC_CHSELR_CHSEL17_Msk                  /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */\n#define ADC_CHSELR_CHSEL16_Pos         (16U)\n#define ADC_CHSELR_CHSEL16_Msk         (0x1UL << ADC_CHSELR_CHSEL16_Pos)       /*!< 0x00010000 */\n#define ADC_CHSELR_CHSEL16             ADC_CHSELR_CHSEL16_Msk                  /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */\n#define ADC_CHSELR_CHSEL15_Pos         (15U)\n#define ADC_CHSELR_CHSEL15_Msk         (0x1UL << ADC_CHSELR_CHSEL15_Pos)       /*!< 0x00008000 */\n#define ADC_CHSELR_CHSEL15             ADC_CHSELR_CHSEL15_Msk                  /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */\n#define ADC_CHSELR_CHSEL14_Pos         (14U)\n#define ADC_CHSELR_CHSEL14_Msk         (0x1UL << ADC_CHSELR_CHSEL14_Pos)       /*!< 0x00004000 */\n#define ADC_CHSELR_CHSEL14             ADC_CHSELR_CHSEL14_Msk                  /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */\n#define ADC_CHSELR_CHSEL13_Pos         (13U)\n#define ADC_CHSELR_CHSEL13_Msk         (0x1UL << ADC_CHSELR_CHSEL13_Pos)       /*!< 0x00002000 */\n#define ADC_CHSELR_CHSEL13             ADC_CHSELR_CHSEL13_Msk                  /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */\n#define ADC_CHSELR_CHSEL12_Pos         (12U)\n#define ADC_CHSELR_CHSEL12_Msk         (0x1UL << ADC_CHSELR_CHSEL12_Pos)       /*!< 0x00001000 */\n#define ADC_CHSELR_CHSEL12             ADC_CHSELR_CHSEL12_Msk                  /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */\n#define ADC_CHSELR_CHSEL11_Pos         (11U)\n#define ADC_CHSELR_CHSEL11_Msk         (0x1UL << ADC_CHSELR_CHSEL11_Pos)       /*!< 0x00000800 */\n#define ADC_CHSELR_CHSEL11             ADC_CHSELR_CHSEL11_Msk                  /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */\n#define ADC_CHSELR_CHSEL10_Pos         (10U)\n#define ADC_CHSELR_CHSEL10_Msk         (0x1UL << ADC_CHSELR_CHSEL10_Pos)       /*!< 0x00000400 */\n#define ADC_CHSELR_CHSEL10             ADC_CHSELR_CHSEL10_Msk                  /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */\n#define ADC_CHSELR_CHSEL9_Pos          (9U)\n#define ADC_CHSELR_CHSEL9_Msk          (0x1UL << ADC_CHSELR_CHSEL9_Pos)        /*!< 0x00000200 */\n#define ADC_CHSELR_CHSEL9              ADC_CHSELR_CHSEL9_Msk                   /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */\n#define ADC_CHSELR_CHSEL8_Pos          (8U)\n#define ADC_CHSELR_CHSEL8_Msk          (0x1UL << ADC_CHSELR_CHSEL8_Pos)        /*!< 0x00000100 */\n#define ADC_CHSELR_CHSEL8              ADC_CHSELR_CHSEL8_Msk                   /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */\n#define ADC_CHSELR_CHSEL7_Pos          (7U)\n#define ADC_CHSELR_CHSEL7_Msk          (0x1UL << ADC_CHSELR_CHSEL7_Pos)        /*!< 0x00000080 */\n#define ADC_CHSELR_CHSEL7              ADC_CHSELR_CHSEL7_Msk                   /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */\n#define ADC_CHSELR_CHSEL6_Pos          (6U)\n#define ADC_CHSELR_CHSEL6_Msk          (0x1UL << ADC_CHSELR_CHSEL6_Pos)        /*!< 0x00000040 */\n#define ADC_CHSELR_CHSEL6              ADC_CHSELR_CHSEL6_Msk                   /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */\n#define ADC_CHSELR_CHSEL5_Pos          (5U)\n#define ADC_CHSELR_CHSEL5_Msk          (0x1UL << ADC_CHSELR_CHSEL5_Pos)        /*!< 0x00000020 */\n#define ADC_CHSELR_CHSEL5              ADC_CHSELR_CHSEL5_Msk                   /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */\n#define ADC_CHSELR_CHSEL4_Pos          (4U)\n#define ADC_CHSELR_CHSEL4_Msk          (0x1UL << ADC_CHSELR_CHSEL4_Pos)        /*!< 0x00000010 */\n#define ADC_CHSELR_CHSEL4              ADC_CHSELR_CHSEL4_Msk                   /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */\n#define ADC_CHSELR_CHSEL3_Pos          (3U)\n#define ADC_CHSELR_CHSEL3_Msk          (0x1UL << ADC_CHSELR_CHSEL3_Pos)        /*!< 0x00000008 */\n#define ADC_CHSELR_CHSEL3              ADC_CHSELR_CHSEL3_Msk                   /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */\n#define ADC_CHSELR_CHSEL2_Pos          (2U)\n#define ADC_CHSELR_CHSEL2_Msk          (0x1UL << ADC_CHSELR_CHSEL2_Pos)        /*!< 0x00000004 */\n#define ADC_CHSELR_CHSEL2              ADC_CHSELR_CHSEL2_Msk                   /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */\n#define ADC_CHSELR_CHSEL1_Pos          (1U)\n#define ADC_CHSELR_CHSEL1_Msk          (0x1UL << ADC_CHSELR_CHSEL1_Pos)        /*!< 0x00000002 */\n#define ADC_CHSELR_CHSEL1              ADC_CHSELR_CHSEL1_Msk                   /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */\n#define ADC_CHSELR_CHSEL0_Pos          (0U)\n#define ADC_CHSELR_CHSEL0_Msk          (0x1UL << ADC_CHSELR_CHSEL0_Pos)        /*!< 0x00000001 */\n#define ADC_CHSELR_CHSEL0              ADC_CHSELR_CHSEL0_Msk                   /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */\n\n#define ADC_CHSELR_SQ_ALL_Pos          (0U)\n#define ADC_CHSELR_SQ_ALL_Msk          (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */\n#define ADC_CHSELR_SQ_ALL              ADC_CHSELR_SQ_ALL_Msk                   /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */\n\n#define ADC_CHSELR_SQ8_Pos             (28U)\n#define ADC_CHSELR_SQ8_Msk             (0xFUL << ADC_CHSELR_SQ8_Pos)           /*!< 0xF0000000 */\n#define ADC_CHSELR_SQ8                 ADC_CHSELR_SQ8_Msk                      /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */\n#define ADC_CHSELR_SQ8_0               (0x1UL << ADC_CHSELR_SQ8_Pos)           /*!< 0x10000000 */\n#define ADC_CHSELR_SQ8_1               (0x2UL << ADC_CHSELR_SQ8_Pos)           /*!< 0x20000000 */\n#define ADC_CHSELR_SQ8_2               (0x4UL << ADC_CHSELR_SQ8_Pos)           /*!< 0x40000000 */\n#define ADC_CHSELR_SQ8_3               (0x8UL << ADC_CHSELR_SQ8_Pos)           /*!< 0x80000000 */\n\n#define ADC_CHSELR_SQ7_Pos             (24U)\n#define ADC_CHSELR_SQ7_Msk             (0xFUL << ADC_CHSELR_SQ7_Pos)           /*!< 0x0F000000 */\n#define ADC_CHSELR_SQ7                 ADC_CHSELR_SQ7_Msk                      /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */\n#define ADC_CHSELR_SQ7_0               (0x1UL << ADC_CHSELR_SQ7_Pos)           /*!< 0x01000000 */\n#define ADC_CHSELR_SQ7_1               (0x2UL << ADC_CHSELR_SQ7_Pos)           /*!< 0x02000000 */\n#define ADC_CHSELR_SQ7_2               (0x4UL << ADC_CHSELR_SQ7_Pos)           /*!< 0x04000000 */\n#define ADC_CHSELR_SQ7_3               (0x8UL << ADC_CHSELR_SQ7_Pos)           /*!< 0x08000000 */\n\n#define ADC_CHSELR_SQ6_Pos             (20U)\n#define ADC_CHSELR_SQ6_Msk             (0xFUL << ADC_CHSELR_SQ6_Pos)           /*!< 0x00F00000 */\n#define ADC_CHSELR_SQ6                 ADC_CHSELR_SQ6_Msk                      /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */\n#define ADC_CHSELR_SQ6_0               (0x1UL << ADC_CHSELR_SQ6_Pos)           /*!< 0x00100000 */\n#define ADC_CHSELR_SQ6_1               (0x2UL << ADC_CHSELR_SQ6_Pos)           /*!< 0x00200000 */\n#define ADC_CHSELR_SQ6_2               (0x4UL << ADC_CHSELR_SQ6_Pos)           /*!< 0x00400000 */\n#define ADC_CHSELR_SQ6_3               (0x8UL << ADC_CHSELR_SQ6_Pos)           /*!< 0x00800000 */\n\n#define ADC_CHSELR_SQ5_Pos             (16U)\n#define ADC_CHSELR_SQ5_Msk             (0xFUL << ADC_CHSELR_SQ5_Pos)           /*!< 0x000F0000 */\n#define ADC_CHSELR_SQ5                 ADC_CHSELR_SQ5_Msk                      /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */\n#define ADC_CHSELR_SQ5_0               (0x1UL << ADC_CHSELR_SQ5_Pos)           /*!< 0x00010000 */\n#define ADC_CHSELR_SQ5_1               (0x2UL << ADC_CHSELR_SQ5_Pos)           /*!< 0x00020000 */\n#define ADC_CHSELR_SQ5_2               (0x4UL << ADC_CHSELR_SQ5_Pos)           /*!< 0x00040000 */\n#define ADC_CHSELR_SQ5_3               (0x8UL << ADC_CHSELR_SQ5_Pos)           /*!< 0x00080000 */\n\n#define ADC_CHSELR_SQ4_Pos             (12U)\n#define ADC_CHSELR_SQ4_Msk             (0xFUL << ADC_CHSELR_SQ4_Pos)           /*!< 0x0000F000 */\n#define ADC_CHSELR_SQ4                 ADC_CHSELR_SQ4_Msk                      /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */\n#define ADC_CHSELR_SQ4_0               (0x1UL << ADC_CHSELR_SQ4_Pos)           /*!< 0x00001000 */\n#define ADC_CHSELR_SQ4_1               (0x2UL << ADC_CHSELR_SQ4_Pos)           /*!< 0x00002000 */\n#define ADC_CHSELR_SQ4_2               (0x4UL << ADC_CHSELR_SQ4_Pos)           /*!< 0x00004000 */\n#define ADC_CHSELR_SQ4_3               (0x8UL << ADC_CHSELR_SQ4_Pos)           /*!< 0x00008000 */\n\n#define ADC_CHSELR_SQ3_Pos             (8U)\n#define ADC_CHSELR_SQ3_Msk             (0xFUL << ADC_CHSELR_SQ3_Pos)           /*!< 0x00000F00 */\n#define ADC_CHSELR_SQ3                 ADC_CHSELR_SQ3_Msk                      /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */\n#define ADC_CHSELR_SQ3_0               (0x1UL << ADC_CHSELR_SQ3_Pos)           /*!< 0x00000100 */\n#define ADC_CHSELR_SQ3_1               (0x2UL << ADC_CHSELR_SQ3_Pos)           /*!< 0x00000200 */\n#define ADC_CHSELR_SQ3_2               (0x4UL << ADC_CHSELR_SQ3_Pos)           /*!< 0x00000400 */\n#define ADC_CHSELR_SQ3_3               (0x8UL << ADC_CHSELR_SQ3_Pos)           /*!< 0x00000800 */\n\n#define ADC_CHSELR_SQ2_Pos             (4U)\n#define ADC_CHSELR_SQ2_Msk             (0xFUL << ADC_CHSELR_SQ2_Pos)           /*!< 0x000000F0 */\n#define ADC_CHSELR_SQ2                 ADC_CHSELR_SQ2_Msk                      /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */\n#define ADC_CHSELR_SQ2_0               (0x1UL << ADC_CHSELR_SQ2_Pos)           /*!< 0x00000010 */\n#define ADC_CHSELR_SQ2_1               (0x2UL << ADC_CHSELR_SQ2_Pos)           /*!< 0x00000020 */\n#define ADC_CHSELR_SQ2_2               (0x4UL << ADC_CHSELR_SQ2_Pos)           /*!< 0x00000040 */\n#define ADC_CHSELR_SQ2_3               (0x8UL << ADC_CHSELR_SQ2_Pos)           /*!< 0x00000080 */\n\n#define ADC_CHSELR_SQ1_Pos             (0U)\n#define ADC_CHSELR_SQ1_Msk             (0xFUL << ADC_CHSELR_SQ1_Pos)           /*!< 0x0000000F */\n#define ADC_CHSELR_SQ1                 ADC_CHSELR_SQ1_Msk                      /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */\n#define ADC_CHSELR_SQ1_0               (0x1UL << ADC_CHSELR_SQ1_Pos)           /*!< 0x00000001 */\n#define ADC_CHSELR_SQ1_1               (0x2UL << ADC_CHSELR_SQ1_Pos)           /*!< 0x00000002 */\n#define ADC_CHSELR_SQ1_2               (0x4UL << ADC_CHSELR_SQ1_Pos)           /*!< 0x00000004 */\n#define ADC_CHSELR_SQ1_3               (0x8UL << ADC_CHSELR_SQ1_Pos)           /*!< 0x00000008 */\n\n/********************  Bit definition for ADC_TR3 register  *******************/\n#define ADC_TR3_LT3_Pos                (0U)\n#define ADC_TR3_LT3_Msk                (0xFFFUL << ADC_TR3_LT3_Pos)            /*!< 0x00000FFF */\n#define ADC_TR3_LT3                    ADC_TR3_LT3_Msk                         /*!< ADC analog watchdog 3 threshold low */\n#define ADC_TR3_LT3_0                  (0x001UL << ADC_TR3_LT3_Pos)            /*!< 0x00000001 */\n#define ADC_TR3_LT3_1                  (0x002UL << ADC_TR3_LT3_Pos)            /*!< 0x00000002 */\n#define ADC_TR3_LT3_2                  (0x004UL << ADC_TR3_LT3_Pos)            /*!< 0x00000004 */\n#define ADC_TR3_LT3_3                  (0x008UL << ADC_TR3_LT3_Pos)            /*!< 0x00000008 */\n#define ADC_TR3_LT3_4                  (0x010UL << ADC_TR3_LT3_Pos)            /*!< 0x00000010 */\n#define ADC_TR3_LT3_5                  (0x020UL << ADC_TR3_LT3_Pos)            /*!< 0x00000020 */\n#define ADC_TR3_LT3_6                  (0x040UL << ADC_TR3_LT3_Pos)            /*!< 0x00000040 */\n#define ADC_TR3_LT3_7                  (0x080UL << ADC_TR3_LT3_Pos)            /*!< 0x00000080 */\n#define ADC_TR3_LT3_8                  (0x100UL << ADC_TR3_LT3_Pos)            /*!< 0x00000100 */\n#define ADC_TR3_LT3_9                  (0x200UL << ADC_TR3_LT3_Pos)            /*!< 0x00000200 */\n#define ADC_TR3_LT3_10                 (0x400UL << ADC_TR3_LT3_Pos)            /*!< 0x00000400 */\n#define ADC_TR3_LT3_11                 (0x800UL << ADC_TR3_LT3_Pos)            /*!< 0x00000800 */\n\n#define ADC_TR3_HT3_Pos                (16U)\n#define ADC_TR3_HT3_Msk                (0xFFFUL << ADC_TR3_HT3_Pos)            /*!< 0x0FFF0000 */\n#define ADC_TR3_HT3                    ADC_TR3_HT3_Msk                         /*!< ADC analog watchdog 3 threshold high */\n#define ADC_TR3_HT3_0                  (0x001UL << ADC_TR3_HT3_Pos)            /*!< 0x00010000 */\n#define ADC_TR3_HT3_1                  (0x002UL << ADC_TR3_HT3_Pos)            /*!< 0x00020000 */\n#define ADC_TR3_HT3_2                  (0x004UL << ADC_TR3_HT3_Pos)            /*!< 0x00040000 */\n#define ADC_TR3_HT3_3                  (0x008UL << ADC_TR3_HT3_Pos)            /*!< 0x00080000 */\n#define ADC_TR3_HT3_4                  (0x010UL << ADC_TR3_HT3_Pos)            /*!< 0x00100000 */\n#define ADC_TR3_HT3_5                  (0x020UL << ADC_TR3_HT3_Pos)            /*!< 0x00200000 */\n#define ADC_TR3_HT3_6                  (0x040UL << ADC_TR3_HT3_Pos)            /*!< 0x00400000 */\n#define ADC_TR3_HT3_7                  (0x080UL << ADC_TR3_HT3_Pos)            /*!< 0x00800000 */\n#define ADC_TR3_HT3_8                  (0x100UL << ADC_TR3_HT3_Pos)            /*!< 0x01000000 */\n#define ADC_TR3_HT3_9                  (0x200UL << ADC_TR3_HT3_Pos)            /*!< 0x02000000 */\n#define ADC_TR3_HT3_10                 (0x400UL << ADC_TR3_HT3_Pos)            /*!< 0x04000000 */\n#define ADC_TR3_HT3_11                 (0x800UL << ADC_TR3_HT3_Pos)            /*!< 0x08000000 */\n\n/********************  Bit definition for ADC_DR register  ********************/\n#define ADC_DR_DATA_Pos                (0U)\n#define ADC_DR_DATA_Msk                (0xFFFFUL << ADC_DR_DATA_Pos)           /*!< 0x0000FFFF */\n#define ADC_DR_DATA                    ADC_DR_DATA_Msk                         /*!< ADC group regular conversion data */\n#define ADC_DR_DATA_0                  (0x0001UL << ADC_DR_DATA_Pos)           /*!< 0x00000001 */\n#define ADC_DR_DATA_1                  (0x0002UL << ADC_DR_DATA_Pos)           /*!< 0x00000002 */\n#define ADC_DR_DATA_2                  (0x0004UL << ADC_DR_DATA_Pos)           /*!< 0x00000004 */\n#define ADC_DR_DATA_3                  (0x0008UL << ADC_DR_DATA_Pos)           /*!< 0x00000008 */\n#define ADC_DR_DATA_4                  (0x0010UL << ADC_DR_DATA_Pos)           /*!< 0x00000010 */\n#define ADC_DR_DATA_5                  (0x0020UL << ADC_DR_DATA_Pos)           /*!< 0x00000020 */\n#define ADC_DR_DATA_6                  (0x0040UL << ADC_DR_DATA_Pos)           /*!< 0x00000040 */\n#define ADC_DR_DATA_7                  (0x0080UL << ADC_DR_DATA_Pos)           /*!< 0x00000080 */\n#define ADC_DR_DATA_8                  (0x0100UL << ADC_DR_DATA_Pos)           /*!< 0x00000100 */\n#define ADC_DR_DATA_9                  (0x0200UL << ADC_DR_DATA_Pos)           /*!< 0x00000200 */\n#define ADC_DR_DATA_10                 (0x0400UL << ADC_DR_DATA_Pos)           /*!< 0x00000400 */\n#define ADC_DR_DATA_11                 (0x0800UL << ADC_DR_DATA_Pos)           /*!< 0x00000800 */\n#define ADC_DR_DATA_12                 (0x1000UL << ADC_DR_DATA_Pos)           /*!< 0x00001000 */\n#define ADC_DR_DATA_13                 (0x2000UL << ADC_DR_DATA_Pos)           /*!< 0x00002000 */\n#define ADC_DR_DATA_14                 (0x4000UL << ADC_DR_DATA_Pos)           /*!< 0x00004000 */\n#define ADC_DR_DATA_15                 (0x8000UL << ADC_DR_DATA_Pos)           /*!< 0x00008000 */\n\n/********************  Bit definition for ADC_AWD2CR register  ****************/\n#define ADC_AWD2CR_AWD2CH_Pos          (0U)\n#define ADC_AWD2CR_AWD2CH_Msk          (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x0007FFFF */\n#define ADC_AWD2CR_AWD2CH              ADC_AWD2CR_AWD2CH_Msk                   /*!< ADC analog watchdog 2 monitored channel selection */\n#define ADC_AWD2CR_AWD2CH_0            (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000001 */\n#define ADC_AWD2CR_AWD2CH_1            (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000002 */\n#define ADC_AWD2CR_AWD2CH_2            (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000004 */\n#define ADC_AWD2CR_AWD2CH_3            (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000008 */\n#define ADC_AWD2CR_AWD2CH_4            (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000010 */\n#define ADC_AWD2CR_AWD2CH_5            (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000020 */\n#define ADC_AWD2CR_AWD2CH_6            (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000040 */\n#define ADC_AWD2CR_AWD2CH_7            (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000080 */\n#define ADC_AWD2CR_AWD2CH_8            (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000100 */\n#define ADC_AWD2CR_AWD2CH_9            (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000200 */\n#define ADC_AWD2CR_AWD2CH_10           (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000400 */\n#define ADC_AWD2CR_AWD2CH_11           (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000800 */\n#define ADC_AWD2CR_AWD2CH_12           (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00001000 */\n#define ADC_AWD2CR_AWD2CH_13           (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00002000 */\n#define ADC_AWD2CR_AWD2CH_14           (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00004000 */\n#define ADC_AWD2CR_AWD2CH_15           (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00008000 */\n#define ADC_AWD2CR_AWD2CH_16           (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00010000 */\n#define ADC_AWD2CR_AWD2CH_17           (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00020000 */\n#define ADC_AWD2CR_AWD2CH_18           (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00040000 */\n\n/********************  Bit definition for ADC_AWD3CR register  ****************/\n#define ADC_AWD3CR_AWD3CH_Pos          (0U)\n#define ADC_AWD3CR_AWD3CH_Msk          (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x0007FFFF */\n#define ADC_AWD3CR_AWD3CH              ADC_AWD3CR_AWD3CH_Msk                   /*!< ADC analog watchdog 3 monitored channel selection */\n#define ADC_AWD3CR_AWD3CH_0            (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000001 */\n#define ADC_AWD3CR_AWD3CH_1            (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000002 */\n#define ADC_AWD3CR_AWD3CH_2            (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000004 */\n#define ADC_AWD3CR_AWD3CH_3            (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000008 */\n#define ADC_AWD3CR_AWD3CH_4            (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000010 */\n#define ADC_AWD3CR_AWD3CH_5            (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000020 */\n#define ADC_AWD3CR_AWD3CH_6            (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000040 */\n#define ADC_AWD3CR_AWD3CH_7            (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000080 */\n#define ADC_AWD3CR_AWD3CH_8            (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000100 */\n#define ADC_AWD3CR_AWD3CH_9            (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000200 */\n#define ADC_AWD3CR_AWD3CH_10           (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000400 */\n#define ADC_AWD3CR_AWD3CH_11           (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000800 */\n#define ADC_AWD3CR_AWD3CH_12           (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00001000 */\n#define ADC_AWD3CR_AWD3CH_13           (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00002000 */\n#define ADC_AWD3CR_AWD3CH_14           (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00004000 */\n#define ADC_AWD3CR_AWD3CH_15           (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00008000 */\n#define ADC_AWD3CR_AWD3CH_16           (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00010000 */\n#define ADC_AWD3CR_AWD3CH_17           (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00020000 */\n#define ADC_AWD3CR_AWD3CH_18           (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00040000 */\n\n/********************  Bit definition for ADC_CALFACT register  ***************/\n#define ADC_CALFACT_CALFACT_Pos        (0U)\n#define ADC_CALFACT_CALFACT_Msk        (0x7FUL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x0000007F */\n#define ADC_CALFACT_CALFACT            ADC_CALFACT_CALFACT_Msk                 /*!< ADC calibration factor in single-ended mode */\n#define ADC_CALFACT_CALFACT_0          (0x01UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000001 */\n#define ADC_CALFACT_CALFACT_1          (0x02UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000002 */\n#define ADC_CALFACT_CALFACT_2          (0x04UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000004 */\n#define ADC_CALFACT_CALFACT_3          (0x08UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000008 */\n#define ADC_CALFACT_CALFACT_4          (0x10UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000010 */\n#define ADC_CALFACT_CALFACT_5          (0x20UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000020 */\n#define ADC_CALFACT_CALFACT_6          (0x40UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000040 */\n\n/*************************  ADC Common registers  *****************************/\n/********************  Bit definition for ADC_CCR register  *******************/\n#define ADC_CCR_PRESC_Pos              (18U)\n#define ADC_CCR_PRESC_Msk              (0xFUL << ADC_CCR_PRESC_Pos)            /*!< 0x003C0000 */\n#define ADC_CCR_PRESC                  ADC_CCR_PRESC_Msk                       /*!< ADC common clock prescaler, only for clock source asynchronous */\n#define ADC_CCR_PRESC_0                (0x1UL << ADC_CCR_PRESC_Pos)            /*!< 0x00040000 */\n#define ADC_CCR_PRESC_1                (0x2UL << ADC_CCR_PRESC_Pos)            /*!< 0x00080000 */\n#define ADC_CCR_PRESC_2                (0x4UL << ADC_CCR_PRESC_Pos)            /*!< 0x00100000 */\n#define ADC_CCR_PRESC_3                (0x8UL << ADC_CCR_PRESC_Pos)            /*!< 0x00200000 */\n\n#define ADC_CCR_VREFEN_Pos             (22U)\n#define ADC_CCR_VREFEN_Msk             (0x1UL << ADC_CCR_VREFEN_Pos)           /*!< 0x00400000 */\n#define ADC_CCR_VREFEN                 ADC_CCR_VREFEN_Msk                      /*!< ADC internal path to VrefInt enable */\n#define ADC_CCR_TSEN_Pos               (23U)\n#define ADC_CCR_TSEN_Msk               (0x1UL << ADC_CCR_TSEN_Pos)             /*!< 0x00800000 */\n#define ADC_CCR_TSEN                   ADC_CCR_TSEN_Msk                        /*!< ADC internal path to temperature sensor enable */\n\n/* Legacy */\n#define ADC_CCR_LFMEN_Pos              (25U)\n#define ADC_CCR_LFMEN_Msk              (0x1UL << ADC_CCR_LFMEN_Pos)            /*!< 0x02000000 */\n#define ADC_CCR_LFMEN                  ADC_CCR_LFMEN_Msk                       /*!< Legacy feature, useless on STM32C0 (ADC common clock low frequency mode is automatically managed by ADC peripheral on STM32C0) */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                          CRC calculation unit                              */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for CRC_DR register  *********************/\n#define CRC_DR_DR_Pos            (0U)\n#define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)                /*!< 0xFFFFFFFF */\n#define CRC_DR_DR                CRC_DR_DR_Msk                                  /*!< Data register bits */\n\n/*******************  Bit definition for CRC_IDR register  ********************/\n#define CRC_IDR_IDR_Pos          (0U)\n#define CRC_IDR_IDR_Msk          (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)              /*!< 0xFFFFFFFF */\n#define CRC_IDR_IDR              CRC_IDR_IDR_Msk                                /*!< General-purpose 32-bits data register bits */\n\n/********************  Bit definition for CRC_CR register  ********************/\n#define CRC_CR_RESET_Pos         (0U)\n#define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                    /*!< 0x00000001 */\n#define CRC_CR_RESET             CRC_CR_RESET_Msk                               /*!< RESET the CRC computation unit bit */\n#define CRC_CR_POLYSIZE_Pos      (3U)\n#define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000018 */\n#define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                            /*!< Polynomial size bits */\n#define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */\n#define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */\n#define CRC_CR_REV_IN_Pos        (5U)\n#define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000060 */\n#define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                              /*!< REV_IN Reverse Input Data bits */\n#define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */\n#define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */\n#define CRC_CR_REV_OUT_Pos       (7U)\n#define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                  /*!< 0x00000080 */\n#define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                             /*!< REV_OUT Reverse Output Data bits */\n\n/*******************  Bit definition for CRC_INIT register  *******************/\n#define CRC_INIT_INIT_Pos        (0U)\n#define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)            /*!< 0xFFFFFFFF */\n#define CRC_INIT_INIT            CRC_INIT_INIT_Msk                              /*!< Initial CRC value bits */\n\n/*******************  Bit definition for CRC_POL register  ********************/\n#define CRC_POL_POL_Pos          (0U)\n#define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)              /*!< 0xFFFFFFFF */\n#define CRC_POL_POL              CRC_POL_POL_Msk                                /*!< Coefficients of the polynomial */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                Debug MCU                                   */\n/*                                                                            */\n/******************************************************************************/\n\n/********************************* DEVICE ID ********************************/\n#define DEV_ID 0x453UL\n\n/********************  Bit definition for DBG_IDCODE register  *************/\n#define DBG_IDCODE_DEV_ID_Pos                          (0U)\n#define DBG_IDCODE_DEV_ID_Msk                          (0xFFFUL << DBG_IDCODE_DEV_ID_Pos)  /*!< 0x00000FFF */\n#define DBG_IDCODE_DEV_ID                              DBG_IDCODE_DEV_ID_Msk\n#define DBG_IDCODE_REV_ID_Pos                          (16U)\n#define DBG_IDCODE_REV_ID_Msk                          (0xFFFFUL << DBG_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */\n#define DBG_IDCODE_REV_ID                              DBG_IDCODE_REV_ID_Msk\n\n/********************  Bit definition for DBG_CR register  *****************/\n#define DBG_CR_DBG_STOP_Pos                            (1U)\n#define DBG_CR_DBG_STOP_Msk                            (0x1UL << DBG_CR_DBG_STOP_Pos)      /*!< 0x00000002 */\n#define DBG_CR_DBG_STOP                                DBG_CR_DBG_STOP_Msk\n#define DBG_CR_DBG_STANDBY_Pos                         (2U)\n#define DBG_CR_DBG_STANDBY_Msk                         (0x1UL << DBG_CR_DBG_STANDBY_Pos)   /*!< 0x00000004 */\n#define DBG_CR_DBG_STANDBY                             DBG_CR_DBG_STANDBY_Msk\n\n/********************  Bit definition for DBG_APB_FZ1 register  ***********/\n#define DBG_APB_FZ1_DBG_TIM3_STOP_Pos                  (1U)\n#define DBG_APB_FZ1_DBG_TIM3_STOP_Msk                  (0x1UL << DBG_APB_FZ1_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */\n#define DBG_APB_FZ1_DBG_TIM3_STOP                      DBG_APB_FZ1_DBG_TIM3_STOP_Msk\n#define DBG_APB_FZ1_DBG_RTC_STOP_Pos                   (10U)\n#define DBG_APB_FZ1_DBG_RTC_STOP_Msk                   (0x1UL << DBG_APB_FZ1_DBG_RTC_STOP_Pos)  /*!< 0x00000400 */\n#define DBG_APB_FZ1_DBG_RTC_STOP                       DBG_APB_FZ1_DBG_RTC_STOP_Msk\n#define DBG_APB_FZ1_DBG_WWDG_STOP_Pos                  (11U)\n#define DBG_APB_FZ1_DBG_WWDG_STOP_Msk                  (0x1UL << DBG_APB_FZ1_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */\n#define DBG_APB_FZ1_DBG_WWDG_STOP                      DBG_APB_FZ1_DBG_WWDG_STOP_Msk\n#define DBG_APB_FZ1_DBG_IWDG_STOP_Pos                  (12U)\n#define DBG_APB_FZ1_DBG_IWDG_STOP_Msk                  (0x1UL << DBG_APB_FZ1_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */\n#define DBG_APB_FZ1_DBG_IWDG_STOP                      DBG_APB_FZ1_DBG_IWDG_STOP_Msk\n#define DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Pos    (21U)\n#define DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Msk    (0x1UL << DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Pos) /*!< 0x00200000 */\n#define DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP        DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Msk\n\n/********************  Bit definition for DBG_APB_FZ2 register  ************/\n#define DBG_APB_FZ2_DBG_TIM1_STOP_Pos                  (11U)\n#define DBG_APB_FZ2_DBG_TIM1_STOP_Msk                  (0x1UL << DBG_APB_FZ2_DBG_TIM1_STOP_Pos)  /*!< 0x00000800 */\n#define DBG_APB_FZ2_DBG_TIM1_STOP                      DBG_APB_FZ2_DBG_TIM1_STOP_Msk\n#define DBG_APB_FZ2_DBG_TIM14_STOP_Pos                 (15U)\n#define DBG_APB_FZ2_DBG_TIM14_STOP_Msk                 (0x1UL << DBG_APB_FZ2_DBG_TIM14_STOP_Pos) /*!< 0x00008000 */\n#define DBG_APB_FZ2_DBG_TIM14_STOP                     DBG_APB_FZ2_DBG_TIM14_STOP_Msk\n#define DBG_APB_FZ2_DBG_TIM16_STOP_Pos                 (17U)\n#define DBG_APB_FZ2_DBG_TIM16_STOP_Msk                 (0x1UL << DBG_APB_FZ2_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */\n#define DBG_APB_FZ2_DBG_TIM16_STOP                     DBG_APB_FZ2_DBG_TIM16_STOP_Msk\n#define DBG_APB_FZ2_DBG_TIM17_STOP_Pos                 (18U)\n#define DBG_APB_FZ2_DBG_TIM17_STOP_Msk                 (0x1UL << DBG_APB_FZ2_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */\n#define DBG_APB_FZ2_DBG_TIM17_STOP                     DBG_APB_FZ2_DBG_TIM17_STOP_Msk\n\n/******************************************************************************/\n/*                                                                            */\n/*                           DMA Controller (DMA)                             */\n/*                                                                            */\n/******************************************************************************/\n\n/*******************  Bit definition for DMA_ISR register  ********************/\n#define DMA_ISR_GIF1_Pos       (0U)\n#define DMA_ISR_GIF1_Msk       (0x1UL << DMA_ISR_GIF1_Pos)                     /*!< 0x00000001 */\n#define DMA_ISR_GIF1           DMA_ISR_GIF1_Msk                                /*!< Channel 1 Global interrupt flag */\n#define DMA_ISR_TCIF1_Pos      (1U)\n#define DMA_ISR_TCIF1_Msk      (0x1UL << DMA_ISR_TCIF1_Pos)                    /*!< 0x00000002 */\n#define DMA_ISR_TCIF1          DMA_ISR_TCIF1_Msk                               /*!< Channel 1 Transfer Complete flag */\n#define DMA_ISR_HTIF1_Pos      (2U)\n#define DMA_ISR_HTIF1_Msk      (0x1UL << DMA_ISR_HTIF1_Pos)                    /*!< 0x00000004 */\n#define DMA_ISR_HTIF1          DMA_ISR_HTIF1_Msk                               /*!< Channel 1 Half Transfer flag */\n#define DMA_ISR_TEIF1_Pos      (3U)\n#define DMA_ISR_TEIF1_Msk      (0x1UL << DMA_ISR_TEIF1_Pos)                    /*!< 0x00000008 */\n#define DMA_ISR_TEIF1          DMA_ISR_TEIF1_Msk                               /*!< Channel 1 Transfer Error flag */\n#define DMA_ISR_GIF2_Pos       (4U)\n#define DMA_ISR_GIF2_Msk       (0x1UL << DMA_ISR_GIF2_Pos)                     /*!< 0x00000010 */\n#define DMA_ISR_GIF2           DMA_ISR_GIF2_Msk                                /*!< Channel 2 Global interrupt flag */\n#define DMA_ISR_TCIF2_Pos      (5U)\n#define DMA_ISR_TCIF2_Msk      (0x1UL << DMA_ISR_TCIF2_Pos)                    /*!< 0x00000020 */\n#define DMA_ISR_TCIF2          DMA_ISR_TCIF2_Msk                               /*!< Channel 2 Transfer Complete flag */\n#define DMA_ISR_HTIF2_Pos      (6U)\n#define DMA_ISR_HTIF2_Msk      (0x1UL << DMA_ISR_HTIF2_Pos)                    /*!< 0x00000040 */\n#define DMA_ISR_HTIF2          DMA_ISR_HTIF2_Msk                               /*!< Channel 2 Half Transfer flag */\n#define DMA_ISR_TEIF2_Pos      (7U)\n#define DMA_ISR_TEIF2_Msk      (0x1UL << DMA_ISR_TEIF2_Pos)                    /*!< 0x00000080 */\n#define DMA_ISR_TEIF2          DMA_ISR_TEIF2_Msk                               /*!< Channel 2 Transfer Error flag */\n#define DMA_ISR_GIF3_Pos       (8U)\n#define DMA_ISR_GIF3_Msk       (0x1UL << DMA_ISR_GIF3_Pos)                     /*!< 0x00000100 */\n#define DMA_ISR_GIF3           DMA_ISR_GIF3_Msk                                /*!< Channel 3 Global interrupt flag */\n#define DMA_ISR_TCIF3_Pos      (9U)\n#define DMA_ISR_TCIF3_Msk      (0x1UL << DMA_ISR_TCIF3_Pos)                    /*!< 0x00000200 */\n#define DMA_ISR_TCIF3          DMA_ISR_TCIF3_Msk                               /*!< Channel 3 Transfer Complete flag */\n#define DMA_ISR_HTIF3_Pos      (10U)\n#define DMA_ISR_HTIF3_Msk      (0x1UL << DMA_ISR_HTIF3_Pos)                    /*!< 0x00000400 */\n#define DMA_ISR_HTIF3          DMA_ISR_HTIF3_Msk                               /*!< Channel 3 Half Transfer flag */\n#define DMA_ISR_TEIF3_Pos      (11U)\n#define DMA_ISR_TEIF3_Msk      (0x1UL << DMA_ISR_TEIF3_Pos)                    /*!< 0x00000800 */\n#define DMA_ISR_TEIF3          DMA_ISR_TEIF3_Msk                               /*!< Channel 3 Transfer Error flag */\n\n/*******************  Bit definition for DMA_IFCR register  *******************/\n#define DMA_IFCR_CGIF1_Pos     (0U)\n#define DMA_IFCR_CGIF1_Msk     (0x1UL << DMA_IFCR_CGIF1_Pos)                   /*!< 0x00000001 */\n#define DMA_IFCR_CGIF1         DMA_IFCR_CGIF1_Msk                              /*!< Channel 1 Global interrupt clearr */\n#define DMA_IFCR_CTCIF1_Pos    (1U)\n#define DMA_IFCR_CTCIF1_Msk    (0x1UL << DMA_IFCR_CTCIF1_Pos)                  /*!< 0x00000002 */\n#define DMA_IFCR_CTCIF1        DMA_IFCR_CTCIF1_Msk                             /*!< Channel 1 Transfer Complete clear */\n#define DMA_IFCR_CHTIF1_Pos    (2U)\n#define DMA_IFCR_CHTIF1_Msk    (0x1UL << DMA_IFCR_CHTIF1_Pos)                  /*!< 0x00000004 */\n#define DMA_IFCR_CHTIF1        DMA_IFCR_CHTIF1_Msk                             /*!< Channel 1 Half Transfer clear */\n#define DMA_IFCR_CTEIF1_Pos    (3U)\n#define DMA_IFCR_CTEIF1_Msk    (0x1UL << DMA_IFCR_CTEIF1_Pos)                  /*!< 0x00000008 */\n#define DMA_IFCR_CTEIF1        DMA_IFCR_CTEIF1_Msk                             /*!< Channel 1 Transfer Error clear */\n#define DMA_IFCR_CGIF2_Pos     (4U)\n#define DMA_IFCR_CGIF2_Msk     (0x1UL << DMA_IFCR_CGIF2_Pos)                   /*!< 0x00000010 */\n#define DMA_IFCR_CGIF2         DMA_IFCR_CGIF2_Msk                              /*!< Channel 2 Global interrupt clear */\n#define DMA_IFCR_CTCIF2_Pos    (5U)\n#define DMA_IFCR_CTCIF2_Msk    (0x1UL << DMA_IFCR_CTCIF2_Pos)                  /*!< 0x00000020 */\n#define DMA_IFCR_CTCIF2        DMA_IFCR_CTCIF2_Msk                             /*!< Channel 2 Transfer Complete clear */\n#define DMA_IFCR_CHTIF2_Pos    (6U)\n#define DMA_IFCR_CHTIF2_Msk    (0x1UL << DMA_IFCR_CHTIF2_Pos)                  /*!< 0x00000040 */\n#define DMA_IFCR_CHTIF2        DMA_IFCR_CHTIF2_Msk                             /*!< Channel 2 Half Transfer clear */\n#define DMA_IFCR_CTEIF2_Pos    (7U)\n#define DMA_IFCR_CTEIF2_Msk    (0x1UL << DMA_IFCR_CTEIF2_Pos)                  /*!< 0x00000080 */\n#define DMA_IFCR_CTEIF2        DMA_IFCR_CTEIF2_Msk                             /*!< Channel 2 Transfer Error clear */\n#define DMA_IFCR_CGIF3_Pos     (8U)\n#define DMA_IFCR_CGIF3_Msk     (0x1UL << DMA_IFCR_CGIF3_Pos)                   /*!< 0x00000100 */\n#define DMA_IFCR_CGIF3         DMA_IFCR_CGIF3_Msk                              /*!< Channel 3 Global interrupt clear */\n#define DMA_IFCR_CTCIF3_Pos    (9U)\n#define DMA_IFCR_CTCIF3_Msk    (0x1UL << DMA_IFCR_CTCIF3_Pos)                  /*!< 0x00000200 */\n#define DMA_IFCR_CTCIF3        DMA_IFCR_CTCIF3_Msk                             /*!< Channel 3 Transfer Complete clear */\n#define DMA_IFCR_CHTIF3_Pos    (10U)\n#define DMA_IFCR_CHTIF3_Msk    (0x1UL << DMA_IFCR_CHTIF3_Pos)                  /*!< 0x00000400 */\n#define DMA_IFCR_CHTIF3        DMA_IFCR_CHTIF3_Msk                             /*!< Channel 3 Half Transfer clear */\n#define DMA_IFCR_CTEIF3_Pos    (11U)\n#define DMA_IFCR_CTEIF3_Msk    (0x1UL << DMA_IFCR_CTEIF3_Pos)                  /*!< 0x00000800 */\n#define DMA_IFCR_CTEIF3        DMA_IFCR_CTEIF3_Msk                             /*!< Channel 3 Transfer Error clear */\n#define DMA_IFCR_CGIF4_Pos     (12U)\n#define DMA_IFCR_CGIF4_Msk     (0x1UL << DMA_IFCR_CGIF4_Pos)                   /*!< 0x00001000 */\n#define DMA_IFCR_CGIF4         DMA_IFCR_CGIF4_Msk                              /*!< Channel 4 Global interrupt clear */\n#define DMA_IFCR_CTCIF4_Pos    (13U)\n#define DMA_IFCR_CTCIF4_Msk    (0x1UL << DMA_IFCR_CTCIF4_Pos)                  /*!< 0x00002000 */\n#define DMA_IFCR_CTCIF4        DMA_IFCR_CTCIF4_Msk                             /*!< Channel 4 Transfer Complete clear */\n#define DMA_IFCR_CHTIF4_Pos    (14U)\n#define DMA_IFCR_CHTIF4_Msk    (0x1UL << DMA_IFCR_CHTIF4_Pos)                  /*!< 0x00004000 */\n#define DMA_IFCR_CHTIF4        DMA_IFCR_CHTIF4_Msk                             /*!< Channel 4 Half Transfer clear */\n#define DMA_IFCR_CTEIF4_Pos    (15U)\n#define DMA_IFCR_CTEIF4_Msk    (0x1UL << DMA_IFCR_CTEIF4_Pos)                  /*!< 0x00008000 */\n#define DMA_IFCR_CTEIF4        DMA_IFCR_CTEIF4_Msk                             /*!< Channel 4 Transfer Error clear */\n\n/*******************  Bit definition for DMA_CCR register  ********************/\n#define DMA_CCR_EN_Pos         (0U)\n#define DMA_CCR_EN_Msk         (0x1UL << DMA_CCR_EN_Pos)                       /*!< 0x00000001 */\n#define DMA_CCR_EN             DMA_CCR_EN_Msk                                  /*!< Channel enable                      */\n#define DMA_CCR_TCIE_Pos       (1U)\n#define DMA_CCR_TCIE_Msk       (0x1UL << DMA_CCR_TCIE_Pos)                     /*!< 0x00000002 */\n#define DMA_CCR_TCIE           DMA_CCR_TCIE_Msk                                /*!< Transfer complete interrupt enable  */\n#define DMA_CCR_HTIE_Pos       (2U)\n#define DMA_CCR_HTIE_Msk       (0x1UL << DMA_CCR_HTIE_Pos)                     /*!< 0x00000004 */\n#define DMA_CCR_HTIE           DMA_CCR_HTIE_Msk                                /*!< Half Transfer interrupt enable      */\n#define DMA_CCR_TEIE_Pos       (3U)\n#define DMA_CCR_TEIE_Msk       (0x1UL << DMA_CCR_TEIE_Pos)                     /*!< 0x00000008 */\n#define DMA_CCR_TEIE           DMA_CCR_TEIE_Msk                                /*!< Transfer error interrupt enable     */\n#define DMA_CCR_DIR_Pos        (4U)\n#define DMA_CCR_DIR_Msk        (0x1UL << DMA_CCR_DIR_Pos)                      /*!< 0x00000010 */\n#define DMA_CCR_DIR            DMA_CCR_DIR_Msk                                 /*!< Data transfer direction             */\n#define DMA_CCR_CIRC_Pos       (5U)\n#define DMA_CCR_CIRC_Msk       (0x1UL << DMA_CCR_CIRC_Pos)                     /*!< 0x00000020 */\n#define DMA_CCR_CIRC           DMA_CCR_CIRC_Msk                                /*!< Circular mode                       */\n#define DMA_CCR_PINC_Pos       (6U)\n#define DMA_CCR_PINC_Msk       (0x1UL << DMA_CCR_PINC_Pos)                     /*!< 0x00000040 */\n#define DMA_CCR_PINC           DMA_CCR_PINC_Msk                                /*!< Peripheral increment mode           */\n#define DMA_CCR_MINC_Pos       (7U)\n#define DMA_CCR_MINC_Msk       (0x1UL << DMA_CCR_MINC_Pos)                     /*!< 0x00000080 */\n#define DMA_CCR_MINC           DMA_CCR_MINC_Msk                                /*!< Memory increment mode               */\n\n#define DMA_CCR_PSIZE_Pos      (8U)\n#define DMA_CCR_PSIZE_Msk      (0x3UL << DMA_CCR_PSIZE_Pos)                    /*!< 0x00000300 */\n#define DMA_CCR_PSIZE          DMA_CCR_PSIZE_Msk                               /*!< PSIZE[1:0] bits (Peripheral size)   */\n#define DMA_CCR_PSIZE_0        (0x1UL << DMA_CCR_PSIZE_Pos)                    /*!< 0x00000100 */\n#define DMA_CCR_PSIZE_1        (0x2UL << DMA_CCR_PSIZE_Pos)                    /*!< 0x00000200 */\n\n#define DMA_CCR_MSIZE_Pos      (10U)\n#define DMA_CCR_MSIZE_Msk      (0x3UL << DMA_CCR_MSIZE_Pos)                    /*!< 0x00000C00 */\n#define DMA_CCR_MSIZE          DMA_CCR_MSIZE_Msk                               /*!< MSIZE[1:0] bits (Memory size)       */\n#define DMA_CCR_MSIZE_0        (0x1UL << DMA_CCR_MSIZE_Pos)                    /*!< 0x00000400 */\n#define DMA_CCR_MSIZE_1        (0x2UL << DMA_CCR_MSIZE_Pos)                    /*!< 0x00000800 */\n\n#define DMA_CCR_PL_Pos         (12U)\n#define DMA_CCR_PL_Msk         (0x3UL << DMA_CCR_PL_Pos)                       /*!< 0x00003000 */\n#define DMA_CCR_PL             DMA_CCR_PL_Msk                                  /*!< PL[1:0] bits(Channel Priority level)*/\n#define DMA_CCR_PL_0           (0x1UL << DMA_CCR_PL_Pos)                       /*!< 0x00001000 */\n#define DMA_CCR_PL_1           (0x2UL << DMA_CCR_PL_Pos)                        /*!< 0x00002000 */\n\n#define DMA_CCR_MEM2MEM_Pos    (14U)\n#define DMA_CCR_MEM2MEM_Msk    (0x1UL << DMA_CCR_MEM2MEM_Pos)                  /*!< 0x00004000 */\n#define DMA_CCR_MEM2MEM        DMA_CCR_MEM2MEM_Msk                             /*!< Memory to memory mode               */\n\n/******************  Bit definition for DMA_CNDTR register  *******************/\n#define DMA_CNDTR_NDT_Pos      (0U)\n#define DMA_CNDTR_NDT_Msk      (0xFFFFUL << DMA_CNDTR_NDT_Pos)                 /*!< 0x0000FFFF */\n#define DMA_CNDTR_NDT          DMA_CNDTR_NDT_Msk                               /*!< Number of data to Transfer          */\n\n/******************  Bit definition for DMA_CPAR register  ********************/\n#define DMA_CPAR_PA_Pos        (0U)\n#define DMA_CPAR_PA_Msk        (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)               /*!< 0xFFFFFFFF */\n#define DMA_CPAR_PA            DMA_CPAR_PA_Msk                                 /*!< Peripheral Address                  */\n\n/******************  Bit definition for DMA_CMAR register  ********************/\n#define DMA_CMAR_MA_Pos        (0U)\n#define DMA_CMAR_MA_Msk        (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)               /*!< 0xFFFFFFFF */\n#define DMA_CMAR_MA            DMA_CMAR_MA_Msk                                 /*!< Memory Address                      */\n\n/******************************************************************************/\n/*                                                                            */\n/*                             DMAMUX Controller                              */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bits definition for DMAMUX_CxCR register  **************/\n#define DMAMUX_CxCR_DMAREQ_ID_Pos              (0U)\n#define DMAMUX_CxCR_DMAREQ_ID_Msk              (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x000000FF */\n#define DMAMUX_CxCR_DMAREQ_ID                  DMAMUX_CxCR_DMAREQ_ID_Msk             /*!< DMA Request ID   */\n#define DMAMUX_CxCR_DMAREQ_ID_0                (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000001 */\n#define DMAMUX_CxCR_DMAREQ_ID_1                (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000002 */\n#define DMAMUX_CxCR_DMAREQ_ID_2                (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000004 */\n#define DMAMUX_CxCR_DMAREQ_ID_3                (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000008 */\n#define DMAMUX_CxCR_DMAREQ_ID_4                (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */\n#define DMAMUX_CxCR_DMAREQ_ID_5                (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */\n#define DMAMUX_CxCR_DMAREQ_ID_6                (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */\n#define DMAMUX_CxCR_DMAREQ_ID_7                (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */\n#define DMAMUX_CxCR_SOIE_Pos                   (8U)\n#define DMAMUX_CxCR_SOIE_Msk                   (0x1UL << DMAMUX_CxCR_SOIE_Pos)  /*!< 0x00000100 */\n#define DMAMUX_CxCR_SOIE                       DMAMUX_CxCR_SOIE_Msk             /*!< Synchro overrun interrupt enable     */\n#define DMAMUX_CxCR_EGE_Pos                    (9U)\n#define DMAMUX_CxCR_EGE_Msk                    (0x1UL << DMAMUX_CxCR_EGE_Pos)   /*!< 0x00000200 */\n#define DMAMUX_CxCR_EGE                        DMAMUX_CxCR_EGE_Msk              /*!< Event generation interrupt enable    */\n#define DMAMUX_CxCR_SE_Pos                     (16U)\n#define DMAMUX_CxCR_SE_Msk                     (0x1UL << DMAMUX_CxCR_SE_Pos)    /*!< 0x00010000 */\n#define DMAMUX_CxCR_SE                         DMAMUX_CxCR_SE_Msk               /*!< Synchronization enable               */\n#define DMAMUX_CxCR_SPOL_Pos                   (17U)\n#define DMAMUX_CxCR_SPOL_Msk                   (0x3UL << DMAMUX_CxCR_SPOL_Pos)  /*!< 0x00060000 */\n#define DMAMUX_CxCR_SPOL                       DMAMUX_CxCR_SPOL_Msk             /*!< Synchronization polarity             */\n#define DMAMUX_CxCR_SPOL_0                     (0x1UL << DMAMUX_CxCR_SPOL_Pos)  /*!< 0x00020000 */\n#define DMAMUX_CxCR_SPOL_1                     (0x2UL << DMAMUX_CxCR_SPOL_Pos)  /*!< 0x00040000 */\n#define DMAMUX_CxCR_NBREQ_Pos                  (19U)\n#define DMAMUX_CxCR_NBREQ_Msk                  (0x1FUL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00F80000 */\n#define DMAMUX_CxCR_NBREQ                      DMAMUX_CxCR_NBREQ_Msk             /*!< Number of request                    */\n#define DMAMUX_CxCR_NBREQ_0                    (0x01UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00080000 */\n#define DMAMUX_CxCR_NBREQ_1                    (0x02UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00100000 */\n#define DMAMUX_CxCR_NBREQ_2                    (0x04UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00200000 */\n#define DMAMUX_CxCR_NBREQ_3                    (0x08UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00400000 */\n#define DMAMUX_CxCR_NBREQ_4                    (0x10UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00800000 */\n#define DMAMUX_CxCR_SYNC_ID_Pos                (24U)\n#define DMAMUX_CxCR_SYNC_ID_Msk                (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x1F000000 */\n#define DMAMUX_CxCR_SYNC_ID                    DMAMUX_CxCR_SYNC_ID_Msk             /*!< Synchronization ID                   */\n#define DMAMUX_CxCR_SYNC_ID_0                  (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x01000000 */\n#define DMAMUX_CxCR_SYNC_ID_1                  (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x02000000 */\n#define DMAMUX_CxCR_SYNC_ID_2                  (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x04000000 */\n#define DMAMUX_CxCR_SYNC_ID_3                  (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x08000000 */\n#define DMAMUX_CxCR_SYNC_ID_4                  (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x10000000 */\n\n/*******************  Bits definition for DMAMUX_CSR register  **************/\n#define DMAMUX_CSR_SOF0_Pos                    (0U)\n#define DMAMUX_CSR_SOF0_Msk                    (0x1UL << DMAMUX_CSR_SOF0_Pos)  /*!< 0x00000001 */\n#define DMAMUX_CSR_SOF0                        DMAMUX_CSR_SOF0_Msk             /*!< Synchronization Overrun Flag 0       */\n#define DMAMUX_CSR_SOF1_Pos                    (1U)\n#define DMAMUX_CSR_SOF1_Msk                    (0x1UL << DMAMUX_CSR_SOF1_Pos)  /*!< 0x00000002 */\n#define DMAMUX_CSR_SOF1                        DMAMUX_CSR_SOF1_Msk             /*!< Synchronization Overrun Flag 1       */\n#define DMAMUX_CSR_SOF2_Pos                    (2U)\n#define DMAMUX_CSR_SOF2_Msk                    (0x1UL << DMAMUX_CSR_SOF2_Pos)  /*!< 0x00000004 */\n#define DMAMUX_CSR_SOF2                        DMAMUX_CSR_SOF2_Msk             /*!< Synchronization Overrun Flag 2       */\n\n/********************  Bits definition for DMAMUX_CFR register  **************/\n#define DMAMUX_CFR_CSOF0_Pos                   (0U)\n#define DMAMUX_CFR_CSOF0_Msk                   (0x1UL << DMAMUX_CFR_CSOF0_Pos)  /*!< 0x00000001 */\n#define DMAMUX_CFR_CSOF0                       DMAMUX_CFR_CSOF0_Msk             /*!< Clear Overrun Flag 0                 */\n#define DMAMUX_CFR_CSOF1_Pos                   (1U)\n#define DMAMUX_CFR_CSOF1_Msk                   (0x1UL << DMAMUX_CFR_CSOF1_Pos)  /*!< 0x00000002 */\n#define DMAMUX_CFR_CSOF1                       DMAMUX_CFR_CSOF1_Msk             /*!< Clear Overrun Flag 1                 */\n#define DMAMUX_CFR_CSOF2_Pos                   (2U)\n#define DMAMUX_CFR_CSOF2_Msk                   (0x1UL << DMAMUX_CFR_CSOF2_Pos)  /*!< 0x00000004 */\n#define DMAMUX_CFR_CSOF2                       DMAMUX_CFR_CSOF2_Msk             /*!< Clear Overrun Flag 2                 */\n\n/********************  Bits definition for DMAMUX_RGxCR register  ************/\n#define DMAMUX_RGxCR_SIG_ID_Pos                (0U)\n#define DMAMUX_RGxCR_SIG_ID_Msk                (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x0000001F */\n#define DMAMUX_RGxCR_SIG_ID                    DMAMUX_RGxCR_SIG_ID_Msk             /*!< Signal ID                         */\n#define DMAMUX_RGxCR_SIG_ID_0                  (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000001 */\n#define DMAMUX_RGxCR_SIG_ID_1                  (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000002 */\n#define DMAMUX_RGxCR_SIG_ID_2                  (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000004 */\n#define DMAMUX_RGxCR_SIG_ID_3                  (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000008 */\n#define DMAMUX_RGxCR_SIG_ID_4                  (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000010 */\n#define DMAMUX_RGxCR_OIE_Pos                   (8U)\n#define DMAMUX_RGxCR_OIE_Msk                   (0x1UL << DMAMUX_RGxCR_OIE_Pos)  /*!< 0x00000100 */\n#define DMAMUX_RGxCR_OIE                       DMAMUX_RGxCR_OIE_Msk             /*!< Overrun interrupt enable             */\n#define DMAMUX_RGxCR_GE_Pos                    (16U)\n#define DMAMUX_RGxCR_GE_Msk                    (0x1UL << DMAMUX_RGxCR_GE_Pos)   /*!< 0x00010000 */\n#define DMAMUX_RGxCR_GE                        DMAMUX_RGxCR_GE_Msk              /*!< Generation enable                    */\n#define DMAMUX_RGxCR_GPOL_Pos                  (17U)\n#define DMAMUX_RGxCR_GPOL_Msk                  (0x3UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00060000 */\n#define DMAMUX_RGxCR_GPOL                      DMAMUX_RGxCR_GPOL_Msk            /*!< Generation polarity                  */\n#define DMAMUX_RGxCR_GPOL_0                    (0x1UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00020000 */\n#define DMAMUX_RGxCR_GPOL_1                    (0x2UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00040000 */\n#define DMAMUX_RGxCR_GNBREQ_Pos                (19U)\n#define DMAMUX_RGxCR_GNBREQ_Msk                (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00F80000 */\n#define DMAMUX_RGxCR_GNBREQ                    DMAMUX_RGxCR_GNBREQ_Msk             /*!< Number of request                 */\n#define DMAMUX_RGxCR_GNBREQ_0                  (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00080000 */\n#define DMAMUX_RGxCR_GNBREQ_1                  (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00100000 */\n#define DMAMUX_RGxCR_GNBREQ_2                  (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00200000 */\n#define DMAMUX_RGxCR_GNBREQ_3                  (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00400000 */\n#define DMAMUX_RGxCR_GNBREQ_4                  (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00800000 */\n\n/********************  Bits definition for DMAMUX_RGSR register  **************/\n#define DMAMUX_RGSR_OF0_Pos                    (0U)\n#define DMAMUX_RGSR_OF0_Msk                    (0x1UL << DMAMUX_RGSR_OF0_Pos)   /*!< 0x00000001 */\n#define DMAMUX_RGSR_OF0                        DMAMUX_RGSR_OF0_Msk              /*!< Overrun flag 0                       */\n#define DMAMUX_RGSR_OF1_Pos                    (1U)\n#define DMAMUX_RGSR_OF1_Msk                    (0x1UL << DMAMUX_RGSR_OF1_Pos)   /*!< 0x00000002 */\n#define DMAMUX_RGSR_OF1                        DMAMUX_RGSR_OF1_Msk              /*!< Overrun flag 1                       */\n#define DMAMUX_RGSR_OF2_Pos                    (2U)\n#define DMAMUX_RGSR_OF2_Msk                    (0x1UL << DMAMUX_RGSR_OF2_Pos)   /*!< 0x00000004 */\n#define DMAMUX_RGSR_OF2                        DMAMUX_RGSR_OF2_Msk              /*!< Overrun flag 2                       */\n#define DMAMUX_RGSR_OF3_Pos                    (3U)\n#define DMAMUX_RGSR_OF3_Msk                    (0x1UL << DMAMUX_RGSR_OF3_Pos)   /*!< 0x00000008 */\n#define DMAMUX_RGSR_OF3                        DMAMUX_RGSR_OF3_Msk              /*!< Overrun flag 3                       */\n\n/********************  Bits definition for DMAMUX_RGCFR register  **************/\n#define DMAMUX_RGCFR_COF0_Pos                  (0U)\n#define DMAMUX_RGCFR_COF0_Msk                  (0x1UL << DMAMUX_RGCFR_COF0_Pos) /*!< 0x00000001 */\n#define DMAMUX_RGCFR_COF0                      DMAMUX_RGCFR_COF0_Msk            /*!< Clear Overrun flag 0                 */\n#define DMAMUX_RGCFR_COF1_Pos                  (1U)\n#define DMAMUX_RGCFR_COF1_Msk                  (0x1UL << DMAMUX_RGCFR_COF1_Pos) /*!< 0x00000002 */\n#define DMAMUX_RGCFR_COF1                      DMAMUX_RGCFR_COF1_Msk            /*!< Clear Overrun flag 1                 */\n#define DMAMUX_RGCFR_COF2_Pos                  (2U)\n#define DMAMUX_RGCFR_COF2_Msk                  (0x1UL << DMAMUX_RGCFR_COF2_Pos) /*!< 0x00000004 */\n#define DMAMUX_RGCFR_COF2                      DMAMUX_RGCFR_COF2_Msk            /*!< Clear Overrun flag 2                 */\n#define DMAMUX_RGCFR_COF3_Pos                  (3U)\n#define DMAMUX_RGCFR_COF3_Msk                  (0x1UL << DMAMUX_RGCFR_COF3_Pos) /*!< 0x00000008 */\n#define DMAMUX_RGCFR_COF3                      DMAMUX_RGCFR_COF3_Msk            /*!< Clear Overrun flag 3                 */\n\n/*****************  Bits definition for DMAMUX_IPHW_CFGR2 register  ************/\n#define DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Pos       (0U)\n#define DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Msk       (0xFFUL << DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Pos) /*!< 0x000000FF */\n#define DMAMUX_IPHW_CFGR2_NB_EXT_REQ           DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Msk /*!< Number of external request sources   */\n\n/*****************  Bits definition for DMAMUX_IPHW_CFGR1 register  ************/\n#define DMAMUX_IPHW_CFGR1_NB_STREAMS_Pos       (0U)\n#define DMAMUX_IPHW_CFGR1_NB_STREAMS_Msk       (0xFFUL << DMAMUX_IPHW_CFGR1_NB_STREAMS_Pos) /*!< 0x000000FF */\n#define DMAMUX_IPHW_CFGR1_NB_STREAMS           DMAMUX_IPHW_CFGR1_NB_STREAMS_Msk /*!< Number of DMA streams                */\n\n#define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Pos    (8U)\n#define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Msk    (0xFFUL << DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Pos) /*!< 0x0000FF00 */\n#define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ        DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Msk /*!< Number of peripheral requests     */\n\n#define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Pos     (16U)\n#define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Msk     (0xFFUL << DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Pos) /*!< 0x00FF0000 */\n#define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG         DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Msk /*!< Number of synchronization triggers */\n\n#define DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Pos       (24U)\n#define DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Msk       (0xFFUL << DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Pos) /*!< 0xFF000000 */\n#define DMAMUX_IPHW_CFGR1_NB_REQ_GEN           DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Msk /*!< Number of request generation blocks  */\n\n/******************************************************************************/\n/*                                                                            */\n/*                    External Interrupt/Event Controller                     */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bit definition for EXTI_RTSR1 register  ******************/\n#define EXTI_RTSR1_RT0_Pos           (0U)\n#define EXTI_RTSR1_RT0_Msk           (0x1UL << EXTI_RTSR1_RT0_Pos)             /*!< 0x00000001 */\n#define EXTI_RTSR1_RT0               EXTI_RTSR1_RT0_Msk                        /*!< Rising trigger configuration for input line 0 */\n#define EXTI_RTSR1_RT1_Pos           (1U)\n#define EXTI_RTSR1_RT1_Msk           (0x1UL << EXTI_RTSR1_RT1_Pos)             /*!< 0x00000002 */\n#define EXTI_RTSR1_RT1               EXTI_RTSR1_RT1_Msk                        /*!< Rising trigger configuration for input line 1 */\n#define EXTI_RTSR1_RT2_Pos           (2U)\n#define EXTI_RTSR1_RT2_Msk           (0x1UL << EXTI_RTSR1_RT2_Pos)             /*!< 0x00000004 */\n#define EXTI_RTSR1_RT2               EXTI_RTSR1_RT2_Msk                        /*!< Rising trigger configuration for input line 2 */\n#define EXTI_RTSR1_RT3_Pos           (3U)\n#define EXTI_RTSR1_RT3_Msk           (0x1UL << EXTI_RTSR1_RT3_Pos)             /*!< 0x00000008 */\n#define EXTI_RTSR1_RT3               EXTI_RTSR1_RT3_Msk                        /*!< Rising trigger configuration for input line 3 */\n#define EXTI_RTSR1_RT4_Pos           (4U)\n#define EXTI_RTSR1_RT4_Msk           (0x1UL << EXTI_RTSR1_RT4_Pos)             /*!< 0x00000010 */\n#define EXTI_RTSR1_RT4               EXTI_RTSR1_RT4_Msk                        /*!< Rising trigger configuration for input line 4 */\n#define EXTI_RTSR1_RT5_Pos           (5U)\n#define EXTI_RTSR1_RT5_Msk           (0x1UL << EXTI_RTSR1_RT5_Pos)             /*!< 0x00000020 */\n#define EXTI_RTSR1_RT5               EXTI_RTSR1_RT5_Msk                        /*!< Rising trigger configuration for input line 5 */\n#define EXTI_RTSR1_RT6_Pos           (6U)\n#define EXTI_RTSR1_RT6_Msk           (0x1UL << EXTI_RTSR1_RT6_Pos)             /*!< 0x00000040 */\n#define EXTI_RTSR1_RT6               EXTI_RTSR1_RT6_Msk                        /*!< Rising trigger configuration for input line 6 */\n#define EXTI_RTSR1_RT7_Pos           (7U)\n#define EXTI_RTSR1_RT7_Msk           (0x1UL << EXTI_RTSR1_RT7_Pos)             /*!< 0x00000080 */\n#define EXTI_RTSR1_RT7               EXTI_RTSR1_RT7_Msk                        /*!< Rising trigger configuration for input line 7 */\n#define EXTI_RTSR1_RT8_Pos           (8U)\n#define EXTI_RTSR1_RT8_Msk           (0x1UL << EXTI_RTSR1_RT8_Pos)             /*!< 0x00000100 */\n#define EXTI_RTSR1_RT8               EXTI_RTSR1_RT8_Msk                        /*!< Rising trigger configuration for input line 8 */\n#define EXTI_RTSR1_RT9_Pos           (9U)\n#define EXTI_RTSR1_RT9_Msk           (0x1UL << EXTI_RTSR1_RT9_Pos)             /*!< 0x00000200 */\n#define EXTI_RTSR1_RT9               EXTI_RTSR1_RT9_Msk                        /*!< Rising trigger configuration for input line 9 */\n#define EXTI_RTSR1_RT10_Pos          (10U)\n#define EXTI_RTSR1_RT10_Msk          (0x1UL << EXTI_RTSR1_RT10_Pos)            /*!< 0x00000400 */\n#define EXTI_RTSR1_RT10              EXTI_RTSR1_RT10_Msk                       /*!< Rising trigger configuration for input line 10 */\n#define EXTI_RTSR1_RT11_Pos          (11U)\n#define EXTI_RTSR1_RT11_Msk          (0x1UL << EXTI_RTSR1_RT11_Pos)            /*!< 0x00000800 */\n#define EXTI_RTSR1_RT11              EXTI_RTSR1_RT11_Msk                       /*!< Rising trigger configuration for input line 11 */\n#define EXTI_RTSR1_RT12_Pos          (12U)\n#define EXTI_RTSR1_RT12_Msk          (0x1UL << EXTI_RTSR1_RT12_Pos)            /*!< 0x00001000 */\n#define EXTI_RTSR1_RT12              EXTI_RTSR1_RT12_Msk                       /*!< Rising trigger configuration for input line 12 */\n#define EXTI_RTSR1_RT13_Pos          (13U)\n#define EXTI_RTSR1_RT13_Msk          (0x1UL << EXTI_RTSR1_RT13_Pos)            /*!< 0x00002000 */\n#define EXTI_RTSR1_RT13              EXTI_RTSR1_RT13_Msk                       /*!< Rising trigger configuration for input line 13 */\n#define EXTI_RTSR1_RT14_Pos          (14U)\n#define EXTI_RTSR1_RT14_Msk          (0x1UL << EXTI_RTSR1_RT14_Pos)            /*!< 0x00004000 */\n#define EXTI_RTSR1_RT14              EXTI_RTSR1_RT14_Msk                       /*!< Rising trigger configuration for input line 14 */\n#define EXTI_RTSR1_RT15_Pos          (15U)\n#define EXTI_RTSR1_RT15_Msk          (0x1UL << EXTI_RTSR1_RT15_Pos)            /*!< 0x00008000 */\n#define EXTI_RTSR1_RT15              EXTI_RTSR1_RT15_Msk                       /*!< Rising trigger configuration for input line 15 */\n\n/******************  Bit definition for EXTI_FTSR1 register  ******************/\n#define EXTI_FTSR1_FT0_Pos           (0U)\n#define EXTI_FTSR1_FT0_Msk           (0x1UL << EXTI_FTSR1_FT0_Pos)             /*!< 0x00000001 */\n#define EXTI_FTSR1_FT0               EXTI_FTSR1_FT0_Msk                        /*!< Falling trigger configuration for input line 0 */\n#define EXTI_FTSR1_FT1_Pos           (1U)\n#define EXTI_FTSR1_FT1_Msk           (0x1UL << EXTI_FTSR1_FT1_Pos)             /*!< 0x00000002 */\n#define EXTI_FTSR1_FT1               EXTI_FTSR1_FT1_Msk                        /*!< Falling trigger configuration for input line 1 */\n#define EXTI_FTSR1_FT2_Pos           (2U)\n#define EXTI_FTSR1_FT2_Msk           (0x1UL << EXTI_FTSR1_FT2_Pos)             /*!< 0x00000004 */\n#define EXTI_FTSR1_FT2               EXTI_FTSR1_FT2_Msk                        /*!< Falling trigger configuration for input line 2 */\n#define EXTI_FTSR1_FT3_Pos           (3U)\n#define EXTI_FTSR1_FT3_Msk           (0x1UL << EXTI_FTSR1_FT3_Pos)             /*!< 0x00000008 */\n#define EXTI_FTSR1_FT3               EXTI_FTSR1_FT3_Msk                        /*!< Falling trigger configuration for input line 3 */\n#define EXTI_FTSR1_FT4_Pos           (4U)\n#define EXTI_FTSR1_FT4_Msk           (0x1UL << EXTI_FTSR1_FT4_Pos)             /*!< 0x00000010 */\n#define EXTI_FTSR1_FT4               EXTI_FTSR1_FT4_Msk                        /*!< Falling trigger configuration for input line 4 */\n#define EXTI_FTSR1_FT5_Pos           (5U)\n#define EXTI_FTSR1_FT5_Msk           (0x1UL << EXTI_FTSR1_FT5_Pos)             /*!< 0x00000020 */\n#define EXTI_FTSR1_FT5               EXTI_FTSR1_FT5_Msk                        /*!< Falling trigger configuration for input line 5 */\n#define EXTI_FTSR1_FT6_Pos           (6U)\n#define EXTI_FTSR1_FT6_Msk           (0x1UL << EXTI_FTSR1_FT6_Pos)             /*!< 0x00000040 */\n#define EXTI_FTSR1_FT6               EXTI_FTSR1_FT6_Msk                        /*!< Falling trigger configuration for input line 6 */\n#define EXTI_FTSR1_FT7_Pos           (7U)\n#define EXTI_FTSR1_FT7_Msk           (0x1UL << EXTI_FTSR1_FT7_Pos)             /*!< 0x00000080 */\n#define EXTI_FTSR1_FT7               EXTI_FTSR1_FT7_Msk                        /*!< Falling trigger configuration for input line 7 */\n#define EXTI_FTSR1_FT8_Pos           (8U)\n#define EXTI_FTSR1_FT8_Msk           (0x1UL << EXTI_FTSR1_FT8_Pos)             /*!< 0x00000100 */\n#define EXTI_FTSR1_FT8               EXTI_FTSR1_FT8_Msk                        /*!< Falling trigger configuration for input line 8 */\n#define EXTI_FTSR1_FT9_Pos           (9U)\n#define EXTI_FTSR1_FT9_Msk           (0x1UL << EXTI_FTSR1_FT9_Pos)             /*!< 0x00000200 */\n#define EXTI_FTSR1_FT9               EXTI_FTSR1_FT9_Msk                        /*!< Falling trigger configuration for input line 9 */\n#define EXTI_FTSR1_FT10_Pos          (10U)\n#define EXTI_FTSR1_FT10_Msk          (0x1UL << EXTI_FTSR1_FT10_Pos)            /*!< 0x00000400 */\n#define EXTI_FTSR1_FT10              EXTI_FTSR1_FT10_Msk                       /*!< Falling trigger configuration for input line 10 */\n#define EXTI_FTSR1_FT11_Pos          (11U)\n#define EXTI_FTSR1_FT11_Msk          (0x1UL << EXTI_FTSR1_FT11_Pos)            /*!< 0x00000800 */\n#define EXTI_FTSR1_FT11              EXTI_FTSR1_FT11_Msk                       /*!< Falling trigger configuration for input line 11 */\n#define EXTI_FTSR1_FT12_Pos          (12U)\n#define EXTI_FTSR1_FT12_Msk          (0x1UL << EXTI_FTSR1_FT12_Pos)            /*!< 0x00001000 */\n#define EXTI_FTSR1_FT12              EXTI_FTSR1_FT12_Msk                       /*!< Falling trigger configuration for input line 12 */\n#define EXTI_FTSR1_FT13_Pos          (13U)\n#define EXTI_FTSR1_FT13_Msk          (0x1UL << EXTI_FTSR1_FT13_Pos)            /*!< 0x00002000 */\n#define EXTI_FTSR1_FT13              EXTI_FTSR1_FT13_Msk                       /*!< Falling trigger configuration for input line 13 */\n#define EXTI_FTSR1_FT14_Pos          (14U)\n#define EXTI_FTSR1_FT14_Msk          (0x1UL << EXTI_FTSR1_FT14_Pos)            /*!< 0x00004000 */\n#define EXTI_FTSR1_FT14              EXTI_FTSR1_FT14_Msk                       /*!< Falling trigger configuration for input line 14 */\n#define EXTI_FTSR1_FT15_Pos          (15U)\n#define EXTI_FTSR1_FT15_Msk          (0x1UL << EXTI_FTSR1_FT15_Pos)            /*!< 0x00008000 */\n#define EXTI_FTSR1_FT15              EXTI_FTSR1_FT15_Msk                       /*!< Falling trigger configuration for input line 15 */\n\n/******************  Bit definition for EXTI_SWIER1 register  *****************/\n#define EXTI_SWIER1_SWI0_Pos         (0U)\n#define EXTI_SWIER1_SWI0_Msk         (0x1UL << EXTI_SWIER1_SWI0_Pos)           /*!< 0x00000001 */\n#define EXTI_SWIER1_SWI0             EXTI_SWIER1_SWI0_Msk                      /*!< Software Interrupt on line 0 */\n#define EXTI_SWIER1_SWI1_Pos         (1U)\n#define EXTI_SWIER1_SWI1_Msk         (0x1UL << EXTI_SWIER1_SWI1_Pos)           /*!< 0x00000002 */\n#define EXTI_SWIER1_SWI1             EXTI_SWIER1_SWI1_Msk                      /*!< Software Interrupt on line 1 */\n#define EXTI_SWIER1_SWI2_Pos         (2U)\n#define EXTI_SWIER1_SWI2_Msk         (0x1UL << EXTI_SWIER1_SWI2_Pos)           /*!< 0x00000004 */\n#define EXTI_SWIER1_SWI2             EXTI_SWIER1_SWI2_Msk                      /*!< Software Interrupt on line 2 */\n#define EXTI_SWIER1_SWI3_Pos         (3U)\n#define EXTI_SWIER1_SWI3_Msk         (0x1UL << EXTI_SWIER1_SWI3_Pos)           /*!< 0x00000008 */\n#define EXTI_SWIER1_SWI3             EXTI_SWIER1_SWI3_Msk                      /*!< Software Interrupt on line 3 */\n#define EXTI_SWIER1_SWI4_Pos         (4U)\n#define EXTI_SWIER1_SWI4_Msk         (0x1UL << EXTI_SWIER1_SWI4_Pos)           /*!< 0x00000010 */\n#define EXTI_SWIER1_SWI4             EXTI_SWIER1_SWI4_Msk                      /*!< Software Interrupt on line 4 */\n#define EXTI_SWIER1_SWI5_Pos         (5U)\n#define EXTI_SWIER1_SWI5_Msk         (0x1UL << EXTI_SWIER1_SWI5_Pos)           /*!< 0x00000020 */\n#define EXTI_SWIER1_SWI5             EXTI_SWIER1_SWI5_Msk                      /*!< Software Interrupt on line 5 */\n#define EXTI_SWIER1_SWI6_Pos         (6U)\n#define EXTI_SWIER1_SWI6_Msk         (0x1UL << EXTI_SWIER1_SWI6_Pos)           /*!< 0x00000040 */\n#define EXTI_SWIER1_SWI6             EXTI_SWIER1_SWI6_Msk                      /*!< Software Interrupt on line 6 */\n#define EXTI_SWIER1_SWI7_Pos         (7U)\n#define EXTI_SWIER1_SWI7_Msk         (0x1UL << EXTI_SWIER1_SWI7_Pos)           /*!< 0x00000080 */\n#define EXTI_SWIER1_SWI7             EXTI_SWIER1_SWI7_Msk                      /*!< Software Interrupt on line 7 */\n#define EXTI_SWIER1_SWI8_Pos         (8U)\n#define EXTI_SWIER1_SWI8_Msk         (0x1UL << EXTI_SWIER1_SWI8_Pos)           /*!< 0x00000100 */\n#define EXTI_SWIER1_SWI8             EXTI_SWIER1_SWI8_Msk                      /*!< Software Interrupt on line 8 */\n#define EXTI_SWIER1_SWI9_Pos         (9U)\n#define EXTI_SWIER1_SWI9_Msk         (0x1UL << EXTI_SWIER1_SWI9_Pos)           /*!< 0x00000200 */\n#define EXTI_SWIER1_SWI9             EXTI_SWIER1_SWI9_Msk                      /*!< Software Interrupt on line 9 */\n#define EXTI_SWIER1_SWI10_Pos        (10U)\n#define EXTI_SWIER1_SWI10_Msk        (0x1UL << EXTI_SWIER1_SWI10_Pos)          /*!< 0x00000400 */\n#define EXTI_SWIER1_SWI10            EXTI_SWIER1_SWI10_Msk                     /*!< Software Interrupt on line 10 */\n#define EXTI_SWIER1_SWI11_Pos        (11U)\n#define EXTI_SWIER1_SWI11_Msk        (0x1UL << EXTI_SWIER1_SWI11_Pos)          /*!< 0x00000800 */\n#define EXTI_SWIER1_SWI11            EXTI_SWIER1_SWI11_Msk                     /*!< Software Interrupt on line 11 */\n#define EXTI_SWIER1_SWI12_Pos        (12U)\n#define EXTI_SWIER1_SWI12_Msk        (0x1UL << EXTI_SWIER1_SWI12_Pos)          /*!< 0x00001000 */\n#define EXTI_SWIER1_SWI12            EXTI_SWIER1_SWI12_Msk                     /*!< Software Interrupt on line 12 */\n#define EXTI_SWIER1_SWI13_Pos        (13U)\n#define EXTI_SWIER1_SWI13_Msk        (0x1UL << EXTI_SWIER1_SWI13_Pos)          /*!< 0x00002000 */\n#define EXTI_SWIER1_SWI13            EXTI_SWIER1_SWI13_Msk                     /*!< Software Interrupt on line 13 */\n#define EXTI_SWIER1_SWI14_Pos        (14U)\n#define EXTI_SWIER1_SWI14_Msk        (0x1UL << EXTI_SWIER1_SWI14_Pos)          /*!< 0x00004000 */\n#define EXTI_SWIER1_SWI14            EXTI_SWIER1_SWI14_Msk                     /*!< Software Interrupt on line 14 */\n#define EXTI_SWIER1_SWI15_Pos        (15U)\n#define EXTI_SWIER1_SWI15_Msk        (0x1UL << EXTI_SWIER1_SWI15_Pos)          /*!< 0x00008000 */\n#define EXTI_SWIER1_SWI15            EXTI_SWIER1_SWI15_Msk                     /*!< Software Interrupt on line 15 */\n\n/*******************  Bit definition for EXTI_RPR1 register  ******************/\n#define EXTI_RPR1_RPIF0_Pos          (0U)\n#define EXTI_RPR1_RPIF0_Msk          (0x1UL << EXTI_RPR1_RPIF0_Pos)            /*!< 0x00000001 */\n#define EXTI_RPR1_RPIF0              EXTI_RPR1_RPIF0_Msk                       /*!< Rising Pending Interrupt Flag on line 0 */\n#define EXTI_RPR1_RPIF1_Pos          (1U)\n#define EXTI_RPR1_RPIF1_Msk          (0x1UL << EXTI_RPR1_RPIF1_Pos)            /*!< 0x00000002 */\n#define EXTI_RPR1_RPIF1              EXTI_RPR1_RPIF1_Msk                       /*!< Rising Pending Interrupt Flag on line 1 */\n#define EXTI_RPR1_RPIF2_Pos          (2U)\n#define EXTI_RPR1_RPIF2_Msk          (0x1UL << EXTI_RPR1_RPIF2_Pos)            /*!< 0x00000004 */\n#define EXTI_RPR1_RPIF2              EXTI_RPR1_RPIF2_Msk                       /*!< Rising Pending Interrupt Flag on line 2 */\n#define EXTI_RPR1_RPIF3_Pos          (3U)\n#define EXTI_RPR1_RPIF3_Msk          (0x1UL << EXTI_RPR1_RPIF3_Pos)            /*!< 0x00000008 */\n#define EXTI_RPR1_RPIF3              EXTI_RPR1_RPIF3_Msk                       /*!< Rising Pending Interrupt Flag on line 3 */\n#define EXTI_RPR1_RPIF4_Pos          (4U)\n#define EXTI_RPR1_RPIF4_Msk          (0x1UL << EXTI_RPR1_RPIF4_Pos)            /*!< 0x00000010 */\n#define EXTI_RPR1_RPIF4              EXTI_RPR1_RPIF4_Msk                       /*!< Rising Pending Interrupt Flag on line 4 */\n#define EXTI_RPR1_RPIF5_Pos          (5U)\n#define EXTI_RPR1_RPIF5_Msk          (0x1UL << EXTI_RPR1_RPIF5_Pos)            /*!< 0x00000020 */\n#define EXTI_RPR1_RPIF5              EXTI_RPR1_RPIF5_Msk                       /*!< Rising Pending Interrupt Flag on line 5 */\n#define EXTI_RPR1_RPIF6_Pos          (6U)\n#define EXTI_RPR1_RPIF6_Msk          (0x1UL << EXTI_RPR1_RPIF6_Pos)            /*!< 0x00000040 */\n#define EXTI_RPR1_RPIF6              EXTI_RPR1_RPIF6_Msk                       /*!< Rising Pending Interrupt Flag on line 6 */\n#define EXTI_RPR1_RPIF7_Pos          (7U)\n#define EXTI_RPR1_RPIF7_Msk          (0x1UL << EXTI_RPR1_RPIF7_Pos)            /*!< 0x00000080 */\n#define EXTI_RPR1_RPIF7              EXTI_RPR1_RPIF7_Msk                       /*!< Rising Pending Interrupt Flag on line 7 */\n#define EXTI_RPR1_RPIF8_Pos          (8U)\n#define EXTI_RPR1_RPIF8_Msk          (0x1UL << EXTI_RPR1_RPIF8_Pos)            /*!< 0x00000100 */\n#define EXTI_RPR1_RPIF8              EXTI_RPR1_RPIF8_Msk                       /*!< Rising Pending Interrupt Flag on line 8 */\n#define EXTI_RPR1_RPIF9_Pos          (9U)\n#define EXTI_RPR1_RPIF9_Msk          (0x1UL << EXTI_RPR1_RPIF9_Pos)            /*!< 0x00000200 */\n#define EXTI_RPR1_RPIF9              EXTI_RPR1_RPIF9_Msk                       /*!< Rising Pending Interrupt Flag on line 9 */\n#define EXTI_RPR1_RPIF10_Pos         (10U)\n#define EXTI_RPR1_RPIF10_Msk         (0x1UL << EXTI_RPR1_RPIF10_Pos)           /*!< 0x00000400 */\n#define EXTI_RPR1_RPIF10             EXTI_RPR1_RPIF10_Msk                      /*!< Rising Pending Interrupt Flag on line 10 */\n#define EXTI_RPR1_RPIF11_Pos         (11U)\n#define EXTI_RPR1_RPIF11_Msk         (0x1UL << EXTI_RPR1_RPIF11_Pos)           /*!< 0x00000800 */\n#define EXTI_RPR1_RPIF11             EXTI_RPR1_RPIF11_Msk                      /*!< Rising Pending Interrupt Flag on line 11 */\n#define EXTI_RPR1_RPIF12_Pos         (12U)\n#define EXTI_RPR1_RPIF12_Msk         (0x1UL << EXTI_RPR1_RPIF12_Pos)           /*!< 0x00001000 */\n#define EXTI_RPR1_RPIF12             EXTI_RPR1_RPIF12_Msk                      /*!< Rising Pending Interrupt Flag on line 12 */\n#define EXTI_RPR1_RPIF13_Pos         (13U)\n#define EXTI_RPR1_RPIF13_Msk         (0x1UL << EXTI_RPR1_RPIF13_Pos)           /*!< 0x00002000 */\n#define EXTI_RPR1_RPIF13             EXTI_RPR1_RPIF13_Msk                      /*!< Rising Pending Interrupt Flag on line 13 */\n#define EXTI_RPR1_RPIF14_Pos         (14U)\n#define EXTI_RPR1_RPIF14_Msk         (0x1UL << EXTI_RPR1_RPIF14_Pos)           /*!< 0x00004000 */\n#define EXTI_RPR1_RPIF14             EXTI_RPR1_RPIF14_Msk                      /*!< Rising Pending Interrupt Flag on line 14 */\n#define EXTI_RPR1_RPIF15_Pos         (15U)\n#define EXTI_RPR1_RPIF15_Msk         (0x1UL << EXTI_RPR1_RPIF15_Pos)           /*!< 0x00008000 */\n#define EXTI_RPR1_RPIF15             EXTI_RPR1_RPIF15_Msk                      /*!< Rising Pending Interrupt Flag on line 15 */\n\n\n/*******************  Bit definition for EXTI_FPR1 register  ******************/\n#define EXTI_FPR1_FPIF0_Pos          (0U)\n#define EXTI_FPR1_FPIF0_Msk          (0x1UL << EXTI_FPR1_FPIF0_Pos)            /*!< 0x00000001 */\n#define EXTI_FPR1_FPIF0              EXTI_FPR1_FPIF0_Msk                       /*!< Falling Pending Interrupt Flag on line 0 */\n#define EXTI_FPR1_FPIF1_Pos          (1U)\n#define EXTI_FPR1_FPIF1_Msk          (0x1UL << EXTI_FPR1_FPIF1_Pos)            /*!< 0x00000002 */\n#define EXTI_FPR1_FPIF1              EXTI_FPR1_FPIF1_Msk                       /*!< Falling Pending Interrupt Flag on line 1 */\n#define EXTI_FPR1_FPIF2_Pos          (2U)\n#define EXTI_FPR1_FPIF2_Msk          (0x1UL << EXTI_FPR1_FPIF2_Pos)            /*!< 0x00000004 */\n#define EXTI_FPR1_FPIF2              EXTI_FPR1_FPIF2_Msk                       /*!< Falling Pending Interrupt Flag on line 2 */\n#define EXTI_FPR1_FPIF3_Pos          (3U)\n#define EXTI_FPR1_FPIF3_Msk          (0x1UL << EXTI_FPR1_FPIF3_Pos)            /*!< 0x00000008 */\n#define EXTI_FPR1_FPIF3              EXTI_FPR1_FPIF3_Msk                       /*!< Falling Pending Interrupt Flag on line 3 */\n#define EXTI_FPR1_FPIF4_Pos          (4U)\n#define EXTI_FPR1_FPIF4_Msk          (0x1UL << EXTI_FPR1_FPIF4_Pos)            /*!< 0x00000010 */\n#define EXTI_FPR1_FPIF4              EXTI_FPR1_FPIF4_Msk                       /*!< Falling Pending Interrupt Flag on line 4 */\n#define EXTI_FPR1_FPIF5_Pos          (5U)\n#define EXTI_FPR1_FPIF5_Msk          (0x1UL << EXTI_FPR1_FPIF5_Pos)            /*!< 0x00000020 */\n#define EXTI_FPR1_FPIF5              EXTI_FPR1_FPIF5_Msk                       /*!< Falling Pending Interrupt Flag on line 5 */\n#define EXTI_FPR1_FPIF6_Pos          (6U)\n#define EXTI_FPR1_FPIF6_Msk          (0x1UL << EXTI_FPR1_FPIF6_Pos)            /*!< 0x00000040 */\n#define EXTI_FPR1_FPIF6              EXTI_FPR1_FPIF6_Msk                       /*!< Falling Pending Interrupt Flag on line 6 */\n#define EXTI_FPR1_FPIF7_Pos          (7U)\n#define EXTI_FPR1_FPIF7_Msk          (0x1UL << EXTI_FPR1_FPIF7_Pos)            /*!< 0x00000080 */\n#define EXTI_FPR1_FPIF7              EXTI_FPR1_FPIF7_Msk                       /*!< Falling Pending Interrupt Flag on line 7 */\n#define EXTI_FPR1_FPIF8_Pos          (8U)\n#define EXTI_FPR1_FPIF8_Msk          (0x1UL << EXTI_FPR1_FPIF8_Pos)            /*!< 0x00000100 */\n#define EXTI_FPR1_FPIF8              EXTI_FPR1_FPIF8_Msk                       /*!< Falling Pending Interrupt Flag on line 8 */\n#define EXTI_FPR1_FPIF9_Pos          (9U)\n#define EXTI_FPR1_FPIF9_Msk          (0x1UL << EXTI_FPR1_FPIF9_Pos)            /*!< 0x00000200 */\n#define EXTI_FPR1_FPIF9              EXTI_FPR1_FPIF9_Msk                       /*!< Falling Pending Interrupt Flag on line 9 */\n#define EXTI_FPR1_FPIF10_Pos         (10U)\n#define EXTI_FPR1_FPIF10_Msk         (0x1UL << EXTI_FPR1_FPIF10_Pos)           /*!< 0x00000400 */\n#define EXTI_FPR1_FPIF10             EXTI_FPR1_FPIF10_Msk                      /*!< Falling Pending Interrupt Flag on line 10 */\n#define EXTI_FPR1_FPIF11_Pos         (11U)\n#define EXTI_FPR1_FPIF11_Msk         (0x1UL << EXTI_FPR1_FPIF11_Pos)           /*!< 0x00000800 */\n#define EXTI_FPR1_FPIF11             EXTI_FPR1_FPIF11_Msk                      /*!< Falling Pending Interrupt Flag on line 11 */\n#define EXTI_FPR1_FPIF12_Pos         (12U)\n#define EXTI_FPR1_FPIF12_Msk         (0x1UL << EXTI_FPR1_FPIF12_Pos)           /*!< 0x00001000 */\n#define EXTI_FPR1_FPIF12             EXTI_FPR1_FPIF12_Msk                      /*!< Falling Pending Interrupt Flag on line 12 */\n#define EXTI_FPR1_FPIF13_Pos         (13U)\n#define EXTI_FPR1_FPIF13_Msk         (0x1UL << EXTI_FPR1_FPIF13_Pos)           /*!< 0x00002000 */\n#define EXTI_FPR1_FPIF13             EXTI_FPR1_FPIF13_Msk                      /*!< Falling Pending Interrupt Flag on line 13 */\n#define EXTI_FPR1_FPIF14_Pos         (14U)\n#define EXTI_FPR1_FPIF14_Msk         (0x1UL << EXTI_FPR1_FPIF14_Pos)           /*!< 0x00004000 */\n#define EXTI_FPR1_FPIF14             EXTI_FPR1_FPIF14_Msk                      /*!< Falling Pending Interrupt Flag on line 14 */\n#define EXTI_FPR1_FPIF15_Pos         (15U)\n#define EXTI_FPR1_FPIF15_Msk         (0x1UL << EXTI_FPR1_FPIF15_Pos)           /*!< 0x00008000 */\n#define EXTI_FPR1_FPIF15             EXTI_FPR1_FPIF15_Msk                      /*!< Falling Pending Interrupt Flag on line 15 */\n\n/*****************  Bit definition for EXTI_EXTICR1 register  **************/\n#define EXTI_EXTICR1_EXTI0_Pos       (0U)\n#define EXTI_EXTICR1_EXTI0_Msk       (0x7UL << EXTI_EXTICR1_EXTI0_Pos)         /*!< 0x00000007 */\n#define EXTI_EXTICR1_EXTI0           EXTI_EXTICR1_EXTI0_Msk                    /*!< EXTI 0 configuration */\n#define EXTI_EXTICR1_EXTI0_0         (0x1UL << EXTI_EXTICR1_EXTI0_Pos)         /*!< 0x00000001 */\n#define EXTI_EXTICR1_EXTI0_1         (0x2UL << EXTI_EXTICR1_EXTI0_Pos)         /*!< 0x00000002 */\n#define EXTI_EXTICR1_EXTI0_2         (0x4UL << EXTI_EXTICR1_EXTI0_Pos)         /*!< 0x00000004 */\n#define EXTI_EXTICR1_EXTI1_Pos       (8U)\n#define EXTI_EXTICR1_EXTI1_Msk       (0x7UL << EXTI_EXTICR1_EXTI1_Pos)         /*!< 0x00000700 */\n#define EXTI_EXTICR1_EXTI1           EXTI_EXTICR1_EXTI1_Msk                    /*!< EXTI 1 configuration */\n#define EXTI_EXTICR1_EXTI1_0         (0x1UL << EXTI_EXTICR1_EXTI1_Pos)         /*!< 0x00000100 */\n#define EXTI_EXTICR1_EXTI1_1         (0x2UL << EXTI_EXTICR1_EXTI1_Pos)         /*!< 0x00000200 */\n#define EXTI_EXTICR1_EXTI1_2         (0x4UL << EXTI_EXTICR1_EXTI1_Pos)         /*!< 0x00000400 */\n#define EXTI_EXTICR1_EXTI2_Pos       (16U)\n#define EXTI_EXTICR1_EXTI2_Msk       (0x7UL << EXTI_EXTICR1_EXTI2_Pos)         /*!< 0x00070000 */\n#define EXTI_EXTICR1_EXTI2           EXTI_EXTICR1_EXTI2_Msk                    /*!< EXTI 2 configuration */\n#define EXTI_EXTICR1_EXTI2_0         (0x1UL << EXTI_EXTICR1_EXTI2_Pos)         /*!< 0x00010000 */\n#define EXTI_EXTICR1_EXTI2_1         (0x2UL << EXTI_EXTICR1_EXTI2_Pos)         /*!< 0x00020000 */\n#define EXTI_EXTICR1_EXTI2_2         (0x4UL << EXTI_EXTICR1_EXTI2_Pos)         /*!< 0x00040000 */\n#define EXTI_EXTICR1_EXTI3_Pos       (24U)\n#define EXTI_EXTICR1_EXTI3_Msk       (0x7UL << EXTI_EXTICR1_EXTI3_Pos)         /*!< 0x07000000 */\n#define EXTI_EXTICR1_EXTI3           EXTI_EXTICR1_EXTI3_Msk                    /*!< EXTI 3 configuration */\n#define EXTI_EXTICR1_EXTI3_0         (0x1UL << EXTI_EXTICR1_EXTI3_Pos)         /*!< 0x01000000 */\n#define EXTI_EXTICR1_EXTI3_1         (0x2UL << EXTI_EXTICR1_EXTI3_Pos)         /*!< 0x02000000 */\n#define EXTI_EXTICR1_EXTI3_2         (0x4UL << EXTI_EXTICR1_EXTI3_Pos)         /*!< 0x04000000 */\n\n/*****************  Bit definition for EXTI_EXTICR2 register  **************/\n#define EXTI_EXTICR2_EXTI4_Pos       (0U)\n#define EXTI_EXTICR2_EXTI4_Msk       (0x7UL << EXTI_EXTICR2_EXTI4_Pos)         /*!< 0x00000007 */\n#define EXTI_EXTICR2_EXTI4           EXTI_EXTICR2_EXTI4_Msk                    /*!< EXTI 4 configuration */\n#define EXTI_EXTICR2_EXTI4_0         (0x1UL << EXTI_EXTICR2_EXTI4_Pos)         /*!< 0x00000001 */\n#define EXTI_EXTICR2_EXTI4_1         (0x2UL << EXTI_EXTICR2_EXTI4_Pos)         /*!< 0x00000002 */\n#define EXTI_EXTICR2_EXTI4_2         (0x4UL << EXTI_EXTICR2_EXTI4_Pos)         /*!< 0x00000004 */\n#define EXTI_EXTICR2_EXTI5_Pos       (8U)\n#define EXTI_EXTICR2_EXTI5_Msk       (0x7UL << EXTI_EXTICR2_EXTI5_Pos)         /*!< 0x00000700 */\n#define EXTI_EXTICR2_EXTI5           EXTI_EXTICR2_EXTI5_Msk                    /*!< EXTI 5 configuration */\n#define EXTI_EXTICR2_EXTI5_0         (0x1UL << EXTI_EXTICR2_EXTI5_Pos)         /*!< 0x00000100 */\n#define EXTI_EXTICR2_EXTI5_1         (0x2UL << EXTI_EXTICR2_EXTI5_Pos)         /*!< 0x00000200 */\n#define EXTI_EXTICR2_EXTI5_2         (0x4UL << EXTI_EXTICR2_EXTI5_Pos)         /*!< 0x00000400 */\n#define EXTI_EXTICR2_EXTI6_Pos       (16U)\n#define EXTI_EXTICR2_EXTI6_Msk       (0x7UL << EXTI_EXTICR2_EXTI6_Pos)         /*!< 0x00070000 */\n#define EXTI_EXTICR2_EXTI6           EXTI_EXTICR2_EXTI6_Msk                    /*!< EXTI 6 configuration */\n#define EXTI_EXTICR2_EXTI6_0         (0x1UL << EXTI_EXTICR2_EXTI6_Pos)         /*!< 0x00010000 */\n#define EXTI_EXTICR2_EXTI6_1         (0x2UL << EXTI_EXTICR2_EXTI6_Pos)         /*!< 0x00020000 */\n#define EXTI_EXTICR2_EXTI6_2         (0x4UL << EXTI_EXTICR2_EXTI6_Pos)         /*!< 0x00040000 */\n#define EXTI_EXTICR2_EXTI7_Pos       (24U)\n#define EXTI_EXTICR2_EXTI7_Msk       (0x7UL << EXTI_EXTICR2_EXTI7_Pos)         /*!< 0x07000000 */\n#define EXTI_EXTICR2_EXTI7           EXTI_EXTICR2_EXTI7_Msk                    /*!< EXTI 7 configuration */\n#define EXTI_EXTICR2_EXTI7_0         (0x1UL << EXTI_EXTICR2_EXTI7_Pos)         /*!< 0x01000000 */\n#define EXTI_EXTICR2_EXTI7_1         (0x2UL << EXTI_EXTICR2_EXTI7_Pos)         /*!< 0x02000000 */\n#define EXTI_EXTICR2_EXTI7_2         (0x4UL << EXTI_EXTICR2_EXTI7_Pos)         /*!< 0x04000000 */\n\n/*****************  Bit definition for EXTI_EXTICR3 register  **************/\n#define EXTI_EXTICR3_EXTI8_Pos       (0U)\n#define EXTI_EXTICR3_EXTI8_Msk       (0x7UL << EXTI_EXTICR3_EXTI8_Pos)         /*!< 0x00000007 */\n#define EXTI_EXTICR3_EXTI8           EXTI_EXTICR3_EXTI8_Msk                    /*!< EXTI 8 configuration */\n#define EXTI_EXTICR3_EXTI8_0         (0x1UL << EXTI_EXTICR3_EXTI8_Pos)         /*!< 0x00000001 */\n#define EXTI_EXTICR3_EXTI8_1         (0x2UL << EXTI_EXTICR3_EXTI8_Pos)         /*!< 0x00000002 */\n#define EXTI_EXTICR3_EXTI8_2         (0x4UL << EXTI_EXTICR3_EXTI8_Pos)         /*!< 0x00000004 */\n#define EXTI_EXTICR3_EXTI9_Pos       (8U)\n#define EXTI_EXTICR3_EXTI9_Msk       (0x7UL << EXTI_EXTICR3_EXTI9_Pos)         /*!< 0x00000700 */\n#define EXTI_EXTICR3_EXTI9           EXTI_EXTICR3_EXTI9_Msk                    /*!< EXTI 9 configuration */\n#define EXTI_EXTICR3_EXTI9_0         (0x1UL << EXTI_EXTICR3_EXTI9_Pos)         /*!< 0x00000100 */\n#define EXTI_EXTICR3_EXTI9_1         (0x2UL << EXTI_EXTICR3_EXTI9_Pos)         /*!< 0x00000200 */\n#define EXTI_EXTICR3_EXTI9_2         (0x4UL << EXTI_EXTICR3_EXTI9_Pos)         /*!< 0x00000400 */\n#define EXTI_EXTICR3_EXTI10_Pos      (16U)\n#define EXTI_EXTICR3_EXTI10_Msk      (0x7UL << EXTI_EXTICR3_EXTI10_Pos)        /*!< 0x00070000 */\n#define EXTI_EXTICR3_EXTI10          EXTI_EXTICR3_EXTI10_Msk                   /*!< EXTI 10 configuration */\n#define EXTI_EXTICR3_EXTI10_0        (0x1UL << EXTI_EXTICR3_EXTI10_Pos)        /*!< 0x00010000 */\n#define EXTI_EXTICR3_EXTI10_1        (0x2UL << EXTI_EXTICR3_EXTI10_Pos)        /*!< 0x00020000 */\n#define EXTI_EXTICR3_EXTI10_2        (0x4UL << EXTI_EXTICR3_EXTI10_Pos)        /*!< 0x00040000 */\n#define EXTI_EXTICR3_EXTI11_Pos      (24U)\n#define EXTI_EXTICR3_EXTI11_Msk      (0x7UL << EXTI_EXTICR3_EXTI11_Pos)        /*!< 0x07000000 */\n#define EXTI_EXTICR3_EXTI11          EXTI_EXTICR3_EXTI11_Msk                   /*!< EXTI 11 configuration */\n#define EXTI_EXTICR3_EXTI11_0        (0x1UL << EXTI_EXTICR3_EXTI11_Pos)        /*!< 0x01000000 */\n#define EXTI_EXTICR3_EXTI11_1        (0x2UL << EXTI_EXTICR3_EXTI11_Pos)        /*!< 0x02000000 */\n#define EXTI_EXTICR3_EXTI11_2        (0x4UL << EXTI_EXTICR3_EXTI11_Pos)        /*!< 0x04000000 */\n\n/*****************  Bit definition for EXTI_EXTICR4 register  **************/\n#define EXTI_EXTICR4_EXTI12_Pos      (0U)\n#define EXTI_EXTICR4_EXTI12_Msk      (0x7UL << EXTI_EXTICR4_EXTI12_Pos)        /*!< 0x00000007 */\n#define EXTI_EXTICR4_EXTI12          EXTI_EXTICR4_EXTI12_Msk                   /*!< EXTI 12 configuration */\n#define EXTI_EXTICR4_EXTI12_0        (0x1UL << EXTI_EXTICR4_EXTI12_Pos)        /*!< 0x00000001 */\n#define EXTI_EXTICR4_EXTI12_1        (0x2UL << EXTI_EXTICR4_EXTI12_Pos)        /*!< 0x00000002 */\n#define EXTI_EXTICR4_EXTI12_2        (0x4UL << EXTI_EXTICR4_EXTI12_Pos)        /*!< 0x00000004 */\n#define EXTI_EXTICR4_EXTI13_Pos      (8U)\n#define EXTI_EXTICR4_EXTI13_Msk      (0x7UL << EXTI_EXTICR4_EXTI13_Pos)        /*!< 0x00000700 */\n#define EXTI_EXTICR4_EXTI13          EXTI_EXTICR4_EXTI13_Msk                   /*!< EXTI 13 configuration */\n#define EXTI_EXTICR4_EXTI13_0        (0x1UL << EXTI_EXTICR4_EXTI13_Pos)        /*!< 0x00000100 */\n#define EXTI_EXTICR4_EXTI13_1        (0x2UL << EXTI_EXTICR4_EXTI13_Pos)       /*!< 0x00000200 */\n#define EXTI_EXTICR4_EXTI13_2        (0x4UL << EXTI_EXTICR4_EXTI13_Pos)         /*!< 0x00000400 */\n#define EXTI_EXTICR4_EXTI14_Pos      (16U)\n#define EXTI_EXTICR4_EXTI14_Msk      (0x7UL << EXTI_EXTICR4_EXTI14_Pos)        /*!< 0x00070000 */\n#define EXTI_EXTICR4_EXTI14          EXTI_EXTICR4_EXTI14_Msk                   /*!< EXTI 14 configuration */\n#define EXTI_EXTICR4_EXTI14_0        (0x1UL << EXTI_EXTICR4_EXTI14_Pos)        /*!< 0x00010000 */\n#define EXTI_EXTICR4_EXTI14_1        (0x2UL << EXTI_EXTICR4_EXTI14_Pos)        /*!< 0x00020000 */\n#define EXTI_EXTICR4_EXTI14_2        (0x4UL << EXTI_EXTICR4_EXTI14_Pos)        /*!< 0x00040000 */\n#define EXTI_EXTICR4_EXTI15_Pos      (24U)\n#define EXTI_EXTICR4_EXTI15_Msk      (0x7UL << EXTI_EXTICR4_EXTI15_Pos)        /*!< 0x07000000 */\n#define EXTI_EXTICR4_EXTI15          EXTI_EXTICR4_EXTI15_Msk                   /*!< EXTI 15 configuration */\n#define EXTI_EXTICR4_EXTI15_0        (0x1UL << EXTI_EXTICR4_EXTI15_Pos)        /*!< 0x01000000 */\n#define EXTI_EXTICR4_EXTI15_1        (0x2UL << EXTI_EXTICR4_EXTI15_Pos)        /*!< 0x02000000 */\n#define EXTI_EXTICR4_EXTI15_2        (0x4UL << EXTI_EXTICR4_EXTI15_Pos)        /*!< 0x04000000 */\n\n/*******************  Bit definition for EXTI_IMR1 register  ******************/\n#define EXTI_IMR1_IM0_Pos            (0U)\n#define EXTI_IMR1_IM0_Msk            (0x1UL << EXTI_IMR1_IM0_Pos)              /*!< 0x00000001 */\n#define EXTI_IMR1_IM0                EXTI_IMR1_IM0_Msk                         /*!< Interrupt Mask on line 0 */\n#define EXTI_IMR1_IM1_Pos            (1U)\n#define EXTI_IMR1_IM1_Msk            (0x1UL << EXTI_IMR1_IM1_Pos)              /*!< 0x00000002 */\n#define EXTI_IMR1_IM1                EXTI_IMR1_IM1_Msk                         /*!< Interrupt Mask on line 1 */\n#define EXTI_IMR1_IM2_Pos            (2U)\n#define EXTI_IMR1_IM2_Msk            (0x1UL << EXTI_IMR1_IM2_Pos)              /*!< 0x00000004 */\n#define EXTI_IMR1_IM2                EXTI_IMR1_IM2_Msk                         /*!< Interrupt Mask on line 2 */\n#define EXTI_IMR1_IM3_Pos            (3U)\n#define EXTI_IMR1_IM3_Msk            (0x1UL << EXTI_IMR1_IM3_Pos)              /*!< 0x00000008 */\n#define EXTI_IMR1_IM3                EXTI_IMR1_IM3_Msk                         /*!< Interrupt Mask on line 3 */\n#define EXTI_IMR1_IM4_Pos            (4U)\n#define EXTI_IMR1_IM4_Msk            (0x1UL << EXTI_IMR1_IM4_Pos)              /*!< 0x00000010 */\n#define EXTI_IMR1_IM4                EXTI_IMR1_IM4_Msk                         /*!< Interrupt Mask on line 4 */\n#define EXTI_IMR1_IM5_Pos            (5U)\n#define EXTI_IMR1_IM5_Msk            (0x1UL << EXTI_IMR1_IM5_Pos)              /*!< 0x00000020 */\n#define EXTI_IMR1_IM5                EXTI_IMR1_IM5_Msk                         /*!< Interrupt Mask on line 5 */\n#define EXTI_IMR1_IM6_Pos            (6U)\n#define EXTI_IMR1_IM6_Msk            (0x1UL << EXTI_IMR1_IM6_Pos)              /*!< 0x00000040 */\n#define EXTI_IMR1_IM6                EXTI_IMR1_IM6_Msk                         /*!< Interrupt Mask on line 6 */\n#define EXTI_IMR1_IM7_Pos            (7U)\n#define EXTI_IMR1_IM7_Msk            (0x1UL << EXTI_IMR1_IM7_Pos)              /*!< 0x00000080 */\n#define EXTI_IMR1_IM7                EXTI_IMR1_IM7_Msk                         /*!< Interrupt Mask on line 7 */\n#define EXTI_IMR1_IM8_Pos            (8U)\n#define EXTI_IMR1_IM8_Msk            (0x1UL << EXTI_IMR1_IM8_Pos)              /*!< 0x00000100 */\n#define EXTI_IMR1_IM8                EXTI_IMR1_IM8_Msk                         /*!< Interrupt Mask on line 8 */\n#define EXTI_IMR1_IM9_Pos            (9U)\n#define EXTI_IMR1_IM9_Msk            (0x1UL << EXTI_IMR1_IM9_Pos)              /*!< 0x00000200 */\n#define EXTI_IMR1_IM9                EXTI_IMR1_IM9_Msk                         /*!< Interrupt Mask on line 9 */\n#define EXTI_IMR1_IM10_Pos           (10U)\n#define EXTI_IMR1_IM10_Msk           (0x1UL << EXTI_IMR1_IM10_Pos)             /*!< 0x00000400 */\n#define EXTI_IMR1_IM10               EXTI_IMR1_IM10_Msk                        /*!< Interrupt Mask on line 10 */\n#define EXTI_IMR1_IM11_Pos           (11U)\n#define EXTI_IMR1_IM11_Msk           (0x1UL << EXTI_IMR1_IM11_Pos)             /*!< 0x00000800 */\n#define EXTI_IMR1_IM11               EXTI_IMR1_IM11_Msk                        /*!< Interrupt Mask on line 11 */\n#define EXTI_IMR1_IM12_Pos           (12U)\n#define EXTI_IMR1_IM12_Msk           (0x1UL << EXTI_IMR1_IM12_Pos)             /*!< 0x00001000 */\n#define EXTI_IMR1_IM12               EXTI_IMR1_IM12_Msk                        /*!< Interrupt Mask on line 12 */\n#define EXTI_IMR1_IM13_Pos           (13U)\n#define EXTI_IMR1_IM13_Msk           (0x1UL << EXTI_IMR1_IM13_Pos)             /*!< 0x00002000 */\n#define EXTI_IMR1_IM13               EXTI_IMR1_IM13_Msk                        /*!< Interrupt Mask on line 13 */\n#define EXTI_IMR1_IM14_Pos           (14U)\n#define EXTI_IMR1_IM14_Msk           (0x1UL << EXTI_IMR1_IM14_Pos)             /*!< 0x00004000 */\n#define EXTI_IMR1_IM14               EXTI_IMR1_IM14_Msk                        /*!< Interrupt Mask on line 14 */\n#define EXTI_IMR1_IM15_Pos           (15U)\n#define EXTI_IMR1_IM15_Msk           (0x1UL << EXTI_IMR1_IM15_Pos)             /*!< 0x00008000 */\n#define EXTI_IMR1_IM15               EXTI_IMR1_IM15_Msk                        /*!< Interrupt Mask on line 15 */\n#define EXTI_IMR1_IM16_Pos           (16U)\n#define EXTI_IMR1_IM16_Msk           (0x1UL << EXTI_IMR1_IM16_Pos)             /*!< 0x00010000 */\n#define EXTI_IMR1_IM16               EXTI_IMR1_IM16_Msk                        /*!< Interrupt Mask on line 16 */\n#define EXTI_IMR1_IM17_Pos           (17U)\n#define EXTI_IMR1_IM17_Msk           (0x1UL << EXTI_IMR1_IM17_Pos)             /*!< 0x00020000 */\n#define EXTI_IMR1_IM17               EXTI_IMR1_IM17_Msk                        /*!< Interrupt Mask on line 17 */\n#define EXTI_IMR1_IM18_Pos           (18U)\n#define EXTI_IMR1_IM18_Msk           (0x1UL << EXTI_IMR1_IM18_Pos)             /*!< 0x00040000 */\n#define EXTI_IMR1_IM18               EXTI_IMR1_IM18_Msk                        /*!< Interrupt Mask on line 18 */\n#define EXTI_IMR1_IM19_Pos           (19U)\n#define EXTI_IMR1_IM19_Msk           (0x1UL << EXTI_IMR1_IM19_Pos)             /*!< 0x00080000 */\n#define EXTI_IMR1_IM19               EXTI_IMR1_IM19_Msk                        /*!< Interrupt Mask on line 19 */\n#define EXTI_IMR1_IM20_Pos           (20U)\n#define EXTI_IMR1_IM20_Msk           (0x1UL << EXTI_IMR1_IM20_Pos)             /*!< 0x00100000 */\n#define EXTI_IMR1_IM20               EXTI_IMR1_IM20_Msk                        /*!< Interrupt Mask on line 20 */\n#define EXTI_IMR1_IM21_Pos           (21U)\n#define EXTI_IMR1_IM21_Msk           (0x1UL << EXTI_IMR1_IM21_Pos)             /*!< 0x00200000 */\n#define EXTI_IMR1_IM21               EXTI_IMR1_IM21_Msk                        /*!< Interrupt Mask on line 21 */\n#define EXTI_IMR1_IM22_Pos           (22U)\n#define EXTI_IMR1_IM22_Msk           (0x1UL << EXTI_IMR1_IM22_Pos)             /*!< 0x00400000 */\n#define EXTI_IMR1_IM22               EXTI_IMR1_IM22_Msk                        /*!< Interrupt Mask on line 22 */\n#define EXTI_IMR1_IM23_Pos           (23U)\n#define EXTI_IMR1_IM23_Msk           (0x1UL << EXTI_IMR1_IM23_Pos)             /*!< 0x00800000 */\n#define EXTI_IMR1_IM23               EXTI_IMR1_IM23_Msk                        /*!< Interrupt Mask on line 23 */\n#define EXTI_IMR1_IM24_Pos           (24U)\n#define EXTI_IMR1_IM24_Msk           (0x1UL << EXTI_IMR1_IM24_Pos)             /*!< 0x01000000 */\n#define EXTI_IMR1_IM24               EXTI_IMR1_IM24_Msk                        /*!< Interrupt Mask on line 24 */\n#define EXTI_IMR1_IM25_Pos           (25U)\n#define EXTI_IMR1_IM25_Msk           (0x1UL << EXTI_IMR1_IM25_Pos)             /*!< 0x02000000 */\n#define EXTI_IMR1_IM25               EXTI_IMR1_IM25_Msk                        /*!< Interrupt Mask on line 25 */\n#define EXTI_IMR1_IM26_Pos           (26U)\n#define EXTI_IMR1_IM26_Msk           (0x1UL << EXTI_IMR1_IM26_Pos)             /*!< 0x04000000 */\n#define EXTI_IMR1_IM26               EXTI_IMR1_IM26_Msk                        /*!< Interrupt Mask on line 26 */\n#define EXTI_IMR1_IM27_Pos           (27U)\n#define EXTI_IMR1_IM27_Msk           (0x1UL << EXTI_IMR1_IM27_Pos)             /*!< 0x08000000 */\n#define EXTI_IMR1_IM27               EXTI_IMR1_IM27_Msk                        /*!< Interrupt Mask on line 27 */\n#define EXTI_IMR1_IM28_Pos           (28U)\n#define EXTI_IMR1_IM28_Msk           (0x1UL << EXTI_IMR1_IM28_Pos)             /*!< 0x10000000 */\n#define EXTI_IMR1_IM28               EXTI_IMR1_IM28_Msk                        /*!< Interrupt Mask on line 28 */\n#define EXTI_IMR1_IM29_Pos           (29U)\n#define EXTI_IMR1_IM29_Msk           (0x1UL << EXTI_IMR1_IM29_Pos)             /*!< 0x20000000 */\n#define EXTI_IMR1_IM29               EXTI_IMR1_IM29_Msk                        /*!< Interrupt Mask on line 29 */\n#define EXTI_IMR1_IM30_Pos           (30U)\n#define EXTI_IMR1_IM30_Msk           (0x1UL << EXTI_IMR1_IM30_Pos)             /*!< 0x40000000 */\n#define EXTI_IMR1_IM30               EXTI_IMR1_IM30_Msk                        /*!< Interrupt Mask on line 30 */\n#define EXTI_IMR1_IM31_Pos           (31U)\n#define EXTI_IMR1_IM31_Msk           (0x1UL << EXTI_IMR1_IM31_Pos)              /*!< 0x80000000 */\n#define EXTI_IMR1_IM31               EXTI_IMR1_IM31_Msk                        /*!< Interrupt Mask on line 31 */\n\n#define EXTI_IMR1_IM_Pos             (0U)\n#define EXTI_IMR1_IM_Msk             (0xFEAFFFFFUL << EXTI_IMR1_IM_Pos)        /*!< 0xFEAFFFFF */\n#define EXTI_IMR1_IM                 EXTI_IMR1_IM_Msk                          /*!< Interrupt Mask All */\n\n/*******************  Bit definition for EXTI_EMR1 register  ******************/\n#define EXTI_EMR1_EM0_Pos            (0U)\n#define EXTI_EMR1_EM0_Msk            (0x1UL << EXTI_EMR1_EM0_Pos)              /*!< 0x00000001 */\n#define EXTI_EMR1_EM0                EXTI_EMR1_EM0_Msk                         /*!< Event Mask on line 0 */\n#define EXTI_EMR1_EM1_Pos            (1U)\n#define EXTI_EMR1_EM1_Msk            (0x1UL << EXTI_EMR1_EM1_Pos)              /*!< 0x00000002 */\n#define EXTI_EMR1_EM1                EXTI_EMR1_EM1_Msk                         /*!< Event Mask on line 1 */\n#define EXTI_EMR1_EM2_Pos            (2U)\n#define EXTI_EMR1_EM2_Msk            (0x1UL << EXTI_EMR1_EM2_Pos)              /*!< 0x00000004 */\n#define EXTI_EMR1_EM2                EXTI_EMR1_EM2_Msk                         /*!< Event Mask on line 2 */\n#define EXTI_EMR1_EM3_Pos            (3U)\n#define EXTI_EMR1_EM3_Msk            (0x1UL << EXTI_EMR1_EM3_Pos)              /*!< 0x00000008 */\n#define EXTI_EMR1_EM3                EXTI_EMR1_EM3_Msk                         /*!< Event Mask on line 3 */\n#define EXTI_EMR1_EM4_Pos            (4U)\n#define EXTI_EMR1_EM4_Msk            (0x1UL << EXTI_EMR1_EM4_Pos)              /*!< 0x00000010 */\n#define EXTI_EMR1_EM4                EXTI_EMR1_EM4_Msk                         /*!< Event Mask on line 4 */\n#define EXTI_EMR1_EM5_Pos            (5U)\n#define EXTI_EMR1_EM5_Msk            (0x1UL << EXTI_EMR1_EM5_Pos)              /*!< 0x00000020 */\n#define EXTI_EMR1_EM5                EXTI_EMR1_EM5_Msk                         /*!< Event Mask on line 5 */\n#define EXTI_EMR1_EM6_Pos            (6U)\n#define EXTI_EMR1_EM6_Msk            (0x1UL << EXTI_EMR1_EM6_Pos)              /*!< 0x00000040 */\n#define EXTI_EMR1_EM6                EXTI_EMR1_EM6_Msk                         /*!< Event Mask on line 6 */\n#define EXTI_EMR1_EM7_Pos            (7U)\n#define EXTI_EMR1_EM7_Msk            (0x1UL << EXTI_EMR1_EM7_Pos)              /*!< 0x00000080 */\n#define EXTI_EMR1_EM7                EXTI_EMR1_EM7_Msk                         /*!< Event Mask on line 7 */\n#define EXTI_EMR1_EM8_Pos            (8U)\n#define EXTI_EMR1_EM8_Msk            (0x1UL << EXTI_EMR1_EM8_Pos)              /*!< 0x00000100 */\n#define EXTI_EMR1_EM8                EXTI_EMR1_EM8_Msk                         /*!< Event Mask on line 8 */\n#define EXTI_EMR1_EM9_Pos            (9U)\n#define EXTI_EMR1_EM9_Msk            (0x1UL << EXTI_EMR1_EM9_Pos)              /*!< 0x00000200 */\n#define EXTI_EMR1_EM9                EXTI_EMR1_EM9_Msk                         /*!< Event Mask on line 9 */\n#define EXTI_EMR1_EM10_Pos           (10U)\n#define EXTI_EMR1_EM10_Msk           (0x1UL << EXTI_EMR1_EM10_Pos)             /*!< 0x00000400 */\n#define EXTI_EMR1_EM10               EXTI_EMR1_EM10_Msk                        /*!< Event Mask on line 10 */\n#define EXTI_EMR1_EM11_Pos           (11U)\n#define EXTI_EMR1_EM11_Msk           (0x1UL << EXTI_EMR1_EM11_Pos)             /*!< 0x00000800 */\n#define EXTI_EMR1_EM11               EXTI_EMR1_EM11_Msk                        /*!< Event Mask on line 11 */\n#define EXTI_EMR1_EM12_Pos           (12U)\n#define EXTI_EMR1_EM12_Msk           (0x1UL << EXTI_EMR1_EM12_Pos)             /*!< 0x00001000 */\n#define EXTI_EMR1_EM12               EXTI_EMR1_EM12_Msk                        /*!< Event Mask on line 12 */\n#define EXTI_EMR1_EM13_Pos           (13U)\n#define EXTI_EMR1_EM13_Msk           (0x1UL << EXTI_EMR1_EM13_Pos)             /*!< 0x00002000 */\n#define EXTI_EMR1_EM13               EXTI_EMR1_EM13_Msk                        /*!< Event Mask on line 13 */\n#define EXTI_EMR1_EM14_Pos           (14U)\n#define EXTI_EMR1_EM14_Msk           (0x1UL << EXTI_EMR1_EM14_Pos)             /*!< 0x00004000 */\n#define EXTI_EMR1_EM14               EXTI_EMR1_EM14_Msk                        /*!< Event Mask on line 14 */\n#define EXTI_EMR1_EM15_Pos           (15U)\n#define EXTI_EMR1_EM15_Msk           (0x1UL << EXTI_EMR1_EM15_Pos)             /*!< 0x00008000 */\n#define EXTI_EMR1_EM15               EXTI_EMR1_EM15_Msk                        /*!< Event Mask on line 15 */\n\n#define EXTI_EMR1_EM16_Pos           (16U)\n#define EXTI_EMR1_EM16_Msk           (0x1UL << EXTI_EMR1_EM16_Pos)             /*!< 0x00010000 */\n#define EXTI_EMR1_EM16               EXTI_EMR1_EM16_Msk                        /*!< Event Mask on line 16 */\n#define EXTI_EMR1_EM17_Pos           (17U)\n#define EXTI_EMR1_EM17_Msk           (0x1UL << EXTI_EMR1_EM17_Pos)             /*!< 0x00020000 */\n#define EXTI_EMR1_EM17               EXTI_EMR1_EM17_Msk                        /*!< Event Mask on line 17 */\n#define EXTI_EMR1_EM18_Pos           (18U)\n#define EXTI_EMR1_EM18_Msk           (0x1UL << EXTI_EMR1_EM18_Pos)             /*!< 0x00040000 */\n#define EXTI_EMR1_EM18               EXTI_EMR1_EM18_Msk                        /*!< Event Mask on line 18 */\n#define EXTI_EMR1_EM19_Pos           (19U)\n#define EXTI_EMR1_EM19_Msk           (0x1UL << EXTI_EMR1_EM19_Pos)             /*!< 0x00080000 */\n#define EXTI_EMR1_EM19               EXTI_EMR1_EM19_Msk                        /*!< Event Mask on line 19 */\n#define EXTI_EMR1_EM21_Pos           (21U)\n#define EXTI_EMR1_EM21_Msk           (0x1UL << EXTI_EMR1_EM21_Pos)             /*!< 0x00200000 */\n#define EXTI_EMR1_EM21               EXTI_EMR1_EM21_Msk                        /*!< Event Mask on line 21 */\n#define EXTI_EMR1_EM23_Pos           (23U)\n#define EXTI_EMR1_EM23_Msk           (0x1UL << EXTI_EMR1_EM23_Pos)             /*!< 0x00800000 */\n#define EXTI_EMR1_EM23               EXTI_EMR1_EM23_Msk                        /*!< Event Mask on line 23 */\n#define EXTI_EMR1_EM25_Pos           (25U)\n#define EXTI_EMR1_EM25_Msk           (0x1UL << EXTI_EMR1_EM25_Pos)             /*!< 0x02000000 */\n#define EXTI_EMR1_EM25               EXTI_EMR1_EM25_Msk                        /*!< Event Mask on line 25 */\n#define EXTI_EMR1_EM26_Pos           (26U)\n#define EXTI_EMR1_EM26_Msk           (0x1UL << EXTI_EMR1_EM26_Pos)             /*!< 0x04000000 */\n#define EXTI_EMR1_EM26               EXTI_EMR1_EM26_Msk                        /*!< Event Mask on line 26 */\n#define EXTI_EMR1_EM27_Pos           (27U)\n#define EXTI_EMR1_EM27_Msk           (0x1UL << EXTI_EMR1_EM27_Pos)             /*!< 0x08000000 */\n#define EXTI_EMR1_EM27               EXTI_EMR1_EM27_Msk                        /*!< Event Mask on line 27 */\n#define EXTI_EMR1_EM28_Pos           (28U)\n#define EXTI_EMR1_EM28_Msk           (0x1UL << EXTI_EMR1_EM28_Pos)             /*!< 0x10000000 */\n#define EXTI_EMR1_EM28               EXTI_EMR1_EM28_Msk                        /*!< Event Mask on line 28 */\n#define EXTI_EMR1_EM29_Pos           (29U)\n#define EXTI_EMR1_EM29_Msk           (0x1UL << EXTI_EMR1_EM29_Pos)             /*!< 0x20000000 */\n#define EXTI_EMR1_EM29               EXTI_EMR1_EM29_Msk                        /*!< Event Mask on line 29 */\n#define EXTI_EMR1_EM30_Pos           (30U)\n#define EXTI_EMR1_EM30_Msk           (0x1UL << EXTI_EMR1_EM30_Pos)             /*!< 0x40000000 */\n#define EXTI_EMR1_EM30               EXTI_EMR1_EM30_Msk                        /*!< Event Mask on line 30 */\n#define EXTI_EMR1_EM31_Pos           (31U)\n#define EXTI_EMR1_EM31_Msk           (0x1UL << EXTI_EMR1_EM31_Pos)             /*!< 0x80000000 */\n#define EXTI_EMR1_EM31               EXTI_EMR1_EM31_Msk                        /*!< Event Mask on line 31 */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                    FLASH                                   */\n/*                                                                            */\n/******************************************************************************/\n\n#define GPIO_NRST_CONFIG_SUPPORT         /*!< GPIO feature available only on specific devices: Configure NRST pin */\n#define FLASH_SECURABLE_MEMORY_SUPPORT   /*!< Flash feature available only on specific devices: allow to secure memory */\n#define FLASH_PCROP_SUPPORT              /*!< Flash feature available only on specific devices: proprietary code read protection areas selected by option */\n\n/*******************  Bits definition for FLASH_ACR register  *****************/\n#define FLASH_ACR_LATENCY_Pos                  (0U)\n#define FLASH_ACR_LATENCY_Msk                  (0x7UL << FLASH_ACR_LATENCY_Pos)    /*!< 0x00000007 */\n#define FLASH_ACR_LATENCY                      FLASH_ACR_LATENCY_Msk\n#define FLASH_ACR_LATENCY_0                    (0x1UL << FLASH_ACR_LATENCY_Pos)    /*!< 0x00000001 */\n#define FLASH_ACR_LATENCY_1                    (0x2UL << FLASH_ACR_LATENCY_Pos)    /*!< 0x00000002 */\n#define FLASH_ACR_PRFTEN_Pos                   (8U)\n#define FLASH_ACR_PRFTEN_Msk                   (0x1UL << FLASH_ACR_PRFTEN_Pos)     /*!< 0x00000100 */\n#define FLASH_ACR_PRFTEN                       FLASH_ACR_PRFTEN_Msk\n#define FLASH_ACR_ICEN_Pos                     (9U)\n#define FLASH_ACR_ICEN_Msk                     (0x1UL << FLASH_ACR_ICEN_Pos)       /*!< 0x00000200 */\n#define FLASH_ACR_ICEN                         FLASH_ACR_ICEN_Msk\n#define FLASH_ACR_ICRST_Pos                    (11U)\n#define FLASH_ACR_ICRST_Msk                    (0x1UL << FLASH_ACR_ICRST_Pos)      /*!< 0x00000800 */\n#define FLASH_ACR_ICRST                        FLASH_ACR_ICRST_Msk\n#define FLASH_ACR_PROGEMPTY_Pos                (16U)\n#define FLASH_ACR_PROGEMPTY_Msk                (0x1UL << FLASH_ACR_PROGEMPTY_Pos)  /*!< 0x00010000 */\n#define FLASH_ACR_PROGEMPTY                    FLASH_ACR_PROGEMPTY_Msk\n#define FLASH_ACR_DBG_SWEN_Pos                 (18U)\n#define FLASH_ACR_DBG_SWEN_Msk                 (0x1UL << FLASH_ACR_DBG_SWEN_Pos)   /*!< 0x00040000 */\n#define FLASH_ACR_DBG_SWEN                     FLASH_ACR_DBG_SWEN_Msk\n\n/*******************  Bits definition for FLASH_SR register  ******************/\n#define FLASH_SR_EOP_Pos                       (0U)\n#define FLASH_SR_EOP_Msk                       (0x1UL << FLASH_SR_EOP_Pos)         /*!< 0x00000001 */\n#define FLASH_SR_EOP                           FLASH_SR_EOP_Msk\n#define FLASH_SR_OPERR_Pos                     (1U)\n#define FLASH_SR_OPERR_Msk                     (0x1UL << FLASH_SR_OPERR_Pos)       /*!< 0x00000002 */\n#define FLASH_SR_OPERR                         FLASH_SR_OPERR_Msk\n#define FLASH_SR_PROGERR_Pos                   (3U)\n#define FLASH_SR_PROGERR_Msk                   (0x1UL << FLASH_SR_PROGERR_Pos)     /*!< 0x00000008 */\n#define FLASH_SR_PROGERR                       FLASH_SR_PROGERR_Msk\n#define FLASH_SR_WRPERR_Pos                    (4U)\n#define FLASH_SR_WRPERR_Msk                    (0x1UL << FLASH_SR_WRPERR_Pos)      /*!< 0x00000010 */\n#define FLASH_SR_WRPERR                        FLASH_SR_WRPERR_Msk\n#define FLASH_SR_PGAERR_Pos                    (5U)\n#define FLASH_SR_PGAERR_Msk                    (0x1UL << FLASH_SR_PGAERR_Pos)      /*!< 0x00000020 */\n#define FLASH_SR_PGAERR                        FLASH_SR_PGAERR_Msk\n#define FLASH_SR_SIZERR_Pos                    (6U)\n#define FLASH_SR_SIZERR_Msk                    (0x1UL << FLASH_SR_SIZERR_Pos)      /*!< 0x00000040 */\n#define FLASH_SR_SIZERR                        FLASH_SR_SIZERR_Msk\n#define FLASH_SR_PGSERR_Pos                    (7U)\n#define FLASH_SR_PGSERR_Msk                    (0x1UL << FLASH_SR_PGSERR_Pos)      /*!< 0x00000080 */\n#define FLASH_SR_PGSERR                        FLASH_SR_PGSERR_Msk\n#define FLASH_SR_MISERR_Pos                    (8U)\n#define FLASH_SR_MISERR_Msk                    (0x1UL << FLASH_SR_MISERR_Pos)      /*!< 0x00000100 */\n#define FLASH_SR_MISERR                        FLASH_SR_MISERR_Msk\n#define FLASH_SR_FASTERR_Pos                   (9U)\n#define FLASH_SR_FASTERR_Msk                   (0x1UL << FLASH_SR_FASTERR_Pos)     /*!< 0x00000200 */\n#define FLASH_SR_FASTERR                       FLASH_SR_FASTERR_Msk\n#define FLASH_SR_RDERR_Pos                     (14U)\n#define FLASH_SR_RDERR_Msk                     (0x1UL << FLASH_SR_RDERR_Pos)       /*!< 0x00004000 */\n#define FLASH_SR_RDERR                         FLASH_SR_RDERR_Msk\n#define FLASH_SR_OPTVERR_Pos                   (15U)\n#define FLASH_SR_OPTVERR_Msk                   (0x1UL << FLASH_SR_OPTVERR_Pos)     /*!< 0x00008000 */\n#define FLASH_SR_OPTVERR                       FLASH_SR_OPTVERR_Msk\n#define FLASH_SR_BSY1_Pos                      (16U)\n#define FLASH_SR_BSY1_Msk                      (0x1UL << FLASH_SR_BSY1_Pos)        /*!< 0x00010000 */\n#define FLASH_SR_BSY1                          FLASH_SR_BSY1_Msk\n#define FLASH_SR_CFGBSY_Pos                    (18U)\n#define FLASH_SR_CFGBSY_Msk                    (0x1UL << FLASH_SR_CFGBSY_Pos)      /*!< 0x00040000 */\n#define FLASH_SR_CFGBSY                        FLASH_SR_CFGBSY_Msk\n\n/*******************  Bits definition for FLASH_CR register  ******************/\n#define FLASH_CR_PG_Pos                        (0U)\n#define FLASH_CR_PG_Msk                        (0x1UL << FLASH_CR_PG_Pos)          /*!< 0x00000001 */\n#define FLASH_CR_PG                            FLASH_CR_PG_Msk\n#define FLASH_CR_PER_Pos                       (1U)\n#define FLASH_CR_PER_Msk                       (0x1UL << FLASH_CR_PER_Pos)         /*!< 0x00000002 */\n#define FLASH_CR_PER                           FLASH_CR_PER_Msk\n#define FLASH_CR_MER1_Pos                      (2U)\n#define FLASH_CR_MER1_Msk                      (0x1UL << FLASH_CR_MER1_Pos)        /*!< 0x00000004 */\n#define FLASH_CR_MER1                          FLASH_CR_MER1_Msk\n#define FLASH_CR_PNB_Pos                       (3U)\n#define FLASH_CR_PNB_Msk                       (0xFUL << FLASH_CR_PNB_Pos)        /*!< 0x000001F8 */\n#define FLASH_CR_PNB                           FLASH_CR_PNB_Msk\n#define FLASH_CR_STRT_Pos                      (16U)\n#define FLASH_CR_STRT_Msk                      (0x1UL << FLASH_CR_STRT_Pos)        /*!< 0x00010000 */\n#define FLASH_CR_STRT                          FLASH_CR_STRT_Msk\n#define FLASH_CR_OPTSTRT_Pos                   (17U)\n#define FLASH_CR_OPTSTRT_Msk                   (0x1UL << FLASH_CR_OPTSTRT_Pos)     /*!< 0x00020000 */\n#define FLASH_CR_OPTSTRT                       FLASH_CR_OPTSTRT_Msk\n#define FLASH_CR_FSTPG_Pos                     (18U)\n#define FLASH_CR_FSTPG_Msk                     (0x1UL << FLASH_CR_FSTPG_Pos)       /*!< 0x00040000 */\n#define FLASH_CR_FSTPG                         FLASH_CR_FSTPG_Msk\n#define FLASH_CR_EOPIE_Pos                     (24U)\n#define FLASH_CR_EOPIE_Msk                     (0x1UL << FLASH_CR_EOPIE_Pos)       /*!< 0x01000000 */\n#define FLASH_CR_EOPIE                         FLASH_CR_EOPIE_Msk\n#define FLASH_CR_ERRIE_Pos                     (25U)\n#define FLASH_CR_ERRIE_Msk                     (0x1UL << FLASH_CR_ERRIE_Pos)       /*!< 0x02000000 */\n#define FLASH_CR_ERRIE                         FLASH_CR_ERRIE_Msk\n#define FLASH_CR_RDERRIE_Pos                   (26U)\n#define FLASH_CR_RDERRIE_Msk                   (0x1UL << FLASH_CR_RDERRIE_Pos)     /*!< 0x04000000 */\n#define FLASH_CR_RDERRIE                       FLASH_CR_RDERRIE_Msk\n#define FLASH_CR_OBL_LAUNCH_Pos                (27U)\n#define FLASH_CR_OBL_LAUNCH_Msk                (0x1UL << FLASH_CR_OBL_LAUNCH_Pos)  /*!< 0x08000000 */\n#define FLASH_CR_OBL_LAUNCH                    FLASH_CR_OBL_LAUNCH_Msk\n#define FLASH_CR_SEC_PROT_Pos                  (28U)\n#define FLASH_CR_SEC_PROT_Msk                  (0x1UL << FLASH_CR_SEC_PROT_Pos)    /*!< 0x10000000 */\n#define FLASH_CR_SEC_PROT                      FLASH_CR_SEC_PROT_Msk\n#define FLASH_CR_OPTLOCK_Pos                   (30U)\n#define FLASH_CR_OPTLOCK_Msk                   (0x1UL << FLASH_CR_OPTLOCK_Pos)     /*!< 0x40000000 */\n#define FLASH_CR_OPTLOCK                       FLASH_CR_OPTLOCK_Msk\n#define FLASH_CR_LOCK_Pos                      (31U)\n#define FLASH_CR_LOCK_Msk                      (0x1UL << FLASH_CR_LOCK_Pos)        /*!< 0x80000000 */\n#define FLASH_CR_LOCK                          FLASH_CR_LOCK_Msk\n\n/*******************  Bits definition for FLASH_ECCR register  ****************/\n#define FLASH_ECCR_ADDR_ECC_Pos                (0U)\n#define FLASH_ECCR_ADDR_ECC_Msk                (0x3FFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x00003FFF */\n#define FLASH_ECCR_ADDR_ECC                    FLASH_ECCR_ADDR_ECC_Msk\n#define FLASH_ECCR_SYSF_ECC_Pos                (20U)\n#define FLASH_ECCR_SYSF_ECC_Msk                (0x1UL << FLASH_ECCR_SYSF_ECC_Pos)    /*!< 0x00100000 */\n#define FLASH_ECCR_SYSF_ECC                    FLASH_ECCR_SYSF_ECC_Msk\n#define FLASH_ECCR_ECCCIE_Pos                  (24U)\n#define FLASH_ECCR_ECCCIE_Msk                  (0x1UL << FLASH_ECCR_ECCCIE_Pos)      /*!< 0x01000000 */\n#define FLASH_ECCR_ECCCIE                      FLASH_ECCR_ECCCIE_Msk\n#define FLASH_ECCR_ECCC_Pos                    (30U)\n#define FLASH_ECCR_ECCC_Msk                    (0x1UL << FLASH_ECCR_ECCC_Pos)        /*!< 0x40000000 */\n#define FLASH_ECCR_ECCC                        FLASH_ECCR_ECCC_Msk\n#define FLASH_ECCR_ECCD_Pos                    (31U)\n#define FLASH_ECCR_ECCD_Msk                    (0x1UL << FLASH_ECCR_ECCD_Pos)        /*!< 0x80000000 */\n#define FLASH_ECCR_ECCD                        FLASH_ECCR_ECCD_Msk\n\n/*******************  Bits definition for FLASH_OPTR register  ****************/\n#define FLASH_OPTR_RDP_Pos                     (0U)\n#define FLASH_OPTR_RDP_Msk                     (0xFFUL << FLASH_OPTR_RDP_Pos)        /*!< 0x000000FF */\n#define FLASH_OPTR_RDP                         FLASH_OPTR_RDP_Msk\n#define FLASH_OPTR_BOR_EN_Pos                  (8U)\n#define FLASH_OPTR_BOR_EN_Msk                  (0x1UL << FLASH_OPTR_BOR_EN_Pos)      /*!< 0x00000100 */\n#define FLASH_OPTR_BOR_EN                      FLASH_OPTR_BOR_EN_Msk\n#define FLASH_OPTR_BORF_LEV_Pos                (9U)\n#define FLASH_OPTR_BORF_LEV_Msk                (0x3UL << FLASH_OPTR_BORF_LEV_Pos)    /*!< 0x00000600 */\n#define FLASH_OPTR_BORF_LEV                    FLASH_OPTR_BORF_LEV_Msk\n#define FLASH_OPTR_BORF_LEV_0                  (0x1UL << FLASH_OPTR_BORF_LEV_Pos)    /*!< 0x00000200 */\n#define FLASH_OPTR_BORF_LEV_1                  (0x2UL << FLASH_OPTR_BORF_LEV_Pos)    /*!< 0x00000400 */\n#define FLASH_OPTR_BORR_LEV_Pos                (11U)\n#define FLASH_OPTR_BORR_LEV_Msk                (0x3UL << FLASH_OPTR_BORR_LEV_Pos)    /*!< 0x00001800 */\n#define FLASH_OPTR_BORR_LEV                    FLASH_OPTR_BORR_LEV_Msk\n#define FLASH_OPTR_BORR_LEV_0                  (0x1UL << FLASH_OPTR_BORR_LEV_Pos)    /*!< 0x00000800 */\n#define FLASH_OPTR_BORR_LEV_1                  (0x2UL << FLASH_OPTR_BORR_LEV_Pos)    /*!< 0x00001000 */\n#define FLASH_OPTR_nRST_STOP_Pos               (13U)\n#define FLASH_OPTR_nRST_STOP_Msk               (0x1UL << FLASH_OPTR_nRST_STOP_Pos)   /*!< 0x00002000 */\n#define FLASH_OPTR_nRST_STOP                   FLASH_OPTR_nRST_STOP_Msk\n#define FLASH_OPTR_nRST_STDBY_Pos              (14U)\n#define FLASH_OPTR_nRST_STDBY_Msk              (0x1UL << FLASH_OPTR_nRST_STDBY_Pos)  /*!< 0x00004000 */\n#define FLASH_OPTR_nRST_STDBY                  FLASH_OPTR_nRST_STDBY_Msk\n#define FLASH_OPTR_nRST_SHDW_Pos               (15U)\n#define FLASH_OPTR_nRST_SHDW_Msk               (0x1UL << FLASH_OPTR_nRST_SHDW_Pos)   /*!< 0x00008000 */\n#define FLASH_OPTR_nRST_SHDW                   FLASH_OPTR_nRST_SHDW_Msk\n#define FLASH_OPTR_IWDG_SW_Pos                 (16U)\n#define FLASH_OPTR_IWDG_SW_Msk                 (0x1UL << FLASH_OPTR_IWDG_SW_Pos)     /*!< 0x00010000 */\n#define FLASH_OPTR_IWDG_SW                     FLASH_OPTR_IWDG_SW_Msk\n#define FLASH_OPTR_IWDG_STOP_Pos               (17U)\n#define FLASH_OPTR_IWDG_STOP_Msk               (0x1UL << FLASH_OPTR_IWDG_STOP_Pos)   /*!< 0x00020000 */\n#define FLASH_OPTR_IWDG_STOP                   FLASH_OPTR_IWDG_STOP_Msk\n#define FLASH_OPTR_IWDG_STDBY_Pos              (18U)\n#define FLASH_OPTR_IWDG_STDBY_Msk              (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos)  /*!< 0x00040000 */\n#define FLASH_OPTR_IWDG_STDBY                  FLASH_OPTR_IWDG_STDBY_Msk\n#define FLASH_OPTR_WWDG_SW_Pos                 (19U)\n#define FLASH_OPTR_WWDG_SW_Msk                 (0x1UL << FLASH_OPTR_WWDG_SW_Pos)     /*!< 0x00080000 */\n#define FLASH_OPTR_WWDG_SW                     FLASH_OPTR_WWDG_SW_Msk\n#define FLASH_OPTR_RAM_PARITY_CHECK_Pos        (22U)\n#define FLASH_OPTR_RAM_PARITY_CHECK_Msk        (0x1UL << FLASH_OPTR_RAM_PARITY_CHECK_Pos) /*!< 0x00400000 */\n#define FLASH_OPTR_RAM_PARITY_CHECK            FLASH_OPTR_RAM_PARITY_CHECK_Msk\n#define FLASH_OPTR_nBOOT_SEL_Pos               (24U)\n#define FLASH_OPTR_nBOOT_SEL_Msk               (0x1UL << FLASH_OPTR_nBOOT_SEL_Pos)  /*!< 0x01000000 */\n#define FLASH_OPTR_nBOOT_SEL                   FLASH_OPTR_nBOOT_SEL_Msk\n#define FLASH_OPTR_nBOOT1_Pos                  (25U)\n#define FLASH_OPTR_nBOOT1_Msk                  (0x1UL << FLASH_OPTR_nBOOT1_Pos)     /*!< 0x02000000 */\n#define FLASH_OPTR_nBOOT1                      FLASH_OPTR_nBOOT1_Msk\n#define FLASH_OPTR_nBOOT0_Pos                  (26U)\n#define FLASH_OPTR_nBOOT0_Msk                  (0x1UL << FLASH_OPTR_nBOOT0_Pos)     /*!< 0x04000000 */\n#define FLASH_OPTR_nBOOT0                      FLASH_OPTR_nBOOT0_Msk\n#define FLASH_OPTR_NRST_MODE_Pos               (27U)\n#define FLASH_OPTR_NRST_MODE_Msk               (0x3UL << FLASH_OPTR_NRST_MODE_Pos)  /*!< 0x18000000 */\n#define FLASH_OPTR_NRST_MODE                   FLASH_OPTR_NRST_MODE_Msk\n#define FLASH_OPTR_NRST_MODE_0                 (0x1UL << FLASH_OPTR_NRST_MODE_Pos)  /*!< 0x08000000 */\n#define FLASH_OPTR_NRST_MODE_1                 (0x2UL << FLASH_OPTR_NRST_MODE_Pos)  /*!< 0x10000000 */\n#define FLASH_OPTR_IRHEN_Pos                   (29U)\n#define FLASH_OPTR_IRHEN_Msk                   (0x1UL << FLASH_OPTR_IRHEN_Pos)      /*!< 0x20000000 */\n#define FLASH_OPTR_IRHEN                       FLASH_OPTR_IRHEN_Msk\n\n/******************  Bits definition for FLASH_PCROP1ASR register  ************/\n#define FLASH_PCROP1ASR_PCROP1A_STRT_Pos       (0U)\n#define FLASH_PCROP1ASR_PCROP1A_STRT_Msk       (0x7FUL << FLASH_PCROP1ASR_PCROP1A_STRT_Pos)   /*!< 0x0000007F */\n#define FLASH_PCROP1ASR_PCROP1A_STRT           FLASH_PCROP1ASR_PCROP1A_STRT_Msk\n\n/******************  Bits definition for FLASH_PCROP1AER register  ************/\n#define FLASH_PCROP1AER_PCROP1A_END_Pos        (0U)\n#define FLASH_PCROP1AER_PCROP1A_END_Msk        (0x7FUL << FLASH_PCROP1AER_PCROP1A_END_Pos)    /*!< 0x0000007F */\n#define FLASH_PCROP1AER_PCROP1A_END            FLASH_PCROP1AER_PCROP1A_END_Msk\n#define FLASH_PCROP1AER_PCROP_RDP_Pos          (31U)\n#define FLASH_PCROP1AER_PCROP_RDP_Msk          (0x1UL << FLASH_PCROP1AER_PCROP_RDP_Pos)       /*!< 0x80000000 */\n#define FLASH_PCROP1AER_PCROP_RDP              FLASH_PCROP1AER_PCROP_RDP_Msk\n\n/******************  Bits definition for FLASH_WRP1AR register  ***************/\n#define FLASH_WRP1AR_WRP1A_STRT_Pos            (0U)\n#define FLASH_WRP1AR_WRP1A_STRT_Msk            (0x1FUL << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x0000001F */\n#define FLASH_WRP1AR_WRP1A_STRT                FLASH_WRP1AR_WRP1A_STRT_Msk\n#define FLASH_WRP1AR_WRP1A_END_Pos             (16U)\n#define FLASH_WRP1AR_WRP1A_END_Msk             (0x1FUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x001F0000 */\n#define FLASH_WRP1AR_WRP1A_END                 FLASH_WRP1AR_WRP1A_END_Msk\n\n/******************  Bits definition for FLASH_WRP1BR register  ***************/\n#define FLASH_WRP1BR_WRP1B_STRT_Pos            (0U)\n#define FLASH_WRP1BR_WRP1B_STRT_Msk            (0x1FUL << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x0000001F */\n#define FLASH_WRP1BR_WRP1B_STRT                FLASH_WRP1BR_WRP1B_STRT_Msk\n#define FLASH_WRP1BR_WRP1B_END_Pos             (16U)\n#define FLASH_WRP1BR_WRP1B_END_Msk             (0x1FUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x001F0000 */\n#define FLASH_WRP1BR_WRP1B_END                 FLASH_WRP1BR_WRP1B_END_Msk\n\n/******************  Bits definition for FLASH_PCROP1BSR register  ************/\n#define FLASH_PCROP1BSR_PCROP1B_STRT_Pos       (0U)\n#define FLASH_PCROP1BSR_PCROP1B_STRT_Msk       (0x7FUL << FLASH_PCROP1BSR_PCROP1B_STRT_Pos)   /*!< 0x0000007F */\n#define FLASH_PCROP1BSR_PCROP1B_STRT           FLASH_PCROP1BSR_PCROP1B_STRT_Msk\n\n/******************  Bits definition for FLASH_PCROP1BER register  ************/\n#define FLASH_PCROP1BER_PCROP1B_END_Pos        (0U)\n#define FLASH_PCROP1BER_PCROP1B_END_Msk        (0x7FUL << FLASH_PCROP1BER_PCROP1B_END_Pos)    /*!< 0x0000007F */\n#define FLASH_PCROP1BER_PCROP1B_END            FLASH_PCROP1BER_PCROP1B_END_Msk\n\n\n/******************  Bits definition for FLASH_SECR register  *****************/\n#define FLASH_SECR_SEC_SIZE_Pos                (0U)\n#define FLASH_SECR_SEC_SIZE_Msk                (0x3FUL << FLASH_SECR_SEC_SIZE_Pos) /*!< 0x0000003F */\n#define FLASH_SECR_SEC_SIZE                    FLASH_SECR_SEC_SIZE_Msk\n#define FLASH_SECR_BOOT_LOCK_Pos               (16U)\n#define FLASH_SECR_BOOT_LOCK_Msk               (0x1UL << FLASH_SECR_BOOT_LOCK_Pos) /*!< 0x00010000 */\n#define FLASH_SECR_BOOT_LOCK                   FLASH_SECR_BOOT_LOCK_Msk\n\n/******************************************************************************/\n/*                                                                            */\n/*                            General Purpose I/O                             */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bits definition for GPIO_MODER register  *****************/\n#define GPIO_MODER_MODE0_Pos           (0U)\n#define GPIO_MODER_MODE0_Msk           (0x3UL << GPIO_MODER_MODE0_Pos)          /*!< 0x00000003 */\n#define GPIO_MODER_MODE0               GPIO_MODER_MODE0_Msk\n#define GPIO_MODER_MODE0_0             (0x1UL << GPIO_MODER_MODE0_Pos)          /*!< 0x00000001 */\n#define GPIO_MODER_MODE0_1             (0x2UL << GPIO_MODER_MODE0_Pos)          /*!< 0x00000002 */\n#define GPIO_MODER_MODE1_Pos           (2U)\n#define GPIO_MODER_MODE1_Msk           (0x3UL << GPIO_MODER_MODE1_Pos)          /*!< 0x0000000C */\n#define GPIO_MODER_MODE1               GPIO_MODER_MODE1_Msk\n#define GPIO_MODER_MODE1_0             (0x1UL << GPIO_MODER_MODE1_Pos)          /*!< 0x00000004 */\n#define GPIO_MODER_MODE1_1             (0x2UL << GPIO_MODER_MODE1_Pos)          /*!< 0x00000008 */\n#define GPIO_MODER_MODE2_Pos           (4U)\n#define GPIO_MODER_MODE2_Msk           (0x3UL << GPIO_MODER_MODE2_Pos)          /*!< 0x00000030 */\n#define GPIO_MODER_MODE2               GPIO_MODER_MODE2_Msk\n#define GPIO_MODER_MODE2_0             (0x1UL << GPIO_MODER_MODE2_Pos)          /*!< 0x00000010 */\n#define GPIO_MODER_MODE2_1             (0x2UL << GPIO_MODER_MODE2_Pos)          /*!< 0x00000020 */\n#define GPIO_MODER_MODE3_Pos           (6U)\n#define GPIO_MODER_MODE3_Msk           (0x3UL << GPIO_MODER_MODE3_Pos)          /*!< 0x000000C0 */\n#define GPIO_MODER_MODE3               GPIO_MODER_MODE3_Msk\n#define GPIO_MODER_MODE3_0             (0x1UL << GPIO_MODER_MODE3_Pos)          /*!< 0x00000040 */\n#define GPIO_MODER_MODE3_1             (0x2UL << GPIO_MODER_MODE3_Pos)          /*!< 0x00000080 */\n#define GPIO_MODER_MODE4_Pos           (8U)\n#define GPIO_MODER_MODE4_Msk           (0x3UL << GPIO_MODER_MODE4_Pos)          /*!< 0x00000300 */\n#define GPIO_MODER_MODE4               GPIO_MODER_MODE4_Msk\n#define GPIO_MODER_MODE4_0             (0x1UL << GPIO_MODER_MODE4_Pos)          /*!< 0x00000100 */\n#define GPIO_MODER_MODE4_1             (0x2UL << GPIO_MODER_MODE4_Pos)          /*!< 0x00000200 */\n#define GPIO_MODER_MODE5_Pos           (10U)\n#define GPIO_MODER_MODE5_Msk           (0x3UL << GPIO_MODER_MODE5_Pos)          /*!< 0x00000C00 */\n#define GPIO_MODER_MODE5               GPIO_MODER_MODE5_Msk\n#define GPIO_MODER_MODE5_0             (0x1UL << GPIO_MODER_MODE5_Pos)          /*!< 0x00000400 */\n#define GPIO_MODER_MODE5_1             (0x2UL << GPIO_MODER_MODE5_Pos)          /*!< 0x00000800 */\n#define GPIO_MODER_MODE6_Pos           (12U)\n#define GPIO_MODER_MODE6_Msk           (0x3UL << GPIO_MODER_MODE6_Pos)          /*!< 0x00003000 */\n#define GPIO_MODER_MODE6               GPIO_MODER_MODE6_Msk\n#define GPIO_MODER_MODE6_0             (0x1UL << GPIO_MODER_MODE6_Pos)          /*!< 0x00001000 */\n#define GPIO_MODER_MODE6_1             (0x2UL << GPIO_MODER_MODE6_Pos)          /*!< 0x00002000 */\n#define GPIO_MODER_MODE7_Pos           (14U)\n#define GPIO_MODER_MODE7_Msk           (0x3UL << GPIO_MODER_MODE7_Pos)          /*!< 0x0000C000 */\n#define GPIO_MODER_MODE7               GPIO_MODER_MODE7_Msk\n#define GPIO_MODER_MODE7_0             (0x1UL << GPIO_MODER_MODE7_Pos)          /*!< 0x00004000 */\n#define GPIO_MODER_MODE7_1             (0x2UL << GPIO_MODER_MODE7_Pos)          /*!< 0x00008000 */\n#define GPIO_MODER_MODE8_Pos           (16U)\n#define GPIO_MODER_MODE8_Msk           (0x3UL << GPIO_MODER_MODE8_Pos)          /*!< 0x00030000 */\n#define GPIO_MODER_MODE8               GPIO_MODER_MODE8_Msk\n#define GPIO_MODER_MODE8_0             (0x1UL << GPIO_MODER_MODE8_Pos)          /*!< 0x00010000 */\n#define GPIO_MODER_MODE8_1             (0x2UL << GPIO_MODER_MODE8_Pos)          /*!< 0x00020000 */\n#define GPIO_MODER_MODE9_Pos           (18U)\n#define GPIO_MODER_MODE9_Msk           (0x3UL << GPIO_MODER_MODE9_Pos)          /*!< 0x000C0000 */\n#define GPIO_MODER_MODE9               GPIO_MODER_MODE9_Msk\n#define GPIO_MODER_MODE9_0             (0x1UL << GPIO_MODER_MODE9_Pos)          /*!< 0x00040000 */\n#define GPIO_MODER_MODE9_1             (0x2UL << GPIO_MODER_MODE9_Pos)          /*!< 0x00080000 */\n#define GPIO_MODER_MODE10_Pos          (20U)\n#define GPIO_MODER_MODE10_Msk          (0x3UL << GPIO_MODER_MODE10_Pos)         /*!< 0x00300000 */\n#define GPIO_MODER_MODE10              GPIO_MODER_MODE10_Msk\n#define GPIO_MODER_MODE10_0            (0x1UL << GPIO_MODER_MODE10_Pos)         /*!< 0x00100000 */\n#define GPIO_MODER_MODE10_1            (0x2UL << GPIO_MODER_MODE10_Pos)         /*!< 0x00200000 */\n#define GPIO_MODER_MODE11_Pos          (22U)\n#define GPIO_MODER_MODE11_Msk          (0x3UL << GPIO_MODER_MODE11_Pos)         /*!< 0x00C00000 */\n#define GPIO_MODER_MODE11              GPIO_MODER_MODE11_Msk\n#define GPIO_MODER_MODE11_0            (0x1UL << GPIO_MODER_MODE11_Pos)         /*!< 0x00400000 */\n#define GPIO_MODER_MODE11_1            (0x2UL << GPIO_MODER_MODE11_Pos)         /*!< 0x00800000 */\n#define GPIO_MODER_MODE12_Pos          (24U)\n#define GPIO_MODER_MODE12_Msk          (0x3UL << GPIO_MODER_MODE12_Pos)         /*!< 0x03000000 */\n#define GPIO_MODER_MODE12              GPIO_MODER_MODE12_Msk\n#define GPIO_MODER_MODE12_0            (0x1UL << GPIO_MODER_MODE12_Pos)         /*!< 0x01000000 */\n#define GPIO_MODER_MODE12_1            (0x2UL << GPIO_MODER_MODE12_Pos)         /*!< 0x02000000 */\n#define GPIO_MODER_MODE13_Pos          (26U)\n#define GPIO_MODER_MODE13_Msk          (0x3UL << GPIO_MODER_MODE13_Pos)         /*!< 0x0C000000 */\n#define GPIO_MODER_MODE13              GPIO_MODER_MODE13_Msk\n#define GPIO_MODER_MODE13_0            (0x1UL << GPIO_MODER_MODE13_Pos)         /*!< 0x04000000 */\n#define GPIO_MODER_MODE13_1            (0x2UL << GPIO_MODER_MODE13_Pos)         /*!< 0x08000000 */\n#define GPIO_MODER_MODE14_Pos          (28U)\n#define GPIO_MODER_MODE14_Msk          (0x3UL << GPIO_MODER_MODE14_Pos)         /*!< 0x30000000 */\n#define GPIO_MODER_MODE14              GPIO_MODER_MODE14_Msk\n#define GPIO_MODER_MODE14_0            (0x1UL << GPIO_MODER_MODE14_Pos)         /*!< 0x10000000 */\n#define GPIO_MODER_MODE14_1            (0x2UL << GPIO_MODER_MODE14_Pos)         /*!< 0x20000000 */\n#define GPIO_MODER_MODE15_Pos          (30U)\n#define GPIO_MODER_MODE15_Msk          (0x3UL << GPIO_MODER_MODE15_Pos)         /*!< 0xC0000000 */\n#define GPIO_MODER_MODE15              GPIO_MODER_MODE15_Msk\n#define GPIO_MODER_MODE15_0            (0x1UL << GPIO_MODER_MODE15_Pos)         /*!< 0x40000000 */\n#define GPIO_MODER_MODE15_1            (0x2UL << GPIO_MODER_MODE15_Pos)         /*!< 0x80000000 */\n\n/******************  Bits definition for GPIO_OTYPER register  ****************/\n#define GPIO_OTYPER_OT0_Pos            (0U)\n#define GPIO_OTYPER_OT0_Msk            (0x1UL << GPIO_OTYPER_OT0_Pos)           /*!< 0x00000001 */\n#define GPIO_OTYPER_OT0                GPIO_OTYPER_OT0_Msk\n#define GPIO_OTYPER_OT1_Pos            (1U)\n#define GPIO_OTYPER_OT1_Msk            (0x1UL << GPIO_OTYPER_OT1_Pos)           /*!< 0x00000002 */\n#define GPIO_OTYPER_OT1                GPIO_OTYPER_OT1_Msk\n#define GPIO_OTYPER_OT2_Pos            (2U)\n#define GPIO_OTYPER_OT2_Msk            (0x1UL << GPIO_OTYPER_OT2_Pos)           /*!< 0x00000004 */\n#define GPIO_OTYPER_OT2                GPIO_OTYPER_OT2_Msk\n#define GPIO_OTYPER_OT3_Pos            (3U)\n#define GPIO_OTYPER_OT3_Msk            (0x1UL << GPIO_OTYPER_OT3_Pos)           /*!< 0x00000008 */\n#define GPIO_OTYPER_OT3                GPIO_OTYPER_OT3_Msk\n#define GPIO_OTYPER_OT4_Pos            (4U)\n#define GPIO_OTYPER_OT4_Msk            (0x1UL << GPIO_OTYPER_OT4_Pos)           /*!< 0x00000010 */\n#define GPIO_OTYPER_OT4                GPIO_OTYPER_OT4_Msk\n#define GPIO_OTYPER_OT5_Pos            (5U)\n#define GPIO_OTYPER_OT5_Msk            (0x1UL << GPIO_OTYPER_OT5_Pos)           /*!< 0x00000020 */\n#define GPIO_OTYPER_OT5                GPIO_OTYPER_OT5_Msk\n#define GPIO_OTYPER_OT6_Pos            (6U)\n#define GPIO_OTYPER_OT6_Msk            (0x1UL << GPIO_OTYPER_OT6_Pos)           /*!< 0x00000040 */\n#define GPIO_OTYPER_OT6                GPIO_OTYPER_OT6_Msk\n#define GPIO_OTYPER_OT7_Pos            (7U)\n#define GPIO_OTYPER_OT7_Msk            (0x1UL << GPIO_OTYPER_OT7_Pos)           /*!< 0x00000080 */\n#define GPIO_OTYPER_OT7                GPIO_OTYPER_OT7_Msk\n#define GPIO_OTYPER_OT8_Pos            (8U)\n#define GPIO_OTYPER_OT8_Msk            (0x1UL << GPIO_OTYPER_OT8_Pos)           /*!< 0x00000100 */\n#define GPIO_OTYPER_OT8                GPIO_OTYPER_OT8_Msk\n#define GPIO_OTYPER_OT9_Pos            (9U)\n#define GPIO_OTYPER_OT9_Msk            (0x1UL << GPIO_OTYPER_OT9_Pos)           /*!< 0x00000200 */\n#define GPIO_OTYPER_OT9                GPIO_OTYPER_OT9_Msk\n#define GPIO_OTYPER_OT10_Pos           (10U)\n#define GPIO_OTYPER_OT10_Msk           (0x1UL << GPIO_OTYPER_OT10_Pos)          /*!< 0x00000400 */\n#define GPIO_OTYPER_OT10               GPIO_OTYPER_OT10_Msk\n#define GPIO_OTYPER_OT11_Pos           (11U)\n#define GPIO_OTYPER_OT11_Msk           (0x1UL << GPIO_OTYPER_OT11_Pos)          /*!< 0x00000800 */\n#define GPIO_OTYPER_OT11               GPIO_OTYPER_OT11_Msk\n#define GPIO_OTYPER_OT12_Pos           (12U)\n#define GPIO_OTYPER_OT12_Msk           (0x1UL << GPIO_OTYPER_OT12_Pos)          /*!< 0x00001000 */\n#define GPIO_OTYPER_OT12               GPIO_OTYPER_OT12_Msk\n#define GPIO_OTYPER_OT13_Pos           (13U)\n#define GPIO_OTYPER_OT13_Msk           (0x1UL << GPIO_OTYPER_OT13_Pos)          /*!< 0x00002000 */\n#define GPIO_OTYPER_OT13               GPIO_OTYPER_OT13_Msk\n#define GPIO_OTYPER_OT14_Pos           (14U)\n#define GPIO_OTYPER_OT14_Msk           (0x1UL << GPIO_OTYPER_OT14_Pos)          /*!< 0x00004000 */\n#define GPIO_OTYPER_OT14               GPIO_OTYPER_OT14_Msk\n#define GPIO_OTYPER_OT15_Pos           (15U)\n#define GPIO_OTYPER_OT15_Msk           (0x1UL << GPIO_OTYPER_OT15_Pos)          /*!< 0x00008000 */\n#define GPIO_OTYPER_OT15               GPIO_OTYPER_OT15_Msk\n\n/******************  Bits definition for GPIO_OSPEEDR register  ***************/\n#define GPIO_OSPEEDR_OSPEED0_Pos       (0U)\n#define GPIO_OSPEEDR_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000003 */\n#define GPIO_OSPEEDR_OSPEED0           GPIO_OSPEEDR_OSPEED0_Msk\n#define GPIO_OSPEEDR_OSPEED0_0         (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000001 */\n#define GPIO_OSPEEDR_OSPEED0_1         (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000002 */\n#define GPIO_OSPEEDR_OSPEED1_Pos       (2U)\n#define GPIO_OSPEEDR_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x0000000C */\n#define GPIO_OSPEEDR_OSPEED1           GPIO_OSPEEDR_OSPEED1_Msk\n#define GPIO_OSPEEDR_OSPEED1_0         (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000004 */\n#define GPIO_OSPEEDR_OSPEED1_1         (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000008 */\n#define GPIO_OSPEEDR_OSPEED2_Pos       (4U)\n#define GPIO_OSPEEDR_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000030 */\n#define GPIO_OSPEEDR_OSPEED2           GPIO_OSPEEDR_OSPEED2_Msk\n#define GPIO_OSPEEDR_OSPEED2_0         (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000010 */\n#define GPIO_OSPEEDR_OSPEED2_1         (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000020 */\n#define GPIO_OSPEEDR_OSPEED3_Pos       (6U)\n#define GPIO_OSPEEDR_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x000000C0 */\n#define GPIO_OSPEEDR_OSPEED3           GPIO_OSPEEDR_OSPEED3_Msk\n#define GPIO_OSPEEDR_OSPEED3_0         (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000040 */\n#define GPIO_OSPEEDR_OSPEED3_1         (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000080 */\n#define GPIO_OSPEEDR_OSPEED4_Pos       (8U)\n#define GPIO_OSPEEDR_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000300 */\n#define GPIO_OSPEEDR_OSPEED4           GPIO_OSPEEDR_OSPEED4_Msk\n#define GPIO_OSPEEDR_OSPEED4_0         (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000100 */\n#define GPIO_OSPEEDR_OSPEED4_1         (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000200 */\n#define GPIO_OSPEEDR_OSPEED5_Pos       (10U)\n#define GPIO_OSPEEDR_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000C00 */\n#define GPIO_OSPEEDR_OSPEED5           GPIO_OSPEEDR_OSPEED5_Msk\n#define GPIO_OSPEEDR_OSPEED5_0         (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000400 */\n#define GPIO_OSPEEDR_OSPEED5_1         (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000800 */\n#define GPIO_OSPEEDR_OSPEED6_Pos       (12U)\n#define GPIO_OSPEEDR_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00003000 */\n#define GPIO_OSPEEDR_OSPEED6           GPIO_OSPEEDR_OSPEED6_Msk\n#define GPIO_OSPEEDR_OSPEED6_0         (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00001000 */\n#define GPIO_OSPEEDR_OSPEED6_1         (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00002000 */\n#define GPIO_OSPEEDR_OSPEED7_Pos       (14U)\n#define GPIO_OSPEEDR_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x0000C000 */\n#define GPIO_OSPEEDR_OSPEED7           GPIO_OSPEEDR_OSPEED7_Msk\n#define GPIO_OSPEEDR_OSPEED7_0         (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00004000 */\n#define GPIO_OSPEEDR_OSPEED7_1         (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00008000 */\n#define GPIO_OSPEEDR_OSPEED8_Pos       (16U)\n#define GPIO_OSPEEDR_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00030000 */\n#define GPIO_OSPEEDR_OSPEED8           GPIO_OSPEEDR_OSPEED8_Msk\n#define GPIO_OSPEEDR_OSPEED8_0         (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00010000 */\n#define GPIO_OSPEEDR_OSPEED8_1         (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00020000 */\n#define GPIO_OSPEEDR_OSPEED9_Pos       (18U)\n#define GPIO_OSPEEDR_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x000C0000 */\n#define GPIO_OSPEEDR_OSPEED9           GPIO_OSPEEDR_OSPEED9_Msk\n#define GPIO_OSPEEDR_OSPEED9_0         (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00040000 */\n#define GPIO_OSPEEDR_OSPEED9_1         (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00080000 */\n#define GPIO_OSPEEDR_OSPEED10_Pos      (20U)\n#define GPIO_OSPEEDR_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00300000 */\n#define GPIO_OSPEEDR_OSPEED10          GPIO_OSPEEDR_OSPEED10_Msk\n#define GPIO_OSPEEDR_OSPEED10_0        (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00100000 */\n#define GPIO_OSPEEDR_OSPEED10_1        (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00200000 */\n#define GPIO_OSPEEDR_OSPEED11_Pos      (22U)\n#define GPIO_OSPEEDR_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00C00000 */\n#define GPIO_OSPEEDR_OSPEED11          GPIO_OSPEEDR_OSPEED11_Msk\n#define GPIO_OSPEEDR_OSPEED11_0        (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00400000 */\n#define GPIO_OSPEEDR_OSPEED11_1        (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00800000 */\n#define GPIO_OSPEEDR_OSPEED12_Pos      (24U)\n#define GPIO_OSPEEDR_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x03000000 */\n#define GPIO_OSPEEDR_OSPEED12          GPIO_OSPEEDR_OSPEED12_Msk\n#define GPIO_OSPEEDR_OSPEED12_0        (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x01000000 */\n#define GPIO_OSPEEDR_OSPEED12_1        (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x02000000 */\n#define GPIO_OSPEEDR_OSPEED13_Pos      (26U)\n#define GPIO_OSPEEDR_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x0C000000 */\n#define GPIO_OSPEEDR_OSPEED13          GPIO_OSPEEDR_OSPEED13_Msk\n#define GPIO_OSPEEDR_OSPEED13_0        (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x04000000 */\n#define GPIO_OSPEEDR_OSPEED13_1        (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x08000000 */\n#define GPIO_OSPEEDR_OSPEED14_Pos      (28U)\n#define GPIO_OSPEEDR_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x30000000 */\n#define GPIO_OSPEEDR_OSPEED14          GPIO_OSPEEDR_OSPEED14_Msk\n#define GPIO_OSPEEDR_OSPEED14_0        (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x10000000 */\n#define GPIO_OSPEEDR_OSPEED14_1        (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x20000000 */\n#define GPIO_OSPEEDR_OSPEED15_Pos      (30U)\n#define GPIO_OSPEEDR_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0xC0000000 */\n#define GPIO_OSPEEDR_OSPEED15          GPIO_OSPEEDR_OSPEED15_Msk\n#define GPIO_OSPEEDR_OSPEED15_0        (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x40000000 */\n#define GPIO_OSPEEDR_OSPEED15_1        (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x80000000 */\n\n/******************  Bits definition for GPIO_PUPDR register  *****************/\n#define GPIO_PUPDR_PUPD0_Pos           (0U)\n#define GPIO_PUPDR_PUPD0_Msk           (0x3UL << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000003 */\n#define GPIO_PUPDR_PUPD0               GPIO_PUPDR_PUPD0_Msk\n#define GPIO_PUPDR_PUPD0_0             (0x1UL << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000001 */\n#define GPIO_PUPDR_PUPD0_1             (0x2UL << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000002 */\n#define GPIO_PUPDR_PUPD1_Pos           (2U)\n#define GPIO_PUPDR_PUPD1_Msk           (0x3UL << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x0000000C */\n#define GPIO_PUPDR_PUPD1               GPIO_PUPDR_PUPD1_Msk\n#define GPIO_PUPDR_PUPD1_0             (0x1UL << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000004 */\n#define GPIO_PUPDR_PUPD1_1             (0x2UL << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000008 */\n#define GPIO_PUPDR_PUPD2_Pos           (4U)\n#define GPIO_PUPDR_PUPD2_Msk           (0x3UL << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000030 */\n#define GPIO_PUPDR_PUPD2               GPIO_PUPDR_PUPD2_Msk\n#define GPIO_PUPDR_PUPD2_0             (0x1UL << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000010 */\n#define GPIO_PUPDR_PUPD2_1             (0x2UL << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000020 */\n#define GPIO_PUPDR_PUPD3_Pos           (6U)\n#define GPIO_PUPDR_PUPD3_Msk           (0x3UL << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x000000C0 */\n#define GPIO_PUPDR_PUPD3               GPIO_PUPDR_PUPD3_Msk\n#define GPIO_PUPDR_PUPD3_0             (0x1UL << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000040 */\n#define GPIO_PUPDR_PUPD3_1             (0x2UL << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000080 */\n#define GPIO_PUPDR_PUPD4_Pos           (8U)\n#define GPIO_PUPDR_PUPD4_Msk           (0x3UL << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000300 */\n#define GPIO_PUPDR_PUPD4               GPIO_PUPDR_PUPD4_Msk\n#define GPIO_PUPDR_PUPD4_0             (0x1UL << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000100 */\n#define GPIO_PUPDR_PUPD4_1             (0x2UL << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000200 */\n#define GPIO_PUPDR_PUPD5_Pos           (10U)\n#define GPIO_PUPDR_PUPD5_Msk           (0x3UL << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000C00 */\n#define GPIO_PUPDR_PUPD5               GPIO_PUPDR_PUPD5_Msk\n#define GPIO_PUPDR_PUPD5_0             (0x1UL << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000400 */\n#define GPIO_PUPDR_PUPD5_1             (0x2UL << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000800 */\n#define GPIO_PUPDR_PUPD6_Pos           (12U)\n#define GPIO_PUPDR_PUPD6_Msk           (0x3UL << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00003000 */\n#define GPIO_PUPDR_PUPD6               GPIO_PUPDR_PUPD6_Msk\n#define GPIO_PUPDR_PUPD6_0             (0x1UL << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00001000 */\n#define GPIO_PUPDR_PUPD6_1             (0x2UL << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00002000 */\n#define GPIO_PUPDR_PUPD7_Pos           (14U)\n#define GPIO_PUPDR_PUPD7_Msk           (0x3UL << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x0000C000 */\n#define GPIO_PUPDR_PUPD7               GPIO_PUPDR_PUPD7_Msk\n#define GPIO_PUPDR_PUPD7_0             (0x1UL << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00004000 */\n#define GPIO_PUPDR_PUPD7_1             (0x2UL << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00008000 */\n#define GPIO_PUPDR_PUPD8_Pos           (16U)\n#define GPIO_PUPDR_PUPD8_Msk           (0x3UL << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00030000 */\n#define GPIO_PUPDR_PUPD8               GPIO_PUPDR_PUPD8_Msk\n#define GPIO_PUPDR_PUPD8_0             (0x1UL << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00010000 */\n#define GPIO_PUPDR_PUPD8_1             (0x2UL << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00020000 */\n#define GPIO_PUPDR_PUPD9_Pos           (18U)\n#define GPIO_PUPDR_PUPD9_Msk           (0x3UL << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x000C0000 */\n#define GPIO_PUPDR_PUPD9               GPIO_PUPDR_PUPD9_Msk\n#define GPIO_PUPDR_PUPD9_0             (0x1UL << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00040000 */\n#define GPIO_PUPDR_PUPD9_1             (0x2UL << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00080000 */\n#define GPIO_PUPDR_PUPD10_Pos          (20U)\n#define GPIO_PUPDR_PUPD10_Msk          (0x3UL << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00300000 */\n#define GPIO_PUPDR_PUPD10              GPIO_PUPDR_PUPD10_Msk\n#define GPIO_PUPDR_PUPD10_0            (0x1UL << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00100000 */\n#define GPIO_PUPDR_PUPD10_1            (0x2UL << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00200000 */\n#define GPIO_PUPDR_PUPD11_Pos          (22U)\n#define GPIO_PUPDR_PUPD11_Msk          (0x3UL << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00C00000 */\n#define GPIO_PUPDR_PUPD11              GPIO_PUPDR_PUPD11_Msk\n#define GPIO_PUPDR_PUPD11_0            (0x1UL << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00400000 */\n#define GPIO_PUPDR_PUPD11_1            (0x2UL << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00800000 */\n#define GPIO_PUPDR_PUPD12_Pos          (24U)\n#define GPIO_PUPDR_PUPD12_Msk          (0x3UL << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x03000000 */\n#define GPIO_PUPDR_PUPD12              GPIO_PUPDR_PUPD12_Msk\n#define GPIO_PUPDR_PUPD12_0            (0x1UL << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x01000000 */\n#define GPIO_PUPDR_PUPD12_1            (0x2UL << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x02000000 */\n#define GPIO_PUPDR_PUPD13_Pos          (26U)\n#define GPIO_PUPDR_PUPD13_Msk          (0x3UL << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x0C000000 */\n#define GPIO_PUPDR_PUPD13              GPIO_PUPDR_PUPD13_Msk\n#define GPIO_PUPDR_PUPD13_0            (0x1UL << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x04000000 */\n#define GPIO_PUPDR_PUPD13_1            (0x2UL << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x08000000 */\n#define GPIO_PUPDR_PUPD14_Pos          (28U)\n#define GPIO_PUPDR_PUPD14_Msk          (0x3UL << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x30000000 */\n#define GPIO_PUPDR_PUPD14              GPIO_PUPDR_PUPD14_Msk\n#define GPIO_PUPDR_PUPD14_0            (0x1UL << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x10000000 */\n#define GPIO_PUPDR_PUPD14_1            (0x2UL << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x20000000 */\n#define GPIO_PUPDR_PUPD15_Pos          (30U)\n#define GPIO_PUPDR_PUPD15_Msk          (0x3UL << GPIO_PUPDR_PUPD15_Pos)         /*!< 0xC0000000 */\n#define GPIO_PUPDR_PUPD15              GPIO_PUPDR_PUPD15_Msk\n#define GPIO_PUPDR_PUPD15_0            (0x1UL << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x40000000 */\n#define GPIO_PUPDR_PUPD15_1            (0x2UL << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x80000000 */\n\n/******************  Bits definition for GPIO_IDR register  *******************/\n#define GPIO_IDR_ID0_Pos               (0U)\n#define GPIO_IDR_ID0_Msk               (0x1UL << GPIO_IDR_ID0_Pos)              /*!< 0x00000001 */\n#define GPIO_IDR_ID0                   GPIO_IDR_ID0_Msk\n#define GPIO_IDR_ID1_Pos               (1U)\n#define GPIO_IDR_ID1_Msk               (0x1UL << GPIO_IDR_ID1_Pos)              /*!< 0x00000002 */\n#define GPIO_IDR_ID1                   GPIO_IDR_ID1_Msk\n#define GPIO_IDR_ID2_Pos               (2U)\n#define GPIO_IDR_ID2_Msk               (0x1UL << GPIO_IDR_ID2_Pos)              /*!< 0x00000004 */\n#define GPIO_IDR_ID2                   GPIO_IDR_ID2_Msk\n#define GPIO_IDR_ID3_Pos               (3U)\n#define GPIO_IDR_ID3_Msk               (0x1UL << GPIO_IDR_ID3_Pos)              /*!< 0x00000008 */\n#define GPIO_IDR_ID3                   GPIO_IDR_ID3_Msk\n#define GPIO_IDR_ID4_Pos               (4U)\n#define GPIO_IDR_ID4_Msk               (0x1UL << GPIO_IDR_ID4_Pos)              /*!< 0x00000010 */\n#define GPIO_IDR_ID4                   GPIO_IDR_ID4_Msk\n#define GPIO_IDR_ID5_Pos               (5U)\n#define GPIO_IDR_ID5_Msk               (0x1UL << GPIO_IDR_ID5_Pos)              /*!< 0x00000020 */\n#define GPIO_IDR_ID5                   GPIO_IDR_ID5_Msk\n#define GPIO_IDR_ID6_Pos               (6U)\n#define GPIO_IDR_ID6_Msk               (0x1UL << GPIO_IDR_ID6_Pos)              /*!< 0x00000040 */\n#define GPIO_IDR_ID6                   GPIO_IDR_ID6_Msk\n#define GPIO_IDR_ID7_Pos               (7U)\n#define GPIO_IDR_ID7_Msk               (0x1UL << GPIO_IDR_ID7_Pos)              /*!< 0x00000080 */\n#define GPIO_IDR_ID7                   GPIO_IDR_ID7_Msk\n#define GPIO_IDR_ID8_Pos               (8U)\n#define GPIO_IDR_ID8_Msk               (0x1UL << GPIO_IDR_ID8_Pos)              /*!< 0x00000100 */\n#define GPIO_IDR_ID8                   GPIO_IDR_ID8_Msk\n#define GPIO_IDR_ID9_Pos               (9U)\n#define GPIO_IDR_ID9_Msk               (0x1UL << GPIO_IDR_ID9_Pos)              /*!< 0x00000200 */\n#define GPIO_IDR_ID9                   GPIO_IDR_ID9_Msk\n#define GPIO_IDR_ID10_Pos              (10U)\n#define GPIO_IDR_ID10_Msk              (0x1UL << GPIO_IDR_ID10_Pos)             /*!< 0x00000400 */\n#define GPIO_IDR_ID10                  GPIO_IDR_ID10_Msk\n#define GPIO_IDR_ID11_Pos              (11U)\n#define GPIO_IDR_ID11_Msk              (0x1UL << GPIO_IDR_ID11_Pos)             /*!< 0x00000800 */\n#define GPIO_IDR_ID11                  GPIO_IDR_ID11_Msk\n#define GPIO_IDR_ID12_Pos              (12U)\n#define GPIO_IDR_ID12_Msk              (0x1UL << GPIO_IDR_ID12_Pos)             /*!< 0x00001000 */\n#define GPIO_IDR_ID12                  GPIO_IDR_ID12_Msk\n#define GPIO_IDR_ID13_Pos              (13U)\n#define GPIO_IDR_ID13_Msk              (0x1UL << GPIO_IDR_ID13_Pos)             /*!< 0x00002000 */\n#define GPIO_IDR_ID13                  GPIO_IDR_ID13_Msk\n#define GPIO_IDR_ID14_Pos              (14U)\n#define GPIO_IDR_ID14_Msk              (0x1UL << GPIO_IDR_ID14_Pos)             /*!< 0x00004000 */\n#define GPIO_IDR_ID14                  GPIO_IDR_ID14_Msk\n#define GPIO_IDR_ID15_Pos              (15U)\n#define GPIO_IDR_ID15_Msk              (0x1UL << GPIO_IDR_ID15_Pos)             /*!< 0x00008000 */\n#define GPIO_IDR_ID15                  GPIO_IDR_ID15_Msk\n\n/******************  Bits definition for GPIO_ODR register  *******************/\n#define GPIO_ODR_OD0_Pos               (0U)\n#define GPIO_ODR_OD0_Msk               (0x1UL << GPIO_ODR_OD0_Pos)              /*!< 0x00000001 */\n#define GPIO_ODR_OD0                   GPIO_ODR_OD0_Msk\n#define GPIO_ODR_OD1_Pos               (1U)\n#define GPIO_ODR_OD1_Msk               (0x1UL << GPIO_ODR_OD1_Pos)              /*!< 0x00000002 */\n#define GPIO_ODR_OD1                   GPIO_ODR_OD1_Msk\n#define GPIO_ODR_OD2_Pos               (2U)\n#define GPIO_ODR_OD2_Msk               (0x1UL << GPIO_ODR_OD2_Pos)              /*!< 0x00000004 */\n#define GPIO_ODR_OD2                   GPIO_ODR_OD2_Msk\n#define GPIO_ODR_OD3_Pos               (3U)\n#define GPIO_ODR_OD3_Msk               (0x1UL << GPIO_ODR_OD3_Pos)              /*!< 0x00000008 */\n#define GPIO_ODR_OD3                   GPIO_ODR_OD3_Msk\n#define GPIO_ODR_OD4_Pos               (4U)\n#define GPIO_ODR_OD4_Msk               (0x1UL << GPIO_ODR_OD4_Pos)              /*!< 0x00000010 */\n#define GPIO_ODR_OD4                   GPIO_ODR_OD4_Msk\n#define GPIO_ODR_OD5_Pos               (5U)\n#define GPIO_ODR_OD5_Msk               (0x1UL << GPIO_ODR_OD5_Pos)              /*!< 0x00000020 */\n#define GPIO_ODR_OD5                   GPIO_ODR_OD5_Msk\n#define GPIO_ODR_OD6_Pos               (6U)\n#define GPIO_ODR_OD6_Msk               (0x1UL << GPIO_ODR_OD6_Pos)              /*!< 0x00000040 */\n#define GPIO_ODR_OD6                   GPIO_ODR_OD6_Msk\n#define GPIO_ODR_OD7_Pos               (7U)\n#define GPIO_ODR_OD7_Msk               (0x1UL << GPIO_ODR_OD7_Pos)              /*!< 0x00000080 */\n#define GPIO_ODR_OD7                   GPIO_ODR_OD7_Msk\n#define GPIO_ODR_OD8_Pos               (8U)\n#define GPIO_ODR_OD8_Msk               (0x1UL << GPIO_ODR_OD8_Pos)              /*!< 0x00000100 */\n#define GPIO_ODR_OD8                   GPIO_ODR_OD8_Msk\n#define GPIO_ODR_OD9_Pos               (9U)\n#define GPIO_ODR_OD9_Msk               (0x1UL << GPIO_ODR_OD9_Pos)              /*!< 0x00000200 */\n#define GPIO_ODR_OD9                   GPIO_ODR_OD9_Msk\n#define GPIO_ODR_OD10_Pos              (10U)\n#define GPIO_ODR_OD10_Msk              (0x1UL << GPIO_ODR_OD10_Pos)             /*!< 0x00000400 */\n#define GPIO_ODR_OD10                  GPIO_ODR_OD10_Msk\n#define GPIO_ODR_OD11_Pos              (11U)\n#define GPIO_ODR_OD11_Msk              (0x1UL << GPIO_ODR_OD11_Pos)             /*!< 0x00000800 */\n#define GPIO_ODR_OD11                  GPIO_ODR_OD11_Msk\n#define GPIO_ODR_OD12_Pos              (12U)\n#define GPIO_ODR_OD12_Msk              (0x1UL << GPIO_ODR_OD12_Pos)             /*!< 0x00001000 */\n#define GPIO_ODR_OD12                  GPIO_ODR_OD12_Msk\n#define GPIO_ODR_OD13_Pos              (13U)\n#define GPIO_ODR_OD13_Msk              (0x1UL << GPIO_ODR_OD13_Pos)             /*!< 0x00002000 */\n#define GPIO_ODR_OD13                  GPIO_ODR_OD13_Msk\n#define GPIO_ODR_OD14_Pos              (14U)\n#define GPIO_ODR_OD14_Msk              (0x1UL << GPIO_ODR_OD14_Pos)             /*!< 0x00004000 */\n#define GPIO_ODR_OD14                  GPIO_ODR_OD14_Msk\n#define GPIO_ODR_OD15_Pos              (15U)\n#define GPIO_ODR_OD15_Msk              (0x1UL << GPIO_ODR_OD15_Pos)             /*!< 0x00008000 */\n#define GPIO_ODR_OD15                  GPIO_ODR_OD15_Msk\n\n/******************  Bits definition for GPIO_BSRR register  ******************/\n#define GPIO_BSRR_BS0_Pos              (0U)\n#define GPIO_BSRR_BS0_Msk              (0x1UL << GPIO_BSRR_BS0_Pos)             /*!< 0x00000001 */\n#define GPIO_BSRR_BS0                  GPIO_BSRR_BS0_Msk\n#define GPIO_BSRR_BS1_Pos              (1U)\n#define GPIO_BSRR_BS1_Msk              (0x1UL << GPIO_BSRR_BS1_Pos)             /*!< 0x00000002 */\n#define GPIO_BSRR_BS1                  GPIO_BSRR_BS1_Msk\n#define GPIO_BSRR_BS2_Pos              (2U)\n#define GPIO_BSRR_BS2_Msk              (0x1UL << GPIO_BSRR_BS2_Pos)             /*!< 0x00000004 */\n#define GPIO_BSRR_BS2                  GPIO_BSRR_BS2_Msk\n#define GPIO_BSRR_BS3_Pos              (3U)\n#define GPIO_BSRR_BS3_Msk              (0x1UL << GPIO_BSRR_BS3_Pos)             /*!< 0x00000008 */\n#define GPIO_BSRR_BS3                  GPIO_BSRR_BS3_Msk\n#define GPIO_BSRR_BS4_Pos              (4U)\n#define GPIO_BSRR_BS4_Msk              (0x1UL << GPIO_BSRR_BS4_Pos)             /*!< 0x00000010 */\n#define GPIO_BSRR_BS4                  GPIO_BSRR_BS4_Msk\n#define GPIO_BSRR_BS5_Pos              (5U)\n#define GPIO_BSRR_BS5_Msk              (0x1UL << GPIO_BSRR_BS5_Pos)             /*!< 0x00000020 */\n#define GPIO_BSRR_BS5                  GPIO_BSRR_BS5_Msk\n#define GPIO_BSRR_BS6_Pos              (6U)\n#define GPIO_BSRR_BS6_Msk              (0x1UL << GPIO_BSRR_BS6_Pos)             /*!< 0x00000040 */\n#define GPIO_BSRR_BS6                  GPIO_BSRR_BS6_Msk\n#define GPIO_BSRR_BS7_Pos              (7U)\n#define GPIO_BSRR_BS7_Msk              (0x1UL << GPIO_BSRR_BS7_Pos)             /*!< 0x00000080 */\n#define GPIO_BSRR_BS7                  GPIO_BSRR_BS7_Msk\n#define GPIO_BSRR_BS8_Pos              (8U)\n#define GPIO_BSRR_BS8_Msk              (0x1UL << GPIO_BSRR_BS8_Pos)             /*!< 0x00000100 */\n#define GPIO_BSRR_BS8                  GPIO_BSRR_BS8_Msk\n#define GPIO_BSRR_BS9_Pos              (9U)\n#define GPIO_BSRR_BS9_Msk              (0x1UL << GPIO_BSRR_BS9_Pos)             /*!< 0x00000200 */\n#define GPIO_BSRR_BS9                  GPIO_BSRR_BS9_Msk\n#define GPIO_BSRR_BS10_Pos             (10U)\n#define GPIO_BSRR_BS10_Msk             (0x1UL << GPIO_BSRR_BS10_Pos)            /*!< 0x00000400 */\n#define GPIO_BSRR_BS10                 GPIO_BSRR_BS10_Msk\n#define GPIO_BSRR_BS11_Pos             (11U)\n#define GPIO_BSRR_BS11_Msk             (0x1UL << GPIO_BSRR_BS11_Pos)            /*!< 0x00000800 */\n#define GPIO_BSRR_BS11                 GPIO_BSRR_BS11_Msk\n#define GPIO_BSRR_BS12_Pos             (12U)\n#define GPIO_BSRR_BS12_Msk             (0x1UL << GPIO_BSRR_BS12_Pos)            /*!< 0x00001000 */\n#define GPIO_BSRR_BS12                 GPIO_BSRR_BS12_Msk\n#define GPIO_BSRR_BS13_Pos             (13U)\n#define GPIO_BSRR_BS13_Msk             (0x1UL << GPIO_BSRR_BS13_Pos)            /*!< 0x00002000 */\n#define GPIO_BSRR_BS13                 GPIO_BSRR_BS13_Msk\n#define GPIO_BSRR_BS14_Pos             (14U)\n#define GPIO_BSRR_BS14_Msk             (0x1UL << GPIO_BSRR_BS14_Pos)            /*!< 0x00004000 */\n#define GPIO_BSRR_BS14                 GPIO_BSRR_BS14_Msk\n#define GPIO_BSRR_BS15_Pos             (15U)\n#define GPIO_BSRR_BS15_Msk             (0x1UL << GPIO_BSRR_BS15_Pos)            /*!< 0x00008000 */\n#define GPIO_BSRR_BS15                 GPIO_BSRR_BS15_Msk\n#define GPIO_BSRR_BR0_Pos              (16U)\n#define GPIO_BSRR_BR0_Msk              (0x1UL << GPIO_BSRR_BR0_Pos)             /*!< 0x00010000 */\n#define GPIO_BSRR_BR0                  GPIO_BSRR_BR0_Msk\n#define GPIO_BSRR_BR1_Pos              (17U)\n#define GPIO_BSRR_BR1_Msk              (0x1UL << GPIO_BSRR_BR1_Pos)             /*!< 0x00020000 */\n#define GPIO_BSRR_BR1                  GPIO_BSRR_BR1_Msk\n#define GPIO_BSRR_BR2_Pos              (18U)\n#define GPIO_BSRR_BR2_Msk              (0x1UL << GPIO_BSRR_BR2_Pos)             /*!< 0x00040000 */\n#define GPIO_BSRR_BR2                  GPIO_BSRR_BR2_Msk\n#define GPIO_BSRR_BR3_Pos              (19U)\n#define GPIO_BSRR_BR3_Msk              (0x1UL << GPIO_BSRR_BR3_Pos)             /*!< 0x00080000 */\n#define GPIO_BSRR_BR3                  GPIO_BSRR_BR3_Msk\n#define GPIO_BSRR_BR4_Pos              (20U)\n#define GPIO_BSRR_BR4_Msk              (0x1UL << GPIO_BSRR_BR4_Pos)             /*!< 0x00100000 */\n#define GPIO_BSRR_BR4                  GPIO_BSRR_BR4_Msk\n#define GPIO_BSRR_BR5_Pos              (21U)\n#define GPIO_BSRR_BR5_Msk              (0x1UL << GPIO_BSRR_BR5_Pos)             /*!< 0x00200000 */\n#define GPIO_BSRR_BR5                  GPIO_BSRR_BR5_Msk\n#define GPIO_BSRR_BR6_Pos              (22U)\n#define GPIO_BSRR_BR6_Msk              (0x1UL << GPIO_BSRR_BR6_Pos)             /*!< 0x00400000 */\n#define GPIO_BSRR_BR6                  GPIO_BSRR_BR6_Msk\n#define GPIO_BSRR_BR7_Pos              (23U)\n#define GPIO_BSRR_BR7_Msk              (0x1UL << GPIO_BSRR_BR7_Pos)             /*!< 0x00800000 */\n#define GPIO_BSRR_BR7                  GPIO_BSRR_BR7_Msk\n#define GPIO_BSRR_BR8_Pos              (24U)\n#define GPIO_BSRR_BR8_Msk              (0x1UL << GPIO_BSRR_BR8_Pos)             /*!< 0x01000000 */\n#define GPIO_BSRR_BR8                  GPIO_BSRR_BR8_Msk\n#define GPIO_BSRR_BR9_Pos              (25U)\n#define GPIO_BSRR_BR9_Msk              (0x1UL << GPIO_BSRR_BR9_Pos)             /*!< 0x02000000 */\n#define GPIO_BSRR_BR9                  GPIO_BSRR_BR9_Msk\n#define GPIO_BSRR_BR10_Pos             (26U)\n#define GPIO_BSRR_BR10_Msk             (0x1UL << GPIO_BSRR_BR10_Pos)            /*!< 0x04000000 */\n#define GPIO_BSRR_BR10                 GPIO_BSRR_BR10_Msk\n#define GPIO_BSRR_BR11_Pos             (27U)\n#define GPIO_BSRR_BR11_Msk             (0x1UL << GPIO_BSRR_BR11_Pos)            /*!< 0x08000000 */\n#define GPIO_BSRR_BR11                 GPIO_BSRR_BR11_Msk\n#define GPIO_BSRR_BR12_Pos             (28U)\n#define GPIO_BSRR_BR12_Msk             (0x1UL << GPIO_BSRR_BR12_Pos)            /*!< 0x10000000 */\n#define GPIO_BSRR_BR12                 GPIO_BSRR_BR12_Msk\n#define GPIO_BSRR_BR13_Pos             (29U)\n#define GPIO_BSRR_BR13_Msk             (0x1UL << GPIO_BSRR_BR13_Pos)            /*!< 0x20000000 */\n#define GPIO_BSRR_BR13                 GPIO_BSRR_BR13_Msk\n#define GPIO_BSRR_BR14_Pos             (30U)\n#define GPIO_BSRR_BR14_Msk             (0x1UL << GPIO_BSRR_BR14_Pos)            /*!< 0x40000000 */\n#define GPIO_BSRR_BR14                 GPIO_BSRR_BR14_Msk\n#define GPIO_BSRR_BR15_Pos             (31U)\n#define GPIO_BSRR_BR15_Msk             (0x1UL << GPIO_BSRR_BR15_Pos)            /*!< 0x80000000 */\n#define GPIO_BSRR_BR15                 GPIO_BSRR_BR15_Msk\n\n/****************** Bit definition for GPIO_LCKR register *********************/\n#define GPIO_LCKR_LCK0_Pos             (0U)\n#define GPIO_LCKR_LCK0_Msk             (0x1UL << GPIO_LCKR_LCK0_Pos)            /*!< 0x00000001 */\n#define GPIO_LCKR_LCK0                 GPIO_LCKR_LCK0_Msk\n#define GPIO_LCKR_LCK1_Pos             (1U)\n#define GPIO_LCKR_LCK1_Msk             (0x1UL << GPIO_LCKR_LCK1_Pos)            /*!< 0x00000002 */\n#define GPIO_LCKR_LCK1                 GPIO_LCKR_LCK1_Msk\n#define GPIO_LCKR_LCK2_Pos             (2U)\n#define GPIO_LCKR_LCK2_Msk             (0x1UL << GPIO_LCKR_LCK2_Pos)            /*!< 0x00000004 */\n#define GPIO_LCKR_LCK2                 GPIO_LCKR_LCK2_Msk\n#define GPIO_LCKR_LCK3_Pos             (3U)\n#define GPIO_LCKR_LCK3_Msk             (0x1UL << GPIO_LCKR_LCK3_Pos)            /*!< 0x00000008 */\n#define GPIO_LCKR_LCK3                 GPIO_LCKR_LCK3_Msk\n#define GPIO_LCKR_LCK4_Pos             (4U)\n#define GPIO_LCKR_LCK4_Msk             (0x1UL << GPIO_LCKR_LCK4_Pos)            /*!< 0x00000010 */\n#define GPIO_LCKR_LCK4                 GPIO_LCKR_LCK4_Msk\n#define GPIO_LCKR_LCK5_Pos             (5U)\n#define GPIO_LCKR_LCK5_Msk             (0x1UL << GPIO_LCKR_LCK5_Pos)            /*!< 0x00000020 */\n#define GPIO_LCKR_LCK5                 GPIO_LCKR_LCK5_Msk\n#define GPIO_LCKR_LCK6_Pos             (6U)\n#define GPIO_LCKR_LCK6_Msk             (0x1UL << GPIO_LCKR_LCK6_Pos)            /*!< 0x00000040 */\n#define GPIO_LCKR_LCK6                 GPIO_LCKR_LCK6_Msk\n#define GPIO_LCKR_LCK7_Pos             (7U)\n#define GPIO_LCKR_LCK7_Msk             (0x1UL << GPIO_LCKR_LCK7_Pos)            /*!< 0x00000080 */\n#define GPIO_LCKR_LCK7                 GPIO_LCKR_LCK7_Msk\n#define GPIO_LCKR_LCK8_Pos             (8U)\n#define GPIO_LCKR_LCK8_Msk             (0x1UL << GPIO_LCKR_LCK8_Pos)            /*!< 0x00000100 */\n#define GPIO_LCKR_LCK8                 GPIO_LCKR_LCK8_Msk\n#define GPIO_LCKR_LCK9_Pos             (9U)\n#define GPIO_LCKR_LCK9_Msk             (0x1UL << GPIO_LCKR_LCK9_Pos)            /*!< 0x00000200 */\n#define GPIO_LCKR_LCK9                 GPIO_LCKR_LCK9_Msk\n#define GPIO_LCKR_LCK10_Pos            (10U)\n#define GPIO_LCKR_LCK10_Msk            (0x1UL << GPIO_LCKR_LCK10_Pos)           /*!< 0x00000400 */\n#define GPIO_LCKR_LCK10                GPIO_LCKR_LCK10_Msk\n#define GPIO_LCKR_LCK11_Pos            (11U)\n#define GPIO_LCKR_LCK11_Msk            (0x1UL << GPIO_LCKR_LCK11_Pos)           /*!< 0x00000800 */\n#define GPIO_LCKR_LCK11                GPIO_LCKR_LCK11_Msk\n#define GPIO_LCKR_LCK12_Pos            (12U)\n#define GPIO_LCKR_LCK12_Msk            (0x1UL << GPIO_LCKR_LCK12_Pos)           /*!< 0x00001000 */\n#define GPIO_LCKR_LCK12                GPIO_LCKR_LCK12_Msk\n#define GPIO_LCKR_LCK13_Pos            (13U)\n#define GPIO_LCKR_LCK13_Msk            (0x1UL << GPIO_LCKR_LCK13_Pos)           /*!< 0x00002000 */\n#define GPIO_LCKR_LCK13                GPIO_LCKR_LCK13_Msk\n#define GPIO_LCKR_LCK14_Pos            (14U)\n#define GPIO_LCKR_LCK14_Msk            (0x1UL << GPIO_LCKR_LCK14_Pos)           /*!< 0x00004000 */\n#define GPIO_LCKR_LCK14                GPIO_LCKR_LCK14_Msk\n#define GPIO_LCKR_LCK15_Pos            (15U)\n#define GPIO_LCKR_LCK15_Msk            (0x1UL << GPIO_LCKR_LCK15_Pos)           /*!< 0x00008000 */\n#define GPIO_LCKR_LCK15                GPIO_LCKR_LCK15_Msk\n#define GPIO_LCKR_LCKK_Pos             (16U)\n#define GPIO_LCKR_LCKK_Msk             (0x1UL << GPIO_LCKR_LCKK_Pos)            /*!< 0x00010000 */\n#define GPIO_LCKR_LCKK                 GPIO_LCKR_LCKK_Msk\n\n/****************** Bit definition for GPIO_AFRL register *********************/\n#define GPIO_AFRL_AFSEL0_Pos           (0U)\n#define GPIO_AFRL_AFSEL0_Msk           (0xFUL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x0000000F */\n#define GPIO_AFRL_AFSEL0               GPIO_AFRL_AFSEL0_Msk\n#define GPIO_AFRL_AFSEL0_0             (0x1UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000001 */\n#define GPIO_AFRL_AFSEL0_1             (0x2UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000002 */\n#define GPIO_AFRL_AFSEL0_2             (0x4UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000004 */\n#define GPIO_AFRL_AFSEL0_3             (0x8UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000008 */\n#define GPIO_AFRL_AFSEL1_Pos           (4U)\n#define GPIO_AFRL_AFSEL1_Msk           (0xFUL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x000000F0 */\n#define GPIO_AFRL_AFSEL1               GPIO_AFRL_AFSEL1_Msk\n#define GPIO_AFRL_AFSEL1_0             (0x1UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000010 */\n#define GPIO_AFRL_AFSEL1_1             (0x2UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000020 */\n#define GPIO_AFRL_AFSEL1_2             (0x4UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000040 */\n#define GPIO_AFRL_AFSEL1_3             (0x8UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000080 */\n#define GPIO_AFRL_AFSEL2_Pos           (8U)\n#define GPIO_AFRL_AFSEL2_Msk           (0xFUL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000F00 */\n#define GPIO_AFRL_AFSEL2               GPIO_AFRL_AFSEL2_Msk\n#define GPIO_AFRL_AFSEL2_0             (0x1UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000100 */\n#define GPIO_AFRL_AFSEL2_1             (0x2UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000200 */\n#define GPIO_AFRL_AFSEL2_2             (0x4UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000400 */\n#define GPIO_AFRL_AFSEL2_3             (0x8UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000800 */\n#define GPIO_AFRL_AFSEL3_Pos           (12U)\n#define GPIO_AFRL_AFSEL3_Msk           (0xFUL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x0000F000 */\n#define GPIO_AFRL_AFSEL3               GPIO_AFRL_AFSEL3_Msk\n#define GPIO_AFRL_AFSEL3_0             (0x1UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00001000 */\n#define GPIO_AFRL_AFSEL3_1             (0x2UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00002000 */\n#define GPIO_AFRL_AFSEL3_2             (0x4UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00004000 */\n#define GPIO_AFRL_AFSEL3_3             (0x8UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00008000 */\n#define GPIO_AFRL_AFSEL4_Pos           (16U)\n#define GPIO_AFRL_AFSEL4_Msk           (0xFUL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x000F0000 */\n#define GPIO_AFRL_AFSEL4               GPIO_AFRL_AFSEL4_Msk\n#define GPIO_AFRL_AFSEL4_0             (0x1UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00010000 */\n#define GPIO_AFRL_AFSEL4_1             (0x2UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00020000 */\n#define GPIO_AFRL_AFSEL4_2             (0x4UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00040000 */\n#define GPIO_AFRL_AFSEL4_3             (0x8UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00080000 */\n#define GPIO_AFRL_AFSEL5_Pos           (20U)\n#define GPIO_AFRL_AFSEL5_Msk           (0xFUL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00F00000 */\n#define GPIO_AFRL_AFSEL5               GPIO_AFRL_AFSEL5_Msk\n#define GPIO_AFRL_AFSEL5_0             (0x1UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00100000 */\n#define GPIO_AFRL_AFSEL5_1             (0x2UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00200000 */\n#define GPIO_AFRL_AFSEL5_2             (0x4UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00400000 */\n#define GPIO_AFRL_AFSEL5_3             (0x8UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00800000 */\n#define GPIO_AFRL_AFSEL6_Pos           (24U)\n#define GPIO_AFRL_AFSEL6_Msk           (0xFUL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x0F000000 */\n#define GPIO_AFRL_AFSEL6               GPIO_AFRL_AFSEL6_Msk\n#define GPIO_AFRL_AFSEL6_0             (0x1UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x01000000 */\n#define GPIO_AFRL_AFSEL6_1             (0x2UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x02000000 */\n#define GPIO_AFRL_AFSEL6_2             (0x4UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x04000000 */\n#define GPIO_AFRL_AFSEL6_3             (0x8UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x08000000 */\n#define GPIO_AFRL_AFSEL7_Pos           (28U)\n#define GPIO_AFRL_AFSEL7_Msk           (0xFUL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0xF0000000 */\n#define GPIO_AFRL_AFSEL7               GPIO_AFRL_AFSEL7_Msk\n#define GPIO_AFRL_AFSEL7_0             (0x1UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x10000000 */\n#define GPIO_AFRL_AFSEL7_1             (0x2UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x20000000 */\n#define GPIO_AFRL_AFSEL7_2             (0x4UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x40000000 */\n#define GPIO_AFRL_AFSEL7_3             (0x8UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x80000000 */\n\n/****************** Bit definition for GPIO_AFRH register *********************/\n#define GPIO_AFRH_AFSEL8_Pos           (0U)\n#define GPIO_AFRH_AFSEL8_Msk           (0xFUL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x0000000F */\n#define GPIO_AFRH_AFSEL8               GPIO_AFRH_AFSEL8_Msk\n#define GPIO_AFRH_AFSEL8_0             (0x1UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000001 */\n#define GPIO_AFRH_AFSEL8_1             (0x2UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000002 */\n#define GPIO_AFRH_AFSEL8_2             (0x4UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000004 */\n#define GPIO_AFRH_AFSEL8_3             (0x8UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000008 */\n#define GPIO_AFRH_AFSEL9_Pos           (4U)\n#define GPIO_AFRH_AFSEL9_Msk           (0xFUL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x000000F0 */\n#define GPIO_AFRH_AFSEL9               GPIO_AFRH_AFSEL9_Msk\n#define GPIO_AFRH_AFSEL9_0             (0x1UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000010 */\n#define GPIO_AFRH_AFSEL9_1             (0x2UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000020 */\n#define GPIO_AFRH_AFSEL9_2             (0x4UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000040 */\n#define GPIO_AFRH_AFSEL9_3             (0x8UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000080 */\n#define GPIO_AFRH_AFSEL10_Pos          (8U)\n#define GPIO_AFRH_AFSEL10_Msk          (0xFUL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000F00 */\n#define GPIO_AFRH_AFSEL10              GPIO_AFRH_AFSEL10_Msk\n#define GPIO_AFRH_AFSEL10_0            (0x1UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000100 */\n#define GPIO_AFRH_AFSEL10_1            (0x2UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000200 */\n#define GPIO_AFRH_AFSEL10_2            (0x4UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000400 */\n#define GPIO_AFRH_AFSEL10_3            (0x8UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000800 */\n#define GPIO_AFRH_AFSEL11_Pos          (12U)\n#define GPIO_AFRH_AFSEL11_Msk          (0xFUL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x0000F000 */\n#define GPIO_AFRH_AFSEL11              GPIO_AFRH_AFSEL11_Msk\n#define GPIO_AFRH_AFSEL11_0            (0x1UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00001000 */\n#define GPIO_AFRH_AFSEL11_1            (0x2UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00002000 */\n#define GPIO_AFRH_AFSEL11_2            (0x4UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00004000 */\n#define GPIO_AFRH_AFSEL11_3            (0x8UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00008000 */\n#define GPIO_AFRH_AFSEL12_Pos          (16U)\n#define GPIO_AFRH_AFSEL12_Msk          (0xFUL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x000F0000 */\n#define GPIO_AFRH_AFSEL12              GPIO_AFRH_AFSEL12_Msk\n#define GPIO_AFRH_AFSEL12_0            (0x1UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00010000 */\n#define GPIO_AFRH_AFSEL12_1            (0x2UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00020000 */\n#define GPIO_AFRH_AFSEL12_2            (0x4UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00040000 */\n#define GPIO_AFRH_AFSEL12_3            (0x8UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00080000 */\n#define GPIO_AFRH_AFSEL13_Pos          (20U)\n#define GPIO_AFRH_AFSEL13_Msk          (0xFUL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00F00000 */\n#define GPIO_AFRH_AFSEL13              GPIO_AFRH_AFSEL13_Msk\n#define GPIO_AFRH_AFSEL13_0            (0x1UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00100000 */\n#define GPIO_AFRH_AFSEL13_1            (0x2UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00200000 */\n#define GPIO_AFRH_AFSEL13_2            (0x4UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00400000 */\n#define GPIO_AFRH_AFSEL13_3            (0x8UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00800000 */\n#define GPIO_AFRH_AFSEL14_Pos          (24U)\n#define GPIO_AFRH_AFSEL14_Msk          (0xFUL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x0F000000 */\n#define GPIO_AFRH_AFSEL14              GPIO_AFRH_AFSEL14_Msk\n#define GPIO_AFRH_AFSEL14_0            (0x1UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x01000000 */\n#define GPIO_AFRH_AFSEL14_1            (0x2UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x02000000 */\n#define GPIO_AFRH_AFSEL14_2            (0x4UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x04000000 */\n#define GPIO_AFRH_AFSEL14_3            (0x8UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x08000000 */\n#define GPIO_AFRH_AFSEL15_Pos          (28U)\n#define GPIO_AFRH_AFSEL15_Msk          (0xFUL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0xF0000000 */\n#define GPIO_AFRH_AFSEL15              GPIO_AFRH_AFSEL15_Msk\n#define GPIO_AFRH_AFSEL15_0            (0x1UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x10000000 */\n#define GPIO_AFRH_AFSEL15_1            (0x2UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x20000000 */\n#define GPIO_AFRH_AFSEL15_2            (0x4UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x40000000 */\n#define GPIO_AFRH_AFSEL15_3            (0x8UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x80000000 */\n\n/******************  Bits definition for GPIO_BRR register  ******************/\n#define GPIO_BRR_BR0_Pos               (0U)\n#define GPIO_BRR_BR0_Msk               (0x1UL << GPIO_BRR_BR0_Pos)              /*!< 0x00000001 */\n#define GPIO_BRR_BR0                   GPIO_BRR_BR0_Msk\n#define GPIO_BRR_BR1_Pos               (1U)\n#define GPIO_BRR_BR1_Msk               (0x1UL << GPIO_BRR_BR1_Pos)              /*!< 0x00000002 */\n#define GPIO_BRR_BR1                   GPIO_BRR_BR1_Msk\n#define GPIO_BRR_BR2_Pos               (2U)\n#define GPIO_BRR_BR2_Msk               (0x1UL << GPIO_BRR_BR2_Pos)              /*!< 0x00000004 */\n#define GPIO_BRR_BR2                   GPIO_BRR_BR2_Msk\n#define GPIO_BRR_BR3_Pos               (3U)\n#define GPIO_BRR_BR3_Msk               (0x1UL << GPIO_BRR_BR3_Pos)              /*!< 0x00000008 */\n#define GPIO_BRR_BR3                   GPIO_BRR_BR3_Msk\n#define GPIO_BRR_BR4_Pos               (4U)\n#define GPIO_BRR_BR4_Msk               (0x1UL << GPIO_BRR_BR4_Pos)              /*!< 0x00000010 */\n#define GPIO_BRR_BR4                   GPIO_BRR_BR4_Msk\n#define GPIO_BRR_BR5_Pos               (5U)\n#define GPIO_BRR_BR5_Msk               (0x1UL << GPIO_BRR_BR5_Pos)              /*!< 0x00000020 */\n#define GPIO_BRR_BR5                   GPIO_BRR_BR5_Msk\n#define GPIO_BRR_BR6_Pos               (6U)\n#define GPIO_BRR_BR6_Msk               (0x1UL << GPIO_BRR_BR6_Pos)              /*!< 0x00000040 */\n#define GPIO_BRR_BR6                   GPIO_BRR_BR6_Msk\n#define GPIO_BRR_BR7_Pos               (7U)\n#define GPIO_BRR_BR7_Msk               (0x1UL << GPIO_BRR_BR7_Pos)              /*!< 0x00000080 */\n#define GPIO_BRR_BR7                   GPIO_BRR_BR7_Msk\n#define GPIO_BRR_BR8_Pos               (8U)\n#define GPIO_BRR_BR8_Msk               (0x1UL << GPIO_BRR_BR8_Pos)              /*!< 0x00000100 */\n#define GPIO_BRR_BR8                   GPIO_BRR_BR8_Msk\n#define GPIO_BRR_BR9_Pos               (9U)\n#define GPIO_BRR_BR9_Msk               (0x1UL << GPIO_BRR_BR9_Pos)              /*!< 0x00000200 */\n#define GPIO_BRR_BR9                   GPIO_BRR_BR9_Msk\n#define GPIO_BRR_BR10_Pos              (10U)\n#define GPIO_BRR_BR10_Msk              (0x1UL << GPIO_BRR_BR10_Pos)             /*!< 0x00000400 */\n#define GPIO_BRR_BR10                  GPIO_BRR_BR10_Msk\n#define GPIO_BRR_BR11_Pos              (11U)\n#define GPIO_BRR_BR11_Msk              (0x1UL << GPIO_BRR_BR11_Pos)             /*!< 0x00000800 */\n#define GPIO_BRR_BR11                  GPIO_BRR_BR11_Msk\n#define GPIO_BRR_BR12_Pos              (12U)\n#define GPIO_BRR_BR12_Msk              (0x1UL << GPIO_BRR_BR12_Pos)             /*!< 0x00001000 */\n#define GPIO_BRR_BR12                  GPIO_BRR_BR12_Msk\n#define GPIO_BRR_BR13_Pos              (13U)\n#define GPIO_BRR_BR13_Msk              (0x1UL << GPIO_BRR_BR13_Pos)             /*!< 0x00002000 */\n#define GPIO_BRR_BR13                  GPIO_BRR_BR13_Msk\n#define GPIO_BRR_BR14_Pos              (14U)\n#define GPIO_BRR_BR14_Msk              (0x1UL << GPIO_BRR_BR14_Pos)             /*!< 0x00004000 */\n#define GPIO_BRR_BR14                  GPIO_BRR_BR14_Msk\n#define GPIO_BRR_BR15_Pos              (15U)\n#define GPIO_BRR_BR15_Msk              (0x1UL << GPIO_BRR_BR15_Pos)             /*!< 0x00008000 */\n#define GPIO_BRR_BR15                  GPIO_BRR_BR15_Msk\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                      Inter-integrated Circuit Interface (I2C)              */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for I2C_CR1 register  *******************/\n#define I2C_CR1_PE_Pos               (0U)\n#define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                 /*!< 0x00000001 */\n#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */\n#define I2C_CR1_TXIE_Pos             (1U)\n#define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)               /*!< 0x00000002 */\n#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */\n#define I2C_CR1_RXIE_Pos             (2U)\n#define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)               /*!< 0x00000004 */\n#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */\n#define I2C_CR1_ADDRIE_Pos           (3U)\n#define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)             /*!< 0x00000008 */\n#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */\n#define I2C_CR1_NACKIE_Pos           (4U)\n#define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)             /*!< 0x00000010 */\n#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */\n#define I2C_CR1_STOPIE_Pos           (5U)\n#define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)             /*!< 0x00000020 */\n#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */\n#define I2C_CR1_TCIE_Pos             (6U)\n#define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)               /*!< 0x00000040 */\n#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */\n#define I2C_CR1_ERRIE_Pos            (7U)\n#define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)              /*!< 0x00000080 */\n#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */\n#define I2C_CR1_DNF_Pos              (8U)\n#define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                /*!< 0x00000F00 */\n#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */\n#define I2C_CR1_ANFOFF_Pos           (12U)\n#define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)             /*!< 0x00001000 */\n#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */\n#define I2C_CR1_SWRST_Pos            (13U)\n#define I2C_CR1_SWRST_Msk            (0x1UL << I2C_CR1_SWRST_Pos)              /*!< 0x00002000 */\n#define I2C_CR1_SWRST                I2C_CR1_SWRST_Msk                         /*!< Software reset */\n#define I2C_CR1_TXDMAEN_Pos          (14U)\n#define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)            /*!< 0x00004000 */\n#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */\n#define I2C_CR1_RXDMAEN_Pos          (15U)\n#define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)            /*!< 0x00008000 */\n#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */\n#define I2C_CR1_SBC_Pos              (16U)\n#define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                /*!< 0x00010000 */\n#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */\n#define I2C_CR1_NOSTRETCH_Pos        (17U)\n#define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)          /*!< 0x00020000 */\n#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */\n#define I2C_CR1_WUPEN_Pos            (18U)\n#define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)              /*!< 0x00040000 */\n#define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */\n#define I2C_CR1_GCEN_Pos             (19U)\n#define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)               /*!< 0x00080000 */\n#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */\n#define I2C_CR1_SMBHEN_Pos           (20U)\n#define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)             /*!< 0x00100000 */\n#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */\n#define I2C_CR1_SMBDEN_Pos           (21U)\n#define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)             /*!< 0x00200000 */\n#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */\n#define I2C_CR1_ALERTEN_Pos          (22U)\n#define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)            /*!< 0x00400000 */\n#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */\n#define I2C_CR1_PECEN_Pos            (23U)\n#define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)              /*!< 0x00800000 */\n#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */\n\n/******************  Bit definition for I2C_CR2 register  ********************/\n#define I2C_CR2_SADD_Pos             (0U)\n#define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)             /*!< 0x000003FF */\n#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */\n#define I2C_CR2_RD_WRN_Pos           (10U)\n#define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)             /*!< 0x00000400 */\n#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */\n#define I2C_CR2_ADD10_Pos            (11U)\n#define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)              /*!< 0x00000800 */\n#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */\n#define I2C_CR2_HEAD10R_Pos          (12U)\n#define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)            /*!< 0x00001000 */\n#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */\n#define I2C_CR2_START_Pos            (13U)\n#define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)              /*!< 0x00002000 */\n#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */\n#define I2C_CR2_STOP_Pos             (14U)\n#define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)               /*!< 0x00004000 */\n#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */\n#define I2C_CR2_NACK_Pos             (15U)\n#define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)               /*!< 0x00008000 */\n#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */\n#define I2C_CR2_NBYTES_Pos           (16U)\n#define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)            /*!< 0x00FF0000 */\n#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */\n#define I2C_CR2_RELOAD_Pos           (24U)\n#define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)             /*!< 0x01000000 */\n#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */\n#define I2C_CR2_AUTOEND_Pos          (25U)\n#define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)            /*!< 0x02000000 */\n#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */\n#define I2C_CR2_PECBYTE_Pos          (26U)\n#define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)            /*!< 0x04000000 */\n#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */\n\n/*******************  Bit definition for I2C_OAR1 register  ******************/\n#define I2C_OAR1_OA1_Pos             (0U)\n#define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)             /*!< 0x000003FF */\n#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */\n#define I2C_OAR1_OA1MODE_Pos         (10U)\n#define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)           /*!< 0x00000400 */\n#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */\n#define I2C_OAR1_OA1EN_Pos           (15U)\n#define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)             /*!< 0x00008000 */\n#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */\n\n/*******************  Bit definition for I2C_OAR2 register  ******************/\n#define I2C_OAR2_OA2_Pos             (1U)\n#define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)              /*!< 0x000000FE */\n#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2 */\n#define I2C_OAR2_OA2MSK_Pos          (8U)\n#define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)            /*!< 0x00000700 */\n#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks */\n#define I2C_OAR2_OA2NOMASK           (0U)                                      /*!< No mask                                        */\n#define I2C_OAR2_OA2MASK01_Pos       (8U)\n#define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)         /*!< 0x00000100 */\n#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared   */\n#define I2C_OAR2_OA2MASK02_Pos       (9U)\n#define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)         /*!< 0x00000200 */\n#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */\n#define I2C_OAR2_OA2MASK03_Pos       (8U)\n#define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)         /*!< 0x00000300 */\n#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */\n#define I2C_OAR2_OA2MASK04_Pos       (10U)\n#define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)         /*!< 0x00000400 */\n#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */\n#define I2C_OAR2_OA2MASK05_Pos       (8U)\n#define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)         /*!< 0x00000500 */\n#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */\n#define I2C_OAR2_OA2MASK06_Pos       (9U)\n#define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)         /*!< 0x00000600 */\n#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared   */\n#define I2C_OAR2_OA2MASK07_Pos       (8U)\n#define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)         /*!< 0x00000700 */\n#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done      */\n#define I2C_OAR2_OA2EN_Pos           (15U)\n#define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)             /*!< 0x00008000 */\n#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable */\n\n/*******************  Bit definition for I2C_TIMINGR register *******************/\n#define I2C_TIMINGR_SCLL_Pos         (0U)\n#define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)          /*!< 0x000000FF */\n#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */\n#define I2C_TIMINGR_SCLH_Pos         (8U)\n#define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)          /*!< 0x0000FF00 */\n#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */\n#define I2C_TIMINGR_SDADEL_Pos       (16U)\n#define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)         /*!< 0x000F0000 */\n#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */\n#define I2C_TIMINGR_SCLDEL_Pos       (20U)\n#define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)         /*!< 0x00F00000 */\n#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */\n#define I2C_TIMINGR_PRESC_Pos        (28U)\n#define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)          /*!< 0xF0000000 */\n#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */\n\n/******************* Bit definition for I2C_TIMEOUTR register *******************/\n#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)\n#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)    /*!< 0x00000FFF */\n#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */\n#define I2C_TIMEOUTR_TIDLE_Pos       (12U)\n#define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)         /*!< 0x00001000 */\n#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */\n#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)\n#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)      /*!< 0x00008000 */\n#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */\n#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)\n#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)    /*!< 0x0FFF0000 */\n#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/\n#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)\n#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)        /*!< 0x80000000 */\n#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */\n\n/******************  Bit definition for I2C_ISR register  *********************/\n#define I2C_ISR_TXE_Pos              (0U)\n#define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                /*!< 0x00000001 */\n#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */\n#define I2C_ISR_TXIS_Pos             (1U)\n#define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)               /*!< 0x00000002 */\n#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */\n#define I2C_ISR_RXNE_Pos             (2U)\n#define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)               /*!< 0x00000004 */\n#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */\n#define I2C_ISR_ADDR_Pos             (3U)\n#define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)               /*!< 0x00000008 */\n#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/\n#define I2C_ISR_NACKF_Pos            (4U)\n#define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)              /*!< 0x00000010 */\n#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */\n#define I2C_ISR_STOPF_Pos            (5U)\n#define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)              /*!< 0x00000020 */\n#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */\n#define I2C_ISR_TC_Pos               (6U)\n#define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                 /*!< 0x00000040 */\n#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */\n#define I2C_ISR_TCR_Pos              (7U)\n#define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                /*!< 0x00000080 */\n#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */\n#define I2C_ISR_BERR_Pos             (8U)\n#define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)               /*!< 0x00000100 */\n#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */\n#define I2C_ISR_ARLO_Pos             (9U)\n#define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)               /*!< 0x00000200 */\n#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */\n#define I2C_ISR_OVR_Pos              (10U)\n#define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                /*!< 0x00000400 */\n#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */\n#define I2C_ISR_PECERR_Pos           (11U)\n#define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)             /*!< 0x00000800 */\n#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */\n#define I2C_ISR_TIMEOUT_Pos          (12U)\n#define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)            /*!< 0x00001000 */\n#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */\n#define I2C_ISR_ALERT_Pos            (13U)\n#define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)              /*!< 0x00002000 */\n#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */\n#define I2C_ISR_BUSY_Pos             (15U)\n#define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)               /*!< 0x00008000 */\n#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */\n#define I2C_ISR_DIR_Pos              (16U)\n#define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                /*!< 0x00010000 */\n#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */\n#define I2C_ISR_ADDCODE_Pos          (17U)\n#define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)           /*!< 0x00FE0000 */\n#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */\n\n/******************  Bit definition for I2C_ICR register  *********************/\n#define I2C_ICR_ADDRCF_Pos           (3U)\n#define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)             /*!< 0x00000008 */\n#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */\n#define I2C_ICR_NACKCF_Pos           (4U)\n#define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)             /*!< 0x00000010 */\n#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */\n#define I2C_ICR_STOPCF_Pos           (5U)\n#define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)             /*!< 0x00000020 */\n#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */\n#define I2C_ICR_BERRCF_Pos           (8U)\n#define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)             /*!< 0x00000100 */\n#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */\n#define I2C_ICR_ARLOCF_Pos           (9U)\n#define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)             /*!< 0x00000200 */\n#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */\n#define I2C_ICR_OVRCF_Pos            (10U)\n#define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)              /*!< 0x00000400 */\n#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */\n#define I2C_ICR_PECCF_Pos            (11U)\n#define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)              /*!< 0x00000800 */\n#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */\n#define I2C_ICR_TIMOUTCF_Pos         (12U)\n#define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)           /*!< 0x00001000 */\n#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */\n#define I2C_ICR_ALERTCF_Pos          (13U)\n#define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)            /*!< 0x00002000 */\n#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */\n\n/******************  Bit definition for I2C_PECR register  *********************/\n#define I2C_PECR_PEC_Pos             (0U)\n#define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)              /*!< 0x000000FF */\n#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */\n\n/******************  Bit definition for I2C_RXDR register  *********************/\n#define I2C_RXDR_RXDATA_Pos          (0U)\n#define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)           /*!< 0x000000FF */\n#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */\n\n/******************  Bit definition for I2C_TXDR register  *********************/\n#define I2C_TXDR_TXDATA_Pos          (0U)\n#define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)           /*!< 0x000000FF */\n#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                        Independent WATCHDOG (IWDG)                         */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for IWDG_KR register  ********************/\n#define IWDG_KR_KEY_Pos      (0U)\n#define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                     /*!< 0x0000FFFF */\n#define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!<Key value (write only, read 0000h)  */\n\n/*******************  Bit definition for IWDG_PR register  ********************/\n#define IWDG_PR_PR_Pos       (0U)\n#define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                         /*!< 0x00000007 */\n#define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!<PR[2:0] (Prescaler divider)         */\n#define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                         /*!< 0x00000001 */\n#define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                         /*!< 0x00000002 */\n#define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                         /*!< 0x00000004 */\n\n/*******************  Bit definition for IWDG_RLR register  *******************/\n#define IWDG_RLR_RL_Pos      (0U)\n#define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                      /*!< 0x00000FFF */\n#define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!<Watchdog counter reload value        */\n\n/*******************  Bit definition for IWDG_SR register  ********************/\n#define IWDG_SR_PVU_Pos      (0U)\n#define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                        /*!< 0x00000001 */\n#define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */\n#define IWDG_SR_RVU_Pos      (1U)\n#define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                        /*!< 0x00000002 */\n#define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */\n#define IWDG_SR_WVU_Pos      (2U)\n#define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                        /*!< 0x00000004 */\n#define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */\n\n/*******************  Bit definition for IWDG_KR register  ********************/\n#define IWDG_WINR_WIN_Pos    (0U)\n#define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                    /*!< 0x00000FFF */\n#define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                        Power Control                                       */\n/*                                                                            */\n/******************************************************************************/\n#define PWR_BOR_SUPPORT                       /*!< PWR feature available only on specific devices: Brown-Out Reset feature         */\n#define PWR_SHDW_SUPPORT                      /*!< PWR feature available only on specific devices: Shutdown mode */\n\n/********************  Bit definition for PWR_CR1 register  ********************/\n#define PWR_CR1_LPMS_Pos          (0U)\n#define PWR_CR1_LPMS_Msk          (0x7UL << PWR_CR1_LPMS_Pos)                  /*!< 0x00000007 */\n#define PWR_CR1_LPMS              PWR_CR1_LPMS_Msk                             /*!< Low Power Mode Selection */\n#define PWR_CR1_LPMS_0            (0x1UL << PWR_CR1_LPMS_Pos)                  /*!< 0x00000001 */\n#define PWR_CR1_LPMS_1            (0x2UL << PWR_CR1_LPMS_Pos)                  /*!< 0x00000002 */\n#define PWR_CR1_LPMS_2            (0x4UL << PWR_CR1_LPMS_Pos)                  /*!< 0x00000004 */\n#define PWR_CR1_FPD_STOP_Pos      (3U)\n#define PWR_CR1_FPD_STOP_Msk      (0x1UL << PWR_CR1_FPD_STOP_Pos)              /*!< 0x00000008 */\n#define PWR_CR1_FPD_STOP          PWR_CR1_FPD_STOP_Msk                         /*!< Flash power down mode during stop */\n#define PWR_CR1_FPD_SLP_Pos       (5U)\n#define PWR_CR1_FPD_SLP_Msk       (0x1UL << PWR_CR1_FPD_SLP_Pos)               /*!< 0x00000020 */\n#define PWR_CR1_FPD_SLP           PWR_CR1_FPD_SLP_Msk                          /*!< Flash power down mode during sleep */\n\n/********************  Bit definition for PWR_CR3 register  ********************/\n#define PWR_CR3_EWUP_Pos          (0U)\n#define PWR_CR3_EWUP_Msk          (0x2FUL << PWR_CR3_EWUP_Pos)                 /*!< 0x0000002F */\n#define PWR_CR3_EWUP              PWR_CR3_EWUP_Msk                             /*!< Enable all external Wake-Up Lines  */\n#define PWR_CR3_EWUP1_Pos         (0U)\n#define PWR_CR3_EWUP1_Msk         (0x1UL << PWR_CR3_EWUP1_Pos)                 /*!< 0x00000001 */\n#define PWR_CR3_EWUP1             PWR_CR3_EWUP1_Msk                            /*!< Enable external WKUP Line 1 */\n#define PWR_CR3_EWUP2_Pos         (1U)\n#define PWR_CR3_EWUP2_Msk         (0x1UL << PWR_CR3_EWUP2_Pos)                 /*!< 0x00000002 */\n#define PWR_CR3_EWUP2             PWR_CR3_EWUP2_Msk                            /*!< Enable external WKUP pin 2 */\n#define PWR_CR3_EWUP3_Pos         (2U)\n#define PWR_CR3_EWUP3_Msk         (0x1UL << PWR_CR3_EWUP3_Pos)                 /*!< 0x00000004 */\n#define PWR_CR3_EWUP3             PWR_CR3_EWUP3_Msk                            /*!< Enable external WKUP pin 3 */\n#define PWR_CR3_EWUP4_Pos         (3U)\n#define PWR_CR3_EWUP4_Msk         (0x1UL << PWR_CR3_EWUP4_Pos)                 /*!< 0x00000004 */\n#define PWR_CR3_EWUP4             PWR_CR3_EWUP4_Msk                            /*!< Enable external WKUP pin 4 */\n#define PWR_CR3_EWUP6_Pos         (5U)\n#define PWR_CR3_EWUP6_Msk         (0x1UL << PWR_CR3_EWUP6_Pos)                 /*!< 0x00000020 */\n#define PWR_CR3_EWUP6             PWR_CR3_EWUP6_Msk                            /*!< Enable external WKUP pin 6 */\n#define PWR_CR3_APC_Pos           (10U)\n#define PWR_CR3_APC_Msk           (0x1UL << PWR_CR3_APC_Pos)                   /*!< 0x00000400 */\n#define PWR_CR3_APC               PWR_CR3_APC_Msk                              /*!< Apply pull-up and pull-down configuration */\n#define PWR_CR3_EIWUL_Pos         (15U)\n#define PWR_CR3_EIWUL_Msk         (0x1UL << PWR_CR3_EIWUL_Pos)                 /*!< 0x00008000 */\n#define PWR_CR3_EIWUL             PWR_CR3_EIWUL_Msk                            /*!< Enable Internal Wake-up line */\n\n/********************  Bit definition for PWR_CR4 register  ********************/\n#define PWR_CR4_WP_Pos            (0U)\n#define PWR_CR4_WP_Msk            (0x2FUL << PWR_CR4_WP_Pos)                   /*!< 0x0000002F */\n#define PWR_CR4_WP                PWR_CR4_WP_Msk                               /*!< all Wake-Up Line polarity */\n#define PWR_CR4_WP1_Pos           (0U)\n#define PWR_CR4_WP1_Msk           (0x1UL << PWR_CR4_WP1_Pos)                   /*!< 0x00000001 */\n#define PWR_CR4_WP1               PWR_CR4_WP1_Msk                              /*!< Wake-Up Line 1 polarity */\n#define PWR_CR4_WP2_Pos           (1U)\n#define PWR_CR4_WP2_Msk           (0x1UL << PWR_CR4_WP2_Pos)                   /*!< 0x00000002 */\n#define PWR_CR4_WP2               PWR_CR4_WP2_Msk                              /*!< Wake-Up Line 2 polarity */\n#define PWR_CR4_WP3_Pos           (2U)\n#define PWR_CR4_WP3_Msk           (0x1UL << PWR_CR4_WP3_Pos)                   /*!< 0x00000004 */\n#define PWR_CR4_WP3               PWR_CR4_WP3_Msk                              /*!< Wake-Up Line 3 polarity */\n#define PWR_CR4_WP4_Pos           (3U)\n#define PWR_CR4_WP4_Msk           (0x1UL << PWR_CR4_WP4_Pos)                   /*!< 0x00000008 */\n#define PWR_CR4_WP4               PWR_CR4_WP4_Msk                              /*!< Wake-Up Line 4 polarity */\n#define PWR_CR4_WP6_Pos           (5U)\n#define PWR_CR4_WP6_Msk           (0x1UL << PWR_CR4_WP6_Pos)                   /*!< 0x00000020 */\n#define PWR_CR4_WP6               PWR_CR4_WP6_Msk                              /*!< Wake-Up Line 6 polarity */\n\n/********************  Bit definition for PWR_SR1 register  ********************/\n#define PWR_SR1_WUF_Pos           (0U)\n#define PWR_SR1_WUF_Msk           (0x2FUL << PWR_SR1_WUF_Pos)                  /*!< 0x0000002F */\n#define PWR_SR1_WUF               PWR_SR1_WUF_Msk                              /*!< Wakeup Flags  */\n#define PWR_SR1_WUF1_Pos          (0U)\n#define PWR_SR1_WUF1_Msk          (0x1UL << PWR_SR1_WUF1_Pos)                  /*!< 0x00000001 */\n#define PWR_SR1_WUF1              PWR_SR1_WUF1_Msk                             /*!< Wakeup Flag 1 */\n#define PWR_SR1_WUF2_Pos          (1U)\n#define PWR_SR1_WUF2_Msk          (0x1UL << PWR_SR1_WUF2_Pos)                  /*!< 0x00000002 */\n#define PWR_SR1_WUF2              PWR_SR1_WUF2_Msk                             /*!< Wakeup Flag 2 */\n#define PWR_SR1_WUF3_Pos          (2U)\n#define PWR_SR1_WUF3_Msk          (0x1UL << PWR_SR1_WUF3_Pos)                  /*!< 0x00000004 */\n#define PWR_SR1_WUF3              PWR_SR1_WUF3_Msk                             /*!< Wakeup Flag 3 */\n#define PWR_SR1_WUF4_Pos          (3U)\n#define PWR_SR1_WUF4_Msk          (0x1UL << PWR_SR1_WUF4_Pos)                  /*!< 0x00000008 */\n#define PWR_SR1_WUF4              PWR_SR1_WUF4_Msk                             /*!< Wakeup Flag 4 */\n#define PWR_SR1_WUF6_Pos          (5U)\n#define PWR_SR1_WUF6_Msk          (0x1UL << PWR_SR1_WUF6_Pos)                  /*!< 0x00000020 */\n#define PWR_SR1_WUF6              PWR_SR1_WUF6_Msk                             /*!< Wakeup Flag 6 */\n#define PWR_SR1_SBF_Pos           (8U)\n#define PWR_SR1_SBF_Msk           (0x1UL << PWR_SR1_SBF_Pos)                   /*!< 0x00000100 */\n#define PWR_SR1_SBF               PWR_SR1_SBF_Msk                              /*!< Standby Flag  */\n#define PWR_SR1_WUFI_Pos          (15U)\n#define PWR_SR1_WUFI_Msk          (0x1UL << PWR_SR1_WUFI_Pos)                  /*!< 0x00008000 */\n#define PWR_SR1_WUFI              PWR_SR1_WUFI_Msk                             /*!< Wakeup Flag Internal */\n\n/********************  Bit definition for PWR_SR2 register  ********************/\n#define PWR_SR2_FLASH_RDY_Pos     (7U)\n#define PWR_SR2_FLASH_RDY_Msk     (0x1UL << PWR_SR2_FLASH_RDY_Pos)             /*!< 0x00000080 */\n#define PWR_SR2_FLASH_RDY         PWR_SR2_FLASH_RDY_Msk                        /*!< Flash Ready */\n#define PWR_SR2_REGLPF_Pos        (9U)\n#define PWR_SR2_REGLPF_Msk        (0x1UL << PWR_SR2_REGLPF_Pos)                /*!< 0x00000200 */\n#define PWR_SR2_REGLPF            PWR_SR2_REGLPF_Msk                           /*!< Regulator Low Power flag    */\n\n/********************  Bit definition for PWR_SCR register  ********************/\n#define PWR_SCR_CWUF_Pos          (0U)\n#define PWR_SCR_CWUF_Msk          (0x2FUL << PWR_SCR_CWUF_Pos)                 /*!< 0x0000002F */\n#define PWR_SCR_CWUF              PWR_SCR_CWUF_Msk                             /*!< Clear Wake-up Flags  */\n#define PWR_SCR_CWUF1_Pos         (0U)\n#define PWR_SCR_CWUF1_Msk         (0x1UL << PWR_SCR_CWUF1_Pos)                 /*!< 0x00000001 */\n#define PWR_SCR_CWUF1             PWR_SCR_CWUF1_Msk                            /*!< Clear Wake-up Flag 1 */\n#define PWR_SCR_CWUF2_Pos         (1U)\n#define PWR_SCR_CWUF2_Msk         (0x1UL << PWR_SCR_CWUF2_Pos)                 /*!< 0x00000002 */\n#define PWR_SCR_CWUF2             PWR_SCR_CWUF2_Msk                            /*!< Clear Wake-up Flag 2 */\n#define PWR_SCR_CWUF3_Pos         (2U)\n#define PWR_SCR_CWUF3_Msk         (0x1UL << PWR_SCR_CWUF3_Pos)                 /*!< 0x00000004 */\n#define PWR_SCR_CWUF3             PWR_SCR_CWUF3_Msk                            /*!< Clear Wake-up Flag 3 */\n#define PWR_SCR_CWUF4_Pos         (3U)\n#define PWR_SCR_CWUF4_Msk         (0x1UL << PWR_SCR_CWUF4_Pos)                 /*!< 0x00000008 */\n#define PWR_SCR_CWUF4             PWR_SCR_CWUF4_Msk                            /*!< Clear Wake-up Flag 4 */\n#define PWR_SCR_CWUF6_Pos         (5U)\n#define PWR_SCR_CWUF6_Msk         (0x1UL << PWR_SCR_CWUF6_Pos)                 /*!< 0x00000020 */\n#define PWR_SCR_CWUF6             PWR_SCR_CWUF6_Msk                            /*!< Clear Wake-up Flag 6 */\n#define PWR_SCR_CSBF_Pos          (8U)\n#define PWR_SCR_CSBF_Msk          (0x1UL << PWR_SCR_CSBF_Pos)                  /*!< 0x00000100 */\n#define PWR_SCR_CSBF              PWR_SCR_CSBF_Msk                             /*!< Clear Standby Flag  */\n\n/********************  Bit definition for PWR_PUCRA register  *****************/\n#define PWR_PUCRA_PU0_Pos         (0U)\n#define PWR_PUCRA_PU0_Msk         (0x1UL << PWR_PUCRA_PU0_Pos)                 /*!< 0x00000001 */\n#define PWR_PUCRA_PU0             PWR_PUCRA_PU0_Msk                            /*!< Pin PA0 Pull-Up set */\n#define PWR_PUCRA_PU1_Pos         (1U)\n#define PWR_PUCRA_PU1_Msk         (0x1UL << PWR_PUCRA_PU1_Pos)                 /*!< 0x00000002 */\n#define PWR_PUCRA_PU1             PWR_PUCRA_PU1_Msk                            /*!< Pin PA1 Pull-Up set */\n#define PWR_PUCRA_PU2_Pos         (2U)\n#define PWR_PUCRA_PU2_Msk         (0x1UL << PWR_PUCRA_PU2_Pos)                 /*!< 0x00000004 */\n#define PWR_PUCRA_PU2             PWR_PUCRA_PU2_Msk                            /*!< Pin PA2 Pull-Up set */\n#define PWR_PUCRA_PU3_Pos         (3U)\n#define PWR_PUCRA_PU3_Msk         (0x1UL << PWR_PUCRA_PU3_Pos)                 /*!< 0x00000008 */\n#define PWR_PUCRA_PU3             PWR_PUCRA_PU3_Msk                            /*!< Pin PA3 Pull-Up set */\n#define PWR_PUCRA_PU4_Pos         (4U)\n#define PWR_PUCRA_PU4_Msk         (0x1UL << PWR_PUCRA_PU4_Pos)                 /*!< 0x00000010 */\n#define PWR_PUCRA_PU4             PWR_PUCRA_PU4_Msk                            /*!< Pin PA4 Pull-Up set */\n#define PWR_PUCRA_PU5_Pos         (5U)\n#define PWR_PUCRA_PU5_Msk         (0x1UL << PWR_PUCRA_PU5_Pos)                 /*!< 0x00000020 */\n#define PWR_PUCRA_PU5             PWR_PUCRA_PU5_Msk                            /*!< Pin PA5 Pull-Up set */\n#define PWR_PUCRA_PU6_Pos         (6U)\n#define PWR_PUCRA_PU6_Msk         (0x1UL << PWR_PUCRA_PU6_Pos)                 /*!< 0x00000040 */\n#define PWR_PUCRA_PU6             PWR_PUCRA_PU6_Msk                            /*!< Pin PA6 Pull-Up set */\n#define PWR_PUCRA_PU7_Pos         (7U)\n#define PWR_PUCRA_PU7_Msk         (0x1UL << PWR_PUCRA_PU7_Pos)                 /*!< 0x00000080 */\n#define PWR_PUCRA_PU7             PWR_PUCRA_PU7_Msk                            /*!< Pin PA7 Pull-Up set */\n#define PWR_PUCRA_PU8_Pos         (8U)\n#define PWR_PUCRA_PU8_Msk         (0x1UL << PWR_PUCRA_PU8_Pos)                 /*!< 0x00000100 */\n#define PWR_PUCRA_PU8             PWR_PUCRA_PU8_Msk                            /*!< Pin PA8 Pull-Up set */\n#define PWR_PUCRA_PU9_Pos         (9U)\n#define PWR_PUCRA_PU9_Msk         (0x1UL << PWR_PUCRA_PU9_Pos)                 /*!< 0x00000200 */\n#define PWR_PUCRA_PU9             PWR_PUCRA_PU9_Msk                            /*!< Pin PA9 Pull-Up set */\n#define PWR_PUCRA_PU10_Pos        (10U)\n#define PWR_PUCRA_PU10_Msk        (0x1UL << PWR_PUCRA_PU10_Pos)                /*!< 0x00000400 */\n#define PWR_PUCRA_PU10            PWR_PUCRA_PU10_Msk                           /*!< Pin PA10 Pull-Up set */\n#define PWR_PUCRA_PU11_Pos        (11U)\n#define PWR_PUCRA_PU11_Msk        (0x1UL << PWR_PUCRA_PU11_Pos)                /*!< 0x00000800 */\n#define PWR_PUCRA_PU11            PWR_PUCRA_PU11_Msk                           /*!< Pin PA11 Pull-Up set */\n#define PWR_PUCRA_PU12_Pos        (12U)\n#define PWR_PUCRA_PU12_Msk        (0x1UL << PWR_PUCRA_PU12_Pos)                /*!< 0x00001000 */\n#define PWR_PUCRA_PU12            PWR_PUCRA_PU12_Msk                           /*!< Pin PA12 Pull-Up set */\n#define PWR_PUCRA_PU13_Pos        (13U)\n#define PWR_PUCRA_PU13_Msk        (0x1UL << PWR_PUCRA_PU13_Pos)                /*!< 0x00002000 */\n#define PWR_PUCRA_PU13            PWR_PUCRA_PU13_Msk                           /*!< Pin PA13 Pull-Up set */\n#define PWR_PUCRA_PU14_Pos        (14U)\n#define PWR_PUCRA_PU14_Msk        (0x1UL << PWR_PUCRA_PU14_Pos)                /*!< 0x00004000 */\n#define PWR_PUCRA_PU14            PWR_PUCRA_PU14_Msk                           /*!< Pin PA14 Pull-Up set */\n#define PWR_PUCRA_PU15_Pos        (15U)\n#define PWR_PUCRA_PU15_Msk        (0x1UL << PWR_PUCRA_PU15_Pos)                /*!< 0x00008000 */\n#define PWR_PUCRA_PU15            PWR_PUCRA_PU15_Msk                           /*!< Pin PA15 Pull-Up set */\n/********************  Bit definition for PWR_PDCRA register  *****************/\n#define PWR_PDCRA_PD0_Pos         (0U)\n#define PWR_PDCRA_PD0_Msk         (0x1UL << PWR_PDCRA_PD0_Pos)                 /*!< 0x00000001 */\n#define PWR_PDCRA_PD0             PWR_PDCRA_PD0_Msk                            /*!< Pin PA0 Pull-Down set */\n#define PWR_PDCRA_PD1_Pos         (1U)\n#define PWR_PDCRA_PD1_Msk         (0x1UL << PWR_PDCRA_PD1_Pos)                 /*!< 0x00000002 */\n#define PWR_PDCRA_PD1             PWR_PDCRA_PD1_Msk                            /*!< Pin PA1 Pull-Down set */\n#define PWR_PDCRA_PD2_Pos         (2U)\n#define PWR_PDCRA_PD2_Msk         (0x1UL << PWR_PDCRA_PD2_Pos)                 /*!< 0x00000004 */\n#define PWR_PDCRA_PD2             PWR_PDCRA_PD2_Msk                            /*!< Pin PA2 Pull-Down set */\n#define PWR_PDCRA_PD3_Pos         (3U)\n#define PWR_PDCRA_PD3_Msk         (0x1UL << PWR_PDCRA_PD3_Pos)                 /*!< 0x00000008 */\n#define PWR_PDCRA_PD3             PWR_PDCRA_PD3_Msk                            /*!< Pin PA3 Pull-Down set */\n#define PWR_PDCRA_PD4_Pos         (4U)\n#define PWR_PDCRA_PD4_Msk         (0x1UL << PWR_PDCRA_PD4_Pos)                 /*!< 0x00000010 */\n#define PWR_PDCRA_PD4             PWR_PDCRA_PD4_Msk                            /*!< Pin PA4 Pull-Down set */\n#define PWR_PDCRA_PD5_Pos         (5U)\n#define PWR_PDCRA_PD5_Msk         (0x1UL << PWR_PDCRA_PD5_Pos)                 /*!< 0x00000020 */\n#define PWR_PDCRA_PD5             PWR_PDCRA_PD5_Msk                            /*!< Pin PA5 Pull-Down set */\n#define PWR_PDCRA_PD6_Pos         (6U)\n#define PWR_PDCRA_PD6_Msk         (0x1UL << PWR_PDCRA_PD6_Pos)                 /*!< 0x00000040 */\n#define PWR_PDCRA_PD6             PWR_PDCRA_PD6_Msk                            /*!< Pin PA6 Pull-Down set */\n#define PWR_PDCRA_PD7_Pos         (7U)\n#define PWR_PDCRA_PD7_Msk         (0x1UL << PWR_PDCRA_PD7_Pos)                 /*!< 0x00000080 */\n#define PWR_PDCRA_PD7             PWR_PDCRA_PD7_Msk                            /*!< Pin PA7 Pull-Down set */\n#define PWR_PDCRA_PD8_Pos         (8U)\n#define PWR_PDCRA_PD8_Msk         (0x1UL << PWR_PDCRA_PD8_Pos)                 /*!< 0x00000100 */\n#define PWR_PDCRA_PD8             PWR_PDCRA_PD8_Msk                            /*!< Pin PA8 Pull-Down set */\n#define PWR_PDCRA_PD9_Pos         (9U)\n#define PWR_PDCRA_PD9_Msk         (0x1UL << PWR_PDCRA_PD9_Pos)                 /*!< 0x00000200 */\n#define PWR_PDCRA_PD9             PWR_PDCRA_PD9_Msk                            /*!< Pin PA9 Pull-Down set */\n#define PWR_PDCRA_PD10_Pos        (10U)\n#define PWR_PDCRA_PD10_Msk        (0x1UL << PWR_PDCRA_PD10_Pos)                /*!< 0x00000400 */\n#define PWR_PDCRA_PD10            PWR_PDCRA_PD10_Msk                           /*!< Pin PA10 Pull-Down set */\n#define PWR_PDCRA_PD11_Pos        (11U)\n#define PWR_PDCRA_PD11_Msk        (0x1UL << PWR_PDCRA_PD11_Pos)                /*!< 0x00000800 */\n#define PWR_PDCRA_PD11            PWR_PDCRA_PD11_Msk                           /*!< Pin PA11 Pull-Down set */\n#define PWR_PDCRA_PD12_Pos        (12U)\n#define PWR_PDCRA_PD12_Msk        (0x1UL << PWR_PDCRA_PD12_Pos)                /*!< 0x00001000 */\n#define PWR_PDCRA_PD12            PWR_PDCRA_PD12_Msk                           /*!< Pin PA12 Pull-Down set */\n#define PWR_PDCRA_PD13_Pos        (13U)\n#define PWR_PDCRA_PD13_Msk        (0x1UL << PWR_PDCRA_PD13_Pos)                /*!< 0x00002000 */\n#define PWR_PDCRA_PD13            PWR_PDCRA_PD13_Msk                           /*!< Pin PA13 Pull-Down set */\n#define PWR_PDCRA_PD14_Pos        (14U)\n#define PWR_PDCRA_PD14_Msk        (0x1UL << PWR_PDCRA_PD14_Pos)                /*!< 0x00004000 */\n#define PWR_PDCRA_PD14            PWR_PDCRA_PD14_Msk                           /*!< Pin PA14 Pull-Down set */\n#define PWR_PDCRA_PD15_Pos        (15U)\n#define PWR_PDCRA_PD15_Msk        (0x1UL << PWR_PDCRA_PD15_Pos)                /*!< 0x00008000 */\n#define PWR_PDCRA_PD15            PWR_PDCRA_PD15_Msk                           /*!< Pin PA15 Pull-Down set */\n/********************  Bit definition for PWR_PUCRB register  *****************/\n#define PWR_PUCRB_PU0_Pos         (0U)\n#define PWR_PUCRB_PU0_Msk         (0x1UL << PWR_PUCRB_PU0_Pos)                 /*!< 0x00000001 */\n#define PWR_PUCRB_PU0             PWR_PUCRB_PU0_Msk                            /*!< Pin PB0 Pull-Up set */\n#define PWR_PUCRB_PU1_Pos         (1U)\n#define PWR_PUCRB_PU1_Msk         (0x1UL << PWR_PUCRB_PU1_Pos)                 /*!< 0x00000002 */\n#define PWR_PUCRB_PU1             PWR_PUCRB_PU1_Msk                            /*!< Pin PB1 Pull-Up set */\n#define PWR_PUCRB_PU2_Pos         (2U)\n#define PWR_PUCRB_PU2_Msk         (0x1UL << PWR_PUCRB_PU2_Pos)                 /*!< 0x00000004 */\n#define PWR_PUCRB_PU2             PWR_PUCRB_PU2_Msk                            /*!< Pin PB2 Pull-Up set */\n#define PWR_PUCRB_PU3_Pos         (3U)\n#define PWR_PUCRB_PU3_Msk         (0x1UL << PWR_PUCRB_PU3_Pos)                 /*!< 0x00000008 */\n#define PWR_PUCRB_PU3             PWR_PUCRB_PU3_Msk                            /*!< Pin PB3 Pull-Up set */\n#define PWR_PUCRB_PU4_Pos         (4U)\n#define PWR_PUCRB_PU4_Msk         (0x1UL << PWR_PUCRB_PU4_Pos)                 /*!< 0x00000010 */\n#define PWR_PUCRB_PU4             PWR_PUCRB_PU4_Msk                            /*!< Pin PB4 Pull-Up set */\n#define PWR_PUCRB_PU5_Pos         (5U)\n#define PWR_PUCRB_PU5_Msk         (0x1UL << PWR_PUCRB_PU5_Pos)                 /*!< 0x00000020 */\n#define PWR_PUCRB_PU5             PWR_PUCRB_PU5_Msk                            /*!< Pin PB5 Pull-Up set */\n#define PWR_PUCRB_PU6_Pos         (6U)\n#define PWR_PUCRB_PU6_Msk         (0x1UL << PWR_PUCRB_PU6_Pos)                 /*!< 0x00000040 */\n#define PWR_PUCRB_PU6             PWR_PUCRB_PU6_Msk                            /*!< Pin PB6 Pull-Up set */\n#define PWR_PUCRB_PU7_Pos         (7U)\n#define PWR_PUCRB_PU7_Msk         (0x1UL << PWR_PUCRB_PU7_Pos)                 /*!< 0x00000080 */\n#define PWR_PUCRB_PU7             PWR_PUCRB_PU7_Msk                            /*!< Pin PB7 Pull-Up set */\n#define PWR_PUCRB_PU8_Pos         (8U)\n#define PWR_PUCRB_PU8_Msk         (0x1UL << PWR_PUCRB_PU8_Pos)                 /*!< 0x00000100 */\n#define PWR_PUCRB_PU8             PWR_PUCRB_PU8_Msk                            /*!< Pin PB8 Pull-Up set */\n#define PWR_PUCRB_PU9_Pos         (9U)\n#define PWR_PUCRB_PU9_Msk         (0x1UL << PWR_PUCRB_PU9_Pos)                 /*!< 0x00000200 */\n#define PWR_PUCRB_PU9             PWR_PUCRB_PU9_Msk                            /*!< Pin PB9 Pull-Up set */\n#define PWR_PUCRB_PU10_Pos        (10U)\n#define PWR_PUCRB_PU10_Msk        (0x1UL << PWR_PUCRB_PU10_Pos)                /*!< 0x00000400 */\n#define PWR_PUCRB_PU10            PWR_PUCRB_PU10_Msk                           /*!< Pin PB10 Pull-Up set */\n#define PWR_PUCRB_PU11_Pos        (11U)\n#define PWR_PUCRB_PU11_Msk        (0x1UL << PWR_PUCRB_PU11_Pos)                /*!< 0x00000800 */\n#define PWR_PUCRB_PU11            PWR_PUCRB_PU11_Msk                           /*!< Pin PB11 Pull-Up set */\n#define PWR_PUCRB_PU12_Pos        (12U)\n#define PWR_PUCRB_PU12_Msk        (0x1UL << PWR_PUCRB_PU12_Pos)                /*!< 0x00001000 */\n#define PWR_PUCRB_PU12            PWR_PUCRB_PU12_Msk                           /*!< Pin PB12 Pull-Up set */\n#define PWR_PUCRB_PU13_Pos        (13U)\n#define PWR_PUCRB_PU13_Msk        (0x1UL << PWR_PUCRB_PU13_Pos)                /*!< 0x00002000 */\n#define PWR_PUCRB_PU13            PWR_PUCRB_PU13_Msk                           /*!< Pin PB13 Pull-Up set */\n#define PWR_PUCRB_PU14_Pos        (14U)\n#define PWR_PUCRB_PU14_Msk        (0x1UL << PWR_PUCRB_PU14_Pos)                /*!< 0x00004000 */\n#define PWR_PUCRB_PU14            PWR_PUCRB_PU14_Msk                           /*!< Pin PB14 Pull-Up set */\n#define PWR_PUCRB_PU15_Pos        (15U)\n#define PWR_PUCRB_PU15_Msk        (0x1UL << PWR_PUCRB_PU15_Pos)                /*!< 0x00008000 */\n#define PWR_PUCRB_PU15            PWR_PUCRB_PU15_Msk                           /*!< Pin PB15 Pull-Up set */\n/********************  Bit definition for PWR_PDCRB register  *****************/\n#define PWR_PDCRB_PD0_Pos         (0U)\n#define PWR_PDCRB_PD0_Msk         (0x1UL << PWR_PDCRB_PD0_Pos)                 /*!< 0x00000001 */\n#define PWR_PDCRB_PD0             PWR_PDCRB_PD0_Msk                            /*!< Pin PB0 Pull-Down set */\n#define PWR_PDCRB_PD1_Pos         (1U)\n#define PWR_PDCRB_PD1_Msk         (0x1UL << PWR_PDCRB_PD1_Pos)                 /*!< 0x00000002 */\n#define PWR_PDCRB_PD1             PWR_PDCRB_PD1_Msk                            /*!< Pin PB1 Pull-Down set */\n#define PWR_PDCRB_PD2_Pos         (2U)\n#define PWR_PDCRB_PD2_Msk         (0x1UL << PWR_PDCRB_PD2_Pos)                 /*!< 0x00000004 */\n#define PWR_PDCRB_PD2             PWR_PDCRB_PD2_Msk                            /*!< Pin PB2 Pull-Down set */\n#define PWR_PDCRB_PD3_Pos         (3U)\n#define PWR_PDCRB_PD3_Msk         (0x1UL << PWR_PDCRB_PD3_Pos)                 /*!< 0x00000008 */\n#define PWR_PDCRB_PD3             PWR_PDCRB_PD3_Msk                            /*!< Pin PB3 Pull-Down set */\n#define PWR_PDCRB_PD4_Pos         (4U)\n#define PWR_PDCRB_PD4_Msk         (0x1UL << PWR_PDCRB_PD4_Pos)                 /*!< 0x00000010 */\n#define PWR_PDCRB_PD4             PWR_PDCRB_PD4_Msk                            /*!< Pin PB4 Pull-Down set */\n#define PWR_PDCRB_PD5_Pos         (5U)\n#define PWR_PDCRB_PD5_Msk         (0x1UL << PWR_PDCRB_PD5_Pos)                 /*!< 0x00000020 */\n#define PWR_PDCRB_PD5             PWR_PDCRB_PD5_Msk                            /*!< Pin PB5 Pull-Down set */\n#define PWR_PDCRB_PD6_Pos         (6U)\n#define PWR_PDCRB_PD6_Msk         (0x1UL << PWR_PDCRB_PD6_Pos)                 /*!< 0x00000040 */\n#define PWR_PDCRB_PD6             PWR_PDCRB_PD6_Msk                            /*!< Pin PB6 Pull-Down set */\n#define PWR_PDCRB_PD7_Pos         (7U)\n#define PWR_PDCRB_PD7_Msk         (0x1UL << PWR_PDCRB_PD7_Pos)                 /*!< 0x00000080 */\n#define PWR_PDCRB_PD7             PWR_PDCRB_PD7_Msk                            /*!< Pin PB7 Pull-Down set */\n#define PWR_PDCRB_PD8_Pos         (8U)\n#define PWR_PDCRB_PD8_Msk         (0x1UL << PWR_PDCRB_PD8_Pos)                 /*!< 0x00000100 */\n#define PWR_PDCRB_PD8             PWR_PDCRB_PD8_Msk                            /*!< Pin PB8 Pull-Down set */\n#define PWR_PDCRB_PD9_Pos         (9U)\n#define PWR_PDCRB_PD9_Msk         (0x1UL << PWR_PDCRB_PD9_Pos)                 /*!< 0x00000200 */\n#define PWR_PDCRB_PD9             PWR_PDCRB_PD9_Msk                            /*!< Pin PB9 Pull-Down set */\n#define PWR_PDCRB_PD10_Pos        (10U)\n#define PWR_PDCRB_PD10_Msk        (0x1UL << PWR_PDCRB_PD10_Pos)                /*!< 0x00000400 */\n#define PWR_PDCRB_PD10            PWR_PDCRB_PD10_Msk                           /*!< Pin PB10 Pull-Down set */\n#define PWR_PDCRB_PD11_Pos        (11U)\n#define PWR_PDCRB_PD11_Msk        (0x1UL << PWR_PDCRB_PD11_Pos)                /*!< 0x00000800 */\n#define PWR_PDCRB_PD11            PWR_PDCRB_PD11_Msk                           /*!< Pin PB11 Pull-Down set */\n#define PWR_PDCRB_PD12_Pos        (12U)\n#define PWR_PDCRB_PD12_Msk        (0x1UL << PWR_PDCRB_PD12_Pos)                /*!< 0x00001000 */\n#define PWR_PDCRB_PD12            PWR_PDCRB_PD12_Msk                           /*!< Pin PB12 Pull-Down set */\n#define PWR_PDCRB_PD13_Pos        (13U)\n#define PWR_PDCRB_PD13_Msk        (0x1UL << PWR_PDCRB_PD13_Pos)                /*!< 0x00002000 */\n#define PWR_PDCRB_PD13            PWR_PDCRB_PD13_Msk                           /*!< Pin PB13 Pull-Down set */\n#define PWR_PDCRB_PD14_Pos        (14U)\n#define PWR_PDCRB_PD14_Msk        (0x1UL << PWR_PDCRB_PD14_Pos)                /*!< 0x00004000 */\n#define PWR_PDCRB_PD14            PWR_PDCRB_PD14_Msk                           /*!< Pin PB14 Pull-Down set */\n#define PWR_PDCRB_PD15_Pos        (15U)\n#define PWR_PDCRB_PD15_Msk        (0x1UL << PWR_PDCRB_PD15_Pos)                /*!< 0x00008000 */\n#define PWR_PDCRB_PD15            PWR_PDCRB_PD15_Msk                           /*!< Pin PB15 Pull-Down set */\n/********************  Bit definition for PWR_PUCRC register  *****************/\n#define PWR_PUCRC_PU6_Pos         (6U)\n#define PWR_PUCRC_PU6_Msk         (0x1UL << PWR_PUCRC_PU6_Pos)                 /*!< 0x00000040 */\n#define PWR_PUCRC_PU6             PWR_PUCRC_PU6_Msk                            /*!< Pin PC6 Pull-Up set */\n#define PWR_PUCRC_PU7_Pos         (7U)\n#define PWR_PUCRC_PU7_Msk         (0x1UL << PWR_PUCRC_PU7_Pos)                 /*!< 0x00000080 */\n#define PWR_PUCRC_PU7             PWR_PUCRC_PU7_Msk                            /*!< Pin PC7 Pull-Up set */\n#define PWR_PUCRC_PU13_Pos        (13U)\n#define PWR_PUCRC_PU13_Msk        (0x1UL << PWR_PUCRC_PU13_Pos)                /*!< 0x00002000 */\n#define PWR_PUCRC_PU13            PWR_PUCRC_PU13_Msk                           /*!< Pin PC13 Pull-Up set */\n#define PWR_PUCRC_PU14_Pos        (14U)\n#define PWR_PUCRC_PU14_Msk        (0x1UL << PWR_PUCRC_PU14_Pos)                /*!< 0x00004000 */\n#define PWR_PUCRC_PU14            PWR_PUCRC_PU14_Msk                           /*!< Pin PC14 Pull-Up set */\n#define PWR_PUCRC_PU15_Pos        (15U)\n#define PWR_PUCRC_PU15_Msk        (0x1UL << PWR_PUCRC_PU15_Pos)                /*!< 0x00008000 */\n#define PWR_PUCRC_PU15            PWR_PUCRC_PU15_Msk                           /*!< Pin PC15 Pull-Up set */\n\n/********************  Bit definition for PWR_PDCRC register  *****************/\n#define PWR_PDCRC_PD6_Pos         (6U)\n#define PWR_PDCRC_PD6_Msk         (0x1UL << PWR_PDCRC_PD6_Pos)                 /*!< 0x00000040 */\n#define PWR_PDCRC_PD6             PWR_PDCRC_PD6_Msk                            /*!< Pin PC6 Pull-Down set */\n#define PWR_PDCRC_PD7_Pos         (7U)\n#define PWR_PDCRC_PD7_Msk         (0x1UL << PWR_PDCRC_PD7_Pos)                 /*!< 0x00000080 */\n#define PWR_PDCRC_PD7             PWR_PDCRC_PD7_Msk                            /*!< Pin PC7 Pull-Down set */\n#define PWR_PDCRC_PD13_Pos        (13U)\n#define PWR_PDCRC_PD13_Msk        (0x1UL << PWR_PDCRC_PD13_Pos)                /*!< 0x00002000 */\n#define PWR_PDCRC_PD13            PWR_PDCRC_PD13_Msk                           /*!< Pin PC13 Pull-Down set */\n#define PWR_PDCRC_PD14_Pos        (14U)\n#define PWR_PDCRC_PD14_Msk        (0x1UL << PWR_PDCRC_PD14_Pos)                /*!< 0x00004000 */\n#define PWR_PDCRC_PD14            PWR_PDCRC_PD14_Msk                           /*!< Pin PC14 Pull-Down set */\n#define PWR_PDCRC_PD15_Pos        (15U)\n#define PWR_PDCRC_PD15_Msk        (0x1UL << PWR_PDCRC_PD15_Pos)                /*!< 0x00008000 */\n#define PWR_PDCRC_PD15            PWR_PDCRC_PD15_Msk                           /*!< Pin PC15 Pull-Down set */\n\n/********************  Bit definition for PWR_PUCRD register  *****************/\n#define PWR_PUCRD_PU0_Pos         (0U)\n#define PWR_PUCRD_PU0_Msk         (0x1UL << PWR_PUCRD_PU0_Pos)                 /*!< 0x00000001 */\n#define PWR_PUCRD_PU0             PWR_PUCRD_PU0_Msk                            /*!< Pin PD0 Pull-Up set */\n#define PWR_PUCRD_PU1_Pos         (1U)\n#define PWR_PUCRD_PU1_Msk         (0x1UL << PWR_PUCRD_PU1_Pos)                 /*!< 0x00000002 */\n#define PWR_PUCRD_PU1             PWR_PUCRD_PU1_Msk                            /*!< Pin PD1 Pull-Up set */\n#define PWR_PUCRD_PU2_Pos         (2U)\n#define PWR_PUCRD_PU2_Msk         (0x1UL << PWR_PUCRD_PU2_Pos)                 /*!< 0x00000004 */\n#define PWR_PUCRD_PU2             PWR_PUCRD_PU2_Msk                            /*!< Pin PD2 Pull-Up set */\n#define PWR_PUCRD_PU3_Pos         (3U)\n#define PWR_PUCRD_PU3_Msk         (0x1UL << PWR_PUCRD_PU3_Pos)                 /*!< 0x00000008 */\n#define PWR_PUCRD_PU3             PWR_PUCRD_PU3_Msk                            /*!< Pin PD3 Pull-Up set */\n\n/********************  Bit definition for PWR_PDCRD register  *****************/\n#define PWR_PDCRD_PD0_Pos         (0U)\n#define PWR_PDCRD_PD0_Msk         (0x1UL << PWR_PDCRD_PD0_Pos)                 /*!< 0x00000001 */\n#define PWR_PDCRD_PD0             PWR_PDCRD_PD0_Msk                            /*!< Pin PD0 Pull-Down set */\n#define PWR_PDCRD_PD1_Pos         (1U)\n#define PWR_PDCRD_PD1_Msk         (0x1UL << PWR_PDCRD_PD1_Pos)                 /*!< 0x00000002 */\n#define PWR_PDCRD_PD1             PWR_PDCRD_PD1_Msk                            /*!< Pin PD1 Pull-Down set */\n#define PWR_PDCRD_PD2_Pos         (2U)\n#define PWR_PDCRD_PD2_Msk         (0x1UL << PWR_PDCRD_PD2_Pos)                 /*!< 0x00000004 */\n#define PWR_PDCRD_PD2             PWR_PDCRD_PD2_Msk                            /*!< Pin PD2 Pull-Down set */\n#define PWR_PDCRD_PD3_Pos         (3U)\n#define PWR_PDCRD_PD3_Msk         (0x1UL << PWR_PDCRD_PD3_Pos)                 /*!< 0x00000008 */\n#define PWR_PDCRD_PD3             PWR_PDCRD_PD3_Msk                            /*!< Pin PD3 Pull-Down set */\n/********************  Bit definition for PWR_PUCRF register  *****************/\n#define PWR_PUCRF_PU0_Pos         (0U)\n#define PWR_PUCRF_PU0_Msk         (0x1UL << PWR_PUCRF_PU0_Pos)                 /*!< 0x00000001 */\n#define PWR_PUCRF_PU0             PWR_PUCRF_PU0_Msk                            /*!< Pin PF0 Pull-Up set */\n#define PWR_PUCRF_PU1_Pos         (1U)\n#define PWR_PUCRF_PU1_Msk         (0x1UL << PWR_PUCRF_PU1_Pos)                 /*!< 0x00000002 */\n#define PWR_PUCRF_PU1             PWR_PUCRF_PU1_Msk                            /*!< Pin PF1 Pull-Up set */\n#define PWR_PUCRF_PU2_Pos         (2U)\n#define PWR_PUCRF_PU2_Msk         (0x1UL << PWR_PUCRF_PU2_Pos)                 /*!< 0x00000004 */\n#define PWR_PUCRF_PU2             PWR_PUCRF_PU2_Msk                            /*!< Pin PF2 Pull-Up set */\n\n/********************  Bit definition for PWR_PDCRF register  *****************/\n#define PWR_PDCRF_PD0_Pos         (0U)\n#define PWR_PDCRF_PD0_Msk         (0x1UL << PWR_PDCRF_PD0_Pos)                 /*!< 0x00000001 */\n#define PWR_PDCRF_PD0             PWR_PDCRF_PD0_Msk                            /*!< Pin PF0 Pull-Down set */\n#define PWR_PDCRF_PD1_Pos         (1U)\n#define PWR_PDCRF_PD1_Msk         (0x1UL << PWR_PDCRF_PD1_Pos)                 /*!< 0x00000002 */\n#define PWR_PDCRF_PD1             PWR_PDCRF_PD1_Msk                            /*!< Pin PF1 Pull-Down set */\n#define PWR_PDCRF_PD2_Pos         (2U)\n#define PWR_PDCRF_PD2_Msk         (0x1UL << PWR_PDCRF_PD2_Pos)                 /*!< 0x00000004 */\n#define PWR_PDCRF_PD2             PWR_PDCRF_PD2_Msk                            /*!< Pin PF2 Pull-Down set */\n\n/********************  Bits definition for PWR_BKP1R register  ***************/\n#define PWR_BKP1R_Pos               (0U)\n#define PWR_BKP1R_Msk               (0xFFFFFFFFUL << PWR_BKP1R_Pos)           /*!< 0xFFFFFFFF */\n#define PWR_BKP1R                   PWR_BKP1R_Msk\n\n/********************  Bits definition for PWR_BKP2R register  ***************/\n#define PWR_BKP2R_Pos               (0U)\n#define PWR_BKP2R_Msk               (0xFFFFFFFFUL << PWR_BKP2R_Pos)           /*!< 0xFFFFFFFF */\n#define PWR_BKP2R                   PWR_BKP2R_Msk\n\n/********************  Bits definition for PWR_BKP3R register  ***************/\n#define PWR_BKP3R_Pos               (0U)\n#define PWR_BKP3R_Msk               (0xFFFFFFFFUL << PWR_BKP3R_Pos)           /*!< 0xFFFFFFFF */\n#define PWR_BKP3R                   PWR_BKP3R_Msk\n\n/********************  Bits definition for PWR_BKP4R register  ***************/\n#define PWR_BKP4R_Pos               (0U)\n#define PWR_BKP4R_Msk               (0xFFFFFFFFUL << PWR_BKP4R_Pos)           /*!< 0xFFFFFFFF */\n#define PWR_BKP4R                   PWR_BKP4R_Msk\n/******************************************************************************/\n/*                                                                            */\n/*                           Reset and Clock Control                          */\n/*                                                                            */\n/******************************************************************************/\n\n/********************  Bit definition for RCC_CR register  *****************/\n#define RCC_CR_SYSDIV_Pos                (2U)\n#define RCC_CR_SYSDIV_Msk                (0x7UL << RCC_CR_SYSDIV_Pos)          /*!< 0x0000001C */\n#define RCC_CR_SYSDIV                    RCC_CR_SYSDIV_Msk                     /*!< Clock division factor for system clock */\n#define RCC_CR_SYSDIV_0                  (0x1UL << RCC_CR_SYSDIV_Pos)          /*!< 0x00000004 */\n#define RCC_CR_SYSDIV_1                  (0x2UL << RCC_CR_SYSDIV_Pos)          /*!< 0x00000008 */\n#define RCC_CR_SYSDIV_2                  (0x4UL << RCC_CR_SYSDIV_Pos)          /*!< 0x00000010 */\n#define RCC_CR_HSIKERDIV_Pos             (5U)\n#define RCC_CR_HSIKERDIV_Msk             (0x7UL << RCC_CR_HSIKERDIV_Pos)       /*!< 0x000000E0 */\n#define RCC_CR_HSIKERDIV                 RCC_CR_HSIKERDIV_Msk                  /*!< HSI48 clock division factor for HSI kernel clocks inputs */\n#define RCC_CR_HSIKERDIV_0               (0x1UL << RCC_CR_HSIKERDIV_Pos)       /*!< 0x00000020 */\n#define RCC_CR_HSIKERDIV_1               (0x2UL << RCC_CR_HSIKERDIV_Pos)       /*!< 0x00000040 */\n#define RCC_CR_HSIKERDIV_2               (0x4UL << RCC_CR_HSIKERDIV_Pos)       /*!< 0x00000080 */\n#define RCC_CR_HSION_Pos                 (8U)\n#define RCC_CR_HSION_Msk                 (0x1UL << RCC_CR_HSION_Pos)           /*!< 0x00000100 */\n#define RCC_CR_HSION                     RCC_CR_HSION_Msk                      /*!< Internal High Speed clock enable */\n#define RCC_CR_HSIKERON_Pos              (9U)\n#define RCC_CR_HSIKERON_Msk              (0x1UL << RCC_CR_HSIKERON_Pos)        /*!< 0x00000200 */\n#define RCC_CR_HSIKERON                  RCC_CR_HSIKERON_Msk                   /*!< Internal High Speed clock enable for some IPs Kernel */\n#define RCC_CR_HSIRDY_Pos                (10U)\n#define RCC_CR_HSIRDY_Msk                (0x1UL << RCC_CR_HSIRDY_Pos)          /*!< 0x00000400 */\n#define RCC_CR_HSIRDY                    RCC_CR_HSIRDY_Msk                     /*!< Internal High Speed clock ready flag */\n#define RCC_CR_HSIDIV_Pos                (11U)\n#define RCC_CR_HSIDIV_Msk                (0x7UL << RCC_CR_HSIDIV_Pos)          /*!< 0x00003800 */\n#define RCC_CR_HSIDIV                    RCC_CR_HSIDIV_Msk                     /*!< HSIDIV[13:11] Internal High Speed clock division factor */\n#define RCC_CR_HSIDIV_0                  (0x1UL << RCC_CR_HSIDIV_Pos)          /*!< 0x00000800 */\n#define RCC_CR_HSIDIV_1                  (0x2UL << RCC_CR_HSIDIV_Pos)          /*!< 0x00001000 */\n#define RCC_CR_HSIDIV_2                  (0x4UL << RCC_CR_HSIDIV_Pos)          /*!< 0x00002000 */\n#define RCC_CR_HSEON_Pos                 (16U)\n#define RCC_CR_HSEON_Msk                 (0x1UL << RCC_CR_HSEON_Pos)           /*!< 0x00010000 */\n#define RCC_CR_HSEON                     RCC_CR_HSEON_Msk                      /*!< External High Speed clock enable */\n#define RCC_CR_HSERDY_Pos                (17U)\n#define RCC_CR_HSERDY_Msk                (0x1UL << RCC_CR_HSERDY_Pos)          /*!< 0x00020000 */\n#define RCC_CR_HSERDY                    RCC_CR_HSERDY_Msk                     /*!< External High Speed clock ready */\n#define RCC_CR_HSEBYP_Pos                (18U)\n#define RCC_CR_HSEBYP_Msk                (0x1UL << RCC_CR_HSEBYP_Pos)          /*!< 0x00040000 */\n#define RCC_CR_HSEBYP                    RCC_CR_HSEBYP_Msk                     /*!< External High Speed clock Bypass */\n#define RCC_CR_CSSON_Pos                 (19U)\n#define RCC_CR_CSSON_Msk                 (0x1UL << RCC_CR_CSSON_Pos)           /*!< 0x00080000 */\n#define RCC_CR_CSSON                     RCC_CR_CSSON_Msk                      /*!< HSE Clock Security System enable */\n\n/********************  Bit definition for RCC_ICSCR register  ***************/\n/*!< HSICAL configuration */\n#define RCC_ICSCR_HSICAL_Pos             (0U)\n#define RCC_ICSCR_HSICAL_Msk             (0xFFUL << RCC_ICSCR_HSICAL_Pos)      /*!< 0x000000FF */\n#define RCC_ICSCR_HSICAL                 RCC_ICSCR_HSICAL_Msk                  /*!< HSICAL[7:0] bits */\n#define RCC_ICSCR_HSICAL_0               (0x01UL << RCC_ICSCR_HSICAL_Pos)      /*!< 0x00000001 */\n#define RCC_ICSCR_HSICAL_1               (0x02UL << RCC_ICSCR_HSICAL_Pos)      /*!< 0x00000002 */\n#define RCC_ICSCR_HSICAL_2               (0x04UL << RCC_ICSCR_HSICAL_Pos)      /*!< 0x00000004 */\n#define RCC_ICSCR_HSICAL_3               (0x08UL << RCC_ICSCR_HSICAL_Pos)      /*!< 0x00000008 */\n#define RCC_ICSCR_HSICAL_4               (0x10UL << RCC_ICSCR_HSICAL_Pos)      /*!< 0x00000010 */\n#define RCC_ICSCR_HSICAL_5               (0x20UL << RCC_ICSCR_HSICAL_Pos)      /*!< 0x00000020 */\n#define RCC_ICSCR_HSICAL_6               (0x40UL << RCC_ICSCR_HSICAL_Pos)      /*!< 0x00000040 */\n#define RCC_ICSCR_HSICAL_7               (0x80UL << RCC_ICSCR_HSICAL_Pos)      /*!< 0x00000080 */\n\n/*!< HSITRIM configuration */\n#define RCC_ICSCR_HSITRIM_Pos            (8U)\n#define RCC_ICSCR_HSITRIM_Msk            (0x7FUL << RCC_ICSCR_HSITRIM_Pos)     /*!< 0x00007F00 */\n#define RCC_ICSCR_HSITRIM                RCC_ICSCR_HSITRIM_Msk                 /*!< HSITRIM[14:8] bits */\n#define RCC_ICSCR_HSITRIM_0              (0x01UL << RCC_ICSCR_HSITRIM_Pos)     /*!< 0x00000100 */\n#define RCC_ICSCR_HSITRIM_1              (0x02UL << RCC_ICSCR_HSITRIM_Pos)     /*!< 0x00000200 */\n#define RCC_ICSCR_HSITRIM_2              (0x04UL << RCC_ICSCR_HSITRIM_Pos)     /*!< 0x00000400 */\n#define RCC_ICSCR_HSITRIM_3              (0x08UL << RCC_ICSCR_HSITRIM_Pos)     /*!< 0x00000800 */\n#define RCC_ICSCR_HSITRIM_4              (0x10UL << RCC_ICSCR_HSITRIM_Pos)     /*!< 0x00001000 */\n#define RCC_ICSCR_HSITRIM_5              (0x20UL << RCC_ICSCR_HSITRIM_Pos)     /*!< 0x00002000 */\n#define RCC_ICSCR_HSITRIM_6              (0x40UL << RCC_ICSCR_HSITRIM_Pos)     /*!< 0x00004000 */\n\n/********************  Bit definition for RCC_CFGR register  ***************/\n/*!< SW configuration */\n#define RCC_CFGR_SW_Pos                (0U)\n#define RCC_CFGR_SW_Msk                (0x7UL << RCC_CFGR_SW_Pos)              /*!< 0x00000007 */\n#define RCC_CFGR_SW                    RCC_CFGR_SW_Msk                         /*!< SW[2:0] bits (System clock Switch) */\n#define RCC_CFGR_SW_0                  (0x1UL << RCC_CFGR_SW_Pos)              /*!< 0x00000001 */\n#define RCC_CFGR_SW_1                  (0x2UL << RCC_CFGR_SW_Pos)              /*!< 0x00000002 */\n#define RCC_CFGR_SW_2                  (0x4UL << RCC_CFGR_SW_Pos)              /*!< 0x00000004 */\n\n/*!< SWS configuration */\n#define RCC_CFGR_SWS_Pos               (3U)\n#define RCC_CFGR_SWS_Msk               (0x7UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000038 */\n#define RCC_CFGR_SWS                   RCC_CFGR_SWS_Msk                        /*!< SWS[2:0] bits (System Clock Switch Status) */\n#define RCC_CFGR_SWS_0                 (0x1UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000008 */\n#define RCC_CFGR_SWS_1                 (0x2UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000010 */\n#define RCC_CFGR_SWS_2                 (0x4UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000020 */\n\n#define RCC_CFGR_SWS_HSI               (0UL)                                   /*!< HSI used as system clock */\n#define RCC_CFGR_SWS_HSE               (0x00000008UL)                          /*!< HSE used as system clock */\n#define RCC_CFGR_SWS_LSI               (0x00000018UL)                          /*!< LSI used as system clock */\n#define RCC_CFGR_SWS_LSE               (0x00000020UL)                          /*!< LSE used as system clock */\n\n/*!< HPRE configuration */\n#define RCC_CFGR_HPRE_Pos              (8U)\n#define RCC_CFGR_HPRE_Msk              (0xFUL << RCC_CFGR_HPRE_Pos)            /*!< 0x00000F00 */\n#define RCC_CFGR_HPRE                  RCC_CFGR_HPRE_Msk                       /*!< HPRE[3:0] bits (AHB prescaler) */\n#define RCC_CFGR_HPRE_0                (0x1UL << RCC_CFGR_HPRE_Pos)            /*!< 0x00000100 */\n#define RCC_CFGR_HPRE_1                (0x2UL << RCC_CFGR_HPRE_Pos)            /*!< 0x00000200 */\n#define RCC_CFGR_HPRE_2                (0x4UL << RCC_CFGR_HPRE_Pos)            /*!< 0x00000400 */\n#define RCC_CFGR_HPRE_3                (0x8UL << RCC_CFGR_HPRE_Pos)            /*!< 0x00000800 */\n\n/*!< PPRE configuration */\n#define RCC_CFGR_PPRE_Pos              (12U)\n#define RCC_CFGR_PPRE_Msk              (0x7UL << RCC_CFGR_PPRE_Pos)            /*!< 0x00007000 */\n#define RCC_CFGR_PPRE                  RCC_CFGR_PPRE_Msk                       /*!< PRE1[2:0] bits (APB prescaler) */\n#define RCC_CFGR_PPRE_0                (0x1UL << RCC_CFGR_PPRE_Pos)            /*!< 0x00001000 */\n#define RCC_CFGR_PPRE_1                (0x2UL << RCC_CFGR_PPRE_Pos)            /*!< 0x00002000 */\n#define RCC_CFGR_PPRE_2                (0x4UL << RCC_CFGR_PPRE_Pos)            /*!< 0x00004000 */\n\n/*!< MCO2SEL configuration */\n#define RCC_CFGR_MCO2SEL_Pos            (16U)\n#define RCC_CFGR_MCO2SEL_Msk            (0xFUL << RCC_CFGR_MCO2SEL_Pos)         /*!< 0x000F0000 */\n#define RCC_CFGR_MCO2SEL                RCC_CFGR_MCO2SEL_Msk                    /*!< MCO2SEL [3:0] bits (Clock output selection) */\n#define RCC_CFGR_MCO2SEL_0              (0x1UL << RCC_CFGR_MCO2SEL_Pos)         /*!< 0x00010000 */\n#define RCC_CFGR_MCO2SEL_1              (0x2UL << RCC_CFGR_MCO2SEL_Pos)         /*!< 0x00020000 */\n#define RCC_CFGR_MCO2SEL_2              (0x4UL << RCC_CFGR_MCO2SEL_Pos)         /*!< 0x00040000 */\n#define RCC_CFGR_MCO2SEL_3              (0x8UL << RCC_CFGR_MCO2SEL_Pos)         /*!< 0x00080000 */\n\n/*!< MCO2 Prescaler configuration */\n#define RCC_CFGR_MCO2PRE_Pos            (20U)\n#define RCC_CFGR_MCO2PRE_Msk            (0xFUL << RCC_CFGR_MCO2PRE_Pos)         /*!< 0x00F00000 */\n#define RCC_CFGR_MCO2PRE                RCC_CFGR_MCO2PRE_Msk                    /*!< MCO prescaler [3:0] */\n#define RCC_CFGR_MCO2PRE_0              (0x1UL << RCC_CFGR_MCO2PRE_Pos)         /*!< 0x00100000 */\n#define RCC_CFGR_MCO2PRE_1              (0x2UL << RCC_CFGR_MCO2PRE_Pos)         /*!< 0x00200000 */\n#define RCC_CFGR_MCO2PRE_2              (0x4UL << RCC_CFGR_MCO2PRE_Pos)         /*!< 0x00400000 */\n#define RCC_CFGR_MCO2PRE_3              (0x8UL << RCC_CFGR_MCO2PRE_Pos)         /*!< 0x00800000 */\n\n/*!< MCOSEL configuration */\n#define RCC_CFGR_MCOSEL_Pos            (24U)\n#define RCC_CFGR_MCOSEL_Msk            (0xFUL << RCC_CFGR_MCOSEL_Pos)          /*!< 0x0F000000 */\n#define RCC_CFGR_MCOSEL                RCC_CFGR_MCOSEL_Msk                     /*!< MCOSEL [3:0] bits (Clock output selection) */\n#define RCC_CFGR_MCOSEL_0              (0x1UL << RCC_CFGR_MCOSEL_Pos)          /*!< 0x01000000 */\n#define RCC_CFGR_MCOSEL_1              (0x2UL << RCC_CFGR_MCOSEL_Pos)          /*!< 0x02000000 */\n#define RCC_CFGR_MCOSEL_2              (0x4UL << RCC_CFGR_MCOSEL_Pos)          /*!< 0x04000000 */\n#define RCC_CFGR_MCOSEL_3              (0x8UL << RCC_CFGR_MCOSEL_Pos)          /*!< 0x08000000 */\n\n/*!< MCO Prescaler configuration */\n#define RCC_CFGR_MCOPRE_Pos            (28U)\n#define RCC_CFGR_MCOPRE_Msk            (0xFUL << RCC_CFGR_MCOPRE_Pos)          /*!< 0xF0000000 */\n#define RCC_CFGR_MCOPRE                RCC_CFGR_MCOPRE_Msk                     /*!< MCO prescaler [3:0] */\n#define RCC_CFGR_MCOPRE_0              (0x1UL << RCC_CFGR_MCOPRE_Pos)          /*!< 0x10000000 */\n#define RCC_CFGR_MCOPRE_1              (0x2UL << RCC_CFGR_MCOPRE_Pos)          /*!< 0x20000000 */\n#define RCC_CFGR_MCOPRE_2              (0x4UL << RCC_CFGR_MCOPRE_Pos)          /*!< 0x40000000 */\n#define RCC_CFGR_MCOPRE_3              (0x8UL << RCC_CFGR_MCOPRE_Pos)          /*!< 0x80000000 */\n\n/********************  Bit definition for RCC_CIER register  ******************/\n#define RCC_CIER_LSIRDYIE_Pos            (0U)\n#define RCC_CIER_LSIRDYIE_Msk            (0x1UL << RCC_CIER_LSIRDYIE_Pos)      /*!< 0x00000001 */\n#define RCC_CIER_LSIRDYIE                RCC_CIER_LSIRDYIE_Msk\n#define RCC_CIER_LSERDYIE_Pos            (1U)\n#define RCC_CIER_LSERDYIE_Msk            (0x1UL << RCC_CIER_LSERDYIE_Pos)      /*!< 0x00000002 */\n#define RCC_CIER_LSERDYIE                RCC_CIER_LSERDYIE_Msk\n#define RCC_CIER_HSIRDYIE_Pos            (3U)\n#define RCC_CIER_HSIRDYIE_Msk            (0x1UL << RCC_CIER_HSIRDYIE_Pos)      /*!< 0x00000008 */\n#define RCC_CIER_HSIRDYIE                RCC_CIER_HSIRDYIE_Msk\n#define RCC_CIER_HSERDYIE_Pos            (4U)\n#define RCC_CIER_HSERDYIE_Msk            (0x1UL << RCC_CIER_HSERDYIE_Pos)      /*!< 0x00000010 */\n#define RCC_CIER_HSERDYIE                RCC_CIER_HSERDYIE_Msk\n\n/********************  Bit definition for RCC_CIFR register  ******************/\n#define RCC_CIFR_LSIRDYF_Pos             (0U)\n#define RCC_CIFR_LSIRDYF_Msk             (0x1UL << RCC_CIFR_LSIRDYF_Pos)       /*!< 0x00000001 */\n#define RCC_CIFR_LSIRDYF                 RCC_CIFR_LSIRDYF_Msk\n#define RCC_CIFR_LSERDYF_Pos             (1U)\n#define RCC_CIFR_LSERDYF_Msk             (0x1UL << RCC_CIFR_LSERDYF_Pos)       /*!< 0x00000002 */\n#define RCC_CIFR_LSERDYF                 RCC_CIFR_LSERDYF_Msk\n#define RCC_CIFR_HSIRDYF_Pos             (3U)\n#define RCC_CIFR_HSIRDYF_Msk             (0x1UL << RCC_CIFR_HSIRDYF_Pos)       /*!< 0x00000008 */\n#define RCC_CIFR_HSIRDYF                 RCC_CIFR_HSIRDYF_Msk\n#define RCC_CIFR_HSERDYF_Pos             (4U)\n#define RCC_CIFR_HSERDYF_Msk             (0x1UL << RCC_CIFR_HSERDYF_Pos)       /*!< 0x00000010 */\n#define RCC_CIFR_HSERDYF                 RCC_CIFR_HSERDYF_Msk\n#define RCC_CIFR_CSSF_Pos                (8U)\n#define RCC_CIFR_CSSF_Msk                (0x1UL << RCC_CIFR_CSSF_Pos)          /*!< 0x00000100 */\n#define RCC_CIFR_CSSF                    RCC_CIFR_CSSF_Msk\n#define RCC_CIFR_LSECSSF_Pos             (9U)\n#define RCC_CIFR_LSECSSF_Msk             (0x1UL << RCC_CIFR_LSECSSF_Pos)       /*!< 0x00000200 */\n#define RCC_CIFR_LSECSSF                 RCC_CIFR_LSECSSF_Msk\n\n/********************  Bit definition for RCC_CICR register  ******************/\n#define RCC_CICR_LSIRDYC_Pos             (0U)\n#define RCC_CICR_LSIRDYC_Msk             (0x1UL << RCC_CICR_LSIRDYC_Pos)       /*!< 0x00000001 */\n#define RCC_CICR_LSIRDYC                 RCC_CICR_LSIRDYC_Msk\n#define RCC_CICR_LSERDYC_Pos             (1U)\n#define RCC_CICR_LSERDYC_Msk             (0x1UL << RCC_CICR_LSERDYC_Pos)       /*!< 0x00000002 */\n#define RCC_CICR_LSERDYC                 RCC_CICR_LSERDYC_Msk\n#define RCC_CICR_HSIRDYC_Pos             (3U)\n#define RCC_CICR_HSIRDYC_Msk             (0x1UL << RCC_CICR_HSIRDYC_Pos)       /*!< 0x00000008 */\n#define RCC_CICR_HSIRDYC                 RCC_CICR_HSIRDYC_Msk\n#define RCC_CICR_HSERDYC_Pos             (4U)\n#define RCC_CICR_HSERDYC_Msk             (0x1UL << RCC_CICR_HSERDYC_Pos)       /*!< 0x00000010 */\n#define RCC_CICR_HSERDYC                 RCC_CICR_HSERDYC_Msk\n#define RCC_CICR_CSSC_Pos                (8U)\n#define RCC_CICR_CSSC_Msk                (0x1UL << RCC_CICR_CSSC_Pos)          /*!< 0x00000100 */\n#define RCC_CICR_CSSC                    RCC_CICR_CSSC_Msk\n#define RCC_CICR_LSECSSC_Pos             (9U)\n#define RCC_CICR_LSECSSC_Msk             (0x1UL << RCC_CICR_LSECSSC_Pos)       /*!< 0x00000200 */\n#define RCC_CICR_LSECSSC                 RCC_CICR_LSECSSC_Msk\n\n/********************  Bit definition for RCC_IOPRSTR register  ****************/\n#define RCC_IOPRSTR_GPIOARST_Pos         (0U)\n#define RCC_IOPRSTR_GPIOARST_Msk         (0x1UL << RCC_IOPRSTR_GPIOARST_Pos)   /*!< 0x00000001 */\n#define RCC_IOPRSTR_GPIOARST             RCC_IOPRSTR_GPIOARST_Msk\n#define RCC_IOPRSTR_GPIOBRST_Pos         (1U)\n#define RCC_IOPRSTR_GPIOBRST_Msk         (0x1UL << RCC_IOPRSTR_GPIOBRST_Pos)   /*!< 0x00000002 */\n#define RCC_IOPRSTR_GPIOBRST             RCC_IOPRSTR_GPIOBRST_Msk\n#define RCC_IOPRSTR_GPIOCRST_Pos         (2U)\n#define RCC_IOPRSTR_GPIOCRST_Msk         (0x1UL << RCC_IOPRSTR_GPIOCRST_Pos)   /*!< 0x00000004 */\n#define RCC_IOPRSTR_GPIOCRST             RCC_IOPRSTR_GPIOCRST_Msk\n#define RCC_IOPRSTR_GPIODRST_Pos         (3U)\n#define RCC_IOPRSTR_GPIODRST_Msk         (0x1UL << RCC_IOPRSTR_GPIODRST_Pos)   /*!< 0x00000008 */\n#define RCC_IOPRSTR_GPIODRST             RCC_IOPRSTR_GPIODRST_Msk\n#define RCC_IOPRSTR_GPIOFRST_Pos         (5U)\n#define RCC_IOPRSTR_GPIOFRST_Msk         (0x1UL << RCC_IOPRSTR_GPIOFRST_Pos)   /*!< 0x00000020 */\n#define RCC_IOPRSTR_GPIOFRST             RCC_IOPRSTR_GPIOFRST_Msk\n\n/********************  Bit definition for RCC_AHBRSTR register  ***************/\n#define RCC_AHBRSTR_DMA1RST_Pos          (0U)\n#define RCC_AHBRSTR_DMA1RST_Msk          (0x1UL << RCC_AHBRSTR_DMA1RST_Pos)    /*!< 0x00000001 */\n#define RCC_AHBRSTR_DMA1RST              RCC_AHBRSTR_DMA1RST_Msk\n#define RCC_AHBRSTR_FLASHRST_Pos         (8U)\n#define RCC_AHBRSTR_FLASHRST_Msk         (0x1UL << RCC_AHBRSTR_FLASHRST_Pos)   /*!< 0x00000100 */\n#define RCC_AHBRSTR_FLASHRST             RCC_AHBRSTR_FLASHRST_Msk\n#define RCC_AHBRSTR_CRCRST_Pos           (12U)\n#define RCC_AHBRSTR_CRCRST_Msk           (0x1UL << RCC_AHBRSTR_CRCRST_Pos)     /*!< 0x00001000 */\n#define RCC_AHBRSTR_CRCRST               RCC_AHBRSTR_CRCRST_Msk\n\n/********************  Bit definition for RCC_APBRSTR1 register  **************/\n#define RCC_APBRSTR1_TIM3RST_Pos         (1U)\n#define RCC_APBRSTR1_TIM3RST_Msk         (0x1UL << RCC_APBRSTR1_TIM3RST_Pos)   /*!< 0x00000002 */\n#define RCC_APBRSTR1_TIM3RST             RCC_APBRSTR1_TIM3RST_Msk\n#define RCC_APBRSTR1_USART2RST_Pos       (17U)\n#define RCC_APBRSTR1_USART2RST_Msk       (0x1UL << RCC_APBRSTR1_USART2RST_Pos) /*!< 0x00020000 */\n#define RCC_APBRSTR1_USART2RST           RCC_APBRSTR1_USART2RST_Msk\n#define RCC_APBRSTR1_I2C1RST_Pos         (21U)\n#define RCC_APBRSTR1_I2C1RST_Msk         (0x1UL << RCC_APBRSTR1_I2C1RST_Pos)    /*!< 0x00200000 */\n#define RCC_APBRSTR1_I2C1RST             RCC_APBRSTR1_I2C1RST_Msk\n#define RCC_APBRSTR1_DBGRST_Pos          (27U)\n#define RCC_APBRSTR1_DBGRST_Msk          (0x1UL << RCC_APBRSTR1_DBGRST_Pos)     /*!< 0x08000000 */\n#define RCC_APBRSTR1_DBGRST              RCC_APBRSTR1_DBGRST_Msk\n#define RCC_APBRSTR1_PWRRST_Pos          (28U)\n#define RCC_APBRSTR1_PWRRST_Msk          (0x1UL << RCC_APBRSTR1_PWRRST_Pos)     /*!< 0x10000000 */\n#define RCC_APBRSTR1_PWRRST              RCC_APBRSTR1_PWRRST_Msk\n\n/********************  Bit definition for RCC_APBRSTR2 register  **************/\n#define RCC_APBRSTR2_SYSCFGRST_Pos       (0U)\n#define RCC_APBRSTR2_SYSCFGRST_Msk       (0x1UL << RCC_APBRSTR2_SYSCFGRST_Pos)  /*!< 0x00000001 */\n#define RCC_APBRSTR2_SYSCFGRST           RCC_APBRSTR2_SYSCFGRST_Msk\n#define RCC_APBRSTR2_TIM1RST_Pos         (11U)\n#define RCC_APBRSTR2_TIM1RST_Msk         (0x1UL << RCC_APBRSTR2_TIM1RST_Pos)    /*!< 0x00000800 */\n#define RCC_APBRSTR2_TIM1RST             RCC_APBRSTR2_TIM1RST_Msk\n#define RCC_APBRSTR2_SPI1RST_Pos         (12U)\n#define RCC_APBRSTR2_SPI1RST_Msk         (0x1UL << RCC_APBRSTR2_SPI1RST_Pos)    /*!< 0x00001000 */\n#define RCC_APBRSTR2_SPI1RST             RCC_APBRSTR2_SPI1RST_Msk\n#define RCC_APBRSTR2_USART1RST_Pos       (14U)\n#define RCC_APBRSTR2_USART1RST_Msk       (0x1UL << RCC_APBRSTR2_USART1RST_Pos)  /*!< 0x00004000 */\n#define RCC_APBRSTR2_USART1RST           RCC_APBRSTR2_USART1RST_Msk\n#define RCC_APBRSTR2_TIM14RST_Pos        (15U)\n#define RCC_APBRSTR2_TIM14RST_Msk        (0x1UL << RCC_APBRSTR2_TIM14RST_Pos)   /*!< 0x00008000 */\n#define RCC_APBRSTR2_TIM14RST            RCC_APBRSTR2_TIM14RST_Msk\n#define RCC_APBRSTR2_TIM16RST_Pos        (17U)\n#define RCC_APBRSTR2_TIM16RST_Msk        (0x1UL << RCC_APBRSTR2_TIM16RST_Pos)   /*!< 0x00020000 */\n#define RCC_APBRSTR2_TIM16RST            RCC_APBRSTR2_TIM16RST_Msk\n#define RCC_APBRSTR2_TIM17RST_Pos        (18U)\n#define RCC_APBRSTR2_TIM17RST_Msk        (0x1UL << RCC_APBRSTR2_TIM17RST_Pos)   /*!< 0x00040000 */\n#define RCC_APBRSTR2_TIM17RST            RCC_APBRSTR2_TIM17RST_Msk\n#define RCC_APBRSTR2_ADCRST_Pos          (20U)\n#define RCC_APBRSTR2_ADCRST_Msk          (0x1UL << RCC_APBRSTR2_ADCRST_Pos)     /*!< 0x00100000 */\n#define RCC_APBRSTR2_ADCRST              RCC_APBRSTR2_ADCRST_Msk\n\n/********************  Bit definition for RCC_IOPENR register  ****************/\n#define RCC_IOPENR_GPIOAEN_Pos           (0U)\n#define RCC_IOPENR_GPIOAEN_Msk           (0x1UL << RCC_IOPENR_GPIOAEN_Pos)      /*!< 0x00000001 */\n#define RCC_IOPENR_GPIOAEN               RCC_IOPENR_GPIOAEN_Msk\n#define RCC_IOPENR_GPIOBEN_Pos           (1U)\n#define RCC_IOPENR_GPIOBEN_Msk           (0x1UL << RCC_IOPENR_GPIOBEN_Pos)      /*!< 0x00000002 */\n#define RCC_IOPENR_GPIOBEN               RCC_IOPENR_GPIOBEN_Msk\n#define RCC_IOPENR_GPIOCEN_Pos           (2U)\n#define RCC_IOPENR_GPIOCEN_Msk           (0x1UL << RCC_IOPENR_GPIOCEN_Pos)      /*!< 0x00000004 */\n#define RCC_IOPENR_GPIOCEN               RCC_IOPENR_GPIOCEN_Msk\n#define RCC_IOPENR_GPIODEN_Pos           (3U)\n#define RCC_IOPENR_GPIODEN_Msk           (0x1UL << RCC_IOPENR_GPIODEN_Pos)      /*!< 0x00000008 */\n#define RCC_IOPENR_GPIODEN               RCC_IOPENR_GPIODEN_Msk\n#define RCC_IOPENR_GPIOFEN_Pos           (5U)\n#define RCC_IOPENR_GPIOFEN_Msk           (0x1UL << RCC_IOPENR_GPIOFEN_Pos)      /*!< 0x00000020 */\n#define RCC_IOPENR_GPIOFEN               RCC_IOPENR_GPIOFEN_Msk\n\n/********************  Bit definition for RCC_AHBENR register  ****************/\n#define RCC_AHBENR_DMA1EN_Pos            (0U)\n#define RCC_AHBENR_DMA1EN_Msk            (0x1UL << RCC_AHBENR_DMA1EN_Pos)       /*!< 0x00000001 */\n#define RCC_AHBENR_DMA1EN                RCC_AHBENR_DMA1EN_Msk\n#define RCC_AHBENR_FLASHEN_Pos           (8U)\n#define RCC_AHBENR_FLASHEN_Msk           (0x1UL << RCC_AHBENR_FLASHEN_Pos)      /*!< 0x00000100 */\n#define RCC_AHBENR_FLASHEN               RCC_AHBENR_FLASHEN_Msk\n#define RCC_AHBENR_CRCEN_Pos             (12U)\n#define RCC_AHBENR_CRCEN_Msk             (0x1UL << RCC_AHBENR_CRCEN_Pos)        /*!< 0x00001000 */\n#define RCC_AHBENR_CRCEN                 RCC_AHBENR_CRCEN_Msk\n\n/********************  Bit definition for RCC_APBENR1 register  ***************/\n#define RCC_APBENR1_TIM3EN_Pos           (1U)\n#define RCC_APBENR1_TIM3EN_Msk           (0x1UL << RCC_APBENR1_TIM3EN_Pos)      /*!< 0x00000002 */\n#define RCC_APBENR1_TIM3EN               RCC_APBENR1_TIM3EN_Msk\n#define RCC_APBENR1_RTCAPBEN_Pos         (10U)\n#define RCC_APBENR1_RTCAPBEN_Msk         (0x1UL << RCC_APBENR1_RTCAPBEN_Pos)    /*!< 0x00000400 */\n#define RCC_APBENR1_RTCAPBEN             RCC_APBENR1_RTCAPBEN_Msk\n#define RCC_APBENR1_WWDGEN_Pos           (11U)\n#define RCC_APBENR1_WWDGEN_Msk           (0x1UL << RCC_APBENR1_WWDGEN_Pos)      /*!< 0x00000800 */\n#define RCC_APBENR1_WWDGEN               RCC_APBENR1_WWDGEN_Msk\n#define RCC_APBENR1_USART2EN_Pos         (17U)\n#define RCC_APBENR1_USART2EN_Msk         (0x1UL << RCC_APBENR1_USART2EN_Pos)    /*!< 0x00020000 */\n#define RCC_APBENR1_USART2EN             RCC_APBENR1_USART2EN_Msk\n#define RCC_APBENR1_I2C1EN_Pos           (21U)\n#define RCC_APBENR1_I2C1EN_Msk           (0x1UL << RCC_APBENR1_I2C1EN_Pos)      /*!< 0x00200000 */\n#define RCC_APBENR1_I2C1EN               RCC_APBENR1_I2C1EN_Msk\n#define RCC_APBENR1_DBGEN_Pos            (27U)\n#define RCC_APBENR1_DBGEN_Msk            (0x1UL << RCC_APBENR1_DBGEN_Pos)       /*!< 0x08000000 */\n#define RCC_APBENR1_DBGEN                RCC_APBENR1_DBGEN_Msk\n#define RCC_APBENR1_PWREN_Pos            (28U)\n#define RCC_APBENR1_PWREN_Msk            (0x1UL << RCC_APBENR1_PWREN_Pos)       /*!< 0x10000000 */\n#define RCC_APBENR1_PWREN                RCC_APBENR1_PWREN_Msk\n\n/********************  Bit definition for RCC_APBENR2 register  **************/\n#define RCC_APBENR2_SYSCFGEN_Pos         (0U)\n#define RCC_APBENR2_SYSCFGEN_Msk         (0x1UL << RCC_APBENR2_SYSCFGEN_Pos)    /*!< 0x00000001 */\n#define RCC_APBENR2_SYSCFGEN             RCC_APBENR2_SYSCFGEN_Msk\n#define RCC_APBENR2_TIM1EN_Pos           (11U)\n#define RCC_APBENR2_TIM1EN_Msk           (0x1UL << RCC_APBENR2_TIM1EN_Pos)      /*!< 0x00000800 */\n#define RCC_APBENR2_TIM1EN               RCC_APBENR2_TIM1EN_Msk\n#define RCC_APBENR2_SPI1EN_Pos           (12U)\n#define RCC_APBENR2_SPI1EN_Msk           (0x1UL << RCC_APBENR2_SPI1EN_Pos)      /*!< 0x00001000 */\n#define RCC_APBENR2_SPI1EN               RCC_APBENR2_SPI1EN_Msk\n#define RCC_APBENR2_USART1EN_Pos         (14U)\n#define RCC_APBENR2_USART1EN_Msk         (0x1UL << RCC_APBENR2_USART1EN_Pos)    /*!< 0x00004000 */\n#define RCC_APBENR2_USART1EN             RCC_APBENR2_USART1EN_Msk\n#define RCC_APBENR2_TIM14EN_Pos          (15U)\n#define RCC_APBENR2_TIM14EN_Msk          (0x1UL << RCC_APBENR2_TIM14EN_Pos)     /*!< 0x00008000 */\n#define RCC_APBENR2_TIM14EN              RCC_APBENR2_TIM14EN_Msk\n#define RCC_APBENR2_TIM16EN_Pos          (17U)\n#define RCC_APBENR2_TIM16EN_Msk          (0x1UL << RCC_APBENR2_TIM16EN_Pos)     /*!< 0x00020000 */\n#define RCC_APBENR2_TIM16EN              RCC_APBENR2_TIM16EN_Msk\n#define RCC_APBENR2_TIM17EN_Pos          (18U)\n#define RCC_APBENR2_TIM17EN_Msk          (0x1UL << RCC_APBENR2_TIM17EN_Pos)     /*!< 0x00040000 */\n#define RCC_APBENR2_TIM17EN              RCC_APBENR2_TIM17EN_Msk\n#define RCC_APBENR2_ADCEN_Pos            (20U)\n#define RCC_APBENR2_ADCEN_Msk            (0x1UL << RCC_APBENR2_ADCEN_Pos)       /*!< 0x00100000 */\n#define RCC_APBENR2_ADCEN                RCC_APBENR2_ADCEN_Msk\n\n/********************  Bit definition for RCC_IOPSMENR register  *************/\n#define RCC_IOPSMENR_GPIOASMEN_Pos       (0U)\n#define RCC_IOPSMENR_GPIOASMEN_Msk       (0x1UL << RCC_IOPSMENR_GPIOASMEN_Pos)  /*!< 0x00000001 */\n#define RCC_IOPSMENR_GPIOASMEN           RCC_IOPSMENR_GPIOASMEN_Msk\n#define RCC_IOPSMENR_GPIOBSMEN_Pos       (1U)\n#define RCC_IOPSMENR_GPIOBSMEN_Msk       (0x1UL << RCC_IOPSMENR_GPIOBSMEN_Pos)  /*!< 0x00000002 */\n#define RCC_IOPSMENR_GPIOBSMEN           RCC_IOPSMENR_GPIOBSMEN_Msk\n#define RCC_IOPSMENR_GPIOCSMEN_Pos       (2U)\n#define RCC_IOPSMENR_GPIOCSMEN_Msk       (0x1UL << RCC_IOPSMENR_GPIOCSMEN_Pos)  /*!< 0x00000004 */\n#define RCC_IOPSMENR_GPIOCSMEN           RCC_IOPSMENR_GPIOCSMEN_Msk\n#define RCC_IOPSMENR_GPIODSMEN_Pos       (3U)\n#define RCC_IOPSMENR_GPIODSMEN_Msk       (0x1UL << RCC_IOPSMENR_GPIODSMEN_Pos)  /*!< 0x00000008 */\n#define RCC_IOPSMENR_GPIODSMEN           RCC_IOPSMENR_GPIODSMEN_Msk\n#define RCC_IOPSMENR_GPIOFSMEN_Pos       (5U)\n#define RCC_IOPSMENR_GPIOFSMEN_Msk       (0x1UL << RCC_IOPSMENR_GPIOFSMEN_Pos)  /*!< 0x00000020 */\n#define RCC_IOPSMENR_GPIOFSMEN           RCC_IOPSMENR_GPIOFSMEN_Msk\n\n/********************  Bit definition for RCC_AHBSMENR register  *************/\n#define RCC_AHBSMENR_DMA1SMEN_Pos        (0U)\n#define RCC_AHBSMENR_DMA1SMEN_Msk        (0x1UL << RCC_AHBSMENR_DMA1SMEN_Pos)   /*!< 0x00000001 */\n#define RCC_AHBSMENR_DMA1SMEN            RCC_AHBSMENR_DMA1SMEN_Msk\n#define RCC_AHBSMENR_FLASHSMEN_Pos       (8U)\n#define RCC_AHBSMENR_FLASHSMEN_Msk       (0x1UL << RCC_AHBSMENR_FLASHSMEN_Pos)  /*!< 0x00000100 */\n#define RCC_AHBSMENR_FLASHSMEN           RCC_AHBSMENR_FLASHSMEN_Msk\n#define RCC_AHBSMENR_SRAMSMEN_Pos        (9U)\n#define RCC_AHBSMENR_SRAMSMEN_Msk        (0x1UL << RCC_AHBSMENR_SRAMSMEN_Pos)   /*!< 0x00000200 */\n#define RCC_AHBSMENR_SRAMSMEN            RCC_AHBSMENR_SRAMSMEN_Msk\n#define RCC_AHBSMENR_CRCSMEN_Pos         (12U)\n#define RCC_AHBSMENR_CRCSMEN_Msk         (0x1UL << RCC_AHBSMENR_CRCSMEN_Pos)    /*!< 0x00001000 */\n#define RCC_AHBSMENR_CRCSMEN             RCC_AHBSMENR_CRCSMEN_Msk\n\n/********************  Bit definition for RCC_APBSMENR1 register  *************/\n#define RCC_APBSMENR1_TIM3SMEN_Pos       (1U)\n#define RCC_APBSMENR1_TIM3SMEN_Msk       (0x1UL << RCC_APBSMENR1_TIM3SMEN_Pos)  /*!< 0x00000002 */\n#define RCC_APBSMENR1_TIM3SMEN           RCC_APBSMENR1_TIM3SMEN_Msk\n#define RCC_APBSMENR1_RTCAPBSMEN_Pos     (10U)\n#define RCC_APBSMENR1_RTCAPBSMEN_Msk     (0x1UL << RCC_APBSMENR1_RTCAPBSMEN_Pos) /*!< 0x00000400 */\n#define RCC_APBSMENR1_RTCAPBSMEN         RCC_APBSMENR1_RTCAPBSMEN_Msk\n#define RCC_APBSMENR1_WWDGSMEN_Pos       (11U)\n#define RCC_APBSMENR1_WWDGSMEN_Msk       (0x1UL << RCC_APBSMENR1_WWDGSMEN_Pos)  /*!< 0x00000800 */\n#define RCC_APBSMENR1_WWDGSMEN           RCC_APBSMENR1_WWDGSMEN_Msk\n#define RCC_APBSMENR1_USART2SMEN_Pos     (17U)\n#define RCC_APBSMENR1_USART2SMEN_Msk     (0x1UL << RCC_APBSMENR1_USART2SMEN_Pos) /*!< 0x00020000 */\n#define RCC_APBSMENR1_USART2SMEN         RCC_APBSMENR1_USART2SMEN_Msk\n#define RCC_APBSMENR1_I2C1SMEN_Pos       (21U)\n#define RCC_APBSMENR1_I2C1SMEN_Msk       (0x1UL << RCC_APBSMENR1_I2C1SMEN_Pos)   /*!< 0x00200000 */\n#define RCC_APBSMENR1_I2C1SMEN           RCC_APBSMENR1_I2C1SMEN_Msk\n#define RCC_APBSMENR1_DBGSMEN_Pos        (27U)\n#define RCC_APBSMENR1_DBGSMEN_Msk        (0x1UL << RCC_APBSMENR1_DBGSMEN_Pos)    /*!< 0x08000000 */\n#define RCC_APBSMENR1_DBGSMEN            RCC_APBSMENR1_DBGSMEN_Msk\n#define RCC_APBSMENR1_PWRSMEN_Pos        (28U)\n#define RCC_APBSMENR1_PWRSMEN_Msk        (0x1UL << RCC_APBSMENR1_PWRSMEN_Pos)    /*!< 0x10000000 */\n#define RCC_APBSMENR1_PWRSMEN            RCC_APBSMENR1_PWRSMEN_Msk\n\n/********************  Bit definition for RCC_APBSMENR2 register  *************/\n#define RCC_APBSMENR2_SYSCFGSMEN_Pos     (0U)\n#define RCC_APBSMENR2_SYSCFGSMEN_Msk     (0x1UL << RCC_APBSMENR2_SYSCFGSMEN_Pos) /*!< 0x00000001 */\n#define RCC_APBSMENR2_SYSCFGSMEN         RCC_APBSMENR2_SYSCFGSMEN_Msk\n#define RCC_APBSMENR2_TIM1SMEN_Pos       (11U)\n#define RCC_APBSMENR2_TIM1SMEN_Msk       (0x1UL << RCC_APBSMENR2_TIM1SMEN_Pos)  /*!< 0x00000800 */\n#define RCC_APBSMENR2_TIM1SMEN           RCC_APBSMENR2_TIM1SMEN_Msk\n#define RCC_APBSMENR2_SPI1SMEN_Pos       (12U)\n#define RCC_APBSMENR2_SPI1SMEN_Msk       (0x1UL << RCC_APBSMENR2_SPI1SMEN_Pos)  /*!< 0x00001000 */\n#define RCC_APBSMENR2_SPI1SMEN           RCC_APBSMENR2_SPI1SMEN_Msk\n#define RCC_APBSMENR2_USART1SMEN_Pos     (14U)\n#define RCC_APBSMENR2_USART1SMEN_Msk     (0x1UL << RCC_APBSMENR2_USART1SMEN_Pos) /*!< 0x00004000 */\n#define RCC_APBSMENR2_USART1SMEN         RCC_APBSMENR2_USART1SMEN_Msk\n#define RCC_APBSMENR2_TIM14SMEN_Pos      (15U)\n#define RCC_APBSMENR2_TIM14SMEN_Msk      (0x1UL << RCC_APBSMENR2_TIM14SMEN_Pos) /*!< 0x00008000 */\n#define RCC_APBSMENR2_TIM14SMEN          RCC_APBSMENR2_TIM14SMEN_Msk\n#define RCC_APBSMENR2_TIM16SMEN_Pos      (17U)\n#define RCC_APBSMENR2_TIM16SMEN_Msk      (0x1UL << RCC_APBSMENR2_TIM16SMEN_Pos) /*!< 0x00020000 */\n#define RCC_APBSMENR2_TIM16SMEN          RCC_APBSMENR2_TIM16SMEN_Msk\n#define RCC_APBSMENR2_TIM17SMEN_Pos      (18U)\n#define RCC_APBSMENR2_TIM17SMEN_Msk      (0x1UL << RCC_APBSMENR2_TIM17SMEN_Pos) /*!< 0x00040000 */\n#define RCC_APBSMENR2_TIM17SMEN          RCC_APBSMENR2_TIM17SMEN_Msk\n#define RCC_APBSMENR2_ADCSMEN_Pos        (20U)\n#define RCC_APBSMENR2_ADCSMEN_Msk        (0x1UL << RCC_APBSMENR2_ADCSMEN_Pos)   /*!< 0x00100000 */\n#define RCC_APBSMENR2_ADCSMEN            RCC_APBSMENR2_ADCSMEN_Msk\n\n/********************  Bit definition for RCC_CCIPR register  ******************/\n#define RCC_CCIPR_USART1SEL_Pos          (0U)\n#define RCC_CCIPR_USART1SEL_Msk          (0x3UL << RCC_CCIPR_USART1SEL_Pos)     /*!< 0x00000003 */\n#define RCC_CCIPR_USART1SEL              RCC_CCIPR_USART1SEL_Msk\n#define RCC_CCIPR_USART1SEL_0            (0x1UL << RCC_CCIPR_USART1SEL_Pos)     /*!< 0x00000001 */\n#define RCC_CCIPR_USART1SEL_1            (0x2UL << RCC_CCIPR_USART1SEL_Pos)     /*!< 0x00000002 */\n#define RCC_CCIPR_I2C1SEL_Pos            (12U)\n#define RCC_CCIPR_I2C1SEL_Msk            (0x3UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00003000 */\n#define RCC_CCIPR_I2C1SEL                RCC_CCIPR_I2C1SEL_Msk\n#define RCC_CCIPR_I2C1SEL_0              (0x1UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00001000 */\n#define RCC_CCIPR_I2C1SEL_1              (0x2UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00002000 */\n#define RCC_CCIPR_I2S1SEL_Pos            (14U)\n#define RCC_CCIPR_I2S1SEL_Msk            (0x3UL << RCC_CCIPR_I2S1SEL_Pos)       /*!< 0x0000C000 */\n#define RCC_CCIPR_I2S1SEL                RCC_CCIPR_I2S1SEL_Msk\n#define RCC_CCIPR_I2S1SEL_0              (0x1UL << RCC_CCIPR_I2S1SEL_Pos)       /*!< 0x00004000 */\n#define RCC_CCIPR_I2S1SEL_1              (0x2UL << RCC_CCIPR_I2S1SEL_Pos)       /*!< 0x00008000 */\n#define RCC_CCIPR_ADCSEL_Pos             (30U)\n#define RCC_CCIPR_ADCSEL_Msk             (0x3UL << RCC_CCIPR_ADCSEL_Pos)        /*!< 0xC0000000 */\n#define RCC_CCIPR_ADCSEL                 RCC_CCIPR_ADCSEL_Msk\n#define RCC_CCIPR_ADCSEL_0               (0x1UL << RCC_CCIPR_ADCSEL_Pos)        /*!< 0x40000000 */\n#define RCC_CCIPR_ADCSEL_1               (0x2UL << RCC_CCIPR_ADCSEL_Pos)        /*!< 0x80000000 */\n\n/********************  Bit definition for RCC_CSR1 register  ******************/\n#define RCC_CSR1_LSEON_Pos               (0U)\n#define RCC_CSR1_LSEON_Msk               (0x1UL << RCC_CSR1_LSEON_Pos)          /*!< 0x00000001 */\n#define RCC_CSR1_LSEON                   RCC_CSR1_LSEON_Msk\n#define RCC_CSR1_LSERDY_Pos              (1U)\n#define RCC_CSR1_LSERDY_Msk              (0x1UL << RCC_CSR1_LSERDY_Pos)         /*!< 0x00000002 */\n#define RCC_CSR1_LSERDY                  RCC_CSR1_LSERDY_Msk\n#define RCC_CSR1_LSEBYP_Pos              (2U)\n#define RCC_CSR1_LSEBYP_Msk              (0x1UL << RCC_CSR1_LSEBYP_Pos)         /*!< 0x00000004 */\n#define RCC_CSR1_LSEBYP                  RCC_CSR1_LSEBYP_Msk\n#define RCC_CSR1_LSEDRV_Pos              (3U)\n#define RCC_CSR1_LSEDRV_Msk              (0x3UL << RCC_CSR1_LSEDRV_Pos)         /*!< 0x00000018 */\n#define RCC_CSR1_LSEDRV                  RCC_CSR1_LSEDRV_Msk\n#define RCC_CSR1_LSEDRV_0                (0x1UL << RCC_CSR1_LSEDRV_Pos)         /*!< 0x00000008 */\n#define RCC_CSR1_LSEDRV_1                (0x2UL << RCC_CSR1_LSEDRV_Pos)         /*!< 0x00000010 */\n#define RCC_CSR1_LSECSSON_Pos            (5U)\n#define RCC_CSR1_LSECSSON_Msk            (0x1UL << RCC_CSR1_LSECSSON_Pos)       /*!< 0x00000020 */\n#define RCC_CSR1_LSECSSON                RCC_CSR1_LSECSSON_Msk\n#define RCC_CSR1_LSECSSD_Pos             (6U)\n#define RCC_CSR1_LSECSSD_Msk             (0x1UL << RCC_CSR1_LSECSSD_Pos)        /*!< 0x00000040 */\n#define RCC_CSR1_LSECSSD                 RCC_CSR1_LSECSSD_Msk\n#define RCC_CSR1_RTCSEL_Pos              (8U)\n#define RCC_CSR1_RTCSEL_Msk              (0x3UL << RCC_CSR1_RTCSEL_Pos)         /*!< 0x00000300 */\n#define RCC_CSR1_RTCSEL                  RCC_CSR1_RTCSEL_Msk\n#define RCC_CSR1_RTCSEL_0                (0x1UL << RCC_CSR1_RTCSEL_Pos)         /*!< 0x00000100 */\n#define RCC_CSR1_RTCSEL_1                (0x2UL << RCC_CSR1_RTCSEL_Pos)         /*!< 0x00000200 */\n#define RCC_CSR1_RTCEN_Pos               (15U)\n#define RCC_CSR1_RTCEN_Msk               (0x1UL << RCC_CSR1_RTCEN_Pos)          /*!< 0x00008000 */\n#define RCC_CSR1_RTCEN                   RCC_CSR1_RTCEN_Msk\n#define RCC_CSR1_RTCRST_Pos              (16U)\n#define RCC_CSR1_RTCRST_Msk              (0x1UL << RCC_CSR1_RTCRST_Pos)          /*!< 0x00010000 */\n#define RCC_CSR1_RTCRST                  RCC_CSR1_RTCRST_Msk\n#define RCC_CSR1_LSCOEN_Pos              (24U)\n#define RCC_CSR1_LSCOEN_Msk              (0x1UL << RCC_CSR1_LSCOEN_Pos)         /*!< 0x01000000 */\n#define RCC_CSR1_LSCOEN                  RCC_CSR1_LSCOEN_Msk\n#define RCC_CSR1_LSCOSEL_Pos             (25U)\n#define RCC_CSR1_LSCOSEL_Msk             (0x1UL << RCC_CSR1_LSCOSEL_Pos)        /*!< 0x02000000 */\n#define RCC_CSR1_LSCOSEL                 RCC_CSR1_LSCOSEL_Msk\n\n/********************  Bit definition for RCC_CSR2 register  *******************/\n#define RCC_CSR2_LSION_Pos               (0U)\n#define RCC_CSR2_LSION_Msk               (0x1UL << RCC_CSR2_LSION_Pos)           /*!< 0x00000001 */\n#define RCC_CSR2_LSION                   RCC_CSR2_LSION_Msk\n#define RCC_CSR2_LSIRDY_Pos              (1U)\n#define RCC_CSR2_LSIRDY_Msk              (0x1UL << RCC_CSR2_LSIRDY_Pos)          /*!< 0x00000002 */\n#define RCC_CSR2_LSIRDY                  RCC_CSR2_LSIRDY_Msk\n#define RCC_CSR2_RMVF_Pos                (23U)\n#define RCC_CSR2_RMVF_Msk                (0x1UL << RCC_CSR2_RMVF_Pos)            /*!< 0x00800000 */\n#define RCC_CSR2_RMVF                    RCC_CSR2_RMVF_Msk\n#define RCC_CSR2_OBLRSTF_Pos             (25U)\n#define RCC_CSR2_OBLRSTF_Msk             (0x1UL << RCC_CSR2_OBLRSTF_Pos)         /*!< 0x02000000 */\n#define RCC_CSR2_OBLRSTF                 RCC_CSR2_OBLRSTF_Msk\n#define RCC_CSR2_PINRSTF_Pos             (26U)\n#define RCC_CSR2_PINRSTF_Msk             (0x1UL << RCC_CSR2_PINRSTF_Pos)         /*!< 0x04000000 */\n#define RCC_CSR2_PINRSTF                 RCC_CSR2_PINRSTF_Msk\n#define RCC_CSR2_PWRRSTF_Pos             (27U)\n#define RCC_CSR2_PWRRSTF_Msk             (0x1UL << RCC_CSR2_PWRRSTF_Pos)         /*!< 0x08000000 */\n#define RCC_CSR2_PWRRSTF                 RCC_CSR2_PWRRSTF_Msk\n#define RCC_CSR2_SFTRSTF_Pos             (28U)\n#define RCC_CSR2_SFTRSTF_Msk             (0x1UL << RCC_CSR2_SFTRSTF_Pos)         /*!< 0x10000000 */\n#define RCC_CSR2_SFTRSTF                 RCC_CSR2_SFTRSTF_Msk\n#define RCC_CSR2_IWDGRSTF_Pos            (29U)\n#define RCC_CSR2_IWDGRSTF_Msk            (0x1UL << RCC_CSR2_IWDGRSTF_Pos)        /*!< 0x20000000 */\n#define RCC_CSR2_IWDGRSTF                RCC_CSR2_IWDGRSTF_Msk\n#define RCC_CSR2_WWDGRSTF_Pos            (30U)\n#define RCC_CSR2_WWDGRSTF_Msk            (0x1UL << RCC_CSR2_WWDGRSTF_Pos)        /*!< 0x40000000 */\n#define RCC_CSR2_WWDGRSTF                RCC_CSR2_WWDGRSTF_Msk\n#define RCC_CSR2_LPWRRSTF_Pos            (31U)\n#define RCC_CSR2_LPWRRSTF_Msk            (0x1UL << RCC_CSR2_LPWRRSTF_Pos)        /*!< 0x80000000 */\n#define RCC_CSR2_LPWRRSTF                RCC_CSR2_LPWRRSTF_Msk\n\n/******************************************************************************/\n/*                                                                            */\n/*                           Real-Time Clock (RTC)                            */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bits definition for RTC_TR register  *******************/\n#define RTC_TR_PM_Pos                (22U)\n#define RTC_TR_PM_Msk                (0x1UL << RTC_TR_PM_Pos)                   /*!< 0x00400000 */\n#define RTC_TR_PM                    RTC_TR_PM_Msk\n#define RTC_TR_HT_Pos                (20U)\n#define RTC_TR_HT_Msk                (0x3UL << RTC_TR_HT_Pos)                   /*!< 0x00300000 */\n#define RTC_TR_HT                    RTC_TR_HT_Msk\n#define RTC_TR_HT_0                  (0x1UL << RTC_TR_HT_Pos)                   /*!< 0x00100000 */\n#define RTC_TR_HT_1                  (0x2UL << RTC_TR_HT_Pos)                   /*!< 0x00200000 */\n#define RTC_TR_HU_Pos                (16U)\n#define RTC_TR_HU_Msk                (0xFUL << RTC_TR_HU_Pos)                   /*!< 0x000F0000 */\n#define RTC_TR_HU                    RTC_TR_HU_Msk\n#define RTC_TR_HU_0                  (0x1UL << RTC_TR_HU_Pos)                   /*!< 0x00010000 */\n#define RTC_TR_HU_1                  (0x2UL << RTC_TR_HU_Pos)                   /*!< 0x00020000 */\n#define RTC_TR_HU_2                  (0x4UL << RTC_TR_HU_Pos)                   /*!< 0x00040000 */\n#define RTC_TR_HU_3                  (0x8UL << RTC_TR_HU_Pos)                   /*!< 0x00080000 */\n#define RTC_TR_MNT_Pos               (12U)\n#define RTC_TR_MNT_Msk               (0x7UL << RTC_TR_MNT_Pos)                  /*!< 0x00007000 */\n#define RTC_TR_MNT                   RTC_TR_MNT_Msk\n#define RTC_TR_MNT_0                 (0x1UL << RTC_TR_MNT_Pos)                  /*!< 0x00001000 */\n#define RTC_TR_MNT_1                 (0x2UL << RTC_TR_MNT_Pos)                  /*!< 0x00002000 */\n#define RTC_TR_MNT_2                 (0x4UL << RTC_TR_MNT_Pos)                  /*!< 0x00004000 */\n#define RTC_TR_MNU_Pos               (8U)\n#define RTC_TR_MNU_Msk               (0xFUL << RTC_TR_MNU_Pos)                  /*!< 0x00000F00 */\n#define RTC_TR_MNU                   RTC_TR_MNU_Msk\n#define RTC_TR_MNU_0                 (0x1UL << RTC_TR_MNU_Pos)                  /*!< 0x00000100 */\n#define RTC_TR_MNU_1                 (0x2UL << RTC_TR_MNU_Pos)                  /*!< 0x00000200 */\n#define RTC_TR_MNU_2                 (0x4UL << RTC_TR_MNU_Pos)                  /*!< 0x00000400 */\n#define RTC_TR_MNU_3                 (0x8UL << RTC_TR_MNU_Pos)                  /*!< 0x00000800 */\n#define RTC_TR_ST_Pos                (4U)\n#define RTC_TR_ST_Msk                (0x7UL << RTC_TR_ST_Pos)                   /*!< 0x00000070 */\n#define RTC_TR_ST                    RTC_TR_ST_Msk\n#define RTC_TR_ST_0                  (0x1UL << RTC_TR_ST_Pos)                   /*!< 0x00000010 */\n#define RTC_TR_ST_1                  (0x2UL << RTC_TR_ST_Pos)                   /*!< 0x00000020 */\n#define RTC_TR_ST_2                  (0x4UL << RTC_TR_ST_Pos)                   /*!< 0x00000040 */\n#define RTC_TR_SU_Pos                (0U)\n#define RTC_TR_SU_Msk                (0xFUL << RTC_TR_SU_Pos)                   /*!< 0x0000000F */\n#define RTC_TR_SU                    RTC_TR_SU_Msk\n#define RTC_TR_SU_0                  (0x1UL << RTC_TR_SU_Pos)                   /*!< 0x00000001 */\n#define RTC_TR_SU_1                  (0x2UL << RTC_TR_SU_Pos)                   /*!< 0x00000002 */\n#define RTC_TR_SU_2                  (0x4UL << RTC_TR_SU_Pos)                   /*!< 0x00000004 */\n#define RTC_TR_SU_3                  (0x8UL << RTC_TR_SU_Pos)                   /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_DR register  *******************/\n#define RTC_DR_YT_Pos                (20U)\n#define RTC_DR_YT_Msk                (0xFUL << RTC_DR_YT_Pos)                   /*!< 0x00F00000 */\n#define RTC_DR_YT                    RTC_DR_YT_Msk\n#define RTC_DR_YT_0                  (0x1UL << RTC_DR_YT_Pos)                   /*!< 0x00100000 */\n#define RTC_DR_YT_1                  (0x2UL << RTC_DR_YT_Pos)                   /*!< 0x00200000 */\n#define RTC_DR_YT_2                  (0x4UL << RTC_DR_YT_Pos)                   /*!< 0x00400000 */\n#define RTC_DR_YT_3                  (0x8UL << RTC_DR_YT_Pos)                   /*!< 0x00800000 */\n#define RTC_DR_YU_Pos                (16U)\n#define RTC_DR_YU_Msk                (0xFUL << RTC_DR_YU_Pos)                   /*!< 0x000F0000 */\n#define RTC_DR_YU                    RTC_DR_YU_Msk\n#define RTC_DR_YU_0                  (0x1UL << RTC_DR_YU_Pos)                   /*!< 0x00010000 */\n#define RTC_DR_YU_1                  (0x2UL << RTC_DR_YU_Pos)                   /*!< 0x00020000 */\n#define RTC_DR_YU_2                  (0x4UL << RTC_DR_YU_Pos)                   /*!< 0x00040000 */\n#define RTC_DR_YU_3                  (0x8UL << RTC_DR_YU_Pos)                   /*!< 0x00080000 */\n#define RTC_DR_WDU_Pos               (13U)\n#define RTC_DR_WDU_Msk               (0x7UL << RTC_DR_WDU_Pos)                  /*!< 0x0000E000 */\n#define RTC_DR_WDU                   RTC_DR_WDU_Msk\n#define RTC_DR_WDU_0                 (0x1UL << RTC_DR_WDU_Pos)                  /*!< 0x00002000 */\n#define RTC_DR_WDU_1                 (0x2UL << RTC_DR_WDU_Pos)                  /*!< 0x00004000 */\n#define RTC_DR_WDU_2                 (0x4UL << RTC_DR_WDU_Pos)                  /*!< 0x00008000 */\n#define RTC_DR_MT_Pos                (12U)\n#define RTC_DR_MT_Msk                (0x1UL << RTC_DR_MT_Pos)                   /*!< 0x00001000 */\n#define RTC_DR_MT                    RTC_DR_MT_Msk\n#define RTC_DR_MU_Pos                (8U)\n#define RTC_DR_MU_Msk                (0xFUL << RTC_DR_MU_Pos)                   /*!< 0x00000F00 */\n#define RTC_DR_MU                    RTC_DR_MU_Msk\n#define RTC_DR_MU_0                  (0x1UL << RTC_DR_MU_Pos)                   /*!< 0x00000100 */\n#define RTC_DR_MU_1                  (0x2UL << RTC_DR_MU_Pos)                   /*!< 0x00000200 */\n#define RTC_DR_MU_2                  (0x4UL << RTC_DR_MU_Pos)                   /*!< 0x00000400 */\n#define RTC_DR_MU_3                  (0x8UL << RTC_DR_MU_Pos)                   /*!< 0x00000800 */\n#define RTC_DR_DT_Pos                (4U)\n#define RTC_DR_DT_Msk                (0x3UL << RTC_DR_DT_Pos)                   /*!< 0x00000030 */\n#define RTC_DR_DT                    RTC_DR_DT_Msk\n#define RTC_DR_DT_0                  (0x1UL << RTC_DR_DT_Pos)                   /*!< 0x00000010 */\n#define RTC_DR_DT_1                  (0x2UL << RTC_DR_DT_Pos)                   /*!< 0x00000020 */\n#define RTC_DR_DU_Pos                (0U)\n#define RTC_DR_DU_Msk                (0xFUL << RTC_DR_DU_Pos)                   /*!< 0x0000000F */\n#define RTC_DR_DU                    RTC_DR_DU_Msk\n#define RTC_DR_DU_0                  (0x1UL << RTC_DR_DU_Pos)                   /*!< 0x00000001 */\n#define RTC_DR_DU_1                  (0x2UL << RTC_DR_DU_Pos)                   /*!< 0x00000002 */\n#define RTC_DR_DU_2                  (0x4UL << RTC_DR_DU_Pos)                   /*!< 0x00000004 */\n#define RTC_DR_DU_3                  (0x8UL << RTC_DR_DU_Pos)                   /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_SSR register  ******************/\n#define RTC_SSR_SS_Pos               (0U)\n#define RTC_SSR_SS_Msk               (0xFFFFUL << RTC_SSR_SS_Pos)               /*!< 0x0000FFFF */\n#define RTC_SSR_SS                   RTC_SSR_SS_Msk\n\n/********************  Bits definition for RTC_ICSR register  ******************/\n#define RTC_ICSR_RECALPF_Pos         (16U)\n#define RTC_ICSR_RECALPF_Msk         (0x1UL << RTC_ICSR_RECALPF_Pos)            /*!< 0x00010000 */\n#define RTC_ICSR_RECALPF             RTC_ICSR_RECALPF_Msk\n#define RTC_ICSR_INIT_Pos            (7U)\n#define RTC_ICSR_INIT_Msk            (0x1UL << RTC_ICSR_INIT_Pos)               /*!< 0x00000080 */\n#define RTC_ICSR_INIT                RTC_ICSR_INIT_Msk\n#define RTC_ICSR_INITF_Pos           (6U)\n#define RTC_ICSR_INITF_Msk           (0x1UL << RTC_ICSR_INITF_Pos)              /*!< 0x00000040 */\n#define RTC_ICSR_INITF               RTC_ICSR_INITF_Msk\n#define RTC_ICSR_RSF_Pos             (5U)\n#define RTC_ICSR_RSF_Msk             (0x1UL << RTC_ICSR_RSF_Pos)                /*!< 0x00000020 */\n#define RTC_ICSR_RSF                 RTC_ICSR_RSF_Msk\n#define RTC_ICSR_INITS_Pos           (4U)\n#define RTC_ICSR_INITS_Msk           (0x1UL << RTC_ICSR_INITS_Pos)              /*!< 0x00000010 */\n#define RTC_ICSR_INITS               RTC_ICSR_INITS_Msk\n#define RTC_ICSR_SHPF_Pos            (3U)\n#define RTC_ICSR_SHPF_Msk            (0x1UL << RTC_ICSR_SHPF_Pos)               /*!< 0x00000008 */\n#define RTC_ICSR_SHPF                RTC_ICSR_SHPF_Msk\n#define RTC_ICSR_ALRAWF_Pos          (0U)\n#define RTC_ICSR_ALRAWF_Msk          (0x1UL << RTC_ICSR_ALRAWF_Pos)             /*!< 0x00000001 */\n#define RTC_ICSR_ALRAWF              RTC_ICSR_ALRAWF_Msk\n\n/********************  Bits definition for RTC_PRER register  *****************/\n#define RTC_PRER_PREDIV_A_Pos        (16U)\n#define RTC_PRER_PREDIV_A_Msk        (0x7FUL << RTC_PRER_PREDIV_A_Pos)          /*!< 0x007F0000 */\n#define RTC_PRER_PREDIV_A            RTC_PRER_PREDIV_A_Msk\n#define RTC_PRER_PREDIV_S_Pos        (0U)\n#define RTC_PRER_PREDIV_S_Msk        (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)        /*!< 0x00007FFF */\n#define RTC_PRER_PREDIV_S            RTC_PRER_PREDIV_S_Msk\n/********************  Bits definition for RTC_CR register  *******************/\n#define RTC_CR_OUT2EN_Pos            (31U)\n#define RTC_CR_OUT2EN_Msk            (0x1UL << RTC_CR_OUT2EN_Pos)              /*!< 0x80000000 */\n#define RTC_CR_OUT2EN                RTC_CR_OUT2EN_Msk                         /*!< RTC_OUT2 output enable */\n#define RTC_CR_TAMPALRM_TYPE_Pos     (30U)\n#define RTC_CR_TAMPALRM_TYPE_Msk     (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos)       /*!< 0x40000000 */\n#define RTC_CR_TAMPALRM_TYPE         RTC_CR_TAMPALRM_TYPE_Msk                  /*!< TAMPALARM output type  */\n#define RTC_CR_TAMPALRM_PU_Pos       (29U)\n#define RTC_CR_TAMPALRM_PU_Msk       (0x1UL << RTC_CR_TAMPALRM_PU_Pos)         /*!< 0x20000000 */\n#define RTC_CR_TAMPALRM_PU           RTC_CR_TAMPALRM_PU_Msk                    /*!< TAMPALARM output pull-up config */\n#define RTC_CR_COE_Pos               (23U)\n#define RTC_CR_COE_Msk               (0x1UL << RTC_CR_COE_Pos)                 /*!< 0x00800000 */\n#define RTC_CR_COE                   RTC_CR_COE_Msk\n#define RTC_CR_OSEL_Pos              (21U)\n#define RTC_CR_OSEL_Msk              (0x3UL << RTC_CR_OSEL_Pos)                 /*!< 0x00600000 */\n#define RTC_CR_OSEL                  RTC_CR_OSEL_Msk\n#define RTC_CR_OSEL_0                (0x1UL << RTC_CR_OSEL_Pos)                 /*!< 0x00200000 */\n#define RTC_CR_OSEL_1                (0x2UL << RTC_CR_OSEL_Pos)                 /*!< 0x00400000 */\n#define RTC_CR_POL_Pos               (20U)\n#define RTC_CR_POL_Msk               (0x1UL << RTC_CR_POL_Pos)                  /*!< 0x00100000 */\n#define RTC_CR_POL                   RTC_CR_POL_Msk\n#define RTC_CR_COSEL_Pos             (19U)\n#define RTC_CR_COSEL_Msk             (0x1UL << RTC_CR_COSEL_Pos)                /*!< 0x00080000 */\n#define RTC_CR_COSEL                 RTC_CR_COSEL_Msk\n#define RTC_CR_BKP_Pos               (18U)\n#define RTC_CR_BKP_Msk               (0x1UL << RTC_CR_BKP_Pos)                  /*!< 0x00040000 */\n#define RTC_CR_BKP                   RTC_CR_BKP_Msk\n#define RTC_CR_SUB1H_Pos             (17U)\n#define RTC_CR_SUB1H_Msk             (0x1UL << RTC_CR_SUB1H_Pos)                /*!< 0x00020000 */\n#define RTC_CR_SUB1H                 RTC_CR_SUB1H_Msk\n#define RTC_CR_ADD1H_Pos             (16U)\n#define RTC_CR_ADD1H_Msk             (0x1UL << RTC_CR_ADD1H_Pos)                /*!< 0x00010000 */\n#define RTC_CR_ADD1H                 RTC_CR_ADD1H_Msk\n#define RTC_CR_TSIE_Pos              (15U)\n#define RTC_CR_TSIE_Msk              (0x1UL << RTC_CR_TSIE_Pos)                /*!< 0x00008000 */\n#define RTC_CR_TSIE                  RTC_CR_TSIE_Msk                           /*!< Timestamp interrupt enable > */\n#define RTC_CR_ALRAIE_Pos            (12U)\n#define RTC_CR_ALRAIE_Msk            (0x1UL << RTC_CR_ALRAIE_Pos)              /*!< 0x00001000 */\n#define RTC_CR_ALRAIE                RTC_CR_ALRAIE_Msk\n#define RTC_CR_TSE_Pos               (11U)\n#define RTC_CR_TSE_Msk               (0x1UL << RTC_CR_TSE_Pos)                 /*!< 0x00000800 */\n#define RTC_CR_TSE                   RTC_CR_TSE_Msk                            /*!< timestamp enable > */\n#define RTC_CR_ALRAE_Pos             (8U)\n#define RTC_CR_ALRAE_Msk             (0x1UL << RTC_CR_ALRAE_Pos)                /*!< 0x00000100 */\n#define RTC_CR_ALRAE                 RTC_CR_ALRAE_Msk\n#define RTC_CR_FMT_Pos               (6U)\n#define RTC_CR_FMT_Msk               (0x1UL << RTC_CR_FMT_Pos)                  /*!< 0x00000040 */\n#define RTC_CR_FMT                   RTC_CR_FMT_Msk\n#define RTC_CR_BYPSHAD_Pos           (5U)\n#define RTC_CR_BYPSHAD_Msk           (0x1UL << RTC_CR_BYPSHAD_Pos)              /*!< 0x00000020 */\n#define RTC_CR_BYPSHAD               RTC_CR_BYPSHAD_Msk\n#define RTC_CR_REFCKON_Pos           (4U)\n#define RTC_CR_REFCKON_Msk           (0x1UL << RTC_CR_REFCKON_Pos)              /*!< 0x00000010 */\n#define RTC_CR_REFCKON               RTC_CR_REFCKON_Msk\n#define RTC_CR_TSEDGE_Pos            (3U)\n#define RTC_CR_TSEDGE_Msk            (0x1UL << RTC_CR_TSEDGE_Pos)              /*!< 0x00000008 */\n#define RTC_CR_TSEDGE                RTC_CR_TSEDGE_Msk                         /*!< Timestamp event active edge > */\n\n/********************  Bits definition for RTC_WPR register  ******************/\n#define RTC_WPR_KEY_Pos              (0U)\n#define RTC_WPR_KEY_Msk              (0xFFUL << RTC_WPR_KEY_Pos)                /*!< 0x000000FF */\n#define RTC_WPR_KEY                  RTC_WPR_KEY_Msk\n\n/********************  Bits definition for RTC_CALR register  *****************/\n#define RTC_CALR_CALP_Pos            (15U)\n#define RTC_CALR_CALP_Msk            (0x1UL << RTC_CALR_CALP_Pos)               /*!< 0x00008000 */\n#define RTC_CALR_CALP                RTC_CALR_CALP_Msk\n#define RTC_CALR_CALW8_Pos           (14U)\n#define RTC_CALR_CALW8_Msk           (0x1UL << RTC_CALR_CALW8_Pos)              /*!< 0x00004000 */\n#define RTC_CALR_CALW8               RTC_CALR_CALW8_Msk\n#define RTC_CALR_CALW16_Pos          (13U)\n#define RTC_CALR_CALW16_Msk          (0x1UL << RTC_CALR_CALW16_Pos)             /*!< 0x00002000 */\n#define RTC_CALR_CALW16              RTC_CALR_CALW16_Msk\n#define RTC_CALR_CALM_Pos            (0U)\n#define RTC_CALR_CALM_Msk            (0x1FFUL << RTC_CALR_CALM_Pos)             /*!< 0x000001FF */\n#define RTC_CALR_CALM                RTC_CALR_CALM_Msk\n#define RTC_CALR_CALM_0              (0x001UL << RTC_CALR_CALM_Pos)             /*!< 0x00000001 */\n#define RTC_CALR_CALM_1              (0x002UL << RTC_CALR_CALM_Pos)             /*!< 0x00000002 */\n#define RTC_CALR_CALM_2              (0x004UL << RTC_CALR_CALM_Pos)             /*!< 0x00000004 */\n#define RTC_CALR_CALM_3              (0x008UL << RTC_CALR_CALM_Pos)             /*!< 0x00000008 */\n#define RTC_CALR_CALM_4              (0x010UL << RTC_CALR_CALM_Pos)             /*!< 0x00000010 */\n#define RTC_CALR_CALM_5              (0x020UL << RTC_CALR_CALM_Pos)             /*!< 0x00000020 */\n#define RTC_CALR_CALM_6              (0x040UL << RTC_CALR_CALM_Pos)             /*!< 0x00000040 */\n#define RTC_CALR_CALM_7              (0x080UL << RTC_CALR_CALM_Pos)             /*!< 0x00000080 */\n#define RTC_CALR_CALM_8              (0x100UL << RTC_CALR_CALM_Pos)             /*!< 0x00000100 */\n\n/********************  Bits definition for RTC_SHIFTR register  ***************/\n#define RTC_SHIFTR_ADD1S_Pos         (31U)\n#define RTC_SHIFTR_ADD1S_Msk         (0x1UL << RTC_SHIFTR_ADD1S_Pos)            /*!< 0x80000000 */\n#define RTC_SHIFTR_ADD1S             RTC_SHIFTR_ADD1S_Msk\n#define RTC_SHIFTR_SUBFS_Pos         (0U)\n#define RTC_SHIFTR_SUBFS_Msk         (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)         /*!< 0x00007FFF */\n#define RTC_SHIFTR_SUBFS             RTC_SHIFTR_SUBFS_Msk\n/********************  Bits definition for RTC_TSTR register  *****************/\n#define RTC_TSTR_PM_Pos              (22U)\n#define RTC_TSTR_PM_Msk              (0x1UL << RTC_TSTR_PM_Pos)                /*!< 0x00400000 */\n#define RTC_TSTR_PM                  RTC_TSTR_PM_Msk                           /*!< AM-PM notation > */\n#define RTC_TSTR_HT_Pos              (20U)\n#define RTC_TSTR_HT_Msk              (0x3UL << RTC_TSTR_HT_Pos)                /*!< 0x00300000 */\n#define RTC_TSTR_HT                  RTC_TSTR_HT_Msk\n#define RTC_TSTR_HT_0                (0x1UL << RTC_TSTR_HT_Pos)                /*!< 0x00100000 */\n#define RTC_TSTR_HT_1                (0x2UL << RTC_TSTR_HT_Pos)                /*!< 0x00200000 */\n#define RTC_TSTR_HU_Pos              (16U)\n#define RTC_TSTR_HU_Msk              (0xFUL << RTC_TSTR_HU_Pos)                /*!< 0x000F0000 */\n#define RTC_TSTR_HU                  RTC_TSTR_HU_Msk\n#define RTC_TSTR_HU_0                (0x1UL << RTC_TSTR_HU_Pos)                /*!< 0x00010000 */\n#define RTC_TSTR_HU_1                (0x2UL << RTC_TSTR_HU_Pos)                /*!< 0x00020000 */\n#define RTC_TSTR_HU_2                (0x4UL << RTC_TSTR_HU_Pos)                /*!< 0x00040000 */\n#define RTC_TSTR_HU_3                (0x8UL << RTC_TSTR_HU_Pos)                /*!< 0x00080000 */\n#define RTC_TSTR_MNT_Pos             (12U)\n#define RTC_TSTR_MNT_Msk             (0x7UL << RTC_TSTR_MNT_Pos)               /*!< 0x00007000 */\n#define RTC_TSTR_MNT                 RTC_TSTR_MNT_Msk\n#define RTC_TSTR_MNT_0               (0x1UL << RTC_TSTR_MNT_Pos)               /*!< 0x00001000 */\n#define RTC_TSTR_MNT_1               (0x2UL << RTC_TSTR_MNT_Pos)               /*!< 0x00002000 */\n#define RTC_TSTR_MNT_2               (0x4UL << RTC_TSTR_MNT_Pos)                /*!< 0x00004000 */\n#define RTC_TSTR_MNU_Pos             (8U)\n#define RTC_TSTR_MNU_Msk             (0xFUL << RTC_TSTR_MNU_Pos)                /*!< 0x00000F00 */\n#define RTC_TSTR_MNU                 RTC_TSTR_MNU_Msk\n#define RTC_TSTR_MNU_0               (0x1UL << RTC_TSTR_MNU_Pos)                /*!< 0x00000100 */\n#define RTC_TSTR_MNU_1               (0x2UL << RTC_TSTR_MNU_Pos)                /*!< 0x00000200 */\n#define RTC_TSTR_MNU_2               (0x4UL << RTC_TSTR_MNU_Pos)                /*!< 0x00000400 */\n#define RTC_TSTR_MNU_3               (0x8UL << RTC_TSTR_MNU_Pos)                /*!< 0x00000800 */\n#define RTC_TSTR_ST_Pos              (4U)\n#define RTC_TSTR_ST_Msk              (0x7UL << RTC_TSTR_ST_Pos)                 /*!< 0x00000070 */\n#define RTC_TSTR_ST                  RTC_TSTR_ST_Msk\n#define RTC_TSTR_ST_0                (0x1UL << RTC_TSTR_ST_Pos)                 /*!< 0x00000010 */\n#define RTC_TSTR_ST_1                (0x2UL << RTC_TSTR_ST_Pos)                 /*!< 0x00000020 */\n#define RTC_TSTR_ST_2                (0x4UL << RTC_TSTR_ST_Pos)                 /*!< 0x00000040 */\n#define RTC_TSTR_SU_Pos              (0U)\n#define RTC_TSTR_SU_Msk              (0xFUL << RTC_TSTR_SU_Pos)                 /*!< 0x0000000F */\n#define RTC_TSTR_SU                  RTC_TSTR_SU_Msk\n#define RTC_TSTR_SU_0                (0x1UL << RTC_TSTR_SU_Pos)                 /*!< 0x00000001 */\n#define RTC_TSTR_SU_1                (0x2UL << RTC_TSTR_SU_Pos)                 /*!< 0x00000002 */\n#define RTC_TSTR_SU_2                (0x4UL << RTC_TSTR_SU_Pos)                 /*!< 0x00000004 */\n#define RTC_TSTR_SU_3                (0x8UL << RTC_TSTR_SU_Pos)                 /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_TSDR register  *****************/\n#define RTC_TSDR_WDU_Pos             (13U)\n#define RTC_TSDR_WDU_Msk             (0x7UL << RTC_TSDR_WDU_Pos)               /*!< 0x0000E000 */\n#define RTC_TSDR_WDU                 RTC_TSDR_WDU_Msk                          /*!< Week day units > */\n#define RTC_TSDR_WDU_0               (0x1UL << RTC_TSDR_WDU_Pos)               /*!< 0x00002000 */\n#define RTC_TSDR_WDU_1               (0x2UL << RTC_TSDR_WDU_Pos)               /*!< 0x00004000 */\n#define RTC_TSDR_WDU_2               (0x4UL << RTC_TSDR_WDU_Pos)               /*!< 0x00008000 */\n#define RTC_TSDR_MT_Pos              (12U)\n#define RTC_TSDR_MT_Msk              (0x1UL << RTC_TSDR_MT_Pos)                /*!< 0x00001000 */\n#define RTC_TSDR_MT                  RTC_TSDR_MT_Msk\n#define RTC_TSDR_MU_Pos              (8U)\n#define RTC_TSDR_MU_Msk              (0xFUL << RTC_TSDR_MU_Pos)                /*!< 0x00000F00 */\n#define RTC_TSDR_MU                  RTC_TSDR_MU_Msk\n#define RTC_TSDR_MU_0                (0x1UL << RTC_TSDR_MU_Pos)                /*!< 0x00000100 */\n#define RTC_TSDR_MU_1                (0x2UL << RTC_TSDR_MU_Pos)                /*!< 0x00000200 */\n#define RTC_TSDR_MU_2                (0x4UL << RTC_TSDR_MU_Pos)                /*!< 0x00000400 */\n#define RTC_TSDR_MU_3                (0x8UL << RTC_TSDR_MU_Pos)                /*!< 0x00000800 */\n#define RTC_TSDR_DT_Pos              (4U)\n#define RTC_TSDR_DT_Msk              (0x3UL << RTC_TSDR_DT_Pos)                /*!< 0x00000030 */\n#define RTC_TSDR_DT                  RTC_TSDR_DT_Msk\n#define RTC_TSDR_DT_0                (0x1UL << RTC_TSDR_DT_Pos)                /*!< 0x00000010 */\n#define RTC_TSDR_DT_1                (0x2UL << RTC_TSDR_DT_Pos)                /*!< 0x00000020 */\n#define RTC_TSDR_DU_Pos              (0U)\n#define RTC_TSDR_DU_Msk              (0xFUL << RTC_TSDR_DU_Pos)                /*!< 0x0000000F */\n#define RTC_TSDR_DU                  RTC_TSDR_DU_Msk\n#define RTC_TSDR_DU_0                (0x1UL << RTC_TSDR_DU_Pos)                /*!< 0x00000001 */\n#define RTC_TSDR_DU_1                (0x2UL << RTC_TSDR_DU_Pos)                /*!< 0x00000002 */\n#define RTC_TSDR_DU_2                (0x4UL << RTC_TSDR_DU_Pos)                /*!< 0x00000004 */\n#define RTC_TSDR_DU_3                (0x8UL << RTC_TSDR_DU_Pos)                /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_TSSSR register  ****************/\n#define RTC_TSSSR_SS_Pos             (0U)\n#define RTC_TSSSR_SS_Msk             (0xFFFFUL << RTC_TSSSR_SS_Pos)            /*!< 0x0000FFFF */\n#define RTC_TSSSR_SS                 RTC_TSSSR_SS_Msk                          /*!< Sub second value > */\n\n/********************  Bits definition for RTC_ALRMAR register  ***************/\n#define RTC_ALRMAR_MSK4_Pos          (31U)\n#define RTC_ALRMAR_MSK4_Msk          (0x1UL << RTC_ALRMAR_MSK4_Pos)            /*!< 0x80000000 */\n#define RTC_ALRMAR_MSK4              RTC_ALRMAR_MSK4_Msk\n#define RTC_ALRMAR_WDSEL_Pos         (30U)\n#define RTC_ALRMAR_WDSEL_Msk         (0x1UL << RTC_ALRMAR_WDSEL_Pos)           /*!< 0x40000000 */\n#define RTC_ALRMAR_WDSEL             RTC_ALRMAR_WDSEL_Msk\n#define RTC_ALRMAR_DT_Pos            (28U)\n#define RTC_ALRMAR_DT_Msk            (0x3UL << RTC_ALRMAR_DT_Pos)              /*!< 0x30000000 */\n#define RTC_ALRMAR_DT                RTC_ALRMAR_DT_Msk\n#define RTC_ALRMAR_DT_0              (0x1UL << RTC_ALRMAR_DT_Pos)              /*!< 0x10000000 */\n#define RTC_ALRMAR_DT_1              (0x2UL << RTC_ALRMAR_DT_Pos)              /*!< 0x20000000 */\n#define RTC_ALRMAR_DU_Pos            (24U)\n#define RTC_ALRMAR_DU_Msk            (0xFUL << RTC_ALRMAR_DU_Pos)              /*!< 0x0F000000 */\n#define RTC_ALRMAR_DU                RTC_ALRMAR_DU_Msk\n#define RTC_ALRMAR_DU_0              (0x1UL << RTC_ALRMAR_DU_Pos)              /*!< 0x01000000 */\n#define RTC_ALRMAR_DU_1              (0x2UL << RTC_ALRMAR_DU_Pos)              /*!< 0x02000000 */\n#define RTC_ALRMAR_DU_2              (0x4UL << RTC_ALRMAR_DU_Pos)              /*!< 0x04000000 */\n#define RTC_ALRMAR_DU_3              (0x8UL << RTC_ALRMAR_DU_Pos)              /*!< 0x08000000 */\n#define RTC_ALRMAR_MSK3_Pos          (23U)\n#define RTC_ALRMAR_MSK3_Msk          (0x1UL << RTC_ALRMAR_MSK3_Pos)            /*!< 0x00800000 */\n#define RTC_ALRMAR_MSK3              RTC_ALRMAR_MSK3_Msk\n#define RTC_ALRMAR_PM_Pos            (22U)\n#define RTC_ALRMAR_PM_Msk            (0x1UL << RTC_ALRMAR_PM_Pos)              /*!< 0x00400000 */\n#define RTC_ALRMAR_PM                RTC_ALRMAR_PM_Msk\n#define RTC_ALRMAR_HT_Pos            (20U)\n#define RTC_ALRMAR_HT_Msk            (0x3UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00300000 */\n#define RTC_ALRMAR_HT                RTC_ALRMAR_HT_Msk\n#define RTC_ALRMAR_HT_0              (0x1UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00100000 */\n#define RTC_ALRMAR_HT_1              (0x2UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00200000 */\n#define RTC_ALRMAR_HU_Pos            (16U)\n#define RTC_ALRMAR_HU_Msk            (0xFUL << RTC_ALRMAR_HU_Pos)              /*!< 0x000F0000 */\n#define RTC_ALRMAR_HU                RTC_ALRMAR_HU_Msk\n#define RTC_ALRMAR_HU_0              (0x1UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00010000 */\n#define RTC_ALRMAR_HU_1              (0x2UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00020000 */\n#define RTC_ALRMAR_HU_2              (0x4UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00040000 */\n#define RTC_ALRMAR_HU_3              (0x8UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00080000 */\n#define RTC_ALRMAR_MSK2_Pos          (15U)\n#define RTC_ALRMAR_MSK2_Msk          (0x1UL << RTC_ALRMAR_MSK2_Pos)            /*!< 0x00008000 */\n#define RTC_ALRMAR_MSK2              RTC_ALRMAR_MSK2_Msk\n#define RTC_ALRMAR_MNT_Pos           (12U)\n#define RTC_ALRMAR_MNT_Msk           (0x7UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00007000 */\n#define RTC_ALRMAR_MNT               RTC_ALRMAR_MNT_Msk\n#define RTC_ALRMAR_MNT_0             (0x1UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00001000 */\n#define RTC_ALRMAR_MNT_1             (0x2UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00002000 */\n#define RTC_ALRMAR_MNT_2             (0x4UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00004000 */\n#define RTC_ALRMAR_MNU_Pos           (8U)\n#define RTC_ALRMAR_MNU_Msk           (0xFUL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000F00 */\n#define RTC_ALRMAR_MNU               RTC_ALRMAR_MNU_Msk\n#define RTC_ALRMAR_MNU_0             (0x1UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000100 */\n#define RTC_ALRMAR_MNU_1             (0x2UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000200 */\n#define RTC_ALRMAR_MNU_2             (0x4UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000400 */\n#define RTC_ALRMAR_MNU_3             (0x8UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000800 */\n#define RTC_ALRMAR_MSK1_Pos          (7U)\n#define RTC_ALRMAR_MSK1_Msk          (0x1UL << RTC_ALRMAR_MSK1_Pos)            /*!< 0x00000080 */\n#define RTC_ALRMAR_MSK1              RTC_ALRMAR_MSK1_Msk\n#define RTC_ALRMAR_ST_Pos            (4U)\n#define RTC_ALRMAR_ST_Msk            (0x7UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000070 */\n#define RTC_ALRMAR_ST                RTC_ALRMAR_ST_Msk\n#define RTC_ALRMAR_ST_0              (0x1UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000010 */\n#define RTC_ALRMAR_ST_1              (0x2UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000020 */\n#define RTC_ALRMAR_ST_2              (0x4UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000040 */\n#define RTC_ALRMAR_SU_Pos            (0U)\n#define RTC_ALRMAR_SU_Msk            (0xFUL << RTC_ALRMAR_SU_Pos)              /*!< 0x0000000F */\n#define RTC_ALRMAR_SU                RTC_ALRMAR_SU_Msk\n#define RTC_ALRMAR_SU_0              (0x1UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000001 */\n#define RTC_ALRMAR_SU_1              (0x2UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000002 */\n#define RTC_ALRMAR_SU_2              (0x4UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000004 */\n#define RTC_ALRMAR_SU_3              (0x8UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_ALRMASSR register  *************/\n#define RTC_ALRMASSR_MASKSS_Pos      (24U)\n#define RTC_ALRMASSR_MASKSS_Msk      (0xFUL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x0F000000 */\n#define RTC_ALRMASSR_MASKSS          RTC_ALRMASSR_MASKSS_Msk\n#define RTC_ALRMASSR_MASKSS_0        (0x1UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x01000000 */\n#define RTC_ALRMASSR_MASKSS_1        (0x2UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x02000000 */\n#define RTC_ALRMASSR_MASKSS_2        (0x4UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x04000000 */\n#define RTC_ALRMASSR_MASKSS_3        (0x8UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x08000000 */\n#define RTC_ALRMASSR_SS_Pos          (0U)\n#define RTC_ALRMASSR_SS_Msk          (0x7FFFUL << RTC_ALRMASSR_SS_Pos)         /*!< 0x00007FFF */\n#define RTC_ALRMASSR_SS              RTC_ALRMASSR_SS_Msk\n\n/********************  Bits definition for RTC_SR register  *******************/\n#define RTC_SR_TSOVF_Pos             (4U)\n#define RTC_SR_TSOVF_Msk             (0x1UL << RTC_SR_TSOVF_Pos)               /*!< 0x00000010 */\n#define RTC_SR_TSOVF                 RTC_SR_TSOVF_Msk                          /*!< Timestamp overflow flag > */\n#define RTC_SR_TSF_Pos               (3U)\n#define RTC_SR_TSF_Msk               (0x1UL << RTC_SR_TSF_Pos)                 /*!< 0x00000008 */\n#define RTC_SR_TSF                   RTC_SR_TSF_Msk                            /*!< Timestamp flag > */\n#define RTC_SR_ALRAF_Pos             (0U)\n#define RTC_SR_ALRAF_Msk             (0x1UL << RTC_SR_ALRAF_Pos)               /*!< 0x00000001 */\n#define RTC_SR_ALRAF                 RTC_SR_ALRAF_Msk\n\n/********************  Bits definition for RTC_MISR register  *****************/\n#define RTC_MISR_TSOVMF_Pos          (4U)\n#define RTC_MISR_TSOVMF_Msk          (0x1UL << RTC_MISR_TSOVMF_Pos)            /*!< 0x00000010 */\n#define RTC_MISR_TSOVMF              RTC_MISR_TSOVMF_Msk                       /*!< Timestamp overflow masked flag > */\n#define RTC_MISR_TSMF_Pos            (3U)\n#define RTC_MISR_TSMF_Msk            (0x1UL << RTC_MISR_TSMF_Pos)              /*!< 0x00000008 */\n#define RTC_MISR_TSMF                RTC_MISR_TSMF_Msk                         /*!< Timestamp masked flag > */\n#define RTC_MISR_ALRAMF_Pos          (0U)\n#define RTC_MISR_ALRAMF_Msk          (0x1UL << RTC_MISR_ALRAMF_Pos)            /*!< 0x00000001 */\n#define RTC_MISR_ALRAMF              RTC_MISR_ALRAMF_Msk\n\n/********************  Bits definition for RTC_SCR register  ******************/\n#define RTC_SCR_CTSOVF_Pos           (4U)\n#define RTC_SCR_CTSOVF_Msk           (0x1UL << RTC_SCR_CTSOVF_Pos)             /*!< 0x00000010 */\n#define RTC_SCR_CTSOVF               RTC_SCR_CTSOVF_Msk                        /*!< Clear timestamp overflow flag > */\n#define RTC_SCR_CTSF_Pos             (3U)\n#define RTC_SCR_CTSF_Msk             (0x1UL << RTC_SCR_CTSF_Pos)               /*!< 0x00000008 */\n#define RTC_SCR_CTSF                 RTC_SCR_CTSF_Msk                          /*!< Clear timestamp flag > */\n#define RTC_SCR_CALRAF_Pos           (0U)\n#define RTC_SCR_CALRAF_Msk           (0x1UL << RTC_SCR_CALRAF_Pos)             /*!< 0x00000001 */\n#define RTC_SCR_CALRAF               RTC_SCR_CALRAF_Msk\n\n/******************************************************************************/\n/*                                                                            */\n/*                        Serial Peripheral Interface (SPI)                   */\n/*                                                                            */\n/******************************************************************************/\n\n#define SPI_I2S_SUPPORT                       /*!< I2S support */\n\n/*******************  Bit definition for SPI_CR1 register  ********************/\n#define SPI_CR1_CPHA_Pos            (0U)\n#define SPI_CR1_CPHA_Msk            (0x1UL << SPI_CR1_CPHA_Pos)                /*!< 0x00000001 */\n#define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!<Clock Phase      */\n#define SPI_CR1_CPOL_Pos            (1U)\n#define SPI_CR1_CPOL_Msk            (0x1UL << SPI_CR1_CPOL_Pos)                /*!< 0x00000002 */\n#define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!<Clock Polarity   */\n#define SPI_CR1_MSTR_Pos            (2U)\n#define SPI_CR1_MSTR_Msk            (0x1UL << SPI_CR1_MSTR_Pos)                /*!< 0x00000004 */\n#define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!<Master Selection */\n\n#define SPI_CR1_BR_Pos              (3U)\n#define SPI_CR1_BR_Msk              (0x7UL << SPI_CR1_BR_Pos)                  /*!< 0x00000038 */\n#define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!<BR[2:0] bits (Baud Rate Control) */\n#define SPI_CR1_BR_0                (0x1UL << SPI_CR1_BR_Pos)                  /*!< 0x00000008 */\n#define SPI_CR1_BR_1                (0x2UL << SPI_CR1_BR_Pos)                  /*!< 0x00000010 */\n#define SPI_CR1_BR_2                (0x4UL << SPI_CR1_BR_Pos)                  /*!< 0x00000020 */\n\n#define SPI_CR1_SPE_Pos             (6U)\n#define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                 /*!< 0x00000040 */\n#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<SPI Enable                          */\n#define SPI_CR1_LSBFIRST_Pos        (7U)\n#define SPI_CR1_LSBFIRST_Msk        (0x1UL << SPI_CR1_LSBFIRST_Pos)            /*!< 0x00000080 */\n#define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!<Frame Format                        */\n#define SPI_CR1_SSI_Pos             (8U)\n#define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                 /*!< 0x00000100 */\n#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal slave select               */\n#define SPI_CR1_SSM_Pos             (9U)\n#define SPI_CR1_SSM_Msk             (0x1UL << SPI_CR1_SSM_Pos)                 /*!< 0x00000200 */\n#define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!<Software slave management           */\n#define SPI_CR1_RXONLY_Pos          (10U)\n#define SPI_CR1_RXONLY_Msk          (0x1UL << SPI_CR1_RXONLY_Pos)              /*!< 0x00000400 */\n#define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!<Receive only                        */\n#define SPI_CR1_CRCL_Pos            (11U)\n#define SPI_CR1_CRCL_Msk            (0x1UL << SPI_CR1_CRCL_Pos)                /*!< 0x00000800 */\n#define SPI_CR1_CRCL                SPI_CR1_CRCL_Msk                           /*!< CRC Length */\n#define SPI_CR1_CRCNEXT_Pos         (12U)\n#define SPI_CR1_CRCNEXT_Msk         (0x1UL << SPI_CR1_CRCNEXT_Pos)             /*!< 0x00001000 */\n#define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!<Transmit CRC next                   */\n#define SPI_CR1_CRCEN_Pos           (13U)\n#define SPI_CR1_CRCEN_Msk           (0x1UL << SPI_CR1_CRCEN_Pos)               /*!< 0x00002000 */\n#define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!<Hardware CRC calculation enable     */\n#define SPI_CR1_BIDIOE_Pos          (14U)\n#define SPI_CR1_BIDIOE_Msk          (0x1UL << SPI_CR1_BIDIOE_Pos)              /*!< 0x00004000 */\n#define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!<Output enable in bidirectional mode */\n#define SPI_CR1_BIDIMODE_Pos        (15U)\n#define SPI_CR1_BIDIMODE_Msk        (0x1UL << SPI_CR1_BIDIMODE_Pos)            /*!< 0x00008000 */\n#define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!<Bidirectional data mode enable      */\n\n/*******************  Bit definition for SPI_CR2 register  ********************/\n#define SPI_CR2_RXDMAEN_Pos         (0U)\n#define SPI_CR2_RXDMAEN_Msk         (0x1UL << SPI_CR2_RXDMAEN_Pos)             /*!< 0x00000001 */\n#define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!< Rx Buffer DMA Enable */\n#define SPI_CR2_TXDMAEN_Pos         (1U)\n#define SPI_CR2_TXDMAEN_Msk         (0x1UL << SPI_CR2_TXDMAEN_Pos)             /*!< 0x00000002 */\n#define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!< Tx Buffer DMA Enable */\n#define SPI_CR2_SSOE_Pos            (2U)\n#define SPI_CR2_SSOE_Msk            (0x1UL << SPI_CR2_SSOE_Pos)                /*!< 0x00000004 */\n#define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!< SS Output Enable */\n#define SPI_CR2_NSSP_Pos            (3U)\n#define SPI_CR2_NSSP_Msk            (0x1UL << SPI_CR2_NSSP_Pos)                /*!< 0x00000008 */\n#define SPI_CR2_NSSP                SPI_CR2_NSSP_Msk                           /*!< NSS pulse management Enable */\n#define SPI_CR2_FRF_Pos             (4U)\n#define SPI_CR2_FRF_Msk             (0x1UL << SPI_CR2_FRF_Pos)                 /*!< 0x00000010 */\n#define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!< Frame Format Enable */\n#define SPI_CR2_ERRIE_Pos           (5U)\n#define SPI_CR2_ERRIE_Msk           (0x1UL << SPI_CR2_ERRIE_Pos)               /*!< 0x00000020 */\n#define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!< Error Interrupt Enable */\n#define SPI_CR2_RXNEIE_Pos          (6U)\n#define SPI_CR2_RXNEIE_Msk          (0x1UL << SPI_CR2_RXNEIE_Pos)              /*!< 0x00000040 */\n#define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!< RX buffer Not Empty Interrupt Enable */\n#define SPI_CR2_TXEIE_Pos           (7U)\n#define SPI_CR2_TXEIE_Msk           (0x1UL << SPI_CR2_TXEIE_Pos)               /*!< 0x00000080 */\n#define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!< Tx buffer Empty Interrupt Enable */\n#define SPI_CR2_DS_Pos              (8U)\n#define SPI_CR2_DS_Msk              (0xFUL << SPI_CR2_DS_Pos)                  /*!< 0x00000F00 */\n#define SPI_CR2_DS                  SPI_CR2_DS_Msk                             /*!< DS[3:0] Data Size */\n#define SPI_CR2_DS_0                (0x1UL << SPI_CR2_DS_Pos)                  /*!< 0x00000100 */\n#define SPI_CR2_DS_1                (0x2UL << SPI_CR2_DS_Pos)                  /*!< 0x00000200 */\n#define SPI_CR2_DS_2                (0x4UL << SPI_CR2_DS_Pos)                  /*!< 0x00000400 */\n#define SPI_CR2_DS_3                (0x8UL << SPI_CR2_DS_Pos)                  /*!< 0x00000800 */\n#define SPI_CR2_FRXTH_Pos           (12U)\n#define SPI_CR2_FRXTH_Msk           (0x1UL << SPI_CR2_FRXTH_Pos)               /*!< 0x00001000 */\n#define SPI_CR2_FRXTH               SPI_CR2_FRXTH_Msk                          /*!< FIFO reception Threshold */\n#define SPI_CR2_LDMARX_Pos          (13U)\n#define SPI_CR2_LDMARX_Msk          (0x1UL << SPI_CR2_LDMARX_Pos)              /*!< 0x00002000 */\n#define SPI_CR2_LDMARX              SPI_CR2_LDMARX_Msk                         /*!< Last DMA transfer for reception */\n#define SPI_CR2_LDMATX_Pos          (14U)\n#define SPI_CR2_LDMATX_Msk          (0x1UL << SPI_CR2_LDMATX_Pos)              /*!< 0x00004000 */\n#define SPI_CR2_LDMATX              SPI_CR2_LDMATX_Msk                         /*!< Last DMA transfer for transmission */\n\n/********************  Bit definition for SPI_SR register  ********************/\n#define SPI_SR_RXNE_Pos             (0U)\n#define SPI_SR_RXNE_Msk             (0x1UL << SPI_SR_RXNE_Pos)                 /*!< 0x00000001 */\n#define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!< Receive buffer Not Empty */\n#define SPI_SR_TXE_Pos              (1U)\n#define SPI_SR_TXE_Msk              (0x1UL << SPI_SR_TXE_Pos)                  /*!< 0x00000002 */\n#define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!< Transmit buffer Empty */\n#define SPI_SR_CHSIDE_Pos           (2U)\n#define SPI_SR_CHSIDE_Msk           (0x1UL << SPI_SR_CHSIDE_Pos)               /*!< 0x00000004 */\n#define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!< Channel side */\n#define SPI_SR_UDR_Pos              (3U)\n#define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                  /*!< 0x00000008 */\n#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!< Underrun flag */\n#define SPI_SR_CRCERR_Pos           (4U)\n#define SPI_SR_CRCERR_Msk           (0x1UL << SPI_SR_CRCERR_Pos)               /*!< 0x00000010 */\n#define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!< CRC Error flag */\n#define SPI_SR_MODF_Pos             (5U)\n#define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                 /*!< 0x00000020 */\n#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!< Mode fault */\n#define SPI_SR_OVR_Pos              (6U)\n#define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                  /*!< 0x00000040 */\n#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!< Overrun flag */\n#define SPI_SR_BSY_Pos              (7U)\n#define SPI_SR_BSY_Msk              (0x1UL << SPI_SR_BSY_Pos)                  /*!< 0x00000080 */\n#define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!< Busy flag */\n#define SPI_SR_FRE_Pos              (8U)\n#define SPI_SR_FRE_Msk              (0x1UL << SPI_SR_FRE_Pos)                  /*!< 0x00000100 */\n#define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!< TI frame format error */\n#define SPI_SR_FRLVL_Pos            (9U)\n#define SPI_SR_FRLVL_Msk            (0x3UL << SPI_SR_FRLVL_Pos)                /*!< 0x00000600 */\n#define SPI_SR_FRLVL                SPI_SR_FRLVL_Msk                           /*!< FIFO Reception Level */\n#define SPI_SR_FRLVL_0              (0x1UL << SPI_SR_FRLVL_Pos)                /*!< 0x00000200 */\n#define SPI_SR_FRLVL_1              (0x2UL << SPI_SR_FRLVL_Pos)                /*!< 0x00000400 */\n#define SPI_SR_FTLVL_Pos            (11U)\n#define SPI_SR_FTLVL_Msk            (0x3UL << SPI_SR_FTLVL_Pos)                /*!< 0x00001800 */\n#define SPI_SR_FTLVL                SPI_SR_FTLVL_Msk                           /*!< FIFO Transmission Level */\n#define SPI_SR_FTLVL_0              (0x1UL << SPI_SR_FTLVL_Pos)                /*!< 0x00000800 */\n#define SPI_SR_FTLVL_1              (0x2UL << SPI_SR_FTLVL_Pos)                /*!< 0x00001000 */\n\n/********************  Bit definition for SPI_DR register  ********************/\n#define SPI_DR_DR_Pos               (0U)\n#define SPI_DR_DR_Msk               (0xFFFFUL << SPI_DR_DR_Pos)                /*!< 0x0000FFFF */\n#define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!<Data Register           */\n\n/*******************  Bit definition for SPI_CRCPR register  ******************/\n#define SPI_CRCPR_CRCPOLY_Pos       (0U)\n#define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)        /*!< 0x0000FFFF */\n#define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!<CRC polynomial register */\n\n/******************  Bit definition for SPI_RXCRCR register  ******************/\n#define SPI_RXCRCR_RXCRC_Pos        (0U)\n#define SPI_RXCRCR_RXCRC_Msk        (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)         /*!< 0x0000FFFF */\n#define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!<Rx CRC Register         */\n\n/******************  Bit definition for SPI_TXCRCR register  ******************/\n#define SPI_TXCRCR_TXCRC_Pos        (0U)\n#define SPI_TXCRCR_TXCRC_Msk        (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)         /*!< 0x0000FFFF */\n#define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!<Tx CRC Register         */\n\n/******************  Bit definition for SPI_I2SCFGR register  *****************/\n#define SPI_I2SCFGR_CHLEN_Pos       (0U)\n#define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)           /*!< 0x00000001 */\n#define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */\n#define SPI_I2SCFGR_DATLEN_Pos      (1U)\n#define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000006 */\n#define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] bits (Data length to be transferred) */\n#define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000002 */\n#define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000004 */\n#define SPI_I2SCFGR_CKPOL_Pos       (3U)\n#define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)           /*!< 0x00000008 */\n#define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<steady state clock polarity */\n#define SPI_I2SCFGR_I2SSTD_Pos      (4U)\n#define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000030 */\n#define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] bits (I2S standard selection) */\n#define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000010 */\n#define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000020 */\n#define SPI_I2SCFGR_PCMSYNC_Pos     (7U)\n#define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)         /*!< 0x00000080 */\n#define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization */\n#define SPI_I2SCFGR_I2SCFG_Pos      (8U)\n#define SPI_I2SCFGR_I2SCFG_Msk      (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x00000300 */\n#define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[1:0] bits (I2S configuration mode) */\n#define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x00000100 */\n#define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x00000200 */\n#define SPI_I2SCFGR_I2SE_Pos        (10U)\n#define SPI_I2SCFGR_I2SE_Msk        (0x1UL << SPI_I2SCFGR_I2SE_Pos)            /*!< 0x00000400 */\n#define SPI_I2SCFGR_I2SE            SPI_I2SCFGR_I2SE_Msk                       /*!<I2S Enable */\n#define SPI_I2SCFGR_I2SMOD_Pos      (11U)\n#define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)          /*!< 0x00000800 */\n#define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */\n#define SPI_I2SCFGR_ASTRTEN_Pos     (12U)\n#define SPI_I2SCFGR_ASTRTEN_Msk     (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos)         /*!< 0x00001000 */\n#define SPI_I2SCFGR_ASTRTEN         SPI_I2SCFGR_ASTRTEN_Msk                    /*!<Asynchronous start enable */\n\n/******************  Bit definition for SPI_I2SPR register  *******************/\n#define SPI_I2SPR_I2SDIV_Pos        (0U)\n#define SPI_I2SPR_I2SDIV_Msk        (0xFFUL << SPI_I2SPR_I2SDIV_Pos)           /*!< 0x000000FF */\n#define SPI_I2SPR_I2SDIV            SPI_I2SPR_I2SDIV_Msk                       /*!<I2S Linear prescaler */\n#define SPI_I2SPR_ODD_Pos           (8U)\n#define SPI_I2SPR_ODD_Msk           (0x1UL << SPI_I2SPR_ODD_Pos)               /*!< 0x00000100 */\n#define SPI_I2SPR_ODD               SPI_I2SPR_ODD_Msk                          /*!<Odd factor for the prescaler */\n#define SPI_I2SPR_MCKOE_Pos         (9U)\n#define SPI_I2SPR_MCKOE_Msk         (0x1UL << SPI_I2SPR_MCKOE_Pos)             /*!< 0x00000200 */\n#define SPI_I2SPR_MCKOE             SPI_I2SPR_MCKOE_Msk                        /*!<Master Clock Output Enable */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                 SYSCFG                                     */\n/*                                                                            */\n/******************************************************************************/\n/*****************  Bit definition for SYSCFG_CFGR1 register  ****************/\n#define SYSCFG_CFGR1_MEM_MODE_Pos             (0U)\n#define SYSCFG_CFGR1_MEM_MODE_Msk             (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */\n#define SYSCFG_CFGR1_MEM_MODE                 SYSCFG_CFGR1_MEM_MODE_Msk            /*!< SYSCFG_Memory Remap Config */\n#define SYSCFG_CFGR1_MEM_MODE_0               (0x1UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */\n#define SYSCFG_CFGR1_MEM_MODE_1               (0x2UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */\n#define SYSCFG_CFGR1_PA11_RMP_Pos             (3U)\n#define SYSCFG_CFGR1_PA11_RMP_Msk             (0x1UL << SYSCFG_CFGR1_PA11_RMP_Pos) /*!< 0x00000008 */\n#define SYSCFG_CFGR1_PA11_RMP                 SYSCFG_CFGR1_PA11_RMP_Msk            /*!< PA11 Remap */\n#define SYSCFG_CFGR1_PA12_RMP_Pos             (4U)\n#define SYSCFG_CFGR1_PA12_RMP_Msk             (0x1UL << SYSCFG_CFGR1_PA12_RMP_Pos) /*!< 0x00000010 */\n#define SYSCFG_CFGR1_PA12_RMP                 SYSCFG_CFGR1_PA12_RMP_Msk            /*!< PA12 Remap */\n#define SYSCFG_CFGR1_IR_POL_Pos               (5U)\n#define SYSCFG_CFGR1_IR_POL_Msk               (0x1UL << SYSCFG_CFGR1_IR_POL_Pos) /*!< 0x00000020 */\n#define SYSCFG_CFGR1_IR_POL                   SYSCFG_CFGR1_IR_POL_Msk            /*!< IROut Polarity Selection */\n#define SYSCFG_CFGR1_IR_MOD_Pos               (6U)\n#define SYSCFG_CFGR1_IR_MOD_Msk               (0x3UL << SYSCFG_CFGR1_IR_MOD_Pos) /*!< 0x000000C0 */\n#define SYSCFG_CFGR1_IR_MOD                   SYSCFG_CFGR1_IR_MOD_Msk            /*!< IRDA Modulation Envelope signal source selection */\n#define SYSCFG_CFGR1_IR_MOD_0                 (0x1UL << SYSCFG_CFGR1_IR_MOD_Pos) /*!< 0x00000040 */\n#define SYSCFG_CFGR1_IR_MOD_1                 (0x2UL << SYSCFG_CFGR1_IR_MOD_Pos) /*!< 0x00000080 */\n#define SYSCFG_CFGR1_BOOSTEN_Pos              (8U)\n#define SYSCFG_CFGR1_BOOSTEN_Msk              (0x1UL << SYSCFG_CFGR1_BOOSTEN_Pos) /*!< 0x00000100 */\n#define SYSCFG_CFGR1_BOOSTEN                  SYSCFG_CFGR1_BOOSTEN_Msk            /*!< I/O analog switch voltage booster enable */\n#define SYSCFG_CFGR1_I2C_PB6_FMP_Pos          (16U)\n#define SYSCFG_CFGR1_I2C_PB6_FMP_Msk          (0x1UL << SYSCFG_CFGR1_I2C_PB6_FMP_Pos)  /*!< 0x00010000 */\n#define SYSCFG_CFGR1_I2C_PB6_FMP              SYSCFG_CFGR1_I2C_PB6_FMP_Msk             /*!< I2C PB6 Fast mode plus */\n#define SYSCFG_CFGR1_I2C_PB7_FMP_Pos          (17U)\n#define SYSCFG_CFGR1_I2C_PB7_FMP_Msk          (0x1UL << SYSCFG_CFGR1_I2C_PB7_FMP_Pos)  /*!< 0x00020000 */\n#define SYSCFG_CFGR1_I2C_PB7_FMP              SYSCFG_CFGR1_I2C_PB7_FMP_Msk             /*!< I2C PB7 Fast mode plus */\n#define SYSCFG_CFGR1_I2C_PB8_FMP_Pos          (18U)\n#define SYSCFG_CFGR1_I2C_PB8_FMP_Msk          (0x1UL << SYSCFG_CFGR1_I2C_PB8_FMP_Pos)  /*!< 0x00040000 */\n#define SYSCFG_CFGR1_I2C_PB8_FMP              SYSCFG_CFGR1_I2C_PB8_FMP_Msk             /*!< I2C PB8 Fast mode plus */\n#define SYSCFG_CFGR1_I2C_PB9_FMP_Pos          (19U)\n#define SYSCFG_CFGR1_I2C_PB9_FMP_Msk          (0x1UL << SYSCFG_CFGR1_I2C_PB9_FMP_Pos)  /*!< 0x00080000 */\n#define SYSCFG_CFGR1_I2C_PB9_FMP              SYSCFG_CFGR1_I2C_PB9_FMP_Msk             /*!< I2C PB9 Fast mode plus */\n#define SYSCFG_CFGR1_I2C1_FMP_Pos             (20U)\n#define SYSCFG_CFGR1_I2C1_FMP_Msk             (0x1UL << SYSCFG_CFGR1_I2C1_FMP_Pos)     /*!< 0x00100000 */\n#define SYSCFG_CFGR1_I2C1_FMP                 SYSCFG_CFGR1_I2C1_FMP_Msk                /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7  */\n#define SYSCFG_CFGR1_I2C2_FMP_Pos             (21U)\n#define SYSCFG_CFGR1_I2C2_FMP_Msk             (0x1UL << SYSCFG_CFGR1_I2C2_FMP_Pos)     /*!< 0x00200000 */\n#define SYSCFG_CFGR1_I2C2_FMP                 SYSCFG_CFGR1_I2C2_FMP_Msk                /*!< Enable I2C2 Fast mode plus  */\n#define SYSCFG_CFGR1_I2C_PA9_FMP_Pos          (22U)\n#define SYSCFG_CFGR1_I2C_PA9_FMP_Msk          (0x1UL << SYSCFG_CFGR1_I2C_PA9_FMP_Pos)  /*!< 0x00400000 */\n#define SYSCFG_CFGR1_I2C_PA9_FMP              SYSCFG_CFGR1_I2C_PA9_FMP_Msk             /*!< Enable Fast Mode Plus on PA9  */\n#define SYSCFG_CFGR1_I2C_PA10_FMP_Pos         (23U)\n#define SYSCFG_CFGR1_I2C_PA10_FMP_Msk         (0x1UL << SYSCFG_CFGR1_I2C_PA10_FMP_Pos) /*!< 0x00800000 */\n#define SYSCFG_CFGR1_I2C_PA10_FMP             SYSCFG_CFGR1_I2C_PA10_FMP_Msk            /*!< Enable Fast Mode Plus on PA10 */\n#define SYSCFG_CFGR1_I2C_PC14_FMP_Pos         (24U)\n#define SYSCFG_CFGR1_I2C_PC14_FMP_Msk         (0x1UL << SYSCFG_CFGR1_I2C_PC14_FMP_Pos) /*!< 0x01000000 */\n#define SYSCFG_CFGR1_I2C_PC14_FMP             SYSCFG_CFGR1_I2C_PC14_FMP_Msk            /*!< Enable Fast Mode Plus on PC14 */\n\n/******************  Bit definition for SYSCFG_CFGR2 register  ****************/\n#define SYSCFG_CFGR2_CLL_Pos                  (0U)\n#define SYSCFG_CFGR2_CLL_Msk                  (0x1UL << SYSCFG_CFGR2_CLL_Pos)          /*!< 0x00000001 */\n#define SYSCFG_CFGR2_CLL                      SYSCFG_CFGR2_CLL_Msk                     /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1/16/17 */\n\n/******************  Bit definition for SYSCFG_CFGR3 register  ****************/\n#define SYSCFG_CFGR3_PINMUX0_Pos             (0U)\n#define SYSCFG_CFGR3_PINMUX0_Msk             (0x2UL << SYSCFG_CFGR3_PINMUX0_Pos)      /*!< 0x00000003 */\n#define SYSCFG_CFGR3_PINMUX0                 SYSCFG_CFGR3_PINMUX0_Msk                 /*!< Pin GPIO multiplexer 0 */\n#define SYSCFG_CFGR3_PINMUX0_0               (0x1UL << SYSCFG_CFGR3_PINMUX0_Pos)      /*!< 0x00000001 */\n#define SYSCFG_CFGR3_PINMUX0_1               (0x2UL << SYSCFG_CFGR3_PINMUX0_Pos)      /*!< 0x00000002 */\n#define SYSCFG_CFGR3_PINMUX1_Pos             (2U)\n#define SYSCFG_CFGR3_PINMUX1_Msk             (0x2UL << SYSCFG_CFGR3_PINMUX1_Pos)      /*!< 0x0000000C */\n#define SYSCFG_CFGR3_PINMUX1                 SYSCFG_CFGR3_PINMUX1_Msk                 /*!< Pin GPIO multiplexer 1 */\n#define SYSCFG_CFGR3_PINMUX1_0               (0x1UL << SYSCFG_CFGR3_PINMUX1_Pos)      /*!< 0x00000004 */\n#define SYSCFG_CFGR3_PINMUX1_1               (0x2UL << SYSCFG_CFGR3_PINMUX1_Pos)      /*!< 0x00000008 */\n#define SYSCFG_CFGR3_PINMUX2_Pos             (4U)\n#define SYSCFG_CFGR3_PINMUX2_Msk             (0x2UL << SYSCFG_CFGR3_PINMUX2_Pos)      /*!< 0x00000030 */\n#define SYSCFG_CFGR3_PINMUX2                 SYSCFG_CFGR3_PINMUX2_Msk                 /*!< Pin GPIO multiplexer 2 */\n#define SYSCFG_CFGR3_PINMUX2_0               (0x1UL << SYSCFG_CFGR3_PINMUX2_Pos)      /*!< 0x00000010 */\n#define SYSCFG_CFGR3_PINMUX2_1               (0x2UL << SYSCFG_CFGR3_PINMUX2_Pos)      /*!< 0x00000020 */\n#define SYSCFG_CFGR3_PINMUX3_Pos             (6U)\n#define SYSCFG_CFGR3_PINMUX3_Msk             (0x2UL << SYSCFG_CFGR3_PINMUX3_Pos)      /*!< 0x000000C0 */\n#define SYSCFG_CFGR3_PINMUX3                 SYSCFG_CFGR3_PINMUX3_Msk                 /*!< Pin GPIO multiplexer 3 */\n#define SYSCFG_CFGR3_PINMUX3_0               (0x1UL << SYSCFG_CFGR3_PINMUX3_Pos)      /*!< 0x00000040 */\n#define SYSCFG_CFGR3_PINMUX3_1               (0x2UL << SYSCFG_CFGR3_PINMUX3_Pos)      /*!< 0x00000080 */\n#define SYSCFG_CFGR3_PINMUX4_Pos             (8U)\n#define SYSCFG_CFGR3_PINMUX4_Msk             (0x2UL << SYSCFG_CFGR3_PINMUX4_Pos)      /*!< 0x00000300 */\n#define SYSCFG_CFGR3_PINMUX4                 SYSCFG_CFGR3_PINMUX4_Msk                 /*!< Pin GPIO multiplexer 4 */\n#define SYSCFG_CFGR3_PINMUX4_0               (0x1UL << SYSCFG_CFGR3_PINMUX4_Pos)      /*!< 0x00000100 */\n#define SYSCFG_CFGR3_PINMUX4_1               (0x2UL << SYSCFG_CFGR3_PINMUX4_Pos)      /*!< 0x00000200 */\n#define SYSCFG_CFGR3_PINMUX5_Pos             (10U)\n#define SYSCFG_CFGR3_PINMUX5_Msk             (0x2UL << SYSCFG_CFGR3_PINMUX5_Pos)      /*!< 0x00000C00 */\n#define SYSCFG_CFGR3_PINMUX5                 SYSCFG_CFGR3_PINMUX5_Msk                 /*!< Pin GPIO multiplexer 5 */\n#define SYSCFG_CFGR3_PINMUX5_0               (0x1UL << SYSCFG_CFGR3_PINMUX5_Pos)      /*!< 0x00000400 */\n#define SYSCFG_CFGR3_PINMUX5_1               (0x2UL << SYSCFG_CFGR3_PINMUX5_Pos)      /*!< 0x00000800 */\n\n/*****************  Bit definition for SYSCFG_ITLINEx ISR Wrapper register  ****************/\n#define SYSCFG_ITLINE0_SR_EWDG_Pos            (0U)\n#define SYSCFG_ITLINE0_SR_EWDG_Msk            (0x1UL << SYSCFG_ITLINE0_SR_EWDG_Pos) /*!< 0x00000001 */\n#define SYSCFG_ITLINE0_SR_EWDG                SYSCFG_ITLINE0_SR_EWDG_Msk            /*!< EWDG interrupt */\n#define SYSCFG_ITLINE2_SR_RTC_Pos             (1U)\n#define SYSCFG_ITLINE2_SR_RTC_Msk             (0x1UL << SYSCFG_ITLINE2_SR_RTC_Pos) /*!< 0x00000002 */\n#define SYSCFG_ITLINE2_SR_RTC                 SYSCFG_ITLINE2_SR_RTC_Msk            /*!< RTC interrupt */\n#define SYSCFG_ITLINE3_SR_FLASH_ITF_Pos       (1U)\n#define SYSCFG_ITLINE3_SR_FLASH_ITF_Msk       (0x1UL << SYSCFG_ITLINE3_SR_FLASH_ITF_Pos) /*!< 0x00000002 */\n#define SYSCFG_ITLINE3_SR_FLASH_ITF           SYSCFG_ITLINE3_SR_FLASH_ITF_Msk            /*!< FLASH ITF interrupt */\n#define SYSCFG_ITLINE4_SR_CLK_CTRL_Pos        (0U)\n#define SYSCFG_ITLINE4_SR_CLK_CTRL_Msk        (0x1UL << SYSCFG_ITLINE4_SR_CLK_CTRL_Pos) /*!< 0x00000001 */\n#define SYSCFG_ITLINE4_SR_CLK_CTRL            SYSCFG_ITLINE4_SR_CLK_CTRL_Msk            /*!< RCC interrupt */\n#define SYSCFG_ITLINE5_SR_EXTI0_Pos           (0U)\n#define SYSCFG_ITLINE5_SR_EXTI0_Msk           (0x1UL << SYSCFG_ITLINE5_SR_EXTI0_Pos) /*!< 0x00000001 */\n#define SYSCFG_ITLINE5_SR_EXTI0               SYSCFG_ITLINE5_SR_EXTI0_Msk            /*!< External Interrupt 0 */\n#define SYSCFG_ITLINE5_SR_EXTI1_Pos           (1U)\n#define SYSCFG_ITLINE5_SR_EXTI1_Msk           (0x1UL << SYSCFG_ITLINE5_SR_EXTI1_Pos) /*!< 0x00000002 */\n#define SYSCFG_ITLINE5_SR_EXTI1               SYSCFG_ITLINE5_SR_EXTI1_Msk            /*!< External Interrupt 1 */\n#define SYSCFG_ITLINE6_SR_EXTI2_Pos           (0U)\n#define SYSCFG_ITLINE6_SR_EXTI2_Msk           (0x1UL << SYSCFG_ITLINE6_SR_EXTI2_Pos) /*!< 0x00000001 */\n#define SYSCFG_ITLINE6_SR_EXTI2               SYSCFG_ITLINE6_SR_EXTI2_Msk            /*!< External Interrupt 2 */\n#define SYSCFG_ITLINE6_SR_EXTI3_Pos           (1U)\n#define SYSCFG_ITLINE6_SR_EXTI3_Msk           (0x1UL << SYSCFG_ITLINE6_SR_EXTI3_Pos) /*!< 0x00000002 */\n#define SYSCFG_ITLINE6_SR_EXTI3               SYSCFG_ITLINE6_SR_EXTI3_Msk            /*!< External Interrupt 3 */\n#define SYSCFG_ITLINE7_SR_EXTI4_Pos           (0U)\n#define SYSCFG_ITLINE7_SR_EXTI4_Msk           (0x1UL << SYSCFG_ITLINE7_SR_EXTI4_Pos) /*!< 0x00000001 */\n#define SYSCFG_ITLINE7_SR_EXTI4               SYSCFG_ITLINE7_SR_EXTI4_Msk            /*!< External Interrupt 4 */\n#define SYSCFG_ITLINE7_SR_EXTI5_Pos           (1U)\n#define SYSCFG_ITLINE7_SR_EXTI5_Msk           (0x1UL << SYSCFG_ITLINE7_SR_EXTI5_Pos) /*!< 0x00000002 */\n#define SYSCFG_ITLINE7_SR_EXTI5               SYSCFG_ITLINE7_SR_EXTI5_Msk            /*!< External Interrupt 5 */\n#define SYSCFG_ITLINE7_SR_EXTI6_Pos           (2U)\n#define SYSCFG_ITLINE7_SR_EXTI6_Msk           (0x1UL << SYSCFG_ITLINE7_SR_EXTI6_Pos) /*!< 0x00000004 */\n#define SYSCFG_ITLINE7_SR_EXTI6               SYSCFG_ITLINE7_SR_EXTI6_Msk            /*!< External Interrupt 6 */\n#define SYSCFG_ITLINE7_SR_EXTI7_Pos           (3U)\n#define SYSCFG_ITLINE7_SR_EXTI7_Msk           (0x1UL << SYSCFG_ITLINE7_SR_EXTI7_Pos) /*!< 0x00000008 */\n#define SYSCFG_ITLINE7_SR_EXTI7               SYSCFG_ITLINE7_SR_EXTI7_Msk            /*!< External Interrupt 7 */\n#define SYSCFG_ITLINE7_SR_EXTI8_Pos           (4U)\n#define SYSCFG_ITLINE7_SR_EXTI8_Msk           (0x1UL << SYSCFG_ITLINE7_SR_EXTI8_Pos) /*!< 0x00000010 */\n#define SYSCFG_ITLINE7_SR_EXTI8               SYSCFG_ITLINE7_SR_EXTI8_Msk            /*!< External Interrupt 8 */\n#define SYSCFG_ITLINE7_SR_EXTI9_Pos           (5U)\n#define SYSCFG_ITLINE7_SR_EXTI9_Msk           (0x1UL << SYSCFG_ITLINE7_SR_EXTI9_Pos) /*!< 0x00000020 */\n#define SYSCFG_ITLINE7_SR_EXTI9               SYSCFG_ITLINE7_SR_EXTI9_Msk            /*!< External Interrupt 9 */\n#define SYSCFG_ITLINE7_SR_EXTI10_Pos          (6U)\n#define SYSCFG_ITLINE7_SR_EXTI10_Msk          (0x1UL << SYSCFG_ITLINE7_SR_EXTI10_Pos) /*!< 0x00000040 */\n#define SYSCFG_ITLINE7_SR_EXTI10              SYSCFG_ITLINE7_SR_EXTI10_Msk            /*!< External Interrupt 10 */\n#define SYSCFG_ITLINE7_SR_EXTI11_Pos          (7U)\n#define SYSCFG_ITLINE7_SR_EXTI11_Msk          (0x1UL << SYSCFG_ITLINE7_SR_EXTI11_Pos) /*!< 0x00000080 */\n#define SYSCFG_ITLINE7_SR_EXTI11              SYSCFG_ITLINE7_SR_EXTI11_Msk            /*!< External Interrupt 11 */\n#define SYSCFG_ITLINE7_SR_EXTI12_Pos          (8U)\n#define SYSCFG_ITLINE7_SR_EXTI12_Msk          (0x1UL << SYSCFG_ITLINE7_SR_EXTI12_Pos) /*!< 0x00000100 */\n#define SYSCFG_ITLINE7_SR_EXTI12              SYSCFG_ITLINE7_SR_EXTI12_Msk            /*!< External Interrupt 12 */\n#define SYSCFG_ITLINE7_SR_EXTI13_Pos          (9U)\n#define SYSCFG_ITLINE7_SR_EXTI13_Msk          (0x1UL << SYSCFG_ITLINE7_SR_EXTI13_Pos) /*!< 0x00000200 */\n#define SYSCFG_ITLINE7_SR_EXTI13              SYSCFG_ITLINE7_SR_EXTI13_Msk            /*!< External Interrupt 13 */\n#define SYSCFG_ITLINE7_SR_EXTI14_Pos          (10U)\n#define SYSCFG_ITLINE7_SR_EXTI14_Msk          (0x1UL << SYSCFG_ITLINE7_SR_EXTI14_Pos) /*!< 0x00000400 */\n#define SYSCFG_ITLINE7_SR_EXTI14              SYSCFG_ITLINE7_SR_EXTI14_Msk            /*!< External Interrupt 14 */\n#define SYSCFG_ITLINE7_SR_EXTI15_Pos          (11U)\n#define SYSCFG_ITLINE7_SR_EXTI15_Msk          (0x1UL << SYSCFG_ITLINE7_SR_EXTI15_Pos) /*!< 0x00000800 */\n#define SYSCFG_ITLINE7_SR_EXTI15              SYSCFG_ITLINE7_SR_EXTI15_Msk            /*!< External Interrupt 15 */\n#define SYSCFG_ITLINE9_SR_DMA1_CH1_Pos        (0U)\n#define SYSCFG_ITLINE9_SR_DMA1_CH1_Msk        (0x1UL << SYSCFG_ITLINE9_SR_DMA1_CH1_Pos) /*!< 0x00000001 */\n#define SYSCFG_ITLINE9_SR_DMA1_CH1            SYSCFG_ITLINE9_SR_DMA1_CH1_Msk            /*!< DMA1 Channel 1 Interrupt */\n#define SYSCFG_ITLINE10_SR_DMA1_CH2_Pos       (0U)\n#define SYSCFG_ITLINE10_SR_DMA1_CH2_Msk       (0x1UL << SYSCFG_ITLINE10_SR_DMA1_CH2_Pos) /*!< 0x00000001 */\n#define SYSCFG_ITLINE10_SR_DMA1_CH2           SYSCFG_ITLINE10_SR_DMA1_CH2_Msk            /*!< DMA1 Channel 2 Interrupt */\n#define SYSCFG_ITLINE10_SR_DMA1_CH3_Pos       (1U)\n#define SYSCFG_ITLINE10_SR_DMA1_CH3_Msk       (0x1UL << SYSCFG_ITLINE10_SR_DMA1_CH3_Pos) /*!< 0x00000002 */\n#define SYSCFG_ITLINE10_SR_DMA1_CH3           SYSCFG_ITLINE10_SR_DMA1_CH3_Msk            /*!< DMA1 Channel 3 Interrupt */\n#define SYSCFG_ITLINE11_SR_DMAMUX1_Pos         (0U)\n#define SYSCFG_ITLINE11_SR_DMAMUX1_Msk         (0x1UL << SYSCFG_ITLINE11_SR_DMAMUX1_Pos) /*!< 0x00000001 */\n#define SYSCFG_ITLINE11_SR_DMAMUX1             SYSCFG_ITLINE11_SR_DMAMUX1_Msk            /*!< DMAMUX Interrupt */\n#define SYSCFG_ITLINE12_SR_ADC_Pos            (0U)\n#define SYSCFG_ITLINE12_SR_ADC_Msk            (0x1UL << SYSCFG_ITLINE12_SR_ADC_Pos) /*!< 0x00000001 */\n#define SYSCFG_ITLINE12_SR_ADC                SYSCFG_ITLINE12_SR_ADC_Msk            /*!< ADC Interrupt */\n#define SYSCFG_ITLINE13_SR_TIM1_CCU_Pos       (0U)\n#define SYSCFG_ITLINE13_SR_TIM1_CCU_Msk       (0x1UL << SYSCFG_ITLINE13_SR_TIM1_CCU_Pos) /*!< 0x00000001 */\n#define SYSCFG_ITLINE13_SR_TIM1_CCU           SYSCFG_ITLINE13_SR_TIM1_CCU_Msk            /*!< TIM1 CCU Interrupt */\n#define SYSCFG_ITLINE13_SR_TIM1_TRG_Pos       (1U)\n#define SYSCFG_ITLINE13_SR_TIM1_TRG_Msk       (0x1UL << SYSCFG_ITLINE13_SR_TIM1_TRG_Pos) /*!< 0x00000002 */\n#define SYSCFG_ITLINE13_SR_TIM1_TRG           SYSCFG_ITLINE13_SR_TIM1_TRG_Msk            /*!< TIM1 TRG Interrupt */\n#define SYSCFG_ITLINE13_SR_TIM1_UPD_Pos       (2U)\n#define SYSCFG_ITLINE13_SR_TIM1_UPD_Msk       (0x1UL << SYSCFG_ITLINE13_SR_TIM1_UPD_Pos) /*!< 0x00000004 */\n#define SYSCFG_ITLINE13_SR_TIM1_UPD           SYSCFG_ITLINE13_SR_TIM1_UPD_Msk            /*!< TIM1 UPD Interrupt */\n#define SYSCFG_ITLINE13_SR_TIM1_BRK_Pos       (3U)\n#define SYSCFG_ITLINE13_SR_TIM1_BRK_Msk       (0x1UL << SYSCFG_ITLINE13_SR_TIM1_BRK_Pos) /*!< 0x00000008 */\n#define SYSCFG_ITLINE13_SR_TIM1_BRK           SYSCFG_ITLINE13_SR_TIM1_BRK_Msk            /*!< TIM1 BRK Interrupt */\n#define SYSCFG_ITLINE14_SR_TIM1_CC_Pos        (0U)\n#define SYSCFG_ITLINE14_SR_TIM1_CC_Msk        (0x1UL << SYSCFG_ITLINE14_SR_TIM1_CC_Pos) /*!< 0x00000001 */\n#define SYSCFG_ITLINE14_SR_TIM1_CC            SYSCFG_ITLINE14_SR_TIM1_CC_Msk            /*!< TIM1 CC Interrupt */\n#define SYSCFG_ITLINE16_SR_TIM3_GLB_Pos       (0U)\n#define SYSCFG_ITLINE16_SR_TIM3_GLB_Msk       (0x1UL << SYSCFG_ITLINE16_SR_TIM3_GLB_Pos) /*!< 0x00000001 */\n#define SYSCFG_ITLINE16_SR_TIM3_GLB           SYSCFG_ITLINE16_SR_TIM3_GLB_Msk            /*!< TIM3 GLB Interrupt */\n#define SYSCFG_ITLINE19_SR_TIM14_GLB_Pos      (0U)\n#define SYSCFG_ITLINE19_SR_TIM14_GLB_Msk      (0x1UL << SYSCFG_ITLINE19_SR_TIM14_GLB_Pos) /*!< 0x00000001 */\n#define SYSCFG_ITLINE19_SR_TIM14_GLB          SYSCFG_ITLINE19_SR_TIM14_GLB_Msk            /*!< TIM14 GLB Interrupt */\n#define SYSCFG_ITLINE21_SR_TIM16_GLB_Pos      (0U)\n#define SYSCFG_ITLINE21_SR_TIM16_GLB_Msk      (0x1UL << SYSCFG_ITLINE21_SR_TIM16_GLB_Pos) /*!< 0x00000001 */\n#define SYSCFG_ITLINE21_SR_TIM16_GLB          SYSCFG_ITLINE21_SR_TIM16_GLB_Msk            /*!< TIM16 GLB Interrupt */\n#define SYSCFG_ITLINE22_SR_TIM17_GLB_Pos      (0U)\n#define SYSCFG_ITLINE22_SR_TIM17_GLB_Msk      (0x1UL << SYSCFG_ITLINE22_SR_TIM17_GLB_Pos) /*!< 0x00000001 */\n#define SYSCFG_ITLINE22_SR_TIM17_GLB          SYSCFG_ITLINE22_SR_TIM17_GLB_Msk            /*!< TIM17 GLB Interrupt */\n#define SYSCFG_ITLINE23_SR_I2C1_GLB_Pos       (0U)\n#define SYSCFG_ITLINE23_SR_I2C1_GLB_Msk       (0x1UL << SYSCFG_ITLINE23_SR_I2C1_GLB_Pos) /*!< 0x00000001 */\n#define SYSCFG_ITLINE23_SR_I2C1_GLB           SYSCFG_ITLINE23_SR_I2C1_GLB_Msk            /*!< I2C1 GLB Interrupt */\n#define SYSCFG_ITLINE25_SR_SPI1_Pos           (0U)\n#define SYSCFG_ITLINE25_SR_SPI1_Msk           (0x1UL << SYSCFG_ITLINE25_SR_SPI1_Pos) /*!< 0x00000001 */\n#define SYSCFG_ITLINE25_SR_SPI1               SYSCFG_ITLINE25_SR_SPI1_Msk            /*!< SPI1 Interrupt */\n#define SYSCFG_ITLINE27_SR_USART1_GLB_Pos     (0U)\n#define SYSCFG_ITLINE27_SR_USART1_GLB_Msk     (0x1UL << SYSCFG_ITLINE27_SR_USART1_GLB_Pos) /*!< 0x00000001 */\n#define SYSCFG_ITLINE27_SR_USART1_GLB         SYSCFG_ITLINE27_SR_USART1_GLB_Msk            /*!< USART1 GLB Interrupt */\n#define SYSCFG_ITLINE28_SR_USART2_GLB_Pos     (0U)\n#define SYSCFG_ITLINE28_SR_USART2_GLB_Msk     (0x1UL << SYSCFG_ITLINE28_SR_USART2_GLB_Pos) /*!< 0x00000001 */\n#define SYSCFG_ITLINE28_SR_USART2_GLB         SYSCFG_ITLINE28_SR_USART2_GLB_Msk            /*!< USART2 GLB Interrupt */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                    TIM                                     */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for TIM_CR1 register  ********************/\n#define TIM_CR1_CEN_Pos           (0U)\n#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                   /*!< 0x00000001 */\n#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */\n#define TIM_CR1_UDIS_Pos          (1U)\n#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                  /*!< 0x00000002 */\n#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */\n#define TIM_CR1_URS_Pos           (2U)\n#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                   /*!< 0x00000004 */\n#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */\n#define TIM_CR1_OPM_Pos           (3U)\n#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                   /*!< 0x00000008 */\n#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */\n#define TIM_CR1_DIR_Pos           (4U)\n#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                   /*!< 0x00000010 */\n#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */\n\n#define TIM_CR1_CMS_Pos           (5U)\n#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000060 */\n#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */\n#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000020 */\n#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000040 */\n\n#define TIM_CR1_ARPE_Pos          (7U)\n#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                  /*!< 0x00000080 */\n#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */\n\n#define TIM_CR1_CKD_Pos           (8U)\n#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000300 */\n#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */\n#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000100 */\n#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000200 */\n\n#define TIM_CR1_UIFREMAP_Pos      (11U)\n#define TIM_CR1_UIFREMAP_Msk      (0x1UL << TIM_CR1_UIFREMAP_Pos)              /*!< 0x00000800 */\n#define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<Update interrupt flag remap */\n\n/*******************  Bit definition for TIM_CR2 register  ********************/\n#define TIM_CR2_CCPC_Pos          (0U)\n#define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                  /*!< 0x00000001 */\n#define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */\n#define TIM_CR2_CCUS_Pos          (2U)\n#define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                  /*!< 0x00000004 */\n#define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */\n#define TIM_CR2_CCDS_Pos          (3U)\n#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                  /*!< 0x00000008 */\n#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */\n\n#define TIM_CR2_MMS_Pos           (4U)\n#define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000070 */\n#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */\n#define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000010 */\n#define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000020 */\n#define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000040 */\n\n#define TIM_CR2_TI1S_Pos          (7U)\n#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                  /*!< 0x00000080 */\n#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */\n#define TIM_CR2_OIS1_Pos          (8U)\n#define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                  /*!< 0x00000100 */\n#define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */\n#define TIM_CR2_OIS1N_Pos         (9U)\n#define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                 /*!< 0x00000200 */\n#define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */\n#define TIM_CR2_OIS2_Pos          (10U)\n#define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                  /*!< 0x00000400 */\n#define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */\n#define TIM_CR2_OIS2N_Pos         (11U)\n#define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                 /*!< 0x00000800 */\n#define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */\n#define TIM_CR2_OIS3_Pos          (12U)\n#define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                  /*!< 0x00001000 */\n#define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */\n#define TIM_CR2_OIS3N_Pos         (13U)\n#define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                 /*!< 0x00002000 */\n#define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */\n#define TIM_CR2_OIS4_Pos          (14U)\n#define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                  /*!< 0x00004000 */\n#define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */\n#define TIM_CR2_OIS5_Pos          (16U)\n#define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */\n#define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 5 (OC5 output) */\n#define TIM_CR2_OIS6_Pos          (18U)\n#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00040000 */\n#define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 6 (OC6 output) */\n\n#define TIM_CR2_MMS2_Pos          (20U)\n#define TIM_CR2_MMS2_Msk          (0xFUL << TIM_CR2_MMS2_Pos)                  /*!< 0x00F00000 */\n#define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */\n#define TIM_CR2_MMS2_0            (0x1UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00100000 */\n#define TIM_CR2_MMS2_1            (0x2UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00200000 */\n#define TIM_CR2_MMS2_2            (0x4UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00400000 */\n#define TIM_CR2_MMS2_3            (0x8UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00800000 */\n\n/*******************  Bit definition for TIM_SMCR register  *******************/\n#define TIM_SMCR_SMS_Pos          (0U)\n#define TIM_SMCR_SMS_Msk          (0x10007UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010007 */\n#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */\n#define TIM_SMCR_SMS_0            (0x00001UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000001 */\n#define TIM_SMCR_SMS_1            (0x00002UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000002 */\n#define TIM_SMCR_SMS_2            (0x00004UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000004 */\n#define TIM_SMCR_SMS_3            (0x10000UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010000 */\n\n#define TIM_SMCR_OCCS_Pos         (3U)\n#define TIM_SMCR_OCCS_Msk         (0x1UL << TIM_SMCR_OCCS_Pos)                 /*!< 0x00000008 */\n#define TIM_SMCR_OCCS             TIM_SMCR_OCCS_Msk                            /*!< OCREF clear selection */\n\n#define TIM_SMCR_TS_Pos           (4U)\n#define TIM_SMCR_TS_Msk           (0x30007UL << TIM_SMCR_TS_Pos)               /*!< 0x00300070 */\n#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */\n#define TIM_SMCR_TS_0             (0x00001UL << TIM_SMCR_TS_Pos)               /*!< 0x00000010 */\n#define TIM_SMCR_TS_1             (0x00002UL << TIM_SMCR_TS_Pos)               /*!< 0x00000020 */\n#define TIM_SMCR_TS_2             (0x00004UL << TIM_SMCR_TS_Pos)               /*!< 0x00000040 */\n#define TIM_SMCR_TS_3             (0x10000UL << TIM_SMCR_TS_Pos)               /*!< 0x00100000 */\n#define TIM_SMCR_TS_4             (0x20000UL << TIM_SMCR_TS_Pos)               /*!< 0x00200000 */\n\n#define TIM_SMCR_MSM_Pos          (7U)\n#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                  /*!< 0x00000080 */\n#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */\n\n#define TIM_SMCR_ETF_Pos          (8U)\n#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000F00 */\n#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */\n#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000100 */\n#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000200 */\n#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000400 */\n#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000800 */\n\n#define TIM_SMCR_ETPS_Pos         (12U)\n#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00003000 */\n#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */\n#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00001000 */\n#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00002000 */\n\n#define TIM_SMCR_ECE_Pos          (14U)\n#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                  /*!< 0x00004000 */\n#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */\n#define TIM_SMCR_ETP_Pos          (15U)\n#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                  /*!< 0x00008000 */\n#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */\n\n/*******************  Bit definition for TIM_DIER register  *******************/\n#define TIM_DIER_UIE_Pos          (0U)\n#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                  /*!< 0x00000001 */\n#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */\n#define TIM_DIER_CC1IE_Pos        (1U)\n#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                /*!< 0x00000002 */\n#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */\n#define TIM_DIER_CC2IE_Pos        (2U)\n#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                /*!< 0x00000004 */\n#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */\n#define TIM_DIER_CC3IE_Pos        (3U)\n#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                /*!< 0x00000008 */\n#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */\n#define TIM_DIER_CC4IE_Pos        (4U)\n#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                /*!< 0x00000010 */\n#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */\n#define TIM_DIER_COMIE_Pos        (5U)\n#define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                /*!< 0x00000020 */\n#define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */\n#define TIM_DIER_TIE_Pos          (6U)\n#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                  /*!< 0x00000040 */\n#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */\n#define TIM_DIER_BIE_Pos          (7U)\n#define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                  /*!< 0x00000080 */\n#define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */\n#define TIM_DIER_UDE_Pos          (8U)\n#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                  /*!< 0x00000100 */\n#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */\n#define TIM_DIER_CC1DE_Pos        (9U)\n#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                /*!< 0x00000200 */\n#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */\n#define TIM_DIER_CC2DE_Pos        (10U)\n#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                /*!< 0x00000400 */\n#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */\n#define TIM_DIER_CC3DE_Pos        (11U)\n#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                /*!< 0x00000800 */\n#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */\n#define TIM_DIER_CC4DE_Pos        (12U)\n#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                /*!< 0x00001000 */\n#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */\n#define TIM_DIER_COMDE_Pos        (13U)\n#define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                /*!< 0x00002000 */\n#define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */\n#define TIM_DIER_TDE_Pos          (14U)\n#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                  /*!< 0x00004000 */\n#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */\n\n/********************  Bit definition for TIM_SR register  ********************/\n#define TIM_SR_UIF_Pos            (0U)\n#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                    /*!< 0x00000001 */\n#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */\n#define TIM_SR_CC1IF_Pos          (1U)\n#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                  /*!< 0x00000002 */\n#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */\n#define TIM_SR_CC2IF_Pos          (2U)\n#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                  /*!< 0x00000004 */\n#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */\n#define TIM_SR_CC3IF_Pos          (3U)\n#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                  /*!< 0x00000008 */\n#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */\n#define TIM_SR_CC4IF_Pos          (4U)\n#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                  /*!< 0x00000010 */\n#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */\n#define TIM_SR_COMIF_Pos          (5U)\n#define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                  /*!< 0x00000020 */\n#define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */\n#define TIM_SR_TIF_Pos            (6U)\n#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                    /*!< 0x00000040 */\n#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */\n#define TIM_SR_BIF_Pos            (7U)\n#define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                    /*!< 0x00000080 */\n#define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */\n#define TIM_SR_B2IF_Pos           (8U)\n#define TIM_SR_B2IF_Msk           (0x1UL << TIM_SR_B2IF_Pos)                   /*!< 0x00000100 */\n#define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break 2 interrupt Flag */\n#define TIM_SR_CC1OF_Pos          (9U)\n#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                  /*!< 0x00000200 */\n#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */\n#define TIM_SR_CC2OF_Pos          (10U)\n#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                  /*!< 0x00000400 */\n#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */\n#define TIM_SR_CC3OF_Pos          (11U)\n#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                  /*!< 0x00000800 */\n#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */\n#define TIM_SR_CC4OF_Pos          (12U)\n#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                  /*!< 0x00001000 */\n#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */\n#define TIM_SR_SBIF_Pos           (13U)\n#define TIM_SR_SBIF_Msk           (0x1UL << TIM_SR_SBIF_Pos)                   /*!< 0x00002000 */\n#define TIM_SR_SBIF               TIM_SR_SBIF_Msk                              /*!<System Break interrupt Flag */\n#define TIM_SR_CC5IF_Pos          (16U)\n#define TIM_SR_CC5IF_Msk          (0x1UL << TIM_SR_CC5IF_Pos)                  /*!< 0x00010000 */\n#define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */\n#define TIM_SR_CC6IF_Pos          (17U)\n#define TIM_SR_CC6IF_Msk          (0x1UL << TIM_SR_CC6IF_Pos)                  /*!< 0x00020000 */\n#define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */\n\n\n/*******************  Bit definition for TIM_EGR register  ********************/\n#define TIM_EGR_UG_Pos            (0U)\n#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                    /*!< 0x00000001 */\n#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */\n#define TIM_EGR_CC1G_Pos          (1U)\n#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                  /*!< 0x00000002 */\n#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */\n#define TIM_EGR_CC2G_Pos          (2U)\n#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                  /*!< 0x00000004 */\n#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */\n#define TIM_EGR_CC3G_Pos          (3U)\n#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                  /*!< 0x00000008 */\n#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */\n#define TIM_EGR_CC4G_Pos          (4U)\n#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                  /*!< 0x00000010 */\n#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */\n#define TIM_EGR_COMG_Pos          (5U)\n#define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                  /*!< 0x00000020 */\n#define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */\n#define TIM_EGR_TG_Pos            (6U)\n#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                    /*!< 0x00000040 */\n#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */\n#define TIM_EGR_BG_Pos            (7U)\n#define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                    /*!< 0x00000080 */\n#define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */\n#define TIM_EGR_B2G_Pos           (8U)\n#define TIM_EGR_B2G_Msk           (0x1UL << TIM_EGR_B2G_Pos)                   /*!< 0x00000100 */\n#define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break 2 Generation */\n\n\n/******************  Bit definition for TIM_CCMR1 register  *******************/\n#define TIM_CCMR1_CC1S_Pos        (0U)\n#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000003 */\n#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */\n#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000001 */\n#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000002 */\n\n#define TIM_CCMR1_OC1FE_Pos       (2U)\n#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)               /*!< 0x00000004 */\n#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */\n#define TIM_CCMR1_OC1PE_Pos       (3U)\n#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)               /*!< 0x00000008 */\n#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */\n\n#define TIM_CCMR1_OC1M_Pos        (4U)\n#define TIM_CCMR1_OC1M_Msk        (0x1007UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010070 */\n#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */\n#define TIM_CCMR1_OC1M_0          (0x0001UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000010 */\n#define TIM_CCMR1_OC1M_1          (0x0002UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000020 */\n#define TIM_CCMR1_OC1M_2          (0x0004UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000040 */\n#define TIM_CCMR1_OC1M_3          (0x1000UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010000 */\n\n#define TIM_CCMR1_OC1CE_Pos       (7U)\n#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)               /*!< 0x00000080 */\n#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1 Clear Enable */\n\n#define TIM_CCMR1_CC2S_Pos        (8U)\n#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000300 */\n#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */\n#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000100 */\n#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000200 */\n\n#define TIM_CCMR1_OC2FE_Pos       (10U)\n#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)               /*!< 0x00000400 */\n#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */\n#define TIM_CCMR1_OC2PE_Pos       (11U)\n#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)               /*!< 0x00000800 */\n#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */\n\n#define TIM_CCMR1_OC2M_Pos        (12U)\n#define TIM_CCMR1_OC2M_Msk        (0x1007UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01007000 */\n#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */\n#define TIM_CCMR1_OC2M_0          (0x0001UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00001000 */\n#define TIM_CCMR1_OC2M_1          (0x0002UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00002000 */\n#define TIM_CCMR1_OC2M_2          (0x0004UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00004000 */\n#define TIM_CCMR1_OC2M_3          (0x1000UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01000000 */\n\n#define TIM_CCMR1_OC2CE_Pos       (15U)\n#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)               /*!< 0x00008000 */\n#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */\n\n/*----------------------------------------------------------------------------*/\n#define TIM_CCMR1_IC1PSC_Pos      (2U)\n#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x0000000C */\n#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */\n#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x00000004 */\n#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x00000008 */\n\n#define TIM_CCMR1_IC1F_Pos        (4U)\n#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                /*!< 0x000000F0 */\n#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */\n#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000010 */\n#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000020 */\n#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000040 */\n#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000080 */\n\n#define TIM_CCMR1_IC2PSC_Pos      (10U)\n#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000C00 */\n#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */\n#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000400 */\n#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000800 */\n\n#define TIM_CCMR1_IC2F_Pos        (12U)\n#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                /*!< 0x0000F000 */\n#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */\n#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00001000 */\n#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00002000 */\n#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00004000 */\n#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00008000 */\n\n/******************  Bit definition for TIM_CCMR2 register  *******************/\n#define TIM_CCMR2_CC3S_Pos        (0U)\n#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000003 */\n#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */\n#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000001 */\n#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000002 */\n\n#define TIM_CCMR2_OC3FE_Pos       (2U)\n#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)               /*!< 0x00000004 */\n#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */\n#define TIM_CCMR2_OC3PE_Pos       (3U)\n#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)               /*!< 0x00000008 */\n#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */\n\n#define TIM_CCMR2_OC3M_Pos        (4U)\n#define TIM_CCMR2_OC3M_Msk        (0x1007UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00010070 */\n#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */\n#define TIM_CCMR2_OC3M_0          (0x0001UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000010 */\n#define TIM_CCMR2_OC3M_1          (0x0002UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000020 */\n#define TIM_CCMR2_OC3M_2          (0x0004UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000040 */\n#define TIM_CCMR2_OC3M_3          (0x1000UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00010000 */\n\n#define TIM_CCMR2_OC3CE_Pos       (7U)\n#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)               /*!< 0x00000080 */\n#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */\n\n#define TIM_CCMR2_CC4S_Pos        (8U)\n#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000300 */\n#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */\n#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000100 */\n#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000200 */\n\n#define TIM_CCMR2_OC4FE_Pos       (10U)\n#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)               /*!< 0x00000400 */\n#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */\n#define TIM_CCMR2_OC4PE_Pos       (11U)\n#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)               /*!< 0x00000800 */\n#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */\n\n#define TIM_CCMR2_OC4M_Pos        (12U)\n#define TIM_CCMR2_OC4M_Msk        (0x1007UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x01007000 */\n#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */\n#define TIM_CCMR2_OC4M_0          (0x0001UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00001000 */\n#define TIM_CCMR2_OC4M_1          (0x0002UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00002000 */\n#define TIM_CCMR2_OC4M_2          (0x0004UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00004000 */\n#define TIM_CCMR2_OC4M_3          (0x1000UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x01000000 */\n\n#define TIM_CCMR2_OC4CE_Pos       (15U)\n#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */\n#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */\n\n/*----------------------------------------------------------------------------*/\n#define TIM_CCMR2_IC3PSC_Pos      (2U)\n#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x0000000C */\n#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */\n#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x00000004 */\n#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x00000008 */\n\n#define TIM_CCMR2_IC3F_Pos        (4U)\n#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                /*!< 0x000000F0 */\n#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */\n#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000010 */\n#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000020 */\n#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000040 */\n#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000080 */\n\n#define TIM_CCMR2_IC4PSC_Pos      (10U)\n#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000C00 */\n#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */\n#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000400 */\n#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000800 */\n\n#define TIM_CCMR2_IC4F_Pos        (12U)\n#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                /*!< 0x0000F000 */\n#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */\n#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00001000 */\n#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00002000 */\n#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00004000 */\n#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00008000 */\n\n/******************  Bit definition for TIM_CCMR3 register  *******************/\n#define TIM_CCMR3_OC5FE_Pos       (2U)\n#define TIM_CCMR3_OC5FE_Msk       (0x1UL << TIM_CCMR3_OC5FE_Pos)               /*!< 0x00000004 */\n#define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */\n#define TIM_CCMR3_OC5PE_Pos       (3U)\n#define TIM_CCMR3_OC5PE_Msk       (0x1UL << TIM_CCMR3_OC5PE_Pos)               /*!< 0x00000008 */\n#define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */\n\n#define TIM_CCMR3_OC5M_Pos        (4U)\n#define TIM_CCMR3_OC5M_Msk        (0x1007UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00010070 */\n#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[3:0] bits (Output Compare 5 Mode) */\n#define TIM_CCMR3_OC5M_0          (0x0001UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000010 */\n#define TIM_CCMR3_OC5M_1          (0x0002UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000020 */\n#define TIM_CCMR3_OC5M_2          (0x0004UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000040 */\n#define TIM_CCMR3_OC5M_3          (0x1000UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00010000 */\n\n#define TIM_CCMR3_OC5CE_Pos       (7U)\n#define TIM_CCMR3_OC5CE_Msk       (0x1UL << TIM_CCMR3_OC5CE_Pos)               /*!< 0x00000080 */\n#define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */\n\n#define TIM_CCMR3_OC6FE_Pos       (10U)\n#define TIM_CCMR3_OC6FE_Msk       (0x1UL << TIM_CCMR3_OC6FE_Pos)               /*!< 0x00000400 */\n#define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 6 Fast enable */\n#define TIM_CCMR3_OC6PE_Pos       (11U)\n#define TIM_CCMR3_OC6PE_Msk       (0x1UL << TIM_CCMR3_OC6PE_Pos)               /*!< 0x00000800 */\n#define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 6 Preload enable */\n\n#define TIM_CCMR3_OC6M_Pos        (12U)\n#define TIM_CCMR3_OC6M_Msk        (0x1007UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x01007000 */\n#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC6M[3:0] bits (Output Compare 6 Mode) */\n#define TIM_CCMR3_OC6M_0          (0x0001UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00001000 */\n#define TIM_CCMR3_OC6M_1          (0x0002UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00002000 */\n#define TIM_CCMR3_OC6M_2          (0x0004UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00004000 */\n#define TIM_CCMR3_OC6M_3          (0x1000UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x01000000 */\n\n#define TIM_CCMR3_OC6CE_Pos       (15U)\n#define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */\n#define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 6 Clear Enable */\n\n/*******************  Bit definition for TIM_CCER register  *******************/\n#define TIM_CCER_CC1E_Pos         (0U)\n#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                 /*!< 0x00000001 */\n#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */\n#define TIM_CCER_CC1P_Pos         (1U)\n#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                 /*!< 0x00000002 */\n#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */\n#define TIM_CCER_CC1NE_Pos        (2U)\n#define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                /*!< 0x00000004 */\n#define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */\n#define TIM_CCER_CC1NP_Pos        (3U)\n#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                /*!< 0x00000008 */\n#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */\n#define TIM_CCER_CC2E_Pos         (4U)\n#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                 /*!< 0x00000010 */\n#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */\n#define TIM_CCER_CC2P_Pos         (5U)\n#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                 /*!< 0x00000020 */\n#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */\n#define TIM_CCER_CC2NE_Pos        (6U)\n#define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                /*!< 0x00000040 */\n#define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */\n#define TIM_CCER_CC2NP_Pos        (7U)\n#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                /*!< 0x00000080 */\n#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */\n#define TIM_CCER_CC3E_Pos         (8U)\n#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                 /*!< 0x00000100 */\n#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */\n#define TIM_CCER_CC3P_Pos         (9U)\n#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                 /*!< 0x00000200 */\n#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */\n#define TIM_CCER_CC3NE_Pos        (10U)\n#define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                /*!< 0x00000400 */\n#define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */\n#define TIM_CCER_CC3NP_Pos        (11U)\n#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                /*!< 0x00000800 */\n#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */\n#define TIM_CCER_CC4E_Pos         (12U)\n#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                 /*!< 0x00001000 */\n#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */\n#define TIM_CCER_CC4P_Pos         (13U)\n#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                 /*!< 0x00002000 */\n#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */\n#define TIM_CCER_CC4NP_Pos        (15U)\n#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                /*!< 0x00008000 */\n#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */\n#define TIM_CCER_CC5E_Pos         (16U)\n#define TIM_CCER_CC5E_Msk         (0x1UL << TIM_CCER_CC5E_Pos)                 /*!< 0x00010000 */\n#define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */\n#define TIM_CCER_CC5P_Pos         (17U)\n#define TIM_CCER_CC5P_Msk         (0x1UL << TIM_CCER_CC5P_Pos)                 /*!< 0x00020000 */\n#define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */\n#define TIM_CCER_CC6E_Pos         (20U)\n#define TIM_CCER_CC6E_Msk         (0x1UL << TIM_CCER_CC6E_Pos)                 /*!< 0x00100000 */\n#define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */\n#define TIM_CCER_CC6P_Pos         (21U)\n#define TIM_CCER_CC6P_Msk         (0x1UL << TIM_CCER_CC6P_Pos)                 /*!< 0x00200000 */\n#define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */\n\n/*******************  Bit definition for TIM_CNT register  ********************/\n#define TIM_CNT_CNT_Pos           (0U)\n#define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)            /*!< 0xFFFFFFFF */\n#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */\n#define TIM_CNT_UIFCPY_Pos        (31U)\n#define TIM_CNT_UIFCPY_Msk        (0x1UL << TIM_CNT_UIFCPY_Pos)                /*!< 0x80000000 */\n#define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy (if UIFREMAP=1) */\n\n/*******************  Bit definition for TIM_PSC register  ********************/\n#define TIM_PSC_PSC_Pos           (0U)\n#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                /*!< 0x0000FFFF */\n#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */\n\n/*******************  Bit definition for TIM_ARR register  ********************/\n#define TIM_ARR_ARR_Pos           (0U)\n#define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)            /*!< 0xFFFFFFFF */\n#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<Actual auto-reload Value */\n\n/*******************  Bit definition for TIM_RCR register  ********************/\n#define TIM_RCR_REP_Pos           (0U)\n#define TIM_RCR_REP_Msk           (0xFFFFUL << TIM_RCR_REP_Pos)                /*!< 0x0000FFFF */\n#define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */\n\n/*******************  Bit definition for TIM_CCR1 register  *******************/\n#define TIM_CCR1_CCR1_Pos         (0U)\n#define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)              /*!< 0x0000FFFF */\n#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */\n\n/*******************  Bit definition for TIM_CCR2 register  *******************/\n#define TIM_CCR2_CCR2_Pos         (0U)\n#define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)              /*!< 0x0000FFFF */\n#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */\n\n/*******************  Bit definition for TIM_CCR3 register  *******************/\n#define TIM_CCR3_CCR3_Pos         (0U)\n#define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)              /*!< 0x0000FFFF */\n#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */\n\n/*******************  Bit definition for TIM_CCR4 register  *******************/\n#define TIM_CCR4_CCR4_Pos         (0U)\n#define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)              /*!< 0x0000FFFF */\n#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */\n\n/*******************  Bit definition for TIM_CCR5 register  *******************/\n#define TIM_CCR5_CCR5_Pos         (0U)\n#define TIM_CCR5_CCR5_Msk         (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)          /*!< 0xFFFFFFFF */\n#define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */\n#define TIM_CCR5_GC5C1_Pos        (29U)\n#define TIM_CCR5_GC5C1_Msk        (0x1UL << TIM_CCR5_GC5C1_Pos)                /*!< 0x20000000 */\n#define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */\n#define TIM_CCR5_GC5C2_Pos        (30U)\n#define TIM_CCR5_GC5C2_Msk        (0x1UL << TIM_CCR5_GC5C2_Pos)                /*!< 0x40000000 */\n#define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */\n#define TIM_CCR5_GC5C3_Pos        (31U)\n#define TIM_CCR5_GC5C3_Msk        (0x1UL << TIM_CCR5_GC5C3_Pos)                /*!< 0x80000000 */\n#define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */\n\n/*******************  Bit definition for TIM_CCR6 register  *******************/\n#define TIM_CCR6_CCR6_Pos         (0U)\n#define TIM_CCR6_CCR6_Msk         (0xFFFFUL << TIM_CCR6_CCR6_Pos)              /*!< 0x0000FFFF */\n#define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */\n\n/*******************  Bit definition for TIM_BDTR register  *******************/\n#define TIM_BDTR_DTG_Pos          (0U)\n#define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                 /*!< 0x000000FF */\n#define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */\n#define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000001 */\n#define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000002 */\n#define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000004 */\n#define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000008 */\n#define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000010 */\n#define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000020 */\n#define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000040 */\n#define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000080 */\n\n#define TIM_BDTR_LOCK_Pos         (8U)\n#define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000300 */\n#define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */\n#define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000100 */\n#define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000200 */\n\n#define TIM_BDTR_OSSI_Pos         (10U)\n#define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                 /*!< 0x00000400 */\n#define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */\n#define TIM_BDTR_OSSR_Pos         (11U)\n#define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                 /*!< 0x00000800 */\n#define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */\n#define TIM_BDTR_BKE_Pos          (12U)\n#define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                  /*!< 0x00001000 */\n#define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break 1 */\n#define TIM_BDTR_BKP_Pos          (13U)\n#define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                  /*!< 0x00002000 */\n#define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break 1 */\n#define TIM_BDTR_AOE_Pos          (14U)\n#define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                  /*!< 0x00004000 */\n#define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */\n#define TIM_BDTR_MOE_Pos          (15U)\n#define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                  /*!< 0x00008000 */\n#define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */\n\n#define TIM_BDTR_BKF_Pos          (16U)\n#define TIM_BDTR_BKF_Msk          (0xFUL << TIM_BDTR_BKF_Pos)                  /*!< 0x000F0000 */\n#define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break 1 */\n#define TIM_BDTR_BK2F_Pos         (20U)\n#define TIM_BDTR_BK2F_Msk         (0xFUL << TIM_BDTR_BK2F_Pos)                 /*!< 0x00F00000 */\n#define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break 2 */\n\n#define TIM_BDTR_BK2E_Pos         (24U)\n#define TIM_BDTR_BK2E_Msk         (0x1UL << TIM_BDTR_BK2E_Pos)                 /*!< 0x01000000 */\n#define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break 2 */\n#define TIM_BDTR_BK2P_Pos         (25U)\n#define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                 /*!< 0x02000000 */\n#define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break 2 */\n\n#define TIM_BDTR_BKDSRM_Pos       (26U)\n#define TIM_BDTR_BKDSRM_Msk       (0x1UL << TIM_BDTR_BKDSRM_Pos)               /*!< 0x04000000 */\n#define TIM_BDTR_BKDSRM           TIM_BDTR_BKDSRM_Msk                          /*!<Break disarming/re-arming */\n#define TIM_BDTR_BK2DSRM_Pos      (27U)\n#define TIM_BDTR_BK2DSRM_Msk      (0x1UL << TIM_BDTR_BK2DSRM_Pos)              /*!< 0x08000000 */\n#define TIM_BDTR_BK2DSRM          TIM_BDTR_BK2DSRM_Msk                         /*!<Break2 disarming/re-arming */\n\n#define TIM_BDTR_BKBID_Pos        (28U)\n#define TIM_BDTR_BKBID_Msk        (0x1UL << TIM_BDTR_BKBID_Pos)                /*!< 0x10000000 */\n#define TIM_BDTR_BKBID            TIM_BDTR_BKBID_Msk                           /*!<Break BIDirectional */\n#define TIM_BDTR_BK2BID_Pos       (29U)\n#define TIM_BDTR_BK2BID_Msk       (0x1UL << TIM_BDTR_BK2BID_Pos)               /*!< 0x20000000 */\n#define TIM_BDTR_BK2BID           TIM_BDTR_BK2BID_Msk                          /*!<Break2 BIDirectional */\n\n/*******************  Bit definition for TIM_DCR register  ********************/\n#define TIM_DCR_DBA_Pos           (0U)\n#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                  /*!< 0x0000001F */\n#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */\n#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000001 */\n#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000002 */\n#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000004 */\n#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000008 */\n#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000010 */\n\n#define TIM_DCR_DBL_Pos           (8U)\n#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                  /*!< 0x00001F00 */\n#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */\n#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000100 */\n#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000200 */\n#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000400 */\n#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000800 */\n#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                  /*!< 0x00001000 */\n\n/*******************  Bit definition for TIM_DMAR register  *******************/\n#define TIM_DMAR_DMAB_Pos         (0U)\n#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)              /*!< 0x0000FFFF */\n#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */\n\n/*******************  Bit definition for TIM1_OR1 register  *******************/\n#define TIM1_OR1_OCREF_CLR_Pos     (0U)\n#define TIM1_OR1_OCREF_CLR_Msk     (0x1UL << TIM1_OR1_OCREF_CLR_Pos)           /*!< 0x00000001 */\n#define TIM1_OR1_OCREF_CLR         TIM1_OR1_OCREF_CLR_Msk                      /*!<OCREF clear input selection */\n\n/*******************  Bit definition for TIM1_AF1 register  *******************/\n#define TIM1_AF1_BKINE_Pos        (0U)\n#define TIM1_AF1_BKINE_Msk        (0x1UL << TIM1_AF1_BKINE_Pos)                /*!< 0x00000001 */\n#define TIM1_AF1_BKINE            TIM1_AF1_BKINE_Msk                           /*!<BRK BKIN input enable */\n#define TIM1_AF1_BKCMP1E_Pos      (1U)\n#define TIM1_AF1_BKCMP1E_Msk      (0x1UL << TIM1_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */\n#define TIM1_AF1_BKCMP1E          TIM1_AF1_BKCMP1E_Msk                         /*!<BRK COMP1 enable */\n#define TIM1_AF1_BKCMP2E_Pos      (2U)\n#define TIM1_AF1_BKCMP2E_Msk      (0x1UL << TIM1_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */\n#define TIM1_AF1_BKCMP2E          TIM1_AF1_BKCMP2E_Msk                         /*!<BRK COMP2 enable */\n#define TIM1_AF1_BKINP_Pos        (9U)\n#define TIM1_AF1_BKINP_Msk        (0x1UL << TIM1_AF1_BKINP_Pos)                /*!< 0x00000200 */\n#define TIM1_AF1_BKINP            TIM1_AF1_BKINP_Msk                           /*!<BRK BKIN input polarity */\n#define TIM1_AF1_BKCMP1P_Pos      (10U)\n#define TIM1_AF1_BKCMP1P_Msk      (0x1UL << TIM1_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */\n#define TIM1_AF1_BKCMP1P          TIM1_AF1_BKCMP1P_Msk                         /*!<BRK COMP1 input polarity */\n#define TIM1_AF1_BKCMP2P_Pos      (11U)\n#define TIM1_AF1_BKCMP2P_Msk      (0x1UL << TIM1_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */\n#define TIM1_AF1_BKCMP2P          TIM1_AF1_BKCMP2P_Msk                         /*!<BRK COMP2 input polarity */\n\n#define TIM1_AF1_ETRSEL_Pos       (14U)\n#define TIM1_AF1_ETRSEL_Msk       (0xFUL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */\n#define TIM1_AF1_ETRSEL           TIM1_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM1 ETR source selection) */\n#define TIM1_AF1_ETRSEL_0         (0x1UL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x00004000 */\n#define TIM1_AF1_ETRSEL_1         (0x2UL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x00008000 */\n#define TIM1_AF1_ETRSEL_2         (0x4UL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x00010000 */\n#define TIM1_AF1_ETRSEL_3         (0x8UL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x00020000 */\n\n/*******************  Bit definition for TIM1_AF2 register  *******************/\n#define TIM1_AF2_BK2INE_Pos       (0U)\n#define TIM1_AF2_BK2INE_Msk       (0x1UL << TIM1_AF2_BK2INE_Pos)               /*!< 0x00000001 */\n#define TIM1_AF2_BK2INE           TIM1_AF2_BK2INE_Msk                          /*!<BRK2 BKIN2 input enable */\n#define TIM1_AF2_BK2CMP1E_Pos     (1U)\n#define TIM1_AF2_BK2CMP1E_Msk     (0x1UL << TIM1_AF2_BK2CMP1E_Pos)             /*!< 0x00000002 */\n#define TIM1_AF2_BK2CMP1E         TIM1_AF2_BK2CMP1E_Msk                        /*!<BRK2 COMP1 enable */\n#define TIM1_AF2_BK2CMP2E_Pos     (2U)\n#define TIM1_AF2_BK2CMP2E_Msk     (0x1UL << TIM1_AF2_BK2CMP2E_Pos)             /*!< 0x00000004 */\n#define TIM1_AF2_BK2CMP2E         TIM1_AF2_BK2CMP2E_Msk                        /*!<BRK2 COMP2 enable */\n#define TIM1_AF2_BK2INP_Pos       (9U)\n#define TIM1_AF2_BK2INP_Msk       (0x1UL << TIM1_AF2_BK2INP_Pos)               /*!< 0x00000200 */\n#define TIM1_AF2_BK2INP           TIM1_AF2_BK2INP_Msk                          /*!<BRK2 BKIN2 input polarity */\n#define TIM1_AF2_BK2CMP1P_Pos     (10U)\n#define TIM1_AF2_BK2CMP1P_Msk     (0x1UL << TIM1_AF2_BK2CMP1P_Pos)             /*!< 0x00000400 */\n#define TIM1_AF2_BK2CMP1P         TIM1_AF2_BK2CMP1P_Msk                        /*!<BRK2 COMP1 input polarity */\n#define TIM1_AF2_BK2CMP2P_Pos     (11U)\n#define TIM1_AF2_BK2CMP2P_Msk     (0x1UL << TIM1_AF2_BK2CMP2P_Pos)             /*!< 0x00000800 */\n#define TIM1_AF2_BK2CMP2P         TIM1_AF2_BK2CMP2P_Msk                        /*!<BRK2 COMP2 input polarity */\n\n\n/*******************  Bit definition for TIM3_OR1 register  *******************/\n#define TIM3_OR1_OCREF_CLR_Pos     (0U)\n#define TIM3_OR1_OCREF_CLR_Msk     (0x1UL << TIM3_OR1_OCREF_CLR_Pos)           /*!< 0x00000001 */\n#define TIM3_OR1_OCREF_CLR         TIM3_OR1_OCREF_CLR_Msk                      /*!<OCREF clear input selection */\n\n/*******************  Bit definition for TIM3_AF1 register  *******************/\n#define TIM3_AF1_ETRSEL_Pos       (14U)\n#define TIM3_AF1_ETRSEL_Msk       (0xFUL << TIM3_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */\n#define TIM3_AF1_ETRSEL           TIM3_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM3 ETR source selection) */\n#define TIM3_AF1_ETRSEL_0         (0x1UL << TIM3_AF1_ETRSEL_Pos)               /*!< 0x00004000 */\n#define TIM3_AF1_ETRSEL_1         (0x2UL << TIM3_AF1_ETRSEL_Pos)               /*!< 0x00008000 */\n#define TIM3_AF1_ETRSEL_2         (0x4UL << TIM3_AF1_ETRSEL_Pos)               /*!< 0x00010000 */\n#define TIM3_AF1_ETRSEL_3         (0x8UL << TIM3_AF1_ETRSEL_Pos)               /*!< 0x00020000 */\n\n/*******************  Bit definition for TIM14_AF1 register  *******************/\n#define TIM14_AF1_ETRSEL_Pos      (14U)\n#define TIM14_AF1_ETRSEL_Msk      (0xFUL << TIM14_AF1_ETRSEL_Pos)              /*!< 0x0003C000 */\n#define TIM14_AF1_ETRSEL          TIM14_AF1_ETRSEL_Msk                         /*!<ETRSEL[3:0] bits (TIM3 ETR source selection) */\n#define TIM14_AF1_ETRSEL_0        (0x1UL << TIM14_AF1_ETRSEL_Pos)              /*!< 0x00004000 */\n#define TIM14_AF1_ETRSEL_1        (0x2UL << TIM14_AF1_ETRSEL_Pos)              /*!< 0x00008000 */\n#define TIM14_AF1_ETRSEL_2        (0x4UL << TIM14_AF1_ETRSEL_Pos)              /*!< 0x00010000 */\n#define TIM14_AF1_ETRSEL_3        (0x8UL << TIM14_AF1_ETRSEL_Pos)              /*!< 0x00020000 */\n\n/*******************  Bit definition for TIM16_AF1 register  ******************/\n#define TIM16_AF1_BKINE_Pos      (0U)\n#define TIM16_AF1_BKINE_Msk      (0x1UL << TIM16_AF1_BKINE_Pos)                /*!< 0x00000001 */\n#define TIM16_AF1_BKINE          TIM16_AF1_BKINE_Msk                           /*!<BRK BKIN input enable */\n#define TIM16_AF1_BKCMP1E_Pos    (1U)\n#define TIM16_AF1_BKCMP1E_Msk    (0x1UL << TIM16_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */\n#define TIM16_AF1_BKCMP1E        TIM16_AF1_BKCMP1E_Msk                         /*!<BRK COMP1 enable */\n#define TIM16_AF1_BKCMP2E_Pos    (2U)\n#define TIM16_AF1_BKCMP2E_Msk    (0x1UL << TIM16_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */\n#define TIM16_AF1_BKCMP2E        TIM16_AF1_BKCMP2E_Msk                         /*!<BRK COMP2 enable */\n#define TIM16_AF1_BKINP_Pos      (9U)\n#define TIM16_AF1_BKINP_Msk      (0x1UL << TIM16_AF1_BKINP_Pos)                /*!< 0x00000200 */\n#define TIM16_AF1_BKINP          TIM16_AF1_BKINP_Msk                           /*!<BRK BKIN input polarity */\n#define TIM16_AF1_BKCMP1P_Pos    (10U)\n#define TIM16_AF1_BKCMP1P_Msk    (0x1UL << TIM16_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */\n#define TIM16_AF1_BKCMP1P        TIM16_AF1_BKCMP1P_Msk                         /*!<BRK COMP1 input polarity */\n#define TIM16_AF1_BKCMP2P_Pos    (11U)\n#define TIM16_AF1_BKCMP2P_Msk    (0x1UL << TIM16_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */\n#define TIM16_AF1_BKCMP2P        TIM16_AF1_BKCMP2P_Msk                         /*!<BRK COMP2 input polarity */\n\n/*******************  Bit definition for TIM17_AF1 register  ******************/\n#define TIM17_AF1_BKINE_Pos      (0U)\n#define TIM17_AF1_BKINE_Msk      (0x1UL << TIM17_AF1_BKINE_Pos)                /*!< 0x00000001 */\n#define TIM17_AF1_BKINE          TIM17_AF1_BKINE_Msk                           /*!<BRK BKIN input enable */\n#define TIM17_AF1_BKCMP1E_Pos    (1U)\n#define TIM17_AF1_BKCMP1E_Msk    (0x1UL << TIM17_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */\n#define TIM17_AF1_BKCMP1E        TIM17_AF1_BKCMP1E_Msk                         /*!<BRK COMP1 enable */\n#define TIM17_AF1_BKCMP2E_Pos    (2U)\n#define TIM17_AF1_BKCMP2E_Msk    (0x1UL << TIM17_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */\n#define TIM17_AF1_BKCMP2E        TIM17_AF1_BKCMP2E_Msk                         /*!<BRK COMP2 enable */\n#define TIM17_AF1_BKINP_Pos      (9U)\n#define TIM17_AF1_BKINP_Msk      (0x1UL << TIM17_AF1_BKINP_Pos)                /*!< 0x00000200 */\n#define TIM17_AF1_BKINP          TIM17_AF1_BKINP_Msk                           /*!<BRK BKIN input polarity */\n#define TIM17_AF1_BKCMP1P_Pos    (10U)\n#define TIM17_AF1_BKCMP1P_Msk    (0x1UL << TIM17_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */\n#define TIM17_AF1_BKCMP1P        TIM17_AF1_BKCMP1P_Msk                         /*!<BRK COMP1 input polarity */\n#define TIM17_AF1_BKCMP2P_Pos    (11U)\n#define TIM17_AF1_BKCMP2P_Msk    (0x1UL << TIM17_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */\n#define TIM17_AF1_BKCMP2P        TIM17_AF1_BKCMP2P_Msk                         /*!<BRK COMP2 input polarity */\n\n/*******************  Bit definition for TIM_TISEL register  *********************/\n#define TIM_TISEL_TI1SEL_Pos      (0U)\n#define TIM_TISEL_TI1SEL_Msk      (0xFUL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x0000000F */\n#define TIM_TISEL_TI1SEL          TIM_TISEL_TI1SEL_Msk                         /*!<TI1SEL[3:0] bits (TIM1 TI1 SEL)*/\n#define TIM_TISEL_TI1SEL_0        (0x1UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000001 */\n#define TIM_TISEL_TI1SEL_1        (0x2UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000002 */\n#define TIM_TISEL_TI1SEL_2        (0x4UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000004 */\n#define TIM_TISEL_TI1SEL_3        (0x8UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000008 */\n\n#define TIM_TISEL_TI2SEL_Pos      (8U)\n#define TIM_TISEL_TI2SEL_Msk      (0xFUL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000F00 */\n#define TIM_TISEL_TI2SEL          TIM_TISEL_TI2SEL_Msk                         /*!<TI2SEL[3:0] bits (TIM1 TI2 SEL)*/\n#define TIM_TISEL_TI2SEL_0        (0x1UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000100 */\n#define TIM_TISEL_TI2SEL_1        (0x2UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000200 */\n#define TIM_TISEL_TI2SEL_2        (0x4UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000400 */\n#define TIM_TISEL_TI2SEL_3        (0x8UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000800 */\n\n#define TIM_TISEL_TI3SEL_Pos      (16U)\n#define TIM_TISEL_TI3SEL_Msk      (0xFUL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x000F0000 */\n#define TIM_TISEL_TI3SEL          TIM_TISEL_TI3SEL_Msk                         /*!<TI3SEL[3:0] bits (TIM1 TI3 SEL)*/\n#define TIM_TISEL_TI3SEL_0        (0x1UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00010000 */\n#define TIM_TISEL_TI3SEL_1        (0x2UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00020000 */\n#define TIM_TISEL_TI3SEL_2        (0x4UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00040000 */\n#define TIM_TISEL_TI3SEL_3        (0x8UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00080000 */\n\n#define TIM_TISEL_TI4SEL_Pos      (24U)\n#define TIM_TISEL_TI4SEL_Msk      (0xFUL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x0F000000 */\n#define TIM_TISEL_TI4SEL          TIM_TISEL_TI4SEL_Msk                         /*!<TI4SEL[3:0] bits (TIM1 TI4 SEL)*/\n#define TIM_TISEL_TI4SEL_0        (0x1UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x01000000 */\n#define TIM_TISEL_TI4SEL_1        (0x2UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x02000000 */\n#define TIM_TISEL_TI4SEL_2        (0x4UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x04000000 */\n#define TIM_TISEL_TI4SEL_3        (0x8UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x08000000 */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bit definition for USART_CR1 register  *******************/\n#define USART_CR1_UE_Pos             (0U)\n#define USART_CR1_UE_Msk             (0x1UL << USART_CR1_UE_Pos)               /*!< 0x00000001 */\n#define USART_CR1_UE                 USART_CR1_UE_Msk                          /*!< USART Enable */\n#define USART_CR1_UESM_Pos           (1U)\n#define USART_CR1_UESM_Msk           (0x1UL << USART_CR1_UESM_Pos)             /*!< 0x00000002 */\n#define USART_CR1_UESM               USART_CR1_UESM_Msk                        /*!< USART Enable in STOP Mode */\n#define USART_CR1_RE_Pos             (2U)\n#define USART_CR1_RE_Msk             (0x1UL << USART_CR1_RE_Pos)               /*!< 0x00000004 */\n#define USART_CR1_RE                 USART_CR1_RE_Msk                          /*!< Receiver Enable */\n#define USART_CR1_TE_Pos             (3U)\n#define USART_CR1_TE_Msk             (0x1UL << USART_CR1_TE_Pos)               /*!< 0x00000008 */\n#define USART_CR1_TE                 USART_CR1_TE_Msk                          /*!< Transmitter Enable */\n#define USART_CR1_IDLEIE_Pos         (4U)\n#define USART_CR1_IDLEIE_Msk         (0x1UL << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */\n#define USART_CR1_IDLEIE             USART_CR1_IDLEIE_Msk                      /*!< IDLE Interrupt Enable */\n#define USART_CR1_RXNEIE_RXFNEIE_Pos   (5U)\n#define USART_CR1_RXNEIE_RXFNEIE_Msk   (0x1UL << USART_CR1_RXNEIE_RXFNEIE_Pos) /*!< 0x00000020 */\n#define USART_CR1_RXNEIE_RXFNEIE       USART_CR1_RXNEIE_RXFNEIE_Msk            /*!< RXNE/RXFIFO not empty Interrupt Enable */\n#define USART_CR1_TCIE_Pos           (6U)\n#define USART_CR1_TCIE_Msk           (0x1UL << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */\n#define USART_CR1_TCIE               USART_CR1_TCIE_Msk                        /*!< Transmission Complete Interrupt Enable */\n#define USART_CR1_TXEIE_TXFNFIE_Pos  (7U)\n#define USART_CR1_TXEIE_TXFNFIE_Msk   (0x1UL << USART_CR1_TXEIE_TXFNFIE_Pos)   /*!< 0x00000080 */\n#define USART_CR1_TXEIE_TXFNFIE       USART_CR1_TXEIE_TXFNFIE_Msk              /*!< TXE/TXFIFO not full Interrupt Enable */\n#define USART_CR1_PEIE_Pos           (8U)\n#define USART_CR1_PEIE_Msk           (0x1UL << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */\n#define USART_CR1_PEIE               USART_CR1_PEIE_Msk                        /*!< PE Interrupt Enable */\n#define USART_CR1_PS_Pos             (9U)\n#define USART_CR1_PS_Msk             (0x1UL << USART_CR1_PS_Pos)               /*!< 0x00000200 */\n#define USART_CR1_PS                 USART_CR1_PS_Msk                          /*!< Parity Selection */\n#define USART_CR1_PCE_Pos            (10U)\n#define USART_CR1_PCE_Msk            (0x1UL << USART_CR1_PCE_Pos)              /*!< 0x00000400 */\n#define USART_CR1_PCE                USART_CR1_PCE_Msk                         /*!< Parity Control Enable */\n#define USART_CR1_WAKE_Pos           (11U)\n#define USART_CR1_WAKE_Msk           (0x1UL << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */\n#define USART_CR1_WAKE               USART_CR1_WAKE_Msk                        /*!< Receiver Wakeup method */\n#define USART_CR1_M_Pos              (12U)\n#define USART_CR1_M_Msk              (0x10001UL << USART_CR1_M_Pos)            /*!< 0x10001000 */\n#define USART_CR1_M                  USART_CR1_M_Msk                           /*!< Word length */\n#define USART_CR1_M0_Pos             (12U)\n#define USART_CR1_M0_Msk             (0x1UL << USART_CR1_M0_Pos)               /*!< 0x00001000 */\n#define USART_CR1_M0                 USART_CR1_M0_Msk                          /*!< Word length - Bit 0 */\n#define USART_CR1_MME_Pos            (13U)\n#define USART_CR1_MME_Msk            (0x1UL << USART_CR1_MME_Pos)              /*!< 0x00002000 */\n#define USART_CR1_MME                USART_CR1_MME_Msk                         /*!< Mute Mode Enable */\n#define USART_CR1_CMIE_Pos           (14U)\n#define USART_CR1_CMIE_Msk           (0x1UL << USART_CR1_CMIE_Pos)             /*!< 0x00004000 */\n#define USART_CR1_CMIE               USART_CR1_CMIE_Msk                        /*!< Character match interrupt enable */\n#define USART_CR1_OVER8_Pos          (15U)\n#define USART_CR1_OVER8_Msk          (0x1UL << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */\n#define USART_CR1_OVER8              USART_CR1_OVER8_Msk                       /*!< Oversampling by 8-bit or 16-bit mode */\n#define USART_CR1_DEDT_Pos           (16U)\n#define USART_CR1_DEDT_Msk           (0x1FUL << USART_CR1_DEDT_Pos)            /*!< 0x001F0000 */\n#define USART_CR1_DEDT               USART_CR1_DEDT_Msk                        /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */\n#define USART_CR1_DEDT_0             (0x01UL << USART_CR1_DEDT_Pos)            /*!< 0x00010000 */\n#define USART_CR1_DEDT_1             (0x02UL << USART_CR1_DEDT_Pos)            /*!< 0x00020000 */\n#define USART_CR1_DEDT_2             (0x04UL << USART_CR1_DEDT_Pos)            /*!< 0x00040000 */\n#define USART_CR1_DEDT_3             (0x08UL << USART_CR1_DEDT_Pos)            /*!< 0x00080000 */\n#define USART_CR1_DEDT_4             (0x10UL << USART_CR1_DEDT_Pos)            /*!< 0x00100000 */\n#define USART_CR1_DEAT_Pos           (21U)\n#define USART_CR1_DEAT_Msk           (0x1FUL << USART_CR1_DEAT_Pos)            /*!< 0x03E00000 */\n#define USART_CR1_DEAT               USART_CR1_DEAT_Msk                        /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */\n#define USART_CR1_DEAT_0             (0x01UL << USART_CR1_DEAT_Pos)            /*!< 0x00200000 */\n#define USART_CR1_DEAT_1             (0x02UL << USART_CR1_DEAT_Pos)            /*!< 0x00400000 */\n#define USART_CR1_DEAT_2             (0x04UL << USART_CR1_DEAT_Pos)            /*!< 0x00800000 */\n#define USART_CR1_DEAT_3             (0x08UL << USART_CR1_DEAT_Pos)            /*!< 0x01000000 */\n#define USART_CR1_DEAT_4             (0x10UL << USART_CR1_DEAT_Pos)            /*!< 0x02000000 */\n#define USART_CR1_RTOIE_Pos          (26U)\n#define USART_CR1_RTOIE_Msk          (0x1UL << USART_CR1_RTOIE_Pos)            /*!< 0x04000000 */\n#define USART_CR1_RTOIE              USART_CR1_RTOIE_Msk                       /*!< Receive Time Out interrupt enable */\n#define USART_CR1_EOBIE_Pos          (27U)\n#define USART_CR1_EOBIE_Msk          (0x1UL << USART_CR1_EOBIE_Pos)            /*!< 0x08000000 */\n#define USART_CR1_EOBIE              USART_CR1_EOBIE_Msk                       /*!< End of Block interrupt enable */\n#define USART_CR1_M1_Pos             (28U)\n#define USART_CR1_M1_Msk             (0x1UL << USART_CR1_M1_Pos)               /*!< 0x10000000 */\n#define USART_CR1_M1                 USART_CR1_M1_Msk                          /*!< Word length - Bit 1 */\n#define USART_CR1_FIFOEN_Pos         (29U)\n#define USART_CR1_FIFOEN_Msk         (0x1UL << USART_CR1_FIFOEN_Pos)           /*!< 0x20000000 */\n#define USART_CR1_FIFOEN             USART_CR1_FIFOEN_Msk                      /*!< FIFO mode enable */\n#define USART_CR1_TXFEIE_Pos         (30U)\n#define USART_CR1_TXFEIE_Msk         (0x1UL << USART_CR1_TXFEIE_Pos)           /*!< 0x40000000 */\n#define USART_CR1_TXFEIE             USART_CR1_TXFEIE_Msk                      /*!< TXFIFO empty interrupt enable */\n#define USART_CR1_RXFFIE_Pos         (31U)\n#define USART_CR1_RXFFIE_Msk         (0x1UL << USART_CR1_RXFFIE_Pos)           /*!< 0x80000000 */\n#define USART_CR1_RXFFIE             USART_CR1_RXFFIE_Msk                      /*!< RXFIFO Full interrupt enable */\n\n/******************  Bit definition for USART_CR2 register  *******************/\n#define USART_CR2_SLVEN_Pos          (0U)\n#define USART_CR2_SLVEN_Msk          (0x1UL << USART_CR2_SLVEN_Pos)            /*!< 0x00000001 */\n#define USART_CR2_SLVEN              USART_CR2_SLVEN_Msk                       /*!< Synchronous Slave mode enable */\n#define USART_CR2_DIS_NSS_Pos        (3U)\n#define USART_CR2_DIS_NSS_Msk        (0x1UL << USART_CR2_DIS_NSS_Pos)          /*!< 0x00000008 */\n#define USART_CR2_DIS_NSS            USART_CR2_DIS_NSS_Msk                     /*!< NSS input pin disable for SPI slave selection */\n#define USART_CR2_ADDM7_Pos          (4U)\n#define USART_CR2_ADDM7_Msk          (0x1UL << USART_CR2_ADDM7_Pos)            /*!< 0x00000010 */\n#define USART_CR2_ADDM7              USART_CR2_ADDM7_Msk                       /*!< 7-bit or 4-bit Address Detection */\n#define USART_CR2_LBDL_Pos           (5U)\n#define USART_CR2_LBDL_Msk           (0x1UL << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */\n#define USART_CR2_LBDL               USART_CR2_LBDL_Msk                        /*!< LIN Break Detection Length */\n#define USART_CR2_LBDIE_Pos          (6U)\n#define USART_CR2_LBDIE_Msk          (0x1UL << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */\n#define USART_CR2_LBDIE              USART_CR2_LBDIE_Msk                       /*!< LIN Break Detection Interrupt Enable */\n#define USART_CR2_LBCL_Pos           (8U)\n#define USART_CR2_LBCL_Msk           (0x1UL << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */\n#define USART_CR2_LBCL               USART_CR2_LBCL_Msk                        /*!< Last Bit Clock pulse */\n#define USART_CR2_CPHA_Pos           (9U)\n#define USART_CR2_CPHA_Msk           (0x1UL << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */\n#define USART_CR2_CPHA               USART_CR2_CPHA_Msk                        /*!< Clock Phase */\n#define USART_CR2_CPOL_Pos           (10U)\n#define USART_CR2_CPOL_Msk           (0x1UL << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */\n#define USART_CR2_CPOL               USART_CR2_CPOL_Msk                        /*!< Clock Polarity */\n#define USART_CR2_CLKEN_Pos          (11U)\n#define USART_CR2_CLKEN_Msk          (0x1UL << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */\n#define USART_CR2_CLKEN              USART_CR2_CLKEN_Msk                       /*!< Clock Enable */\n#define USART_CR2_STOP_Pos           (12U)\n#define USART_CR2_STOP_Msk           (0x3UL << USART_CR2_STOP_Pos)             /*!< 0x00003000 */\n#define USART_CR2_STOP               USART_CR2_STOP_Msk                        /*!< STOP[1:0] bits (STOP bits) */\n#define USART_CR2_STOP_0             (0x1UL << USART_CR2_STOP_Pos)             /*!< 0x00001000 */\n#define USART_CR2_STOP_1             (0x2UL << USART_CR2_STOP_Pos)             /*!< 0x00002000 */\n#define USART_CR2_LINEN_Pos          (14U)\n#define USART_CR2_LINEN_Msk          (0x1UL << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */\n#define USART_CR2_LINEN              USART_CR2_LINEN_Msk                       /*!< LIN mode enable */\n#define USART_CR2_SWAP_Pos           (15U)\n#define USART_CR2_SWAP_Msk           (0x1UL << USART_CR2_SWAP_Pos)             /*!< 0x00008000 */\n#define USART_CR2_SWAP               USART_CR2_SWAP_Msk                        /*!< SWAP TX/RX pins */\n#define USART_CR2_RXINV_Pos          (16U)\n#define USART_CR2_RXINV_Msk          (0x1UL << USART_CR2_RXINV_Pos)            /*!< 0x00010000 */\n#define USART_CR2_RXINV              USART_CR2_RXINV_Msk                       /*!< RX pin active level inversion */\n#define USART_CR2_TXINV_Pos          (17U)\n#define USART_CR2_TXINV_Msk          (0x1UL << USART_CR2_TXINV_Pos)            /*!< 0x00020000 */\n#define USART_CR2_TXINV              USART_CR2_TXINV_Msk                       /*!< TX pin active level inversion */\n#define USART_CR2_DATAINV_Pos        (18U)\n#define USART_CR2_DATAINV_Msk        (0x1UL << USART_CR2_DATAINV_Pos)          /*!< 0x00040000 */\n#define USART_CR2_DATAINV            USART_CR2_DATAINV_Msk                     /*!< Binary data inversion */\n#define USART_CR2_MSBFIRST_Pos       (19U)\n#define USART_CR2_MSBFIRST_Msk       (0x1UL << USART_CR2_MSBFIRST_Pos)         /*!< 0x00080000 */\n#define USART_CR2_MSBFIRST           USART_CR2_MSBFIRST_Msk                    /*!< Most Significant Bit First */\n#define USART_CR2_ABREN_Pos          (20U)\n#define USART_CR2_ABREN_Msk          (0x1UL << USART_CR2_ABREN_Pos)            /*!< 0x00100000 */\n#define USART_CR2_ABREN              USART_CR2_ABREN_Msk                       /*!< Auto Baud-Rate Enable*/\n#define USART_CR2_ABRMODE_Pos        (21U)\n#define USART_CR2_ABRMODE_Msk        (0x3UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00600000 */\n#define USART_CR2_ABRMODE            USART_CR2_ABRMODE_Msk                     /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */\n#define USART_CR2_ABRMODE_0          (0x1UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00200000 */\n#define USART_CR2_ABRMODE_1          (0x2UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00400000 */\n#define USART_CR2_RTOEN_Pos          (23U)\n#define USART_CR2_RTOEN_Msk          (0x1UL << USART_CR2_RTOEN_Pos)            /*!< 0x00800000 */\n#define USART_CR2_RTOEN              USART_CR2_RTOEN_Msk                       /*!< Receiver Time-Out enable */\n#define USART_CR2_ADD_Pos            (24U)\n#define USART_CR2_ADD_Msk            (0xFFUL << USART_CR2_ADD_Pos)             /*!< 0xFF000000 */\n#define USART_CR2_ADD                USART_CR2_ADD_Msk                         /*!< Address of the USART node */\n\n/******************  Bit definition for USART_CR3 register  *******************/\n#define USART_CR3_EIE_Pos            (0U)\n#define USART_CR3_EIE_Msk            (0x1UL << USART_CR3_EIE_Pos)              /*!< 0x00000001 */\n#define USART_CR3_EIE                USART_CR3_EIE_Msk                         /*!< Error Interrupt Enable */\n#define USART_CR3_IREN_Pos           (1U)\n#define USART_CR3_IREN_Msk           (0x1UL << USART_CR3_IREN_Pos)             /*!< 0x00000002 */\n#define USART_CR3_IREN               USART_CR3_IREN_Msk                        /*!< IrDA mode Enable */\n#define USART_CR3_IRLP_Pos           (2U)\n#define USART_CR3_IRLP_Msk           (0x1UL << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */\n#define USART_CR3_IRLP               USART_CR3_IRLP_Msk                        /*!< IrDA Low-Power */\n#define USART_CR3_HDSEL_Pos          (3U)\n#define USART_CR3_HDSEL_Msk          (0x1UL << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */\n#define USART_CR3_HDSEL              USART_CR3_HDSEL_Msk                       /*!< Half-Duplex Selection */\n#define USART_CR3_NACK_Pos           (4U)\n#define USART_CR3_NACK_Msk           (0x1UL << USART_CR3_NACK_Pos)             /*!< 0x00000010 */\n#define USART_CR3_NACK               USART_CR3_NACK_Msk                        /*!< SmartCard NACK enable */\n#define USART_CR3_SCEN_Pos           (5U)\n#define USART_CR3_SCEN_Msk           (0x1UL << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */\n#define USART_CR3_SCEN               USART_CR3_SCEN_Msk                        /*!< SmartCard mode enable */\n#define USART_CR3_DMAR_Pos           (6U)\n#define USART_CR3_DMAR_Msk           (0x1UL << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */\n#define USART_CR3_DMAR               USART_CR3_DMAR_Msk                        /*!< DMA Enable Receiver */\n#define USART_CR3_DMAT_Pos           (7U)\n#define USART_CR3_DMAT_Msk           (0x1UL << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */\n#define USART_CR3_DMAT               USART_CR3_DMAT_Msk                        /*!< DMA Enable Transmitter */\n#define USART_CR3_RTSE_Pos           (8U)\n#define USART_CR3_RTSE_Msk           (0x1UL << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */\n#define USART_CR3_RTSE               USART_CR3_RTSE_Msk                        /*!< RTS Enable */\n#define USART_CR3_CTSE_Pos           (9U)\n#define USART_CR3_CTSE_Msk           (0x1UL << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */\n#define USART_CR3_CTSE               USART_CR3_CTSE_Msk                        /*!< CTS Enable */\n#define USART_CR3_CTSIE_Pos          (10U)\n#define USART_CR3_CTSIE_Msk          (0x1UL << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */\n#define USART_CR3_CTSIE              USART_CR3_CTSIE_Msk                       /*!< CTS Interrupt Enable */\n#define USART_CR3_ONEBIT_Pos         (11U)\n#define USART_CR3_ONEBIT_Msk         (0x1UL << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */\n#define USART_CR3_ONEBIT             USART_CR3_ONEBIT_Msk                      /*!< One sample bit method enable */\n#define USART_CR3_OVRDIS_Pos         (12U)\n#define USART_CR3_OVRDIS_Msk         (0x1UL << USART_CR3_OVRDIS_Pos)           /*!< 0x00001000 */\n#define USART_CR3_OVRDIS             USART_CR3_OVRDIS_Msk                      /*!< Overrun Disable */\n#define USART_CR3_DDRE_Pos           (13U)\n#define USART_CR3_DDRE_Msk           (0x1UL << USART_CR3_DDRE_Pos)             /*!< 0x00002000 */\n#define USART_CR3_DDRE               USART_CR3_DDRE_Msk                        /*!< DMA Disable on Reception Error */\n#define USART_CR3_DEM_Pos            (14U)\n#define USART_CR3_DEM_Msk            (0x1UL << USART_CR3_DEM_Pos)              /*!< 0x00004000 */\n#define USART_CR3_DEM                USART_CR3_DEM_Msk                         /*!< Driver Enable Mode */\n#define USART_CR3_DEP_Pos            (15U)\n#define USART_CR3_DEP_Msk            (0x1UL << USART_CR3_DEP_Pos)              /*!< 0x00008000 */\n#define USART_CR3_DEP                USART_CR3_DEP_Msk                         /*!< Driver Enable Polarity Selection */\n#define USART_CR3_SCARCNT_Pos        (17U)\n#define USART_CR3_SCARCNT_Msk        (0x7UL << USART_CR3_SCARCNT_Pos)          /*!< 0x000E0000 */\n#define USART_CR3_SCARCNT            USART_CR3_SCARCNT_Msk                     /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */\n#define USART_CR3_SCARCNT_0          (0x1UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00020000 */\n#define USART_CR3_SCARCNT_1          (0x2UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00040000 */\n#define USART_CR3_SCARCNT_2          (0x4UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00080000 */\n#define USART_CR3_WUS_Pos            (20U)\n#define USART_CR3_WUS_Msk            (0x3UL << USART_CR3_WUS_Pos)              /*!< 0x00300000 */\n#define USART_CR3_WUS                USART_CR3_WUS_Msk                         /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */\n#define USART_CR3_WUS_0              (0x1UL << USART_CR3_WUS_Pos)              /*!< 0x00100000 */\n#define USART_CR3_WUS_1              (0x2UL << USART_CR3_WUS_Pos)              /*!< 0x00200000 */\n#define USART_CR3_WUFIE_Pos          (22U)\n#define USART_CR3_WUFIE_Msk          (0x1UL << USART_CR3_WUFIE_Pos)            /*!< 0x00400000 */\n#define USART_CR3_WUFIE              USART_CR3_WUFIE_Msk                       /*!< Wake Up Interrupt Enable */\n#define USART_CR3_TXFTIE_Pos         (23U)\n#define USART_CR3_TXFTIE_Msk         (0x1UL << USART_CR3_TXFTIE_Pos)           /*!< 0x00800000 */\n#define USART_CR3_TXFTIE             USART_CR3_TXFTIE_Msk                      /*!< TXFIFO threshold interrupt enable */\n#define USART_CR3_TCBGTIE_Pos        (24U)\n#define USART_CR3_TCBGTIE_Msk        (0x1UL << USART_CR3_TCBGTIE_Pos)          /*!< 0x01000000 */\n#define USART_CR3_TCBGTIE            USART_CR3_TCBGTIE_Msk                     /*!< Transmission Complete Before Guard Time Interrupt Enable */\n#define USART_CR3_RXFTCFG_Pos        (25U)\n#define USART_CR3_RXFTCFG_Msk        (0x7UL << USART_CR3_RXFTCFG_Pos)          /*!< 0x0E000000 */\n#define USART_CR3_RXFTCFG            USART_CR3_RXFTCFG_Msk                     /*!< RXFIFO FIFO threshold configuration */\n#define USART_CR3_RXFTCFG_0          (0x1UL << USART_CR3_RXFTCFG_Pos)          /*!< 0x02000000 */\n#define USART_CR3_RXFTCFG_1          (0x2UL << USART_CR3_RXFTCFG_Pos)          /*!< 0x04000000 */\n#define USART_CR3_RXFTCFG_2          (0x4UL << USART_CR3_RXFTCFG_Pos)          /*!< 0x08000000 */\n#define USART_CR3_RXFTIE_Pos         (28U)\n#define USART_CR3_RXFTIE_Msk         (0x1UL << USART_CR3_RXFTIE_Pos)           /*!< 0x10000000 */\n#define USART_CR3_RXFTIE             USART_CR3_RXFTIE_Msk                      /*!< RXFIFO threshold interrupt enable */\n#define USART_CR3_TXFTCFG_Pos        (29U)\n#define USART_CR3_TXFTCFG_Msk        (0x7UL << USART_CR3_TXFTCFG_Pos)          /*!< 0xE0000000 */\n#define USART_CR3_TXFTCFG            USART_CR3_TXFTCFG_Msk                     /*!< TXFIFO threshold configuration */\n#define USART_CR3_TXFTCFG_0          (0x1UL << USART_CR3_TXFTCFG_Pos)          /*!< 0x20000000 */\n#define USART_CR3_TXFTCFG_1          (0x2UL << USART_CR3_TXFTCFG_Pos)          /*!< 0x40000000 */\n#define USART_CR3_TXFTCFG_2          (0x4UL << USART_CR3_TXFTCFG_Pos)          /*!< 0x80000000 */\n\n/******************  Bit definition for USART_BRR register  *******************/\n#define USART_BRR_BRR                ((uint16_t)0xFFFF)                        /*!< USART  Baud rate register [15:0] */\n\n/******************  Bit definition for USART_GTPR register  ******************/\n#define USART_GTPR_PSC_Pos           (0U)\n#define USART_GTPR_PSC_Msk           (0xFFUL << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */\n#define USART_GTPR_PSC               USART_GTPR_PSC_Msk                        /*!< PSC[7:0] bits (Prescaler value) */\n#define USART_GTPR_GT_Pos            (8U)\n#define USART_GTPR_GT_Msk            (0xFFUL << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */\n#define USART_GTPR_GT                USART_GTPR_GT_Msk                         /*!< GT[7:0] bits (Guard time value) */\n\n/*******************  Bit definition for USART_RTOR register  *****************/\n#define USART_RTOR_RTO_Pos           (0U)\n#define USART_RTOR_RTO_Msk           (0xFFFFFFUL << USART_RTOR_RTO_Pos)        /*!< 0x00FFFFFF */\n#define USART_RTOR_RTO               USART_RTOR_RTO_Msk                        /*!< Receiver Time Out Value */\n#define USART_RTOR_BLEN_Pos          (24U)\n#define USART_RTOR_BLEN_Msk          (0xFFUL << USART_RTOR_BLEN_Pos)           /*!< 0xFF000000 */\n#define USART_RTOR_BLEN              USART_RTOR_BLEN_Msk                       /*!< Block Length */\n\n/*******************  Bit definition for USART_RQR register  ******************/\n#define USART_RQR_ABRRQ        ((uint16_t)0x0001)                              /*!< Auto-Baud Rate Request */\n#define USART_RQR_SBKRQ        ((uint16_t)0x0002)                              /*!< Send Break Request */\n#define USART_RQR_MMRQ         ((uint16_t)0x0004)                              /*!< Mute Mode Request */\n#define USART_RQR_RXFRQ        ((uint16_t)0x0008)                              /*!< Receive Data flush Request */\n#define USART_RQR_TXFRQ        ((uint16_t)0x0010)                              /*!< Transmit data flush Request */\n\n/*******************  Bit definition for USART_ISR register  ******************/\n#define USART_ISR_PE_Pos             (0U)\n#define USART_ISR_PE_Msk             (0x1UL << USART_ISR_PE_Pos)               /*!< 0x00000001 */\n#define USART_ISR_PE                 USART_ISR_PE_Msk                          /*!< Parity Error */\n#define USART_ISR_FE_Pos             (1U)\n#define USART_ISR_FE_Msk             (0x1UL << USART_ISR_FE_Pos)               /*!< 0x00000002 */\n#define USART_ISR_FE                 USART_ISR_FE_Msk                          /*!< Framing Error */\n#define USART_ISR_NE_Pos             (2U)\n#define USART_ISR_NE_Msk             (0x1UL << USART_ISR_NE_Pos)               /*!< 0x00000004 */\n#define USART_ISR_NE                 USART_ISR_NE_Msk                          /*!< Noise detected Flag */\n#define USART_ISR_ORE_Pos            (3U)\n#define USART_ISR_ORE_Msk            (0x1UL << USART_ISR_ORE_Pos)              /*!< 0x00000008 */\n#define USART_ISR_ORE                USART_ISR_ORE_Msk                         /*!< OverRun Error */\n#define USART_ISR_IDLE_Pos           (4U)\n#define USART_ISR_IDLE_Msk           (0x1UL << USART_ISR_IDLE_Pos)             /*!< 0x00000010 */\n#define USART_ISR_IDLE               USART_ISR_IDLE_Msk                        /*!< IDLE line detected */\n#define USART_ISR_RXNE_RXFNE_Pos     (5U)\n#define USART_ISR_RXNE_RXFNE_Msk     (0x1UL << USART_ISR_RXNE_RXFNE_Pos)       /*!< 0x00000020 */\n#define USART_ISR_RXNE_RXFNE         USART_ISR_RXNE_RXFNE_Msk                  /*!< Read Data Register Not Empty/RXFIFO Not Empty */\n#define USART_ISR_TC_Pos             (6U)\n#define USART_ISR_TC_Msk             (0x1UL << USART_ISR_TC_Pos)               /*!< 0x00000040 */\n#define USART_ISR_TC                 USART_ISR_TC_Msk                          /*!< Transmission Complete */\n#define USART_ISR_TXE_TXFNF_Pos      (7U)\n#define USART_ISR_TXE_TXFNF_Msk      (0x1UL << USART_ISR_TXE_TXFNF_Pos)        /*!< 0x00000080 */\n#define USART_ISR_TXE_TXFNF          USART_ISR_TXE_TXFNF_Msk                   /*!< Transmit Data Register Empty/TXFIFO Not Full */\n#define USART_ISR_LBDF_Pos           (8U)\n#define USART_ISR_LBDF_Msk           (0x1UL << USART_ISR_LBDF_Pos)             /*!< 0x00000100 */\n#define USART_ISR_LBDF               USART_ISR_LBDF_Msk                        /*!< LIN Break Detection Flag */\n#define USART_ISR_CTSIF_Pos          (9U)\n#define USART_ISR_CTSIF_Msk          (0x1UL << USART_ISR_CTSIF_Pos)            /*!< 0x00000200 */\n#define USART_ISR_CTSIF              USART_ISR_CTSIF_Msk                       /*!< CTS interrupt flag */\n#define USART_ISR_CTS_Pos            (10U)\n#define USART_ISR_CTS_Msk            (0x1UL << USART_ISR_CTS_Pos)              /*!< 0x00000400 */\n#define USART_ISR_CTS                USART_ISR_CTS_Msk                         /*!< CTS flag */\n#define USART_ISR_RTOF_Pos           (11U)\n#define USART_ISR_RTOF_Msk           (0x1UL << USART_ISR_RTOF_Pos)             /*!< 0x00000800 */\n#define USART_ISR_RTOF               USART_ISR_RTOF_Msk                        /*!< Receiver Time Out */\n#define USART_ISR_EOBF_Pos           (12U)\n#define USART_ISR_EOBF_Msk           (0x1UL << USART_ISR_EOBF_Pos)             /*!< 0x00001000 */\n#define USART_ISR_EOBF               USART_ISR_EOBF_Msk                        /*!< End Of Block Flag */\n#define USART_ISR_UDR_Pos            (13U)\n#define USART_ISR_UDR_Msk            (0x1UL << USART_ISR_UDR_Pos)              /*!< 0x00002000 */\n#define USART_ISR_UDR                 USART_ISR_UDR_Msk                        /*!< SPI Slave Underrun Error Flag */\n#define USART_ISR_ABRE_Pos           (14U)\n#define USART_ISR_ABRE_Msk           (0x1UL << USART_ISR_ABRE_Pos)             /*!< 0x00004000 */\n#define USART_ISR_ABRE               USART_ISR_ABRE_Msk                        /*!< Auto-Baud Rate Error */\n#define USART_ISR_ABRF_Pos           (15U)\n#define USART_ISR_ABRF_Msk           (0x1UL << USART_ISR_ABRF_Pos)             /*!< 0x00008000 */\n#define USART_ISR_ABRF               USART_ISR_ABRF_Msk                        /*!< Auto-Baud Rate Flag */\n#define USART_ISR_BUSY_Pos           (16U)\n#define USART_ISR_BUSY_Msk           (0x1UL << USART_ISR_BUSY_Pos)             /*!< 0x00010000 */\n#define USART_ISR_BUSY               USART_ISR_BUSY_Msk                        /*!< Busy Flag */\n#define USART_ISR_CMF_Pos            (17U)\n#define USART_ISR_CMF_Msk            (0x1UL << USART_ISR_CMF_Pos)              /*!< 0x00020000 */\n#define USART_ISR_CMF                USART_ISR_CMF_Msk                         /*!< Character Match Flag */\n#define USART_ISR_SBKF_Pos           (18U)\n#define USART_ISR_SBKF_Msk           (0x1UL << USART_ISR_SBKF_Pos)             /*!< 0x00040000 */\n#define USART_ISR_SBKF               USART_ISR_SBKF_Msk                        /*!< Send Break Flag */\n#define USART_ISR_RWU_Pos            (19U)\n#define USART_ISR_RWU_Msk            (0x1UL << USART_ISR_RWU_Pos)              /*!< 0x00080000 */\n#define USART_ISR_RWU                USART_ISR_RWU_Msk                         /*!< Receive Wake Up from mute mode Flag */\n#define USART_ISR_WUF_Pos            (20U)\n#define USART_ISR_WUF_Msk            (0x1UL << USART_ISR_WUF_Pos)              /*!< 0x00100000 */\n#define USART_ISR_WUF                USART_ISR_WUF_Msk                         /*!< Wake Up from stop mode Flag */\n#define USART_ISR_TEACK_Pos          (21U)\n#define USART_ISR_TEACK_Msk          (0x1UL << USART_ISR_TEACK_Pos)            /*!< 0x00200000 */\n#define USART_ISR_TEACK              USART_ISR_TEACK_Msk                       /*!< Transmit Enable Acknowledge Flag */\n#define USART_ISR_REACK_Pos          (22U)\n#define USART_ISR_REACK_Msk          (0x1UL << USART_ISR_REACK_Pos)            /*!< 0x00400000 */\n#define USART_ISR_REACK              USART_ISR_REACK_Msk                       /*!< Receive Enable Acknowledge Flag */\n#define USART_ISR_TXFE_Pos           (23U)\n#define USART_ISR_TXFE_Msk           (0x1UL << USART_ISR_TXFE_Pos)             /*!< 0x00800000 */\n#define USART_ISR_TXFE               USART_ISR_TXFE_Msk                        /*!< TXFIFO Empty Flag */\n#define USART_ISR_RXFF_Pos           (24U)\n#define USART_ISR_RXFF_Msk           (0x1UL << USART_ISR_RXFF_Pos)             /*!< 0x01000000 */\n#define USART_ISR_RXFF               USART_ISR_RXFF_Msk                        /*!< RXFIFO Full Flag */\n#define USART_ISR_TCBGT_Pos          (25U)\n#define USART_ISR_TCBGT_Msk          (0x1UL << USART_ISR_TCBGT_Pos)            /*!< 0x02000000 */\n#define USART_ISR_TCBGT              USART_ISR_TCBGT_Msk                       /*!< Transmission Complete Before Guard Time Completion Flag */\n#define USART_ISR_RXFT_Pos           (26U)\n#define USART_ISR_RXFT_Msk           (0x1UL << USART_ISR_RXFT_Pos)             /*!< 0x04000000 */\n#define USART_ISR_RXFT               USART_ISR_RXFT_Msk                        /*!< RXFIFO Threshold Flag */\n#define USART_ISR_TXFT_Pos           (27U)\n#define USART_ISR_TXFT_Msk           (0x1UL << USART_ISR_TXFT_Pos)             /*!< 0x08000000 */\n#define USART_ISR_TXFT               USART_ISR_TXFT_Msk                        /*!< TXFIFO Threshold Flag */\n\n/*******************  Bit definition for USART_ICR register  ******************/\n#define USART_ICR_PECF_Pos           (0U)\n#define USART_ICR_PECF_Msk           (0x1UL << USART_ICR_PECF_Pos)             /*!< 0x00000001 */\n#define USART_ICR_PECF               USART_ICR_PECF_Msk                        /*!< Parity Error Clear Flag */\n#define USART_ICR_FECF_Pos           (1U)\n#define USART_ICR_FECF_Msk           (0x1UL << USART_ICR_FECF_Pos)             /*!< 0x00000002 */\n#define USART_ICR_FECF               USART_ICR_FECF_Msk                        /*!< Framing Error Clear Flag */\n#define USART_ICR_NECF_Pos           (2U)\n#define USART_ICR_NECF_Msk           (0x1UL << USART_ICR_NECF_Pos)             /*!< 0x00000004 */\n#define USART_ICR_NECF               USART_ICR_NECF_Msk                        /*!< Noise Error detected Clear Flag */\n#define USART_ICR_ORECF_Pos          (3U)\n#define USART_ICR_ORECF_Msk          (0x1UL << USART_ICR_ORECF_Pos)            /*!< 0x00000008 */\n#define USART_ICR_ORECF              USART_ICR_ORECF_Msk                       /*!< OverRun Error Clear Flag */\n#define USART_ICR_IDLECF_Pos         (4U)\n#define USART_ICR_IDLECF_Msk         (0x1UL << USART_ICR_IDLECF_Pos)           /*!< 0x00000010 */\n#define USART_ICR_IDLECF             USART_ICR_IDLECF_Msk                      /*!< IDLE line detected Clear Flag */\n#define USART_ICR_TXFECF_Pos         (5U)\n#define USART_ICR_TXFECF_Msk         (0x1UL << USART_ICR_TXFECF_Pos)           /*!< 0x00000020 */\n#define USART_ICR_TXFECF             USART_ICR_TXFECF_Msk                      /*!< TXFIFO Empty Clear Flag */\n#define USART_ICR_TCCF_Pos           (6U)\n#define USART_ICR_TCCF_Msk           (0x1UL << USART_ICR_TCCF_Pos)             /*!< 0x00000040 */\n#define USART_ICR_TCCF               USART_ICR_TCCF_Msk                        /*!< Transmission Complete Clear Flag */\n#define USART_ICR_TCBGTCF_Pos        (7U)\n#define USART_ICR_TCBGTCF_Msk        (0x1UL << USART_ICR_TCBGTCF_Pos)          /*!< 0x00000080 */\n#define USART_ICR_TCBGTCF            USART_ICR_TCBGTCF_Msk                     /*!< Transmission Complete Before Guard Time Clear Flag */\n#define USART_ICR_LBDCF_Pos          (8U)\n#define USART_ICR_LBDCF_Msk          (0x1UL << USART_ICR_LBDCF_Pos)            /*!< 0x00000100 */\n#define USART_ICR_LBDCF              USART_ICR_LBDCF_Msk                       /*!< LIN Break Detection Clear Flag */\n#define USART_ICR_CTSCF_Pos          (9U)\n#define USART_ICR_CTSCF_Msk          (0x1UL << USART_ICR_CTSCF_Pos)            /*!< 0x00000200 */\n#define USART_ICR_CTSCF              USART_ICR_CTSCF_Msk                       /*!< CTS Interrupt Clear Flag */\n#define USART_ICR_RTOCF_Pos          (11U)\n#define USART_ICR_RTOCF_Msk          (0x1UL << USART_ICR_RTOCF_Pos)            /*!< 0x00000800 */\n#define USART_ICR_RTOCF              USART_ICR_RTOCF_Msk                       /*!< Receiver Time Out Clear Flag */\n#define USART_ICR_EOBCF_Pos          (12U)\n#define USART_ICR_EOBCF_Msk          (0x1UL << USART_ICR_EOBCF_Pos)            /*!< 0x00001000 */\n#define USART_ICR_EOBCF              USART_ICR_EOBCF_Msk                       /*!< End Of Block Clear Flag */\n#define USART_ICR_UDRCF_Pos          (13U)\n#define USART_ICR_UDRCF_Msk          (0x1UL << USART_ICR_UDRCF_Pos)            /*!< 0x00002000 */\n#define USART_ICR_UDRCF              USART_ICR_UDRCF_Msk                       /*!< SPI Slave Underrun Clear Flag */\n#define USART_ICR_CMCF_Pos           (17U)\n#define USART_ICR_CMCF_Msk           (0x1UL << USART_ICR_CMCF_Pos)             /*!< 0x00020000 */\n#define USART_ICR_CMCF               USART_ICR_CMCF_Msk                        /*!< Character Match Clear Flag */\n#define USART_ICR_WUCF_Pos           (20U)\n#define USART_ICR_WUCF_Msk           (0x1UL << USART_ICR_WUCF_Pos)             /*!< 0x00100000 */\n#define USART_ICR_WUCF               USART_ICR_WUCF_Msk                        /*!< Wake Up from stop mode Clear Flag */\n\n/*******************  Bit definition for USART_RDR register  ******************/\n#define USART_RDR_RDR_Pos             (0U)\n#define USART_RDR_RDR_Msk             (0x1FFUL << USART_RDR_RDR_Pos)           /*!< 0x000001FF */\n#define USART_RDR_RDR                 USART_RDR_RDR_Msk                        /*!< RDR[8:0] bits (Receive Data value) */\n\n/*******************  Bit definition for USART_TDR register  ******************/\n#define USART_TDR_TDR_Pos             (0U)\n#define USART_TDR_TDR_Msk             (0x1FFUL << USART_TDR_TDR_Pos)           /*!< 0x000001FF */\n#define USART_TDR_TDR                 USART_TDR_TDR_Msk                        /*!< TDR[8:0] bits (Transmit Data value) */\n\n/*******************  Bit definition for USART_PRESC register  ****************/\n#define USART_PRESC_PRESCALER_Pos    (0U)\n#define USART_PRESC_PRESCALER_Msk    (0xFUL << USART_PRESC_PRESCALER_Pos)      /*!< 0x0000000F */\n#define USART_PRESC_PRESCALER        USART_PRESC_PRESCALER_Msk                 /*!< PRESCALER[3:0] bits (Clock prescaler) */\n#define USART_PRESC_PRESCALER_0      (0x1UL << USART_PRESC_PRESCALER_Pos)      /*!< 0x00000001 */\n#define USART_PRESC_PRESCALER_1      (0x2UL << USART_PRESC_PRESCALER_Pos)      /*!< 0x00000002 */\n#define USART_PRESC_PRESCALER_2      (0x4UL << USART_PRESC_PRESCALER_Pos)      /*!< 0x00000004 */\n#define USART_PRESC_PRESCALER_3      (0x8UL << USART_PRESC_PRESCALER_Pos)      /*!< 0x00000008 */\n\n/******************************************************************************/\n/*                                                                            */\n/*                            Window WATCHDOG                                 */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for WWDG_CR register  ********************/\n#define WWDG_CR_T_Pos           (0U)\n#define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                      /*!< 0x0000007F */\n#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */\n#define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                      /*!< 0x00000001 */\n#define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                      /*!< 0x00000002 */\n#define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                      /*!< 0x00000004 */\n#define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                      /*!< 0x00000008 */\n#define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                      /*!< 0x00000010 */\n#define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                      /*!< 0x00000020 */\n#define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                      /*!< 0x00000040 */\n\n#define WWDG_CR_WDGA_Pos        (7U)\n#define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                    /*!< 0x00000080 */\n#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */\n\n/*******************  Bit definition for WWDG_CFR register  *******************/\n#define WWDG_CFR_W_Pos          (0U)\n#define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                     /*!< 0x0000007F */\n#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */\n#define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                     /*!< 0x00000001 */\n#define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                     /*!< 0x00000002 */\n#define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                     /*!< 0x00000004 */\n#define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                     /*!< 0x00000008 */\n#define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                     /*!< 0x00000010 */\n#define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                     /*!< 0x00000020 */\n#define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                     /*!< 0x00000040 */\n\n#define WWDG_CFR_WDGTB_Pos      (11U)\n#define WWDG_CFR_WDGTB_Msk      (0x7UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00003800 */\n#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[2:0] bits (Timer Base) */\n#define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00000800 */\n#define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00001000 */\n#define WWDG_CFR_WDGTB_2        (0x4UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00002000 */\n\n#define WWDG_CFR_EWI_Pos        (9U)\n#define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                    /*!< 0x00000200 */\n#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */\n\n/*******************  Bit definition for WWDG_SR register  ********************/\n#define WWDG_SR_EWIF_Pos        (0U)\n#define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                    /*!< 0x00000001 */\n#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */\n\n\n/** @addtogroup Exported_macros\n  * @{\n  */\n\n/******************************* ADC Instances ********************************/\n#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)\n\n#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)\n\n/******************************* CRC Instances ********************************/\n#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)\n\n/******************************** DMA Instances *******************************/\n\n#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \\\n                                       ((INSTANCE) == DMA1_Channel2) || \\\n                                       ((INSTANCE) == DMA1_Channel3))\n                                       \n/******************************** DMAMUX Instances ****************************/\n#define IS_DMAMUX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMAMUX1)\n\n#define IS_DMAMUX_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \\\n                                                      ((INSTANCE) == DMAMUX1_RequestGenerator1) || \\\n                                                      ((INSTANCE) == DMAMUX1_RequestGenerator2))\n\n/******************************* GPIO Instances *******************************/\n#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \\\n                                        ((INSTANCE) == GPIOB) || \\\n                                        ((INSTANCE) == GPIOC) || \\\n                                        ((INSTANCE) == GPIOD) || \\\n                                        ((INSTANCE) == GPIOF))\n/******************************* GPIO AF Instances ****************************/\n#define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)\n\n/**************************** GPIO Lock Instances *****************************/\n#define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \\\n                                         ((INSTANCE) == GPIOB) || \\\n                                         ((INSTANCE) == GPIOC))\n\n/******************************** I2C Instances *******************************/\n#define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)\n\n/****************************** RTC Instances *********************************/\n#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)\n\n/****************************** SMBUS Instances *******************************/\n#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))\n\n/****************************** WAKEUP_FROMSTOP Instances *******************************/\n#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))\n\n/******************************** SPI Instances *******************************/\n#define IS_SPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)\n/******************************** SPI Instances *******************************/\n#define IS_I2S_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == SPI1)\n\n\n/****************** TIM Instances : All supported instances *******************/\n#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \\\n                                         ((INSTANCE) == TIM3)   || \\\n                                         ((INSTANCE) == TIM14)  || \\\n                                         ((INSTANCE) == TIM16)  || \\\n                                         ((INSTANCE) == TIM17))\n/****************** TIM Instances : supporting 32 bits counter ****************/\n#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (0UL)\n/****************** TIM Instances : supporting the break function *************/\n#define IS_TIM_BREAK_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \\\n                                            ((INSTANCE) == TIM16)   || \\\n                                            ((INSTANCE) == TIM17))\n/************** TIM Instances : supporting Break source selection *************/\n#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (0UL)\n/****************** TIM Instances : supporting 2 break inputs *****************/\n#define IS_TIM_BKIN2_INSTANCE(INSTANCE)    ((INSTANCE) == TIM1)\n/************* TIM Instances : at least 1 capture/compare channel *************/\n#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \\\n                                         ((INSTANCE) == TIM3)   || \\\n                                         ((INSTANCE) == TIM14)  || \\\n                                         ((INSTANCE) == TIM16)  || \\\n                                         ((INSTANCE) == TIM17))\n/************ TIM Instances : at least 2 capture/compare channels *************/\n#define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \\\n                                         ((INSTANCE) == TIM3))\n/************ TIM Instances : at least 3 capture/compare channels *************/\n#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \\\n                                         ((INSTANCE) == TIM3))\n/************ TIM Instances : at least 4 capture/compare channels *************/\n#define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \\\n                                         ((INSTANCE) == TIM3))\n/****************** TIM Instances : at least 5 capture/compare channels *******/\n#define IS_TIM_CC5_INSTANCE(INSTANCE)   ((INSTANCE) == TIM1)\n\n/****************** TIM Instances : at least 6 capture/compare channels *******/\n#define IS_TIM_CC6_INSTANCE(INSTANCE)   ((INSTANCE) == TIM1)\n\n/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/\n#define IS_TIM_CCDMA_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)   || \\\n                                            ((INSTANCE) == TIM16)  || \\\n                                            ((INSTANCE) == TIM17))\n/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/\n#define IS_TIM_DMA_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \\\n                                            ((INSTANCE) == TIM3)   || \\\n                                            ((INSTANCE) == TIM16)  || \\\n                                            ((INSTANCE) == TIM17))\n/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/\n#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \\\n                                            ((INSTANCE) == TIM3)   || \\\n                                            ((INSTANCE) == TIM14)  || \\\n                                            ((INSTANCE) == TIM16)  || \\\n                                            ((INSTANCE) == TIM17))\n/******************** TIM Instances : DMA burst feature ***********************/\n#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \\\n                                            ((INSTANCE) == TIM3)   || \\\n                                            ((INSTANCE) == TIM16)  || \\\n                                            ((INSTANCE) == TIM17))\n/******************* TIM Instances : output(s) available **********************/\n#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \\\n    ((((INSTANCE) == TIM1) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_5) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_6)))           \\\n     ||                                        \\\n     (((INSTANCE) == TIM3) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n     ||                                        \\\n     (((INSTANCE) == TIM14) &&                 \\\n     (((CHANNEL) == TIM_CHANNEL_1)))           \\\n     ||                                        \\\n     (((INSTANCE) == TIM16) &&                 \\\n     (((CHANNEL) == TIM_CHANNEL_1)))           \\\n     ||                                        \\\n     (((INSTANCE) == TIM17) &&                 \\\n      (((CHANNEL) == TIM_CHANNEL_1))))\n\n/****************** TIM Instances : supporting complementary output(s) ********/\n#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \\\n   ((((INSTANCE) == TIM1) &&                    \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||           \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||           \\\n      ((CHANNEL) == TIM_CHANNEL_3)))            \\\n    ||                                          \\\n    (((INSTANCE) == TIM16) &&                   \\\n     ((CHANNEL) == TIM_CHANNEL_1))              \\\n    ||                                          \\\n    (((INSTANCE) == TIM17) &&                   \\\n     ((CHANNEL) == TIM_CHANNEL_1)))\n\n/****************** TIM Instances : supporting clock division *****************/\n#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)    || \\\n                                                    ((INSTANCE) == TIM3)    || \\\n                                                    ((INSTANCE) == TIM14)   || \\\n                                                    ((INSTANCE) == TIM16)   || \\\n                                                    ((INSTANCE) == TIM17))\n\n/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/\n#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                                        ((INSTANCE) == TIM3))\n/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/\n#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                                        ((INSTANCE) == TIM3))\n/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/\n#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1) || \\\n                                                        ((INSTANCE) == TIM3))\n/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/\n#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1) || \\\n                                                        ((INSTANCE) == TIM3))\n/****************** TIM Instances : supporting combined 3-phase PWM mode ******/\n#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE)    ((INSTANCE) == TIM1)\n\n/****************** TIM Instances : supporting commutation event generation ***/\n#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \\\n                                                     ((INSTANCE) == TIM16)  || \\\n                                                     ((INSTANCE) == TIM17))\n/****************** TIM Instances : supporting counting mode selection ********/\n#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                                        ((INSTANCE) == TIM3))\n/****************** TIM Instances : supporting encoder interface **************/\n#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \\\n                                                      ((INSTANCE) == TIM3))\n\n/****************** TIM Instances : supporting Hall sensor interface **********/\n#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \\\n                                                         ((INSTANCE) == TIM3))\n/**************** TIM Instances : external trigger input available ************/\n#define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)  || \\\n                                            ((INSTANCE) == TIM3))\n/**************** TIM Instances : supporting ETR source selection ***************/\n#define IS_TIM_ETRSEL_INSTANCE(INSTANCE)   (0UL)\n/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/\n#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \\\n                                            ((INSTANCE) == TIM3))\n/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/\n#define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \\\n                                            ((INSTANCE) == TIM3))\n/****************** TIM Instances : supporting OCxREF clear *******************/\n#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)        (((INSTANCE) == TIM1) || \\\n                                                       ((INSTANCE) == TIM3))\n/****************** TIM Instances : remapping capability **********************/\n#define IS_TIM_REMAP_INSTANCE(INSTANCE)    ((INSTANCE) == TIM1)\n\n/****************** TIM Instances : supporting repetition counter *************/\n#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \\\n                                                       ((INSTANCE) == TIM16) || \\\n                                                       ((INSTANCE) == TIM17))\n\n/****************** TIM Instances : supporting synchronization ****************/\n#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)  IS_TIM_MASTER_INSTANCE(INSTANCE)\n\n/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/\n#define IS_TIM_TRGO2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1))\n\n/******************* TIM Instances : Timer input XOR function *****************/\n#define IS_TIM_XOR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \\\n                                            ((INSTANCE) == TIM3))\n/******************* TIM Instances : Timer input selection ********************/\n#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM14)  || \\\n                                         ((INSTANCE) == TIM16)  || \\\n                                         ((INSTANCE) == TIM17))\n/************ TIM Instances : Advanced timers  ********************************/\n#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1))\n\n/******************** UART Instances : Asynchronous mode **********************/\n#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                    ((INSTANCE) == USART2))\n/******************** USART Instances : Synchronous mode **********************/\n#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                     ((INSTANCE) == USART2))\n/****************** UART Instances : Hardware Flow control ********************/\n#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                           ((INSTANCE) == USART2))\n/********************* USART Instances : Smard card mode ***********************/\n#define IS_SMARTCARD_INSTANCE(INSTANCE) ((INSTANCE) == USART1)\n/****************** UART Instances : Auto Baud Rate detection ****************/\n#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1)\n\n/******************** UART Instances : Half-Duplex mode **********************/\n#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \\\n                                                 ((INSTANCE) == USART2))\n/******************** UART Instances : LIN mode **********************/\n#define IS_UART_LIN_INSTANCE(INSTANCE)   ((INSTANCE) == USART1)\n/******************** UART Instances : Wake-up from Stop mode **********************/\n#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   ((INSTANCE) == USART1)\n\n/****************** UART Instances : Driver Enable *****************/\n#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE)     (((INSTANCE) == USART1) || \\\n                                                      ((INSTANCE) == USART2))\n/****************** UART Instances : SPI Slave selection mode ***************/\n#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                              ((INSTANCE) == USART2))\n/****************** UART Instances : Driver Enable *****************/\n#define IS_UART_FIFO_INSTANCE(INSTANCE)     ((INSTANCE) == USART1)\n/*********************** UART Instances : IRDA mode ***************************/\n#define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART1)\n/****************************** IWDG Instances ********************************/\n#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)\n\n/****************************** WWDG Instances ********************************/\n#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)\n\n/**\n  * @}\n  */\n\n /**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* STM32C031xx_H */\n\n/**\n  * @}\n  */\n\n  /**\n  * @}\n  */\n"
  },
  {
    "path": "3rd_party/nucleo-c031c6/stm32c0xx.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32c0xx.h\n  * @author  MCD Application Team\n  * @brief   CMSIS STM32C0xx Device Peripheral Access Layer Header File.\n  *\n  *          The file is the unique include file that the application programmer\n  *          is using in the C source code, usually in main.c. This file contains:\n  *           - Configuration section that allows to select:\n  *              - The STM32C0xx device used in the target application\n  *              - To use or not the peripherals drivers in application code(i.e.\n  *                code will be based on direct access to peripherals registers\n  *                rather than drivers API), this option is controlled by\n  *                \"#define USE_HAL_DRIVER\"\n  *\n  ******************************************************************************\n  * @attention\n  *\n  * Copyright (c) 2022 STMicroelectronics.\n  * All rights reserved.\n  *\n  * This software is licensed under terms that can be found in the LICENSE file\n  * in the root directory of this software component.\n  * If no LICENSE file comes with this software, it is provided AS-IS.\n  *\n  ******************************************************************************\n  */\n\n/** @addtogroup CMSIS\n  * @{\n  */\n\n/** @addtogroup stm32c0xx\n  * @{\n  */\n\n#ifndef STM32C0xx_H\n#define STM32C0xx_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif /* __cplusplus */\n\n/** @addtogroup Library_configuration_section\n  * @{\n  */\n\n/**\n  * @brief STM32 Family\n  */\n#if !defined (STM32C0)\n#define STM32C0\n#endif /* STM32C0 */\n\n/* Uncomment the line below according to the target STM32C0 device used in your\n   application\n  */\n\n#if !defined (STM32C011xx) && !defined (STM32C031xx)\n  /* #define STM32C011xx */   /*!< STM32C011xx Devices */\n  /* #define STM32C031xx */   /*!< STM32C031xx Devices */\n#endif\n\n/*  Tip: To avoid modifying this file each time you need to switch between these\n        devices, you can define the device in your toolchain compiler preprocessor.\n  */\n#if !defined  (USE_HAL_DRIVER)\n/**\n * @brief Comment the line below if you will not use the peripherals drivers.\n   In this case, these drivers will not be included and the application code will\n   be based on direct access to peripherals registers\n   */\n  /*#define USE_HAL_DRIVER */\n#endif /* USE_HAL_DRIVER */\n\n/**\n  * @brief CMSIS Device version number V1.0.0\n  */\n#define __STM32C0_CMSIS_VERSION_MAIN   (0x01U) /*!< [31:24] main version */\n#define __STM32C0_CMSIS_VERSION_SUB1   (0x00U) /*!< [23:16] sub1 version */\n#define __STM32C0_CMSIS_VERSION_SUB2   (0x00U) /*!< [15:8]  sub2 version */\n#define __STM32C0_CMSIS_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */\n#define __STM32C0_CMSIS_VERSION        ((__STM32C0_CMSIS_VERSION_MAIN << 24)\\\n                                       |(__STM32C0_CMSIS_VERSION_SUB1 << 16)\\\n                                       |(__STM32C0_CMSIS_VERSION_SUB2 << 8 )\\\n                                       |(__STM32C0_CMSIS_VERSION_RC))\n\n/**\n  * @}\n  */\n\n/** @addtogroup Device_Included\n  * @{\n  */\n\n#if defined(STM32C011xx)\n  #include \"stm32c011xx.h\"\n#elif defined(STM32C031xx)\n  #include \"stm32c031xx.h\"\n#else\n #error \"Please select first the target STM32C0xx device used in your application (in stm32c0xx.h file)\"\n#endif\n\n/**\n  * @}\n  */\n\n/** @addtogroup Exported_types\n  * @{\n  */\ntypedef enum\n{\n  RESET = 0,\n  SET = !RESET\n} FlagStatus, ITStatus;\n\ntypedef enum\n{\n  DISABLE = 0,\n  ENABLE = !DISABLE\n} FunctionalState;\n#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))\n\ntypedef enum\n{\n  SUCCESS = 0,\n  ERROR = !SUCCESS\n} ErrorStatus;\n\n/**\n  * @}\n  */\n\n/** @addtogroup Exported_macros\n  * @{\n  */\n#define SET_BIT(REG, BIT)     ((REG) |= (BIT))\n\n#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))\n\n#define READ_BIT(REG, BIT)    ((REG) & (BIT))\n\n#define CLEAR_REG(REG)        ((REG) = (0x0))\n\n#define WRITE_REG(REG, VAL)   ((REG) = (VAL))\n\n#define READ_REG(REG)         ((REG))\n\n#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))\n\n/* Use of interrupt control for register exclusive access */\n/* Atomic 32-bit register access macro to set one or several bits */\n#define ATOMIC_SET_BIT(REG, BIT)                             \\\n  do {                                                       \\\n    uint32_t primask;                                        \\\n    primask = __get_PRIMASK();                               \\\n    __set_PRIMASK(1);                                        \\\n    SET_BIT((REG), (BIT));                                   \\\n    __set_PRIMASK(primask);                                  \\\n  } while(0)\n\n/* Atomic 32-bit register access macro to clear one or several bits */\n#define ATOMIC_CLEAR_BIT(REG, BIT)                           \\\n  do {                                                       \\\n    uint32_t primask;                                        \\\n    primask = __get_PRIMASK();                               \\\n    __set_PRIMASK(1);                                        \\\n    CLEAR_BIT((REG), (BIT));                                 \\\n    __set_PRIMASK(primask);                                  \\\n  } while(0)\n\n/* Atomic 32-bit register access macro to clear and set one or several bits */\n#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK)            \\\n  do {                                                       \\\n    uint32_t primask;                                        \\\n    primask = __get_PRIMASK();                               \\\n    __set_PRIMASK(1);                                        \\\n    MODIFY_REG((REG), (CLEARMSK), (SETMASK));                \\\n    __set_PRIMASK(primask);                                  \\\n  } while(0)\n\n/* Atomic 16-bit register access macro to set one or several bits */\n#define ATOMIC_SETH_BIT(REG, BIT) ATOMIC_SET_BIT(REG, BIT)                                   \\\n\n/* Atomic 16-bit register access macro to clear one or several bits */\n#define ATOMIC_CLEARH_BIT(REG, BIT) ATOMIC_CLEAR_BIT(REG, BIT)                               \\\n\n/* Atomic 16-bit register access macro to clear and set one or several bits */\n#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \\\n\n#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL)))\n/**\n  * @}\n  */\n\n#if defined (USE_HAL_DRIVER)\n #include \"stm32c0xx_hal.h\"\n#endif /* USE_HAL_DRIVER */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* STM32C0xx_H */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n"
  },
  {
    "path": "3rd_party/nucleo-c031c6/system_stm32c0xx.c",
    "content": "/**\n  ******************************************************************************\n  * @file    system_stm32c0xx.c\n  * @author  MCD Application Team\n  * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File\n  *\n  *   This file provides two functions and one global variable to be called from\n  *   user application:\n  *      - SystemInit(): This function is called at startup just after reset and\n  *                      before branch to main program. This call is made inside\n  *                      the \"startup_stm32c0xx.s\" file.\n  *\n  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used\n  *                                  by the user application to setup the SysTick\n  *                                  timer or configure other parameters.\n  *\n  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must\n  *                                 be called whenever the core clock is changed\n  *                                 during program execution.\n  *\n  ******************************************************************************\n  * @attention\n  *\n  * Copyright (c) 2022 STMicroelectronics.\n  * All rights reserved.\n  *\n  * This software is licensed under terms that can be found in the LICENSE file\n  * in the root directory of this software component.\n  * If no LICENSE file comes with this software, it is provided AS-IS.\n  *\n  ******************************************************************************\n  */\n\n/** @addtogroup CMSIS\n  * @{\n  */\n\n/** @addtogroup stm32c0xx_system\n  * @{\n  */\n\n/** @addtogroup STM32C0xx_System_Private_Includes\n  * @{\n  */\n\n#include \"stm32c0xx.h\"\n\n#if !defined  (HSE_VALUE)\n#define HSE_VALUE    (48000000UL)    /*!< Value of the External oscillator in Hz */\n#endif /* HSE_VALUE */\n\n#if !defined  (HSI_VALUE)\n  #define HSI_VALUE  (48000000UL)   /*!< Value of the Internal oscillator in Hz*/\n#endif /* HSI_VALUE */\n\n#if !defined  (LSI_VALUE)\n #define LSI_VALUE   (32000UL)     /*!< Value of LSI in Hz*/\n#endif /* LSI_VALUE */\n\n#if !defined  (LSE_VALUE)\n  #define LSE_VALUE  (32768UL)      /*!< Value of LSE in Hz*/\n#endif /* LSE_VALUE */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32C0xx_System_Private_TypesDefinitions\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32C0xx_System_Private_Defines\n  * @{\n  */\n\n/************************* Miscellaneous Configuration ************************/\n/*!< Uncomment the following line if you need to relocate your vector Table in\n     Internal SRAM. */\n//#define VECT_TAB_SRAM \n#define VECT_TAB_OFFSET  0x0U /*!< Vector Table base offset field.\n                                   This value must be a multiple of 0x100. */\n/******************************************************************************/\n/**\n  * @}\n  */\n\n/** @addtogroup STM32C0xx_System_Private_Macros\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32C0xx_System_Private_Variables\n  * @{\n  */\n  /* The SystemCoreClock variable is updated in three ways:\n      1) by calling CMSIS function SystemCoreClockUpdate()\n      2) by calling HAL API function HAL_RCC_GetHCLKFreq()\n      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency\n         Note: If you use this function to configure the system clock; then there\n               is no need to call the 2 first functions listed above, since SystemCoreClock\n               variable is updated automatically.\n  */\n  uint32_t SystemCoreClock = 48000000UL;\n\n  const uint32_t AHBPrescTable[16UL] = {0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL, 6UL, 7UL, 8UL, 9UL};\n  const uint32_t APBPrescTable[8UL] =  {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32C0xx_System_Private_FunctionPrototypes\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32C0xx_System_Private_Functions\n  * @{\n  */\n\n/**\n  * @brief  Setup the microcontroller system.\n  * @param  None\n  * @retval None\n  */\nvoid SystemInit(void)\n{\n  \n  /* Configure the Vector Table location add offset address ------------------*/\n#ifdef VECT_TAB_SRAM\n  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */\n#else\n  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */\n#endif\n}\n\n/**\n  * @brief  Update SystemCoreClock variable according to Clock Register Values.\n  *         The SystemCoreClock variable contains the core clock (HCLK), it can\n  *         be used by the user application to setup the SysTick timer or configure\n  *         other parameters.\n  *\n  * @note   Each time the core clock (HCLK) changes, this function must be called\n  *         to update SystemCoreClock variable value. Otherwise, any configuration\n  *         based on this variable will be incorrect.\n  *\n  * @note   - The system frequency computed by this function is not the real\n  *           frequency in the chip. It is calculated based on the predefined\n  *           constant and the selected clock source:\n  *\n  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) / HSI division factor\n  *\n  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)\n  *\n  *           - If SYSCLK source is LSI, SystemCoreClock will contain the LSI_VALUE\n  *\n  *           - If SYSCLK source is LSE, SystemCoreClock will contain the LSE_VALUE\n  *\n  *         (**) HSI_VALUE is a constant defined in stm32c0xx_hal_conf.h file (default value\n  *              48 MHz) but the real value may vary depending on the variations\n  *              in voltage and temperature.\n  *\n  *         (***) HSE_VALUE is a constant defined in stm32c0xx_hal_conf.h file (default value\n  *              48 MHz), user has to ensure that HSE_VALUE is same as the real\n  *              frequency of the crystal used. Otherwise, this function may\n  *              have wrong result.\n  *\n  *         - The result of this function could be not correct when using fractional\n  *           value for HSE crystal.\n  *\n  * @param  None\n  * @retval None\n  */\nvoid SystemCoreClockUpdate(void)\n{\n  uint32_t tmp;\n  uint32_t hsidiv;\n\n  /* Get SYSCLK source -------------------------------------------------------*/\n  switch (RCC->CFGR & RCC_CFGR_SWS)\n  {\n    case RCC_CFGR_SWS_0:                /* HSE used as system clock */\n      SystemCoreClock = HSE_VALUE;\n      break;\n\n    case (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0):  /* LSI used as system clock */\n      SystemCoreClock = LSI_VALUE;\n      break;\n\n    case RCC_CFGR_SWS_2:                /* LSE used as system clock */\n      SystemCoreClock = LSE_VALUE;\n      break;\n\n    case 0x00000000U:                   /* HSI used as system clock */\n    default:                            /* HSI used as system clock */\n      hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV))>> RCC_CR_HSIDIV_Pos));\n      SystemCoreClock = (HSI_VALUE/hsidiv);\n      break;\n  }\n  /* Compute HCLK clock frequency --------------------------------------------*/\n  /* Get HCLK prescaler */\n  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];\n  /* HCLK clock frequency */\n  SystemCoreClock >>= tmp;\n}\n\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n"
  },
  {
    "path": "3rd_party/nucleo-c031c6/system_stm32c0xx.h",
    "content": "/**\n  ******************************************************************************\n  * @file    system_stm32c0xx.h\n  * @author  MCD Application Team\n  * @brief   CMSIS Cortex-M0+ Device System Source File for STM32C0xx devices.\n  ******************************************************************************\n  * @attention\n  *\n  * Copyright (c) 2022 STMicroelectronics.\n  * All rights reserved.\n  *\n  * This software is licensed under terms that can be found in the LICENSE file\n  * in the root directory of this software component.\n  * If no LICENSE file comes with this software, it is provided AS-IS.\n  *\n  ******************************************************************************\n  */\n\n/** @addtogroup CMSIS\n  * @{\n  */\n\n/** @addtogroup stm32c0xx_system\n  * @{\n  */\n\n/**\n  * @brief Define to prevent recursive inclusion\n  */\n#ifndef SYSTEM_STM32C0XX_H\n#define SYSTEM_STM32C0XX_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/** @addtogroup STM32C0xx_System_Includes\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n\n/** @addtogroup STM32C0xx_System_Exported_types\n  * @{\n  */\n  /* This variable is updated in three ways:\n      1) by calling CMSIS function SystemCoreClockUpdate()\n      2) by calling HAL API function HAL_RCC_GetSysClockFreq()\n      3) each time HAL_RCC_ClockConfig()  is called to configure the system clock frequency\n         Note: If you use this function to configure the system clock; then there\n               is no need to call the 2 first functions listed above, since SystemCoreClock\n               variable is updated automatically.\n  */\nextern uint32_t SystemCoreClock;         /*!< System Clock Frequency (Core Clock) */\n\nextern const uint32_t AHBPrescTable[16];  /*!<  AHB prescalers table values */\nextern const uint32_t APBPrescTable[8];   /*!< APB prescalers table values */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32C0xx_System_Exported_Constants\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32C0xx_System_Exported_Macros\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32C0xx_System_Exported_Functions\n  * @{\n  */\n\nextern void SystemInit(void);\nextern void SystemCoreClockUpdate(void);\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /*SYSTEM_STM32C0XX_H */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n"
  },
  {
    "path": "3rd_party/nucleo-h743zi/README.txt",
    "content": "This folder contains the support code for the NUCLEO-H743ZI board.\n\n\nCMSIS-Compliant Device Files\n============================\nThe code also includes the CMSIS-compliant interface to the\nSTM32L053xx MCU files:\n\narm\\startup_stm32h743xx.s\ngnu\\startup_stm32h743xx.c\niar\\startup_stm32h743xx.s\ncmsis_*\nstm32h7xx.h\nstm32h743xx.h\nsystem_stm32h7xx.h\nsystem_stm32h7xx.c\n\n\n\n "
  },
  {
    "path": "3rd_party/nucleo-h743zi/arm/startup_stm32h743xx.s",
    "content": ";/***************************************************************************/\n; * @file     startup_stm32h743xx.s for ARM-KEIL ARM assembler\n; * @brief    CMSIS Cortex-M7 Core Device Startup File for STM32H743xx\n; * @version  CMSIS 5.9.0\n; * @date     1 Feb 2023\n; *\n; * Modified by Quantum Leaps:\n; * - Added relocating of the Vector Table to free up the 256B region at 0x0\n; *   for NULL-pointer protection by the MPU.\n; * - Modified all exception handlers to branch to assert_failed()\n; *   instead of locking up the CPU inside an endless loop.\n; *\n; * @description\n; * Created from the CMSIS template for the specified device\n; * Quantum Leaps, www.state-machine.com\n; *\n; * @note\n; * The symbols Stack_Size and Heap_Size should be provided on the command-\n; * line options to the assembler, for example as:\n; *     --pd \"Stack_Size SETA 1024\" --pd \"Heap_Size SETA 0\"\n\n\n;******************************************************************************\n; Allocate space for the stack.\n;\n        AREA    STACK, NOINIT, READWRITE, ALIGN=3\n__stack_base\nStackMem\n        SPACE   Stack_Size    ; provided in command-line option, for example:\n                              ; --pd \"Stack_Size SETA 512\"\n__stack_limit\n__initial_sp\n\n;******************************************************************************\n; Allocate space for the heap.\n;\n        AREA    HEAP, NOINIT, READWRITE, ALIGN=3\n__heap_base\nHeapMem\n        SPACE   Heap_Size     ; provided in command-line option, for example:\n                              ; --pd \"Heap_Size SETA 0\"\n__heap_limit\n\n; Indicate that the code in this file preserves 8-byte alignment of the stack.\n        PRESERVE8\n\n;******************************************************************************\n; The vector table.\n;\n; Place code into the reset code section.\n        AREA   RESET, DATA, READONLY, ALIGN=8\n        EXPORT  __Vectors\n        EXPORT  __Vectors_End\n        EXPORT  __Vectors_Size\n\n__Vectors\n    ; Initial Vector Table before relocation\n        DCD     __initial_sp                ; Top of Stack\n        DCD     Reset_Handler               ; Reset Handler\n        DCD     NMI_Handler                 ; NMI Handler\n        DCD     HardFault_Handler           ; Hard Fault Handler\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     SVC_Handler                 ; SVCall handler\n        DCD     DebugMon_Handler            ; Debug Monitor handler\n        DCD     Default_Handler             ; Reserved\n        DCD     PendSV_Handler              ; PendSV handler\n        DCD     SysTick_Handler             ; SysTick handler\n\n        ; IRQ handlers...\n        DCD     WWDG_IRQHandler             ; [ 0] Window WatchDog Interrupt ( wwdg1_it)\n        DCD     PVD_AVD_IRQHandler          ; [ 1] PVD/AVD through EXTI Line detection\n        DCD     TAMP_STAMP_IRQHandler       ; [ 2] Tamper and TimeStamps through EXTI line\n        DCD     RTC_WKUP_IRQHandler         ; [ 3] RTC Wakeup through the EXTI line\n        DCD     FLASH_IRQHandler            ; [ 4] FLASH\n        DCD     RCC_IRQHandler              ; [ 5] RCC\n        DCD     EXTI0_IRQHandler            ; [ 6] EXTI Line0\n        DCD     EXTI1_IRQHandler            ; [ 7] EXTI Line1\n        DCD     EXTI2_IRQHandler            ; [ 8] EXTI Line2\n        DCD     EXTI3_IRQHandler            ; [ 9] EXTI Line3\n        DCD     EXTI4_IRQHandler            ; [10] EXTI Line4\n        DCD     DMA1_Stream0_IRQHandler     ; [11] DMA1 Stream 0\n        DCD     DMA1_Stream1_IRQHandler     ; [12] DMA1 Stream 1\n        DCD     DMA1_Stream2_IRQHandler     ; [13] DMA1 Stream 2\n        DCD     DMA1_Stream3_IRQHandler     ; [14] DMA1 Stream 3\n        DCD     DMA1_Stream4_IRQHandler     ; [15] DMA1 Stream 4\n        DCD     DMA1_Stream5_IRQHandler     ; [16] DMA1 Stream 5\n        DCD     DMA1_Stream6_IRQHandler     ; [17] DMA1 Stream 6\n        DCD     ADC_IRQHandler              ; [18] ADC1, ADC2\n        DCD     FDCAN1_IT0_IRQHandler       ; [19] FDCAN1 interrupt line 0\n        DCD     FDCAN2_IT0_IRQHandler       ; [20] FDCAN2 interrupt line 0\n        DCD     FDCAN1_IT1_IRQHandler       ; [21] FDCAN1 interrupt line 1\n        DCD     FDCAN2_IT1_IRQHandler       ; [22] FDCAN2 interrupt line 1\n        DCD     EXTI9_5_IRQHandler          ; [23] External Line[9:5]s\n        DCD     TIM1_BRK_IRQHandler         ; [24] TIM1 Break interrupt\n        DCD     TIM1_UP_IRQHandler          ; [25] TIM1 Update\n        DCD     TIM1_TRG_COM_IRQHandler     ; [26] TIM1 Trigger and Commutation Interrupt\n        DCD     TIM1_CC_IRQHandler          ; [27] TIM1 Capture Compare\n        DCD     TIM2_IRQHandler             ; [28] TIM2\n        DCD     TIM3_IRQHandler             ; [29] TIM3\n        DCD     TIM4_IRQHandler             ; [30] TIM4\n        DCD     I2C1_EV_IRQHandler          ; [31] I2C1 Event\n        DCD     I2C1_ER_IRQHandler          ; [32] I2C1 Error\n        DCD     I2C2_EV_IRQHandler          ; [33] I2C2 Event\n        DCD     I2C2_ER_IRQHandler          ; [34] I2C2 Error\n        DCD     SPI1_IRQHandler             ; [35] SPI1\n        DCD     SPI2_IRQHandler             ; [36] SPI2\n        DCD     USART1_IRQHandler           ; [37] USART1\n        DCD     USART2_IRQHandler           ; [38] USART2\n        DCD     USART3_IRQHandler           ; [39] USART3\n        DCD     EXTI15_10_IRQHandler        ; [40] External Line[15:10]\n        DCD     RTC_Alarm_IRQHandler        ; [41] RTC Alarm (A and B) through EXTI Line\n        DCD     Reserved42_IRQHandler       ; [42] Reserved\n        DCD     TIM8_BRK_TIM12_IRQHandler   ; [43] TIM8 Break Interrupt and TIM12 global interrupt\n        DCD     TIM8_UP_TIM13_IRQHandler    ; [44] TIM8 Update Interrupt and TIM13 global interrupt\n        DCD     TIM8_TRG_COM_TIM14_IRQHandler;[45] TIM8 Trigger and Commutation Interrupt and TIM14 glob\n        DCD     TIM8_CC_IRQHandler          ; [46] TIM8 Capture Compare Interrupt\n        DCD     DMA1_Stream7_IRQHandler     ; [47] DMA1 Stream7\n        DCD     FMC_IRQHandler              ; [48] FMC\n        DCD     SDMMC1_IRQHandler           ; [49] SDMMC1\n        DCD     TIM5_IRQHandler             ; [50] TIM5\n        DCD     SPI3_IRQHandler             ; [51] SPI3\n        DCD     UART4_IRQHandler            ; [52] UART4\n        DCD     UART5_IRQHandler            ; [53] UART5\n        DCD     TIM6_DAC_IRQHandler         ; [54] TIM6 and DAC1&2 underrun errors\n        DCD     TIM7_IRQHandler             ; [55] TIM7\n        DCD     DMA2_Stream0_IRQHandler     ; [56] DMA2 Stream 0\n        DCD     DMA2_Stream1_IRQHandler     ; [57] DMA2 Stream 1\n        DCD     DMA2_Stream2_IRQHandler     ; [58] DMA2 Stream 2\n        DCD     DMA2_Stream3_IRQHandler     ; [59] DMA2 Stream 3\n        DCD     DMA2_Stream4_IRQHandler     ; [60] DMA2 Stream 4\n        DCD     ETH_IRQHandler              ; [61] Ethernet\n        DCD     ETH_WKUP_IRQHandler         ; [62] Ethernet Wakeup through EXTI line\n        DCD     FDCAN_CAL_IRQHandler        ; [63] FDCAN calibration unit interrupt\n        DCD     Reserved64_IRQHandler       ; [64] Reserved\n        DCD     Reserved65_IRQHandler       ; [65] Reserved\n        DCD     Reserved66_IRQHandler       ; [66] Reserved\n        DCD     Reserved67_IRQHandler       ; [67] Reserved\n        DCD     DMA2_Stream5_IRQHandler     ; [68] DMA2 Stream 5\n        DCD     DMA2_Stream6_IRQHandler     ; [69] DMA2 Stream 6\n        DCD     DMA2_Stream7_IRQHandler     ; [70] DMA2 Stream 7\n        DCD     USART6_IRQHandler           ; [71] USART6\n        DCD     I2C3_EV_IRQHandler          ; [72] I2C3 event\n        DCD     I2C3_ER_IRQHandler          ; [73] I2C3 error\n        DCD     OTG_HS_EP1_OUT_IRQHandler   ; [74] USB OTG HS End Point 1 Out\n        DCD     OTG_HS_EP1_IN_IRQHandler    ; [75] USB OTG HS End Point 1 In\n        DCD     OTG_HS_WKUP_IRQHandler      ; [76] USB OTG HS Wakeup through EXTI\n        DCD     OTG_HS_IRQHandler           ; [77] USB OTG HS\n        DCD     DCMI_IRQHandler             ; [78] DCMI\n        DCD     Reserved79_IRQHandler       ; [79] Reserved\n        DCD     RNG_IRQHandler              ; [80] Rng\n        DCD     FPU_IRQHandler              ; [81] FPU\n        DCD     UART7_IRQHandler            ; [82] UART7\n        DCD     UART8_IRQHandler            ; [83] UART8\n        DCD     SPI4_IRQHandler             ; [84] SPI4\n        DCD     SPI5_IRQHandler             ; [85] SPI5\n        DCD     SPI6_IRQHandler             ; [86] SPI6\n        DCD     SAI1_IRQHandler             ; [87] SAI1\n        DCD     LTDC_IRQHandler             ; [88] LTDC\n        DCD     LTDC_ER_IRQHandler          ; [89] LTDC error\n        DCD     DMA2D_IRQHandler            ; [90] DMA2D\n        DCD     SAI2_IRQHandler             ; [91] SAI2\n        DCD     QUADSPI_IRQHandler          ; [92] QUADSPI\n        DCD     LPTIM1_IRQHandler           ; [93] LPTIM1\n        DCD     CEC_IRQHandler              ; [94] HDMI_CEC\n        DCD     I2C4_EV_IRQHandler          ; [95] I2C4 Event\n        DCD     I2C4_ER_IRQHandler          ; [96] I2C4 Error\n        DCD     SPDIF_RX_IRQHandler         ; [97] SPDIF_RX\n        DCD     OTG_FS_EP1_OUT_IRQHandler   ; [98] USB OTG FS End Point 1 Out\n        DCD     OTG_FS_EP1_IN_IRQHandler    ; [99] USB OTG FS End Point 1 In\n        DCD     OTG_FS_WKUP_IRQHandler      ; [100] USB OTG FS Wakeup through EXTI\n        DCD     OTG_FS_IRQHandler           ; [101] USB OTG FS\n        DCD     DMAMUX1_OVR_IRQHandler      ; [102] DMAMUX1 Overrun interrupt\n        DCD     HRTIM1_Master_IRQHandler    ; [103] HRTIM Master Timer global Interrupts\n        DCD     HRTIM1_TIMA_IRQHandler      ; [104] HRTIM Timer A global Interrupt\n        DCD     HRTIM1_TIMB_IRQHandler      ; [105] HRTIM Timer B global Interrupt\n        DCD     HRTIM1_TIMC_IRQHandler      ; [106] HRTIM Timer C global Interrupt\n        DCD     HRTIM1_TIMD_IRQHandler      ; [107] HRTIM Timer D global Interrupt\n        DCD     HRTIM1_TIME_IRQHandler      ; [108] HRTIM Timer E global Interrupt\n        DCD     HRTIM1_FLT_IRQHandler       ; [109] HRTIM Fault global Interrupt\n        DCD     DFSDM1_FLT0_IRQHandler      ; [110] DFSDM Filter0 Interrupt\n        DCD     DFSDM1_FLT1_IRQHandler      ; [111] DFSDM Filter1 Interrupt\n        DCD     DFSDM1_FLT2_IRQHandler      ; [112] DFSDM Filter2 Interrupt\n        DCD     DFSDM1_FLT3_IRQHandler      ; [113] DFSDM Filter3 Interrupt\n        DCD     SAI3_IRQHandler             ; [114] SAI3 global Interrupt\n        DCD     SWPMI1_IRQHandler           ; [115] Serial Wire Interface 1 global interrupt\n        DCD     TIM15_IRQHandler            ; [116] TIM15 global Interrupt\n        DCD     TIM16_IRQHandler            ; [117] TIM16 global Interrupt\n        DCD     TIM17_IRQHandler            ; [118] TIM17 global Interrupt\n        DCD     MDIOS_WKUP_IRQHandler       ; [119] MDIOS Wakeup  Interrupt\n        DCD     MDIOS_IRQHandler            ; [120] MDIOS global Interrupt\n        DCD     JPEG_IRQHandler             ; [121] JPEG global Interrupt\n        DCD     MDMA_IRQHandler             ; [122] MDMA global Interrupt\n        DCD     Reserved123_IRQHandler      ; [123] Reserved\n        DCD     SDMMC2_IRQHandler           ; [124] SDMMC2 global Interrupt\n        DCD     HSEM1_IRQHandler            ; [125] HSEM1 global Interrupt\n        DCD     Reserved126_IRQHandler      ; [126] Reserved\n        DCD     ADC3_IRQHandler             ; [127] ADC3 global Interrupt\n        DCD     DMAMUX2_OVR_IRQHandler      ; [128] DMAMUX Overrun interrupt\n        DCD     BDMA_Channel0_IRQHandler    ; [129] BDMA Channel 0 global Interrupt\n        DCD     BDMA_Channel1_IRQHandler    ; [130] BDMA Channel 1 global Interrupt\n        DCD     BDMA_Channel2_IRQHandler    ; [131] BDMA Channel 2 global Interrupt\n        DCD     BDMA_Channel3_IRQHandler    ; [132] BDMA Channel 3 global Interrupt\n        DCD     BDMA_Channel4_IRQHandler    ; [133] BDMA Channel 4 global Interrupt\n        DCD     BDMA_Channel5_IRQHandler    ; [134] BDMA Channel 5 global Interrupt\n        DCD     BDMA_Channel6_IRQHandler    ; [135] BDMA Channel 6 global Interrupt\n        DCD     BDMA_Channel7_IRQHandler    ; [136] BDMA Channel 7 global Interrupt\n        DCD     COMP1_IRQHandler            ; [137] COMP1 global Interrupt\n        DCD     LPTIM2_IRQHandler           ; [138] LP TIM2 global interrupt\n        DCD     LPTIM3_IRQHandler           ; [139] LP TIM3 global interrupt\n        DCD     LPTIM4_IRQHandler           ; [140] LP TIM4 global interrupt\n        DCD     LPTIM5_IRQHandler           ; [141] LP TIM5 global interrupt\n        DCD     LPUART1_IRQHandler          ; [142] LP UART1 interrupt\n        DCD     Reserved143_IRQHandler      ; [143] Reserved\n        DCD     CRS_IRQHandler              ; [144] Clock Recovery Global Interrupt\n        DCD     Reserved145_IRQHandler      ; [145] Reserved\n        DCD     SAI4_IRQHandler             ; [146] SAI4 global interrupt\n        DCD     Reserved147_IRQHandler      ; [147] Reserved\n        DCD     Reserved148_IRQHandler      ; [148] Reserved\n        DCD     WAKEUP_PIN_IRQHandler       ; [149] Interrupt for all 6 wake-up pins\n\n__Vectors_End\n\n__Vectors_Size  EQU   __Vectors_End - __Vectors\n\n\n;******************************************************************************\n; This is the code for exception handlers.\n;\n        AREA    |.text|, CODE, READONLY\n\n;******************************************************************************\n; This is the code that gets called when the processor first starts execution\n; following a reset event.\n;\nReset_Handler   PROC\n        EXPORT  Reset_Handler  [WEAK]\n        IMPORT  SystemInit\n        IMPORT  __main\n        IMPORT  assert_failed\n\n        LDR     r0,=SystemInit  ; CMSIS system initialization\n        BLX     r0\n\n        ; Call the C library enty point that handles startup. This will copy\n        ; the .data section initializers from flash to SRAM and zero fill the\n        ; .bss section.\n        ; NOTE: The __main function clears the C stack as well\n        LDR     r0,=__main\n        BX      r0\n\n        ; __main calls the main() function, which should not return,\n        ; but just in case jump to assert_failed() if main returns.\n        LDR     r0,=str_EXIT\n        MOVS    r1,#1\n        LDR     r2,=__initial_sp  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_EXIT\n        DCB     \"EXIT\"\n        ALIGN\n        ENDP\n\n;******************************************************************************\nNMI_Handler     PROC\n        EXPORT  NMI_Handler     [WEAK]\n        IMPORT  assert_failed\n        LDR     r0,=str_NMI\n        MOVS    r1,#1\n        LDR     r2,=__initial_sp  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_NMI\n        DCB     \"NMI\"\n        ALIGN\n        ENDP\n\n;******************************************************************************\nHardFault_Handler PROC\n        EXPORT  HardFault_Handler [WEAK]\n        IMPORT  assert_failed\n        LDR     r0,=str_HardFault\n        MOVS    r1,#1\n        LDR     r2,=__initial_sp  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_HardFault\n        DCB     \"HardFault\"\n        ALIGN\n        ENDP\n\n;******************************************************************************\nMemManage_Handler PROC\n        EXPORT  MemManage_Handler     [WEAK]\n        IMPORT  assert_failed\n        LDR     r0,=str_MemManage\n        MOVS    r1,#1\n        LDR     r2,=__initial_sp  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_MemManage\n        DCB     \"MemManage\"\n        ALIGN\n        ENDP\n\n;******************************************************************************\nBusFault_Handler PROC\n        EXPORT  BusFault_Handler     [WEAK]\n        IMPORT  assert_failed\n        LDR     r0,=str_BusFault\n        MOVS    r1,#1\n        LDR     r2,=__initial_sp  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_BusFault\n        DCB     \"BusFault\"\n        ALIGN\n        ENDP\n\n;******************************************************************************\nUsageFault_Handler PROC\n        EXPORT  UsageFault_Handler   [WEAK]\n        IMPORT  assert_failed\n        LDR     r0,=str_UsageFault\n        MOVS    r1,#1\n        LDR     r2,=__initial_sp  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_UsageFault\n        DCB     \"UsageFault\"\n        ALIGN\n        ENDP\n\n\n;******************************************************************************\n;\n; Weak non-fault handlers...\n;\n\n;******************************************************************************\nSVC_Handler PROC\n        EXPORT  SVC_Handler   [WEAK]\n        IMPORT  assert_failed\n        LDR     r0,=str_SVC\n        MOVS    r1,#1\n        LDR     r2,=__initial_sp  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_SVC\n        DCB     \"SVC\"\n        ALIGN\n        ENDP\n\n;******************************************************************************\nDebugMon_Handler PROC\n        EXPORT  DebugMon_Handler     [WEAK]\n        IMPORT  assert_failed\n        LDR     r0,=str_DebugMon\n        MOVS    r1,#1\n        LDR     r2,=__initial_sp  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_DebugMon\n        DCB     \"DebugMon\"\n        ALIGN\n        ENDP\n\n;******************************************************************************\nPendSV_Handler PROC\n        EXPORT  PendSV_Handler       [WEAK]\n        IMPORT  assert_failed\n        LDR     r0,=str_PendSV\n        MOVS    r1,#1\n        LDR     r2,=__initial_sp  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_PendSV\n        DCB     \"PendSV\"\n        ALIGN\n        ENDP\n\n;******************************************************************************\nSysTick_Handler PROC\n        EXPORT  SysTick_Handler     [WEAK]\n        IMPORT  assert_failed\n        LDR     r0,=str_SysTick\n        MOVS    r1,#1\n        LDR     r2,=__initial_sp  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_SysTick\n        DCB     \"SysTick\"\n        ALIGN\n        ENDP\n\n;******************************************************************************\nDefault_Handler PROC\n        EXPORT  WWDG_IRQHandler               [WEAK]\n        EXPORT  PVD_AVD_IRQHandler            [WEAK]\n        EXPORT  TAMP_STAMP_IRQHandler         [WEAK]\n        EXPORT  RTC_WKUP_IRQHandler           [WEAK]\n        EXPORT  FLASH_IRQHandler              [WEAK]\n        EXPORT  RCC_IRQHandler                [WEAK]\n        EXPORT  EXTI0_IRQHandler              [WEAK]\n        EXPORT  EXTI1_IRQHandler              [WEAK]\n        EXPORT  EXTI2_IRQHandler              [WEAK]\n        EXPORT  EXTI3_IRQHandler              [WEAK]\n        EXPORT  EXTI4_IRQHandler              [WEAK]\n        EXPORT  DMA1_Stream0_IRQHandler       [WEAK]\n        EXPORT  DMA1_Stream1_IRQHandler       [WEAK]\n        EXPORT  DMA1_Stream2_IRQHandler       [WEAK]\n        EXPORT  DMA1_Stream3_IRQHandler       [WEAK]\n        EXPORT  DMA1_Stream4_IRQHandler       [WEAK]\n        EXPORT  DMA1_Stream5_IRQHandler       [WEAK]\n        EXPORT  DMA1_Stream6_IRQHandler       [WEAK]\n        EXPORT  ADC_IRQHandler                [WEAK]\n        EXPORT  FDCAN1_IT0_IRQHandler         [WEAK]\n        EXPORT  FDCAN2_IT0_IRQHandler         [WEAK]\n        EXPORT  FDCAN1_IT1_IRQHandler         [WEAK]\n        EXPORT  FDCAN2_IT1_IRQHandler         [WEAK]\n        EXPORT  EXTI9_5_IRQHandler            [WEAK]\n        EXPORT  TIM1_BRK_IRQHandler           [WEAK]\n        EXPORT  TIM1_UP_IRQHandler            [WEAK]\n        EXPORT  TIM1_TRG_COM_IRQHandler       [WEAK]\n        EXPORT  TIM1_CC_IRQHandler            [WEAK]\n        EXPORT  TIM2_IRQHandler               [WEAK]\n        EXPORT  TIM3_IRQHandler               [WEAK]\n        EXPORT  TIM4_IRQHandler               [WEAK]\n        EXPORT  I2C1_EV_IRQHandler            [WEAK]\n        EXPORT  I2C1_ER_IRQHandler            [WEAK]\n        EXPORT  I2C2_EV_IRQHandler            [WEAK]\n        EXPORT  I2C2_ER_IRQHandler            [WEAK]\n        EXPORT  SPI1_IRQHandler               [WEAK]\n        EXPORT  SPI2_IRQHandler               [WEAK]\n        EXPORT  USART1_IRQHandler             [WEAK]\n        EXPORT  USART2_IRQHandler             [WEAK]\n        EXPORT  USART3_IRQHandler             [WEAK]\n        EXPORT  EXTI15_10_IRQHandler          [WEAK]\n        EXPORT  RTC_Alarm_IRQHandler          [WEAK]\n        EXPORT  TIM8_BRK_TIM12_IRQHandler     [WEAK]\n        EXPORT  TIM8_UP_TIM13_IRQHandler      [WEAK]\n        EXPORT  TIM8_TRG_COM_TIM14_IRQHandler [WEAK]\n        EXPORT  TIM8_CC_IRQHandler            [WEAK]\n        EXPORT  DMA1_Stream7_IRQHandler       [WEAK]\n        EXPORT  FMC_IRQHandler                [WEAK]\n        EXPORT  SDMMC1_IRQHandler             [WEAK]\n        EXPORT  TIM5_IRQHandler               [WEAK]\n        EXPORT  SPI3_IRQHandler               [WEAK]\n        EXPORT  UART4_IRQHandler              [WEAK]\n        EXPORT  UART5_IRQHandler              [WEAK]\n        EXPORT  TIM6_DAC_IRQHandler           [WEAK]\n        EXPORT  TIM7_IRQHandler               [WEAK]\n        EXPORT  DMA2_Stream0_IRQHandler       [WEAK]\n        EXPORT  DMA2_Stream1_IRQHandler       [WEAK]\n        EXPORT  DMA2_Stream2_IRQHandler       [WEAK]\n        EXPORT  DMA2_Stream3_IRQHandler       [WEAK]\n        EXPORT  DMA2_Stream4_IRQHandler       [WEAK]\n        EXPORT  ETH_IRQHandler                [WEAK]\n        EXPORT  ETH_WKUP_IRQHandler           [WEAK]\n        EXPORT  FDCAN_CAL_IRQHandler          [WEAK]\n        EXPORT  DMA2_Stream5_IRQHandler       [WEAK]\n        EXPORT  DMA2_Stream6_IRQHandler       [WEAK]\n        EXPORT  DMA2_Stream7_IRQHandler       [WEAK]\n        EXPORT  USART6_IRQHandler             [WEAK]\n        EXPORT  I2C3_EV_IRQHandler            [WEAK]\n        EXPORT  I2C3_ER_IRQHandler            [WEAK]\n        EXPORT  OTG_HS_EP1_OUT_IRQHandler     [WEAK]\n        EXPORT  OTG_HS_EP1_IN_IRQHandler      [WEAK]\n        EXPORT  OTG_HS_WKUP_IRQHandler        [WEAK]\n        EXPORT  OTG_HS_IRQHandler             [WEAK]\n        EXPORT  DCMI_IRQHandler               [WEAK]\n        EXPORT  RNG_IRQHandler                [WEAK]\n        EXPORT  FPU_IRQHandler                [WEAK]\n        EXPORT  UART7_IRQHandler              [WEAK]\n        EXPORT  UART8_IRQHandler              [WEAK]\n        EXPORT  SPI4_IRQHandler               [WEAK]\n        EXPORT  SPI5_IRQHandler               [WEAK]\n        EXPORT  SPI6_IRQHandler               [WEAK]\n        EXPORT  SAI1_IRQHandler               [WEAK]\n        EXPORT  LTDC_IRQHandler               [WEAK]\n        EXPORT  LTDC_ER_IRQHandler            [WEAK]\n        EXPORT  DMA2D_IRQHandler              [WEAK]\n        EXPORT  SAI2_IRQHandler               [WEAK]\n        EXPORT  QUADSPI_IRQHandler            [WEAK]\n        EXPORT  LPTIM1_IRQHandler             [WEAK]\n        EXPORT  CEC_IRQHandler                [WEAK]\n        EXPORT  I2C4_EV_IRQHandler            [WEAK]\n        EXPORT  I2C4_ER_IRQHandler            [WEAK]\n        EXPORT  SPDIF_RX_IRQHandler           [WEAK]\n        EXPORT  OTG_FS_EP1_OUT_IRQHandler     [WEAK]\n        EXPORT  OTG_FS_EP1_IN_IRQHandler      [WEAK]\n        EXPORT  OTG_FS_WKUP_IRQHandler        [WEAK]\n        EXPORT  OTG_FS_IRQHandler             [WEAK]\n        EXPORT  DMAMUX1_OVR_IRQHandler        [WEAK]\n        EXPORT  HRTIM1_Master_IRQHandler      [WEAK]\n        EXPORT  HRTIM1_TIMA_IRQHandler        [WEAK]\n        EXPORT  HRTIM1_TIMB_IRQHandler        [WEAK]\n        EXPORT  HRTIM1_TIMC_IRQHandler        [WEAK]\n        EXPORT  HRTIM1_TIMD_IRQHandler        [WEAK]\n        EXPORT  HRTIM1_TIME_IRQHandler        [WEAK]\n        EXPORT  HRTIM1_FLT_IRQHandler         [WEAK]\n        EXPORT  DFSDM1_FLT0_IRQHandler        [WEAK]\n        EXPORT  DFSDM1_FLT1_IRQHandler        [WEAK]\n        EXPORT  DFSDM1_FLT2_IRQHandler        [WEAK]\n        EXPORT  DFSDM1_FLT3_IRQHandler        [WEAK]\n        EXPORT  SAI3_IRQHandler               [WEAK]\n        EXPORT  SWPMI1_IRQHandler             [WEAK]\n        EXPORT  TIM15_IRQHandler              [WEAK]\n        EXPORT  TIM16_IRQHandler              [WEAK]\n        EXPORT  TIM17_IRQHandler              [WEAK]\n        EXPORT  MDIOS_WKUP_IRQHandler         [WEAK]\n        EXPORT  MDIOS_IRQHandler              [WEAK]\n        EXPORT  JPEG_IRQHandler               [WEAK]\n        EXPORT  MDMA_IRQHandler               [WEAK]\n        EXPORT  SDMMC2_IRQHandler             [WEAK]\n        EXPORT  HSEM1_IRQHandler              [WEAK]\n        EXPORT  ADC3_IRQHandler               [WEAK]\n        EXPORT  DMAMUX2_OVR_IRQHandler        [WEAK]\n        EXPORT  BDMA_Channel0_IRQHandler      [WEAK]\n        EXPORT  BDMA_Channel1_IRQHandler      [WEAK]\n        EXPORT  BDMA_Channel2_IRQHandler      [WEAK]\n        EXPORT  BDMA_Channel3_IRQHandler      [WEAK]\n        EXPORT  BDMA_Channel4_IRQHandler      [WEAK]\n        EXPORT  BDMA_Channel5_IRQHandler      [WEAK]\n        EXPORT  BDMA_Channel6_IRQHandler      [WEAK]\n        EXPORT  BDMA_Channel7_IRQHandler      [WEAK]\n        EXPORT  COMP1_IRQHandler              [WEAK]\n        EXPORT  LPTIM2_IRQHandler             [WEAK]\n        EXPORT  LPTIM3_IRQHandler             [WEAK]\n        EXPORT  LPTIM4_IRQHandler             [WEAK]\n        EXPORT  LPTIM5_IRQHandler             [WEAK]\n        EXPORT  LPUART1_IRQHandler            [WEAK]\n        EXPORT  CRS_IRQHandler                [WEAK]\n        EXPORT  SAI4_IRQHandler               [WEAK]\n        EXPORT  WAKEUP_PIN_IRQHandler         [WEAK]\n        EXPORT  Reserved42_IRQHandler         [WEAK]\n        EXPORT  Reserved64_IRQHandler         [WEAK]\n        EXPORT  Reserved65_IRQHandler         [WEAK]\n        EXPORT  Reserved66_IRQHandler         [WEAK]\n        EXPORT  Reserved67_IRQHandler         [WEAK]\n        EXPORT  Reserved79_IRQHandler         [WEAK]\n        EXPORT  Reserved124_IRQHandler        [WEAK]\n        EXPORT  Reserved123_IRQHandler        [WEAK]\n        EXPORT  Reserved126_IRQHandler        [WEAK]\n        EXPORT  Reserved143_IRQHandler        [WEAK]\n        EXPORT  Reserved145_IRQHandler        [WEAK]\n        EXPORT  Reserved147_IRQHandler        [WEAK]\n        EXPORT  Reserved148_IRQHandler        [WEAK]\n\nWWDG_IRQHandler\nPVD_AVD_IRQHandler\nTAMP_STAMP_IRQHandler\nRTC_WKUP_IRQHandler\nFLASH_IRQHandler\nRCC_IRQHandler\nEXTI0_IRQHandler\nEXTI1_IRQHandler\nEXTI2_IRQHandler\nEXTI3_IRQHandler\nEXTI4_IRQHandler\nDMA1_Stream0_IRQHandler\nDMA1_Stream1_IRQHandler\nDMA1_Stream2_IRQHandler\nDMA1_Stream3_IRQHandler\nDMA1_Stream4_IRQHandler\nDMA1_Stream5_IRQHandler\nDMA1_Stream6_IRQHandler\nADC_IRQHandler\nFDCAN1_IT0_IRQHandler\nFDCAN2_IT0_IRQHandler\nFDCAN1_IT1_IRQHandler\nFDCAN2_IT1_IRQHandler\nEXTI9_5_IRQHandler\nTIM1_BRK_IRQHandler\nTIM1_UP_IRQHandler\nTIM1_TRG_COM_IRQHandler\nTIM1_CC_IRQHandler\nTIM2_IRQHandler\nTIM3_IRQHandler\nTIM4_IRQHandler\nI2C1_EV_IRQHandler\nI2C1_ER_IRQHandler\nI2C2_EV_IRQHandler\nI2C2_ER_IRQHandler\nSPI1_IRQHandler\nSPI2_IRQHandler\nUSART1_IRQHandler\nUSART2_IRQHandler\nUSART3_IRQHandler\nEXTI15_10_IRQHandler\nRTC_Alarm_IRQHandler\nTIM8_BRK_TIM12_IRQHandler\nTIM8_UP_TIM13_IRQHandler\nTIM8_TRG_COM_TIM14_IRQHandler\nTIM8_CC_IRQHandler\nDMA1_Stream7_IRQHandler\nFMC_IRQHandler\nSDMMC1_IRQHandler\nTIM5_IRQHandler\nSPI3_IRQHandler\nUART4_IRQHandler\nUART5_IRQHandler\nTIM6_DAC_IRQHandler\nTIM7_IRQHandler\nDMA2_Stream0_IRQHandler\nDMA2_Stream1_IRQHandler\nDMA2_Stream2_IRQHandler\nDMA2_Stream3_IRQHandler\nDMA2_Stream4_IRQHandler\nETH_IRQHandler\nETH_WKUP_IRQHandler\nFDCAN_CAL_IRQHandler\nDMA2_Stream5_IRQHandler\nDMA2_Stream6_IRQHandler\nDMA2_Stream7_IRQHandler\nUSART6_IRQHandler\nI2C3_EV_IRQHandler\nI2C3_ER_IRQHandler\nOTG_HS_EP1_OUT_IRQHandler\nOTG_HS_EP1_IN_IRQHandler\nOTG_HS_WKUP_IRQHandler\nOTG_HS_IRQHandler\nDCMI_IRQHandler\nRNG_IRQHandler\nFPU_IRQHandler\nUART7_IRQHandler\nUART8_IRQHandler\nSPI4_IRQHandler\nSPI5_IRQHandler\nSPI6_IRQHandler\nSAI1_IRQHandler\nLTDC_IRQHandler\nLTDC_ER_IRQHandler\nDMA2D_IRQHandler\nSAI2_IRQHandler\nQUADSPI_IRQHandler\nLPTIM1_IRQHandler\nCEC_IRQHandler\nI2C4_EV_IRQHandler\nI2C4_ER_IRQHandler\nSPDIF_RX_IRQHandler\nOTG_FS_EP1_OUT_IRQHandler\nOTG_FS_EP1_IN_IRQHandler\nOTG_FS_WKUP_IRQHandler\nOTG_FS_IRQHandler\nDMAMUX1_OVR_IRQHandler\nHRTIM1_Master_IRQHandler\nHRTIM1_TIMA_IRQHandler\nHRTIM1_TIMB_IRQHandler\nHRTIM1_TIMC_IRQHandler\nHRTIM1_TIMD_IRQHandler\nHRTIM1_TIME_IRQHandler\nHRTIM1_FLT_IRQHandler\nDFSDM1_FLT0_IRQHandler\nDFSDM1_FLT1_IRQHandler\nDFSDM1_FLT2_IRQHandler\nDFSDM1_FLT3_IRQHandler\nSAI3_IRQHandler\nSWPMI1_IRQHandler\nTIM15_IRQHandler\nTIM16_IRQHandler\nTIM17_IRQHandler\nMDIOS_WKUP_IRQHandler\nMDIOS_IRQHandler\nJPEG_IRQHandler\nMDMA_IRQHandler\nSDMMC2_IRQHandler\nHSEM1_IRQHandler\nADC3_IRQHandler\nDMAMUX2_OVR_IRQHandler\nBDMA_Channel0_IRQHandler\nBDMA_Channel1_IRQHandler\nBDMA_Channel2_IRQHandler\nBDMA_Channel3_IRQHandler\nBDMA_Channel4_IRQHandler\nBDMA_Channel5_IRQHandler\nBDMA_Channel6_IRQHandler\nBDMA_Channel7_IRQHandler\nCOMP1_IRQHandler\nLPTIM2_IRQHandler\nLPTIM3_IRQHandler\nLPTIM4_IRQHandler\nLPTIM5_IRQHandler\nLPUART1_IRQHandler\nCRS_IRQHandler\nSAI4_IRQHandler\nWAKEUP_PIN_IRQHandler\nReserved42_IRQHandler\nReserved64_IRQHandler\nReserved65_IRQHandler\nReserved66_IRQHandler\nReserved67_IRQHandler\nReserved79_IRQHandler\nReserved124_IRQHandler\nReserved123_IRQHandler\nReserved126_IRQHandler\nReserved143_IRQHandler\nReserved145_IRQHandler\nReserved147_IRQHandler\nReserved148_IRQHandler\n        IMPORT  assert_failed\n        LDR     r0,=str_Undefined\n        MOVS    r1,#1\n        LDR     r2,=__initial_sp  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_Undefined\n        DCB     \"Undefined\"\n        ALIGN\n        ENDP\n\n        ALIGN               ; make sure the end of this section is aligned\n\n;******************************************************************************\n; The function expected of the C library startup code for defining the stack\n; and heap memory locations.  For the C library version of the startup code,\n; provide this function so that the C library initialization code can find out\n; the location of the stack and heap.\n;\n    IF :DEF: __MICROLIB\n        EXPORT  __initial_sp\n        EXPORT  __stack_limit\n        EXPORT  __heap_base\n        EXPORT  __heap_limit\n    ELSE\n        IMPORT  __use_two_region_memory\n        EXPORT  __user_initial_stackheap\n\n__user_initial_stackheap PROC\n        LDR     R0, =__heap_base\n        LDR     R1, =__stack_limit\n        LDR     R2, =__heap_limit\n        LDR     R3, =__stack_base\n        BX      LR\n        ENDP\n    ENDIF\n        ALIGN               ; make sure the end of this section is aligned\n\n    END                     ; end of module\n\n"
  },
  {
    "path": "3rd_party/nucleo-h743zi/gnu/nucleo-h743zi.ld",
    "content": "/*****************************************************************************\n* Product: Linker script for STM32H743xx, GNU-ARM linker\n* Last Updated for Version: 6.1.0\n* Date of the Last Update:  2018-01-30\n*\n*                    Q u a n t u m     L e a P s\n*                    ---------------------------\n*                    innovating embedded systems\n*\n* Copyright (C) Quantum Leaps, LLC. All rights reserved.\n*\n* This program is open source software: you can redistribute it and/or\n* modify it under the terms of the GNU General Public License as published\n* by the Free Software Foundation, either version 3 of the License, or\n* (at your option) any later version.\n*\n* Alternatively, this program may be distributed and modified under the\n* terms of Quantum Leaps commercial licenses, which expressly supersede\n* the GNU General Public License and are specifically designed for\n* licensees interested in retaining the proprietary status of their code.\n*\n* This program is distributed in the hope that it will be useful,\n* but WITHOUT ANY WARRANTY; without even the implied warranty of\n* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n* GNU General Public License for more details.\n*\n* You should have received a copy of the GNU General Public License\n* along with this program. If not, see <http://www.gnu.org/licenses/>.\n*\n* Contact information:\n* https://state-machine.com\n* mailto:info@state-machine.com\n*****************************************************************************/\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nENTRY(Reset_Handler) /* entry Point */\n\nMEMORY { /* memory map of STM32F746NG */\n    ROM (rx)  : ORIGIN = 0x08000000, LENGTH = 2048K\n    RAM (xrw) : ORIGIN = 0x24000000, LENGTH = 512K\n}\n\n/* The size of the stack used by the application. NOTE: you need to adjust  */\nSTACK_SIZE = 2048;\n\n/* The size of the heap used by the application. NOTE: you need to adjust   */\nHEAP_SIZE = 0;\n\nSECTIONS {\n\n    .isr_vector : {        /* the vector table goes FIRST into ROM */\n        KEEP(*(.isr_vector)) /* vector table */\n        . = ALIGN(4);\n    } >ROM\n\n    .text : {              /* code and constants */\n        . = ALIGN(4);\n        *(.text)           /* .text sections (code) */\n        *(.text*)          /* .text* sections (code) */\n        *(.rodata)         /* .rodata sections (constants, strings, etc.) */\n        *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */\n\n        KEEP (*(.init))\n        KEEP (*(.fini))\n\n        . = ALIGN(4);\n    } >ROM\n\n    .preinit_array : {\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP (*(.preinit_array*))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n    } >ROM\n\n    .init_array : {\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array*))\n        PROVIDE_HIDDEN (__init_array_end = .);\n    } >ROM\n\n    .fini_array : {\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP (*(.fini_array*))\n        KEEP (*(SORT(.fini_array.*)))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n    } >ROM\n\n    _etext = .;            /* global symbols at end of code */\n\n    .stack : {\n        __stack_start__ = .;\n        . = . + STACK_SIZE;\n        . = ALIGN(4);\n        __stack_end__ = .;\n    } >RAM\n\n    .data :  AT (_etext) {\n        __data_load = LOADADDR (.data);\n        __data_start = .;\n        *(.data)           /* .data sections */\n        *(.data*)          /* .data* sections */\n        . = ALIGN(4);\n        __data_end__ = .;\n        _edata = __data_end__;\n    } >RAM\n\n    .bss : {\n        __bss_start__ = .;\n        *(.bss)\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = .;         /* define a global symbol at bss end */\n        __bss_end__ = .;\n    } >RAM\n\n    __exidx_start = .;\n    .ARM.exidx   : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } >RAM\n    __exidx_end = .;\n\n    PROVIDE ( end = _ebss );\n    PROVIDE ( _end = _ebss );\n    PROVIDE ( __end__ = _ebss );\n\n    .heap : {\n        __heap_start__ = .;\n        . = . + HEAP_SIZE;\n        . = ALIGN(4);\n        __heap_end__ = .;\n    } >RAM\n\n    /* Remove information from the standard libraries */\n    /DISCARD/ : {\n        libc.a ( * )\n        libm.a ( * )\n        libgcc.a ( * )\n    }\n}\n"
  },
  {
    "path": "3rd_party/nucleo-h743zi/gnu/startup_stm32h743xx.c",
    "content": "/* File: startup_stm32h743xx.c for GNU-ARM\n * Purpose: startup file for STM32H743xx Cortex-M7 device.\n *          Should be used with GCC 'GNU Tools ARM Embedded'\n * Version: CMSIS 5.0.1\n * Date: 2017-09-13\n *\n * Modified by Quantum Leaps:\n * - Added relocating of the Vector Table to free up the 256B region at 0x0\n *   for NULL-pointer protection by the MPU.\n * - Modified all exception handlers to branch to assert_failed()\n *   instead of locking up the CPU inside an endless loop.\n *\n * Created from the CMSIS template for the specified device\n * Quantum Leaps, www.state-machine.com\n *\n * NOTE:\n * The function assert_failed defined at the end of this file defines\n * the error/assertion handling policy for the application and might\n * need to be customized for each project. This function is defined in\n * assembly to re-set the stack pointer, in case it is corrupted by the\n * time assert_failed is called.\n */\n\n/* start and end of stack defined in the linker script ---------------------*/\n/*extern int __stack_start__;*/\nextern int __stack_end__;\n\n/* Weak prototypes for error handlers --------------------------------------*/\n/**\n* \\note\n* The function assert_failed defined at the end of this file defines\n* the error/assertion handling policy for the application and might\n* need to be customized for each project. This function is defined in\n* assembly to avoid accessing the stack, which might be corrupted by\n* the time assert_failed is called.\n*/\n__attribute__ ((naked, noreturn))\nvoid assert_failed(char const *module, int loc);\n\n/* Function prototypes -----------------------------------------------------*/\nvoid Default_Handler(void);  /* Default empty handler */\nvoid Reset_Handler(void);    /* Reset Handler */\nvoid SystemInit(void);       /* CMSIS system initialization */\n\n/*----------------------------------------------------------------------------\n* weak aliases for each Exception handler to the Default_Handler.\n* Any function with the same name will override these definitions.\n*/\n/* Cortex-M Processor fault exceptions... */\nvoid NMI_Handler           (void) __attribute__ ((weak));\nvoid HardFault_Handler     (void) __attribute__ ((weak));\nvoid MemManage_Handler     (void) __attribute__ ((weak));\nvoid BusFault_Handler      (void) __attribute__ ((weak));\nvoid UsageFault_Handler    (void) __attribute__ ((weak));\n\n/* Cortex-M Processor non-fault exceptions... */\nvoid SVC_Handler           (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n/* external interrupts...   */\nvoid WWDG_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PVD_AVD_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid TAMP_STAMP_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid RTC_WKUP_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid FLASH_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid RCC_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid EXTI0_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid EXTI1_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid EXTI2_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid EXTI3_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid EXTI4_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DMA1_Stream0_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DMA1_Stream1_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DMA1_Stream2_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DMA1_Stream3_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DMA1_Stream4_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DMA1_Stream5_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DMA1_Stream6_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid ADC_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid FDCAN1_IT0_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid FDCAN2_IT0_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid FDCAN1_IT1_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid FDCAN2_IT1_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid EXTI9_5_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid TIM1_BRK_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid TIM1_UP_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid TIM1_TRG_COM_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid TIM1_CC_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid TIM2_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid TIM3_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid TIM4_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid I2C1_EV_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid I2C1_ER_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid I2C2_EV_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid I2C2_ER_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SPI1_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SPI2_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid USART1_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid USART2_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid USART3_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid EXTI15_10_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid RTC_Alarm_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid TIM8_BRK_TIM12_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid TIM8_UP_TIM13_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid TIM8_TRG_COM_TIM14_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid TIM8_CC_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DMA1_Stream7_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid FMC_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SDMMC1_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid TIM5_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SPI3_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UART4_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UART5_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid TIM6_DAC_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid TIM7_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DMA2_Stream0_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DMA2_Stream1_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DMA2_Stream2_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DMA2_Stream3_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DMA2_Stream4_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid ETH_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid ETH_WKUP_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid FDCAN_CAL_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DMA2_Stream5_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DMA2_Stream6_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DMA2_Stream7_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid USART6_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid I2C3_EV_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid I2C3_ER_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid OTG_HS_EP1_OUT_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid OTG_HS_EP1_IN_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid OTG_HS_WKUP_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid OTG_HS_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DCMI_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid RNG_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid FPU_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UART7_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UART8_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SPI4_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SPI5_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SPI6_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SAI1_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid LTDC_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid LTDC_ER_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DMA2D_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SAI2_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid QUADSPI_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid LPTIM1_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid CEC_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid I2C4_EV_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid I2C4_ER_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SPDIF_RX_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid OTG_FS_EP1_OUT_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid OTG_FS_EP1_IN_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid OTG_FS_WKUP_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid OTG_FS_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DMAMUX1_OVR_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HRTIM1_Master_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HRTIM1_TIMA_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HRTIM1_TIMB_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HRTIM1_TIMC_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HRTIM1_TIMD_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HRTIM1_TIME_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HRTIM1_FLT_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DFSDM1_FLT0_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DFSDM1_FLT1_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DFSDM1_FLT2_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DFSDM1_FLT3_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SAI3_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SWPMI1_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid TIM15_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid TIM16_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid TIM17_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid MDIOS_WKUP_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid MDIOS_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid JPEG_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid MDMA_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SDMMC2_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HSEM1_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid ADC3_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DMAMUX2_OVR_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BDMA_Channel0_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BDMA_Channel1_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BDMA_Channel2_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BDMA_Channel3_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BDMA_Channel4_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BDMA_Channel5_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BDMA_Channel6_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BDMA_Channel7_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid COMP1_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid LPTIM2_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid LPTIM3_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid LPTIM4_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid LPTIM5_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid LPUART1_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid CRS_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SAI4_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid WAKEUP_PIN_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Reserved42_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Reserved64_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Reserved65_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Reserved66_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Reserved67_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Reserved79_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Reserved124_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Reserved123_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Reserved126_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Reserved143_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Reserved145_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Reserved147_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Reserved148_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n/*..........................................................................*/\n__attribute__ ((section(\".isr_vector\")))\nint const g_pfnVectors[] = {\n    (int)&__stack_end__,            /* Top of Stack                        */\n    (int)&Reset_Handler,            /* Reset Handler                       */\n    (int)&NMI_Handler,              /* NMI Handler                         */\n    (int)&HardFault_Handler,        /* Hard Fault Handler                  */\n    (int)&MemManage_Handler,        /* The MPU fault handler               */\n    (int)&BusFault_Handler,         /* The bus fault handler               */\n    (int)&UsageFault_Handler,       /* The usage fault handler             */\n    (int)&Default_Handler,          /* Reserved                            */\n    (int)&Default_Handler,          /* Reserved                            */\n    (int)&Default_Handler,          /* Reserved                            */\n    (int)&Default_Handler,          /* Reserved                            */\n    (int)&SVC_Handler,              /* SVCall handler                      */\n    (int)&DebugMon_Handler,         /* Debug monitor handler               */\n    (int)&Default_Handler,          /* Reserved                            */\n    (int)&PendSV_Handler,           /* The PendSV handler                  */\n    (int)&SysTick_Handler,          /* The SysTick handler                 */\n\n    /* IRQ handlers... */\n    (int)&WWDG_IRQHandler,          /* [ 0] Window WatchDog Interrupt ( wwdg1_it) */\n    (int)&PVD_AVD_IRQHandler,       /* [ 1] PVD/AVD through EXTI Line detection */\n    (int)&TAMP_STAMP_IRQHandler,    /* [ 2] Tamper and TimeStamps through EXTI line */\n    (int)&RTC_WKUP_IRQHandler,      /* [ 3] RTC Wakeup through the EXTI line */\n    (int)&FLASH_IRQHandler,         /* [ 4] FLASH */\n    (int)&RCC_IRQHandler,           /* [ 5] RCC */\n    (int)&EXTI0_IRQHandler,         /* [ 6] EXTI Line0 */\n    (int)&EXTI1_IRQHandler,         /* [ 7] EXTI Line1 */\n    (int)&EXTI2_IRQHandler,         /* [ 8] EXTI Line2 */\n    (int)&EXTI3_IRQHandler,         /* [ 9] EXTI Line3 */\n    (int)&EXTI4_IRQHandler,         /* [10] EXTI Line4 */\n    (int)&DMA1_Stream0_IRQHandler,  /* [11] DMA1 Stream 0 */\n    (int)&DMA1_Stream1_IRQHandler,  /* [12] DMA1 Stream 1 */\n    (int)&DMA1_Stream2_IRQHandler,  /* [13] DMA1 Stream 2 */\n    (int)&DMA1_Stream3_IRQHandler,  /* [14] DMA1 Stream 3 */\n    (int)&DMA1_Stream4_IRQHandler,  /* [15] DMA1 Stream 4 */\n    (int)&DMA1_Stream5_IRQHandler,  /* [16] DMA1 Stream 5 */\n    (int)&DMA1_Stream6_IRQHandler,  /* [17] DMA1 Stream 6 */\n    (int)&ADC_IRQHandler,           /* [18] ADC1, ADC2 */\n    (int)&FDCAN1_IT0_IRQHandler,    /* [19] FDCAN1 interrupt line 0 */\n    (int)&FDCAN2_IT0_IRQHandler,    /* [20] FDCAN2 interrupt line 0 */\n    (int)&FDCAN1_IT1_IRQHandler,    /* [21] FDCAN1 interrupt line 1 */\n    (int)&FDCAN2_IT1_IRQHandler,    /* [22] FDCAN2 interrupt line 1 */\n    (int)&EXTI9_5_IRQHandler,       /* [23] External Line[9:5]s */\n    (int)&TIM1_BRK_IRQHandler,      /* [24] TIM1 Break interrupt */\n    (int)&TIM1_UP_IRQHandler,       /* [25] TIM1 Update */\n    (int)&TIM1_TRG_COM_IRQHandler,  /* [26] TIM1 Trigger and Commutation Interrupt */\n    (int)&TIM1_CC_IRQHandler,       /* [27] TIM1 Capture Compare */\n    (int)&TIM2_IRQHandler,          /* [28] TIM2 */\n    (int)&TIM3_IRQHandler,          /* [29] TIM3 */\n    (int)&TIM4_IRQHandler,          /* [30] TIM4 */\n    (int)&I2C1_EV_IRQHandler,       /* [31] I2C1 Event */\n    (int)&I2C1_ER_IRQHandler,       /* [32] I2C1 Error */\n    (int)&I2C2_EV_IRQHandler,       /* [33] I2C2 Event */\n    (int)&I2C2_ER_IRQHandler,       /* [34] I2C2 Error */\n    (int)&SPI1_IRQHandler,          /* [35] SPI1 */\n    (int)&SPI2_IRQHandler,          /* [36] SPI2 */\n    (int)&USART1_IRQHandler,        /* [37] USART1 */\n    (int)&USART2_IRQHandler,        /* [38] USART2 */\n    (int)&USART3_IRQHandler,        /* [39] USART3 */\n    (int)&EXTI15_10_IRQHandler,     /* [40] External Line[15:10] */\n    (int)&RTC_Alarm_IRQHandler,     /* [41] RTC Alarm (A and B) through EXTI Line */\n    (int)&Reserved42_IRQHandler,    /* [42] Reserved */\n    (int)&TIM8_BRK_TIM12_IRQHandler,/* [43] TIM8 Break Interrupt and TIM12 global interrupt */\n    (int)&TIM8_UP_TIM13_IRQHandler, /* [44] TIM8 Update Interrupt and TIM13 global interrupt */\n    (int)&TIM8_TRG_COM_TIM14_IRQHandler,/* [45] TIM8 Trigger and Commutation Interrupt and TIM14 glob */\n    (int)&TIM8_CC_IRQHandler,       /* [46] TIM8 Capture Compare Interrupt */\n    (int)&DMA1_Stream7_IRQHandler,  /* [47] DMA1 Stream7 */\n    (int)&FMC_IRQHandler,           /* [48] FMC */\n    (int)&SDMMC1_IRQHandler,        /* [49] SDMMC1 */\n    (int)&TIM5_IRQHandler,          /* [50] TIM5 */\n    (int)&SPI3_IRQHandler,          /* [51] SPI3 */\n    (int)&UART4_IRQHandler,         /* [52] UART4 */\n    (int)&UART5_IRQHandler,         /* [53] UART5 */\n    (int)&TIM6_DAC_IRQHandler,      /* [54] TIM6 and DAC1&2 underrun errors */\n    (int)&TIM7_IRQHandler,          /* [55] TIM7 */\n    (int)&DMA2_Stream0_IRQHandler,  /* [56] DMA2 Stream 0 */\n    (int)&DMA2_Stream1_IRQHandler,  /* [57] DMA2 Stream 1 */\n    (int)&DMA2_Stream2_IRQHandler,  /* [58] DMA2 Stream 2 */\n    (int)&DMA2_Stream3_IRQHandler,  /* [59] DMA2 Stream 3 */\n    (int)&DMA2_Stream4_IRQHandler,  /* [60] DMA2 Stream 4 */\n    (int)&ETH_IRQHandler,           /* [61] Ethernet */\n    (int)&ETH_WKUP_IRQHandler,      /* [62] Ethernet Wakeup through EXTI line */\n    (int)&FDCAN_CAL_IRQHandler,     /* [63] FDCAN calibration unit interrupt */\n    (int)&Reserved64_IRQHandler,    /* [64] Reserved */\n    (int)&Reserved65_IRQHandler,    /* [65] Reserved */\n    (int)&Reserved66_IRQHandler,    /* [66] Reserved */\n    (int)&Reserved67_IRQHandler,    /* [67] Reserved */\n    (int)&DMA2_Stream5_IRQHandler,  /* [68] DMA2 Stream 5 */\n    (int)&DMA2_Stream6_IRQHandler,  /* [69] DMA2 Stream 6 */\n    (int)&DMA2_Stream7_IRQHandler,  /* [70] DMA2 Stream 7 */\n    (int)&USART6_IRQHandler,        /* [71] USART6 */\n    (int)&I2C3_EV_IRQHandler,       /* [72] I2C3 event */\n    (int)&I2C3_ER_IRQHandler,       /* [73] I2C3 error */\n    (int)&OTG_HS_EP1_OUT_IRQHandler,/* [74] USB OTG HS End Point 1 Out */\n    (int)&OTG_HS_EP1_IN_IRQHandler, /* [75] USB OTG HS End Point 1 In */\n    (int)&OTG_HS_WKUP_IRQHandler,   /* [76] USB OTG HS Wakeup through EXTI */\n    (int)&OTG_HS_IRQHandler,        /* [77] USB OTG HS */\n    (int)&DCMI_IRQHandler,          /* [78] DCMI */\n    (int)&Reserved79_IRQHandler,    /* [79] Reserved */\n    (int)&RNG_IRQHandler,           /* [80] Rng */\n    (int)&FPU_IRQHandler,           /* [81] FPU */\n    (int)&UART7_IRQHandler,         /* [82] UART7 */\n    (int)&UART8_IRQHandler,         /* [83] UART8 */\n    (int)&SPI4_IRQHandler,          /* [84] SPI4 */\n    (int)&SPI5_IRQHandler,          /* [85] SPI5 */\n    (int)&SPI6_IRQHandler,          /* [86] SPI6 */\n    (int)&SAI1_IRQHandler,          /* [87] SAI1 */\n    (int)&LTDC_IRQHandler,          /* [88] LTDC */\n    (int)&LTDC_ER_IRQHandler,       /* [89] LTDC error */\n    (int)&DMA2D_IRQHandler,         /* [90] DMA2D */\n    (int)&SAI2_IRQHandler,          /* [91] SAI2 */\n    (int)&QUADSPI_IRQHandler,       /* [92] QUADSPI */\n    (int)&LPTIM1_IRQHandler,        /* [93] LPTIM1 */\n    (int)&CEC_IRQHandler,           /* [94] HDMI_CEC */\n    (int)&I2C4_EV_IRQHandler,       /* [95] I2C4 Event */\n    (int)&I2C4_ER_IRQHandler,       /* [96] I2C4 Error */\n    (int)&SPDIF_RX_IRQHandler,      /* [97] SPDIF_RX */\n    (int)&OTG_FS_EP1_OUT_IRQHandler,/* [98] USB OTG FS End Point 1 Out */\n    (int)&OTG_FS_EP1_IN_IRQHandler, /* [99] USB OTG FS End Point 1 In */\n    (int)&OTG_FS_WKUP_IRQHandler,   /* [100] USB OTG FS Wakeup through EXTI */\n    (int)&OTG_FS_IRQHandler,        /* [101] USB OTG FS */\n    (int)&DMAMUX1_OVR_IRQHandler,   /* [102] DMAMUX1 Overrun interrupt */\n    (int)&HRTIM1_Master_IRQHandler, /* [103] HRTIM Master Timer global Interrupts */\n    (int)&HRTIM1_TIMA_IRQHandler,   /* [104] HRTIM Timer A global Interrupt */\n    (int)&HRTIM1_TIMB_IRQHandler,   /* [105] HRTIM Timer B global Interrupt */\n    (int)&HRTIM1_TIMC_IRQHandler,   /* [106] HRTIM Timer C global Interrupt */\n    (int)&HRTIM1_TIMD_IRQHandler,   /* [107] HRTIM Timer D global Interrupt */\n    (int)&HRTIM1_TIME_IRQHandler,   /* [108] HRTIM Timer E global Interrupt */\n    (int)&HRTIM1_FLT_IRQHandler,    /* [109] HRTIM Fault global Interrupt */\n    (int)&DFSDM1_FLT0_IRQHandler,   /* [110] DFSDM Filter0 Interrupt */\n    (int)&DFSDM1_FLT1_IRQHandler,   /* [111] DFSDM Filter1 Interrupt */\n    (int)&DFSDM1_FLT2_IRQHandler,   /* [112] DFSDM Filter2 Interrupt */\n    (int)&DFSDM1_FLT3_IRQHandler,   /* [113] DFSDM Filter3 Interrupt */\n    (int)&SAI3_IRQHandler,          /* [114] SAI3 global Interrupt */\n    (int)&SWPMI1_IRQHandler,        /* [115] Serial Wire Interface 1 global interrupt */\n    (int)&TIM15_IRQHandler,         /* [116] TIM15 global Interrupt */\n    (int)&TIM16_IRQHandler,         /* [117] TIM16 global Interrupt */\n    (int)&TIM17_IRQHandler,         /* [118] TIM17 global Interrupt */\n    (int)&MDIOS_WKUP_IRQHandler,    /* [119] MDIOS Wakeup  Interrupt */\n    (int)&MDIOS_IRQHandler,         /* [120] MDIOS global Interrupt */\n    (int)&JPEG_IRQHandler,          /* [121] JPEG global Interrupt */\n    (int)&MDMA_IRQHandler,          /* [122] MDMA global Interrupt */\n    (int)&Reserved123_IRQHandler,   /* [123] Reserved */\n    (int)&SDMMC2_IRQHandler,        /* [124] SDMMC2 global Interrupt */\n    (int)&HSEM1_IRQHandler,         /* [125] HSEM1 global Interrupt */\n    (int)&Reserved126_IRQHandler,   /* [126] Reserved */\n    (int)&ADC3_IRQHandler,          /* [127] ADC3 global Interrupt */\n    (int)&DMAMUX2_OVR_IRQHandler,   /* [128] DMAMUX Overrun interrupt */\n    (int)&BDMA_Channel0_IRQHandler, /* [129] BDMA Channel 0 global Interrupt */\n    (int)&BDMA_Channel1_IRQHandler, /* [130] BDMA Channel 1 global Interrupt */\n    (int)&BDMA_Channel2_IRQHandler, /* [131] BDMA Channel 2 global Interrupt */\n    (int)&BDMA_Channel3_IRQHandler, /* [132] BDMA Channel 3 global Interrupt */\n    (int)&BDMA_Channel4_IRQHandler, /* [133] BDMA Channel 4 global Interrupt */\n    (int)&BDMA_Channel5_IRQHandler, /* [134] BDMA Channel 5 global Interrupt */\n    (int)&BDMA_Channel6_IRQHandler, /* [135] BDMA Channel 6 global Interrupt */\n    (int)&BDMA_Channel7_IRQHandler, /* [136] BDMA Channel 7 global Interrupt */\n    (int)&COMP1_IRQHandler,         /* [137] COMP1 global Interrupt */\n    (int)&LPTIM2_IRQHandler,        /* [138] LP TIM2 global interrupt */\n    (int)&LPTIM3_IRQHandler,        /* [139] LP TIM3 global interrupt */\n    (int)&LPTIM4_IRQHandler,        /* [140] LP TIM4 global interrupt */\n    (int)&LPTIM5_IRQHandler,        /* [141] LP TIM5 global interrupt */\n    (int)&LPUART1_IRQHandler,       /* [142] LP UART1 interrupt */\n    (int)&Reserved143_IRQHandler,   /* [143] Reserved */\n    (int)&CRS_IRQHandler,           /* [144] Clock Recovery Global Interrupt */\n    (int)&Reserved145_IRQHandler,   /* [145] Reserved */\n    (int)&SAI4_IRQHandler,          /* [146] SAI4 global interrupt */\n    (int)&Reserved147_IRQHandler,   /* [147] Reserved */\n    (int)&Reserved148_IRQHandler,   /* [148] Reserved */\n    (int)&WAKEUP_PIN_IRQHandler,    /* [149] Interrupt for all 6 wake-up pins */\n};\n\n\n/* reset handler -----------------------------------------------------------*/\n__attribute__((naked)) void Reset_Handler(void);\nvoid Reset_Handler(void) {\n    extern int main(void);\n    extern int __libc_init_array(void);\n    extern unsigned __data_start;  /* start of .data in the linker script */\n    extern unsigned __data_end__;  /* end of .data in the linker script */\n    extern unsigned const __data_load; /* initialization values for .data  */\n    extern unsigned __bss_start__; /* start of .bss in the linker script */\n    extern unsigned __bss_end__;   /* end of .bss in the linker script */\n    extern void software_init_hook(void) __attribute__((weak));\n\n    SystemInit(); /* CMSIS system initialization */\n\n    /* copy the data segment initializers from flash to RAM... */\n    unsigned const *src = &__data_load;\n    unsigned *dst;\n    for (dst = &__data_start; dst < &__data_end__; ++dst, ++src) {\n        *dst = *src;\n    }\n\n    /* zero fill the .bss segment in RAM... */\n    for (dst = &__bss_start__; dst < &__bss_end__; ++dst) {\n        *dst = 0;\n    }\n\n    /* init hook provided? */\n    if (&software_init_hook != (void (*)(void))(0)) {\n        /* give control to the RTOS */\n        software_init_hook(); /* this will also call __libc_init_array */\n    }\n    else {\n        /* call all static constructors in C++ (harmless in C programs) */\n        __libc_init_array();\n        (void)main(); /* application's entry point; should never return! */\n    }\n\n    /* the previous code should not return, but assert just in case... */\n    assert_failed(\"Reset_Handler\", 1U);\n}\n\n\n/* fault exception handlers ------------------------------------------------*/\n__attribute__((naked)) void NMI_Handler(void);\nvoid NMI_Handler(void) {\n    /* reset the SP to the initial value in case of stack overflow */\n    __asm volatile (\"  MOV  sp,%0\" : : \"r\" (&__stack_end__));\n    assert_failed(\"NMI_Handler\", 1U);\n}\n/*..........................................................................*/\n__attribute__((naked)) void HardFault_Handler(void);\nvoid HardFault_Handler(void) {\n    /* reset the SP to the initial value in case of stack overflow */\n    __asm volatile (\"  MOV  sp,%0\" : : \"r\" (&__stack_end__));\n    assert_failed(\"HardFault_Handler\", 1U);\n}\n/*..........................................................................*/\n__attribute__((naked)) void MemManage_Handler(void);\nvoid MemManage_Handler(void) {\n    /* reset the SP to the initial value in case of stack overflow */\n    __asm volatile (\"  MOV  sp,%0\" : : \"r\" (&__stack_end__));\n    assert_failed(\"MemManage_Handler\", 1U);\n}\n/*..........................................................................*/\n__attribute__((naked)) void BusFault_Handler(void);\nvoid BusFault_Handler(void) {\n    /* reset the SP to the initial value in case of stack overflow */\n    __asm volatile (\"  MOV  sp,%0\" : : \"r\" (&__stack_end__));\n    assert_failed(\"MemManage_Handler\", 1U);\n}\n/*..........................................................................*/\n__attribute__((naked)) void UsageFault_Handler(void);\nvoid UsageFault_Handler(void) {\n    /* reset the SP to the initial value in case of stack overflow */\n    __asm volatile (\"  MOV  sp,%0\" : : \"r\" (&__stack_end__));\n    assert_failed(\"BusFault_Handler\", 1U);\n}\n/*..........................................................................*/\n__attribute__((naked)) void Default_Handler(void);\nvoid Default_Handler(void) {\n    /* reset the SP to the initial value in case of stack overflow */\n    __asm volatile (\"  MOV  sp,%0\" : : \"r\" (&__stack_end__));\n    assert_failed(\"Default_Handler\", 1U);\n}\n"
  },
  {
    "path": "3rd_party/nucleo-h743zi/iar/startup_stm32h743xx.s",
    "content": ";/***************************************************************************/\n; * @file     startup_stm32h743xx.s for IAR ARM assembler\n; * @brief    CMSIS Cortex-M7 Core Device Startup File for STM32H743xx\n; * @version  CMSIS 5.9.0\n; * @date     1 Feb 2023\n; *\n; * Modified by Quantum Leaps:\n; * - Added relocating of the Vector Table to free up the 256B region at 0x0\n; *   for NULL-pointer protection by the MPU.\n; * - Modified all exception handlers to branch to assert_failed()\n; *   instead of locking up the CPU inside an endless loop.\n; *\n; * @description\n; * Created from the CMSIS template for the specified device\n; * Quantum Leaps, www.state-machine.com\n; *\n\n        MODULE  ?cstartup\n\n        ; Forward declaration of sections.\n        SECTION CSTACK:DATA:NOROOT(3)\n\n        SECTION .intvec:CODE:NOROOT(8)\n\n        PUBLIC  __vector_table\n        PUBLIC  __Vectors\n        PUBLIC  __Vectors_End\n        PUBLIC  __Vectors_Size\n\n;******************************************************************************\n; The vector table.\n;\n        DATA\n__vector_table\n    ; Initial Vector Table before relocation\n        DCD     sfe(CSTACK)\n        DCD     Reset_Handler               ; Reset Handler\n        DCD     NMI_Handler                 ; NMI Handler\n        DCD     HardFault_Handler           ; Hard Fault Handler\n        DCD     MemManage_Handler           ; MPU fault handler\n        DCD     BusFault_Handler            ; Bus fault handler\n        DCD     UsageFault_Handler          ; Usage fault handler\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     SVC_Handler                 ; SVCall handler\n        DCD     DebugMon_Handler            ; Debug Monitor handler\n        DCD     Default_Handler             ; Reserved\n        DCD     PendSV_Handler              ; PendSV handler\n        DCD     SysTick_Handler             ; SysTick handler\n\n        ; IRQ handlers...\n        DCD     WWDG_IRQHandler             ; [ 0] Window WatchDog Interrupt ( wwdg1_it)\n        DCD     PVD_AVD_IRQHandler          ; [ 1] PVD/AVD through EXTI Line detection\n        DCD     TAMP_STAMP_IRQHandler       ; [ 2] Tamper and TimeStamps through EXTI line\n        DCD     RTC_WKUP_IRQHandler         ; [ 3] RTC Wakeup through the EXTI line\n        DCD     FLASH_IRQHandler            ; [ 4] FLASH\n        DCD     RCC_IRQHandler              ; [ 5] RCC\n        DCD     EXTI0_IRQHandler            ; [ 6] EXTI Line0\n        DCD     EXTI1_IRQHandler            ; [ 7] EXTI Line1\n        DCD     EXTI2_IRQHandler            ; [ 8] EXTI Line2\n        DCD     EXTI3_IRQHandler            ; [ 9] EXTI Line3\n        DCD     EXTI4_IRQHandler            ; [10] EXTI Line4\n        DCD     DMA1_Stream0_IRQHandler     ; [11] DMA1 Stream 0\n        DCD     DMA1_Stream1_IRQHandler     ; [12] DMA1 Stream 1\n        DCD     DMA1_Stream2_IRQHandler     ; [13] DMA1 Stream 2\n        DCD     DMA1_Stream3_IRQHandler     ; [14] DMA1 Stream 3\n        DCD     DMA1_Stream4_IRQHandler     ; [15] DMA1 Stream 4\n        DCD     DMA1_Stream5_IRQHandler     ; [16] DMA1 Stream 5\n        DCD     DMA1_Stream6_IRQHandler     ; [17] DMA1 Stream 6\n        DCD     ADC_IRQHandler              ; [18] ADC1, ADC2\n        DCD     FDCAN1_IT0_IRQHandler       ; [19] FDCAN1 interrupt line 0\n        DCD     FDCAN2_IT0_IRQHandler       ; [20] FDCAN2 interrupt line 0\n        DCD     FDCAN1_IT1_IRQHandler       ; [21] FDCAN1 interrupt line 1\n        DCD     FDCAN2_IT1_IRQHandler       ; [22] FDCAN2 interrupt line 1\n        DCD     EXTI9_5_IRQHandler          ; [23] External Line[9:5]s\n        DCD     TIM1_BRK_IRQHandler         ; [24] TIM1 Break interrupt\n        DCD     TIM1_UP_IRQHandler          ; [25] TIM1 Update\n        DCD     TIM1_TRG_COM_IRQHandler     ; [26] TIM1 Trigger and Commutation Interrupt\n        DCD     TIM1_CC_IRQHandler          ; [27] TIM1 Capture Compare\n        DCD     TIM2_IRQHandler             ; [28] TIM2\n        DCD     TIM3_IRQHandler             ; [29] TIM3\n        DCD     TIM4_IRQHandler             ; [30] TIM4\n        DCD     I2C1_EV_IRQHandler          ; [31] I2C1 Event\n        DCD     I2C1_ER_IRQHandler          ; [32] I2C1 Error\n        DCD     I2C2_EV_IRQHandler          ; [33] I2C2 Event\n        DCD     I2C2_ER_IRQHandler          ; [34] I2C2 Error\n        DCD     SPI1_IRQHandler             ; [35] SPI1\n        DCD     SPI2_IRQHandler             ; [36] SPI2\n        DCD     USART1_IRQHandler           ; [37] USART1\n        DCD     USART2_IRQHandler           ; [38] USART2\n        DCD     USART3_IRQHandler           ; [39] USART3\n        DCD     EXTI15_10_IRQHandler        ; [40] External Line[15:10]\n        DCD     RTC_Alarm_IRQHandler        ; [41] RTC Alarm (A and B) through EXTI Line\n        DCD     Reserved42_IRQHandler       ; [42] Reserved\n        DCD     TIM8_BRK_TIM12_IRQHandler   ; [43] TIM8 Break Interrupt and TIM12 global interrupt\n        DCD     TIM8_UP_TIM13_IRQHandler    ; [44] TIM8 Update Interrupt and TIM13 global interrupt\n        DCD     TIM8_TRG_COM_TIM14_IRQHandler;[45] TIM8 Trigger and Commutation Interrupt and TIM14 glob\n        DCD     TIM8_CC_IRQHandler          ; [46] TIM8 Capture Compare Interrupt\n        DCD     DMA1_Stream7_IRQHandler     ; [47] DMA1 Stream7\n        DCD     FMC_IRQHandler              ; [48] FMC\n        DCD     SDMMC1_IRQHandler           ; [49] SDMMC1\n        DCD     TIM5_IRQHandler             ; [50] TIM5\n        DCD     SPI3_IRQHandler             ; [51] SPI3\n        DCD     UART4_IRQHandler            ; [52] UART4\n        DCD     UART5_IRQHandler            ; [53] UART5\n        DCD     TIM6_DAC_IRQHandler         ; [54] TIM6 and DAC1&2 underrun errors\n        DCD     TIM7_IRQHandler             ; [55] TIM7\n        DCD     DMA2_Stream0_IRQHandler     ; [56] DMA2 Stream 0\n        DCD     DMA2_Stream1_IRQHandler     ; [57] DMA2 Stream 1\n        DCD     DMA2_Stream2_IRQHandler     ; [58] DMA2 Stream 2\n        DCD     DMA2_Stream3_IRQHandler     ; [59] DMA2 Stream 3\n        DCD     DMA2_Stream4_IRQHandler     ; [60] DMA2 Stream 4\n        DCD     ETH_IRQHandler              ; [61] Ethernet\n        DCD     ETH_WKUP_IRQHandler         ; [62] Ethernet Wakeup through EXTI line\n        DCD     FDCAN_CAL_IRQHandler        ; [63] FDCAN calibration unit interrupt\n        DCD     Reserved64_IRQHandler       ; [64] Reserved\n        DCD     Reserved65_IRQHandler       ; [65] Reserved\n        DCD     Reserved66_IRQHandler       ; [66] Reserved\n        DCD     Reserved67_IRQHandler       ; [67] Reserved\n        DCD     DMA2_Stream5_IRQHandler     ; [68] DMA2 Stream 5\n        DCD     DMA2_Stream6_IRQHandler     ; [69] DMA2 Stream 6\n        DCD     DMA2_Stream7_IRQHandler     ; [70] DMA2 Stream 7\n        DCD     USART6_IRQHandler           ; [71] USART6\n        DCD     I2C3_EV_IRQHandler          ; [72] I2C3 event\n        DCD     I2C3_ER_IRQHandler          ; [73] I2C3 error\n        DCD     OTG_HS_EP1_OUT_IRQHandler   ; [74] USB OTG HS End Point 1 Out\n        DCD     OTG_HS_EP1_IN_IRQHandler    ; [75] USB OTG HS End Point 1 In\n        DCD     OTG_HS_WKUP_IRQHandler      ; [76] USB OTG HS Wakeup through EXTI\n        DCD     OTG_HS_IRQHandler           ; [77] USB OTG HS\n        DCD     DCMI_IRQHandler             ; [78] DCMI\n        DCD     Reserved79_IRQHandler       ; [79] Reserved\n        DCD     RNG_IRQHandler              ; [80] Rng\n        DCD     FPU_IRQHandler              ; [81] FPU\n        DCD     UART7_IRQHandler            ; [82] UART7\n        DCD     UART8_IRQHandler            ; [83] UART8\n        DCD     SPI4_IRQHandler             ; [84] SPI4\n        DCD     SPI5_IRQHandler             ; [85] SPI5\n        DCD     SPI6_IRQHandler             ; [86] SPI6\n        DCD     SAI1_IRQHandler             ; [87] SAI1\n        DCD     LTDC_IRQHandler             ; [88] LTDC\n        DCD     LTDC_ER_IRQHandler          ; [89] LTDC error\n        DCD     DMA2D_IRQHandler            ; [90] DMA2D\n        DCD     SAI2_IRQHandler             ; [91] SAI2\n        DCD     QUADSPI_IRQHandler          ; [92] QUADSPI\n        DCD     LPTIM1_IRQHandler           ; [93] LPTIM1\n        DCD     CEC_IRQHandler              ; [94] HDMI_CEC\n        DCD     I2C4_EV_IRQHandler          ; [95] I2C4 Event\n        DCD     I2C4_ER_IRQHandler          ; [96] I2C4 Error\n        DCD     SPDIF_RX_IRQHandler         ; [97] SPDIF_RX\n        DCD     OTG_FS_EP1_OUT_IRQHandler   ; [98] USB OTG FS End Point 1 Out\n        DCD     OTG_FS_EP1_IN_IRQHandler    ; [99] USB OTG FS End Point 1 In\n        DCD     OTG_FS_WKUP_IRQHandler      ; [100] USB OTG FS Wakeup through EXTI\n        DCD     OTG_FS_IRQHandler           ; [101] USB OTG FS\n        DCD     DMAMUX1_OVR_IRQHandler      ; [102] DMAMUX1 Overrun interrupt\n        DCD     HRTIM1_Master_IRQHandler    ; [103] HRTIM Master Timer global Interrupts\n        DCD     HRTIM1_TIMA_IRQHandler      ; [104] HRTIM Timer A global Interrupt\n        DCD     HRTIM1_TIMB_IRQHandler      ; [105] HRTIM Timer B global Interrupt\n        DCD     HRTIM1_TIMC_IRQHandler      ; [106] HRTIM Timer C global Interrupt\n        DCD     HRTIM1_TIMD_IRQHandler      ; [107] HRTIM Timer D global Interrupt\n        DCD     HRTIM1_TIME_IRQHandler      ; [108] HRTIM Timer E global Interrupt\n        DCD     HRTIM1_FLT_IRQHandler       ; [109] HRTIM Fault global Interrupt\n        DCD     DFSDM1_FLT0_IRQHandler      ; [110] DFSDM Filter0 Interrupt\n        DCD     DFSDM1_FLT1_IRQHandler      ; [111] DFSDM Filter1 Interrupt\n        DCD     DFSDM1_FLT2_IRQHandler      ; [112] DFSDM Filter2 Interrupt\n        DCD     DFSDM1_FLT3_IRQHandler      ; [113] DFSDM Filter3 Interrupt\n        DCD     SAI3_IRQHandler             ; [114] SAI3 global Interrupt\n        DCD     SWPMI1_IRQHandler           ; [115] Serial Wire Interface 1 global interrupt\n        DCD     TIM15_IRQHandler            ; [116] TIM15 global Interrupt\n        DCD     TIM16_IRQHandler            ; [117] TIM16 global Interrupt\n        DCD     TIM17_IRQHandler            ; [118] TIM17 global Interrupt\n        DCD     MDIOS_WKUP_IRQHandler       ; [119] MDIOS Wakeup  Interrupt\n        DCD     MDIOS_IRQHandler            ; [120] MDIOS global Interrupt\n        DCD     JPEG_IRQHandler             ; [121] JPEG global Interrupt\n        DCD     MDMA_IRQHandler             ; [122] MDMA global Interrupt\n        DCD     Reserved123_IRQHandler      ; [123] Reserved\n        DCD     SDMMC2_IRQHandler           ; [124] SDMMC2 global Interrupt\n        DCD     HSEM1_IRQHandler            ; [125] HSEM1 global Interrupt\n        DCD     Reserved126_IRQHandler      ; [126] Reserved\n        DCD     ADC3_IRQHandler             ; [127] ADC3 global Interrupt\n        DCD     DMAMUX2_OVR_IRQHandler      ; [128] DMAMUX Overrun interrupt\n        DCD     BDMA_Channel0_IRQHandler    ; [129] BDMA Channel 0 global Interrupt\n        DCD     BDMA_Channel1_IRQHandler    ; [130] BDMA Channel 1 global Interrupt\n        DCD     BDMA_Channel2_IRQHandler    ; [131] BDMA Channel 2 global Interrupt\n        DCD     BDMA_Channel3_IRQHandler    ; [132] BDMA Channel 3 global Interrupt\n        DCD     BDMA_Channel4_IRQHandler    ; [133] BDMA Channel 4 global Interrupt\n        DCD     BDMA_Channel5_IRQHandler    ; [134] BDMA Channel 5 global Interrupt\n        DCD     BDMA_Channel6_IRQHandler    ; [135] BDMA Channel 6 global Interrupt\n        DCD     BDMA_Channel7_IRQHandler    ; [136] BDMA Channel 7 global Interrupt\n        DCD     COMP1_IRQHandler            ; [137] COMP1 global Interrupt\n        DCD     LPTIM2_IRQHandler           ; [138] LP TIM2 global interrupt\n        DCD     LPTIM3_IRQHandler           ; [139] LP TIM3 global interrupt\n        DCD     LPTIM4_IRQHandler           ; [140] LP TIM4 global interrupt\n        DCD     LPTIM5_IRQHandler           ; [141] LP TIM5 global interrupt\n        DCD     LPUART1_IRQHandler          ; [142] LP UART1 interrupt\n        DCD     Reserved143_IRQHandler      ; [143] Reserved\n        DCD     CRS_IRQHandler              ; [144] Clock Recovery Global Interrupt\n        DCD     Reserved145_IRQHandler      ; [145] Reserved\n        DCD     SAI4_IRQHandler             ; [146] SAI4 global interrupt\n        DCD     Reserved147_IRQHandler      ; [147] Reserved\n        DCD     Reserved148_IRQHandler      ; [148] Reserved\n        DCD     WAKEUP_PIN_IRQHandler       ; [149] Interrupt for all 6 wake-up pins\n\n__Vectors_End\n\n__Vectors       EQU   __vector_table\n__Vectors_Size  EQU   __Vectors_End - __Vectors\n\n\n;******************************************************************************\n; This is the code for exception handlers.\n;\n        SECTION .text:CODE:REORDER:NOROOT(2)\n\n;******************************************************************************\n; This is the code that gets called when theessor first starts execution\n; following a reset event.\n;\n        PUBWEAK Reset_Handler\n        EXTERN  SystemInit\n        EXTERN  __iar_program_start\n        EXTERN  assert_failed\n\nReset_Handler\n        LDR     r0,=SystemInit  ; CMSIS system initialization\n        BLX     r0\n\n        ; pre-fill the CSTACK with 0xDEADBEEF...................\n        LDR     r0,=0xDEADBEEF\n        MOV     r1,r0\n        LDR     r2,=sfb(CSTACK)\n        LDR     r3,=sfe(CSTACK)\nReset_stackInit_fill:\n        STMIA   r2!,{r0,r1}\n        CMP     r2,r3\n        BLT.N   Reset_stackInit_fill\n\n        LDR     r0,=__iar_program_start ; IAR startup code\n        BLX     r0\n\n        ; __iar_program_start calls the main() function, which should not return,\n        ; but just in case jump to assert_failed() if main returns.\n        LDR     r0,=str_EXIT\n        MOVS    r1,#1\n        LDR     r2,=sfe(CSTACK)  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_EXIT\n        DCB     \"EXIT\"\n        ALIGNROM 2\n\n;******************************************************************************\n        PUBWEAK NMI_Handler\nNMI_Handler\n        LDR     r0,=str_NMI\n        MOVS    r1,#1\n        LDR     r2,=sfe(CSTACK)  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_NMI\n        DCB     \"NMI\"\n        ALIGNROM 2\n\n;******************************************************************************\n        PUBWEAK HardFault_Handler\nHardFault_Handler\n        LDR     r0,=str_HardFault\n        MOVS    r1,#1\n        LDR     r2,=sfe(CSTACK)  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_HardFault\n        DCB     \"HardFault\"\n        ALIGNROM 2\n\n;******************************************************************************\n        PUBWEAK MemManage_Handler\nMemManage_Handler\n        LDR     r0,=str_MemManage\n        MOVS    r1,#1\n        LDR     r2,=sfe(CSTACK)  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_MemManage\n        DCB     \"MemManage\"\n        ALIGNROM 2\n\n;******************************************************************************\n        PUBWEAK BusFault_Handler\nBusFault_Handler\n        LDR     r0,=str_BusFault\n        MOVS    r1,#1\n        LDR     r2,=sfe(CSTACK)  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_BusFault\n        DCB     \"BusFault\"\n        ALIGNROM 2\n\n;******************************************************************************\n        PUBWEAK UsageFault_Handler\nUsageFault_Handler\n        LDR     r0,=str_UsageFault\n        MOVS    r1,#1\n        LDR     r2,=sfe(CSTACK)  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_UsageFault\n        DCB     \"UsageFault\"\n        ALIGNROM 2\n\n;******************************************************************************\n;\n; Weak non-fault handlers...\n;\n\n;******************************************************************************\n        PUBWEAK SVC_Handler\nSVC_Handler\n        LDR     r0,=str_SVC\n        MOVS    r1,#1\n        LDR     r2,=sfe(CSTACK)  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_SVC\n        DCB     \"SVC\"\n        ALIGNROM 2\n\n;******************************************************************************\n        PUBWEAK DebugMon_Handler\nDebugMon_Handler\n        LDR     r0,=str_DebugMon\n        MOVS    r1,#1\n        LDR     r2,=sfe(CSTACK)  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_DebugMon\n        DCB     \"DebugMon\"\n        ALIGNROM 2\n\n;******************************************************************************\n        PUBWEAK PendSV_Handler\nPendSV_Handler\n        LDR     r0,=str_PendSV\n        MOVS    r1,#1\n        LDR     r2,=sfe(CSTACK)  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_PendSV\n        DCB     \"PendSV\"\n        ALIGNROM 2\n\n;******************************************************************************\n        PUBWEAK SysTick_Handler\nSysTick_Handler\n        LDR     r0,=str_SysTick\n        MOVS    r1,#1\n        LDR     r2,=sfe(CSTACK)  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_SysTick\n        DCB     \"SysTick\"\n        ALIGNROM 2\n\n;******************************************************************************\n; Weak IRQ handlers...\n;\n\n        PUBWEAK Default_Handler\n        PUBWEAK WWDG_IRQHandler\n        PUBWEAK PVD_AVD_IRQHandler\n        PUBWEAK TAMP_STAMP_IRQHandler\n        PUBWEAK RTC_WKUP_IRQHandler\n        PUBWEAK FLASH_IRQHandler\n        PUBWEAK RCC_IRQHandler\n        PUBWEAK EXTI0_IRQHandler\n        PUBWEAK EXTI1_IRQHandler\n        PUBWEAK EXTI2_IRQHandler\n        PUBWEAK EXTI3_IRQHandler\n        PUBWEAK EXTI4_IRQHandler\n        PUBWEAK DMA1_Stream0_IRQHandler\n        PUBWEAK DMA1_Stream1_IRQHandler\n        PUBWEAK DMA1_Stream2_IRQHandler\n        PUBWEAK DMA1_Stream3_IRQHandler\n        PUBWEAK DMA1_Stream4_IRQHandler\n        PUBWEAK DMA1_Stream5_IRQHandler\n        PUBWEAK DMA1_Stream6_IRQHandler\n        PUBWEAK ADC_IRQHandler\n        PUBWEAK FDCAN1_IT0_IRQHandler\n        PUBWEAK FDCAN2_IT0_IRQHandler\n        PUBWEAK FDCAN1_IT1_IRQHandler\n        PUBWEAK FDCAN2_IT1_IRQHandler\n        PUBWEAK EXTI9_5_IRQHandler\n        PUBWEAK TIM1_BRK_IRQHandler\n        PUBWEAK TIM1_UP_IRQHandler\n        PUBWEAK TIM1_TRG_COM_IRQHandler\n        PUBWEAK TIM1_CC_IRQHandler\n        PUBWEAK TIM2_IRQHandler\n        PUBWEAK TIM3_IRQHandler\n        PUBWEAK TIM4_IRQHandler\n        PUBWEAK I2C1_EV_IRQHandler\n        PUBWEAK I2C1_ER_IRQHandler\n        PUBWEAK I2C2_EV_IRQHandler\n        PUBWEAK I2C2_ER_IRQHandler\n        PUBWEAK SPI1_IRQHandler\n        PUBWEAK SPI2_IRQHandler\n        PUBWEAK USART1_IRQHandler\n        PUBWEAK USART2_IRQHandler\n        PUBWEAK USART3_IRQHandler\n        PUBWEAK EXTI15_10_IRQHandler\n        PUBWEAK RTC_Alarm_IRQHandler\n        PUBWEAK TIM8_BRK_TIM12_IRQHandler\n        PUBWEAK TIM8_UP_TIM13_IRQHandler\n        PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler\n        PUBWEAK TIM8_CC_IRQHandler\n        PUBWEAK DMA1_Stream7_IRQHandler\n        PUBWEAK FMC_IRQHandler\n        PUBWEAK SDMMC1_IRQHandler\n        PUBWEAK TIM5_IRQHandler\n        PUBWEAK SPI3_IRQHandler\n        PUBWEAK UART4_IRQHandler\n        PUBWEAK UART5_IRQHandler\n        PUBWEAK TIM6_DAC_IRQHandler\n        PUBWEAK TIM7_IRQHandler\n        PUBWEAK DMA2_Stream0_IRQHandler\n        PUBWEAK DMA2_Stream1_IRQHandler\n        PUBWEAK DMA2_Stream2_IRQHandler\n        PUBWEAK DMA2_Stream3_IRQHandler\n        PUBWEAK DMA2_Stream4_IRQHandler\n        PUBWEAK ETH_IRQHandler\n        PUBWEAK ETH_WKUP_IRQHandler\n        PUBWEAK FDCAN_CAL_IRQHandler\n        PUBWEAK DMA2_Stream5_IRQHandler\n        PUBWEAK DMA2_Stream6_IRQHandler\n        PUBWEAK DMA2_Stream7_IRQHandler\n        PUBWEAK USART6_IRQHandler\n        PUBWEAK I2C3_EV_IRQHandler\n        PUBWEAK I2C3_ER_IRQHandler\n        PUBWEAK OTG_HS_EP1_OUT_IRQHandler\n        PUBWEAK OTG_HS_EP1_IN_IRQHandler\n        PUBWEAK OTG_HS_WKUP_IRQHandler\n        PUBWEAK OTG_HS_IRQHandler\n        PUBWEAK DCMI_IRQHandler\n        PUBWEAK RNG_IRQHandler\n        PUBWEAK FPU_IRQHandler\n        PUBWEAK UART7_IRQHandler\n        PUBWEAK UART8_IRQHandler\n        PUBWEAK SPI4_IRQHandler\n        PUBWEAK SPI5_IRQHandler\n        PUBWEAK SPI6_IRQHandler\n        PUBWEAK SAI1_IRQHandler\n        PUBWEAK LTDC_IRQHandler\n        PUBWEAK LTDC_ER_IRQHandler\n        PUBWEAK DMA2D_IRQHandler\n        PUBWEAK SAI2_IRQHandler\n        PUBWEAK QUADSPI_IRQHandler\n        PUBWEAK LPTIM1_IRQHandler\n        PUBWEAK CEC_IRQHandler\n        PUBWEAK I2C4_EV_IRQHandler\n        PUBWEAK I2C4_ER_IRQHandler\n        PUBWEAK SPDIF_RX_IRQHandler\n        PUBWEAK OTG_FS_EP1_OUT_IRQHandler\n        PUBWEAK OTG_FS_EP1_IN_IRQHandler\n        PUBWEAK OTG_FS_WKUP_IRQHandler\n        PUBWEAK OTG_FS_IRQHandler\n        PUBWEAK DMAMUX1_OVR_IRQHandler\n        PUBWEAK HRTIM1_Master_IRQHandler\n        PUBWEAK HRTIM1_TIMA_IRQHandler\n        PUBWEAK HRTIM1_TIMB_IRQHandler\n        PUBWEAK HRTIM1_TIMC_IRQHandler\n        PUBWEAK HRTIM1_TIMD_IRQHandler\n        PUBWEAK HRTIM1_TIME_IRQHandler\n        PUBWEAK HRTIM1_FLT_IRQHandler\n        PUBWEAK DFSDM1_FLT0_IRQHandler\n        PUBWEAK DFSDM1_FLT1_IRQHandler\n        PUBWEAK DFSDM1_FLT2_IRQHandler\n        PUBWEAK DFSDM1_FLT3_IRQHandler\n        PUBWEAK SAI3_IRQHandler\n        PUBWEAK SWPMI1_IRQHandler\n        PUBWEAK TIM15_IRQHandler\n        PUBWEAK TIM16_IRQHandler\n        PUBWEAK TIM17_IRQHandler\n        PUBWEAK MDIOS_WKUP_IRQHandler\n        PUBWEAK MDIOS_IRQHandler\n        PUBWEAK JPEG_IRQHandler\n        PUBWEAK MDMA_IRQHandler\n        PUBWEAK SDMMC2_IRQHandler\n        PUBWEAK HSEM1_IRQHandler\n        PUBWEAK ADC3_IRQHandler\n        PUBWEAK DMAMUX2_OVR_IRQHandler\n        PUBWEAK BDMA_Channel0_IRQHandler\n        PUBWEAK BDMA_Channel1_IRQHandler\n        PUBWEAK BDMA_Channel2_IRQHandler\n        PUBWEAK BDMA_Channel3_IRQHandler\n        PUBWEAK BDMA_Channel4_IRQHandler\n        PUBWEAK BDMA_Channel5_IRQHandler\n        PUBWEAK BDMA_Channel6_IRQHandler\n        PUBWEAK BDMA_Channel7_IRQHandler\n        PUBWEAK COMP1_IRQHandler\n        PUBWEAK LPTIM2_IRQHandler\n        PUBWEAK LPTIM3_IRQHandler\n        PUBWEAK LPTIM4_IRQHandler\n        PUBWEAK LPTIM5_IRQHandler\n        PUBWEAK LPUART1_IRQHandler\n        PUBWEAK CRS_IRQHandler\n        PUBWEAK SAI4_IRQHandler\n        PUBWEAK WAKEUP_PIN_IRQHandler\n        PUBWEAK Reserved42_IRQHandler\n        PUBWEAK Reserved64_IRQHandler\n        PUBWEAK Reserved65_IRQHandler\n        PUBWEAK Reserved66_IRQHandler\n        PUBWEAK Reserved67_IRQHandler\n        PUBWEAK Reserved79_IRQHandler\n        PUBWEAK Reserved124_IRQHandler\n        PUBWEAK Reserved123_IRQHandler\n        PUBWEAK Reserved126_IRQHandler\n        PUBWEAK Reserved143_IRQHandler\n        PUBWEAK Reserved145_IRQHandler\n        PUBWEAK Reserved147_IRQHandler\n        PUBWEAK Reserved148_IRQHandler\n\nDefault_Handler\nWWDG_IRQHandler\nPVD_AVD_IRQHandler\nTAMP_STAMP_IRQHandler\nRTC_WKUP_IRQHandler\nFLASH_IRQHandler\nRCC_IRQHandler\nEXTI0_IRQHandler\nEXTI1_IRQHandler\nEXTI2_IRQHandler\nEXTI3_IRQHandler\nEXTI4_IRQHandler\nDMA1_Stream0_IRQHandler\nDMA1_Stream1_IRQHandler\nDMA1_Stream2_IRQHandler\nDMA1_Stream3_IRQHandler\nDMA1_Stream4_IRQHandler\nDMA1_Stream5_IRQHandler\nDMA1_Stream6_IRQHandler\nADC_IRQHandler\nFDCAN1_IT0_IRQHandler\nFDCAN2_IT0_IRQHandler\nFDCAN1_IT1_IRQHandler\nFDCAN2_IT1_IRQHandler\nEXTI9_5_IRQHandler\nTIM1_BRK_IRQHandler\nTIM1_UP_IRQHandler\nTIM1_TRG_COM_IRQHandler\nTIM1_CC_IRQHandler\nTIM2_IRQHandler\nTIM3_IRQHandler\nTIM4_IRQHandler\nI2C1_EV_IRQHandler\nI2C1_ER_IRQHandler\nI2C2_EV_IRQHandler\nI2C2_ER_IRQHandler\nSPI1_IRQHandler\nSPI2_IRQHandler\nUSART1_IRQHandler\nUSART2_IRQHandler\nUSART3_IRQHandler\nEXTI15_10_IRQHandler\nRTC_Alarm_IRQHandler\nTIM8_BRK_TIM12_IRQHandler\nTIM8_UP_TIM13_IRQHandler\nTIM8_TRG_COM_TIM14_IRQHandler\nTIM8_CC_IRQHandler\nDMA1_Stream7_IRQHandler\nFMC_IRQHandler\nSDMMC1_IRQHandler\nTIM5_IRQHandler\nSPI3_IRQHandler\nUART4_IRQHandler\nUART5_IRQHandler\nTIM6_DAC_IRQHandler\nTIM7_IRQHandler\nDMA2_Stream0_IRQHandler\nDMA2_Stream1_IRQHandler\nDMA2_Stream2_IRQHandler\nDMA2_Stream3_IRQHandler\nDMA2_Stream4_IRQHandler\nETH_IRQHandler\nETH_WKUP_IRQHandler\nFDCAN_CAL_IRQHandler\nDMA2_Stream5_IRQHandler\nDMA2_Stream6_IRQHandler\nDMA2_Stream7_IRQHandler\nUSART6_IRQHandler\nI2C3_EV_IRQHandler\nI2C3_ER_IRQHandler\nOTG_HS_EP1_OUT_IRQHandler\nOTG_HS_EP1_IN_IRQHandler\nOTG_HS_WKUP_IRQHandler\nOTG_HS_IRQHandler\nDCMI_IRQHandler\nRNG_IRQHandler\nFPU_IRQHandler\nUART7_IRQHandler\nUART8_IRQHandler\nSPI4_IRQHandler\nSPI5_IRQHandler\nSPI6_IRQHandler\nSAI1_IRQHandler\nLTDC_IRQHandler\nLTDC_ER_IRQHandler\nDMA2D_IRQHandler\nSAI2_IRQHandler\nQUADSPI_IRQHandler\nLPTIM1_IRQHandler\nCEC_IRQHandler\nI2C4_EV_IRQHandler\nI2C4_ER_IRQHandler\nSPDIF_RX_IRQHandler\nOTG_FS_EP1_OUT_IRQHandler\nOTG_FS_EP1_IN_IRQHandler\nOTG_FS_WKUP_IRQHandler\nOTG_FS_IRQHandler\nDMAMUX1_OVR_IRQHandler\nHRTIM1_Master_IRQHandler\nHRTIM1_TIMA_IRQHandler\nHRTIM1_TIMB_IRQHandler\nHRTIM1_TIMC_IRQHandler\nHRTIM1_TIMD_IRQHandler\nHRTIM1_TIME_IRQHandler\nHRTIM1_FLT_IRQHandler\nDFSDM1_FLT0_IRQHandler\nDFSDM1_FLT1_IRQHandler\nDFSDM1_FLT2_IRQHandler\nDFSDM1_FLT3_IRQHandler\nSAI3_IRQHandler\nSWPMI1_IRQHandler\nTIM15_IRQHandler\nTIM16_IRQHandler\nTIM17_IRQHandler\nMDIOS_WKUP_IRQHandler\nMDIOS_IRQHandler\nJPEG_IRQHandler\nMDMA_IRQHandler\nSDMMC2_IRQHandler\nHSEM1_IRQHandler\nADC3_IRQHandler\nDMAMUX2_OVR_IRQHandler\nBDMA_Channel0_IRQHandler\nBDMA_Channel1_IRQHandler\nBDMA_Channel2_IRQHandler\nBDMA_Channel3_IRQHandler\nBDMA_Channel4_IRQHandler\nBDMA_Channel5_IRQHandler\nBDMA_Channel6_IRQHandler\nBDMA_Channel7_IRQHandler\nCOMP1_IRQHandler\nLPTIM2_IRQHandler\nLPTIM3_IRQHandler\nLPTIM4_IRQHandler\nLPTIM5_IRQHandler\nLPUART1_IRQHandler\nCRS_IRQHandler\nSAI4_IRQHandler\nWAKEUP_PIN_IRQHandler\nReserved42_IRQHandler\nReserved64_IRQHandler\nReserved65_IRQHandler\nReserved66_IRQHandler\nReserved67_IRQHandler\nReserved79_IRQHandler\nReserved124_IRQHandler\nReserved123_IRQHandler\nReserved126_IRQHandler\nReserved143_IRQHandler\nReserved145_IRQHandler\nReserved147_IRQHandler\nReserved148_IRQHandler\n        LDR     r0,=str_Undefined\n        MOVS    r1,#1\n        LDR     r2,=sfe(CSTACK)  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_Undefined\n        DCB     \"Undefined\"\n        ALIGNROM 2\n\n        END                     ; end of module\n\n"
  },
  {
    "path": "3rd_party/nucleo-h743zi/stm32h743xx.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32h743xx.h\n  * @author  MCD Application Team\n  * @brief   CMSIS STM32H743xx Device Peripheral Access Layer Header File.\n  *\n  *          This file contains:\n  *           - Data structures and the address mapping for all peripherals\n  *           - Peripheral's registers declarations and bits definition\n  *           - Macros to access peripheral's registers hardware\n  *\n  ******************************************************************************\n  * @attention\n  *\n  * Copyright (c) 2017 STMicroelectronics.\n  * All rights reserved.\n  *\n  * This software is licensed under terms that can be found in the LICENSE file\n  * in the root directory of this software component.\n  * If no LICENSE file comes with this software, it is provided AS-IS.\n  *\n  ******************************************************************************\n  */\n\n/** @addtogroup CMSIS_Device\n  * @{\n  */\n\n/** @addtogroup stm32h743xx\n  * @{\n  */\n\n#ifndef STM32H743xx_H\n#define STM32H743xx_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif /* __cplusplus */\n\n/** @addtogroup Peripheral_interrupt_number_definition\n  * @{\n  */\n\n/**\n * @brief STM32H7XX Interrupt Number Definition, according to the selected device\n *        in @ref Library_configuration_section\n */\ntypedef enum\n{\n/******  Cortex-M Processor Exceptions Numbers *****************************************************************/\n  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */\n  HardFault_IRQn              = -13,    /*!< 3 Cortex-M Hard Fault Interrupt                                   */\n  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M Memory Management Interrupt                            */\n  BusFault_IRQn               = -11,    /*!< 5 Cortex-M Bus Fault Interrupt                                    */\n  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M Usage Fault Interrupt                                  */\n  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M SV Call Interrupt                                     */\n  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M Debug Monitor Interrupt                               */\n  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M Pend SV Interrupt                                     */\n  SysTick_IRQn                = -1,     /*!< 15 Cortex-M System Tick Interrupt                                 */\n/******  STM32 specific Interrupt Numbers **********************************************************************/\n  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt ( wwdg1_it, wwdg2_it)                   */\n  PVD_AVD_IRQn                = 1,      /*!< PVD/AVD through EXTI Line detection Interrupt                     */\n  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */\n  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */\n  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */\n  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */\n  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */\n  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */\n  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */\n  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */\n  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */\n  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */\n  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */\n  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */\n  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */\n  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */\n  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */\n  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */\n  ADC_IRQn                    = 18,     /*!< ADC1 and  ADC2 global Interrupts                                  */\n  FDCAN1_IT0_IRQn             = 19,     /*!< FDCAN1 Interrupt line 0                                           */\n  FDCAN2_IT0_IRQn             = 20,     /*!< FDCAN2 Interrupt line 0                                           */\n  FDCAN1_IT1_IRQn             = 21,     /*!< FDCAN1 Interrupt line 1                                           */\n  FDCAN2_IT1_IRQn             = 22,     /*!< FDCAN2 Interrupt line 1                                           */\n  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */\n  TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                              */\n  TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                             */\n  TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt                            */\n  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */\n  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */\n  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */\n  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */\n  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */\n  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */\n  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */\n  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */\n  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */\n  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */\n  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */\n  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */\n  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */\n  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */\n  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */\n  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */\n  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */\n  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */\n  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */\n  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */\n  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */\n  SDMMC1_IRQn                 = 49,     /*!< SDMMC1 global Interrupt                                           */\n  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */\n  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */\n  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */\n  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */\n  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */\n  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */\n  DMA2_Stream0_IRQn           = 56,     /*!<   DMA2 Stream 0 global Interrupt                                  */\n  DMA2_Stream1_IRQn           = 57,     /*!<   DMA2 Stream 1 global Interrupt                                  */\n  DMA2_Stream2_IRQn           = 58,     /*!<   DMA2 Stream 2 global Interrupt                                  */\n  DMA2_Stream3_IRQn           = 59,     /*!<   DMA2 Stream 3 global Interrupt                                  */\n  DMA2_Stream4_IRQn           = 60,     /*!<   DMA2 Stream 4 global Interrupt                                  */\n  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */\n  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */\n  FDCAN_CAL_IRQn              = 63,     /*!< FDCAN Calibration unit Interrupt                                  */\n  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */\n  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */\n  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */\n  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */\n  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */\n  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */\n  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */\n  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */\n  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */\n  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */\n  DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */\n  RNG_IRQn                    = 80,     /*!< RNG global interrupt                                              */\n  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */\n  UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */\n  UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */\n  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */\n  SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */\n  SPI6_IRQn                   = 86,     /*!< SPI6 global Interrupt                                             */\n  SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */\n  LTDC_IRQn                   = 88,     /*!< LTDC global Interrupt                                             */\n  LTDC_ER_IRQn                = 89,     /*!< LTDC Error global Interrupt                                       */\n  DMA2D_IRQn                  = 90,     /*!< DMA2D global Interrupt                                            */\n  SAI2_IRQn                   = 91,     /*!< SAI2 global Interrupt                                             */\n  QUADSPI_IRQn                = 92,     /*!< Quad SPI global interrupt                                         */\n  LPTIM1_IRQn                 = 93,     /*!< LP TIM1 interrupt                                                 */\n  CEC_IRQn                    = 94,     /*!< HDMI-CEC global Interrupt                                         */\n  I2C4_EV_IRQn                = 95,     /*!< I2C4 Event Interrupt                                              */\n  I2C4_ER_IRQn                = 96,     /*!< I2C4 Error Interrupt                                              */\n  SPDIF_RX_IRQn               = 97,     /*!< SPDIF-RX global Interrupt                                         */\n  OTG_FS_EP1_OUT_IRQn         = 98,     /*!< USB OTG HS2 global interrupt                                      */\n  OTG_FS_EP1_IN_IRQn          = 99,     /*!< USB OTG HS2 End Point 1 Out global interrupt                      */\n  OTG_FS_WKUP_IRQn            = 100,    /*!< USB OTG HS2 End Point 1 In global interrupt                       */\n  OTG_FS_IRQn                 = 101,    /*!< USB OTG HS2 Wakeup through EXTI interrupt                         */\n  DMAMUX1_OVR_IRQn            = 102,    /*!<DMAMUX1 Overrun interrupt                                          */\n  HRTIM1_Master_IRQn          = 103,    /*!< HRTIM Master Timer global Interrupts                              */\n  HRTIM1_TIMA_IRQn            = 104,    /*!< HRTIM Timer A global Interrupt                                    */\n  HRTIM1_TIMB_IRQn            = 105,    /*!< HRTIM Timer B global Interrupt                                    */\n  HRTIM1_TIMC_IRQn            = 106,    /*!< HRTIM Timer C global Interrupt                                    */\n  HRTIM1_TIMD_IRQn            = 107,    /*!< HRTIM Timer D global Interrupt                                    */\n  HRTIM1_TIME_IRQn            = 108,    /*!< HRTIM Timer E global Interrupt                                    */\n  HRTIM1_FLT_IRQn             = 109,    /*!< HRTIM Fault global Interrupt                                      */\n  DFSDM1_FLT0_IRQn            = 110,    /*!<DFSDM Filter1 Interrupt                                            */\n  DFSDM1_FLT1_IRQn            = 111,    /*!<DFSDM Filter2 Interrupt                                            */\n  DFSDM1_FLT2_IRQn            = 112,    /*!<DFSDM Filter3 Interrupt                                            */\n  DFSDM1_FLT3_IRQn            = 113,    /*!<DFSDM Filter4 Interrupt                                            */\n  SAI3_IRQn                   = 114,    /*!< SAI3 global Interrupt                                             */\n  SWPMI1_IRQn                 = 115,    /*!< Serial Wire Interface 1 global interrupt                          */\n  TIM15_IRQn                  = 116,    /*!< TIM15 global Interrupt                                            */\n  TIM16_IRQn                  = 117,    /*!< TIM16 global Interrupt                                            */\n  TIM17_IRQn                  = 118,    /*!< TIM17 global Interrupt                                            */\n  MDIOS_WKUP_IRQn             = 119,    /*!< MDIOS Wakeup  Interrupt                                           */\n  MDIOS_IRQn                  = 120,    /*!< MDIOS global Interrupt                                            */\n  JPEG_IRQn                   = 121,    /*!< JPEG global Interrupt                                             */\n  MDMA_IRQn                   = 122,    /*!< MDMA global Interrupt                                             */\n  SDMMC2_IRQn                 = 124,    /*!< SDMMC2 global Interrupt                                           */\n  HSEM1_IRQn                  = 125,    /*!< HSEM1 global Interrupt                                            */\n  ADC3_IRQn                   = 127,    /*!< ADC3 global Interrupt                                             */\n  DMAMUX2_OVR_IRQn            = 128,    /*!<DMAMUX2 Overrun interrupt                                          */\n  BDMA_Channel0_IRQn          = 129,    /*!< BDMA Channel 0 global Interrupt                                   */\n  BDMA_Channel1_IRQn          = 130,    /*!< BDMA Channel 1 global Interrupt                                   */\n  BDMA_Channel2_IRQn          = 131,    /*!< BDMA Channel 2 global Interrupt                                   */\n  BDMA_Channel3_IRQn          = 132,    /*!< BDMA Channel 3 global Interrupt                                   */\n  BDMA_Channel4_IRQn          = 133,    /*!< BDMA Channel 4 global Interrupt                                   */\n  BDMA_Channel5_IRQn          = 134,    /*!< BDMA Channel 5 global Interrupt                                   */\n  BDMA_Channel6_IRQn          = 135,    /*!< BDMA Channel 6 global Interrupt                                   */\n  BDMA_Channel7_IRQn          = 136,    /*!< BDMA Channel 7 global Interrupt                                   */\n  COMP_IRQn                   = 137 ,   /*!< COMP global Interrupt                                             */\n  LPTIM2_IRQn                 = 138,    /*!< LP TIM2 global interrupt                                          */\n  LPTIM3_IRQn                 = 139,    /*!< LP TIM3 global interrupt                                          */\n  LPTIM4_IRQn                 = 140,    /*!< LP TIM4 global interrupt                                          */\n  LPTIM5_IRQn                 = 141,    /*!< LP TIM5 global interrupt                                          */\n  LPUART1_IRQn                = 142,    /*!< LP UART1 interrupt                                                */\n  CRS_IRQn                    = 144,    /*!< Clock Recovery Global Interrupt                                   */\n  ECC_IRQn                    = 145,    /*!< ECC diagnostic Global Interrupt                                   */\n  SAI4_IRQn                   = 146,    /*!< SAI4 global interrupt                                             */\n  WAKEUP_PIN_IRQn             = 149,    /*!< Interrupt for all 6 wake-up pins                                  */\n} IRQn_Type;\n\n/**\n  * @}\n  */\n\n/** @addtogroup Configuration_section_for_CMSIS\n  * @{\n  */\n\n\n\n\n/**\n  * @brief Configuration of the Cortex-M7 Processor and Core Peripherals\n   */\n#define __CM7_REV               0x0100U   /*!< Cortex-M7 revision r1p0                       */\n#define __MPU_PRESENT             1U       /*!< CM7 provides an MPU                           */\n#define __NVIC_PRIO_BITS          4U       /*!< CM7 uses 4 Bits for the Priority Levels       */\n#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */\n#define __FPU_PRESENT             1U       /*!< FPU present                                   */\n#define __ICACHE_PRESENT          1U       /*!< CM7 instruction cache present                 */\n#define __DCACHE_PRESENT          1U       /*!< CM7 data cache present                        */\n#include \"core_cm7.h\"                     /*!< Cortex-M7 processor and core peripherals      */\n\n/**\n  * @}\n  */\n\n\n\n\n#include \"system_stm32h7xx.h\"\n#include <stdint.h>\n\n/** @addtogroup Peripheral_registers_structures\n  * @{\n  */\n\n/**\n  * @brief Analog to Digital Converter\n  */\n\ntypedef struct\n{\n  __IO uint32_t ISR;              /*!< ADC Interrupt and Status Register,                          Address offset: 0x00 */\n  __IO uint32_t IER;              /*!< ADC Interrupt Enable Register,                              Address offset: 0x04 */\n  __IO uint32_t CR;               /*!< ADC control register,                                       Address offset: 0x08 */\n  __IO uint32_t CFGR;             /*!< ADC Configuration register,                                 Address offset: 0x0C */\n  __IO uint32_t CFGR2;            /*!< ADC Configuration register 2,                               Address offset: 0x10 */\n  __IO uint32_t SMPR1;            /*!< ADC sample time register 1,                                 Address offset: 0x14 */\n  __IO uint32_t SMPR2;            /*!< ADC sample time register 2,                                 Address offset: 0x18 */\n  __IO uint32_t PCSEL;            /*!< ADC pre-channel selection,                                  Address offset: 0x1C */\n  __IO uint32_t LTR1;             /*!< ADC watchdog Lower threshold register 1,                    Address offset: 0x20 */\n  __IO uint32_t HTR1;             /*!< ADC watchdog higher threshold register 1,                   Address offset: 0x24 */\n  uint32_t      RESERVED1;        /*!< Reserved, 0x028                                                                  */\n  uint32_t      RESERVED2;        /*!< Reserved, 0x02C                                                                  */\n  __IO uint32_t SQR1;             /*!< ADC regular sequence register 1,                            Address offset: 0x30 */\n  __IO uint32_t SQR2;             /*!< ADC regular sequence register 2,                            Address offset: 0x34 */\n  __IO uint32_t SQR3;             /*!< ADC regular sequence register 3,                            Address offset: 0x38 */\n  __IO uint32_t SQR4;             /*!< ADC regular sequence register 4,                            Address offset: 0x3C */\n  __IO uint32_t DR;               /*!< ADC regular data register,                                  Address offset: 0x40 */\n  uint32_t      RESERVED3;        /*!< Reserved, 0x044                                                                  */\n  uint32_t      RESERVED4;        /*!< Reserved, 0x048                                                                  */\n  __IO uint32_t JSQR;             /*!< ADC injected sequence register,                             Address offset: 0x4C */\n  uint32_t      RESERVED5[4];     /*!< Reserved, 0x050 - 0x05C                                                          */\n  __IO uint32_t OFR1;             /*!< ADC offset register 1,                                      Address offset: 0x60 */\n  __IO uint32_t OFR2;             /*!< ADC offset register 2,                                      Address offset: 0x64 */\n  __IO uint32_t OFR3;             /*!< ADC offset register 3,                                      Address offset: 0x68 */\n  __IO uint32_t OFR4;             /*!< ADC offset register 4,                                      Address offset: 0x6C */\n  uint32_t      RESERVED6[4];     /*!< Reserved, 0x070 - 0x07C                                                          */\n  __IO uint32_t JDR1;             /*!< ADC injected data register 1,                               Address offset: 0x80 */\n  __IO uint32_t JDR2;             /*!< ADC injected data register 2,                               Address offset: 0x84 */\n  __IO uint32_t JDR3;             /*!< ADC injected data register 3,                               Address offset: 0x88 */\n  __IO uint32_t JDR4;             /*!< ADC injected data register 4,                               Address offset: 0x8C */\n  uint32_t      RESERVED7[4];     /*!< Reserved, 0x090 - 0x09C                                                          */\n  __IO uint32_t AWD2CR;           /*!< ADC  Analog Watchdog 2 Configuration Register,              Address offset: 0xA0 */\n  __IO uint32_t AWD3CR;           /*!< ADC  Analog Watchdog 3 Configuration Register,              Address offset: 0xA4 */\n  uint32_t      RESERVED8;        /*!< Reserved, 0x0A8                                                                  */\n  uint32_t      RESERVED9;        /*!< Reserved, 0x0AC                                                                  */\n  __IO uint32_t LTR2;             /*!< ADC watchdog Lower threshold register 2,                    Address offset: 0xB0 */\n  __IO uint32_t HTR2;             /*!< ADC watchdog Higher threshold register 2,                   Address offset: 0xB4 */\n  __IO uint32_t LTR3;             /*!< ADC watchdog Lower threshold register 3,                    Address offset: 0xB8 */\n  __IO uint32_t HTR3;             /*!< ADC watchdog Higher threshold register 3,                   Address offset: 0xBC */\n  __IO uint32_t DIFSEL;           /*!< ADC  Differential Mode Selection Register,                  Address offset: 0xC0 */\n  __IO uint32_t CALFACT;          /*!< ADC  Calibration Factors,                                   Address offset: 0xC4 */\n  __IO uint32_t CALFACT2;         /*!< ADC  Linearity Calibration Factors,                         Address offset: 0xC8 */\n} ADC_TypeDef;\n\n\ntypedef struct\n{\n__IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */\nuint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */\n__IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */\n__IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */\n__IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */\n\n} ADC_Common_TypeDef;\n\n\n/**\n  * @brief VREFBUF\n  */\n\ntypedef struct\n{\n  __IO uint32_t CSR;         /*!< VREFBUF control and status register,         Address offset: 0x00 */\n  __IO uint32_t CCR;         /*!< VREFBUF calibration and control register,    Address offset: 0x04 */\n} VREFBUF_TypeDef;\n\n\n/**\n  * @brief FD Controller Area Network\n  */\n\ntypedef struct\n{\n  __IO uint32_t CREL;         /*!< FDCAN Core Release register,                                     Address offset: 0x000 */\n  __IO uint32_t ENDN;         /*!< FDCAN Endian register,                                           Address offset: 0x004 */\n  __IO uint32_t RESERVED1;    /*!< Reserved,                                                                        0x008 */\n  __IO uint32_t DBTP;         /*!< FDCAN Data Bit Timing & Prescaler register,                      Address offset: 0x00C */\n  __IO uint32_t TEST;         /*!< FDCAN Test register,                                             Address offset: 0x010 */\n  __IO uint32_t RWD;          /*!< FDCAN RAM Watchdog register,                                     Address offset: 0x014 */\n  __IO uint32_t CCCR;         /*!< FDCAN CC Control register,                                       Address offset: 0x018 */\n  __IO uint32_t NBTP;         /*!< FDCAN Nominal Bit Timing & Prescaler register,                   Address offset: 0x01C */\n  __IO uint32_t TSCC;         /*!< FDCAN Timestamp Counter Configuration register,                  Address offset: 0x020 */\n  __IO uint32_t TSCV;         /*!< FDCAN Timestamp Counter Value register,                          Address offset: 0x024 */\n  __IO uint32_t TOCC;         /*!< FDCAN Timeout Counter Configuration register,                    Address offset: 0x028 */\n  __IO uint32_t TOCV;         /*!< FDCAN Timeout Counter Value register,                            Address offset: 0x02C */\n  __IO uint32_t RESERVED2[4]; /*!< Reserved,                                                                0x030 - 0x03C */\n  __IO uint32_t ECR;          /*!< FDCAN Error Counter register,                                    Address offset: 0x040 */\n  __IO uint32_t PSR;          /*!< FDCAN Protocol Status register,                                  Address offset: 0x044 */\n  __IO uint32_t TDCR;         /*!< FDCAN Transmitter Delay Compensation register,                   Address offset: 0x048 */\n  __IO uint32_t RESERVED3;    /*!< Reserved,                                                                        0x04C */\n  __IO uint32_t IR;           /*!< FDCAN Interrupt register,                                        Address offset: 0x050 */\n  __IO uint32_t IE;           /*!< FDCAN Interrupt Enable register,                                 Address offset: 0x054 */\n  __IO uint32_t ILS;          /*!< FDCAN Interrupt Line Select register,                            Address offset: 0x058 */\n  __IO uint32_t ILE;          /*!< FDCAN Interrupt Line Enable register,                            Address offset: 0x05C */\n  __IO uint32_t RESERVED4[8]; /*!< Reserved,                                                                0x060 - 0x07C */\n  __IO uint32_t GFC;          /*!< FDCAN Global Filter Configuration register,                      Address offset: 0x080 */\n  __IO uint32_t SIDFC;        /*!< FDCAN Standard ID Filter Configuration register,                 Address offset: 0x084 */\n  __IO uint32_t XIDFC;        /*!< FDCAN Extended ID Filter Configuration register,                 Address offset: 0x088 */\n  __IO uint32_t RESERVED5;    /*!< Reserved,                                                                        0x08C */\n  __IO uint32_t XIDAM;        /*!< FDCAN Extended ID AND Mask register,                             Address offset: 0x090 */\n  __IO uint32_t HPMS;         /*!< FDCAN High Priority Message Status register,                     Address offset: 0x094 */\n  __IO uint32_t NDAT1;        /*!< FDCAN New Data 1 register,                                       Address offset: 0x098 */\n  __IO uint32_t NDAT2;        /*!< FDCAN New Data 2 register,                                       Address offset: 0x09C */\n  __IO uint32_t RXF0C;        /*!< FDCAN Rx FIFO 0 Configuration register,                          Address offset: 0x0A0 */\n  __IO uint32_t RXF0S;        /*!< FDCAN Rx FIFO 0 Status register,                                 Address offset: 0x0A4 */\n  __IO uint32_t RXF0A;        /*!< FDCAN Rx FIFO 0 Acknowledge register,                            Address offset: 0x0A8 */\n  __IO uint32_t RXBC;         /*!< FDCAN Rx Buffer Configuration register,                          Address offset: 0x0AC */\n  __IO uint32_t RXF1C;        /*!< FDCAN Rx FIFO 1 Configuration register,                          Address offset: 0x0B0 */\n  __IO uint32_t RXF1S;        /*!< FDCAN Rx FIFO 1 Status register,                                 Address offset: 0x0B4 */\n  __IO uint32_t RXF1A;        /*!< FDCAN Rx FIFO 1 Acknowledge register,                            Address offset: 0x0B8 */\n  __IO uint32_t RXESC;        /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register,        Address offset: 0x0BC */\n  __IO uint32_t TXBC;         /*!< FDCAN Tx Buffer Configuration register,                          Address offset: 0x0C0 */\n  __IO uint32_t TXFQS;        /*!< FDCAN Tx FIFO/Queue Status register,                             Address offset: 0x0C4 */\n  __IO uint32_t TXESC;        /*!< FDCAN Tx Buffer Element Size Configuration register,             Address offset: 0x0C8 */\n  __IO uint32_t TXBRP;        /*!< FDCAN Tx Buffer Request Pending register,                        Address offset: 0x0CC */\n  __IO uint32_t TXBAR;        /*!< FDCAN Tx Buffer Add Request register,                            Address offset: 0x0D0 */\n  __IO uint32_t TXBCR;        /*!< FDCAN Tx Buffer Cancellation Request register,                   Address offset: 0x0D4 */\n  __IO uint32_t TXBTO;        /*!< FDCAN Tx Buffer Transmission Occurred register,                  Address offset: 0x0D8 */\n  __IO uint32_t TXBCF;        /*!< FDCAN Tx Buffer Cancellation Finished register,                  Address offset: 0x0DC */\n  __IO uint32_t TXBTIE;       /*!< FDCAN Tx Buffer Transmission Interrupt Enable register,          Address offset: 0x0E0 */\n  __IO uint32_t TXBCIE;       /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */\n  __IO uint32_t RESERVED6[2]; /*!< Reserved,                                                                0x0E8 - 0x0EC */\n  __IO uint32_t TXEFC;        /*!< FDCAN Tx Event FIFO Configuration register,                      Address offset: 0x0F0 */\n  __IO uint32_t TXEFS;        /*!< FDCAN Tx Event FIFO Status register,                             Address offset: 0x0F4 */\n  __IO uint32_t TXEFA;        /*!< FDCAN Tx Event FIFO Acknowledge register,                        Address offset: 0x0F8 */\n  __IO uint32_t RESERVED7;    /*!< Reserved,                                                                        0x0FC */\n} FDCAN_GlobalTypeDef;\n\n/**\n  * @brief TTFD Controller Area Network\n  */\n\ntypedef struct\n{\n  __IO uint32_t TTTMC;          /*!< TT Trigger Memory Configuration register,    Address offset: 0x100 */\n  __IO uint32_t TTRMC;          /*!< TT Reference Message Configuration register, Address offset: 0x104 */\n  __IO uint32_t TTOCF;          /*!< TT Operation Configuration register,         Address offset: 0x108 */\n  __IO uint32_t TTMLM;          /*!< TT Matrix Limits register,                   Address offset: 0x10C */\n  __IO uint32_t TURCF;          /*!< TUR Configuration register,                  Address offset: 0x110 */\n  __IO uint32_t TTOCN;          /*!< TT Operation Control register,               Address offset: 0x114 */\n  __IO uint32_t TTGTP;          /*!< TT Global Time Preset register,              Address offset: 0x118 */\n  __IO uint32_t TTTMK;          /*!< TT Time Mark register,                       Address offset: 0x11C */\n  __IO uint32_t TTIR;           /*!< TT Interrupt register,                       Address offset: 0x120 */\n  __IO uint32_t TTIE;           /*!< TT Interrupt Enable register,                Address offset: 0x124 */\n  __IO uint32_t TTILS;          /*!< TT Interrupt Line Select register,           Address offset: 0x128 */\n  __IO uint32_t TTOST;          /*!< TT Operation Status register,                Address offset: 0x12C */\n  __IO uint32_t TURNA;          /*!< TT TUR Numerator Actual register,            Address offset: 0x130 */\n  __IO uint32_t TTLGT;          /*!< TT Local and Global Time register,           Address offset: 0x134 */\n  __IO uint32_t TTCTC;          /*!< TT Cycle Time and Count register,            Address offset: 0x138 */\n  __IO uint32_t TTCPT;          /*!< TT Capture Time register,                    Address offset: 0x13C */\n  __IO uint32_t TTCSM;          /*!< TT Cycle Sync Mark register,                 Address offset: 0x140 */\n  __IO uint32_t RESERVED1[111]; /*!< Reserved,                                            0x144 - 0x2FC */\n  __IO uint32_t TTTS;           /*!< TT Trigger Select register,                  Address offset: 0x300 */\n} TTCAN_TypeDef;\n\n/**\n  * @brief FD Controller Area Network\n  */\n\ntypedef struct\n{\n  __IO uint32_t CREL;  /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */\n  __IO uint32_t CCFG;  /*!< Calibration Configuration register,           Address offset: 0x04 */\n  __IO uint32_t CSTAT; /*!< Calibration Status register,                  Address offset: 0x08 */\n  __IO uint32_t CWD;   /*!< Calibration Watchdog register,                Address offset: 0x0C */\n  __IO uint32_t IR;    /*!< CCU Interrupt register,                       Address offset: 0x10 */\n  __IO uint32_t IE;    /*!< CCU Interrupt Enable register,                Address offset: 0x14 */\n} FDCAN_ClockCalibrationUnit_TypeDef;\n\n\n/**\n  * @brief Consumer Electronics Control\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;           /*!< CEC control register,              Address offset:0x00 */\n  __IO uint32_t CFGR;         /*!< CEC configuration register,        Address offset:0x04 */\n  __IO uint32_t TXDR;         /*!< CEC Tx data register ,             Address offset:0x08 */\n  __IO uint32_t RXDR;         /*!< CEC Rx Data Register,              Address offset:0x0C */\n  __IO uint32_t ISR;          /*!< CEC Interrupt and Status Register, Address offset:0x10 */\n  __IO uint32_t IER;          /*!< CEC interrupt enable register,     Address offset:0x14 */\n}CEC_TypeDef;\n\n/**\n  * @brief CRC calculation unit\n  */\n\ntypedef struct\n{\n  __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */\n  __IO uint32_t IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */\n  __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */\n  uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */\n  __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */\n  __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */\n} CRC_TypeDef;\n\n\n/**\n  * @brief Clock Recovery System\n  */\ntypedef struct\n{\n__IO uint32_t CR;            /*!< CRS ccontrol register,              Address offset: 0x00 */\n__IO uint32_t CFGR;          /*!< CRS configuration register,         Address offset: 0x04 */\n__IO uint32_t ISR;           /*!< CRS interrupt and status register,  Address offset: 0x08 */\n__IO uint32_t ICR;           /*!< CRS interrupt flag clear register,  Address offset: 0x0C */\n} CRS_TypeDef;\n\n\n/**\n  * @brief Digital to Analog Converter\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */\n  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */\n  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */\n  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */\n  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */\n  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */\n  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */\n  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */\n  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */\n  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */\n  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */\n  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */\n  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */\n  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */\n  __IO uint32_t CCR;      /*!< DAC calibration control register,                        Address offset: 0x38 */\n  __IO uint32_t MCR;      /*!< DAC mode control register,                               Address offset: 0x3C */\n  __IO uint32_t SHSR1;    /*!< DAC Sample and Hold sample time register 1,              Address offset: 0x40 */\n  __IO uint32_t SHSR2;    /*!< DAC Sample and Hold sample time register 2,              Address offset: 0x44 */\n  __IO uint32_t SHHR;     /*!< DAC Sample and Hold hold time register,                  Address offset: 0x48 */\n  __IO uint32_t SHRR;     /*!< DAC Sample and Hold refresh time register,               Address offset: 0x4C */\n} DAC_TypeDef;\n\n/**\n  * @brief DFSDM module registers\n  */\ntypedef struct\n{\n  __IO uint32_t FLTCR1;          /*!< DFSDM control register1,                          Address offset: 0x100 */\n  __IO uint32_t FLTCR2;          /*!< DFSDM control register2,                          Address offset: 0x104 */\n  __IO uint32_t FLTISR;          /*!< DFSDM interrupt and status register,              Address offset: 0x108 */\n  __IO uint32_t FLTICR;          /*!< DFSDM interrupt flag clear register,              Address offset: 0x10C */\n  __IO uint32_t FLTJCHGR;        /*!< DFSDM injected channel group selection register,  Address offset: 0x110 */\n  __IO uint32_t FLTFCR;          /*!< DFSDM filter control register,                    Address offset: 0x114 */\n  __IO uint32_t FLTJDATAR;       /*!< DFSDM data register for injected group,           Address offset: 0x118 */\n  __IO uint32_t FLTRDATAR;       /*!< DFSDM data register for regular group,            Address offset: 0x11C */\n  __IO uint32_t FLTAWHTR;        /*!< DFSDM analog watchdog high threshold register,    Address offset: 0x120 */\n  __IO uint32_t FLTAWLTR;        /*!< DFSDM analog watchdog low threshold register,     Address offset: 0x124 */\n  __IO uint32_t FLTAWSR;         /*!< DFSDM analog watchdog status register             Address offset: 0x128 */\n  __IO uint32_t FLTAWCFR;        /*!< DFSDM analog watchdog clear flag register         Address offset: 0x12C */\n  __IO uint32_t FLTEXMAX;        /*!< DFSDM extreme detector maximum register,          Address offset: 0x130 */\n  __IO uint32_t FLTEXMIN;        /*!< DFSDM extreme detector minimum register           Address offset: 0x134 */\n  __IO uint32_t FLTCNVTIMR;      /*!< DFSDM conversion timer,                           Address offset: 0x138 */\n} DFSDM_Filter_TypeDef;\n\n/**\n  * @brief DFSDM channel configuration registers\n  */\ntypedef struct\n{\n  __IO uint32_t CHCFGR1;      /*!< DFSDM channel configuration register1,            Address offset: 0x00 */\n  __IO uint32_t CHCFGR2;      /*!< DFSDM channel configuration register2,            Address offset: 0x04 */\n  __IO uint32_t CHAWSCDR;     /*!< DFSDM channel analog watchdog and\n                                   short circuit detector register,                  Address offset: 0x08 */\n  __IO uint32_t CHWDATAR;     /*!< DFSDM channel watchdog filter data register,      Address offset: 0x0C */\n  __IO uint32_t CHDATINR;     /*!< DFSDM channel data input register,                Address offset: 0x10 */\n} DFSDM_Channel_TypeDef;\n\n/**\n  * @brief Debug MCU\n  */\ntypedef struct\n{\n  __IO uint32_t IDCODE;        /*!< MCU device ID code,                     Address offset: 0x00 */\n  __IO uint32_t CR;            /*!< Debug MCU configuration register,       Address offset: 0x04 */\n  uint32_t RESERVED4[11];      /*!< Reserved,                             Address offset: 0x08 */\n  __IO uint32_t APB3FZ1;     /*!< Debug MCU APB3FZ1 freeze register,    Address offset: 0x34 */\n  uint32_t RESERVED5;          /*!< Reserved,                             Address offset: 0x38 */\n  __IO uint32_t APB1LFZ1;    /*!< Debug MCU APB1LFZ1 freeze register,   Address offset: 0x3C */\n  uint32_t RESERVED6;          /*!< Reserved,                             Address offset: 0x40 */\n  __IO uint32_t APB1HFZ1;    /*!< Debug MCU APB1LFZ1 freeze register,   Address offset: 0x44 */\n  uint32_t RESERVED7;          /*!< Reserved,                             Address offset: 0x48 */\n  __IO uint32_t APB2FZ1;     /*!< Debug MCU APB2FZ1 freeze register,    Address offset: 0x4C */\n  uint32_t RESERVED8;          /*!< Reserved,                             Address offset: 0x50 */\n  __IO uint32_t APB4FZ1;     /*!< Debug MCU APB4FZ1 freeze register,    Address offset: 0x54 */\n}DBGMCU_TypeDef;\n/**\n  * @brief DCMI\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */\n  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */\n  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */\n  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */\n  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */\n  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */\n  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */\n  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */\n  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */\n  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */\n  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */\n} DCMI_TypeDef;\n\n/**\n  * @brief DMA Controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;     /*!< DMA stream x configuration register      */\n  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */\n  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */\n  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */\n  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */\n  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */\n} DMA_Stream_TypeDef;\n\ntypedef struct\n{\n  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */\n  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */\n  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */\n  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */\n} DMA_TypeDef;\n\ntypedef struct\n{\n  __IO uint32_t CCR;          /*!< DMA channel x configuration register          */\n  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register         */\n  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register     */\n  __IO uint32_t CM0AR;        /*!< DMA channel x memory 0 address register       */\n  __IO uint32_t CM1AR;        /*!< DMA channel x memory 1 address register       */\n} BDMA_Channel_TypeDef;\n\ntypedef struct\n{\n  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */\n  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */\n} BDMA_TypeDef;\n\ntypedef struct\n{\n  __IO uint32_t  CCR;        /*!< DMA Multiplexer Channel x Control Register   */\n}DMAMUX_Channel_TypeDef;\n\ntypedef struct\n{\n  __IO uint32_t  CSR;      /*!< DMA Channel Status Register     */\n  __IO uint32_t  CFR;      /*!< DMA Channel Clear Flag Register */\n}DMAMUX_ChannelStatus_TypeDef;\n\ntypedef struct\n{\n  __IO uint32_t  RGCR;        /*!< DMA Request Generator x Control Register   */\n}DMAMUX_RequestGen_TypeDef;\n\ntypedef struct\n{\n  __IO uint32_t  RGSR;        /*!< DMA Request Generator Status Register       */\n  __IO uint32_t  RGCFR;       /*!< DMA Request Generator Clear Flag Register   */\n}DMAMUX_RequestGenStatus_TypeDef;\n\n/**\n  * @brief MDMA Controller\n  */\ntypedef struct\n{\n  __IO uint32_t  GISR0;   /*!< MDMA Global Interrupt/Status Register 0,          Address offset: 0x00 */\n}MDMA_TypeDef;\n\ntypedef struct\n{\n  __IO uint32_t  CISR;      /*!< MDMA channel x interrupt/status register,             Address offset: 0x40 */\n  __IO uint32_t  CIFCR;     /*!< MDMA channel x interrupt flag clear register,         Address offset: 0x44 */\n  __IO uint32_t  CESR;      /*!< MDMA Channel x error status register,                 Address offset: 0x48 */\n  __IO uint32_t  CCR;       /*!< MDMA channel x control register,                      Address offset: 0x4C */\n  __IO uint32_t  CTCR;      /*!< MDMA channel x Transfer Configuration register,       Address offset: 0x50 */\n  __IO uint32_t  CBNDTR;    /*!< MDMA Channel x block number of data register,         Address offset: 0x54 */\n  __IO uint32_t  CSAR;      /*!< MDMA channel x source address register,               Address offset: 0x58 */\n  __IO uint32_t  CDAR;      /*!< MDMA channel x destination address register,          Address offset: 0x5C */\n  __IO uint32_t  CBRUR;     /*!< MDMA channel x Block Repeat address Update register,  Address offset: 0x60 */\n  __IO uint32_t  CLAR;      /*!< MDMA channel x Link Address register,                 Address offset: 0x64 */\n  __IO uint32_t  CTBR;      /*!< MDMA channel x Trigger and Bus selection Register,    Address offset: 0x68 */\n  uint32_t       RESERVED0; /*!< Reserved, 0x6C                                                             */\n  __IO uint32_t  CMAR;      /*!< MDMA channel x Mask address register,                 Address offset: 0x70 */\n  __IO uint32_t  CMDR;      /*!< MDMA channel x Mask Data register,                    Address offset: 0x74 */\n}MDMA_Channel_TypeDef;\n\n/**\n  * @brief DMA2D Controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */\n  __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */\n  __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */\n  __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */\n  __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */\n  __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */\n  __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */\n  __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */\n  __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */\n  __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */\n  __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */\n  __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */\n  __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */\n  __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */\n  __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */\n  __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */\n  __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */\n  __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */\n  __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */\n  __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */\n  uint32_t      RESERVED[236]; /*!< Reserved, 0x50-0x3FF */\n  __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                          Address offset:400-7FF */\n  __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                          Address offset:800-BFF */\n} DMA2D_TypeDef;\n\n\n/**\n  * @brief Ethernet MAC\n  */\ntypedef struct\n{\n  __IO uint32_t MACCR;\n  __IO uint32_t MACECR;\n  __IO uint32_t MACPFR;\n  __IO uint32_t MACWTR;\n  __IO uint32_t MACHT0R;\n  __IO uint32_t MACHT1R;\n  uint32_t      RESERVED1[14];\n  __IO uint32_t MACVTR;\n  uint32_t      RESERVED2;\n  __IO uint32_t MACVHTR;\n  uint32_t      RESERVED3;\n  __IO uint32_t MACVIR;\n  __IO uint32_t MACIVIR;\n  uint32_t      RESERVED4[2];\n  __IO uint32_t MACTFCR;\n  uint32_t      RESERVED5[7];\n  __IO uint32_t MACRFCR;\n  uint32_t      RESERVED6[7];\n  __IO uint32_t MACISR;\n  __IO uint32_t MACIER;\n  __IO uint32_t MACRXTXSR;\n  uint32_t      RESERVED7;\n  __IO uint32_t MACPCSR;\n  __IO uint32_t MACRWKPFR;\n  uint32_t      RESERVED8[2];\n  __IO uint32_t MACLCSR;\n  __IO uint32_t MACLTCR;\n  __IO uint32_t MACLETR;\n  __IO uint32_t MAC1USTCR;\n  uint32_t      RESERVED9[12];\n  __IO uint32_t MACVR;\n  __IO uint32_t MACDR;\n  uint32_t      RESERVED10;\n  __IO uint32_t MACHWF0R;\n  __IO uint32_t MACHWF1R;\n  __IO uint32_t MACHWF2R;\n  uint32_t      RESERVED11[54];\n  __IO uint32_t MACMDIOAR;\n  __IO uint32_t MACMDIODR;\n  uint32_t      RESERVED12[2];\n  __IO uint32_t MACARPAR;\n  uint32_t      RESERVED13[59];\n  __IO uint32_t MACA0HR;\n  __IO uint32_t MACA0LR;\n  __IO uint32_t MACA1HR;\n  __IO uint32_t MACA1LR;\n  __IO uint32_t MACA2HR;\n  __IO uint32_t MACA2LR;\n  __IO uint32_t MACA3HR;\n  __IO uint32_t MACA3LR;\n  uint32_t      RESERVED14[248];\n  __IO uint32_t MMCCR;\n  __IO uint32_t MMCRIR;\n  __IO uint32_t MMCTIR;\n  __IO uint32_t MMCRIMR;\n  __IO uint32_t MMCTIMR;\n  uint32_t      RESERVED15[14];\n  __IO uint32_t MMCTSCGPR;\n  __IO uint32_t MMCTMCGPR;\n  uint32_t      RESERVED16[5];\n  __IO uint32_t MMCTPCGR;\n  uint32_t      RESERVED17[10];\n  __IO uint32_t MMCRCRCEPR;\n  __IO uint32_t MMCRAEPR;\n  uint32_t      RESERVED18[10];\n  __IO uint32_t MMCRUPGR;\n  uint32_t      RESERVED19[9];\n  __IO uint32_t MMCTLPIMSTR;\n  __IO uint32_t MMCTLPITCR;\n  __IO uint32_t MMCRLPIMSTR;\n  __IO uint32_t MMCRLPITCR;\n  uint32_t      RESERVED20[65];\n  __IO uint32_t MACL3L4C0R;\n  __IO uint32_t MACL4A0R;\n  uint32_t      RESERVED21[2];\n  __IO uint32_t MACL3A0R0R;\n  __IO uint32_t MACL3A1R0R;\n  __IO uint32_t MACL3A2R0R;\n  __IO uint32_t MACL3A3R0R;\n  uint32_t      RESERVED22[4];\n  __IO uint32_t MACL3L4C1R;\n  __IO uint32_t MACL4A1R;\n  uint32_t      RESERVED23[2];\n  __IO uint32_t MACL3A0R1R;\n  __IO uint32_t MACL3A1R1R;\n  __IO uint32_t MACL3A2R1R;\n  __IO uint32_t MACL3A3R1R;\n  uint32_t      RESERVED24[108];\n  __IO uint32_t MACTSCR;\n  __IO uint32_t MACSSIR;\n  __IO uint32_t MACSTSR;\n  __IO uint32_t MACSTNR;\n  __IO uint32_t MACSTSUR;\n  __IO uint32_t MACSTNUR;\n  __IO uint32_t MACTSAR;\n  uint32_t      RESERVED25;\n  __IO uint32_t MACTSSR;\n  uint32_t      RESERVED26[3];\n  __IO uint32_t MACTTSSNR;\n  __IO uint32_t MACTTSSSR;\n  uint32_t      RESERVED27[2];\n  __IO uint32_t MACACR;\n  uint32_t      RESERVED28;\n  __IO uint32_t MACATSNR;\n  __IO uint32_t MACATSSR;\n  __IO uint32_t MACTSIACR;\n  __IO uint32_t MACTSEACR;\n  __IO uint32_t MACTSICNR;\n  __IO uint32_t MACTSECNR;\n  uint32_t      RESERVED29[4];\n  __IO uint32_t MACPPSCR;\n  uint32_t      RESERVED30[3];\n  __IO uint32_t MACPPSTTSR;\n  __IO uint32_t MACPPSTTNR;\n  __IO uint32_t MACPPSIR;\n  __IO uint32_t MACPPSWR;\n  uint32_t      RESERVED31[12];\n  __IO uint32_t MACPOCR;\n  __IO uint32_t MACSPI0R;\n  __IO uint32_t MACSPI1R;\n  __IO uint32_t MACSPI2R;\n  __IO uint32_t MACLMIR;\n  uint32_t      RESERVED32[11];\n  __IO uint32_t MTLOMR;\n  uint32_t      RESERVED33[7];\n  __IO uint32_t MTLISR;\n  uint32_t      RESERVED34[55];\n  __IO uint32_t MTLTQOMR;\n  __IO uint32_t MTLTQUR;\n  __IO uint32_t MTLTQDR;\n  uint32_t      RESERVED35[8];\n  __IO uint32_t MTLQICSR;\n  __IO uint32_t MTLRQOMR;\n  __IO uint32_t MTLRQMPOCR;\n  __IO uint32_t MTLRQDR;\n  uint32_t      RESERVED36[177];\n  __IO uint32_t DMAMR;\n  __IO uint32_t DMASBMR;\n  __IO uint32_t DMAISR;\n  __IO uint32_t DMADSR;\n  uint32_t      RESERVED37[60];\n  __IO uint32_t DMACCR;\n  __IO uint32_t DMACTCR;\n  __IO uint32_t DMACRCR;\n  uint32_t      RESERVED38[2];\n  __IO uint32_t DMACTDLAR;\n  uint32_t      RESERVED39;\n  __IO uint32_t DMACRDLAR;\n  __IO uint32_t DMACTDTPR;\n  uint32_t      RESERVED40;\n  __IO uint32_t DMACRDTPR;\n  __IO uint32_t DMACTDRLR;\n  __IO uint32_t DMACRDRLR;\n  __IO uint32_t DMACIER;\n  __IO uint32_t DMACRIWTR;\n__IO uint32_t DMACSFCSR;\n  uint32_t      RESERVED41;\n  __IO uint32_t DMACCATDR;\n  uint32_t      RESERVED42;\n  __IO uint32_t DMACCARDR;\n  uint32_t      RESERVED43;\n  __IO uint32_t DMACCATBR;\n  uint32_t      RESERVED44;\n  __IO uint32_t DMACCARBR;\n  __IO uint32_t DMACSR;\nuint32_t      RESERVED45[2];\n__IO uint32_t DMACMFCR;\n}ETH_TypeDef;\n/**\n  * @brief External Interrupt/Event Controller\n  */\n\ntypedef struct\n{\n__IO uint32_t RTSR1;               /*!< EXTI Rising trigger selection register,          Address offset: 0x00 */\n__IO uint32_t FTSR1;               /*!< EXTI Falling trigger selection register,         Address offset: 0x04 */\n__IO uint32_t SWIER1;              /*!< EXTI Software interrupt event register,          Address offset: 0x08 */\n__IO uint32_t D3PMR1;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR1) Address offset: 0x0C */\n__IO uint32_t D3PCR1L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR1L)     Address offset: 0x10 */\n__IO uint32_t D3PCR1H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR1H)   Address offset: 0x14 */\nuint32_t      RESERVED1[2];        /*!< Reserved,                                        0x18 to 0x1C         */\n__IO uint32_t RTSR2;               /*!< EXTI Rising trigger selection register,          Address offset: 0x20 */\n__IO uint32_t FTSR2;               /*!< EXTI Falling trigger selection register,         Address offset: 0x24 */\n__IO uint32_t SWIER2;              /*!< EXTI Software interrupt event register,          Address offset: 0x28 */\n__IO uint32_t D3PMR2;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR2) Address offset: 0x2C */\n__IO uint32_t D3PCR2L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR2L)  Address offset: 0x30 */\n__IO uint32_t D3PCR2H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR2H) Address offset: 0x34 */\nuint32_t      RESERVED2[2];        /*!< Reserved,                                        0x38 to 0x3C         */\n__IO uint32_t RTSR3;               /*!< EXTI Rising trigger selection register,          Address offset: 0x40 */\n__IO uint32_t FTSR3;               /*!< EXTI Falling trigger selection register,         Address offset: 0x44 */\n__IO uint32_t SWIER3;              /*!< EXTI Software interrupt event register,          Address offset: 0x48 */\n__IO uint32_t D3PMR3;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR3) Address offset: 0x4C */\n__IO uint32_t D3PCR3L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR3L) Address offset: 0x50 */\n__IO uint32_t D3PCR3H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR3H) Address offset: 0x54 */\nuint32_t      RESERVED3[10];       /*!< Reserved,                                        0x58 to 0x7C         */\n__IO uint32_t IMR1;                /*!< EXTI Interrupt mask register,                    Address offset: 0x80 */\n__IO uint32_t EMR1;                /*!< EXTI Event mask register,                        Address offset: 0x84 */\n__IO uint32_t PR1;                 /*!< EXTI Pending register,                           Address offset: 0x88 */\nuint32_t      RESERVED4;           /*!< Reserved,                                        0x8C                 */\n__IO uint32_t IMR2;                /*!< EXTI Interrupt mask register,                    Address offset: 0x90 */\n__IO uint32_t EMR2;                /*!< EXTI Event mask register,                        Address offset: 0x94 */\n__IO uint32_t PR2;                 /*!< EXTI Pending register,                           Address offset: 0x98 */\nuint32_t      RESERVED5;           /*!< Reserved,                                        0x9C                 */\n__IO uint32_t IMR3;                /*!< EXTI Interrupt mask register,                    Address offset: 0xA0 */\n__IO uint32_t EMR3;                /*!< EXTI Event mask register,                        Address offset: 0xA4 */\n__IO uint32_t PR3;                 /*!< EXTI Pending register,                           Address offset: 0xA8 */\n}EXTI_TypeDef;\n\n/**\n  * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2\n  *        with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.\n  *        Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:\n  *           IMR1   in case of EXTI_D1 that is addressing CPU1 (Cortex-M7)\n  *           C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4)\n  *        Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only\n  */\n\ntypedef struct\n{\n__IO uint32_t IMR1;                /*!< EXTI Interrupt mask register,                Address offset: 0x00 */\n__IO uint32_t EMR1;                /*!< EXTI Event mask register,                    Address offset: 0x04 */\n__IO uint32_t PR1;                 /*!< EXTI Pending register,                       Address offset: 0x08 */\nuint32_t      RESERVED1;           /*!< Reserved, 0x0C                                                    */\n__IO uint32_t IMR2;                /*!< EXTI Interrupt mask register,                Address offset: 0x10 */\n__IO uint32_t EMR2;                /*!< EXTI Event mask register,                    Address offset: 0x14 */\n__IO uint32_t PR2;                 /*!< EXTI Pending register,                       Address offset: 0x18 */\nuint32_t      RESERVED2;           /*!< Reserved, 0x1C                                                    */\n__IO uint32_t IMR3;                /*!< EXTI Interrupt mask register,                Address offset: 0x20 */\n__IO uint32_t EMR3;                /*!< EXTI Event mask register,                    Address offset: 0x24 */\n__IO uint32_t PR3;                 /*!< EXTI Pending register,                       Address offset: 0x28 */\n}EXTI_Core_TypeDef;\n\n\n/**\n  * @brief FLASH Registers\n  */\n\ntypedef struct\n{\n  __IO uint32_t ACR;             /*!< FLASH access control register,                            Address offset: 0x00  */\n  __IO uint32_t KEYR1;           /*!< Flash Key Register for bank1,                             Address offset: 0x04  */\n  __IO uint32_t OPTKEYR;         /*!< Flash Option Key Register,                                Address offset: 0x08  */\n  __IO uint32_t CR1;             /*!< Flash Control Register for bank1,                         Address offset: 0x0C  */\n  __IO uint32_t SR1;             /*!< Flash Status Register for bank1,                          Address offset: 0x10  */\n  __IO uint32_t CCR1;            /*!< Flash Control Register for bank1,                         Address offset: 0x14  */\n  __IO uint32_t OPTCR;           /*!< Flash Option Control Register,                            Address offset: 0x18  */\n  __IO uint32_t OPTSR_CUR;       /*!< Flash Option Status Current Register,                     Address offset: 0x1C  */\n  __IO uint32_t OPTSR_PRG;       /*!< Flash Option Status to Program Register,                  Address offset: 0x20  */\n  __IO uint32_t OPTCCR;          /*!< Flash Option Clear Control Register,                      Address offset: 0x24  */\n  __IO uint32_t PRAR_CUR1;       /*!< Flash Current Protection Address Register for bank1,      Address offset: 0x28  */\n  __IO uint32_t PRAR_PRG1;       /*!< Flash Protection Address to Program Register for bank1,   Address offset: 0x2C  */\n  __IO uint32_t SCAR_CUR1;       /*!< Flash Current Secure Address Register for bank1,          Address offset: 0x30  */\n  __IO uint32_t SCAR_PRG1;       /*!< Flash Secure Address to Program Register for bank1,       Address offset: 0x34  */\n  __IO uint32_t WPSN_CUR1;       /*!< Flash Current Write Protection Register on bank1,         Address offset: 0x38  */\n  __IO uint32_t WPSN_PRG1;       /*!< Flash Write Protection to Program Register on bank1,      Address offset: 0x3C  */\n  __IO uint32_t BOOT_CUR;        /*!< Flash Current Boot Address for Pelican Core Register,     Address offset: 0x40  */\n  __IO uint32_t BOOT_PRG;        /*!< Flash Boot Address to Program for Pelican Core Register,  Address offset: 0x44  */\n  uint32_t      RESERVED0[2];    /*!< Reserved, 0x48 to 0x4C                                                          */\n  __IO uint32_t CRCCR1;          /*!< Flash CRC Control register For Bank1 Register ,           Address offset: 0x50  */\n  __IO uint32_t CRCSADD1;        /*!< Flash CRC Start Address Register for Bank1 ,              Address offset: 0x54  */\n  __IO uint32_t CRCEADD1;        /*!< Flash CRC End Address Register for Bank1 ,                Address offset: 0x58  */\n  __IO uint32_t CRCDATA;         /*!< Flash CRC Data Register for Bank1 ,                       Address offset: 0x5C  */\n  __IO uint32_t ECC_FA1;         /*!< Flash ECC Fail Address For Bank1 Register ,               Address offset: 0x60  */\n  uint32_t      RESERVED1[40];   /*!< Reserved, 0x64 to 0x100                                                         */\n  __IO uint32_t KEYR2;           /*!< Flash Key Register for bank2,                             Address offset: 0x104 */\n  uint32_t      RESERVED2;       /*!< Reserved, 0x108                                                                 */\n  __IO uint32_t CR2;             /*!< Flash Control Register for bank2,                         Address offset: 0x10C */\n  __IO uint32_t SR2;             /*!< Flash Status Register for bank2,                          Address offset: 0x110 */\n  __IO uint32_t CCR2;            /*!< Flash Status Register for bank2,                          Address offset: 0x114 */\n  uint32_t      RESERVED3[4];    /*!< Reserved, 0x118 to 0x124                                                        */\n  __IO uint32_t PRAR_CUR2;       /*!< Flash Current Protection Address Register for bank2,      Address offset: 0x128 */\n  __IO uint32_t PRAR_PRG2;       /*!< Flash Protection Address to Program Register for bank2,   Address offset: 0x12C */\n  __IO uint32_t SCAR_CUR2;       /*!< Flash Current Secure Address Register for bank2,          Address offset: 0x130 */\n  __IO uint32_t SCAR_PRG2;       /*!< Flash Secure Address Register for bank2,                  Address offset: 0x134 */\n  __IO uint32_t WPSN_CUR2;       /*!< Flash Current Write Protection Register on bank2,         Address offset: 0x138 */\n  __IO uint32_t WPSN_PRG2;       /*!< Flash Write Protection to Program Register on bank2,      Address offset: 0x13C */\n  uint32_t      RESERVED4[4];    /*!< Reserved, 0x140 to 0x14C                                                        */\n  __IO uint32_t CRCCR2;          /*!< Flash CRC Control register For Bank2 Register ,           Address offset: 0x150 */\n  __IO uint32_t CRCSADD2;        /*!< Flash CRC Start Address Register for Bank2 ,              Address offset: 0x154 */\n  __IO uint32_t CRCEADD2;        /*!< Flash CRC End Address Register for Bank2 ,                Address offset: 0x158 */\n  __IO uint32_t CRCDATA2;        /*!< Flash CRC Data Register for Bank2 ,                       Address offset: 0x15C */\n  __IO uint32_t ECC_FA2;         /*!< Flash ECC Fail Address For Bank2 Register ,               Address offset: 0x160 */\n} FLASH_TypeDef;\n\n/**\n  * @brief Flexible Memory Controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */\n} FMC_Bank1_TypeDef;\n\n/**\n  * @brief Flexible Memory Controller Bank1E\n  */\n\ntypedef struct\n{\n  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */\n} FMC_Bank1E_TypeDef;\n\n/**\n  * @brief Flexible Memory Controller Bank2\n  */\n\ntypedef struct\n{\n  __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */\n  __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */\n  __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */\n  __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */\n  uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */\n  __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */\n} FMC_Bank2_TypeDef;\n\n/**\n  * @brief Flexible Memory Controller Bank3\n  */\n\ntypedef struct\n{\n  __IO uint32_t PCR;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */\n  __IO uint32_t SR;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */\n  __IO uint32_t PMEM;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */\n  __IO uint32_t PATT;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */\n  uint32_t      RESERVED;  /*!< Reserved, 0x90                                                            */\n  __IO uint32_t ECCR;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */\n} FMC_Bank3_TypeDef;\n\n/**\n  * @brief Flexible Memory Controller Bank5 and 6\n  */\n\n\ntypedef struct\n{\n  __IO uint32_t SDCR[2];        /*!< SDRAM Control registers ,      Address offset: 0x140-0x144  */\n  __IO uint32_t SDTR[2];        /*!< SDRAM Timing registers ,       Address offset: 0x148-0x14C  */\n  __IO uint32_t SDCMR;       /*!< SDRAM Command Mode register,    Address offset: 0x150  */\n  __IO uint32_t SDRTR;       /*!< SDRAM Refresh Timer register,   Address offset: 0x154  */\n  __IO uint32_t SDSR;        /*!< SDRAM Status register,          Address offset: 0x158  */\n} FMC_Bank5_6_TypeDef;\n\n/**\n  * @brief General Purpose I/O\n  */\n\ntypedef struct\n{\n  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */\n  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */\n  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */\n  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */\n  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */\n  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */\n  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset,               Address offset: 0x18      */\n  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */\n  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */\n} GPIO_TypeDef;\n\n/**\n  * @brief Operational Amplifier (OPAMP)\n  */\n\ntypedef struct\n{\n  __IO uint32_t CSR;          /*!< OPAMP control/status register,                      Address offset: 0x00 */\n  __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode,     Address offset: 0x04 */\n  __IO uint32_t HSOTR;        /*!< OPAMP offset trimming register for high speed mode, Address offset: 0x08 */\n} OPAMP_TypeDef;\n\n/**\n  * @brief System configuration controller\n  */\n\ntypedef struct\n{\n uint32_t RESERVED1;           /*!< Reserved,                                           Address offset: 0x00        */\n __IO uint32_t PMCR;           /*!< SYSCFG peripheral mode configuration register,      Address offset: 0x04        */\n __IO uint32_t EXTICR[4];      /*!< SYSCFG external interrupt configuration registers,  Address offset: 0x08-0x14   */\n __IO uint32_t CFGR;           /*!< SYSCFG configuration registers,                     Address offset: 0x18        */\n uint32_t RESERVED2;           /*!< Reserved,                                           Address offset: 0x1C        */\n __IO uint32_t CCCSR;          /*!< SYSCFG compensation cell control/status register,   Address offset: 0x20        */\n __IO uint32_t CCVR;           /*!< SYSCFG compensation cell value register,            Address offset: 0x24        */\n __IO uint32_t CCCR;           /*!< SYSCFG compensation cell code register,             Address offset: 0x28        */\n __IO uint32_t PWRCR;          /*!< PWR control register,                               Address offset: 0x2C        */\n  uint32_t     RESERVED3[61];  /*!< Reserved, 0x30-0x120                                                            */\n  __IO uint32_t PKGR;          /*!< SYSCFG package register,                            Address offset: 0x124       */\n  uint32_t     RESERVED4[118]; /*!< Reserved, 0x128-0x2FC                                                           */\n __IO uint32_t UR0;            /*!< SYSCFG user register 0,                             Address offset: 0x300       */\n __IO uint32_t UR1;            /*!< SYSCFG user register 1,                             Address offset: 0x304       */\n __IO uint32_t UR2;            /*!< SYSCFG user register 2,                             Address offset: 0x308       */\n __IO uint32_t UR3;            /*!< SYSCFG user register 3,                             Address offset: 0x30C       */\n __IO uint32_t UR4;            /*!< SYSCFG user register 4,                             Address offset: 0x310       */\n __IO uint32_t UR5;            /*!< SYSCFG user register 5,                             Address offset: 0x314       */\n __IO uint32_t UR6;            /*!< SYSCFG user register 6,                             Address offset: 0x318       */\n __IO uint32_t UR7;            /*!< SYSCFG user register 7,                             Address offset: 0x31C       */\n __IO uint32_t UR8;            /*!< SYSCFG user register 8,                             Address offset: 0x320       */\n __IO uint32_t UR9;            /*!< SYSCFG user register 9,                             Address offset: 0x324       */\n __IO uint32_t UR10;           /*!< SYSCFG user register 10,                            Address offset: 0x328       */\n __IO uint32_t UR11;           /*!< SYSCFG user register 11,                            Address offset: 0x32C       */\n __IO uint32_t UR12;           /*!< SYSCFG user register 12,                            Address offset: 0x330       */\n __IO uint32_t UR13;           /*!< SYSCFG user register 13,                            Address offset: 0x334       */\n __IO uint32_t UR14;           /*!< SYSCFG user register 14,                            Address offset: 0x338       */\n __IO uint32_t UR15;           /*!< SYSCFG user register 15,                            Address offset: 0x33C       */\n __IO uint32_t UR16;           /*!< SYSCFG user register 16,                            Address offset: 0x340       */\n __IO uint32_t UR17;           /*!< SYSCFG user register 17,                            Address offset: 0x344       */\n\n} SYSCFG_TypeDef;\n\n/**\n  * @brief Inter-integrated Circuit Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */\n  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */\n  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */\n  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */\n  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */\n  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */\n  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */\n  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */\n  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */\n  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */\n  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */\n} I2C_TypeDef;\n\n/**\n  * @brief Independent WATCHDOG\n  */\n\ntypedef struct\n{\n  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */\n  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */\n  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */\n  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */\n  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */\n} IWDG_TypeDef;\n\n\n/**\n  * @brief JPEG Codec\n  */\ntypedef struct\n{\n  __IO uint32_t CONFR0;          /*!< JPEG Codec Control Register (JPEG_CONFR0),        Address offset: 00h       */\n  __IO uint32_t CONFR1;          /*!< JPEG Codec Control Register (JPEG_CONFR1),        Address offset: 04h       */\n  __IO uint32_t CONFR2;          /*!< JPEG Codec Control Register (JPEG_CONFR2),        Address offset: 08h       */\n  __IO uint32_t CONFR3;          /*!< JPEG Codec Control Register (JPEG_CONFR3),        Address offset: 0Ch       */\n  __IO uint32_t CONFR4;          /*!< JPEG Codec Control Register (JPEG_CONFR4),        Address offset: 10h       */\n  __IO uint32_t CONFR5;          /*!< JPEG Codec Control Register (JPEG_CONFR5),        Address offset: 14h       */\n  __IO uint32_t CONFR6;          /*!< JPEG Codec Control Register (JPEG_CONFR6),        Address offset: 18h       */\n  __IO uint32_t CONFR7;          /*!< JPEG Codec Control Register (JPEG_CONFR7),        Address offset: 1Ch       */\n  uint32_t  Reserved20[4];       /* Reserved                                            Address offset: 20h-2Ch   */\n  __IO uint32_t CR;              /*!< JPEG Control Register (JPEG_CR),                  Address offset: 30h       */\n  __IO uint32_t SR;              /*!< JPEG Status Register (JPEG_SR),                   Address offset: 34h       */\n  __IO uint32_t CFR;             /*!< JPEG Clear Flag Register (JPEG_CFR),              Address offset: 38h       */\n  uint32_t  Reserved3c;          /* Reserved                                            Address offset: 3Ch       */\n  __IO uint32_t DIR;             /*!< JPEG Data Input Register (JPEG_DIR),              Address offset: 40h       */\n  __IO uint32_t DOR;             /*!< JPEG Data Output Register (JPEG_DOR),             Address offset: 44h       */\n  uint32_t  Reserved48[2];       /* Reserved                                            Address offset: 48h-4Ch   */\n  __IO uint32_t QMEM0[16];       /*!< JPEG quantization tables 0,                       Address offset: 50h-8Ch   */\n  __IO uint32_t QMEM1[16];       /*!< JPEG quantization tables 1,                       Address offset: 90h-CCh   */\n  __IO uint32_t QMEM2[16];       /*!< JPEG quantization tables 2,                       Address offset: D0h-10Ch  */\n  __IO uint32_t QMEM3[16];       /*!< JPEG quantization tables 3,                       Address offset: 110h-14Ch */\n  __IO uint32_t HUFFMIN[16];     /*!< JPEG HuffMin tables,                              Address offset: 150h-18Ch */\n  __IO uint32_t HUFFBASE[32];    /*!< JPEG HuffSymb tables,                             Address offset: 190h-20Ch */\n  __IO uint32_t HUFFSYMB[84];    /*!< JPEG HUFFSYMB tables,                             Address offset: 210h-35Ch */\n  __IO uint32_t DHTMEM[103];     /*!< JPEG DHTMem tables,                               Address offset: 360h-4F8h */\n  uint32_t  Reserved4FC;         /* Reserved                                            Address offset: 4FCh      */\n  __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0,                 Address offset: 500h-65Ch */\n  __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1,                 Address offset: 660h-7BCh */\n  __IO uint32_t HUFFENC_DC0[8];  /*!< JPEG encodor, DC Huffman table 0,                 Address offset: 7C0h-7DCh */\n  __IO uint32_t HUFFENC_DC1[8];  /*!< JPEG encodor, DC Huffman table 1,                 Address offset: 7E0h-7FCh */\n\n} JPEG_TypeDef;\n\n/**\n  * @brief LCD-TFT Display Controller\n  */\n\ntypedef struct\n{\n  uint32_t      RESERVED0[2];  /*!< Reserved, 0x00-0x04                                                       */\n  __IO uint32_t SSCR;          /*!< LTDC Synchronization Size Configuration Register,    Address offset: 0x08 */\n  __IO uint32_t BPCR;          /*!< LTDC Back Porch Configuration Register,              Address offset: 0x0C */\n  __IO uint32_t AWCR;          /*!< LTDC Active Width Configuration Register,            Address offset: 0x10 */\n  __IO uint32_t TWCR;          /*!< LTDC Total Width Configuration Register,             Address offset: 0x14 */\n  __IO uint32_t GCR;           /*!< LTDC Global Control Register,                        Address offset: 0x18 */\n  uint32_t      RESERVED1[2];  /*!< Reserved, 0x1C-0x20                                                       */\n  __IO uint32_t SRCR;          /*!< LTDC Shadow Reload Configuration Register,           Address offset: 0x24 */\n  uint32_t      RESERVED2[1];  /*!< Reserved, 0x28                                                            */\n  __IO uint32_t BCCR;          /*!< LTDC Background Color Configuration Register,        Address offset: 0x2C */\n  uint32_t      RESERVED3[1];  /*!< Reserved, 0x30                                                            */\n  __IO uint32_t IER;           /*!< LTDC Interrupt Enable Register,                      Address offset: 0x34 */\n  __IO uint32_t ISR;           /*!< LTDC Interrupt Status Register,                      Address offset: 0x38 */\n  __IO uint32_t ICR;           /*!< LTDC Interrupt Clear Register,                       Address offset: 0x3C */\n  __IO uint32_t LIPCR;         /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */\n  __IO uint32_t CPSR;          /*!< LTDC Current Position Status Register,               Address offset: 0x44 */\n  __IO uint32_t CDSR;         /*!< LTDC Current Display Status Register,                 Address offset: 0x48 */\n} LTDC_TypeDef;\n\n/**\n  * @brief LCD-TFT Display layer x Controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;            /*!< LTDC Layerx Control Register                                  Address offset: 0x84 */\n  __IO uint32_t WHPCR;         /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */\n  __IO uint32_t WVPCR;         /*!< LTDC Layerx Window Vertical Position Configuration Register   Address offset: 0x8C */\n  __IO uint32_t CKCR;          /*!< LTDC Layerx Color Keying Configuration Register               Address offset: 0x90 */\n  __IO uint32_t PFCR;          /*!< LTDC Layerx Pixel Format Configuration Register               Address offset: 0x94 */\n  __IO uint32_t CACR;          /*!< LTDC Layerx Constant Alpha Configuration Register             Address offset: 0x98 */\n  __IO uint32_t DCCR;          /*!< LTDC Layerx Default Color Configuration Register              Address offset: 0x9C */\n  __IO uint32_t BFCR;          /*!< LTDC Layerx Blending Factors Configuration Register           Address offset: 0xA0 */\n  uint32_t      RESERVED0[2];  /*!< Reserved */\n  __IO uint32_t CFBAR;         /*!< LTDC Layerx Color Frame Buffer Address Register               Address offset: 0xAC */\n  __IO uint32_t CFBLR;         /*!< LTDC Layerx Color Frame Buffer Length Register                Address offset: 0xB0 */\n  __IO uint32_t CFBLNR;        /*!< LTDC Layerx ColorFrame Buffer Line Number Register            Address offset: 0xB4 */\n  uint32_t      RESERVED1[3];  /*!< Reserved */\n  __IO uint32_t CLUTWR;         /*!< LTDC Layerx CLUT Write Register                               Address offset: 0x144 */\n\n} LTDC_Layer_TypeDef;\n\n/**\n  * @brief Power Control\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR1;       /*!< PWR power control register 1,            Address offset: 0x00 */\n  __IO uint32_t CSR1;      /*!< PWR power control status register 1,     Address offset: 0x04 */\n  __IO uint32_t CR2;       /*!< PWR power control register 2,            Address offset: 0x08 */\n  __IO uint32_t CR3;       /*!< PWR power control register 3,            Address offset: 0x0C */\n  __IO uint32_t CPUCR;     /*!< PWR CPU control register,                Address offset: 0x10 */\n       uint32_t RESERVED0; /*!< Reserved,                                Address offset: 0x14 */\n  __IO uint32_t D3CR;      /*!< PWR D3 domain control register,          Address offset: 0x18 */\n       uint32_t RESERVED1; /*!< Reserved,                                Address offset: 0x1C */\n  __IO uint32_t WKUPCR;    /*!< PWR wakeup clear register,               Address offset: 0x20 */\n  __IO uint32_t WKUPFR;    /*!< PWR wakeup flag register,                Address offset: 0x24 */\n  __IO uint32_t WKUPEPR;   /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */\n} PWR_TypeDef;\n\n/**\n  * @brief Reset and Clock Control\n  */\n\ntypedef struct\n{\n __IO uint32_t CR;             /*!< RCC clock control register,                                              Address offset: 0x00  */\n __IO uint32_t HSICFGR;        /*!< HSI Clock Calibration Register,                                          Address offset: 0x04  */\n __IO uint32_t CRRCR;          /*!< Clock Recovery RC  Register,                                             Address offset: 0x08  */\n __IO uint32_t CSICFGR;        /*!< CSI Clock Calibration Register,                                          Address offset: 0x0C  */\n __IO uint32_t CFGR;           /*!< RCC clock configuration register,                                        Address offset: 0x10  */\n uint32_t     RESERVED1;       /*!< Reserved,                                                                Address offset: 0x14  */\n __IO uint32_t D1CFGR;         /*!< RCC Domain 1 configuration register,                                     Address offset: 0x18  */\n __IO uint32_t D2CFGR;         /*!< RCC Domain 2 configuration register,                                     Address offset: 0x1C  */\n __IO uint32_t D3CFGR;         /*!< RCC Domain 3 configuration register,                                     Address offset: 0x20  */\n uint32_t     RESERVED2;       /*!< Reserved,                                                                Address offset: 0x24  */\n __IO uint32_t PLLCKSELR;      /*!< RCC PLLs Clock Source Selection Register,                                Address offset: 0x28  */\n __IO uint32_t PLLCFGR;        /*!< RCC PLLs  Configuration Register,                                        Address offset: 0x2C  */\n __IO uint32_t PLL1DIVR;       /*!< RCC PLL1 Dividers Configuration Register,                                Address offset: 0x30  */\n __IO uint32_t PLL1FRACR;      /*!< RCC PLL1 Fractional Divider Configuration Register,                      Address offset: 0x34  */\n __IO uint32_t PLL2DIVR;       /*!< RCC PLL2 Dividers Configuration Register,                                Address offset: 0x38  */\n __IO uint32_t PLL2FRACR;      /*!< RCC PLL2 Fractional Divider Configuration Register,                      Address offset: 0x3C  */\n __IO uint32_t PLL3DIVR;       /*!< RCC PLL3 Dividers Configuration Register,                                Address offset: 0x40  */\n __IO uint32_t PLL3FRACR;      /*!< RCC PLL3 Fractional Divider Configuration Register,                      Address offset: 0x44  */\n uint32_t      RESERVED3;      /*!< Reserved,                                                                Address offset: 0x48  */\n __IO uint32_t  D1CCIPR;       /*!< RCC Domain 1 Kernel Clock Configuration Register                         Address offset: 0x4C  */\n __IO uint32_t  D2CCIP1R;      /*!< RCC Domain 2 Kernel Clock Configuration Register                         Address offset: 0x50  */\n __IO uint32_t  D2CCIP2R;      /*!< RCC Domain 2 Kernel Clock Configuration Register                         Address offset: 0x54  */\n __IO uint32_t  D3CCIPR;       /*!< RCC Domain 3 Kernel Clock Configuration Register                         Address offset: 0x58  */\n uint32_t      RESERVED4;      /*!< Reserved,                                                                Address offset: 0x5C  */\n __IO uint32_t  CIER;          /*!< RCC Clock Source Interrupt Enable Register                               Address offset: 0x60  */\n __IO uint32_t  CIFR;          /*!< RCC Clock Source Interrupt Flag Register                                 Address offset: 0x64  */\n __IO uint32_t  CICR;          /*!< RCC Clock Source Interrupt Clear Register                                Address offset: 0x68  */\n uint32_t     RESERVED5;       /*!< Reserved,                                                                Address offset: 0x6C  */\n __IO uint32_t  BDCR;          /*!< RCC Vswitch Backup Domain Control Register,                              Address offset: 0x70  */\n __IO uint32_t  CSR;           /*!< RCC clock control & status register,                                     Address offset: 0x74  */\n uint32_t     RESERVED6;       /*!< Reserved,                                                                Address offset: 0x78  */\n __IO uint32_t AHB3RSTR;       /*!< RCC AHB3 peripheral reset register,                                      Address offset: 0x7C  */\n __IO uint32_t AHB1RSTR;       /*!< RCC AHB1 peripheral reset register,                                      Address offset: 0x80  */\n __IO uint32_t AHB2RSTR;       /*!< RCC AHB2 peripheral reset register,                                      Address offset: 0x84  */\n __IO uint32_t AHB4RSTR;       /*!< RCC AHB4 peripheral reset register,                                      Address offset: 0x88  */\n __IO uint32_t APB3RSTR;       /*!< RCC APB3 peripheral reset register,                                      Address offset: 0x8C  */\n __IO uint32_t APB1LRSTR;      /*!< RCC APB1 peripheral reset Low Word register,                             Address offset: 0x90  */\n __IO uint32_t APB1HRSTR;      /*!< RCC APB1 peripheral reset High Word register,                            Address offset: 0x94  */\n __IO uint32_t APB2RSTR;       /*!< RCC APB2 peripheral reset register,                                      Address offset: 0x98  */\n __IO uint32_t APB4RSTR;       /*!< RCC APB4 peripheral reset register,                                      Address offset: 0x9C  */\n __IO uint32_t GCR;            /*!< RCC RCC Global Control  Register,                                        Address offset: 0xA0  */\n uint32_t     RESERVED8;       /*!< Reserved,                                                                Address offset: 0xA4  */\n __IO uint32_t D3AMR;          /*!< RCC Domain 3 Autonomous Mode Register,                                   Address offset: 0xA8  */\n uint32_t     RESERVED11[9];    /*!< Reserved, 0xAC-0xCC                                                      Address offset: 0xAC  */\n __IO uint32_t RSR;            /*!< RCC Reset status register,                                               Address offset: 0xD0  */\n __IO uint32_t AHB3ENR;        /*!< RCC AHB3 peripheral clock  register,                                     Address offset: 0xD4  */\n __IO uint32_t AHB1ENR;        /*!< RCC AHB1 peripheral clock  register,                                     Address offset: 0xD8  */\n __IO uint32_t AHB2ENR;        /*!< RCC AHB2 peripheral clock  register,                                     Address offset: 0xDC  */\n __IO uint32_t AHB4ENR;        /*!< RCC AHB4 peripheral clock  register,                                     Address offset: 0xE0  */\n __IO uint32_t APB3ENR;        /*!< RCC APB3 peripheral clock  register,                                     Address offset: 0xE4  */\n __IO uint32_t APB1LENR;       /*!< RCC APB1 peripheral clock  Low Word register,                            Address offset: 0xE8  */\n __IO uint32_t APB1HENR;       /*!< RCC APB1 peripheral clock  High Word register,                           Address offset: 0xEC  */\n __IO uint32_t APB2ENR;        /*!< RCC APB2 peripheral clock  register,                                     Address offset: 0xF0  */\n __IO uint32_t APB4ENR;        /*!< RCC APB4 peripheral clock  register,                                     Address offset: 0xF4  */\n uint32_t      RESERVED12;      /*!< Reserved,                                                                Address offset: 0xF8  */\n __IO uint32_t AHB3LPENR;      /*!< RCC AHB3 peripheral sleep clock  register,                               Address offset: 0xFC  */\n __IO uint32_t AHB1LPENR;      /*!< RCC AHB1 peripheral sleep clock  register,                               Address offset: 0x100 */\n __IO uint32_t AHB2LPENR;      /*!< RCC AHB2 peripheral sleep clock  register,                               Address offset: 0x104 */\n __IO uint32_t AHB4LPENR;      /*!< RCC AHB4 peripheral sleep clock  register,                               Address offset: 0x108 */\n __IO uint32_t APB3LPENR;      /*!< RCC APB3 peripheral sleep clock  register,                               Address offset: 0x10C */\n __IO uint32_t APB1LLPENR;     /*!< RCC APB1 peripheral sleep clock  Low Word register,                      Address offset: 0x110 */\n __IO uint32_t APB1HLPENR;     /*!< RCC APB1 peripheral sleep clock  High Word register,                     Address offset: 0x114 */\n __IO uint32_t APB2LPENR;      /*!< RCC APB2 peripheral sleep clock  register,                               Address offset: 0x118 */\n __IO uint32_t APB4LPENR;      /*!< RCC APB4 peripheral sleep clock  register,                               Address offset: 0x11C */\n uint32_t     RESERVED13[4];   /*!< Reserved, 0x120-0x12C                                                    Address offset: 0x120 */\n\n} RCC_TypeDef;\n\n\n/**\n  * @brief Real-Time Clock\n  */\ntypedef struct\n{\n  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */\n  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */\n  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */\n  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */\n  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */\n  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */\n       uint32_t RESERVED;   /*!< Reserved,                                                  Address offset: 0x18 */\n  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */\n  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */\n  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */\n  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */\n  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */\n  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */\n  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */\n  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */\n  __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */\n  __IO uint32_t TAMPCR;     /*!< RTC tamper configuration register,                         Address offset: 0x40 */\n  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */\n  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */\n  __IO uint32_t OR;         /*!< RTC option register,                                       Address offset: 0x4C */\n  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */\n  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */\n  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */\n  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */\n  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */\n  __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                     Address offset: 0x64 */\n  __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                     Address offset: 0x68 */\n  __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                     Address offset: 0x6C */\n  __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                     Address offset: 0x70 */\n  __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                     Address offset: 0x74 */\n  __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                    Address offset: 0x78 */\n  __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                    Address offset: 0x7C */\n  __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                    Address offset: 0x80 */\n  __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                    Address offset: 0x84 */\n  __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                    Address offset: 0x88 */\n  __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                    Address offset: 0x8C */\n  __IO uint32_t BKP16R;     /*!< RTC backup register 16,                                    Address offset: 0x90 */\n  __IO uint32_t BKP17R;     /*!< RTC backup register 17,                                    Address offset: 0x94 */\n  __IO uint32_t BKP18R;     /*!< RTC backup register 18,                                    Address offset: 0x98 */\n  __IO uint32_t BKP19R;     /*!< RTC backup register 19,                                    Address offset: 0x9C */\n  __IO uint32_t BKP20R;     /*!< RTC backup register 20,                                    Address offset: 0xA0 */\n  __IO uint32_t BKP21R;     /*!< RTC backup register 21,                                    Address offset: 0xA4 */\n  __IO uint32_t BKP22R;     /*!< RTC backup register 22,                                    Address offset: 0xA8 */\n  __IO uint32_t BKP23R;     /*!< RTC backup register 23,                                    Address offset: 0xAC */\n  __IO uint32_t BKP24R;     /*!< RTC backup register 24,                                    Address offset: 0xB0 */\n  __IO uint32_t BKP25R;     /*!< RTC backup register 25,                                    Address offset: 0xB4 */\n  __IO uint32_t BKP26R;     /*!< RTC backup register 26,                                    Address offset: 0xB8 */\n  __IO uint32_t BKP27R;     /*!< RTC backup register 27,                                    Address offset: 0xBC */\n  __IO uint32_t BKP28R;     /*!< RTC backup register 28,                                    Address offset: 0xC0 */\n  __IO uint32_t BKP29R;     /*!< RTC backup register 29,                                    Address offset: 0xC4 */\n  __IO uint32_t BKP30R;     /*!< RTC backup register 30,                                    Address offset: 0xC8 */\n  __IO uint32_t BKP31R;     /*!< RTC backup register 31,                                    Address offset: 0xCC */\n} RTC_TypeDef;\n\n/**\n  * @brief Serial Audio Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t GCR;           /*!< SAI global configuration register, Address offset: 0x00 */\n  uint32_t      RESERVED0[16]; /*!< Reserved, 0x04 - 0x43                                   */\n  __IO uint32_t PDMCR;         /*!< SAI PDM control register,          Address offset: 0x44 */\n  __IO uint32_t PDMDLY;        /*!< SAI PDM delay register,            Address offset: 0x48 */\n} SAI_TypeDef;\n\ntypedef struct\n{\n  __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */\n  __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */\n  __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */\n  __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */\n  __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,      Address offset: 0x14 */\n  __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */\n  __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */\n  __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */\n} SAI_Block_TypeDef;\n\n/**\n  * @brief SPDIF-RX Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t   CR;           /*!< Control register,                   Address offset: 0x00 */\n  __IO uint32_t   IMR;          /*!< Interrupt mask register,            Address offset: 0x04 */\n  __IO uint32_t   SR;           /*!< Status register,                    Address offset: 0x08 */\n  __IO uint32_t   IFCR;         /*!< Interrupt Flag Clear register,      Address offset: 0x0C */\n  __IO uint32_t   DR;           /*!< Data input register,                Address offset: 0x10 */\n  __IO uint32_t   CSR;          /*!< Channel Status register,            Address offset: 0x14 */\n  __IO uint32_t   DIR;          /*!< Debug Information register,         Address offset: 0x18 */\n  uint32_t        RESERVED2;    /*!< Reserved,  0x1A                                          */\n} SPDIFRX_TypeDef;\n\n\n/**\n  * @brief Secure digital input/output Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t POWER;          /*!< SDMMC power control register,             Address offset: 0x00  */\n  __IO uint32_t CLKCR;          /*!< SDMMC clock control register,             Address offset: 0x04  */\n  __IO uint32_t ARG;            /*!< SDMMC argument register,                  Address offset: 0x08  */\n  __IO uint32_t CMD;            /*!< SDMMC command register,                   Address offset: 0x0C  */\n  __I uint32_t  RESPCMD;        /*!< SDMMC command response register,          Address offset: 0x10  */\n  __I uint32_t  RESP1;          /*!< SDMMC response 1 register,                Address offset: 0x14  */\n  __I uint32_t  RESP2;          /*!< SDMMC response 2 register,                Address offset: 0x18  */\n  __I uint32_t  RESP3;          /*!< SDMMC response 3 register,                Address offset: 0x1C  */\n  __I uint32_t  RESP4;          /*!< SDMMC response 4 register,                Address offset: 0x20  */\n  __IO uint32_t DTIMER;         /*!< SDMMC data timer register,                Address offset: 0x24  */\n  __IO uint32_t DLEN;           /*!< SDMMC data length register,               Address offset: 0x28  */\n  __IO uint32_t DCTRL;          /*!< SDMMC data control register,              Address offset: 0x2C  */\n  __I uint32_t  DCOUNT;         /*!< SDMMC data counter register,              Address offset: 0x30  */\n  __I uint32_t  STA;            /*!< SDMMC status register,                    Address offset: 0x34  */\n  __IO uint32_t ICR;            /*!< SDMMC interrupt clear register,           Address offset: 0x38  */\n  __IO uint32_t MASK;           /*!< SDMMC mask register,                      Address offset: 0x3C  */\n  __IO uint32_t ACKTIME;        /*!< SDMMC Acknowledgement timer register,     Address offset: 0x40  */\n  uint32_t      RESERVED0[3];   /*!< Reserved, 0x44 - 0x4C - 0x4C                                    */\n  __IO uint32_t IDMACTRL;       /*!< SDMMC DMA control register,               Address offset: 0x50  */\n  __IO uint32_t IDMABSIZE;      /*!< SDMMC DMA buffer size register,           Address offset: 0x54  */\n  __IO uint32_t IDMABASE0;      /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58  */\n  __IO uint32_t IDMABASE1;      /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C  */\n  uint32_t      RESERVED1[8];   /*!< Reserved, 0x60-0x7C                                             */\n  __IO uint32_t FIFO;           /*!< SDMMC data FIFO register,                 Address offset: 0x80  */\n  uint32_t      RESERVED2[222]; /*!< Reserved, 0x84-0x3F8                                            */\n  __IO uint32_t IPVR;           /*!< SDMMC data FIFO register,                 Address offset: 0x3FC */\n} SDMMC_TypeDef;\n\n\n/**\n  * @brief Delay Block DLYB\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;          /*!< DELAY BLOCK control register,  Address offset: 0x00 */\n  __IO uint32_t CFGR;        /*!< DELAY BLOCK configuration register,  Address offset: 0x04 */\n} DLYB_TypeDef;\n\n/**\n  * @brief HW Semaphore HSEM\n  */\n\ntypedef struct\n{\n  __IO uint32_t R[32];      /*!< 2-step write lock and read back registers,     Address offset: 00h-7Ch  */\n  __IO uint32_t RLR[32];    /*!< 1-step read lock registers,                    Address offset: 80h-FCh  */\n  __IO uint32_t C1IER;      /*!< HSEM Interrupt enable register ,             Address offset: 100h     */\n  __IO uint32_t C1ICR;      /*!< HSEM Interrupt clear register ,              Address offset: 104h     */\n  __IO uint32_t C1ISR;      /*!< HSEM Interrupt Status register ,             Address offset: 108h     */\n  __IO uint32_t C1MISR;     /*!< HSEM Interrupt Masked Status register ,      Address offset: 10Ch     */\n  uint32_t  Reserved[12];   /* Reserved                                       Address offset: 110h-13Ch  */\n  __IO uint32_t CR;         /*!< HSEM Semaphore clear register ,                Address offset: 140h      */\n  __IO uint32_t KEYR;       /*!< HSEM Semaphore clear key register ,            Address offset: 144h      */\n\n} HSEM_TypeDef;\n\ntypedef struct\n{\n  __IO uint32_t IER;        /*!< HSEM interrupt enable register ,                Address offset:   0h     */\n  __IO uint32_t ICR;        /*!< HSEM interrupt clear register ,                 Address offset:   4h     */\n  __IO uint32_t ISR;        /*!< HSEM interrupt status register ,                Address offset:   8h     */\n  __IO uint32_t MISR;       /*!< HSEM masked interrupt status register ,         Address offset:   Ch     */\n} HSEM_Common_TypeDef;\n\n/**\n  * @brief Serial Peripheral Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR1;           /*!< SPI/I2S Control register 1,                      Address offset: 0x00 */\n  __IO uint32_t CR2;           /*!< SPI Control register 2,                          Address offset: 0x04 */\n  __IO uint32_t CFG1;          /*!< SPI Configuration register 1,                    Address offset: 0x08 */\n  __IO uint32_t CFG2;          /*!< SPI Configuration register 2,                    Address offset: 0x0C */\n  __IO uint32_t IER;           /*!< SPI/I2S Interrupt Enable register,               Address offset: 0x10 */\n  __IO uint32_t SR;            /*!< SPI/I2S Status register,                         Address offset: 0x14 */\n  __IO uint32_t IFCR;          /*!< SPI/I2S Interrupt/Status flags clear register,   Address offset: 0x18 */\n  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                        */\n  __IO uint32_t TXDR;          /*!< SPI/I2S Transmit data register,                  Address offset: 0x20 */\n  uint32_t      RESERVED1[3];  /*!< Reserved, 0x24-0x2C                                                   */\n  __IO uint32_t RXDR;          /*!< SPI/I2S Receive data register,                   Address offset: 0x30 */\n  uint32_t      RESERVED2[3];  /*!< Reserved, 0x34-0x3C                                                   */\n  __IO uint32_t CRCPOLY;       /*!< SPI CRC Polynomial register,                     Address offset: 0x40 */\n  __IO uint32_t TXCRC;         /*!< SPI Transmitter CRC register,                    Address offset: 0x44 */\n  __IO uint32_t RXCRC;         /*!< SPI Receiver CRC register,                       Address offset: 0x48 */\n  __IO uint32_t UDRDR;         /*!< SPI Underrun data register,                      Address offset: 0x4C */\n  __IO uint32_t I2SCFGR;       /*!< I2S Configuration register,                      Address offset: 0x50 */\n\n} SPI_TypeDef;\n/**\n  * @brief QUAD Serial Peripheral Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;       /*!< QUADSPI Control register,                           Address offset: 0x00 */\n  __IO uint32_t DCR;      /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */\n  __IO uint32_t SR;       /*!< QUADSPI Status register,                            Address offset: 0x08 */\n  __IO uint32_t FCR;      /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */\n  __IO uint32_t DLR;      /*!< QUADSPI Data Length register,                       Address offset: 0x10 */\n  __IO uint32_t CCR;      /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */\n  __IO uint32_t AR;       /*!< QUADSPI Address register,                           Address offset: 0x18 */\n  __IO uint32_t ABR;      /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */\n  __IO uint32_t DR;       /*!< QUADSPI Data register,                              Address offset: 0x20 */\n  __IO uint32_t PSMKR;    /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */\n  __IO uint32_t PSMAR;    /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */\n  __IO uint32_t PIR;      /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */\n  __IO uint32_t LPTR;     /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */\n} QUADSPI_TypeDef;\n\n/**\n  * @brief TIM\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR1;         /*!< TIM control register 1,                   Address offset: 0x00 */\n  __IO uint32_t CR2;         /*!< TIM control register 2,                   Address offset: 0x04 */\n  __IO uint32_t SMCR;        /*!< TIM slave mode control register,          Address offset: 0x08 */\n  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C */\n  __IO uint32_t SR;          /*!< TIM status register,                      Address offset: 0x10 */\n  __IO uint32_t EGR;         /*!< TIM event generation register,            Address offset: 0x14 */\n  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1,      Address offset: 0x18 */\n  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2,      Address offset: 0x1C */\n  __IO uint32_t CCER;        /*!< TIM capture/compare enable register,      Address offset: 0x20 */\n  __IO uint32_t CNT;         /*!< TIM counter register,                     Address offset: 0x24 */\n  __IO uint32_t PSC;         /*!< TIM prescaler,                            Address offset: 0x28 */\n  __IO uint32_t ARR;         /*!< TIM auto-reload register,                 Address offset: 0x2C */\n  __IO uint32_t RCR;         /*!< TIM repetition counter register,          Address offset: 0x30 */\n  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,           Address offset: 0x34 */\n  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,           Address offset: 0x38 */\n  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,           Address offset: 0x3C */\n  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,           Address offset: 0x40 */\n  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,         Address offset: 0x44 */\n  __IO uint32_t DCR;         /*!< TIM DMA control register,                 Address offset: 0x48 */\n  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,        Address offset: 0x4C */\n  uint32_t      RESERVED1;   /*!< Reserved, 0x50                                                 */\n  __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */\n  __IO uint32_t CCR5;        /*!< TIM capture/compare register5,            Address offset: 0x58 */\n  __IO uint32_t CCR6;        /*!< TIM capture/compare register6,            Address offset: 0x5C */\n  __IO uint32_t AF1;         /*!< TIM alternate function option register 1, Address offset: 0x60 */\n  __IO uint32_t AF2;         /*!< TIM alternate function option register 2, Address offset: 0x64 */\n  __IO uint32_t TISEL;       /*!< TIM Input Selection register,             Address offset: 0x68 */\n} TIM_TypeDef;\n\n/**\n  * @brief LPTIMIMER\n  */\ntypedef struct\n{\n  __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,         Address offset: 0x00 */\n  __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,              Address offset: 0x04 */\n  __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,             Address offset: 0x08 */\n  __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                Address offset: 0x0C */\n  __IO uint32_t CR;       /*!< LPTIM Control register,                      Address offset: 0x10 */\n  __IO uint32_t CMP;      /*!< LPTIM Compare register,                      Address offset: 0x14 */\n  __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                   Address offset: 0x18 */\n  __IO uint32_t CNT;      /*!< LPTIM Counter register,                      Address offset: 0x1C */\n  uint32_t  RESERVED1;    /*!< Reserved, 0x20                                                    */\n  __IO uint32_t CFGR2;    /*!< LPTIM Configuration register,                Address offset: 0x24 */\n} LPTIM_TypeDef;\n\n/**\n  * @brief Comparator\n  */\ntypedef struct\n{\n  __IO uint32_t SR;        /*!< Comparator status register,                    Address offset: 0x00 */\n  __IO uint32_t ICFR;      /*!< Comparator interrupt clear flag register,       Address offset: 0x04 */\n  __IO uint32_t OR;        /*!< Comparator option register,                  Address offset: 0x08 */\n} COMPOPT_TypeDef;\n\ntypedef struct\n{\n  __IO uint32_t CFGR;      /*!< Comparator configuration register  ,           Address offset: 0x00 */\n} COMP_TypeDef;\n\ntypedef struct\n{\n  __IO uint32_t CFGR;       /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */\n} COMP_Common_TypeDef;\n/**\n  * @brief Universal Synchronous Asynchronous Receiver Transmitter\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */\n  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */\n  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */\n  __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */\n  __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */\n  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */\n  __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */\n  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */\n  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */\n  __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */\n  __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */\n  __IO uint32_t PRESC;  /*!< USART clock Prescaler register,           Address offset: 0x2C */\n} USART_TypeDef;\n\n/**\n  * @brief Single Wire Protocol Master Interface SPWMI\n  */\ntypedef struct\n{\n  __IO uint32_t CR;          /*!< SWPMI Configuration/Control register,     Address offset: 0x00 */\n  __IO uint32_t BRR;         /*!< SWPMI bitrate register,                   Address offset: 0x04 */\n    uint32_t  RESERVED1;     /*!< Reserved, 0x08                                                 */\n  __IO uint32_t ISR;         /*!< SWPMI Interrupt and Status register,      Address offset: 0x0C */\n  __IO uint32_t ICR;         /*!< SWPMI Interrupt Flag Clear register,      Address offset: 0x10 */\n  __IO uint32_t IER;         /*!< SWPMI Interrupt Enable register,          Address offset: 0x14 */\n  __IO uint32_t RFL;         /*!< SWPMI Receive Frame Length register,      Address offset: 0x18 */\n  __IO uint32_t TDR;         /*!< SWPMI Transmit data register,             Address offset: 0x1C */\n  __IO uint32_t RDR;         /*!< SWPMI Receive data register,              Address offset: 0x20 */\n  __IO uint32_t OR;          /*!< SWPMI Option register,                    Address offset: 0x24 */\n} SWPMI_TypeDef;\n\n/**\n  * @brief Window WATCHDOG\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */\n  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */\n  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */\n} WWDG_TypeDef;\n\n\n/**\n  * @brief RAM_ECC_Specific_Registers\n  */\ntypedef struct\n{\n  __IO uint32_t CR;           /*!< RAMECC monitor configuration register          */\n  __IO uint32_t SR;           /*!< RAMECC monitor status register                 */\n  __IO uint32_t FAR;          /*!< RAMECC monitor failing address register        */\n  __IO uint32_t FDRL;         /*!< RAMECC monitor failing data low register       */\n  __IO uint32_t FDRH;         /*!< RAMECC monitor failing data high register      */\n  __IO uint32_t FECR;         /*!< RAMECC monitor failing ECC error code register */\n} RAMECC_MonitorTypeDef;\n\ntypedef struct\n{\n  __IO uint32_t IER;          /*!< RAMECC interrupt enable register */\n} RAMECC_TypeDef;\n/**\n  * @}\n  */\n\n\n\n/**\n  * @brief High resolution Timer (HRTIM)\n  */\n/* HRTIM master registers definition */\ntypedef struct\n{\n  __IO uint32_t MCR;            /*!< HRTIM Master Timer control register,                     Address offset: 0x00 */\n  __IO uint32_t MISR;           /*!< HRTIM Master Timer interrupt status register,            Address offset: 0x04 */\n  __IO uint32_t MICR;           /*!< HRTIM Master Timer interrupt clear register,             Address offset: 0x08 */\n  __IO uint32_t MDIER;          /*!< HRTIM Master Timer DMA/interrupt enable register         Address offset: 0x0C */\n  __IO uint32_t MCNTR;          /*!< HRTIM Master Timer counter register,                     Address offset: 0x10 */\n  __IO uint32_t MPER;           /*!< HRTIM Master Timer period register,                      Address offset: 0x14 */\n  __IO uint32_t MREP;           /*!< HRTIM Master Timer repetition register,                  Address offset: 0x18 */\n  __IO uint32_t MCMP1R;         /*!< HRTIM Master Timer compare 1 register,                   Address offset: 0x1C */\n  uint32_t      RESERVED0;     /*!< Reserved,                                                                 0x20 */\n  __IO uint32_t MCMP2R;         /*!< HRTIM Master Timer compare 2 register,                   Address offset: 0x24 */\n  __IO uint32_t MCMP3R;         /*!< HRTIM Master Timer compare 3 register,                   Address offset: 0x28 */\n  __IO uint32_t MCMP4R;         /*!< HRTIM Master Timer compare 4 register,                   Address offset: 0x2C */\n  uint32_t      RESERVED1[20];  /*!< Reserved,                                                          0x30..0x7C */\n}HRTIM_Master_TypeDef;\n\n/* HRTIM Timer A to E registers definition */\ntypedef struct\n{\n  __IO uint32_t TIMxCR;     /*!< HRTIM Timerx control register,                              Address offset: 0x00 */\n  __IO uint32_t TIMxISR;    /*!< HRTIM Timerx interrupt status register,                     Address offset: 0x04 */\n  __IO uint32_t TIMxICR;    /*!< HRTIM Timerx interrupt clear register,                      Address offset: 0x08 */\n  __IO uint32_t TIMxDIER;   /*!< HRTIM Timerx DMA/interrupt enable register,                 Address offset: 0x0C */\n  __IO uint32_t CNTxR;      /*!< HRTIM Timerx counter register,                              Address offset: 0x10 */\n  __IO uint32_t PERxR;      /*!< HRTIM Timerx period register,                               Address offset: 0x14 */\n  __IO uint32_t REPxR;      /*!< HRTIM Timerx repetition register,                           Address offset: 0x18 */\n  __IO uint32_t CMP1xR;     /*!< HRTIM Timerx compare 1 register,                            Address offset: 0x1C */\n  __IO uint32_t CMP1CxR;    /*!< HRTIM Timerx compare 1 compound register,                   Address offset: 0x20 */\n  __IO uint32_t CMP2xR;     /*!< HRTIM Timerx compare 2 register,                            Address offset: 0x24 */\n  __IO uint32_t CMP3xR;     /*!< HRTIM Timerx compare 3 register,                            Address offset: 0x28 */\n  __IO uint32_t CMP4xR;     /*!< HRTIM Timerx compare 4 register,                            Address offset: 0x2C */\n  __IO uint32_t CPT1xR;     /*!< HRTIM Timerx capture 1 register,                            Address offset: 0x30 */\n  __IO uint32_t CPT2xR;     /*!< HRTIM Timerx capture 2 register,                            Address offset: 0x34 */\n  __IO uint32_t DTxR;       /*!< HRTIM Timerx dead time register,                            Address offset: 0x38 */\n  __IO uint32_t SETx1R;     /*!< HRTIM Timerx output 1 set register,                         Address offset: 0x3C */\n  __IO uint32_t RSTx1R;     /*!< HRTIM Timerx output 1 reset register,                       Address offset: 0x40 */\n  __IO uint32_t SETx2R;     /*!< HRTIM Timerx output 2 set register,                         Address offset: 0x44 */\n  __IO uint32_t RSTx2R;     /*!< HRTIM Timerx output 2 reset register,                       Address offset: 0x48 */\n  __IO uint32_t EEFxR1;     /*!< HRTIM Timerx external event filtering 1 register,           Address offset: 0x4C */\n  __IO uint32_t EEFxR2;     /*!< HRTIM Timerx external event filtering 2 register,           Address offset: 0x50 */\n  __IO uint32_t RSTxR;      /*!< HRTIM Timerx Reset register,                                Address offset: 0x54 */\n  __IO uint32_t CHPxR;      /*!< HRTIM Timerx Chopper register,                              Address offset: 0x58 */\n  __IO uint32_t CPT1xCR;    /*!< HRTIM Timerx Capture 1 register,                            Address offset: 0x5C */\n  __IO uint32_t CPT2xCR;    /*!< HRTIM Timerx Capture 2 register,                            Address offset: 0x60 */\n  __IO uint32_t OUTxR;      /*!< HRTIM Timerx Output register,                               Address offset: 0x64 */\n  __IO uint32_t FLTxR;      /*!< HRTIM Timerx Fault register,                                Address offset: 0x68 */\n  uint32_t      RESERVED0[5];  /*!< Reserved,                                                          0x6C..0x7C */\n}HRTIM_Timerx_TypeDef;\n\n/* HRTIM common register definition */\ntypedef struct\n{\n  __IO uint32_t CR1;        /*!< HRTIM control register1,                                    Address offset: 0x00 */\n  __IO uint32_t CR2;        /*!< HRTIM control register2,                                    Address offset: 0x04 */\n  __IO uint32_t ISR;        /*!< HRTIM interrupt status register,                            Address offset: 0x08 */\n  __IO uint32_t ICR;        /*!< HRTIM interrupt clear register,                             Address offset: 0x0C */\n  __IO uint32_t IER;        /*!< HRTIM interrupt enable register,                            Address offset: 0x10 */\n  __IO uint32_t OENR;       /*!< HRTIM Output enable register,                               Address offset: 0x14 */\n  __IO uint32_t ODISR;      /*!< HRTIM Output disable register,                              Address offset: 0x18 */\n  __IO uint32_t ODSR;       /*!< HRTIM Output disable status register,                       Address offset: 0x1C */\n  __IO uint32_t BMCR;       /*!< HRTIM Burst mode control register,                          Address offset: 0x20 */\n  __IO uint32_t BMTRGR;     /*!< HRTIM Burst mode trigger register,                          Address offset: 0x24 */\n  __IO uint32_t BMCMPR;     /*!< HRTIM Burst mode compare register,                          Address offset: 0x28 */\n  __IO uint32_t BMPER;      /*!< HRTIM Burst mode period register,                           Address offset: 0x2C */\n  __IO uint32_t EECR1;      /*!< HRTIM Timer external event control register1,               Address offset: 0x30 */\n  __IO uint32_t EECR2;      /*!< HRTIM Timer external event control register2,               Address offset: 0x34 */\n  __IO uint32_t EECR3;      /*!< HRTIM Timer external event control register3,               Address offset: 0x38 */\n  __IO uint32_t ADC1R;      /*!< HRTIM ADC Trigger 1 register,                               Address offset: 0x3C */\n  __IO uint32_t ADC2R;      /*!< HRTIM ADC Trigger 2 register,                               Address offset: 0x40 */\n  __IO uint32_t ADC3R;      /*!< HRTIM ADC Trigger 3 register,                               Address offset: 0x44 */\n  __IO uint32_t ADC4R;      /*!< HRTIM ADC Trigger 4 register,                               Address offset: 0x48 */\n  __IO uint32_t RESERVED0;  /*!< Reserved,                                                   Address offset: 0x4C */\n  __IO uint32_t FLTINR1;    /*!< HRTIM Fault input register1,                                Address offset: 0x50 */\n  __IO uint32_t FLTINR2;    /*!< HRTIM Fault input register2,                                Address offset: 0x54 */\n  __IO uint32_t BDMUPR;     /*!< HRTIM Burst DMA Master Timer update register,               Address offset: 0x58 */\n  __IO uint32_t BDTAUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x5C */\n  __IO uint32_t BDTBUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x60 */\n  __IO uint32_t BDTCUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x64 */\n  __IO uint32_t BDTDUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x68 */\n  __IO uint32_t BDTEUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x6C */\n  __IO uint32_t BDMADR;     /*!< HRTIM Burst DMA Master Data register,                       Address offset: 0x70 */\n}HRTIM_Common_TypeDef;\n\n/* HRTIM  register definition */\ntypedef struct {\n  HRTIM_Master_TypeDef sMasterRegs;\n  HRTIM_Timerx_TypeDef sTimerxRegs[5];\n  uint32_t             RESERVED0[32];\n  HRTIM_Common_TypeDef sCommonRegs;\n}HRTIM_TypeDef;\n/**\n  * @brief RNG\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */\n  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */\n  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */\n} RNG_TypeDef;\n\n/**\n  * @brief MDIOS\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;\n  __IO uint32_t WRFR;\n  __IO uint32_t CWRFR;\n  __IO uint32_t RDFR;\n  __IO uint32_t CRDFR;\n  __IO uint32_t SR;\n  __IO uint32_t CLRFR;\n  uint32_t RESERVED[57];\n  __IO uint32_t DINR0;\n  __IO uint32_t DINR1;\n  __IO uint32_t DINR2;\n  __IO uint32_t DINR3;\n  __IO uint32_t DINR4;\n  __IO uint32_t DINR5;\n  __IO uint32_t DINR6;\n  __IO uint32_t DINR7;\n  __IO uint32_t DINR8;\n  __IO uint32_t DINR9;\n  __IO uint32_t DINR10;\n  __IO uint32_t DINR11;\n  __IO uint32_t DINR12;\n  __IO uint32_t DINR13;\n  __IO uint32_t DINR14;\n  __IO uint32_t DINR15;\n  __IO uint32_t DINR16;\n  __IO uint32_t DINR17;\n  __IO uint32_t DINR18;\n  __IO uint32_t DINR19;\n  __IO uint32_t DINR20;\n  __IO uint32_t DINR21;\n  __IO uint32_t DINR22;\n  __IO uint32_t DINR23;\n  __IO uint32_t DINR24;\n  __IO uint32_t DINR25;\n  __IO uint32_t DINR26;\n  __IO uint32_t DINR27;\n  __IO uint32_t DINR28;\n  __IO uint32_t DINR29;\n  __IO uint32_t DINR30;\n  __IO uint32_t DINR31;\n  __IO uint32_t DOUTR0;\n  __IO uint32_t DOUTR1;\n  __IO uint32_t DOUTR2;\n  __IO uint32_t DOUTR3;\n  __IO uint32_t DOUTR4;\n  __IO uint32_t DOUTR5;\n  __IO uint32_t DOUTR6;\n  __IO uint32_t DOUTR7;\n  __IO uint32_t DOUTR8;\n  __IO uint32_t DOUTR9;\n  __IO uint32_t DOUTR10;\n  __IO uint32_t DOUTR11;\n  __IO uint32_t DOUTR12;\n  __IO uint32_t DOUTR13;\n  __IO uint32_t DOUTR14;\n  __IO uint32_t DOUTR15;\n  __IO uint32_t DOUTR16;\n  __IO uint32_t DOUTR17;\n  __IO uint32_t DOUTR18;\n  __IO uint32_t DOUTR19;\n  __IO uint32_t DOUTR20;\n  __IO uint32_t DOUTR21;\n  __IO uint32_t DOUTR22;\n  __IO uint32_t DOUTR23;\n  __IO uint32_t DOUTR24;\n  __IO uint32_t DOUTR25;\n  __IO uint32_t DOUTR26;\n  __IO uint32_t DOUTR27;\n  __IO uint32_t DOUTR28;\n  __IO uint32_t DOUTR29;\n  __IO uint32_t DOUTR30;\n  __IO uint32_t DOUTR31;\n} MDIOS_TypeDef;\n\n\n/**\n  * @brief USB_OTG_Core_Registers\n  */\ntypedef struct\n{\n __IO uint32_t GOTGCTL;               /*!< USB_OTG Control and Status Register          000h */\n  __IO uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */\n  __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */\n  __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */\n  __IO uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */\n  __IO uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */\n  __IO uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */\n  __IO uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */\n  __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */\n  __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */\n  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */\n  __IO uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */\n  uint32_t Reserved30[2];             /*!< Reserved                                     030h */\n  __IO uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */\n  __IO uint32_t CID;                  /*!< User ID Register                             03Ch */\n  __IO uint32_t GSNPSID;              /* USB_OTG core ID                                040h*/\n  __IO uint32_t GHWCFG1;              /* User HW config1                                044h*/\n  __IO uint32_t GHWCFG2;              /* User HW config2                                048h*/\n  __IO uint32_t GHWCFG3;              /*!< User HW config3                              04Ch */\n  uint32_t  Reserved6;                /*!< Reserved                                     050h */\n  __IO uint32_t GLPMCFG;              /*!< LPM Register                                 054h */\n  __IO uint32_t GPWRDN;               /*!< Power Down Register                          058h */\n  __IO uint32_t GDFIFOCFG;            /*!< DFIFO Software Config Register               05Ch */\n   __IO uint32_t GADPCTL;             /*!< ADP Timer, Control and Status Register       60Ch */\n    uint32_t  Reserved43[39];         /*!< Reserved                                058h-0FFh */\n  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */\n  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO */\n} USB_OTG_GlobalTypeDef;\n\n\n/**\n  * @brief USB_OTG_device_Registers\n  */\ntypedef struct\n{\n  __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */\n  __IO uint32_t DCTL;            /*!< dev Control Register         804h */\n  __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */\n  uint32_t Reserved0C;           /*!< Reserved                     80Ch */\n  __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */\n  __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */\n  __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */\n  __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */\n  uint32_t  Reserved20;          /*!< Reserved                     820h */\n  uint32_t Reserved9;            /*!< Reserved                     824h */\n  __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */\n  __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */\n  __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */\n  __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */\n  __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */\n  __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */\n  uint32_t Reserved40;           /*!< dedicated EP mask            840h */\n  __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */\n  uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */\n  __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */\n} USB_OTG_DeviceTypeDef;\n\n\n/**\n  * @brief USB_OTG_IN_Endpoint-Specific_Register\n  */\ntypedef struct\n{\n  __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */\n  uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */\n  __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */\n  uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */\n  __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */\n  __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */\n  __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */\n  uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */\n} USB_OTG_INEndpointTypeDef;\n\n\n/**\n  * @brief USB_OTG_OUT_Endpoint-Specific_Registers\n  */\ntypedef struct\n{\n  __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */\n  uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */\n  __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */\n  uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */\n  __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */\n  __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */\n  uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */\n} USB_OTG_OUTEndpointTypeDef;\n\n\n/**\n  * @brief USB_OTG_Host_Mode_Register_Structures\n  */\ntypedef struct\n{\n  __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */\n  __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */\n  __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */\n  uint32_t Reserved40C;           /*!< Reserved                             40Ch */\n  __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */\n  __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */\n  __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */\n} USB_OTG_HostTypeDef;\n\n/**\n  * @brief USB_OTG_Host_Channel_Specific_Registers\n  */\ntypedef struct\n{\n  __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */\n  __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */\n  __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */\n  __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */\n  __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */\n  __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */\n  uint32_t Reserved[2];           /*!< Reserved                                      */\n} USB_OTG_HostChannelTypeDef;\n/**\n  * @}\n  */\n\n\n/**\n  * @brief Global Programmer View\n  */\n\ntypedef struct\n{\n  uint32_t      RESERVED0[2036];     /*!< Reserved,                                                                           Address offset: 0x00-0x1FCC     */\n  __IO uint32_t AXI_PERIPH_ID_4;     /*!< AXI interconnect - peripheral ID4 register,                                         Address offset: 0x1FD0          */\n  uint32_t      AXI_PERIPH_ID_5;     /*!< Reserved,                                                                           Address offset: 0x1FD4          */\n  uint32_t      AXI_PERIPH_ID_6;     /*!< Reserved,                                                                           Address offset: 0x1FD8          */\n  uint32_t      AXI_PERIPH_ID_7;     /*!< Reserved,                                                                           Address offset: 0x1FDC          */\n  __IO uint32_t AXI_PERIPH_ID_0;     /*!< AXI interconnect - peripheral ID0 register,                                         Address offset: 0x1FE0          */\n  __IO uint32_t AXI_PERIPH_ID_1;     /*!< AXI interconnect - peripheral ID1 register,                                         Address offset: 0x1FE4          */\n  __IO uint32_t AXI_PERIPH_ID_2;     /*!< AXI interconnect - peripheral ID2 register,                                         Address offset: 0x1FE8          */\n  __IO uint32_t AXI_PERIPH_ID_3;     /*!< AXI interconnect - peripheral ID3 register,                                         Address offset: 0x1FEC          */\n  __IO uint32_t AXI_COMP_ID_0;       /*!< AXI interconnect - component ID0 register,                                          Address offset: 0x1FF0          */\n  __IO uint32_t AXI_COMP_ID_1;       /*!< AXI interconnect - component ID1 register,                                          Address offset: 0x1FF4          */\n  __IO uint32_t AXI_COMP_ID_2;       /*!< AXI interconnect - component ID2 register,                                          Address offset: 0x1FF8          */\n  __IO uint32_t AXI_COMP_ID_3;       /*!< AXI interconnect - component ID3 register,                                          Address offset: 0x1FFC          */\n  uint32_t      RESERVED1[2];        /*!< Reserved,                                                                           Address offset: 0x2000-0x2004   */\n  __IO uint32_t AXI_TARG1_FN_MOD_ISS_BM;  /*!< AXI interconnect - TARG 1 bus matrix issuing functionality register,           Address offset: 0x2008          */\n  uint32_t      RESERVED2[6];        /*!< Reserved,                                                                           Address offset: 0x200C-0x2020   */\n  __IO uint32_t AXI_TARG1_FN_MOD2;   /*!< AXI interconnect - TARG 1 bus matrix functionality 2 register,                      Address offset: 0x2024          */\n  uint32_t      RESERVED3;           /*!< Reserved,                                                                           Address offset: 0x2028          */\n  __IO uint32_t AXI_TARG1_FN_MOD_LB; /*!< AXI interconnect - TARG 1 long burst functionality modification register,           Address offset: 0x202C          */\n  uint32_t      RESERVED4[54];       /*!< Reserved,                                                                           Address offset: 0x2030-0x2104   */\n  __IO uint32_t AXI_TARG1_FN_MOD;    /*!< AXI interconnect - TARG 1 issuing functionality modification register,              Address offset: 0x2108          */\n  uint32_t      RESERVED5[959];      /*!< Reserved,                                                                           Address offset: 0x210C-0x3004   */\n  __IO uint32_t AXI_TARG2_FN_MOD_ISS_BM;  /*!< AXI interconnect - TARG 2 bus matrix issuing functionality register,           Address offset: 0x3008          */\n  uint32_t      RESERVED6[6];        /*!< Reserved,                                                                           Address offset: 0x300C-0x3020   */\n  __IO uint32_t AXI_TARG2_FN_MOD2;   /*!< AXI interconnect - TARG 2 bus matrix functionality 2 register,                      Address offset: 0x3024          */\n  uint32_t      RESERVED7;           /*!< Reserved,                                                                           Address offset: 0x3028          */\n  __IO uint32_t AXI_TARG2_FN_MOD_LB; /*!< AXI interconnect - TARG 2 long burst functionality modification register,           Address offset: 0x302C          */\n  uint32_t      RESERVED8[54];       /*!< Reserved,                                                                           Address offset: 0x3030-0x3104   */\n  __IO uint32_t AXI_TARG2_FN_MOD;    /*!< AXI interconnect - TARG 2 issuing functionality modification register,              Address offset: 0x3108          */\n  uint32_t      RESERVED9[959];      /*!< Reserved,                                                                           Address offset: 0x310C-0x4004   */\n  __IO uint32_t AXI_TARG3_FN_MOD_ISS_BM;   /*!< AXI interconnect - TARG 3 bus matrix issuing functionality register,          Address offset: 0x4008          */\n  uint32_t      RESERVED10[1023];    /*!< Reserved,                                                                           Address offset: 0x400C-0x5004   */\n  __IO uint32_t AXI_TARG4_FN_MOD_ISS_BM;  /*!< AXI interconnect - TARG 4 bus matrix issuing functionality register,           Address offset: 0x5008          */\n  uint32_t      RESERVED11[1023];    /*!< Reserved,                                                                           Address offset: 0x500C-0x6004   */\n  __IO uint32_t AXI_TARG5_FN_MOD_ISS_BM;  /*!< AXI interconnect - TARG 5 bus matrix issuing functionality register,           Address offset: 0x6008          */\n  uint32_t      RESERVED12[1023];    /*!< Reserved,                                                                           Address offset: 0x600C-0x7004   */\n  __IO uint32_t AXI_TARG6_FN_MOD_ISS_BM;  /*!< AXI interconnect - TARG 6 bus matrix issuing functionality register,           Address offset: 0x7008          */\n  uint32_t      RESERVED13[1023];    /*!< Reserved,                                                                           Address offset: 0x700C-0x8004   */\n  __IO uint32_t AXI_TARG7_FN_MOD_ISS_BM;  /*!< AXI interconnect - TARG 7 bus matrix issuing functionality register,           Address offset: 0x8008          */\n  uint32_t      RESERVED14[6];       /*!< Reserved,                                                                           Address offset: 0x800C-0x8020   */\n  __IO uint32_t AXI_TARG7_FN_MOD2;   /*!< AXI interconnect - TARG 7 bus matrix functionality 2 register,                      Address offset: 0x8024          */\n  uint32_t      RESERVED15;          /*!< Reserved,                                                                           Address offset: 0x8028          */\n  __IO uint32_t AXI_TARG7_FN_MOD_LB; /*!< AXI interconnect - TARG 7 long burst functionality modification register,           Address offset: 0x802C          */\n  uint32_t      RESERVED16[54];      /*!< Reserved,                                                                           Address offset: 0x8030-0x8104   */\n  __IO uint32_t AXI_TARG7_FN_MOD;    /*!< AXI interconnect - TARG 7 issuing functionality modification register,              Address offset: 0x8108          */\n  uint32_t      RESERVED17[59334];    /*!< Reserved,                                                                          Address offset: 0x810C-0x42020  */\n  __IO uint32_t AXI_INI1_FN_MOD2;    /*!< AXI interconnect - INI 1 functionality modification 2 register,                     Address offset: 0x42024         */\n  __IO uint32_t AXI_INI1_FN_MOD_AHB; /*!< AXI interconnect - INI 1 AHB functionality modification register,                   Address offset: 0x42028         */\n  uint32_t      RESERVED18[53];      /*!< Reserved,                                                                           Address offset: 0x4202C-0x420FC */\n  __IO uint32_t AXI_INI1_READ_QOS;   /*!< AXI interconnect - INI 1 read QoS register,                                         Address offset: 0x42100         */\n  __IO uint32_t AXI_INI1_WRITE_QOS;  /*!< AXI interconnect - INI 1 write QoS register,                                        Address offset: 0x42104         */\n  __IO uint32_t AXI_INI1_FN_MOD;     /*!< AXI interconnect - INI 1 issuing functionality modification register,               Address offset: 0x42108         */\n  uint32_t      RESERVED19[1021];    /*!< Reserved,                                                                           Address offset: 0x4210C-0x430FC */\n  __IO uint32_t AXI_INI2_READ_QOS;   /*!< AXI interconnect - INI 2 read QoS register,                                         Address offset: 0x43100         */\n  __IO uint32_t AXI_INI2_WRITE_QOS;  /*!< AXI interconnect - INI 2 write QoS register,                                        Address offset: 0x43104         */\n  __IO uint32_t AXI_INI2_FN_MOD;     /*!< AXI interconnect - INI 2 issuing functionality modification register,               Address offset: 0x43108         */\n  uint32_t      RESERVED20[966];     /*!< Reserved,                                                                           Address offset: 0x4310C-0x44020 */\n  __IO uint32_t AXI_INI3_FN_MOD2;    /*!< AXI interconnect - INI 3 functionality modification 2 register,                     Address offset: 0x44024         */\n  __IO uint32_t AXI_INI3_FN_MOD_AHB; /*!< AXI interconnect - INI 3 AHB functionality modification register,                   Address offset: 0x44028         */\n  uint32_t      RESERVED21[53];      /*!< Reserved,                                                                           Address offset: 0x4402C-0x440FC */\n  __IO uint32_t AXI_INI3_READ_QOS;   /*!< AXI interconnect - INI 3 read QoS register,                                         Address offset: 0x44100         */\n  __IO uint32_t AXI_INI3_WRITE_QOS;  /*!< AXI interconnect - INI 3 write QoS register,                                        Address offset: 0x44104         */\n  __IO uint32_t AXI_INI3_FN_MOD;     /*!< AXI interconnect - INI 3 issuing functionality modification register,               Address offset: 0x44108         */\n  uint32_t      RESERVED22[1021];    /*!< Reserved,                                                                           Address offset: 0x4410C-0x450FC */\n  __IO uint32_t AXI_INI4_READ_QOS;   /*!< AXI interconnect - INI 4 read QoS register,                                         Address offset: 0x45100         */\n  __IO uint32_t AXI_INI4_WRITE_QOS;  /*!< AXI interconnect - INI 4 write QoS register,                                        Address offset: 0x45104         */\n  __IO uint32_t AXI_INI4_FN_MOD;     /*!< AXI interconnect - INI 4 issuing functionality modification register,               Address offset: 0x45108         */\n  uint32_t      RESERVED23[1021];    /*!< Reserved,                                                                           Address offset: 0x4510C-0x460FC */\n  __IO uint32_t AXI_INI5_READ_QOS;   /*!< AXI interconnect - INI 5 read QoS register,                                         Address offset: 0x46100         */\n  __IO uint32_t AXI_INI5_WRITE_QOS;  /*!< AXI interconnect - INI 5 write QoS register,                                        Address offset: 0x46104         */\n  __IO uint32_t AXI_INI5_FN_MOD;     /*!< AXI interconnect - INI 5 issuing functionality modification register,               Address offset: 0x46108         */\n  uint32_t      RESERVED24[1021];    /*!< Reserved,                                                                           Address offset: 0x4610C-0x470FC */\n  __IO uint32_t AXI_INI6_READ_QOS;   /*!< AXI interconnect - INI 6 read QoS register,                                         Address offset: 0x47100         */\n  __IO uint32_t AXI_INI6_WRITE_QOS;  /*!< AXI interconnect - INI 6 write QoS register,                                        Address offset: 0x47104         */\n  __IO uint32_t AXI_INI6_FN_MOD;     /*!< AXI interconnect - INI 6 issuing functionality modification register,               Address offset: 0x47108         */\n\n} GPV_TypeDef;\n\n/** @addtogroup Peripheral_memory_map\n  * @{\n  */\n#define D1_ITCMRAM_BASE           (0x00000000UL) /*!< Base address of : 64KB RAM reserved for CPU execution/instruction accessible over ITCM  */\n#define D1_ITCMICP_BASE           (0x00100000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over ITCM         */\n#define D1_DTCMRAM_BASE           (0x20000000UL) /*!< Base address of : 128KB system data RAM accessible over DTCM                            */\n#define D1_AXIFLASH_BASE          (0x08000000UL) /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI                */\n#define D1_AXIICP_BASE            (0x1FF00000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over AXI          */\n#define D1_AXISRAM_BASE           (0x24000000UL) /*!< Base address of : (up to 512KB) system data RAM accessible over over AXI                */\n\n#define D2_AXISRAM_BASE           (0x10000000UL) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI                */\n#define D2_AHBSRAM_BASE           (0x30000000UL) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI->AHB Bridge    */\n\n#define D3_BKPSRAM_BASE           (0x38800000UL) /*!< Base address of : Backup SRAM(4 KB) over AXI->AHB Bridge                                */\n#define D3_SRAM_BASE              (0x38000000UL) /*!< Base address of : Backup SRAM(64 KB) over AXI->AHB Bridge                               */\n\n#define PERIPH_BASE               (0x40000000UL) /*!< Base address of : AHB/APB Peripherals                                                   */\n#define QSPI_BASE                 (0x90000000UL) /*!< Base address of : QSPI memories  accessible over AXI                                    */\n\n#define FLASH_BANK1_BASE          (0x08000000UL) /*!< Base address of : (up to 1 MB) Flash Bank1 accessible over AXI                          */\n#define FLASH_BANK2_BASE          (0x08100000UL) /*!< Base address of : (up to 1 MB) Flash Bank2 accessible over AXI                          */\n#define FLASH_END                 (0x081FFFFFUL) /*!< FLASH end address                                                                       */\n\n/* Legacy define */\n#define FLASH_BASE                FLASH_BANK1_BASE\n\n/*!< Device electronic signature memory map */\n#define UID_BASE                  (0x1FF1E800UL)            /*!< Unique device ID register base address */\n#define FLASHSIZE_BASE            (0x1FF1E880UL)            /*!< FLASH Size register base address */\n\n\n/*!< Peripheral memory map */\n#define D2_APB1PERIPH_BASE        PERIPH_BASE\n#define D2_APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)\n#define D2_AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)\n#define D2_AHB2PERIPH_BASE       (PERIPH_BASE + 0x08020000UL)\n\n#define D1_APB1PERIPH_BASE       (PERIPH_BASE + 0x10000000UL)\n#define D1_AHB1PERIPH_BASE       (PERIPH_BASE + 0x12000000UL)\n\n#define D3_APB1PERIPH_BASE       (PERIPH_BASE + 0x18000000UL)\n#define D3_AHB1PERIPH_BASE       (PERIPH_BASE + 0x18020000UL)\n\n/*!< Legacy Peripheral memory map */\n#define APB1PERIPH_BASE        PERIPH_BASE\n#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)\n#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)\n#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000UL)\n\n\n/*!< D1_AHB1PERIPH peripherals */\n\n#define MDMA_BASE             (D1_AHB1PERIPH_BASE + 0x0000UL)\n#define DMA2D_BASE            (D1_AHB1PERIPH_BASE + 0x1000UL)\n#define JPGDEC_BASE           (D1_AHB1PERIPH_BASE + 0x3000UL)\n#define FLASH_R_BASE          (D1_AHB1PERIPH_BASE + 0x2000UL)\n#define FMC_R_BASE            (D1_AHB1PERIPH_BASE + 0x4000UL)\n#define QSPI_R_BASE           (D1_AHB1PERIPH_BASE + 0x5000UL)\n#define DLYB_QSPI_BASE        (D1_AHB1PERIPH_BASE + 0x6000UL)\n#define SDMMC1_BASE           (D1_AHB1PERIPH_BASE + 0x7000UL)\n#define DLYB_SDMMC1_BASE      (D1_AHB1PERIPH_BASE + 0x8000UL)\n#define RAMECC1_BASE          (D1_AHB1PERIPH_BASE + 0x9000UL)\n\n/*!< D2_AHB1PERIPH peripherals */\n\n#define DMA1_BASE               (D2_AHB1PERIPH_BASE + 0x0000UL)\n#define DMA2_BASE               (D2_AHB1PERIPH_BASE + 0x0400UL)\n#define DMAMUX1_BASE            (D2_AHB1PERIPH_BASE + 0x0800UL)\n#define ADC1_BASE               (D2_AHB1PERIPH_BASE + 0x2000UL)\n#define ADC2_BASE               (D2_AHB1PERIPH_BASE + 0x2100UL)\n#define ADC12_COMMON_BASE       (D2_AHB1PERIPH_BASE + 0x2300UL)\n#define ETH_BASE                (D2_AHB1PERIPH_BASE + 0x8000UL)\n#define ETH_MAC_BASE            (ETH_BASE)\n\n/*!< USB registers base address */\n#define USB1_OTG_HS_PERIPH_BASE              (0x40040000UL)\n#define USB2_OTG_FS_PERIPH_BASE              (0x40080000UL)\n#define USB_OTG_GLOBAL_BASE                  (0x000UL)\n#define USB_OTG_DEVICE_BASE                  (0x800UL)\n#define USB_OTG_IN_ENDPOINT_BASE             (0x900UL)\n#define USB_OTG_OUT_ENDPOINT_BASE            (0xB00UL)\n#define USB_OTG_EP_REG_SIZE                  (0x20UL)\n#define USB_OTG_HOST_BASE                    (0x400UL)\n#define USB_OTG_HOST_PORT_BASE               (0x440UL)\n#define USB_OTG_HOST_CHANNEL_BASE            (0x500UL)\n#define USB_OTG_HOST_CHANNEL_SIZE            (0x20UL)\n#define USB_OTG_PCGCCTL_BASE                 (0xE00UL)\n#define USB_OTG_FIFO_BASE                    (0x1000UL)\n#define USB_OTG_FIFO_SIZE                    (0x1000UL)\n\n/*!< D2_AHB2PERIPH peripherals */\n\n#define DCMI_BASE              (D2_AHB2PERIPH_BASE + 0x0000UL)\n#define RNG_BASE               (D2_AHB2PERIPH_BASE + 0x1800UL)\n#define SDMMC2_BASE            (D2_AHB2PERIPH_BASE + 0x2400UL)\n#define DLYB_SDMMC2_BASE       (D2_AHB2PERIPH_BASE + 0x2800UL)\n#define RAMECC2_BASE           (D2_AHB2PERIPH_BASE + 0x3000UL)\n\n/*!< D3_AHB1PERIPH peripherals */\n#define GPIOA_BASE            (D3_AHB1PERIPH_BASE + 0x0000UL)\n#define GPIOB_BASE            (D3_AHB1PERIPH_BASE + 0x0400UL)\n#define GPIOC_BASE            (D3_AHB1PERIPH_BASE + 0x0800UL)\n#define GPIOD_BASE            (D3_AHB1PERIPH_BASE + 0x0C00UL)\n#define GPIOE_BASE            (D3_AHB1PERIPH_BASE + 0x1000UL)\n#define GPIOF_BASE            (D3_AHB1PERIPH_BASE + 0x1400UL)\n#define GPIOG_BASE            (D3_AHB1PERIPH_BASE + 0x1800UL)\n#define GPIOH_BASE            (D3_AHB1PERIPH_BASE + 0x1C00UL)\n#define GPIOI_BASE            (D3_AHB1PERIPH_BASE + 0x2000UL)\n#define GPIOJ_BASE            (D3_AHB1PERIPH_BASE + 0x2400UL)\n#define GPIOK_BASE            (D3_AHB1PERIPH_BASE + 0x2800UL)\n#define RCC_BASE              (D3_AHB1PERIPH_BASE + 0x4400UL)\n#define PWR_BASE              (D3_AHB1PERIPH_BASE + 0x4800UL)\n#define CRC_BASE              (D3_AHB1PERIPH_BASE + 0x4C00UL)\n#define BDMA_BASE             (D3_AHB1PERIPH_BASE + 0x5400UL)\n#define DMAMUX2_BASE          (D3_AHB1PERIPH_BASE + 0x5800UL)\n#define ADC3_BASE             (D3_AHB1PERIPH_BASE + 0x6000UL)\n#define ADC3_COMMON_BASE      (D3_AHB1PERIPH_BASE + 0x6300UL)\n#define HSEM_BASE             (D3_AHB1PERIPH_BASE + 0x6400UL)\n#define RAMECC3_BASE          (D3_AHB1PERIPH_BASE + 0x7000UL)\n\n/*!< D1_APB1PERIPH peripherals */\n#define LTDC_BASE             (D1_APB1PERIPH_BASE + 0x1000UL)\n#define LTDC_Layer1_BASE      (LTDC_BASE + 0x84UL)\n#define LTDC_Layer2_BASE      (LTDC_BASE + 0x104UL)\n#define WWDG1_BASE            (D1_APB1PERIPH_BASE + 0x3000UL)\n\n/*!< D2_APB1PERIPH peripherals */\n#define TIM2_BASE             (D2_APB1PERIPH_BASE + 0x0000UL)\n#define TIM3_BASE             (D2_APB1PERIPH_BASE + 0x0400UL)\n#define TIM4_BASE             (D2_APB1PERIPH_BASE + 0x0800UL)\n#define TIM5_BASE             (D2_APB1PERIPH_BASE + 0x0C00UL)\n#define TIM6_BASE             (D2_APB1PERIPH_BASE + 0x1000UL)\n#define TIM7_BASE             (D2_APB1PERIPH_BASE + 0x1400UL)\n#define TIM12_BASE            (D2_APB1PERIPH_BASE + 0x1800UL)\n#define TIM13_BASE            (D2_APB1PERIPH_BASE + 0x1C00UL)\n#define TIM14_BASE            (D2_APB1PERIPH_BASE + 0x2000UL)\n#define LPTIM1_BASE           (D2_APB1PERIPH_BASE + 0x2400UL)\n\n\n#define SPI2_BASE             (D2_APB1PERIPH_BASE + 0x3800UL)\n#define SPI3_BASE             (D2_APB1PERIPH_BASE + 0x3C00UL)\n#define SPDIFRX_BASE          (D2_APB1PERIPH_BASE + 0x4000UL)\n#define USART2_BASE           (D2_APB1PERIPH_BASE + 0x4400UL)\n#define USART3_BASE           (D2_APB1PERIPH_BASE + 0x4800UL)\n#define UART4_BASE            (D2_APB1PERIPH_BASE + 0x4C00UL)\n#define UART5_BASE            (D2_APB1PERIPH_BASE + 0x5000UL)\n#define I2C1_BASE             (D2_APB1PERIPH_BASE + 0x5400UL)\n#define I2C2_BASE             (D2_APB1PERIPH_BASE + 0x5800UL)\n#define I2C3_BASE             (D2_APB1PERIPH_BASE + 0x5C00UL)\n#define CEC_BASE              (D2_APB1PERIPH_BASE + 0x6C00UL)\n#define DAC1_BASE             (D2_APB1PERIPH_BASE + 0x7400UL)\n#define UART7_BASE            (D2_APB1PERIPH_BASE + 0x7800UL)\n#define UART8_BASE            (D2_APB1PERIPH_BASE + 0x7C00UL)\n#define CRS_BASE              (D2_APB1PERIPH_BASE + 0x8400UL)\n#define SWPMI1_BASE           (D2_APB1PERIPH_BASE + 0x8800UL)\n#define OPAMP_BASE            (D2_APB1PERIPH_BASE + 0x9000UL)\n#define OPAMP1_BASE           (D2_APB1PERIPH_BASE + 0x9000UL)\n#define OPAMP2_BASE           (D2_APB1PERIPH_BASE + 0x9010UL)\n#define MDIOS_BASE            (D2_APB1PERIPH_BASE + 0x9400UL)\n#define FDCAN1_BASE           (D2_APB1PERIPH_BASE + 0xA000UL)\n#define FDCAN2_BASE           (D2_APB1PERIPH_BASE + 0xA400UL)\n#define FDCAN_CCU_BASE        (D2_APB1PERIPH_BASE + 0xA800UL)\n#define SRAMCAN_BASE          (D2_APB1PERIPH_BASE + 0xAC00UL)\n\n/*!< D2_APB2PERIPH peripherals */\n\n#define TIM1_BASE             (D2_APB2PERIPH_BASE + 0x0000UL)\n#define TIM8_BASE             (D2_APB2PERIPH_BASE + 0x0400UL)\n#define USART1_BASE           (D2_APB2PERIPH_BASE + 0x1000UL)\n#define USART6_BASE           (D2_APB2PERIPH_BASE + 0x1400UL)\n#define SPI1_BASE             (D2_APB2PERIPH_BASE + 0x3000UL)\n#define SPI4_BASE             (D2_APB2PERIPH_BASE + 0x3400UL)\n#define TIM15_BASE            (D2_APB2PERIPH_BASE + 0x4000UL)\n#define TIM16_BASE            (D2_APB2PERIPH_BASE + 0x4400UL)\n#define TIM17_BASE            (D2_APB2PERIPH_BASE + 0x4800UL)\n#define SPI5_BASE             (D2_APB2PERIPH_BASE + 0x5000UL)\n#define SAI1_BASE             (D2_APB2PERIPH_BASE + 0x5800UL)\n#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004UL)\n#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024UL)\n#define SAI2_BASE             (D2_APB2PERIPH_BASE + 0x5C00UL)\n#define SAI2_Block_A_BASE     (SAI2_BASE + 0x004UL)\n#define SAI2_Block_B_BASE     (SAI2_BASE + 0x024UL)\n#define SAI3_BASE             (D2_APB2PERIPH_BASE + 0x6000UL)\n#define SAI3_Block_A_BASE     (SAI3_BASE + 0x004UL)\n#define SAI3_Block_B_BASE     (SAI3_BASE + 0x024UL)\n#define DFSDM1_BASE           (D2_APB2PERIPH_BASE + 0x7000UL)\n#define DFSDM1_Channel0_BASE  (DFSDM1_BASE + 0x00UL)\n#define DFSDM1_Channel1_BASE  (DFSDM1_BASE + 0x20UL)\n#define DFSDM1_Channel2_BASE  (DFSDM1_BASE + 0x40UL)\n#define DFSDM1_Channel3_BASE  (DFSDM1_BASE + 0x60UL)\n#define DFSDM1_Channel4_BASE  (DFSDM1_BASE + 0x80UL)\n#define DFSDM1_Channel5_BASE  (DFSDM1_BASE + 0xA0UL)\n#define DFSDM1_Channel6_BASE  (DFSDM1_BASE + 0xC0UL)\n#define DFSDM1_Channel7_BASE  (DFSDM1_BASE + 0xE0UL)\n#define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x100UL)\n#define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x180UL)\n#define DFSDM1_Filter2_BASE   (DFSDM1_BASE + 0x200UL)\n#define DFSDM1_Filter3_BASE   (DFSDM1_BASE + 0x280UL)\n#define HRTIM1_BASE           (D2_APB2PERIPH_BASE + 0x7400UL)\n#define HRTIM1_TIMA_BASE      (HRTIM1_BASE + 0x00000080UL)\n#define HRTIM1_TIMB_BASE      (HRTIM1_BASE + 0x00000100UL)\n#define HRTIM1_TIMC_BASE      (HRTIM1_BASE + 0x00000180UL)\n#define HRTIM1_TIMD_BASE      (HRTIM1_BASE + 0x00000200UL)\n#define HRTIM1_TIME_BASE      (HRTIM1_BASE + 0x00000280UL)\n#define HRTIM1_COMMON_BASE    (HRTIM1_BASE + 0x00000380UL)\n\n\n/*!< D3_APB1PERIPH peripherals */\n#define EXTI_BASE             (D3_APB1PERIPH_BASE + 0x0000UL)\n#define EXTI_D1_BASE          (EXTI_BASE + 0x0080UL)\n#define EXTI_D2_BASE          (EXTI_BASE + 0x00C0UL)\n#define SYSCFG_BASE           (D3_APB1PERIPH_BASE + 0x0400UL)\n#define LPUART1_BASE          (D3_APB1PERIPH_BASE + 0x0C00UL)\n#define SPI6_BASE             (D3_APB1PERIPH_BASE + 0x1400UL)\n#define I2C4_BASE             (D3_APB1PERIPH_BASE + 0x1C00UL)\n#define LPTIM2_BASE           (D3_APB1PERIPH_BASE + 0x2400UL)\n#define LPTIM3_BASE           (D3_APB1PERIPH_BASE + 0x2800UL)\n#define LPTIM4_BASE           (D3_APB1PERIPH_BASE + 0x2C00UL)\n#define LPTIM5_BASE           (D3_APB1PERIPH_BASE + 0x3000UL)\n#define COMP12_BASE           (D3_APB1PERIPH_BASE + 0x3800UL)\n#define COMP1_BASE            (COMP12_BASE + 0x0CUL)\n#define COMP2_BASE            (COMP12_BASE + 0x10UL)\n#define VREFBUF_BASE          (D3_APB1PERIPH_BASE + 0x3C00UL)\n#define RTC_BASE              (D3_APB1PERIPH_BASE + 0x4000UL)\n#define IWDG1_BASE            (D3_APB1PERIPH_BASE + 0x4800UL)\n\n\n#define SAI4_BASE             (D3_APB1PERIPH_BASE + 0x5400UL)\n#define SAI4_Block_A_BASE     (SAI4_BASE + 0x004UL)\n#define SAI4_Block_B_BASE     (SAI4_BASE + 0x024UL)\n\n\n\n\n#define BDMA_Channel0_BASE    (BDMA_BASE + 0x0008UL)\n#define BDMA_Channel1_BASE    (BDMA_BASE + 0x001CUL)\n#define BDMA_Channel2_BASE    (BDMA_BASE + 0x0030UL)\n#define BDMA_Channel3_BASE    (BDMA_BASE + 0x0044UL)\n#define BDMA_Channel4_BASE    (BDMA_BASE + 0x0058UL)\n#define BDMA_Channel5_BASE    (BDMA_BASE + 0x006CUL)\n#define BDMA_Channel6_BASE    (BDMA_BASE + 0x0080UL)\n#define BDMA_Channel7_BASE    (BDMA_BASE + 0x0094UL)\n\n#define DMAMUX2_Channel0_BASE    (DMAMUX2_BASE)\n#define DMAMUX2_Channel1_BASE    (DMAMUX2_BASE + 0x0004UL)\n#define DMAMUX2_Channel2_BASE    (DMAMUX2_BASE + 0x0008UL)\n#define DMAMUX2_Channel3_BASE    (DMAMUX2_BASE + 0x000CUL)\n#define DMAMUX2_Channel4_BASE    (DMAMUX2_BASE + 0x0010UL)\n#define DMAMUX2_Channel5_BASE    (DMAMUX2_BASE + 0x0014UL)\n#define DMAMUX2_Channel6_BASE    (DMAMUX2_BASE + 0x0018UL)\n#define DMAMUX2_Channel7_BASE    (DMAMUX2_BASE + 0x001CUL)\n\n#define DMAMUX2_RequestGenerator0_BASE  (DMAMUX2_BASE + 0x0100UL)\n#define DMAMUX2_RequestGenerator1_BASE  (DMAMUX2_BASE + 0x0104UL)\n#define DMAMUX2_RequestGenerator2_BASE  (DMAMUX2_BASE + 0x0108UL)\n#define DMAMUX2_RequestGenerator3_BASE  (DMAMUX2_BASE + 0x010CUL)\n#define DMAMUX2_RequestGenerator4_BASE  (DMAMUX2_BASE + 0x0110UL)\n#define DMAMUX2_RequestGenerator5_BASE  (DMAMUX2_BASE + 0x0114UL)\n#define DMAMUX2_RequestGenerator6_BASE  (DMAMUX2_BASE + 0x0118UL)\n#define DMAMUX2_RequestGenerator7_BASE  (DMAMUX2_BASE + 0x011CUL)\n\n#define DMAMUX2_ChannelStatus_BASE      (DMAMUX2_BASE + 0x0080UL)\n#define DMAMUX2_RequestGenStatus_BASE   (DMAMUX2_BASE + 0x0140UL)\n\n#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010UL)\n#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028UL)\n#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040UL)\n#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058UL)\n#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070UL)\n#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088UL)\n#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0UL)\n#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8UL)\n\n#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010UL)\n#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028UL)\n#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040UL)\n#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058UL)\n#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070UL)\n#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088UL)\n#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0UL)\n#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8UL)\n\n#define DMAMUX1_Channel0_BASE    (DMAMUX1_BASE)\n#define DMAMUX1_Channel1_BASE    (DMAMUX1_BASE + 0x0004UL)\n#define DMAMUX1_Channel2_BASE    (DMAMUX1_BASE + 0x0008UL)\n#define DMAMUX1_Channel3_BASE    (DMAMUX1_BASE + 0x000CUL)\n#define DMAMUX1_Channel4_BASE    (DMAMUX1_BASE + 0x0010UL)\n#define DMAMUX1_Channel5_BASE    (DMAMUX1_BASE + 0x0014UL)\n#define DMAMUX1_Channel6_BASE    (DMAMUX1_BASE + 0x0018UL)\n#define DMAMUX1_Channel7_BASE    (DMAMUX1_BASE + 0x001CUL)\n#define DMAMUX1_Channel8_BASE    (DMAMUX1_BASE + 0x0020UL)\n#define DMAMUX1_Channel9_BASE    (DMAMUX1_BASE + 0x0024UL)\n#define DMAMUX1_Channel10_BASE   (DMAMUX1_BASE + 0x0028UL)\n#define DMAMUX1_Channel11_BASE   (DMAMUX1_BASE + 0x002CUL)\n#define DMAMUX1_Channel12_BASE   (DMAMUX1_BASE + 0x0030UL)\n#define DMAMUX1_Channel13_BASE   (DMAMUX1_BASE + 0x0034UL)\n#define DMAMUX1_Channel14_BASE   (DMAMUX1_BASE + 0x0038UL)\n#define DMAMUX1_Channel15_BASE   (DMAMUX1_BASE + 0x003CUL)\n\n#define DMAMUX1_RequestGenerator0_BASE  (DMAMUX1_BASE + 0x0100UL)\n#define DMAMUX1_RequestGenerator1_BASE  (DMAMUX1_BASE + 0x0104UL)\n#define DMAMUX1_RequestGenerator2_BASE  (DMAMUX1_BASE + 0x0108UL)\n#define DMAMUX1_RequestGenerator3_BASE  (DMAMUX1_BASE + 0x010CUL)\n#define DMAMUX1_RequestGenerator4_BASE  (DMAMUX1_BASE + 0x0110UL)\n#define DMAMUX1_RequestGenerator5_BASE  (DMAMUX1_BASE + 0x0114UL)\n#define DMAMUX1_RequestGenerator6_BASE  (DMAMUX1_BASE + 0x0118UL)\n#define DMAMUX1_RequestGenerator7_BASE  (DMAMUX1_BASE + 0x011CUL)\n\n#define DMAMUX1_ChannelStatus_BASE      (DMAMUX1_BASE + 0x0080UL)\n#define DMAMUX1_RequestGenStatus_BASE   (DMAMUX1_BASE + 0x0140UL)\n\n/*!< FMC Banks registers base  address */\n#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000UL)\n#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104UL)\n#define FMC_Bank2_R_BASE      (FMC_R_BASE + 0x0060UL)\n#define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080UL)\n#define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140UL)\n\n/* Debug MCU registers base address */\n#define DBGMCU_BASE           (0x5C001000UL)\n\n#define MDMA_Channel0_BASE    (MDMA_BASE + 0x00000040UL)\n#define MDMA_Channel1_BASE    (MDMA_BASE + 0x00000080UL)\n#define MDMA_Channel2_BASE    (MDMA_BASE + 0x000000C0UL)\n#define MDMA_Channel3_BASE    (MDMA_BASE + 0x00000100UL)\n#define MDMA_Channel4_BASE    (MDMA_BASE + 0x00000140UL)\n#define MDMA_Channel5_BASE    (MDMA_BASE + 0x00000180UL)\n#define MDMA_Channel6_BASE    (MDMA_BASE + 0x000001C0UL)\n#define MDMA_Channel7_BASE    (MDMA_BASE + 0x00000200UL)\n#define MDMA_Channel8_BASE    (MDMA_BASE + 0x00000240UL)\n#define MDMA_Channel9_BASE    (MDMA_BASE + 0x00000280UL)\n#define MDMA_Channel10_BASE   (MDMA_BASE + 0x000002C0UL)\n#define MDMA_Channel11_BASE   (MDMA_BASE + 0x00000300UL)\n#define MDMA_Channel12_BASE   (MDMA_BASE + 0x00000340UL)\n#define MDMA_Channel13_BASE   (MDMA_BASE + 0x00000380UL)\n#define MDMA_Channel14_BASE   (MDMA_BASE + 0x000003C0UL)\n#define MDMA_Channel15_BASE   (MDMA_BASE + 0x00000400UL)\n\n#define RAMECC1_Monitor1_BASE (RAMECC1_BASE + 0x20UL)\n#define RAMECC1_Monitor2_BASE (RAMECC1_BASE + 0x40UL)\n#define RAMECC1_Monitor3_BASE (RAMECC1_BASE + 0x60UL)\n#define RAMECC1_Monitor4_BASE (RAMECC1_BASE + 0x80UL)\n#define RAMECC1_Monitor5_BASE (RAMECC1_BASE + 0xA0UL)\n\n#define RAMECC2_Monitor1_BASE (RAMECC2_BASE + 0x20UL)\n#define RAMECC2_Monitor2_BASE (RAMECC2_BASE + 0x40UL)\n#define RAMECC2_Monitor3_BASE (RAMECC2_BASE + 0x60UL)\n#define RAMECC2_Monitor4_BASE (RAMECC2_BASE + 0x80UL)\n#define RAMECC2_Monitor5_BASE (RAMECC2_BASE + 0xA0UL)\n\n#define RAMECC3_Monitor1_BASE (RAMECC3_BASE + 0x20UL)\n#define RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL)\n\n\n\n#define GPV_BASE       (PERIPH_BASE + 0x11000000UL)   /*!<  GPV_BASE       (PERIPH_BASE + 0x11000000UL)                    */\n\n/**\n  * @}\n  */\n\n/** @addtogroup Peripheral_declaration\n  * @{\n  */\n#define TIM2                ((TIM_TypeDef *) TIM2_BASE)\n#define TIM3                ((TIM_TypeDef *) TIM3_BASE)\n#define TIM4                ((TIM_TypeDef *) TIM4_BASE)\n#define TIM5                ((TIM_TypeDef *) TIM5_BASE)\n#define TIM6                ((TIM_TypeDef *) TIM6_BASE)\n#define TIM7                ((TIM_TypeDef *) TIM7_BASE)\n#define TIM13               ((TIM_TypeDef *) TIM13_BASE)\n#define TIM14               ((TIM_TypeDef *) TIM14_BASE)\n#define VREFBUF             ((VREFBUF_TypeDef *) VREFBUF_BASE)\n#define RTC                 ((RTC_TypeDef *) RTC_BASE)\n#define WWDG1               ((WWDG_TypeDef *) WWDG1_BASE)\n\n\n#define IWDG1               ((IWDG_TypeDef *) IWDG1_BASE)\n#define SPI2                ((SPI_TypeDef *) SPI2_BASE)\n#define SPI3                ((SPI_TypeDef *) SPI3_BASE)\n#define SPI4                ((SPI_TypeDef *) SPI4_BASE)\n#define SPI5                ((SPI_TypeDef *) SPI5_BASE)\n#define SPI6                ((SPI_TypeDef *) SPI6_BASE)\n#define USART2              ((USART_TypeDef *) USART2_BASE)\n#define USART3              ((USART_TypeDef *) USART3_BASE)\n#define USART6              ((USART_TypeDef *) USART6_BASE)\n#define UART7               ((USART_TypeDef *) UART7_BASE)\n#define UART8               ((USART_TypeDef *) UART8_BASE)\n#define CRS                 ((CRS_TypeDef *) CRS_BASE)\n#define UART4               ((USART_TypeDef *) UART4_BASE)\n#define UART5               ((USART_TypeDef *) UART5_BASE)\n#define I2C1                ((I2C_TypeDef *) I2C1_BASE)\n#define I2C2                ((I2C_TypeDef *) I2C2_BASE)\n#define I2C3                ((I2C_TypeDef *) I2C3_BASE)\n#define I2C4                ((I2C_TypeDef *) I2C4_BASE)\n#define FDCAN1              ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)\n#define FDCAN2              ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)\n#define FDCAN_CCU           ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)\n#define CEC                 ((CEC_TypeDef *) CEC_BASE)\n#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)\n#define PWR                 ((PWR_TypeDef *) PWR_BASE)\n#define DAC1                ((DAC_TypeDef *) DAC1_BASE)\n#define LPUART1             ((USART_TypeDef *) LPUART1_BASE)\n#define SWPMI1              ((SWPMI_TypeDef *) SWPMI1_BASE)\n#define LPTIM2              ((LPTIM_TypeDef *) LPTIM2_BASE)\n#define LPTIM3              ((LPTIM_TypeDef *) LPTIM3_BASE)\n#define LPTIM4              ((LPTIM_TypeDef *) LPTIM4_BASE)\n#define LPTIM5              ((LPTIM_TypeDef *) LPTIM5_BASE)\n\n#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)\n#define COMP12              ((COMPOPT_TypeDef *) COMP12_BASE)\n#define COMP1               ((COMP_TypeDef *) COMP1_BASE)\n#define COMP2               ((COMP_TypeDef *) COMP2_BASE)\n#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP2_BASE)\n#define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)\n#define OPAMP1              ((OPAMP_TypeDef *) OPAMP1_BASE)\n#define OPAMP2              ((OPAMP_TypeDef *) OPAMP2_BASE)\n\n\n#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)\n#define EXTI_D1             ((EXTI_Core_TypeDef *) EXTI_D1_BASE)\n#define EXTI_D2             ((EXTI_Core_TypeDef *) EXTI_D2_BASE)\n#define TIM1                ((TIM_TypeDef *) TIM1_BASE)\n#define SPI1                ((SPI_TypeDef *) SPI1_BASE)\n#define TIM8                ((TIM_TypeDef *) TIM8_BASE)\n#define USART1              ((USART_TypeDef *) USART1_BASE)\n#define TIM12               ((TIM_TypeDef *) TIM12_BASE)\n#define TIM15               ((TIM_TypeDef *) TIM15_BASE)\n#define TIM16               ((TIM_TypeDef *) TIM16_BASE)\n#define TIM17               ((TIM_TypeDef *) TIM17_BASE)\n#define HRTIM1              ((HRTIM_TypeDef *) HRTIM1_BASE)\n#define HRTIM1_TIMA         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMA_BASE)\n#define HRTIM1_TIMB         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMB_BASE)\n#define HRTIM1_TIMC         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMC_BASE)\n#define HRTIM1_TIMD         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMD_BASE)\n#define HRTIM1_TIME         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIME_BASE)\n#define HRTIM1_COMMON       ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE)\n#define SAI1                ((SAI_TypeDef *) SAI1_BASE)\n#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)\n#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)\n#define SAI2                ((SAI_TypeDef *) SAI2_BASE)\n#define SAI2_Block_A        ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)\n#define SAI2_Block_B        ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)\n#define SAI3                ((SAI_TypeDef *) SAI3_BASE)\n#define SAI3_Block_A        ((SAI_Block_TypeDef *)SAI3_Block_A_BASE)\n#define SAI3_Block_B        ((SAI_Block_TypeDef *)SAI3_Block_B_BASE)\n#define SAI4                ((SAI_TypeDef *) SAI4_BASE)\n#define SAI4_Block_A        ((SAI_Block_TypeDef *)SAI4_Block_A_BASE)\n#define SAI4_Block_B        ((SAI_Block_TypeDef *)SAI4_Block_B_BASE)\n\n#define SPDIFRX             ((SPDIFRX_TypeDef *) SPDIFRX_BASE)\n#define DFSDM1_Channel0     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)\n#define DFSDM1_Channel1     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)\n#define DFSDM1_Channel2     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)\n#define DFSDM1_Channel3     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)\n#define DFSDM1_Channel4     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)\n#define DFSDM1_Channel5     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)\n#define DFSDM1_Channel6     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)\n#define DFSDM1_Channel7     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)\n#define DFSDM1_Filter0      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)\n#define DFSDM1_Filter1      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)\n#define DFSDM1_Filter2      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)\n#define DFSDM1_Filter3      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)\n#define DMA2D               ((DMA2D_TypeDef *) DMA2D_BASE)\n#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)\n#define RCC                 ((RCC_TypeDef *) RCC_BASE)\n#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)\n#define CRC                 ((CRC_TypeDef *) CRC_BASE)\n\n#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)\n#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)\n#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)\n#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)\n#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)\n#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)\n#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)\n#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)\n#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)\n#define GPIOJ               ((GPIO_TypeDef *) GPIOJ_BASE)\n#define GPIOK               ((GPIO_TypeDef *) GPIOK_BASE)\n\n#define ADC1                ((ADC_TypeDef *) ADC1_BASE)\n#define ADC2                ((ADC_TypeDef *) ADC2_BASE)\n#define ADC3                ((ADC_TypeDef *) ADC3_BASE)\n#define ADC3_COMMON         ((ADC_Common_TypeDef *) ADC3_COMMON_BASE)\n#define ADC12_COMMON        ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)\n\n#define RNG                 ((RNG_TypeDef *) RNG_BASE)\n#define SDMMC2              ((SDMMC_TypeDef *) SDMMC2_BASE)\n#define DLYB_SDMMC2         ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)\n\n#define BDMA                ((BDMA_TypeDef *) BDMA_BASE)\n#define BDMA_Channel0       ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE)\n#define BDMA_Channel1       ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE)\n#define BDMA_Channel2       ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE)\n#define BDMA_Channel3       ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE)\n#define BDMA_Channel4       ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE)\n#define BDMA_Channel5       ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE)\n#define BDMA_Channel6       ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE)\n#define BDMA_Channel7       ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE)\n\n#define RAMECC1              ((RAMECC_TypeDef *)RAMECC1_BASE)\n#define RAMECC1_Monitor1     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE)\n#define RAMECC1_Monitor2     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE)\n#define RAMECC1_Monitor3     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE)\n#define RAMECC1_Monitor4     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE)\n#define RAMECC1_Monitor5     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE)\n\n#define RAMECC2              ((RAMECC_TypeDef *)RAMECC2_BASE)\n#define RAMECC2_Monitor1     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE)\n#define RAMECC2_Monitor2     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE)\n#define RAMECC2_Monitor3     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE)\n#define RAMECC2_Monitor4     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor4_BASE)\n#define RAMECC2_Monitor5     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor5_BASE)\n\n#define RAMECC3              ((RAMECC_TypeDef *)RAMECC3_BASE)\n#define RAMECC3_Monitor1     ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE)\n#define RAMECC3_Monitor2     ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE)\n\n#define DMAMUX2                ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)\n#define DMAMUX2_Channel0       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)\n#define DMAMUX2_Channel1       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)\n#define DMAMUX2_Channel2       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)\n#define DMAMUX2_Channel3       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)\n#define DMAMUX2_Channel4       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)\n#define DMAMUX2_Channel5       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)\n#define DMAMUX2_Channel6       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)\n#define DMAMUX2_Channel7       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)\n\n\n#define DMAMUX2_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)\n#define DMAMUX2_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)\n#define DMAMUX2_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)\n#define DMAMUX2_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)\n#define DMAMUX2_RequestGenerator4  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)\n#define DMAMUX2_RequestGenerator5  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)\n#define DMAMUX2_RequestGenerator6  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)\n#define DMAMUX2_RequestGenerator7  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)\n\n#define DMAMUX2_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)\n#define DMAMUX2_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)\n\n#define DMA2                ((DMA_TypeDef *) DMA2_BASE)\n#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)\n#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)\n#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)\n#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)\n#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)\n#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)\n#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)\n#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)\n\n#define DMA1                ((DMA_TypeDef *) DMA1_BASE)\n#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)\n#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)\n#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)\n#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)\n#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)\n#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)\n#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)\n#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)\n\n\n#define DMAMUX1              ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)\n#define DMAMUX1_Channel0     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)\n#define DMAMUX1_Channel1     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)\n#define DMAMUX1_Channel2     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)\n#define DMAMUX1_Channel3     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)\n#define DMAMUX1_Channel4     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)\n#define DMAMUX1_Channel5     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)\n#define DMAMUX1_Channel6     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)\n#define DMAMUX1_Channel7     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)\n#define DMAMUX1_Channel8     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)\n#define DMAMUX1_Channel9     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)\n#define DMAMUX1_Channel10    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)\n#define DMAMUX1_Channel11    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)\n#define DMAMUX1_Channel12    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)\n#define DMAMUX1_Channel13    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)\n#define DMAMUX1_Channel14    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)\n#define DMAMUX1_Channel15    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)\n\n#define DMAMUX1_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)\n#define DMAMUX1_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)\n#define DMAMUX1_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)\n#define DMAMUX1_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)\n#define DMAMUX1_RequestGenerator4  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)\n#define DMAMUX1_RequestGenerator5  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)\n#define DMAMUX1_RequestGenerator6  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)\n#define DMAMUX1_RequestGenerator7  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)\n\n#define DMAMUX1_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *)    DMAMUX1_ChannelStatus_BASE)\n#define DMAMUX1_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)\n\n\n#define FMC_Bank1_R           ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)\n#define FMC_Bank1E_R          ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)\n#define FMC_Bank2_R           ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)\n#define FMC_Bank3_R           ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)\n#define FMC_Bank5_6_R         ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)\n\n\n#define QUADSPI               ((QUADSPI_TypeDef *) QSPI_R_BASE)\n#define DLYB_QUADSPI          ((DLYB_TypeDef *) DLYB_QSPI_BASE)\n#define SDMMC1                ((SDMMC_TypeDef *) SDMMC1_BASE)\n#define DLYB_SDMMC1           ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)\n\n#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)\n\n#define JPEG                ((JPEG_TypeDef *) JPGDEC_BASE)\n#define HSEM                ((HSEM_TypeDef *) HSEM_BASE)\n#define HSEM_COMMON         ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))\n\n#define LTDC                ((LTDC_TypeDef *)LTDC_BASE)\n#define LTDC_Layer1         ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)\n#define LTDC_Layer2         ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)\n\n#define MDIOS               ((MDIOS_TypeDef *) MDIOS_BASE)\n\n#define ETH                 ((ETH_TypeDef *)ETH_BASE)\n#define MDMA                ((MDMA_TypeDef *)MDMA_BASE)\n#define MDMA_Channel0       ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)\n#define MDMA_Channel1       ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)\n#define MDMA_Channel2       ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)\n#define MDMA_Channel3       ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)\n#define MDMA_Channel4       ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)\n#define MDMA_Channel5       ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)\n#define MDMA_Channel6       ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)\n#define MDMA_Channel7       ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)\n#define MDMA_Channel8       ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)\n#define MDMA_Channel9       ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)\n#define MDMA_Channel10      ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)\n#define MDMA_Channel11      ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)\n#define MDMA_Channel12      ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)\n#define MDMA_Channel13      ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)\n#define MDMA_Channel14      ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)\n#define MDMA_Channel15      ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)\n\n\n#define USB1_OTG_HS         ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)\n#define USB2_OTG_FS         ((USB_OTG_GlobalTypeDef *) USB2_OTG_FS_PERIPH_BASE)\n\n/* Legacy defines */\n#define USB_OTG_HS                   USB1_OTG_HS\n#define USB_OTG_HS_PERIPH_BASE       USB1_OTG_HS_PERIPH_BASE\n#define USB_OTG_FS                   USB2_OTG_FS\n#define USB_OTG_FS_PERIPH_BASE       USB2_OTG_FS_PERIPH_BASE\n\n#define GPV                ((GPV_TypeDef *) GPV_BASE)\n\n/**\n  * @}\n  */\n\n/** @addtogroup Exported_constants\n  * @{\n  */\n\n  /** @addtogroup Hardware_Constant_Definition\n    * @{\n    */\n#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */\n\n  /**\n    * @}\n    */\n\n  /** @addtogroup Peripheral_Registers_Bits_Definition\n  * @{\n  */\n\n/******************************************************************************/\n/*                         Peripheral Registers_Bits_Definition               */\n/******************************************************************************/\n\n/******************************************************************************/\n/*                                                                            */\n/*                        Analog to Digital Converter                         */\n/*                                                                            */\n/******************************************************************************/\n/*******************************  ADC VERSION  ********************************/\n#define ADC_VER_V5_X\n/********************  Bit definition for ADC_ISR register  ********************/\n#define ADC_ISR_ADRDY_Pos                 (0U)\n#define ADC_ISR_ADRDY_Msk                 (0x1UL << ADC_ISR_ADRDY_Pos)         /*!< 0x00000001 */\n#define ADC_ISR_ADRDY                     ADC_ISR_ADRDY_Msk                    /*!< ADC Ready (ADRDY) flag  */\n#define ADC_ISR_EOSMP_Pos                 (1U)\n#define ADC_ISR_EOSMP_Msk                 (0x1UL << ADC_ISR_EOSMP_Pos)         /*!< 0x00000002 */\n#define ADC_ISR_EOSMP                     ADC_ISR_EOSMP_Msk                    /*!< ADC End of Sampling flag */\n#define ADC_ISR_EOC_Pos                   (2U)\n#define ADC_ISR_EOC_Msk                   (0x1UL << ADC_ISR_EOC_Pos)           /*!< 0x00000004 */\n#define ADC_ISR_EOC                       ADC_ISR_EOC_Msk                      /*!< ADC End of Regular Conversion flag */\n#define ADC_ISR_EOS_Pos                   (3U)\n#define ADC_ISR_EOS_Msk                   (0x1UL << ADC_ISR_EOS_Pos)           /*!< 0x00000008 */\n#define ADC_ISR_EOS                       ADC_ISR_EOS_Msk                      /*!< ADC End of Regular sequence of Conversions flag */\n#define ADC_ISR_OVR_Pos                   (4U)\n#define ADC_ISR_OVR_Msk                   (0x1UL << ADC_ISR_OVR_Pos)           /*!< 0x00000010 */\n#define ADC_ISR_OVR                       ADC_ISR_OVR_Msk                      /*!< ADC overrun flag */\n#define ADC_ISR_JEOC_Pos                  (5U)\n#define ADC_ISR_JEOC_Msk                  (0x1UL << ADC_ISR_JEOC_Pos)          /*!< 0x00000020 */\n#define ADC_ISR_JEOC                      ADC_ISR_JEOC_Msk                     /*!< ADC End of Injected Conversion flag */\n#define ADC_ISR_JEOS_Pos                  (6U)\n#define ADC_ISR_JEOS_Msk                  (0x1UL << ADC_ISR_JEOS_Pos)          /*!< 0x00000040 */\n#define ADC_ISR_JEOS                      ADC_ISR_JEOS_Msk                     /*!< ADC End of Injected sequence of Conversions flag */\n#define ADC_ISR_AWD1_Pos                  (7U)\n#define ADC_ISR_AWD1_Msk                  (0x1UL << ADC_ISR_AWD1_Pos)          /*!< 0x00000080 */\n#define ADC_ISR_AWD1                      ADC_ISR_AWD1_Msk                     /*!< ADC Analog watchdog 1 flag */\n#define ADC_ISR_AWD2_Pos                  (8U)\n#define ADC_ISR_AWD2_Msk                  (0x1UL << ADC_ISR_AWD2_Pos)          /*!< 0x00000100 */\n#define ADC_ISR_AWD2                      ADC_ISR_AWD2_Msk                     /*!< ADC Analog watchdog 2 flag */\n#define ADC_ISR_AWD3_Pos                  (9U)\n#define ADC_ISR_AWD3_Msk                  (0x1UL << ADC_ISR_AWD3_Pos)          /*!< 0x00000200 */\n#define ADC_ISR_AWD3                      ADC_ISR_AWD3_Msk                     /*!< ADC Analog watchdog 3 flag */\n#define ADC_ISR_JQOVF_Pos                 (10U)\n#define ADC_ISR_JQOVF_Msk                 (0x1UL << ADC_ISR_JQOVF_Pos)         /*!< 0x00000400 */\n#define ADC_ISR_JQOVF                     ADC_ISR_JQOVF_Msk                    /*!< ADC Injected Context Queue Overflow flag */\n\n/********************  Bit definition for ADC_IER register  ********************/\n#define ADC_IER_ADRDYIE_Pos               (0U)\n#define ADC_IER_ADRDYIE_Msk               (0x1UL << ADC_IER_ADRDYIE_Pos)       /*!< 0x00000001 */\n#define ADC_IER_ADRDYIE                   ADC_IER_ADRDYIE_Msk                  /*!< ADC Ready (ADRDY) interrupt source */\n#define ADC_IER_EOSMPIE_Pos               (1U)\n#define ADC_IER_EOSMPIE_Msk               (0x1UL << ADC_IER_EOSMPIE_Pos)       /*!< 0x00000002 */\n#define ADC_IER_EOSMPIE                   ADC_IER_EOSMPIE_Msk                  /*!< ADC End of Sampling interrupt source */\n#define ADC_IER_EOCIE_Pos                 (2U)\n#define ADC_IER_EOCIE_Msk                 (0x1UL << ADC_IER_EOCIE_Pos)         /*!< 0x00000004 */\n#define ADC_IER_EOCIE                     ADC_IER_EOCIE_Msk                    /*!< ADC End of Regular Conversion interrupt source */\n#define ADC_IER_EOSIE_Pos                 (3U)\n#define ADC_IER_EOSIE_Msk                 (0x1UL << ADC_IER_EOSIE_Pos)         /*!< 0x00000008 */\n#define ADC_IER_EOSIE                     ADC_IER_EOSIE_Msk                    /*!< ADC End of Regular sequence of Conversions interrupt source */\n#define ADC_IER_OVRIE_Pos                 (4U)\n#define ADC_IER_OVRIE_Msk                 (0x1UL << ADC_IER_OVRIE_Pos)         /*!< 0x00000010 */\n#define ADC_IER_OVRIE                     ADC_IER_OVRIE_Msk                    /*!< ADC overrun interrupt source */\n#define ADC_IER_JEOCIE_Pos                (5U)\n#define ADC_IER_JEOCIE_Msk                (0x1UL << ADC_IER_JEOCIE_Pos)        /*!< 0x00000020 */\n#define ADC_IER_JEOCIE                    ADC_IER_JEOCIE_Msk                   /*!< ADC End of Injected Conversion interrupt source */\n#define ADC_IER_JEOSIE_Pos                (6U)\n#define ADC_IER_JEOSIE_Msk                (0x1UL << ADC_IER_JEOSIE_Pos)        /*!< 0x00000040 */\n#define ADC_IER_JEOSIE                    ADC_IER_JEOSIE_Msk                   /*!< ADC End of Injected sequence of Conversions interrupt source */\n#define ADC_IER_AWD1IE_Pos                (7U)\n#define ADC_IER_AWD1IE_Msk                (0x1UL << ADC_IER_AWD1IE_Pos)        /*!< 0x00000080 */\n#define ADC_IER_AWD1IE                    ADC_IER_AWD1IE_Msk                   /*!< ADC Analog watchdog 1 interrupt source */\n#define ADC_IER_AWD2IE_Pos                (8U)\n#define ADC_IER_AWD2IE_Msk                (0x1UL << ADC_IER_AWD2IE_Pos)        /*!< 0x00000100 */\n#define ADC_IER_AWD2IE                    ADC_IER_AWD2IE_Msk                   /*!< ADC Analog watchdog 2 interrupt source */\n#define ADC_IER_AWD3IE_Pos                (9U)\n#define ADC_IER_AWD3IE_Msk                (0x1UL << ADC_IER_AWD3IE_Pos)        /*!< 0x00000200 */\n#define ADC_IER_AWD3IE                    ADC_IER_AWD3IE_Msk                   /*!< ADC Analog watchdog 3 interrupt source */\n#define ADC_IER_JQOVFIE_Pos               (10U)\n#define ADC_IER_JQOVFIE_Msk               (0x1UL << ADC_IER_JQOVFIE_Pos)       /*!< 0x00000400 */\n#define ADC_IER_JQOVFIE                   ADC_IER_JQOVFIE_Msk                  /*!< ADC Injected Context Queue Overflow interrupt source */\n\n/********************  Bit definition for ADC_CR register  ********************/\n#define ADC_CR_ADEN_Pos                   (0U)\n#define ADC_CR_ADEN_Msk                   (0x1UL << ADC_CR_ADEN_Pos)           /*!< 0x00000001 */\n#define ADC_CR_ADEN                       ADC_CR_ADEN_Msk                      /*!< ADC Enable control */\n#define ADC_CR_ADDIS_Pos                  (1U)\n#define ADC_CR_ADDIS_Msk                  (0x1UL << ADC_CR_ADDIS_Pos)          /*!< 0x00000002 */\n#define ADC_CR_ADDIS                      ADC_CR_ADDIS_Msk                     /*!< ADC Disable command */\n#define ADC_CR_ADSTART_Pos                (2U)\n#define ADC_CR_ADSTART_Msk                (0x1UL << ADC_CR_ADSTART_Pos)        /*!< 0x00000004 */\n#define ADC_CR_ADSTART                    ADC_CR_ADSTART_Msk                   /*!< ADC Start of Regular conversion */\n#define ADC_CR_JADSTART_Pos               (3U)\n#define ADC_CR_JADSTART_Msk               (0x1UL << ADC_CR_JADSTART_Pos)       /*!< 0x00000008 */\n#define ADC_CR_JADSTART                   ADC_CR_JADSTART_Msk                  /*!< ADC Start of injected conversion */\n#define ADC_CR_ADSTP_Pos                  (4U)\n#define ADC_CR_ADSTP_Msk                  (0x1UL << ADC_CR_ADSTP_Pos)          /*!< 0x00000010 */\n#define ADC_CR_ADSTP                      ADC_CR_ADSTP_Msk                     /*!< ADC Stop of Regular conversion */\n#define ADC_CR_JADSTP_Pos                 (5U)\n#define ADC_CR_JADSTP_Msk                 (0x1UL << ADC_CR_JADSTP_Pos)         /*!< 0x00000020 */\n#define ADC_CR_JADSTP                     ADC_CR_JADSTP_Msk                    /*!< ADC Stop of injected conversion */\n#define ADC_CR_BOOST_Pos                  (8U)\n#define ADC_CR_BOOST_Msk                  (0x3UL << ADC_CR_BOOST_Pos)          /*!< 0x00000300 */\n#define ADC_CR_BOOST                      ADC_CR_BOOST_Msk                     /*!< ADC Boost Mode configuration */\n#define ADC_CR_BOOST_0                    (0x1UL << ADC_CR_BOOST_Pos)           /*!< 0x00000100 */\n#define ADC_CR_BOOST_1                    (0x2UL << ADC_CR_BOOST_Pos)           /*!< 0x00000200 */\n#define ADC_CR_ADCALLIN_Pos               (16U)\n#define ADC_CR_ADCALLIN_Msk               (0x1UL << ADC_CR_ADCALLIN_Pos)       /*!< 0x00010000 */\n#define ADC_CR_ADCALLIN                   ADC_CR_ADCALLIN_Msk                  /*!< ADC Linearity calibration */\n#define ADC_CR_LINCALRDYW1_Pos            (22U)\n#define ADC_CR_LINCALRDYW1_Msk            (0x1UL << ADC_CR_LINCALRDYW1_Pos)    /*!< 0x00400000 */\n#define ADC_CR_LINCALRDYW1                ADC_CR_LINCALRDYW1_Msk               /*!< ADC Linearity calibration ready Word 1 */\n#define ADC_CR_LINCALRDYW2_Pos            (23U)\n#define ADC_CR_LINCALRDYW2_Msk            (0x1UL << ADC_CR_LINCALRDYW2_Pos)    /*!< 0x00800000 */\n#define ADC_CR_LINCALRDYW2                ADC_CR_LINCALRDYW2_Msk               /*!< ADC Linearity calibration ready Word 2 */\n#define ADC_CR_LINCALRDYW3_Pos            (24U)\n#define ADC_CR_LINCALRDYW3_Msk            (0x1UL << ADC_CR_LINCALRDYW3_Pos)    /*!< 0x01000000 */\n#define ADC_CR_LINCALRDYW3                ADC_CR_LINCALRDYW3_Msk               /*!< ADC Linearity calibration ready Word 3 */\n#define ADC_CR_LINCALRDYW4_Pos            (25U)\n#define ADC_CR_LINCALRDYW4_Msk            (0x1UL << ADC_CR_LINCALRDYW4_Pos)    /*!< 0x02000000 */\n#define ADC_CR_LINCALRDYW4                ADC_CR_LINCALRDYW4_Msk               /*!< ADC Linearity calibration ready Word 4 */\n#define ADC_CR_LINCALRDYW5_Pos            (26U)\n#define ADC_CR_LINCALRDYW5_Msk            (0x1UL << ADC_CR_LINCALRDYW5_Pos)    /*!< 0x04000000 */\n#define ADC_CR_LINCALRDYW5                ADC_CR_LINCALRDYW5_Msk               /*!< ADC Linearity calibration ready Word 5 */\n#define ADC_CR_LINCALRDYW6_Pos            (27U)\n#define ADC_CR_LINCALRDYW6_Msk            (0x1UL << ADC_CR_LINCALRDYW6_Pos)    /*!< 0x08000000 */\n#define ADC_CR_LINCALRDYW6                ADC_CR_LINCALRDYW6_Msk               /*!< ADC Linearity calibration ready Word 6 */\n#define ADC_CR_ADVREGEN_Pos               (28U)\n#define ADC_CR_ADVREGEN_Msk               (0x1UL << ADC_CR_ADVREGEN_Pos)       /*!< 0x10000000 */\n#define ADC_CR_ADVREGEN                   ADC_CR_ADVREGEN_Msk                  /*!< ADC Voltage regulator Enable */\n#define ADC_CR_DEEPPWD_Pos                (29U)\n#define ADC_CR_DEEPPWD_Msk                (0x1UL << ADC_CR_DEEPPWD_Pos)        /*!< 0x20000000 */\n#define ADC_CR_DEEPPWD                    ADC_CR_DEEPPWD_Msk                   /*!< ADC Deep power down Enable */\n#define ADC_CR_ADCALDIF_Pos               (30U)\n#define ADC_CR_ADCALDIF_Msk               (0x1UL << ADC_CR_ADCALDIF_Pos)       /*!< 0x40000000 */\n#define ADC_CR_ADCALDIF                   ADC_CR_ADCALDIF_Msk                  /*!< ADC Differential Mode for calibration */\n#define ADC_CR_ADCAL_Pos                  (31U)\n#define ADC_CR_ADCAL_Msk                  (0x1UL << ADC_CR_ADCAL_Pos)          /*!< 0x80000000 */\n#define ADC_CR_ADCAL                      ADC_CR_ADCAL_Msk                     /*!< ADC Calibration */\n\n/********************  Bit definition for ADC_CFGR register  ********************/\n#define ADC_CFGR_DMNGT_Pos                (0U)\n#define ADC_CFGR_DMNGT_Msk                (0x3UL << ADC_CFGR_DMNGT_Pos)        /*!< 0x00000003 */\n#define ADC_CFGR_DMNGT                    ADC_CFGR_DMNGT_Msk                   /*!< ADC Data Management configuration */\n#define ADC_CFGR_DMNGT_0                  (0x1UL << ADC_CFGR_DMNGT_Pos)         /*!< 0x00000001 */\n#define ADC_CFGR_DMNGT_1                  (0x2UL << ADC_CFGR_DMNGT_Pos)         /*!< 0x00000002 */\n\n#define ADC_CFGR_RES_Pos                  (2U)\n#define ADC_CFGR_RES_Msk                  (0x7UL << ADC_CFGR_RES_Pos)          /*!< 0x0000001C */\n#define ADC_CFGR_RES                      ADC_CFGR_RES_Msk                     /*!< ADC Data resolution */\n#define ADC_CFGR_RES_0                    (0x1UL << ADC_CFGR_RES_Pos)           /*!< 0x00000004 */\n#define ADC_CFGR_RES_1                    (0x2UL << ADC_CFGR_RES_Pos)           /*!< 0x00000008 */\n#define ADC_CFGR_RES_2                    (0x4UL << ADC_CFGR_RES_Pos)           /*!< 0x00000010 */\n\n#define ADC_CFGR_EXTSEL_Pos               (5U)\n#define ADC_CFGR_EXTSEL_Msk               (0x1FUL << ADC_CFGR_EXTSEL_Pos)      /*!< 0x000003E0 */\n#define ADC_CFGR_EXTSEL                   ADC_CFGR_EXTSEL_Msk                  /*!< ADC External trigger selection for regular group */\n#define ADC_CFGR_EXTSEL_0                 (0x01UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000020 */\n#define ADC_CFGR_EXTSEL_1                 (0x02UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000040 */\n#define ADC_CFGR_EXTSEL_2                 (0x04UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000080 */\n#define ADC_CFGR_EXTSEL_3                 (0x08UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000100 */\n#define ADC_CFGR_EXTSEL_4                 (0x10UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000200 */\n\n#define ADC_CFGR_EXTEN_Pos                (10U)\n#define ADC_CFGR_EXTEN_Msk                (0x3UL << ADC_CFGR_EXTEN_Pos)        /*!< 0x00000C00 */\n#define ADC_CFGR_EXTEN                    ADC_CFGR_EXTEN_Msk                   /*!< ADC External trigger enable and polarity selection for regular channels */\n#define ADC_CFGR_EXTEN_0                  (0x1UL << ADC_CFGR_EXTEN_Pos)         /*!< 0x00000400 */\n#define ADC_CFGR_EXTEN_1                  (0x2UL << ADC_CFGR_EXTEN_Pos)         /*!< 0x00000800 */\n\n#define ADC_CFGR_OVRMOD_Pos               (12U)\n#define ADC_CFGR_OVRMOD_Msk               (0x1UL << ADC_CFGR_OVRMOD_Pos)       /*!< 0x00001000 */\n#define ADC_CFGR_OVRMOD                   ADC_CFGR_OVRMOD_Msk                  /*!< ADC overrun mode */\n#define ADC_CFGR_CONT_Pos                 (13U)\n#define ADC_CFGR_CONT_Msk                 (0x1UL << ADC_CFGR_CONT_Pos)         /*!< 0x00002000 */\n#define ADC_CFGR_CONT                     ADC_CFGR_CONT_Msk                    /*!< ADC Single/continuous conversion mode for regular conversion */\n#define ADC_CFGR_AUTDLY_Pos               (14U)\n#define ADC_CFGR_AUTDLY_Msk               (0x1UL << ADC_CFGR_AUTDLY_Pos)       /*!< 0x00004000 */\n#define ADC_CFGR_AUTDLY                   ADC_CFGR_AUTDLY_Msk                  /*!< ADC Delayed conversion mode */\n\n#define ADC_CFGR_DISCEN_Pos               (16U)\n#define ADC_CFGR_DISCEN_Msk               (0x1UL << ADC_CFGR_DISCEN_Pos)       /*!< 0x00010000 */\n#define ADC_CFGR_DISCEN                   ADC_CFGR_DISCEN_Msk                  /*!< ADC Discontinuous mode for regular channels */\n\n#define ADC_CFGR_DISCNUM_Pos              (17U)\n#define ADC_CFGR_DISCNUM_Msk              (0x7UL << ADC_CFGR_DISCNUM_Pos)      /*!< 0x000E0000 */\n#define ADC_CFGR_DISCNUM                  ADC_CFGR_DISCNUM_Msk                 /*!< ADC Discontinuous mode channel count */\n#define ADC_CFGR_DISCNUM_0                (0x1UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00020000 */\n#define ADC_CFGR_DISCNUM_1                (0x2UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00040000 */\n#define ADC_CFGR_DISCNUM_2                (0x4UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00080000 */\n\n#define ADC_CFGR_JDISCEN_Pos              (20U)\n#define ADC_CFGR_JDISCEN_Msk              (0x1UL << ADC_CFGR_JDISCEN_Pos)      /*!< 0x00100000 */\n#define ADC_CFGR_JDISCEN                  ADC_CFGR_JDISCEN_Msk                 /*!< ADC Discontinuous mode on injected channels */\n#define ADC_CFGR_JQM_Pos                  (21U)\n#define ADC_CFGR_JQM_Msk                  (0x1UL << ADC_CFGR_JQM_Pos)          /*!< 0x00200000 */\n#define ADC_CFGR_JQM                      ADC_CFGR_JQM_Msk                     /*!< ADC JSQR Queue mode */\n#define ADC_CFGR_AWD1SGL_Pos              (22U)\n#define ADC_CFGR_AWD1SGL_Msk              (0x1UL << ADC_CFGR_AWD1SGL_Pos)      /*!< 0x00400000 */\n#define ADC_CFGR_AWD1SGL                  ADC_CFGR_AWD1SGL_Msk                 /*!< Enable the watchdog 1 on a single channel or on all channels */\n#define ADC_CFGR_AWD1EN_Pos               (23U)\n#define ADC_CFGR_AWD1EN_Msk               (0x1UL << ADC_CFGR_AWD1EN_Pos)       /*!< 0x00800000 */\n#define ADC_CFGR_AWD1EN                   ADC_CFGR_AWD1EN_Msk                  /*!< ADC Analog watchdog 1 enable on regular Channels */\n#define ADC_CFGR_JAWD1EN_Pos              (24U)\n#define ADC_CFGR_JAWD1EN_Msk              (0x1UL << ADC_CFGR_JAWD1EN_Pos)      /*!< 0x01000000 */\n#define ADC_CFGR_JAWD1EN                  ADC_CFGR_JAWD1EN_Msk                 /*!< ADC Analog watchdog 1 enable on injected Channels */\n#define ADC_CFGR_JAUTO_Pos                (25U)\n#define ADC_CFGR_JAUTO_Msk                (0x1UL << ADC_CFGR_JAUTO_Pos)        /*!< 0x02000000 */\n#define ADC_CFGR_JAUTO                    ADC_CFGR_JAUTO_Msk                   /*!< ADC Automatic injected group conversion */\n\n#define ADC_CFGR_AWD1CH_Pos               (26U)\n#define ADC_CFGR_AWD1CH_Msk               (0x1FUL << ADC_CFGR_AWD1CH_Pos)      /*!< 0x7C000000 */\n#define ADC_CFGR_AWD1CH                   ADC_CFGR_AWD1CH_Msk                  /*!< ADC Analog watchdog 1 Channel selection */\n#define ADC_CFGR_AWD1CH_0                 (0x01UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x04000000 */\n#define ADC_CFGR_AWD1CH_1                 (0x02UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x08000000 */\n#define ADC_CFGR_AWD1CH_2                 (0x04UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x10000000 */\n#define ADC_CFGR_AWD1CH_3                 (0x08UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x20000000 */\n#define ADC_CFGR_AWD1CH_4                 (0x10UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x40000000 */\n\n#define ADC_CFGR_JQDIS_Pos                (31U)\n#define ADC_CFGR_JQDIS_Msk                (0x1UL << ADC_CFGR_JQDIS_Pos)        /*!< 0x80000000 */\n#define ADC_CFGR_JQDIS                    ADC_CFGR_JQDIS_Msk                   /*!< ADC Injected queue disable */\n\n/********************  Bit definition for ADC_CFGR2 register  ********************/\n#define ADC_CFGR2_ROVSE_Pos               (0U)\n#define ADC_CFGR2_ROVSE_Msk               (0x1UL << ADC_CFGR2_ROVSE_Pos)       /*!< 0x00000001 */\n#define ADC_CFGR2_ROVSE                   ADC_CFGR2_ROVSE_Msk                  /*!< ADC Regular group oversampler enable */\n#define ADC_CFGR2_JOVSE_Pos               (1U)\n#define ADC_CFGR2_JOVSE_Msk               (0x1UL << ADC_CFGR2_JOVSE_Pos)       /*!< 0x00000002 */\n#define ADC_CFGR2_JOVSE                   ADC_CFGR2_JOVSE_Msk                  /*!< ADC Injected group oversampler enable */\n\n#define ADC_CFGR2_OVSS_Pos                (5U)\n#define ADC_CFGR2_OVSS_Msk                (0xFUL << ADC_CFGR2_OVSS_Pos)        /*!< 0x000001E0 */\n#define ADC_CFGR2_OVSS                    ADC_CFGR2_OVSS_Msk                   /*!< ADC Regular Oversampling shift */\n#define ADC_CFGR2_OVSS_0                  (0x1UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000020 */\n#define ADC_CFGR2_OVSS_1                  (0x2UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000040 */\n#define ADC_CFGR2_OVSS_2                  (0x4UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000080 */\n#define ADC_CFGR2_OVSS_3                  (0x8UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000100 */\n\n#define ADC_CFGR2_TROVS_Pos               (9U)\n#define ADC_CFGR2_TROVS_Msk               (0x1UL << ADC_CFGR2_TROVS_Pos)       /*!< 0x00000200 */\n#define ADC_CFGR2_TROVS                   ADC_CFGR2_TROVS_Msk                  /*!< ADC Triggered regular Oversampling */\n#define ADC_CFGR2_ROVSM_Pos               (10U)\n#define ADC_CFGR2_ROVSM_Msk               (0x1UL << ADC_CFGR2_ROVSM_Pos)       /*!< 0x00000400 */\n#define ADC_CFGR2_ROVSM                   ADC_CFGR2_ROVSM_Msk                  /*!< ADC Regular oversampling mode */\n\n#define ADC_CFGR2_RSHIFT1_Pos             (11U)\n#define ADC_CFGR2_RSHIFT1_Msk             (0x1UL << ADC_CFGR2_RSHIFT1_Pos)     /*!< 0x00000800 */\n#define ADC_CFGR2_RSHIFT1                 ADC_CFGR2_RSHIFT1_Msk                /*!< ADC Right-shift data after Offset 1 correction */\n#define ADC_CFGR2_RSHIFT2_Pos             (12U)\n#define ADC_CFGR2_RSHIFT2_Msk             (0x1UL << ADC_CFGR2_RSHIFT2_Pos)     /*!< 0x00001000 */\n#define ADC_CFGR2_RSHIFT2                 ADC_CFGR2_RSHIFT2_Msk                /*!< ADC Right-shift data after Offset 2 correction */\n#define ADC_CFGR2_RSHIFT3_Pos             (13U)\n#define ADC_CFGR2_RSHIFT3_Msk             (0x1UL << ADC_CFGR2_RSHIFT3_Pos)     /*!< 0x00002000 */\n#define ADC_CFGR2_RSHIFT3                 ADC_CFGR2_RSHIFT3_Msk                /*!< ADC Right-shift data after Offset 3 correction */\n#define ADC_CFGR2_RSHIFT4_Pos             (14U)\n#define ADC_CFGR2_RSHIFT4_Msk             (0x1UL << ADC_CFGR2_RSHIFT4_Pos)     /*!< 0x00004000 */\n#define ADC_CFGR2_RSHIFT4                 ADC_CFGR2_RSHIFT4_Msk                /*!< ADC Right-shift data after Offset 4 correction */\n\n#define ADC_CFGR2_OVSR_Pos                (16U)\n#define ADC_CFGR2_OVSR_Msk                (0x3FFUL << ADC_CFGR2_OVSR_Pos)      /*!< 0x03FF0000 */\n#define ADC_CFGR2_OVSR                    ADC_CFGR2_OVSR_Msk                   /*!< ADC oversampling Ratio */\n#define ADC_CFGR2_OVSR_0                  (0x001UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00010000 */\n#define ADC_CFGR2_OVSR_1                  (0x002UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00020000 */\n#define ADC_CFGR2_OVSR_2                  (0x004UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00040000 */\n#define ADC_CFGR2_OVSR_3                  (0x008UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00080000 */\n#define ADC_CFGR2_OVSR_4                  (0x010UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00100000 */\n#define ADC_CFGR2_OVSR_5                  (0x020UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00200000 */\n#define ADC_CFGR2_OVSR_6                  (0x040UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00400000 */\n#define ADC_CFGR2_OVSR_7                  (0x080UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00800000 */\n#define ADC_CFGR2_OVSR_8                  (0x100UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x01000000 */\n#define ADC_CFGR2_OVSR_9                  (0x200UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x02000000 */\n\n#define ADC_CFGR2_LSHIFT_Pos              (28U)\n#define ADC_CFGR2_LSHIFT_Msk              (0xFUL << ADC_CFGR2_LSHIFT_Pos)      /*!< 0xF0000000 */\n#define ADC_CFGR2_LSHIFT                  ADC_CFGR2_LSHIFT_Msk                 /*!< ADC Left shift factor */\n#define ADC_CFGR2_LSHIFT_0                (0x1UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x10000000 */\n#define ADC_CFGR2_LSHIFT_1                (0x2UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x20000000 */\n#define ADC_CFGR2_LSHIFT_2                (0x4UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x40000000 */\n#define ADC_CFGR2_LSHIFT_3                (0x8UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x80000000 */\n\n/********************  Bit definition for ADC_SMPR1 register  ********************/\n#define ADC_SMPR1_SMP0_Pos                (0U)\n#define ADC_SMPR1_SMP0_Msk                (0x7UL << ADC_SMPR1_SMP0_Pos)        /*!< 0x00000007 */\n#define ADC_SMPR1_SMP0                    ADC_SMPR1_SMP0_Msk                   /*!< ADC Channel 0 Sampling time selection  */\n#define ADC_SMPR1_SMP0_0                  (0x1UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000001 */\n#define ADC_SMPR1_SMP0_1                  (0x2UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000002 */\n#define ADC_SMPR1_SMP0_2                  (0x4UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000004 */\n\n#define ADC_SMPR1_SMP1_Pos                (3U)\n#define ADC_SMPR1_SMP1_Msk                (0x7UL << ADC_SMPR1_SMP1_Pos)        /*!< 0x00000038 */\n#define ADC_SMPR1_SMP1                    ADC_SMPR1_SMP1_Msk                   /*!< ADC Channel 1 Sampling time selection  */\n#define ADC_SMPR1_SMP1_0                  (0x1UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000008 */\n#define ADC_SMPR1_SMP1_1                  (0x2UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000010 */\n#define ADC_SMPR1_SMP1_2                  (0x4UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000020 */\n\n#define ADC_SMPR1_SMP2_Pos                (6U)\n#define ADC_SMPR1_SMP2_Msk                (0x7UL << ADC_SMPR1_SMP2_Pos)        /*!< 0x000001C0 */\n#define ADC_SMPR1_SMP2                    ADC_SMPR1_SMP2_Msk                   /*!< ADC Channel 2 Sampling time selection  */\n#define ADC_SMPR1_SMP2_0                  (0x1UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000040 */\n#define ADC_SMPR1_SMP2_1                  (0x2UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000080 */\n#define ADC_SMPR1_SMP2_2                  (0x4UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000100 */\n\n#define ADC_SMPR1_SMP3_Pos                (9U)\n#define ADC_SMPR1_SMP3_Msk                (0x7UL << ADC_SMPR1_SMP3_Pos)        /*!< 0x00000E00 */\n#define ADC_SMPR1_SMP3                    ADC_SMPR1_SMP3_Msk                   /*!< ADC Channel 3 Sampling time selection  */\n#define ADC_SMPR1_SMP3_0                  (0x1UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000200 */\n#define ADC_SMPR1_SMP3_1                  (0x2UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000400 */\n#define ADC_SMPR1_SMP3_2                  (0x4UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000800 */\n\n#define ADC_SMPR1_SMP4_Pos                (12U)\n#define ADC_SMPR1_SMP4_Msk                (0x7UL << ADC_SMPR1_SMP4_Pos)        /*!< 0x00007000 */\n#define ADC_SMPR1_SMP4                    ADC_SMPR1_SMP4_Msk                   /*!< ADC Channel 4 Sampling time selection  */\n#define ADC_SMPR1_SMP4_0                  (0x1UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00001000 */\n#define ADC_SMPR1_SMP4_1                  (0x2UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00002000 */\n#define ADC_SMPR1_SMP4_2                  (0x4UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00004000 */\n\n#define ADC_SMPR1_SMP5_Pos                (15U)\n#define ADC_SMPR1_SMP5_Msk                (0x7UL << ADC_SMPR1_SMP5_Pos)        /*!< 0x00038000 */\n#define ADC_SMPR1_SMP5                    ADC_SMPR1_SMP5_Msk                   /*!< ADC Channel 5 Sampling time selection  */\n#define ADC_SMPR1_SMP5_0                  (0x1UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00008000 */\n#define ADC_SMPR1_SMP5_1                  (0x2UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00010000 */\n#define ADC_SMPR1_SMP5_2                  (0x4UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00020000 */\n\n#define ADC_SMPR1_SMP6_Pos                (18U)\n#define ADC_SMPR1_SMP6_Msk                (0x7UL << ADC_SMPR1_SMP6_Pos)        /*!< 0x001C0000 */\n#define ADC_SMPR1_SMP6                    ADC_SMPR1_SMP6_Msk                   /*!< ADC Channel 6 Sampling time selection  */\n#define ADC_SMPR1_SMP6_0                  (0x1UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00040000 */\n#define ADC_SMPR1_SMP6_1                  (0x2UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00080000 */\n#define ADC_SMPR1_SMP6_2                  (0x4UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00100000 */\n\n#define ADC_SMPR1_SMP7_Pos                (21U)\n#define ADC_SMPR1_SMP7_Msk                (0x7UL << ADC_SMPR1_SMP7_Pos)        /*!< 0x00E00000 */\n#define ADC_SMPR1_SMP7                    ADC_SMPR1_SMP7_Msk                   /*!< ADC Channel 7 Sampling time selection  */\n#define ADC_SMPR1_SMP7_0                  (0x1UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00200000 */\n#define ADC_SMPR1_SMP7_1                  (0x2UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00400000 */\n#define ADC_SMPR1_SMP7_2                  (0x4UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00800000 */\n\n#define ADC_SMPR1_SMP8_Pos                (24U)\n#define ADC_SMPR1_SMP8_Msk                (0x7UL << ADC_SMPR1_SMP8_Pos)        /*!< 0x07000000 */\n#define ADC_SMPR1_SMP8                    ADC_SMPR1_SMP8_Msk                   /*!< ADC Channel 8 Sampling time selection  */\n#define ADC_SMPR1_SMP8_0                  (0x1UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x01000000 */\n#define ADC_SMPR1_SMP8_1                  (0x2UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x02000000 */\n#define ADC_SMPR1_SMP8_2                  (0x4UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x04000000 */\n\n#define ADC_SMPR1_SMP9_Pos                (27U)\n#define ADC_SMPR1_SMP9_Msk                (0x7UL << ADC_SMPR1_SMP9_Pos)        /*!< 0x38000000 */\n#define ADC_SMPR1_SMP9                    ADC_SMPR1_SMP9_Msk                   /*!< ADC Channel 9 Sampling time selection  */\n#define ADC_SMPR1_SMP9_0                  (0x1UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x08000000 */\n#define ADC_SMPR1_SMP9_1                  (0x2UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x10000000 */\n#define ADC_SMPR1_SMP9_2                  (0x4UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x20000000 */\n\n/********************  Bit definition for ADC_SMPR2 register  ********************/\n#define ADC_SMPR2_SMP10_Pos               (0U)\n#define ADC_SMPR2_SMP10_Msk               (0x7UL << ADC_SMPR2_SMP10_Pos)       /*!< 0x00000007 */\n#define ADC_SMPR2_SMP10                   ADC_SMPR2_SMP10_Msk                  /*!< ADC Channel 10 Sampling time selection  */\n#define ADC_SMPR2_SMP10_0                 (0x1UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000001 */\n#define ADC_SMPR2_SMP10_1                 (0x2UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000002 */\n#define ADC_SMPR2_SMP10_2                 (0x4UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000004 */\n\n#define ADC_SMPR2_SMP11_Pos               (3U)\n#define ADC_SMPR2_SMP11_Msk               (0x7UL << ADC_SMPR2_SMP11_Pos)       /*!< 0x00000038 */\n#define ADC_SMPR2_SMP11                   ADC_SMPR2_SMP11_Msk                  /*!< ADC Channel 11 Sampling time selection  */\n#define ADC_SMPR2_SMP11_0                 (0x1UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000008 */\n#define ADC_SMPR2_SMP11_1                 (0x2UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000010 */\n#define ADC_SMPR2_SMP11_2                 (0x4UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000020 */\n\n#define ADC_SMPR2_SMP12_Pos               (6U)\n#define ADC_SMPR2_SMP12_Msk               (0x7UL << ADC_SMPR2_SMP12_Pos)       /*!< 0x000001C0 */\n#define ADC_SMPR2_SMP12                   ADC_SMPR2_SMP12_Msk                  /*!< ADC Channel 12 Sampling time selection  */\n#define ADC_SMPR2_SMP12_0                 (0x1UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000040 */\n#define ADC_SMPR2_SMP12_1                 (0x2UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000080 */\n#define ADC_SMPR2_SMP12_2                 (0x4UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000100 */\n\n#define ADC_SMPR2_SMP13_Pos               (9U)\n#define ADC_SMPR2_SMP13_Msk               (0x7UL << ADC_SMPR2_SMP13_Pos)       /*!< 0x00000E00 */\n#define ADC_SMPR2_SMP13                   ADC_SMPR2_SMP13_Msk                  /*!< ADC Channel 13 Sampling time selection  */\n#define ADC_SMPR2_SMP13_0                 (0x1UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000200 */\n#define ADC_SMPR2_SMP13_1                 (0x2UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000400 */\n#define ADC_SMPR2_SMP13_2                 (0x4UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000800 */\n\n#define ADC_SMPR2_SMP14_Pos               (12U)\n#define ADC_SMPR2_SMP14_Msk               (0x7UL << ADC_SMPR2_SMP14_Pos)       /*!< 0x00007000 */\n#define ADC_SMPR2_SMP14                   ADC_SMPR2_SMP14_Msk                  /*!< ADC Channel 14 Sampling time selection  */\n#define ADC_SMPR2_SMP14_0                 (0x1UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00001000 */\n#define ADC_SMPR2_SMP14_1                 (0x2UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00002000 */\n#define ADC_SMPR2_SMP14_2                 (0x4UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00004000 */\n\n#define ADC_SMPR2_SMP15_Pos               (15U)\n#define ADC_SMPR2_SMP15_Msk               (0x7UL << ADC_SMPR2_SMP15_Pos)       /*!< 0x00038000 */\n#define ADC_SMPR2_SMP15                   ADC_SMPR2_SMP15_Msk                  /*!< ADC Channel 15 Sampling time selection  */\n#define ADC_SMPR2_SMP15_0                 (0x1UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00008000 */\n#define ADC_SMPR2_SMP15_1                 (0x2UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00010000 */\n#define ADC_SMPR2_SMP15_2                 (0x4UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00020000 */\n\n#define ADC_SMPR2_SMP16_Pos               (18U)\n#define ADC_SMPR2_SMP16_Msk               (0x7UL << ADC_SMPR2_SMP16_Pos)       /*!< 0x001C0000 */\n#define ADC_SMPR2_SMP16                   ADC_SMPR2_SMP16_Msk                  /*!< ADC Channel 16 Sampling time selection  */\n#define ADC_SMPR2_SMP16_0                 (0x1UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00040000 */\n#define ADC_SMPR2_SMP16_1                 (0x2UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00080000 */\n#define ADC_SMPR2_SMP16_2                 (0x4UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00100000 */\n\n#define ADC_SMPR2_SMP17_Pos               (21U)\n#define ADC_SMPR2_SMP17_Msk               (0x7UL << ADC_SMPR2_SMP17_Pos)       /*!< 0x00E00000 */\n#define ADC_SMPR2_SMP17                   ADC_SMPR2_SMP17_Msk                  /*!< ADC Channel 17 Sampling time selection  */\n#define ADC_SMPR2_SMP17_0                 (0x1UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00200000 */\n#define ADC_SMPR2_SMP17_1                 (0x2UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00400000 */\n#define ADC_SMPR2_SMP17_2                 (0x4UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00800000 */\n\n#define ADC_SMPR2_SMP18_Pos               (24U)\n#define ADC_SMPR2_SMP18_Msk               (0x7UL << ADC_SMPR2_SMP18_Pos)       /*!< 0x07000000 */\n#define ADC_SMPR2_SMP18                   ADC_SMPR2_SMP18_Msk                  /*!< ADC Channel 18 Sampling time selection  */\n#define ADC_SMPR2_SMP18_0                 (0x1UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x01000000 */\n#define ADC_SMPR2_SMP18_1                 (0x2UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x02000000 */\n#define ADC_SMPR2_SMP18_2                 (0x4UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x04000000 */\n\n#define ADC_SMPR2_SMP19_Pos               (27U)\n#define ADC_SMPR2_SMP19_Msk               (0x7UL << ADC_SMPR2_SMP19_Pos)       /*!< 0x38000000 */\n#define ADC_SMPR2_SMP19                   ADC_SMPR2_SMP19_Msk                  /*!< ADC Channel 19 Sampling time selection  */\n#define ADC_SMPR2_SMP19_0                 (0x1UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x08000000 */\n#define ADC_SMPR2_SMP19_1                 (0x2UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x10000000 */\n#define ADC_SMPR2_SMP19_2                 (0x4UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x20000000 */\n\n/********************  Bit definition for ADC_PCSEL register  ********************/\n#define ADC_PCSEL_PCSEL_Pos               (0U)\n#define ADC_PCSEL_PCSEL_Msk               (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos)   /*!< 0x000FFFFF */\n#define ADC_PCSEL_PCSEL                   ADC_PCSEL_PCSEL_Msk                  /*!< ADC pre channel selection */\n#define ADC_PCSEL_PCSEL_0                 (0x00001UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000001 */\n#define ADC_PCSEL_PCSEL_1                 (0x00002UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000002 */\n#define ADC_PCSEL_PCSEL_2                 (0x00004UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000004 */\n#define ADC_PCSEL_PCSEL_3                 (0x00008UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000008 */\n#define ADC_PCSEL_PCSEL_4                 (0x00010UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000010 */\n#define ADC_PCSEL_PCSEL_5                 (0x00020UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000020 */\n#define ADC_PCSEL_PCSEL_6                 (0x00040UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000040 */\n#define ADC_PCSEL_PCSEL_7                 (0x00080UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000080 */\n#define ADC_PCSEL_PCSEL_8                 (0x00100UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000100 */\n#define ADC_PCSEL_PCSEL_9                 (0x00200UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000200 */\n#define ADC_PCSEL_PCSEL_10                (0x00400UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000400 */\n#define ADC_PCSEL_PCSEL_11                (0x00800UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000800 */\n#define ADC_PCSEL_PCSEL_12                (0x01000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00001000 */\n#define ADC_PCSEL_PCSEL_13                (0x02000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00002000 */\n#define ADC_PCSEL_PCSEL_14                (0x04000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00004000 */\n#define ADC_PCSEL_PCSEL_15                (0x08000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00008000 */\n#define ADC_PCSEL_PCSEL_16                (0x10000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00010000 */\n#define ADC_PCSEL_PCSEL_17                (0x20000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00020000 */\n#define ADC_PCSEL_PCSEL_18                (0x40000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00040000 */\n#define ADC_PCSEL_PCSEL_19                (0x80000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00080000 */\n\n/*****************  Bit definition for ADC_LTR1, 2, 3 registers *****************/\n#define ADC_LTR_LT_Pos                    (0U)\n#define ADC_LTR_LT_Msk                    (0x3FFFFFFUL << ADC_LTR_LT_Pos)      /*!< 0x03FFFFFF */\n#define ADC_LTR_LT                        ADC_LTR_LT_Msk                       /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */\n\n/*****************  Bit definition for ADC_HTR1, 2, 3 registers  ****************/\n#define ADC_HTR_HT_Pos                    (0U)\n#define ADC_HTR_HT_Msk                    (0x3FFFFFFUL << ADC_HTR_HT_Pos)      /*!< 0x03FFFFFF */\n#define ADC_HTR_HT                        ADC_HTR_HT_Msk                       /*!< ADC Analog watchdog 1,2 and 3 higher threshold */\n\n\n/********************  Bit definition for ADC_SQR1 register  ********************/\n#define ADC_SQR1_L_Pos                    (0U)\n#define ADC_SQR1_L_Msk                    (0xFUL << ADC_SQR1_L_Pos)            /*!< 0x0000000F */\n#define ADC_SQR1_L                        ADC_SQR1_L_Msk                       /*!< ADC regular channel sequence length */\n#define ADC_SQR1_L_0                      (0x1UL << ADC_SQR1_L_Pos)             /*!< 0x00000001 */\n#define ADC_SQR1_L_1                      (0x2UL << ADC_SQR1_L_Pos)             /*!< 0x00000002 */\n#define ADC_SQR1_L_2                      (0x4UL << ADC_SQR1_L_Pos)             /*!< 0x00000004 */\n#define ADC_SQR1_L_3                      (0x8UL << ADC_SQR1_L_Pos)             /*!< 0x00000008 */\n\n#define ADC_SQR1_SQ1_Pos                  (6U)\n#define ADC_SQR1_SQ1_Msk                  (0x1FUL << ADC_SQR1_SQ1_Pos)         /*!< 0x000007C0 */\n#define ADC_SQR1_SQ1                      ADC_SQR1_SQ1_Msk                     /*!< ADC 1st conversion in regular sequence */\n#define ADC_SQR1_SQ1_0                    (0x01UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000040 */\n#define ADC_SQR1_SQ1_1                    (0x02UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000080 */\n#define ADC_SQR1_SQ1_2                    (0x04UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000100 */\n#define ADC_SQR1_SQ1_3                    (0x08UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000200 */\n#define ADC_SQR1_SQ1_4                    (0x10UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000400 */\n\n#define ADC_SQR1_SQ2_Pos                  (12U)\n#define ADC_SQR1_SQ2_Msk                  (0x1FUL << ADC_SQR1_SQ2_Pos)         /*!< 0x0001F000 */\n#define ADC_SQR1_SQ2                      ADC_SQR1_SQ2_Msk                     /*!< ADC 2nd conversion in regular sequence */\n#define ADC_SQR1_SQ2_0                    (0x01UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00001000 */\n#define ADC_SQR1_SQ2_1                    (0x02UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00002000 */\n#define ADC_SQR1_SQ2_2                    (0x04UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00004000 */\n#define ADC_SQR1_SQ2_3                    (0x08UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00008000 */\n#define ADC_SQR1_SQ2_4                    (0x10UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00010000 */\n\n#define ADC_SQR1_SQ3_Pos                  (18U)\n#define ADC_SQR1_SQ3_Msk                  (0x1FUL << ADC_SQR1_SQ3_Pos)         /*!< 0x007C0000 */\n#define ADC_SQR1_SQ3                      ADC_SQR1_SQ3_Msk                     /*!< ADC 3rd conversion in regular sequence */\n#define ADC_SQR1_SQ3_0                    (0x01UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00040000 */\n#define ADC_SQR1_SQ3_1                    (0x02UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00080000 */\n#define ADC_SQR1_SQ3_2                    (0x04UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00100000 */\n#define ADC_SQR1_SQ3_3                    (0x08UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00200000 */\n#define ADC_SQR1_SQ3_4                    (0x10UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00400000 */\n\n#define ADC_SQR1_SQ4_Pos                  (24U)\n#define ADC_SQR1_SQ4_Msk                  (0x1FUL << ADC_SQR1_SQ4_Pos)         /*!< 0x1F000000 */\n#define ADC_SQR1_SQ4                      ADC_SQR1_SQ4_Msk                     /*!< ADC 4th conversion in regular sequence */\n#define ADC_SQR1_SQ4_0                    (0x01UL << ADC_SQR1_SQ4_Pos)          /*!< 0x01000000 */\n#define ADC_SQR1_SQ4_1                    (0x02UL << ADC_SQR1_SQ4_Pos)          /*!< 0x02000000 */\n#define ADC_SQR1_SQ4_2                    (0x04UL << ADC_SQR1_SQ4_Pos)          /*!< 0x04000000 */\n#define ADC_SQR1_SQ4_3                    (0x08UL << ADC_SQR1_SQ4_Pos)          /*!< 0x08000000 */\n#define ADC_SQR1_SQ4_4                    (0x10UL << ADC_SQR1_SQ4_Pos)          /*!< 0x10000000 */\n\n/********************  Bit definition for ADC_SQR2 register  ********************/\n#define ADC_SQR2_SQ5_Pos                  (0U)\n#define ADC_SQR2_SQ5_Msk                  (0x1FUL << ADC_SQR2_SQ5_Pos)         /*!< 0x0000001F */\n#define ADC_SQR2_SQ5                      ADC_SQR2_SQ5_Msk                     /*!< ADC 5th conversion in regular sequence */\n#define ADC_SQR2_SQ5_0                    (0x01UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000001 */\n#define ADC_SQR2_SQ5_1                    (0x02UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000002 */\n#define ADC_SQR2_SQ5_2                    (0x04UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000004 */\n#define ADC_SQR2_SQ5_3                    (0x08UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000008 */\n#define ADC_SQR2_SQ5_4                    (0x10UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000010 */\n\n#define ADC_SQR2_SQ6_Pos                  (6U)\n#define ADC_SQR2_SQ6_Msk                  (0x1FUL << ADC_SQR2_SQ6_Pos)         /*!< 0x000007C0 */\n#define ADC_SQR2_SQ6                      ADC_SQR2_SQ6_Msk                     /*!< ADC 6th conversion in regular sequence */\n#define ADC_SQR2_SQ6_0                    (0x01UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000040 */\n#define ADC_SQR2_SQ6_1                    (0x02UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000080 */\n#define ADC_SQR2_SQ6_2                    (0x04UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000100 */\n#define ADC_SQR2_SQ6_3                    (0x08UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000200 */\n#define ADC_SQR2_SQ6_4                    (0x10UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000400 */\n\n#define ADC_SQR2_SQ7_Pos                  (12U)\n#define ADC_SQR2_SQ7_Msk                  (0x1FUL << ADC_SQR2_SQ7_Pos)         /*!< 0x0001F000 */\n#define ADC_SQR2_SQ7                      ADC_SQR2_SQ7_Msk                     /*!< ADC 7th conversion in regular sequence */\n#define ADC_SQR2_SQ7_0                    (0x01UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00001000 */\n#define ADC_SQR2_SQ7_1                    (0x02UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00002000 */\n#define ADC_SQR2_SQ7_2                    (0x04UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00004000 */\n#define ADC_SQR2_SQ7_3                    (0x08UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00008000 */\n#define ADC_SQR2_SQ7_4                    (0x10UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00010000 */\n\n#define ADC_SQR2_SQ8_Pos                  (18U)\n#define ADC_SQR2_SQ8_Msk                  (0x1FUL << ADC_SQR2_SQ8_Pos)         /*!< 0x007C0000 */\n#define ADC_SQR2_SQ8                      ADC_SQR2_SQ8_Msk                     /*!< ADC 8th conversion in regular sequence */\n#define ADC_SQR2_SQ8_0                    (0x01UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00040000 */\n#define ADC_SQR2_SQ8_1                    (0x02UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00080000 */\n#define ADC_SQR2_SQ8_2                    (0x04UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00100000 */\n#define ADC_SQR2_SQ8_3                    (0x08UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00200000 */\n#define ADC_SQR2_SQ8_4                    (0x10UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00400000 */\n\n#define ADC_SQR2_SQ9_Pos                  (24U)\n#define ADC_SQR2_SQ9_Msk                  (0x1FUL << ADC_SQR2_SQ9_Pos)         /*!< 0x1F000000 */\n#define ADC_SQR2_SQ9                      ADC_SQR2_SQ9_Msk                     /*!< ADC 9th conversion in regular sequence */\n#define ADC_SQR2_SQ9_0                    (0x01UL << ADC_SQR2_SQ9_Pos)          /*!< 0x01000000 */\n#define ADC_SQR2_SQ9_1                    (0x02UL << ADC_SQR2_SQ9_Pos)          /*!< 0x02000000 */\n#define ADC_SQR2_SQ9_2                    (0x04UL << ADC_SQR2_SQ9_Pos)          /*!< 0x04000000 */\n#define ADC_SQR2_SQ9_3                    (0x08UL << ADC_SQR2_SQ9_Pos)          /*!< 0x08000000 */\n#define ADC_SQR2_SQ9_4                    (0x10UL << ADC_SQR2_SQ9_Pos)          /*!< 0x10000000 */\n\n/********************  Bit definition for ADC_SQR3 register  ********************/\n#define ADC_SQR3_SQ10_Pos                 (0U)\n#define ADC_SQR3_SQ10_Msk                 (0x1FUL << ADC_SQR3_SQ10_Pos)        /*!< 0x0000001F */\n#define ADC_SQR3_SQ10                     ADC_SQR3_SQ10_Msk                    /*!< ADC 10th conversion in regular sequence */\n#define ADC_SQR3_SQ10_0                   (0x01UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000001 */\n#define ADC_SQR3_SQ10_1                   (0x02UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000002 */\n#define ADC_SQR3_SQ10_2                   (0x04UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000004 */\n#define ADC_SQR3_SQ10_3                   (0x08UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000008 */\n#define ADC_SQR3_SQ10_4                   (0x10UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000010 */\n\n#define ADC_SQR3_SQ11_Pos                 (6U)\n#define ADC_SQR3_SQ11_Msk                 (0x1FUL << ADC_SQR3_SQ11_Pos)        /*!< 0x000007C0 */\n#define ADC_SQR3_SQ11                     ADC_SQR3_SQ11_Msk                    /*!< ADC 11th conversion in regular sequence */\n#define ADC_SQR3_SQ11_0                   (0x01UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000040 */\n#define ADC_SQR3_SQ11_1                   (0x02UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000080 */\n#define ADC_SQR3_SQ11_2                   (0x04UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000100 */\n#define ADC_SQR3_SQ11_3                   (0x08UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000200 */\n#define ADC_SQR3_SQ11_4                   (0x10UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000400 */\n\n#define ADC_SQR3_SQ12_Pos                 (12U)\n#define ADC_SQR3_SQ12_Msk                 (0x1FUL << ADC_SQR3_SQ12_Pos)        /*!< 0x0001F000 */\n#define ADC_SQR3_SQ12                     ADC_SQR3_SQ12_Msk                    /*!< ADC 12th conversion in regular sequence */\n#define ADC_SQR3_SQ12_0                   (0x01UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00001000 */\n#define ADC_SQR3_SQ12_1                   (0x02UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00002000 */\n#define ADC_SQR3_SQ12_2                   (0x04UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00004000 */\n#define ADC_SQR3_SQ12_3                   (0x08UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00008000 */\n#define ADC_SQR3_SQ12_4                   (0x10UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00010000 */\n\n#define ADC_SQR3_SQ13_Pos                 (18U)\n#define ADC_SQR3_SQ13_Msk                 (0x1FUL << ADC_SQR3_SQ13_Pos)        /*!< 0x007C0000 */\n#define ADC_SQR3_SQ13                     ADC_SQR3_SQ13_Msk                    /*!< ADC 13th conversion in regular sequence */\n#define ADC_SQR3_SQ13_0                   (0x01UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00040000 */\n#define ADC_SQR3_SQ13_1                   (0x02UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00080000 */\n#define ADC_SQR3_SQ13_2                   (0x04UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00100000 */\n#define ADC_SQR3_SQ13_3                   (0x08UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00200000 */\n#define ADC_SQR3_SQ13_4                   (0x10UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00400000 */\n\n#define ADC_SQR3_SQ14_Pos                 (24U)\n#define ADC_SQR3_SQ14_Msk                 (0x1FUL << ADC_SQR3_SQ14_Pos)        /*!< 0x1F000000 */\n#define ADC_SQR3_SQ14                     ADC_SQR3_SQ14_Msk                    /*!< ADC 14th conversion in regular sequence */\n#define ADC_SQR3_SQ14_0                   (0x01UL << ADC_SQR3_SQ14_Pos)         /*!< 0x01000000 */\n#define ADC_SQR3_SQ14_1                   (0x02UL << ADC_SQR3_SQ14_Pos)         /*!< 0x02000000 */\n#define ADC_SQR3_SQ14_2                   (0x04UL << ADC_SQR3_SQ14_Pos)         /*!< 0x04000000 */\n#define ADC_SQR3_SQ14_3                   (0x08UL << ADC_SQR3_SQ14_Pos)         /*!< 0x08000000 */\n#define ADC_SQR3_SQ14_4                   (0x10UL << ADC_SQR3_SQ14_Pos)         /*!< 0x10000000 */\n\n/********************  Bit definition for ADC_SQR4 register  ********************/\n#define ADC_SQR4_SQ15_Pos                 (0U)\n#define ADC_SQR4_SQ15_Msk                 (0x1FUL << ADC_SQR4_SQ15_Pos)        /*!< 0x0000001F */\n#define ADC_SQR4_SQ15                     ADC_SQR4_SQ15_Msk                    /*!< ADC 15th conversion in regular sequence */\n#define ADC_SQR4_SQ15_0                   (0x01UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000001 */\n#define ADC_SQR4_SQ15_1                   (0x02UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000002 */\n#define ADC_SQR4_SQ15_2                   (0x04UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000004 */\n#define ADC_SQR4_SQ15_3                   (0x08UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000008 */\n#define ADC_SQR4_SQ15_4                   (0x10UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000010 */\n\n#define ADC_SQR4_SQ16_Pos                 (6U)\n#define ADC_SQR4_SQ16_Msk                 (0x1FUL << ADC_SQR4_SQ16_Pos)        /*!< 0x000007C0 */\n#define ADC_SQR4_SQ16                     ADC_SQR4_SQ16_Msk                    /*!< ADC 16th conversion in regular sequence */\n#define ADC_SQR4_SQ16_0                   (0x01UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000040 */\n#define ADC_SQR4_SQ16_1                   (0x02UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000080 */\n#define ADC_SQR4_SQ16_2                   (0x04UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000100 */\n#define ADC_SQR4_SQ16_3                   (0x08UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000200 */\n#define ADC_SQR4_SQ16_4                   (0x10UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000400 */\n/********************  Bit definition for ADC_DR register  ********************/\n#define ADC_DR_RDATA_Pos                  (0U)\n#define ADC_DR_RDATA_Msk                  (0xFFFFFFFFUL << ADC_DR_RDATA_Pos)   /*!< 0xFFFFFFFF */\n#define ADC_DR_RDATA                      ADC_DR_RDATA_Msk                     /*!< ADC regular Data converted */\n\n/********************  Bit definition for ADC_JSQR register  ********************/\n#define ADC_JSQR_JL_Pos                   (0U)\n#define ADC_JSQR_JL_Msk                   (0x3UL << ADC_JSQR_JL_Pos)           /*!< 0x00000003 */\n#define ADC_JSQR_JL                       ADC_JSQR_JL_Msk                      /*!< ADC injected channel sequence length */\n#define ADC_JSQR_JL_0                     (0x1UL << ADC_JSQR_JL_Pos)           /*!< 0x00000001 */\n#define ADC_JSQR_JL_1                     (0x2UL << ADC_JSQR_JL_Pos)           /*!< 0x00000002 */\n\n#define ADC_JSQR_JEXTSEL_Pos              (2U)\n#define ADC_JSQR_JEXTSEL_Msk              (0x1FUL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x0000007C */\n#define ADC_JSQR_JEXTSEL                  ADC_JSQR_JEXTSEL_Msk                 /*!< ADC external trigger selection for injected group */\n#define ADC_JSQR_JEXTSEL_0                (0x01UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000004 */\n#define ADC_JSQR_JEXTSEL_1                (0x02UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000008 */\n#define ADC_JSQR_JEXTSEL_2                (0x04UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000010 */\n#define ADC_JSQR_JEXTSEL_3                (0x08UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000020 */\n#define ADC_JSQR_JEXTSEL_4                (0x10UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000040 */\n\n#define ADC_JSQR_JEXTEN_Pos               (7U)\n#define ADC_JSQR_JEXTEN_Msk               (0x3UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000180 */\n#define ADC_JSQR_JEXTEN                   ADC_JSQR_JEXTEN_Msk                  /*!< ADC external trigger enable and polarity selection for injected channels */\n#define ADC_JSQR_JEXTEN_0                 (0x1UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000080 */\n#define ADC_JSQR_JEXTEN_1                 (0x2UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000100 */\n\n#define ADC_JSQR_JSQ1_Pos                 (9U)\n#define ADC_JSQR_JSQ1_Msk                 (0x1FUL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00003E00 */\n#define ADC_JSQR_JSQ1                     ADC_JSQR_JSQ1_Msk                    /*!< ADC 1st conversion in injected sequence */\n#define ADC_JSQR_JSQ1_0                   (0x01UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000200 */\n#define ADC_JSQR_JSQ1_1                   (0x02UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000400 */\n#define ADC_JSQR_JSQ1_2                   (0x04UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000800 */\n#define ADC_JSQR_JSQ1_3                   (0x08UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00001000 */\n#define ADC_JSQR_JSQ1_4                   (0x10UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00002000 */\n\n#define ADC_JSQR_JSQ2_Pos                 (15U)\n#define ADC_JSQR_JSQ2_Msk                 (0x1FUL << ADC_JSQR_JSQ2_Pos)        /*!< 0x000F8000 */\n#define ADC_JSQR_JSQ2                     ADC_JSQR_JSQ2_Msk                    /*!< ADC 2nd conversion in injected sequence */\n#define ADC_JSQR_JSQ2_0                   (0x01UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00008000 */\n#define ADC_JSQR_JSQ2_1                   (0x02UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00010000 */\n#define ADC_JSQR_JSQ2_2                   (0x04UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00020000 */\n#define ADC_JSQR_JSQ2_3                   (0x08UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00040000 */\n#define ADC_JSQR_JSQ2_4                   (0x10UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00080000 */\n\n#define ADC_JSQR_JSQ3_Pos                 (21U)\n#define ADC_JSQR_JSQ3_Msk                 (0x1FUL << ADC_JSQR_JSQ3_Pos)        /*!< 0x03E00000 */\n#define ADC_JSQR_JSQ3                     ADC_JSQR_JSQ3_Msk                    /*!< ADC 3rd conversion in injected sequence */\n#define ADC_JSQR_JSQ3_0                   (0x01UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00200000 */\n#define ADC_JSQR_JSQ3_1                   (0x02UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00400000 */\n#define ADC_JSQR_JSQ3_2                   (0x04UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00800000 */\n#define ADC_JSQR_JSQ3_3                   (0x08UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x01000000 */\n#define ADC_JSQR_JSQ3_4                   (0x10UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x02000000 */\n\n#define ADC_JSQR_JSQ4_Pos                 (27U)\n#define ADC_JSQR_JSQ4_Msk                 (0x1FUL << ADC_JSQR_JSQ4_Pos)        /*!< 0xF8000000 */\n#define ADC_JSQR_JSQ4                     ADC_JSQR_JSQ4_Msk                    /*!< ADC 4th conversion in injected sequence */\n#define ADC_JSQR_JSQ4_0                   (0x01UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x08000000 */\n#define ADC_JSQR_JSQ4_1                   (0x02UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x10000000 */\n#define ADC_JSQR_JSQ4_2                   (0x04UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x20000000 */\n#define ADC_JSQR_JSQ4_3                   (0x08UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x40000000 */\n#define ADC_JSQR_JSQ4_4                   (0x10UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x80000000 */\n\n/********************  Bit definition for ADC_OFR1 register  ********************/\n#define ADC_OFR1_OFFSET1_Pos              (0U)\n#define ADC_OFR1_OFFSET1_Msk              (0x3FFFFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x03FFFFFF */\n#define ADC_OFR1_OFFSET1                  ADC_OFR1_OFFSET1_Msk                  /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */\n#define ADC_OFR1_OFFSET1_0                (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */\n#define ADC_OFR1_OFFSET1_1                (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */\n#define ADC_OFR1_OFFSET1_2                (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */\n#define ADC_OFR1_OFFSET1_3                (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */\n#define ADC_OFR1_OFFSET1_4                (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */\n#define ADC_OFR1_OFFSET1_5                (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */\n#define ADC_OFR1_OFFSET1_6                (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */\n#define ADC_OFR1_OFFSET1_7                (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */\n#define ADC_OFR1_OFFSET1_8                (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */\n#define ADC_OFR1_OFFSET1_9                (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */\n#define ADC_OFR1_OFFSET1_10               (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */\n#define ADC_OFR1_OFFSET1_11               (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */\n#define ADC_OFR1_OFFSET1_12               (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */\n#define ADC_OFR1_OFFSET1_13               (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */\n#define ADC_OFR1_OFFSET1_14               (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */\n#define ADC_OFR1_OFFSET1_15               (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */\n#define ADC_OFR1_OFFSET1_16               (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */\n#define ADC_OFR1_OFFSET1_17               (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */\n#define ADC_OFR1_OFFSET1_18               (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */\n#define ADC_OFR1_OFFSET1_19               (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */\n#define ADC_OFR1_OFFSET1_20               (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */\n#define ADC_OFR1_OFFSET1_21               (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */\n#define ADC_OFR1_OFFSET1_22               (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */\n#define ADC_OFR1_OFFSET1_23               (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */\n#define ADC_OFR1_OFFSET1_24               (0x1000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x01000000 */\n#define ADC_OFR1_OFFSET1_25               (0x2000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x02000000 */\n\n#define ADC_OFR1_OFFSET1_CH_Pos           (26U)\n#define ADC_OFR1_OFFSET1_CH_Msk           (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x7C000000 */\n#define ADC_OFR1_OFFSET1_CH               ADC_OFR1_OFFSET1_CH_Msk               /*!< ADC Channel selection for the data offset 1 */\n#define ADC_OFR1_OFFSET1_CH_0             (0x01UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x04000000 */\n#define ADC_OFR1_OFFSET1_CH_1             (0x02UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x08000000 */\n#define ADC_OFR1_OFFSET1_CH_2             (0x04UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x10000000 */\n#define ADC_OFR1_OFFSET1_CH_3             (0x08UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x20000000 */\n#define ADC_OFR1_OFFSET1_CH_4             (0x10UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x40000000 */\n\n#define ADC_OFR1_SSATE_Pos                (31U)\n#define ADC_OFR1_SSATE_Msk                (0x1UL << ADC_OFR1_SSATE_Pos)         /*!< 0x80000000 */\n#define ADC_OFR1_SSATE                    ADC_OFR1_SSATE_Msk                    /*!< ADC Signed saturation Enable */\n\n\n/********************  Bit definition for ADC_OFR2 register  ********************/\n#define ADC_OFR2_OFFSET2_Pos              (0U)\n#define ADC_OFR2_OFFSET2_Msk              (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */\n#define ADC_OFR2_OFFSET2                  ADC_OFR2_OFFSET2_Msk                  /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */\n#define ADC_OFR2_OFFSET2_0                (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */\n#define ADC_OFR2_OFFSET2_1                (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */\n#define ADC_OFR2_OFFSET2_2                (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */\n#define ADC_OFR2_OFFSET2_3                (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */\n#define ADC_OFR2_OFFSET2_4                (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */\n#define ADC_OFR2_OFFSET2_5                (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */\n#define ADC_OFR2_OFFSET2_6                (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */\n#define ADC_OFR2_OFFSET2_7                (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */\n#define ADC_OFR2_OFFSET2_8                (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */\n#define ADC_OFR2_OFFSET2_9                (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */\n#define ADC_OFR2_OFFSET2_10               (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */\n#define ADC_OFR2_OFFSET2_11               (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */\n#define ADC_OFR2_OFFSET2_12               (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */\n#define ADC_OFR2_OFFSET2_13               (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */\n#define ADC_OFR2_OFFSET2_14               (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */\n#define ADC_OFR2_OFFSET2_15               (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */\n#define ADC_OFR2_OFFSET2_16               (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */\n#define ADC_OFR2_OFFSET2_17               (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */\n#define ADC_OFR2_OFFSET2_18               (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */\n#define ADC_OFR2_OFFSET2_19               (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */\n#define ADC_OFR2_OFFSET2_20               (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */\n#define ADC_OFR2_OFFSET2_21               (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */\n#define ADC_OFR2_OFFSET2_22               (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */\n#define ADC_OFR2_OFFSET2_23               (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */\n#define ADC_OFR2_OFFSET2_24               (0x1000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x01000000 */\n#define ADC_OFR2_OFFSET2_25               (0x2000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x02000000 */\n\n#define ADC_OFR2_OFFSET2_CH_Pos           (26U)\n#define ADC_OFR2_OFFSET2_CH_Msk           (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x7C000000 */\n#define ADC_OFR2_OFFSET2_CH               ADC_OFR2_OFFSET2_CH_Msk               /*!< ADC Channel selection for the data offset 2 */\n#define ADC_OFR2_OFFSET2_CH_0             (0x01UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x04000000 */\n#define ADC_OFR2_OFFSET2_CH_1             (0x02UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x08000000 */\n#define ADC_OFR2_OFFSET2_CH_2             (0x04UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x10000000 */\n#define ADC_OFR2_OFFSET2_CH_3             (0x08UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x20000000 */\n#define ADC_OFR2_OFFSET2_CH_4             (0x10UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x40000000 */\n\n#define ADC_OFR2_SSATE_Pos                (31U)\n#define ADC_OFR2_SSATE_Msk                (0x1UL << ADC_OFR2_SSATE_Pos)         /*!< 0x80000000 */\n#define ADC_OFR2_SSATE                    ADC_OFR2_SSATE_Msk                    /*!< ADC Signed saturation Enable */\n\n\n/********************  Bit definition for ADC_OFR3 register  ********************/\n#define ADC_OFR3_OFFSET3_Pos              (0U)\n#define ADC_OFR3_OFFSET3_Msk              (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */\n#define ADC_OFR3_OFFSET3                  ADC_OFR3_OFFSET3_Msk                  /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */\n#define ADC_OFR3_OFFSET3_0                (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */\n#define ADC_OFR3_OFFSET3_1                (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */\n#define ADC_OFR3_OFFSET3_2                (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */\n#define ADC_OFR3_OFFSET3_3                (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */\n#define ADC_OFR3_OFFSET3_4                (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */\n#define ADC_OFR3_OFFSET3_5                (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */\n#define ADC_OFR3_OFFSET3_6                (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */\n#define ADC_OFR3_OFFSET3_7                (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */\n#define ADC_OFR3_OFFSET3_8                (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */\n#define ADC_OFR3_OFFSET3_9                (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */\n#define ADC_OFR3_OFFSET3_10               (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */\n#define ADC_OFR3_OFFSET3_11               (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */\n#define ADC_OFR3_OFFSET3_12               (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */\n#define ADC_OFR3_OFFSET3_13               (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */\n#define ADC_OFR3_OFFSET3_14               (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */\n#define ADC_OFR3_OFFSET3_15               (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */\n#define ADC_OFR3_OFFSET3_16               (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */\n#define ADC_OFR3_OFFSET3_17               (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */\n#define ADC_OFR3_OFFSET3_18               (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */\n#define ADC_OFR3_OFFSET3_19               (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */\n#define ADC_OFR3_OFFSET3_20               (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */\n#define ADC_OFR3_OFFSET3_21               (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */\n#define ADC_OFR3_OFFSET3_22               (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */\n#define ADC_OFR3_OFFSET3_23               (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */\n#define ADC_OFR3_OFFSET3_24               (0x1000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x01000000 */\n#define ADC_OFR3_OFFSET3_25               (0x2000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x02000000 */\n\n#define ADC_OFR3_OFFSET3_CH_Pos           (26U)\n#define ADC_OFR3_OFFSET3_CH_Msk           (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x7C000000 */\n#define ADC_OFR3_OFFSET3_CH               ADC_OFR3_OFFSET3_CH_Msk               /*!< ADC Channel selection for the data offset 3 */\n#define ADC_OFR3_OFFSET3_CH_0             (0x01UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x04000000 */\n#define ADC_OFR3_OFFSET3_CH_1             (0x02UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x08000000 */\n#define ADC_OFR3_OFFSET3_CH_2             (0x04UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x10000000 */\n#define ADC_OFR3_OFFSET3_CH_3             (0x08UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x20000000 */\n#define ADC_OFR3_OFFSET3_CH_4             (0x10UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x40000000 */\n\n#define ADC_OFR3_SSATE_Pos                (31U)\n#define ADC_OFR3_SSATE_Msk                (0x1UL << ADC_OFR3_SSATE_Pos)         /*!< 0x80000000 */\n#define ADC_OFR3_SSATE                    ADC_OFR3_SSATE_Msk                    /*!< ADC Signed saturation Enable */\n\n\n/********************  Bit definition for ADC_OFR4 register  ********************/\n#define ADC_OFR4_OFFSET4_Pos              (0U)\n#define ADC_OFR4_OFFSET4_Msk              (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */\n#define ADC_OFR4_OFFSET4                  ADC_OFR4_OFFSET4_Msk                  /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */\n#define ADC_OFR4_OFFSET4_0                (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */\n#define ADC_OFR4_OFFSET4_1                (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */\n#define ADC_OFR4_OFFSET4_2                (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */\n#define ADC_OFR4_OFFSET4_3                (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */\n#define ADC_OFR4_OFFSET4_4                (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */\n#define ADC_OFR4_OFFSET4_5                (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */\n#define ADC_OFR4_OFFSET4_6                (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */\n#define ADC_OFR4_OFFSET4_7                (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */\n#define ADC_OFR4_OFFSET4_8                (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */\n#define ADC_OFR4_OFFSET4_9                (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */\n#define ADC_OFR4_OFFSET4_10               (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */\n#define ADC_OFR4_OFFSET4_11               (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */\n#define ADC_OFR4_OFFSET4_12               (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */\n#define ADC_OFR4_OFFSET4_13               (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */\n#define ADC_OFR4_OFFSET4_14               (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */\n#define ADC_OFR4_OFFSET4_15               (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */\n#define ADC_OFR4_OFFSET4_16               (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */\n#define ADC_OFR4_OFFSET4_17               (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */\n#define ADC_OFR4_OFFSET4_18               (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */\n#define ADC_OFR4_OFFSET4_19               (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */\n#define ADC_OFR4_OFFSET4_20               (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */\n#define ADC_OFR4_OFFSET4_21               (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */\n#define ADC_OFR4_OFFSET4_22               (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */\n#define ADC_OFR4_OFFSET4_23               (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */\n#define ADC_OFR4_OFFSET4_24               (0x1000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x01000000 */\n#define ADC_OFR4_OFFSET4_25               (0x2000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x02000000 */\n\n#define ADC_OFR4_OFFSET4_CH_Pos           (26U)\n#define ADC_OFR4_OFFSET4_CH_Msk           (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x7C000000 */\n#define ADC_OFR4_OFFSET4_CH               ADC_OFR4_OFFSET4_CH_Msk               /*!< ADC Channel selection for the data offset 4 */\n#define ADC_OFR4_OFFSET4_CH_0             (0x01UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x04000000 */\n#define ADC_OFR4_OFFSET4_CH_1             (0x02UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x08000000 */\n#define ADC_OFR4_OFFSET4_CH_2             (0x04UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x10000000 */\n#define ADC_OFR4_OFFSET4_CH_3             (0x08UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x20000000 */\n#define ADC_OFR4_OFFSET4_CH_4             (0x10UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x40000000 */\n\n#define ADC_OFR4_SSATE_Pos                (31U)\n#define ADC_OFR4_SSATE_Msk                (0x1UL << ADC_OFR4_SSATE_Pos)         /*!< 0x80000000 */\n#define ADC_OFR4_SSATE                    ADC_OFR4_SSATE_Msk                    /*!< ADC Signed saturation Enable */\n\n\n/********************  Bit definition for ADC_JDR1 register  ********************/\n#define ADC_JDR1_JDATA_Pos                (0U)\n#define ADC_JDR1_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos)  /*!< 0xFFFFFFFF */\n#define ADC_JDR1_JDATA                    ADC_JDR1_JDATA_Msk                    /*!< ADC Injected DATA */\n#define ADC_JDR1_JDATA_0                  (0x00000001UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000001 */\n#define ADC_JDR1_JDATA_1                  (0x00000002UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000002 */\n#define ADC_JDR1_JDATA_2                  (0x00000004UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000004 */\n#define ADC_JDR1_JDATA_3                  (0x00000008UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000008 */\n#define ADC_JDR1_JDATA_4                  (0x00000010UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000010 */\n#define ADC_JDR1_JDATA_5                  (0x00000020UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000020 */\n#define ADC_JDR1_JDATA_6                  (0x00000040UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000040 */\n#define ADC_JDR1_JDATA_7                  (0x00000080UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000080 */\n#define ADC_JDR1_JDATA_8                  (0x00000100UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000100 */\n#define ADC_JDR1_JDATA_9                  (0x00000200UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000200 */\n#define ADC_JDR1_JDATA_10                 (0x00000400UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000400 */\n#define ADC_JDR1_JDATA_11                 (0x00000800UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000800 */\n#define ADC_JDR1_JDATA_12                 (0x00001000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00001000 */\n#define ADC_JDR1_JDATA_13                 (0x00002000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00002000 */\n#define ADC_JDR1_JDATA_14                 (0x00004000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00004000 */\n#define ADC_JDR1_JDATA_15                 (0x00008000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00008000 */\n#define ADC_JDR1_JDATA_16                 (0x00010000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00010000 */\n#define ADC_JDR1_JDATA_17                 (0x00020000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00020000 */\n#define ADC_JDR1_JDATA_18                 (0x00040000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00040000 */\n#define ADC_JDR1_JDATA_19                 (0x00080000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00080000 */\n#define ADC_JDR1_JDATA_20                 (0x00100000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00100000 */\n#define ADC_JDR1_JDATA_21                 (0x00200000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00200000 */\n#define ADC_JDR1_JDATA_22                 (0x00400000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00400000 */\n#define ADC_JDR1_JDATA_23                 (0x00800000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00800000 */\n#define ADC_JDR1_JDATA_24                 (0x01000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x01000000 */\n#define ADC_JDR1_JDATA_25                 (0x02000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x02000000 */\n#define ADC_JDR1_JDATA_26                 (0x04000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x04000000 */\n#define ADC_JDR1_JDATA_27                 (0x08000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x08000000 */\n#define ADC_JDR1_JDATA_28                 (0x10000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x10000000 */\n#define ADC_JDR1_JDATA_29                 (0x20000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x20000000 */\n#define ADC_JDR1_JDATA_30                 (0x40000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x40000000 */\n#define ADC_JDR1_JDATA_31                 (0x80000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x80000000 */\n\n/********************  Bit definition for ADC_JDR2 register  ********************/\n#define ADC_JDR2_JDATA_Pos                (0U)\n#define ADC_JDR2_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos)  /*!< 0xFFFFFFFF */\n#define ADC_JDR2_JDATA                    ADC_JDR2_JDATA_Msk                    /*!< ADC Injected DATA */\n#define ADC_JDR2_JDATA_0                  (0x00000001UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000001 */\n#define ADC_JDR2_JDATA_1                  (0x00000002UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000002 */\n#define ADC_JDR2_JDATA_2                  (0x00000004UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000004 */\n#define ADC_JDR2_JDATA_3                  (0x00000008UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000008 */\n#define ADC_JDR2_JDATA_4                  (0x00000010UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000010 */\n#define ADC_JDR2_JDATA_5                  (0x00000020UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000020 */\n#define ADC_JDR2_JDATA_6                  (0x00000040UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000040 */\n#define ADC_JDR2_JDATA_7                  (0x00000080UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000080 */\n#define ADC_JDR2_JDATA_8                  (0x00000100UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000100 */\n#define ADC_JDR2_JDATA_9                  (0x00000200UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000200 */\n#define ADC_JDR2_JDATA_10                 (0x00000400UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000400 */\n#define ADC_JDR2_JDATA_11                 (0x00000800UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000800 */\n#define ADC_JDR2_JDATA_12                 (0x00001000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00001000 */\n#define ADC_JDR2_JDATA_13                 (0x00002000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00002000 */\n#define ADC_JDR2_JDATA_14                 (0x00004000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00004000 */\n#define ADC_JDR2_JDATA_15                 (0x00008000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00008000 */\n#define ADC_JDR2_JDATA_16                 (0x00010000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00010000 */\n#define ADC_JDR2_JDATA_17                 (0x00020000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00020000 */\n#define ADC_JDR2_JDATA_18                 (0x00040000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00040000 */\n#define ADC_JDR2_JDATA_19                 (0x00080000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00080000 */\n#define ADC_JDR2_JDATA_20                 (0x00100000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00100000 */\n#define ADC_JDR2_JDATA_21                 (0x00200000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00200000 */\n#define ADC_JDR2_JDATA_22                 (0x00400000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00400000 */\n#define ADC_JDR2_JDATA_23                 (0x00800000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00800000 */\n#define ADC_JDR2_JDATA_24                 (0x01000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x01000000 */\n#define ADC_JDR2_JDATA_25                 (0x02000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x02000000 */\n#define ADC_JDR2_JDATA_26                 (0x04000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x04000000 */\n#define ADC_JDR2_JDATA_27                 (0x08000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x08000000 */\n#define ADC_JDR2_JDATA_28                 (0x10000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x10000000 */\n#define ADC_JDR2_JDATA_29                 (0x20000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x20000000 */\n#define ADC_JDR2_JDATA_30                 (0x40000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x40000000 */\n#define ADC_JDR2_JDATA_31                 (0x80000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x80000000 */\n\n/********************  Bit definition for ADC_JDR3 register  ********************/\n#define ADC_JDR3_JDATA_Pos                (0U)\n#define ADC_JDR3_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos)  /*!< 0xFFFFFFFF */\n#define ADC_JDR3_JDATA                    ADC_JDR3_JDATA_Msk                    /*!< ADC Injected DATA */\n#define ADC_JDR3_JDATA_0                  (0x00000001UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000001 */\n#define ADC_JDR3_JDATA_1                  (0x00000002UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000002 */\n#define ADC_JDR3_JDATA_2                  (0x00000004UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000004 */\n#define ADC_JDR3_JDATA_3                  (0x00000008UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000008 */\n#define ADC_JDR3_JDATA_4                  (0x00000010UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000010 */\n#define ADC_JDR3_JDATA_5                  (0x00000020UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000020 */\n#define ADC_JDR3_JDATA_6                  (0x00000040UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000040 */\n#define ADC_JDR3_JDATA_7                  (0x00000080UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000080 */\n#define ADC_JDR3_JDATA_8                  (0x00000100UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000100 */\n#define ADC_JDR3_JDATA_9                  (0x00000200UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000200 */\n#define ADC_JDR3_JDATA_10                 (0x00000400UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000400 */\n#define ADC_JDR3_JDATA_11                 (0x00000800UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000800 */\n#define ADC_JDR3_JDATA_12                 (0x00001000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00001000 */\n#define ADC_JDR3_JDATA_13                 (0x00002000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00002000 */\n#define ADC_JDR3_JDATA_14                 (0x00004000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00004000 */\n#define ADC_JDR3_JDATA_15                 (0x00008000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00008000 */\n#define ADC_JDR3_JDATA_16                 (0x00010000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00010000 */\n#define ADC_JDR3_JDATA_17                 (0x00020000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00020000 */\n#define ADC_JDR3_JDATA_18                 (0x00040000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00040000 */\n#define ADC_JDR3_JDATA_19                 (0x00080000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00080000 */\n#define ADC_JDR3_JDATA_20                 (0x00100000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00100000 */\n#define ADC_JDR3_JDATA_21                 (0x00200000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00200000 */\n#define ADC_JDR3_JDATA_22                 (0x00400000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00400000 */\n#define ADC_JDR3_JDATA_23                 (0x00800000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00800000 */\n#define ADC_JDR3_JDATA_24                 (0x01000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x01000000 */\n#define ADC_JDR3_JDATA_25                 (0x02000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x02000000 */\n#define ADC_JDR3_JDATA_26                 (0x04000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x04000000 */\n#define ADC_JDR3_JDATA_27                 (0x08000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x08000000 */\n#define ADC_JDR3_JDATA_28                 (0x10000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x10000000 */\n#define ADC_JDR3_JDATA_29                 (0x20000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x20000000 */\n#define ADC_JDR3_JDATA_30                 (0x40000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x40000000 */\n#define ADC_JDR3_JDATA_31                 (0x80000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x80000000 */\n\n/********************  Bit definition for ADC_JDR4 register  ********************/\n#define ADC_JDR4_JDATA_Pos                (0U)\n#define ADC_JDR4_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos)  /*!< 0xFFFFFFFF */\n#define ADC_JDR4_JDATA                    ADC_JDR4_JDATA_Msk                    /*!< ADC Injected DATA */\n#define ADC_JDR4_JDATA_0                  (0x00000001UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000001 */\n#define ADC_JDR4_JDATA_1                  (0x00000002UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000002 */\n#define ADC_JDR4_JDATA_2                  (0x00000004UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000004 */\n#define ADC_JDR4_JDATA_3                  (0x00000008UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000008 */\n#define ADC_JDR4_JDATA_4                  (0x00000010UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000010 */\n#define ADC_JDR4_JDATA_5                  (0x00000020UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000020 */\n#define ADC_JDR4_JDATA_6                  (0x00000040UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000040 */\n#define ADC_JDR4_JDATA_7                  (0x00000080UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000080 */\n#define ADC_JDR4_JDATA_8                  (0x00000100UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000100 */\n#define ADC_JDR4_JDATA_9                  (0x00000200UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000200 */\n#define ADC_JDR4_JDATA_10                 (0x00000400UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000400 */\n#define ADC_JDR4_JDATA_11                 (0x00000800UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000800 */\n#define ADC_JDR4_JDATA_12                 (0x00001000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00001000 */\n#define ADC_JDR4_JDATA_13                 (0x00002000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00002000 */\n#define ADC_JDR4_JDATA_14                 (0x00004000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00004000 */\n#define ADC_JDR4_JDATA_15                 (0x00008000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00008000 */\n#define ADC_JDR4_JDATA_16                 (0x00010000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00010000 */\n#define ADC_JDR4_JDATA_17                 (0x00020000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00020000 */\n#define ADC_JDR4_JDATA_18                 (0x00040000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00040000 */\n#define ADC_JDR4_JDATA_19                 (0x00080000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00080000 */\n#define ADC_JDR4_JDATA_20                 (0x00100000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00100000 */\n#define ADC_JDR4_JDATA_21                 (0x00200000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00200000 */\n#define ADC_JDR4_JDATA_22                 (0x00400000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00400000 */\n#define ADC_JDR4_JDATA_23                 (0x00800000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00800000 */\n#define ADC_JDR4_JDATA_24                 (0x01000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x01000000 */\n#define ADC_JDR4_JDATA_25                 (0x02000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x02000000 */\n#define ADC_JDR4_JDATA_26                 (0x04000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x04000000 */\n#define ADC_JDR4_JDATA_27                 (0x08000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x08000000 */\n#define ADC_JDR4_JDATA_28                 (0x10000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x10000000 */\n#define ADC_JDR4_JDATA_29                 (0x20000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x20000000 */\n#define ADC_JDR4_JDATA_30                 (0x40000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x40000000 */\n#define ADC_JDR4_JDATA_31                 (0x80000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x80000000 */\n\n/********************  Bit definition for ADC_AWD2CR register  ********************/\n#define ADC_AWD2CR_AWD2CH_Pos             (0U)\n#define ADC_AWD2CR_AWD2CH_Msk             (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x000FFFFF */\n#define ADC_AWD2CR_AWD2CH                 ADC_AWD2CR_AWD2CH_Msk                 /*!< ADC Analog watchdog 2 channel selection */\n#define ADC_AWD2CR_AWD2CH_0               (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000001 */\n#define ADC_AWD2CR_AWD2CH_1               (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000002 */\n#define ADC_AWD2CR_AWD2CH_2               (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000004 */\n#define ADC_AWD2CR_AWD2CH_3               (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000008 */\n#define ADC_AWD2CR_AWD2CH_4               (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000010 */\n#define ADC_AWD2CR_AWD2CH_5               (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000020 */\n#define ADC_AWD2CR_AWD2CH_6               (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000040 */\n#define ADC_AWD2CR_AWD2CH_7               (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000080 */\n#define ADC_AWD2CR_AWD2CH_8               (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000100 */\n#define ADC_AWD2CR_AWD2CH_9               (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000200 */\n#define ADC_AWD2CR_AWD2CH_10              (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000400 */\n#define ADC_AWD2CR_AWD2CH_11              (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000800 */\n#define ADC_AWD2CR_AWD2CH_12              (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00001000 */\n#define ADC_AWD2CR_AWD2CH_13              (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00002000 */\n#define ADC_AWD2CR_AWD2CH_14              (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00004000 */\n#define ADC_AWD2CR_AWD2CH_15              (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00008000 */\n#define ADC_AWD2CR_AWD2CH_16              (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00010000 */\n#define ADC_AWD2CR_AWD2CH_17              (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00020000 */\n#define ADC_AWD2CR_AWD2CH_18              (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00040000 */\n#define ADC_AWD2CR_AWD2CH_19              (0x80000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00080000 */\n\n/********************  Bit definition for ADC_AWD3CR register  ********************/\n#define ADC_AWD3CR_AWD3CH_Pos             (0U)\n#define ADC_AWD3CR_AWD3CH_Msk             (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x000FFFFF */\n#define ADC_AWD3CR_AWD3CH                 ADC_AWD3CR_AWD3CH_Msk                 /*!< ADC Analog watchdog 2 channel selection */\n#define ADC_AWD3CR_AWD3CH_0               (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000001 */\n#define ADC_AWD3CR_AWD3CH_1               (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000002 */\n#define ADC_AWD3CR_AWD3CH_2               (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000004 */\n#define ADC_AWD3CR_AWD3CH_3               (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000008 */\n#define ADC_AWD3CR_AWD3CH_4               (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000010 */\n#define ADC_AWD3CR_AWD3CH_5               (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000020 */\n#define ADC_AWD3CR_AWD3CH_6               (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000040 */\n#define ADC_AWD3CR_AWD3CH_7               (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000080 */\n#define ADC_AWD3CR_AWD3CH_8               (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000100 */\n#define ADC_AWD3CR_AWD3CH_9               (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000200 */\n#define ADC_AWD3CR_AWD3CH_10              (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000400 */\n#define ADC_AWD3CR_AWD3CH_11              (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000800 */\n#define ADC_AWD3CR_AWD3CH_12              (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00001000 */\n#define ADC_AWD3CR_AWD3CH_13              (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00002000 */\n#define ADC_AWD3CR_AWD3CH_14              (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00004000 */\n#define ADC_AWD3CR_AWD3CH_15              (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00008000 */\n#define ADC_AWD3CR_AWD3CH_16              (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00010000 */\n#define ADC_AWD3CR_AWD3CH_17              (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00020000 */\n#define ADC_AWD3CR_AWD3CH_18              (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00040000 */\n#define ADC_AWD3CR_AWD3CH_19              (0x80000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00080000 */\n\n/********************  Bit definition for ADC_DIFSEL register  ********************/\n#define ADC_DIFSEL_DIFSEL_Pos             (0U)\n#define ADC_DIFSEL_DIFSEL_Msk             (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x000FFFFF */\n#define ADC_DIFSEL_DIFSEL                 ADC_DIFSEL_DIFSEL_Msk                 /*!< ADC differential modes for channels 1 to 18 */\n#define ADC_DIFSEL_DIFSEL_0               (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000001 */\n#define ADC_DIFSEL_DIFSEL_1               (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000002 */\n#define ADC_DIFSEL_DIFSEL_2               (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000004 */\n#define ADC_DIFSEL_DIFSEL_3               (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000008 */\n#define ADC_DIFSEL_DIFSEL_4               (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000010 */\n#define ADC_DIFSEL_DIFSEL_5               (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000020 */\n#define ADC_DIFSEL_DIFSEL_6               (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000040 */\n#define ADC_DIFSEL_DIFSEL_7               (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000080 */\n#define ADC_DIFSEL_DIFSEL_8               (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000100 */\n#define ADC_DIFSEL_DIFSEL_9               (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000200 */\n#define ADC_DIFSEL_DIFSEL_10              (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000400 */\n#define ADC_DIFSEL_DIFSEL_11              (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000800 */\n#define ADC_DIFSEL_DIFSEL_12              (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00001000 */\n#define ADC_DIFSEL_DIFSEL_13              (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00002000 */\n#define ADC_DIFSEL_DIFSEL_14              (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00004000 */\n#define ADC_DIFSEL_DIFSEL_15              (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00008000 */\n#define ADC_DIFSEL_DIFSEL_16              (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00010000 */\n#define ADC_DIFSEL_DIFSEL_17              (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00020000 */\n#define ADC_DIFSEL_DIFSEL_18              (0x40000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00040000 */\n#define ADC_DIFSEL_DIFSEL_19              (0x80000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00080000 */\n\n/********************  Bit definition for ADC_CALFACT register  ********************/\n#define ADC_CALFACT_CALFACT_S_Pos         (0U)\n#define ADC_CALFACT_CALFACT_S_Msk         (0x7FFUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000007FF */\n#define ADC_CALFACT_CALFACT_S             ADC_CALFACT_CALFACT_S_Msk              /*!< ADC calibration factors in single-ended mode */\n#define ADC_CALFACT_CALFACT_S_0           (0x001UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */\n#define ADC_CALFACT_CALFACT_S_1           (0x002UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */\n#define ADC_CALFACT_CALFACT_S_2           (0x004UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */\n#define ADC_CALFACT_CALFACT_S_3           (0x008UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */\n#define ADC_CALFACT_CALFACT_S_4           (0x010UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */\n#define ADC_CALFACT_CALFACT_S_5           (0x020UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */\n#define ADC_CALFACT_CALFACT_S_6           (0x040UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */\n#define ADC_CALFACT_CALFACT_S_7           (0x080UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */\n#define ADC_CALFACT_CALFACT_S_8           (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */\n#define ADC_CALFACT_CALFACT_S_9           (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */\n#define ADC_CALFACT_CALFACT_S_10          (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */\n#define ADC_CALFACT_CALFACT_D_Pos         (16U)\n#define ADC_CALFACT_CALFACT_D_Msk         (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */\n#define ADC_CALFACT_CALFACT_D             ADC_CALFACT_CALFACT_D_Msk              /*!< ADC calibration factors in differential mode */\n#define ADC_CALFACT_CALFACT_D_0           (0x001UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */\n#define ADC_CALFACT_CALFACT_D_1           (0x002UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */\n#define ADC_CALFACT_CALFACT_D_2           (0x004UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */\n#define ADC_CALFACT_CALFACT_D_3           (0x008UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */\n#define ADC_CALFACT_CALFACT_D_4           (0x010UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */\n#define ADC_CALFACT_CALFACT_D_5           (0x020UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */\n#define ADC_CALFACT_CALFACT_D_6           (0x040UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */\n#define ADC_CALFACT_CALFACT_D_7           (0x080UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */\n#define ADC_CALFACT_CALFACT_D_8           (0x100UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */\n#define ADC_CALFACT_CALFACT_D_9           (0x200UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */\n#define ADC_CALFACT_CALFACT_D_10          (0x400UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x04000000 */\n\n/********************  Bit definition for ADC_CALFACT2 register  ********************/\n#define ADC_CALFACT2_LINCALFACT_Pos       (0U)\n#define ADC_CALFACT2_LINCALFACT_Msk       (0x3FFFFFFFUL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x3FFFFFFF */\n#define ADC_CALFACT2_LINCALFACT           ADC_CALFACT2_LINCALFACT_Msk                   /*!< ADC Linearity calibration factors */\n#define ADC_CALFACT2_LINCALFACT_0         (0x00000001UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000001 */\n#define ADC_CALFACT2_LINCALFACT_1         (0x00000002UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000002 */\n#define ADC_CALFACT2_LINCALFACT_2         (0x00000004UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000004 */\n#define ADC_CALFACT2_LINCALFACT_3         (0x00000008UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000008 */\n#define ADC_CALFACT2_LINCALFACT_4         (0x00000010UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000010 */\n#define ADC_CALFACT2_LINCALFACT_5         (0x00000020UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000020 */\n#define ADC_CALFACT2_LINCALFACT_6         (0x00000040UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000040 */\n#define ADC_CALFACT2_LINCALFACT_7         (0x00000080UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000080 */\n#define ADC_CALFACT2_LINCALFACT_8         (0x00000100UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000100 */\n#define ADC_CALFACT2_LINCALFACT_9         (0x00000200UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000200 */\n#define ADC_CALFACT2_LINCALFACT_10        (0x00000400UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000400 */\n#define ADC_CALFACT2_LINCALFACT_11        (0x00000800UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000800 */\n#define ADC_CALFACT2_LINCALFACT_12        (0x00001000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00001000 */\n#define ADC_CALFACT2_LINCALFACT_13        (0x00002000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00002000 */\n#define ADC_CALFACT2_LINCALFACT_14        (0x00004000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00004000 */\n#define ADC_CALFACT2_LINCALFACT_15        (0x00008000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00008000 */\n#define ADC_CALFACT2_LINCALFACT_16        (0x00010000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00010000 */\n#define ADC_CALFACT2_LINCALFACT_17        (0x00020000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00020000 */\n#define ADC_CALFACT2_LINCALFACT_18        (0x00040000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00040000 */\n#define ADC_CALFACT2_LINCALFACT_19        (0x00080000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00080000 */\n#define ADC_CALFACT2_LINCALFACT_20        (0x00100000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00100000 */\n#define ADC_CALFACT2_LINCALFACT_21        (0x00200000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00200000 */\n#define ADC_CALFACT2_LINCALFACT_22        (0x00400000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00400000 */\n#define ADC_CALFACT2_LINCALFACT_23        (0x00800000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00800000 */\n#define ADC_CALFACT2_LINCALFACT_24        (0x01000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x01000000 */\n#define ADC_CALFACT2_LINCALFACT_25        (0x02000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x02000000 */\n#define ADC_CALFACT2_LINCALFACT_26        (0x04000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x04000000 */\n#define ADC_CALFACT2_LINCALFACT_27        (0x08000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x08000000 */\n#define ADC_CALFACT2_LINCALFACT_28        (0x10000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x10000000 */\n#define ADC_CALFACT2_LINCALFACT_29        (0x20000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x20000000 */\n\n/*************************  ADC Common registers  *****************************/\n/********************  Bit definition for ADC_CSR register  ********************/\n#define ADC_CSR_ADRDY_MST_Pos             (0U)\n#define ADC_CSR_ADRDY_MST_Msk             (0x1UL << ADC_CSR_ADRDY_MST_Pos)     /*!< 0x00000001 */\n#define ADC_CSR_ADRDY_MST                 ADC_CSR_ADRDY_MST_Msk                /*!< Master ADC ready */\n#define ADC_CSR_EOSMP_MST_Pos             (1U)\n#define ADC_CSR_EOSMP_MST_Msk             (0x1UL << ADC_CSR_EOSMP_MST_Pos)     /*!< 0x00000002 */\n#define ADC_CSR_EOSMP_MST                 ADC_CSR_EOSMP_MST_Msk                /*!< End of sampling phase flag of the master ADC */\n#define ADC_CSR_EOC_MST_Pos               (2U)\n#define ADC_CSR_EOC_MST_Msk               (0x1UL << ADC_CSR_EOC_MST_Pos)       /*!< 0x00000004 */\n#define ADC_CSR_EOC_MST                   ADC_CSR_EOC_MST_Msk                  /*!< End of regular conversion of the master ADC */\n#define ADC_CSR_EOS_MST_Pos               (3U)\n#define ADC_CSR_EOS_MST_Msk               (0x1UL << ADC_CSR_EOS_MST_Pos)       /*!< 0x00000008 */\n#define ADC_CSR_EOS_MST                   ADC_CSR_EOS_MST_Msk                  /*!< End of regular sequence flag of the master ADC */\n#define ADC_CSR_OVR_MST_Pos               (4U)\n#define ADC_CSR_OVR_MST_Msk               (0x1UL << ADC_CSR_OVR_MST_Pos)       /*!< 0x00000010 */\n#define ADC_CSR_OVR_MST                   ADC_CSR_OVR_MST_Msk                  /*!< Overrun flag of the master ADC */\n#define ADC_CSR_JEOC_MST_Pos              (5U)\n#define ADC_CSR_JEOC_MST_Msk              (0x1UL << ADC_CSR_JEOC_MST_Pos)      /*!< 0x00000020 */\n#define ADC_CSR_JEOC_MST                  ADC_CSR_JEOC_MST_Msk                 /*!< End of injected conversion of the master ADC */\n#define ADC_CSR_JEOS_MST_Pos              (6U)\n#define ADC_CSR_JEOS_MST_Msk              (0x1UL << ADC_CSR_JEOS_MST_Pos)      /*!< 0x00000040 */\n#define ADC_CSR_JEOS_MST                  ADC_CSR_JEOS_MST_Msk                 /*!< End of injected sequence flag of the master ADC */\n#define ADC_CSR_AWD1_MST_Pos              (7U)\n#define ADC_CSR_AWD1_MST_Msk              (0x1UL << ADC_CSR_AWD1_MST_Pos)      /*!< 0x00000080 */\n#define ADC_CSR_AWD1_MST                  ADC_CSR_AWD1_MST_Msk                 /*!< Analog watchdog 1 flag of the master ADC */\n#define ADC_CSR_AWD2_MST_Pos              (8U)\n#define ADC_CSR_AWD2_MST_Msk              (0x1UL << ADC_CSR_AWD2_MST_Pos)      /*!< 0x00000100 */\n#define ADC_CSR_AWD2_MST                  ADC_CSR_AWD2_MST_Msk                 /*!< Analog watchdog 2 flag of the master ADC */\n#define ADC_CSR_AWD3_MST_Pos              (9U)\n#define ADC_CSR_AWD3_MST_Msk              (0x1UL << ADC_CSR_AWD3_MST_Pos)      /*!< 0x00000200 */\n#define ADC_CSR_AWD3_MST                  ADC_CSR_AWD3_MST_Msk                 /*!< Analog watchdog 3 flag of the master ADC */\n#define ADC_CSR_JQOVF_MST_Pos             (10U)\n#define ADC_CSR_JQOVF_MST_Msk             (0x1UL << ADC_CSR_JQOVF_MST_Pos)     /*!< 0x00000400 */\n#define ADC_CSR_JQOVF_MST                 ADC_CSR_JQOVF_MST_Msk                /*!< Injected context queue overflow flag of the master ADC */\n#define ADC_CSR_ADRDY_SLV_Pos             (16U)\n#define ADC_CSR_ADRDY_SLV_Msk             (0x1UL << ADC_CSR_ADRDY_SLV_Pos)     /*!< 0x00010000 */\n#define ADC_CSR_ADRDY_SLV                 ADC_CSR_ADRDY_SLV_Msk                /*!< Slave ADC ready */\n#define ADC_CSR_EOSMP_SLV_Pos             (17U)\n#define ADC_CSR_EOSMP_SLV_Msk             (0x1UL << ADC_CSR_EOSMP_SLV_Pos)     /*!< 0x00020000 */\n#define ADC_CSR_EOSMP_SLV                 ADC_CSR_EOSMP_SLV_Msk                /*!< End of sampling phase flag of the slave ADC */\n#define ADC_CSR_EOC_SLV_Pos               (18U)\n#define ADC_CSR_EOC_SLV_Msk               (0x1UL << ADC_CSR_EOC_SLV_Pos)       /*!< 0x00040000 */\n#define ADC_CSR_EOC_SLV                   ADC_CSR_EOC_SLV_Msk                  /*!< End of regular conversion of the slave ADC */\n#define ADC_CSR_EOS_SLV_Pos               (19U)\n#define ADC_CSR_EOS_SLV_Msk               (0x1UL << ADC_CSR_EOS_SLV_Pos)       /*!< 0x00080000 */\n#define ADC_CSR_EOS_SLV                   ADC_CSR_EOS_SLV_Msk                  /*!< End of regular sequence flag of the slave ADC */\n#define ADC_CSR_OVR_SLV_Pos               (20U)\n#define ADC_CSR_OVR_SLV_Msk               (0x1UL << ADC_CSR_OVR_SLV_Pos)       /*!< 0x00100000 */\n#define ADC_CSR_OVR_SLV                   ADC_CSR_OVR_SLV_Msk                  /*!< Overrun flag of the slave ADC */\n#define ADC_CSR_JEOC_SLV_Pos              (21U)\n#define ADC_CSR_JEOC_SLV_Msk              (0x1UL << ADC_CSR_JEOC_SLV_Pos)      /*!< 0x00200000 */\n#define ADC_CSR_JEOC_SLV                  ADC_CSR_JEOC_SLV_Msk                 /*!< End of injected conversion of the slave ADC */\n#define ADC_CSR_JEOS_SLV_Pos              (22U)\n#define ADC_CSR_JEOS_SLV_Msk              (0x1UL << ADC_CSR_JEOS_SLV_Pos)      /*!< 0x00400000 */\n#define ADC_CSR_JEOS_SLV                  ADC_CSR_JEOS_SLV_Msk                 /*!< End of injected sequence flag of the slave ADC */\n#define ADC_CSR_AWD1_SLV_Pos              (23U)\n#define ADC_CSR_AWD1_SLV_Msk              (0x1UL << ADC_CSR_AWD1_SLV_Pos)      /*!< 0x00800000 */\n#define ADC_CSR_AWD1_SLV                  ADC_CSR_AWD1_SLV_Msk                 /*!< Analog watchdog 1 flag of the slave ADC */\n#define ADC_CSR_AWD2_SLV_Pos              (24U)\n#define ADC_CSR_AWD2_SLV_Msk              (0x1UL << ADC_CSR_AWD2_SLV_Pos)      /*!< 0x01000000 */\n#define ADC_CSR_AWD2_SLV                  ADC_CSR_AWD2_SLV_Msk                 /*!< Analog watchdog 2 flag of the slave ADC */\n#define ADC_CSR_AWD3_SLV_Pos              (25U)\n#define ADC_CSR_AWD3_SLV_Msk              (0x1UL << ADC_CSR_AWD3_SLV_Pos)      /*!< 0x02000000 */\n#define ADC_CSR_AWD3_SLV                  ADC_CSR_AWD3_SLV_Msk                 /*!< Analog watchdog 3 flag of the slave ADC */\n#define ADC_CSR_JQOVF_SLV_Pos             (26U)\n#define ADC_CSR_JQOVF_SLV_Msk             (0x1UL << ADC_CSR_JQOVF_SLV_Pos)     /*!< 0x04000000 */\n#define ADC_CSR_JQOVF_SLV                 ADC_CSR_JQOVF_SLV_Msk                /*!< Injected context queue overflow flag of the slave ADC */\n\n/********************  Bit definition for ADC_CCR register  ********************/\n#define ADC_CCR_DUAL_Pos                  (0U)\n#define ADC_CCR_DUAL_Msk                  (0x1FUL << ADC_CCR_DUAL_Pos)          /*!< 0x0000001F */\n#define ADC_CCR_DUAL                      ADC_CCR_DUAL_Msk                      /*!< Dual ADC mode selection */\n#define ADC_CCR_DUAL_0                    (0x01UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000001 */\n#define ADC_CCR_DUAL_1                    (0x02UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000002 */\n#define ADC_CCR_DUAL_2                    (0x04UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000004 */\n#define ADC_CCR_DUAL_3                    (0x08UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000008 */\n#define ADC_CCR_DUAL_4                    (0x10UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000010 */\n\n#define ADC_CCR_DELAY_Pos                 (8U)\n#define ADC_CCR_DELAY_Msk                 (0xFUL << ADC_CCR_DELAY_Pos)          /*!< 0x00000F00 */\n#define ADC_CCR_DELAY                     ADC_CCR_DELAY_Msk                     /*!< Delay between 2 sampling phases */\n#define ADC_CCR_DELAY_0                   (0x1UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000100 */\n#define ADC_CCR_DELAY_1                   (0x2UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000200 */\n#define ADC_CCR_DELAY_2                   (0x4UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000400 */\n#define ADC_CCR_DELAY_3                   (0x8UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000800 */\n\n\n#define ADC_CCR_DAMDF_Pos                 (14U)\n#define ADC_CCR_DAMDF_Msk                 (0x3UL << ADC_CCR_DAMDF_Pos)          /*!< 0x0000C000 */\n#define ADC_CCR_DAMDF                     ADC_CCR_DAMDF_Msk                     /*!< Dual ADC mode Data format */\n#define ADC_CCR_DAMDF_0                   (0x1UL << ADC_CCR_DAMDF_Pos)          /*!< 0x00004000 */\n#define ADC_CCR_DAMDF_1                   (0x2UL << ADC_CCR_DAMDF_Pos)          /*!< 0x00008000 */\n\n#define ADC_CCR_CKMODE_Pos                (16U)\n#define ADC_CCR_CKMODE_Msk                (0x3UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00030000 */\n#define ADC_CCR_CKMODE                    ADC_CCR_CKMODE_Msk                    /*!< ADC clock mode */\n#define ADC_CCR_CKMODE_0                  (0x1UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00010000 */\n#define ADC_CCR_CKMODE_1                  (0x2UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00020000 */\n\n#define ADC_CCR_PRESC_Pos                 (18U)\n#define ADC_CCR_PRESC_Msk                 (0xFUL << ADC_CCR_PRESC_Pos)          /*!< 0x003C0000 */\n#define ADC_CCR_PRESC                     ADC_CCR_PRESC_Msk                     /*!< ADC prescaler */\n#define ADC_CCR_PRESC_0                   (0x1UL << ADC_CCR_PRESC_Pos)          /*!< 0x00040000 */\n#define ADC_CCR_PRESC_1                   (0x2UL << ADC_CCR_PRESC_Pos)          /*!< 0x00080000 */\n#define ADC_CCR_PRESC_2                   (0x4UL << ADC_CCR_PRESC_Pos)          /*!< 0x00100000 */\n#define ADC_CCR_PRESC_3                   (0x8UL << ADC_CCR_PRESC_Pos)          /*!< 0x00200000 */\n\n#define ADC_CCR_VREFEN_Pos                (22U)\n#define ADC_CCR_VREFEN_Msk                (0x1UL << ADC_CCR_VREFEN_Pos)         /*!< 0x00400000 */\n#define ADC_CCR_VREFEN                    ADC_CCR_VREFEN_Msk                    /*!< VREFINT enable */\n#define ADC_CCR_TSEN_Pos                  (23U)\n#define ADC_CCR_TSEN_Msk                  (0x1UL << ADC_CCR_TSEN_Pos)           /*!< 0x00800000 */\n#define ADC_CCR_TSEN                      ADC_CCR_TSEN_Msk                      /*!< Temperature sensor enable */\n#define ADC_CCR_VBATEN_Pos                (24U)\n#define ADC_CCR_VBATEN_Msk                (0x1UL << ADC_CCR_VBATEN_Pos)         /*!< 0x01000000 */\n#define ADC_CCR_VBATEN                    ADC_CCR_VBATEN_Msk                    /*!< VBAT enable */\n\n/********************  Bit definition for ADC_CDR register  *******************/\n#define ADC_CDR_RDATA_MST_Pos             (0U)\n#define ADC_CDR_RDATA_MST_Msk             (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)   /*!< 0x0000FFFF */\n#define ADC_CDR_RDATA_MST                 ADC_CDR_RDATA_MST_Msk                 /*!< ADC multimode master group regular conversion data */\n\n#define ADC_CDR_RDATA_SLV_Pos             (16U)\n#define ADC_CDR_RDATA_SLV_Msk             (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)   /*!< 0xFFFF0000 */\n#define ADC_CDR_RDATA_SLV                 ADC_CDR_RDATA_SLV_Msk                 /*!< ADC multimode slave group regular conversion data */\n\n/********************  Bit definition for ADC_CDR2 register  ******************/\n#define ADC_CDR2_RDATA_ALT_Pos            (0U)\n#define ADC_CDR2_RDATA_ALT_Msk            (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */\n#define ADC_CDR2_RDATA_ALT                ADC_CDR2_RDATA_ALT_Msk                   /*!< Regular data of the master/slave alternated ADCs */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                                   VREFBUF                                  */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for VREFBUF_CSR register  ****************/\n#define VREFBUF_CSR_ENVR_Pos        (0U)\n#define VREFBUF_CSR_ENVR_Msk        (0x1UL << VREFBUF_CSR_ENVR_Pos)            /*!< 0x00000001 */\n#define VREFBUF_CSR_ENVR            VREFBUF_CSR_ENVR_Msk                       /*!<Voltage reference buffer enable */\n#define VREFBUF_CSR_HIZ_Pos         (1U)\n#define VREFBUF_CSR_HIZ_Msk         (0x1UL << VREFBUF_CSR_HIZ_Pos)             /*!< 0x00000002 */\n#define VREFBUF_CSR_HIZ             VREFBUF_CSR_HIZ_Msk                        /*!<High impedance mode             */\n#define VREFBUF_CSR_VRR_Pos         (3U)\n#define VREFBUF_CSR_VRR_Msk         (0x1UL << VREFBUF_CSR_VRR_Pos)             /*!< 0x00000008 */\n#define VREFBUF_CSR_VRR             VREFBUF_CSR_VRR_Msk                        /*!<Voltage reference buffer ready  */\n#define VREFBUF_CSR_VRS_Pos         (4U)\n#define VREFBUF_CSR_VRS_Msk         (0x7UL << VREFBUF_CSR_VRS_Pos)             /*!< 0x00000070 */\n#define VREFBUF_CSR_VRS             VREFBUF_CSR_VRS_Msk                        /*!<Voltage reference scale         */\n\n#define VREFBUF_CSR_VRS_OUT1        ((uint32_t)0x00000000)                     /*!<Voltage reference VREF_OUT1     */\n#define VREFBUF_CSR_VRS_OUT2_Pos    (4U)\n#define VREFBUF_CSR_VRS_OUT2_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos)        /*!< 0x00000010 */\n#define VREFBUF_CSR_VRS_OUT2        VREFBUF_CSR_VRS_OUT2_Msk                   /*!<Voltage reference VREF_OUT2     */\n#define VREFBUF_CSR_VRS_OUT3_Pos    (5U)\n#define VREFBUF_CSR_VRS_OUT3_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT3_Pos)        /*!< 0x00000020 */\n#define VREFBUF_CSR_VRS_OUT3        VREFBUF_CSR_VRS_OUT3_Msk                   /*!<Voltage reference VREF_OUT3     */\n#define VREFBUF_CSR_VRS_OUT4_Pos    (4U)\n#define VREFBUF_CSR_VRS_OUT4_Msk    (0x3UL << VREFBUF_CSR_VRS_OUT4_Pos)        /*!< 0x00000030 */\n#define VREFBUF_CSR_VRS_OUT4        VREFBUF_CSR_VRS_OUT4_Msk                   /*!<Voltage reference VREF_OUT4     */\n\n/*******************  Bit definition for VREFBUF_CCR register  ****************/\n#define VREFBUF_CCR_TRIM_Pos        (0U)\n#define VREFBUF_CCR_TRIM_Msk        (0x3FUL << VREFBUF_CCR_TRIM_Pos)           /*!< 0x0000003F */\n#define VREFBUF_CCR_TRIM            VREFBUF_CCR_TRIM_Msk                       /*!<TRIM[5:0] bits (Trimming code)  */\n\n/******************************************************************************/\n/*                                                                            */\n/*                 Flexible Datarate Controller Area Network                  */\n/*                                                                            */\n/******************************************************************************/\n/*!<FDCAN control and status registers */\n/*****************  Bit definition for FDCAN_CREL register  *******************/\n#define FDCAN_CREL_DAY_Pos        (0U)\n#define FDCAN_CREL_DAY_Msk        (0xFFUL << FDCAN_CREL_DAY_Pos)               /*!< 0x000000FF */\n#define FDCAN_CREL_DAY            FDCAN_CREL_DAY_Msk                           /*!<Timestamp Day                           */\n#define FDCAN_CREL_MON_Pos        (8U)\n#define FDCAN_CREL_MON_Msk        (0xFFUL << FDCAN_CREL_MON_Pos)               /*!< 0x0000FF00 */\n#define FDCAN_CREL_MON            FDCAN_CREL_MON_Msk                           /*!<Timestamp Month                         */\n#define FDCAN_CREL_YEAR_Pos       (16U)\n#define FDCAN_CREL_YEAR_Msk       (0xFUL << FDCAN_CREL_YEAR_Pos)               /*!< 0x000F0000 */\n#define FDCAN_CREL_YEAR           FDCAN_CREL_YEAR_Msk                          /*!<Timestamp Year                          */\n#define FDCAN_CREL_SUBSTEP_Pos    (20U)\n#define FDCAN_CREL_SUBSTEP_Msk    (0xFUL << FDCAN_CREL_SUBSTEP_Pos)            /*!< 0x00F00000 */\n#define FDCAN_CREL_SUBSTEP        FDCAN_CREL_SUBSTEP_Msk                       /*!<Sub-step of Core release                */\n#define FDCAN_CREL_STEP_Pos       (24U)\n#define FDCAN_CREL_STEP_Msk       (0xFUL << FDCAN_CREL_STEP_Pos)               /*!< 0x0F000000 */\n#define FDCAN_CREL_STEP           FDCAN_CREL_STEP_Msk                          /*!<Step of Core release                    */\n#define FDCAN_CREL_REL_Pos        (28U)\n#define FDCAN_CREL_REL_Msk        (0xFUL << FDCAN_CREL_REL_Pos)                /*!< 0xF0000000 */\n#define FDCAN_CREL_REL            FDCAN_CREL_REL_Msk                           /*!<Core release                            */\n\n/*****************  Bit definition for FDCAN_ENDN register  *******************/\n#define FDCAN_ENDN_ETV_Pos        (0U)\n#define FDCAN_ENDN_ETV_Msk        (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos)         /*!< 0xFFFFFFFF */\n#define FDCAN_ENDN_ETV            FDCAN_ENDN_ETV_Msk                           /*!<Endianness Test Value                   */\n\n/*****************  Bit definition for FDCAN_DBTP register  *******************/\n#define FDCAN_DBTP_DSJW_Pos       (0U)\n#define FDCAN_DBTP_DSJW_Msk       (0xFUL << FDCAN_DBTP_DSJW_Pos)               /*!< 0x0000000F */\n#define FDCAN_DBTP_DSJW           FDCAN_DBTP_DSJW_Msk                          /*!<Synchronization Jump Width              */\n#define FDCAN_DBTP_DTSEG2_Pos     (4U)\n#define FDCAN_DBTP_DTSEG2_Msk     (0xFUL << FDCAN_DBTP_DTSEG2_Pos)             /*!< 0x000000F0 */\n#define FDCAN_DBTP_DTSEG2         FDCAN_DBTP_DTSEG2_Msk                        /*!<Data time segment after sample point    */\n#define FDCAN_DBTP_DTSEG1_Pos     (8U)\n#define FDCAN_DBTP_DTSEG1_Msk     (0x1FUL << FDCAN_DBTP_DTSEG1_Pos)            /*!< 0x00001F00 */\n#define FDCAN_DBTP_DTSEG1         FDCAN_DBTP_DTSEG1_Msk                        /*!<Data time segment before sample point   */\n#define FDCAN_DBTP_DBRP_Pos       (16U)\n#define FDCAN_DBTP_DBRP_Msk       (0x1FUL << FDCAN_DBTP_DBRP_Pos)              /*!< 0x001F0000 */\n#define FDCAN_DBTP_DBRP           FDCAN_DBTP_DBRP_Msk                          /*!<Data BIt Rate Prescaler                 */\n#define FDCAN_DBTP_TDC_Pos        (23U)\n#define FDCAN_DBTP_TDC_Msk        (0x1UL << FDCAN_DBTP_TDC_Pos)                /*!< 0x00800000 */\n#define FDCAN_DBTP_TDC            FDCAN_DBTP_TDC_Msk                           /*!<Transceiver Delay Compensation          */\n\n/*****************  Bit definition for FDCAN_TEST register  *******************/\n#define FDCAN_TEST_LBCK_Pos       (4U)\n#define FDCAN_TEST_LBCK_Msk       (0x1UL << FDCAN_TEST_LBCK_Pos)               /*!< 0x00000010 */\n#define FDCAN_TEST_LBCK           FDCAN_TEST_LBCK_Msk                          /*!<Loop Back mode                           */\n#define FDCAN_TEST_TX_Pos         (5U)\n#define FDCAN_TEST_TX_Msk         (0x3UL << FDCAN_TEST_TX_Pos)                 /*!< 0x00000060 */\n#define FDCAN_TEST_TX             FDCAN_TEST_TX_Msk                            /*!<Control of Transmit Pin                  */\n#define FDCAN_TEST_RX_Pos         (7U)\n#define FDCAN_TEST_RX_Msk         (0x1UL << FDCAN_TEST_RX_Pos)                 /*!< 0x00000080 */\n#define FDCAN_TEST_RX             FDCAN_TEST_RX_Msk                            /*!<Receive Pin                              */\n\n/*****************  Bit definition for FDCAN_RWD register  ********************/\n#define FDCAN_RWD_WDC_Pos         (0U)\n#define FDCAN_RWD_WDC_Msk         (0xFFUL << FDCAN_RWD_WDC_Pos)                /*!< 0x000000FF */\n#define FDCAN_RWD_WDC             FDCAN_RWD_WDC_Msk                            /*!<Watchdog configuration                   */\n#define FDCAN_RWD_WDV_Pos         (8U)\n#define FDCAN_RWD_WDV_Msk         (0xFFUL << FDCAN_RWD_WDV_Pos)                /*!< 0x0000FF00 */\n#define FDCAN_RWD_WDV             FDCAN_RWD_WDV_Msk                            /*!<Watchdog value                           */\n\n/*****************  Bit definition for FDCAN_CCCR register  ********************/\n#define FDCAN_CCCR_INIT_Pos       (0U)\n#define FDCAN_CCCR_INIT_Msk       (0x1UL << FDCAN_CCCR_INIT_Pos)               /*!< 0x00000001 */\n#define FDCAN_CCCR_INIT           FDCAN_CCCR_INIT_Msk                          /*!<Initialization                           */\n#define FDCAN_CCCR_CCE_Pos        (1U)\n#define FDCAN_CCCR_CCE_Msk        (0x1UL << FDCAN_CCCR_CCE_Pos)                /*!< 0x00000002 */\n#define FDCAN_CCCR_CCE            FDCAN_CCCR_CCE_Msk                           /*!<Configuration Change Enable              */\n#define FDCAN_CCCR_ASM_Pos        (2U)\n#define FDCAN_CCCR_ASM_Msk        (0x1UL << FDCAN_CCCR_ASM_Pos)                /*!< 0x00000004 */\n#define FDCAN_CCCR_ASM            FDCAN_CCCR_ASM_Msk                           /*!<ASM Restricted Operation Mode            */\n#define FDCAN_CCCR_CSA_Pos        (3U)\n#define FDCAN_CCCR_CSA_Msk        (0x1UL << FDCAN_CCCR_CSA_Pos)                /*!< 0x00000008 */\n#define FDCAN_CCCR_CSA            FDCAN_CCCR_CSA_Msk                           /*!<Clock Stop Acknowledge                   */\n#define FDCAN_CCCR_CSR_Pos        (4U)\n#define FDCAN_CCCR_CSR_Msk        (0x1UL << FDCAN_CCCR_CSR_Pos)                /*!< 0x00000010 */\n#define FDCAN_CCCR_CSR            FDCAN_CCCR_CSR_Msk                           /*!<Clock Stop Request                       */\n#define FDCAN_CCCR_MON_Pos        (5U)\n#define FDCAN_CCCR_MON_Msk        (0x1UL << FDCAN_CCCR_MON_Pos)                /*!< 0x00000020 */\n#define FDCAN_CCCR_MON            FDCAN_CCCR_MON_Msk                           /*!<Bus Monitoring Mode                      */\n#define FDCAN_CCCR_DAR_Pos        (6U)\n#define FDCAN_CCCR_DAR_Msk        (0x1UL << FDCAN_CCCR_DAR_Pos)                /*!< 0x00000040 */\n#define FDCAN_CCCR_DAR            FDCAN_CCCR_DAR_Msk                           /*!<Disable Automatic Retransmission         */\n#define FDCAN_CCCR_TEST_Pos       (7U)\n#define FDCAN_CCCR_TEST_Msk       (0x1UL << FDCAN_CCCR_TEST_Pos)               /*!< 0x00000080 */\n#define FDCAN_CCCR_TEST           FDCAN_CCCR_TEST_Msk                          /*!<Test Mode Enable                         */\n#define FDCAN_CCCR_FDOE_Pos       (8U)\n#define FDCAN_CCCR_FDOE_Msk       (0x1UL << FDCAN_CCCR_FDOE_Pos)               /*!< 0x00000100 */\n#define FDCAN_CCCR_FDOE           FDCAN_CCCR_FDOE_Msk                          /*!<FD Operation Enable                      */\n#define FDCAN_CCCR_BRSE_Pos       (9U)\n#define FDCAN_CCCR_BRSE_Msk       (0x1UL << FDCAN_CCCR_BRSE_Pos)               /*!< 0x00000200 */\n#define FDCAN_CCCR_BRSE           FDCAN_CCCR_BRSE_Msk                          /*!<FDCAN Bit Rate Switching                 */\n#define FDCAN_CCCR_PXHD_Pos       (12U)\n#define FDCAN_CCCR_PXHD_Msk       (0x1UL << FDCAN_CCCR_PXHD_Pos)               /*!< 0x00001000 */\n#define FDCAN_CCCR_PXHD           FDCAN_CCCR_PXHD_Msk                          /*!<Protocol Exception Handling Disable      */\n#define FDCAN_CCCR_EFBI_Pos       (13U)\n#define FDCAN_CCCR_EFBI_Msk       (0x1UL << FDCAN_CCCR_EFBI_Pos)               /*!< 0x00002000 */\n#define FDCAN_CCCR_EFBI           FDCAN_CCCR_EFBI_Msk                          /*!<Edge Filtering during Bus Integration    */\n#define FDCAN_CCCR_TXP_Pos        (14U)\n#define FDCAN_CCCR_TXP_Msk        (0x1UL << FDCAN_CCCR_TXP_Pos)                /*!< 0x00004000 */\n#define FDCAN_CCCR_TXP            FDCAN_CCCR_TXP_Msk                           /*!<Two CAN bit times Pause                  */\n#define FDCAN_CCCR_NISO_Pos       (15U)\n#define FDCAN_CCCR_NISO_Msk       (0x1UL << FDCAN_CCCR_NISO_Pos)               /*!< 0x00008000 */\n#define FDCAN_CCCR_NISO           FDCAN_CCCR_NISO_Msk                          /*!<Non ISO Operation                        */\n\n/*****************  Bit definition for FDCAN_NBTP register  ********************/\n#define FDCAN_NBTP_NTSEG2_Pos     (0U)\n#define FDCAN_NBTP_NTSEG2_Msk     (0x7FUL << FDCAN_NBTP_NTSEG2_Pos)            /*!< 0x0000007F */\n#define FDCAN_NBTP_NTSEG2         FDCAN_NBTP_NTSEG2_Msk                        /*!<Nominal Time segment after sample point  */\n#define FDCAN_NBTP_NTSEG1_Pos     (8U)\n#define FDCAN_NBTP_NTSEG1_Msk     (0xFFUL << FDCAN_NBTP_NTSEG1_Pos)            /*!< 0x0000FF00 */\n#define FDCAN_NBTP_NTSEG1         FDCAN_NBTP_NTSEG1_Msk                        /*!<Nominal Time segment before sample point */\n#define FDCAN_NBTP_NBRP_Pos       (16U)\n#define FDCAN_NBTP_NBRP_Msk       (0x1FFUL << FDCAN_NBTP_NBRP_Pos)             /*!< 0x01FF0000 */\n#define FDCAN_NBTP_NBRP           FDCAN_NBTP_NBRP_Msk                          /*!<Bit Rate Prescaler                       */\n#define FDCAN_NBTP_NSJW_Pos       (25U)\n#define FDCAN_NBTP_NSJW_Msk       (0x7FUL << FDCAN_NBTP_NSJW_Pos)              /*!< 0xFE000000 */\n#define FDCAN_NBTP_NSJW           FDCAN_NBTP_NSJW_Msk                          /*!<Nominal (Re)Synchronization Jump Width   */\n\n/*****************  Bit definition for FDCAN_TSCC register  ********************/\n#define FDCAN_TSCC_TSS_Pos        (0U)\n#define FDCAN_TSCC_TSS_Msk        (0x3UL << FDCAN_TSCC_TSS_Pos)                /*!< 0x00000003 */\n#define FDCAN_TSCC_TSS            FDCAN_TSCC_TSS_Msk                           /*!<Timestamp Select                         */\n#define FDCAN_TSCC_TCP_Pos        (16U)\n#define FDCAN_TSCC_TCP_Msk        (0xFUL << FDCAN_TSCC_TCP_Pos)                /*!< 0x000F0000 */\n#define FDCAN_TSCC_TCP            FDCAN_TSCC_TCP_Msk                           /*!<Timestamp Counter Prescaler              */\n\n/*****************  Bit definition for FDCAN_TSCV register  ********************/\n#define FDCAN_TSCV_TSC_Pos        (0U)\n#define FDCAN_TSCV_TSC_Msk        (0xFFFFUL << FDCAN_TSCV_TSC_Pos)             /*!< 0x0000FFFF */\n#define FDCAN_TSCV_TSC            FDCAN_TSCV_TSC_Msk                           /*!<Timestamp Counter                        */\n\n/*****************  Bit definition for FDCAN_TOCC register  ********************/\n#define FDCAN_TOCC_ETOC_Pos       (0U)\n#define FDCAN_TOCC_ETOC_Msk       (0x1UL << FDCAN_TOCC_ETOC_Pos)               /*!< 0x00000001 */\n#define FDCAN_TOCC_ETOC           FDCAN_TOCC_ETOC_Msk                          /*!<Enable Timeout Counter                   */\n#define FDCAN_TOCC_TOS_Pos        (1U)\n#define FDCAN_TOCC_TOS_Msk        (0x3UL << FDCAN_TOCC_TOS_Pos)                /*!< 0x00000006 */\n#define FDCAN_TOCC_TOS            FDCAN_TOCC_TOS_Msk                           /*!<Timeout Select                           */\n#define FDCAN_TOCC_TOP_Pos        (16U)\n#define FDCAN_TOCC_TOP_Msk        (0xFFFFUL << FDCAN_TOCC_TOP_Pos)             /*!< 0xFFFF0000 */\n#define FDCAN_TOCC_TOP            FDCAN_TOCC_TOP_Msk                           /*!<Timeout Period                           */\n\n/*****************  Bit definition for FDCAN_TOCV register  ********************/\n#define FDCAN_TOCV_TOC_Pos        (0U)\n#define FDCAN_TOCV_TOC_Msk        (0xFFFFUL << FDCAN_TOCV_TOC_Pos)             /*!< 0x0000FFFF */\n#define FDCAN_TOCV_TOC            FDCAN_TOCV_TOC_Msk                           /*!<Timeout Counter                          */\n\n/*****************  Bit definition for FDCAN_ECR register  *********************/\n#define FDCAN_ECR_TEC_Pos         (0U)\n#define FDCAN_ECR_TEC_Msk         (0xFFUL << FDCAN_ECR_TEC_Pos)                 /*!< 0x000000FF */\n#define FDCAN_ECR_TEC             FDCAN_ECR_TEC_Msk                            /*!<Transmit Error Counter                   */\n#define FDCAN_ECR_REC_Pos         (8U)\n#define FDCAN_ECR_REC_Msk         (0x7FUL << FDCAN_ECR_REC_Pos)                /*!< 0x00007F00 */\n#define FDCAN_ECR_REC             FDCAN_ECR_REC_Msk                            /*!<Receive Error Counter                    */\n#define FDCAN_ECR_RP_Pos          (15U)\n#define FDCAN_ECR_RP_Msk          (0x1UL << FDCAN_ECR_RP_Pos)                  /*!< 0x00008000 */\n#define FDCAN_ECR_RP              FDCAN_ECR_RP_Msk                             /*!<Receive Error Passive                    */\n#define FDCAN_ECR_CEL_Pos         (16U)\n#define FDCAN_ECR_CEL_Msk         (0xFFUL << FDCAN_ECR_CEL_Pos)                /*!< 0x00FF0000 */\n#define FDCAN_ECR_CEL             FDCAN_ECR_CEL_Msk                            /*!<CAN Error Logging                        */\n\n/*****************  Bit definition for FDCAN_PSR register  *********************/\n#define FDCAN_PSR_LEC_Pos         (0U)\n#define FDCAN_PSR_LEC_Msk         (0x7UL << FDCAN_PSR_LEC_Pos)                 /*!< 0x00000007 */\n#define FDCAN_PSR_LEC             FDCAN_PSR_LEC_Msk                            /*!<Last Error Code                          */\n#define FDCAN_PSR_ACT_Pos         (3U)\n#define FDCAN_PSR_ACT_Msk         (0x3UL << FDCAN_PSR_ACT_Pos)                 /*!< 0x00000018 */\n#define FDCAN_PSR_ACT             FDCAN_PSR_ACT_Msk                            /*!<Activity                                 */\n#define FDCAN_PSR_EP_Pos          (5U)\n#define FDCAN_PSR_EP_Msk          (0x1UL << FDCAN_PSR_EP_Pos)                  /*!< 0x00000020 */\n#define FDCAN_PSR_EP              FDCAN_PSR_EP_Msk                             /*!<Error Passive                            */\n#define FDCAN_PSR_EW_Pos          (6U)\n#define FDCAN_PSR_EW_Msk          (0x1UL << FDCAN_PSR_EW_Pos)                  /*!< 0x00000040 */\n#define FDCAN_PSR_EW              FDCAN_PSR_EW_Msk                             /*!<Warning Status                           */\n#define FDCAN_PSR_BO_Pos          (7U)\n#define FDCAN_PSR_BO_Msk          (0x1UL << FDCAN_PSR_BO_Pos)                  /*!< 0x00000080 */\n#define FDCAN_PSR_BO              FDCAN_PSR_BO_Msk                             /*!<Bus_Off Status                           */\n#define FDCAN_PSR_DLEC_Pos        (8U)\n#define FDCAN_PSR_DLEC_Msk        (0x7UL << FDCAN_PSR_DLEC_Pos)                /*!< 0x00000700 */\n#define FDCAN_PSR_DLEC            FDCAN_PSR_DLEC_Msk                           /*!<Data Last Error Code                     */\n#define FDCAN_PSR_RESI_Pos        (11U)\n#define FDCAN_PSR_RESI_Msk        (0x1UL << FDCAN_PSR_RESI_Pos)                /*!< 0x00000800 */\n#define FDCAN_PSR_RESI            FDCAN_PSR_RESI_Msk                           /*!<ESI flag of last received FDCAN Message  */\n#define FDCAN_PSR_RBRS_Pos        (12U)\n#define FDCAN_PSR_RBRS_Msk        (0x1UL << FDCAN_PSR_RBRS_Pos)                /*!< 0x00001000 */\n#define FDCAN_PSR_RBRS            FDCAN_PSR_RBRS_Msk                           /*!<BRS flag of last received FDCAN Message  */\n#define FDCAN_PSR_REDL_Pos        (13U)\n#define FDCAN_PSR_REDL_Msk        (0x1UL << FDCAN_PSR_REDL_Pos)                /*!< 0x00002000 */\n#define FDCAN_PSR_REDL            FDCAN_PSR_REDL_Msk                           /*!<Received FDCAN Message                   */\n#define FDCAN_PSR_PXE_Pos         (14U)\n#define FDCAN_PSR_PXE_Msk         (0x1UL << FDCAN_PSR_PXE_Pos)                 /*!< 0x00004000 */\n#define FDCAN_PSR_PXE             FDCAN_PSR_PXE_Msk                            /*!<Protocol Exception Event                 */\n#define FDCAN_PSR_TDCV_Pos        (16U)\n#define FDCAN_PSR_TDCV_Msk        (0x7FUL << FDCAN_PSR_TDCV_Pos)               /*!< 0x007F0000 */\n#define FDCAN_PSR_TDCV            FDCAN_PSR_TDCV_Msk                           /*!<Transmitter Delay Compensation Value     */\n\n/*****************  Bit definition for FDCAN_TDCR register  ********************/\n#define FDCAN_TDCR_TDCF_Pos       (0U)\n#define FDCAN_TDCR_TDCF_Msk       (0x7FUL << FDCAN_TDCR_TDCF_Pos)              /*!< 0x0000007F */\n#define FDCAN_TDCR_TDCF           FDCAN_TDCR_TDCF_Msk                          /*!<Transmitter Delay Compensation Filter    */\n#define FDCAN_TDCR_TDCO_Pos       (8U)\n#define FDCAN_TDCR_TDCO_Msk       (0x7FUL << FDCAN_TDCR_TDCO_Pos)              /*!< 0x00007F00 */\n#define FDCAN_TDCR_TDCO           FDCAN_TDCR_TDCO_Msk                          /*!<Transmitter Delay Compensation Offset    */\n\n/*****************  Bit definition for FDCAN_IR register  **********************/\n#define FDCAN_IR_RF0N_Pos         (0U)\n#define FDCAN_IR_RF0N_Msk         (0x1UL << FDCAN_IR_RF0N_Pos)                 /*!< 0x00000001 */\n#define FDCAN_IR_RF0N             FDCAN_IR_RF0N_Msk                            /*!<Rx FIFO 0 New Message                    */\n#define FDCAN_IR_RF0W_Pos         (1U)\n#define FDCAN_IR_RF0W_Msk         (0x1UL << FDCAN_IR_RF0W_Pos)                 /*!< 0x00000002 */\n#define FDCAN_IR_RF0W             FDCAN_IR_RF0W_Msk                            /*!<Rx FIFO 0 Watermark Reached              */\n#define FDCAN_IR_RF0F_Pos         (2U)\n#define FDCAN_IR_RF0F_Msk         (0x1UL << FDCAN_IR_RF0F_Pos)                 /*!< 0x00000004 */\n#define FDCAN_IR_RF0F             FDCAN_IR_RF0F_Msk                            /*!<Rx FIFO 0 Full                           */\n#define FDCAN_IR_RF0L_Pos         (3U)\n#define FDCAN_IR_RF0L_Msk         (0x1UL << FDCAN_IR_RF0L_Pos)                 /*!< 0x00000008 */\n#define FDCAN_IR_RF0L             FDCAN_IR_RF0L_Msk                            /*!<Rx FIFO 0 Message Lost                   */\n#define FDCAN_IR_RF1N_Pos         (4U)\n#define FDCAN_IR_RF1N_Msk         (0x1UL << FDCAN_IR_RF1N_Pos)                 /*!< 0x00000010 */\n#define FDCAN_IR_RF1N             FDCAN_IR_RF1N_Msk                            /*!<Rx FIFO 1 New Message                    */\n#define FDCAN_IR_RF1W_Pos         (5U)\n#define FDCAN_IR_RF1W_Msk         (0x1UL << FDCAN_IR_RF1W_Pos)                 /*!< 0x00000020 */\n#define FDCAN_IR_RF1W             FDCAN_IR_RF1W_Msk                            /*!<Rx FIFO 1 Watermark Reached              */\n#define FDCAN_IR_RF1F_Pos         (6U)\n#define FDCAN_IR_RF1F_Msk         (0x1UL << FDCAN_IR_RF1F_Pos)                 /*!< 0x00000040 */\n#define FDCAN_IR_RF1F             FDCAN_IR_RF1F_Msk                            /*!<Rx FIFO 1 Full                           */\n#define FDCAN_IR_RF1L_Pos         (7U)\n#define FDCAN_IR_RF1L_Msk         (0x1UL << FDCAN_IR_RF1L_Pos)                 /*!< 0x00000080 */\n#define FDCAN_IR_RF1L             FDCAN_IR_RF1L_Msk                            /*!<Rx FIFO 1 Message Lost                   */\n#define FDCAN_IR_HPM_Pos          (8U)\n#define FDCAN_IR_HPM_Msk          (0x1UL << FDCAN_IR_HPM_Pos)                  /*!< 0x00000100 */\n#define FDCAN_IR_HPM              FDCAN_IR_HPM_Msk                             /*!<High Priority Message                    */\n#define FDCAN_IR_TC_Pos           (9U)\n#define FDCAN_IR_TC_Msk           (0x1UL << FDCAN_IR_TC_Pos)                   /*!< 0x00000200 */\n#define FDCAN_IR_TC               FDCAN_IR_TC_Msk                              /*!<Transmission Completed                   */\n#define FDCAN_IR_TCF_Pos          (10U)\n#define FDCAN_IR_TCF_Msk          (0x1UL << FDCAN_IR_TCF_Pos)                  /*!< 0x00000400 */\n#define FDCAN_IR_TCF              FDCAN_IR_TCF_Msk                             /*!<Transmission Cancellation Finished       */\n#define FDCAN_IR_TFE_Pos          (11U)\n#define FDCAN_IR_TFE_Msk          (0x1UL << FDCAN_IR_TFE_Pos)                  /*!< 0x00000800 */\n#define FDCAN_IR_TFE              FDCAN_IR_TFE_Msk                             /*!<Tx FIFO Empty                            */\n#define FDCAN_IR_TEFN_Pos         (12U)\n#define FDCAN_IR_TEFN_Msk         (0x1UL << FDCAN_IR_TEFN_Pos)                 /*!< 0x00001000 */\n#define FDCAN_IR_TEFN             FDCAN_IR_TEFN_Msk                            /*!<Tx Event FIFO New Entry                  */\n#define FDCAN_IR_TEFW_Pos         (13U)\n#define FDCAN_IR_TEFW_Msk         (0x1UL << FDCAN_IR_TEFW_Pos)                 /*!< 0x00002000 */\n#define FDCAN_IR_TEFW             FDCAN_IR_TEFW_Msk                            /*!<Tx Event FIFO Watermark Reached          */\n#define FDCAN_IR_TEFF_Pos         (14U)\n#define FDCAN_IR_TEFF_Msk         (0x1UL << FDCAN_IR_TEFF_Pos)                 /*!< 0x00004000 */\n#define FDCAN_IR_TEFF             FDCAN_IR_TEFF_Msk                            /*!<Tx Event FIFO Full                       */\n#define FDCAN_IR_TEFL_Pos         (15U)\n#define FDCAN_IR_TEFL_Msk         (0x1UL << FDCAN_IR_TEFL_Pos)                 /*!< 0x00008000 */\n#define FDCAN_IR_TEFL             FDCAN_IR_TEFL_Msk                            /*!<Tx Event FIFO Element Lost               */\n#define FDCAN_IR_TSW_Pos          (16U)\n#define FDCAN_IR_TSW_Msk          (0x1UL << FDCAN_IR_TSW_Pos)                  /*!< 0x00010000 */\n#define FDCAN_IR_TSW              FDCAN_IR_TSW_Msk                             /*!<Timestamp Wraparound                     */\n#define FDCAN_IR_MRAF_Pos         (17U)\n#define FDCAN_IR_MRAF_Msk         (0x1UL << FDCAN_IR_MRAF_Pos)                 /*!< 0x00020000 */\n#define FDCAN_IR_MRAF             FDCAN_IR_MRAF_Msk                            /*!<Message RAM Access Failure               */\n#define FDCAN_IR_TOO_Pos          (18U)\n#define FDCAN_IR_TOO_Msk          (0x1UL << FDCAN_IR_TOO_Pos)                  /*!< 0x00040000 */\n#define FDCAN_IR_TOO              FDCAN_IR_TOO_Msk                             /*!<Timeout Occurred                         */\n#define FDCAN_IR_DRX_Pos          (19U)\n#define FDCAN_IR_DRX_Msk          (0x1UL << FDCAN_IR_DRX_Pos)                  /*!< 0x00080000 */\n#define FDCAN_IR_DRX              FDCAN_IR_DRX_Msk                             /*!<Message stored to Dedicated Rx Buffer    */\n#define FDCAN_IR_ELO_Pos          (22U)\n#define FDCAN_IR_ELO_Msk          (0x1UL << FDCAN_IR_ELO_Pos)                  /*!< 0x00400000 */\n#define FDCAN_IR_ELO              FDCAN_IR_ELO_Msk                             /*!<Error Logging Overflow                   */\n#define FDCAN_IR_EP_Pos           (23U)\n#define FDCAN_IR_EP_Msk           (0x1UL << FDCAN_IR_EP_Pos)                   /*!< 0x00800000 */\n#define FDCAN_IR_EP               FDCAN_IR_EP_Msk                              /*!<Error Passive                            */\n#define FDCAN_IR_EW_Pos           (24U)\n#define FDCAN_IR_EW_Msk           (0x1UL << FDCAN_IR_EW_Pos)                   /*!< 0x01000000 */\n#define FDCAN_IR_EW               FDCAN_IR_EW_Msk                              /*!<Warning Status                           */\n#define FDCAN_IR_BO_Pos           (25U)\n#define FDCAN_IR_BO_Msk           (0x1UL << FDCAN_IR_BO_Pos)                   /*!< 0x02000000 */\n#define FDCAN_IR_BO               FDCAN_IR_BO_Msk                              /*!<Bus_Off Status                           */\n#define FDCAN_IR_WDI_Pos          (26U)\n#define FDCAN_IR_WDI_Msk          (0x1UL << FDCAN_IR_WDI_Pos)                  /*!< 0x04000000 */\n#define FDCAN_IR_WDI              FDCAN_IR_WDI_Msk                             /*!<Watchdog Interrupt                       */\n#define FDCAN_IR_PEA_Pos          (27U)\n#define FDCAN_IR_PEA_Msk          (0x1UL << FDCAN_IR_PEA_Pos)                  /*!< 0x08000000 */\n#define FDCAN_IR_PEA              FDCAN_IR_PEA_Msk                             /*!<Protocol Error in Arbitration Phase      */\n#define FDCAN_IR_PED_Pos          (28U)\n#define FDCAN_IR_PED_Msk          (0x1UL << FDCAN_IR_PED_Pos)                  /*!< 0x10000000 */\n#define FDCAN_IR_PED              FDCAN_IR_PED_Msk                             /*!<Protocol Error in Data Phase             */\n#define FDCAN_IR_ARA_Pos          (29U)\n#define FDCAN_IR_ARA_Msk          (0x1UL << FDCAN_IR_ARA_Pos)                  /*!< 0x20000000 */\n#define FDCAN_IR_ARA              FDCAN_IR_ARA_Msk                             /*!<Access to Reserved Address               */\n\n/*****************  Bit definition for FDCAN_IE register  **********************/\n#define FDCAN_IE_RF0NE_Pos        (0U)\n#define FDCAN_IE_RF0NE_Msk        (0x1UL << FDCAN_IE_RF0NE_Pos)                /*!< 0x00000001 */\n#define FDCAN_IE_RF0NE            FDCAN_IE_RF0NE_Msk                           /*!<Rx FIFO 0 New Message Enable                 */\n#define FDCAN_IE_RF0WE_Pos        (1U)\n#define FDCAN_IE_RF0WE_Msk        (0x1UL << FDCAN_IE_RF0WE_Pos)                /*!< 0x00000002 */\n#define FDCAN_IE_RF0WE            FDCAN_IE_RF0WE_Msk                           /*!<Rx FIFO 0 Watermark Reached Enable           */\n#define FDCAN_IE_RF0FE_Pos        (2U)\n#define FDCAN_IE_RF0FE_Msk        (0x1UL << FDCAN_IE_RF0FE_Pos)                /*!< 0x00000004 */\n#define FDCAN_IE_RF0FE            FDCAN_IE_RF0FE_Msk                           /*!<Rx FIFO 0 Full Enable                        */\n#define FDCAN_IE_RF0LE_Pos        (3U)\n#define FDCAN_IE_RF0LE_Msk        (0x1UL << FDCAN_IE_RF0LE_Pos)                /*!< 0x00000008 */\n#define FDCAN_IE_RF0LE            FDCAN_IE_RF0LE_Msk                           /*!<Rx FIFO 0 Message Lost Enable                */\n#define FDCAN_IE_RF1NE_Pos        (4U)\n#define FDCAN_IE_RF1NE_Msk        (0x1UL << FDCAN_IE_RF1NE_Pos)                /*!< 0x00000010 */\n#define FDCAN_IE_RF1NE            FDCAN_IE_RF1NE_Msk                           /*!<Rx FIFO 1 New Message Enable                 */\n#define FDCAN_IE_RF1WE_Pos        (5U)\n#define FDCAN_IE_RF1WE_Msk        (0x1UL << FDCAN_IE_RF1WE_Pos)                /*!< 0x00000020 */\n#define FDCAN_IE_RF1WE            FDCAN_IE_RF1WE_Msk                           /*!<Rx FIFO 1 Watermark Reached Enable           */\n#define FDCAN_IE_RF1FE_Pos        (6U)\n#define FDCAN_IE_RF1FE_Msk        (0x1UL << FDCAN_IE_RF1FE_Pos)                /*!< 0x00000040 */\n#define FDCAN_IE_RF1FE            FDCAN_IE_RF1FE_Msk                           /*!<Rx FIFO 1 Full Enable                        */\n#define FDCAN_IE_RF1LE_Pos        (7U)\n#define FDCAN_IE_RF1LE_Msk        (0x1UL << FDCAN_IE_RF1LE_Pos)                /*!< 0x00000080 */\n#define FDCAN_IE_RF1LE            FDCAN_IE_RF1LE_Msk                           /*!<Rx FIFO 1 Message Lost Enable                */\n#define FDCAN_IE_HPME_Pos         (8U)\n#define FDCAN_IE_HPME_Msk         (0x1UL << FDCAN_IE_HPME_Pos)                 /*!< 0x00000100 */\n#define FDCAN_IE_HPME             FDCAN_IE_HPME_Msk                            /*!<High Priority Message Enable                 */\n#define FDCAN_IE_TCE_Pos          (9U)\n#define FDCAN_IE_TCE_Msk          (0x1UL << FDCAN_IE_TCE_Pos)                  /*!< 0x00000200 */\n#define FDCAN_IE_TCE              FDCAN_IE_TCE_Msk                             /*!<Transmission Completed Enable                */\n#define FDCAN_IE_TCFE_Pos         (10U)\n#define FDCAN_IE_TCFE_Msk         (0x1UL << FDCAN_IE_TCFE_Pos)                 /*!< 0x00000400 */\n#define FDCAN_IE_TCFE             FDCAN_IE_TCFE_Msk                            /*!<Transmission Cancellation Finished Enable    */\n#define FDCAN_IE_TFEE_Pos         (11U)\n#define FDCAN_IE_TFEE_Msk         (0x1UL << FDCAN_IE_TFEE_Pos)                 /*!< 0x00000800 */\n#define FDCAN_IE_TFEE             FDCAN_IE_TFEE_Msk                            /*!<Tx FIFO Empty Enable                         */\n#define FDCAN_IE_TEFNE_Pos        (12U)\n#define FDCAN_IE_TEFNE_Msk        (0x1UL << FDCAN_IE_TEFNE_Pos)                /*!< 0x00001000 */\n#define FDCAN_IE_TEFNE            FDCAN_IE_TEFNE_Msk                           /*!<Tx Event FIFO New Entry Enable               */\n#define FDCAN_IE_TEFWE_Pos        (13U)\n#define FDCAN_IE_TEFWE_Msk        (0x1UL << FDCAN_IE_TEFWE_Pos)                /*!< 0x00002000 */\n#define FDCAN_IE_TEFWE            FDCAN_IE_TEFWE_Msk                           /*!<Tx Event FIFO Watermark Reached Enable       */\n#define FDCAN_IE_TEFFE_Pos        (14U)\n#define FDCAN_IE_TEFFE_Msk        (0x1UL << FDCAN_IE_TEFFE_Pos)                /*!< 0x00004000 */\n#define FDCAN_IE_TEFFE            FDCAN_IE_TEFFE_Msk                           /*!<Tx Event FIFO Full Enable                    */\n#define FDCAN_IE_TEFLE_Pos        (15U)\n#define FDCAN_IE_TEFLE_Msk        (0x1UL << FDCAN_IE_TEFLE_Pos)                /*!< 0x00008000 */\n#define FDCAN_IE_TEFLE            FDCAN_IE_TEFLE_Msk                           /*!<Tx Event FIFO Element Lost Enable            */\n#define FDCAN_IE_TSWE_Pos         (16U)\n#define FDCAN_IE_TSWE_Msk         (0x1UL << FDCAN_IE_TSWE_Pos)                 /*!< 0x00010000 */\n#define FDCAN_IE_TSWE             FDCAN_IE_TSWE_Msk                            /*!<Timestamp Wraparound Enable                  */\n#define FDCAN_IE_MRAFE_Pos        (17U)\n#define FDCAN_IE_MRAFE_Msk        (0x1UL << FDCAN_IE_MRAFE_Pos)                /*!< 0x00020000 */\n#define FDCAN_IE_MRAFE            FDCAN_IE_MRAFE_Msk                           /*!<Message RAM Access Failure Enable            */\n#define FDCAN_IE_TOOE_Pos         (18U)\n#define FDCAN_IE_TOOE_Msk         (0x1UL << FDCAN_IE_TOOE_Pos)                 /*!< 0x00040000 */\n#define FDCAN_IE_TOOE             FDCAN_IE_TOOE_Msk                            /*!<Timeout Occurred Enable                      */\n#define FDCAN_IE_DRXE_Pos         (19U)\n#define FDCAN_IE_DRXE_Msk         (0x1UL << FDCAN_IE_DRXE_Pos)                 /*!< 0x00080000 */\n#define FDCAN_IE_DRXE             FDCAN_IE_DRXE_Msk                            /*!<Message stored to Dedicated Rx Buffer Enable */\n#define FDCAN_IE_BECE_Pos         (20U)\n#define FDCAN_IE_BECE_Msk         (0x1UL << FDCAN_IE_BECE_Pos)                 /*!< 0x00100000 */\n#define FDCAN_IE_BECE             FDCAN_IE_BECE_Msk                            /*!<Bit Error Corrected Interrupt Enable         */\n#define FDCAN_IE_BEUE_Pos         (21U)\n#define FDCAN_IE_BEUE_Msk         (0x1UL << FDCAN_IE_BEUE_Pos)                 /*!< 0x00200000 */\n#define FDCAN_IE_BEUE             FDCAN_IE_BEUE_Msk                            /*!<Bit Error Uncorrected Interrupt Enable       */\n#define FDCAN_IE_ELOE_Pos         (22U)\n#define FDCAN_IE_ELOE_Msk         (0x1UL << FDCAN_IE_ELOE_Pos)                 /*!< 0x00400000 */\n#define FDCAN_IE_ELOE             FDCAN_IE_ELOE_Msk                            /*!<Error Logging Overflow Enable                */\n#define FDCAN_IE_EPE_Pos          (23U)\n#define FDCAN_IE_EPE_Msk          (0x1UL << FDCAN_IE_EPE_Pos)                  /*!< 0x00800000 */\n#define FDCAN_IE_EPE              FDCAN_IE_EPE_Msk                             /*!<Error Passive Enable                         */\n#define FDCAN_IE_EWE_Pos          (24U)\n#define FDCAN_IE_EWE_Msk          (0x1UL << FDCAN_IE_EWE_Pos)                  /*!< 0x01000000 */\n#define FDCAN_IE_EWE              FDCAN_IE_EWE_Msk                             /*!<Warning Status Enable                        */\n#define FDCAN_IE_BOE_Pos          (25U)\n#define FDCAN_IE_BOE_Msk          (0x1UL << FDCAN_IE_BOE_Pos)                  /*!< 0x02000000 */\n#define FDCAN_IE_BOE              FDCAN_IE_BOE_Msk                             /*!<Bus_Off Status Enable                        */\n#define FDCAN_IE_WDIE_Pos         (26U)\n#define FDCAN_IE_WDIE_Msk         (0x1UL << FDCAN_IE_WDIE_Pos)                 /*!< 0x04000000 */\n#define FDCAN_IE_WDIE             FDCAN_IE_WDIE_Msk                            /*!<Watchdog Interrupt Enable                    */\n#define FDCAN_IE_PEAE_Pos         (27U)\n#define FDCAN_IE_PEAE_Msk         (0x1UL << FDCAN_IE_PEAE_Pos)                 /*!< 0x08000000 */\n#define FDCAN_IE_PEAE             FDCAN_IE_PEAE_Msk                            /*!<Protocol Error in Arbitration Phase Enable   */\n#define FDCAN_IE_PEDE_Pos         (28U)\n#define FDCAN_IE_PEDE_Msk         (0x1UL << FDCAN_IE_PEDE_Pos)                 /*!< 0x10000000 */\n#define FDCAN_IE_PEDE             FDCAN_IE_PEDE_Msk                            /*!<Protocol Error in Data Phase Enable          */\n#define FDCAN_IE_ARAE_Pos         (29U)\n#define FDCAN_IE_ARAE_Msk         (0x1UL << FDCAN_IE_ARAE_Pos)                 /*!< 0x20000000 */\n#define FDCAN_IE_ARAE             FDCAN_IE_ARAE_Msk                            /*!<Access to Reserved Address Enable            */\n\n/*****************  Bit definition for FDCAN_ILS register  **********************/\n#define FDCAN_ILS_RF0NL_Pos       (0U)\n#define FDCAN_ILS_RF0NL_Msk       (0x1UL << FDCAN_ILS_RF0NL_Pos)               /*!< 0x00000001 */\n#define FDCAN_ILS_RF0NL           FDCAN_ILS_RF0NL_Msk                          /*!<Rx FIFO 0 New Message Line                  */\n#define FDCAN_ILS_RF0WL_Pos       (1U)\n#define FDCAN_ILS_RF0WL_Msk       (0x1UL << FDCAN_ILS_RF0WL_Pos)               /*!< 0x00000002 */\n#define FDCAN_ILS_RF0WL           FDCAN_ILS_RF0WL_Msk                          /*!<Rx FIFO 0 Watermark Reached Line            */\n#define FDCAN_ILS_RF0FL_Pos       (2U)\n#define FDCAN_ILS_RF0FL_Msk       (0x1UL << FDCAN_ILS_RF0FL_Pos)               /*!< 0x00000004 */\n#define FDCAN_ILS_RF0FL           FDCAN_ILS_RF0FL_Msk                          /*!<Rx FIFO 0 Full Line                         */\n#define FDCAN_ILS_RF0LL_Pos       (3U)\n#define FDCAN_ILS_RF0LL_Msk       (0x1UL << FDCAN_ILS_RF0LL_Pos)               /*!< 0x00000008 */\n#define FDCAN_ILS_RF0LL           FDCAN_ILS_RF0LL_Msk                          /*!<Rx FIFO 0 Message Lost Line                 */\n#define FDCAN_ILS_RF1NL_Pos       (4U)\n#define FDCAN_ILS_RF1NL_Msk       (0x1UL << FDCAN_ILS_RF1NL_Pos)               /*!< 0x00000010 */\n#define FDCAN_ILS_RF1NL           FDCAN_ILS_RF1NL_Msk                          /*!<Rx FIFO 1 New Message Line                  */\n#define FDCAN_ILS_RF1WL_Pos       (5U)\n#define FDCAN_ILS_RF1WL_Msk       (0x1UL << FDCAN_ILS_RF1WL_Pos)               /*!< 0x00000020 */\n#define FDCAN_ILS_RF1WL           FDCAN_ILS_RF1WL_Msk                          /*!<Rx FIFO 1 Watermark Reached Line            */\n#define FDCAN_ILS_RF1FL_Pos       (6U)\n#define FDCAN_ILS_RF1FL_Msk       (0x1UL << FDCAN_ILS_RF1FL_Pos)               /*!< 0x00000040 */\n#define FDCAN_ILS_RF1FL           FDCAN_ILS_RF1FL_Msk                          /*!<Rx FIFO 1 Full Line                         */\n#define FDCAN_ILS_RF1LL_Pos       (7U)\n#define FDCAN_ILS_RF1LL_Msk       (0x1UL << FDCAN_ILS_RF1LL_Pos)               /*!< 0x00000080 */\n#define FDCAN_ILS_RF1LL           FDCAN_ILS_RF1LL_Msk                          /*!<Rx FIFO 1 Message Lost Line                 */\n#define FDCAN_ILS_HPML_Pos        (8U)\n#define FDCAN_ILS_HPML_Msk        (0x1UL << FDCAN_ILS_HPML_Pos)                /*!< 0x00000100 */\n#define FDCAN_ILS_HPML            FDCAN_ILS_HPML_Msk                           /*!<High Priority Message Line                  */\n#define FDCAN_ILS_TCL_Pos         (9U)\n#define FDCAN_ILS_TCL_Msk         (0x1UL << FDCAN_ILS_TCL_Pos)                 /*!< 0x00000200 */\n#define FDCAN_ILS_TCL             FDCAN_ILS_TCL_Msk                            /*!<Transmission Completed Line                 */\n#define FDCAN_ILS_TCFL_Pos        (10U)\n#define FDCAN_ILS_TCFL_Msk        (0x1UL << FDCAN_ILS_TCFL_Pos)                /*!< 0x00000400 */\n#define FDCAN_ILS_TCFL            FDCAN_ILS_TCFL_Msk                           /*!<Transmission Cancellation Finished Line     */\n#define FDCAN_ILS_TFEL_Pos        (11U)\n#define FDCAN_ILS_TFEL_Msk        (0x1UL << FDCAN_ILS_TFEL_Pos)                /*!< 0x00000800 */\n#define FDCAN_ILS_TFEL            FDCAN_ILS_TFEL_Msk                           /*!<Tx FIFO Empty Line                          */\n#define FDCAN_ILS_TEFNL_Pos       (12U)\n#define FDCAN_ILS_TEFNL_Msk       (0x1UL << FDCAN_ILS_TEFNL_Pos)               /*!< 0x00001000 */\n#define FDCAN_ILS_TEFNL           FDCAN_ILS_TEFNL_Msk                          /*!<Tx Event FIFO New Entry Line                */\n#define FDCAN_ILS_TEFWL_Pos       (13U)\n#define FDCAN_ILS_TEFWL_Msk       (0x1UL << FDCAN_ILS_TEFWL_Pos)               /*!< 0x00002000 */\n#define FDCAN_ILS_TEFWL           FDCAN_ILS_TEFWL_Msk                          /*!<Tx Event FIFO Watermark Reached Line        */\n#define FDCAN_ILS_TEFFL_Pos       (14U)\n#define FDCAN_ILS_TEFFL_Msk       (0x1UL << FDCAN_ILS_TEFFL_Pos)               /*!< 0x00004000 */\n#define FDCAN_ILS_TEFFL           FDCAN_ILS_TEFFL_Msk                          /*!<Tx Event FIFO Full Line                     */\n#define FDCAN_ILS_TEFLL_Pos       (15U)\n#define FDCAN_ILS_TEFLL_Msk       (0x1UL << FDCAN_ILS_TEFLL_Pos)               /*!< 0x00008000 */\n#define FDCAN_ILS_TEFLL           FDCAN_ILS_TEFLL_Msk                          /*!<Tx Event FIFO Element Lost Line             */\n#define FDCAN_ILS_TSWL_Pos        (16U)\n#define FDCAN_ILS_TSWL_Msk        (0x1UL << FDCAN_ILS_TSWL_Pos)                /*!< 0x00010000 */\n#define FDCAN_ILS_TSWL            FDCAN_ILS_TSWL_Msk                           /*!<Timestamp Wraparound Line                   */\n#define FDCAN_ILS_MRAFE_Pos       (17U)\n#define FDCAN_ILS_MRAFE_Msk       (0x1UL << FDCAN_ILS_MRAFE_Pos)               /*!< 0x00020000 */\n#define FDCAN_ILS_MRAFE           FDCAN_ILS_MRAFE_Msk                          /*!<Message RAM Access Failure Line             */\n#define FDCAN_ILS_TOOE_Pos        (18U)\n#define FDCAN_ILS_TOOE_Msk        (0x1UL << FDCAN_ILS_TOOE_Pos)                /*!< 0x00040000 */\n#define FDCAN_ILS_TOOE            FDCAN_ILS_TOOE_Msk                           /*!<Timeout Occurred Line                       */\n#define FDCAN_ILS_DRXE_Pos        (19U)\n#define FDCAN_ILS_DRXE_Msk        (0x1UL << FDCAN_ILS_DRXE_Pos)                /*!< 0x00080000 */\n#define FDCAN_ILS_DRXE            FDCAN_ILS_DRXE_Msk                           /*!<Message stored to Dedicated Rx Buffer Line  */\n#define FDCAN_ILS_BECE_Pos        (20U)\n#define FDCAN_ILS_BECE_Msk        (0x1UL << FDCAN_ILS_BECE_Pos)                /*!< 0x00100000 */\n#define FDCAN_ILS_BECE            FDCAN_ILS_BECE_Msk                           /*!<Bit Error Corrected Interrupt Line          */\n#define FDCAN_ILS_BEUE_Pos        (21U)\n#define FDCAN_ILS_BEUE_Msk        (0x1UL << FDCAN_ILS_BEUE_Pos)                /*!< 0x00200000 */\n#define FDCAN_ILS_BEUE            FDCAN_ILS_BEUE_Msk                           /*!<Bit Error Uncorrected Interrupt Line        */\n#define FDCAN_ILS_ELOE_Pos        (22U)\n#define FDCAN_ILS_ELOE_Msk        (0x1UL << FDCAN_ILS_ELOE_Pos)                /*!< 0x00400000 */\n#define FDCAN_ILS_ELOE            FDCAN_ILS_ELOE_Msk                           /*!<Error Logging Overflow Line                 */\n#define FDCAN_ILS_EPE_Pos         (23U)\n#define FDCAN_ILS_EPE_Msk         (0x1UL << FDCAN_ILS_EPE_Pos)                 /*!< 0x00800000 */\n#define FDCAN_ILS_EPE             FDCAN_ILS_EPE_Msk                            /*!<Error Passive Line                          */\n#define FDCAN_ILS_EWE_Pos         (24U)\n#define FDCAN_ILS_EWE_Msk         (0x1UL << FDCAN_ILS_EWE_Pos)                 /*!< 0x01000000 */\n#define FDCAN_ILS_EWE             FDCAN_ILS_EWE_Msk                            /*!<Warning Status Line                         */\n#define FDCAN_ILS_BOE_Pos         (25U)\n#define FDCAN_ILS_BOE_Msk         (0x1UL << FDCAN_ILS_BOE_Pos)                 /*!< 0x02000000 */\n#define FDCAN_ILS_BOE             FDCAN_ILS_BOE_Msk                            /*!<Bus_Off Status Line                         */\n#define FDCAN_ILS_WDIE_Pos        (26U)\n#define FDCAN_ILS_WDIE_Msk        (0x1UL << FDCAN_ILS_WDIE_Pos)                /*!< 0x04000000 */\n#define FDCAN_ILS_WDIE            FDCAN_ILS_WDIE_Msk                           /*!<Watchdog Interrupt Line                     */\n#define FDCAN_ILS_PEAE_Pos        (27U)\n#define FDCAN_ILS_PEAE_Msk        (0x1UL << FDCAN_ILS_PEAE_Pos)                /*!< 0x08000000 */\n#define FDCAN_ILS_PEAE            FDCAN_ILS_PEAE_Msk                           /*!<Protocol Error in Arbitration Phase Line    */\n#define FDCAN_ILS_PEDE_Pos        (28U)\n#define FDCAN_ILS_PEDE_Msk        (0x1UL << FDCAN_ILS_PEDE_Pos)                /*!< 0x10000000 */\n#define FDCAN_ILS_PEDE            FDCAN_ILS_PEDE_Msk                           /*!<Protocol Error in Data Phase Line           */\n#define FDCAN_ILS_ARAE_Pos        (29U)\n#define FDCAN_ILS_ARAE_Msk        (0x1UL << FDCAN_ILS_ARAE_Pos)                /*!< 0x20000000 */\n#define FDCAN_ILS_ARAE            FDCAN_ILS_ARAE_Msk                           /*!<Access to Reserved Address Line             */\n\n/*****************  Bit definition for FDCAN_ILE register  **********************/\n#define FDCAN_ILE_EINT0_Pos       (0U)\n#define FDCAN_ILE_EINT0_Msk       (0x1UL << FDCAN_ILE_EINT0_Pos)               /*!< 0x00000001 */\n#define FDCAN_ILE_EINT0           FDCAN_ILE_EINT0_Msk                          /*!<Enable Interrupt Line 0                   */\n#define FDCAN_ILE_EINT1_Pos       (1U)\n#define FDCAN_ILE_EINT1_Msk       (0x1UL << FDCAN_ILE_EINT1_Pos)               /*!< 0x00000002 */\n#define FDCAN_ILE_EINT1           FDCAN_ILE_EINT1_Msk                          /*!<Enable Interrupt Line 1                   */\n\n/*****************  Bit definition for FDCAN_GFC register  **********************/\n#define FDCAN_GFC_RRFE_Pos        (0U)\n#define FDCAN_GFC_RRFE_Msk        (0x1UL << FDCAN_GFC_RRFE_Pos)                /*!< 0x00000001 */\n#define FDCAN_GFC_RRFE            FDCAN_GFC_RRFE_Msk                           /*!<Reject Remote Frames Extended             */\n#define FDCAN_GFC_RRFS_Pos        (1U)\n#define FDCAN_GFC_RRFS_Msk        (0x1UL << FDCAN_GFC_RRFS_Pos)                /*!< 0x00000002 */\n#define FDCAN_GFC_RRFS            FDCAN_GFC_RRFS_Msk                           /*!<Reject Remote Frames Standard             */\n#define FDCAN_GFC_ANFE_Pos        (2U)\n#define FDCAN_GFC_ANFE_Msk        (0x3UL << FDCAN_GFC_ANFE_Pos)                /*!< 0x0000000C */\n#define FDCAN_GFC_ANFE            FDCAN_GFC_ANFE_Msk                           /*!<Accept Non-matching Frames Extended       */\n#define FDCAN_GFC_ANFS_Pos        (4U)\n#define FDCAN_GFC_ANFS_Msk        (0x3UL << FDCAN_GFC_ANFS_Pos)                /*!< 0x00000030 */\n#define FDCAN_GFC_ANFS            FDCAN_GFC_ANFS_Msk                           /*!<Accept Non-matching Frames Standard       */\n\n/*****************  Bit definition for FDCAN_SIDFC register  ********************/\n#define FDCAN_SIDFC_FLSSA_Pos     (2U)\n#define FDCAN_SIDFC_FLSSA_Msk     (0x3FFFUL << FDCAN_SIDFC_FLSSA_Pos)          /*!< 0x0000FFFC */\n#define FDCAN_SIDFC_FLSSA         FDCAN_SIDFC_FLSSA_Msk                        /*!<Filter List Standard Start Address        */\n#define FDCAN_SIDFC_LSS_Pos       (16U)\n#define FDCAN_SIDFC_LSS_Msk       (0xFFUL << FDCAN_SIDFC_LSS_Pos)              /*!< 0x00FF0000 */\n#define FDCAN_SIDFC_LSS           FDCAN_SIDFC_LSS_Msk                          /*!<List Size Standard                        */\n\n/*****************  Bit definition for FDCAN_XIDFC register  ********************/\n#define FDCAN_XIDFC_FLESA_Pos     (2U)\n#define FDCAN_XIDFC_FLESA_Msk     (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos)          /*!< 0x0000FFFC */\n#define FDCAN_XIDFC_FLESA         FDCAN_XIDFC_FLESA_Msk                        /*!<Filter List Standard Start Address        */\n#define FDCAN_XIDFC_LSE_Pos       (16U)\n#define FDCAN_XIDFC_LSE_Msk       (0x7FUL << FDCAN_XIDFC_LSE_Pos)              /*!< 0x007F0000 */\n#define FDCAN_XIDFC_LSE           FDCAN_XIDFC_LSE_Msk                          /*!<List Size Extended                        */\n\n/*****************  Bit definition for FDCAN_XIDAM register  ********************/\n#define FDCAN_XIDAM_EIDM_Pos      (0U)\n#define FDCAN_XIDAM_EIDM_Msk      (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos)       /*!< 0x1FFFFFFF */\n#define FDCAN_XIDAM_EIDM          FDCAN_XIDAM_EIDM_Msk                         /*!<Extended ID Mask                          */\n\n/*****************  Bit definition for FDCAN_HPMS register  *********************/\n#define FDCAN_HPMS_BIDX_Pos       (0U)\n#define FDCAN_HPMS_BIDX_Msk       (0x3FUL << FDCAN_HPMS_BIDX_Pos)              /*!< 0x0000003F */\n#define FDCAN_HPMS_BIDX           FDCAN_HPMS_BIDX_Msk                          /*!<Buffer Index                              */\n#define FDCAN_HPMS_MSI_Pos        (6U)\n#define FDCAN_HPMS_MSI_Msk        (0x3UL << FDCAN_HPMS_MSI_Pos)                /*!< 0x000000C0 */\n#define FDCAN_HPMS_MSI            FDCAN_HPMS_MSI_Msk                           /*!<Message Storage Indicator                 */\n#define FDCAN_HPMS_FIDX_Pos       (8U)\n#define FDCAN_HPMS_FIDX_Msk       (0x7FUL << FDCAN_HPMS_FIDX_Pos)              /*!< 0x00007F00 */\n#define FDCAN_HPMS_FIDX           FDCAN_HPMS_FIDX_Msk                          /*!<Filter Index                              */\n#define FDCAN_HPMS_FLST_Pos       (15U)\n#define FDCAN_HPMS_FLST_Msk       (0x1UL << FDCAN_HPMS_FLST_Pos)               /*!< 0x00008000 */\n#define FDCAN_HPMS_FLST           FDCAN_HPMS_FLST_Msk                          /*!<Filter List                               */\n\n/*****************  Bit definition for FDCAN_NDAT1 register  ********************/\n#define FDCAN_NDAT1_ND0_Pos       (0U)\n#define FDCAN_NDAT1_ND0_Msk       (0x1UL << FDCAN_NDAT1_ND0_Pos)               /*!< 0x00000001 */\n#define FDCAN_NDAT1_ND0           FDCAN_NDAT1_ND0_Msk                          /*!<New Data flag of Rx Buffer 0              */\n#define FDCAN_NDAT1_ND1_Pos       (1U)\n#define FDCAN_NDAT1_ND1_Msk       (0x1UL << FDCAN_NDAT1_ND1_Pos)               /*!< 0x00000002 */\n#define FDCAN_NDAT1_ND1           FDCAN_NDAT1_ND1_Msk                          /*!<New Data flag of Rx Buffer 1              */\n#define FDCAN_NDAT1_ND2_Pos       (2U)\n#define FDCAN_NDAT1_ND2_Msk       (0x1UL << FDCAN_NDAT1_ND2_Pos)               /*!< 0x00000004 */\n#define FDCAN_NDAT1_ND2           FDCAN_NDAT1_ND2_Msk                          /*!<New Data flag of Rx Buffer 2              */\n#define FDCAN_NDAT1_ND3_Pos       (3U)\n#define FDCAN_NDAT1_ND3_Msk       (0x1UL << FDCAN_NDAT1_ND3_Pos)               /*!< 0x00000008 */\n#define FDCAN_NDAT1_ND3           FDCAN_NDAT1_ND3_Msk                          /*!<New Data flag of Rx Buffer 3              */\n#define FDCAN_NDAT1_ND4_Pos       (4U)\n#define FDCAN_NDAT1_ND4_Msk       (0x1UL << FDCAN_NDAT1_ND4_Pos)               /*!< 0x00000010 */\n#define FDCAN_NDAT1_ND4           FDCAN_NDAT1_ND4_Msk                          /*!<New Data flag of Rx Buffer 4              */\n#define FDCAN_NDAT1_ND5_Pos       (5U)\n#define FDCAN_NDAT1_ND5_Msk       (0x1UL << FDCAN_NDAT1_ND5_Pos)               /*!< 0x00000020 */\n#define FDCAN_NDAT1_ND5           FDCAN_NDAT1_ND5_Msk                          /*!<New Data flag of Rx Buffer 5              */\n#define FDCAN_NDAT1_ND6_Pos       (6U)\n#define FDCAN_NDAT1_ND6_Msk       (0x1UL << FDCAN_NDAT1_ND6_Pos)               /*!< 0x00000040 */\n#define FDCAN_NDAT1_ND6           FDCAN_NDAT1_ND6_Msk                          /*!<New Data flag of Rx Buffer 6              */\n#define FDCAN_NDAT1_ND7_Pos       (7U)\n#define FDCAN_NDAT1_ND7_Msk       (0x1UL << FDCAN_NDAT1_ND7_Pos)               /*!< 0x00000080 */\n#define FDCAN_NDAT1_ND7           FDCAN_NDAT1_ND7_Msk                          /*!<New Data flag of Rx Buffer 7              */\n#define FDCAN_NDAT1_ND8_Pos       (8U)\n#define FDCAN_NDAT1_ND8_Msk       (0x1UL << FDCAN_NDAT1_ND8_Pos)               /*!< 0x00000100 */\n#define FDCAN_NDAT1_ND8           FDCAN_NDAT1_ND8_Msk                          /*!<New Data flag of Rx Buffer 8              */\n#define FDCAN_NDAT1_ND9_Pos       (9U)\n#define FDCAN_NDAT1_ND9_Msk       (0x1UL << FDCAN_NDAT1_ND9_Pos)               /*!< 0x00000200 */\n#define FDCAN_NDAT1_ND9           FDCAN_NDAT1_ND9_Msk                          /*!<New Data flag of Rx Buffer 9              */\n#define FDCAN_NDAT1_ND10_Pos      (10U)\n#define FDCAN_NDAT1_ND10_Msk      (0x1UL << FDCAN_NDAT1_ND10_Pos)              /*!< 0x00000400 */\n#define FDCAN_NDAT1_ND10          FDCAN_NDAT1_ND10_Msk                         /*!<New Data flag of Rx Buffer 10             */\n#define FDCAN_NDAT1_ND11_Pos      (11U)\n#define FDCAN_NDAT1_ND11_Msk      (0x1UL << FDCAN_NDAT1_ND11_Pos)              /*!< 0x00000800 */\n#define FDCAN_NDAT1_ND11          FDCAN_NDAT1_ND11_Msk                         /*!<New Data flag of Rx Buffer 11             */\n#define FDCAN_NDAT1_ND12_Pos      (12U)\n#define FDCAN_NDAT1_ND12_Msk      (0x1UL << FDCAN_NDAT1_ND12_Pos)              /*!< 0x00001000 */\n#define FDCAN_NDAT1_ND12          FDCAN_NDAT1_ND12_Msk                         /*!<New Data flag of Rx Buffer 12             */\n#define FDCAN_NDAT1_ND13_Pos      (13U)\n#define FDCAN_NDAT1_ND13_Msk      (0x1UL << FDCAN_NDAT1_ND13_Pos)              /*!< 0x00002000 */\n#define FDCAN_NDAT1_ND13          FDCAN_NDAT1_ND13_Msk                         /*!<New Data flag of Rx Buffer 13             */\n#define FDCAN_NDAT1_ND14_Pos      (14U)\n#define FDCAN_NDAT1_ND14_Msk      (0x1UL << FDCAN_NDAT1_ND14_Pos)              /*!< 0x00004000 */\n#define FDCAN_NDAT1_ND14          FDCAN_NDAT1_ND14_Msk                         /*!<New Data flag of Rx Buffer 14             */\n#define FDCAN_NDAT1_ND15_Pos      (15U)\n#define FDCAN_NDAT1_ND15_Msk      (0x1UL << FDCAN_NDAT1_ND15_Pos)              /*!< 0x00008000 */\n#define FDCAN_NDAT1_ND15          FDCAN_NDAT1_ND15_Msk                         /*!<New Data flag of Rx Buffer 15             */\n#define FDCAN_NDAT1_ND16_Pos      (16U)\n#define FDCAN_NDAT1_ND16_Msk      (0x1UL << FDCAN_NDAT1_ND16_Pos)              /*!< 0x00010000 */\n#define FDCAN_NDAT1_ND16          FDCAN_NDAT1_ND16_Msk                         /*!<New Data flag of Rx Buffer 16             */\n#define FDCAN_NDAT1_ND17_Pos      (17U)\n#define FDCAN_NDAT1_ND17_Msk      (0x1UL << FDCAN_NDAT1_ND17_Pos)              /*!< 0x00020000 */\n#define FDCAN_NDAT1_ND17          FDCAN_NDAT1_ND17_Msk                         /*!<New Data flag of Rx Buffer 17             */\n#define FDCAN_NDAT1_ND18_Pos      (18U)\n#define FDCAN_NDAT1_ND18_Msk      (0x1UL << FDCAN_NDAT1_ND18_Pos)              /*!< 0x00040000 */\n#define FDCAN_NDAT1_ND18          FDCAN_NDAT1_ND18_Msk                         /*!<New Data flag of Rx Buffer 18             */\n#define FDCAN_NDAT1_ND19_Pos      (19U)\n#define FDCAN_NDAT1_ND19_Msk      (0x1UL << FDCAN_NDAT1_ND19_Pos)              /*!< 0x00080000 */\n#define FDCAN_NDAT1_ND19          FDCAN_NDAT1_ND19_Msk                         /*!<New Data flag of Rx Buffer 19             */\n#define FDCAN_NDAT1_ND20_Pos      (20U)\n#define FDCAN_NDAT1_ND20_Msk      (0x1UL << FDCAN_NDAT1_ND20_Pos)              /*!< 0x00100000 */\n#define FDCAN_NDAT1_ND20          FDCAN_NDAT1_ND20_Msk                         /*!<New Data flag of Rx Buffer 20             */\n#define FDCAN_NDAT1_ND21_Pos      (21U)\n#define FDCAN_NDAT1_ND21_Msk      (0x1UL << FDCAN_NDAT1_ND21_Pos)              /*!< 0x00200000 */\n#define FDCAN_NDAT1_ND21          FDCAN_NDAT1_ND21_Msk                         /*!<New Data flag of Rx Buffer 21             */\n#define FDCAN_NDAT1_ND22_Pos      (22U)\n#define FDCAN_NDAT1_ND22_Msk      (0x1UL << FDCAN_NDAT1_ND22_Pos)              /*!< 0x00400000 */\n#define FDCAN_NDAT1_ND22          FDCAN_NDAT1_ND22_Msk                         /*!<New Data flag of Rx Buffer 22             */\n#define FDCAN_NDAT1_ND23_Pos      (23U)\n#define FDCAN_NDAT1_ND23_Msk      (0x1UL << FDCAN_NDAT1_ND23_Pos)              /*!< 0x00800000 */\n#define FDCAN_NDAT1_ND23          FDCAN_NDAT1_ND23_Msk                         /*!<New Data flag of Rx Buffer 23             */\n#define FDCAN_NDAT1_ND24_Pos      (24U)\n#define FDCAN_NDAT1_ND24_Msk      (0x1UL << FDCAN_NDAT1_ND24_Pos)              /*!< 0x01000000 */\n#define FDCAN_NDAT1_ND24          FDCAN_NDAT1_ND24_Msk                         /*!<New Data flag of Rx Buffer 24             */\n#define FDCAN_NDAT1_ND25_Pos      (25U)\n#define FDCAN_NDAT1_ND25_Msk      (0x1UL << FDCAN_NDAT1_ND25_Pos)              /*!< 0x02000000 */\n#define FDCAN_NDAT1_ND25          FDCAN_NDAT1_ND25_Msk                         /*!<New Data flag of Rx Buffer 25             */\n#define FDCAN_NDAT1_ND26_Pos      (26U)\n#define FDCAN_NDAT1_ND26_Msk      (0x1UL << FDCAN_NDAT1_ND26_Pos)              /*!< 0x04000000 */\n#define FDCAN_NDAT1_ND26          FDCAN_NDAT1_ND26_Msk                         /*!<New Data flag of Rx Buffer 26             */\n#define FDCAN_NDAT1_ND27_Pos      (27U)\n#define FDCAN_NDAT1_ND27_Msk      (0x1UL << FDCAN_NDAT1_ND27_Pos)              /*!< 0x08000000 */\n#define FDCAN_NDAT1_ND27          FDCAN_NDAT1_ND27_Msk                         /*!<New Data flag of Rx Buffer 27             */\n#define FDCAN_NDAT1_ND28_Pos      (28U)\n#define FDCAN_NDAT1_ND28_Msk      (0x1UL << FDCAN_NDAT1_ND28_Pos)              /*!< 0x10000000 */\n#define FDCAN_NDAT1_ND28          FDCAN_NDAT1_ND28_Msk                         /*!<New Data flag of Rx Buffer 28             */\n#define FDCAN_NDAT1_ND29_Pos      (29U)\n#define FDCAN_NDAT1_ND29_Msk      (0x1UL << FDCAN_NDAT1_ND29_Pos)              /*!< 0x20000000 */\n#define FDCAN_NDAT1_ND29          FDCAN_NDAT1_ND29_Msk                         /*!<New Data flag of Rx Buffer 29             */\n#define FDCAN_NDAT1_ND30_Pos      (30U)\n#define FDCAN_NDAT1_ND30_Msk      (0x1UL << FDCAN_NDAT1_ND30_Pos)              /*!< 0x40000000 */\n#define FDCAN_NDAT1_ND30          FDCAN_NDAT1_ND30_Msk                         /*!<New Data flag of Rx Buffer 30             */\n#define FDCAN_NDAT1_ND31_Pos      (31U)\n#define FDCAN_NDAT1_ND31_Msk      (0x1UL << FDCAN_NDAT1_ND31_Pos)              /*!< 0x80000000 */\n#define FDCAN_NDAT1_ND31          FDCAN_NDAT1_ND31_Msk                         /*!<New Data flag of Rx Buffer 31             */\n\n/*****************  Bit definition for FDCAN_NDAT2 register  ********************/\n#define FDCAN_NDAT2_ND32_Pos      (0U)\n#define FDCAN_NDAT2_ND32_Msk      (0x1UL << FDCAN_NDAT2_ND32_Pos)              /*!< 0x00000001 */\n#define FDCAN_NDAT2_ND32          FDCAN_NDAT2_ND32_Msk                         /*!<New Data flag of Rx Buffer 32             */\n#define FDCAN_NDAT2_ND33_Pos      (1U)\n#define FDCAN_NDAT2_ND33_Msk      (0x1UL << FDCAN_NDAT2_ND33_Pos)              /*!< 0x00000002 */\n#define FDCAN_NDAT2_ND33          FDCAN_NDAT2_ND33_Msk                         /*!<New Data flag of Rx Buffer 33             */\n#define FDCAN_NDAT2_ND34_Pos      (2U)\n#define FDCAN_NDAT2_ND34_Msk      (0x1UL << FDCAN_NDAT2_ND34_Pos)              /*!< 0x00000004 */\n#define FDCAN_NDAT2_ND34          FDCAN_NDAT2_ND34_Msk                         /*!<New Data flag of Rx Buffer 34             */\n#define FDCAN_NDAT2_ND35_Pos      (3U)\n#define FDCAN_NDAT2_ND35_Msk      (0x1UL << FDCAN_NDAT2_ND35_Pos)              /*!< 0x00000008 */\n#define FDCAN_NDAT2_ND35          FDCAN_NDAT2_ND35_Msk                         /*!<New Data flag of Rx Buffer 35             */\n#define FDCAN_NDAT2_ND36_Pos      (4U)\n#define FDCAN_NDAT2_ND36_Msk      (0x1UL << FDCAN_NDAT2_ND36_Pos)              /*!< 0x00000010 */\n#define FDCAN_NDAT2_ND36          FDCAN_NDAT2_ND36_Msk                         /*!<New Data flag of Rx Buffer 36             */\n#define FDCAN_NDAT2_ND37_Pos      (5U)\n#define FDCAN_NDAT2_ND37_Msk      (0x1UL << FDCAN_NDAT2_ND37_Pos)              /*!< 0x00000020 */\n#define FDCAN_NDAT2_ND37          FDCAN_NDAT2_ND37_Msk                         /*!<New Data flag of Rx Buffer 37             */\n#define FDCAN_NDAT2_ND38_Pos      (6U)\n#define FDCAN_NDAT2_ND38_Msk      (0x1UL << FDCAN_NDAT2_ND38_Pos)              /*!< 0x00000040 */\n#define FDCAN_NDAT2_ND38          FDCAN_NDAT2_ND38_Msk                         /*!<New Data flag of Rx Buffer 38             */\n#define FDCAN_NDAT2_ND39_Pos      (7U)\n#define FDCAN_NDAT2_ND39_Msk      (0x1UL << FDCAN_NDAT2_ND39_Pos)              /*!< 0x00000080 */\n#define FDCAN_NDAT2_ND39          FDCAN_NDAT2_ND39_Msk                         /*!<New Data flag of Rx Buffer 39             */\n#define FDCAN_NDAT2_ND40_Pos      (8U)\n#define FDCAN_NDAT2_ND40_Msk      (0x1UL << FDCAN_NDAT2_ND40_Pos)              /*!< 0x00000100 */\n#define FDCAN_NDAT2_ND40          FDCAN_NDAT2_ND40_Msk                         /*!<New Data flag of Rx Buffer 40             */\n#define FDCAN_NDAT2_ND41_Pos      (9U)\n#define FDCAN_NDAT2_ND41_Msk      (0x1UL << FDCAN_NDAT2_ND41_Pos)              /*!< 0x00000200 */\n#define FDCAN_NDAT2_ND41          FDCAN_NDAT2_ND41_Msk                         /*!<New Data flag of Rx Buffer 41             */\n#define FDCAN_NDAT2_ND42_Pos      (10U)\n#define FDCAN_NDAT2_ND42_Msk      (0x1UL << FDCAN_NDAT2_ND42_Pos)              /*!< 0x00000400 */\n#define FDCAN_NDAT2_ND42          FDCAN_NDAT2_ND42_Msk                         /*!<New Data flag of Rx Buffer 42             */\n#define FDCAN_NDAT2_ND43_Pos      (11U)\n#define FDCAN_NDAT2_ND43_Msk      (0x1UL << FDCAN_NDAT2_ND43_Pos)              /*!< 0x00000800 */\n#define FDCAN_NDAT2_ND43          FDCAN_NDAT2_ND43_Msk                         /*!<New Data flag of Rx Buffer 43             */\n#define FDCAN_NDAT2_ND44_Pos      (12U)\n#define FDCAN_NDAT2_ND44_Msk      (0x1UL << FDCAN_NDAT2_ND44_Pos)              /*!< 0x00001000 */\n#define FDCAN_NDAT2_ND44          FDCAN_NDAT2_ND44_Msk                         /*!<New Data flag of Rx Buffer 44             */\n#define FDCAN_NDAT2_ND45_Pos      (13U)\n#define FDCAN_NDAT2_ND45_Msk      (0x1UL << FDCAN_NDAT2_ND45_Pos)              /*!< 0x00002000 */\n#define FDCAN_NDAT2_ND45          FDCAN_NDAT2_ND45_Msk                         /*!<New Data flag of Rx Buffer 45             */\n#define FDCAN_NDAT2_ND46_Pos      (14U)\n#define FDCAN_NDAT2_ND46_Msk      (0x1UL << FDCAN_NDAT2_ND46_Pos)              /*!< 0x00004000 */\n#define FDCAN_NDAT2_ND46          FDCAN_NDAT2_ND46_Msk                         /*!<New Data flag of Rx Buffer 46             */\n#define FDCAN_NDAT2_ND47_Pos      (15U)\n#define FDCAN_NDAT2_ND47_Msk      (0x1UL << FDCAN_NDAT2_ND47_Pos)              /*!< 0x00008000 */\n#define FDCAN_NDAT2_ND47          FDCAN_NDAT2_ND47_Msk                         /*!<New Data flag of Rx Buffer 47             */\n#define FDCAN_NDAT2_ND48_Pos      (16U)\n#define FDCAN_NDAT2_ND48_Msk      (0x1UL << FDCAN_NDAT2_ND48_Pos)              /*!< 0x00010000 */\n#define FDCAN_NDAT2_ND48          FDCAN_NDAT2_ND48_Msk                         /*!<New Data flag of Rx Buffer 48             */\n#define FDCAN_NDAT2_ND49_Pos      (17U)\n#define FDCAN_NDAT2_ND49_Msk      (0x1UL << FDCAN_NDAT2_ND49_Pos)              /*!< 0x00020000 */\n#define FDCAN_NDAT2_ND49          FDCAN_NDAT2_ND49_Msk                         /*!<New Data flag of Rx Buffer 49             */\n#define FDCAN_NDAT2_ND50_Pos      (18U)\n#define FDCAN_NDAT2_ND50_Msk      (0x1UL << FDCAN_NDAT2_ND50_Pos)              /*!< 0x00040000 */\n#define FDCAN_NDAT2_ND50          FDCAN_NDAT2_ND50_Msk                         /*!<New Data flag of Rx Buffer 50             */\n#define FDCAN_NDAT2_ND51_Pos      (19U)\n#define FDCAN_NDAT2_ND51_Msk      (0x1UL << FDCAN_NDAT2_ND51_Pos)              /*!< 0x00080000 */\n#define FDCAN_NDAT2_ND51          FDCAN_NDAT2_ND51_Msk                         /*!<New Data flag of Rx Buffer 51             */\n#define FDCAN_NDAT2_ND52_Pos      (20U)\n#define FDCAN_NDAT2_ND52_Msk      (0x1UL << FDCAN_NDAT2_ND52_Pos)              /*!< 0x00100000 */\n#define FDCAN_NDAT2_ND52          FDCAN_NDAT2_ND52_Msk                         /*!<New Data flag of Rx Buffer 52             */\n#define FDCAN_NDAT2_ND53_Pos      (21U)\n#define FDCAN_NDAT2_ND53_Msk      (0x1UL << FDCAN_NDAT2_ND53_Pos)              /*!< 0x00200000 */\n#define FDCAN_NDAT2_ND53          FDCAN_NDAT2_ND53_Msk                         /*!<New Data flag of Rx Buffer 53             */\n#define FDCAN_NDAT2_ND54_Pos      (22U)\n#define FDCAN_NDAT2_ND54_Msk      (0x1UL << FDCAN_NDAT2_ND54_Pos)              /*!< 0x00400000 */\n#define FDCAN_NDAT2_ND54          FDCAN_NDAT2_ND54_Msk                         /*!<New Data flag of Rx Buffer 54             */\n#define FDCAN_NDAT2_ND55_Pos      (23U)\n#define FDCAN_NDAT2_ND55_Msk      (0x1UL << FDCAN_NDAT2_ND55_Pos)              /*!< 0x00800000 */\n#define FDCAN_NDAT2_ND55          FDCAN_NDAT2_ND55_Msk                         /*!<New Data flag of Rx Buffer 55             */\n#define FDCAN_NDAT2_ND56_Pos      (24U)\n#define FDCAN_NDAT2_ND56_Msk      (0x1UL << FDCAN_NDAT2_ND56_Pos)              /*!< 0x01000000 */\n#define FDCAN_NDAT2_ND56          FDCAN_NDAT2_ND56_Msk                         /*!<New Data flag of Rx Buffer 56             */\n#define FDCAN_NDAT2_ND57_Pos      (25U)\n#define FDCAN_NDAT2_ND57_Msk      (0x1UL << FDCAN_NDAT2_ND57_Pos)              /*!< 0x02000000 */\n#define FDCAN_NDAT2_ND57          FDCAN_NDAT2_ND57_Msk                         /*!<New Data flag of Rx Buffer 57             */\n#define FDCAN_NDAT2_ND58_Pos      (26U)\n#define FDCAN_NDAT2_ND58_Msk      (0x1UL << FDCAN_NDAT2_ND58_Pos)              /*!< 0x04000000 */\n#define FDCAN_NDAT2_ND58          FDCAN_NDAT2_ND58_Msk                         /*!<New Data flag of Rx Buffer 58             */\n#define FDCAN_NDAT2_ND59_Pos      (27U)\n#define FDCAN_NDAT2_ND59_Msk      (0x1UL << FDCAN_NDAT2_ND59_Pos)              /*!< 0x08000000 */\n#define FDCAN_NDAT2_ND59          FDCAN_NDAT2_ND59_Msk                         /*!<New Data flag of Rx Buffer 59             */\n#define FDCAN_NDAT2_ND60_Pos      (28U)\n#define FDCAN_NDAT2_ND60_Msk      (0x1UL << FDCAN_NDAT2_ND60_Pos)              /*!< 0x10000000 */\n#define FDCAN_NDAT2_ND60          FDCAN_NDAT2_ND60_Msk                         /*!<New Data flag of Rx Buffer 60             */\n#define FDCAN_NDAT2_ND61_Pos      (29U)\n#define FDCAN_NDAT2_ND61_Msk      (0x1UL << FDCAN_NDAT2_ND61_Pos)              /*!< 0x20000000 */\n#define FDCAN_NDAT2_ND61          FDCAN_NDAT2_ND61_Msk                         /*!<New Data flag of Rx Buffer 61             */\n#define FDCAN_NDAT2_ND62_Pos      (30U)\n#define FDCAN_NDAT2_ND62_Msk      (0x1UL << FDCAN_NDAT2_ND62_Pos)              /*!< 0x40000000 */\n#define FDCAN_NDAT2_ND62          FDCAN_NDAT2_ND62_Msk                         /*!<New Data flag of Rx Buffer 62             */\n#define FDCAN_NDAT2_ND63_Pos      (31U)\n#define FDCAN_NDAT2_ND63_Msk      (0x1UL << FDCAN_NDAT2_ND63_Pos)              /*!< 0x80000000 */\n#define FDCAN_NDAT2_ND63          FDCAN_NDAT2_ND63_Msk                         /*!<New Data flag of Rx Buffer 63             */\n\n/*****************  Bit definition for FDCAN_RXF0C register  ********************/\n#define FDCAN_RXF0C_F0SA_Pos      (2U)\n#define FDCAN_RXF0C_F0SA_Msk      (0x3FFFUL << FDCAN_RXF0C_F0SA_Pos)           /*!< 0x0000FFFC */\n#define FDCAN_RXF0C_F0SA          FDCAN_RXF0C_F0SA_Msk                         /*!<Rx FIFO 0 Start Address                   */\n#define FDCAN_RXF0C_F0S_Pos       (16U)\n#define FDCAN_RXF0C_F0S_Msk       (0x7FUL << FDCAN_RXF0C_F0S_Pos)              /*!< 0x007F0000 */\n#define FDCAN_RXF0C_F0S           FDCAN_RXF0C_F0S_Msk                          /*!<Number of Rx FIFO 0 elements              */\n#define FDCAN_RXF0C_F0WM_Pos      (24U)\n#define FDCAN_RXF0C_F0WM_Msk      (0x7FUL << FDCAN_RXF0C_F0WM_Pos)             /*!< 0x7F000000 */\n#define FDCAN_RXF0C_F0WM          FDCAN_RXF0C_F0WM_Msk                         /*!<FIFO 0 Watermark                          */\n#define FDCAN_RXF0C_F0OM_Pos      (31U)\n#define FDCAN_RXF0C_F0OM_Msk      (0x1UL << FDCAN_RXF0C_F0OM_Pos)              /*!< 0x80000000 */\n#define FDCAN_RXF0C_F0OM          FDCAN_RXF0C_F0OM_Msk                         /*!<FIFO 0 Operation Mode                     */\n\n/*****************  Bit definition for FDCAN_RXF0S register  ********************/\n#define FDCAN_RXF0S_F0FL_Pos      (0U)\n#define FDCAN_RXF0S_F0FL_Msk      (0x7FUL << FDCAN_RXF0S_F0FL_Pos)             /*!< 0x0000007F */\n#define FDCAN_RXF0S_F0FL          FDCAN_RXF0S_F0FL_Msk                         /*!<Rx FIFO 0 Fill Level                      */\n#define FDCAN_RXF0S_F0GI_Pos      (8U)\n#define FDCAN_RXF0S_F0GI_Msk      (0x3FUL << FDCAN_RXF0S_F0GI_Pos)             /*!< 0x00003F00 */\n#define FDCAN_RXF0S_F0GI          FDCAN_RXF0S_F0GI_Msk                         /*!<Rx FIFO 0 Get Index                       */\n#define FDCAN_RXF0S_F0PI_Pos      (16U)\n#define FDCAN_RXF0S_F0PI_Msk      (0x3FUL << FDCAN_RXF0S_F0PI_Pos)             /*!< 0x003F0000 */\n#define FDCAN_RXF0S_F0PI          FDCAN_RXF0S_F0PI_Msk                         /*!<Rx FIFO 0 Put Index                       */\n#define FDCAN_RXF0S_F0F_Pos       (24U)\n#define FDCAN_RXF0S_F0F_Msk       (0x1UL << FDCAN_RXF0S_F0F_Pos)               /*!< 0x01000000 */\n#define FDCAN_RXF0S_F0F           FDCAN_RXF0S_F0F_Msk                          /*!<Rx FIFO 0 Full                            */\n#define FDCAN_RXF0S_RF0L_Pos      (25U)\n#define FDCAN_RXF0S_RF0L_Msk      (0x1UL << FDCAN_RXF0S_RF0L_Pos)              /*!< 0x02000000 */\n#define FDCAN_RXF0S_RF0L          FDCAN_RXF0S_RF0L_Msk                         /*!<Rx FIFO 0 Message Lost                    */\n\n/*****************  Bit definition for FDCAN_RXF0A register  ********************/\n#define FDCAN_RXF0A_F0AI_Pos      (0U)\n#define FDCAN_RXF0A_F0AI_Msk      (0x3FUL << FDCAN_RXF0A_F0AI_Pos)             /*!< 0x0000003F */\n#define FDCAN_RXF0A_F0AI          FDCAN_RXF0A_F0AI_Msk                         /*!<Rx FIFO 0 Acknowledge Index               */\n\n/*****************  Bit definition for FDCAN_RXBC register  ********************/\n#define FDCAN_RXBC_RBSA_Pos       (2U)\n#define FDCAN_RXBC_RBSA_Msk       (0x3FFFUL << FDCAN_RXBC_RBSA_Pos)            /*!< 0x0000FFFC */\n#define FDCAN_RXBC_RBSA           FDCAN_RXBC_RBSA_Msk                          /*!<Rx Buffer Start Address                   */\n\n/*****************  Bit definition for FDCAN_RXF1C register  ********************/\n#define FDCAN_RXF1C_F1SA_Pos      (2U)\n#define FDCAN_RXF1C_F1SA_Msk      (0x3FFFUL << FDCAN_RXF1C_F1SA_Pos)           /*!< 0x0000FFFC */\n#define FDCAN_RXF1C_F1SA          FDCAN_RXF1C_F1SA_Msk                         /*!<Rx FIFO 1 Start Address                   */\n#define FDCAN_RXF1C_F1S_Pos       (16U)\n#define FDCAN_RXF1C_F1S_Msk       (0x7FUL << FDCAN_RXF1C_F1S_Pos)              /*!< 0x007F0000 */\n#define FDCAN_RXF1C_F1S           FDCAN_RXF1C_F1S_Msk                          /*!<Number of Rx FIFO 1 elements              */\n#define FDCAN_RXF1C_F1WM_Pos      (24U)\n#define FDCAN_RXF1C_F1WM_Msk      (0x7FUL << FDCAN_RXF1C_F1WM_Pos)             /*!< 0x7F000000 */\n#define FDCAN_RXF1C_F1WM          FDCAN_RXF1C_F1WM_Msk                         /*!<Rx FIFO 1 Watermark                       */\n#define FDCAN_RXF1C_F1OM_Pos      (31U)\n#define FDCAN_RXF1C_F1OM_Msk      (0x1UL << FDCAN_RXF1C_F1OM_Pos)              /*!< 0x80000000 */\n#define FDCAN_RXF1C_F1OM          FDCAN_RXF1C_F1OM_Msk                         /*!<FIFO 1 Operation Mode                     */\n\n/*****************  Bit definition for FDCAN_RXF1S register  ********************/\n#define FDCAN_RXF1S_F1FL_Pos      (0U)\n#define FDCAN_RXF1S_F1FL_Msk      (0x7FUL << FDCAN_RXF1S_F1FL_Pos)             /*!< 0x0000007F */\n#define FDCAN_RXF1S_F1FL          FDCAN_RXF1S_F1FL_Msk                         /*!<Rx FIFO 1 Fill Level                      */\n#define FDCAN_RXF1S_F1GI_Pos      (8U)\n#define FDCAN_RXF1S_F1GI_Msk      (0x3FUL << FDCAN_RXF1S_F1GI_Pos)             /*!< 0x00003F00 */\n#define FDCAN_RXF1S_F1GI          FDCAN_RXF1S_F1GI_Msk                         /*!<Rx FIFO 1 Get Index                       */\n#define FDCAN_RXF1S_F1PI_Pos      (16U)\n#define FDCAN_RXF1S_F1PI_Msk      (0x3FUL << FDCAN_RXF1S_F1PI_Pos)             /*!< 0x003F0000 */\n#define FDCAN_RXF1S_F1PI          FDCAN_RXF1S_F1PI_Msk                         /*!<Rx FIFO 1 Put Index                       */\n#define FDCAN_RXF1S_F1F_Pos       (24U)\n#define FDCAN_RXF1S_F1F_Msk       (0x1UL << FDCAN_RXF1S_F1F_Pos)               /*!< 0x01000000 */\n#define FDCAN_RXF1S_F1F           FDCAN_RXF1S_F1F_Msk                          /*!<Rx FIFO 1 Full                            */\n#define FDCAN_RXF1S_RF1L_Pos      (25U)\n#define FDCAN_RXF1S_RF1L_Msk      (0x1UL << FDCAN_RXF1S_RF1L_Pos)              /*!< 0x02000000 */\n#define FDCAN_RXF1S_RF1L          FDCAN_RXF1S_RF1L_Msk                         /*!<Rx FIFO 1 Message Lost                    */\n\n/*****************  Bit definition for FDCAN_RXF1A register  ********************/\n#define FDCAN_RXF1A_F1AI_Pos      (0U)\n#define FDCAN_RXF1A_F1AI_Msk      (0x3FUL << FDCAN_RXF1A_F1AI_Pos)             /*!< 0x0000003F */\n#define FDCAN_RXF1A_F1AI          FDCAN_RXF1A_F1AI_Msk                         /*!<Rx FIFO 1 Acknowledge Index               */\n\n/*****************  Bit definition for FDCAN_RXESC register  ********************/\n#define FDCAN_RXESC_F0DS_Pos      (0U)\n#define FDCAN_RXESC_F0DS_Msk      (0x7UL << FDCAN_RXESC_F0DS_Pos)              /*!< 0x00000007 */\n#define FDCAN_RXESC_F0DS          FDCAN_RXESC_F0DS_Msk                         /*!<Rx FIFO 1 Data Field Size                 */\n#define FDCAN_RXESC_F1DS_Pos      (4U)\n#define FDCAN_RXESC_F1DS_Msk      (0x7UL << FDCAN_RXESC_F1DS_Pos)              /*!< 0x00000070 */\n#define FDCAN_RXESC_F1DS          FDCAN_RXESC_F1DS_Msk                         /*!<Rx FIFO 0 Data Field Size                 */\n#define FDCAN_RXESC_RBDS_Pos      (8U)\n#define FDCAN_RXESC_RBDS_Msk      (0x7UL << FDCAN_RXESC_RBDS_Pos)              /*!< 0x00000700 */\n#define FDCAN_RXESC_RBDS          FDCAN_RXESC_RBDS_Msk                         /*!<Rx Buffer Data Field Size                 */\n\n/*****************  Bit definition for FDCAN_TXBC register  *********************/\n#define FDCAN_TXBC_TBSA_Pos       (2U)\n#define FDCAN_TXBC_TBSA_Msk       (0x3FFFUL << FDCAN_TXBC_TBSA_Pos)            /*!< 0x0000FFFC */\n#define FDCAN_TXBC_TBSA           FDCAN_TXBC_TBSA_Msk                          /*!<Tx Buffers Start Address                  */\n#define FDCAN_TXBC_NDTB_Pos       (16U)\n#define FDCAN_TXBC_NDTB_Msk       (0x3FUL << FDCAN_TXBC_NDTB_Pos)              /*!< 0x003F0000 */\n#define FDCAN_TXBC_NDTB           FDCAN_TXBC_NDTB_Msk                          /*!<Number of Dedicated Transmit Buffers      */\n#define FDCAN_TXBC_TFQS_Pos       (24U)\n#define FDCAN_TXBC_TFQS_Msk       (0x3FUL << FDCAN_TXBC_TFQS_Pos)              /*!< 0x3F000000 */\n#define FDCAN_TXBC_TFQS           FDCAN_TXBC_TFQS_Msk                          /*!<Transmit FIFO/Queue Size                  */\n#define FDCAN_TXBC_TFQM_Pos       (30U)\n#define FDCAN_TXBC_TFQM_Msk       (0x1UL << FDCAN_TXBC_TFQM_Pos)               /*!< 0x40000000 */\n#define FDCAN_TXBC_TFQM           FDCAN_TXBC_TFQM_Msk                          /*!<Tx FIFO/Queue Mode                        */\n\n/*****************  Bit definition for FDCAN_TXFQS register  *********************/\n#define FDCAN_TXFQS_TFFL_Pos      (0U)\n#define FDCAN_TXFQS_TFFL_Msk      (0x3FUL << FDCAN_TXFQS_TFFL_Pos)             /*!< 0x0000003F */\n#define FDCAN_TXFQS_TFFL          FDCAN_TXFQS_TFFL_Msk                         /*!<Tx FIFO Free Level                        */\n#define FDCAN_TXFQS_TFGI_Pos      (8U)\n#define FDCAN_TXFQS_TFGI_Msk      (0x1FUL << FDCAN_TXFQS_TFGI_Pos)             /*!< 0x00001F00 */\n#define FDCAN_TXFQS_TFGI          FDCAN_TXFQS_TFGI_Msk                         /*!<Tx FIFO Get Index                         */\n#define FDCAN_TXFQS_TFQPI_Pos     (16U)\n#define FDCAN_TXFQS_TFQPI_Msk     (0x1FUL << FDCAN_TXFQS_TFQPI_Pos)            /*!< 0x001F0000 */\n#define FDCAN_TXFQS_TFQPI         FDCAN_TXFQS_TFQPI_Msk                        /*!<Tx FIFO/Queue Put Index                   */\n#define FDCAN_TXFQS_TFQF_Pos      (21U)\n#define FDCAN_TXFQS_TFQF_Msk      (0x1UL << FDCAN_TXFQS_TFQF_Pos)              /*!< 0x00200000 */\n#define FDCAN_TXFQS_TFQF          FDCAN_TXFQS_TFQF_Msk                         /*!<Tx FIFO/Queue Full                        */\n\n/*****************  Bit definition for FDCAN_TXESC register  *********************/\n#define FDCAN_TXESC_TBDS_Pos      (0U)\n#define FDCAN_TXESC_TBDS_Msk      (0x7UL << FDCAN_TXESC_TBDS_Pos)              /*!< 0x00000007 */\n#define FDCAN_TXESC_TBDS          FDCAN_TXESC_TBDS_Msk                         /*!<Tx Buffer Data Field Size                 */\n\n/*****************  Bit definition for FDCAN_TXBRP register  *********************/\n#define FDCAN_TXBRP_TRP_Pos       (0U)\n#define FDCAN_TXBRP_TRP_Msk       (0xFFFFFFFFUL << FDCAN_TXBRP_TRP_Pos)        /*!< 0xFFFFFFFF */\n#define FDCAN_TXBRP_TRP           FDCAN_TXBRP_TRP_Msk                          /*!<Transmission Request Pending              */\n\n/*****************  Bit definition for FDCAN_TXBAR register  *********************/\n#define FDCAN_TXBAR_AR_Pos        (0U)\n#define FDCAN_TXBAR_AR_Msk        (0xFFFFFFFFUL << FDCAN_TXBAR_AR_Pos)         /*!< 0xFFFFFFFF */\n#define FDCAN_TXBAR_AR            FDCAN_TXBAR_AR_Msk                           /*!<Add Request                               */\n\n/*****************  Bit definition for FDCAN_TXBCR register  *********************/\n#define FDCAN_TXBCR_CR_Pos        (0U)\n#define FDCAN_TXBCR_CR_Msk        (0xFFFFFFFFUL << FDCAN_TXBCR_CR_Pos)         /*!< 0xFFFFFFFF */\n#define FDCAN_TXBCR_CR            FDCAN_TXBCR_CR_Msk                           /*!<Cancellation Request                      */\n\n/*****************  Bit definition for FDCAN_TXBTO register  *********************/\n#define FDCAN_TXBTO_TO_Pos        (0U)\n#define FDCAN_TXBTO_TO_Msk        (0xFFFFFFFFUL << FDCAN_TXBTO_TO_Pos)         /*!< 0xFFFFFFFF */\n#define FDCAN_TXBTO_TO            FDCAN_TXBTO_TO_Msk                           /*!<Transmission Occurred                     */\n\n/*****************  Bit definition for FDCAN_TXBCF register  *********************/\n#define FDCAN_TXBCF_CF_Pos        (0U)\n#define FDCAN_TXBCF_CF_Msk        (0xFFFFFFFFUL << FDCAN_TXBCF_CF_Pos)         /*!< 0xFFFFFFFF */\n#define FDCAN_TXBCF_CF            FDCAN_TXBCF_CF_Msk                           /*!<Cancellation Finished                     */\n\n/*****************  Bit definition for FDCAN_TXBTIE register  ********************/\n#define FDCAN_TXBTIE_TIE_Pos      (0U)\n#define FDCAN_TXBTIE_TIE_Msk      (0xFFFFFFFFUL << FDCAN_TXBTIE_TIE_Pos)       /*!< 0xFFFFFFFF */\n#define FDCAN_TXBTIE_TIE          FDCAN_TXBTIE_TIE_Msk                         /*!<Transmission Interrupt Enable             */\n\n/*****************  Bit definition for FDCAN_ TXBCIE register  *******************/\n#define FDCAN_TXBCIE_CFIE_Pos     (0U)\n#define FDCAN_TXBCIE_CFIE_Msk     (0xFFFFFFFFUL << FDCAN_TXBCIE_CFIE_Pos)      /*!< 0xFFFFFFFF */\n#define FDCAN_TXBCIE_CFIE         FDCAN_TXBCIE_CFIE_Msk                        /*!<Cancellation Finished Interrupt Enable    */\n\n/*****************  Bit definition for FDCAN_TXEFC register  *********************/\n#define FDCAN_TXEFC_EFSA_Pos      (2U)\n#define FDCAN_TXEFC_EFSA_Msk      (0x3FFFUL << FDCAN_TXEFC_EFSA_Pos)           /*!< 0x0000FFFC */\n#define FDCAN_TXEFC_EFSA          FDCAN_TXEFC_EFSA_Msk                         /*!<Event FIFO Start Address                  */\n#define FDCAN_TXEFC_EFS_Pos       (16U)\n#define FDCAN_TXEFC_EFS_Msk       (0x3FUL << FDCAN_TXEFC_EFS_Pos)              /*!< 0x003F0000 */\n#define FDCAN_TXEFC_EFS           FDCAN_TXEFC_EFS_Msk                          /*!<Event FIFO Size                           */\n#define FDCAN_TXEFC_EFWM_Pos      (24U)\n#define FDCAN_TXEFC_EFWM_Msk      (0x3FUL << FDCAN_TXEFC_EFWM_Pos)             /*!< 0x3F000000 */\n#define FDCAN_TXEFC_EFWM          FDCAN_TXEFC_EFWM_Msk                         /*!<Event FIFO Watermark                      */\n\n/*****************  Bit definition for FDCAN_TXEFS register  *********************/\n#define FDCAN_TXEFS_EFFL_Pos      (0U)\n#define FDCAN_TXEFS_EFFL_Msk      (0x3FUL << FDCAN_TXEFS_EFFL_Pos)             /*!< 0x0000003F */\n#define FDCAN_TXEFS_EFFL          FDCAN_TXEFS_EFFL_Msk                         /*!<Event FIFO Fill Level                     */\n#define FDCAN_TXEFS_EFGI_Pos      (8U)\n#define FDCAN_TXEFS_EFGI_Msk      (0x1FUL << FDCAN_TXEFS_EFGI_Pos)             /*!< 0x00001F00 */\n#define FDCAN_TXEFS_EFGI          FDCAN_TXEFS_EFGI_Msk                         /*!<Event FIFO Get Index                      */\n#define FDCAN_TXEFS_EFPI_Pos      (16U)\n#define FDCAN_TXEFS_EFPI_Msk      (0x1FUL << FDCAN_TXEFS_EFPI_Pos)             /*!< 0x001F0000 */\n#define FDCAN_TXEFS_EFPI          FDCAN_TXEFS_EFPI_Msk                         /*!<Event FIFO Put Index                      */\n#define FDCAN_TXEFS_EFF_Pos       (24U)\n#define FDCAN_TXEFS_EFF_Msk       (0x1UL << FDCAN_TXEFS_EFF_Pos)               /*!< 0x01000000 */\n#define FDCAN_TXEFS_EFF           FDCAN_TXEFS_EFF_Msk                          /*!<Event FIFO Full                           */\n#define FDCAN_TXEFS_TEFL_Pos      (25U)\n#define FDCAN_TXEFS_TEFL_Msk      (0x1UL << FDCAN_TXEFS_TEFL_Pos)              /*!< 0x02000000 */\n#define FDCAN_TXEFS_TEFL          FDCAN_TXEFS_TEFL_Msk                         /*!<Tx Event FIFO Element Lost                */\n\n/*****************  Bit definition for FDCAN_TXEFA register  *********************/\n#define FDCAN_TXEFA_EFAI_Pos      (0U)\n#define FDCAN_TXEFA_EFAI_Msk      (0x1FUL << FDCAN_TXEFA_EFAI_Pos)             /*!< 0x0000001F */\n#define FDCAN_TXEFA_EFAI          FDCAN_TXEFA_EFAI_Msk                         /*!<Event FIFO Acknowledge Index              */\n\n/*****************  Bit definition for FDCAN_TTTMC register  *********************/\n#define FDCAN_TTTMC_TMSA_Pos      (2U)\n#define FDCAN_TTTMC_TMSA_Msk      (0x3FFFUL << FDCAN_TTTMC_TMSA_Pos)           /*!< 0x0000FFFC */\n#define FDCAN_TTTMC_TMSA          FDCAN_TTTMC_TMSA_Msk                         /*!<Trigger Memory Start Address              */\n#define FDCAN_TTTMC_TME_Pos       (16U)\n#define FDCAN_TTTMC_TME_Msk       (0x7FUL << FDCAN_TTTMC_TME_Pos)              /*!< 0x007F0000 */\n#define FDCAN_TTTMC_TME           FDCAN_TTTMC_TME_Msk                          /*!<Trigger Memory Elements                   */\n\n/*****************  Bit definition for FDCAN_TTRMC register  *********************/\n#define FDCAN_TTRMC_RID_Pos       (0U)\n#define FDCAN_TTRMC_RID_Msk       (0x1FFFFFFFUL << FDCAN_TTRMC_RID_Pos)        /*!< 0x1FFFFFFF */\n#define FDCAN_TTRMC_RID           FDCAN_TTRMC_RID_Msk                          /*!<Reference Identifier                      */\n#define FDCAN_TTRMC_XTD_Pos       (30U)\n#define FDCAN_TTRMC_XTD_Msk       (0x1UL << FDCAN_TTRMC_XTD_Pos)               /*!< 0x40000000 */\n#define FDCAN_TTRMC_XTD           FDCAN_TTRMC_XTD_Msk                          /*!< Extended Identifier                      */\n#define FDCAN_TTRMC_RMPS_Pos      (31U)\n#define FDCAN_TTRMC_RMPS_Msk      (0x1UL << FDCAN_TTRMC_RMPS_Pos)              /*!< 0x80000000 */\n#define FDCAN_TTRMC_RMPS          FDCAN_TTRMC_RMPS_Msk                         /*!<Reference Message Payload Select          */\n\n/*****************  Bit definition for FDCAN_TTOCF register  *********************/\n#define FDCAN_TTOCF_OM_Pos        (0U)\n#define FDCAN_TTOCF_OM_Msk        (0x3UL << FDCAN_TTOCF_OM_Pos)                /*!< 0x00000003 */\n#define FDCAN_TTOCF_OM            FDCAN_TTOCF_OM_Msk                           /*!<Operation Mode                            */\n#define FDCAN_TTOCF_GEN_Pos       (3U)\n#define FDCAN_TTOCF_GEN_Msk       (0x1UL << FDCAN_TTOCF_GEN_Pos)               /*!< 0x00000008 */\n#define FDCAN_TTOCF_GEN           FDCAN_TTOCF_GEN_Msk                          /*!<Gap Enable                                */\n#define FDCAN_TTOCF_TM_Pos        (4U)\n#define FDCAN_TTOCF_TM_Msk        (0x1UL << FDCAN_TTOCF_TM_Pos)                /*!< 0x00000010 */\n#define FDCAN_TTOCF_TM            FDCAN_TTOCF_TM_Msk                           /*!<Time Master                               */\n#define FDCAN_TTOCF_LDSDL_Pos     (5U)\n#define FDCAN_TTOCF_LDSDL_Msk     (0x7UL << FDCAN_TTOCF_LDSDL_Pos)             /*!< 0x000000E0 */\n#define FDCAN_TTOCF_LDSDL         FDCAN_TTOCF_LDSDL_Msk                        /*!<LD of Synchronization Deviation Limit     */\n#define FDCAN_TTOCF_IRTO_Pos      (8U)\n#define FDCAN_TTOCF_IRTO_Msk      (0x7FUL << FDCAN_TTOCF_IRTO_Pos)             /*!< 0x00007F00 */\n#define FDCAN_TTOCF_IRTO          FDCAN_TTOCF_IRTO_Msk                         /*!<Initial Reference Trigger Offset          */\n#define FDCAN_TTOCF_EECS_Pos      (15U)\n#define FDCAN_TTOCF_EECS_Msk      (0x1UL << FDCAN_TTOCF_EECS_Pos)              /*!< 0x00008000 */\n#define FDCAN_TTOCF_EECS          FDCAN_TTOCF_EECS_Msk                         /*!<Enable External Clock Synchronization     */\n#define FDCAN_TTOCF_AWL_Pos       (16U)\n#define FDCAN_TTOCF_AWL_Msk       (0xFFUL << FDCAN_TTOCF_AWL_Pos)              /*!< 0x00FF0000 */\n#define FDCAN_TTOCF_AWL           FDCAN_TTOCF_AWL_Msk                          /*!<Application Watchdog Limit                */\n#define FDCAN_TTOCF_EGTF_Pos      (24U)\n#define FDCAN_TTOCF_EGTF_Msk      (0x1UL << FDCAN_TTOCF_EGTF_Pos)              /*!< 0x01000000 */\n#define FDCAN_TTOCF_EGTF          FDCAN_TTOCF_EGTF_Msk                         /*!<Enable Global Time Filtering              */\n#define FDCAN_TTOCF_ECC_Pos       (25U)\n#define FDCAN_TTOCF_ECC_Msk       (0x1UL << FDCAN_TTOCF_ECC_Pos)               /*!< 0x02000000 */\n#define FDCAN_TTOCF_ECC           FDCAN_TTOCF_ECC_Msk                          /*!<Enable Clock Calibration                  */\n#define FDCAN_TTOCF_EVTP_Pos      (26U)\n#define FDCAN_TTOCF_EVTP_Msk      (0x1UL << FDCAN_TTOCF_EVTP_Pos)              /*!< 0x04000000 */\n#define FDCAN_TTOCF_EVTP          FDCAN_TTOCF_EVTP_Msk                         /*!<Event Trigger Polarity                    */\n\n/*****************  Bit definition for FDCAN_TTMLM register  *********************/\n#define FDCAN_TTMLM_CCM_Pos       (0U)\n#define FDCAN_TTMLM_CCM_Msk       (0x3FUL << FDCAN_TTMLM_CCM_Pos)              /*!< 0x0000003F */\n#define FDCAN_TTMLM_CCM           FDCAN_TTMLM_CCM_Msk                          /*!<Cycle Count Max                           */\n#define FDCAN_TTMLM_CSS_Pos       (6U)\n#define FDCAN_TTMLM_CSS_Msk       (0x3UL << FDCAN_TTMLM_CSS_Pos)               /*!< 0x000000C0 */\n#define FDCAN_TTMLM_CSS           FDCAN_TTMLM_CSS_Msk                          /*!<Cycle Start Synchronization               */\n#define FDCAN_TTMLM_TXEW_Pos      (8U)\n#define FDCAN_TTMLM_TXEW_Msk      (0xFUL << FDCAN_TTMLM_TXEW_Pos)              /*!< 0x00000F00 */\n#define FDCAN_TTMLM_TXEW          FDCAN_TTMLM_TXEW_Msk                         /*!<Tx Enable Window                          */\n#define FDCAN_TTMLM_ENTT_Pos      (16U)\n#define FDCAN_TTMLM_ENTT_Msk      (0xFFFUL << FDCAN_TTMLM_ENTT_Pos)            /*!< 0x0FFF0000 */\n#define FDCAN_TTMLM_ENTT          FDCAN_TTMLM_ENTT_Msk                         /*!<Expected Number of Tx Triggers            */\n\n/*****************  Bit definition for FDCAN_TURCF register  *********************/\n#define FDCAN_TURCF_NCL_Pos       (0U)\n#define FDCAN_TURCF_NCL_Msk       (0xFFFFUL << FDCAN_TURCF_NCL_Pos)            /*!< 0x0000FFFF */\n#define FDCAN_TURCF_NCL           FDCAN_TURCF_NCL_Msk                          /*!<Numerator Configuration Low               */\n#define FDCAN_TURCF_DC_Pos        (16U)\n#define FDCAN_TURCF_DC_Msk        (0x3FFFUL << FDCAN_TURCF_DC_Pos)             /*!< 0x3FFF0000 */\n#define FDCAN_TURCF_DC            FDCAN_TURCF_DC_Msk                           /*!<Denominator Configuration                 */\n#define FDCAN_TURCF_ELT_Pos       (31U)\n#define FDCAN_TURCF_ELT_Msk       (0x1UL << FDCAN_TURCF_ELT_Pos)               /*!< 0x80000000 */\n#define FDCAN_TURCF_ELT           FDCAN_TURCF_ELT_Msk                          /*!<Enable Local Time                         */\n\n/*****************  Bit definition for FDCAN_TTOCN register  ********************/\n#define FDCAN_TTOCN_SGT_Pos       (0U)\n#define FDCAN_TTOCN_SGT_Msk       (0x1UL << FDCAN_TTOCN_SGT_Pos)               /*!< 0x00000001 */\n#define FDCAN_TTOCN_SGT           FDCAN_TTOCN_SGT_Msk                          /*!<Set Global time                           */\n#define FDCAN_TTOCN_ECS_Pos       (1U)\n#define FDCAN_TTOCN_ECS_Msk       (0x1UL << FDCAN_TTOCN_ECS_Pos)               /*!< 0x00000002 */\n#define FDCAN_TTOCN_ECS           FDCAN_TTOCN_ECS_Msk                          /*!<External Clock Synchronization            */\n#define FDCAN_TTOCN_SWP_Pos       (2U)\n#define FDCAN_TTOCN_SWP_Msk       (0x1UL << FDCAN_TTOCN_SWP_Pos)               /*!< 0x00000004 */\n#define FDCAN_TTOCN_SWP           FDCAN_TTOCN_SWP_Msk                          /*!<Stop Watch Polarity                       */\n#define FDCAN_TTOCN_SWS_Pos       (3U)\n#define FDCAN_TTOCN_SWS_Msk       (0x3UL << FDCAN_TTOCN_SWS_Pos)               /*!< 0x00000018 */\n#define FDCAN_TTOCN_SWS           FDCAN_TTOCN_SWS_Msk                          /*!<Stop Watch Source                         */\n#define FDCAN_TTOCN_RTIE_Pos      (5U)\n#define FDCAN_TTOCN_RTIE_Msk      (0x1UL << FDCAN_TTOCN_RTIE_Pos)              /*!< 0x00000020 */\n#define FDCAN_TTOCN_RTIE          FDCAN_TTOCN_RTIE_Msk                         /*!<Register Time Mark Interrupt Pulse Enable */\n#define FDCAN_TTOCN_TMC_Pos       (6U)\n#define FDCAN_TTOCN_TMC_Msk       (0x3UL << FDCAN_TTOCN_TMC_Pos)               /*!< 0x000000C0 */\n#define FDCAN_TTOCN_TMC           FDCAN_TTOCN_TMC_Msk                          /*!<Register Time Mark Compare                */\n#define FDCAN_TTOCN_TTIE_Pos      (8U)\n#define FDCAN_TTOCN_TTIE_Msk      (0x1UL << FDCAN_TTOCN_TTIE_Pos)              /*!< 0x00000100 */\n#define FDCAN_TTOCN_TTIE          FDCAN_TTOCN_TTIE_Msk                         /*!<Trigger Time Mark Interrupt Pulse Enable  */\n#define FDCAN_TTOCN_GCS_Pos       (9U)\n#define FDCAN_TTOCN_GCS_Msk       (0x1UL << FDCAN_TTOCN_GCS_Pos)               /*!< 0x00000200 */\n#define FDCAN_TTOCN_GCS           FDCAN_TTOCN_GCS_Msk                          /*!<Gap Control Select                        */\n#define FDCAN_TTOCN_FGP_Pos       (10U)\n#define FDCAN_TTOCN_FGP_Msk       (0x1UL << FDCAN_TTOCN_FGP_Pos)               /*!< 0x00000400 */\n#define FDCAN_TTOCN_FGP           FDCAN_TTOCN_FGP_Msk                          /*!<Finish Gap                                */\n#define FDCAN_TTOCN_TMG_Pos       (11U)\n#define FDCAN_TTOCN_TMG_Msk       (0x1UL << FDCAN_TTOCN_TMG_Pos)               /*!< 0x00000800 */\n#define FDCAN_TTOCN_TMG           FDCAN_TTOCN_TMG_Msk                          /*!<Time Mark Gap                             */\n#define FDCAN_TTOCN_NIG_Pos       (12U)\n#define FDCAN_TTOCN_NIG_Msk       (0x1UL << FDCAN_TTOCN_NIG_Pos)               /*!< 0x00001000 */\n#define FDCAN_TTOCN_NIG           FDCAN_TTOCN_NIG_Msk                          /*!<Next is Gap                               */\n#define FDCAN_TTOCN_ESCN_Pos      (13U)\n#define FDCAN_TTOCN_ESCN_Msk      (0x1UL << FDCAN_TTOCN_ESCN_Pos)              /*!< 0x00002000 */\n#define FDCAN_TTOCN_ESCN          FDCAN_TTOCN_ESCN_Msk                         /*!<External Synchronization Control          */\n#define FDCAN_TTOCN_LCKC_Pos      (15U)\n#define FDCAN_TTOCN_LCKC_Msk      (0x1UL << FDCAN_TTOCN_LCKC_Pos)              /*!< 0x00008000 */\n#define FDCAN_TTOCN_LCKC          FDCAN_TTOCN_LCKC_Msk                         /*!<TT Operation Control Register Locked      */\n\n/*****************  Bit definition for FDCAN_TTGTP register  ********************/\n#define FDCAN_TTGTP_TP_Pos        (0U)\n#define FDCAN_TTGTP_TP_Msk        (0xFFFFUL << FDCAN_TTGTP_TP_Pos)             /*!< 0x0000FFFF */\n#define FDCAN_TTGTP_TP            FDCAN_TTGTP_TP_Msk                           /*!<Time Preset                               */\n#define FDCAN_TTGTP_CTP_Pos       (16U)\n#define FDCAN_TTGTP_CTP_Msk       (0xFFFFUL << FDCAN_TTGTP_CTP_Pos)            /*!< 0xFFFF0000 */\n#define FDCAN_TTGTP_CTP           FDCAN_TTGTP_CTP_Msk                          /*!<Cycle Time Target Phase                   */\n\n/*****************  Bit definition for FDCAN_TTTMK register  ********************/\n#define FDCAN_TTTMK_TM_Pos        (0U)\n#define FDCAN_TTTMK_TM_Msk        (0xFFFFUL << FDCAN_TTTMK_TM_Pos)             /*!< 0x0000FFFF */\n#define FDCAN_TTTMK_TM            FDCAN_TTTMK_TM_Msk                           /*!<Time Mark                                 */\n#define FDCAN_TTTMK_TICC_Pos      (16U)\n#define FDCAN_TTTMK_TICC_Msk      (0x7FUL << FDCAN_TTTMK_TICC_Pos)             /*!< 0x007F0000 */\n#define FDCAN_TTTMK_TICC          FDCAN_TTTMK_TICC_Msk                         /*!<Time Mark Cycle Code                      */\n#define FDCAN_TTTMK_LCKM_Pos      (31U)\n#define FDCAN_TTTMK_LCKM_Msk      (0x1UL << FDCAN_TTTMK_LCKM_Pos)              /*!< 0x80000000 */\n#define FDCAN_TTTMK_LCKM          FDCAN_TTTMK_LCKM_Msk                         /*!<TT Time Mark Register Locked              */\n\n/*****************  Bit definition for FDCAN_TTIR register  ********************/\n#define FDCAN_TTIR_SBC_Pos        (0U)\n#define FDCAN_TTIR_SBC_Msk        (0x1UL << FDCAN_TTIR_SBC_Pos)                /*!< 0x00000001 */\n#define FDCAN_TTIR_SBC            FDCAN_TTIR_SBC_Msk                           /*!<Start of Basic Cycle                      */\n#define FDCAN_TTIR_SMC_Pos        (1U)\n#define FDCAN_TTIR_SMC_Msk        (0x1UL << FDCAN_TTIR_SMC_Pos)                /*!< 0x00000002 */\n#define FDCAN_TTIR_SMC            FDCAN_TTIR_SMC_Msk                           /*!<Start of Matrix Cycle                     */\n#define FDCAN_TTIR_CSM_Pos        (2U)\n#define FDCAN_TTIR_CSM_Msk        (0x1UL << FDCAN_TTIR_CSM_Pos)                /*!< 0x00000004 */\n#define FDCAN_TTIR_CSM            FDCAN_TTIR_CSM_Msk                           /*!<Change of Synchronization Mode            */\n#define FDCAN_TTIR_SOG_Pos        (3U)\n#define FDCAN_TTIR_SOG_Msk        (0x1UL << FDCAN_TTIR_SOG_Pos)                /*!< 0x00000008 */\n#define FDCAN_TTIR_SOG            FDCAN_TTIR_SOG_Msk                           /*!<Start of Gap                              */\n#define FDCAN_TTIR_RTMI_Pos       (4U)\n#define FDCAN_TTIR_RTMI_Msk       (0x1UL << FDCAN_TTIR_RTMI_Pos)               /*!< 0x00000010 */\n#define FDCAN_TTIR_RTMI           FDCAN_TTIR_RTMI_Msk                          /*!<Register Time Mark Interrupt              */\n#define FDCAN_TTIR_TTMI_Pos       (5U)\n#define FDCAN_TTIR_TTMI_Msk       (0x1UL << FDCAN_TTIR_TTMI_Pos)               /*!< 0x00000020 */\n#define FDCAN_TTIR_TTMI           FDCAN_TTIR_TTMI_Msk                          /*!<Trigger Time Mark Event Internal          */\n#define FDCAN_TTIR_SWE_Pos        (6U)\n#define FDCAN_TTIR_SWE_Msk        (0x1UL << FDCAN_TTIR_SWE_Pos)                /*!< 0x00000040 */\n#define FDCAN_TTIR_SWE            FDCAN_TTIR_SWE_Msk                           /*!<Stop Watch Event                          */\n#define FDCAN_TTIR_GTW_Pos        (7U)\n#define FDCAN_TTIR_GTW_Msk        (0x1UL << FDCAN_TTIR_GTW_Pos)                /*!< 0x00000080 */\n#define FDCAN_TTIR_GTW            FDCAN_TTIR_GTW_Msk                           /*!<Global Time Wrap                          */\n#define FDCAN_TTIR_GTD_Pos        (8U)\n#define FDCAN_TTIR_GTD_Msk        (0x1UL << FDCAN_TTIR_GTD_Pos)                /*!< 0x00000100 */\n#define FDCAN_TTIR_GTD            FDCAN_TTIR_GTD_Msk                           /*!<Global Time Discontinuity                 */\n#define FDCAN_TTIR_GTE_Pos        (9U)\n#define FDCAN_TTIR_GTE_Msk        (0x1UL << FDCAN_TTIR_GTE_Pos)                /*!< 0x00000200 */\n#define FDCAN_TTIR_GTE            FDCAN_TTIR_GTE_Msk                           /*!<Global Time Error                         */\n#define FDCAN_TTIR_TXU_Pos        (10U)\n#define FDCAN_TTIR_TXU_Msk        (0x1UL << FDCAN_TTIR_TXU_Pos)                /*!< 0x00000400 */\n#define FDCAN_TTIR_TXU            FDCAN_TTIR_TXU_Msk                           /*!<Tx Count Underflow                        */\n#define FDCAN_TTIR_TXO_Pos        (11U)\n#define FDCAN_TTIR_TXO_Msk        (0x1UL << FDCAN_TTIR_TXO_Pos)                /*!< 0x00000800 */\n#define FDCAN_TTIR_TXO            FDCAN_TTIR_TXO_Msk                           /*!<Tx Count Overflow                         */\n#define FDCAN_TTIR_SE1_Pos        (12U)\n#define FDCAN_TTIR_SE1_Msk        (0x1UL << FDCAN_TTIR_SE1_Pos)                /*!< 0x00001000 */\n#define FDCAN_TTIR_SE1            FDCAN_TTIR_SE1_Msk                           /*!<Scheduling Error 1                        */\n#define FDCAN_TTIR_SE2_Pos        (13U)\n#define FDCAN_TTIR_SE2_Msk        (0x1UL << FDCAN_TTIR_SE2_Pos)                /*!< 0x00002000 */\n#define FDCAN_TTIR_SE2            FDCAN_TTIR_SE2_Msk                           /*!<Scheduling Error 2                        */\n#define FDCAN_TTIR_ELC_Pos        (14U)\n#define FDCAN_TTIR_ELC_Msk        (0x1UL << FDCAN_TTIR_ELC_Pos)                /*!< 0x00004000 */\n#define FDCAN_TTIR_ELC            FDCAN_TTIR_ELC_Msk                           /*!<Error Level Changed                       */\n#define FDCAN_TTIR_IWT_Pos        (15U)\n#define FDCAN_TTIR_IWT_Msk        (0x1UL << FDCAN_TTIR_IWT_Pos)                /*!< 0x00008000 */\n#define FDCAN_TTIR_IWT            FDCAN_TTIR_IWT_Msk                           /*!<Initialization Watch Trigger              */\n#define FDCAN_TTIR_WT_Pos         (16U)\n#define FDCAN_TTIR_WT_Msk         (0x1UL << FDCAN_TTIR_WT_Pos)                 /*!< 0x00010000 */\n#define FDCAN_TTIR_WT             FDCAN_TTIR_WT_Msk                            /*!<Watch Trigger                             */\n#define FDCAN_TTIR_AW_Pos         (17U)\n#define FDCAN_TTIR_AW_Msk         (0x1UL << FDCAN_TTIR_AW_Pos)                 /*!< 0x00020000 */\n#define FDCAN_TTIR_AW             FDCAN_TTIR_AW_Msk                            /*!<Application Watchdog                      */\n#define FDCAN_TTIR_CER_Pos        (18U)\n#define FDCAN_TTIR_CER_Msk        (0x1UL << FDCAN_TTIR_CER_Pos)                /*!< 0x00040000 */\n#define FDCAN_TTIR_CER            FDCAN_TTIR_CER_Msk                           /*!<Configuration Error                       */\n\n/*****************  Bit definition for FDCAN_TTIE register  ********************/\n#define FDCAN_TTIE_SBCE_Pos       (0U)\n#define FDCAN_TTIE_SBCE_Msk       (0x1UL << FDCAN_TTIE_SBCE_Pos)               /*!< 0x00000001 */\n#define FDCAN_TTIE_SBCE           FDCAN_TTIE_SBCE_Msk                          /*!<Start of Basic Cycle Interrupt Enable             */\n#define FDCAN_TTIE_SMCE_Pos       (1U)\n#define FDCAN_TTIE_SMCE_Msk       (0x1UL << FDCAN_TTIE_SMCE_Pos)               /*!< 0x00000002 */\n#define FDCAN_TTIE_SMCE           FDCAN_TTIE_SMCE_Msk                          /*!<Start of Matrix Cycle Interrupt Enable            */\n#define FDCAN_TTIE_CSME_Pos       (2U)\n#define FDCAN_TTIE_CSME_Msk       (0x1UL << FDCAN_TTIE_CSME_Pos)               /*!< 0x00000004 */\n#define FDCAN_TTIE_CSME           FDCAN_TTIE_CSME_Msk                          /*!<Change of Synchronization Mode Interrupt Enable   */\n#define FDCAN_TTIE_SOGE_Pos       (3U)\n#define FDCAN_TTIE_SOGE_Msk       (0x1UL << FDCAN_TTIE_SOGE_Pos)               /*!< 0x00000008 */\n#define FDCAN_TTIE_SOGE           FDCAN_TTIE_SOGE_Msk                          /*!<Start of Gap Interrupt Enable                     */\n#define FDCAN_TTIE_RTMIE_Pos      (4U)\n#define FDCAN_TTIE_RTMIE_Msk      (0x1UL << FDCAN_TTIE_RTMIE_Pos)              /*!< 0x00000010 */\n#define FDCAN_TTIE_RTMIE          FDCAN_TTIE_RTMIE_Msk                         /*!<Register Time Mark Interrupt Interrupt Enable     */\n#define FDCAN_TTIE_TTMIE_Pos      (5U)\n#define FDCAN_TTIE_TTMIE_Msk      (0x1UL << FDCAN_TTIE_TTMIE_Pos)              /*!< 0x00000020 */\n#define FDCAN_TTIE_TTMIE          FDCAN_TTIE_TTMIE_Msk                         /*!<Trigger Time Mark Event Internal Interrupt Enable */\n#define FDCAN_TTIE_SWEE_Pos       (6U)\n#define FDCAN_TTIE_SWEE_Msk       (0x1UL << FDCAN_TTIE_SWEE_Pos)               /*!< 0x00000040 */\n#define FDCAN_TTIE_SWEE           FDCAN_TTIE_SWEE_Msk                          /*!<Stop Watch Event Interrupt Enable                 */\n#define FDCAN_TTIE_GTWE_Pos       (7U)\n#define FDCAN_TTIE_GTWE_Msk       (0x1UL << FDCAN_TTIE_GTWE_Pos)               /*!< 0x00000080 */\n#define FDCAN_TTIE_GTWE           FDCAN_TTIE_GTWE_Msk                          /*!<Global Time Wrap Interrupt Enable                 */\n#define FDCAN_TTIE_GTDE_Pos       (8U)\n#define FDCAN_TTIE_GTDE_Msk       (0x1UL << FDCAN_TTIE_GTDE_Pos)               /*!< 0x00000100 */\n#define FDCAN_TTIE_GTDE           FDCAN_TTIE_GTDE_Msk                          /*!<Global Time Discontinuity Interrupt Enable        */\n#define FDCAN_TTIE_GTEE_Pos       (9U)\n#define FDCAN_TTIE_GTEE_Msk       (0x1UL << FDCAN_TTIE_GTEE_Pos)               /*!< 0x00000200 */\n#define FDCAN_TTIE_GTEE           FDCAN_TTIE_GTEE_Msk                          /*!<Global Time Error Interrupt Enable                */\n#define FDCAN_TTIE_TXUE_Pos       (10U)\n#define FDCAN_TTIE_TXUE_Msk       (0x1UL << FDCAN_TTIE_TXUE_Pos)               /*!< 0x00000400 */\n#define FDCAN_TTIE_TXUE           FDCAN_TTIE_TXUE_Msk                          /*!<Tx Count Underflow Interrupt Enable               */\n#define FDCAN_TTIE_TXOE_Pos       (11U)\n#define FDCAN_TTIE_TXOE_Msk       (0x1UL << FDCAN_TTIE_TXOE_Pos)               /*!< 0x00000800 */\n#define FDCAN_TTIE_TXOE           FDCAN_TTIE_TXOE_Msk                          /*!<Tx Count Overflow Interrupt Enable                */\n#define FDCAN_TTIE_SE1E_Pos       (12U)\n#define FDCAN_TTIE_SE1E_Msk       (0x1UL << FDCAN_TTIE_SE1E_Pos)               /*!< 0x00001000 */\n#define FDCAN_TTIE_SE1E           FDCAN_TTIE_SE1E_Msk                          /*!<Scheduling Error 1 Interrupt Enable               */\n#define FDCAN_TTIE_SE2E_Pos       (13U)\n#define FDCAN_TTIE_SE2E_Msk       (0x1UL << FDCAN_TTIE_SE2E_Pos)               /*!< 0x00002000 */\n#define FDCAN_TTIE_SE2E           FDCAN_TTIE_SE2E_Msk                          /*!<Scheduling Error 2 Interrupt Enable               */\n#define FDCAN_TTIE_ELCE_Pos       (14U)\n#define FDCAN_TTIE_ELCE_Msk       (0x1UL << FDCAN_TTIE_ELCE_Pos)               /*!< 0x00004000 */\n#define FDCAN_TTIE_ELCE           FDCAN_TTIE_ELCE_Msk                          /*!<Error Level Changed Interrupt Enable              */\n#define FDCAN_TTIE_IWTE_Pos       (15U)\n#define FDCAN_TTIE_IWTE_Msk       (0x1UL << FDCAN_TTIE_IWTE_Pos)               /*!< 0x00008000 */\n#define FDCAN_TTIE_IWTE           FDCAN_TTIE_IWTE_Msk                          /*!<Initialization Watch Trigger Interrupt Enable     */\n#define FDCAN_TTIE_WTE_Pos        (16U)\n#define FDCAN_TTIE_WTE_Msk        (0x1UL << FDCAN_TTIE_WTE_Pos)                /*!< 0x00010000 */\n#define FDCAN_TTIE_WTE            FDCAN_TTIE_WTE_Msk                           /*!<Watch Trigger Interrupt Enable                    */\n#define FDCAN_TTIE_AWE_Pos        (17U)\n#define FDCAN_TTIE_AWE_Msk        (0x1UL << FDCAN_TTIE_AWE_Pos)                /*!< 0x00020000 */\n#define FDCAN_TTIE_AWE            FDCAN_TTIE_AWE_Msk                           /*!<Application Watchdog Interrupt Enable             */\n#define FDCAN_TTIE_CERE_Pos       (18U)\n#define FDCAN_TTIE_CERE_Msk       (0x1UL << FDCAN_TTIE_CERE_Pos)               /*!< 0x00040000 */\n#define FDCAN_TTIE_CERE           FDCAN_TTIE_CERE_Msk                          /*!<Configuration Error Interrupt Enable              */\n\n/*****************  Bit definition for FDCAN_TTILS register  ********************/\n#define FDCAN_TTILS_SBCS_Pos      (0U)\n#define FDCAN_TTILS_SBCS_Msk      (0x1UL << FDCAN_TTILS_SBCS_Pos)              /*!< 0x00000001 */\n#define FDCAN_TTILS_SBCS          FDCAN_TTILS_SBCS_Msk                         /*!<Start of Basic Cycle Interrupt Line               */\n#define FDCAN_TTILS_SMCS_Pos      (1U)\n#define FDCAN_TTILS_SMCS_Msk      (0x1UL << FDCAN_TTILS_SMCS_Pos)              /*!< 0x00000002 */\n#define FDCAN_TTILS_SMCS          FDCAN_TTILS_SMCS_Msk                         /*!<Start of Matrix Cycle Interrupt Line              */\n#define FDCAN_TTILS_CSMS_Pos      (2U)\n#define FDCAN_TTILS_CSMS_Msk      (0x1UL << FDCAN_TTILS_CSMS_Pos)              /*!< 0x00000004 */\n#define FDCAN_TTILS_CSMS          FDCAN_TTILS_CSMS_Msk                         /*!<Change of Synchronization Mode Interrupt Line     */\n#define FDCAN_TTILS_SOGS_Pos      (3U)\n#define FDCAN_TTILS_SOGS_Msk      (0x1UL << FDCAN_TTILS_SOGS_Pos)              /*!< 0x00000008 */\n#define FDCAN_TTILS_SOGS          FDCAN_TTILS_SOGS_Msk                         /*!<Start of Gap Interrupt Line                       */\n#define FDCAN_TTILS_RTMIS_Pos     (4U)\n#define FDCAN_TTILS_RTMIS_Msk     (0x1UL << FDCAN_TTILS_RTMIS_Pos)             /*!< 0x00000010 */\n#define FDCAN_TTILS_RTMIS         FDCAN_TTILS_RTMIS_Msk                        /*!<Register Time Mark Interrupt Interrupt Line       */\n#define FDCAN_TTILS_TTMIS_Pos     (5U)\n#define FDCAN_TTILS_TTMIS_Msk     (0x1UL << FDCAN_TTILS_TTMIS_Pos)             /*!< 0x00000020 */\n#define FDCAN_TTILS_TTMIS         FDCAN_TTILS_TTMIS_Msk                        /*!<Trigger Time Mark Event Internal Interrupt Line   */\n#define FDCAN_TTILS_SWES_Pos      (6U)\n#define FDCAN_TTILS_SWES_Msk      (0x1UL << FDCAN_TTILS_SWES_Pos)              /*!< 0x00000040 */\n#define FDCAN_TTILS_SWES          FDCAN_TTILS_SWES_Msk                         /*!<Stop Watch Event Interrupt Line                   */\n#define FDCAN_TTILS_GTWS_Pos      (7U)\n#define FDCAN_TTILS_GTWS_Msk      (0x1UL << FDCAN_TTILS_GTWS_Pos)              /*!< 0x00000080 */\n#define FDCAN_TTILS_GTWS          FDCAN_TTILS_GTWS_Msk                         /*!<Global Time Wrap Interrupt Line                   */\n#define FDCAN_TTILS_GTDS_Pos      (8U)\n#define FDCAN_TTILS_GTDS_Msk      (0x1UL << FDCAN_TTILS_GTDS_Pos)              /*!< 0x00000100 */\n#define FDCAN_TTILS_GTDS          FDCAN_TTILS_GTDS_Msk                         /*!<Global Time Discontinuity Interrupt Line          */\n#define FDCAN_TTILS_GTES_Pos      (9U)\n#define FDCAN_TTILS_GTES_Msk      (0x1UL << FDCAN_TTILS_GTES_Pos)              /*!< 0x00000200 */\n#define FDCAN_TTILS_GTES          FDCAN_TTILS_GTES_Msk                         /*!<Global Time Error Interrupt Line                  */\n#define FDCAN_TTILS_TXUS_Pos      (10U)\n#define FDCAN_TTILS_TXUS_Msk      (0x1UL << FDCAN_TTILS_TXUS_Pos)              /*!< 0x00000400 */\n#define FDCAN_TTILS_TXUS          FDCAN_TTILS_TXUS_Msk                         /*!<Tx Count Underflow Interrupt Line                 */\n#define FDCAN_TTILS_TXOS_Pos      (11U)\n#define FDCAN_TTILS_TXOS_Msk      (0x1UL << FDCAN_TTILS_TXOS_Pos)              /*!< 0x00000800 */\n#define FDCAN_TTILS_TXOS          FDCAN_TTILS_TXOS_Msk                         /*!<Tx Count Overflow Interrupt Line                  */\n#define FDCAN_TTILS_SE1S_Pos      (12U)\n#define FDCAN_TTILS_SE1S_Msk      (0x1UL << FDCAN_TTILS_SE1S_Pos)              /*!< 0x00001000 */\n#define FDCAN_TTILS_SE1S          FDCAN_TTILS_SE1S_Msk                         /*!<Scheduling Error 1 Interrupt Line                 */\n#define FDCAN_TTILS_SE2S_Pos      (13U)\n#define FDCAN_TTILS_SE2S_Msk      (0x1UL << FDCAN_TTILS_SE2S_Pos)              /*!< 0x00002000 */\n#define FDCAN_TTILS_SE2S          FDCAN_TTILS_SE2S_Msk                         /*!<Scheduling Error 2 Interrupt Line                 */\n#define FDCAN_TTILS_ELCS_Pos      (14U)\n#define FDCAN_TTILS_ELCS_Msk      (0x1UL << FDCAN_TTILS_ELCS_Pos)              /*!< 0x00004000 */\n#define FDCAN_TTILS_ELCS          FDCAN_TTILS_ELCS_Msk                         /*!<Error Level Changed Interrupt Line                */\n#define FDCAN_TTILS_IWTS_Pos      (15U)\n#define FDCAN_TTILS_IWTS_Msk      (0x1UL << FDCAN_TTILS_IWTS_Pos)              /*!< 0x00008000 */\n#define FDCAN_TTILS_IWTS          FDCAN_TTILS_IWTS_Msk                         /*!<Initialization Watch Trigger Interrupt Line       */\n#define FDCAN_TTILS_WTS_Pos       (16U)\n#define FDCAN_TTILS_WTS_Msk       (0x1UL << FDCAN_TTILS_WTS_Pos)               /*!< 0x00010000 */\n#define FDCAN_TTILS_WTS           FDCAN_TTILS_WTS_Msk                          /*!<Watch Trigger Interrupt Line                      */\n#define FDCAN_TTILS_AWS_Pos       (17U)\n#define FDCAN_TTILS_AWS_Msk       (0x1UL << FDCAN_TTILS_AWS_Pos)               /*!< 0x00020000 */\n#define FDCAN_TTILS_AWS           FDCAN_TTILS_AWS_Msk                          /*!<Application Watchdog Interrupt Line               */\n#define FDCAN_TTILS_CERS_Pos      (18U)\n#define FDCAN_TTILS_CERS_Msk      (0x1UL << FDCAN_TTILS_CERS_Pos)              /*!< 0x00040000 */\n#define FDCAN_TTILS_CERS          FDCAN_TTILS_CERS_Msk                         /*!<Configuration Error Interrupt Line                */\n\n/*****************  Bit definition for FDCAN_TTOST register  ********************/\n#define FDCAN_TTOST_EL_Pos        (0U)\n#define FDCAN_TTOST_EL_Msk        (0x3UL << FDCAN_TTOST_EL_Pos)                /*!< 0x00000003 */\n#define FDCAN_TTOST_EL            FDCAN_TTOST_EL_Msk                           /*!<Error Level                              */\n#define FDCAN_TTOST_MS_Pos        (2U)\n#define FDCAN_TTOST_MS_Msk        (0x3UL << FDCAN_TTOST_MS_Pos)                /*!< 0x0000000C */\n#define FDCAN_TTOST_MS            FDCAN_TTOST_MS_Msk                           /*!<Master State                             */\n#define FDCAN_TTOST_SYS_Pos       (4U)\n#define FDCAN_TTOST_SYS_Msk       (0x3UL << FDCAN_TTOST_SYS_Pos)               /*!< 0x00000030 */\n#define FDCAN_TTOST_SYS           FDCAN_TTOST_SYS_Msk                          /*!<Synchronization State                    */\n#define FDCAN_TTOST_QGTP_Pos      (6U)\n#define FDCAN_TTOST_QGTP_Msk      (0x1UL << FDCAN_TTOST_QGTP_Pos)              /*!< 0x00000040 */\n#define FDCAN_TTOST_QGTP          FDCAN_TTOST_QGTP_Msk                         /*!<Quality of Global Time Phase             */\n#define FDCAN_TTOST_QCS_Pos       (7U)\n#define FDCAN_TTOST_QCS_Msk       (0x1UL << FDCAN_TTOST_QCS_Pos)               /*!< 0x00000080 */\n#define FDCAN_TTOST_QCS           FDCAN_TTOST_QCS_Msk                          /*!<Quality of Clock Speed                   */\n#define FDCAN_TTOST_RTO_Pos       (8U)\n#define FDCAN_TTOST_RTO_Msk       (0xFFUL << FDCAN_TTOST_RTO_Pos)              /*!< 0x0000FF00 */\n#define FDCAN_TTOST_RTO           FDCAN_TTOST_RTO_Msk                          /*!<Reference Trigger Offset                 */\n#define FDCAN_TTOST_WGTD_Pos      (22U)\n#define FDCAN_TTOST_WGTD_Msk      (0x1UL << FDCAN_TTOST_WGTD_Pos)              /*!< 0x00400000 */\n#define FDCAN_TTOST_WGTD          FDCAN_TTOST_WGTD_Msk                         /*!<Wait for Global Time Discontinuity       */\n#define FDCAN_TTOST_GFI_Pos       (23U)\n#define FDCAN_TTOST_GFI_Msk       (0x1UL << FDCAN_TTOST_GFI_Pos)               /*!< 0x00800000 */\n#define FDCAN_TTOST_GFI           FDCAN_TTOST_GFI_Msk                          /*!<Gap Finished Indicator                   */\n#define FDCAN_TTOST_TMP_Pos       (24U)\n#define FDCAN_TTOST_TMP_Msk       (0x7UL << FDCAN_TTOST_TMP_Pos)               /*!< 0x07000000 */\n#define FDCAN_TTOST_TMP           FDCAN_TTOST_TMP_Msk                          /*!<Time Master Priority                     */\n#define FDCAN_TTOST_GSI_Pos       (27U)\n#define FDCAN_TTOST_GSI_Msk       (0x1UL << FDCAN_TTOST_GSI_Pos)               /*!< 0x08000000 */\n#define FDCAN_TTOST_GSI           FDCAN_TTOST_GSI_Msk                          /*!<Gap Started Indicator                    */\n#define FDCAN_TTOST_WFE_Pos       (28U)\n#define FDCAN_TTOST_WFE_Msk       (0x1UL << FDCAN_TTOST_WFE_Pos)               /*!< 0x10000000 */\n#define FDCAN_TTOST_WFE           FDCAN_TTOST_WFE_Msk                          /*!<Wait for Event                           */\n#define FDCAN_TTOST_AWE_Pos       (29U)\n#define FDCAN_TTOST_AWE_Msk       (0x1UL << FDCAN_TTOST_AWE_Pos)               /*!< 0x20000000 */\n#define FDCAN_TTOST_AWE           FDCAN_TTOST_AWE_Msk                          /*!<Application Watchdog Event               */\n#define FDCAN_TTOST_WECS_Pos      (30U)\n#define FDCAN_TTOST_WECS_Msk      (0x1UL << FDCAN_TTOST_WECS_Pos)              /*!< 0x40000000 */\n#define FDCAN_TTOST_WECS          FDCAN_TTOST_WECS_Msk                         /*!<Wait for External Clock Synchronization  */\n#define FDCAN_TTOST_SPL_Pos       (31U)\n#define FDCAN_TTOST_SPL_Msk       (0x1UL << FDCAN_TTOST_SPL_Pos)               /*!< 0x80000000 */\n#define FDCAN_TTOST_SPL           FDCAN_TTOST_SPL_Msk                          /*!<Schedule Phase Lock                      */\n\n/*****************  Bit definition for FDCAN_TURNA register  ********************/\n#define FDCAN_TURNA_NAV_Pos       (0U)\n#define FDCAN_TURNA_NAV_Msk       (0x3FFFFUL << FDCAN_TURNA_NAV_Pos)           /*!< 0x0003FFFF */\n#define FDCAN_TURNA_NAV           FDCAN_TURNA_NAV_Msk                          /*!<Numerator Actual Value                   */\n\n/*****************  Bit definition for FDCAN_TTLGT register  ********************/\n#define FDCAN_TTLGT_LT_Pos        (0U)\n#define FDCAN_TTLGT_LT_Msk        (0xFFFFUL << FDCAN_TTLGT_LT_Pos)             /*!< 0x0000FFFF */\n#define FDCAN_TTLGT_LT            FDCAN_TTLGT_LT_Msk                           /*!<Local Time                               */\n#define FDCAN_TTLGT_GT_Pos        (16U)\n#define FDCAN_TTLGT_GT_Msk        (0xFFFFUL << FDCAN_TTLGT_GT_Pos)             /*!< 0xFFFF0000 */\n#define FDCAN_TTLGT_GT            FDCAN_TTLGT_GT_Msk                           /*!<Global Time                              */\n\n/*****************  Bit definition for FDCAN_TTCTC register  ********************/\n#define FDCAN_TTCTC_CT_Pos        (0U)\n#define FDCAN_TTCTC_CT_Msk        (0xFFFFUL << FDCAN_TTCTC_CT_Pos)             /*!< 0x0000FFFF */\n#define FDCAN_TTCTC_CT            FDCAN_TTCTC_CT_Msk                           /*!<Cycle Time                               */\n#define FDCAN_TTCTC_CC_Pos        (16U)\n#define FDCAN_TTCTC_CC_Msk        (0x3FUL << FDCAN_TTCTC_CC_Pos)               /*!< 0x003F0000 */\n#define FDCAN_TTCTC_CC            FDCAN_TTCTC_CC_Msk                           /*!<Cycle Count                              */\n\n/*****************  Bit definition for FDCAN_TTCPT register  ********************/\n#define FDCAN_TTCPT_CCV_Pos       (0U)\n#define FDCAN_TTCPT_CCV_Msk       (0x3FUL << FDCAN_TTCPT_CCV_Pos)              /*!< 0x0000003F */\n#define FDCAN_TTCPT_CCV           FDCAN_TTCPT_CCV_Msk                          /*!<Cycle Count Value                        */\n#define FDCAN_TTCPT_SWV_Pos       (16U)\n#define FDCAN_TTCPT_SWV_Msk       (0xFFFFUL << FDCAN_TTCPT_SWV_Pos)            /*!< 0xFFFF0000 */\n#define FDCAN_TTCPT_SWV           FDCAN_TTCPT_SWV_Msk                          /*!<Stop Watch Value                         */\n\n/*****************  Bit definition for FDCAN_TTCSM register  ********************/\n#define FDCAN_TTCSM_CSM_Pos       (0U)\n#define FDCAN_TTCSM_CSM_Msk       (0xFFFFUL << FDCAN_TTCSM_CSM_Pos)            /*!< 0x0000FFFF */\n#define FDCAN_TTCSM_CSM           FDCAN_TTCSM_CSM_Msk                          /*!<Cycle Sync Mark                          */\n\n/*****************  Bit definition for FDCAN_TTTS register  *********************/\n#define FDCAN_TTTS_SWTSEL_Pos     (0U)\n#define FDCAN_TTTS_SWTSEL_Msk     (0x3UL << FDCAN_TTTS_SWTSEL_Pos)             /*!< 0x00000003 */\n#define FDCAN_TTTS_SWTSEL         FDCAN_TTTS_SWTSEL_Msk                        /*!<Stop watch trigger input selection       */\n#define FDCAN_TTTS_EVTSEL_Pos     (4U)\n#define FDCAN_TTTS_EVTSEL_Msk     (0x3UL << FDCAN_TTTS_EVTSEL_Pos)             /*!< 0x00000030 */\n#define FDCAN_TTTS_EVTSEL         FDCAN_TTTS_EVTSEL_Msk                        /*!<Event trigger input selection            */\n\n/********************************************************************************/\n/*                                                                              */\n/*                      FDCANCCU (Clock Calibration unit)                       */\n/*                                                                              */\n/********************************************************************************/\n\n/*****************  Bit definition for FDCANCCU_CREL register  ******************/\n#define FDCANCCU_CREL_DAY_Pos        (0U)\n#define FDCANCCU_CREL_DAY_Msk        (0xFFUL << FDCANCCU_CREL_DAY_Pos)         /*!< 0x000000FF */\n#define FDCANCCU_CREL_DAY            FDCANCCU_CREL_DAY_Msk                     /*!<Timestamp Day                           */\n#define FDCANCCU_CREL_MON_Pos        (8U)\n#define FDCANCCU_CREL_MON_Msk        (0xFFUL << FDCANCCU_CREL_MON_Pos)         /*!< 0x0000FF00 */\n#define FDCANCCU_CREL_MON            FDCANCCU_CREL_MON_Msk                     /*!<Timestamp Month                         */\n#define FDCANCCU_CREL_YEAR_Pos       (16U)\n#define FDCANCCU_CREL_YEAR_Msk       (0xFUL << FDCANCCU_CREL_YEAR_Pos)         /*!< 0x000F0000 */\n#define FDCANCCU_CREL_YEAR           FDCANCCU_CREL_YEAR_Msk                    /*!<Timestamp Year                          */\n#define FDCANCCU_CREL_SUBSTEP_Pos    (20U)\n#define FDCANCCU_CREL_SUBSTEP_Msk    (0xFUL << FDCANCCU_CREL_SUBSTEP_Pos)      /*!< 0x00F00000 */\n#define FDCANCCU_CREL_SUBSTEP        FDCANCCU_CREL_SUBSTEP_Msk                 /*!<Sub-step of Core release                */\n#define FDCANCCU_CREL_STEP_Pos       (24U)\n#define FDCANCCU_CREL_STEP_Msk       (0xFUL << FDCANCCU_CREL_STEP_Pos)         /*!< 0x0F000000 */\n#define FDCANCCU_CREL_STEP           FDCANCCU_CREL_STEP_Msk                    /*!<Step of Core release                    */\n#define FDCANCCU_CREL_REL_Pos        (28U)\n#define FDCANCCU_CREL_REL_Msk        (0xFUL << FDCANCCU_CREL_REL_Pos)          /*!< 0xF0000000 */\n#define FDCANCCU_CREL_REL            FDCANCCU_CREL_REL_Msk                     /*!<Core release                            */\n\n/*****************  Bit definition for FDCANCCU_CCFG register  ******************/\n#define FDCANCCU_CCFG_TQBT_Pos       (0U)\n#define FDCANCCU_CCFG_TQBT_Msk       (0x1FUL << FDCANCCU_CCFG_TQBT_Pos)        /*!< 0x0000001F */\n#define FDCANCCU_CCFG_TQBT           FDCANCCU_CCFG_TQBT_Msk                    /*!<Time Quanta per Bit Time                */\n#define FDCANCCU_CCFG_BCC_Pos        (6U)\n#define FDCANCCU_CCFG_BCC_Msk        (0x1UL << FDCANCCU_CCFG_BCC_Pos)          /*!< 0x00000040 */\n#define FDCANCCU_CCFG_BCC            FDCANCCU_CCFG_BCC_Msk                     /*!<Bypass Clock Calibration                */\n#define FDCANCCU_CCFG_CFL_Pos        (7U)\n#define FDCANCCU_CCFG_CFL_Msk        (0x1UL << FDCANCCU_CCFG_CFL_Pos)          /*!< 0x00000080 */\n#define FDCANCCU_CCFG_CFL            FDCANCCU_CCFG_CFL_Msk                     /*!<Calibration Field Length                */\n#define FDCANCCU_CCFG_OCPM_Pos       (8U)\n#define FDCANCCU_CCFG_OCPM_Msk       (0xFFUL << FDCANCCU_CCFG_OCPM_Pos)        /*!< 0x0000FF00 */\n#define FDCANCCU_CCFG_OCPM           FDCANCCU_CCFG_OCPM_Msk                    /*!<Oscillator Clock Periods Minimum        */\n#define FDCANCCU_CCFG_CDIV_Pos       (16U)\n#define FDCANCCU_CCFG_CDIV_Msk       (0xFUL << FDCANCCU_CCFG_CDIV_Pos)         /*!< 0x000F0000 */\n#define FDCANCCU_CCFG_CDIV           FDCANCCU_CCFG_CDIV_Msk                    /*!<Clock Divider                           */\n#define FDCANCCU_CCFG_SWR_Pos        (31U)\n#define FDCANCCU_CCFG_SWR_Msk        (0x1UL << FDCANCCU_CCFG_SWR_Pos)          /*!< 0x80000000 */\n#define FDCANCCU_CCFG_SWR            FDCANCCU_CCFG_SWR_Msk                     /*!<Software Reset                          */\n\n/*****************  Bit definition for FDCANCCU_CSTAT register  *****************/\n#define FDCANCCU_CSTAT_OCPC_Pos      (0U)\n#define FDCANCCU_CSTAT_OCPC_Msk      (0x3FFFFUL << FDCANCCU_CSTAT_OCPC_Pos)    /*!< 0x0003FFFF */\n#define FDCANCCU_CSTAT_OCPC          FDCANCCU_CSTAT_OCPC_Msk                   /*!<Oscillator Clock Period Counter        */\n#define FDCANCCU_CSTAT_TQC_Pos       (18U)\n#define FDCANCCU_CSTAT_TQC_Msk       (0x7FFUL << FDCANCCU_CSTAT_TQC_Pos)       /*!< 0x1FFC0000 */\n#define FDCANCCU_CSTAT_TQC           FDCANCCU_CSTAT_TQC_Msk                    /*!<Time Quanta Counter                    */\n#define FDCANCCU_CSTAT_CALS_Pos      (30U)\n#define FDCANCCU_CSTAT_CALS_Msk      (0x3UL << FDCANCCU_CSTAT_CALS_Pos)        /*!< 0xC0000000 */\n#define FDCANCCU_CSTAT_CALS          FDCANCCU_CSTAT_CALS_Msk                   /*!<Calibration State                      */\n\n/******************  Bit definition for FDCANCCU_CWD register  ******************/\n#define FDCANCCU_CWD_WDC_Pos         (0U)\n#define FDCANCCU_CWD_WDC_Msk         (0xFFFFUL << FDCANCCU_CWD_WDC_Pos)        /*!< 0x0000FFFF */\n#define FDCANCCU_CWD_WDC             FDCANCCU_CWD_WDC_Msk                      /*!<Watchdog Configuration                 */\n#define FDCANCCU_CWD_WDV_Pos         (16U)\n#define FDCANCCU_CWD_WDV_Msk         (0xFFFFUL << FDCANCCU_CWD_WDV_Pos)        /*!< 0xFFFF0000 */\n#define FDCANCCU_CWD_WDV             FDCANCCU_CWD_WDV_Msk                      /*!<Watchdog Value                         */\n\n/******************  Bit definition for FDCANCCU_IR register  *******************/\n#define FDCANCCU_IR_CWE_Pos          (0U)\n#define FDCANCCU_IR_CWE_Msk          (0x1UL << FDCANCCU_IR_CWE_Pos)            /*!< 0x00000001 */\n#define FDCANCCU_IR_CWE              FDCANCCU_IR_CWE_Msk                       /*!<Calibration Watchdog Event             */\n#define FDCANCCU_IR_CSC_Pos          (1U)\n#define FDCANCCU_IR_CSC_Msk          (0x1UL << FDCANCCU_IR_CSC_Pos)            /*!< 0x00000002 */\n#define FDCANCCU_IR_CSC              FDCANCCU_IR_CSC_Msk                       /*!<Calibration State Changed              */\n\n/******************  Bit definition for FDCANCCU_IE register  *******************/\n#define FDCANCCU_IE_CWEE_Pos         (0U)\n#define FDCANCCU_IE_CWEE_Msk         (0x1UL << FDCANCCU_IE_CWEE_Pos)           /*!< 0x00000001 */\n#define FDCANCCU_IE_CWEE             FDCANCCU_IE_CWEE_Msk                      /*!<Calibration Watchdog Event Enable      */\n#define FDCANCCU_IE_CSCE_Pos         (1U)\n#define FDCANCCU_IE_CSCE_Msk         (0x1UL << FDCANCCU_IE_CSCE_Pos)           /*!< 0x00000002 */\n#define FDCANCCU_IE_CSCE             FDCANCCU_IE_CSCE_Msk                      /*!<Calibration State Changed Enable       */\n\n/******************************************************************************/\n/*                                                                            */\n/*                          HDMI-CEC (CEC)                                    */\n/*                                                                            */\n/******************************************************************************/\n\n/*******************  Bit definition for CEC_CR register  *********************/\n#define CEC_CR_CECEN_Pos         (0U)\n#define CEC_CR_CECEN_Msk         (0x1UL << CEC_CR_CECEN_Pos)                   /*!< 0x00000001 */\n#define CEC_CR_CECEN             CEC_CR_CECEN_Msk                              /*!< CEC Enable                                */\n#define CEC_CR_TXSOM_Pos         (1U)\n#define CEC_CR_TXSOM_Msk         (0x1UL << CEC_CR_TXSOM_Pos)                   /*!< 0x00000002 */\n#define CEC_CR_TXSOM             CEC_CR_TXSOM_Msk                              /*!< CEC Tx Start Of Message                   */\n#define CEC_CR_TXEOM_Pos         (2U)\n#define CEC_CR_TXEOM_Msk         (0x1UL << CEC_CR_TXEOM_Pos)                   /*!< 0x00000004 */\n#define CEC_CR_TXEOM             CEC_CR_TXEOM_Msk                              /*!< CEC Tx End Of Message                     */\n\n/*******************  Bit definition for CEC_CFGR register  *******************/\n#define CEC_CFGR_SFT_Pos         (0U)\n#define CEC_CFGR_SFT_Msk         (0x7UL << CEC_CFGR_SFT_Pos)                   /*!< 0x00000007 */\n#define CEC_CFGR_SFT             CEC_CFGR_SFT_Msk                              /*!< CEC Signal Free Time                      */\n#define CEC_CFGR_RXTOL_Pos       (3U)\n#define CEC_CFGR_RXTOL_Msk       (0x1UL << CEC_CFGR_RXTOL_Pos)                 /*!< 0x00000008 */\n#define CEC_CFGR_RXTOL           CEC_CFGR_RXTOL_Msk                            /*!< CEC Tolerance                             */\n#define CEC_CFGR_BRESTP_Pos      (4U)\n#define CEC_CFGR_BRESTP_Msk      (0x1UL << CEC_CFGR_BRESTP_Pos)                /*!< 0x00000010 */\n#define CEC_CFGR_BRESTP          CEC_CFGR_BRESTP_Msk                           /*!< CEC Rx Stop                               */\n#define CEC_CFGR_BREGEN_Pos      (5U)\n#define CEC_CFGR_BREGEN_Msk      (0x1UL << CEC_CFGR_BREGEN_Pos)                /*!< 0x00000020 */\n#define CEC_CFGR_BREGEN          CEC_CFGR_BREGEN_Msk                           /*!< CEC Bit Rising Error generation           */\n#define CEC_CFGR_LBPEGEN_Pos     (6U)\n#define CEC_CFGR_LBPEGEN_Msk     (0x1UL << CEC_CFGR_LBPEGEN_Pos)               /*!< 0x00000040 */\n#define CEC_CFGR_LBPEGEN         CEC_CFGR_LBPEGEN_Msk                          /*!< CEC Long Bit Period Error generation      */\n#define CEC_CFGR_SFTOPT_Pos      (8U)\n#define CEC_CFGR_SFTOPT_Msk      (0x1UL << CEC_CFGR_SFTOPT_Pos)                /*!< 0x00000100 */\n#define CEC_CFGR_SFTOPT          CEC_CFGR_SFTOPT_Msk                           /*!< CEC Signal Free Time optional             */\n#define CEC_CFGR_BRDNOGEN_Pos    (7U)\n#define CEC_CFGR_BRDNOGEN_Msk    (0x1UL << CEC_CFGR_BRDNOGEN_Pos)              /*!< 0x00000080 */\n#define CEC_CFGR_BRDNOGEN        CEC_CFGR_BRDNOGEN_Msk                         /*!< CEC Broadcast No error generation         */\n#define CEC_CFGR_OAR_Pos         (16U)\n#define CEC_CFGR_OAR_Msk         (0x7FFFUL << CEC_CFGR_OAR_Pos)                /*!< 0x7FFF0000 */\n#define CEC_CFGR_OAR             CEC_CFGR_OAR_Msk                              /*!< CEC Own Address                           */\n#define CEC_CFGR_LSTN_Pos        (31U)\n#define CEC_CFGR_LSTN_Msk        (0x1UL << CEC_CFGR_LSTN_Pos)                  /*!< 0x80000000 */\n#define CEC_CFGR_LSTN            CEC_CFGR_LSTN_Msk                             /*!< CEC Listen mode                           */\n\n/*******************  Bit definition for CEC_TXDR register  *******************/\n#define CEC_TXDR_TXD_Pos         (0U)\n#define CEC_TXDR_TXD_Msk         (0xFFUL << CEC_TXDR_TXD_Pos)                  /*!< 0x000000FF */\n#define CEC_TXDR_TXD             CEC_TXDR_TXD_Msk                              /*!< CEC Tx Data                               */\n\n/*******************  Bit definition for CEC_RXDR register  *******************/\n#define CEC_RXDR_RXD_Pos         (0U)\n#define CEC_RXDR_RXD_Msk         (0xFFUL << CEC_RXDR_RXD_Pos)                  /*!< 0x000000FF */\n#define CEC_RXDR_RXD             CEC_RXDR_RXD_Msk                              /*!< CEC Rx Data                               */\n\n/*******************  Bit definition for CEC_ISR register  ********************/\n#define CEC_ISR_RXBR_Pos         (0U)\n#define CEC_ISR_RXBR_Msk         (0x1UL << CEC_ISR_RXBR_Pos)                   /*!< 0x00000001 */\n#define CEC_ISR_RXBR             CEC_ISR_RXBR_Msk                              /*!< CEC Rx-Byte Received                      */\n#define CEC_ISR_RXEND_Pos        (1U)\n#define CEC_ISR_RXEND_Msk        (0x1UL << CEC_ISR_RXEND_Pos)                  /*!< 0x00000002 */\n#define CEC_ISR_RXEND            CEC_ISR_RXEND_Msk                             /*!< CEC End Of Reception                      */\n#define CEC_ISR_RXOVR_Pos        (2U)\n#define CEC_ISR_RXOVR_Msk        (0x1UL << CEC_ISR_RXOVR_Pos)                  /*!< 0x00000004 */\n#define CEC_ISR_RXOVR            CEC_ISR_RXOVR_Msk                             /*!< CEC Rx-Overrun                            */\n#define CEC_ISR_BRE_Pos          (3U)\n#define CEC_ISR_BRE_Msk          (0x1UL << CEC_ISR_BRE_Pos)                    /*!< 0x00000008 */\n#define CEC_ISR_BRE              CEC_ISR_BRE_Msk                               /*!< CEC Rx Bit Rising Error                   */\n#define CEC_ISR_SBPE_Pos         (4U)\n#define CEC_ISR_SBPE_Msk         (0x1UL << CEC_ISR_SBPE_Pos)                   /*!< 0x00000010 */\n#define CEC_ISR_SBPE             CEC_ISR_SBPE_Msk                              /*!< CEC Rx Short Bit period Error             */\n#define CEC_ISR_LBPE_Pos         (5U)\n#define CEC_ISR_LBPE_Msk         (0x1UL << CEC_ISR_LBPE_Pos)                   /*!< 0x00000020 */\n#define CEC_ISR_LBPE             CEC_ISR_LBPE_Msk                              /*!< CEC Rx Long Bit period Error              */\n#define CEC_ISR_RXACKE_Pos       (6U)\n#define CEC_ISR_RXACKE_Msk       (0x1UL << CEC_ISR_RXACKE_Pos)                 /*!< 0x00000040 */\n#define CEC_ISR_RXACKE           CEC_ISR_RXACKE_Msk                            /*!< CEC Rx Missing Acknowledge                */\n#define CEC_ISR_ARBLST_Pos       (7U)\n#define CEC_ISR_ARBLST_Msk       (0x1UL << CEC_ISR_ARBLST_Pos)                 /*!< 0x00000080 */\n#define CEC_ISR_ARBLST           CEC_ISR_ARBLST_Msk                            /*!< CEC Arbitration Lost                      */\n#define CEC_ISR_TXBR_Pos         (8U)\n#define CEC_ISR_TXBR_Msk         (0x1UL << CEC_ISR_TXBR_Pos)                   /*!< 0x00000100 */\n#define CEC_ISR_TXBR             CEC_ISR_TXBR_Msk                              /*!< CEC Tx Byte Request                       */\n#define CEC_ISR_TXEND_Pos        (9U)\n#define CEC_ISR_TXEND_Msk        (0x1UL << CEC_ISR_TXEND_Pos)                  /*!< 0x00000200 */\n#define CEC_ISR_TXEND            CEC_ISR_TXEND_Msk                             /*!< CEC End of Transmission                   */\n#define CEC_ISR_TXUDR_Pos        (10U)\n#define CEC_ISR_TXUDR_Msk        (0x1UL << CEC_ISR_TXUDR_Pos)                  /*!< 0x00000400 */\n#define CEC_ISR_TXUDR            CEC_ISR_TXUDR_Msk                             /*!< CEC Tx-Buffer Underrun                    */\n#define CEC_ISR_TXERR_Pos        (11U)\n#define CEC_ISR_TXERR_Msk        (0x1UL << CEC_ISR_TXERR_Pos)                  /*!< 0x00000800 */\n#define CEC_ISR_TXERR            CEC_ISR_TXERR_Msk                             /*!< CEC Tx-Error                              */\n#define CEC_ISR_TXACKE_Pos       (12U)\n#define CEC_ISR_TXACKE_Msk       (0x1UL << CEC_ISR_TXACKE_Pos)                 /*!< 0x00001000 */\n#define CEC_ISR_TXACKE           CEC_ISR_TXACKE_Msk                            /*!< CEC Tx Missing Acknowledge                */\n\n/*******************  Bit definition for CEC_IER register  ********************/\n#define CEC_IER_RXBRIE_Pos       (0U)\n#define CEC_IER_RXBRIE_Msk       (0x1UL << CEC_IER_RXBRIE_Pos)                 /*!< 0x00000001 */\n#define CEC_IER_RXBRIE           CEC_IER_RXBRIE_Msk                            /*!< CEC Rx-Byte Received IT Enable            */\n#define CEC_IER_RXENDIE_Pos      (1U)\n#define CEC_IER_RXENDIE_Msk      (0x1UL << CEC_IER_RXENDIE_Pos)                /*!< 0x00000002 */\n#define CEC_IER_RXENDIE          CEC_IER_RXENDIE_Msk                           /*!< CEC End Of Reception IT Enable            */\n#define CEC_IER_RXOVRIE_Pos      (2U)\n#define CEC_IER_RXOVRIE_Msk      (0x1UL << CEC_IER_RXOVRIE_Pos)                /*!< 0x00000004 */\n#define CEC_IER_RXOVRIE          CEC_IER_RXOVRIE_Msk                           /*!< CEC Rx-Overrun IT Enable                  */\n#define CEC_IER_BREIE_Pos        (3U)\n#define CEC_IER_BREIE_Msk        (0x1UL << CEC_IER_BREIE_Pos)                  /*!< 0x00000008 */\n#define CEC_IER_BREIE            CEC_IER_BREIE_Msk                             /*!< CEC Rx Bit Rising Error IT Enable         */\n#define CEC_IER_SBPEIE_Pos       (4U)\n#define CEC_IER_SBPEIE_Msk       (0x1UL << CEC_IER_SBPEIE_Pos)                 /*!< 0x00000010 */\n#define CEC_IER_SBPEIE           CEC_IER_SBPEIE_Msk                            /*!< CEC Rx Short Bit period Error IT Enable   */\n#define CEC_IER_LBPEIE_Pos       (5U)\n#define CEC_IER_LBPEIE_Msk       (0x1UL << CEC_IER_LBPEIE_Pos)                 /*!< 0x00000020 */\n#define CEC_IER_LBPEIE           CEC_IER_LBPEIE_Msk                            /*!< CEC Rx Long Bit period Error IT Enable    */\n#define CEC_IER_RXACKEIE_Pos     (6U)\n#define CEC_IER_RXACKEIE_Msk     (0x1UL << CEC_IER_RXACKEIE_Pos)               /*!< 0x00000040 */\n#define CEC_IER_RXACKEIE         CEC_IER_RXACKEIE_Msk                          /*!< CEC Rx Missing Acknowledge IT Enable      */\n#define CEC_IER_ARBLSTIE_Pos     (7U)\n#define CEC_IER_ARBLSTIE_Msk     (0x1UL << CEC_IER_ARBLSTIE_Pos)               /*!< 0x00000080 */\n#define CEC_IER_ARBLSTIE         CEC_IER_ARBLSTIE_Msk                          /*!< CEC Arbitration Lost IT Enable            */\n#define CEC_IER_TXBRIE_Pos       (8U)\n#define CEC_IER_TXBRIE_Msk       (0x1UL << CEC_IER_TXBRIE_Pos)                 /*!< 0x00000100 */\n#define CEC_IER_TXBRIE           CEC_IER_TXBRIE_Msk                            /*!< CEC Tx Byte Request  IT Enable            */\n#define CEC_IER_TXENDIE_Pos      (9U)\n#define CEC_IER_TXENDIE_Msk      (0x1UL << CEC_IER_TXENDIE_Pos)                /*!< 0x00000200 */\n#define CEC_IER_TXENDIE          CEC_IER_TXENDIE_Msk                           /*!< CEC End of Transmission IT Enable         */\n#define CEC_IER_TXUDRIE_Pos      (10U)\n#define CEC_IER_TXUDRIE_Msk      (0x1UL << CEC_IER_TXUDRIE_Pos)                /*!< 0x00000400 */\n#define CEC_IER_TXUDRIE          CEC_IER_TXUDRIE_Msk                           /*!< CEC Tx-Buffer Underrun IT Enable          */\n#define CEC_IER_TXERRIE_Pos      (11U)\n#define CEC_IER_TXERRIE_Msk      (0x1UL << CEC_IER_TXERRIE_Pos)                /*!< 0x00000800 */\n#define CEC_IER_TXERRIE          CEC_IER_TXERRIE_Msk                           /*!< CEC Tx-Error IT Enable                    */\n#define CEC_IER_TXACKEIE_Pos     (12U)\n#define CEC_IER_TXACKEIE_Msk     (0x1UL << CEC_IER_TXACKEIE_Pos)               /*!< 0x00001000 */\n#define CEC_IER_TXACKEIE         CEC_IER_TXACKEIE_Msk                          /*!< CEC Tx Missing Acknowledge IT Enable      */\n\n/******************************************************************************/\n/*                                                                            */\n/*                          CRC calculation unit                              */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for CRC_DR register  *********************/\n#define CRC_DR_DR_Pos            (0U)\n#define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)               /*!< 0xFFFFFFFF */\n#define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */\n\n/*******************  Bit definition for CRC_IDR register  ********************/\n#define CRC_IDR_IDR_Pos          (0U)\n#define CRC_IDR_IDR_Msk          (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)             /*!< 0xFFFFFFFF */\n#define CRC_IDR_IDR              CRC_IDR_IDR_Msk                               /*!< General-purpose 32-bit data register bits */\n\n/********************  Bit definition for CRC_CR register  ********************/\n#define CRC_CR_RESET_Pos         (0U)\n#define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                   /*!< 0x00000001 */\n#define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */\n#define CRC_CR_POLYSIZE_Pos      (3U)\n#define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000018 */\n#define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */\n#define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */\n#define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */\n#define CRC_CR_REV_IN_Pos        (5U)\n#define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000060 */\n#define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */\n#define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */\n#define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */\n#define CRC_CR_REV_OUT_Pos       (7U)\n#define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                 /*!< 0x00000080 */\n#define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */\n\n/*******************  Bit definition for CRC_INIT register  *******************/\n#define CRC_INIT_INIT_Pos        (0U)\n#define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)           /*!< 0xFFFFFFFF */\n#define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */\n\n/*******************  Bit definition for CRC_POL register  ********************/\n#define CRC_POL_POL_Pos          (0U)\n#define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)             /*!< 0xFFFFFFFF */\n#define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */\n\n/******************************************************************************/\n/*                                                                            */\n/*                          CRS Clock Recovery System                         */\n/******************************************************************************/\n\n/*******************  Bit definition for CRS_CR register  *********************/\n#define CRS_CR_SYNCOKIE_Pos       (0U)\n#define CRS_CR_SYNCOKIE_Msk       (0x1UL << CRS_CR_SYNCOKIE_Pos)               /*!< 0x00000001 */\n#define CRS_CR_SYNCOKIE           CRS_CR_SYNCOKIE_Msk                          /*!< SYNC event OK interrupt enable */\n#define CRS_CR_SYNCWARNIE_Pos     (1U)\n#define CRS_CR_SYNCWARNIE_Msk     (0x1UL << CRS_CR_SYNCWARNIE_Pos)             /*!< 0x00000002 */\n#define CRS_CR_SYNCWARNIE         CRS_CR_SYNCWARNIE_Msk                        /*!< SYNC warning interrupt enable */\n#define CRS_CR_ERRIE_Pos          (2U)\n#define CRS_CR_ERRIE_Msk          (0x1UL << CRS_CR_ERRIE_Pos)                  /*!< 0x00000004 */\n#define CRS_CR_ERRIE              CRS_CR_ERRIE_Msk                             /*!< SYNC error or trimming error interrupt enable */\n#define CRS_CR_ESYNCIE_Pos        (3U)\n#define CRS_CR_ESYNCIE_Msk        (0x1UL << CRS_CR_ESYNCIE_Pos)                /*!< 0x00000008 */\n#define CRS_CR_ESYNCIE            CRS_CR_ESYNCIE_Msk                           /*!< Expected SYNC interrupt enable */\n#define CRS_CR_CEN_Pos            (5U)\n#define CRS_CR_CEN_Msk            (0x1UL << CRS_CR_CEN_Pos)                    /*!< 0x00000020 */\n#define CRS_CR_CEN                CRS_CR_CEN_Msk                               /*!< Frequency error counter enable */\n#define CRS_CR_AUTOTRIMEN_Pos     (6U)\n#define CRS_CR_AUTOTRIMEN_Msk     (0x1UL << CRS_CR_AUTOTRIMEN_Pos)             /*!< 0x00000040 */\n#define CRS_CR_AUTOTRIMEN         CRS_CR_AUTOTRIMEN_Msk                        /*!< Automatic trimming enable */\n#define CRS_CR_SWSYNC_Pos         (7U)\n#define CRS_CR_SWSYNC_Msk         (0x1UL << CRS_CR_SWSYNC_Pos)                 /*!< 0x00000080 */\n#define CRS_CR_SWSYNC             CRS_CR_SWSYNC_Msk                            /*!< Generate software SYNC event */\n#define CRS_CR_TRIM_Pos           (8U)\n#define CRS_CR_TRIM_Msk           (0x3FUL << CRS_CR_TRIM_Pos)                  /*!< 0x00003F00 */\n#define CRS_CR_TRIM               CRS_CR_TRIM_Msk                              /*!< HSI48 oscillator smooth trimming */\n\n/*******************  Bit definition for CRS_CFGR register  *********************/\n#define CRS_CFGR_RELOAD_Pos       (0U)\n#define CRS_CFGR_RELOAD_Msk       (0xFFFFUL << CRS_CFGR_RELOAD_Pos)            /*!< 0x0000FFFF */\n#define CRS_CFGR_RELOAD           CRS_CFGR_RELOAD_Msk                          /*!< Counter reload value */\n#define CRS_CFGR_FELIM_Pos        (16U)\n#define CRS_CFGR_FELIM_Msk        (0xFFUL << CRS_CFGR_FELIM_Pos)               /*!< 0x00FF0000 */\n#define CRS_CFGR_FELIM            CRS_CFGR_FELIM_Msk                           /*!< Frequency error limit */\n\n#define CRS_CFGR_SYNCDIV_Pos      (24U)\n#define CRS_CFGR_SYNCDIV_Msk      (0x7UL << CRS_CFGR_SYNCDIV_Pos)              /*!< 0x07000000 */\n#define CRS_CFGR_SYNCDIV          CRS_CFGR_SYNCDIV_Msk                         /*!< SYNC divider */\n#define CRS_CFGR_SYNCDIV_0        (0x1UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x01000000 */\n#define CRS_CFGR_SYNCDIV_1        (0x2UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x02000000 */\n#define CRS_CFGR_SYNCDIV_2        (0x4UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x04000000 */\n\n#define CRS_CFGR_SYNCSRC_Pos      (28U)\n#define CRS_CFGR_SYNCSRC_Msk      (0x3UL << CRS_CFGR_SYNCSRC_Pos)              /*!< 0x30000000 */\n#define CRS_CFGR_SYNCSRC          CRS_CFGR_SYNCSRC_Msk                         /*!< SYNC signal source selection */\n#define CRS_CFGR_SYNCSRC_0        (0x1UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x10000000 */\n#define CRS_CFGR_SYNCSRC_1        (0x2UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x20000000 */\n\n#define CRS_CFGR_SYNCPOL_Pos      (31U)\n#define CRS_CFGR_SYNCPOL_Msk      (0x1UL << CRS_CFGR_SYNCPOL_Pos)              /*!< 0x80000000 */\n#define CRS_CFGR_SYNCPOL          CRS_CFGR_SYNCPOL_Msk                         /*!< SYNC polarity selection */\n\n/*******************  Bit definition for CRS_ISR register  *********************/\n#define CRS_ISR_SYNCOKF_Pos       (0U)\n#define CRS_ISR_SYNCOKF_Msk       (0x1UL << CRS_ISR_SYNCOKF_Pos)               /*!< 0x00000001 */\n#define CRS_ISR_SYNCOKF           CRS_ISR_SYNCOKF_Msk                          /*!< SYNC event OK flag */\n#define CRS_ISR_SYNCWARNF_Pos     (1U)\n#define CRS_ISR_SYNCWARNF_Msk     (0x1UL << CRS_ISR_SYNCWARNF_Pos)             /*!< 0x00000002 */\n#define CRS_ISR_SYNCWARNF         CRS_ISR_SYNCWARNF_Msk                        /*!< SYNC warning flag */\n#define CRS_ISR_ERRF_Pos          (2U)\n#define CRS_ISR_ERRF_Msk          (0x1UL << CRS_ISR_ERRF_Pos)                  /*!< 0x00000004 */\n#define CRS_ISR_ERRF              CRS_ISR_ERRF_Msk                             /*!< Error flag */\n#define CRS_ISR_ESYNCF_Pos        (3U)\n#define CRS_ISR_ESYNCF_Msk        (0x1UL << CRS_ISR_ESYNCF_Pos)                /*!< 0x00000008 */\n#define CRS_ISR_ESYNCF            CRS_ISR_ESYNCF_Msk                           /*!< Expected SYNC flag */\n#define CRS_ISR_SYNCERR_Pos       (8U)\n#define CRS_ISR_SYNCERR_Msk       (0x1UL << CRS_ISR_SYNCERR_Pos)               /*!< 0x00000100 */\n#define CRS_ISR_SYNCERR           CRS_ISR_SYNCERR_Msk                          /*!< SYNC error */\n#define CRS_ISR_SYNCMISS_Pos      (9U)\n#define CRS_ISR_SYNCMISS_Msk      (0x1UL << CRS_ISR_SYNCMISS_Pos)              /*!< 0x00000200 */\n#define CRS_ISR_SYNCMISS          CRS_ISR_SYNCMISS_Msk                         /*!< SYNC missed */\n#define CRS_ISR_TRIMOVF_Pos       (10U)\n#define CRS_ISR_TRIMOVF_Msk       (0x1UL << CRS_ISR_TRIMOVF_Pos)               /*!< 0x00000400 */\n#define CRS_ISR_TRIMOVF           CRS_ISR_TRIMOVF_Msk                          /*!< Trimming overflow or underflow */\n#define CRS_ISR_FEDIR_Pos         (15U)\n#define CRS_ISR_FEDIR_Msk         (0x1UL << CRS_ISR_FEDIR_Pos)                 /*!< 0x00008000 */\n#define CRS_ISR_FEDIR             CRS_ISR_FEDIR_Msk                            /*!< Frequency error direction */\n#define CRS_ISR_FECAP_Pos         (16U)\n#define CRS_ISR_FECAP_Msk         (0xFFFFUL << CRS_ISR_FECAP_Pos)              /*!< 0xFFFF0000 */\n#define CRS_ISR_FECAP             CRS_ISR_FECAP_Msk                            /*!< Frequency error capture */\n\n/*******************  Bit definition for CRS_ICR register  *********************/\n#define CRS_ICR_SYNCOKC_Pos       (0U)\n#define CRS_ICR_SYNCOKC_Msk       (0x1UL << CRS_ICR_SYNCOKC_Pos)               /*!< 0x00000001 */\n#define CRS_ICR_SYNCOKC           CRS_ICR_SYNCOKC_Msk                          /*!< SYNC event OK clear flag */\n#define CRS_ICR_SYNCWARNC_Pos     (1U)\n#define CRS_ICR_SYNCWARNC_Msk     (0x1UL << CRS_ICR_SYNCWARNC_Pos)             /*!< 0x00000002 */\n#define CRS_ICR_SYNCWARNC         CRS_ICR_SYNCWARNC_Msk                        /*!< SYNC warning clear flag */\n#define CRS_ICR_ERRC_Pos          (2U)\n#define CRS_ICR_ERRC_Msk          (0x1UL << CRS_ICR_ERRC_Pos)                  /*!< 0x00000004 */\n#define CRS_ICR_ERRC              CRS_ICR_ERRC_Msk                             /*!< Error clear flag */\n#define CRS_ICR_ESYNCC_Pos        (3U)\n#define CRS_ICR_ESYNCC_Msk        (0x1UL << CRS_ICR_ESYNCC_Pos)                /*!< 0x00000008 */\n#define CRS_ICR_ESYNCC            CRS_ICR_ESYNCC_Msk                           /*!< Expected SYNC clear flag */\n\n/******************************************************************************/\n/*                                                                            */\n/*                      Digital to Analog Converter                           */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for DAC_CR register  ********************/\n#define DAC_CR_EN1_Pos              (0U)\n#define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                  /*!< 0x00000001 */\n#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */\n#define DAC_CR_TEN1_Pos             (1U)\n#define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                 /*!< 0x00000002 */\n#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */\n\n#define DAC_CR_TSEL1_Pos            (2U)\n#define DAC_CR_TSEL1_Msk            (0xFUL << DAC_CR_TSEL1_Pos)                /*!< 0x0000003C */\n#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */\n#define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000004 */\n#define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */\n#define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */\n#define DAC_CR_TSEL1_3              (0x8UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */\n\n\n#define DAC_CR_WAVE1_Pos            (6U)\n#define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                /*!< 0x000000C0 */\n#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */\n#define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */\n#define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */\n\n#define DAC_CR_MAMP1_Pos            (8U)\n#define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                /*!< 0x00000F00 */\n#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */\n#define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */\n#define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */\n#define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */\n#define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */\n\n#define DAC_CR_DMAEN1_Pos           (12U)\n#define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)               /*!< 0x00001000 */\n#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */\n#define DAC_CR_DMAUDRIE1_Pos        (13U)\n#define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)            /*!< 0x00002000 */\n#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel 1 DMA underrun interrupt enable  >*/\n#define DAC_CR_CEN1_Pos             (14U)\n#define DAC_CR_CEN1_Msk             (0x1UL << DAC_CR_CEN1_Pos)                 /*!< 0x00004000 */\n#define DAC_CR_CEN1                 DAC_CR_CEN1_Msk                            /*!<DAC channel 1 calibration enable >*/\n\n#define DAC_CR_EN2_Pos              (16U)\n#define DAC_CR_EN2_Msk              (0x1UL << DAC_CR_EN2_Pos)                  /*!< 0x00010000 */\n#define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */\n#define DAC_CR_TEN2_Pos             (17U)\n#define DAC_CR_TEN2_Msk             (0x1UL << DAC_CR_TEN2_Pos)                 /*!< 0x00020000 */\n#define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */\n\n#define DAC_CR_TSEL2_Pos            (18U)\n#define DAC_CR_TSEL2_Msk            (0xFUL << DAC_CR_TSEL2_Pos)                /*!< 0x003C0000 */\n#define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */\n#define DAC_CR_TSEL2_0              (0x1UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00040000 */\n#define DAC_CR_TSEL2_1              (0x2UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */\n#define DAC_CR_TSEL2_2              (0x4UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */\n#define DAC_CR_TSEL2_3              (0x8UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */\n\n\n#define DAC_CR_WAVE2_Pos            (22U)\n#define DAC_CR_WAVE2_Msk            (0x3UL << DAC_CR_WAVE2_Pos)                /*!< 0x00C00000 */\n#define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */\n#define DAC_CR_WAVE2_0              (0x1UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */\n#define DAC_CR_WAVE2_1              (0x2UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */\n\n#define DAC_CR_MAMP2_Pos            (24U)\n#define DAC_CR_MAMP2_Msk            (0xFUL << DAC_CR_MAMP2_Pos)                /*!< 0x0F000000 */\n#define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */\n#define DAC_CR_MAMP2_0              (0x1UL << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */\n#define DAC_CR_MAMP2_1              (0x2UL << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */\n#define DAC_CR_MAMP2_2              (0x4UL << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */\n#define DAC_CR_MAMP2_3              (0x8UL << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */\n\n#define DAC_CR_DMAEN2_Pos           (28U)\n#define DAC_CR_DMAEN2_Msk           (0x1UL << DAC_CR_DMAEN2_Pos)               /*!< 0x10000000 */\n#define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */\n#define DAC_CR_DMAUDRIE2_Pos        (29U)\n#define DAC_CR_DMAUDRIE2_Msk        (0x1UL << DAC_CR_DMAUDRIE2_Pos)            /*!< 0x20000000 */\n#define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable  >*/\n#define DAC_CR_CEN2_Pos             (30U)\n#define DAC_CR_CEN2_Msk             (0x1UL << DAC_CR_CEN2_Pos)                 /*!< 0x40000000 */\n#define DAC_CR_CEN2                 DAC_CR_CEN2_Msk                            /*!<DAC channel2 calibration enable >*/\n\n/*****************  Bit definition for DAC_SWTRIGR register  ******************/\n#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)\n#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)         /*!< 0x00000001 */\n#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */\n#define DAC_SWTRIGR_SWTRIG2_Pos     (1U)\n#define DAC_SWTRIGR_SWTRIG2_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)         /*!< 0x00000002 */\n#define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */\n\n/*****************  Bit definition for DAC_DHR12R1 register  ******************/\n#define DAC_DHR12R1_DACC1DHR_Pos    (0U)\n#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)      /*!< 0x00000FFF */\n#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */\n\n/*****************  Bit definition for DAC_DHR12L1 register  ******************/\n#define DAC_DHR12L1_DACC1DHR_Pos    (4U)\n#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)      /*!< 0x0000FFF0 */\n#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */\n\n/******************  Bit definition for DAC_DHR8R1 register  ******************/\n#define DAC_DHR8R1_DACC1DHR_Pos     (0U)\n#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)        /*!< 0x000000FF */\n#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */\n\n/*****************  Bit definition for DAC_DHR12R2 register  ******************/\n#define DAC_DHR12R2_DACC2DHR_Pos    (0U)\n#define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)      /*!< 0x00000FFF */\n#define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */\n\n/*****************  Bit definition for DAC_DHR12L2 register  ******************/\n#define DAC_DHR12L2_DACC2DHR_Pos    (4U)\n#define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)      /*!< 0x0000FFF0 */\n#define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */\n\n/******************  Bit definition for DAC_DHR8R2 register  ******************/\n#define DAC_DHR8R2_DACC2DHR_Pos     (0U)\n#define DAC_DHR8R2_DACC2DHR_Msk     (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)        /*!< 0x000000FF */\n#define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */\n\n/*****************  Bit definition for DAC_DHR12RD register  ******************/\n#define DAC_DHR12RD_DACC1DHR_Pos    (0U)\n#define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)      /*!< 0x00000FFF */\n#define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */\n#define DAC_DHR12RD_DACC2DHR_Pos    (16U)\n#define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)      /*!< 0x0FFF0000 */\n#define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */\n\n/*****************  Bit definition for DAC_DHR12LD register  ******************/\n#define DAC_DHR12LD_DACC1DHR_Pos    (4U)\n#define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)      /*!< 0x0000FFF0 */\n#define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */\n#define DAC_DHR12LD_DACC2DHR_Pos    (20U)\n#define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)      /*!< 0xFFF00000 */\n#define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */\n\n/******************  Bit definition for DAC_DHR8RD register  ******************/\n#define DAC_DHR8RD_DACC1DHR_Pos     (0U)\n#define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)        /*!< 0x000000FF */\n#define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */\n#define DAC_DHR8RD_DACC2DHR_Pos     (8U)\n#define DAC_DHR8RD_DACC2DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)        /*!< 0x0000FF00 */\n#define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */\n\n/*******************  Bit definition for DAC_DOR1 register  *******************/\n#define DAC_DOR1_DACC1DOR_Pos       (0U)\n#define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)         /*!< 0x00000FFF */\n#define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */\n\n/*******************  Bit definition for DAC_DOR2 register  *******************/\n#define DAC_DOR2_DACC2DOR_Pos       (0U)\n#define DAC_DOR2_DACC2DOR_Msk       (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)         /*!< 0x00000FFF */\n#define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */\n\n/********************  Bit definition for DAC_SR register  ********************/\n#define DAC_SR_DMAUDR1_Pos          (13U)\n#define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)              /*!< 0x00002000 */\n#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */\n#define DAC_SR_CAL_FLAG1_Pos        (14U)\n#define DAC_SR_CAL_FLAG1_Msk        (0x1UL << DAC_SR_CAL_FLAG1_Pos)            /*!< 0x00004000 */\n#define DAC_SR_CAL_FLAG1            DAC_SR_CAL_FLAG1_Msk                       /*!<DAC channel1 calibration offset status */\n#define DAC_SR_BWST1_Pos            (15U)\n#define DAC_SR_BWST1_Msk            (0x4001UL << DAC_SR_BWST1_Pos)             /*!< 0x20008000 */\n#define DAC_SR_BWST1                DAC_SR_BWST1_Msk                           /*!<DAC channel1 busy writing sample time flag */\n\n#define DAC_SR_DMAUDR2_Pos          (29U)\n#define DAC_SR_DMAUDR2_Msk          (0x1UL << DAC_SR_DMAUDR2_Pos)              /*!< 0x20000000 */\n#define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */\n#define DAC_SR_CAL_FLAG2_Pos        (30U)\n#define DAC_SR_CAL_FLAG2_Msk        (0x1UL << DAC_SR_CAL_FLAG2_Pos)            /*!< 0x40000000 */\n#define DAC_SR_CAL_FLAG2            DAC_SR_CAL_FLAG2_Msk                       /*!<DAC channel2 calibration offset status */\n#define DAC_SR_BWST2_Pos            (31U)\n#define DAC_SR_BWST2_Msk            (0x1UL << DAC_SR_BWST2_Pos)                /*!< 0x80000000 */\n#define DAC_SR_BWST2                DAC_SR_BWST2_Msk                           /*!<DAC channel2 busy writing sample time flag */\n\n/*******************  Bit definition for DAC_CCR register  ********************/\n#define DAC_CCR_OTRIM1_Pos          (0U)\n#define DAC_CCR_OTRIM1_Msk          (0x1FUL << DAC_CCR_OTRIM1_Pos)             /*!< 0x0000001F */\n#define DAC_CCR_OTRIM1              DAC_CCR_OTRIM1_Msk                         /*!<DAC channel1 offset trimming value */\n#define DAC_CCR_OTRIM2_Pos          (16U)\n#define DAC_CCR_OTRIM2_Msk          (0x1FUL << DAC_CCR_OTRIM2_Pos)             /*!< 0x001F0000 */\n#define DAC_CCR_OTRIM2              DAC_CCR_OTRIM2_Msk                         /*!<DAC channel2 offset trimming value */\n\n/*******************  Bit definition for DAC_MCR register  *******************/\n#define DAC_MCR_MODE1_Pos           (0U)\n#define DAC_MCR_MODE1_Msk           (0x7UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000007 */\n#define DAC_MCR_MODE1               DAC_MCR_MODE1_Msk                          /*!<MODE1[2:0] (DAC channel1 mode) */\n#define DAC_MCR_MODE1_0             (0x1UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000001 */\n#define DAC_MCR_MODE1_1             (0x2UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000002 */\n#define DAC_MCR_MODE1_2             (0x4UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000004 */\n\n#define DAC_MCR_MODE2_Pos           (16U)\n#define DAC_MCR_MODE2_Msk           (0x7UL << DAC_MCR_MODE2_Pos)               /*!< 0x00070000 */\n#define DAC_MCR_MODE2               DAC_MCR_MODE2_Msk                          /*!<MODE2[2:0] (DAC channel2 mode) */\n#define DAC_MCR_MODE2_0             (0x1UL << DAC_MCR_MODE2_Pos)                /*!< 0x00010000 */\n#define DAC_MCR_MODE2_1             (0x2UL << DAC_MCR_MODE2_Pos)                /*!< 0x00020000 */\n#define DAC_MCR_MODE2_2             (0x4UL << DAC_MCR_MODE2_Pos)                /*!< 0x00040000 */\n\n/******************  Bit definition for DAC_SHSR1 register  ******************/\n#define DAC_SHSR1_TSAMPLE1_Pos      (0U)\n#define DAC_SHSR1_TSAMPLE1_Msk      (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos)        /*!< 0x000003FF */\n#define DAC_SHSR1_TSAMPLE1          DAC_SHSR1_TSAMPLE1_Msk                     /*!<DAC channel1 sample time */\n\n/******************  Bit definition for DAC_SHSR2 register  ******************/\n#define DAC_SHSR2_TSAMPLE2_Pos      (0U)\n#define DAC_SHSR2_TSAMPLE2_Msk      (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos)        /*!< 0x000003FF */\n#define DAC_SHSR2_TSAMPLE2          DAC_SHSR2_TSAMPLE2_Msk                     /*!<DAC channel2 sample time */\n\n/******************  Bit definition for DAC_SHHR register  ******************/\n#define DAC_SHHR_THOLD1_Pos         (0U)\n#define DAC_SHHR_THOLD1_Msk         (0x3FFUL << DAC_SHHR_THOLD1_Pos)           /*!< 0x000003FF */\n#define DAC_SHHR_THOLD1             DAC_SHHR_THOLD1_Msk                        /*!<DAC channel1 hold time */\n#define DAC_SHHR_THOLD2_Pos         (16U)\n#define DAC_SHHR_THOLD2_Msk         (0x3FFUL << DAC_SHHR_THOLD2_Pos)           /*!< 0x03FF0000 */\n#define DAC_SHHR_THOLD2             DAC_SHHR_THOLD2_Msk                        /*!<DAC channel2 hold time */\n\n/******************  Bit definition for DAC_SHRR register  ******************/\n#define DAC_SHRR_TREFRESH1_Pos      (0U)\n#define DAC_SHRR_TREFRESH1_Msk      (0xFFUL << DAC_SHRR_TREFRESH1_Pos)         /*!< 0x000000FF */\n#define DAC_SHRR_TREFRESH1          DAC_SHRR_TREFRESH1_Msk                     /*!<DAC channel1 refresh time */\n#define DAC_SHRR_TREFRESH2_Pos      (16U)\n#define DAC_SHRR_TREFRESH2_Msk      (0xFFUL << DAC_SHRR_TREFRESH2_Pos)         /*!< 0x00FF0000 */\n#define DAC_SHRR_TREFRESH2          DAC_SHRR_TREFRESH2_Msk                     /*!<DAC channel2 refresh time */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                    DCMI                                    */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bits definition for DCMI_CR register  ******************/\n#define DCMI_CR_CAPTURE_Pos        (0U)\n#define DCMI_CR_CAPTURE_Msk        (0x1UL << DCMI_CR_CAPTURE_Pos)              /*!< 0x00000001 */\n#define DCMI_CR_CAPTURE            DCMI_CR_CAPTURE_Msk\n#define DCMI_CR_CM_Pos             (1U)\n#define DCMI_CR_CM_Msk             (0x1UL << DCMI_CR_CM_Pos)                   /*!< 0x00000002 */\n#define DCMI_CR_CM                 DCMI_CR_CM_Msk\n#define DCMI_CR_CROP_Pos           (2U)\n#define DCMI_CR_CROP_Msk           (0x1UL << DCMI_CR_CROP_Pos)                 /*!< 0x00000004 */\n#define DCMI_CR_CROP               DCMI_CR_CROP_Msk\n#define DCMI_CR_JPEG_Pos           (3U)\n#define DCMI_CR_JPEG_Msk           (0x1UL << DCMI_CR_JPEG_Pos)                 /*!< 0x00000008 */\n#define DCMI_CR_JPEG               DCMI_CR_JPEG_Msk\n#define DCMI_CR_ESS_Pos            (4U)\n#define DCMI_CR_ESS_Msk            (0x1UL << DCMI_CR_ESS_Pos)                  /*!< 0x00000010 */\n#define DCMI_CR_ESS                DCMI_CR_ESS_Msk\n#define DCMI_CR_PCKPOL_Pos         (5U)\n#define DCMI_CR_PCKPOL_Msk         (0x1UL << DCMI_CR_PCKPOL_Pos)               /*!< 0x00000020 */\n#define DCMI_CR_PCKPOL             DCMI_CR_PCKPOL_Msk\n#define DCMI_CR_HSPOL_Pos          (6U)\n#define DCMI_CR_HSPOL_Msk          (0x1UL << DCMI_CR_HSPOL_Pos)                /*!< 0x00000040 */\n#define DCMI_CR_HSPOL              DCMI_CR_HSPOL_Msk\n#define DCMI_CR_VSPOL_Pos          (7U)\n#define DCMI_CR_VSPOL_Msk          (0x1UL << DCMI_CR_VSPOL_Pos)                /*!< 0x00000080 */\n#define DCMI_CR_VSPOL              DCMI_CR_VSPOL_Msk\n#define DCMI_CR_FCRC_0             ((uint32_t)0x00000100U)\n#define DCMI_CR_FCRC_1             ((uint32_t)0x00000200U)\n#define DCMI_CR_EDM_0              ((uint32_t)0x00000400U)\n#define DCMI_CR_EDM_1              ((uint32_t)0x00000800U)\n#define DCMI_CR_CRE_Pos            (12U)\n#define DCMI_CR_CRE_Msk            (0x1UL << DCMI_CR_CRE_Pos)                  /*!< 0x00001000 */\n#define DCMI_CR_CRE                DCMI_CR_CRE_Msk\n#define DCMI_CR_ENABLE_Pos         (14U)\n#define DCMI_CR_ENABLE_Msk         (0x1UL << DCMI_CR_ENABLE_Pos)               /*!< 0x00004000 */\n#define DCMI_CR_ENABLE             DCMI_CR_ENABLE_Msk\n#define DCMI_CR_BSM_Pos            (16U)\n#define DCMI_CR_BSM_Msk            (0x3UL << DCMI_CR_BSM_Pos)                  /*!< 0x00030000 */\n#define DCMI_CR_BSM                DCMI_CR_BSM_Msk\n#define DCMI_CR_BSM_0              (0x1UL << DCMI_CR_BSM_Pos)                   /*!< 0x00010000 */\n#define DCMI_CR_BSM_1              (0x2UL << DCMI_CR_BSM_Pos)                   /*!< 0x00020000 */\n#define DCMI_CR_OEBS_Pos           (18U)\n#define DCMI_CR_OEBS_Msk           (0x1UL << DCMI_CR_OEBS_Pos)                 /*!< 0x00040000 */\n#define DCMI_CR_OEBS               DCMI_CR_OEBS_Msk\n#define DCMI_CR_LSM_Pos            (19U)\n#define DCMI_CR_LSM_Msk            (0x1UL << DCMI_CR_LSM_Pos)                  /*!< 0x00080000 */\n#define DCMI_CR_LSM                DCMI_CR_LSM_Msk\n#define DCMI_CR_OELS_Pos           (20U)\n#define DCMI_CR_OELS_Msk           (0x1UL << DCMI_CR_OELS_Pos)                 /*!< 0x00100000 */\n#define DCMI_CR_OELS               DCMI_CR_OELS_Msk\n\n/********************  Bits definition for DCMI_SR register  ******************/\n#define DCMI_SR_HSYNC_Pos          (0U)\n#define DCMI_SR_HSYNC_Msk          (0x1UL << DCMI_SR_HSYNC_Pos)                /*!< 0x00000001 */\n#define DCMI_SR_HSYNC              DCMI_SR_HSYNC_Msk\n#define DCMI_SR_VSYNC_Pos          (1U)\n#define DCMI_SR_VSYNC_Msk          (0x1UL << DCMI_SR_VSYNC_Pos)                /*!< 0x00000002 */\n#define DCMI_SR_VSYNC              DCMI_SR_VSYNC_Msk\n#define DCMI_SR_FNE_Pos            (2U)\n#define DCMI_SR_FNE_Msk            (0x1UL << DCMI_SR_FNE_Pos)                  /*!< 0x00000004 */\n#define DCMI_SR_FNE                DCMI_SR_FNE_Msk\n\n/********************  Bits definition for DCMI_RIS register   ****************/\n#define DCMI_RIS_FRAME_RIS_Pos     (0U)\n#define DCMI_RIS_FRAME_RIS_Msk     (0x1UL << DCMI_RIS_FRAME_RIS_Pos)           /*!< 0x00000001 */\n#define DCMI_RIS_FRAME_RIS         DCMI_RIS_FRAME_RIS_Msk\n#define DCMI_RIS_OVR_RIS_Pos       (1U)\n#define DCMI_RIS_OVR_RIS_Msk       (0x1UL << DCMI_RIS_OVR_RIS_Pos)             /*!< 0x00000002 */\n#define DCMI_RIS_OVR_RIS           DCMI_RIS_OVR_RIS_Msk\n#define DCMI_RIS_ERR_RIS_Pos       (2U)\n#define DCMI_RIS_ERR_RIS_Msk       (0x1UL << DCMI_RIS_ERR_RIS_Pos)             /*!< 0x00000004 */\n#define DCMI_RIS_ERR_RIS           DCMI_RIS_ERR_RIS_Msk\n#define DCMI_RIS_VSYNC_RIS_Pos     (3U)\n#define DCMI_RIS_VSYNC_RIS_Msk     (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)           /*!< 0x00000008 */\n#define DCMI_RIS_VSYNC_RIS         DCMI_RIS_VSYNC_RIS_Msk\n#define DCMI_RIS_LINE_RIS_Pos      (4U)\n#define DCMI_RIS_LINE_RIS_Msk      (0x1UL << DCMI_RIS_LINE_RIS_Pos)            /*!< 0x00000010 */\n#define DCMI_RIS_LINE_RIS          DCMI_RIS_LINE_RIS_Msk\n\n/********************  Bits definition for DCMI_IER register  *****************/\n#define DCMI_IER_FRAME_IE_Pos      (0U)\n#define DCMI_IER_FRAME_IE_Msk      (0x1UL << DCMI_IER_FRAME_IE_Pos)            /*!< 0x00000001 */\n#define DCMI_IER_FRAME_IE          DCMI_IER_FRAME_IE_Msk\n#define DCMI_IER_OVR_IE_Pos        (1U)\n#define DCMI_IER_OVR_IE_Msk        (0x1UL << DCMI_IER_OVR_IE_Pos)              /*!< 0x00000002 */\n#define DCMI_IER_OVR_IE            DCMI_IER_OVR_IE_Msk\n#define DCMI_IER_ERR_IE_Pos        (2U)\n#define DCMI_IER_ERR_IE_Msk        (0x1UL << DCMI_IER_ERR_IE_Pos)              /*!< 0x00000004 */\n#define DCMI_IER_ERR_IE            DCMI_IER_ERR_IE_Msk\n#define DCMI_IER_VSYNC_IE_Pos      (3U)\n#define DCMI_IER_VSYNC_IE_Msk      (0x1UL << DCMI_IER_VSYNC_IE_Pos)            /*!< 0x00000008 */\n#define DCMI_IER_VSYNC_IE          DCMI_IER_VSYNC_IE_Msk\n#define DCMI_IER_LINE_IE_Pos       (4U)\n#define DCMI_IER_LINE_IE_Msk       (0x1UL << DCMI_IER_LINE_IE_Pos)             /*!< 0x00000010 */\n#define DCMI_IER_LINE_IE           DCMI_IER_LINE_IE_Msk\n\n\n/********************  Bits definition for DCMI_MIS register  *****************/\n#define DCMI_MIS_FRAME_MIS_Pos     (0U)\n#define DCMI_MIS_FRAME_MIS_Msk     (0x1UL << DCMI_MIS_FRAME_MIS_Pos)           /*!< 0x00000001 */\n#define DCMI_MIS_FRAME_MIS         DCMI_MIS_FRAME_MIS_Msk\n#define DCMI_MIS_OVR_MIS_Pos       (1U)\n#define DCMI_MIS_OVR_MIS_Msk       (0x1UL << DCMI_MIS_OVR_MIS_Pos)             /*!< 0x00000002 */\n#define DCMI_MIS_OVR_MIS           DCMI_MIS_OVR_MIS_Msk\n#define DCMI_MIS_ERR_MIS_Pos       (2U)\n#define DCMI_MIS_ERR_MIS_Msk       (0x1UL << DCMI_MIS_ERR_MIS_Pos)             /*!< 0x00000004 */\n#define DCMI_MIS_ERR_MIS           DCMI_MIS_ERR_MIS_Msk\n#define DCMI_MIS_VSYNC_MIS_Pos     (3U)\n#define DCMI_MIS_VSYNC_MIS_Msk     (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)           /*!< 0x00000008 */\n#define DCMI_MIS_VSYNC_MIS         DCMI_MIS_VSYNC_MIS_Msk\n#define DCMI_MIS_LINE_MIS_Pos      (4U)\n#define DCMI_MIS_LINE_MIS_Msk      (0x1UL << DCMI_MIS_LINE_MIS_Pos)            /*!< 0x00000010 */\n#define DCMI_MIS_LINE_MIS          DCMI_MIS_LINE_MIS_Msk\n\n\n/********************  Bits definition for DCMI_ICR register  *****************/\n#define DCMI_ICR_FRAME_ISC_Pos     (0U)\n#define DCMI_ICR_FRAME_ISC_Msk     (0x1UL << DCMI_ICR_FRAME_ISC_Pos)           /*!< 0x00000001 */\n#define DCMI_ICR_FRAME_ISC         DCMI_ICR_FRAME_ISC_Msk\n#define DCMI_ICR_OVR_ISC_Pos       (1U)\n#define DCMI_ICR_OVR_ISC_Msk       (0x1UL << DCMI_ICR_OVR_ISC_Pos)             /*!< 0x00000002 */\n#define DCMI_ICR_OVR_ISC           DCMI_ICR_OVR_ISC_Msk\n#define DCMI_ICR_ERR_ISC_Pos       (2U)\n#define DCMI_ICR_ERR_ISC_Msk       (0x1UL << DCMI_ICR_ERR_ISC_Pos)             /*!< 0x00000004 */\n#define DCMI_ICR_ERR_ISC           DCMI_ICR_ERR_ISC_Msk\n#define DCMI_ICR_VSYNC_ISC_Pos     (3U)\n#define DCMI_ICR_VSYNC_ISC_Msk     (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)           /*!< 0x00000008 */\n#define DCMI_ICR_VSYNC_ISC         DCMI_ICR_VSYNC_ISC_Msk\n#define DCMI_ICR_LINE_ISC_Pos      (4U)\n#define DCMI_ICR_LINE_ISC_Msk      (0x1UL << DCMI_ICR_LINE_ISC_Pos)            /*!< 0x00000010 */\n#define DCMI_ICR_LINE_ISC          DCMI_ICR_LINE_ISC_Msk\n\n\n/********************  Bits definition for DCMI_ESCR register  ******************/\n#define DCMI_ESCR_FSC_Pos          (0U)\n#define DCMI_ESCR_FSC_Msk          (0xFFUL << DCMI_ESCR_FSC_Pos)               /*!< 0x000000FF */\n#define DCMI_ESCR_FSC              DCMI_ESCR_FSC_Msk\n#define DCMI_ESCR_LSC_Pos          (8U)\n#define DCMI_ESCR_LSC_Msk          (0xFFUL << DCMI_ESCR_LSC_Pos)               /*!< 0x0000FF00 */\n#define DCMI_ESCR_LSC              DCMI_ESCR_LSC_Msk\n#define DCMI_ESCR_LEC_Pos          (16U)\n#define DCMI_ESCR_LEC_Msk          (0xFFUL << DCMI_ESCR_LEC_Pos)               /*!< 0x00FF0000 */\n#define DCMI_ESCR_LEC              DCMI_ESCR_LEC_Msk\n#define DCMI_ESCR_FEC_Pos          (24U)\n#define DCMI_ESCR_FEC_Msk          (0xFFUL << DCMI_ESCR_FEC_Pos)               /*!< 0xFF000000 */\n#define DCMI_ESCR_FEC              DCMI_ESCR_FEC_Msk\n\n/********************  Bits definition for DCMI_ESUR register  ******************/\n#define DCMI_ESUR_FSU_Pos          (0U)\n#define DCMI_ESUR_FSU_Msk          (0xFFUL << DCMI_ESUR_FSU_Pos)               /*!< 0x000000FF */\n#define DCMI_ESUR_FSU              DCMI_ESUR_FSU_Msk\n#define DCMI_ESUR_LSU_Pos          (8U)\n#define DCMI_ESUR_LSU_Msk          (0xFFUL << DCMI_ESUR_LSU_Pos)               /*!< 0x0000FF00 */\n#define DCMI_ESUR_LSU              DCMI_ESUR_LSU_Msk\n#define DCMI_ESUR_LEU_Pos          (16U)\n#define DCMI_ESUR_LEU_Msk          (0xFFUL << DCMI_ESUR_LEU_Pos)               /*!< 0x00FF0000 */\n#define DCMI_ESUR_LEU              DCMI_ESUR_LEU_Msk\n#define DCMI_ESUR_FEU_Pos          (24U)\n#define DCMI_ESUR_FEU_Msk          (0xFFUL << DCMI_ESUR_FEU_Pos)               /*!< 0xFF000000 */\n#define DCMI_ESUR_FEU              DCMI_ESUR_FEU_Msk\n\n/********************  Bits definition for DCMI_CWSTRT register  ******************/\n#define DCMI_CWSTRT_HOFFCNT_Pos    (0U)\n#define DCMI_CWSTRT_HOFFCNT_Msk    (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)       /*!< 0x00003FFF */\n#define DCMI_CWSTRT_HOFFCNT        DCMI_CWSTRT_HOFFCNT_Msk\n#define DCMI_CWSTRT_VST_Pos        (16U)\n#define DCMI_CWSTRT_VST_Msk        (0x1FFFUL << DCMI_CWSTRT_VST_Pos)           /*!< 0x1FFF0000 */\n#define DCMI_CWSTRT_VST            DCMI_CWSTRT_VST_Msk\n\n/********************  Bits definition for DCMI_CWSIZE register  ******************/\n#define DCMI_CWSIZE_CAPCNT_Pos     (0U)\n#define DCMI_CWSIZE_CAPCNT_Msk     (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)        /*!< 0x00003FFF */\n#define DCMI_CWSIZE_CAPCNT         DCMI_CWSIZE_CAPCNT_Msk\n#define DCMI_CWSIZE_VLINE_Pos      (16U)\n#define DCMI_CWSIZE_VLINE_Msk      (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)         /*!< 0x3FFF0000 */\n#define DCMI_CWSIZE_VLINE          DCMI_CWSIZE_VLINE_Msk\n\n/********************  Bits definition for DCMI_DR register  ******************/\n#define DCMI_DR_BYTE0_Pos          (0U)\n#define DCMI_DR_BYTE0_Msk          (0xFFUL << DCMI_DR_BYTE0_Pos)               /*!< 0x000000FF */\n#define DCMI_DR_BYTE0              DCMI_DR_BYTE0_Msk\n#define DCMI_DR_BYTE1_Pos          (8U)\n#define DCMI_DR_BYTE1_Msk          (0xFFUL << DCMI_DR_BYTE1_Pos)               /*!< 0x0000FF00 */\n#define DCMI_DR_BYTE1              DCMI_DR_BYTE1_Msk\n#define DCMI_DR_BYTE2_Pos          (16U)\n#define DCMI_DR_BYTE2_Msk          (0xFFUL << DCMI_DR_BYTE2_Pos)               /*!< 0x00FF0000 */\n#define DCMI_DR_BYTE2              DCMI_DR_BYTE2_Msk\n#define DCMI_DR_BYTE3_Pos          (24U)\n#define DCMI_DR_BYTE3_Msk          (0xFFUL << DCMI_DR_BYTE3_Pos)               /*!< 0xFF000000 */\n#define DCMI_DR_BYTE3              DCMI_DR_BYTE3_Msk\n\n/******************************************************************************/\n/*                                                                            */\n/*                 Digital Filter for Sigma Delta Modulators                  */\n/*                                                                            */\n/******************************************************************************/\n\n/****************   DFSDM channel configuration registers  ********************/\n\n/***************  Bit definition for DFSDM_CHCFGR1 register  ******************/\n#define DFSDM_CHCFGR1_DFSDMEN_Pos       (31U)\n#define DFSDM_CHCFGR1_DFSDMEN_Msk       (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos)   /*!< 0x80000000 */\n#define DFSDM_CHCFGR1_DFSDMEN           DFSDM_CHCFGR1_DFSDMEN_Msk              /*!< Global enable for DFSDM interface */\n#define DFSDM_CHCFGR1_CKOUTSRC_Pos      (30U)\n#define DFSDM_CHCFGR1_CKOUTSRC_Msk      (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos)  /*!< 0x40000000 */\n#define DFSDM_CHCFGR1_CKOUTSRC          DFSDM_CHCFGR1_CKOUTSRC_Msk             /*!< Output serial clock source selection */\n#define DFSDM_CHCFGR1_CKOUTDIV_Pos      (16U)\n#define DFSDM_CHCFGR1_CKOUTDIV_Msk      (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */\n#define DFSDM_CHCFGR1_CKOUTDIV          DFSDM_CHCFGR1_CKOUTDIV_Msk             /*!< CKOUTDIV[7:0] output serial clock divider */\n#define DFSDM_CHCFGR1_DATPACK_Pos       (14U)\n#define DFSDM_CHCFGR1_DATPACK_Msk       (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos)   /*!< 0x0000C000 */\n#define DFSDM_CHCFGR1_DATPACK           DFSDM_CHCFGR1_DATPACK_Msk              /*!< DATPACK[1:0] Data packing mode */\n#define DFSDM_CHCFGR1_DATPACK_1         (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00008000 */\n#define DFSDM_CHCFGR1_DATPACK_0         (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00004000 */\n#define DFSDM_CHCFGR1_DATMPX_Pos        (12U)\n#define DFSDM_CHCFGR1_DATMPX_Msk        (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos)    /*!< 0x00003000 */\n#define DFSDM_CHCFGR1_DATMPX            DFSDM_CHCFGR1_DATMPX_Msk               /*!< DATMPX[1:0] Input data multiplexer for channel y */\n#define DFSDM_CHCFGR1_DATMPX_1          (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00002000 */\n#define DFSDM_CHCFGR1_DATMPX_0          (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00001000 */\n#define DFSDM_CHCFGR1_CHINSEL_Pos       (8U)\n#define DFSDM_CHCFGR1_CHINSEL_Msk       (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos)   /*!< 0x00000100 */\n#define DFSDM_CHCFGR1_CHINSEL           DFSDM_CHCFGR1_CHINSEL_Msk              /*!< Serial inputs selection for channel y */\n#define DFSDM_CHCFGR1_CHEN_Pos          (7U)\n#define DFSDM_CHCFGR1_CHEN_Msk          (0x1UL << DFSDM_CHCFGR1_CHEN_Pos)      /*!< 0x00000080 */\n#define DFSDM_CHCFGR1_CHEN              DFSDM_CHCFGR1_CHEN_Msk                 /*!< Channel y enable */\n#define DFSDM_CHCFGR1_CKABEN_Pos        (6U)\n#define DFSDM_CHCFGR1_CKABEN_Msk        (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos)    /*!< 0x00000040 */\n#define DFSDM_CHCFGR1_CKABEN            DFSDM_CHCFGR1_CKABEN_Msk               /*!< Clock absence detector enable on channel y */\n#define DFSDM_CHCFGR1_SCDEN_Pos         (5U)\n#define DFSDM_CHCFGR1_SCDEN_Msk         (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos)     /*!< 0x00000020 */\n#define DFSDM_CHCFGR1_SCDEN             DFSDM_CHCFGR1_SCDEN_Msk                /*!< Short circuit detector enable on channel y */\n#define DFSDM_CHCFGR1_SPICKSEL_Pos      (2U)\n#define DFSDM_CHCFGR1_SPICKSEL_Msk      (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos)  /*!< 0x0000000C */\n#define DFSDM_CHCFGR1_SPICKSEL          DFSDM_CHCFGR1_SPICKSEL_Msk             /*!< SPICKSEL[1:0] SPI clock select for channel y */\n#define DFSDM_CHCFGR1_SPICKSEL_1        (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000008 */\n#define DFSDM_CHCFGR1_SPICKSEL_0        (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000004 */\n#define DFSDM_CHCFGR1_SITP_Pos          (0U)\n#define DFSDM_CHCFGR1_SITP_Msk          (0x3UL << DFSDM_CHCFGR1_SITP_Pos)      /*!< 0x00000003 */\n#define DFSDM_CHCFGR1_SITP              DFSDM_CHCFGR1_SITP_Msk                 /*!< SITP[1:0] Serial interface type for channel y */\n#define DFSDM_CHCFGR1_SITP_1            (0x2UL << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000002 */\n#define DFSDM_CHCFGR1_SITP_0            (0x1UL << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000001 */\n\n/***************  Bit definition for DFSDM_CHCFGR2 register  ******************/\n#define DFSDM_CHCFGR2_OFFSET_Pos        (8U)\n#define DFSDM_CHCFGR2_OFFSET_Msk        (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */\n#define DFSDM_CHCFGR2_OFFSET            DFSDM_CHCFGR2_OFFSET_Msk               /*!< OFFSET[23:0] 24-bit calibration offset for channel y */\n#define DFSDM_CHCFGR2_DTRBS_Pos         (3U)\n#define DFSDM_CHCFGR2_DTRBS_Msk         (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos)    /*!< 0x000000F8 */\n#define DFSDM_CHCFGR2_DTRBS             DFSDM_CHCFGR2_DTRBS_Msk                /*!< DTRBS[4:0] Data right bit-shift for channel y */\n\n/******************  Bit definition for DFSDM_CHAWSCDR register *****************/\n#define DFSDM_CHAWSCDR_AWFORD_Pos       (22U)\n#define DFSDM_CHAWSCDR_AWFORD_Msk       (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos)   /*!< 0x00C00000 */\n#define DFSDM_CHAWSCDR_AWFORD           DFSDM_CHAWSCDR_AWFORD_Msk              /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */\n#define DFSDM_CHAWSCDR_AWFORD_1         (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00800000 */\n#define DFSDM_CHAWSCDR_AWFORD_0         (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00400000 */\n#define DFSDM_CHAWSCDR_AWFOSR_Pos       (16U)\n#define DFSDM_CHAWSCDR_AWFOSR_Msk       (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos)  /*!< 0x001F0000 */\n#define DFSDM_CHAWSCDR_AWFOSR           DFSDM_CHAWSCDR_AWFOSR_Msk              /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */\n#define DFSDM_CHAWSCDR_BKSCD_Pos        (12U)\n#define DFSDM_CHAWSCDR_BKSCD_Msk        (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos)    /*!< 0x0000F000 */\n#define DFSDM_CHAWSCDR_BKSCD            DFSDM_CHAWSCDR_BKSCD_Msk               /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */\n#define DFSDM_CHAWSCDR_SCDT_Pos         (0U)\n#define DFSDM_CHAWSCDR_SCDT_Msk         (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos)    /*!< 0x000000FF */\n#define DFSDM_CHAWSCDR_SCDT             DFSDM_CHAWSCDR_SCDT_Msk                /*!< SCDT[7:0] Short circuit detector threshold for channel y */\n\n/****************  Bit definition for DFSDM_CHWDATR register *******************/\n#define DFSDM_CHWDATR_WDATA_Pos         (0U)\n#define DFSDM_CHWDATR_WDATA_Msk         (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos)  /*!< 0x0000FFFF */\n#define DFSDM_CHWDATR_WDATA             DFSDM_CHWDATR_WDATA_Msk                /*!< WDATA[15:0] Input channel y watchdog data */\n\n/****************  Bit definition for DFSDM_CHDATINR register *****************/\n#define DFSDM_CHDATINR_INDAT0_Pos       (0U)\n#define DFSDM_CHDATINR_INDAT0_Msk       (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */\n#define DFSDM_CHDATINR_INDAT0           DFSDM_CHDATINR_INDAT0_Msk              /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */\n#define DFSDM_CHDATINR_INDAT1_Pos       (16U)\n#define DFSDM_CHDATINR_INDAT1_Msk       (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */\n#define DFSDM_CHDATINR_INDAT1           DFSDM_CHDATINR_INDAT1_Msk              /*!< INDAT0[15:0] Input data for channel y */\n\n/************************   DFSDM module registers  ****************************/\n\n/********************  Bit definition for DFSDM_FLTCR1 register *******************/\n#define DFSDM_FLTCR1_AWFSEL_Pos         (30U)\n#define DFSDM_FLTCR1_AWFSEL_Msk         (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos)     /*!< 0x40000000 */\n#define DFSDM_FLTCR1_AWFSEL             DFSDM_FLTCR1_AWFSEL_Msk                /*!< Analog watchdog fast mode select */\n#define DFSDM_FLTCR1_FAST_Pos           (29U)\n#define DFSDM_FLTCR1_FAST_Msk           (0x1UL << DFSDM_FLTCR1_FAST_Pos)       /*!< 0x20000000 */\n#define DFSDM_FLTCR1_FAST               DFSDM_FLTCR1_FAST_Msk                  /*!< Fast conversion mode selection */\n#define DFSDM_FLTCR1_RCH_Pos            (24U)\n#define DFSDM_FLTCR1_RCH_Msk            (0x7UL << DFSDM_FLTCR1_RCH_Pos)        /*!< 0x07000000 */\n#define DFSDM_FLTCR1_RCH                DFSDM_FLTCR1_RCH_Msk                   /*!< RCH[2:0] Regular channel selection */\n#define DFSDM_FLTCR1_RDMAEN_Pos         (21U)\n#define DFSDM_FLTCR1_RDMAEN_Msk         (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos)     /*!< 0x00200000 */\n#define DFSDM_FLTCR1_RDMAEN             DFSDM_FLTCR1_RDMAEN_Msk                /*!< DMA channel enabled to read data for the regular conversion */\n#define DFSDM_FLTCR1_RSYNC_Pos          (19U)\n#define DFSDM_FLTCR1_RSYNC_Msk          (0x1UL << DFSDM_FLTCR1_RSYNC_Pos)      /*!< 0x00080000 */\n#define DFSDM_FLTCR1_RSYNC              DFSDM_FLTCR1_RSYNC_Msk                 /*!< Launch regular conversion synchronously with DFSDMx */\n#define DFSDM_FLTCR1_RCONT_Pos          (18U)\n#define DFSDM_FLTCR1_RCONT_Msk          (0x1UL << DFSDM_FLTCR1_RCONT_Pos)      /*!< 0x00040000 */\n#define DFSDM_FLTCR1_RCONT              DFSDM_FLTCR1_RCONT_Msk                 /*!< Continuous mode selection for regular conversions */\n#define DFSDM_FLTCR1_RSWSTART_Pos       (17U)\n#define DFSDM_FLTCR1_RSWSTART_Msk       (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos)   /*!< 0x00020000 */\n#define DFSDM_FLTCR1_RSWSTART           DFSDM_FLTCR1_RSWSTART_Msk              /*!< Software start of a conversion on the regular channel */\n#define DFSDM_FLTCR1_JEXTEN_Pos         (13U)\n#define DFSDM_FLTCR1_JEXTEN_Msk         (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos)     /*!< 0x00006000 */\n#define DFSDM_FLTCR1_JEXTEN             DFSDM_FLTCR1_JEXTEN_Msk                /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */\n#define DFSDM_FLTCR1_JEXTEN_1           (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00004000 */\n#define DFSDM_FLTCR1_JEXTEN_0           (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00002000 */\n#define DFSDM_FLTCR1_JEXTSEL_Pos        (8U)\n#define DFSDM_FLTCR1_JEXTSEL_Msk        (0x1FUL << DFSDM_FLTCR1_JEXTSEL_Pos)   /*!< 0x00001F00 */\n#define DFSDM_FLTCR1_JEXTSEL            DFSDM_FLTCR1_JEXTSEL_Msk               /*!< JEXTSEL[4:0]Trigger signal selection for launching injected conversions */\n#define DFSDM_FLTCR1_JEXTSEL_0          (0x01UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000100 */\n#define DFSDM_FLTCR1_JEXTSEL_1          (0x02UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000200 */\n#define DFSDM_FLTCR1_JEXTSEL_2          (0x04UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000400 */\n#define DFSDM_FLTCR1_JEXTSEL_3          (0x08UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000800 */\n#define DFSDM_FLTCR1_JEXTSEL_4          (0x10UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00001000 */\n\n#define DFSDM_FLTCR1_JDMAEN_Pos         (5U)\n#define DFSDM_FLTCR1_JDMAEN_Msk         (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos)     /*!< 0x00000020 */\n#define DFSDM_FLTCR1_JDMAEN             DFSDM_FLTCR1_JDMAEN_Msk                /*!< DMA channel enabled to read data for the injected channel group */\n#define DFSDM_FLTCR1_JSCAN_Pos          (4U)\n#define DFSDM_FLTCR1_JSCAN_Msk          (0x1UL << DFSDM_FLTCR1_JSCAN_Pos)      /*!< 0x00000010 */\n#define DFSDM_FLTCR1_JSCAN              DFSDM_FLTCR1_JSCAN_Msk                 /*!< Scanning conversion in continuous mode selection for injected conversions */\n#define DFSDM_FLTCR1_JSYNC_Pos          (3U)\n#define DFSDM_FLTCR1_JSYNC_Msk          (0x1UL << DFSDM_FLTCR1_JSYNC_Pos)      /*!< 0x00000008 */\n#define DFSDM_FLTCR1_JSYNC              DFSDM_FLTCR1_JSYNC_Msk                 /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger  */\n#define DFSDM_FLTCR1_JSWSTART_Pos       (1U)\n#define DFSDM_FLTCR1_JSWSTART_Msk       (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos)   /*!< 0x00000002 */\n#define DFSDM_FLTCR1_JSWSTART           DFSDM_FLTCR1_JSWSTART_Msk              /*!< Start the conversion of the injected group of channels */\n#define DFSDM_FLTCR1_DFEN_Pos           (0U)\n#define DFSDM_FLTCR1_DFEN_Msk           (0x1UL << DFSDM_FLTCR1_DFEN_Pos)       /*!< 0x00000001 */\n#define DFSDM_FLTCR1_DFEN               DFSDM_FLTCR1_DFEN_Msk                  /*!< DFSDM enable */\n\n/********************  Bit definition for DFSDM_FLTCR2 register *******************/\n#define DFSDM_FLTCR2_AWDCH_Pos          (16U)\n#define DFSDM_FLTCR2_AWDCH_Msk          (0xFFUL << DFSDM_FLTCR2_AWDCH_Pos)     /*!< 0x00FF0000 */\n#define DFSDM_FLTCR2_AWDCH              DFSDM_FLTCR2_AWDCH_Msk                 /*!< AWDCH[7:0] Analog watchdog channel selection */\n#define DFSDM_FLTCR2_EXCH_Pos           (8U)\n#define DFSDM_FLTCR2_EXCH_Msk           (0xFFUL << DFSDM_FLTCR2_EXCH_Pos)      /*!< 0x0000FF00 */\n#define DFSDM_FLTCR2_EXCH               DFSDM_FLTCR2_EXCH_Msk                  /*!< EXCH[7:0] Extreme detector channel selection */\n#define DFSDM_FLTCR2_CKABIE_Pos         (6U)\n#define DFSDM_FLTCR2_CKABIE_Msk         (0x1UL << DFSDM_FLTCR2_CKABIE_Pos)     /*!< 0x00000040 */\n#define DFSDM_FLTCR2_CKABIE             DFSDM_FLTCR2_CKABIE_Msk                /*!< Clock absence interrupt enable */\n#define DFSDM_FLTCR2_SCDIE_Pos          (5U)\n#define DFSDM_FLTCR2_SCDIE_Msk          (0x1UL << DFSDM_FLTCR2_SCDIE_Pos)      /*!< 0x00000020 */\n#define DFSDM_FLTCR2_SCDIE              DFSDM_FLTCR2_SCDIE_Msk                 /*!< Short circuit detector interrupt enable */\n#define DFSDM_FLTCR2_AWDIE_Pos          (4U)\n#define DFSDM_FLTCR2_AWDIE_Msk          (0x1UL << DFSDM_FLTCR2_AWDIE_Pos)      /*!< 0x00000010 */\n#define DFSDM_FLTCR2_AWDIE              DFSDM_FLTCR2_AWDIE_Msk                 /*!< Analog watchdog interrupt enable */\n#define DFSDM_FLTCR2_ROVRIE_Pos         (3U)\n#define DFSDM_FLTCR2_ROVRIE_Msk         (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos)     /*!< 0x00000008 */\n#define DFSDM_FLTCR2_ROVRIE             DFSDM_FLTCR2_ROVRIE_Msk                /*!< Regular data overrun interrupt enable */\n#define DFSDM_FLTCR2_JOVRIE_Pos         (2U)\n#define DFSDM_FLTCR2_JOVRIE_Msk         (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos)     /*!< 0x00000004 */\n#define DFSDM_FLTCR2_JOVRIE             DFSDM_FLTCR2_JOVRIE_Msk                /*!< Injected data overrun interrupt enable */\n#define DFSDM_FLTCR2_REOCIE_Pos         (1U)\n#define DFSDM_FLTCR2_REOCIE_Msk         (0x1UL << DFSDM_FLTCR2_REOCIE_Pos)     /*!< 0x00000002 */\n#define DFSDM_FLTCR2_REOCIE             DFSDM_FLTCR2_REOCIE_Msk                /*!< Regular end of conversion interrupt enable */\n#define DFSDM_FLTCR2_JEOCIE_Pos         (0U)\n#define DFSDM_FLTCR2_JEOCIE_Msk         (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos)     /*!< 0x00000001 */\n#define DFSDM_FLTCR2_JEOCIE             DFSDM_FLTCR2_JEOCIE_Msk                /*!< Injected end of conversion interrupt enable */\n\n/********************  Bit definition for DFSDM_FLTISR register *******************/\n#define DFSDM_FLTISR_SCDF_Pos           (24U)\n#define DFSDM_FLTISR_SCDF_Msk           (0xFFUL << DFSDM_FLTISR_SCDF_Pos)      /*!< 0xFF000000 */\n#define DFSDM_FLTISR_SCDF               DFSDM_FLTISR_SCDF_Msk                  /*!< SCDF[7:0] Short circuit detector flag */\n#define DFSDM_FLTISR_CKABF_Pos          (16U)\n#define DFSDM_FLTISR_CKABF_Msk          (0xFFUL << DFSDM_FLTISR_CKABF_Pos)     /*!< 0x00FF0000 */\n#define DFSDM_FLTISR_CKABF              DFSDM_FLTISR_CKABF_Msk                 /*!< CKABF[7:0] Clock absence flag */\n#define DFSDM_FLTISR_RCIP_Pos           (14U)\n#define DFSDM_FLTISR_RCIP_Msk           (0x1UL << DFSDM_FLTISR_RCIP_Pos)       /*!< 0x00004000 */\n#define DFSDM_FLTISR_RCIP               DFSDM_FLTISR_RCIP_Msk                  /*!< Regular conversion in progress status */\n#define DFSDM_FLTISR_JCIP_Pos           (13U)\n#define DFSDM_FLTISR_JCIP_Msk           (0x1UL << DFSDM_FLTISR_JCIP_Pos)       /*!< 0x00002000 */\n#define DFSDM_FLTISR_JCIP               DFSDM_FLTISR_JCIP_Msk                  /*!< Injected conversion in progress status */\n#define DFSDM_FLTISR_AWDF_Pos           (4U)\n#define DFSDM_FLTISR_AWDF_Msk           (0x1UL << DFSDM_FLTISR_AWDF_Pos)       /*!< 0x00000010 */\n#define DFSDM_FLTISR_AWDF               DFSDM_FLTISR_AWDF_Msk                  /*!< Analog watchdog */\n#define DFSDM_FLTISR_ROVRF_Pos          (3U)\n#define DFSDM_FLTISR_ROVRF_Msk          (0x1UL << DFSDM_FLTISR_ROVRF_Pos)      /*!< 0x00000008 */\n#define DFSDM_FLTISR_ROVRF              DFSDM_FLTISR_ROVRF_Msk                 /*!< Regular conversion overrun flag */\n#define DFSDM_FLTISR_JOVRF_Pos          (2U)\n#define DFSDM_FLTISR_JOVRF_Msk          (0x1UL << DFSDM_FLTISR_JOVRF_Pos)      /*!< 0x00000004 */\n#define DFSDM_FLTISR_JOVRF              DFSDM_FLTISR_JOVRF_Msk                 /*!< Injected conversion overrun flag */\n#define DFSDM_FLTISR_REOCF_Pos          (1U)\n#define DFSDM_FLTISR_REOCF_Msk          (0x1UL << DFSDM_FLTISR_REOCF_Pos)      /*!< 0x00000002 */\n#define DFSDM_FLTISR_REOCF              DFSDM_FLTISR_REOCF_Msk                 /*!< End of regular conversion flag */\n#define DFSDM_FLTISR_JEOCF_Pos          (0U)\n#define DFSDM_FLTISR_JEOCF_Msk          (0x1UL << DFSDM_FLTISR_JEOCF_Pos)      /*!< 0x00000001 */\n#define DFSDM_FLTISR_JEOCF              DFSDM_FLTISR_JEOCF_Msk                 /*!< End of injected conversion flag */\n\n/********************  Bit definition for DFSDM_FLTICR register *******************/\n#define DFSDM_FLTICR_CLRSCDF_Pos        (24U)\n#define DFSDM_FLTICR_CLRSCDF_Msk        (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos)   /*!< 0xFF000000 */\n#define DFSDM_FLTICR_CLRSCDF            DFSDM_FLTICR_CLRSCDF_Msk               /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */\n#define DFSDM_FLTICR_CLRCKABF_Pos       (16U)\n#define DFSDM_FLTICR_CLRCKABF_Msk       (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos)  /*!< 0x00FF0000 */\n#define DFSDM_FLTICR_CLRCKABF           DFSDM_FLTICR_CLRCKABF_Msk              /*!< CLRCKABF[7:0] Clear the clock absence flag */\n#define DFSDM_FLTICR_CLRROVRF_Pos       (3U)\n#define DFSDM_FLTICR_CLRROVRF_Msk       (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos)   /*!< 0x00000008 */\n#define DFSDM_FLTICR_CLRROVRF           DFSDM_FLTICR_CLRROVRF_Msk              /*!< Clear the regular conversion overrun flag */\n#define DFSDM_FLTICR_CLRJOVRF_Pos       (2U)\n#define DFSDM_FLTICR_CLRJOVRF_Msk       (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos)   /*!< 0x00000004 */\n#define DFSDM_FLTICR_CLRJOVRF           DFSDM_FLTICR_CLRJOVRF_Msk              /*!< Clear the injected conversion overrun flag */\n\n/*******************  Bit definition for DFSDM_FLTJCHGR register ******************/\n#define DFSDM_FLTJCHGR_JCHG_Pos         (0U)\n#define DFSDM_FLTJCHGR_JCHG_Msk         (0xFFUL << DFSDM_FLTJCHGR_JCHG_Pos)    /*!< 0x000000FF */\n#define DFSDM_FLTJCHGR_JCHG             DFSDM_FLTJCHGR_JCHG_Msk                /*!< JCHG[7:0] Injected channel group selection */\n\n/********************  Bit definition for DFSDM_FLTFCR register *******************/\n#define DFSDM_FLTFCR_FORD_Pos           (29U)\n#define DFSDM_FLTFCR_FORD_Msk           (0x7UL << DFSDM_FLTFCR_FORD_Pos)       /*!< 0xE0000000 */\n#define DFSDM_FLTFCR_FORD               DFSDM_FLTFCR_FORD_Msk                  /*!< FORD[2:0] Sinc filter order */\n#define DFSDM_FLTFCR_FORD_2             (0x4UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x80000000 */\n#define DFSDM_FLTFCR_FORD_1             (0x2UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x40000000 */\n#define DFSDM_FLTFCR_FORD_0             (0x1UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x20000000 */\n#define DFSDM_FLTFCR_FOSR_Pos           (16U)\n#define DFSDM_FLTFCR_FOSR_Msk           (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos)     /*!< 0x03FF0000 */\n#define DFSDM_FLTFCR_FOSR               DFSDM_FLTFCR_FOSR_Msk                  /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */\n#define DFSDM_FLTFCR_IOSR_Pos           (0U)\n#define DFSDM_FLTFCR_IOSR_Msk           (0xFFUL << DFSDM_FLTFCR_IOSR_Pos)      /*!< 0x000000FF */\n#define DFSDM_FLTFCR_IOSR               DFSDM_FLTFCR_IOSR_Msk                  /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */\n\n/******************  Bit definition for DFSDM_FLTJDATAR register *****************/\n#define DFSDM_FLTJDATAR_JDATA_Pos       (8U)\n#define DFSDM_FLTJDATAR_JDATA_Msk       (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */\n#define DFSDM_FLTJDATAR_JDATA           DFSDM_FLTJDATAR_JDATA_Msk              /*!< JDATA[23:0] Injected group conversion data */\n#define DFSDM_FLTJDATAR_JDATACH_Pos     (0U)\n#define DFSDM_FLTJDATAR_JDATACH_Msk     (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */\n#define DFSDM_FLTJDATAR_JDATACH         DFSDM_FLTJDATAR_JDATACH_Msk            /*!< JDATACH[2:0] Injected channel most recently converted */\n\n/******************  Bit definition for DFSDM_FLTRDATAR register *****************/\n#define DFSDM_FLTRDATAR_RDATA_Pos       (8U)\n#define DFSDM_FLTRDATAR_RDATA_Msk       (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */\n#define DFSDM_FLTRDATAR_RDATA           DFSDM_FLTRDATAR_RDATA_Msk              /*!< RDATA[23:0] Regular channel conversion data */\n#define DFSDM_FLTRDATAR_RPEND_Pos       (4U)\n#define DFSDM_FLTRDATAR_RPEND_Msk       (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos)   /*!< 0x00000010 */\n#define DFSDM_FLTRDATAR_RPEND           DFSDM_FLTRDATAR_RPEND_Msk              /*!< RPEND Regular channel pending data */\n#define DFSDM_FLTRDATAR_RDATACH_Pos     (0U)\n#define DFSDM_FLTRDATAR_RDATACH_Msk     (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */\n#define DFSDM_FLTRDATAR_RDATACH         DFSDM_FLTRDATAR_RDATACH_Msk            /*!< RDATACH[2:0] Regular channel most recently converted */\n\n/******************  Bit definition for DFSDM_FLTAWHTR register ******************/\n#define DFSDM_FLTAWHTR_AWHT_Pos         (8U)\n#define DFSDM_FLTAWHTR_AWHT_Msk         (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */\n#define DFSDM_FLTAWHTR_AWHT             DFSDM_FLTAWHTR_AWHT_Msk                /*!< AWHT[23:0] Analog watchdog high threshold */\n#define DFSDM_FLTAWHTR_BKAWH_Pos        (0U)\n#define DFSDM_FLTAWHTR_BKAWH_Msk        (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos)    /*!< 0x0000000F */\n#define DFSDM_FLTAWHTR_BKAWH            DFSDM_FLTAWHTR_BKAWH_Msk               /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */\n\n/******************  Bit definition for DFSDM_FLTAWLTR register ******************/\n#define DFSDM_FLTAWLTR_AWLT_Pos         (8U)\n#define DFSDM_FLTAWLTR_AWLT_Msk         (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */\n#define DFSDM_FLTAWLTR_AWLT             DFSDM_FLTAWLTR_AWLT_Msk                /*!< AWHT[23:0] Analog watchdog low threshold */\n#define DFSDM_FLTAWLTR_BKAWL_Pos        (0U)\n#define DFSDM_FLTAWLTR_BKAWL_Msk        (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos)    /*!< 0x0000000F */\n#define DFSDM_FLTAWLTR_BKAWL            DFSDM_FLTAWLTR_BKAWL_Msk               /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */\n\n/******************  Bit definition for DFSDM_FLTAWSR register ******************/\n#define DFSDM_FLTAWSR_AWHTF_Pos         (8U)\n#define DFSDM_FLTAWSR_AWHTF_Msk         (0xFFUL << DFSDM_FLTAWSR_AWHTF_Pos)    /*!< 0x0000FF00 */\n#define DFSDM_FLTAWSR_AWHTF             DFSDM_FLTAWSR_AWHTF_Msk                /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */\n#define DFSDM_FLTAWSR_AWLTF_Pos         (0U)\n#define DFSDM_FLTAWSR_AWLTF_Msk         (0xFFUL << DFSDM_FLTAWSR_AWLTF_Pos)    /*!< 0x000000FF */\n#define DFSDM_FLTAWSR_AWLTF             DFSDM_FLTAWSR_AWLTF_Msk                /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */\n\n/******************  Bit definition for DFSDM_FLTAWCFR) register *****************/\n#define DFSDM_FLTAWCFR_CLRAWHTF_Pos     (8U)\n#define DFSDM_FLTAWCFR_CLRAWHTF_Msk     (0xFFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */\n#define DFSDM_FLTAWCFR_CLRAWHTF         DFSDM_FLTAWCFR_CLRAWHTF_Msk            /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */\n#define DFSDM_FLTAWCFR_CLRAWLTF_Pos     (0U)\n#define DFSDM_FLTAWCFR_CLRAWLTF_Msk     (0xFFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */\n#define DFSDM_FLTAWCFR_CLRAWLTF         DFSDM_FLTAWCFR_CLRAWLTF_Msk            /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */\n\n/******************  Bit definition for DFSDM_FLTEXMAX register ******************/\n#define DFSDM_FLTEXMAX_EXMAX_Pos        (8U)\n#define DFSDM_FLTEXMAX_EXMAX_Msk        (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */\n#define DFSDM_FLTEXMAX_EXMAX            DFSDM_FLTEXMAX_EXMAX_Msk               /*!< EXMAX[23:0] Extreme detector maximum value */\n#define DFSDM_FLTEXMAX_EXMAXCH_Pos      (0U)\n#define DFSDM_FLTEXMAX_EXMAXCH_Msk      (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos)  /*!< 0x00000007 */\n#define DFSDM_FLTEXMAX_EXMAXCH          DFSDM_FLTEXMAX_EXMAXCH_Msk             /*!< EXMAXCH[2:0] Extreme detector maximum data channel */\n\n/******************  Bit definition for DFSDM_FLTEXMIN register ******************/\n#define DFSDM_FLTEXMIN_EXMIN_Pos        (8U)\n#define DFSDM_FLTEXMIN_EXMIN_Msk        (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */\n#define DFSDM_FLTEXMIN_EXMIN            DFSDM_FLTEXMIN_EXMIN_Msk               /*!< EXMIN[23:0] Extreme detector minimum value */\n#define DFSDM_FLTEXMIN_EXMINCH_Pos      (0U)\n#define DFSDM_FLTEXMIN_EXMINCH_Msk      (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos)  /*!< 0x00000007 */\n#define DFSDM_FLTEXMIN_EXMINCH          DFSDM_FLTEXMIN_EXMINCH_Msk             /*!< EXMINCH[2:0] Extreme detector minimum data channel */\n\n/******************  Bit definition for DFSDM_FLTCNVTIMR register ******************/\n#define DFSDM_FLTCNVTIMR_CNVCNT_Pos     (4U)\n#define DFSDM_FLTCNVTIMR_CNVCNT_Msk     (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */\n#define DFSDM_FLTCNVTIMR_CNVCNT         DFSDM_FLTCNVTIMR_CNVCNT_Msk            /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */\n\n/******************************************************************************/\n/*                                                                            */\n/*                           BDMA Controller                                  */\n/*                                                                            */\n/******************************************************************************/\n\n/*******************  Bit definition for BDMA_ISR register  ********************/\n#define BDMA_ISR_GIF0_Pos       (0U)\n#define BDMA_ISR_GIF0_Msk       (0x1UL << BDMA_ISR_GIF0_Pos)                   /*!< 0x00000001 */\n#define BDMA_ISR_GIF0           BDMA_ISR_GIF0_Msk                              /*!< Channel 0 Global interrupt flag */\n#define BDMA_ISR_TCIF0_Pos      (1U)\n#define BDMA_ISR_TCIF0_Msk      (0x1UL << BDMA_ISR_TCIF0_Pos)                  /*!< 0x00000002 */\n#define BDMA_ISR_TCIF0          BDMA_ISR_TCIF0_Msk                             /*!< Channel 0 Transfer Complete flag */\n#define BDMA_ISR_HTIF0_Pos      (2U)\n#define BDMA_ISR_HTIF0_Msk      (0x1UL << BDMA_ISR_HTIF0_Pos)                  /*!< 0x00000004 */\n#define BDMA_ISR_HTIF0          BDMA_ISR_HTIF0_Msk                             /*!< Channel 0 Half Transfer flag */\n#define BDMA_ISR_TEIF0_Pos      (3U)\n#define BDMA_ISR_TEIF0_Msk      (0x1UL << BDMA_ISR_TEIF0_Pos)                  /*!< 0x00000008 */\n#define BDMA_ISR_TEIF0          BDMA_ISR_TEIF0_Msk                             /*!< Channel 0 Transfer Error flag */\n#define BDMA_ISR_GIF1_Pos       (4U)\n#define BDMA_ISR_GIF1_Msk       (0x1UL << BDMA_ISR_GIF1_Pos)                   /*!< 0x00000010 */\n#define BDMA_ISR_GIF1           BDMA_ISR_GIF1_Msk                              /*!< Channel 1 Global interrupt flag */\n#define BDMA_ISR_TCIF1_Pos      (5U)\n#define BDMA_ISR_TCIF1_Msk      (0x1UL << BDMA_ISR_TCIF1_Pos)                  /*!< 0x00000020 */\n#define BDMA_ISR_TCIF1          BDMA_ISR_TCIF1_Msk                             /*!< Channel 1 Transfer Complete flag */\n#define BDMA_ISR_HTIF1_Pos      (6U)\n#define BDMA_ISR_HTIF1_Msk      (0x1UL << BDMA_ISR_HTIF1_Pos)                  /*!< 0x00000040 */\n#define BDMA_ISR_HTIF1          BDMA_ISR_HTIF1_Msk                             /*!< Channel 1 Half Transfer flag */\n#define BDMA_ISR_TEIF1_Pos      (7U)\n#define BDMA_ISR_TEIF1_Msk      (0x1UL << BDMA_ISR_TEIF1_Pos)                  /*!< 0x00000080 */\n#define BDMA_ISR_TEIF1          BDMA_ISR_TEIF1_Msk                             /*!< Channel 1 Transfer Error flag */\n#define BDMA_ISR_GIF2_Pos       (8U)\n#define BDMA_ISR_GIF2_Msk       (0x1UL << BDMA_ISR_GIF2_Pos)                   /*!< 0x00000100 */\n#define BDMA_ISR_GIF2           BDMA_ISR_GIF2_Msk                              /*!< Channel 2 Global interrupt flag */\n#define BDMA_ISR_TCIF2_Pos      (9U)\n#define BDMA_ISR_TCIF2_Msk      (0x1UL << BDMA_ISR_TCIF2_Pos)                  /*!< 0x00000200 */\n#define BDMA_ISR_TCIF2          BDMA_ISR_TCIF2_Msk                             /*!< Channel 2 Transfer Complete flag */\n#define BDMA_ISR_HTIF2_Pos      (10U)\n#define BDMA_ISR_HTIF2_Msk      (0x1UL << BDMA_ISR_HTIF2_Pos)                  /*!< 0x00000400 */\n#define BDMA_ISR_HTIF2          BDMA_ISR_HTIF2_Msk                             /*!< Channel 2 Half Transfer flag */\n#define BDMA_ISR_TEIF2_Pos      (11U)\n#define BDMA_ISR_TEIF2_Msk      (0x1UL << BDMA_ISR_TEIF2_Pos)                  /*!< 0x00000800 */\n#define BDMA_ISR_TEIF2          BDMA_ISR_TEIF2_Msk                             /*!< Channel 2 Transfer Error flag */\n#define BDMA_ISR_GIF3_Pos       (12U)\n#define BDMA_ISR_GIF3_Msk       (0x1UL << BDMA_ISR_GIF3_Pos)                   /*!< 0x00001000 */\n#define BDMA_ISR_GIF3           BDMA_ISR_GIF3_Msk                              /*!< Channel 3 Global interrupt flag */\n#define BDMA_ISR_TCIF3_Pos      (13U)\n#define BDMA_ISR_TCIF3_Msk      (0x1UL << BDMA_ISR_TCIF3_Pos)                  /*!< 0x00002000 */\n#define BDMA_ISR_TCIF3          BDMA_ISR_TCIF3_Msk                             /*!< Channel 3 Transfer Complete flag */\n#define BDMA_ISR_HTIF3_Pos      (14U)\n#define BDMA_ISR_HTIF3_Msk      (0x1UL << BDMA_ISR_HTIF3_Pos)                  /*!< 0x00004000 */\n#define BDMA_ISR_HTIF3          BDMA_ISR_HTIF3_Msk                             /*!< Channel 3 Half Transfer flag */\n#define BDMA_ISR_TEIF3_Pos      (15U)\n#define BDMA_ISR_TEIF3_Msk      (0x1UL << BDMA_ISR_TEIF3_Pos)                  /*!< 0x00008000 */\n#define BDMA_ISR_TEIF3          BDMA_ISR_TEIF3_Msk                             /*!< Channel 3 Transfer Error flag */\n#define BDMA_ISR_GIF4_Pos       (16U)\n#define BDMA_ISR_GIF4_Msk       (0x1UL << BDMA_ISR_GIF4_Pos)                   /*!< 0x00010000 */\n#define BDMA_ISR_GIF4           BDMA_ISR_GIF4_Msk                              /*!< Channel 4 Global interrupt flag */\n#define BDMA_ISR_TCIF4_Pos      (17U)\n#define BDMA_ISR_TCIF4_Msk      (0x1UL << BDMA_ISR_TCIF4_Pos)                  /*!< 0x00020000 */\n#define BDMA_ISR_TCIF4          BDMA_ISR_TCIF4_Msk                             /*!< Channel 4 Transfer Complete flag */\n#define BDMA_ISR_HTIF4_Pos      (18U)\n#define BDMA_ISR_HTIF4_Msk      (0x1UL << BDMA_ISR_HTIF4_Pos)                  /*!< 0x00040000 */\n#define BDMA_ISR_HTIF4          BDMA_ISR_HTIF4_Msk                             /*!< Channel 4 Half Transfer flag */\n#define BDMA_ISR_TEIF4_Pos      (19U)\n#define BDMA_ISR_TEIF4_Msk      (0x1UL << BDMA_ISR_TEIF4_Pos)                  /*!< 0x00080000 */\n#define BDMA_ISR_TEIF4          BDMA_ISR_TEIF4_Msk                             /*!< Channel 4 Transfer Error flag */\n#define BDMA_ISR_GIF5_Pos       (20U)\n#define BDMA_ISR_GIF5_Msk       (0x1UL << BDMA_ISR_GIF5_Pos)                   /*!< 0x00100000 */\n#define BDMA_ISR_GIF5           BDMA_ISR_GIF5_Msk                              /*!< Channel 5 Global interrupt flag */\n#define BDMA_ISR_TCIF5_Pos      (21U)\n#define BDMA_ISR_TCIF5_Msk      (0x1UL << BDMA_ISR_TCIF5_Pos)                  /*!< 0x00200000 */\n#define BDMA_ISR_TCIF5          BDMA_ISR_TCIF5_Msk                             /*!< Channel 5 Transfer Complete flag */\n#define BDMA_ISR_HTIF5_Pos      (22U)\n#define BDMA_ISR_HTIF5_Msk      (0x1UL << BDMA_ISR_HTIF5_Pos)                  /*!< 0x00400000 */\n#define BDMA_ISR_HTIF5          BDMA_ISR_HTIF5_Msk                             /*!< Channel 5 Half Transfer flag */\n#define BDMA_ISR_TEIF5_Pos      (23U)\n#define BDMA_ISR_TEIF5_Msk      (0x1UL << BDMA_ISR_TEIF5_Pos)                  /*!< 0x00800000 */\n#define BDMA_ISR_TEIF5          BDMA_ISR_TEIF5_Msk                             /*!< Channel 5 Transfer Error flag */\n#define BDMA_ISR_GIF6_Pos       (24U)\n#define BDMA_ISR_GIF6_Msk       (0x1UL << BDMA_ISR_GIF6_Pos)                   /*!< 0x01000000 */\n#define BDMA_ISR_GIF6           BDMA_ISR_GIF6_Msk                              /*!< Channel 6 Global interrupt flag */\n#define BDMA_ISR_TCIF6_Pos      (25U)\n#define BDMA_ISR_TCIF6_Msk      (0x1UL << BDMA_ISR_TCIF6_Pos)                  /*!< 0x02000000 */\n#define BDMA_ISR_TCIF6          BDMA_ISR_TCIF6_Msk                             /*!< Channel 6 Transfer Complete flag */\n#define BDMA_ISR_HTIF6_Pos      (26U)\n#define BDMA_ISR_HTIF6_Msk      (0x1UL << BDMA_ISR_HTIF6_Pos)                  /*!< 0x04000000 */\n#define BDMA_ISR_HTIF6          BDMA_ISR_HTIF6_Msk                             /*!< Channel 6 Half Transfer flag */\n#define BDMA_ISR_TEIF6_Pos      (27U)\n#define BDMA_ISR_TEIF6_Msk      (0x1UL << BDMA_ISR_TEIF6_Pos)                  /*!< 0x08000000 */\n#define BDMA_ISR_TEIF6          BDMA_ISR_TEIF6_Msk                             /*!< Channel 6 Transfer Error flag */\n#define BDMA_ISR_GIF7_Pos       (28U)\n#define BDMA_ISR_GIF7_Msk       (0x1UL << BDMA_ISR_GIF7_Pos)                   /*!< 0x10000000 */\n#define BDMA_ISR_GIF7           BDMA_ISR_GIF7_Msk                              /*!< Channel 7 Global interrupt flag */\n#define BDMA_ISR_TCIF7_Pos      (29U)\n#define BDMA_ISR_TCIF7_Msk      (0x1UL << BDMA_ISR_TCIF7_Pos)                  /*!< 0x20000000 */\n#define BDMA_ISR_TCIF7          BDMA_ISR_TCIF7_Msk                             /*!< Channel 7 Transfer Complete flag */\n#define BDMA_ISR_HTIF7_Pos      (30U)\n#define BDMA_ISR_HTIF7_Msk      (0x1UL << BDMA_ISR_HTIF7_Pos)                  /*!< 0x40000000 */\n#define BDMA_ISR_HTIF7          BDMA_ISR_HTIF7_Msk                             /*!< Channel 7 Half Transfer flag */\n#define BDMA_ISR_TEIF7_Pos      (31U)\n#define BDMA_ISR_TEIF7_Msk      (0x1UL << BDMA_ISR_TEIF7_Pos)                  /*!< 0x80000000 */\n#define BDMA_ISR_TEIF7          BDMA_ISR_TEIF7_Msk                             /*!< Channel 7 Transfer Error flag */\n\n/*******************  Bit definition for BDMA_IFCR register  *******************/\n#define BDMA_IFCR_CGIF0_Pos     (0U)\n#define BDMA_IFCR_CGIF0_Msk     (0x1UL << BDMA_IFCR_CGIF0_Pos)                 /*!< 0x00000001 */\n#define BDMA_IFCR_CGIF0         BDMA_IFCR_CGIF0_Msk                            /*!< Channel 0 Global interrupt clearr */\n#define BDMA_IFCR_CTCIF0_Pos    (1U)\n#define BDMA_IFCR_CTCIF0_Msk    (0x1UL << BDMA_IFCR_CTCIF0_Pos)                /*!< 0x00000002 */\n#define BDMA_IFCR_CTCIF0        BDMA_IFCR_CTCIF0_Msk                           /*!< Channel 0 Transfer Complete clear */\n#define BDMA_IFCR_CHTIF0_Pos    (2U)\n#define BDMA_IFCR_CHTIF0_Msk    (0x1UL << BDMA_IFCR_CHTIF0_Pos)                /*!< 0x00000004 */\n#define BDMA_IFCR_CHTIF0        BDMA_IFCR_CHTIF0_Msk                           /*!< Channel 0 Half Transfer clear */\n#define BDMA_IFCR_CTEIF0_Pos    (3U)\n#define BDMA_IFCR_CTEIF0_Msk    (0x1UL << BDMA_IFCR_CTEIF0_Pos)                /*!< 0x00000008 */\n#define BDMA_IFCR_CTEIF0        BDMA_IFCR_CTEIF0_Msk                           /*!< Channel 0 Transfer Error clear */\n#define BDMA_IFCR_CGIF1_Pos     (4U)\n#define BDMA_IFCR_CGIF1_Msk     (0x1UL << BDMA_IFCR_CGIF1_Pos)                 /*!< 0x00000010 */\n#define BDMA_IFCR_CGIF1         BDMA_IFCR_CGIF1_Msk                            /*!< Channel 1 Global interrupt clear */\n#define BDMA_IFCR_CTCIF1_Pos    (5U)\n#define BDMA_IFCR_CTCIF1_Msk    (0x1UL << BDMA_IFCR_CTCIF1_Pos)                /*!< 0x00000020 */\n#define BDMA_IFCR_CTCIF1        BDMA_IFCR_CTCIF1_Msk                           /*!< Channel 1 Transfer Complete clear */\n#define BDMA_IFCR_CHTIF1_Pos    (6U)\n#define BDMA_IFCR_CHTIF1_Msk    (0x1UL << BDMA_IFCR_CHTIF1_Pos)                /*!< 0x00000040 */\n#define BDMA_IFCR_CHTIF1        BDMA_IFCR_CHTIF1_Msk                           /*!< Channel 1 Half Transfer clear */\n#define BDMA_IFCR_CTEIF1_Pos    (7U)\n#define BDMA_IFCR_CTEIF1_Msk    (0x1UL << BDMA_IFCR_CTEIF1_Pos)                /*!< 0x00000080 */\n#define BDMA_IFCR_CTEIF1        BDMA_IFCR_CTEIF1_Msk                           /*!< Channel 1 Transfer Error clear */\n#define BDMA_IFCR_CGIF2_Pos     (8U)\n#define BDMA_IFCR_CGIF2_Msk     (0x1UL << BDMA_IFCR_CGIF2_Pos)                 /*!< 0x00000100 */\n#define BDMA_IFCR_CGIF2         BDMA_IFCR_CGIF2_Msk                            /*!< Channel 2 Global interrupt clear */\n#define BDMA_IFCR_CTCIF2_Pos    (9U)\n#define BDMA_IFCR_CTCIF2_Msk    (0x1UL << BDMA_IFCR_CTCIF2_Pos)                /*!< 0x00000200 */\n#define BDMA_IFCR_CTCIF2        BDMA_IFCR_CTCIF2_Msk                           /*!< Channel 2 Transfer Complete clear */\n#define BDMA_IFCR_CHTIF2_Pos    (10U)\n#define BDMA_IFCR_CHTIF2_Msk    (0x1UL << BDMA_IFCR_CHTIF2_Pos)                /*!< 0x00000400 */\n#define BDMA_IFCR_CHTIF2        BDMA_IFCR_CHTIF2_Msk                           /*!< Channel 2 Half Transfer clear */\n#define BDMA_IFCR_CTEIF2_Pos    (11U)\n#define BDMA_IFCR_CTEIF2_Msk    (0x1UL << BDMA_IFCR_CTEIF2_Pos)                /*!< 0x00000800 */\n#define BDMA_IFCR_CTEIF2        BDMA_IFCR_CTEIF2_Msk                           /*!< Channel 2 Transfer Error clear */\n#define BDMA_IFCR_CGIF3_Pos     (12U)\n#define BDMA_IFCR_CGIF3_Msk     (0x1UL << BDMA_IFCR_CGIF3_Pos)                 /*!< 0x00001000 */\n#define BDMA_IFCR_CGIF3         BDMA_IFCR_CGIF3_Msk                            /*!< Channel 3 Global interrupt clear */\n#define BDMA_IFCR_CTCIF3_Pos    (13U)\n#define BDMA_IFCR_CTCIF3_Msk    (0x1UL << BDMA_IFCR_CTCIF3_Pos)                /*!< 0x00002000 */\n#define BDMA_IFCR_CTCIF3        BDMA_IFCR_CTCIF3_Msk                           /*!< Channel 3 Transfer Complete clear */\n#define BDMA_IFCR_CHTIF3_Pos    (14U)\n#define BDMA_IFCR_CHTIF3_Msk    (0x1UL << BDMA_IFCR_CHTIF3_Pos)                /*!< 0x00004000 */\n#define BDMA_IFCR_CHTIF3        BDMA_IFCR_CHTIF3_Msk                           /*!< Channel 3 Half Transfer clear */\n#define BDMA_IFCR_CTEIF3_Pos    (15U)\n#define BDMA_IFCR_CTEIF3_Msk    (0x1UL << BDMA_IFCR_CTEIF3_Pos)                /*!< 0x00008000 */\n#define BDMA_IFCR_CTEIF3        BDMA_IFCR_CTEIF3_Msk                           /*!< Channel 3 Transfer Error clear */\n#define BDMA_IFCR_CGIF4_Pos     (16U)\n#define BDMA_IFCR_CGIF4_Msk     (0x1UL << BDMA_IFCR_CGIF4_Pos)                 /*!< 0x00010000 */\n#define BDMA_IFCR_CGIF4         BDMA_IFCR_CGIF4_Msk                            /*!< Channel 4 Global interrupt clear */\n#define BDMA_IFCR_CTCIF4_Pos    (17U)\n#define BDMA_IFCR_CTCIF4_Msk    (0x1UL << BDMA_IFCR_CTCIF4_Pos)                /*!< 0x00020000 */\n#define BDMA_IFCR_CTCIF4        BDMA_IFCR_CTCIF4_Msk                           /*!< Channel 4 Transfer Complete clear */\n#define BDMA_IFCR_CHTIF4_Pos    (18U)\n#define BDMA_IFCR_CHTIF4_Msk    (0x1UL << BDMA_IFCR_CHTIF4_Pos)                /*!< 0x00040000 */\n#define BDMA_IFCR_CHTIF4        BDMA_IFCR_CHTIF4_Msk                           /*!< Channel 4 Half Transfer clear */\n#define BDMA_IFCR_CTEIF4_Pos    (19U)\n#define BDMA_IFCR_CTEIF4_Msk    (0x1UL << BDMA_IFCR_CTEIF4_Pos)                /*!< 0x00080000 */\n#define BDMA_IFCR_CTEIF4        BDMA_IFCR_CTEIF4_Msk                           /*!< Channel 4 Transfer Error clear */\n#define BDMA_IFCR_CGIF5_Pos     (20U)\n#define BDMA_IFCR_CGIF5_Msk     (0x1UL << BDMA_IFCR_CGIF5_Pos)                 /*!< 0x00100000 */\n#define BDMA_IFCR_CGIF5         BDMA_IFCR_CGIF5_Msk                            /*!< Channel 5 Global interrupt clear */\n#define BDMA_IFCR_CTCIF5_Pos    (21U)\n#define BDMA_IFCR_CTCIF5_Msk    (0x1UL << BDMA_IFCR_CTCIF5_Pos)                /*!< 0x00200000 */\n#define BDMA_IFCR_CTCIF5        BDMA_IFCR_CTCIF5_Msk                           /*!< Channel 5 Transfer Complete clear */\n#define BDMA_IFCR_CHTIF5_Pos    (22U)\n#define BDMA_IFCR_CHTIF5_Msk    (0x1UL << BDMA_IFCR_CHTIF5_Pos)                /*!< 0x00400000 */\n#define BDMA_IFCR_CHTIF5        BDMA_IFCR_CHTIF5_Msk                           /*!< Channel 5 Half Transfer clear */\n#define BDMA_IFCR_CTEIF5_Pos    (23U)\n#define BDMA_IFCR_CTEIF5_Msk    (0x1UL << BDMA_IFCR_CTEIF5_Pos)                /*!< 0x00800000 */\n#define BDMA_IFCR_CTEIF5        BDMA_IFCR_CTEIF5_Msk                           /*!< Channel 5 Transfer Error clear */\n#define BDMA_IFCR_CGIF6_Pos     (24U)\n#define BDMA_IFCR_CGIF6_Msk     (0x1UL << BDMA_IFCR_CGIF6_Pos)                 /*!< 0x01000000 */\n#define BDMA_IFCR_CGIF6         BDMA_IFCR_CGIF6_Msk                            /*!< Channel 6 Global interrupt clear */\n#define BDMA_IFCR_CTCIF6_Pos    (25U)\n#define BDMA_IFCR_CTCIF6_Msk    (0x1UL << BDMA_IFCR_CTCIF6_Pos)                /*!< 0x02000000 */\n#define BDMA_IFCR_CTCIF6        BDMA_IFCR_CTCIF6_Msk                           /*!< Channel 6 Transfer Complete clear */\n#define BDMA_IFCR_CHTIF6_Pos    (26U)\n#define BDMA_IFCR_CHTIF6_Msk    (0x1UL << BDMA_IFCR_CHTIF6_Pos)                /*!< 0x04000000 */\n#define BDMA_IFCR_CHTIF6        BDMA_IFCR_CHTIF6_Msk                           /*!< Channel 6 Half Transfer clear */\n#define BDMA_IFCR_CTEIF6_Pos    (27U)\n#define BDMA_IFCR_CTEIF6_Msk    (0x1UL << BDMA_IFCR_CTEIF6_Pos)                /*!< 0x08000000 */\n#define BDMA_IFCR_CTEIF6        BDMA_IFCR_CTEIF6_Msk                           /*!< Channel 6 Transfer Error clear */\n#define BDMA_IFCR_CGIF7_Pos     (28U)\n#define BDMA_IFCR_CGIF7_Msk     (0x1UL << BDMA_IFCR_CGIF7_Pos)                 /*!< 0x10000000 */\n#define BDMA_IFCR_CGIF7         BDMA_IFCR_CGIF7_Msk                            /*!< Channel 7 Global interrupt clear */\n#define BDMA_IFCR_CTCIF7_Pos    (29U)\n#define BDMA_IFCR_CTCIF7_Msk    (0x1UL << BDMA_IFCR_CTCIF7_Pos)                /*!< 0x20000000 */\n#define BDMA_IFCR_CTCIF7        BDMA_IFCR_CTCIF7_Msk                           /*!< Channel 7 Transfer Complete clear */\n#define BDMA_IFCR_CHTIF7_Pos    (30U)\n#define BDMA_IFCR_CHTIF7_Msk    (0x1UL << BDMA_IFCR_CHTIF7_Pos)                /*!< 0x40000000 */\n#define BDMA_IFCR_CHTIF7        BDMA_IFCR_CHTIF7_Msk                           /*!< Channel 7 Half Transfer clear */\n#define BDMA_IFCR_CTEIF7_Pos    (31U)\n#define BDMA_IFCR_CTEIF7_Msk    (0x1UL << BDMA_IFCR_CTEIF7_Pos)                /*!< 0x80000000 */\n#define BDMA_IFCR_CTEIF7        BDMA_IFCR_CTEIF7_Msk                           /*!< Channel 7 Transfer Error clear */\n\n/*******************  Bit definition for BDMA_CCR register  ********************/\n#define BDMA_CCR_EN_Pos         (0U)\n#define BDMA_CCR_EN_Msk         (0x1UL << BDMA_CCR_EN_Pos)                     /*!< 0x00000001 */\n#define BDMA_CCR_EN             BDMA_CCR_EN_Msk                                /*!< Channel enable                      */\n#define BDMA_CCR_TCIE_Pos       (1U)\n#define BDMA_CCR_TCIE_Msk       (0x1UL << BDMA_CCR_TCIE_Pos)                   /*!< 0x00000002 */\n#define BDMA_CCR_TCIE           BDMA_CCR_TCIE_Msk                              /*!< Transfer complete interrupt enable  */\n#define BDMA_CCR_HTIE_Pos       (2U)\n#define BDMA_CCR_HTIE_Msk       (0x1UL << BDMA_CCR_HTIE_Pos)                   /*!< 0x00000004 */\n#define BDMA_CCR_HTIE           BDMA_CCR_HTIE_Msk                              /*!< Half Transfer interrupt enable      */\n#define BDMA_CCR_TEIE_Pos       (3U)\n#define BDMA_CCR_TEIE_Msk       (0x1UL << BDMA_CCR_TEIE_Pos)                   /*!< 0x00000008 */\n#define BDMA_CCR_TEIE           BDMA_CCR_TEIE_Msk                              /*!< Transfer error interrupt enable     */\n#define BDMA_CCR_DIR_Pos        (4U)\n#define BDMA_CCR_DIR_Msk        (0x1UL << BDMA_CCR_DIR_Pos)                    /*!< 0x00000010 */\n#define BDMA_CCR_DIR            BDMA_CCR_DIR_Msk                               /*!< Data transfer direction             */\n#define BDMA_CCR_CIRC_Pos       (5U)\n#define BDMA_CCR_CIRC_Msk       (0x1UL << BDMA_CCR_CIRC_Pos)                   /*!< 0x00000020 */\n#define BDMA_CCR_CIRC           BDMA_CCR_CIRC_Msk                              /*!< Circular mode                       */\n#define BDMA_CCR_PINC_Pos       (6U)\n#define BDMA_CCR_PINC_Msk       (0x1UL << BDMA_CCR_PINC_Pos)                   /*!< 0x00000040 */\n#define BDMA_CCR_PINC           BDMA_CCR_PINC_Msk                              /*!< Peripheral increment mode           */\n#define BDMA_CCR_MINC_Pos       (7U)\n#define BDMA_CCR_MINC_Msk       (0x1UL << BDMA_CCR_MINC_Pos)                   /*!< 0x00000080 */\n#define BDMA_CCR_MINC           BDMA_CCR_MINC_Msk                              /*!< Memory increment mode               */\n\n#define BDMA_CCR_PSIZE_Pos      (8U)\n#define BDMA_CCR_PSIZE_Msk      (0x3UL << BDMA_CCR_PSIZE_Pos)                  /*!< 0x00000300 */\n#define BDMA_CCR_PSIZE          BDMA_CCR_PSIZE_Msk                             /*!< PSIZE[1:0] bits (Peripheral size)   */\n#define BDMA_CCR_PSIZE_0        (0x1UL << BDMA_CCR_PSIZE_Pos)                   /*!< 0x00000100 */\n#define BDMA_CCR_PSIZE_1        (0x2UL << BDMA_CCR_PSIZE_Pos)                   /*!< 0x00000200 */\n\n#define BDMA_CCR_MSIZE_Pos      (10U)\n#define BDMA_CCR_MSIZE_Msk      (0x3UL << BDMA_CCR_MSIZE_Pos)                  /*!< 0x00000C00 */\n#define BDMA_CCR_MSIZE          BDMA_CCR_MSIZE_Msk                             /*!< MSIZE[1:0] bits (Memory size)       */\n#define BDMA_CCR_MSIZE_0        (0x1UL << BDMA_CCR_MSIZE_Pos)                   /*!< 0x00000400 */\n#define BDMA_CCR_MSIZE_1        (0x2UL << BDMA_CCR_MSIZE_Pos)                   /*!< 0x00000800 */\n\n#define BDMA_CCR_PL_Pos         (12U)\n#define BDMA_CCR_PL_Msk         (0x3UL << BDMA_CCR_PL_Pos)                     /*!< 0x00003000 */\n#define BDMA_CCR_PL             BDMA_CCR_PL_Msk                                /*!< PL[1:0] bits(Channel Priority level)*/\n#define BDMA_CCR_PL_0           (0x1UL << BDMA_CCR_PL_Pos)                      /*!< 0x00001000 */\n#define BDMA_CCR_PL_1           (0x2UL << BDMA_CCR_PL_Pos)                      /*!< 0x00002000 */\n\n#define BDMA_CCR_MEM2MEM_Pos    (14U)\n#define BDMA_CCR_MEM2MEM_Msk    (0x1UL << BDMA_CCR_MEM2MEM_Pos)                /*!< 0x00004000 */\n#define BDMA_CCR_MEM2MEM        BDMA_CCR_MEM2MEM_Msk                           /*!< Memory to memory mode               */\n#define BDMA_CCR_DBM_Pos        (15U)\n#define BDMA_CCR_DBM_Msk        (0x1UL << BDMA_CCR_DBM_Pos)                    /*!< 0x0000A000 */\n#define BDMA_CCR_DBM            BDMA_CCR_DBM_Msk                               /*!< Memory to memory mode               */\n#define BDMA_CCR_CT_Pos         (16U)\n#define BDMA_CCR_CT_Msk         (0x1UL << BDMA_CCR_CT_Pos)                     /*!< 0x00010000 */\n#define BDMA_CCR_CT             BDMA_CCR_CT_Msk                                /*!< Memory to memory mode               */\n\n/******************  Bit definition for BDMA_CNDTR register  *******************/\n#define BDMA_CNDTR_NDT_Pos      (0U)\n#define BDMA_CNDTR_NDT_Msk      (0xFFFFUL << BDMA_CNDTR_NDT_Pos)               /*!< 0x0000FFFF */\n#define BDMA_CNDTR_NDT          BDMA_CNDTR_NDT_Msk                             /*!< Number of data to Transfer          */\n\n/******************  Bit definition for BDMA_CPAR register  ********************/\n#define BDMA_CPAR_PA_Pos        (0U)\n#define BDMA_CPAR_PA_Msk        (0xFFFFFFFFUL << BDMA_CPAR_PA_Pos)             /*!< 0xFFFFFFFF */\n#define BDMA_CPAR_PA            BDMA_CPAR_PA_Msk                               /*!< Peripheral Address                  */\n\n/******************  Bit definition for BDMA_CM0AR register  ********************/\n#define BDMA_CM0AR_MA_Pos        (0U)\n#define BDMA_CM0AR_MA_Msk        (0xFFFFFFFFUL << BDMA_CM0AR_MA_Pos)             /*!< 0xFFFFFFFF */\n#define BDMA_CM0AR_MA            BDMA_CM0AR_MA_Msk                               /*!< Memory Address                      */\n\n/******************  Bit definition for BDMA_CM1AR register  ********************/\n#define BDMA_CM1AR_MA_Pos        (0U)\n#define BDMA_CM1AR_MA_Msk        (0xFFFFFFFFUL << BDMA_CM1AR_MA_Pos)             /*!< 0xFFFFFFFF */\n#define BDMA_CM1AR_MA            BDMA_CM1AR_MA_Msk                               /*!< Memory Address                      */\n\n/******************************************************************************/\n/*                                                                            */\n/*                Ethernet MAC Registers bits definitions                     */\n/*                                                                            */\n/******************************************************************************/\n/* Bit definition for Ethernet MAC Configuration Register register */\n#define ETH_MACCR_ARP_Pos                             (31U)\n#define ETH_MACCR_ARP_Msk                             (0x1UL << ETH_MACCR_ARP_Pos) /*!< 0x80000000 */\n#define ETH_MACCR_ARP                                 ETH_MACCR_ARP_Msk        /* ARP Offload Enable */\n#define ETH_MACCR_SARC_Pos                            (28U)\n#define ETH_MACCR_SARC_Msk                            (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */\n#define ETH_MACCR_SARC                                ETH_MACCR_SARC_Msk       /* Source Address Insertion or Replacement Control */\n#define ETH_MACCR_SARC_MTIATI                         ((uint32_t)0x00000000)   /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */\n#define ETH_MACCR_SARC_INSADDR0_Pos                   (29U)\n#define ETH_MACCR_SARC_INSADDR0_Msk                   (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */\n#define ETH_MACCR_SARC_INSADDR0                       ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */\n#define ETH_MACCR_SARC_INSADDR1_Pos                   (29U)\n#define ETH_MACCR_SARC_INSADDR1_Msk                   (0x3UL << ETH_MACCR_SARC_INSADDR1_Pos) /*!< 0x60000000 */\n#define ETH_MACCR_SARC_INSADDR1                       ETH_MACCR_SARC_INSADDR1_Msk /* Insert MAC Address1 in the SA field of all transmitted packets. */\n#define ETH_MACCR_SARC_REPADDR0_Pos                   (28U)\n#define ETH_MACCR_SARC_REPADDR0_Msk                   (0x3UL << ETH_MACCR_SARC_REPADDR0_Pos) /*!< 0x30000000 */\n#define ETH_MACCR_SARC_REPADDR0                       ETH_MACCR_SARC_REPADDR0_Msk /* Replace MAC Address0 in the SA field of all transmitted packets. */\n#define ETH_MACCR_SARC_REPADDR1_Pos                   (28U)\n#define ETH_MACCR_SARC_REPADDR1_Msk                   (0x7UL << ETH_MACCR_SARC_REPADDR1_Pos) /*!< 0x70000000 */\n#define ETH_MACCR_SARC_REPADDR1                       ETH_MACCR_SARC_REPADDR1_Msk /* Replace MAC Address1 in the SA field of all transmitted packets. */\n#define ETH_MACCR_IPC_Pos                             (27U)\n#define ETH_MACCR_IPC_Msk                             (0x1UL << ETH_MACCR_IPC_Pos) /*!< 0x08000000 */\n#define ETH_MACCR_IPC                                 ETH_MACCR_IPC_Msk        /* Checksum Offload */\n#define ETH_MACCR_IPG_Pos                             (24U)\n#define ETH_MACCR_IPG_Msk                             (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */\n#define ETH_MACCR_IPG                                 ETH_MACCR_IPG_Msk        /* Inter-Packet Gap */\n#define ETH_MACCR_IPG_96BIT                           ((uint32_t)0x00000000)   /* Minimum IFG between Packets during transmission is 96Bit */\n#define ETH_MACCR_IPG_88BIT                           ((uint32_t)0x01000000)   /* Minimum IFG between Packets during transmission is 88Bit */\n#define ETH_MACCR_IPG_80BIT                           ((uint32_t)0x02000000)   /* Minimum IFG between Packets during transmission is 80Bit */\n#define ETH_MACCR_IPG_72BIT                           ((uint32_t)0x03000000)   /* Minimum IFG between Packets during transmission is 72Bit */\n#define ETH_MACCR_IPG_64BIT                           ((uint32_t)0x04000000)   /* Minimum IFG between Packets during transmission is 64Bit */\n#define ETH_MACCR_IPG_56BIT                           ((uint32_t)0x05000000)   /* Minimum IFG between Packets during transmission is 56Bit */\n#define ETH_MACCR_IPG_48BIT                           ((uint32_t)0x06000000)   /* Minimum IFG between Packets during transmission is 48Bit */\n#define ETH_MACCR_IPG_40BIT                           ((uint32_t)0x07000000)   /* Minimum IFG between Packets during transmission is 40Bit */\n#define ETH_MACCR_GPSLCE_Pos                          (23U)\n#define ETH_MACCR_GPSLCE_Msk                          (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */\n#define ETH_MACCR_GPSLCE                              ETH_MACCR_GPSLCE_Msk     /* Giant Packet Size Limit Control Enable */\n#define ETH_MACCR_S2KP_Pos                            (22U)\n#define ETH_MACCR_S2KP_Msk                            (0x1UL << ETH_MACCR_S2KP_Pos) /*!< 0x00400000 */\n#define ETH_MACCR_S2KP                                ETH_MACCR_S2KP_Msk       /* IEEE 802.3as Support for 2K Packets */\n#define ETH_MACCR_CST_Pos                             (21U)\n#define ETH_MACCR_CST_Msk                             (0x1UL << ETH_MACCR_CST_Pos) /*!< 0x00200000 */\n#define ETH_MACCR_CST                                 ETH_MACCR_CST_Msk        /* CRC stripping for Type packets */\n#define ETH_MACCR_ACS_Pos                             (20U)\n#define ETH_MACCR_ACS_Msk                             (0x1UL << ETH_MACCR_ACS_Pos) /*!< 0x00100000 */\n#define ETH_MACCR_ACS                                 ETH_MACCR_ACS_Msk        /* Automatic Pad or CRC Stripping */\n#define ETH_MACCR_WD_Pos                              (19U)\n#define ETH_MACCR_WD_Msk                              (0x1UL << ETH_MACCR_WD_Pos) /*!< 0x00080000 */\n#define ETH_MACCR_WD                                  ETH_MACCR_WD_Msk         /* Watchdog disable */\n#define ETH_MACCR_JD_Pos                              (17U)\n#define ETH_MACCR_JD_Msk                              (0x1UL << ETH_MACCR_JD_Pos) /*!< 0x00020000 */\n#define ETH_MACCR_JD                                  ETH_MACCR_JD_Msk         /* Jabber disable */\n#define ETH_MACCR_JE_Pos                              (16U)\n#define ETH_MACCR_JE_Msk                              (0x1UL << ETH_MACCR_JE_Pos) /*!< 0x00010000 */\n#define ETH_MACCR_JE                                  ETH_MACCR_JE_Msk         /* Jumbo Packet Enable */\n#define ETH_MACCR_FES_Pos                             (14U)\n#define ETH_MACCR_FES_Msk                             (0x1UL << ETH_MACCR_FES_Pos) /*!< 0x00004000 */\n#define ETH_MACCR_FES                                 ETH_MACCR_FES_Msk        /* Fast ethernet speed */\n#define ETH_MACCR_DM_Pos                              (13U)\n#define ETH_MACCR_DM_Msk                              (0x1UL << ETH_MACCR_DM_Pos) /*!< 0x00002000 */\n#define ETH_MACCR_DM                                  ETH_MACCR_DM_Msk         /* Duplex mode */\n#define ETH_MACCR_LM_Pos                              (12U)\n#define ETH_MACCR_LM_Msk                              (0x1UL << ETH_MACCR_LM_Pos) /*!< 0x00001000 */\n#define ETH_MACCR_LM                                  ETH_MACCR_LM_Msk         /* loopback mode */\n#define ETH_MACCR_ECRSFD_Pos                          (11U)\n#define ETH_MACCR_ECRSFD_Msk                          (0x1UL << ETH_MACCR_ECRSFD_Pos) /*!< 0x00000800 */\n#define ETH_MACCR_ECRSFD                              ETH_MACCR_ECRSFD_Msk     /* Enable Carrier Sense Before Transmission in Full-Duplex Mode */\n#define ETH_MACCR_DO_Pos                              (10U)\n#define ETH_MACCR_DO_Msk                              (0x1UL << ETH_MACCR_DO_Pos) /*!< 0x00000400 */\n#define ETH_MACCR_DO                                  ETH_MACCR_DO_Msk         /* Disable Receive own  */\n#define ETH_MACCR_DCRS_Pos                            (9U)\n#define ETH_MACCR_DCRS_Msk                            (0x1UL << ETH_MACCR_DCRS_Pos) /*!< 0x00000200 */\n#define ETH_MACCR_DCRS                                ETH_MACCR_DCRS_Msk       /* Disable Carrier Sense During Transmission */\n#define ETH_MACCR_DR_Pos                              (8U)\n#define ETH_MACCR_DR_Msk                              (0x1UL << ETH_MACCR_DR_Pos) /*!< 0x00000100 */\n#define ETH_MACCR_DR                                  ETH_MACCR_DR_Msk         /* Disable Retry */\n#define ETH_MACCR_BL_Pos                              (5U)\n#define ETH_MACCR_BL_Msk                              (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */\n#define ETH_MACCR_BL                                  ETH_MACCR_BL_Msk         /* Back-off limit mask */\n#define ETH_MACCR_BL_10                               (0x0UL << ETH_MACCR_BL_Pos) /*!< 0x00000000 */\n#define ETH_MACCR_BL_8                                (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */\n#define ETH_MACCR_BL_4                                (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */\n#define ETH_MACCR_BL_1                                (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */\n#define ETH_MACCR_DC_Pos                              (4U)\n#define ETH_MACCR_DC_Msk                              (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */\n#define ETH_MACCR_DC                                  ETH_MACCR_DC_Msk         /* Defferal check */\n#define ETH_MACCR_PRELEN_Pos                          (2U)\n#define ETH_MACCR_PRELEN_Msk                          (0x3UL << ETH_MACCR_PRELEN_Pos) /*!< 0x0000000C */\n#define ETH_MACCR_PRELEN                              ETH_MACCR_PRELEN_Msk     /* Preamble Length for Transmit packets */\n#define ETH_MACCR_PRELEN_7                            (0x0UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000000 */\n#define ETH_MACCR_PRELEN_5                            (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */\n#define ETH_MACCR_PRELEN_3                            (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000008 */\n#define ETH_MACCR_TE_Pos                              (1U)\n#define ETH_MACCR_TE_Msk                              (0x1UL << ETH_MACCR_TE_Pos) /*!< 0x00000002 */\n#define ETH_MACCR_TE                                  ETH_MACCR_TE_Msk         /* Transmitter enable */\n#define ETH_MACCR_RE_Pos                              (0U)\n#define ETH_MACCR_RE_Msk                              (0x1UL << ETH_MACCR_RE_Pos) /*!< 0x00000001 */\n#define ETH_MACCR_RE                                  ETH_MACCR_RE_Msk         /* Receiver enable */\n\n/* Bit definition for Ethernet MAC Extended Configuration Register register */\n#define ETH_MACECR_EIPG_Pos                           (25U)\n#define ETH_MACECR_EIPG_Msk                           (0x1FUL << ETH_MACECR_EIPG_Pos) /*!< 0x3E000000 */\n#define ETH_MACECR_EIPG                               ETH_MACECR_EIPG_Msk      /* Extended Inter-Packet Gap */\n#define ETH_MACECR_EIPGEN_Pos                         (24U)\n#define ETH_MACECR_EIPGEN_Msk                         (0x1UL << ETH_MACECR_EIPGEN_Pos) /*!< 0x01000000 */\n#define ETH_MACECR_EIPGEN                             ETH_MACECR_EIPGEN_Msk    /* Extended Inter-Packet Gap Enable */\n#define ETH_MACECR_USP_Pos                            (18U)\n#define ETH_MACECR_USP_Msk                            (0x1UL << ETH_MACECR_USP_Pos) /*!< 0x00040000 */\n#define ETH_MACECR_USP                                ETH_MACECR_USP_Msk       /* Unicast Slow Protocol Packet Detect */\n#define ETH_MACECR_SPEN_Pos                           (17U)\n#define ETH_MACECR_SPEN_Msk                           (0x1UL << ETH_MACECR_SPEN_Pos) /*!< 0x00020000 */\n#define ETH_MACECR_SPEN                               ETH_MACECR_SPEN_Msk      /* Slow Protocol Detection Enable */\n#define ETH_MACECR_DCRCC_Pos                          (16U)\n#define ETH_MACECR_DCRCC_Msk                          (0x1UL << ETH_MACECR_DCRCC_Pos) /*!< 0x00010000 */\n#define ETH_MACECR_DCRCC                              ETH_MACECR_DCRCC_Msk     /* Disable CRC Checking for Received Packets */\n#define ETH_MACECR_GPSL_Pos                           (0U)\n#define ETH_MACECR_GPSL_Msk                           (0x3FFFUL << ETH_MACECR_GPSL_Pos) /*!< 0x00003FFF */\n#define ETH_MACECR_GPSL                               ETH_MACECR_GPSL_Msk      /* Giant Packet Size Limit */\n\n/* Bit definition for Ethernet MAC Packet Filter Register */\n#define ETH_MACPFR_RA_Pos                             (31U)\n#define ETH_MACPFR_RA_Msk                             (0x1UL << ETH_MACPFR_RA_Pos) /*!< 0x80000000 */\n#define ETH_MACPFR_RA                                 ETH_MACPFR_RA_Msk        /* Receive all */\n#define ETH_MACPFR_DNTU_Pos                           (21U)\n#define ETH_MACPFR_DNTU_Msk                           (0x1UL << ETH_MACPFR_DNTU_Pos) /*!< 0x00200000 */\n#define ETH_MACPFR_DNTU                               ETH_MACPFR_DNTU_Msk      /* Drop Non-TCP/UDP over IP Packets */\n#define ETH_MACPFR_IPFE_Pos                           (20U)\n#define ETH_MACPFR_IPFE_Msk                           (0x1UL << ETH_MACPFR_IPFE_Pos) /*!< 0x00100000 */\n#define ETH_MACPFR_IPFE                               ETH_MACPFR_IPFE_Msk      /* Layer 3 and Layer 4 Filter Enable */\n#define ETH_MACPFR_VTFE_Pos                           (16U)\n#define ETH_MACPFR_VTFE_Msk                           (0x1UL << ETH_MACPFR_VTFE_Pos) /*!< 0x00010000 */\n#define ETH_MACPFR_VTFE                               ETH_MACPFR_VTFE_Msk      /* VLAN Tag Filter Enable */\n#define ETH_MACPFR_HPF_Pos                            (10U)\n#define ETH_MACPFR_HPF_Msk                            (0x1UL << ETH_MACPFR_HPF_Pos) /*!< 0x00000400 */\n#define ETH_MACPFR_HPF                                ETH_MACPFR_HPF_Msk       /* Hash or perfect filter */\n#define ETH_MACPFR_SAF_Pos                            (9U)\n#define ETH_MACPFR_SAF_Msk                            (0x1UL << ETH_MACPFR_SAF_Pos) /*!< 0x00000200 */\n#define ETH_MACPFR_SAF                                ETH_MACPFR_SAF_Msk       /* Source address filter enable */\n#define ETH_MACPFR_SAIF_Pos                           (8U)\n#define ETH_MACPFR_SAIF_Msk                           (0x1UL << ETH_MACPFR_SAIF_Pos) /*!< 0x00000100 */\n#define ETH_MACPFR_SAIF                               ETH_MACPFR_SAIF_Msk      /* SA inverse filtering */\n#define ETH_MACPFR_PCF_Pos                            (6U)\n#define ETH_MACPFR_PCF_Msk                            (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */\n#define ETH_MACPFR_PCF                                ETH_MACPFR_PCF_Msk       /* Pass control frames: 4 cases */\n#define ETH_MACPFR_PCF_BLOCKALL                       ((uint32_t)0x00000000)   /* MAC filters all control frames from reaching the application */\n#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos         (6U)\n#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk         (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */\n#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA             ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */\n#define ETH_MACPFR_PCF_FORWARDALL_Pos                 (7U)\n#define ETH_MACPFR_PCF_FORWARDALL_Msk                 (0x1UL << ETH_MACPFR_PCF_FORWARDALL_Pos) /*!< 0x00000080 */\n#define ETH_MACPFR_PCF_FORWARDALL                     ETH_MACPFR_PCF_FORWARDALL_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */\n#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos    (6U)\n#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk    (0x3UL << ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos) /*!< 0x000000C0 */\n#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER        ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk /* MAC forwards control frames that pass the Address Filter. */\n#define ETH_MACPFR_DBF_Pos                            (5U)\n#define ETH_MACPFR_DBF_Msk                            (0x1UL << ETH_MACPFR_DBF_Pos) /*!< 0x00000020 */\n#define ETH_MACPFR_DBF                                ETH_MACPFR_DBF_Msk       /* Disable Broadcast Packets */\n#define ETH_MACPFR_PM_Pos                             (4U)\n#define ETH_MACPFR_PM_Msk                             (0x1UL << ETH_MACPFR_PM_Pos) /*!< 0x00000010 */\n#define ETH_MACPFR_PM                                 ETH_MACPFR_PM_Msk        /* Pass all mutlicast */\n#define ETH_MACPFR_DAIF_Pos                           (3U)\n#define ETH_MACPFR_DAIF_Msk                           (0x1UL << ETH_MACPFR_DAIF_Pos) /*!< 0x00000008 */\n#define ETH_MACPFR_DAIF                               ETH_MACPFR_DAIF_Msk      /* DA Inverse filtering */\n#define ETH_MACPFR_HMC_Pos                            (2U)\n#define ETH_MACPFR_HMC_Msk                            (0x1UL << ETH_MACPFR_HMC_Pos) /*!< 0x00000004 */\n#define ETH_MACPFR_HMC                                ETH_MACPFR_HMC_Msk       /* Hash multicast */\n#define ETH_MACPFR_HUC_Pos                            (1U)\n#define ETH_MACPFR_HUC_Msk                            (0x1UL << ETH_MACPFR_HUC_Pos) /*!< 0x00000002 */\n#define ETH_MACPFR_HUC                                ETH_MACPFR_HUC_Msk       /* Hash unicast */\n#define ETH_MACPFR_PR_Pos                             (0U)\n#define ETH_MACPFR_PR_Msk                             (0x1UL << ETH_MACPFR_PR_Pos) /*!< 0x00000001 */\n#define ETH_MACPFR_PR                                 ETH_MACPFR_PR_Msk        /* Promiscuous mode */\n\n/* Bit definition for Ethernet MAC Watchdog Timeout Register */\n#define ETH_MACWTR_PWE_Pos                            (8U)\n#define ETH_MACWTR_PWE_Msk                            (0x1UL << ETH_MACWTR_PWE_Pos) /*!< 0x00000100 */\n#define ETH_MACWTR_PWE                                ETH_MACWTR_PWE_Msk       /* Programmable Watchdog Enable */\n#define ETH_MACWTR_WTO_Pos                            (0U)\n#define ETH_MACWTR_WTO_Msk                            (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */\n#define ETH_MACWTR_WTO                                ETH_MACWTR_WTO_Msk       /* Watchdog Timeout */\n#define ETH_MACWTR_WTO_2KB                            ((uint32_t)0x00000000)   /* Maximum received packet length 2KB*/\n#define ETH_MACWTR_WTO_3KB                            ((uint32_t)0x00000001)   /* Maximum received packet length 3KB */\n#define ETH_MACWTR_WTO_4KB                            ((uint32_t)0x00000002)   /* Maximum received packet length 4KB */\n#define ETH_MACWTR_WTO_5KB                            ((uint32_t)0x00000003)   /* Maximum received packet length 5KB */\n#define ETH_MACWTR_WTO_6KB                            ((uint32_t)0x00000004)   /* Maximum received packet length 6KB */\n#define ETH_MACWTR_WTO_7KB                            ((uint32_t)0x00000005)   /* Maximum received packet length 7KB */\n#define ETH_MACWTR_WTO_8KB                            ((uint32_t)0x00000006)   /* Maximum received packet length 8KB */\n#define ETH_MACWTR_WTO_9KB                            ((uint32_t)0x00000007)   /* Maximum received packet length 9KB */\n#define ETH_MACWTR_WTO_10KB                           ((uint32_t)0x00000008)   /* Maximum received packet length 10KB */\n#define ETH_MACWTR_WTO_11KB                           ((uint32_t)0x00000009)   /* Maximum received packet length 11KB */\n#define ETH_MACWTR_WTO_12KB                           ((uint32_t)0x0000000A)   /* Maximum received packet length 12KB */\n#define ETH_MACWTR_WTO_13KB                           ((uint32_t)0x0000000B)   /* Maximum received packet length 13KB */\n#define ETH_MACWTR_WTO_14KB                           ((uint32_t)0x0000000C)   /* Maximum received packet length 14KB */\n#define ETH_MACWTR_WTO_15KB                           ((uint32_t)0x0000000D)   /* Maximum received packet length 15KB */\n#define ETH_MACWTR_WTO_16KB                           ((uint32_t)0x0000000E)   /* Maximum received packet length 16KB */\n\n/* Bit definition for Ethernet MAC Hash Table High Register */\n#define ETH_MACHTHR_HTH_Pos                           (0U)\n#define ETH_MACHTHR_HTH_Msk                           (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MACHTHR_HTH                               ETH_MACHTHR_HTH_Msk      /* Hash table high */\n\n/* Bit definition for Ethernet MAC Hash Table Low Register */\n#define ETH_MACHTLR_HTL_Pos                           (0U)\n#define ETH_MACHTLR_HTL_Msk                           (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MACHTLR_HTL                               ETH_MACHTLR_HTL_Msk      /* Hash table low */\n\n/* Bit definition for Ethernet MAC VLAN Tag Register */\n#define ETH_MACVTR_EIVLRXS_Pos                        (31U)\n#define ETH_MACVTR_EIVLRXS_Msk                        (0x1UL << ETH_MACVTR_EIVLRXS_Pos) /*!< 0x80000000 */\n#define ETH_MACVTR_EIVLRXS                            ETH_MACVTR_EIVLRXS_Msk   /* Enable Inner VLAN Tag in Rx Status */\n#define ETH_MACVTR_EIVLS_Pos                          (28U)\n#define ETH_MACVTR_EIVLS_Msk                          (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */\n#define ETH_MACVTR_EIVLS                              ETH_MACVTR_EIVLS_Msk     /* Enable Inner VLAN Tag Stripping on Receive */\n#define ETH_MACVTR_EIVLS_DONOTSTRIP                   ((uint32_t)0x00000000)   /* Do not strip */\n#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos              (28U)\n#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk              (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */\n#define ETH_MACVTR_EIVLS_STRIPIFPASS                  ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */\n#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos             (29U)\n#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk             (0x1UL << ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos) /*!< 0x20000000 */\n#define ETH_MACVTR_EIVLS_STRIPIFFAILS                 ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */\n#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos              (28U)\n#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk              (0x3UL << ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos) /*!< 0x30000000 */\n#define ETH_MACVTR_EIVLS_ALWAYSSTRIP                  ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */\n#define ETH_MACVTR_ERIVLT_Pos                         (27U)\n#define ETH_MACVTR_ERIVLT_Msk                         (0x1UL << ETH_MACVTR_ERIVLT_Pos) /*!< 0x08000000 */\n#define ETH_MACVTR_ERIVLT                             ETH_MACVTR_ERIVLT_Msk    /* Enable Inner VLAN Tag */\n#define ETH_MACVTR_EDVLP_Pos                          (26U)\n#define ETH_MACVTR_EDVLP_Msk                          (0x1UL << ETH_MACVTR_EDVLP_Pos) /*!< 0x04000000 */\n#define ETH_MACVTR_EDVLP                              ETH_MACVTR_EDVLP_Msk     /* Enable Double VLAN Processing */\n#define ETH_MACVTR_VTHM_Pos                           (25U)\n#define ETH_MACVTR_VTHM_Msk                           (0x1UL << ETH_MACVTR_VTHM_Pos) /*!< 0x02000000 */\n#define ETH_MACVTR_VTHM                               ETH_MACVTR_VTHM_Msk      /* VLAN Tag Hash Table Match Enable */\n#define ETH_MACVTR_EVLRXS_Pos                         (24U)\n#define ETH_MACVTR_EVLRXS_Msk                         (0x1UL << ETH_MACVTR_EVLRXS_Pos) /*!< 0x01000000 */\n#define ETH_MACVTR_EVLRXS                             ETH_MACVTR_EVLRXS_Msk    /* Enable VLAN Tag in Rx status */\n#define ETH_MACVTR_EVLS_Pos                           (21U)\n#define ETH_MACVTR_EVLS_Msk                           (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */\n#define ETH_MACVTR_EVLS                               ETH_MACVTR_EVLS_Msk      /* Enable VLAN Tag Stripping on Receive */\n#define ETH_MACVTR_EVLS_DONOTSTRIP                    ((uint32_t)0x00000000)   /* Do not strip */\n#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos               (21U)\n#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk               (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */\n#define ETH_MACVTR_EVLS_STRIPIFPASS                   ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */\n#define ETH_MACVTR_EVLS_STRIPIFFAILS_Pos              (22U)\n#define ETH_MACVTR_EVLS_STRIPIFFAILS_Msk              (0x1UL << ETH_MACVTR_EVLS_STRIPIFFAILS_Pos) /*!< 0x00400000 */\n#define ETH_MACVTR_EVLS_STRIPIFFAILS                  ETH_MACVTR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */\n#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos               (21U)\n#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk               (0x3UL << ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos) /*!< 0x00600000 */\n#define ETH_MACVTR_EVLS_ALWAYSSTRIP                   ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk /* Always strip */\n#define ETH_MACVTR_DOVLTC_Pos                         (20U)\n#define ETH_MACVTR_DOVLTC_Msk                         (0x1UL << ETH_MACVTR_DOVLTC_Pos) /*!< 0x00100000 */\n#define ETH_MACVTR_DOVLTC                             ETH_MACVTR_DOVLTC_Msk    /* Disable VLAN Type Check */\n#define ETH_MACVTR_ERSVLM_Pos                         (19U)\n#define ETH_MACVTR_ERSVLM_Msk                         (0x1UL << ETH_MACVTR_ERSVLM_Pos) /*!< 0x00080000 */\n#define ETH_MACVTR_ERSVLM                             ETH_MACVTR_ERSVLM_Msk    /* Enable Receive S-VLAN Match */\n#define ETH_MACVTR_ESVL_Pos                           (18U)\n#define ETH_MACVTR_ESVL_Msk                           (0x1UL << ETH_MACVTR_ESVL_Pos) /*!< 0x00040000 */\n#define ETH_MACVTR_ESVL                               ETH_MACVTR_ESVL_Msk      /* Enable S-VLAN */\n#define ETH_MACVTR_VTIM_Pos                           (17U)\n#define ETH_MACVTR_VTIM_Msk                           (0x1UL << ETH_MACVTR_VTIM_Pos) /*!< 0x00020000 */\n#define ETH_MACVTR_VTIM                               ETH_MACVTR_VTIM_Msk      /* VLAN Tag Inverse Match Enable */\n#define ETH_MACVTR_ETV_Pos                            (16U)\n#define ETH_MACVTR_ETV_Msk                            (0x1UL << ETH_MACVTR_ETV_Pos) /*!< 0x00010000 */\n#define ETH_MACVTR_ETV                                ETH_MACVTR_ETV_Msk       /* Enable 12-Bit VLAN Tag Comparison */\n#define ETH_MACVTR_VL_Pos                             (0U)\n#define ETH_MACVTR_VL_Msk                             (0xFFFFUL << ETH_MACVTR_VL_Pos) /*!< 0x0000FFFF */\n#define ETH_MACVTR_VL                                 ETH_MACVTR_VL_Msk        /* VLAN Tag Identifier for Receive Packets */\n#define ETH_MACVTR_VL_UP_Pos                          (13U)\n#define ETH_MACVTR_VL_UP_Msk                          (0x7UL << ETH_MACVTR_VL_UP_Pos) /*!< 0x0000E000 */\n#define ETH_MACVTR_VL_UP                              ETH_MACVTR_VL_UP_Msk     /* User Priority */\n#define ETH_MACVTR_VL_CFIDEI_Pos                      (12U)\n#define ETH_MACVTR_VL_CFIDEI_Msk                      (0x1UL << ETH_MACVTR_VL_CFIDEI_Pos) /*!< 0x00001000 */\n#define ETH_MACVTR_VL_CFIDEI                          ETH_MACVTR_VL_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */\n#define ETH_MACVTR_VL_VID_Pos                         (0U)\n#define ETH_MACVTR_VL_VID_Msk                         (0xFFFUL << ETH_MACVTR_VL_VID_Pos) /*!< 0x00000FFF */\n#define ETH_MACVTR_VL_VID                             ETH_MACVTR_VL_VID_Msk    /* VLAN Identifier field of VLAN tag */\n\n/* Bit definition for Ethernet MAC VLAN Hash Table Register */\n#define ETH_MACVHTR_VLHT_Pos                          (0U)\n#define ETH_MACVHTR_VLHT_Msk                          (0xFFFFUL << ETH_MACVHTR_VLHT_Pos) /*!< 0x0000FFFF */\n#define ETH_MACVHTR_VLHT                              ETH_MACVHTR_VLHT_Msk     /* VLAN Hash Table */\n\n/* Bit definition for Ethernet MAC VLAN Incl Register */\n#define ETH_MACVIR_VLTI_Pos                           (20U)\n#define ETH_MACVIR_VLTI_Msk                           (0x1UL << ETH_MACVIR_VLTI_Pos) /*!< 0x00100000 */\n#define ETH_MACVIR_VLTI                               ETH_MACVIR_VLTI_Msk      /* VLAN Tag Input */\n#define ETH_MACVIR_CSVL_Pos                           (19U)\n#define ETH_MACVIR_CSVL_Msk                           (0x1UL << ETH_MACVIR_CSVL_Pos) /*!< 0x00080000 */\n#define ETH_MACVIR_CSVL                               ETH_MACVIR_CSVL_Msk      /* C-VLAN or S-VLAN */\n#define ETH_MACVIR_VLP_Pos                            (18U)\n#define ETH_MACVIR_VLP_Msk                            (0x1UL << ETH_MACVIR_VLP_Pos) /*!< 0x00040000 */\n#define ETH_MACVIR_VLP                                ETH_MACVIR_VLP_Msk       /* VLAN Priority Control */\n#define ETH_MACVIR_VLC_Pos                            (16U)\n#define ETH_MACVIR_VLC_Msk                            (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */\n#define ETH_MACVIR_VLC                                ETH_MACVIR_VLC_Msk       /* VLAN Tag Control in Transmit Packets */\n#define ETH_MACVIR_VLC_NOVLANTAG                      ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */\n#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos              (16U)\n#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk              (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */\n#define ETH_MACVIR_VLC_VLANTAGDELETE                  ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */\n#define ETH_MACVIR_VLC_VLANTAGINSERT_Pos              (17U)\n#define ETH_MACVIR_VLC_VLANTAGINSERT_Msk              (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */\n#define ETH_MACVIR_VLC_VLANTAGINSERT                  ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */\n#define ETH_MACVIR_VLC_VLANTAGREPLACE_Pos             (16U)\n#define ETH_MACVIR_VLC_VLANTAGREPLACE_Msk             (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */\n#define ETH_MACVIR_VLC_VLANTAGREPLACE                 ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */\n#define ETH_MACVIR_VLT_Pos                            (0U)\n#define ETH_MACVIR_VLT_Msk                            (0xFFFFUL << ETH_MACVIR_VLT_Pos) /*!< 0x0000FFFF */\n#define ETH_MACVIR_VLT                                ETH_MACVIR_VLT_Msk       /* VLAN Tag for Transmit Packets */\n#define ETH_MACVIR_VLT_UP_Pos                         (13U)\n#define ETH_MACVIR_VLT_UP_Msk                         (0x7UL << ETH_MACVIR_VLT_UP_Pos) /*!< 0x0000E000 */\n#define ETH_MACVIR_VLT_UP                             ETH_MACVIR_VLT_UP_Msk    /* User Priority */\n#define ETH_MACVIR_VLT_CFIDEI_Pos                     (12U)\n#define ETH_MACVIR_VLT_CFIDEI_Msk                     (0x1UL << ETH_MACVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */\n#define ETH_MACVIR_VLT_CFIDEI                         ETH_MACVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */\n#define ETH_MACVIR_VLT_VID_Pos                        (0U)\n#define ETH_MACVIR_VLT_VID_Msk                        (0xFFFUL << ETH_MACVIR_VLT_VID_Pos) /*!< 0x00000FFF */\n#define ETH_MACVIR_VLT_VID                            ETH_MACVIR_VLT_VID_Msk   /* VLAN Identifier field of VLAN tag */\n\n/* Bit definition for Ethernet MAC Inner_VLAN Incl Register */\n#define ETH_MACIVIR_VLTI_Pos                          (20U)\n#define ETH_MACIVIR_VLTI_Msk                          (0x1UL << ETH_MACIVIR_VLTI_Pos) /*!< 0x00100000 */\n#define ETH_MACIVIR_VLTI                              ETH_MACIVIR_VLTI_Msk     /* VLAN Tag Input */\n#define ETH_MACIVIR_CSVL_Pos                          (19U)\n#define ETH_MACIVIR_CSVL_Msk                          (0x1UL << ETH_MACIVIR_CSVL_Pos) /*!< 0x00080000 */\n#define ETH_MACIVIR_CSVL                              ETH_MACIVIR_CSVL_Msk     /* C-VLAN or S-VLAN */\n#define ETH_MACIVIR_VLP_Pos                           (18U)\n#define ETH_MACIVIR_VLP_Msk                           (0x1UL << ETH_MACIVIR_VLP_Pos) /*!< 0x00040000 */\n#define ETH_MACIVIR_VLP                               ETH_MACIVIR_VLP_Msk      /* VLAN Priority Control */\n#define ETH_MACIVIR_VLC_Pos                           (16U)\n#define ETH_MACIVIR_VLC_Msk                           (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */\n#define ETH_MACIVIR_VLC                               ETH_MACIVIR_VLC_Msk      /* VLAN Tag Control in Transmit Packets */\n#define ETH_MACIVIR_VLC_NOVLANTAG                     ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */\n#define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos             (16U)\n#define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk             (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */\n#define ETH_MACIVIR_VLC_VLANTAGDELETE                 ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */\n#define ETH_MACIVIR_VLC_VLANTAGINSERT_Pos             (17U)\n#define ETH_MACIVIR_VLC_VLANTAGINSERT_Msk             (0x1UL << ETH_MACIVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */\n#define ETH_MACIVIR_VLC_VLANTAGINSERT                 ETH_MACIVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */\n#define ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos            (16U)\n#define ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk            (0x3UL << ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */\n#define ETH_MACIVIR_VLC_VLANTAGREPLACE                ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */\n#define ETH_MACIVIR_VLT_Pos                           (0U)\n#define ETH_MACIVIR_VLT_Msk                           (0xFFFFUL << ETH_MACIVIR_VLT_Pos) /*!< 0x0000FFFF */\n#define ETH_MACIVIR_VLT                               ETH_MACIVIR_VLT_Msk      /* VLAN Tag for Transmit Packets */\n#define ETH_MACIVIR_VLT_UP_Pos                        (13U)\n#define ETH_MACIVIR_VLT_UP_Msk                        (0x7UL << ETH_MACIVIR_VLT_UP_Pos) /*!< 0x0000E000 */\n#define ETH_MACIVIR_VLT_UP                            ETH_MACIVIR_VLT_UP_Msk   /* User Priority */\n#define ETH_MACIVIR_VLT_CFIDEI_Pos                    (12U)\n#define ETH_MACIVIR_VLT_CFIDEI_Msk                    (0x1UL << ETH_MACIVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */\n#define ETH_MACIVIR_VLT_CFIDEI                        ETH_MACIVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */\n#define ETH_MACIVIR_VLT_VID_Pos                       (0U)\n#define ETH_MACIVIR_VLT_VID_Msk                       (0xFFFUL << ETH_MACIVIR_VLT_VID_Pos) /*!< 0x00000FFF */\n#define ETH_MACIVIR_VLT_VID                           ETH_MACIVIR_VLT_VID_Msk  /* VLAN Identifier field of VLAN tag */\n\n/* Bit definition for Ethernet MAC Tx Flow Ctrl Register */\n#define ETH_MACTFCR_PT_Pos                            (16U)\n#define ETH_MACTFCR_PT_Msk                            (0xFFFFUL << ETH_MACTFCR_PT_Pos) /*!< 0xFFFF0000 */\n#define ETH_MACTFCR_PT                                ETH_MACTFCR_PT_Msk       /* Pause Time */\n#define ETH_MACTFCR_DZPQ_Pos                          (7U)\n#define ETH_MACTFCR_DZPQ_Msk                          (0x1UL << ETH_MACTFCR_DZPQ_Pos) /*!< 0x00000080 */\n#define ETH_MACTFCR_DZPQ                              ETH_MACTFCR_DZPQ_Msk     /* Disable Zero-Quanta Pause */\n#define ETH_MACTFCR_PLT_Pos                           (4U)\n#define ETH_MACTFCR_PLT_Msk                           (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */\n#define ETH_MACTFCR_PLT                               ETH_MACTFCR_PLT_Msk      /* Pause Low Threshold */\n#define ETH_MACTFCR_PLT_MINUS4                        ((uint32_t)0x00000000)   /* Pause time minus 4 slot times */\n#define ETH_MACTFCR_PLT_MINUS28_Pos                   (4U)\n#define ETH_MACTFCR_PLT_MINUS28_Msk                   (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */\n#define ETH_MACTFCR_PLT_MINUS28                       ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */\n#define ETH_MACTFCR_PLT_MINUS36_Pos                   (5U)\n#define ETH_MACTFCR_PLT_MINUS36_Msk                   (0x1UL << ETH_MACTFCR_PLT_MINUS36_Pos) /*!< 0x00000020 */\n#define ETH_MACTFCR_PLT_MINUS36                       ETH_MACTFCR_PLT_MINUS36_Msk /* Pause time minus 36 slot times */\n#define ETH_MACTFCR_PLT_MINUS144_Pos                  (4U)\n#define ETH_MACTFCR_PLT_MINUS144_Msk                  (0x3UL << ETH_MACTFCR_PLT_MINUS144_Pos) /*!< 0x00000030 */\n#define ETH_MACTFCR_PLT_MINUS144                      ETH_MACTFCR_PLT_MINUS144_Msk /* Pause time minus 144 slot times */\n#define ETH_MACTFCR_PLT_MINUS256_Pos                  (6U)\n#define ETH_MACTFCR_PLT_MINUS256_Msk                  (0x1UL << ETH_MACTFCR_PLT_MINUS256_Pos) /*!< 0x00000040 */\n#define ETH_MACTFCR_PLT_MINUS256                      ETH_MACTFCR_PLT_MINUS256_Msk /* Pause time minus 256 slot times */\n#define ETH_MACTFCR_PLT_MINUS512_Pos                  (4U)\n#define ETH_MACTFCR_PLT_MINUS512_Msk                  (0x5UL << ETH_MACTFCR_PLT_MINUS512_Pos) /*!< 0x00000050 */\n#define ETH_MACTFCR_PLT_MINUS512                      ETH_MACTFCR_PLT_MINUS512_Msk /* Pause time minus 512 slot times */\n#define ETH_MACTFCR_TFE_Pos                           (1U)\n#define ETH_MACTFCR_TFE_Msk                           (0x1UL << ETH_MACTFCR_TFE_Pos) /*!< 0x00000002 */\n#define ETH_MACTFCR_TFE                               ETH_MACTFCR_TFE_Msk      /* Transmit Flow Control Enable */\n#define ETH_MACTFCR_FCB_Pos                           (0U)\n#define ETH_MACTFCR_FCB_Msk                           (0x1UL << ETH_MACTFCR_FCB_Pos) /*!< 0x00000001 */\n#define ETH_MACTFCR_FCB                               ETH_MACTFCR_FCB_Msk      /* Flow Control Busy or Backpressure Activate */\n\n/* Bit definition for Ethernet MAC Rx Flow Ctrl Register */\n#define ETH_MACRFCR_UP_Pos                            (1U)\n#define ETH_MACRFCR_UP_Msk                            (0x1UL << ETH_MACRFCR_UP_Pos) /*!< 0x00000002 */\n#define ETH_MACRFCR_UP                                ETH_MACRFCR_UP_Msk       /* Unicast Pause Packet Detect */\n#define ETH_MACRFCR_RFE_Pos                           (0U)\n#define ETH_MACRFCR_RFE_Msk                           (0x1UL << ETH_MACRFCR_RFE_Pos) /*!< 0x00000001 */\n#define ETH_MACRFCR_RFE                               ETH_MACRFCR_RFE_Msk      /* Receive Flow Control Enable */\n\n/* Bit definition for Ethernet MAC Interrupt Status Register */\n#define ETH_MACISR_RXSTSIS_Pos                        (14U)\n#define ETH_MACISR_RXSTSIS_Msk                        (0x1UL << ETH_MACISR_RXSTSIS_Pos) /*!< 0x00004000 */\n#define ETH_MACISR_RXSTSIS                            ETH_MACISR_RXSTSIS_Msk   /* Receive Status Interrupt */\n#define ETH_MACISR_TXSTSIS_Pos                        (13U)\n#define ETH_MACISR_TXSTSIS_Msk                        (0x1UL << ETH_MACISR_TXSTSIS_Pos) /*!< 0x00002000 */\n#define ETH_MACISR_TXSTSIS                            ETH_MACISR_TXSTSIS_Msk   /* Transmit Status Interrupt */\n#define ETH_MACISR_TSIS_Pos                           (12U)\n#define ETH_MACISR_TSIS_Msk                           (0x1UL << ETH_MACISR_TSIS_Pos) /*!< 0x00001000 */\n#define ETH_MACISR_TSIS                               ETH_MACISR_TSIS_Msk      /* Timestamp Interrupt Status */\n#define ETH_MACISR_MMCTXIS_Pos                        (10U)\n#define ETH_MACISR_MMCTXIS_Msk                        (0x1UL << ETH_MACISR_MMCTXIS_Pos) /*!< 0x00000400 */\n#define ETH_MACISR_MMCTXIS                            ETH_MACISR_MMCTXIS_Msk   /* MMC Transmit Interrupt Status */\n#define ETH_MACISR_MMCRXIS_Pos                        (9U)\n#define ETH_MACISR_MMCRXIS_Msk                        (0x1UL << ETH_MACISR_MMCRXIS_Pos) /*!< 0x00000200 */\n#define ETH_MACISR_MMCRXIS                            ETH_MACISR_MMCRXIS_Msk   /* MMC Receive Interrupt Status */\n#define ETH_MACISR_MMCIS_Pos                          (8U)\n#define ETH_MACISR_MMCIS_Msk                          (0x1UL << ETH_MACISR_MMCIS_Pos) /*!< 0x00000100 */\n#define ETH_MACISR_MMCIS                              ETH_MACISR_MMCIS_Msk     /* MMC Interrupt Status */\n#define ETH_MACISR_LPIIS_Pos                          (5U)\n#define ETH_MACISR_LPIIS_Msk                          (0x1UL << ETH_MACISR_LPIIS_Pos) /*!< 0x00000020 */\n#define ETH_MACISR_LPIIS                              ETH_MACISR_LPIIS_Msk     /* LPI Interrupt Status */\n#define ETH_MACISR_PMTIS_Pos                          (4U)\n#define ETH_MACISR_PMTIS_Msk                          (0x1UL << ETH_MACISR_PMTIS_Pos) /*!< 0x00000010 */\n#define ETH_MACISR_PMTIS                              ETH_MACISR_PMTIS_Msk     /* PMT Interrupt Status */\n#define ETH_MACISR_PHYIS_Pos                          (3U)\n#define ETH_MACISR_PHYIS_Msk                          (0x1UL << ETH_MACISR_PHYIS_Pos) /*!< 0x00000008 */\n#define ETH_MACISR_PHYIS                              ETH_MACISR_PHYIS_Msk     /* PHY Interrupt */\n\n/* Bit definition for Ethernet MAC Interrupt Enable Register */\n#define ETH_MACIER_RXSTSIE_Pos                        (14U)\n#define ETH_MACIER_RXSTSIE_Msk                        (0x1UL << ETH_MACIER_RXSTSIE_Pos) /*!< 0x00004000 */\n#define ETH_MACIER_RXSTSIE                            ETH_MACIER_RXSTSIE_Msk   /* Receive Status Interrupt Enable */\n#define ETH_MACIER_TXSTSIE_Pos                        (13U)\n#define ETH_MACIER_TXSTSIE_Msk                        (0x1UL << ETH_MACIER_TXSTSIE_Pos) /*!< 0x00002000 */\n#define ETH_MACIER_TXSTSIE                            ETH_MACIER_TXSTSIE_Msk   /* Transmit Status Interrupt Enable */\n#define ETH_MACIER_TSIE_Pos                           (12U)\n#define ETH_MACIER_TSIE_Msk                           (0x1UL << ETH_MACIER_TSIE_Pos) /*!< 0x00001000 */\n#define ETH_MACIER_TSIE                               ETH_MACIER_TSIE_Msk      /* Timestamp Interrupt Enable */\n#define ETH_MACIER_LPIIE_Pos                          (5U)\n#define ETH_MACIER_LPIIE_Msk                          (0x1UL << ETH_MACIER_LPIIE_Pos) /*!< 0x00000020 */\n#define ETH_MACIER_LPIIE                              ETH_MACIER_LPIIE_Msk     /* LPI Interrupt Enable */\n#define ETH_MACIER_PMTIE_Pos                          (4U)\n#define ETH_MACIER_PMTIE_Msk                          (0x1UL << ETH_MACIER_PMTIE_Pos) /*!< 0x00000010 */\n#define ETH_MACIER_PMTIE                              ETH_MACIER_PMTIE_Msk     /* PMT Interrupt Enable */\n#define ETH_MACIER_PHYIE_Pos                          (3U)\n#define ETH_MACIER_PHYIE_Msk                          (0x1UL << ETH_MACIER_PHYIE_Pos) /*!< 0x00000008 */\n#define ETH_MACIER_PHYIE                              ETH_MACIER_PHYIE_Msk     /* PHY Interrupt Enable */\n\n/* Bit definition for Ethernet MAC Rx Tx Status Register */\n#define ETH_MACRXTXSR_RWT_Pos                         (8U)\n#define ETH_MACRXTXSR_RWT_Msk                         (0x1UL << ETH_MACRXTXSR_RWT_Pos) /*!< 0x00000100 */\n#define ETH_MACRXTXSR_RWT                             ETH_MACRXTXSR_RWT_Msk    /* Receive Watchdog Timeout */\n#define ETH_MACRXTXSR_EXCOL_Pos                       (5U)\n#define ETH_MACRXTXSR_EXCOL_Msk                       (0x1UL << ETH_MACRXTXSR_EXCOL_Pos) /*!< 0x00000020 */\n#define ETH_MACRXTXSR_EXCOL                           ETH_MACRXTXSR_EXCOL_Msk  /* Excessive Collisions */\n#define ETH_MACRXTXSR_LCOL_Pos                        (4U)\n#define ETH_MACRXTXSR_LCOL_Msk                        (0x1UL << ETH_MACRXTXSR_LCOL_Pos) /*!< 0x00000010 */\n#define ETH_MACRXTXSR_LCOL                            ETH_MACRXTXSR_LCOL_Msk   /* Late Collision */\n#define ETH_MACRXTXSR_EXDEF_Pos                       (3U)\n#define ETH_MACRXTXSR_EXDEF_Msk                       (0x1UL << ETH_MACRXTXSR_EXDEF_Pos) /*!< 0x00000008 */\n#define ETH_MACRXTXSR_EXDEF                           ETH_MACRXTXSR_EXDEF_Msk  /* Excessive Deferral */\n#define ETH_MACRXTXSR_LCARR_Pos                       (2U)\n#define ETH_MACRXTXSR_LCARR_Msk                       (0x1UL << ETH_MACRXTXSR_LCARR_Pos) /*!< 0x00000004 */\n#define ETH_MACRXTXSR_LCARR                           ETH_MACRXTXSR_LCARR_Msk  /* Loss of Carrier */\n#define ETH_MACRXTXSR_NCARR_Pos                       (1U)\n#define ETH_MACRXTXSR_NCARR_Msk                       (0x1UL << ETH_MACRXTXSR_NCARR_Pos) /*!< 0x00000002 */\n#define ETH_MACRXTXSR_NCARR                           ETH_MACRXTXSR_NCARR_Msk  /* No Carrier */\n#define ETH_MACRXTXSR_TJT_Pos                         (0U)\n#define ETH_MACRXTXSR_TJT_Msk                         (0x1UL << ETH_MACRXTXSR_TJT_Pos) /*!< 0x00000001 */\n#define ETH_MACRXTXSR_TJT                             ETH_MACRXTXSR_TJT_Msk    /* Transmit Jabber Timeout */\n\n/* Bit definition for Ethernet MAC PMT Control Status Register */\n#define ETH_MACPCSR_RWKFILTRST_Pos                    (31U)\n#define ETH_MACPCSR_RWKFILTRST_Msk                    (0x1UL << ETH_MACPCSR_RWKFILTRST_Pos) /*!< 0x80000000 */\n#define ETH_MACPCSR_RWKFILTRST                        ETH_MACPCSR_RWKFILTRST_Msk /* Remote Wake-Up Packet Filter Register Pointer Reset */\n#define ETH_MACPCSR_RWKPTR_Pos                        (24U)\n#define ETH_MACPCSR_RWKPTR_Msk                        (0x1FUL << ETH_MACPCSR_RWKPTR_Pos) /*!< 0x1F000000 */\n#define ETH_MACPCSR_RWKPTR                            ETH_MACPCSR_RWKPTR_Msk   /* Remote Wake-up FIFO Pointer */\n#define ETH_MACPCSR_RWKPFE_Pos                        (10U)\n#define ETH_MACPCSR_RWKPFE_Msk                        (0x1UL << ETH_MACPCSR_RWKPFE_Pos) /*!< 0x00000400 */\n#define ETH_MACPCSR_RWKPFE                            ETH_MACPCSR_RWKPFE_Msk   /* Remote Wake-up Packet Forwarding Enable */\n#define ETH_MACPCSR_GLBLUCAST_Pos                     (9U)\n#define ETH_MACPCSR_GLBLUCAST_Msk                     (0x1UL << ETH_MACPCSR_GLBLUCAST_Pos) /*!< 0x00000200 */\n#define ETH_MACPCSR_GLBLUCAST                         ETH_MACPCSR_GLBLUCAST_Msk /* Global Unicast */\n#define ETH_MACPCSR_RWKPRCVD_Pos                      (6U)\n#define ETH_MACPCSR_RWKPRCVD_Msk                      (0x1UL << ETH_MACPCSR_RWKPRCVD_Pos) /*!< 0x00000040 */\n#define ETH_MACPCSR_RWKPRCVD                          ETH_MACPCSR_RWKPRCVD_Msk /* Remote Wake-Up Packet Received */\n#define ETH_MACPCSR_MGKPRCVD_Pos                      (5U)\n#define ETH_MACPCSR_MGKPRCVD_Msk                      (0x1UL << ETH_MACPCSR_MGKPRCVD_Pos) /*!< 0x00000020 */\n#define ETH_MACPCSR_MGKPRCVD                          ETH_MACPCSR_MGKPRCVD_Msk /* Magic Packet Received */\n#define ETH_MACPCSR_RWKPKTEN_Pos                      (2U)\n#define ETH_MACPCSR_RWKPKTEN_Msk                      (0x1UL << ETH_MACPCSR_RWKPKTEN_Pos) /*!< 0x00000004 */\n#define ETH_MACPCSR_RWKPKTEN                          ETH_MACPCSR_RWKPKTEN_Msk /* Remote Wake-Up Packet Enable */\n#define ETH_MACPCSR_MGKPKTEN_Pos                      (1U)\n#define ETH_MACPCSR_MGKPKTEN_Msk                      (0x1UL << ETH_MACPCSR_MGKPKTEN_Pos) /*!< 0x00000002 */\n#define ETH_MACPCSR_MGKPKTEN                          ETH_MACPCSR_MGKPKTEN_Msk /* Magic Packet Enable */\n#define ETH_MACPCSR_PWRDWN_Pos                        (0U)\n#define ETH_MACPCSR_PWRDWN_Msk                        (0x1UL << ETH_MACPCSR_PWRDWN_Pos) /*!< 0x00000001 */\n#define ETH_MACPCSR_PWRDWN                            ETH_MACPCSR_PWRDWN_Msk   /* Power Down */\n\n/* Bit definition for Ethernet MAC Remote Wake-Up Packet Filter Register */\n#define ETH_MACRWUPFR_D_Pos                           (0U)\n#define ETH_MACRWUPFR_D_Msk                           (0xFFFFFFFFUL << ETH_MACRWUPFR_D_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MACRWUPFR_D                               ETH_MACRWUPFR_D_Msk      /* Wake-up Packet filter register data */\n\n/* Bit definition for Ethernet MAC LPI Control Status Register */\n#define ETH_MACLCSR_LPITCSE_Pos                       (21U)\n#define ETH_MACLCSR_LPITCSE_Msk                       (0x1UL << ETH_MACLCSR_LPITCSE_Pos) /*!< 0x00200000 */\n#define ETH_MACLCSR_LPITCSE                           ETH_MACLCSR_LPITCSE_Msk  /* LPI Tx Clock Stop Enable */\n#define ETH_MACLCSR_LPITE_Pos                         (20U)\n#define ETH_MACLCSR_LPITE_Msk                         (0x1UL << ETH_MACLCSR_LPITE_Pos) /*!< 0x00100000 */\n#define ETH_MACLCSR_LPITE                             ETH_MACLCSR_LPITE_Msk    /* LPI Timer Enable */\n#define ETH_MACLCSR_LPITXA_Pos                        (19U)\n#define ETH_MACLCSR_LPITXA_Msk                        (0x1UL << ETH_MACLCSR_LPITXA_Pos) /*!< 0x00080000 */\n#define ETH_MACLCSR_LPITXA                            ETH_MACLCSR_LPITXA_Msk   /* LPI Tx Automate */\n#define ETH_MACLCSR_PLS_Pos                           (17U)\n#define ETH_MACLCSR_PLS_Msk                           (0x1UL << ETH_MACLCSR_PLS_Pos) /*!< 0x00020000 */\n#define ETH_MACLCSR_PLS                               ETH_MACLCSR_PLS_Msk      /* PHY Link Status */\n#define ETH_MACLCSR_LPIEN_Pos                         (16U)\n#define ETH_MACLCSR_LPIEN_Msk                         (0x1UL << ETH_MACLCSR_LPIEN_Pos) /*!< 0x00010000 */\n#define ETH_MACLCSR_LPIEN                             ETH_MACLCSR_LPIEN_Msk    /* LPI Enable */\n#define ETH_MACLCSR_RLPIST_Pos                        (9U)\n#define ETH_MACLCSR_RLPIST_Msk                        (0x1UL << ETH_MACLCSR_RLPIST_Pos) /*!< 0x00000200 */\n#define ETH_MACLCSR_RLPIST                            ETH_MACLCSR_RLPIST_Msk   /* Receive LPI State */\n#define ETH_MACLCSR_TLPIST_Pos                        (8U)\n#define ETH_MACLCSR_TLPIST_Msk                        (0x1UL << ETH_MACLCSR_TLPIST_Pos) /*!< 0x00000100 */\n#define ETH_MACLCSR_TLPIST                            ETH_MACLCSR_TLPIST_Msk   /* Transmit LPI State */\n#define ETH_MACLCSR_RLPIEX_Pos                        (3U)\n#define ETH_MACLCSR_RLPIEX_Msk                        (0x1UL << ETH_MACLCSR_RLPIEX_Pos) /*!< 0x00000008 */\n#define ETH_MACLCSR_RLPIEX                            ETH_MACLCSR_RLPIEX_Msk   /* Receive LPI Exit */\n#define ETH_MACLCSR_RLPIEN_Pos                        (2U)\n#define ETH_MACLCSR_RLPIEN_Msk                        (0x1UL << ETH_MACLCSR_RLPIEN_Pos) /*!< 0x00000004 */\n#define ETH_MACLCSR_RLPIEN                            ETH_MACLCSR_RLPIEN_Msk   /* Receive LPI Entry */\n#define ETH_MACLCSR_TLPIEX_Pos                        (1U)\n#define ETH_MACLCSR_TLPIEX_Msk                        (0x1UL << ETH_MACLCSR_TLPIEX_Pos) /*!< 0x00000002 */\n#define ETH_MACLCSR_TLPIEX                            ETH_MACLCSR_TLPIEX_Msk   /* Transmit LPI Exit */\n#define ETH_MACLCSR_TLPIEN_Pos                        (0U)\n#define ETH_MACLCSR_TLPIEN_Msk                        (0x1UL << ETH_MACLCSR_TLPIEN_Pos) /*!< 0x00000001 */\n#define ETH_MACLCSR_TLPIEN                            ETH_MACLCSR_TLPIEN_Msk   /* Transmit LPI Entry */\n\n/* Bit definition for Ethernet MAC LPI Timers Control Register */\n#define ETH_MACLTCR_LST_Pos                           (16U)\n#define ETH_MACLTCR_LST_Msk                           (0x3FFUL << ETH_MACLTCR_LST_Pos) /*!< 0x03FF0000 */\n#define ETH_MACLTCR_LST                               ETH_MACLTCR_LST_Msk      /* LPI LS TIMER */\n#define ETH_MACLTCR_TWT_Pos                           (0U)\n#define ETH_MACLTCR_TWT_Msk                           (0xFFFFUL << ETH_MACLTCR_TWT_Pos) /*!< 0x0000FFFF */\n#define ETH_MACLTCR_TWT                               ETH_MACLTCR_TWT_Msk      /* LPI TW TIMER */\n\n/* Bit definition for Ethernet MAC LPI Entry Timer Register */\n#define ETH_MACLETR_LPIET_Pos                         (0U)\n#define ETH_MACLETR_LPIET_Msk                         (0xFFFFFUL << ETH_MACLETR_LPIET_Pos) /*!< 0x000FFFFF */\n#define ETH_MACLETR_LPIET                             ETH_MACLETR_LPIET_Msk    /* LPI Entry Timer */\n\n/* Bit definition for Ethernet MAC 1US Tic Counter Register */\n#define ETH_MAC1USTCR_TIC1USCNTR_Pos                  (0U)\n#define ETH_MAC1USTCR_TIC1USCNTR_Msk                  (0xFFFUL << ETH_MAC1USTCR_TIC1USCNTR_Pos) /*!< 0x00000FFF */\n#define ETH_MAC1USTCR_TIC1USCNTR                      ETH_MAC1USTCR_TIC1USCNTR_Msk /* 1US TIC Counter */\n\n/* Bit definition for Ethernet MAC Version Register */\n#define ETH_MACVR_USERVER_Pos                         (8U)\n#define ETH_MACVR_USERVER_Msk                         (0xFFUL << ETH_MACVR_USERVER_Pos) /*!< 0x0000FF00 */\n#define ETH_MACVR_USERVER                             ETH_MACVR_USERVER_Msk    /* User-defined Version */\n#define ETH_MACVR_SNPSVER_Pos                         (0U)\n#define ETH_MACVR_SNPSVER_Msk                         (0xFFUL << ETH_MACVR_SNPSVER_Pos) /*!< 0x000000FF */\n#define ETH_MACVR_SNPSVER                             ETH_MACVR_SNPSVER_Msk    /* Synopsys-defined Version */\n\n/* Bit definition for Ethernet MAC Debug Register */\n#define ETH_MACDR_TFCSTS_Pos                          (17U)\n#define ETH_MACDR_TFCSTS_Msk                          (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */\n#define ETH_MACDR_TFCSTS                              ETH_MACDR_TFCSTS_Msk     /* MAC Transmit Packet Controller Status */\n#define ETH_MACDR_TFCSTS_IDLE                         ((uint32_t)0x00000000)   /* Idle state */\n#define ETH_MACDR_TFCSTS_WAIT_Pos                     (17U)\n#define ETH_MACDR_TFCSTS_WAIT_Msk                     (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */\n#define ETH_MACDR_TFCSTS_WAIT                         ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */\n#define ETH_MACDR_TFCSTS_GENERATEPCP_Pos              (18U)\n#define ETH_MACDR_TFCSTS_GENERATEPCP_Msk              (0x1UL << ETH_MACDR_TFCSTS_GENERATEPCP_Pos) /*!< 0x00040000 */\n#define ETH_MACDR_TFCSTS_GENERATEPCP                  ETH_MACDR_TFCSTS_GENERATEPCP_Msk /* Generating and transmitting a Pause control packet */\n#define ETH_MACDR_TFCSTS_TRASFERIP_Pos                (17U)\n#define ETH_MACDR_TFCSTS_TRASFERIP_Msk                (0x3UL << ETH_MACDR_TFCSTS_TRASFERIP_Pos) /*!< 0x00060000 */\n#define ETH_MACDR_TFCSTS_TRASFERIP                    ETH_MACDR_TFCSTS_TRASFERIP_Msk /* Transferring input packet for transmission */\n#define ETH_MACDR_TPESTS_Pos                          (16U)\n#define ETH_MACDR_TPESTS_Msk                          (0x1UL << ETH_MACDR_TPESTS_Pos) /*!< 0x00010000 */\n#define ETH_MACDR_TPESTS                              ETH_MACDR_TPESTS_Msk     /* MAC Receive Packet Controller FIFO Status */\n#define ETH_MACDR_RFCFCSTS_Pos                        (1U)\n#define ETH_MACDR_RFCFCSTS_Msk                        (0x3UL << ETH_MACDR_RFCFCSTS_Pos) /*!< 0x00000006 */\n#define ETH_MACDR_RFCFCSTS                            ETH_MACDR_RFCFCSTS_Msk   /* MAC MII Transmit Protocol Engine Status */\n#define ETH_MACDR_RPESTS_Pos                          (0U)\n#define ETH_MACDR_RPESTS_Msk                          (0x1UL << ETH_MACDR_RPESTS_Pos) /*!< 0x00000001 */\n#define ETH_MACDR_RPESTS                              ETH_MACDR_RPESTS_Msk     /* MAC MII Receive Protocol Engine Status */\n\n/* Bit definition for Ethernet MAC HW Feature0 Register */\n#define ETH_MACHWF0R_ACTPHYSEL_Pos                    (28U)\n#define ETH_MACHWF0R_ACTPHYSEL_Msk                    (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */\n#define ETH_MACHWF0R_ACTPHYSEL                        ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */\n#define ETH_MACHWF0R_ACTPHYSEL_MII                    ((uint32_t)0x00000000)   /* MII */\n#define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos               (30U)\n#define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk               (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */\n#define ETH_MACHWF0R_ACTPHYSEL_RMII                   ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */\n#define ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos             (28U)\n#define ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk             (0x7UL << ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos) /*!< 0x70000000 */\n#define ETH_MACHWF0R_ACTPHYSEL_REVMII                 ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk /* RevMII */\n#define ETH_MACHWF0R_SAVLANINS_Pos                    (27U)\n#define ETH_MACHWF0R_SAVLANINS_Msk                    (0x1UL << ETH_MACHWF0R_SAVLANINS_Pos) /*!< 0x08000000 */\n#define ETH_MACHWF0R_SAVLANINS                        ETH_MACHWF0R_SAVLANINS_Msk /* Source Address or VLAN Insertion Enable */\n#define ETH_MACHWF0R_TSSTSSEL_Pos                     (25U)\n#define ETH_MACHWF0R_TSSTSSEL_Msk                     (0x3UL << ETH_MACHWF0R_TSSTSSEL_Pos) /*!< 0x06000000 */\n#define ETH_MACHWF0R_TSSTSSEL                         ETH_MACHWF0R_TSSTSSEL_Msk /* Timestamp System Time Source */\n#define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos            (25U)\n#define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk            (0x1UL << ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos) /*!< 0x02000000 */\n#define ETH_MACHWF0R_TSSTSSEL_INTERNAL                ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk /* Timestamp System Time Source: Internal */\n#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos            (26U)\n#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk            (0x1UL << ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos) /*!< 0x04000000 */\n#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL                ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk /* Timestamp System Time Source: External */\n#define ETH_MACHWF0R_TSSTSSEL_BOTH_Pos                (25U)\n#define ETH_MACHWF0R_TSSTSSEL_BOTH_Msk                (0x3UL << ETH_MACHWF0R_TSSTSSEL_BOTH_Pos) /*!< 0x06000000 */\n#define ETH_MACHWF0R_TSSTSSEL_BOTH                    ETH_MACHWF0R_TSSTSSEL_BOTH_Msk /* Timestamp System Time Source: Internal & External */\n#define ETH_MACHWF0R_MACADR64SEL_Pos                  (24U)\n#define ETH_MACHWF0R_MACADR64SEL_Msk                  (0x1UL << ETH_MACHWF0R_MACADR64SEL_Pos) /*!< 0x01000000 */\n#define ETH_MACHWF0R_MACADR64SEL                      ETH_MACHWF0R_MACADR64SEL_Msk /* MAC Addresses 64-127 Selected */\n#define ETH_MACHWF0R_MACADR32SEL_Pos                  (23U)\n#define ETH_MACHWF0R_MACADR32SEL_Msk                  (0x1UL << ETH_MACHWF0R_MACADR32SEL_Pos) /*!< 0x00800000 */\n#define ETH_MACHWF0R_MACADR32SEL                      ETH_MACHWF0R_MACADR32SEL_Msk /* MAC Addresses 32-63 Selected */\n#define ETH_MACHWF0R_ADDMACADRSEL_Pos                 (18U)\n#define ETH_MACHWF0R_ADDMACADRSEL_Msk                 (0x1FUL << ETH_MACHWF0R_ADDMACADRSEL_Pos) /*!< 0x007C0000 */\n#define ETH_MACHWF0R_ADDMACADRSEL                     ETH_MACHWF0R_ADDMACADRSEL_Msk /* MAC Addresses 1- 31 Selected */\n#define ETH_MACHWF0R_RXCOESEL_Pos                     (16U)\n#define ETH_MACHWF0R_RXCOESEL_Msk                     (0x1UL << ETH_MACHWF0R_RXCOESEL_Pos) /*!< 0x00010000 */\n#define ETH_MACHWF0R_RXCOESEL                         ETH_MACHWF0R_RXCOESEL_Msk /* Receive Checksum Offload Enabled */\n#define ETH_MACHWF0R_TXCOESEL_Pos                     (14U)\n#define ETH_MACHWF0R_TXCOESEL_Msk                     (0x1UL << ETH_MACHWF0R_TXCOESEL_Pos) /*!< 0x00004000 */\n#define ETH_MACHWF0R_TXCOESEL                         ETH_MACHWF0R_TXCOESEL_Msk /* Transmit Checksum Offload Enabled */\n#define ETH_MACHWF0R_EEESEL_Pos                       (13U)\n#define ETH_MACHWF0R_EEESEL_Msk                       (0x1UL << ETH_MACHWF0R_EEESEL_Pos) /*!< 0x00002000 */\n#define ETH_MACHWF0R_EEESEL                           ETH_MACHWF0R_EEESEL_Msk  /* Energy Efficient Ethernet Enabled */\n#define ETH_MACHWF0R_TSSEL_Pos                        (12U)\n#define ETH_MACHWF0R_TSSEL_Msk                        (0x1UL << ETH_MACHWF0R_TSSEL_Pos) /*!< 0x00001000 */\n#define ETH_MACHWF0R_TSSEL                            ETH_MACHWF0R_TSSEL_Msk   /* IEEE 1588-2008 Timestamp Enabled */\n#define ETH_MACHWF0R_ARPOFFSEL_Pos                    (9U)\n#define ETH_MACHWF0R_ARPOFFSEL_Msk                    (0x1UL << ETH_MACHWF0R_ARPOFFSEL_Pos) /*!< 0x00000200 */\n#define ETH_MACHWF0R_ARPOFFSEL                        ETH_MACHWF0R_ARPOFFSEL_Msk /* ARP Offload Enabled */\n#define ETH_MACHWF0R_MMCSEL_Pos                       (8U)\n#define ETH_MACHWF0R_MMCSEL_Msk                       (0x1UL << ETH_MACHWF0R_MMCSEL_Pos) /*!< 0x00000100 */\n#define ETH_MACHWF0R_MMCSEL                           ETH_MACHWF0R_MMCSEL_Msk  /* RMON Module Enable */\n#define ETH_MACHWF0R_MGKSEL_Pos                       (7U)\n#define ETH_MACHWF0R_MGKSEL_Msk                       (0x1UL << ETH_MACHWF0R_MGKSEL_Pos) /*!< 0x00000080 */\n#define ETH_MACHWF0R_MGKSEL                           ETH_MACHWF0R_MGKSEL_Msk  /* PMT Magic Packet Enable */\n#define ETH_MACHWF0R_RWKSEL_Pos                       (6U)\n#define ETH_MACHWF0R_RWKSEL_Msk                       (0x1UL << ETH_MACHWF0R_RWKSEL_Pos) /*!< 0x00000040 */\n#define ETH_MACHWF0R_RWKSEL                           ETH_MACHWF0R_RWKSEL_Msk  /* PMT Remote Wake-up Packet Enable */\n#define ETH_MACHWF0R_SMASEL_Pos                       (5U)\n#define ETH_MACHWF0R_SMASEL_Msk                       (0x1UL << ETH_MACHWF0R_SMASEL_Pos) /*!< 0x00000020 */\n#define ETH_MACHWF0R_SMASEL                           ETH_MACHWF0R_SMASEL_Msk  /* SMA (MDIO) Interface */\n#define ETH_MACHWF0R_VLHASH_Pos                       (4U)\n#define ETH_MACHWF0R_VLHASH_Msk                       (0x1UL << ETH_MACHWF0R_VLHASH_Pos) /*!< 0x00000010 */\n#define ETH_MACHWF0R_VLHASH                           ETH_MACHWF0R_VLHASH_Msk  /* VLAN Hash Filter Selected */\n#define ETH_MACHWF0R_PCSSEL_Pos                       (3U)\n#define ETH_MACHWF0R_PCSSEL_Msk                       (0x1UL << ETH_MACHWF0R_PCSSEL_Pos) /*!< 0x00000008 */\n#define ETH_MACHWF0R_PCSSEL                           ETH_MACHWF0R_PCSSEL_Msk  /* PCS Registers (TBI, SGMII, or RTBI PHY interface) */\n#define ETH_MACHWF0R_HDSEL_Pos                        (2U)\n#define ETH_MACHWF0R_HDSEL_Msk                        (0x1UL << ETH_MACHWF0R_HDSEL_Pos) /*!< 0x00000004 */\n#define ETH_MACHWF0R_HDSEL                            ETH_MACHWF0R_HDSEL_Msk   /* Half-duplex Support */\n#define ETH_MACHWF0R_GMIISEL_Pos                      (1U)\n#define ETH_MACHWF0R_GMIISEL_Msk                      (0x1UL << ETH_MACHWF0R_GMIISEL_Pos) /*!< 0x00000002 */\n#define ETH_MACHWF0R_GMIISEL                          ETH_MACHWF0R_GMIISEL_Msk /* 1000 Mbps Support */\n#define ETH_MACHWF0R_MIISEL_Pos                       (0U)\n#define ETH_MACHWF0R_MIISEL_Msk                       (0x1UL << ETH_MACHWF0R_MIISEL_Pos) /*!< 0x00000001 */\n#define ETH_MACHWF0R_MIISEL                           ETH_MACHWF0R_MIISEL_Msk  /* 10 or 100 Mbps Support */\n\n/* Bit definition for Ethernet MAC HW Feature1 Register */\n#define ETH_MACHWF1R_L3L4FNUM_Pos                     (27U)\n#define ETH_MACHWF1R_L3L4FNUM_Msk                     (0xFUL << ETH_MACHWF1R_L3L4FNUM_Pos) /*!< 0x78000000 */\n#define ETH_MACHWF1R_L3L4FNUM                         ETH_MACHWF1R_L3L4FNUM_Msk /* Total number of L3 or L4 Filters */\n#define ETH_MACHWF1R_HASHTBLSZ_Pos                    (24U)\n#define ETH_MACHWF1R_HASHTBLSZ_Msk                    (0x3UL << ETH_MACHWF1R_HASHTBLSZ_Pos) /*!< 0x03000000 */\n#define ETH_MACHWF1R_HASHTBLSZ                        ETH_MACHWF1R_HASHTBLSZ_Msk /* Hash Table Size */\n#define ETH_MACHWF1R_AVSEL_Pos                        (20U)\n#define ETH_MACHWF1R_AVSEL_Msk                        (0x1UL << ETH_MACHWF1R_AVSEL_Pos) /*!< 0x00100000 */\n#define ETH_MACHWF1R_AVSEL                            ETH_MACHWF1R_AVSEL_Msk   /* AV Feature Enabled */\n#define ETH_MACHWF1R_DBGMEMA_Pos                      (19U)\n#define ETH_MACHWF1R_DBGMEMA_Msk                      (0x1UL << ETH_MACHWF1R_DBGMEMA_Pos) /*!< 0x00080000 */\n#define ETH_MACHWF1R_DBGMEMA                          ETH_MACHWF1R_DBGMEMA_Msk /* Debug Memory Interface Enabled */\n#define ETH_MACHWF1R_TSOEN_Pos                        (18U)\n#define ETH_MACHWF1R_TSOEN_Msk                        (0x1UL << ETH_MACHWF1R_TSOEN_Pos) /*!< 0x00040000 */\n#define ETH_MACHWF1R_TSOEN                            ETH_MACHWF1R_TSOEN_Msk   /* TCP Segmentation Offload Enable */\n#define ETH_MACHWF1R_SPHEN_Pos                        (17U)\n#define ETH_MACHWF1R_SPHEN_Msk                        (0x1UL << ETH_MACHWF1R_SPHEN_Pos) /*!< 0x00020000 */\n#define ETH_MACHWF1R_SPHEN                            ETH_MACHWF1R_SPHEN_Msk   /* Split Header Feature Enable */\n#define ETH_MACHWF1R_DCBEN_Pos                        (16U)\n#define ETH_MACHWF1R_DCBEN_Msk                        (0x1UL << ETH_MACHWF1R_DCBEN_Pos) /*!< 0x00010000 */\n#define ETH_MACHWF1R_DCBEN                            ETH_MACHWF1R_DCBEN_Msk   /* DCB Feature Enable */\n#define ETH_MACHWF1R_ADDR64_Pos                       (14U)\n#define ETH_MACHWF1R_ADDR64_Msk                       (0x3UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x0000C000 */\n#define ETH_MACHWF1R_ADDR64                           ETH_MACHWF1R_ADDR64_Msk  /* Address Width */\n#define ETH_MACHWF1R_ADDR64_32                        (0x0UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00000000 */\n#define ETH_MACHWF1R_ADDR64_40                        (0x1UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00004000 */\n#define ETH_MACHWF1R_ADDR64_48                        (0x2UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00008000 */\n#define ETH_MACHWF1R_ADVTHWORD_Pos                    (13U)\n#define ETH_MACHWF1R_ADVTHWORD_Msk                    (0x1UL << ETH_MACHWF1R_ADVTHWORD_Pos) /*!< 0x00002000 */\n#define ETH_MACHWF1R_ADVTHWORD                        ETH_MACHWF1R_ADVTHWORD_Msk /* IEEE 1588 High Word Register Enable */\n#define ETH_MACHWF1R_PTOEN_Pos                        (12U)\n#define ETH_MACHWF1R_PTOEN_Msk                        (0x1UL << ETH_MACHWF1R_PTOEN_Pos) /*!< 0x00001000 */\n#define ETH_MACHWF1R_PTOEN                            ETH_MACHWF1R_PTOEN_Msk   /* PTP Offload Enable */\n#define ETH_MACHWF1R_OSTEN_Pos                        (11U)\n#define ETH_MACHWF1R_OSTEN_Msk                        (0x1UL << ETH_MACHWF1R_OSTEN_Pos) /*!< 0x00000800 */\n#define ETH_MACHWF1R_OSTEN                            ETH_MACHWF1R_OSTEN_Msk   /* One-Step Timestamping Enable */\n#define ETH_MACHWF1R_TXFIFOSIZE_Pos                   (6U)\n#define ETH_MACHWF1R_TXFIFOSIZE_Msk                   (0x1FUL << ETH_MACHWF1R_TXFIFOSIZE_Pos) /*!< 0x000007C0 */\n#define ETH_MACHWF1R_TXFIFOSIZE                       ETH_MACHWF1R_TXFIFOSIZE_Msk /* MTL Transmit FIFO Size */\n#define ETH_MACHWF1R_RXFIFOSIZE_Pos                   (0U)\n#define ETH_MACHWF1R_RXFIFOSIZE_Msk                   (0x1FUL << ETH_MACHWF1R_RXFIFOSIZE_Pos) /*!< 0x0000001F */\n#define ETH_MACHWF1R_RXFIFOSIZE                       ETH_MACHWF1R_RXFIFOSIZE_Msk /* MTL Receive FIFO Size */\n\n/* Bit definition for Ethernet MAC HW Feature2 Register */\n#define ETH_MACHWF2R_AUXSNAPNUM_Pos                   (28U)\n#define ETH_MACHWF2R_AUXSNAPNUM_Msk                   (0x7UL << ETH_MACHWF2R_AUXSNAPNUM_Pos) /*!< 0x70000000 */\n#define ETH_MACHWF2R_AUXSNAPNUM                       ETH_MACHWF2R_AUXSNAPNUM_Msk /* Number of Auxiliary Snapshot Inputs */\n#define ETH_MACHWF2R_PPSOUTNUM_Pos                    (24U)\n#define ETH_MACHWF2R_PPSOUTNUM_Msk                    (0x7UL << ETH_MACHWF2R_PPSOUTNUM_Pos) /*!< 0x07000000 */\n#define ETH_MACHWF2R_PPSOUTNUM                        ETH_MACHWF2R_PPSOUTNUM_Msk /*  Number of PPS Outputs */\n#define ETH_MACHWF2R_TXCHCNT_Pos                      (18U)\n#define ETH_MACHWF2R_TXCHCNT_Msk                      (0xFUL << ETH_MACHWF2R_TXCHCNT_Pos) /*!< 0x003C0000 */\n#define ETH_MACHWF2R_TXCHCNT                          ETH_MACHWF2R_TXCHCNT_Msk /* Number of DMA Transmit Channels */\n#define ETH_MACHWF2R_RXCHCNT_Pos                      (13U)\n#define ETH_MACHWF2R_RXCHCNT_Msk                      (0x7UL << ETH_MACHWF2R_RXCHCNT_Pos) /*!< 0x0000E000 */\n#define ETH_MACHWF2R_RXCHCNT                          ETH_MACHWF2R_RXCHCNT_Msk /* Number of DMA Receive Channels */\n#define ETH_MACHWF2R_TXQCNT_Pos                       (6U)\n#define ETH_MACHWF2R_TXQCNT_Msk                       (0xFUL << ETH_MACHWF2R_TXQCNT_Pos) /*!< 0x000003C0 */\n#define ETH_MACHWF2R_TXQCNT                           ETH_MACHWF2R_TXQCNT_Msk  /* Number of MTL Transmit Queues */\n#define ETH_MACHWF2R_RXQCNT_Pos                       (0U)\n#define ETH_MACHWF2R_RXQCNT_Msk                       (0xFUL << ETH_MACHWF2R_RXQCNT_Pos) /*!< 0x0000000F */\n#define ETH_MACHWF2R_RXQCNT                           ETH_MACHWF2R_RXQCNT_Msk  /* Number of MTL Receive Queues */\n\n/* Bit definition for Ethernet MAC MDIO Address Register */\n#define ETH_MACMDIOAR_PSE_Pos                         (27U)\n#define ETH_MACMDIOAR_PSE_Msk                         (0x1UL << ETH_MACMDIOAR_PSE_Pos) /*!< 0x08000000 */\n#define ETH_MACMDIOAR_PSE                             ETH_MACMDIOAR_PSE_Msk    /* Preamble Suppression Enable */\n#define ETH_MACMDIOAR_BTB_Pos                         (26U)\n#define ETH_MACMDIOAR_BTB_Msk                         (0x1UL << ETH_MACMDIOAR_BTB_Pos) /*!< 0x04000000 */\n#define ETH_MACMDIOAR_BTB                             ETH_MACMDIOAR_BTB_Msk    /* Back to Back transactions */\n#define ETH_MACMDIOAR_PA_Pos                          (21U)\n#define ETH_MACMDIOAR_PA_Msk                          (0x1FUL << ETH_MACMDIOAR_PA_Pos) /*!< 0x03E00000 */\n#define ETH_MACMDIOAR_PA                              ETH_MACMDIOAR_PA_Msk     /* Physical Layer Address */\n#define ETH_MACMDIOAR_RDA_Pos                         (16U)\n#define ETH_MACMDIOAR_RDA_Msk                         (0x1FUL << ETH_MACMDIOAR_RDA_Pos) /*!< 0x001F0000 */\n#define ETH_MACMDIOAR_RDA                             ETH_MACMDIOAR_RDA_Msk    /* Register/Device Address */\n#define ETH_MACMDIOAR_NTC_Pos                         (12U)\n#define ETH_MACMDIOAR_NTC_Msk                         (0x7UL << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00007000 */\n#define ETH_MACMDIOAR_NTC                             ETH_MACMDIOAR_NTC_Msk    /* Number of Trailing Clocks */\n#define ETH_MACMDIOAR_CR_Pos                          (8U)\n#define ETH_MACMDIOAR_CR_Msk                          (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */\n#define ETH_MACMDIOAR_CR                              ETH_MACMDIOAR_CR_Msk     /* CSR Clock Range */\n#define ETH_MACMDIOAR_CR_DIV42                        ((uint32_t)0x00000000)   /* CSR clock/42 */\n#define ETH_MACMDIOAR_CR_DIV62_Pos                    (8U)\n#define ETH_MACMDIOAR_CR_DIV62_Msk                    (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */\n#define ETH_MACMDIOAR_CR_DIV62                        ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */\n#define ETH_MACMDIOAR_CR_DIV16_Pos                    (9U)\n#define ETH_MACMDIOAR_CR_DIV16_Msk                    (0x1UL << ETH_MACMDIOAR_CR_DIV16_Pos) /*!< 0x00000200 */\n#define ETH_MACMDIOAR_CR_DIV16                        ETH_MACMDIOAR_CR_DIV16_Msk /* CSR clock/16 */\n#define ETH_MACMDIOAR_CR_DIV26_Pos                    (8U)\n#define ETH_MACMDIOAR_CR_DIV26_Msk                    (0x3UL << ETH_MACMDIOAR_CR_DIV26_Pos) /*!< 0x00000300 */\n#define ETH_MACMDIOAR_CR_DIV26                        ETH_MACMDIOAR_CR_DIV26_Msk /* CSR clock/26 */\n#define ETH_MACMDIOAR_CR_DIV102_Pos                   (10U)\n#define ETH_MACMDIOAR_CR_DIV102_Msk                   (0x1UL << ETH_MACMDIOAR_CR_DIV102_Pos) /*!< 0x00000400 */\n#define ETH_MACMDIOAR_CR_DIV102                       ETH_MACMDIOAR_CR_DIV102_Msk /* CSR clock/102 */\n#define ETH_MACMDIOAR_CR_DIV124_Pos                   (8U)\n#define ETH_MACMDIOAR_CR_DIV124_Msk                   (0x5UL << ETH_MACMDIOAR_CR_DIV124_Pos) /*!< 0x00000500 */\n#define ETH_MACMDIOAR_CR_DIV124                       ETH_MACMDIOAR_CR_DIV124_Msk /* CSR clock/124 */\n#define ETH_MACMDIOAR_CR_DIV4AR_Pos                   (11U)\n#define ETH_MACMDIOAR_CR_DIV4AR_Msk                   (0x1UL << ETH_MACMDIOAR_CR_DIV4AR_Pos) /*!< 0x00000800 */\n#define ETH_MACMDIOAR_CR_DIV4AR                       ETH_MACMDIOAR_CR_DIV4AR_Msk /* CSR clock/4: MDC clock above range specified in IEEE */\n#define ETH_MACMDIOAR_CR_DIV6AR_Pos                   (8U)\n#define ETH_MACMDIOAR_CR_DIV6AR_Msk                   (0x9UL << ETH_MACMDIOAR_CR_DIV6AR_Pos) /*!< 0x00000900 */\n#define ETH_MACMDIOAR_CR_DIV6AR                       ETH_MACMDIOAR_CR_DIV6AR_Msk /* CSR clock/6: MDC clock above range specified in IEEE */\n#define ETH_MACMDIOAR_CR_DIV8AR_Pos                   (9U)\n#define ETH_MACMDIOAR_CR_DIV8AR_Msk                   (0x5UL << ETH_MACMDIOAR_CR_DIV8AR_Pos) /*!< 0x00000A00 */\n#define ETH_MACMDIOAR_CR_DIV8AR                       ETH_MACMDIOAR_CR_DIV8AR_Msk /* CSR clock/8: MDC clock above range specified in IEEE */\n#define ETH_MACMDIOAR_CR_DIV10AR_Pos                  (8U)\n#define ETH_MACMDIOAR_CR_DIV10AR_Msk                  (0xBUL << ETH_MACMDIOAR_CR_DIV10AR_Pos) /*!< 0x00000B00 */\n#define ETH_MACMDIOAR_CR_DIV10AR                      ETH_MACMDIOAR_CR_DIV10AR_Msk /* CSR clock/10: MDC clock above range specified in IEEE */\n#define ETH_MACMDIOAR_CR_DIV12AR_Pos                  (10U)\n#define ETH_MACMDIOAR_CR_DIV12AR_Msk                  (0x3UL << ETH_MACMDIOAR_CR_DIV12AR_Pos) /*!< 0x00000C00 */\n#define ETH_MACMDIOAR_CR_DIV12AR                      ETH_MACMDIOAR_CR_DIV12AR_Msk /* CSR clock/12: MDC clock above range specified in IEEE */\n#define ETH_MACMDIOAR_CR_DIV14AR_Pos                  (8U)\n#define ETH_MACMDIOAR_CR_DIV14AR_Msk                  (0xDUL << ETH_MACMDIOAR_CR_DIV14AR_Pos) /*!< 0x00000D00 */\n#define ETH_MACMDIOAR_CR_DIV14AR                      ETH_MACMDIOAR_CR_DIV14AR_Msk /* CSR clock/14: MDC clock above range specified in IEEE */\n#define ETH_MACMDIOAR_CR_DIV16AR_Pos                  (9U)\n#define ETH_MACMDIOAR_CR_DIV16AR_Msk                  (0x7UL << ETH_MACMDIOAR_CR_DIV16AR_Pos) /*!< 0x00000E00 */\n#define ETH_MACMDIOAR_CR_DIV16AR                      ETH_MACMDIOAR_CR_DIV16AR_Msk /* CSR clock/16: MDC clock above range specified in IEEE */\n#define ETH_MACMDIOAR_CR_DIV18AR_Pos                  (8U)\n#define ETH_MACMDIOAR_CR_DIV18AR_Msk                  (0xFUL << ETH_MACMDIOAR_CR_DIV18AR_Pos) /*!< 0x00000F00 */\n#define ETH_MACMDIOAR_CR_DIV18AR                      ETH_MACMDIOAR_CR_DIV18AR_Msk /* CSR clock/18: MDC clock above range specified in IEEE */\n#define ETH_MACMDIOAR_SKAP_Pos                        (4U)\n#define ETH_MACMDIOAR_SKAP_Msk                        (0x1UL << ETH_MACMDIOAR_SKAP_Pos) /*!< 0x00000010 */\n#define ETH_MACMDIOAR_SKAP                            ETH_MACMDIOAR_SKAP_Msk   /* Skip Address Packet */\n#define ETH_MACMDIOAR_MOC_Pos                         (2U)\n#define ETH_MACMDIOAR_MOC_Msk                         (0x3UL << ETH_MACMDIOAR_MOC_Pos) /*!< 0x0000000C */\n#define ETH_MACMDIOAR_MOC                             ETH_MACMDIOAR_MOC_Msk    /* MII Operation Command */\n#define ETH_MACMDIOAR_MOC_WR_Pos                      (2U)\n#define ETH_MACMDIOAR_MOC_WR_Msk                      (0x1UL << ETH_MACMDIOAR_MOC_WR_Pos) /*!< 0x00000004 */\n#define ETH_MACMDIOAR_MOC_WR                          ETH_MACMDIOAR_MOC_WR_Msk /* Write */\n#define ETH_MACMDIOAR_MOC_PRDIA_Pos                   (3U)\n#define ETH_MACMDIOAR_MOC_PRDIA_Msk                   (0x1UL << ETH_MACMDIOAR_MOC_PRDIA_Pos) /*!< 0x00000008 */\n#define ETH_MACMDIOAR_MOC_PRDIA                       ETH_MACMDIOAR_MOC_PRDIA_Msk /* Post Read Increment Address for Clause 45 PHY */\n#define ETH_MACMDIOAR_MOC_RD_Pos                      (2U)\n#define ETH_MACMDIOAR_MOC_RD_Msk                      (0x3UL << ETH_MACMDIOAR_MOC_RD_Pos) /*!< 0x0000000C */\n#define ETH_MACMDIOAR_MOC_RD                          ETH_MACMDIOAR_MOC_RD_Msk /* Read */\n#define ETH_MACMDIOAR_C45E_Pos                        (1U)\n#define ETH_MACMDIOAR_C45E_Msk                        (0x1UL << ETH_MACMDIOAR_C45E_Pos) /*!< 0x00000002 */\n#define ETH_MACMDIOAR_C45E                            ETH_MACMDIOAR_C45E_Msk   /* Clause 45 PHY Enable */\n#define ETH_MACMDIOAR_MB_Pos                          (0U)\n#define ETH_MACMDIOAR_MB_Msk                          (0x1UL << ETH_MACMDIOAR_MB_Pos) /*!< 0x00000001 */\n#define ETH_MACMDIOAR_MB                              ETH_MACMDIOAR_MB_Msk     /* MII Busy */\n\n/* Bit definition for Ethernet MAC MDIO Data Register */\n#define ETH_MACMDIODR_RA_Pos                          (16U)\n#define ETH_MACMDIODR_RA_Msk                          (0xFFFFUL << ETH_MACMDIODR_RA_Pos) /*!< 0xFFFF0000 */\n#define ETH_MACMDIODR_RA                              ETH_MACMDIODR_RA_Msk     /* Register Address */\n#define ETH_MACMDIODR_MD_Pos                          (0U)\n#define ETH_MACMDIODR_MD_Msk                          (0xFFFFUL << ETH_MACMDIODR_MD_Pos) /*!< 0x0000FFFF */\n#define ETH_MACMDIODR_MD                              ETH_MACMDIODR_MD_Msk     /* MII Data */\n\n/* Bit definition for Ethernet ARP Address Register */\n#define ETH_MACARPAR_ARPPA_Pos                         (0U)\n#define ETH_MACARPAR_ARPPA_Msk                         (0xFFFFFFFFUL << ETH_MACARPAR_ARPPA_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MACARPAR_ARPPA                             ETH_MACARPAR_ARPPA_Msk     /* ARP Protocol Address */\n\n/* Bit definition for Ethernet MAC Address 0 High Register */\n#define ETH_MACA0HR_AE_Pos                            (31U)\n#define ETH_MACA0HR_AE_Msk                            (0x1UL << ETH_MACA0HR_AE_Pos) /*!< 0x80000000 */\n#define ETH_MACA0HR_AE                                ETH_MACA0HR_AE_Msk /* Address Enable*/\n#define ETH_MACA0HR_ADDRHI_Pos                        (0U)\n#define ETH_MACA0HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x0000FFFF */\n#define ETH_MACA0HR_ADDRHI                            ETH_MACA0HR_ADDRHI_Msk   /* MAC Address 0*/\n\n/* Bit definition for Ethernet MAC Address 0 Low Register */\n#define ETH_MACA0LR_ADDRLO_Pos                        (0U)\n#define ETH_MACA0LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA0LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MACA0LR_ADDRLO                            ETH_MACA0LR_ADDRLO_Msk   /* MAC Address 0*/\n\n/* Bit definition for Ethernet MAC Address 1 High Register */\n#define ETH_MACA1HR_AE_Pos                            (31U)\n#define ETH_MACA1HR_AE_Msk                            (0x1UL << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */\n#define ETH_MACA1HR_AE                                ETH_MACA1HR_AE_Msk /* Address Enable*/\n#define ETH_MACA1HR_SA_Pos                            (30U)\n#define ETH_MACA1HR_SA_Msk                            (0x1UL << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */\n#define ETH_MACA1HR_SA                                ETH_MACA1HR_SA_Msk /* Source Address */\n#define ETH_MACA1HR_MBC_Pos                           (24U)\n#define ETH_MACA1HR_MBC_Msk                           (0x3FUL << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */\n#define ETH_MACA1HR_MBC                               ETH_MACA1HR_MBC_Msk /* Mask Byte Control */\n#define ETH_MACA1HR_ADDRHI_Pos                        (0U)\n#define ETH_MACA1HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA1HR_ADDRHI_Pos) /*!< 0x0000FFFF */\n#define ETH_MACA1HR_ADDRHI                            ETH_MACA1HR_ADDRHI_Msk   /* MAC Address 1*/\n\n/* Bit definition for Ethernet MAC Address 1 Low Register */\n#define ETH_MACA1LR_ADDRLO_Pos                        (0U)\n#define ETH_MACA1LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA1LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MACA1LR_ADDRLO                            ETH_MACA1LR_ADDRLO_Msk   /* MAC Address 1*/\n\n/* Bit definition for Ethernet MAC Address 2 High Register */\n#define ETH_MACA2HR_AE_Pos                            (31U)\n#define ETH_MACA2HR_AE_Msk                            (0x1UL << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */\n#define ETH_MACA2HR_AE                                ETH_MACA2HR_AE_Msk /* Address Enable*/\n#define ETH_MACA2HR_SA_Pos                            (30U)\n#define ETH_MACA2HR_SA_Msk                            (0x1UL << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */\n#define ETH_MACA2HR_SA                                ETH_MACA2HR_SA_Msk /* Source Address */\n#define ETH_MACA2HR_MBC_Pos                           (24U)\n#define ETH_MACA2HR_MBC_Msk                           (0x3FUL << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */\n#define ETH_MACA2HR_MBC                               ETH_MACA2HR_MBC_Msk /* Mask Byte Control */\n#define ETH_MACA2HR_ADDRHI_Pos                        (0U)\n#define ETH_MACA2HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA2HR_ADDRHI_Pos) /*!< 0x0000FFFF */\n#define ETH_MACA2HR_ADDRHI                            ETH_MACA2HR_ADDRHI_Msk   /* MAC Address 1*/\n\n/* Bit definition for Ethernet MAC Address 2 Low Register */\n#define ETH_MACA2LR_ADDRLO_Pos                        (0U)\n#define ETH_MACA2LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA2LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MACA2LR_ADDRLO                            ETH_MACA2LR_ADDRLO_Msk   /* MAC Address 2*/\n\n/* Bit definition for Ethernet MAC Address 3 High Register */\n#define ETH_MACA3HR_AE_Pos                            (31U)\n#define ETH_MACA3HR_AE_Msk                            (0x1UL << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */\n#define ETH_MACA3HR_AE                                ETH_MACA3HR_AE_Msk /* Address Enable*/\n#define ETH_MACA3HR_SA_Pos                            (30U)\n#define ETH_MACA3HR_SA_Msk                            (0x1UL << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */\n#define ETH_MACA3HR_SA                                ETH_MACA3HR_SA_Msk /* Source Address */\n#define ETH_MACA3HR_MBC_Pos                           (24U)\n#define ETH_MACA3HR_MBC_Msk                           (0x3FUL << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */\n#define ETH_MACA3HR_MBC                               ETH_MACA3HR_MBC_Msk /* Mask Byte Control */\n#define ETH_MACA3HR_ADDRHI_Pos                        (0U)\n#define ETH_MACA3HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA3HR_ADDRHI_Pos) /*!< 0x0000FFFF */\n#define ETH_MACA3HR_ADDRHI                            ETH_MACA3HR_ADDRHI_Msk   /* MAC Address 1*/\n\n/* Bit definition for Ethernet MAC Address 3 Low Register */\n#define ETH_MACA3LR_ADDRLO_Pos                        (0U)\n#define ETH_MACA3LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA3LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MACA3LR_ADDRLO                            ETH_MACA3LR_ADDRLO_Msk   /* MAC Address 3*/\n\n/* Bit definition for Ethernet MAC Address High Register */\n#define ETH_MACAHR_AE_Pos                             (31U)\n#define ETH_MACAHR_AE_Msk                             (0x1UL << ETH_MACAHR_AE_Pos) /*!< 0x80000000 */\n#define ETH_MACAHR_AE                                 ETH_MACAHR_AE_Msk        /* Address enable */\n#define ETH_MACAHR_SA_Pos                             (30U)\n#define ETH_MACAHR_SA_Msk                             (0x1UL << ETH_MACAHR_SA_Pos) /*!< 0x40000000 */\n#define ETH_MACAHR_SA                                 ETH_MACAHR_SA_Msk        /* Source address */\n#define ETH_MACAHR_MBC_Pos                            (24U)\n#define ETH_MACAHR_MBC_Msk                            (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */\n#define ETH_MACAHR_MBC                                ETH_MACAHR_MBC_Msk       /* Mask byte control: bits to mask for comparison of the MAC Address bytes */\n#define ETH_MACAHR_MBC_HBITS15_8                      ((uint32_t)0x20000000)   /* Mask MAC Address high reg bits [15:8] */\n#define ETH_MACAHR_MBC_HBITS7_0                       ((uint32_t)0x10000000)   /* Mask MAC Address high reg bits [7:0] */\n#define ETH_MACAHR_MBC_LBITS31_24                     ((uint32_t)0x08000000)   /* Mask MAC Address low reg bits [31:24] */\n#define ETH_MACAHR_MBC_LBITS23_16                     ((uint32_t)0x04000000)   /* Mask MAC Address low reg bits [23:16] */\n#define ETH_MACAHR_MBC_LBITS15_8                      ((uint32_t)0x02000000)   /* Mask MAC Address low reg bits [15:8] */\n#define ETH_MACAHR_MBC_LBITS7_0                       ((uint32_t)0x01000000)   /* Mask MAC Address low reg bits [7:0] */\n#define ETH_MACAHR_MACAH_Pos                          (0U)\n#define ETH_MACAHR_MACAH_Msk                          (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */\n#define ETH_MACAHR_MACAH                              ETH_MACAHR_MACAH_Msk     /* MAC address high */\n\n/* Bit definition for Ethernet MAC Address Low Register */\n#define ETH_MACALR_MACAL_Pos                          (0U)\n#define ETH_MACALR_MACAL_Msk                          (0xFFFFFFFFUL << ETH_MACALR_MACAL_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MACALR_MACAL                              ETH_MACALR_MACAL_Msk     /* MAC address low */\n\n/* Bit definition for Ethernet MMC Control Register */\n#define ETH_MMCCR_UCDBC_Pos                           (8U)\n#define ETH_MMCCR_UCDBC_Msk                           (0x1UL << ETH_MMCCR_UCDBC_Pos) /*!< 0x00000100 */\n#define ETH_MMCCR_UCDBC                               ETH_MMCCR_UCDBC_Msk  /* Update MMC Counters for Dropped Broadcast Packets */\n#define ETH_MMCCR_CNTPRSTLVL_Pos                      (5U)\n#define ETH_MMCCR_CNTPRSTLVL_Msk                      (0x1UL << ETH_MMCCR_CNTPRSTLVL_Pos) /*!< 0x00000020 */\n#define ETH_MMCCR_CNTPRSTLVL                          ETH_MMCCR_CNTPRSTLVL_Msk  /* Full-Half Preset */\n#define ETH_MMCCR_CNTPRST_Pos                         (4U)\n#define ETH_MMCCR_CNTPRST_Msk                         (0x1UL << ETH_MMCCR_CNTPRST_Pos) /*!< 0x00000010 */\n#define ETH_MMCCR_CNTPRST                             ETH_MMCCR_CNTPRST_Msk  /* Counters Reset */\n#define ETH_MMCCR_CNTFREEZ_Pos                        (3U)\n#define ETH_MMCCR_CNTFREEZ_Msk                        (0x1UL << ETH_MMCCR_CNTFREEZ_Pos) /*!< 0x00000008 */\n#define ETH_MMCCR_CNTFREEZ                            ETH_MMCCR_CNTFREEZ_Msk  /* MMC Counter Freeze */\n#define ETH_MMCCR_RSTONRD_Pos                         (2U)\n#define ETH_MMCCR_RSTONRD_Msk                         (0x1UL << ETH_MMCCR_RSTONRD_Pos) /*!< 0x00000004 */\n#define ETH_MMCCR_RSTONRD                             ETH_MMCCR_RSTONRD_Msk  /* Reset On Read */\n#define ETH_MMCCR_CNTSTOPRO_Pos                       (1U)\n#define ETH_MMCCR_CNTSTOPRO_Msk                       (0x1UL << ETH_MMCCR_CNTSTOPRO_Pos) /*!< 0x00000002 */\n#define ETH_MMCCR_CNTSTOPRO                           ETH_MMCCR_CNTSTOPRO_Msk  /* Counter Stop Rollover */\n#define ETH_MMCCR_CNTRST_Pos                          (0U)\n#define ETH_MMCCR_CNTRST_Msk                          (0x1UL << ETH_MMCCR_CNTRST_Pos) /*!< 0x00000001 */\n#define ETH_MMCCR_CNTRST                              ETH_MMCCR_CNTRST_Msk  /* Counters Reset */\n\n/* Bit definition for Ethernet MMC Rx Interrupt Register */\n#define ETH_MMCRIR_RXLPITRCIS_Pos                     (27U)\n#define ETH_MMCRIR_RXLPITRCIS_Msk                     (0x1UL << ETH_MMCRIR_RXLPITRCIS_Pos) /*!< 0x08000000 */\n#define ETH_MMCRIR_RXLPITRCIS                         ETH_MMCRIR_RXLPITRCIS_Msk  /* MMC Receive LPI transition counter interrupt status */\n#define ETH_MMCRIR_RXLPIUSCIS_Pos                     (26U)\n#define ETH_MMCRIR_RXLPIUSCIS_Msk                     (0x1UL << ETH_MMCRIR_RXLPIUSCIS_Pos) /*!< 0x04000000 */\n#define ETH_MMCRIR_RXLPIUSCIS                         ETH_MMCRIR_RXLPIUSCIS_Msk  /* MMC Receive LPI microsecond counter interrupt status */\n#define ETH_MMCRIR_RXUCGPIS_Pos                       (17U)\n#define ETH_MMCRIR_RXUCGPIS_Msk                       (0x1UL << ETH_MMCRIR_RXUCGPIS_Pos) /*!< 0x00020000 */\n#define ETH_MMCRIR_RXUCGPIS                           ETH_MMCRIR_RXUCGPIS_Msk  /* MMC Receive Unicast Good Packet Counter Interrupt Status */\n#define ETH_MMCRIR_RXALGNERPIS_Pos                    (6U)\n#define ETH_MMCRIR_RXALGNERPIS_Msk                    (0x1UL << ETH_MMCRIR_RXALGNERPIS_Pos) /*!< 0x00000040 */\n#define ETH_MMCRIR_RXALGNERPIS                        ETH_MMCRIR_RXALGNERPIS_Msk  /* MMC Receive Alignment Error Packet Counter Interrupt Status */\n#define ETH_MMCRIR_RXCRCERPIS_Pos                     (5U)\n#define ETH_MMCRIR_RXCRCERPIS_Msk                     (0x1UL << ETH_MMCRIR_RXCRCERPIS_Pos) /*!< 0x00000020 */\n#define ETH_MMCRIR_RXCRCERPIS                         ETH_MMCRIR_RXCRCERPIS_Msk  /* MMC Receive CRC Error Packet Counter Interrupt Status */\n\n/* Bit definition for Ethernet MMC Tx Interrupt Register */\n#define ETH_MMCTIR_TXLPITRCIS_Pos                     (27U)\n#define ETH_MMCTIR_TXLPITRCIS_Msk                     (0x1UL << ETH_MMCTIR_TXLPITRCIS_Pos) /*!< 0x08000000 */\n#define ETH_MMCTIR_TXLPITRCIS                         ETH_MMCTIR_TXLPITRCIS_Msk  /* MMC Transmit LPI transition counter interrupt status */\n#define ETH_MMCTIR_TXLPIUSCIS_Pos                     (26U)\n#define ETH_MMCTIR_TXLPIUSCIS_Msk                     (0x1UL << ETH_MMCTIR_TXLPIUSCIS_Pos) /*!< 0x04000000 */\n#define ETH_MMCTIR_TXLPIUSCIS                         ETH_MMCTIR_TXLPIUSCIS_Msk  /* MMC Transmit LPI microsecond counter interrupt status */\n#define ETH_MMCTIR_TXGPKTIS_Pos                       (21U)\n#define ETH_MMCTIR_TXGPKTIS_Msk                       (0x1UL << ETH_MMCTIR_TXGPKTIS_Pos) /*!< 0x00200000 */\n#define ETH_MMCTIR_TXGPKTIS                           ETH_MMCTIR_TXGPKTIS_Msk  /* MMC Transmit Good Packet Counter Interrupt Status */\n#define ETH_MMCTIR_TXMCOLGPIS_Pos                     (15U)\n#define ETH_MMCTIR_TXMCOLGPIS_Msk                     (0x1UL << ETH_MMCTIR_TXMCOLGPIS_Pos) /*!< 0x00008000 */\n#define ETH_MMCTIR_TXMCOLGPIS                         ETH_MMCTIR_TXMCOLGPIS_Msk  /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Status */\n#define ETH_MMCTIR_TXSCOLGPIS_Pos                     (14U)\n#define ETH_MMCTIR_TXSCOLGPIS_Msk                     (0x1UL << ETH_MMCTIR_TXSCOLGPIS_Pos) /*!< 0x00004000 */\n#define ETH_MMCTIR_TXSCOLGPIS                         ETH_MMCTIR_TXSCOLGPIS_Msk  /* MMC Transmit Single Collision Good Packet Counter Interrupt Status */\n\n/* Bit definition for Ethernet MMC Rx interrupt Mask register */\n#define ETH_MMCRIMR_RXLPITRCIM_Pos                    (27U)\n#define ETH_MMCRIMR_RXLPITRCIM_Msk                    (0x1UL << ETH_MMCRIMR_RXLPITRCIM_Pos) /*!< 0x08000000 */\n#define ETH_MMCRIMR_RXLPITRCIM                        ETH_MMCRIMR_RXLPITRCIM_Msk  /* MMC Receive LPI transition counter interrupt Mask */\n#define ETH_MMCRIMR_RXLPIUSCIM_Pos                    (26U)\n#define ETH_MMCRIMR_RXLPIUSCIM_Msk                    (0x1UL << ETH_MMCRIMR_RXLPIUSCIM_Pos) /*!< 0x04000000 */\n#define ETH_MMCRIMR_RXLPIUSCIM                        ETH_MMCRIMR_RXLPIUSCIM_Msk  /* MMC Receive LPI microsecond counter interrupt Mask */\n#define ETH_MMCRIMR_RXUCGPIM_Pos                      (17U)\n#define ETH_MMCRIMR_RXUCGPIM_Msk                      (0x1UL << ETH_MMCRIMR_RXUCGPIM_Pos) /*!< 0x00020000 */\n#define ETH_MMCRIMR_RXUCGPIM                          ETH_MMCRIMR_RXUCGPIM_Msk  /* MMC Receive Unicast Good Packet Counter Interrupt Mask */\n#define ETH_MMCRIMR_RXALGNERPIM_Pos                   (6U)\n#define ETH_MMCRIMR_RXALGNERPIM_Msk                   (0x1UL << ETH_MMCRIMR_RXALGNERPIM_Pos) /*!< 0x00000040 */\n#define ETH_MMCRIMR_RXALGNERPIM                       ETH_MMCRIMR_RXALGNERPIM_Msk  /* MMC Receive Alignment Error Packet Counter Interrupt Mask */\n#define ETH_MMCRIMR_RXCRCERPIM_Pos                    (5U)\n#define ETH_MMCRIMR_RXCRCERPIM_Msk                    (0x1UL << ETH_MMCRIMR_RXCRCERPIM_Pos) /*!< 0x00000020 */\n#define ETH_MMCRIMR_RXCRCERPIM                        ETH_MMCRIMR_RXCRCERPIM_Msk  /* MMC Receive CRC Error Packet Counter Interrupt Mask */\n\n/* Bit definition for Ethernet MMC Tx Interrupt Mask Register */\n#define ETH_MMCTIMR_TXLPITRCIM_Pos                    (27U)\n#define ETH_MMCTIMR_TXLPITRCIM_Msk                    (0x1UL << ETH_MMCTIMR_TXLPITRCIM_Pos) /*!< 0x08000000 */\n#define ETH_MMCTIMR_TXLPITRCIM                        ETH_MMCTIMR_TXLPITRCIM_Msk  /* MMC Transmit LPI transition counter interrupt Mask*/\n#define ETH_MMCTIMR_TXLPIUSCIM_Pos                    (26U)\n#define ETH_MMCTIMR_TXLPIUSCIM_Msk                    (0x1UL << ETH_MMCTIMR_TXLPIUSCIM_Pos) /*!< 0x04000000 */\n#define ETH_MMCTIMR_TXLPIUSCIM                        ETH_MMCTIMR_TXLPIUSCIM_Msk  /* MMC Transmit LPI microsecond counter interrupt Mask*/\n#define ETH_MMCTIMR_TXGPKTIM_Pos                      (21U)\n#define ETH_MMCTIMR_TXGPKTIM_Msk                      (0x1UL << ETH_MMCTIMR_TXGPKTIM_Pos) /*!< 0x00200000 */\n#define ETH_MMCTIMR_TXGPKTIM                          ETH_MMCTIMR_TXGPKTIM_Msk  /* MMC Transmit Good Packet Counter Interrupt Mask*/\n#define ETH_MMCTIMR_TXMCOLGPIM_Pos                    (15U)\n#define ETH_MMCTIMR_TXMCOLGPIM_Msk                    (0x1UL << ETH_MMCTIMR_TXMCOLGPIM_Pos) /*!< 0x00008000 */\n#define ETH_MMCTIMR_TXMCOLGPIM                        ETH_MMCTIMR_TXMCOLGPIM_Msk  /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask */\n#define ETH_MMCTIMR_TXSCOLGPIM_Pos                    (14U)\n#define ETH_MMCTIMR_TXSCOLGPIM_Msk                    (0x1UL << ETH_MMCTIMR_TXSCOLGPIM_Pos) /*!< 0x00004000 */\n#define ETH_MMCTIMR_TXSCOLGPIM                        ETH_MMCTIMR_TXSCOLGPIM_Msk  /* MMC Transmit Single Collision Good Packet Counter Interrupt Mask */\n\n/* Bit definition for Ethernet MMC Tx Single Collision Good Packets Register */\n#define ETH_MMCTSCGPR_TXSNGLCOLG_Pos                  (0U)\n#define ETH_MMCTSCGPR_TXSNGLCOLG_msk                  (0xFFFFFFFFUL <<  ETH_MMCTSCGPR_TXSNGLCOLG_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MMCTSCGPR_TXSNGLCOLG                      ETH_MMCTSCGPR_TXSNGLCOLG_msk /* Tx Single Collision Good Packets */\n\n/* Bit definition for Ethernet MMC Tx Multiple Collision Good Packets Register */\n#define ETH_MMCTMCGPR_TXMULTCOLG_Pos                  (0U)\n#define ETH_MMCTMCGPR_TXMULTCOLG_msk                  (0xFFFFFFFFUL <<  ETH_MMCTMCGPR_TXMULTCOLG_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MMCTMCGPR_TXMULTCOLG                      ETH_MMCTMCGPR_TXMULTCOLG_msk /* Tx Multiple Collision Good Packets */\n\n/* Bit definition for Ethernet MMC Tx Packet Count Good Register */\n#define ETH_MMCTPCGR_TXPKTG_Pos                       (0U)\n#define ETH_MMCTPCGR_TXPKTG_msk                       (0xFFFFFFFFUL <<  ETH_MMCTPCGR_TXPKTG_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MMCTPCGR_TXPKTG                           ETH_MMCTPCGR_TXPKTG_msk /* Tx Packet Count Good */\n\n/* Bit definition for Ethernet MMC Rx CRC Error Packets Register */\n#define ETH_MMCRCRCEPR_RXCRCERR_Pos                   (0U)\n#define ETH_MMCRCRCEPR_RXCRCERR_msk                   (0xFFFFFFFFUL <<  ETH_MMCRCRCEPR_RXCRCERR_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MMCRCRCEPR_RXCRCERR                       ETH_MMCRCRCEPR_RXCRCERR_msk /* Rx CRC Error Packets */\n\n/* Bit definition for Ethernet MMC Rx alignment error packets register */\n#define ETH_MMCRAEPR_RXALGNERR_Pos                    (0U)\n#define ETH_MMCRAEPR_RXALGNERR_msk                    (0xFFFFFFFFUL <<  ETH_MMCRAEPR_RXALGNERR_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MMCRAEPR_RXALGNERR                        ETH_MMCRAEPR_RXALGNERR_msk /* Rx Alignment Error Packets */\n\n/* Bit definition for Ethernet MMC Rx Unicast Packets Good Register */\n#define ETH_MMCRUPGR_RXUCASTG_Pos                     (0U)\n#define ETH_MMCRUPGR_RXUCASTG_msk                     (0xFFFFFFFFUL <<  ETH_MMCRUPGR_RXUCASTG_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MMCRUPGR_RXUCASTG                         ETH_MMCRUPGR_RXUCASTG_msk /* Rx Unicast Packets Good */\n\n/* Bit definition for Ethernet MMC Tx LPI Microsecond Timer Register */\n#define ETH_MMCTLPIMSTR_TXLPIUSC_Pos                  (0U)\n#define ETH_MMCTLPIMSTR_TXLPIUSC_msk                  (0xFFFFFFFFUL <<  ETH_MMCTLPIMSTR_TXLPIUSC_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MMCTLPIMSTR_TXLPIUSC                      ETH_MMCTLPIMSTR_TXLPIUSC_msk /* Tx LPI Microseconds Counter */\n\n/* Bit definition for Ethernet MMC Tx LPI Transition Counter Register */\n#define ETH_MMCTLPITCR_TXLPITRC_Pos                   (0U)\n#define ETH_MMCTLPITCR_TXLPITRC_msk                   (0xFFFFFFFFUL <<  ETH_MMCTLPITCR_TXLPITRC_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MMCTLPITCR_TXLPITRC                       ETH_MMCTLPITCR_TXLPITRC_msk /* Tx LPI Transition counter */\n\n/* Bit definition for Ethernet MMC Rx LPI Microsecond Counter Register */\n#define ETH_MMCRLPIMSTR_RXLPIUSC_Pos                  (0U)\n#define ETH_MMCRLPIMSTR_RXLPIUSC_msk                  (0xFFFFFFFFUL <<  ETH_MMCRLPIMSTR_RXLPIUSC_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MMCRLPIMSTR_RXLPIUSC                      ETH_MMCRLPIMSTR_RXLPIUSC_msk /* Rx LPI Microseconds Counter */\n\n/* Bit definition for Ethernet MMC Rx LPI Transition Counter Register */\n#define ETH_MMCRLPITCR_RXLPITRC_Pos                   (0U)\n#define ETH_MMCRLPITCR_RXLPITRC_msk                   (0xFFFFFFFFUL <<  ETH_MMCRLPITCR_RXLPITRC_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MMCRLPITCR_RXLPITRC                       ETH_MMCRLPITCR_RXLPITRC_msk /* Rx LPI Transition counter */\n\n/* Bit definition for Ethernet MAC L3 L4 Control Register */\n#define ETH_MACL3L4CR_L4DPIM_Pos                      (21U)\n#define ETH_MACL3L4CR_L4DPIM_Msk                      (0x1UL << ETH_MACL3L4CR_L4DPIM_Pos) /*!< 0x00200000 */\n#define ETH_MACL3L4CR_L4DPIM                          ETH_MACL3L4CR_L4DPIM_Msk /* Layer 4 Destination Port Inverse Match Enable */\n#define ETH_MACL3L4CR_L4DPM_Pos                       (20U)\n#define ETH_MACL3L4CR_L4DPM_Msk                       (0x1UL << ETH_MACL3L4CR_L4DPM_Pos) /*!< 0x00100000 */\n#define ETH_MACL3L4CR_L4DPM                           ETH_MACL3L4CR_L4DPM_Msk  /* Layer 4 Destination Port Match Enable */\n#define ETH_MACL3L4CR_L4SPIM_Pos                      (19U)\n#define ETH_MACL3L4CR_L4SPIM_Msk                      (0x1UL << ETH_MACL3L4CR_L4SPIM_Pos) /*!< 0x00080000 */\n#define ETH_MACL3L4CR_L4SPIM                          ETH_MACL3L4CR_L4SPIM_Msk /* Layer 4 Source Port Inverse Match Enable */\n#define ETH_MACL3L4CR_L4SPM_Pos                       (18U)\n#define ETH_MACL3L4CR_L4SPM_Msk                       (0x1UL << ETH_MACL3L4CR_L4SPM_Pos) /*!< 0x00040000 */\n#define ETH_MACL3L4CR_L4SPM                           ETH_MACL3L4CR_L4SPM_Msk  /* Layer 4 Source Port Match Enable */\n#define ETH_MACL3L4CR_L4PEN_Pos                       (16U)\n#define ETH_MACL3L4CR_L4PEN_Msk                       (0x1UL << ETH_MACL3L4CR_L4PEN_Pos) /*!< 0x00010000 */\n#define ETH_MACL3L4CR_L4PEN                           ETH_MACL3L4CR_L4PEN_Msk  /* Layer 4 Protocol Enable */\n#define ETH_MACL3L4CR_L3HDBM_Pos                      (11U)\n#define ETH_MACL3L4CR_L3HDBM_Msk                      (0x1FUL << ETH_MACL3L4CR_L3HDBM_Pos) /*!< 0x0000F800 */\n#define ETH_MACL3L4CR_L3HDBM                          ETH_MACL3L4CR_L3HDBM_Msk /* Layer 3 IP DA Higher Bits Match */\n#define ETH_MACL3L4CR_L3HSBM_Pos                      (6U)\n#define ETH_MACL3L4CR_L3HSBM_Msk                      (0x1FUL << ETH_MACL3L4CR_L3HSBM_Pos) /*!< 0x000007C0 */\n#define ETH_MACL3L4CR_L3HSBM                          ETH_MACL3L4CR_L3HSBM_Msk /* Layer 3 IP SA Higher Bits Match */\n#define ETH_MACL3L4CR_L3DAIM_Pos                      (5U)\n#define ETH_MACL3L4CR_L3DAIM_Msk                      (0x1UL << ETH_MACL3L4CR_L3DAIM_Pos) /*!< 0x00000020 */\n#define ETH_MACL3L4CR_L3DAIM                          ETH_MACL3L4CR_L3DAIM_Msk /* Layer 3 IP DA Inverse Match Enable */\n#define ETH_MACL3L4CR_L3DAM_Pos                       (4U)\n#define ETH_MACL3L4CR_L3DAM_Msk                       (0x1UL << ETH_MACL3L4CR_L3DAM_Pos) /*!< 0x00000010 */\n#define ETH_MACL3L4CR_L3DAM                           ETH_MACL3L4CR_L3DAM_Msk  /* Layer 3 IP DA Match Enable */\n#define ETH_MACL3L4CR_L3SAIM_Pos                      (3U)\n#define ETH_MACL3L4CR_L3SAIM_Msk                      (0x1UL << ETH_MACL3L4CR_L3SAIM_Pos) /*!< 0x00000008 */\n#define ETH_MACL3L4CR_L3SAIM                          ETH_MACL3L4CR_L3SAIM_Msk /* Layer 3 IP SA Inverse Match Enable */\n#define ETH_MACL3L4CR_L3SAM_Pos                       (2U)\n#define ETH_MACL3L4CR_L3SAM_Msk                       (0x1UL << ETH_MACL3L4CR_L3SAM_Pos) /*!< 0x00000004 */\n#define ETH_MACL3L4CR_L3SAM                           ETH_MACL3L4CR_L3SAM_Msk  /* Layer 3 IP SA Match Enable*/\n#define ETH_MACL3L4CR_L3PEN_Pos                       (0U)\n#define ETH_MACL3L4CR_L3PEN_Msk                       (0x1UL << ETH_MACL3L4CR_L3PEN_Pos) /*!< 0x00000001 */\n#define ETH_MACL3L4CR_L3PEN                           ETH_MACL3L4CR_L3PEN_Msk  /* Layer 3 Protocol Enable */\n\n/* Bit definition for Ethernet MAC L4 Address Register */\n#define ETH_MACL4AR_L4DP_Pos                          (16U)\n#define ETH_MACL4AR_L4DP_Msk                          (0xFFFFUL << ETH_MACL4AR_L4DP_Pos) /*!< 0xFFFF0000 */\n#define ETH_MACL4AR_L4DP                              ETH_MACL4AR_L4DP_Msk     /* Layer 4 Destination Port Number Field */\n#define ETH_MACL4AR_L4SP_Pos                          (0U)\n#define ETH_MACL4AR_L4SP_Msk                          (0xFFFFUL << ETH_MACL4AR_L4SP_Pos) /*!< 0x0000FFFF */\n#define ETH_MACL4AR_L4SP                              ETH_MACL4AR_L4SP_Msk     /* Layer 4 Source Port Number Field */\n\n/* Bit definition for Ethernet MAC L3 Address0 Register */\n#define ETH_MACL3A0R_L3A0_Pos                         (0U)\n#define ETH_MACL3A0R_L3A0_Msk                         (0xFFFFFFFFUL << ETH_MACL3A0R_L3A0_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MACL3A0R_L3A0                             ETH_MACL3A0R_L3A0_Msk    /* Layer 3 Address 0 Field */\n\n/* Bit definition for Ethernet MAC L4 Address1 Register */\n#define ETH_MACL3A1R_L3A1_Pos                         (0U)\n#define ETH_MACL3A1R_L3A1_Msk                         (0xFFFFFFFFUL << ETH_MACL3A1R_L3A1_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MACL3A1R_L3A1                             ETH_MACL3A1R_L3A1_Msk    /* Layer 3 Address 1 Field */\n\n/* Bit definition for Ethernet MAC L4 Address2 Register */\n#define ETH_MACL3A2R_L3A2_Pos                         (0U)\n#define ETH_MACL3A2R_L3A2_Msk                         (0xFFFFFFFFUL << ETH_MACL3A2R_L3A2_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MACL3A2R_L3A2                             ETH_MACL3A2R_L3A2_Msk    /* Layer 3 Address 2 Field */\n\n/* Bit definition for Ethernet MAC L4 Address3 Register */\n#define ETH_MACL3A3R_L3A3_Pos                         (0U)\n#define ETH_MACL3A3R_L3A3_Msk                         (0xFFFFFFFFUL << ETH_MACL3A3R_L3A3_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MACL3A3R_L3A3                             ETH_MACL3A3R_L3A3_Msk    /* Layer 3 Address 3 Field */\n\n/* Bit definition for Ethernet MAC Timestamp Control Register */\n#define ETH_MACTSCR_TXTSSTSM_Pos                      (24U)\n#define ETH_MACTSCR_TXTSSTSM_Msk                      (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos) /*!< 0x01000000 */\n#define ETH_MACTSCR_TXTSSTSM                          ETH_MACTSCR_TXTSSTSM_Msk  /* Transmit Timestamp Status Mode */\n#define ETH_MACTSCR_CSC_Pos                           (19U)\n#define ETH_MACTSCR_CSC_Msk                           (0x1UL << ETH_MACTSCR_CSC_Pos) /*!< 0x00080000 */\n#define ETH_MACTSCR_CSC                               ETH_MACTSCR_CSC_Msk  /* Enable checksum correction during OST for PTP over UDP/IPv4 packets */\n#define ETH_MACTSCR_TSENMACADDR_Pos                   (18U)\n#define ETH_MACTSCR_TSENMACADDR_Msk                   (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos) /*!< 0x00040000 */\n#define ETH_MACTSCR_TSENMACADDR                       ETH_MACTSCR_TSENMACADDR_Msk  /* Enable MAC Address for PTP Packet Filtering */\n#define ETH_MACTSCR_SNAPTYPSEL_Pos                    (16U)\n#define ETH_MACTSCR_SNAPTYPSEL_Msk                    (0x3UL << ETH_MACTSCR_SNAPTYPSEL_Pos) /*!< 0x00030000 */\n#define ETH_MACTSCR_SNAPTYPSEL                        ETH_MACTSCR_SNAPTYPSEL_Msk  /* Select PTP packets for Taking Snapshots */\n#define ETH_MACTSCR_TSMSTRENA_Pos                     (15U)\n#define ETH_MACTSCR_TSMSTRENA_Msk                     (0x1UL << ETH_MACTSCR_TSMSTRENA_Pos) /*!< 0x00008000 */\n#define ETH_MACTSCR_TSMSTRENA                         ETH_MACTSCR_TSMSTRENA_Msk  /* Enable Snapshot for Messages Relevant to Master */\n#define ETH_MACTSCR_TSEVNTENA_Pos                     (14U)\n#define ETH_MACTSCR_TSEVNTENA_Msk                     (0x1UL << ETH_MACTSCR_TSEVNTENA_Pos) /*!< 0x00004000 */\n#define ETH_MACTSCR_TSEVNTENA                         ETH_MACTSCR_TSEVNTENA_Msk  /* Enable Timestamp Snapshot for Event Messages */\n#define ETH_MACTSCR_TSIPV4ENA_Pos                     (13U)\n#define ETH_MACTSCR_TSIPV4ENA_Msk                     (0x1UL << ETH_MACTSCR_TSIPV4ENA_Pos) /*!< 0x00002000 */\n#define ETH_MACTSCR_TSIPV4ENA                         ETH_MACTSCR_TSIPV4ENA_Msk  /* Enable Processing of PTP Packets Sent over IPv4-UDP */\n#define ETH_MACTSCR_TSIPV6ENA_Pos                     (12U)\n#define ETH_MACTSCR_TSIPV6ENA_Msk                     (0x1UL << ETH_MACTSCR_TSIPV6ENA_Pos) /*!< 0x00001000 */\n#define ETH_MACTSCR_TSIPV6ENA                         ETH_MACTSCR_TSIPV6ENA_Msk  /* Enable Processing of PTP Packets Sent over IPv6-UDP */\n#define ETH_MACTSCR_TSIPENA_Pos                       (11U)\n#define ETH_MACTSCR_TSIPENA_Msk                       (0x1UL << ETH_MACTSCR_TSIPENA_Pos) /*!< 0x00000800 */\n#define ETH_MACTSCR_TSIPENA                           ETH_MACTSCR_TSIPENA_Msk  /* Enable Processing of PTP over Ethernet Packets */\n#define ETH_MACTSCR_TSVER2ENA_Pos                     (10U)\n#define ETH_MACTSCR_TSVER2ENA_Msk                     (0x1UL << ETH_MACTSCR_TSVER2ENA_Pos) /*!< 0x00000400 */\n#define ETH_MACTSCR_TSVER2ENA                         ETH_MACTSCR_TSVER2ENA_Msk  /* Enable PTP Packet Processing for Version 2 Format */\n#define ETH_MACTSCR_TSCTRLSSR_Pos                     (9U)\n#define ETH_MACTSCR_TSCTRLSSR_Msk                     (0x1UL << ETH_MACTSCR_TSCTRLSSR_Pos) /*!< 0x00000200 */\n#define ETH_MACTSCR_TSCTRLSSR                         ETH_MACTSCR_TSCTRLSSR_Msk  /* Timestamp Digital or Binary Rollover Control */\n#define ETH_MACTSCR_TSENALL_Pos                       (8U)\n#define ETH_MACTSCR_TSENALL_Msk                       (0x1UL << ETH_MACTSCR_TSENALL_Pos) /*!< 0x00000100 */\n#define ETH_MACTSCR_TSENALL                           ETH_MACTSCR_TSENALL_Msk  /* Enable Timestamp for All Packets */\n#define ETH_MACTSCR_TSADDREG_Pos                      (5U)\n#define ETH_MACTSCR_TSADDREG_Msk                      (0x1UL << ETH_MACTSCR_TSADDREG_Pos) /*!< 0x00000020 */\n#define ETH_MACTSCR_TSADDREG                          ETH_MACTSCR_TSADDREG_Msk  /* Update Addend Register */\n#define ETH_MACTSCR_TSUPDT_Pos                        (3U)\n#define ETH_MACTSCR_TSUPDT_Msk                        (0x1UL << ETH_MACTSCR_TSUPDT_Pos) /*!< 0x00000008 */\n#define ETH_MACTSCR_TSUPDT                            ETH_MACTSCR_TSUPDT_Msk  /* Update Timestamp */\n#define ETH_MACTSCR_TSINIT_Pos                        (2U)\n#define ETH_MACTSCR_TSINIT_Msk                        (0x1UL << ETH_MACTSCR_TSINIT_Pos) /*!< 0x00000004 */\n#define ETH_MACTSCR_TSINIT                             ETH_MACTSCR_TSINIT_Msk  /* Initialize Timestamp */\n#define ETH_MACTSCR_TSCFUPDT_Pos                      (1U)\n#define ETH_MACTSCR_TSCFUPDT_Msk                      (0x1UL << ETH_MACTSCR_TSCFUPDT_Pos) /*!< 0x00000002 */\n#define ETH_MACTSCR_TSCFUPDT                          ETH_MACTSCR_TSCFUPDT_Msk  /* Fine or Coarse Timestamp Update*/\n#define ETH_MACTSCR_TSENA_Pos                         (0U)\n#define ETH_MACTSCR_TSENA_Msk                         (0x1UL << ETH_MACTSCR_TSENA_Pos) /*!< 0x00000001 */\n#define ETH_MACTSCR_TSENA                             ETH_MACTSCR_TSENA_Msk  /* Enable Timestamp */\n\n/* Bit definition for Ethernet MAC Sub-second Increment Register */\n#define ETH_MACMACSSIR_SSINC_Pos                      (16U)\n#define ETH_MACMACSSIR_SSINC_Msk                      (0xFFUL << ETH_MACMACSSIR_SSINC_Pos) /*!< 0x0000FF00 */\n#define ETH_MACMACSSIR_SSINC                          ETH_MACMACSSIR_SSINC_Msk  /* Sub-second Increment Value */\n#define ETH_MACMACSSIR_SNSINC_Pos                     (8U)\n#define ETH_MACMACSSIR_SNSINC_Msk                     (0xFFUL << ETH_MACMACSSIR_SNSINC_Pos) /*!< 0x000000FF */\n#define ETH_MACMACSSIR_SNSINC                         ETH_MACMACSSIR_SNSINC_Msk  /* Sub-nanosecond Increment Value */\n\n/* Bit definition for Ethernet MAC System Time Seconds Register */\n#define ETH_MACSTSR_TSS_Pos                           (0U)\n#define ETH_MACSTSR_TSS_Msk                           (0xFFFFFFFFUL << ETH_MACSTSR_TSS_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MACSTSR_TSS                               ETH_MACSTSR_TSS_Msk  /* Timestamp Second */\n\n/* Bit definition for Ethernet MAC System Time Nanoseconds Register */\n#define ETH_MACSTNR_TSSS_Pos                          (0U)\n#define ETH_MACSTNR_TSSS_Msk                          (0x7FFFFFFFUL << ETH_MACSTNR_TSSS_Pos) /*!< 0x7FFFFFFF */\n#define ETH_MACSTNR_TSSS                              ETH_MACSTNR_TSSS_Msk  /* Timestamp Sub-seconds */\n\n/* Bit definition for Ethernet MAC System Time Seconds Update Register */\n#define ETH_MACSTSUR_TSS_Pos                          (0U)\n#define ETH_MACSTSUR_TSS_Msk                          (0xFFFFFFFFUL << ETH_MACSTSUR_TSS_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MACSTSUR_TSS                              ETH_MACSTSUR_TSS_Msk  /* Timestamp Seconds */\n\n/* Bit definition for Ethernet MAC System Time Nanoseconds Update Register */\n#define ETH_MACSTNUR_ADDSUB_Pos                       (31U)\n#define ETH_MACSTNUR_ADDSUB_Msk                       (0x1UL << ETH_MACSTNUR_ADDSUB_Pos) /*!< 0x80000000 */\n#define ETH_MACSTNUR_ADDSUB                           ETH_MACSTNUR_ADDSUB_Msk  /* Add or Subtract Time */\n#define ETH_MACSTNUR_TSSS_Pos                         (0U)\n#define ETH_MACSTNUR_TSSS_Msk                         (0x7FFFFFFFUL << ETH_MACSTNUR_TSSS_Pos) /*!< 0x7FFFFFFF */\n#define ETH_MACSTNUR_TSSS                             ETH_MACSTNUR_TSSS_Msk  /* Timestamp Sub-seconds */\n\n/* Bit definition for Ethernet MAC Timestamp Addend Register */\n#define ETH_MACTSAR_TSAR_Pos                          (0U)\n#define ETH_MACTSAR_TSAR_Msk                          (0xFFFFFFFFUL << ETH_MACTSAR_TSAR_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MACTSAR_TSAR                              ETH_MACTSAR_TSAR_Msk  /* Timestamp Addend Register */\n\n/* Bit definition for Ethernet MAC Timestamp Status Register */\n#define ETH_MACTSSR_ATSNS_Pos                         (25U)\n#define ETH_MACTSSR_ATSNS_Msk                         (0x1FUL << ETH_MACTSSR_ATSNS_Pos) /*!< 0x3E000000 */\n#define ETH_MACTSSR_ATSNS                             ETH_MACTSSR_ATSNS_Msk  /* Number of Auxiliary Timestamp Snapshots */\n#define ETH_MACTSSR_ATSSTM_Pos                        (24U)\n#define ETH_MACTSSR_ATSSTM_Msk                        (0x1UL << ETH_MACTSSR_ATSSTM_Pos) /*!< 0x01000000 */\n#define ETH_MACTSSR_ATSSTM                            ETH_MACTSSR_ATSSTM_Msk  /* Auxiliary Timestamp Snapshot Trigger Missed */\n#define ETH_MACTSSR_ATSSTN_Pos                        (16U)\n#define ETH_MACTSSR_ATSSTN_Msk                        (0xFUL << ETH_MACTSSR_ATSSTN_Pos) /*!< 0x000F0000 */\n#define ETH_MACTSSR_ATSSTN                            ETH_MACTSSR_ATSSTN_Msk  /* Auxiliary Timestamp Snapshot Trigger Identifier */\n#define ETH_MACTSSR_TXTSSIS_Pos                       (15U)\n#define ETH_MACTSSR_TXTSSIS_Msk                       (0x1UL << ETH_MACTSSR_TXTSSIS_Pos) /*!< 0x00008000 */\n#define ETH_MACTSSR_TXTSSIS                           ETH_MACTSSR_TXTSSIS_Msk  /* Tx Timestamp Status Interrupt Status */\n#define ETH_MACTSSR_TSTRGTERR0_Pos                    (3U)\n#define ETH_MACTSSR_TSTRGTERR0_Msk                    (0x1UL << ETH_MACTSSR_TSTRGTERR0_Pos) /*!< 0x00000008 */\n#define ETH_MACTSSR_TSTRGTERR0                        ETH_MACTSSR_TSTRGTERR0_Msk  /* Timestamp Target Time Error */\n#define ETH_MACTSSR_AUXTSTRIG_Pos                     (2U)\n#define ETH_MACTSSR_AUXTSTRIG_Msk                     (0x1UL << ETH_MACTSSR_AUXTSTRIG_Pos) /*!< 0x00000004 */\n#define ETH_MACTSSR_AUXTSTRIG                         ETH_MACTSSR_AUXTSTRIG_Msk  /* Auxiliary Timestamp Trigger Snapshot*/\n#define ETH_MACTSSR_TSTARGT0_Pos                      (1U)\n#define ETH_MACTSSR_TSTARGT0_Msk                      (0x1UL << ETH_MACTSSR_TSTARGT0_Pos) /*!< 0x00000002 */\n#define ETH_MACTSSR_TSTARGT0                          ETH_MACTSSR_TSTARGT0_Msk  /* Timestamp Target Time Reached */\n#define ETH_MACTSSR_TSSOVF_Pos                        (0U)\n#define ETH_MACTSSR_TSSOVF_Msk                        (0x1UL << ETH_MACTSSR_TSSOVF_Pos) /*!< 0x00000001 */\n#define ETH_MACTSSR_TSSOVF                            ETH_MACTSSR_TSSOVF_Msk  /* Timestamp Seconds Overflow */\n\n/* Bit definition for Ethernet MAC Tx Timestamp Status Nanoseconds Register */\n#define ETH_MACTTSSNR_TXTSSMIS_Pos                    (31U)\n#define ETH_MACTTSSNR_TXTSSMIS_Msk                    (0x1UL << ETH_MACTTSSNR_TXTSSMIS_Pos) /*!< 0x80000000 */\n#define ETH_MACTTSSNR_TXTSSMIS                        ETH_MACTTSSNR_TXTSSMIS_Msk  /* Transmit Timestamp Status Missed */\n#define ETH_MACTTSSNR_TXTSSLO_Pos                     (0U)\n#define ETH_MACTTSSNR_TXTSSLO_Msk                     (0x7FFFFFFFUL << ETH_MACTTSSNR_TXTSSLO_Pos) /*!< 0x7FFFFFFF */\n#define ETH_MACTTSSNR_TXTSSLO                         ETH_MACTTSSNR_TXTSSLO_Msk  /* Transmit Timestamp Status Low */\n\n/* Bit definition for Ethernet MAC Tx Timestamp Status Seconds Register */\n#define ETH_MACTTSSSR_TXTSSHI_Pos                     (0U)\n#define ETH_MACTTSSSR_TXTSSHI_Msk                     (0xFFFFFFFFUL << ETH_MACTTSSSR_TXTSSHI_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MACTTSSSR_TXTSSHI                         ETH_MACTTSSSR_TXTSSHI_Msk  /* Transmit Timestamp Status High */\n\n/* Bit definition for Ethernet MAC Auxiliary Control Register*/\n#define ETH_MACACR_ATSEN3_Pos                         (7U)\n#define ETH_MACACR_ATSEN3_Msk                         (0x1UL << ETH_MACACR_ATSEN3_Pos) /*!< 0x00000080 */\n#define ETH_MACACR_ATSEN3                             ETH_MACACR_ATSEN3_Msk  /* Auxiliary Snapshot 3 Enable */\n#define ETH_MACACR_ATSEN2_Pos                         (6U)\n#define ETH_MACACR_ATSEN2_Msk                         (0x1UL << ETH_MACACR_ATSEN2_Pos) /*!< 0x00000040 */\n#define ETH_MACACR_ATSEN2                             ETH_MACACR_ATSEN2_Msk  /* Auxiliary Snapshot 2 Enable */\n#define ETH_MACACR_ATSEN1_Pos                         (5U)\n#define ETH_MACACR_ATSEN1_Msk                         (0x1UL << ETH_MACACR_ATSEN1_Pos) /*!< 0x00000020 */\n#define ETH_MACACR_ATSEN1                             ETH_MACACR_ATSEN1_Msk  /* Auxiliary Snapshot 1 Enable */\n#define ETH_MACACR_ATSEN0_Pos                         (4U)\n#define ETH_MACACR_ATSEN0_Msk                         (0x1UL << ETH_MACACR_ATSEN0_Pos) /*!< 0x00000010 */\n#define ETH_MACACR_ATSEN0                             ETH_MACACR_ATSEN0_Msk  /* Auxiliary Snapshot 0 Enable */\n#define ETH_MACACR_ATSFC_Pos                          (0U)\n#define ETH_MACACR_ATSFC_Msk                          (0x1UL << ETH_MACACR_ATSFC_Pos) /*!< 0x00000001 */\n#define ETH_MACACR_ATSFC                              ETH_MACACR_ATSFC_Msk  /* Auxiliary Snapshot FIFO Clear */\n\n/* Bit definition for Ethernet MAC Auxiliary Timestamp Nanoseconds Register */\n#define ETH_MACATSNR_AUXTSLO_Pos                      (0U)\n#define ETH_MACATSNR_AUXTSLO_Msk                      (0x7FFFFFFFUL << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x7FFFFFFF */\n#define ETH_MACATSNR_AUXTSLO                          ETH_MACATSNR_AUXTSLO_Msk  /* Auxiliary Timestamp */\n\n/* Bit definition for Ethernet MAC Auxiliary Timestamp Seconds Register */\n#define ETH_MACATSSR_AUXTSHI_Pos                      (0U)\n#define ETH_MACATSSR_AUXTSHI_Msk                      (0xFFFFFFFFUL << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MACATSSR_AUXTSHI                          ETH_MACATSSR_AUXTSHI_Msk  /* Auxiliary Timestamp */\n\n/* Bit definition for Ethernet MAC Timestamp Ingress Asymmetric Correction Register */\n#define ETH_MACTSIACR_OSTIAC_Pos                      (0U)\n#define ETH_MACTSIACR_OSTIAC_Msk                      (0xFFFFFFFFUL << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MACTSIACR_OSTIAC                          ETH_MACTSIACR_OSTIAC_Msk  /* One-Step Timestamp Ingress Asymmetry Correction */\n\n/* Bit definition for Ethernet MAC Timestamp Egress Asymmetric Correction Register */\n#define ETH_MACTSEACR_OSTEAC_Pos                      (0U)\n#define ETH_MACTSEACR_OSTEAC_Msk                      (0xFFFFFFFFUL << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MACTSEACR_OSTEAC                          ETH_MACTSEACR_OSTEAC_Msk  /* One-Step Timestamp Egress Asymmetry Correction */\n\n/* Bit definition for Ethernet MAC Timestamp Ingress Correction Nanosecond Register */\n#define ETH_MACTSICNR_TSIC_Pos                        (0U)\n#define ETH_MACTSICNR_TSIC_Msk                        (0xFFFFFFFFUL << ETH_MACTSICNR_TSIC_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MACTSICNR_TSIC                            ETH_MACTSICNR_TSIC_Msk  /* Timestamp Ingress Correction */\n\n/* Bit definition for Ethernet MAC Timestamp Egress correction Nanosecond Register */\n#define ETH_MACTSECNR_TSEC_Pos                        (0U)\n#define ETH_MACTSECNR_TSEC_Msk                        (0xFFFFFFFFUL << ETH_MACTSECNR_TSEC_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MACTSECNR_TSEC                            ETH_MACTSECNR_TSEC_Msk  /* Timestamp Egress Correction */\n\n/* Bit definition for Ethernet MAC PPS Control Register */\n#define ETH_MACPPSCR_TRGTMODSEL0_Pos                  (5U)\n#define ETH_MACPPSCR_TRGTMODSEL0_Msk                  (0x3UL << ETH_MACPPSCR_TRGTMODSEL0_Pos) /*!< 0x00000060 */\n#define ETH_MACPPSCR_TRGTMODSEL0                      ETH_MACPPSCR_TRGTMODSEL0_Msk  /* Target Time Register Mode for PPS Output */\n#define ETH_MACPPSCR_PPSEN0_Pos                       (4U)\n#define ETH_MACPPSCR_PPSEN0_Msk                       (0x1UL << ETH_MACPPSCR_PPSEN0_Pos) /*!< 0x00000010 */\n#define ETH_MACPPSCR_PPSEN0                           ETH_MACPPSCR_PPSEN0_Msk  /* Flexible PPS Output Mode Enable */\n#define ETH_MACPPSCR_PPSCTRL_Pos                      (0U)\n#define ETH_MACPPSCR_PPSCTRL_Msk                      (0xFUL << ETH_MACPPSCR_PPSCTRL_Pos) /*!< 0x0000000F */\n#define ETH_MACPPSCR_PPSCTRL                          ETH_MACPPSCR_PPSCTRL_Msk  /* PPS Output Frequency Control */\n\n/* Bit definition for Ethernet MAC PPS Target Time Seconds Register */\n#define ETH_MACPPSTTSR_TSTRH0_Pos                     (0U)\n#define ETH_MACPPSTTSR_TSTRH0_Msk                     (0xFFFFFFFFUL << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MACPPSTTSR_TSTRH0                         ETH_MACPPSTTSR_TSTRH0_Msk  /* PPS Target Time Seconds Register */\n\n/* Bit definition for Ethernet MAC PPS Target Time Nanoseconds Register */\n#define ETH_MACPPSTTNR_TRGTBUSY0_Pos                  (31U)\n#define ETH_MACPPSTTNR_TRGTBUSY0_Msk                  (0x1UL << ETH_MACPPSTTNR_TRGTBUSY0_Pos) /*!< 0x80000000 */\n#define ETH_MACPPSTTNR_TRGTBUSY0                      ETH_MACPPSTTNR_TRGTBUSY0_Msk  /* PPS Target Time Register Busy */\n#define ETH_MACPPSTTNR_TTSL0_Pos                      (0U)\n#define ETH_MACPPSTTNR_TTSL0_Msk                      (0x7FFFFFFFUL << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x7FFFFFFF */\n#define ETH_MACPPSTTNR_TTSL0                          ETH_MACPPSTTNR_TTSL0_Msk  /* Target Time Low for PPS Register */\n\n/* Bit definition for Ethernet MAC PPS Interval Register */\n#define ETH_MACPPSIR_PPSINT0_Pos                      (0U)\n#define ETH_MACPPSIR_PPSINT0_Msk                      (0xFFFFFFFFUL << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MACPPSIR_PPSINT0                          ETH_MACPPSIR_PPSINT0_Msk  /* PPS Output Signal Interval */\n\n/* Bit definition for Ethernet MAC PPS Width Register */\n#define ETH_MACPPSWR_PPSWIDTH0_Pos                    (0U)\n#define ETH_MACPPSWR_PPSWIDTH0_Msk                    (0xFFFFFFFFUL << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MACPPSWR_PPSWIDTH0                        ETH_MACPPSWR_PPSWIDTH0_Msk  /* PPS Output Signal Width */\n\n/* Bit definition for Ethernet MAC PTP Offload Control Register */\n#define ETH_MACPOCR_DN_Pos                            (8U)\n#define ETH_MACPOCR_DN_Msk                            (0xFFUL << ETH_MACPOCR_DN_Pos) /*!< 0x0000FF00 */\n#define ETH_MACPOCR_DN                                ETH_MACPOCR_DN_Msk  /* Domain Number */\n#define ETH_MACPOCR_DRRDIS_Pos                        (6U)\n#define ETH_MACPOCR_DRRDIS_Msk                        (0x1UL << ETH_MACPOCR_DRRDIS_Pos) /*!< 0x00000040 */\n#define ETH_MACPOCR_DRRDIS                            ETH_MACPOCR_DRRDIS_Msk  /* Disable PTO Delay Request/Response response generation */\n#define ETH_MACPOCR_APDREQTRIG_Pos                    (5U)\n#define ETH_MACPOCR_APDREQTRIG_Msk                    (0x1UL << ETH_MACPOCR_APDREQTRIG_Pos) /*!< 0x00000020 */\n#define ETH_MACPOCR_APDREQTRIG                        ETH_MACPOCR_APDREQTRIG_Msk  /* Automatic PTP Pdelay_Req message Trigger */\n#define ETH_MACPOCR_ASYNCTRIG_Pos                     (4U)\n#define ETH_MACPOCR_ASYNCTRIG_Msk                     (0x1UL << ETH_MACPOCR_ASYNCTRIG_Pos) /*!< 0x00000010 */\n#define ETH_MACPOCR_ASYNCTRIG                         ETH_MACPOCR_ASYNCTRIG_Msk  /* Automatic PTP SYNC message Trigger */\n#define ETH_MACPOCR_APDREQEN_Pos                      (2U)\n#define ETH_MACPOCR_APDREQEN_Msk                      (0x1UL << ETH_MACPOCR_APDREQEN_Pos) /*!< 0x00000004 */\n#define ETH_MACPOCR_APDREQEN                          ETH_MACPOCR_APDREQEN_Msk  /* Automatic PTP Pdelay_Req message Enable */\n#define ETH_MACPOCR_ASYNCEN_Pos                       (1U)\n#define ETH_MACPOCR_ASYNCEN_Msk                       (0x1UL << ETH_MACPOCR_ASYNCEN_Pos) /*!< 0x00000002 */\n#define ETH_MACPOCR_ASYNCEN                           ETH_MACPOCR_ASYNCEN_Msk  /* Automatic PTP SYNC message Enable */\n#define ETH_MACPOCR_PTOEN_Pos                         (0U)\n#define ETH_MACPOCR_PTOEN_Msk                         (0x1UL << ETH_MACPOCR_PTOEN_Pos) /*!< 0x00000001 */\n#define ETH_MACPOCR_PTOEN                             ETH_MACPOCR_PTOEN_Msk  /* PTP Offload Enable */\n\n/* Bit definition for Ethernet MAC PTP Source Port Identity 0 Register */\n#define ETH_MACSPI0R_SPI0_Pos                         (0U)\n#define ETH_MACSPI0R_SPI0_Msk                         (0xFFFFFFFFUL << ETH_MACSPI0R_SPI0_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MACSPI0R_SPI0                             ETH_MACSPI0R_SPI0_Msk  /* Source Port Identity 0 */\n\n/* Bit definition for Ethernet MAC PTP Source Port Identity 1 Register */\n#define ETH_MACSPI1R_SPI1_Pos                         (0U)\n#define ETH_MACSPI1R_SPI1_Msk                         (0xFFFFFFFFUL << ETH_MACSPI1R_SPI1_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MACSPI1R_SPI1                             ETH_MACSPI1R_SPI1_Msk  /* Source Port Identity 1 */\n\n/* Bit definition for Ethernet MAC PTP Source Port Identity 2 Register */\n#define ETH_MACSPI2R_SPI2_Pos                         (0U)\n#define ETH_MACSPI2R_SPI2_Msk                         (0xFFFFUL << ETH_MACSPI2R_SPI2_Pos) /*!< 0x0000FFFF */\n#define ETH_MACSPI2R_SPI2                             ETH_MACSPI2R_SPI2_Msk  /* Source Port Identity 2 */\n\n/* Bit definition for Ethernet MAC Log Message Interval Register */\n#define ETH_MACLMIR_LMPDRI_Pos                        (24U)\n#define ETH_MACLMIR_LMPDRI_Msk                        (0xFFUL << ETH_MACLMIR_LMPDRI_Pos) /*!< 0xFF000000 */\n#define ETH_MACLMIR_LMPDRI                             ETH_MACLMIR_LMPDRI_Msk  /* Log Min Pdelay_Req Interval */\n#define ETH_MACLMIR_DRSYNCR_Pos                       (8U)\n#define ETH_MACLMIR_DRSYNCR_Msk                       (0x7UL << ETH_MACLMIR_DRSYNCR_Pos) /*!< 0x00000700 */\n#define ETH_MACLMIR_DRSYNCR                           ETH_MACLMIR_DRSYNCR_Msk  /* Delay_Req to SYNC Ratio */\n#define ETH_MACLMIR_LSI_Pos                           (0U)\n#define ETH_MACLMIR_LSI_Msk                           (0xFFUL << ETH_MACLMIR_LSI_Pos) /*!< 0x000000FF */\n#define ETH_MACLMIR_LSI                               ETH_MACLMIR_LSI_Msk  /* Log Sync Interval */\n\n/* Bit definition for Ethernet MTL Operation Mode Register */\n#define ETH_MTLOMR_CNTCLR_Pos                         (9U)\n#define ETH_MTLOMR_CNTCLR_Msk                         (0x1UL << ETH_MTLOMR_CNTCLR_Pos) /*!< 0x00000200 */\n#define ETH_MTLOMR_CNTCLR                             ETH_MTLOMR_CNTCLR_Msk    /* Counters Reset */\n#define ETH_MTLOMR_CNTPRST_Pos                        (8U)\n#define ETH_MTLOMR_CNTPRST_Msk                        (0x1UL << ETH_MTLOMR_CNTPRST_Pos) /*!< 0x00000100 */\n#define ETH_MTLOMR_CNTPRST                            ETH_MTLOMR_CNTPRST_Msk   /* Counters Preset */\n#define ETH_MTLOMR_DTXSTS_Pos                         (1U)\n#define ETH_MTLOMR_DTXSTS_Msk                         (0x1UL << ETH_MTLOMR_DTXSTS_Pos) /*!< 0x00000002 */\n#define ETH_MTLOMR_DTXSTS                             ETH_MTLOMR_DTXSTS_Msk  /* Drop Transmit Status */\n\n/* Bit definition for Ethernet MTL Interrupt Status Register */\n#define ETH_MTLISR_MACIS_Pos                          (16U)\n#define ETH_MTLISR_MACIS_Msk                          (0x1UL << ETH_MTLISR_MACIS_Pos) /*!< 0x00010000 */\n#define ETH_MTLISR_MACIS                              ETH_MTLISR_MACIS_Msk     /* MAC Interrupt Status */\n#define ETH_MTLISR_QIS_Pos                            (0U)\n#define ETH_MTLISR_QIS_Msk                            (0x1UL << ETH_MTLISR_QIS_Pos) /*!< 0x00000001 */\n#define ETH_MTLISR_QIS                                ETH_MTLISR_QIS_Msk       /* Queue Interrupt status */\n\n/* Bit definition for Ethernet MTL Tx Queue Operation Mode Register */\n#define ETH_MTLTQOMR_TTC_Pos                          (4U)\n#define ETH_MTLTQOMR_TTC_Msk                          (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */\n#define ETH_MTLTQOMR_TTC                              ETH_MTLTQOMR_TTC_Msk     /* Transmit Threshold Control */\n#define ETH_MTLTQOMR_TTC_32BITS                       ((uint32_t)0x00000000)   /* 32 bits Threshold */\n#define ETH_MTLTQOMR_TTC_64BITS                       ((uint32_t)0x00000010)   /* 64  bits Threshold */\n#define ETH_MTLTQOMR_TTC_96BITS                       ((uint32_t)0x00000020)   /* 96 bits Threshold */\n#define ETH_MTLTQOMR_TTC_128BITS                      ((uint32_t)0x00000030)   /* 128 bits Threshold */\n#define ETH_MTLTQOMR_TTC_192BITS                      ((uint32_t)0x00000040)   /* 192 bits Threshold */\n#define ETH_MTLTQOMR_TTC_256BITS                      ((uint32_t)0x00000050)   /* 256 bits Threshold */\n#define ETH_MTLTQOMR_TTC_384BITS                      ((uint32_t)0x00000060)   /* 384 bits Threshold */\n#define ETH_MTLTQOMR_TTC_512BITS                      ((uint32_t)0x00000070)   /* 512 bits Threshold */\n#define ETH_MTLTQOMR_TSF_Pos                          (1U)\n#define ETH_MTLTQOMR_TSF_Msk                          (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */\n#define ETH_MTLTQOMR_TSF                              ETH_MTLTQOMR_TSF_Msk     /* Transmit Store and Forward */\n#define ETH_MTLTQOMR_FTQ_Pos                          (0U)\n#define ETH_MTLTQOMR_FTQ_Msk                          (0x1UL << ETH_MTLTQOMR_FTQ_Pos) /*!< 0x00000001 */\n#define ETH_MTLTQOMR_FTQ                              ETH_MTLTQOMR_FTQ_Msk     /* Flush Transmit Queue */\n\n/* Bit definition for Ethernet MTL Tx Queue Underflow Register */\n#define ETH_MTLTQUR_UFCNTOVF_Pos                      (11U)\n#define ETH_MTLTQUR_UFCNTOVF_Msk                      (0x1UL << ETH_MTLTQUR_UFCNTOVF_Pos) /*!< 0x00000800 */\n#define ETH_MTLTQUR_UFCNTOVF                          ETH_MTLTQUR_UFCNTOVF_Msk /* Overflow Bit for Underflow Packet Counter */\n#define ETH_MTLTQUR_UFPKTCNT_Pos                      (0U)\n#define ETH_MTLTQUR_UFPKTCNT_Msk                      (0x7FFUL << ETH_MTLTQUR_UFPKTCNT_Pos) /*!< 0x000007FF */\n#define ETH_MTLTQUR_UFPKTCNT                          ETH_MTLTQUR_UFPKTCNT_Msk /* Underflow Packet Counter */\n\n/* Bit definition for Ethernet MTL Tx Queue Debug Register */\n#define ETH_MTLTQDR_STXSTSF_Pos                       (20U)\n#define ETH_MTLTQDR_STXSTSF_Msk                       (0x7UL << ETH_MTLTQDR_STXSTSF_Pos) /*!< 0x00700000 */\n#define ETH_MTLTQDR_STXSTSF                           ETH_MTLTQDR_STXSTSF_Msk  /* Number of Status Words in the Tx Status FIFO of Queue */\n#define ETH_MTLTQDR_PTXQ_Pos                          (16U)\n#define ETH_MTLTQDR_PTXQ_Msk                          (0x7UL << ETH_MTLTQDR_PTXQ_Pos) /*!< 0x00070000 */\n#define ETH_MTLTQDR_PTXQ                              ETH_MTLTQDR_PTXQ_Msk     /* Number of Packets in the Transmit Queue */\n#define ETH_MTLTQDR_TXSTSFSTS_Pos                     (5U)\n#define ETH_MTLTQDR_TXSTSFSTS_Msk                     (0x1UL << ETH_MTLTQDR_TXSTSFSTS_Pos) /*!< 0x00000020 */\n#define ETH_MTLTQDR_TXSTSFSTS                         ETH_MTLTQDR_TXSTSFSTS_Msk /* MTL Tx Status FIFO Full Status */\n#define ETH_MTLTQDR_TXQSTS_Pos                        (4U)\n#define ETH_MTLTQDR_TXQSTS_Msk                        (0x1UL << ETH_MTLTQDR_TXQSTS_Pos) /*!< 0x00000010 */\n#define ETH_MTLTQDR_TXQSTS                            ETH_MTLTQDR_TXQSTS_Msk   /* MTL Tx Queue Not Empty Status */\n#define ETH_MTLTQDR_TWCSTS_Pos                        (3U)\n#define ETH_MTLTQDR_TWCSTS_Msk                        (0x1UL << ETH_MTLTQDR_TWCSTS_Pos) /*!< 0x00000008 */\n#define ETH_MTLTQDR_TWCSTS                            ETH_MTLTQDR_TWCSTS_Msk   /* MTL Tx Queue Write Controller Status */\n#define ETH_MTLTQDR_TRCSTS_Pos                        (1U)\n#define ETH_MTLTQDR_TRCSTS_Msk                        (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */\n#define ETH_MTLTQDR_TRCSTS                            ETH_MTLTQDR_TRCSTS_Msk  /* MTL Tx Queue Read Controller Status */\n#define ETH_MTLTQDR_TRCSTS_IDLE                       ((uint32_t)0x00000000)  /* Idle state */\n#define ETH_MTLTQDR_TRCSTS_READ                       ((uint32_t)0x00000002)  /* Read state (transferring data to the MAC transmitter) */\n#define ETH_MTLTQDR_TRCSTS_WAITING                    ((uint32_t)0x00000004)  /* Waiting for pending Tx Status from the MAC transmitter */\n#define ETH_MTLTQDR_TRCSTS_FLUSHING                   ((uint32_t)0x00000006)  /* Flushing the Tx queue because of the Packet Abort request from the MAC */\n#define ETH_MTLTQDR_TXQPAUSED_Pos                     (0U)\n#define ETH_MTLTQDR_TXQPAUSED_Msk                     (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */\n#define ETH_MTLTQDR_TXQPAUSED                         ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */\n\n/* Bit definition for Ethernet MTL Queue Interrupt Control Status Register */\n#define ETH_MTLQICSR_RXOIE_Pos                        (24U)\n#define ETH_MTLQICSR_RXOIE_Msk                        (0x1UL << ETH_MTLQICSR_RXOIE_Pos) /*!< 0x01000000 */\n#define ETH_MTLQICSR_RXOIE                            ETH_MTLQICSR_RXOIE_Msk   /* Receive Queue Overflow Interrupt Enable */\n#define ETH_MTLQICSR_RXOVFIS_Pos                      (16U)\n#define ETH_MTLQICSR_RXOVFIS_Msk                      (0x1UL << ETH_MTLQICSR_RXOVFIS_Pos) /*!< 0x00010000 */\n#define ETH_MTLQICSR_RXOVFIS                          ETH_MTLQICSR_RXOVFIS_Msk /* Receive Queue Overflow Interrupt Status */\n#define ETH_MTLQICSR_TXUIE_Pos                        (8U)\n#define ETH_MTLQICSR_TXUIE_Msk                        (0x1UL << ETH_MTLQICSR_TXUIE_Pos) /*!< 0x00000100 */\n#define ETH_MTLQICSR_TXUIE                            ETH_MTLQICSR_TXUIE_Msk   /* Transmit Queue Underflow Interrupt Enable */\n#define ETH_MTLQICSR_TXUNFIS_Pos                      (0U)\n#define ETH_MTLQICSR_TXUNFIS_Msk                      (0x1UL << ETH_MTLQICSR_TXUNFIS_Pos) /*!< 0x00000001 */\n#define ETH_MTLQICSR_TXUNFIS                          ETH_MTLQICSR_TXUNFIS_Msk /* Transmit Queue Underflow Interrupt Status */\n\n/* Bit definition for Ethernet MTL Rx Queue Operation Mode Register */\n#define ETH_MTLRQOMR_RQS_Pos                          (20U)\n#define ETH_MTLRQOMR_RQS_Msk                          (0x7UL << ETH_MTLRQOMR_RQS_Pos) /*!< 0x00700000 */\n#define ETH_MTLRQOMR_RQS                              ETH_MTLRQOMR_RQS_Msk /* Receive Queue Size */\n#define ETH_MTLRQOMR_RFD_Pos                          (14U)\n#define ETH_MTLRQOMR_RFD_Msk                          (0x7UL << ETH_MTLRQOMR_RFD_Pos) /*!< 0x0001C000 */\n#define ETH_MTLRQOMR_RFD                              ETH_MTLRQOMR_RFD_Msk /* Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) */\n#define ETH_MTLRQOMR_RFA_Pos                          (8U)\n#define ETH_MTLRQOMR_RFA_Msk                          (0x7UL << ETH_MTLRQOMR_RFA_Pos) /*!< 0x00000700 */\n#define ETH_MTLRQOMR_RFA                              ETH_MTLRQOMR_RFA_Msk /* Threshold for Activating Flow Control (in half-duplex and full-duplex */\n#define ETH_MTLRQOMR_EHFC_Pos                         (7U)\n#define ETH_MTLRQOMR_EHFC_Msk                         (0x1UL << ETH_MTLRQOMR_EHFC_Pos) /*!< 0x00000080 */\n#define ETH_MTLRQOMR_EHFC                             ETH_MTLRQOMR_EHFC_Msk /* DEnable Hardware Flow Control */\n#define ETH_MTLRQOMR_DISTCPEF_Pos                     (6U)\n#define ETH_MTLRQOMR_DISTCPEF_Msk                     (0x1UL << ETH_MTLRQOMR_DISTCPEF_Pos) /*!< 0x00000040 */\n#define ETH_MTLRQOMR_DISTCPEF                         ETH_MTLRQOMR_DISTCPEF_Msk /* Disable Dropping of TCP/IP Checksum Error Packets */\n#define ETH_MTLRQOMR_RSF_Pos                          (5U)\n#define ETH_MTLRQOMR_RSF_Msk                          (0x1UL << ETH_MTLRQOMR_RSF_Pos) /*!< 0x00000020 */\n#define ETH_MTLRQOMR_RSF                              ETH_MTLRQOMR_RSF_Msk     /* Receive Queue Store and Forward */\n#define ETH_MTLRQOMR_FEP_Pos                          (4U)\n#define ETH_MTLRQOMR_FEP_Msk                          (0x1UL << ETH_MTLRQOMR_FEP_Pos) /*!< 0x00000010 */\n#define ETH_MTLRQOMR_FEP                              ETH_MTLRQOMR_FEP_Msk     /* Forward Error Packets */\n#define ETH_MTLRQOMR_FUP_Pos                          (3U)\n#define ETH_MTLRQOMR_FUP_Msk                          (0x1UL << ETH_MTLRQOMR_FUP_Pos) /*!< 0x00000008 */\n#define ETH_MTLRQOMR_FUP                              ETH_MTLRQOMR_FUP_Msk     /* Forward Undersized Good Packets */\n#define ETH_MTLRQOMR_RTC_Pos                          (0U)\n#define ETH_MTLRQOMR_RTC_Msk                          (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */\n#define ETH_MTLRQOMR_RTC                              ETH_MTLRQOMR_RTC_Msk     /* Receive Queue Threshold Control */\n#define ETH_MTLRQOMR_RTC_64BITS                       ((uint32_t)0x00000000)   /* 64 bits Threshold */\n#define ETH_MTLRQOMR_RTC_32BITS                       ((uint32_t)0x00000001)   /* 32 bits Threshold */\n#define ETH_MTLRQOMR_RTC_96BITS                       ((uint32_t)0x00000002)   /* 96 bits Threshold */\n#define ETH_MTLRQOMR_RTC_128BITS                      ((uint32_t)0x00000003)   /* 128 bits Threshold */\n\n/* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */\n#define ETH_MTLRQMPOCR_MISCNTOVF_Pos                  (27U)\n#define ETH_MTLRQMPOCR_MISCNTOVF_Msk                  (0x1UL << ETH_MTLRQMPOCR_MISCNTOVF_Pos) /*!< 0x08000000 */\n#define ETH_MTLRQMPOCR_MISCNTOVF                      ETH_MTLRQMPOCR_MISCNTOVF_Msk /* Missed Packet Counter Overflow Bit */\n#define ETH_MTLRQMPOCR_MISPKTCNT_Pos                  (16U)\n#define ETH_MTLRQMPOCR_MISPKTCNT_Msk                  (0x7FFUL << ETH_MTLRQMPOCR_MISPKTCNT_Pos) /*!< 0x07FF0000 */\n#define ETH_MTLRQMPOCR_MISPKTCNT                      ETH_MTLRQMPOCR_MISPKTCNT_Msk /* Missed Packet Counter */\n#define ETH_MTLRQMPOCR_OVFCNTOVF_Pos                  (11U)\n#define ETH_MTLRQMPOCR_OVFCNTOVF_Msk                  (0x1UL << ETH_MTLRQMPOCR_OVFCNTOVF_Pos) /*!< 0x00000800 */\n#define ETH_MTLRQMPOCR_OVFCNTOVF                      ETH_MTLRQMPOCR_OVFCNTOVF_Msk /* Overflow Counter Overflow Bit */\n#define ETH_MTLRQMPOCR_OVFPKTCNT_Pos                  (0U)\n#define ETH_MTLRQMPOCR_OVFPKTCNT_Msk                  (0x7FFUL << ETH_MTLRQMPOCR_OVFPKTCNT_Pos) /*!< 0x000007FF */\n#define ETH_MTLRQMPOCR_OVFPKTCNT                      ETH_MTLRQMPOCR_OVFPKTCNT_Msk /* Overflow Packet Counter */\n\n/* Bit definition for Ethernet MTL Rx Queue Debug Register */\n#define ETH_MTLRQDR_PRXQ_Pos                          (16U)\n#define ETH_MTLRQDR_PRXQ_Msk                          (0x3FFFUL << ETH_MTLRQDR_PRXQ_Pos) /*!< 0x3FFF0000 */\n#define ETH_MTLRQDR_PRXQ                              ETH_MTLRQDR_PRXQ_Msk     /* Number of Packets in Receive Queue */\n#define ETH_MTLRQDR_RXQSTS_Pos                        (4U)\n#define ETH_MTLRQDR_RXQSTS_Msk                        (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */\n#define ETH_MTLRQDR_RXQSTS                            ETH_MTLRQDR_RXQSTS_Msk   /* MTL Rx Queue Fill-Level Status */\n#define ETH_MTLRQDR_RXQSTS_EMPTY                      ((uint32_t)0x00000000)   /* Rx Queue empty */\n#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos         (4U)\n#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk         (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */\n#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD             ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */\n#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos         (5U)\n#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk         (0x1UL << ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos) /*!< 0x00000020 */\n#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD             ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk /* Rx Queue fill-level above flow-control activate threshold */\n#define ETH_MTLRQDR_RXQSTS_FULL_Pos                   (4U)\n#define ETH_MTLRQDR_RXQSTS_FULL_Msk                   (0x3UL << ETH_MTLRQDR_RXQSTS_FULL_Pos) /*!< 0x00000030 */\n#define ETH_MTLRQDR_RXQSTS_FULL                       ETH_MTLRQDR_RXQSTS_FULL_Msk /* Rx Queue full */\n#define ETH_MTLRQDR_RRCSTS_Pos                        (1U)\n#define ETH_MTLRQDR_RRCSTS_Msk                        (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */\n#define ETH_MTLRQDR_RRCSTS                            ETH_MTLRQDR_RRCSTS_Msk   /* MTL Rx Queue Read Controller State */\n#define ETH_MTLRQDR_RRCSTS_IDLE                       ((uint32_t)0x00000000)   /* Idle state */\n#define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos            (1U)\n#define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk            (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */\n#define ETH_MTLRQDR_RRCSTS_READINGDATA                ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */\n#define ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos          (2U)\n#define ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk          (0x1UL << ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos) /*!< 0x00000004 */\n#define ETH_MTLRQDR_RRCSTS_READINGSTATUS              ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk /* Reading packet status (or timestamp) */\n#define ETH_MTLRQDR_RRCSTS_FLUSHING_Pos               (1U)\n#define ETH_MTLRQDR_RRCSTS_FLUSHING_Msk               (0x3UL << ETH_MTLRQDR_RRCSTS_FLUSHING_Pos) /*!< 0x00000006 */\n#define ETH_MTLRQDR_RRCSTS_FLUSHING                   ETH_MTLRQDR_RRCSTS_FLUSHING_Msk /* Flushing the packet data and status */\n#define ETH_MTLRQDR_RWCSTS_Pos                        (0U)\n#define ETH_MTLRQDR_RWCSTS_Msk                        (0x1UL << ETH_MTLRQDR_RWCSTS_Pos) /*!< 0x00000001 */\n#define ETH_MTLRQDR_RWCSTS                            ETH_MTLRQDR_RWCSTS_Msk   /* MTL Rx Queue Write Controller Active Status */\n\n/* Bit definition for Ethernet MTL Rx Queue Control Register */\n#define ETH_MTLRQCR_RQPA_Pos                          (3U)\n#define ETH_MTLRQCR_RQPA_Msk                          (0x1UL << ETH_MTLRQCR_RQPA_Pos) /*!< 0x00000008 */\n#define ETH_MTLRQCR_RQPA                              ETH_MTLRQCR_RQPA_Msk     /* Receive Queue Packet Arbitration */\n#define ETH_MTLRQCR_RQW_Pos                           (0U)\n#define ETH_MTLRQCR_RQW_Msk                           (0x7UL << ETH_MTLRQCR_RQW_Pos) /*!< 0x00000007 */\n#define ETH_MTLRQCR_RQW                               ETH_MTLRQCR_RQW_Msk      /* Receive Queue Weight */\n\n/* Bit definition for Ethernet DMA Mode Register */\n#define ETH_DMAMR_INTM_Pos                            (16U)\n#define ETH_DMAMR_INTM_Msk                            (0x3UL << ETH_DMAMR_INTM_Pos) /*!< 0x00030000 */\n#define ETH_DMAMR_INTM                                ETH_DMAMR_INTM_Msk       /* This field defines the interrupt mode */\n#define ETH_DMAMR_INTM_0                              (0x0UL << ETH_DMAMR_INTM_Pos) /*!< 0x00000000 */\n#define ETH_DMAMR_INTM_1                              (0x1UL << ETH_DMAMR_INTM_Pos) /*!< 0x00010000 */\n#define ETH_DMAMR_INTM_2                              (0x2UL << ETH_DMAMR_INTM_Pos) /*!< 0x00020000 */\n#define ETH_DMAMR_PR_Pos                              (12U)\n#define ETH_DMAMR_PR_Msk                              (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */\n#define ETH_DMAMR_PR                                  ETH_DMAMR_PR_Msk         /* Priority Ratio */\n#define ETH_DMAMR_PR_1_1                              ((uint32_t)0x00000000)   /* The priority ratio is 1:1 */\n#define ETH_DMAMR_PR_2_1                              ((uint32_t)0x00001000)   /* The priority ratio is 2:1 */\n#define ETH_DMAMR_PR_3_1                              ((uint32_t)0x00002000)   /* The priority ratio is 3:1 */\n#define ETH_DMAMR_PR_4_1                              ((uint32_t)0x00003000)   /* The priority ratio is 4:1 */\n#define ETH_DMAMR_PR_5_1                              ((uint32_t)0x00004000)   /* The priority ratio is 5:1 */\n#define ETH_DMAMR_PR_6_1                              ((uint32_t)0x00005000)   /* The priority ratio is 6:1 */\n#define ETH_DMAMR_PR_7_1                              ((uint32_t)0x00006000)   /* The priority ratio is 7:1 */\n#define ETH_DMAMR_PR_8_1                              ((uint32_t)0x00007000)   /* The priority ratio is 8:1 */\n#define ETH_DMAMR_TXPR_Pos                            (11U)\n#define ETH_DMAMR_TXPR_Msk                            (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */\n#define ETH_DMAMR_TXPR                                ETH_DMAMR_TXPR_Msk       /* Transmit Priority */\n#define ETH_DMAMR_DA_Pos                              (1U)\n#define ETH_DMAMR_DA_Msk                              (0x1UL << ETH_DMAMR_DA_Pos) /*!< 0x00000002 */\n#define ETH_DMAMR_DA                                  ETH_DMAMR_DA_Msk         /* DMA Tx or Rx Arbitration Scheme */\n#define ETH_DMAMR_SWR_Pos                             (0U)\n#define ETH_DMAMR_SWR_Msk                             (0x1UL << ETH_DMAMR_SWR_Pos) /*!< 0x00000001 */\n#define ETH_DMAMR_SWR                                 ETH_DMAMR_SWR_Msk        /* Software Reset */\n\n/* Bit definition for Ethernet DMA SysBus Mode Register */\n#define ETH_DMASBMR_RB_Pos                            (15U)\n#define ETH_DMASBMR_RB_Msk                            (0x1UL << ETH_DMASBMR_RB_Pos) /*!< 0x00008000 */\n#define ETH_DMASBMR_RB                                ETH_DMASBMR_RB_Msk       /* Rebuild INCRx Burst */\n#define ETH_DMASBMR_MB_Pos                            (14U)\n#define ETH_DMASBMR_MB_Msk                            (0x1UL << ETH_DMASBMR_MB_Pos) /*!< 0x00004000 */\n#define ETH_DMASBMR_MB                                ETH_DMASBMR_MB_Msk       /* Mixed Burst */\n#define ETH_DMASBMR_AAL_Pos                           (12U)\n#define ETH_DMASBMR_AAL_Msk                           (0x1UL << ETH_DMASBMR_AAL_Pos) /*!< 0x00001000 */\n#define ETH_DMASBMR_AAL                               ETH_DMASBMR_AAL_Msk      /* Address-Aligned Beats */\n#define ETH_DMASBMR_FB_Pos                            (0U)\n#define ETH_DMASBMR_FB_Msk                            (0x1UL << ETH_DMASBMR_FB_Pos) /*!< 0x00000001 */\n#define ETH_DMASBMR_FB                                ETH_DMASBMR_FB_Msk       /* Fixed Burst Length */\n\n/* Bit definition for Ethernet DMA Interrupt Status Register */\n#define ETH_DMAISR_MACIS_Pos                          (17U)\n#define ETH_DMAISR_MACIS_Msk                          (0x1UL << ETH_DMAISR_MACIS_Pos) /*!< 0x00020000 */\n#define ETH_DMAISR_MACIS                              ETH_DMAISR_MACIS_Msk     /* MAC Interrupt Status */\n#define ETH_DMAISR_MTLIS_Pos                          (16U)\n#define ETH_DMAISR_MTLIS_Msk                          (0x1UL << ETH_DMAISR_MTLIS_Pos) /*!< 0x00010000 */\n#define ETH_DMAISR_MTLIS                              ETH_DMAISR_MTLIS_Msk     /* MAC Interrupt Status */\n#define ETH_DMAISR_DMACIS_Pos                         (0U)\n#define ETH_DMAISR_DMACIS_Msk                         (0x1UL << ETH_DMAISR_DMACIS_Pos) /*!< 0x00000001 */\n#define ETH_DMAISR_DMACIS                             ETH_DMAISR_DMACIS_Msk    /* DMA Channel Interrupt Status */\n\n/* Bit definition for Ethernet DMA Debug Status Register */\n#define ETH_DMADSR_TPS_Pos                            (12U)\n#define ETH_DMADSR_TPS_Msk                            (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */\n#define ETH_DMADSR_TPS                                ETH_DMADSR_TPS_Msk       /* DMA Channel Transmit Process State */\n#define ETH_DMADSR_TPS_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Transmit Command issued) */\n#define ETH_DMADSR_TPS_FETCHING_Pos                   (12U)\n#define ETH_DMADSR_TPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */\n#define ETH_DMADSR_TPS_FETCHING                       ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */\n#define ETH_DMADSR_TPS_WAITING_Pos                    (13U)\n#define ETH_DMADSR_TPS_WAITING_Msk                    (0x1UL << ETH_DMADSR_TPS_WAITING_Pos) /*!< 0x00002000 */\n#define ETH_DMADSR_TPS_WAITING                        ETH_DMADSR_TPS_WAITING_Msk /* Running (Waiting for status) */\n#define ETH_DMADSR_TPS_READING_Pos                    (12U)\n#define ETH_DMADSR_TPS_READING_Msk                    (0x3UL << ETH_DMADSR_TPS_READING_Pos) /*!< 0x00003000 */\n#define ETH_DMADSR_TPS_READING                        ETH_DMADSR_TPS_READING_Msk /* Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) */\n#define ETH_DMADSR_TPS_TIMESTAMP_WR_Pos               (14U)\n#define ETH_DMADSR_TPS_TIMESTAMP_WR_Msk               (0x1UL << ETH_DMADSR_TPS_TIMESTAMP_WR_Pos) /*!< 0x00004000 */\n#define ETH_DMADSR_TPS_TIMESTAMP_WR                   ETH_DMADSR_TPS_TIMESTAMP_WR_Msk /* Timestamp write state */\n#define ETH_DMADSR_TPS_SUSPENDED_Pos                  (13U)\n#define ETH_DMADSR_TPS_SUSPENDED_Msk                  (0x3UL << ETH_DMADSR_TPS_SUSPENDED_Pos) /*!< 0x00006000 */\n#define ETH_DMADSR_TPS_SUSPENDED                      ETH_DMADSR_TPS_SUSPENDED_Msk /* Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) */\n#define ETH_DMADSR_TPS_CLOSING_Pos                    (12U)\n#define ETH_DMADSR_TPS_CLOSING_Msk                    (0x7UL << ETH_DMADSR_TPS_CLOSING_Pos) /*!< 0x00007000 */\n#define ETH_DMADSR_TPS_CLOSING                        ETH_DMADSR_TPS_CLOSING_Msk /* Running (Closing Tx Descriptor) */\n#define ETH_DMADSR_RPS_Pos                            (8U)\n#define ETH_DMADSR_RPS_Msk                            (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */\n#define ETH_DMADSR_RPS                                ETH_DMADSR_RPS_Msk       /* DMA Channel Receive Process State */\n#define ETH_DMADSR_RPS_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Receive Command issued) */\n#define ETH_DMADSR_RPS_FETCHING_Pos                   (12U)\n#define ETH_DMADSR_RPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */\n#define ETH_DMADSR_RPS_FETCHING                       ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */\n#define ETH_DMADSR_RPS_WAITING_Pos                    (12U)\n#define ETH_DMADSR_RPS_WAITING_Msk                    (0x3UL << ETH_DMADSR_RPS_WAITING_Pos) /*!< 0x00003000 */\n#define ETH_DMADSR_RPS_WAITING                        ETH_DMADSR_RPS_WAITING_Msk /* Running (Waiting for status) */\n#define ETH_DMADSR_RPS_SUSPENDED_Pos                  (14U)\n#define ETH_DMADSR_RPS_SUSPENDED_Msk                  (0x1UL << ETH_DMADSR_RPS_SUSPENDED_Pos) /*!< 0x00004000 */\n#define ETH_DMADSR_RPS_SUSPENDED                      ETH_DMADSR_RPS_SUSPENDED_Msk /* Suspended (Rx Descriptor Unavailable) */\n#define ETH_DMADSR_RPS_CLOSING_Pos                    (12U)\n#define ETH_DMADSR_RPS_CLOSING_Msk                    (0x5UL << ETH_DMADSR_RPS_CLOSING_Pos) /*!< 0x00005000 */\n#define ETH_DMADSR_RPS_CLOSING                        ETH_DMADSR_RPS_CLOSING_Msk /* Running (Closing the Rx Descriptor) */\n#define ETH_DMADSR_RPS_TIMESTAMP_WR_Pos               (13U)\n#define ETH_DMADSR_RPS_TIMESTAMP_WR_Msk               (0x3UL << ETH_DMADSR_RPS_TIMESTAMP_WR_Pos) /*!< 0x00006000 */\n#define ETH_DMADSR_RPS_TIMESTAMP_WR                   ETH_DMADSR_RPS_TIMESTAMP_WR_Msk /* Timestamp write state */\n#define ETH_DMADSR_RPS_TRANSFERRING_Pos               (12U)\n#define ETH_DMADSR_RPS_TRANSFERRING_Msk               (0x7UL << ETH_DMADSR_RPS_TRANSFERRING_Pos) /*!< 0x00007000 */\n#define ETH_DMADSR_RPS_TRANSFERRING                   ETH_DMADSR_RPS_TRANSFERRING_Msk /* Running (Transferring the received packet data from the Rx buffer to the system memory) */\n\n/* Bit definition for Ethernet DMA Channel Control Register */\n#define ETH_DMACCR_DSL_Pos                            (18U)\n#define ETH_DMACCR_DSL_Msk                            (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */\n#define ETH_DMACCR_DSL                                ETH_DMACCR_DSL_Msk       /* Descriptor Skip Length */\n#define ETH_DMACCR_DSL_0BIT                           ((uint32_t)0x00000000)\n#define ETH_DMACCR_DSL_32BIT                          ((uint32_t)0x00040000)\n#define ETH_DMACCR_DSL_64BIT                          ((uint32_t)0x00080000)\n#define ETH_DMACCR_DSL_128BIT                         ((uint32_t)0x00100000)\n#define ETH_DMACCR_8PBL                               ((uint32_t)0x00010000)   /* 8xPBL mode */\n#define ETH_DMACCR_MSS_Pos                            (0U)\n#define ETH_DMACCR_MSS_Msk                            (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */\n#define ETH_DMACCR_MSS                                ETH_DMACCR_MSS_Msk       /* Maximum Segment Size */\n\n/* Bit definition for Ethernet DMA Channel Tx Control Register */\n#define ETH_DMACTCR_TPBL_Pos                          (16U)\n#define ETH_DMACTCR_TPBL_Msk                          (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */\n#define ETH_DMACTCR_TPBL                              ETH_DMACTCR_TPBL_Msk     /* Transmit Programmable Burst Length */\n#define ETH_DMACTCR_TPBL_1PBL                         ((uint32_t)0x00010000)   /* Transmit Programmable Burst Length 1 */\n#define ETH_DMACTCR_TPBL_2PBL                         ((uint32_t)0x00020000)   /* Transmit Programmable Burst Length 2 */\n#define ETH_DMACTCR_TPBL_4PBL                         ((uint32_t)0x00040000)   /* Transmit Programmable Burst Length 4 */\n#define ETH_DMACTCR_TPBL_8PBL                         ((uint32_t)0x00080000)   /* Transmit Programmable Burst Length 8 */\n#define ETH_DMACTCR_TPBL_16PBL                        ((uint32_t)0x00100000)   /* Transmit Programmable Burst Length 16 */\n#define ETH_DMACTCR_TPBL_32PBL                        ((uint32_t)0x00200000)   /* Transmit Programmable Burst Length 32 */\n#define ETH_DMACTCR_TSE_Pos                           (12U)\n#define ETH_DMACTCR_TSE_Msk                           (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */\n#define ETH_DMACTCR_TSE                               ETH_DMACTCR_TSE_Msk      /* TCP Segmentation Enabled */\n#define ETH_DMACTCR_OSP_Pos                           (4U)\n#define ETH_DMACTCR_OSP_Msk                           (0x1UL << ETH_DMACTCR_OSP_Pos) /*!< 0x00000010 */\n#define ETH_DMACTCR_OSP                               ETH_DMACTCR_OSP_Msk      /* Operate on Second Packet */\n#define ETH_DMACTCR_ST_Pos                            (0U)\n#define ETH_DMACTCR_ST_Msk                            (0x1UL << ETH_DMACTCR_ST_Pos) /*!< 0x00000001 */\n#define ETH_DMACTCR_ST                                ETH_DMACTCR_ST_Msk       /* Start or Stop Transmission Command */\n\n/* Bit definition for Ethernet DMA Channel Rx Control Register */\n#define ETH_DMACRCR_RPF_Pos                           (31U)\n#define ETH_DMACRCR_RPF_Msk                           (0x1UL << ETH_DMACRCR_RPF_Pos) /*!< 0x80000000 */\n#define ETH_DMACRCR_RPF                               ETH_DMACRCR_RPF_Msk      /* Rx Packet Flush */\n#define ETH_DMACRCR_RPBL_Pos                          (16U)\n#define ETH_DMACRCR_RPBL_Msk                          (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */\n#define ETH_DMACRCR_RPBL                              ETH_DMACRCR_RPBL_Msk     /* Receive Programmable Burst Length */\n#define ETH_DMACRCR_RPBL_1PBL                         ((uint32_t)0x00010000)   /* Receive Programmable Burst Length 1 */\n#define ETH_DMACRCR_RPBL_2PBL                         ((uint32_t)0x00020000)   /* Receive Programmable Burst Length 2 */\n#define ETH_DMACRCR_RPBL_4PBL                         ((uint32_t)0x00040000)   /* Receive Programmable Burst Length 4 */\n#define ETH_DMACRCR_RPBL_8PBL                         ((uint32_t)0x00080000)   /* Receive Programmable Burst Length 8 */\n#define ETH_DMACRCR_RPBL_16PBL                        ((uint32_t)0x00100000)   /* Receive Programmable Burst Length 16 */\n#define ETH_DMACRCR_RPBL_32PBL                        ((uint32_t)0x00200000)   /* Receive Programmable Burst Length 32 */\n#define ETH_DMACRCR_RBSZ_Pos                          (1U)\n#define ETH_DMACRCR_RBSZ_Msk                          (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */\n#define ETH_DMACRCR_RBSZ                              ETH_DMACRCR_RBSZ_Msk     /* Receive Buffer size */\n#define ETH_DMACRCR_SR_Pos                            (0U)\n#define ETH_DMACRCR_SR_Msk                            (0x1UL << ETH_DMACRCR_SR_Pos) /*!< 0x00000001 */\n#define ETH_DMACRCR_SR                                ETH_DMACRCR_SR_Msk       /* Start or Stop Receive */\n\n/* Bit definition for Ethernet DMA CH Tx Desc List Address Register */\n#define ETH_DMACTDLAR_TDESLA_Pos                      (2U)\n#define ETH_DMACTDLAR_TDESLA_Msk                      (0x3FFFFFFFUL << ETH_DMACTDLAR_TDESLA_Pos) /*!< 0xFFFFFFFC */\n#define ETH_DMACTDLAR_TDESLA                          ETH_DMACTDLAR_TDESLA_Msk /* Start of Transmit List */\n\n/* Bit definition for Ethernet DMA CH Rx Desc List Address Register */\n#define ETH_DMACRDLAR_RDESLA_Pos                      (2U)\n#define ETH_DMACRDLAR_RDESLA_Msk                      (0x3FFFFFFFUL << ETH_DMACRDLAR_RDESLA_Pos) /*!< 0xFFFFFFFC */\n#define ETH_DMACRDLAR_RDESLA                          ETH_DMACRDLAR_RDESLA_Msk /* Start of Receive List */\n\n/* Bit definition for Ethernet DMA CH Tx Desc Tail Pointer Register */\n#define ETH_DMACTDTPR_TDT_Pos                         (2U)\n#define ETH_DMACTDTPR_TDT_Msk                         (0x3FFFFFFFUL << ETH_DMACTDTPR_TDT_Pos) /*!< 0xFFFFFFFC */\n#define ETH_DMACTDTPR_TDT                             ETH_DMACTDTPR_TDT_Msk    /* Transmit Descriptor Tail Pointer */\n\n/* Bit definition for Ethernet DMA CH Rx Desc Tail Pointer Register */\n#define ETH_DMACRDTPR_RDT_Pos                         (2U)\n#define ETH_DMACRDTPR_RDT_Msk                         (0x3FFFFFFFUL << ETH_DMACRDTPR_RDT_Pos) /*!< 0xFFFFFFFC */\n#define ETH_DMACRDTPR_RDT                             ETH_DMACRDTPR_RDT_Msk    /* Receive Descriptor Tail Pointer */\n\n/* Bit definition for Ethernet DMA CH Tx Desc Ring Length Register */\n#define ETH_DMACTDRLR_TDRL_Pos                        (0U)\n#define ETH_DMACTDRLR_TDRL_Msk                        (0x3FFUL << ETH_DMACTDRLR_TDRL_Pos) /*!< 0x000003FF */\n#define ETH_DMACTDRLR_TDRL                            ETH_DMACTDRLR_TDRL_Msk   /* Transmit Descriptor Ring Length */\n\n/* Bit definition for Ethernet DMA CH Rx Desc Ring Length Register */\n#define ETH_DMACRDRLR_RDRL_Pos                        (0U)\n#define ETH_DMACRDRLR_RDRL_Msk                        (0x3FFUL << ETH_DMACRDRLR_RDRL_Pos) /*!< 0x000003FF */\n#define ETH_DMACRDRLR_RDRL                            ETH_DMACRDRLR_RDRL_Msk   /* Receive Descriptor Ring Length */\n\n/* Bit definition for Ethernet DMA Channel Interrupt Enable Register */\n#define ETH_DMACIER_NIE_Pos                           (15U)\n#define ETH_DMACIER_NIE_Msk                           (0x1UL << ETH_DMACIER_NIE_Pos) /*!< 0x00008000 */\n#define ETH_DMACIER_NIE                               ETH_DMACIER_NIE_Msk      /* Normal Interrupt Summary Enable */\n#define ETH_DMACIER_AIE_Pos                           (14U)\n#define ETH_DMACIER_AIE_Msk                           (0x1UL << ETH_DMACIER_AIE_Pos) /*!< 0x00004000 */\n#define ETH_DMACIER_AIE                               ETH_DMACIER_AIE_Msk      /* Abnormal Interrupt Summary Enable */\n#define ETH_DMACIER_CDEE_Pos                          (13U)\n#define ETH_DMACIER_CDEE_Msk                          (0x1UL << ETH_DMACIER_CDEE_Pos) /*!< 0x00002000 */\n#define ETH_DMACIER_CDEE                              ETH_DMACIER_CDEE_Msk     /* Context Descriptor Error Enable */\n#define ETH_DMACIER_FBEE_Pos                          (12U)\n#define ETH_DMACIER_FBEE_Msk                          (0x1UL << ETH_DMACIER_FBEE_Pos) /*!< 0x00001000 */\n#define ETH_DMACIER_FBEE                              ETH_DMACIER_FBEE_Msk     /* Fatal Bus Error Enable */\n#define ETH_DMACIER_ERIE_Pos                          (11U)\n#define ETH_DMACIER_ERIE_Msk                          (0x1UL << ETH_DMACIER_ERIE_Pos) /*!< 0x00000800 */\n#define ETH_DMACIER_ERIE                              ETH_DMACIER_ERIE_Msk     /* Early Receive Interrupt Enable */\n#define ETH_DMACIER_ETIE_Pos                          (10U)\n#define ETH_DMACIER_ETIE_Msk                          (0x1UL << ETH_DMACIER_ETIE_Pos) /*!< 0x00000400 */\n#define ETH_DMACIER_ETIE                              ETH_DMACIER_ETIE_Msk     /* Early Transmit Interrupt Enable */\n#define ETH_DMACIER_RWTE_Pos                          (9U)\n#define ETH_DMACIER_RWTE_Msk                          (0x1UL << ETH_DMACIER_RWTE_Pos) /*!< 0x00000200 */\n#define ETH_DMACIER_RWTE                              ETH_DMACIER_RWTE_Msk     /* Receive Watchdog Timeout Enable */\n#define ETH_DMACIER_RSE_Pos                           (8U)\n#define ETH_DMACIER_RSE_Msk                           (0x1UL << ETH_DMACIER_RSE_Pos) /*!< 0x00000100 */\n#define ETH_DMACIER_RSE                               ETH_DMACIER_RSE_Msk      /* Receive Stopped Enable */\n#define ETH_DMACIER_RBUE_Pos                          (7U)\n#define ETH_DMACIER_RBUE_Msk                          (0x1UL << ETH_DMACIER_RBUE_Pos) /*!< 0x00000080 */\n#define ETH_DMACIER_RBUE                              ETH_DMACIER_RBUE_Msk     /* Receive Buffer Unavailable Enable */\n#define ETH_DMACIER_RIE_Pos                           (6U)\n#define ETH_DMACIER_RIE_Msk                           (0x1UL << ETH_DMACIER_RIE_Pos) /*!< 0x00000040 */\n#define ETH_DMACIER_RIE                               ETH_DMACIER_RIE_Msk      /* Receive Interrupt Enable */\n#define ETH_DMACIER_TBUE_Pos                          (2U)\n#define ETH_DMACIER_TBUE_Msk                          (0x1UL << ETH_DMACIER_TBUE_Pos) /*!< 0x00000004 */\n#define ETH_DMACIER_TBUE                              ETH_DMACIER_TBUE_Msk     /* Transmit Buffer Unavailable Enable */\n#define ETH_DMACIER_TXSE_Pos                          (1U)\n#define ETH_DMACIER_TXSE_Msk                          (0x1UL << ETH_DMACIER_TXSE_Pos) /*!< 0x00000002 */\n#define ETH_DMACIER_TXSE                              ETH_DMACIER_TXSE_Msk     /* Transmit Stopped Enable */\n#define ETH_DMACIER_TIE_Pos                           (0U)\n#define ETH_DMACIER_TIE_Msk                           (0x1UL << ETH_DMACIER_TIE_Pos) /*!< 0x00000001 */\n#define ETH_DMACIER_TIE                               ETH_DMACIER_TIE_Msk      /* Transmit Interrupt Enable */\n\n/* Bit definition for Ethernet DMA Channel Rx Interrupt Watchdog Timer Register */\n#define ETH_DMACRIWTR_RWT_Pos                         (0U)\n#define ETH_DMACRIWTR_RWT_Msk                         (0xFFUL << ETH_DMACRIWTR_RWT_Pos) /*!< 0x000000FF */\n#define ETH_DMACRIWTR_RWT                             ETH_DMACRIWTR_RWT_Msk    /* Receive Interrupt Watchdog Timer Count */\n\n/* Bit definition for Ethernet DMA Channel Current App Tx Desc Register */\n#define ETH_DMACCATDR_CURTDESAPTR_Pos                 (0U)\n#define ETH_DMACCATDR_CURTDESAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCATDR_CURTDESAPTR_Pos) /*!< 0xFFFFFFFF */\n#define ETH_DMACCATDR_CURTDESAPTR                     ETH_DMACCATDR_CURTDESAPTR_Msk /* Application Transmit Descriptor Address Pointer */\n\n/* Bit definition for Ethernet DMA Channel Current App Rx Desc Register */\n#define ETH_DMACCARDR_CURRDESAPTR_Pos                 (0U)\n#define ETH_DMACCARDR_CURRDESAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCARDR_CURRDESAPTR_Pos) /*!< 0xFFFFFFFF */\n#define ETH_DMACCARDR_CURRDESAPTR                     ETH_DMACCARDR_CURRDESAPTR_Msk /* Application Receive Descriptor Address Pointer */\n\n/* Bit definition for Ethernet DMA Channel Current App Tx Buffer Register */\n#define ETH_DMACCATBR_CURTBUFAPTR_Pos                 (0U)\n#define ETH_DMACCATBR_CURTBUFAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCATBR_CURTBUFAPTR_Pos) /*!< 0xFFFFFFFF */\n#define ETH_DMACCATBR_CURTBUFAPTR                     ETH_DMACCATBR_CURTBUFAPTR_Msk /* Application Transmit Buffer Address Pointer */\n\n/* Bit definition for Ethernet DMA Channel Current App Rx Buffer Register */\n#define ETH_DMACCARBR_CURRBUFAPTR_Pos                 (0U)\n#define ETH_DMACCARBR_CURRBUFAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCARBR_CURRBUFAPTR_Pos) /*!< 0xFFFFFFFF */\n#define ETH_DMACCARBR_CURRBUFAPTR                     ETH_DMACCARBR_CURRBUFAPTR_Msk /* Application Receive Buffer Address Pointer */\n\n/* Bit definition for Ethernet DMA Channel Status Register */\n#define ETH_DMACSR_REB_Pos                            (19U)\n#define ETH_DMACSR_REB_Msk                            (0x7UL << ETH_DMACSR_REB_Pos) /*!< 0x00380000 */\n#define ETH_DMACSR_REB                                ETH_DMACSR_REB_Msk       /* Rx DMA Error Bits */\n#define ETH_DMACSR_TEB_Pos                            (16U)\n#define ETH_DMACSR_TEB_Msk                            (0x7UL << ETH_DMACSR_TEB_Pos) /*!< 0x00070000 */\n#define ETH_DMACSR_TEB                                ETH_DMACSR_TEB_Msk       /* Tx DMA Error Bits */\n#define ETH_DMACSR_NIS_Pos                            (15U)\n#define ETH_DMACSR_NIS_Msk                            (0x1UL << ETH_DMACSR_NIS_Pos) /*!< 0x00008000 */\n#define ETH_DMACSR_NIS                                ETH_DMACSR_NIS_Msk       /* Normal Interrupt Summary */\n#define ETH_DMACSR_AIS_Pos                            (14U)\n#define ETH_DMACSR_AIS_Msk                            (0x1UL << ETH_DMACSR_AIS_Pos) /*!< 0x00004000 */\n#define ETH_DMACSR_AIS                                ETH_DMACSR_AIS_Msk       /* Abnormal Interrupt Summary */\n#define ETH_DMACSR_CDE_Pos                            (13U)\n#define ETH_DMACSR_CDE_Msk                            (0x1UL << ETH_DMACSR_CDE_Pos) /*!< 0x00002000 */\n#define ETH_DMACSR_CDE                                ETH_DMACSR_CDE_Msk       /* Context Descriptor Error */\n#define ETH_DMACSR_FBE_Pos                            (12U)\n#define ETH_DMACSR_FBE_Msk                            (0x1UL << ETH_DMACSR_FBE_Pos) /*!< 0x00001000 */\n#define ETH_DMACSR_FBE                                ETH_DMACSR_FBE_Msk       /* Fatal Bus Error */\n#define ETH_DMACSR_ERI_Pos                            (11U)\n#define ETH_DMACSR_ERI_Msk                            (0x1UL << ETH_DMACSR_ERI_Pos) /*!< 0x00000800 */\n#define ETH_DMACSR_ERI                                ETH_DMACSR_ERI_Msk       /* Early Receive Interrupt */\n#define ETH_DMACSR_ETI_Pos                            (10U)\n#define ETH_DMACSR_ETI_Msk                            (0x1UL << ETH_DMACSR_ETI_Pos) /*!< 0x00000400 */\n#define ETH_DMACSR_ETI                                ETH_DMACSR_ETI_Msk       /* Early Transmit Interrupt */\n#define ETH_DMACSR_RWT_Pos                            (9U)\n#define ETH_DMACSR_RWT_Msk                            (0x1UL << ETH_DMACSR_RWT_Pos) /*!< 0x00000200 */\n#define ETH_DMACSR_RWT                                ETH_DMACSR_RWT_Msk       /* Receive Watchdog Timeout */\n#define ETH_DMACSR_RPS_Pos                            (8U)\n#define ETH_DMACSR_RPS_Msk                            (0x1UL << ETH_DMACSR_RPS_Pos) /*!< 0x00000100 */\n#define ETH_DMACSR_RPS                                ETH_DMACSR_RPS_Msk       /* Receive Process Stopped */\n#define ETH_DMACSR_RBU_Pos                            (7U)\n#define ETH_DMACSR_RBU_Msk                            (0x1UL << ETH_DMACSR_RBU_Pos) /*!< 0x00000080 */\n#define ETH_DMACSR_RBU                                ETH_DMACSR_RBU_Msk       /* Receive Buffer Unavailable */\n#define ETH_DMACSR_RI_Pos                             (6U)\n#define ETH_DMACSR_RI_Msk                             (0x1UL << ETH_DMACSR_RI_Pos) /*!< 0x00000040 */\n#define ETH_DMACSR_RI                                 ETH_DMACSR_RI_Msk        /* Receive Interrupt */\n#define ETH_DMACSR_TBU_Pos                            (2U)\n#define ETH_DMACSR_TBU_Msk                            (0x1UL << ETH_DMACSR_TBU_Pos) /*!< 0x00000004 */\n#define ETH_DMACSR_TBU                                ETH_DMACSR_TBU_Msk       /* Transmit Buffer Unavailable */\n#define ETH_DMACSR_TPS_Pos                            (1U)\n#define ETH_DMACSR_TPS_Msk                            (0x1UL << ETH_DMACSR_TPS_Pos) /*!< 0x00000002 */\n#define ETH_DMACSR_TPS                                ETH_DMACSR_TPS_Msk       /* Transmit Process Stopped */\n#define ETH_DMACSR_TI_Pos                             (0U)\n#define ETH_DMACSR_TI_Msk                             (0x1UL << ETH_DMACSR_TI_Pos) /*!< 0x00000001 */\n#define ETH_DMACSR_TI                                 ETH_DMACSR_TI_Msk        /* Transmit Interrupt */\n\n/* Bit definition for Ethernet DMA Channel missed frame count register */\n#define ETH_DMACMFCR_MFCO_Pos                         (15U)\n#define ETH_DMACMFCR_MFCO_Msk                         (0x1UL << ETH_DMACMFCR_MFCO_Pos) /*!< 0x00008000 */\n#define ETH_DMACMFCR_MFCO                             ETH_DMACMFCR_MFCO_Msk    /* Overflow status of the MFC Counter */\n#define ETH_DMACMFCR_MFC_Pos                          (0U)\n#define ETH_DMACMFCR_MFC_Msk                          (0x7FFUL << ETH_DMACMFCR_MFC_Pos) /*!< 0x000007FF */\n#define ETH_DMACMFCR_MFC                              ETH_DMACMFCR_MFC_Msk     /* The number of packet counters dropped by the DMA */\n\n/******************************************************************************/\n/*                                                                            */\n/*                             DMA Controller                                 */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bits definition for DMA_SxCR register  *****************/\n#define DMA_SxCR_MBURST_Pos      (23U)\n#define DMA_SxCR_MBURST_Msk      (0x3UL << DMA_SxCR_MBURST_Pos)                /*!< 0x01800000 */\n#define DMA_SxCR_MBURST          DMA_SxCR_MBURST_Msk                           /*!< Memory burst transfer configuration */\n#define DMA_SxCR_MBURST_0        (0x1UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x00800000 */\n#define DMA_SxCR_MBURST_1        (0x2UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x01000000 */\n#define DMA_SxCR_PBURST_Pos      (21U)\n#define DMA_SxCR_PBURST_Msk      (0x3UL << DMA_SxCR_PBURST_Pos)                /*!< 0x00600000 */\n#define DMA_SxCR_PBURST          DMA_SxCR_PBURST_Msk                           /*!< Peripheral burst transfer configuration */\n#define DMA_SxCR_PBURST_0        (0x1UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00200000 */\n#define DMA_SxCR_PBURST_1        (0x2UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00400000 */\n#define DMA_SxCR_TRBUFF_Pos      (20U)\n#define DMA_SxCR_TRBUFF_Msk      (0x1UL << DMA_SxCR_TRBUFF_Pos)                 /*!< 0x00100000 */\n#define DMA_SxCR_TRBUFF          DMA_SxCR_TRBUFF_Msk                            /*!< bufferable transfers enabled/disable */\n#define DMA_SxCR_CT_Pos          (19U)\n#define DMA_SxCR_CT_Msk          (0x1UL << DMA_SxCR_CT_Pos)                    /*!< 0x00080000 */\n#define DMA_SxCR_CT              DMA_SxCR_CT_Msk                               /*!< Current target (only in double buffer mode) */\n#define DMA_SxCR_DBM_Pos         (18U)\n#define DMA_SxCR_DBM_Msk         (0x1UL << DMA_SxCR_DBM_Pos)                   /*!< 0x00040000 */\n#define DMA_SxCR_DBM             DMA_SxCR_DBM_Msk                              /*!< Double buffer mode */\n#define DMA_SxCR_PL_Pos          (16U)\n#define DMA_SxCR_PL_Msk          (0x3UL << DMA_SxCR_PL_Pos)                    /*!< 0x00030000 */\n#define DMA_SxCR_PL              DMA_SxCR_PL_Msk                               /*!< Priority level */\n#define DMA_SxCR_PL_0            (0x1UL << DMA_SxCR_PL_Pos)                     /*!< 0x00010000 */\n#define DMA_SxCR_PL_1            (0x2UL << DMA_SxCR_PL_Pos)                     /*!< 0x00020000 */\n#define DMA_SxCR_PINCOS_Pos      (15U)\n#define DMA_SxCR_PINCOS_Msk      (0x1UL << DMA_SxCR_PINCOS_Pos)                /*!< 0x00008000 */\n#define DMA_SxCR_PINCOS          DMA_SxCR_PINCOS_Msk                           /*!< Peripheral increment offset size */\n#define DMA_SxCR_MSIZE_Pos       (13U)\n#define DMA_SxCR_MSIZE_Msk       (0x3UL << DMA_SxCR_MSIZE_Pos)                 /*!< 0x00006000 */\n#define DMA_SxCR_MSIZE           DMA_SxCR_MSIZE_Msk                            /*!< Memory data size */\n#define DMA_SxCR_MSIZE_0         (0x1UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00002000 */\n#define DMA_SxCR_MSIZE_1         (0x2UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00004000 */\n#define DMA_SxCR_PSIZE_Pos       (11U)\n#define DMA_SxCR_PSIZE_Msk       (0x3UL << DMA_SxCR_PSIZE_Pos)                 /*!< 0x00001800 */\n#define DMA_SxCR_PSIZE           DMA_SxCR_PSIZE_Msk                            /*< Peripheral data size */\n#define DMA_SxCR_PSIZE_0         (0x1UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00000800 */\n#define DMA_SxCR_PSIZE_1         (0x2UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001000 */\n#define DMA_SxCR_MINC_Pos        (10U)\n#define DMA_SxCR_MINC_Msk        (0x1UL << DMA_SxCR_MINC_Pos)                  /*!< 0x00000400 */\n#define DMA_SxCR_MINC            DMA_SxCR_MINC_Msk                             /*!< Memory increment mode */\n#define DMA_SxCR_PINC_Pos        (9U)\n#define DMA_SxCR_PINC_Msk        (0x1UL << DMA_SxCR_PINC_Pos)                  /*!< 0x00000200 */\n#define DMA_SxCR_PINC            DMA_SxCR_PINC_Msk                             /*!< Peripheral increment mode */\n#define DMA_SxCR_CIRC_Pos        (8U)\n#define DMA_SxCR_CIRC_Msk        (0x1UL << DMA_SxCR_CIRC_Pos)                  /*!< 0x00000100 */\n#define DMA_SxCR_CIRC            DMA_SxCR_CIRC_Msk                             /*!< Circular mode */\n#define DMA_SxCR_DIR_Pos         (6U)\n#define DMA_SxCR_DIR_Msk         (0x3UL << DMA_SxCR_DIR_Pos)                   /*!< 0x000000C0 */\n#define DMA_SxCR_DIR             DMA_SxCR_DIR_Msk                              /*!< Data transfer direction */\n#define DMA_SxCR_DIR_0           (0x1UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000040 */\n#define DMA_SxCR_DIR_1           (0x2UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000080 */\n#define DMA_SxCR_PFCTRL_Pos      (5U)\n#define DMA_SxCR_PFCTRL_Msk      (0x1UL << DMA_SxCR_PFCTRL_Pos)                /*!< 0x00000020 */\n#define DMA_SxCR_PFCTRL          DMA_SxCR_PFCTRL_Msk                           /*!< Peripheral flow controller */\n#define DMA_SxCR_TCIE_Pos        (4U)\n#define DMA_SxCR_TCIE_Msk        (0x1UL << DMA_SxCR_TCIE_Pos)                  /*!< 0x00000010 */\n#define DMA_SxCR_TCIE            DMA_SxCR_TCIE_Msk                             /*!< Transfer complete interrupt enable */\n#define DMA_SxCR_HTIE_Pos        (3U)\n#define DMA_SxCR_HTIE_Msk        (0x1UL << DMA_SxCR_HTIE_Pos)                  /*!< 0x00000008 */\n#define DMA_SxCR_HTIE            DMA_SxCR_HTIE_Msk                             /*!< Half transfer interrupt enable */\n#define DMA_SxCR_TEIE_Pos        (2U)\n#define DMA_SxCR_TEIE_Msk        (0x1UL << DMA_SxCR_TEIE_Pos)                  /*!< 0x00000004 */\n#define DMA_SxCR_TEIE            DMA_SxCR_TEIE_Msk                             /*!< Transfer error interrupt enable */\n#define DMA_SxCR_DMEIE_Pos       (1U)\n#define DMA_SxCR_DMEIE_Msk       (0x1UL << DMA_SxCR_DMEIE_Pos)                 /*!< 0x00000002 */\n#define DMA_SxCR_DMEIE           DMA_SxCR_DMEIE_Msk                            /*!< Direct mode error interrupt enable */\n#define DMA_SxCR_EN_Pos          (0U)\n#define DMA_SxCR_EN_Msk          (0x1UL << DMA_SxCR_EN_Pos)                    /*!< 0x00000001 */\n#define DMA_SxCR_EN              DMA_SxCR_EN_Msk                               /*!< Stream enable / flag stream ready when read low */\n\n/********************  Bits definition for DMA_SxCNDTR register  **************/\n#define DMA_SxNDT_Pos            (0U)\n#define DMA_SxNDT_Msk            (0xFFFFUL << DMA_SxNDT_Pos)                   /*!< 0x0000FFFF */\n#define DMA_SxNDT                DMA_SxNDT_Msk                                 /*!< Number of data items to transfer */\n#define DMA_SxNDT_0              (0x0001UL << DMA_SxNDT_Pos)                    /*!< 0x00000001 */\n#define DMA_SxNDT_1              (0x0002UL << DMA_SxNDT_Pos)                    /*!< 0x00000002 */\n#define DMA_SxNDT_2              (0x0004UL << DMA_SxNDT_Pos)                    /*!< 0x00000004 */\n#define DMA_SxNDT_3              (0x0008UL << DMA_SxNDT_Pos)                    /*!< 0x00000008 */\n#define DMA_SxNDT_4              (0x0010UL << DMA_SxNDT_Pos)                    /*!< 0x00000010 */\n#define DMA_SxNDT_5              (0x0020UL << DMA_SxNDT_Pos)                    /*!< 0x00000020 */\n#define DMA_SxNDT_6              (0x0040UL << DMA_SxNDT_Pos)                    /*!< 0x00000040 */\n#define DMA_SxNDT_7              (0x0080UL << DMA_SxNDT_Pos)                    /*!< 0x00000080 */\n#define DMA_SxNDT_8              (0x0100UL << DMA_SxNDT_Pos)                    /*!< 0x00000100 */\n#define DMA_SxNDT_9              (0x0200UL << DMA_SxNDT_Pos)                    /*!< 0x00000200 */\n#define DMA_SxNDT_10             (0x0400UL << DMA_SxNDT_Pos)                    /*!< 0x00000400 */\n#define DMA_SxNDT_11             (0x0800UL << DMA_SxNDT_Pos)                    /*!< 0x00000800 */\n#define DMA_SxNDT_12             (0x1000UL << DMA_SxNDT_Pos)                    /*!< 0x00001000 */\n#define DMA_SxNDT_13             (0x2000UL << DMA_SxNDT_Pos)                    /*!< 0x00002000 */\n#define DMA_SxNDT_14             (0x4000UL << DMA_SxNDT_Pos)                    /*!< 0x00004000 */\n#define DMA_SxNDT_15             (0x8000UL << DMA_SxNDT_Pos)                    /*!< 0x00008000 */\n\n/********************  Bits definition for DMA_SxFCR register  ****************/\n#define DMA_SxFCR_FEIE_Pos       (7U)\n#define DMA_SxFCR_FEIE_Msk       (0x1UL << DMA_SxFCR_FEIE_Pos)                 /*!< 0x00000080 */\n#define DMA_SxFCR_FEIE           DMA_SxFCR_FEIE_Msk                            /*!< FIFO error interrupt enable */\n#define DMA_SxFCR_FS_Pos         (3U)\n#define DMA_SxFCR_FS_Msk         (0x7UL << DMA_SxFCR_FS_Pos)                   /*!< 0x00000038 */\n#define DMA_SxFCR_FS             DMA_SxFCR_FS_Msk                              /*!< FIFO status */\n#define DMA_SxFCR_FS_0           (0x1UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000008 */\n#define DMA_SxFCR_FS_1           (0x2UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000010 */\n#define DMA_SxFCR_FS_2           (0x4UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000020 */\n#define DMA_SxFCR_DMDIS_Pos      (2U)\n#define DMA_SxFCR_DMDIS_Msk      (0x1UL << DMA_SxFCR_DMDIS_Pos)                /*!< 0x00000004 */\n#define DMA_SxFCR_DMDIS          DMA_SxFCR_DMDIS_Msk                           /*!< Direct mode disable */\n#define DMA_SxFCR_FTH_Pos        (0U)\n#define DMA_SxFCR_FTH_Msk        (0x3UL << DMA_SxFCR_FTH_Pos)                  /*!< 0x00000003 */\n#define DMA_SxFCR_FTH            DMA_SxFCR_FTH_Msk                             /*!< FIFO threshold selection */\n#define DMA_SxFCR_FTH_0          (0x1UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000001 */\n#define DMA_SxFCR_FTH_1          (0x2UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000002 */\n\n/********************  Bits definition for DMA_LISR register  *****************/\n#define DMA_LISR_TCIF3_Pos       (27U)\n#define DMA_LISR_TCIF3_Msk       (0x1UL << DMA_LISR_TCIF3_Pos)                 /*!< 0x08000000 */\n#define DMA_LISR_TCIF3           DMA_LISR_TCIF3_Msk                            /*!<  Stream 3 transfer complete interrupt flag */\n#define DMA_LISR_HTIF3_Pos       (26U)\n#define DMA_LISR_HTIF3_Msk       (0x1UL << DMA_LISR_HTIF3_Pos)                 /*!< 0x04000000 */\n#define DMA_LISR_HTIF3           DMA_LISR_HTIF3_Msk                            /*!<  Stream 3 half transfer interrupt flag */\n#define DMA_LISR_TEIF3_Pos       (25U)\n#define DMA_LISR_TEIF3_Msk       (0x1UL << DMA_LISR_TEIF3_Pos)                 /*!< 0x02000000 */\n#define DMA_LISR_TEIF3           DMA_LISR_TEIF3_Msk                            /*!<  Stream 3 transfer error interrupt flag */\n#define DMA_LISR_DMEIF3_Pos      (24U)\n#define DMA_LISR_DMEIF3_Msk      (0x1UL << DMA_LISR_DMEIF3_Pos)                /*!< 0x01000000 */\n#define DMA_LISR_DMEIF3          DMA_LISR_DMEIF3_Msk                           /*!<  Stream 3 direct mode error interrupt flag */\n#define DMA_LISR_FEIF3_Pos       (22U)\n#define DMA_LISR_FEIF3_Msk       (0x1UL << DMA_LISR_FEIF3_Pos)                 /*!< 0x00400000 */\n#define DMA_LISR_FEIF3           DMA_LISR_FEIF3_Msk                            /*!<  Stream 3 FIFO error interrupt flag */\n#define DMA_LISR_TCIF2_Pos       (21U)\n#define DMA_LISR_TCIF2_Msk       (0x1UL << DMA_LISR_TCIF2_Pos)                 /*!< 0x00200000 */\n#define DMA_LISR_TCIF2           DMA_LISR_TCIF2_Msk                            /*!<  Stream 2 transfer complete interrupt flag */\n#define DMA_LISR_HTIF2_Pos       (20U)\n#define DMA_LISR_HTIF2_Msk       (0x1UL << DMA_LISR_HTIF2_Pos)                 /*!< 0x00100000 */\n#define DMA_LISR_HTIF2           DMA_LISR_HTIF2_Msk                            /*!<  Stream 2 half transfer interrupt flag */\n#define DMA_LISR_TEIF2_Pos       (19U)\n#define DMA_LISR_TEIF2_Msk       (0x1UL << DMA_LISR_TEIF2_Pos)                 /*!< 0x00080000 */\n#define DMA_LISR_TEIF2           DMA_LISR_TEIF2_Msk                            /*!<  Stream 2 transfer error interrupt flag */\n#define DMA_LISR_DMEIF2_Pos      (18U)\n#define DMA_LISR_DMEIF2_Msk      (0x1UL << DMA_LISR_DMEIF2_Pos)                /*!< 0x00040000 */\n#define DMA_LISR_DMEIF2          DMA_LISR_DMEIF2_Msk                           /*!<  Stream 2 direct mode error interrupt flag */\n#define DMA_LISR_FEIF2_Pos       (16U)\n#define DMA_LISR_FEIF2_Msk       (0x1UL << DMA_LISR_FEIF2_Pos)                 /*!< 0x00010000 */\n#define DMA_LISR_FEIF2           DMA_LISR_FEIF2_Msk                            /*!<  Stream 2 FIFO error interrupt flag */\n#define DMA_LISR_TCIF1_Pos       (11U)\n#define DMA_LISR_TCIF1_Msk       (0x1UL << DMA_LISR_TCIF1_Pos)                 /*!< 0x00000800 */\n#define DMA_LISR_TCIF1           DMA_LISR_TCIF1_Msk                            /*!<  Stream 1 transfer complete interrupt flag */\n#define DMA_LISR_HTIF1_Pos       (10U)\n#define DMA_LISR_HTIF1_Msk       (0x1UL << DMA_LISR_HTIF1_Pos)                 /*!< 0x00000400 */\n#define DMA_LISR_HTIF1           DMA_LISR_HTIF1_Msk                            /*!<  Stream 1 half transfer interrupt flag */\n#define DMA_LISR_TEIF1_Pos       (9U)\n#define DMA_LISR_TEIF1_Msk       (0x1UL << DMA_LISR_TEIF1_Pos)                 /*!< 0x00000200 */\n#define DMA_LISR_TEIF1           DMA_LISR_TEIF1_Msk                            /*!<  Stream 1 transfer error interrupt flag */\n#define DMA_LISR_DMEIF1_Pos      (8U)\n#define DMA_LISR_DMEIF1_Msk      (0x1UL << DMA_LISR_DMEIF1_Pos)                /*!< 0x00000100 */\n#define DMA_LISR_DMEIF1          DMA_LISR_DMEIF1_Msk                           /*!<  Stream 1 direct mode error interrupt flag */\n#define DMA_LISR_FEIF1_Pos       (6U)\n#define DMA_LISR_FEIF1_Msk       (0x1UL << DMA_LISR_FEIF1_Pos)                 /*!< 0x00000040 */\n#define DMA_LISR_FEIF1           DMA_LISR_FEIF1_Msk                            /*!<  Stream 1 FIFO error interrupt flag */\n#define DMA_LISR_TCIF0_Pos       (5U)\n#define DMA_LISR_TCIF0_Msk       (0x1UL << DMA_LISR_TCIF0_Pos)                 /*!< 0x00000020 */\n#define DMA_LISR_TCIF0           DMA_LISR_TCIF0_Msk                            /*!<  Stream 0 transfer complete interrupt flag */\n#define DMA_LISR_HTIF0_Pos       (4U)\n#define DMA_LISR_HTIF0_Msk       (0x1UL << DMA_LISR_HTIF0_Pos)                 /*!< 0x00000010 */\n#define DMA_LISR_HTIF0           DMA_LISR_HTIF0_Msk                            /*!<  Stream 0 half transfer interrupt flag */\n#define DMA_LISR_TEIF0_Pos       (3U)\n#define DMA_LISR_TEIF0_Msk       (0x1UL << DMA_LISR_TEIF0_Pos)                 /*!< 0x00000008 */\n#define DMA_LISR_TEIF0           DMA_LISR_TEIF0_Msk                            /*!<  Stream 0 transfer error interrupt flag */\n#define DMA_LISR_DMEIF0_Pos      (2U)\n#define DMA_LISR_DMEIF0_Msk      (0x1UL << DMA_LISR_DMEIF0_Pos)                /*!< 0x00000004 */\n#define DMA_LISR_DMEIF0          DMA_LISR_DMEIF0_Msk                           /*!<  Stream 0 direct mode error interrupt flag */\n#define DMA_LISR_FEIF0_Pos       (0U)\n#define DMA_LISR_FEIF0_Msk       (0x1UL << DMA_LISR_FEIF0_Pos)                 /*!< 0x00000001 */\n#define DMA_LISR_FEIF0           DMA_LISR_FEIF0_Msk                            /*!<  Stream 0 FIFO error interrupt flag */\n\n/********************  Bits definition for DMA_HISR register  *****************/\n#define DMA_HISR_TCIF7_Pos       (27U)\n#define DMA_HISR_TCIF7_Msk       (0x1UL << DMA_HISR_TCIF7_Pos)                 /*!< 0x08000000 */\n#define DMA_HISR_TCIF7           DMA_HISR_TCIF7_Msk                            /*!<  Stream 7 transfer complete interrupt flag */\n#define DMA_HISR_HTIF7_Pos       (26U)\n#define DMA_HISR_HTIF7_Msk       (0x1UL << DMA_HISR_HTIF7_Pos)                 /*!< 0x04000000 */\n#define DMA_HISR_HTIF7           DMA_HISR_HTIF7_Msk                            /*!<  Stream 7 half transfer interrupt flag */\n#define DMA_HISR_TEIF7_Pos       (25U)\n#define DMA_HISR_TEIF7_Msk       (0x1UL << DMA_HISR_TEIF7_Pos)                 /*!< 0x02000000 */\n#define DMA_HISR_TEIF7           DMA_HISR_TEIF7_Msk                            /*!<  Stream 7 transfer error interrupt flag */\n#define DMA_HISR_DMEIF7_Pos      (24U)\n#define DMA_HISR_DMEIF7_Msk      (0x1UL << DMA_HISR_DMEIF7_Pos)                /*!< 0x01000000 */\n#define DMA_HISR_DMEIF7          DMA_HISR_DMEIF7_Msk                           /*!<  Stream 7 direct mode error interrupt flag */\n#define DMA_HISR_FEIF7_Pos       (22U)\n#define DMA_HISR_FEIF7_Msk       (0x1UL << DMA_HISR_FEIF7_Pos)                 /*!< 0x00400000 */\n#define DMA_HISR_FEIF7           DMA_HISR_FEIF7_Msk                            /*!<  Stream 7 FIFO error interrupt flag */\n#define DMA_HISR_TCIF6_Pos       (21U)\n#define DMA_HISR_TCIF6_Msk       (0x1UL << DMA_HISR_TCIF6_Pos)                 /*!< 0x00200000 */\n#define DMA_HISR_TCIF6           DMA_HISR_TCIF6_Msk                            /*!<  Stream 6 transfer complete interrupt flag */\n#define DMA_HISR_HTIF6_Pos       (20U)\n#define DMA_HISR_HTIF6_Msk       (0x1UL << DMA_HISR_HTIF6_Pos)                 /*!< 0x00100000 */\n#define DMA_HISR_HTIF6           DMA_HISR_HTIF6_Msk                            /*!<  Stream 6 half transfer interrupt flag */\n#define DMA_HISR_TEIF6_Pos       (19U)\n#define DMA_HISR_TEIF6_Msk       (0x1UL << DMA_HISR_TEIF6_Pos)                 /*!< 0x00080000 */\n#define DMA_HISR_TEIF6           DMA_HISR_TEIF6_Msk                            /*!<  Stream 6 transfer error interrupt flag */\n#define DMA_HISR_DMEIF6_Pos      (18U)\n#define DMA_HISR_DMEIF6_Msk      (0x1UL << DMA_HISR_DMEIF6_Pos)                /*!< 0x00040000 */\n#define DMA_HISR_DMEIF6          DMA_HISR_DMEIF6_Msk                           /*!<  Stream 6 direct mode error interrupt flag */\n#define DMA_HISR_FEIF6_Pos       (16U)\n#define DMA_HISR_FEIF6_Msk       (0x1UL << DMA_HISR_FEIF6_Pos)                 /*!< 0x00010000 */\n#define DMA_HISR_FEIF6           DMA_HISR_FEIF6_Msk                            /*!<  Stream 6 FIFO error interrupt flag */\n#define DMA_HISR_TCIF5_Pos       (11U)\n#define DMA_HISR_TCIF5_Msk       (0x1UL << DMA_HISR_TCIF5_Pos)                 /*!< 0x00000800 */\n#define DMA_HISR_TCIF5           DMA_HISR_TCIF5_Msk                            /*!<  Stream 5 transfer complete interrupt flag */\n#define DMA_HISR_HTIF5_Pos       (10U)\n#define DMA_HISR_HTIF5_Msk       (0x1UL << DMA_HISR_HTIF5_Pos)                 /*!< 0x00000400 */\n#define DMA_HISR_HTIF5           DMA_HISR_HTIF5_Msk                            /*!<  Stream 5 half transfer interrupt flag */\n#define DMA_HISR_TEIF5_Pos       (9U)\n#define DMA_HISR_TEIF5_Msk       (0x1UL << DMA_HISR_TEIF5_Pos)                 /*!< 0x00000200 */\n#define DMA_HISR_TEIF5           DMA_HISR_TEIF5_Msk                            /*!<  Stream 5 transfer error interrupt flag */\n#define DMA_HISR_DMEIF5_Pos      (8U)\n#define DMA_HISR_DMEIF5_Msk      (0x1UL << DMA_HISR_DMEIF5_Pos)                /*!< 0x00000100 */\n#define DMA_HISR_DMEIF5          DMA_HISR_DMEIF5_Msk                           /*!<  Stream 5 direct mode error interrupt flag */\n#define DMA_HISR_FEIF5_Pos       (6U)\n#define DMA_HISR_FEIF5_Msk       (0x1UL << DMA_HISR_FEIF5_Pos)                 /*!< 0x00000040 */\n#define DMA_HISR_FEIF5           DMA_HISR_FEIF5_Msk                            /*!<  Stream 5 FIFO error interrupt flag */\n#define DMA_HISR_TCIF4_Pos       (5U)\n#define DMA_HISR_TCIF4_Msk       (0x1UL << DMA_HISR_TCIF4_Pos)                 /*!< 0x00000020 */\n#define DMA_HISR_TCIF4           DMA_HISR_TCIF4_Msk                            /*!<  Stream 4 transfer complete interrupt flag */\n#define DMA_HISR_HTIF4_Pos       (4U)\n#define DMA_HISR_HTIF4_Msk       (0x1UL << DMA_HISR_HTIF4_Pos)                 /*!< 0x00000010 */\n#define DMA_HISR_HTIF4           DMA_HISR_HTIF4_Msk                            /*!<  Stream 4 half transfer interrupt flag */\n#define DMA_HISR_TEIF4_Pos       (3U)\n#define DMA_HISR_TEIF4_Msk       (0x1UL << DMA_HISR_TEIF4_Pos)                 /*!< 0x00000008 */\n#define DMA_HISR_TEIF4           DMA_HISR_TEIF4_Msk                            /*!<  Stream 4 transfer error interrupt flag */\n#define DMA_HISR_DMEIF4_Pos      (2U)\n#define DMA_HISR_DMEIF4_Msk      (0x1UL << DMA_HISR_DMEIF4_Pos)                /*!< 0x00000004 */\n#define DMA_HISR_DMEIF4          DMA_HISR_DMEIF4_Msk                           /*!<  Stream 4 direct mode error interrupt flag */\n#define DMA_HISR_FEIF4_Pos       (0U)\n#define DMA_HISR_FEIF4_Msk       (0x1UL << DMA_HISR_FEIF4_Pos)                 /*!< 0x00000001 */\n#define DMA_HISR_FEIF4           DMA_HISR_FEIF4_Msk                            /*!<  Stream 4 FIFO error interrupt flag */\n\n/********************  Bits definition for DMA_LIFCR register  ****************/\n#define DMA_LIFCR_CTCIF3_Pos     (27U)\n#define DMA_LIFCR_CTCIF3_Msk     (0x1UL << DMA_LIFCR_CTCIF3_Pos)               /*!< 0x08000000 */\n#define DMA_LIFCR_CTCIF3         DMA_LIFCR_CTCIF3_Msk                          /*!<  Stream 3 clear transfer complete interrupt flag */\n#define DMA_LIFCR_CHTIF3_Pos     (26U)\n#define DMA_LIFCR_CHTIF3_Msk     (0x1UL << DMA_LIFCR_CHTIF3_Pos)               /*!< 0x04000000 */\n#define DMA_LIFCR_CHTIF3         DMA_LIFCR_CHTIF3_Msk                          /*!<  Stream 3 clear half transfer interrupt flag */\n#define DMA_LIFCR_CTEIF3_Pos     (25U)\n#define DMA_LIFCR_CTEIF3_Msk     (0x1UL << DMA_LIFCR_CTEIF3_Pos)               /*!< 0x02000000 */\n#define DMA_LIFCR_CTEIF3         DMA_LIFCR_CTEIF3_Msk                          /*!<  Stream 3 clear transfer error interrupt flag */\n#define DMA_LIFCR_CDMEIF3_Pos    (24U)\n#define DMA_LIFCR_CDMEIF3_Msk    (0x1UL << DMA_LIFCR_CDMEIF3_Pos)              /*!< 0x01000000 */\n#define DMA_LIFCR_CDMEIF3        DMA_LIFCR_CDMEIF3_Msk                         /*!<  Stream 3 clear direct mode error interrupt flag */\n#define DMA_LIFCR_CFEIF3_Pos     (22U)\n#define DMA_LIFCR_CFEIF3_Msk     (0x1UL << DMA_LIFCR_CFEIF3_Pos)               /*!< 0x00400000 */\n#define DMA_LIFCR_CFEIF3         DMA_LIFCR_CFEIF3_Msk                          /*!<  Stream 3 clear FIFO error interrupt flag */\n#define DMA_LIFCR_CTCIF2_Pos     (21U)\n#define DMA_LIFCR_CTCIF2_Msk     (0x1UL << DMA_LIFCR_CTCIF2_Pos)               /*!< 0x00200000 */\n#define DMA_LIFCR_CTCIF2         DMA_LIFCR_CTCIF2_Msk                          /*!<  Stream 2 clear transfer complete interrupt flag */\n#define DMA_LIFCR_CHTIF2_Pos     (20U)\n#define DMA_LIFCR_CHTIF2_Msk     (0x1UL << DMA_LIFCR_CHTIF2_Pos)               /*!< 0x00100000 */\n#define DMA_LIFCR_CHTIF2         DMA_LIFCR_CHTIF2_Msk                          /*!<  Stream 2 clear half transfer interrupt flag */\n#define DMA_LIFCR_CTEIF2_Pos     (19U)\n#define DMA_LIFCR_CTEIF2_Msk     (0x1UL << DMA_LIFCR_CTEIF2_Pos)               /*!< 0x00080000 */\n#define DMA_LIFCR_CTEIF2         DMA_LIFCR_CTEIF2_Msk                          /*!<  Stream 2 clear transfer error interrupt flag */\n#define DMA_LIFCR_CDMEIF2_Pos    (18U)\n#define DMA_LIFCR_CDMEIF2_Msk    (0x1UL << DMA_LIFCR_CDMEIF2_Pos)              /*!< 0x00040000 */\n#define DMA_LIFCR_CDMEIF2        DMA_LIFCR_CDMEIF2_Msk                         /*!<  Stream 2 clear direct mode error interrupt flag */\n#define DMA_LIFCR_CFEIF2_Pos     (16U)\n#define DMA_LIFCR_CFEIF2_Msk     (0x1UL << DMA_LIFCR_CFEIF2_Pos)               /*!< 0x00010000 */\n#define DMA_LIFCR_CFEIF2         DMA_LIFCR_CFEIF2_Msk                          /*!<  Stream 2 clear FIFO error interrupt flag */\n#define DMA_LIFCR_CTCIF1_Pos     (11U)\n#define DMA_LIFCR_CTCIF1_Msk     (0x1UL << DMA_LIFCR_CTCIF1_Pos)               /*!< 0x00000800 */\n#define DMA_LIFCR_CTCIF1         DMA_LIFCR_CTCIF1_Msk                          /*!<  Stream 1 clear transfer complete interrupt flag */\n#define DMA_LIFCR_CHTIF1_Pos     (10U)\n#define DMA_LIFCR_CHTIF1_Msk     (0x1UL << DMA_LIFCR_CHTIF1_Pos)               /*!< 0x00000400 */\n#define DMA_LIFCR_CHTIF1         DMA_LIFCR_CHTIF1_Msk                          /*!<  Stream 1 clear half transfer interrupt flag */\n#define DMA_LIFCR_CTEIF1_Pos     (9U)\n#define DMA_LIFCR_CTEIF1_Msk     (0x1UL << DMA_LIFCR_CTEIF1_Pos)               /*!< 0x00000200 */\n#define DMA_LIFCR_CTEIF1         DMA_LIFCR_CTEIF1_Msk                          /*!<  Stream 1 clear transfer error interrupt flag */\n#define DMA_LIFCR_CDMEIF1_Pos    (8U)\n#define DMA_LIFCR_CDMEIF1_Msk    (0x1UL << DMA_LIFCR_CDMEIF1_Pos)              /*!< 0x00000100 */\n#define DMA_LIFCR_CDMEIF1        DMA_LIFCR_CDMEIF1_Msk                         /*!<  Stream 1 clear direct mode error interrupt flag */\n#define DMA_LIFCR_CFEIF1_Pos     (6U)\n#define DMA_LIFCR_CFEIF1_Msk     (0x1UL << DMA_LIFCR_CFEIF1_Pos)               /*!< 0x00000040 */\n#define DMA_LIFCR_CFEIF1         DMA_LIFCR_CFEIF1_Msk                          /*!<  Stream 1 clear FIFO error interrupt flag */\n#define DMA_LIFCR_CTCIF0_Pos     (5U)\n#define DMA_LIFCR_CTCIF0_Msk     (0x1UL << DMA_LIFCR_CTCIF0_Pos)               /*!< 0x00000020 */\n#define DMA_LIFCR_CTCIF0         DMA_LIFCR_CTCIF0_Msk                          /*!<  Stream 0 clear transfer complete interrupt flag */\n#define DMA_LIFCR_CHTIF0_Pos     (4U)\n#define DMA_LIFCR_CHTIF0_Msk     (0x1UL << DMA_LIFCR_CHTIF0_Pos)               /*!< 0x00000010 */\n#define DMA_LIFCR_CHTIF0         DMA_LIFCR_CHTIF0_Msk                          /*!<  Stream 0 clear half transfer interrupt flag */\n#define DMA_LIFCR_CTEIF0_Pos     (3U)\n#define DMA_LIFCR_CTEIF0_Msk     (0x1UL << DMA_LIFCR_CTEIF0_Pos)               /*!< 0x00000008 */\n#define DMA_LIFCR_CTEIF0         DMA_LIFCR_CTEIF0_Msk                          /*!<  Stream 0 clear transfer error interrupt flag */\n#define DMA_LIFCR_CDMEIF0_Pos    (2U)\n#define DMA_LIFCR_CDMEIF0_Msk    (0x1UL << DMA_LIFCR_CDMEIF0_Pos)              /*!< 0x00000004 */\n#define DMA_LIFCR_CDMEIF0        DMA_LIFCR_CDMEIF0_Msk                         /*!<  Stream 0 clear direct mode error interrupt flag */\n#define DMA_LIFCR_CFEIF0_Pos     (0U)\n#define DMA_LIFCR_CFEIF0_Msk     (0x1UL << DMA_LIFCR_CFEIF0_Pos)               /*!< 0x00000001 */\n#define DMA_LIFCR_CFEIF0         DMA_LIFCR_CFEIF0_Msk                          /*!<  Stream 0 clear FIFO error interrupt flag */\n\n/********************  Bits definition for DMA_HIFCR  register  ****************/\n#define DMA_HIFCR_CTCIF7_Pos     (27U)\n#define DMA_HIFCR_CTCIF7_Msk     (0x1UL << DMA_HIFCR_CTCIF7_Pos)               /*!< 0x08000000 */\n#define DMA_HIFCR_CTCIF7         DMA_HIFCR_CTCIF7_Msk                          /*!<  Stream 7 clear transfer complete interrupt flag */\n#define DMA_HIFCR_CHTIF7_Pos     (26U)\n#define DMA_HIFCR_CHTIF7_Msk     (0x1UL << DMA_HIFCR_CHTIF7_Pos)               /*!< 0x04000000 */\n#define DMA_HIFCR_CHTIF7         DMA_HIFCR_CHTIF7_Msk                          /*!<  Stream 7 clear half transfer interrupt flag */\n#define DMA_HIFCR_CTEIF7_Pos     (25U)\n#define DMA_HIFCR_CTEIF7_Msk     (0x1UL << DMA_HIFCR_CTEIF7_Pos)               /*!< 0x02000000 */\n#define DMA_HIFCR_CTEIF7         DMA_HIFCR_CTEIF7_Msk                          /*!<  Stream 7 clear transfer error interrupt flag */\n#define DMA_HIFCR_CDMEIF7_Pos    (24U)\n#define DMA_HIFCR_CDMEIF7_Msk    (0x1UL << DMA_HIFCR_CDMEIF7_Pos)              /*!< 0x01000000 */\n#define DMA_HIFCR_CDMEIF7        DMA_HIFCR_CDMEIF7_Msk                         /*!<  Stream 7 clear direct mode error interrupt flag */\n#define DMA_HIFCR_CFEIF7_Pos     (22U)\n#define DMA_HIFCR_CFEIF7_Msk     (0x1UL << DMA_HIFCR_CFEIF7_Pos)               /*!< 0x00400000 */\n#define DMA_HIFCR_CFEIF7         DMA_HIFCR_CFEIF7_Msk                          /*!<  Stream 7 clear FIFO error interrupt flag */\n#define DMA_HIFCR_CTCIF6_Pos     (21U)\n#define DMA_HIFCR_CTCIF6_Msk     (0x1UL << DMA_HIFCR_CTCIF6_Pos)               /*!< 0x00200000 */\n#define DMA_HIFCR_CTCIF6         DMA_HIFCR_CTCIF6_Msk                          /*!<  Stream 6 clear transfer complete interrupt flag */\n#define DMA_HIFCR_CHTIF6_Pos     (20U)\n#define DMA_HIFCR_CHTIF6_Msk     (0x1UL << DMA_HIFCR_CHTIF6_Pos)               /*!< 0x00100000 */\n#define DMA_HIFCR_CHTIF6         DMA_HIFCR_CHTIF6_Msk                          /*!<  Stream 6 clear half transfer interrupt flag */\n#define DMA_HIFCR_CTEIF6_Pos     (19U)\n#define DMA_HIFCR_CTEIF6_Msk     (0x1UL << DMA_HIFCR_CTEIF6_Pos)               /*!< 0x00080000 */\n#define DMA_HIFCR_CTEIF6         DMA_HIFCR_CTEIF6_Msk                          /*!<  Stream 6 clear transfer error interrupt flag */\n#define DMA_HIFCR_CDMEIF6_Pos    (18U)\n#define DMA_HIFCR_CDMEIF6_Msk    (0x1UL << DMA_HIFCR_CDMEIF6_Pos)              /*!< 0x00040000 */\n#define DMA_HIFCR_CDMEIF6        DMA_HIFCR_CDMEIF6_Msk                         /*!<  Stream 6 clear direct mode error interrupt flag */\n#define DMA_HIFCR_CFEIF6_Pos     (16U)\n#define DMA_HIFCR_CFEIF6_Msk     (0x1UL << DMA_HIFCR_CFEIF6_Pos)               /*!< 0x00010000 */\n#define DMA_HIFCR_CFEIF6         DMA_HIFCR_CFEIF6_Msk                          /*!<  Stream 6 clear FIFO error interrupt flag */\n#define DMA_HIFCR_CTCIF5_Pos     (11U)\n#define DMA_HIFCR_CTCIF5_Msk     (0x1UL << DMA_HIFCR_CTCIF5_Pos)               /*!< 0x00000800 */\n#define DMA_HIFCR_CTCIF5         DMA_HIFCR_CTCIF5_Msk                          /*!<  Stream 5 clear transfer complete interrupt flag */\n#define DMA_HIFCR_CHTIF5_Pos     (10U)\n#define DMA_HIFCR_CHTIF5_Msk     (0x1UL << DMA_HIFCR_CHTIF5_Pos)               /*!< 0x00000400 */\n#define DMA_HIFCR_CHTIF5         DMA_HIFCR_CHTIF5_Msk                          /*!<  Stream 5 clear half transfer interrupt flag */\n#define DMA_HIFCR_CTEIF5_Pos     (9U)\n#define DMA_HIFCR_CTEIF5_Msk     (0x1UL << DMA_HIFCR_CTEIF5_Pos)               /*!< 0x00000200 */\n#define DMA_HIFCR_CTEIF5         DMA_HIFCR_CTEIF5_Msk                          /*!<  Stream 5 clear transfer error interrupt flag */\n#define DMA_HIFCR_CDMEIF5_Pos    (8U)\n#define DMA_HIFCR_CDMEIF5_Msk    (0x1UL << DMA_HIFCR_CDMEIF5_Pos)              /*!< 0x00000100 */\n#define DMA_HIFCR_CDMEIF5        DMA_HIFCR_CDMEIF5_Msk                         /*!<  Stream 5 clear direct mode error interrupt flag */\n#define DMA_HIFCR_CFEIF5_Pos     (6U)\n#define DMA_HIFCR_CFEIF5_Msk     (0x1UL << DMA_HIFCR_CFEIF5_Pos)               /*!< 0x00000040 */\n#define DMA_HIFCR_CFEIF5         DMA_HIFCR_CFEIF5_Msk                          /*!<  Stream 5 clear FIFO error interrupt flag */\n#define DMA_HIFCR_CTCIF4_Pos     (5U)\n#define DMA_HIFCR_CTCIF4_Msk     (0x1UL << DMA_HIFCR_CTCIF4_Pos)               /*!< 0x00000020 */\n#define DMA_HIFCR_CTCIF4         DMA_HIFCR_CTCIF4_Msk                          /*!<  Stream 4 clear transfer complete interrupt flag */\n#define DMA_HIFCR_CHTIF4_Pos     (4U)\n#define DMA_HIFCR_CHTIF4_Msk     (0x1UL << DMA_HIFCR_CHTIF4_Pos)               /*!< 0x00000010 */\n#define DMA_HIFCR_CHTIF4         DMA_HIFCR_CHTIF4_Msk                          /*!<  Stream 4 clear half transfer interrupt flag */\n#define DMA_HIFCR_CTEIF4_Pos     (3U)\n#define DMA_HIFCR_CTEIF4_Msk     (0x1UL << DMA_HIFCR_CTEIF4_Pos)               /*!< 0x00000008 */\n#define DMA_HIFCR_CTEIF4         DMA_HIFCR_CTEIF4_Msk                          /*!<  Stream 4 clear transfer error interrupt flag */\n#define DMA_HIFCR_CDMEIF4_Pos    (2U)\n#define DMA_HIFCR_CDMEIF4_Msk    (0x1UL << DMA_HIFCR_CDMEIF4_Pos)              /*!< 0x00000004 */\n#define DMA_HIFCR_CDMEIF4        DMA_HIFCR_CDMEIF4_Msk                         /*!<  Stream 4 clear direct mode error interrupt flag */\n#define DMA_HIFCR_CFEIF4_Pos     (0U)\n#define DMA_HIFCR_CFEIF4_Msk     (0x1UL << DMA_HIFCR_CFEIF4_Pos)               /*!< 0x00000001 */\n#define DMA_HIFCR_CFEIF4         DMA_HIFCR_CFEIF4_Msk                          /*!<  Stream 4 clear FIFO error interrupt flag */\n\n/******************  Bit definition for DMA_SxPAR register  ********************/\n#define DMA_SxPAR_PA_Pos         (0U)\n#define DMA_SxPAR_PA_Msk         (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)            /*!< 0xFFFFFFFF */\n#define DMA_SxPAR_PA             DMA_SxPAR_PA_Msk                              /*!< Peripheral Address */\n\n/******************  Bit definition for DMA_SxM0AR register  ********************/\n#define DMA_SxM0AR_M0A_Pos       (0U)\n#define DMA_SxM0AR_M0A_Msk       (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)          /*!< 0xFFFFFFFF */\n#define DMA_SxM0AR_M0A           DMA_SxM0AR_M0A_Msk                            /*!< Memory 0 Address */\n\n/******************  Bit definition for DMA_SxM1AR register  ********************/\n#define DMA_SxM1AR_M1A_Pos       (0U)\n#define DMA_SxM1AR_M1A_Msk       (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)          /*!< 0xFFFFFFFF */\n#define DMA_SxM1AR_M1A           DMA_SxM1AR_M1A_Msk                            /*!< Memory 1 Address */\n\n/******************************************************************************/\n/*                                                                            */\n/*                             DMAMUX Controller                              */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bits definition for DMAMUX_CxCR register  **************/\n#define DMAMUX_CxCR_DMAREQ_ID_Pos      (0U)\n#define DMAMUX_CxCR_DMAREQ_ID_Msk      (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos)   /*!< 0x000000FF */\n#define DMAMUX_CxCR_DMAREQ_ID          DMAMUX_CxCR_DMAREQ_ID_Msk               /*!<  DMA request identification */\n#define DMAMUX_CxCR_DMAREQ_ID_0        (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000001 */\n#define DMAMUX_CxCR_DMAREQ_ID_1        (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000002 */\n#define DMAMUX_CxCR_DMAREQ_ID_2        (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000004 */\n#define DMAMUX_CxCR_DMAREQ_ID_3        (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000008 */\n#define DMAMUX_CxCR_DMAREQ_ID_4        (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000010 */\n#define DMAMUX_CxCR_DMAREQ_ID_5        (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000020 */\n#define DMAMUX_CxCR_DMAREQ_ID_6        (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000040 */\n#define DMAMUX_CxCR_DMAREQ_ID_7        (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000080 */\n#define DMAMUX_CxCR_SOIE_Pos           (8U)\n#define DMAMUX_CxCR_SOIE_Msk           (0x1UL << DMAMUX_CxCR_SOIE_Pos)         /*!< 0x00000100 */\n#define DMAMUX_CxCR_SOIE               DMAMUX_CxCR_SOIE_Msk                    /*!<  Synchronization overrun interrupt enable */\n#define DMAMUX_CxCR_EGE_Pos            (9U)\n#define DMAMUX_CxCR_EGE_Msk            (0x1UL << DMAMUX_CxCR_EGE_Pos)          /*!< 0x00000200 */\n#define DMAMUX_CxCR_EGE                DMAMUX_CxCR_EGE_Msk                     /*!<  Event generation enable */\n#define DMAMUX_CxCR_SE_Pos             (16U)\n#define DMAMUX_CxCR_SE_Msk             (0x1UL << DMAMUX_CxCR_SE_Pos)           /*!< 0x00010000 */\n#define DMAMUX_CxCR_SE                 DMAMUX_CxCR_SE_Msk                      /*!<  Synchronization enable */\n#define DMAMUX_CxCR_SPOL_Pos           (17U)\n#define DMAMUX_CxCR_SPOL_Msk           (0x3UL << DMAMUX_CxCR_SPOL_Pos)         /*!< 0x00060000 */\n#define DMAMUX_CxCR_SPOL               DMAMUX_CxCR_SPOL_Msk                    /*!<  Synchronization polarity */\n#define DMAMUX_CxCR_SPOL_0             (0x1UL << DMAMUX_CxCR_SPOL_Pos)          /*!< 0x00020000 */\n#define DMAMUX_CxCR_SPOL_1             (0x2UL << DMAMUX_CxCR_SPOL_Pos)          /*!< 0x00040000 */\n#define DMAMUX_CxCR_NBREQ_Pos          (19U)\n#define DMAMUX_CxCR_NBREQ_Msk          (0x1FUL << DMAMUX_CxCR_NBREQ_Pos)       /*!< 0x00F80000 */\n#define DMAMUX_CxCR_NBREQ              DMAMUX_CxCR_NBREQ_Msk                   /*!<  Number of DMA requests minus 1 to forward */\n#define DMAMUX_CxCR_NBREQ_0            (0x01UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00080000 */\n#define DMAMUX_CxCR_NBREQ_1            (0x02UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00100000 */\n#define DMAMUX_CxCR_NBREQ_2            (0x04UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00200000 */\n#define DMAMUX_CxCR_NBREQ_3            (0x08UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00400000 */\n#define DMAMUX_CxCR_NBREQ_4            (0x10UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00800000 */\n#define DMAMUX_CxCR_SYNC_ID_Pos        (24U)\n#define DMAMUX_CxCR_SYNC_ID_Msk        (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos)     /*!< 0x1F000000 */\n#define DMAMUX_CxCR_SYNC_ID            DMAMUX_CxCR_SYNC_ID_Msk                 /*!<  Synchronization identification */\n#define DMAMUX_CxCR_SYNC_ID_0          (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x01000000 */\n#define DMAMUX_CxCR_SYNC_ID_1          (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x02000000 */\n#define DMAMUX_CxCR_SYNC_ID_2          (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x04000000 */\n#define DMAMUX_CxCR_SYNC_ID_3          (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x08000000 */\n#define DMAMUX_CxCR_SYNC_ID_4          (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x10000000 */\n\n/********************  Bits definition for DMAMUX_CSR register  **************/\n#define DMAMUX_CSR_SOF0_Pos            (0U)\n#define DMAMUX_CSR_SOF0_Msk            (0x1UL << DMAMUX_CSR_SOF0_Pos)          /*!< 0x00000001 */\n#define DMAMUX_CSR_SOF0                DMAMUX_CSR_SOF0_Msk                     /*!< Channel 0 Synchronization overrun event flag */\n#define DMAMUX_CSR_SOF1_Pos            (1U)\n#define DMAMUX_CSR_SOF1_Msk            (0x1UL << DMAMUX_CSR_SOF1_Pos)          /*!< 0x00000002 */\n#define DMAMUX_CSR_SOF1                DMAMUX_CSR_SOF1_Msk                     /*!< Channel 1 Synchronization overrun event flag */\n#define DMAMUX_CSR_SOF2_Pos            (2U)\n#define DMAMUX_CSR_SOF2_Msk            (0x1UL << DMAMUX_CSR_SOF2_Pos)          /*!< 0x00000004 */\n#define DMAMUX_CSR_SOF2                DMAMUX_CSR_SOF2_Msk                     /*!< Channel 2 Synchronization overrun event flag */\n#define DMAMUX_CSR_SOF3_Pos            (3U)\n#define DMAMUX_CSR_SOF3_Msk            (0x1UL << DMAMUX_CSR_SOF3_Pos)          /*!< 0x00000008 */\n#define DMAMUX_CSR_SOF3                DMAMUX_CSR_SOF3_Msk                     /*!< Channel 3 Synchronization overrun event flag */\n#define DMAMUX_CSR_SOF4_Pos            (4U)\n#define DMAMUX_CSR_SOF4_Msk            (0x1UL << DMAMUX_CSR_SOF4_Pos)          /*!< 0x00000010 */\n#define DMAMUX_CSR_SOF4                DMAMUX_CSR_SOF4_Msk                     /*!< Channel 4 Synchronization overrun event flag */\n#define DMAMUX_CSR_SOF5_Pos            (5U)\n#define DMAMUX_CSR_SOF5_Msk            (0x1UL << DMAMUX_CSR_SOF5_Pos)          /*!< 0x00000020 */\n#define DMAMUX_CSR_SOF5                DMAMUX_CSR_SOF5_Msk                     /*!< Channel 5 Synchronization overrun event flag */\n#define DMAMUX_CSR_SOF6_Pos            (6U)\n#define DMAMUX_CSR_SOF6_Msk            (0x1UL << DMAMUX_CSR_SOF6_Pos)          /*!< 0x00000040 */\n#define DMAMUX_CSR_SOF6                DMAMUX_CSR_SOF6_Msk                     /*!< Channel 6 Synchronization overrun event flag */\n#define DMAMUX_CSR_SOF7_Pos            (7U)\n#define DMAMUX_CSR_SOF7_Msk            (0x1UL << DMAMUX_CSR_SOF7_Pos)          /*!< 0x00000080 */\n#define DMAMUX_CSR_SOF7                DMAMUX_CSR_SOF7_Msk                     /*!< Channel 7 Synchronization overrun event flag */\n#define DMAMUX_CSR_SOF8_Pos            (8U)\n#define DMAMUX_CSR_SOF8_Msk            (0x1UL << DMAMUX_CSR_SOF8_Pos)          /*!< 0x00000100 */\n#define DMAMUX_CSR_SOF8                DMAMUX_CSR_SOF8_Msk                     /*!< Channel 8 Synchronization overrun event flag */\n#define DMAMUX_CSR_SOF9_Pos            (9U)\n#define DMAMUX_CSR_SOF9_Msk            (0x1UL << DMAMUX_CSR_SOF9_Pos)          /*!< 0x00000200 */\n#define DMAMUX_CSR_SOF9                DMAMUX_CSR_SOF9_Msk                     /*!< Channel 9 Synchronization overrun event flag */\n#define DMAMUX_CSR_SOF10_Pos           (10U)\n#define DMAMUX_CSR_SOF10_Msk           (0x1UL << DMAMUX_CSR_SOF10_Pos)         /*!< 0x00000400 */\n#define DMAMUX_CSR_SOF10               DMAMUX_CSR_SOF10_Msk                    /*!< Channel 10 Synchronization overrun event flag */\n#define DMAMUX_CSR_SOF11_Pos           (11U)\n#define DMAMUX_CSR_SOF11_Msk           (0x1UL << DMAMUX_CSR_SOF11_Pos)         /*!< 0x00000800 */\n#define DMAMUX_CSR_SOF11               DMAMUX_CSR_SOF11_Msk                    /*!< Channel 11 Synchronization overrun event flag */\n#define DMAMUX_CSR_SOF12_Pos           (12U)\n#define DMAMUX_CSR_SOF12_Msk           (0x1UL << DMAMUX_CSR_SOF12_Pos)         /*!< 0x00001000 */\n#define DMAMUX_CSR_SOF12               DMAMUX_CSR_SOF12_Msk                    /*!< Channel 12 Synchronization overrun event flag */\n#define DMAMUX_CSR_SOF13_Pos           (13U)\n#define DMAMUX_CSR_SOF13_Msk           (0x1UL << DMAMUX_CSR_SOF13_Pos)         /*!< 0x00002000 */\n#define DMAMUX_CSR_SOF13               DMAMUX_CSR_SOF13_Msk                    /*!< Channel 13 Synchronization overrun event flag */\n#define DMAMUX_CSR_SOF14_Pos           (14U)\n#define DMAMUX_CSR_SOF14_Msk           (0x1UL << DMAMUX_CSR_SOF14_Pos)         /*!< 0x00004000 */\n#define DMAMUX_CSR_SOF14               DMAMUX_CSR_SOF14_Msk                    /*!< Channel 14 Synchronization overrun event flag */\n#define DMAMUX_CSR_SOF15_Pos           (15U)\n#define DMAMUX_CSR_SOF15_Msk           (0x1UL << DMAMUX_CSR_SOF15_Pos)         /*!< 0x00008000 */\n#define DMAMUX_CSR_SOF15               DMAMUX_CSR_SOF15_Msk                    /*!< Channel 15 Synchronization overrun event flag */\n\n/********************  Bits definition for DMAMUX_CFR register  **************/\n#define DMAMUX_CFR_CSOF0_Pos           (0U)\n#define DMAMUX_CFR_CSOF0_Msk           (0x1UL << DMAMUX_CFR_CSOF0_Pos)         /*!< 0x00000001 */\n#define DMAMUX_CFR_CSOF0               DMAMUX_CFR_CSOF0_Msk                    /*!< Channel 0 Clear synchronization overrun event flag */\n#define DMAMUX_CFR_CSOF1_Pos           (1U)\n#define DMAMUX_CFR_CSOF1_Msk           (0x1UL << DMAMUX_CFR_CSOF1_Pos)         /*!< 0x00000002 */\n#define DMAMUX_CFR_CSOF1               DMAMUX_CFR_CSOF1_Msk                    /*!< Channel 1 Clear synchronization overrun event flag */\n#define DMAMUX_CFR_CSOF2_Pos           (2U)\n#define DMAMUX_CFR_CSOF2_Msk           (0x1UL << DMAMUX_CFR_CSOF2_Pos)         /*!< 0x00000004 */\n#define DMAMUX_CFR_CSOF2               DMAMUX_CFR_CSOF2_Msk                    /*!< Channel 2 Clear synchronization overrun event flag */\n#define DMAMUX_CFR_CSOF3_Pos           (3U)\n#define DMAMUX_CFR_CSOF3_Msk           (0x1UL << DMAMUX_CFR_CSOF3_Pos)         /*!< 0x00000008 */\n#define DMAMUX_CFR_CSOF3               DMAMUX_CFR_CSOF3_Msk                    /*!< Channel 3 Clear synchronization overrun event flag */\n#define DMAMUX_CFR_CSOF4_Pos           (4U)\n#define DMAMUX_CFR_CSOF4_Msk           (0x1UL << DMAMUX_CFR_CSOF4_Pos)         /*!< 0x00000010 */\n#define DMAMUX_CFR_CSOF4               DMAMUX_CFR_CSOF4_Msk                    /*!< Channel 4 Clear synchronization overrun event flag */\n#define DMAMUX_CFR_CSOF5_Pos           (5U)\n#define DMAMUX_CFR_CSOF5_Msk           (0x1UL << DMAMUX_CFR_CSOF5_Pos)         /*!< 0x00000020 */\n#define DMAMUX_CFR_CSOF5               DMAMUX_CFR_CSOF5_Msk                    /*!< Channel 5 Clear synchronization overrun event flag */\n#define DMAMUX_CFR_CSOF6_Pos           (6U)\n#define DMAMUX_CFR_CSOF6_Msk           (0x1UL << DMAMUX_CFR_CSOF6_Pos)         /*!< 0x00000040 */\n#define DMAMUX_CFR_CSOF6               DMAMUX_CFR_CSOF6_Msk                    /*!< Channel 6 Clear synchronization overrun event flag */\n#define DMAMUX_CFR_CSOF7_Pos           (7U)\n#define DMAMUX_CFR_CSOF7_Msk           (0x1UL << DMAMUX_CFR_CSOF7_Pos)         /*!< 0x00000080 */\n#define DMAMUX_CFR_CSOF7               DMAMUX_CFR_CSOF7_Msk                    /*!< Channel 7 Clear synchronization overrun event flag */\n#define DMAMUX_CFR_CSOF8_Pos           (8U)\n#define DMAMUX_CFR_CSOF8_Msk           (0x1UL << DMAMUX_CFR_CSOF8_Pos)         /*!< 0x00000100 */\n#define DMAMUX_CFR_CSOF8               DMAMUX_CFR_CSOF8_Msk                    /*!< Channel 8 Clear synchronization overrun event flag */\n#define DMAMUX_CFR_CSOF9_Pos           (9U)\n#define DMAMUX_CFR_CSOF9_Msk           (0x1UL << DMAMUX_CFR_CSOF9_Pos)         /*!< 0x00000200 */\n#define DMAMUX_CFR_CSOF9               DMAMUX_CFR_CSOF9_Msk                    /*!< Channel 9 Clear synchronization overrun event flag */\n#define DMAMUX_CFR_CSOF10_Pos          (10U)\n#define DMAMUX_CFR_CSOF10_Msk          (0x1UL << DMAMUX_CFR_CSOF10_Pos)        /*!< 0x00000400 */\n#define DMAMUX_CFR_CSOF10              DMAMUX_CFR_CSOF10_Msk                   /*!< Channel 10 Clear synchronization overrun event flag */\n#define DMAMUX_CFR_CSOF11_Pos          (11U)\n#define DMAMUX_CFR_CSOF11_Msk          (0x1UL << DMAMUX_CFR_CSOF11_Pos)        /*!< 0x00000800 */\n#define DMAMUX_CFR_CSOF11              DMAMUX_CFR_CSOF11_Msk                   /*!< Channel 11 Clear synchronization overrun event flag */\n#define DMAMUX_CFR_CSOF12_Pos          (12U)\n#define DMAMUX_CFR_CSOF12_Msk          (0x1UL << DMAMUX_CFR_CSOF12_Pos)        /*!< 0x00001000 */\n#define DMAMUX_CFR_CSOF12              DMAMUX_CFR_CSOF12_Msk                   /*!< Channel 12 Clear synchronization overrun event flag */\n#define DMAMUX_CFR_CSOF13_Pos          (13U)\n#define DMAMUX_CFR_CSOF13_Msk          (0x1UL << DMAMUX_CFR_CSOF13_Pos)        /*!< 0x00002000 */\n#define DMAMUX_CFR_CSOF13              DMAMUX_CFR_CSOF13_Msk                   /*!< Channel 13 Clear synchronization overrun event flag */\n#define DMAMUX_CFR_CSOF14_Pos          (14U)\n#define DMAMUX_CFR_CSOF14_Msk          (0x1UL << DMAMUX_CFR_CSOF14_Pos)        /*!< 0x00004000 */\n#define DMAMUX_CFR_CSOF14              DMAMUX_CFR_CSOF14_Msk                   /*!< Channel 14 Clear synchronization overrun event flag */\n#define DMAMUX_CFR_CSOF15_Pos          (15U)\n#define DMAMUX_CFR_CSOF15_Msk          (0x1UL << DMAMUX_CFR_CSOF15_Pos)        /*!< 0x00008000 */\n#define DMAMUX_CFR_CSOF15              DMAMUX_CFR_CSOF15_Msk                   /*!< Channel 15 Clear synchronization overrun event flag */\n\n/********************  Bits definition for DMAMUX_RGxCR register  ************/\n#define DMAMUX_RGxCR_SIG_ID_Pos        (0U)\n#define DMAMUX_RGxCR_SIG_ID_Msk        (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos)     /*!< 0x0000001F */\n#define DMAMUX_RGxCR_SIG_ID            DMAMUX_RGxCR_SIG_ID_Msk                 /*!< Signal identification */\n#define DMAMUX_RGxCR_SIG_ID_0          (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000001 */\n#define DMAMUX_RGxCR_SIG_ID_1          (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000002 */\n#define DMAMUX_RGxCR_SIG_ID_2          (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000004 */\n#define DMAMUX_RGxCR_SIG_ID_3          (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000008 */\n#define DMAMUX_RGxCR_SIG_ID_4          (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000010 */\n#define DMAMUX_RGxCR_OIE_Pos           (8U)\n#define DMAMUX_RGxCR_OIE_Msk           (0x1UL << DMAMUX_RGxCR_OIE_Pos)         /*!< 0x00000100 */\n#define DMAMUX_RGxCR_OIE               DMAMUX_RGxCR_OIE_Msk                    /*!< Trigger overrun interrupt enable */\n#define DMAMUX_RGxCR_GE_Pos            (16U)\n#define DMAMUX_RGxCR_GE_Msk            (0x1UL << DMAMUX_RGxCR_GE_Pos)          /*!< 0x00010000 */\n#define DMAMUX_RGxCR_GE                DMAMUX_RGxCR_GE_Msk                     /*!< DMA request generator enable */\n#define DMAMUX_RGxCR_GPOL_Pos          (17U)\n#define DMAMUX_RGxCR_GPOL_Msk          (0x3UL << DMAMUX_RGxCR_GPOL_Pos)        /*!< 0x00060000 */\n#define DMAMUX_RGxCR_GPOL              DMAMUX_RGxCR_GPOL_Msk                   /*!< DMA request generator trigger polarity */\n#define DMAMUX_RGxCR_GPOL_0            (0x1UL << DMAMUX_RGxCR_GPOL_Pos)         /*!< 0x00020000 */\n#define DMAMUX_RGxCR_GPOL_1            (0x2UL << DMAMUX_RGxCR_GPOL_Pos)         /*!< 0x00040000 */\n#define DMAMUX_RGxCR_GNBREQ_Pos        (19U)\n#define DMAMUX_RGxCR_GNBREQ_Msk        (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos)     /*!< 0x00F80000 */\n#define DMAMUX_RGxCR_GNBREQ            DMAMUX_RGxCR_GNBREQ_Msk                 /*!< Number of DMA requests to be generated */\n#define DMAMUX_RGxCR_GNBREQ_0          (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00080000 */\n#define DMAMUX_RGxCR_GNBREQ_1          (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00100000 */\n#define DMAMUX_RGxCR_GNBREQ_2          (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00200000 */\n#define DMAMUX_RGxCR_GNBREQ_3          (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00400000 */\n#define DMAMUX_RGxCR_GNBREQ_4          (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00800000 */\n\n/********************  Bits definition for DMAMUX_RGSR register  **************/\n#define DMAMUX_RGSR_OF0_Pos            (0U)\n#define DMAMUX_RGSR_OF0_Msk            (0x1UL << DMAMUX_RGSR_OF0_Pos)          /*!< 0x00000001 */\n#define DMAMUX_RGSR_OF0                DMAMUX_RGSR_OF0_Msk                     /*!< Request generator channel 0 Trigger overrun event flag */\n#define DMAMUX_RGSR_OF1_Pos            (1U)\n#define DMAMUX_RGSR_OF1_Msk            (0x1UL << DMAMUX_RGSR_OF1_Pos)          /*!< 0x00000002 */\n#define DMAMUX_RGSR_OF1                DMAMUX_RGSR_OF1_Msk                     /*!< Request generator channel 1 Trigger overrun event flag */\n#define DMAMUX_RGSR_OF2_Pos            (2U)\n#define DMAMUX_RGSR_OF2_Msk            (0x1UL << DMAMUX_RGSR_OF2_Pos)          /*!< 0x00000004 */\n#define DMAMUX_RGSR_OF2                DMAMUX_RGSR_OF2_Msk                     /*!< Request generator channel 2 Trigger overrun event flag */\n#define DMAMUX_RGSR_OF3_Pos            (3U)\n#define DMAMUX_RGSR_OF3_Msk            (0x1UL << DMAMUX_RGSR_OF3_Pos)          /*!< 0x00000008 */\n#define DMAMUX_RGSR_OF3                DMAMUX_RGSR_OF3_Msk                     /*!< Request generator channel 3 Trigger overrun event flag */\n#define DMAMUX_RGSR_OF4_Pos            (4U)\n#define DMAMUX_RGSR_OF4_Msk            (0x1UL << DMAMUX_RGSR_OF4_Pos)          /*!< 0x00000010 */\n#define DMAMUX_RGSR_OF4                DMAMUX_RGSR_OF4_Msk                     /*!< Request generator channel 4 Trigger overrun event flag */\n#define DMAMUX_RGSR_OF5_Pos            (5U)\n#define DMAMUX_RGSR_OF5_Msk            (0x1UL << DMAMUX_RGSR_OF5_Pos)          /*!< 0x00000020 */\n#define DMAMUX_RGSR_OF5                DMAMUX_RGSR_OF5_Msk                     /*!< Request generator channel 5 Trigger overrun event flag */\n#define DMAMUX_RGSR_OF6_Pos            (6U)\n#define DMAMUX_RGSR_OF6_Msk            (0x1UL << DMAMUX_RGSR_OF6_Pos)          /*!< 0x00000040 */\n#define DMAMUX_RGSR_OF6                DMAMUX_RGSR_OF6_Msk                     /*!< Request generator channel 6 Trigger overrun event flag */\n#define DMAMUX_RGSR_OF7_Pos            (7U)\n#define DMAMUX_RGSR_OF7_Msk            (0x1UL << DMAMUX_RGSR_OF7_Pos)          /*!< 0x00000080 */\n#define DMAMUX_RGSR_OF7                DMAMUX_RGSR_OF7_Msk                     /*!< Request generator channel 7 Trigger overrun event flag */\n\n/********************  Bits definition for DMAMUX_RGCFR register  **************/\n#define DMAMUX_RGCFR_COF0_Pos          (0U)\n#define DMAMUX_RGCFR_COF0_Msk          (0x1UL << DMAMUX_RGCFR_COF0_Pos)        /*!< 0x00000001 */\n#define DMAMUX_RGCFR_COF0              DMAMUX_RGCFR_COF0_Msk                   /*!< Request generator channel 0 Clear trigger overrun event flag */\n#define DMAMUX_RGCFR_COF1_Pos          (1U)\n#define DMAMUX_RGCFR_COF1_Msk          (0x1UL << DMAMUX_RGCFR_COF1_Pos)        /*!< 0x00000002 */\n#define DMAMUX_RGCFR_COF1              DMAMUX_RGCFR_COF1_Msk                   /*!< Request generator channel 1 Clear trigger overrun event flag */\n#define DMAMUX_RGCFR_COF2_Pos          (2U)\n#define DMAMUX_RGCFR_COF2_Msk          (0x1UL << DMAMUX_RGCFR_COF2_Pos)        /*!< 0x00000004 */\n#define DMAMUX_RGCFR_COF2              DMAMUX_RGCFR_COF2_Msk                   /*!< Request generator channel 2 Clear trigger overrun event flag */\n#define DMAMUX_RGCFR_COF3_Pos          (3U)\n#define DMAMUX_RGCFR_COF3_Msk          (0x1UL << DMAMUX_RGCFR_COF3_Pos)        /*!< 0x00000008 */\n#define DMAMUX_RGCFR_COF3              DMAMUX_RGCFR_COF3_Msk                   /*!< Request generator channel 3 Clear trigger overrun event flag */\n#define DMAMUX_RGCFR_COF4_Pos          (4U)\n#define DMAMUX_RGCFR_COF4_Msk          (0x1UL << DMAMUX_RGCFR_COF4_Pos)        /*!< 0x00000010 */\n#define DMAMUX_RGCFR_COF4              DMAMUX_RGCFR_COF4_Msk                   /*!< Request generator channel 4 Clear trigger overrun event flag */\n#define DMAMUX_RGCFR_COF5_Pos          (5U)\n#define DMAMUX_RGCFR_COF5_Msk          (0x1UL << DMAMUX_RGCFR_COF5_Pos)        /*!< 0x00000020 */\n#define DMAMUX_RGCFR_COF5              DMAMUX_RGCFR_COF5_Msk                   /*!< Request generator channel 5 Clear trigger overrun event flag */\n#define DMAMUX_RGCFR_COF6_Pos          (6U)\n#define DMAMUX_RGCFR_COF6_Msk          (0x1UL << DMAMUX_RGCFR_COF6_Pos)        /*!< 0x00000040 */\n#define DMAMUX_RGCFR_COF6              DMAMUX_RGCFR_COF6_Msk                   /*!< Request generator channel 6 Clear trigger overrun event flag */\n#define DMAMUX_RGCFR_COF7_Pos          (7U)\n#define DMAMUX_RGCFR_COF7_Msk          (0x1UL << DMAMUX_RGCFR_COF7_Pos)        /*!< 0x00000080 */\n#define DMAMUX_RGCFR_COF7              DMAMUX_RGCFR_COF7_Msk                   /*!< Request generator channel 7 Clear trigger overrun event flag */\n\n/******************************************************************************/\n/*                                                                            */\n/*                         AHB Master DMA2D Controller (DMA2D)                */\n/*                                                                            */\n/******************************************************************************/\n\n/********************  Bit definition for DMA2D_CR register  ******************/\n\n#define DMA2D_CR_START_Pos         (0U)\n#define DMA2D_CR_START_Msk         (0x1UL << DMA2D_CR_START_Pos)               /*!< 0x00000001 */\n#define DMA2D_CR_START             DMA2D_CR_START_Msk                          /*!< Start transfer                          */\n#define DMA2D_CR_SUSP_Pos          (1U)\n#define DMA2D_CR_SUSP_Msk          (0x1UL << DMA2D_CR_SUSP_Pos)                /*!< 0x00000002 */\n#define DMA2D_CR_SUSP              DMA2D_CR_SUSP_Msk                           /*!< Suspend transfer                        */\n#define DMA2D_CR_ABORT_Pos         (2U)\n#define DMA2D_CR_ABORT_Msk         (0x1UL << DMA2D_CR_ABORT_Pos)               /*!< 0x00000004 */\n#define DMA2D_CR_ABORT             DMA2D_CR_ABORT_Msk                          /*!< Abort transfer                          */\n#define DMA2D_CR_LOM_Pos           (6U)\n#define DMA2D_CR_LOM_Msk           (0x1UL << DMA2D_CR_LOM_Pos)                 /*!< 0x00000040 */\n#define DMA2D_CR_LOM               DMA2D_CR_LOM_Msk                            /*!< Line Offset Mode                         */\n#define DMA2D_CR_TEIE_Pos          (8U)\n#define DMA2D_CR_TEIE_Msk          (0x1UL << DMA2D_CR_TEIE_Pos)                /*!< 0x00000100 */\n#define DMA2D_CR_TEIE              DMA2D_CR_TEIE_Msk                           /*!< Transfer Error Interrupt Enable         */\n#define DMA2D_CR_TCIE_Pos          (9U)\n#define DMA2D_CR_TCIE_Msk          (0x1UL << DMA2D_CR_TCIE_Pos)                /*!< 0x00000200 */\n#define DMA2D_CR_TCIE              DMA2D_CR_TCIE_Msk                           /*!< Transfer Complete Interrupt Enable      */\n#define DMA2D_CR_TWIE_Pos          (10U)\n#define DMA2D_CR_TWIE_Msk          (0x1UL << DMA2D_CR_TWIE_Pos)                /*!< 0x00000400 */\n#define DMA2D_CR_TWIE              DMA2D_CR_TWIE_Msk                           /*!< Transfer Watermark Interrupt Enable     */\n#define DMA2D_CR_CAEIE_Pos         (11U)\n#define DMA2D_CR_CAEIE_Msk         (0x1UL << DMA2D_CR_CAEIE_Pos)               /*!< 0x00000800 */\n#define DMA2D_CR_CAEIE             DMA2D_CR_CAEIE_Msk                          /*!< CLUT Access Error Interrupt Enable      */\n#define DMA2D_CR_CTCIE_Pos         (12U)\n#define DMA2D_CR_CTCIE_Msk         (0x1UL << DMA2D_CR_CTCIE_Pos)               /*!< 0x00001000 */\n#define DMA2D_CR_CTCIE             DMA2D_CR_CTCIE_Msk                          /*!< CLUT Transfer Complete Interrupt Enable */\n#define DMA2D_CR_CEIE_Pos          (13U)\n#define DMA2D_CR_CEIE_Msk          (0x1UL << DMA2D_CR_CEIE_Pos)                /*!< 0x00002000 */\n#define DMA2D_CR_CEIE              DMA2D_CR_CEIE_Msk                           /*!< Configuration Error Interrupt Enable    */\n#define DMA2D_CR_MODE_Pos          (16U)\n#define DMA2D_CR_MODE_Msk          (0x7UL << DMA2D_CR_MODE_Pos)                /*!< 0x00070000 */\n#define DMA2D_CR_MODE              DMA2D_CR_MODE_Msk                           /*!< DMA2D Mode[2:0]                         */\n#define DMA2D_CR_MODE_0            (0x1UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00010000 */\n#define DMA2D_CR_MODE_1            (0x2UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00020000 */\n#define DMA2D_CR_MODE_2            (0x4UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00040000 */\n\n/********************  Bit definition for DMA2D_ISR register  *****************/\n\n#define DMA2D_ISR_TEIF_Pos         (0U)\n#define DMA2D_ISR_TEIF_Msk         (0x1UL << DMA2D_ISR_TEIF_Pos)               /*!< 0x00000001 */\n#define DMA2D_ISR_TEIF             DMA2D_ISR_TEIF_Msk                          /*!< Transfer Error Interrupt Flag         */\n#define DMA2D_ISR_TCIF_Pos         (1U)\n#define DMA2D_ISR_TCIF_Msk         (0x1UL << DMA2D_ISR_TCIF_Pos)               /*!< 0x00000002 */\n#define DMA2D_ISR_TCIF             DMA2D_ISR_TCIF_Msk                          /*!< Transfer Complete Interrupt Flag      */\n#define DMA2D_ISR_TWIF_Pos         (2U)\n#define DMA2D_ISR_TWIF_Msk         (0x1UL << DMA2D_ISR_TWIF_Pos)               /*!< 0x00000004 */\n#define DMA2D_ISR_TWIF             DMA2D_ISR_TWIF_Msk                          /*!< Transfer Watermark Interrupt Flag     */\n#define DMA2D_ISR_CAEIF_Pos        (3U)\n#define DMA2D_ISR_CAEIF_Msk        (0x1UL << DMA2D_ISR_CAEIF_Pos)              /*!< 0x00000008 */\n#define DMA2D_ISR_CAEIF            DMA2D_ISR_CAEIF_Msk                         /*!< CLUT Access Error Interrupt Flag      */\n#define DMA2D_ISR_CTCIF_Pos        (4U)\n#define DMA2D_ISR_CTCIF_Msk        (0x1UL << DMA2D_ISR_CTCIF_Pos)              /*!< 0x00000010 */\n#define DMA2D_ISR_CTCIF            DMA2D_ISR_CTCIF_Msk                         /*!< CLUT Transfer Complete Interrupt Flag */\n#define DMA2D_ISR_CEIF_Pos         (5U)\n#define DMA2D_ISR_CEIF_Msk         (0x1UL << DMA2D_ISR_CEIF_Pos)               /*!< 0x00000020 */\n#define DMA2D_ISR_CEIF             DMA2D_ISR_CEIF_Msk                          /*!< Configuration Error Interrupt Flag    */\n\n/********************  Bit definition for DMA2D_IFCR register  ****************/\n\n#define DMA2D_IFCR_CTEIF_Pos       (0U)\n#define DMA2D_IFCR_CTEIF_Msk       (0x1UL << DMA2D_IFCR_CTEIF_Pos)             /*!< 0x00000001 */\n#define DMA2D_IFCR_CTEIF           DMA2D_IFCR_CTEIF_Msk                        /*!< Clears Transfer Error Interrupt Flag         */\n#define DMA2D_IFCR_CTCIF_Pos       (1U)\n#define DMA2D_IFCR_CTCIF_Msk       (0x1UL << DMA2D_IFCR_CTCIF_Pos)             /*!< 0x00000002 */\n#define DMA2D_IFCR_CTCIF           DMA2D_IFCR_CTCIF_Msk                        /*!< Clears Transfer Complete Interrupt Flag      */\n#define DMA2D_IFCR_CTWIF_Pos       (2U)\n#define DMA2D_IFCR_CTWIF_Msk       (0x1UL << DMA2D_IFCR_CTWIF_Pos)             /*!< 0x00000004 */\n#define DMA2D_IFCR_CTWIF           DMA2D_IFCR_CTWIF_Msk                        /*!< Clears Transfer Watermark Interrupt Flag     */\n#define DMA2D_IFCR_CAECIF_Pos      (3U)\n#define DMA2D_IFCR_CAECIF_Msk      (0x1UL << DMA2D_IFCR_CAECIF_Pos)            /*!< 0x00000008 */\n#define DMA2D_IFCR_CAECIF          DMA2D_IFCR_CAECIF_Msk                       /*!< Clears CLUT Access Error Interrupt Flag      */\n#define DMA2D_IFCR_CCTCIF_Pos      (4U)\n#define DMA2D_IFCR_CCTCIF_Msk      (0x1UL << DMA2D_IFCR_CCTCIF_Pos)            /*!< 0x00000010 */\n#define DMA2D_IFCR_CCTCIF          DMA2D_IFCR_CCTCIF_Msk                       /*!< Clears CLUT Transfer Complete Interrupt Flag */\n#define DMA2D_IFCR_CCEIF_Pos       (5U)\n#define DMA2D_IFCR_CCEIF_Msk       (0x1UL << DMA2D_IFCR_CCEIF_Pos)             /*!< 0x00000020 */\n#define DMA2D_IFCR_CCEIF           DMA2D_IFCR_CCEIF_Msk                        /*!< Clears Configuration Error Interrupt Flag    */\n\n/********************  Bit definition for DMA2D_FGMAR register  ***************/\n\n#define DMA2D_FGMAR_MA_Pos         (0U)\n#define DMA2D_FGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos)        /*!< 0xFFFFFFFF */\n#define DMA2D_FGMAR_MA             DMA2D_FGMAR_MA_Msk                          /*!< Foreground Memory Address */\n\n/********************  Bit definition for DMA2D_FGOR register  ****************/\n\n#define DMA2D_FGOR_LO_Pos          (0U)\n#define DMA2D_FGOR_LO_Msk          (0xFFFFUL << DMA2D_FGOR_LO_Pos)             /*!< 0x0000FFFF */\n#define DMA2D_FGOR_LO              DMA2D_FGOR_LO_Msk                           /*!< Line Offset */\n\n/********************  Bit definition for DMA2D_BGMAR register  ***************/\n\n#define DMA2D_BGMAR_MA_Pos         (0U)\n#define DMA2D_BGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos)        /*!< 0xFFFFFFFF */\n#define DMA2D_BGMAR_MA             DMA2D_BGMAR_MA_Msk                          /*!< Background Memory Address */\n\n/********************  Bit definition for DMA2D_BGOR register  ****************/\n\n#define DMA2D_BGOR_LO_Pos          (0U)\n#define DMA2D_BGOR_LO_Msk          (0xFFFFUL << DMA2D_BGOR_LO_Pos)             /*!< 0x0000FFFF */\n#define DMA2D_BGOR_LO              DMA2D_BGOR_LO_Msk                           /*!< Line Offset */\n\n/********************  Bit definition for DMA2D_FGPFCCR register  *************/\n\n#define DMA2D_FGPFCCR_CM_Pos       (0U)\n#define DMA2D_FGPFCCR_CM_Msk       (0xFUL << DMA2D_FGPFCCR_CM_Pos)             /*!< 0x0000000F */\n#define DMA2D_FGPFCCR_CM           DMA2D_FGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */\n#define DMA2D_FGPFCCR_CM_0         (0x1UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000001 */\n#define DMA2D_FGPFCCR_CM_1         (0x2UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000002 */\n#define DMA2D_FGPFCCR_CM_2         (0x4UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000004 */\n#define DMA2D_FGPFCCR_CM_3         (0x8UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000008 */\n#define DMA2D_FGPFCCR_CCM_Pos      (4U)\n#define DMA2D_FGPFCCR_CCM_Msk      (0x1UL << DMA2D_FGPFCCR_CCM_Pos)            /*!< 0x00000010 */\n#define DMA2D_FGPFCCR_CCM          DMA2D_FGPFCCR_CCM_Msk                       /*!< CLUT Color mode */\n#define DMA2D_FGPFCCR_START_Pos    (5U)\n#define DMA2D_FGPFCCR_START_Msk    (0x1UL << DMA2D_FGPFCCR_START_Pos)          /*!< 0x00000020 */\n#define DMA2D_FGPFCCR_START        DMA2D_FGPFCCR_START_Msk                     /*!< Start */\n#define DMA2D_FGPFCCR_CS_Pos       (8U)\n#define DMA2D_FGPFCCR_CS_Msk       (0xFFUL << DMA2D_FGPFCCR_CS_Pos)            /*!< 0x0000FF00 */\n#define DMA2D_FGPFCCR_CS           DMA2D_FGPFCCR_CS_Msk                        /*!< CLUT size */\n#define DMA2D_FGPFCCR_AM_Pos       (16U)\n#define DMA2D_FGPFCCR_AM_Msk       (0x3UL << DMA2D_FGPFCCR_AM_Pos)             /*!< 0x00030000 */\n#define DMA2D_FGPFCCR_AM           DMA2D_FGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */\n#define DMA2D_FGPFCCR_AM_0         (0x1UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00010000 */\n#define DMA2D_FGPFCCR_AM_1         (0x2UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00020000 */\n#define DMA2D_FGPFCCR_CSS_Pos      (18U)\n#define DMA2D_FGPFCCR_CSS_Msk      (0x3UL << DMA2D_FGPFCCR_CSS_Pos)            /*!< 0x000C0000 */\n#define DMA2D_FGPFCCR_CSS          DMA2D_FGPFCCR_CSS_Msk                       /* !< Chroma Sub-Sampling */\n#define DMA2D_FGPFCCR_CSS_0        (0x1UL << DMA2D_FGPFCCR_CSS_Pos)             /*!< 0x00040000 */\n#define DMA2D_FGPFCCR_CSS_1        (0x2UL << DMA2D_FGPFCCR_CSS_Pos)             /*!< 0x00080000 */\n#define DMA2D_FGPFCCR_AI_Pos       (20U)\n#define DMA2D_FGPFCCR_AI_Msk       (0x1UL << DMA2D_FGPFCCR_AI_Pos)             /*!< 0x00100000 */\n#define DMA2D_FGPFCCR_AI           DMA2D_FGPFCCR_AI_Msk                        /*!< Foreground Input Alpha Inverted */\n#define DMA2D_FGPFCCR_RBS_Pos      (21U)\n#define DMA2D_FGPFCCR_RBS_Msk      (0x1UL << DMA2D_FGPFCCR_RBS_Pos)            /*!< 0x00200000 */\n#define DMA2D_FGPFCCR_RBS          DMA2D_FGPFCCR_RBS_Msk                       /*!< Foreground Input Red Blue Swap */\n#define DMA2D_FGPFCCR_ALPHA_Pos    (24U)\n#define DMA2D_FGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos)         /*!< 0xFF000000 */\n#define DMA2D_FGPFCCR_ALPHA        DMA2D_FGPFCCR_ALPHA_Msk                     /*!< Alpha value */\n\n/********************  Bit definition for DMA2D_FGCOLR register  **************/\n\n#define DMA2D_FGCOLR_BLUE_Pos      (0U)\n#define DMA2D_FGCOLR_BLUE_Msk      (0xFFUL << DMA2D_FGCOLR_BLUE_Pos)           /*!< 0x000000FF */\n#define DMA2D_FGCOLR_BLUE          DMA2D_FGCOLR_BLUE_Msk                       /*!< Foreground Blue Value */\n#define DMA2D_FGCOLR_GREEN_Pos     (8U)\n#define DMA2D_FGCOLR_GREEN_Msk     (0xFFUL << DMA2D_FGCOLR_GREEN_Pos)          /*!< 0x0000FF00 */\n#define DMA2D_FGCOLR_GREEN         DMA2D_FGCOLR_GREEN_Msk                      /*!< Foreground Green Value */\n#define DMA2D_FGCOLR_RED_Pos       (16U)\n#define DMA2D_FGCOLR_RED_Msk       (0xFFUL << DMA2D_FGCOLR_RED_Pos)            /*!< 0x00FF0000 */\n#define DMA2D_FGCOLR_RED           DMA2D_FGCOLR_RED_Msk                        /*!< Foreground Red Value */\n\n/********************  Bit definition for DMA2D_BGPFCCR register  *************/\n\n#define DMA2D_BGPFCCR_CM_Pos       (0U)\n#define DMA2D_BGPFCCR_CM_Msk       (0xFUL << DMA2D_BGPFCCR_CM_Pos)             /*!< 0x0000000F */\n#define DMA2D_BGPFCCR_CM           DMA2D_BGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */\n#define DMA2D_BGPFCCR_CM_0         (0x1UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000001 */\n#define DMA2D_BGPFCCR_CM_1         (0x2UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000002 */\n#define DMA2D_BGPFCCR_CM_2         (0x4UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000004 */\n#define DMA2D_BGPFCCR_CM_3         (0x8UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000008 */\n#define DMA2D_BGPFCCR_CCM_Pos      (4U)\n#define DMA2D_BGPFCCR_CCM_Msk      (0x1UL << DMA2D_BGPFCCR_CCM_Pos)            /*!< 0x00000010 */\n#define DMA2D_BGPFCCR_CCM          DMA2D_BGPFCCR_CCM_Msk                       /*!< CLUT Color mode */\n#define DMA2D_BGPFCCR_START_Pos    (5U)\n#define DMA2D_BGPFCCR_START_Msk    (0x1UL << DMA2D_BGPFCCR_START_Pos)          /*!< 0x00000020 */\n#define DMA2D_BGPFCCR_START        DMA2D_BGPFCCR_START_Msk                     /*!< Start */\n#define DMA2D_BGPFCCR_CS_Pos       (8U)\n#define DMA2D_BGPFCCR_CS_Msk       (0xFFUL << DMA2D_BGPFCCR_CS_Pos)            /*!< 0x0000FF00 */\n#define DMA2D_BGPFCCR_CS           DMA2D_BGPFCCR_CS_Msk                        /*!< CLUT size */\n#define DMA2D_BGPFCCR_AM_Pos       (16U)\n#define DMA2D_BGPFCCR_AM_Msk       (0x3UL << DMA2D_BGPFCCR_AM_Pos)             /*!< 0x00030000 */\n#define DMA2D_BGPFCCR_AM           DMA2D_BGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */\n#define DMA2D_BGPFCCR_AM_0         (0x1UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00010000 */\n#define DMA2D_BGPFCCR_AM_1         (0x2UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00020000 */\n#define DMA2D_BGPFCCR_AI_Pos       (20U)\n#define DMA2D_BGPFCCR_AI_Msk       (0x1UL << DMA2D_BGPFCCR_AI_Pos)             /*!< 0x00100000 */\n#define DMA2D_BGPFCCR_AI           DMA2D_BGPFCCR_AI_Msk                        /*!< background Input Alpha Inverted */\n#define DMA2D_BGPFCCR_RBS_Pos      (21U)\n#define DMA2D_BGPFCCR_RBS_Msk      (0x1UL << DMA2D_BGPFCCR_RBS_Pos)            /*!< 0x00200000 */\n#define DMA2D_BGPFCCR_RBS          DMA2D_BGPFCCR_RBS_Msk                       /*!< Background Input Red Blue Swap */\n#define DMA2D_BGPFCCR_ALPHA_Pos    (24U)\n#define DMA2D_BGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos)         /*!< 0xFF000000 */\n#define DMA2D_BGPFCCR_ALPHA        DMA2D_BGPFCCR_ALPHA_Msk                     /*!< background Input Alpha value */\n\n/********************  Bit definition for DMA2D_BGCOLR register  **************/\n\n#define DMA2D_BGCOLR_BLUE_Pos      (0U)\n#define DMA2D_BGCOLR_BLUE_Msk      (0xFFUL << DMA2D_BGCOLR_BLUE_Pos)           /*!< 0x000000FF */\n#define DMA2D_BGCOLR_BLUE          DMA2D_BGCOLR_BLUE_Msk                       /*!< Background Blue Value */\n#define DMA2D_BGCOLR_GREEN_Pos     (8U)\n#define DMA2D_BGCOLR_GREEN_Msk     (0xFFUL << DMA2D_BGCOLR_GREEN_Pos)          /*!< 0x0000FF00 */\n#define DMA2D_BGCOLR_GREEN         DMA2D_BGCOLR_GREEN_Msk                      /*!< Background Green Value */\n#define DMA2D_BGCOLR_RED_Pos       (16U)\n#define DMA2D_BGCOLR_RED_Msk       (0xFFUL << DMA2D_BGCOLR_RED_Pos)            /*!< 0x00FF0000 */\n#define DMA2D_BGCOLR_RED           DMA2D_BGCOLR_RED_Msk                        /*!< Background Red Value */\n\n/********************  Bit definition for DMA2D_FGCMAR register  **************/\n\n#define DMA2D_FGCMAR_MA_Pos        (0U)\n#define DMA2D_FGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos)       /*!< 0xFFFFFFFF */\n#define DMA2D_FGCMAR_MA            DMA2D_FGCMAR_MA_Msk                         /*!< Foreground CLUT Memory Address */\n\n/********************  Bit definition for DMA2D_BGCMAR register  **************/\n\n#define DMA2D_BGCMAR_MA_Pos        (0U)\n#define DMA2D_BGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos)       /*!< 0xFFFFFFFF */\n#define DMA2D_BGCMAR_MA            DMA2D_BGCMAR_MA_Msk                         /*!< Background CLUT Memory Address */\n\n/********************  Bit definition for DMA2D_OPFCCR register  **************/\n\n#define DMA2D_OPFCCR_CM_Pos        (0U)\n#define DMA2D_OPFCCR_CM_Msk        (0x7UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000007 */\n#define DMA2D_OPFCCR_CM            DMA2D_OPFCCR_CM_Msk                         /*!< Output Color mode CM[2:0] */\n#define DMA2D_OPFCCR_CM_0          (0x1UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000001 */\n#define DMA2D_OPFCCR_CM_1          (0x2UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000002 */\n#define DMA2D_OPFCCR_CM_2          (0x4UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000004 */\n#define DMA2D_OPFCCR_SB_Pos        (8U)\n#define DMA2D_OPFCCR_SB_Msk        (0x1UL << DMA2D_OPFCCR_SB_Pos)              /*!< 0x00000100 */\n#define DMA2D_OPFCCR_SB            DMA2D_OPFCCR_SB_Msk                         /*!< Swap Bytes */\n#define DMA2D_OPFCCR_AI_Pos        (20U)\n#define DMA2D_OPFCCR_AI_Msk        (0x1UL << DMA2D_OPFCCR_AI_Pos)              /*!< 0x00100000 */\n#define DMA2D_OPFCCR_AI            DMA2D_OPFCCR_AI_Msk                         /*!< Output Alpha Inverted */\n#define DMA2D_OPFCCR_RBS_Pos       (21U)\n#define DMA2D_OPFCCR_RBS_Msk       (0x1UL << DMA2D_OPFCCR_RBS_Pos)             /*!< 0x00200000 */\n#define DMA2D_OPFCCR_RBS           DMA2D_OPFCCR_RBS_Msk                        /*!< Output Red Blue Swap */\n\n/********************  Bit definition for DMA2D_OCOLR register  ***************/\n\n/*!<Mode_ARGB8888/RGB888 */\n\n#define DMA2D_OCOLR_BLUE_1_Pos     (0U)\n#define DMA2D_OCOLR_BLUE_1_Msk     (0xFFUL <<DMA2D_OCOLR_BLUE_1_Pos)            /*0x000000FFU*/\n#define DMA2D_OCOLR_BLUE_1         DMA2D_OCOLR_BLUE_1_Msk                      /*!< Output BLUE Value */\n#define DMA2D_OCOLR_GREEN_1_Pos    (8U)\n#define DMA2D_OCOLR_GREEN_1_Msk    (0xFFUL<<DMA2D_OCOLR_GREEN_1_Pos)            /*0x0000FF00U)*/\n#define DMA2D_OCOLR_GREEN_1        DMA2D_OCOLR_GREEN_1_Msk                     /*!< Output GREEN Value  */\n#define DMA2D_OCOLR_RED_1_Pos      (16U)\n#define DMA2D_OCOLR_RED_1_Msk      (0xFFUL << DMA2D_OCOLR_RED_1_Pos)            /*0x00FF0000U */\n#define DMA2D_OCOLR_RED_1          DMA2D_OCOLR_RED_1_Msk                       /*!< Output Red Value */\n#define DMA2D_OCOLR_ALPHA_1_Pos    (24U)\n#define DMA2D_OCOLR_ALPHA_1_Msk    (0xFFUL << DMA2D_OCOLR_ALPHA_1_Pos)          /*0xFF000000U*/\n#define DMA2D_OCOLR_ALPHA_1        DMA2D_OCOLR_ALPHA_1_Msk                     /*!< Output Alpha Channel Value */\n\n/*!<Mode_RGB565 */\n#define DMA2D_OCOLR_BLUE_2_Pos     (0U)\n#define DMA2D_OCOLR_BLUE_2_Msk     (0x1FUL <<DMA2D_OCOLR_BLUE_2_Pos)            /*0x0000001FU*/\n#define DMA2D_OCOLR_BLUE_2         DMA2D_OCOLR_BLUE_2_Msk                      /*!< Output BLUE Value */\n#define DMA2D_OCOLR_GREEN_2_Pos    (5U)\n#define DMA2D_OCOLR_GREEN_2_Msk    (0x7EUL << DMA2D_OCOLR_GREEN_2_Pos)          /* 0x000007E0U */\n#define DMA2D_OCOLR_GREEN_2        DMA2D_OCOLR_GREEN_2_Msk                     /*!< Output GREEN Value  */\n#define DMA2D_OCOLR_RED_2_Pos      (11U)\n#define DMA2D_OCOLR_RED_2_Msk      (0xF8UL<<DMA2D_OCOLR_RED_2_Pos)              /*0x0000F800U*/\n#define DMA2D_OCOLR_RED_2          DMA2D_OCOLR_RED_2_Msk                       /*!< Output Red Value */\n\n/*!<Mode_ARGB1555 */\n#define DMA2D_OCOLR_BLUE_3_Pos     (0U)\n#define DMA2D_OCOLR_BLUE_3_Msk     (0x1FUL << DMA2D_OCOLR_BLUE_3_Pos)           /*0x0000001FU*/\n#define DMA2D_OCOLR_BLUE_3         DMA2D_OCOLR_BLUE_3_Msk                      /*!< Output BLUE Value */\n#define DMA2D_OCOLR_GREEN_3_Pos    (5U)\n#define DMA2D_OCOLR_GREEN_3_Msk    (0x3EUL << DMA2D_OCOLR_GREEN_3_Pos)          /*0x000003E0U*/\n#define DMA2D_OCOLR_GREEN_3        DMA2D_OCOLR_GREEN_3_Msk                     /*!< Output GREEN Value  */\n#define DMA2D_OCOLR_RED_3_Pos      (10U)\n#define DMA2D_OCOLR_RED_3_Msk      (0x7CUL << DMA2D_OCOLR_RED_3_Pos)            /* 0x00007C00U*/\n#define DMA2D_OCOLR_RED_3          DMA2D_OCOLR_RED_3_Msk                       /*!< Output Red Value */\n#define DMA2D_OCOLR_ALPHA_3_Pos    (15U)\n#define DMA2D_OCOLR_ALPHA_3_Msk    (0x1UL << DMA2D_OCOLR_ALPHA_3_Pos)           /*0x00008000U*/\n#define DMA2D_OCOLR_ALPHA_3        DMA2D_OCOLR_ALPHA_3_Msk                     /*!< Output Alpha Channel Value */\n\n/*!<Mode_ARGB4444 */\n#define DMA2D_OCOLR_BLUE_4_Pos     (0U)\n#define DMA2D_OCOLR_BLUE_4_Msk     (0xFUL << DMA2D_OCOLR_BLUE_4_Pos)            /*0x0000000FU*/\n#define DMA2D_OCOLR_BLUE_4         DMA2D_OCOLR_BLUE_4_Msk                      /*!< Output BLUE Value */\n#define DMA2D_OCOLR_GREEN_4_Pos    (4U)\n#define DMA2D_OCOLR_GREEN_4_Msk    (0xFUL << DMA2D_OCOLR_GREEN_4_Pos)           /*0x000000F0U*/\n#define DMA2D_OCOLR_GREEN_4        DMA2D_OCOLR_GREEN_4_Msk                     /*!< Output GREEN Value  */\n#define DMA2D_OCOLR_RED_4_Pos      (8U)\n#define DMA2D_OCOLR_RED_4_Msk      (0xFUL << DMA2D_OCOLR_RED_4_Pos)             /*0x00000F00U*/\n#define DMA2D_OCOLR_RED_4          DMA2D_OCOLR_RED_4_Msk                       /*!< Output Red Value */\n#define DMA2D_OCOLR_ALPHA_4_Pos    (12U)\n#define DMA2D_OCOLR_ALPHA_4_Msk    (0xFUL << DMA2D_OCOLR_ALPHA_4_Pos)            /*0x0000F000U*/\n#define DMA2D_OCOLR_ALPHA_4        DMA2D_OCOLR_ALPHA_4_Msk                     /*!< Output Alpha Channel Value */\n\n/********************  Bit definition for DMA2D_OMAR register  ****************/\n\n#define DMA2D_OMAR_MA_Pos          (0U)\n#define DMA2D_OMAR_MA_Msk          (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos)         /*!< 0xFFFFFFFF */\n#define DMA2D_OMAR_MA              DMA2D_OMAR_MA_Msk                           /*!< Output Memory Address */\n\n/********************  Bit definition for DMA2D_OOR register  *****************/\n\n#define DMA2D_OOR_LO_Pos           (0U)\n#define DMA2D_OOR_LO_Msk           (0xFFFFUL << DMA2D_OOR_LO_Pos)              /*!< 0x0000FFFF */\n#define DMA2D_OOR_LO               DMA2D_OOR_LO_Msk                            /*!< Output Line Offset */\n\n/********************  Bit definition for DMA2D_NLR register  *****************/\n\n#define DMA2D_NLR_NL_Pos           (0U)\n#define DMA2D_NLR_NL_Msk           (0xFFFFUL << DMA2D_NLR_NL_Pos)              /*!< 0x0000FFFF */\n#define DMA2D_NLR_NL               DMA2D_NLR_NL_Msk                            /*!< Number of Lines */\n#define DMA2D_NLR_PL_Pos           (16U)\n#define DMA2D_NLR_PL_Msk           (0x3FFFUL << DMA2D_NLR_PL_Pos)              /*!< 0x3FFF0000 */\n#define DMA2D_NLR_PL               DMA2D_NLR_PL_Msk                            /*!< Pixel per Lines */\n\n/********************  Bit definition for DMA2D_LWR register  *****************/\n\n#define DMA2D_LWR_LW_Pos           (0U)\n#define DMA2D_LWR_LW_Msk           (0xFFFFUL << DMA2D_LWR_LW_Pos)              /*!< 0x0000FFFF */\n#define DMA2D_LWR_LW               DMA2D_LWR_LW_Msk                            /*!< Line Watermark */\n\n/********************  Bit definition for DMA2D_AMTCR register  ***************/\n\n#define DMA2D_AMTCR_EN_Pos         (0U)\n#define DMA2D_AMTCR_EN_Msk         (0x1UL << DMA2D_AMTCR_EN_Pos)               /*!< 0x00000001 */\n#define DMA2D_AMTCR_EN             DMA2D_AMTCR_EN_Msk                          /*!< Enable */\n#define DMA2D_AMTCR_DT_Pos         (8U)\n#define DMA2D_AMTCR_DT_Msk         (0xFFUL << DMA2D_AMTCR_DT_Pos)              /*!< 0x0000FF00 */\n#define DMA2D_AMTCR_DT             DMA2D_AMTCR_DT_Msk                          /*!< Dead Time */\n\n\n/********************  Bit definition for DMA2D_FGCLUT register  **************/\n\n/********************  Bit definition for DMA2D_BGCLUT register  **************/\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                    External Interrupt/Event Controller                     */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bit definition for EXTI_RTSR1 register  *******************/\n#define EXTI_RTSR1_TR_Pos          (0U)\n#define EXTI_RTSR1_TR_Msk          (0x3FFFFFUL << EXTI_RTSR1_TR_Pos)           /*!< 0x003FFFFF */\n#define EXTI_RTSR1_TR              EXTI_RTSR1_TR_Msk                           /*!< Rising trigger event configuration bit */\n#define EXTI_RTSR1_TR0_Pos         (0U)\n#define EXTI_RTSR1_TR0_Msk         (0x1UL << EXTI_RTSR1_TR0_Pos)               /*!< 0x00000001 */\n#define EXTI_RTSR1_TR0             EXTI_RTSR1_TR0_Msk                          /*!< Rising trigger event configuration bit of line 0 */\n#define EXTI_RTSR1_TR1_Pos         (1U)\n#define EXTI_RTSR1_TR1_Msk         (0x1UL << EXTI_RTSR1_TR1_Pos)               /*!< 0x00000002 */\n#define EXTI_RTSR1_TR1             EXTI_RTSR1_TR1_Msk                          /*!< Rising trigger event configuration bit of line 1 */\n#define EXTI_RTSR1_TR2_Pos         (2U)\n#define EXTI_RTSR1_TR2_Msk         (0x1UL << EXTI_RTSR1_TR2_Pos)               /*!< 0x00000004 */\n#define EXTI_RTSR1_TR2             EXTI_RTSR1_TR2_Msk                          /*!< Rising trigger event configuration bit of line 2 */\n#define EXTI_RTSR1_TR3_Pos         (3U)\n#define EXTI_RTSR1_TR3_Msk         (0x1UL << EXTI_RTSR1_TR3_Pos)               /*!< 0x00000008 */\n#define EXTI_RTSR1_TR3             EXTI_RTSR1_TR3_Msk                          /*!< Rising trigger event configuration bit of line 3 */\n#define EXTI_RTSR1_TR4_Pos         (4U)\n#define EXTI_RTSR1_TR4_Msk         (0x1UL << EXTI_RTSR1_TR4_Pos)               /*!< 0x00000010 */\n#define EXTI_RTSR1_TR4             EXTI_RTSR1_TR4_Msk                          /*!< Rising trigger event configuration bit of line 4 */\n#define EXTI_RTSR1_TR5_Pos         (5U)\n#define EXTI_RTSR1_TR5_Msk         (0x1UL << EXTI_RTSR1_TR5_Pos)               /*!< 0x00000020 */\n#define EXTI_RTSR1_TR5             EXTI_RTSR1_TR5_Msk                          /*!< Rising trigger event configuration bit of line 5 */\n#define EXTI_RTSR1_TR6_Pos         (6U)\n#define EXTI_RTSR1_TR6_Msk         (0x1UL << EXTI_RTSR1_TR6_Pos)               /*!< 0x00000040 */\n#define EXTI_RTSR1_TR6             EXTI_RTSR1_TR6_Msk                          /*!< Rising trigger event configuration bit of line 6 */\n#define EXTI_RTSR1_TR7_Pos         (7U)\n#define EXTI_RTSR1_TR7_Msk         (0x1UL << EXTI_RTSR1_TR7_Pos)               /*!< 0x00000080 */\n#define EXTI_RTSR1_TR7             EXTI_RTSR1_TR7_Msk                          /*!< Rising trigger event configuration bit of line 7 */\n#define EXTI_RTSR1_TR8_Pos         (8U)\n#define EXTI_RTSR1_TR8_Msk         (0x1UL << EXTI_RTSR1_TR8_Pos)               /*!< 0x00000100 */\n#define EXTI_RTSR1_TR8             EXTI_RTSR1_TR8_Msk                          /*!< Rising trigger event configuration bit of line 8 */\n#define EXTI_RTSR1_TR9_Pos         (9U)\n#define EXTI_RTSR1_TR9_Msk         (0x1UL << EXTI_RTSR1_TR9_Pos)               /*!< 0x00000200 */\n#define EXTI_RTSR1_TR9             EXTI_RTSR1_TR9_Msk                          /*!< Rising trigger event configuration bit of line 9 */\n#define EXTI_RTSR1_TR10_Pos        (10U)\n#define EXTI_RTSR1_TR10_Msk        (0x1UL << EXTI_RTSR1_TR10_Pos)              /*!< 0x00000400 */\n#define EXTI_RTSR1_TR10            EXTI_RTSR1_TR10_Msk                         /*!< Rising trigger event configuration bit of line 10 */\n#define EXTI_RTSR1_TR11_Pos        (11U)\n#define EXTI_RTSR1_TR11_Msk        (0x1UL << EXTI_RTSR1_TR11_Pos)              /*!< 0x00000800 */\n#define EXTI_RTSR1_TR11            EXTI_RTSR1_TR11_Msk                         /*!< Rising trigger event configuration bit of line 11 */\n#define EXTI_RTSR1_TR12_Pos        (12U)\n#define EXTI_RTSR1_TR12_Msk        (0x1UL << EXTI_RTSR1_TR12_Pos)              /*!< 0x00001000 */\n#define EXTI_RTSR1_TR12            EXTI_RTSR1_TR12_Msk                         /*!< Rising trigger event configuration bit of line 12 */\n#define EXTI_RTSR1_TR13_Pos        (13U)\n#define EXTI_RTSR1_TR13_Msk        (0x1UL << EXTI_RTSR1_TR13_Pos)              /*!< 0x00002000 */\n#define EXTI_RTSR1_TR13            EXTI_RTSR1_TR13_Msk                         /*!< Rising trigger event configuration bit of line 13 */\n#define EXTI_RTSR1_TR14_Pos        (14U)\n#define EXTI_RTSR1_TR14_Msk        (0x1UL << EXTI_RTSR1_TR14_Pos)              /*!< 0x00004000 */\n#define EXTI_RTSR1_TR14            EXTI_RTSR1_TR14_Msk                         /*!< Rising trigger event configuration bit of line 14 */\n#define EXTI_RTSR1_TR15_Pos        (15U)\n#define EXTI_RTSR1_TR15_Msk        (0x1UL << EXTI_RTSR1_TR15_Pos)              /*!< 0x00008000 */\n#define EXTI_RTSR1_TR15            EXTI_RTSR1_TR15_Msk                         /*!< Rising trigger event configuration bit of line 15 */\n#define EXTI_RTSR1_TR16_Pos        (16U)\n#define EXTI_RTSR1_TR16_Msk        (0x1UL << EXTI_RTSR1_TR16_Pos)              /*!< 0x00010000 */\n#define EXTI_RTSR1_TR16            EXTI_RTSR1_TR16_Msk                         /*!< Rising trigger event configuration bit of line 16 */\n#define EXTI_RTSR1_TR17_Pos        (17U)\n#define EXTI_RTSR1_TR17_Msk        (0x1UL << EXTI_RTSR1_TR17_Pos)              /*!< 0x00020000 */\n#define EXTI_RTSR1_TR17            EXTI_RTSR1_TR17_Msk                         /*!< Rising trigger event configuration bit of line 17 */\n#define EXTI_RTSR1_TR18_Pos        (18U)\n#define EXTI_RTSR1_TR18_Msk        (0x1UL << EXTI_RTSR1_TR18_Pos)              /*!< 0x00040000 */\n#define EXTI_RTSR1_TR18            EXTI_RTSR1_TR18_Msk                         /*!< Rising trigger event configuration bit of line 18 */\n#define EXTI_RTSR1_TR19_Pos        (19U)\n#define EXTI_RTSR1_TR19_Msk        (0x1UL << EXTI_RTSR1_TR19_Pos)              /*!< 0x00080000 */\n#define EXTI_RTSR1_TR19            EXTI_RTSR1_TR19_Msk                         /*!< Rising trigger event configuration bit of line 19 */\n#define EXTI_RTSR1_TR20_Pos        (20U)\n#define EXTI_RTSR1_TR20_Msk        (0x1UL << EXTI_RTSR1_TR20_Pos)              /*!< 0x00100000 */\n#define EXTI_RTSR1_TR20            EXTI_RTSR1_TR20_Msk                         /*!< Rising trigger event configuration bit of line 20 */\n#define EXTI_RTSR1_TR21_Pos        (21U)\n#define EXTI_RTSR1_TR21_Msk        (0x1UL << EXTI_RTSR1_TR21_Pos)              /*!< 0x00200000 */\n#define EXTI_RTSR1_TR21            EXTI_RTSR1_TR21_Msk                         /*!< Rising trigger event configuration bit of line 21 */\n\n/******************  Bit definition for EXTI_FTSR1 register  *******************/\n#define EXTI_FTSR1_TR_Pos          (0U)\n#define EXTI_FTSR1_TR_Msk          (0x3FFFFFUL << EXTI_FTSR1_TR_Pos)           /*!< 0x003FFFFF */\n#define EXTI_FTSR1_TR              EXTI_FTSR1_TR_Msk                           /*!< Falling trigger event configuration bit */\n#define EXTI_FTSR1_TR0_Pos         (0U)\n#define EXTI_FTSR1_TR0_Msk         (0x1UL << EXTI_FTSR1_TR0_Pos)               /*!< 0x00000001 */\n#define EXTI_FTSR1_TR0             EXTI_FTSR1_TR0_Msk                          /*!< Falling trigger event configuration bit of line 0 */\n#define EXTI_FTSR1_TR1_Pos         (1U)\n#define EXTI_FTSR1_TR1_Msk         (0x1UL << EXTI_FTSR1_TR1_Pos)               /*!< 0x00000002 */\n#define EXTI_FTSR1_TR1             EXTI_FTSR1_TR1_Msk                          /*!< Falling trigger event configuration bit of line 1 */\n#define EXTI_FTSR1_TR2_Pos         (2U)\n#define EXTI_FTSR1_TR2_Msk         (0x1UL << EXTI_FTSR1_TR2_Pos)               /*!< 0x00000004 */\n#define EXTI_FTSR1_TR2             EXTI_FTSR1_TR2_Msk                          /*!< Falling trigger event configuration bit of line 2 */\n#define EXTI_FTSR1_TR3_Pos         (3U)\n#define EXTI_FTSR1_TR3_Msk         (0x1UL << EXTI_FTSR1_TR3_Pos)               /*!< 0x00000008 */\n#define EXTI_FTSR1_TR3             EXTI_FTSR1_TR3_Msk                          /*!< Falling trigger event configuration bit of line 3 */\n#define EXTI_FTSR1_TR4_Pos         (4U)\n#define EXTI_FTSR1_TR4_Msk         (0x1UL << EXTI_FTSR1_TR4_Pos)               /*!< 0x00000010 */\n#define EXTI_FTSR1_TR4             EXTI_FTSR1_TR4_Msk                          /*!< Falling trigger event configuration bit of line 4 */\n#define EXTI_FTSR1_TR5_Pos         (5U)\n#define EXTI_FTSR1_TR5_Msk         (0x1UL << EXTI_FTSR1_TR5_Pos)               /*!< 0x00000020 */\n#define EXTI_FTSR1_TR5             EXTI_FTSR1_TR5_Msk                          /*!< Falling trigger event configuration bit of line 5 */\n#define EXTI_FTSR1_TR6_Pos         (6U)\n#define EXTI_FTSR1_TR6_Msk         (0x1UL << EXTI_FTSR1_TR6_Pos)               /*!< 0x00000040 */\n#define EXTI_FTSR1_TR6             EXTI_FTSR1_TR6_Msk                          /*!< Falling trigger event configuration bit of line 6 */\n#define EXTI_FTSR1_TR7_Pos         (7U)\n#define EXTI_FTSR1_TR7_Msk         (0x1UL << EXTI_FTSR1_TR7_Pos)               /*!< 0x00000080 */\n#define EXTI_FTSR1_TR7             EXTI_FTSR1_TR7_Msk                          /*!< Falling trigger event configuration bit of line 7 */\n#define EXTI_FTSR1_TR8_Pos         (8U)\n#define EXTI_FTSR1_TR8_Msk         (0x1UL << EXTI_FTSR1_TR8_Pos)               /*!< 0x00000100 */\n#define EXTI_FTSR1_TR8             EXTI_FTSR1_TR8_Msk                          /*!< Falling trigger event configuration bit of line 8 */\n#define EXTI_FTSR1_TR9_Pos         (9U)\n#define EXTI_FTSR1_TR9_Msk         (0x1UL << EXTI_FTSR1_TR9_Pos)               /*!< 0x00000200 */\n#define EXTI_FTSR1_TR9             EXTI_FTSR1_TR9_Msk                          /*!< Falling trigger event configuration bit of line 9 */\n#define EXTI_FTSR1_TR10_Pos        (10U)\n#define EXTI_FTSR1_TR10_Msk        (0x1UL << EXTI_FTSR1_TR10_Pos)              /*!< 0x00000400 */\n#define EXTI_FTSR1_TR10            EXTI_FTSR1_TR10_Msk                         /*!< Falling trigger event configuration bit of line 10 */\n#define EXTI_FTSR1_TR11_Pos        (11U)\n#define EXTI_FTSR1_TR11_Msk        (0x1UL << EXTI_FTSR1_TR11_Pos)              /*!< 0x00000800 */\n#define EXTI_FTSR1_TR11            EXTI_FTSR1_TR11_Msk                         /*!< Falling trigger event configuration bit of line 11 */\n#define EXTI_FTSR1_TR12_Pos        (12U)\n#define EXTI_FTSR1_TR12_Msk        (0x1UL << EXTI_FTSR1_TR12_Pos)              /*!< 0x00001000 */\n#define EXTI_FTSR1_TR12            EXTI_FTSR1_TR12_Msk                         /*!< Falling trigger event configuration bit of line 12 */\n#define EXTI_FTSR1_TR13_Pos        (13U)\n#define EXTI_FTSR1_TR13_Msk        (0x1UL << EXTI_FTSR1_TR13_Pos)              /*!< 0x00002000 */\n#define EXTI_FTSR1_TR13            EXTI_FTSR1_TR13_Msk                         /*!< Falling trigger event configuration bit of line 13 */\n#define EXTI_FTSR1_TR14_Pos        (14U)\n#define EXTI_FTSR1_TR14_Msk        (0x1UL << EXTI_FTSR1_TR14_Pos)              /*!< 0x00004000 */\n#define EXTI_FTSR1_TR14            EXTI_FTSR1_TR14_Msk                         /*!< Falling trigger event configuration bit of line 14 */\n#define EXTI_FTSR1_TR15_Pos        (15U)\n#define EXTI_FTSR1_TR15_Msk        (0x1UL << EXTI_FTSR1_TR15_Pos)              /*!< 0x00008000 */\n#define EXTI_FTSR1_TR15            EXTI_FTSR1_TR15_Msk                         /*!< Falling trigger event configuration bit of line 15 */\n#define EXTI_FTSR1_TR16_Pos        (16U)\n#define EXTI_FTSR1_TR16_Msk        (0x1UL << EXTI_FTSR1_TR16_Pos)              /*!< 0x00010000 */\n#define EXTI_FTSR1_TR16            EXTI_FTSR1_TR16_Msk                         /*!< Falling trigger event configuration bit of line 16 */\n#define EXTI_FTSR1_TR17_Pos        (17U)\n#define EXTI_FTSR1_TR17_Msk        (0x1UL << EXTI_FTSR1_TR17_Pos)              /*!< 0x00020000 */\n#define EXTI_FTSR1_TR17            EXTI_FTSR1_TR17_Msk                         /*!< Falling trigger event configuration bit of line 17 */\n#define EXTI_FTSR1_TR18_Pos        (18U)\n#define EXTI_FTSR1_TR18_Msk        (0x1UL << EXTI_FTSR1_TR18_Pos)              /*!< 0x00040000 */\n#define EXTI_FTSR1_TR18            EXTI_FTSR1_TR18_Msk                         /*!< Falling trigger event configuration bit of line 18 */\n#define EXTI_FTSR1_TR19_Pos        (19U)\n#define EXTI_FTSR1_TR19_Msk        (0x1UL << EXTI_FTSR1_TR19_Pos)              /*!< 0x00080000 */\n#define EXTI_FTSR1_TR19            EXTI_FTSR1_TR19_Msk                         /*!< Falling trigger event configuration bit of line 19 */\n#define EXTI_FTSR1_TR20_Pos        (20U)\n#define EXTI_FTSR1_TR20_Msk        (0x1UL << EXTI_FTSR1_TR20_Pos)              /*!< 0x00100000 */\n#define EXTI_FTSR1_TR20            EXTI_FTSR1_TR20_Msk                         /*!< Falling trigger event configuration bit of line 20 */\n#define EXTI_FTSR1_TR21_Pos        (21U)\n#define EXTI_FTSR1_TR21_Msk        (0x1UL << EXTI_FTSR1_TR21_Pos)              /*!< 0x00200000 */\n#define EXTI_FTSR1_TR21            EXTI_FTSR1_TR21_Msk                         /*!< Falling trigger event configuration bit of line 21 */\n\n/******************  Bit definition for EXTI_SWIER1 register  ******************/\n#define EXTI_SWIER1_SWIER0_Pos     (0U)\n#define EXTI_SWIER1_SWIER0_Msk     (0x1UL << EXTI_SWIER1_SWIER0_Pos)           /*!< 0x00000001 */\n#define EXTI_SWIER1_SWIER0         EXTI_SWIER1_SWIER0_Msk                      /*!< Software Interrupt on line 0 */\n#define EXTI_SWIER1_SWIER1_Pos     (1U)\n#define EXTI_SWIER1_SWIER1_Msk     (0x1UL << EXTI_SWIER1_SWIER1_Pos)           /*!< 0x00000002 */\n#define EXTI_SWIER1_SWIER1         EXTI_SWIER1_SWIER1_Msk                      /*!< Software Interrupt on line 1 */\n#define EXTI_SWIER1_SWIER2_Pos     (2U)\n#define EXTI_SWIER1_SWIER2_Msk     (0x1UL << EXTI_SWIER1_SWIER2_Pos)           /*!< 0x00000004 */\n#define EXTI_SWIER1_SWIER2         EXTI_SWIER1_SWIER2_Msk                      /*!< Software Interrupt on line 2 */\n#define EXTI_SWIER1_SWIER3_Pos     (3U)\n#define EXTI_SWIER1_SWIER3_Msk     (0x1UL << EXTI_SWIER1_SWIER3_Pos)           /*!< 0x00000008 */\n#define EXTI_SWIER1_SWIER3         EXTI_SWIER1_SWIER3_Msk                      /*!< Software Interrupt on line 3 */\n#define EXTI_SWIER1_SWIER4_Pos     (4U)\n#define EXTI_SWIER1_SWIER4_Msk     (0x1UL << EXTI_SWIER1_SWIER4_Pos)           /*!< 0x00000010 */\n#define EXTI_SWIER1_SWIER4         EXTI_SWIER1_SWIER4_Msk                      /*!< Software Interrupt on line 4 */\n#define EXTI_SWIER1_SWIER5_Pos     (5U)\n#define EXTI_SWIER1_SWIER5_Msk     (0x1UL << EXTI_SWIER1_SWIER5_Pos)           /*!< 0x00000020 */\n#define EXTI_SWIER1_SWIER5         EXTI_SWIER1_SWIER5_Msk                      /*!< Software Interrupt on line 5 */\n#define EXTI_SWIER1_SWIER6_Pos     (6U)\n#define EXTI_SWIER1_SWIER6_Msk     (0x1UL << EXTI_SWIER1_SWIER6_Pos)           /*!< 0x00000040 */\n#define EXTI_SWIER1_SWIER6         EXTI_SWIER1_SWIER6_Msk                      /*!< Software Interrupt on line 6 */\n#define EXTI_SWIER1_SWIER7_Pos     (7U)\n#define EXTI_SWIER1_SWIER7_Msk     (0x1UL << EXTI_SWIER1_SWIER7_Pos)           /*!< 0x00000080 */\n#define EXTI_SWIER1_SWIER7         EXTI_SWIER1_SWIER7_Msk                      /*!< Software Interrupt on line 7 */\n#define EXTI_SWIER1_SWIER8_Pos     (8U)\n#define EXTI_SWIER1_SWIER8_Msk     (0x1UL << EXTI_SWIER1_SWIER8_Pos)           /*!< 0x00000100 */\n#define EXTI_SWIER1_SWIER8         EXTI_SWIER1_SWIER8_Msk                      /*!< Software Interrupt on line 8 */\n#define EXTI_SWIER1_SWIER9_Pos     (9U)\n#define EXTI_SWIER1_SWIER9_Msk     (0x1UL << EXTI_SWIER1_SWIER9_Pos)           /*!< 0x00000200 */\n#define EXTI_SWIER1_SWIER9         EXTI_SWIER1_SWIER9_Msk                      /*!< Software Interrupt on line 9 */\n#define EXTI_SWIER1_SWIER10_Pos    (10U)\n#define EXTI_SWIER1_SWIER10_Msk    (0x1UL << EXTI_SWIER1_SWIER10_Pos)          /*!< 0x00000400 */\n#define EXTI_SWIER1_SWIER10        EXTI_SWIER1_SWIER10_Msk                     /*!< Software Interrupt on line 10 */\n#define EXTI_SWIER1_SWIER11_Pos    (11U)\n#define EXTI_SWIER1_SWIER11_Msk    (0x1UL << EXTI_SWIER1_SWIER11_Pos)          /*!< 0x00000800 */\n#define EXTI_SWIER1_SWIER11        EXTI_SWIER1_SWIER11_Msk                     /*!< Software Interrupt on line 11 */\n#define EXTI_SWIER1_SWIER12_Pos    (12U)\n#define EXTI_SWIER1_SWIER12_Msk    (0x1UL << EXTI_SWIER1_SWIER12_Pos)          /*!< 0x00001000 */\n#define EXTI_SWIER1_SWIER12        EXTI_SWIER1_SWIER12_Msk                     /*!< Software Interrupt on line 12 */\n#define EXTI_SWIER1_SWIER13_Pos    (13U)\n#define EXTI_SWIER1_SWIER13_Msk    (0x1UL << EXTI_SWIER1_SWIER13_Pos)          /*!< 0x00002000 */\n#define EXTI_SWIER1_SWIER13        EXTI_SWIER1_SWIER13_Msk                     /*!< Software Interrupt on line 13 */\n#define EXTI_SWIER1_SWIER14_Pos    (14U)\n#define EXTI_SWIER1_SWIER14_Msk    (0x1UL << EXTI_SWIER1_SWIER14_Pos)          /*!< 0x00004000 */\n#define EXTI_SWIER1_SWIER14        EXTI_SWIER1_SWIER14_Msk                     /*!< Software Interrupt on line 14 */\n#define EXTI_SWIER1_SWIER15_Pos    (15U)\n#define EXTI_SWIER1_SWIER15_Msk    (0x1UL << EXTI_SWIER1_SWIER15_Pos)          /*!< 0x00008000 */\n#define EXTI_SWIER1_SWIER15        EXTI_SWIER1_SWIER15_Msk                     /*!< Software Interrupt on line 15 */\n#define EXTI_SWIER1_SWIER16_Pos    (16U)\n#define EXTI_SWIER1_SWIER16_Msk    (0x1UL << EXTI_SWIER1_SWIER16_Pos)          /*!< 0x00010000 */\n#define EXTI_SWIER1_SWIER16        EXTI_SWIER1_SWIER16_Msk                     /*!< Software Interrupt on line 16 */\n#define EXTI_SWIER1_SWIER17_Pos    (17U)\n#define EXTI_SWIER1_SWIER17_Msk    (0x1UL << EXTI_SWIER1_SWIER17_Pos)          /*!< 0x00020000 */\n#define EXTI_SWIER1_SWIER17        EXTI_SWIER1_SWIER17_Msk                     /*!< Software Interrupt on line 17 */\n#define EXTI_SWIER1_SWIER18_Pos    (18U)\n#define EXTI_SWIER1_SWIER18_Msk    (0x1UL << EXTI_SWIER1_SWIER18_Pos)          /*!< 0x00040000 */\n#define EXTI_SWIER1_SWIER18        EXTI_SWIER1_SWIER18_Msk                     /*!< Software Interrupt on line 18 */\n#define EXTI_SWIER1_SWIER19_Pos    (19U)\n#define EXTI_SWIER1_SWIER19_Msk    (0x1UL << EXTI_SWIER1_SWIER19_Pos)          /*!< 0x00080000 */\n#define EXTI_SWIER1_SWIER19        EXTI_SWIER1_SWIER19_Msk                     /*!< Software Interrupt on line 19 */\n#define EXTI_SWIER1_SWIER20_Pos    (20U)\n#define EXTI_SWIER1_SWIER20_Msk    (0x1UL << EXTI_SWIER1_SWIER20_Pos)          /*!< 0x00100000 */\n#define EXTI_SWIER1_SWIER20        EXTI_SWIER1_SWIER20_Msk                     /*!< Software Interrupt on line 20 */\n#define EXTI_SWIER1_SWIER21_Pos    (21U)\n#define EXTI_SWIER1_SWIER21_Msk    (0x1UL << EXTI_SWIER1_SWIER21_Pos)          /*!< 0x00200000 */\n#define EXTI_SWIER1_SWIER21        EXTI_SWIER1_SWIER21_Msk                     /*!< Software Interrupt on line 21 */\n\n/******************  Bit definition for EXTI_D3PMR1 register  ******************/\n#define EXTI_D3PMR1_MR0_Pos        (0U)\n#define EXTI_D3PMR1_MR0_Msk        (0x1UL << EXTI_D3PMR1_MR0_Pos)              /*!< 0x00000001 */\n#define EXTI_D3PMR1_MR0            EXTI_D3PMR1_MR0_Msk                         /*!< Pending Mask Event for line 0  */\n#define EXTI_D3PMR1_MR1_Pos        (1U)\n#define EXTI_D3PMR1_MR1_Msk        (0x1UL << EXTI_D3PMR1_MR1_Pos)              /*!< 0x00000002 */\n#define EXTI_D3PMR1_MR1            EXTI_D3PMR1_MR1_Msk                         /*!< Pending Mask Event for line 1  */\n#define EXTI_D3PMR1_MR2_Pos        (2U)\n#define EXTI_D3PMR1_MR2_Msk        (0x1UL << EXTI_D3PMR1_MR2_Pos)              /*!< 0x00000004 */\n#define EXTI_D3PMR1_MR2            EXTI_D3PMR1_MR2_Msk                         /*!< Pending Mask Event for line 2  */\n#define EXTI_D3PMR1_MR3_Pos        (3U)\n#define EXTI_D3PMR1_MR3_Msk        (0x1UL << EXTI_D3PMR1_MR3_Pos)              /*!< 0x00000008 */\n#define EXTI_D3PMR1_MR3            EXTI_D3PMR1_MR3_Msk                         /*!< Pending Mask Event for line 3  */\n#define EXTI_D3PMR1_MR4_Pos        (4U)\n#define EXTI_D3PMR1_MR4_Msk        (0x1UL << EXTI_D3PMR1_MR4_Pos)              /*!< 0x00000010 */\n#define EXTI_D3PMR1_MR4            EXTI_D3PMR1_MR4_Msk                         /*!< Pending Mask Event for line 4  */\n#define EXTI_D3PMR1_MR5_Pos        (5U)\n#define EXTI_D3PMR1_MR5_Msk        (0x1UL << EXTI_D3PMR1_MR5_Pos)              /*!< 0x00000020 */\n#define EXTI_D3PMR1_MR5            EXTI_D3PMR1_MR5_Msk                         /*!< Pending Mask Event for line 5  */\n#define EXTI_D3PMR1_MR6_Pos        (6U)\n#define EXTI_D3PMR1_MR6_Msk        (0x1UL << EXTI_D3PMR1_MR6_Pos)              /*!< 0x00000040 */\n#define EXTI_D3PMR1_MR6            EXTI_D3PMR1_MR6_Msk                         /*!< Pending Mask Event for line 6  */\n#define EXTI_D3PMR1_MR7_Pos        (7U)\n#define EXTI_D3PMR1_MR7_Msk        (0x1UL << EXTI_D3PMR1_MR7_Pos)              /*!< 0x00000080 */\n#define EXTI_D3PMR1_MR7            EXTI_D3PMR1_MR7_Msk                         /*!< Pending Mask Event for line 7  */\n#define EXTI_D3PMR1_MR8_Pos        (8U)\n#define EXTI_D3PMR1_MR8_Msk        (0x1UL << EXTI_D3PMR1_MR8_Pos)              /*!< 0x00000100 */\n#define EXTI_D3PMR1_MR8            EXTI_D3PMR1_MR8_Msk                         /*!< Pending Mask Event for line 8  */\n#define EXTI_D3PMR1_MR9_Pos        (9U)\n#define EXTI_D3PMR1_MR9_Msk        (0x1UL << EXTI_D3PMR1_MR9_Pos)              /*!< 0x00000200 */\n#define EXTI_D3PMR1_MR9            EXTI_D3PMR1_MR9_Msk                         /*!< Pending Mask Event for line 9  */\n#define EXTI_D3PMR1_MR10_Pos       (10U)\n#define EXTI_D3PMR1_MR10_Msk       (0x1UL << EXTI_D3PMR1_MR10_Pos)             /*!< 0x00000400 */\n#define EXTI_D3PMR1_MR10           EXTI_D3PMR1_MR10_Msk                        /*!< Pending Mask Event for line 10 */\n#define EXTI_D3PMR1_MR11_Pos       (11U)\n#define EXTI_D3PMR1_MR11_Msk       (0x1UL << EXTI_D3PMR1_MR11_Pos)             /*!< 0x00000800 */\n#define EXTI_D3PMR1_MR11           EXTI_D3PMR1_MR11_Msk                        /*!< Pending Mask Event for line 11 */\n#define EXTI_D3PMR1_MR12_Pos       (12U)\n#define EXTI_D3PMR1_MR12_Msk       (0x1UL << EXTI_D3PMR1_MR12_Pos)             /*!< 0x00001000 */\n#define EXTI_D3PMR1_MR12           EXTI_D3PMR1_MR12_Msk                        /*!< Pending Mask Event for line 12 */\n#define EXTI_D3PMR1_MR13_Pos       (13U)\n#define EXTI_D3PMR1_MR13_Msk       (0x1UL << EXTI_D3PMR1_MR13_Pos)             /*!< 0x00002000 */\n#define EXTI_D3PMR1_MR13           EXTI_D3PMR1_MR13_Msk                        /*!< Pending Mask Event for line 13 */\n#define EXTI_D3PMR1_MR14_Pos       (14U)\n#define EXTI_D3PMR1_MR14_Msk       (0x1UL << EXTI_D3PMR1_MR14_Pos)             /*!< 0x00004000 */\n#define EXTI_D3PMR1_MR14           EXTI_D3PMR1_MR14_Msk                        /*!< Pending Mask Event for line 14 */\n#define EXTI_D3PMR1_MR15_Pos       (15U)\n#define EXTI_D3PMR1_MR15_Msk       (0x1UL << EXTI_D3PMR1_MR15_Pos)             /*!< 0x00008000 */\n#define EXTI_D3PMR1_MR15           EXTI_D3PMR1_MR15_Msk                        /*!< Pending Mask Event for line 15 */\n#define EXTI_D3PMR1_MR19_Pos       (19U)\n#define EXTI_D3PMR1_MR19_Msk       (0x1UL << EXTI_D3PMR1_MR19_Pos)             /*!< 0x00080000 */\n#define EXTI_D3PMR1_MR19           EXTI_D3PMR1_MR19_Msk                        /*!< Pending Mask Event for line 19 */\n#define EXTI_D3PMR1_MR20_Pos       (20U)\n#define EXTI_D3PMR1_MR20_Msk       (0x1UL << EXTI_D3PMR1_MR20_Pos)             /*!< 0x00100000 */\n#define EXTI_D3PMR1_MR20           EXTI_D3PMR1_MR20_Msk                        /*!< Pending Mask Event for line 20 */\n#define EXTI_D3PMR1_MR21_Pos       (21U)\n#define EXTI_D3PMR1_MR21_Msk       (0x1UL << EXTI_D3PMR1_MR21_Pos)             /*!< 0x00200000 */\n#define EXTI_D3PMR1_MR21           EXTI_D3PMR1_MR21_Msk                        /*!< Pending Mask Event for line 21 */\n#define EXTI_D3PMR1_MR25_Pos       (24U)\n#define EXTI_D3PMR1_MR25_Msk       (0x1UL << EXTI_D3PMR1_MR25_Pos)             /*!< 0x01000000 */\n#define EXTI_D3PMR1_MR25           EXTI_D3PMR1_MR25_Msk                        /*!< Pending Mask Event for line 25 */\n\n/*******************  Bit definition for EXTI_D3PCR1L register  ****************/\n#define EXTI_D3PCR1L_PCS0_Pos       (0U)\n#define EXTI_D3PCR1L_PCS0_Msk       (0x3UL << EXTI_D3PCR1L_PCS0_Pos)           /*!< 0x00000003 */\n#define EXTI_D3PCR1L_PCS0           EXTI_D3PCR1L_PCS0_Msk                      /*!< D3 Pending request clear input signal selection on line 0 */\n#define EXTI_D3PCR1L_PCS1_Pos       (2U)\n#define EXTI_D3PCR1L_PCS1_Msk       (0x3UL << EXTI_D3PCR1L_PCS1_Pos)           /*!< 0x000000C0 */\n#define EXTI_D3PCR1L_PCS1           EXTI_D3PCR1L_PCS1_Msk                      /*!< D3 Pending request clear input signal selection on line 1 */\n#define EXTI_D3PCR1L_PCS2_Pos       (4U)\n#define EXTI_D3PCR1L_PCS2_Msk       (0x3UL << EXTI_D3PCR1L_PCS2_Pos)           /*!< 0x00000030 */\n#define EXTI_D3PCR1L_PCS2           EXTI_D3PCR1L_PCS2_Msk                      /*!< D3 Pending request clear input signal selection on line 2 */\n#define EXTI_D3PCR1L_PCS3_Pos       (6U)\n#define EXTI_D3PCR1L_PCS3_Msk       (0x3UL << EXTI_D3PCR1L_PCS3_Pos)           /*!< 0x000000C0 */\n#define EXTI_D3PCR1L_PCS3           EXTI_D3PCR1L_PCS3_Msk                      /*!< D3 Pending request clear input signal selection on line 3 */\n#define EXTI_D3PCR1L_PCS4_Pos       (8U)\n#define EXTI_D3PCR1L_PCS4_Msk       (0x3UL << EXTI_D3PCR1L_PCS4_Pos)           /*!< 0x00000300 */\n#define EXTI_D3PCR1L_PCS4           EXTI_D3PCR1L_PCS4_Msk                      /*!< D3 Pending request clear input signal selection on line 4 */\n#define EXTI_D3PCR1L_PCS5_Pos       (10U)\n#define EXTI_D3PCR1L_PCS5_Msk       (0x3UL << EXTI_D3PCR1L_PCS5_Pos)           /*!< 0x00000C00 */\n#define EXTI_D3PCR1L_PCS5           EXTI_D3PCR1L_PCS5_Msk                      /*!< D3 Pending request clear input signal selection on line 5 */\n#define EXTI_D3PCR1L_PCS6_Pos       (12U)\n#define EXTI_D3PCR1L_PCS6_Msk       (0x3UL << EXTI_D3PCR1L_PCS6_Pos)           /*!< 0x00003000 */\n#define EXTI_D3PCR1L_PCS6           EXTI_D3PCR1L_PCS6_Msk                      /*!< D3 Pending request clear input signal selection on line 6 */\n#define EXTI_D3PCR1L_PCS7_Pos       (14U)\n#define EXTI_D3PCR1L_PCS7_Msk       (0x3UL << EXTI_D3PCR1L_PCS7_Pos)           /*!< 0x0000C000 */\n#define EXTI_D3PCR1L_PCS7           EXTI_D3PCR1L_PCS7_Msk                      /*!< D3 Pending request clear input signal selection on line 7 */\n#define EXTI_D3PCR1L_PCS8_Pos       (16U)\n#define EXTI_D3PCR1L_PCS8_Msk       (0x3UL << EXTI_D3PCR1L_PCS8_Pos)           /*!< 0x00030000 */\n#define EXTI_D3PCR1L_PCS8           EXTI_D3PCR1L_PCS8_Msk                      /*!< D3 Pending request clear input signal selection on line 8 */\n#define EXTI_D3PCR1L_PCS9_Pos       (18U)\n#define EXTI_D3PCR1L_PCS9_Msk       (0x3UL << EXTI_D3PCR1L_PCS9_Pos)           /*!< 0x000C0000 */\n#define EXTI_D3PCR1L_PCS9           EXTI_D3PCR1L_PCS9_Msk                      /*!< D3 Pending request clear input signal selection on line 9 */\n#define EXTI_D3PCR1L_PCS10_Pos      (20U)\n#define EXTI_D3PCR1L_PCS10_Msk      (0x3UL << EXTI_D3PCR1L_PCS10_Pos)          /*!< 0x00300000 */\n#define EXTI_D3PCR1L_PCS10          EXTI_D3PCR1L_PCS10_Msk                     /*!< D3 Pending request clear input signal selection on line 10*/\n#define EXTI_D3PCR1L_PCS11_Pos      (22U)\n#define EXTI_D3PCR1L_PCS11_Msk      (0x3UL << EXTI_D3PCR1L_PCS11_Pos)          /*!< 0x00C00000 */\n#define EXTI_D3PCR1L_PCS11          EXTI_D3PCR1L_PCS11_Msk                     /*!< D3 Pending request clear input signal selection on line 11*/\n#define EXTI_D3PCR1L_PCS12_Pos      (24U)\n#define EXTI_D3PCR1L_PCS12_Msk      (0x3UL << EXTI_D3PCR1L_PCS12_Pos)          /*!< 0x03000000 */\n#define EXTI_D3PCR1L_PCS12          EXTI_D3PCR1L_PCS12_Msk                     /*!< D3 Pending request clear input signal selection on line 12*/\n#define EXTI_D3PCR1L_PCS13_Pos      (26U)\n#define EXTI_D3PCR1L_PCS13_Msk      (0x3UL << EXTI_D3PCR1L_PCS13_Pos)          /*!< 0x0C000000 */\n#define EXTI_D3PCR1L_PCS13          EXTI_D3PCR1L_PCS13_Msk                     /*!< D3 Pending request clear input signal selection on line 13*/\n#define EXTI_D3PCR1L_PCS14_Pos      (28U)\n#define EXTI_D3PCR1L_PCS14_Msk      (0x3UL << EXTI_D3PCR1L_PCS14_Pos)          /*!< 0x30000000 */\n#define EXTI_D3PCR1L_PCS14          EXTI_D3PCR1L_PCS14_Msk                     /*!< D3 Pending request clear input signal selection on line 14*/\n#define EXTI_D3PCR1L_PCS15_Pos      (30U)\n#define EXTI_D3PCR1L_PCS15_Msk      (0x3UL << EXTI_D3PCR1L_PCS15_Pos)          /*!< 0xC0000000 */\n#define EXTI_D3PCR1L_PCS15          EXTI_D3PCR1L_PCS15_Msk                     /*!< D3 Pending request clear input signal selection on line 15*/\n\n/*******************  Bit definition for EXTI_D3PCR1H register  ****************/\n#define EXTI_D3PCR1H_PCS19_Pos       (6U)\n#define EXTI_D3PCR1H_PCS19_Msk       (0x3UL << EXTI_D3PCR1H_PCS19_Pos)         /*!< 0x000000C0 */\n#define EXTI_D3PCR1H_PCS19           EXTI_D3PCR1H_PCS19_Msk                    /*!< D3 Pending request clear input signal selection on line 19 */\n#define EXTI_D3PCR1H_PCS20_Pos       (8U)\n#define EXTI_D3PCR1H_PCS20_Msk       (0x3UL << EXTI_D3PCR1H_PCS20_Pos)         /*!< 0x00000300 */\n#define EXTI_D3PCR1H_PCS20           EXTI_D3PCR1H_PCS20_Msk                    /*!< D3 Pending request clear input signal selection on line 20 */\n#define EXTI_D3PCR1H_PCS21_Pos       (10U)\n#define EXTI_D3PCR1H_PCS21_Msk       (0x3UL << EXTI_D3PCR1H_PCS21_Pos)         /*!< 0x00000C00 */\n#define EXTI_D3PCR1H_PCS21           EXTI_D3PCR1H_PCS21_Msk                    /*!< D3 Pending request clear input signal selection on line 21 */\n#define EXTI_D3PCR1H_PCS25_Pos       (18U)\n#define EXTI_D3PCR1H_PCS25_Msk       (0x3UL << EXTI_D3PCR1H_PCS25_Pos)         /*!< 0x000C0000 */\n#define EXTI_D3PCR1H_PCS25           EXTI_D3PCR1H_PCS25_Msk                    /*!< D3 Pending request clear input signal selection on line 25 */\n\n/******************  Bit definition for EXTI_RTSR2 register  *******************/\n#define EXTI_RTSR2_TR_Pos          (17U)\n#define EXTI_RTSR2_TR_Msk          (0x5UL << EXTI_RTSR2_TR_Pos)                /*!< 0x000A0000 */\n#define EXTI_RTSR2_TR              EXTI_RTSR2_TR_Msk                           /*!< Rising trigger event configuration bit */\n#define EXTI_RTSR2_TR49_Pos        (17U)\n#define EXTI_RTSR2_TR49_Msk        (0x1UL << EXTI_RTSR2_TR49_Pos)              /*!< 0x00020000 */\n#define EXTI_RTSR2_TR49            EXTI_RTSR2_TR49_Msk                         /*!< Rising trigger event configuration bit of line 49 */\n#define EXTI_RTSR2_TR51_Pos        (19U)\n#define EXTI_RTSR2_TR51_Msk        (0x1UL << EXTI_RTSR2_TR51_Pos)              /*!< 0x00080000 */\n#define EXTI_RTSR2_TR51            EXTI_RTSR2_TR51_Msk                         /*!< Rising trigger event configuration bit of line 51 */\n\n/******************  Bit definition for EXTI_FTSR2 register  *******************/\n#define EXTI_FTSR2_TR_Pos          (17U)\n#define EXTI_FTSR2_TR_Msk          (0x5UL << EXTI_FTSR2_TR_Pos)                /*!< 0x000A0000 */\n#define EXTI_FTSR2_TR              EXTI_FTSR2_TR_Msk                           /*!< Falling trigger event configuration bit */\n#define EXTI_FTSR2_TR49_Pos        (17U)\n#define EXTI_FTSR2_TR49_Msk        (0x1UL << EXTI_FTSR2_TR49_Pos)              /*!< 0x00020000 */\n#define EXTI_FTSR2_TR49            EXTI_FTSR2_TR49_Msk                         /*!< Falling trigger event configuration bit of line 49 */\n#define EXTI_FTSR2_TR51_Pos        (19U)\n#define EXTI_FTSR2_TR51_Msk        (0x1UL << EXTI_FTSR2_TR51_Pos)              /*!< 0x00080000 */\n#define EXTI_FTSR2_TR51            EXTI_FTSR2_TR51_Msk                         /*!< Falling trigger event configuration bit of line 51 */\n\n/******************  Bit definition for EXTI_SWIER2 register  ******************/\n#define EXTI_SWIER2_SWIER49_Pos    (17U)\n#define EXTI_SWIER2_SWIER49_Msk    (0x1UL << EXTI_SWIER2_SWIER49_Pos)          /*!< 0x00020000 */\n#define EXTI_SWIER2_SWIER49        EXTI_SWIER2_SWIER49_Msk                     /*!< Software Interrupt on line 49 */\n#define EXTI_SWIER2_SWIER51_Pos    (19U)\n#define EXTI_SWIER2_SWIER51_Msk    (0x1UL << EXTI_SWIER2_SWIER51_Pos)          /*!< 0x00080000 */\n#define EXTI_SWIER2_SWIER51        EXTI_SWIER2_SWIER51_Msk                     /*!< Software Interrupt on line 51 */\n\n/******************  Bit definition for EXTI_D3PMR2 register  ******************/\n#define EXTI_D3PMR2_MR34_Pos       (2U)\n#define EXTI_D3PMR2_MR34_Msk       (0x1UL << EXTI_D3PMR2_MR34_Pos)             /*!< 0x00000004 */\n#define EXTI_D3PMR2_MR34           EXTI_D3PMR2_MR34_Msk                        /*!< Pending Mask Event for line 34  */\n#define EXTI_D3PMR2_MR35_Pos       (3U)\n#define EXTI_D3PMR2_MR35_Msk       (0x1UL << EXTI_D3PMR2_MR35_Pos)             /*!< 0x00000008 */\n#define EXTI_D3PMR2_MR35           EXTI_D3PMR2_MR35_Msk                        /*!< Pending Mask Event for line 35  */\n#define EXTI_D3PMR2_MR41_Pos       (9U)\n#define EXTI_D3PMR2_MR41_Msk       (0x1UL << EXTI_D3PMR2_MR41_Pos)             /*!< 0x00000200 */\n#define EXTI_D3PMR2_MR41           EXTI_D3PMR2_MR41_Msk                        /*!< Pending Mask Event for line 41  */\n#define EXTI_D3PMR2_MR48_Pos       (16U)\n#define EXTI_D3PMR2_MR48_Msk       (0x1UL << EXTI_D3PMR2_MR48_Pos)             /*!< 0x00010000 */\n#define EXTI_D3PMR2_MR48           EXTI_D3PMR2_MR48_Msk                        /*!< Pending Mask Event for line 48  */\n#define EXTI_D3PMR2_MR49_Pos       (17U)\n#define EXTI_D3PMR2_MR49_Msk       (0x1UL << EXTI_D3PMR2_MR49_Pos)             /*!< 0x00020000 */\n#define EXTI_D3PMR2_MR49           EXTI_D3PMR2_MR49_Msk                        /*!< Pending Mask Event for line 49  */\n#define EXTI_D3PMR2_MR50_Pos       (18U)\n#define EXTI_D3PMR2_MR50_Msk       (0x1UL << EXTI_D3PMR2_MR50_Pos)             /*!< 0x00040000 */\n#define EXTI_D3PMR2_MR50           EXTI_D3PMR2_MR50_Msk                        /*!< Pending Mask Event for line 50  */\n#define EXTI_D3PMR2_MR51_Pos       (19U)\n#define EXTI_D3PMR2_MR51_Msk       (0x1UL << EXTI_D3PMR2_MR51_Pos)             /*!< 0x00080000 */\n#define EXTI_D3PMR2_MR51           EXTI_D3PMR2_MR51_Msk                        /*!< Pending Mask Event for line 51  */\n#define EXTI_D3PMR2_MR52_Pos       (20U)\n#define EXTI_D3PMR2_MR52_Msk       (0x1UL << EXTI_D3PMR2_MR52_Pos)             /*!< 0x00100000 */\n#define EXTI_D3PMR2_MR52           EXTI_D3PMR2_MR52_Msk                        /*!< Pending Mask Event for line 52  */\n#define EXTI_D3PMR2_MR53_Pos       (21U)\n#define EXTI_D3PMR2_MR53_Msk       (0x1UL << EXTI_D3PMR2_MR53_Pos)             /*!< 0x00200000 */\n#define EXTI_D3PMR2_MR53           EXTI_D3PMR2_MR53_Msk                        /*!< Pending Mask Event for line 53  */\n/*******************  Bit definition for EXTI_D3PCR2L register  ****************/\n#define EXTI_D3PCR2L_PCS34_Pos       (4U)\n#define EXTI_D3PCR2L_PCS34_Msk       (0x3UL << EXTI_D3PCR2L_PCS34_Pos)         /*!< 0x00000030 */\n#define EXTI_D3PCR2L_PCS34           EXTI_D3PCR2L_PCS34_Msk                    /*!< D3 Pending request clear input signal selection on line 34 */\n#define EXTI_D3PCR2L_PCS35_Pos       (6U)\n#define EXTI_D3PCR2L_PCS35_Msk       (0x3UL << EXTI_D3PCR2L_PCS35_Pos)         /*!< 0x000000C0 */\n#define EXTI_D3PCR2L_PCS35           EXTI_D3PCR2L_PCS35_Msk                    /*!< D3 Pending request clear input signal selection on line 35 */\n#define EXTI_D3PCR2L_PCS41_Pos       (18U)\n#define EXTI_D3PCR2L_PCS41_Msk       (0x3UL << EXTI_D3PCR2L_PCS41_Pos)         /*!< 0x000C0000 */\n#define EXTI_D3PCR2L_PCS41           EXTI_D3PCR2L_PCS41_Msk                    /*!< D3 Pending request clear input signal selection on line 41 */\n\n\n/*******************  Bit definition for EXTI_D3PCR2H register  ****************/\n#define EXTI_D3PCR2H_PCS48_Pos       (0U)\n#define EXTI_D3PCR2H_PCS48_Msk       (0x3UL << EXTI_D3PCR2H_PCS48_Pos)         /*!< 0x00000003 */\n#define EXTI_D3PCR2H_PCS48           EXTI_D3PCR2H_PCS48_Msk                    /*!< D3 Pending request clear input signal selection on line 48 */\n#define EXTI_D3PCR2H_PCS49_Pos       (2U)\n#define EXTI_D3PCR2H_PCS49_Msk       (0x3UL << EXTI_D3PCR2H_PCS49_Pos)         /*!< 0x0000000C */\n#define EXTI_D3PCR2H_PCS49           EXTI_D3PCR2H_PCS49_Msk                    /*!< D3 Pending request clear input signal selection on line 49 */\n#define EXTI_D3PCR2H_PCS50_Pos       (4U)\n#define EXTI_D3PCR2H_PCS50_Msk       (0x3UL << EXTI_D3PCR2H_PCS50_Pos)         /*!< 0x00000030 */\n#define EXTI_D3PCR2H_PCS50           EXTI_D3PCR2H_PCS50_Msk                    /*!< D3 Pending request clear input signal selection on line 50 */\n#define EXTI_D3PCR2H_PCS51_Pos       (6U)\n#define EXTI_D3PCR2H_PCS51_Msk       (0x3UL << EXTI_D3PCR2H_PCS51_Pos)         /*!< 0x000000C0 */\n#define EXTI_D3PCR2H_PCS51           EXTI_D3PCR2H_PCS51_Msk                    /*!< D3 Pending request clear input signal selection on line 51 */\n#define EXTI_D3PCR2H_PCS52_Pos       (8U)\n#define EXTI_D3PCR2H_PCS52_Msk       (0x3UL << EXTI_D3PCR2H_PCS52_Pos)         /*!< 0x00000300 */\n#define EXTI_D3PCR2H_PCS52           EXTI_D3PCR2H_PCS52_Msk                    /*!< D3 Pending request clear input signal selection on line 52 */\n#define EXTI_D3PCR2H_PCS53_Pos       (10U)\n#define EXTI_D3PCR2H_PCS53_Msk       (0x3UL << EXTI_D3PCR2H_PCS53_Pos)         /*!< 0x00000C00 */\n#define EXTI_D3PCR2H_PCS53           EXTI_D3PCR2H_PCS53_Msk                    /*!< D3 Pending request clear input signal selection on line 53 */\n/******************  Bit definition for EXTI_RTSR3 register  *******************/\n#define EXTI_RTSR3_TR_Pos          (18U)\n#define EXTI_RTSR3_TR_Msk          (0x1DUL << EXTI_RTSR3_TR_Pos)               /*!< 0x00740000 */\n#define EXTI_RTSR3_TR              EXTI_RTSR3_TR_Msk                           /*!< Rising trigger event configuration bit */\n#define EXTI_RTSR3_TR82_Pos        (18U)\n#define EXTI_RTSR3_TR82_Msk        (0x1UL << EXTI_RTSR3_TR82_Pos)              /*!< 0x00040000 */\n#define EXTI_RTSR3_TR82            EXTI_RTSR3_TR82_Msk                         /*!< Rising trigger event configuration bit of line 82 */\n#define EXTI_RTSR3_TR84_Pos        (20U)\n#define EXTI_RTSR3_TR84_Msk        (0x1UL << EXTI_RTSR3_TR84_Pos)              /*!< 0x00100000 */\n#define EXTI_RTSR3_TR84            EXTI_RTSR3_TR84_Msk                         /*!< Rising trigger event configuration bit of line 84 */\n#define EXTI_RTSR3_TR85_Pos        (21U)\n#define EXTI_RTSR3_TR85_Msk        (0x1UL << EXTI_RTSR3_TR85_Pos)              /*!< 0x00200000 */\n#define EXTI_RTSR3_TR85            EXTI_RTSR3_TR85_Msk                         /*!< Rising trigger event configuration bit of line 85 */\n#define EXTI_RTSR3_TR86_Pos        (22U)\n#define EXTI_RTSR3_TR86_Msk        (0x1UL << EXTI_RTSR3_TR86_Pos)              /*!< 0x00400000 */\n#define EXTI_RTSR3_TR86            EXTI_RTSR3_TR86_Msk                         /*!< Rising trigger event configuration bit of line 86 */\n\n/******************  Bit definition for EXTI_FTSR3 register  *******************/\n#define EXTI_FTSR3_TR_Pos          (18U)\n#define EXTI_FTSR3_TR_Msk          (0x1DUL << EXTI_FTSR3_TR_Pos)               /*!< 0x00740000 */\n#define EXTI_FTSR3_TR              EXTI_FTSR3_TR_Msk                           /*!< Falling trigger event configuration bit */\n#define EXTI_FTSR3_TR82_Pos        (18U)\n#define EXTI_FTSR3_TR82_Msk        (0x1UL << EXTI_FTSR3_TR82_Pos)              /*!< 0x00040000 */\n#define EXTI_FTSR3_TR82            EXTI_FTSR3_TR82_Msk                         /*!< Falling trigger event configuration bit of line 82 */\n#define EXTI_FTSR3_TR84_Pos        (20U)\n#define EXTI_FTSR3_TR84_Msk        (0x1UL << EXTI_FTSR3_TR84_Pos)              /*!< 0x00100000 */\n#define EXTI_FTSR3_TR84            EXTI_FTSR3_TR84_Msk                         /*!< Falling trigger event configuration bit of line 84 */\n#define EXTI_FTSR3_TR85_Pos        (21U)\n#define EXTI_FTSR3_TR85_Msk        (0x1UL << EXTI_FTSR3_TR85_Pos)              /*!< 0x00200000 */\n#define EXTI_FTSR3_TR85            EXTI_FTSR3_TR85_Msk                         /*!< Falling trigger event configuration bit of line 85 */\n#define EXTI_FTSR3_TR86_Pos        (22U)\n#define EXTI_FTSR3_TR86_Msk        (0x1UL << EXTI_FTSR3_TR86_Pos)              /*!< 0x00400000 */\n#define EXTI_FTSR3_TR86            EXTI_FTSR3_TR86_Msk                         /*!< Falling trigger event configuration bit of line 86 */\n\n/******************  Bit definition for EXTI_SWIER3 register  ******************/\n#define EXTI_SWIER3_SWI_Pos        (18U)\n#define EXTI_SWIER3_SWI_Msk        (0x1DUL << EXTI_SWIER3_SWI_Pos)             /*!< 0x00740000 */\n#define EXTI_SWIER3_SWI            EXTI_SWIER3_SWI_Msk                         /*!< Software Interrupt event bit */\n#define EXTI_SWIER3_SWIER82_Pos    (18U)\n#define EXTI_SWIER3_SWIER82_Msk    (0x1UL << EXTI_SWIER3_SWIER82_Pos)          /*!< 0x00040000 */\n#define EXTI_SWIER3_SWIER82        EXTI_SWIER3_SWIER82_Msk                     /*!< Software Interrupt on line 82 */\n#define EXTI_SWIER3_SWIER84_Pos    (20U)\n#define EXTI_SWIER3_SWIER84_Msk    (0x1UL << EXTI_SWIER3_SWIER84_Pos)          /*!< 0x00100000 */\n#define EXTI_SWIER3_SWIER84        EXTI_SWIER3_SWIER84_Msk                     /*!< Software Interrupt on line 84 */\n#define EXTI_SWIER3_SWIER85_Pos    (21U)\n#define EXTI_SWIER3_SWIER85_Msk    (0x1UL << EXTI_SWIER3_SWIER85_Pos)          /*!< 0x00200000 */\n#define EXTI_SWIER3_SWIER85        EXTI_SWIER3_SWIER85_Msk                     /*!< Software Interrupt on line 85 */\n#define EXTI_SWIER3_SWIER86_Pos    (22U)\n#define EXTI_SWIER3_SWIER86_Msk    (0x1UL << EXTI_SWIER3_SWIER86_Pos)          /*!< 0x00400000 */\n#define EXTI_SWIER3_SWIER86        EXTI_SWIER3_SWIER86_Msk                     /*!< Software Interrupt on line 86 */\n\n/*******************  Bit definition for EXTI_IMR1 register  *******************/\n#define EXTI_IMR1_IM_Pos           (0U)\n#define EXTI_IMR1_IM_Msk           (0xFFFFFFFFUL << EXTI_IMR1_IM_Pos)          /*!< 0xFFFFFFFF */\n#define EXTI_IMR1_IM               EXTI_IMR1_IM_Msk                            /*!< Interrupt Mask */\n#define EXTI_IMR1_IM0_Pos          (0U)\n#define EXTI_IMR1_IM0_Msk          (0x1UL << EXTI_IMR1_IM0_Pos)                /*!< 0x00000001 */\n#define EXTI_IMR1_IM0              EXTI_IMR1_IM0_Msk                           /*!< Interrupt Mask on line 0 */\n#define EXTI_IMR1_IM1_Pos          (1U)\n#define EXTI_IMR1_IM1_Msk          (0x1UL << EXTI_IMR1_IM1_Pos)                /*!< 0x00000002 */\n#define EXTI_IMR1_IM1              EXTI_IMR1_IM1_Msk                           /*!< Interrupt Mask on line 1 */\n#define EXTI_IMR1_IM2_Pos          (2U)\n#define EXTI_IMR1_IM2_Msk          (0x1UL << EXTI_IMR1_IM2_Pos)                /*!< 0x00000004 */\n#define EXTI_IMR1_IM2              EXTI_IMR1_IM2_Msk                           /*!< Interrupt Mask on line 2 */\n#define EXTI_IMR1_IM3_Pos          (3U)\n#define EXTI_IMR1_IM3_Msk          (0x1UL << EXTI_IMR1_IM3_Pos)                /*!< 0x00000008 */\n#define EXTI_IMR1_IM3              EXTI_IMR1_IM3_Msk                           /*!< Interrupt Mask on line 3 */\n#define EXTI_IMR1_IM4_Pos          (4U)\n#define EXTI_IMR1_IM4_Msk          (0x1UL << EXTI_IMR1_IM4_Pos)                /*!< 0x00000010 */\n#define EXTI_IMR1_IM4              EXTI_IMR1_IM4_Msk                           /*!< Interrupt Mask on line 4 */\n#define EXTI_IMR1_IM5_Pos          (5U)\n#define EXTI_IMR1_IM5_Msk          (0x1UL << EXTI_IMR1_IM5_Pos)                /*!< 0x00000020 */\n#define EXTI_IMR1_IM5              EXTI_IMR1_IM5_Msk                           /*!< Interrupt Mask on line 5 */\n#define EXTI_IMR1_IM6_Pos          (6U)\n#define EXTI_IMR1_IM6_Msk          (0x1UL << EXTI_IMR1_IM6_Pos)                /*!< 0x00000040 */\n#define EXTI_IMR1_IM6              EXTI_IMR1_IM6_Msk                           /*!< Interrupt Mask on line 6 */\n#define EXTI_IMR1_IM7_Pos          (7U)\n#define EXTI_IMR1_IM7_Msk          (0x1UL << EXTI_IMR1_IM7_Pos)                /*!< 0x00000080 */\n#define EXTI_IMR1_IM7              EXTI_IMR1_IM7_Msk                           /*!< Interrupt Mask on line 7 */\n#define EXTI_IMR1_IM8_Pos          (8U)\n#define EXTI_IMR1_IM8_Msk          (0x1UL << EXTI_IMR1_IM8_Pos)                /*!< 0x00000100 */\n#define EXTI_IMR1_IM8              EXTI_IMR1_IM8_Msk                           /*!< Interrupt Mask on line 8 */\n#define EXTI_IMR1_IM9_Pos          (9U)\n#define EXTI_IMR1_IM9_Msk          (0x1UL << EXTI_IMR1_IM9_Pos)                /*!< 0x00000200 */\n#define EXTI_IMR1_IM9              EXTI_IMR1_IM9_Msk                           /*!< Interrupt Mask on line 9 */\n#define EXTI_IMR1_IM10_Pos         (10U)\n#define EXTI_IMR1_IM10_Msk         (0x1UL << EXTI_IMR1_IM10_Pos)               /*!< 0x00000400 */\n#define EXTI_IMR1_IM10             EXTI_IMR1_IM10_Msk                          /*!< Interrupt Mask on line 10 */\n#define EXTI_IMR1_IM11_Pos         (11U)\n#define EXTI_IMR1_IM11_Msk         (0x1UL << EXTI_IMR1_IM11_Pos)               /*!< 0x00000800 */\n#define EXTI_IMR1_IM11             EXTI_IMR1_IM11_Msk                          /*!< Interrupt Mask on line 11 */\n#define EXTI_IMR1_IM12_Pos         (12U)\n#define EXTI_IMR1_IM12_Msk         (0x1UL << EXTI_IMR1_IM12_Pos)               /*!< 0x00001000 */\n#define EXTI_IMR1_IM12             EXTI_IMR1_IM12_Msk                          /*!< Interrupt Mask on line 12 */\n#define EXTI_IMR1_IM13_Pos         (13U)\n#define EXTI_IMR1_IM13_Msk         (0x1UL << EXTI_IMR1_IM13_Pos)               /*!< 0x00002000 */\n#define EXTI_IMR1_IM13             EXTI_IMR1_IM13_Msk                          /*!< Interrupt Mask on line 13 */\n#define EXTI_IMR1_IM14_Pos         (14U)\n#define EXTI_IMR1_IM14_Msk         (0x1UL << EXTI_IMR1_IM14_Pos)               /*!< 0x00004000 */\n#define EXTI_IMR1_IM14             EXTI_IMR1_IM14_Msk                          /*!< Interrupt Mask on line 14 */\n#define EXTI_IMR1_IM15_Pos         (15U)\n#define EXTI_IMR1_IM15_Msk         (0x1UL << EXTI_IMR1_IM15_Pos)               /*!< 0x00008000 */\n#define EXTI_IMR1_IM15             EXTI_IMR1_IM15_Msk                          /*!< Interrupt Mask on line 15 */\n#define EXTI_IMR1_IM16_Pos         (16U)\n#define EXTI_IMR1_IM16_Msk         (0x1UL << EXTI_IMR1_IM16_Pos)               /*!< 0x00010000 */\n#define EXTI_IMR1_IM16             EXTI_IMR1_IM16_Msk                          /*!< Interrupt Mask on line 16 */\n#define EXTI_IMR1_IM17_Pos         (17U)\n#define EXTI_IMR1_IM17_Msk         (0x1UL << EXTI_IMR1_IM17_Pos)               /*!< 0x00020000 */\n#define EXTI_IMR1_IM17             EXTI_IMR1_IM17_Msk                          /*!< Interrupt Mask on line 17 */\n#define EXTI_IMR1_IM18_Pos         (18U)\n#define EXTI_IMR1_IM18_Msk         (0x1UL << EXTI_IMR1_IM18_Pos)               /*!< 0x00040000 */\n#define EXTI_IMR1_IM18             EXTI_IMR1_IM18_Msk                          /*!< Interrupt Mask on line 18 */\n#define EXTI_IMR1_IM19_Pos         (19U)\n#define EXTI_IMR1_IM19_Msk         (0x1UL << EXTI_IMR1_IM19_Pos)               /*!< 0x00080000 */\n#define EXTI_IMR1_IM19             EXTI_IMR1_IM19_Msk                          /*!< Interrupt Mask on line 19 */\n#define EXTI_IMR1_IM20_Pos         (20U)\n#define EXTI_IMR1_IM20_Msk         (0x1UL << EXTI_IMR1_IM20_Pos)               /*!< 0x00100000 */\n#define EXTI_IMR1_IM20             EXTI_IMR1_IM20_Msk                          /*!< Interrupt Mask on line 20 */\n#define EXTI_IMR1_IM21_Pos         (21U)\n#define EXTI_IMR1_IM21_Msk         (0x1UL << EXTI_IMR1_IM21_Pos)               /*!< 0x00200000 */\n#define EXTI_IMR1_IM21             EXTI_IMR1_IM21_Msk                          /*!< Interrupt Mask on line 21 */\n#define EXTI_IMR1_IM22_Pos         (22U)\n#define EXTI_IMR1_IM22_Msk         (0x1UL << EXTI_IMR1_IM22_Pos)               /*!< 0x00400000 */\n#define EXTI_IMR1_IM22             EXTI_IMR1_IM22_Msk                          /*!< Interrupt Mask on line 22 */\n#define EXTI_IMR1_IM23_Pos         (23U)\n#define EXTI_IMR1_IM23_Msk         (0x1UL << EXTI_IMR1_IM23_Pos)               /*!< 0x00800000 */\n#define EXTI_IMR1_IM23             EXTI_IMR1_IM23_Msk                          /*!< Interrupt Mask on line 23 */\n#define EXTI_IMR1_IM24_Pos         (24U)\n#define EXTI_IMR1_IM24_Msk         (0x1UL << EXTI_IMR1_IM24_Pos)               /*!< 0x01000000 */\n#define EXTI_IMR1_IM24             EXTI_IMR1_IM24_Msk                          /*!< Interrupt Mask on line 24 */\n#define EXTI_IMR1_IM25_Pos         (25U)\n#define EXTI_IMR1_IM25_Msk         (0x1UL << EXTI_IMR1_IM25_Pos)               /*!< 0x02000000 */\n#define EXTI_IMR1_IM25             EXTI_IMR1_IM25_Msk                          /*!< Interrupt Mask on line 25 */\n#define EXTI_IMR1_IM26_Pos         (26U)\n#define EXTI_IMR1_IM26_Msk         (0x1UL << EXTI_IMR1_IM26_Pos)               /*!< 0x04000000 */\n#define EXTI_IMR1_IM26             EXTI_IMR1_IM26_Msk                          /*!< Interrupt Mask on line 26 */\n#define EXTI_IMR1_IM27_Pos         (27U)\n#define EXTI_IMR1_IM27_Msk         (0x1UL << EXTI_IMR1_IM27_Pos)               /*!< 0x08000000 */\n#define EXTI_IMR1_IM27             EXTI_IMR1_IM27_Msk                          /*!< Interrupt Mask on line 27 */\n#define EXTI_IMR1_IM28_Pos         (28U)\n#define EXTI_IMR1_IM28_Msk         (0x1UL << EXTI_IMR1_IM28_Pos)               /*!< 0x10000000 */\n#define EXTI_IMR1_IM28             EXTI_IMR1_IM28_Msk                          /*!< Interrupt Mask on line 28 */\n#define EXTI_IMR1_IM29_Pos         (29U)\n#define EXTI_IMR1_IM29_Msk         (0x1UL << EXTI_IMR1_IM29_Pos)               /*!< 0x20000000 */\n#define EXTI_IMR1_IM29             EXTI_IMR1_IM29_Msk                          /*!< Interrupt Mask on line 29 */\n#define EXTI_IMR1_IM30_Pos         (30U)\n#define EXTI_IMR1_IM30_Msk         (0x1UL << EXTI_IMR1_IM30_Pos)               /*!< 0x40000000 */\n#define EXTI_IMR1_IM30             EXTI_IMR1_IM30_Msk                          /*!< Interrupt Mask on line 30 */\n#define EXTI_IMR1_IM31_Pos         (31U)\n#define EXTI_IMR1_IM31_Msk         (0x1UL << EXTI_IMR1_IM31_Pos)               /*!< 0x80000000 */\n#define EXTI_IMR1_IM31             EXTI_IMR1_IM31_Msk                          /*!< Interrupt Mask on line 31 */\n\n/*******************  Bit definition for EXTI_EMR1 register  *******************/\n#define EXTI_EMR1_EM_Pos           (0U)\n#define EXTI_EMR1_EM_Msk           (0xFFFFFFFFUL << EXTI_EMR1_EM_Pos)          /*!< 0xFFFFFFFF */\n#define EXTI_EMR1_EM               EXTI_EMR1_EM_Msk                            /*!< Event Mask */\n#define EXTI_EMR1_EM0_Pos          (0U)\n#define EXTI_EMR1_EM0_Msk          (0x1UL << EXTI_EMR1_EM0_Pos)                /*!< 0x00000001 */\n#define EXTI_EMR1_EM0              EXTI_EMR1_EM0_Msk                           /*!< Event Mask on line 0 */\n#define EXTI_EMR1_EM1_Pos          (1U)\n#define EXTI_EMR1_EM1_Msk          (0x1UL << EXTI_EMR1_EM1_Pos)                /*!< 0x00000002 */\n#define EXTI_EMR1_EM1              EXTI_EMR1_EM1_Msk                           /*!< Event Mask on line 1 */\n#define EXTI_EMR1_EM2_Pos          (2U)\n#define EXTI_EMR1_EM2_Msk          (0x1UL << EXTI_EMR1_EM2_Pos)                /*!< 0x00000004 */\n#define EXTI_EMR1_EM2              EXTI_EMR1_EM2_Msk                           /*!< Event Mask on line 2 */\n#define EXTI_EMR1_EM3_Pos          (3U)\n#define EXTI_EMR1_EM3_Msk          (0x1UL << EXTI_EMR1_EM3_Pos)                /*!< 0x00000008 */\n#define EXTI_EMR1_EM3              EXTI_EMR1_EM3_Msk                           /*!< Event Mask on line 3 */\n#define EXTI_EMR1_EM4_Pos          (4U)\n#define EXTI_EMR1_EM4_Msk          (0x1UL << EXTI_EMR1_EM4_Pos)                /*!< 0x00000010 */\n#define EXTI_EMR1_EM4              EXTI_EMR1_EM4_Msk                           /*!< Event Mask on line 4 */\n#define EXTI_EMR1_EM5_Pos          (5U)\n#define EXTI_EMR1_EM5_Msk          (0x1UL << EXTI_EMR1_EM5_Pos)                /*!< 0x00000020 */\n#define EXTI_EMR1_EM5              EXTI_EMR1_EM5_Msk                           /*!< Event Mask on line 5 */\n#define EXTI_EMR1_EM6_Pos          (6U)\n#define EXTI_EMR1_EM6_Msk          (0x1UL << EXTI_EMR1_EM6_Pos)                /*!< 0x00000040 */\n#define EXTI_EMR1_EM6              EXTI_EMR1_EM6_Msk                           /*!< Event Mask on line 6 */\n#define EXTI_EMR1_EM7_Pos          (7U)\n#define EXTI_EMR1_EM7_Msk          (0x1UL << EXTI_EMR1_EM7_Pos)                /*!< 0x00000080 */\n#define EXTI_EMR1_EM7              EXTI_EMR1_EM7_Msk                           /*!< Event Mask on line 7 */\n#define EXTI_EMR1_EM8_Pos          (8U)\n#define EXTI_EMR1_EM8_Msk          (0x1UL << EXTI_EMR1_EM8_Pos)                /*!< 0x00000100 */\n#define EXTI_EMR1_EM8              EXTI_EMR1_EM8_Msk                           /*!< Event Mask on line 8 */\n#define EXTI_EMR1_EM9_Pos          (9U)\n#define EXTI_EMR1_EM9_Msk          (0x1UL << EXTI_EMR1_EM9_Pos)                /*!< 0x00000200 */\n#define EXTI_EMR1_EM9              EXTI_EMR1_EM9_Msk                           /*!< Event Mask on line 9 */\n#define EXTI_EMR1_EM10_Pos         (10U)\n#define EXTI_EMR1_EM10_Msk         (0x1UL << EXTI_EMR1_EM10_Pos)               /*!< 0x00000400 */\n#define EXTI_EMR1_EM10             EXTI_EMR1_EM10_Msk                          /*!< Event Mask on line 10 */\n#define EXTI_EMR1_EM11_Pos         (11U)\n#define EXTI_EMR1_EM11_Msk         (0x1UL << EXTI_EMR1_EM11_Pos)               /*!< 0x00000800 */\n#define EXTI_EMR1_EM11             EXTI_EMR1_EM11_Msk                          /*!< Event Mask on line 11 */\n#define EXTI_EMR1_EM12_Pos         (12U)\n#define EXTI_EMR1_EM12_Msk         (0x1UL << EXTI_EMR1_EM12_Pos)               /*!< 0x00001000 */\n#define EXTI_EMR1_EM12             EXTI_EMR1_EM12_Msk                          /*!< Event Mask on line 12 */\n#define EXTI_EMR1_EM13_Pos         (13U)\n#define EXTI_EMR1_EM13_Msk         (0x1UL << EXTI_EMR1_EM13_Pos)               /*!< 0x00002000 */\n#define EXTI_EMR1_EM13             EXTI_EMR1_EM13_Msk                          /*!< Event Mask on line 13 */\n#define EXTI_EMR1_EM14_Pos         (14U)\n#define EXTI_EMR1_EM14_Msk         (0x1UL << EXTI_EMR1_EM14_Pos)               /*!< 0x00004000 */\n#define EXTI_EMR1_EM14             EXTI_EMR1_EM14_Msk                          /*!< Event Mask on line 14 */\n#define EXTI_EMR1_EM15_Pos         (15U)\n#define EXTI_EMR1_EM15_Msk         (0x1UL << EXTI_EMR1_EM15_Pos)               /*!< 0x00008000 */\n#define EXTI_EMR1_EM15             EXTI_EMR1_EM15_Msk                          /*!< Event Mask on line 15 */\n#define EXTI_EMR1_EM16_Pos         (16U)\n#define EXTI_EMR1_EM16_Msk         (0x1UL << EXTI_EMR1_EM16_Pos)               /*!< 0x00010000 */\n#define EXTI_EMR1_EM16             EXTI_EMR1_EM16_Msk                          /*!< Event Mask on line 16 */\n#define EXTI_EMR1_EM17_Pos         (17U)\n#define EXTI_EMR1_EM17_Msk         (0x1UL << EXTI_EMR1_EM17_Pos)               /*!< 0x00020000 */\n#define EXTI_EMR1_EM17             EXTI_EMR1_EM17_Msk                          /*!< Event Mask on line 17 */\n#define EXTI_EMR1_EM18_Pos         (18U)\n#define EXTI_EMR1_EM18_Msk         (0x1UL << EXTI_EMR1_EM18_Pos)               /*!< 0x00040000 */\n#define EXTI_EMR1_EM18             EXTI_EMR1_EM18_Msk                          /*!< Event Mask on line 18 */\n#define EXTI_EMR1_EM20_Pos         (20U)\n#define EXTI_EMR1_EM20_Msk         (0x1UL << EXTI_EMR1_EM20_Pos)               /*!< 0x00100000 */\n#define EXTI_EMR1_EM20             EXTI_EMR1_EM20_Msk                          /*!< Event Mask on line 20 */\n#define EXTI_EMR1_EM21_Pos         (21U)\n#define EXTI_EMR1_EM21_Msk         (0x1UL << EXTI_EMR1_EM21_Pos)               /*!< 0x00200000 */\n#define EXTI_EMR1_EM21             EXTI_EMR1_EM21_Msk                          /*!< Event Mask on line 21 */\n#define EXTI_EMR1_EM22_Pos         (22U)\n#define EXTI_EMR1_EM22_Msk         (0x1UL << EXTI_EMR1_EM22_Pos)               /*!< 0x00400000 */\n#define EXTI_EMR1_EM22             EXTI_EMR1_EM22_Msk                          /*!< Event Mask on line 22 */\n#define EXTI_EMR1_EM23_Pos         (23U)\n#define EXTI_EMR1_EM23_Msk         (0x1UL << EXTI_EMR1_EM23_Pos)               /*!< 0x00800000 */\n#define EXTI_EMR1_EM23             EXTI_EMR1_EM23_Msk                          /*!< Event Mask on line 23 */\n#define EXTI_EMR1_EM24_Pos         (24U)\n#define EXTI_EMR1_EM24_Msk         (0x1UL << EXTI_EMR1_EM24_Pos)               /*!< 0x01000000 */\n#define EXTI_EMR1_EM24             EXTI_EMR1_EM24_Msk                          /*!< Event Mask on line 24 */\n#define EXTI_EMR1_EM25_Pos         (25U)\n#define EXTI_EMR1_EM25_Msk         (0x1UL << EXTI_EMR1_EM25_Pos)               /*!< 0x02000000 */\n#define EXTI_EMR1_EM25             EXTI_EMR1_EM25_Msk                          /*!< Event Mask on line 25 */\n#define EXTI_EMR1_EM26_Pos         (26U)\n#define EXTI_EMR1_EM26_Msk         (0x1UL << EXTI_EMR1_EM26_Pos)               /*!< 0x04000000 */\n#define EXTI_EMR1_EM26             EXTI_EMR1_EM26_Msk                          /*!< Event Mask on line 26 */\n#define EXTI_EMR1_EM27_Pos         (27U)\n#define EXTI_EMR1_EM27_Msk         (0x1UL << EXTI_EMR1_EM27_Pos)               /*!< 0x08000000 */\n#define EXTI_EMR1_EM27             EXTI_EMR1_EM27_Msk                          /*!< Event Mask on line 27 */\n#define EXTI_EMR1_EM28_Pos         (28U)\n#define EXTI_EMR1_EM28_Msk         (0x1UL << EXTI_EMR1_EM28_Pos)               /*!< 0x10000000 */\n#define EXTI_EMR1_EM28             EXTI_EMR1_EM28_Msk                          /*!< Event Mask on line 28 */\n#define EXTI_EMR1_EM29_Pos         (29U)\n#define EXTI_EMR1_EM29_Msk         (0x1UL << EXTI_EMR1_EM29_Pos)               /*!< 0x20000000 */\n#define EXTI_EMR1_EM29             EXTI_EMR1_EM29_Msk                          /*!< Event Mask on line 29 */\n#define EXTI_EMR1_EM30_Pos         (30U)\n#define EXTI_EMR1_EM30_Msk         (0x1UL << EXTI_EMR1_EM30_Pos)               /*!< 0x40000000 */\n#define EXTI_EMR1_EM30             EXTI_EMR1_EM30_Msk                          /*!< Event Mask on line 30 */\n#define EXTI_EMR1_EM31_Pos         (31U)\n#define EXTI_EMR1_EM31_Msk         (0x1UL << EXTI_EMR1_EM31_Pos)               /*!< 0x80000000 */\n#define EXTI_EMR1_EM31             EXTI_EMR1_EM31_Msk                          /*!< Event Mask on line 31 */\n\n/*******************  Bit definition for EXTI_PR1 register  ********************/\n#define EXTI_PR1_PR_Pos            (0U)\n#define EXTI_PR1_PR_Msk            (0x3FFFFFUL << EXTI_PR1_PR_Pos)             /*!< 0x003FFFFF */\n#define EXTI_PR1_PR                EXTI_PR1_PR_Msk                             /*!< Pending bit */\n#define EXTI_PR1_PR0_Pos           (0U)\n#define EXTI_PR1_PR0_Msk           (0x1UL << EXTI_PR1_PR0_Pos)                 /*!< 0x00000001 */\n#define EXTI_PR1_PR0               EXTI_PR1_PR0_Msk                            /*!< Pending bit for line 0 */\n#define EXTI_PR1_PR1_Pos           (1U)\n#define EXTI_PR1_PR1_Msk           (0x1UL << EXTI_PR1_PR1_Pos)                 /*!< 0x00000002 */\n#define EXTI_PR1_PR1               EXTI_PR1_PR1_Msk                            /*!< Pending bit for line 1 */\n#define EXTI_PR1_PR2_Pos           (2U)\n#define EXTI_PR1_PR2_Msk           (0x1UL << EXTI_PR1_PR2_Pos)                 /*!< 0x00000004 */\n#define EXTI_PR1_PR2               EXTI_PR1_PR2_Msk                            /*!< Pending bit for line 2 */\n#define EXTI_PR1_PR3_Pos           (3U)\n#define EXTI_PR1_PR3_Msk           (0x1UL << EXTI_PR1_PR3_Pos)                 /*!< 0x00000008 */\n#define EXTI_PR1_PR3               EXTI_PR1_PR3_Msk                            /*!< Pending bit for line 3 */\n#define EXTI_PR1_PR4_Pos           (4U)\n#define EXTI_PR1_PR4_Msk           (0x1UL << EXTI_PR1_PR4_Pos)                 /*!< 0x00000010 */\n#define EXTI_PR1_PR4               EXTI_PR1_PR4_Msk                            /*!< Pending bit for line 4 */\n#define EXTI_PR1_PR5_Pos           (5U)\n#define EXTI_PR1_PR5_Msk           (0x1UL << EXTI_PR1_PR5_Pos)                 /*!< 0x00000020 */\n#define EXTI_PR1_PR5               EXTI_PR1_PR5_Msk                            /*!< Pending bit for line 5 */\n#define EXTI_PR1_PR6_Pos           (6U)\n#define EXTI_PR1_PR6_Msk           (0x1UL << EXTI_PR1_PR6_Pos)                 /*!< 0x00000040 */\n#define EXTI_PR1_PR6               EXTI_PR1_PR6_Msk                            /*!< Pending bit for line 6 */\n#define EXTI_PR1_PR7_Pos           (7U)\n#define EXTI_PR1_PR7_Msk           (0x1UL << EXTI_PR1_PR7_Pos)                 /*!< 0x00000080 */\n#define EXTI_PR1_PR7               EXTI_PR1_PR7_Msk                            /*!< Pending bit for line 7 */\n#define EXTI_PR1_PR8_Pos           (8U)\n#define EXTI_PR1_PR8_Msk           (0x1UL << EXTI_PR1_PR8_Pos)                 /*!< 0x00000100 */\n#define EXTI_PR1_PR8               EXTI_PR1_PR8_Msk                            /*!< Pending bit for line 8 */\n#define EXTI_PR1_PR9_Pos           (9U)\n#define EXTI_PR1_PR9_Msk           (0x1UL << EXTI_PR1_PR9_Pos)                 /*!< 0x00000200 */\n#define EXTI_PR1_PR9               EXTI_PR1_PR9_Msk                            /*!< Pending bit for line 9 */\n#define EXTI_PR1_PR10_Pos          (10U)\n#define EXTI_PR1_PR10_Msk          (0x1UL << EXTI_PR1_PR10_Pos)                /*!< 0x00000400 */\n#define EXTI_PR1_PR10              EXTI_PR1_PR10_Msk                           /*!< Pending bit for line 10 */\n#define EXTI_PR1_PR11_Pos          (11U)\n#define EXTI_PR1_PR11_Msk          (0x1UL << EXTI_PR1_PR11_Pos)                /*!< 0x00000800 */\n#define EXTI_PR1_PR11              EXTI_PR1_PR11_Msk                           /*!< Pending bit for line 11 */\n#define EXTI_PR1_PR12_Pos          (12U)\n#define EXTI_PR1_PR12_Msk          (0x1UL << EXTI_PR1_PR12_Pos)                /*!< 0x00001000 */\n#define EXTI_PR1_PR12              EXTI_PR1_PR12_Msk                           /*!< Pending bit for line 12 */\n#define EXTI_PR1_PR13_Pos          (13U)\n#define EXTI_PR1_PR13_Msk          (0x1UL << EXTI_PR1_PR13_Pos)                /*!< 0x00002000 */\n#define EXTI_PR1_PR13              EXTI_PR1_PR13_Msk                           /*!< Pending bit for line 13 */\n#define EXTI_PR1_PR14_Pos          (14U)\n#define EXTI_PR1_PR14_Msk          (0x1UL << EXTI_PR1_PR14_Pos)                /*!< 0x00004000 */\n#define EXTI_PR1_PR14              EXTI_PR1_PR14_Msk                           /*!< Pending bit for line 14 */\n#define EXTI_PR1_PR15_Pos          (15U)\n#define EXTI_PR1_PR15_Msk          (0x1UL << EXTI_PR1_PR15_Pos)                /*!< 0x00008000 */\n#define EXTI_PR1_PR15              EXTI_PR1_PR15_Msk                           /*!< Pending bit for line 15 */\n#define EXTI_PR1_PR16_Pos          (16U)\n#define EXTI_PR1_PR16_Msk          (0x1UL << EXTI_PR1_PR16_Pos)                /*!< 0x00010000 */\n#define EXTI_PR1_PR16              EXTI_PR1_PR16_Msk                           /*!< Pending bit for line 16 */\n#define EXTI_PR1_PR17_Pos          (17U)\n#define EXTI_PR1_PR17_Msk          (0x1UL << EXTI_PR1_PR17_Pos)                /*!< 0x00020000 */\n#define EXTI_PR1_PR17              EXTI_PR1_PR17_Msk                           /*!< Pending bit for line 17 */\n#define EXTI_PR1_PR18_Pos          (18U)\n#define EXTI_PR1_PR18_Msk          (0x1UL << EXTI_PR1_PR18_Pos)                /*!< 0x00040000 */\n#define EXTI_PR1_PR18              EXTI_PR1_PR18_Msk                           /*!< Pending bit for line 18 */\n#define EXTI_PR1_PR19_Pos          (19U)\n#define EXTI_PR1_PR19_Msk          (0x1UL << EXTI_PR1_PR19_Pos)                /*!< 0x00080000 */\n#define EXTI_PR1_PR19              EXTI_PR1_PR19_Msk                           /*!< Pending bit for line 19 */\n#define EXTI_PR1_PR20_Pos          (20U)\n#define EXTI_PR1_PR20_Msk          (0x1UL << EXTI_PR1_PR20_Pos)                /*!< 0x00100000 */\n#define EXTI_PR1_PR20              EXTI_PR1_PR20_Msk                           /*!< Pending bit for line 20 */\n#define EXTI_PR1_PR21_Pos          (21U)\n#define EXTI_PR1_PR21_Msk          (0x1UL << EXTI_PR1_PR21_Pos)                /*!< 0x00200000 */\n#define EXTI_PR1_PR21              EXTI_PR1_PR21_Msk                           /*!< Pending bit for line 21 */\n\n/*******************  Bit definition for EXTI_IMR2 register  *******************/\n#define EXTI_IMR2_IM_Pos           (0U)\n#define EXTI_IMR2_IM_Msk           (0xFFFFDFFFUL << EXTI_IMR2_IM_Pos)          /*!< 0xFFFFDFFF */\n#define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk                            /*!< Interrupt Mask */\n#define EXTI_IMR2_IM32_Pos         (0U)\n#define EXTI_IMR2_IM32_Msk         (0x1UL << EXTI_IMR2_IM32_Pos)               /*!< 0x00000001 */\n#define EXTI_IMR2_IM32             EXTI_IMR2_IM32_Msk                          /*!< Interrupt Mask on line 32 */\n#define EXTI_IMR2_IM33_Pos         (1U)\n#define EXTI_IMR2_IM33_Msk         (0x1UL << EXTI_IMR2_IM33_Pos)               /*!< 0x00000002 */\n#define EXTI_IMR2_IM33             EXTI_IMR2_IM33_Msk                          /*!< Interrupt Mask on line 33 */\n#define EXTI_IMR2_IM34_Pos         (2U)\n#define EXTI_IMR2_IM34_Msk         (0x1UL << EXTI_IMR2_IM34_Pos)               /*!< 0x00000004 */\n#define EXTI_IMR2_IM34             EXTI_IMR2_IM34_Msk                          /*!< Interrupt Mask on line 34 */\n#define EXTI_IMR2_IM35_Pos         (3U)\n#define EXTI_IMR2_IM35_Msk         (0x1UL << EXTI_IMR2_IM35_Pos)               /*!< 0x00000008 */\n#define EXTI_IMR2_IM35             EXTI_IMR2_IM35_Msk                          /*!< Interrupt Mask on line 35 */\n#define EXTI_IMR2_IM36_Pos         (4U)\n#define EXTI_IMR2_IM36_Msk         (0x1UL << EXTI_IMR2_IM36_Pos)               /*!< 0x00000010 */\n#define EXTI_IMR2_IM36             EXTI_IMR2_IM36_Msk                          /*!< Interrupt Mask on line 36 */\n#define EXTI_IMR2_IM37_Pos         (5U)\n#define EXTI_IMR2_IM37_Msk         (0x1UL << EXTI_IMR2_IM37_Pos)               /*!< 0x00000020 */\n#define EXTI_IMR2_IM37             EXTI_IMR2_IM37_Msk                          /*!< Interrupt Mask on line 37 */\n#define EXTI_IMR2_IM38_Pos         (6U)\n#define EXTI_IMR2_IM38_Msk         (0x1UL << EXTI_IMR2_IM38_Pos)               /*!< 0x00000040 */\n#define EXTI_IMR2_IM38             EXTI_IMR2_IM38_Msk                          /*!< Interrupt Mask on line 38 */\n#define EXTI_IMR2_IM39_Pos         (7U)\n#define EXTI_IMR2_IM39_Msk         (0x1UL << EXTI_IMR2_IM39_Pos)               /*!< 0x00000080 */\n#define EXTI_IMR2_IM39             EXTI_IMR2_IM39_Msk                          /*!< Interrupt Mask on line 39 */\n#define EXTI_IMR2_IM40_Pos         (8U)\n#define EXTI_IMR2_IM40_Msk         (0x1UL << EXTI_IMR2_IM40_Pos)               /*!< 0x00000100 */\n#define EXTI_IMR2_IM40             EXTI_IMR2_IM40_Msk                          /*!< Interrupt Mask on line 40 */\n#define EXTI_IMR2_IM41_Pos         (9U)\n#define EXTI_IMR2_IM41_Msk         (0x1UL << EXTI_IMR2_IM41_Pos)               /*!< 0x00000200 */\n#define EXTI_IMR2_IM41             EXTI_IMR2_IM41_Msk                          /*!< Interrupt Mask on line 41 */\n#define EXTI_IMR2_IM42_Pos         (10U)\n#define EXTI_IMR2_IM42_Msk         (0x1UL << EXTI_IMR2_IM42_Pos)               /*!< 0x00000400 */\n#define EXTI_IMR2_IM42             EXTI_IMR2_IM42_Msk                          /*!< Interrupt Mask on line 42 */\n#define EXTI_IMR2_IM43_Pos         (11U)\n#define EXTI_IMR2_IM43_Msk         (0x1UL << EXTI_IMR2_IM43_Pos)               /*!< 0x00000800 */\n#define EXTI_IMR2_IM43             EXTI_IMR2_IM43_Msk                          /*!< Interrupt Mask on line 43 */\n#define EXTI_IMR2_IM44_Pos         (12U)\n#define EXTI_IMR2_IM44_Msk         (0x1UL << EXTI_IMR2_IM44_Pos)               /*!< 0x00001000 */\n#define EXTI_IMR2_IM44             EXTI_IMR2_IM44_Msk                          /*!< Interrupt Mask on line 44 */\n#define EXTI_IMR2_IM46_Pos         (14U)\n#define EXTI_IMR2_IM46_Msk         (0x1UL << EXTI_IMR2_IM46_Pos)               /*!< 0x00004000 */\n#define EXTI_IMR2_IM46             EXTI_IMR2_IM46_Msk                          /*!< Interrupt Mask on line 46 */\n#define EXTI_IMR2_IM47_Pos         (15U)\n#define EXTI_IMR2_IM47_Msk         (0x1UL << EXTI_IMR2_IM47_Pos)               /*!< 0x00008000 */\n#define EXTI_IMR2_IM47             EXTI_IMR2_IM47_Msk                          /*!< Interrupt Mask on line 47 */\n#define EXTI_IMR2_IM48_Pos         (16U)\n#define EXTI_IMR2_IM48_Msk         (0x1UL << EXTI_IMR2_IM48_Pos)               /*!< 0x00010000 */\n#define EXTI_IMR2_IM48             EXTI_IMR2_IM48_Msk                          /*!< Interrupt Mask on line 48 */\n#define EXTI_IMR2_IM49_Pos         (17U)\n#define EXTI_IMR2_IM49_Msk         (0x1UL << EXTI_IMR2_IM49_Pos)               /*!< 0x00020000 */\n#define EXTI_IMR2_IM49             EXTI_IMR2_IM49_Msk                          /*!< Interrupt Mask on line 49 */\n#define EXTI_IMR2_IM50_Pos         (18U)\n#define EXTI_IMR2_IM50_Msk         (0x1UL << EXTI_IMR2_IM50_Pos)               /*!< 0x00040000 */\n#define EXTI_IMR2_IM50             EXTI_IMR2_IM50_Msk                          /*!< Interrupt Mask on line 50 */\n#define EXTI_IMR2_IM51_Pos         (19U)\n#define EXTI_IMR2_IM51_Msk         (0x1UL << EXTI_IMR2_IM51_Pos)               /*!< 0x00080000 */\n#define EXTI_IMR2_IM51             EXTI_IMR2_IM51_Msk                          /*!< Interrupt Mask on line 51 */\n#define EXTI_IMR2_IM52_Pos         (20U)\n#define EXTI_IMR2_IM52_Msk         (0x1UL << EXTI_IMR2_IM52_Pos)               /*!< 0x00100000 */\n#define EXTI_IMR2_IM52             EXTI_IMR2_IM52_Msk                          /*!< Interrupt Mask on line 52 */\n#define EXTI_IMR2_IM53_Pos         (21U)\n#define EXTI_IMR2_IM53_Msk         (0x1UL << EXTI_IMR2_IM53_Pos)               /*!< 0x00200000 */\n#define EXTI_IMR2_IM53             EXTI_IMR2_IM53_Msk                          /*!< Interrupt Mask on line 53 */\n#define EXTI_IMR2_IM54_Pos         (22U)\n#define EXTI_IMR2_IM54_Msk         (0x1UL << EXTI_IMR2_IM54_Pos)               /*!< 0x00400000 */\n#define EXTI_IMR2_IM54             EXTI_IMR2_IM54_Msk                          /*!< Interrupt Mask on line 54 */\n#define EXTI_IMR2_IM55_Pos         (23U)\n#define EXTI_IMR2_IM55_Msk         (0x1UL << EXTI_IMR2_IM55_Pos)               /*!< 0x00800000 */\n#define EXTI_IMR2_IM55             EXTI_IMR2_IM55_Msk                          /*!< Interrupt Mask on line 55 */\n#define EXTI_IMR2_IM56_Pos         (24U)\n#define EXTI_IMR2_IM56_Msk         (0x1UL << EXTI_IMR2_IM56_Pos)               /*!< 0x01000000 */\n#define EXTI_IMR2_IM56             EXTI_IMR2_IM56_Msk                          /*!< Interrupt Mask on line 56 */\n#define EXTI_IMR2_IM57_Pos         (25U)\n#define EXTI_IMR2_IM57_Msk         (0x1UL << EXTI_IMR2_IM57_Pos)               /*!< 0x02000000 */\n#define EXTI_IMR2_IM57             EXTI_IMR2_IM57_Msk                          /*!< Interrupt Mask on line 57 */\n#define EXTI_IMR2_IM58_Pos         (26U)\n#define EXTI_IMR2_IM58_Msk         (0x1UL << EXTI_IMR2_IM58_Pos)               /*!< 0x04000000 */\n#define EXTI_IMR2_IM58             EXTI_IMR2_IM58_Msk                          /*!< Interrupt Mask on line 58 */\n#define EXTI_IMR2_IM59_Pos         (27U)\n#define EXTI_IMR2_IM59_Msk         (0x1UL << EXTI_IMR2_IM59_Pos)               /*!< 0x08000000 */\n#define EXTI_IMR2_IM59             EXTI_IMR2_IM59_Msk                          /*!< Interrupt Mask on line 59 */\n#define EXTI_IMR2_IM60_Pos         (28U)\n#define EXTI_IMR2_IM60_Msk         (0x1UL << EXTI_IMR2_IM60_Pos)               /*!< 0x10000000 */\n#define EXTI_IMR2_IM60             EXTI_IMR2_IM60_Msk                          /*!< Interrupt Mask on line 60 */\n#define EXTI_IMR2_IM61_Pos         (29U)\n#define EXTI_IMR2_IM61_Msk         (0x1UL << EXTI_IMR2_IM61_Pos)               /*!< 0x20000000 */\n#define EXTI_IMR2_IM61             EXTI_IMR2_IM61_Msk                          /*!< Interrupt Mask on line 61 */\n#define EXTI_IMR2_IM62_Pos         (30U)\n#define EXTI_IMR2_IM62_Msk         (0x1UL << EXTI_IMR2_IM62_Pos)               /*!< 0x40000000 */\n#define EXTI_IMR2_IM62             EXTI_IMR2_IM62_Msk                          /*!< Interrupt Mask on line 62 */\n#define EXTI_IMR2_IM63_Pos         (31U)\n#define EXTI_IMR2_IM63_Msk         (0x1UL << EXTI_IMR2_IM63_Pos)               /*!< 0x80000000 */\n#define EXTI_IMR2_IM63             EXTI_IMR2_IM63_Msk                          /*!< Interrupt Mask on line 63 */\n\n/*******************  Bit definition for EXTI_EMR2 register  *******************/\n#define EXTI_EMR2_EM_Pos           (0U)\n#define EXTI_EMR2_EM_Msk           (0xFFFFDFFFUL << EXTI_EMR2_EM_Pos)          /*!< 0xFFFFDFFF */\n#define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            /*!< Event Mask */\n#define EXTI_EMR2_EM32_Pos         (0U)\n#define EXTI_EMR2_EM32_Msk         (0x1UL << EXTI_EMR2_EM32_Pos)               /*!< 0x00000001 */\n#define EXTI_EMR2_EM32             EXTI_EMR2_EM32_Msk                          /*!< Event Mask on line 32*/\n#define EXTI_EMR2_EM33_Pos         (1U)\n#define EXTI_EMR2_EM33_Msk         (0x1UL << EXTI_EMR2_EM33_Pos)               /*!< 0x00000002 */\n#define EXTI_EMR2_EM33             EXTI_EMR2_EM33_Msk                          /*!< Event Mask on line 33*/\n#define EXTI_EMR2_EM34_Pos         (2U)\n#define EXTI_EMR2_EM34_Msk         (0x1UL << EXTI_EMR2_EM34_Pos)               /*!< 0x00000004 */\n#define EXTI_EMR2_EM34             EXTI_EMR2_EM34_Msk                          /*!< Event Mask on line 34*/\n#define EXTI_EMR2_EM35_Pos         (3U)\n#define EXTI_EMR2_EM35_Msk         (0x1UL << EXTI_EMR2_EM35_Pos)               /*!< 0x00000008 */\n#define EXTI_EMR2_EM35             EXTI_EMR2_EM35_Msk                          /*!< Event Mask on line 35*/\n#define EXTI_EMR2_EM36_Pos         (4U)\n#define EXTI_EMR2_EM36_Msk         (0x1UL << EXTI_EMR2_EM36_Pos)               /*!< 0x00000010 */\n#define EXTI_EMR2_EM36             EXTI_EMR2_EM36_Msk                          /*!< Event Mask on line 36*/\n#define EXTI_EMR2_EM37_Pos         (5U)\n#define EXTI_EMR2_EM37_Msk         (0x1UL << EXTI_EMR2_EM37_Pos)               /*!< 0x00000020 */\n#define EXTI_EMR2_EM37             EXTI_EMR2_EM37_Msk                          /*!< Event Mask on line 37*/\n#define EXTI_EMR2_EM38_Pos         (6U)\n#define EXTI_EMR2_EM38_Msk         (0x1UL << EXTI_EMR2_EM38_Pos)               /*!< 0x00000040 */\n#define EXTI_EMR2_EM38             EXTI_EMR2_EM38_Msk                          /*!< Event Mask on line 38*/\n#define EXTI_EMR2_EM39_Pos         (7U)\n#define EXTI_EMR2_EM39_Msk         (0x1UL << EXTI_EMR2_EM39_Pos)               /*!< 0x00000080 */\n#define EXTI_EMR2_EM39             EXTI_EMR2_EM39_Msk                          /*!< Event Mask on line 39*/\n#define EXTI_EMR2_EM40_Pos         (8U)\n#define EXTI_EMR2_EM40_Msk         (0x1UL << EXTI_EMR2_EM40_Pos)               /*!< 0x00000100 */\n#define EXTI_EMR2_EM40             EXTI_EMR2_EM40_Msk                          /*!< Event Mask on line 40*/\n#define EXTI_EMR2_EM41_Pos         (9U)\n#define EXTI_EMR2_EM41_Msk         (0x1UL << EXTI_EMR2_EM41_Pos)               /*!< 0x00000200 */\n#define EXTI_EMR2_EM41             EXTI_EMR2_EM41_Msk                          /*!< Event Mask on line 41*/\n#define EXTI_EMR2_EM42_Pos         (10U)\n#define EXTI_EMR2_EM42_Msk         (0x1UL << EXTI_EMR2_EM42_Pos)               /*!< 0x00000400 */\n#define EXTI_EMR2_EM42             EXTI_EMR2_EM42_Msk                          /*!< Event Mask on line 42 */\n#define EXTI_EMR2_EM43_Pos         (11U)\n#define EXTI_EMR2_EM43_Msk         (0x1UL << EXTI_EMR2_EM43_Pos)               /*!< 0x00000800 */\n#define EXTI_EMR2_EM43             EXTI_EMR2_EM43_Msk                          /*!< Event Mask on line 43 */\n#define EXTI_EMR2_EM44_Pos         (12U)\n#define EXTI_EMR2_EM44_Msk         (0x1UL << EXTI_EMR2_EM44_Pos)               /*!< 0x00001000 */\n#define EXTI_EMR2_EM44             EXTI_EMR2_EM44_Msk                          /*!< Event Mask on line 44 */\n#define EXTI_EMR2_EM46_Pos         (14U)\n#define EXTI_EMR2_EM46_Msk         (0x1UL << EXTI_EMR2_EM46_Pos)               /*!< 0x00004000 */\n#define EXTI_EMR2_EM46             EXTI_EMR2_EM46_Msk                          /*!< Event Mask on line 46 */\n#define EXTI_EMR2_EM47_Pos         (15U)\n#define EXTI_EMR2_EM47_Msk         (0x1UL << EXTI_EMR2_EM47_Pos)               /*!< 0x00008000 */\n#define EXTI_EMR2_EM47             EXTI_EMR2_EM47_Msk                          /*!< Event Mask on line 47 */\n#define EXTI_EMR2_EM48_Pos         (16U)\n#define EXTI_EMR2_EM48_Msk         (0x1UL << EXTI_EMR2_EM48_Pos)               /*!< 0x00010000 */\n#define EXTI_EMR2_EM48             EXTI_EMR2_EM48_Msk                          /*!< Event Mask on line 48 */\n#define EXTI_EMR2_EM49_Pos         (17U)\n#define EXTI_EMR2_EM49_Msk         (0x1UL << EXTI_EMR2_EM49_Pos)               /*!< 0x00020000 */\n#define EXTI_EMR2_EM49             EXTI_EMR2_EM49_Msk                          /*!< Event Mask on line 49 */\n#define EXTI_EMR2_EM50_Pos         (18U)\n#define EXTI_EMR2_EM50_Msk         (0x1UL << EXTI_EMR2_EM50_Pos)               /*!< 0x00040000 */\n#define EXTI_EMR2_EM50             EXTI_EMR2_EM50_Msk                          /*!< Event Mask on line 50 */\n#define EXTI_EMR2_EM51_Pos         (19U)\n#define EXTI_EMR2_EM51_Msk         (0x1UL << EXTI_EMR2_EM51_Pos)               /*!< 0x00080000 */\n#define EXTI_EMR2_EM51             EXTI_EMR2_EM51_Msk                          /*!< Event Mask on line 51 */\n#define EXTI_EMR2_EM52_Pos         (20U)\n#define EXTI_EMR2_EM52_Msk         (0x1UL << EXTI_EMR2_EM52_Pos)               /*!< 0x00100000 */\n#define EXTI_EMR2_EM52             EXTI_EMR2_EM52_Msk                          /*!< Event Mask on line 52 */\n#define EXTI_EMR2_EM53_Pos         (21U)\n#define EXTI_EMR2_EM53_Msk         (0x1UL << EXTI_EMR2_EM53_Pos)               /*!< 0x00200000 */\n#define EXTI_EMR2_EM53             EXTI_EMR2_EM53_Msk                          /*!< Event Mask on line 53 */\n#define EXTI_EMR2_EM54_Pos         (22U)\n#define EXTI_EMR2_EM54_Msk         (0x1UL << EXTI_EMR2_EM54_Pos)               /*!< 0x00400000 */\n#define EXTI_EMR2_EM54             EXTI_EMR2_EM54_Msk                          /*!< Event Mask on line 54 */\n#define EXTI_EMR2_EM55_Pos         (23U)\n#define EXTI_EMR2_EM55_Msk         (0x1UL << EXTI_EMR2_EM55_Pos)               /*!< 0x00800000 */\n#define EXTI_EMR2_EM55             EXTI_EMR2_EM55_Msk                          /*!< Event Mask on line 55 */\n#define EXTI_EMR2_EM56_Pos         (24U)\n#define EXTI_EMR2_EM56_Msk         (0x1UL << EXTI_EMR2_EM56_Pos)               /*!< 0x01000000 */\n#define EXTI_EMR2_EM56             EXTI_EMR2_EM56_Msk                          /*!< Event Mask on line 56 */\n#define EXTI_EMR2_EM57_Pos         (25U)\n#define EXTI_EMR2_EM57_Msk         (0x1UL << EXTI_EMR2_EM57_Pos)               /*!< 0x02000000 */\n#define EXTI_EMR2_EM57             EXTI_EMR2_EM57_Msk                          /*!< Event Mask on line 57 */\n#define EXTI_EMR2_EM58_Pos         (26U)\n#define EXTI_EMR2_EM58_Msk         (0x1UL << EXTI_EMR2_EM58_Pos)               /*!< 0x04000000 */\n#define EXTI_EMR2_EM58             EXTI_EMR2_EM58_Msk                          /*!< Event Mask on line 58 */\n#define EXTI_EMR2_EM59_Pos         (27U)\n#define EXTI_EMR2_EM59_Msk         (0x1UL << EXTI_EMR2_EM59_Pos)               /*!< 0x08000000 */\n#define EXTI_EMR2_EM59             EXTI_EMR2_EM59_Msk                          /*!< Event Mask on line 59 */\n#define EXTI_EMR2_EM60_Pos         (28U)\n#define EXTI_EMR2_EM60_Msk         (0x1UL << EXTI_EMR2_EM60_Pos)               /*!< 0x10000000 */\n#define EXTI_EMR2_EM60             EXTI_EMR2_EM60_Msk                          /*!< Event Mask on line 60 */\n#define EXTI_EMR2_EM61_Pos         (29U)\n#define EXTI_EMR2_EM61_Msk         (0x1UL << EXTI_EMR2_EM61_Pos)               /*!< 0x20000000 */\n#define EXTI_EMR2_EM61             EXTI_EMR2_EM61_Msk                          /*!< Event Mask on line 61 */\n#define EXTI_EMR2_EM62_Pos         (30U)\n#define EXTI_EMR2_EM62_Msk         (0x1UL << EXTI_EMR2_EM62_Pos)               /*!< 0x40000000 */\n#define EXTI_EMR2_EM62             EXTI_EMR2_EM62_Msk                          /*!< Event Mask on line 62 */\n#define EXTI_EMR2_EM63_Pos         (31U)\n#define EXTI_EMR2_EM63_Msk         (0x1UL << EXTI_EMR2_EM63_Pos)               /*!< 0x80000000 */\n#define EXTI_EMR2_EM63             EXTI_EMR2_EM63_Msk                          /*!< Event Mask on line 63 */\n\n/*******************  Bit definition for EXTI_PR2 register  ********************/\n#define EXTI_PR2_PR_Pos            (17U)\n#define EXTI_PR2_PR_Msk            (0x5UL << EXTI_PR2_PR_Pos)                  /*!< 0x000A0000 */\n#define EXTI_PR2_PR                EXTI_PR2_PR_Msk                             /*!< Pending bit */\n#define EXTI_PR2_PR49_Pos          (17U)\n#define EXTI_PR2_PR49_Msk          (0x1UL << EXTI_PR2_PR49_Pos)                /*!< 0x00020000 */\n#define EXTI_PR2_PR49              EXTI_PR2_PR49_Msk                           /*!< Pending bit for line 49 */\n#define EXTI_PR2_PR51_Pos          (19U)\n#define EXTI_PR2_PR51_Msk          (0x1UL << EXTI_PR2_PR51_Pos)                /*!< 0x00080000 */\n#define EXTI_PR2_PR51              EXTI_PR2_PR51_Msk                           /*!< Pending bit for line 51 */\n\n/*******************  Bit definition for EXTI_IMR3 register  *******************/\n#define EXTI_IMR3_IM_Pos           (0U)\n#define EXTI_IMR3_IM_Msk           (0x00F5FFFFUL << EXTI_IMR3_IM_Pos)          /*!< 0x00F5FFFF */\n#define EXTI_IMR3_IM               EXTI_IMR3_IM_Msk                            /*!< Interrupt Mask */\n#define EXTI_IMR3_IM64_Pos         (0U)\n#define EXTI_IMR3_IM64_Msk         (0x1UL << EXTI_IMR3_IM64_Pos)               /*!< 0x00000001 */\n#define EXTI_IMR3_IM64             EXTI_IMR3_IM64_Msk                          /*!< Interrupt Mask on line 64 */\n#define EXTI_IMR3_IM65_Pos         (1U)\n#define EXTI_IMR3_IM65_Msk         (0x1UL << EXTI_IMR3_IM65_Pos)               /*!< 0x00000002 */\n#define EXTI_IMR3_IM65             EXTI_IMR3_IM65_Msk                          /*!< Interrupt Mask on line 65 */\n#define EXTI_IMR3_IM66_Pos         (2U)\n#define EXTI_IMR3_IM66_Msk         (0x1UL << EXTI_IMR3_IM66_Pos)               /*!< 0x00000004 */\n#define EXTI_IMR3_IM66             EXTI_IMR3_IM66_Msk                          /*!< Interrupt Mask on line 66 */\n#define EXTI_IMR3_IM67_Pos         (3U)\n#define EXTI_IMR3_IM67_Msk         (0x1UL << EXTI_IMR3_IM67_Pos)               /*!< 0x00000008 */\n#define EXTI_IMR3_IM67             EXTI_IMR3_IM67_Msk                          /*!< Interrupt Mask on line 67 */\n#define EXTI_IMR3_IM68_Pos         (4U)\n#define EXTI_IMR3_IM68_Msk         (0x1UL << EXTI_IMR3_IM68_Pos)               /*!< 0x00000010 */\n#define EXTI_IMR3_IM68             EXTI_IMR3_IM68_Msk                          /*!< Interrupt Mask on line 68 */\n#define EXTI_IMR3_IM69_Pos         (5U)\n#define EXTI_IMR3_IM69_Msk         (0x1UL << EXTI_IMR3_IM69_Pos)               /*!< 0x00000020 */\n#define EXTI_IMR3_IM69             EXTI_IMR3_IM69_Msk                          /*!< Interrupt Mask on line 69 */\n#define EXTI_IMR3_IM70_Pos         (6U)\n#define EXTI_IMR3_IM70_Msk         (0x1UL << EXTI_IMR3_IM70_Pos)               /*!< 0x00000040 */\n#define EXTI_IMR3_IM70             EXTI_IMR3_IM70_Msk                          /*!< Interrupt Mask on line 70 */\n#define EXTI_IMR3_IM71_Pos         (7U)\n#define EXTI_IMR3_IM71_Msk         (0x1UL << EXTI_IMR3_IM71_Pos)               /*!< 0x00000080 */\n#define EXTI_IMR3_IM71             EXTI_IMR3_IM71_Msk                          /*!< Interrupt Mask on line 71 */\n#define EXTI_IMR3_IM72_Pos         (8U)\n#define EXTI_IMR3_IM72_Msk         (0x1UL << EXTI_IMR3_IM72_Pos)               /*!< 0x00000100 */\n#define EXTI_IMR3_IM72             EXTI_IMR3_IM72_Msk                          /*!< Interrupt Mask on line 72 */\n#define EXTI_IMR3_IM73_Pos         (9U)\n#define EXTI_IMR3_IM73_Msk         (0x1UL << EXTI_IMR3_IM73_Pos)               /*!< 0x00000200 */\n#define EXTI_IMR3_IM73             EXTI_IMR3_IM73_Msk                          /*!< Interrupt Mask on line 73 */\n#define EXTI_IMR3_IM74_Pos         (10U)\n#define EXTI_IMR3_IM74_Msk         (0x1UL << EXTI_IMR3_IM74_Pos)               /*!< 0x00000400 */\n#define EXTI_IMR3_IM74             EXTI_IMR3_IM74_Msk                          /*!< Interrupt Mask on line 74 */\n#define EXTI_IMR3_IM75_Pos         (11U)\n#define EXTI_IMR3_IM75_Msk         (0x1UL << EXTI_IMR3_IM75_Pos)               /*!< 0x00000800 */\n#define EXTI_IMR3_IM75             EXTI_IMR3_IM75_Msk                          /*!< Interrupt Mask on line 75 */\n#define EXTI_IMR3_IM76_Pos         (12U)\n#define EXTI_IMR3_IM76_Msk         (0x1UL << EXTI_IMR3_IM76_Pos)               /*!< 0x00001000 */\n#define EXTI_IMR3_IM76             EXTI_IMR3_IM76_Msk                          /*!< Interrupt Mask on line 76 */\n#define EXTI_IMR3_IM77_Pos         (13U)\n#define EXTI_IMR3_IM77_Msk         (0x1UL << EXTI_IMR3_IM77_Pos)               /*!< 0x00002000 */\n#define EXTI_IMR3_IM77             EXTI_IMR3_IM77_Msk                          /*!< Interrupt Mask on line 77 */\n#define EXTI_IMR3_IM78_Pos         (14U)\n#define EXTI_IMR3_IM78_Msk         (0x1UL << EXTI_IMR3_IM78_Pos)               /*!< 0x00004000 */\n#define EXTI_IMR3_IM78             EXTI_IMR3_IM78_Msk                          /*!< Interrupt Mask on line 78 */\n#define EXTI_IMR3_IM79_Pos         (15U)\n#define EXTI_IMR3_IM79_Msk         (0x1UL << EXTI_IMR3_IM79_Pos)               /*!< 0x00008000 */\n#define EXTI_IMR3_IM79             EXTI_IMR3_IM79_Msk                          /*!< Interrupt Mask on line 79 */\n#define EXTI_IMR3_IM80_Pos         (16U)\n#define EXTI_IMR3_IM80_Msk         (0x1UL << EXTI_IMR3_IM80_Pos)               /*!< 0x00010000 */\n#define EXTI_IMR3_IM80             EXTI_IMR3_IM80_Msk                          /*!< Interrupt Mask on line 80 */\n#define EXTI_IMR3_IM82_Pos         (18U)\n#define EXTI_IMR3_IM82_Msk         (0x1UL << EXTI_IMR3_IM82_Pos)               /*!< 0x00040000 */\n#define EXTI_IMR3_IM82             EXTI_IMR3_IM82_Msk                          /*!< Interrupt Mask on line 82 */\n#define EXTI_IMR3_IM84_Pos         (20U)\n#define EXTI_IMR3_IM84_Msk         (0x1UL << EXTI_IMR3_IM84_Pos)               /*!< 0x00100000 */\n#define EXTI_IMR3_IM84             EXTI_IMR3_IM84_Msk                          /*!< Interrupt Mask on line 84 */\n#define EXTI_IMR3_IM85_Pos         (21U)\n#define EXTI_IMR3_IM85_Msk         (0x1UL << EXTI_IMR3_IM85_Pos)               /*!< 0x00200000 */\n#define EXTI_IMR3_IM85             EXTI_IMR3_IM85_Msk                          /*!< Interrupt Mask on line 85 */\n#define EXTI_IMR3_IM86_Pos         (22U)\n#define EXTI_IMR3_IM86_Msk         (0x1UL << EXTI_IMR3_IM86_Pos)               /*!< 0x00400000 */\n#define EXTI_IMR3_IM86             EXTI_IMR3_IM86_Msk                          /*!< Interrupt Mask on line 86 */\n#define EXTI_IMR3_IM87_Pos         (23U)\n#define EXTI_IMR3_IM87_Msk         (0x1UL << EXTI_IMR3_IM87_Pos)               /*!< 0x00800000 */\n#define EXTI_IMR3_IM87             EXTI_IMR3_IM87_Msk                          /*!< Interrupt Mask on line 87 */\n\n\n/*******************  Bit definition for EXTI_EMR3 register  *******************/\n#define EXTI_EMR3_EM_Pos           (0U)\n#define EXTI_EMR3_EM_Msk           (0x00F5FFFFUL << EXTI_EMR3_EM_Pos)          /*!< 0x00F5FFFF */\n#define EXTI_EMR3_EM               EXTI_EMR3_EM_Msk                            /*!< Event Mask           */\n#define EXTI_EMR3_EM64_Pos         (0U)\n#define EXTI_EMR3_EM64_Msk         (0x1UL << EXTI_EMR3_EM64_Pos)               /*!< 0x00000001 */\n#define EXTI_EMR3_EM64             EXTI_EMR3_EM64_Msk                          /*!< Event Mask on line 64*/\n#define EXTI_EMR3_EM65_Pos         (1U)\n#define EXTI_EMR3_EM65_Msk         (0x1UL << EXTI_EMR3_EM65_Pos)               /*!< 0x00000002 */\n#define EXTI_EMR3_EM65             EXTI_EMR3_EM65_Msk                          /*!< Event Mask on line 65*/\n#define EXTI_EMR3_EM66_Pos         (2U)\n#define EXTI_EMR3_EM66_Msk         (0x1UL << EXTI_EMR3_EM66_Pos)               /*!< 0x00000004 */\n#define EXTI_EMR3_EM66             EXTI_EMR3_EM66_Msk                          /*!< Event Mask on line 66*/\n#define EXTI_EMR3_EM67_Pos         (3U)\n#define EXTI_EMR3_EM67_Msk         (0x1UL << EXTI_EMR3_EM67_Pos)               /*!< 0x00000008 */\n#define EXTI_EMR3_EM67             EXTI_EMR3_EM67_Msk                          /*!< Event Mask on line 67*/\n#define EXTI_EMR3_EM68_Pos         (4U)\n#define EXTI_EMR3_EM68_Msk         (0x1UL << EXTI_EMR3_EM68_Pos)               /*!< 0x00000010 */\n#define EXTI_EMR3_EM68             EXTI_EMR3_EM68_Msk                          /*!< Event Mask on line 68*/\n#define EXTI_EMR3_EM69_Pos         (5U)\n#define EXTI_EMR3_EM69_Msk         (0x1UL << EXTI_EMR3_EM69_Pos)               /*!< 0x00000020 */\n#define EXTI_EMR3_EM69             EXTI_EMR3_EM69_Msk                          /*!< Event Mask on line 69*/\n#define EXTI_EMR3_EM70_Pos         (6U)\n#define EXTI_EMR3_EM70_Msk         (0x1UL << EXTI_EMR3_EM70_Pos)               /*!< 0x00000040 */\n#define EXTI_EMR3_EM70             EXTI_EMR3_EM70_Msk                          /*!< Event Mask on line 70*/\n#define EXTI_EMR3_EM71_Pos         (7U)\n#define EXTI_EMR3_EM71_Msk         (0x1UL << EXTI_EMR3_EM71_Pos)               /*!< 0x00000080 */\n#define EXTI_EMR3_EM71             EXTI_EMR3_EM71_Msk                          /*!< Event Mask on line 71*/\n#define EXTI_EMR3_EM72_Pos         (8U)\n#define EXTI_EMR3_EM72_Msk         (0x1UL << EXTI_EMR3_EM72_Pos)               /*!< 0x00000100 */\n#define EXTI_EMR3_EM72             EXTI_EMR3_EM72_Msk                          /*!< Event Mask on line 72*/\n#define EXTI_EMR3_EM73_Pos         (9U)\n#define EXTI_EMR3_EM73_Msk         (0x1UL << EXTI_EMR3_EM73_Pos)               /*!< 0x00000200 */\n#define EXTI_EMR3_EM73             EXTI_EMR3_EM73_Msk                          /*!< Event Mask on line 73*/\n#define EXTI_EMR3_EM74_Pos         (10U)\n#define EXTI_EMR3_EM74_Msk         (0x1UL << EXTI_EMR3_EM74_Pos)               /*!< 0x00000400 */\n#define EXTI_EMR3_EM74             EXTI_EMR3_EM74_Msk                          /*!< Event Mask on line 74 */\n#define EXTI_EMR3_EM75_Pos         (11U)\n#define EXTI_EMR3_EM75_Msk         (0x1UL << EXTI_EMR3_EM75_Pos)               /*!< 0x00000800 */\n#define EXTI_EMR3_EM75             EXTI_EMR3_EM75_Msk                          /*!< Event Mask on line 75 */\n#define EXTI_EMR3_EM76_Pos         (12U)\n#define EXTI_EMR3_EM76_Msk         (0x1UL << EXTI_EMR3_EM76_Pos)               /*!< 0x00001000 */\n#define EXTI_EMR3_EM76             EXTI_EMR3_EM76_Msk                          /*!< Event Mask on line 76 */\n#define EXTI_EMR3_EM77_Pos         (13U)\n#define EXTI_EMR3_EM77_Msk         (0x1UL << EXTI_EMR3_EM77_Pos)               /*!< 0x00002000 */\n#define EXTI_EMR3_EM77             EXTI_EMR3_EM77_Msk                          /*!< Event Mask on line 77 */\n#define EXTI_EMR3_EM78_Pos         (14U)\n#define EXTI_EMR3_EM78_Msk         (0x1UL << EXTI_EMR3_EM78_Pos)               /*!< 0x00004000 */\n#define EXTI_EMR3_EM78             EXTI_EMR3_EM78_Msk                          /*!< Event Mask on line 78 */\n#define EXTI_EMR3_EM79_Pos         (15U)\n#define EXTI_EMR3_EM79_Msk         (0x1UL << EXTI_EMR3_EM79_Pos)               /*!< 0x00008000 */\n#define EXTI_EMR3_EM79             EXTI_EMR3_EM79_Msk                          /*!< Event Mask on line 79 */\n#define EXTI_EMR3_EM80_Pos         (16U)\n#define EXTI_EMR3_EM80_Msk         (0x1UL << EXTI_EMR3_EM80_Pos)               /*!< 0x00010000 */\n#define EXTI_EMR3_EM80             EXTI_EMR3_EM80_Msk                          /*!< Event Mask on line 80 */\n#define EXTI_EMR3_EM81_Pos         (17U)\n#define EXTI_EMR3_EM81_Msk         (0x1UL << EXTI_EMR3_EM81_Pos)               /*!< 0x00020000 */\n#define EXTI_EMR3_EM81             EXTI_EMR3_EM81_Msk                          /*!< Event Mask on line 81 */\n#define EXTI_EMR3_EM82_Pos         (18U)\n#define EXTI_EMR3_EM82_Msk         (0x1UL << EXTI_EMR3_EM82_Pos)               /*!< 0x00040000 */\n#define EXTI_EMR3_EM82             EXTI_EMR3_EM82_Msk                          /*!< Event Mask on line 82 */\n#define EXTI_EMR3_EM84_Pos         (20U)\n#define EXTI_EMR3_EM84_Msk         (0x1UL << EXTI_EMR3_EM84_Pos)               /*!< 0x00100000 */\n#define EXTI_EMR3_EM84             EXTI_EMR3_EM84_Msk                          /*!< Event Mask on line 84 */\n#define EXTI_EMR3_EM85_Pos         (21U)\n#define EXTI_EMR3_EM85_Msk         (0x1UL << EXTI_EMR3_EM85_Pos)               /*!< 0x00200000 */\n#define EXTI_EMR3_EM85             EXTI_EMR3_EM85_Msk                          /*!< Event Mask on line 85 */\n#define EXTI_EMR3_EM86_Pos         (22U)\n#define EXTI_EMR3_EM86_Msk         (0x1UL << EXTI_EMR3_EM86_Pos)               /*!< 0x00400000 */\n#define EXTI_EMR3_EM86             EXTI_EMR3_EM86_Msk                          /*!< Event Mask on line 86 */\n#define EXTI_EMR3_EM87_Pos         (23U)\n#define EXTI_EMR3_EM87_Msk         (0x1UL << EXTI_EMR3_EM87_Pos)               /*!< 0x00800000 */\n#define EXTI_EMR3_EM87             EXTI_EMR3_EM87_Msk                          /*!< Event Mask on line 87 */\n\n/*******************  Bit definition for EXTI_PR3 register  ********************/\n#define EXTI_PR3_PR_Pos            (18U)\n#define EXTI_PR3_PR_Msk            (0x1DUL << EXTI_PR3_PR_Pos)                 /*!< 0x00740000 */\n#define EXTI_PR3_PR                EXTI_PR3_PR_Msk                             /*!< Pending bit */\n#define EXTI_PR3_PR82_Pos          (18U)\n#define EXTI_PR3_PR82_Msk          (0x1UL << EXTI_PR3_PR82_Pos)                /*!< 0x00040000 */\n#define EXTI_PR3_PR82              EXTI_PR3_PR82_Msk                           /*!< Pending bit for line 82 */\n#define EXTI_PR3_PR84_Pos          (20U)\n#define EXTI_PR3_PR84_Msk          (0x1UL << EXTI_PR3_PR84_Pos)                /*!< 0x00100000 */\n#define EXTI_PR3_PR84              EXTI_PR3_PR84_Msk                           /*!< Pending bit for line 84 */\n#define EXTI_PR3_PR85_Pos          (21U)\n#define EXTI_PR3_PR85_Msk          (0x1UL << EXTI_PR3_PR85_Pos)                /*!< 0x00200000 */\n#define EXTI_PR3_PR85              EXTI_PR3_PR85_Msk                           /*!< Pending bit for line 85 */\n#define EXTI_PR3_PR86_Pos          (22U)\n#define EXTI_PR3_PR86_Msk          (0x1UL << EXTI_PR3_PR86_Pos)                /*!< 0x00400000 */\n#define EXTI_PR3_PR86              EXTI_PR3_PR86_Msk                           /*!< Pending bit for line 86 */\n/******************************************************************************/\n/*                                                                            */\n/*                                    FLASH                                   */\n/*                                                                            */\n/******************************************************************************/\n/*\n* @brief FLASH Global Defines\n*/\n#define FLASH_SIZE_DATA_REGISTER             0x1FF1E880U\n#define FLASH_SECTOR_TOTAL                   8U                    /* 8 sectors */\n#define FLASH_SIZE                           ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? 0x200000U : \\\n                                             ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x0000U)) ? 0x200000U : \\\n                                             (((uint32_t)(*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U)))  /* 2 MB   */\n#define FLASH_BANK_SIZE                      (FLASH_SIZE >> 1)     /* 1 MB   */\n#define FLASH_SECTOR_SIZE                    0x00020000UL          /* 128 KB */\n#define FLASH_LATENCY_DEFAULT                FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */\n#define FLASH_NB_32BITWORD_IN_FLASHWORD      8U                    /* 256 bits */\n#define DUAL_BANK                                                  /* Dual-bank Flash */\n\n/*******************  Bits definition for FLASH_ACR register  **********************/\n#define FLASH_ACR_LATENCY_Pos                (0U)\n#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F: bit4 is kept only for legacy purpose */\n#define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Read Latency */\n#define FLASH_ACR_LATENCY_0WS                (0x00000000UL)\n#define FLASH_ACR_LATENCY_1WS                (0x00000001UL)\n#define FLASH_ACR_LATENCY_2WS                (0x00000002UL)\n#define FLASH_ACR_LATENCY_3WS                (0x00000003UL)\n#define FLASH_ACR_LATENCY_4WS                (0x00000004UL)\n#define FLASH_ACR_LATENCY_5WS                (0x00000005UL)\n#define FLASH_ACR_LATENCY_6WS                (0x00000006UL)\n#define FLASH_ACR_LATENCY_7WS                (0x00000007UL)\n\n#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)\n#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */\n#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */\n#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */\n#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */\n\n/* Legacy FLASH Latency defines */\n#define FLASH_ACR_LATENCY_8WS                (0x00000008UL)\n#define FLASH_ACR_LATENCY_9WS                (0x00000009UL)\n#define FLASH_ACR_LATENCY_10WS               (0x0000000AUL)\n#define FLASH_ACR_LATENCY_11WS               (0x0000000BUL)\n#define FLASH_ACR_LATENCY_12WS               (0x0000000CUL)\n#define FLASH_ACR_LATENCY_13WS               (0x0000000DUL)\n#define FLASH_ACR_LATENCY_14WS               (0x0000000EUL)\n#define FLASH_ACR_LATENCY_15WS               (0x0000000FUL)\n/*******************  Bits definition for FLASH_CR register  ***********************/\n#define FLASH_CR_LOCK_Pos                    (0U)\n#define FLASH_CR_LOCK_Msk                    (0x1UL << FLASH_CR_LOCK_Pos)      /*!< 0x00000001 */\n#define FLASH_CR_LOCK                        FLASH_CR_LOCK_Msk                 /*!< Configuration lock bit */\n#define FLASH_CR_PG_Pos                      (1U)\n#define FLASH_CR_PG_Msk                      (0x1UL << FLASH_CR_PG_Pos)        /*!< 0x00000002 */\n#define FLASH_CR_PG                          FLASH_CR_PG_Msk                   /*!< Internal buffer control bit */\n#define FLASH_CR_SER_Pos                     (2U)\n#define FLASH_CR_SER_Msk                     (0x1UL << FLASH_CR_SER_Pos)       /*!< 0x00000004 */\n#define FLASH_CR_SER                         FLASH_CR_SER_Msk                  /*!< Sector erase request */\n#define FLASH_CR_BER_Pos                     (3U)\n#define FLASH_CR_BER_Msk                     (0x1UL << FLASH_CR_BER_Pos)       /*!< 0x00000008 */\n#define FLASH_CR_BER                         FLASH_CR_BER_Msk                  /*!< Bank erase request */\n#define FLASH_CR_PSIZE_Pos                   (4U)\n#define FLASH_CR_PSIZE_Msk                   (0x3UL << FLASH_CR_PSIZE_Pos)     /*!< 0x00000030 */\n#define FLASH_CR_PSIZE                       FLASH_CR_PSIZE_Msk                /*!< Program size */\n#define FLASH_CR_PSIZE_0                     (0x1UL << FLASH_CR_PSIZE_Pos)     /*!< 0x00000010 */\n#define FLASH_CR_PSIZE_1                     (0x2UL << FLASH_CR_PSIZE_Pos)     /*!< 0x00000020 */\n#define FLASH_CR_FW_Pos                      (6U)\n#define FLASH_CR_FW_Msk                      (0x1UL << FLASH_CR_FW_Pos)        /*!< 0x00000040 */\n#define FLASH_CR_FW                          FLASH_CR_FW_Msk                   /*!< Write forcing control bit */\n#define FLASH_CR_START_Pos                   (7U)\n#define FLASH_CR_START_Msk                   (0x1UL << FLASH_CR_START_Pos)     /*!< 0x00000080 */\n#define FLASH_CR_START                       FLASH_CR_START_Msk                /*!< Erase start control bit */\n#define FLASH_CR_SNB_Pos                     (8U)\n#define FLASH_CR_SNB_Msk                     (0x7UL << FLASH_CR_SNB_Pos)       /*!< 0x00000700 */\n#define FLASH_CR_SNB                         FLASH_CR_SNB_Msk                  /*!< Sector erase selection number */\n#define FLASH_CR_SNB_0                       (0x1UL << FLASH_CR_SNB_Pos)       /*!< 0x00000100 */\n#define FLASH_CR_SNB_1                       (0x2UL << FLASH_CR_SNB_Pos)       /*!< 0x00000200 */\n#define FLASH_CR_SNB_2                       (0x4UL << FLASH_CR_SNB_Pos)       /*!< 0x00000400 */\n#define FLASH_CR_CRC_EN_Pos                  (15U)\n#define FLASH_CR_CRC_EN_Msk                  (0x1UL << FLASH_CR_CRC_EN_Pos)    /*!< 0x00008000 */\n#define FLASH_CR_CRC_EN                      FLASH_CR_CRC_EN_Msk               /*!< CRC control bit */\n#define FLASH_CR_EOPIE_Pos                   (16U)\n#define FLASH_CR_EOPIE_Msk                   (0x1UL << FLASH_CR_EOPIE_Pos)     /*!< 0x00010000 */\n#define FLASH_CR_EOPIE                       FLASH_CR_EOPIE_Msk                /*!< End-of-program interrupt control bit */\n#define FLASH_CR_WRPERRIE_Pos                (17U)\n#define FLASH_CR_WRPERRIE_Msk                (0x1UL << FLASH_CR_WRPERRIE_Pos)  /*!< 0x00020000 */\n#define FLASH_CR_WRPERRIE                    FLASH_CR_WRPERRIE_Msk             /*!< Write protection error interrupt enable bit */\n#define FLASH_CR_PGSERRIE_Pos                (18U)\n#define FLASH_CR_PGSERRIE_Msk                (0x1UL << FLASH_CR_PGSERRIE_Pos)  /*!< 0x00040000 */\n#define FLASH_CR_PGSERRIE                    FLASH_CR_PGSERRIE_Msk             /*!< Programming sequence error interrupt enable bit */\n#define FLASH_CR_STRBERRIE_Pos               (19U)\n#define FLASH_CR_STRBERRIE_Msk               (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */\n#define FLASH_CR_STRBERRIE                   FLASH_CR_STRBERRIE_Msk            /*!< Strobe error interrupt enable bit */\n#define FLASH_CR_INCERRIE_Pos                (21U)\n#define FLASH_CR_INCERRIE_Msk                (0x1UL << FLASH_CR_INCERRIE_Pos)  /*!< 0x00200000 */\n#define FLASH_CR_INCERRIE                    FLASH_CR_INCERRIE_Msk             /*!< Inconsistency error interrupt enable bit */\n#define FLASH_CR_OPERRIE_Pos                 (22U)\n#define FLASH_CR_OPERRIE_Msk                 (0x1UL << FLASH_CR_OPERRIE_Pos)   /*!< 0x00400000 */\n#define FLASH_CR_OPERRIE                     FLASH_CR_OPERRIE_Msk              /*!< Write/erase error interrupt enable bit */\n#define FLASH_CR_RDPERRIE_Pos                (23U)\n#define FLASH_CR_RDPERRIE_Msk                (0x1UL << FLASH_CR_RDPERRIE_Pos)  /*!< 0x00800000 */\n#define FLASH_CR_RDPERRIE                    FLASH_CR_RDPERRIE_Msk             /*!< Read protection error interrupt enable bit */\n#define FLASH_CR_RDSERRIE_Pos                (24U)\n#define FLASH_CR_RDSERRIE_Msk                (0x1UL << FLASH_CR_RDSERRIE_Pos)  /*!< 0x01000000 */\n#define FLASH_CR_RDSERRIE                    FLASH_CR_RDSERRIE_Msk             /*!< Secure error interrupt enable bit */\n#define FLASH_CR_SNECCERRIE_Pos              (25U)\n#define FLASH_CR_SNECCERRIE_Msk              (0x1UL << FLASH_CR_SNECCERRIE_Pos) /*!< 0x02000000 */\n#define FLASH_CR_SNECCERRIE                  FLASH_CR_SNECCERRIE_Msk            /*!< ECC single correction error interrupt enable bit */\n#define FLASH_CR_DBECCERRIE_Pos              (26U)\n#define FLASH_CR_DBECCERRIE_Msk              (0x1UL << FLASH_CR_DBECCERRIE_Pos) /*!< 0x04000000 */\n#define FLASH_CR_DBECCERRIE                  FLASH_CR_DBECCERRIE_Msk            /*!< ECC double detection error interrupt enable bit */\n#define FLASH_CR_CRCENDIE_Pos                (27U)\n#define FLASH_CR_CRCENDIE_Msk                (0x1UL << FLASH_CR_CRCENDIE_Pos)  /*!< 0x08000000 */\n#define FLASH_CR_CRCENDIE                    FLASH_CR_CRCENDIE_Msk             /*!< CRC end of calculation interrupt enable bit */\n#define FLASH_CR_CRCRDERRIE_Pos              (28U)\n#define FLASH_CR_CRCRDERRIE_Msk              (0x1UL << FLASH_CR_CRCRDERRIE_Pos) /*!< 0x10000000 */\n#define FLASH_CR_CRCRDERRIE                  FLASH_CR_CRCRDERRIE_Msk            /*!< CRC read error interrupt enable bit */\n\n/*******************  Bits definition for FLASH_SR register  ***********************/\n#define FLASH_SR_BSY_Pos                     (0U)\n#define FLASH_SR_BSY_Msk                     (0x1UL << FLASH_SR_BSY_Pos)       /*!< 0x00000001 */\n#define FLASH_SR_BSY                         FLASH_SR_BSY_Msk                  /*!< Busy flag */\n#define FLASH_SR_WBNE_Pos                    (1U)\n#define FLASH_SR_WBNE_Msk                    (0x1UL << FLASH_SR_WBNE_Pos)      /*!< 0x00000002 */\n#define FLASH_SR_WBNE                        FLASH_SR_WBNE_Msk                 /*!< Write buffer not empty flag */\n#define FLASH_SR_QW_Pos                      (2U)\n#define FLASH_SR_QW_Msk                      (0x1UL << FLASH_SR_QW_Pos)        /*!< 0x00000004 */\n#define FLASH_SR_QW                          FLASH_SR_QW_Msk                   /*!< Wait queue flag */\n#define FLASH_SR_CRC_BUSY_Pos                (3U)\n#define FLASH_SR_CRC_BUSY_Msk                (0x1UL << FLASH_SR_CRC_BUSY_Pos)  /*!< 0x00000008 */\n#define FLASH_SR_CRC_BUSY                    FLASH_SR_CRC_BUSY_Msk             /*!< CRC busy flag */\n#define FLASH_SR_EOP_Pos                     (16U)\n#define FLASH_SR_EOP_Msk                     (0x1UL << FLASH_SR_EOP_Pos)       /*!< 0x00010000 */\n#define FLASH_SR_EOP                         FLASH_SR_EOP_Msk                  /*!< End-of-program flag */\n#define FLASH_SR_WRPERR_Pos                  (17U)\n#define FLASH_SR_WRPERR_Msk                  (0x1UL << FLASH_SR_WRPERR_Pos)    /*!< 0x00020000 */\n#define FLASH_SR_WRPERR                      FLASH_SR_WRPERR_Msk               /*!< Write protection error flag */\n#define FLASH_SR_PGSERR_Pos                  (18U)\n#define FLASH_SR_PGSERR_Msk                  (0x1UL << FLASH_SR_PGSERR_Pos)    /*!< 0x00040000 */\n#define FLASH_SR_PGSERR                      FLASH_SR_PGSERR_Msk               /*!< Programming sequence error flag */\n#define FLASH_SR_STRBERR_Pos                 (19U)\n#define FLASH_SR_STRBERR_Msk                 (0x1UL << FLASH_SR_STRBERR_Pos)   /*!< 0x00080000 */\n#define FLASH_SR_STRBERR                     FLASH_SR_STRBERR_Msk              /*!< Strobe error flag */\n#define FLASH_SR_INCERR_Pos                  (21U)\n#define FLASH_SR_INCERR_Msk                  (0x1UL << FLASH_SR_INCERR_Pos)    /*!< 0x00200000 */\n#define FLASH_SR_INCERR                      FLASH_SR_INCERR_Msk               /*!< Inconsistency error flag */\n#define FLASH_SR_OPERR_Pos                   (22U)\n#define FLASH_SR_OPERR_Msk                   (0x1UL << FLASH_SR_OPERR_Pos)     /*!< 0x00400000 */\n#define FLASH_SR_OPERR                       FLASH_SR_OPERR_Msk                /*!< Write/erase error flag */\n#define FLASH_SR_RDPERR_Pos                  (23U)\n#define FLASH_SR_RDPERR_Msk                  (0x1UL << FLASH_SR_RDPERR_Pos)    /*!< 0x00800000 */\n#define FLASH_SR_RDPERR                      FLASH_SR_RDPERR_Msk               /*!< Read protection error flag */\n#define FLASH_SR_RDSERR_Pos                  (24U)\n#define FLASH_SR_RDSERR_Msk                  (0x1UL << FLASH_SR_RDSERR_Pos)    /*!< 0x01000000 */\n#define FLASH_SR_RDSERR                      FLASH_SR_RDSERR_Msk               /*!< Secure error flag */\n#define FLASH_SR_SNECCERR_Pos                (25U)\n#define FLASH_SR_SNECCERR_Msk                (0x1UL << FLASH_SR_SNECCERR_Pos)  /*!< 0x02000000 */\n#define FLASH_SR_SNECCERR                    FLASH_SR_SNECCERR_Msk             /*!< Single correction error flag */\n#define FLASH_SR_DBECCERR_Pos                (26U)\n#define FLASH_SR_DBECCERR_Msk                (0x1UL << FLASH_SR_DBECCERR_Pos)  /*!< 0x04000000 */\n#define FLASH_SR_DBECCERR                    FLASH_SR_DBECCERR_Msk             /*!< ECC double detection error flag */\n#define FLASH_SR_CRCEND_Pos                  (27U)\n#define FLASH_SR_CRCEND_Msk                  (0x1UL << FLASH_SR_CRCEND_Pos)    /*!< 0x08000000 */\n#define FLASH_SR_CRCEND                      FLASH_SR_CRCEND_Msk               /*!< CRC end of calculation flag */\n#define FLASH_SR_CRCRDERR_Pos                (28U)\n#define FLASH_SR_CRCRDERR_Msk                (0x1UL << FLASH_SR_CRCRDERR_Pos)  /*!< 0x10000000 */\n#define FLASH_SR_CRCRDERR                    FLASH_SR_CRCRDERR_Msk             /*!< CRC read error flag */\n\n/*******************  Bits definition for FLASH_CCR register  *******************/\n#define FLASH_CCR_CLR_EOP_Pos                (16U)\n#define FLASH_CCR_CLR_EOP_Msk                (0x1UL << FLASH_CCR_CLR_EOP_Pos)  /*!< 0x00010000 */\n#define FLASH_CCR_CLR_EOP                    FLASH_CCR_CLR_EOP_Msk             /*!< EOP flag clear bit */\n#define FLASH_CCR_CLR_WRPERR_Pos             (17U)\n#define FLASH_CCR_CLR_WRPERR_Msk             (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */\n#define FLASH_CCR_CLR_WRPERR                 FLASH_CCR_CLR_WRPERR_Msk            /*!< WRPERR flag clear bit */\n#define FLASH_CCR_CLR_PGSERR_Pos             (18U)\n#define FLASH_CCR_CLR_PGSERR_Msk             (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */\n#define FLASH_CCR_CLR_PGSERR                 FLASH_CCR_CLR_PGSERR_Msk            /*!< PGSERR flag clear bit */\n#define FLASH_CCR_CLR_STRBERR_Pos            (19U)\n#define FLASH_CCR_CLR_STRBERR_Msk            (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */\n#define FLASH_CCR_CLR_STRBERR                FLASH_CCR_CLR_STRBERR_Msk            /*!< STRBERR flag clear bit */\n#define FLASH_CCR_CLR_INCERR_Pos             (21U)\n#define FLASH_CCR_CLR_INCERR_Msk             (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00200000 */\n#define FLASH_CCR_CLR_INCERR                 FLASH_CCR_CLR_INCERR_Msk            /*!< INCERR flag clear bit */\n#define FLASH_CCR_CLR_OPERR_Pos              (22U)\n#define FLASH_CCR_CLR_OPERR_Msk              (0x1UL << FLASH_CCR_CLR_OPERR_Pos) /*!< 0x00400000 */\n#define FLASH_CCR_CLR_OPERR                  FLASH_CCR_CLR_OPERR_Msk            /*!< OPERR flag clear bit */\n#define FLASH_CCR_CLR_RDPERR_Pos             (23U)\n#define FLASH_CCR_CLR_RDPERR_Msk             (0x1UL << FLASH_CCR_CLR_RDPERR_Pos) /*!< 0x00800000 */\n#define FLASH_CCR_CLR_RDPERR                 FLASH_CCR_CLR_RDPERR_Msk            /*!< RDPERR flag clear bit */\n#define FLASH_CCR_CLR_RDSERR_Pos             (24U)\n#define FLASH_CCR_CLR_RDSERR_Msk             (0x1UL << FLASH_CCR_CLR_RDSERR_Pos) /*!< 0x01000000 */\n#define FLASH_CCR_CLR_RDSERR                 FLASH_CCR_CLR_RDSERR_Msk            /*!< RDSERR flag clear bit */\n#define FLASH_CCR_CLR_SNECCERR_Pos           (25U)\n#define FLASH_CCR_CLR_SNECCERR_Msk           (0x1UL << FLASH_CCR_CLR_SNECCERR_Pos) /*!< 0x02000000 */\n#define FLASH_CCR_CLR_SNECCERR               FLASH_CCR_CLR_SNECCERR_Msk            /*!< SNECCERR flag clear bit */\n#define FLASH_CCR_CLR_DBECCERR_Pos           (26U)\n#define FLASH_CCR_CLR_DBECCERR_Msk           (0x1UL << FLASH_CCR_CLR_DBECCERR_Pos) /*!< 0x04000000 */\n#define FLASH_CCR_CLR_DBECCERR               FLASH_CCR_CLR_DBECCERR_Msk            /*!< DBECCERR flag clear bit */\n#define FLASH_CCR_CLR_CRCEND_Pos             (27U)\n#define FLASH_CCR_CLR_CRCEND_Msk             (0x1UL << FLASH_CCR_CLR_CRCEND_Pos) /*!< 0x08000000 */\n#define FLASH_CCR_CLR_CRCEND                 FLASH_CCR_CLR_CRCEND_Msk            /*!< CRCEND flag clear bit */\n#define FLASH_CCR_CLR_CRCRDERR_Pos           (28U)\n#define FLASH_CCR_CLR_CRCRDERR_Msk           (0x1UL << FLASH_CCR_CLR_CRCRDERR_Pos) /*!< 0x10000000 */\n#define FLASH_CCR_CLR_CRCRDERR               FLASH_CCR_CLR_CRCRDERR_Msk            /*!< CRCRDERR flag clear bit */\n\n/*******************  Bits definition for FLASH_OPTCR register  *******************/\n#define FLASH_OPTCR_OPTLOCK_Pos              (0U)\n#define FLASH_OPTCR_OPTLOCK_Msk              (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)  /*!< 0x00000001 */\n#define FLASH_OPTCR_OPTLOCK                  FLASH_OPTCR_OPTLOCK_Msk             /*!< FLASH_OPTCR lock option configuration bit */\n#define FLASH_OPTCR_OPTSTART_Pos             (1U)\n#define FLASH_OPTCR_OPTSTART_Msk             (0x1UL << FLASH_OPTCR_OPTSTART_Pos) /*!< 0x00000002 */\n#define FLASH_OPTCR_OPTSTART                 FLASH_OPTCR_OPTSTART_Msk            /*!< Option byte start change option configuration bit */\n#define FLASH_OPTCR_MER_Pos                  (4U)\n#define FLASH_OPTCR_MER_Msk                  (0x1UL << FLASH_OPTCR_MER_Pos)      /*!< 0x00000010 */\n#define FLASH_OPTCR_MER                      FLASH_OPTCR_MER_Msk                 /*!< Mass erase request */\n#define FLASH_OPTCR_OPTCHANGEERRIE_Pos       (30U)\n#define FLASH_OPTCR_OPTCHANGEERRIE_Msk       (0x1UL << FLASH_OPTCR_OPTCHANGEERRIE_Pos) /*!< 0x40000000 */\n#define FLASH_OPTCR_OPTCHANGEERRIE           FLASH_OPTCR_OPTCHANGEERRIE_Msk            /*!< Option byte change error interrupt enable bit */\n#define FLASH_OPTCR_SWAP_BANK_Pos            (31U)\n#define FLASH_OPTCR_SWAP_BANK_Msk            (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */\n#define FLASH_OPTCR_SWAP_BANK                FLASH_OPTCR_SWAP_BANK_Msk            /*!< Bank swapping option configuration bit */\n\n/*******************  Bits definition for FLASH_OPTSR register  ***************/\n#define FLASH_OPTSR_OPT_BUSY_Pos             (0U)\n#define FLASH_OPTSR_OPT_BUSY_Msk             (0x1UL << FLASH_OPTSR_OPT_BUSY_Pos) /*!< 0x00000001 */\n#define FLASH_OPTSR_OPT_BUSY                 FLASH_OPTSR_OPT_BUSY_Msk            /*!< Option byte change ongoing flag */\n#define FLASH_OPTSR_BOR_LEV_Pos              (2U)\n#define FLASH_OPTSR_BOR_LEV_Msk              (0x3UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x0000000C */\n#define FLASH_OPTSR_BOR_LEV                  FLASH_OPTSR_BOR_LEV_Msk            /*!< Brownout level option status bit */\n#define FLASH_OPTSR_BOR_LEV_0                (0x1UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000004 */\n#define FLASH_OPTSR_BOR_LEV_1                (0x2UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000008 */\n#define FLASH_OPTSR_IWDG1_SW_Pos             (4U)\n#define FLASH_OPTSR_IWDG1_SW_Msk             (0x1UL << FLASH_OPTSR_IWDG1_SW_Pos) /*!< 0x00000010 */\n#define FLASH_OPTSR_IWDG1_SW                 FLASH_OPTSR_IWDG1_SW_Msk            /*!< IWDG1 control mode option status bit */\n#define FLASH_OPTSR_NRST_STOP_D1_Pos         (6U)\n#define FLASH_OPTSR_NRST_STOP_D1_Msk         (0x1UL << FLASH_OPTSR_NRST_STOP_D1_Pos) /*!< 0x00000040 */\n#define FLASH_OPTSR_NRST_STOP_D1             FLASH_OPTSR_NRST_STOP_D1_Msk            /*!< D1 domain DStop entry reset option status bit */\n#define FLASH_OPTSR_NRST_STBY_D1_Pos         (7U)\n#define FLASH_OPTSR_NRST_STBY_D1_Msk         (0x1UL << FLASH_OPTSR_NRST_STBY_D1_Pos) /*!< 0x00000080 */\n#define FLASH_OPTSR_NRST_STBY_D1             FLASH_OPTSR_NRST_STBY_D1_Msk            /*!< D1 domain DStandby entry reset option status bit */\n#define FLASH_OPTSR_RDP_Pos                  (8U)\n#define FLASH_OPTSR_RDP_Msk                  (0xFFUL << FLASH_OPTSR_RDP_Pos)   /*!< 0x0000FF00 */\n#define FLASH_OPTSR_RDP                      FLASH_OPTSR_RDP_Msk               /*!< Readout protection level option status byte */\n#define FLASH_OPTSR_FZ_IWDG_STOP_Pos         (17U)\n#define FLASH_OPTSR_FZ_IWDG_STOP_Msk         (0x1UL << FLASH_OPTSR_FZ_IWDG_STOP_Pos) /*!< 0x00020000 */\n#define FLASH_OPTSR_FZ_IWDG_STOP             FLASH_OPTSR_FZ_IWDG_STOP_Msk            /*!< IWDG Stop mode freeze option status bit */\n#define FLASH_OPTSR_FZ_IWDG_SDBY_Pos         (18U)\n#define FLASH_OPTSR_FZ_IWDG_SDBY_Msk         (0x1UL << FLASH_OPTSR_FZ_IWDG_SDBY_Pos) /*!< 0x00040000 */\n#define FLASH_OPTSR_FZ_IWDG_SDBY             FLASH_OPTSR_FZ_IWDG_SDBY_Msk            /*!< IWDG Standby mode freeze option status bit */\n#define FLASH_OPTSR_ST_RAM_SIZE_Pos          (19U)\n#define FLASH_OPTSR_ST_RAM_SIZE_Msk          (0x3UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00180000 */\n#define FLASH_OPTSR_ST_RAM_SIZE              FLASH_OPTSR_ST_RAM_SIZE_Msk            /*!< ST RAM size option status */\n#define FLASH_OPTSR_ST_RAM_SIZE_0            (0x1UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00080000 */\n#define FLASH_OPTSR_ST_RAM_SIZE_1            (0x2UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00100000 */\n#define FLASH_OPTSR_SECURITY_Pos             (21U)\n#define FLASH_OPTSR_SECURITY_Msk             (0x1UL << FLASH_OPTSR_SECURITY_Pos) /*!< 0x00200000 */\n#define FLASH_OPTSR_SECURITY                 FLASH_OPTSR_SECURITY_Msk            /*!< Security enable option status bit */\n#define FLASH_OPTSR_IO_HSLV_Pos              (29U)\n#define FLASH_OPTSR_IO_HSLV_Msk              (0x1UL << FLASH_OPTSR_IO_HSLV_Pos) /*!< 0x20000000 */\n#define FLASH_OPTSR_IO_HSLV                  FLASH_OPTSR_IO_HSLV_Msk            /*!< I/O high-speed at low-voltage status bit */\n#define FLASH_OPTSR_OPTCHANGEERR_Pos         (30U)\n#define FLASH_OPTSR_OPTCHANGEERR_Msk         (0x1UL << FLASH_OPTSR_OPTCHANGEERR_Pos) /*!< 0x40000000 */\n#define FLASH_OPTSR_OPTCHANGEERR             FLASH_OPTSR_OPTCHANGEERR_Msk            /*!< Option byte change error flag */\n#define FLASH_OPTSR_SWAP_BANK_OPT_Pos        (31U)\n#define FLASH_OPTSR_SWAP_BANK_OPT_Msk        (0x1UL << FLASH_OPTSR_SWAP_BANK_OPT_Pos) /*!< 0x80000000 */\n#define FLASH_OPTSR_SWAP_BANK_OPT            FLASH_OPTSR_SWAP_BANK_OPT_Msk            /*!< Bank swapping option status bit */\n\n/*******************  Bits definition for FLASH_OPTCCR register  *******************/\n#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos    (30U)\n#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk    (0x1UL << FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos) /*!< 0x40000000 */\n#define FLASH_OPTCCR_CLR_OPTCHANGEERR        FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk            /*!< OPTCHANGEERR reset bit */\n\n/*******************  Bits definition for FLASH_PRAR register  *********************/\n#define FLASH_PRAR_PROT_AREA_START_Pos       (0U)\n#define FLASH_PRAR_PROT_AREA_START_Msk       (0xFFFUL << FLASH_PRAR_PROT_AREA_START_Pos) /*!< 0x00000FFF */\n#define FLASH_PRAR_PROT_AREA_START           FLASH_PRAR_PROT_AREA_START_Msk              /*!< PCROP area start status bits */\n#define FLASH_PRAR_PROT_AREA_END_Pos         (16U)\n#define FLASH_PRAR_PROT_AREA_END_Msk         (0xFFFUL << FLASH_PRAR_PROT_AREA_END_Pos) /*!< 0x0FFF0000 */\n#define FLASH_PRAR_PROT_AREA_END             FLASH_PRAR_PROT_AREA_END_Msk              /*!< PCROP area end status bits */\n#define FLASH_PRAR_DMEP_Pos                  (31U)\n#define FLASH_PRAR_DMEP_Msk                  (0x1UL << FLASH_PRAR_DMEP_Pos)    /*!< 0x80000000 */\n#define FLASH_PRAR_DMEP                      FLASH_PRAR_DMEP_Msk               /*!< PCROP protected erase enable option status bit */\n\n/*******************  Bits definition for FLASH_SCAR register  *********************/\n#define FLASH_SCAR_SEC_AREA_START_Pos        (0U)\n#define FLASH_SCAR_SEC_AREA_START_Msk        (0xFFFUL << FLASH_SCAR_SEC_AREA_START_Pos) /*!< 0x00000FFF */\n#define FLASH_SCAR_SEC_AREA_START            FLASH_SCAR_SEC_AREA_START_Msk              /*!< Secure-only area start status bits */\n#define FLASH_SCAR_SEC_AREA_END_Pos          (16U)\n#define FLASH_SCAR_SEC_AREA_END_Msk          (0xFFFUL << FLASH_SCAR_SEC_AREA_END_Pos) /*!< 0x0FFF0000 */\n#define FLASH_SCAR_SEC_AREA_END              FLASH_SCAR_SEC_AREA_END_Msk              /*!< Secure-only area end status bits */\n#define FLASH_SCAR_DMES_Pos                  (31U)\n#define FLASH_SCAR_DMES_Msk                  (0x1UL << FLASH_SCAR_DMES_Pos)    /*!< 0x80000000 */\n#define FLASH_SCAR_DMES                      FLASH_SCAR_DMES_Msk               /*!< Secure access protected erase enable option status bit */\n\n/*******************  Bits definition for FLASH_WPSN register  *********************/\n#define FLASH_WPSN_WRPSN_Pos                 (0U)\n#define FLASH_WPSN_WRPSN_Msk                 (0xFFUL << FLASH_WPSN_WRPSN_Pos)  /*!< 0x000000FF */\n#define FLASH_WPSN_WRPSN                     FLASH_WPSN_WRPSN_Msk              /*!< Sector write protection option status byte */\n\n/*******************  Bits definition for FLASH_BOOT_CUR register  ****************/\n#define FLASH_BOOT_ADD0_Pos                  (0U)\n#define FLASH_BOOT_ADD0_Msk                  (0xFFFFUL << FLASH_BOOT_ADD0_Pos) /*!< 0x0000FFFF */\n#define FLASH_BOOT_ADD0                      FLASH_BOOT_ADD0_Msk               /*!< Arm Cortex-M7 boot address 0 */\n#define FLASH_BOOT_ADD1_Pos                  (16U)\n#define FLASH_BOOT_ADD1_Msk                  (0xFFFFUL << FLASH_BOOT_ADD1_Pos) /*!< 0xFFFF0000 */\n#define FLASH_BOOT_ADD1                      FLASH_BOOT_ADD1_Msk               /*!< Arm Cortex-M7 boot address 1 */\n\n\n/*******************  Bits definition for FLASH_CRCCR register  ********************/\n#define FLASH_CRCCR_CRC_SECT_Pos             (0U)\n#define FLASH_CRCCR_CRC_SECT_Msk             (0x7UL << FLASH_CRCCR_CRC_SECT_Pos) /*!< 0x00000007 */\n#define FLASH_CRCCR_CRC_SECT                 FLASH_CRCCR_CRC_SECT_Msk            /*!< CRC sector number */\n#define FLASH_CRCCR_CRC_BY_SECT_Pos          (8U)\n#define FLASH_CRCCR_CRC_BY_SECT_Msk          (0x1UL << FLASH_CRCCR_CRC_BY_SECT_Pos) /*!< 0x00000100 */\n#define FLASH_CRCCR_CRC_BY_SECT              FLASH_CRCCR_CRC_BY_SECT_Msk            /*!< CRC sector mode select bit */\n#define FLASH_CRCCR_ADD_SECT_Pos             (9U)\n#define FLASH_CRCCR_ADD_SECT_Msk             (0x1UL << FLASH_CRCCR_ADD_SECT_Pos) /*!< 0x00000200 */\n#define FLASH_CRCCR_ADD_SECT                 FLASH_CRCCR_ADD_SECT_Msk            /*!< CRC sector select bit */\n#define FLASH_CRCCR_CLEAN_SECT_Pos           (10U)\n#define FLASH_CRCCR_CLEAN_SECT_Msk           (0x1UL << FLASH_CRCCR_CLEAN_SECT_Pos) /*!< 0x00000400 */\n#define FLASH_CRCCR_CLEAN_SECT               FLASH_CRCCR_CLEAN_SECT_Msk            /*!< CRC sector list clear bit */\n#define FLASH_CRCCR_START_CRC_Pos            (16U)\n#define FLASH_CRCCR_START_CRC_Msk            (0x1UL << FLASH_CRCCR_START_CRC_Pos) /*!< 0x00010000 */\n#define FLASH_CRCCR_START_CRC                FLASH_CRCCR_START_CRC_Msk            /*!< CRC start bit */\n#define FLASH_CRCCR_CLEAN_CRC_Pos            (17U)\n#define FLASH_CRCCR_CLEAN_CRC_Msk            (0x1UL << FLASH_CRCCR_CLEAN_CRC_Pos) /*!< 0x00020000 */\n#define FLASH_CRCCR_CLEAN_CRC                FLASH_CRCCR_CLEAN_CRC_Msk            /*!< CRC clear bit */\n#define FLASH_CRCCR_CRC_BURST_Pos            (20U)\n#define FLASH_CRCCR_CRC_BURST_Msk            (0x3UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00300000 */\n#define FLASH_CRCCR_CRC_BURST                FLASH_CRCCR_CRC_BURST_Msk            /*!< CRC burst size */\n#define FLASH_CRCCR_CRC_BURST_0              (0x1UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00100000 */\n#define FLASH_CRCCR_CRC_BURST_1              (0x2UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00200000 */\n#define FLASH_CRCCR_ALL_BANK_Pos             (22U)\n#define FLASH_CRCCR_ALL_BANK_Msk             (0x1UL << FLASH_CRCCR_ALL_BANK_Pos) /*!< 0x00400000 */\n#define FLASH_CRCCR_ALL_BANK                 FLASH_CRCCR_ALL_BANK_Msk            /*!< CRC select bit */\n\n/*******************  Bits definition for FLASH_CRCSADD register  ****************/\n#define FLASH_CRCSADD_CRC_START_ADDR_Pos     (0U)\n#define FLASH_CRCSADD_CRC_START_ADDR_Msk     (0xFFFFFFFFUL << FLASH_CRCSADD_CRC_START_ADDR_Pos) /*!< 0xFFFFFFFF */\n#define FLASH_CRCSADD_CRC_START_ADDR         FLASH_CRCSADD_CRC_START_ADDR_Msk                   /*!< CRC start address */\n\n/*******************  Bits definition for FLASH_CRCEADD register  ****************/\n#define FLASH_CRCEADD_CRC_END_ADDR_Pos       (0U)\n#define FLASH_CRCEADD_CRC_END_ADDR_Msk       (0xFFFFFFFFUL << FLASH_CRCEADD_CRC_END_ADDR_Pos) /*!< 0xFFFFFFFF */\n#define FLASH_CRCEADD_CRC_END_ADDR           FLASH_CRCEADD_CRC_END_ADDR_Msk                   /*!< CRC end address */\n\n/*******************  Bits definition for FLASH_CRCDATA register  ***************/\n#define FLASH_CRCDATA_CRC_DATA_Pos           (0U)\n#define FLASH_CRCDATA_CRC_DATA_Msk           (0xFFFFFFFFUL << FLASH_CRCDATA_CRC_DATA_Pos) /*!< 0xFFFFFFFF */\n#define FLASH_CRCDATA_CRC_DATA               FLASH_CRCDATA_CRC_DATA_Msk                   /*!< CRC result */\n\n/*******************  Bits definition for FLASH_ECC_FA register  *******************/\n#define FLASH_ECC_FA_FAIL_ECC_ADDR_Pos       (0U)\n#define FLASH_ECC_FA_FAIL_ECC_ADDR_Msk       (0x7FFFUL << FLASH_ECC_FA_FAIL_ECC_ADDR_Pos) /*!< 0x00007FFF */\n#define FLASH_ECC_FA_FAIL_ECC_ADDR           FLASH_ECC_FA_FAIL_ECC_ADDR_Msk               /*!< ECC error address */\n\n/******************************************************************************/\n/*                                                                            */\n/*                          Flexible Memory Controller                        */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bit definition for FMC_BCR1 register  *******************/\n#define FMC_BCR1_CCLKEN_Pos        (20U)\n#define FMC_BCR1_CCLKEN_Msk        (0x1UL << FMC_BCR1_CCLKEN_Pos)              /*!< 0x00100000 */\n#define FMC_BCR1_CCLKEN            FMC_BCR1_CCLKEN_Msk                         /*!<Continuous clock enable     */\n#define FMC_BCR1_WFDIS_Pos         (21U)\n#define FMC_BCR1_WFDIS_Msk         (0x1UL << FMC_BCR1_WFDIS_Pos)               /*!< 0x00200000 */\n#define FMC_BCR1_WFDIS             FMC_BCR1_WFDIS_Msk                          /*!<Write FIFO Disable         */\n\n#define FMC_BCR1_BMAP_Pos          (24U)\n#define FMC_BCR1_BMAP_Msk          (0x3UL << FMC_BCR1_BMAP_Pos)                /*!< 0x03000000 */\n#define FMC_BCR1_BMAP              FMC_BCR1_BMAP_Msk                           /*!<BMAP[1:0] FMC bank mapping */\n#define FMC_BCR1_BMAP_0            (0x1UL << FMC_BCR1_BMAP_Pos)                 /*!< 0x01000000 */\n#define FMC_BCR1_BMAP_1            (0x2UL << FMC_BCR1_BMAP_Pos)                 /*!< 0x02000000 */\n\n#define FMC_BCR1_FMCEN_Pos         (31U)\n#define FMC_BCR1_FMCEN_Msk         (0x1UL << FMC_BCR1_FMCEN_Pos)               /*!< 0x80000000 */\n#define FMC_BCR1_FMCEN             FMC_BCR1_FMCEN_Msk                          /*!<FMC controller Enable */\n/******************  Bit definition for FMC_BCRx registers (x=1..4)  *********/\n#define FMC_BCRx_MBKEN_Pos         (0U)\n#define FMC_BCRx_MBKEN_Msk         (0x1UL << FMC_BCRx_MBKEN_Pos)               /*!< 0x00000001 */\n#define FMC_BCRx_MBKEN             FMC_BCRx_MBKEN_Msk                          /*!<Memory bank enable bit                 */\n#define FMC_BCRx_MUXEN_Pos         (1U)\n#define FMC_BCRx_MUXEN_Msk         (0x1UL << FMC_BCRx_MUXEN_Pos)               /*!< 0x00000002 */\n#define FMC_BCRx_MUXEN             FMC_BCRx_MUXEN_Msk                          /*!<Address/data multiplexing enable bit   */\n\n#define FMC_BCRx_MTYP_Pos          (2U)\n#define FMC_BCRx_MTYP_Msk          (0x3UL << FMC_BCRx_MTYP_Pos)                /*!< 0x0000000C */\n#define FMC_BCRx_MTYP              FMC_BCRx_MTYP_Msk                           /*!<MTYP[1:0] bits (Memory type)           */\n#define FMC_BCRx_MTYP_0            (0x1UL << FMC_BCRx_MTYP_Pos)                 /*!< 0x00000004 */\n#define FMC_BCRx_MTYP_1            (0x2UL << FMC_BCRx_MTYP_Pos)                 /*!< 0x00000008 */\n\n#define FMC_BCRx_MWID_Pos          (4U)\n#define FMC_BCRx_MWID_Msk          (0x3UL << FMC_BCRx_MWID_Pos)                /*!< 0x00000030 */\n#define FMC_BCRx_MWID              FMC_BCRx_MWID_Msk                           /*!<MWID[1:0] bits (Memory data bus width) */\n#define FMC_BCRx_MWID_0            (0x1UL << FMC_BCRx_MWID_Pos)                 /*!< 0x00000010 */\n#define FMC_BCRx_MWID_1            (0x2UL << FMC_BCRx_MWID_Pos)                 /*!< 0x00000020 */\n\n#define FMC_BCRx_FACCEN_Pos        (6U)\n#define FMC_BCRx_FACCEN_Msk        (0x1UL << FMC_BCRx_FACCEN_Pos)              /*!< 0x00000040 */\n#define FMC_BCRx_FACCEN            FMC_BCRx_FACCEN_Msk                         /*!<Flash access enable        */\n#define FMC_BCRx_BURSTEN_Pos       (8U)\n#define FMC_BCRx_BURSTEN_Msk       (0x1UL << FMC_BCRx_BURSTEN_Pos)             /*!< 0x00000100 */\n#define FMC_BCRx_BURSTEN           FMC_BCRx_BURSTEN_Msk                        /*!<Burst enable bit           */\n#define FMC_BCRx_WAITPOL_Pos       (9U)\n#define FMC_BCRx_WAITPOL_Msk       (0x1UL << FMC_BCRx_WAITPOL_Pos)             /*!< 0x00000200 */\n#define FMC_BCRx_WAITPOL           FMC_BCRx_WAITPOL_Msk                        /*!<Wait signal polarity bit   */\n#define FMC_BCRx_WAITCFG_Pos       (11U)\n#define FMC_BCRx_WAITCFG_Msk       (0x1UL << FMC_BCRx_WAITCFG_Pos)             /*!< 0x00000800 */\n#define FMC_BCRx_WAITCFG           FMC_BCRx_WAITCFG_Msk                        /*!<Wait timing configuration  */\n#define FMC_BCRx_WREN_Pos          (12U)\n#define FMC_BCRx_WREN_Msk          (0x1UL << FMC_BCRx_WREN_Pos)                /*!< 0x00001000 */\n#define FMC_BCRx_WREN              FMC_BCRx_WREN_Msk                           /*!<Write enable bit           */\n#define FMC_BCRx_WAITEN_Pos        (13U)\n#define FMC_BCRx_WAITEN_Msk        (0x1UL << FMC_BCRx_WAITEN_Pos)              /*!< 0x00002000 */\n#define FMC_BCRx_WAITEN            FMC_BCRx_WAITEN_Msk                         /*!<Wait enable bit            */\n#define FMC_BCRx_EXTMOD_Pos        (14U)\n#define FMC_BCRx_EXTMOD_Msk        (0x1UL << FMC_BCRx_EXTMOD_Pos)              /*!< 0x00004000 */\n#define FMC_BCRx_EXTMOD            FMC_BCRx_EXTMOD_Msk                         /*!<Extended mode enable       */\n#define FMC_BCRx_ASYNCWAIT_Pos     (15U)\n#define FMC_BCRx_ASYNCWAIT_Msk     (0x1UL << FMC_BCRx_ASYNCWAIT_Pos)           /*!< 0x00008000 */\n#define FMC_BCRx_ASYNCWAIT         FMC_BCRx_ASYNCWAIT_Msk                      /*!<Asynchronous wait          */\n\n#define FMC_BCRx_CPSIZE_Pos        (16U)\n#define FMC_BCRx_CPSIZE_Msk        (0x7UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00070000 */\n#define FMC_BCRx_CPSIZE            FMC_BCRx_CPSIZE_Msk                         /*!<PSIZE[2:0] bits CRAM Page Size */\n#define FMC_BCRx_CPSIZE_0          (0x1UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00010000 */\n#define FMC_BCRx_CPSIZE_1          (0x2UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00020000 */\n#define FMC_BCRx_CPSIZE_2          (0x4UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00040000 */\n\n#define FMC_BCRx_CBURSTRW_Pos      (19U)\n#define FMC_BCRx_CBURSTRW_Msk      (0x1UL << FMC_BCRx_CBURSTRW_Pos)            /*!< 0x00080000 */\n#define FMC_BCRx_CBURSTRW          FMC_BCRx_CBURSTRW_Msk                       /*!<Write burst enable         */\n\n/******************  Bit definition for FMC_BTRx registers (x=1..4)  *********/\n#define FMC_BTRx_ADDSET_Pos        (0U)\n#define FMC_BTRx_ADDSET_Msk        (0xFUL << FMC_BTRx_ADDSET_Pos)              /*!< 0x0000000F */\n#define FMC_BTRx_ADDSET            FMC_BTRx_ADDSET_Msk                         /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FMC_BTRx_ADDSET_0          (0x1UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000001 */\n#define FMC_BTRx_ADDSET_1          (0x2UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000002 */\n#define FMC_BTRx_ADDSET_2          (0x4UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000004 */\n#define FMC_BTRx_ADDSET_3          (0x8UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000008 */\n\n#define FMC_BTRx_ADDHLD_Pos        (4U)\n#define FMC_BTRx_ADDHLD_Msk        (0xFUL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x000000F0 */\n#define FMC_BTRx_ADDHLD            FMC_BTRx_ADDHLD_Msk                         /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */\n#define FMC_BTRx_ADDHLD_0          (0x1UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000010 */\n#define FMC_BTRx_ADDHLD_1          (0x2UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000020 */\n#define FMC_BTRx_ADDHLD_2          (0x4UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000040 */\n#define FMC_BTRx_ADDHLD_3          (0x8UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000080 */\n\n#define FMC_BTRx_DATAST_Pos        (8U)\n#define FMC_BTRx_DATAST_Msk        (0xFFUL << FMC_BTRx_DATAST_Pos)             /*!< 0x0000FF00 */\n#define FMC_BTRx_DATAST            FMC_BTRx_DATAST_Msk                         /*!<DATAST [3:0] bits (Data-phase duration) */\n#define FMC_BTRx_DATAST_0          (0x01UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000100 */\n#define FMC_BTRx_DATAST_1          (0x02UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000200 */\n#define FMC_BTRx_DATAST_2          (0x04UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000400 */\n#define FMC_BTRx_DATAST_3          (0x08UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000800 */\n#define FMC_BTRx_DATAST_4          (0x10UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00001000 */\n#define FMC_BTRx_DATAST_5          (0x20UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00002000 */\n#define FMC_BTRx_DATAST_6          (0x40UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00004000 */\n#define FMC_BTRx_DATAST_7          (0x80UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00008000 */\n\n#define FMC_BTRx_BUSTURN_Pos       (16U)\n#define FMC_BTRx_BUSTURN_Msk       (0xFUL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x000F0000 */\n#define FMC_BTRx_BUSTURN           FMC_BTRx_BUSTURN_Msk                        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\n#define FMC_BTRx_BUSTURN_0         (0x1UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00010000 */\n#define FMC_BTRx_BUSTURN_1         (0x2UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00020000 */\n#define FMC_BTRx_BUSTURN_2         (0x4UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00040000 */\n#define FMC_BTRx_BUSTURN_3         (0x8UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00080000 */\n\n#define FMC_BTRx_CLKDIV_Pos        (20U)\n#define FMC_BTRx_CLKDIV_Msk        (0xFUL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00F00000 */\n#define FMC_BTRx_CLKDIV            FMC_BTRx_CLKDIV_Msk                         /*!<CLKDIV[3:0] bits (Clock divide ratio) */\n#define FMC_BTRx_CLKDIV_0          (0x1UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00100000 */\n#define FMC_BTRx_CLKDIV_1          (0x2UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00200000 */\n#define FMC_BTRx_CLKDIV_2          (0x4UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00400000 */\n#define FMC_BTRx_CLKDIV_3          (0x8UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00800000 */\n\n#define FMC_BTRx_DATLAT_Pos        (24U)\n#define FMC_BTRx_DATLAT_Msk        (0xFUL << FMC_BTRx_DATLAT_Pos)              /*!< 0x0F000000 */\n#define FMC_BTRx_DATLAT            FMC_BTRx_DATLAT_Msk                         /*!<DATLA[3:0] bits (Data latency) */\n#define FMC_BTRx_DATLAT_0          (0x1UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x01000000 */\n#define FMC_BTRx_DATLAT_1          (0x2UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x02000000 */\n#define FMC_BTRx_DATLAT_2          (0x4UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x04000000 */\n#define FMC_BTRx_DATLAT_3          (0x8UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x08000000 */\n\n#define FMC_BTRx_ACCMOD_Pos        (28U)\n#define FMC_BTRx_ACCMOD_Msk        (0x3UL << FMC_BTRx_ACCMOD_Pos)              /*!< 0x30000000 */\n#define FMC_BTRx_ACCMOD            FMC_BTRx_ACCMOD_Msk                         /*!<ACCMOD[1:0] bits (Access mode) */\n#define FMC_BTRx_ACCMOD_0          (0x1UL << FMC_BTRx_ACCMOD_Pos)               /*!< 0x10000000 */\n#define FMC_BTRx_ACCMOD_1          (0x2UL << FMC_BTRx_ACCMOD_Pos)               /*!< 0x20000000 */\n\n/******************  Bit definition for FMC_BWTRx registers (x=1..4)  *********/\n#define FMC_BWTRx_ADDSET_Pos       (0U)\n#define FMC_BWTRx_ADDSET_Msk       (0xFUL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x0000000F */\n#define FMC_BWTRx_ADDSET           FMC_BWTRx_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FMC_BWTRx_ADDSET_0         (0x1UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000001 */\n#define FMC_BWTRx_ADDSET_1         (0x2UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000002 */\n#define FMC_BWTRx_ADDSET_2         (0x4UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000004 */\n#define FMC_BWTRx_ADDSET_3         (0x8UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000008 */\n\n#define FMC_BWTRx_ADDHLD_Pos       (4U)\n#define FMC_BWTRx_ADDHLD_Msk       (0xFUL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x000000F0 */\n#define FMC_BWTRx_ADDHLD           FMC_BWTRx_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FMC_BWTRx_ADDHLD_0         (0x1UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000010 */\n#define FMC_BWTRx_ADDHLD_1         (0x2UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000020 */\n#define FMC_BWTRx_ADDHLD_2         (0x4UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000040 */\n#define FMC_BWTRx_ADDHLD_3         (0x8UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000080 */\n\n#define FMC_BWTRx_DATAST_Pos       (8U)\n#define FMC_BWTRx_DATAST_Msk       (0xFFUL << FMC_BWTRx_DATAST_Pos)            /*!< 0x0000FF00 */\n#define FMC_BWTRx_DATAST           FMC_BWTRx_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */\n#define FMC_BWTRx_DATAST_0         (0x01UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000100 */\n#define FMC_BWTRx_DATAST_1         (0x02UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000200 */\n#define FMC_BWTRx_DATAST_2         (0x04UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000400 */\n#define FMC_BWTRx_DATAST_3         (0x08UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000800 */\n#define FMC_BWTRx_DATAST_4         (0x10UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00001000 */\n#define FMC_BWTRx_DATAST_5         (0x20UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00002000 */\n#define FMC_BWTRx_DATAST_6         (0x40UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00004000 */\n#define FMC_BWTRx_DATAST_7         (0x80UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00008000 */\n\n#define FMC_BWTRx_BUSTURN_Pos      (16U)\n#define FMC_BWTRx_BUSTURN_Msk      (0xFUL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x000F0000 */\n#define FMC_BWTRx_BUSTURN          FMC_BWTRx_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\n#define FMC_BWTRx_BUSTURN_0        (0x1UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00010000 */\n#define FMC_BWTRx_BUSTURN_1        (0x2UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00020000 */\n#define FMC_BWTRx_BUSTURN_2        (0x4UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00040000 */\n#define FMC_BWTRx_BUSTURN_3        (0x8UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00080000 */\n\n#define FMC_BWTRx_ACCMOD_Pos       (28U)\n#define FMC_BWTRx_ACCMOD_Msk       (0x3UL << FMC_BWTRx_ACCMOD_Pos)             /*!< 0x30000000 */\n#define FMC_BWTRx_ACCMOD           FMC_BWTRx_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */\n#define FMC_BWTRx_ACCMOD_0         (0x1UL << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x10000000 */\n#define FMC_BWTRx_ACCMOD_1         (0x2UL << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x20000000 */\n\n/******************  Bit definition for FMC_PCR register  *******************/\n#define FMC_PCR_PWAITEN_Pos        (1U)\n#define FMC_PCR_PWAITEN_Msk        (0x1UL << FMC_PCR_PWAITEN_Pos)              /*!< 0x00000002 */\n#define FMC_PCR_PWAITEN            FMC_PCR_PWAITEN_Msk                         /*!<Wait feature enable bit                   */\n#define FMC_PCR_PBKEN_Pos          (2U)\n#define FMC_PCR_PBKEN_Msk          (0x1UL << FMC_PCR_PBKEN_Pos)                /*!< 0x00000004 */\n#define FMC_PCR_PBKEN              FMC_PCR_PBKEN_Msk                           /*!<NAND Flash memory bank enable bit */\n\n#define FMC_PCR_PWID_Pos           (4U)\n#define FMC_PCR_PWID_Msk           (0x3UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000030 */\n#define FMC_PCR_PWID               FMC_PCR_PWID_Msk                            /*!<PWID[1:0] bits (NAND Flash databus width) */\n#define FMC_PCR_PWID_0             (0x1UL << FMC_PCR_PWID_Pos)                  /*!< 0x00000010 */\n#define FMC_PCR_PWID_1             (0x2UL << FMC_PCR_PWID_Pos)                  /*!< 0x00000020 */\n\n#define FMC_PCR_ECCEN_Pos          (6U)\n#define FMC_PCR_ECCEN_Msk          (0x1UL << FMC_PCR_ECCEN_Pos)                /*!< 0x00000040 */\n#define FMC_PCR_ECCEN              FMC_PCR_ECCEN_Msk                           /*!<ECC computation logic enable bit          */\n\n#define FMC_PCR_TCLR_Pos           (9U)\n#define FMC_PCR_TCLR_Msk           (0xFUL << FMC_PCR_TCLR_Pos)                 /*!< 0x00001E00 */\n#define FMC_PCR_TCLR               FMC_PCR_TCLR_Msk                            /*!<TCLR[3:0] bits (CLE to RE delay)          */\n#define FMC_PCR_TCLR_0             (0x1UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000200 */\n#define FMC_PCR_TCLR_1             (0x2UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000400 */\n#define FMC_PCR_TCLR_2             (0x4UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000800 */\n#define FMC_PCR_TCLR_3             (0x8UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00001000 */\n\n#define FMC_PCR_TAR_Pos            (13U)\n#define FMC_PCR_TAR_Msk            (0xFUL << FMC_PCR_TAR_Pos)                  /*!< 0x0001E000 */\n#define FMC_PCR_TAR                FMC_PCR_TAR_Msk                             /*!<TAR[3:0] bits (ALE to RE delay)           */\n#define FMC_PCR_TAR_0              (0x1UL << FMC_PCR_TAR_Pos)                   /*!< 0x00002000 */\n#define FMC_PCR_TAR_1              (0x2UL << FMC_PCR_TAR_Pos)                   /*!< 0x00004000 */\n#define FMC_PCR_TAR_2              (0x4UL << FMC_PCR_TAR_Pos)                   /*!< 0x00008000 */\n#define FMC_PCR_TAR_3              (0x8UL << FMC_PCR_TAR_Pos)                   /*!< 0x00010000 */\n\n#define FMC_PCR_ECCPS_Pos          (17U)\n#define FMC_PCR_ECCPS_Msk          (0x7UL << FMC_PCR_ECCPS_Pos)                /*!< 0x000E0000 */\n#define FMC_PCR_ECCPS              FMC_PCR_ECCPS_Msk                           /*!<ECCPS[1:0] bits (ECC page size)           */\n#define FMC_PCR_ECCPS_0            (0x1UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00020000 */\n#define FMC_PCR_ECCPS_1            (0x2UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00040000 */\n#define FMC_PCR_ECCPS_2            (0x4UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00080000 */\n\n/*******************  Bit definition for FMC_SR register  *******************/\n#define FMC_SR_IRS_Pos             (0U)\n#define FMC_SR_IRS_Msk             (0x1UL << FMC_SR_IRS_Pos)                   /*!< 0x00000001 */\n#define FMC_SR_IRS                 FMC_SR_IRS_Msk                              /*!<Interrupt Rising Edge status                */\n#define FMC_SR_ILS_Pos             (1U)\n#define FMC_SR_ILS_Msk             (0x1UL << FMC_SR_ILS_Pos)                   /*!< 0x00000002 */\n#define FMC_SR_ILS                 FMC_SR_ILS_Msk                              /*!<Interrupt Level status                      */\n#define FMC_SR_IFS_Pos             (2U)\n#define FMC_SR_IFS_Msk             (0x1UL << FMC_SR_IFS_Pos)                   /*!< 0x00000004 */\n#define FMC_SR_IFS                 FMC_SR_IFS_Msk                              /*!<Interrupt Falling Edge status               */\n#define FMC_SR_IREN_Pos            (3U)\n#define FMC_SR_IREN_Msk            (0x1UL << FMC_SR_IREN_Pos)                  /*!< 0x00000008 */\n#define FMC_SR_IREN                FMC_SR_IREN_Msk                             /*!<Interrupt Rising Edge detection Enable bit  */\n#define FMC_SR_ILEN_Pos            (4U)\n#define FMC_SR_ILEN_Msk            (0x1UL << FMC_SR_ILEN_Pos)                  /*!< 0x00000010 */\n#define FMC_SR_ILEN                FMC_SR_ILEN_Msk                             /*!<Interrupt Level detection Enable bit        */\n#define FMC_SR_IFEN_Pos            (5U)\n#define FMC_SR_IFEN_Msk            (0x1UL << FMC_SR_IFEN_Pos)                  /*!< 0x00000020 */\n#define FMC_SR_IFEN                FMC_SR_IFEN_Msk                             /*!<Interrupt Falling Edge detection Enable bit */\n#define FMC_SR_FEMPT_Pos           (6U)\n#define FMC_SR_FEMPT_Msk           (0x1UL << FMC_SR_FEMPT_Pos)                 /*!< 0x00000040 */\n#define FMC_SR_FEMPT               FMC_SR_FEMPT_Msk                            /*!<FIFO empty                                  */\n\n/******************  Bit definition for FMC_PMEM register  ******************/\n#define FMC_PMEM_MEMSET_Pos       (0U)\n#define FMC_PMEM_MEMSET_Msk       (0xFFUL << FMC_PMEM_MEMSET_Pos)            /*!< 0x000000FF */\n#define FMC_PMEM_MEMSET           FMC_PMEM_MEMSET_Msk                        /*!<MEMSET[7:0] bits (Common memory setup time) */\n#define FMC_PMEM_MEMSET_0         (0x01UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000001 */\n#define FMC_PMEM_MEMSET_1         (0x02UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000002 */\n#define FMC_PMEM_MEMSET_2         (0x04UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000004 */\n#define FMC_PMEM_MEMSET_3         (0x08UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000008 */\n#define FMC_PMEM_MEMSET_4         (0x10UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000010 */\n#define FMC_PMEM_MEMSET_5         (0x20UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000020 */\n#define FMC_PMEM_MEMSET_6         (0x40UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000040 */\n#define FMC_PMEM_MEMSET_7         (0x80UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000080 */\n\n#define FMC_PMEM_MEMWAIT_Pos      (8U)\n#define FMC_PMEM_MEMWAIT_Msk      (0xFFUL << FMC_PMEM_MEMWAIT_Pos)           /*!< 0x0000FF00 */\n#define FMC_PMEM_MEMWAIT          FMC_PMEM_MEMWAIT_Msk                       /*!<MEMWAIT[7:0] bits (Common memory wait time) */\n#define FMC_PMEM_MEMWAIT_0        (0x01UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000100 */\n#define FMC_PMEM_MEMWAIT_1        (0x02UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000200 */\n#define FMC_PMEM_MEMWAIT_2        (0x04UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000400 */\n#define FMC_PMEM_MEMWAIT_3        (0x08UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000800 */\n#define FMC_PMEM_MEMWAIT_4        (0x10UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00001000 */\n#define FMC_PMEM_MEMWAIT_5        (0x20UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00002000 */\n#define FMC_PMEM_MEMWAIT_6        (0x40UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00004000 */\n#define FMC_PMEM_MEMWAIT_7        (0x80UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00008000 */\n\n#define FMC_PMEM_MEMHOLD_Pos      (16U)\n#define FMC_PMEM_MEMHOLD_Msk      (0xFFUL << FMC_PMEM_MEMHOLD_Pos)           /*!< 0x00FF0000 */\n#define FMC_PMEM_MEMHOLD          FMC_PMEM_MEMHOLD_Msk                       /*!<MEMHOLD[7:0] bits (Common memory hold time) */\n#define FMC_PMEM_MEMHOLD_0        (0x01UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00010000 */\n#define FMC_PMEM_MEMHOLD_1        (0x02UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00020000 */\n#define FMC_PMEM_MEMHOLD_2        (0x04UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00040000 */\n#define FMC_PMEM_MEMHOLD_3        (0x08UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00080000 */\n#define FMC_PMEM_MEMHOLD_4        (0x10UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00100000 */\n#define FMC_PMEM_MEMHOLD_5        (0x20UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00200000 */\n#define FMC_PMEM_MEMHOLD_6        (0x40UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00400000 */\n#define FMC_PMEM_MEMHOLD_7        (0x80UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00800000 */\n\n#define FMC_PMEM_MEMHIZ_Pos       (24U)\n#define FMC_PMEM_MEMHIZ_Msk       (0xFFUL << FMC_PMEM_MEMHIZ_Pos)            /*!< 0xFF000000 */\n#define FMC_PMEM_MEMHIZ           FMC_PMEM_MEMHIZ_Msk                        /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */\n#define FMC_PMEM_MEMHIZ_0         (0x01UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x01000000 */\n#define FMC_PMEM_MEMHIZ_1         (0x02UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x02000000 */\n#define FMC_PMEM_MEMHIZ_2         (0x04UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x04000000 */\n#define FMC_PMEM_MEMHIZ_3         (0x08UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x08000000 */\n#define FMC_PMEM_MEMHIZ_4         (0x10UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x10000000 */\n#define FMC_PMEM_MEMHIZ_5         (0x20UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x20000000 */\n#define FMC_PMEM_MEMHIZ_6         (0x40UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x40000000 */\n#define FMC_PMEM_MEMHIZ_7         (0x80UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x80000000 */\n\n/******************  Bit definition for FMC_PATT register  ******************/\n#define FMC_PATT_ATTSET_Pos       (0U)\n#define FMC_PATT_ATTSET_Msk       (0xFFUL << FMC_PATT_ATTSET_Pos)            /*!< 0x000000FF */\n#define FMC_PATT_ATTSET           FMC_PATT_ATTSET_Msk                        /*!<ATTSET[7:0] bits (Attribute memory setup time) */\n#define FMC_PATT_ATTSET_0         (0x01UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000001 */\n#define FMC_PATT_ATTSET_1         (0x02UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000002 */\n#define FMC_PATT_ATTSET_2         (0x04UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000004 */\n#define FMC_PATT_ATTSET_3         (0x08UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000008 */\n#define FMC_PATT_ATTSET_4         (0x10UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000010 */\n#define FMC_PATT_ATTSET_5         (0x20UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000020 */\n#define FMC_PATT_ATTSET_6         (0x40UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000040 */\n#define FMC_PATT_ATTSET_7         (0x80UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000080 */\n\n#define FMC_PATT_ATTWAIT_Pos      (8U)\n#define FMC_PATT_ATTWAIT_Msk      (0xFFUL << FMC_PATT_ATTWAIT_Pos)           /*!< 0x0000FF00 */\n#define FMC_PATT_ATTWAIT          FMC_PATT_ATTWAIT_Msk                       /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */\n#define FMC_PATT_ATTWAIT_0        (0x01UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000100 */\n#define FMC_PATT_ATTWAIT_1        (0x02UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000200 */\n#define FMC_PATT_ATTWAIT_2        (0x04UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000400 */\n#define FMC_PATT_ATTWAIT_3        (0x08UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000800 */\n#define FMC_PATT_ATTWAIT_4        (0x10UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00001000 */\n#define FMC_PATT_ATTWAIT_5        (0x20UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00002000 */\n#define FMC_PATT_ATTWAIT_6        (0x40UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00004000 */\n#define FMC_PATT_ATTWAIT_7        (0x80UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00008000 */\n\n#define FMC_PATT_ATTHOLD_Pos      (16U)\n#define FMC_PATT_ATTHOLD_Msk      (0xFFUL << FMC_PATT_ATTHOLD_Pos)           /*!< 0x00FF0000 */\n#define FMC_PATT_ATTHOLD          FMC_PATT_ATTHOLD_Msk                       /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */\n#define FMC_PATT_ATTHOLD_0        (0x01UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00010000 */\n#define FMC_PATT_ATTHOLD_1        (0x02UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00020000 */\n#define FMC_PATT_ATTHOLD_2        (0x04UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00040000 */\n#define FMC_PATT_ATTHOLD_3        (0x08UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00080000 */\n#define FMC_PATT_ATTHOLD_4        (0x10UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00100000 */\n#define FMC_PATT_ATTHOLD_5        (0x20UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00200000 */\n#define FMC_PATT_ATTHOLD_6        (0x40UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00400000 */\n#define FMC_PATT_ATTHOLD_7        (0x80UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00800000 */\n\n#define FMC_PATT_ATTHIZ_Pos       (24U)\n#define FMC_PATT_ATTHIZ_Msk       (0xFFUL << FMC_PATT_ATTHIZ_Pos)            /*!< 0xFF000000 */\n#define FMC_PATT_ATTHIZ           FMC_PATT_ATTHIZ_Msk                        /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */\n#define FMC_PATT_ATTHIZ_0         (0x01UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x01000000 */\n#define FMC_PATT_ATTHIZ_1         (0x02UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x02000000 */\n#define FMC_PATT_ATTHIZ_2         (0x04UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x04000000 */\n#define FMC_PATT_ATTHIZ_3         (0x08UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x08000000 */\n#define FMC_PATT_ATTHIZ_4         (0x10UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x10000000 */\n#define FMC_PATT_ATTHIZ_5         (0x20UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x20000000 */\n#define FMC_PATT_ATTHIZ_6         (0x40UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x40000000 */\n#define FMC_PATT_ATTHIZ_7         (0x80UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x80000000 */\n\n/******************  Bit definition for FMC_ECCR3 register  ******************/\n#define FMC_ECCR3_ECC3_Pos         (0U)\n#define FMC_ECCR3_ECC3_Msk         (0xFFFFFFFFUL << FMC_ECCR3_ECC3_Pos)        /*!< 0xFFFFFFFF */\n#define FMC_ECCR3_ECC3             FMC_ECCR3_ECC3_Msk                          /*!<ECC result */\n\n/******************  Bit definition for FMC_SDCRx registers (x=1..4)  *********/\n#define FMC_SDCRx_NC_Pos           (0U)\n#define FMC_SDCRx_NC_Msk           (0x3UL << FMC_SDCRx_NC_Pos)                 /*!< 0x00000003 */\n#define FMC_SDCRx_NC               FMC_SDCRx_NC_Msk                            /*!<NC[1:0] bits (Number of column bits) */\n#define FMC_SDCRx_NC_0             (0x1UL << FMC_SDCRx_NC_Pos)                  /*!< 0x00000001 */\n#define FMC_SDCRx_NC_1             (0x2UL << FMC_SDCRx_NC_Pos)                  /*!< 0x00000002 */\n\n#define FMC_SDCRx_NR_Pos           (2U)\n#define FMC_SDCRx_NR_Msk           (0x3UL << FMC_SDCRx_NR_Pos)                 /*!< 0x0000000C */\n#define FMC_SDCRx_NR               FMC_SDCRx_NR_Msk                            /*!<NR[1:0] bits (Number of row bits) */\n#define FMC_SDCRx_NR_0             (0x1UL << FMC_SDCRx_NR_Pos)                  /*!< 0x00000004 */\n#define FMC_SDCRx_NR_1             (0x2UL << FMC_SDCRx_NR_Pos)                  /*!< 0x00000008 */\n\n#define FMC_SDCRx_MWID_Pos         (4U)\n#define FMC_SDCRx_MWID_Msk         (0x3UL << FMC_SDCRx_MWID_Pos)               /*!< 0x00000030 */\n#define FMC_SDCRx_MWID             FMC_SDCRx_MWID_Msk                          /*!<NR[1:0] bits (Number of row bits) */\n#define FMC_SDCRx_MWID_0           (0x1UL << FMC_SDCRx_MWID_Pos)                /*!< 0x00000010 */\n#define FMC_SDCRx_MWID_1           (0x2UL << FMC_SDCRx_MWID_Pos)                /*!< 0x00000020 */\n\n#define FMC_SDCRx_NB_Pos           (6U)\n#define FMC_SDCRx_NB_Msk           (0x1UL << FMC_SDCRx_NB_Pos)                 /*!< 0x00000040 */\n#define FMC_SDCRx_NB               FMC_SDCRx_NB_Msk                            /*!<Number of internal bank */\n\n#define FMC_SDCRx_CAS_Pos          (7U)\n#define FMC_SDCRx_CAS_Msk          (0x3UL << FMC_SDCRx_CAS_Pos)                /*!< 0x00000180 */\n#define FMC_SDCRx_CAS              FMC_SDCRx_CAS_Msk                           /*!<CAS[1:0] bits (CAS latency) */\n#define FMC_SDCRx_CAS_0            (0x1UL << FMC_SDCRx_CAS_Pos)                 /*!< 0x00000080 */\n#define FMC_SDCRx_CAS_1            (0x2UL << FMC_SDCRx_CAS_Pos)                 /*!< 0x00000100 */\n\n#define FMC_SDCRx_WP_Pos           (9U)\n#define FMC_SDCRx_WP_Msk           (0x1UL << FMC_SDCRx_WP_Pos)                 /*!< 0x00000200 */\n#define FMC_SDCRx_WP               FMC_SDCRx_WP_Msk                            /*!<Write protection */\n\n#define FMC_SDCRx_SDCLK_Pos        (10U)\n#define FMC_SDCRx_SDCLK_Msk        (0x3UL << FMC_SDCRx_SDCLK_Pos)              /*!< 0x00000C00 */\n#define FMC_SDCRx_SDCLK            FMC_SDCRx_SDCLK_Msk                         /*!<SDRAM clock configuration */\n#define FMC_SDCRx_SDCLK_0          (0x1UL << FMC_SDCRx_SDCLK_Pos)               /*!< 0x00000400 */\n#define FMC_SDCRx_SDCLK_1          (0x2UL << FMC_SDCRx_SDCLK_Pos)               /*!< 0x00000800 */\n\n#define FMC_SDCRx_RBURST_Pos       (12U)\n#define FMC_SDCRx_RBURST_Msk       (0x1UL << FMC_SDCRx_RBURST_Pos)             /*!< 0x00001000 */\n#define FMC_SDCRx_RBURST           FMC_SDCRx_RBURST_Msk                        /*!<Read burst */\n\n#define FMC_SDCRx_RPIPE_Pos        (13U)\n#define FMC_SDCRx_RPIPE_Msk        (0x3UL << FMC_SDCRx_RPIPE_Pos)              /*!< 0x00006000 */\n#define FMC_SDCRx_RPIPE            FMC_SDCRx_RPIPE_Msk                         /*!<Write protection */\n#define FMC_SDCRx_RPIPE_0          (0x1UL << FMC_SDCRx_RPIPE_Pos)               /*!< 0x00002000 */\n#define FMC_SDCRx_RPIPE_1          (0x2UL << FMC_SDCRx_RPIPE_Pos)               /*!< 0x00004000 */\n\n/******************  Bit definition for FMC_SDTRx(1,2) register  ******************/\n#define FMC_SDTRx_TMRD_Pos         (0U)\n#define FMC_SDTRx_TMRD_Msk         (0xFUL << FMC_SDTRx_TMRD_Pos)               /*!< 0x0000000F */\n#define FMC_SDTRx_TMRD             FMC_SDTRx_TMRD_Msk                          /*!<TMRD[3:0] bits (Load mode register to active) */\n#define FMC_SDTRx_TMRD_0           (0x1UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000001 */\n#define FMC_SDTRx_TMRD_1           (0x2UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000002 */\n#define FMC_SDTRx_TMRD_2           (0x4UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000004 */\n#define FMC_SDTRx_TMRD_3           (0x8UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000008 */\n\n#define FMC_SDTRx_TXSR_Pos         (4U)\n#define FMC_SDTRx_TXSR_Msk         (0xFUL << FMC_SDTRx_TXSR_Pos)               /*!< 0x000000F0 */\n#define FMC_SDTRx_TXSR             FMC_SDTRx_TXSR_Msk                          /*!<TXSR[3:0] bits (Exit self refresh) */\n#define FMC_SDTRx_TXSR_0           (0x1UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000010 */\n#define FMC_SDTRx_TXSR_1           (0x2UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000020 */\n#define FMC_SDTRx_TXSR_2           (0x4UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000040 */\n#define FMC_SDTRx_TXSR_3           (0x8UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000080 */\n\n#define FMC_SDTRx_TRAS_Pos         (8U)\n#define FMC_SDTRx_TRAS_Msk         (0xFUL << FMC_SDTRx_TRAS_Pos)               /*!< 0x00000F00 */\n#define FMC_SDTRx_TRAS             FMC_SDTRx_TRAS_Msk                          /*!<TRAS[3:0] bits (Self refresh time) */\n#define FMC_SDTRx_TRAS_0           (0x1UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000100 */\n#define FMC_SDTRx_TRAS_1           (0x2UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000200 */\n#define FMC_SDTRx_TRAS_2           (0x4UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000400 */\n#define FMC_SDTRx_TRAS_3           (0x8UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000800 */\n\n#define FMC_SDTRx_TRC_Pos          (12U)\n#define FMC_SDTRx_TRC_Msk          (0xFUL << FMC_SDTRx_TRC_Pos)                /*!< 0x0000F000 */\n#define FMC_SDTRx_TRC              FMC_SDTRx_TRC_Msk                           /*!<TRC[2:0] bits (Row cycle delay) */\n#define FMC_SDTRx_TRC_0            (0x1UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00001000 */\n#define FMC_SDTRx_TRC_1            (0x2UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00002000 */\n#define FMC_SDTRx_TRC_2            (0x4UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00004000 */\n\n#define FMC_SDTRx_TWR_Pos          (16U)\n#define FMC_SDTRx_TWR_Msk          (0xFUL << FMC_SDTRx_TWR_Pos)                /*!< 0x000F0000 */\n#define FMC_SDTRx_TWR              FMC_SDTRx_TWR_Msk                           /*!<TRC[2:0] bits (Write recovery delay) */\n#define FMC_SDTRx_TWR_0            (0x1UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00010000 */\n#define FMC_SDTRx_TWR_1            (0x2UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00020000 */\n#define FMC_SDTRx_TWR_2            (0x4UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00040000 */\n\n#define FMC_SDTRx_TRP_Pos          (20U)\n#define FMC_SDTRx_TRP_Msk          (0xFUL << FMC_SDTRx_TRP_Pos)                /*!< 0x00F00000 */\n#define FMC_SDTRx_TRP              FMC_SDTRx_TRP_Msk                           /*!<TRP[2:0] bits (Row precharge delay) */\n#define FMC_SDTRx_TRP_0            (0x1UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00100000 */\n#define FMC_SDTRx_TRP_1            (0x2UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00200000 */\n#define FMC_SDTRx_TRP_2            (0x4UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00400000 */\n\n#define FMC_SDTRx_TRCD_Pos         (24U)\n#define FMC_SDTRx_TRCD_Msk         (0xFUL << FMC_SDTRx_TRCD_Pos)               /*!< 0x0F000000 */\n#define FMC_SDTRx_TRCD             FMC_SDTRx_TRCD_Msk                          /*!<TRP[2:0] bits (Row to column delay) */\n#define FMC_SDTRx_TRCD_0           (0x1UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x01000000 */\n#define FMC_SDTRx_TRCD_1           (0x2UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x02000000 */\n#define FMC_SDTRx_TRCD_2           (0x4UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x04000000 */\n\n/******************  Bit definition for FMC_SDCMR register  ******************/\n#define FMC_SDCMR_MODE_Pos         (0U)\n#define FMC_SDCMR_MODE_Msk         (0x7UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000007 */\n#define FMC_SDCMR_MODE             FMC_SDCMR_MODE_Msk                          /*!<MODE[2:0] bits (Command mode) */\n#define FMC_SDCMR_MODE_0           (0x1UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000001 */\n#define FMC_SDCMR_MODE_1           (0x2UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000002 */\n#define FMC_SDCMR_MODE_2           (0x3UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000003 */\n\n#define FMC_SDCMR_CTB2_Pos         (3U)\n#define FMC_SDCMR_CTB2_Msk         (0x1UL << FMC_SDCMR_CTB2_Pos)               /*!< 0x00000008 */\n#define FMC_SDCMR_CTB2             FMC_SDCMR_CTB2_Msk                          /*!<Command target 2 */\n\n#define FMC_SDCMR_CTB1_Pos         (4U)\n#define FMC_SDCMR_CTB1_Msk         (0x1UL << FMC_SDCMR_CTB1_Pos)               /*!< 0x00000010 */\n#define FMC_SDCMR_CTB1             FMC_SDCMR_CTB1_Msk                          /*!<Command target 1 */\n\n#define FMC_SDCMR_NRFS_Pos         (5U)\n#define FMC_SDCMR_NRFS_Msk         (0xFUL << FMC_SDCMR_NRFS_Pos)               /*!< 0x000001E0 */\n#define FMC_SDCMR_NRFS             FMC_SDCMR_NRFS_Msk                          /*!<NRFS[3:0] bits (Number of auto-refresh) */\n#define FMC_SDCMR_NRFS_0           (0x1UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000020 */\n#define FMC_SDCMR_NRFS_1           (0x2UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000040 */\n#define FMC_SDCMR_NRFS_2           (0x4UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000080 */\n#define FMC_SDCMR_NRFS_3           (0x8UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000100 */\n\n#define FMC_SDCMR_MRD_Pos          (9U)\n#define FMC_SDCMR_MRD_Msk          (0x1FFFUL << FMC_SDCMR_MRD_Pos)             /*!< 0x003FFE00 */\n#define FMC_SDCMR_MRD              FMC_SDCMR_MRD_Msk                           /*!<MRD[12:0] bits (Mode register definition) */\n\n/******************  Bit definition for FMC_SDRTR register  ******************/\n#define FMC_SDRTR_CRE_Pos          (0U)\n#define FMC_SDRTR_CRE_Msk          (0x1UL << FMC_SDRTR_CRE_Pos)                /*!< 0x00000001 */\n#define FMC_SDRTR_CRE              FMC_SDRTR_CRE_Msk                           /*!<Clear refresh error flag */\n\n#define FMC_SDRTR_COUNT_Pos        (1U)\n#define FMC_SDRTR_COUNT_Msk        (0x1FFFUL << FMC_SDRTR_COUNT_Pos)           /*!< 0x00003FFE */\n#define FMC_SDRTR_COUNT            FMC_SDRTR_COUNT_Msk                         /*!<COUNT[12:0] bits (Refresh timer count) */\n\n#define FMC_SDRTR_REIE_Pos         (14U)\n#define FMC_SDRTR_REIE_Msk         (0x1UL << FMC_SDRTR_REIE_Pos)               /*!< 0x00004000 */\n#define FMC_SDRTR_REIE             FMC_SDRTR_REIE_Msk                          /*!<RES interrupt enable */\n\n/******************  Bit definition for FMC_SDSR register  ******************/\n#define FMC_SDSR_RE_Pos            (0U)\n#define FMC_SDSR_RE_Msk            (0x1UL << FMC_SDSR_RE_Pos)                  /*!< 0x00000001 */\n#define FMC_SDSR_RE                FMC_SDSR_RE_Msk                             /*!<Refresh error flag */\n\n#define FMC_SDSR_MODES1_Pos        (1U)\n#define FMC_SDSR_MODES1_Msk        (0x3UL << FMC_SDSR_MODES1_Pos)              /*!< 0x00000006 */\n#define FMC_SDSR_MODES1            FMC_SDSR_MODES1_Msk                         /*!<MODES1[1:0]bits (Status mode for bank 1) */\n#define FMC_SDSR_MODES1_0          (0x1UL << FMC_SDSR_MODES1_Pos)               /*!< 0x00000002 */\n#define FMC_SDSR_MODES1_1          (0x2UL << FMC_SDSR_MODES1_Pos)               /*!< 0x00000004 */\n\n#define FMC_SDSR_MODES2_Pos        (3U)\n#define FMC_SDSR_MODES2_Msk        (0x3UL << FMC_SDSR_MODES2_Pos)              /*!< 0x00000018 */\n#define FMC_SDSR_MODES2            FMC_SDSR_MODES2_Msk                         /*!<MODES2[1:0]bits (Status mode for bank 2) */\n#define FMC_SDSR_MODES2_0          (0x1UL << FMC_SDSR_MODES2_Pos)               /*!< 0x00000008 */\n#define FMC_SDSR_MODES2_1          (0x2UL << FMC_SDSR_MODES2_Pos)               /*!< 0x00000010 */\n\n/******************************************************************************/\n/*                                                                            */\n/*                            General Purpose I/O                             */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bits definition for GPIO_MODER register  *****************/\n#define GPIO_MODER_MODE0_Pos           (0U)\n#define GPIO_MODER_MODE0_Msk           (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */\n#define GPIO_MODER_MODE0               GPIO_MODER_MODE0_Msk\n#define GPIO_MODER_MODE0_0             (0x1UL << GPIO_MODER_MODE0_Pos)          /*!< 0x00000001 */\n#define GPIO_MODER_MODE0_1             (0x2UL << GPIO_MODER_MODE0_Pos)          /*!< 0x00000002 */\n\n#define GPIO_MODER_MODE1_Pos           (2U)\n#define GPIO_MODER_MODE1_Msk           (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */\n#define GPIO_MODER_MODE1               GPIO_MODER_MODE1_Msk\n#define GPIO_MODER_MODE1_0             (0x1UL << GPIO_MODER_MODE1_Pos)          /*!< 0x00000004 */\n#define GPIO_MODER_MODE1_1             (0x2UL << GPIO_MODER_MODE1_Pos)          /*!< 0x00000008 */\n\n#define GPIO_MODER_MODE2_Pos           (4U)\n#define GPIO_MODER_MODE2_Msk           (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */\n#define GPIO_MODER_MODE2               GPIO_MODER_MODE2_Msk\n#define GPIO_MODER_MODE2_0             (0x1UL << GPIO_MODER_MODE2_Pos)          /*!< 0x00000010 */\n#define GPIO_MODER_MODE2_1             (0x2UL << GPIO_MODER_MODE2_Pos)          /*!< 0x00000020 */\n\n#define GPIO_MODER_MODE3_Pos           (6U)\n#define GPIO_MODER_MODE3_Msk           (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */\n#define GPIO_MODER_MODE3               GPIO_MODER_MODE3_Msk\n#define GPIO_MODER_MODE3_0             (0x1UL << GPIO_MODER_MODE3_Pos)          /*!< 0x00000040 */\n#define GPIO_MODER_MODE3_1             (0x2UL << GPIO_MODER_MODE3_Pos)          /*!< 0x00000080 */\n\n#define GPIO_MODER_MODE4_Pos           (8U)\n#define GPIO_MODER_MODE4_Msk           (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */\n#define GPIO_MODER_MODE4               GPIO_MODER_MODE4_Msk\n#define GPIO_MODER_MODE4_0             (0x1UL << GPIO_MODER_MODE4_Pos)          /*!< 0x00000100 */\n#define GPIO_MODER_MODE4_1             (0x2UL << GPIO_MODER_MODE4_Pos)          /*!< 0x00000200 */\n\n#define GPIO_MODER_MODE5_Pos           (10U)\n#define GPIO_MODER_MODE5_Msk           (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */\n#define GPIO_MODER_MODE5               GPIO_MODER_MODE5_Msk\n#define GPIO_MODER_MODE5_0             (0x1UL << GPIO_MODER_MODE5_Pos)          /*!< 0x00000400 */\n#define GPIO_MODER_MODE5_1             (0x2UL << GPIO_MODER_MODE5_Pos)          /*!< 0x00000800 */\n\n#define GPIO_MODER_MODE6_Pos           (12U)\n#define GPIO_MODER_MODE6_Msk           (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */\n#define GPIO_MODER_MODE6               GPIO_MODER_MODE6_Msk\n#define GPIO_MODER_MODE6_0             (0x1UL << GPIO_MODER_MODE6_Pos)          /*!< 0x00001000 */\n#define GPIO_MODER_MODE6_1             (0x2UL << GPIO_MODER_MODE6_Pos)          /*!< 0x00002000 */\n\n#define GPIO_MODER_MODE7_Pos           (14U)\n#define GPIO_MODER_MODE7_Msk           (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */\n#define GPIO_MODER_MODE7               GPIO_MODER_MODE7_Msk\n#define GPIO_MODER_MODE7_0             (0x1UL << GPIO_MODER_MODE7_Pos)          /*!< 0x00004000 */\n#define GPIO_MODER_MODE7_1             (0x2UL << GPIO_MODER_MODE7_Pos)          /*!< 0x00008000 */\n\n#define GPIO_MODER_MODE8_Pos           (16U)\n#define GPIO_MODER_MODE8_Msk           (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */\n#define GPIO_MODER_MODE8               GPIO_MODER_MODE8_Msk\n#define GPIO_MODER_MODE8_0             (0x1UL << GPIO_MODER_MODE8_Pos)          /*!< 0x00010000 */\n#define GPIO_MODER_MODE8_1             (0x2UL << GPIO_MODER_MODE8_Pos)          /*!< 0x00020000 */\n\n#define GPIO_MODER_MODE9_Pos           (18U)\n#define GPIO_MODER_MODE9_Msk           (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */\n#define GPIO_MODER_MODE9               GPIO_MODER_MODE9_Msk\n#define GPIO_MODER_MODE9_0             (0x1UL << GPIO_MODER_MODE9_Pos)          /*!< 0x00040000 */\n#define GPIO_MODER_MODE9_1             (0x2UL << GPIO_MODER_MODE9_Pos)          /*!< 0x00080000 */\n\n#define GPIO_MODER_MODE10_Pos          (20U)\n#define GPIO_MODER_MODE10_Msk          (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */\n#define GPIO_MODER_MODE10              GPIO_MODER_MODE10_Msk\n#define GPIO_MODER_MODE10_0            (0x1UL << GPIO_MODER_MODE10_Pos)         /*!< 0x00100000 */\n#define GPIO_MODER_MODE10_1            (0x2UL << GPIO_MODER_MODE10_Pos)         /*!< 0x00200000 */\n\n#define GPIO_MODER_MODE11_Pos          (22U)\n#define GPIO_MODER_MODE11_Msk          (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */\n#define GPIO_MODER_MODE11              GPIO_MODER_MODE11_Msk\n#define GPIO_MODER_MODE11_0            (0x1UL << GPIO_MODER_MODE11_Pos)         /*!< 0x00400000 */\n#define GPIO_MODER_MODE11_1            (0x2UL << GPIO_MODER_MODE11_Pos)         /*!< 0x00800000 */\n\n#define GPIO_MODER_MODE12_Pos          (24U)\n#define GPIO_MODER_MODE12_Msk          (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */\n#define GPIO_MODER_MODE12              GPIO_MODER_MODE12_Msk\n#define GPIO_MODER_MODE12_0            (0x1UL << GPIO_MODER_MODE12_Pos)         /*!< 0x01000000 */\n#define GPIO_MODER_MODE12_1            (0x2UL << GPIO_MODER_MODE12_Pos)         /*!< 0x02000000 */\n\n#define GPIO_MODER_MODE13_Pos          (26U)\n#define GPIO_MODER_MODE13_Msk          (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */\n#define GPIO_MODER_MODE13              GPIO_MODER_MODE13_Msk\n#define GPIO_MODER_MODE13_0            (0x1UL << GPIO_MODER_MODE13_Pos)         /*!< 0x04000000 */\n#define GPIO_MODER_MODE13_1            (0x2UL << GPIO_MODER_MODE13_Pos)         /*!< 0x08000000 */\n\n#define GPIO_MODER_MODE14_Pos          (28U)\n#define GPIO_MODER_MODE14_Msk          (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */\n#define GPIO_MODER_MODE14              GPIO_MODER_MODE14_Msk\n#define GPIO_MODER_MODE14_0            (0x1UL << GPIO_MODER_MODE14_Pos)         /*!< 0x10000000 */\n#define GPIO_MODER_MODE14_1            (0x2UL << GPIO_MODER_MODE14_Pos)         /*!< 0x20000000 */\n\n#define GPIO_MODER_MODE15_Pos          (30U)\n#define GPIO_MODER_MODE15_Msk          (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */\n#define GPIO_MODER_MODE15              GPIO_MODER_MODE15_Msk\n#define GPIO_MODER_MODE15_0            (0x1UL << GPIO_MODER_MODE15_Pos)         /*!< 0x40000000 */\n#define GPIO_MODER_MODE15_1            (0x2UL << GPIO_MODER_MODE15_Pos)         /*!< 0x80000000 */\n\n/******************  Bits definition for GPIO_OTYPER register  ****************/\n#define GPIO_OTYPER_OT0_Pos            (0U)\n#define GPIO_OTYPER_OT0_Msk            (0x1UL << GPIO_OTYPER_OT0_Pos)          /*!< 0x00000001 */\n#define GPIO_OTYPER_OT0                GPIO_OTYPER_OT0_Msk\n#define GPIO_OTYPER_OT1_Pos            (1U)\n#define GPIO_OTYPER_OT1_Msk            (0x1UL << GPIO_OTYPER_OT1_Pos)          /*!< 0x00000002 */\n#define GPIO_OTYPER_OT1                GPIO_OTYPER_OT1_Msk\n#define GPIO_OTYPER_OT2_Pos            (2U)\n#define GPIO_OTYPER_OT2_Msk            (0x1UL << GPIO_OTYPER_OT2_Pos)          /*!< 0x00000004 */\n#define GPIO_OTYPER_OT2                GPIO_OTYPER_OT2_Msk\n#define GPIO_OTYPER_OT3_Pos            (3U)\n#define GPIO_OTYPER_OT3_Msk            (0x1UL << GPIO_OTYPER_OT3_Pos)          /*!< 0x00000008 */\n#define GPIO_OTYPER_OT3                GPIO_OTYPER_OT3_Msk\n#define GPIO_OTYPER_OT4_Pos            (4U)\n#define GPIO_OTYPER_OT4_Msk            (0x1UL << GPIO_OTYPER_OT4_Pos)          /*!< 0x00000010 */\n#define GPIO_OTYPER_OT4                GPIO_OTYPER_OT4_Msk\n#define GPIO_OTYPER_OT5_Pos            (5U)\n#define GPIO_OTYPER_OT5_Msk            (0x1UL << GPIO_OTYPER_OT5_Pos)          /*!< 0x00000020 */\n#define GPIO_OTYPER_OT5                GPIO_OTYPER_OT5_Msk\n#define GPIO_OTYPER_OT6_Pos            (6U)\n#define GPIO_OTYPER_OT6_Msk            (0x1UL << GPIO_OTYPER_OT6_Pos)          /*!< 0x00000040 */\n#define GPIO_OTYPER_OT6                GPIO_OTYPER_OT6_Msk\n#define GPIO_OTYPER_OT7_Pos            (7U)\n#define GPIO_OTYPER_OT7_Msk            (0x1UL << GPIO_OTYPER_OT7_Pos)          /*!< 0x00000080 */\n#define GPIO_OTYPER_OT7                GPIO_OTYPER_OT7_Msk\n#define GPIO_OTYPER_OT8_Pos            (8U)\n#define GPIO_OTYPER_OT8_Msk            (0x1UL << GPIO_OTYPER_OT8_Pos)          /*!< 0x00000100 */\n#define GPIO_OTYPER_OT8                GPIO_OTYPER_OT8_Msk\n#define GPIO_OTYPER_OT9_Pos            (9U)\n#define GPIO_OTYPER_OT9_Msk            (0x1UL << GPIO_OTYPER_OT9_Pos)          /*!< 0x00000200 */\n#define GPIO_OTYPER_OT9                GPIO_OTYPER_OT9_Msk\n#define GPIO_OTYPER_OT10_Pos           (10U)\n#define GPIO_OTYPER_OT10_Msk           (0x1UL << GPIO_OTYPER_OT10_Pos)         /*!< 0x00000400 */\n#define GPIO_OTYPER_OT10               GPIO_OTYPER_OT10_Msk\n#define GPIO_OTYPER_OT11_Pos           (11U)\n#define GPIO_OTYPER_OT11_Msk           (0x1UL << GPIO_OTYPER_OT11_Pos)         /*!< 0x00000800 */\n#define GPIO_OTYPER_OT11               GPIO_OTYPER_OT11_Msk\n#define GPIO_OTYPER_OT12_Pos           (12U)\n#define GPIO_OTYPER_OT12_Msk           (0x1UL << GPIO_OTYPER_OT12_Pos)         /*!< 0x00001000 */\n#define GPIO_OTYPER_OT12               GPIO_OTYPER_OT12_Msk\n#define GPIO_OTYPER_OT13_Pos           (13U)\n#define GPIO_OTYPER_OT13_Msk           (0x1UL << GPIO_OTYPER_OT13_Pos)         /*!< 0x00002000 */\n#define GPIO_OTYPER_OT13               GPIO_OTYPER_OT13_Msk\n#define GPIO_OTYPER_OT14_Pos           (14U)\n#define GPIO_OTYPER_OT14_Msk           (0x1UL << GPIO_OTYPER_OT14_Pos)         /*!< 0x00004000 */\n#define GPIO_OTYPER_OT14               GPIO_OTYPER_OT14_Msk\n#define GPIO_OTYPER_OT15_Pos           (15U)\n#define GPIO_OTYPER_OT15_Msk           (0x1UL << GPIO_OTYPER_OT15_Pos)         /*!< 0x00008000 */\n#define GPIO_OTYPER_OT15               GPIO_OTYPER_OT15_Msk\n\n/******************  Bits definition for GPIO_OSPEEDR register  ***************/\n#define GPIO_OSPEEDR_OSPEED0_Pos       (0U)\n#define GPIO_OSPEEDR_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000003 */\n#define GPIO_OSPEEDR_OSPEED0           GPIO_OSPEEDR_OSPEED0_Msk\n#define GPIO_OSPEEDR_OSPEED0_0         (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000001 */\n#define GPIO_OSPEEDR_OSPEED0_1         (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000002 */\n\n#define GPIO_OSPEEDR_OSPEED1_Pos       (2U)\n#define GPIO_OSPEEDR_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x0000000C */\n#define GPIO_OSPEEDR_OSPEED1           GPIO_OSPEEDR_OSPEED1_Msk\n#define GPIO_OSPEEDR_OSPEED1_0         (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000004 */\n#define GPIO_OSPEEDR_OSPEED1_1         (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000008 */\n\n#define GPIO_OSPEEDR_OSPEED2_Pos       (4U)\n#define GPIO_OSPEEDR_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000030 */\n#define GPIO_OSPEEDR_OSPEED2           GPIO_OSPEEDR_OSPEED2_Msk\n#define GPIO_OSPEEDR_OSPEED2_0         (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000010 */\n#define GPIO_OSPEEDR_OSPEED2_1         (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000020 */\n\n#define GPIO_OSPEEDR_OSPEED3_Pos       (6U)\n#define GPIO_OSPEEDR_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x000000C0 */\n#define GPIO_OSPEEDR_OSPEED3           GPIO_OSPEEDR_OSPEED3_Msk\n#define GPIO_OSPEEDR_OSPEED3_0         (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000040 */\n#define GPIO_OSPEEDR_OSPEED3_1         (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000080 */\n\n#define GPIO_OSPEEDR_OSPEED4_Pos       (8U)\n#define GPIO_OSPEEDR_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000300 */\n#define GPIO_OSPEEDR_OSPEED4           GPIO_OSPEEDR_OSPEED4_Msk\n#define GPIO_OSPEEDR_OSPEED4_0         (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000100 */\n#define GPIO_OSPEEDR_OSPEED4_1         (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000200 */\n\n#define GPIO_OSPEEDR_OSPEED5_Pos       (10U)\n#define GPIO_OSPEEDR_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000C00 */\n#define GPIO_OSPEEDR_OSPEED5           GPIO_OSPEEDR_OSPEED5_Msk\n#define GPIO_OSPEEDR_OSPEED5_0         (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000400 */\n#define GPIO_OSPEEDR_OSPEED5_1         (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000800 */\n\n#define GPIO_OSPEEDR_OSPEED6_Pos       (12U)\n#define GPIO_OSPEEDR_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00003000 */\n#define GPIO_OSPEEDR_OSPEED6           GPIO_OSPEEDR_OSPEED6_Msk\n#define GPIO_OSPEEDR_OSPEED6_0         (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00001000 */\n#define GPIO_OSPEEDR_OSPEED6_1         (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00002000 */\n\n#define GPIO_OSPEEDR_OSPEED7_Pos       (14U)\n#define GPIO_OSPEEDR_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x0000C000 */\n#define GPIO_OSPEEDR_OSPEED7           GPIO_OSPEEDR_OSPEED7_Msk\n#define GPIO_OSPEEDR_OSPEED7_0         (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00004000 */\n#define GPIO_OSPEEDR_OSPEED7_1         (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00008000 */\n\n#define GPIO_OSPEEDR_OSPEED8_Pos       (16U)\n#define GPIO_OSPEEDR_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00030000 */\n#define GPIO_OSPEEDR_OSPEED8           GPIO_OSPEEDR_OSPEED8_Msk\n#define GPIO_OSPEEDR_OSPEED8_0         (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00010000 */\n#define GPIO_OSPEEDR_OSPEED8_1         (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00020000 */\n\n#define GPIO_OSPEEDR_OSPEED9_Pos       (18U)\n#define GPIO_OSPEEDR_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x000C0000 */\n#define GPIO_OSPEEDR_OSPEED9           GPIO_OSPEEDR_OSPEED9_Msk\n#define GPIO_OSPEEDR_OSPEED9_0         (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00040000 */\n#define GPIO_OSPEEDR_OSPEED9_1         (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00080000 */\n\n#define GPIO_OSPEEDR_OSPEED10_Pos      (20U)\n#define GPIO_OSPEEDR_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00300000 */\n#define GPIO_OSPEEDR_OSPEED10          GPIO_OSPEEDR_OSPEED10_Msk\n#define GPIO_OSPEEDR_OSPEED10_0        (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00100000 */\n#define GPIO_OSPEEDR_OSPEED10_1        (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00200000 */\n\n#define GPIO_OSPEEDR_OSPEED11_Pos      (22U)\n#define GPIO_OSPEEDR_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00C00000 */\n#define GPIO_OSPEEDR_OSPEED11          GPIO_OSPEEDR_OSPEED11_Msk\n#define GPIO_OSPEEDR_OSPEED11_0        (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00400000 */\n#define GPIO_OSPEEDR_OSPEED11_1        (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00800000 */\n\n#define GPIO_OSPEEDR_OSPEED12_Pos      (24U)\n#define GPIO_OSPEEDR_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x03000000 */\n#define GPIO_OSPEEDR_OSPEED12          GPIO_OSPEEDR_OSPEED12_Msk\n#define GPIO_OSPEEDR_OSPEED12_0        (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x01000000 */\n#define GPIO_OSPEEDR_OSPEED12_1        (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x02000000 */\n\n#define GPIO_OSPEEDR_OSPEED13_Pos      (26U)\n#define GPIO_OSPEEDR_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x0C000000 */\n#define GPIO_OSPEEDR_OSPEED13          GPIO_OSPEEDR_OSPEED13_Msk\n#define GPIO_OSPEEDR_OSPEED13_0        (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x04000000 */\n#define GPIO_OSPEEDR_OSPEED13_1        (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x08000000 */\n\n#define GPIO_OSPEEDR_OSPEED14_Pos      (28U)\n#define GPIO_OSPEEDR_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x30000000 */\n#define GPIO_OSPEEDR_OSPEED14          GPIO_OSPEEDR_OSPEED14_Msk\n#define GPIO_OSPEEDR_OSPEED14_0        (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x10000000 */\n#define GPIO_OSPEEDR_OSPEED14_1        (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x20000000 */\n\n#define GPIO_OSPEEDR_OSPEED15_Pos      (30U)\n#define GPIO_OSPEEDR_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0xC0000000 */\n#define GPIO_OSPEEDR_OSPEED15          GPIO_OSPEEDR_OSPEED15_Msk\n#define GPIO_OSPEEDR_OSPEED15_0        (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x40000000 */\n#define GPIO_OSPEEDR_OSPEED15_1        (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x80000000 */\n\n/******************  Bits definition for GPIO_PUPDR register  *****************/\n#define GPIO_PUPDR_PUPD0_Pos           (0U)\n#define GPIO_PUPDR_PUPD0_Msk           (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */\n#define GPIO_PUPDR_PUPD0               GPIO_PUPDR_PUPD0_Msk\n#define GPIO_PUPDR_PUPD0_0             (0x1UL << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000001 */\n#define GPIO_PUPDR_PUPD0_1             (0x2UL << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000002 */\n\n#define GPIO_PUPDR_PUPD1_Pos           (2U)\n#define GPIO_PUPDR_PUPD1_Msk           (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */\n#define GPIO_PUPDR_PUPD1               GPIO_PUPDR_PUPD1_Msk\n#define GPIO_PUPDR_PUPD1_0             (0x1UL << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000004 */\n#define GPIO_PUPDR_PUPD1_1             (0x2UL << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000008 */\n\n#define GPIO_PUPDR_PUPD2_Pos           (4U)\n#define GPIO_PUPDR_PUPD2_Msk           (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */\n#define GPIO_PUPDR_PUPD2               GPIO_PUPDR_PUPD2_Msk\n#define GPIO_PUPDR_PUPD2_0             (0x1UL << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000010 */\n#define GPIO_PUPDR_PUPD2_1             (0x2UL << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000020 */\n\n#define GPIO_PUPDR_PUPD3_Pos           (6U)\n#define GPIO_PUPDR_PUPD3_Msk           (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */\n#define GPIO_PUPDR_PUPD3               GPIO_PUPDR_PUPD3_Msk\n#define GPIO_PUPDR_PUPD3_0             (0x1UL << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000040 */\n#define GPIO_PUPDR_PUPD3_1             (0x2UL << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000080 */\n\n#define GPIO_PUPDR_PUPD4_Pos           (8U)\n#define GPIO_PUPDR_PUPD4_Msk           (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */\n#define GPIO_PUPDR_PUPD4               GPIO_PUPDR_PUPD4_Msk\n#define GPIO_PUPDR_PUPD4_0             (0x1UL << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000100 */\n#define GPIO_PUPDR_PUPD4_1             (0x2UL << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000200 */\n\n#define GPIO_PUPDR_PUPD5_Pos           (10U)\n#define GPIO_PUPDR_PUPD5_Msk           (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */\n#define GPIO_PUPDR_PUPD5               GPIO_PUPDR_PUPD5_Msk\n#define GPIO_PUPDR_PUPD5_0             (0x1UL << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000400 */\n#define GPIO_PUPDR_PUPD5_1             (0x2UL << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000800 */\n\n#define GPIO_PUPDR_PUPD6_Pos           (12U)\n#define GPIO_PUPDR_PUPD6_Msk           (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */\n#define GPIO_PUPDR_PUPD6               GPIO_PUPDR_PUPD6_Msk\n#define GPIO_PUPDR_PUPD6_0             (0x1UL << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00001000 */\n#define GPIO_PUPDR_PUPD6_1             (0x2UL << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00002000 */\n\n#define GPIO_PUPDR_PUPD7_Pos           (14U)\n#define GPIO_PUPDR_PUPD7_Msk           (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */\n#define GPIO_PUPDR_PUPD7               GPIO_PUPDR_PUPD7_Msk\n#define GPIO_PUPDR_PUPD7_0             (0x1UL << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00004000 */\n#define GPIO_PUPDR_PUPD7_1             (0x2UL << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00008000 */\n\n#define GPIO_PUPDR_PUPD8_Pos           (16U)\n#define GPIO_PUPDR_PUPD8_Msk           (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */\n#define GPIO_PUPDR_PUPD8               GPIO_PUPDR_PUPD8_Msk\n#define GPIO_PUPDR_PUPD8_0             (0x1UL << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00010000 */\n#define GPIO_PUPDR_PUPD8_1             (0x2UL << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00020000 */\n\n#define GPIO_PUPDR_PUPD9_Pos           (18U)\n#define GPIO_PUPDR_PUPD9_Msk           (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */\n#define GPIO_PUPDR_PUPD9               GPIO_PUPDR_PUPD9_Msk\n#define GPIO_PUPDR_PUPD9_0             (0x1UL << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00040000 */\n#define GPIO_PUPDR_PUPD9_1             (0x2UL << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00080000 */\n\n#define GPIO_PUPDR_PUPD10_Pos          (20U)\n#define GPIO_PUPDR_PUPD10_Msk          (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */\n#define GPIO_PUPDR_PUPD10              GPIO_PUPDR_PUPD10_Msk\n#define GPIO_PUPDR_PUPD10_0            (0x1UL << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00100000 */\n#define GPIO_PUPDR_PUPD10_1            (0x2UL << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00200000 */\n\n#define GPIO_PUPDR_PUPD11_Pos          (22U)\n#define GPIO_PUPDR_PUPD11_Msk          (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */\n#define GPIO_PUPDR_PUPD11              GPIO_PUPDR_PUPD11_Msk\n#define GPIO_PUPDR_PUPD11_0            (0x1UL << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00400000 */\n#define GPIO_PUPDR_PUPD11_1            (0x2UL << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00800000 */\n\n#define GPIO_PUPDR_PUPD12_Pos          (24U)\n#define GPIO_PUPDR_PUPD12_Msk          (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */\n#define GPIO_PUPDR_PUPD12              GPIO_PUPDR_PUPD12_Msk\n#define GPIO_PUPDR_PUPD12_0            (0x1UL << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x01000000 */\n#define GPIO_PUPDR_PUPD12_1            (0x2UL << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x02000000 */\n\n#define GPIO_PUPDR_PUPD13_Pos          (26U)\n#define GPIO_PUPDR_PUPD13_Msk          (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */\n#define GPIO_PUPDR_PUPD13              GPIO_PUPDR_PUPD13_Msk\n#define GPIO_PUPDR_PUPD13_0            (0x1UL << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x04000000 */\n#define GPIO_PUPDR_PUPD13_1            (0x2UL << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x08000000 */\n\n#define GPIO_PUPDR_PUPD14_Pos          (28U)\n#define GPIO_PUPDR_PUPD14_Msk          (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */\n#define GPIO_PUPDR_PUPD14              GPIO_PUPDR_PUPD14_Msk\n#define GPIO_PUPDR_PUPD14_0            (0x1UL << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x10000000 */\n#define GPIO_PUPDR_PUPD14_1            (0x2UL << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x20000000 */\n\n#define GPIO_PUPDR_PUPD15_Pos          (30U)\n#define GPIO_PUPDR_PUPD15_Msk          (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */\n#define GPIO_PUPDR_PUPD15              GPIO_PUPDR_PUPD15_Msk\n#define GPIO_PUPDR_PUPD15_0            (0x1UL << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x40000000 */\n#define GPIO_PUPDR_PUPD15_1            (0x2UL << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x80000000 */\n\n/******************  Bits definition for GPIO_IDR register  *******************/\n#define GPIO_IDR_ID0_Pos               (0U)\n#define GPIO_IDR_ID0_Msk               (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */\n#define GPIO_IDR_ID0                   GPIO_IDR_ID0_Msk\n#define GPIO_IDR_ID1_Pos               (1U)\n#define GPIO_IDR_ID1_Msk               (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */\n#define GPIO_IDR_ID1                   GPIO_IDR_ID1_Msk\n#define GPIO_IDR_ID2_Pos               (2U)\n#define GPIO_IDR_ID2_Msk               (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */\n#define GPIO_IDR_ID2                   GPIO_IDR_ID2_Msk\n#define GPIO_IDR_ID3_Pos               (3U)\n#define GPIO_IDR_ID3_Msk               (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */\n#define GPIO_IDR_ID3                   GPIO_IDR_ID3_Msk\n#define GPIO_IDR_ID4_Pos               (4U)\n#define GPIO_IDR_ID4_Msk               (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */\n#define GPIO_IDR_ID4                   GPIO_IDR_ID4_Msk\n#define GPIO_IDR_ID5_Pos               (5U)\n#define GPIO_IDR_ID5_Msk               (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */\n#define GPIO_IDR_ID5                   GPIO_IDR_ID5_Msk\n#define GPIO_IDR_ID6_Pos               (6U)\n#define GPIO_IDR_ID6_Msk               (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */\n#define GPIO_IDR_ID6                   GPIO_IDR_ID6_Msk\n#define GPIO_IDR_ID7_Pos               (7U)\n#define GPIO_IDR_ID7_Msk               (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */\n#define GPIO_IDR_ID7                   GPIO_IDR_ID7_Msk\n#define GPIO_IDR_ID8_Pos               (8U)\n#define GPIO_IDR_ID8_Msk               (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */\n#define GPIO_IDR_ID8                   GPIO_IDR_ID8_Msk\n#define GPIO_IDR_ID9_Pos               (9U)\n#define GPIO_IDR_ID9_Msk               (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */\n#define GPIO_IDR_ID9                   GPIO_IDR_ID9_Msk\n#define GPIO_IDR_ID10_Pos              (10U)\n#define GPIO_IDR_ID10_Msk              (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */\n#define GPIO_IDR_ID10                  GPIO_IDR_ID10_Msk\n#define GPIO_IDR_ID11_Pos              (11U)\n#define GPIO_IDR_ID11_Msk              (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */\n#define GPIO_IDR_ID11                  GPIO_IDR_ID11_Msk\n#define GPIO_IDR_ID12_Pos              (12U)\n#define GPIO_IDR_ID12_Msk              (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */\n#define GPIO_IDR_ID12                  GPIO_IDR_ID12_Msk\n#define GPIO_IDR_ID13_Pos              (13U)\n#define GPIO_IDR_ID13_Msk              (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */\n#define GPIO_IDR_ID13                  GPIO_IDR_ID13_Msk\n#define GPIO_IDR_ID14_Pos              (14U)\n#define GPIO_IDR_ID14_Msk              (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */\n#define GPIO_IDR_ID14                  GPIO_IDR_ID14_Msk\n#define GPIO_IDR_ID15_Pos              (15U)\n#define GPIO_IDR_ID15_Msk              (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */\n#define GPIO_IDR_ID15                  GPIO_IDR_ID15_Msk\n\n/******************  Bits definition for GPIO_ODR register  *******************/\n#define GPIO_ODR_OD0_Pos               (0U)\n#define GPIO_ODR_OD0_Msk               (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */\n#define GPIO_ODR_OD0                   GPIO_ODR_OD0_Msk\n#define GPIO_ODR_OD1_Pos               (1U)\n#define GPIO_ODR_OD1_Msk               (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */\n#define GPIO_ODR_OD1                   GPIO_ODR_OD1_Msk\n#define GPIO_ODR_OD2_Pos               (2U)\n#define GPIO_ODR_OD2_Msk               (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */\n#define GPIO_ODR_OD2                   GPIO_ODR_OD2_Msk\n#define GPIO_ODR_OD3_Pos               (3U)\n#define GPIO_ODR_OD3_Msk               (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */\n#define GPIO_ODR_OD3                   GPIO_ODR_OD3_Msk\n#define GPIO_ODR_OD4_Pos               (4U)\n#define GPIO_ODR_OD4_Msk               (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */\n#define GPIO_ODR_OD4                   GPIO_ODR_OD4_Msk\n#define GPIO_ODR_OD5_Pos               (5U)\n#define GPIO_ODR_OD5_Msk               (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */\n#define GPIO_ODR_OD5                   GPIO_ODR_OD5_Msk\n#define GPIO_ODR_OD6_Pos               (6U)\n#define GPIO_ODR_OD6_Msk               (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */\n#define GPIO_ODR_OD6                   GPIO_ODR_OD6_Msk\n#define GPIO_ODR_OD7_Pos               (7U)\n#define GPIO_ODR_OD7_Msk               (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */\n#define GPIO_ODR_OD7                   GPIO_ODR_OD7_Msk\n#define GPIO_ODR_OD8_Pos               (8U)\n#define GPIO_ODR_OD8_Msk               (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */\n#define GPIO_ODR_OD8                   GPIO_ODR_OD8_Msk\n#define GPIO_ODR_OD9_Pos               (9U)\n#define GPIO_ODR_OD9_Msk               (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */\n#define GPIO_ODR_OD9                   GPIO_ODR_OD9_Msk\n#define GPIO_ODR_OD10_Pos              (10U)\n#define GPIO_ODR_OD10_Msk              (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */\n#define GPIO_ODR_OD10                  GPIO_ODR_OD10_Msk\n#define GPIO_ODR_OD11_Pos              (11U)\n#define GPIO_ODR_OD11_Msk              (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */\n#define GPIO_ODR_OD11                  GPIO_ODR_OD11_Msk\n#define GPIO_ODR_OD12_Pos              (12U)\n#define GPIO_ODR_OD12_Msk              (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */\n#define GPIO_ODR_OD12                  GPIO_ODR_OD12_Msk\n#define GPIO_ODR_OD13_Pos              (13U)\n#define GPIO_ODR_OD13_Msk              (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */\n#define GPIO_ODR_OD13                  GPIO_ODR_OD13_Msk\n#define GPIO_ODR_OD14_Pos              (14U)\n#define GPIO_ODR_OD14_Msk              (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */\n#define GPIO_ODR_OD14                  GPIO_ODR_OD14_Msk\n#define GPIO_ODR_OD15_Pos              (15U)\n#define GPIO_ODR_OD15_Msk              (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */\n#define GPIO_ODR_OD15                  GPIO_ODR_OD15_Msk\n\n/******************  Bits definition for GPIO_BSRR register  ******************/\n#define GPIO_BSRR_BS0_Pos              (0U)\n#define GPIO_BSRR_BS0_Msk              (0x1UL << GPIO_BSRR_BS0_Pos)            /*!< 0x00000001 */\n#define GPIO_BSRR_BS0                  GPIO_BSRR_BS0_Msk\n#define GPIO_BSRR_BS1_Pos              (1U)\n#define GPIO_BSRR_BS1_Msk              (0x1UL << GPIO_BSRR_BS1_Pos)            /*!< 0x00000002 */\n#define GPIO_BSRR_BS1                  GPIO_BSRR_BS1_Msk\n#define GPIO_BSRR_BS2_Pos              (2U)\n#define GPIO_BSRR_BS2_Msk              (0x1UL << GPIO_BSRR_BS2_Pos)            /*!< 0x00000004 */\n#define GPIO_BSRR_BS2                  GPIO_BSRR_BS2_Msk\n#define GPIO_BSRR_BS3_Pos              (3U)\n#define GPIO_BSRR_BS3_Msk              (0x1UL << GPIO_BSRR_BS3_Pos)            /*!< 0x00000008 */\n#define GPIO_BSRR_BS3                  GPIO_BSRR_BS3_Msk\n#define GPIO_BSRR_BS4_Pos              (4U)\n#define GPIO_BSRR_BS4_Msk              (0x1UL << GPIO_BSRR_BS4_Pos)            /*!< 0x00000010 */\n#define GPIO_BSRR_BS4                  GPIO_BSRR_BS4_Msk\n#define GPIO_BSRR_BS5_Pos              (5U)\n#define GPIO_BSRR_BS5_Msk              (0x1UL << GPIO_BSRR_BS5_Pos)            /*!< 0x00000020 */\n#define GPIO_BSRR_BS5                  GPIO_BSRR_BS5_Msk\n#define GPIO_BSRR_BS6_Pos              (6U)\n#define GPIO_BSRR_BS6_Msk              (0x1UL << GPIO_BSRR_BS6_Pos)            /*!< 0x00000040 */\n#define GPIO_BSRR_BS6                  GPIO_BSRR_BS6_Msk\n#define GPIO_BSRR_BS7_Pos              (7U)\n#define GPIO_BSRR_BS7_Msk              (0x1UL << GPIO_BSRR_BS7_Pos)            /*!< 0x00000080 */\n#define GPIO_BSRR_BS7                  GPIO_BSRR_BS7_Msk\n#define GPIO_BSRR_BS8_Pos              (8U)\n#define GPIO_BSRR_BS8_Msk              (0x1UL << GPIO_BSRR_BS8_Pos)            /*!< 0x00000100 */\n#define GPIO_BSRR_BS8                  GPIO_BSRR_BS8_Msk\n#define GPIO_BSRR_BS9_Pos              (9U)\n#define GPIO_BSRR_BS9_Msk              (0x1UL << GPIO_BSRR_BS9_Pos)            /*!< 0x00000200 */\n#define GPIO_BSRR_BS9                  GPIO_BSRR_BS9_Msk\n#define GPIO_BSRR_BS10_Pos             (10U)\n#define GPIO_BSRR_BS10_Msk             (0x1UL << GPIO_BSRR_BS10_Pos)           /*!< 0x00000400 */\n#define GPIO_BSRR_BS10                 GPIO_BSRR_BS10_Msk\n#define GPIO_BSRR_BS11_Pos             (11U)\n#define GPIO_BSRR_BS11_Msk             (0x1UL << GPIO_BSRR_BS11_Pos)           /*!< 0x00000800 */\n#define GPIO_BSRR_BS11                 GPIO_BSRR_BS11_Msk\n#define GPIO_BSRR_BS12_Pos             (12U)\n#define GPIO_BSRR_BS12_Msk             (0x1UL << GPIO_BSRR_BS12_Pos)           /*!< 0x00001000 */\n#define GPIO_BSRR_BS12                 GPIO_BSRR_BS12_Msk\n#define GPIO_BSRR_BS13_Pos             (13U)\n#define GPIO_BSRR_BS13_Msk             (0x1UL << GPIO_BSRR_BS13_Pos)           /*!< 0x00002000 */\n#define GPIO_BSRR_BS13                 GPIO_BSRR_BS13_Msk\n#define GPIO_BSRR_BS14_Pos             (14U)\n#define GPIO_BSRR_BS14_Msk             (0x1UL << GPIO_BSRR_BS14_Pos)           /*!< 0x00004000 */\n#define GPIO_BSRR_BS14                 GPIO_BSRR_BS14_Msk\n#define GPIO_BSRR_BS15_Pos             (15U)\n#define GPIO_BSRR_BS15_Msk             (0x1UL << GPIO_BSRR_BS15_Pos)           /*!< 0x00008000 */\n#define GPIO_BSRR_BS15                 GPIO_BSRR_BS15_Msk\n#define GPIO_BSRR_BR0_Pos              (16U)\n#define GPIO_BSRR_BR0_Msk              (0x1UL << GPIO_BSRR_BR0_Pos)            /*!< 0x00010000 */\n#define GPIO_BSRR_BR0                  GPIO_BSRR_BR0_Msk\n#define GPIO_BSRR_BR1_Pos              (17U)\n#define GPIO_BSRR_BR1_Msk              (0x1UL << GPIO_BSRR_BR1_Pos)            /*!< 0x00020000 */\n#define GPIO_BSRR_BR1                  GPIO_BSRR_BR1_Msk\n#define GPIO_BSRR_BR2_Pos              (18U)\n#define GPIO_BSRR_BR2_Msk              (0x1UL << GPIO_BSRR_BR2_Pos)            /*!< 0x00040000 */\n#define GPIO_BSRR_BR2                  GPIO_BSRR_BR2_Msk\n#define GPIO_BSRR_BR3_Pos              (19U)\n#define GPIO_BSRR_BR3_Msk              (0x1UL << GPIO_BSRR_BR3_Pos)            /*!< 0x00080000 */\n#define GPIO_BSRR_BR3                  GPIO_BSRR_BR3_Msk\n#define GPIO_BSRR_BR4_Pos              (20U)\n#define GPIO_BSRR_BR4_Msk              (0x1UL << GPIO_BSRR_BR4_Pos)            /*!< 0x00100000 */\n#define GPIO_BSRR_BR4                  GPIO_BSRR_BR4_Msk\n#define GPIO_BSRR_BR5_Pos              (21U)\n#define GPIO_BSRR_BR5_Msk              (0x1UL << GPIO_BSRR_BR5_Pos)            /*!< 0x00200000 */\n#define GPIO_BSRR_BR5                  GPIO_BSRR_BR5_Msk\n#define GPIO_BSRR_BR6_Pos              (22U)\n#define GPIO_BSRR_BR6_Msk              (0x1UL << GPIO_BSRR_BR6_Pos)            /*!< 0x00400000 */\n#define GPIO_BSRR_BR6                  GPIO_BSRR_BR6_Msk\n#define GPIO_BSRR_BR7_Pos              (23U)\n#define GPIO_BSRR_BR7_Msk              (0x1UL << GPIO_BSRR_BR7_Pos)            /*!< 0x00800000 */\n#define GPIO_BSRR_BR7                  GPIO_BSRR_BR7_Msk\n#define GPIO_BSRR_BR8_Pos              (24U)\n#define GPIO_BSRR_BR8_Msk              (0x1UL << GPIO_BSRR_BR8_Pos)            /*!< 0x01000000 */\n#define GPIO_BSRR_BR8                  GPIO_BSRR_BR8_Msk\n#define GPIO_BSRR_BR9_Pos              (25U)\n#define GPIO_BSRR_BR9_Msk              (0x1UL << GPIO_BSRR_BR9_Pos)            /*!< 0x02000000 */\n#define GPIO_BSRR_BR9                  GPIO_BSRR_BR9_Msk\n#define GPIO_BSRR_BR10_Pos             (26U)\n#define GPIO_BSRR_BR10_Msk             (0x1UL << GPIO_BSRR_BR10_Pos)           /*!< 0x04000000 */\n#define GPIO_BSRR_BR10                 GPIO_BSRR_BR10_Msk\n#define GPIO_BSRR_BR11_Pos             (27U)\n#define GPIO_BSRR_BR11_Msk             (0x1UL << GPIO_BSRR_BR11_Pos)           /*!< 0x08000000 */\n#define GPIO_BSRR_BR11                 GPIO_BSRR_BR11_Msk\n#define GPIO_BSRR_BR12_Pos             (28U)\n#define GPIO_BSRR_BR12_Msk             (0x1UL << GPIO_BSRR_BR12_Pos)           /*!< 0x10000000 */\n#define GPIO_BSRR_BR12                 GPIO_BSRR_BR12_Msk\n#define GPIO_BSRR_BR13_Pos             (29U)\n#define GPIO_BSRR_BR13_Msk             (0x1UL << GPIO_BSRR_BR13_Pos)           /*!< 0x20000000 */\n#define GPIO_BSRR_BR13                 GPIO_BSRR_BR13_Msk\n#define GPIO_BSRR_BR14_Pos             (30U)\n#define GPIO_BSRR_BR14_Msk             (0x1UL << GPIO_BSRR_BR14_Pos)           /*!< 0x40000000 */\n#define GPIO_BSRR_BR14                 GPIO_BSRR_BR14_Msk\n#define GPIO_BSRR_BR15_Pos             (31U)\n#define GPIO_BSRR_BR15_Msk             (0x1UL << GPIO_BSRR_BR15_Pos)           /*!< 0x80000000 */\n#define GPIO_BSRR_BR15                 GPIO_BSRR_BR15_Msk\n\n/****************** Bit definition for GPIO_LCKR register *********************/\n#define GPIO_LCKR_LCK0_Pos             (0U)\n#define GPIO_LCKR_LCK0_Msk             (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */\n#define GPIO_LCKR_LCK0                 GPIO_LCKR_LCK0_Msk\n#define GPIO_LCKR_LCK1_Pos             (1U)\n#define GPIO_LCKR_LCK1_Msk             (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */\n#define GPIO_LCKR_LCK1                 GPIO_LCKR_LCK1_Msk\n#define GPIO_LCKR_LCK2_Pos             (2U)\n#define GPIO_LCKR_LCK2_Msk             (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */\n#define GPIO_LCKR_LCK2                 GPIO_LCKR_LCK2_Msk\n#define GPIO_LCKR_LCK3_Pos             (3U)\n#define GPIO_LCKR_LCK3_Msk             (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */\n#define GPIO_LCKR_LCK3                 GPIO_LCKR_LCK3_Msk\n#define GPIO_LCKR_LCK4_Pos             (4U)\n#define GPIO_LCKR_LCK4_Msk             (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */\n#define GPIO_LCKR_LCK4                 GPIO_LCKR_LCK4_Msk\n#define GPIO_LCKR_LCK5_Pos             (5U)\n#define GPIO_LCKR_LCK5_Msk             (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */\n#define GPIO_LCKR_LCK5                 GPIO_LCKR_LCK5_Msk\n#define GPIO_LCKR_LCK6_Pos             (6U)\n#define GPIO_LCKR_LCK6_Msk             (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */\n#define GPIO_LCKR_LCK6                 GPIO_LCKR_LCK6_Msk\n#define GPIO_LCKR_LCK7_Pos             (7U)\n#define GPIO_LCKR_LCK7_Msk             (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */\n#define GPIO_LCKR_LCK7                 GPIO_LCKR_LCK7_Msk\n#define GPIO_LCKR_LCK8_Pos             (8U)\n#define GPIO_LCKR_LCK8_Msk             (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */\n#define GPIO_LCKR_LCK8                 GPIO_LCKR_LCK8_Msk\n#define GPIO_LCKR_LCK9_Pos             (9U)\n#define GPIO_LCKR_LCK9_Msk             (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */\n#define GPIO_LCKR_LCK9                 GPIO_LCKR_LCK9_Msk\n#define GPIO_LCKR_LCK10_Pos            (10U)\n#define GPIO_LCKR_LCK10_Msk            (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */\n#define GPIO_LCKR_LCK10                GPIO_LCKR_LCK10_Msk\n#define GPIO_LCKR_LCK11_Pos            (11U)\n#define GPIO_LCKR_LCK11_Msk            (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */\n#define GPIO_LCKR_LCK11                GPIO_LCKR_LCK11_Msk\n#define GPIO_LCKR_LCK12_Pos            (12U)\n#define GPIO_LCKR_LCK12_Msk            (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */\n#define GPIO_LCKR_LCK12                GPIO_LCKR_LCK12_Msk\n#define GPIO_LCKR_LCK13_Pos            (13U)\n#define GPIO_LCKR_LCK13_Msk            (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */\n#define GPIO_LCKR_LCK13                GPIO_LCKR_LCK13_Msk\n#define GPIO_LCKR_LCK14_Pos            (14U)\n#define GPIO_LCKR_LCK14_Msk            (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */\n#define GPIO_LCKR_LCK14                GPIO_LCKR_LCK14_Msk\n#define GPIO_LCKR_LCK15_Pos            (15U)\n#define GPIO_LCKR_LCK15_Msk            (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */\n#define GPIO_LCKR_LCK15                GPIO_LCKR_LCK15_Msk\n#define GPIO_LCKR_LCKK_Pos             (16U)\n#define GPIO_LCKR_LCKK_Msk             (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */\n#define GPIO_LCKR_LCKK                 GPIO_LCKR_LCKK_Msk\n\n/****************** Bit definition for GPIO_AFRL register  ********************/\n#define GPIO_AFRL_AFSEL0_Pos           (0U)\n#define GPIO_AFRL_AFSEL0_Msk           (0xFUL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */\n#define GPIO_AFRL_AFSEL0               GPIO_AFRL_AFSEL0_Msk\n#define GPIO_AFRL_AFSEL0_0             (0x1UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000001 */\n#define GPIO_AFRL_AFSEL0_1             (0x2UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000002 */\n#define GPIO_AFRL_AFSEL0_2             (0x4UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000004 */\n#define GPIO_AFRL_AFSEL0_3             (0x8UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000008 */\n#define GPIO_AFRL_AFSEL1_Pos           (4U)\n#define GPIO_AFRL_AFSEL1_Msk           (0xFUL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */\n#define GPIO_AFRL_AFSEL1               GPIO_AFRL_AFSEL1_Msk\n#define GPIO_AFRL_AFSEL1_0             (0x1UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000010 */\n#define GPIO_AFRL_AFSEL1_1             (0x2UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000020 */\n#define GPIO_AFRL_AFSEL1_2             (0x4UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000040 */\n#define GPIO_AFRL_AFSEL1_3             (0x8UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000080 */\n#define GPIO_AFRL_AFSEL2_Pos           (8U)\n#define GPIO_AFRL_AFSEL2_Msk           (0xFUL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */\n#define GPIO_AFRL_AFSEL2               GPIO_AFRL_AFSEL2_Msk\n#define GPIO_AFRL_AFSEL2_0             (0x1UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000100 */\n#define GPIO_AFRL_AFSEL2_1             (0x2UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000200 */\n#define GPIO_AFRL_AFSEL2_2             (0x4UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000400 */\n#define GPIO_AFRL_AFSEL2_3             (0x8UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000800 */\n#define GPIO_AFRL_AFSEL3_Pos           (12U)\n#define GPIO_AFRL_AFSEL3_Msk           (0xFUL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */\n#define GPIO_AFRL_AFSEL3               GPIO_AFRL_AFSEL3_Msk\n#define GPIO_AFRL_AFSEL3_0             (0x1UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00001000 */\n#define GPIO_AFRL_AFSEL3_1             (0x2UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00002000 */\n#define GPIO_AFRL_AFSEL3_2             (0x4UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00004000 */\n#define GPIO_AFRL_AFSEL3_3             (0x8UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00008000 */\n#define GPIO_AFRL_AFSEL4_Pos           (16U)\n#define GPIO_AFRL_AFSEL4_Msk           (0xFUL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */\n#define GPIO_AFRL_AFSEL4               GPIO_AFRL_AFSEL4_Msk\n#define GPIO_AFRL_AFSEL4_0             (0x1UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00010000 */\n#define GPIO_AFRL_AFSEL4_1             (0x2UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00020000 */\n#define GPIO_AFRL_AFSEL4_2             (0x4UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00040000 */\n#define GPIO_AFRL_AFSEL4_3             (0x8UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00080000 */\n#define GPIO_AFRL_AFSEL5_Pos           (20U)\n#define GPIO_AFRL_AFSEL5_Msk           (0xFUL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */\n#define GPIO_AFRL_AFSEL5               GPIO_AFRL_AFSEL5_Msk\n#define GPIO_AFRL_AFSEL5_0             (0x1UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00100000 */\n#define GPIO_AFRL_AFSEL5_1             (0x2UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00200000 */\n#define GPIO_AFRL_AFSEL5_2             (0x4UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00400000 */\n#define GPIO_AFRL_AFSEL5_3             (0x8UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00800000 */\n#define GPIO_AFRL_AFSEL6_Pos           (24U)\n#define GPIO_AFRL_AFSEL6_Msk           (0xFUL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */\n#define GPIO_AFRL_AFSEL6               GPIO_AFRL_AFSEL6_Msk\n#define GPIO_AFRL_AFSEL6_0             (0x1UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x01000000 */\n#define GPIO_AFRL_AFSEL6_1             (0x2UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x02000000 */\n#define GPIO_AFRL_AFSEL6_2             (0x4UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x04000000 */\n#define GPIO_AFRL_AFSEL6_3             (0x8UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x08000000 */\n#define GPIO_AFRL_AFSEL7_Pos           (28U)\n#define GPIO_AFRL_AFSEL7_Msk           (0xFUL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */\n#define GPIO_AFRL_AFSEL7               GPIO_AFRL_AFSEL7_Msk\n#define GPIO_AFRL_AFSEL7_0             (0x1UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x10000000 */\n#define GPIO_AFRL_AFSEL7_1             (0x2UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x20000000 */\n#define GPIO_AFRL_AFSEL7_2             (0x4UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x40000000 */\n#define GPIO_AFRL_AFSEL7_3             (0x8UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x80000000 */\n\n/* Legacy defines */\n#define GPIO_AFRL_AFRL0                      GPIO_AFRL_AFSEL0\n#define GPIO_AFRL_AFRL1                      GPIO_AFRL_AFSEL1\n#define GPIO_AFRL_AFRL2                      GPIO_AFRL_AFSEL2\n#define GPIO_AFRL_AFRL3                      GPIO_AFRL_AFSEL3\n#define GPIO_AFRL_AFRL4                      GPIO_AFRL_AFSEL4\n#define GPIO_AFRL_AFRL5                      GPIO_AFRL_AFSEL5\n#define GPIO_AFRL_AFRL6                      GPIO_AFRL_AFSEL6\n#define GPIO_AFRL_AFRL7                      GPIO_AFRL_AFSEL7\n\n/****************** Bit definition for GPIO_AFRH register  ********************/\n#define GPIO_AFRH_AFSEL8_Pos           (0U)\n#define GPIO_AFRH_AFSEL8_Msk           (0xFUL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */\n#define GPIO_AFRH_AFSEL8               GPIO_AFRH_AFSEL8_Msk\n#define GPIO_AFRH_AFSEL8_0             (0x1UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000001 */\n#define GPIO_AFRH_AFSEL8_1             (0x2UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000002 */\n#define GPIO_AFRH_AFSEL8_2             (0x4UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000004 */\n#define GPIO_AFRH_AFSEL8_3             (0x8UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000008 */\n#define GPIO_AFRH_AFSEL9_Pos           (4U)\n#define GPIO_AFRH_AFSEL9_Msk           (0xFUL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */\n#define GPIO_AFRH_AFSEL9               GPIO_AFRH_AFSEL9_Msk\n#define GPIO_AFRH_AFSEL9_0             (0x1UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000010 */\n#define GPIO_AFRH_AFSEL9_1             (0x2UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000020 */\n#define GPIO_AFRH_AFSEL9_2             (0x4UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000040 */\n#define GPIO_AFRH_AFSEL9_3             (0x8UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000080 */\n#define GPIO_AFRH_AFSEL10_Pos          (8U)\n#define GPIO_AFRH_AFSEL10_Msk          (0xFUL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */\n#define GPIO_AFRH_AFSEL10              GPIO_AFRH_AFSEL10_Msk\n#define GPIO_AFRH_AFSEL10_0            (0x1UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000100 */\n#define GPIO_AFRH_AFSEL10_1            (0x2UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000200 */\n#define GPIO_AFRH_AFSEL10_2            (0x4UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000400 */\n#define GPIO_AFRH_AFSEL10_3            (0x8UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000800 */\n#define GPIO_AFRH_AFSEL11_Pos          (12U)\n#define GPIO_AFRH_AFSEL11_Msk          (0xFUL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */\n#define GPIO_AFRH_AFSEL11              GPIO_AFRH_AFSEL11_Msk\n#define GPIO_AFRH_AFSEL11_0            (0x1UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00001000 */\n#define GPIO_AFRH_AFSEL11_1            (0x2UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00002000 */\n#define GPIO_AFRH_AFSEL11_2            (0x4UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00004000 */\n#define GPIO_AFRH_AFSEL11_3            (0x8UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00008000 */\n#define GPIO_AFRH_AFSEL12_Pos          (16U)\n#define GPIO_AFRH_AFSEL12_Msk          (0xFUL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */\n#define GPIO_AFRH_AFSEL12              GPIO_AFRH_AFSEL12_Msk\n#define GPIO_AFRH_AFSEL12_0            (0x1UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00010000 */\n#define GPIO_AFRH_AFSEL12_1            (0x2UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00020000 */\n#define GPIO_AFRH_AFSEL12_2            (0x4UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00040000 */\n#define GPIO_AFRH_AFSEL12_3            (0x8UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00080000 */\n#define GPIO_AFRH_AFSEL13_Pos          (20U)\n#define GPIO_AFRH_AFSEL13_Msk          (0xFUL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */\n#define GPIO_AFRH_AFSEL13              GPIO_AFRH_AFSEL13_Msk\n#define GPIO_AFRH_AFSEL13_0            (0x1UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00100000 */\n#define GPIO_AFRH_AFSEL13_1            (0x2UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00200000 */\n#define GPIO_AFRH_AFSEL13_2            (0x4UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00400000 */\n#define GPIO_AFRH_AFSEL13_3            (0x8UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00800000 */\n#define GPIO_AFRH_AFSEL14_Pos          (24U)\n#define GPIO_AFRH_AFSEL14_Msk          (0xFUL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */\n#define GPIO_AFRH_AFSEL14              GPIO_AFRH_AFSEL14_Msk\n#define GPIO_AFRH_AFSEL14_0            (0x1UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x01000000 */\n#define GPIO_AFRH_AFSEL14_1            (0x2UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x02000000 */\n#define GPIO_AFRH_AFSEL14_2            (0x4UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x04000000 */\n#define GPIO_AFRH_AFSEL14_3            (0x8UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x08000000 */\n#define GPIO_AFRH_AFSEL15_Pos          (28U)\n#define GPIO_AFRH_AFSEL15_Msk          (0xFUL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */\n#define GPIO_AFRH_AFSEL15              GPIO_AFRH_AFSEL15_Msk\n#define GPIO_AFRH_AFSEL15_0            (0x1UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x10000000 */\n#define GPIO_AFRH_AFSEL15_1            (0x2UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x20000000 */\n#define GPIO_AFRH_AFSEL15_2            (0x4UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x40000000 */\n#define GPIO_AFRH_AFSEL15_3            (0x8UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x80000000 */\n\n/* Legacy defines */\n#define GPIO_AFRH_AFRH0                      GPIO_AFRH_AFSEL8\n#define GPIO_AFRH_AFRH1                      GPIO_AFRH_AFSEL9\n#define GPIO_AFRH_AFRH2                      GPIO_AFRH_AFSEL10\n#define GPIO_AFRH_AFRH3                      GPIO_AFRH_AFSEL11\n#define GPIO_AFRH_AFRH4                      GPIO_AFRH_AFSEL12\n#define GPIO_AFRH_AFRH5                      GPIO_AFRH_AFSEL13\n#define GPIO_AFRH_AFRH6                      GPIO_AFRH_AFSEL14\n#define GPIO_AFRH_AFRH7                      GPIO_AFRH_AFSEL15\n\n/******************************************************************************/\n/*                                                                            */\n/*                        HSEM HW Semaphore                                   */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for HSEM_R register  ********************/\n#define HSEM_R_PROCID_Pos         (0U)\n#define HSEM_R_PROCID_Msk         (0xFFUL << HSEM_R_PROCID_Pos)                /*!< 0x000000FF */\n#define HSEM_R_PROCID             HSEM_R_PROCID_Msk                            /*!<Semaphore ProcessID */\n#define HSEM_R_COREID_Pos         (8U)\n#define HSEM_R_COREID_Msk         (0xFFUL << HSEM_R_COREID_Pos)                /*!< 0x0000FF00 */\n#define HSEM_R_COREID             HSEM_R_COREID_Msk                            /*!<Semaphore CoreID.   */\n#define HSEM_R_LOCK_Pos           (31U)\n#define HSEM_R_LOCK_Msk           (0x1UL << HSEM_R_LOCK_Pos)                   /*!< 0x80000000 */\n#define HSEM_R_LOCK               HSEM_R_LOCK_Msk                              /*!<Lock indication.    */\n\n/********************  Bit definition for HSEM_RLR register  ******************/\n#define HSEM_RLR_PROCID_Pos       (0U)\n#define HSEM_RLR_PROCID_Msk       (0xFFUL << HSEM_RLR_PROCID_Pos)              /*!< 0x000000FF */\n#define HSEM_RLR_PROCID           HSEM_RLR_PROCID_Msk                          /*!<Semaphore ProcessID */\n#define HSEM_RLR_COREID_Pos       (8U)\n#define HSEM_RLR_COREID_Msk       (0xFFUL << HSEM_RLR_COREID_Pos)              /*!< 0x0000FF00 */\n#define HSEM_RLR_COREID           HSEM_RLR_COREID_Msk                          /*!<Semaphore CoreID.   */\n#define HSEM_RLR_LOCK_Pos         (31U)\n#define HSEM_RLR_LOCK_Msk         (0x1UL << HSEM_RLR_LOCK_Pos)                 /*!< 0x80000000 */\n#define HSEM_RLR_LOCK             HSEM_RLR_LOCK_Msk                            /*!<Lock indication.    */\n\n/********************  Bit definition for HSEM_C1IER register  *****************/\n#define HSEM_C1IER_ISE0_Pos       (0U)\n#define HSEM_C1IER_ISE0_Msk       (0x1UL << HSEM_C1IER_ISE0_Pos)               /*!< 0x00000001 */\n#define HSEM_C1IER_ISE0           HSEM_C1IER_ISE0_Msk                          /*!<semaphore 0 , interrupt 0 enable bit.  */\n#define HSEM_C1IER_ISE1_Pos       (1U)\n#define HSEM_C1IER_ISE1_Msk       (0x1UL << HSEM_C1IER_ISE1_Pos)               /*!< 0x00000002 */\n#define HSEM_C1IER_ISE1           HSEM_C1IER_ISE1_Msk                          /*!<semaphore 1 , interrupt 0 enable bit.  */\n#define HSEM_C1IER_ISE2_Pos       (2U)\n#define HSEM_C1IER_ISE2_Msk       (0x1UL << HSEM_C1IER_ISE2_Pos)               /*!< 0x00000004 */\n#define HSEM_C1IER_ISE2           HSEM_C1IER_ISE2_Msk                          /*!<semaphore 2 , interrupt 0 enable bit.  */\n#define HSEM_C1IER_ISE3_Pos       (3U)\n#define HSEM_C1IER_ISE3_Msk       (0x1UL << HSEM_C1IER_ISE3_Pos)               /*!< 0x00000008 */\n#define HSEM_C1IER_ISE3           HSEM_C1IER_ISE3_Msk                          /*!<semaphore 3 , interrupt 0 enable bit.  */\n#define HSEM_C1IER_ISE4_Pos       (4U)\n#define HSEM_C1IER_ISE4_Msk       (0x1UL << HSEM_C1IER_ISE4_Pos)               /*!< 0x00000010 */\n#define HSEM_C1IER_ISE4           HSEM_C1IER_ISE4_Msk                          /*!<semaphore 4 , interrupt 0 enable bit.  */\n#define HSEM_C1IER_ISE5_Pos       (5U)\n#define HSEM_C1IER_ISE5_Msk       (0x1UL << HSEM_C1IER_ISE5_Pos)               /*!< 0x00000020 */\n#define HSEM_C1IER_ISE5           HSEM_C1IER_ISE5_Msk                          /*!<semaphore 5 interrupt 0 enable bit.    */\n#define HSEM_C1IER_ISE6_Pos       (6U)\n#define HSEM_C1IER_ISE6_Msk       (0x1UL << HSEM_C1IER_ISE6_Pos)               /*!< 0x00000040 */\n#define HSEM_C1IER_ISE6           HSEM_C1IER_ISE6_Msk                          /*!<semaphore 6 interrupt 0 enable bit.    */\n#define HSEM_C1IER_ISE7_Pos       (7U)\n#define HSEM_C1IER_ISE7_Msk       (0x1UL << HSEM_C1IER_ISE7_Pos)               /*!< 0x00000080 */\n#define HSEM_C1IER_ISE7           HSEM_C1IER_ISE7_Msk                          /*!<semaphore 7 interrupt 0 enable bit.    */\n#define HSEM_C1IER_ISE8_Pos       (8U)\n#define HSEM_C1IER_ISE8_Msk       (0x1UL << HSEM_C1IER_ISE8_Pos)               /*!< 0x00000100 */\n#define HSEM_C1IER_ISE8           HSEM_C1IER_ISE8_Msk                          /*!<semaphore 8 interrupt 0 enable bit.    */\n#define HSEM_C1IER_ISE9_Pos       (9U)\n#define HSEM_C1IER_ISE9_Msk       (0x1UL << HSEM_C1IER_ISE9_Pos)               /*!< 0x00000200 */\n#define HSEM_C1IER_ISE9           HSEM_C1IER_ISE9_Msk                          /*!<semaphore 9 interrupt 0 enable bit.    */\n#define HSEM_C1IER_ISE10_Pos      (10U)\n#define HSEM_C1IER_ISE10_Msk      (0x1UL << HSEM_C1IER_ISE10_Pos)              /*!< 0x00000400 */\n#define HSEM_C1IER_ISE10          HSEM_C1IER_ISE10_Msk                         /*!<semaphore 10 interrupt 0 enable bit.   */\n#define HSEM_C1IER_ISE11_Pos      (11U)\n#define HSEM_C1IER_ISE11_Msk      (0x1UL << HSEM_C1IER_ISE11_Pos)              /*!< 0x00000800 */\n#define HSEM_C1IER_ISE11          HSEM_C1IER_ISE11_Msk                         /*!<semaphore 11 interrupt 0 enable bit.   */\n#define HSEM_C1IER_ISE12_Pos      (12U)\n#define HSEM_C1IER_ISE12_Msk      (0x1UL << HSEM_C1IER_ISE12_Pos)              /*!< 0x00001000 */\n#define HSEM_C1IER_ISE12          HSEM_C1IER_ISE12_Msk                         /*!<semaphore 12 interrupt 0 enable bit.   */\n#define HSEM_C1IER_ISE13_Pos      (13U)\n#define HSEM_C1IER_ISE13_Msk      (0x1UL << HSEM_C1IER_ISE13_Pos)              /*!< 0x00002000 */\n#define HSEM_C1IER_ISE13          HSEM_C1IER_ISE13_Msk                         /*!<semaphore 13 interrupt 0 enable bit.   */\n#define HSEM_C1IER_ISE14_Pos      (14U)\n#define HSEM_C1IER_ISE14_Msk      (0x1UL << HSEM_C1IER_ISE14_Pos)              /*!< 0x00004000 */\n#define HSEM_C1IER_ISE14          HSEM_C1IER_ISE14_Msk                         /*!<semaphore 14 interrupt 0 enable bit.   */\n#define HSEM_C1IER_ISE15_Pos      (15U)\n#define HSEM_C1IER_ISE15_Msk      (0x1UL << HSEM_C1IER_ISE15_Pos)              /*!< 0x00008000 */\n#define HSEM_C1IER_ISE15          HSEM_C1IER_ISE15_Msk                         /*!<semaphore 15 interrupt 0 enable bit. */\n#define HSEM_C1IER_ISE16_Pos      (16U)\n#define HSEM_C1IER_ISE16_Msk      (0x1UL << HSEM_C1IER_ISE16_Pos)              /*!< 0x00010000 */\n#define HSEM_C1IER_ISE16          HSEM_C1IER_ISE16_Msk                         /*!<semaphore 16 interrupt 0 enable bit. */\n#define HSEM_C1IER_ISE17_Pos      (17U)\n#define HSEM_C1IER_ISE17_Msk      (0x1UL << HSEM_C1IER_ISE17_Pos)              /*!< 0x00020000 */\n#define HSEM_C1IER_ISE17          HSEM_C1IER_ISE17_Msk                         /*!<semaphore 17 interrupt 0 enable bit. */\n#define HSEM_C1IER_ISE18_Pos      (18U)\n#define HSEM_C1IER_ISE18_Msk      (0x1UL << HSEM_C1IER_ISE18_Pos)              /*!< 0x00040000 */\n#define HSEM_C1IER_ISE18          HSEM_C1IER_ISE18_Msk                         /*!<semaphore 18 interrupt 0 enable bit. */\n#define HSEM_C1IER_ISE19_Pos      (19U)\n#define HSEM_C1IER_ISE19_Msk      (0x1UL << HSEM_C1IER_ISE19_Pos)              /*!< 0x00080000 */\n#define HSEM_C1IER_ISE19          HSEM_C1IER_ISE19_Msk                         /*!<semaphore 19 interrupt 0 enable bit. */\n#define HSEM_C1IER_ISE20_Pos      (20U)\n#define HSEM_C1IER_ISE20_Msk      (0x1UL << HSEM_C1IER_ISE20_Pos)              /*!< 0x00100000 */\n#define HSEM_C1IER_ISE20          HSEM_C1IER_ISE20_Msk                         /*!<semaphore 20 interrupt 0 enable bit. */\n#define HSEM_C1IER_ISE21_Pos      (21U)\n#define HSEM_C1IER_ISE21_Msk      (0x1UL << HSEM_C1IER_ISE21_Pos)              /*!< 0x00200000 */\n#define HSEM_C1IER_ISE21          HSEM_C1IER_ISE21_Msk                         /*!<semaphore 21 interrupt 0 enable bit. */\n#define HSEM_C1IER_ISE22_Pos      (22U)\n#define HSEM_C1IER_ISE22_Msk      (0x1UL << HSEM_C1IER_ISE22_Pos)              /*!< 0x00400000 */\n#define HSEM_C1IER_ISE22          HSEM_C1IER_ISE22_Msk                         /*!<semaphore 22 interrupt 0 enable bit. */\n#define HSEM_C1IER_ISE23_Pos      (23U)\n#define HSEM_C1IER_ISE23_Msk      (0x1UL << HSEM_C1IER_ISE23_Pos)              /*!< 0x00800000 */\n#define HSEM_C1IER_ISE23          HSEM_C1IER_ISE23_Msk                         /*!<semaphore 23 interrupt 0 enable bit. */\n#define HSEM_C1IER_ISE24_Pos      (24U)\n#define HSEM_C1IER_ISE24_Msk      (0x1UL << HSEM_C1IER_ISE24_Pos)              /*!< 0x01000000 */\n#define HSEM_C1IER_ISE24          HSEM_C1IER_ISE24_Msk                         /*!<semaphore 24 interrupt 0 enable bit. */\n#define HSEM_C1IER_ISE25_Pos      (25U)\n#define HSEM_C1IER_ISE25_Msk      (0x1UL << HSEM_C1IER_ISE25_Pos)              /*!< 0x02000000 */\n#define HSEM_C1IER_ISE25          HSEM_C1IER_ISE25_Msk                         /*!<semaphore 25 interrupt 0 enable bit. */\n#define HSEM_C1IER_ISE26_Pos      (26U)\n#define HSEM_C1IER_ISE26_Msk      (0x1UL << HSEM_C1IER_ISE26_Pos)              /*!< 0x04000000 */\n#define HSEM_C1IER_ISE26          HSEM_C1IER_ISE26_Msk                         /*!<semaphore 26 interrupt 0 enable bit. */\n#define HSEM_C1IER_ISE27_Pos      (27U)\n#define HSEM_C1IER_ISE27_Msk      (0x1UL << HSEM_C1IER_ISE27_Pos)              /*!< 0x08000000 */\n#define HSEM_C1IER_ISE27          HSEM_C1IER_ISE27_Msk                         /*!<semaphore 27 interrupt 0 enable bit. */\n#define HSEM_C1IER_ISE28_Pos      (28U)\n#define HSEM_C1IER_ISE28_Msk      (0x1UL << HSEM_C1IER_ISE28_Pos)              /*!< 0x10000000 */\n#define HSEM_C1IER_ISE28          HSEM_C1IER_ISE28_Msk                         /*!<semaphore 28 interrupt 0 enable bit. */\n#define HSEM_C1IER_ISE29_Pos      (29U)\n#define HSEM_C1IER_ISE29_Msk      (0x1UL << HSEM_C1IER_ISE29_Pos)              /*!< 0x20000000 */\n#define HSEM_C1IER_ISE29          HSEM_C1IER_ISE29_Msk                         /*!<semaphore 29 interrupt 0 enable bit. */\n#define HSEM_C1IER_ISE30_Pos      (30U)\n#define HSEM_C1IER_ISE30_Msk      (0x1UL << HSEM_C1IER_ISE30_Pos)              /*!< 0x40000000 */\n#define HSEM_C1IER_ISE30          HSEM_C1IER_ISE30_Msk                         /*!<semaphore 30 interrupt 0 enable bit. */\n#define HSEM_C1IER_ISE31_Pos      (31U)\n#define HSEM_C1IER_ISE31_Msk      (0x1UL << HSEM_C1IER_ISE31_Pos)              /*!< 0x80000000 */\n#define HSEM_C1IER_ISE31          HSEM_C1IER_ISE31_Msk                         /*!<semaphore 31 interrupt 0 enable bit. */\n\n/********************  Bit definition for HSEM_C1ICR register  *****************/\n#define HSEM_C1ICR_ISC0_Pos       (0U)\n#define HSEM_C1ICR_ISC0_Msk       (0x1UL << HSEM_C1ICR_ISC0_Pos)               /*!< 0x00000001 */\n#define HSEM_C1ICR_ISC0           HSEM_C1ICR_ISC0_Msk                          /*!<semaphore 0 , interrupt 0 clear bit.  */\n#define HSEM_C1ICR_ISC1_Pos       (1U)\n#define HSEM_C1ICR_ISC1_Msk       (0x1UL << HSEM_C1ICR_ISC1_Pos)               /*!< 0x00000002 */\n#define HSEM_C1ICR_ISC1           HSEM_C1ICR_ISC1_Msk                          /*!<semaphore 1 , interrupt 0 clear bit.  */\n#define HSEM_C1ICR_ISC2_Pos       (2U)\n#define HSEM_C1ICR_ISC2_Msk       (0x1UL << HSEM_C1ICR_ISC2_Pos)               /*!< 0x00000004 */\n#define HSEM_C1ICR_ISC2           HSEM_C1ICR_ISC2_Msk                          /*!<semaphore 2 , interrupt 0 clear bit.  */\n#define HSEM_C1ICR_ISC3_Pos       (3U)\n#define HSEM_C1ICR_ISC3_Msk       (0x1UL << HSEM_C1ICR_ISC3_Pos)               /*!< 0x00000008 */\n#define HSEM_C1ICR_ISC3           HSEM_C1ICR_ISC3_Msk                          /*!<semaphore 3 , interrupt 0 clear bit.  */\n#define HSEM_C1ICR_ISC4_Pos       (4U)\n#define HSEM_C1ICR_ISC4_Msk       (0x1UL << HSEM_C1ICR_ISC4_Pos)               /*!< 0x00000010 */\n#define HSEM_C1ICR_ISC4           HSEM_C1ICR_ISC4_Msk                          /*!<semaphore 4 , interrupt 0 clear bit.  */\n#define HSEM_C1ICR_ISC5_Pos       (5U)\n#define HSEM_C1ICR_ISC5_Msk       (0x1UL << HSEM_C1ICR_ISC5_Pos)               /*!< 0x00000020 */\n#define HSEM_C1ICR_ISC5           HSEM_C1ICR_ISC5_Msk                          /*!<semaphore 5 interrupt 0 clear bit.  */\n#define HSEM_C1ICR_ISC6_Pos       (6U)\n#define HSEM_C1ICR_ISC6_Msk       (0x1UL << HSEM_C1ICR_ISC6_Pos)               /*!< 0x00000040 */\n#define HSEM_C1ICR_ISC6           HSEM_C1ICR_ISC6_Msk                          /*!<semaphore 6 interrupt 0 clear bit.  */\n#define HSEM_C1ICR_ISC7_Pos       (7U)\n#define HSEM_C1ICR_ISC7_Msk       (0x1UL << HSEM_C1ICR_ISC7_Pos)               /*!< 0x00000080 */\n#define HSEM_C1ICR_ISC7           HSEM_C1ICR_ISC7_Msk                          /*!<semaphore 7 interrupt 0 clear bit.  */\n#define HSEM_C1ICR_ISC8_Pos       (8U)\n#define HSEM_C1ICR_ISC8_Msk       (0x1UL << HSEM_C1ICR_ISC8_Pos)               /*!< 0x00000100 */\n#define HSEM_C1ICR_ISC8           HSEM_C1ICR_ISC8_Msk                          /*!<semaphore 8 interrupt 0 clear bit.  */\n#define HSEM_C1ICR_ISC9_Pos       (9U)\n#define HSEM_C1ICR_ISC9_Msk       (0x1UL << HSEM_C1ICR_ISC9_Pos)               /*!< 0x00000200 */\n#define HSEM_C1ICR_ISC9           HSEM_C1ICR_ISC9_Msk                          /*!<semaphore 9 interrupt 0 clear bit.  */\n#define HSEM_C1ICR_ISC10_Pos      (10U)\n#define HSEM_C1ICR_ISC10_Msk      (0x1UL << HSEM_C1ICR_ISC10_Pos)              /*!< 0x00000400 */\n#define HSEM_C1ICR_ISC10          HSEM_C1ICR_ISC10_Msk                         /*!<semaphore 10 interrupt 0 clear bit. */\n#define HSEM_C1ICR_ISC11_Pos      (11U)\n#define HSEM_C1ICR_ISC11_Msk      (0x1UL << HSEM_C1ICR_ISC11_Pos)              /*!< 0x00000800 */\n#define HSEM_C1ICR_ISC11          HSEM_C1ICR_ISC11_Msk                         /*!<semaphore 11 interrupt 0 clear bit. */\n#define HSEM_C1ICR_ISC12_Pos      (12U)\n#define HSEM_C1ICR_ISC12_Msk      (0x1UL << HSEM_C1ICR_ISC12_Pos)              /*!< 0x00001000 */\n#define HSEM_C1ICR_ISC12          HSEM_C1ICR_ISC12_Msk                         /*!<semaphore 12 interrupt 0 clear bit. */\n#define HSEM_C1ICR_ISC13_Pos      (13U)\n#define HSEM_C1ICR_ISC13_Msk      (0x1UL << HSEM_C1ICR_ISC13_Pos)              /*!< 0x00002000 */\n#define HSEM_C1ICR_ISC13          HSEM_C1ICR_ISC13_Msk                         /*!<semaphore 13 interrupt 0 clear bit. */\n#define HSEM_C1ICR_ISC14_Pos      (14U)\n#define HSEM_C1ICR_ISC14_Msk      (0x1UL << HSEM_C1ICR_ISC14_Pos)              /*!< 0x00004000 */\n#define HSEM_C1ICR_ISC14          HSEM_C1ICR_ISC14_Msk                         /*!<semaphore 14 interrupt 0 clear bit. */\n#define HSEM_C1ICR_ISC15_Pos      (15U)\n#define HSEM_C1ICR_ISC15_Msk      (0x1UL << HSEM_C1ICR_ISC15_Pos)              /*!< 0x00008000 */\n#define HSEM_C1ICR_ISC15          HSEM_C1ICR_ISC15_Msk                         /*!<semaphore 15 interrupt 0 clear bit. */\n#define HSEM_C1ICR_ISC16_Pos      (16U)\n#define HSEM_C1ICR_ISC16_Msk      (0x1UL << HSEM_C1ICR_ISC16_Pos)              /*!< 0x00010000 */\n#define HSEM_C1ICR_ISC16          HSEM_C1ICR_ISC16_Msk                         /*!<semaphore 16 interrupt 0 clear bit. */\n#define HSEM_C1ICR_ISC17_Pos      (17U)\n#define HSEM_C1ICR_ISC17_Msk      (0x1UL << HSEM_C1ICR_ISC17_Pos)              /*!< 0x00020000 */\n#define HSEM_C1ICR_ISC17          HSEM_C1ICR_ISC17_Msk                         /*!<semaphore 17 interrupt 0 clear bit. */\n#define HSEM_C1ICR_ISC18_Pos      (18U)\n#define HSEM_C1ICR_ISC18_Msk      (0x1UL << HSEM_C1ICR_ISC18_Pos)              /*!< 0x00040000 */\n#define HSEM_C1ICR_ISC18          HSEM_C1ICR_ISC18_Msk                         /*!<semaphore 18 interrupt 0 clear bit. */\n#define HSEM_C1ICR_ISC19_Pos      (19U)\n#define HSEM_C1ICR_ISC19_Msk      (0x1UL << HSEM_C1ICR_ISC19_Pos)              /*!< 0x00080000 */\n#define HSEM_C1ICR_ISC19          HSEM_C1ICR_ISC19_Msk                         /*!<semaphore 19 interrupt 0 clear bit. */\n#define HSEM_C1ICR_ISC20_Pos      (20U)\n#define HSEM_C1ICR_ISC20_Msk      (0x1UL << HSEM_C1ICR_ISC20_Pos)              /*!< 0x00100000 */\n#define HSEM_C1ICR_ISC20          HSEM_C1ICR_ISC20_Msk                         /*!<semaphore 20 interrupt 0 clear bit. */\n#define HSEM_C1ICR_ISC21_Pos      (21U)\n#define HSEM_C1ICR_ISC21_Msk      (0x1UL << HSEM_C1ICR_ISC21_Pos)              /*!< 0x00200000 */\n#define HSEM_C1ICR_ISC21          HSEM_C1ICR_ISC21_Msk                         /*!<semaphore 21 interrupt 0 clear bit. */\n#define HSEM_C1ICR_ISC22_Pos      (22U)\n#define HSEM_C1ICR_ISC22_Msk      (0x1UL << HSEM_C1ICR_ISC22_Pos)              /*!< 0x00400000 */\n#define HSEM_C1ICR_ISC22          HSEM_C1ICR_ISC22_Msk                         /*!<semaphore 22 interrupt 0 clear bit. */\n#define HSEM_C1ICR_ISC23_Pos      (23U)\n#define HSEM_C1ICR_ISC23_Msk      (0x1UL << HSEM_C1ICR_ISC23_Pos)              /*!< 0x00800000 */\n#define HSEM_C1ICR_ISC23          HSEM_C1ICR_ISC23_Msk                         /*!<semaphore 23 interrupt 0 clear bit. */\n#define HSEM_C1ICR_ISC24_Pos      (24U)\n#define HSEM_C1ICR_ISC24_Msk      (0x1UL << HSEM_C1ICR_ISC24_Pos)              /*!< 0x01000000 */\n#define HSEM_C1ICR_ISC24          HSEM_C1ICR_ISC24_Msk                         /*!<semaphore 24 interrupt 0 clear bit. */\n#define HSEM_C1ICR_ISC25_Pos      (25U)\n#define HSEM_C1ICR_ISC25_Msk      (0x1UL << HSEM_C1ICR_ISC25_Pos)              /*!< 0x02000000 */\n#define HSEM_C1ICR_ISC25          HSEM_C1ICR_ISC25_Msk                         /*!<semaphore 25 interrupt 0 clear bit. */\n#define HSEM_C1ICR_ISC26_Pos      (26U)\n#define HSEM_C1ICR_ISC26_Msk      (0x1UL << HSEM_C1ICR_ISC26_Pos)              /*!< 0x04000000 */\n#define HSEM_C1ICR_ISC26          HSEM_C1ICR_ISC26_Msk                         /*!<semaphore 26 interrupt 0 clear bit. */\n#define HSEM_C1ICR_ISC27_Pos      (27U)\n#define HSEM_C1ICR_ISC27_Msk      (0x1UL << HSEM_C1ICR_ISC27_Pos)              /*!< 0x08000000 */\n#define HSEM_C1ICR_ISC27          HSEM_C1ICR_ISC27_Msk                         /*!<semaphore 27 interrupt 0 clear bit. */\n#define HSEM_C1ICR_ISC28_Pos      (28U)\n#define HSEM_C1ICR_ISC28_Msk      (0x1UL << HSEM_C1ICR_ISC28_Pos)              /*!< 0x10000000 */\n#define HSEM_C1ICR_ISC28          HSEM_C1ICR_ISC28_Msk                         /*!<semaphore 28 interrupt 0 clear bit. */\n#define HSEM_C1ICR_ISC29_Pos      (29U)\n#define HSEM_C1ICR_ISC29_Msk      (0x1UL << HSEM_C1ICR_ISC29_Pos)              /*!< 0x20000000 */\n#define HSEM_C1ICR_ISC29          HSEM_C1ICR_ISC29_Msk                         /*!<semaphore 29 interrupt 0 clear bit. */\n#define HSEM_C1ICR_ISC30_Pos      (30U)\n#define HSEM_C1ICR_ISC30_Msk      (0x1UL << HSEM_C1ICR_ISC30_Pos)              /*!< 0x40000000 */\n#define HSEM_C1ICR_ISC30          HSEM_C1ICR_ISC30_Msk                         /*!<semaphore 30 interrupt 0 clear bit. */\n#define HSEM_C1ICR_ISC31_Pos      (31U)\n#define HSEM_C1ICR_ISC31_Msk      (0x1UL << HSEM_C1ICR_ISC31_Pos)              /*!< 0x80000000 */\n#define HSEM_C1ICR_ISC31          HSEM_C1ICR_ISC31_Msk                         /*!<semaphore 31 interrupt 0 clear bit. */\n\n/********************  Bit definition for HSEM_C1ISR register  *****************/\n#define HSEM_C1ISR_ISF0_Pos       (0U)\n#define HSEM_C1ISR_ISF0_Msk       (0x1UL << HSEM_C1ISR_ISF0_Pos)               /*!< 0x00000001 */\n#define HSEM_C1ISR_ISF0           HSEM_C1ISR_ISF0_Msk                          /*!<semaphore 0 interrupt 0 status bit.  */\n#define HSEM_C1ISR_ISF1_Pos       (1U)\n#define HSEM_C1ISR_ISF1_Msk       (0x1UL << HSEM_C1ISR_ISF1_Pos)               /*!< 0x00000002 */\n#define HSEM_C1ISR_ISF1           HSEM_C1ISR_ISF1_Msk                          /*!<semaphore 1 interrupt 0 status bit.  */\n#define HSEM_C1ISR_ISF2_Pos       (2U)\n#define HSEM_C1ISR_ISF2_Msk       (0x1UL << HSEM_C1ISR_ISF2_Pos)               /*!< 0x00000004 */\n#define HSEM_C1ISR_ISF2           HSEM_C1ISR_ISF2_Msk                          /*!<semaphore 2 interrupt 0 status bit.  */\n#define HSEM_C1ISR_ISF3_Pos       (3U)\n#define HSEM_C1ISR_ISF3_Msk       (0x1UL << HSEM_C1ISR_ISF3_Pos)               /*!< 0x00000008 */\n#define HSEM_C1ISR_ISF3           HSEM_C1ISR_ISF3_Msk                          /*!<semaphore 3 interrupt 0 status bit.  */\n#define HSEM_C1ISR_ISF4_Pos       (4U)\n#define HSEM_C1ISR_ISF4_Msk       (0x1UL << HSEM_C1ISR_ISF4_Pos)               /*!< 0x00000010 */\n#define HSEM_C1ISR_ISF4           HSEM_C1ISR_ISF4_Msk                          /*!<semaphore 4 interrupt 0 status bit.  */\n#define HSEM_C1ISR_ISF5_Pos       (5U)\n#define HSEM_C1ISR_ISF5_Msk       (0x1UL << HSEM_C1ISR_ISF5_Pos)               /*!< 0x00000020 */\n#define HSEM_C1ISR_ISF5           HSEM_C1ISR_ISF5_Msk                          /*!<semaphore 5 interrupt 0 status bit.  */\n#define HSEM_C1ISR_ISF6_Pos       (6U)\n#define HSEM_C1ISR_ISF6_Msk       (0x1UL << HSEM_C1ISR_ISF6_Pos)               /*!< 0x00000040 */\n#define HSEM_C1ISR_ISF6           HSEM_C1ISR_ISF6_Msk                          /*!<semaphore 6 interrupt 0 status bit.  */\n#define HSEM_C1ISR_ISF7_Pos       (7U)\n#define HSEM_C1ISR_ISF7_Msk       (0x1UL << HSEM_C1ISR_ISF7_Pos)               /*!< 0x00000080 */\n#define HSEM_C1ISR_ISF7           HSEM_C1ISR_ISF7_Msk                          /*!<semaphore 7 interrupt 0 status bit.  */\n#define HSEM_C1ISR_ISF8_Pos       (8U)\n#define HSEM_C1ISR_ISF8_Msk       (0x1UL << HSEM_C1ISR_ISF8_Pos)               /*!< 0x00000100 */\n#define HSEM_C1ISR_ISF8           HSEM_C1ISR_ISF8_Msk                          /*!<semaphore 8 interrupt 0 status bit.  */\n#define HSEM_C1ISR_ISF9_Pos       (9U)\n#define HSEM_C1ISR_ISF9_Msk       (0x1UL << HSEM_C1ISR_ISF9_Pos)               /*!< 0x00000200 */\n#define HSEM_C1ISR_ISF9           HSEM_C1ISR_ISF9_Msk                          /*!<semaphore 9 interrupt 0 status bit.  */\n#define HSEM_C1ISR_ISF10_Pos      (10U)\n#define HSEM_C1ISR_ISF10_Msk      (0x1UL << HSEM_C1ISR_ISF10_Pos)              /*!< 0x00000400 */\n#define HSEM_C1ISR_ISF10          HSEM_C1ISR_ISF10_Msk                         /*!<semaphore 10 interrupt 0 status bit. */\n#define HSEM_C1ISR_ISF11_Pos      (11U)\n#define HSEM_C1ISR_ISF11_Msk      (0x1UL << HSEM_C1ISR_ISF11_Pos)              /*!< 0x00000800 */\n#define HSEM_C1ISR_ISF11          HSEM_C1ISR_ISF11_Msk                         /*!<semaphore 11 interrupt 0 status bit. */\n#define HSEM_C1ISR_ISF12_Pos      (12U)\n#define HSEM_C1ISR_ISF12_Msk      (0x1UL << HSEM_C1ISR_ISF12_Pos)              /*!< 0x00001000 */\n#define HSEM_C1ISR_ISF12          HSEM_C1ISR_ISF12_Msk                         /*!<semaphore 12 interrupt 0 status bit. */\n#define HSEM_C1ISR_ISF13_Pos      (13U)\n#define HSEM_C1ISR_ISF13_Msk      (0x1UL << HSEM_C1ISR_ISF13_Pos)              /*!< 0x00002000 */\n#define HSEM_C1ISR_ISF13          HSEM_C1ISR_ISF13_Msk                         /*!<semaphore 13 interrupt 0 status bit. */\n#define HSEM_C1ISR_ISF14_Pos      (14U)\n#define HSEM_C1ISR_ISF14_Msk      (0x1UL << HSEM_C1ISR_ISF14_Pos)              /*!< 0x00004000 */\n#define HSEM_C1ISR_ISF14          HSEM_C1ISR_ISF14_Msk                         /*!<semaphore 14 interrupt 0 status bit. */\n#define HSEM_C1ISR_ISF15_Pos      (15U)\n#define HSEM_C1ISR_ISF15_Msk      (0x1UL << HSEM_C1ISR_ISF15_Pos)              /*!< 0x00008000 */\n#define HSEM_C1ISR_ISF15          HSEM_C1ISR_ISF15_Msk                         /*!<semaphore 15 interrupt 0 status bit. */\n#define HSEM_C1ISR_ISF16_Pos      (16U)\n#define HSEM_C1ISR_ISF16_Msk      (0x1UL << HSEM_C1ISR_ISF16_Pos)              /*!< 0x00010000 */\n#define HSEM_C1ISR_ISF16          HSEM_C1ISR_ISF16_Msk                         /*!<semaphore 16 interrupt 0 status bit. */\n#define HSEM_C1ISR_ISF17_Pos      (17U)\n#define HSEM_C1ISR_ISF17_Msk      (0x1UL << HSEM_C1ISR_ISF17_Pos)              /*!< 0x00020000 */\n#define HSEM_C1ISR_ISF17          HSEM_C1ISR_ISF17_Msk                         /*!<semaphore 17 interrupt 0 status bit. */\n#define HSEM_C1ISR_ISF18_Pos      (18U)\n#define HSEM_C1ISR_ISF18_Msk      (0x1UL << HSEM_C1ISR_ISF18_Pos)              /*!< 0x00040000 */\n#define HSEM_C1ISR_ISF18          HSEM_C1ISR_ISF18_Msk                         /*!<semaphore 18 interrupt 0 status bit. */\n#define HSEM_C1ISR_ISF19_Pos      (19U)\n#define HSEM_C1ISR_ISF19_Msk      (0x1UL << HSEM_C1ISR_ISF19_Pos)              /*!< 0x00080000 */\n#define HSEM_C1ISR_ISF19          HSEM_C1ISR_ISF19_Msk                         /*!<semaphore 19 interrupt 0 status bit. */\n#define HSEM_C1ISR_ISF20_Pos      (20U)\n#define HSEM_C1ISR_ISF20_Msk      (0x1UL << HSEM_C1ISR_ISF20_Pos)              /*!< 0x00100000 */\n#define HSEM_C1ISR_ISF20          HSEM_C1ISR_ISF20_Msk                         /*!<semaphore 20 interrupt 0 status bit. */\n#define HSEM_C1ISR_ISF21_Pos      (21U)\n#define HSEM_C1ISR_ISF21_Msk      (0x1UL << HSEM_C1ISR_ISF21_Pos)              /*!< 0x00200000 */\n#define HSEM_C1ISR_ISF21          HSEM_C1ISR_ISF21_Msk                         /*!<semaphore 21 interrupt 0 status bit. */\n#define HSEM_C1ISR_ISF22_Pos      (22U)\n#define HSEM_C1ISR_ISF22_Msk      (0x1UL << HSEM_C1ISR_ISF22_Pos)              /*!< 0x00400000 */\n#define HSEM_C1ISR_ISF22          HSEM_C1ISR_ISF22_Msk                         /*!<semaphore 22 interrupt 0 status bit. */\n#define HSEM_C1ISR_ISF23_Pos      (23U)\n#define HSEM_C1ISR_ISF23_Msk      (0x1UL << HSEM_C1ISR_ISF23_Pos)              /*!< 0x00800000 */\n#define HSEM_C1ISR_ISF23          HSEM_C1ISR_ISF23_Msk                         /*!<semaphore 23 interrupt 0 status bit. */\n#define HSEM_C1ISR_ISF24_Pos      (24U)\n#define HSEM_C1ISR_ISF24_Msk      (0x1UL << HSEM_C1ISR_ISF24_Pos)              /*!< 0x01000000 */\n#define HSEM_C1ISR_ISF24          HSEM_C1ISR_ISF24_Msk                         /*!<semaphore 24 interrupt 0 status bit. */\n#define HSEM_C1ISR_ISF25_Pos      (25U)\n#define HSEM_C1ISR_ISF25_Msk      (0x1UL << HSEM_C1ISR_ISF25_Pos)              /*!< 0x02000000 */\n#define HSEM_C1ISR_ISF25          HSEM_C1ISR_ISF25_Msk                         /*!<semaphore 25 interrupt 0 status bit. */\n#define HSEM_C1ISR_ISF26_Pos      (26U)\n#define HSEM_C1ISR_ISF26_Msk      (0x1UL << HSEM_C1ISR_ISF26_Pos)              /*!< 0x04000000 */\n#define HSEM_C1ISR_ISF26          HSEM_C1ISR_ISF26_Msk                         /*!<semaphore 26 interrupt 0 status bit. */\n#define HSEM_C1ISR_ISF27_Pos      (27U)\n#define HSEM_C1ISR_ISF27_Msk      (0x1UL << HSEM_C1ISR_ISF27_Pos)              /*!< 0x08000000 */\n#define HSEM_C1ISR_ISF27          HSEM_C1ISR_ISF27_Msk                         /*!<semaphore 27 interrupt 0 status bit. */\n#define HSEM_C1ISR_ISF28_Pos      (28U)\n#define HSEM_C1ISR_ISF28_Msk      (0x1UL << HSEM_C1ISR_ISF28_Pos)              /*!< 0x10000000 */\n#define HSEM_C1ISR_ISF28          HSEM_C1ISR_ISF28_Msk                         /*!<semaphore 28 interrupt 0 status bit. */\n#define HSEM_C1ISR_ISF29_Pos      (29U)\n#define HSEM_C1ISR_ISF29_Msk      (0x1UL << HSEM_C1ISR_ISF29_Pos)              /*!< 0x20000000 */\n#define HSEM_C1ISR_ISF29          HSEM_C1ISR_ISF29_Msk                         /*!<semaphore 29 interrupt 0 status bit. */\n#define HSEM_C1ISR_ISF30_Pos      (30U)\n#define HSEM_C1ISR_ISF30_Msk      (0x1UL << HSEM_C1ISR_ISF30_Pos)              /*!< 0x40000000 */\n#define HSEM_C1ISR_ISF30          HSEM_C1ISR_ISF30_Msk                         /*!<semaphore 30 interrupt 0 status bit. */\n#define HSEM_C1ISR_ISF31_Pos      (31U)\n#define HSEM_C1ISR_ISF31_Msk      (0x1UL << HSEM_C1ISR_ISF31_Pos)              /*!< 0x80000000 */\n#define HSEM_C1ISR_ISF31          HSEM_C1ISR_ISF31_Msk                         /*!<semaphore 31 interrupt 0 status bit. */\n\n/********************  Bit definition for HSEM_C1MISR register  *****************/\n#define HSEM_C1MISR_MISF0_Pos     (0U)\n#define HSEM_C1MISR_MISF0_Msk     (0x1UL << HSEM_C1MISR_MISF0_Pos)             /*!< 0x00000001 */\n#define HSEM_C1MISR_MISF0         HSEM_C1MISR_MISF0_Msk                        /*!<semaphore 0 interrupt 0 masked status bit.  */\n#define HSEM_C1MISR_MISF1_Pos     (1U)\n#define HSEM_C1MISR_MISF1_Msk     (0x1UL << HSEM_C1MISR_MISF1_Pos)             /*!< 0x00000002 */\n#define HSEM_C1MISR_MISF1         HSEM_C1MISR_MISF1_Msk                        /*!<semaphore 1 interrupt 0 masked status bit.  */\n#define HSEM_C1MISR_MISF2_Pos     (2U)\n#define HSEM_C1MISR_MISF2_Msk     (0x1UL << HSEM_C1MISR_MISF2_Pos)             /*!< 0x00000004 */\n#define HSEM_C1MISR_MISF2         HSEM_C1MISR_MISF2_Msk                        /*!<semaphore 2 interrupt 0 masked status bit.  */\n#define HSEM_C1MISR_MISF3_Pos     (3U)\n#define HSEM_C1MISR_MISF3_Msk     (0x1UL << HSEM_C1MISR_MISF3_Pos)             /*!< 0x00000008 */\n#define HSEM_C1MISR_MISF3         HSEM_C1MISR_MISF3_Msk                        /*!<semaphore 3 interrupt 0 masked status bit.  */\n#define HSEM_C1MISR_MISF4_Pos     (4U)\n#define HSEM_C1MISR_MISF4_Msk     (0x1UL << HSEM_C1MISR_MISF4_Pos)             /*!< 0x00000010 */\n#define HSEM_C1MISR_MISF4         HSEM_C1MISR_MISF4_Msk                        /*!<semaphore 4 interrupt 0 masked status bit.  */\n#define HSEM_C1MISR_MISF5_Pos     (5U)\n#define HSEM_C1MISR_MISF5_Msk     (0x1UL << HSEM_C1MISR_MISF5_Pos)             /*!< 0x00000020 */\n#define HSEM_C1MISR_MISF5         HSEM_C1MISR_MISF5_Msk                        /*!<semaphore 5 interrupt 0 masked status bit.  */\n#define HSEM_C1MISR_MISF6_Pos     (6U)\n#define HSEM_C1MISR_MISF6_Msk     (0x1UL << HSEM_C1MISR_MISF6_Pos)             /*!< 0x00000040 */\n#define HSEM_C1MISR_MISF6         HSEM_C1MISR_MISF6_Msk                        /*!<semaphore 6 interrupt 0 masked status bit.  */\n#define HSEM_C1MISR_MISF7_Pos     (7U)\n#define HSEM_C1MISR_MISF7_Msk     (0x1UL << HSEM_C1MISR_MISF7_Pos)             /*!< 0x00000080 */\n#define HSEM_C1MISR_MISF7         HSEM_C1MISR_MISF7_Msk                        /*!<semaphore 7 interrupt 0 masked status bit.  */\n#define HSEM_C1MISR_MISF8_Pos     (8U)\n#define HSEM_C1MISR_MISF8_Msk     (0x1UL << HSEM_C1MISR_MISF8_Pos)             /*!< 0x00000100 */\n#define HSEM_C1MISR_MISF8         HSEM_C1MISR_MISF8_Msk                        /*!<semaphore 8 interrupt 0 masked status bit.  */\n#define HSEM_C1MISR_MISF9_Pos     (9U)\n#define HSEM_C1MISR_MISF9_Msk     (0x1UL << HSEM_C1MISR_MISF9_Pos)             /*!< 0x00000200 */\n#define HSEM_C1MISR_MISF9         HSEM_C1MISR_MISF9_Msk                        /*!<semaphore 9 interrupt 0 masked status bit.  */\n#define HSEM_C1MISR_MISF10_Pos    (10U)\n#define HSEM_C1MISR_MISF10_Msk    (0x1UL << HSEM_C1MISR_MISF10_Pos)            /*!< 0x00000400 */\n#define HSEM_C1MISR_MISF10        HSEM_C1MISR_MISF10_Msk                       /*!<semaphore 10 interrupt 0 masked status bit. */\n#define HSEM_C1MISR_MISF11_Pos    (11U)\n#define HSEM_C1MISR_MISF11_Msk    (0x1UL << HSEM_C1MISR_MISF11_Pos)            /*!< 0x00000800 */\n#define HSEM_C1MISR_MISF11        HSEM_C1MISR_MISF11_Msk                       /*!<semaphore 11 interrupt 0 masked status bit. */\n#define HSEM_C1MISR_MISF12_Pos    (12U)\n#define HSEM_C1MISR_MISF12_Msk    (0x1UL << HSEM_C1MISR_MISF12_Pos)            /*!< 0x00001000 */\n#define HSEM_C1MISR_MISF12        HSEM_C1MISR_MISF12_Msk                       /*!<semaphore 12 interrupt 0 masked status bit. */\n#define HSEM_C1MISR_MISF13_Pos    (13U)\n#define HSEM_C1MISR_MISF13_Msk    (0x1UL << HSEM_C1MISR_MISF13_Pos)            /*!< 0x00002000 */\n#define HSEM_C1MISR_MISF13        HSEM_C1MISR_MISF13_Msk                       /*!<semaphore 13 interrupt 0 masked status bit. */\n#define HSEM_C1MISR_MISF14_Pos    (14U)\n#define HSEM_C1MISR_MISF14_Msk    (0x1UL << HSEM_C1MISR_MISF14_Pos)            /*!< 0x00004000 */\n#define HSEM_C1MISR_MISF14        HSEM_C1MISR_MISF14_Msk                       /*!<semaphore 14 interrupt 0 masked status bit. */\n#define HSEM_C1MISR_MISF15_Pos    (15U)\n#define HSEM_C1MISR_MISF15_Msk    (0x1UL << HSEM_C1MISR_MISF15_Pos)            /*!< 0x00008000 */\n#define HSEM_C1MISR_MISF15        HSEM_C1MISR_MISF15_Msk                       /*!<semaphore 15 interrupt 0 masked status bit. */\n#define HSEM_C1MISR_MISF16_Pos    (16U)\n#define HSEM_C1MISR_MISF16_Msk    (0x1UL << HSEM_C1MISR_MISF16_Pos)            /*!< 0x00010000 */\n#define HSEM_C1MISR_MISF16        HSEM_C1MISR_MISF16_Msk                       /*!<semaphore 16 interrupt 0 masked status bit. */\n#define HSEM_C1MISR_MISF17_Pos    (17U)\n#define HSEM_C1MISR_MISF17_Msk    (0x1UL << HSEM_C1MISR_MISF17_Pos)            /*!< 0x00020000 */\n#define HSEM_C1MISR_MISF17        HSEM_C1MISR_MISF17_Msk                       /*!<semaphore 17 interrupt 0 masked status bit. */\n#define HSEM_C1MISR_MISF18_Pos    (18U)\n#define HSEM_C1MISR_MISF18_Msk    (0x1UL << HSEM_C1MISR_MISF18_Pos)            /*!< 0x00040000 */\n#define HSEM_C1MISR_MISF18        HSEM_C1MISR_MISF18_Msk                       /*!<semaphore 18 interrupt 0 masked status bit. */\n#define HSEM_C1MISR_MISF19_Pos    (19U)\n#define HSEM_C1MISR_MISF19_Msk    (0x1UL << HSEM_C1MISR_MISF19_Pos)            /*!< 0x00080000 */\n#define HSEM_C1MISR_MISF19        HSEM_C1MISR_MISF19_Msk                       /*!<semaphore 19 interrupt 0 masked status bit. */\n#define HSEM_C1MISR_MISF20_Pos    (20U)\n#define HSEM_C1MISR_MISF20_Msk    (0x1UL << HSEM_C1MISR_MISF20_Pos)            /*!< 0x00100000 */\n#define HSEM_C1MISR_MISF20        HSEM_C1MISR_MISF20_Msk                       /*!<semaphore 20 interrupt 0 masked status bit. */\n#define HSEM_C1MISR_MISF21_Pos    (21U)\n#define HSEM_C1MISR_MISF21_Msk    (0x1UL << HSEM_C1MISR_MISF21_Pos)            /*!< 0x00200000 */\n#define HSEM_C1MISR_MISF21        HSEM_C1MISR_MISF21_Msk                       /*!<semaphore 21 interrupt 0 masked status bit. */\n#define HSEM_C1MISR_MISF22_Pos    (22U)\n#define HSEM_C1MISR_MISF22_Msk    (0x1UL << HSEM_C1MISR_MISF22_Pos)            /*!< 0x00400000 */\n#define HSEM_C1MISR_MISF22        HSEM_C1MISR_MISF22_Msk                       /*!<semaphore 22 interrupt 0 masked status bit. */\n#define HSEM_C1MISR_MISF23_Pos    (23U)\n#define HSEM_C1MISR_MISF23_Msk    (0x1UL << HSEM_C1MISR_MISF23_Pos)            /*!< 0x00800000 */\n#define HSEM_C1MISR_MISF23        HSEM_C1MISR_MISF23_Msk                       /*!<semaphore 23 interrupt 0 masked status bit. */\n#define HSEM_C1MISR_MISF24_Pos    (24U)\n#define HSEM_C1MISR_MISF24_Msk    (0x1UL << HSEM_C1MISR_MISF24_Pos)            /*!< 0x01000000 */\n#define HSEM_C1MISR_MISF24        HSEM_C1MISR_MISF24_Msk                       /*!<semaphore 24 interrupt 0 masked status bit. */\n#define HSEM_C1MISR_MISF25_Pos    (25U)\n#define HSEM_C1MISR_MISF25_Msk    (0x1UL << HSEM_C1MISR_MISF25_Pos)            /*!< 0x02000000 */\n#define HSEM_C1MISR_MISF25        HSEM_C1MISR_MISF25_Msk                       /*!<semaphore 25 interrupt 0 masked status bit. */\n#define HSEM_C1MISR_MISF26_Pos    (26U)\n#define HSEM_C1MISR_MISF26_Msk    (0x1UL << HSEM_C1MISR_MISF26_Pos)            /*!< 0x04000000 */\n#define HSEM_C1MISR_MISF26        HSEM_C1MISR_MISF26_Msk                       /*!<semaphore 26 interrupt 0 masked status bit. */\n#define HSEM_C1MISR_MISF27_Pos    (27U)\n#define HSEM_C1MISR_MISF27_Msk    (0x1UL << HSEM_C1MISR_MISF27_Pos)            /*!< 0x08000000 */\n#define HSEM_C1MISR_MISF27        HSEM_C1MISR_MISF27_Msk                       /*!<semaphore 27 interrupt 0 masked status bit. */\n#define HSEM_C1MISR_MISF28_Pos    (28U)\n#define HSEM_C1MISR_MISF28_Msk    (0x1UL << HSEM_C1MISR_MISF28_Pos)            /*!< 0x10000000 */\n#define HSEM_C1MISR_MISF28        HSEM_C1MISR_MISF28_Msk                       /*!<semaphore 28 interrupt 0 masked status bit. */\n#define HSEM_C1MISR_MISF29_Pos    (29U)\n#define HSEM_C1MISR_MISF29_Msk    (0x1UL << HSEM_C1MISR_MISF29_Pos)            /*!< 0x20000000 */\n#define HSEM_C1MISR_MISF29        HSEM_C1MISR_MISF29_Msk                       /*!<semaphore 29 interrupt 0 masked status bit. */\n#define HSEM_C1MISR_MISF30_Pos    (30U)\n#define HSEM_C1MISR_MISF30_Msk    (0x1UL << HSEM_C1MISR_MISF30_Pos)            /*!< 0x40000000 */\n#define HSEM_C1MISR_MISF30        HSEM_C1MISR_MISF30_Msk                       /*!<semaphore 30 interrupt 0 masked status bit. */\n#define HSEM_C1MISR_MISF31_Pos    (31U)\n#define HSEM_C1MISR_MISF31_Msk    (0x1UL << HSEM_C1MISR_MISF31_Pos)            /*!< 0x80000000 */\n#define HSEM_C1MISR_MISF31        HSEM_C1MISR_MISF31_Msk                       /*!<semaphore 31 interrupt 0 masked status bit. */\n\n/********************  Bit definition for HSEM_CR register  *****************/\n#define HSEM_CR_COREID_Pos        (8U)\n#define HSEM_CR_COREID_Msk        (0xFFUL << HSEM_CR_COREID_Pos)               /*!< 0x0000FF00 */\n#define HSEM_CR_COREID            HSEM_CR_COREID_Msk                           /*!<CoreID of semaphores to be cleared. */\n#define HSEM_CR_KEY_Pos           (16U)\n#define HSEM_CR_KEY_Msk           (0xFFFFUL << HSEM_CR_KEY_Pos)                /*!< 0xFFFF0000 */\n#define HSEM_CR_KEY               HSEM_CR_KEY_Msk                              /*!<semaphores clear key. */\n\n/********************  Bit definition for HSEM_KEYR register  *****************/\n#define HSEM_KEYR_KEY_Pos         (16U)\n#define HSEM_KEYR_KEY_Msk         (0xFFFFUL << HSEM_KEYR_KEY_Pos)              /*!< 0xFFFF0000 */\n#define HSEM_KEYR_KEY             HSEM_KEYR_KEY_Msk                            /*!<semaphores clear key. */\n\n/******************************************************************************/\n/*                                                                            */\n/*                      Inter-integrated Circuit Interface (I2C)              */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for I2C_CR1 register  *******************/\n#define I2C_CR1_PE_Pos               (0U)\n#define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                 /*!< 0x00000001 */\n#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */\n#define I2C_CR1_TXIE_Pos             (1U)\n#define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)               /*!< 0x00000002 */\n#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */\n#define I2C_CR1_RXIE_Pos             (2U)\n#define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)               /*!< 0x00000004 */\n#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */\n#define I2C_CR1_ADDRIE_Pos           (3U)\n#define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)             /*!< 0x00000008 */\n#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */\n#define I2C_CR1_NACKIE_Pos           (4U)\n#define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)             /*!< 0x00000010 */\n#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */\n#define I2C_CR1_STOPIE_Pos           (5U)\n#define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)             /*!< 0x00000020 */\n#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */\n#define I2C_CR1_TCIE_Pos             (6U)\n#define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)               /*!< 0x00000040 */\n#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */\n#define I2C_CR1_ERRIE_Pos            (7U)\n#define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)              /*!< 0x00000080 */\n#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */\n#define I2C_CR1_DNF_Pos              (8U)\n#define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                /*!< 0x00000F00 */\n#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */\n#define I2C_CR1_ANFOFF_Pos           (12U)\n#define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)             /*!< 0x00001000 */\n#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */\n#define I2C_CR1_TXDMAEN_Pos          (14U)\n#define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)            /*!< 0x00004000 */\n#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */\n#define I2C_CR1_RXDMAEN_Pos          (15U)\n#define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)            /*!< 0x00008000 */\n#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */\n#define I2C_CR1_SBC_Pos              (16U)\n#define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                /*!< 0x00010000 */\n#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */\n#define I2C_CR1_NOSTRETCH_Pos        (17U)\n#define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)          /*!< 0x00020000 */\n#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */\n#define I2C_CR1_WUPEN_Pos            (18U)\n#define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)              /*!< 0x00040000 */\n#define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */\n#define I2C_CR1_GCEN_Pos             (19U)\n#define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)               /*!< 0x00080000 */\n#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */\n#define I2C_CR1_SMBHEN_Pos           (20U)\n#define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)             /*!< 0x00100000 */\n#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */\n#define I2C_CR1_SMBDEN_Pos           (21U)\n#define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)             /*!< 0x00200000 */\n#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */\n#define I2C_CR1_ALERTEN_Pos          (22U)\n#define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)            /*!< 0x00400000 */\n#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */\n#define I2C_CR1_PECEN_Pos            (23U)\n#define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)              /*!< 0x00800000 */\n#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */\n\n/******************  Bit definition for I2C_CR2 register  ********************/\n#define I2C_CR2_SADD_Pos             (0U)\n#define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)             /*!< 0x000003FF */\n#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */\n#define I2C_CR2_RD_WRN_Pos           (10U)\n#define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)             /*!< 0x00000400 */\n#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */\n#define I2C_CR2_ADD10_Pos            (11U)\n#define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)              /*!< 0x00000800 */\n#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */\n#define I2C_CR2_HEAD10R_Pos          (12U)\n#define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)            /*!< 0x00001000 */\n#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */\n#define I2C_CR2_START_Pos            (13U)\n#define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)              /*!< 0x00002000 */\n#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */\n#define I2C_CR2_STOP_Pos             (14U)\n#define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)               /*!< 0x00004000 */\n#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */\n#define I2C_CR2_NACK_Pos             (15U)\n#define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)               /*!< 0x00008000 */\n#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */\n#define I2C_CR2_NBYTES_Pos           (16U)\n#define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)            /*!< 0x00FF0000 */\n#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */\n#define I2C_CR2_RELOAD_Pos           (24U)\n#define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)             /*!< 0x01000000 */\n#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */\n#define I2C_CR2_AUTOEND_Pos          (25U)\n#define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)            /*!< 0x02000000 */\n#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */\n#define I2C_CR2_PECBYTE_Pos          (26U)\n#define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)            /*!< 0x04000000 */\n#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */\n\n/*******************  Bit definition for I2C_OAR1 register  ******************/\n#define I2C_OAR1_OA1_Pos             (0U)\n#define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)             /*!< 0x000003FF */\n#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */\n#define I2C_OAR1_OA1MODE_Pos         (10U)\n#define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)           /*!< 0x00000400 */\n#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */\n#define I2C_OAR1_OA1EN_Pos           (15U)\n#define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)             /*!< 0x00008000 */\n#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */\n\n/*******************  Bit definition for I2C_OAR2 register  ******************/\n#define I2C_OAR2_OA2_Pos             (1U)\n#define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)              /*!< 0x000000FE */\n#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2 */\n#define I2C_OAR2_OA2MSK_Pos          (8U)\n#define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)            /*!< 0x00000700 */\n#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks */\n#define I2C_OAR2_OA2NOMASK           0x00000000UL                              /*!< No mask */\n#define I2C_OAR2_OA2MASK01_Pos       (8U)\n#define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)         /*!< 0x00000100 */\n#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared */\n#define I2C_OAR2_OA2MASK02_Pos       (9U)\n#define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)         /*!< 0x00000200 */\n#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */\n#define I2C_OAR2_OA2MASK03_Pos       (8U)\n#define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)         /*!< 0x00000300 */\n#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */\n#define I2C_OAR2_OA2MASK04_Pos       (10U)\n#define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)         /*!< 0x00000400 */\n#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */\n#define I2C_OAR2_OA2MASK05_Pos       (8U)\n#define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)         /*!< 0x00000500 */\n#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */\n#define I2C_OAR2_OA2MASK06_Pos       (9U)\n#define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)         /*!< 0x00000600 */\n#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared */\n#define I2C_OAR2_OA2MASK07_Pos       (8U)\n#define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)         /*!< 0x00000700 */\n#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done */\n#define I2C_OAR2_OA2EN_Pos           (15U)\n#define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)             /*!< 0x00008000 */\n#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable */\n\n/*******************  Bit definition for I2C_TIMINGR register *******************/\n#define I2C_TIMINGR_SCLL_Pos         (0U)\n#define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)          /*!< 0x000000FF */\n#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */\n#define I2C_TIMINGR_SCLH_Pos         (8U)\n#define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)          /*!< 0x0000FF00 */\n#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */\n#define I2C_TIMINGR_SDADEL_Pos       (16U)\n#define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)         /*!< 0x000F0000 */\n#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */\n#define I2C_TIMINGR_SCLDEL_Pos       (20U)\n#define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)         /*!< 0x00F00000 */\n#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */\n#define I2C_TIMINGR_PRESC_Pos        (28U)\n#define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)          /*!< 0xF0000000 */\n#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */\n\n/******************* Bit definition for I2C_TIMEOUTR register *******************/\n#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)\n#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)    /*!< 0x00000FFF */\n#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */\n#define I2C_TIMEOUTR_TIDLE_Pos       (12U)\n#define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)         /*!< 0x00001000 */\n#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */\n#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)\n#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)      /*!< 0x00008000 */\n#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */\n#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)\n#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)    /*!< 0x0FFF0000 */\n#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/\n#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)\n#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)        /*!< 0x80000000 */\n#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */\n\n/******************  Bit definition for I2C_ISR register  *********************/\n#define I2C_ISR_TXE_Pos              (0U)\n#define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                /*!< 0x00000001 */\n#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */\n#define I2C_ISR_TXIS_Pos             (1U)\n#define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)               /*!< 0x00000002 */\n#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */\n#define I2C_ISR_RXNE_Pos             (2U)\n#define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)               /*!< 0x00000004 */\n#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */\n#define I2C_ISR_ADDR_Pos             (3U)\n#define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)               /*!< 0x00000008 */\n#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/\n#define I2C_ISR_NACKF_Pos            (4U)\n#define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)              /*!< 0x00000010 */\n#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */\n#define I2C_ISR_STOPF_Pos            (5U)\n#define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)              /*!< 0x00000020 */\n#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */\n#define I2C_ISR_TC_Pos               (6U)\n#define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                 /*!< 0x00000040 */\n#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */\n#define I2C_ISR_TCR_Pos              (7U)\n#define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                /*!< 0x00000080 */\n#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */\n#define I2C_ISR_BERR_Pos             (8U)\n#define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)               /*!< 0x00000100 */\n#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */\n#define I2C_ISR_ARLO_Pos             (9U)\n#define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)               /*!< 0x00000200 */\n#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */\n#define I2C_ISR_OVR_Pos              (10U)\n#define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                /*!< 0x00000400 */\n#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */\n#define I2C_ISR_PECERR_Pos           (11U)\n#define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)             /*!< 0x00000800 */\n#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */\n#define I2C_ISR_TIMEOUT_Pos          (12U)\n#define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)            /*!< 0x00001000 */\n#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */\n#define I2C_ISR_ALERT_Pos            (13U)\n#define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)              /*!< 0x00002000 */\n#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */\n#define I2C_ISR_BUSY_Pos             (15U)\n#define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)               /*!< 0x00008000 */\n#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */\n#define I2C_ISR_DIR_Pos              (16U)\n#define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                /*!< 0x00010000 */\n#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */\n#define I2C_ISR_ADDCODE_Pos          (17U)\n#define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)           /*!< 0x00FE0000 */\n#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */\n\n/******************  Bit definition for I2C_ICR register  *********************/\n#define I2C_ICR_ADDRCF_Pos           (3U)\n#define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)             /*!< 0x00000008 */\n#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */\n#define I2C_ICR_NACKCF_Pos           (4U)\n#define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)             /*!< 0x00000010 */\n#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */\n#define I2C_ICR_STOPCF_Pos           (5U)\n#define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)             /*!< 0x00000020 */\n#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */\n#define I2C_ICR_BERRCF_Pos           (8U)\n#define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)             /*!< 0x00000100 */\n#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */\n#define I2C_ICR_ARLOCF_Pos           (9U)\n#define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)             /*!< 0x00000200 */\n#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */\n#define I2C_ICR_OVRCF_Pos            (10U)\n#define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)              /*!< 0x00000400 */\n#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */\n#define I2C_ICR_PECCF_Pos            (11U)\n#define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)              /*!< 0x00000800 */\n#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */\n#define I2C_ICR_TIMOUTCF_Pos         (12U)\n#define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)           /*!< 0x00001000 */\n#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */\n#define I2C_ICR_ALERTCF_Pos          (13U)\n#define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)            /*!< 0x00002000 */\n#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */\n\n/******************  Bit definition for I2C_PECR register  *********************/\n#define I2C_PECR_PEC_Pos             (0U)\n#define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)              /*!< 0x000000FF */\n#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */\n\n/******************  Bit definition for I2C_RXDR register  *********************/\n#define I2C_RXDR_RXDATA_Pos          (0U)\n#define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)           /*!< 0x000000FF */\n#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */\n\n/******************  Bit definition for I2C_TXDR register  *********************/\n#define I2C_TXDR_TXDATA_Pos          (0U)\n#define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)           /*!< 0x000000FF */\n#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */\n\n/******************************************************************************/\n/*                                                                            */\n/*                           Independent WATCHDOG                             */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for IWDG_KR register  ********************/\n#define IWDG_KR_KEY_Pos      (0U)\n#define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                     /*!< 0x0000FFFF */\n#define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!<Key value (write only, read 0000h)  */\n\n/*******************  Bit definition for IWDG_PR register  ********************/\n#define IWDG_PR_PR_Pos       (0U)\n#define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                         /*!< 0x00000007 */\n#define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!<PR[2:0] (Prescaler divider)         */\n#define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                          /*!< 0x00000001 */\n#define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                          /*!< 0x00000002 */\n#define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                          /*!< 0x00000004 */\n\n/*******************  Bit definition for IWDG_RLR register  *******************/\n#define IWDG_RLR_RL_Pos      (0U)\n#define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                      /*!< 0x00000FFF */\n#define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!<Watchdog counter reload value        */\n\n/*******************  Bit definition for IWDG_SR register  ********************/\n#define IWDG_SR_PVU_Pos      (0U)\n#define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                        /*!< 0x00000001 */\n#define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */\n#define IWDG_SR_RVU_Pos      (1U)\n#define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                        /*!< 0x00000002 */\n#define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */\n#define IWDG_SR_WVU_Pos      (2U)\n#define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                        /*!< 0x00000004 */\n#define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */\n\n/*******************  Bit definition for IWDG_KR register  ********************/\n#define IWDG_WINR_WIN_Pos    (0U)\n#define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                    /*!< 0x00000FFF */\n#define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */\n\n/******************************************************************************/\n/*                                                                            */\n/*                        JPEG Encoder/Decoder                                */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for CONFR0 register  ********************/\n#define JPEG_CONFR0_START_Pos           (0U)\n#define JPEG_CONFR0_START_Msk           (0x1UL << JPEG_CONFR0_START_Pos)       /*!< 0x00000001 */\n#define JPEG_CONFR0_START               JPEG_CONFR0_START_Msk                  /*!<Start/Stop bit */\n\n/********************  Bit definition for CONFR1 register  ********************/\n#define JPEG_CONFR1_NF_Pos              (0U)\n#define JPEG_CONFR1_NF_Msk              (0x3UL << JPEG_CONFR1_NF_Pos)          /*!< 0x00000003 */\n#define JPEG_CONFR1_NF                  JPEG_CONFR1_NF_Msk                     /*!<Number of color components */\n#define JPEG_CONFR1_NF_0                (0x1UL << JPEG_CONFR1_NF_Pos)           /*!< 0x00000001 */\n#define JPEG_CONFR1_NF_1                (0x2UL << JPEG_CONFR1_NF_Pos)           /*!< 0x00000002 */\n#define JPEG_CONFR1_DE_Pos              (3U)\n#define JPEG_CONFR1_DE_Msk              (0x1UL << JPEG_CONFR1_DE_Pos)          /*!< 0x00000008 */\n#define JPEG_CONFR1_DE                  JPEG_CONFR1_DE_Msk                     /*!<Decoding Enable */\n#define JPEG_CONFR1_COLORSPACE_Pos      (4U)\n#define JPEG_CONFR1_COLORSPACE_Msk      (0x3UL << JPEG_CONFR1_COLORSPACE_Pos)  /*!< 0x00000030 */\n#define JPEG_CONFR1_COLORSPACE          JPEG_CONFR1_COLORSPACE_Msk             /*!<Color Space */\n#define JPEG_CONFR1_COLORSPACE_0        (0x1UL << JPEG_CONFR1_COLORSPACE_Pos)   /*!< 0x00000010 */\n#define JPEG_CONFR1_COLORSPACE_1        (0x2UL << JPEG_CONFR1_COLORSPACE_Pos)   /*!< 0x00000020 */\n#define JPEG_CONFR1_NS_Pos              (6U)\n#define JPEG_CONFR1_NS_Msk              (0x3UL << JPEG_CONFR1_NS_Pos)          /*!< 0x000000C0 */\n#define JPEG_CONFR1_NS                  JPEG_CONFR1_NS_Msk                     /*!<Number of components for Scan */\n#define JPEG_CONFR1_NS_0                (0x1UL << JPEG_CONFR1_NS_Pos)           /*!< 0x00000040 */\n#define JPEG_CONFR1_NS_1                (0x2UL << JPEG_CONFR1_NS_Pos)           /*!< 0x00000080 */\n#define JPEG_CONFR1_HDR_Pos             (8U)\n#define JPEG_CONFR1_HDR_Msk             (0x1UL << JPEG_CONFR1_HDR_Pos)         /*!< 0x00000100 */\n#define JPEG_CONFR1_HDR                 JPEG_CONFR1_HDR_Msk                    /*!<Header Processing On/Off */\n#define JPEG_CONFR1_YSIZE_Pos           (16U)\n#define JPEG_CONFR1_YSIZE_Msk           (0xFFFFUL << JPEG_CONFR1_YSIZE_Pos)    /*!< 0xFFFF0000 */\n#define JPEG_CONFR1_YSIZE               JPEG_CONFR1_YSIZE_Msk                  /*!<Number of lines in source image */\n\n/********************  Bit definition for CONFR2 register  ********************/\n#define JPEG_CONFR2_NMCU_Pos            (0U)\n#define JPEG_CONFR2_NMCU_Msk            (0x3FFFFFFUL << JPEG_CONFR2_NMCU_Pos)  /*!< 0x03FFFFFF */\n#define JPEG_CONFR2_NMCU                JPEG_CONFR2_NMCU_Msk                   /*!<Number of MCU units minus 1 to encode */\n\n/********************  Bit definition for CONFR3 register  ********************/\n#define JPEG_CONFR3_XSIZE_Pos           (16U)\n#define JPEG_CONFR3_XSIZE_Msk           (0xFFFFUL << JPEG_CONFR3_XSIZE_Pos)    /*!< 0xFFFF0000 */\n#define JPEG_CONFR3_XSIZE               JPEG_CONFR3_XSIZE_Msk                  /*!<Number of pixels per line */\n\n/********************  Bit definition for CONFR4 register  ********************/\n#define JPEG_CONFR4_HD_Pos              (0U)\n#define JPEG_CONFR4_HD_Msk              (0x1UL << JPEG_CONFR4_HD_Pos)          /*!< 0x00000001 */\n#define JPEG_CONFR4_HD                  JPEG_CONFR4_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */\n#define JPEG_CONFR4_HA_Pos              (1U)\n#define JPEG_CONFR4_HA_Msk              (0x1UL << JPEG_CONFR4_HA_Pos)          /*!< 0x00000002 */\n#define JPEG_CONFR4_HA                  JPEG_CONFR4_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */\n#define JPEG_CONFR4_QT_Pos              (2U)\n#define JPEG_CONFR4_QT_Msk              (0x3UL << JPEG_CONFR4_QT_Pos)          /*!< 0x0000000C */\n#define JPEG_CONFR4_QT                  JPEG_CONFR4_QT_Msk                     /*!<Selects quantization table associated with a color component */\n#define JPEG_CONFR4_QT_0                (0x1UL << JPEG_CONFR4_QT_Pos)           /*!< 0x00000004 */\n#define JPEG_CONFR4_QT_1                (0x2UL << JPEG_CONFR4_QT_Pos)           /*!< 0x00000008 */\n#define JPEG_CONFR4_NB_Pos              (4U)\n#define JPEG_CONFR4_NB_Msk              (0xFUL << JPEG_CONFR4_NB_Pos)          /*!< 0x000000F0 */\n#define JPEG_CONFR4_NB                  JPEG_CONFR4_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */\n#define JPEG_CONFR4_NB_0                (0x1UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000010 */\n#define JPEG_CONFR4_NB_1                (0x2UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000020 */\n#define JPEG_CONFR4_NB_2                (0x4UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000040 */\n#define JPEG_CONFR4_NB_3                (0x8UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000080 */\n#define JPEG_CONFR4_VSF_Pos             (8U)\n#define JPEG_CONFR4_VSF_Msk             (0xFUL << JPEG_CONFR4_VSF_Pos)         /*!< 0x00000F00 */\n#define JPEG_CONFR4_VSF                 JPEG_CONFR4_VSF_Msk                    /*!<Vertical sampling factor for component 1 */\n#define JPEG_CONFR4_VSF_0               (0x1UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000100 */\n#define JPEG_CONFR4_VSF_1               (0x2UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000200 */\n#define JPEG_CONFR4_VSF_2               (0x4UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000400 */\n#define JPEG_CONFR4_VSF_3               (0x8UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000800 */\n#define JPEG_CONFR4_HSF_Pos             (12U)\n#define JPEG_CONFR4_HSF_Msk             (0xFUL << JPEG_CONFR4_HSF_Pos)         /*!< 0x0000F000 */\n#define JPEG_CONFR4_HSF                 JPEG_CONFR4_HSF_Msk                    /*!<Horizontal sampling factor for component 1 */\n#define JPEG_CONFR4_HSF_0               (0x1UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00001000 */\n#define JPEG_CONFR4_HSF_1               (0x2UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00002000 */\n#define JPEG_CONFR4_HSF_2               (0x4UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00004000 */\n#define JPEG_CONFR4_HSF_3               (0x8UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00008000 */\n\n/********************  Bit definition for CONFR5 register  ********************/\n#define JPEG_CONFR5_HD_Pos              (0U)\n#define JPEG_CONFR5_HD_Msk              (0x1UL << JPEG_CONFR5_HD_Pos)          /*!< 0x00000001 */\n#define JPEG_CONFR5_HD                  JPEG_CONFR5_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */\n#define JPEG_CONFR5_HA_Pos              (1U)\n#define JPEG_CONFR5_HA_Msk              (0x1UL << JPEG_CONFR5_HA_Pos)          /*!< 0x00000002 */\n#define JPEG_CONFR5_HA                  JPEG_CONFR5_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */\n#define JPEG_CONFR5_QT_Pos              (2U)\n#define JPEG_CONFR5_QT_Msk              (0x3UL << JPEG_CONFR5_QT_Pos)          /*!< 0x0000000C */\n#define JPEG_CONFR5_QT                  JPEG_CONFR5_QT_Msk                     /*!<Selects quantization table associated with a color component */\n#define JPEG_CONFR5_QT_0                (0x1UL << JPEG_CONFR5_QT_Pos)           /*!< 0x00000004 */\n#define JPEG_CONFR5_QT_1                (0x2UL << JPEG_CONFR5_QT_Pos)           /*!< 0x00000008 */\n#define JPEG_CONFR5_NB_Pos              (4U)\n#define JPEG_CONFR5_NB_Msk              (0xFUL << JPEG_CONFR5_NB_Pos)          /*!< 0x000000F0 */\n#define JPEG_CONFR5_NB                  JPEG_CONFR5_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */\n#define JPEG_CONFR5_NB_0                (0x1UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000010 */\n#define JPEG_CONFR5_NB_1                (0x2UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000020 */\n#define JPEG_CONFR5_NB_2                (0x4UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000040 */\n#define JPEG_CONFR5_NB_3                (0x8UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000080 */\n#define JPEG_CONFR5_VSF_Pos             (8U)\n#define JPEG_CONFR5_VSF_Msk             (0xFUL << JPEG_CONFR5_VSF_Pos)         /*!< 0x00000F00 */\n#define JPEG_CONFR5_VSF                 JPEG_CONFR5_VSF_Msk                    /*!<Vertical sampling factor for component 2 */\n#define JPEG_CONFR5_VSF_0               (0x1UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000100 */\n#define JPEG_CONFR5_VSF_1               (0x2UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000200 */\n#define JPEG_CONFR5_VSF_2               (0x4UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000400 */\n#define JPEG_CONFR5_VSF_3               (0x8UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000800 */\n#define JPEG_CONFR5_HSF_Pos             (12U)\n#define JPEG_CONFR5_HSF_Msk             (0xFUL << JPEG_CONFR5_HSF_Pos)         /*!< 0x0000F000 */\n#define JPEG_CONFR5_HSF                 JPEG_CONFR5_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */\n#define JPEG_CONFR5_HSF_0               (0x1UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00001000 */\n#define JPEG_CONFR5_HSF_1               (0x2UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00002000 */\n#define JPEG_CONFR5_HSF_2               (0x4UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00004000 */\n#define JPEG_CONFR5_HSF_3               (0x8UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00008000 */\n\n/********************  Bit definition for CONFR6 register  ********************/\n#define JPEG_CONFR6_HD_Pos              (0U)\n#define JPEG_CONFR6_HD_Msk              (0x1UL << JPEG_CONFR6_HD_Pos)          /*!< 0x00000001 */\n#define JPEG_CONFR6_HD                  JPEG_CONFR6_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */\n#define JPEG_CONFR6_HA_Pos              (1U)\n#define JPEG_CONFR6_HA_Msk              (0x1UL << JPEG_CONFR6_HA_Pos)          /*!< 0x00000002 */\n#define JPEG_CONFR6_HA                  JPEG_CONFR6_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */\n#define JPEG_CONFR6_QT_Pos              (2U)\n#define JPEG_CONFR6_QT_Msk              (0x3UL << JPEG_CONFR6_QT_Pos)          /*!< 0x0000000C */\n#define JPEG_CONFR6_QT                  JPEG_CONFR6_QT_Msk                     /*!<Selects quantization table associated with a color component */\n#define JPEG_CONFR6_QT_0                (0x1UL << JPEG_CONFR6_QT_Pos)           /*!< 0x00000004 */\n#define JPEG_CONFR6_QT_1                (0x2UL << JPEG_CONFR6_QT_Pos)           /*!< 0x00000008 */\n#define JPEG_CONFR6_NB_Pos              (4U)\n#define JPEG_CONFR6_NB_Msk              (0xFUL << JPEG_CONFR6_NB_Pos)          /*!< 0x000000F0 */\n#define JPEG_CONFR6_NB                  JPEG_CONFR6_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */\n#define JPEG_CONFR6_NB_0                (0x1UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000010 */\n#define JPEG_CONFR6_NB_1                (0x2UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000020 */\n#define JPEG_CONFR6_NB_2                (0x4UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000040 */\n#define JPEG_CONFR6_NB_3                (0x8UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000080 */\n#define JPEG_CONFR6_VSF_Pos             (8U)\n#define JPEG_CONFR6_VSF_Msk             (0xFUL << JPEG_CONFR6_VSF_Pos)         /*!< 0x00000F00 */\n#define JPEG_CONFR6_VSF                 JPEG_CONFR6_VSF_Msk                    /*!<Vertical sampling factor for component 2 */\n#define JPEG_CONFR6_VSF_0               (0x1UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000100 */\n#define JPEG_CONFR6_VSF_1               (0x2UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000200 */\n#define JPEG_CONFR6_VSF_2               (0x4UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000400 */\n#define JPEG_CONFR6_VSF_3               (0x8UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000800 */\n#define JPEG_CONFR6_HSF_Pos             (12U)\n#define JPEG_CONFR6_HSF_Msk             (0xFUL << JPEG_CONFR6_HSF_Pos)         /*!< 0x0000F000 */\n#define JPEG_CONFR6_HSF                 JPEG_CONFR6_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */\n#define JPEG_CONFR6_HSF_0               (0x1UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00001000 */\n#define JPEG_CONFR6_HSF_1               (0x2UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00002000 */\n#define JPEG_CONFR6_HSF_2               (0x4UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00004000 */\n#define JPEG_CONFR6_HSF_3               (0x8UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00008000 */\n\n/********************  Bit definition for CONFR7 register  ********************/\n#define JPEG_CONFR7_HD_Pos              (0U)\n#define JPEG_CONFR7_HD_Msk              (0x1UL << JPEG_CONFR7_HD_Pos)          /*!< 0x00000001 */\n#define JPEG_CONFR7_HD                  JPEG_CONFR7_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */\n#define JPEG_CONFR7_HA_Pos              (1U)\n#define JPEG_CONFR7_HA_Msk              (0x1UL << JPEG_CONFR7_HA_Pos)          /*!< 0x00000002 */\n#define JPEG_CONFR7_HA                  JPEG_CONFR7_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */\n#define JPEG_CONFR7_QT_Pos              (2U)\n#define JPEG_CONFR7_QT_Msk              (0x3UL << JPEG_CONFR7_QT_Pos)          /*!< 0x0000000C */\n#define JPEG_CONFR7_QT                  JPEG_CONFR7_QT_Msk                     /*!<Selects quantization table associated with a color component */\n#define JPEG_CONFR7_QT_0                (0x1UL << JPEG_CONFR7_QT_Pos)           /*!< 0x00000004 */\n#define JPEG_CONFR7_QT_1                (0x2UL << JPEG_CONFR7_QT_Pos)           /*!< 0x00000008 */\n#define JPEG_CONFR7_NB_Pos              (4U)\n#define JPEG_CONFR7_NB_Msk              (0xFUL << JPEG_CONFR7_NB_Pos)          /*!< 0x000000F0 */\n#define JPEG_CONFR7_NB                  JPEG_CONFR7_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */\n#define JPEG_CONFR7_NB_0                (0x1UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000010 */\n#define JPEG_CONFR7_NB_1                (0x2UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000020 */\n#define JPEG_CONFR7_NB_2                (0x4UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000040 */\n#define JPEG_CONFR7_NB_3                (0x8UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000080 */\n#define JPEG_CONFR7_VSF_Pos             (8U)\n#define JPEG_CONFR7_VSF_Msk             (0xFUL << JPEG_CONFR7_VSF_Pos)         /*!< 0x00000F00 */\n#define JPEG_CONFR7_VSF                 JPEG_CONFR7_VSF_Msk                    /*!<Vertical sampling factor for component 2 */\n#define JPEG_CONFR7_VSF_0               (0x1UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000100 */\n#define JPEG_CONFR7_VSF_1               (0x2UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000200 */\n#define JPEG_CONFR7_VSF_2               (0x4UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000400 */\n#define JPEG_CONFR7_VSF_3               (0x8UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000800 */\n#define JPEG_CONFR7_HSF_Pos             (12U)\n#define JPEG_CONFR7_HSF_Msk             (0xFUL << JPEG_CONFR7_HSF_Pos)         /*!< 0x0000F000 */\n#define JPEG_CONFR7_HSF                 JPEG_CONFR7_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */\n#define JPEG_CONFR7_HSF_0               (0x1UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00001000 */\n#define JPEG_CONFR7_HSF_1               (0x2UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00002000 */\n#define JPEG_CONFR7_HSF_2               (0x4UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00004000 */\n#define JPEG_CONFR7_HSF_3               (0x8UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00008000 */\n\n/********************  Bit definition for CR register  ********************/\n#define JPEG_CR_JCEN_Pos                (0U)\n#define JPEG_CR_JCEN_Msk                (0x1UL << JPEG_CR_JCEN_Pos)            /*!< 0x00000001 */\n#define JPEG_CR_JCEN                    JPEG_CR_JCEN_Msk                       /*!<Enable the JPEG Codec Core */\n#define JPEG_CR_IFTIE_Pos               (1U)\n#define JPEG_CR_IFTIE_Msk               (0x1UL << JPEG_CR_IFTIE_Pos)           /*!< 0x00000002 */\n#define JPEG_CR_IFTIE                   JPEG_CR_IFTIE_Msk                      /*!<Input FIFO Threshold Interrupt Enable */\n#define JPEG_CR_IFNFIE_Pos              (2U)\n#define JPEG_CR_IFNFIE_Msk              (0x1UL << JPEG_CR_IFNFIE_Pos)          /*!< 0x00000004 */\n#define JPEG_CR_IFNFIE                  JPEG_CR_IFNFIE_Msk                     /*!<Input FIFO Not Full Interrupt Enable */\n#define JPEG_CR_OFTIE_Pos               (3U)\n#define JPEG_CR_OFTIE_Msk               (0x1UL << JPEG_CR_OFTIE_Pos)           /*!< 0x00000008 */\n#define JPEG_CR_OFTIE                   JPEG_CR_OFTIE_Msk                      /*!<Output FIFO Threshold Interrupt Enable */\n#define JPEG_CR_OFNEIE_Pos              (4U)\n#define JPEG_CR_OFNEIE_Msk              (0x1UL << JPEG_CR_OFNEIE_Pos)          /*!< 0x00000010 */\n#define JPEG_CR_OFNEIE                  JPEG_CR_OFNEIE_Msk                     /*!<Output FIFO Not Empty Interrupt Enable */\n#define JPEG_CR_EOCIE_Pos               (5U)\n#define JPEG_CR_EOCIE_Msk               (0x1UL << JPEG_CR_EOCIE_Pos)           /*!< 0x00000020 */\n#define JPEG_CR_EOCIE                   JPEG_CR_EOCIE_Msk                      /*!<End of Conversion Interrupt Enable */\n#define JPEG_CR_HPDIE_Pos               (6U)\n#define JPEG_CR_HPDIE_Msk               (0x1UL << JPEG_CR_HPDIE_Pos)           /*!< 0x00000040 */\n#define JPEG_CR_HPDIE                   JPEG_CR_HPDIE_Msk                      /*!<Header Parsing Done Interrupt Enable */\n#define JPEG_CR_IFF_Pos                 (13U)\n#define JPEG_CR_IFF_Msk                 (0x1UL << JPEG_CR_IFF_Pos)             /*!< 0x00002000 */\n#define JPEG_CR_IFF                     JPEG_CR_IFF_Msk                        /*!<Flush the input FIFO */\n#define JPEG_CR_OFF_Pos                 (14U)\n#define JPEG_CR_OFF_Msk                 (0x1UL << JPEG_CR_OFF_Pos)             /*!< 0x00004000 */\n#define JPEG_CR_OFF                     JPEG_CR_OFF_Msk                        /*!<Flush the output FIFO */\n\n/********************  Bit definition for SR register  ********************/\n#define JPEG_SR_IFTF_Pos                (1U)\n#define JPEG_SR_IFTF_Msk                (0x1UL << JPEG_SR_IFTF_Pos)            /*!< 0x00000002 */\n#define JPEG_SR_IFTF                    JPEG_SR_IFTF_Msk                       /*!<Input FIFO is not full and is bellow its threshold flag */\n#define JPEG_SR_IFNFF_Pos               (2U)\n#define JPEG_SR_IFNFF_Msk               (0x1UL << JPEG_SR_IFNFF_Pos)           /*!< 0x00000004 */\n#define JPEG_SR_IFNFF                   JPEG_SR_IFNFF_Msk                      /*!<Input FIFO Not Full Flag, a data can be written */\n#define JPEG_SR_OFTF_Pos                (3U)\n#define JPEG_SR_OFTF_Msk                (0x1UL << JPEG_SR_OFTF_Pos)            /*!< 0x00000008 */\n#define JPEG_SR_OFTF                    JPEG_SR_OFTF_Msk                       /*!<Output FIFO is not empty and has reach its threshold */\n#define JPEG_SR_OFNEF_Pos               (4U)\n#define JPEG_SR_OFNEF_Msk               (0x1UL << JPEG_SR_OFNEF_Pos)           /*!< 0x00000010 */\n#define JPEG_SR_OFNEF                   JPEG_SR_OFNEF_Msk                      /*!<Output FIFO is not empty, a data is available */\n#define JPEG_SR_EOCF_Pos                (5U)\n#define JPEG_SR_EOCF_Msk                (0x1UL << JPEG_SR_EOCF_Pos)            /*!< 0x00000020 */\n#define JPEG_SR_EOCF                    JPEG_SR_EOCF_Msk                       /*!<JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO */\n#define JPEG_SR_HPDF_Pos                (6U)\n#define JPEG_SR_HPDF_Msk                (0x1UL << JPEG_SR_HPDF_Pos)            /*!< 0x00000040 */\n#define JPEG_SR_HPDF                    JPEG_SR_HPDF_Msk                       /*!<JPEG Codec has finished the parsing of the headers and the internal registers have been updated */\n#define JPEG_SR_COF_Pos                 (7U)\n#define JPEG_SR_COF_Msk                 (0x1UL << JPEG_SR_COF_Pos)             /*!< 0x00000080 */\n#define JPEG_SR_COF                     JPEG_SR_COF_Msk                        /*!<JPEG Codec operation on going flag */\n\n/********************  Bit definition for CFR register  ********************/\n#define JPEG_CFR_CEOCF_Pos              (4U)\n#define JPEG_CFR_CEOCF_Msk              (0x1UL << JPEG_CFR_CEOCF_Pos)          /*!< 0x00000010 */\n#define JPEG_CFR_CEOCF                  JPEG_CFR_CEOCF_Msk                     /*!<Clear End of Conversion Flag */\n#define JPEG_CFR_CHPDF_Pos              (5U)\n#define JPEG_CFR_CHPDF_Msk              (0x1UL << JPEG_CFR_CHPDF_Pos)          /*!< 0x00000020 */\n#define JPEG_CFR_CHPDF                  JPEG_CFR_CHPDF_Msk                     /*!<Clear Header Parsing Done Flag */\n\n/********************  Bit definition for DIR register  ********************/\n#define JPEG_DIR_DATAIN_Pos             (0U)\n#define JPEG_DIR_DATAIN_Msk             (0xFFFFFFFFUL << JPEG_DIR_DATAIN_Pos)  /*!< 0xFFFFFFFF */\n#define JPEG_DIR_DATAIN                 JPEG_DIR_DATAIN_Msk                    /*!<Data Input FIFO */\n\n/********************  Bit definition for DOR register  ********************/\n#define JPEG_DOR_DATAOUT_Pos            (0U)\n#define JPEG_DOR_DATAOUT_Msk            (0xFFFFFFFFUL << JPEG_DOR_DATAOUT_Pos) /*!< 0xFFFFFFFF */\n#define JPEG_DOR_DATAOUT                JPEG_DOR_DATAOUT_Msk                   /*!<Data Output FIFO */\n\n/******************************************************************************/\n/*                                                                            */\n/*                      LCD-TFT Display Controller (LTDC)                     */\n/*                                                                            */\n/******************************************************************************/\n\n/********************  Bit definition for LTDC_SSCR register  *****************/\n\n#define LTDC_SSCR_VSH_Pos            (0U)\n#define LTDC_SSCR_VSH_Msk            (0x7FFUL << LTDC_SSCR_VSH_Pos)            /*!< 0x000007FF */\n#define LTDC_SSCR_VSH                LTDC_SSCR_VSH_Msk                         /*!< Vertical Synchronization Height  */\n#define LTDC_SSCR_HSW_Pos            (16U)\n#define LTDC_SSCR_HSW_Msk            (0xFFFUL << LTDC_SSCR_HSW_Pos)            /*!< 0x0FFF0000 */\n#define LTDC_SSCR_HSW                LTDC_SSCR_HSW_Msk                         /*!< Horizontal Synchronization Width */\n\n/********************  Bit definition for LTDC_BPCR register  *****************/\n\n#define LTDC_BPCR_AVBP_Pos           (0U)\n#define LTDC_BPCR_AVBP_Msk           (0x7FFUL << LTDC_BPCR_AVBP_Pos)           /*!< 0x000007FF */\n#define LTDC_BPCR_AVBP               LTDC_BPCR_AVBP_Msk                        /*!< Accumulated Vertical Back Porch   */\n#define LTDC_BPCR_AHBP_Pos           (16U)\n#define LTDC_BPCR_AHBP_Msk           (0xFFFUL << LTDC_BPCR_AHBP_Pos)           /*!< 0x0FFF0000 */\n#define LTDC_BPCR_AHBP               LTDC_BPCR_AHBP_Msk                        /*!< Accumulated Horizontal Back Porch */\n\n/********************  Bit definition for LTDC_AWCR register  *****************/\n\n#define LTDC_AWCR_AAH_Pos            (0U)\n#define LTDC_AWCR_AAH_Msk            (0x7FFUL << LTDC_AWCR_AAH_Pos)            /*!< 0x000007FF */\n#define LTDC_AWCR_AAH                LTDC_AWCR_AAH_Msk                         /*!< Accumulated Active height */\n#define LTDC_AWCR_AAW_Pos            (16U)\n#define LTDC_AWCR_AAW_Msk            (0xFFFUL << LTDC_AWCR_AAW_Pos)            /*!< 0x0FFF0000 */\n#define LTDC_AWCR_AAW                LTDC_AWCR_AAW_Msk                         /*!< Accumulated Active Width */\n\n/********************  Bit definition for LTDC_TWCR register  *****************/\n\n#define LTDC_TWCR_TOTALH_Pos         (0U)\n#define LTDC_TWCR_TOTALH_Msk         (0x7FFUL << LTDC_TWCR_TOTALH_Pos)         /*!< 0x000007FF */\n#define LTDC_TWCR_TOTALH             LTDC_TWCR_TOTALH_Msk                      /*!< Total height */\n#define LTDC_TWCR_TOTALW_Pos         (16U)\n#define LTDC_TWCR_TOTALW_Msk         (0xFFFUL << LTDC_TWCR_TOTALW_Pos)         /*!< 0x0FFF0000 */\n#define LTDC_TWCR_TOTALW             LTDC_TWCR_TOTALW_Msk                      /*!< Total Width */\n\n/********************  Bit definition for LTDC_GCR register  ******************/\n\n#define LTDC_GCR_LTDCEN_Pos          (0U)\n#define LTDC_GCR_LTDCEN_Msk          (0x1UL << LTDC_GCR_LTDCEN_Pos)            /*!< 0x00000001 */\n#define LTDC_GCR_LTDCEN              LTDC_GCR_LTDCEN_Msk                       /*!< LCD-TFT controller enable bit       */\n#define LTDC_GCR_DBW_Pos             (4U)\n#define LTDC_GCR_DBW_Msk             (0x7UL << LTDC_GCR_DBW_Pos)               /*!< 0x00000070 */\n#define LTDC_GCR_DBW                 LTDC_GCR_DBW_Msk                          /*!< Dither Blue Width                   */\n#define LTDC_GCR_DGW_Pos             (8U)\n#define LTDC_GCR_DGW_Msk             (0x7UL << LTDC_GCR_DGW_Pos)               /*!< 0x00000700 */\n#define LTDC_GCR_DGW                 LTDC_GCR_DGW_Msk                          /*!< Dither Green Width                  */\n#define LTDC_GCR_DRW_Pos             (12U)\n#define LTDC_GCR_DRW_Msk             (0x7UL << LTDC_GCR_DRW_Pos)               /*!< 0x00007000 */\n#define LTDC_GCR_DRW                 LTDC_GCR_DRW_Msk                          /*!< Dither Red Width                    */\n#define LTDC_GCR_DEN_Pos             (16U)\n#define LTDC_GCR_DEN_Msk             (0x1UL << LTDC_GCR_DEN_Pos)               /*!< 0x00010000 */\n#define LTDC_GCR_DEN                 LTDC_GCR_DEN_Msk                          /*!< Dither Enable                       */\n#define LTDC_GCR_PCPOL_Pos           (28U)\n#define LTDC_GCR_PCPOL_Msk           (0x1UL << LTDC_GCR_PCPOL_Pos)             /*!< 0x10000000 */\n#define LTDC_GCR_PCPOL               LTDC_GCR_PCPOL_Msk                        /*!< Pixel Clock Polarity                */\n#define LTDC_GCR_DEPOL_Pos           (29U)\n#define LTDC_GCR_DEPOL_Msk           (0x1UL << LTDC_GCR_DEPOL_Pos)             /*!< 0x20000000 */\n#define LTDC_GCR_DEPOL               LTDC_GCR_DEPOL_Msk                        /*!< Data Enable Polarity                */\n#define LTDC_GCR_VSPOL_Pos           (30U)\n#define LTDC_GCR_VSPOL_Msk           (0x1UL << LTDC_GCR_VSPOL_Pos)             /*!< 0x40000000 */\n#define LTDC_GCR_VSPOL               LTDC_GCR_VSPOL_Msk                        /*!< Vertical Synchronization Polarity   */\n#define LTDC_GCR_HSPOL_Pos           (31U)\n#define LTDC_GCR_HSPOL_Msk           (0x1UL << LTDC_GCR_HSPOL_Pos)             /*!< 0x80000000 */\n#define LTDC_GCR_HSPOL               LTDC_GCR_HSPOL_Msk                        /*!< Horizontal Synchronization Polarity */\n\n\n/********************  Bit definition for LTDC_SRCR register  *****************/\n\n#define LTDC_SRCR_IMR_Pos            (0U)\n#define LTDC_SRCR_IMR_Msk            (0x1UL << LTDC_SRCR_IMR_Pos)              /*!< 0x00000001 */\n#define LTDC_SRCR_IMR                LTDC_SRCR_IMR_Msk                         /*!< Immediate Reload         */\n#define LTDC_SRCR_VBR_Pos            (1U)\n#define LTDC_SRCR_VBR_Msk            (0x1UL << LTDC_SRCR_VBR_Pos)              /*!< 0x00000002 */\n#define LTDC_SRCR_VBR                LTDC_SRCR_VBR_Msk                         /*!< Vertical Blanking Reload */\n\n/********************  Bit definition for LTDC_BCCR register  *****************/\n\n#define LTDC_BCCR_BCBLUE_Pos         (0U)\n#define LTDC_BCCR_BCBLUE_Msk         (0xFFUL << LTDC_BCCR_BCBLUE_Pos)          /*!< 0x000000FF */\n#define LTDC_BCCR_BCBLUE             LTDC_BCCR_BCBLUE_Msk                      /*!< Background Blue value  */\n#define LTDC_BCCR_BCGREEN_Pos        (8U)\n#define LTDC_BCCR_BCGREEN_Msk        (0xFFUL << LTDC_BCCR_BCGREEN_Pos)         /*!< 0x0000FF00 */\n#define LTDC_BCCR_BCGREEN            LTDC_BCCR_BCGREEN_Msk                     /*!< Background Green value */\n#define LTDC_BCCR_BCRED_Pos          (16U)\n#define LTDC_BCCR_BCRED_Msk          (0xFFUL << LTDC_BCCR_BCRED_Pos)           /*!< 0x00FF0000 */\n#define LTDC_BCCR_BCRED              LTDC_BCCR_BCRED_Msk                       /*!< Background Red value   */\n\n/********************  Bit definition for LTDC_IER register  ******************/\n\n#define LTDC_IER_LIE_Pos             (0U)\n#define LTDC_IER_LIE_Msk             (0x1UL << LTDC_IER_LIE_Pos)               /*!< 0x00000001 */\n#define LTDC_IER_LIE                 LTDC_IER_LIE_Msk                          /*!< Line Interrupt Enable            */\n#define LTDC_IER_FUIE_Pos            (1U)\n#define LTDC_IER_FUIE_Msk            (0x1UL << LTDC_IER_FUIE_Pos)              /*!< 0x00000002 */\n#define LTDC_IER_FUIE                LTDC_IER_FUIE_Msk                         /*!< FIFO Underrun Interrupt Enable   */\n#define LTDC_IER_TERRIE_Pos          (2U)\n#define LTDC_IER_TERRIE_Msk          (0x1UL << LTDC_IER_TERRIE_Pos)            /*!< 0x00000004 */\n#define LTDC_IER_TERRIE              LTDC_IER_TERRIE_Msk                       /*!< Transfer Error Interrupt Enable  */\n#define LTDC_IER_RRIE_Pos            (3U)\n#define LTDC_IER_RRIE_Msk            (0x1UL << LTDC_IER_RRIE_Pos)              /*!< 0x00000008 */\n#define LTDC_IER_RRIE                LTDC_IER_RRIE_Msk                         /*!< Register Reload interrupt enable */\n\n/********************  Bit definition for LTDC_ISR register  ******************/\n\n#define LTDC_ISR_LIF_Pos             (0U)\n#define LTDC_ISR_LIF_Msk             (0x1UL << LTDC_ISR_LIF_Pos)               /*!< 0x00000001 */\n#define LTDC_ISR_LIF                 LTDC_ISR_LIF_Msk                          /*!< Line Interrupt Flag */\n#define LTDC_ISR_FUIF_Pos            (1U)\n#define LTDC_ISR_FUIF_Msk            (0x1UL << LTDC_ISR_FUIF_Pos)              /*!< 0x00000002 */\n#define LTDC_ISR_FUIF                LTDC_ISR_FUIF_Msk                         /*!< FIFO Underrun Interrupt Flag */\n#define LTDC_ISR_TERRIF_Pos          (2U)\n#define LTDC_ISR_TERRIF_Msk          (0x1UL << LTDC_ISR_TERRIF_Pos)            /*!< 0x00000004 */\n#define LTDC_ISR_TERRIF              LTDC_ISR_TERRIF_Msk                       /*!< Transfer Error Interrupt Flag */\n#define LTDC_ISR_RRIF_Pos            (3U)\n#define LTDC_ISR_RRIF_Msk            (0x1UL << LTDC_ISR_RRIF_Pos)              /*!< 0x00000008 */\n#define LTDC_ISR_RRIF                LTDC_ISR_RRIF_Msk                         /*!< Register Reload interrupt Flag */\n\n/********************  Bit definition for LTDC_ICR register  ******************/\n\n#define LTDC_ICR_CLIF_Pos            (0U)\n#define LTDC_ICR_CLIF_Msk            (0x1UL << LTDC_ICR_CLIF_Pos)              /*!< 0x00000001 */\n#define LTDC_ICR_CLIF                LTDC_ICR_CLIF_Msk                         /*!< Clears the Line Interrupt Flag */\n#define LTDC_ICR_CFUIF_Pos           (1U)\n#define LTDC_ICR_CFUIF_Msk           (0x1UL << LTDC_ICR_CFUIF_Pos)             /*!< 0x00000002 */\n#define LTDC_ICR_CFUIF               LTDC_ICR_CFUIF_Msk                        /*!< Clears the FIFO Underrun Interrupt Flag */\n#define LTDC_ICR_CTERRIF_Pos         (2U)\n#define LTDC_ICR_CTERRIF_Msk         (0x1UL << LTDC_ICR_CTERRIF_Pos)           /*!< 0x00000004 */\n#define LTDC_ICR_CTERRIF             LTDC_ICR_CTERRIF_Msk                      /*!< Clears the Transfer Error Interrupt Flag */\n#define LTDC_ICR_CRRIF_Pos           (3U)\n#define LTDC_ICR_CRRIF_Msk           (0x1UL << LTDC_ICR_CRRIF_Pos)             /*!< 0x00000008 */\n#define LTDC_ICR_CRRIF               LTDC_ICR_CRRIF_Msk                        /*!< Clears Register Reload interrupt Flag */\n\n/********************  Bit definition for LTDC_LIPCR register  ****************/\n\n#define LTDC_LIPCR_LIPOS_Pos         (0U)\n#define LTDC_LIPCR_LIPOS_Msk         (0x7FFUL << LTDC_LIPCR_LIPOS_Pos)         /*!< 0x000007FF */\n#define LTDC_LIPCR_LIPOS             LTDC_LIPCR_LIPOS_Msk                      /*!< Line Interrupt Position */\n\n/********************  Bit definition for LTDC_CPSR register  *****************/\n\n#define LTDC_CPSR_CYPOS_Pos          (0U)\n#define LTDC_CPSR_CYPOS_Msk          (0xFFFFUL << LTDC_CPSR_CYPOS_Pos)         /*!< 0x0000FFFF */\n#define LTDC_CPSR_CYPOS              LTDC_CPSR_CYPOS_Msk                       /*!< Current Y Position */\n#define LTDC_CPSR_CXPOS_Pos          (16U)\n#define LTDC_CPSR_CXPOS_Msk          (0xFFFFUL << LTDC_CPSR_CXPOS_Pos)         /*!< 0xFFFF0000 */\n#define LTDC_CPSR_CXPOS              LTDC_CPSR_CXPOS_Msk                       /*!< Current X Position */\n\n/********************  Bit definition for LTDC_CDSR register  *****************/\n\n#define LTDC_CDSR_VDES_Pos           (0U)\n#define LTDC_CDSR_VDES_Msk           (0x1UL << LTDC_CDSR_VDES_Pos)             /*!< 0x00000001 */\n#define LTDC_CDSR_VDES               LTDC_CDSR_VDES_Msk                        /*!< Vertical Data Enable Status       */\n#define LTDC_CDSR_HDES_Pos           (1U)\n#define LTDC_CDSR_HDES_Msk           (0x1UL << LTDC_CDSR_HDES_Pos)             /*!< 0x00000002 */\n#define LTDC_CDSR_HDES               LTDC_CDSR_HDES_Msk                        /*!< Horizontal Data Enable Status     */\n#define LTDC_CDSR_VSYNCS_Pos         (2U)\n#define LTDC_CDSR_VSYNCS_Msk         (0x1UL << LTDC_CDSR_VSYNCS_Pos)           /*!< 0x00000004 */\n#define LTDC_CDSR_VSYNCS             LTDC_CDSR_VSYNCS_Msk                      /*!< Vertical Synchronization Status   */\n#define LTDC_CDSR_HSYNCS_Pos         (3U)\n#define LTDC_CDSR_HSYNCS_Msk         (0x1UL << LTDC_CDSR_HSYNCS_Pos)           /*!< 0x00000008 */\n#define LTDC_CDSR_HSYNCS             LTDC_CDSR_HSYNCS_Msk                      /*!< Horizontal Synchronization Status */\n\n/********************  Bit definition for LTDC_LxCR register  *****************/\n\n#define LTDC_LxCR_LEN_Pos            (0U)\n#define LTDC_LxCR_LEN_Msk            (0x1UL << LTDC_LxCR_LEN_Pos)              /*!< 0x00000001 */\n#define LTDC_LxCR_LEN                LTDC_LxCR_LEN_Msk                         /*!< Layer Enable              */\n#define LTDC_LxCR_COLKEN_Pos         (1U)\n#define LTDC_LxCR_COLKEN_Msk         (0x1UL << LTDC_LxCR_COLKEN_Pos)           /*!< 0x00000002 */\n#define LTDC_LxCR_COLKEN             LTDC_LxCR_COLKEN_Msk                      /*!< Color Keying Enable       */\n#define LTDC_LxCR_CLUTEN_Pos         (4U)\n#define LTDC_LxCR_CLUTEN_Msk         (0x1UL << LTDC_LxCR_CLUTEN_Pos)           /*!< 0x00000010 */\n#define LTDC_LxCR_CLUTEN             LTDC_LxCR_CLUTEN_Msk                      /*!< Color Lockup Table Enable */\n\n/********************  Bit definition for LTDC_LxWHPCR register  **************/\n\n#define LTDC_LxWHPCR_WHSTPOS_Pos     (0U)\n#define LTDC_LxWHPCR_WHSTPOS_Msk     (0xFFFUL << LTDC_LxWHPCR_WHSTPOS_Pos)     /*!< 0x00000FFF */\n#define LTDC_LxWHPCR_WHSTPOS         LTDC_LxWHPCR_WHSTPOS_Msk                  /*!< Window Horizontal Start Position */\n#define LTDC_LxWHPCR_WHSPPOS_Pos     (16U)\n#define LTDC_LxWHPCR_WHSPPOS_Msk     (0xFFFFUL << LTDC_LxWHPCR_WHSPPOS_Pos)    /*!< 0xFFFF0000 */\n#define LTDC_LxWHPCR_WHSPPOS         LTDC_LxWHPCR_WHSPPOS_Msk                  /*!< Window Horizontal Stop Position  */\n\n/********************  Bit definition for LTDC_LxWVPCR register  **************/\n\n#define LTDC_LxWVPCR_WVSTPOS_Pos     (0U)\n#define LTDC_LxWVPCR_WVSTPOS_Msk     (0xFFFUL << LTDC_LxWVPCR_WVSTPOS_Pos)     /*!< 0x00000FFF */\n#define LTDC_LxWVPCR_WVSTPOS         LTDC_LxWVPCR_WVSTPOS_Msk                  /*!< Window Vertical Start Position */\n#define LTDC_LxWVPCR_WVSPPOS_Pos     (16U)\n#define LTDC_LxWVPCR_WVSPPOS_Msk     (0xFFFFUL << LTDC_LxWVPCR_WVSPPOS_Pos)    /*!< 0xFFFF0000 */\n#define LTDC_LxWVPCR_WVSPPOS         LTDC_LxWVPCR_WVSPPOS_Msk                  /*!< Window Vertical Stop Position  */\n\n/********************  Bit definition for LTDC_LxCKCR register  ***************/\n\n#define LTDC_LxCKCR_CKBLUE_Pos       (0U)\n#define LTDC_LxCKCR_CKBLUE_Msk       (0xFFUL << LTDC_LxCKCR_CKBLUE_Pos)        /*!< 0x000000FF */\n#define LTDC_LxCKCR_CKBLUE           LTDC_LxCKCR_CKBLUE_Msk                    /*!< Color Key Blue value  */\n#define LTDC_LxCKCR_CKGREEN_Pos      (8U)\n#define LTDC_LxCKCR_CKGREEN_Msk      (0xFFUL << LTDC_LxCKCR_CKGREEN_Pos)       /*!< 0x0000FF00 */\n#define LTDC_LxCKCR_CKGREEN          LTDC_LxCKCR_CKGREEN_Msk                   /*!< Color Key Green value */\n#define LTDC_LxCKCR_CKRED_Pos        (16U)\n#define LTDC_LxCKCR_CKRED_Msk        (0xFFUL << LTDC_LxCKCR_CKRED_Pos)         /*!< 0x00FF0000 */\n#define LTDC_LxCKCR_CKRED            LTDC_LxCKCR_CKRED_Msk                     /*!< Color Key Red value   */\n\n/********************  Bit definition for LTDC_LxPFCR register  ***************/\n\n#define LTDC_LxPFCR_PF_Pos           (0U)\n#define LTDC_LxPFCR_PF_Msk           (0x7UL << LTDC_LxPFCR_PF_Pos)             /*!< 0x00000007 */\n#define LTDC_LxPFCR_PF               LTDC_LxPFCR_PF_Msk                        /*!< Pixel Format */\n\n/********************  Bit definition for LTDC_LxCACR register  ***************/\n\n#define LTDC_LxCACR_CONSTA_Pos       (0U)\n#define LTDC_LxCACR_CONSTA_Msk       (0xFFUL << LTDC_LxCACR_CONSTA_Pos)        /*!< 0x000000FF */\n#define LTDC_LxCACR_CONSTA           LTDC_LxCACR_CONSTA_Msk                    /*!< Constant Alpha */\n\n/********************  Bit definition for LTDC_LxDCCR register  ***************/\n\n#define LTDC_LxDCCR_DCBLUE_Pos       (0U)\n#define LTDC_LxDCCR_DCBLUE_Msk       (0xFFUL << LTDC_LxDCCR_DCBLUE_Pos)        /*!< 0x000000FF */\n#define LTDC_LxDCCR_DCBLUE           LTDC_LxDCCR_DCBLUE_Msk                    /*!< Default Color Blue  */\n#define LTDC_LxDCCR_DCGREEN_Pos      (8U)\n#define LTDC_LxDCCR_DCGREEN_Msk      (0xFFUL << LTDC_LxDCCR_DCGREEN_Pos)       /*!< 0x0000FF00 */\n#define LTDC_LxDCCR_DCGREEN          LTDC_LxDCCR_DCGREEN_Msk                   /*!< Default Color Green */\n#define LTDC_LxDCCR_DCRED_Pos        (16U)\n#define LTDC_LxDCCR_DCRED_Msk        (0xFFUL << LTDC_LxDCCR_DCRED_Pos)         /*!< 0x00FF0000 */\n#define LTDC_LxDCCR_DCRED            LTDC_LxDCCR_DCRED_Msk                     /*!< Default Color Red   */\n#define LTDC_LxDCCR_DCALPHA_Pos      (24U)\n#define LTDC_LxDCCR_DCALPHA_Msk      (0xFFUL << LTDC_LxDCCR_DCALPHA_Pos)       /*!< 0xFF000000 */\n#define LTDC_LxDCCR_DCALPHA          LTDC_LxDCCR_DCALPHA_Msk                   /*!< Default Color Alpha */\n\n/********************  Bit definition for LTDC_LxBFCR register  ***************/\n\n#define LTDC_LxBFCR_BF2_Pos          (0U)\n#define LTDC_LxBFCR_BF2_Msk          (0x7UL << LTDC_LxBFCR_BF2_Pos)            /*!< 0x00000007 */\n#define LTDC_LxBFCR_BF2              LTDC_LxBFCR_BF2_Msk                       /*!< Blending Factor 2 */\n#define LTDC_LxBFCR_BF1_Pos          (8U)\n#define LTDC_LxBFCR_BF1_Msk          (0x7UL << LTDC_LxBFCR_BF1_Pos)            /*!< 0x00000700 */\n#define LTDC_LxBFCR_BF1              LTDC_LxBFCR_BF1_Msk                       /*!< Blending Factor 1 */\n\n/********************  Bit definition for LTDC_LxCFBAR register  **************/\n\n#define LTDC_LxCFBAR_CFBADD_Pos      (0U)\n#define LTDC_LxCFBAR_CFBADD_Msk      (0xFFFFFFFFUL << LTDC_LxCFBAR_CFBADD_Pos) /*!< 0xFFFFFFFF */\n#define LTDC_LxCFBAR_CFBADD          LTDC_LxCFBAR_CFBADD_Msk                   /*!< Color Frame Buffer Start Address */\n\n/********************  Bit definition for LTDC_LxCFBLR register  **************/\n\n#define LTDC_LxCFBLR_CFBLL_Pos       (0U)\n#define LTDC_LxCFBLR_CFBLL_Msk       (0x1FFFUL << LTDC_LxCFBLR_CFBLL_Pos)      /*!< 0x00001FFF */\n#define LTDC_LxCFBLR_CFBLL           LTDC_LxCFBLR_CFBLL_Msk                    /*!< Color Frame Buffer Line Length    */\n#define LTDC_LxCFBLR_CFBP_Pos        (16U)\n#define LTDC_LxCFBLR_CFBP_Msk        (0x1FFFUL << LTDC_LxCFBLR_CFBP_Pos)       /*!< 0x1FFF0000 */\n#define LTDC_LxCFBLR_CFBP            LTDC_LxCFBLR_CFBP_Msk                     /*!< Color Frame Buffer Pitch in bytes */\n\n/********************  Bit definition for LTDC_LxCFBLNR register  *************/\n\n#define LTDC_LxCFBLNR_CFBLNBR_Pos    (0U)\n#define LTDC_LxCFBLNR_CFBLNBR_Msk    (0x7FFUL << LTDC_LxCFBLNR_CFBLNBR_Pos)    /*!< 0x000007FF */\n#define LTDC_LxCFBLNR_CFBLNBR        LTDC_LxCFBLNR_CFBLNBR_Msk                 /*!< Frame Buffer Line Number */\n\n/********************  Bit definition for LTDC_LxCLUTWR register  *************/\n\n#define LTDC_LxCLUTWR_BLUE_Pos       (0U)\n#define LTDC_LxCLUTWR_BLUE_Msk       (0xFFUL << LTDC_LxCLUTWR_BLUE_Pos)        /*!< 0x000000FF */\n#define LTDC_LxCLUTWR_BLUE           LTDC_LxCLUTWR_BLUE_Msk                    /*!< Blue value   */\n#define LTDC_LxCLUTWR_GREEN_Pos      (8U)\n#define LTDC_LxCLUTWR_GREEN_Msk      (0xFFUL << LTDC_LxCLUTWR_GREEN_Pos)       /*!< 0x0000FF00 */\n#define LTDC_LxCLUTWR_GREEN          LTDC_LxCLUTWR_GREEN_Msk                   /*!< Green value  */\n#define LTDC_LxCLUTWR_RED_Pos        (16U)\n#define LTDC_LxCLUTWR_RED_Msk        (0xFFUL << LTDC_LxCLUTWR_RED_Pos)         /*!< 0x00FF0000 */\n#define LTDC_LxCLUTWR_RED            LTDC_LxCLUTWR_RED_Msk                     /*!< Red value    */\n#define LTDC_LxCLUTWR_CLUTADD_Pos    (24U)\n#define LTDC_LxCLUTWR_CLUTADD_Msk    (0xFFUL << LTDC_LxCLUTWR_CLUTADD_Pos)     /*!< 0xFF000000 */\n#define LTDC_LxCLUTWR_CLUTADD        LTDC_LxCLUTWR_CLUTADD_Msk                 /*!< CLUT address */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                     MDMA                                   */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for MDMA_GISR0 register  ****************/\n#define MDMA_GISR0_GIF0_Pos       (0U)\n#define MDMA_GISR0_GIF0_Msk       (0x1UL << MDMA_GISR0_GIF0_Pos)               /*!< 0x00000001 */\n#define MDMA_GISR0_GIF0           MDMA_GISR0_GIF0_Msk                          /*!< Channel 0 global interrupt flag */\n#define MDMA_GISR0_GIF1_Pos       (1U)\n#define MDMA_GISR0_GIF1_Msk       (0x1UL << MDMA_GISR0_GIF1_Pos)               /*!< 0x00000002 */\n#define MDMA_GISR0_GIF1           MDMA_GISR0_GIF1_Msk                          /*!< Channel 1 global interrupt flag */\n#define MDMA_GISR0_GIF2_Pos       (2U)\n#define MDMA_GISR0_GIF2_Msk       (0x1UL << MDMA_GISR0_GIF2_Pos)               /*!< 0x00000004 */\n#define MDMA_GISR0_GIF2           MDMA_GISR0_GIF2_Msk                          /*!< Channel 2 global interrupt flag */\n#define MDMA_GISR0_GIF3_Pos       (3U)\n#define MDMA_GISR0_GIF3_Msk       (0x1UL << MDMA_GISR0_GIF3_Pos)               /*!< 0x00000008 */\n#define MDMA_GISR0_GIF3           MDMA_GISR0_GIF3_Msk                          /*!< Channel 3 global interrupt flag */\n#define MDMA_GISR0_GIF4_Pos       (4U)\n#define MDMA_GISR0_GIF4_Msk       (0x1UL << MDMA_GISR0_GIF4_Pos)               /*!< 0x00000010 */\n#define MDMA_GISR0_GIF4           MDMA_GISR0_GIF4_Msk                          /*!< Channel 4 global interrupt flag */\n#define MDMA_GISR0_GIF5_Pos       (5U)\n#define MDMA_GISR0_GIF5_Msk       (0x1UL << MDMA_GISR0_GIF5_Pos)               /*!< 0x00000020 */\n#define MDMA_GISR0_GIF5           MDMA_GISR0_GIF5_Msk                          /*!< Channel 5 global interrupt flag */\n#define MDMA_GISR0_GIF6_Pos       (6U)\n#define MDMA_GISR0_GIF6_Msk       (0x1UL << MDMA_GISR0_GIF6_Pos)               /*!< 0x00000040 */\n#define MDMA_GISR0_GIF6           MDMA_GISR0_GIF6_Msk                          /*!< Channel 6 global interrupt flag */\n#define MDMA_GISR0_GIF7_Pos       (7U)\n#define MDMA_GISR0_GIF7_Msk       (0x1UL << MDMA_GISR0_GIF7_Pos)               /*!< 0x00000080 */\n#define MDMA_GISR0_GIF7           MDMA_GISR0_GIF7_Msk                          /*!< Channel 7 global interrupt flag */\n#define MDMA_GISR0_GIF8_Pos       (8U)\n#define MDMA_GISR0_GIF8_Msk       (0x1UL << MDMA_GISR0_GIF8_Pos)               /*!< 0x00000100 */\n#define MDMA_GISR0_GIF8           MDMA_GISR0_GIF8_Msk                          /*!< Channel 8 global interrupt flag */\n#define MDMA_GISR0_GIF9_Pos       (9U)\n#define MDMA_GISR0_GIF9_Msk       (0x1UL << MDMA_GISR0_GIF9_Pos)               /*!< 0x00000200 */\n#define MDMA_GISR0_GIF9           MDMA_GISR0_GIF9_Msk                          /*!< Channel 9 global interrupt flag */\n#define MDMA_GISR0_GIF10_Pos      (10U)\n#define MDMA_GISR0_GIF10_Msk      (0x1UL << MDMA_GISR0_GIF10_Pos)              /*!< 0x00000400 */\n#define MDMA_GISR0_GIF10          MDMA_GISR0_GIF10_Msk                         /*!< Channel 10 global interrupt flag */\n#define MDMA_GISR0_GIF11_Pos      (11U)\n#define MDMA_GISR0_GIF11_Msk      (0x1UL << MDMA_GISR0_GIF11_Pos)              /*!< 0x00000800 */\n#define MDMA_GISR0_GIF11          MDMA_GISR0_GIF11_Msk                         /*!< Channel 11 global interrupt flag */\n#define MDMA_GISR0_GIF12_Pos      (12U)\n#define MDMA_GISR0_GIF12_Msk      (0x1UL << MDMA_GISR0_GIF12_Pos)              /*!< 0x00001000 */\n#define MDMA_GISR0_GIF12          MDMA_GISR0_GIF12_Msk                         /*!< Channel 12 global interrupt flag */\n#define MDMA_GISR0_GIF13_Pos      (13U)\n#define MDMA_GISR0_GIF13_Msk      (0x1UL << MDMA_GISR0_GIF13_Pos)              /*!< 0x00002000 */\n#define MDMA_GISR0_GIF13          MDMA_GISR0_GIF13_Msk                         /*!< Channel 13 global interrupt flag */\n#define MDMA_GISR0_GIF14_Pos      (14U)\n#define MDMA_GISR0_GIF14_Msk      (0x1UL << MDMA_GISR0_GIF14_Pos)              /*!< 0x00004000 */\n#define MDMA_GISR0_GIF14          MDMA_GISR0_GIF14_Msk                         /*!< Channel 14 global interrupt flag */\n#define MDMA_GISR0_GIF15_Pos      (15U)\n#define MDMA_GISR0_GIF15_Msk      (0x1UL << MDMA_GISR0_GIF15_Pos)              /*!< 0x00008000 */\n#define MDMA_GISR0_GIF15          MDMA_GISR0_GIF15_Msk                         /*!< Channel 15 global interrupt flag */\n\n/********************  Bit definition for MDMA_CxISR register  ****************/\n#define MDMA_CISR_TEIF_Pos        (0U)\n#define MDMA_CISR_TEIF_Msk        (0x1UL << MDMA_CISR_TEIF_Pos)                /*!< 0x00000001 */\n#define MDMA_CISR_TEIF            MDMA_CISR_TEIF_Msk                           /*!< Channel x transfer error interrupt flag */\n#define MDMA_CISR_CTCIF_Pos       (1U)\n#define MDMA_CISR_CTCIF_Msk       (0x1UL << MDMA_CISR_CTCIF_Pos)               /*!< 0x00000002 */\n#define MDMA_CISR_CTCIF           MDMA_CISR_CTCIF_Msk                          /*!< Channel x Channel Transfer Complete interrupt flag */\n#define MDMA_CISR_BRTIF_Pos       (2U)\n#define MDMA_CISR_BRTIF_Msk       (0x1UL << MDMA_CISR_BRTIF_Pos)               /*!< 0x00000004 */\n#define MDMA_CISR_BRTIF           MDMA_CISR_BRTIF_Msk                          /*!< Channel x block repeat transfer complete interrupt flag */\n#define MDMA_CISR_BTIF_Pos        (3U)\n#define MDMA_CISR_BTIF_Msk        (0x1UL << MDMA_CISR_BTIF_Pos)                /*!< 0x00000008 */\n#define MDMA_CISR_BTIF            MDMA_CISR_BTIF_Msk                           /*!< Channel x block transfer complete interrupt flag */\n#define MDMA_CISR_TCIF_Pos        (4U)\n#define MDMA_CISR_TCIF_Msk        (0x1UL << MDMA_CISR_TCIF_Pos)                /*!< 0x00000010 */\n#define MDMA_CISR_TCIF            MDMA_CISR_TCIF_Msk                           /*!< Channel x buffer transfer complete interrupt flag */\n#define MDMA_CISR_CRQA_Pos        (16U)\n#define MDMA_CISR_CRQA_Msk        (0x1UL << MDMA_CISR_CRQA_Pos)                /*!< 0x00010000 */\n#define MDMA_CISR_CRQA            MDMA_CISR_CRQA_Msk                           /*!< Channel x request Active flag */\n\n/********************  Bit definition for MDMA_CxIFCR register  ****************/\n#define MDMA_CIFCR_CTEIF_Pos      (0U)\n#define MDMA_CIFCR_CTEIF_Msk      (0x1UL << MDMA_CIFCR_CTEIF_Pos)              /*!< 0x00000001 */\n#define MDMA_CIFCR_CTEIF          MDMA_CIFCR_CTEIF_Msk                         /*!< Channel x clear transfer error interrupt flag */\n#define MDMA_CIFCR_CCTCIF_Pos     (1U)\n#define MDMA_CIFCR_CCTCIF_Msk     (0x1UL << MDMA_CIFCR_CCTCIF_Pos)             /*!< 0x00000002 */\n#define MDMA_CIFCR_CCTCIF         MDMA_CIFCR_CCTCIF_Msk                        /*!< Clear Channel transfer complete interrupt flag for channel x */\n#define MDMA_CIFCR_CBRTIF_Pos     (2U)\n#define MDMA_CIFCR_CBRTIF_Msk     (0x1UL << MDMA_CIFCR_CBRTIF_Pos)             /*!< 0x00000004 */\n#define MDMA_CIFCR_CBRTIF         MDMA_CIFCR_CBRTIF_Msk                        /*!< Channel x clear block repeat transfer complete interrupt flag */\n#define MDMA_CIFCR_CBTIF_Pos      (3U)\n#define MDMA_CIFCR_CBTIF_Msk      (0x1UL << MDMA_CIFCR_CBTIF_Pos)              /*!< 0x00000008 */\n#define MDMA_CIFCR_CBTIF          MDMA_CIFCR_CBTIF_Msk                         /*!< Channel x Clear block transfer complete interrupt flag */\n#define MDMA_CIFCR_CLTCIF_Pos     (4U)\n#define MDMA_CIFCR_CLTCIF_Msk     (0x1UL << MDMA_CIFCR_CLTCIF_Pos)             /*!< 0x00000010 */\n#define MDMA_CIFCR_CLTCIF         MDMA_CIFCR_CLTCIF_Msk                        /*!< CLear Transfer buffer Complete Interrupt Flag for channel */\n\n/********************  Bit definition for MDMA_CxESR register  ****************/\n#define MDMA_CESR_TEA_Pos         (0U)\n#define MDMA_CESR_TEA_Msk         (0x7FUL << MDMA_CESR_TEA_Pos)                /*!< 0x0000007F */\n#define MDMA_CESR_TEA             MDMA_CESR_TEA_Msk                            /*!< Transfer Error Address */\n#define MDMA_CESR_TED_Pos         (7U)\n#define MDMA_CESR_TED_Msk         (0x1UL << MDMA_CESR_TED_Pos)                 /*!< 0x00000080 */\n#define MDMA_CESR_TED             MDMA_CESR_TED_Msk                            /*!< Transfer Error Direction */\n#define MDMA_CESR_TELD_Pos        (8U)\n#define MDMA_CESR_TELD_Msk        (0x1UL << MDMA_CESR_TELD_Pos)                /*!< 0x00000100 */\n#define MDMA_CESR_TELD            MDMA_CESR_TELD_Msk                           /*!< Transfer Error Link Data */\n#define MDMA_CESR_TEMD_Pos        (9U)\n#define MDMA_CESR_TEMD_Msk        (0x1UL << MDMA_CESR_TEMD_Pos)                /*!< 0x00000200 */\n#define MDMA_CESR_TEMD            MDMA_CESR_TEMD_Msk                           /*!< Transfer Error Mask Data */\n#define MDMA_CESR_ASE_Pos         (10U)\n#define MDMA_CESR_ASE_Msk         (0x1UL << MDMA_CESR_ASE_Pos)                 /*!< 0x00000400 */\n#define MDMA_CESR_ASE             MDMA_CESR_ASE_Msk                            /*!< Address/Size Error       */\n#define MDMA_CESR_BSE_Pos         (11U)\n#define MDMA_CESR_BSE_Msk         (0x1UL << MDMA_CESR_BSE_Pos)                 /*!< 0x00000800 */\n#define MDMA_CESR_BSE             MDMA_CESR_BSE_Msk                            /*!< Block Size Error         */\n\n/********************  Bit definition for MDMA_CxCR register  ****************/\n#define MDMA_CCR_EN_Pos           (0U)\n#define MDMA_CCR_EN_Msk           (0x1UL << MDMA_CCR_EN_Pos)                   /*!< 0x00000001 */\n#define MDMA_CCR_EN               MDMA_CCR_EN_Msk                              /*!< Channel enable / flag channel ready when read low */\n#define MDMA_CCR_TEIE_Pos         (1U)\n#define MDMA_CCR_TEIE_Msk         (0x1UL << MDMA_CCR_TEIE_Pos)                 /*!< 0x00000002 */\n#define MDMA_CCR_TEIE             MDMA_CCR_TEIE_Msk                            /*!< Transfer error interrupt enable */\n#define MDMA_CCR_CTCIE_Pos        (2U)\n#define MDMA_CCR_CTCIE_Msk        (0x1UL << MDMA_CCR_CTCIE_Pos)                /*!< 0x00000004 */\n#define MDMA_CCR_CTCIE            MDMA_CCR_CTCIE_Msk                           /*!< Channel Transfer Complete interrupt enable */\n#define MDMA_CCR_BRTIE_Pos        (3U)\n#define MDMA_CCR_BRTIE_Msk        (0x1UL << MDMA_CCR_BRTIE_Pos)                /*!< 0x00000008 */\n#define MDMA_CCR_BRTIE            MDMA_CCR_BRTIE_Msk                           /*!< Block Repeat transfer interrupt enable */\n#define MDMA_CCR_BTIE_Pos         (4U)\n#define MDMA_CCR_BTIE_Msk         (0x1UL << MDMA_CCR_BTIE_Pos)                 /*!< 0x00000010 */\n#define MDMA_CCR_BTIE             MDMA_CCR_BTIE_Msk                            /*!< Block Transfer interrupt enable */\n#define MDMA_CCR_TCIE_Pos         (5U)\n#define MDMA_CCR_TCIE_Msk         (0x1UL << MDMA_CCR_TCIE_Pos)                 /*!< 0x00000020 */\n#define MDMA_CCR_TCIE             MDMA_CCR_TCIE_Msk                            /*!< buffer Transfer Complete interrupt enable */\n#define MDMA_CCR_PL_Pos           (6U)\n#define MDMA_CCR_PL_Msk           (0x3UL << MDMA_CCR_PL_Pos)                   /*!< 0x000000C0 */\n#define MDMA_CCR_PL               MDMA_CCR_PL_Msk                              /*!< Priority level */\n#define MDMA_CCR_PL_0             (0x1UL << MDMA_CCR_PL_Pos)                    /*!< 0x00000040 */\n#define MDMA_CCR_PL_1             (0x2UL << MDMA_CCR_PL_Pos)                    /*!< 0x00000080 */\n#define MDMA_CCR_BEX_Pos          (12U)\n#define MDMA_CCR_BEX_Msk          (0x1UL << MDMA_CCR_BEX_Pos)                  /*!< 0x00001000 */\n#define MDMA_CCR_BEX              MDMA_CCR_BEX_Msk                             /*!< Byte Endianness eXchange */\n#define MDMA_CCR_HEX_Pos          (13U)\n#define MDMA_CCR_HEX_Msk          (0x1UL << MDMA_CCR_HEX_Pos)                  /*!< 0x00002000 */\n#define MDMA_CCR_HEX              MDMA_CCR_HEX_Msk                             /*!< Half word Endianness eXchange */\n#define MDMA_CCR_WEX_Pos          (14U)\n#define MDMA_CCR_WEX_Msk          (0x1UL << MDMA_CCR_WEX_Pos)                  /*!< 0x00004000 */\n#define MDMA_CCR_WEX              MDMA_CCR_WEX_Msk                             /*!< Word Endianness eXchange */\n#define MDMA_CCR_SWRQ_Pos         (16U)\n#define MDMA_CCR_SWRQ_Msk         (0x1UL << MDMA_CCR_SWRQ_Pos)                 /*!< 0x00010000 */\n#define MDMA_CCR_SWRQ             MDMA_CCR_SWRQ_Msk                            /*!< SW ReQuest */\n\n/********************  Bit definition for MDMA_CxTCR register  ****************/\n#define MDMA_CTCR_SINC_Pos        (0U)\n#define MDMA_CTCR_SINC_Msk        (0x3UL << MDMA_CTCR_SINC_Pos)                /*!< 0x00000003 */\n#define MDMA_CTCR_SINC            MDMA_CTCR_SINC_Msk                           /*!< Source increment mode */\n#define MDMA_CTCR_SINC_0          (0x1UL << MDMA_CTCR_SINC_Pos)                 /*!< 0x00000001 */\n#define MDMA_CTCR_SINC_1          (0x2UL << MDMA_CTCR_SINC_Pos)                 /*!< 0x00000002 */\n#define MDMA_CTCR_DINC_Pos        (2U)\n#define MDMA_CTCR_DINC_Msk        (0x3UL << MDMA_CTCR_DINC_Pos)                /*!< 0x0000000C */\n#define MDMA_CTCR_DINC            MDMA_CTCR_DINC_Msk                           /*!< Source increment mode */\n#define MDMA_CTCR_DINC_0          (0x1UL << MDMA_CTCR_DINC_Pos)                 /*!< 0x00000004 */\n#define MDMA_CTCR_DINC_1          (0x2UL << MDMA_CTCR_DINC_Pos)                 /*!< 0x00000008 */\n#define MDMA_CTCR_SSIZE_Pos       (4U)\n#define MDMA_CTCR_SSIZE_Msk       (0x3UL << MDMA_CTCR_SSIZE_Pos)               /*!< 0x00000030 */\n#define MDMA_CTCR_SSIZE           MDMA_CTCR_SSIZE_Msk                          /*!< Source data size */\n#define MDMA_CTCR_SSIZE_0         (0x1UL << MDMA_CTCR_SSIZE_Pos)                /*!< 0x00000010 */\n#define MDMA_CTCR_SSIZE_1         (0x2UL << MDMA_CTCR_SSIZE_Pos)                /*!< 0x00000020 */\n#define MDMA_CTCR_DSIZE_Pos       (6U)\n#define MDMA_CTCR_DSIZE_Msk       (0x3UL << MDMA_CTCR_DSIZE_Pos)               /*!< 0x000000C0 */\n#define MDMA_CTCR_DSIZE           MDMA_CTCR_DSIZE_Msk                          /*!< Destination data size */\n#define MDMA_CTCR_DSIZE_0         (0x1UL << MDMA_CTCR_DSIZE_Pos)                /*!< 0x00000040 */\n#define MDMA_CTCR_DSIZE_1         (0x2UL << MDMA_CTCR_DSIZE_Pos)                /*!< 0x00000080 */\n#define MDMA_CTCR_SINCOS_Pos      (8U)\n#define MDMA_CTCR_SINCOS_Msk      (0x3UL << MDMA_CTCR_SINCOS_Pos)              /*!< 0x00000300 */\n#define MDMA_CTCR_SINCOS          MDMA_CTCR_SINCOS_Msk                         /*!< Source increment offset size */\n#define MDMA_CTCR_SINCOS_0        (0x1UL << MDMA_CTCR_SINCOS_Pos)               /*!< 0x00000100 */\n#define MDMA_CTCR_SINCOS_1        (0x2UL << MDMA_CTCR_SINCOS_Pos)               /*!< 0x00000200 */\n#define MDMA_CTCR_DINCOS_Pos      (10U)\n#define MDMA_CTCR_DINCOS_Msk      (0x3UL << MDMA_CTCR_DINCOS_Pos)              /*!< 0x00000C00 */\n#define MDMA_CTCR_DINCOS          MDMA_CTCR_DINCOS_Msk                         /*!< Destination increment offset size */\n#define MDMA_CTCR_DINCOS_0        (0x1UL << MDMA_CTCR_DINCOS_Pos)               /*!< 0x00000400 */\n#define MDMA_CTCR_DINCOS_1        (0x2UL << MDMA_CTCR_DINCOS_Pos)               /*!< 0x00000800 */\n#define MDMA_CTCR_SBURST_Pos      (12U)\n#define MDMA_CTCR_SBURST_Msk      (0x7UL << MDMA_CTCR_SBURST_Pos)              /*!< 0x00007000 */\n#define MDMA_CTCR_SBURST          MDMA_CTCR_SBURST_Msk                         /*!< Source burst transfer configuration */\n#define MDMA_CTCR_SBURST_0        (0x1UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00001000 */\n#define MDMA_CTCR_SBURST_1        (0x2UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00002000 */\n#define MDMA_CTCR_SBURST_2        (0x4UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00004000 */\n#define MDMA_CTCR_DBURST_Pos      (15U)\n#define MDMA_CTCR_DBURST_Msk      (0x7UL << MDMA_CTCR_DBURST_Pos)              /*!< 0x00038000 */\n#define MDMA_CTCR_DBURST          MDMA_CTCR_DBURST_Msk                         /*!< Destination burst transfer configuration */\n#define MDMA_CTCR_DBURST_0        (0x1UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00008000 */\n#define MDMA_CTCR_DBURST_1        (0x2UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00010000 */\n#define MDMA_CTCR_DBURST_2        (0x4UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00020000 */\n#define MDMA_CTCR_TLEN_Pos        (18U)\n#define MDMA_CTCR_TLEN_Msk        (0x7FUL << MDMA_CTCR_TLEN_Pos)               /*!< 0x01FC0000 */\n#define MDMA_CTCR_TLEN            MDMA_CTCR_TLEN_Msk                           /*!< buffer Transfer Length (number of bytes - 1) */\n#define MDMA_CTCR_PKE_Pos         (25U)\n#define MDMA_CTCR_PKE_Msk         (0x1UL << MDMA_CTCR_PKE_Pos)                 /*!< 0x02000000 */\n#define MDMA_CTCR_PKE             MDMA_CTCR_PKE_Msk                            /*!< PacK Enable */\n#define MDMA_CTCR_PAM_Pos         (26U)\n#define MDMA_CTCR_PAM_Msk         (0x3UL << MDMA_CTCR_PAM_Pos)                 /*!< 0x0C000000 */\n#define MDMA_CTCR_PAM             MDMA_CTCR_PAM_Msk                            /*!< Padding/Alignment Mode */\n#define MDMA_CTCR_PAM_0           (0x1UL << MDMA_CTCR_PAM_Pos)                  /*!< 0x4000000 */\n#define MDMA_CTCR_PAM_1           (0x2UL << MDMA_CTCR_PAM_Pos)                  /*!< 0x8000000 */\n#define MDMA_CTCR_TRGM_Pos        (28U)\n#define MDMA_CTCR_TRGM_Msk        (0x3UL << MDMA_CTCR_TRGM_Pos)                /*!< 0x30000000 */\n#define MDMA_CTCR_TRGM            MDMA_CTCR_TRGM_Msk                           /*!< Trigger Mode */\n#define MDMA_CTCR_TRGM_0          (0x1UL << MDMA_CTCR_TRGM_Pos)                 /*!< 0x10000000 */\n#define MDMA_CTCR_TRGM_1          (0x2UL << MDMA_CTCR_TRGM_Pos)                 /*!< 0x20000000 */\n#define MDMA_CTCR_SWRM_Pos        (30U)\n#define MDMA_CTCR_SWRM_Msk        (0x1UL << MDMA_CTCR_SWRM_Pos)                /*!< 0x40000000 */\n#define MDMA_CTCR_SWRM            MDMA_CTCR_SWRM_Msk                           /*!< SW Request Mode */\n#define MDMA_CTCR_BWM_Pos         (31U)\n#define MDMA_CTCR_BWM_Msk         (0x1UL << MDMA_CTCR_BWM_Pos)                 /*!< 0x80000000 */\n#define MDMA_CTCR_BWM             MDMA_CTCR_BWM_Msk                            /*!< Bufferable Write Mode */\n\n/********************  Bit definition for MDMA_CxBNDTR register  ****************/\n#define MDMA_CBNDTR_BNDT_Pos      (0U)\n#define MDMA_CBNDTR_BNDT_Msk      (0x1FFFFUL << MDMA_CBNDTR_BNDT_Pos)          /*!< 0x0001FFFF */\n#define MDMA_CBNDTR_BNDT          MDMA_CBNDTR_BNDT_Msk                         /*!< Block Number of data bytes to transfer */\n#define MDMA_CBNDTR_BRSUM_Pos     (18U)\n#define MDMA_CBNDTR_BRSUM_Msk     (0x1UL << MDMA_CBNDTR_BRSUM_Pos)             /*!< 0x00040000 */\n#define MDMA_CBNDTR_BRSUM         MDMA_CBNDTR_BRSUM_Msk                        /*!< Block Repeat Source address Update Mode */\n#define MDMA_CBNDTR_BRDUM_Pos     (19U)\n#define MDMA_CBNDTR_BRDUM_Msk     (0x1UL << MDMA_CBNDTR_BRDUM_Pos)             /*!< 0x00080000 */\n#define MDMA_CBNDTR_BRDUM         MDMA_CBNDTR_BRDUM_Msk                        /*!< Block Repeat Destination address Update Mode */\n#define MDMA_CBNDTR_BRC_Pos       (20U)\n#define MDMA_CBNDTR_BRC_Msk       (0xFFFUL << MDMA_CBNDTR_BRC_Pos)             /*!< 0xFFF00000 */\n#define MDMA_CBNDTR_BRC           MDMA_CBNDTR_BRC_Msk                          /*!< Block Repeat Count */\n\n/********************  Bit definition for MDMA_CxSAR register  ****************/\n#define MDMA_CSAR_SAR_Pos         (0U)\n#define MDMA_CSAR_SAR_Msk         (0xFFFFFFFFUL << MDMA_CSAR_SAR_Pos)          /*!< 0xFFFFFFFF */\n#define MDMA_CSAR_SAR             MDMA_CSAR_SAR_Msk                            /*!< Source address */\n\n/********************  Bit definition for MDMA_CxDAR register  ****************/\n#define MDMA_CDAR_DAR_Pos         (0U)\n#define MDMA_CDAR_DAR_Msk         (0xFFFFFFFFUL << MDMA_CDAR_DAR_Pos)          /*!< 0xFFFFFFFF */\n#define MDMA_CDAR_DAR             MDMA_CDAR_DAR_Msk                            /*!< Destination address */\n\n/********************  Bit definition for MDMA_CxBRUR  ************************/\n#define MDMA_CBRUR_SUV_Pos        (0U)\n#define MDMA_CBRUR_SUV_Msk        (0xFFFFUL << MDMA_CBRUR_SUV_Pos)             /*!< 0x0000FFFF */\n#define MDMA_CBRUR_SUV            MDMA_CBRUR_SUV_Msk                           /*!< Source address Update Value */\n#define MDMA_CBRUR_DUV_Pos        (16U)\n#define MDMA_CBRUR_DUV_Msk        (0xFFFFUL << MDMA_CBRUR_DUV_Pos)             /*!< 0xFFFF0000 */\n#define MDMA_CBRUR_DUV            MDMA_CBRUR_DUV_Msk                           /*!< Destination address Update Value */\n\n/********************  Bit definition for MDMA_CxLAR  *************************/\n#define MDMA_CLAR_LAR_Pos         (0U)\n#define MDMA_CLAR_LAR_Msk         (0xFFFFFFFFUL << MDMA_CLAR_LAR_Pos)          /*!< 0xFFFFFFFF */\n#define MDMA_CLAR_LAR             MDMA_CLAR_LAR_Msk                            /*!< Link Address Register */\n\n/********************  Bit definition for MDMA_CxTBR)  ************************/\n#define MDMA_CTBR_TSEL_Pos        (0U)\n#define MDMA_CTBR_TSEL_Msk        (0xFFUL << MDMA_CTBR_TSEL_Pos)               /*!< 0x000000FF */\n#define MDMA_CTBR_TSEL            MDMA_CTBR_TSEL_Msk                           /*!< Trigger SELection */\n#define MDMA_CTBR_SBUS_Pos        (16U)\n#define MDMA_CTBR_SBUS_Msk        (0x1UL << MDMA_CTBR_SBUS_Pos)                /*!< 0x00010000 */\n#define MDMA_CTBR_SBUS            MDMA_CTBR_SBUS_Msk                           /*!< Source BUS select */\n#define MDMA_CTBR_DBUS_Pos        (17U)\n#define MDMA_CTBR_DBUS_Msk        (0x1UL << MDMA_CTBR_DBUS_Pos)                /*!< 0x00020000 */\n#define MDMA_CTBR_DBUS            MDMA_CTBR_DBUS_Msk                           /*!< Destination BUS select */\n\n/********************  Bit definition for MDMA_CxMAR)  ************************/\n#define MDMA_CMAR_MAR_Pos         (0U)\n#define MDMA_CMAR_MAR_Msk         (0xFFFFFFFFUL << MDMA_CMAR_MAR_Pos)          /*!< 0xFFFFFFFF */\n#define MDMA_CMAR_MAR             MDMA_CMAR_MAR_Msk                            /*!< Mask address */\n\n/********************  Bit definition for MDMA_CxMDR)  ************************/\n#define MDMA_CMDR_MDR_Pos         (0U)\n#define MDMA_CMDR_MDR_Msk         (0xFFFFFFFFUL << MDMA_CMDR_MDR_Pos)          /*!< 0xFFFFFFFF */\n#define MDMA_CMDR_MDR             MDMA_CMDR_MDR_Msk                            /*!< Mask Data */\n\n/******************************************************************************/\n/*                                                                            */\n/*                         Operational Amplifier (OPAMP)                      */\n/*                                                                            */\n/******************************************************************************/\n/*********************  Bit definition for OPAMPx_CSR register  ***************/\n#define OPAMP_CSR_OPAMPxEN_Pos           (0U)\n#define OPAMP_CSR_OPAMPxEN_Msk           (0x1UL << OPAMP_CSR_OPAMPxEN_Pos)     /*!< 0x00000001 */\n#define OPAMP_CSR_OPAMPxEN               OPAMP_CSR_OPAMPxEN_Msk                /*!< OPAMP enable */\n#define OPAMP_CSR_FORCEVP_Pos            (1U)\n#define OPAMP_CSR_FORCEVP_Msk            (0x1UL << OPAMP_CSR_FORCEVP_Pos)      /*!< 0x00000002 */\n#define OPAMP_CSR_FORCEVP                OPAMP_CSR_FORCEVP_Msk                 /*!< Force internal reference on VP */\n\n#define OPAMP_CSR_VPSEL_Pos              (2U)\n#define OPAMP_CSR_VPSEL_Msk              (0x3UL << OPAMP_CSR_VPSEL_Pos)        /*!< 0x0000000C */\n#define OPAMP_CSR_VPSEL                  OPAMP_CSR_VPSEL_Msk                   /*!< Non inverted input selection */\n#define OPAMP_CSR_VPSEL_0                (0x1UL << OPAMP_CSR_VPSEL_Pos)         /*!< 0x00000004 */\n#define OPAMP_CSR_VPSEL_1                (0x2UL << OPAMP_CSR_VPSEL_Pos)         /*!< 0x00000008 */\n\n#define OPAMP_CSR_VMSEL_Pos              (5U)\n#define OPAMP_CSR_VMSEL_Msk              (0x3UL << OPAMP_CSR_VMSEL_Pos)        /*!< 0x00000060 */\n#define OPAMP_CSR_VMSEL                  OPAMP_CSR_VMSEL_Msk                   /*!< Inverting input selection */\n#define OPAMP_CSR_VMSEL_0                (0x1UL << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000020 */\n#define OPAMP_CSR_VMSEL_1                (0x2UL << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000040 */\n\n#define OPAMP_CSR_OPAHSM_Pos             (8U)\n#define OPAMP_CSR_OPAHSM_Msk             (0x1UL << OPAMP_CSR_OPAHSM_Pos)       /*!< 0x00000100 */\n#define OPAMP_CSR_OPAHSM                 OPAMP_CSR_OPAHSM_Msk                  /*!< Operational amplifier high speed mode */\n#define OPAMP_CSR_CALON_Pos              (11U)\n#define OPAMP_CSR_CALON_Msk              (0x1UL << OPAMP_CSR_CALON_Pos)        /*!< 0x00000800 */\n#define OPAMP_CSR_CALON                  OPAMP_CSR_CALON_Msk                   /*!< Calibration mode enable */\n\n#define OPAMP_CSR_CALSEL_Pos             (12U)\n#define OPAMP_CSR_CALSEL_Msk             (0x3UL << OPAMP_CSR_CALSEL_Pos)       /*!< 0x00003000 */\n#define OPAMP_CSR_CALSEL                 OPAMP_CSR_CALSEL_Msk                  /*!< Calibration selection */\n#define OPAMP_CSR_CALSEL_0               (0x1UL << OPAMP_CSR_CALSEL_Pos)        /*!< 0x00001000 */\n#define OPAMP_CSR_CALSEL_1               (0x2UL << OPAMP_CSR_CALSEL_Pos)        /*!< 0x00002000 */\n\n#define OPAMP_CSR_PGGAIN_Pos             (14U)\n#define OPAMP_CSR_PGGAIN_Msk             (0xFUL << OPAMP_CSR_PGGAIN_Pos)       /*!< 0x0003C000 */\n#define OPAMP_CSR_PGGAIN                 OPAMP_CSR_PGGAIN_Msk                  /*!< Operational amplifier Programmable amplifier gain value */\n#define OPAMP_CSR_PGGAIN_0               (0x1UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00004000 */\n#define OPAMP_CSR_PGGAIN_1               (0x2UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00008000 */\n#define OPAMP_CSR_PGGAIN_2               (0x4UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00010000 */\n#define OPAMP_CSR_PGGAIN_3               (0x8UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00020000 */\n\n#define OPAMP_CSR_USERTRIM_Pos           (18U)\n#define OPAMP_CSR_USERTRIM_Msk           (0x1UL << OPAMP_CSR_USERTRIM_Pos)     /*!< 0x00040000 */\n#define OPAMP_CSR_USERTRIM               OPAMP_CSR_USERTRIM_Msk                /*!< User trimming enable */\n#define OPAMP_CSR_TSTREF_Pos             (29U)\n#define OPAMP_CSR_TSTREF_Msk             (0x1UL << OPAMP_CSR_TSTREF_Pos)       /*!< 0x20000000 */\n#define OPAMP_CSR_TSTREF                 OPAMP_CSR_TSTREF_Msk                  /*!< OpAmp calibration reference voltage output control */\n#define OPAMP_CSR_CALOUT_Pos             (30U)\n#define OPAMP_CSR_CALOUT_Msk             (0x1UL << OPAMP_CSR_CALOUT_Pos)       /*!< 0x40000000 */\n#define OPAMP_CSR_CALOUT                 OPAMP_CSR_CALOUT_Msk                  /*!< Operational amplifier calibration output */\n\n/*********************  Bit definition for OPAMP1_CSR register  ***************/\n#define OPAMP1_CSR_OPAEN_Pos              (0U)\n#define OPAMP1_CSR_OPAEN_Msk              (0x1UL << OPAMP1_CSR_OPAEN_Pos)      /*!< 0x00000001 */\n#define OPAMP1_CSR_OPAEN                  OPAMP1_CSR_OPAEN_Msk                 /*!< Operational amplifier1 Enable */\n#define OPAMP1_CSR_FORCEVP_Pos            (1U)\n#define OPAMP1_CSR_FORCEVP_Msk            (0x1UL << OPAMP1_CSR_FORCEVP_Pos)    /*!< 0x00000002 */\n#define OPAMP1_CSR_FORCEVP                OPAMP1_CSR_FORCEVP_Msk               /*!< Force internal reference on VP */\n\n#define OPAMP1_CSR_VPSEL_Pos              (2U)\n#define OPAMP1_CSR_VPSEL_Msk              (0x3UL << OPAMP1_CSR_VPSEL_Pos)      /*!< 0x0000000C */\n#define OPAMP1_CSR_VPSEL                  OPAMP1_CSR_VPSEL_Msk                 /*!< Non inverted input selection */\n#define OPAMP1_CSR_VPSEL_0                (0x1UL << OPAMP1_CSR_VPSEL_Pos)       /*!< 0x00000004 */\n#define OPAMP1_CSR_VPSEL_1                (0x2UL << OPAMP1_CSR_VPSEL_Pos)       /*!< 0x00000008 */\n\n#define OPAMP1_CSR_VMSEL_Pos              (5U)\n#define OPAMP1_CSR_VMSEL_Msk              (0x3UL << OPAMP1_CSR_VMSEL_Pos)      /*!< 0x00000060 */\n#define OPAMP1_CSR_VMSEL                  OPAMP1_CSR_VMSEL_Msk                 /*!< Inverting input selection */\n#define OPAMP1_CSR_VMSEL_0                (0x1UL << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000020 */\n#define OPAMP1_CSR_VMSEL_1                (0x2UL << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000040 */\n\n#define OPAMP1_CSR_OPAHSM_Pos             (8U)\n#define OPAMP1_CSR_OPAHSM_Msk             (0x1UL << OPAMP1_CSR_OPAHSM_Pos)     /*!< 0x00000100 */\n#define OPAMP1_CSR_OPAHSM                 OPAMP1_CSR_OPAHSM_Msk                /*!< Operational amplifier1 high speed mode */\n#define OPAMP1_CSR_CALON_Pos              (11U)\n#define OPAMP1_CSR_CALON_Msk              (0x1UL << OPAMP1_CSR_CALON_Pos)      /*!< 0x00000800 */\n#define OPAMP1_CSR_CALON                  OPAMP1_CSR_CALON_Msk                 /*!< Calibration mode enable */\n\n#define OPAMP1_CSR_CALSEL_Pos             (12U)\n#define OPAMP1_CSR_CALSEL_Msk             (0x3UL << OPAMP1_CSR_CALSEL_Pos)     /*!< 0x00003000 */\n#define OPAMP1_CSR_CALSEL                 OPAMP1_CSR_CALSEL_Msk                /*!< Calibration selection */\n#define OPAMP1_CSR_CALSEL_0               (0x1UL << OPAMP1_CSR_CALSEL_Pos)      /*!< 0x00001000 */\n#define OPAMP1_CSR_CALSEL_1               (0x2UL << OPAMP1_CSR_CALSEL_Pos)      /*!< 0x00002000 */\n\n#define OPAMP1_CSR_PGGAIN_Pos             (14U)\n#define OPAMP1_CSR_PGGAIN_Msk             (0xFUL << OPAMP1_CSR_PGGAIN_Pos)     /*!< 0x0003C000 */\n#define OPAMP1_CSR_PGGAIN                 OPAMP1_CSR_PGGAIN_Msk                /*!< Operational amplifier1 Programmable amplifier gain value */\n#define OPAMP1_CSR_PGGAIN_0               (0x1UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00004000 */\n#define OPAMP1_CSR_PGGAIN_1               (0x2UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00008000 */\n#define OPAMP1_CSR_PGGAIN_2               (0x4UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00010000 */\n#define OPAMP1_CSR_PGGAIN_3               (0x8UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00020000 */\n\n#define OPAMP1_CSR_USERTRIM_Pos           (18U)\n#define OPAMP1_CSR_USERTRIM_Msk           (0x1UL << OPAMP1_CSR_USERTRIM_Pos)   /*!< 0x00040000 */\n#define OPAMP1_CSR_USERTRIM               OPAMP1_CSR_USERTRIM_Msk              /*!< User trimming enable */\n#define OPAMP1_CSR_TSTREF_Pos             (29U)\n#define OPAMP1_CSR_TSTREF_Msk             (0x1UL << OPAMP1_CSR_TSTREF_Pos)     /*!< 0x20000000 */\n#define OPAMP1_CSR_TSTREF                 OPAMP1_CSR_TSTREF_Msk                /*!< OpAmp calibration reference voltage output control */\n#define OPAMP1_CSR_CALOUT_Pos             (30U)\n#define OPAMP1_CSR_CALOUT_Msk             (0x1UL << OPAMP1_CSR_CALOUT_Pos)     /*!< 0x40000000 */\n#define OPAMP1_CSR_CALOUT                 OPAMP1_CSR_CALOUT_Msk                /*!< Operational amplifier1 calibration output */\n\n/*********************  Bit definition for OPAMP2_CSR register  ***************/\n#define OPAMP2_CSR_OPAEN_Pos              (0U)\n#define OPAMP2_CSR_OPAEN_Msk              (0x1UL << OPAMP2_CSR_OPAEN_Pos)      /*!< 0x00000001 */\n#define OPAMP2_CSR_OPAEN                  OPAMP2_CSR_OPAEN_Msk                 /*!< Operational amplifier2 Enable */\n#define OPAMP2_CSR_FORCEVP_Pos            (1U)\n#define OPAMP2_CSR_FORCEVP_Msk            (0x1UL << OPAMP2_CSR_FORCEVP_Pos)    /*!< 0x00000002 */\n#define OPAMP2_CSR_FORCEVP                OPAMP2_CSR_FORCEVP_Msk               /*!< Force internal reference on VP */\n\n#define OPAMP2_CSR_VPSEL_Pos              (2U)\n#define OPAMP2_CSR_VPSEL_Msk              (0x3UL << OPAMP2_CSR_VPSEL_Pos)      /*!< 0x0000000C */\n#define OPAMP2_CSR_VPSEL                  OPAMP2_CSR_VPSEL_Msk                 /*!< Non inverted input selection */\n#define OPAMP2_CSR_VPSEL_0                (0x1UL << OPAMP2_CSR_VPSEL_Pos)       /*!< 0x00000004 */\n#define OPAMP2_CSR_VPSEL_1                (0x2UL << OPAMP2_CSR_VPSEL_Pos)       /*!< 0x00000008 */\n\n#define OPAMP2_CSR_VMSEL_Pos              (5U)\n#define OPAMP2_CSR_VMSEL_Msk              (0x3UL << OPAMP2_CSR_VMSEL_Pos)      /*!< 0x00000060 */\n#define OPAMP2_CSR_VMSEL                  OPAMP2_CSR_VMSEL_Msk                 /*!< Inverting input selection */\n#define OPAMP2_CSR_VMSEL_0                (0x1UL << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000020 */\n#define OPAMP2_CSR_VMSEL_1                (0x2UL << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000040 */\n\n#define OPAMP2_CSR_OPAHSM_Pos             (8U)\n#define OPAMP2_CSR_OPAHSM_Msk             (0x1UL << OPAMP2_CSR_OPAHSM_Pos)     /*!< 0x00000100 */\n#define OPAMP2_CSR_OPAHSM                 OPAMP2_CSR_OPAHSM_Msk                /*!< Operational amplifier2 high speed mode */\n#define OPAMP2_CSR_CALON_Pos              (11U)\n#define OPAMP2_CSR_CALON_Msk              (0x1UL << OPAMP2_CSR_CALON_Pos)      /*!< 0x00000800 */\n#define OPAMP2_CSR_CALON                  OPAMP2_CSR_CALON_Msk                 /*!< Calibration mode enable */\n\n#define OPAMP2_CSR_CALSEL_Pos             (12U)\n#define OPAMP2_CSR_CALSEL_Msk             (0x3UL << OPAMP2_CSR_CALSEL_Pos)     /*!< 0x00003000 */\n#define OPAMP2_CSR_CALSEL                 OPAMP2_CSR_CALSEL_Msk                /*!< Calibration selection */\n#define OPAMP2_CSR_CALSEL_0               (0x1UL << OPAMP2_CSR_CALSEL_Pos)      /*!< 0x00001000 */\n#define OPAMP2_CSR_CALSEL_1               (0x2UL << OPAMP2_CSR_CALSEL_Pos)      /*!< 0x00002000 */\n\n#define OPAMP2_CSR_PGGAIN_Pos             (14U)\n#define OPAMP2_CSR_PGGAIN_Msk             (0xFUL << OPAMP2_CSR_PGGAIN_Pos)     /*!< 0x0003C000 */\n#define OPAMP2_CSR_PGGAIN                 OPAMP2_CSR_PGGAIN_Msk                /*!< Operational amplifier2 Programmable amplifier gain value */\n#define OPAMP2_CSR_PGGAIN_0               (0x1UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00004000 */\n#define OPAMP2_CSR_PGGAIN_1               (0x2UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00008000 */\n#define OPAMP2_CSR_PGGAIN_2               (0x4UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00010000 */\n#define OPAMP2_CSR_PGGAIN_3               (0x8UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00020000 */\n\n#define OPAMP2_CSR_USERTRIM_Pos           (18U)\n#define OPAMP2_CSR_USERTRIM_Msk           (0x1UL << OPAMP2_CSR_USERTRIM_Pos)   /*!< 0x00040000 */\n#define OPAMP2_CSR_USERTRIM               OPAMP2_CSR_USERTRIM_Msk              /*!< User trimming enable */\n#define OPAMP2_CSR_TSTREF_Pos             (29U)\n#define OPAMP2_CSR_TSTREF_Msk             (0x1UL << OPAMP2_CSR_TSTREF_Pos)     /*!< 0x20000000 */\n#define OPAMP2_CSR_TSTREF                 OPAMP2_CSR_TSTREF_Msk                /*!< OpAmp calibration reference voltage output control */\n#define OPAMP2_CSR_CALOUT_Pos             (30U)\n#define OPAMP2_CSR_CALOUT_Msk             (0x1UL << OPAMP2_CSR_CALOUT_Pos)     /*!< 0x40000000 */\n#define OPAMP2_CSR_CALOUT                 OPAMP2_CSR_CALOUT_Msk                /*!< Operational amplifier2 calibration output */\n\n/*******************  Bit definition for OPAMP_OTR register  ******************/\n#define OPAMP_OTR_TRIMOFFSETN_Pos        (0U)\n#define OPAMP_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */\n#define OPAMP_OTR_TRIMOFFSETN            OPAMP_OTR_TRIMOFFSETN_Msk             /*!< Trim for NMOS differential pairs */\n#define OPAMP_OTR_TRIMOFFSETP_Pos        (8U)\n#define OPAMP_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */\n#define OPAMP_OTR_TRIMOFFSETP            OPAMP_OTR_TRIMOFFSETP_Msk             /*!< Trim for PMOS differential pairs */\n\n/*******************  Bit definition for OPAMP1_OTR register  ******************/\n#define OPAMP1_OTR_TRIMOFFSETN_Pos        (0U)\n#define OPAMP1_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */\n#define OPAMP1_OTR_TRIMOFFSETN            OPAMP1_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */\n#define OPAMP1_OTR_TRIMOFFSETP_Pos        (8U)\n#define OPAMP1_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */\n#define OPAMP1_OTR_TRIMOFFSETP            OPAMP1_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */\n\n/*******************  Bit definition for OPAMP2_OTR register  ******************/\n#define OPAMP2_OTR_TRIMOFFSETN_Pos        (0U)\n#define OPAMP2_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP2_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */\n#define OPAMP2_OTR_TRIMOFFSETN            OPAMP2_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */\n#define OPAMP2_OTR_TRIMOFFSETP_Pos        (8U)\n#define OPAMP2_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP2_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */\n#define OPAMP2_OTR_TRIMOFFSETP            OPAMP2_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */\n\n/*******************  Bit definition for OPAMP_HSOTR register  ****************/\n#define OPAMP_HSOTR_TRIMHSOFFSETN_Pos    (0U)\n#define OPAMP_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */\n#define OPAMP_HSOTR_TRIMHSOFFSETN        OPAMP_HSOTR_TRIMHSOFFSETN_Msk         /*!< Trim for NMOS differential pairs */\n#define OPAMP_HSOTR_TRIMHSOFFSETP_Pos    (8U)\n#define OPAMP_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */\n#define OPAMP_HSOTR_TRIMHSOFFSETP        OPAMP_HSOTR_TRIMHSOFFSETP_Msk         /*!< Trim for PMOS differential pairs */\n\n/*******************  Bit definition for OPAMP1_HSOTR register  ****************/\n#define OPAMP1_HSOTR_TRIMHSOFFSETN_Pos    (0U)\n#define OPAMP1_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */\n#define OPAMP1_HSOTR_TRIMHSOFFSETN        OPAMP1_HSOTR_TRIMHSOFFSETN_Msk       /*!< Trim for NMOS differential pairs */\n#define OPAMP1_HSOTR_TRIMHSOFFSETP_Pos    (8U)\n#define OPAMP1_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */\n#define OPAMP1_HSOTR_TRIMHSOFFSETP        OPAMP1_HSOTR_TRIMHSOFFSETP_Msk       /*!< Trim for PMOS differential pairs */\n\n/*******************  Bit definition for OPAMP2_HSOTR register  ****************/\n#define OPAMP2_HSOTR_TRIMHSOFFSETN_Pos    (0U)\n#define OPAMP2_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */\n#define OPAMP2_HSOTR_TRIMHSOFFSETN        OPAMP2_HSOTR_TRIMHSOFFSETN_Msk       /*!< Trim for NMOS differential pairs */\n#define OPAMP2_HSOTR_TRIMHSOFFSETP_Pos    (8U)\n#define OPAMP2_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */\n#define OPAMP2_HSOTR_TRIMHSOFFSETP        OPAMP2_HSOTR_TRIMHSOFFSETP_Msk       /*!< Trim for PMOS differential pairs */\n\n/******************************************************************************/\n/*                                                                            */\n/*                             Power Control                                  */\n/*                                                                            */\n/******************************************************************************/\n/*************************  NUMBER OF POWER DOMAINS  **************************/\n#define POWER_DOMAINS_NUMBER           3U                                      /*!< 3 Domains */\n\n/********************  Bit definition for PWR_CR1 register  *******************/\n#define PWR_CR1_ALS_Pos                (17U)\n#define PWR_CR1_ALS_Msk                (0x3UL << PWR_CR1_ALS_Pos)              /*!< 0x00060000 */\n#define PWR_CR1_ALS                    PWR_CR1_ALS_Msk                         /*!< Analog Voltage Detector level selection */\n#define PWR_CR1_ALS_0                  (0x1UL << PWR_CR1_ALS_Pos)              /*!< 0x00020000 */\n#define PWR_CR1_ALS_1                  (0x2UL << PWR_CR1_ALS_Pos)              /*!< 0x00040000 */\n#define PWR_CR1_AVDEN_Pos              (16U)\n#define PWR_CR1_AVDEN_Msk              (0x1UL << PWR_CR1_AVDEN_Pos)            /*!< 0x00010000 */\n#define PWR_CR1_AVDEN                  PWR_CR1_AVDEN_Msk                       /*!< Analog Voltage Detector Enable */\n#define PWR_CR1_SVOS_Pos               (14U)\n#define PWR_CR1_SVOS_Msk               (0x3UL << PWR_CR1_SVOS_Pos)             /*!< 0x0000C000 */\n#define PWR_CR1_SVOS                   PWR_CR1_SVOS_Msk                        /*!< System STOP mode Voltage Scaling selection */\n#define PWR_CR1_SVOS_0                 (0x1UL << PWR_CR1_SVOS_Pos)             /*!< 0x00004000 */\n#define PWR_CR1_SVOS_1                 (0x2UL << PWR_CR1_SVOS_Pos)             /*!< 0x00008000 */\n#define PWR_CR1_FLPS_Pos               (9U)\n#define PWR_CR1_FLPS_Msk               (0x1UL << PWR_CR1_FLPS_Pos)             /*!< 0x00000200 */\n#define PWR_CR1_FLPS                   PWR_CR1_FLPS_Msk                        /*!< Flash low power mode in DSTOP */\n#define PWR_CR1_DBP_Pos                (8U)\n#define PWR_CR1_DBP_Msk                (0x1UL << PWR_CR1_DBP_Pos)              /*!< 0x00000100 */\n#define PWR_CR1_DBP                    PWR_CR1_DBP_Msk                         /*!< Disable Back-up domain Protection */\n#define PWR_CR1_PLS_Pos                (5U)\n#define PWR_CR1_PLS_Msk                (0x7UL << PWR_CR1_PLS_Pos)              /*!< 0x000000E0 */\n#define PWR_CR1_PLS                    PWR_CR1_PLS_Msk                         /*!< Programmable Voltage Detector level selection */\n#define PWR_CR1_PLS_0                  (0x1UL << PWR_CR1_PLS_Pos)              /*!< 0x00000020 */\n#define PWR_CR1_PLS_1                  (0x2UL << PWR_CR1_PLS_Pos)              /*!< 0x00000040 */\n#define PWR_CR1_PLS_2                  (0x4UL << PWR_CR1_PLS_Pos)              /*!< 0x00000080 */\n#define PWR_CR1_PVDEN_Pos              (4U)\n#define PWR_CR1_PVDEN_Msk              (0x1UL << PWR_CR1_PVDEN_Pos)            /*!< 0x00000010 */\n#define PWR_CR1_PVDEN                  PWR_CR1_PVDEN_Msk                       /*!< Programmable Voltage detector enable */\n#define PWR_CR1_LPDS_Pos               (0U)\n#define PWR_CR1_LPDS_Msk               (0x1UL << PWR_CR1_LPDS_Pos)             /*!< 0x00000001 */\n#define PWR_CR1_LPDS                   PWR_CR1_LPDS_Msk                        /*!< Low Power Deepsleep with SVOS3 */\n\n/*!< PVD level configuration */\n#define PWR_CR1_PLS_LEV0               (0UL)                                   /*!< PVD level 0 */\n#define PWR_CR1_PLS_LEV1_Pos           (5U)\n#define PWR_CR1_PLS_LEV1_Msk           (0x1UL << PWR_CR1_PLS_LEV1_Pos)         /*!< 0x00000020 */\n#define PWR_CR1_PLS_LEV1               PWR_CR1_PLS_LEV1_Msk                    /*!< PVD level 1 */\n#define PWR_CR1_PLS_LEV2_Pos           (6U)\n#define PWR_CR1_PLS_LEV2_Msk           (0x1UL << PWR_CR1_PLS_LEV2_Pos)         /*!< 0x00000040 */\n#define PWR_CR1_PLS_LEV2               PWR_CR1_PLS_LEV2_Msk                    /*!< PVD level 2 */\n#define PWR_CR1_PLS_LEV3_Pos           (5U)\n#define PWR_CR1_PLS_LEV3_Msk           (0x3UL << PWR_CR1_PLS_LEV3_Pos)         /*!< 0x00000060 */\n#define PWR_CR1_PLS_LEV3               PWR_CR1_PLS_LEV3_Msk                    /*!< PVD level 3 */\n#define PWR_CR1_PLS_LEV4_Pos           (7U)\n#define PWR_CR1_PLS_LEV4_Msk           (0x1UL << PWR_CR1_PLS_LEV4_Pos)         /*!< 0x00000080 */\n#define PWR_CR1_PLS_LEV4               PWR_CR1_PLS_LEV4_Msk                    /*!< PVD level 4 */\n#define PWR_CR1_PLS_LEV5_Pos           (5U)\n#define PWR_CR1_PLS_LEV5_Msk           (0x5UL << PWR_CR1_PLS_LEV5_Pos)         /*!< 0x000000A0 */\n#define PWR_CR1_PLS_LEV5               PWR_CR1_PLS_LEV5_Msk                    /*!< PVD level 5 */\n#define PWR_CR1_PLS_LEV6_Pos           (6U)\n#define PWR_CR1_PLS_LEV6_Msk           (0x3UL << PWR_CR1_PLS_LEV6_Pos)         /*!< 0x000000C0 */\n#define PWR_CR1_PLS_LEV6               PWR_CR1_PLS_LEV6_Msk                    /*!< PVD level 6 */\n#define PWR_CR1_PLS_LEV7_Pos           (5U)\n#define PWR_CR1_PLS_LEV7_Msk           (0x7UL << PWR_CR1_PLS_LEV7_Pos)         /*!< 0x000000E0 */\n#define PWR_CR1_PLS_LEV7               PWR_CR1_PLS_LEV7_Msk                    /*!< PVD level 7 */\n\n/*!< AVD level configuration */\n#define PWR_CR1_ALS_LEV0               (0UL)                                   /*!< AVD level 0 */\n#define PWR_CR1_ALS_LEV1_Pos           (17U)\n#define PWR_CR1_ALS_LEV1_Msk           (0x1UL << PWR_CR1_ALS_LEV1_Pos)         /*!< 0x00020000 */\n#define PWR_CR1_ALS_LEV1               PWR_CR1_ALS_LEV1_Msk                    /*!< AVD level 1 */\n#define PWR_CR1_ALS_LEV2_Pos           (18U)\n#define PWR_CR1_ALS_LEV2_Msk           (0x1UL << PWR_CR1_ALS_LEV2_Pos)         /*!< 0x00040000 */\n#define PWR_CR1_ALS_LEV2               PWR_CR1_ALS_LEV2_Msk                    /*!< AVD level 2 */\n#define PWR_CR1_ALS_LEV3_Pos           (17U)\n#define PWR_CR1_ALS_LEV3_Msk           (0x3UL << PWR_CR1_ALS_LEV3_Pos)         /*!< 0x00060000 */\n#define PWR_CR1_ALS_LEV3               PWR_CR1_ALS_LEV3_Msk                    /*!< AVD level 3 */\n\n/********************  Bit definition for PWR_CSR1 register  ******************/\n#define PWR_CSR1_AVDO_Pos              (16U)\n#define PWR_CSR1_AVDO_Msk              (0x1UL << PWR_CSR1_AVDO_Pos)            /*!< 0x00010000 */\n#define PWR_CSR1_AVDO                  PWR_CSR1_AVDO_Msk                       /*!< Analog Voltage Detect Output */\n#define PWR_CSR1_ACTVOS_Pos            (14U)\n#define PWR_CSR1_ACTVOS_Msk            (0x3UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x0000C000 */\n#define PWR_CSR1_ACTVOS                PWR_CSR1_ACTVOS_Msk                     /*!< Current actual used VOS for VDD11 Voltage Scaling */\n#define PWR_CSR1_ACTVOS_0              (0x1UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x00004000 */\n#define PWR_CSR1_ACTVOS_1              (0x2UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x00008000 */\n#define PWR_CSR1_ACTVOSRDY_Pos         (13U)\n#define PWR_CSR1_ACTVOSRDY_Msk         (0x1UL << PWR_CSR1_ACTVOSRDY_Pos)       /*!< 0x00002000 */\n#define PWR_CSR1_ACTVOSRDY             PWR_CSR1_ACTVOSRDY_Msk                  /*!< Ready bit for current actual used VOS for VDD11 Voltage Scaling  */\n#define PWR_CSR1_PVDO_Pos              (4U)\n#define PWR_CSR1_PVDO_Msk              (0x1UL << PWR_CSR1_PVDO_Pos)            /*!< 0x00000010 */\n#define PWR_CSR1_PVDO                  PWR_CSR1_PVDO_Msk                       /*!< Programmable Voltage Detect Output */\n\n/********************  Bit definition for PWR_CR2 register  *******************/\n#define PWR_CR2_TEMPH_Pos              (23U)\n#define PWR_CR2_TEMPH_Msk              (0x1UL << PWR_CR2_TEMPH_Pos)            /*!< 0x00800000 */\n#define PWR_CR2_TEMPH                  PWR_CR2_TEMPH_Msk                       /*!< Monitored temperature level above high threshold */\n#define PWR_CR2_TEMPL_Pos              (22U)\n#define PWR_CR2_TEMPL_Msk              (0x1UL << PWR_CR2_TEMPL_Pos)            /*!< 0x00400000 */\n#define PWR_CR2_TEMPL                  PWR_CR2_TEMPL_Msk                       /*!< Monitored temperature level above low threshold */\n#define PWR_CR2_VBATH_Pos              (21U)\n#define PWR_CR2_VBATH_Msk              (0x1UL << PWR_CR2_VBATH_Pos)            /*!< 0x00200000 */\n#define PWR_CR2_VBATH                  PWR_CR2_VBATH_Msk                       /*!< Monitored VBAT level above high threshold */\n#define PWR_CR2_VBATL_Pos              (20U)\n#define PWR_CR2_VBATL_Msk              (0x1UL << PWR_CR2_VBATL_Pos)            /*!< 0x00100000 */\n#define PWR_CR2_VBATL                  PWR_CR2_VBATL_Msk                       /*!< Monitored VBAT level above low threshold */\n#define PWR_CR2_BRRDY_Pos              (16U)\n#define PWR_CR2_BRRDY_Msk              (0x1UL << PWR_CR2_BRRDY_Pos)            /*!< 0x00010000 */\n#define PWR_CR2_BRRDY                  PWR_CR2_BRRDY_Msk                       /*!< Backup regulator ready */\n#define PWR_CR2_MONEN_Pos              (4U)\n#define PWR_CR2_MONEN_Msk              (0x1UL << PWR_CR2_MONEN_Pos)            /*!< 0x00000010 */\n#define PWR_CR2_MONEN                  PWR_CR2_MONEN_Msk                       /*!< VBAT and temperature monitoring enable */\n#define PWR_CR2_BREN_Pos               (0U)\n#define PWR_CR2_BREN_Msk               (0x1UL << PWR_CR2_BREN_Pos)             /*!< 0x00000001 */\n#define PWR_CR2_BREN                   PWR_CR2_BREN_Msk                        /*!< Backup regulator enable */\n\n/********************  Bit definition for PWR_CR3 register  *******************/\n#define PWR_CR3_USB33RDY_Pos           (26U)\n#define PWR_CR3_USB33RDY_Msk           (0x1UL << PWR_CR3_USB33RDY_Pos)         /*!< 0x04000000 */\n#define PWR_CR3_USB33RDY               PWR_CR3_USB33RDY_Msk                    /*!< USB supply ready */\n#define PWR_CR3_USBREGEN_Pos           (25U)\n#define PWR_CR3_USBREGEN_Msk           (0x1UL << PWR_CR3_USBREGEN_Pos)         /*!< 0x02000000 */\n#define PWR_CR3_USBREGEN               PWR_CR3_USBREGEN_Msk                    /*!< USB regulator enable */\n#define PWR_CR3_USB33DEN_Pos           (24U)\n#define PWR_CR3_USB33DEN_Msk           (0x1UL << PWR_CR3_USB33DEN_Pos)         /*!< 0x01000000 */\n#define PWR_CR3_USB33DEN               PWR_CR3_USB33DEN_Msk                    /*!< VDD33_USB voltage level detector enable */\n#define PWR_CR3_VBRS_Pos               (9U)\n#define PWR_CR3_VBRS_Msk               (0x1UL << PWR_CR3_VBRS_Pos)             /*!< 0x00000200 */\n#define PWR_CR3_VBRS                   PWR_CR3_VBRS_Msk                        /*!< VBAT charging resistor selection */\n#define PWR_CR3_VBE_Pos                (8U)\n#define PWR_CR3_VBE_Msk                (0x1UL << PWR_CR3_VBE_Pos)              /*!< 0x00000100 */\n#define PWR_CR3_VBE                    PWR_CR3_VBE_Msk                         /*!< VBAT charging enable */\n#define PWR_CR3_SCUEN_Pos              (2U)\n#define PWR_CR3_SCUEN_Msk              (0x1UL << PWR_CR3_SCUEN_Pos)            /*!< 0x00000004 */\n#define PWR_CR3_SCUEN                  PWR_CR3_SCUEN_Msk                       /*!< Supply configuration update enable */\n#define PWR_CR3_LDOEN_Pos              (1U)\n#define PWR_CR3_LDOEN_Msk              (0x1UL << PWR_CR3_LDOEN_Pos)            /*!< 0x00000002 */\n#define PWR_CR3_LDOEN                  PWR_CR3_LDOEN_Msk                       /*!< Low Drop Output regulator enable */\n#define PWR_CR3_BYPASS_Pos             (0U)\n#define PWR_CR3_BYPASS_Msk             (0x1UL << PWR_CR3_BYPASS_Pos)           /*!< 0x00000001 */\n#define PWR_CR3_BYPASS                 PWR_CR3_BYPASS_Msk                      /*!< Power Management Unit bypass */\n\n/********************  Bit definition for PWR_CPUCR register  *****************/\n#define PWR_CPUCR_RUN_D3_Pos           (11U)\n#define PWR_CPUCR_RUN_D3_Msk           (0x1UL << PWR_CPUCR_RUN_D3_Pos)         /*!< 0x00000800 */\n#define PWR_CPUCR_RUN_D3               PWR_CPUCR_RUN_D3_Msk                    /*!< Keep system D3 domain in RUN mode regardless of the CPU sub-systems modes */\n#define PWR_CPUCR_CSSF_Pos             (9U)\n#define PWR_CPUCR_CSSF_Msk             (0x1UL << PWR_CPUCR_CSSF_Pos)           /*!< 0x00000200 */\n#define PWR_CPUCR_CSSF                 PWR_CPUCR_CSSF_Msk                      /*!< Clear D1 domain CPU1 STANDBY, STOP and HOLD flags */\n#define PWR_CPUCR_SBF_D2_Pos           (8U)\n#define PWR_CPUCR_SBF_D2_Msk           (0x1UL << PWR_CPUCR_SBF_D2_Pos)         /*!< 0x00000100 */\n#define PWR_CPUCR_SBF_D2               PWR_CPUCR_SBF_D2_Msk                    /*!< D2 domain DSTANDBY Flag */\n#define PWR_CPUCR_SBF_D1_Pos           (7U)\n#define PWR_CPUCR_SBF_D1_Msk           (0x1UL << PWR_CPUCR_SBF_D1_Pos)         /*!< 0x00000080 */\n#define PWR_CPUCR_SBF_D1               PWR_CPUCR_SBF_D1_Msk                    /*!< D1 domain DSTANDBY Flag */\n#define PWR_CPUCR_SBF_Pos              (6U)\n#define PWR_CPUCR_SBF_Msk              (0x1UL << PWR_CPUCR_SBF_Pos)            /*!< 0x00000040 */\n#define PWR_CPUCR_SBF                  PWR_CPUCR_SBF_Msk                       /*!< System STANDBY Flag */\n#define PWR_CPUCR_STOPF_Pos            (5U)\n#define PWR_CPUCR_STOPF_Msk            (0x1UL << PWR_CPUCR_STOPF_Pos)          /*!< 0x00000020 */\n#define PWR_CPUCR_STOPF                PWR_CPUCR_STOPF_Msk                     /*!< STOP Flag */\n#define PWR_CPUCR_PDDS_D3_Pos          (2U)\n#define PWR_CPUCR_PDDS_D3_Msk          (0x1UL << PWR_CPUCR_PDDS_D3_Pos)        /*!< 0x00000004 */\n#define PWR_CPUCR_PDDS_D3              PWR_CPUCR_PDDS_D3_Msk                   /*!< System D3 domain Power Down Deepsleep */\n#define PWR_CPUCR_PDDS_D2_Pos          (1U)\n#define PWR_CPUCR_PDDS_D2_Msk          (0x1UL << PWR_CPUCR_PDDS_D2_Pos)        /*!< 0x00000002 */\n#define PWR_CPUCR_PDDS_D2              PWR_CPUCR_PDDS_D2_Msk                   /*!< D2 domain Power Down Deepsleep */\n#define PWR_CPUCR_PDDS_D1_Pos          (0U)\n#define PWR_CPUCR_PDDS_D1_Msk          (0x1UL << PWR_CPUCR_PDDS_D1_Pos)        /*!< 0x00000001 */\n#define PWR_CPUCR_PDDS_D1              PWR_CPUCR_PDDS_D1_Msk                   /*!< D1 domain Power Down Deepsleep selection */\n\n\n/********************  Bit definition for PWR_D3CR register  ******************/\n#define PWR_D3CR_VOS_Pos               (14U)\n#define PWR_D3CR_VOS_Msk               (0x3UL << PWR_D3CR_VOS_Pos)             /*!< 0x0000C000 */\n#define PWR_D3CR_VOS                   PWR_D3CR_VOS_Msk                        /*!< Voltage Scaling selection according performance */\n#define PWR_D3CR_VOS_0                 (0x1UL << PWR_D3CR_VOS_Pos)             /*!< 0x00004000 */\n#define PWR_D3CR_VOS_1                 (0x2UL << PWR_D3CR_VOS_Pos)             /*!< 0x00008000 */\n#define PWR_D3CR_VOSRDY_Pos            (13U)\n#define PWR_D3CR_VOSRDY_Msk            (0x1UL << PWR_D3CR_VOSRDY_Pos)          /*!< 0x00002000 */\n#define PWR_D3CR_VOSRDY                PWR_D3CR_VOSRDY_Msk                     /*!< VOS Ready bit for VDD11 Voltage Scaling output selection */\n\n/******************  Bit definition for PWR_WKUPCR register  ******************/\n#define PWR_WKUPCR_WKUPC6_Pos          (5U)\n#define PWR_WKUPCR_WKUPC6_Msk          (0x1UL << PWR_WKUPCR_WKUPC6_Pos)        /*!< 0x00000020 */\n#define PWR_WKUPCR_WKUPC6              PWR_WKUPCR_WKUPC6_Msk                   /*!< Clear Wakeup Pin Flag 6 */\n#define PWR_WKUPCR_WKUPC5_Pos          (4U)\n#define PWR_WKUPCR_WKUPC5_Msk          (0x1UL << PWR_WKUPCR_WKUPC5_Pos)        /*!< 0x00000010 */\n#define PWR_WKUPCR_WKUPC5              PWR_WKUPCR_WKUPC5_Msk                   /*!< Clear Wakeup Pin Flag 5 */\n#define PWR_WKUPCR_WKUPC4_Pos          (3U)\n#define PWR_WKUPCR_WKUPC4_Msk          (0x1UL << PWR_WKUPCR_WKUPC4_Pos)        /*!< 0x00000008 */\n#define PWR_WKUPCR_WKUPC4              PWR_WKUPCR_WKUPC4_Msk                   /*!< Clear Wakeup Pin Flag 4 */\n#define PWR_WKUPCR_WKUPC3_Pos          (2U)\n#define PWR_WKUPCR_WKUPC3_Msk          (0x1UL << PWR_WKUPCR_WKUPC3_Pos)        /*!< 0x00000004 */\n#define PWR_WKUPCR_WKUPC3              PWR_WKUPCR_WKUPC3_Msk                   /*!< Clear Wakeup Pin Flag 3 */\n#define PWR_WKUPCR_WKUPC2_Pos          (1U)\n#define PWR_WKUPCR_WKUPC2_Msk          (0x1UL << PWR_WKUPCR_WKUPC2_Pos)        /*!< 0x00000002 */\n#define PWR_WKUPCR_WKUPC2              PWR_WKUPCR_WKUPC2_Msk                   /*!< Clear Wakeup Pin Flag 2 */\n#define PWR_WKUPCR_WKUPC1_Pos          (0U)\n#define PWR_WKUPCR_WKUPC1_Msk          (0x1UL << PWR_WKUPCR_WKUPC1_Pos)        /*!< 0x00000001 */\n#define PWR_WKUPCR_WKUPC1              PWR_WKUPCR_WKUPC1_Msk                   /*!< Clear Wakeup Pin Flag 1 */\n\n/********************  Bit definition for PWR_WKUPFR register  ****************/\n#define PWR_WKUPFR_WKUPF6_Pos          (5U)\n#define PWR_WKUPFR_WKUPF6_Msk          (0x1UL << PWR_WKUPFR_WKUPF6_Pos)        /*!< 0x00000020 */\n#define PWR_WKUPFR_WKUPF6              PWR_WKUPFR_WKUPF6_Msk                   /*!< Wakeup Pin Flag 6 */\n#define PWR_WKUPFR_WKUPF5_Pos          (4U)\n#define PWR_WKUPFR_WKUPF5_Msk          (0x1UL << PWR_WKUPFR_WKUPF5_Pos)        /*!< 0x00000010 */\n#define PWR_WKUPFR_WKUPF5              PWR_WKUPFR_WKUPF5_Msk                   /*!< Wakeup Pin Flag 5 */\n#define PWR_WKUPFR_WKUPF4_Pos          (3U)\n#define PWR_WKUPFR_WKUPF4_Msk          (0x1UL << PWR_WKUPFR_WKUPF4_Pos)        /*!< 0x00000008 */\n#define PWR_WKUPFR_WKUPF4              PWR_WKUPFR_WKUPF4_Msk                   /*!< Wakeup Pin Flag 4 */\n#define PWR_WKUPFR_WKUPF3_Pos          (2U)\n#define PWR_WKUPFR_WKUPF3_Msk          (0x1UL << PWR_WKUPFR_WKUPF3_Pos)        /*!< 0x00000004 */\n#define PWR_WKUPFR_WKUPF3              PWR_WKUPFR_WKUPF3_Msk                   /*!< Wakeup Pin Flag 3 */\n#define PWR_WKUPFR_WKUPF2_Pos          (1U)\n#define PWR_WKUPFR_WKUPF2_Msk          (0x1UL << PWR_WKUPFR_WKUPF2_Pos)        /*!< 0x00000002 */\n#define PWR_WKUPFR_WKUPF2              PWR_WKUPFR_WKUPF2_Msk                   /*!< Wakeup Pin Flag 2 */\n#define PWR_WKUPFR_WKUPF1_Pos          (0U)\n#define PWR_WKUPFR_WKUPF1_Msk          (0x1UL << PWR_WKUPFR_WKUPF1_Pos)        /*!< 0x00000001 */\n#define PWR_WKUPFR_WKUPF1              PWR_WKUPFR_WKUPF1_Msk                   /*!< Wakeup Pin Flag 1 */\n\n/******************  Bit definition for PWR_WKUPEPR register  *****************/\n#define PWR_WKUPEPR_WKUPPUPD6_Pos      (26U)\n#define PWR_WKUPEPR_WKUPPUPD6_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x0C000000 */\n#define PWR_WKUPEPR_WKUPPUPD6          PWR_WKUPEPR_WKUPPUPD6_Msk               /*!< Wakeup Pin pull configuration for WKUP6 */\n#define PWR_WKUPEPR_WKUPPUPD6_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x04000000 */\n#define PWR_WKUPEPR_WKUPPUPD6_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x08000000 */\n#define PWR_WKUPEPR_WKUPPUPD5_Pos      (24U)\n#define PWR_WKUPEPR_WKUPPUPD5_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x03000000 */\n#define PWR_WKUPEPR_WKUPPUPD5          PWR_WKUPEPR_WKUPPUPD5_Msk               /*!< Wakeup Pin pull configuration for WKUP5 */\n#define PWR_WKUPEPR_WKUPPUPD5_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x01000000 */\n#define PWR_WKUPEPR_WKUPPUPD5_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x02000000 */\n#define PWR_WKUPEPR_WKUPPUPD4_Pos      (22U)\n#define PWR_WKUPEPR_WKUPPUPD4_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00C00000 */\n#define PWR_WKUPEPR_WKUPPUPD4          PWR_WKUPEPR_WKUPPUPD4_Msk               /*!< Wakeup Pin pull configuration for WKUP4 */\n#define PWR_WKUPEPR_WKUPPUPD4_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00400000 */\n#define PWR_WKUPEPR_WKUPPUPD4_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00800000 */\n#define PWR_WKUPEPR_WKUPPUPD3_Pos      (20U)\n#define PWR_WKUPEPR_WKUPPUPD3_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00300000 */\n#define PWR_WKUPEPR_WKUPPUPD3          PWR_WKUPEPR_WKUPPUPD3_Msk               /*!< Wakeup Pin pull configuration for WKUP3 */\n#define PWR_WKUPEPR_WKUPPUPD3_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00100000 */\n#define PWR_WKUPEPR_WKUPPUPD3_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00200000 */\n#define PWR_WKUPEPR_WKUPPUPD2_Pos      (18U)\n#define PWR_WKUPEPR_WKUPPUPD2_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x000C0000 */\n#define PWR_WKUPEPR_WKUPPUPD2          PWR_WKUPEPR_WKUPPUPD2_Msk               /*!< Wakeup Pin pull configuration for WKUP2 */\n#define PWR_WKUPEPR_WKUPPUPD2_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x00040000 */\n#define PWR_WKUPEPR_WKUPPUPD2_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x00080000 */\n#define PWR_WKUPEPR_WKUPPUPD1_Pos      (16U)\n#define PWR_WKUPEPR_WKUPPUPD1_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00030000 */\n#define PWR_WKUPEPR_WKUPPUPD1          PWR_WKUPEPR_WKUPPUPD1_Msk               /*!< Wakeup Pin pull configuration for WKUP1 */\n#define PWR_WKUPEPR_WKUPPUPD1_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00010000 */\n#define PWR_WKUPEPR_WKUPPUPD1_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00020000 */\n#define PWR_WKUPEPR_WKUPP6_Pos         (13U)\n#define PWR_WKUPEPR_WKUPP6_Msk         (0x1UL << PWR_WKUPEPR_WKUPP6_Pos)       /*!< 0x00002000 */\n#define PWR_WKUPEPR_WKUPP6             PWR_WKUPEPR_WKUPP6_Msk                  /*!< Wakeup Pin Polarity for WKUP6 */\n#define PWR_WKUPEPR_WKUPP5_Pos         (12U)\n#define PWR_WKUPEPR_WKUPP5_Msk         (0x1UL << PWR_WKUPEPR_WKUPP5_Pos)       /*!< 0x00001000 */\n#define PWR_WKUPEPR_WKUPP5             PWR_WKUPEPR_WKUPP5_Msk                  /*!< Wakeup Pin Polarity for WKUP5 */\n#define PWR_WKUPEPR_WKUPP4_Pos         (11U)\n#define PWR_WKUPEPR_WKUPP4_Msk         (0x1UL << PWR_WKUPEPR_WKUPP4_Pos)       /*!< 0x00000800 */\n#define PWR_WKUPEPR_WKUPP4             PWR_WKUPEPR_WKUPP4_Msk                  /*!< Wakeup Pin Polarity for WKUP4 */\n#define PWR_WKUPEPR_WKUPP3_Pos         (10U)\n#define PWR_WKUPEPR_WKUPP3_Msk         (0x1UL << PWR_WKUPEPR_WKUPP3_Pos)       /*!< 0x00000400 */\n#define PWR_WKUPEPR_WKUPP3             PWR_WKUPEPR_WKUPP3_Msk                  /*!< Wakeup Pin Polarity for WKUP3 */\n#define PWR_WKUPEPR_WKUPP2_Pos         (9U)\n#define PWR_WKUPEPR_WKUPP2_Msk         (0x1UL << PWR_WKUPEPR_WKUPP2_Pos)       /*!< 0x00000200 */\n#define PWR_WKUPEPR_WKUPP2             PWR_WKUPEPR_WKUPP2_Msk                  /*!< Wakeup Pin Polarity for WKUP2 */\n#define PWR_WKUPEPR_WKUPP1_Pos         (8U)\n#define PWR_WKUPEPR_WKUPP1_Msk         (0x1UL << PWR_WKUPEPR_WKUPP1_Pos)       /*!< 0x00000100 */\n#define PWR_WKUPEPR_WKUPP1             PWR_WKUPEPR_WKUPP1_Msk                  /*!< Wakeup Pin Polarity for WKUP1 */\n#define PWR_WKUPEPR_WKUPEN6_Pos        (5U)\n#define PWR_WKUPEPR_WKUPEN6_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN6_Pos)      /*!< 0x00000020 */\n#define PWR_WKUPEPR_WKUPEN6            PWR_WKUPEPR_WKUPEN6_Msk                 /*!< Enable Wakeup Pin WKUP6 */\n#define PWR_WKUPEPR_WKUPEN5_Pos        (4U)\n#define PWR_WKUPEPR_WKUPEN5_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN5_Pos)      /*!< 0x00000010 */\n#define PWR_WKUPEPR_WKUPEN5            PWR_WKUPEPR_WKUPEN5_Msk                 /*!< Enable Wakeup Pin WKUP5 */\n#define PWR_WKUPEPR_WKUPEN4_Pos        (3U)\n#define PWR_WKUPEPR_WKUPEN4_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN4_Pos)      /*!< 0x00000008 */\n#define PWR_WKUPEPR_WKUPEN4            PWR_WKUPEPR_WKUPEN4_Msk                 /*!< Enable Wakeup Pin WKUP4 */\n#define PWR_WKUPEPR_WKUPEN3_Pos        (2U)\n#define PWR_WKUPEPR_WKUPEN3_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN3_Pos)      /*!< 0x00000004 */\n#define PWR_WKUPEPR_WKUPEN3            PWR_WKUPEPR_WKUPEN3_Msk                 /*!< Enable Wakeup Pin WKUP3 */\n#define PWR_WKUPEPR_WKUPEN2_Pos        (1U)\n#define PWR_WKUPEPR_WKUPEN2_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN2_Pos)      /*!< 0x00000002 */\n#define PWR_WKUPEPR_WKUPEN2            PWR_WKUPEPR_WKUPEN2_Msk                 /*!< Enable Wakeup Pin WKUP2 */\n#define PWR_WKUPEPR_WKUPEN1_Pos        (0U)\n#define PWR_WKUPEPR_WKUPEN1_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN1_Pos)      /*!< 0x00000001 */\n#define PWR_WKUPEPR_WKUPEN1            PWR_WKUPEPR_WKUPEN1_Msk                 /*!< Enable Wakeup Pin WKUP1 */\n#define PWR_WKUPEPR_WKUPEN_Pos         (0U)\n#define PWR_WKUPEPR_WKUPEN_Msk         (0x3FUL << PWR_WKUPEPR_WKUPEN_Pos)      /*!< 0x0000003F */\n#define PWR_WKUPEPR_WKUPEN             PWR_WKUPEPR_WKUPEN_Msk                  /*!< Enable all Wakeup Pin */\n\n/******************************************************************************/\n/*                                                                            */\n/*                         Reset and Clock Control                            */\n/*                                                                            */\n/******************************************************************************/\n/*******************************  RCC VERSION  ********************************/\n#define RCC_VER_X\n\n/********************  Bit definition for RCC_CR register  ********************/\n#define RCC_CR_HSION_Pos                       (0U)\n#define RCC_CR_HSION_Msk                       (0x1UL << RCC_CR_HSION_Pos)     /*!< 0x00000001 */\n#define RCC_CR_HSION                           RCC_CR_HSION_Msk                /*!< Internal High Speed clock enable */\n#define RCC_CR_HSIKERON_Pos                    (1U)\n#define RCC_CR_HSIKERON_Msk                    (0x1UL << RCC_CR_HSIKERON_Pos)  /*!< 0x00000002 */\n#define RCC_CR_HSIKERON                        RCC_CR_HSIKERON_Msk             /*!< Internal High Speed clock enable for some IPs Kernel */\n#define RCC_CR_HSIRDY_Pos                      (2U)\n#define RCC_CR_HSIRDY_Msk                      (0x1UL << RCC_CR_HSIRDY_Pos)    /*!< 0x00000004 */\n#define RCC_CR_HSIRDY                          RCC_CR_HSIRDY_Msk               /*!< Internal High Speed clock ready flag */\n#define RCC_CR_HSIDIV_Pos                      (3U)\n#define RCC_CR_HSIDIV_Msk                      (0x3UL << RCC_CR_HSIDIV_Pos)    /*!< 0x00000018 */\n#define RCC_CR_HSIDIV                          RCC_CR_HSIDIV_Msk               /*!< Internal High Speed clock divider selection */\n#define RCC_CR_HSIDIV_1                        (0x0UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000000 */\n#define RCC_CR_HSIDIV_2                        (0x1UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000008 */\n#define RCC_CR_HSIDIV_4                        (0x2UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000010 */\n#define RCC_CR_HSIDIV_8                        (0x3UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000018 */\n\n#define RCC_CR_HSIDIVF_Pos                     (5U)\n#define RCC_CR_HSIDIVF_Msk                     (0x1UL << RCC_CR_HSIDIVF_Pos)   /*!< 0x00000020 */\n#define RCC_CR_HSIDIVF                         RCC_CR_HSIDIVF_Msk              /*!< HSI Divider flag */\n#define RCC_CR_CSION_Pos                       (7U)\n#define RCC_CR_CSION_Msk                       (0x1UL << RCC_CR_CSION_Pos)     /*!< 0x00000080 */\n#define RCC_CR_CSION                           RCC_CR_CSION_Msk                /*!< The Internal RC 4MHz oscillator clock enable */\n#define RCC_CR_CSIRDY_Pos                      (8U)\n#define RCC_CR_CSIRDY_Msk                      (0x1UL << RCC_CR_CSIRDY_Pos)    /*!< 0x00000100 */\n#define RCC_CR_CSIRDY                          RCC_CR_CSIRDY_Msk               /*!< The Internal RC 4MHz oscillator clock ready */\n#define RCC_CR_CSIKERON_Pos                    (9U)\n#define RCC_CR_CSIKERON_Msk                    (0x1UL << RCC_CR_CSIKERON_Pos)  /*!< 0x00000200 */\n#define RCC_CR_CSIKERON                        RCC_CR_CSIKERON_Msk             /*!< Internal RC 4MHz oscillator clock enable for some IPs Kernel */\n#define RCC_CR_HSI48ON_Pos                     (12U)\n#define RCC_CR_HSI48ON_Msk                     (0x1UL << RCC_CR_HSI48ON_Pos)   /*!< 0x00001000 */\n#define RCC_CR_HSI48ON                         RCC_CR_HSI48ON_Msk              /*!< HSI48 clock enable clock enable  */\n#define RCC_CR_HSI48RDY_Pos                    (13U)\n#define RCC_CR_HSI48RDY_Msk                    (0x1UL << RCC_CR_HSI48RDY_Pos)  /*!< 0x00002000 */\n#define RCC_CR_HSI48RDY                        RCC_CR_HSI48RDY_Msk             /*!< HSI48 clock ready */\n\n#define RCC_CR_D1CKRDY_Pos                     (14U)\n#define RCC_CR_D1CKRDY_Msk                     (0x1UL << RCC_CR_D1CKRDY_Pos)   /*!< 0x00004000 */\n#define RCC_CR_D1CKRDY                         RCC_CR_D1CKRDY_Msk              /*!< D1 domain clocks ready flag  */\n#define RCC_CR_D2CKRDY_Pos                     (15U)\n#define RCC_CR_D2CKRDY_Msk                     (0x1UL << RCC_CR_D2CKRDY_Pos)   /*!< 0x00008000 */\n#define RCC_CR_D2CKRDY                         RCC_CR_D2CKRDY_Msk              /*!< D2 domain clocks ready flag */\n\n#define RCC_CR_HSEON_Pos                       (16U)\n#define RCC_CR_HSEON_Msk                       (0x1UL << RCC_CR_HSEON_Pos)     /*!< 0x00010000 */\n#define RCC_CR_HSEON                           RCC_CR_HSEON_Msk                /*!< External High Speed clock enable */\n#define RCC_CR_HSERDY_Pos                      (17U)\n#define RCC_CR_HSERDY_Msk                      (0x1UL << RCC_CR_HSERDY_Pos)    /*!< 0x00020000 */\n#define RCC_CR_HSERDY                          RCC_CR_HSERDY_Msk               /*!< External High Speed clock ready */\n#define RCC_CR_HSEBYP_Pos                      (18U)\n#define RCC_CR_HSEBYP_Msk                      (0x1UL << RCC_CR_HSEBYP_Pos)    /*!< 0x00040000 */\n#define RCC_CR_HSEBYP                          RCC_CR_HSEBYP_Msk               /*!< External High Speed clock Bypass */\n#define RCC_CR_CSSHSEON_Pos                    (19U)\n#define RCC_CR_CSSHSEON_Msk                    (0x1UL << RCC_CR_CSSHSEON_Pos)  /*!< 0x00080000 */\n#define RCC_CR_CSSHSEON                        RCC_CR_CSSHSEON_Msk             /*!< HSE Clock security System enable */\n\n\n#define RCC_CR_PLL1ON_Pos                      (24U)\n#define RCC_CR_PLL1ON_Msk                      (0x1UL << RCC_CR_PLL1ON_Pos)    /*!< 0x01000000 */\n#define RCC_CR_PLL1ON                          RCC_CR_PLL1ON_Msk               /*!< System PLL1 clock enable */\n#define RCC_CR_PLL1RDY_Pos                     (25U)\n#define RCC_CR_PLL1RDY_Msk                     (0x1UL << RCC_CR_PLL1RDY_Pos)   /*!< 0x02000000 */\n#define RCC_CR_PLL1RDY                         RCC_CR_PLL1RDY_Msk              /*!< System PLL1 clock ready */\n#define RCC_CR_PLL2ON_Pos                      (26U)\n#define RCC_CR_PLL2ON_Msk                      (0x1UL << RCC_CR_PLL2ON_Pos)    /*!< 0x04000000 */\n#define RCC_CR_PLL2ON                          RCC_CR_PLL2ON_Msk               /*!< System PLL2 clock enable */\n#define RCC_CR_PLL2RDY_Pos                     (27U)\n#define RCC_CR_PLL2RDY_Msk                     (0x1UL << RCC_CR_PLL2RDY_Pos)   /*!< 0x08000000 */\n#define RCC_CR_PLL2RDY                         RCC_CR_PLL2RDY_Msk              /*!< System PLL2 clock ready */\n#define RCC_CR_PLL3ON_Pos                      (28U)\n#define RCC_CR_PLL3ON_Msk                      (0x1UL << RCC_CR_PLL3ON_Pos)    /*!< 0x10000000 */\n#define RCC_CR_PLL3ON                          RCC_CR_PLL3ON_Msk               /*!< System PLL3 clock enable */\n#define RCC_CR_PLL3RDY_Pos                     (29U)\n#define RCC_CR_PLL3RDY_Msk                     (0x1UL << RCC_CR_PLL3RDY_Pos)   /*!< 0x20000000 */\n#define RCC_CR_PLL3RDY                         RCC_CR_PLL3RDY_Msk              /*!< System PLL3 clock ready */\n\n/*Legacy */\n#define RCC_CR_PLLON_Pos                       (24U)\n#define RCC_CR_PLLON_Msk                       (0x1UL << RCC_CR_PLLON_Pos)     /*!< 0x01000000 */\n#define RCC_CR_PLLON                           RCC_CR_PLLON_Msk                /*!< System PLL clock enable */\n#define RCC_CR_PLLRDY_Pos                      (25U)\n#define RCC_CR_PLLRDY_Msk                      (0x1UL << RCC_CR_PLLRDY_Pos)    /*!< 0x02000000 */\n#define RCC_CR_PLLRDY                          RCC_CR_PLLRDY_Msk               /*!< System PLL clock ready */\n\n/********************  Bit definition for RCC_HSICFGR register  ***************/\n/*!< HSICAL configuration */\n#define RCC_HSICFGR_HSICAL_Pos                 (0U)\n#define RCC_HSICFGR_HSICAL_Msk                 (0xFFFUL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000FFF */\n#define RCC_HSICFGR_HSICAL                     RCC_HSICFGR_HSICAL_Msk          /*!< HSICAL[11:0] bits */\n#define RCC_HSICFGR_HSICAL_0                   (0x001UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000001 */\n#define RCC_HSICFGR_HSICAL_1                   (0x002UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000002 */\n#define RCC_HSICFGR_HSICAL_2                   (0x004UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000004 */\n#define RCC_HSICFGR_HSICAL_3                   (0x008UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000008 */\n#define RCC_HSICFGR_HSICAL_4                   (0x010UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000010 */\n#define RCC_HSICFGR_HSICAL_5                   (0x020UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000020 */\n#define RCC_HSICFGR_HSICAL_6                   (0x040UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000040 */\n#define RCC_HSICFGR_HSICAL_7                   (0x080UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000080 */\n#define RCC_HSICFGR_HSICAL_8                   (0x100UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000100 */\n#define RCC_HSICFGR_HSICAL_9                   (0x200UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000200 */\n#define RCC_HSICFGR_HSICAL_10                  (0x400UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000400 */\n#define RCC_HSICFGR_HSICAL_11                  (0x800UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000800 */\n\n/*!< HSITRIM configuration */\n#define RCC_HSICFGR_HSITRIM_Pos                (24U)\n#define RCC_HSICFGR_HSITRIM_Msk                (0x7FUL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x7F000000 */\n#define RCC_HSICFGR_HSITRIM                    RCC_HSICFGR_HSITRIM_Msk         /*!< HSITRIM[6:0] bits */\n#define RCC_HSICFGR_HSITRIM_0                  (0x01UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x01000000 */\n#define RCC_HSICFGR_HSITRIM_1                  (0x02UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x02000000 */\n#define RCC_HSICFGR_HSITRIM_2                  (0x04UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x04000000 */\n#define RCC_HSICFGR_HSITRIM_3                  (0x08UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x08000000 */\n#define RCC_HSICFGR_HSITRIM_4                  (0x10UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x10000000 */\n#define RCC_HSICFGR_HSITRIM_5                  (0x20UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x20000000 */\n#define RCC_HSICFGR_HSITRIM_6                  (0x40UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x40000000 */\n\n\n/********************  Bit definition for RCC_CRRCR register  *****************/\n\n/*!< HSI48CAL configuration */\n#define RCC_CRRCR_HSI48CAL_Pos                 (0U)\n#define RCC_CRRCR_HSI48CAL_Msk                 (0x3FFUL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x000003FF */\n#define RCC_CRRCR_HSI48CAL                     RCC_CRRCR_HSI48CAL_Msk          /*!< HSI48CAL[9:0] bits */\n#define RCC_CRRCR_HSI48CAL_0                   (0x001UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000001 */\n#define RCC_CRRCR_HSI48CAL_1                   (0x002UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000002 */\n#define RCC_CRRCR_HSI48CAL_2                   (0x004UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000004 */\n#define RCC_CRRCR_HSI48CAL_3                   (0x008UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000008 */\n#define RCC_CRRCR_HSI48CAL_4                   (0x010UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000010 */\n#define RCC_CRRCR_HSI48CAL_5                   (0x020UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000020 */\n#define RCC_CRRCR_HSI48CAL_6                   (0x040UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000040 */\n#define RCC_CRRCR_HSI48CAL_7                   (0x080UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000080 */\n#define RCC_CRRCR_HSI48CAL_8                   (0x100UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000100 */\n#define RCC_CRRCR_HSI48CAL_9                   (0x200UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000200 */\n\n\n/********************  Bit definition for RCC_CSICFGR register  *****************/\n/*!< CSICAL configuration */\n#define RCC_CSICFGR_CSICAL_Pos                 (0U)\n#define RCC_CSICFGR_CSICAL_Msk                 (0xFFUL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x000000FF */\n#define RCC_CSICFGR_CSICAL                     RCC_CSICFGR_CSICAL_Msk          /*!< CSICAL[7:0] bits */\n#define RCC_CSICFGR_CSICAL_0                   (0x01UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000001 */\n#define RCC_CSICFGR_CSICAL_1                   (0x02UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000002 */\n#define RCC_CSICFGR_CSICAL_2                   (0x04UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000004 */\n#define RCC_CSICFGR_CSICAL_3                   (0x08UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000008 */\n#define RCC_CSICFGR_CSICAL_4                   (0x10UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000010 */\n#define RCC_CSICFGR_CSICAL_5                   (0x20UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000020 */\n#define RCC_CSICFGR_CSICAL_6                   (0x40UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000040 */\n#define RCC_CSICFGR_CSICAL_7                   (0x80UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000080 */\n\n/*!< CSITRIM configuration */\n#define RCC_CSICFGR_CSITRIM_Pos                (24U)\n#define RCC_CSICFGR_CSITRIM_Msk                (0x3FUL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x3F000000 */\n#define RCC_CSICFGR_CSITRIM                    RCC_CSICFGR_CSITRIM_Msk         /*!< CSITRIM[5:0] bits */\n#define RCC_CSICFGR_CSITRIM_0                  (0x01UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x01000000 */\n#define RCC_CSICFGR_CSITRIM_1                  (0x02UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x02000000 */\n#define RCC_CSICFGR_CSITRIM_2                  (0x04UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x04000000 */\n#define RCC_CSICFGR_CSITRIM_3                  (0x08UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x08000000 */\n#define RCC_CSICFGR_CSITRIM_4                  (0x10UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x10000000 */\n#define RCC_CSICFGR_CSITRIM_5                  (0x20UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x20000000 */\n\n/********************  Bit definition for RCC_CFGR register  ******************/\n/*!< SW configuration */\n#define RCC_CFGR_SW_Pos                        (0U)\n#define RCC_CFGR_SW_Msk                        (0x7UL << RCC_CFGR_SW_Pos)           /*!< 0x00000007 */\n#define RCC_CFGR_SW                            RCC_CFGR_SW_Msk                     /*!< SW[2:0] bits (System clock Switch) */\n#define RCC_CFGR_SW_0                          (0x1UL << RCC_CFGR_SW_Pos)           /*!< 0x00000001 */\n#define RCC_CFGR_SW_1                          (0x2UL << RCC_CFGR_SW_Pos)           /*!< 0x00000002 */\n#define RCC_CFGR_SW_2                          (0x4UL << RCC_CFGR_SW_Pos)           /*!< 0x00000004 */\n\n#define RCC_CFGR_SW_HSI                        (0x00000000UL)                       /*!< HSI selection as system clock */\n#define RCC_CFGR_SW_CSI                        (0x00000001UL)                       /*!< CSI selection as system clock */\n#define RCC_CFGR_SW_HSE                        (0x00000002UL)                       /*!< HSE selection as system clock */\n#define RCC_CFGR_SW_PLL1                       (0x00000003UL)                       /*!< PLL1 selection as system clock */\n\n/*!< SWS configuration */\n#define RCC_CFGR_SWS_Pos                       (3U)\n#define RCC_CFGR_SWS_Msk                       (0x7UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000038 */\n#define RCC_CFGR_SWS                           RCC_CFGR_SWS_Msk                    /*!< SWS[2:0] bits (System Clock Switch Status) */\n#define RCC_CFGR_SWS_0                         (0x1UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000008 */\n#define RCC_CFGR_SWS_1                         (0x2UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000010 */\n#define RCC_CFGR_SWS_2                         (0x4UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000020 */\n\n#define RCC_CFGR_SWS_HSI                       (0x00000000UL)                       /*!< HSI used as system clock */\n#define RCC_CFGR_SWS_CSI                       (0x00000008UL)                       /*!< CSI used as system clock */\n#define RCC_CFGR_SWS_HSE                       (0x00000010UL)                       /*!< HSE used as system clock */\n#define RCC_CFGR_SWS_PLL1                      (0x00000018UL)                       /*!< PLL1 used as system clock */\n\n#define RCC_CFGR_STOPWUCK_Pos                  (6U)\n#define RCC_CFGR_STOPWUCK_Msk                  (0x1UL << RCC_CFGR_STOPWUCK_Pos)     /*!< 0x00000040 */\n#define RCC_CFGR_STOPWUCK                      RCC_CFGR_STOPWUCK_Msk                /*!< Wake Up from stop and CSS backup clock selection */\n\n#define RCC_CFGR_STOPKERWUCK_Pos               (7U)\n#define RCC_CFGR_STOPKERWUCK_Msk               (0x1UL << RCC_CFGR_STOPKERWUCK_Pos)  /*!< 0x00000080 */\n#define RCC_CFGR_STOPKERWUCK                   RCC_CFGR_STOPKERWUCK_Msk             /*!< Kernel Clock Selection after a Wake Up from STOP */\n\n/*!< RTCPRE configuration */\n#define RCC_CFGR_RTCPRE_Pos                    (8U)\n#define RCC_CFGR_RTCPRE_Msk                    (0x3FUL << RCC_CFGR_RTCPRE_Pos)\n#define RCC_CFGR_RTCPRE                        RCC_CFGR_RTCPRE_Msk                  /*!< 0x00003F00 */\n#define RCC_CFGR_RTCPRE_0                      (0x1UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000100 */\n#define RCC_CFGR_RTCPRE_1                      (0x2UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000200 */\n#define RCC_CFGR_RTCPRE_2                      (0x4UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000400 */\n#define RCC_CFGR_RTCPRE_3                      (0x8UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000800 */\n#define RCC_CFGR_RTCPRE_4                      (0x10UL << RCC_CFGR_RTCPRE_Pos)       /*!< 0x00001000 */\n#define RCC_CFGR_RTCPRE_5                      (0x20UL << RCC_CFGR_RTCPRE_Pos)       /*!< 0x00002000 */\n\n/*!< HRTIMSEL configuration */\n#define RCC_CFGR_HRTIMSEL_Pos                  (14U)\n#define RCC_CFGR_HRTIMSEL_Msk                  (0x1UL << RCC_CFGR_HRTIMSEL_Pos)\n#define RCC_CFGR_HRTIMSEL                      RCC_CFGR_HRTIMSEL_Msk                /*!< 0x00004000 */\n\n/*!< TIMPRE configuration */\n#define RCC_CFGR_TIMPRE_Pos                    (15U)\n#define RCC_CFGR_TIMPRE_Msk                    (0x1UL << RCC_CFGR_TIMPRE_Pos)\n#define RCC_CFGR_TIMPRE                        RCC_CFGR_TIMPRE_Msk                  /*!< 0x00008000 */\n\n/*!< MCO1 configuration */\n#define RCC_CFGR_MCO1_Pos                      (22U)\n#define RCC_CFGR_MCO1_Msk                      (0x7UL << RCC_CFGR_MCO1_Pos)\n#define RCC_CFGR_MCO1                          RCC_CFGR_MCO1_Msk                       /*!< 0x01C00000 */\n#define RCC_CFGR_MCO1_0                        (0x1UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x00400000 */\n#define RCC_CFGR_MCO1_1                        (0x2UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x00800000 */\n#define RCC_CFGR_MCO1_2                        (0x4UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x01000000 */\n\n#define RCC_CFGR_MCO1PRE_Pos                   (18U)\n#define RCC_CFGR_MCO1PRE_Msk                   (0xFUL << RCC_CFGR_MCO1PRE_Pos)\n#define RCC_CFGR_MCO1PRE                       RCC_CFGR_MCO1PRE_Msk                    /*!< 0x003C0000 */\n#define RCC_CFGR_MCO1PRE_0                     (0x1UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00040000 */\n#define RCC_CFGR_MCO1PRE_1                     (0x2UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00080000 */\n#define RCC_CFGR_MCO1PRE_2                     (0x4UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00100000 */\n#define RCC_CFGR_MCO1PRE_3                     (0x8UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00200000 */\n\n#define RCC_CFGR_MCO2PRE_Pos                   (25U)\n#define RCC_CFGR_MCO2PRE_Msk                   (0xFUL << RCC_CFGR_MCO2PRE_Pos)\n#define RCC_CFGR_MCO2PRE                       RCC_CFGR_MCO2PRE_Msk                    /*!< 0x1E000000 */\n#define RCC_CFGR_MCO2PRE_0                     (0x1UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x02000000 */\n#define RCC_CFGR_MCO2PRE_1                     (0x2UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x04000000 */\n#define RCC_CFGR_MCO2PRE_2                     (0x4UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x08000000 */\n#define RCC_CFGR_MCO2PRE_3                     (0x8UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x10000000 */\n\n#define RCC_CFGR_MCO2_Pos                      (29U)\n#define RCC_CFGR_MCO2_Msk                      (0x7UL << RCC_CFGR_MCO2_Pos)\n#define RCC_CFGR_MCO2                          RCC_CFGR_MCO2_Msk                       /*!< 0xE0000000 */\n#define RCC_CFGR_MCO2_0                        (0x1UL << RCC_CFGR_MCO2_Pos)             /*!< 0x20000000 */\n#define RCC_CFGR_MCO2_1                        (0x2UL << RCC_CFGR_MCO2_Pos)             /*!< 0x40000000 */\n#define RCC_CFGR_MCO2_2                        (0x4UL << RCC_CFGR_MCO2_Pos)             /*!< 0x80000000 */\n\n/********************  Bit definition for RCC_D1CFGR register  ******************/\n/*!< D1HPRE configuration */\n#define RCC_D1CFGR_HPRE_Pos                    (0U)\n#define RCC_D1CFGR_HPRE_Msk                    (0xFUL << RCC_D1CFGR_HPRE_Pos)  /*!< 0x0000000F */\n#define RCC_D1CFGR_HPRE                        RCC_D1CFGR_HPRE_Msk             /*!< HPRE[3:0] bits (AHB3 prescaler) */\n#define RCC_D1CFGR_HPRE_0                      (0x1UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000001 */\n#define RCC_D1CFGR_HPRE_1                      (0x2UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000002 */\n#define RCC_D1CFGR_HPRE_2                      (0x4UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000004 */\n#define RCC_D1CFGR_HPRE_3                      (0x8UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000008 */\n\n\n#define RCC_D1CFGR_HPRE_DIV1                   ((uint32_t)0x00000000)          /*!< AHB3 Clock not divided */\n#define RCC_D1CFGR_HPRE_DIV2_Pos               (3U)\n#define RCC_D1CFGR_HPRE_DIV2_Msk               (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */\n#define RCC_D1CFGR_HPRE_DIV2                   RCC_D1CFGR_HPRE_DIV2_Msk        /*!< AHB3 Clock divided by 2 */\n#define RCC_D1CFGR_HPRE_DIV4_Pos               (0U)\n#define RCC_D1CFGR_HPRE_DIV4_Msk               (0x9UL << RCC_D1CFGR_HPRE_DIV4_Pos) /*!< 0x00000009 */\n#define RCC_D1CFGR_HPRE_DIV4                   RCC_D1CFGR_HPRE_DIV4_Msk        /*!< AHB3 Clock divided by 4 */\n#define RCC_D1CFGR_HPRE_DIV8_Pos               (1U)\n#define RCC_D1CFGR_HPRE_DIV8_Msk               (0x5UL << RCC_D1CFGR_HPRE_DIV8_Pos) /*!< 0x0000000A */\n#define RCC_D1CFGR_HPRE_DIV8                   RCC_D1CFGR_HPRE_DIV8_Msk        /*!< AHB3 Clock divided by 8 */\n#define RCC_D1CFGR_HPRE_DIV16_Pos              (0U)\n#define RCC_D1CFGR_HPRE_DIV16_Msk              (0xBUL << RCC_D1CFGR_HPRE_DIV16_Pos) /*!< 0x0000000B */\n#define RCC_D1CFGR_HPRE_DIV16                  RCC_D1CFGR_HPRE_DIV16_Msk       /*!< AHB3 Clock divided by 16 */\n#define RCC_D1CFGR_HPRE_DIV64_Pos              (2U)\n#define RCC_D1CFGR_HPRE_DIV64_Msk              (0x3UL << RCC_D1CFGR_HPRE_DIV64_Pos) /*!< 0x0000000C */\n#define RCC_D1CFGR_HPRE_DIV64                  RCC_D1CFGR_HPRE_DIV64_Msk       /*!< AHB3 Clock divided by 64 */\n#define RCC_D1CFGR_HPRE_DIV128_Pos             (0U)\n#define RCC_D1CFGR_HPRE_DIV128_Msk             (0xDUL << RCC_D1CFGR_HPRE_DIV128_Pos) /*!< 0x0000000D */\n#define RCC_D1CFGR_HPRE_DIV128                 RCC_D1CFGR_HPRE_DIV128_Msk      /*!< AHB3 Clock divided by 128 */\n#define RCC_D1CFGR_HPRE_DIV256_Pos             (1U)\n#define RCC_D1CFGR_HPRE_DIV256_Msk             (0x7UL << RCC_D1CFGR_HPRE_DIV256_Pos) /*!< 0x0000000E */\n#define RCC_D1CFGR_HPRE_DIV256                 RCC_D1CFGR_HPRE_DIV256_Msk      /*!< AHB3 Clock divided by 256 */\n#define RCC_D1CFGR_HPRE_DIV512_Pos             (0U)\n#define RCC_D1CFGR_HPRE_DIV512_Msk             (0xFUL << RCC_D1CFGR_HPRE_DIV512_Pos) /*!< 0x0000000F */\n#define RCC_D1CFGR_HPRE_DIV512                 RCC_D1CFGR_HPRE_DIV512_Msk      /*!< AHB3 Clock divided by 512 */\n\n/*!< D1PPRE configuration */\n#define RCC_D1CFGR_D1PPRE_Pos                  (4U)\n#define RCC_D1CFGR_D1PPRE_Msk                  (0x7UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000070 */\n#define RCC_D1CFGR_D1PPRE                      RCC_D1CFGR_D1PPRE_Msk           /*!< D1PRE[2:0] bits (APB3 prescaler) */\n#define RCC_D1CFGR_D1PPRE_0                    (0x1UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000010 */\n#define RCC_D1CFGR_D1PPRE_1                    (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */\n#define RCC_D1CFGR_D1PPRE_2                    (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */\n\n#define RCC_D1CFGR_D1PPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB3 clock not divided */\n#define RCC_D1CFGR_D1PPRE_DIV2_Pos             (6U)\n#define RCC_D1CFGR_D1PPRE_DIV2_Msk             (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */\n#define RCC_D1CFGR_D1PPRE_DIV2                 RCC_D1CFGR_D1PPRE_DIV2_Msk      /*!< APB3 clock divided by 2 */\n#define RCC_D1CFGR_D1PPRE_DIV4_Pos             (4U)\n#define RCC_D1CFGR_D1PPRE_DIV4_Msk             (0x5UL << RCC_D1CFGR_D1PPRE_DIV4_Pos) /*!< 0x00000050 */\n#define RCC_D1CFGR_D1PPRE_DIV4                 RCC_D1CFGR_D1PPRE_DIV4_Msk      /*!< APB3 clock divided by 4 */\n#define RCC_D1CFGR_D1PPRE_DIV8_Pos             (5U)\n#define RCC_D1CFGR_D1PPRE_DIV8_Msk             (0x3UL << RCC_D1CFGR_D1PPRE_DIV8_Pos) /*!< 0x00000060 */\n#define RCC_D1CFGR_D1PPRE_DIV8                 RCC_D1CFGR_D1PPRE_DIV8_Msk      /*!< APB3 clock divided by 8 */\n#define RCC_D1CFGR_D1PPRE_DIV16_Pos            (4U)\n#define RCC_D1CFGR_D1PPRE_DIV16_Msk            (0x7UL << RCC_D1CFGR_D1PPRE_DIV16_Pos) /*!< 0x00000070 */\n#define RCC_D1CFGR_D1PPRE_DIV16                RCC_D1CFGR_D1PPRE_DIV16_Msk     /*!< APB3 clock divided by 16 */\n\n#define RCC_D1CFGR_D1CPRE_Pos                  (8U)\n#define RCC_D1CFGR_D1CPRE_Msk                  (0xFUL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000F00 */\n#define RCC_D1CFGR_D1CPRE                      RCC_D1CFGR_D1CPRE_Msk           /*!< D1CPRE[2:0] bits (Domain 1 Core prescaler) */\n#define RCC_D1CFGR_D1CPRE_0                    (0x1UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000100 */\n#define RCC_D1CFGR_D1CPRE_1                    (0x2UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000200 */\n#define RCC_D1CFGR_D1CPRE_2                    (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */\n#define RCC_D1CFGR_D1CPRE_3                    (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */\n\n#define RCC_D1CFGR_D1CPRE_DIV1                 ((uint32_t)0x00000000)          /*!< Domain 1 Core clock not divided */\n#define RCC_D1CFGR_D1CPRE_DIV2_Pos             (11U)\n#define RCC_D1CFGR_D1CPRE_DIV2_Msk             (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */\n#define RCC_D1CFGR_D1CPRE_DIV2                 RCC_D1CFGR_D1CPRE_DIV2_Msk      /*!< Domain 1 Core clock divided by 2 */\n#define RCC_D1CFGR_D1CPRE_DIV4_Pos             (8U)\n#define RCC_D1CFGR_D1CPRE_DIV4_Msk             (0x9UL << RCC_D1CFGR_D1CPRE_DIV4_Pos) /*!< 0x00000900 */\n#define RCC_D1CFGR_D1CPRE_DIV4                 RCC_D1CFGR_D1CPRE_DIV4_Msk      /*!< Domain 1 Core clock divided by 4 */\n#define RCC_D1CFGR_D1CPRE_DIV8_Pos             (9U)\n#define RCC_D1CFGR_D1CPRE_DIV8_Msk             (0x5UL << RCC_D1CFGR_D1CPRE_DIV8_Pos) /*!< 0x00000A00 */\n#define RCC_D1CFGR_D1CPRE_DIV8                 RCC_D1CFGR_D1CPRE_DIV8_Msk      /*!< Domain 1 Core clock divided by 8 */\n#define RCC_D1CFGR_D1CPRE_DIV16_Pos            (8U)\n#define RCC_D1CFGR_D1CPRE_DIV16_Msk            (0xBUL << RCC_D1CFGR_D1CPRE_DIV16_Pos) /*!< 0x00000B00 */\n#define RCC_D1CFGR_D1CPRE_DIV16                RCC_D1CFGR_D1CPRE_DIV16_Msk     /*!< Domain 1 Core clock divided by 16 */\n#define RCC_D1CFGR_D1CPRE_DIV64_Pos            (10U)\n#define RCC_D1CFGR_D1CPRE_DIV64_Msk            (0x3UL << RCC_D1CFGR_D1CPRE_DIV64_Pos) /*!< 0x00000C00 */\n#define RCC_D1CFGR_D1CPRE_DIV64                RCC_D1CFGR_D1CPRE_DIV64_Msk     /*!< Domain 1 Core clock divided by 64 */\n#define RCC_D1CFGR_D1CPRE_DIV128_Pos           (8U)\n#define RCC_D1CFGR_D1CPRE_DIV128_Msk           (0xDUL << RCC_D1CFGR_D1CPRE_DIV128_Pos) /*!< 0x00000D00 */\n#define RCC_D1CFGR_D1CPRE_DIV128               RCC_D1CFGR_D1CPRE_DIV128_Msk    /*!< Domain 1 Core clock divided by 128 */\n#define RCC_D1CFGR_D1CPRE_DIV256_Pos           (9U)\n#define RCC_D1CFGR_D1CPRE_DIV256_Msk           (0x7UL << RCC_D1CFGR_D1CPRE_DIV256_Pos) /*!< 0x00000E00 */\n#define RCC_D1CFGR_D1CPRE_DIV256               RCC_D1CFGR_D1CPRE_DIV256_Msk    /*!< Domain 1 Core clock divided by 256 */\n#define RCC_D1CFGR_D1CPRE_DIV512_Pos           (8U)\n#define RCC_D1CFGR_D1CPRE_DIV512_Msk           (0xFUL << RCC_D1CFGR_D1CPRE_DIV512_Pos) /*!< 0x00000F00 */\n#define RCC_D1CFGR_D1CPRE_DIV512               RCC_D1CFGR_D1CPRE_DIV512_Msk    /*!< Domain 1 Core clock divided by 512 */\n\n/********************  Bit definition for RCC_D2CFGR register  ******************/\n/*!< D2PPRE1 configuration */\n#define RCC_D2CFGR_D2PPRE1_Pos                 (4U)\n#define RCC_D2CFGR_D2PPRE1_Msk                 (0x7UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000070 */\n#define RCC_D2CFGR_D2PPRE1                     RCC_D2CFGR_D2PPRE1_Msk          /*!< D1PPRE1[2:0] bits (APB1 prescaler) */\n#define RCC_D2CFGR_D2PPRE1_0                   (0x1UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000010 */\n#define RCC_D2CFGR_D2PPRE1_1                   (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */\n#define RCC_D2CFGR_D2PPRE1_2                   (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */\n\n#define RCC_D2CFGR_D2PPRE1_DIV1                ((uint32_t)0x00000000)          /*!< APB1 clock not divided */\n#define RCC_D2CFGR_D2PPRE1_DIV2_Pos            (6U)\n#define RCC_D2CFGR_D2PPRE1_DIV2_Msk            (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */\n#define RCC_D2CFGR_D2PPRE1_DIV2                RCC_D2CFGR_D2PPRE1_DIV2_Msk     /*!< APB1 clock divided by 2 */\n#define RCC_D2CFGR_D2PPRE1_DIV4_Pos            (4U)\n#define RCC_D2CFGR_D2PPRE1_DIV4_Msk            (0x5UL << RCC_D2CFGR_D2PPRE1_DIV4_Pos) /*!< 0x00000050 */\n#define RCC_D2CFGR_D2PPRE1_DIV4                RCC_D2CFGR_D2PPRE1_DIV4_Msk     /*!< APB1 clock divided by 4 */\n#define RCC_D2CFGR_D2PPRE1_DIV8_Pos            (5U)\n#define RCC_D2CFGR_D2PPRE1_DIV8_Msk            (0x3UL << RCC_D2CFGR_D2PPRE1_DIV8_Pos) /*!< 0x00000060 */\n#define RCC_D2CFGR_D2PPRE1_DIV8                RCC_D2CFGR_D2PPRE1_DIV8_Msk     /*!< APB1 clock divided by 8 */\n#define RCC_D2CFGR_D2PPRE1_DIV16_Pos           (4U)\n#define RCC_D2CFGR_D2PPRE1_DIV16_Msk           (0x7UL << RCC_D2CFGR_D2PPRE1_DIV16_Pos) /*!< 0x00000070 */\n#define RCC_D2CFGR_D2PPRE1_DIV16               RCC_D2CFGR_D2PPRE1_DIV16_Msk    /*!< APB1 clock divided by 16 */\n\n/*!< D2PPRE2 configuration */\n#define RCC_D2CFGR_D2PPRE2_Pos                 (8U)\n#define RCC_D2CFGR_D2PPRE2_Msk                 (0x7UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000700 */\n#define RCC_D2CFGR_D2PPRE2                     RCC_D2CFGR_D2PPRE2_Msk          /*!< D2PPRE2[2:0] bits (APB2 prescaler) */\n#define RCC_D2CFGR_D2PPRE2_0                   (0x1UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000100 */\n#define RCC_D2CFGR_D2PPRE2_1                   (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */\n#define RCC_D2CFGR_D2PPRE2_2                   (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */\n\n#define RCC_D2CFGR_D2PPRE2_DIV1                ((uint32_t)0x00000000)          /*!< APB2 clock not divided */\n#define RCC_D2CFGR_D2PPRE2_DIV2_Pos            (10U)\n#define RCC_D2CFGR_D2PPRE2_DIV2_Msk            (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */\n#define RCC_D2CFGR_D2PPRE2_DIV2                RCC_D2CFGR_D2PPRE2_DIV2_Msk     /*!< APB2 clock divided by 2 */\n#define RCC_D2CFGR_D2PPRE2_DIV4_Pos            (8U)\n#define RCC_D2CFGR_D2PPRE2_DIV4_Msk            (0x5UL << RCC_D2CFGR_D2PPRE2_DIV4_Pos) /*!< 0x00000500 */\n#define RCC_D2CFGR_D2PPRE2_DIV4                RCC_D2CFGR_D2PPRE2_DIV4_Msk     /*!< APB2 clock divided by 4 */\n#define RCC_D2CFGR_D2PPRE2_DIV8_Pos            (9U)\n#define RCC_D2CFGR_D2PPRE2_DIV8_Msk            (0x3UL << RCC_D2CFGR_D2PPRE2_DIV8_Pos) /*!< 0x00000600 */\n#define RCC_D2CFGR_D2PPRE2_DIV8                RCC_D2CFGR_D2PPRE2_DIV8_Msk     /*!< APB2 clock divided by 8 */\n#define RCC_D2CFGR_D2PPRE2_DIV16_Pos           (8U)\n#define RCC_D2CFGR_D2PPRE2_DIV16_Msk           (0x7UL << RCC_D2CFGR_D2PPRE2_DIV16_Pos) /*!< 0x00000700 */\n#define RCC_D2CFGR_D2PPRE2_DIV16               RCC_D2CFGR_D2PPRE2_DIV16_Msk    /*!< APB2 clock divided by 16 */\n\n/********************  Bit definition for RCC_D3CFGR register  ******************/\n/*!< D3PPRE configuration */\n#define RCC_D3CFGR_D3PPRE_Pos                  (4U)\n#define RCC_D3CFGR_D3PPRE_Msk                  (0x7UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000070 */\n#define RCC_D3CFGR_D3PPRE                      RCC_D3CFGR_D3PPRE_Msk           /*!< D3PPRE1[2:0] bits (APB4 prescaler) */\n#define RCC_D3CFGR_D3PPRE_0                    (0x1UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000010 */\n#define RCC_D3CFGR_D3PPRE_1                    (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */\n#define RCC_D3CFGR_D3PPRE_2                    (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */\n\n#define RCC_D3CFGR_D3PPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB4 clock not divided */\n#define RCC_D3CFGR_D3PPRE_DIV2_Pos             (6U)\n#define RCC_D3CFGR_D3PPRE_DIV2_Msk             (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */\n#define RCC_D3CFGR_D3PPRE_DIV2                 RCC_D3CFGR_D3PPRE_DIV2_Msk      /*!< APB4 clock divided by 2 */\n#define RCC_D3CFGR_D3PPRE_DIV4_Pos             (4U)\n#define RCC_D3CFGR_D3PPRE_DIV4_Msk             (0x5UL << RCC_D3CFGR_D3PPRE_DIV4_Pos) /*!< 0x00000050 */\n#define RCC_D3CFGR_D3PPRE_DIV4                 RCC_D3CFGR_D3PPRE_DIV4_Msk      /*!< APB4 clock divided by 4 */\n#define RCC_D3CFGR_D3PPRE_DIV8_Pos             (5U)\n#define RCC_D3CFGR_D3PPRE_DIV8_Msk             (0x3UL << RCC_D3CFGR_D3PPRE_DIV8_Pos) /*!< 0x00000060 */\n#define RCC_D3CFGR_D3PPRE_DIV8                 RCC_D3CFGR_D3PPRE_DIV8_Msk      /*!< APB4 clock divided by 8 */\n#define RCC_D3CFGR_D3PPRE_DIV16_Pos            (4U)\n#define RCC_D3CFGR_D3PPRE_DIV16_Msk            (0x7UL << RCC_D3CFGR_D3PPRE_DIV16_Pos) /*!< 0x00000070 */\n#define RCC_D3CFGR_D3PPRE_DIV16                RCC_D3CFGR_D3PPRE_DIV16_Msk     /*!< APB4 clock divided by 16 */\n\n/********************  Bit definition for RCC_PLLCKSELR register  *************/\n\n#define RCC_PLLCKSELR_PLLSRC_Pos               (0U)\n#define RCC_PLLCKSELR_PLLSRC_Msk               (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */\n#define RCC_PLLCKSELR_PLLSRC                   RCC_PLLCKSELR_PLLSRC_Msk\n\n#define RCC_PLLCKSELR_PLLSRC_HSI               ((uint32_t)0x00000000)          /*!< HSI source clock selected */\n#define RCC_PLLCKSELR_PLLSRC_CSI_Pos           (0U)\n#define RCC_PLLCKSELR_PLLSRC_CSI_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */\n#define RCC_PLLCKSELR_PLLSRC_CSI               RCC_PLLCKSELR_PLLSRC_CSI_Msk    /*!< CSI source clock selected */\n#define RCC_PLLCKSELR_PLLSRC_HSE_Pos           (1U)\n#define RCC_PLLCKSELR_PLLSRC_HSE_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_HSE_Pos) /*!< 0x00000002 */\n#define RCC_PLLCKSELR_PLLSRC_HSE               RCC_PLLCKSELR_PLLSRC_HSE_Msk    /*!< HSE source clock selected */\n#define RCC_PLLCKSELR_PLLSRC_NONE_Pos          (0U)\n#define RCC_PLLCKSELR_PLLSRC_NONE_Msk          (0x3UL << RCC_PLLCKSELR_PLLSRC_NONE_Pos) /*!< 0x00000003 */\n#define RCC_PLLCKSELR_PLLSRC_NONE              RCC_PLLCKSELR_PLLSRC_NONE_Msk   /*!< No source clock selected  */\n\n#define RCC_PLLCKSELR_DIVM1_Pos                (4U)\n#define RCC_PLLCKSELR_DIVM1_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x000003F0 */\n#define RCC_PLLCKSELR_DIVM1                    RCC_PLLCKSELR_DIVM1_Msk\n#define RCC_PLLCKSELR_DIVM1_0                  (0x01UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000010 */\n#define RCC_PLLCKSELR_DIVM1_1                  (0x02UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000020 */\n#define RCC_PLLCKSELR_DIVM1_2                  (0x04UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000040 */\n#define RCC_PLLCKSELR_DIVM1_3                  (0x08UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000080 */\n#define RCC_PLLCKSELR_DIVM1_4                  (0x10UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000100 */\n#define RCC_PLLCKSELR_DIVM1_5                  (0x20UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000200 */\n\n#define RCC_PLLCKSELR_DIVM2_Pos                (12U)\n#define RCC_PLLCKSELR_DIVM2_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x0003F000 */\n#define RCC_PLLCKSELR_DIVM2                    RCC_PLLCKSELR_DIVM2_Msk\n#define RCC_PLLCKSELR_DIVM2_0                  (0x01UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00001000 */\n#define RCC_PLLCKSELR_DIVM2_1                  (0x02UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00002000 */\n#define RCC_PLLCKSELR_DIVM2_2                  (0x04UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00004000 */\n#define RCC_PLLCKSELR_DIVM2_3                  (0x08UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00008000 */\n#define RCC_PLLCKSELR_DIVM2_4                  (0x10UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00010000 */\n#define RCC_PLLCKSELR_DIVM2_5                  (0x20UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00020000 */\n\n#define RCC_PLLCKSELR_DIVM3_Pos                (20U)\n#define RCC_PLLCKSELR_DIVM3_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x03F00000 */\n#define RCC_PLLCKSELR_DIVM3                    RCC_PLLCKSELR_DIVM3_Msk\n#define RCC_PLLCKSELR_DIVM3_0                  (0x01UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00100000 */\n#define RCC_PLLCKSELR_DIVM3_1                  (0x02UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00200000 */\n#define RCC_PLLCKSELR_DIVM3_2                  (0x04UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00400000 */\n#define RCC_PLLCKSELR_DIVM3_3                  (0x08UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00800000 */\n#define RCC_PLLCKSELR_DIVM3_4                  (0x10UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x01000000 */\n#define RCC_PLLCKSELR_DIVM3_5                  (0x20UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x02000000 */\n\n/********************  Bit definition for RCC_PLLCFGR register  ***************/\n\n#define RCC_PLLCFGR_PLL1FRACEN_Pos             (0U)\n#define RCC_PLLCFGR_PLL1FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL1FRACEN_Pos) /*!< 0x00000001 */\n#define RCC_PLLCFGR_PLL1FRACEN                 RCC_PLLCFGR_PLL1FRACEN_Msk\n#define RCC_PLLCFGR_PLL1VCOSEL_Pos             (1U)\n#define RCC_PLLCFGR_PLL1VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL1VCOSEL_Pos) /*!< 0x00000002 */\n#define RCC_PLLCFGR_PLL1VCOSEL                 RCC_PLLCFGR_PLL1VCOSEL_Msk\n#define RCC_PLLCFGR_PLL1RGE_Pos                (2U)\n#define RCC_PLLCFGR_PLL1RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */\n#define RCC_PLLCFGR_PLL1RGE                    RCC_PLLCFGR_PLL1RGE_Msk\n#define RCC_PLLCFGR_PLL1RGE_0                  (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000000 */\n#define RCC_PLLCFGR_PLL1RGE_1                  (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */\n#define RCC_PLLCFGR_PLL1RGE_2                  (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000008 */\n#define RCC_PLLCFGR_PLL1RGE_3                  (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */\n\n#define RCC_PLLCFGR_PLL2FRACEN_Pos             (4U)\n#define RCC_PLLCFGR_PLL2FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL2FRACEN_Pos) /*!< 0x00000010 */\n#define RCC_PLLCFGR_PLL2FRACEN                 RCC_PLLCFGR_PLL2FRACEN_Msk\n#define RCC_PLLCFGR_PLL2VCOSEL_Pos             (5U)\n#define RCC_PLLCFGR_PLL2VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL2VCOSEL_Pos) /*!< 0x00000020 */\n#define RCC_PLLCFGR_PLL2VCOSEL                 RCC_PLLCFGR_PLL2VCOSEL_Msk\n#define RCC_PLLCFGR_PLL2RGE_Pos                (6U)\n#define RCC_PLLCFGR_PLL2RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */\n#define RCC_PLLCFGR_PLL2RGE                    RCC_PLLCFGR_PLL2RGE_Msk\n#define RCC_PLLCFGR_PLL2RGE_0                  (0x0UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000000 */\n#define RCC_PLLCFGR_PLL2RGE_1                  (0x1UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000040 */\n#define RCC_PLLCFGR_PLL2RGE_2                  (0x2UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000080 */\n#define RCC_PLLCFGR_PLL2RGE_3                  (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */\n\n#define RCC_PLLCFGR_PLL3FRACEN_Pos             (8U)\n#define RCC_PLLCFGR_PLL3FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL3FRACEN_Pos) /*!< 0x00000100 */\n#define RCC_PLLCFGR_PLL3FRACEN                 RCC_PLLCFGR_PLL3FRACEN_Msk\n#define RCC_PLLCFGR_PLL3VCOSEL_Pos             (9U)\n#define RCC_PLLCFGR_PLL3VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL3VCOSEL_Pos) /*!< 0x00000200 */\n#define RCC_PLLCFGR_PLL3VCOSEL                 RCC_PLLCFGR_PLL3VCOSEL_Msk\n#define RCC_PLLCFGR_PLL3RGE_Pos                (10U)\n#define RCC_PLLCFGR_PLL3RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */\n#define RCC_PLLCFGR_PLL3RGE                    RCC_PLLCFGR_PLL3RGE_Msk\n#define RCC_PLLCFGR_PLL3RGE_0                  (0x0UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000000 */\n#define RCC_PLLCFGR_PLL3RGE_1                  (0x1UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000400 */\n#define RCC_PLLCFGR_PLL3RGE_2                  (0x2UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000800 */\n#define RCC_PLLCFGR_PLL3RGE_3                  (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */\n\n#define RCC_PLLCFGR_DIVP1EN_Pos                (16U)\n#define RCC_PLLCFGR_DIVP1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP1EN_Pos) /*!< 0x00010000 */\n#define RCC_PLLCFGR_DIVP1EN                    RCC_PLLCFGR_DIVP1EN_Msk\n#define RCC_PLLCFGR_DIVQ1EN_Pos                (17U)\n#define RCC_PLLCFGR_DIVQ1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ1EN_Pos) /*!< 0x00020000 */\n#define RCC_PLLCFGR_DIVQ1EN                    RCC_PLLCFGR_DIVQ1EN_Msk\n#define RCC_PLLCFGR_DIVR1EN_Pos                (18U)\n#define RCC_PLLCFGR_DIVR1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR1EN_Pos) /*!< 0x00040000 */\n#define RCC_PLLCFGR_DIVR1EN                    RCC_PLLCFGR_DIVR1EN_Msk\n\n#define RCC_PLLCFGR_DIVP2EN_Pos                (19U)\n#define RCC_PLLCFGR_DIVP2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP2EN_Pos) /*!< 0x00080000 */\n#define RCC_PLLCFGR_DIVP2EN                    RCC_PLLCFGR_DIVP2EN_Msk\n#define RCC_PLLCFGR_DIVQ2EN_Pos                (20U)\n#define RCC_PLLCFGR_DIVQ2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ2EN_Pos) /*!< 0x00100000 */\n#define RCC_PLLCFGR_DIVQ2EN                    RCC_PLLCFGR_DIVQ2EN_Msk\n#define RCC_PLLCFGR_DIVR2EN_Pos                (21U)\n#define RCC_PLLCFGR_DIVR2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR2EN_Pos) /*!< 0x00200000 */\n#define RCC_PLLCFGR_DIVR2EN                    RCC_PLLCFGR_DIVR2EN_Msk\n\n#define RCC_PLLCFGR_DIVP3EN_Pos                (22U)\n#define RCC_PLLCFGR_DIVP3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP3EN_Pos) /*!< 0x00400000 */\n#define RCC_PLLCFGR_DIVP3EN                    RCC_PLLCFGR_DIVP3EN_Msk\n#define RCC_PLLCFGR_DIVQ3EN_Pos                (23U)\n#define RCC_PLLCFGR_DIVQ3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ3EN_Pos) /*!< 0x00800000 */\n#define RCC_PLLCFGR_DIVQ3EN                    RCC_PLLCFGR_DIVQ3EN_Msk\n#define RCC_PLLCFGR_DIVR3EN_Pos                (24U)\n#define RCC_PLLCFGR_DIVR3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR3EN_Pos) /*!< 0x01000000 */\n#define RCC_PLLCFGR_DIVR3EN                    RCC_PLLCFGR_DIVR3EN_Msk\n\n\n/********************  Bit definition for RCC_PLL1DIVR register  ***************/\n#define RCC_PLL1DIVR_N1_Pos                    (0U)\n#define RCC_PLL1DIVR_N1_Msk                    (0x1FFUL << RCC_PLL1DIVR_N1_Pos) /*!< 0x000001FF */\n#define RCC_PLL1DIVR_N1                        RCC_PLL1DIVR_N1_Msk\n#define RCC_PLL1DIVR_P1_Pos                    (9U)\n#define RCC_PLL1DIVR_P1_Msk                    (0x7FUL << RCC_PLL1DIVR_P1_Pos) /*!< 0x0000FE00 */\n#define RCC_PLL1DIVR_P1                        RCC_PLL1DIVR_P1_Msk\n#define RCC_PLL1DIVR_Q1_Pos                    (16U)\n#define RCC_PLL1DIVR_Q1_Msk                    (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */\n#define RCC_PLL1DIVR_Q1                        RCC_PLL1DIVR_Q1_Msk\n#define RCC_PLL1DIVR_R1_Pos                    (24U)\n#define RCC_PLL1DIVR_R1_Msk                    (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */\n#define RCC_PLL1DIVR_R1                        RCC_PLL1DIVR_R1_Msk\n\n/********************  Bit definition for RCC_PLL1FRACR register  ***************/\n#define RCC_PLL1FRACR_FRACN1_Pos               (3U)\n#define RCC_PLL1FRACR_FRACN1_Msk               (0x1FFFUL << RCC_PLL1FRACR_FRACN1_Pos) /*!< 0x0000FFF8 */\n#define RCC_PLL1FRACR_FRACN1                   RCC_PLL1FRACR_FRACN1_Msk\n\n/********************  Bit definition for RCC_PLL2DIVR register  ***************/\n#define RCC_PLL2DIVR_N2_Pos                    (0U)\n#define RCC_PLL2DIVR_N2_Msk                    (0x1FFUL << RCC_PLL2DIVR_N2_Pos) /*!< 0x000001FF */\n#define RCC_PLL2DIVR_N2                        RCC_PLL2DIVR_N2_Msk\n#define RCC_PLL2DIVR_P2_Pos                    (9U)\n#define RCC_PLL2DIVR_P2_Msk                    (0x7FUL << RCC_PLL2DIVR_P2_Pos) /*!< 0x0000FE00 */\n#define RCC_PLL2DIVR_P2                        RCC_PLL2DIVR_P2_Msk\n#define RCC_PLL2DIVR_Q2_Pos                    (16U)\n#define RCC_PLL2DIVR_Q2_Msk                    (0x7FUL << RCC_PLL2DIVR_Q2_Pos) /*!< 0x007F0000 */\n#define RCC_PLL2DIVR_Q2                        RCC_PLL2DIVR_Q2_Msk\n#define RCC_PLL2DIVR_R2_Pos                    (24U)\n#define RCC_PLL2DIVR_R2_Msk                    (0x7FUL << RCC_PLL2DIVR_R2_Pos) /*!< 0x7F000000 */\n#define RCC_PLL2DIVR_R2                        RCC_PLL2DIVR_R2_Msk\n\n/********************  Bit definition for RCC_PLL2FRACR register  ***************/\n#define RCC_PLL2FRACR_FRACN2_Pos               (3U)\n#define RCC_PLL2FRACR_FRACN2_Msk               (0x1FFFUL << RCC_PLL2FRACR_FRACN2_Pos) /*!< 0x0000FFF8 */\n#define RCC_PLL2FRACR_FRACN2                   RCC_PLL2FRACR_FRACN2_Msk\n\n/********************  Bit definition for RCC_PLL3DIVR register  ***************/\n#define RCC_PLL3DIVR_N3_Pos                    (0U)\n#define RCC_PLL3DIVR_N3_Msk                    (0x1FFUL << RCC_PLL3DIVR_N3_Pos) /*!< 0x000001FF */\n#define RCC_PLL3DIVR_N3                        RCC_PLL3DIVR_N3_Msk\n#define RCC_PLL3DIVR_P3_Pos                    (9U)\n#define RCC_PLL3DIVR_P3_Msk                    (0x7FUL << RCC_PLL3DIVR_P3_Pos) /*!< 0x0000FE00 */\n#define RCC_PLL3DIVR_P3                        RCC_PLL3DIVR_P3_Msk\n#define RCC_PLL3DIVR_Q3_Pos                    (16U)\n#define RCC_PLL3DIVR_Q3_Msk                    (0x7FUL << RCC_PLL3DIVR_Q3_Pos) /*!< 0x007F0000 */\n#define RCC_PLL3DIVR_Q3                        RCC_PLL3DIVR_Q3_Msk\n#define RCC_PLL3DIVR_R3_Pos                    (24U)\n#define RCC_PLL3DIVR_R3_Msk                    (0x7FUL << RCC_PLL3DIVR_R3_Pos) /*!< 0x7F000000 */\n#define RCC_PLL3DIVR_R3                        RCC_PLL3DIVR_R3_Msk\n\n/********************  Bit definition for RCC_PLL3FRACR register  ***************/\n#define RCC_PLL3FRACR_FRACN3_Pos               (3U)\n#define RCC_PLL3FRACR_FRACN3_Msk               (0x1FFFUL << RCC_PLL3FRACR_FRACN3_Pos) /*!< 0x0000FFF8 */\n#define RCC_PLL3FRACR_FRACN3                   RCC_PLL3FRACR_FRACN3_Msk\n\n/********************  Bit definition for RCC_D1CCIPR register  ***************/\n#define RCC_D1CCIPR_FMCSEL_Pos                 (0U)\n#define RCC_D1CCIPR_FMCSEL_Msk                 (0x3UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000003 */\n#define RCC_D1CCIPR_FMCSEL                     RCC_D1CCIPR_FMCSEL_Msk\n#define RCC_D1CCIPR_FMCSEL_0                   (0x1UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000001 */\n#define RCC_D1CCIPR_FMCSEL_1                   (0x2UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000002 */\n#define RCC_D1CCIPR_QSPISEL_Pos                (4U)\n#define RCC_D1CCIPR_QSPISEL_Msk                (0x3UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000030 */\n#define RCC_D1CCIPR_QSPISEL                    RCC_D1CCIPR_QSPISEL_Msk\n#define RCC_D1CCIPR_QSPISEL_0                  (0x1UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000010 */\n#define RCC_D1CCIPR_QSPISEL_1                  (0x2UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000020 */\n#define RCC_D1CCIPR_SDMMCSEL_Pos               (16U)\n#define RCC_D1CCIPR_SDMMCSEL_Msk               (0x1UL << RCC_D1CCIPR_SDMMCSEL_Pos) /*!< 0x00010000 */\n#define RCC_D1CCIPR_SDMMCSEL                   RCC_D1CCIPR_SDMMCSEL_Msk\n#define RCC_D1CCIPR_CKPERSEL_Pos               (28U)\n#define RCC_D1CCIPR_CKPERSEL_Msk               (0x3UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x30000000 */\n#define RCC_D1CCIPR_CKPERSEL                   RCC_D1CCIPR_CKPERSEL_Msk\n#define RCC_D1CCIPR_CKPERSEL_0                 (0x1UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x10000000 */\n#define RCC_D1CCIPR_CKPERSEL_1                 (0x2UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x20000000 */\n\n/********************  Bit definition for RCC_D2CCIP1R register  ***************/\n#define RCC_D2CCIP1R_SAI1SEL_Pos               (0U)\n#define RCC_D2CCIP1R_SAI1SEL_Msk               (0x7UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000007 */\n#define RCC_D2CCIP1R_SAI1SEL                   RCC_D2CCIP1R_SAI1SEL_Msk\n#define RCC_D2CCIP1R_SAI1SEL_0                 (0x1UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000001 */\n#define RCC_D2CCIP1R_SAI1SEL_1                 (0x2UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000002 */\n#define RCC_D2CCIP1R_SAI1SEL_2                 (0x4UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000004 */\n\n#define RCC_D2CCIP1R_SAI23SEL_Pos              (6U)\n#define RCC_D2CCIP1R_SAI23SEL_Msk              (0x7UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x000001C0 */\n#define RCC_D2CCIP1R_SAI23SEL                  RCC_D2CCIP1R_SAI23SEL_Msk\n#define RCC_D2CCIP1R_SAI23SEL_0                (0x1UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000040 */\n#define RCC_D2CCIP1R_SAI23SEL_1                (0x2UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000080 */\n#define RCC_D2CCIP1R_SAI23SEL_2                (0x4UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000100 */\n\n#define RCC_D2CCIP1R_SPI123SEL_Pos             (12U)\n#define RCC_D2CCIP1R_SPI123SEL_Msk             (0x7UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00007000 */\n#define RCC_D2CCIP1R_SPI123SEL                 RCC_D2CCIP1R_SPI123SEL_Msk\n#define RCC_D2CCIP1R_SPI123SEL_0               (0x1UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00001000 */\n#define RCC_D2CCIP1R_SPI123SEL_1               (0x2UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00002000 */\n#define RCC_D2CCIP1R_SPI123SEL_2               (0x4UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00004000 */\n\n#define RCC_D2CCIP1R_SPI45SEL_Pos              (16U)\n#define RCC_D2CCIP1R_SPI45SEL_Msk              (0x7UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00070000 */\n#define RCC_D2CCIP1R_SPI45SEL                  RCC_D2CCIP1R_SPI45SEL_Msk\n#define RCC_D2CCIP1R_SPI45SEL_0                (0x1UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00010000 */\n#define RCC_D2CCIP1R_SPI45SEL_1                (0x2UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00020000 */\n#define RCC_D2CCIP1R_SPI45SEL_2                (0x4UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00040000 */\n\n#define RCC_D2CCIP1R_SPDIFSEL_Pos              (20U)\n#define RCC_D2CCIP1R_SPDIFSEL_Msk              (0x3UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00300000 */\n#define RCC_D2CCIP1R_SPDIFSEL                  RCC_D2CCIP1R_SPDIFSEL_Msk\n#define RCC_D2CCIP1R_SPDIFSEL_0                (0x1UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00100000 */\n#define RCC_D2CCIP1R_SPDIFSEL_1                (0x2UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00200000 */\n\n#define RCC_D2CCIP1R_DFSDM1SEL_Pos             (24U)\n#define RCC_D2CCIP1R_DFSDM1SEL_Msk             (0x1UL << RCC_D2CCIP1R_DFSDM1SEL_Pos) /*!< 0x01000000 */\n#define RCC_D2CCIP1R_DFSDM1SEL                 RCC_D2CCIP1R_DFSDM1SEL_Msk\n\n#define RCC_D2CCIP1R_FDCANSEL_Pos              (28U)\n#define RCC_D2CCIP1R_FDCANSEL_Msk              (0x3UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x30000000 */\n#define RCC_D2CCIP1R_FDCANSEL                  RCC_D2CCIP1R_FDCANSEL_Msk\n#define RCC_D2CCIP1R_FDCANSEL_0                (0x1UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x10000000 */\n#define RCC_D2CCIP1R_FDCANSEL_1                (0x2UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x20000000 */\n\n#define RCC_D2CCIP1R_SWPSEL_Pos                (31U)\n#define RCC_D2CCIP1R_SWPSEL_Msk                (0x1UL << RCC_D2CCIP1R_SWPSEL_Pos) /*!< 0x80000000 */\n#define RCC_D2CCIP1R_SWPSEL                    RCC_D2CCIP1R_SWPSEL_Msk\n\n/********************  Bit definition for RCC_D2CCIP2R register  ***************/\n#define RCC_D2CCIP2R_USART16SEL_Pos            (3U)\n#define RCC_D2CCIP2R_USART16SEL_Msk            (0x7UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000038 */\n#define RCC_D2CCIP2R_USART16SEL                RCC_D2CCIP2R_USART16SEL_Msk\n#define RCC_D2CCIP2R_USART16SEL_0              (0x1UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000008 */\n#define RCC_D2CCIP2R_USART16SEL_1              (0x2UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000010 */\n#define RCC_D2CCIP2R_USART16SEL_2              (0x4UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000020 */\n\n#define RCC_D2CCIP2R_USART28SEL_Pos            (0U)\n#define RCC_D2CCIP2R_USART28SEL_Msk            (0x7UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000007 */\n#define RCC_D2CCIP2R_USART28SEL                RCC_D2CCIP2R_USART28SEL_Msk\n#define RCC_D2CCIP2R_USART28SEL_0              (0x1UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000001 */\n#define RCC_D2CCIP2R_USART28SEL_1              (0x2UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000002 */\n#define RCC_D2CCIP2R_USART28SEL_2              (0x4UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000004 */\n\n#define RCC_D2CCIP2R_RNGSEL_Pos                (8U)\n#define RCC_D2CCIP2R_RNGSEL_Msk                (0x3UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000300 */\n#define RCC_D2CCIP2R_RNGSEL                    RCC_D2CCIP2R_RNGSEL_Msk\n#define RCC_D2CCIP2R_RNGSEL_0                  (0x1UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000100 */\n#define RCC_D2CCIP2R_RNGSEL_1                  (0x2UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000200 */\n\n#define RCC_D2CCIP2R_I2C123SEL_Pos             (12U)\n#define RCC_D2CCIP2R_I2C123SEL_Msk             (0x3UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00003000 */\n#define RCC_D2CCIP2R_I2C123SEL                 RCC_D2CCIP2R_I2C123SEL_Msk\n#define RCC_D2CCIP2R_I2C123SEL_0               (0x1UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00001000 */\n#define RCC_D2CCIP2R_I2C123SEL_1               (0x2UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00002000 */\n\n#define RCC_D2CCIP2R_USBSEL_Pos                (20U)\n#define RCC_D2CCIP2R_USBSEL_Msk                (0x3UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00300000 */\n#define RCC_D2CCIP2R_USBSEL                    RCC_D2CCIP2R_USBSEL_Msk\n#define RCC_D2CCIP2R_USBSEL_0                  (0x1UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00100000 */\n#define RCC_D2CCIP2R_USBSEL_1                  (0x2UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00200000 */\n\n#define RCC_D2CCIP2R_CECSEL_Pos                (22U)\n#define RCC_D2CCIP2R_CECSEL_Msk                (0x3UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00C00000 */\n#define RCC_D2CCIP2R_CECSEL                    RCC_D2CCIP2R_CECSEL_Msk\n#define RCC_D2CCIP2R_CECSEL_0                  (0x1UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00400000 */\n#define RCC_D2CCIP2R_CECSEL_1                  (0x2UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00800000 */\n\n#define RCC_D2CCIP2R_LPTIM1SEL_Pos             (28U)\n#define RCC_D2CCIP2R_LPTIM1SEL_Msk             (0x7UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x70000000 */\n#define RCC_D2CCIP2R_LPTIM1SEL                 RCC_D2CCIP2R_LPTIM1SEL_Msk\n#define RCC_D2CCIP2R_LPTIM1SEL_0               (0x1UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x10000000 */\n#define RCC_D2CCIP2R_LPTIM1SEL_1               (0x2UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x20000000 */\n#define RCC_D2CCIP2R_LPTIM1SEL_2               (0x4UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x40000000 */\n\n/********************  Bit definition for RCC_D3CCIPR register  ***************/\n#define RCC_D3CCIPR_LPUART1SEL_Pos             (0U)\n#define RCC_D3CCIPR_LPUART1SEL_Msk             (0x7UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000007 */\n#define RCC_D3CCIPR_LPUART1SEL                 RCC_D3CCIPR_LPUART1SEL_Msk\n#define RCC_D3CCIPR_LPUART1SEL_0               (0x1UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000001 */\n#define RCC_D3CCIPR_LPUART1SEL_1               (0x2UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000002 */\n#define RCC_D3CCIPR_LPUART1SEL_2               (0x4UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000004 */\n\n#define RCC_D3CCIPR_I2C4SEL_Pos                (8U)\n#define RCC_D3CCIPR_I2C4SEL_Msk                (0x3UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000300 */\n#define RCC_D3CCIPR_I2C4SEL                    RCC_D3CCIPR_I2C4SEL_Msk\n#define RCC_D3CCIPR_I2C4SEL_0                  (0x1UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000100 */\n#define RCC_D3CCIPR_I2C4SEL_1                  (0x2UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000200 */\n\n#define RCC_D3CCIPR_LPTIM2SEL_Pos              (10U)\n#define RCC_D3CCIPR_LPTIM2SEL_Msk              (0x7UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00001C00 */\n#define RCC_D3CCIPR_LPTIM2SEL                  RCC_D3CCIPR_LPTIM2SEL_Msk\n#define RCC_D3CCIPR_LPTIM2SEL_0                (0x1UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00000400 */\n#define RCC_D3CCIPR_LPTIM2SEL_1                (0x2UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00000800 */\n#define RCC_D3CCIPR_LPTIM2SEL_2                (0x4UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00001000 */\n\n#define RCC_D3CCIPR_LPTIM345SEL_Pos            (13U)\n#define RCC_D3CCIPR_LPTIM345SEL_Msk            (0x7UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x0000E000 */\n#define RCC_D3CCIPR_LPTIM345SEL                RCC_D3CCIPR_LPTIM345SEL_Msk\n#define RCC_D3CCIPR_LPTIM345SEL_0              (0x1UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00002000 */\n#define RCC_D3CCIPR_LPTIM345SEL_1              (0x2UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00004000 */\n#define RCC_D3CCIPR_LPTIM345SEL_2              (0x4UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00008000 */\n\n#define RCC_D3CCIPR_SAI4ASEL_Pos               (21U)\n#define RCC_D3CCIPR_SAI4ASEL_Msk               (0x7UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00E00000 */\n#define RCC_D3CCIPR_SAI4ASEL                   RCC_D3CCIPR_SAI4ASEL_Msk\n#define RCC_D3CCIPR_SAI4ASEL_0                 (0x1UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00200000 */\n#define RCC_D3CCIPR_SAI4ASEL_1                 (0x2UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00400000 */\n#define RCC_D3CCIPR_SAI4ASEL_2                 (0x4UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00800000 */\n\n#define RCC_D3CCIPR_SAI4BSEL_Pos               (24U)\n#define RCC_D3CCIPR_SAI4BSEL_Msk               (0x7UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x07000000 */\n#define RCC_D3CCIPR_SAI4BSEL                   RCC_D3CCIPR_SAI4BSEL_Msk\n#define RCC_D3CCIPR_SAI4BSEL_0                 (0x1UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x01000000 */\n#define RCC_D3CCIPR_SAI4BSEL_1                 (0x2UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x02000000 */\n#define RCC_D3CCIPR_SAI4BSEL_2                 (0x4UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x04000000 */\n\n#define RCC_D3CCIPR_ADCSEL_Pos                 (16U)\n#define RCC_D3CCIPR_ADCSEL_Msk                 (0x3UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00030000 */\n#define RCC_D3CCIPR_ADCSEL                     RCC_D3CCIPR_ADCSEL_Msk\n#define RCC_D3CCIPR_ADCSEL_0                   (0x1UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00010000 */\n#define RCC_D3CCIPR_ADCSEL_1                   (0x2UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00020000 */\n\n#define RCC_D3CCIPR_SPI6SEL_Pos                (28U)\n#define RCC_D3CCIPR_SPI6SEL_Msk                (0x7UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x70000000 */\n#define RCC_D3CCIPR_SPI6SEL                    RCC_D3CCIPR_SPI6SEL_Msk\n#define RCC_D3CCIPR_SPI6SEL_0                  (0x1UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x10000000 */\n#define RCC_D3CCIPR_SPI6SEL_1                  (0x2UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x20000000 */\n#define RCC_D3CCIPR_SPI6SEL_2                  (0x4UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x40000000 */\n/********************  Bit definition for RCC_CIER register  ******************/\n#define RCC_CIER_LSIRDYIE_Pos                  (0U)\n#define RCC_CIER_LSIRDYIE_Msk                  (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */\n#define RCC_CIER_LSIRDYIE                      RCC_CIER_LSIRDYIE_Msk\n#define RCC_CIER_LSERDYIE_Pos                  (1U)\n#define RCC_CIER_LSERDYIE_Msk                  (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */\n#define RCC_CIER_LSERDYIE                      RCC_CIER_LSERDYIE_Msk\n#define RCC_CIER_HSIRDYIE_Pos                  (2U)\n#define RCC_CIER_HSIRDYIE_Msk                  (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */\n#define RCC_CIER_HSIRDYIE                      RCC_CIER_HSIRDYIE_Msk\n#define RCC_CIER_HSERDYIE_Pos                  (3U)\n#define RCC_CIER_HSERDYIE_Msk                  (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */\n#define RCC_CIER_HSERDYIE                      RCC_CIER_HSERDYIE_Msk\n#define RCC_CIER_CSIRDYIE_Pos                  (4U)\n#define RCC_CIER_CSIRDYIE_Msk                  (0x1UL << RCC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */\n#define RCC_CIER_CSIRDYIE                      RCC_CIER_CSIRDYIE_Msk\n#define RCC_CIER_HSI48RDYIE_Pos                (5U)\n#define RCC_CIER_HSI48RDYIE_Msk                (0x1UL << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000020 */\n#define RCC_CIER_HSI48RDYIE                    RCC_CIER_HSI48RDYIE_Msk\n#define RCC_CIER_PLL1RDYIE_Pos                 (6U)\n#define RCC_CIER_PLL1RDYIE_Msk                 (0x1UL << RCC_CIER_PLL1RDYIE_Pos) /*!< 0x00000040 */\n#define RCC_CIER_PLL1RDYIE                     RCC_CIER_PLL1RDYIE_Msk\n#define RCC_CIER_PLL2RDYIE_Pos                 (7U)\n#define RCC_CIER_PLL2RDYIE_Msk                 (0x1UL << RCC_CIER_PLL2RDYIE_Pos) /*!< 0x00000080 */\n#define RCC_CIER_PLL2RDYIE                     RCC_CIER_PLL2RDYIE_Msk\n#define RCC_CIER_PLL3RDYIE_Pos                 (8U)\n#define RCC_CIER_PLL3RDYIE_Msk                 (0x1UL << RCC_CIER_PLL3RDYIE_Pos) /*!< 0x00000100 */\n#define RCC_CIER_PLL3RDYIE                     RCC_CIER_PLL3RDYIE_Msk\n#define RCC_CIER_LSECSSIE_Pos                  (9U)\n#define RCC_CIER_LSECSSIE_Msk                  (0x1UL << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */\n#define RCC_CIER_LSECSSIE                      RCC_CIER_LSECSSIE_Msk\n\n/********************  Bit definition for RCC_CIFR register  ******************/\n#define RCC_CIFR_LSIRDYF_Pos                   (0U)\n#define RCC_CIFR_LSIRDYF_Msk                   (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */\n#define RCC_CIFR_LSIRDYF                       RCC_CIFR_LSIRDYF_Msk\n#define RCC_CIFR_LSERDYF_Pos                   (1U)\n#define RCC_CIFR_LSERDYF_Msk                   (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */\n#define RCC_CIFR_LSERDYF                       RCC_CIFR_LSERDYF_Msk\n#define RCC_CIFR_HSIRDYF_Pos                   (2U)\n#define RCC_CIFR_HSIRDYF_Msk                   (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */\n#define RCC_CIFR_HSIRDYF                       RCC_CIFR_HSIRDYF_Msk\n#define RCC_CIFR_HSERDYF_Pos                   (3U)\n#define RCC_CIFR_HSERDYF_Msk                   (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */\n#define RCC_CIFR_HSERDYF                       RCC_CIFR_HSERDYF_Msk\n#define RCC_CIFR_CSIRDYF_Pos                   (4U)\n#define RCC_CIFR_CSIRDYF_Msk                   (0x1UL << RCC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */\n#define RCC_CIFR_CSIRDYF                       RCC_CIFR_CSIRDYF_Msk\n#define RCC_CIFR_HSI48RDYF_Pos                 (5U)\n#define RCC_CIFR_HSI48RDYF_Msk                 (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000020 */\n#define RCC_CIFR_HSI48RDYF                     RCC_CIFR_HSI48RDYF_Msk\n#define RCC_CIFR_PLLRDYF_Pos                   (6U)\n#define RCC_CIFR_PLLRDYF_Msk                   (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000040 */\n#define RCC_CIFR_PLLRDYF                       RCC_CIFR_PLLRDYF_Msk\n#define RCC_CIFR_PLL2RDYF_Pos                  (7U)\n#define RCC_CIFR_PLL2RDYF_Msk                  (0x1UL << RCC_CIFR_PLL2RDYF_Pos) /*!< 0x00000080 */\n#define RCC_CIFR_PLL2RDYF                      RCC_CIFR_PLL2RDYF_Msk\n#define RCC_CIFR_PLL3RDYF_Pos                  (8U)\n#define RCC_CIFR_PLL3RDYF_Msk                  (0x1UL << RCC_CIFR_PLL3RDYF_Pos) /*!< 0x00000100 */\n#define RCC_CIFR_PLL3RDYF                      RCC_CIFR_PLL3RDYF_Msk\n#define RCC_CIFR_LSECSSF_Pos                   (9U)\n#define RCC_CIFR_LSECSSF_Msk                   (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */\n#define RCC_CIFR_LSECSSF                       RCC_CIFR_LSECSSF_Msk\n#define RCC_CIFR_HSECSSF_Pos                   (10U)\n#define RCC_CIFR_HSECSSF_Msk                   (0x1UL << RCC_CIFR_HSECSSF_Pos) /*!< 0x00000400 */\n#define RCC_CIFR_HSECSSF                       RCC_CIFR_HSECSSF_Msk\n\n/********************  Bit definition for RCC_CICR register  ******************/\n#define RCC_CICR_LSIRDYC_Pos                   (0U)\n#define RCC_CICR_LSIRDYC_Msk                   (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */\n#define RCC_CICR_LSIRDYC                       RCC_CICR_LSIRDYC_Msk\n#define RCC_CICR_LSERDYC_Pos                   (1U)\n#define RCC_CICR_LSERDYC_Msk                   (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */\n#define RCC_CICR_LSERDYC                       RCC_CICR_LSERDYC_Msk\n#define RCC_CICR_HSIRDYC_Pos                   (2U)\n#define RCC_CICR_HSIRDYC_Msk                   (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */\n#define RCC_CICR_HSIRDYC                       RCC_CICR_HSIRDYC_Msk\n#define RCC_CICR_HSERDYC_Pos                   (3U)\n#define RCC_CICR_HSERDYC_Msk                   (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */\n#define RCC_CICR_HSERDYC                       RCC_CICR_HSERDYC_Msk\n#define RCC_CICR_CSIRDYC_Pos                   (4U)\n#define RCC_CICR_CSIRDYC_Msk                   (0x1UL << RCC_CICR_CSIRDYC_Pos) /*!< 0x00000010 */\n#define RCC_CICR_CSIRDYC                       RCC_CICR_CSIRDYC_Msk\n#define RCC_CICR_HSI48RDYC_Pos                 (5U)\n#define RCC_CICR_HSI48RDYC_Msk                 (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000020 */\n#define RCC_CICR_HSI48RDYC                     RCC_CICR_HSI48RDYC_Msk\n#define RCC_CICR_PLLRDYC_Pos                   (6U)\n#define RCC_CICR_PLLRDYC_Msk                   (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000040 */\n#define RCC_CICR_PLLRDYC                       RCC_CICR_PLLRDYC_Msk\n#define RCC_CICR_PLL2RDYC_Pos                  (7U)\n#define RCC_CICR_PLL2RDYC_Msk                  (0x1UL << RCC_CICR_PLL2RDYC_Pos) /*!< 0x00000080 */\n#define RCC_CICR_PLL2RDYC                      RCC_CICR_PLL2RDYC_Msk\n#define RCC_CICR_PLL3RDYC_Pos                  (8U)\n#define RCC_CICR_PLL3RDYC_Msk                  (0x1UL << RCC_CICR_PLL3RDYC_Pos) /*!< 0x00000100 */\n#define RCC_CICR_PLL3RDYC                      RCC_CICR_PLL3RDYC_Msk\n#define RCC_CICR_LSECSSC_Pos                   (9U)\n#define RCC_CICR_LSECSSC_Msk                   (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */\n#define RCC_CICR_LSECSSC                       RCC_CICR_LSECSSC_Msk\n#define RCC_CICR_HSECSSC_Pos                   (10U)\n#define RCC_CICR_HSECSSC_Msk                   (0x1UL << RCC_CICR_HSECSSC_Pos) /*!< 0x00000400 */\n#define RCC_CICR_HSECSSC                       RCC_CICR_HSECSSC_Msk\n\n/********************  Bit definition for RCC_BDCR register  ******************/\n#define RCC_BDCR_LSEON_Pos                     (0U)\n#define RCC_BDCR_LSEON_Msk                     (0x1UL << RCC_BDCR_LSEON_Pos)   /*!< 0x00000001 */\n#define RCC_BDCR_LSEON                         RCC_BDCR_LSEON_Msk\n#define RCC_BDCR_LSERDY_Pos                    (1U)\n#define RCC_BDCR_LSERDY_Msk                    (0x1UL << RCC_BDCR_LSERDY_Pos)  /*!< 0x00000002 */\n#define RCC_BDCR_LSERDY                        RCC_BDCR_LSERDY_Msk\n#define RCC_BDCR_LSEBYP_Pos                    (2U)\n#define RCC_BDCR_LSEBYP_Msk                    (0x1UL << RCC_BDCR_LSEBYP_Pos)  /*!< 0x00000004 */\n#define RCC_BDCR_LSEBYP                        RCC_BDCR_LSEBYP_Msk\n\n#define RCC_BDCR_LSEDRV_Pos                    (3U)\n#define RCC_BDCR_LSEDRV_Msk                    (0x3UL << RCC_BDCR_LSEDRV_Pos)  /*!< 0x00000018 */\n#define RCC_BDCR_LSEDRV                        RCC_BDCR_LSEDRV_Msk\n#define RCC_BDCR_LSEDRV_0                      (0x1UL << RCC_BDCR_LSEDRV_Pos)   /*!< 0x00000008 */\n#define RCC_BDCR_LSEDRV_1                      (0x2UL << RCC_BDCR_LSEDRV_Pos)   /*!< 0x00000010 */\n\n#define RCC_BDCR_LSECSSON_Pos                  (5U)\n#define RCC_BDCR_LSECSSON_Msk                  (0x1UL << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */\n#define RCC_BDCR_LSECSSON                      RCC_BDCR_LSECSSON_Msk\n#define RCC_BDCR_LSECSSD_Pos                   (6U)\n#define RCC_BDCR_LSECSSD_Msk                   (0x1UL << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */\n#define RCC_BDCR_LSECSSD                       RCC_BDCR_LSECSSD_Msk\n\n#define RCC_BDCR_RTCSEL_Pos                    (8U)\n#define RCC_BDCR_RTCSEL_Msk                    (0x3UL << RCC_BDCR_RTCSEL_Pos)  /*!< 0x00000300 */\n#define RCC_BDCR_RTCSEL                        RCC_BDCR_RTCSEL_Msk\n#define RCC_BDCR_RTCSEL_0                      (0x1UL << RCC_BDCR_RTCSEL_Pos)   /*!< 0x00000100 */\n#define RCC_BDCR_RTCSEL_1                      (0x2UL << RCC_BDCR_RTCSEL_Pos)   /*!< 0x00000200 */\n\n#define RCC_BDCR_RTCEN_Pos                     (15U)\n#define RCC_BDCR_RTCEN_Msk                     (0x1UL << RCC_BDCR_RTCEN_Pos)   /*!< 0x00008000 */\n#define RCC_BDCR_RTCEN                         RCC_BDCR_RTCEN_Msk\n#define RCC_BDCR_BDRST_Pos                     (16U)\n#define RCC_BDCR_BDRST_Msk                     (0x1UL << RCC_BDCR_BDRST_Pos)   /*!< 0x00010000 */\n#define RCC_BDCR_BDRST                         RCC_BDCR_BDRST_Msk\n/********************  Bit definition for RCC_CSR register  *******************/\n#define RCC_CSR_LSION_Pos                      (0U)\n#define RCC_CSR_LSION_Msk                      (0x1UL << RCC_CSR_LSION_Pos)    /*!< 0x00000001 */\n#define RCC_CSR_LSION                          RCC_CSR_LSION_Msk\n#define RCC_CSR_LSIRDY_Pos                     (1U)\n#define RCC_CSR_LSIRDY_Msk                     (0x1UL << RCC_CSR_LSIRDY_Pos)   /*!< 0x00000002 */\n#define RCC_CSR_LSIRDY                         RCC_CSR_LSIRDY_Msk\n\n\n/********************  Bit definition for RCC_AHB3ENR register  **************/\n#define RCC_AHB3ENR_MDMAEN_Pos                 (0U)\n#define RCC_AHB3ENR_MDMAEN_Msk                 (0x1UL << RCC_AHB3ENR_MDMAEN_Pos)       /*!< 0x00000001 */\n#define RCC_AHB3ENR_MDMAEN                     RCC_AHB3ENR_MDMAEN_Msk\n#define RCC_AHB3ENR_DMA2DEN_Pos                (4U)\n#define RCC_AHB3ENR_DMA2DEN_Msk                (0x1UL << RCC_AHB3ENR_DMA2DEN_Pos)      /*!< 0x00000010 */\n#define RCC_AHB3ENR_DMA2DEN                    RCC_AHB3ENR_DMA2DEN_Msk\n#define RCC_AHB3ENR_JPGDECEN_Pos               (5U)\n#define RCC_AHB3ENR_JPGDECEN_Msk               (0x1UL << RCC_AHB3ENR_JPGDECEN_Pos)     /*!< 0x00000020 */\n#define RCC_AHB3ENR_JPGDECEN                   RCC_AHB3ENR_JPGDECEN_Msk\n#define RCC_AHB3ENR_FMCEN_Pos                  (12U)\n#define RCC_AHB3ENR_FMCEN_Msk                  (0x1UL << RCC_AHB3ENR_FMCEN_Pos)        /*!< 0x00001000 */\n#define RCC_AHB3ENR_FMCEN                      RCC_AHB3ENR_FMCEN_Msk\n#define RCC_AHB3ENR_QSPIEN_Pos                 (14U)\n#define RCC_AHB3ENR_QSPIEN_Msk                 (0x1UL << RCC_AHB3ENR_QSPIEN_Pos)       /*!< 0x00004000 */\n#define RCC_AHB3ENR_QSPIEN                     RCC_AHB3ENR_QSPIEN_Msk\n#define RCC_AHB3ENR_SDMMC1EN_Pos               (16U)\n#define RCC_AHB3ENR_SDMMC1EN_Msk               (0x1UL << RCC_AHB3ENR_SDMMC1EN_Pos)     /*!< 0x00010000 */\n#define RCC_AHB3ENR_SDMMC1EN                   RCC_AHB3ENR_SDMMC1EN_Msk\n\n/********************  Bit definition for RCC_AHB1ENR register  ***************/\n#define RCC_AHB1ENR_DMA1EN_Pos                 (0U)\n#define RCC_AHB1ENR_DMA1EN_Msk                 (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)          /*!< 0x00000001 */\n#define RCC_AHB1ENR_DMA1EN                     RCC_AHB1ENR_DMA1EN_Msk\n#define RCC_AHB1ENR_DMA2EN_Pos                 (1U)\n#define RCC_AHB1ENR_DMA2EN_Msk                 (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)          /*!< 0x00000002 */\n#define RCC_AHB1ENR_DMA2EN                     RCC_AHB1ENR_DMA2EN_Msk\n#define RCC_AHB1ENR_ADC12EN_Pos                (5U)\n#define RCC_AHB1ENR_ADC12EN_Msk                (0x1UL << RCC_AHB1ENR_ADC12EN_Pos)         /*!< 0x00000020 */\n#define RCC_AHB1ENR_ADC12EN                    RCC_AHB1ENR_ADC12EN_Msk\n#define RCC_AHB1ENR_ETH1MACEN_Pos              (15U)\n#define RCC_AHB1ENR_ETH1MACEN_Msk              (0x1UL << RCC_AHB1ENR_ETH1MACEN_Pos)       /*!< 0x00008000 */\n#define RCC_AHB1ENR_ETH1MACEN                  RCC_AHB1ENR_ETH1MACEN_Msk\n#define RCC_AHB1ENR_ETH1TXEN_Pos               (16U)\n#define RCC_AHB1ENR_ETH1TXEN_Msk               (0x1UL << RCC_AHB1ENR_ETH1TXEN_Pos)        /*!< 0x00010000 */\n#define RCC_AHB1ENR_ETH1TXEN                   RCC_AHB1ENR_ETH1TXEN_Msk\n#define RCC_AHB1ENR_ETH1RXEN_Pos               (17U)\n#define RCC_AHB1ENR_ETH1RXEN_Msk               (0x1UL << RCC_AHB1ENR_ETH1RXEN_Pos)        /*!< 0x00020000 */\n#define RCC_AHB1ENR_ETH1RXEN                   RCC_AHB1ENR_ETH1RXEN_Msk\n#define RCC_AHB1ENR_USB1OTGHSEN_Pos            (25U)\n#define RCC_AHB1ENR_USB1OTGHSEN_Msk            (0x1UL << RCC_AHB1ENR_USB1OTGHSEN_Pos)     /*!< 0x02000000 */\n#define RCC_AHB1ENR_USB1OTGHSEN                RCC_AHB1ENR_USB1OTGHSEN_Msk\n#define RCC_AHB1ENR_USB1OTGHSULPIEN_Pos        (26U)\n#define RCC_AHB1ENR_USB1OTGHSULPIEN_Msk        (0x1UL << RCC_AHB1ENR_USB1OTGHSULPIEN_Pos) /*!< 0x04000000 */\n#define RCC_AHB1ENR_USB1OTGHSULPIEN            RCC_AHB1ENR_USB1OTGHSULPIEN_Msk\n#define RCC_AHB1ENR_USB2OTGFSEN_Pos            (27U)\n#define RCC_AHB1ENR_USB2OTGFSEN_Msk            (0x1UL << RCC_AHB1ENR_USB2OTGFSEN_Pos)     /*!< 0x08000000 */\n#define RCC_AHB1ENR_USB2OTGFSEN                RCC_AHB1ENR_USB2OTGFSEN_Msk\n#define RCC_AHB1ENR_USB2OTGFSULPIEN_Pos        (28U)\n#define RCC_AHB1ENR_USB2OTGFSULPIEN_Msk        (0x1UL << RCC_AHB1ENR_USB2OTGFSULPIEN_Pos) /*!< 0x10000000 */\n#define RCC_AHB1ENR_USB2OTGFSULPIEN            RCC_AHB1ENR_USB2OTGFSULPIEN_Msk\n\n/* Legacy define */\n#define RCC_AHB1ENR_USB2OTGHSEN_Pos            RCC_AHB1ENR_USB2OTGFSEN_Pos\n#define RCC_AHB1ENR_USB2OTGHSEN_Msk            RCC_AHB1ENR_USB2OTGFSEN_Msk\n#define RCC_AHB1ENR_USB2OTGHSEN                RCC_AHB1ENR_USB2OTGFSEN\n#define RCC_AHB1ENR_USB2OTGHSULPIEN_Pos        RCC_AHB1ENR_USB2OTGFSULPIEN_Pos\n#define RCC_AHB1ENR_USB2OTGHSULPIEN_Msk        RCC_AHB1ENR_USB2OTGFSULPIEN_Msk\n#define RCC_AHB1ENR_USB2OTGHSULPIEN            RCC_AHB1ENR_USB2OTGFSULPIEN\n\n\n/********************  Bit definition for RCC_AHB2ENR register  ***************/\n#define RCC_AHB2ENR_DCMIEN_Pos                 (0U)\n#define RCC_AHB2ENR_DCMIEN_Msk                 (0x1UL << RCC_AHB2ENR_DCMIEN_Pos)          /*!< 0x00000001 */\n#define RCC_AHB2ENR_DCMIEN                     RCC_AHB2ENR_DCMIEN_Msk\n#define RCC_AHB2ENR_RNGEN_Pos                  (6U)\n#define RCC_AHB2ENR_RNGEN_Msk                  (0x1UL << RCC_AHB2ENR_RNGEN_Pos)           /*!< 0x00000040 */\n#define RCC_AHB2ENR_RNGEN                      RCC_AHB2ENR_RNGEN_Msk\n#define RCC_AHB2ENR_SDMMC2EN_Pos               (9U)\n#define RCC_AHB2ENR_SDMMC2EN_Msk               (0x1UL << RCC_AHB2ENR_SDMMC2EN_Pos)        /*!< 0x00000200 */\n#define RCC_AHB2ENR_SDMMC2EN                   RCC_AHB2ENR_SDMMC2EN_Msk\n#define RCC_AHB2ENR_SRAM1EN_Pos                (29U)\n#define RCC_AHB2ENR_SRAM1EN_Msk                (0x1UL << RCC_AHB2ENR_SRAM1EN_Pos)       /*!< 0x20000000 */\n#define RCC_AHB2ENR_SRAM1EN                    RCC_AHB2ENR_SRAM1EN_Msk\n#define RCC_AHB2ENR_SRAM2EN_Pos                (30U)\n#define RCC_AHB2ENR_SRAM2EN_Msk                (0x1UL << RCC_AHB2ENR_SRAM2EN_Pos)       /*!< 0x40000000 */\n#define RCC_AHB2ENR_SRAM2EN                    RCC_AHB2ENR_SRAM2EN_Msk\n#define RCC_AHB2ENR_SRAM3EN_Pos                (31U)\n#define RCC_AHB2ENR_SRAM3EN_Msk                (0x1UL << RCC_AHB2ENR_SRAM3EN_Pos)       /*!< 0x80000000 */\n#define RCC_AHB2ENR_SRAM3EN                    RCC_AHB2ENR_SRAM3EN_Msk\n\n/* Legacy define */\n#define RCC_AHB2ENR_D2SRAM1EN_Pos              RCC_AHB2ENR_SRAM1EN_Pos\n#define RCC_AHB2ENR_D2SRAM1EN_Msk              RCC_AHB2ENR_SRAM1EN_Msk\n#define RCC_AHB2ENR_D2SRAM1EN                  RCC_AHB2ENR_SRAM1EN\n#define RCC_AHB2ENR_D2SRAM2EN_Pos              RCC_AHB2ENR_SRAM2EN_Pos\n#define RCC_AHB2ENR_D2SRAM2EN_Msk              RCC_AHB2ENR_SRAM2EN_Msk\n#define RCC_AHB2ENR_D2SRAM2EN                  RCC_AHB2ENR_SRAM2EN\n#define RCC_AHB2ENR_D2SRAM3EN_Pos              RCC_AHB2ENR_SRAM3EN_Pos\n#define RCC_AHB2ENR_D2SRAM3EN_Msk              RCC_AHB2ENR_SRAM3EN_Msk\n#define RCC_AHB2ENR_D2SRAM3EN                  RCC_AHB2ENR_SRAM3EN\n\n/********************  Bit definition for RCC_AHB4ENR register  ******************/\n#define RCC_AHB4ENR_GPIOAEN_Pos                (0U)\n#define RCC_AHB4ENR_GPIOAEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOAEN_Pos)         /*!< 0x00000001 */\n#define RCC_AHB4ENR_GPIOAEN                    RCC_AHB4ENR_GPIOAEN_Msk\n#define RCC_AHB4ENR_GPIOBEN_Pos                (1U)\n#define RCC_AHB4ENR_GPIOBEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOBEN_Pos)         /*!< 0x00000002 */\n#define RCC_AHB4ENR_GPIOBEN                    RCC_AHB4ENR_GPIOBEN_Msk\n#define RCC_AHB4ENR_GPIOCEN_Pos                (2U)\n#define RCC_AHB4ENR_GPIOCEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOCEN_Pos)         /*!< 0x00000004 */\n#define RCC_AHB4ENR_GPIOCEN                    RCC_AHB4ENR_GPIOCEN_Msk\n#define RCC_AHB4ENR_GPIODEN_Pos                (3U)\n#define RCC_AHB4ENR_GPIODEN_Msk                (0x1UL << RCC_AHB4ENR_GPIODEN_Pos)         /*!< 0x00000008 */\n#define RCC_AHB4ENR_GPIODEN                    RCC_AHB4ENR_GPIODEN_Msk\n#define RCC_AHB4ENR_GPIOEEN_Pos                (4U)\n#define RCC_AHB4ENR_GPIOEEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOEEN_Pos)         /*!< 0x00000010 */\n#define RCC_AHB4ENR_GPIOEEN                    RCC_AHB4ENR_GPIOEEN_Msk\n#define RCC_AHB4ENR_GPIOFEN_Pos                (5U)\n#define RCC_AHB4ENR_GPIOFEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOFEN_Pos)         /*!< 0x00000020 */\n#define RCC_AHB4ENR_GPIOFEN                    RCC_AHB4ENR_GPIOFEN_Msk\n#define RCC_AHB4ENR_GPIOGEN_Pos                (6U)\n#define RCC_AHB4ENR_GPIOGEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOGEN_Pos)         /*!< 0x00000040 */\n#define RCC_AHB4ENR_GPIOGEN                    RCC_AHB4ENR_GPIOGEN_Msk\n#define RCC_AHB4ENR_GPIOHEN_Pos                (7U)\n#define RCC_AHB4ENR_GPIOHEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOHEN_Pos)         /*!< 0x00000080 */\n#define RCC_AHB4ENR_GPIOHEN                    RCC_AHB4ENR_GPIOHEN_Msk\n#define RCC_AHB4ENR_GPIOIEN_Pos                (8U)\n#define RCC_AHB4ENR_GPIOIEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOIEN_Pos)         /*!< 0x00000100 */\n#define RCC_AHB4ENR_GPIOIEN                    RCC_AHB4ENR_GPIOIEN_Msk\n#define RCC_AHB4ENR_GPIOJEN_Pos                (9U)\n#define RCC_AHB4ENR_GPIOJEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOJEN_Pos)         /*!< 0x00000200 */\n#define RCC_AHB4ENR_GPIOJEN                    RCC_AHB4ENR_GPIOJEN_Msk\n#define RCC_AHB4ENR_GPIOKEN_Pos                (10U)\n#define RCC_AHB4ENR_GPIOKEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOKEN_Pos)         /*!< 0x00000400 */\n#define RCC_AHB4ENR_GPIOKEN                    RCC_AHB4ENR_GPIOKEN_Msk\n#define RCC_AHB4ENR_CRCEN_Pos                  (19U)\n#define RCC_AHB4ENR_CRCEN_Msk                  (0x1UL << RCC_AHB4ENR_CRCEN_Pos)           /*!< 0x00080000 */\n#define RCC_AHB4ENR_CRCEN                      RCC_AHB4ENR_CRCEN_Msk\n#define RCC_AHB4ENR_BDMAEN_Pos                 (21U)\n#define RCC_AHB4ENR_BDMAEN_Msk                 (0x1UL << RCC_AHB4ENR_BDMAEN_Pos)          /*!< 0x00200000 */\n#define RCC_AHB4ENR_BDMAEN                     RCC_AHB4ENR_BDMAEN_Msk\n#define RCC_AHB4ENR_ADC3EN_Pos                 (24U)\n#define RCC_AHB4ENR_ADC3EN_Msk                 (0x1UL << RCC_AHB4ENR_ADC3EN_Pos)          /*!< 0x01000000 */\n#define RCC_AHB4ENR_ADC3EN                     RCC_AHB4ENR_ADC3EN_Msk\n#define RCC_AHB4ENR_HSEMEN_Pos                 (25U)\n#define RCC_AHB4ENR_HSEMEN_Msk                 (0x1UL << RCC_AHB4ENR_HSEMEN_Pos)          /*!< 0x02000000 */\n#define RCC_AHB4ENR_HSEMEN                     RCC_AHB4ENR_HSEMEN_Msk\n#define RCC_AHB4ENR_BKPRAMEN_Pos               (28U)\n#define RCC_AHB4ENR_BKPRAMEN_Msk               (0x1UL << RCC_AHB4ENR_BKPRAMEN_Pos)        /*!< 0x10000000 */\n#define RCC_AHB4ENR_BKPRAMEN                   RCC_AHB4ENR_BKPRAMEN_Msk\n\n/********************  Bit definition for RCC_APB3ENR register  ******************/\n#define RCC_APB3ENR_LTDCEN_Pos                 (3U)\n#define RCC_APB3ENR_LTDCEN_Msk                 (0x1UL << RCC_APB3ENR_LTDCEN_Pos) /*!< 0x00000008 */\n#define RCC_APB3ENR_LTDCEN                     RCC_APB3ENR_LTDCEN_Msk\n#define RCC_APB3ENR_WWDG1EN_Pos                (6U)\n#define RCC_APB3ENR_WWDG1EN_Msk                (0x1UL << RCC_APB3ENR_WWDG1EN_Pos) /*!< 0x00000040 */\n#define RCC_APB3ENR_WWDG1EN                    RCC_APB3ENR_WWDG1EN_Msk\n\n/********************  Bit definition for RCC_APB1LENR register  ******************/\n\n#define RCC_APB1LENR_TIM2EN_Pos                (0U)\n#define RCC_APB1LENR_TIM2EN_Msk                (0x1UL << RCC_APB1LENR_TIM2EN_Pos) /*!< 0x00000001 */\n#define RCC_APB1LENR_TIM2EN                    RCC_APB1LENR_TIM2EN_Msk\n#define RCC_APB1LENR_TIM3EN_Pos                (1U)\n#define RCC_APB1LENR_TIM3EN_Msk                (0x1UL << RCC_APB1LENR_TIM3EN_Pos) /*!< 0x00000002 */\n#define RCC_APB1LENR_TIM3EN                    RCC_APB1LENR_TIM3EN_Msk\n#define RCC_APB1LENR_TIM4EN_Pos                (2U)\n#define RCC_APB1LENR_TIM4EN_Msk                (0x1UL << RCC_APB1LENR_TIM4EN_Pos) /*!< 0x00000004 */\n#define RCC_APB1LENR_TIM4EN                    RCC_APB1LENR_TIM4EN_Msk\n#define RCC_APB1LENR_TIM5EN_Pos                (3U)\n#define RCC_APB1LENR_TIM5EN_Msk                (0x1UL << RCC_APB1LENR_TIM5EN_Pos) /*!< 0x00000008 */\n#define RCC_APB1LENR_TIM5EN                    RCC_APB1LENR_TIM5EN_Msk\n#define RCC_APB1LENR_TIM6EN_Pos                (4U)\n#define RCC_APB1LENR_TIM6EN_Msk                (0x1UL << RCC_APB1LENR_TIM6EN_Pos) /*!< 0x00000010 */\n#define RCC_APB1LENR_TIM6EN                    RCC_APB1LENR_TIM6EN_Msk\n#define RCC_APB1LENR_TIM7EN_Pos                (5U)\n#define RCC_APB1LENR_TIM7EN_Msk                (0x1UL << RCC_APB1LENR_TIM7EN_Pos) /*!< 0x00000020 */\n#define RCC_APB1LENR_TIM7EN                    RCC_APB1LENR_TIM7EN_Msk\n#define RCC_APB1LENR_TIM12EN_Pos               (6U)\n#define RCC_APB1LENR_TIM12EN_Msk               (0x1UL << RCC_APB1LENR_TIM12EN_Pos) /*!< 0x00000040 */\n#define RCC_APB1LENR_TIM12EN                   RCC_APB1LENR_TIM12EN_Msk\n#define RCC_APB1LENR_TIM13EN_Pos               (7U)\n#define RCC_APB1LENR_TIM13EN_Msk               (0x1UL << RCC_APB1LENR_TIM13EN_Pos) /*!< 0x00000080 */\n#define RCC_APB1LENR_TIM13EN                   RCC_APB1LENR_TIM13EN_Msk\n#define RCC_APB1LENR_TIM14EN_Pos               (8U)\n#define RCC_APB1LENR_TIM14EN_Msk               (0x1UL << RCC_APB1LENR_TIM14EN_Pos) /*!< 0x00000100 */\n#define RCC_APB1LENR_TIM14EN                   RCC_APB1LENR_TIM14EN_Msk\n#define RCC_APB1LENR_LPTIM1EN_Pos              (9U)\n#define RCC_APB1LENR_LPTIM1EN_Msk              (0x1UL << RCC_APB1LENR_LPTIM1EN_Pos) /*!< 0x00000200 */\n#define RCC_APB1LENR_LPTIM1EN                  RCC_APB1LENR_LPTIM1EN_Msk\n\n\n#define RCC_APB1LENR_SPI2EN_Pos                (14U)\n#define RCC_APB1LENR_SPI2EN_Msk                (0x1UL << RCC_APB1LENR_SPI2EN_Pos) /*!< 0x00004000 */\n#define RCC_APB1LENR_SPI2EN                    RCC_APB1LENR_SPI2EN_Msk\n#define RCC_APB1LENR_SPI3EN_Pos                (15U)\n#define RCC_APB1LENR_SPI3EN_Msk                (0x1UL << RCC_APB1LENR_SPI3EN_Pos) /*!< 0x00008000 */\n#define RCC_APB1LENR_SPI3EN                    RCC_APB1LENR_SPI3EN_Msk\n#define RCC_APB1LENR_SPDIFRXEN_Pos             (16U)\n#define RCC_APB1LENR_SPDIFRXEN_Msk             (0x1UL << RCC_APB1LENR_SPDIFRXEN_Pos) /*!< 0x00010000 */\n#define RCC_APB1LENR_SPDIFRXEN                 RCC_APB1LENR_SPDIFRXEN_Msk\n#define RCC_APB1LENR_USART2EN_Pos              (17U)\n#define RCC_APB1LENR_USART2EN_Msk              (0x1UL << RCC_APB1LENR_USART2EN_Pos) /*!< 0x00020000 */\n#define RCC_APB1LENR_USART2EN                  RCC_APB1LENR_USART2EN_Msk\n#define RCC_APB1LENR_USART3EN_Pos              (18U)\n#define RCC_APB1LENR_USART3EN_Msk              (0x1UL << RCC_APB1LENR_USART3EN_Pos) /*!< 0x00040000 */\n#define RCC_APB1LENR_USART3EN                  RCC_APB1LENR_USART3EN_Msk\n#define RCC_APB1LENR_UART4EN_Pos               (19U)\n#define RCC_APB1LENR_UART4EN_Msk               (0x1UL << RCC_APB1LENR_UART4EN_Pos) /*!< 0x00080000 */\n#define RCC_APB1LENR_UART4EN                   RCC_APB1LENR_UART4EN_Msk\n#define RCC_APB1LENR_UART5EN_Pos               (20U)\n#define RCC_APB1LENR_UART5EN_Msk               (0x1UL << RCC_APB1LENR_UART5EN_Pos) /*!< 0x00100000 */\n#define RCC_APB1LENR_UART5EN                   RCC_APB1LENR_UART5EN_Msk\n#define RCC_APB1LENR_I2C1EN_Pos                (21U)\n#define RCC_APB1LENR_I2C1EN_Msk                (0x1UL << RCC_APB1LENR_I2C1EN_Pos) /*!< 0x00200000 */\n#define RCC_APB1LENR_I2C1EN                    RCC_APB1LENR_I2C1EN_Msk\n#define RCC_APB1LENR_I2C2EN_Pos                (22U)\n#define RCC_APB1LENR_I2C2EN_Msk                (0x1UL << RCC_APB1LENR_I2C2EN_Pos) /*!< 0x00400000 */\n#define RCC_APB1LENR_I2C2EN                    RCC_APB1LENR_I2C2EN_Msk\n#define RCC_APB1LENR_I2C3EN_Pos                (23U)\n#define RCC_APB1LENR_I2C3EN_Msk                (0x1UL << RCC_APB1LENR_I2C3EN_Pos) /*!< 0x00800000 */\n#define RCC_APB1LENR_I2C3EN                    RCC_APB1LENR_I2C3EN_Msk\n#define RCC_APB1LENR_CECEN_Pos                 (27U)\n#define RCC_APB1LENR_CECEN_Msk                 (0x1UL << RCC_APB1LENR_CECEN_Pos) /*!< 0x08000000 */\n#define RCC_APB1LENR_CECEN                     RCC_APB1LENR_CECEN_Msk\n#define RCC_APB1LENR_DAC12EN_Pos               (29U)\n#define RCC_APB1LENR_DAC12EN_Msk               (0x1UL << RCC_APB1LENR_DAC12EN_Pos) /*!< 0x20000000 */\n#define RCC_APB1LENR_DAC12EN                   RCC_APB1LENR_DAC12EN_Msk\n#define RCC_APB1LENR_UART7EN_Pos               (30U)\n#define RCC_APB1LENR_UART7EN_Msk               (0x1UL << RCC_APB1LENR_UART7EN_Pos) /*!< 0x40000000 */\n#define RCC_APB1LENR_UART7EN                   RCC_APB1LENR_UART7EN_Msk\n#define RCC_APB1LENR_UART8EN_Pos               (31U)\n#define RCC_APB1LENR_UART8EN_Msk               (0x1UL << RCC_APB1LENR_UART8EN_Pos) /*!< 0x80000000 */\n#define RCC_APB1LENR_UART8EN                   RCC_APB1LENR_UART8EN_Msk\n\n/* Legacy define */\n#define RCC_APB1LENR_HDMICECEN_Pos             RCC_APB1LENR_CECEN_Pos\n#define RCC_APB1LENR_HDMICECEN_Msk             RCC_APB1LENR_CECEN_Msk\n#define RCC_APB1LENR_HDMICECEN                 RCC_APB1LENR_CECEN\n/********************  Bit definition for RCC_APB1HENR register  ******************/\n#define RCC_APB1HENR_CRSEN_Pos                 (1U)\n#define RCC_APB1HENR_CRSEN_Msk                 (0x1UL << RCC_APB1HENR_CRSEN_Pos) /*!< 0x00000002 */\n#define RCC_APB1HENR_CRSEN                     RCC_APB1HENR_CRSEN_Msk\n#define RCC_APB1HENR_SWPMIEN_Pos               (2U)\n#define RCC_APB1HENR_SWPMIEN_Msk               (0x1UL << RCC_APB1HENR_SWPMIEN_Pos) /*!< 0x00000004 */\n#define RCC_APB1HENR_SWPMIEN                   RCC_APB1HENR_SWPMIEN_Msk\n#define RCC_APB1HENR_OPAMPEN_Pos               (4U)\n#define RCC_APB1HENR_OPAMPEN_Msk               (0x1UL << RCC_APB1HENR_OPAMPEN_Pos) /*!< 0x00000010 */\n#define RCC_APB1HENR_OPAMPEN                   RCC_APB1HENR_OPAMPEN_Msk\n#define RCC_APB1HENR_MDIOSEN_Pos               (5U)\n#define RCC_APB1HENR_MDIOSEN_Msk               (0x1UL << RCC_APB1HENR_MDIOSEN_Pos) /*!< 0x00000020 */\n#define RCC_APB1HENR_MDIOSEN                   RCC_APB1HENR_MDIOSEN_Msk\n#define RCC_APB1HENR_FDCANEN_Pos               (8U)\n#define RCC_APB1HENR_FDCANEN_Msk               (0x1UL << RCC_APB1HENR_FDCANEN_Pos) /*!< 0x00000100 */\n#define RCC_APB1HENR_FDCANEN                   RCC_APB1HENR_FDCANEN_Msk\n\n/********************  Bit definition for RCC_APB2ENR register  ******************/\n#define RCC_APB2ENR_TIM1EN_Pos                 (0U)\n#define RCC_APB2ENR_TIM1EN_Msk                 (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */\n#define RCC_APB2ENR_TIM1EN                     RCC_APB2ENR_TIM1EN_Msk\n#define RCC_APB2ENR_TIM8EN_Pos                 (1U)\n#define RCC_APB2ENR_TIM8EN_Msk                 (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */\n#define RCC_APB2ENR_TIM8EN                     RCC_APB2ENR_TIM8EN_Msk\n#define RCC_APB2ENR_USART1EN_Pos               (4U)\n#define RCC_APB2ENR_USART1EN_Msk               (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */\n#define RCC_APB2ENR_USART1EN                   RCC_APB2ENR_USART1EN_Msk\n#define RCC_APB2ENR_USART6EN_Pos               (5U)\n#define RCC_APB2ENR_USART6EN_Msk               (0x1UL << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */\n#define RCC_APB2ENR_USART6EN                   RCC_APB2ENR_USART6EN_Msk\n#define RCC_APB2ENR_SPI1EN_Pos                 (12U)\n#define RCC_APB2ENR_SPI1EN_Msk                 (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */\n#define RCC_APB2ENR_SPI1EN                     RCC_APB2ENR_SPI1EN_Msk\n#define RCC_APB2ENR_SPI4EN_Pos                 (13U)\n#define RCC_APB2ENR_SPI4EN_Msk                 (0x1UL << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */\n#define RCC_APB2ENR_SPI4EN                     RCC_APB2ENR_SPI4EN_Msk\n#define RCC_APB2ENR_TIM15EN_Pos                (16U)\n#define RCC_APB2ENR_TIM15EN_Msk                (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */\n#define RCC_APB2ENR_TIM15EN                    RCC_APB2ENR_TIM15EN_Msk\n#define RCC_APB2ENR_TIM16EN_Pos                (17U)\n#define RCC_APB2ENR_TIM16EN_Msk                (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */\n#define RCC_APB2ENR_TIM16EN                    RCC_APB2ENR_TIM16EN_Msk\n#define RCC_APB2ENR_TIM17EN_Pos                (18U)\n#define RCC_APB2ENR_TIM17EN_Msk                (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */\n#define RCC_APB2ENR_TIM17EN                    RCC_APB2ENR_TIM17EN_Msk\n#define RCC_APB2ENR_SPI5EN_Pos                 (20U)\n#define RCC_APB2ENR_SPI5EN_Msk                 (0x1UL << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */\n#define RCC_APB2ENR_SPI5EN                     RCC_APB2ENR_SPI5EN_Msk\n#define RCC_APB2ENR_SAI1EN_Pos                 (22U)\n#define RCC_APB2ENR_SAI1EN_Msk                 (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */\n#define RCC_APB2ENR_SAI1EN                     RCC_APB2ENR_SAI1EN_Msk\n#define RCC_APB2ENR_SAI2EN_Pos                 (23U)\n#define RCC_APB2ENR_SAI2EN_Msk                 (0x1UL << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00800000 */\n#define RCC_APB2ENR_SAI2EN                     RCC_APB2ENR_SAI2EN_Msk\n#define RCC_APB2ENR_SAI3EN_Pos                 (24U)\n#define RCC_APB2ENR_SAI3EN_Msk                 (0x1UL << RCC_APB2ENR_SAI3EN_Pos) /*!< 0x01000000 */\n#define RCC_APB2ENR_SAI3EN                     RCC_APB2ENR_SAI3EN_Msk\n#define RCC_APB2ENR_DFSDM1EN_Pos               (28U)\n#define RCC_APB2ENR_DFSDM1EN_Msk               (0x1UL << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x10000000 */\n#define RCC_APB2ENR_DFSDM1EN                   RCC_APB2ENR_DFSDM1EN_Msk\n#define RCC_APB2ENR_HRTIMEN_Pos                (29U)\n#define RCC_APB2ENR_HRTIMEN_Msk                (0x1UL << RCC_APB2ENR_HRTIMEN_Pos) /*!< 0x20000000 */\n#define RCC_APB2ENR_HRTIMEN                    RCC_APB2ENR_HRTIMEN_Msk\n\n/********************  Bit definition for RCC_APB4ENR register  ******************/\n#define RCC_APB4ENR_SYSCFGEN_Pos               (1U)\n#define RCC_APB4ENR_SYSCFGEN_Msk               (0x1UL << RCC_APB4ENR_SYSCFGEN_Pos) /*!< 0x00000002 */\n#define RCC_APB4ENR_SYSCFGEN                   RCC_APB4ENR_SYSCFGEN_Msk\n#define RCC_APB4ENR_LPUART1EN_Pos              (3U)\n#define RCC_APB4ENR_LPUART1EN_Msk              (0x1UL << RCC_APB4ENR_LPUART1EN_Pos) /*!< 0x00000008 */\n#define RCC_APB4ENR_LPUART1EN                  RCC_APB4ENR_LPUART1EN_Msk\n#define RCC_APB4ENR_SPI6EN_Pos                 (5U)\n#define RCC_APB4ENR_SPI6EN_Msk                 (0x1UL << RCC_APB4ENR_SPI6EN_Pos) /*!< 0x00000020 */\n#define RCC_APB4ENR_SPI6EN                     RCC_APB4ENR_SPI6EN_Msk\n#define RCC_APB4ENR_I2C4EN_Pos                 (7U)\n#define RCC_APB4ENR_I2C4EN_Msk                 (0x1UL << RCC_APB4ENR_I2C4EN_Pos) /*!< 0x00000080 */\n#define RCC_APB4ENR_I2C4EN                     RCC_APB4ENR_I2C4EN_Msk\n#define RCC_APB4ENR_LPTIM2EN_Pos               (9U)\n#define RCC_APB4ENR_LPTIM2EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM2EN_Pos) /*!< 0x00000200 */\n#define RCC_APB4ENR_LPTIM2EN                   RCC_APB4ENR_LPTIM2EN_Msk\n#define RCC_APB4ENR_LPTIM3EN_Pos               (10U)\n#define RCC_APB4ENR_LPTIM3EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM3EN_Pos) /*!< 0x00000400 */\n#define RCC_APB4ENR_LPTIM3EN                   RCC_APB4ENR_LPTIM3EN_Msk\n#define RCC_APB4ENR_LPTIM4EN_Pos               (11U)\n#define RCC_APB4ENR_LPTIM4EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM4EN_Pos) /*!< 0x00000800 */\n#define RCC_APB4ENR_LPTIM4EN                   RCC_APB4ENR_LPTIM4EN_Msk\n#define RCC_APB4ENR_LPTIM5EN_Pos               (12U)\n#define RCC_APB4ENR_LPTIM5EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM5EN_Pos) /*!< 0x00001000 */\n#define RCC_APB4ENR_LPTIM5EN                   RCC_APB4ENR_LPTIM5EN_Msk\n#define RCC_APB4ENR_COMP12EN_Pos               (14U)\n#define RCC_APB4ENR_COMP12EN_Msk               (0x1UL << RCC_APB4ENR_COMP12EN_Pos) /*!< 0x00004000 */\n#define RCC_APB4ENR_COMP12EN                   RCC_APB4ENR_COMP12EN_Msk\n#define RCC_APB4ENR_VREFEN_Pos                 (15U)\n#define RCC_APB4ENR_VREFEN_Msk                 (0x1UL << RCC_APB4ENR_VREFEN_Pos) /*!< 0x00008000 */\n#define RCC_APB4ENR_VREFEN                     RCC_APB4ENR_VREFEN_Msk\n#define RCC_APB4ENR_RTCAPBEN_Pos               (16U)\n#define RCC_APB4ENR_RTCAPBEN_Msk               (0x1UL << RCC_APB4ENR_RTCAPBEN_Pos) /*!< 0x00010000 */\n#define RCC_APB4ENR_RTCAPBEN                   RCC_APB4ENR_RTCAPBEN_Msk\n#define RCC_APB4ENR_SAI4EN_Pos                 (21U)\n#define RCC_APB4ENR_SAI4EN_Msk                 (0x1UL << RCC_APB4ENR_SAI4EN_Pos) /*!< 0x00200000 */\n#define RCC_APB4ENR_SAI4EN                     RCC_APB4ENR_SAI4EN_Msk\n\n\n/********************  Bit definition for RCC_AHB3RSTR register  ***************/\n#define RCC_AHB3RSTR_MDMARST_Pos               (0U)\n#define RCC_AHB3RSTR_MDMARST_Msk               (0x1UL << RCC_AHB3RSTR_MDMARST_Pos)      /*!< 0x00000001 */\n#define RCC_AHB3RSTR_MDMARST                   RCC_AHB3RSTR_MDMARST_Msk\n#define RCC_AHB3RSTR_DMA2DRST_Pos              (4U)\n#define RCC_AHB3RSTR_DMA2DRST_Msk              (0x1UL << RCC_AHB3RSTR_DMA2DRST_Pos)     /*!< 0x00000010 */\n#define RCC_AHB3RSTR_DMA2DRST                  RCC_AHB3RSTR_DMA2DRST_Msk\n#define RCC_AHB3RSTR_JPGDECRST_Pos             (5U)\n#define RCC_AHB3RSTR_JPGDECRST_Msk             (0x1UL << RCC_AHB3RSTR_JPGDECRST_Pos)    /*!< 0x00000020 */\n#define RCC_AHB3RSTR_JPGDECRST                 RCC_AHB3RSTR_JPGDECRST_Msk\n#define RCC_AHB3RSTR_FMCRST_Pos                (12U)\n#define RCC_AHB3RSTR_FMCRST_Msk                (0x1UL << RCC_AHB3RSTR_FMCRST_Pos)      /*!< 0x00001000 */\n#define RCC_AHB3RSTR_FMCRST                    RCC_AHB3RSTR_FMCRST_Msk\n#define RCC_AHB3RSTR_QSPIRST_Pos               (14U)\n#define RCC_AHB3RSTR_QSPIRST_Msk               (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos)     /*!< 0x00004000 */\n#define RCC_AHB3RSTR_QSPIRST                   RCC_AHB3RSTR_QSPIRST_Msk\n#define RCC_AHB3RSTR_SDMMC1RST_Pos             (16U)\n#define RCC_AHB3RSTR_SDMMC1RST_Msk             (0x1UL << RCC_AHB3RSTR_SDMMC1RST_Pos)   /*!< 0x00010000 */\n#define RCC_AHB3RSTR_SDMMC1RST                 RCC_AHB3RSTR_SDMMC1RST_Msk\n\n\n/********************  Bit definition for RCC_AHB1RSTR register  ***************/\n#define RCC_AHB1RSTR_DMA1RST_Pos               (0U)\n#define RCC_AHB1RSTR_DMA1RST_Msk               (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)      /*!< 0x00000001 */\n#define RCC_AHB1RSTR_DMA1RST                   RCC_AHB1RSTR_DMA1RST_Msk\n#define RCC_AHB1RSTR_DMA2RST_Pos               (1U)\n#define RCC_AHB1RSTR_DMA2RST_Msk               (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)      /*!< 0x00000002 */\n#define RCC_AHB1RSTR_DMA2RST                   RCC_AHB1RSTR_DMA2RST_Msk\n#define RCC_AHB1RSTR_ADC12RST_Pos              (5U)\n#define RCC_AHB1RSTR_ADC12RST_Msk              (0x1UL << RCC_AHB1RSTR_ADC12RST_Pos)     /*!< 0x00000020 */\n#define RCC_AHB1RSTR_ADC12RST                  RCC_AHB1RSTR_ADC12RST_Msk\n#define RCC_AHB1RSTR_ETH1MACRST_Pos            (15U)\n#define RCC_AHB1RSTR_ETH1MACRST_Msk            (0x1UL << RCC_AHB1RSTR_ETH1MACRST_Pos)   /*!< 0x00008000 */\n#define RCC_AHB1RSTR_ETH1MACRST                RCC_AHB1RSTR_ETH1MACRST_Msk\n#define RCC_AHB1RSTR_USB1OTGHSRST_Pos          (25U)\n#define RCC_AHB1RSTR_USB1OTGHSRST_Msk          (0x1UL << RCC_AHB1RSTR_USB1OTGHSRST_Pos) /*!< 0x02000000 */\n#define RCC_AHB1RSTR_USB1OTGHSRST              RCC_AHB1RSTR_USB1OTGHSRST_Msk\n#define RCC_AHB1RSTR_USB2OTGFSRST_Pos          (27U)\n#define RCC_AHB1RSTR_USB2OTGFSRST_Msk          (0x1UL << RCC_AHB1RSTR_USB2OTGFSRST_Pos) /*!< 0x08000000 */\n#define RCC_AHB1RSTR_USB2OTGFSRST              RCC_AHB1RSTR_USB2OTGFSRST_Msk\n\n/* Legacy define */\n#define RCC_AHB1RSTR_USB2OTGHSRST_Pos          RCC_AHB1RSTR_USB2OTGFSRST_Pos\n#define RCC_AHB1RSTR_USB2OTGHSRST_Msk          RCC_AHB1RSTR_USB2OTGFSRST_Msk\n#define RCC_AHB1RSTR_USB2OTGHSRST              RCC_AHB1RSTR_USB2OTGFSRST\n\n/********************  Bit definition for RCC_AHB2RSTR register  ***************/\n#define RCC_AHB2RSTR_DCMIRST_Pos               (0U)\n#define RCC_AHB2RSTR_DCMIRST_Msk               (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos)       /*!< 0x00000001 */\n#define RCC_AHB2RSTR_DCMIRST                   RCC_AHB2RSTR_DCMIRST_Msk\n#define RCC_AHB2RSTR_RNGRST_Pos                (6U)\n#define RCC_AHB2RSTR_RNGRST_Msk                (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)        /*!< 0x00000040 */\n#define RCC_AHB2RSTR_RNGRST                    RCC_AHB2RSTR_RNGRST_Msk\n#define RCC_AHB2RSTR_SDMMC2RST_Pos             (9U)\n#define RCC_AHB2RSTR_SDMMC2RST_Msk             (0x1UL << RCC_AHB2RSTR_SDMMC2RST_Pos)     /*!< 0x00000200 */\n#define RCC_AHB2RSTR_SDMMC2RST                 RCC_AHB2RSTR_SDMMC2RST_Msk\n\n/********************  Bit definition for RCC_AHB4RSTR register  ******************/\n#define RCC_AHB4RSTR_GPIOARST_Pos              (0U)\n#define RCC_AHB4RSTR_GPIOARST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOARST_Pos)      /*!< 0x00000001 */\n#define RCC_AHB4RSTR_GPIOARST                  RCC_AHB4RSTR_GPIOARST_Msk\n#define RCC_AHB4RSTR_GPIOBRST_Pos              (1U)\n#define RCC_AHB4RSTR_GPIOBRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOBRST_Pos)      /*!< 0x00000002 */\n#define RCC_AHB4RSTR_GPIOBRST                  RCC_AHB4RSTR_GPIOBRST_Msk\n#define RCC_AHB4RSTR_GPIOCRST_Pos              (2U)\n#define RCC_AHB4RSTR_GPIOCRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOCRST_Pos)      /*!< 0x00000004 */\n#define RCC_AHB4RSTR_GPIOCRST                  RCC_AHB4RSTR_GPIOCRST_Msk\n#define RCC_AHB4RSTR_GPIODRST_Pos              (3U)\n#define RCC_AHB4RSTR_GPIODRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIODRST_Pos)      /*!< 0x00000008 */\n#define RCC_AHB4RSTR_GPIODRST                  RCC_AHB4RSTR_GPIODRST_Msk\n#define RCC_AHB4RSTR_GPIOERST_Pos              (4U)\n#define RCC_AHB4RSTR_GPIOERST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOERST_Pos)      /*!< 0x00000010 */\n#define RCC_AHB4RSTR_GPIOERST                  RCC_AHB4RSTR_GPIOERST_Msk\n#define RCC_AHB4RSTR_GPIOFRST_Pos              (5U)\n#define RCC_AHB4RSTR_GPIOFRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOFRST_Pos)       /*!< 0x00000020 */\n#define RCC_AHB4RSTR_GPIOFRST                  RCC_AHB4RSTR_GPIOFRST_Msk\n#define RCC_AHB4RSTR_GPIOGRST_Pos              (6U)\n#define RCC_AHB4RSTR_GPIOGRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOGRST_Pos)       /*!< 0x00000040 */\n#define RCC_AHB4RSTR_GPIOGRST                  RCC_AHB4RSTR_GPIOGRST_Msk\n#define RCC_AHB4RSTR_GPIOHRST_Pos              (7U)\n#define RCC_AHB4RSTR_GPIOHRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOHRST_Pos)       /*!< 0x00000080 */\n#define RCC_AHB4RSTR_GPIOHRST                  RCC_AHB4RSTR_GPIOHRST_Msk\n#define RCC_AHB4RSTR_GPIOIRST_Pos              (8U)\n#define RCC_AHB4RSTR_GPIOIRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOIRST_Pos)       /*!< 0x00000100 */\n#define RCC_AHB4RSTR_GPIOIRST                  RCC_AHB4RSTR_GPIOIRST_Msk\n#define RCC_AHB4RSTR_GPIOJRST_Pos              (9U)\n#define RCC_AHB4RSTR_GPIOJRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOJRST_Pos)       /*!< 0x00000200 */\n#define RCC_AHB4RSTR_GPIOJRST                  RCC_AHB4RSTR_GPIOJRST_Msk\n#define RCC_AHB4RSTR_GPIOKRST_Pos              (10U)\n#define RCC_AHB4RSTR_GPIOKRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOKRST_Pos)       /*!< 0x00000400 */\n#define RCC_AHB4RSTR_GPIOKRST                  RCC_AHB4RSTR_GPIOKRST_Msk\n#define RCC_AHB4RSTR_CRCRST_Pos                (19U)\n#define RCC_AHB4RSTR_CRCRST_Msk                (0x1UL << RCC_AHB4RSTR_CRCRST_Pos)         /*!< 0x00080000 */\n#define RCC_AHB4RSTR_CRCRST                    RCC_AHB4RSTR_CRCRST_Msk\n#define RCC_AHB4RSTR_BDMARST_Pos               (21U)\n#define RCC_AHB4RSTR_BDMARST_Msk               (0x1UL << RCC_AHB4RSTR_BDMARST_Pos)        /*!< 0x00200000 */\n#define RCC_AHB4RSTR_BDMARST                   RCC_AHB4RSTR_BDMARST_Msk\n#define RCC_AHB4RSTR_ADC3RST_Pos               (24U)\n#define RCC_AHB4RSTR_ADC3RST_Msk               (0x1UL << RCC_AHB4RSTR_ADC3RST_Pos)        /*!< 0x01000000 */\n#define RCC_AHB4RSTR_ADC3RST                   RCC_AHB4RSTR_ADC3RST_Msk\n#define RCC_AHB4RSTR_HSEMRST_Pos               (25U)\n#define RCC_AHB4RSTR_HSEMRST_Msk               (0x1UL << RCC_AHB4RSTR_HSEMRST_Pos)        /*!< 0x02000000 */\n#define RCC_AHB4RSTR_HSEMRST                   RCC_AHB4RSTR_HSEMRST_Msk\n\n\n/********************  Bit definition for RCC_APB3RSTR register  ******************/\n#define RCC_APB3RSTR_LTDCRST_Pos               (3U)\n#define RCC_APB3RSTR_LTDCRST_Msk               (0x1UL << RCC_APB3RSTR_LTDCRST_Pos) /*!< 0x00000008 */\n#define RCC_APB3RSTR_LTDCRST                   RCC_APB3RSTR_LTDCRST_Msk\n\n/********************  Bit definition for RCC_APB1LRSTR register  ******************/\n\n#define RCC_APB1LRSTR_TIM2RST_Pos              (0U)\n#define RCC_APB1LRSTR_TIM2RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM2RST_Pos) /*!< 0x00000001 */\n#define RCC_APB1LRSTR_TIM2RST                  RCC_APB1LRSTR_TIM2RST_Msk\n#define RCC_APB1LRSTR_TIM3RST_Pos              (1U)\n#define RCC_APB1LRSTR_TIM3RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM3RST_Pos) /*!< 0x00000002 */\n#define RCC_APB1LRSTR_TIM3RST                  RCC_APB1LRSTR_TIM3RST_Msk\n#define RCC_APB1LRSTR_TIM4RST_Pos              (2U)\n#define RCC_APB1LRSTR_TIM4RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM4RST_Pos) /*!< 0x00000004 */\n#define RCC_APB1LRSTR_TIM4RST                  RCC_APB1LRSTR_TIM4RST_Msk\n#define RCC_APB1LRSTR_TIM5RST_Pos              (3U)\n#define RCC_APB1LRSTR_TIM5RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM5RST_Pos) /*!< 0x00000008 */\n#define RCC_APB1LRSTR_TIM5RST                  RCC_APB1LRSTR_TIM5RST_Msk\n#define RCC_APB1LRSTR_TIM6RST_Pos              (4U)\n#define RCC_APB1LRSTR_TIM6RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM6RST_Pos) /*!< 0x00000010 */\n#define RCC_APB1LRSTR_TIM6RST                  RCC_APB1LRSTR_TIM6RST_Msk\n#define RCC_APB1LRSTR_TIM7RST_Pos              (5U)\n#define RCC_APB1LRSTR_TIM7RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM7RST_Pos) /*!< 0x00000020 */\n#define RCC_APB1LRSTR_TIM7RST                  RCC_APB1LRSTR_TIM7RST_Msk\n#define RCC_APB1LRSTR_TIM12RST_Pos             (6U)\n#define RCC_APB1LRSTR_TIM12RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM12RST_Pos) /*!< 0x00000040 */\n#define RCC_APB1LRSTR_TIM12RST                 RCC_APB1LRSTR_TIM12RST_Msk\n#define RCC_APB1LRSTR_TIM13RST_Pos             (7U)\n#define RCC_APB1LRSTR_TIM13RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM13RST_Pos) /*!< 0x00000080 */\n#define RCC_APB1LRSTR_TIM13RST                 RCC_APB1LRSTR_TIM13RST_Msk\n#define RCC_APB1LRSTR_TIM14RST_Pos             (8U)\n#define RCC_APB1LRSTR_TIM14RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM14RST_Pos) /*!< 0x00000100 */\n#define RCC_APB1LRSTR_TIM14RST                 RCC_APB1LRSTR_TIM14RST_Msk\n#define RCC_APB1LRSTR_LPTIM1RST_Pos            (9U)\n#define RCC_APB1LRSTR_LPTIM1RST_Msk            (0x1UL << RCC_APB1LRSTR_LPTIM1RST_Pos) /*!< 0x00000200 */\n#define RCC_APB1LRSTR_LPTIM1RST                RCC_APB1LRSTR_LPTIM1RST_Msk\n#define RCC_APB1LRSTR_SPI2RST_Pos              (14U)\n#define RCC_APB1LRSTR_SPI2RST_Msk              (0x1UL << RCC_APB1LRSTR_SPI2RST_Pos) /*!< 0x00004000 */\n#define RCC_APB1LRSTR_SPI2RST                  RCC_APB1LRSTR_SPI2RST_Msk\n#define RCC_APB1LRSTR_SPI3RST_Pos              (15U)\n#define RCC_APB1LRSTR_SPI3RST_Msk              (0x1UL << RCC_APB1LRSTR_SPI3RST_Pos) /*!< 0x00008000 */\n#define RCC_APB1LRSTR_SPI3RST                  RCC_APB1LRSTR_SPI3RST_Msk\n#define RCC_APB1LRSTR_SPDIFRXRST_Pos           (16U)\n#define RCC_APB1LRSTR_SPDIFRXRST_Msk           (0x1UL << RCC_APB1LRSTR_SPDIFRXRST_Pos) /*!< 0x00010000 */\n#define RCC_APB1LRSTR_SPDIFRXRST               RCC_APB1LRSTR_SPDIFRXRST_Msk\n#define RCC_APB1LRSTR_USART2RST_Pos            (17U)\n#define RCC_APB1LRSTR_USART2RST_Msk            (0x1UL << RCC_APB1LRSTR_USART2RST_Pos) /*!< 0x00020000 */\n#define RCC_APB1LRSTR_USART2RST                RCC_APB1LRSTR_USART2RST_Msk\n#define RCC_APB1LRSTR_USART3RST_Pos            (18U)\n#define RCC_APB1LRSTR_USART3RST_Msk            (0x1UL << RCC_APB1LRSTR_USART3RST_Pos) /*!< 0x00040000 */\n#define RCC_APB1LRSTR_USART3RST                RCC_APB1LRSTR_USART3RST_Msk\n#define RCC_APB1LRSTR_UART4RST_Pos             (19U)\n#define RCC_APB1LRSTR_UART4RST_Msk             (0x1UL << RCC_APB1LRSTR_UART4RST_Pos) /*!< 0x00080000 */\n#define RCC_APB1LRSTR_UART4RST                 RCC_APB1LRSTR_UART4RST_Msk\n#define RCC_APB1LRSTR_UART5RST_Pos             (20U)\n#define RCC_APB1LRSTR_UART5RST_Msk             (0x1UL << RCC_APB1LRSTR_UART5RST_Pos) /*!< 0x00100000 */\n#define RCC_APB1LRSTR_UART5RST                 RCC_APB1LRSTR_UART5RST_Msk\n#define RCC_APB1LRSTR_I2C1RST_Pos              (21U)\n#define RCC_APB1LRSTR_I2C1RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C1RST_Pos) /*!< 0x00200000 */\n#define RCC_APB1LRSTR_I2C1RST                  RCC_APB1LRSTR_I2C1RST_Msk\n#define RCC_APB1LRSTR_I2C2RST_Pos              (22U)\n#define RCC_APB1LRSTR_I2C2RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C2RST_Pos) /*!< 0x00400000 */\n#define RCC_APB1LRSTR_I2C2RST                  RCC_APB1LRSTR_I2C2RST_Msk\n#define RCC_APB1LRSTR_I2C3RST_Pos              (23U)\n#define RCC_APB1LRSTR_I2C3RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C3RST_Pos) /*!< 0x00800000 */\n#define RCC_APB1LRSTR_I2C3RST                  RCC_APB1LRSTR_I2C3RST_Msk\n#define RCC_APB1LRSTR_CECRST_Pos               (27U)\n#define RCC_APB1LRSTR_CECRST_Msk               (0x1UL << RCC_APB1LRSTR_CECRST_Pos) /*!< 0x08000000 */\n#define RCC_APB1LRSTR_CECRST                   RCC_APB1LRSTR_CECRST_Msk\n#define RCC_APB1LRSTR_DAC12RST_Pos             (29U)\n#define RCC_APB1LRSTR_DAC12RST_Msk             (0x1UL << RCC_APB1LRSTR_DAC12RST_Pos) /*!< 0x20000000 */\n#define RCC_APB1LRSTR_DAC12RST                 RCC_APB1LRSTR_DAC12RST_Msk\n#define RCC_APB1LRSTR_UART7RST_Pos             (30U)\n#define RCC_APB1LRSTR_UART7RST_Msk             (0x1UL << RCC_APB1LRSTR_UART7RST_Pos) /*!< 0x40000000 */\n#define RCC_APB1LRSTR_UART7RST                 RCC_APB1LRSTR_UART7RST_Msk\n#define RCC_APB1LRSTR_UART8RST_Pos             (31U)\n#define RCC_APB1LRSTR_UART8RST_Msk             (0x1UL << RCC_APB1LRSTR_UART8RST_Pos) /*!< 0x80000000 */\n#define RCC_APB1LRSTR_UART8RST                 RCC_APB1LRSTR_UART8RST_Msk\n\n/* Legacy define */\n#define RCC_APB1LRSTR_HDMICECRST_Pos           RCC_APB1LRSTR_CECRST_Pos\n#define RCC_APB1LRSTR_HDMICECRST_Msk           RCC_APB1LRSTR_CECRST_Msk\n#define RCC_APB1LRSTR_HDMICECRST               RCC_APB1LRSTR_CECRST\n/********************  Bit definition for RCC_APB1HRSTR register  ******************/\n#define RCC_APB1HRSTR_CRSRST_Pos               (1U)\n#define RCC_APB1HRSTR_CRSRST_Msk               (0x1UL << RCC_APB1HRSTR_CRSRST_Pos) /*!< 0x00000002 */\n#define RCC_APB1HRSTR_CRSRST                   RCC_APB1HRSTR_CRSRST_Msk\n#define RCC_APB1HRSTR_SWPMIRST_Pos             (2U)\n#define RCC_APB1HRSTR_SWPMIRST_Msk             (0x1UL << RCC_APB1HRSTR_SWPMIRST_Pos) /*!< 0x00000004 */\n#define RCC_APB1HRSTR_SWPMIRST                 RCC_APB1HRSTR_SWPMIRST_Msk\n#define RCC_APB1HRSTR_OPAMPRST_Pos             (4U)\n#define RCC_APB1HRSTR_OPAMPRST_Msk             (0x1UL << RCC_APB1HRSTR_OPAMPRST_Pos) /*!< 0x00000010 */\n#define RCC_APB1HRSTR_OPAMPRST                 RCC_APB1HRSTR_OPAMPRST_Msk\n#define RCC_APB1HRSTR_MDIOSRST_Pos             (5U)\n#define RCC_APB1HRSTR_MDIOSRST_Msk             (0x1UL << RCC_APB1HRSTR_MDIOSRST_Pos) /*!< 0x00000020 */\n#define RCC_APB1HRSTR_MDIOSRST                 RCC_APB1HRSTR_MDIOSRST_Msk\n#define RCC_APB1HRSTR_FDCANRST_Pos             (8U)\n#define RCC_APB1HRSTR_FDCANRST_Msk             (0x1UL << RCC_APB1HRSTR_FDCANRST_Pos) /*!< 0x00000100 */\n#define RCC_APB1HRSTR_FDCANRST                 RCC_APB1HRSTR_FDCANRST_Msk\n\n/********************  Bit definition for RCC_APB2RSTR register  ******************/\n#define RCC_APB2RSTR_TIM1RST_Pos               (0U)\n#define RCC_APB2RSTR_TIM1RST_Msk               (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */\n#define RCC_APB2RSTR_TIM1RST                   RCC_APB2RSTR_TIM1RST_Msk\n#define RCC_APB2RSTR_TIM8RST_Pos               (1U)\n#define RCC_APB2RSTR_TIM8RST_Msk               (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */\n#define RCC_APB2RSTR_TIM8RST                   RCC_APB2RSTR_TIM8RST_Msk\n#define RCC_APB2RSTR_USART1RST_Pos             (4U)\n#define RCC_APB2RSTR_USART1RST_Msk             (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */\n#define RCC_APB2RSTR_USART1RST                 RCC_APB2RSTR_USART1RST_Msk\n#define RCC_APB2RSTR_USART6RST_Pos             (5U)\n#define RCC_APB2RSTR_USART6RST_Msk             (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */\n#define RCC_APB2RSTR_USART6RST                 RCC_APB2RSTR_USART6RST_Msk\n#define RCC_APB2RSTR_SPI1RST_Pos               (12U)\n#define RCC_APB2RSTR_SPI1RST_Msk               (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */\n#define RCC_APB2RSTR_SPI1RST                   RCC_APB2RSTR_SPI1RST_Msk\n#define RCC_APB2RSTR_SPI4RST_Pos               (13U)\n#define RCC_APB2RSTR_SPI4RST_Msk               (0x1UL << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */\n#define RCC_APB2RSTR_SPI4RST                   RCC_APB2RSTR_SPI4RST_Msk\n#define RCC_APB2RSTR_TIM15RST_Pos              (16U)\n#define RCC_APB2RSTR_TIM15RST_Msk              (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */\n#define RCC_APB2RSTR_TIM15RST                  RCC_APB2RSTR_TIM15RST_Msk\n#define RCC_APB2RSTR_TIM16RST_Pos              (17U)\n#define RCC_APB2RSTR_TIM16RST_Msk              (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */\n#define RCC_APB2RSTR_TIM16RST                  RCC_APB2RSTR_TIM16RST_Msk\n#define RCC_APB2RSTR_TIM17RST_Pos              (18U)\n#define RCC_APB2RSTR_TIM17RST_Msk              (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */\n#define RCC_APB2RSTR_TIM17RST                  RCC_APB2RSTR_TIM17RST_Msk\n#define RCC_APB2RSTR_SPI5RST_Pos               (20U)\n#define RCC_APB2RSTR_SPI5RST_Msk               (0x1UL << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */\n#define RCC_APB2RSTR_SPI5RST                   RCC_APB2RSTR_SPI5RST_Msk\n#define RCC_APB2RSTR_SAI1RST_Pos               (22U)\n#define RCC_APB2RSTR_SAI1RST_Msk               (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */\n#define RCC_APB2RSTR_SAI1RST                   RCC_APB2RSTR_SAI1RST_Msk\n#define RCC_APB2RSTR_SAI2RST_Pos               (23U)\n#define RCC_APB2RSTR_SAI2RST_Msk               (0x1UL << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00800000 */\n#define RCC_APB2RSTR_SAI2RST                   RCC_APB2RSTR_SAI2RST_Msk\n#define RCC_APB2RSTR_SAI3RST_Pos               (24U)\n#define RCC_APB2RSTR_SAI3RST_Msk               (0x1UL << RCC_APB2RSTR_SAI3RST_Pos) /*!< 0x01000000 */\n#define RCC_APB2RSTR_SAI3RST                   RCC_APB2RSTR_SAI3RST_Msk\n#define RCC_APB2RSTR_DFSDM1RST_Pos             (28U)\n#define RCC_APB2RSTR_DFSDM1RST_Msk             (0x1UL << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x10000000 */\n#define RCC_APB2RSTR_DFSDM1RST                 RCC_APB2RSTR_DFSDM1RST_Msk\n#define RCC_APB2RSTR_HRTIMRST_Pos              (29U)\n#define RCC_APB2RSTR_HRTIMRST_Msk              (0x1UL << RCC_APB2RSTR_HRTIMRST_Pos) /*!< 0x20000000 */\n#define RCC_APB2RSTR_HRTIMRST                  RCC_APB2RSTR_HRTIMRST_Msk\n\n/********************  Bit definition for RCC_APB4RSTR register  ******************/\n#define RCC_APB4RSTR_SYSCFGRST_Pos             (1U)\n#define RCC_APB4RSTR_SYSCFGRST_Msk             (0x1UL << RCC_APB4RSTR_SYSCFGRST_Pos) /*!< 0x00000002 */\n#define RCC_APB4RSTR_SYSCFGRST                 RCC_APB4RSTR_SYSCFGRST_Msk\n#define RCC_APB4RSTR_LPUART1RST_Pos            (3U)\n#define RCC_APB4RSTR_LPUART1RST_Msk            (0x1UL << RCC_APB4RSTR_LPUART1RST_Pos) /*!< 0x00000008 */\n#define RCC_APB4RSTR_LPUART1RST                RCC_APB4RSTR_LPUART1RST_Msk\n#define RCC_APB4RSTR_SPI6RST_Pos               (5U)\n#define RCC_APB4RSTR_SPI6RST_Msk               (0x1UL << RCC_APB4RSTR_SPI6RST_Pos) /*!< 0x00000020 */\n#define RCC_APB4RSTR_SPI6RST                   RCC_APB4RSTR_SPI6RST_Msk\n#define RCC_APB4RSTR_I2C4RST_Pos               (7U)\n#define RCC_APB4RSTR_I2C4RST_Msk               (0x1UL << RCC_APB4RSTR_I2C4RST_Pos) /*!< 0x00000080 */\n#define RCC_APB4RSTR_I2C4RST                   RCC_APB4RSTR_I2C4RST_Msk\n#define RCC_APB4RSTR_LPTIM2RST_Pos             (9U)\n#define RCC_APB4RSTR_LPTIM2RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM2RST_Pos) /*!< 0x00000200 */\n#define RCC_APB4RSTR_LPTIM2RST                 RCC_APB4RSTR_LPTIM2RST_Msk\n#define RCC_APB4RSTR_LPTIM3RST_Pos             (10U)\n#define RCC_APB4RSTR_LPTIM3RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM3RST_Pos) /*!< 0x00000400 */\n#define RCC_APB4RSTR_LPTIM3RST                 RCC_APB4RSTR_LPTIM3RST_Msk\n#define RCC_APB4RSTR_LPTIM4RST_Pos             (11U)\n#define RCC_APB4RSTR_LPTIM4RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM4RST_Pos) /*!< 0x00000800 */\n#define RCC_APB4RSTR_LPTIM4RST                 RCC_APB4RSTR_LPTIM4RST_Msk\n#define RCC_APB4RSTR_LPTIM5RST_Pos             (12U)\n#define RCC_APB4RSTR_LPTIM5RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM5RST_Pos) /*!< 0x00001000 */\n#define RCC_APB4RSTR_LPTIM5RST                 RCC_APB4RSTR_LPTIM5RST_Msk\n#define RCC_APB4RSTR_COMP12RST_Pos             (14U)\n#define RCC_APB4RSTR_COMP12RST_Msk             (0x1UL << RCC_APB4RSTR_COMP12RST_Pos) /*!< 0x00004000 */\n#define RCC_APB4RSTR_COMP12RST                 RCC_APB4RSTR_COMP12RST_Msk\n#define RCC_APB4RSTR_VREFRST_Pos               (15U)\n#define RCC_APB4RSTR_VREFRST_Msk               (0x1UL << RCC_APB4RSTR_VREFRST_Pos) /*!< 0x00008000 */\n#define RCC_APB4RSTR_VREFRST                   RCC_APB4RSTR_VREFRST_Msk\n#define RCC_APB4RSTR_SAI4RST_Pos               (21U)\n#define RCC_APB4RSTR_SAI4RST_Msk               (0x1UL << RCC_APB4RSTR_SAI4RST_Pos) /*!< 0x00200000 */\n#define RCC_APB4RSTR_SAI4RST                   RCC_APB4RSTR_SAI4RST_Msk\n\n\n/********************  Bit definition for RCC_GCR register  ********************/\n#define RCC_GCR_WW1RSC_Pos                     (0U)\n#define RCC_GCR_WW1RSC_Msk                     (0x1UL << RCC_GCR_WW1RSC_Pos)   /*!< 0x00000001 */\n#define RCC_GCR_WW1RSC                         RCC_GCR_WW1RSC_Msk\n\n/********************  Bit definition for RCC_D3AMR register  ********************/\n#define RCC_D3AMR_BDMAAMEN_Pos                 (0U)\n#define RCC_D3AMR_BDMAAMEN_Msk                 (0x1UL << RCC_D3AMR_BDMAAMEN_Pos) /*!< 0x00000001 */\n#define RCC_D3AMR_BDMAAMEN                     RCC_D3AMR_BDMAAMEN_Msk\n#define RCC_D3AMR_LPUART1AMEN_Pos              (3U)\n#define RCC_D3AMR_LPUART1AMEN_Msk              (0x1UL << RCC_D3AMR_LPUART1AMEN_Pos) /*!< 0x00000008 */\n#define RCC_D3AMR_LPUART1AMEN                  RCC_D3AMR_LPUART1AMEN_Msk\n#define RCC_D3AMR_SPI6AMEN_Pos                 (5U)\n#define RCC_D3AMR_SPI6AMEN_Msk                 (0x1UL << RCC_D3AMR_SPI6AMEN_Pos) /*!< 0x00000020 */\n#define RCC_D3AMR_SPI6AMEN                     RCC_D3AMR_SPI6AMEN_Msk\n#define RCC_D3AMR_I2C4AMEN_Pos                 (7U)\n#define RCC_D3AMR_I2C4AMEN_Msk                 (0x1UL << RCC_D3AMR_I2C4AMEN_Pos) /*!< 0x00000080 */\n#define RCC_D3AMR_I2C4AMEN                     RCC_D3AMR_I2C4AMEN_Msk\n#define RCC_D3AMR_LPTIM2AMEN_Pos               (9U)\n#define RCC_D3AMR_LPTIM2AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM2AMEN_Pos) /*!< 0x00000200 */\n#define RCC_D3AMR_LPTIM2AMEN                   RCC_D3AMR_LPTIM2AMEN_Msk\n#define RCC_D3AMR_LPTIM3AMEN_Pos               (10U)\n#define RCC_D3AMR_LPTIM3AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM3AMEN_Pos) /*!< 0x00000400 */\n#define RCC_D3AMR_LPTIM3AMEN                   RCC_D3AMR_LPTIM3AMEN_Msk\n#define RCC_D3AMR_LPTIM4AMEN_Pos               (11U)\n#define RCC_D3AMR_LPTIM4AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM4AMEN_Pos) /*!< 0x00000800 */\n#define RCC_D3AMR_LPTIM4AMEN                   RCC_D3AMR_LPTIM4AMEN_Msk\n#define RCC_D3AMR_LPTIM5AMEN_Pos               (12U)\n#define RCC_D3AMR_LPTIM5AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM5AMEN_Pos) /*!< 0x00001000 */\n#define RCC_D3AMR_LPTIM5AMEN                   RCC_D3AMR_LPTIM5AMEN_Msk\n#define RCC_D3AMR_COMP12AMEN_Pos               (14U)\n#define RCC_D3AMR_COMP12AMEN_Msk               (0x1UL << RCC_D3AMR_COMP12AMEN_Pos) /*!< 0x00004000 */\n#define RCC_D3AMR_COMP12AMEN                   RCC_D3AMR_COMP12AMEN_Msk\n#define RCC_D3AMR_VREFAMEN_Pos                 (15U)\n#define RCC_D3AMR_VREFAMEN_Msk                 (0x1UL << RCC_D3AMR_VREFAMEN_Pos) /*!< 0x00008000 */\n#define RCC_D3AMR_VREFAMEN                     RCC_D3AMR_VREFAMEN_Msk\n#define RCC_D3AMR_RTCAMEN_Pos                  (16U)\n#define RCC_D3AMR_RTCAMEN_Msk                  (0x1UL << RCC_D3AMR_RTCAMEN_Pos) /*!< 0x00010000 */\n#define RCC_D3AMR_RTCAMEN                      RCC_D3AMR_RTCAMEN_Msk\n#define RCC_D3AMR_CRCAMEN_Pos                  (19U)\n#define RCC_D3AMR_CRCAMEN_Msk                  (0x1UL << RCC_D3AMR_CRCAMEN_Pos) /*!< 0x00080000 */\n#define RCC_D3AMR_CRCAMEN                      RCC_D3AMR_CRCAMEN_Msk\n#define RCC_D3AMR_SAI4AMEN_Pos                 (21U)\n#define RCC_D3AMR_SAI4AMEN_Msk                 (0x1UL << RCC_D3AMR_SAI4AMEN_Pos) /*!< 0x00200000 */\n#define RCC_D3AMR_SAI4AMEN                     RCC_D3AMR_SAI4AMEN_Msk\n#define RCC_D3AMR_ADC3AMEN_Pos                 (24U)\n#define RCC_D3AMR_ADC3AMEN_Msk                 (0x1UL << RCC_D3AMR_ADC3AMEN_Pos) /*!< 0x01000000 */\n#define RCC_D3AMR_ADC3AMEN                     RCC_D3AMR_ADC3AMEN_Msk\n\n\n#define RCC_D3AMR_BKPRAMAMEN_Pos               (28U)\n#define RCC_D3AMR_BKPRAMAMEN_Msk               (0x1UL << RCC_D3AMR_BKPRAMAMEN_Pos) /*!< 0x10000000 */\n#define RCC_D3AMR_BKPRAMAMEN                   RCC_D3AMR_BKPRAMAMEN_Msk\n#define RCC_D3AMR_SRAM4AMEN_Pos                (29U)\n#define RCC_D3AMR_SRAM4AMEN_Msk                (0x1UL << RCC_D3AMR_SRAM4AMEN_Pos) /*!< 0x20000000 */\n#define RCC_D3AMR_SRAM4AMEN                    RCC_D3AMR_SRAM4AMEN_Msk\n/********************  Bit definition for RCC_AHB3LPENR register  **************/\n#define RCC_AHB3LPENR_MDMALPEN_Pos             (0U)\n#define RCC_AHB3LPENR_MDMALPEN_Msk             (0x1UL << RCC_AHB3LPENR_MDMALPEN_Pos)         /*!< 0x00000001 */\n#define RCC_AHB3LPENR_MDMALPEN                 RCC_AHB3LPENR_MDMALPEN_Msk\n#define RCC_AHB3LPENR_DMA2DLPEN_Pos            (4U)\n#define RCC_AHB3LPENR_DMA2DLPEN_Msk            (0x1UL << RCC_AHB3LPENR_DMA2DLPEN_Pos)        /*!< 0x00000010 */\n#define RCC_AHB3LPENR_DMA2DLPEN                RCC_AHB3LPENR_DMA2DLPEN_Msk\n#define RCC_AHB3LPENR_JPGDECLPEN_Pos           (5U)\n#define RCC_AHB3LPENR_JPGDECLPEN_Msk           (0x1UL << RCC_AHB3LPENR_JPGDECLPEN_Pos)       /*!< 0x00000020 */\n#define RCC_AHB3LPENR_JPGDECLPEN               RCC_AHB3LPENR_JPGDECLPEN_Msk\n#define RCC_AHB3LPENR_FLASHLPEN_Pos            (8U)\n#define RCC_AHB3LPENR_FLASHLPEN_Msk            (0x1UL << RCC_AHB3LPENR_FLASHLPEN_Pos)        /*!< 0x00000100 */\n#define RCC_AHB3LPENR_FLASHLPEN                RCC_AHB3LPENR_FLASHLPEN_Msk\n#define RCC_AHB3LPENR_FMCLPEN_Pos              (12U)\n#define RCC_AHB3LPENR_FMCLPEN_Msk              (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos)          /*!< 0x00001000 */\n#define RCC_AHB3LPENR_FMCLPEN                  RCC_AHB3LPENR_FMCLPEN_Msk\n#define RCC_AHB3LPENR_QSPILPEN_Pos             (14U)\n#define RCC_AHB3LPENR_QSPILPEN_Msk             (0x1UL << RCC_AHB3LPENR_QSPILPEN_Pos)         /*!< 0x00004000 */\n#define RCC_AHB3LPENR_QSPILPEN                 RCC_AHB3LPENR_QSPILPEN_Msk\n#define RCC_AHB3LPENR_SDMMC1LPEN_Pos           (16U)\n#define RCC_AHB3LPENR_SDMMC1LPEN_Msk           (0x1UL << RCC_AHB3LPENR_SDMMC1LPEN_Pos)       /*!< 0x00010000 */\n#define RCC_AHB3LPENR_SDMMC1LPEN               RCC_AHB3LPENR_SDMMC1LPEN_Msk\n#define RCC_AHB3LPENR_DTCM1LPEN_Pos            (28U)\n#define RCC_AHB3LPENR_DTCM1LPEN_Msk            (0x1UL << RCC_AHB3LPENR_DTCM1LPEN_Pos)        /*!< 0x10000000 */\n#define RCC_AHB3LPENR_DTCM1LPEN                RCC_AHB3LPENR_DTCM1LPEN_Msk\n#define RCC_AHB3LPENR_DTCM2LPEN_Pos            (29U)\n#define RCC_AHB3LPENR_DTCM2LPEN_Msk            (0x1UL << RCC_AHB3LPENR_DTCM2LPEN_Pos)        /*!< 0x20000000 */\n#define RCC_AHB3LPENR_DTCM2LPEN                RCC_AHB3LPENR_DTCM2LPEN_Msk\n#define RCC_AHB3LPENR_ITCMLPEN_Pos             (30U)\n#define RCC_AHB3LPENR_ITCMLPEN_Msk             (0x1UL << RCC_AHB3LPENR_ITCMLPEN_Pos)         /*!< 0x40000000 */\n#define RCC_AHB3LPENR_ITCMLPEN                 RCC_AHB3LPENR_ITCMLPEN_Msk\n#define RCC_AHB3LPENR_AXISRAMLPEN_Pos          (31U)\n#define RCC_AHB3LPENR_AXISRAMLPEN_Msk          (0x1UL << RCC_AHB3LPENR_AXISRAMLPEN_Pos)      /*!< 0x80000000 */\n#define RCC_AHB3LPENR_AXISRAMLPEN              RCC_AHB3LPENR_AXISRAMLPEN_Msk\n\n\n/********************  Bit definition for RCC_AHB1LPENR register  ***************/\n#define RCC_AHB1LPENR_DMA1LPEN_Pos             (0U)\n#define RCC_AHB1LPENR_DMA1LPEN_Msk             (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00000001 */\n#define RCC_AHB1LPENR_DMA1LPEN                 RCC_AHB1LPENR_DMA1LPEN_Msk\n#define RCC_AHB1LPENR_DMA2LPEN_Pos             (1U)\n#define RCC_AHB1LPENR_DMA2LPEN_Msk             (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00000002 */\n#define RCC_AHB1LPENR_DMA2LPEN                 RCC_AHB1LPENR_DMA2LPEN_Msk\n#define RCC_AHB1LPENR_ADC12LPEN_Pos            (5U)\n#define RCC_AHB1LPENR_ADC12LPEN_Msk            (0x1UL << RCC_AHB1LPENR_ADC12LPEN_Pos) /*!< 0x00000020 */\n#define RCC_AHB1LPENR_ADC12LPEN                RCC_AHB1LPENR_ADC12LPEN_Msk\n#define RCC_AHB1LPENR_ETH1MACLPEN_Pos          (15U)\n#define RCC_AHB1LPENR_ETH1MACLPEN_Msk          (0x1UL << RCC_AHB1LPENR_ETH1MACLPEN_Pos) /*!< 0x00008000 */\n#define RCC_AHB1LPENR_ETH1MACLPEN              RCC_AHB1LPENR_ETH1MACLPEN_Msk\n#define RCC_AHB1LPENR_ETH1TXLPEN_Pos           (16U)\n#define RCC_AHB1LPENR_ETH1TXLPEN_Msk           (0x1UL << RCC_AHB1LPENR_ETH1TXLPEN_Pos) /*!< 0x00010000 */\n#define RCC_AHB1LPENR_ETH1TXLPEN               RCC_AHB1LPENR_ETH1TXLPEN_Msk\n#define RCC_AHB1LPENR_ETH1RXLPEN_Pos           (17U)\n#define RCC_AHB1LPENR_ETH1RXLPEN_Msk           (0x1UL << RCC_AHB1LPENR_ETH1RXLPEN_Pos) /*!< 0x00020000 */\n#define RCC_AHB1LPENR_ETH1RXLPEN               RCC_AHB1LPENR_ETH1RXLPEN_Msk\n#define RCC_AHB1LPENR_USB1OTGHSLPEN_Pos        (25U)\n#define RCC_AHB1LPENR_USB1OTGHSLPEN_Msk        (0x1UL << RCC_AHB1LPENR_USB1OTGHSLPEN_Pos) /*!< 0x02000000 */\n#define RCC_AHB1LPENR_USB1OTGHSLPEN            RCC_AHB1LPENR_USB1OTGHSLPEN_Msk\n#define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos    (26U)\n#define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk    (0x1UL << RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos) /*!< 0x04000000 */\n#define RCC_AHB1LPENR_USB1OTGHSULPILPEN        RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk\n#define RCC_AHB1LPENR_USB2OTGFSLPEN_Pos        (27U)\n#define RCC_AHB1LPENR_USB2OTGFSLPEN_Msk        (0x1UL << RCC_AHB1LPENR_USB2OTGFSLPEN_Pos) /*!< 0x08000000 */\n#define RCC_AHB1LPENR_USB2OTGFSLPEN            RCC_AHB1LPENR_USB2OTGFSLPEN_Msk\n#define RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos    (28U)\n#define RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk    (0x1UL << RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos) /*!< 0x10000000 */\n#define RCC_AHB1LPENR_USB2OTGFSULPILPEN        RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk\n\n/* Legacy define */\n#define RCC_AHB1LPENR_USB2OTGHSLPEN_Pos        RCC_AHB1LPENR_USB2OTGFSLPEN_Pos\n#define RCC_AHB1LPENR_USB2OTGHSLPEN_Msk        RCC_AHB1LPENR_USB2OTGFSLPEN_Msk\n#define RCC_AHB1LPENR_USB2OTGHSLPEN            RCC_AHB1LPENR_USB2OTGFSLPEN\n#define RCC_AHB1LPENR_USB2OTGHSULPILPEN_Pos    RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos\n#define RCC_AHB1LPENR_USB2OTGHSULPILPEN_Msk    RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk\n#define RCC_AHB1LPENR_USB2OTGHSULPILPEN        RCC_AHB1LPENR_USB2OTGFSULPILPEN\n\n/********************  Bit definition for RCC_AHB2LPENR register  ***************/\n#define RCC_AHB2LPENR_DCMILPEN_Pos             (0U)\n#define RCC_AHB2LPENR_DCMILPEN_Msk             (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */\n#define RCC_AHB2LPENR_DCMILPEN                 RCC_AHB2LPENR_DCMILPEN_Msk\n#define RCC_AHB2LPENR_RNGLPEN_Pos              (6U)\n#define RCC_AHB2LPENR_RNGLPEN_Msk              (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */\n#define RCC_AHB2LPENR_RNGLPEN                  RCC_AHB2LPENR_RNGLPEN_Msk\n#define RCC_AHB2LPENR_SDMMC2LPEN_Pos           (9U)\n#define RCC_AHB2LPENR_SDMMC2LPEN_Msk           (0x1UL << RCC_AHB2LPENR_SDMMC2LPEN_Pos) /*!< 0x00000200 */\n#define RCC_AHB2LPENR_SDMMC2LPEN               RCC_AHB2LPENR_SDMMC2LPEN_Msk\n#define RCC_AHB2LPENR_SRAM1LPEN_Pos          (29U)\n#define RCC_AHB2LPENR_SRAM1LPEN_Msk          (0x1UL << RCC_AHB2LPENR_SRAM1LPEN_Pos) /*!< 0x20000000 */\n#define RCC_AHB2LPENR_SRAM1LPEN              RCC_AHB2LPENR_SRAM1LPEN_Msk\n#define RCC_AHB2LPENR_SRAM2LPEN_Pos          (30U)\n#define RCC_AHB2LPENR_SRAM2LPEN_Msk          (0x1UL << RCC_AHB2LPENR_SRAM2LPEN_Pos) /*!< 0x40000000 */\n#define RCC_AHB2LPENR_SRAM2LPEN              RCC_AHB2LPENR_SRAM2LPEN_Msk\n#define RCC_AHB2LPENR_SRAM3LPEN_Pos          (31U)\n#define RCC_AHB2LPENR_SRAM3LPEN_Msk          (0x1UL << RCC_AHB2LPENR_SRAM3LPEN_Pos) /*!< 0x80000000 */\n#define RCC_AHB2LPENR_SRAM3LPEN              RCC_AHB2LPENR_SRAM3LPEN_Msk\n\n/* Legacy define */\n#define RCC_AHB2LPENR_D2SRAM1LPEN_Pos          RCC_AHB2LPENR_SRAM1LPEN_Pos\n#define RCC_AHB2LPENR_D2SRAM1LPEN_Msk          RCC_AHB2LPENR_SRAM1LPEN_Msk\n#define RCC_AHB2LPENR_D2SRAM1LPEN              RCC_AHB2LPENR_SRAM1LPEN\n#define RCC_AHB2LPENR_D2SRAM2LPEN_Pos          RCC_AHB2LPENR_SRAM2LPEN_Pos\n#define RCC_AHB2LPENR_D2SRAM2LPEN_Msk          RCC_AHB2LPENR_SRAM2LPEN_Msk\n#define RCC_AHB2LPENR_D2SRAM2LPEN              RCC_AHB2LPENR_SRAM2LPEN\n#define RCC_AHB2LPENR_D2SRAM3LPEN_Pos          RCC_AHB2LPENR_SRAM3LPEN_Pos\n#define RCC_AHB2LPENR_D2SRAM3LPEN_Msk          RCC_AHB2LPENR_SRAM3LPEN_Msk\n#define RCC_AHB2LPENR_D2SRAM3LPEN              RCC_AHB2LPENR_SRAM3LPEN\n\n/********************  Bit definition for RCC_AHB4LPENR register  ******************/\n#define RCC_AHB4LPENR_GPIOALPEN_Pos            (0U)\n#define RCC_AHB4LPENR_GPIOALPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */\n#define RCC_AHB4LPENR_GPIOALPEN                RCC_AHB4LPENR_GPIOALPEN_Msk\n#define RCC_AHB4LPENR_GPIOBLPEN_Pos            (1U)\n#define RCC_AHB4LPENR_GPIOBLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */\n#define RCC_AHB4LPENR_GPIOBLPEN                RCC_AHB4LPENR_GPIOBLPEN_Msk\n#define RCC_AHB4LPENR_GPIOCLPEN_Pos            (2U)\n#define RCC_AHB4LPENR_GPIOCLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */\n#define RCC_AHB4LPENR_GPIOCLPEN                RCC_AHB4LPENR_GPIOCLPEN_Msk\n#define RCC_AHB4LPENR_GPIODLPEN_Pos            (3U)\n#define RCC_AHB4LPENR_GPIODLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */\n#define RCC_AHB4LPENR_GPIODLPEN                RCC_AHB4LPENR_GPIODLPEN_Msk\n#define RCC_AHB4LPENR_GPIOELPEN_Pos            (4U)\n#define RCC_AHB4LPENR_GPIOELPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */\n#define RCC_AHB4LPENR_GPIOELPEN                RCC_AHB4LPENR_GPIOELPEN_Msk\n#define RCC_AHB4LPENR_GPIOFLPEN_Pos            (5U)\n#define RCC_AHB4LPENR_GPIOFLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */\n#define RCC_AHB4LPENR_GPIOFLPEN                RCC_AHB4LPENR_GPIOFLPEN_Msk\n#define RCC_AHB4LPENR_GPIOGLPEN_Pos            (6U)\n#define RCC_AHB4LPENR_GPIOGLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */\n#define RCC_AHB4LPENR_GPIOGLPEN                RCC_AHB4LPENR_GPIOGLPEN_Msk\n#define RCC_AHB4LPENR_GPIOHLPEN_Pos            (7U)\n#define RCC_AHB4LPENR_GPIOHLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */\n#define RCC_AHB4LPENR_GPIOHLPEN                RCC_AHB4LPENR_GPIOHLPEN_Msk\n#define RCC_AHB4LPENR_GPIOILPEN_Pos            (8U)\n#define RCC_AHB4LPENR_GPIOILPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */\n#define RCC_AHB4LPENR_GPIOILPEN                RCC_AHB4LPENR_GPIOILPEN_Msk\n#define RCC_AHB4LPENR_GPIOJLPEN_Pos            (9U)\n#define RCC_AHB4LPENR_GPIOJLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */\n#define RCC_AHB4LPENR_GPIOJLPEN                RCC_AHB4LPENR_GPIOJLPEN_Msk\n#define RCC_AHB4LPENR_GPIOKLPEN_Pos            (10U)\n#define RCC_AHB4LPENR_GPIOKLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */\n#define RCC_AHB4LPENR_GPIOKLPEN                RCC_AHB4LPENR_GPIOKLPEN_Msk\n#define RCC_AHB4LPENR_CRCLPEN_Pos              (19U)\n#define RCC_AHB4LPENR_CRCLPEN_Msk              (0x1UL << RCC_AHB4LPENR_CRCLPEN_Pos) /*!< 0x00080000 */\n#define RCC_AHB4LPENR_CRCLPEN                  RCC_AHB4LPENR_CRCLPEN_Msk\n#define RCC_AHB4LPENR_BDMALPEN_Pos             (21U)\n#define RCC_AHB4LPENR_BDMALPEN_Msk             (0x1UL << RCC_AHB4LPENR_BDMALPEN_Pos) /*!< 0x00200000 */\n#define RCC_AHB4LPENR_BDMALPEN                 RCC_AHB4LPENR_BDMALPEN_Msk\n#define RCC_AHB4LPENR_ADC3LPEN_Pos             (24U)\n#define RCC_AHB4LPENR_ADC3LPEN_Msk             (0x1UL << RCC_AHB4LPENR_ADC3LPEN_Pos) /*!< 0x01000000 */\n#define RCC_AHB4LPENR_ADC3LPEN                 RCC_AHB4LPENR_ADC3LPEN_Msk\n#define RCC_AHB4LPENR_BKPRAMLPEN_Pos           (28U)\n#define RCC_AHB4LPENR_BKPRAMLPEN_Msk           (0x1UL << RCC_AHB4LPENR_BKPRAMLPEN_Pos) /*!< 0x10000000 */\n#define RCC_AHB4LPENR_BKPRAMLPEN               RCC_AHB4LPENR_BKPRAMLPEN_Msk\n#define RCC_AHB4LPENR_SRAM4LPEN_Pos            (29U)\n#define RCC_AHB4LPENR_SRAM4LPEN_Msk            (0x1UL << RCC_AHB4LPENR_SRAM4LPEN_Pos) /*!< 0x20000000 */\n#define RCC_AHB4LPENR_SRAM4LPEN                RCC_AHB4LPENR_SRAM4LPEN_Msk\n\n/* Legacy define */\n#define RCC_AHB4LPENR_D3SRAM1LPEN_Pos          RCC_AHB4LPENR_SRAM4LPEN_Pos\n#define RCC_AHB4LPENR_D3SRAM1LPEN_Msk          RCC_AHB4LPENR_SRAM4LPEN_Msk\n#define RCC_AHB4LPENR_D3SRAM1LPEN              RCC_AHB4LPENR_SRAM4LPEN\n/********************  Bit definition for RCC_APB3LPENR register  ******************/\n#define RCC_APB3LPENR_LTDCLPEN_Pos             (3U)\n#define RCC_APB3LPENR_LTDCLPEN_Msk             (0x1UL << RCC_APB3LPENR_LTDCLPEN_Pos) /*!< 0x00000008 */\n#define RCC_APB3LPENR_LTDCLPEN                 RCC_APB3LPENR_LTDCLPEN_Msk\n#define RCC_APB3LPENR_WWDG1LPEN_Pos            (6U)\n#define RCC_APB3LPENR_WWDG1LPEN_Msk            (0x1UL << RCC_APB3LPENR_WWDG1LPEN_Pos) /*!< 0x00000040 */\n#define RCC_APB3LPENR_WWDG1LPEN                RCC_APB3LPENR_WWDG1LPEN_Msk\n\n/********************  Bit definition for RCC_APB1LLPENR register  ******************/\n\n#define RCC_APB1LLPENR_TIM2LPEN_Pos            (0U)\n#define RCC_APB1LLPENR_TIM2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM2LPEN_Pos) /*!< 0x00000001 */\n#define RCC_APB1LLPENR_TIM2LPEN                RCC_APB1LLPENR_TIM2LPEN_Msk\n#define RCC_APB1LLPENR_TIM3LPEN_Pos            (1U)\n#define RCC_APB1LLPENR_TIM3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM3LPEN_Pos) /*!< 0x00000002 */\n#define RCC_APB1LLPENR_TIM3LPEN                RCC_APB1LLPENR_TIM3LPEN_Msk\n#define RCC_APB1LLPENR_TIM4LPEN_Pos            (2U)\n#define RCC_APB1LLPENR_TIM4LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM4LPEN_Pos) /*!< 0x00000004 */\n#define RCC_APB1LLPENR_TIM4LPEN                RCC_APB1LLPENR_TIM4LPEN_Msk\n#define RCC_APB1LLPENR_TIM5LPEN_Pos            (3U)\n#define RCC_APB1LLPENR_TIM5LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM5LPEN_Pos) /*!< 0x00000008 */\n#define RCC_APB1LLPENR_TIM5LPEN                RCC_APB1LLPENR_TIM5LPEN_Msk\n#define RCC_APB1LLPENR_TIM6LPEN_Pos            (4U)\n#define RCC_APB1LLPENR_TIM6LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM6LPEN_Pos) /*!< 0x00000010 */\n#define RCC_APB1LLPENR_TIM6LPEN                RCC_APB1LLPENR_TIM6LPEN_Msk\n#define RCC_APB1LLPENR_TIM7LPEN_Pos            (5U)\n#define RCC_APB1LLPENR_TIM7LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM7LPEN_Pos) /*!< 0x00000020 */\n#define RCC_APB1LLPENR_TIM7LPEN                RCC_APB1LLPENR_TIM7LPEN_Msk\n#define RCC_APB1LLPENR_TIM12LPEN_Pos           (6U)\n#define RCC_APB1LLPENR_TIM12LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM12LPEN_Pos) /*!< 0x00000040 */\n#define RCC_APB1LLPENR_TIM12LPEN               RCC_APB1LLPENR_TIM12LPEN_Msk\n#define RCC_APB1LLPENR_TIM13LPEN_Pos           (7U)\n#define RCC_APB1LLPENR_TIM13LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM13LPEN_Pos) /*!< 0x00000080 */\n#define RCC_APB1LLPENR_TIM13LPEN               RCC_APB1LLPENR_TIM13LPEN_Msk\n#define RCC_APB1LLPENR_TIM14LPEN_Pos           (8U)\n#define RCC_APB1LLPENR_TIM14LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM14LPEN_Pos) /*!< 0x00000100 */\n#define RCC_APB1LLPENR_TIM14LPEN               RCC_APB1LLPENR_TIM14LPEN_Msk\n#define RCC_APB1LLPENR_LPTIM1LPEN_Pos          (9U)\n#define RCC_APB1LLPENR_LPTIM1LPEN_Msk          (0x1UL << RCC_APB1LLPENR_LPTIM1LPEN_Pos) /*!< 0x00000200 */\n#define RCC_APB1LLPENR_LPTIM1LPEN              RCC_APB1LLPENR_LPTIM1LPEN_Msk\n\n\n#define RCC_APB1LLPENR_SPI2LPEN_Pos            (14U)\n#define RCC_APB1LLPENR_SPI2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_SPI2LPEN_Pos) /*!< 0x00004000 */\n#define RCC_APB1LLPENR_SPI2LPEN                RCC_APB1LLPENR_SPI2LPEN_Msk\n#define RCC_APB1LLPENR_SPI3LPEN_Pos            (15U)\n#define RCC_APB1LLPENR_SPI3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_SPI3LPEN_Pos) /*!< 0x00008000 */\n#define RCC_APB1LLPENR_SPI3LPEN                RCC_APB1LLPENR_SPI3LPEN_Msk\n#define RCC_APB1LLPENR_SPDIFRXLPEN_Pos         (16U)\n#define RCC_APB1LLPENR_SPDIFRXLPEN_Msk         (0x1UL << RCC_APB1LLPENR_SPDIFRXLPEN_Pos) /*!< 0x00010000 */\n#define RCC_APB1LLPENR_SPDIFRXLPEN             RCC_APB1LLPENR_SPDIFRXLPEN_Msk\n#define RCC_APB1LLPENR_USART2LPEN_Pos          (17U)\n#define RCC_APB1LLPENR_USART2LPEN_Msk          (0x1UL << RCC_APB1LLPENR_USART2LPEN_Pos) /*!< 0x00020000 */\n#define RCC_APB1LLPENR_USART2LPEN              RCC_APB1LLPENR_USART2LPEN_Msk\n#define RCC_APB1LLPENR_USART3LPEN_Pos          (18U)\n#define RCC_APB1LLPENR_USART3LPEN_Msk          (0x1UL << RCC_APB1LLPENR_USART3LPEN_Pos) /*!< 0x00040000 */\n#define RCC_APB1LLPENR_USART3LPEN              RCC_APB1LLPENR_USART3LPEN_Msk\n#define RCC_APB1LLPENR_UART4LPEN_Pos           (19U)\n#define RCC_APB1LLPENR_UART4LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART4LPEN_Pos) /*!< 0x00080000 */\n#define RCC_APB1LLPENR_UART4LPEN               RCC_APB1LLPENR_UART4LPEN_Msk\n#define RCC_APB1LLPENR_UART5LPEN_Pos           (20U)\n#define RCC_APB1LLPENR_UART5LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART5LPEN_Pos) /*!< 0x00100000 */\n#define RCC_APB1LLPENR_UART5LPEN               RCC_APB1LLPENR_UART5LPEN_Msk\n#define RCC_APB1LLPENR_I2C1LPEN_Pos            (21U)\n#define RCC_APB1LLPENR_I2C1LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C1LPEN_Pos) /*!< 0x00200000 */\n#define RCC_APB1LLPENR_I2C1LPEN                RCC_APB1LLPENR_I2C1LPEN_Msk\n#define RCC_APB1LLPENR_I2C2LPEN_Pos            (22U)\n#define RCC_APB1LLPENR_I2C2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C2LPEN_Pos) /*!< 0x00400000 */\n#define RCC_APB1LLPENR_I2C2LPEN                RCC_APB1LLPENR_I2C2LPEN_Msk\n#define RCC_APB1LLPENR_I2C3LPEN_Pos            (23U)\n#define RCC_APB1LLPENR_I2C3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C3LPEN_Pos) /*!< 0x00800000 */\n#define RCC_APB1LLPENR_I2C3LPEN                RCC_APB1LLPENR_I2C3LPEN_Msk\n#define RCC_APB1LLPENR_CECLPEN_Pos             (27U)\n#define RCC_APB1LLPENR_CECLPEN_Msk             (0x1UL << RCC_APB1LLPENR_CECLPEN_Pos) /*!< 0x08000000 */\n#define RCC_APB1LLPENR_CECLPEN                 RCC_APB1LLPENR_CECLPEN_Msk\n#define RCC_APB1LLPENR_DAC12LPEN_Pos           (29U)\n#define RCC_APB1LLPENR_DAC12LPEN_Msk           (0x1UL << RCC_APB1LLPENR_DAC12LPEN_Pos) /*!< 0x20000000 */\n#define RCC_APB1LLPENR_DAC12LPEN               RCC_APB1LLPENR_DAC12LPEN_Msk\n#define RCC_APB1LLPENR_UART7LPEN_Pos           (30U)\n#define RCC_APB1LLPENR_UART7LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART7LPEN_Pos) /*!< 0x40000000 */\n#define RCC_APB1LLPENR_UART7LPEN               RCC_APB1LLPENR_UART7LPEN_Msk\n#define RCC_APB1LLPENR_UART8LPEN_Pos           (31U)\n#define RCC_APB1LLPENR_UART8LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART8LPEN_Pos) /*!< 0x80000000 */\n#define RCC_APB1LLPENR_UART8LPEN               RCC_APB1LLPENR_UART8LPEN_Msk\n\n/* Legacy define */\n#define RCC_APB1LLPENR_HDMICECEN_Pos           RCC_APB1LLPENR_CECLPEN_Pos\n#define RCC_APB1LLPENR_HDMICECEN_Msk           RCC_APB1LLPENR_CECLPEN_Msk\n#define RCC_APB1LLPENR_HDMICECEN               RCC_APB1LLPENR_CECLPEN\n/********************  Bit definition for RCC_APB1HLPENR register  ******************/\n#define RCC_APB1HLPENR_CRSLPEN_Pos             (1U)\n#define RCC_APB1HLPENR_CRSLPEN_Msk             (0x1UL << RCC_APB1HLPENR_CRSLPEN_Pos) /*!< 0x00000002 */\n#define RCC_APB1HLPENR_CRSLPEN                 RCC_APB1HLPENR_CRSLPEN_Msk\n#define RCC_APB1HLPENR_SWPMILPEN_Pos           (2U)\n#define RCC_APB1HLPENR_SWPMILPEN_Msk           (0x1UL << RCC_APB1HLPENR_SWPMILPEN_Pos) /*!< 0x00000004 */\n#define RCC_APB1HLPENR_SWPMILPEN               RCC_APB1HLPENR_SWPMILPEN_Msk\n#define RCC_APB1HLPENR_OPAMPLPEN_Pos           (4U)\n#define RCC_APB1HLPENR_OPAMPLPEN_Msk           (0x1UL << RCC_APB1HLPENR_OPAMPLPEN_Pos) /*!< 0x00000010 */\n#define RCC_APB1HLPENR_OPAMPLPEN               RCC_APB1HLPENR_OPAMPLPEN_Msk\n#define RCC_APB1HLPENR_MDIOSLPEN_Pos           (5U)\n#define RCC_APB1HLPENR_MDIOSLPEN_Msk           (0x1UL << RCC_APB1HLPENR_MDIOSLPEN_Pos) /*!< 0x00000020 */\n#define RCC_APB1HLPENR_MDIOSLPEN               RCC_APB1HLPENR_MDIOSLPEN_Msk\n#define RCC_APB1HLPENR_FDCANLPEN_Pos           (8U)\n#define RCC_APB1HLPENR_FDCANLPEN_Msk           (0x1UL << RCC_APB1HLPENR_FDCANLPEN_Pos) /*!< 0x00000100 */\n#define RCC_APB1HLPENR_FDCANLPEN               RCC_APB1HLPENR_FDCANLPEN_Msk\n\n/********************  Bit definition for RCC_APB2LPENR register  ******************/\n#define RCC_APB2LPENR_TIM1LPEN_Pos             (0U)\n#define RCC_APB2LPENR_TIM1LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */\n#define RCC_APB2LPENR_TIM1LPEN                 RCC_APB2LPENR_TIM1LPEN_Msk\n#define RCC_APB2LPENR_TIM8LPEN_Pos             (1U)\n#define RCC_APB2LPENR_TIM8LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */\n#define RCC_APB2LPENR_TIM8LPEN                 RCC_APB2LPENR_TIM8LPEN_Msk\n#define RCC_APB2LPENR_USART1LPEN_Pos           (4U)\n#define RCC_APB2LPENR_USART1LPEN_Msk           (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */\n#define RCC_APB2LPENR_USART1LPEN               RCC_APB2LPENR_USART1LPEN_Msk\n#define RCC_APB2LPENR_USART6LPEN_Pos           (5U)\n#define RCC_APB2LPENR_USART6LPEN_Msk           (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */\n#define RCC_APB2LPENR_USART6LPEN               RCC_APB2LPENR_USART6LPEN_Msk\n#define RCC_APB2LPENR_SPI1LPEN_Pos             (12U)\n#define RCC_APB2LPENR_SPI1LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */\n#define RCC_APB2LPENR_SPI1LPEN                 RCC_APB2LPENR_SPI1LPEN_Msk\n#define RCC_APB2LPENR_SPI4LPEN_Pos             (13U)\n#define RCC_APB2LPENR_SPI4LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */\n#define RCC_APB2LPENR_SPI4LPEN                 RCC_APB2LPENR_SPI4LPEN_Msk\n#define RCC_APB2LPENR_TIM15LPEN_Pos            (16U)\n#define RCC_APB2LPENR_TIM15LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos) /*!< 0x00010000 */\n#define RCC_APB2LPENR_TIM15LPEN                RCC_APB2LPENR_TIM15LPEN_Msk\n#define RCC_APB2LPENR_TIM16LPEN_Pos            (17U)\n#define RCC_APB2LPENR_TIM16LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos) /*!< 0x00020000 */\n#define RCC_APB2LPENR_TIM16LPEN                RCC_APB2LPENR_TIM16LPEN_Msk\n#define RCC_APB2LPENR_TIM17LPEN_Pos            (18U)\n#define RCC_APB2LPENR_TIM17LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos) /*!< 0x00040000 */\n#define RCC_APB2LPENR_TIM17LPEN                RCC_APB2LPENR_TIM17LPEN_Msk\n#define RCC_APB2LPENR_SPI5LPEN_Pos             (20U)\n#define RCC_APB2LPENR_SPI5LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */\n#define RCC_APB2LPENR_SPI5LPEN                 RCC_APB2LPENR_SPI5LPEN_Msk\n#define RCC_APB2LPENR_SAI1LPEN_Pos             (22U)\n#define RCC_APB2LPENR_SAI1LPEN_Msk             (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */\n#define RCC_APB2LPENR_SAI1LPEN                 RCC_APB2LPENR_SAI1LPEN_Msk\n#define RCC_APB2LPENR_SAI2LPEN_Pos             (23U)\n#define RCC_APB2LPENR_SAI2LPEN_Msk             (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00800000 */\n#define RCC_APB2LPENR_SAI2LPEN                 RCC_APB2LPENR_SAI2LPEN_Msk\n#define RCC_APB2LPENR_SAI3LPEN_Pos             (24U)\n#define RCC_APB2LPENR_SAI3LPEN_Msk             (0x1UL << RCC_APB2LPENR_SAI3LPEN_Pos) /*!< 0x01000000 */\n#define RCC_APB2LPENR_SAI3LPEN                 RCC_APB2LPENR_SAI3LPEN_Msk\n#define RCC_APB2LPENR_DFSDM1LPEN_Pos           (28U)\n#define RCC_APB2LPENR_DFSDM1LPEN_Msk           (0x1UL << RCC_APB2LPENR_DFSDM1LPEN_Pos) /*!< 0x10000000 */\n#define RCC_APB2LPENR_DFSDM1LPEN               RCC_APB2LPENR_DFSDM1LPEN_Msk\n#define RCC_APB2LPENR_HRTIMLPEN_Pos            (29U)\n#define RCC_APB2LPENR_HRTIMLPEN_Msk            (0x1UL << RCC_APB2LPENR_HRTIMLPEN_Pos) /*!< 0x20000000 */\n#define RCC_APB2LPENR_HRTIMLPEN                RCC_APB2LPENR_HRTIMLPEN_Msk\n\n/********************  Bit definition for RCC_APB4LPENR register  ******************/\n#define RCC_APB4LPENR_SYSCFGLPEN_Pos           (1U)\n#define RCC_APB4LPENR_SYSCFGLPEN_Msk           (0x1UL << RCC_APB4LPENR_SYSCFGLPEN_Pos) /*!< 0x00000002 */\n#define RCC_APB4LPENR_SYSCFGLPEN               RCC_APB4LPENR_SYSCFGLPEN_Msk\n#define RCC_APB4LPENR_LPUART1LPEN_Pos          (3U)\n#define RCC_APB4LPENR_LPUART1LPEN_Msk          (0x1UL << RCC_APB4LPENR_LPUART1LPEN_Pos) /*!< 0x00000008 */\n#define RCC_APB4LPENR_LPUART1LPEN              RCC_APB4LPENR_LPUART1LPEN_Msk\n#define RCC_APB4LPENR_SPI6LPEN_Pos             (5U)\n#define RCC_APB4LPENR_SPI6LPEN_Msk             (0x1UL << RCC_APB4LPENR_SPI6LPEN_Pos) /*!< 0x00000020 */\n#define RCC_APB4LPENR_SPI6LPEN                 RCC_APB4LPENR_SPI6LPEN_Msk\n#define RCC_APB4LPENR_I2C4LPEN_Pos             (7U)\n#define RCC_APB4LPENR_I2C4LPEN_Msk             (0x1UL << RCC_APB4LPENR_I2C4LPEN_Pos) /*!< 0x00000080 */\n#define RCC_APB4LPENR_I2C4LPEN                 RCC_APB4LPENR_I2C4LPEN_Msk\n#define RCC_APB4LPENR_LPTIM2LPEN_Pos           (9U)\n#define RCC_APB4LPENR_LPTIM2LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM2LPEN_Pos) /*!< 0x00000200 */\n#define RCC_APB4LPENR_LPTIM2LPEN               RCC_APB4LPENR_LPTIM2LPEN_Msk\n#define RCC_APB4LPENR_LPTIM3LPEN_Pos           (10U)\n#define RCC_APB4LPENR_LPTIM3LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM3LPEN_Pos) /*!< 0x00000400 */\n#define RCC_APB4LPENR_LPTIM3LPEN               RCC_APB4LPENR_LPTIM3LPEN_Msk\n#define RCC_APB4LPENR_LPTIM4LPEN_Pos           (11U)\n#define RCC_APB4LPENR_LPTIM4LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM4LPEN_Pos) /*!< 0x00000800 */\n#define RCC_APB4LPENR_LPTIM4LPEN               RCC_APB4LPENR_LPTIM4LPEN_Msk\n#define RCC_APB4LPENR_LPTIM5LPEN_Pos           (12U)\n#define RCC_APB4LPENR_LPTIM5LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM5LPEN_Pos) /*!< 0x00001000 */\n#define RCC_APB4LPENR_LPTIM5LPEN               RCC_APB4LPENR_LPTIM5LPEN_Msk\n#define RCC_APB4LPENR_COMP12LPEN_Pos           (14U)\n#define RCC_APB4LPENR_COMP12LPEN_Msk           (0x1UL << RCC_APB4LPENR_COMP12LPEN_Pos) /*!< 0x00004000 */\n#define RCC_APB4LPENR_COMP12LPEN               RCC_APB4LPENR_COMP12LPEN_Msk\n#define RCC_APB4LPENR_VREFLPEN_Pos             (15U)\n#define RCC_APB4LPENR_VREFLPEN_Msk             (0x1UL << RCC_APB4LPENR_VREFLPEN_Pos) /*!< 0x00008000 */\n#define RCC_APB4LPENR_VREFLPEN                 RCC_APB4LPENR_VREFLPEN_Msk\n#define RCC_APB4LPENR_RTCAPBLPEN_Pos           (16U)\n#define RCC_APB4LPENR_RTCAPBLPEN_Msk           (0x1UL << RCC_APB4LPENR_RTCAPBLPEN_Pos) /*!< 0x00010000 */\n#define RCC_APB4LPENR_RTCAPBLPEN               RCC_APB4LPENR_RTCAPBLPEN_Msk\n#define RCC_APB4LPENR_SAI4LPEN_Pos             (21U)\n#define RCC_APB4LPENR_SAI4LPEN_Msk             (0x1UL << RCC_APB4LPENR_SAI4LPEN_Pos) /*!< 0x00200000 */\n#define RCC_APB4LPENR_SAI4LPEN                 RCC_APB4LPENR_SAI4LPEN_Msk\n\n\n/********************  Bit definition for RCC_RSR register  *******************/\n#define RCC_RSR_RMVF_Pos                       (16U)\n#define RCC_RSR_RMVF_Msk                       (0x1UL << RCC_RSR_RMVF_Pos)     /*!< 0x00010000 */\n#define RCC_RSR_RMVF                           RCC_RSR_RMVF_Msk\n#define RCC_RSR_CPURSTF_Pos                    (17U)\n#define RCC_RSR_CPURSTF_Msk                    (0x1UL << RCC_RSR_CPURSTF_Pos)  /*!< 0x00020000 */\n#define RCC_RSR_CPURSTF                        RCC_RSR_CPURSTF_Msk\n#define RCC_RSR_D1RSTF_Pos                     (19U)\n#define RCC_RSR_D1RSTF_Msk                     (0x1UL << RCC_RSR_D1RSTF_Pos)   /*!< 0x00080000 */\n#define RCC_RSR_D1RSTF                         RCC_RSR_D1RSTF_Msk\n#define RCC_RSR_D2RSTF_Pos                     (20U)\n#define RCC_RSR_D2RSTF_Msk                     (0x1UL << RCC_RSR_D2RSTF_Pos)   /*!< 0x00100000 */\n#define RCC_RSR_D2RSTF                         RCC_RSR_D2RSTF_Msk\n#define RCC_RSR_BORRSTF_Pos                    (21U)\n#define RCC_RSR_BORRSTF_Msk                    (0x1UL << RCC_RSR_BORRSTF_Pos)  /*!< 0x00200000 */\n#define RCC_RSR_BORRSTF                        RCC_RSR_BORRSTF_Msk\n#define RCC_RSR_PINRSTF_Pos                    (22U)\n#define RCC_RSR_PINRSTF_Msk                    (0x1UL << RCC_RSR_PINRSTF_Pos)  /*!< 0x00400000 */\n#define RCC_RSR_PINRSTF                        RCC_RSR_PINRSTF_Msk\n#define RCC_RSR_PORRSTF_Pos                    (23U)\n#define RCC_RSR_PORRSTF_Msk                    (0x1UL << RCC_RSR_PORRSTF_Pos)  /*!< 0x00800000 */\n#define RCC_RSR_PORRSTF                        RCC_RSR_PORRSTF_Msk\n#define RCC_RSR_SFTRSTF_Pos                    (24U)\n#define RCC_RSR_SFTRSTF_Msk                    (0x1UL << RCC_RSR_SFTRSTF_Pos)  /*!< 0x01000000 */\n#define RCC_RSR_SFTRSTF                        RCC_RSR_SFTRSTF_Msk\n#define RCC_RSR_IWDG1RSTF_Pos                  (26U)\n#define RCC_RSR_IWDG1RSTF_Msk                  (0x1UL << RCC_RSR_IWDG1RSTF_Pos) /*!< 0x04000000 */\n#define RCC_RSR_IWDG1RSTF                      RCC_RSR_IWDG1RSTF_Msk\n#define RCC_RSR_WWDG1RSTF_Pos                  (28U)\n#define RCC_RSR_WWDG1RSTF_Msk                  (0x1UL << RCC_RSR_WWDG1RSTF_Pos) /*!< 0x10000000 */\n#define RCC_RSR_WWDG1RSTF                      RCC_RSR_WWDG1RSTF_Msk\n\n#define RCC_RSR_LPWRRSTF_Pos                   (30U)\n#define RCC_RSR_LPWRRSTF_Msk                   (0x1UL << RCC_RSR_LPWRRSTF_Pos) /*!< 0x40000000 */\n#define RCC_RSR_LPWRRSTF                       RCC_RSR_LPWRRSTF_Msk\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                                    RNG                                     */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bits definition for RNG_CR register  *******************/\n#define RNG_CR_RNGEN_Pos    (2U)\n#define RNG_CR_RNGEN_Msk    (0x1UL << RNG_CR_RNGEN_Pos)                        /*!< 0x00000004 */\n#define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk\n#define RNG_CR_IE_Pos       (3U)\n#define RNG_CR_IE_Msk       (0x1UL << RNG_CR_IE_Pos)                           /*!< 0x00000008 */\n#define RNG_CR_IE           RNG_CR_IE_Msk\n#define RNG_CR_CED_Pos      (5U)\n#define RNG_CR_CED_Msk      (0x1UL << RNG_CR_CED_Pos)                          /*!< 0x00000020 */\n#define RNG_CR_CED          RNG_CR_CED_Msk\n\n/********************  Bits definition for RNG_SR register  *******************/\n#define RNG_SR_DRDY_Pos     (0U)\n#define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                         /*!< 0x00000001 */\n#define RNG_SR_DRDY         RNG_SR_DRDY_Msk\n#define RNG_SR_CECS_Pos     (1U)\n#define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                         /*!< 0x00000002 */\n#define RNG_SR_CECS         RNG_SR_CECS_Msk\n#define RNG_SR_SECS_Pos     (2U)\n#define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                         /*!< 0x00000004 */\n#define RNG_SR_SECS         RNG_SR_SECS_Msk\n#define RNG_SR_CEIS_Pos     (5U)\n#define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                         /*!< 0x00000020 */\n#define RNG_SR_CEIS         RNG_SR_CEIS_Msk\n#define RNG_SR_SEIS_Pos     (6U)\n#define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                         /*!< 0x00000040 */\n#define RNG_SR_SEIS         RNG_SR_SEIS_Msk\n\n/******************************************************************************/\n/*                                                                            */\n/*                           Real-Time Clock (RTC)                            */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bits definition for RTC_TR register  *******************/\n#define RTC_TR_PM_Pos                  (22U)\n#define RTC_TR_PM_Msk                  (0x1UL << RTC_TR_PM_Pos)                /*!< 0x00400000 */\n#define RTC_TR_PM                      RTC_TR_PM_Msk\n#define RTC_TR_HT_Pos                  (20U)\n#define RTC_TR_HT_Msk                  (0x3UL << RTC_TR_HT_Pos)                /*!< 0x00300000 */\n#define RTC_TR_HT                      RTC_TR_HT_Msk\n#define RTC_TR_HT_0                    (0x1UL << RTC_TR_HT_Pos)                 /*!< 0x00100000 */\n#define RTC_TR_HT_1                    (0x2UL << RTC_TR_HT_Pos)                 /*!< 0x00200000 */\n#define RTC_TR_HU_Pos                  (16U)\n#define RTC_TR_HU_Msk                  (0xFUL << RTC_TR_HU_Pos)                /*!< 0x000F0000 */\n#define RTC_TR_HU                      RTC_TR_HU_Msk\n#define RTC_TR_HU_0                    (0x1UL << RTC_TR_HU_Pos)                 /*!< 0x00010000 */\n#define RTC_TR_HU_1                    (0x2UL << RTC_TR_HU_Pos)                 /*!< 0x00020000 */\n#define RTC_TR_HU_2                    (0x4UL << RTC_TR_HU_Pos)                 /*!< 0x00040000 */\n#define RTC_TR_HU_3                    (0x8UL << RTC_TR_HU_Pos)                 /*!< 0x00080000 */\n#define RTC_TR_MNT_Pos                 (12U)\n#define RTC_TR_MNT_Msk                 (0x7UL << RTC_TR_MNT_Pos)               /*!< 0x00007000 */\n#define RTC_TR_MNT                     RTC_TR_MNT_Msk\n#define RTC_TR_MNT_0                   (0x1UL << RTC_TR_MNT_Pos)                /*!< 0x00001000 */\n#define RTC_TR_MNT_1                   (0x2UL << RTC_TR_MNT_Pos)                /*!< 0x00002000 */\n#define RTC_TR_MNT_2                   (0x4UL << RTC_TR_MNT_Pos)                /*!< 0x00004000 */\n#define RTC_TR_MNU_Pos                 (8U)\n#define RTC_TR_MNU_Msk                 (0xFUL << RTC_TR_MNU_Pos)               /*!< 0x00000F00 */\n#define RTC_TR_MNU                     RTC_TR_MNU_Msk\n#define RTC_TR_MNU_0                   (0x1UL << RTC_TR_MNU_Pos)                /*!< 0x00000100 */\n#define RTC_TR_MNU_1                   (0x2UL << RTC_TR_MNU_Pos)                /*!< 0x00000200 */\n#define RTC_TR_MNU_2                   (0x4UL << RTC_TR_MNU_Pos)                /*!< 0x00000400 */\n#define RTC_TR_MNU_3                   (0x8UL << RTC_TR_MNU_Pos)                /*!< 0x00000800 */\n#define RTC_TR_ST_Pos                  (4U)\n#define RTC_TR_ST_Msk                  (0x7UL << RTC_TR_ST_Pos)                /*!< 0x00000070 */\n#define RTC_TR_ST                      RTC_TR_ST_Msk\n#define RTC_TR_ST_0                    (0x1UL << RTC_TR_ST_Pos)                 /*!< 0x00000010 */\n#define RTC_TR_ST_1                    (0x2UL << RTC_TR_ST_Pos)                 /*!< 0x00000020 */\n#define RTC_TR_ST_2                    (0x4UL << RTC_TR_ST_Pos)                 /*!< 0x00000040 */\n#define RTC_TR_SU_Pos                  (0U)\n#define RTC_TR_SU_Msk                  (0xFUL << RTC_TR_SU_Pos)                /*!< 0x0000000F */\n#define RTC_TR_SU                      RTC_TR_SU_Msk\n#define RTC_TR_SU_0                    (0x1UL << RTC_TR_SU_Pos)                 /*!< 0x00000001 */\n#define RTC_TR_SU_1                    (0x2UL << RTC_TR_SU_Pos)                 /*!< 0x00000002 */\n#define RTC_TR_SU_2                    (0x4UL << RTC_TR_SU_Pos)                 /*!< 0x00000004 */\n#define RTC_TR_SU_3                    (0x8UL << RTC_TR_SU_Pos)                 /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_DR register  *******************/\n#define RTC_DR_YT_Pos                  (20U)\n#define RTC_DR_YT_Msk                  (0xFUL << RTC_DR_YT_Pos)                /*!< 0x00F00000 */\n#define RTC_DR_YT                      RTC_DR_YT_Msk\n#define RTC_DR_YT_0                    (0x1UL << RTC_DR_YT_Pos)                 /*!< 0x00100000 */\n#define RTC_DR_YT_1                    (0x2UL << RTC_DR_YT_Pos)                 /*!< 0x00200000 */\n#define RTC_DR_YT_2                    (0x4UL << RTC_DR_YT_Pos)                 /*!< 0x00400000 */\n#define RTC_DR_YT_3                    (0x8UL << RTC_DR_YT_Pos)                 /*!< 0x00800000 */\n#define RTC_DR_YU_Pos                  (16U)\n#define RTC_DR_YU_Msk                  (0xFUL << RTC_DR_YU_Pos)                /*!< 0x000F0000 */\n#define RTC_DR_YU                      RTC_DR_YU_Msk\n#define RTC_DR_YU_0                    (0x1UL << RTC_DR_YU_Pos)                 /*!< 0x00010000 */\n#define RTC_DR_YU_1                    (0x2UL << RTC_DR_YU_Pos)                 /*!< 0x00020000 */\n#define RTC_DR_YU_2                    (0x4UL << RTC_DR_YU_Pos)                 /*!< 0x00040000 */\n#define RTC_DR_YU_3                    (0x8UL << RTC_DR_YU_Pos)                 /*!< 0x00080000 */\n#define RTC_DR_WDU_Pos                 (13U)\n#define RTC_DR_WDU_Msk                 (0x7UL << RTC_DR_WDU_Pos)               /*!< 0x0000E000 */\n#define RTC_DR_WDU                     RTC_DR_WDU_Msk\n#define RTC_DR_WDU_0                   (0x1UL << RTC_DR_WDU_Pos)                /*!< 0x00002000 */\n#define RTC_DR_WDU_1                   (0x2UL << RTC_DR_WDU_Pos)                /*!< 0x00004000 */\n#define RTC_DR_WDU_2                   (0x4UL << RTC_DR_WDU_Pos)                /*!< 0x00008000 */\n#define RTC_DR_MT_Pos                  (12U)\n#define RTC_DR_MT_Msk                  (0x1UL << RTC_DR_MT_Pos)                /*!< 0x00001000 */\n#define RTC_DR_MT                      RTC_DR_MT_Msk\n#define RTC_DR_MU_Pos                  (8U)\n#define RTC_DR_MU_Msk                  (0xFUL << RTC_DR_MU_Pos)                /*!< 0x00000F00 */\n#define RTC_DR_MU                      RTC_DR_MU_Msk\n#define RTC_DR_MU_0                    (0x1UL << RTC_DR_MU_Pos)                 /*!< 0x00000100 */\n#define RTC_DR_MU_1                    (0x2UL << RTC_DR_MU_Pos)                 /*!< 0x00000200 */\n#define RTC_DR_MU_2                    (0x4UL << RTC_DR_MU_Pos)                 /*!< 0x00000400 */\n#define RTC_DR_MU_3                    (0x8UL << RTC_DR_MU_Pos)                 /*!< 0x00000800 */\n#define RTC_DR_DT_Pos                  (4U)\n#define RTC_DR_DT_Msk                  (0x3UL << RTC_DR_DT_Pos)                /*!< 0x00000030 */\n#define RTC_DR_DT                      RTC_DR_DT_Msk\n#define RTC_DR_DT_0                    (0x1UL << RTC_DR_DT_Pos)                 /*!< 0x00000010 */\n#define RTC_DR_DT_1                    (0x2UL << RTC_DR_DT_Pos)                 /*!< 0x00000020 */\n#define RTC_DR_DU_Pos                  (0U)\n#define RTC_DR_DU_Msk                  (0xFUL << RTC_DR_DU_Pos)                /*!< 0x0000000F */\n#define RTC_DR_DU                      RTC_DR_DU_Msk\n#define RTC_DR_DU_0                    (0x1UL << RTC_DR_DU_Pos)                 /*!< 0x00000001 */\n#define RTC_DR_DU_1                    (0x2UL << RTC_DR_DU_Pos)                 /*!< 0x00000002 */\n#define RTC_DR_DU_2                    (0x4UL << RTC_DR_DU_Pos)                 /*!< 0x00000004 */\n#define RTC_DR_DU_3                    (0x8UL << RTC_DR_DU_Pos)                 /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_CR register  *******************/\n#define RTC_CR_ITSE_Pos                (24U)\n#define RTC_CR_ITSE_Msk                (0x1UL << RTC_CR_ITSE_Pos)              /*!< 0x01000000 */\n#define RTC_CR_ITSE                    RTC_CR_ITSE_Msk\n#define RTC_CR_COE_Pos                 (23U)\n#define RTC_CR_COE_Msk                 (0x1UL << RTC_CR_COE_Pos)               /*!< 0x00800000 */\n#define RTC_CR_COE                     RTC_CR_COE_Msk\n#define RTC_CR_OSEL_Pos                (21U)\n#define RTC_CR_OSEL_Msk                (0x3UL << RTC_CR_OSEL_Pos)              /*!< 0x00600000 */\n#define RTC_CR_OSEL                    RTC_CR_OSEL_Msk\n#define RTC_CR_OSEL_0                  (0x1UL << RTC_CR_OSEL_Pos)               /*!< 0x00200000 */\n#define RTC_CR_OSEL_1                  (0x2UL << RTC_CR_OSEL_Pos)               /*!< 0x00400000 */\n#define RTC_CR_POL_Pos                 (20U)\n#define RTC_CR_POL_Msk                 (0x1UL << RTC_CR_POL_Pos)               /*!< 0x00100000 */\n#define RTC_CR_POL                     RTC_CR_POL_Msk\n#define RTC_CR_COSEL_Pos               (19U)\n#define RTC_CR_COSEL_Msk               (0x1UL << RTC_CR_COSEL_Pos)             /*!< 0x00080000 */\n#define RTC_CR_COSEL                   RTC_CR_COSEL_Msk\n#define RTC_CR_BKP_Pos                 (18U)\n#define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)               /*!< 0x00040000 */\n#define RTC_CR_BKP                     RTC_CR_BKP_Msk\n#define RTC_CR_SUB1H_Pos               (17U)\n#define RTC_CR_SUB1H_Msk               (0x1UL << RTC_CR_SUB1H_Pos)             /*!< 0x00020000 */\n#define RTC_CR_SUB1H                   RTC_CR_SUB1H_Msk\n#define RTC_CR_ADD1H_Pos               (16U)\n#define RTC_CR_ADD1H_Msk               (0x1UL << RTC_CR_ADD1H_Pos)             /*!< 0x00010000 */\n#define RTC_CR_ADD1H                   RTC_CR_ADD1H_Msk\n#define RTC_CR_TSIE_Pos                (15U)\n#define RTC_CR_TSIE_Msk                (0x1UL << RTC_CR_TSIE_Pos)              /*!< 0x00008000 */\n#define RTC_CR_TSIE                    RTC_CR_TSIE_Msk\n#define RTC_CR_WUTIE_Pos               (14U)\n#define RTC_CR_WUTIE_Msk               (0x1UL << RTC_CR_WUTIE_Pos)             /*!< 0x00004000 */\n#define RTC_CR_WUTIE                   RTC_CR_WUTIE_Msk\n#define RTC_CR_ALRBIE_Pos              (13U)\n#define RTC_CR_ALRBIE_Msk              (0x1UL << RTC_CR_ALRBIE_Pos)            /*!< 0x00002000 */\n#define RTC_CR_ALRBIE                  RTC_CR_ALRBIE_Msk\n#define RTC_CR_ALRAIE_Pos              (12U)\n#define RTC_CR_ALRAIE_Msk              (0x1UL << RTC_CR_ALRAIE_Pos)            /*!< 0x00001000 */\n#define RTC_CR_ALRAIE                  RTC_CR_ALRAIE_Msk\n#define RTC_CR_TSE_Pos                 (11U)\n#define RTC_CR_TSE_Msk                 (0x1UL << RTC_CR_TSE_Pos)               /*!< 0x00000800 */\n#define RTC_CR_TSE                     RTC_CR_TSE_Msk\n#define RTC_CR_WUTE_Pos                (10U)\n#define RTC_CR_WUTE_Msk                (0x1UL << RTC_CR_WUTE_Pos)              /*!< 0x00000400 */\n#define RTC_CR_WUTE                    RTC_CR_WUTE_Msk\n#define RTC_CR_ALRBE_Pos               (9U)\n#define RTC_CR_ALRBE_Msk               (0x1UL << RTC_CR_ALRBE_Pos)             /*!< 0x00000200 */\n#define RTC_CR_ALRBE                   RTC_CR_ALRBE_Msk\n#define RTC_CR_ALRAE_Pos               (8U)\n#define RTC_CR_ALRAE_Msk               (0x1UL << RTC_CR_ALRAE_Pos)             /*!< 0x00000100 */\n#define RTC_CR_ALRAE                   RTC_CR_ALRAE_Msk\n#define RTC_CR_FMT_Pos                 (6U)\n#define RTC_CR_FMT_Msk                 (0x1UL << RTC_CR_FMT_Pos)               /*!< 0x00000040 */\n#define RTC_CR_FMT                     RTC_CR_FMT_Msk\n#define RTC_CR_BYPSHAD_Pos             (5U)\n#define RTC_CR_BYPSHAD_Msk             (0x1UL << RTC_CR_BYPSHAD_Pos)           /*!< 0x00000020 */\n#define RTC_CR_BYPSHAD                 RTC_CR_BYPSHAD_Msk\n#define RTC_CR_REFCKON_Pos             (4U)\n#define RTC_CR_REFCKON_Msk             (0x1UL << RTC_CR_REFCKON_Pos)           /*!< 0x00000010 */\n#define RTC_CR_REFCKON                 RTC_CR_REFCKON_Msk\n#define RTC_CR_TSEDGE_Pos              (3U)\n#define RTC_CR_TSEDGE_Msk              (0x1UL << RTC_CR_TSEDGE_Pos)            /*!< 0x00000008 */\n#define RTC_CR_TSEDGE                  RTC_CR_TSEDGE_Msk\n#define RTC_CR_WUCKSEL_Pos             (0U)\n#define RTC_CR_WUCKSEL_Msk             (0x7UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000007 */\n#define RTC_CR_WUCKSEL                 RTC_CR_WUCKSEL_Msk\n#define RTC_CR_WUCKSEL_0               (0x1UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000001 */\n#define RTC_CR_WUCKSEL_1               (0x2UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000002 */\n#define RTC_CR_WUCKSEL_2               (0x4UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000004 */\n\n/********************  Bits definition for RTC_ISR register  ******************/\n#define RTC_ISR_ITSF_Pos               (17U)\n#define RTC_ISR_ITSF_Msk               (0x1UL << RTC_ISR_ITSF_Pos)             /*!< 0x00020000 */\n#define RTC_ISR_ITSF                   RTC_ISR_ITSF_Msk\n#define RTC_ISR_RECALPF_Pos            (16U)\n#define RTC_ISR_RECALPF_Msk            (0x1UL << RTC_ISR_RECALPF_Pos)          /*!< 0x00010000 */\n#define RTC_ISR_RECALPF                RTC_ISR_RECALPF_Msk\n#define RTC_ISR_TAMP3F_Pos             (15U)\n#define RTC_ISR_TAMP3F_Msk             (0x1UL << RTC_ISR_TAMP3F_Pos)           /*!< 0x00008000 */\n#define RTC_ISR_TAMP3F                 RTC_ISR_TAMP3F_Msk\n#define RTC_ISR_TAMP2F_Pos             (14U)\n#define RTC_ISR_TAMP2F_Msk             (0x1UL << RTC_ISR_TAMP2F_Pos)           /*!< 0x00004000 */\n#define RTC_ISR_TAMP2F                 RTC_ISR_TAMP2F_Msk\n#define RTC_ISR_TAMP1F_Pos             (13U)\n#define RTC_ISR_TAMP1F_Msk             (0x1UL << RTC_ISR_TAMP1F_Pos)           /*!< 0x00002000 */\n#define RTC_ISR_TAMP1F                 RTC_ISR_TAMP1F_Msk\n#define RTC_ISR_TSOVF_Pos              (12U)\n#define RTC_ISR_TSOVF_Msk              (0x1UL << RTC_ISR_TSOVF_Pos)            /*!< 0x00001000 */\n#define RTC_ISR_TSOVF                  RTC_ISR_TSOVF_Msk\n#define RTC_ISR_TSF_Pos                (11U)\n#define RTC_ISR_TSF_Msk                (0x1UL << RTC_ISR_TSF_Pos)              /*!< 0x00000800 */\n#define RTC_ISR_TSF                    RTC_ISR_TSF_Msk\n#define RTC_ISR_WUTF_Pos               (10U)\n#define RTC_ISR_WUTF_Msk               (0x1UL << RTC_ISR_WUTF_Pos)             /*!< 0x00000400 */\n#define RTC_ISR_WUTF                   RTC_ISR_WUTF_Msk\n#define RTC_ISR_ALRBF_Pos              (9U)\n#define RTC_ISR_ALRBF_Msk              (0x1UL << RTC_ISR_ALRBF_Pos)            /*!< 0x00000200 */\n#define RTC_ISR_ALRBF                  RTC_ISR_ALRBF_Msk\n#define RTC_ISR_ALRAF_Pos              (8U)\n#define RTC_ISR_ALRAF_Msk              (0x1UL << RTC_ISR_ALRAF_Pos)            /*!< 0x00000100 */\n#define RTC_ISR_ALRAF                  RTC_ISR_ALRAF_Msk\n#define RTC_ISR_INIT_Pos               (7U)\n#define RTC_ISR_INIT_Msk               (0x1UL << RTC_ISR_INIT_Pos)             /*!< 0x00000080 */\n#define RTC_ISR_INIT                   RTC_ISR_INIT_Msk\n#define RTC_ISR_INITF_Pos              (6U)\n#define RTC_ISR_INITF_Msk              (0x1UL << RTC_ISR_INITF_Pos)            /*!< 0x00000040 */\n#define RTC_ISR_INITF                  RTC_ISR_INITF_Msk\n#define RTC_ISR_RSF_Pos                (5U)\n#define RTC_ISR_RSF_Msk                (0x1UL << RTC_ISR_RSF_Pos)              /*!< 0x00000020 */\n#define RTC_ISR_RSF                    RTC_ISR_RSF_Msk\n#define RTC_ISR_INITS_Pos              (4U)\n#define RTC_ISR_INITS_Msk              (0x1UL << RTC_ISR_INITS_Pos)            /*!< 0x00000010 */\n#define RTC_ISR_INITS                  RTC_ISR_INITS_Msk\n#define RTC_ISR_SHPF_Pos               (3U)\n#define RTC_ISR_SHPF_Msk               (0x1UL << RTC_ISR_SHPF_Pos)             /*!< 0x00000008 */\n#define RTC_ISR_SHPF                   RTC_ISR_SHPF_Msk\n#define RTC_ISR_WUTWF_Pos              (2U)\n#define RTC_ISR_WUTWF_Msk              (0x1UL << RTC_ISR_WUTWF_Pos)            /*!< 0x00000004 */\n#define RTC_ISR_WUTWF                  RTC_ISR_WUTWF_Msk\n#define RTC_ISR_ALRBWF_Pos             (1U)\n#define RTC_ISR_ALRBWF_Msk             (0x1UL << RTC_ISR_ALRBWF_Pos)           /*!< 0x00000002 */\n#define RTC_ISR_ALRBWF                 RTC_ISR_ALRBWF_Msk\n#define RTC_ISR_ALRAWF_Pos             (0U)\n#define RTC_ISR_ALRAWF_Msk             (0x1UL << RTC_ISR_ALRAWF_Pos)           /*!< 0x00000001 */\n#define RTC_ISR_ALRAWF                 RTC_ISR_ALRAWF_Msk\n\n/********************  Bits definition for RTC_PRER register  *****************/\n#define RTC_PRER_PREDIV_A_Pos          (16U)\n#define RTC_PRER_PREDIV_A_Msk          (0x7FUL << RTC_PRER_PREDIV_A_Pos)       /*!< 0x007F0000 */\n#define RTC_PRER_PREDIV_A              RTC_PRER_PREDIV_A_Msk\n#define RTC_PRER_PREDIV_S_Pos          (0U)\n#define RTC_PRER_PREDIV_S_Msk          (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)     /*!< 0x00007FFF */\n#define RTC_PRER_PREDIV_S              RTC_PRER_PREDIV_S_Msk\n\n/********************  Bits definition for RTC_WUTR register  *****************/\n#define RTC_WUTR_WUT_Pos               (0U)\n#define RTC_WUTR_WUT_Msk               (0xFFFFUL << RTC_WUTR_WUT_Pos)          /*!< 0x0000FFFF */\n#define RTC_WUTR_WUT                   RTC_WUTR_WUT_Msk\n\n/********************  Bits definition for RTC_ALRMAR register  ***************/\n#define RTC_ALRMAR_MSK4_Pos            (31U)\n#define RTC_ALRMAR_MSK4_Msk            (0x1UL << RTC_ALRMAR_MSK4_Pos)          /*!< 0x80000000 */\n#define RTC_ALRMAR_MSK4                RTC_ALRMAR_MSK4_Msk\n#define RTC_ALRMAR_WDSEL_Pos           (30U)\n#define RTC_ALRMAR_WDSEL_Msk           (0x1UL << RTC_ALRMAR_WDSEL_Pos)         /*!< 0x40000000 */\n#define RTC_ALRMAR_WDSEL               RTC_ALRMAR_WDSEL_Msk\n#define RTC_ALRMAR_DT_Pos              (28U)\n#define RTC_ALRMAR_DT_Msk              (0x3UL << RTC_ALRMAR_DT_Pos)            /*!< 0x30000000 */\n#define RTC_ALRMAR_DT                  RTC_ALRMAR_DT_Msk\n#define RTC_ALRMAR_DT_0                (0x1UL << RTC_ALRMAR_DT_Pos)             /*!< 0x10000000 */\n#define RTC_ALRMAR_DT_1                (0x2UL << RTC_ALRMAR_DT_Pos)             /*!< 0x20000000 */\n#define RTC_ALRMAR_DU_Pos              (24U)\n#define RTC_ALRMAR_DU_Msk              (0xFUL << RTC_ALRMAR_DU_Pos)            /*!< 0x0F000000 */\n#define RTC_ALRMAR_DU                  RTC_ALRMAR_DU_Msk\n#define RTC_ALRMAR_DU_0                (0x1UL << RTC_ALRMAR_DU_Pos)             /*!< 0x01000000 */\n#define RTC_ALRMAR_DU_1                (0x2UL << RTC_ALRMAR_DU_Pos)             /*!< 0x02000000 */\n#define RTC_ALRMAR_DU_2                (0x4UL << RTC_ALRMAR_DU_Pos)             /*!< 0x04000000 */\n#define RTC_ALRMAR_DU_3                (0x8UL << RTC_ALRMAR_DU_Pos)             /*!< 0x08000000 */\n#define RTC_ALRMAR_MSK3_Pos            (23U)\n#define RTC_ALRMAR_MSK3_Msk            (0x1UL << RTC_ALRMAR_MSK3_Pos)          /*!< 0x00800000 */\n#define RTC_ALRMAR_MSK3                RTC_ALRMAR_MSK3_Msk\n#define RTC_ALRMAR_PM_Pos              (22U)\n#define RTC_ALRMAR_PM_Msk              (0x1UL << RTC_ALRMAR_PM_Pos)            /*!< 0x00400000 */\n#define RTC_ALRMAR_PM                  RTC_ALRMAR_PM_Msk\n#define RTC_ALRMAR_HT_Pos              (20U)\n#define RTC_ALRMAR_HT_Msk              (0x3UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00300000 */\n#define RTC_ALRMAR_HT                  RTC_ALRMAR_HT_Msk\n#define RTC_ALRMAR_HT_0                (0x1UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00100000 */\n#define RTC_ALRMAR_HT_1                (0x2UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00200000 */\n#define RTC_ALRMAR_HU_Pos              (16U)\n#define RTC_ALRMAR_HU_Msk              (0xFUL << RTC_ALRMAR_HU_Pos)            /*!< 0x000F0000 */\n#define RTC_ALRMAR_HU                  RTC_ALRMAR_HU_Msk\n#define RTC_ALRMAR_HU_0                (0x1UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00010000 */\n#define RTC_ALRMAR_HU_1                (0x2UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00020000 */\n#define RTC_ALRMAR_HU_2                (0x4UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00040000 */\n#define RTC_ALRMAR_HU_3                (0x8UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00080000 */\n#define RTC_ALRMAR_MSK2_Pos            (15U)\n#define RTC_ALRMAR_MSK2_Msk            (0x1UL << RTC_ALRMAR_MSK2_Pos)          /*!< 0x00008000 */\n#define RTC_ALRMAR_MSK2                RTC_ALRMAR_MSK2_Msk\n#define RTC_ALRMAR_MNT_Pos             (12U)\n#define RTC_ALRMAR_MNT_Msk             (0x7UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00007000 */\n#define RTC_ALRMAR_MNT                 RTC_ALRMAR_MNT_Msk\n#define RTC_ALRMAR_MNT_0               (0x1UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00001000 */\n#define RTC_ALRMAR_MNT_1               (0x2UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00002000 */\n#define RTC_ALRMAR_MNT_2               (0x4UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00004000 */\n#define RTC_ALRMAR_MNU_Pos             (8U)\n#define RTC_ALRMAR_MNU_Msk             (0xFUL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000F00 */\n#define RTC_ALRMAR_MNU                 RTC_ALRMAR_MNU_Msk\n#define RTC_ALRMAR_MNU_0               (0x1UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000100 */\n#define RTC_ALRMAR_MNU_1               (0x2UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000200 */\n#define RTC_ALRMAR_MNU_2               (0x4UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000400 */\n#define RTC_ALRMAR_MNU_3               (0x8UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000800 */\n#define RTC_ALRMAR_MSK1_Pos            (7U)\n#define RTC_ALRMAR_MSK1_Msk            (0x1UL << RTC_ALRMAR_MSK1_Pos)          /*!< 0x00000080 */\n#define RTC_ALRMAR_MSK1                RTC_ALRMAR_MSK1_Msk\n#define RTC_ALRMAR_ST_Pos              (4U)\n#define RTC_ALRMAR_ST_Msk              (0x7UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000070 */\n#define RTC_ALRMAR_ST                  RTC_ALRMAR_ST_Msk\n#define RTC_ALRMAR_ST_0                (0x1UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000010 */\n#define RTC_ALRMAR_ST_1                (0x2UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000020 */\n#define RTC_ALRMAR_ST_2                (0x4UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000040 */\n#define RTC_ALRMAR_SU_Pos              (0U)\n#define RTC_ALRMAR_SU_Msk              (0xFUL << RTC_ALRMAR_SU_Pos)            /*!< 0x0000000F */\n#define RTC_ALRMAR_SU                  RTC_ALRMAR_SU_Msk\n#define RTC_ALRMAR_SU_0                (0x1UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000001 */\n#define RTC_ALRMAR_SU_1                (0x2UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000002 */\n#define RTC_ALRMAR_SU_2                (0x4UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000004 */\n#define RTC_ALRMAR_SU_3                (0x8UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_ALRMBR register  ***************/\n#define RTC_ALRMBR_MSK4_Pos            (31U)\n#define RTC_ALRMBR_MSK4_Msk            (0x1UL << RTC_ALRMBR_MSK4_Pos)          /*!< 0x80000000 */\n#define RTC_ALRMBR_MSK4                RTC_ALRMBR_MSK4_Msk\n#define RTC_ALRMBR_WDSEL_Pos           (30U)\n#define RTC_ALRMBR_WDSEL_Msk           (0x1UL << RTC_ALRMBR_WDSEL_Pos)         /*!< 0x40000000 */\n#define RTC_ALRMBR_WDSEL               RTC_ALRMBR_WDSEL_Msk\n#define RTC_ALRMBR_DT_Pos              (28U)\n#define RTC_ALRMBR_DT_Msk              (0x3UL << RTC_ALRMBR_DT_Pos)            /*!< 0x30000000 */\n#define RTC_ALRMBR_DT                  RTC_ALRMBR_DT_Msk\n#define RTC_ALRMBR_DT_0                (0x1UL << RTC_ALRMBR_DT_Pos)             /*!< 0x10000000 */\n#define RTC_ALRMBR_DT_1                (0x2UL << RTC_ALRMBR_DT_Pos)             /*!< 0x20000000 */\n#define RTC_ALRMBR_DU_Pos              (24U)\n#define RTC_ALRMBR_DU_Msk              (0xFUL << RTC_ALRMBR_DU_Pos)            /*!< 0x0F000000 */\n#define RTC_ALRMBR_DU                  RTC_ALRMBR_DU_Msk\n#define RTC_ALRMBR_DU_0                (0x1UL << RTC_ALRMBR_DU_Pos)             /*!< 0x01000000 */\n#define RTC_ALRMBR_DU_1                (0x2UL << RTC_ALRMBR_DU_Pos)             /*!< 0x02000000 */\n#define RTC_ALRMBR_DU_2                (0x4UL << RTC_ALRMBR_DU_Pos)             /*!< 0x04000000 */\n#define RTC_ALRMBR_DU_3                (0x8UL << RTC_ALRMBR_DU_Pos)             /*!< 0x08000000 */\n#define RTC_ALRMBR_MSK3_Pos            (23U)\n#define RTC_ALRMBR_MSK3_Msk            (0x1UL << RTC_ALRMBR_MSK3_Pos)          /*!< 0x00800000 */\n#define RTC_ALRMBR_MSK3                RTC_ALRMBR_MSK3_Msk\n#define RTC_ALRMBR_PM_Pos              (22U)\n#define RTC_ALRMBR_PM_Msk              (0x1UL << RTC_ALRMBR_PM_Pos)            /*!< 0x00400000 */\n#define RTC_ALRMBR_PM                  RTC_ALRMBR_PM_Msk\n#define RTC_ALRMBR_HT_Pos              (20U)\n#define RTC_ALRMBR_HT_Msk              (0x3UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00300000 */\n#define RTC_ALRMBR_HT                  RTC_ALRMBR_HT_Msk\n#define RTC_ALRMBR_HT_0                (0x1UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00100000 */\n#define RTC_ALRMBR_HT_1                (0x2UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00200000 */\n#define RTC_ALRMBR_HU_Pos              (16U)\n#define RTC_ALRMBR_HU_Msk              (0xFUL << RTC_ALRMBR_HU_Pos)            /*!< 0x000F0000 */\n#define RTC_ALRMBR_HU                  RTC_ALRMBR_HU_Msk\n#define RTC_ALRMBR_HU_0                (0x1UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00010000 */\n#define RTC_ALRMBR_HU_1                (0x2UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00020000 */\n#define RTC_ALRMBR_HU_2                (0x4UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00040000 */\n#define RTC_ALRMBR_HU_3                (0x8UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00080000 */\n#define RTC_ALRMBR_MSK2_Pos            (15U)\n#define RTC_ALRMBR_MSK2_Msk            (0x1UL << RTC_ALRMBR_MSK2_Pos)          /*!< 0x00008000 */\n#define RTC_ALRMBR_MSK2                RTC_ALRMBR_MSK2_Msk\n#define RTC_ALRMBR_MNT_Pos             (12U)\n#define RTC_ALRMBR_MNT_Msk             (0x7UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00007000 */\n#define RTC_ALRMBR_MNT                 RTC_ALRMBR_MNT_Msk\n#define RTC_ALRMBR_MNT_0               (0x1UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00001000 */\n#define RTC_ALRMBR_MNT_1               (0x2UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00002000 */\n#define RTC_ALRMBR_MNT_2               (0x4UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00004000 */\n#define RTC_ALRMBR_MNU_Pos             (8U)\n#define RTC_ALRMBR_MNU_Msk             (0xFUL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000F00 */\n#define RTC_ALRMBR_MNU                 RTC_ALRMBR_MNU_Msk\n#define RTC_ALRMBR_MNU_0               (0x1UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000100 */\n#define RTC_ALRMBR_MNU_1               (0x2UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000200 */\n#define RTC_ALRMBR_MNU_2               (0x4UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000400 */\n#define RTC_ALRMBR_MNU_3               (0x8UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000800 */\n#define RTC_ALRMBR_MSK1_Pos            (7U)\n#define RTC_ALRMBR_MSK1_Msk            (0x1UL << RTC_ALRMBR_MSK1_Pos)          /*!< 0x00000080 */\n#define RTC_ALRMBR_MSK1                RTC_ALRMBR_MSK1_Msk\n#define RTC_ALRMBR_ST_Pos              (4U)\n#define RTC_ALRMBR_ST_Msk              (0x7UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000070 */\n#define RTC_ALRMBR_ST                  RTC_ALRMBR_ST_Msk\n#define RTC_ALRMBR_ST_0                (0x1UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000010 */\n#define RTC_ALRMBR_ST_1                (0x2UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000020 */\n#define RTC_ALRMBR_ST_2                (0x4UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000040 */\n#define RTC_ALRMBR_SU_Pos              (0U)\n#define RTC_ALRMBR_SU_Msk              (0xFUL << RTC_ALRMBR_SU_Pos)            /*!< 0x0000000F */\n#define RTC_ALRMBR_SU                  RTC_ALRMBR_SU_Msk\n#define RTC_ALRMBR_SU_0                (0x1UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000001 */\n#define RTC_ALRMBR_SU_1                (0x2UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000002 */\n#define RTC_ALRMBR_SU_2                (0x4UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000004 */\n#define RTC_ALRMBR_SU_3                (0x8UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_WPR register  ******************/\n#define RTC_WPR_KEY_Pos                (0U)\n#define RTC_WPR_KEY_Msk                (0xFFUL << RTC_WPR_KEY_Pos)             /*!< 0x000000FF */\n#define RTC_WPR_KEY                    RTC_WPR_KEY_Msk\n\n/********************  Bits definition for RTC_SSR register  ******************/\n#define RTC_SSR_SS_Pos                 (0U)\n#define RTC_SSR_SS_Msk                 (0xFFFFUL << RTC_SSR_SS_Pos)            /*!< 0x0000FFFF */\n#define RTC_SSR_SS                     RTC_SSR_SS_Msk\n\n/********************  Bits definition for RTC_SHIFTR register  ***************/\n#define RTC_SHIFTR_SUBFS_Pos           (0U)\n#define RTC_SHIFTR_SUBFS_Msk           (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)      /*!< 0x00007FFF */\n#define RTC_SHIFTR_SUBFS               RTC_SHIFTR_SUBFS_Msk\n#define RTC_SHIFTR_ADD1S_Pos           (31U)\n#define RTC_SHIFTR_ADD1S_Msk           (0x1UL << RTC_SHIFTR_ADD1S_Pos)         /*!< 0x80000000 */\n#define RTC_SHIFTR_ADD1S               RTC_SHIFTR_ADD1S_Msk\n\n/********************  Bits definition for RTC_TSTR register  *****************/\n#define RTC_TSTR_PM_Pos                (22U)\n#define RTC_TSTR_PM_Msk                (0x1UL << RTC_TSTR_PM_Pos)              /*!< 0x00400000 */\n#define RTC_TSTR_PM                    RTC_TSTR_PM_Msk\n#define RTC_TSTR_HT_Pos                (20U)\n#define RTC_TSTR_HT_Msk                (0x3UL << RTC_TSTR_HT_Pos)              /*!< 0x00300000 */\n#define RTC_TSTR_HT                    RTC_TSTR_HT_Msk\n#define RTC_TSTR_HT_0                  (0x1UL << RTC_TSTR_HT_Pos)               /*!< 0x00100000 */\n#define RTC_TSTR_HT_1                  (0x2UL << RTC_TSTR_HT_Pos)               /*!< 0x00200000 */\n#define RTC_TSTR_HU_Pos                (16U)\n#define RTC_TSTR_HU_Msk                (0xFUL << RTC_TSTR_HU_Pos)              /*!< 0x000F0000 */\n#define RTC_TSTR_HU                    RTC_TSTR_HU_Msk\n#define RTC_TSTR_HU_0                  (0x1UL << RTC_TSTR_HU_Pos)               /*!< 0x00010000 */\n#define RTC_TSTR_HU_1                  (0x2UL << RTC_TSTR_HU_Pos)               /*!< 0x00020000 */\n#define RTC_TSTR_HU_2                  (0x4UL << RTC_TSTR_HU_Pos)               /*!< 0x00040000 */\n#define RTC_TSTR_HU_3                  (0x8UL << RTC_TSTR_HU_Pos)               /*!< 0x00080000 */\n#define RTC_TSTR_MNT_Pos               (12U)\n#define RTC_TSTR_MNT_Msk               (0x7UL << RTC_TSTR_MNT_Pos)             /*!< 0x00007000 */\n#define RTC_TSTR_MNT                   RTC_TSTR_MNT_Msk\n#define RTC_TSTR_MNT_0                 (0x1UL << RTC_TSTR_MNT_Pos)              /*!< 0x00001000 */\n#define RTC_TSTR_MNT_1                 (0x2UL << RTC_TSTR_MNT_Pos)              /*!< 0x00002000 */\n#define RTC_TSTR_MNT_2                 (0x4UL << RTC_TSTR_MNT_Pos)              /*!< 0x00004000 */\n#define RTC_TSTR_MNU_Pos               (8U)\n#define RTC_TSTR_MNU_Msk               (0xFUL << RTC_TSTR_MNU_Pos)             /*!< 0x00000F00 */\n#define RTC_TSTR_MNU                   RTC_TSTR_MNU_Msk\n#define RTC_TSTR_MNU_0                 (0x1UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000100 */\n#define RTC_TSTR_MNU_1                 (0x2UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000200 */\n#define RTC_TSTR_MNU_2                 (0x4UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000400 */\n#define RTC_TSTR_MNU_3                 (0x8UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000800 */\n#define RTC_TSTR_ST_Pos                (4U)\n#define RTC_TSTR_ST_Msk                (0x7UL << RTC_TSTR_ST_Pos)              /*!< 0x00000070 */\n#define RTC_TSTR_ST                    RTC_TSTR_ST_Msk\n#define RTC_TSTR_ST_0                  (0x1UL << RTC_TSTR_ST_Pos)               /*!< 0x00000010 */\n#define RTC_TSTR_ST_1                  (0x2UL << RTC_TSTR_ST_Pos)               /*!< 0x00000020 */\n#define RTC_TSTR_ST_2                  (0x4UL << RTC_TSTR_ST_Pos)               /*!< 0x00000040 */\n#define RTC_TSTR_SU_Pos                (0U)\n#define RTC_TSTR_SU_Msk                (0xFUL << RTC_TSTR_SU_Pos)              /*!< 0x0000000F */\n#define RTC_TSTR_SU                    RTC_TSTR_SU_Msk\n#define RTC_TSTR_SU_0                  (0x1UL << RTC_TSTR_SU_Pos)               /*!< 0x00000001 */\n#define RTC_TSTR_SU_1                  (0x2UL << RTC_TSTR_SU_Pos)               /*!< 0x00000002 */\n#define RTC_TSTR_SU_2                  (0x4UL << RTC_TSTR_SU_Pos)               /*!< 0x00000004 */\n#define RTC_TSTR_SU_3                  (0x8UL << RTC_TSTR_SU_Pos)               /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_TSDR register  *****************/\n#define RTC_TSDR_WDU_Pos               (13U)\n#define RTC_TSDR_WDU_Msk               (0x7UL << RTC_TSDR_WDU_Pos)             /*!< 0x0000E000 */\n#define RTC_TSDR_WDU                   RTC_TSDR_WDU_Msk\n#define RTC_TSDR_WDU_0                 (0x1UL << RTC_TSDR_WDU_Pos)              /*!< 0x00002000 */\n#define RTC_TSDR_WDU_1                 (0x2UL << RTC_TSDR_WDU_Pos)              /*!< 0x00004000 */\n#define RTC_TSDR_WDU_2                 (0x4UL << RTC_TSDR_WDU_Pos)              /*!< 0x00008000 */\n#define RTC_TSDR_MT_Pos                (12U)\n#define RTC_TSDR_MT_Msk                (0x1UL << RTC_TSDR_MT_Pos)              /*!< 0x00001000 */\n#define RTC_TSDR_MT                    RTC_TSDR_MT_Msk\n#define RTC_TSDR_MU_Pos                (8U)\n#define RTC_TSDR_MU_Msk                (0xFUL << RTC_TSDR_MU_Pos)              /*!< 0x00000F00 */\n#define RTC_TSDR_MU                    RTC_TSDR_MU_Msk\n#define RTC_TSDR_MU_0                  (0x1UL << RTC_TSDR_MU_Pos)               /*!< 0x00000100 */\n#define RTC_TSDR_MU_1                  (0x2UL << RTC_TSDR_MU_Pos)               /*!< 0x00000200 */\n#define RTC_TSDR_MU_2                  (0x4UL << RTC_TSDR_MU_Pos)               /*!< 0x00000400 */\n#define RTC_TSDR_MU_3                  (0x8UL << RTC_TSDR_MU_Pos)               /*!< 0x00000800 */\n#define RTC_TSDR_DT_Pos                (4U)\n#define RTC_TSDR_DT_Msk                (0x3UL << RTC_TSDR_DT_Pos)              /*!< 0x00000030 */\n#define RTC_TSDR_DT                    RTC_TSDR_DT_Msk\n#define RTC_TSDR_DT_0                  (0x1UL << RTC_TSDR_DT_Pos)               /*!< 0x00000010 */\n#define RTC_TSDR_DT_1                  (0x2UL << RTC_TSDR_DT_Pos)               /*!< 0x00000020 */\n#define RTC_TSDR_DU_Pos                (0U)\n#define RTC_TSDR_DU_Msk                (0xFUL << RTC_TSDR_DU_Pos)              /*!< 0x0000000F */\n#define RTC_TSDR_DU                    RTC_TSDR_DU_Msk\n#define RTC_TSDR_DU_0                  (0x1UL << RTC_TSDR_DU_Pos)               /*!< 0x00000001 */\n#define RTC_TSDR_DU_1                  (0x2UL << RTC_TSDR_DU_Pos)               /*!< 0x00000002 */\n#define RTC_TSDR_DU_2                  (0x4UL << RTC_TSDR_DU_Pos)               /*!< 0x00000004 */\n#define RTC_TSDR_DU_3                  (0x8UL << RTC_TSDR_DU_Pos)               /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_TSSSR register  ****************/\n#define RTC_TSSSR_SS_Pos               (0U)\n#define RTC_TSSSR_SS_Msk               (0xFFFFUL << RTC_TSSSR_SS_Pos)          /*!< 0x0000FFFF */\n#define RTC_TSSSR_SS                   RTC_TSSSR_SS_Msk\n\n/********************  Bits definition for RTC_CALR register  *****************/\n#define RTC_CALR_CALP_Pos              (15U)\n#define RTC_CALR_CALP_Msk              (0x1UL << RTC_CALR_CALP_Pos)            /*!< 0x00008000 */\n#define RTC_CALR_CALP                  RTC_CALR_CALP_Msk\n#define RTC_CALR_CALW8_Pos             (14U)\n#define RTC_CALR_CALW8_Msk             (0x1UL << RTC_CALR_CALW8_Pos)           /*!< 0x00004000 */\n#define RTC_CALR_CALW8                 RTC_CALR_CALW8_Msk\n#define RTC_CALR_CALW16_Pos            (13U)\n#define RTC_CALR_CALW16_Msk            (0x1UL << RTC_CALR_CALW16_Pos)          /*!< 0x00002000 */\n#define RTC_CALR_CALW16                RTC_CALR_CALW16_Msk\n#define RTC_CALR_CALM_Pos              (0U)\n#define RTC_CALR_CALM_Msk              (0x1FFUL << RTC_CALR_CALM_Pos)          /*!< 0x000001FF */\n#define RTC_CALR_CALM                  RTC_CALR_CALM_Msk\n#define RTC_CALR_CALM_0                (0x001UL << RTC_CALR_CALM_Pos)           /*!< 0x00000001 */\n#define RTC_CALR_CALM_1                (0x002UL << RTC_CALR_CALM_Pos)           /*!< 0x00000002 */\n#define RTC_CALR_CALM_2                (0x004UL << RTC_CALR_CALM_Pos)           /*!< 0x00000004 */\n#define RTC_CALR_CALM_3                (0x008UL << RTC_CALR_CALM_Pos)           /*!< 0x00000008 */\n#define RTC_CALR_CALM_4                (0x010UL << RTC_CALR_CALM_Pos)           /*!< 0x00000010 */\n#define RTC_CALR_CALM_5                (0x020UL << RTC_CALR_CALM_Pos)           /*!< 0x00000020 */\n#define RTC_CALR_CALM_6                (0x040UL << RTC_CALR_CALM_Pos)           /*!< 0x00000040 */\n#define RTC_CALR_CALM_7                (0x080UL << RTC_CALR_CALM_Pos)           /*!< 0x00000080 */\n#define RTC_CALR_CALM_8                (0x100UL << RTC_CALR_CALM_Pos)           /*!< 0x00000100 */\n\n/********************  Bits definition for RTC_TAMPCR register  ***************/\n#define RTC_TAMPCR_TAMP3MF_Pos         (24U)\n#define RTC_TAMPCR_TAMP3MF_Msk         (0x1UL << RTC_TAMPCR_TAMP3MF_Pos)       /*!< 0x01000000 */\n#define RTC_TAMPCR_TAMP3MF             RTC_TAMPCR_TAMP3MF_Msk\n#define RTC_TAMPCR_TAMP3NOERASE_Pos    (23U)\n#define RTC_TAMPCR_TAMP3NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos)  /*!< 0x00800000 */\n#define RTC_TAMPCR_TAMP3NOERASE        RTC_TAMPCR_TAMP3NOERASE_Msk\n#define RTC_TAMPCR_TAMP3IE_Pos         (22U)\n#define RTC_TAMPCR_TAMP3IE_Msk         (0x1UL << RTC_TAMPCR_TAMP3IE_Pos)       /*!< 0x00400000 */\n#define RTC_TAMPCR_TAMP3IE             RTC_TAMPCR_TAMP3IE_Msk\n#define RTC_TAMPCR_TAMP2MF_Pos         (21U)\n#define RTC_TAMPCR_TAMP2MF_Msk         (0x1UL << RTC_TAMPCR_TAMP2MF_Pos)       /*!< 0x00200000 */\n#define RTC_TAMPCR_TAMP2MF             RTC_TAMPCR_TAMP2MF_Msk\n#define RTC_TAMPCR_TAMP2NOERASE_Pos    (20U)\n#define RTC_TAMPCR_TAMP2NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos)  /*!< 0x00100000 */\n#define RTC_TAMPCR_TAMP2NOERASE        RTC_TAMPCR_TAMP2NOERASE_Msk\n#define RTC_TAMPCR_TAMP2IE_Pos         (19U)\n#define RTC_TAMPCR_TAMP2IE_Msk         (0x1UL << RTC_TAMPCR_TAMP2IE_Pos)       /*!< 0x00080000 */\n#define RTC_TAMPCR_TAMP2IE             RTC_TAMPCR_TAMP2IE_Msk\n#define RTC_TAMPCR_TAMP1MF_Pos         (18U)\n#define RTC_TAMPCR_TAMP1MF_Msk         (0x1UL << RTC_TAMPCR_TAMP1MF_Pos)       /*!< 0x00040000 */\n#define RTC_TAMPCR_TAMP1MF             RTC_TAMPCR_TAMP1MF_Msk\n#define RTC_TAMPCR_TAMP1NOERASE_Pos    (17U)\n#define RTC_TAMPCR_TAMP1NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos)  /*!< 0x00020000 */\n#define RTC_TAMPCR_TAMP1NOERASE        RTC_TAMPCR_TAMP1NOERASE_Msk\n#define RTC_TAMPCR_TAMP1IE_Pos         (16U)\n#define RTC_TAMPCR_TAMP1IE_Msk         (0x1UL << RTC_TAMPCR_TAMP1IE_Pos)       /*!< 0x00010000 */\n#define RTC_TAMPCR_TAMP1IE             RTC_TAMPCR_TAMP1IE_Msk\n#define RTC_TAMPCR_TAMPPUDIS_Pos       (15U)\n#define RTC_TAMPCR_TAMPPUDIS_Msk       (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos)     /*!< 0x00008000 */\n#define RTC_TAMPCR_TAMPPUDIS           RTC_TAMPCR_TAMPPUDIS_Msk\n#define RTC_TAMPCR_TAMPPRCH_Pos        (13U)\n#define RTC_TAMPCR_TAMPPRCH_Msk        (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos)      /*!< 0x00006000 */\n#define RTC_TAMPCR_TAMPPRCH            RTC_TAMPCR_TAMPPRCH_Msk\n#define RTC_TAMPCR_TAMPPRCH_0          (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00002000 */\n#define RTC_TAMPCR_TAMPPRCH_1          (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00004000 */\n#define RTC_TAMPCR_TAMPFLT_Pos         (11U)\n#define RTC_TAMPCR_TAMPFLT_Msk         (0x3UL << RTC_TAMPCR_TAMPFLT_Pos)       /*!< 0x00001800 */\n#define RTC_TAMPCR_TAMPFLT             RTC_TAMPCR_TAMPFLT_Msk\n#define RTC_TAMPCR_TAMPFLT_0           (0x1UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00000800 */\n#define RTC_TAMPCR_TAMPFLT_1           (0x2UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001000 */\n#define RTC_TAMPCR_TAMPFREQ_Pos        (8U)\n#define RTC_TAMPCR_TAMPFREQ_Msk        (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos)      /*!< 0x00000700 */\n#define RTC_TAMPCR_TAMPFREQ            RTC_TAMPCR_TAMPFREQ_Msk\n#define RTC_TAMPCR_TAMPFREQ_0          (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000100 */\n#define RTC_TAMPCR_TAMPFREQ_1          (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000200 */\n#define RTC_TAMPCR_TAMPFREQ_2          (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000400 */\n#define RTC_TAMPCR_TAMPTS_Pos          (7U)\n#define RTC_TAMPCR_TAMPTS_Msk          (0x1UL << RTC_TAMPCR_TAMPTS_Pos)        /*!< 0x00000080 */\n#define RTC_TAMPCR_TAMPTS              RTC_TAMPCR_TAMPTS_Msk\n#define RTC_TAMPCR_TAMP3TRG_Pos        (6U)\n#define RTC_TAMPCR_TAMP3TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos)      /*!< 0x00000040 */\n#define RTC_TAMPCR_TAMP3TRG            RTC_TAMPCR_TAMP3TRG_Msk\n#define RTC_TAMPCR_TAMP3E_Pos          (5U)\n#define RTC_TAMPCR_TAMP3E_Msk          (0x1UL << RTC_TAMPCR_TAMP3E_Pos)        /*!< 0x00000020 */\n#define RTC_TAMPCR_TAMP3E              RTC_TAMPCR_TAMP3E_Msk\n#define RTC_TAMPCR_TAMP2TRG_Pos        (4U)\n#define RTC_TAMPCR_TAMP2TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos)      /*!< 0x00000010 */\n#define RTC_TAMPCR_TAMP2TRG            RTC_TAMPCR_TAMP2TRG_Msk\n#define RTC_TAMPCR_TAMP2E_Pos          (3U)\n#define RTC_TAMPCR_TAMP2E_Msk          (0x1UL << RTC_TAMPCR_TAMP2E_Pos)        /*!< 0x00000008 */\n#define RTC_TAMPCR_TAMP2E              RTC_TAMPCR_TAMP2E_Msk\n#define RTC_TAMPCR_TAMPIE_Pos          (2U)\n#define RTC_TAMPCR_TAMPIE_Msk          (0x1UL << RTC_TAMPCR_TAMPIE_Pos)        /*!< 0x00000004 */\n#define RTC_TAMPCR_TAMPIE              RTC_TAMPCR_TAMPIE_Msk\n#define RTC_TAMPCR_TAMP1TRG_Pos        (1U)\n#define RTC_TAMPCR_TAMP1TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos)      /*!< 0x00000002 */\n#define RTC_TAMPCR_TAMP1TRG            RTC_TAMPCR_TAMP1TRG_Msk\n#define RTC_TAMPCR_TAMP1E_Pos          (0U)\n#define RTC_TAMPCR_TAMP1E_Msk          (0x1UL << RTC_TAMPCR_TAMP1E_Pos)        /*!< 0x00000001 */\n#define RTC_TAMPCR_TAMP1E              RTC_TAMPCR_TAMP1E_Msk\n\n/********************  Bits definition for RTC_ALRMASSR register  *************/\n#define RTC_ALRMASSR_MASKSS_Pos        (24U)\n#define RTC_ALRMASSR_MASKSS_Msk        (0xFUL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x0F000000 */\n#define RTC_ALRMASSR_MASKSS            RTC_ALRMASSR_MASKSS_Msk\n#define RTC_ALRMASSR_MASKSS_0          (0x1UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x01000000 */\n#define RTC_ALRMASSR_MASKSS_1          (0x2UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x02000000 */\n#define RTC_ALRMASSR_MASKSS_2          (0x4UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x04000000 */\n#define RTC_ALRMASSR_MASKSS_3          (0x8UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x08000000 */\n#define RTC_ALRMASSR_SS_Pos            (0U)\n#define RTC_ALRMASSR_SS_Msk            (0x7FFFUL << RTC_ALRMASSR_SS_Pos)       /*!< 0x00007FFF */\n#define RTC_ALRMASSR_SS                RTC_ALRMASSR_SS_Msk\n\n/********************  Bits definition for RTC_ALRMBSSR register  *************/\n#define RTC_ALRMBSSR_MASKSS_Pos        (24U)\n#define RTC_ALRMBSSR_MASKSS_Msk        (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x0F000000 */\n#define RTC_ALRMBSSR_MASKSS            RTC_ALRMBSSR_MASKSS_Msk\n#define RTC_ALRMBSSR_MASKSS_0          (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x01000000 */\n#define RTC_ALRMBSSR_MASKSS_1          (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x02000000 */\n#define RTC_ALRMBSSR_MASKSS_2          (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x04000000 */\n#define RTC_ALRMBSSR_MASKSS_3          (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x08000000 */\n#define RTC_ALRMBSSR_SS_Pos            (0U)\n#define RTC_ALRMBSSR_SS_Msk            (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)       /*!< 0x00007FFF */\n#define RTC_ALRMBSSR_SS                RTC_ALRMBSSR_SS_Msk\n\n/********************  Bits definition for RTC_OR register  *******************/\n#define RTC_OR_OUT_RMP_Pos             (1U)\n#define RTC_OR_OUT_RMP_Msk             (0x1UL << RTC_OR_OUT_RMP_Pos)           /*!< 0x00000002 */\n#define RTC_OR_OUT_RMP                 RTC_OR_OUT_RMP_Msk\n#define RTC_OR_ALARMOUTTYPE_Pos        (0U)\n#define RTC_OR_ALARMOUTTYPE_Msk        (0x1UL << RTC_OR_ALARMOUTTYPE_Pos)      /*!< 0x00000001 */\n#define RTC_OR_ALARMOUTTYPE            RTC_OR_ALARMOUTTYPE_Msk\n\n/********************  Bits definition for RTC_BKP0R register  ****************/\n#define RTC_BKP0R_Pos                  (0U)\n#define RTC_BKP0R_Msk                  (0xFFFFFFFFUL << RTC_BKP0R_Pos)         /*!< 0xFFFFFFFF */\n#define RTC_BKP0R                      RTC_BKP0R_Msk\n\n/********************  Bits definition for RTC_BKP1R register  ****************/\n#define RTC_BKP1R_Pos                  (0U)\n#define RTC_BKP1R_Msk                  (0xFFFFFFFFUL << RTC_BKP1R_Pos)         /*!< 0xFFFFFFFF */\n#define RTC_BKP1R                      RTC_BKP1R_Msk\n\n/********************  Bits definition for RTC_BKP2R register  ****************/\n#define RTC_BKP2R_Pos                  (0U)\n#define RTC_BKP2R_Msk                  (0xFFFFFFFFUL << RTC_BKP2R_Pos)         /*!< 0xFFFFFFFF */\n#define RTC_BKP2R                      RTC_BKP2R_Msk\n\n/********************  Bits definition for RTC_BKP3R register  ****************/\n#define RTC_BKP3R_Pos                  (0U)\n#define RTC_BKP3R_Msk                  (0xFFFFFFFFUL << RTC_BKP3R_Pos)         /*!< 0xFFFFFFFF */\n#define RTC_BKP3R                      RTC_BKP3R_Msk\n\n/********************  Bits definition for RTC_BKP4R register  ****************/\n#define RTC_BKP4R_Pos                  (0U)\n#define RTC_BKP4R_Msk                  (0xFFFFFFFFUL << RTC_BKP4R_Pos)         /*!< 0xFFFFFFFF */\n#define RTC_BKP4R                      RTC_BKP4R_Msk\n\n/********************  Bits definition for RTC_BKP5R register  ****************/\n#define RTC_BKP5R_Pos                  (0U)\n#define RTC_BKP5R_Msk                  (0xFFFFFFFFUL << RTC_BKP5R_Pos)         /*!< 0xFFFFFFFF */\n#define RTC_BKP5R                      RTC_BKP5R_Msk\n\n/********************  Bits definition for RTC_BKP6R register  ****************/\n#define RTC_BKP6R_Pos                  (0U)\n#define RTC_BKP6R_Msk                  (0xFFFFFFFFUL << RTC_BKP6R_Pos)         /*!< 0xFFFFFFFF */\n#define RTC_BKP6R                      RTC_BKP6R_Msk\n\n/********************  Bits definition for RTC_BKP7R register  ****************/\n#define RTC_BKP7R_Pos                  (0U)\n#define RTC_BKP7R_Msk                  (0xFFFFFFFFUL << RTC_BKP7R_Pos)         /*!< 0xFFFFFFFF */\n#define RTC_BKP7R                      RTC_BKP7R_Msk\n\n/********************  Bits definition for RTC_BKP8R register  ****************/\n#define RTC_BKP8R_Pos                  (0U)\n#define RTC_BKP8R_Msk                  (0xFFFFFFFFUL << RTC_BKP8R_Pos)         /*!< 0xFFFFFFFF */\n#define RTC_BKP8R                      RTC_BKP8R_Msk\n\n/********************  Bits definition for RTC_BKP9R register  ****************/\n#define RTC_BKP9R_Pos                  (0U)\n#define RTC_BKP9R_Msk                  (0xFFFFFFFFUL << RTC_BKP9R_Pos)         /*!< 0xFFFFFFFF */\n#define RTC_BKP9R                      RTC_BKP9R_Msk\n\n/********************  Bits definition for RTC_BKP10R register  ***************/\n#define RTC_BKP10R_Pos                 (0U)\n#define RTC_BKP10R_Msk                 (0xFFFFFFFFUL << RTC_BKP10R_Pos)        /*!< 0xFFFFFFFF */\n#define RTC_BKP10R                     RTC_BKP10R_Msk\n\n/********************  Bits definition for RTC_BKP11R register  ***************/\n#define RTC_BKP11R_Pos                 (0U)\n#define RTC_BKP11R_Msk                 (0xFFFFFFFFUL << RTC_BKP11R_Pos)        /*!< 0xFFFFFFFF */\n#define RTC_BKP11R                     RTC_BKP11R_Msk\n\n/********************  Bits definition for RTC_BKP12R register  ***************/\n#define RTC_BKP12R_Pos                 (0U)\n#define RTC_BKP12R_Msk                 (0xFFFFFFFFUL << RTC_BKP12R_Pos)        /*!< 0xFFFFFFFF */\n#define RTC_BKP12R                     RTC_BKP12R_Msk\n\n/********************  Bits definition for RTC_BKP13R register  ***************/\n#define RTC_BKP13R_Pos                 (0U)\n#define RTC_BKP13R_Msk                 (0xFFFFFFFFUL << RTC_BKP13R_Pos)        /*!< 0xFFFFFFFF */\n#define RTC_BKP13R                     RTC_BKP13R_Msk\n\n/********************  Bits definition for RTC_BKP14R register  ***************/\n#define RTC_BKP14R_Pos                 (0U)\n#define RTC_BKP14R_Msk                 (0xFFFFFFFFUL << RTC_BKP14R_Pos)        /*!< 0xFFFFFFFF */\n#define RTC_BKP14R                     RTC_BKP14R_Msk\n\n/********************  Bits definition for RTC_BKP15R register  ***************/\n#define RTC_BKP15R_Pos                 (0U)\n#define RTC_BKP15R_Msk                 (0xFFFFFFFFUL << RTC_BKP15R_Pos)        /*!< 0xFFFFFFFF */\n#define RTC_BKP15R                     RTC_BKP15R_Msk\n\n/********************  Bits definition for RTC_BKP16R register  ***************/\n#define RTC_BKP16R_Pos                 (0U)\n#define RTC_BKP16R_Msk                 (0xFFFFFFFFUL << RTC_BKP16R_Pos)        /*!< 0xFFFFFFFF */\n#define RTC_BKP16R                     RTC_BKP16R_Msk\n\n/********************  Bits definition for RTC_BKP17R register  ***************/\n#define RTC_BKP17R_Pos                 (0U)\n#define RTC_BKP17R_Msk                 (0xFFFFFFFFUL << RTC_BKP17R_Pos)        /*!< 0xFFFFFFFF */\n#define RTC_BKP17R                     RTC_BKP17R_Msk\n\n/********************  Bits definition for RTC_BKP18R register  ***************/\n#define RTC_BKP18R_Pos                 (0U)\n#define RTC_BKP18R_Msk                 (0xFFFFFFFFUL << RTC_BKP18R_Pos)        /*!< 0xFFFFFFFF */\n#define RTC_BKP18R                     RTC_BKP18R_Msk\n\n/********************  Bits definition for RTC_BKP19R register  ***************/\n#define RTC_BKP19R_Pos                 (0U)\n#define RTC_BKP19R_Msk                 (0xFFFFFFFFUL << RTC_BKP19R_Pos)        /*!< 0xFFFFFFFF */\n#define RTC_BKP19R                     RTC_BKP19R_Msk\n\n/********************  Bits definition for RTC_BKP20R register  ***************/\n#define RTC_BKP20R_Pos                 (0U)\n#define RTC_BKP20R_Msk                 (0xFFFFFFFFUL << RTC_BKP20R_Pos)        /*!< 0xFFFFFFFF */\n#define RTC_BKP20R                     RTC_BKP20R_Msk\n\n/********************  Bits definition for RTC_BKP21R register  ***************/\n#define RTC_BKP21R_Pos                 (0U)\n#define RTC_BKP21R_Msk                 (0xFFFFFFFFUL << RTC_BKP21R_Pos)        /*!< 0xFFFFFFFF */\n#define RTC_BKP21R                     RTC_BKP21R_Msk\n\n/********************  Bits definition for RTC_BKP22R register  ***************/\n#define RTC_BKP22R_Pos                 (0U)\n#define RTC_BKP22R_Msk                 (0xFFFFFFFFUL << RTC_BKP22R_Pos)        /*!< 0xFFFFFFFF */\n#define RTC_BKP22R                     RTC_BKP22R_Msk\n\n/********************  Bits definition for RTC_BKP23R register  ***************/\n#define RTC_BKP23R_Pos                 (0U)\n#define RTC_BKP23R_Msk                 (0xFFFFFFFFUL << RTC_BKP23R_Pos)        /*!< 0xFFFFFFFF */\n#define RTC_BKP23R                     RTC_BKP23R_Msk\n\n/********************  Bits definition for RTC_BKP24R register  ***************/\n#define RTC_BKP24R_Pos                 (0U)\n#define RTC_BKP24R_Msk                 (0xFFFFFFFFUL << RTC_BKP24R_Pos)        /*!< 0xFFFFFFFF */\n#define RTC_BKP24R                     RTC_BKP24R_Msk\n\n/********************  Bits definition for RTC_BKP25R register  ***************/\n#define RTC_BKP25R_Pos                 (0U)\n#define RTC_BKP25R_Msk                 (0xFFFFFFFFUL << RTC_BKP25R_Pos)        /*!< 0xFFFFFFFF */\n#define RTC_BKP25R                     RTC_BKP25R_Msk\n\n/********************  Bits definition for RTC_BKP26R register  ***************/\n#define RTC_BKP26R_Pos                 (0U)\n#define RTC_BKP26R_Msk                 (0xFFFFFFFFUL << RTC_BKP26R_Pos)        /*!< 0xFFFFFFFF */\n#define RTC_BKP26R                     RTC_BKP26R_Msk\n\n/********************  Bits definition for RTC_BKP27R register  ***************/\n#define RTC_BKP27R_Pos                 (0U)\n#define RTC_BKP27R_Msk                 (0xFFFFFFFFUL << RTC_BKP27R_Pos)        /*!< 0xFFFFFFFF */\n#define RTC_BKP27R                     RTC_BKP27R_Msk\n\n/********************  Bits definition for RTC_BKP28R register  ***************/\n#define RTC_BKP28R_Pos                 (0U)\n#define RTC_BKP28R_Msk                 (0xFFFFFFFFUL << RTC_BKP28R_Pos)        /*!< 0xFFFFFFFF */\n#define RTC_BKP28R                     RTC_BKP28R_Msk\n\n/********************  Bits definition for RTC_BKP29R register  ***************/\n#define RTC_BKP29R_Pos                 (0U)\n#define RTC_BKP29R_Msk                 (0xFFFFFFFFUL << RTC_BKP29R_Pos)        /*!< 0xFFFFFFFF */\n#define RTC_BKP29R                     RTC_BKP29R_Msk\n\n/********************  Bits definition for RTC_BKP30R register  ***************/\n#define RTC_BKP30R_Pos                 (0U)\n#define RTC_BKP30R_Msk                 (0xFFFFFFFFUL << RTC_BKP30R_Pos)        /*!< 0xFFFFFFFF */\n#define RTC_BKP30R                     RTC_BKP30R_Msk\n\n/********************  Bits definition for RTC_BKP31R register  ***************/\n#define RTC_BKP31R_Pos                 (0U)\n#define RTC_BKP31R_Msk                 (0xFFFFFFFFUL << RTC_BKP31R_Pos)        /*!< 0xFFFFFFFF */\n#define RTC_BKP31R                     RTC_BKP31R_Msk\n\n/******************** Number of backup registers ******************************/\n#define RTC_BKP_NUMBER_Pos             (5U)\n#define RTC_BKP_NUMBER_Msk             (0x1UL << RTC_BKP_NUMBER_Pos)           /*!< 0x00000020 */\n#define RTC_BKP_NUMBER                 RTC_BKP_NUMBER_Msk\n\n/******************************************************************************/\n/*                                                                            */\n/*                              SPDIF-RX Interface                            */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for SPDIF_CR register  ******************/\n#define SPDIFRX_CR_SPDIFEN_Pos      (0U)\n#define SPDIFRX_CR_SPDIFEN_Msk      (0x3UL << SPDIFRX_CR_SPDIFEN_Pos)          /*!< 0x00000003 */\n#define SPDIFRX_CR_SPDIFEN          SPDIFRX_CR_SPDIFEN_Msk                     /*!<Peripheral Block Enable                      */\n#define SPDIFRX_CR_RXDMAEN_Pos      (2U)\n#define SPDIFRX_CR_RXDMAEN_Msk      (0x1UL << SPDIFRX_CR_RXDMAEN_Pos)          /*!< 0x00000004 */\n#define SPDIFRX_CR_RXDMAEN          SPDIFRX_CR_RXDMAEN_Msk                     /*!<Receiver DMA Enable for data flow            */\n#define SPDIFRX_CR_RXSTEO_Pos       (3U)\n#define SPDIFRX_CR_RXSTEO_Msk       (0x1UL << SPDIFRX_CR_RXSTEO_Pos)           /*!< 0x00000008 */\n#define SPDIFRX_CR_RXSTEO           SPDIFRX_CR_RXSTEO_Msk                      /*!<Stereo Mode                                  */\n#define SPDIFRX_CR_DRFMT_Pos        (4U)\n#define SPDIFRX_CR_DRFMT_Msk        (0x3UL << SPDIFRX_CR_DRFMT_Pos)            /*!< 0x00000030 */\n#define SPDIFRX_CR_DRFMT            SPDIFRX_CR_DRFMT_Msk                       /*!<RX Data format                               */\n#define SPDIFRX_CR_PMSK_Pos         (6U)\n#define SPDIFRX_CR_PMSK_Msk         (0x1UL << SPDIFRX_CR_PMSK_Pos)             /*!< 0x00000040 */\n#define SPDIFRX_CR_PMSK             SPDIFRX_CR_PMSK_Msk                        /*!<Mask Parity error bit                        */\n#define SPDIFRX_CR_VMSK_Pos         (7U)\n#define SPDIFRX_CR_VMSK_Msk         (0x1UL << SPDIFRX_CR_VMSK_Pos)             /*!< 0x00000080 */\n#define SPDIFRX_CR_VMSK             SPDIFRX_CR_VMSK_Msk                        /*!<Mask of Validity bit                         */\n#define SPDIFRX_CR_CUMSK_Pos        (8U)\n#define SPDIFRX_CR_CUMSK_Msk        (0x1UL << SPDIFRX_CR_CUMSK_Pos)            /*!< 0x00000100 */\n#define SPDIFRX_CR_CUMSK            SPDIFRX_CR_CUMSK_Msk                       /*!<Mask of channel status and user bits         */\n#define SPDIFRX_CR_PTMSK_Pos        (9U)\n#define SPDIFRX_CR_PTMSK_Msk        (0x1UL << SPDIFRX_CR_PTMSK_Pos)            /*!< 0x00000200 */\n#define SPDIFRX_CR_PTMSK            SPDIFRX_CR_PTMSK_Msk                       /*!<Mask of Preamble Type bits                   */\n#define SPDIFRX_CR_CBDMAEN_Pos      (10U)\n#define SPDIFRX_CR_CBDMAEN_Msk      (0x1UL << SPDIFRX_CR_CBDMAEN_Pos)          /*!< 0x00000400 */\n#define SPDIFRX_CR_CBDMAEN          SPDIFRX_CR_CBDMAEN_Msk                     /*!<Control Buffer DMA ENable for control flow   */\n#define SPDIFRX_CR_CHSEL_Pos        (11U)\n#define SPDIFRX_CR_CHSEL_Msk        (0x1UL << SPDIFRX_CR_CHSEL_Pos)            /*!< 0x00000800 */\n#define SPDIFRX_CR_CHSEL            SPDIFRX_CR_CHSEL_Msk                       /*!<Channel Selection                            */\n#define SPDIFRX_CR_NBTR_Pos         (12U)\n#define SPDIFRX_CR_NBTR_Msk         (0x3UL << SPDIFRX_CR_NBTR_Pos)             /*!< 0x00003000 */\n#define SPDIFRX_CR_NBTR             SPDIFRX_CR_NBTR_Msk                        /*!<Maximum allowed re-tries during synchronization phase */\n#define SPDIFRX_CR_WFA_Pos          (14U)\n#define SPDIFRX_CR_WFA_Msk          (0x1UL << SPDIFRX_CR_WFA_Pos)              /*!< 0x00004000 */\n#define SPDIFRX_CR_WFA              SPDIFRX_CR_WFA_Msk                         /*!<Wait For Activity     */\n#define SPDIFRX_CR_INSEL_Pos        (16U)\n#define SPDIFRX_CR_INSEL_Msk        (0x7UL << SPDIFRX_CR_INSEL_Pos)            /*!< 0x00070000 */\n#define SPDIFRX_CR_INSEL            SPDIFRX_CR_INSEL_Msk                       /*!<SPDIF input selection */\n#define SPDIFRX_CR_CKSEN_Pos        (20U)\n#define SPDIFRX_CR_CKSEN_Msk        (0x1UL << SPDIFRX_CR_CKSEN_Pos)            /*!< 0x00100000 */\n#define SPDIFRX_CR_CKSEN            SPDIFRX_CR_CKSEN_Msk                       /*!<Symbol Clock Enable */\n#define SPDIFRX_CR_CKSBKPEN_Pos     (21U)\n#define SPDIFRX_CR_CKSBKPEN_Msk     (0x1UL << SPDIFRX_CR_CKSBKPEN_Pos)         /*!< 0x00200000 */\n#define SPDIFRX_CR_CKSBKPEN         SPDIFRX_CR_CKSBKPEN_Msk                    /*!<Backup Symbol Clock Enable */\n\n/*******************  Bit definition for SPDIFRX_IMR register  *******************/\n#define SPDIFRX_IMR_RXNEIE_Pos      (0U)\n#define SPDIFRX_IMR_RXNEIE_Msk      (0x1UL << SPDIFRX_IMR_RXNEIE_Pos)          /*!< 0x00000001 */\n#define SPDIFRX_IMR_RXNEIE          SPDIFRX_IMR_RXNEIE_Msk                     /*!<RXNE interrupt enable                              */\n#define SPDIFRX_IMR_CSRNEIE_Pos     (1U)\n#define SPDIFRX_IMR_CSRNEIE_Msk     (0x1UL << SPDIFRX_IMR_CSRNEIE_Pos)         /*!< 0x00000002 */\n#define SPDIFRX_IMR_CSRNEIE         SPDIFRX_IMR_CSRNEIE_Msk                    /*!<Control Buffer Ready Interrupt Enable              */\n#define SPDIFRX_IMR_PERRIE_Pos      (2U)\n#define SPDIFRX_IMR_PERRIE_Msk      (0x1UL << SPDIFRX_IMR_PERRIE_Pos)          /*!< 0x00000004 */\n#define SPDIFRX_IMR_PERRIE          SPDIFRX_IMR_PERRIE_Msk                     /*!<Parity error interrupt enable                      */\n#define SPDIFRX_IMR_OVRIE_Pos       (3U)\n#define SPDIFRX_IMR_OVRIE_Msk       (0x1UL << SPDIFRX_IMR_OVRIE_Pos)           /*!< 0x00000008 */\n#define SPDIFRX_IMR_OVRIE           SPDIFRX_IMR_OVRIE_Msk                      /*!<Overrun error Interrupt Enable                     */\n#define SPDIFRX_IMR_SBLKIE_Pos      (4U)\n#define SPDIFRX_IMR_SBLKIE_Msk      (0x1UL << SPDIFRX_IMR_SBLKIE_Pos)          /*!< 0x00000010 */\n#define SPDIFRX_IMR_SBLKIE          SPDIFRX_IMR_SBLKIE_Msk                     /*!<Synchronization Block Detected Interrupt Enable    */\n#define SPDIFRX_IMR_SYNCDIE_Pos     (5U)\n#define SPDIFRX_IMR_SYNCDIE_Msk     (0x1UL << SPDIFRX_IMR_SYNCDIE_Pos)         /*!< 0x00000020 */\n#define SPDIFRX_IMR_SYNCDIE         SPDIFRX_IMR_SYNCDIE_Msk                    /*!<Synchronization Done                               */\n#define SPDIFRX_IMR_IFEIE_Pos       (6U)\n#define SPDIFRX_IMR_IFEIE_Msk       (0x1UL << SPDIFRX_IMR_IFEIE_Pos)           /*!< 0x00000040 */\n#define SPDIFRX_IMR_IFEIE           SPDIFRX_IMR_IFEIE_Msk                      /*!<Serial Interface Error Interrupt Enable            */\n\n/*******************  Bit definition for SPDIFRX_SR register  *******************/\n#define SPDIFRX_SR_RXNE_Pos         (0U)\n#define SPDIFRX_SR_RXNE_Msk         (0x1UL << SPDIFRX_SR_RXNE_Pos)             /*!< 0x00000001 */\n#define SPDIFRX_SR_RXNE             SPDIFRX_SR_RXNE_Msk                        /*!<Read data register not empty                          */\n#define SPDIFRX_SR_CSRNE_Pos        (1U)\n#define SPDIFRX_SR_CSRNE_Msk        (0x1UL << SPDIFRX_SR_CSRNE_Pos)            /*!< 0x00000002 */\n#define SPDIFRX_SR_CSRNE            SPDIFRX_SR_CSRNE_Msk                       /*!<The Control Buffer register is not empty              */\n#define SPDIFRX_SR_PERR_Pos         (2U)\n#define SPDIFRX_SR_PERR_Msk         (0x1UL << SPDIFRX_SR_PERR_Pos)             /*!< 0x00000004 */\n#define SPDIFRX_SR_PERR             SPDIFRX_SR_PERR_Msk                        /*!<Parity error                                          */\n#define SPDIFRX_SR_OVR_Pos          (3U)\n#define SPDIFRX_SR_OVR_Msk          (0x1UL << SPDIFRX_SR_OVR_Pos)              /*!< 0x00000008 */\n#define SPDIFRX_SR_OVR              SPDIFRX_SR_OVR_Msk                         /*!<Overrun error                                         */\n#define SPDIFRX_SR_SBD_Pos          (4U)\n#define SPDIFRX_SR_SBD_Msk          (0x1UL << SPDIFRX_SR_SBD_Pos)              /*!< 0x00000010 */\n#define SPDIFRX_SR_SBD              SPDIFRX_SR_SBD_Msk                         /*!<Synchronization Block Detected                        */\n#define SPDIFRX_SR_SYNCD_Pos        (5U)\n#define SPDIFRX_SR_SYNCD_Msk        (0x1UL << SPDIFRX_SR_SYNCD_Pos)            /*!< 0x00000020 */\n#define SPDIFRX_SR_SYNCD            SPDIFRX_SR_SYNCD_Msk                       /*!<Synchronization Done                                  */\n#define SPDIFRX_SR_FERR_Pos         (6U)\n#define SPDIFRX_SR_FERR_Msk         (0x1UL << SPDIFRX_SR_FERR_Pos)             /*!< 0x00000040 */\n#define SPDIFRX_SR_FERR             SPDIFRX_SR_FERR_Msk                        /*!<Framing error                                         */\n#define SPDIFRX_SR_SERR_Pos         (7U)\n#define SPDIFRX_SR_SERR_Msk         (0x1UL << SPDIFRX_SR_SERR_Pos)             /*!< 0x00000080 */\n#define SPDIFRX_SR_SERR             SPDIFRX_SR_SERR_Msk                        /*!<Synchronization error                                 */\n#define SPDIFRX_SR_TERR_Pos         (8U)\n#define SPDIFRX_SR_TERR_Msk         (0x1UL << SPDIFRX_SR_TERR_Pos)             /*!< 0x00000100 */\n#define SPDIFRX_SR_TERR             SPDIFRX_SR_TERR_Msk                        /*!<Time-out error                                        */\n#define SPDIFRX_SR_WIDTH5_Pos       (16U)\n#define SPDIFRX_SR_WIDTH5_Msk       (0x7FFFUL << SPDIFRX_SR_WIDTH5_Pos)        /*!< 0x7FFF0000 */\n#define SPDIFRX_SR_WIDTH5           SPDIFRX_SR_WIDTH5_Msk                      /*!<Duration of 5 symbols counted with spdif_clk          */\n\n/*******************  Bit definition for SPDIFRX_IFCR register  *******************/\n#define SPDIFRX_IFCR_PERRCF_Pos     (2U)\n#define SPDIFRX_IFCR_PERRCF_Msk     (0x1UL << SPDIFRX_IFCR_PERRCF_Pos)         /*!< 0x00000004 */\n#define SPDIFRX_IFCR_PERRCF         SPDIFRX_IFCR_PERRCF_Msk                    /*!<Clears the Parity error flag                         */\n#define SPDIFRX_IFCR_OVRCF_Pos      (3U)\n#define SPDIFRX_IFCR_OVRCF_Msk      (0x1UL << SPDIFRX_IFCR_OVRCF_Pos)          /*!< 0x00000008 */\n#define SPDIFRX_IFCR_OVRCF          SPDIFRX_IFCR_OVRCF_Msk                     /*!<Clears the Overrun error flag                        */\n#define SPDIFRX_IFCR_SBDCF_Pos      (4U)\n#define SPDIFRX_IFCR_SBDCF_Msk      (0x1UL << SPDIFRX_IFCR_SBDCF_Pos)          /*!< 0x00000010 */\n#define SPDIFRX_IFCR_SBDCF          SPDIFRX_IFCR_SBDCF_Msk                     /*!<Clears the Synchronization Block Detected flag       */\n#define SPDIFRX_IFCR_SYNCDCF_Pos    (5U)\n#define SPDIFRX_IFCR_SYNCDCF_Msk    (0x1UL << SPDIFRX_IFCR_SYNCDCF_Pos)        /*!< 0x00000020 */\n#define SPDIFRX_IFCR_SYNCDCF        SPDIFRX_IFCR_SYNCDCF_Msk                   /*!<Clears the Synchronization Done flag                 */\n\n/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b00 case) *******************/\n#define SPDIFRX_DR0_DR_Pos          (0U)\n#define SPDIFRX_DR0_DR_Msk          (0xFFFFFFUL << SPDIFRX_DR0_DR_Pos)         /*!< 0x00FFFFFF */\n#define SPDIFRX_DR0_DR              SPDIFRX_DR0_DR_Msk                         /*!<Data value            */\n#define SPDIFRX_DR0_PE_Pos          (24U)\n#define SPDIFRX_DR0_PE_Msk          (0x1UL << SPDIFRX_DR0_PE_Pos)              /*!< 0x01000000 */\n#define SPDIFRX_DR0_PE              SPDIFRX_DR0_PE_Msk                         /*!<Parity Error bit      */\n#define SPDIFRX_DR0_V_Pos           (25U)\n#define SPDIFRX_DR0_V_Msk           (0x1UL << SPDIFRX_DR0_V_Pos)               /*!< 0x02000000 */\n#define SPDIFRX_DR0_V               SPDIFRX_DR0_V_Msk                          /*!<Validity bit          */\n#define SPDIFRX_DR0_U_Pos           (26U)\n#define SPDIFRX_DR0_U_Msk           (0x1UL << SPDIFRX_DR0_U_Pos)               /*!< 0x04000000 */\n#define SPDIFRX_DR0_U               SPDIFRX_DR0_U_Msk                          /*!<User bit              */\n#define SPDIFRX_DR0_C_Pos           (27U)\n#define SPDIFRX_DR0_C_Msk           (0x1UL << SPDIFRX_DR0_C_Pos)               /*!< 0x08000000 */\n#define SPDIFRX_DR0_C               SPDIFRX_DR0_C_Msk                          /*!<Channel Status bit    */\n#define SPDIFRX_DR0_PT_Pos          (28U)\n#define SPDIFRX_DR0_PT_Msk          (0x3UL << SPDIFRX_DR0_PT_Pos)              /*!< 0x30000000 */\n#define SPDIFRX_DR0_PT              SPDIFRX_DR0_PT_Msk                         /*!<Preamble Type         */\n\n/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b01 case) *******************/\n#define SPDIFRX_DR1_DR_Pos          (8U)\n#define SPDIFRX_DR1_DR_Msk          (0xFFFFFFUL << SPDIFRX_DR1_DR_Pos)         /*!< 0xFFFFFF00 */\n#define SPDIFRX_DR1_DR              SPDIFRX_DR1_DR_Msk                         /*!<Data value            */\n#define SPDIFRX_DR1_PT_Pos          (4U)\n#define SPDIFRX_DR1_PT_Msk          (0x3UL << SPDIFRX_DR1_PT_Pos)              /*!< 0x00000030 */\n#define SPDIFRX_DR1_PT              SPDIFRX_DR1_PT_Msk                         /*!<Preamble Type         */\n#define SPDIFRX_DR1_C_Pos           (3U)\n#define SPDIFRX_DR1_C_Msk           (0x1UL << SPDIFRX_DR1_C_Pos)               /*!< 0x00000008 */\n#define SPDIFRX_DR1_C               SPDIFRX_DR1_C_Msk                          /*!<Channel Status bit    */\n#define SPDIFRX_DR1_U_Pos           (2U)\n#define SPDIFRX_DR1_U_Msk           (0x1UL << SPDIFRX_DR1_U_Pos)               /*!< 0x00000004 */\n#define SPDIFRX_DR1_U               SPDIFRX_DR1_U_Msk                          /*!<User bit              */\n#define SPDIFRX_DR1_V_Pos           (1U)\n#define SPDIFRX_DR1_V_Msk           (0x1UL << SPDIFRX_DR1_V_Pos)               /*!< 0x00000002 */\n#define SPDIFRX_DR1_V               SPDIFRX_DR1_V_Msk                          /*!<Validity bit          */\n#define SPDIFRX_DR1_PE_Pos          (0U)\n#define SPDIFRX_DR1_PE_Msk          (0x1UL << SPDIFRX_DR1_PE_Pos)              /*!< 0x00000001 */\n#define SPDIFRX_DR1_PE              SPDIFRX_DR1_PE_Msk                         /*!<Parity Error bit      */\n\n/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b10 case) *******************/\n#define SPDIFRX_DR1_DRNL1_Pos       (16U)\n#define SPDIFRX_DR1_DRNL1_Msk       (0xFFFFUL << SPDIFRX_DR1_DRNL1_Pos)        /*!< 0xFFFF0000 */\n#define SPDIFRX_DR1_DRNL1           SPDIFRX_DR1_DRNL1_Msk                      /*!<Data value Channel B      */\n#define SPDIFRX_DR1_DRNL2_Pos       (0U)\n#define SPDIFRX_DR1_DRNL2_Msk       (0xFFFFUL << SPDIFRX_DR1_DRNL2_Pos)        /*!< 0x0000FFFF */\n#define SPDIFRX_DR1_DRNL2           SPDIFRX_DR1_DRNL2_Msk                      /*!<Data value Channel A      */\n\n/*******************  Bit definition for SPDIFRX_CSR register   *******************/\n#define SPDIFRX_CSR_USR_Pos         (0U)\n#define SPDIFRX_CSR_USR_Msk         (0xFFFFUL << SPDIFRX_CSR_USR_Pos)          /*!< 0x0000FFFF */\n#define SPDIFRX_CSR_USR             SPDIFRX_CSR_USR_Msk                        /*!<User data information           */\n#define SPDIFRX_CSR_CS_Pos          (16U)\n#define SPDIFRX_CSR_CS_Msk          (0xFFUL << SPDIFRX_CSR_CS_Pos)             /*!< 0x00FF0000 */\n#define SPDIFRX_CSR_CS              SPDIFRX_CSR_CS_Msk                         /*!<Channel A status information    */\n#define SPDIFRX_CSR_SOB_Pos         (24U)\n#define SPDIFRX_CSR_SOB_Msk         (0x1UL << SPDIFRX_CSR_SOB_Pos)             /*!< 0x01000000 */\n#define SPDIFRX_CSR_SOB             SPDIFRX_CSR_SOB_Msk                        /*!<Start Of Block                  */\n\n/*******************  Bit definition for SPDIFRX_DIR register    *******************/\n#define SPDIFRX_DIR_THI_Pos         (0U)\n#define SPDIFRX_DIR_THI_Msk         (0x1FFFUL << SPDIFRX_DIR_THI_Pos)          /*!< 0x00001FFF */\n#define SPDIFRX_DIR_THI             SPDIFRX_DIR_THI_Msk                        /*!<Threshold LOW      */\n#define SPDIFRX_DIR_TLO_Pos         (16U)\n#define SPDIFRX_DIR_TLO_Msk         (0x1FFFUL << SPDIFRX_DIR_TLO_Pos)          /*!< 0x1FFF0000 */\n#define SPDIFRX_DIR_TLO             SPDIFRX_DIR_TLO_Msk                        /*!<Threshold HIGH     */\n\n/*******************  Bit definition for SPDIFRX_VERR register    *******************/\n#define SPDIFRX_VERR_MINREV_Pos     (0U)\n#define SPDIFRX_VERR_MINREV_Msk     (0xFUL << SPDIFRX_VERR_MINREV_Pos)         /*!< 0x0000000F */\n#define SPDIFRX_VERR_MINREV         SPDIFRX_VERR_MINREV_Msk                    /*!<SPDIFRX Minor revision     */\n#define SPDIFRX_VERR_MAJREV_Pos     (4U)\n#define SPDIFRX_VERR_MAJREV_Msk     (0xFUL << SPDIFRX_VERR_MAJREV_Pos)         /*!< 0x000000F0 */\n#define SPDIFRX_VERR_MAJREV         SPDIFRX_VERR_MAJREV_Msk                    /*!<SPDIFRX Major revision     */\n\n/*******************  Bit definition for SPDIFRX_IDR register    *******************/\n#define SPDIFRX_IDR_ID_Pos          (0U)\n#define SPDIFRX_IDR_ID_Msk          (0xFFFFFFFFUL << SPDIFRX_IDR_ID_Pos)       /*!< 0xFFFFFFFF */\n#define SPDIFRX_IDR_ID              SPDIFRX_IDR_ID_Msk                         /*!<SPDIFRX identifier     */\n\n/*******************  Bit definition for SPDIFRX_SIDR register    *******************/\n#define SPDIFRX_SIDR_SID_Pos        (0U)\n#define SPDIFRX_SIDR_SID_Msk        (0xFFFFFFFFUL << SPDIFRX_SIDR_SID_Pos)     /*!< 0xFFFFFFFF */\n#define SPDIFRX_SIDR_SID            SPDIFRX_SIDR_SID_Msk                       /*!<Size of the memory region allocated to SPDIFRX registers */\n\n/******************************************************************************/\n/*                                                                            */\n/*                          Serial Audio Interface                            */\n/*                                                                            */\n/******************************************************************************/\n/*******************************  SAI VERSION  ********************************/\n#define SAI_VER_V2_X\n\n/********************  Bit definition for SAI_GCR register  *******************/\n#define SAI_GCR_SYNCIN_Pos         (0U)\n#define SAI_GCR_SYNCIN_Msk         (0x3UL << SAI_GCR_SYNCIN_Pos)               /*!< 0x00000003 */\n#define SAI_GCR_SYNCIN             SAI_GCR_SYNCIN_Msk                          /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */\n#define SAI_GCR_SYNCIN_0           (0x1UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000001 */\n#define SAI_GCR_SYNCIN_1           (0x2UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000002 */\n\n#define SAI_GCR_SYNCOUT_Pos        (4U)\n#define SAI_GCR_SYNCOUT_Msk        (0x3UL << SAI_GCR_SYNCOUT_Pos)              /*!< 0x00000030 */\n#define SAI_GCR_SYNCOUT            SAI_GCR_SYNCOUT_Msk                         /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */\n#define SAI_GCR_SYNCOUT_0          (0x1UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000010 */\n#define SAI_GCR_SYNCOUT_1          (0x2UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000020 */\n\n/*******************  Bit definition for SAI_xCR1 register  *******************/\n#define SAI_xCR1_MODE_Pos          (0U)\n#define SAI_xCR1_MODE_Msk          (0x3UL << SAI_xCR1_MODE_Pos)                /*!< 0x00000003 */\n#define SAI_xCR1_MODE              SAI_xCR1_MODE_Msk                           /*!<MODE[1:0] bits (Audio Block Mode)           */\n#define SAI_xCR1_MODE_0            (0x1UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000001 */\n#define SAI_xCR1_MODE_1            (0x2UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000002 */\n\n#define SAI_xCR1_PRTCFG_Pos        (2U)\n#define SAI_xCR1_PRTCFG_Msk        (0x3UL << SAI_xCR1_PRTCFG_Pos)              /*!< 0x0000000C */\n#define SAI_xCR1_PRTCFG            SAI_xCR1_PRTCFG_Msk                         /*!<PRTCFG[1:0] bits (Protocol Configuration)   */\n#define SAI_xCR1_PRTCFG_0          (0x1UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000004 */\n#define SAI_xCR1_PRTCFG_1          (0x2UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000008 */\n\n#define SAI_xCR1_DS_Pos            (5U)\n#define SAI_xCR1_DS_Msk            (0x7UL << SAI_xCR1_DS_Pos)                  /*!< 0x000000E0 */\n#define SAI_xCR1_DS                SAI_xCR1_DS_Msk                             /*!<DS[1:0] bits (Data Size) */\n#define SAI_xCR1_DS_0              (0x1UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000020 */\n#define SAI_xCR1_DS_1              (0x2UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000040 */\n#define SAI_xCR1_DS_2              (0x4UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000080 */\n\n#define SAI_xCR1_LSBFIRST_Pos      (8U)\n#define SAI_xCR1_LSBFIRST_Msk      (0x1UL << SAI_xCR1_LSBFIRST_Pos)            /*!< 0x00000100 */\n#define SAI_xCR1_LSBFIRST          SAI_xCR1_LSBFIRST_Msk                       /*!<LSB First Configuration  */\n#define SAI_xCR1_CKSTR_Pos         (9U)\n#define SAI_xCR1_CKSTR_Msk         (0x1UL << SAI_xCR1_CKSTR_Pos)               /*!< 0x00000200 */\n#define SAI_xCR1_CKSTR             SAI_xCR1_CKSTR_Msk                          /*!<ClocK STRobing edge      */\n\n#define SAI_xCR1_SYNCEN_Pos        (10U)\n#define SAI_xCR1_SYNCEN_Msk        (0x3UL << SAI_xCR1_SYNCEN_Pos)              /*!< 0x00000C00 */\n#define SAI_xCR1_SYNCEN            SAI_xCR1_SYNCEN_Msk                         /*!<SYNCEN[1:0](SYNChronization ENable) */\n#define SAI_xCR1_SYNCEN_0          (0x1UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000400 */\n#define SAI_xCR1_SYNCEN_1          (0x2UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000800 */\n\n#define SAI_xCR1_MONO_Pos          (12U)\n#define SAI_xCR1_MONO_Msk          (0x1UL << SAI_xCR1_MONO_Pos)                /*!< 0x00001000 */\n#define SAI_xCR1_MONO              SAI_xCR1_MONO_Msk                           /*!<Mono mode                  */\n#define SAI_xCR1_OUTDRIV_Pos       (13U)\n#define SAI_xCR1_OUTDRIV_Msk       (0x1UL << SAI_xCR1_OUTDRIV_Pos)             /*!< 0x00002000 */\n#define SAI_xCR1_OUTDRIV           SAI_xCR1_OUTDRIV_Msk                        /*!<Output Drive               */\n#define SAI_xCR1_SAIEN_Pos         (16U)\n#define SAI_xCR1_SAIEN_Msk         (0x1UL << SAI_xCR1_SAIEN_Pos)               /*!< 0x00010000 */\n#define SAI_xCR1_SAIEN             SAI_xCR1_SAIEN_Msk                          /*!<Audio Block enable         */\n#define SAI_xCR1_DMAEN_Pos         (17U)\n#define SAI_xCR1_DMAEN_Msk         (0x1UL << SAI_xCR1_DMAEN_Pos)               /*!< 0x00020000 */\n#define SAI_xCR1_DMAEN             SAI_xCR1_DMAEN_Msk                          /*!<DMA enable                 */\n#define SAI_xCR1_NODIV_Pos         (19U)\n#define SAI_xCR1_NODIV_Msk         (0x1UL << SAI_xCR1_NODIV_Pos)               /*!< 0x00080000 */\n#define SAI_xCR1_NODIV             SAI_xCR1_NODIV_Msk                          /*!<No Divider Configuration   */\n\n#define SAI_xCR1_MCKDIV_Pos        (20U)\n#define SAI_xCR1_MCKDIV_Msk        (0x3FUL << SAI_xCR1_MCKDIV_Pos)             /*!< 0x03F00000 */\n#define SAI_xCR1_MCKDIV            SAI_xCR1_MCKDIV_Msk                         /*!<MCKDIV[5:0] (Master ClocK Divider)  */\n#define SAI_xCR1_MCKDIV_0          (0x01UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00100000 */\n#define SAI_xCR1_MCKDIV_1          (0x02UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00200000 */\n#define SAI_xCR1_MCKDIV_2          (0x04UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00400000 */\n#define SAI_xCR1_MCKDIV_3          (0x08UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00800000 */\n#define SAI_xCR1_MCKDIV_4          (0x10UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x01000000 */\n#define SAI_xCR1_MCKDIV_5          (0x20UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x02000000 */\n\n#define SAI_xCR1_MCKEN_Pos         (27U)\n#define SAI_xCR1_MCKEN_Msk         (0x1UL << SAI_xCR1_MCKEN_Pos)               /*!< 0x08000000 */\n#define SAI_xCR1_MCKEN             SAI_xCR1_MCKEN_Msk                          /*!<Master ClocK enable */\n\n#define SAI_xCR1_OSR_Pos           (26U)\n#define SAI_xCR1_OSR_Msk           (0x1UL << SAI_xCR1_OSR_Pos)                 /*!< 0x04000000 */\n#define SAI_xCR1_OSR               SAI_xCR1_OSR_Msk                            /*!<OverSampling Ratio for master clock  */\n\n/* Legacy define */\n#define  SAI_xCR1_NOMCK               SAI_xCR1_NODIV\n\n/*******************  Bit definition for SAI_xCR2 register  *******************/\n#define SAI_xCR2_FTH_Pos           (0U)\n#define SAI_xCR2_FTH_Msk           (0x7UL << SAI_xCR2_FTH_Pos)                 /*!< 0x00000007 */\n#define SAI_xCR2_FTH               SAI_xCR2_FTH_Msk                            /*!<FTH[2:0](Fifo THreshold)  */\n#define SAI_xCR2_FTH_0             (0x1UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000001 */\n#define SAI_xCR2_FTH_1             (0x2UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000002 */\n#define SAI_xCR2_FTH_2             (0x4UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000004 */\n\n#define SAI_xCR2_FFLUSH_Pos        (3U)\n#define SAI_xCR2_FFLUSH_Msk        (0x1UL << SAI_xCR2_FFLUSH_Pos)              /*!< 0x00000008 */\n#define SAI_xCR2_FFLUSH            SAI_xCR2_FFLUSH_Msk                         /*!<Fifo FLUSH                       */\n#define SAI_xCR2_TRIS_Pos          (4U)\n#define SAI_xCR2_TRIS_Msk          (0x1UL << SAI_xCR2_TRIS_Pos)                /*!< 0x00000010 */\n#define SAI_xCR2_TRIS              SAI_xCR2_TRIS_Msk                           /*!<TRIState Management on data line */\n#define SAI_xCR2_MUTE_Pos          (5U)\n#define SAI_xCR2_MUTE_Msk          (0x1UL << SAI_xCR2_MUTE_Pos)                /*!< 0x00000020 */\n#define SAI_xCR2_MUTE              SAI_xCR2_MUTE_Msk                           /*!<Mute mode                        */\n#define SAI_xCR2_MUTEVAL_Pos       (6U)\n#define SAI_xCR2_MUTEVAL_Msk       (0x1UL << SAI_xCR2_MUTEVAL_Pos)             /*!< 0x00000040 */\n#define SAI_xCR2_MUTEVAL           SAI_xCR2_MUTEVAL_Msk                        /*!<Muate value                      */\n\n#define SAI_xCR2_MUTECNT_Pos       (7U)\n#define SAI_xCR2_MUTECNT_Msk       (0x3FUL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00001F80 */\n#define SAI_xCR2_MUTECNT           SAI_xCR2_MUTECNT_Msk                        /*!<MUTECNT[5:0] (MUTE counter) */\n#define SAI_xCR2_MUTECNT_0         (0x01UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000080 */\n#define SAI_xCR2_MUTECNT_1         (0x02UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000100 */\n#define SAI_xCR2_MUTECNT_2         (0x04UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000200 */\n#define SAI_xCR2_MUTECNT_3         (0x08UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000400 */\n#define SAI_xCR2_MUTECNT_4         (0x10UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000800 */\n#define SAI_xCR2_MUTECNT_5         (0x20UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001000 */\n\n#define SAI_xCR2_CPL_Pos           (13U)\n#define SAI_xCR2_CPL_Msk           (0x1UL << SAI_xCR2_CPL_Pos)                 /*!< 0x00002000 */\n#define SAI_xCR2_CPL               SAI_xCR2_CPL_Msk                            /*!< Complement Bit             */\n\n#define SAI_xCR2_COMP_Pos          (14U)\n#define SAI_xCR2_COMP_Msk          (0x3UL << SAI_xCR2_COMP_Pos)                /*!< 0x0000C000 */\n#define SAI_xCR2_COMP              SAI_xCR2_COMP_Msk                           /*!<COMP[1:0] (Companding mode) */\n#define SAI_xCR2_COMP_0            (0x1UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00004000 */\n#define SAI_xCR2_COMP_1            (0x2UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00008000 */\n\n/******************  Bit definition for SAI_xFRCR register  *******************/\n#define SAI_xFRCR_FRL_Pos          (0U)\n#define SAI_xFRCR_FRL_Msk          (0xFFUL << SAI_xFRCR_FRL_Pos)               /*!< 0x000000FF */\n#define SAI_xFRCR_FRL              SAI_xFRCR_FRL_Msk                           /*!<FRL[7:0](FRame Length)  */\n#define SAI_xFRCR_FRL_0            (0x01UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000001 */\n#define SAI_xFRCR_FRL_1            (0x02UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000002 */\n#define SAI_xFRCR_FRL_2            (0x04UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000004 */\n#define SAI_xFRCR_FRL_3            (0x08UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000008 */\n#define SAI_xFRCR_FRL_4            (0x10UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000010 */\n#define SAI_xFRCR_FRL_5            (0x20UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000020 */\n#define SAI_xFRCR_FRL_6            (0x40UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000040 */\n#define SAI_xFRCR_FRL_7            (0x80UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000080 */\n\n#define SAI_xFRCR_FSALL_Pos        (8U)\n#define SAI_xFRCR_FSALL_Msk        (0x7FUL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00007F00 */\n#define SAI_xFRCR_FSALL            SAI_xFRCR_FSALL_Msk                         /*!<FSALL[6:0] (Frame Synchronization Active Level Length)  */\n#define SAI_xFRCR_FSALL_0          (0x01UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000100 */\n#define SAI_xFRCR_FSALL_1          (0x02UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000200 */\n#define SAI_xFRCR_FSALL_2          (0x04UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000400 */\n#define SAI_xFRCR_FSALL_3          (0x08UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000800 */\n#define SAI_xFRCR_FSALL_4          (0x10UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00001000 */\n#define SAI_xFRCR_FSALL_5          (0x20UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00002000 */\n#define SAI_xFRCR_FSALL_6          (0x40UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00004000 */\n\n#define SAI_xFRCR_FSDEF_Pos        (16U)\n#define SAI_xFRCR_FSDEF_Msk        (0x1UL << SAI_xFRCR_FSDEF_Pos)              /*!< 0x00010000 */\n#define SAI_xFRCR_FSDEF            SAI_xFRCR_FSDEF_Msk                         /*!<Frame Synchronization Definition  */\n#define SAI_xFRCR_FSPOL_Pos        (17U)\n#define SAI_xFRCR_FSPOL_Msk        (0x1UL << SAI_xFRCR_FSPOL_Pos)              /*!< 0x00020000 */\n#define SAI_xFRCR_FSPOL            SAI_xFRCR_FSPOL_Msk                         /*!<Frame Synchronization POLarity    */\n#define SAI_xFRCR_FSOFF_Pos        (18U)\n#define SAI_xFRCR_FSOFF_Msk        (0x1UL << SAI_xFRCR_FSOFF_Pos)              /*!< 0x00040000 */\n#define SAI_xFRCR_FSOFF            SAI_xFRCR_FSOFF_Msk                         /*!<Frame Synchronization OFFset      */\n\n/* Legacy define */\n#define  SAI_xFRCR_FSPO                      SAI_xFRCR_FSPOL\n\n/******************  Bit definition for SAI_xSLOTR register  *******************/\n#define SAI_xSLOTR_FBOFF_Pos       (0U)\n#define SAI_xSLOTR_FBOFF_Msk       (0x1FUL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x0000001F */\n#define SAI_xSLOTR_FBOFF           SAI_xSLOTR_FBOFF_Msk                        /*!<FBOFF[4:0](First Bit Offset)  */\n#define SAI_xSLOTR_FBOFF_0         (0x01UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000001 */\n#define SAI_xSLOTR_FBOFF_1         (0x02UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000002 */\n#define SAI_xSLOTR_FBOFF_2         (0x04UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000004 */\n#define SAI_xSLOTR_FBOFF_3         (0x08UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000008 */\n#define SAI_xSLOTR_FBOFF_4         (0x10UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000010 */\n\n#define SAI_xSLOTR_SLOTSZ_Pos      (6U)\n#define SAI_xSLOTR_SLOTSZ_Msk      (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)            /*!< 0x000000C0 */\n#define SAI_xSLOTR_SLOTSZ          SAI_xSLOTR_SLOTSZ_Msk                       /*!<SLOTSZ[1:0] (Slot size)  */\n#define SAI_xSLOTR_SLOTSZ_0        (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000040 */\n#define SAI_xSLOTR_SLOTSZ_1        (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000080 */\n\n#define SAI_xSLOTR_NBSLOT_Pos      (8U)\n#define SAI_xSLOTR_NBSLOT_Msk      (0xFUL << SAI_xSLOTR_NBSLOT_Pos)            /*!< 0x00000F00 */\n#define SAI_xSLOTR_NBSLOT          SAI_xSLOTR_NBSLOT_Msk                       /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */\n#define SAI_xSLOTR_NBSLOT_0        (0x1UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000100 */\n#define SAI_xSLOTR_NBSLOT_1        (0x2UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000200 */\n#define SAI_xSLOTR_NBSLOT_2        (0x4UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000400 */\n#define SAI_xSLOTR_NBSLOT_3        (0x8UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000800 */\n\n#define SAI_xSLOTR_SLOTEN_Pos      (16U)\n#define SAI_xSLOTR_SLOTEN_Msk      (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)         /*!< 0xFFFF0000 */\n#define SAI_xSLOTR_SLOTEN          SAI_xSLOTR_SLOTEN_Msk                       /*!<SLOTEN[15:0] (Slot Enable)  */\n\n/*******************  Bit definition for SAI_xIMR register  *******************/\n#define SAI_xIMR_OVRUDRIE_Pos      (0U)\n#define SAI_xIMR_OVRUDRIE_Msk      (0x1UL << SAI_xIMR_OVRUDRIE_Pos)            /*!< 0x00000001 */\n#define SAI_xIMR_OVRUDRIE          SAI_xIMR_OVRUDRIE_Msk                       /*!<Overrun underrun interrupt enable                              */\n#define SAI_xIMR_MUTEDETIE_Pos     (1U)\n#define SAI_xIMR_MUTEDETIE_Msk     (0x1UL << SAI_xIMR_MUTEDETIE_Pos)           /*!< 0x00000002 */\n#define SAI_xIMR_MUTEDETIE         SAI_xIMR_MUTEDETIE_Msk                      /*!<Mute detection interrupt enable                                */\n#define SAI_xIMR_WCKCFGIE_Pos      (2U)\n#define SAI_xIMR_WCKCFGIE_Msk      (0x1UL << SAI_xIMR_WCKCFGIE_Pos)            /*!< 0x00000004 */\n#define SAI_xIMR_WCKCFGIE          SAI_xIMR_WCKCFGIE_Msk                       /*!<Wrong Clock Configuration interrupt enable                     */\n#define SAI_xIMR_FREQIE_Pos        (3U)\n#define SAI_xIMR_FREQIE_Msk        (0x1UL << SAI_xIMR_FREQIE_Pos)              /*!< 0x00000008 */\n#define SAI_xIMR_FREQIE            SAI_xIMR_FREQIE_Msk                         /*!<FIFO request interrupt enable                                  */\n#define SAI_xIMR_CNRDYIE_Pos       (4U)\n#define SAI_xIMR_CNRDYIE_Msk       (0x1UL << SAI_xIMR_CNRDYIE_Pos)             /*!< 0x00000010 */\n#define SAI_xIMR_CNRDYIE           SAI_xIMR_CNRDYIE_Msk                        /*!<Codec not ready interrupt enable                               */\n#define SAI_xIMR_AFSDETIE_Pos      (5U)\n#define SAI_xIMR_AFSDETIE_Msk      (0x1UL << SAI_xIMR_AFSDETIE_Pos)            /*!< 0x00000020 */\n#define SAI_xIMR_AFSDETIE          SAI_xIMR_AFSDETIE_Msk                       /*!<Anticipated frame synchronization detection interrupt enable   */\n#define SAI_xIMR_LFSDETIE_Pos      (6U)\n#define SAI_xIMR_LFSDETIE_Msk      (0x1UL << SAI_xIMR_LFSDETIE_Pos)            /*!< 0x00000040 */\n#define SAI_xIMR_LFSDETIE          SAI_xIMR_LFSDETIE_Msk                       /*!<Late frame synchronization detection interrupt enable          */\n\n/********************  Bit definition for SAI_xSR register  *******************/\n#define SAI_xSR_OVRUDR_Pos         (0U)\n#define SAI_xSR_OVRUDR_Msk         (0x1UL << SAI_xSR_OVRUDR_Pos)               /*!< 0x00000001 */\n#define SAI_xSR_OVRUDR             SAI_xSR_OVRUDR_Msk                          /*!<Overrun underrun                               */\n#define SAI_xSR_MUTEDET_Pos        (1U)\n#define SAI_xSR_MUTEDET_Msk        (0x1UL << SAI_xSR_MUTEDET_Pos)              /*!< 0x00000002 */\n#define SAI_xSR_MUTEDET            SAI_xSR_MUTEDET_Msk                         /*!<Mute detection                                 */\n#define SAI_xSR_WCKCFG_Pos         (2U)\n#define SAI_xSR_WCKCFG_Msk         (0x1UL << SAI_xSR_WCKCFG_Pos)               /*!< 0x00000004 */\n#define SAI_xSR_WCKCFG             SAI_xSR_WCKCFG_Msk                          /*!<Wrong Clock Configuration                      */\n#define SAI_xSR_FREQ_Pos           (3U)\n#define SAI_xSR_FREQ_Msk           (0x1UL << SAI_xSR_FREQ_Pos)                 /*!< 0x00000008 */\n#define SAI_xSR_FREQ               SAI_xSR_FREQ_Msk                            /*!<FIFO request                                   */\n#define SAI_xSR_CNRDY_Pos          (4U)\n#define SAI_xSR_CNRDY_Msk          (0x1UL << SAI_xSR_CNRDY_Pos)                /*!< 0x00000010 */\n#define SAI_xSR_CNRDY              SAI_xSR_CNRDY_Msk                           /*!<Codec not ready                                */\n#define SAI_xSR_AFSDET_Pos         (5U)\n#define SAI_xSR_AFSDET_Msk         (0x1UL << SAI_xSR_AFSDET_Pos)               /*!< 0x00000020 */\n#define SAI_xSR_AFSDET             SAI_xSR_AFSDET_Msk                          /*!<Anticipated frame synchronization detection    */\n#define SAI_xSR_LFSDET_Pos         (6U)\n#define SAI_xSR_LFSDET_Msk         (0x1UL << SAI_xSR_LFSDET_Pos)               /*!< 0x00000040 */\n#define SAI_xSR_LFSDET             SAI_xSR_LFSDET_Msk                          /*!<Late frame synchronization detection           */\n\n#define SAI_xSR_FLVL_Pos           (16U)\n#define SAI_xSR_FLVL_Msk           (0x7UL << SAI_xSR_FLVL_Pos)                 /*!< 0x00070000 */\n#define SAI_xSR_FLVL               SAI_xSR_FLVL_Msk                            /*!<FLVL[2:0] (FIFO Level Threshold)               */\n#define SAI_xSR_FLVL_0             (0x1UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00010000 */\n#define SAI_xSR_FLVL_1             (0x2UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00020000 */\n#define SAI_xSR_FLVL_2             (0x4UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00040000 */\n\n/******************  Bit definition for SAI_xCLRFR register  ******************/\n#define SAI_xCLRFR_COVRUDR_Pos     (0U)\n#define SAI_xCLRFR_COVRUDR_Msk     (0x1UL << SAI_xCLRFR_COVRUDR_Pos)           /*!< 0x00000001 */\n#define SAI_xCLRFR_COVRUDR         SAI_xCLRFR_COVRUDR_Msk                      /*!<Clear Overrun underrun                               */\n#define SAI_xCLRFR_CMUTEDET_Pos    (1U)\n#define SAI_xCLRFR_CMUTEDET_Msk    (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)          /*!< 0x00000002 */\n#define SAI_xCLRFR_CMUTEDET        SAI_xCLRFR_CMUTEDET_Msk                     /*!<Clear Mute detection                                 */\n#define SAI_xCLRFR_CWCKCFG_Pos     (2U)\n#define SAI_xCLRFR_CWCKCFG_Msk     (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)           /*!< 0x00000004 */\n#define SAI_xCLRFR_CWCKCFG         SAI_xCLRFR_CWCKCFG_Msk                      /*!<Clear Wrong Clock Configuration                      */\n#define SAI_xCLRFR_CFREQ_Pos       (3U)\n#define SAI_xCLRFR_CFREQ_Msk       (0x1UL << SAI_xCLRFR_CFREQ_Pos)             /*!< 0x00000008 */\n#define SAI_xCLRFR_CFREQ           SAI_xCLRFR_CFREQ_Msk                        /*!<Clear FIFO request                                   */\n#define SAI_xCLRFR_CCNRDY_Pos      (4U)\n#define SAI_xCLRFR_CCNRDY_Msk      (0x1UL << SAI_xCLRFR_CCNRDY_Pos)            /*!< 0x00000010 */\n#define SAI_xCLRFR_CCNRDY          SAI_xCLRFR_CCNRDY_Msk                       /*!<Clear Codec not ready                                */\n#define SAI_xCLRFR_CAFSDET_Pos     (5U)\n#define SAI_xCLRFR_CAFSDET_Msk     (0x1UL << SAI_xCLRFR_CAFSDET_Pos)           /*!< 0x00000020 */\n#define SAI_xCLRFR_CAFSDET         SAI_xCLRFR_CAFSDET_Msk                      /*!<Clear Anticipated frame synchronization detection    */\n#define SAI_xCLRFR_CLFSDET_Pos     (6U)\n#define SAI_xCLRFR_CLFSDET_Msk     (0x1UL << SAI_xCLRFR_CLFSDET_Pos)           /*!< 0x00000040 */\n#define SAI_xCLRFR_CLFSDET         SAI_xCLRFR_CLFSDET_Msk                      /*!<Clear Late frame synchronization detection           */\n\n/******************  Bit definition for SAI_xDR register  *********************/\n#define SAI_xDR_DATA_Pos           (0U)\n#define SAI_xDR_DATA_Msk           (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)          /*!< 0xFFFFFFFF */\n#define SAI_xDR_DATA               SAI_xDR_DATA_Msk\n\n/*******************  Bit definition for SAI_PDMCR register  ******************/\n#define SAI_PDMCR_PDMEN_Pos        (0U)\n#define SAI_PDMCR_PDMEN_Msk        (0x1UL << SAI_PDMCR_PDMEN_Pos)              /*!< 0x00000001 */\n#define SAI_PDMCR_PDMEN            SAI_PDMCR_PDMEN_Msk                         /*!<PDM Enable                                          */\n\n#define SAI_PDMCR_MICNBR_Pos       (4U)\n#define SAI_PDMCR_MICNBR_Msk       (0x3UL << SAI_PDMCR_MICNBR_Pos)             /*!< 0x00000030 */\n#define SAI_PDMCR_MICNBR           SAI_PDMCR_MICNBR_Msk                        /*!<Number of microphones                               */\n#define SAI_PDMCR_MICNBR_0         (0x1UL << SAI_PDMCR_MICNBR_Pos)              /*!< 0x00000010 */\n#define SAI_PDMCR_MICNBR_1         (0x2UL << SAI_PDMCR_MICNBR_Pos)              /*!< 0x00000020 */\n\n#define SAI_PDMCR_CKEN1_Pos        (8U)\n#define SAI_PDMCR_CKEN1_Msk        (0x1UL << SAI_PDMCR_CKEN1_Pos)              /*!< 0x00000100 */\n#define SAI_PDMCR_CKEN1            SAI_PDMCR_CKEN1_Msk                         /*!<Clock enable of bitstream clock number 1            */\n#define SAI_PDMCR_CKEN2_Pos        (9U)\n#define SAI_PDMCR_CKEN2_Msk        (0x1UL << SAI_PDMCR_CKEN2_Pos)              /*!< 0x00000200 */\n#define SAI_PDMCR_CKEN2            SAI_PDMCR_CKEN2_Msk                         /*!<Clock enable of bitstream clock number 2            */\n#define SAI_PDMCR_CKEN3_Pos        (10U)\n#define SAI_PDMCR_CKEN3_Msk        (0x1UL << SAI_PDMCR_CKEN3_Pos)              /*!< 0x00000400 */\n#define SAI_PDMCR_CKEN3            SAI_PDMCR_CKEN3_Msk                         /*!<Clock enable of bitstream clock number 3            */\n#define SAI_PDMCR_CKEN4_Pos        (11U)\n#define SAI_PDMCR_CKEN4_Msk        (0x1UL << SAI_PDMCR_CKEN4_Pos)              /*!< 0x00000800 */\n#define SAI_PDMCR_CKEN4            SAI_PDMCR_CKEN4_Msk                         /*!<Clock enable of bitstream clock number 4            */\n\n/******************  Bit definition for SAI_PDMDLY register  ******************/\n#define SAI_PDMDLY_DLYM1L_Pos      (0U)\n#define SAI_PDMDLY_DLYM1L_Msk      (0x7UL << SAI_PDMDLY_DLYM1L_Pos)            /*!< 0x00000007 */\n#define SAI_PDMDLY_DLYM1L          SAI_PDMDLY_DLYM1L_Msk                       /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */\n#define SAI_PDMDLY_DLYM1L_0        (0x1UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000001 */\n#define SAI_PDMDLY_DLYM1L_1        (0x2UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000002 */\n#define SAI_PDMDLY_DLYM1L_2        (0x4UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000004 */\n\n#define SAI_PDMDLY_DLYM1R_Pos      (4U)\n#define SAI_PDMDLY_DLYM1R_Msk      (0x7UL << SAI_PDMDLY_DLYM1R_Pos)            /*!< 0x00000070 */\n#define SAI_PDMDLY_DLYM1R          SAI_PDMDLY_DLYM1R_Msk                       /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */\n#define SAI_PDMDLY_DLYM1R_0        (0x1UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000010 */\n#define SAI_PDMDLY_DLYM1R_1        (0x2UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000020 */\n#define SAI_PDMDLY_DLYM1R_2        (0x4UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000040 */\n\n#define SAI_PDMDLY_DLYM2L_Pos      (8U)\n#define SAI_PDMDLY_DLYM2L_Msk      (0x7UL << SAI_PDMDLY_DLYM2L_Pos)            /*!< 0x00000700 */\n#define SAI_PDMDLY_DLYM2L          SAI_PDMDLY_DLYM2L_Msk                       /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */\n#define SAI_PDMDLY_DLYM2L_0        (0x1UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000100 */\n#define SAI_PDMDLY_DLYM2L_1        (0x2UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000200 */\n#define SAI_PDMDLY_DLYM2L_2        (0x4UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000400 */\n\n#define SAI_PDMDLY_DLYM2R_Pos      (12U)\n#define SAI_PDMDLY_DLYM2R_Msk      (0x7UL << SAI_PDMDLY_DLYM2R_Pos)            /*!< 0x00007000 */\n#define SAI_PDMDLY_DLYM2R          SAI_PDMDLY_DLYM2R_Msk                       /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2)*/\n#define SAI_PDMDLY_DLYM2R_0        (0x1UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00001000 */\n#define SAI_PDMDLY_DLYM2R_1        (0x2UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00002000 */\n#define SAI_PDMDLY_DLYM2R_2        (0x4UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00004000 */\n\n#define SAI_PDMDLY_DLYM3L_Pos      (16U)\n#define SAI_PDMDLY_DLYM3L_Msk      (0x7UL << SAI_PDMDLY_DLYM3L_Pos)            /*!< 0x00070000 */\n#define SAI_PDMDLY_DLYM3L          SAI_PDMDLY_DLYM3L_Msk                       /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3)*/\n#define SAI_PDMDLY_DLYM3L_0        (0x1UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00010000 */\n#define SAI_PDMDLY_DLYM3L_1        (0x2UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00020000 */\n#define SAI_PDMDLY_DLYM3L_2        (0x4UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00040000 */\n\n#define SAI_PDMDLY_DLYM3R_Pos      (20U)\n#define SAI_PDMDLY_DLYM3R_Msk      (0x7UL << SAI_PDMDLY_DLYM3R_Pos)            /*!< 0x00700000 */\n#define SAI_PDMDLY_DLYM3R          SAI_PDMDLY_DLYM3R_Msk                       /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3)*/\n#define SAI_PDMDLY_DLYM3R_0        (0x1UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00100000 */\n#define SAI_PDMDLY_DLYM3R_1        (0x2UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00200000 */\n#define SAI_PDMDLY_DLYM3R_2        (0x4UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00400000 */\n\n#define SAI_PDMDLY_DLYM4L_Pos      (24U)\n#define SAI_PDMDLY_DLYM4L_Msk      (0x7UL << SAI_PDMDLY_DLYM4L_Pos)            /*!< 0x07000000 */\n#define SAI_PDMDLY_DLYM4L          SAI_PDMDLY_DLYM4L_Msk                       /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4)*/\n#define SAI_PDMDLY_DLYM4L_0        (0x1UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x01000000 */\n#define SAI_PDMDLY_DLYM4L_1        (0x2UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x02000000 */\n#define SAI_PDMDLY_DLYM4L_2        (0x4UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x04000000 */\n\n#define SAI_PDMDLY_DLYM4R_Pos      (28U)\n#define SAI_PDMDLY_DLYM4R_Msk      (0x7UL << SAI_PDMDLY_DLYM4R_Pos)            /*!< 0x70000000 */\n#define SAI_PDMDLY_DLYM4R          SAI_PDMDLY_DLYM4R_Msk                       /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4)*/\n#define SAI_PDMDLY_DLYM4R_0        (0x1UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x10000000 */\n#define SAI_PDMDLY_DLYM4R_1        (0x2UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x20000000 */\n#define SAI_PDMDLY_DLYM4R_2        (0x4UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x40000000 */\n\n/******************************************************************************/\n/*                                                                            */\n/*                           SDMMC Interface                                  */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bit definition for SDMMC_POWER register  ******************/\n#define SDMMC_POWER_PWRCTRL_Pos          (0U)\n#define SDMMC_POWER_PWRCTRL_Msk          (0x3UL << SDMMC_POWER_PWRCTRL_Pos)    /*!< 0x00000003 */\n#define SDMMC_POWER_PWRCTRL              SDMMC_POWER_PWRCTRL_Msk               /*!<PWRCTRL[1:0] bits (Power supply control bits) */\n#define SDMMC_POWER_PWRCTRL_0            (0x1UL << SDMMC_POWER_PWRCTRL_Pos)     /*!< 0x00000001 */\n#define SDMMC_POWER_PWRCTRL_1            (0x2UL << SDMMC_POWER_PWRCTRL_Pos)     /*!< 0x00000002 */\n#define SDMMC_POWER_VSWITCH_Pos          (2U)\n#define SDMMC_POWER_VSWITCH_Msk          (0x1UL << SDMMC_POWER_VSWITCH_Pos)    /*!< 0x00000004 */\n#define SDMMC_POWER_VSWITCH              SDMMC_POWER_VSWITCH_Msk               /*!<Voltage switch sequence start */\n#define SDMMC_POWER_VSWITCHEN_Pos        (3U)\n#define SDMMC_POWER_VSWITCHEN_Msk        (0x1UL << SDMMC_POWER_VSWITCHEN_Pos)  /*!< 0x00000008 */\n#define SDMMC_POWER_VSWITCHEN            SDMMC_POWER_VSWITCHEN_Msk             /*!<Voltage switch procedure enable */\n#define SDMMC_POWER_DIRPOL_Pos           (4U)\n#define SDMMC_POWER_DIRPOL_Msk           (0x1UL << SDMMC_POWER_DIRPOL_Pos)     /*!< 0x00000010 */\n#define SDMMC_POWER_DIRPOL               SDMMC_POWER_DIRPOL_Msk                /*!<Data and Command direction signals polarity selection */\n\n/******************  Bit definition for SDMMC_CLKCR register  ******************/\n#define SDMMC_CLKCR_CLKDIV_Pos           (0U)\n#define SDMMC_CLKCR_CLKDIV_Msk           (0x3FFUL << SDMMC_CLKCR_CLKDIV_Pos)   /*!< 0x000003FF */\n#define SDMMC_CLKCR_CLKDIV               SDMMC_CLKCR_CLKDIV_Msk                /*!<Clock divide factor             */\n#define SDMMC_CLKCR_PWRSAV_Pos           (12U)\n#define SDMMC_CLKCR_PWRSAV_Msk           (0x1UL << SDMMC_CLKCR_PWRSAV_Pos)     /*!< 0x00001000 */\n#define SDMMC_CLKCR_PWRSAV               SDMMC_CLKCR_PWRSAV_Msk                /*!<Power saving configuration bit  */\n\n#define SDMMC_CLKCR_WIDBUS_Pos           (14U)\n#define SDMMC_CLKCR_WIDBUS_Msk           (0x3UL << SDMMC_CLKCR_WIDBUS_Pos)     /*!< 0x0000C000 */\n#define SDMMC_CLKCR_WIDBUS               SDMMC_CLKCR_WIDBUS_Msk                /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */\n#define SDMMC_CLKCR_WIDBUS_0             (0x1UL << SDMMC_CLKCR_WIDBUS_Pos)      /*!< 0x00004000 */\n#define SDMMC_CLKCR_WIDBUS_1             (0x2UL << SDMMC_CLKCR_WIDBUS_Pos)      /*!< 0x00008000 */\n\n#define SDMMC_CLKCR_NEGEDGE_Pos          (16U)\n#define SDMMC_CLKCR_NEGEDGE_Msk          (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos)    /*!< 0x00010000 */\n#define SDMMC_CLKCR_NEGEDGE              SDMMC_CLKCR_NEGEDGE_Msk               /*!<SDMMC_CK dephasing selection bit */\n#define SDMMC_CLKCR_HWFC_EN_Pos          (17U)\n#define SDMMC_CLKCR_HWFC_EN_Msk          (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos)    /*!< 0x00020000 */\n#define SDMMC_CLKCR_HWFC_EN              SDMMC_CLKCR_HWFC_EN_Msk               /*!<HW Flow Control enable           */\n#define SDMMC_CLKCR_DDR_Pos              (18U)\n#define SDMMC_CLKCR_DDR_Msk              (0x1UL << SDMMC_CLKCR_DDR_Pos)        /*!< 0x00040000 */\n#define SDMMC_CLKCR_DDR                  SDMMC_CLKCR_DDR_Msk                   /*!<Data rate signaling selection    */\n#define SDMMC_CLKCR_BUSSPEED_Pos         (19U)\n#define SDMMC_CLKCR_BUSSPEED_Msk         (0x1UL << SDMMC_CLKCR_BUSSPEED_Pos)   /*!< 0x00080000 */\n#define SDMMC_CLKCR_BUSSPEED             SDMMC_CLKCR_BUSSPEED_Msk              /*!<Bus speed mode selection         */\n#define SDMMC_CLKCR_SELCLKRX_Pos         (20U)\n#define SDMMC_CLKCR_SELCLKRX_Msk         (0x3UL << SDMMC_CLKCR_SELCLKRX_Pos)   /*!< 0x00300000 */\n#define SDMMC_CLKCR_SELCLKRX             SDMMC_CLKCR_SELCLKRX_Msk              /*!<SELCLKRX[1:0] bits (Receive clock selection) */\n#define SDMMC_CLKCR_SELCLKRX_0           (0x1UL << SDMMC_CLKCR_SELCLKRX_Pos)    /*!< 0x00100000 */\n#define SDMMC_CLKCR_SELCLKRX_1           (0x2UL << SDMMC_CLKCR_SELCLKRX_Pos)    /*!< 0x00200000 */\n\n/*******************  Bit definition for SDMMC_ARG register  *******************/\n#define SDMMC_ARG_CMDARG_Pos             (0U)\n#define SDMMC_ARG_CMDARG_Msk             (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */\n#define SDMMC_ARG_CMDARG                 SDMMC_ARG_CMDARG_Msk                  /*!<Command argument */\n\n/*******************  Bit definition for SDMMC_CMD register  *******************/\n#define SDMMC_CMD_CMDINDEX_Pos           (0U)\n#define SDMMC_CMD_CMDINDEX_Msk           (0x3FUL << SDMMC_CMD_CMDINDEX_Pos)    /*!< 0x0000003F */\n#define SDMMC_CMD_CMDINDEX               SDMMC_CMD_CMDINDEX_Msk                /*!<Command Index                               */\n#define SDMMC_CMD_CMDTRANS_Pos           (6U)\n#define SDMMC_CMD_CMDTRANS_Msk           (0x1UL << SDMMC_CMD_CMDTRANS_Pos)     /*!< 0x00000040 */\n#define SDMMC_CMD_CMDTRANS               SDMMC_CMD_CMDTRANS_Msk                /*!<CPSM Treats command as a Data Transfer      */\n#define SDMMC_CMD_CMDSTOP_Pos            (7U)\n#define SDMMC_CMD_CMDSTOP_Msk            (0x1UL << SDMMC_CMD_CMDSTOP_Pos)      /*!< 0x00000080 */\n#define SDMMC_CMD_CMDSTOP                SDMMC_CMD_CMDSTOP_Msk                 /*!<CPSM Treats command as a Stop               */\n\n#define SDMMC_CMD_WAITRESP_Pos           (8U)\n#define SDMMC_CMD_WAITRESP_Msk           (0x3UL << SDMMC_CMD_WAITRESP_Pos)     /*!< 0x00000300 */\n#define SDMMC_CMD_WAITRESP               SDMMC_CMD_WAITRESP_Msk                /*!<WAITRESP[1:0] bits (Wait for response bits) */\n#define SDMMC_CMD_WAITRESP_0             (0x1UL << SDMMC_CMD_WAITRESP_Pos)      /*!< 0x00000100 */\n#define SDMMC_CMD_WAITRESP_1             (0x2UL << SDMMC_CMD_WAITRESP_Pos)      /*!< 0x00000200 */\n\n#define SDMMC_CMD_WAITINT_Pos            (10U)\n#define SDMMC_CMD_WAITINT_Msk            (0x1UL << SDMMC_CMD_WAITINT_Pos)      /*!< 0x00000400 */\n#define SDMMC_CMD_WAITINT                SDMMC_CMD_WAITINT_Msk                 /*!<CPSM Waits for Interrupt Request                               */\n#define SDMMC_CMD_WAITPEND_Pos           (11U)\n#define SDMMC_CMD_WAITPEND_Msk           (0x1UL << SDMMC_CMD_WAITPEND_Pos)     /*!< 0x00000800 */\n#define SDMMC_CMD_WAITPEND               SDMMC_CMD_WAITPEND_Msk                /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */\n#define SDMMC_CMD_CPSMEN_Pos             (12U)\n#define SDMMC_CMD_CPSMEN_Msk             (0x1UL << SDMMC_CMD_CPSMEN_Pos)       /*!< 0x00001000 */\n#define SDMMC_CMD_CPSMEN                 SDMMC_CMD_CPSMEN_Msk                  /*!<Command path state machine (CPSM) Enable bit                   */\n#define SDMMC_CMD_DTHOLD_Pos             (13U)\n#define SDMMC_CMD_DTHOLD_Msk             (0x1UL << SDMMC_CMD_DTHOLD_Pos)       /*!< 0x00002000 */\n#define SDMMC_CMD_DTHOLD                 SDMMC_CMD_DTHOLD_Msk                  /*!<Hold new data block transmission and reception in the DPSM     */\n#define SDMMC_CMD_BOOTMODE_Pos           (14U)\n#define SDMMC_CMD_BOOTMODE_Msk           (0x1UL << SDMMC_CMD_BOOTMODE_Pos)     /*!< 0x00004000 */\n#define SDMMC_CMD_BOOTMODE               SDMMC_CMD_BOOTMODE_Msk                /*!<Boot mode                                                      */\n#define SDMMC_CMD_BOOTEN_Pos             (15U)\n#define SDMMC_CMD_BOOTEN_Msk             (0x1UL << SDMMC_CMD_BOOTEN_Pos)       /*!< 0x00008000 */\n#define SDMMC_CMD_BOOTEN                 SDMMC_CMD_BOOTEN_Msk                  /*!<Enable Boot mode procedure                                     */\n#define SDMMC_CMD_CMDSUSPEND_Pos         (16U)\n#define SDMMC_CMD_CMDSUSPEND_Msk         (0x1UL << SDMMC_CMD_CMDSUSPEND_Pos)   /*!< 0x00010000 */\n#define SDMMC_CMD_CMDSUSPEND             SDMMC_CMD_CMDSUSPEND_Msk              /*!<CPSM Treats command as a Suspend or Resume command             */\n\n/*****************  Bit definition for SDMMC_RESPCMD register  *****************/\n#define SDMMC_RESPCMD_RESPCMD_Pos        (0U)\n#define SDMMC_RESPCMD_RESPCMD_Msk        (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */\n#define SDMMC_RESPCMD_RESPCMD            SDMMC_RESPCMD_RESPCMD_Msk             /*!<Response command index */\n\n/******************  Bit definition for SDMMC_RESP0 register  ******************/\n#define SDMMC_RESP0_CARDSTATUS0_Pos      (0U)\n#define SDMMC_RESP0_CARDSTATUS0_Msk      (0xFFFFFFFFUL << SDMMC_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */\n#define SDMMC_RESP0_CARDSTATUS0          SDMMC_RESP0_CARDSTATUS0_Msk           /*!<Card Status */\n\n/******************  Bit definition for SDMMC_RESP1 register  ******************/\n#define SDMMC_RESP1_CARDSTATUS1_Pos      (0U)\n#define SDMMC_RESP1_CARDSTATUS1_Msk      (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */\n#define SDMMC_RESP1_CARDSTATUS1          SDMMC_RESP1_CARDSTATUS1_Msk           /*!<Card Status */\n\n/******************  Bit definition for SDMMC_RESP2 register  ******************/\n#define SDMMC_RESP2_CARDSTATUS2_Pos      (0U)\n#define SDMMC_RESP2_CARDSTATUS2_Msk      (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */\n#define SDMMC_RESP2_CARDSTATUS2          SDMMC_RESP2_CARDSTATUS2_Msk           /*!<Card Status */\n\n/******************  Bit definition for SDMMC_RESP3 register  ******************/\n#define SDMMC_RESP3_CARDSTATUS3_Pos      (0U)\n#define SDMMC_RESP3_CARDSTATUS3_Msk      (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */\n#define SDMMC_RESP3_CARDSTATUS3          SDMMC_RESP3_CARDSTATUS3_Msk           /*!<Card Status */\n\n/******************  Bit definition for SDMMC_RESP4 register  ******************/\n#define SDMMC_RESP4_CARDSTATUS4_Pos      (0U)\n#define SDMMC_RESP4_CARDSTATUS4_Msk      (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */\n#define SDMMC_RESP4_CARDSTATUS4          SDMMC_RESP4_CARDSTATUS4_Msk           /*!<Card Status */\n\n/******************  Bit definition for SDMMC_DTIMER register  *****************/\n#define SDMMC_DTIMER_DATATIME_Pos        (0U)\n#define SDMMC_DTIMER_DATATIME_Msk        (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */\n#define SDMMC_DTIMER_DATATIME            SDMMC_DTIMER_DATATIME_Msk             /*!<Data timeout period. */\n\n/******************  Bit definition for SDMMC_DLEN register  *******************/\n#define SDMMC_DLEN_DATALENGTH_Pos        (0U)\n#define SDMMC_DLEN_DATALENGTH_Msk        (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */\n#define SDMMC_DLEN_DATALENGTH            SDMMC_DLEN_DATALENGTH_Msk             /*!<Data length value    */\n\n/******************  Bit definition for SDMMC_DCTRL register  ******************/\n#define SDMMC_DCTRL_DTEN_Pos             (0U)\n#define SDMMC_DCTRL_DTEN_Msk             (0x1UL << SDMMC_DCTRL_DTEN_Pos)       /*!< 0x00000001 */\n#define SDMMC_DCTRL_DTEN                 SDMMC_DCTRL_DTEN_Msk                  /*!<Data transfer enabled bit                */\n#define SDMMC_DCTRL_DTDIR_Pos            (1U)\n#define SDMMC_DCTRL_DTDIR_Msk            (0x1UL << SDMMC_DCTRL_DTDIR_Pos)      /*!< 0x00000002 */\n#define SDMMC_DCTRL_DTDIR                SDMMC_DCTRL_DTDIR_Msk                 /*!<Data transfer direction selection        */\n#define SDMMC_DCTRL_DTMODE_Pos           (2U)\n#define SDMMC_DCTRL_DTMODE_Msk           (0x3UL << SDMMC_DCTRL_DTMODE_Pos)     /*!< 0x0000000C */\n#define SDMMC_DCTRL_DTMODE               SDMMC_DCTRL_DTMODE_Msk                /*!<DTMODE[1:0] Data transfer mode selection */\n#define SDMMC_DCTRL_DTMODE_0             (0x1UL << SDMMC_DCTRL_DTMODE_Pos)      /*!< 0x00000004 */\n#define SDMMC_DCTRL_DTMODE_1             (0x2UL << SDMMC_DCTRL_DTMODE_Pos)      /*!< 0x00000008 */\n\n#define SDMMC_DCTRL_DBLOCKSIZE_Pos       (4U)\n#define SDMMC_DCTRL_DBLOCKSIZE_Msk       (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */\n#define SDMMC_DCTRL_DBLOCKSIZE           SDMMC_DCTRL_DBLOCKSIZE_Msk            /*!<DBLOCKSIZE[3:0] bits (Data block size) */\n#define SDMMC_DCTRL_DBLOCKSIZE_0         (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000010 */\n#define SDMMC_DCTRL_DBLOCKSIZE_1         (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000020 */\n#define SDMMC_DCTRL_DBLOCKSIZE_2         (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000040 */\n#define SDMMC_DCTRL_DBLOCKSIZE_3         (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000080 */\n\n#define SDMMC_DCTRL_RWSTART_Pos          (8U)\n#define SDMMC_DCTRL_RWSTART_Msk          (0x1UL << SDMMC_DCTRL_RWSTART_Pos)    /*!< 0x00000100 */\n#define SDMMC_DCTRL_RWSTART              SDMMC_DCTRL_RWSTART_Msk               /*!<Read wait start                                 */\n#define SDMMC_DCTRL_RWSTOP_Pos           (9U)\n#define SDMMC_DCTRL_RWSTOP_Msk           (0x1UL << SDMMC_DCTRL_RWSTOP_Pos)     /*!< 0x00000200 */\n#define SDMMC_DCTRL_RWSTOP               SDMMC_DCTRL_RWSTOP_Msk                /*!<Read wait stop                                  */\n#define SDMMC_DCTRL_RWMOD_Pos            (10U)\n#define SDMMC_DCTRL_RWMOD_Msk            (0x1UL << SDMMC_DCTRL_RWMOD_Pos)      /*!< 0x00000400 */\n#define SDMMC_DCTRL_RWMOD                SDMMC_DCTRL_RWMOD_Msk                 /*!<Read wait mode                                  */\n#define SDMMC_DCTRL_SDIOEN_Pos           (11U)\n#define SDMMC_DCTRL_SDIOEN_Msk           (0x1UL << SDMMC_DCTRL_SDIOEN_Pos)     /*!< 0x00000800 */\n#define SDMMC_DCTRL_SDIOEN               SDMMC_DCTRL_SDIOEN_Msk                /*!<SD I/O enable functions                         */\n#define SDMMC_DCTRL_BOOTACKEN_Pos        (12U)\n#define SDMMC_DCTRL_BOOTACKEN_Msk        (0x1UL << SDMMC_DCTRL_BOOTACKEN_Pos)  /*!< 0x00001000 */\n#define SDMMC_DCTRL_BOOTACKEN            SDMMC_DCTRL_BOOTACKEN_Msk             /*!<Enable the reception of the Boot Acknowledgment */\n#define SDMMC_DCTRL_FIFORST_Pos          (13U)\n#define SDMMC_DCTRL_FIFORST_Msk          (0x1UL << SDMMC_DCTRL_FIFORST_Pos)    /*!< 0x00002000 */\n#define SDMMC_DCTRL_FIFORST              SDMMC_DCTRL_FIFORST_Msk               /*!<FIFO reset                                      */\n\n/******************  Bit definition for SDMMC_DCOUNT register  *****************/\n#define SDMMC_DCOUNT_DATACOUNT_Pos       (0U)\n#define SDMMC_DCOUNT_DATACOUNT_Msk       (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */\n#define SDMMC_DCOUNT_DATACOUNT           SDMMC_DCOUNT_DATACOUNT_Msk            /*!<Data count value */\n\n/******************  Bit definition for SDMMC_STA register  ********************/\n#define SDMMC_STA_CCRCFAIL_Pos           (0U)\n#define SDMMC_STA_CCRCFAIL_Msk           (0x1UL << SDMMC_STA_CCRCFAIL_Pos)     /*!< 0x00000001 */\n#define SDMMC_STA_CCRCFAIL               SDMMC_STA_CCRCFAIL_Msk                /*!<Command response received (CRC check failed)  */\n#define SDMMC_STA_DCRCFAIL_Pos           (1U)\n#define SDMMC_STA_DCRCFAIL_Msk           (0x1UL << SDMMC_STA_DCRCFAIL_Pos)     /*!< 0x00000002 */\n#define SDMMC_STA_DCRCFAIL               SDMMC_STA_DCRCFAIL_Msk                /*!<Data block sent/received (CRC check failed)   */\n#define SDMMC_STA_CTIMEOUT_Pos           (2U)\n#define SDMMC_STA_CTIMEOUT_Msk           (0x1UL << SDMMC_STA_CTIMEOUT_Pos)     /*!< 0x00000004 */\n#define SDMMC_STA_CTIMEOUT               SDMMC_STA_CTIMEOUT_Msk                /*!<Command response timeout                      */\n#define SDMMC_STA_DTIMEOUT_Pos           (3U)\n#define SDMMC_STA_DTIMEOUT_Msk           (0x1UL << SDMMC_STA_DTIMEOUT_Pos)     /*!< 0x00000008 */\n#define SDMMC_STA_DTIMEOUT               SDMMC_STA_DTIMEOUT_Msk                /*!<Data timeout                                  */\n#define SDMMC_STA_TXUNDERR_Pos           (4U)\n#define SDMMC_STA_TXUNDERR_Msk           (0x1UL << SDMMC_STA_TXUNDERR_Pos)     /*!< 0x00000010 */\n#define SDMMC_STA_TXUNDERR               SDMMC_STA_TXUNDERR_Msk                /*!<Transmit FIFO underrun error                  */\n#define SDMMC_STA_RXOVERR_Pos            (5U)\n#define SDMMC_STA_RXOVERR_Msk            (0x1UL << SDMMC_STA_RXOVERR_Pos)      /*!< 0x00000020 */\n#define SDMMC_STA_RXOVERR                SDMMC_STA_RXOVERR_Msk                 /*!<Received FIFO overrun error                   */\n#define SDMMC_STA_CMDREND_Pos            (6U)\n#define SDMMC_STA_CMDREND_Msk            (0x1UL << SDMMC_STA_CMDREND_Pos)      /*!< 0x00000040 */\n#define SDMMC_STA_CMDREND                SDMMC_STA_CMDREND_Msk                 /*!<Command response received (CRC check passed)  */\n#define SDMMC_STA_CMDSENT_Pos            (7U)\n#define SDMMC_STA_CMDSENT_Msk            (0x1UL << SDMMC_STA_CMDSENT_Pos)      /*!< 0x00000080 */\n#define SDMMC_STA_CMDSENT                SDMMC_STA_CMDSENT_Msk                 /*!<Command sent (no response required)           */\n#define SDMMC_STA_DATAEND_Pos            (8U)\n#define SDMMC_STA_DATAEND_Msk            (0x1UL << SDMMC_STA_DATAEND_Pos)      /*!< 0x00000100 */\n#define SDMMC_STA_DATAEND                SDMMC_STA_DATAEND_Msk                 /*!<Data end (data counter, SDIDCOUNT, is zero)   */\n#define SDMMC_STA_DHOLD_Pos              (9U)\n#define SDMMC_STA_DHOLD_Msk              (0x1UL << SDMMC_STA_DHOLD_Pos)        /*!< 0x00000200 */\n#define SDMMC_STA_DHOLD                  SDMMC_STA_DHOLD_Msk                   /*!<Data transfer Hold                                                      */\n#define SDMMC_STA_DBCKEND_Pos            (10U)\n#define SDMMC_STA_DBCKEND_Msk            (0x1UL << SDMMC_STA_DBCKEND_Pos)      /*!< 0x00000400 */\n#define SDMMC_STA_DBCKEND                SDMMC_STA_DBCKEND_Msk                 /*!<Data block sent/received (CRC check passed)   */\n#define SDMMC_STA_DABORT_Pos             (11U)\n#define SDMMC_STA_DABORT_Msk             (0x1UL << SDMMC_STA_DABORT_Pos)       /*!< 0x00000800 */\n#define SDMMC_STA_DABORT                 SDMMC_STA_DABORT_Msk                  /*!<Data transfer aborted by CMD12                                          */\n#define SDMMC_STA_DPSMACT_Pos            (12U)\n#define SDMMC_STA_DPSMACT_Msk            (0x1UL << SDMMC_STA_DPSMACT_Pos)      /*!< 0x00001000 */\n#define SDMMC_STA_DPSMACT                SDMMC_STA_DPSMACT_Msk                 /*!<Data path state machine active                                       */\n#define SDMMC_STA_CPSMACT_Pos            (13U)\n#define SDMMC_STA_CPSMACT_Msk            (0x1UL << SDMMC_STA_CPSMACT_Pos)      /*!< 0x00002000 */\n#define SDMMC_STA_CPSMACT                SDMMC_STA_CPSMACT_Msk                 /*!<Command path state machine active                                          */\n#define SDMMC_STA_TXFIFOHE_Pos           (14U)\n#define SDMMC_STA_TXFIFOHE_Msk           (0x1UL << SDMMC_STA_TXFIFOHE_Pos)     /*!< 0x00004000 */\n#define SDMMC_STA_TXFIFOHE               SDMMC_STA_TXFIFOHE_Msk                /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */\n#define SDMMC_STA_RXFIFOHF_Pos           (15U)\n#define SDMMC_STA_RXFIFOHF_Msk           (0x1UL << SDMMC_STA_RXFIFOHF_Pos)     /*!< 0x00008000 */\n#define SDMMC_STA_RXFIFOHF               SDMMC_STA_RXFIFOHF_Msk                /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */\n#define SDMMC_STA_TXFIFOF_Pos            (16U)\n#define SDMMC_STA_TXFIFOF_Msk            (0x1UL << SDMMC_STA_TXFIFOF_Pos)      /*!< 0x00010000 */\n#define SDMMC_STA_TXFIFOF                SDMMC_STA_TXFIFOF_Msk                 /*!<Transmit FIFO full                            */\n#define SDMMC_STA_RXFIFOF_Pos            (17U)\n#define SDMMC_STA_RXFIFOF_Msk            (0x1UL << SDMMC_STA_RXFIFOF_Pos)      /*!< 0x00020000 */\n#define SDMMC_STA_RXFIFOF                SDMMC_STA_RXFIFOF_Msk                 /*!<Receive FIFO full                             */\n#define SDMMC_STA_TXFIFOE_Pos            (18U)\n#define SDMMC_STA_TXFIFOE_Msk            (0x1UL << SDMMC_STA_TXFIFOE_Pos)      /*!< 0x00040000 */\n#define SDMMC_STA_TXFIFOE                SDMMC_STA_TXFIFOE_Msk                 /*!<Transmit FIFO empty                           */\n#define SDMMC_STA_RXFIFOE_Pos            (19U)\n#define SDMMC_STA_RXFIFOE_Msk            (0x1UL << SDMMC_STA_RXFIFOE_Pos)      /*!< 0x00080000 */\n#define SDMMC_STA_RXFIFOE                SDMMC_STA_RXFIFOE_Msk                 /*!<Receive FIFO empty                            */\n#define SDMMC_STA_BUSYD0_Pos             (20U)\n#define SDMMC_STA_BUSYD0_Msk             (0x1UL << SDMMC_STA_BUSYD0_Pos)       /*!< 0x00100000 */\n#define SDMMC_STA_BUSYD0                 SDMMC_STA_BUSYD0_Msk                  /*!<Inverted value of SDMMC_D0 line (Busy)                                  */\n#define SDMMC_STA_BUSYD0END_Pos          (21U)\n#define SDMMC_STA_BUSYD0END_Msk          (0x1UL << SDMMC_STA_BUSYD0END_Pos)    /*!< 0x00200000 */\n#define SDMMC_STA_BUSYD0END              SDMMC_STA_BUSYD0END_Msk               /*!<End of SDMMC_D0 Busy following a CMD response detected                  */\n#define SDMMC_STA_SDIOIT_Pos             (22U)\n#define SDMMC_STA_SDIOIT_Msk             (0x1UL << SDMMC_STA_SDIOIT_Pos)       /*!< 0x00400000 */\n#define SDMMC_STA_SDIOIT                 SDMMC_STA_SDIOIT_Msk                  /*!<SDIO interrupt received                                                 */\n#define SDMMC_STA_ACKFAIL_Pos            (23U)\n#define SDMMC_STA_ACKFAIL_Msk            (0x1UL << SDMMC_STA_ACKFAIL_Pos)      /*!< 0x00800000 */\n#define SDMMC_STA_ACKFAIL                SDMMC_STA_ACKFAIL_Msk                 /*!<Boot Acknowledgment received (BootAck check fail)                       */\n#define SDMMC_STA_ACKTIMEOUT_Pos         (24U)\n#define SDMMC_STA_ACKTIMEOUT_Msk         (0x1UL << SDMMC_STA_ACKTIMEOUT_Pos)   /*!< 0x01000000 */\n#define SDMMC_STA_ACKTIMEOUT             SDMMC_STA_ACKTIMEOUT_Msk              /*!<Boot Acknowledgment timeout                                             */\n#define SDMMC_STA_VSWEND_Pos             (25U)\n#define SDMMC_STA_VSWEND_Msk             (0x1UL << SDMMC_STA_VSWEND_Pos)       /*!< 0x02000000 */\n#define SDMMC_STA_VSWEND                 SDMMC_STA_VSWEND_Msk                  /*!<Voltage switch critical timing section completion                       */\n#define SDMMC_STA_CKSTOP_Pos             (26U)\n#define SDMMC_STA_CKSTOP_Msk             (0x1UL << SDMMC_STA_CKSTOP_Pos)       /*!< 0x04000000 */\n#define SDMMC_STA_CKSTOP                 SDMMC_STA_CKSTOP_Msk                  /*!<SDMMC_CK stopped in Voltage switch procedure                            */\n#define SDMMC_STA_IDMATE_Pos             (27U)\n#define SDMMC_STA_IDMATE_Msk             (0x1UL << SDMMC_STA_IDMATE_Pos)       /*!< 0x08000000 */\n#define SDMMC_STA_IDMATE                 SDMMC_STA_IDMATE_Msk                  /*!<IDMA transfer error                                                     */\n#define SDMMC_STA_IDMABTC_Pos            (28U)\n#define SDMMC_STA_IDMABTC_Msk            (0x1UL << SDMMC_STA_IDMABTC_Pos)      /*!< 0x10000000 */\n#define SDMMC_STA_IDMABTC                SDMMC_STA_IDMABTC_Msk                 /*!<IDMA buffer transfer complete                                           */\n\n/*******************  Bit definition for SDMMC_ICR register  *******************/\n#define SDMMC_ICR_CCRCFAILC_Pos          (0U)\n#define SDMMC_ICR_CCRCFAILC_Msk          (0x1UL << SDMMC_ICR_CCRCFAILC_Pos)    /*!< 0x00000001 */\n#define SDMMC_ICR_CCRCFAILC              SDMMC_ICR_CCRCFAILC_Msk               /*!<CCRCFAIL flag clear bit */\n#define SDMMC_ICR_DCRCFAILC_Pos          (1U)\n#define SDMMC_ICR_DCRCFAILC_Msk          (0x1UL << SDMMC_ICR_DCRCFAILC_Pos)    /*!< 0x00000002 */\n#define SDMMC_ICR_DCRCFAILC              SDMMC_ICR_DCRCFAILC_Msk               /*!<DCRCFAIL flag clear bit */\n#define SDMMC_ICR_CTIMEOUTC_Pos          (2U)\n#define SDMMC_ICR_CTIMEOUTC_Msk          (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos)    /*!< 0x00000004 */\n#define SDMMC_ICR_CTIMEOUTC              SDMMC_ICR_CTIMEOUTC_Msk               /*!<CTIMEOUT flag clear bit */\n#define SDMMC_ICR_DTIMEOUTC_Pos          (3U)\n#define SDMMC_ICR_DTIMEOUTC_Msk          (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos)    /*!< 0x00000008 */\n#define SDMMC_ICR_DTIMEOUTC              SDMMC_ICR_DTIMEOUTC_Msk               /*!<DTIMEOUT flag clear bit */\n#define SDMMC_ICR_TXUNDERRC_Pos          (4U)\n#define SDMMC_ICR_TXUNDERRC_Msk          (0x1UL << SDMMC_ICR_TXUNDERRC_Pos)    /*!< 0x00000010 */\n#define SDMMC_ICR_TXUNDERRC              SDMMC_ICR_TXUNDERRC_Msk               /*!<TXUNDERR flag clear bit */\n#define SDMMC_ICR_RXOVERRC_Pos           (5U)\n#define SDMMC_ICR_RXOVERRC_Msk           (0x1UL << SDMMC_ICR_RXOVERRC_Pos)     /*!< 0x00000020 */\n#define SDMMC_ICR_RXOVERRC               SDMMC_ICR_RXOVERRC_Msk                /*!<RXOVERR flag clear bit  */\n#define SDMMC_ICR_CMDRENDC_Pos           (6U)\n#define SDMMC_ICR_CMDRENDC_Msk           (0x1UL << SDMMC_ICR_CMDRENDC_Pos)     /*!< 0x00000040 */\n#define SDMMC_ICR_CMDRENDC               SDMMC_ICR_CMDRENDC_Msk                /*!<CMDREND flag clear bit  */\n#define SDMMC_ICR_CMDSENTC_Pos           (7U)\n#define SDMMC_ICR_CMDSENTC_Msk           (0x1UL << SDMMC_ICR_CMDSENTC_Pos)     /*!< 0x00000080 */\n#define SDMMC_ICR_CMDSENTC               SDMMC_ICR_CMDSENTC_Msk                /*!<CMDSENT flag clear bit  */\n#define SDMMC_ICR_DATAENDC_Pos           (8U)\n#define SDMMC_ICR_DATAENDC_Msk           (0x1UL << SDMMC_ICR_DATAENDC_Pos)     /*!< 0x00000100 */\n#define SDMMC_ICR_DATAENDC               SDMMC_ICR_DATAENDC_Msk                /*!<DATAEND flag clear bit  */\n#define SDMMC_ICR_DHOLDC_Pos             (9U)\n#define SDMMC_ICR_DHOLDC_Msk             (0x1UL << SDMMC_ICR_DHOLDC_Pos)       /*!< 0x00000200 */\n#define SDMMC_ICR_DHOLDC                 SDMMC_ICR_DHOLDC_Msk                  /*!<DHOLD flag clear bit       */\n#define SDMMC_ICR_DBCKENDC_Pos           (10U)\n#define SDMMC_ICR_DBCKENDC_Msk           (0x1UL << SDMMC_ICR_DBCKENDC_Pos)     /*!< 0x00000400 */\n#define SDMMC_ICR_DBCKENDC               SDMMC_ICR_DBCKENDC_Msk                /*!<DBCKEND flag clear bit  */\n#define SDMMC_ICR_DABORTC_Pos            (11U)\n#define SDMMC_ICR_DABORTC_Msk            (0x1UL << SDMMC_ICR_DABORTC_Pos)      /*!< 0x00000800 */\n#define SDMMC_ICR_DABORTC                SDMMC_ICR_DABORTC_Msk                 /*!<DABORTC flag clear bit     */\n#define SDMMC_ICR_BUSYD0ENDC_Pos         (21U)\n#define SDMMC_ICR_BUSYD0ENDC_Msk         (0x1UL << SDMMC_ICR_BUSYD0ENDC_Pos)   /*!< 0x00200000 */\n#define SDMMC_ICR_BUSYD0ENDC             SDMMC_ICR_BUSYD0ENDC_Msk              /*!<BUSYD0ENDC flag clear bit  */\n#define SDMMC_ICR_SDIOITC_Pos            (22U)\n#define SDMMC_ICR_SDIOITC_Msk            (0x1UL << SDMMC_ICR_SDIOITC_Pos)      /*!< 0x00400000 */\n#define SDMMC_ICR_SDIOITC                SDMMC_ICR_SDIOITC_Msk                 /*!<SDIOIT flag clear bit      */\n#define SDMMC_ICR_ACKFAILC_Pos           (23U)\n#define SDMMC_ICR_ACKFAILC_Msk           (0x1UL << SDMMC_ICR_ACKFAILC_Pos)     /*!< 0x00800000 */\n#define SDMMC_ICR_ACKFAILC               SDMMC_ICR_ACKFAILC_Msk                /*!<ACKFAILC flag clear bit    */\n#define SDMMC_ICR_ACKTIMEOUTC_Pos        (24U)\n#define SDMMC_ICR_ACKTIMEOUTC_Msk        (0x1UL << SDMMC_ICR_ACKTIMEOUTC_Pos)  /*!< 0x01000000 */\n#define SDMMC_ICR_ACKTIMEOUTC            SDMMC_ICR_ACKTIMEOUTC_Msk             /*!<ACKTIMEOUTC flag clear bit */\n#define SDMMC_ICR_VSWENDC_Pos            (25U)\n#define SDMMC_ICR_VSWENDC_Msk            (0x1UL << SDMMC_ICR_VSWENDC_Pos)      /*!< 0x02000000 */\n#define SDMMC_ICR_VSWENDC                SDMMC_ICR_VSWENDC_Msk                 /*!<VSWENDC flag clear bit     */\n#define SDMMC_ICR_CKSTOPC_Pos            (26U)\n#define SDMMC_ICR_CKSTOPC_Msk            (0x1UL << SDMMC_ICR_CKSTOPC_Pos)      /*!< 0x04000000 */\n#define SDMMC_ICR_CKSTOPC                SDMMC_ICR_CKSTOPC_Msk                 /*!<CKSTOPC flag clear bit     */\n#define SDMMC_ICR_IDMATEC_Pos            (27U)\n#define SDMMC_ICR_IDMATEC_Msk            (0x1UL << SDMMC_ICR_IDMATEC_Pos)      /*!< 0x08000000 */\n#define SDMMC_ICR_IDMATEC                SDMMC_ICR_IDMATEC_Msk                 /*!<IDMATEC flag clear bit     */\n#define SDMMC_ICR_IDMABTCC_Pos           (28U)\n#define SDMMC_ICR_IDMABTCC_Msk           (0x1UL << SDMMC_ICR_IDMABTCC_Pos)     /*!< 0x10000000 */\n#define SDMMC_ICR_IDMABTCC               SDMMC_ICR_IDMABTCC_Msk                /*!<IDMABTCC flag clear bit    */\n\n/******************  Bit definition for SDMMC_MASK register  *******************/\n#define SDMMC_MASK_CCRCFAILIE_Pos        (0U)\n#define SDMMC_MASK_CCRCFAILIE_Msk        (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos)  /*!< 0x00000001 */\n#define SDMMC_MASK_CCRCFAILIE            SDMMC_MASK_CCRCFAILIE_Msk             /*!<Command CRC Fail Interrupt Enable          */\n#define SDMMC_MASK_DCRCFAILIE_Pos        (1U)\n#define SDMMC_MASK_DCRCFAILIE_Msk        (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos)  /*!< 0x00000002 */\n#define SDMMC_MASK_DCRCFAILIE            SDMMC_MASK_DCRCFAILIE_Msk             /*!<Data CRC Fail Interrupt Enable             */\n#define SDMMC_MASK_CTIMEOUTIE_Pos        (2U)\n#define SDMMC_MASK_CTIMEOUTIE_Msk        (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos)  /*!< 0x00000004 */\n#define SDMMC_MASK_CTIMEOUTIE            SDMMC_MASK_CTIMEOUTIE_Msk             /*!<Command TimeOut Interrupt Enable           */\n#define SDMMC_MASK_DTIMEOUTIE_Pos        (3U)\n#define SDMMC_MASK_DTIMEOUTIE_Msk        (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos)  /*!< 0x00000008 */\n#define SDMMC_MASK_DTIMEOUTIE            SDMMC_MASK_DTIMEOUTIE_Msk             /*!<Data TimeOut Interrupt Enable              */\n#define SDMMC_MASK_TXUNDERRIE_Pos        (4U)\n#define SDMMC_MASK_TXUNDERRIE_Msk        (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos)  /*!< 0x00000010 */\n#define SDMMC_MASK_TXUNDERRIE            SDMMC_MASK_TXUNDERRIE_Msk             /*!<Tx FIFO UnderRun Error Interrupt Enable    */\n#define SDMMC_MASK_RXOVERRIE_Pos         (5U)\n#define SDMMC_MASK_RXOVERRIE_Msk         (0x1UL << SDMMC_MASK_RXOVERRIE_Pos)   /*!< 0x00000020 */\n#define SDMMC_MASK_RXOVERRIE             SDMMC_MASK_RXOVERRIE_Msk              /*!<Rx FIFO OverRun Error Interrupt Enable     */\n#define SDMMC_MASK_CMDRENDIE_Pos         (6U)\n#define SDMMC_MASK_CMDRENDIE_Msk         (0x1UL << SDMMC_MASK_CMDRENDIE_Pos)   /*!< 0x00000040 */\n#define SDMMC_MASK_CMDRENDIE             SDMMC_MASK_CMDRENDIE_Msk              /*!<Command Response Received Interrupt Enable */\n#define SDMMC_MASK_CMDSENTIE_Pos         (7U)\n#define SDMMC_MASK_CMDSENTIE_Msk         (0x1UL << SDMMC_MASK_CMDSENTIE_Pos)   /*!< 0x00000080 */\n#define SDMMC_MASK_CMDSENTIE             SDMMC_MASK_CMDSENTIE_Msk              /*!<Command Sent Interrupt Enable              */\n#define SDMMC_MASK_DATAENDIE_Pos         (8U)\n#define SDMMC_MASK_DATAENDIE_Msk         (0x1UL << SDMMC_MASK_DATAENDIE_Pos)   /*!< 0x00000100 */\n#define SDMMC_MASK_DATAENDIE             SDMMC_MASK_DATAENDIE_Msk              /*!<Data End Interrupt Enable                  */\n#define SDMMC_MASK_DHOLDIE_Pos           (9U)\n#define SDMMC_MASK_DHOLDIE_Msk           (0x1UL << SDMMC_MASK_DHOLDIE_Pos)     /*!< 0x00000200 */\n#define SDMMC_MASK_DHOLDIE               SDMMC_MASK_DHOLDIE_Msk                /*!<Data Hold Interrupt Enable                 */\n#define SDMMC_MASK_DBCKENDIE_Pos         (10U)\n#define SDMMC_MASK_DBCKENDIE_Msk         (0x1UL << SDMMC_MASK_DBCKENDIE_Pos)   /*!< 0x00000400 */\n#define SDMMC_MASK_DBCKENDIE             SDMMC_MASK_DBCKENDIE_Msk              /*!<Data Block End Interrupt Enable            */\n#define SDMMC_MASK_DABORTIE_Pos          (11U)\n#define SDMMC_MASK_DABORTIE_Msk          (0x1UL << SDMMC_MASK_DABORTIE_Pos)    /*!< 0x00000800 */\n#define SDMMC_MASK_DABORTIE              SDMMC_MASK_DABORTIE_Msk               /*!<Data transfer aborted interrupt enable     */\n\n#define SDMMC_MASK_TXFIFOHEIE_Pos        (14U)\n#define SDMMC_MASK_TXFIFOHEIE_Msk        (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos)  /*!< 0x00004000 */\n#define SDMMC_MASK_TXFIFOHEIE            SDMMC_MASK_TXFIFOHEIE_Msk             /*!<Tx FIFO Half Empty interrupt Enable        */\n#define SDMMC_MASK_RXFIFOHFIE_Pos        (15U)\n#define SDMMC_MASK_RXFIFOHFIE_Msk        (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos)  /*!< 0x00008000 */\n#define SDMMC_MASK_RXFIFOHFIE            SDMMC_MASK_RXFIFOHFIE_Msk             /*!<Rx FIFO Half Full interrupt Enable         */\n\n#define SDMMC_MASK_RXFIFOFIE_Pos         (17U)\n#define SDMMC_MASK_RXFIFOFIE_Msk         (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos)   /*!< 0x00020000 */\n#define SDMMC_MASK_RXFIFOFIE             SDMMC_MASK_RXFIFOFIE_Msk              /*!<Rx FIFO Full interrupt Enable              */\n#define SDMMC_MASK_TXFIFOEIE_Pos         (18U)\n#define SDMMC_MASK_TXFIFOEIE_Msk         (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos)   /*!< 0x00040000 */\n#define SDMMC_MASK_TXFIFOEIE             SDMMC_MASK_TXFIFOEIE_Msk              /*!<Tx FIFO Empty interrupt Enable             */\n\n#define SDMMC_MASK_BUSYD0ENDIE_Pos       (21U)\n#define SDMMC_MASK_BUSYD0ENDIE_Msk       (0x1UL << SDMMC_MASK_BUSYD0ENDIE_Pos) /*!< 0x00200000 */\n#define SDMMC_MASK_BUSYD0ENDIE           SDMMC_MASK_BUSYD0ENDIE_Msk            /*!<BUSYD0ENDIE interrupt Enable */\n#define SDMMC_MASK_SDIOITIE_Pos           (22U)\n#define SDMMC_MASK_SDIOITIE_Msk           (0x1UL << SDMMC_MASK_SDIOITIE_Pos)     /*!< 0x00400000 */\n#define SDMMC_MASK_SDIOITIE               SDMMC_MASK_SDIOITIE_Msk                /*!<SDMMC Mode Interrupt Received interrupt Enable */\n#define SDMMC_MASK_ACKFAILIE_Pos         (23U)\n#define SDMMC_MASK_ACKFAILIE_Msk         (0x1UL << SDMMC_MASK_ACKFAILIE_Pos)   /*!< 0x00800000 */\n#define SDMMC_MASK_ACKFAILIE             SDMMC_MASK_ACKFAILIE_Msk              /*!<Acknowledgment Fail Interrupt Enable */\n#define SDMMC_MASK_ACKTIMEOUTIE_Pos      (24U)\n#define SDMMC_MASK_ACKTIMEOUTIE_Msk      (0x1UL << SDMMC_MASK_ACKTIMEOUTIE_Pos) /*!< 0x01000000 */\n#define SDMMC_MASK_ACKTIMEOUTIE          SDMMC_MASK_ACKTIMEOUTIE_Msk           /*!<Acknowledgment timeout Interrupt Enable */\n#define SDMMC_MASK_VSWENDIE_Pos          (25U)\n#define SDMMC_MASK_VSWENDIE_Msk          (0x1UL << SDMMC_MASK_VSWENDIE_Pos)    /*!< 0x02000000 */\n#define SDMMC_MASK_VSWENDIE              SDMMC_MASK_VSWENDIE_Msk               /*!<Voltage switch critical timing section completion Interrupt Enable */\n#define SDMMC_MASK_CKSTOPIE_Pos          (26U)\n#define SDMMC_MASK_CKSTOPIE_Msk          (0x1UL << SDMMC_MASK_CKSTOPIE_Pos)    /*!< 0x04000000 */\n#define SDMMC_MASK_CKSTOPIE              SDMMC_MASK_CKSTOPIE_Msk               /*!<Voltage Switch clock stopped Interrupt Enable */\n#define SDMMC_MASK_IDMABTCIE_Pos         (28U)\n#define SDMMC_MASK_IDMABTCIE_Msk         (0x1UL << SDMMC_MASK_IDMABTCIE_Pos)   /*!< 0x10000000 */\n#define SDMMC_MASK_IDMABTCIE             SDMMC_MASK_IDMABTCIE_Msk              /*!<IDMA buffer transfer complete Interrupt Enable */\n\n/*****************  Bit definition for SDMMC_ACKTIME register  *****************/\n#define SDMMC_ACKTIME_ACKTIME_Pos        (0U)\n#define SDMMC_ACKTIME_ACKTIME_Msk        (0x1FFFFFFUL << SDMMC_ACKTIME_ACKTIME_Pos) /*!< 0x01FFFFFF */\n#define SDMMC_ACKTIME_ACKTIME            SDMMC_ACKTIME_ACKTIME_Msk             /*!<Boot acknowledgment timeout period */\n\n/******************  Bit definition for SDMMC_FIFO register  *******************/\n#define SDMMC_FIFO_FIFODATA_Pos          (0U)\n#define SDMMC_FIFO_FIFODATA_Msk          (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */\n#define SDMMC_FIFO_FIFODATA              SDMMC_FIFO_FIFODATA_Msk               /*!<Receive and transmit FIFO data */\n\n/******************  Bit definition for SDMMC_IDMACTRL register ****************/\n#define SDMMC_IDMA_IDMAEN_Pos            (0U)\n#define SDMMC_IDMA_IDMAEN_Msk            (0x1UL << SDMMC_IDMA_IDMAEN_Pos)      /*!< 0x00000001 */\n#define SDMMC_IDMA_IDMAEN                SDMMC_IDMA_IDMAEN_Msk                 /*!< Enable the internal DMA of the SDMMC peripheral */\n#define SDMMC_IDMA_IDMABMODE_Pos         (1U)\n#define SDMMC_IDMA_IDMABMODE_Msk         (0x1UL << SDMMC_IDMA_IDMABMODE_Pos)   /*!< 0x00000002 */\n#define SDMMC_IDMA_IDMABMODE             SDMMC_IDMA_IDMABMODE_Msk              /*!< Enable double buffer mode for IDMA */\n#define SDMMC_IDMA_IDMABACT_Pos          (2U)\n#define SDMMC_IDMA_IDMABACT_Msk          (0x1UL << SDMMC_IDMA_IDMABACT_Pos)    /*!< 0x00000004 */\n#define SDMMC_IDMA_IDMABACT              SDMMC_IDMA_IDMABACT_Msk               /*!< Uses buffer 1 when double buffer mode is selected */\n\n/*****************  Bit definition for SDMMC_IDMABSIZE register  ***************/\n#define SDMMC_IDMABSIZE_IDMABNDT_Pos     (5U)\n#define SDMMC_IDMABSIZE_IDMABNDT_Msk     (0xFFUL << SDMMC_IDMABSIZE_IDMABNDT_Pos) /*!< 0x00001FE0 */\n#define SDMMC_IDMABSIZE_IDMABNDT         SDMMC_IDMABSIZE_IDMABNDT_Msk          /*!< Number of transfers per buffer */\n\n/*****************  Bit definition for SDMMC_IDMABASE0 register  ***************/\n#define SDMMC_IDMABASE0_IDMABASE0        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 0 memory base address */\n\n/*****************  Bit definition for SDMMC_IDMABASE1 register  ***************/\n#define SDMMC_IDMABASE1_IDMABASE1        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 1 memory base address */\n\n/******************************************************************************/\n/*                                                                            */\n/*                        Delay Block Interface (DLYB)                        */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for DLYB_CR register  ********************/\n#define DLYB_CR_DEN_Pos         (0U)\n#define DLYB_CR_DEN_Msk         (0x1UL << DLYB_CR_DEN_Pos)                     /*!< 0x00000001 */\n#define DLYB_CR_DEN             DLYB_CR_DEN_Msk                                /*!<Delay Block enable */\n#define DLYB_CR_SEN_Pos         (1U)\n#define DLYB_CR_SEN_Msk         (0x1UL << DLYB_CR_SEN_Pos)                     /*!< 0x00000002 */\n#define DLYB_CR_SEN             DLYB_CR_SEN_Msk                                /*!<Sampler length enable */\n\n\n/*******************  Bit definition for DLYB_CFGR register  ********************/\n#define DLYB_CFGR_SEL_Pos       (0U)\n#define DLYB_CFGR_SEL_Msk       (0xFUL << DLYB_CFGR_SEL_Pos)                   /*!< 0x0000000F */\n#define DLYB_CFGR_SEL           DLYB_CFGR_SEL_Msk                              /*!<Select the phase for the Output clock[3:0] */\n#define DLYB_CFGR_SEL_0         (0x1UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000001 */\n#define DLYB_CFGR_SEL_1         (0x2UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000002 */\n#define DLYB_CFGR_SEL_2         (0x3UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000003 */\n#define DLYB_CFGR_SEL_3         (0x8UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000008 */\n\n#define DLYB_CFGR_UNIT_Pos      (8U)\n#define DLYB_CFGR_UNIT_Msk      (0x7FUL << DLYB_CFGR_UNIT_Pos)                 /*!< 0x00007F00 */\n#define DLYB_CFGR_UNIT          DLYB_CFGR_UNIT_Msk                             /*!<Delay Defines the delay of a Unit delay cell[6:0] */\n#define DLYB_CFGR_UNIT_0        (0x01UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000100 */\n#define DLYB_CFGR_UNIT_1        (0x02UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000200 */\n#define DLYB_CFGR_UNIT_2        (0x04UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000400 */\n#define DLYB_CFGR_UNIT_3        (0x08UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000800 */\n#define DLYB_CFGR_UNIT_4        (0x10UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00001000 */\n#define DLYB_CFGR_UNIT_5        (0x20UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00002000 */\n#define DLYB_CFGR_UNIT_6        (0x40UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00004000 */\n\n#define DLYB_CFGR_LNG_Pos       (16U)\n#define DLYB_CFGR_LNG_Msk       (0xFFFUL << DLYB_CFGR_LNG_Pos)                 /*!< 0x0FFF0000 */\n#define DLYB_CFGR_LNG           DLYB_CFGR_LNG_Msk                              /*!<Delay line length value[11:0] */\n#define DLYB_CFGR_LNG_0         (0x001UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00010000 */\n#define DLYB_CFGR_LNG_1         (0x002UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00020000 */\n#define DLYB_CFGR_LNG_2         (0x004UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00040000 */\n#define DLYB_CFGR_LNG_3         (0x008UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00080000 */\n#define DLYB_CFGR_LNG_4         (0x010UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00100000 */\n#define DLYB_CFGR_LNG_5         (0x020UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00200000 */\n#define DLYB_CFGR_LNG_6         (0x040UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00400000 */\n#define DLYB_CFGR_LNG_7         (0x080UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00800000 */\n#define DLYB_CFGR_LNG_8         (0x100UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x01000000 */\n#define DLYB_CFGR_LNG_9         (0x200UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x02000000 */\n#define DLYB_CFGR_LNG_10        (0x400UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x04000000 */\n#define DLYB_CFGR_LNG_11        (0x800UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x08000000 */\n\n#define DLYB_CFGR_LNGF_Pos      (31U)\n#define DLYB_CFGR_LNGF_Msk      (0x1UL << DLYB_CFGR_LNGF_Pos)                  /*!< 0x80000000 */\n#define DLYB_CFGR_LNGF          DLYB_CFGR_LNGF_Msk                             /*!<Length valid flag */\n\n/******************************************************************************/\n/*                                                                            */\n/*                   Serial Peripheral Interface (SPI/I2S)                    */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for SPI_CR1 register  ********************/\n#define SPI_CR1_SPE_Pos             (0U)\n#define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                 /*!< 0x00000001 */\n#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<Serial Peripheral Enable                         */\n#define SPI_CR1_MASRX_Pos           (8U)\n#define SPI_CR1_MASRX_Msk           (0x1UL << SPI_CR1_MASRX_Pos)               /*!< 0x00000100 */\n#define SPI_CR1_MASRX               SPI_CR1_MASRX_Msk                          /*!<Master automatic SUSP in Receive mode            */\n#define SPI_CR1_CSTART_Pos          (9U)\n#define SPI_CR1_CSTART_Msk          (0x1UL << SPI_CR1_CSTART_Pos)              /*!< 0x00000200 */\n#define SPI_CR1_CSTART              SPI_CR1_CSTART_Msk                         /*!<Master transfer start                            */\n#define SPI_CR1_CSUSP_Pos           (10U)\n#define SPI_CR1_CSUSP_Msk           (0x1UL << SPI_CR1_CSUSP_Pos)               /*!< 0x00000400 */\n#define SPI_CR1_CSUSP               SPI_CR1_CSUSP_Msk                          /*!<Master SUSPend request                           */\n#define SPI_CR1_HDDIR_Pos           (11U)\n#define SPI_CR1_HDDIR_Msk           (0x1UL << SPI_CR1_HDDIR_Pos)               /*!< 0x00000800 */\n#define SPI_CR1_HDDIR               SPI_CR1_HDDIR_Msk                          /*!<Rx/Tx direction at Half-duplex mode              */\n#define SPI_CR1_SSI_Pos             (12U)\n#define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                 /*!< 0x00001000 */\n#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal SS signal input level                   */\n#define SPI_CR1_CRC33_17_Pos        (13U)\n#define SPI_CR1_CRC33_17_Msk        (0x1UL << SPI_CR1_CRC33_17_Pos)            /*!< 0x00002000 */\n#define SPI_CR1_CRC33_17             SPI_CR1_CRC33_17_Msk                      /*!<32-bit CRC polynomial configuration              */\n#define SPI_CR1_RCRCINI_Pos         (14U)\n#define SPI_CR1_RCRCINI_Msk         (0x1UL << SPI_CR1_RCRCINI_Pos)             /*!< 0x00004000 */\n#define SPI_CR1_RCRCINI             SPI_CR1_RCRCINI_Msk                        /*!<CRC init pattern control for receiver            */\n#define SPI_CR1_TCRCINI_Pos         (15U)\n#define SPI_CR1_TCRCINI_Msk         (0x1UL << SPI_CR1_TCRCINI_Pos)             /*!< 0x00008000 */\n#define SPI_CR1_TCRCINI             SPI_CR1_TCRCINI_Msk                        /*!<CRC init pattern control for transmitter         */\n#define SPI_CR1_IOLOCK_Pos          (16U)\n#define SPI_CR1_IOLOCK_Msk          (0x1UL << SPI_CR1_IOLOCK_Pos)              /*!< 0x00010000 */\n#define SPI_CR1_IOLOCK              SPI_CR1_IOLOCK_Msk                         /*!<Locking the AF configuration of associated IOs   */\n\n/*******************  Bit definition for SPI_CR2 register  ********************/\n#define SPI_CR2_TSER_Pos            (16U)\n#define SPI_CR2_TSER_Msk            (0xFFFFUL << SPI_CR2_TSER_Pos)             /*!< 0xFFFF0000 */\n#define SPI_CR2_TSER                SPI_CR2_TSER_Msk                           /*!<Number of data transfer extension                */\n#define SPI_CR2_TSIZE_Pos           (0U)\n#define SPI_CR2_TSIZE_Msk           (0xFFFFUL << SPI_CR2_TSIZE_Pos)            /*!< 0x0000FFFF */\n#define SPI_CR2_TSIZE               SPI_CR2_TSIZE_Msk                          /*!<Number of data at current transfer               */\n\n/*******************  Bit definition for SPI_CFG1 register  ********************/\n#define SPI_CFG1_DSIZE_Pos          (0U)\n#define SPI_CFG1_DSIZE_Msk          (0x1FUL << SPI_CFG1_DSIZE_Pos)             /*!< 0x0000001F */\n#define SPI_CFG1_DSIZE              SPI_CFG1_DSIZE_Msk                         /*!<DSIZE[4:0]: Bits number in single SPI data frame */\n#define SPI_CFG1_DSIZE_0            (0x01UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000001 */\n#define SPI_CFG1_DSIZE_1            (0x02UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000002 */\n#define SPI_CFG1_DSIZE_2            (0x04UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000004 */\n#define SPI_CFG1_DSIZE_3            (0x08UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000008 */\n#define SPI_CFG1_DSIZE_4            (0x10UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000010 */\n\n#define SPI_CFG1_FTHLV_Pos          (5U)\n#define SPI_CFG1_FTHLV_Msk          (0xFUL << SPI_CFG1_FTHLV_Pos)              /*!< 0x000001E0 */\n#define SPI_CFG1_FTHLV              SPI_CFG1_FTHLV_Msk                         /*!<FTHVL [3:0]: FIFO threshold level*/\n#define SPI_CFG1_FTHLV_0            (0x1UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000020 */\n#define SPI_CFG1_FTHLV_1            (0x2UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000040 */\n#define SPI_CFG1_FTHLV_2            (0x4UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000080 */\n#define SPI_CFG1_FTHLV_3            (0x8UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000100 */\n\n#define SPI_CFG1_UDRCFG_Pos         (9U)\n#define SPI_CFG1_UDRCFG_Msk         (0x3UL << SPI_CFG1_UDRCFG_Pos)             /*!< 0x00000600 */\n#define SPI_CFG1_UDRCFG             SPI_CFG1_UDRCFG_Msk                        /*!<UDRCFG[1:0]: Behavior of transmitter at underrun */\n#define SPI_CFG1_UDRCFG_0           (0x1UL << SPI_CFG1_UDRCFG_Pos)              /*!< 0x00000200 */\n#define SPI_CFG1_UDRCFG_1           (0x2UL << SPI_CFG1_UDRCFG_Pos)              /*!< 0x00000400 */\n\n\n#define SPI_CFG1_UDRDET_Pos         (11U)\n#define SPI_CFG1_UDRDET_Msk         (0x3UL << SPI_CFG1_UDRDET_Pos)             /*!< 0x00001800 */\n#define SPI_CFG1_UDRDET             SPI_CFG1_UDRDET_Msk                        /*!<UDRDET[1:0]: Detection of underrun condition     */\n#define SPI_CFG1_UDRDET_0           (0x1UL << SPI_CFG1_UDRDET_Pos)              /*!< 0x00000800 */\n#define SPI_CFG1_UDRDET_1           (0x2UL << SPI_CFG1_UDRDET_Pos)              /*!< 0x00001000 */\n\n#define SPI_CFG1_RXDMAEN_Pos        (14U)\n#define SPI_CFG1_RXDMAEN_Msk        (0x1UL << SPI_CFG1_RXDMAEN_Pos)            /*!< 0x00004000 */\n#define SPI_CFG1_RXDMAEN            SPI_CFG1_RXDMAEN_Msk                       /*!<Rx DMA stream enable                */\n#define SPI_CFG1_TXDMAEN_Pos        (15U)\n#define SPI_CFG1_TXDMAEN_Msk        (0x1UL << SPI_CFG1_TXDMAEN_Pos)            /*!< 0x00008000 */\n#define SPI_CFG1_TXDMAEN            SPI_CFG1_TXDMAEN_Msk                       /*!<Tx DMA stream enable                */\n\n#define SPI_CFG1_CRCSIZE_Pos        (16U)\n#define SPI_CFG1_CRCSIZE_Msk        (0x1FUL << SPI_CFG1_CRCSIZE_Pos)           /*!< 0x001F0000 */\n#define SPI_CFG1_CRCSIZE            SPI_CFG1_CRCSIZE_Msk                       /*!<CRCSIZE [4:0]: Length of CRC frame*/\n#define SPI_CFG1_CRCSIZE_0          (0x01UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00010000 */\n#define SPI_CFG1_CRCSIZE_1          (0x02UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00020000 */\n#define SPI_CFG1_CRCSIZE_2          (0x04UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00040000 */\n#define SPI_CFG1_CRCSIZE_3          (0x08UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00080000 */\n#define SPI_CFG1_CRCSIZE_4          (0x10UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00100000 */\n\n#define SPI_CFG1_CRCEN_Pos          (22U)\n#define SPI_CFG1_CRCEN_Msk          (0x1UL << SPI_CFG1_CRCEN_Pos)              /*!< 0x00400000 */\n#define SPI_CFG1_CRCEN              SPI_CFG1_CRCEN_Msk                         /*!<Hardware CRC computation enable */\n\n#define SPI_CFG1_MBR_Pos            (28U)\n#define SPI_CFG1_MBR_Msk            (0x7UL << SPI_CFG1_MBR_Pos)                /*!< 0x70000000 */\n#define SPI_CFG1_MBR                SPI_CFG1_MBR_Msk                           /*!<Master baud rate                */\n#define SPI_CFG1_MBR_0              (0x1UL << SPI_CFG1_MBR_Pos)                 /*!< 0x10000000 */\n#define SPI_CFG1_MBR_1              (0x2UL << SPI_CFG1_MBR_Pos)                 /*!< 0x20000000 */\n#define SPI_CFG1_MBR_2              (0x4UL << SPI_CFG1_MBR_Pos)                 /*!< 0x40000000 */\n\n/*******************  Bit definition for SPI_CFG2 register  ********************/\n#define SPI_CFG2_MSSI_Pos           (0U)\n#define SPI_CFG2_MSSI_Msk           (0xFUL << SPI_CFG2_MSSI_Pos)               /*!< 0x0000000F */\n#define SPI_CFG2_MSSI               SPI_CFG2_MSSI_Msk                          /*!<Master SS Idleness */\n#define SPI_CFG2_MSSI_0             (0x1UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000001 */\n#define SPI_CFG2_MSSI_1             (0x2UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000002 */\n#define SPI_CFG2_MSSI_2             (0x4UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000004 */\n#define SPI_CFG2_MSSI_3             (0x8UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000008 */\n\n#define SPI_CFG2_MIDI_Pos           (4U)\n#define SPI_CFG2_MIDI_Msk           (0xFUL << SPI_CFG2_MIDI_Pos)               /*!< 0x000000F0 */\n#define SPI_CFG2_MIDI               SPI_CFG2_MIDI_Msk                          /*!<Master Inter-Data Idleness */\n#define SPI_CFG2_MIDI_0             (0x1UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000010 */\n#define SPI_CFG2_MIDI_1             (0x2UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000020 */\n#define SPI_CFG2_MIDI_2             (0x4UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000040 */\n#define SPI_CFG2_MIDI_3             (0x8UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000080 */\n\n#define SPI_CFG2_IOSWP_Pos          (15U)\n#define SPI_CFG2_IOSWP_Msk          (0x1UL << SPI_CFG2_IOSWP_Pos)              /*!< 0x00008000 */\n#define SPI_CFG2_IOSWP              SPI_CFG2_IOSWP_Msk                         /*!<Swap functionality of MISO and MOSI pins */\n\n#define SPI_CFG2_COMM_Pos           (17U)\n#define SPI_CFG2_COMM_Msk           (0x3UL << SPI_CFG2_COMM_Pos)               /*!< 0x00060000 */\n#define SPI_CFG2_COMM               SPI_CFG2_COMM_Msk                          /*!<COMM [1:0]: SPI Communication Mode*/\n#define SPI_CFG2_COMM_0             (0x1UL << SPI_CFG2_COMM_Pos)                /*!< 0x00020000 */\n#define SPI_CFG2_COMM_1             (0x2UL << SPI_CFG2_COMM_Pos)                /*!< 0x00040000 */\n\n#define SPI_CFG2_SP_Pos             (19U)\n#define SPI_CFG2_SP_Msk             (0x7UL << SPI_CFG2_SP_Pos)                 /*!< 0x00380000 */\n#define SPI_CFG2_SP                 SPI_CFG2_SP_Msk                            /*!<SP[2:0]: Serial Protocol */\n#define SPI_CFG2_SP_0               (0x1UL << SPI_CFG2_SP_Pos)                  /*!< 0x00080000 */\n#define SPI_CFG2_SP_1               (0x2UL << SPI_CFG2_SP_Pos)                  /*!< 0x00100000 */\n#define SPI_CFG2_SP_2               (0x4UL << SPI_CFG2_SP_Pos)                  /*!< 0x00200000 */\n\n#define SPI_CFG2_MASTER_Pos         (22U)\n#define SPI_CFG2_MASTER_Msk         (0x1UL << SPI_CFG2_MASTER_Pos)             /*!< 0x00400000 */\n#define SPI_CFG2_MASTER             SPI_CFG2_MASTER_Msk                        /*!<SPI Master           */\n#define SPI_CFG2_LSBFRST_Pos        (23U)\n#define SPI_CFG2_LSBFRST_Msk        (0x1UL << SPI_CFG2_LSBFRST_Pos)            /*!< 0x00800000 */\n#define SPI_CFG2_LSBFRST            SPI_CFG2_LSBFRST_Msk                       /*!<Data frame format               */\n#define SPI_CFG2_CPHA_Pos           (24U)\n#define SPI_CFG2_CPHA_Msk           (0x1UL << SPI_CFG2_CPHA_Pos)               /*!< 0x01000000 */\n#define SPI_CFG2_CPHA               SPI_CFG2_CPHA_Msk                          /*!<Clock Phase      */\n#define SPI_CFG2_CPOL_Pos           (25U)\n#define SPI_CFG2_CPOL_Msk           (0x1UL << SPI_CFG2_CPOL_Pos)               /*!< 0x02000000 */\n#define SPI_CFG2_CPOL               SPI_CFG2_CPOL_Msk                          /*!<Clock Polarity   */\n#define SPI_CFG2_SSM_Pos            (26U)\n#define SPI_CFG2_SSM_Msk            (0x1UL << SPI_CFG2_SSM_Pos)                /*!< 0x04000000 */\n#define SPI_CFG2_SSM                SPI_CFG2_SSM_Msk                           /*!<Software slave management */\n\n#define SPI_CFG2_SSIOP_Pos          (28U)\n#define SPI_CFG2_SSIOP_Msk          (0x1UL << SPI_CFG2_SSIOP_Pos)              /*!< 0x10000000 */\n#define SPI_CFG2_SSIOP              SPI_CFG2_SSIOP_Msk                         /*!<SS input/output polarity */\n#define SPI_CFG2_SSOE_Pos           (29U)\n#define SPI_CFG2_SSOE_Msk           (0x1UL << SPI_CFG2_SSOE_Pos)               /*!< 0x20000000 */\n#define SPI_CFG2_SSOE               SPI_CFG2_SSOE_Msk                          /*!<SS output enable */\n#define SPI_CFG2_SSOM_Pos           (30U)\n#define SPI_CFG2_SSOM_Msk           (0x1UL << SPI_CFG2_SSOM_Pos)               /*!< 0x40000000 */\n#define SPI_CFG2_SSOM               SPI_CFG2_SSOM_Msk                          /*!<SS output management in master mode */\n\n#define SPI_CFG2_AFCNTR_Pos         (31U)\n#define SPI_CFG2_AFCNTR_Msk         (0x1UL << SPI_CFG2_AFCNTR_Pos)             /*!< 0x80000000 */\n#define SPI_CFG2_AFCNTR             SPI_CFG2_AFCNTR_Msk                        /*!<Alternate function GPIOs control */\n\n/*******************  Bit definition for SPI_IER register  ********************/\n#define SPI_IER_RXPIE_Pos           (0U)\n#define SPI_IER_RXPIE_Msk           (0x1UL << SPI_IER_RXPIE_Pos)               /*!< 0x00000001 */\n#define SPI_IER_RXPIE               SPI_IER_RXPIE_Msk                          /*!<RXP Interrupt Enable            */\n#define SPI_IER_TXPIE_Pos           (1U)\n#define SPI_IER_TXPIE_Msk           (0x1UL << SPI_IER_TXPIE_Pos)               /*!< 0x00000002 */\n#define SPI_IER_TXPIE               SPI_IER_TXPIE_Msk                          /*!<TXP interrupt enable            */\n#define SPI_IER_DXPIE_Pos           (2U)\n#define SPI_IER_DXPIE_Msk           (0x1UL << SPI_IER_DXPIE_Pos)               /*!< 0x00000004 */\n#define SPI_IER_DXPIE               SPI_IER_DXPIE_Msk                          /*!<DXP interrupt enable            */\n#define SPI_IER_EOTIE_Pos           (3U)\n#define SPI_IER_EOTIE_Msk           (0x1UL << SPI_IER_EOTIE_Pos)               /*!< 0x00000008 */\n#define SPI_IER_EOTIE               SPI_IER_EOTIE_Msk                          /*!<EOT/SUSP/TXC interrupt enable   */\n#define SPI_IER_TXTFIE_Pos          (4U)\n#define SPI_IER_TXTFIE_Msk          (0x1UL << SPI_IER_TXTFIE_Pos)              /*!< 0x00000010 */\n#define SPI_IER_TXTFIE              SPI_IER_TXTFIE_Msk                         /*!<TXTF interrupt enable           */\n#define SPI_IER_UDRIE_Pos           (5U)\n#define SPI_IER_UDRIE_Msk           (0x1UL << SPI_IER_UDRIE_Pos)               /*!< 0x00000020 */\n#define SPI_IER_UDRIE               SPI_IER_UDRIE_Msk                          /*!<UDR interrupt enable            */\n#define SPI_IER_OVRIE_Pos           (6U)\n#define SPI_IER_OVRIE_Msk           (0x1UL << SPI_IER_OVRIE_Pos)               /*!< 0x00000040 */\n#define SPI_IER_OVRIE               SPI_IER_OVRIE_Msk                          /*!<OVR interrupt enable            */\n#define SPI_IER_CRCEIE_Pos          (7U)\n#define SPI_IER_CRCEIE_Msk          (0x1UL << SPI_IER_CRCEIE_Pos)               /*!< 0x00000080 */\n#define SPI_IER_CRCEIE              SPI_IER_CRCEIE_Msk                          /*!<CRCE interrupt enable           */\n#define SPI_IER_TIFREIE_Pos         (8U)\n#define SPI_IER_TIFREIE_Msk         (0x1UL << SPI_IER_TIFREIE_Pos)             /*!< 0x00000100 */\n#define SPI_IER_TIFREIE             SPI_IER_TIFREIE_Msk                        /*!<TI Frame Error interrupt enable */\n#define SPI_IER_MODFIE_Pos          (9U)\n#define SPI_IER_MODFIE_Msk          (0x1UL << SPI_IER_MODFIE_Pos)              /*!< 0x00000200 */\n#define SPI_IER_MODFIE              SPI_IER_MODFIE_Msk                         /*!<MODF interrupt enable           */\n#define SPI_IER_TSERFIE_Pos         (10U)\n#define SPI_IER_TSERFIE_Msk         (0x1UL << SPI_IER_TSERFIE_Pos)              /*!< 0x00000400 */\n#define SPI_IER_TSERFIE             SPI_IER_TSERFIE_Msk                        /*!<TSERF interrupt enable          */\n\n/*******************  Bit definition for SPI_SR register  ********************/\n#define SPI_SR_RXP_Pos              (0U)\n#define SPI_SR_RXP_Msk              (0x1UL << SPI_SR_RXP_Pos)                  /*!< 0x00000001 */\n#define SPI_SR_RXP                  SPI_SR_RXP_Msk                             /*!<Rx-Packet available             */\n#define SPI_SR_TXP_Pos              (1U)\n#define SPI_SR_TXP_Msk              (0x1UL << SPI_SR_TXP_Pos)                  /*!< 0x00000002 */\n#define SPI_SR_TXP                  SPI_SR_TXP_Msk                             /*!<Tx-Packet space available       */\n#define SPI_SR_DXP_Pos              (2U)\n#define SPI_SR_DXP_Msk              (0x1UL << SPI_SR_DXP_Pos)                  /*!< 0x00000004 */\n#define SPI_SR_DXP                  SPI_SR_DXP_Msk                             /*!<Duplex Packet available         */\n#define SPI_SR_EOT_Pos              (3U)\n#define SPI_SR_EOT_Msk              (0x1UL << SPI_SR_EOT_Pos)                  /*!< 0x00000008 */\n#define SPI_SR_EOT                  SPI_SR_EOT_Msk                             /*!<Duplex Packet available         */\n#define SPI_SR_TXTF_Pos             (4U)\n#define SPI_SR_TXTF_Msk             (0x1UL << SPI_SR_TXTF_Pos)                 /*!< 0x00000010 */\n#define SPI_SR_TXTF                 SPI_SR_TXTF_Msk                            /*!<Transmission Transfer Filled    */\n#define SPI_SR_UDR_Pos              (5U)\n#define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                  /*!< 0x00000020 */\n#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!<UDR at Slave transmission       */\n#define SPI_SR_OVR_Pos              (6U)\n#define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                  /*!< 0x00000040 */\n#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!<Rx-Packet available             */\n#define SPI_SR_CRCE_Pos             (7U)\n#define SPI_SR_CRCE_Msk             (0x1UL << SPI_SR_CRCE_Pos)                 /*!< 0x00000080 */\n#define SPI_SR_CRCE                 SPI_SR_CRCE_Msk                            /*!<CRC Error Detected              */\n#define SPI_SR_TIFRE_Pos            (8U)\n#define SPI_SR_TIFRE_Msk            (0x1UL << SPI_SR_TIFRE_Pos)                /*!< 0x00000100 */\n#define SPI_SR_TIFRE                SPI_SR_TIFRE_Msk                           /*!<TI frame format error Detected  */\n#define SPI_SR_MODF_Pos             (9U)\n#define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                 /*!< 0x00000200 */\n#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!<Mode Fault Detected             */\n#define SPI_SR_TSERF_Pos            (10U)\n#define SPI_SR_TSERF_Msk            (0x1UL << SPI_SR_TSERF_Pos)                /*!< 0x00000400 */\n#define SPI_SR_TSERF                SPI_SR_TSERF_Msk                           /*!<Number of SPI data to be transacted reloaded     */\n#define SPI_SR_SUSP_Pos             (11U)\n#define SPI_SR_SUSP_Msk             (0x1UL << SPI_SR_SUSP_Pos)                 /*!< 0x00000800 */\n#define SPI_SR_SUSP                 SPI_SR_SUSP_Msk                            /*!<SUSP is set by hardware  */\n#define SPI_SR_TXC_Pos              (12U)\n#define SPI_SR_TXC_Msk              (0x1UL << SPI_SR_TXC_Pos)                  /*!< 0x00001000 */\n#define SPI_SR_TXC                  SPI_SR_TXC_Msk                             /*!<TxFIFO transmission complete */\n#define SPI_SR_RXPLVL_Pos           (13U)\n#define SPI_SR_RXPLVL_Msk           (0x3UL << SPI_SR_RXPLVL_Pos)               /*!< 0x00006000 */\n#define SPI_SR_RXPLVL               SPI_SR_RXPLVL_Msk                          /*!<RxFIFO Packing Level                             */\n#define SPI_SR_RXPLVL_0             (0x1UL << SPI_SR_RXPLVL_Pos)                /*!< 0x00002000 */\n#define SPI_SR_RXPLVL_1             (0x2UL << SPI_SR_RXPLVL_Pos)                /*!< 0x00004000 */\n#define SPI_SR_RXWNE_Pos            (15U)\n#define SPI_SR_RXWNE_Msk            (0x1UL << SPI_SR_RXWNE_Pos)                /*!< 0x00008000 */\n#define SPI_SR_RXWNE                SPI_SR_RXWNE_Msk                           /*!<Rx FIFO Word Not Empty                           */\n#define SPI_SR_CTSIZE_Pos           (16U)\n#define SPI_SR_CTSIZE_Msk           (0xFFFFUL << SPI_SR_CTSIZE_Pos)            /*!< 0xFFFF0000 */\n#define SPI_SR_CTSIZE               SPI_SR_CTSIZE_Msk                          /*!<Number of data frames remaining in TSIZE         */\n\n/*******************  Bit definition for SPI_IFCR register  ********************/\n#define SPI_IFCR_EOTC_Pos           (3U)\n#define SPI_IFCR_EOTC_Msk           (0x1UL << SPI_IFCR_EOTC_Pos)               /*!< 0x00000008 */\n#define SPI_IFCR_EOTC               SPI_IFCR_EOTC_Msk                          /*!<End Of Transfer flag clear              */\n#define SPI_IFCR_TXTFC_Pos          (4U)\n#define SPI_IFCR_TXTFC_Msk          (0x1UL << SPI_IFCR_TXTFC_Pos)              /*!< 0x00000010 */\n#define SPI_IFCR_TXTFC              SPI_IFCR_TXTFC_Msk                         /*!<Transmission Transfer Filled flag clear */\n#define SPI_IFCR_UDRC_Pos           (5U)\n#define SPI_IFCR_UDRC_Msk           (0x1UL << SPI_IFCR_UDRC_Pos)               /*!< 0x00000020 */\n#define SPI_IFCR_UDRC               SPI_IFCR_UDRC_Msk                          /*!<Underrun flag clear                     */\n#define SPI_IFCR_OVRC_Pos           (6U)\n#define SPI_IFCR_OVRC_Msk           (0x1UL << SPI_IFCR_OVRC_Pos)               /*!< 0x00000040 */\n#define SPI_IFCR_OVRC               SPI_IFCR_OVRC_Msk                          /*!<Overrun flag clear                      */\n#define SPI_IFCR_CRCEC_Pos          (7U)\n#define SPI_IFCR_CRCEC_Msk          (0x1UL << SPI_IFCR_CRCEC_Pos)              /*!< 0x00000080 */\n#define SPI_IFCR_CRCEC              SPI_IFCR_CRCEC_Msk                         /*!<CRC Error flag clear                    */\n#define SPI_IFCR_TIFREC_Pos         (8U)\n#define SPI_IFCR_TIFREC_Msk         (0x1UL << SPI_IFCR_TIFREC_Pos)             /*!< 0x00000100 */\n#define SPI_IFCR_TIFREC             SPI_IFCR_TIFREC_Msk                        /*!<TI frame format error flag clear        */\n#define SPI_IFCR_MODFC_Pos          (9U)\n#define SPI_IFCR_MODFC_Msk          (0x1UL << SPI_IFCR_MODFC_Pos)              /*!< 0x00000200 */\n#define SPI_IFCR_MODFC              SPI_IFCR_MODFC_Msk                         /*!<Mode Fault flag clear                   */\n#define SPI_IFCR_TSERFC_Pos         (10U)\n#define SPI_IFCR_TSERFC_Msk         (0x1UL << SPI_IFCR_TSERFC_Pos)             /*!< 0x00000400 */\n#define SPI_IFCR_TSERFC             SPI_IFCR_TSERFC_Msk                        /*!<TSERFC flag clear                       */\n#define SPI_IFCR_SUSPC_Pos          (11U)\n#define SPI_IFCR_SUSPC_Msk          (0x1UL << SPI_IFCR_SUSPC_Pos)              /*!< 0x00000800 */\n#define SPI_IFCR_SUSPC              SPI_IFCR_SUSPC_Msk                         /*!<SUSPend flag clear                      */\n\n/*******************  Bit definition for SPI_TXDR register  ********************/\n#define SPI_TXDR_TXDR_Pos           (0U)\n#define SPI_TXDR_TXDR_Msk           (0xFFFFFFFFUL << SPI_TXDR_TXDR_Pos)        /*!< 0xFFFFFFFF */\n#define SPI_TXDR_TXDR               SPI_TXDR_TXDR_Msk                          /* Transmit Data Register */\n\n/*******************  Bit definition for SPI_RXDR register  ********************/\n#define SPI_RXDR_RXDR_Pos           (0U)\n#define SPI_RXDR_RXDR_Msk           (0xFFFFFFFFUL << SPI_RXDR_RXDR_Pos)        /*!< 0xFFFFFFFF */\n#define SPI_RXDR_RXDR               SPI_RXDR_RXDR_Msk                          /* Receive Data Register  */\n\n/*******************  Bit definition for SPI_CRCPOLY register  ********************/\n#define SPI_CRCPOLY_CRCPOLY_Pos     (0U)\n#define SPI_CRCPOLY_CRCPOLY_Msk     (0xFFFFFFFFUL << SPI_CRCPOLY_CRCPOLY_Pos)  /*!< 0xFFFFFFFF */\n#define SPI_CRCPOLY_CRCPOLY         SPI_CRCPOLY_CRCPOLY_Msk                    /* CRC Polynomial register  */\n\n/*******************  Bit definition for SPI_TXCRC register  ********************/\n#define SPI_TXCRC_TXCRC_Pos         (0U)\n#define SPI_TXCRC_TXCRC_Msk         (0xFFFFFFFFUL << SPI_TXCRC_TXCRC_Pos)      /*!< 0xFFFFFFFF */\n#define SPI_TXCRC_TXCRC             SPI_TXCRC_TXCRC_Msk                        /* CRCRegister for transmitter */\n\n/*******************  Bit definition for SPI_RXCRC register  ********************/\n#define SPI_RXCRC_RXCRC_Pos         (0U)\n#define SPI_RXCRC_RXCRC_Msk         (0xFFFFFFFFUL << SPI_RXCRC_RXCRC_Pos)      /*!< 0xFFFFFFFF */\n#define SPI_RXCRC_RXCRC             SPI_RXCRC_RXCRC_Msk                        /* CRCRegister for receiver */\n\n/*******************  Bit definition for SPI_UDRDR register  ********************/\n#define SPI_UDRDR_UDRDR_Pos         (0U)\n#define SPI_UDRDR_UDRDR_Msk         (0xFFFFFFFFUL << SPI_UDRDR_UDRDR_Pos)      /*!< 0xFFFFFFFF */\n#define SPI_UDRDR_UDRDR             SPI_UDRDR_UDRDR_Msk                        /* Data at slave underrun condition */\n\n/******************  Bit definition for SPI_I2SCFGR register  *****************/\n#define SPI_I2SCFGR_I2SMOD_Pos      (0U)\n#define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)          /*!< 0x00000001 */\n#define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */\n#define SPI_I2SCFGR_I2SCFG_Pos      (1U)\n#define SPI_I2SCFGR_I2SCFG_Msk      (0x7UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x0000000E */\n#define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[2:0] I2S configuration mode                */\n#define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000002 */\n#define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000004 */\n#define SPI_I2SCFGR_I2SCFG_2        (0x4UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000008 */\n#define SPI_I2SCFGR_I2SSTD_Pos      (4U)\n#define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000030 */\n#define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] I2S standard selection                */\n#define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */\n#define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */\n#define SPI_I2SCFGR_PCMSYNC_Pos     (7U)\n#define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)         /*!< 0x00000080 */\n#define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization                         */\n#define SPI_I2SCFGR_DATLEN_Pos      (8U)\n#define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000300 */\n#define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] Data length to be transferred         */\n#define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000100 */\n#define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000200 */\n#define SPI_I2SCFGR_CHLEN_Pos       (10U)\n#define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)           /*!< 0x00000400 */\n#define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */\n#define SPI_I2SCFGR_CKPOL_Pos       (11U)\n#define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)           /*!< 0x00000800 */\n#define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<Steady state clock polarity                       */\n#define SPI_I2SCFGR_FIXCH_Pos       (12U)\n#define SPI_I2SCFGR_FIXCH_Msk       (0x1UL << SPI_I2SCFGR_FIXCH_Pos)           /*!< 0x00001000 */\n#define SPI_I2SCFGR_FIXCH           SPI_I2SCFGR_FIXCH_Msk                      /*!<Fixed channel length in SLAVE                     */\n#define SPI_I2SCFGR_WSINV_Pos       (13U)\n#define SPI_I2SCFGR_WSINV_Msk       (0x1UL << SPI_I2SCFGR_WSINV_Pos)           /*!< 0x00002000 */\n#define SPI_I2SCFGR_WSINV           SPI_I2SCFGR_WSINV_Msk                      /*!<Word select inversion                             */\n#define SPI_I2SCFGR_DATFMT_Pos      (14U)\n#define SPI_I2SCFGR_DATFMT_Msk      (0x1UL << SPI_I2SCFGR_DATFMT_Pos)          /*!< 0x00004000 */\n#define SPI_I2SCFGR_DATFMT          SPI_I2SCFGR_DATFMT_Msk                     /*!<Data format                                       */\n#define SPI_I2SCFGR_I2SDIV_Pos      (16U)\n#define SPI_I2SCFGR_I2SDIV_Msk      (0xFFUL << SPI_I2SCFGR_I2SDIV_Pos)         /*!< 0x00FF0000 */\n#define SPI_I2SCFGR_I2SDIV          SPI_I2SCFGR_I2SDIV_Msk                     /*!<I2S Linear prescaler */\n#define SPI_I2SCFGR_ODD_Pos         (24U)\n#define SPI_I2SCFGR_ODD_Msk         (0x1UL << SPI_I2SCFGR_ODD_Pos)             /*!< 0x01000000 */\n#define SPI_I2SCFGR_ODD             SPI_I2SCFGR_ODD_Msk                        /*!<Odd factor for the prescaler */\n#define SPI_I2SCFGR_MCKOE_Pos       (25U)\n#define SPI_I2SCFGR_MCKOE_Msk       (0x1UL << SPI_I2SCFGR_MCKOE_Pos)           /*!< 0x02000000 */\n#define SPI_I2SCFGR_MCKOE           SPI_I2SCFGR_MCKOE_Msk                      /*!<Master Clock Output Enable */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                                    QUADSPI                                 */\n/*                                                                            */\n/******************************************************************************/\n/*****************  Bit definition for QUADSPI_CR register  *******************/\n#define QUADSPI_CR_EN_Pos                (0U)\n#define QUADSPI_CR_EN_Msk                (0x1UL << QUADSPI_CR_EN_Pos)          /*!< 0x00000001 */\n#define QUADSPI_CR_EN                    QUADSPI_CR_EN_Msk                     /*!< Enable */\n#define QUADSPI_CR_ABORT_Pos             (1U)\n#define QUADSPI_CR_ABORT_Msk             (0x1UL << QUADSPI_CR_ABORT_Pos)       /*!< 0x00000002 */\n#define QUADSPI_CR_ABORT                 QUADSPI_CR_ABORT_Msk                  /*!< Abort request */\n#define QUADSPI_CR_DMAEN_Pos             (2U)\n#define QUADSPI_CR_DMAEN_Msk             (0x1UL << QUADSPI_CR_DMAEN_Pos)       /*!< 0x00000004 */\n#define QUADSPI_CR_DMAEN                 QUADSPI_CR_DMAEN_Msk                  /*!< Reserved: needed for softawre compatibility (DMA Enable) */\n#define QUADSPI_CR_TCEN_Pos              (3U)\n#define QUADSPI_CR_TCEN_Msk              (0x1UL << QUADSPI_CR_TCEN_Pos)        /*!< 0x00000008 */\n#define QUADSPI_CR_TCEN                  QUADSPI_CR_TCEN_Msk                   /*!< Timeout Counter Enable */\n#define QUADSPI_CR_SSHIFT_Pos            (4U)\n#define QUADSPI_CR_SSHIFT_Msk            (0x1UL << QUADSPI_CR_SSHIFT_Pos)      /*!< 0x00000010 */\n#define QUADSPI_CR_SSHIFT                QUADSPI_CR_SSHIFT_Msk                 /*!< SSHIFT Sample Shift */\n#define QUADSPI_CR_DFM_Pos               (6U)\n#define QUADSPI_CR_DFM_Msk               (0x1UL << QUADSPI_CR_DFM_Pos)         /*!< 0x00000040 */\n#define QUADSPI_CR_DFM                   QUADSPI_CR_DFM_Msk                    /*!< Dual Flash Mode */\n#define QUADSPI_CR_FSEL_Pos              (7U)\n#define QUADSPI_CR_FSEL_Msk              (0x1UL << QUADSPI_CR_FSEL_Pos)        /*!< 0x00000080 */\n#define QUADSPI_CR_FSEL                  QUADSPI_CR_FSEL_Msk                   /*!< Flash Select */\n#define QUADSPI_CR_FTHRES_Pos            (8U)\n#define QUADSPI_CR_FTHRES_Msk            (0xFUL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000F00 */\n#define QUADSPI_CR_FTHRES                QUADSPI_CR_FTHRES_Msk                 /*!< FTHRES[3:0] FIFO Level */\n#define QUADSPI_CR_FTHRES_0              (0x1UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000100 */\n#define QUADSPI_CR_FTHRES_1              (0x2UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000200 */\n#define QUADSPI_CR_FTHRES_2              (0x4UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000400 */\n#define QUADSPI_CR_FTHRES_3              (0x8UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000800 */\n#define QUADSPI_CR_TEIE_Pos              (16U)\n#define QUADSPI_CR_TEIE_Msk              (0x1UL << QUADSPI_CR_TEIE_Pos)        /*!< 0x00010000 */\n#define QUADSPI_CR_TEIE                  QUADSPI_CR_TEIE_Msk                   /*!< Transfer Error Interrupt Enable */\n#define QUADSPI_CR_TCIE_Pos              (17U)\n#define QUADSPI_CR_TCIE_Msk              (0x1UL << QUADSPI_CR_TCIE_Pos)        /*!< 0x00020000 */\n#define QUADSPI_CR_TCIE                  QUADSPI_CR_TCIE_Msk                   /*!< Transfer Complete Interrupt Enable */\n#define QUADSPI_CR_FTIE_Pos              (18U)\n#define QUADSPI_CR_FTIE_Msk              (0x1UL << QUADSPI_CR_FTIE_Pos)        /*!< 0x00040000 */\n#define QUADSPI_CR_FTIE                  QUADSPI_CR_FTIE_Msk                   /*!< FIFO Threshold Interrupt Enable */\n#define QUADSPI_CR_SMIE_Pos              (19U)\n#define QUADSPI_CR_SMIE_Msk              (0x1UL << QUADSPI_CR_SMIE_Pos)        /*!< 0x00080000 */\n#define QUADSPI_CR_SMIE                  QUADSPI_CR_SMIE_Msk                   /*!< Status Match Interrupt Enable */\n#define QUADSPI_CR_TOIE_Pos              (20U)\n#define QUADSPI_CR_TOIE_Msk              (0x1UL << QUADSPI_CR_TOIE_Pos)        /*!< 0x00100000 */\n#define QUADSPI_CR_TOIE                  QUADSPI_CR_TOIE_Msk                   /*!< TimeOut Interrupt Enable */\n#define QUADSPI_CR_APMS_Pos              (22U)\n#define QUADSPI_CR_APMS_Msk              (0x1UL << QUADSPI_CR_APMS_Pos)        /*!< 0x00400000 */\n#define QUADSPI_CR_APMS                  QUADSPI_CR_APMS_Msk                   /*!< Bit 1 */\n#define QUADSPI_CR_PMM_Pos               (23U)\n#define QUADSPI_CR_PMM_Msk               (0x1UL << QUADSPI_CR_PMM_Pos)         /*!< 0x00800000 */\n#define QUADSPI_CR_PMM                   QUADSPI_CR_PMM_Msk                    /*!< Polling Match Mode */\n#define QUADSPI_CR_PRESCALER_Pos         (24U)\n#define QUADSPI_CR_PRESCALER_Msk         (0xFFUL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0xFF000000 */\n#define QUADSPI_CR_PRESCALER             QUADSPI_CR_PRESCALER_Msk              /*!< PRESCALER[7:0] Clock prescaler */\n#define QUADSPI_CR_PRESCALER_0           (0x01UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x01000000 */\n#define QUADSPI_CR_PRESCALER_1           (0x02UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x02000000 */\n#define QUADSPI_CR_PRESCALER_2           (0x04UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x04000000 */\n#define QUADSPI_CR_PRESCALER_3           (0x08UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x08000000 */\n#define QUADSPI_CR_PRESCALER_4           (0x10UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x10000000 */\n#define QUADSPI_CR_PRESCALER_5           (0x20UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x20000000 */\n#define QUADSPI_CR_PRESCALER_6           (0x40UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x40000000 */\n#define QUADSPI_CR_PRESCALER_7           (0x80UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x80000000 */\n\n/*****************  Bit definition for QUADSPI_DCR register  ******************/\n#define QUADSPI_DCR_CKMODE_Pos           (0U)\n#define QUADSPI_DCR_CKMODE_Msk           (0x1UL << QUADSPI_DCR_CKMODE_Pos)     /*!< 0x00000001 */\n#define QUADSPI_DCR_CKMODE               QUADSPI_DCR_CKMODE_Msk                /*!< Mode 0 / Mode 3 */\n#define QUADSPI_DCR_CSHT_Pos             (8U)\n#define QUADSPI_DCR_CSHT_Msk             (0x7UL << QUADSPI_DCR_CSHT_Pos)       /*!< 0x00000700 */\n#define QUADSPI_DCR_CSHT                 QUADSPI_DCR_CSHT_Msk                  /*!< CSHT[2:0]: ChipSelect High Time */\n#define QUADSPI_DCR_CSHT_0               (0x1UL << QUADSPI_DCR_CSHT_Pos)       /*!< 0x00000100 */\n#define QUADSPI_DCR_CSHT_1               (0x2UL << QUADSPI_DCR_CSHT_Pos)       /*!< 0x00000200 */\n#define QUADSPI_DCR_CSHT_2               (0x4UL << QUADSPI_DCR_CSHT_Pos)       /*!< 0x00000400 */\n#define QUADSPI_DCR_FSIZE_Pos            (16U)\n#define QUADSPI_DCR_FSIZE_Msk            (0x1FUL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x001F0000 */\n#define QUADSPI_DCR_FSIZE                QUADSPI_DCR_FSIZE_Msk                 /*!< FSIZE[4:0]: Flash Size */\n#define QUADSPI_DCR_FSIZE_0              (0x01UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00010000 */\n#define QUADSPI_DCR_FSIZE_1              (0x02UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00020000 */\n#define QUADSPI_DCR_FSIZE_2              (0x04UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00040000 */\n#define QUADSPI_DCR_FSIZE_3              (0x08UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00080000 */\n#define QUADSPI_DCR_FSIZE_4              (0x10UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00100000 */\n\n/******************  Bit definition for QUADSPI_SR register  *******************/\n#define QUADSPI_SR_TEF_Pos               (0U)\n#define QUADSPI_SR_TEF_Msk               (0x1UL << QUADSPI_SR_TEF_Pos)         /*!< 0x00000001 */\n#define QUADSPI_SR_TEF                   QUADSPI_SR_TEF_Msk                    /*!< Transfer Error Flag */\n#define QUADSPI_SR_TCF_Pos               (1U)\n#define QUADSPI_SR_TCF_Msk               (0x1UL << QUADSPI_SR_TCF_Pos)         /*!< 0x00000002 */\n#define QUADSPI_SR_TCF                   QUADSPI_SR_TCF_Msk                    /*!< Transfer Complete Flag */\n#define QUADSPI_SR_FTF_Pos               (2U)\n#define QUADSPI_SR_FTF_Msk               (0x1UL << QUADSPI_SR_FTF_Pos)         /*!< 0x00000004 */\n#define QUADSPI_SR_FTF                   QUADSPI_SR_FTF_Msk                    /*!< FIFO Threshlod Flag */\n#define QUADSPI_SR_SMF_Pos               (3U)\n#define QUADSPI_SR_SMF_Msk               (0x1UL << QUADSPI_SR_SMF_Pos)         /*!< 0x00000008 */\n#define QUADSPI_SR_SMF                   QUADSPI_SR_SMF_Msk                    /*!< Status Match Flag */\n#define QUADSPI_SR_TOF_Pos               (4U)\n#define QUADSPI_SR_TOF_Msk               (0x1UL << QUADSPI_SR_TOF_Pos)         /*!< 0x00000010 */\n#define QUADSPI_SR_TOF                   QUADSPI_SR_TOF_Msk                    /*!< Timeout Flag */\n#define QUADSPI_SR_BUSY_Pos              (5U)\n#define QUADSPI_SR_BUSY_Msk              (0x1UL << QUADSPI_SR_BUSY_Pos)        /*!< 0x00000020 */\n#define QUADSPI_SR_BUSY                  QUADSPI_SR_BUSY_Msk                   /*!< Busy */\n#define QUADSPI_SR_FLEVEL_Pos            (8U)\n#define QUADSPI_SR_FLEVEL_Msk            (0x3FUL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00003F00 */\n#define QUADSPI_SR_FLEVEL                QUADSPI_SR_FLEVEL_Msk                 /*!< FIFO Threshlod Flag */\n#define QUADSPI_SR_FLEVEL_0              (0x01UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00000100 */\n#define QUADSPI_SR_FLEVEL_1              (0x02UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00000200 */\n#define QUADSPI_SR_FLEVEL_2              (0x04UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00000400 */\n#define QUADSPI_SR_FLEVEL_3              (0x08UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00000800 */\n#define QUADSPI_SR_FLEVEL_4              (0x10UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00001000 */\n#define QUADSPI_SR_FLEVEL_5              (0x20UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00002000 */\n\n/******************  Bit definition for QUADSPI_FCR register  ******************/\n#define QUADSPI_FCR_CTEF_Pos             (0U)\n#define QUADSPI_FCR_CTEF_Msk             (0x1UL << QUADSPI_FCR_CTEF_Pos)       /*!< 0x00000001 */\n#define QUADSPI_FCR_CTEF                 QUADSPI_FCR_CTEF_Msk                  /*!< Clear Transfer Error Flag */\n#define QUADSPI_FCR_CTCF_Pos             (1U)\n#define QUADSPI_FCR_CTCF_Msk             (0x1UL << QUADSPI_FCR_CTCF_Pos)       /*!< 0x00000002 */\n#define QUADSPI_FCR_CTCF                 QUADSPI_FCR_CTCF_Msk                  /*!< Clear Transfer Complete Flag */\n#define QUADSPI_FCR_CSMF_Pos             (3U)\n#define QUADSPI_FCR_CSMF_Msk             (0x1UL << QUADSPI_FCR_CSMF_Pos)       /*!< 0x00000008 */\n#define QUADSPI_FCR_CSMF                 QUADSPI_FCR_CSMF_Msk                  /*!< Clear Status Match Flag */\n#define QUADSPI_FCR_CTOF_Pos             (4U)\n#define QUADSPI_FCR_CTOF_Msk             (0x1UL << QUADSPI_FCR_CTOF_Pos)       /*!< 0x00000010 */\n#define QUADSPI_FCR_CTOF                 QUADSPI_FCR_CTOF_Msk                  /*!< Clear Timeout Flag */\n\n/******************  Bit definition for QUADSPI_DLR register  ******************/\n#define QUADSPI_DLR_DL_Pos               (0U)\n#define QUADSPI_DLR_DL_Msk               (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos)  /*!< 0xFFFFFFFF */\n#define QUADSPI_DLR_DL                   QUADSPI_DLR_DL_Msk                    /*!< DL[31:0]: Data Length */\n\n/******************  Bit definition for QUADSPI_CCR register  ******************/\n#define QUADSPI_CCR_INSTRUCTION_Pos      (0U)\n#define QUADSPI_CCR_INSTRUCTION_Msk      (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */\n#define QUADSPI_CCR_INSTRUCTION          QUADSPI_CCR_INSTRUCTION_Msk             /*!< INSTRUCTION[7:0]: Instruction */\n#define QUADSPI_CCR_INSTRUCTION_0        (0x01UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000001 */\n#define QUADSPI_CCR_INSTRUCTION_1        (0x02UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000002 */\n#define QUADSPI_CCR_INSTRUCTION_2        (0x04UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000004 */\n#define QUADSPI_CCR_INSTRUCTION_3        (0x08UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000008 */\n#define QUADSPI_CCR_INSTRUCTION_4        (0x10UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000010 */\n#define QUADSPI_CCR_INSTRUCTION_5        (0x20UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000020 */\n#define QUADSPI_CCR_INSTRUCTION_6        (0x40UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000040 */\n#define QUADSPI_CCR_INSTRUCTION_7        (0x80UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000080 */\n#define QUADSPI_CCR_IMODE_Pos            (8U)\n#define QUADSPI_CCR_IMODE_Msk            (0x3UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000300 */\n#define QUADSPI_CCR_IMODE                QUADSPI_CCR_IMODE_Msk                   /*!< IMODE[1:0]: Instruction Mode */\n#define QUADSPI_CCR_IMODE_0              (0x1UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000100 */\n#define QUADSPI_CCR_IMODE_1              (0x2UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000200 */\n#define QUADSPI_CCR_ADMODE_Pos           (10U)\n#define QUADSPI_CCR_ADMODE_Msk           (0x3UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000C00 */\n#define QUADSPI_CCR_ADMODE               QUADSPI_CCR_ADMODE_Msk                  /*!< ADMODE[1:0]: Address Mode */\n#define QUADSPI_CCR_ADMODE_0             (0x1UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000400 */\n#define QUADSPI_CCR_ADMODE_1             (0x2UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000800 */\n#define QUADSPI_CCR_ADSIZE_Pos           (12U)\n#define QUADSPI_CCR_ADSIZE_Msk           (0x3UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00003000 */\n#define QUADSPI_CCR_ADSIZE               QUADSPI_CCR_ADSIZE_Msk                  /*!< ADSIZE[1:0]: Address Size */\n#define QUADSPI_CCR_ADSIZE_0             (0x1UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00001000 */\n#define QUADSPI_CCR_ADSIZE_1             (0x2UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00002000 */\n#define QUADSPI_CCR_ABMODE_Pos           (14U)\n#define QUADSPI_CCR_ABMODE_Msk           (0x3UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x0000C000 */\n#define QUADSPI_CCR_ABMODE               QUADSPI_CCR_ABMODE_Msk                  /*!< ABMODE[1:0]: Alternate Bytes Mode */\n#define QUADSPI_CCR_ABMODE_0             (0x1UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x00004000 */\n#define QUADSPI_CCR_ABMODE_1             (0x2UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x00008000 */\n#define QUADSPI_CCR_ABSIZE_Pos           (16U)\n#define QUADSPI_CCR_ABSIZE_Msk           (0x3UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00030000 */\n#define QUADSPI_CCR_ABSIZE               QUADSPI_CCR_ABSIZE_Msk                  /*!< ABSIZE[1:0]: Instruction Mode */\n#define QUADSPI_CCR_ABSIZE_0             (0x1UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00010000 */\n#define QUADSPI_CCR_ABSIZE_1             (0x2UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00020000 */\n#define QUADSPI_CCR_DCYC_Pos             (18U)\n#define QUADSPI_CCR_DCYC_Msk             (0x1FUL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x007C0000 */\n#define QUADSPI_CCR_DCYC                 QUADSPI_CCR_DCYC_Msk                    /*!< DCYC[4:0]: Dummy Cycles */\n#define QUADSPI_CCR_DCYC_0               (0x01UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00040000 */\n#define QUADSPI_CCR_DCYC_1               (0x02UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00080000 */\n#define QUADSPI_CCR_DCYC_2               (0x04UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00100000 */\n#define QUADSPI_CCR_DCYC_3               (0x08UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00200000 */\n#define QUADSPI_CCR_DCYC_4               (0x10UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00400000 */\n#define QUADSPI_CCR_DMODE_Pos            (24U)\n#define QUADSPI_CCR_DMODE_Msk            (0x3UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x03000000 */\n#define QUADSPI_CCR_DMODE                QUADSPI_CCR_DMODE_Msk                   /*!< DMODE[1:0]: Data Mode */\n#define QUADSPI_CCR_DMODE_0              (0x1UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x01000000 */\n#define QUADSPI_CCR_DMODE_1              (0x2UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x02000000 */\n#define QUADSPI_CCR_FMODE_Pos            (26U)\n#define QUADSPI_CCR_FMODE_Msk            (0x3UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x0C000000 */\n#define QUADSPI_CCR_FMODE                QUADSPI_CCR_FMODE_Msk                   /*!< FMODE[1:0]: Functional Mode */\n#define QUADSPI_CCR_FMODE_0              (0x1UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x04000000 */\n#define QUADSPI_CCR_FMODE_1              (0x2UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x08000000 */\n#define QUADSPI_CCR_SIOO_Pos             (28U)\n#define QUADSPI_CCR_SIOO_Msk             (0x1UL << QUADSPI_CCR_SIOO_Pos)         /*!< 0x10000000 */\n#define QUADSPI_CCR_SIOO                 QUADSPI_CCR_SIOO_Msk                    /*!< SIOO: Send Instruction Only Once Mode */\n#define QUADSPI_CCR_DHHC_Pos             (30U)\n#define QUADSPI_CCR_DHHC_Msk             (0x1UL << QUADSPI_CCR_DHHC_Pos)         /*!< 0x40000000 */\n#define QUADSPI_CCR_DHHC                 QUADSPI_CCR_DHHC_Msk                    /*!< DHHC: DDR hold half cycle */\n#define QUADSPI_CCR_DDRM_Pos             (31U)\n#define QUADSPI_CCR_DDRM_Msk             (0x1UL << QUADSPI_CCR_DDRM_Pos)         /*!< 0x80000000 */\n#define QUADSPI_CCR_DDRM                 QUADSPI_CCR_DDRM_Msk                    /*!< DDRM: Double Data Rate Mode */\n\n/******************  Bit definition for QUADSPI_AR register  *******************/\n#define QUADSPI_AR_ADDRESS_Pos           (0U)\n#define QUADSPI_AR_ADDRESS_Msk           (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */\n#define QUADSPI_AR_ADDRESS               QUADSPI_AR_ADDRESS_Msk                /*!< ADDRESS[31:0]: Address */\n\n/******************  Bit definition for QUADSPI_ABR register  ******************/\n#define QUADSPI_ABR_ALTERNATE_Pos        (0U)\n#define QUADSPI_ABR_ALTERNATE_Msk        (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */\n#define QUADSPI_ABR_ALTERNATE            QUADSPI_ABR_ALTERNATE_Msk             /*!< ALTERNATE[31:0]: Alternate Bytes */\n\n/******************  Bit definition for QUADSPI_DR register  *******************/\n#define QUADSPI_DR_DATA_Pos              (0U)\n#define QUADSPI_DR_DATA_Msk              (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */\n#define QUADSPI_DR_DATA                  QUADSPI_DR_DATA_Msk                   /*!< DATA[31:0]: Data */\n\n/******************  Bit definition for QUADSPI_PSMKR register  ****************/\n#define QUADSPI_PSMKR_MASK_Pos           (0U)\n#define QUADSPI_PSMKR_MASK_Msk           (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */\n#define QUADSPI_PSMKR_MASK               QUADSPI_PSMKR_MASK_Msk                /*!< MASK[31:0]: Status Mask */\n\n/******************  Bit definition for QUADSPI_PSMAR register  ****************/\n#define QUADSPI_PSMAR_MATCH_Pos          (0U)\n#define QUADSPI_PSMAR_MATCH_Msk          (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */\n#define QUADSPI_PSMAR_MATCH              QUADSPI_PSMAR_MATCH_Msk               /*!< MATCH[31:0]: Status Match */\n\n/******************  Bit definition for QUADSPI_PIR register  *****************/\n#define QUADSPI_PIR_INTERVAL_Pos         (0U)\n#define QUADSPI_PIR_INTERVAL_Msk         (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */\n#define QUADSPI_PIR_INTERVAL             QUADSPI_PIR_INTERVAL_Msk              /*!< INTERVAL[15:0]: Polling Interval */\n\n/******************  Bit definition for QUADSPI_LPTR register  *****************/\n#define QUADSPI_LPTR_TIMEOUT_Pos         (0U)\n#define QUADSPI_LPTR_TIMEOUT_Msk         (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */\n#define QUADSPI_LPTR_TIMEOUT             QUADSPI_LPTR_TIMEOUT_Msk              /*!< TIMEOUT[15:0]: Timeout period */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                 SYSCFG                                     */\n/*                                                                            */\n/******************************************************************************/\n\n/******************  Bit definition for SYSCFG_PMCR register  ******************/\n#define SYSCFG_PMCR_I2C1_FMP_Pos        (0U)\n#define SYSCFG_PMCR_I2C1_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C1_FMP_Pos)    /*!< 0x00000001 */\n#define SYSCFG_PMCR_I2C1_FMP            SYSCFG_PMCR_I2C1_FMP_Msk               /*!< I2C1 Fast mode plus */\n#define SYSCFG_PMCR_I2C2_FMP_Pos        (1U)\n#define SYSCFG_PMCR_I2C2_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C2_FMP_Pos)    /*!< 0x00000002 */\n#define SYSCFG_PMCR_I2C2_FMP            SYSCFG_PMCR_I2C2_FMP_Msk               /*!< I2C2 Fast mode plus */\n#define SYSCFG_PMCR_I2C3_FMP_Pos        (2U)\n#define SYSCFG_PMCR_I2C3_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C3_FMP_Pos)    /*!< 0x00000004 */\n#define SYSCFG_PMCR_I2C3_FMP            SYSCFG_PMCR_I2C3_FMP_Msk               /*!< I2C3 Fast mode plus */\n#define SYSCFG_PMCR_I2C4_FMP_Pos        (3U)\n#define SYSCFG_PMCR_I2C4_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C4_FMP_Pos)    /*!< 0x00000008 */\n#define SYSCFG_PMCR_I2C4_FMP            SYSCFG_PMCR_I2C4_FMP_Msk               /*!< I2C4 Fast mode plus */\n#define SYSCFG_PMCR_I2C_PB6_FMP_Pos     (4U)\n#define SYSCFG_PMCR_I2C_PB6_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB6_FMP_Pos) /*!< 0x00000010 */\n#define SYSCFG_PMCR_I2C_PB6_FMP         SYSCFG_PMCR_I2C_PB6_FMP_Msk            /*!< I2C PB6 Fast mode plus */\n#define SYSCFG_PMCR_I2C_PB7_FMP_Pos     (5U)\n#define SYSCFG_PMCR_I2C_PB7_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB7_FMP_Pos) /*!< 0x00000020 */\n#define SYSCFG_PMCR_I2C_PB7_FMP         SYSCFG_PMCR_I2C_PB7_FMP_Msk            /*!< I2C PB7 Fast mode plus */\n#define SYSCFG_PMCR_I2C_PB8_FMP_Pos     (6U)\n#define SYSCFG_PMCR_I2C_PB8_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB8_FMP_Pos) /*!< 0x00000040 */\n#define SYSCFG_PMCR_I2C_PB8_FMP         SYSCFG_PMCR_I2C_PB8_FMP_Msk            /*!< I2C PB8 Fast mode plus */\n#define SYSCFG_PMCR_I2C_PB9_FMP_Pos     (7U)\n#define SYSCFG_PMCR_I2C_PB9_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB9_FMP_Pos) /*!< 0x00000080 */\n#define SYSCFG_PMCR_I2C_PB9_FMP         SYSCFG_PMCR_I2C_PB9_FMP_Msk            /*!< I2C PB9 Fast mode plus */\n#define SYSCFG_PMCR_BOOSTEN_Pos         (8U)\n#define SYSCFG_PMCR_BOOSTEN_Msk         (0x1UL << SYSCFG_PMCR_BOOSTEN_Pos)     /*!< 0x00000100 */\n#define SYSCFG_PMCR_BOOSTEN             SYSCFG_PMCR_BOOSTEN_Msk                /*!< I/O analog switch voltage booster enable */\n\n#define SYSCFG_PMCR_BOOSTVDDSEL_Pos     (9U)\n#define SYSCFG_PMCR_BOOSTVDDSEL_Msk     (0x1UL << SYSCFG_PMCR_BOOSTVDDSEL_Pos) /*!< 0x00000200 */\n#define SYSCFG_PMCR_BOOSTVDDSEL         SYSCFG_PMCR_BOOSTVDDSEL_Msk            /*!< Analog switch supply source selection : VDD/VDDA */\n\n#define SYSCFG_PMCR_EPIS_SEL_Pos        (21U)\n#define SYSCFG_PMCR_EPIS_SEL_Msk        (0x7UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00E00000 */\n#define SYSCFG_PMCR_EPIS_SEL            SYSCFG_PMCR_EPIS_SEL_Msk               /*!< Ethernet PHY Interface Selection */\n#define SYSCFG_PMCR_EPIS_SEL_0          (0x1UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00200000 */\n#define SYSCFG_PMCR_EPIS_SEL_1          (0x2UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00400000 */\n#define SYSCFG_PMCR_EPIS_SEL_2          (0x4UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00800000 */\n#define SYSCFG_PMCR_PA0SO_Pos           (24U)\n#define SYSCFG_PMCR_PA0SO_Msk           (0x1UL << SYSCFG_PMCR_PA0SO_Pos)       /*!< 0x01000000 */\n#define SYSCFG_PMCR_PA0SO               SYSCFG_PMCR_PA0SO_Msk                  /*!< PA0 Switch Open */\n#define SYSCFG_PMCR_PA1SO_Pos           (25U)\n#define SYSCFG_PMCR_PA1SO_Msk           (0x1UL << SYSCFG_PMCR_PA1SO_Pos)       /*!< 0x02000000 */\n#define SYSCFG_PMCR_PA1SO               SYSCFG_PMCR_PA1SO_Msk                  /*!< PA1 Switch Open */\n#define SYSCFG_PMCR_PC2SO_Pos           (26U)\n#define SYSCFG_PMCR_PC2SO_Msk           (0x1UL << SYSCFG_PMCR_PC2SO_Pos)       /*!< 0x04000000 */\n#define SYSCFG_PMCR_PC2SO               SYSCFG_PMCR_PC2SO_Msk                  /*!< PC2 Switch Open */\n#define SYSCFG_PMCR_PC3SO_Pos           (27U)\n#define SYSCFG_PMCR_PC3SO_Msk           (0x1UL << SYSCFG_PMCR_PC3SO_Pos)       /*!< 0x08000000 */\n#define SYSCFG_PMCR_PC3SO               SYSCFG_PMCR_PC3SO_Msk                  /*!< PC3 Switch Open */\n\n/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/\n#define SYSCFG_EXTICR1_EXTI0_Pos        (0U)\n#define SYSCFG_EXTICR1_EXTI0_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)    /*!< 0x0000000F */\n#define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!<EXTI 0 configuration */\n#define SYSCFG_EXTICR1_EXTI1_Pos        (4U)\n#define SYSCFG_EXTICR1_EXTI1_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)    /*!< 0x000000F0 */\n#define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!<EXTI 1 configuration */\n#define SYSCFG_EXTICR1_EXTI2_Pos        (8U)\n#define SYSCFG_EXTICR1_EXTI2_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)    /*!< 0x00000F00 */\n#define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!<EXTI 2 configuration */\n#define SYSCFG_EXTICR1_EXTI3_Pos        (12U)\n#define SYSCFG_EXTICR1_EXTI3_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)    /*!< 0x0000F000 */\n#define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!<EXTI 3 configuration */\n/**\n  * @brief   EXTI0 configuration\n  */\n#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x00000000)                 /*!<PA[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x00000001)                 /*!<PB[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x00000002)                 /*!<PC[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PD         ((uint32_t)0x00000003)                 /*!<PD[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PE         ((uint32_t)0x00000004)                 /*!<PE[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PF         ((uint32_t)0x00000005)                 /*!<PF[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PG         ((uint32_t)0x00000006)                 /*!<PG[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x00000007)                 /*!<PH[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PI         ((uint32_t)0x00000008)                 /*!<PI[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PJ         ((uint32_t)0x00000009)                 /*!<PJ[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PK         ((uint32_t)0x0000000A)                 /*!<PK[0] pin */\n\n/**\n  * @brief   EXTI1 configuration\n  */\n#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x00000000)                 /*!<PA[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x00000010)                 /*!<PB[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x00000020)                 /*!<PC[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PD         ((uint32_t)0x00000030)                 /*!<PD[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PE         ((uint32_t)0x00000040)                 /*!<PE[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PF         ((uint32_t)0x00000050)                 /*!<PF[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PG         ((uint32_t)0x00000060)                 /*!<PG[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x00000070)                 /*!<PH[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PI         ((uint32_t)0x00000080)                 /*!<PI[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PJ         ((uint32_t)0x00000090)                 /*!<PJ[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PK         ((uint32_t)0x000000A0)                 /*!<PK[1] pin */\n/**\n  * @brief   EXTI2 configuration\n  */\n#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x00000000)                 /*!<PA[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x00000100)                 /*!<PB[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x00000200)                 /*!<PC[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x00000300)                 /*!<PD[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PE         ((uint32_t)0x00000400)                 /*!<PE[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PF         ((uint32_t)0x00000500)                 /*!<PF[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PG         ((uint32_t)0x00000600)                 /*!<PG[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PH         ((uint32_t)0x00000700)                 /*!<PH[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PI         ((uint32_t)0x00000800)                 /*!<PI[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PJ         ((uint32_t)0x00000900)                 /*!<PJ[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PK         ((uint32_t)0x00000A00)                 /*!<PK[2] pin */\n\n/**\n  * @brief   EXTI3 configuration\n  */\n#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x00000000)                 /*!<PA[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x00001000)                 /*!<PB[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x00002000)                 /*!<PC[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PD         ((uint32_t)0x00003000)                 /*!<PD[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PE         ((uint32_t)0x00004000)                 /*!<PE[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PF         ((uint32_t)0x00005000)                 /*!<PF[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PG         ((uint32_t)0x00006000)                 /*!<PG[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PH         ((uint32_t)0x00007000)                 /*!<PH[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PI         ((uint32_t)0x00008000)                 /*!<PI[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PJ         ((uint32_t)0x00009000)                 /*!<PJ[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PK         ((uint32_t)0x0000A000)                 /*!<PK[3] pin */\n\n/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/\n#define SYSCFG_EXTICR2_EXTI4_Pos        (0U)\n#define SYSCFG_EXTICR2_EXTI4_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)    /*!< 0x0000000F */\n#define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!<EXTI 4 configuration */\n#define SYSCFG_EXTICR2_EXTI5_Pos        (4U)\n#define SYSCFG_EXTICR2_EXTI5_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)    /*!< 0x000000F0 */\n#define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!<EXTI 5 configuration */\n#define SYSCFG_EXTICR2_EXTI6_Pos        (8U)\n#define SYSCFG_EXTICR2_EXTI6_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)    /*!< 0x00000F00 */\n#define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!<EXTI 6 configuration */\n#define SYSCFG_EXTICR2_EXTI7_Pos        (12U)\n#define SYSCFG_EXTICR2_EXTI7_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)    /*!< 0x0000F000 */\n#define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!<EXTI 7 configuration */\n/**\n  * @brief   EXTI4 configuration\n  */\n#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x00000000)                 /*!<PA[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x00000001)                 /*!<PB[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x00000002)                 /*!<PC[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PD         ((uint32_t)0x00000003)                 /*!<PD[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PE         ((uint32_t)0x00000004)                 /*!<PE[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PF         ((uint32_t)0x00000005)                 /*!<PF[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PG         ((uint32_t)0x00000006)                 /*!<PG[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PH         ((uint32_t)0x00000007)                 /*!<PH[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PI         ((uint32_t)0x00000008)                 /*!<PI[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PJ         ((uint32_t)0x00000009)                 /*!<PJ[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PK         ((uint32_t)0x0000000A)                 /*!<PK[4] pin */\n/**\n  * @brief   EXTI5 configuration\n  */\n#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x00000000)                 /*!<PA[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x00000010)                 /*!<PB[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x00000020)                 /*!<PC[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PD         ((uint32_t)0x00000030)                 /*!<PD[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PE         ((uint32_t)0x00000040)                 /*!<PE[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PF         ((uint32_t)0x00000050)                 /*!<PF[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PG         ((uint32_t)0x00000060)                 /*!<PG[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PH         ((uint32_t)0x00000070)                 /*!<PH[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PI         ((uint32_t)0x00000080)                 /*!<PI[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PJ         ((uint32_t)0x00000090)                 /*!<PJ[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PK         ((uint32_t)0x000000A0)                 /*!<PK[5] pin */\n/**\n  * @brief   EXTI6 configuration\n  */\n#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x00000000)                 /*!<PA[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x00000100)                 /*!<PB[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x00000200)                 /*!<PC[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PD         ((uint32_t)0x00000300)                 /*!<PD[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PE         ((uint32_t)0x00000400)                 /*!<PE[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PF         ((uint32_t)0x00000500)                 /*!<PF[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PG         ((uint32_t)0x00000600)                 /*!<PG[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PH         ((uint32_t)0x00000700)                 /*!<PH[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PI         ((uint32_t)0x00000800)                 /*!<PI[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PJ         ((uint32_t)0x00000900)                 /*!<PJ[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PK         ((uint32_t)0x00000A00)                 /*!<PK[6] pin */\n\n/**\n  * @brief   EXTI7 configuration\n  */\n#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x00000000)                 /*!<PA[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x00001000)                 /*!<PB[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x00002000)                 /*!<PC[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PD         ((uint32_t)0x00003000)                 /*!<PD[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PE         ((uint32_t)0x00004000)                 /*!<PE[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PF         ((uint32_t)0x00005000)                 /*!<PF[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PG         ((uint32_t)0x00006000)                 /*!<PG[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PH         ((uint32_t)0x00007000)                 /*!<PH[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PI         ((uint32_t)0x00008000)                 /*!<PI[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PJ         ((uint32_t)0x00009000)                 /*!<PJ[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PK         ((uint32_t)0x0000A000)                 /*!<PK[7] pin */\n\n/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/\n#define SYSCFG_EXTICR3_EXTI8_Pos        (0U)\n#define SYSCFG_EXTICR3_EXTI8_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)    /*!< 0x0000000F */\n#define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!<EXTI 8 configuration */\n#define SYSCFG_EXTICR3_EXTI9_Pos        (4U)\n#define SYSCFG_EXTICR3_EXTI9_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)    /*!< 0x000000F0 */\n#define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!<EXTI 9 configuration */\n#define SYSCFG_EXTICR3_EXTI10_Pos       (8U)\n#define SYSCFG_EXTICR3_EXTI10_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)   /*!< 0x00000F00 */\n#define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!<EXTI 10 configuration */\n#define SYSCFG_EXTICR3_EXTI11_Pos       (12U)\n#define SYSCFG_EXTICR3_EXTI11_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)   /*!< 0x0000F000 */\n#define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!<EXTI 11 configuration */\n\n/**\n  * @brief   EXTI8 configuration\n  */\n#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x00000000)                 /*!<PA[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x00000001)                 /*!<PB[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x00000002)                 /*!<PC[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PD         ((uint32_t)0x00000003)                 /*!<PD[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PE         ((uint32_t)0x00000004)                 /*!<PE[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PF         ((uint32_t)0x00000005)                 /*!<PF[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PG         ((uint32_t)0x00000006)                 /*!<PG[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PH         ((uint32_t)0x00000007)                 /*!<PH[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PI         ((uint32_t)0x00000008)                 /*!<PI[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PJ         ((uint32_t)0x00000009)                 /*!<PJ[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PK         ((uint32_t)0x0000000A)                 /*!<PK[8] pin */\n\n/**\n  * @brief   EXTI9 configuration\n  */\n#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x00000000)                 /*!<PA[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x00000010)                 /*!<PB[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x00000020)                 /*!<PC[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PD         ((uint32_t)0x00000030)                 /*!<PD[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PE         ((uint32_t)0x00000040)                 /*!<PE[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PF         ((uint32_t)0x00000050)                 /*!<PF[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PG         ((uint32_t)0x00000060)                 /*!<PG[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PH         ((uint32_t)0x00000070)                 /*!<PH[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PI         ((uint32_t)0x00000080)                 /*!<PI[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PJ         ((uint32_t)0x00000090)                 /*!<PJ[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PK         ((uint32_t)0x000000A0)                 /*!<PK[9] pin */\n\n/**\n  * @brief   EXTI10 configuration\n  */\n#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x00000000)                 /*!<PA[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x00000100)                 /*!<PB[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x00000200)                 /*!<PC[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PD        ((uint32_t)0x00000300)                 /*!<PD[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PE        ((uint32_t)0x00000400)                 /*!<PE[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PF        ((uint32_t)0x00000500)                 /*!<PF[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PG        ((uint32_t)0x00000600)                 /*!<PG[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PH        ((uint32_t)0x00000700)                 /*!<PH[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PI        ((uint32_t)0x00000800)                 /*!<PI[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PJ        ((uint32_t)0x00000900)                 /*!<PJ[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PK        ((uint32_t)0x00000A00)                 /*!<PK[10] pin */\n\n/**\n  * @brief   EXTI11 configuration\n  */\n#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x00000000)                 /*!<PA[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x00001000)                 /*!<PB[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x00002000)                 /*!<PC[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PD        ((uint32_t)0x00003000)                 /*!<PD[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PE        ((uint32_t)0x00004000)                 /*!<PE[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PF        ((uint32_t)0x00005000)                 /*!<PF[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PG        ((uint32_t)0x00006000)                 /*!<PG[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PH        ((uint32_t)0x00007000)                 /*!<PH[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PI        ((uint32_t)0x00008000)                 /*!<PI[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PJ        ((uint32_t)0x00009000)                 /*!<PJ[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PK        ((uint32_t)0x0000A000)                 /*!<PK[11] pin */\n\n/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/\n#define SYSCFG_EXTICR4_EXTI12_Pos       (0U)\n#define SYSCFG_EXTICR4_EXTI12_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)   /*!< 0x0000000F */\n#define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!<EXTI 12 configuration */\n#define SYSCFG_EXTICR4_EXTI13_Pos       (4U)\n#define SYSCFG_EXTICR4_EXTI13_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)   /*!< 0x000000F0 */\n#define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!<EXTI 13 configuration */\n#define SYSCFG_EXTICR4_EXTI14_Pos       (8U)\n#define SYSCFG_EXTICR4_EXTI14_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)   /*!< 0x00000F00 */\n#define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!<EXTI 14 configuration */\n#define SYSCFG_EXTICR4_EXTI15_Pos       (12U)\n#define SYSCFG_EXTICR4_EXTI15_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)   /*!< 0x0000F000 */\n#define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!<EXTI 15 configuration */\n/**\n  * @brief   EXTI12 configuration\n  */\n#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x00000000)                 /*!<PA[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x00000001)                 /*!<PB[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x00000002)                 /*!<PC[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PD        ((uint32_t)0x00000003)                 /*!<PD[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PE        ((uint32_t)0x00000004)                 /*!<PE[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PF        ((uint32_t)0x00000005)                 /*!<PF[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PG        ((uint32_t)0x00000006)                 /*!<PG[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PH        ((uint32_t)0x00000007)                 /*!<PH[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PI        ((uint32_t)0x00000008)                 /*!<PI[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PJ        ((uint32_t)0x00000009)                 /*!<PJ[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PK        ((uint32_t)0x0000000A)                 /*!<PK[12] pin */\n/**\n  * @brief   EXTI13 configuration\n  */\n#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x00000000)                 /*!<PA[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x00000010)                 /*!<PB[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x00000020)                 /*!<PC[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PD        ((uint32_t)0x00000030)                 /*!<PD[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PE        ((uint32_t)0x00000040)                 /*!<PE[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PF        ((uint32_t)0x00000050)                 /*!<PF[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PG        ((uint32_t)0x00000060)                 /*!<PG[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PH        ((uint32_t)0x00000070)                 /*!<PH[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PI        ((uint32_t)0x00000080)                 /*!<PI[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PJ        ((uint32_t)0x00000090)                 /*!<PJ[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PK        ((uint32_t)0x000000A0)                 /*!<PK[13] pin */\n/**\n  * @brief   EXTI14 configuration\n  */\n#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x00000000)                 /*!<PA[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x00000100)                 /*!<PB[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x00000200)                 /*!<PC[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PD        ((uint32_t)0x00000300)                 /*!<PD[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PE        ((uint32_t)0x00000400)                 /*!<PE[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PF        ((uint32_t)0x00000500)                 /*!<PF[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PG        ((uint32_t)0x00000600)                 /*!<PG[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PH        ((uint32_t)0x00000700)                 /*!<PH[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PI        ((uint32_t)0x00000800)                 /*!<PI[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PJ        ((uint32_t)0x00000900)                 /*!<PJ[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PK        ((uint32_t)0x00000A00)                 /*!<PK[14] pin */\n/**\n  * @brief   EXTI15 configuration\n  */\n#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x00000000)                 /*!<PA[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x00001000)                 /*!<PB[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x00002000)                 /*!<PC[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PD        ((uint32_t)0x00003000)                 /*!<PD[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PE        ((uint32_t)0x00004000)                 /*!<PE[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PF        ((uint32_t)0x00005000)                 /*!<PF[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PG        ((uint32_t)0x00006000)                 /*!<PG[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PH        ((uint32_t)0x00007000)                 /*!<PH[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PI        ((uint32_t)0x00008000)                 /*!<PI[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PJ        ((uint32_t)0x00009000)                 /*!<PJ[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PK        ((uint32_t)0x0000A000)                 /*!<PK[15] pin */\n\n/******************  Bit definition for SYSCFG_CFGR register  ******************/\n#define SYSCFG_CFGR_PVDL_Pos            (2U)\n#define SYSCFG_CFGR_PVDL_Msk            (0x1UL << SYSCFG_CFGR_PVDL_Pos)        /*!< 0x00000004 */\n#define SYSCFG_CFGR_PVDL                SYSCFG_CFGR_PVDL_Msk                   /*!<PVD lock enable bit */\n#define SYSCFG_CFGR_FLASHL_Pos          (3U)\n#define SYSCFG_CFGR_FLASHL_Msk          (0x1UL << SYSCFG_CFGR_FLASHL_Pos)      /*!< 0x00000008 */\n#define SYSCFG_CFGR_FLASHL              SYSCFG_CFGR_FLASHL_Msk                 /*!<FLASH double ECC error lock bit */\n#define SYSCFG_CFGR_CM7L_Pos            (6U)\n#define SYSCFG_CFGR_CM7L_Msk            (0x1UL << SYSCFG_CFGR_CM7L_Pos)        /*!< 0x00000040 */\n#define SYSCFG_CFGR_CM7L                SYSCFG_CFGR_CM7L_Msk                   /*!<Cortex-M7 LOCKUP (Hardfault) output enable bit */\n#define SYSCFG_CFGR_BKRAML_Pos          (7U)\n#define SYSCFG_CFGR_BKRAML_Msk          (0x1UL << SYSCFG_CFGR_BKRAML_Pos)      /*!< 0x00000080 */\n#define SYSCFG_CFGR_BKRAML              SYSCFG_CFGR_BKRAML_Msk                 /*!<Backup SRAM double ECC error lock bit */\n#define SYSCFG_CFGR_SRAM4L_Pos          (9U)\n#define SYSCFG_CFGR_SRAM4L_Msk          (0x1UL << SYSCFG_CFGR_SRAM4L_Pos)      /*!< 0x00000200 */\n#define SYSCFG_CFGR_SRAM4L              SYSCFG_CFGR_SRAM4L_Msk                 /*!<SRAM4 double ECC error lock bit */\n#define SYSCFG_CFGR_SRAM3L_Pos          (10U)\n#define SYSCFG_CFGR_SRAM3L_Msk          (0x1UL << SYSCFG_CFGR_SRAM3L_Pos)      /*!< 0x00000400 */\n#define SYSCFG_CFGR_SRAM3L              SYSCFG_CFGR_SRAM3L_Msk                 /*!<SRAM3 double ECC error lock bit */\n#define SYSCFG_CFGR_SRAM2L_Pos          (11U)\n#define SYSCFG_CFGR_SRAM2L_Msk          (0x1UL << SYSCFG_CFGR_SRAM2L_Pos)      /*!< 0x00000800 */\n#define SYSCFG_CFGR_SRAM2L              SYSCFG_CFGR_SRAM2L_Msk                 /*!<SRAM2 double ECC error lock bit */\n#define SYSCFG_CFGR_SRAM1L_Pos          (12U)\n#define SYSCFG_CFGR_SRAM1L_Msk          (0x1UL << SYSCFG_CFGR_SRAM1L_Pos)      /*!< 0x00001000 */\n#define SYSCFG_CFGR_SRAM1L              SYSCFG_CFGR_SRAM1L_Msk                 /*!<SRAM1 double ECC error lock bit */\n#define SYSCFG_CFGR_DTCML_Pos           (13U)\n#define SYSCFG_CFGR_DTCML_Msk           (0x1UL << SYSCFG_CFGR_DTCML_Pos)       /*!< 0x00002000 */\n#define SYSCFG_CFGR_DTCML               SYSCFG_CFGR_DTCML_Msk                  /*!<DTCM double ECC error lock bit */\n#define SYSCFG_CFGR_ITCML_Pos           (14U)\n#define SYSCFG_CFGR_ITCML_Msk           (0x1UL << SYSCFG_CFGR_ITCML_Pos)       /*!< 0x00004000 */\n#define SYSCFG_CFGR_ITCML               SYSCFG_CFGR_ITCML_Msk                  /*!<ITCM double ECC error lock bit */\n#define SYSCFG_CFGR_AXISRAML_Pos        (15U)\n#define SYSCFG_CFGR_AXISRAML_Msk        (0x1UL << SYSCFG_CFGR_AXISRAML_Pos)    /*!< 0x00008000 */\n#define SYSCFG_CFGR_AXISRAML            SYSCFG_CFGR_AXISRAML_Msk               /*!<AXISRAM double ECC error lock bit */\n\n/******************  Bit definition for SYSCFG_CCCSR register  ******************/\n#define SYSCFG_CCCSR_EN_Pos             (0U)\n#define SYSCFG_CCCSR_EN_Msk             (0x1UL << SYSCFG_CCCSR_EN_Pos)         /*!< 0x00000001 */\n#define SYSCFG_CCCSR_EN                 SYSCFG_CCCSR_EN_Msk                    /*!< I/O compensation cell enable */\n#define SYSCFG_CCCSR_CS_Pos             (1U)\n#define SYSCFG_CCCSR_CS_Msk             (0x1UL << SYSCFG_CCCSR_CS_Pos)         /*!< 0x00000002 */\n#define SYSCFG_CCCSR_CS                 SYSCFG_CCCSR_CS_Msk                    /*!< I/O compensation cell code selection */\n#define SYSCFG_CCCSR_READY_Pos          (8U)\n#define SYSCFG_CCCSR_READY_Msk          (0x1UL << SYSCFG_CCCSR_READY_Pos)      /*!< 0x00000100 */\n#define SYSCFG_CCCSR_READY              SYSCFG_CCCSR_READY_Msk                 /*!< I/O compensation cell ready flag */\n#define SYSCFG_CCCSR_HSLV_Pos           (16U)\n#define SYSCFG_CCCSR_HSLV_Msk           (0x1UL << SYSCFG_CCCSR_HSLV_Pos)       /*!< 0x00010000 */\n#define SYSCFG_CCCSR_HSLV               SYSCFG_CCCSR_HSLV_Msk                  /*!< High-speed at low-voltage */\n\n/******************  Bit definition for SYSCFG_CCVR register  *******************/\n#define SYSCFG_CCVR_NCV_Pos             (0U)\n#define SYSCFG_CCVR_NCV_Msk             (0xFUL << SYSCFG_CCVR_NCV_Pos)         /*!< 0x0000000F */\n#define SYSCFG_CCVR_NCV                 SYSCFG_CCVR_NCV_Msk                    /*!< NMOS compensation value */\n#define SYSCFG_CCVR_PCV_Pos             (4U)\n#define SYSCFG_CCVR_PCV_Msk             (0xFUL << SYSCFG_CCVR_PCV_Pos)         /*!< 0x000000F0 */\n#define SYSCFG_CCVR_PCV                 SYSCFG_CCVR_PCV_Msk                    /*!< PMOS compensation value */\n\n/******************  Bit definition for SYSCFG_CCCR register  *******************/\n#define SYSCFG_CCCR_NCC_Pos             (0U)\n#define SYSCFG_CCCR_NCC_Msk             (0xFUL << SYSCFG_CCCR_NCC_Pos)         /*!< 0x0000000F */\n#define SYSCFG_CCCR_NCC                 SYSCFG_CCCR_NCC_Msk                    /*!< NMOS compensation code */\n#define SYSCFG_CCCR_PCC_Pos             (4U)\n#define SYSCFG_CCCR_PCC_Msk             (0xFUL << SYSCFG_CCCR_PCC_Pos)         /*!< 0x000000F0 */\n#define SYSCFG_CCCR_PCC                 SYSCFG_CCCR_PCC_Msk                    /*!< PMOS compensation code */\n/******************  Bit definition for SYSCFG_PWRCR register  *******************/\n#define SYSCFG_PWRCR_ODEN_Pos           (0U)\n#define SYSCFG_PWRCR_ODEN_Msk           (0x1UL << SYSCFG_PWRCR_ODEN_Pos)         /*!< 0x00000001 */\n#define SYSCFG_PWRCR_ODEN               SYSCFG_PWRCR_ODEN_Msk                    /*!< PWR overdrive enable */\n\n/******************  Bit definition for SYSCFG_PKGR register  *******************/\n#define SYSCFG_PKGR_PKG_Pos             (0U)\n#define SYSCFG_PKGR_PKG_Msk             (0xFUL << SYSCFG_PKGR_PKG_Pos)         /*!< 0x0000000F */\n#define SYSCFG_PKGR_PKG                 SYSCFG_PKGR_PKG_Msk                    /*!< Package type */\n\n/******************  Bit definition for SYSCFG_UR0 register  *******************/\n#define SYSCFG_UR0_BKS_Pos              (0U)\n#define SYSCFG_UR0_BKS_Msk              (0x1UL << SYSCFG_UR0_BKS_Pos)          /*!< 0x00000001 */\n#define SYSCFG_UR0_BKS                  SYSCFG_UR0_BKS_Msk                     /*!< Bank Swap */\n#define SYSCFG_UR0_RDP_Pos              (16U)\n#define SYSCFG_UR0_RDP_Msk              (0xFFUL << SYSCFG_UR0_RDP_Pos)         /*!< 0x00FF0000 */\n#define SYSCFG_UR0_RDP                  SYSCFG_UR0_RDP_Msk                     /*!< Readout protection */\n\n/******************  Bit definition for SYSCFG_UR2 register  *******************/\n#define SYSCFG_UR2_BORH_Pos             (0U)\n#define SYSCFG_UR2_BORH_Msk             (0x3UL << SYSCFG_UR2_BORH_Pos)         /*!< 0x00000003 */\n#define SYSCFG_UR2_BORH                 SYSCFG_UR2_BORH_Msk                    /*!< Brown Out Reset High level */\n#define SYSCFG_UR2_BORH_0               (0x1UL << SYSCFG_UR2_BORH_Pos)         /*!< 0x00000001 */\n#define SYSCFG_UR2_BORH_1               (0x2UL << SYSCFG_UR2_BORH_Pos)         /*!< 0x00000002 */\n#define SYSCFG_UR2_BOOT_ADD0_Pos        (16U)\n#define SYSCFG_UR2_BOOT_ADD0_Msk        (0xFFFFUL << SYSCFG_UR2_BOOT_ADD0_Pos) /*!< 0xFFFF0000 */\n#define SYSCFG_UR2_BOOT_ADD0            SYSCFG_UR2_BOOT_ADD0_Msk               /*!< Core Boot Address 0 */\n/******************  Bit definition for SYSCFG_UR3 register  *******************/\n#define SYSCFG_UR3_BOOT_ADD1_Pos        (0U)\n#define SYSCFG_UR3_BOOT_ADD1_Msk        (0xFFFFUL << SYSCFG_UR3_BOOT_ADD1_Pos) /*!< 0x0000FFFF */\n#define SYSCFG_UR3_BOOT_ADD1            SYSCFG_UR3_BOOT_ADD1_Msk               /*!< Core Boot Address 1 */\n\n  /******************  Bit definition for SYSCFG_UR4 register  *******************/\n\n#define SYSCFG_UR4_MEPAD_BANK1_Pos      (16U)\n#define SYSCFG_UR4_MEPAD_BANK1_Msk      (0x1UL << SYSCFG_UR4_MEPAD_BANK1_Pos)  /*!< 0x00010000 */\n#define SYSCFG_UR4_MEPAD_BANK1          SYSCFG_UR4_MEPAD_BANK1_Msk             /*!< Mass Erase Protected Area Disabled for bank 1 */\n\n/******************  Bit definition for SYSCFG_UR5 register  *******************/\n#define SYSCFG_UR5_MESAD_BANK1_Pos      (0U)\n#define SYSCFG_UR5_MESAD_BANK1_Msk      (0x1UL << SYSCFG_UR5_MESAD_BANK1_Pos)  /*!< 0x00000001 */\n#define SYSCFG_UR5_MESAD_BANK1          SYSCFG_UR5_MESAD_BANK1_Msk             /*!< Mass erase secured area disabled for bank 1 */\n#define SYSCFG_UR5_WRPN_BANK1_Pos       (16U)\n#define SYSCFG_UR5_WRPN_BANK1_Msk       (0xFFUL << SYSCFG_UR5_WRPN_BANK1_Pos)  /*!< 0x00FF0000 */\n#define SYSCFG_UR5_WRPN_BANK1           SYSCFG_UR5_WRPN_BANK1_Msk              /*!< Write protection for flash bank 1 */\n\n/******************  Bit definition for SYSCFG_UR6 register  *******************/\n#define SYSCFG_UR6_PABEG_BANK1_Pos      (0U)\n#define SYSCFG_UR6_PABEG_BANK1_Msk      (0xFFFUL << SYSCFG_UR6_PABEG_BANK1_Pos) /*!< 0x00000FFF */\n#define SYSCFG_UR6_PABEG_BANK1          SYSCFG_UR6_PABEG_BANK1_Msk             /*!< Protected area start address for bank 1 */\n#define SYSCFG_UR6_PAEND_BANK1_Pos      (16U)\n#define SYSCFG_UR6_PAEND_BANK1_Msk      (0xFFFUL << SYSCFG_UR6_PAEND_BANK1_Pos) /*!< 0x0FFF0000 */\n#define SYSCFG_UR6_PAEND_BANK1          SYSCFG_UR6_PAEND_BANK1_Msk             /*!< Protected area end address for bank 1 */\n\n/******************  Bit definition for SYSCFG_UR7 register  *******************/\n#define SYSCFG_UR7_SABEG_BANK1_Pos      (0U)\n#define SYSCFG_UR7_SABEG_BANK1_Msk      (0xFFFUL << SYSCFG_UR7_SABEG_BANK1_Pos) /*!< 0x00000FFF */\n#define SYSCFG_UR7_SABEG_BANK1          SYSCFG_UR7_SABEG_BANK1_Msk             /*!< Secured area start address for bank 1 */\n#define SYSCFG_UR7_SAEND_BANK1_Pos      (16U)\n#define SYSCFG_UR7_SAEND_BANK1_Msk      (0xFFFUL << SYSCFG_UR7_SAEND_BANK1_Pos) /*!< 0x0FFF0000 */\n#define SYSCFG_UR7_SAEND_BANK1          SYSCFG_UR7_SAEND_BANK1_Msk             /*!< Secured area end address for bank 1 */\n\n/******************  Bit definition for SYSCFG_UR8 register  *******************/\n#define SYSCFG_UR8_MEPAD_BANK2_Pos      (0U)\n#define SYSCFG_UR8_MEPAD_BANK2_Msk      (0x1UL << SYSCFG_UR8_MEPAD_BANK2_Pos)  /*!< 0x00000001 */\n#define SYSCFG_UR8_MEPAD_BANK2          SYSCFG_UR8_MEPAD_BANK2_Msk             /*!< Mass erase Protected area disabled for bank 2 */\n#define SYSCFG_UR8_MESAD_BANK2_Pos      (16U)\n#define SYSCFG_UR8_MESAD_BANK2_Msk      (0x1UL << SYSCFG_UR8_MESAD_BANK2_Pos)  /*!< 0x00010000 */\n#define SYSCFG_UR8_MESAD_BANK2          SYSCFG_UR8_MESAD_BANK2_Msk             /*!< Mass Erase Secured Area Disabled for bank 2 */\n\n/******************  Bit definition for SYSCFG_UR9 register  *******************/\n#define SYSCFG_UR9_WRPN_BANK2_Pos       (0U)\n#define SYSCFG_UR9_WRPN_BANK2_Msk       (0xFFUL << SYSCFG_UR9_WRPN_BANK2_Pos)  /*!< 0x000000FF */\n#define SYSCFG_UR9_WRPN_BANK2           SYSCFG_UR9_WRPN_BANK2_Msk              /*!< Write protection for flash bank 2 */\n#define SYSCFG_UR9_PABEG_BANK2_Pos      (16U)\n#define SYSCFG_UR9_PABEG_BANK2_Msk      (0xFFFUL << SYSCFG_UR9_PABEG_BANK2_Pos) /*!< 0x0FFF0000 */\n#define SYSCFG_UR9_PABEG_BANK2          SYSCFG_UR9_PABEG_BANK2_Msk             /*!< Protected area start address for bank 2 */\n\n/******************  Bit definition for SYSCFG_UR10 register  *******************/\n#define SYSCFG_UR10_PAEND_BANK2_Pos     (0U)\n#define SYSCFG_UR10_PAEND_BANK2_Msk     (0xFFFUL << SYSCFG_UR10_PAEND_BANK2_Pos) /*!< 0x00000FFF */\n#define SYSCFG_UR10_PAEND_BANK2         SYSCFG_UR10_PAEND_BANK2_Msk            /*!< Protected area end address for bank 2 */\n#define SYSCFG_UR10_SABEG_BANK2_Pos     (16U)\n#define SYSCFG_UR10_SABEG_BANK2_Msk     (0xFFFUL << SYSCFG_UR10_SABEG_BANK2_Pos) /*!< 0x0FFF0000 */\n#define SYSCFG_UR10_SABEG_BANK2         SYSCFG_UR10_SABEG_BANK2_Msk            /*!< Secured area start address for bank 2 */\n\n/******************  Bit definition for SYSCFG_UR11 register  *******************/\n#define SYSCFG_UR11_SAEND_BANK2_Pos     (0U)\n#define SYSCFG_UR11_SAEND_BANK2_Msk     (0xFFFUL << SYSCFG_UR11_SAEND_BANK2_Pos) /*!< 0x00000FFF */\n#define SYSCFG_UR11_SAEND_BANK2         SYSCFG_UR11_SAEND_BANK2_Msk            /*!< Secured area end address for bank 2 */\n#define SYSCFG_UR11_IWDG1M_Pos          (16U)\n#define SYSCFG_UR11_IWDG1M_Msk          (0x1UL << SYSCFG_UR11_IWDG1M_Pos)      /*!< 0x00010000 */\n#define SYSCFG_UR11_IWDG1M              SYSCFG_UR11_IWDG1M_Msk                 /*!< Independent Watchdog 1 mode (SW or HW) */\n\n/******************  Bit definition for SYSCFG_UR12 register  *******************/\n\n#define SYSCFG_UR12_SECURE_Pos          (16U)\n#define SYSCFG_UR12_SECURE_Msk          (0x1UL << SYSCFG_UR12_SECURE_Pos)      /*!< 0x00010000 */\n#define SYSCFG_UR12_SECURE              SYSCFG_UR12_SECURE_Msk                 /*!< Secure mode status */\n\n/******************  Bit definition for SYSCFG_UR13 register  *******************/\n#define SYSCFG_UR13_SDRS_Pos            (0U)\n#define SYSCFG_UR13_SDRS_Msk            (0x3UL << SYSCFG_UR13_SDRS_Pos)        /*!< 0x00000003 */\n#define SYSCFG_UR13_SDRS                SYSCFG_UR13_SDRS_Msk                   /*!< Secured DTCM RAM Size */\n#define SYSCFG_UR13_D1SBRST_Pos         (16U)\n#define SYSCFG_UR13_D1SBRST_Msk         (0x1UL << SYSCFG_UR13_D1SBRST_Pos)     /*!< 0x00010000 */\n#define SYSCFG_UR13_D1SBRST             SYSCFG_UR13_D1SBRST_Msk                /*!< D1 Standby reset */\n\n/******************  Bit definition for SYSCFG_UR14 register  *******************/\n#define SYSCFG_UR14_D1STPRST_Pos        (0U)\n#define SYSCFG_UR14_D1STPRST_Msk        (0x1UL << SYSCFG_UR14_D1STPRST_Pos)    /*!< 0x00000001 */\n#define SYSCFG_UR14_D1STPRST            SYSCFG_UR14_D1STPRST_Msk               /*!< D1 Stop Reset */\n\n/******************  Bit definition for SYSCFG_UR15 register  *******************/\n#define SYSCFG_UR15_FZIWDGSTB_Pos       (16U)\n#define SYSCFG_UR15_FZIWDGSTB_Msk       (0x1UL << SYSCFG_UR15_FZIWDGSTB_Pos)   /*!< 0x00010000 */\n#define SYSCFG_UR15_FZIWDGSTB           SYSCFG_UR15_FZIWDGSTB_Msk              /*!< Freeze independent watchdogs in Standby mode */\n\n/******************  Bit definition for SYSCFG_UR16 register  *******************/\n#define SYSCFG_UR16_FZIWDGSTP_Pos       (0U)\n#define SYSCFG_UR16_FZIWDGSTP_Msk       (0x1UL << SYSCFG_UR16_FZIWDGSTP_Pos)   /*!< 0x00000001 */\n#define SYSCFG_UR16_FZIWDGSTP           SYSCFG_UR16_FZIWDGSTP_Msk              /*!< Freeze independent watchdogs in Stop mode */\n#define SYSCFG_UR16_PKP_Pos             (16U)\n#define SYSCFG_UR16_PKP_Msk             (0x1UL << SYSCFG_UR16_PKP_Pos)         /*!< 0x00010000 */\n#define SYSCFG_UR16_PKP                 SYSCFG_UR16_PKP_Msk                    /*!< Private key programmed */\n\n/******************  Bit definition for SYSCFG_UR17 register  *******************/\n#define SYSCFG_UR17_IOHSLV_Pos          (0U)\n#define SYSCFG_UR17_IOHSLV_Msk          (0x1UL << SYSCFG_UR17_IOHSLV_Pos)      /*!< 0x00000001 */\n#define SYSCFG_UR17_IOHSLV              SYSCFG_UR17_IOHSLV_Msk                 /*!< I/O high speed / low voltage */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                                    TIM                                     */\n/*                                                                            */\n/******************************************************************************/\n#define TIM_BREAK_INPUT_SUPPORT             /*!<TIM Break input feature */\n\n/*******************  Bit definition for TIM_CR1 register  ********************/\n#define TIM_CR1_CEN_Pos           (0U)\n#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                   /*!< 0x00000001 */\n#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */\n#define TIM_CR1_UDIS_Pos          (1U)\n#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                  /*!< 0x00000002 */\n#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */\n#define TIM_CR1_URS_Pos           (2U)\n#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                   /*!< 0x00000004 */\n#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */\n#define TIM_CR1_OPM_Pos           (3U)\n#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                   /*!< 0x00000008 */\n#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */\n#define TIM_CR1_DIR_Pos           (4U)\n#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                   /*!< 0x00000010 */\n#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */\n\n#define TIM_CR1_CMS_Pos           (5U)\n#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000060 */\n#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */\n#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */\n#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */\n\n#define TIM_CR1_ARPE_Pos          (7U)\n#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                  /*!< 0x00000080 */\n#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */\n\n#define TIM_CR1_CKD_Pos           (8U)\n#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000300 */\n#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */\n#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */\n#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */\n\n#define TIM_CR1_UIFREMAP_Pos      (11U)\n#define TIM_CR1_UIFREMAP_Msk      (0x1UL << TIM_CR1_UIFREMAP_Pos)              /*!< 0x00000800 */\n#define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<Update interrupt flag remap */\n\n/*******************  Bit definition for TIM_CR2 register  ********************/\n#define TIM_CR2_CCPC_Pos          (0U)\n#define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                  /*!< 0x00000001 */\n#define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */\n#define TIM_CR2_CCUS_Pos          (2U)\n#define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                  /*!< 0x00000004 */\n#define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */\n#define TIM_CR2_CCDS_Pos          (3U)\n#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                  /*!< 0x00000008 */\n#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */\n\n#define TIM_CR2_MMS_Pos           (4U)\n#define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000070 */\n#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */\n#define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */\n#define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */\n#define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */\n\n#define TIM_CR2_TI1S_Pos          (7U)\n#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                  /*!< 0x00000080 */\n#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */\n#define TIM_CR2_OIS1_Pos          (8U)\n#define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                  /*!< 0x00000100 */\n#define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */\n#define TIM_CR2_OIS1N_Pos         (9U)\n#define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                 /*!< 0x00000200 */\n#define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */\n#define TIM_CR2_OIS2_Pos          (10U)\n#define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                  /*!< 0x00000400 */\n#define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */\n#define TIM_CR2_OIS2N_Pos         (11U)\n#define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                 /*!< 0x00000800 */\n#define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */\n#define TIM_CR2_OIS3_Pos          (12U)\n#define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                  /*!< 0x00001000 */\n#define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */\n#define TIM_CR2_OIS3N_Pos         (13U)\n#define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                 /*!< 0x00002000 */\n#define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */\n#define TIM_CR2_OIS4_Pos          (14U)\n#define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                  /*!< 0x00004000 */\n#define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */\n#define TIM_CR2_OIS5_Pos          (16U)\n#define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */\n#define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 4 (OC4 output) */\n#define TIM_CR2_OIS6_Pos          (18U)\n#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00040000 */\n#define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 4 (OC4 output) */\n\n#define TIM_CR2_MMS2_Pos          (20U)\n#define TIM_CR2_MMS2_Msk          (0xFUL << TIM_CR2_MMS2_Pos)                  /*!< 0x00F00000 */\n#define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */\n#define TIM_CR2_MMS2_0            (0x1UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00100000 */\n#define TIM_CR2_MMS2_1            (0x2UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00200000 */\n#define TIM_CR2_MMS2_2            (0x4UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00400000 */\n#define TIM_CR2_MMS2_3            (0x8UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00800000 */\n\n/*******************  Bit definition for TIM_SMCR register  *******************/\n#define TIM_SMCR_SMS_Pos          (0U)\n#define TIM_SMCR_SMS_Msk          (0x10007UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010007 */\n#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */\n#define TIM_SMCR_SMS_0            (0x00001UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000001 */\n#define TIM_SMCR_SMS_1            (0x00002UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000002 */\n#define TIM_SMCR_SMS_2            (0x00004UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000004 */\n#define TIM_SMCR_SMS_3            (0x10000UL << TIM_SMCR_SMS_Pos)               /*!< 0x00010000 */\n\n#define TIM_SMCR_TS_Pos           (4U)\n#define TIM_SMCR_TS_Msk           (0x30007UL << TIM_SMCR_TS_Pos)               /*!< 0x00300070 */\n#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[4:0] bits (Trigger selection) */\n#define TIM_SMCR_TS_0             (0x00001UL << TIM_SMCR_TS_Pos)                /*!< 0x00000010 */\n#define TIM_SMCR_TS_1             (0x00002UL << TIM_SMCR_TS_Pos)                /*!< 0x00000020 */\n#define TIM_SMCR_TS_2             (0x00004UL << TIM_SMCR_TS_Pos)                /*!< 0x00000040 */\n#define TIM_SMCR_TS_3             (0x10000UL << TIM_SMCR_TS_Pos)                /*!< 0x00100000 */\n#define TIM_SMCR_TS_4             (0x20000UL << TIM_SMCR_TS_Pos)                /*!< 0x00200000 */\n\n#define TIM_SMCR_MSM_Pos          (7U)\n#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                  /*!< 0x00000080 */\n#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */\n\n#define TIM_SMCR_ETF_Pos          (8U)\n#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000F00 */\n#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */\n#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */\n#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */\n#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */\n#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */\n\n#define TIM_SMCR_ETPS_Pos         (12U)\n#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00003000 */\n#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */\n#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */\n#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */\n\n#define TIM_SMCR_ECE_Pos          (14U)\n#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                  /*!< 0x00004000 */\n#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */\n#define TIM_SMCR_ETP_Pos          (15U)\n#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                  /*!< 0x00008000 */\n#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */\n\n/*******************  Bit definition for TIM_DIER register  *******************/\n#define TIM_DIER_UIE_Pos          (0U)\n#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                  /*!< 0x00000001 */\n#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */\n#define TIM_DIER_CC1IE_Pos        (1U)\n#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                /*!< 0x00000002 */\n#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */\n#define TIM_DIER_CC2IE_Pos        (2U)\n#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                /*!< 0x00000004 */\n#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */\n#define TIM_DIER_CC3IE_Pos        (3U)\n#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                /*!< 0x00000008 */\n#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */\n#define TIM_DIER_CC4IE_Pos        (4U)\n#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                /*!< 0x00000010 */\n#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */\n#define TIM_DIER_COMIE_Pos        (5U)\n#define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                /*!< 0x00000020 */\n#define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */\n#define TIM_DIER_TIE_Pos          (6U)\n#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                  /*!< 0x00000040 */\n#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */\n#define TIM_DIER_BIE_Pos          (7U)\n#define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                  /*!< 0x00000080 */\n#define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */\n#define TIM_DIER_UDE_Pos          (8U)\n#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                  /*!< 0x00000100 */\n#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */\n#define TIM_DIER_CC1DE_Pos        (9U)\n#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                /*!< 0x00000200 */\n#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */\n#define TIM_DIER_CC2DE_Pos        (10U)\n#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                /*!< 0x00000400 */\n#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */\n#define TIM_DIER_CC3DE_Pos        (11U)\n#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                /*!< 0x00000800 */\n#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */\n#define TIM_DIER_CC4DE_Pos        (12U)\n#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                /*!< 0x00001000 */\n#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */\n#define TIM_DIER_COMDE_Pos        (13U)\n#define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                /*!< 0x00002000 */\n#define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */\n#define TIM_DIER_TDE_Pos          (14U)\n#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                  /*!< 0x00004000 */\n#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */\n\n/********************  Bit definition for TIM_SR register  ********************/\n#define TIM_SR_UIF_Pos            (0U)\n#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                    /*!< 0x00000001 */\n#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */\n#define TIM_SR_CC1IF_Pos          (1U)\n#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                  /*!< 0x00000002 */\n#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */\n#define TIM_SR_CC2IF_Pos          (2U)\n#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                  /*!< 0x00000004 */\n#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */\n#define TIM_SR_CC3IF_Pos          (3U)\n#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                  /*!< 0x00000008 */\n#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */\n#define TIM_SR_CC4IF_Pos          (4U)\n#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                  /*!< 0x00000010 */\n#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */\n#define TIM_SR_COMIF_Pos          (5U)\n#define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                  /*!< 0x00000020 */\n#define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */\n#define TIM_SR_TIF_Pos            (6U)\n#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                    /*!< 0x00000040 */\n#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */\n#define TIM_SR_BIF_Pos            (7U)\n#define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                    /*!< 0x00000080 */\n#define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */\n#define TIM_SR_B2IF_Pos           (8U)\n#define TIM_SR_B2IF_Msk           (0x1UL << TIM_SR_B2IF_Pos)                   /*!< 0x00000100 */\n#define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break2 interrupt Flag */\n#define TIM_SR_CC1OF_Pos          (9U)\n#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                  /*!< 0x00000200 */\n#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */\n#define TIM_SR_CC2OF_Pos          (10U)\n#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                  /*!< 0x00000400 */\n#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */\n#define TIM_SR_CC3OF_Pos          (11U)\n#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                  /*!< 0x00000800 */\n#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */\n#define TIM_SR_CC4OF_Pos          (12U)\n#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                  /*!< 0x00001000 */\n#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */\n#define TIM_SR_CC5IF_Pos          (16U)\n#define TIM_SR_CC5IF_Msk          (0x1UL << TIM_SR_CC5IF_Pos)                  /*!< 0x00010000 */\n#define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */\n#define TIM_SR_CC6IF_Pos          (17U)\n#define TIM_SR_CC6IF_Msk          (0x1UL << TIM_SR_CC6IF_Pos)                  /*!< 0x00020000 */\n#define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */\n#define TIM_SR_SBIF_Pos           (13U)\n#define TIM_SR_SBIF_Msk           (0x1UL << TIM_SR_SBIF_Pos)                   /*!< 0x00002000 */\n#define TIM_SR_SBIF               TIM_SR_SBIF_Msk                              /*!< System Break Flag */\n\n/*******************  Bit definition for TIM_EGR register  ********************/\n#define TIM_EGR_UG_Pos            (0U)\n#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                    /*!< 0x00000001 */\n#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */\n#define TIM_EGR_CC1G_Pos          (1U)\n#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                  /*!< 0x00000002 */\n#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */\n#define TIM_EGR_CC2G_Pos          (2U)\n#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                  /*!< 0x00000004 */\n#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */\n#define TIM_EGR_CC3G_Pos          (3U)\n#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                  /*!< 0x00000008 */\n#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */\n#define TIM_EGR_CC4G_Pos          (4U)\n#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                  /*!< 0x00000010 */\n#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */\n#define TIM_EGR_COMG_Pos          (5U)\n#define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                  /*!< 0x00000020 */\n#define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */\n#define TIM_EGR_TG_Pos            (6U)\n#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                    /*!< 0x00000040 */\n#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */\n#define TIM_EGR_BG_Pos            (7U)\n#define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                    /*!< 0x00000080 */\n#define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */\n#define TIM_EGR_B2G_Pos           (8U)\n#define TIM_EGR_B2G_Msk           (0x1UL << TIM_EGR_B2G_Pos)                   /*!< 0x00000100 */\n#define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break Generation */\n\n\n/******************  Bit definition for TIM_CCMR1 register  *******************/\n#define TIM_CCMR1_CC1S_Pos        (0U)\n#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000003 */\n#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */\n#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */\n#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */\n\n#define TIM_CCMR1_OC1FE_Pos       (2U)\n#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)               /*!< 0x00000004 */\n#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */\n#define TIM_CCMR1_OC1PE_Pos       (3U)\n#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)               /*!< 0x00000008 */\n#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */\n\n#define TIM_CCMR1_OC1M_Pos        (4U)\n#define TIM_CCMR1_OC1M_Msk        (0x1007UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010070 */\n#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */\n#define TIM_CCMR1_OC1M_0          (0x0001UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000010 */\n#define TIM_CCMR1_OC1M_1          (0x0002UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000020 */\n#define TIM_CCMR1_OC1M_2          (0x0004UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000040 */\n#define TIM_CCMR1_OC1M_3          (0x1000UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00010000 */\n\n#define TIM_CCMR1_OC1CE_Pos       (7U)\n#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)               /*!< 0x00000080 */\n#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable */\n\n#define TIM_CCMR1_CC2S_Pos        (8U)\n#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000300 */\n#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */\n#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */\n#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */\n\n#define TIM_CCMR1_OC2FE_Pos       (10U)\n#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)               /*!< 0x00000400 */\n#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */\n#define TIM_CCMR1_OC2PE_Pos       (11U)\n#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)               /*!< 0x00000800 */\n#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */\n\n#define TIM_CCMR1_OC2M_Pos        (12U)\n#define TIM_CCMR1_OC2M_Msk        (0x1007UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01007000 */\n#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */\n#define TIM_CCMR1_OC2M_0          (0x0001UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00001000 */\n#define TIM_CCMR1_OC2M_1          (0x0002UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00002000 */\n#define TIM_CCMR1_OC2M_2          (0x0004UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00004000 */\n#define TIM_CCMR1_OC2M_3          (0x1000UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x01000000 */\n\n#define TIM_CCMR1_OC2CE_Pos       (15U)\n#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)               /*!< 0x00008000 */\n#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */\n\n/*----------------------------------------------------------------------------*/\n\n#define TIM_CCMR1_IC1PSC_Pos      (2U)\n#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x0000000C */\n#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */\n#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */\n#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */\n\n#define TIM_CCMR1_IC1F_Pos        (4U)\n#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                /*!< 0x000000F0 */\n#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */\n#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */\n#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */\n#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */\n#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */\n\n#define TIM_CCMR1_IC2PSC_Pos      (10U)\n#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000C00 */\n#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */\n#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */\n#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */\n\n#define TIM_CCMR1_IC2F_Pos        (12U)\n#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                /*!< 0x0000F000 */\n#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */\n#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */\n#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */\n#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */\n#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */\n\n/******************  Bit definition for TIM_CCMR2 register  *******************/\n#define TIM_CCMR2_CC3S_Pos        (0U)\n#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000003 */\n#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */\n#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */\n#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */\n\n#define TIM_CCMR2_OC3FE_Pos       (2U)\n#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)               /*!< 0x00000004 */\n#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */\n#define TIM_CCMR2_OC3PE_Pos       (3U)\n#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)               /*!< 0x00000008 */\n#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */\n\n#define TIM_CCMR2_OC3M_Pos        (4U)\n#define TIM_CCMR2_OC3M_Msk        (0x1007UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00010070 */\n#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[3:0] bits (Output Compare 3 Mode) */\n#define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */\n#define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */\n#define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */\n#define TIM_CCMR2_OC3M_3          (0x1000UL << TIM_CCMR2_OC3M_Pos)              /*!< 0x00010000 */\n\n#define TIM_CCMR2_OC3CE_Pos       (7U)\n#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)               /*!< 0x00000080 */\n#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */\n\n#define TIM_CCMR2_CC4S_Pos        (8U)\n#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000300 */\n#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */\n#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */\n#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */\n\n#define TIM_CCMR2_OC4FE_Pos       (10U)\n#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)               /*!< 0x00000400 */\n#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */\n#define TIM_CCMR2_OC4PE_Pos       (11U)\n#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)               /*!< 0x00000800 */\n#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */\n\n#define TIM_CCMR2_OC4M_Pos        (12U)\n#define TIM_CCMR2_OC4M_Msk        (0x1007UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x01007000 */\n#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[3:0] bits (Output Compare 4 Mode) */\n#define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */\n#define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */\n#define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */\n#define TIM_CCMR2_OC4M_3          (0x1000UL << TIM_CCMR2_OC4M_Pos)              /*!< 0x01000000 */\n\n#define TIM_CCMR2_OC4CE_Pos       (15U)\n#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */\n#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */\n\n/*----------------------------------------------------------------------------*/\n\n#define TIM_CCMR2_IC3PSC_Pos      (2U)\n#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x0000000C */\n#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */\n#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */\n#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */\n\n#define TIM_CCMR2_IC3F_Pos        (4U)\n#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                /*!< 0x000000F0 */\n#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */\n#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */\n#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */\n#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */\n#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */\n\n#define TIM_CCMR2_IC4PSC_Pos      (10U)\n#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000C00 */\n#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */\n#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */\n#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */\n\n#define TIM_CCMR2_IC4F_Pos        (12U)\n#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                /*!< 0x0000F000 */\n#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */\n#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */\n#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */\n#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */\n#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */\n\n/*******************  Bit definition for TIM_CCER register  *******************/\n#define TIM_CCER_CC1E_Pos         (0U)\n#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                 /*!< 0x00000001 */\n#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */\n#define TIM_CCER_CC1P_Pos         (1U)\n#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                 /*!< 0x00000002 */\n#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */\n#define TIM_CCER_CC1NE_Pos        (2U)\n#define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                /*!< 0x00000004 */\n#define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */\n#define TIM_CCER_CC1NP_Pos        (3U)\n#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                /*!< 0x00000008 */\n#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */\n#define TIM_CCER_CC2E_Pos         (4U)\n#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                 /*!< 0x00000010 */\n#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */\n#define TIM_CCER_CC2P_Pos         (5U)\n#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                 /*!< 0x00000020 */\n#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */\n#define TIM_CCER_CC2NE_Pos        (6U)\n#define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                /*!< 0x00000040 */\n#define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */\n#define TIM_CCER_CC2NP_Pos        (7U)\n#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                /*!< 0x00000080 */\n#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */\n#define TIM_CCER_CC3E_Pos         (8U)\n#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                 /*!< 0x00000100 */\n#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */\n#define TIM_CCER_CC3P_Pos         (9U)\n#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                 /*!< 0x00000200 */\n#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */\n#define TIM_CCER_CC3NE_Pos        (10U)\n#define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                /*!< 0x00000400 */\n#define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */\n#define TIM_CCER_CC3NP_Pos        (11U)\n#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                /*!< 0x00000800 */\n#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */\n#define TIM_CCER_CC4E_Pos         (12U)\n#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                 /*!< 0x00001000 */\n#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */\n#define TIM_CCER_CC4P_Pos         (13U)\n#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                 /*!< 0x00002000 */\n#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */\n#define TIM_CCER_CC4NP_Pos        (15U)\n#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                /*!< 0x00008000 */\n#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */\n#define TIM_CCER_CC5E_Pos         (16U)\n#define TIM_CCER_CC5E_Msk         (0x1UL << TIM_CCER_CC5E_Pos)                 /*!< 0x00010000 */\n#define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */\n#define TIM_CCER_CC5P_Pos         (17U)\n#define TIM_CCER_CC5P_Msk         (0x1UL << TIM_CCER_CC5P_Pos)                 /*!< 0x00020000 */\n#define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */\n#define TIM_CCER_CC6E_Pos         (20U)\n#define TIM_CCER_CC6E_Msk         (0x1UL << TIM_CCER_CC6E_Pos)                 /*!< 0x00100000 */\n#define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */\n#define TIM_CCER_CC6P_Pos         (21U)\n#define TIM_CCER_CC6P_Msk         (0x1UL << TIM_CCER_CC6P_Pos)                 /*!< 0x00200000 */\n#define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */\n/*******************  Bit definition for TIM_CNT register  ********************/\n#define TIM_CNT_CNT_Pos           (0U)\n#define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)            /*!< 0xFFFFFFFF */\n#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */\n#define TIM_CNT_UIFCPY_Pos        (31U)\n#define TIM_CNT_UIFCPY_Msk        (0x1UL << TIM_CNT_UIFCPY_Pos)                /*!< 0x80000000 */\n#define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy */\n/*******************  Bit definition for TIM_PSC register  ********************/\n#define TIM_PSC_PSC_Pos           (0U)\n#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                /*!< 0x0000FFFF */\n#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */\n\n/*******************  Bit definition for TIM_ARR register  ********************/\n#define TIM_ARR_ARR_Pos           (0U)\n#define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)            /*!< 0xFFFFFFFF */\n#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */\n\n/*******************  Bit definition for TIM_RCR register  ********************/\n#define TIM_RCR_REP_Pos           (0U)\n#define TIM_RCR_REP_Msk           (0xFFUL << TIM_RCR_REP_Pos)                  /*!< 0x000000FF */\n#define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */\n\n/*******************  Bit definition for TIM_CCR1 register  *******************/\n#define TIM_CCR1_CCR1_Pos         (0U)\n#define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)              /*!< 0x0000FFFF */\n#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */\n\n/*******************  Bit definition for TIM_CCR2 register  *******************/\n#define TIM_CCR2_CCR2_Pos         (0U)\n#define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)              /*!< 0x0000FFFF */\n#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */\n\n/*******************  Bit definition for TIM_CCR3 register  *******************/\n#define TIM_CCR3_CCR3_Pos         (0U)\n#define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)              /*!< 0x0000FFFF */\n#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */\n\n/*******************  Bit definition for TIM_CCR4 register  *******************/\n#define TIM_CCR4_CCR4_Pos         (0U)\n#define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)              /*!< 0x0000FFFF */\n#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */\n\n/*******************  Bit definition for TIM_CCR5 register  *******************/\n#define TIM_CCR5_CCR5_Pos         (0U)\n#define TIM_CCR5_CCR5_Msk         (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)          /*!< 0xFFFFFFFF */\n#define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */\n#define TIM_CCR5_GC5C1_Pos        (29U)\n#define TIM_CCR5_GC5C1_Msk        (0x1UL << TIM_CCR5_GC5C1_Pos)                /*!< 0x20000000 */\n#define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */\n#define TIM_CCR5_GC5C2_Pos        (30U)\n#define TIM_CCR5_GC5C2_Msk        (0x1UL << TIM_CCR5_GC5C2_Pos)                /*!< 0x40000000 */\n#define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */\n#define TIM_CCR5_GC5C3_Pos        (31U)\n#define TIM_CCR5_GC5C3_Msk        (0x1UL << TIM_CCR5_GC5C3_Pos)                /*!< 0x80000000 */\n#define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */\n\n/*******************  Bit definition for TIM_CCR6 register  *******************/\n#define TIM_CCR6_CCR6_Pos         (0U)\n#define TIM_CCR6_CCR6_Msk         (0xFFFFUL << TIM_CCR6_CCR6_Pos)              /*!< 0x0000FFFF */\n#define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */\n\n/*******************  Bit definition for TIM_BDTR register  *******************/\n#define TIM_BDTR_DTG_Pos          (0U)\n#define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                 /*!< 0x000000FF */\n#define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */\n#define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000001 */\n#define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000002 */\n#define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000004 */\n#define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000008 */\n#define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000010 */\n#define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000020 */\n#define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000040 */\n#define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000080 */\n\n#define TIM_BDTR_LOCK_Pos         (8U)\n#define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000300 */\n#define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */\n#define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000100 */\n#define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000200 */\n\n#define TIM_BDTR_OSSI_Pos         (10U)\n#define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                 /*!< 0x00000400 */\n#define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */\n#define TIM_BDTR_OSSR_Pos         (11U)\n#define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                 /*!< 0x00000800 */\n#define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */\n#define TIM_BDTR_BKE_Pos          (12U)\n#define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                  /*!< 0x00001000 */\n#define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break1 */\n#define TIM_BDTR_BKP_Pos          (13U)\n#define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                  /*!< 0x00002000 */\n#define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break1 */\n#define TIM_BDTR_AOE_Pos          (14U)\n#define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                  /*!< 0x00004000 */\n#define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */\n#define TIM_BDTR_MOE_Pos          (15U)\n#define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                  /*!< 0x00008000 */\n#define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */\n\n#define TIM_BDTR_BKF_Pos          (16U)\n#define TIM_BDTR_BKF_Msk          (0xFUL << TIM_BDTR_BKF_Pos)                  /*!< 0x000F0000 */\n#define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break1 */\n#define TIM_BDTR_BK2F_Pos         (20U)\n#define TIM_BDTR_BK2F_Msk         (0xFUL << TIM_BDTR_BK2F_Pos)                 /*!< 0x00F00000 */\n#define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break2 */\n\n#define TIM_BDTR_BK2E_Pos         (24U)\n#define TIM_BDTR_BK2E_Msk         (0x1UL << TIM_BDTR_BK2E_Pos)                 /*!< 0x01000000 */\n#define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break2 */\n#define TIM_BDTR_BK2P_Pos         (25U)\n#define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                 /*!< 0x02000000 */\n#define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break2 */\n\n/*******************  Bit definition for TIM_DCR register  ********************/\n#define TIM_DCR_DBA_Pos           (0U)\n#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                  /*!< 0x0000001F */\n#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */\n#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */\n#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */\n#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */\n#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */\n#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */\n\n#define TIM_DCR_DBL_Pos           (8U)\n#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                  /*!< 0x00001F00 */\n#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */\n#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */\n#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */\n#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */\n#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */\n#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */\n\n/*******************  Bit definition for TIM_DMAR register  *******************/\n#define TIM_DMAR_DMAB_Pos         (0U)\n#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)              /*!< 0x0000FFFF */\n#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */\n\n/******************  Bit definition for TIM_CCMR3 register  *******************/\n#define TIM_CCMR3_OC5FE_Pos       (2U)\n#define TIM_CCMR3_OC5FE_Msk       (0x1UL << TIM_CCMR3_OC5FE_Pos)               /*!< 0x00000004 */\n#define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */\n#define TIM_CCMR3_OC5PE_Pos       (3U)\n#define TIM_CCMR3_OC5PE_Msk       (0x1UL << TIM_CCMR3_OC5PE_Pos)               /*!< 0x00000008 */\n#define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */\n\n#define TIM_CCMR3_OC5M_Pos        (4U)\n#define TIM_CCMR3_OC5M_Msk        (0x1007UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00010070 */\n#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[3:0] bits (Output Compare 5 Mode) */\n#define TIM_CCMR3_OC5M_0          (0x1UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000010 */\n#define TIM_CCMR3_OC5M_1          (0x2UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000020 */\n#define TIM_CCMR3_OC5M_2          (0x4UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000040 */\n#define TIM_CCMR3_OC5M_3          (0x1000UL << TIM_CCMR3_OC5M_Pos)              /*!< 0x00010000 */\n\n#define TIM_CCMR3_OC5CE_Pos       (7U)\n#define TIM_CCMR3_OC5CE_Msk       (0x1UL << TIM_CCMR3_OC5CE_Pos)               /*!< 0x00000080 */\n#define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */\n\n#define TIM_CCMR3_OC6FE_Pos       (10U)\n#define TIM_CCMR3_OC6FE_Msk       (0x1UL << TIM_CCMR3_OC6FE_Pos)               /*!< 0x00000400 */\n#define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 4 Fast enable */\n#define TIM_CCMR3_OC6PE_Pos       (11U)\n#define TIM_CCMR3_OC6PE_Msk       (0x1UL << TIM_CCMR3_OC6PE_Pos)               /*!< 0x00000800 */\n#define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 4 Preload enable */\n\n#define TIM_CCMR3_OC6M_Pos        (12U)\n#define TIM_CCMR3_OC6M_Msk        (0x1007UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x01007000 */\n#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[3:0] bits (Output Compare 4 Mode) */\n#define TIM_CCMR3_OC6M_0          (0x1UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00001000 */\n#define TIM_CCMR3_OC6M_1          (0x2UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00002000 */\n#define TIM_CCMR3_OC6M_2          (0x4UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00004000 */\n#define TIM_CCMR3_OC6M_3          (0x1000UL << TIM_CCMR3_OC6M_Pos)              /*!< 0x01000000 */\n\n#define TIM_CCMR3_OC6CE_Pos       (15U)\n#define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */\n#define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 4 Clear Enable */\n/*******************  Bit definition for TIM1_AF1 register  *********************/\n#define TIM1_AF1_BKINE_Pos        (0U)\n#define TIM1_AF1_BKINE_Msk        (0x1UL << TIM1_AF1_BKINE_Pos)                /*!< 0x00000001 */\n#define TIM1_AF1_BKINE            TIM1_AF1_BKINE_Msk                           /*!<BKINE Break input enable bit */\n#define TIM1_AF1_BKCMP1E_Pos      (1U)\n#define TIM1_AF1_BKCMP1E_Msk      (0x1UL << TIM1_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */\n#define TIM1_AF1_BKCMP1E          TIM1_AF1_BKCMP1E_Msk                         /*!<BKCMP1E Break Compare1 Enable bit */\n#define TIM1_AF1_BKCMP2E_Pos      (2U)\n#define TIM1_AF1_BKCMP2E_Msk      (0x1UL << TIM1_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */\n#define TIM1_AF1_BKCMP2E          TIM1_AF1_BKCMP2E_Msk                         /*!<BKCMP1E Break Compare2 Enable bit */\n#define TIM1_AF1_BKDF1BK0E_Pos    (8U)\n#define TIM1_AF1_BKDF1BK0E_Msk    (0x1UL << TIM1_AF1_BKDF1BK0E_Pos)            /*!< 0x00000100 */\n#define TIM1_AF1_BKDF1BK0E        TIM1_AF1_BKDF1BK0E_Msk                       /*!<BKDF1BK0E Break input DFSDM Break 0 */\n#define TIM1_AF1_BKINP_Pos        (9U)\n#define TIM1_AF1_BKINP_Msk        (0x1UL << TIM1_AF1_BKINP_Pos)                /*!< 0x00000200 */\n#define TIM1_AF1_BKINP            TIM1_AF1_BKINP_Msk                           /*!<BRKINP Break input polarity */\n#define TIM1_AF1_BKCMP1P_Pos      (10U)\n#define TIM1_AF1_BKCMP1P_Msk      (0x1UL << TIM1_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */\n#define TIM1_AF1_BKCMP1P          TIM1_AF1_BKCMP1P_Msk                         /*!<BKCMP1P Break COMP1 input polarity */\n#define TIM1_AF1_BKCMP2P_Pos      (11U)\n#define TIM1_AF1_BKCMP2P_Msk      (0x1UL << TIM1_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */\n#define TIM1_AF1_BKCMP2P          TIM1_AF1_BKCMP2P_Msk                         /*!<BKCMP2P Break COMP2 input polarity */\n\n#define TIM1_AF1_ETRSEL_Pos       (14U)\n#define TIM1_AF1_ETRSEL_Msk       (0xFUL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */\n#define TIM1_AF1_ETRSEL           TIM1_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM1 ETRSEL) */\n#define TIM1_AF1_ETRSEL_0         (0x1UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00004000 */\n#define TIM1_AF1_ETRSEL_1         (0x2UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00008000 */\n#define TIM1_AF1_ETRSEL_2         (0x4UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00010000 */\n#define TIM1_AF1_ETRSEL_3         (0x8UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00020000 */\n\n/*******************  Bit definition for TIM1_AF2 register  *********************/\n#define TIM1_AF2_BK2INE_Pos       (0U)\n#define TIM1_AF2_BK2INE_Msk       (0x1UL << TIM1_AF2_BK2INE_Pos)               /*!< 0x00000001 */\n#define TIM1_AF2_BK2INE           TIM1_AF2_BK2INE_Msk                          /*!<BK2INE Break input 2 enable bit */\n#define TIM1_AF2_BK2CMP1E_Pos     (1U)\n#define TIM1_AF2_BK2CMP1E_Msk     (0x1UL << TIM1_AF2_BK2CMP1E_Pos)             /*!< 0x00000002 */\n#define TIM1_AF2_BK2CMP1E         TIM1_AF2_BK2CMP1E_Msk                        /*!<BK2CMP1E Break2 Compare1 Enable bit */\n#define TIM1_AF2_BK2CMP2E_Pos     (2U)\n#define TIM1_AF2_BK2CMP2E_Msk     (0x1UL << TIM1_AF2_BK2CMP2E_Pos)             /*!< 0x00000004 */\n#define TIM1_AF2_BK2CMP2E         TIM1_AF2_BK2CMP2E_Msk                        /*!<BK2CMP1E Break2 Compare2 Enable bit  */\n#define TIM1_AF2_BK2DFBK1E_Pos    (8U)\n#define TIM1_AF2_BK2DFBK1E_Msk    (0x1UL << TIM1_AF2_BK2DFBK1E_Pos)            /*!< 0x00000100 */\n#define TIM1_AF2_BK2DFBK1E        TIM1_AF2_BK2DFBK1E_Msk                       /*!<BK2DFBK1E Break input2 DFSDM Break 1 */\n#define TIM1_AF2_BK2INP_Pos       (9U)\n#define TIM1_AF2_BK2INP_Msk       (0x1UL << TIM1_AF2_BK2INP_Pos)               /*!< 0x00000200 */\n#define TIM1_AF2_BK2INP           TIM1_AF2_BK2INP_Msk                          /*!<BRKINP Break2 input polarity */\n#define TIM1_AF2_BK2CMP1P_Pos     (10U)\n#define TIM1_AF2_BK2CMP1P_Msk     (0x1UL << TIM1_AF2_BK2CMP1P_Pos)             /*!< 0x00000400 */\n#define TIM1_AF2_BK2CMP1P         TIM1_AF2_BK2CMP1P_Msk                        /*!<BKCMP1P Break2 COMP1 input polarity */\n#define TIM1_AF2_BK2CMP2P_Pos     (11U)\n#define TIM1_AF2_BK2CMP2P_Msk     (0x1UL << TIM1_AF2_BK2CMP2P_Pos)             /*!< 0x00000800 */\n#define TIM1_AF2_BK2CMP2P         TIM1_AF2_BK2CMP2P_Msk                        /*!<BKCMP2P Break2 COMP2 input polarity */\n\n/*******************  Bit definition for TIM_TISEL register  *********************/\n#define TIM_TISEL_TI1SEL_Pos      (0U)\n#define TIM_TISEL_TI1SEL_Msk      (0xFUL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x0000000F */\n#define TIM_TISEL_TI1SEL          TIM_TISEL_TI1SEL_Msk                         /*!<TI1SEL[3:0] bits (TIM TI1 SEL)*/\n#define TIM_TISEL_TI1SEL_0        (0x1UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000001 */\n#define TIM_TISEL_TI1SEL_1        (0x2UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000002 */\n#define TIM_TISEL_TI1SEL_2        (0x4UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000004 */\n#define TIM_TISEL_TI1SEL_3        (0x8UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000008 */\n\n#define TIM_TISEL_TI2SEL_Pos      (8U)\n#define TIM_TISEL_TI2SEL_Msk      (0xFUL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000F00 */\n#define TIM_TISEL_TI2SEL          TIM_TISEL_TI2SEL_Msk                         /*!<TI2SEL[3:0] bits (TIM TI2 SEL)*/\n#define TIM_TISEL_TI2SEL_0        (0x1UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000100 */\n#define TIM_TISEL_TI2SEL_1        (0x2UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000200 */\n#define TIM_TISEL_TI2SEL_2        (0x4UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000400 */\n#define TIM_TISEL_TI2SEL_3        (0x8UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000800 */\n\n#define TIM_TISEL_TI3SEL_Pos      (16U)\n#define TIM_TISEL_TI3SEL_Msk      (0xFUL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x000F0000 */\n#define TIM_TISEL_TI3SEL          TIM_TISEL_TI3SEL_Msk                         /*!<TI3SEL[3:0] bits (TIM TI3 SEL)*/\n#define TIM_TISEL_TI3SEL_0        (0x1UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00010000 */\n#define TIM_TISEL_TI3SEL_1        (0x2UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00020000 */\n#define TIM_TISEL_TI3SEL_2        (0x4UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00040000 */\n#define TIM_TISEL_TI3SEL_3        (0x8UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00080000 */\n\n#define TIM_TISEL_TI4SEL_Pos      (24U)\n#define TIM_TISEL_TI4SEL_Msk      (0xFUL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x0F000000 */\n#define TIM_TISEL_TI4SEL          TIM_TISEL_TI4SEL_Msk                         /*!<TI4SEL[3:0] bits (TIM TI4 SEL)*/\n#define TIM_TISEL_TI4SEL_0        (0x1UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x01000000 */\n#define TIM_TISEL_TI4SEL_1        (0x2UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x02000000 */\n#define TIM_TISEL_TI4SEL_2        (0x4UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x04000000 */\n#define TIM_TISEL_TI4SEL_3        (0x8UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x08000000 */\n\n/*******************  Bit definition for TIM8_AF1 register  *********************/\n#define TIM8_AF1_BKINE_Pos        (0U)\n#define TIM8_AF1_BKINE_Msk        (0x1UL << TIM8_AF1_BKINE_Pos)                /*!< 0x00000001 */\n#define TIM8_AF1_BKINE            TIM8_AF1_BKINE_Msk                           /*!<BKINE Break input enable bit */\n#define TIM8_AF1_BKCMP1E_Pos      (1U)\n#define TIM8_AF1_BKCMP1E_Msk      (0x1UL << TIM8_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */\n#define TIM8_AF1_BKCMP1E          TIM8_AF1_BKCMP1E_Msk                         /*!<BKCMP1E Break Compare1 Enable bit */\n#define TIM8_AF1_BKCMP2E_Pos      (2U)\n#define TIM8_AF1_BKCMP2E_Msk      (0x1UL << TIM8_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */\n#define TIM8_AF1_BKCMP2E          TIM8_AF1_BKCMP2E_Msk                         /*!<BKCMP1E Break Compare2 Enable bit  */\n#define TIM8_AF1_BKDFBK2E_Pos     (8U)\n#define TIM8_AF1_BKDFBK2E_Msk     (0x1UL << TIM8_AF1_BKDFBK2E_Pos)             /*!< 0x00000100 */\n#define TIM8_AF1_BKDFBK2E         TIM8_AF1_BKDFBK2E_Msk                        /*!<BKDFBK2E Break input DFSDM Break 2 */\n#define TIM8_AF1_BKINP_Pos        (9U)\n#define TIM8_AF1_BKINP_Msk        (0x1UL << TIM8_AF1_BKINP_Pos)                /*!< 0x00000200 */\n#define TIM8_AF1_BKINP            TIM8_AF1_BKINP_Msk                           /*!<BRKINP Break input polarity */\n#define TIM8_AF1_BKCMP1P_Pos      (10U)\n#define TIM8_AF1_BKCMP1P_Msk      (0x1UL << TIM8_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */\n#define TIM8_AF1_BKCMP1P          TIM8_AF1_BKCMP1P_Msk                         /*!<BKCMP1P Break COMP1 input polarity */\n#define TIM8_AF1_BKCMP2P_Pos      (11U)\n#define TIM8_AF1_BKCMP2P_Msk      (0x1UL << TIM8_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */\n#define TIM8_AF1_BKCMP2P          TIM8_AF1_BKCMP2P_Msk                         /*!<BKCMP2P Break COMP2 input polarity */\n\n#define TIM8_AF1_ETRSEL_Pos       (14U)\n#define TIM8_AF1_ETRSEL_Msk       (0xFUL << TIM8_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */\n#define TIM8_AF1_ETRSEL           TIM8_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM8 ETRSEL) */\n#define TIM8_AF1_ETRSEL_0         (0x1UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00004000 */\n#define TIM8_AF1_ETRSEL_1         (0x2UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00008000 */\n#define TIM8_AF1_ETRSEL_2         (0x4UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00010000 */\n#define TIM8_AF1_ETRSEL_3         (0x8UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00020000 */\n/*******************  Bit definition for TIM8_AF2 register  *********************/\n#define TIM8_AF2_BK2INE_Pos       (0U)\n#define TIM8_AF2_BK2INE_Msk       (0x1UL << TIM8_AF2_BK2INE_Pos)               /*!< 0x00000001 */\n#define TIM8_AF2_BK2INE           TIM8_AF2_BK2INE_Msk                          /*!<BK2INE Break input 2 enable bit */\n#define TIM8_AF2_BK2CMP1E_Pos     (1U)\n#define TIM8_AF2_BK2CMP1E_Msk     (0x1UL << TIM8_AF2_BK2CMP1E_Pos)             /*!< 0x00000002 */\n#define TIM8_AF2_BK2CMP1E         TIM8_AF2_BK2CMP1E_Msk                        /*!<BK2CMP1E Break2 Compare1 Enable bit */\n#define TIM8_AF2_BK2CMP2E_Pos     (2U)\n#define TIM8_AF2_BK2CMP2E_Msk     (0x1UL << TIM8_AF2_BK2CMP2E_Pos)             /*!< 0x00000004 */\n#define TIM8_AF2_BK2CMP2E         TIM8_AF2_BK2CMP2E_Msk                        /*!<BK2CMP1E Break2 Compare2 Enable bit  */\n#define TIM8_AF2_BK2DFBK3E_Pos    (8U)\n#define TIM8_AF2_BK2DFBK3E_Msk    (0x1UL << TIM8_AF2_BK2DFBK3E_Pos)            /*!< 0x00000100 */\n#define TIM8_AF2_BK2DFBK3E        TIM8_AF2_BK2DFBK3E_Msk                       /*!<BK2DFBK1E Break input2 DFSDM Break 3 */\n#define TIM8_AF2_BK2INP_Pos       (9U)\n#define TIM8_AF2_BK2INP_Msk       (0x1UL << TIM8_AF2_BK2INP_Pos)               /*!< 0x00000200 */\n#define TIM8_AF2_BK2INP           TIM8_AF2_BK2INP_Msk                          /*!<BRKINP Break2 input polarity */\n#define TIM8_AF2_BK2CMP1P_Pos     (10U)\n#define TIM8_AF2_BK2CMP1P_Msk     (0x1UL << TIM8_AF2_BK2CMP1P_Pos)             /*!< 0x00000400 */\n#define TIM8_AF2_BK2CMP1P         TIM8_AF2_BK2CMP1P_Msk                        /*!<BKCMP1P Break2 COMP1 input polarity */\n#define TIM8_AF2_BK2CMP2P_Pos     (11U)\n#define TIM8_AF2_BK2CMP2P_Msk     (0x1UL << TIM8_AF2_BK2CMP2P_Pos)             /*!< 0x00000800 */\n#define TIM8_AF2_BK2CMP2P         TIM8_AF2_BK2CMP2P_Msk                        /*!<BKCMP2P Break2 COMP2 input polarity */\n\n/*******************  Bit definition for TIM2_AF1 register  *********************/\n#define TIM2_AF1_ETRSEL_Pos      (14U)\n#define TIM2_AF1_ETRSEL_Msk      (0xFUL << TIM2_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */\n#define TIM2_AF1_ETRSEL          TIM2_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM2 ETRSEL) */\n#define TIM2_AF1_ETRSEL_0        (0x1UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */\n#define TIM2_AF1_ETRSEL_1        (0x2UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */\n#define TIM2_AF1_ETRSEL_2        (0x4UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */\n#define TIM2_AF1_ETRSEL_3        (0x8UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */\n\n/*******************  Bit definition for TIM3_AF1 register  *********************/\n#define TIM3_AF1_ETRSEL_Pos      (14U)\n#define TIM3_AF1_ETRSEL_Msk      (0xFUL << TIM3_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */\n#define TIM3_AF1_ETRSEL          TIM3_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM3 ETRSEL) */\n#define TIM3_AF1_ETRSEL_0        (0x1UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */\n#define TIM3_AF1_ETRSEL_1        (0x2UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */\n#define TIM3_AF1_ETRSEL_2        (0x4UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */\n#define TIM3_AF1_ETRSEL_3        (0x8UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */\n\n/*******************  Bit definition for TIM5_AF1 register  *********************/\n#define TIM5_AF1_ETRSEL_Pos      (14U)\n#define TIM5_AF1_ETRSEL_Msk      (0xFUL << TIM5_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */\n#define TIM5_AF1_ETRSEL          TIM5_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM5 ETRSEL) */\n#define TIM5_AF1_ETRSEL_0        (0x1UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */\n#define TIM5_AF1_ETRSEL_1        (0x2UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */\n#define TIM5_AF1_ETRSEL_2        (0x4UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */\n#define TIM5_AF1_ETRSEL_3        (0x8UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */\n\n/*******************  Bit definition for TIM15_AF1 register  *********************/\n#define TIM15_AF1_BKINE_Pos        (0U)\n#define TIM15_AF1_BKINE_Msk        (0x1UL << TIM15_AF1_BKINE_Pos)              /*!< 0x00000001 */\n#define TIM15_AF1_BKINE            TIM15_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */\n#define TIM15_AF1_BKCMP1E_Pos      (1U)\n#define TIM15_AF1_BKCMP1E_Msk      (0x1UL << TIM15_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */\n#define TIM15_AF1_BKCMP1E          TIM15_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */\n#define TIM15_AF1_BKCMP2E_Pos      (2U)\n#define TIM15_AF1_BKCMP2E_Msk      (0x1UL << TIM15_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */\n#define TIM15_AF1_BKCMP2E          TIM15_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */\n#define TIM15_AF1_BKDF1BK2E_Pos    (8U)\n#define TIM15_AF1_BKDF1BK2E_Msk    (0x1UL << TIM15_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */\n#define TIM15_AF1_BKDF1BK2E        TIM15_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[0] enable */\n#define TIM15_AF1_BKINP_Pos        (9U)\n#define TIM15_AF1_BKINP_Msk        (0x1UL << TIM15_AF1_BKINP_Pos)              /*!< 0x00000200 */\n#define TIM15_AF1_BKINP            TIM15_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */\n#define TIM15_AF1_BKCMP1P_Pos      (10U)\n#define TIM15_AF1_BKCMP1P_Msk      (0x1UL << TIM15_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */\n#define TIM15_AF1_BKCMP1P          TIM15_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */\n#define TIM15_AF1_BKCMP2P_Pos      (11U)\n#define TIM15_AF1_BKCMP2P_Msk      (0x1UL << TIM15_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */\n#define TIM15_AF1_BKCMP2P          TIM15_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */\n\n/*******************  Bit definition for TIM16_ register  *********************/\n#define TIM16_AF1_BKINE_Pos        (0U)\n#define TIM16_AF1_BKINE_Msk        (0x1UL << TIM16_AF1_BKINE_Pos)              /*!< 0x00000001 */\n#define TIM16_AF1_BKINE            TIM16_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */\n#define TIM16_AF1_BKCMP1E_Pos      (1U)\n#define TIM16_AF1_BKCMP1E_Msk      (0x1UL << TIM16_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */\n#define TIM16_AF1_BKCMP1E          TIM16_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */\n#define TIM16_AF1_BKCMP2E_Pos      (2U)\n#define TIM16_AF1_BKCMP2E_Msk      (0x1UL << TIM16_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */\n#define TIM16_AF1_BKCMP2E          TIM16_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */\n#define TIM16_AF1_BKDF1BK2E_Pos    (8U)\n#define TIM16_AF1_BKDF1BK2E_Msk    (0x1UL << TIM16_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */\n#define TIM16_AF1_BKDF1BK2E        TIM16_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[1] enable */\n#define TIM16_AF1_BKINP_Pos        (9U)\n#define TIM16_AF1_BKINP_Msk        (0x1UL << TIM16_AF1_BKINP_Pos)              /*!< 0x00000200 */\n#define TIM16_AF1_BKINP            TIM16_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */\n#define TIM16_AF1_BKCMP1P_Pos      (10U)\n#define TIM16_AF1_BKCMP1P_Msk      (0x1UL << TIM16_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */\n#define TIM16_AF1_BKCMP1P          TIM16_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */\n#define TIM16_AF1_BKCMP2P_Pos      (11U)\n#define TIM16_AF1_BKCMP2P_Msk      (0x1UL << TIM16_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */\n#define TIM16_AF1_BKCMP2P          TIM16_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */\n\n/*******************  Bit definition for TIM17_AF1 register  *********************/\n#define TIM17_AF1_BKINE_Pos        (0U)\n#define TIM17_AF1_BKINE_Msk        (0x1UL << TIM17_AF1_BKINE_Pos)              /*!< 0x00000001 */\n#define TIM17_AF1_BKINE            TIM17_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */\n#define TIM17_AF1_BKCMP1E_Pos      (1U)\n#define TIM17_AF1_BKCMP1E_Msk      (0x1UL << TIM17_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */\n#define TIM17_AF1_BKCMP1E          TIM17_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */\n#define TIM17_AF1_BKCMP2E_Pos      (2U)\n#define TIM17_AF1_BKCMP2E_Msk      (0x1UL << TIM17_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */\n#define TIM17_AF1_BKCMP2E          TIM17_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */\n#define TIM17_AF1_BKDF1BK2E_Pos    (8U)\n#define TIM17_AF1_BKDF1BK2E_Msk    (0x1UL << TIM17_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */\n#define TIM17_AF1_BKDF1BK2E        TIM17_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[2] enable */\n#define TIM17_AF1_BKINP_Pos        (9U)\n#define TIM17_AF1_BKINP_Msk        (0x1UL << TIM17_AF1_BKINP_Pos)              /*!< 0x00000200 */\n#define TIM17_AF1_BKINP            TIM17_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */\n#define TIM17_AF1_BKCMP1P_Pos      (10U)\n#define TIM17_AF1_BKCMP1P_Msk      (0x1UL << TIM17_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */\n#define TIM17_AF1_BKCMP1P          TIM17_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */\n#define TIM17_AF1_BKCMP2P_Pos      (11U)\n#define TIM17_AF1_BKCMP2P_Msk      (0x1UL << TIM17_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */\n#define TIM17_AF1_BKCMP2P          TIM17_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */\n\n/******************************************************************************/\n/*                                                                            */\n/*                         Low Power Timer (LPTTIM)                           */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bit definition for LPTIM_ISR register  *******************/\n#define LPTIM_ISR_CMPM_Pos          (0U)\n#define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)              /*!< 0x00000001 */\n#define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */\n#define LPTIM_ISR_ARRM_Pos          (1U)\n#define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)              /*!< 0x00000002 */\n#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */\n#define LPTIM_ISR_EXTTRIG_Pos       (2U)\n#define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)           /*!< 0x00000004 */\n#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */\n#define LPTIM_ISR_CMPOK_Pos         (3U)\n#define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)             /*!< 0x00000008 */\n#define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */\n#define LPTIM_ISR_ARROK_Pos         (4U)\n#define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)             /*!< 0x00000010 */\n#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */\n#define LPTIM_ISR_UP_Pos            (5U)\n#define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                /*!< 0x00000020 */\n#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */\n#define LPTIM_ISR_DOWN_Pos          (6U)\n#define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)              /*!< 0x00000040 */\n#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */\n\n/******************  Bit definition for LPTIM_ICR register  *******************/\n#define LPTIM_ICR_CMPMCF_Pos        (0U)\n#define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)            /*!< 0x00000001 */\n#define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */\n#define LPTIM_ICR_ARRMCF_Pos        (1U)\n#define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)            /*!< 0x00000002 */\n#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */\n#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)\n#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)         /*!< 0x00000004 */\n#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */\n#define LPTIM_ICR_CMPOKCF_Pos       (3U)\n#define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)           /*!< 0x00000008 */\n#define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */\n#define LPTIM_ICR_ARROKCF_Pos       (4U)\n#define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)           /*!< 0x00000010 */\n#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */\n#define LPTIM_ICR_UPCF_Pos          (5U)\n#define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)              /*!< 0x00000020 */\n#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */\n#define LPTIM_ICR_DOWNCF_Pos        (6U)\n#define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)            /*!< 0x00000040 */\n#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */\n\n/******************  Bit definition for LPTIM_IER register ********************/\n#define LPTIM_IER_CMPMIE_Pos        (0U)\n#define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)            /*!< 0x00000001 */\n#define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */\n#define LPTIM_IER_ARRMIE_Pos        (1U)\n#define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)            /*!< 0x00000002 */\n#define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */\n#define LPTIM_IER_EXTTRIGIE_Pos     (2U)\n#define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)         /*!< 0x00000004 */\n#define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */\n#define LPTIM_IER_CMPOKIE_Pos       (3U)\n#define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)           /*!< 0x00000008 */\n#define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */\n#define LPTIM_IER_ARROKIE_Pos       (4U)\n#define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)           /*!< 0x00000010 */\n#define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */\n#define LPTIM_IER_UPIE_Pos          (5U)\n#define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)              /*!< 0x00000020 */\n#define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */\n#define LPTIM_IER_DOWNIE_Pos        (6U)\n#define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)            /*!< 0x00000040 */\n#define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */\n\n/******************  Bit definition for LPTIM_CFGR register *******************/\n#define LPTIM_CFGR_CKSEL_Pos        (0U)\n#define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)            /*!< 0x00000001 */\n#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */\n\n#define LPTIM_CFGR_CKPOL_Pos        (1U)\n#define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000006 */\n#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */\n#define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000002 */\n#define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000004 */\n\n#define LPTIM_CFGR_CKFLT_Pos        (3U)\n#define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000018 */\n#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */\n#define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000008 */\n#define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000010 */\n\n#define LPTIM_CFGR_TRGFLT_Pos       (6U)\n#define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x000000C0 */\n#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */\n#define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000040 */\n#define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000080 */\n\n#define LPTIM_CFGR_PRESC_Pos        (9U)\n#define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000E00 */\n#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */\n#define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000200 */\n#define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000400 */\n#define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000800 */\n\n#define LPTIM_CFGR_TRIGSEL_Pos      (13U)\n#define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x0000E000 */\n#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */\n#define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00002000 */\n#define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00004000 */\n#define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00008000 */\n\n#define LPTIM_CFGR_TRIGEN_Pos       (17U)\n#define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00060000 */\n#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */\n#define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00020000 */\n#define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00040000 */\n\n#define LPTIM_CFGR_TIMOUT_Pos       (19U)\n#define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)           /*!< 0x00080000 */\n#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */\n#define LPTIM_CFGR_WAVE_Pos         (20U)\n#define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)             /*!< 0x00100000 */\n#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */\n#define LPTIM_CFGR_WAVPOL_Pos       (21U)\n#define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)           /*!< 0x00200000 */\n#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */\n#define LPTIM_CFGR_PRELOAD_Pos      (22U)\n#define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)          /*!< 0x00400000 */\n#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */\n#define LPTIM_CFGR_COUNTMODE_Pos    (23U)\n#define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)        /*!< 0x00800000 */\n#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */\n#define LPTIM_CFGR_ENC_Pos          (24U)\n#define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)              /*!< 0x01000000 */\n#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */\n\n/******************  Bit definition for LPTIM_CR register  ********************/\n#define LPTIM_CR_ENABLE_Pos         (0U)\n#define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)             /*!< 0x00000001 */\n#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */\n#define LPTIM_CR_SNGSTRT_Pos        (1U)\n#define LPTIM_CR_SNGSTRT_Msk        (0x40001UL << LPTIM_CR_SNGSTRT_Pos)        /*!< 0x00080002 */\n#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */\n#define LPTIM_CR_CNTSTRT_Pos        (2U)\n#define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)            /*!< 0x00000004 */\n#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */\n#define LPTIM_CR_COUNTRST_Pos       (3U)\n#define LPTIM_CR_COUNTRST_Msk       (0x1UL << LPTIM_CR_COUNTRST_Pos)           /*!< 0x00000008 */\n#define LPTIM_CR_COUNTRST           LPTIM_CR_COUNTRST_Msk                      /*!< Timer Counter reset in synchronous mode*/\n#define LPTIM_CR_RSTARE_Pos         (4U)\n#define LPTIM_CR_RSTARE_Msk         (0x1UL << LPTIM_CR_RSTARE_Pos)             /*!< 0x00000010 */\n#define LPTIM_CR_RSTARE             LPTIM_CR_RSTARE_Msk                        /*!< Timer Counter reset after read enable (asynchronously)*/\n\n\n/******************  Bit definition for LPTIM_CMP register  *******************/\n#define LPTIM_CMP_CMP_Pos           (0U)\n#define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)            /*!< 0x0000FFFF */\n#define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */\n\n/******************  Bit definition for LPTIM_ARR register  *******************/\n#define LPTIM_ARR_ARR_Pos           (0U)\n#define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)            /*!< 0x0000FFFF */\n#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */\n\n/******************  Bit definition for LPTIM_CNT register  *******************/\n#define LPTIM_CNT_CNT_Pos           (0U)\n#define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)            /*!< 0x0000FFFF */\n#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */\n\n/******************  Bit definition for LPTIM_CFGR2 register  *****************/\n#define LPTIM_CFGR2_IN1SEL_Pos      (0U)\n#define LPTIM_CFGR2_IN1SEL_Msk      (0x3UL << LPTIM_CFGR2_IN1SEL_Pos)          /*!< 0x00000003 */\n#define LPTIM_CFGR2_IN1SEL          LPTIM_CFGR2_IN1SEL_Msk                     /*!< IN1SEL[1:0] bits (Remap selection) */\n#define LPTIM_CFGR2_IN1SEL_0        (0x1UL << LPTIM_CFGR2_IN1SEL_Pos)           /*!< 0x00000001 */\n#define LPTIM_CFGR2_IN1SEL_1        (0x2UL << LPTIM_CFGR2_IN1SEL_Pos)           /*!< 0x00000002 */\n#define LPTIM_CFGR2_IN2SEL_Pos      (4U)\n#define LPTIM_CFGR2_IN2SEL_Msk      (0x3UL << LPTIM_CFGR2_IN2SEL_Pos)          /*!< 0x00000030 */\n#define LPTIM_CFGR2_IN2SEL          LPTIM_CFGR2_IN2SEL_Msk                     /*!< IN2SEL[5:4] bits (Remap selection) */\n#define LPTIM_CFGR2_IN2SEL_0        (0x1UL << LPTIM_CFGR2_IN2SEL_Pos)           /*!< 0x00000010 */\n#define LPTIM_CFGR2_IN2SEL_1        (0x2UL << LPTIM_CFGR2_IN2SEL_Pos)           /*!< 0x00000020 */\n\n/******************************************************************************/\n/*                                                                            */\n/*                      Analog Comparators (COMP)                             */\n/*                                                                            */\n/******************************************************************************/\n\n/*******************  Bit definition for COMP_SR register  ********************/\n#define COMP_SR_C1VAL_Pos            (0U)\n#define COMP_SR_C1VAL_Msk            (0x1UL << COMP_SR_C1VAL_Pos)              /*!< 0x00000001 */\n#define COMP_SR_C1VAL                COMP_SR_C1VAL_Msk\n#define COMP_SR_C2VAL_Pos            (1U)\n#define COMP_SR_C2VAL_Msk            (0x1UL << COMP_SR_C2VAL_Pos)              /*!< 0x00000002 */\n#define COMP_SR_C2VAL                COMP_SR_C2VAL_Msk\n#define COMP_SR_C1IF_Pos             (16U)\n#define COMP_SR_C1IF_Msk             (0x1UL << COMP_SR_C1IF_Pos)               /*!< 0x00010000 */\n#define COMP_SR_C1IF                 COMP_SR_C1IF_Msk\n#define COMP_SR_C2IF_Pos             (17U)\n#define COMP_SR_C2IF_Msk             (0x1UL << COMP_SR_C2IF_Pos)               /*!< 0x00020000 */\n#define COMP_SR_C2IF                 COMP_SR_C2IF_Msk\n/*******************  Bit definition for COMP_ICFR register  ********************/\n#define COMP_ICFR_C1IF_Pos           (16U)\n#define COMP_ICFR_C1IF_Msk           (0x1UL << COMP_ICFR_C1IF_Pos)             /*!< 0x00010000 */\n#define COMP_ICFR_C1IF               COMP_ICFR_C1IF_Msk\n#define COMP_ICFR_C2IF_Pos           (17U)\n#define COMP_ICFR_C2IF_Msk           (0x1UL << COMP_ICFR_C2IF_Pos)             /*!< 0x00020000 */\n#define COMP_ICFR_C2IF               COMP_ICFR_C2IF_Msk\n/*******************  Bit definition for COMP_OR register  ********************/\n#define COMP_OR_AFOPA6_Pos           (0U)\n#define COMP_OR_AFOPA6_Msk           (0x1UL << COMP_OR_AFOPA6_Pos)             /*!< 0x00000001 */\n#define COMP_OR_AFOPA6               COMP_OR_AFOPA6_Msk\n#define COMP_OR_AFOPA8_Pos           (1U)\n#define COMP_OR_AFOPA8_Msk           (0x1UL << COMP_OR_AFOPA8_Pos)             /*!< 0x00000002 */\n#define COMP_OR_AFOPA8               COMP_OR_AFOPA8_Msk\n#define COMP_OR_AFOPB12_Pos          (2U)\n#define COMP_OR_AFOPB12_Msk          (0x1UL << COMP_OR_AFOPB12_Pos)            /*!< 0x00000004 */\n#define COMP_OR_AFOPB12              COMP_OR_AFOPB12_Msk\n#define COMP_OR_AFOPE6_Pos           (3U)\n#define COMP_OR_AFOPE6_Msk           (0x1UL << COMP_OR_AFOPE6_Pos)             /*!< 0x00000008 */\n#define COMP_OR_AFOPE6               COMP_OR_AFOPE6_Msk\n#define COMP_OR_AFOPE15_Pos          (4U)\n#define COMP_OR_AFOPE15_Msk          (0x1UL << COMP_OR_AFOPE15_Pos)            /*!< 0x00000010 */\n#define COMP_OR_AFOPE15              COMP_OR_AFOPE15_Msk\n#define COMP_OR_AFOPG2_Pos           (5U)\n#define COMP_OR_AFOPG2_Msk           (0x1UL << COMP_OR_AFOPG2_Pos)             /*!< 0x00000020 */\n#define COMP_OR_AFOPG2               COMP_OR_AFOPG2_Msk\n#define COMP_OR_AFOPG3_Pos           (6U)\n#define COMP_OR_AFOPG3_Msk           (0x1UL << COMP_OR_AFOPG3_Pos)             /*!< 0x00000040 */\n#define COMP_OR_AFOPG3               COMP_OR_AFOPG3_Msk\n#define COMP_OR_AFOPG4_Pos           (7U)\n#define COMP_OR_AFOPG4_Msk           (0x1UL << COMP_OR_AFOPG4_Pos)             /*!< 0x00000080 */\n#define COMP_OR_AFOPG4               COMP_OR_AFOPG4_Msk\n#define COMP_OR_AFOPI1_Pos           (8U)\n#define COMP_OR_AFOPI1_Msk           (0x1UL << COMP_OR_AFOPI1_Pos)             /*!< 0x00000100 */\n#define COMP_OR_AFOPI1               COMP_OR_AFOPI1_Msk\n#define COMP_OR_AFOPI4_Pos           (9U)\n#define COMP_OR_AFOPI4_Msk           (0x1UL << COMP_OR_AFOPI4_Pos)             /*!< 0x00000200 */\n#define COMP_OR_AFOPI4               COMP_OR_AFOPI4_Msk\n#define COMP_OR_AFOPK2_Pos           (10U)\n#define COMP_OR_AFOPK2_Msk           (0x1UL << COMP_OR_AFOPK2_Pos)             /*!< 0x00000400 */\n#define COMP_OR_AFOPK2               COMP_OR_AFOPK2_Msk\n\n/*!< ******************  Bit definition for COMP_CFGRx register  ********************/\n#define COMP_CFGRx_EN_Pos            (0U)\n#define COMP_CFGRx_EN_Msk            (0x1UL << COMP_CFGRx_EN_Pos)              /*!< 0x00000001 */\n#define COMP_CFGRx_EN                COMP_CFGRx_EN_Msk                         /*!< COMPx enable bit                     */\n#define COMP_CFGRx_BRGEN_Pos         (1U)\n#define COMP_CFGRx_BRGEN_Msk         (0x1UL << COMP_CFGRx_BRGEN_Pos)           /*!< 0x00000002 */\n#define COMP_CFGRx_BRGEN             COMP_CFGRx_BRGEN_Msk                      /*!< COMPx Scaler bridge enable           */\n#define COMP_CFGRx_SCALEN_Pos        (2U)\n#define COMP_CFGRx_SCALEN_Msk        (0x1UL << COMP_CFGRx_SCALEN_Pos)          /*!< 0x00000004 */\n#define COMP_CFGRx_SCALEN            COMP_CFGRx_SCALEN_Msk                     /*!< COMPx Voltage scaler enable bit      */\n#define COMP_CFGRx_POLARITY_Pos      (3U)\n#define COMP_CFGRx_POLARITY_Msk      (0x1UL << COMP_CFGRx_POLARITY_Pos)        /*!< 0x00000008 */\n#define COMP_CFGRx_POLARITY          COMP_CFGRx_POLARITY_Msk                   /*!< COMPx  polarity selection bit        */\n#define COMP_CFGRx_WINMODE_Pos       (4U)\n#define COMP_CFGRx_WINMODE_Msk       (0x1UL << COMP_CFGRx_WINMODE_Pos)         /*!< 0x00000010 */\n#define COMP_CFGRx_WINMODE           COMP_CFGRx_WINMODE_Msk                    /*!< COMPx Windows mode selection bit     */\n#define COMP_CFGRx_ITEN_Pos          (6U)\n#define COMP_CFGRx_ITEN_Msk          (0x1UL << COMP_CFGRx_ITEN_Pos)            /*!< 0x00000040 */\n#define COMP_CFGRx_ITEN              COMP_CFGRx_ITEN_Msk                       /*!< COMPx  interrupt enable              */\n#define COMP_CFGRx_HYST_Pos          (8U)\n#define COMP_CFGRx_HYST_Msk          (0x3UL << COMP_CFGRx_HYST_Pos)            /*!< 0x00000300 */\n#define COMP_CFGRx_HYST              COMP_CFGRx_HYST_Msk                       /*!< COMPx  hysteresis selection bits     */\n#define COMP_CFGRx_HYST_0            (0x1UL << COMP_CFGRx_HYST_Pos)             /*!< 0x00000100 */\n#define COMP_CFGRx_HYST_1            (0x2UL << COMP_CFGRx_HYST_Pos)             /*!< 0x00000200 */\n#define COMP_CFGRx_PWRMODE_Pos       (12U)\n#define COMP_CFGRx_PWRMODE_Msk       (0x3UL << COMP_CFGRx_PWRMODE_Pos)         /*!< 0x00003000 */\n#define COMP_CFGRx_PWRMODE           COMP_CFGRx_PWRMODE_Msk                    /*!< COMPx Power Mode of the comparator   */\n#define COMP_CFGRx_PWRMODE_0         (0x1UL << COMP_CFGRx_PWRMODE_Pos)          /*!< 0x00001000 */\n#define COMP_CFGRx_PWRMODE_1         (0x2UL << COMP_CFGRx_PWRMODE_Pos)          /*!< 0x00002000 */\n#define COMP_CFGRx_INMSEL_Pos        (16U)\n#define COMP_CFGRx_INMSEL_Msk        (0x7UL << COMP_CFGRx_INMSEL_Pos)          /*!< 0x00070000 */\n#define COMP_CFGRx_INMSEL            COMP_CFGRx_INMSEL_Msk                     /*!< COMPx  input minus selection bit  */\n#define COMP_CFGRx_INMSEL_0          (0x1UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00010000 */\n#define COMP_CFGRx_INMSEL_1          (0x2UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00020000 */\n#define COMP_CFGRx_INMSEL_2          (0x4UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00040000 */\n#define COMP_CFGRx_INPSEL_Pos        (20U)\n#define COMP_CFGRx_INPSEL_Msk        (0x1UL << COMP_CFGRx_INPSEL_Pos)          /*!< 0x00100000 */\n#define COMP_CFGRx_INPSEL            COMP_CFGRx_INPSEL_Msk                     /*!< COMPx  input plus selection bit       */\n#define COMP_CFGRx_BLANKING_Pos      (24U)\n#define COMP_CFGRx_BLANKING_Msk      (0xFUL << COMP_CFGRx_BLANKING_Pos)        /*!< 0x0F000000 */\n#define COMP_CFGRx_BLANKING          COMP_CFGRx_BLANKING_Msk                   /*!< COMPx  blanking source selection bits */\n#define COMP_CFGRx_BLANKING_0        (0x1UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x01000000 */\n#define COMP_CFGRx_BLANKING_1        (0x2UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x02000000 */\n#define COMP_CFGRx_BLANKING_2        (0x4UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x04000000 */\n#define COMP_CFGRx_LOCK_Pos          (31U)\n#define COMP_CFGRx_LOCK_Msk          (0x1UL << COMP_CFGRx_LOCK_Pos)            /*!< 0x80000000 */\n#define COMP_CFGRx_LOCK              COMP_CFGRx_LOCK_Msk                       /*!< COMPx Lock Bit                        */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bit definition for USART_CR1 register  *******************/\n#define USART_CR1_UE_Pos                (0U)\n#define USART_CR1_UE_Msk                (0x1UL << USART_CR1_UE_Pos)            /*!< 0x00000001 */\n#define USART_CR1_UE                    USART_CR1_UE_Msk                       /*!< USART Enable */\n#define USART_CR1_UESM_Pos              (1U)\n#define USART_CR1_UESM_Msk              (0x1UL << USART_CR1_UESM_Pos)          /*!< 0x00000002 */\n#define USART_CR1_UESM                  USART_CR1_UESM_Msk                     /*!< USART Enable in STOP Mode */\n#define USART_CR1_RE_Pos                (2U)\n#define USART_CR1_RE_Msk                (0x1UL << USART_CR1_RE_Pos)            /*!< 0x00000004 */\n#define USART_CR1_RE                    USART_CR1_RE_Msk                       /*!< Receiver Enable */\n#define USART_CR1_TE_Pos                (3U)\n#define USART_CR1_TE_Msk                (0x1UL << USART_CR1_TE_Pos)            /*!< 0x00000008 */\n#define USART_CR1_TE                    USART_CR1_TE_Msk                       /*!< Transmitter Enable */\n#define USART_CR1_IDLEIE_Pos            (4U)\n#define USART_CR1_IDLEIE_Msk            (0x1UL << USART_CR1_IDLEIE_Pos)        /*!< 0x00000010 */\n#define USART_CR1_IDLEIE                USART_CR1_IDLEIE_Msk                   /*!< IDLE Interrupt Enable */\n#define USART_CR1_RXNEIE_RXFNEIE_Pos    (5U)\n#define USART_CR1_RXNEIE_RXFNEIE_Msk    (0x1UL << USART_CR1_RXNEIE_RXFNEIE_Pos) /*!< 0x00000020 */\n#define USART_CR1_RXNEIE_RXFNEIE        USART_CR1_RXNEIE_RXFNEIE_Msk           /*!< RXNE and RX FIFO Not Empty Interrupt Enable */\n#define USART_CR1_TCIE_Pos              (6U)\n#define USART_CR1_TCIE_Msk              (0x1UL << USART_CR1_TCIE_Pos)          /*!< 0x00000040 */\n#define USART_CR1_TCIE                  USART_CR1_TCIE_Msk                     /*!< Transmission Complete Interrupt Enable */\n#define USART_CR1_TXEIE_TXFNFIE_Pos     (7U)\n#define USART_CR1_TXEIE_TXFNFIE_Msk     (0x1UL << USART_CR1_TXEIE_TXFNFIE_Pos) /*!< 0x00000080 */\n#define USART_CR1_TXEIE_TXFNFIE         USART_CR1_TXEIE_TXFNFIE_Msk            /*!< TXE and TX FIFO Not Full Interrupt Enable */\n#define USART_CR1_PEIE_Pos              (8U)\n#define USART_CR1_PEIE_Msk              (0x1UL << USART_CR1_PEIE_Pos)          /*!< 0x00000100 */\n#define USART_CR1_PEIE                  USART_CR1_PEIE_Msk                     /*!< PE Interrupt Enable */\n#define USART_CR1_PS_Pos                (9U)\n#define USART_CR1_PS_Msk                (0x1UL << USART_CR1_PS_Pos)            /*!< 0x00000200 */\n#define USART_CR1_PS                    USART_CR1_PS_Msk                       /*!< Parity Selection */\n#define USART_CR1_PCE_Pos               (10U)\n#define USART_CR1_PCE_Msk               (0x1UL << USART_CR1_PCE_Pos)           /*!< 0x00000400 */\n#define USART_CR1_PCE                   USART_CR1_PCE_Msk                      /*!< Parity Control Enable */\n#define USART_CR1_WAKE_Pos              (11U)\n#define USART_CR1_WAKE_Msk              (0x1UL << USART_CR1_WAKE_Pos)          /*!< 0x00000800 */\n#define USART_CR1_WAKE                  USART_CR1_WAKE_Msk                     /*!< Receiver Wakeup method */\n#define USART_CR1_M_Pos                 (12U)\n#define USART_CR1_M_Msk                 (0x10001UL << USART_CR1_M_Pos)         /*!< 0x10001000 */\n#define USART_CR1_M                     USART_CR1_M_Msk                        /*!< Word length */\n#define USART_CR1_M0_Pos                (12U)\n#define USART_CR1_M0_Msk                (0x1UL << USART_CR1_M0_Pos)            /*!< 0x00001000 */\n#define USART_CR1_M0                    USART_CR1_M0_Msk                       /*!< Word length - Bit 0 */\n#define USART_CR1_MME_Pos               (13U)\n#define USART_CR1_MME_Msk               (0x1UL << USART_CR1_MME_Pos)           /*!< 0x00002000 */\n#define USART_CR1_MME                   USART_CR1_MME_Msk                      /*!< Mute Mode Enable */\n#define USART_CR1_CMIE_Pos              (14U)\n#define USART_CR1_CMIE_Msk              (0x1UL << USART_CR1_CMIE_Pos)          /*!< 0x00004000 */\n#define USART_CR1_CMIE                  USART_CR1_CMIE_Msk                     /*!< Character match interrupt enable */\n#define USART_CR1_OVER8_Pos             (15U)\n#define USART_CR1_OVER8_Msk             (0x1UL << USART_CR1_OVER8_Pos)         /*!< 0x00008000 */\n#define USART_CR1_OVER8                 USART_CR1_OVER8_Msk                    /*!< Oversampling by 8-bit or 16-bit mode */\n#define USART_CR1_DEDT_Pos              (16U)\n#define USART_CR1_DEDT_Msk              (0x1FUL << USART_CR1_DEDT_Pos)         /*!< 0x001F0000 */\n#define USART_CR1_DEDT                  USART_CR1_DEDT_Msk                     /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */\n#define USART_CR1_DEDT_0                (0x01UL << USART_CR1_DEDT_Pos)          /*!< 0x00010000 */\n#define USART_CR1_DEDT_1                (0x02UL << USART_CR1_DEDT_Pos)          /*!< 0x00020000 */\n#define USART_CR1_DEDT_2                (0x04UL << USART_CR1_DEDT_Pos)          /*!< 0x00040000 */\n#define USART_CR1_DEDT_3                (0x08UL << USART_CR1_DEDT_Pos)          /*!< 0x00080000 */\n#define USART_CR1_DEDT_4                (0x10UL << USART_CR1_DEDT_Pos)          /*!< 0x00100000 */\n#define USART_CR1_DEAT_Pos              (21U)\n#define USART_CR1_DEAT_Msk              (0x1FUL << USART_CR1_DEAT_Pos)         /*!< 0x03E00000 */\n#define USART_CR1_DEAT                  USART_CR1_DEAT_Msk                     /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */\n#define USART_CR1_DEAT_0                (0x01UL << USART_CR1_DEAT_Pos)          /*!< 0x00200000 */\n#define USART_CR1_DEAT_1                (0x02UL << USART_CR1_DEAT_Pos)          /*!< 0x00400000 */\n#define USART_CR1_DEAT_2                (0x04UL << USART_CR1_DEAT_Pos)          /*!< 0x00800000 */\n#define USART_CR1_DEAT_3                (0x08UL << USART_CR1_DEAT_Pos)          /*!< 0x01000000 */\n#define USART_CR1_DEAT_4                (0x10UL << USART_CR1_DEAT_Pos)          /*!< 0x02000000 */\n#define USART_CR1_RTOIE_Pos             (26U)\n#define USART_CR1_RTOIE_Msk             (0x1UL << USART_CR1_RTOIE_Pos)         /*!< 0x04000000 */\n#define USART_CR1_RTOIE                 USART_CR1_RTOIE_Msk                    /*!< Receive Time Out interrupt enable */\n#define USART_CR1_EOBIE_Pos             (27U)\n#define USART_CR1_EOBIE_Msk             (0x1UL << USART_CR1_EOBIE_Pos)         /*!< 0x08000000 */\n#define USART_CR1_EOBIE                 USART_CR1_EOBIE_Msk                    /*!< End of Block interrupt enable */\n#define USART_CR1_M1_Pos                (28U)\n#define USART_CR1_M1_Msk                (0x1UL << USART_CR1_M1_Pos)            /*!< 0x10000000 */\n#define USART_CR1_M1                    USART_CR1_M1_Msk                       /*!< Word length - Bit 1 */\n#define USART_CR1_FIFOEN_Pos            (29U)\n#define USART_CR1_FIFOEN_Msk            (0x1UL << USART_CR1_FIFOEN_Pos)        /*!< 0x20000000 */\n#define USART_CR1_FIFOEN                USART_CR1_FIFOEN_Msk                   /*!< FIFO mode enable */\n#define USART_CR1_TXFEIE_Pos            (30U)\n#define USART_CR1_TXFEIE_Msk            (0x1UL << USART_CR1_TXFEIE_Pos)        /*!< 0x40000000 */\n#define USART_CR1_TXFEIE                USART_CR1_TXFEIE_Msk                   /*!< TXFIFO empty interrupt enable */\n#define USART_CR1_RXFFIE_Pos            (31U)\n#define USART_CR1_RXFFIE_Msk            (0x1UL << USART_CR1_RXFFIE_Pos)        /*!< 0x80000000 */\n#define USART_CR1_RXFFIE                USART_CR1_RXFFIE_Msk                   /*!< RXFIFO Full interrupt enable */\n\n/* Legacy define */\n#define  USART_CR1_RXNEIE  USART_CR1_RXNEIE_RXFNEIE\n#define  USART_CR1_TXEIE   USART_CR1_TXEIE_TXFNFIE\n\n/******************  Bit definition for USART_CR2 register  *******************/\n#define USART_CR2_SLVEN_Pos             (0U)\n#define USART_CR2_SLVEN_Msk             (0x1UL << USART_CR2_SLVEN_Pos)         /*!< 0x00000001 */\n#define USART_CR2_SLVEN                 USART_CR2_SLVEN_Msk                    /*!< Synchronous Slave mode Enable */\n#define USART_CR2_DIS_NSS_Pos           (3U)\n#define USART_CR2_DIS_NSS_Msk           (0x1UL << USART_CR2_DIS_NSS_Pos)       /*!< 0x00000008 */\n#define USART_CR2_DIS_NSS               USART_CR2_DIS_NSS_Msk                  /*!< Negative Slave Select (NSS) pin management */\n#define USART_CR2_ADDM7_Pos             (4U)\n#define USART_CR2_ADDM7_Msk             (0x1UL << USART_CR2_ADDM7_Pos)         /*!< 0x00000010 */\n#define USART_CR2_ADDM7                 USART_CR2_ADDM7_Msk                    /*!< 7-bit or 4-bit Address Detection */\n#define USART_CR2_LBDL_Pos              (5U)\n#define USART_CR2_LBDL_Msk              (0x1UL << USART_CR2_LBDL_Pos)          /*!< 0x00000020 */\n#define USART_CR2_LBDL                  USART_CR2_LBDL_Msk                     /*!< LIN Break Detection Length */\n#define USART_CR2_LBDIE_Pos             (6U)\n#define USART_CR2_LBDIE_Msk             (0x1UL << USART_CR2_LBDIE_Pos)         /*!< 0x00000040 */\n#define USART_CR2_LBDIE                 USART_CR2_LBDIE_Msk                    /*!< LIN Break Detection Interrupt Enable */\n#define USART_CR2_LBCL_Pos              (8U)\n#define USART_CR2_LBCL_Msk              (0x1UL << USART_CR2_LBCL_Pos)          /*!< 0x00000100 */\n#define USART_CR2_LBCL                  USART_CR2_LBCL_Msk                     /*!< Last Bit Clock pulse */\n#define USART_CR2_CPHA_Pos              (9U)\n#define USART_CR2_CPHA_Msk              (0x1UL << USART_CR2_CPHA_Pos)          /*!< 0x00000200 */\n#define USART_CR2_CPHA                  USART_CR2_CPHA_Msk                     /*!< Clock Phase */\n#define USART_CR2_CPOL_Pos              (10U)\n#define USART_CR2_CPOL_Msk              (0x1UL << USART_CR2_CPOL_Pos)          /*!< 0x00000400 */\n#define USART_CR2_CPOL                  USART_CR2_CPOL_Msk                     /*!< Clock Polarity */\n#define USART_CR2_CLKEN_Pos             (11U)\n#define USART_CR2_CLKEN_Msk             (0x1UL << USART_CR2_CLKEN_Pos)         /*!< 0x00000800 */\n#define USART_CR2_CLKEN                 USART_CR2_CLKEN_Msk                    /*!< Clock Enable */\n#define USART_CR2_STOP_Pos              (12U)\n#define USART_CR2_STOP_Msk              (0x3UL << USART_CR2_STOP_Pos)          /*!< 0x00003000 */\n#define USART_CR2_STOP                  USART_CR2_STOP_Msk                     /*!< STOP[1:0] bits (STOP bits) */\n#define USART_CR2_STOP_0                (0x1UL << USART_CR2_STOP_Pos)           /*!< 0x00001000 */\n#define USART_CR2_STOP_1                (0x2UL << USART_CR2_STOP_Pos)           /*!< 0x00002000 */\n#define USART_CR2_LINEN_Pos             (14U)\n#define USART_CR2_LINEN_Msk             (0x1UL << USART_CR2_LINEN_Pos)         /*!< 0x00004000 */\n#define USART_CR2_LINEN                 USART_CR2_LINEN_Msk                    /*!< LIN mode enable */\n#define USART_CR2_SWAP_Pos              (15U)\n#define USART_CR2_SWAP_Msk              (0x1UL << USART_CR2_SWAP_Pos)          /*!< 0x00008000 */\n#define USART_CR2_SWAP                  USART_CR2_SWAP_Msk                     /*!< SWAP TX/RX pins */\n#define USART_CR2_RXINV_Pos             (16U)\n#define USART_CR2_RXINV_Msk             (0x1UL << USART_CR2_RXINV_Pos)         /*!< 0x00010000 */\n#define USART_CR2_RXINV                 USART_CR2_RXINV_Msk                    /*!< RX pin active level inversion */\n#define USART_CR2_TXINV_Pos             (17U)\n#define USART_CR2_TXINV_Msk             (0x1UL << USART_CR2_TXINV_Pos)         /*!< 0x00020000 */\n#define USART_CR2_TXINV                 USART_CR2_TXINV_Msk                    /*!< TX pin active level inversion */\n#define USART_CR2_DATAINV_Pos           (18U)\n#define USART_CR2_DATAINV_Msk           (0x1UL << USART_CR2_DATAINV_Pos)       /*!< 0x00040000 */\n#define USART_CR2_DATAINV               USART_CR2_DATAINV_Msk                  /*!< Binary data inversion */\n#define USART_CR2_MSBFIRST_Pos          (19U)\n#define USART_CR2_MSBFIRST_Msk          (0x1UL << USART_CR2_MSBFIRST_Pos)      /*!< 0x00080000 */\n#define USART_CR2_MSBFIRST              USART_CR2_MSBFIRST_Msk                 /*!< Most Significant Bit First */\n#define USART_CR2_ABREN_Pos             (20U)\n#define USART_CR2_ABREN_Msk             (0x1UL << USART_CR2_ABREN_Pos)         /*!< 0x00100000 */\n#define USART_CR2_ABREN                 USART_CR2_ABREN_Msk                    /*!< Auto Baud-Rate Enable*/\n#define USART_CR2_ABRMODE_Pos           (21U)\n#define USART_CR2_ABRMODE_Msk           (0x3UL << USART_CR2_ABRMODE_Pos)       /*!< 0x00600000 */\n#define USART_CR2_ABRMODE               USART_CR2_ABRMODE_Msk                  /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */\n#define USART_CR2_ABRMODE_0             (0x1UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00200000 */\n#define USART_CR2_ABRMODE_1             (0x2UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00400000 */\n#define USART_CR2_RTOEN_Pos             (23U)\n#define USART_CR2_RTOEN_Msk             (0x1UL << USART_CR2_RTOEN_Pos)         /*!< 0x00800000 */\n#define USART_CR2_RTOEN                 USART_CR2_RTOEN_Msk                    /*!< Receiver Time-Out enable */\n#define USART_CR2_ADD_Pos               (24U)\n#define USART_CR2_ADD_Msk               (0xFFUL << USART_CR2_ADD_Pos)          /*!< 0xFF000000 */\n#define USART_CR2_ADD                   USART_CR2_ADD_Msk                      /*!< Address of the USART node */\n\n/******************  Bit definition for USART_CR3 register  *******************/\n#define USART_CR3_EIE_Pos               (0U)\n#define USART_CR3_EIE_Msk               (0x1UL << USART_CR3_EIE_Pos)           /*!< 0x00000001 */\n#define USART_CR3_EIE                   USART_CR3_EIE_Msk                      /*!< Error Interrupt Enable */\n#define USART_CR3_IREN_Pos              (1U)\n#define USART_CR3_IREN_Msk              (0x1UL << USART_CR3_IREN_Pos)          /*!< 0x00000002 */\n#define USART_CR3_IREN                  USART_CR3_IREN_Msk                     /*!< IrDA mode Enable */\n#define USART_CR3_IRLP_Pos              (2U)\n#define USART_CR3_IRLP_Msk              (0x1UL << USART_CR3_IRLP_Pos)          /*!< 0x00000004 */\n#define USART_CR3_IRLP                  USART_CR3_IRLP_Msk                     /*!< IrDA Low-Power */\n#define USART_CR3_HDSEL_Pos             (3U)\n#define USART_CR3_HDSEL_Msk             (0x1UL << USART_CR3_HDSEL_Pos)         /*!< 0x00000008 */\n#define USART_CR3_HDSEL                 USART_CR3_HDSEL_Msk                    /*!< Half-Duplex Selection */\n#define USART_CR3_NACK_Pos              (4U)\n#define USART_CR3_NACK_Msk              (0x1UL << USART_CR3_NACK_Pos)          /*!< 0x00000010 */\n#define USART_CR3_NACK                  USART_CR3_NACK_Msk                     /*!< SmartCard NACK enable */\n#define USART_CR3_SCEN_Pos              (5U)\n#define USART_CR3_SCEN_Msk              (0x1UL << USART_CR3_SCEN_Pos)          /*!< 0x00000020 */\n#define USART_CR3_SCEN                  USART_CR3_SCEN_Msk                     /*!< SmartCard mode enable */\n#define USART_CR3_DMAR_Pos              (6U)\n#define USART_CR3_DMAR_Msk              (0x1UL << USART_CR3_DMAR_Pos)          /*!< 0x00000040 */\n#define USART_CR3_DMAR                  USART_CR3_DMAR_Msk                     /*!< DMA Enable Receiver */\n#define USART_CR3_DMAT_Pos              (7U)\n#define USART_CR3_DMAT_Msk              (0x1UL << USART_CR3_DMAT_Pos)          /*!< 0x00000080 */\n#define USART_CR3_DMAT                  USART_CR3_DMAT_Msk                     /*!< DMA Enable Transmitter */\n#define USART_CR3_RTSE_Pos              (8U)\n#define USART_CR3_RTSE_Msk              (0x1UL << USART_CR3_RTSE_Pos)          /*!< 0x00000100 */\n#define USART_CR3_RTSE                  USART_CR3_RTSE_Msk                     /*!< RTS Enable */\n#define USART_CR3_CTSE_Pos              (9U)\n#define USART_CR3_CTSE_Msk              (0x1UL << USART_CR3_CTSE_Pos)          /*!< 0x00000200 */\n#define USART_CR3_CTSE                  USART_CR3_CTSE_Msk                     /*!< CTS Enable */\n#define USART_CR3_CTSIE_Pos             (10U)\n#define USART_CR3_CTSIE_Msk             (0x1UL << USART_CR3_CTSIE_Pos)         /*!< 0x00000400 */\n#define USART_CR3_CTSIE                 USART_CR3_CTSIE_Msk                    /*!< CTS Interrupt Enable */\n#define USART_CR3_ONEBIT_Pos            (11U)\n#define USART_CR3_ONEBIT_Msk            (0x1UL << USART_CR3_ONEBIT_Pos)        /*!< 0x00000800 */\n#define USART_CR3_ONEBIT                USART_CR3_ONEBIT_Msk                   /*!< One sample bit method enable */\n#define USART_CR3_OVRDIS_Pos            (12U)\n#define USART_CR3_OVRDIS_Msk            (0x1UL << USART_CR3_OVRDIS_Pos)        /*!< 0x00001000 */\n#define USART_CR3_OVRDIS                USART_CR3_OVRDIS_Msk                   /*!< Overrun Disable */\n#define USART_CR3_DDRE_Pos              (13U)\n#define USART_CR3_DDRE_Msk              (0x1UL << USART_CR3_DDRE_Pos)          /*!< 0x00002000 */\n#define USART_CR3_DDRE                  USART_CR3_DDRE_Msk                     /*!< DMA Disable on Reception Error */\n#define USART_CR3_DEM_Pos               (14U)\n#define USART_CR3_DEM_Msk               (0x1UL << USART_CR3_DEM_Pos)           /*!< 0x00004000 */\n#define USART_CR3_DEM                   USART_CR3_DEM_Msk                      /*!< Driver Enable Mode */\n#define USART_CR3_DEP_Pos               (15U)\n#define USART_CR3_DEP_Msk               (0x1UL << USART_CR3_DEP_Pos)           /*!< 0x00008000 */\n#define USART_CR3_DEP                   USART_CR3_DEP_Msk                      /*!< Driver Enable Polarity Selection */\n#define USART_CR3_SCARCNT_Pos           (17U)\n#define USART_CR3_SCARCNT_Msk           (0x7UL << USART_CR3_SCARCNT_Pos)       /*!< 0x000E0000 */\n#define USART_CR3_SCARCNT               USART_CR3_SCARCNT_Msk                  /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */\n#define USART_CR3_SCARCNT_0             (0x1UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00020000 */\n#define USART_CR3_SCARCNT_1             (0x2UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00040000 */\n#define USART_CR3_SCARCNT_2             (0x4UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00080000 */\n#define USART_CR3_WUS_Pos               (20U)\n#define USART_CR3_WUS_Msk               (0x3UL << USART_CR3_WUS_Pos)           /*!< 0x00300000 */\n#define USART_CR3_WUS                   USART_CR3_WUS_Msk                      /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */\n#define USART_CR3_WUS_0                 (0x1UL << USART_CR3_WUS_Pos)            /*!< 0x00100000 */\n#define USART_CR3_WUS_1                 (0x2UL << USART_CR3_WUS_Pos)            /*!< 0x00200000 */\n#define USART_CR3_WUFIE_Pos             (22U)\n#define USART_CR3_WUFIE_Msk             (0x1UL << USART_CR3_WUFIE_Pos)         /*!< 0x00400000 */\n#define USART_CR3_WUFIE                 USART_CR3_WUFIE_Msk                    /*!< Wake Up Interrupt Enable */\n#define USART_CR3_TXFTIE_Pos            (23U)\n#define USART_CR3_TXFTIE_Msk            (0x1UL << USART_CR3_TXFTIE_Pos)        /*!< 0x00800000 */\n#define USART_CR3_TXFTIE                USART_CR3_TXFTIE_Msk                   /*!< TXFIFO threshold interrupt enable */\n#define USART_CR3_TCBGTIE_Pos           (24U)\n#define USART_CR3_TCBGTIE_Msk           (0x1UL << USART_CR3_TCBGTIE_Pos)       /*!< 0x01000000 */\n#define USART_CR3_TCBGTIE               USART_CR3_TCBGTIE_Msk                  /*!< Transmission Complete before guard time, interrupt enable */\n#define USART_CR3_RXFTCFG_Pos           (25U)\n#define USART_CR3_RXFTCFG_Msk           (0x7UL << USART_CR3_RXFTCFG_Pos)       /*!< 0x0E000000 */\n#define USART_CR3_RXFTCFG               USART_CR3_RXFTCFG_Msk                  /*!< RXFTCFG [2:0]Receive FIFO threshold configuration */\n#define USART_CR3_RXFTCFG_0             (0x1UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x02000000 */\n#define USART_CR3_RXFTCFG_1             (0x2UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x04000000 */\n#define USART_CR3_RXFTCFG_2             (0x4UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x08000000 */\n#define USART_CR3_RXFTIE_Pos            (28U)\n#define USART_CR3_RXFTIE_Msk            (0x1UL << USART_CR3_RXFTIE_Pos)        /*!< 0x10000000 */\n#define USART_CR3_RXFTIE                USART_CR3_RXFTIE_Msk                   /*!< RXFIFO threshold interrupt enable */\n#define USART_CR3_TXFTCFG_Pos           (29U)\n#define USART_CR3_TXFTCFG_Msk           (0x7UL << USART_CR3_TXFTCFG_Pos)       /*!< 0xE0000000 */\n#define USART_CR3_TXFTCFG               USART_CR3_TXFTCFG_Msk                  /*!< TXFIFO [2:0] threshold configuration */\n#define USART_CR3_TXFTCFG_0             (0x1UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x20000000 */\n#define USART_CR3_TXFTCFG_1             (0x2UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x40000000 */\n#define USART_CR3_TXFTCFG_2             (0x4UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x80000000 */\n\n/******************  Bit definition for USART_BRR register  *******************/\n#define USART_BRR_DIV_FRACTION_Pos      (0U)\n#define USART_BRR_DIV_FRACTION_Msk      (0xFUL << USART_BRR_DIV_FRACTION_Pos)  /*!< 0x0000000F */\n#define USART_BRR_DIV_FRACTION          USART_BRR_DIV_FRACTION_Msk             /*!< Fraction of USARTDIV */\n#define USART_BRR_DIV_MANTISSA_Pos      (4U)\n#define USART_BRR_DIV_MANTISSA_Msk      (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */\n#define USART_BRR_DIV_MANTISSA          USART_BRR_DIV_MANTISSA_Msk             /*!< Mantissa of USARTDIV */\n\n/******************  Bit definition for USART_GTPR register  ******************/\n#define USART_GTPR_PSC_Pos              (0U)\n#define USART_GTPR_PSC_Msk              (0xFFUL << USART_GTPR_PSC_Pos)         /*!< 0x000000FF */\n#define USART_GTPR_PSC                  USART_GTPR_PSC_Msk                     /*!< PSC[7:0] bits (Prescaler value) */\n#define USART_GTPR_GT_Pos               (8U)\n#define USART_GTPR_GT_Msk               (0xFFUL << USART_GTPR_GT_Pos)          /*!< 0x0000FF00 */\n#define USART_GTPR_GT                   USART_GTPR_GT_Msk                      /*!< GT[7:0] bits (Guard time value) */\n\n/*******************  Bit definition for USART_RTOR register  *****************/\n#define USART_RTOR_RTO_Pos              (0U)\n#define USART_RTOR_RTO_Msk              (0xFFFFFFUL << USART_RTOR_RTO_Pos)     /*!< 0x00FFFFFF */\n#define USART_RTOR_RTO                  USART_RTOR_RTO_Msk                     /*!< Receiver Time Out Value */\n#define USART_RTOR_BLEN_Pos             (24U)\n#define USART_RTOR_BLEN_Msk             (0xFFUL << USART_RTOR_BLEN_Pos)        /*!< 0xFF000000 */\n#define USART_RTOR_BLEN                 USART_RTOR_BLEN_Msk                    /*!< Block Length */\n\n/*******************  Bit definition for USART_RQR register  ******************/\n#define USART_RQR_ABRRQ_Pos             (0U)\n#define USART_RQR_ABRRQ_Msk             (0x1UL << USART_RQR_ABRRQ_Pos)         /*!< 0x00000001 */\n#define USART_RQR_ABRRQ                 USART_RQR_ABRRQ_Msk                    /*!< Auto-Baud Rate Request */\n#define USART_RQR_SBKRQ_Pos             (1U)\n#define USART_RQR_SBKRQ_Msk             (0x1UL << USART_RQR_SBKRQ_Pos)         /*!< 0x00000002 */\n#define USART_RQR_SBKRQ                 USART_RQR_SBKRQ_Msk                    /*!< Send Break Request */\n#define USART_RQR_MMRQ_Pos              (2U)\n#define USART_RQR_MMRQ_Msk              (0x1UL << USART_RQR_MMRQ_Pos)          /*!< 0x00000004 */\n#define USART_RQR_MMRQ                  USART_RQR_MMRQ_Msk                     /*!< Mute Mode Request */\n#define USART_RQR_RXFRQ_Pos             (3U)\n#define USART_RQR_RXFRQ_Msk             (0x1UL << USART_RQR_RXFRQ_Pos)         /*!< 0x00000008 */\n#define USART_RQR_RXFRQ                 USART_RQR_RXFRQ_Msk                    /*!< Receive Data flush Request */\n#define USART_RQR_TXFRQ_Pos             (4U)\n#define USART_RQR_TXFRQ_Msk             (0x1UL << USART_RQR_TXFRQ_Pos)         /*!< 0x00000010 */\n#define USART_RQR_TXFRQ                 USART_RQR_TXFRQ_Msk                    /*!< Transmit data flush Request */\n\n/*******************  Bit definition for USART_ISR register  ******************/\n#define USART_ISR_PE_Pos                (0U)\n#define USART_ISR_PE_Msk                (0x1UL << USART_ISR_PE_Pos)            /*!< 0x00000001 */\n#define USART_ISR_PE                    USART_ISR_PE_Msk                       /*!< Parity Error */\n#define USART_ISR_FE_Pos                (1U)\n#define USART_ISR_FE_Msk                (0x1UL << USART_ISR_FE_Pos)            /*!< 0x00000002 */\n#define USART_ISR_FE                    USART_ISR_FE_Msk                       /*!< Framing Error */\n#define USART_ISR_NE_Pos                (2U)\n#define USART_ISR_NE_Msk                (0x1UL << USART_ISR_NE_Pos)            /*!< 0x00000004 */\n#define USART_ISR_NE                    USART_ISR_NE_Msk                       /*!< Noise detected Flag */\n#define USART_ISR_ORE_Pos               (3U)\n#define USART_ISR_ORE_Msk               (0x1UL << USART_ISR_ORE_Pos)           /*!< 0x00000008 */\n#define USART_ISR_ORE                   USART_ISR_ORE_Msk                      /*!< OverRun Error */\n#define USART_ISR_IDLE_Pos              (4U)\n#define USART_ISR_IDLE_Msk              (0x1UL << USART_ISR_IDLE_Pos)          /*!< 0x00000010 */\n#define USART_ISR_IDLE                  USART_ISR_IDLE_Msk                     /*!< IDLE line detected */\n#define USART_ISR_RXNE_RXFNE_Pos        (5U)\n#define USART_ISR_RXNE_RXFNE_Msk        (0x1UL << USART_ISR_RXNE_RXFNE_Pos)    /*!< 0x00000020 */\n#define USART_ISR_RXNE_RXFNE            USART_ISR_RXNE_RXFNE_Msk               /*!< Read Data Register or RX FIFO Not Empty */\n#define USART_ISR_TC_Pos                (6U)\n#define USART_ISR_TC_Msk                (0x1UL << USART_ISR_TC_Pos)            /*!< 0x00000040 */\n#define USART_ISR_TC                    USART_ISR_TC_Msk                       /*!< Transmission Complete */\n#define USART_ISR_TXE_TXFNF_Pos         (7U)\n#define USART_ISR_TXE_TXFNF_Msk         (0x1UL << USART_ISR_TXE_TXFNF_Pos)     /*!< 0x00000080 */\n#define USART_ISR_TXE_TXFNF             USART_ISR_TXE_TXFNF_Msk                /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */\n#define USART_ISR_LBDF_Pos              (8U)\n#define USART_ISR_LBDF_Msk              (0x1UL << USART_ISR_LBDF_Pos)          /*!< 0x00000100 */\n#define USART_ISR_LBDF                  USART_ISR_LBDF_Msk                     /*!< LIN Break Detection Flag */\n#define USART_ISR_CTSIF_Pos             (9U)\n#define USART_ISR_CTSIF_Msk             (0x1UL << USART_ISR_CTSIF_Pos)         /*!< 0x00000200 */\n#define USART_ISR_CTSIF                 USART_ISR_CTSIF_Msk                    /*!< CTS interrupt flag */\n#define USART_ISR_CTS_Pos               (10U)\n#define USART_ISR_CTS_Msk               (0x1UL << USART_ISR_CTS_Pos)           /*!< 0x00000400 */\n#define USART_ISR_CTS                   USART_ISR_CTS_Msk                      /*!< CTS flag */\n#define USART_ISR_RTOF_Pos              (11U)\n#define USART_ISR_RTOF_Msk              (0x1UL << USART_ISR_RTOF_Pos)          /*!< 0x00000800 */\n#define USART_ISR_RTOF                  USART_ISR_RTOF_Msk                     /*!< Receiver Time Out */\n#define USART_ISR_EOBF_Pos              (12U)\n#define USART_ISR_EOBF_Msk              (0x1UL << USART_ISR_EOBF_Pos)          /*!< 0x00001000 */\n#define USART_ISR_EOBF                  USART_ISR_EOBF_Msk                     /*!< End Of Block Flag */\n#define USART_ISR_UDR_Pos               (13U)\n#define USART_ISR_UDR_Msk               (0x1UL << USART_ISR_UDR_Pos)           /*!< 0x00002000 */\n#define USART_ISR_UDR                   USART_ISR_UDR_Msk                      /*!< SPI slave underrun error flag */\n#define USART_ISR_ABRE_Pos              (14U)\n#define USART_ISR_ABRE_Msk              (0x1UL << USART_ISR_ABRE_Pos)          /*!< 0x00004000 */\n#define USART_ISR_ABRE                  USART_ISR_ABRE_Msk                     /*!< Auto-Baud Rate Error */\n#define USART_ISR_ABRF_Pos              (15U)\n#define USART_ISR_ABRF_Msk              (0x1UL << USART_ISR_ABRF_Pos)          /*!< 0x00008000 */\n#define USART_ISR_ABRF                  USART_ISR_ABRF_Msk                     /*!< Auto-Baud Rate Flag */\n#define USART_ISR_BUSY_Pos              (16U)\n#define USART_ISR_BUSY_Msk              (0x1UL << USART_ISR_BUSY_Pos)          /*!< 0x00010000 */\n#define USART_ISR_BUSY                  USART_ISR_BUSY_Msk                     /*!< Busy Flag */\n#define USART_ISR_CMF_Pos               (17U)\n#define USART_ISR_CMF_Msk               (0x1UL << USART_ISR_CMF_Pos)           /*!< 0x00020000 */\n#define USART_ISR_CMF                   USART_ISR_CMF_Msk                      /*!< Character Match Flag */\n#define USART_ISR_SBKF_Pos              (18U)\n#define USART_ISR_SBKF_Msk              (0x1UL << USART_ISR_SBKF_Pos)          /*!< 0x00040000 */\n#define USART_ISR_SBKF                  USART_ISR_SBKF_Msk                     /*!< Send Break Flag */\n#define USART_ISR_RWU_Pos               (19U)\n#define USART_ISR_RWU_Msk               (0x1UL << USART_ISR_RWU_Pos)           /*!< 0x00080000 */\n#define USART_ISR_RWU                   USART_ISR_RWU_Msk                      /*!< Receive Wake Up from mute mode Flag */\n#define USART_ISR_WUF_Pos               (20U)\n#define USART_ISR_WUF_Msk               (0x1UL << USART_ISR_WUF_Pos)           /*!< 0x00100000 */\n#define USART_ISR_WUF                   USART_ISR_WUF_Msk                      /*!< Wake Up from stop mode Flag */\n#define USART_ISR_TEACK_Pos             (21U)\n#define USART_ISR_TEACK_Msk             (0x1UL << USART_ISR_TEACK_Pos)         /*!< 0x00200000 */\n#define USART_ISR_TEACK                 USART_ISR_TEACK_Msk                    /*!< Transmit Enable Acknowledge Flag */\n#define USART_ISR_REACK_Pos             (22U)\n#define USART_ISR_REACK_Msk             (0x1UL << USART_ISR_REACK_Pos)         /*!< 0x00400000 */\n#define USART_ISR_REACK                 USART_ISR_REACK_Msk                    /*!< Receive Enable Acknowledge Flag */\n#define USART_ISR_TXFE_Pos              (23U)\n#define USART_ISR_TXFE_Msk              (0x1UL << USART_ISR_TXFE_Pos)          /*!< 0x00800000 */\n#define USART_ISR_TXFE                  USART_ISR_TXFE_Msk                     /*!< TXFIFO Empty */\n#define USART_ISR_RXFF_Pos              (24U)\n#define USART_ISR_RXFF_Msk              (0x1UL << USART_ISR_RXFF_Pos)          /*!< 0x01000000 */\n#define USART_ISR_RXFF                  USART_ISR_RXFF_Msk                     /*!< RXFIFO Full Flag */\n#define USART_ISR_TCBGT_Pos             (25U)\n#define USART_ISR_TCBGT_Msk             (0x1UL << USART_ISR_TCBGT_Pos)         /*!< 0x02000000 */\n#define USART_ISR_TCBGT                 USART_ISR_TCBGT_Msk                    /*!< Transmission complete before guard time Flag */\n#define USART_ISR_RXFT_Pos              (26U)\n#define USART_ISR_RXFT_Msk              (0x1UL << USART_ISR_RXFT_Pos)          /*!< 0x04000000 */\n#define USART_ISR_RXFT                  USART_ISR_RXFT_Msk                     /*!< RXFIFO threshold Flag */\n#define USART_ISR_TXFT_Pos              (27U)\n#define USART_ISR_TXFT_Msk              (0x1UL << USART_ISR_TXFT_Pos)          /*!< 0x08000000 */\n#define USART_ISR_TXFT                  USART_ISR_TXFT_Msk                     /*!< TXFIFO threshold Flag */\n\n/*******************  Bit definition for USART_ICR register  ******************/\n#define USART_ICR_PECF_Pos              (0U)\n#define USART_ICR_PECF_Msk              (0x1UL << USART_ICR_PECF_Pos)          /*!< 0x00000001 */\n#define USART_ICR_PECF                  USART_ICR_PECF_Msk                     /*!< Parity Error Clear Flag */\n#define USART_ICR_FECF_Pos              (1U)\n#define USART_ICR_FECF_Msk              (0x1UL << USART_ICR_FECF_Pos)          /*!< 0x00000002 */\n#define USART_ICR_FECF                  USART_ICR_FECF_Msk                     /*!< Framing Error Clear Flag */\n#define USART_ICR_NECF_Pos              (2U)\n#define USART_ICR_NECF_Msk              (0x1UL << USART_ICR_NECF_Pos)          /*!< 0x00000004 */\n#define USART_ICR_NECF                  USART_ICR_NECF_Msk                     /*!< Noise detected Clear Flag */\n#define USART_ICR_ORECF_Pos             (3U)\n#define USART_ICR_ORECF_Msk             (0x1UL << USART_ICR_ORECF_Pos)         /*!< 0x00000008 */\n#define USART_ICR_ORECF                 USART_ICR_ORECF_Msk                    /*!< OverRun Error Clear Flag */\n#define USART_ICR_IDLECF_Pos            (4U)\n#define USART_ICR_IDLECF_Msk            (0x1UL << USART_ICR_IDLECF_Pos)        /*!< 0x00000010 */\n#define USART_ICR_IDLECF                USART_ICR_IDLECF_Msk                   /*!< IDLE line detected Clear Flag */\n#define USART_ICR_TXFECF_Pos            (5U)\n#define USART_ICR_TXFECF_Msk            (0x1UL << USART_ICR_TXFECF_Pos)        /*!< 0x00000020 */\n#define USART_ICR_TXFECF                USART_ICR_TXFECF_Msk                   /*!< TXFIFO empty clear flag */\n#define USART_ICR_TCCF_Pos              (6U)\n#define USART_ICR_TCCF_Msk              (0x1UL << USART_ICR_TCCF_Pos)          /*!< 0x00000040 */\n#define USART_ICR_TCCF                  USART_ICR_TCCF_Msk                     /*!< Transmission Complete Clear Flag */\n#define USART_ICR_TCBGTCF_Pos           (7U)\n#define USART_ICR_TCBGTCF_Msk           (0x1UL << USART_ICR_TCBGTCF_Pos)       /*!< 0x00000080 */\n#define USART_ICR_TCBGTCF               USART_ICR_TCBGTCF_Msk                  /*!< Transmission complete before guard time Clear Flag */\n#define USART_ICR_LBDCF_Pos             (8U)\n#define USART_ICR_LBDCF_Msk             (0x1UL << USART_ICR_LBDCF_Pos)         /*!< 0x00000100 */\n#define USART_ICR_LBDCF                 USART_ICR_LBDCF_Msk                    /*!< LIN Break Detection Clear Flag */\n#define USART_ICR_CTSCF_Pos             (9U)\n#define USART_ICR_CTSCF_Msk             (0x1UL << USART_ICR_CTSCF_Pos)         /*!< 0x00000200 */\n#define USART_ICR_CTSCF                 USART_ICR_CTSCF_Msk                    /*!< CTS Interrupt Clear Flag */\n#define USART_ICR_RTOCF_Pos             (11U)\n#define USART_ICR_RTOCF_Msk             (0x1UL << USART_ICR_RTOCF_Pos)         /*!< 0x00000800 */\n#define USART_ICR_RTOCF                 USART_ICR_RTOCF_Msk                    /*!< Receiver Time Out Clear Flag */\n#define USART_ICR_EOBCF_Pos             (12U)\n#define USART_ICR_EOBCF_Msk             (0x1UL << USART_ICR_EOBCF_Pos)         /*!< 0x00001000 */\n#define USART_ICR_EOBCF                 USART_ICR_EOBCF_Msk                    /*!< End Of Block Clear Flag */\n#define USART_ICR_UDRCF_Pos             (13U)\n#define USART_ICR_UDRCF_Msk             (0x1UL << USART_ICR_UDRCF_Pos)         /*!< 0x00002000 */\n#define USART_ICR_UDRCF                 USART_ICR_UDRCF_Msk                    /*!< SPI slave underrun clear flag */\n#define USART_ICR_CMCF_Pos              (17U)\n#define USART_ICR_CMCF_Msk              (0x1UL << USART_ICR_CMCF_Pos)          /*!< 0x00020000 */\n#define USART_ICR_CMCF                  USART_ICR_CMCF_Msk                     /*!< Character Match Clear Flag */\n#define USART_ICR_WUCF_Pos              (20U)\n#define USART_ICR_WUCF_Msk              (0x1UL << USART_ICR_WUCF_Pos)          /*!< 0x00100000 */\n#define USART_ICR_WUCF                  USART_ICR_WUCF_Msk                     /*!< Wake Up from stop mode Clear Flag */\n\n/*******************  Bit definition for USART_RDR register  ******************/\n#define USART_RDR_RDR_Pos               (0U)\n#define USART_RDR_RDR_Msk               (0x1FFUL << USART_RDR_RDR_Pos)         /*!< 0x000001FF */\n#define USART_RDR_RDR                   USART_RDR_RDR_Msk                      /*!< RDR[8:0] bits (Receive Data value) */\n\n/*******************  Bit definition for USART_TDR register  ******************/\n#define USART_TDR_TDR_Pos               (0U)\n#define USART_TDR_TDR_Msk               (0x1FFUL << USART_TDR_TDR_Pos)         /*!< 0x000001FF */\n#define USART_TDR_TDR                   USART_TDR_TDR_Msk                      /*!< TDR[8:0] bits (Transmit Data value) */\n\n/*******************  Bit definition for USART_PRESC register  ******************/\n#define USART_PRESC_PRESCALER_Pos       (0U)\n#define USART_PRESC_PRESCALER_Msk       (0xFUL << USART_PRESC_PRESCALER_Pos)   /*!< 0x0000000F */\n#define USART_PRESC_PRESCALER           USART_PRESC_PRESCALER_Msk              /*!< PRESCALER[3:0] bits (Clock prescaler) */\n#define USART_PRESC_PRESCALER_0         (0x1UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000001 */\n#define USART_PRESC_PRESCALER_1         (0x2UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000002 */\n#define USART_PRESC_PRESCALER_2         (0x4UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000004 */\n#define USART_PRESC_PRESCALER_3         (0x8UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000008 */\n\n/******************************************************************************/\n/*                                                                            */\n/*           Single Wire Protocol Master Interface (SWPMI)                    */\n/*                                                                            */\n/******************************************************************************/\n\n/*******************  Bit definition for SWPMI_CR register   ********************/\n#define SWPMI_CR_RXDMA_Pos       (0U)\n#define SWPMI_CR_RXDMA_Msk       (0x1UL << SWPMI_CR_RXDMA_Pos)                 /*!< 0x00000001 */\n#define SWPMI_CR_RXDMA           SWPMI_CR_RXDMA_Msk                            /*!<Reception DMA enable                                 */\n#define SWPMI_CR_TXDMA_Pos       (1U)\n#define SWPMI_CR_TXDMA_Msk       (0x1UL << SWPMI_CR_TXDMA_Pos)                 /*!< 0x00000002 */\n#define SWPMI_CR_TXDMA           SWPMI_CR_TXDMA_Msk                            /*!<Transmission DMA enable                              */\n#define SWPMI_CR_RXMODE_Pos      (2U)\n#define SWPMI_CR_RXMODE_Msk      (0x1UL << SWPMI_CR_RXMODE_Pos)                /*!< 0x00000004 */\n#define SWPMI_CR_RXMODE          SWPMI_CR_RXMODE_Msk                           /*!<Reception buffering mode                             */\n#define SWPMI_CR_TXMODE_Pos      (3U)\n#define SWPMI_CR_TXMODE_Msk      (0x1UL << SWPMI_CR_TXMODE_Pos)                /*!< 0x00000008 */\n#define SWPMI_CR_TXMODE          SWPMI_CR_TXMODE_Msk                           /*!<Transmission buffering mode                          */\n#define SWPMI_CR_LPBK_Pos        (4U)\n#define SWPMI_CR_LPBK_Msk        (0x1UL << SWPMI_CR_LPBK_Pos)                  /*!< 0x00000010 */\n#define SWPMI_CR_LPBK            SWPMI_CR_LPBK_Msk                             /*!<Loopback mode enable                                 */\n#define SWPMI_CR_SWPACT_Pos      (5U)\n#define SWPMI_CR_SWPACT_Msk      (0x1UL << SWPMI_CR_SWPACT_Pos)                /*!< 0x00000020 */\n#define SWPMI_CR_SWPACT          SWPMI_CR_SWPACT_Msk                           /*!<Single wire protocol master interface activate       */\n#define SWPMI_CR_DEACT_Pos       (10U)\n#define SWPMI_CR_DEACT_Msk       (0x1UL << SWPMI_CR_DEACT_Pos)                 /*!< 0x00000400 */\n#define SWPMI_CR_DEACT           SWPMI_CR_DEACT_Msk                            /*!<Single wire protocol master interface deactivate     */\n#define SWPMI_CR_SWPEN_Pos       (11U)\n#define SWPMI_CR_SWPEN_Msk       (0x1UL << SWPMI_CR_SWPEN_Pos)                 /*!< 0x00000800 */\n#define SWPMI_CR_SWPEN           SWPMI_CR_SWPEN_Msk                            /*!<Single wire protocol master transceiver enable       */\n\n/*******************  Bit definition for SWPMI_BRR register  ********************/\n#define SWPMI_BRR_BR_Pos         (0U)\n#define SWPMI_BRR_BR_Msk         (0xFFUL << SWPMI_BRR_BR_Pos)                  /*!< 0x000000FF */\n#define SWPMI_BRR_BR             SWPMI_BRR_BR_Msk                              /*!<BR[7:0] bits (Bitrate prescaler) */\n\n/*******************  Bit definition for SWPMI_ISR register  ********************/\n#define SWPMI_ISR_RXBFF_Pos      (0U)\n#define SWPMI_ISR_RXBFF_Msk      (0x1UL << SWPMI_ISR_RXBFF_Pos)                /*!< 0x00000001 */\n#define SWPMI_ISR_RXBFF          SWPMI_ISR_RXBFF_Msk                           /*!<Receive buffer full flag        */\n#define SWPMI_ISR_TXBEF_Pos      (1U)\n#define SWPMI_ISR_TXBEF_Msk      (0x1UL << SWPMI_ISR_TXBEF_Pos)                /*!< 0x00000002 */\n#define SWPMI_ISR_TXBEF          SWPMI_ISR_TXBEF_Msk                           /*!<Transmit buffer empty flag      */\n#define SWPMI_ISR_RXBERF_Pos     (2U)\n#define SWPMI_ISR_RXBERF_Msk     (0x1UL << SWPMI_ISR_RXBERF_Pos)               /*!< 0x00000004 */\n#define SWPMI_ISR_RXBERF         SWPMI_ISR_RXBERF_Msk                          /*!<Receive CRC error flag          */\n#define SWPMI_ISR_RXOVRF_Pos     (3U)\n#define SWPMI_ISR_RXOVRF_Msk     (0x1UL << SWPMI_ISR_RXOVRF_Pos)               /*!< 0x00000008 */\n#define SWPMI_ISR_RXOVRF         SWPMI_ISR_RXOVRF_Msk                          /*!<Receive overrun error flag      */\n#define SWPMI_ISR_TXUNRF_Pos     (4U)\n#define SWPMI_ISR_TXUNRF_Msk     (0x1UL << SWPMI_ISR_TXUNRF_Pos)               /*!< 0x00000010 */\n#define SWPMI_ISR_TXUNRF         SWPMI_ISR_TXUNRF_Msk                          /*!<Transmit underrun error flag    */\n#define SWPMI_ISR_RXNE_Pos       (5U)\n#define SWPMI_ISR_RXNE_Msk       (0x1UL << SWPMI_ISR_RXNE_Pos)                 /*!< 0x00000020 */\n#define SWPMI_ISR_RXNE           SWPMI_ISR_RXNE_Msk                            /*!<Receive data register not empty */\n#define SWPMI_ISR_TXE_Pos        (6U)\n#define SWPMI_ISR_TXE_Msk        (0x1UL << SWPMI_ISR_TXE_Pos)                  /*!< 0x00000040 */\n#define SWPMI_ISR_TXE            SWPMI_ISR_TXE_Msk                             /*!<Transmit data register empty    */\n#define SWPMI_ISR_TCF_Pos        (7U)\n#define SWPMI_ISR_TCF_Msk        (0x1UL << SWPMI_ISR_TCF_Pos)                  /*!< 0x00000080 */\n#define SWPMI_ISR_TCF            SWPMI_ISR_TCF_Msk                             /*!<Transfer complete flag          */\n#define SWPMI_ISR_SRF_Pos        (8U)\n#define SWPMI_ISR_SRF_Msk        (0x1UL << SWPMI_ISR_SRF_Pos)                  /*!< 0x00000100 */\n#define SWPMI_ISR_SRF            SWPMI_ISR_SRF_Msk                             /*!<Slave resume flag               */\n#define SWPMI_ISR_SUSP_Pos       (9U)\n#define SWPMI_ISR_SUSP_Msk       (0x1UL << SWPMI_ISR_SUSP_Pos)                 /*!< 0x00000200 */\n#define SWPMI_ISR_SUSP           SWPMI_ISR_SUSP_Msk                            /*!<SUSPEND flag                    */\n#define SWPMI_ISR_DEACTF_Pos     (10U)\n#define SWPMI_ISR_DEACTF_Msk     (0x1UL << SWPMI_ISR_DEACTF_Pos)               /*!< 0x00000400 */\n#define SWPMI_ISR_DEACTF         SWPMI_ISR_DEACTF_Msk                          /*!<DEACTIVATED flag                */\n#define SWPMI_ISR_RDYF_Pos       (11U)\n#define SWPMI_ISR_RDYF_Msk       (0x1UL << SWPMI_ISR_RDYF_Pos)                 /*!< 0x00000800 */\n#define SWPMI_ISR_RDYF           SWPMI_ISR_RDYF_Msk                            /*!<Transceiver ready flag          */\n\n/*******************  Bit definition for SWPMI_ICR register  ********************/\n#define SWPMI_ICR_CRXBFF_Pos     (0U)\n#define SWPMI_ICR_CRXBFF_Msk     (0x1UL << SWPMI_ICR_CRXBFF_Pos)               /*!< 0x00000001 */\n#define SWPMI_ICR_CRXBFF         SWPMI_ICR_CRXBFF_Msk                          /*!<Clear receive buffer full flag       */\n#define SWPMI_ICR_CTXBEF_Pos     (1U)\n#define SWPMI_ICR_CTXBEF_Msk     (0x1UL << SWPMI_ICR_CTXBEF_Pos)               /*!< 0x00000002 */\n#define SWPMI_ICR_CTXBEF         SWPMI_ICR_CTXBEF_Msk                          /*!<Clear transmit buffer empty flag     */\n#define SWPMI_ICR_CRXBERF_Pos    (2U)\n#define SWPMI_ICR_CRXBERF_Msk    (0x1UL << SWPMI_ICR_CRXBERF_Pos)              /*!< 0x00000004 */\n#define SWPMI_ICR_CRXBERF        SWPMI_ICR_CRXBERF_Msk                         /*!<Clear receive CRC error flag         */\n#define SWPMI_ICR_CRXOVRF_Pos    (3U)\n#define SWPMI_ICR_CRXOVRF_Msk    (0x1UL << SWPMI_ICR_CRXOVRF_Pos)              /*!< 0x00000008 */\n#define SWPMI_ICR_CRXOVRF        SWPMI_ICR_CRXOVRF_Msk                         /*!<Clear receive overrun error flag     */\n#define SWPMI_ICR_CTXUNRF_Pos    (4U)\n#define SWPMI_ICR_CTXUNRF_Msk    (0x1UL << SWPMI_ICR_CTXUNRF_Pos)              /*!< 0x00000010 */\n#define SWPMI_ICR_CTXUNRF        SWPMI_ICR_CTXUNRF_Msk                         /*!<Clear transmit underrun error flag   */\n#define SWPMI_ICR_CTCF_Pos       (7U)\n#define SWPMI_ICR_CTCF_Msk       (0x1UL << SWPMI_ICR_CTCF_Pos)                 /*!< 0x00000080 */\n#define SWPMI_ICR_CTCF           SWPMI_ICR_CTCF_Msk                            /*!<Clear transfer complete flag         */\n#define SWPMI_ICR_CSRF_Pos       (8U)\n#define SWPMI_ICR_CSRF_Msk       (0x1UL << SWPMI_ICR_CSRF_Pos)                 /*!< 0x00000100 */\n#define SWPMI_ICR_CSRF           SWPMI_ICR_CSRF_Msk                            /*!<Clear slave resume flag              */\n#define SWPMI_ICR_CRDYF_Pos      (11U)\n#define SWPMI_ICR_CRDYF_Msk      (0x1UL << SWPMI_ICR_CRDYF_Pos)                /*!< 0x00000800 */\n#define SWPMI_ICR_CRDYF          SWPMI_ICR_CRDYF_Msk                           /*!<Clear transceiver ready flag         */\n\n/*******************  Bit definition for SWPMI_IER register  ********************/\n#define SWPMI_IER_RXBFIE_Pos     (0U)\n#define SWPMI_IER_RXBFIE_Msk     (0x1UL << SWPMI_IER_RXBFIE_Pos)               /*!< 0x00000001 */\n#define SWPMI_IER_RXBFIE         SWPMI_IER_RXBFIE_Msk                          /*!<Receive buffer full interrupt enable        */\n#define SWPMI_IER_TXBEIE_Pos     (1U)\n#define SWPMI_IER_TXBEIE_Msk     (0x1UL << SWPMI_IER_TXBEIE_Pos)               /*!< 0x00000002 */\n#define SWPMI_IER_TXBEIE         SWPMI_IER_TXBEIE_Msk                          /*!<Transmit buffer empty interrupt enable      */\n#define SWPMI_IER_RXBERIE_Pos    (2U)\n#define SWPMI_IER_RXBERIE_Msk    (0x1UL << SWPMI_IER_RXBERIE_Pos)              /*!< 0x00000004 */\n#define SWPMI_IER_RXBERIE        SWPMI_IER_RXBERIE_Msk                         /*!<Receive CRC error interrupt enable          */\n#define SWPMI_IER_RXOVRIE_Pos    (3U)\n#define SWPMI_IER_RXOVRIE_Msk    (0x1UL << SWPMI_IER_RXOVRIE_Pos)              /*!< 0x00000008 */\n#define SWPMI_IER_RXOVRIE        SWPMI_IER_RXOVRIE_Msk                         /*!<Receive overrun error interrupt enable      */\n#define SWPMI_IER_TXUNRIE_Pos    (4U)\n#define SWPMI_IER_TXUNRIE_Msk    (0x1UL << SWPMI_IER_TXUNRIE_Pos)              /*!< 0x00000010 */\n#define SWPMI_IER_TXUNRIE        SWPMI_IER_TXUNRIE_Msk                         /*!<Transmit underrun error interrupt enable    */\n#define SWPMI_IER_RIE_Pos        (5U)\n#define SWPMI_IER_RIE_Msk        (0x1UL << SWPMI_IER_RIE_Pos)                  /*!< 0x00000020 */\n#define SWPMI_IER_RIE            SWPMI_IER_RIE_Msk                             /*!<Receive interrupt enable                    */\n#define SWPMI_IER_TIE_Pos        (6U)\n#define SWPMI_IER_TIE_Msk        (0x1UL << SWPMI_IER_TIE_Pos)                  /*!< 0x00000040 */\n#define SWPMI_IER_TIE            SWPMI_IER_TIE_Msk                             /*!<Transmit interrupt enable                   */\n#define SWPMI_IER_TCIE_Pos       (7U)\n#define SWPMI_IER_TCIE_Msk       (0x1UL << SWPMI_IER_TCIE_Pos)                 /*!< 0x00000080 */\n#define SWPMI_IER_TCIE           SWPMI_IER_TCIE_Msk                            /*!<Transmit complete interrupt enable          */\n#define SWPMI_IER_SRIE_Pos       (8U)\n#define SWPMI_IER_SRIE_Msk       (0x1UL << SWPMI_IER_SRIE_Pos)                 /*!< 0x00000100 */\n#define SWPMI_IER_SRIE           SWPMI_IER_SRIE_Msk                            /*!<Slave resume interrupt enable               */\n#define SWPMI_IER_RDYIE_Pos      (11U)\n#define SWPMI_IER_RDYIE_Msk      (0x1UL << SWPMI_IER_RDYIE_Pos)                /*!< 0x00000800 */\n#define SWPMI_IER_RDYIE          SWPMI_IER_RDYIE_Msk                           /*!<Transceiver ready interrupt enable          */\n\n/*******************  Bit definition for SWPMI_RFL register  ********************/\n#define SWPMI_RFL_RFL_Pos        (0U)\n#define SWPMI_RFL_RFL_Msk        (0x1FUL << SWPMI_RFL_RFL_Pos)                 /*!< 0x0000001F */\n#define SWPMI_RFL_RFL            SWPMI_RFL_RFL_Msk                             /*!<RFL[4:0] bits (Receive Frame length) */\n#define SWPMI_RFL_RFL_0_1        ((uint32_t)0x00000003)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */\n\n/*******************  Bit definition for SWPMI_TDR register  ********************/\n#define SWPMI_TDR_TD_Pos         (0U)\n#define SWPMI_TDR_TD_Msk         (0xFFFFFFFFUL << SWPMI_TDR_TD_Pos)            /*!< 0xFFFFFFFF */\n#define SWPMI_TDR_TD             SWPMI_TDR_TD_Msk                              /*!<Transmit Data Register         */\n\n/*******************  Bit definition for SWPMI_RDR register  ********************/\n#define SWPMI_RDR_RD_Pos         (0U)\n#define SWPMI_RDR_RD_Msk         (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos)            /*!< 0xFFFFFFFF */\n#define SWPMI_RDR_RD             SWPMI_RDR_RD_Msk                              /*!<Receive Data Register           */\n\n\n/*******************  Bit definition for SWPMI_OR register  ********************/\n#define SWPMI_OR_TBYP_Pos        (0U)\n#define SWPMI_OR_TBYP_Msk        (0x1UL << SWPMI_OR_TBYP_Pos)                  /*!< 0x00000001 */\n#define SWPMI_OR_TBYP            SWPMI_OR_TBYP_Msk                             /*!<SWP Transceiver Bypass */\n#define SWPMI_OR_CLASS_Pos       (1U)\n#define SWPMI_OR_CLASS_Msk       (0x1UL << SWPMI_OR_CLASS_Pos)                 /*!< 0x00000002 */\n#define SWPMI_OR_CLASS           SWPMI_OR_CLASS_Msk                            /*!<SWP CLASS selection */\n\n/******************************************************************************/\n/*                                                                            */\n/*                            Window WATCHDOG                                 */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for WWDG_CR register  ********************/\n#define WWDG_CR_T_Pos           (0U)\n#define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                      /*!< 0x0000007F */\n#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */\n#define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x00000001 */\n#define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x00000002 */\n#define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x00000004 */\n#define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x00000008 */\n#define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x00000010 */\n#define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x00000020 */\n#define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x00000040 */\n\n#define WWDG_CR_WDGA_Pos        (7U)\n#define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                    /*!< 0x00000080 */\n#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */\n\n/*******************  Bit definition for WWDG_CFR register  *******************/\n#define WWDG_CFR_W_Pos          (0U)\n#define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                     /*!< 0x0000007F */\n#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */\n#define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */\n#define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */\n#define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */\n#define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */\n#define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */\n#define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */\n#define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */\n\n#define WWDG_CFR_EWI_Pos        (9U)\n#define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                    /*!< 0x00000200 */\n#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */\n\n#define WWDG_CFR_WDGTB_Pos      (11U)\n#define WWDG_CFR_WDGTB_Msk      (0x7UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00003800 */\n#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[2:0] bits (Timer Base) */\n#define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000800 */\n#define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00001000 */\n#define WWDG_CFR_WDGTB_2        (0x4UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00002000 */\n\n/*******************  Bit definition for WWDG_SR register  ********************/\n#define WWDG_SR_EWIF_Pos        (0U)\n#define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                    /*!< 0x00000001 */\n#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                                DBG                                         */\n/*                                                                            */\n/******************************************************************************/\n/*********************************  DEVICE ID  ********************************/\n#define STM32H7_DEV_ID           0x450UL\n\n/********************  Bit definition for DBGMCU_IDCODE register  *************/\n#define DBGMCU_IDCODE_DEV_ID_Pos          (0U)\n#define DBGMCU_IDCODE_DEV_ID_Msk          (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */\n#define DBGMCU_IDCODE_DEV_ID              DBGMCU_IDCODE_DEV_ID_Msk\n#define DBGMCU_IDCODE_REV_ID_Pos          (16U)\n#define DBGMCU_IDCODE_REV_ID_Msk          (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */\n#define DBGMCU_IDCODE_REV_ID              DBGMCU_IDCODE_REV_ID_Msk\n\n/********************  Bit definition for DBGMCU_CR register  *****************/\n#define DBGMCU_CR_DBG_SLEEPD1_Pos         (0U)\n#define DBGMCU_CR_DBG_SLEEPD1_Msk         (0x1UL << DBGMCU_CR_DBG_SLEEPD1_Pos) /*!< 0x00000001 */\n#define DBGMCU_CR_DBG_SLEEPD1             DBGMCU_CR_DBG_SLEEPD1_Msk\n#define DBGMCU_CR_DBG_STOPD1_Pos          (1U)\n#define DBGMCU_CR_DBG_STOPD1_Msk          (0x1UL << DBGMCU_CR_DBG_STOPD1_Pos)  /*!< 0x00000002 */\n#define DBGMCU_CR_DBG_STOPD1              DBGMCU_CR_DBG_STOPD1_Msk\n#define DBGMCU_CR_DBG_STANDBYD1_Pos       (2U)\n#define DBGMCU_CR_DBG_STANDBYD1_Msk       (0x1UL << DBGMCU_CR_DBG_STANDBYD1_Pos) /*!< 0x00000004 */\n#define DBGMCU_CR_DBG_STANDBYD1           DBGMCU_CR_DBG_STANDBYD1_Msk\n#define DBGMCU_CR_DBG_TRACECKEN_Pos       (20U)\n#define DBGMCU_CR_DBG_TRACECKEN_Msk       (0x1UL << DBGMCU_CR_DBG_TRACECKEN_Pos) /*!< 0x00100000 */\n#define DBGMCU_CR_DBG_TRACECKEN           DBGMCU_CR_DBG_TRACECKEN_Msk\n#define DBGMCU_CR_DBG_CKD1EN_Pos          (21U)\n#define DBGMCU_CR_DBG_CKD1EN_Msk          (0x1UL << DBGMCU_CR_DBG_CKD1EN_Pos)  /*!< 0x00200000 */\n#define DBGMCU_CR_DBG_CKD1EN              DBGMCU_CR_DBG_CKD1EN_Msk\n#define DBGMCU_CR_DBG_CKD3EN_Pos          (22U)\n#define DBGMCU_CR_DBG_CKD3EN_Msk          (0x1UL << DBGMCU_CR_DBG_CKD3EN_Pos)  /*!< 0x00400000 */\n#define DBGMCU_CR_DBG_CKD3EN              DBGMCU_CR_DBG_CKD3EN_Msk\n#define DBGMCU_CR_DBG_TRGOEN_Pos          (28U)\n#define DBGMCU_CR_DBG_TRGOEN_Msk          (0x1UL << DBGMCU_CR_DBG_TRGOEN_Pos)  /*!< 0x10000000 */\n#define DBGMCU_CR_DBG_TRGOEN              DBGMCU_CR_DBG_TRGOEN_Msk\n\n/********************  Bit definition for APB3FZ1 register  ************/\n#define DBGMCU_APB3FZ1_DBG_WWDG1_Pos      (6U)\n#define DBGMCU_APB3FZ1_DBG_WWDG1_Msk      (0x1UL << DBGMCU_APB3FZ1_DBG_WWDG1_Pos) /*!< 0x00000040 */\n#define DBGMCU_APB3FZ1_DBG_WWDG1          DBGMCU_APB3FZ1_DBG_WWDG1_Msk\n/********************  Bit definition for APB1LFZ1 register  ************/\n#define DBGMCU_APB1LFZ1_DBG_TIM2_Pos      (0U)\n#define DBGMCU_APB1LFZ1_DBG_TIM2_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM2_Pos) /*!< 0x00000001 */\n#define DBGMCU_APB1LFZ1_DBG_TIM2          DBGMCU_APB1LFZ1_DBG_TIM2_Msk\n#define DBGMCU_APB1LFZ1_DBG_TIM3_Pos      (1U)\n#define DBGMCU_APB1LFZ1_DBG_TIM3_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM3_Pos) /*!< 0x00000002 */\n#define DBGMCU_APB1LFZ1_DBG_TIM3          DBGMCU_APB1LFZ1_DBG_TIM3_Msk\n#define DBGMCU_APB1LFZ1_DBG_TIM4_Pos      (2U)\n#define DBGMCU_APB1LFZ1_DBG_TIM4_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM4_Pos) /*!< 0x00000004 */\n#define DBGMCU_APB1LFZ1_DBG_TIM4          DBGMCU_APB1LFZ1_DBG_TIM4_Msk\n#define DBGMCU_APB1LFZ1_DBG_TIM5_Pos      (3U)\n#define DBGMCU_APB1LFZ1_DBG_TIM5_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM5_Pos) /*!< 0x00000008 */\n#define DBGMCU_APB1LFZ1_DBG_TIM5          DBGMCU_APB1LFZ1_DBG_TIM5_Msk\n#define DBGMCU_APB1LFZ1_DBG_TIM6_Pos      (4U)\n#define DBGMCU_APB1LFZ1_DBG_TIM6_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM6_Pos) /*!< 0x00000010 */\n#define DBGMCU_APB1LFZ1_DBG_TIM6          DBGMCU_APB1LFZ1_DBG_TIM6_Msk\n#define DBGMCU_APB1LFZ1_DBG_TIM7_Pos      (5U)\n#define DBGMCU_APB1LFZ1_DBG_TIM7_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM7_Pos) /*!< 0x00000020 */\n#define DBGMCU_APB1LFZ1_DBG_TIM7          DBGMCU_APB1LFZ1_DBG_TIM7_Msk\n#define DBGMCU_APB1LFZ1_DBG_TIM12_Pos     (6U)\n#define DBGMCU_APB1LFZ1_DBG_TIM12_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM12_Pos) /*!< 0x00000040 */\n#define DBGMCU_APB1LFZ1_DBG_TIM12         DBGMCU_APB1LFZ1_DBG_TIM12_Msk\n#define DBGMCU_APB1LFZ1_DBG_TIM13_Pos     (7U)\n#define DBGMCU_APB1LFZ1_DBG_TIM13_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM13_Pos) /*!< 0x00000080 */\n#define DBGMCU_APB1LFZ1_DBG_TIM13         DBGMCU_APB1LFZ1_DBG_TIM13_Msk\n#define DBGMCU_APB1LFZ1_DBG_TIM14_Pos     (8U)\n#define DBGMCU_APB1LFZ1_DBG_TIM14_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM14_Pos) /*!< 0x00000100 */\n#define DBGMCU_APB1LFZ1_DBG_TIM14         DBGMCU_APB1LFZ1_DBG_TIM14_Msk\n#define DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos    (9U)\n#define DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos) /*!< 0x00000200 */\n#define DBGMCU_APB1LFZ1_DBG_LPTIM1        DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk\n#define DBGMCU_APB1LFZ1_DBG_I2C1_Pos      (21U)\n#define DBGMCU_APB1LFZ1_DBG_I2C1_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C1_Pos) /*!< 0x00200000 */\n#define DBGMCU_APB1LFZ1_DBG_I2C1          DBGMCU_APB1LFZ1_DBG_I2C1_Msk\n#define DBGMCU_APB1LFZ1_DBG_I2C2_Pos      (22U)\n#define DBGMCU_APB1LFZ1_DBG_I2C2_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C2_Pos) /*!< 0x00400000 */\n#define DBGMCU_APB1LFZ1_DBG_I2C2          DBGMCU_APB1LFZ1_DBG_I2C2_Msk\n#define DBGMCU_APB1LFZ1_DBG_I2C3_Pos      (23U)\n#define DBGMCU_APB1LFZ1_DBG_I2C3_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C3_Pos) /*!< 0x00800000 */\n#define DBGMCU_APB1LFZ1_DBG_I2C3          DBGMCU_APB1LFZ1_DBG_I2C3_Msk\n\n/********************  Bit definition for APB1HFZ1 register  ************/\n#define DBGMCU_APB1HFZ1_DBG_FDCAN_Pos     (8U)\n#define DBGMCU_APB1HFZ1_DBG_FDCAN_Msk     (0x1UL << DBGMCU_APB1HFZ1_DBG_FDCAN_Pos) /*!< 0x00000100 */\n#define DBGMCU_APB1HFZ1_DBG_FDCAN         DBGMCU_APB1HFZ1_DBG_FDCAN_Msk\n/********************  Bit definition for APB2FZ1 register  ************/\n#define DBGMCU_APB2FZ1_DBG_TIM1_Pos       (0U)\n#define DBGMCU_APB2FZ1_DBG_TIM1_Msk       (0x1UL << DBGMCU_APB2FZ1_DBG_TIM1_Pos) /*!< 0x00000001 */\n#define DBGMCU_APB2FZ1_DBG_TIM1           DBGMCU_APB2FZ1_DBG_TIM1_Msk\n#define DBGMCU_APB2FZ1_DBG_TIM8_Pos       (1U)\n#define DBGMCU_APB2FZ1_DBG_TIM8_Msk       (0x1UL << DBGMCU_APB2FZ1_DBG_TIM8_Pos) /*!< 0x00000002 */\n#define DBGMCU_APB2FZ1_DBG_TIM8           DBGMCU_APB2FZ1_DBG_TIM8_Msk\n#define DBGMCU_APB2FZ1_DBG_TIM15_Pos      (16U)\n#define DBGMCU_APB2FZ1_DBG_TIM15_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM15_Pos) /*!< 0x00010000 */\n#define DBGMCU_APB2FZ1_DBG_TIM15          DBGMCU_APB2FZ1_DBG_TIM15_Msk\n#define DBGMCU_APB2FZ1_DBG_TIM16_Pos      (17U)\n#define DBGMCU_APB2FZ1_DBG_TIM16_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM16_Pos) /*!< 0x00020000 */\n#define DBGMCU_APB2FZ1_DBG_TIM16          DBGMCU_APB2FZ1_DBG_TIM16_Msk\n#define DBGMCU_APB2FZ1_DBG_TIM17_Pos      (18U)\n#define DBGMCU_APB2FZ1_DBG_TIM17_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM17_Pos) /*!< 0x00040000 */\n#define DBGMCU_APB2FZ1_DBG_TIM17          DBGMCU_APB2FZ1_DBG_TIM17_Msk\n#define DBGMCU_APB2FZ1_DBG_HRTIM_Pos      (29U)\n#define DBGMCU_APB2FZ1_DBG_HRTIM_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_HRTIM_Pos) /*!< 0x20000000 */\n#define DBGMCU_APB2FZ1_DBG_HRTIM          DBGMCU_APB2FZ1_DBG_HRTIM_Msk\n\n/********************  Bit definition for APB4FZ1 register  ************/\n#define DBGMCU_APB4FZ1_DBG_I2C4_Pos       (7U)\n#define DBGMCU_APB4FZ1_DBG_I2C4_Msk       (0x1UL << DBGMCU_APB4FZ1_DBG_I2C4_Pos) /*!< 0x00000080 */\n#define DBGMCU_APB4FZ1_DBG_I2C4           DBGMCU_APB4FZ1_DBG_I2C4_Msk\n#define DBGMCU_APB4FZ1_DBG_LPTIM2_Pos     (9U)\n#define DBGMCU_APB4FZ1_DBG_LPTIM2_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM2_Pos) /*!< 0x00000200 */\n#define DBGMCU_APB4FZ1_DBG_LPTIM2         DBGMCU_APB4FZ1_DBG_LPTIM2_Msk\n#define DBGMCU_APB4FZ1_DBG_LPTIM3_Pos     (10U)\n#define DBGMCU_APB4FZ1_DBG_LPTIM3_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM3_Pos) /*!< 0x00000400 */\n#define DBGMCU_APB4FZ1_DBG_LPTIM3         DBGMCU_APB4FZ1_DBG_LPTIM3_Msk\n#define DBGMCU_APB4FZ1_DBG_LPTIM4_Pos     (11U)\n#define DBGMCU_APB4FZ1_DBG_LPTIM4_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM4_Pos) /*!< 0x00000800 */\n#define DBGMCU_APB4FZ1_DBG_LPTIM4         DBGMCU_APB4FZ1_DBG_LPTIM4_Msk\n#define DBGMCU_APB4FZ1_DBG_LPTIM5_Pos     (12U)\n#define DBGMCU_APB4FZ1_DBG_LPTIM5_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM5_Pos) /*!< 0x00001000 */\n#define DBGMCU_APB4FZ1_DBG_LPTIM5         DBGMCU_APB4FZ1_DBG_LPTIM5_Msk\n#define DBGMCU_APB4FZ1_DBG_RTC_Pos        (16U)\n#define DBGMCU_APB4FZ1_DBG_RTC_Msk        (0x1UL << DBGMCU_APB4FZ1_DBG_RTC_Pos) /*!< 0x00010000 */\n#define DBGMCU_APB4FZ1_DBG_RTC            DBGMCU_APB4FZ1_DBG_RTC_Msk\n#define DBGMCU_APB4FZ1_DBG_IWDG1_Pos      (18U)\n#define DBGMCU_APB4FZ1_DBG_IWDG1_Msk      (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG1_Pos) /*!< 0x00040000 */\n#define DBGMCU_APB4FZ1_DBG_IWDG1          DBGMCU_APB4FZ1_DBG_IWDG1_Msk\n/******************************************************************************/\n/*                                                                            */\n/*                        High Resolution Timer (HRTIM)                       */\n/*                                                                            */\n/******************************************************************************/\n/******************** Master Timer control register ***************************/\n#define HRTIM_MCR_CK_PSC_Pos          (0U)\n#define HRTIM_MCR_CK_PSC_Msk          (0x7UL << HRTIM_MCR_CK_PSC_Pos)          /*!< 0x00000007 */\n#define HRTIM_MCR_CK_PSC              HRTIM_MCR_CK_PSC_Msk                     /*!< Prescaler mask */\n#define HRTIM_MCR_CK_PSC_0            (0x1UL << HRTIM_MCR_CK_PSC_Pos)           /*!< 0x00000001 */\n#define HRTIM_MCR_CK_PSC_1            (0x2UL << HRTIM_MCR_CK_PSC_Pos)           /*!< 0x00000002 */\n#define HRTIM_MCR_CK_PSC_2            (0x4UL << HRTIM_MCR_CK_PSC_Pos)           /*!< 0x00000004 */\n\n#define HRTIM_MCR_CONT_Pos            (3U)\n#define HRTIM_MCR_CONT_Msk            (0x1UL << HRTIM_MCR_CONT_Pos)            /*!< 0x00000008 */\n#define HRTIM_MCR_CONT                HRTIM_MCR_CONT_Msk                       /*!< Continuous mode */\n#define HRTIM_MCR_RETRIG_Pos          (4U)\n#define HRTIM_MCR_RETRIG_Msk          (0x1UL << HRTIM_MCR_RETRIG_Pos)          /*!< 0x00000010 */\n#define HRTIM_MCR_RETRIG              HRTIM_MCR_RETRIG_Msk                     /*!< Rettrigreable mode */\n#define HRTIM_MCR_HALF_Pos            (5U)\n#define HRTIM_MCR_HALF_Msk            (0x1UL << HRTIM_MCR_HALF_Pos)            /*!< 0x00000020 */\n#define HRTIM_MCR_HALF                HRTIM_MCR_HALF_Msk                       /*!< Half mode */\n\n#define HRTIM_MCR_SYNC_IN_Pos         (8U)\n#define HRTIM_MCR_SYNC_IN_Msk         (0x3UL << HRTIM_MCR_SYNC_IN_Pos)         /*!< 0x00000300 */\n#define HRTIM_MCR_SYNC_IN             HRTIM_MCR_SYNC_IN_Msk                    /*!< Synchronization input master */\n#define HRTIM_MCR_SYNC_IN_0           (0x1UL << HRTIM_MCR_SYNC_IN_Pos)          /*!< 0x00000100 */\n#define HRTIM_MCR_SYNC_IN_1           (0x2UL << HRTIM_MCR_SYNC_IN_Pos)          /*!< 0x00000200 */\n#define HRTIM_MCR_SYNCRSTM_Pos        (10U)\n#define HRTIM_MCR_SYNCRSTM_Msk        (0x1UL << HRTIM_MCR_SYNCRSTM_Pos)        /*!< 0x00000400 */\n#define HRTIM_MCR_SYNCRSTM            HRTIM_MCR_SYNCRSTM_Msk                   /*!< Synchronization reset master */\n#define HRTIM_MCR_SYNCSTRTM_Pos       (11U)\n#define HRTIM_MCR_SYNCSTRTM_Msk       (0x1UL << HRTIM_MCR_SYNCSTRTM_Pos)       /*!< 0x00000800 */\n#define HRTIM_MCR_SYNCSTRTM           HRTIM_MCR_SYNCSTRTM_Msk                  /*!< Synchronization start master */\n#define HRTIM_MCR_SYNC_OUT_Pos        (12U)\n#define HRTIM_MCR_SYNC_OUT_Msk        (0x3UL << HRTIM_MCR_SYNC_OUT_Pos)        /*!< 0x00003000 */\n#define HRTIM_MCR_SYNC_OUT            HRTIM_MCR_SYNC_OUT_Msk                   /*!< Synchronization output master */\n#define HRTIM_MCR_SYNC_OUT_0          (0x1UL << HRTIM_MCR_SYNC_OUT_Pos)         /*!< 0x00001000 */\n#define HRTIM_MCR_SYNC_OUT_1          (0x2UL << HRTIM_MCR_SYNC_OUT_Pos)         /*!< 0x00002000 */\n#define HRTIM_MCR_SYNC_SRC_Pos        (14U)\n#define HRTIM_MCR_SYNC_SRC_Msk        (0x3UL << HRTIM_MCR_SYNC_SRC_Pos)        /*!< 0x0000C000 */\n#define HRTIM_MCR_SYNC_SRC            HRTIM_MCR_SYNC_SRC_Msk                   /*!< Synchronization source */\n#define HRTIM_MCR_SYNC_SRC_0          (0x1UL << HRTIM_MCR_SYNC_SRC_Pos)         /*!< 0x00004000 */\n#define HRTIM_MCR_SYNC_SRC_1          (0x2UL << HRTIM_MCR_SYNC_SRC_Pos)         /*!< 0x00008000 */\n\n#define HRTIM_MCR_MCEN_Pos            (16U)\n#define HRTIM_MCR_MCEN_Msk            (0x1UL << HRTIM_MCR_MCEN_Pos)            /*!< 0x00010000 */\n#define HRTIM_MCR_MCEN                HRTIM_MCR_MCEN_Msk                       /*!< Master counter enable */\n#define HRTIM_MCR_TACEN_Pos           (17U)\n#define HRTIM_MCR_TACEN_Msk           (0x1UL << HRTIM_MCR_TACEN_Pos)           /*!< 0x00020000 */\n#define HRTIM_MCR_TACEN               HRTIM_MCR_TACEN_Msk                      /*!< Timer A counter enable */\n#define HRTIM_MCR_TBCEN_Pos           (18U)\n#define HRTIM_MCR_TBCEN_Msk           (0x1UL << HRTIM_MCR_TBCEN_Pos)           /*!< 0x00040000 */\n#define HRTIM_MCR_TBCEN               HRTIM_MCR_TBCEN_Msk                      /*!< Timer B counter enable */\n#define HRTIM_MCR_TCCEN_Pos           (19U)\n#define HRTIM_MCR_TCCEN_Msk           (0x1UL << HRTIM_MCR_TCCEN_Pos)           /*!< 0x00080000 */\n#define HRTIM_MCR_TCCEN               HRTIM_MCR_TCCEN_Msk                      /*!< Timer C counter enable */\n#define HRTIM_MCR_TDCEN_Pos           (20U)\n#define HRTIM_MCR_TDCEN_Msk           (0x1UL << HRTIM_MCR_TDCEN_Pos)           /*!< 0x00100000 */\n#define HRTIM_MCR_TDCEN               HRTIM_MCR_TDCEN_Msk                      /*!< Timer D counter enable */\n#define HRTIM_MCR_TECEN_Pos           (21U)\n#define HRTIM_MCR_TECEN_Msk           (0x1UL << HRTIM_MCR_TECEN_Pos)           /*!< 0x00200000 */\n#define HRTIM_MCR_TECEN               HRTIM_MCR_TECEN_Msk                      /*!< Timer E counter enable */\n\n#define HRTIM_MCR_DACSYNC_Pos         (25U)\n#define HRTIM_MCR_DACSYNC_Msk         (0x3UL << HRTIM_MCR_DACSYNC_Pos)         /*!< 0x06000000 */\n#define HRTIM_MCR_DACSYNC             HRTIM_MCR_DACSYNC_Msk                    /*!< DAC sychronization mask */\n#define HRTIM_MCR_DACSYNC_0           (0x1UL << HRTIM_MCR_DACSYNC_Pos)          /*!< 0x02000000 */\n#define HRTIM_MCR_DACSYNC_1           (0x2UL << HRTIM_MCR_DACSYNC_Pos)          /*!< 0x04000000 */\n\n#define HRTIM_MCR_PREEN_Pos           (27U)\n#define HRTIM_MCR_PREEN_Msk           (0x1UL << HRTIM_MCR_PREEN_Pos)           /*!< 0x08000000 */\n#define HRTIM_MCR_PREEN               HRTIM_MCR_PREEN_Msk                      /*!< Master preload enable */\n#define HRTIM_MCR_MREPU_Pos           (29U)\n#define HRTIM_MCR_MREPU_Msk           (0x1UL << HRTIM_MCR_MREPU_Pos)           /*!< 0x20000000 */\n#define HRTIM_MCR_MREPU               HRTIM_MCR_MREPU_Msk                      /*!< Master repetition update */\n\n#define HRTIM_MCR_BRSTDMA_Pos         (30U)\n#define HRTIM_MCR_BRSTDMA_Msk         (0x3UL << HRTIM_MCR_BRSTDMA_Pos)         /*!< 0xC0000000 */\n#define HRTIM_MCR_BRSTDMA             HRTIM_MCR_BRSTDMA_Msk                    /*!< Burst DMA update */\n#define HRTIM_MCR_BRSTDMA_0           (0x1UL << HRTIM_MCR_BRSTDMA_Pos)          /*!< 0x40000000 */\n#define HRTIM_MCR_BRSTDMA_1           (0x2UL << HRTIM_MCR_BRSTDMA_Pos)          /*!< 0x80000000 */\n\n/******************** Master Timer Interrupt status register ******************/\n#define HRTIM_MISR_MCMP1_Pos          (0U)\n#define HRTIM_MISR_MCMP1_Msk          (0x1UL << HRTIM_MISR_MCMP1_Pos)          /*!< 0x00000001 */\n#define HRTIM_MISR_MCMP1              HRTIM_MISR_MCMP1_Msk                     /*!< Master compare 1 interrupt flag */\n#define HRTIM_MISR_MCMP2_Pos          (1U)\n#define HRTIM_MISR_MCMP2_Msk          (0x1UL << HRTIM_MISR_MCMP2_Pos)          /*!< 0x00000002 */\n#define HRTIM_MISR_MCMP2              HRTIM_MISR_MCMP2_Msk                     /*!< Master compare 2 interrupt flag */\n#define HRTIM_MISR_MCMP3_Pos          (2U)\n#define HRTIM_MISR_MCMP3_Msk          (0x1UL << HRTIM_MISR_MCMP3_Pos)          /*!< 0x00000004 */\n#define HRTIM_MISR_MCMP3              HRTIM_MISR_MCMP3_Msk                     /*!< Master compare 3 interrupt flag */\n#define HRTIM_MISR_MCMP4_Pos          (3U)\n#define HRTIM_MISR_MCMP4_Msk          (0x1UL << HRTIM_MISR_MCMP4_Pos)          /*!< 0x00000008 */\n#define HRTIM_MISR_MCMP4              HRTIM_MISR_MCMP4_Msk                     /*!< Master compare 4 interrupt flag */\n#define HRTIM_MISR_MREP_Pos           (4U)\n#define HRTIM_MISR_MREP_Msk           (0x1UL << HRTIM_MISR_MREP_Pos)           /*!< 0x00000010 */\n#define HRTIM_MISR_MREP               HRTIM_MISR_MREP_Msk                      /*!< Master Repetition interrupt flag */\n#define HRTIM_MISR_SYNC_Pos           (5U)\n#define HRTIM_MISR_SYNC_Msk           (0x1UL << HRTIM_MISR_SYNC_Pos)           /*!< 0x00000020 */\n#define HRTIM_MISR_SYNC               HRTIM_MISR_SYNC_Msk                      /*!< Synchronization input interrupt flag */\n#define HRTIM_MISR_MUPD_Pos           (6U)\n#define HRTIM_MISR_MUPD_Msk           (0x1UL << HRTIM_MISR_MUPD_Pos)           /*!< 0x00000040 */\n#define HRTIM_MISR_MUPD               HRTIM_MISR_MUPD_Msk                      /*!< Master update interrupt flag */\n\n/******************** Master Timer Interrupt clear register *******************/\n#define HRTIM_MICR_MCMP1_Pos          (0U)\n#define HRTIM_MICR_MCMP1_Msk          (0x1UL << HRTIM_MICR_MCMP1_Pos)          /*!< 0x00000001 */\n#define HRTIM_MICR_MCMP1              HRTIM_MICR_MCMP1_Msk                     /*!< Master compare 1 interrupt flag clear */\n#define HRTIM_MICR_MCMP2_Pos          (1U)\n#define HRTIM_MICR_MCMP2_Msk          (0x1UL << HRTIM_MICR_MCMP2_Pos)          /*!< 0x00000002 */\n#define HRTIM_MICR_MCMP2              HRTIM_MICR_MCMP2_Msk                     /*!< Master compare 2 interrupt flag clear */\n#define HRTIM_MICR_MCMP3_Pos          (2U)\n#define HRTIM_MICR_MCMP3_Msk          (0x1UL << HRTIM_MICR_MCMP3_Pos)          /*!< 0x00000004 */\n#define HRTIM_MICR_MCMP3              HRTIM_MICR_MCMP3_Msk                     /*!< Master compare 3 interrupt flag clear */\n#define HRTIM_MICR_MCMP4_Pos          (3U)\n#define HRTIM_MICR_MCMP4_Msk          (0x1UL << HRTIM_MICR_MCMP4_Pos)          /*!< 0x00000008 */\n#define HRTIM_MICR_MCMP4              HRTIM_MICR_MCMP4_Msk                     /*!< Master compare 4 interrupt flag clear */\n#define HRTIM_MICR_MREP_Pos           (4U)\n#define HRTIM_MICR_MREP_Msk           (0x1UL << HRTIM_MICR_MREP_Pos)           /*!< 0x00000010 */\n#define HRTIM_MICR_MREP               HRTIM_MICR_MREP_Msk                      /*!< Master Repetition interrupt flag clear */\n#define HRTIM_MICR_SYNC_Pos           (5U)\n#define HRTIM_MICR_SYNC_Msk           (0x1UL << HRTIM_MICR_SYNC_Pos)           /*!< 0x00000020 */\n#define HRTIM_MICR_SYNC               HRTIM_MICR_SYNC_Msk                      /*!< Synchronization input interrupt flag clear */\n#define HRTIM_MICR_MUPD_Pos           (6U)\n#define HRTIM_MICR_MUPD_Msk           (0x1UL << HRTIM_MICR_MUPD_Pos)           /*!< 0x00000040 */\n#define HRTIM_MICR_MUPD               HRTIM_MICR_MUPD_Msk                      /*!< Master update interrupt flag clear */\n\n/******************** Master Timer DMA/Interrupt enable register **************/\n#define HRTIM_MDIER_MCMP1IE_Pos       (0U)\n#define HRTIM_MDIER_MCMP1IE_Msk       (0x1UL << HRTIM_MDIER_MCMP1IE_Pos)       /*!< 0x00000001 */\n#define HRTIM_MDIER_MCMP1IE           HRTIM_MDIER_MCMP1IE_Msk                  /*!< Master compare 1 interrupt enable */\n#define HRTIM_MDIER_MCMP2IE_Pos       (1U)\n#define HRTIM_MDIER_MCMP2IE_Msk       (0x1UL << HRTIM_MDIER_MCMP2IE_Pos)       /*!< 0x00000002 */\n#define HRTIM_MDIER_MCMP2IE           HRTIM_MDIER_MCMP2IE_Msk                  /*!< Master compare 2 interrupt enable */\n#define HRTIM_MDIER_MCMP3IE_Pos       (2U)\n#define HRTIM_MDIER_MCMP3IE_Msk       (0x1UL << HRTIM_MDIER_MCMP3IE_Pos)       /*!< 0x00000004 */\n#define HRTIM_MDIER_MCMP3IE           HRTIM_MDIER_MCMP3IE_Msk                  /*!< Master compare 3 interrupt enable */\n#define HRTIM_MDIER_MCMP4IE_Pos       (3U)\n#define HRTIM_MDIER_MCMP4IE_Msk       (0x1UL << HRTIM_MDIER_MCMP4IE_Pos)       /*!< 0x00000008 */\n#define HRTIM_MDIER_MCMP4IE           HRTIM_MDIER_MCMP4IE_Msk                  /*!< Master compare 4 interrupt enable */\n#define HRTIM_MDIER_MREPIE_Pos        (4U)\n#define HRTIM_MDIER_MREPIE_Msk        (0x1UL << HRTIM_MDIER_MREPIE_Pos)        /*!< 0x00000010 */\n#define HRTIM_MDIER_MREPIE            HRTIM_MDIER_MREPIE_Msk                   /*!< Master Repetition interrupt enable */\n#define HRTIM_MDIER_SYNCIE_Pos        (5U)\n#define HRTIM_MDIER_SYNCIE_Msk        (0x1UL << HRTIM_MDIER_SYNCIE_Pos)        /*!< 0x00000020 */\n#define HRTIM_MDIER_SYNCIE            HRTIM_MDIER_SYNCIE_Msk                   /*!< Synchronization input interrupt enable */\n#define HRTIM_MDIER_MUPDIE_Pos        (6U)\n#define HRTIM_MDIER_MUPDIE_Msk        (0x1UL << HRTIM_MDIER_MUPDIE_Pos)        /*!< 0x00000040 */\n#define HRTIM_MDIER_MUPDIE            HRTIM_MDIER_MUPDIE_Msk                   /*!< Master update interrupt enable */\n\n#define HRTIM_MDIER_MCMP1DE_Pos       (16U)\n#define HRTIM_MDIER_MCMP1DE_Msk       (0x1UL << HRTIM_MDIER_MCMP1DE_Pos)       /*!< 0x00010000 */\n#define HRTIM_MDIER_MCMP1DE           HRTIM_MDIER_MCMP1DE_Msk                  /*!< Master compare 1 DMA enable */\n#define HRTIM_MDIER_MCMP2DE_Pos       (17U)\n#define HRTIM_MDIER_MCMP2DE_Msk       (0x1UL << HRTIM_MDIER_MCMP2DE_Pos)       /*!< 0x00020000 */\n#define HRTIM_MDIER_MCMP2DE           HRTIM_MDIER_MCMP2DE_Msk                  /*!< Master compare 2 DMA enable */\n#define HRTIM_MDIER_MCMP3DE_Pos       (18U)\n#define HRTIM_MDIER_MCMP3DE_Msk       (0x1UL << HRTIM_MDIER_MCMP3DE_Pos)       /*!< 0x00040000 */\n#define HRTIM_MDIER_MCMP3DE           HRTIM_MDIER_MCMP3DE_Msk                  /*!< Master compare 3 DMA enable */\n#define HRTIM_MDIER_MCMP4DE_Pos       (19U)\n#define HRTIM_MDIER_MCMP4DE_Msk       (0x1UL << HRTIM_MDIER_MCMP4DE_Pos)       /*!< 0x00080000 */\n#define HRTIM_MDIER_MCMP4DE           HRTIM_MDIER_MCMP4DE_Msk                  /*!< Master compare 4 DMA enable */\n#define HRTIM_MDIER_MREPDE_Pos        (20U)\n#define HRTIM_MDIER_MREPDE_Msk        (0x1UL << HRTIM_MDIER_MREPDE_Pos)        /*!< 0x00100000 */\n#define HRTIM_MDIER_MREPDE            HRTIM_MDIER_MREPDE_Msk                   /*!< Master Repetition DMA enable */\n#define HRTIM_MDIER_SYNCDE_Pos        (21U)\n#define HRTIM_MDIER_SYNCDE_Msk        (0x1UL << HRTIM_MDIER_SYNCDE_Pos)        /*!< 0x00200000 */\n#define HRTIM_MDIER_SYNCDE            HRTIM_MDIER_SYNCDE_Msk                   /*!< Synchronization input DMA enable */\n#define HRTIM_MDIER_MUPDDE_Pos        (22U)\n#define HRTIM_MDIER_MUPDDE_Msk        (0x1UL << HRTIM_MDIER_MUPDDE_Pos)        /*!< 0x00400000 */\n#define HRTIM_MDIER_MUPDDE            HRTIM_MDIER_MUPDDE_Msk                   /*!< Master update DMA enable */\n\n/*******************  Bit definition for HRTIM_MCNTR register  ****************/\n#define HRTIM_MCNTR_MCNTR_Pos         (0U)\n#define HRTIM_MCNTR_MCNTR_Msk         (0xFFFFUL << HRTIM_MCNTR_MCNTR_Pos)      /*!< 0x0000FFFF */\n#define HRTIM_MCNTR_MCNTR             HRTIM_MCNTR_MCNTR_Msk                    /*!<Counter Value */\n\n/*******************  Bit definition for HRTIM_MPER register  *****************/\n#define HRTIM_MPER_MPER_Pos           (0U)\n#define HRTIM_MPER_MPER_Msk           (0xFFFFUL << HRTIM_MPER_MPER_Pos)        /*!< 0x0000FFFF */\n#define HRTIM_MPER_MPER               HRTIM_MPER_MPER_Msk                      /*!< Period Value */\n\n/*******************  Bit definition for HRTIM_MREP register  *****************/\n#define HRTIM_MREP_MREP_Pos           (0U)\n#define HRTIM_MREP_MREP_Msk           (0xFFUL << HRTIM_MREP_MREP_Pos)          /*!< 0x000000FF */\n#define HRTIM_MREP_MREP               HRTIM_MREP_MREP_Msk                      /*!<Repetition Value */\n\n/*******************  Bit definition for HRTIM_MCMP1R register  *****************/\n#define HRTIM_MCMP1R_MCMP1R_Pos       (0U)\n#define HRTIM_MCMP1R_MCMP1R_Msk       (0xFFFFUL << HRTIM_MCMP1R_MCMP1R_Pos)    /*!< 0x0000FFFF */\n#define HRTIM_MCMP1R_MCMP1R           HRTIM_MCMP1R_MCMP1R_Msk                  /*!<Compare Value */\n\n/*******************  Bit definition for HRTIM_MCMP2R register  *****************/\n#define HRTIM_MCMP1R_MCMP2R_Pos       (0U)\n#define HRTIM_MCMP1R_MCMP2R_Msk       (0xFFFFUL << HRTIM_MCMP1R_MCMP2R_Pos)    /*!< 0x0000FFFF */\n#define HRTIM_MCMP1R_MCMP2R           HRTIM_MCMP1R_MCMP2R_Msk                  /*!<Compare Value */\n\n/*******************  Bit definition for HRTIM_MCMP3R register  *****************/\n#define HRTIM_MCMP1R_MCMP3R_Pos       (0U)\n#define HRTIM_MCMP1R_MCMP3R_Msk       (0xFFFFUL << HRTIM_MCMP1R_MCMP3R_Pos)    /*!< 0x0000FFFF */\n#define HRTIM_MCMP1R_MCMP3R           HRTIM_MCMP1R_MCMP3R_Msk                  /*!<Compare Value */\n\n/*******************  Bit definition for HRTIM_MCMP4R register  *****************/\n#define HRTIM_MCMP1R_MCMP4R_Pos       (0U)\n#define HRTIM_MCMP1R_MCMP4R_Msk       (0xFFFFUL << HRTIM_MCMP1R_MCMP4R_Pos)    /*!< 0x0000FFFF */\n#define HRTIM_MCMP1R_MCMP4R           HRTIM_MCMP1R_MCMP4R_Msk                  /*!<Compare Value */\n\n/******************** Slave control register **********************************/\n#define HRTIM_TIMCR_CK_PSC_Pos        (0U)\n#define HRTIM_TIMCR_CK_PSC_Msk        (0x7UL << HRTIM_TIMCR_CK_PSC_Pos)        /*!< 0x00000007 */\n#define HRTIM_TIMCR_CK_PSC            HRTIM_TIMCR_CK_PSC_Msk                   /*!< Slave prescaler mask*/\n#define HRTIM_TIMCR_CK_PSC_0          (0x1UL << HRTIM_TIMCR_CK_PSC_Pos)         /*!< 0x00000001 */\n#define HRTIM_TIMCR_CK_PSC_1          (0x2UL << HRTIM_TIMCR_CK_PSC_Pos)         /*!< 0x00000002 */\n#define HRTIM_TIMCR_CK_PSC_2          (0x4UL << HRTIM_TIMCR_CK_PSC_Pos)         /*!< 0x00000004 */\n\n#define HRTIM_TIMCR_CONT_Pos          (3U)\n#define HRTIM_TIMCR_CONT_Msk          (0x1UL << HRTIM_TIMCR_CONT_Pos)          /*!< 0x00000008 */\n#define HRTIM_TIMCR_CONT              HRTIM_TIMCR_CONT_Msk                     /*!< Slave continuous mode */\n#define HRTIM_TIMCR_RETRIG_Pos        (4U)\n#define HRTIM_TIMCR_RETRIG_Msk        (0x1UL << HRTIM_TIMCR_RETRIG_Pos)        /*!< 0x00000010 */\n#define HRTIM_TIMCR_RETRIG            HRTIM_TIMCR_RETRIG_Msk                   /*!< Slave Retrigreable mode */\n#define HRTIM_TIMCR_HALF_Pos          (5U)\n#define HRTIM_TIMCR_HALF_Msk          (0x1UL << HRTIM_TIMCR_HALF_Pos)          /*!< 0x00000020 */\n#define HRTIM_TIMCR_HALF              HRTIM_TIMCR_HALF_Msk                     /*!< Slave Half mode */\n#define HRTIM_TIMCR_PSHPLL_Pos        (6U)\n#define HRTIM_TIMCR_PSHPLL_Msk        (0x1UL << HRTIM_TIMCR_PSHPLL_Pos)        /*!< 0x00000040 */\n#define HRTIM_TIMCR_PSHPLL            HRTIM_TIMCR_PSHPLL_Msk                   /*!< Slave push-pull mode */\n\n#define HRTIM_TIMCR_SYNCRST_Pos       (10U)\n#define HRTIM_TIMCR_SYNCRST_Msk       (0x1UL << HRTIM_TIMCR_SYNCRST_Pos)       /*!< 0x00000400 */\n#define HRTIM_TIMCR_SYNCRST           HRTIM_TIMCR_SYNCRST_Msk                  /*!< Slave synchronization resets */\n#define HRTIM_TIMCR_SYNCSTRT_Pos      (11U)\n#define HRTIM_TIMCR_SYNCSTRT_Msk      (0x1UL << HRTIM_TIMCR_SYNCSTRT_Pos)      /*!< 0x00000800 */\n#define HRTIM_TIMCR_SYNCSTRT          HRTIM_TIMCR_SYNCSTRT_Msk                 /*!< Slave synchronization starts */\n\n#define HRTIM_TIMCR_DELCMP2_Pos       (12U)\n#define HRTIM_TIMCR_DELCMP2_Msk       (0x3UL << HRTIM_TIMCR_DELCMP2_Pos)       /*!< 0x00003000 */\n#define HRTIM_TIMCR_DELCMP2           HRTIM_TIMCR_DELCMP2_Msk                  /*!< Slave delayed compartor 2 mode mask */\n#define HRTIM_TIMCR_DELCMP2_0         (0x1UL << HRTIM_TIMCR_DELCMP2_Pos)        /*!< 0x00001000 */\n#define HRTIM_TIMCR_DELCMP2_1         (0x2UL << HRTIM_TIMCR_DELCMP2_Pos)        /*!< 0x00002000 */\n#define HRTIM_TIMCR_DELCMP4_Pos       (14U)\n#define HRTIM_TIMCR_DELCMP4_Msk       (0x3UL << HRTIM_TIMCR_DELCMP4_Pos)       /*!< 0x0000C000 */\n#define HRTIM_TIMCR_DELCMP4           HRTIM_TIMCR_DELCMP4_Msk                  /*!< Slave delayed compartor 4 mode mask */\n#define HRTIM_TIMCR_DELCMP4_0         (0x1UL << HRTIM_TIMCR_DELCMP4_Pos)        /*!< 0x00004000 */\n#define HRTIM_TIMCR_DELCMP4_1         (0x2UL << HRTIM_TIMCR_DELCMP4_Pos)        /*!< 0x00008000 */\n\n#define HRTIM_TIMCR_TREPU_Pos         (17U)\n#define HRTIM_TIMCR_TREPU_Msk         (0x1UL << HRTIM_TIMCR_TREPU_Pos)         /*!< 0x00020000 */\n#define HRTIM_TIMCR_TREPU             HRTIM_TIMCR_TREPU_Msk                    /*!< Slave repetition update */\n#define HRTIM_TIMCR_TRSTU_Pos         (18U)\n#define HRTIM_TIMCR_TRSTU_Msk         (0x1UL << HRTIM_TIMCR_TRSTU_Pos)         /*!< 0x00040000 */\n#define HRTIM_TIMCR_TRSTU             HRTIM_TIMCR_TRSTU_Msk                    /*!< Slave reset update */\n#define HRTIM_TIMCR_TAU_Pos           (19U)\n#define HRTIM_TIMCR_TAU_Msk           (0x1UL << HRTIM_TIMCR_TAU_Pos)           /*!< 0x00080000 */\n#define HRTIM_TIMCR_TAU               HRTIM_TIMCR_TAU_Msk                      /*!< Slave Timer A update reserved for TIM A */\n#define HRTIM_TIMCR_TBU_Pos           (20U)\n#define HRTIM_TIMCR_TBU_Msk           (0x1UL << HRTIM_TIMCR_TBU_Pos)           /*!< 0x00100000 */\n#define HRTIM_TIMCR_TBU               HRTIM_TIMCR_TBU_Msk                      /*!< Slave Timer B update reserved for TIM B */\n#define HRTIM_TIMCR_TCU_Pos           (21U)\n#define HRTIM_TIMCR_TCU_Msk           (0x1UL << HRTIM_TIMCR_TCU_Pos)           /*!< 0x00200000 */\n#define HRTIM_TIMCR_TCU               HRTIM_TIMCR_TCU_Msk                      /*!< Slave Timer C update reserved for TIM C */\n#define HRTIM_TIMCR_TDU_Pos           (22U)\n#define HRTIM_TIMCR_TDU_Msk           (0x1UL << HRTIM_TIMCR_TDU_Pos)           /*!< 0x00400000 */\n#define HRTIM_TIMCR_TDU               HRTIM_TIMCR_TDU_Msk                      /*!< Slave Timer D update reserved for TIM D */\n#define HRTIM_TIMCR_TEU_Pos           (23U)\n#define HRTIM_TIMCR_TEU_Msk           (0x1UL << HRTIM_TIMCR_TEU_Pos)           /*!< 0x00800000 */\n#define HRTIM_TIMCR_TEU               HRTIM_TIMCR_TEU_Msk                      /*!< Slave Timer E update reserved for TIM E */\n#define HRTIM_TIMCR_MSTU_Pos          (24U)\n#define HRTIM_TIMCR_MSTU_Msk          (0x1UL << HRTIM_TIMCR_MSTU_Pos)          /*!< 0x01000000 */\n#define HRTIM_TIMCR_MSTU              HRTIM_TIMCR_MSTU_Msk                     /*!< Master Update */\n\n#define HRTIM_TIMCR_DACSYNC_Pos       (25U)\n#define HRTIM_TIMCR_DACSYNC_Msk       (0x3UL << HRTIM_TIMCR_DACSYNC_Pos)       /*!< 0x06000000 */\n#define HRTIM_TIMCR_DACSYNC           HRTIM_TIMCR_DACSYNC_Msk                  /*!< DAC sychronization mask */\n#define HRTIM_TIMCR_DACSYNC_0         (0x1UL << HRTIM_TIMCR_DACSYNC_Pos)        /*!< 0x02000000 */\n#define HRTIM_TIMCR_DACSYNC_1         (0x2UL << HRTIM_TIMCR_DACSYNC_Pos)        /*!< 0x04000000 */\n#define HRTIM_TIMCR_PREEN_Pos         (27U)\n#define HRTIM_TIMCR_PREEN_Msk         (0x1UL << HRTIM_TIMCR_PREEN_Pos)         /*!< 0x08000000 */\n#define HRTIM_TIMCR_PREEN             HRTIM_TIMCR_PREEN_Msk                    /*!< Slave preload enable */\n\n#define HRTIM_TIMCR_UPDGAT_Pos        (28U)\n#define HRTIM_TIMCR_UPDGAT_Msk        (0xFUL << HRTIM_TIMCR_UPDGAT_Pos)        /*!< 0xF0000000 */\n#define HRTIM_TIMCR_UPDGAT            HRTIM_TIMCR_UPDGAT_Msk                   /*!< Slave update gating mask */\n#define HRTIM_TIMCR_UPDGAT_0          (0x1UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x10000000 */\n#define HRTIM_TIMCR_UPDGAT_1          (0x2UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x20000000 */\n#define HRTIM_TIMCR_UPDGAT_2          (0x4UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x40000000 */\n#define HRTIM_TIMCR_UPDGAT_3          (0x8UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x80000000 */\n\n/******************** Slave Interrupt status register **************************/\n#define HRTIM_TIMISR_CMP1_Pos         (0U)\n#define HRTIM_TIMISR_CMP1_Msk         (0x1UL << HRTIM_TIMISR_CMP1_Pos)         /*!< 0x00000001 */\n#define HRTIM_TIMISR_CMP1             HRTIM_TIMISR_CMP1_Msk                    /*!< Slave compare 1 interrupt flag */\n#define HRTIM_TIMISR_CMP2_Pos         (1U)\n#define HRTIM_TIMISR_CMP2_Msk         (0x1UL << HRTIM_TIMISR_CMP2_Pos)         /*!< 0x00000002 */\n#define HRTIM_TIMISR_CMP2             HRTIM_TIMISR_CMP2_Msk                    /*!< Slave compare 2 interrupt flag */\n#define HRTIM_TIMISR_CMP3_Pos         (2U)\n#define HRTIM_TIMISR_CMP3_Msk         (0x1UL << HRTIM_TIMISR_CMP3_Pos)         /*!< 0x00000004 */\n#define HRTIM_TIMISR_CMP3             HRTIM_TIMISR_CMP3_Msk                    /*!< Slave compare 3 interrupt flag */\n#define HRTIM_TIMISR_CMP4_Pos         (3U)\n#define HRTIM_TIMISR_CMP4_Msk         (0x1UL << HRTIM_TIMISR_CMP4_Pos)         /*!< 0x00000008 */\n#define HRTIM_TIMISR_CMP4             HRTIM_TIMISR_CMP4_Msk                    /*!< Slave compare 4 interrupt flag */\n#define HRTIM_TIMISR_REP_Pos          (4U)\n#define HRTIM_TIMISR_REP_Msk          (0x1UL << HRTIM_TIMISR_REP_Pos)          /*!< 0x00000010 */\n#define HRTIM_TIMISR_REP              HRTIM_TIMISR_REP_Msk                     /*!< Slave repetition interrupt flag */\n#define HRTIM_TIMISR_UPD_Pos          (6U)\n#define HRTIM_TIMISR_UPD_Msk          (0x1UL << HRTIM_TIMISR_UPD_Pos)          /*!< 0x00000040 */\n#define HRTIM_TIMISR_UPD              HRTIM_TIMISR_UPD_Msk                     /*!< Slave update interrupt flag */\n#define HRTIM_TIMISR_CPT1_Pos         (7U)\n#define HRTIM_TIMISR_CPT1_Msk         (0x1UL << HRTIM_TIMISR_CPT1_Pos)         /*!< 0x00000080 */\n#define HRTIM_TIMISR_CPT1             HRTIM_TIMISR_CPT1_Msk                    /*!< Slave capture 1 interrupt flag */\n#define HRTIM_TIMISR_CPT2_Pos         (8U)\n#define HRTIM_TIMISR_CPT2_Msk         (0x1UL << HRTIM_TIMISR_CPT2_Pos)         /*!< 0x00000100 */\n#define HRTIM_TIMISR_CPT2             HRTIM_TIMISR_CPT2_Msk                    /*!< Slave capture 2 interrupt flag */\n#define HRTIM_TIMISR_SET1_Pos         (9U)\n#define HRTIM_TIMISR_SET1_Msk         (0x1UL << HRTIM_TIMISR_SET1_Pos)         /*!< 0x00000200 */\n#define HRTIM_TIMISR_SET1             HRTIM_TIMISR_SET1_Msk                    /*!< Slave output 1 set interrupt flag */\n#define HRTIM_TIMISR_RST1_Pos         (10U)\n#define HRTIM_TIMISR_RST1_Msk         (0x1UL << HRTIM_TIMISR_RST1_Pos)         /*!< 0x00000400 */\n#define HRTIM_TIMISR_RST1             HRTIM_TIMISR_RST1_Msk                    /*!< Slave output 1 reset interrupt flag */\n#define HRTIM_TIMISR_SET2_Pos         (11U)\n#define HRTIM_TIMISR_SET2_Msk         (0x1UL << HRTIM_TIMISR_SET2_Pos)         /*!< 0x00000800 */\n#define HRTIM_TIMISR_SET2             HRTIM_TIMISR_SET2_Msk                    /*!< Slave output 2 set interrupt flag */\n#define HRTIM_TIMISR_RST2_Pos         (12U)\n#define HRTIM_TIMISR_RST2_Msk         (0x1UL << HRTIM_TIMISR_RST2_Pos)         /*!< 0x00001000 */\n#define HRTIM_TIMISR_RST2             HRTIM_TIMISR_RST2_Msk                    /*!< Slave output 2 reset interrupt flag */\n#define HRTIM_TIMISR_RST_Pos          (13U)\n#define HRTIM_TIMISR_RST_Msk          (0x1UL << HRTIM_TIMISR_RST_Pos)          /*!< 0x00002000 */\n#define HRTIM_TIMISR_RST              HRTIM_TIMISR_RST_Msk                     /*!< Slave reset interrupt flag */\n#define HRTIM_TIMISR_DLYPRT_Pos       (14U)\n#define HRTIM_TIMISR_DLYPRT_Msk       (0x1UL << HRTIM_TIMISR_DLYPRT_Pos)       /*!< 0x00004000 */\n#define HRTIM_TIMISR_DLYPRT           HRTIM_TIMISR_DLYPRT_Msk                  /*!< Slave output 1 delay protection interrupt flag */\n#define HRTIM_TIMISR_CPPSTAT_Pos      (16U)\n#define HRTIM_TIMISR_CPPSTAT_Msk      (0x1UL << HRTIM_TIMISR_CPPSTAT_Pos)      /*!< 0x00010000 */\n#define HRTIM_TIMISR_CPPSTAT          HRTIM_TIMISR_CPPSTAT_Msk                 /*!< Slave current push-pull flag */\n#define HRTIM_TIMISR_IPPSTAT_Pos      (17U)\n#define HRTIM_TIMISR_IPPSTAT_Msk      (0x1UL << HRTIM_TIMISR_IPPSTAT_Pos)      /*!< 0x00020000 */\n#define HRTIM_TIMISR_IPPSTAT          HRTIM_TIMISR_IPPSTAT_Msk                 /*!< Slave idle push-pull flag */\n#define HRTIM_TIMISR_O1STAT_Pos       (18U)\n#define HRTIM_TIMISR_O1STAT_Msk       (0x1UL << HRTIM_TIMISR_O1STAT_Pos)       /*!< 0x00040000 */\n#define HRTIM_TIMISR_O1STAT           HRTIM_TIMISR_O1STAT_Msk                  /*!< Slave output 1 state flag */\n#define HRTIM_TIMISR_O2STAT_Pos       (19U)\n#define HRTIM_TIMISR_O2STAT_Msk       (0x1UL << HRTIM_TIMISR_O2STAT_Pos)       /*!< 0x00080000 */\n#define HRTIM_TIMISR_O2STAT           HRTIM_TIMISR_O2STAT_Msk                  /*!< Slave output 2 state flag */\n#define HRTIM_TIMISR_O1CPY_Pos        (20U)\n#define HRTIM_TIMISR_O1CPY_Msk        (0x1UL << HRTIM_TIMISR_O1CPY_Pos)        /*!< 0x00100000 */\n#define HRTIM_TIMISR_O1CPY            HRTIM_TIMISR_O1CPY_Msk                   /*!< Slave output 1 copy flag */\n#define HRTIM_TIMISR_O2CPY_Pos        (21U)\n#define HRTIM_TIMISR_O2CPY_Msk        (0x1UL << HRTIM_TIMISR_O2CPY_Pos)        /*!< 0x00200000 */\n#define HRTIM_TIMISR_O2CPY            HRTIM_TIMISR_O2CPY_Msk                   /*!< Slave output 2 copy flag */\n\n/******************** Slave Interrupt clear register **************************/\n#define HRTIM_TIMICR_CMP1C_Pos        (0U)\n#define HRTIM_TIMICR_CMP1C_Msk        (0x1UL << HRTIM_TIMICR_CMP1C_Pos)        /*!< 0x00000001 */\n#define HRTIM_TIMICR_CMP1C            HRTIM_TIMICR_CMP1C_Msk                   /*!< Slave compare 1 clear flag */\n#define HRTIM_TIMICR_CMP2C_Pos        (1U)\n#define HRTIM_TIMICR_CMP2C_Msk        (0x1UL << HRTIM_TIMICR_CMP2C_Pos)        /*!< 0x00000002 */\n#define HRTIM_TIMICR_CMP2C            HRTIM_TIMICR_CMP2C_Msk                   /*!< Slave compare 2 clear flag */\n#define HRTIM_TIMICR_CMP3C_Pos        (2U)\n#define HRTIM_TIMICR_CMP3C_Msk        (0x1UL << HRTIM_TIMICR_CMP3C_Pos)        /*!< 0x00000004 */\n#define HRTIM_TIMICR_CMP3C            HRTIM_TIMICR_CMP3C_Msk                   /*!< Slave compare 3 clear flag */\n#define HRTIM_TIMICR_CMP4C_Pos        (3U)\n#define HRTIM_TIMICR_CMP4C_Msk        (0x1UL << HRTIM_TIMICR_CMP4C_Pos)        /*!< 0x00000008 */\n#define HRTIM_TIMICR_CMP4C            HRTIM_TIMICR_CMP4C_Msk                   /*!< Slave compare 4 clear flag */\n#define HRTIM_TIMICR_REPC_Pos         (4U)\n#define HRTIM_TIMICR_REPC_Msk         (0x1UL << HRTIM_TIMICR_REPC_Pos)         /*!< 0x00000010 */\n#define HRTIM_TIMICR_REPC             HRTIM_TIMICR_REPC_Msk                    /*!< Slave repetition clear flag */\n#define HRTIM_TIMICR_UPDC_Pos         (6U)\n#define HRTIM_TIMICR_UPDC_Msk         (0x1UL << HRTIM_TIMICR_UPDC_Pos)         /*!< 0x00000040 */\n#define HRTIM_TIMICR_UPDC             HRTIM_TIMICR_UPDC_Msk                    /*!< Slave update clear flag */\n#define HRTIM_TIMICR_CPT1C_Pos        (7U)\n#define HRTIM_TIMICR_CPT1C_Msk        (0x1UL << HRTIM_TIMICR_CPT1C_Pos)        /*!< 0x00000080 */\n#define HRTIM_TIMICR_CPT1C            HRTIM_TIMICR_CPT1C_Msk                   /*!< Slave capture 1 clear flag */\n#define HRTIM_TIMICR_CPT2C_Pos        (8U)\n#define HRTIM_TIMICR_CPT2C_Msk        (0x1UL << HRTIM_TIMICR_CPT2C_Pos)        /*!< 0x00000100 */\n#define HRTIM_TIMICR_CPT2C            HRTIM_TIMICR_CPT2C_Msk                   /*!< Slave capture 2 clear flag */\n#define HRTIM_TIMICR_SET1C_Pos        (9U)\n#define HRTIM_TIMICR_SET1C_Msk        (0x1UL << HRTIM_TIMICR_SET1C_Pos)        /*!< 0x00000200 */\n#define HRTIM_TIMICR_SET1C            HRTIM_TIMICR_SET1C_Msk                   /*!< Slave output 1 set clear flag */\n#define HRTIM_TIMICR_RST1C_Pos        (10U)\n#define HRTIM_TIMICR_RST1C_Msk        (0x1UL << HRTIM_TIMICR_RST1C_Pos)        /*!< 0x00000400 */\n#define HRTIM_TIMICR_RST1C            HRTIM_TIMICR_RST1C_Msk                   /*!< Slave output 1 reset clear flag */\n#define HRTIM_TIMICR_SET2C_Pos        (11U)\n#define HRTIM_TIMICR_SET2C_Msk        (0x1UL << HRTIM_TIMICR_SET2C_Pos)        /*!< 0x00000800 */\n#define HRTIM_TIMICR_SET2C            HRTIM_TIMICR_SET2C_Msk                   /*!< Slave output 2 set clear flag */\n#define HRTIM_TIMICR_RST2C_Pos        (12U)\n#define HRTIM_TIMICR_RST2C_Msk        (0x1UL << HRTIM_TIMICR_RST2C_Pos)        /*!< 0x00001000 */\n#define HRTIM_TIMICR_RST2C            HRTIM_TIMICR_RST2C_Msk                   /*!< Slave output 2 reset clear flag */\n#define HRTIM_TIMICR_RSTC_Pos         (13U)\n#define HRTIM_TIMICR_RSTC_Msk         (0x1UL << HRTIM_TIMICR_RSTC_Pos)         /*!< 0x00002000 */\n#define HRTIM_TIMICR_RSTC             HRTIM_TIMICR_RSTC_Msk                    /*!< Slave reset clear flag */\n#define HRTIM_TIMICR_DLYPRTC_Pos      (14U)\n#define HRTIM_TIMICR_DLYPRTC_Msk      (0x1UL << HRTIM_TIMICR_DLYPRTC_Pos)      /*!< 0x00004000 */\n#define HRTIM_TIMICR_DLYPRTC          HRTIM_TIMICR_DLYPRTC_Msk                 /*!< Slave output 1 delay protection clear flag */\n\n/******************** Slave DMA/Interrupt enable register *********************/\n#define HRTIM_TIMDIER_CMP1IE_Pos      (0U)\n#define HRTIM_TIMDIER_CMP1IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP1IE_Pos)      /*!< 0x00000001 */\n#define HRTIM_TIMDIER_CMP1IE          HRTIM_TIMDIER_CMP1IE_Msk                 /*!< Slave compare 1 interrupt enable */\n#define HRTIM_TIMDIER_CMP2IE_Pos      (1U)\n#define HRTIM_TIMDIER_CMP2IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP2IE_Pos)      /*!< 0x00000002 */\n#define HRTIM_TIMDIER_CMP2IE          HRTIM_TIMDIER_CMP2IE_Msk                 /*!< Slave compare 2 interrupt enable */\n#define HRTIM_TIMDIER_CMP3IE_Pos      (2U)\n#define HRTIM_TIMDIER_CMP3IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP3IE_Pos)      /*!< 0x00000004 */\n#define HRTIM_TIMDIER_CMP3IE          HRTIM_TIMDIER_CMP3IE_Msk                 /*!< Slave compare 3 interrupt enable */\n#define HRTIM_TIMDIER_CMP4IE_Pos      (3U)\n#define HRTIM_TIMDIER_CMP4IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP4IE_Pos)      /*!< 0x00000008 */\n#define HRTIM_TIMDIER_CMP4IE          HRTIM_TIMDIER_CMP4IE_Msk                 /*!< Slave compare 4 interrupt enable */\n#define HRTIM_TIMDIER_REPIE_Pos       (4U)\n#define HRTIM_TIMDIER_REPIE_Msk       (0x1UL << HRTIM_TIMDIER_REPIE_Pos)       /*!< 0x00000010 */\n#define HRTIM_TIMDIER_REPIE           HRTIM_TIMDIER_REPIE_Msk                  /*!< Slave repetition interrupt enable */\n#define HRTIM_TIMDIER_UPDIE_Pos       (6U)\n#define HRTIM_TIMDIER_UPDIE_Msk       (0x1UL << HRTIM_TIMDIER_UPDIE_Pos)       /*!< 0x00000040 */\n#define HRTIM_TIMDIER_UPDIE           HRTIM_TIMDIER_UPDIE_Msk                  /*!< Slave update interrupt enable */\n#define HRTIM_TIMDIER_CPT1IE_Pos      (7U)\n#define HRTIM_TIMDIER_CPT1IE_Msk      (0x1UL << HRTIM_TIMDIER_CPT1IE_Pos)      /*!< 0x00000080 */\n#define HRTIM_TIMDIER_CPT1IE          HRTIM_TIMDIER_CPT1IE_Msk                 /*!< Slave capture 1 interrupt enable */\n#define HRTIM_TIMDIER_CPT2IE_Pos      (8U)\n#define HRTIM_TIMDIER_CPT2IE_Msk      (0x1UL << HRTIM_TIMDIER_CPT2IE_Pos)      /*!< 0x00000100 */\n#define HRTIM_TIMDIER_CPT2IE          HRTIM_TIMDIER_CPT2IE_Msk                 /*!< Slave capture 2 interrupt enable */\n#define HRTIM_TIMDIER_SET1IE_Pos      (9U)\n#define HRTIM_TIMDIER_SET1IE_Msk      (0x1UL << HRTIM_TIMDIER_SET1IE_Pos)      /*!< 0x00000200 */\n#define HRTIM_TIMDIER_SET1IE          HRTIM_TIMDIER_SET1IE_Msk                 /*!< Slave output 1 set interrupt enable */\n#define HRTIM_TIMDIER_RST1IE_Pos      (10U)\n#define HRTIM_TIMDIER_RST1IE_Msk      (0x1UL << HRTIM_TIMDIER_RST1IE_Pos)      /*!< 0x00000400 */\n#define HRTIM_TIMDIER_RST1IE          HRTIM_TIMDIER_RST1IE_Msk                 /*!< Slave output 1 reset interrupt enable */\n#define HRTIM_TIMDIER_SET2IE_Pos      (11U)\n#define HRTIM_TIMDIER_SET2IE_Msk      (0x1UL << HRTIM_TIMDIER_SET2IE_Pos)      /*!< 0x00000800 */\n#define HRTIM_TIMDIER_SET2IE          HRTIM_TIMDIER_SET2IE_Msk                 /*!< Slave output 2 set interrupt enable */\n#define HRTIM_TIMDIER_RST2IE_Pos      (12U)\n#define HRTIM_TIMDIER_RST2IE_Msk      (0x1UL << HRTIM_TIMDIER_RST2IE_Pos)      /*!< 0x00001000 */\n#define HRTIM_TIMDIER_RST2IE          HRTIM_TIMDIER_RST2IE_Msk                 /*!< Slave output 2 reset interrupt enable */\n#define HRTIM_TIMDIER_RSTIE_Pos       (13U)\n#define HRTIM_TIMDIER_RSTIE_Msk       (0x1UL << HRTIM_TIMDIER_RSTIE_Pos)       /*!< 0x00002000 */\n#define HRTIM_TIMDIER_RSTIE           HRTIM_TIMDIER_RSTIE_Msk                  /*!< Slave reset interrupt enable */\n#define HRTIM_TIMDIER_DLYPRTIE_Pos    (14U)\n#define HRTIM_TIMDIER_DLYPRTIE_Msk    (0x1UL << HRTIM_TIMDIER_DLYPRTIE_Pos)    /*!< 0x00004000 */\n#define HRTIM_TIMDIER_DLYPRTIE        HRTIM_TIMDIER_DLYPRTIE_Msk               /*!< Slave delay protection interrupt enable */\n\n#define HRTIM_TIMDIER_CMP1DE_Pos      (16U)\n#define HRTIM_TIMDIER_CMP1DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP1DE_Pos)      /*!< 0x00010000 */\n#define HRTIM_TIMDIER_CMP1DE          HRTIM_TIMDIER_CMP1DE_Msk                 /*!< Slave compare 1 request enable */\n#define HRTIM_TIMDIER_CMP2DE_Pos      (17U)\n#define HRTIM_TIMDIER_CMP2DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP2DE_Pos)      /*!< 0x00020000 */\n#define HRTIM_TIMDIER_CMP2DE          HRTIM_TIMDIER_CMP2DE_Msk                 /*!< Slave compare 2 request enable */\n#define HRTIM_TIMDIER_CMP3DE_Pos      (18U)\n#define HRTIM_TIMDIER_CMP3DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP3DE_Pos)      /*!< 0x00040000 */\n#define HRTIM_TIMDIER_CMP3DE          HRTIM_TIMDIER_CMP3DE_Msk                 /*!< Slave compare 3 request enable */\n#define HRTIM_TIMDIER_CMP4DE_Pos      (19U)\n#define HRTIM_TIMDIER_CMP4DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP4DE_Pos)      /*!< 0x00080000 */\n#define HRTIM_TIMDIER_CMP4DE          HRTIM_TIMDIER_CMP4DE_Msk                 /*!< Slave compare 4 request enable */\n#define HRTIM_TIMDIER_REPDE_Pos       (20U)\n#define HRTIM_TIMDIER_REPDE_Msk       (0x1UL << HRTIM_TIMDIER_REPDE_Pos)       /*!< 0x00100000 */\n#define HRTIM_TIMDIER_REPDE           HRTIM_TIMDIER_REPDE_Msk                  /*!< Slave repetition request enable */\n#define HRTIM_TIMDIER_UPDDE_Pos       (22U)\n#define HRTIM_TIMDIER_UPDDE_Msk       (0x1UL << HRTIM_TIMDIER_UPDDE_Pos)       /*!< 0x00400000 */\n#define HRTIM_TIMDIER_UPDDE           HRTIM_TIMDIER_UPDDE_Msk                  /*!< Slave update request enable */\n#define HRTIM_TIMDIER_CPT1DE_Pos      (23U)\n#define HRTIM_TIMDIER_CPT1DE_Msk      (0x1UL << HRTIM_TIMDIER_CPT1DE_Pos)      /*!< 0x00800000 */\n#define HRTIM_TIMDIER_CPT1DE          HRTIM_TIMDIER_CPT1DE_Msk                 /*!< Slave capture 1 request enable */\n#define HRTIM_TIMDIER_CPT2DE_Pos      (24U)\n#define HRTIM_TIMDIER_CPT2DE_Msk      (0x1UL << HRTIM_TIMDIER_CPT2DE_Pos)      /*!< 0x01000000 */\n#define HRTIM_TIMDIER_CPT2DE          HRTIM_TIMDIER_CPT2DE_Msk                 /*!< Slave capture 2 request enable */\n#define HRTIM_TIMDIER_SET1DE_Pos      (25U)\n#define HRTIM_TIMDIER_SET1DE_Msk      (0x1UL << HRTIM_TIMDIER_SET1DE_Pos)      /*!< 0x02000000 */\n#define HRTIM_TIMDIER_SET1DE          HRTIM_TIMDIER_SET1DE_Msk                 /*!< Slave output 1 set request enable */\n#define HRTIM_TIMDIER_RST1DE_Pos      (26U)\n#define HRTIM_TIMDIER_RST1DE_Msk      (0x1UL << HRTIM_TIMDIER_RST1DE_Pos)      /*!< 0x04000000 */\n#define HRTIM_TIMDIER_RST1DE          HRTIM_TIMDIER_RST1DE_Msk                 /*!< Slave output 1 reset request enable */\n#define HRTIM_TIMDIER_SET2DE_Pos      (27U)\n#define HRTIM_TIMDIER_SET2DE_Msk      (0x1UL << HRTIM_TIMDIER_SET2DE_Pos)      /*!< 0x08000000 */\n#define HRTIM_TIMDIER_SET2DE          HRTIM_TIMDIER_SET2DE_Msk                 /*!< Slave output 2 set request enable */\n#define HRTIM_TIMDIER_RST2DE_Pos      (28U)\n#define HRTIM_TIMDIER_RST2DE_Msk      (0x1UL << HRTIM_TIMDIER_RST2DE_Pos)      /*!< 0x10000000 */\n#define HRTIM_TIMDIER_RST2DE          HRTIM_TIMDIER_RST2DE_Msk                 /*!< Slave output 2 reset request enable */\n#define HRTIM_TIMDIER_RSTDE_Pos       (29U)\n#define HRTIM_TIMDIER_RSTDE_Msk       (0x1UL << HRTIM_TIMDIER_RSTDE_Pos)       /*!< 0x20000000 */\n#define HRTIM_TIMDIER_RSTDE           HRTIM_TIMDIER_RSTDE_Msk                  /*!< Slave reset request enable */\n#define HRTIM_TIMDIER_DLYPRTDE_Pos    (30U)\n#define HRTIM_TIMDIER_DLYPRTDE_Msk    (0x1UL << HRTIM_TIMDIER_DLYPRTDE_Pos)    /*!< 0x40000000 */\n#define HRTIM_TIMDIER_DLYPRTDE        HRTIM_TIMDIER_DLYPRTDE_Msk               /*!< Slavedelay protection request enable */\n\n/******************  Bit definition for HRTIM_CNTR register  ****************/\n#define HRTIM_CNTR_CNTR_Pos           (0U)\n#define HRTIM_CNTR_CNTR_Msk           (0xFFFFUL << HRTIM_CNTR_CNTR_Pos)        /*!< 0x0000FFFF */\n#define HRTIM_CNTR_CNTR               HRTIM_CNTR_CNTR_Msk                      /*!< Counter Value */\n\n/*******************  Bit definition for HRTIM_PER register  *****************/\n#define HRTIM_PER_PER_Pos             (0U)\n#define HRTIM_PER_PER_Msk             (0xFFFFUL << HRTIM_PER_PER_Pos)          /*!< 0x0000FFFF */\n#define HRTIM_PER_PER                 HRTIM_PER_PER_Msk                        /*!< Period Value */\n\n/*******************  Bit definition for HRTIM_REP register  *****************/\n#define HRTIM_REP_REP_Pos             (0U)\n#define HRTIM_REP_REP_Msk             (0xFFUL << HRTIM_REP_REP_Pos)            /*!< 0x000000FF */\n#define HRTIM_REP_REP                 HRTIM_REP_REP_Msk                        /*!< Repetition Value */\n\n/*******************  Bit definition for HRTIM_CMP1R register  *****************/\n#define HRTIM_CMP1R_CMP1R_Pos         (0U)\n#define HRTIM_CMP1R_CMP1R_Msk         (0xFFFFUL << HRTIM_CMP1R_CMP1R_Pos)      /*!< 0x0000FFFF */\n#define HRTIM_CMP1R_CMP1R             HRTIM_CMP1R_CMP1R_Msk                    /*!< Compare Value */\n\n/*******************  Bit definition for HRTIM_CMP1CR register  *****************/\n#define HRTIM_CMP1CR_CMP1CR_Pos       (0U)\n#define HRTIM_CMP1CR_CMP1CR_Msk       (0xFFFFFFFFUL << HRTIM_CMP1CR_CMP1CR_Pos) /*!< 0xFFFFFFFF */\n#define HRTIM_CMP1CR_CMP1CR           HRTIM_CMP1CR_CMP1CR_Msk                  /*!< Compare Value */\n\n/*******************  Bit definition for HRTIM_CMP2R register  *****************/\n#define HRTIM_CMP2R_CMP2R_Pos         (0U)\n#define HRTIM_CMP2R_CMP2R_Msk         (0xFFFFUL << HRTIM_CMP2R_CMP2R_Pos)      /*!< 0x0000FFFF */\n#define HRTIM_CMP2R_CMP2R             HRTIM_CMP2R_CMP2R_Msk                    /*!< Compare Value */\n\n/*******************  Bit definition for HRTIM_CMP3R register  *****************/\n#define HRTIM_CMP3R_CMP3R_Pos         (0U)\n#define HRTIM_CMP3R_CMP3R_Msk         (0xFFFFUL << HRTIM_CMP3R_CMP3R_Pos)      /*!< 0x0000FFFF */\n#define HRTIM_CMP3R_CMP3R             HRTIM_CMP3R_CMP3R_Msk                    /*!< Compare Value */\n\n/*******************  Bit definition for HRTIM_CMP4R register  *****************/\n#define HRTIM_CMP4R_CMP4R_Pos         (0U)\n#define HRTIM_CMP4R_CMP4R_Msk         (0xFFFFUL << HRTIM_CMP4R_CMP4R_Pos)      /*!< 0x0000FFFF */\n#define HRTIM_CMP4R_CMP4R             HRTIM_CMP4R_CMP4R_Msk                    /*!< Compare Value */\n\n/*******************  Bit definition for HRTIM_CPT1R register  ****************/\n#define HRTIM_CPT1R_CPT1R_Pos         (0U)\n#define HRTIM_CPT1R_CPT1R_Msk         (0xFFFFUL << HRTIM_CPT1R_CPT1R_Pos)      /*!< 0x0000FFFF */\n#define HRTIM_CPT1R_CPT1R             HRTIM_CPT1R_CPT1R_Msk                    /*!< Capture Value */\n\n/*******************  Bit definition for HRTIM_CPT2R register  ****************/\n#define HRTIM_CPT2R_CPT2R_Pos         (0U)\n#define HRTIM_CPT2R_CPT2R_Msk         (0xFFFFUL << HRTIM_CPT2R_CPT2R_Pos)      /*!< 0x0000FFFF */\n#define HRTIM_CPT2R_CPT2R             HRTIM_CPT2R_CPT2R_Msk                    /*!< Capture Value */\n\n/******************** Bit definition for Slave Deadtime register **************/\n#define HRTIM_DTR_DTR_Pos             (0U)\n#define HRTIM_DTR_DTR_Msk             (0x1FFUL << HRTIM_DTR_DTR_Pos)           /*!< 0x000001FF */\n#define HRTIM_DTR_DTR                 HRTIM_DTR_DTR_Msk                        /*!< Dead time rising value */\n#define HRTIM_DTR_DTR_0               (0x001UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000001 */\n#define HRTIM_DTR_DTR_1               (0x002UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000002 */\n#define HRTIM_DTR_DTR_2               (0x004UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000004 */\n#define HRTIM_DTR_DTR_3               (0x008UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000008 */\n#define HRTIM_DTR_DTR_4               (0x010UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000010 */\n#define HRTIM_DTR_DTR_5               (0x020UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000020 */\n#define HRTIM_DTR_DTR_6               (0x040UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000040 */\n#define HRTIM_DTR_DTR_7               (0x080UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000080 */\n#define HRTIM_DTR_DTR_8               (0x100UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000100 */\n#define HRTIM_DTR_SDTR_Pos            (9U)\n#define HRTIM_DTR_SDTR_Msk            (0x1UL << HRTIM_DTR_SDTR_Pos)            /*!< 0x00000200 */\n#define HRTIM_DTR_SDTR                HRTIM_DTR_SDTR_Msk                       /*!< Sign dead time rising value */\n#define HRTIM_DTR_DTPRSC_Pos          (10U)\n#define HRTIM_DTR_DTPRSC_Msk          (0x7UL << HRTIM_DTR_DTPRSC_Pos)          /*!< 0x00001C00 */\n#define HRTIM_DTR_DTPRSC              HRTIM_DTR_DTPRSC_Msk                     /*!< Dead time prescaler */\n#define HRTIM_DTR_DTPRSC_0            (0x1UL << HRTIM_DTR_DTPRSC_Pos)           /*!< 0x00000400 */\n#define HRTIM_DTR_DTPRSC_1            (0x2UL << HRTIM_DTR_DTPRSC_Pos)           /*!< 0x00000800 */\n#define HRTIM_DTR_DTPRSC_2            (0x4UL << HRTIM_DTR_DTPRSC_Pos)           /*!< 0x00001000 */\n#define HRTIM_DTR_DTRSLK_Pos          (14U)\n#define HRTIM_DTR_DTRSLK_Msk          (0x1UL << HRTIM_DTR_DTRSLK_Pos)          /*!< 0x00004000 */\n#define HRTIM_DTR_DTRSLK              HRTIM_DTR_DTRSLK_Msk                     /*!< Dead time rising sign lock */\n#define HRTIM_DTR_DTRLK_Pos           (15U)\n#define HRTIM_DTR_DTRLK_Msk           (0x1UL << HRTIM_DTR_DTRLK_Pos)           /*!< 0x00008000 */\n#define HRTIM_DTR_DTRLK               HRTIM_DTR_DTRLK_Msk                      /*!< Dead time rising lock */\n#define HRTIM_DTR_DTF_Pos             (16U)\n#define HRTIM_DTR_DTF_Msk             (0x1FFUL << HRTIM_DTR_DTF_Pos)           /*!< 0x01FF0000 */\n#define HRTIM_DTR_DTF                 HRTIM_DTR_DTF_Msk                        /*!< Dead time falling value */\n#define HRTIM_DTR_DTF_0               (0x001UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00010000 */\n#define HRTIM_DTR_DTF_1               (0x002UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00020000 */\n#define HRTIM_DTR_DTF_2               (0x004UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00040000 */\n#define HRTIM_DTR_DTF_3               (0x008UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00080000 */\n#define HRTIM_DTR_DTF_4               (0x010UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00100000 */\n#define HRTIM_DTR_DTF_5               (0x020UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00200000 */\n#define HRTIM_DTR_DTF_6               (0x040UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00400000 */\n#define HRTIM_DTR_DTF_7               (0x080UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00800000 */\n#define HRTIM_DTR_DTF_8               (0x100UL << HRTIM_DTR_DTF_Pos)            /*!< 0x01000000 */\n#define HRTIM_DTR_SDTF_Pos            (25U)\n#define HRTIM_DTR_SDTF_Msk            (0x1UL << HRTIM_DTR_SDTF_Pos)            /*!< 0x02000000 */\n#define HRTIM_DTR_SDTF                HRTIM_DTR_SDTF_Msk                       /*!< Sign dead time falling value */\n#define HRTIM_DTR_DTFSLK_Pos          (30U)\n#define HRTIM_DTR_DTFSLK_Msk          (0x1UL << HRTIM_DTR_DTFSLK_Pos)          /*!< 0x40000000 */\n#define HRTIM_DTR_DTFSLK              HRTIM_DTR_DTFSLK_Msk                     /*!< Dead time falling sign lock */\n#define HRTIM_DTR_DTFLK_Pos           (31U)\n#define HRTIM_DTR_DTFLK_Msk           (0x1UL << HRTIM_DTR_DTFLK_Pos)           /*!< 0x80000000 */\n#define HRTIM_DTR_DTFLK               HRTIM_DTR_DTFLK_Msk                      /*!< Dead time falling lock */\n\n/**** Bit definition for Slave Output 1 set register **************************/\n#define HRTIM_SET1R_SST_Pos           (0U)\n#define HRTIM_SET1R_SST_Msk           (0x1UL << HRTIM_SET1R_SST_Pos)           /*!< 0x00000001 */\n#define HRTIM_SET1R_SST               HRTIM_SET1R_SST_Msk                      /*!< software set trigger */\n#define HRTIM_SET1R_RESYNC_Pos        (1U)\n#define HRTIM_SET1R_RESYNC_Msk        (0x1UL << HRTIM_SET1R_RESYNC_Pos)        /*!< 0x00000002 */\n#define HRTIM_SET1R_RESYNC            HRTIM_SET1R_RESYNC_Msk                   /*!< Timer A resynchronization */\n#define HRTIM_SET1R_PER_Pos           (2U)\n#define HRTIM_SET1R_PER_Msk           (0x1UL << HRTIM_SET1R_PER_Pos)           /*!< 0x00000004 */\n#define HRTIM_SET1R_PER               HRTIM_SET1R_PER_Msk                      /*!< Timer A period */\n#define HRTIM_SET1R_CMP1_Pos          (3U)\n#define HRTIM_SET1R_CMP1_Msk          (0x1UL << HRTIM_SET1R_CMP1_Pos)          /*!< 0x00000008 */\n#define HRTIM_SET1R_CMP1              HRTIM_SET1R_CMP1_Msk                     /*!< Timer A compare 1 */\n#define HRTIM_SET1R_CMP2_Pos          (4U)\n#define HRTIM_SET1R_CMP2_Msk          (0x1UL << HRTIM_SET1R_CMP2_Pos)          /*!< 0x00000010 */\n#define HRTIM_SET1R_CMP2              HRTIM_SET1R_CMP2_Msk                     /*!< Timer A compare 2 */\n#define HRTIM_SET1R_CMP3_Pos          (5U)\n#define HRTIM_SET1R_CMP3_Msk          (0x1UL << HRTIM_SET1R_CMP3_Pos)          /*!< 0x00000020 */\n#define HRTIM_SET1R_CMP3              HRTIM_SET1R_CMP3_Msk                     /*!< Timer A compare 3 */\n#define HRTIM_SET1R_CMP4_Pos          (6U)\n#define HRTIM_SET1R_CMP4_Msk          (0x1UL << HRTIM_SET1R_CMP4_Pos)          /*!< 0x00000040 */\n#define HRTIM_SET1R_CMP4              HRTIM_SET1R_CMP4_Msk                     /*!< Timer A compare 4 */\n\n#define HRTIM_SET1R_MSTPER_Pos        (7U)\n#define HRTIM_SET1R_MSTPER_Msk        (0x1UL << HRTIM_SET1R_MSTPER_Pos)        /*!< 0x00000080 */\n#define HRTIM_SET1R_MSTPER            HRTIM_SET1R_MSTPER_Msk                   /*!< Master period */\n#define HRTIM_SET1R_MSTCMP1_Pos       (8U)\n#define HRTIM_SET1R_MSTCMP1_Msk       (0x1UL << HRTIM_SET1R_MSTCMP1_Pos)       /*!< 0x00000100 */\n#define HRTIM_SET1R_MSTCMP1           HRTIM_SET1R_MSTCMP1_Msk                  /*!< Master compare 1 */\n#define HRTIM_SET1R_MSTCMP2_Pos       (9U)\n#define HRTIM_SET1R_MSTCMP2_Msk       (0x1UL << HRTIM_SET1R_MSTCMP2_Pos)       /*!< 0x00000200 */\n#define HRTIM_SET1R_MSTCMP2           HRTIM_SET1R_MSTCMP2_Msk                  /*!< Master compare 2 */\n#define HRTIM_SET1R_MSTCMP3_Pos       (10U)\n#define HRTIM_SET1R_MSTCMP3_Msk       (0x1UL << HRTIM_SET1R_MSTCMP3_Pos)       /*!< 0x00000400 */\n#define HRTIM_SET1R_MSTCMP3           HRTIM_SET1R_MSTCMP3_Msk                  /*!< Master compare 3 */\n#define HRTIM_SET1R_MSTCMP4_Pos       (11U)\n#define HRTIM_SET1R_MSTCMP4_Msk       (0x1UL << HRTIM_SET1R_MSTCMP4_Pos)       /*!< 0x00000800 */\n#define HRTIM_SET1R_MSTCMP4           HRTIM_SET1R_MSTCMP4_Msk                  /*!< Master compare 4 */\n\n#define HRTIM_SET1R_TIMEVNT1_Pos      (12U)\n#define HRTIM_SET1R_TIMEVNT1_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT1_Pos)      /*!< 0x00001000 */\n#define HRTIM_SET1R_TIMEVNT1          HRTIM_SET1R_TIMEVNT1_Msk                 /*!< Timer event 1 */\n#define HRTIM_SET1R_TIMEVNT2_Pos      (13U)\n#define HRTIM_SET1R_TIMEVNT2_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT2_Pos)      /*!< 0x00002000 */\n#define HRTIM_SET1R_TIMEVNT2          HRTIM_SET1R_TIMEVNT2_Msk                 /*!< Timer event 2 */\n#define HRTIM_SET1R_TIMEVNT3_Pos      (14U)\n#define HRTIM_SET1R_TIMEVNT3_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT3_Pos)      /*!< 0x00004000 */\n#define HRTIM_SET1R_TIMEVNT3          HRTIM_SET1R_TIMEVNT3_Msk                 /*!< Timer event 3 */\n#define HRTIM_SET1R_TIMEVNT4_Pos      (15U)\n#define HRTIM_SET1R_TIMEVNT4_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT4_Pos)      /*!< 0x00008000 */\n#define HRTIM_SET1R_TIMEVNT4          HRTIM_SET1R_TIMEVNT4_Msk                 /*!< Timer event 4 */\n#define HRTIM_SET1R_TIMEVNT5_Pos      (16U)\n#define HRTIM_SET1R_TIMEVNT5_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT5_Pos)      /*!< 0x00010000 */\n#define HRTIM_SET1R_TIMEVNT5          HRTIM_SET1R_TIMEVNT5_Msk                 /*!< Timer event 5 */\n#define HRTIM_SET1R_TIMEVNT6_Pos      (17U)\n#define HRTIM_SET1R_TIMEVNT6_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT6_Pos)      /*!< 0x00020000 */\n#define HRTIM_SET1R_TIMEVNT6          HRTIM_SET1R_TIMEVNT6_Msk                 /*!< Timer event 6 */\n#define HRTIM_SET1R_TIMEVNT7_Pos      (18U)\n#define HRTIM_SET1R_TIMEVNT7_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT7_Pos)      /*!< 0x00040000 */\n#define HRTIM_SET1R_TIMEVNT7          HRTIM_SET1R_TIMEVNT7_Msk                 /*!< Timer event 7 */\n#define HRTIM_SET1R_TIMEVNT8_Pos      (19U)\n#define HRTIM_SET1R_TIMEVNT8_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT8_Pos)      /*!< 0x00080000 */\n#define HRTIM_SET1R_TIMEVNT8          HRTIM_SET1R_TIMEVNT8_Msk                 /*!< Timer event 8 */\n#define HRTIM_SET1R_TIMEVNT9_Pos      (20U)\n#define HRTIM_SET1R_TIMEVNT9_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT9_Pos)      /*!< 0x00100000 */\n#define HRTIM_SET1R_TIMEVNT9          HRTIM_SET1R_TIMEVNT9_Msk                 /*!< Timer event 9 */\n\n#define HRTIM_SET1R_EXTVNT1_Pos       (21U)\n#define HRTIM_SET1R_EXTVNT1_Msk       (0x1UL << HRTIM_SET1R_EXTVNT1_Pos)       /*!< 0x00200000 */\n#define HRTIM_SET1R_EXTVNT1           HRTIM_SET1R_EXTVNT1_Msk                  /*!< External event 1 */\n#define HRTIM_SET1R_EXTVNT2_Pos       (22U)\n#define HRTIM_SET1R_EXTVNT2_Msk       (0x1UL << HRTIM_SET1R_EXTVNT2_Pos)       /*!< 0x00400000 */\n#define HRTIM_SET1R_EXTVNT2           HRTIM_SET1R_EXTVNT2_Msk                  /*!< External event 2 */\n#define HRTIM_SET1R_EXTVNT3_Pos       (23U)\n#define HRTIM_SET1R_EXTVNT3_Msk       (0x1UL << HRTIM_SET1R_EXTVNT3_Pos)       /*!< 0x00800000 */\n#define HRTIM_SET1R_EXTVNT3           HRTIM_SET1R_EXTVNT3_Msk                  /*!< External event 3 */\n#define HRTIM_SET1R_EXTVNT4_Pos       (24U)\n#define HRTIM_SET1R_EXTVNT4_Msk       (0x1UL << HRTIM_SET1R_EXTVNT4_Pos)       /*!< 0x01000000 */\n#define HRTIM_SET1R_EXTVNT4           HRTIM_SET1R_EXTVNT4_Msk                  /*!< External event 4 */\n#define HRTIM_SET1R_EXTVNT5_Pos       (25U)\n#define HRTIM_SET1R_EXTVNT5_Msk       (0x1UL << HRTIM_SET1R_EXTVNT5_Pos)       /*!< 0x02000000 */\n#define HRTIM_SET1R_EXTVNT5           HRTIM_SET1R_EXTVNT5_Msk                  /*!< External event 5 */\n#define HRTIM_SET1R_EXTVNT6_Pos       (26U)\n#define HRTIM_SET1R_EXTVNT6_Msk       (0x1UL << HRTIM_SET1R_EXTVNT6_Pos)       /*!< 0x04000000 */\n#define HRTIM_SET1R_EXTVNT6           HRTIM_SET1R_EXTVNT6_Msk                  /*!< External event 6 */\n#define HRTIM_SET1R_EXTVNT7_Pos       (27U)\n#define HRTIM_SET1R_EXTVNT7_Msk       (0x1UL << HRTIM_SET1R_EXTVNT7_Pos)       /*!< 0x08000000 */\n#define HRTIM_SET1R_EXTVNT7           HRTIM_SET1R_EXTVNT7_Msk                  /*!< External event 7 */\n#define HRTIM_SET1R_EXTVNT8_Pos       (28U)\n#define HRTIM_SET1R_EXTVNT8_Msk       (0x1UL << HRTIM_SET1R_EXTVNT8_Pos)       /*!< 0x10000000 */\n#define HRTIM_SET1R_EXTVNT8           HRTIM_SET1R_EXTVNT8_Msk                  /*!< External event 8 */\n#define HRTIM_SET1R_EXTVNT9_Pos       (29U)\n#define HRTIM_SET1R_EXTVNT9_Msk       (0x1UL << HRTIM_SET1R_EXTVNT9_Pos)       /*!< 0x20000000 */\n#define HRTIM_SET1R_EXTVNT9           HRTIM_SET1R_EXTVNT9_Msk                  /*!< External event 9 */\n#define HRTIM_SET1R_EXTVNT10_Pos      (30U)\n#define HRTIM_SET1R_EXTVNT10_Msk      (0x1UL << HRTIM_SET1R_EXTVNT10_Pos)      /*!< 0x40000000 */\n#define HRTIM_SET1R_EXTVNT10          HRTIM_SET1R_EXTVNT10_Msk                 /*!< External event 10 */\n\n#define HRTIM_SET1R_UPDATE_Pos        (31U)\n#define HRTIM_SET1R_UPDATE_Msk        (0x1UL << HRTIM_SET1R_UPDATE_Pos)        /*!< 0x80000000 */\n#define HRTIM_SET1R_UPDATE            HRTIM_SET1R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */\n\n/**** Bit definition for Slave Output 1 reset register ************************/\n#define HRTIM_RST1R_SRT_Pos           (0U)\n#define HRTIM_RST1R_SRT_Msk           (0x1UL << HRTIM_RST1R_SRT_Pos)           /*!< 0x00000001 */\n#define HRTIM_RST1R_SRT               HRTIM_RST1R_SRT_Msk                      /*!< software reset trigger */\n#define HRTIM_RST1R_RESYNC_Pos        (1U)\n#define HRTIM_RST1R_RESYNC_Msk        (0x1UL << HRTIM_RST1R_RESYNC_Pos)        /*!< 0x00000002 */\n#define HRTIM_RST1R_RESYNC            HRTIM_RST1R_RESYNC_Msk                   /*!< Timer A resynchronization */\n#define HRTIM_RST1R_PER_Pos           (2U)\n#define HRTIM_RST1R_PER_Msk           (0x1UL << HRTIM_RST1R_PER_Pos)           /*!< 0x00000004 */\n#define HRTIM_RST1R_PER               HRTIM_RST1R_PER_Msk                      /*!< Timer A period */\n#define HRTIM_RST1R_CMP1_Pos          (3U)\n#define HRTIM_RST1R_CMP1_Msk          (0x1UL << HRTIM_RST1R_CMP1_Pos)          /*!< 0x00000008 */\n#define HRTIM_RST1R_CMP1              HRTIM_RST1R_CMP1_Msk                     /*!< Timer A compare 1 */\n#define HRTIM_RST1R_CMP2_Pos          (4U)\n#define HRTIM_RST1R_CMP2_Msk          (0x1UL << HRTIM_RST1R_CMP2_Pos)          /*!< 0x00000010 */\n#define HRTIM_RST1R_CMP2              HRTIM_RST1R_CMP2_Msk                     /*!< Timer A compare 2 */\n#define HRTIM_RST1R_CMP3_Pos          (5U)\n#define HRTIM_RST1R_CMP3_Msk          (0x1UL << HRTIM_RST1R_CMP3_Pos)          /*!< 0x00000020 */\n#define HRTIM_RST1R_CMP3              HRTIM_RST1R_CMP3_Msk                     /*!< Timer A compare 3 */\n#define HRTIM_RST1R_CMP4_Pos          (6U)\n#define HRTIM_RST1R_CMP4_Msk          (0x1UL << HRTIM_RST1R_CMP4_Pos)          /*!< 0x00000040 */\n#define HRTIM_RST1R_CMP4              HRTIM_RST1R_CMP4_Msk                     /*!< Timer A compare 4 */\n\n#define HRTIM_RST1R_MSTPER_Pos        (7U)\n#define HRTIM_RST1R_MSTPER_Msk        (0x1UL << HRTIM_RST1R_MSTPER_Pos)        /*!< 0x00000080 */\n#define HRTIM_RST1R_MSTPER            HRTIM_RST1R_MSTPER_Msk                   /*!< Master period */\n#define HRTIM_RST1R_MSTCMP1_Pos       (8U)\n#define HRTIM_RST1R_MSTCMP1_Msk       (0x1UL << HRTIM_RST1R_MSTCMP1_Pos)       /*!< 0x00000100 */\n#define HRTIM_RST1R_MSTCMP1           HRTIM_RST1R_MSTCMP1_Msk                  /*!< Master compare 1 */\n#define HRTIM_RST1R_MSTCMP2_Pos       (9U)\n#define HRTIM_RST1R_MSTCMP2_Msk       (0x1UL << HRTIM_RST1R_MSTCMP2_Pos)       /*!< 0x00000200 */\n#define HRTIM_RST1R_MSTCMP2           HRTIM_RST1R_MSTCMP2_Msk                  /*!< Master compare 2 */\n#define HRTIM_RST1R_MSTCMP3_Pos       (10U)\n#define HRTIM_RST1R_MSTCMP3_Msk       (0x1UL << HRTIM_RST1R_MSTCMP3_Pos)       /*!< 0x00000400 */\n#define HRTIM_RST1R_MSTCMP3           HRTIM_RST1R_MSTCMP3_Msk                  /*!< Master compare 3 */\n#define HRTIM_RST1R_MSTCMP4_Pos       (11U)\n#define HRTIM_RST1R_MSTCMP4_Msk       (0x1UL << HRTIM_RST1R_MSTCMP4_Pos)       /*!< 0x00000800 */\n#define HRTIM_RST1R_MSTCMP4           HRTIM_RST1R_MSTCMP4_Msk                  /*!< Master compare 4 */\n\n#define HRTIM_RST1R_TIMEVNT1_Pos      (12U)\n#define HRTIM_RST1R_TIMEVNT1_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT1_Pos)      /*!< 0x00001000 */\n#define HRTIM_RST1R_TIMEVNT1          HRTIM_RST1R_TIMEVNT1_Msk                 /*!< Timer event 1 */\n#define HRTIM_RST1R_TIMEVNT2_Pos      (13U)\n#define HRTIM_RST1R_TIMEVNT2_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT2_Pos)      /*!< 0x00002000 */\n#define HRTIM_RST1R_TIMEVNT2          HRTIM_RST1R_TIMEVNT2_Msk                 /*!< Timer event 2 */\n#define HRTIM_RST1R_TIMEVNT3_Pos      (14U)\n#define HRTIM_RST1R_TIMEVNT3_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT3_Pos)      /*!< 0x00004000 */\n#define HRTIM_RST1R_TIMEVNT3          HRTIM_RST1R_TIMEVNT3_Msk                 /*!< Timer event 3 */\n#define HRTIM_RST1R_TIMEVNT4_Pos      (15U)\n#define HRTIM_RST1R_TIMEVNT4_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT4_Pos)      /*!< 0x00008000 */\n#define HRTIM_RST1R_TIMEVNT4          HRTIM_RST1R_TIMEVNT4_Msk                 /*!< Timer event 4 */\n#define HRTIM_RST1R_TIMEVNT5_Pos      (16U)\n#define HRTIM_RST1R_TIMEVNT5_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT5_Pos)      /*!< 0x00010000 */\n#define HRTIM_RST1R_TIMEVNT5          HRTIM_RST1R_TIMEVNT5_Msk                 /*!< Timer event 5 */\n#define HRTIM_RST1R_TIMEVNT6_Pos      (17U)\n#define HRTIM_RST1R_TIMEVNT6_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT6_Pos)      /*!< 0x00020000 */\n#define HRTIM_RST1R_TIMEVNT6          HRTIM_RST1R_TIMEVNT6_Msk                 /*!< Timer event 6 */\n#define HRTIM_RST1R_TIMEVNT7_Pos      (18U)\n#define HRTIM_RST1R_TIMEVNT7_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT7_Pos)      /*!< 0x00040000 */\n#define HRTIM_RST1R_TIMEVNT7          HRTIM_RST1R_TIMEVNT7_Msk                 /*!< Timer event 7 */\n#define HRTIM_RST1R_TIMEVNT8_Pos      (19U)\n#define HRTIM_RST1R_TIMEVNT8_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT8_Pos)      /*!< 0x00080000 */\n#define HRTIM_RST1R_TIMEVNT8          HRTIM_RST1R_TIMEVNT8_Msk                 /*!< Timer event 8 */\n#define HRTIM_RST1R_TIMEVNT9_Pos      (20U)\n#define HRTIM_RST1R_TIMEVNT9_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT9_Pos)      /*!< 0x00100000 */\n#define HRTIM_RST1R_TIMEVNT9          HRTIM_RST1R_TIMEVNT9_Msk                 /*!< Timer event 9 */\n\n#define HRTIM_RST1R_EXTVNT1_Pos       (21U)\n#define HRTIM_RST1R_EXTVNT1_Msk       (0x1UL << HRTIM_RST1R_EXTVNT1_Pos)       /*!< 0x00200000 */\n#define HRTIM_RST1R_EXTVNT1           HRTIM_RST1R_EXTVNT1_Msk                  /*!< External event 1 */\n#define HRTIM_RST1R_EXTVNT2_Pos       (22U)\n#define HRTIM_RST1R_EXTVNT2_Msk       (0x1UL << HRTIM_RST1R_EXTVNT2_Pos)       /*!< 0x00400000 */\n#define HRTIM_RST1R_EXTVNT2           HRTIM_RST1R_EXTVNT2_Msk                  /*!< External event 2 */\n#define HRTIM_RST1R_EXTVNT3_Pos       (23U)\n#define HRTIM_RST1R_EXTVNT3_Msk       (0x1UL << HRTIM_RST1R_EXTVNT3_Pos)       /*!< 0x00800000 */\n#define HRTIM_RST1R_EXTVNT3           HRTIM_RST1R_EXTVNT3_Msk                  /*!< External event 3 */\n#define HRTIM_RST1R_EXTVNT4_Pos       (24U)\n#define HRTIM_RST1R_EXTVNT4_Msk       (0x1UL << HRTIM_RST1R_EXTVNT4_Pos)       /*!< 0x01000000 */\n#define HRTIM_RST1R_EXTVNT4           HRTIM_RST1R_EXTVNT4_Msk                  /*!< External event 4 */\n#define HRTIM_RST1R_EXTVNT5_Pos       (25U)\n#define HRTIM_RST1R_EXTVNT5_Msk       (0x1UL << HRTIM_RST1R_EXTVNT5_Pos)       /*!< 0x02000000 */\n#define HRTIM_RST1R_EXTVNT5           HRTIM_RST1R_EXTVNT5_Msk                  /*!< External event 5 */\n#define HRTIM_RST1R_EXTVNT6_Pos       (26U)\n#define HRTIM_RST1R_EXTVNT6_Msk       (0x1UL << HRTIM_RST1R_EXTVNT6_Pos)       /*!< 0x04000000 */\n#define HRTIM_RST1R_EXTVNT6           HRTIM_RST1R_EXTVNT6_Msk                  /*!< External event 6 */\n#define HRTIM_RST1R_EXTVNT7_Pos       (27U)\n#define HRTIM_RST1R_EXTVNT7_Msk       (0x1UL << HRTIM_RST1R_EXTVNT7_Pos)       /*!< 0x08000000 */\n#define HRTIM_RST1R_EXTVNT7           HRTIM_RST1R_EXTVNT7_Msk                  /*!< External event 7 */\n#define HRTIM_RST1R_EXTVNT8_Pos       (28U)\n#define HRTIM_RST1R_EXTVNT8_Msk       (0x1UL << HRTIM_RST1R_EXTVNT8_Pos)       /*!< 0x10000000 */\n#define HRTIM_RST1R_EXTVNT8           HRTIM_RST1R_EXTVNT8_Msk                  /*!< External event 8 */\n#define HRTIM_RST1R_EXTVNT9_Pos       (29U)\n#define HRTIM_RST1R_EXTVNT9_Msk       (0x1UL << HRTIM_RST1R_EXTVNT9_Pos)       /*!< 0x20000000 */\n#define HRTIM_RST1R_EXTVNT9           HRTIM_RST1R_EXTVNT9_Msk                  /*!< External event 9 */\n#define HRTIM_RST1R_EXTVNT10_Pos      (30U)\n#define HRTIM_RST1R_EXTVNT10_Msk      (0x1UL << HRTIM_RST1R_EXTVNT10_Pos)      /*!< 0x40000000 */\n#define HRTIM_RST1R_EXTVNT10          HRTIM_RST1R_EXTVNT10_Msk                 /*!< External event 10 */\n\n#define HRTIM_RST1R_UPDATE_Pos        (31U)\n#define HRTIM_RST1R_UPDATE_Msk        (0x1UL << HRTIM_RST1R_UPDATE_Pos)        /*!< 0x80000000 */\n#define HRTIM_RST1R_UPDATE            HRTIM_RST1R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */\n\n\n/**** Bit definition for Slave Output 2 set register **************************/\n#define HRTIM_SET2R_SST_Pos           (0U)\n#define HRTIM_SET2R_SST_Msk           (0x1UL << HRTIM_SET2R_SST_Pos)           /*!< 0x00000001 */\n#define HRTIM_SET2R_SST               HRTIM_SET2R_SST_Msk                      /*!< software set trigger */\n#define HRTIM_SET2R_RESYNC_Pos        (1U)\n#define HRTIM_SET2R_RESYNC_Msk        (0x1UL << HRTIM_SET2R_RESYNC_Pos)        /*!< 0x00000002 */\n#define HRTIM_SET2R_RESYNC            HRTIM_SET2R_RESYNC_Msk                   /*!< Timer A resynchronization */\n#define HRTIM_SET2R_PER_Pos           (2U)\n#define HRTIM_SET2R_PER_Msk           (0x1UL << HRTIM_SET2R_PER_Pos)           /*!< 0x00000004 */\n#define HRTIM_SET2R_PER               HRTIM_SET2R_PER_Msk                      /*!< Timer A period */\n#define HRTIM_SET2R_CMP1_Pos          (3U)\n#define HRTIM_SET2R_CMP1_Msk          (0x1UL << HRTIM_SET2R_CMP1_Pos)          /*!< 0x00000008 */\n#define HRTIM_SET2R_CMP1              HRTIM_SET2R_CMP1_Msk                     /*!< Timer A compare 1 */\n#define HRTIM_SET2R_CMP2_Pos          (4U)\n#define HRTIM_SET2R_CMP2_Msk          (0x1UL << HRTIM_SET2R_CMP2_Pos)          /*!< 0x00000010 */\n#define HRTIM_SET2R_CMP2              HRTIM_SET2R_CMP2_Msk                     /*!< Timer A compare 2 */\n#define HRTIM_SET2R_CMP3_Pos          (5U)\n#define HRTIM_SET2R_CMP3_Msk          (0x1UL << HRTIM_SET2R_CMP3_Pos)          /*!< 0x00000020 */\n#define HRTIM_SET2R_CMP3              HRTIM_SET2R_CMP3_Msk                     /*!< Timer A compare 3 */\n#define HRTIM_SET2R_CMP4_Pos          (6U)\n#define HRTIM_SET2R_CMP4_Msk          (0x1UL << HRTIM_SET2R_CMP4_Pos)          /*!< 0x00000040 */\n#define HRTIM_SET2R_CMP4              HRTIM_SET2R_CMP4_Msk                     /*!< Timer A compare 4 */\n\n#define HRTIM_SET2R_MSTPER_Pos        (7U)\n#define HRTIM_SET2R_MSTPER_Msk        (0x1UL << HRTIM_SET2R_MSTPER_Pos)        /*!< 0x00000080 */\n#define HRTIM_SET2R_MSTPER            HRTIM_SET2R_MSTPER_Msk                   /*!< Master period */\n#define HRTIM_SET2R_MSTCMP1_Pos       (8U)\n#define HRTIM_SET2R_MSTCMP1_Msk       (0x1UL << HRTIM_SET2R_MSTCMP1_Pos)       /*!< 0x00000100 */\n#define HRTIM_SET2R_MSTCMP1           HRTIM_SET2R_MSTCMP1_Msk                  /*!< Master compare 1 */\n#define HRTIM_SET2R_MSTCMP2_Pos       (9U)\n#define HRTIM_SET2R_MSTCMP2_Msk       (0x1UL << HRTIM_SET2R_MSTCMP2_Pos)       /*!< 0x00000200 */\n#define HRTIM_SET2R_MSTCMP2           HRTIM_SET2R_MSTCMP2_Msk                  /*!< Master compare 2 */\n#define HRTIM_SET2R_MSTCMP3_Pos       (10U)\n#define HRTIM_SET2R_MSTCMP3_Msk       (0x1UL << HRTIM_SET2R_MSTCMP3_Pos)       /*!< 0x00000400 */\n#define HRTIM_SET2R_MSTCMP3           HRTIM_SET2R_MSTCMP3_Msk                  /*!< Master compare 3 */\n#define HRTIM_SET2R_MSTCMP4_Pos       (11U)\n#define HRTIM_SET2R_MSTCMP4_Msk       (0x1UL << HRTIM_SET2R_MSTCMP4_Pos)       /*!< 0x00000800 */\n#define HRTIM_SET2R_MSTCMP4           HRTIM_SET2R_MSTCMP4_Msk                  /*!< Master compare 4 */\n\n#define HRTIM_SET2R_TIMEVNT1_Pos      (12U)\n#define HRTIM_SET2R_TIMEVNT1_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT1_Pos)      /*!< 0x00001000 */\n#define HRTIM_SET2R_TIMEVNT1          HRTIM_SET2R_TIMEVNT1_Msk                 /*!< Timer event 1 */\n#define HRTIM_SET2R_TIMEVNT2_Pos      (13U)\n#define HRTIM_SET2R_TIMEVNT2_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT2_Pos)      /*!< 0x00002000 */\n#define HRTIM_SET2R_TIMEVNT2          HRTIM_SET2R_TIMEVNT2_Msk                 /*!< Timer event 2 */\n#define HRTIM_SET2R_TIMEVNT3_Pos      (14U)\n#define HRTIM_SET2R_TIMEVNT3_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT3_Pos)      /*!< 0x00004000 */\n#define HRTIM_SET2R_TIMEVNT3          HRTIM_SET2R_TIMEVNT3_Msk                 /*!< Timer event 3 */\n#define HRTIM_SET2R_TIMEVNT4_Pos      (15U)\n#define HRTIM_SET2R_TIMEVNT4_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT4_Pos)      /*!< 0x00008000 */\n#define HRTIM_SET2R_TIMEVNT4          HRTIM_SET2R_TIMEVNT4_Msk                 /*!< Timer event 4 */\n#define HRTIM_SET2R_TIMEVNT5_Pos      (16U)\n#define HRTIM_SET2R_TIMEVNT5_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT5_Pos)      /*!< 0x00010000 */\n#define HRTIM_SET2R_TIMEVNT5          HRTIM_SET2R_TIMEVNT5_Msk                 /*!< Timer event 5 */\n#define HRTIM_SET2R_TIMEVNT6_Pos      (17U)\n#define HRTIM_SET2R_TIMEVNT6_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT6_Pos)      /*!< 0x00020000 */\n#define HRTIM_SET2R_TIMEVNT6          HRTIM_SET2R_TIMEVNT6_Msk                 /*!< Timer event 6 */\n#define HRTIM_SET2R_TIMEVNT7_Pos      (18U)\n#define HRTIM_SET2R_TIMEVNT7_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT7_Pos)      /*!< 0x00040000 */\n#define HRTIM_SET2R_TIMEVNT7          HRTIM_SET2R_TIMEVNT7_Msk                 /*!< Timer event 7 */\n#define HRTIM_SET2R_TIMEVNT8_Pos      (19U)\n#define HRTIM_SET2R_TIMEVNT8_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT8_Pos)      /*!< 0x00080000 */\n#define HRTIM_SET2R_TIMEVNT8          HRTIM_SET2R_TIMEVNT8_Msk                 /*!< Timer event 8 */\n#define HRTIM_SET2R_TIMEVNT9_Pos      (20U)\n#define HRTIM_SET2R_TIMEVNT9_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT9_Pos)      /*!< 0x00100000 */\n#define HRTIM_SET2R_TIMEVNT9          HRTIM_SET2R_TIMEVNT9_Msk                 /*!< Timer event 9 */\n\n#define HRTIM_SET2R_EXTVNT1_Pos       (21U)\n#define HRTIM_SET2R_EXTVNT1_Msk       (0x1UL << HRTIM_SET2R_EXTVNT1_Pos)       /*!< 0x00200000 */\n#define HRTIM_SET2R_EXTVNT1           HRTIM_SET2R_EXTVNT1_Msk                  /*!< External event 1 */\n#define HRTIM_SET2R_EXTVNT2_Pos       (22U)\n#define HRTIM_SET2R_EXTVNT2_Msk       (0x1UL << HRTIM_SET2R_EXTVNT2_Pos)       /*!< 0x00400000 */\n#define HRTIM_SET2R_EXTVNT2           HRTIM_SET2R_EXTVNT2_Msk                  /*!< External event 2 */\n#define HRTIM_SET2R_EXTVNT3_Pos       (23U)\n#define HRTIM_SET2R_EXTVNT3_Msk       (0x1UL << HRTIM_SET2R_EXTVNT3_Pos)       /*!< 0x00800000 */\n#define HRTIM_SET2R_EXTVNT3           HRTIM_SET2R_EXTVNT3_Msk                  /*!< External event 3 */\n#define HRTIM_SET2R_EXTVNT4_Pos       (24U)\n#define HRTIM_SET2R_EXTVNT4_Msk       (0x1UL << HRTIM_SET2R_EXTVNT4_Pos)       /*!< 0x01000000 */\n#define HRTIM_SET2R_EXTVNT4           HRTIM_SET2R_EXTVNT4_Msk                  /*!< External event 4 */\n#define HRTIM_SET2R_EXTVNT5_Pos       (25U)\n#define HRTIM_SET2R_EXTVNT5_Msk       (0x1UL << HRTIM_SET2R_EXTVNT5_Pos)       /*!< 0x02000000 */\n#define HRTIM_SET2R_EXTVNT5           HRTIM_SET2R_EXTVNT5_Msk                  /*!< External event 5 */\n#define HRTIM_SET2R_EXTVNT6_Pos       (26U)\n#define HRTIM_SET2R_EXTVNT6_Msk       (0x1UL << HRTIM_SET2R_EXTVNT6_Pos)       /*!< 0x04000000 */\n#define HRTIM_SET2R_EXTVNT6           HRTIM_SET2R_EXTVNT6_Msk                  /*!< External event 6 */\n#define HRTIM_SET2R_EXTVNT7_Pos       (27U)\n#define HRTIM_SET2R_EXTVNT7_Msk       (0x1UL << HRTIM_SET2R_EXTVNT7_Pos)       /*!< 0x08000000 */\n#define HRTIM_SET2R_EXTVNT7           HRTIM_SET2R_EXTVNT7_Msk                  /*!< External event 7 */\n#define HRTIM_SET2R_EXTVNT8_Pos       (28U)\n#define HRTIM_SET2R_EXTVNT8_Msk       (0x1UL << HRTIM_SET2R_EXTVNT8_Pos)       /*!< 0x10000000 */\n#define HRTIM_SET2R_EXTVNT8           HRTIM_SET2R_EXTVNT8_Msk                  /*!< External event 8 */\n#define HRTIM_SET2R_EXTVNT9_Pos       (29U)\n#define HRTIM_SET2R_EXTVNT9_Msk       (0x1UL << HRTIM_SET2R_EXTVNT9_Pos)       /*!< 0x20000000 */\n#define HRTIM_SET2R_EXTVNT9           HRTIM_SET2R_EXTVNT9_Msk                  /*!< External event 9 */\n#define HRTIM_SET2R_EXTVNT10_Pos      (30U)\n#define HRTIM_SET2R_EXTVNT10_Msk      (0x1UL << HRTIM_SET2R_EXTVNT10_Pos)      /*!< 0x40000000 */\n#define HRTIM_SET2R_EXTVNT10          HRTIM_SET2R_EXTVNT10_Msk                 /*!< External event 10 */\n\n#define HRTIM_SET2R_UPDATE_Pos        (31U)\n#define HRTIM_SET2R_UPDATE_Msk        (0x1UL << HRTIM_SET2R_UPDATE_Pos)        /*!< 0x80000000 */\n#define HRTIM_SET2R_UPDATE            HRTIM_SET2R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */\n\n/**** Bit definition for Slave Output 2 reset register ************************/\n#define HRTIM_RST2R_SRT_Pos           (0U)\n#define HRTIM_RST2R_SRT_Msk           (0x1UL << HRTIM_RST2R_SRT_Pos)           /*!< 0x00000001 */\n#define HRTIM_RST2R_SRT               HRTIM_RST2R_SRT_Msk                      /*!< software reset trigger */\n#define HRTIM_RST2R_RESYNC_Pos        (1U)\n#define HRTIM_RST2R_RESYNC_Msk        (0x1UL << HRTIM_RST2R_RESYNC_Pos)        /*!< 0x00000002 */\n#define HRTIM_RST2R_RESYNC            HRTIM_RST2R_RESYNC_Msk                   /*!< Timer A resynchronization */\n#define HRTIM_RST2R_PER_Pos           (2U)\n#define HRTIM_RST2R_PER_Msk           (0x1UL << HRTIM_RST2R_PER_Pos)           /*!< 0x00000004 */\n#define HRTIM_RST2R_PER               HRTIM_RST2R_PER_Msk                      /*!< Timer A period */\n#define HRTIM_RST2R_CMP1_Pos          (3U)\n#define HRTIM_RST2R_CMP1_Msk          (0x1UL << HRTIM_RST2R_CMP1_Pos)          /*!< 0x00000008 */\n#define HRTIM_RST2R_CMP1              HRTIM_RST2R_CMP1_Msk                     /*!< Timer A compare 1 */\n#define HRTIM_RST2R_CMP2_Pos          (4U)\n#define HRTIM_RST2R_CMP2_Msk          (0x1UL << HRTIM_RST2R_CMP2_Pos)          /*!< 0x00000010 */\n#define HRTIM_RST2R_CMP2              HRTIM_RST2R_CMP2_Msk                     /*!< Timer A compare 2 */\n#define HRTIM_RST2R_CMP3_Pos          (5U)\n#define HRTIM_RST2R_CMP3_Msk          (0x1UL << HRTIM_RST2R_CMP3_Pos)          /*!< 0x00000020 */\n#define HRTIM_RST2R_CMP3              HRTIM_RST2R_CMP3_Msk                     /*!< Timer A compare 3 */\n#define HRTIM_RST2R_CMP4_Pos          (6U)\n#define HRTIM_RST2R_CMP4_Msk          (0x1UL << HRTIM_RST2R_CMP4_Pos)          /*!< 0x00000040 */\n#define HRTIM_RST2R_CMP4              HRTIM_RST2R_CMP4_Msk                     /*!< Timer A compare 4 */\n\n#define HRTIM_RST2R_MSTPER_Pos        (7U)\n#define HRTIM_RST2R_MSTPER_Msk        (0x1UL << HRTIM_RST2R_MSTPER_Pos)        /*!< 0x00000080 */\n#define HRTIM_RST2R_MSTPER            HRTIM_RST2R_MSTPER_Msk                   /*!< Master period */\n#define HRTIM_RST2R_MSTCMP1_Pos       (8U)\n#define HRTIM_RST2R_MSTCMP1_Msk       (0x1UL << HRTIM_RST2R_MSTCMP1_Pos)       /*!< 0x00000100 */\n#define HRTIM_RST2R_MSTCMP1           HRTIM_RST2R_MSTCMP1_Msk                  /*!< Master compare 1 */\n#define HRTIM_RST2R_MSTCMP2_Pos       (9U)\n#define HRTIM_RST2R_MSTCMP2_Msk       (0x1UL << HRTIM_RST2R_MSTCMP2_Pos)       /*!< 0x00000200 */\n#define HRTIM_RST2R_MSTCMP2           HRTIM_RST2R_MSTCMP2_Msk                  /*!< Master compare 2 */\n#define HRTIM_RST2R_MSTCMP3_Pos       (10U)\n#define HRTIM_RST2R_MSTCMP3_Msk       (0x1UL << HRTIM_RST2R_MSTCMP3_Pos)       /*!< 0x00000400 */\n#define HRTIM_RST2R_MSTCMP3           HRTIM_RST2R_MSTCMP3_Msk                  /*!< Master compare 3 */\n#define HRTIM_RST2R_MSTCMP4_Pos       (11U)\n#define HRTIM_RST2R_MSTCMP4_Msk       (0x1UL << HRTIM_RST2R_MSTCMP4_Pos)       /*!< 0x00000800 */\n#define HRTIM_RST2R_MSTCMP4           HRTIM_RST2R_MSTCMP4_Msk                  /*!< Master compare 4 */\n\n#define HRTIM_RST2R_TIMEVNT1_Pos      (12U)\n#define HRTIM_RST2R_TIMEVNT1_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT1_Pos)      /*!< 0x00001000 */\n#define HRTIM_RST2R_TIMEVNT1          HRTIM_RST2R_TIMEVNT1_Msk                 /*!< Timer event 1 */\n#define HRTIM_RST2R_TIMEVNT2_Pos      (13U)\n#define HRTIM_RST2R_TIMEVNT2_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT2_Pos)      /*!< 0x00002000 */\n#define HRTIM_RST2R_TIMEVNT2          HRTIM_RST2R_TIMEVNT2_Msk                 /*!< Timer event 2 */\n#define HRTIM_RST2R_TIMEVNT3_Pos      (14U)\n#define HRTIM_RST2R_TIMEVNT3_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT3_Pos)      /*!< 0x00004000 */\n#define HRTIM_RST2R_TIMEVNT3          HRTIM_RST2R_TIMEVNT3_Msk                 /*!< Timer event 3 */\n#define HRTIM_RST2R_TIMEVNT4_Pos      (15U)\n#define HRTIM_RST2R_TIMEVNT4_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT4_Pos)      /*!< 0x00008000 */\n#define HRTIM_RST2R_TIMEVNT4          HRTIM_RST2R_TIMEVNT4_Msk                 /*!< Timer event 4 */\n#define HRTIM_RST2R_TIMEVNT5_Pos      (16U)\n#define HRTIM_RST2R_TIMEVNT5_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT5_Pos)      /*!< 0x00010000 */\n#define HRTIM_RST2R_TIMEVNT5          HRTIM_RST2R_TIMEVNT5_Msk                 /*!< Timer event 5 */\n#define HRTIM_RST2R_TIMEVNT6_Pos      (17U)\n#define HRTIM_RST2R_TIMEVNT6_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT6_Pos)      /*!< 0x00020000 */\n#define HRTIM_RST2R_TIMEVNT6          HRTIM_RST2R_TIMEVNT6_Msk                 /*!< Timer event 6 */\n#define HRTIM_RST2R_TIMEVNT7_Pos      (18U)\n#define HRTIM_RST2R_TIMEVNT7_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT7_Pos)      /*!< 0x00040000 */\n#define HRTIM_RST2R_TIMEVNT7          HRTIM_RST2R_TIMEVNT7_Msk                 /*!< Timer event 7 */\n#define HRTIM_RST2R_TIMEVNT8_Pos      (19U)\n#define HRTIM_RST2R_TIMEVNT8_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT8_Pos)      /*!< 0x00080000 */\n#define HRTIM_RST2R_TIMEVNT8          HRTIM_RST2R_TIMEVNT8_Msk                 /*!< Timer event 8 */\n#define HRTIM_RST2R_TIMEVNT9_Pos      (20U)\n#define HRTIM_RST2R_TIMEVNT9_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT9_Pos)      /*!< 0x00100000 */\n#define HRTIM_RST2R_TIMEVNT9          HRTIM_RST2R_TIMEVNT9_Msk                 /*!< Timer event 9 */\n\n#define HRTIM_RST2R_EXTVNT1_Pos       (21U)\n#define HRTIM_RST2R_EXTVNT1_Msk       (0x1UL << HRTIM_RST2R_EXTVNT1_Pos)       /*!< 0x00200000 */\n#define HRTIM_RST2R_EXTVNT1           HRTIM_RST2R_EXTVNT1_Msk                  /*!< External event 1 */\n#define HRTIM_RST2R_EXTVNT2_Pos       (22U)\n#define HRTIM_RST2R_EXTVNT2_Msk       (0x1UL << HRTIM_RST2R_EXTVNT2_Pos)       /*!< 0x00400000 */\n#define HRTIM_RST2R_EXTVNT2           HRTIM_RST2R_EXTVNT2_Msk                  /*!< External event 2 */\n#define HRTIM_RST2R_EXTVNT3_Pos       (23U)\n#define HRTIM_RST2R_EXTVNT3_Msk       (0x1UL << HRTIM_RST2R_EXTVNT3_Pos)       /*!< 0x00800000 */\n#define HRTIM_RST2R_EXTVNT3           HRTIM_RST2R_EXTVNT3_Msk                  /*!< External event 3 */\n#define HRTIM_RST2R_EXTVNT4_Pos       (24U)\n#define HRTIM_RST2R_EXTVNT4_Msk       (0x1UL << HRTIM_RST2R_EXTVNT4_Pos)       /*!< 0x01000000 */\n#define HRTIM_RST2R_EXTVNT4           HRTIM_RST2R_EXTVNT4_Msk                  /*!< External event 4 */\n#define HRTIM_RST2R_EXTVNT5_Pos       (25U)\n#define HRTIM_RST2R_EXTVNT5_Msk       (0x1UL << HRTIM_RST2R_EXTVNT5_Pos)       /*!< 0x02000000 */\n#define HRTIM_RST2R_EXTVNT5           HRTIM_RST2R_EXTVNT5_Msk                  /*!< External event 5 */\n#define HRTIM_RST2R_EXTVNT6_Pos       (26U)\n#define HRTIM_RST2R_EXTVNT6_Msk       (0x1UL << HRTIM_RST2R_EXTVNT6_Pos)       /*!< 0x04000000 */\n#define HRTIM_RST2R_EXTVNT6           HRTIM_RST2R_EXTVNT6_Msk                  /*!< External event 6 */\n#define HRTIM_RST2R_EXTVNT7_Pos       (27U)\n#define HRTIM_RST2R_EXTVNT7_Msk       (0x1UL << HRTIM_RST2R_EXTVNT7_Pos)       /*!< 0x08000000 */\n#define HRTIM_RST2R_EXTVNT7           HRTIM_RST2R_EXTVNT7_Msk                  /*!< External event 7 */\n#define HRTIM_RST2R_EXTVNT8_Pos       (28U)\n#define HRTIM_RST2R_EXTVNT8_Msk       (0x1UL << HRTIM_RST2R_EXTVNT8_Pos)       /*!< 0x10000000 */\n#define HRTIM_RST2R_EXTVNT8           HRTIM_RST2R_EXTVNT8_Msk                  /*!< External event 8 */\n#define HRTIM_RST2R_EXTVNT9_Pos       (29U)\n#define HRTIM_RST2R_EXTVNT9_Msk       (0x1UL << HRTIM_RST2R_EXTVNT9_Pos)       /*!< 0x20000000 */\n#define HRTIM_RST2R_EXTVNT9           HRTIM_RST2R_EXTVNT9_Msk                  /*!< External event 9 */\n#define HRTIM_RST2R_EXTVNT10_Pos      (30U)\n#define HRTIM_RST2R_EXTVNT10_Msk      (0x1UL << HRTIM_RST2R_EXTVNT10_Pos)      /*!< 0x40000000 */\n#define HRTIM_RST2R_EXTVNT10          HRTIM_RST2R_EXTVNT10_Msk                 /*!< External event 10 */\n\n#define HRTIM_RST2R_UPDATE_Pos        (31U)\n#define HRTIM_RST2R_UPDATE_Msk        (0x1UL << HRTIM_RST2R_UPDATE_Pos)        /*!< 0x80000000 */\n#define HRTIM_RST2R_UPDATE            HRTIM_RST2R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */\n\n/**** Bit definition for Slave external event filtering  register 1 ***********/\n#define HRTIM_EEFR1_EE1LTCH_Pos       (0U)\n#define HRTIM_EEFR1_EE1LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE1LTCH_Pos)       /*!< 0x00000001 */\n#define HRTIM_EEFR1_EE1LTCH           HRTIM_EEFR1_EE1LTCH_Msk                  /*!< External Event 1 latch */\n#define HRTIM_EEFR1_EE1FLTR_Pos       (1U)\n#define HRTIM_EEFR1_EE1FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE1FLTR_Pos)       /*!< 0x0000001E */\n#define HRTIM_EEFR1_EE1FLTR           HRTIM_EEFR1_EE1FLTR_Msk                  /*!< External Event 1 filter mask */\n#define HRTIM_EEFR1_EE1FLTR_0         (0x1UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000002 */\n#define HRTIM_EEFR1_EE1FLTR_1         (0x2UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000004 */\n#define HRTIM_EEFR1_EE1FLTR_2         (0x4UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000008 */\n#define HRTIM_EEFR1_EE1FLTR_3         (0x8UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000010 */\n\n#define HRTIM_EEFR1_EE2LTCH_Pos       (6U)\n#define HRTIM_EEFR1_EE2LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE2LTCH_Pos)       /*!< 0x00000040 */\n#define HRTIM_EEFR1_EE2LTCH           HRTIM_EEFR1_EE2LTCH_Msk                  /*!< External Event 2 latch */\n#define HRTIM_EEFR1_EE2FLTR_Pos       (7U)\n#define HRTIM_EEFR1_EE2FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE2FLTR_Pos)       /*!< 0x00000780 */\n#define HRTIM_EEFR1_EE2FLTR           HRTIM_EEFR1_EE2FLTR_Msk                  /*!< External Event 2 filter mask */\n#define HRTIM_EEFR1_EE2FLTR_0         (0x1UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000080 */\n#define HRTIM_EEFR1_EE2FLTR_1         (0x2UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000100 */\n#define HRTIM_EEFR1_EE2FLTR_2         (0x4UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000200 */\n#define HRTIM_EEFR1_EE2FLTR_3         (0x8UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000400 */\n\n#define HRTIM_EEFR1_EE3LTCH_Pos       (12U)\n#define HRTIM_EEFR1_EE3LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE3LTCH_Pos)       /*!< 0x00001000 */\n#define HRTIM_EEFR1_EE3LTCH           HRTIM_EEFR1_EE3LTCH_Msk                  /*!< External Event 3 latch */\n#define HRTIM_EEFR1_EE3FLTR_Pos       (13U)\n#define HRTIM_EEFR1_EE3FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE3FLTR_Pos)       /*!< 0x0001E000 */\n#define HRTIM_EEFR1_EE3FLTR           HRTIM_EEFR1_EE3FLTR_Msk                  /*!< External Event 3 filter mask */\n#define HRTIM_EEFR1_EE3FLTR_0         (0x1UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00002000 */\n#define HRTIM_EEFR1_EE3FLTR_1         (0x2UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00004000 */\n#define HRTIM_EEFR1_EE3FLTR_2         (0x4UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00008000 */\n#define HRTIM_EEFR1_EE3FLTR_3         (0x8UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00010000 */\n\n#define HRTIM_EEFR1_EE4LTCH_Pos       (18U)\n#define HRTIM_EEFR1_EE4LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE4LTCH_Pos)       /*!< 0x00040000 */\n#define HRTIM_EEFR1_EE4LTCH           HRTIM_EEFR1_EE4LTCH_Msk                  /*!< External Event 4 latch */\n#define HRTIM_EEFR1_EE4FLTR_Pos       (19U)\n#define HRTIM_EEFR1_EE4FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE4FLTR_Pos)       /*!< 0x00780000 */\n#define HRTIM_EEFR1_EE4FLTR           HRTIM_EEFR1_EE4FLTR_Msk                  /*!< External Event 4 filter mask */\n#define HRTIM_EEFR1_EE4FLTR_0         (0x1UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00080000 */\n#define HRTIM_EEFR1_EE4FLTR_1         (0x2UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00100000 */\n#define HRTIM_EEFR1_EE4FLTR_2         (0x4UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00200000 */\n#define HRTIM_EEFR1_EE4FLTR_3         (0x8UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00400000 */\n\n#define HRTIM_EEFR1_EE5LTCH_Pos       (24U)\n#define HRTIM_EEFR1_EE5LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE5LTCH_Pos)       /*!< 0x01000000 */\n#define HRTIM_EEFR1_EE5LTCH           HRTIM_EEFR1_EE5LTCH_Msk                  /*!< External Event 5 latch */\n#define HRTIM_EEFR1_EE5FLTR_Pos       (25U)\n#define HRTIM_EEFR1_EE5FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE5FLTR_Pos)       /*!< 0x1E000000 */\n#define HRTIM_EEFR1_EE5FLTR           HRTIM_EEFR1_EE5FLTR_Msk                  /*!< External Event 5 filter mask */\n#define HRTIM_EEFR1_EE5FLTR_0         (0x1UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x02000000 */\n#define HRTIM_EEFR1_EE5FLTR_1         (0x2UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x04000000 */\n#define HRTIM_EEFR1_EE5FLTR_2         (0x4UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x08000000 */\n#define HRTIM_EEFR1_EE5FLTR_3         (0x8UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x10000000 */\n\n/**** Bit definition for Slave external event filtering  register 2 ***********/\n#define HRTIM_EEFR2_EE6LTCH_Pos       (0U)\n#define HRTIM_EEFR2_EE6LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE6LTCH_Pos)       /*!< 0x00000001 */\n#define HRTIM_EEFR2_EE6LTCH           HRTIM_EEFR2_EE6LTCH_Msk                  /*!< External Event 6 latch */\n#define HRTIM_EEFR2_EE6FLTR_Pos       (1U)\n#define HRTIM_EEFR2_EE6FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE6FLTR_Pos)       /*!< 0x0000001E */\n#define HRTIM_EEFR2_EE6FLTR           HRTIM_EEFR2_EE6FLTR_Msk                  /*!< External Event 6 filter mask */\n#define HRTIM_EEFR2_EE6FLTR_0         (0x1UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000002 */\n#define HRTIM_EEFR2_EE6FLTR_1         (0x2UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000004 */\n#define HRTIM_EEFR2_EE6FLTR_2         (0x4UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000008 */\n#define HRTIM_EEFR2_EE6FLTR_3         (0x8UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000010 */\n\n#define HRTIM_EEFR2_EE7LTCH_Pos       (6U)\n#define HRTIM_EEFR2_EE7LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE7LTCH_Pos)       /*!< 0x00000040 */\n#define HRTIM_EEFR2_EE7LTCH           HRTIM_EEFR2_EE7LTCH_Msk                  /*!< External Event 7 latch */\n#define HRTIM_EEFR2_EE7FLTR_Pos       (7U)\n#define HRTIM_EEFR2_EE7FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE7FLTR_Pos)       /*!< 0x00000780 */\n#define HRTIM_EEFR2_EE7FLTR           HRTIM_EEFR2_EE7FLTR_Msk                  /*!< External Event 7 filter mask */\n#define HRTIM_EEFR2_EE7FLTR_0         (0x1UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000080 */\n#define HRTIM_EEFR2_EE7FLTR_1         (0x2UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000100 */\n#define HRTIM_EEFR2_EE7FLTR_2         (0x4UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000200 */\n#define HRTIM_EEFR2_EE7FLTR_3         (0x8UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000400 */\n\n#define HRTIM_EEFR2_EE8LTCH_Pos       (12U)\n#define HRTIM_EEFR2_EE8LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE8LTCH_Pos)       /*!< 0x00001000 */\n#define HRTIM_EEFR2_EE8LTCH           HRTIM_EEFR2_EE8LTCH_Msk                  /*!< External Event 8 latch */\n#define HRTIM_EEFR2_EE8FLTR_Pos       (13U)\n#define HRTIM_EEFR2_EE8FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE8FLTR_Pos)       /*!< 0x0001E000 */\n#define HRTIM_EEFR2_EE8FLTR           HRTIM_EEFR2_EE8FLTR_Msk                  /*!< External Event 8 filter mask */\n#define HRTIM_EEFR2_EE8FLTR_0         (0x1UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00002000 */\n#define HRTIM_EEFR2_EE8FLTR_1         (0x2UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00004000 */\n#define HRTIM_EEFR2_EE8FLTR_2         (0x4UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00008000 */\n#define HRTIM_EEFR2_EE8FLTR_3         (0x8UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00010000 */\n\n#define HRTIM_EEFR2_EE9LTCH_Pos       (18U)\n#define HRTIM_EEFR2_EE9LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE9LTCH_Pos)       /*!< 0x00040000 */\n#define HRTIM_EEFR2_EE9LTCH           HRTIM_EEFR2_EE9LTCH_Msk                  /*!< External Event 9 latch */\n#define HRTIM_EEFR2_EE9FLTR_Pos       (19U)\n#define HRTIM_EEFR2_EE9FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE9FLTR_Pos)       /*!< 0x00780000 */\n#define HRTIM_EEFR2_EE9FLTR           HRTIM_EEFR2_EE9FLTR_Msk                  /*!< External Event 9 filter mask */\n#define HRTIM_EEFR2_EE9FLTR_0         (0x1UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00080000 */\n#define HRTIM_EEFR2_EE9FLTR_1         (0x2UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00100000 */\n#define HRTIM_EEFR2_EE9FLTR_2         (0x4UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00200000 */\n#define HRTIM_EEFR2_EE9FLTR_3         (0x8UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00400000 */\n\n#define HRTIM_EEFR2_EE10LTCH_Pos      (24U)\n#define HRTIM_EEFR2_EE10LTCH_Msk      (0x1UL << HRTIM_EEFR2_EE10LTCH_Pos)      /*!< 0x01000000 */\n#define HRTIM_EEFR2_EE10LTCH          HRTIM_EEFR2_EE10LTCH_Msk                 /*!< External Event 10 latch */\n#define HRTIM_EEFR2_EE10FLTR_Pos      (25U)\n#define HRTIM_EEFR2_EE10FLTR_Msk      (0xFUL << HRTIM_EEFR2_EE10FLTR_Pos)      /*!< 0x1E000000 */\n#define HRTIM_EEFR2_EE10FLTR          HRTIM_EEFR2_EE10FLTR_Msk                 /*!< External Event 10 filter mask */\n#define HRTIM_EEFR2_EE10FLTR_0        (0x1UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x02000000 */\n#define HRTIM_EEFR2_EE10FLTR_1        (0x2UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x04000000 */\n#define HRTIM_EEFR2_EE10FLTR_2        (0x4UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x08000000 */\n#define HRTIM_EEFR2_EE10FLTR_3        (0x8UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x10000000 */\n\n/**** Bit definition for Slave Timer reset register ***************************/\n#define HRTIM_RSTR_UPDATE_Pos         (1U)\n#define HRTIM_RSTR_UPDATE_Msk         (0x1UL << HRTIM_RSTR_UPDATE_Pos)         /*!< 0x00000002 */\n#define HRTIM_RSTR_UPDATE             HRTIM_RSTR_UPDATE_Msk                    /*!< Timer update */\n#define HRTIM_RSTR_CMP2_Pos           (2U)\n#define HRTIM_RSTR_CMP2_Msk           (0x1UL << HRTIM_RSTR_CMP2_Pos)           /*!< 0x00000004 */\n#define HRTIM_RSTR_CMP2               HRTIM_RSTR_CMP2_Msk                      /*!< Timer compare2 */\n#define HRTIM_RSTR_CMP4_Pos           (3U)\n#define HRTIM_RSTR_CMP4_Msk           (0x1UL << HRTIM_RSTR_CMP4_Pos)           /*!< 0x00000008 */\n#define HRTIM_RSTR_CMP4               HRTIM_RSTR_CMP4_Msk                      /*!< Timer compare4 */\n\n#define HRTIM_RSTR_MSTPER_Pos         (4U)\n#define HRTIM_RSTR_MSTPER_Msk         (0x1UL << HRTIM_RSTR_MSTPER_Pos)         /*!< 0x00000010 */\n#define HRTIM_RSTR_MSTPER             HRTIM_RSTR_MSTPER_Msk                    /*!< Master period */\n#define HRTIM_RSTR_MSTCMP1_Pos        (5U)\n#define HRTIM_RSTR_MSTCMP1_Msk        (0x1UL << HRTIM_RSTR_MSTCMP1_Pos)        /*!< 0x00000020 */\n#define HRTIM_RSTR_MSTCMP1            HRTIM_RSTR_MSTCMP1_Msk                   /*!< Master compare1 */\n#define HRTIM_RSTR_MSTCMP2_Pos        (6U)\n#define HRTIM_RSTR_MSTCMP2_Msk        (0x1UL << HRTIM_RSTR_MSTCMP2_Pos)        /*!< 0x00000040 */\n#define HRTIM_RSTR_MSTCMP2            HRTIM_RSTR_MSTCMP2_Msk                   /*!< Master compare2 */\n#define HRTIM_RSTR_MSTCMP3_Pos        (7U)\n#define HRTIM_RSTR_MSTCMP3_Msk        (0x1UL << HRTIM_RSTR_MSTCMP3_Pos)        /*!< 0x00000080 */\n#define HRTIM_RSTR_MSTCMP3            HRTIM_RSTR_MSTCMP3_Msk                   /*!< Master compare3 */\n#define HRTIM_RSTR_MSTCMP4_Pos        (8U)\n#define HRTIM_RSTR_MSTCMP4_Msk        (0x1UL << HRTIM_RSTR_MSTCMP4_Pos)        /*!< 0x00000100 */\n#define HRTIM_RSTR_MSTCMP4            HRTIM_RSTR_MSTCMP4_Msk                   /*!< Master compare4 */\n\n#define HRTIM_RSTR_EXTEVNT1_Pos       (9U)\n#define HRTIM_RSTR_EXTEVNT1_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT1_Pos)       /*!< 0x00000200 */\n#define HRTIM_RSTR_EXTEVNT1           HRTIM_RSTR_EXTEVNT1_Msk                  /*!< External event 1 */\n#define HRTIM_RSTR_EXTEVNT2_Pos       (10U)\n#define HRTIM_RSTR_EXTEVNT2_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT2_Pos)       /*!< 0x00000400 */\n#define HRTIM_RSTR_EXTEVNT2           HRTIM_RSTR_EXTEVNT2_Msk                  /*!< External event 2 */\n#define HRTIM_RSTR_EXTEVNT3_Pos       (11U)\n#define HRTIM_RSTR_EXTEVNT3_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT3_Pos)       /*!< 0x00000800 */\n#define HRTIM_RSTR_EXTEVNT3           HRTIM_RSTR_EXTEVNT3_Msk                  /*!< External event 3 */\n#define HRTIM_RSTR_EXTEVNT4_Pos       (12U)\n#define HRTIM_RSTR_EXTEVNT4_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT4_Pos)       /*!< 0x00001000 */\n#define HRTIM_RSTR_EXTEVNT4           HRTIM_RSTR_EXTEVNT4_Msk                  /*!< External event 4 */\n#define HRTIM_RSTR_EXTEVNT5_Pos       (13U)\n#define HRTIM_RSTR_EXTEVNT5_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT5_Pos)       /*!< 0x00002000 */\n#define HRTIM_RSTR_EXTEVNT5           HRTIM_RSTR_EXTEVNT5_Msk                  /*!< External event 5 */\n#define HRTIM_RSTR_EXTEVNT6_Pos       (14U)\n#define HRTIM_RSTR_EXTEVNT6_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT6_Pos)       /*!< 0x00004000 */\n#define HRTIM_RSTR_EXTEVNT6           HRTIM_RSTR_EXTEVNT6_Msk                  /*!< External event 6 */\n#define HRTIM_RSTR_EXTEVNT7_Pos       (15U)\n#define HRTIM_RSTR_EXTEVNT7_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT7_Pos)       /*!< 0x00008000 */\n#define HRTIM_RSTR_EXTEVNT7           HRTIM_RSTR_EXTEVNT7_Msk                  /*!< External event 7 */\n#define HRTIM_RSTR_EXTEVNT8_Pos       (16U)\n#define HRTIM_RSTR_EXTEVNT8_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT8_Pos)       /*!< 0x00010000 */\n#define HRTIM_RSTR_EXTEVNT8           HRTIM_RSTR_EXTEVNT8_Msk                  /*!< External event 8 */\n#define HRTIM_RSTR_EXTEVNT9_Pos       (17U)\n#define HRTIM_RSTR_EXTEVNT9_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT9_Pos)       /*!< 0x00020000 */\n#define HRTIM_RSTR_EXTEVNT9           HRTIM_RSTR_EXTEVNT9_Msk                  /*!< External event 9 */\n#define HRTIM_RSTR_EXTEVNT10_Pos      (18U)\n#define HRTIM_RSTR_EXTEVNT10_Msk      (0x1UL << HRTIM_RSTR_EXTEVNT10_Pos)      /*!< 0x00040000 */\n#define HRTIM_RSTR_EXTEVNT10          HRTIM_RSTR_EXTEVNT10_Msk                 /*!< External event 10 */\n\n/* Slave Timer A reset enable bits upon other slave timers events */\n#define HRTIM_RSTR_TIMBCMP1_Pos       (19U)\n#define HRTIM_RSTR_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMBCMP1_Pos)       /*!< 0x00080000 */\n#define HRTIM_RSTR_TIMBCMP1           HRTIM_RSTR_TIMBCMP1_Msk                  /*!< Timer B compare 1 */\n#define HRTIM_RSTR_TIMBCMP2_Pos       (20U)\n#define HRTIM_RSTR_TIMBCMP2_Msk       (0x1UL << HRTIM_RSTR_TIMBCMP2_Pos)       /*!< 0x00100000 */\n#define HRTIM_RSTR_TIMBCMP2           HRTIM_RSTR_TIMBCMP2_Msk                  /*!< Timer B compare 2 */\n#define HRTIM_RSTR_TIMBCMP4_Pos       (21U)\n#define HRTIM_RSTR_TIMBCMP4_Msk       (0x1UL << HRTIM_RSTR_TIMBCMP4_Pos)       /*!< 0x00200000 */\n#define HRTIM_RSTR_TIMBCMP4           HRTIM_RSTR_TIMBCMP4_Msk                  /*!< Timer B compare 4 */\n\n#define HRTIM_RSTR_TIMCCMP1_Pos       (22U)\n#define HRTIM_RSTR_TIMCCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMCCMP1_Pos)       /*!< 0x00400000 */\n#define HRTIM_RSTR_TIMCCMP1           HRTIM_RSTR_TIMCCMP1_Msk                  /*!< Timer C compare 1 */\n#define HRTIM_RSTR_TIMCCMP2_Pos       (23U)\n#define HRTIM_RSTR_TIMCCMP2_Msk       (0x1UL << HRTIM_RSTR_TIMCCMP2_Pos)       /*!< 0x00800000 */\n#define HRTIM_RSTR_TIMCCMP2           HRTIM_RSTR_TIMCCMP2_Msk                  /*!< Timer C compare 2 */\n#define HRTIM_RSTR_TIMCCMP4_Pos       (24U)\n#define HRTIM_RSTR_TIMCCMP4_Msk       (0x1UL << HRTIM_RSTR_TIMCCMP4_Pos)       /*!< 0x01000000 */\n#define HRTIM_RSTR_TIMCCMP4           HRTIM_RSTR_TIMCCMP4_Msk                  /*!< Timer C compare 4 */\n\n#define HRTIM_RSTR_TIMDCMP1_Pos       (25U)\n#define HRTIM_RSTR_TIMDCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMDCMP1_Pos)       /*!< 0x02000000 */\n#define HRTIM_RSTR_TIMDCMP1           HRTIM_RSTR_TIMDCMP1_Msk                  /*!< Timer D compare 1 */\n#define HRTIM_RSTR_TIMDCMP2_Pos       (26U)\n#define HRTIM_RSTR_TIMDCMP2_Msk       (0x1UL << HRTIM_RSTR_TIMDCMP2_Pos)       /*!< 0x04000000 */\n#define HRTIM_RSTR_TIMDCMP2           HRTIM_RSTR_TIMDCMP2_Msk                  /*!< Timer D compare 2 */\n#define HRTIM_RSTR_TIMDCMP4_Pos       (27U)\n#define HRTIM_RSTR_TIMDCMP4_Msk       (0x1UL << HRTIM_RSTR_TIMDCMP4_Pos)       /*!< 0x08000000 */\n#define HRTIM_RSTR_TIMDCMP4           HRTIM_RSTR_TIMDCMP4_Msk                  /*!< Timer D compare 4 */\n\n#define HRTIM_RSTR_TIMECMP1_Pos       (28U)\n#define HRTIM_RSTR_TIMECMP1_Msk       (0x1UL << HRTIM_RSTR_TIMECMP1_Pos)       /*!< 0x10000000 */\n#define HRTIM_RSTR_TIMECMP1           HRTIM_RSTR_TIMECMP1_Msk                  /*!< Timer E compare 1 */\n#define HRTIM_RSTR_TIMECMP2_Pos       (29U)\n#define HRTIM_RSTR_TIMECMP2_Msk       (0x1UL << HRTIM_RSTR_TIMECMP2_Pos)       /*!< 0x20000000 */\n#define HRTIM_RSTR_TIMECMP2           HRTIM_RSTR_TIMECMP2_Msk                  /*!< Timer E compare 2 */\n#define HRTIM_RSTR_TIMECMP4_Pos       (30U)\n#define HRTIM_RSTR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTR_TIMECMP4_Pos)       /*!< 0x40000000 */\n#define HRTIM_RSTR_TIMECMP4           HRTIM_RSTR_TIMECMP4_Msk                  /*!< Timer E compare 4 */\n\n/* Slave Timer B reset enable bits upon other slave timers events */\n#define HRTIM_RSTBR_TIMACMP1_Pos       (19U)\n#define HRTIM_RSTBR_TIMACMP1_Msk       (0x1UL << HRTIM_RSTBR_TIMACMP1_Pos)     /*!< 0x00080000 */\n#define HRTIM_RSTBR_TIMACMP1           HRTIM_RSTBR_TIMACMP1_Msk                /*!< Timer A compare 1 */\n#define HRTIM_RSTBR_TIMACMP2_Pos       (20U)\n#define HRTIM_RSTBR_TIMACMP2_Msk       (0x1UL << HRTIM_RSTBR_TIMACMP2_Pos)     /*!< 0x00100000 */\n#define HRTIM_RSTBR_TIMACMP2           HRTIM_RSTBR_TIMACMP2_Msk                /*!< Timer A compare 2 */\n#define HRTIM_RSTBR_TIMACMP4_Pos       (21U)\n#define HRTIM_RSTBR_TIMACMP4_Msk       (0x1UL << HRTIM_RSTBR_TIMACMP4_Pos)     /*!< 0x00200000 */\n#define HRTIM_RSTBR_TIMACMP4           HRTIM_RSTBR_TIMACMP4_Msk                /*!< Timer A compare 4 */\n\n#define HRTIM_RSTBR_TIMCCMP1_Pos       (22U)\n#define HRTIM_RSTBR_TIMCCMP1_Msk       (0x1UL << HRTIM_RSTBR_TIMCCMP1_Pos)     /*!< 0x00400000 */\n#define HRTIM_RSTBR_TIMCCMP1           HRTIM_RSTBR_TIMCCMP1_Msk                /*!< Timer C compare 1 */\n#define HRTIM_RSTBR_TIMCCMP2_Pos       (23U)\n#define HRTIM_RSTBR_TIMCCMP2_Msk       (0x1UL << HRTIM_RSTBR_TIMCCMP2_Pos)     /*!< 0x00800000 */\n#define HRTIM_RSTBR_TIMCCMP2           HRTIM_RSTBR_TIMCCMP2_Msk                /*!< Timer C compare 2 */\n#define HRTIM_RSTBR_TIMCCMP4_Pos       (24U)\n#define HRTIM_RSTBR_TIMCCMP4_Msk       (0x1UL << HRTIM_RSTBR_TIMCCMP4_Pos)     /*!< 0x01000000 */\n#define HRTIM_RSTBR_TIMCCMP4           HRTIM_RSTBR_TIMCCMP4_Msk                /*!< Timer C compare 4 */\n\n#define HRTIM_RSTBR_TIMDCMP1_Pos       (25U)\n#define HRTIM_RSTBR_TIMDCMP1_Msk       (0x1UL << HRTIM_RSTBR_TIMDCMP1_Pos)     /*!< 0x02000000 */\n#define HRTIM_RSTBR_TIMDCMP1           HRTIM_RSTBR_TIMDCMP1_Msk                /*!< Timer D compare 1 */\n#define HRTIM_RSTBR_TIMDCMP2_Pos       (26U)\n#define HRTIM_RSTBR_TIMDCMP2_Msk       (0x1UL << HRTIM_RSTBR_TIMDCMP2_Pos)     /*!< 0x04000000 */\n#define HRTIM_RSTBR_TIMDCMP2           HRTIM_RSTBR_TIMDCMP2_Msk                /*!< Timer D compare 2 */\n#define HRTIM_RSTBR_TIMDCMP4_Pos       (27U)\n#define HRTIM_RSTBR_TIMDCMP4_Msk       (0x1UL << HRTIM_RSTBR_TIMDCMP4_Pos)     /*!< 0x08000000 */\n#define HRTIM_RSTBR_TIMDCMP4           HRTIM_RSTBR_TIMDCMP4_Msk                /*!< Timer D compare 4 */\n\n#define HRTIM_RSTBR_TIMECMP1_Pos       (28U)\n#define HRTIM_RSTBR_TIMECMP1_Msk       (0x1UL << HRTIM_RSTBR_TIMECMP1_Pos)     /*!< 0x10000000 */\n#define HRTIM_RSTBR_TIMECMP1           HRTIM_RSTBR_TIMECMP1_Msk                /*!< Timer E compare 1 */\n#define HRTIM_RSTBR_TIMECMP2_Pos       (29U)\n#define HRTIM_RSTBR_TIMECMP2_Msk       (0x1UL << HRTIM_RSTBR_TIMECMP2_Pos)     /*!< 0x20000000 */\n#define HRTIM_RSTBR_TIMECMP2           HRTIM_RSTBR_TIMECMP2_Msk                /*!< Timer E compare 2 */\n#define HRTIM_RSTBR_TIMECMP4_Pos       (30U)\n#define HRTIM_RSTBR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTBR_TIMECMP4_Pos)     /*!< 0x40000000 */\n#define HRTIM_RSTBR_TIMECMP4           HRTIM_RSTBR_TIMECMP4_Msk                /*!< Timer E compare 4 */\n\n/* Slave Timer C reset enable bits upon other slave timers events */\n#define HRTIM_RSTCR_TIMACMP1_Pos       (19U)\n#define HRTIM_RSTCR_TIMACMP1_Msk       (0x1UL << HRTIM_RSTCR_TIMACMP1_Pos)     /*!< 0x00080000 */\n#define HRTIM_RSTCR_TIMACMP1           HRTIM_RSTCR_TIMACMP1_Msk                /*!< Timer A compare 1 */\n#define HRTIM_RSTCR_TIMACMP2_Pos       (20U)\n#define HRTIM_RSTCR_TIMACMP2_Msk       (0x1UL << HRTIM_RSTCR_TIMACMP2_Pos)     /*!< 0x00100000 */\n#define HRTIM_RSTCR_TIMACMP2           HRTIM_RSTCR_TIMACMP2_Msk                /*!< Timer A compare 2 */\n#define HRTIM_RSTCR_TIMACMP4_Pos       (21U)\n#define HRTIM_RSTCR_TIMACMP4_Msk       (0x1UL << HRTIM_RSTCR_TIMACMP4_Pos)     /*!< 0x00200000 */\n#define HRTIM_RSTCR_TIMACMP4           HRTIM_RSTCR_TIMACMP4_Msk                /*!< Timer A compare 4 */\n\n#define HRTIM_RSTCR_TIMBCMP1_Pos       (22U)\n#define HRTIM_RSTCR_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTCR_TIMBCMP1_Pos)     /*!< 0x00400000 */\n#define HRTIM_RSTCR_TIMBCMP1           HRTIM_RSTCR_TIMBCMP1_Msk                /*!< Timer B compare 1 */\n#define HRTIM_RSTCR_TIMBCMP2_Pos       (23U)\n#define HRTIM_RSTCR_TIMBCMP2_Msk       (0x1UL << HRTIM_RSTCR_TIMBCMP2_Pos)     /*!< 0x00800000 */\n#define HRTIM_RSTCR_TIMBCMP2           HRTIM_RSTCR_TIMBCMP2_Msk                /*!< Timer B compare 2 */\n#define HRTIM_RSTCR_TIMBCMP4_Pos       (24U)\n#define HRTIM_RSTCR_TIMBCMP4_Msk       (0x1UL << HRTIM_RSTCR_TIMBCMP4_Pos)     /*!< 0x01000000 */\n#define HRTIM_RSTCR_TIMBCMP4           HRTIM_RSTCR_TIMBCMP4_Msk                /*!< Timer B compare 4 */\n\n#define HRTIM_RSTCR_TIMDCMP1_Pos       (25U)\n#define HRTIM_RSTCR_TIMDCMP1_Msk       (0x1UL << HRTIM_RSTCR_TIMDCMP1_Pos)     /*!< 0x02000000 */\n#define HRTIM_RSTCR_TIMDCMP1           HRTIM_RSTCR_TIMDCMP1_Msk                /*!< Timer D compare 1 */\n#define HRTIM_RSTCR_TIMDCMP2_Pos       (26U)\n#define HRTIM_RSTCR_TIMDCMP2_Msk       (0x1UL << HRTIM_RSTCR_TIMDCMP2_Pos)     /*!< 0x04000000 */\n#define HRTIM_RSTCR_TIMDCMP2           HRTIM_RSTCR_TIMDCMP2_Msk                /*!< Timer D compare 2 */\n#define HRTIM_RSTCR_TIMDCMP4_Pos       (27U)\n#define HRTIM_RSTCR_TIMDCMP4_Msk       (0x1UL << HRTIM_RSTCR_TIMDCMP4_Pos)     /*!< 0x08000000 */\n#define HRTIM_RSTCR_TIMDCMP4           HRTIM_RSTCR_TIMDCMP4_Msk                /*!< Timer D compare 4 */\n\n#define HRTIM_RSTCR_TIMECMP1_Pos       (28U)\n#define HRTIM_RSTCR_TIMECMP1_Msk       (0x1UL << HRTIM_RSTCR_TIMECMP1_Pos)     /*!< 0x10000000 */\n#define HRTIM_RSTCR_TIMECMP1           HRTIM_RSTCR_TIMECMP1_Msk                /*!< Timer E compare 1 */\n#define HRTIM_RSTCR_TIMECMP2_Pos       (29U)\n#define HRTIM_RSTCR_TIMECMP2_Msk       (0x1UL << HRTIM_RSTCR_TIMECMP2_Pos)     /*!< 0x20000000 */\n#define HRTIM_RSTCR_TIMECMP2           HRTIM_RSTCR_TIMECMP2_Msk                /*!< Timer E compare 2 */\n#define HRTIM_RSTCR_TIMECMP4_Pos       (30U)\n#define HRTIM_RSTCR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTCR_TIMECMP4_Pos)     /*!< 0x40000000 */\n#define HRTIM_RSTCR_TIMECMP4           HRTIM_RSTCR_TIMECMP4_Msk                /*!< Timer E compare 4 */\n\n/* Slave Timer D reset enable bits upon other slave timers events */\n#define HRTIM_RSTDR_TIMACMP1_Pos       (19U)\n#define HRTIM_RSTDR_TIMACMP1_Msk       (0x1UL << HRTIM_RSTDR_TIMACMP1_Pos)     /*!< 0x00080000 */\n#define HRTIM_RSTDR_TIMACMP1           HRTIM_RSTDR_TIMACMP1_Msk                /*!< Timer A compare 1 */\n#define HRTIM_RSTDR_TIMACMP2_Pos       (20U)\n#define HRTIM_RSTDR_TIMACMP2_Msk       (0x1UL << HRTIM_RSTDR_TIMACMP2_Pos)     /*!< 0x00100000 */\n#define HRTIM_RSTDR_TIMACMP2           HRTIM_RSTDR_TIMACMP2_Msk                /*!< Timer A compare 2 */\n#define HRTIM_RSTDR_TIMACMP4_Pos       (21U)\n#define HRTIM_RSTDR_TIMACMP4_Msk       (0x1UL << HRTIM_RSTDR_TIMACMP4_Pos)     /*!< 0x00200000 */\n#define HRTIM_RSTDR_TIMACMP4           HRTIM_RSTDR_TIMACMP4_Msk                /*!< Timer A compare 4 */\n\n#define HRTIM_RSTDR_TIMBCMP1_Pos       (22U)\n#define HRTIM_RSTDR_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTDR_TIMBCMP1_Pos)     /*!< 0x00400000 */\n#define HRTIM_RSTDR_TIMBCMP1           HRTIM_RSTDR_TIMBCMP1_Msk                /*!< Timer B compare 1 */\n#define HRTIM_RSTDR_TIMBCMP2_Pos       (23U)\n#define HRTIM_RSTDR_TIMBCMP2_Msk       (0x1UL << HRTIM_RSTDR_TIMBCMP2_Pos)     /*!< 0x00800000 */\n#define HRTIM_RSTDR_TIMBCMP2           HRTIM_RSTDR_TIMBCMP2_Msk                /*!< Timer B compare 2 */\n#define HRTIM_RSTDR_TIMBCMP4_Pos       (24U)\n#define HRTIM_RSTDR_TIMBCMP4_Msk       (0x1UL << HRTIM_RSTDR_TIMBCMP4_Pos)     /*!< 0x01000000 */\n#define HRTIM_RSTDR_TIMBCMP4           HRTIM_RSTDR_TIMBCMP4_Msk                /*!< Timer B compare 4 */\n\n#define HRTIM_RSTDR_TIMCCMP1_Pos       (25U)\n#define HRTIM_RSTDR_TIMCCMP1_Msk       (0x1UL << HRTIM_RSTDR_TIMCCMP1_Pos)     /*!< 0x02000000 */\n#define HRTIM_RSTDR_TIMCCMP1           HRTIM_RSTDR_TIMCCMP1_Msk                /*!< Timer C compare 1 */\n#define HRTIM_RSTDR_TIMCCMP2_Pos       (26U)\n#define HRTIM_RSTDR_TIMCCMP2_Msk       (0x1UL << HRTIM_RSTDR_TIMCCMP2_Pos)     /*!< 0x04000000 */\n#define HRTIM_RSTDR_TIMCCMP2           HRTIM_RSTDR_TIMCCMP2_Msk                /*!< Timer C compare 2 */\n#define HRTIM_RSTDR_TIMCCMP4_Pos       (27U)\n#define HRTIM_RSTDR_TIMCCMP4_Msk       (0x1UL << HRTIM_RSTDR_TIMCCMP4_Pos)     /*!< 0x08000000 */\n#define HRTIM_RSTDR_TIMCCMP4           HRTIM_RSTDR_TIMCCMP4_Msk                /*!< Timer C compare 4 */\n\n#define HRTIM_RSTDR_TIMECMP1_Pos       (28U)\n#define HRTIM_RSTDR_TIMECMP1_Msk       (0x1UL << HRTIM_RSTDR_TIMECMP1_Pos)     /*!< 0x10000000 */\n#define HRTIM_RSTDR_TIMECMP1           HRTIM_RSTDR_TIMECMP1_Msk                /*!< Timer E compare 1 */\n#define HRTIM_RSTDR_TIMECMP2_Pos       (29U)\n#define HRTIM_RSTDR_TIMECMP2_Msk       (0x1UL << HRTIM_RSTDR_TIMECMP2_Pos)     /*!< 0x20000000 */\n#define HRTIM_RSTDR_TIMECMP2           HRTIM_RSTDR_TIMECMP2_Msk                /*!< Timer E compare 2 */\n#define HRTIM_RSTDR_TIMECMP4_Pos       (30U)\n#define HRTIM_RSTDR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTDR_TIMECMP4_Pos)     /*!< 0x40000000 */\n#define HRTIM_RSTDR_TIMECMP4           HRTIM_RSTDR_TIMECMP4_Msk                /*!< Timer E compare 4 */\n\n/* Slave Timer E reset enable bits upon other slave timers events */\n#define HRTIM_RSTER_TIMACMP1_Pos       (19U)\n#define HRTIM_RSTER_TIMACMP1_Msk       (0x1UL << HRTIM_RSTER_TIMACMP1_Pos)     /*!< 0x00080000 */\n#define HRTIM_RSTER_TIMACMP1           HRTIM_RSTER_TIMACMP1_Msk                /*!< Timer A compare 1 */\n#define HRTIM_RSTER_TIMACMP2_Pos       (20U)\n#define HRTIM_RSTER_TIMACMP2_Msk       (0x1UL << HRTIM_RSTER_TIMACMP2_Pos)     /*!< 0x00100000 */\n#define HRTIM_RSTER_TIMACMP2           HRTIM_RSTER_TIMACMP2_Msk                /*!< Timer A compare 2 */\n#define HRTIM_RSTER_TIMACMP4_Pos       (21U)\n#define HRTIM_RSTER_TIMACMP4_Msk       (0x1UL << HRTIM_RSTER_TIMACMP4_Pos)     /*!< 0x00200000 */\n#define HRTIM_RSTER_TIMACMP4           HRTIM_RSTER_TIMACMP4_Msk                /*!< Timer A compare 4 */\n\n#define HRTIM_RSTER_TIMBCMP1_Pos       (22U)\n#define HRTIM_RSTER_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTER_TIMBCMP1_Pos)     /*!< 0x00400000 */\n#define HRTIM_RSTER_TIMBCMP1           HRTIM_RSTER_TIMBCMP1_Msk                /*!< Timer B compare 1 */\n#define HRTIM_RSTER_TIMBCMP2_Pos       (23U)\n#define HRTIM_RSTER_TIMBCMP2_Msk       (0x1UL << HRTIM_RSTER_TIMBCMP2_Pos)     /*!< 0x00800000 */\n#define HRTIM_RSTER_TIMBCMP2           HRTIM_RSTER_TIMBCMP2_Msk                /*!< Timer B compare 2 */\n#define HRTIM_RSTER_TIMBCMP4_Pos       (24U)\n#define HRTIM_RSTER_TIMBCMP4_Msk       (0x1UL << HRTIM_RSTER_TIMBCMP4_Pos)     /*!< 0x01000000 */\n#define HRTIM_RSTER_TIMBCMP4           HRTIM_RSTER_TIMBCMP4_Msk                /*!< Timer B compare 4 */\n\n#define HRTIM_RSTER_TIMCCMP1_Pos       (25U)\n#define HRTIM_RSTER_TIMCCMP1_Msk       (0x1UL << HRTIM_RSTER_TIMCCMP1_Pos)     /*!< 0x02000000 */\n#define HRTIM_RSTER_TIMCCMP1           HRTIM_RSTER_TIMCCMP1_Msk                /*!< Timer C compare 1 */\n#define HRTIM_RSTER_TIMCCMP2_Pos       (26U)\n#define HRTIM_RSTER_TIMCCMP2_Msk       (0x1UL << HRTIM_RSTER_TIMCCMP2_Pos)     /*!< 0x04000000 */\n#define HRTIM_RSTER_TIMCCMP2           HRTIM_RSTER_TIMCCMP2_Msk                /*!< Timer C compare 2 */\n#define HRTIM_RSTER_TIMCCMP4_Pos       (27U)\n#define HRTIM_RSTER_TIMCCMP4_Msk       (0x1UL << HRTIM_RSTER_TIMCCMP4_Pos)     /*!< 0x08000000 */\n#define HRTIM_RSTER_TIMCCMP4           HRTIM_RSTER_TIMCCMP4_Msk                /*!< Timer C compare 4 */\n\n#define HRTIM_RSTER_TIMDCMP1_Pos       (28U)\n#define HRTIM_RSTER_TIMDCMP1_Msk       (0x1UL << HRTIM_RSTER_TIMDCMP1_Pos)     /*!< 0x10000000 */\n#define HRTIM_RSTER_TIMDCMP1           HRTIM_RSTER_TIMDCMP1_Msk                /*!< Timer D compare 1 */\n#define HRTIM_RSTER_TIMDCMP2_Pos       (29U)\n#define HRTIM_RSTER_TIMDCMP2_Msk       (0x1UL << HRTIM_RSTER_TIMDCMP2_Pos)     /*!< 0x20000000 */\n#define HRTIM_RSTER_TIMDCMP2           HRTIM_RSTER_TIMDCMP2_Msk                /*!< Timer D compare 2 */\n#define HRTIM_RSTER_TIMDCMP4_Pos       (30U)\n#define HRTIM_RSTER_TIMDCMP4_Msk       (0x1UL << HRTIM_RSTER_TIMDCMP4_Pos)     /*!< 0x40000000 */\n#define HRTIM_RSTER_TIMDCMP4           HRTIM_RSTER_TIMDCMP4_Msk                /*!< Timer D compare 4 */\n\n/**** Bit definition for Slave Timer Chopper register *************************/\n#define HRTIM_CHPR_CARFRQ_Pos         (0U)\n#define HRTIM_CHPR_CARFRQ_Msk         (0xFUL << HRTIM_CHPR_CARFRQ_Pos)         /*!< 0x0000000F */\n#define HRTIM_CHPR_CARFRQ             HRTIM_CHPR_CARFRQ_Msk                    /*!< Timer carrier frequency value */\n#define HRTIM_CHPR_CARFRQ_0           (0x1UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000001 */\n#define HRTIM_CHPR_CARFRQ_1           (0x2UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000002 */\n#define HRTIM_CHPR_CARFRQ_2           (0x4UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000004 */\n#define HRTIM_CHPR_CARFRQ_3           (0x8UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000008 */\n\n#define HRTIM_CHPR_CARDTY_Pos         (4U)\n#define HRTIM_CHPR_CARDTY_Msk         (0x7UL << HRTIM_CHPR_CARDTY_Pos)         /*!< 0x00000070 */\n#define HRTIM_CHPR_CARDTY             HRTIM_CHPR_CARDTY_Msk                    /*!< Timer chopper duty cycle value */\n#define HRTIM_CHPR_CARDTY_0           (0x1UL << HRTIM_CHPR_CARDTY_Pos)          /*!< 0x00000010 */\n#define HRTIM_CHPR_CARDTY_1           (0x2UL << HRTIM_CHPR_CARDTY_Pos)          /*!< 0x00000020 */\n#define HRTIM_CHPR_CARDTY_2           (0x4UL << HRTIM_CHPR_CARDTY_Pos)          /*!< 0x00000040 */\n\n#define HRTIM_CHPR_STRPW_Pos          (7U)\n#define HRTIM_CHPR_STRPW_Msk          (0xFUL << HRTIM_CHPR_STRPW_Pos)          /*!< 0x00000780 */\n#define HRTIM_CHPR_STRPW              HRTIM_CHPR_STRPW_Msk                     /*!< Timer start pulse width value */\n#define HRTIM_CHPR_STRPW_0            (0x1UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000080 */\n#define HRTIM_CHPR_STRPW_1            (0x2UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000100 */\n#define HRTIM_CHPR_STRPW_2            (0x4UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000200 */\n#define HRTIM_CHPR_STRPW_3            (0x8UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000400 */\n\n/**** Bit definition for Slave Timer Capture 1 control register ***************/\n#define HRTIM_CPT1CR_SWCPT_Pos        (0U)\n#define HRTIM_CPT1CR_SWCPT_Msk        (0x1UL << HRTIM_CPT1CR_SWCPT_Pos)        /*!< 0x00000001 */\n#define HRTIM_CPT1CR_SWCPT            HRTIM_CPT1CR_SWCPT_Msk                   /*!< Software capture */\n#define HRTIM_CPT1CR_UPDCPT_Pos       (1U)\n#define HRTIM_CPT1CR_UPDCPT_Msk       (0x1UL << HRTIM_CPT1CR_UPDCPT_Pos)       /*!< 0x00000002 */\n#define HRTIM_CPT1CR_UPDCPT           HRTIM_CPT1CR_UPDCPT_Msk                  /*!< Update capture */\n#define HRTIM_CPT1CR_EXEV1CPT_Pos     (2U)\n#define HRTIM_CPT1CR_EXEV1CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV1CPT_Pos)     /*!< 0x00000004 */\n#define HRTIM_CPT1CR_EXEV1CPT         HRTIM_CPT1CR_EXEV1CPT_Msk                /*!< External event 1 capture */\n#define HRTIM_CPT1CR_EXEV2CPT_Pos     (3U)\n#define HRTIM_CPT1CR_EXEV2CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV2CPT_Pos)     /*!< 0x00000008 */\n#define HRTIM_CPT1CR_EXEV2CPT         HRTIM_CPT1CR_EXEV2CPT_Msk                /*!< External event 2 capture */\n#define HRTIM_CPT1CR_EXEV3CPT_Pos     (4U)\n#define HRTIM_CPT1CR_EXEV3CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV3CPT_Pos)     /*!< 0x00000010 */\n#define HRTIM_CPT1CR_EXEV3CPT         HRTIM_CPT1CR_EXEV3CPT_Msk                /*!< External event 3 capture */\n#define HRTIM_CPT1CR_EXEV4CPT_Pos     (5U)\n#define HRTIM_CPT1CR_EXEV4CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV4CPT_Pos)     /*!< 0x00000020 */\n#define HRTIM_CPT1CR_EXEV4CPT         HRTIM_CPT1CR_EXEV4CPT_Msk                /*!< External event 4 capture */\n#define HRTIM_CPT1CR_EXEV5CPT_Pos     (6U)\n#define HRTIM_CPT1CR_EXEV5CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV5CPT_Pos)     /*!< 0x00000040 */\n#define HRTIM_CPT1CR_EXEV5CPT         HRTIM_CPT1CR_EXEV5CPT_Msk                /*!< External event 5 capture */\n#define HRTIM_CPT1CR_EXEV6CPT_Pos     (7U)\n#define HRTIM_CPT1CR_EXEV6CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV6CPT_Pos)     /*!< 0x00000080 */\n#define HRTIM_CPT1CR_EXEV6CPT         HRTIM_CPT1CR_EXEV6CPT_Msk                /*!< External event 6 capture */\n#define HRTIM_CPT1CR_EXEV7CPT_Pos     (8U)\n#define HRTIM_CPT1CR_EXEV7CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV7CPT_Pos)     /*!< 0x00000100 */\n#define HRTIM_CPT1CR_EXEV7CPT         HRTIM_CPT1CR_EXEV7CPT_Msk                /*!< External event 7 capture */\n#define HRTIM_CPT1CR_EXEV8CPT_Pos     (9U)\n#define HRTIM_CPT1CR_EXEV8CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV8CPT_Pos)     /*!< 0x00000200 */\n#define HRTIM_CPT1CR_EXEV8CPT         HRTIM_CPT1CR_EXEV8CPT_Msk                /*!< External event 8 capture */\n#define HRTIM_CPT1CR_EXEV9CPT_Pos     (10U)\n#define HRTIM_CPT1CR_EXEV9CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV9CPT_Pos)     /*!< 0x00000400 */\n#define HRTIM_CPT1CR_EXEV9CPT         HRTIM_CPT1CR_EXEV9CPT_Msk                /*!< External event 9 capture */\n#define HRTIM_CPT1CR_EXEV10CPT_Pos    (11U)\n#define HRTIM_CPT1CR_EXEV10CPT_Msk    (0x1UL << HRTIM_CPT1CR_EXEV10CPT_Pos)    /*!< 0x00000800 */\n#define HRTIM_CPT1CR_EXEV10CPT        HRTIM_CPT1CR_EXEV10CPT_Msk               /*!< External event 10 capture */\n\n#define HRTIM_CPT1CR_TA1SET_Pos       (12U)\n#define HRTIM_CPT1CR_TA1SET_Msk       (0x1UL << HRTIM_CPT1CR_TA1SET_Pos)       /*!< 0x00001000 */\n#define HRTIM_CPT1CR_TA1SET           HRTIM_CPT1CR_TA1SET_Msk                  /*!< Timer A output 1 set */\n#define HRTIM_CPT1CR_TA1RST_Pos       (13U)\n#define HRTIM_CPT1CR_TA1RST_Msk       (0x1UL << HRTIM_CPT1CR_TA1RST_Pos)       /*!< 0x00002000 */\n#define HRTIM_CPT1CR_TA1RST           HRTIM_CPT1CR_TA1RST_Msk                  /*!< Timer A output 1 reset */\n#define HRTIM_CPT1CR_TIMACMP1_Pos     (14U)\n#define HRTIM_CPT1CR_TIMACMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMACMP1_Pos)     /*!< 0x00004000 */\n#define HRTIM_CPT1CR_TIMACMP1         HRTIM_CPT1CR_TIMACMP1_Msk                /*!< Timer A compare 1 */\n#define HRTIM_CPT1CR_TIMACMP2_Pos     (15U)\n#define HRTIM_CPT1CR_TIMACMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMACMP2_Pos)     /*!< 0x00008000 */\n#define HRTIM_CPT1CR_TIMACMP2         HRTIM_CPT1CR_TIMACMP2_Msk                /*!< Timer A compare 2 */\n\n#define HRTIM_CPT1CR_TB1SET_Pos       (16U)\n#define HRTIM_CPT1CR_TB1SET_Msk       (0x1UL << HRTIM_CPT1CR_TB1SET_Pos)       /*!< 0x00010000 */\n#define HRTIM_CPT1CR_TB1SET           HRTIM_CPT1CR_TB1SET_Msk                  /*!< Timer B output 1 set */\n#define HRTIM_CPT1CR_TB1RST_Pos       (17U)\n#define HRTIM_CPT1CR_TB1RST_Msk       (0x1UL << HRTIM_CPT1CR_TB1RST_Pos)       /*!< 0x00020000 */\n#define HRTIM_CPT1CR_TB1RST           HRTIM_CPT1CR_TB1RST_Msk                  /*!< Timer B output 1 reset */\n#define HRTIM_CPT1CR_TIMBCMP1_Pos     (18U)\n#define HRTIM_CPT1CR_TIMBCMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMBCMP1_Pos)     /*!< 0x00040000 */\n#define HRTIM_CPT1CR_TIMBCMP1         HRTIM_CPT1CR_TIMBCMP1_Msk                /*!< Timer B compare 1 */\n#define HRTIM_CPT1CR_TIMBCMP2_Pos     (19U)\n#define HRTIM_CPT1CR_TIMBCMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMBCMP2_Pos)     /*!< 0x00080000 */\n#define HRTIM_CPT1CR_TIMBCMP2         HRTIM_CPT1CR_TIMBCMP2_Msk                /*!< Timer B compare 2 */\n\n#define HRTIM_CPT1CR_TC1SET_Pos       (20U)\n#define HRTIM_CPT1CR_TC1SET_Msk       (0x1UL << HRTIM_CPT1CR_TC1SET_Pos)       /*!< 0x00100000 */\n#define HRTIM_CPT1CR_TC1SET           HRTIM_CPT1CR_TC1SET_Msk                  /*!< Timer C output 1 set */\n#define HRTIM_CPT1CR_TC1RST_Pos       (21U)\n#define HRTIM_CPT1CR_TC1RST_Msk       (0x1UL << HRTIM_CPT1CR_TC1RST_Pos)       /*!< 0x00200000 */\n#define HRTIM_CPT1CR_TC1RST           HRTIM_CPT1CR_TC1RST_Msk                  /*!< Timer C output 1 reset */\n#define HRTIM_CPT1CR_TIMCCMP1_Pos     (22U)\n#define HRTIM_CPT1CR_TIMCCMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMCCMP1_Pos)     /*!< 0x00400000 */\n#define HRTIM_CPT1CR_TIMCCMP1         HRTIM_CPT1CR_TIMCCMP1_Msk                /*!< Timer C compare 1 */\n#define HRTIM_CPT1CR_TIMCCMP2_Pos     (23U)\n#define HRTIM_CPT1CR_TIMCCMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMCCMP2_Pos)     /*!< 0x00800000 */\n#define HRTIM_CPT1CR_TIMCCMP2         HRTIM_CPT1CR_TIMCCMP2_Msk                /*!< Timer C compare 2 */\n\n#define HRTIM_CPT1CR_TD1SET_Pos       (24U)\n#define HRTIM_CPT1CR_TD1SET_Msk       (0x1UL << HRTIM_CPT1CR_TD1SET_Pos)       /*!< 0x01000000 */\n#define HRTIM_CPT1CR_TD1SET           HRTIM_CPT1CR_TD1SET_Msk                  /*!< Timer D output 1 set */\n#define HRTIM_CPT1CR_TD1RST_Pos       (25U)\n#define HRTIM_CPT1CR_TD1RST_Msk       (0x1UL << HRTIM_CPT1CR_TD1RST_Pos)       /*!< 0x02000000 */\n#define HRTIM_CPT1CR_TD1RST           HRTIM_CPT1CR_TD1RST_Msk                  /*!< Timer D output 1 reset */\n#define HRTIM_CPT1CR_TIMDCMP1_Pos     (26U)\n#define HRTIM_CPT1CR_TIMDCMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMDCMP1_Pos)     /*!< 0x04000000 */\n#define HRTIM_CPT1CR_TIMDCMP1         HRTIM_CPT1CR_TIMDCMP1_Msk                /*!< Timer D compare 1 */\n#define HRTIM_CPT1CR_TIMDCMP2_Pos     (27U)\n#define HRTIM_CPT1CR_TIMDCMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMDCMP2_Pos)     /*!< 0x08000000 */\n#define HRTIM_CPT1CR_TIMDCMP2         HRTIM_CPT1CR_TIMDCMP2_Msk                /*!< Timer D compare 2 */\n\n#define HRTIM_CPT1CR_TE1SET_Pos       (28U)\n#define HRTIM_CPT1CR_TE1SET_Msk       (0x1UL << HRTIM_CPT1CR_TE1SET_Pos)       /*!< 0x10000000 */\n#define HRTIM_CPT1CR_TE1SET           HRTIM_CPT1CR_TE1SET_Msk                  /*!< Timer E output 1 set */\n#define HRTIM_CPT1CR_TE1RST_Pos       (29U)\n#define HRTIM_CPT1CR_TE1RST_Msk       (0x1UL << HRTIM_CPT1CR_TE1RST_Pos)       /*!< 0x20000000 */\n#define HRTIM_CPT1CR_TE1RST           HRTIM_CPT1CR_TE1RST_Msk                  /*!< Timer E output 1 reset */\n#define HRTIM_CPT1CR_TIMECMP1_Pos     (30U)\n#define HRTIM_CPT1CR_TIMECMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMECMP1_Pos)     /*!< 0x40000000 */\n#define HRTIM_CPT1CR_TIMECMP1         HRTIM_CPT1CR_TIMECMP1_Msk                /*!< Timer E compare 1 */\n#define HRTIM_CPT1CR_TIMECMP2_Pos     (31U)\n#define HRTIM_CPT1CR_TIMECMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMECMP2_Pos)     /*!< 0x80000000 */\n#define HRTIM_CPT1CR_TIMECMP2         HRTIM_CPT1CR_TIMECMP2_Msk                /*!< Timer E compare 2 */\n\n/**** Bit definition for Slave Timer Capture 2 control register ***************/\n#define HRTIM_CPT2CR_SWCPT_Pos        (0U)\n#define HRTIM_CPT2CR_SWCPT_Msk        (0x1UL << HRTIM_CPT2CR_SWCPT_Pos)        /*!< 0x00000001 */\n#define HRTIM_CPT2CR_SWCPT            HRTIM_CPT2CR_SWCPT_Msk                   /*!< Software capture */\n#define HRTIM_CPT2CR_UPDCPT_Pos       (1U)\n#define HRTIM_CPT2CR_UPDCPT_Msk       (0x1UL << HRTIM_CPT2CR_UPDCPT_Pos)       /*!< 0x00000002 */\n#define HRTIM_CPT2CR_UPDCPT           HRTIM_CPT2CR_UPDCPT_Msk                  /*!< Update capture */\n#define HRTIM_CPT2CR_EXEV1CPT_Pos     (2U)\n#define HRTIM_CPT2CR_EXEV1CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV1CPT_Pos)     /*!< 0x00000004 */\n#define HRTIM_CPT2CR_EXEV1CPT         HRTIM_CPT2CR_EXEV1CPT_Msk                /*!< External event 1 capture */\n#define HRTIM_CPT2CR_EXEV2CPT_Pos     (3U)\n#define HRTIM_CPT2CR_EXEV2CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV2CPT_Pos)     /*!< 0x00000008 */\n#define HRTIM_CPT2CR_EXEV2CPT         HRTIM_CPT2CR_EXEV2CPT_Msk                /*!< External event 2 capture */\n#define HRTIM_CPT2CR_EXEV3CPT_Pos     (4U)\n#define HRTIM_CPT2CR_EXEV3CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV3CPT_Pos)     /*!< 0x00000010 */\n#define HRTIM_CPT2CR_EXEV3CPT         HRTIM_CPT2CR_EXEV3CPT_Msk                /*!< External event 3 capture */\n#define HRTIM_CPT2CR_EXEV4CPT_Pos     (5U)\n#define HRTIM_CPT2CR_EXEV4CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV4CPT_Pos)     /*!< 0x00000020 */\n#define HRTIM_CPT2CR_EXEV4CPT         HRTIM_CPT2CR_EXEV4CPT_Msk                /*!< External event 4 capture */\n#define HRTIM_CPT2CR_EXEV5CPT_Pos     (6U)\n#define HRTIM_CPT2CR_EXEV5CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV5CPT_Pos)     /*!< 0x00000040 */\n#define HRTIM_CPT2CR_EXEV5CPT         HRTIM_CPT2CR_EXEV5CPT_Msk                /*!< External event 5 capture */\n#define HRTIM_CPT2CR_EXEV6CPT_Pos     (7U)\n#define HRTIM_CPT2CR_EXEV6CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV6CPT_Pos)     /*!< 0x00000080 */\n#define HRTIM_CPT2CR_EXEV6CPT         HRTIM_CPT2CR_EXEV6CPT_Msk                /*!< External event 6 capture */\n#define HRTIM_CPT2CR_EXEV7CPT_Pos     (8U)\n#define HRTIM_CPT2CR_EXEV7CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV7CPT_Pos)     /*!< 0x00000100 */\n#define HRTIM_CPT2CR_EXEV7CPT         HRTIM_CPT2CR_EXEV7CPT_Msk                /*!< External event 7 capture */\n#define HRTIM_CPT2CR_EXEV8CPT_Pos     (9U)\n#define HRTIM_CPT2CR_EXEV8CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV8CPT_Pos)     /*!< 0x00000200 */\n#define HRTIM_CPT2CR_EXEV8CPT         HRTIM_CPT2CR_EXEV8CPT_Msk                /*!< External event 8 capture */\n#define HRTIM_CPT2CR_EXEV9CPT_Pos     (10U)\n#define HRTIM_CPT2CR_EXEV9CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV9CPT_Pos)     /*!< 0x00000400 */\n#define HRTIM_CPT2CR_EXEV9CPT         HRTIM_CPT2CR_EXEV9CPT_Msk                /*!< External event 9 capture */\n#define HRTIM_CPT2CR_EXEV10CPT_Pos    (11U)\n#define HRTIM_CPT2CR_EXEV10CPT_Msk    (0x1UL << HRTIM_CPT2CR_EXEV10CPT_Pos)    /*!< 0x00000800 */\n#define HRTIM_CPT2CR_EXEV10CPT        HRTIM_CPT2CR_EXEV10CPT_Msk               /*!< External event 10 capture */\n\n#define HRTIM_CPT2CR_TA1SET_Pos       (12U)\n#define HRTIM_CPT2CR_TA1SET_Msk       (0x1UL << HRTIM_CPT2CR_TA1SET_Pos)       /*!< 0x00001000 */\n#define HRTIM_CPT2CR_TA1SET           HRTIM_CPT2CR_TA1SET_Msk                  /*!< Timer A output 1 set */\n#define HRTIM_CPT2CR_TA1RST_Pos       (13U)\n#define HRTIM_CPT2CR_TA1RST_Msk       (0x1UL << HRTIM_CPT2CR_TA1RST_Pos)       /*!< 0x00002000 */\n#define HRTIM_CPT2CR_TA1RST           HRTIM_CPT2CR_TA1RST_Msk                  /*!< Timer A output 1 reset */\n#define HRTIM_CPT2CR_TIMACMP1_Pos     (14U)\n#define HRTIM_CPT2CR_TIMACMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMACMP1_Pos)     /*!< 0x00004000 */\n#define HRTIM_CPT2CR_TIMACMP1         HRTIM_CPT2CR_TIMACMP1_Msk                /*!< Timer A compare 1 */\n#define HRTIM_CPT2CR_TIMACMP2_Pos     (15U)\n#define HRTIM_CPT2CR_TIMACMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMACMP2_Pos)     /*!< 0x00008000 */\n#define HRTIM_CPT2CR_TIMACMP2         HRTIM_CPT2CR_TIMACMP2_Msk                /*!< Timer A compare 2 */\n\n#define HRTIM_CPT2CR_TB1SET_Pos       (16U)\n#define HRTIM_CPT2CR_TB1SET_Msk       (0x1UL << HRTIM_CPT2CR_TB1SET_Pos)       /*!< 0x00010000 */\n#define HRTIM_CPT2CR_TB1SET           HRTIM_CPT2CR_TB1SET_Msk                  /*!< Timer B output 1 set */\n#define HRTIM_CPT2CR_TB1RST_Pos       (17U)\n#define HRTIM_CPT2CR_TB1RST_Msk       (0x1UL << HRTIM_CPT2CR_TB1RST_Pos)       /*!< 0x00020000 */\n#define HRTIM_CPT2CR_TB1RST           HRTIM_CPT2CR_TB1RST_Msk                  /*!< Timer B output 1 reset */\n#define HRTIM_CPT2CR_TIMBCMP1_Pos     (18U)\n#define HRTIM_CPT2CR_TIMBCMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMBCMP1_Pos)     /*!< 0x00040000 */\n#define HRTIM_CPT2CR_TIMBCMP1         HRTIM_CPT2CR_TIMBCMP1_Msk                /*!< Timer B compare 1 */\n#define HRTIM_CPT2CR_TIMBCMP2_Pos     (19U)\n#define HRTIM_CPT2CR_TIMBCMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMBCMP2_Pos)     /*!< 0x00080000 */\n#define HRTIM_CPT2CR_TIMBCMP2         HRTIM_CPT2CR_TIMBCMP2_Msk                /*!< Timer B compare 2 */\n\n#define HRTIM_CPT2CR_TC1SET_Pos       (20U)\n#define HRTIM_CPT2CR_TC1SET_Msk       (0x1UL << HRTIM_CPT2CR_TC1SET_Pos)       /*!< 0x00100000 */\n#define HRTIM_CPT2CR_TC1SET           HRTIM_CPT2CR_TC1SET_Msk                  /*!< Timer C output 1 set */\n#define HRTIM_CPT2CR_TC1RST_Pos       (21U)\n#define HRTIM_CPT2CR_TC1RST_Msk       (0x1UL << HRTIM_CPT2CR_TC1RST_Pos)       /*!< 0x00200000 */\n#define HRTIM_CPT2CR_TC1RST           HRTIM_CPT2CR_TC1RST_Msk                  /*!< Timer C output 1 reset */\n#define HRTIM_CPT2CR_TIMCCMP1_Pos     (22U)\n#define HRTIM_CPT2CR_TIMCCMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMCCMP1_Pos)     /*!< 0x00400000 */\n#define HRTIM_CPT2CR_TIMCCMP1         HRTIM_CPT2CR_TIMCCMP1_Msk                /*!< Timer C compare 1 */\n#define HRTIM_CPT2CR_TIMCCMP2_Pos     (23U)\n#define HRTIM_CPT2CR_TIMCCMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMCCMP2_Pos)     /*!< 0x00800000 */\n#define HRTIM_CPT2CR_TIMCCMP2         HRTIM_CPT2CR_TIMCCMP2_Msk                /*!< Timer C compare 2 */\n\n#define HRTIM_CPT2CR_TD1SET_Pos       (24U)\n#define HRTIM_CPT2CR_TD1SET_Msk       (0x1UL << HRTIM_CPT2CR_TD1SET_Pos)       /*!< 0x01000000 */\n#define HRTIM_CPT2CR_TD1SET           HRTIM_CPT2CR_TD1SET_Msk                  /*!< Timer D output 1 set */\n#define HRTIM_CPT2CR_TD1RST_Pos       (25U)\n#define HRTIM_CPT2CR_TD1RST_Msk       (0x1UL << HRTIM_CPT2CR_TD1RST_Pos)       /*!< 0x02000000 */\n#define HRTIM_CPT2CR_TD1RST           HRTIM_CPT2CR_TD1RST_Msk                  /*!< Timer D output 1 reset */\n#define HRTIM_CPT2CR_TIMDCMP1_Pos     (26U)\n#define HRTIM_CPT2CR_TIMDCMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMDCMP1_Pos)     /*!< 0x04000000 */\n#define HRTIM_CPT2CR_TIMDCMP1         HRTIM_CPT2CR_TIMDCMP1_Msk                /*!< Timer D compare 1 */\n#define HRTIM_CPT2CR_TIMDCMP2_Pos     (27U)\n#define HRTIM_CPT2CR_TIMDCMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMDCMP2_Pos)     /*!< 0x08000000 */\n#define HRTIM_CPT2CR_TIMDCMP2         HRTIM_CPT2CR_TIMDCMP2_Msk                /*!< Timer D compare 2 */\n\n#define HRTIM_CPT2CR_TE1SET_Pos       (28U)\n#define HRTIM_CPT2CR_TE1SET_Msk       (0x1UL << HRTIM_CPT2CR_TE1SET_Pos)       /*!< 0x10000000 */\n#define HRTIM_CPT2CR_TE1SET           HRTIM_CPT2CR_TE1SET_Msk                  /*!< Timer E output 1 set */\n#define HRTIM_CPT2CR_TE1RST_Pos       (29U)\n#define HRTIM_CPT2CR_TE1RST_Msk       (0x1UL << HRTIM_CPT2CR_TE1RST_Pos)       /*!< 0x20000000 */\n#define HRTIM_CPT2CR_TE1RST           HRTIM_CPT2CR_TE1RST_Msk                  /*!< Timer E output 1 reset */\n#define HRTIM_CPT2CR_TIMECMP1_Pos     (30U)\n#define HRTIM_CPT2CR_TIMECMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMECMP1_Pos)     /*!< 0x40000000 */\n#define HRTIM_CPT2CR_TIMECMP1         HRTIM_CPT2CR_TIMECMP1_Msk                /*!< Timer E compare 1 */\n#define HRTIM_CPT2CR_TIMECMP2_Pos     (31U)\n#define HRTIM_CPT2CR_TIMECMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMECMP2_Pos)     /*!< 0x80000000 */\n#define HRTIM_CPT2CR_TIMECMP2         HRTIM_CPT2CR_TIMECMP2_Msk                /*!< Timer E compare 2 */\n\n/**** Bit definition for Slave Timer Output register **************************/\n#define HRTIM_OUTR_POL1_Pos           (1U)\n#define HRTIM_OUTR_POL1_Msk           (0x1UL << HRTIM_OUTR_POL1_Pos)           /*!< 0x00000002 */\n#define HRTIM_OUTR_POL1               HRTIM_OUTR_POL1_Msk                      /*!< Slave output 1 polarity */\n#define HRTIM_OUTR_IDLM1_Pos          (2U)\n#define HRTIM_OUTR_IDLM1_Msk          (0x1UL << HRTIM_OUTR_IDLM1_Pos)          /*!< 0x00000004 */\n#define HRTIM_OUTR_IDLM1              HRTIM_OUTR_IDLM1_Msk                     /*!< Slave output 1 idle mode */\n#define HRTIM_OUTR_IDLES1_Pos         (3U)\n#define HRTIM_OUTR_IDLES1_Msk         (0x1UL << HRTIM_OUTR_IDLES1_Pos)         /*!< 0x00000008 */\n#define HRTIM_OUTR_IDLES1             HRTIM_OUTR_IDLES1_Msk                    /*!< Slave output 1 idle state */\n#define HRTIM_OUTR_FAULT1_Pos         (4U)\n#define HRTIM_OUTR_FAULT1_Msk         (0x3UL << HRTIM_OUTR_FAULT1_Pos)         /*!< 0x00000030 */\n#define HRTIM_OUTR_FAULT1             HRTIM_OUTR_FAULT1_Msk                    /*!< Slave output 1 fault state */\n#define HRTIM_OUTR_FAULT1_0           (0x1UL << HRTIM_OUTR_FAULT1_Pos)          /*!< 0x00000010 */\n#define HRTIM_OUTR_FAULT1_1           (0x2UL << HRTIM_OUTR_FAULT1_Pos)          /*!< 0x00000020 */\n#define HRTIM_OUTR_CHP1_Pos           (6U)\n#define HRTIM_OUTR_CHP1_Msk           (0x1UL << HRTIM_OUTR_CHP1_Pos)           /*!< 0x00000040 */\n#define HRTIM_OUTR_CHP1               HRTIM_OUTR_CHP1_Msk                      /*!< Slave output 1 chopper enable */\n#define HRTIM_OUTR_DIDL1_Pos          (7U)\n#define HRTIM_OUTR_DIDL1_Msk          (0x1UL << HRTIM_OUTR_DIDL1_Pos)          /*!< 0x00000080 */\n#define HRTIM_OUTR_DIDL1              HRTIM_OUTR_DIDL1_Msk                     /*!< Slave output 1 dead time idle */\n\n#define HRTIM_OUTR_DTEN_Pos           (8U)\n#define HRTIM_OUTR_DTEN_Msk           (0x1UL << HRTIM_OUTR_DTEN_Pos)           /*!< 0x00000100 */\n#define HRTIM_OUTR_DTEN               HRTIM_OUTR_DTEN_Msk                      /*!< Slave output deadtime enable */\n#define HRTIM_OUTR_DLYPRTEN_Pos       (9U)\n#define HRTIM_OUTR_DLYPRTEN_Msk       (0x1UL << HRTIM_OUTR_DLYPRTEN_Pos)       /*!< 0x00000200 */\n#define HRTIM_OUTR_DLYPRTEN           HRTIM_OUTR_DLYPRTEN_Msk                  /*!< Slave output delay protection enable */\n#define HRTIM_OUTR_DLYPRT_Pos         (10U)\n#define HRTIM_OUTR_DLYPRT_Msk         (0x7UL << HRTIM_OUTR_DLYPRT_Pos)         /*!< 0x00001C00 */\n#define HRTIM_OUTR_DLYPRT             HRTIM_OUTR_DLYPRT_Msk                    /*!< Slave output delay protection */\n#define HRTIM_OUTR_DLYPRT_0           (0x1UL << HRTIM_OUTR_DLYPRT_Pos)          /*!< 0x00000400 */\n#define HRTIM_OUTR_DLYPRT_1           (0x2UL << HRTIM_OUTR_DLYPRT_Pos)          /*!< 0x00000800 */\n#define HRTIM_OUTR_DLYPRT_2           (0x4UL << HRTIM_OUTR_DLYPRT_Pos)          /*!< 0x00001000 */\n\n#define HRTIM_OUTR_POL2_Pos           (17U)\n#define HRTIM_OUTR_POL2_Msk           (0x1UL << HRTIM_OUTR_POL2_Pos)           /*!< 0x00020000 */\n#define HRTIM_OUTR_POL2               HRTIM_OUTR_POL2_Msk                      /*!< Slave output 2 polarity */\n#define HRTIM_OUTR_IDLM2_Pos          (18U)\n#define HRTIM_OUTR_IDLM2_Msk          (0x1UL << HRTIM_OUTR_IDLM2_Pos)          /*!< 0x00040000 */\n#define HRTIM_OUTR_IDLM2              HRTIM_OUTR_IDLM2_Msk                     /*!< Slave output 2 idle mode */\n#define HRTIM_OUTR_IDLES2_Pos         (19U)\n#define HRTIM_OUTR_IDLES2_Msk         (0x1UL << HRTIM_OUTR_IDLES2_Pos)         /*!< 0x00080000 */\n#define HRTIM_OUTR_IDLES2             HRTIM_OUTR_IDLES2_Msk                    /*!< Slave output 2 idle state */\n#define HRTIM_OUTR_FAULT2_Pos         (20U)\n#define HRTIM_OUTR_FAULT2_Msk         (0x3UL << HRTIM_OUTR_FAULT2_Pos)         /*!< 0x00300000 */\n#define HRTIM_OUTR_FAULT2             HRTIM_OUTR_FAULT2_Msk                    /*!< Slave output 2 fault state */\n#define HRTIM_OUTR_FAULT2_0           (0x1UL << HRTIM_OUTR_FAULT2_Pos)          /*!< 0x00100000 */\n#define HRTIM_OUTR_FAULT2_1           (0x2UL << HRTIM_OUTR_FAULT2_Pos)          /*!< 0x00200000 */\n#define HRTIM_OUTR_CHP2_Pos           (22U)\n#define HRTIM_OUTR_CHP2_Msk           (0x1UL << HRTIM_OUTR_CHP2_Pos)           /*!< 0x00400000 */\n#define HRTIM_OUTR_CHP2               HRTIM_OUTR_CHP2_Msk                      /*!< Slave output 2 chopper enable */\n#define HRTIM_OUTR_DIDL2_Pos          (23U)\n#define HRTIM_OUTR_DIDL2_Msk          (0x1UL << HRTIM_OUTR_DIDL2_Pos)          /*!< 0x00800000 */\n#define HRTIM_OUTR_DIDL2              HRTIM_OUTR_DIDL2_Msk                     /*!< Slave output 2 dead time idle */\n\n/**** Bit definition for Slave Timer Fault register ***************************/\n#define HRTIM_FLTR_FLT1EN_Pos         (0U)\n#define HRTIM_FLTR_FLT1EN_Msk         (0x1UL << HRTIM_FLTR_FLT1EN_Pos)         /*!< 0x00000001 */\n#define HRTIM_FLTR_FLT1EN             HRTIM_FLTR_FLT1EN_Msk                    /*!< Fault 1 enable */\n#define HRTIM_FLTR_FLT2EN_Pos         (1U)\n#define HRTIM_FLTR_FLT2EN_Msk         (0x1UL << HRTIM_FLTR_FLT2EN_Pos)         /*!< 0x00000002 */\n#define HRTIM_FLTR_FLT2EN             HRTIM_FLTR_FLT2EN_Msk                    /*!< Fault 2 enable */\n#define HRTIM_FLTR_FLT3EN_Pos         (2U)\n#define HRTIM_FLTR_FLT3EN_Msk         (0x1UL << HRTIM_FLTR_FLT3EN_Pos)         /*!< 0x00000004 */\n#define HRTIM_FLTR_FLT3EN             HRTIM_FLTR_FLT3EN_Msk                    /*!< Fault 3 enable */\n#define HRTIM_FLTR_FLT4EN_Pos         (3U)\n#define HRTIM_FLTR_FLT4EN_Msk         (0x1UL << HRTIM_FLTR_FLT4EN_Pos)         /*!< 0x00000008 */\n#define HRTIM_FLTR_FLT4EN             HRTIM_FLTR_FLT4EN_Msk                    /*!< Fault 4 enable */\n#define HRTIM_FLTR_FLT5EN_Pos         (4U)\n#define HRTIM_FLTR_FLT5EN_Msk         (0x1UL << HRTIM_FLTR_FLT5EN_Pos)         /*!< 0x00000010 */\n#define HRTIM_FLTR_FLT5EN             HRTIM_FLTR_FLT5EN_Msk                    /*!< Fault 5 enable */\n#define HRTIM_FLTR_FLTLCK_Pos         (31U)\n#define HRTIM_FLTR_FLTLCK_Msk         (0x1UL << HRTIM_FLTR_FLTLCK_Pos)         /*!< 0x80000000 */\n#define HRTIM_FLTR_FLTLCK             HRTIM_FLTR_FLTLCK_Msk                    /*!< Fault sources lock */\n\n/**** Bit definition for Common HRTIM Timer control register 1 ****************/\n#define HRTIM_CR1_MUDIS_Pos           (0U)\n#define HRTIM_CR1_MUDIS_Msk           (0x1UL << HRTIM_CR1_MUDIS_Pos)           /*!< 0x00000001 */\n#define HRTIM_CR1_MUDIS               HRTIM_CR1_MUDIS_Msk                      /*!< Master update disable*/\n#define HRTIM_CR1_TAUDIS_Pos          (1U)\n#define HRTIM_CR1_TAUDIS_Msk          (0x1UL << HRTIM_CR1_TAUDIS_Pos)          /*!< 0x00000002 */\n#define HRTIM_CR1_TAUDIS              HRTIM_CR1_TAUDIS_Msk                     /*!< Timer A update disable*/\n#define HRTIM_CR1_TBUDIS_Pos          (2U)\n#define HRTIM_CR1_TBUDIS_Msk          (0x1UL << HRTIM_CR1_TBUDIS_Pos)          /*!< 0x00000004 */\n#define HRTIM_CR1_TBUDIS              HRTIM_CR1_TBUDIS_Msk                     /*!< Timer B update disable*/\n#define HRTIM_CR1_TCUDIS_Pos          (3U)\n#define HRTIM_CR1_TCUDIS_Msk          (0x1UL << HRTIM_CR1_TCUDIS_Pos)          /*!< 0x00000008 */\n#define HRTIM_CR1_TCUDIS              HRTIM_CR1_TCUDIS_Msk                     /*!< Timer C update disable*/\n#define HRTIM_CR1_TDUDIS_Pos          (4U)\n#define HRTIM_CR1_TDUDIS_Msk          (0x1UL << HRTIM_CR1_TDUDIS_Pos)          /*!< 0x00000010 */\n#define HRTIM_CR1_TDUDIS              HRTIM_CR1_TDUDIS_Msk                     /*!< Timer D update disable*/\n#define HRTIM_CR1_TEUDIS_Pos          (5U)\n#define HRTIM_CR1_TEUDIS_Msk          (0x1UL << HRTIM_CR1_TEUDIS_Pos)          /*!< 0x00000020 */\n#define HRTIM_CR1_TEUDIS              HRTIM_CR1_TEUDIS_Msk                     /*!< Timer E update disable*/\n#define HRTIM_CR1_ADC1USRC_Pos        (16U)\n#define HRTIM_CR1_ADC1USRC_Msk        (0x7UL << HRTIM_CR1_ADC1USRC_Pos)        /*!< 0x00070000 */\n#define HRTIM_CR1_ADC1USRC            HRTIM_CR1_ADC1USRC_Msk                   /*!< ADC Trigger 1 update source */\n#define HRTIM_CR1_ADC1USRC_0          (0x1UL << HRTIM_CR1_ADC1USRC_Pos)         /*!< 0x00010000 */\n#define HRTIM_CR1_ADC1USRC_1          (0x2UL << HRTIM_CR1_ADC1USRC_Pos)         /*!< 0x00020000 */\n#define HRTIM_CR1_ADC1USRC_2          (0x4UL << HRTIM_CR1_ADC1USRC_Pos)         /*!< 0x00040000 */\n#define HRTIM_CR1_ADC2USRC_Pos        (19U)\n#define HRTIM_CR1_ADC2USRC_Msk        (0x7UL << HRTIM_CR1_ADC2USRC_Pos)        /*!< 0x00380000 */\n#define HRTIM_CR1_ADC2USRC            HRTIM_CR1_ADC2USRC_Msk                   /*!< ADC Trigger 2 update source */\n#define HRTIM_CR1_ADC2USRC_0          (0x1UL << HRTIM_CR1_ADC2USRC_Pos)         /*!< 0x00080000 */\n#define HRTIM_CR1_ADC2USRC_1          (0x2UL << HRTIM_CR1_ADC2USRC_Pos)         /*!< 0x00100000 */\n#define HRTIM_CR1_ADC2USRC_2          (0x4UL << HRTIM_CR1_ADC2USRC_Pos)         /*!< 0x00200000 */\n#define HRTIM_CR1_ADC3USRC_Pos        (22U)\n#define HRTIM_CR1_ADC3USRC_Msk        (0x7UL << HRTIM_CR1_ADC3USRC_Pos)        /*!< 0x01C00000 */\n#define HRTIM_CR1_ADC3USRC            HRTIM_CR1_ADC3USRC_Msk                   /*!< ADC Trigger 3 update source */\n#define HRTIM_CR1_ADC3USRC_0          (0x1UL << HRTIM_CR1_ADC3USRC_Pos)         /*!< 0x00400000 */\n#define HRTIM_CR1_ADC3USRC_1          (0x2UL << HRTIM_CR1_ADC3USRC_Pos)         /*!< 0x00800000 */\n#define HRTIM_CR1_ADC3USRC_2          (0x4UL << HRTIM_CR1_ADC3USRC_Pos)         /*!< 0x01000000 */\n#define HRTIM_CR1_ADC4USRC_Pos        (25U)\n#define HRTIM_CR1_ADC4USRC_Msk        (0x7UL << HRTIM_CR1_ADC4USRC_Pos)        /*!< 0x0E000000 */\n#define HRTIM_CR1_ADC4USRC            HRTIM_CR1_ADC4USRC_Msk                   /*!< ADC Trigger 4 update source */\n#define HRTIM_CR1_ADC4USRC_0          (0x1UL << HRTIM_CR1_ADC4USRC_Pos)         /*!< 0x02000000 */\n#define HRTIM_CR1_ADC4USRC_1          (0x2UL << HRTIM_CR1_ADC4USRC_Pos)         /*!< 0x04000000 */\n#define HRTIM_CR1_ADC4USRC_2          (0x0UL << HRTIM_CR1_ADC4USRC_Pos)         /*!< 0x0800000 */\n\n/**** Bit definition for Common HRTIM Timer control register 2 ****************/\n#define HRTIM_CR2_MSWU_Pos            (0U)\n#define HRTIM_CR2_MSWU_Msk            (0x1UL << HRTIM_CR2_MSWU_Pos)            /*!< 0x00000001 */\n#define HRTIM_CR2_MSWU                HRTIM_CR2_MSWU_Msk                       /*!< Master software update */\n#define HRTIM_CR2_TASWU_Pos           (1U)\n#define HRTIM_CR2_TASWU_Msk           (0x1UL << HRTIM_CR2_TASWU_Pos)           /*!< 0x00000002 */\n#define HRTIM_CR2_TASWU               HRTIM_CR2_TASWU_Msk                      /*!< Timer A software update */\n#define HRTIM_CR2_TBSWU_Pos           (2U)\n#define HRTIM_CR2_TBSWU_Msk           (0x1UL << HRTIM_CR2_TBSWU_Pos)           /*!< 0x00000004 */\n#define HRTIM_CR2_TBSWU               HRTIM_CR2_TBSWU_Msk                      /*!< Timer B software update */\n#define HRTIM_CR2_TCSWU_Pos           (3U)\n#define HRTIM_CR2_TCSWU_Msk           (0x1UL << HRTIM_CR2_TCSWU_Pos)           /*!< 0x00000008 */\n#define HRTIM_CR2_TCSWU               HRTIM_CR2_TCSWU_Msk                      /*!< Timer C software update */\n#define HRTIM_CR2_TDSWU_Pos           (4U)\n#define HRTIM_CR2_TDSWU_Msk           (0x1UL << HRTIM_CR2_TDSWU_Pos)           /*!< 0x00000010 */\n#define HRTIM_CR2_TDSWU               HRTIM_CR2_TDSWU_Msk                      /*!< Timer D software update */\n#define HRTIM_CR2_TESWU_Pos           (5U)\n#define HRTIM_CR2_TESWU_Msk           (0x1UL << HRTIM_CR2_TESWU_Pos)           /*!< 0x00000020 */\n#define HRTIM_CR2_TESWU               HRTIM_CR2_TESWU_Msk                      /*!< Timer E software update */\n#define HRTIM_CR2_MRST_Pos            (8U)\n#define HRTIM_CR2_MRST_Msk            (0x1UL << HRTIM_CR2_MRST_Pos)            /*!< 0x00000100 */\n#define HRTIM_CR2_MRST                HRTIM_CR2_MRST_Msk                       /*!< Master count software reset */\n#define HRTIM_CR2_TARST_Pos           (9U)\n#define HRTIM_CR2_TARST_Msk           (0x1UL << HRTIM_CR2_TARST_Pos)           /*!< 0x00000200 */\n#define HRTIM_CR2_TARST               HRTIM_CR2_TARST_Msk                      /*!< Timer A count software reset */\n#define HRTIM_CR2_TBRST_Pos           (10U)\n#define HRTIM_CR2_TBRST_Msk           (0x1UL << HRTIM_CR2_TBRST_Pos)           /*!< 0x00000400 */\n#define HRTIM_CR2_TBRST               HRTIM_CR2_TBRST_Msk                      /*!< Timer B count software reset */\n#define HRTIM_CR2_TCRST_Pos           (11U)\n#define HRTIM_CR2_TCRST_Msk           (0x1UL << HRTIM_CR2_TCRST_Pos)           /*!< 0x00000800 */\n#define HRTIM_CR2_TCRST               HRTIM_CR2_TCRST_Msk                      /*!< Timer C count software reset */\n#define HRTIM_CR2_TDRST_Pos           (12U)\n#define HRTIM_CR2_TDRST_Msk           (0x1UL << HRTIM_CR2_TDRST_Pos)           /*!< 0x00001000 */\n#define HRTIM_CR2_TDRST               HRTIM_CR2_TDRST_Msk                      /*!< Timer D count software reset */\n#define HRTIM_CR2_TERST_Pos           (13U)\n#define HRTIM_CR2_TERST_Msk           (0x1UL << HRTIM_CR2_TERST_Pos)           /*!< 0x00002000 */\n#define HRTIM_CR2_TERST               HRTIM_CR2_TERST_Msk                      /*!< Timer E count software reset */\n\n/**** Bit definition for Common HRTIM Timer interrupt status register *********/\n#define HRTIM_ISR_FLT1_Pos            (0U)\n#define HRTIM_ISR_FLT1_Msk            (0x1UL << HRTIM_ISR_FLT1_Pos)            /*!< 0x00000001 */\n#define HRTIM_ISR_FLT1                HRTIM_ISR_FLT1_Msk                       /*!< Fault 1 interrupt flag */\n#define HRTIM_ISR_FLT2_Pos            (1U)\n#define HRTIM_ISR_FLT2_Msk            (0x1UL << HRTIM_ISR_FLT2_Pos)            /*!< 0x00000002 */\n#define HRTIM_ISR_FLT2                HRTIM_ISR_FLT2_Msk                       /*!< Fault 2 interrupt flag */\n#define HRTIM_ISR_FLT3_Pos            (2U)\n#define HRTIM_ISR_FLT3_Msk            (0x1UL << HRTIM_ISR_FLT3_Pos)            /*!< 0x00000004 */\n#define HRTIM_ISR_FLT3                HRTIM_ISR_FLT3_Msk                       /*!< Fault 3 interrupt flag */\n#define HRTIM_ISR_FLT4_Pos            (3U)\n#define HRTIM_ISR_FLT4_Msk            (0x1UL << HRTIM_ISR_FLT4_Pos)            /*!< 0x00000008 */\n#define HRTIM_ISR_FLT4                HRTIM_ISR_FLT4_Msk                       /*!< Fault 4 interrupt flag */\n#define HRTIM_ISR_FLT5_Pos            (4U)\n#define HRTIM_ISR_FLT5_Msk            (0x1UL << HRTIM_ISR_FLT5_Pos)            /*!< 0x00000010 */\n#define HRTIM_ISR_FLT5                HRTIM_ISR_FLT5_Msk                       /*!< Fault 5 interrupt flag */\n#define HRTIM_ISR_SYSFLT_Pos          (5U)\n#define HRTIM_ISR_SYSFLT_Msk          (0x1UL << HRTIM_ISR_SYSFLT_Pos)          /*!< 0x00000020 */\n#define HRTIM_ISR_SYSFLT              HRTIM_ISR_SYSFLT_Msk                     /*!< System Fault interrupt flag */\n#define HRTIM_ISR_BMPER_Pos           (17U)\n#define HRTIM_ISR_BMPER_Msk           (0x1UL << HRTIM_ISR_BMPER_Pos)           /*!< 0x00020000 */\n#define HRTIM_ISR_BMPER               HRTIM_ISR_BMPER_Msk                      /*!<  Burst mode period interrupt flag */\n\n/**** Bit definition for Common HRTIM Timer interrupt clear register **********/\n#define HRTIM_ICR_FLT1C_Pos           (0U)\n#define HRTIM_ICR_FLT1C_Msk           (0x1UL << HRTIM_ICR_FLT1C_Pos)           /*!< 0x00000001 */\n#define HRTIM_ICR_FLT1C               HRTIM_ICR_FLT1C_Msk                      /*!< Fault 1 interrupt flag clear */\n#define HRTIM_ICR_FLT2C_Pos           (1U)\n#define HRTIM_ICR_FLT2C_Msk           (0x1UL << HRTIM_ICR_FLT2C_Pos)           /*!< 0x00000002 */\n#define HRTIM_ICR_FLT2C               HRTIM_ICR_FLT2C_Msk                      /*!< Fault 2 interrupt flag clear */\n#define HRTIM_ICR_FLT3C_Pos           (2U)\n#define HRTIM_ICR_FLT3C_Msk           (0x1UL << HRTIM_ICR_FLT3C_Pos)           /*!< 0x00000004 */\n#define HRTIM_ICR_FLT3C               HRTIM_ICR_FLT3C_Msk                      /*!< Fault 3 interrupt flag clear */\n#define HRTIM_ICR_FLT4C_Pos           (3U)\n#define HRTIM_ICR_FLT4C_Msk           (0x1UL << HRTIM_ICR_FLT4C_Pos)           /*!< 0x00000008 */\n#define HRTIM_ICR_FLT4C               HRTIM_ICR_FLT4C_Msk                      /*!< Fault 4 interrupt flag clear */\n#define HRTIM_ICR_FLT5C_Pos           (4U)\n#define HRTIM_ICR_FLT5C_Msk           (0x1UL << HRTIM_ICR_FLT5C_Pos)           /*!< 0x00000010 */\n#define HRTIM_ICR_FLT5C               HRTIM_ICR_FLT5C_Msk                      /*!< Fault 5 interrupt flag clear */\n#define HRTIM_ICR_SYSFLTC_Pos         (5U)\n#define HRTIM_ICR_SYSFLTC_Msk         (0x1UL << HRTIM_ICR_SYSFLTC_Pos)         /*!< 0x00000020 */\n#define HRTIM_ICR_SYSFLTC             HRTIM_ICR_SYSFLTC_Msk                    /*!< System Fault interrupt flag clear */\n#define HRTIM_ICR_BMPERC_Pos          (17U)\n#define HRTIM_ICR_BMPERC_Msk          (0x1UL << HRTIM_ICR_BMPERC_Pos)          /*!< 0x00020000 */\n#define HRTIM_ICR_BMPERC              HRTIM_ICR_BMPERC_Msk                     /*!<  Burst mode period interrupt flag clear */\n\n/**** Bit definition for Common HRTIM Timer interrupt enable register *********/\n#define HRTIM_IER_FLT1_Pos            (0U)\n#define HRTIM_IER_FLT1_Msk            (0x1UL << HRTIM_IER_FLT1_Pos)            /*!< 0x00000001 */\n#define HRTIM_IER_FLT1                HRTIM_IER_FLT1_Msk                       /*!< Fault 1 interrupt enable */\n#define HRTIM_IER_FLT2_Pos            (1U)\n#define HRTIM_IER_FLT2_Msk            (0x1UL << HRTIM_IER_FLT2_Pos)            /*!< 0x00000002 */\n#define HRTIM_IER_FLT2                HRTIM_IER_FLT2_Msk                       /*!< Fault 2 interrupt enable */\n#define HRTIM_IER_FLT3_Pos            (2U)\n#define HRTIM_IER_FLT3_Msk            (0x1UL << HRTIM_IER_FLT3_Pos)            /*!< 0x00000004 */\n#define HRTIM_IER_FLT3                HRTIM_IER_FLT3_Msk                       /*!< Fault 3 interrupt enable */\n#define HRTIM_IER_FLT4_Pos            (3U)\n#define HRTIM_IER_FLT4_Msk            (0x1UL << HRTIM_IER_FLT4_Pos)            /*!< 0x00000008 */\n#define HRTIM_IER_FLT4                HRTIM_IER_FLT4_Msk                       /*!< Fault 4 interrupt enable */\n#define HRTIM_IER_FLT5_Pos            (4U)\n#define HRTIM_IER_FLT5_Msk            (0x1UL << HRTIM_IER_FLT5_Pos)            /*!< 0x00000010 */\n#define HRTIM_IER_FLT5                HRTIM_IER_FLT5_Msk                       /*!< Fault 5 interrupt enable */\n#define HRTIM_IER_SYSFLT_Pos          (5U)\n#define HRTIM_IER_SYSFLT_Msk          (0x1UL << HRTIM_IER_SYSFLT_Pos)          /*!< 0x00000020 */\n#define HRTIM_IER_SYSFLT              HRTIM_IER_SYSFLT_Msk                     /*!< System Fault interrupt enable */\n#define HRTIM_IER_BMPER_Pos           (17U)\n#define HRTIM_IER_BMPER_Msk           (0x1UL << HRTIM_IER_BMPER_Pos)           /*!< 0x00020000 */\n#define HRTIM_IER_BMPER               HRTIM_IER_BMPER_Msk                      /*!<  Burst mode period interrupt enable */\n\n/**** Bit definition for Common HRTIM Timer output enable register ************/\n#define HRTIM_OENR_TA1OEN_Pos         (0U)\n#define HRTIM_OENR_TA1OEN_Msk         (0x1UL << HRTIM_OENR_TA1OEN_Pos)         /*!< 0x00000001 */\n#define HRTIM_OENR_TA1OEN             HRTIM_OENR_TA1OEN_Msk                    /*!< Timer A Output 1 enable */\n#define HRTIM_OENR_TA2OEN_Pos         (1U)\n#define HRTIM_OENR_TA2OEN_Msk         (0x1UL << HRTIM_OENR_TA2OEN_Pos)         /*!< 0x00000002 */\n#define HRTIM_OENR_TA2OEN             HRTIM_OENR_TA2OEN_Msk                    /*!< Timer A Output 2 enable */\n#define HRTIM_OENR_TB1OEN_Pos         (2U)\n#define HRTIM_OENR_TB1OEN_Msk         (0x1UL << HRTIM_OENR_TB1OEN_Pos)         /*!< 0x00000004 */\n#define HRTIM_OENR_TB1OEN             HRTIM_OENR_TB1OEN_Msk                    /*!< Timer B Output 1 enable */\n#define HRTIM_OENR_TB2OEN_Pos         (3U)\n#define HRTIM_OENR_TB2OEN_Msk         (0x1UL << HRTIM_OENR_TB2OEN_Pos)         /*!< 0x00000008 */\n#define HRTIM_OENR_TB2OEN             HRTIM_OENR_TB2OEN_Msk                    /*!< Timer B Output 2 enable */\n#define HRTIM_OENR_TC1OEN_Pos         (4U)\n#define HRTIM_OENR_TC1OEN_Msk         (0x1UL << HRTIM_OENR_TC1OEN_Pos)         /*!< 0x00000010 */\n#define HRTIM_OENR_TC1OEN             HRTIM_OENR_TC1OEN_Msk                    /*!< Timer C Output 1 enable */\n#define HRTIM_OENR_TC2OEN_Pos         (5U)\n#define HRTIM_OENR_TC2OEN_Msk         (0x1UL << HRTIM_OENR_TC2OEN_Pos)         /*!< 0x00000020 */\n#define HRTIM_OENR_TC2OEN             HRTIM_OENR_TC2OEN_Msk                    /*!< Timer C Output 2 enable */\n#define HRTIM_OENR_TD1OEN_Pos         (6U)\n#define HRTIM_OENR_TD1OEN_Msk         (0x1UL << HRTIM_OENR_TD1OEN_Pos)         /*!< 0x00000040 */\n#define HRTIM_OENR_TD1OEN             HRTIM_OENR_TD1OEN_Msk                    /*!< Timer D Output 1 enable */\n#define HRTIM_OENR_TD2OEN_Pos         (7U)\n#define HRTIM_OENR_TD2OEN_Msk         (0x1UL << HRTIM_OENR_TD2OEN_Pos)         /*!< 0x00000080 */\n#define HRTIM_OENR_TD2OEN             HRTIM_OENR_TD2OEN_Msk                    /*!< Timer D Output 2 enable */\n#define HRTIM_OENR_TE1OEN_Pos         (8U)\n#define HRTIM_OENR_TE1OEN_Msk         (0x1UL << HRTIM_OENR_TE1OEN_Pos)         /*!< 0x00000100 */\n#define HRTIM_OENR_TE1OEN             HRTIM_OENR_TE1OEN_Msk                    /*!< Timer E Output 1 enable */\n#define HRTIM_OENR_TE2OEN_Pos         (9U)\n#define HRTIM_OENR_TE2OEN_Msk         (0x1UL << HRTIM_OENR_TE2OEN_Pos)         /*!< 0x00000200 */\n#define HRTIM_OENR_TE2OEN             HRTIM_OENR_TE2OEN_Msk                    /*!< Timer E Output 2 enable */\n\n/**** Bit definition for Common HRTIM Timer output disable register ***********/\n#define HRTIM_ODISR_TA1ODIS_Pos       (0U)\n#define HRTIM_ODISR_TA1ODIS_Msk       (0x1UL << HRTIM_ODISR_TA1ODIS_Pos)       /*!< 0x00000001 */\n#define HRTIM_ODISR_TA1ODIS           HRTIM_ODISR_TA1ODIS_Msk                  /*!< Timer A Output 1 disable */\n#define HRTIM_ODISR_TA2ODIS_Pos       (1U)\n#define HRTIM_ODISR_TA2ODIS_Msk       (0x1UL << HRTIM_ODISR_TA2ODIS_Pos)       /*!< 0x00000002 */\n#define HRTIM_ODISR_TA2ODIS           HRTIM_ODISR_TA2ODIS_Msk                  /*!< Timer A Output 2 disable */\n#define HRTIM_ODISR_TB1ODIS_Pos       (2U)\n#define HRTIM_ODISR_TB1ODIS_Msk       (0x1UL << HRTIM_ODISR_TB1ODIS_Pos)       /*!< 0x00000004 */\n#define HRTIM_ODISR_TB1ODIS           HRTIM_ODISR_TB1ODIS_Msk                  /*!< Timer B Output 1 disable */\n#define HRTIM_ODISR_TB2ODIS_Pos       (3U)\n#define HRTIM_ODISR_TB2ODIS_Msk       (0x1UL << HRTIM_ODISR_TB2ODIS_Pos)       /*!< 0x00000008 */\n#define HRTIM_ODISR_TB2ODIS           HRTIM_ODISR_TB2ODIS_Msk                  /*!< Timer B Output 2 disable */\n#define HRTIM_ODISR_TC1ODIS_Pos       (4U)\n#define HRTIM_ODISR_TC1ODIS_Msk       (0x1UL << HRTIM_ODISR_TC1ODIS_Pos)       /*!< 0x00000010 */\n#define HRTIM_ODISR_TC1ODIS           HRTIM_ODISR_TC1ODIS_Msk                  /*!< Timer C Output 1 disable */\n#define HRTIM_ODISR_TC2ODIS_Pos       (5U)\n#define HRTIM_ODISR_TC2ODIS_Msk       (0x1UL << HRTIM_ODISR_TC2ODIS_Pos)       /*!< 0x00000020 */\n#define HRTIM_ODISR_TC2ODIS           HRTIM_ODISR_TC2ODIS_Msk                  /*!< Timer C Output 2 disable */\n#define HRTIM_ODISR_TD1ODIS_Pos       (6U)\n#define HRTIM_ODISR_TD1ODIS_Msk       (0x1UL << HRTIM_ODISR_TD1ODIS_Pos)       /*!< 0x00000040 */\n#define HRTIM_ODISR_TD1ODIS           HRTIM_ODISR_TD1ODIS_Msk                  /*!< Timer D Output 1 disable */\n#define HRTIM_ODISR_TD2ODIS_Pos       (7U)\n#define HRTIM_ODISR_TD2ODIS_Msk       (0x1UL << HRTIM_ODISR_TD2ODIS_Pos)       /*!< 0x00000080 */\n#define HRTIM_ODISR_TD2ODIS           HRTIM_ODISR_TD2ODIS_Msk                  /*!< Timer D Output 2 disable */\n#define HRTIM_ODISR_TE1ODIS_Pos       (8U)\n#define HRTIM_ODISR_TE1ODIS_Msk       (0x1UL << HRTIM_ODISR_TE1ODIS_Pos)       /*!< 0x00000100 */\n#define HRTIM_ODISR_TE1ODIS           HRTIM_ODISR_TE1ODIS_Msk                  /*!< Timer E Output 1 disable */\n#define HRTIM_ODISR_TE2ODIS_Pos       (9U)\n#define HRTIM_ODISR_TE2ODIS_Msk       (0x1UL << HRTIM_ODISR_TE2ODIS_Pos)       /*!< 0x00000200 */\n#define HRTIM_ODISR_TE2ODIS           HRTIM_ODISR_TE2ODIS_Msk                  /*!< Timer E Output 2 disable */\n\n/**** Bit definition for Common HRTIM Timer output disable status register *****/\n#define HRTIM_ODSR_TA1ODS_Pos         (0U)\n#define HRTIM_ODSR_TA1ODS_Msk         (0x1UL << HRTIM_ODSR_TA1ODS_Pos)         /*!< 0x00000001 */\n#define HRTIM_ODSR_TA1ODS             HRTIM_ODSR_TA1ODS_Msk                    /*!< Timer A Output 1 disable status */\n#define HRTIM_ODSR_TA2ODS_Pos         (1U)\n#define HRTIM_ODSR_TA2ODS_Msk         (0x1UL << HRTIM_ODSR_TA2ODS_Pos)         /*!< 0x00000002 */\n#define HRTIM_ODSR_TA2ODS             HRTIM_ODSR_TA2ODS_Msk                    /*!< Timer A Output 2 disable status */\n#define HRTIM_ODSR_TB1ODS_Pos         (2U)\n#define HRTIM_ODSR_TB1ODS_Msk         (0x1UL << HRTIM_ODSR_TB1ODS_Pos)         /*!< 0x00000004 */\n#define HRTIM_ODSR_TB1ODS             HRTIM_ODSR_TB1ODS_Msk                    /*!< Timer B Output 1 disable status */\n#define HRTIM_ODSR_TB2ODS_Pos         (3U)\n#define HRTIM_ODSR_TB2ODS_Msk         (0x1UL << HRTIM_ODSR_TB2ODS_Pos)         /*!< 0x00000008 */\n#define HRTIM_ODSR_TB2ODS             HRTIM_ODSR_TB2ODS_Msk                    /*!< Timer B Output 2 disable status */\n#define HRTIM_ODSR_TC1ODS_Pos         (4U)\n#define HRTIM_ODSR_TC1ODS_Msk         (0x1UL << HRTIM_ODSR_TC1ODS_Pos)         /*!< 0x00000010 */\n#define HRTIM_ODSR_TC1ODS             HRTIM_ODSR_TC1ODS_Msk                    /*!< Timer C Output 1 disable status */\n#define HRTIM_ODSR_TC2ODS_Pos         (5U)\n#define HRTIM_ODSR_TC2ODS_Msk         (0x1UL << HRTIM_ODSR_TC2ODS_Pos)         /*!< 0x00000020 */\n#define HRTIM_ODSR_TC2ODS             HRTIM_ODSR_TC2ODS_Msk                    /*!< Timer C Output 2 disable status */\n#define HRTIM_ODSR_TD1ODS_Pos         (6U)\n#define HRTIM_ODSR_TD1ODS_Msk         (0x1UL << HRTIM_ODSR_TD1ODS_Pos)         /*!< 0x00000040 */\n#define HRTIM_ODSR_TD1ODS             HRTIM_ODSR_TD1ODS_Msk                    /*!< Timer D Output 1 disable status */\n#define HRTIM_ODSR_TD2ODS_Pos         (7U)\n#define HRTIM_ODSR_TD2ODS_Msk         (0x1UL << HRTIM_ODSR_TD2ODS_Pos)         /*!< 0x00000080 */\n#define HRTIM_ODSR_TD2ODS             HRTIM_ODSR_TD2ODS_Msk                    /*!< Timer D Output 2 disable status */\n#define HRTIM_ODSR_TE1ODS_Pos         (8U)\n#define HRTIM_ODSR_TE1ODS_Msk         (0x1UL << HRTIM_ODSR_TE1ODS_Pos)         /*!< 0x00000100 */\n#define HRTIM_ODSR_TE1ODS             HRTIM_ODSR_TE1ODS_Msk                    /*!< Timer E Output 1 disable status */\n#define HRTIM_ODSR_TE2ODS_Pos         (9U)\n#define HRTIM_ODSR_TE2ODS_Msk         (0x1UL << HRTIM_ODSR_TE2ODS_Pos)         /*!< 0x00000200 */\n#define HRTIM_ODSR_TE2ODS             HRTIM_ODSR_TE2ODS_Msk                    /*!< Timer E Output 2 disable status */\n\n/**** Bit definition for Common HRTIM Timer Burst mode control register ********/\n#define HRTIM_BMCR_BME_Pos            (0U)\n#define HRTIM_BMCR_BME_Msk            (0x1UL << HRTIM_BMCR_BME_Pos)            /*!< 0x00000001 */\n#define HRTIM_BMCR_BME                HRTIM_BMCR_BME_Msk                       /*!< Burst mode enable */\n#define HRTIM_BMCR_BMOM_Pos           (1U)\n#define HRTIM_BMCR_BMOM_Msk           (0x1UL << HRTIM_BMCR_BMOM_Pos)           /*!< 0x00000002 */\n#define HRTIM_BMCR_BMOM               HRTIM_BMCR_BMOM_Msk                      /*!< Burst mode operating mode */\n#define HRTIM_BMCR_BMCLK_Pos          (2U)\n#define HRTIM_BMCR_BMCLK_Msk          (0xFUL << HRTIM_BMCR_BMCLK_Pos)          /*!< 0x0000003C */\n#define HRTIM_BMCR_BMCLK              HRTIM_BMCR_BMCLK_Msk                     /*!< Burst mode clock source */\n#define HRTIM_BMCR_BMCLK_0            (0x1UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000004 */\n#define HRTIM_BMCR_BMCLK_1            (0x2UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000008 */\n#define HRTIM_BMCR_BMCLK_2            (0x4UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000010 */\n#define HRTIM_BMCR_BMCLK_3            (0x8UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000020 */\n#define HRTIM_BMCR_BMPRSC_Pos         (6U)\n#define HRTIM_BMCR_BMPRSC_Msk         (0xFUL << HRTIM_BMCR_BMPRSC_Pos)         /*!< 0x000003C0 */\n#define HRTIM_BMCR_BMPRSC             HRTIM_BMCR_BMPRSC_Msk                    /*!< Burst mode prescaler */\n#define HRTIM_BMCR_BMPRSC_0           (0x1UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000040 */\n#define HRTIM_BMCR_BMPRSC_1           (0x2UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000080 */\n#define HRTIM_BMCR_BMPRSC_2           (0x4UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000100 */\n#define HRTIM_BMCR_BMPRSC_3           (0x8UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000200 */\n#define HRTIM_BMCR_BMPREN_Pos         (10U)\n#define HRTIM_BMCR_BMPREN_Msk         (0x1UL << HRTIM_BMCR_BMPREN_Pos)         /*!< 0x00000400 */\n#define HRTIM_BMCR_BMPREN             HRTIM_BMCR_BMPREN_Msk                    /*!< Burst mode Preload bit */\n#define HRTIM_BMCR_MTBM_Pos           (16U)\n#define HRTIM_BMCR_MTBM_Msk           (0x1UL << HRTIM_BMCR_MTBM_Pos)           /*!< 0x00010000 */\n#define HRTIM_BMCR_MTBM               HRTIM_BMCR_MTBM_Msk                      /*!< Master Timer Burst mode */\n#define HRTIM_BMCR_TABM_Pos           (17U)\n#define HRTIM_BMCR_TABM_Msk           (0x1UL << HRTIM_BMCR_TABM_Pos)           /*!< 0x00020000 */\n#define HRTIM_BMCR_TABM               HRTIM_BMCR_TABM_Msk                      /*!< Timer A Burst mode */\n#define HRTIM_BMCR_TBBM_Pos           (18U)\n#define HRTIM_BMCR_TBBM_Msk           (0x1UL << HRTIM_BMCR_TBBM_Pos)           /*!< 0x00040000 */\n#define HRTIM_BMCR_TBBM               HRTIM_BMCR_TBBM_Msk                      /*!< Timer B Burst mode */\n#define HRTIM_BMCR_TCBM_Pos           (19U)\n#define HRTIM_BMCR_TCBM_Msk           (0x1UL << HRTIM_BMCR_TCBM_Pos)           /*!< 0x00080000 */\n#define HRTIM_BMCR_TCBM               HRTIM_BMCR_TCBM_Msk                      /*!< Timer C Burst mode */\n#define HRTIM_BMCR_TDBM_Pos           (20U)\n#define HRTIM_BMCR_TDBM_Msk           (0x1UL << HRTIM_BMCR_TDBM_Pos)           /*!< 0x00100000 */\n#define HRTIM_BMCR_TDBM               HRTIM_BMCR_TDBM_Msk                      /*!< Timer D Burst mode */\n#define HRTIM_BMCR_TEBM_Pos           (21U)\n#define HRTIM_BMCR_TEBM_Msk           (0x1UL << HRTIM_BMCR_TEBM_Pos)           /*!< 0x00200000 */\n#define HRTIM_BMCR_TEBM               HRTIM_BMCR_TEBM_Msk                      /*!< Timer E Burst mode */\n#define HRTIM_BMCR_BMSTAT_Pos         (31U)\n#define HRTIM_BMCR_BMSTAT_Msk         (0x1UL << HRTIM_BMCR_BMSTAT_Pos)         /*!< 0x80000000 */\n#define HRTIM_BMCR_BMSTAT             HRTIM_BMCR_BMSTAT_Msk                    /*!< Burst mode status */\n\n/**** Bit definition for Common HRTIM Timer Burst mode Trigger register *******/\n#define HRTIM_BMTRGR_SW_Pos           (0U)\n#define HRTIM_BMTRGR_SW_Msk           (0x1UL << HRTIM_BMTRGR_SW_Pos)           /*!< 0x00000001 */\n#define HRTIM_BMTRGR_SW               HRTIM_BMTRGR_SW_Msk                      /*!< Software start */\n#define HRTIM_BMTRGR_MSTRST_Pos       (1U)\n#define HRTIM_BMTRGR_MSTRST_Msk       (0x1UL << HRTIM_BMTRGR_MSTRST_Pos)       /*!< 0x00000002 */\n#define HRTIM_BMTRGR_MSTRST           HRTIM_BMTRGR_MSTRST_Msk                  /*!<  Master reset */\n#define HRTIM_BMTRGR_MSTREP_Pos       (2U)\n#define HRTIM_BMTRGR_MSTREP_Msk       (0x1UL << HRTIM_BMTRGR_MSTREP_Pos)       /*!< 0x00000004 */\n#define HRTIM_BMTRGR_MSTREP           HRTIM_BMTRGR_MSTREP_Msk                  /*!<  Master repetition */\n#define HRTIM_BMTRGR_MSTCMP1_Pos      (3U)\n#define HRTIM_BMTRGR_MSTCMP1_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP1_Pos)      /*!< 0x00000008 */\n#define HRTIM_BMTRGR_MSTCMP1          HRTIM_BMTRGR_MSTCMP1_Msk                 /*!<  Master compare 1 */\n#define HRTIM_BMTRGR_MSTCMP2_Pos      (4U)\n#define HRTIM_BMTRGR_MSTCMP2_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP2_Pos)      /*!< 0x00000010 */\n#define HRTIM_BMTRGR_MSTCMP2          HRTIM_BMTRGR_MSTCMP2_Msk                 /*!< Master compare 2  */\n#define HRTIM_BMTRGR_MSTCMP3_Pos      (5U)\n#define HRTIM_BMTRGR_MSTCMP3_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP3_Pos)      /*!< 0x00000020 */\n#define HRTIM_BMTRGR_MSTCMP3          HRTIM_BMTRGR_MSTCMP3_Msk                 /*!< Master compare 3 */\n#define HRTIM_BMTRGR_MSTCMP4_Pos      (6U)\n#define HRTIM_BMTRGR_MSTCMP4_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP4_Pos)      /*!< 0x00000040 */\n#define HRTIM_BMTRGR_MSTCMP4          HRTIM_BMTRGR_MSTCMP4_Msk                 /*!< Master compare 4 */\n#define HRTIM_BMTRGR_TARST_Pos        (7U)\n#define HRTIM_BMTRGR_TARST_Msk        (0x1UL << HRTIM_BMTRGR_TARST_Pos)        /*!< 0x00000080 */\n#define HRTIM_BMTRGR_TARST            HRTIM_BMTRGR_TARST_Msk                   /*!< Timer A reset  */\n#define HRTIM_BMTRGR_TAREP_Pos        (8U)\n#define HRTIM_BMTRGR_TAREP_Msk        (0x1UL << HRTIM_BMTRGR_TAREP_Pos)        /*!< 0x00000100 */\n#define HRTIM_BMTRGR_TAREP            HRTIM_BMTRGR_TAREP_Msk                   /*!< Timer A repetition  */\n#define HRTIM_BMTRGR_TACMP1_Pos       (9U)\n#define HRTIM_BMTRGR_TACMP1_Msk       (0x1UL << HRTIM_BMTRGR_TACMP1_Pos)       /*!< 0x00000200 */\n#define HRTIM_BMTRGR_TACMP1           HRTIM_BMTRGR_TACMP1_Msk                  /*!< Timer A compare 1  */\n#define HRTIM_BMTRGR_TACMP2_Pos       (10U)\n#define HRTIM_BMTRGR_TACMP2_Msk       (0x1UL << HRTIM_BMTRGR_TACMP2_Pos)       /*!< 0x00000400 */\n#define HRTIM_BMTRGR_TACMP2           HRTIM_BMTRGR_TACMP2_Msk                  /*!< Timer A compare 2  */\n#define HRTIM_BMTRGR_TBRST_Pos        (11U)\n#define HRTIM_BMTRGR_TBRST_Msk        (0x1UL << HRTIM_BMTRGR_TBRST_Pos)        /*!< 0x00000800 */\n#define HRTIM_BMTRGR_TBRST            HRTIM_BMTRGR_TBRST_Msk                   /*!< Timer B reset  */\n#define HRTIM_BMTRGR_TBREP_Pos        (12U)\n#define HRTIM_BMTRGR_TBREP_Msk        (0x1UL << HRTIM_BMTRGR_TBREP_Pos)        /*!< 0x00001000 */\n#define HRTIM_BMTRGR_TBREP            HRTIM_BMTRGR_TBREP_Msk                   /*!< Timer B repetition  */\n#define HRTIM_BMTRGR_TBCMP1_Pos       (13U)\n#define HRTIM_BMTRGR_TBCMP1_Msk       (0x1UL << HRTIM_BMTRGR_TBCMP1_Pos)       /*!< 0x00002000 */\n#define HRTIM_BMTRGR_TBCMP1           HRTIM_BMTRGR_TBCMP1_Msk                  /*!< Timer B compare 1 */\n#define HRTIM_BMTRGR_TBCMP2_Pos       (14U)\n#define HRTIM_BMTRGR_TBCMP2_Msk       (0x1UL << HRTIM_BMTRGR_TBCMP2_Pos)       /*!< 0x00004000 */\n#define HRTIM_BMTRGR_TBCMP2           HRTIM_BMTRGR_TBCMP2_Msk                  /*!< Timer B compare 2 */\n#define HRTIM_BMTRGR_TCRST_Pos        (15U)\n#define HRTIM_BMTRGR_TCRST_Msk        (0x1UL << HRTIM_BMTRGR_TCRST_Pos)        /*!< 0x00008000 */\n#define HRTIM_BMTRGR_TCRST            HRTIM_BMTRGR_TCRST_Msk                   /*!< Timer C reset  */\n#define HRTIM_BMTRGR_TCREP_Pos        (16U)\n#define HRTIM_BMTRGR_TCREP_Msk        (0x1UL << HRTIM_BMTRGR_TCREP_Pos)        /*!< 0x00010000 */\n#define HRTIM_BMTRGR_TCREP            HRTIM_BMTRGR_TCREP_Msk                   /*!< Timer C repetition */\n#define HRTIM_BMTRGR_TCCMP1_Pos       (17U)\n#define HRTIM_BMTRGR_TCCMP1_Msk       (0x1UL << HRTIM_BMTRGR_TCCMP1_Pos)       /*!< 0x00020000 */\n#define HRTIM_BMTRGR_TCCMP1           HRTIM_BMTRGR_TCCMP1_Msk                  /*!< Timer C compare 1 */\n#define HRTIM_BMTRGR_TCCMP2_Pos       (18U)\n#define HRTIM_BMTRGR_TCCMP2_Msk       (0x1UL << HRTIM_BMTRGR_TCCMP2_Pos)       /*!< 0x00040000 */\n#define HRTIM_BMTRGR_TCCMP2           HRTIM_BMTRGR_TCCMP2_Msk                  /*!< Timer C compare 2 */\n#define HRTIM_BMTRGR_TDRST_Pos        (19U)\n#define HRTIM_BMTRGR_TDRST_Msk        (0x1UL << HRTIM_BMTRGR_TDRST_Pos)        /*!< 0x00080000 */\n#define HRTIM_BMTRGR_TDRST            HRTIM_BMTRGR_TDRST_Msk                   /*!< Timer D reset  */\n#define HRTIM_BMTRGR_TDREP_Pos        (20U)\n#define HRTIM_BMTRGR_TDREP_Msk        (0x1UL << HRTIM_BMTRGR_TDREP_Pos)        /*!< 0x00100000 */\n#define HRTIM_BMTRGR_TDREP            HRTIM_BMTRGR_TDREP_Msk                   /*!< Timer D repetition  */\n#define HRTIM_BMTRGR_TDCMP1_Pos       (21U)\n#define HRTIM_BMTRGR_TDCMP1_Msk       (0x1UL << HRTIM_BMTRGR_TDCMP1_Pos)       /*!< 0x00200000 */\n#define HRTIM_BMTRGR_TDCMP1           HRTIM_BMTRGR_TDCMP1_Msk                  /*!< Timer D compare 1 */\n#define HRTIM_BMTRGR_TDCMP2_Pos       (22U)\n#define HRTIM_BMTRGR_TDCMP2_Msk       (0x1UL << HRTIM_BMTRGR_TDCMP2_Pos)       /*!< 0x00400000 */\n#define HRTIM_BMTRGR_TDCMP2           HRTIM_BMTRGR_TDCMP2_Msk                  /*!< Timer D compare 2 */\n#define HRTIM_BMTRGR_TERST_Pos        (23U)\n#define HRTIM_BMTRGR_TERST_Msk        (0x1UL << HRTIM_BMTRGR_TERST_Pos)        /*!< 0x00800000 */\n#define HRTIM_BMTRGR_TERST            HRTIM_BMTRGR_TERST_Msk                   /*!< Timer E reset  */\n#define HRTIM_BMTRGR_TEREP_Pos        (24U)\n#define HRTIM_BMTRGR_TEREP_Msk        (0x1UL << HRTIM_BMTRGR_TEREP_Pos)        /*!< 0x01000000 */\n#define HRTIM_BMTRGR_TEREP            HRTIM_BMTRGR_TEREP_Msk                   /*!< Timer E repetition  */\n#define HRTIM_BMTRGR_TECMP1_Pos       (25U)\n#define HRTIM_BMTRGR_TECMP1_Msk       (0x1UL << HRTIM_BMTRGR_TECMP1_Pos)       /*!< 0x02000000 */\n#define HRTIM_BMTRGR_TECMP1           HRTIM_BMTRGR_TECMP1_Msk                  /*!< Timer E compare 1 */\n#define HRTIM_BMTRGR_TECMP2_Pos       (26U)\n#define HRTIM_BMTRGR_TECMP2_Msk       (0x1UL << HRTIM_BMTRGR_TECMP2_Pos)       /*!< 0x04000000 */\n#define HRTIM_BMTRGR_TECMP2           HRTIM_BMTRGR_TECMP2_Msk                  /*!< Timer E compare 2 */\n#define HRTIM_BMTRGR_TAEEV7_Pos       (27U)\n#define HRTIM_BMTRGR_TAEEV7_Msk       (0x1UL << HRTIM_BMTRGR_TAEEV7_Pos)       /*!< 0x08000000 */\n#define HRTIM_BMTRGR_TAEEV7           HRTIM_BMTRGR_TAEEV7_Msk                  /*!< Timer A period following External Event7  */\n#define HRTIM_BMTRGR_TDEEV8_Pos       (28U)\n#define HRTIM_BMTRGR_TDEEV8_Msk       (0x1UL << HRTIM_BMTRGR_TDEEV8_Pos)       /*!< 0x10000000 */\n#define HRTIM_BMTRGR_TDEEV8           HRTIM_BMTRGR_TDEEV8_Msk                  /*!< Timer D period following External Event8  */\n#define HRTIM_BMTRGR_EEV7_Pos         (29U)\n#define HRTIM_BMTRGR_EEV7_Msk         (0x1UL << HRTIM_BMTRGR_EEV7_Pos)         /*!< 0x20000000 */\n#define HRTIM_BMTRGR_EEV7             HRTIM_BMTRGR_EEV7_Msk                    /*!< External Event 7 */\n#define HRTIM_BMTRGR_EEV8_Pos         (30U)\n#define HRTIM_BMTRGR_EEV8_Msk         (0x1UL << HRTIM_BMTRGR_EEV8_Pos)         /*!< 0x40000000 */\n#define HRTIM_BMTRGR_EEV8             HRTIM_BMTRGR_EEV8_Msk                    /*!< External Event 8 */\n#define HRTIM_BMTRGR_OCHPEV_Pos       (31U)\n#define HRTIM_BMTRGR_OCHPEV_Msk       (0x1UL << HRTIM_BMTRGR_OCHPEV_Pos)       /*!< 0x80000000 */\n#define HRTIM_BMTRGR_OCHPEV           HRTIM_BMTRGR_OCHPEV_Msk                  /*!< on-chip Event */\n\n/*******************  Bit definition for HRTIM_BMCMPR register  ***************/\n#define HRTIM_BMCMPR_BMCMPR_Pos       (0U)\n#define HRTIM_BMCMPR_BMCMPR_Msk       (0xFFFFUL << HRTIM_BMCMPR_BMCMPR_Pos)    /*!< 0x0000FFFF */\n#define HRTIM_BMCMPR_BMCMPR           HRTIM_BMCMPR_BMCMPR_Msk                  /*!<!<Burst Compare Value */\n\n/*******************  Bit definition for HRTIM_BMPER register  ****************/\n#define HRTIM_BMPER_BMPER_Pos         (0U)\n#define HRTIM_BMPER_BMPER_Msk         (0xFFFFUL << HRTIM_BMPER_BMPER_Pos)      /*!< 0x0000FFFF */\n#define HRTIM_BMPER_BMPER             HRTIM_BMPER_BMPER_Msk                    /*!<!<Burst period Value */\n\n/*******************  Bit definition for HRTIM_EECR1 register  ****************/\n#define HRTIM_EECR1_EE1SRC_Pos        (0U)\n#define HRTIM_EECR1_EE1SRC_Msk        (0x3UL << HRTIM_EECR1_EE1SRC_Pos)        /*!< 0x00000003 */\n#define HRTIM_EECR1_EE1SRC            HRTIM_EECR1_EE1SRC_Msk                   /*!< External event 1 source */\n#define HRTIM_EECR1_EE1SRC_0          (0x1UL << HRTIM_EECR1_EE1SRC_Pos)         /*!< 0x00000001 */\n#define HRTIM_EECR1_EE1SRC_1          (0x2UL << HRTIM_EECR1_EE1SRC_Pos)         /*!< 0x00000002 */\n#define HRTIM_EECR1_EE1POL_Pos        (2U)\n#define HRTIM_EECR1_EE1POL_Msk        (0x1UL << HRTIM_EECR1_EE1POL_Pos)        /*!< 0x00000004 */\n#define HRTIM_EECR1_EE1POL            HRTIM_EECR1_EE1POL_Msk                   /*!< External event 1 Polarity */\n#define HRTIM_EECR1_EE1SNS_Pos        (3U)\n#define HRTIM_EECR1_EE1SNS_Msk        (0x3UL << HRTIM_EECR1_EE1SNS_Pos)        /*!< 0x00000018 */\n#define HRTIM_EECR1_EE1SNS            HRTIM_EECR1_EE1SNS_Msk                   /*!< External event 1 sensitivity */\n#define HRTIM_EECR1_EE1SNS_0          (0x1UL << HRTIM_EECR1_EE1SNS_Pos)         /*!< 0x00000008 */\n#define HRTIM_EECR1_EE1SNS_1          (0x2UL << HRTIM_EECR1_EE1SNS_Pos)         /*!< 0x00000010 */\n#define HRTIM_EECR1_EE1FAST_Pos       (5U)\n#define HRTIM_EECR1_EE1FAST_Msk       (0x1UL << HRTIM_EECR1_EE1FAST_Pos)       /*!< 0x00000020 */\n#define HRTIM_EECR1_EE1FAST           HRTIM_EECR1_EE1FAST_Msk                  /*!< External event 1 Fast mode */\n\n#define HRTIM_EECR1_EE2SRC_Pos        (6U)\n#define HRTIM_EECR1_EE2SRC_Msk        (0x3UL << HRTIM_EECR1_EE2SRC_Pos)        /*!< 0x000000C0 */\n#define HRTIM_EECR1_EE2SRC            HRTIM_EECR1_EE2SRC_Msk                   /*!< External event 2 source */\n#define HRTIM_EECR1_EE2SRC_0          (0x1UL << HRTIM_EECR1_EE2SRC_Pos)         /*!< 0x00000040 */\n#define HRTIM_EECR1_EE2SRC_1          (0x2UL << HRTIM_EECR1_EE2SRC_Pos)         /*!< 0x00000080 */\n#define HRTIM_EECR1_EE2POL_Pos        (8U)\n#define HRTIM_EECR1_EE2POL_Msk        (0x1UL << HRTIM_EECR1_EE2POL_Pos)        /*!< 0x00000100 */\n#define HRTIM_EECR1_EE2POL            HRTIM_EECR1_EE2POL_Msk                   /*!< External event 2 Polarity */\n#define HRTIM_EECR1_EE2SNS_Pos        (9U)\n#define HRTIM_EECR1_EE2SNS_Msk        (0x3UL << HRTIM_EECR1_EE2SNS_Pos)        /*!< 0x00000600 */\n#define HRTIM_EECR1_EE2SNS            HRTIM_EECR1_EE2SNS_Msk                   /*!< External event 2 sensitivity */\n#define HRTIM_EECR1_EE2SNS_0          (0x1UL << HRTIM_EECR1_EE2SNS_Pos)         /*!< 0x00000200 */\n#define HRTIM_EECR1_EE2SNS_1          (0x2UL << HRTIM_EECR1_EE2SNS_Pos)         /*!< 0x00000400 */\n#define HRTIM_EECR1_EE2FAST_Pos       (11U)\n#define HRTIM_EECR1_EE2FAST_Msk       (0x1UL << HRTIM_EECR1_EE2FAST_Pos)       /*!< 0x00000800 */\n#define HRTIM_EECR1_EE2FAST           HRTIM_EECR1_EE2FAST_Msk                  /*!< External event 2 Fast mode */\n\n#define HRTIM_EECR1_EE3SRC_Pos        (12U)\n#define HRTIM_EECR1_EE3SRC_Msk        (0x3UL << HRTIM_EECR1_EE3SRC_Pos)        /*!< 0x00003000 */\n#define HRTIM_EECR1_EE3SRC            HRTIM_EECR1_EE3SRC_Msk                   /*!< External event 3 source */\n#define HRTIM_EECR1_EE3SRC_0          (0x1UL << HRTIM_EECR1_EE3SRC_Pos)         /*!< 0x00001000 */\n#define HRTIM_EECR1_EE3SRC_1          (0x2UL << HRTIM_EECR1_EE3SRC_Pos)         /*!< 0x00002000 */\n#define HRTIM_EECR1_EE3POL_Pos        (14U)\n#define HRTIM_EECR1_EE3POL_Msk        (0x1UL << HRTIM_EECR1_EE3POL_Pos)        /*!< 0x00004000 */\n#define HRTIM_EECR1_EE3POL            HRTIM_EECR1_EE3POL_Msk                   /*!< External event 3 Polarity */\n#define HRTIM_EECR1_EE3SNS_Pos        (15U)\n#define HRTIM_EECR1_EE3SNS_Msk        (0x3UL << HRTIM_EECR1_EE3SNS_Pos)        /*!< 0x00018000 */\n#define HRTIM_EECR1_EE3SNS            HRTIM_EECR1_EE3SNS_Msk                   /*!< External event 3 sensitivity */\n#define HRTIM_EECR1_EE3SNS_0          (0x1UL << HRTIM_EECR1_EE3SNS_Pos)         /*!< 0x00008000 */\n#define HRTIM_EECR1_EE3SNS_1          (0x2UL << HRTIM_EECR1_EE3SNS_Pos)         /*!< 0x00010000 */\n#define HRTIM_EECR1_EE3FAST_Pos       (17U)\n#define HRTIM_EECR1_EE3FAST_Msk       (0x1UL << HRTIM_EECR1_EE3FAST_Pos)       /*!< 0x00020000 */\n#define HRTIM_EECR1_EE3FAST           HRTIM_EECR1_EE3FAST_Msk                  /*!< External event 3 Fast mode */\n\n#define HRTIM_EECR1_EE4SRC_Pos        (18U)\n#define HRTIM_EECR1_EE4SRC_Msk        (0x3UL << HRTIM_EECR1_EE4SRC_Pos)        /*!< 0x000C0000 */\n#define HRTIM_EECR1_EE4SRC            HRTIM_EECR1_EE4SRC_Msk                   /*!< External event 4 source */\n#define HRTIM_EECR1_EE4SRC_0          (0x1UL << HRTIM_EECR1_EE4SRC_Pos)         /*!< 0x00040000 */\n#define HRTIM_EECR1_EE4SRC_1          (0x2UL << HRTIM_EECR1_EE4SRC_Pos)         /*!< 0x00080000 */\n#define HRTIM_EECR1_EE4POL_Pos        (20U)\n#define HRTIM_EECR1_EE4POL_Msk        (0x1UL << HRTIM_EECR1_EE4POL_Pos)        /*!< 0x00100000 */\n#define HRTIM_EECR1_EE4POL            HRTIM_EECR1_EE4POL_Msk                   /*!< External event 4 Polarity */\n#define HRTIM_EECR1_EE4SNS_Pos        (21U)\n#define HRTIM_EECR1_EE4SNS_Msk        (0x3UL << HRTIM_EECR1_EE4SNS_Pos)        /*!< 0x00600000 */\n#define HRTIM_EECR1_EE4SNS            HRTIM_EECR1_EE4SNS_Msk                   /*!< External event 4 sensitivity */\n#define HRTIM_EECR1_EE4SNS_0          (0x1UL << HRTIM_EECR1_EE4SNS_Pos)         /*!< 0x00200000 */\n#define HRTIM_EECR1_EE4SNS_1          (0x2UL << HRTIM_EECR1_EE4SNS_Pos)         /*!< 0x00400000 */\n#define HRTIM_EECR1_EE4FAST_Pos       (23U)\n#define HRTIM_EECR1_EE4FAST_Msk       (0x1UL << HRTIM_EECR1_EE4FAST_Pos)       /*!< 0x00800000 */\n#define HRTIM_EECR1_EE4FAST           HRTIM_EECR1_EE4FAST_Msk                  /*!< External event 4 Fast mode */\n\n#define HRTIM_EECR1_EE5SRC_Pos        (24U)\n#define HRTIM_EECR1_EE5SRC_Msk        (0x3UL << HRTIM_EECR1_EE5SRC_Pos)        /*!< 0x03000000 */\n#define HRTIM_EECR1_EE5SRC            HRTIM_EECR1_EE5SRC_Msk                   /*!< External event 5 source */\n#define HRTIM_EECR1_EE5SRC_0          (0x1UL << HRTIM_EECR1_EE5SRC_Pos)         /*!< 0x01000000 */\n#define HRTIM_EECR1_EE5SRC_1          (0x2UL << HRTIM_EECR1_EE5SRC_Pos)         /*!< 0x02000000 */\n#define HRTIM_EECR1_EE5POL_Pos        (26U)\n#define HRTIM_EECR1_EE5POL_Msk        (0x1UL << HRTIM_EECR1_EE5POL_Pos)        /*!< 0x04000000 */\n#define HRTIM_EECR1_EE5POL            HRTIM_EECR1_EE5POL_Msk                   /*!< External event 5 Polarity */\n#define HRTIM_EECR1_EE5SNS_Pos        (27U)\n#define HRTIM_EECR1_EE5SNS_Msk        (0x3UL << HRTIM_EECR1_EE5SNS_Pos)        /*!< 0x18000000 */\n#define HRTIM_EECR1_EE5SNS            HRTIM_EECR1_EE5SNS_Msk                   /*!< External event 5 sensitivity */\n#define HRTIM_EECR1_EE5SNS_0          (0x1UL << HRTIM_EECR1_EE5SNS_Pos)         /*!< 0x08000000 */\n#define HRTIM_EECR1_EE5SNS_1          (0x2UL << HRTIM_EECR1_EE5SNS_Pos)         /*!< 0x10000000 */\n#define HRTIM_EECR1_EE5FAST_Pos       (29U)\n#define HRTIM_EECR1_EE5FAST_Msk       (0x1UL << HRTIM_EECR1_EE5FAST_Pos)       /*!< 0x20000000 */\n#define HRTIM_EECR1_EE5FAST           HRTIM_EECR1_EE5FAST_Msk                  /*!< External event 5 Fast mode */\n\n/*******************  Bit definition for HRTIM_EECR2 register  ****************/\n#define HRTIM_EECR2_EE6SRC_Pos        (0U)\n#define HRTIM_EECR2_EE6SRC_Msk        (0x3UL << HRTIM_EECR2_EE6SRC_Pos)        /*!< 0x00000003 */\n#define HRTIM_EECR2_EE6SRC            HRTIM_EECR2_EE6SRC_Msk                   /*!< External event 6 source */\n#define HRTIM_EECR2_EE6SRC_0          (0x1UL << HRTIM_EECR2_EE6SRC_Pos)         /*!< 0x00000001 */\n#define HRTIM_EECR2_EE6SRC_1          (0x2UL << HRTIM_EECR2_EE6SRC_Pos)         /*!< 0x00000002 */\n#define HRTIM_EECR2_EE6POL_Pos        (2U)\n#define HRTIM_EECR2_EE6POL_Msk        (0x1UL << HRTIM_EECR2_EE6POL_Pos)        /*!< 0x00000004 */\n#define HRTIM_EECR2_EE6POL            HRTIM_EECR2_EE6POL_Msk                   /*!< External event 6 Polarity */\n#define HRTIM_EECR2_EE6SNS_Pos        (3U)\n#define HRTIM_EECR2_EE6SNS_Msk        (0x3UL << HRTIM_EECR2_EE6SNS_Pos)        /*!< 0x00000018 */\n#define HRTIM_EECR2_EE6SNS            HRTIM_EECR2_EE6SNS_Msk                   /*!< External event 6 sensitivity */\n#define HRTIM_EECR2_EE6SNS_0          (0x1UL << HRTIM_EECR2_EE6SNS_Pos)         /*!< 0x00000008 */\n#define HRTIM_EECR2_EE6SNS_1          (0x2UL << HRTIM_EECR2_EE6SNS_Pos)         /*!< 0x00000010 */\n\n#define HRTIM_EECR2_EE7SRC_Pos        (6U)\n#define HRTIM_EECR2_EE7SRC_Msk        (0x3UL << HRTIM_EECR2_EE7SRC_Pos)        /*!< 0x000000C0 */\n#define HRTIM_EECR2_EE7SRC            HRTIM_EECR2_EE7SRC_Msk                   /*!< External event 7 source */\n#define HRTIM_EECR2_EE7SRC_0          (0x1UL << HRTIM_EECR2_EE7SRC_Pos)         /*!< 0x00000040 */\n#define HRTIM_EECR2_EE7SRC_1          (0x2UL << HRTIM_EECR2_EE7SRC_Pos)         /*!< 0x00000080 */\n#define HRTIM_EECR2_EE7POL_Pos        (8U)\n#define HRTIM_EECR2_EE7POL_Msk        (0x1UL << HRTIM_EECR2_EE7POL_Pos)        /*!< 0x00000100 */\n#define HRTIM_EECR2_EE7POL            HRTIM_EECR2_EE7POL_Msk                   /*!< External event 7 Polarity */\n#define HRTIM_EECR2_EE7SNS_Pos        (9U)\n#define HRTIM_EECR2_EE7SNS_Msk        (0x3UL << HRTIM_EECR2_EE7SNS_Pos)        /*!< 0x00000600 */\n#define HRTIM_EECR2_EE7SNS            HRTIM_EECR2_EE7SNS_Msk                   /*!< External event 7 sensitivity */\n#define HRTIM_EECR2_EE7SNS_0          (0x1UL << HRTIM_EECR2_EE7SNS_Pos)         /*!< 0x00000200 */\n#define HRTIM_EECR2_EE7SNS_1          (0x2UL << HRTIM_EECR2_EE7SNS_Pos)         /*!< 0x00000400 */\n\n#define HRTIM_EECR2_EE8SRC_Pos        (12U)\n#define HRTIM_EECR2_EE8SRC_Msk        (0x3UL << HRTIM_EECR2_EE8SRC_Pos)        /*!< 0x00003000 */\n#define HRTIM_EECR2_EE8SRC            HRTIM_EECR2_EE8SRC_Msk                   /*!< External event 8 source */\n#define HRTIM_EECR2_EE8SRC_0          (0x1UL << HRTIM_EECR2_EE8SRC_Pos)         /*!< 0x00001000 */\n#define HRTIM_EECR2_EE8SRC_1          (0x2UL << HRTIM_EECR2_EE8SRC_Pos)         /*!< 0x00002000 */\n#define HRTIM_EECR2_EE8POL_Pos        (14U)\n#define HRTIM_EECR2_EE8POL_Msk        (0x1UL << HRTIM_EECR2_EE8POL_Pos)        /*!< 0x00004000 */\n#define HRTIM_EECR2_EE8POL            HRTIM_EECR2_EE8POL_Msk                   /*!< External event 8 Polarity */\n#define HRTIM_EECR2_EE8SNS_Pos        (15U)\n#define HRTIM_EECR2_EE8SNS_Msk        (0x3UL << HRTIM_EECR2_EE8SNS_Pos)        /*!< 0x00018000 */\n#define HRTIM_EECR2_EE8SNS            HRTIM_EECR2_EE8SNS_Msk                   /*!< External event 8 sensitivity */\n#define HRTIM_EECR2_EE8SNS_0          (0x1UL << HRTIM_EECR2_EE8SNS_Pos)         /*!< 0x00008000 */\n#define HRTIM_EECR2_EE8SNS_1          (0x2UL << HRTIM_EECR2_EE8SNS_Pos)         /*!< 0x00010000 */\n\n#define HRTIM_EECR2_EE9SRC_Pos        (18U)\n#define HRTIM_EECR2_EE9SRC_Msk        (0x3UL << HRTIM_EECR2_EE9SRC_Pos)        /*!< 0x000C0000 */\n#define HRTIM_EECR2_EE9SRC            HRTIM_EECR2_EE9SRC_Msk                   /*!< External event 9 source */\n#define HRTIM_EECR2_EE9SRC_0          (0x1UL << HRTIM_EECR2_EE9SRC_Pos)         /*!< 0x00040000 */\n#define HRTIM_EECR2_EE9SRC_1          (0x2UL << HRTIM_EECR2_EE9SRC_Pos)         /*!< 0x00080000 */\n#define HRTIM_EECR2_EE9POL_Pos        (20U)\n#define HRTIM_EECR2_EE9POL_Msk        (0x1UL << HRTIM_EECR2_EE9POL_Pos)        /*!< 0x00100000 */\n#define HRTIM_EECR2_EE9POL            HRTIM_EECR2_EE9POL_Msk                   /*!< External event 9 Polarity */\n#define HRTIM_EECR2_EE9SNS_Pos        (21U)\n#define HRTIM_EECR2_EE9SNS_Msk        (0x3UL << HRTIM_EECR2_EE9SNS_Pos)        /*!< 0x00600000 */\n#define HRTIM_EECR2_EE9SNS            HRTIM_EECR2_EE9SNS_Msk                   /*!< External event 9 sensitivity */\n#define HRTIM_EECR2_EE9SNS_0          (0x1UL << HRTIM_EECR2_EE9SNS_Pos)         /*!< 0x00200000 */\n#define HRTIM_EECR2_EE9SNS_1          (0x2UL << HRTIM_EECR2_EE9SNS_Pos)         /*!< 0x00400000 */\n\n#define HRTIM_EECR2_EE10SRC_Pos       (24U)\n#define HRTIM_EECR2_EE10SRC_Msk       (0x3UL << HRTIM_EECR2_EE10SRC_Pos)       /*!< 0x03000000 */\n#define HRTIM_EECR2_EE10SRC           HRTIM_EECR2_EE10SRC_Msk                  /*!< External event 10 source */\n#define HRTIM_EECR2_EE10SRC_0         (0x1UL << HRTIM_EECR2_EE10SRC_Pos)        /*!< 0x01000000 */\n#define HRTIM_EECR2_EE10SRC_1         (0x2UL << HRTIM_EECR2_EE10SRC_Pos)        /*!< 0x02000000 */\n#define HRTIM_EECR2_EE10POL_Pos       (26U)\n#define HRTIM_EECR2_EE10POL_Msk       (0x1UL << HRTIM_EECR2_EE10POL_Pos)       /*!< 0x04000000 */\n#define HRTIM_EECR2_EE10POL           HRTIM_EECR2_EE10POL_Msk                  /*!< External event 10 Polarity */\n#define HRTIM_EECR2_EE10SNS_Pos       (27U)\n#define HRTIM_EECR2_EE10SNS_Msk       (0x3UL << HRTIM_EECR2_EE10SNS_Pos)       /*!< 0x18000000 */\n#define HRTIM_EECR2_EE10SNS           HRTIM_EECR2_EE10SNS_Msk                  /*!< External event 10 sensitivity */\n#define HRTIM_EECR2_EE10SNS_0         (0x1UL << HRTIM_EECR2_EE10SNS_Pos)        /*!< 0x08000000 */\n#define HRTIM_EECR2_EE10SNS_1         (0x2UL << HRTIM_EECR2_EE10SNS_Pos)        /*!< 0x10000000 */\n\n/*******************  Bit definition for HRTIM_EECR3 register  ****************/\n#define HRTIM_EECR3_EE6F_Pos          (0U)\n#define HRTIM_EECR3_EE6F_Msk          (0xFUL << HRTIM_EECR3_EE6F_Pos)          /*!< 0x0000000F */\n#define HRTIM_EECR3_EE6F              HRTIM_EECR3_EE6F_Msk                     /*!< External event 6 filter */\n#define HRTIM_EECR3_EE6F_0            (0x1UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000001 */\n#define HRTIM_EECR3_EE6F_1            (0x2UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000002 */\n#define HRTIM_EECR3_EE6F_2            (0x4UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000004 */\n#define HRTIM_EECR3_EE6F_3            (0x8UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000008 */\n#define HRTIM_EECR3_EE7F_Pos          (6U)\n#define HRTIM_EECR3_EE7F_Msk          (0xFUL << HRTIM_EECR3_EE7F_Pos)          /*!< 0x000003C0 */\n#define HRTIM_EECR3_EE7F              HRTIM_EECR3_EE7F_Msk                     /*!< External event 7 filter */\n#define HRTIM_EECR3_EE7F_0            (0x1UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000040 */\n#define HRTIM_EECR3_EE7F_1            (0x2UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000080 */\n#define HRTIM_EECR3_EE7F_2            (0x4UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000100 */\n#define HRTIM_EECR3_EE7F_3            (0x8UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000200 */\n#define HRTIM_EECR3_EE8F_Pos          (12U)\n#define HRTIM_EECR3_EE8F_Msk          (0xFUL << HRTIM_EECR3_EE8F_Pos)          /*!< 0x0000F000 */\n#define HRTIM_EECR3_EE8F              HRTIM_EECR3_EE8F_Msk                     /*!< External event 8 filter */\n#define HRTIM_EECR3_EE8F_0            (0x1UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00001000 */\n#define HRTIM_EECR3_EE8F_1            (0x2UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00002000 */\n#define HRTIM_EECR3_EE8F_2            (0x4UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00004000 */\n#define HRTIM_EECR3_EE8F_3            (0x8UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00008000 */\n#define HRTIM_EECR3_EE9F_Pos          (18U)\n#define HRTIM_EECR3_EE9F_Msk          (0xFUL << HRTIM_EECR3_EE9F_Pos)          /*!< 0x003C0000 */\n#define HRTIM_EECR3_EE9F              HRTIM_EECR3_EE9F_Msk                     /*!< External event 9 filter */\n#define HRTIM_EECR3_EE9F_0            (0x1UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00040000 */\n#define HRTIM_EECR3_EE9F_1            (0x2UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00080000 */\n#define HRTIM_EECR3_EE9F_2            (0x4UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00100000 */\n#define HRTIM_EECR3_EE9F_3            (0x8UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00200000 */\n#define HRTIM_EECR3_EE10F_Pos         (24U)\n#define HRTIM_EECR3_EE10F_Msk         (0xFUL << HRTIM_EECR3_EE10F_Pos)         /*!< 0x0F000000 */\n#define HRTIM_EECR3_EE10F             HRTIM_EECR3_EE10F_Msk                    /*!< External event 10 filter */\n#define HRTIM_EECR3_EE10F_0           (0x1UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x01000000 */\n#define HRTIM_EECR3_EE10F_1           (0x2UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x02000000 */\n#define HRTIM_EECR3_EE10F_2           (0x4UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x04000000 */\n#define HRTIM_EECR3_EE10F_3           (0x8UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x08000000 */\n#define HRTIM_EECR3_EEVSD_Pos         (30U)\n#define HRTIM_EECR3_EEVSD_Msk         (0x3UL << HRTIM_EECR3_EEVSD_Pos)         /*!< 0xC0000000 */\n#define HRTIM_EECR3_EEVSD             HRTIM_EECR3_EEVSD_Msk                    /*!< External event sampling clock division */\n#define HRTIM_EECR3_EEVSD_0           (0x1UL << HRTIM_EECR3_EEVSD_Pos)          /*!< 0x40000000 */\n#define HRTIM_EECR3_EEVSD_1           (0x2UL << HRTIM_EECR3_EEVSD_Pos)          /*!< 0x80000000 */\n\n/*******************  Bit definition for HRTIM_ADC1R register  ****************/\n#define HRTIM_ADC1R_AD1MC1_Pos        (0U)\n#define HRTIM_ADC1R_AD1MC1_Msk        (0x1UL << HRTIM_ADC1R_AD1MC1_Pos)        /*!< 0x00000001 */\n#define HRTIM_ADC1R_AD1MC1            HRTIM_ADC1R_AD1MC1_Msk                   /*!< ADC Trigger 1 on master compare 1 */\n#define HRTIM_ADC1R_AD1MC2_Pos        (1U)\n#define HRTIM_ADC1R_AD1MC2_Msk        (0x1UL << HRTIM_ADC1R_AD1MC2_Pos)        /*!< 0x00000002 */\n#define HRTIM_ADC1R_AD1MC2            HRTIM_ADC1R_AD1MC2_Msk                   /*!< ADC Trigger 1 on master compare 2 */\n#define HRTIM_ADC1R_AD1MC3_Pos        (2U)\n#define HRTIM_ADC1R_AD1MC3_Msk        (0x1UL << HRTIM_ADC1R_AD1MC3_Pos)        /*!< 0x00000004 */\n#define HRTIM_ADC1R_AD1MC3            HRTIM_ADC1R_AD1MC3_Msk                   /*!< ADC Trigger 1 on master compare 3 */\n#define HRTIM_ADC1R_AD1MC4_Pos        (3U)\n#define HRTIM_ADC1R_AD1MC4_Msk        (0x1UL << HRTIM_ADC1R_AD1MC4_Pos)        /*!< 0x00000008 */\n#define HRTIM_ADC1R_AD1MC4            HRTIM_ADC1R_AD1MC4_Msk                   /*!< ADC Trigger 1 on master compare 4 */\n#define HRTIM_ADC1R_AD1MPER_Pos       (4U)\n#define HRTIM_ADC1R_AD1MPER_Msk       (0x1UL << HRTIM_ADC1R_AD1MPER_Pos)       /*!< 0x00000010 */\n#define HRTIM_ADC1R_AD1MPER           HRTIM_ADC1R_AD1MPER_Msk                  /*!< ADC Trigger 1 on master period */\n#define HRTIM_ADC1R_AD1EEV1_Pos       (5U)\n#define HRTIM_ADC1R_AD1EEV1_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV1_Pos)       /*!< 0x00000020 */\n#define HRTIM_ADC1R_AD1EEV1           HRTIM_ADC1R_AD1EEV1_Msk                  /*!< ADC Trigger 1 on external event 1 */\n#define HRTIM_ADC1R_AD1EEV2_Pos       (6U)\n#define HRTIM_ADC1R_AD1EEV2_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV2_Pos)       /*!< 0x00000040 */\n#define HRTIM_ADC1R_AD1EEV2           HRTIM_ADC1R_AD1EEV2_Msk                  /*!< ADC Trigger 1 on external event 2 */\n#define HRTIM_ADC1R_AD1EEV3_Pos       (7U)\n#define HRTIM_ADC1R_AD1EEV3_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV3_Pos)       /*!< 0x00000080 */\n#define HRTIM_ADC1R_AD1EEV3           HRTIM_ADC1R_AD1EEV3_Msk                  /*!< ADC Trigger 1 on external event 3 */\n#define HRTIM_ADC1R_AD1EEV4_Pos       (8U)\n#define HRTIM_ADC1R_AD1EEV4_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV4_Pos)       /*!< 0x00000100 */\n#define HRTIM_ADC1R_AD1EEV4           HRTIM_ADC1R_AD1EEV4_Msk                  /*!< ADC Trigger 1 on external event 4 */\n#define HRTIM_ADC1R_AD1EEV5_Pos       (9U)\n#define HRTIM_ADC1R_AD1EEV5_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV5_Pos)       /*!< 0x00000200 */\n#define HRTIM_ADC1R_AD1EEV5           HRTIM_ADC1R_AD1EEV5_Msk                  /*!< ADC Trigger 1 on external event 5 */\n#define HRTIM_ADC1R_AD1TAC2_Pos       (10U)\n#define HRTIM_ADC1R_AD1TAC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TAC2_Pos)       /*!< 0x00000400 */\n#define HRTIM_ADC1R_AD1TAC2           HRTIM_ADC1R_AD1TAC2_Msk                  /*!< ADC Trigger 1 on Timer A compare 2 */\n#define HRTIM_ADC1R_AD1TAC3_Pos       (11U)\n#define HRTIM_ADC1R_AD1TAC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TAC3_Pos)       /*!< 0x00000800 */\n#define HRTIM_ADC1R_AD1TAC3           HRTIM_ADC1R_AD1TAC3_Msk                  /*!< ADC Trigger 1 on Timer A compare 3 */\n#define HRTIM_ADC1R_AD1TAC4_Pos       (12U)\n#define HRTIM_ADC1R_AD1TAC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TAC4_Pos)       /*!< 0x00001000 */\n#define HRTIM_ADC1R_AD1TAC4           HRTIM_ADC1R_AD1TAC4_Msk                  /*!< ADC Trigger 1 on Timer A compare 4 */\n#define HRTIM_ADC1R_AD1TAPER_Pos      (13U)\n#define HRTIM_ADC1R_AD1TAPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TAPER_Pos)      /*!< 0x00002000 */\n#define HRTIM_ADC1R_AD1TAPER          HRTIM_ADC1R_AD1TAPER_Msk                 /*!< ADC Trigger 1 on Timer A period */\n#define HRTIM_ADC1R_AD1TARST_Pos      (14U)\n#define HRTIM_ADC1R_AD1TARST_Msk      (0x1UL << HRTIM_ADC1R_AD1TARST_Pos)      /*!< 0x00004000 */\n#define HRTIM_ADC1R_AD1TARST          HRTIM_ADC1R_AD1TARST_Msk                 /*!< ADC Trigger 1 on Timer A reset */\n#define HRTIM_ADC1R_AD1TBC2_Pos       (15U)\n#define HRTIM_ADC1R_AD1TBC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TBC2_Pos)       /*!< 0x00008000 */\n#define HRTIM_ADC1R_AD1TBC2           HRTIM_ADC1R_AD1TBC2_Msk                  /*!< ADC Trigger 1 on Timer B compare 2 */\n#define HRTIM_ADC1R_AD1TBC3_Pos       (16U)\n#define HRTIM_ADC1R_AD1TBC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TBC3_Pos)       /*!< 0x00010000 */\n#define HRTIM_ADC1R_AD1TBC3           HRTIM_ADC1R_AD1TBC3_Msk                  /*!< ADC Trigger 1 on Timer B compare 3 */\n#define HRTIM_ADC1R_AD1TBC4_Pos       (17U)\n#define HRTIM_ADC1R_AD1TBC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TBC4_Pos)       /*!< 0x00020000 */\n#define HRTIM_ADC1R_AD1TBC4           HRTIM_ADC1R_AD1TBC4_Msk                  /*!< ADC Trigger 1 on Timer B compare 4 */\n#define HRTIM_ADC1R_AD1TBPER_Pos      (18U)\n#define HRTIM_ADC1R_AD1TBPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TBPER_Pos)      /*!< 0x00040000 */\n#define HRTIM_ADC1R_AD1TBPER          HRTIM_ADC1R_AD1TBPER_Msk                 /*!< ADC Trigger 1 on Timer B period */\n#define HRTIM_ADC1R_AD1TBRST_Pos      (19U)\n#define HRTIM_ADC1R_AD1TBRST_Msk      (0x1UL << HRTIM_ADC1R_AD1TBRST_Pos)      /*!< 0x00080000 */\n#define HRTIM_ADC1R_AD1TBRST          HRTIM_ADC1R_AD1TBRST_Msk                 /*!< ADC Trigger 1 on Timer B reset */\n#define HRTIM_ADC1R_AD1TCC2_Pos       (20U)\n#define HRTIM_ADC1R_AD1TCC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TCC2_Pos)       /*!< 0x00100000 */\n#define HRTIM_ADC1R_AD1TCC2           HRTIM_ADC1R_AD1TCC2_Msk                  /*!< ADC Trigger 1 on Timer C compare 2 */\n#define HRTIM_ADC1R_AD1TCC3_Pos       (21U)\n#define HRTIM_ADC1R_AD1TCC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TCC3_Pos)       /*!< 0x00200000 */\n#define HRTIM_ADC1R_AD1TCC3           HRTIM_ADC1R_AD1TCC3_Msk                  /*!< ADC Trigger 1 on Timer C compare 3 */\n#define HRTIM_ADC1R_AD1TCC4_Pos       (22U)\n#define HRTIM_ADC1R_AD1TCC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TCC4_Pos)       /*!< 0x00400000 */\n#define HRTIM_ADC1R_AD1TCC4           HRTIM_ADC1R_AD1TCC4_Msk                  /*!< ADC Trigger 1 on Timer C compare 4 */\n#define HRTIM_ADC1R_AD1TCPER_Pos      (23U)\n#define HRTIM_ADC1R_AD1TCPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TCPER_Pos)      /*!< 0x00800000 */\n#define HRTIM_ADC1R_AD1TCPER          HRTIM_ADC1R_AD1TCPER_Msk                 /*!< ADC Trigger 1 on Timer C period */\n#define HRTIM_ADC1R_AD1TDC2_Pos       (24U)\n#define HRTIM_ADC1R_AD1TDC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TDC2_Pos)       /*!< 0x01000000 */\n#define HRTIM_ADC1R_AD1TDC2           HRTIM_ADC1R_AD1TDC2_Msk                  /*!< ADC Trigger 1 on Timer D compare 2 */\n#define HRTIM_ADC1R_AD1TDC3_Pos       (25U)\n#define HRTIM_ADC1R_AD1TDC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TDC3_Pos)       /*!< 0x02000000 */\n#define HRTIM_ADC1R_AD1TDC3           HRTIM_ADC1R_AD1TDC3_Msk                  /*!< ADC Trigger 1 on Timer D compare 3 */\n#define HRTIM_ADC1R_AD1TDC4_Pos       (26U)\n#define HRTIM_ADC1R_AD1TDC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TDC4_Pos)       /*!< 0x04000000 */\n#define HRTIM_ADC1R_AD1TDC4           HRTIM_ADC1R_AD1TDC4_Msk                  /*!< ADC Trigger 1 on Timer D compare 4 */\n#define HRTIM_ADC1R_AD1TDPER_Pos      (27U)\n#define HRTIM_ADC1R_AD1TDPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TDPER_Pos)      /*!< 0x08000000 */\n#define HRTIM_ADC1R_AD1TDPER          HRTIM_ADC1R_AD1TDPER_Msk                 /*!< ADC Trigger 1 on Timer D period */\n#define HRTIM_ADC1R_AD1TEC2_Pos       (28U)\n#define HRTIM_ADC1R_AD1TEC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TEC2_Pos)       /*!< 0x10000000 */\n#define HRTIM_ADC1R_AD1TEC2           HRTIM_ADC1R_AD1TEC2_Msk                  /*!< ADC Trigger 1 on Timer E compare 2 */\n#define HRTIM_ADC1R_AD1TEC3_Pos       (29U)\n#define HRTIM_ADC1R_AD1TEC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TEC3_Pos)       /*!< 0x20000000 */\n#define HRTIM_ADC1R_AD1TEC3           HRTIM_ADC1R_AD1TEC3_Msk                  /*!< ADC Trigger 1 on Timer E compare 3 */\n#define HRTIM_ADC1R_AD1TEC4_Pos       (30U)\n#define HRTIM_ADC1R_AD1TEC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TEC4_Pos)       /*!< 0x40000000 */\n#define HRTIM_ADC1R_AD1TEC4           HRTIM_ADC1R_AD1TEC4_Msk                  /*!< ADC Trigger 1 on Timer E compare 4 */\n#define HRTIM_ADC1R_AD1TEPER_Pos      (31U)\n#define HRTIM_ADC1R_AD1TEPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TEPER_Pos)      /*!< 0x80000000 */\n#define HRTIM_ADC1R_AD1TEPER          HRTIM_ADC1R_AD1TEPER_Msk                 /*!< ADC Trigger 1 on Timer E period */\n\n/*******************  Bit definition for HRTIM_ADC2R register  ****************/\n#define HRTIM_ADC2R_AD2MC1_Pos        (0U)\n#define HRTIM_ADC2R_AD2MC1_Msk        (0x1UL << HRTIM_ADC2R_AD2MC1_Pos)        /*!< 0x00000001 */\n#define HRTIM_ADC2R_AD2MC1            HRTIM_ADC2R_AD2MC1_Msk                   /*!< ADC Trigger 2 on master compare 1 */\n#define HRTIM_ADC2R_AD2MC2_Pos        (1U)\n#define HRTIM_ADC2R_AD2MC2_Msk        (0x1UL << HRTIM_ADC2R_AD2MC2_Pos)        /*!< 0x00000002 */\n#define HRTIM_ADC2R_AD2MC2            HRTIM_ADC2R_AD2MC2_Msk                   /*!< ADC Trigger 2 on master compare 2 */\n#define HRTIM_ADC2R_AD2MC3_Pos        (2U)\n#define HRTIM_ADC2R_AD2MC3_Msk        (0x1UL << HRTIM_ADC2R_AD2MC3_Pos)        /*!< 0x00000004 */\n#define HRTIM_ADC2R_AD2MC3            HRTIM_ADC2R_AD2MC3_Msk                   /*!< ADC Trigger 2 on master compare 3 */\n#define HRTIM_ADC2R_AD2MC4_Pos        (3U)\n#define HRTIM_ADC2R_AD2MC4_Msk        (0x1UL << HRTIM_ADC2R_AD2MC4_Pos)        /*!< 0x00000008 */\n#define HRTIM_ADC2R_AD2MC4            HRTIM_ADC2R_AD2MC4_Msk                   /*!< ADC Trigger 2 on master compare 4 */\n#define HRTIM_ADC2R_AD2MPER_Pos       (4U)\n#define HRTIM_ADC2R_AD2MPER_Msk       (0x1UL << HRTIM_ADC2R_AD2MPER_Pos)       /*!< 0x00000010 */\n#define HRTIM_ADC2R_AD2MPER           HRTIM_ADC2R_AD2MPER_Msk                  /*!< ADC Trigger 2 on master period */\n#define HRTIM_ADC2R_AD2EEV6_Pos       (5U)\n#define HRTIM_ADC2R_AD2EEV6_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV6_Pos)       /*!< 0x00000020 */\n#define HRTIM_ADC2R_AD2EEV6           HRTIM_ADC2R_AD2EEV6_Msk                  /*!< ADC Trigger 2 on external event 6 */\n#define HRTIM_ADC2R_AD2EEV7_Pos       (6U)\n#define HRTIM_ADC2R_AD2EEV7_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV7_Pos)       /*!< 0x00000040 */\n#define HRTIM_ADC2R_AD2EEV7           HRTIM_ADC2R_AD2EEV7_Msk                  /*!< ADC Trigger 2 on external event 7 */\n#define HRTIM_ADC2R_AD2EEV8_Pos       (7U)\n#define HRTIM_ADC2R_AD2EEV8_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV8_Pos)       /*!< 0x00000080 */\n#define HRTIM_ADC2R_AD2EEV8           HRTIM_ADC2R_AD2EEV8_Msk                  /*!< ADC Trigger 2 on external event 8 */\n#define HRTIM_ADC2R_AD2EEV9_Pos       (8U)\n#define HRTIM_ADC2R_AD2EEV9_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV9_Pos)       /*!< 0x00000100 */\n#define HRTIM_ADC2R_AD2EEV9           HRTIM_ADC2R_AD2EEV9_Msk                  /*!< ADC Trigger 2 on external event 9 */\n#define HRTIM_ADC2R_AD2EEV10_Pos      (9U)\n#define HRTIM_ADC2R_AD2EEV10_Msk      (0x1UL << HRTIM_ADC2R_AD2EEV10_Pos)      /*!< 0x00000200 */\n#define HRTIM_ADC2R_AD2EEV10          HRTIM_ADC2R_AD2EEV10_Msk                 /*!< ADC Trigger 2 on external event 10 */\n#define HRTIM_ADC2R_AD2TAC2_Pos       (10U)\n#define HRTIM_ADC2R_AD2TAC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TAC2_Pos)       /*!< 0x00000400 */\n#define HRTIM_ADC2R_AD2TAC2           HRTIM_ADC2R_AD2TAC2_Msk                  /*!< ADC Trigger 2 on Timer A compare 2 */\n#define HRTIM_ADC2R_AD2TAC3_Pos       (11U)\n#define HRTIM_ADC2R_AD2TAC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TAC3_Pos)       /*!< 0x00000800 */\n#define HRTIM_ADC2R_AD2TAC3           HRTIM_ADC2R_AD2TAC3_Msk                  /*!< ADC Trigger 2 on Timer A compare 3 */\n#define HRTIM_ADC2R_AD2TAC4_Pos       (12U)\n#define HRTIM_ADC2R_AD2TAC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TAC4_Pos)       /*!< 0x00001000 */\n#define HRTIM_ADC2R_AD2TAC4           HRTIM_ADC2R_AD2TAC4_Msk                  /*!< ADC Trigger 2 on Timer A compare 4*/\n#define HRTIM_ADC2R_AD2TAPER_Pos      (13U)\n#define HRTIM_ADC2R_AD2TAPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TAPER_Pos)      /*!< 0x00002000 */\n#define HRTIM_ADC2R_AD2TAPER          HRTIM_ADC2R_AD2TAPER_Msk                 /*!< ADC Trigger 2 on Timer A period */\n#define HRTIM_ADC2R_AD2TBC2_Pos       (14U)\n#define HRTIM_ADC2R_AD2TBC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TBC2_Pos)       /*!< 0x00004000 */\n#define HRTIM_ADC2R_AD2TBC2           HRTIM_ADC2R_AD2TBC2_Msk                  /*!< ADC Trigger 2 on Timer B compare 2 */\n#define HRTIM_ADC2R_AD2TBC3_Pos       (15U)\n#define HRTIM_ADC2R_AD2TBC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TBC3_Pos)       /*!< 0x00008000 */\n#define HRTIM_ADC2R_AD2TBC3           HRTIM_ADC2R_AD2TBC3_Msk                  /*!< ADC Trigger 2 on Timer B compare 3 */\n#define HRTIM_ADC2R_AD2TBC4_Pos       (16U)\n#define HRTIM_ADC2R_AD2TBC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TBC4_Pos)       /*!< 0x00010000 */\n#define HRTIM_ADC2R_AD2TBC4           HRTIM_ADC2R_AD2TBC4_Msk                  /*!< ADC Trigger 2 on Timer B compare 4 */\n#define HRTIM_ADC2R_AD2TBPER_Pos      (17U)\n#define HRTIM_ADC2R_AD2TBPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TBPER_Pos)      /*!< 0x00020000 */\n#define HRTIM_ADC2R_AD2TBPER          HRTIM_ADC2R_AD2TBPER_Msk                 /*!< ADC Trigger 2 on Timer B period */\n#define HRTIM_ADC2R_AD2TCC2_Pos       (18U)\n#define HRTIM_ADC2R_AD2TCC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TCC2_Pos)       /*!< 0x00040000 */\n#define HRTIM_ADC2R_AD2TCC2           HRTIM_ADC2R_AD2TCC2_Msk                  /*!< ADC Trigger 2 on Timer C compare 2 */\n#define HRTIM_ADC2R_AD2TCC3_Pos       (19U)\n#define HRTIM_ADC2R_AD2TCC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TCC3_Pos)       /*!< 0x00080000 */\n#define HRTIM_ADC2R_AD2TCC3           HRTIM_ADC2R_AD2TCC3_Msk                  /*!< ADC Trigger 2 on Timer C compare 3 */\n#define HRTIM_ADC2R_AD2TCC4_Pos       (20U)\n#define HRTIM_ADC2R_AD2TCC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TCC4_Pos)       /*!< 0x00100000 */\n#define HRTIM_ADC2R_AD2TCC4           HRTIM_ADC2R_AD2TCC4_Msk                  /*!< ADC Trigger 2 on Timer C compare 4 */\n#define HRTIM_ADC2R_AD2TCPER_Pos      (21U)\n#define HRTIM_ADC2R_AD2TCPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TCPER_Pos)      /*!< 0x00200000 */\n#define HRTIM_ADC2R_AD2TCPER          HRTIM_ADC2R_AD2TCPER_Msk                 /*!< ADC Trigger 2 on Timer C period */\n#define HRTIM_ADC2R_AD2TCRST_Pos      (22U)\n#define HRTIM_ADC2R_AD2TCRST_Msk      (0x1UL << HRTIM_ADC2R_AD2TCRST_Pos)      /*!< 0x00400000 */\n#define HRTIM_ADC2R_AD2TCRST          HRTIM_ADC2R_AD2TCRST_Msk                 /*!< ADC Trigger 2 on Timer C reset */\n#define HRTIM_ADC2R_AD2TDC2_Pos       (23U)\n#define HRTIM_ADC2R_AD2TDC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TDC2_Pos)       /*!< 0x00800000 */\n#define HRTIM_ADC2R_AD2TDC2           HRTIM_ADC2R_AD2TDC2_Msk                  /*!< ADC Trigger 2 on Timer D compare 2 */\n#define HRTIM_ADC2R_AD2TDC3_Pos       (24U)\n#define HRTIM_ADC2R_AD2TDC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TDC3_Pos)       /*!< 0x01000000 */\n#define HRTIM_ADC2R_AD2TDC3           HRTIM_ADC2R_AD2TDC3_Msk                  /*!< ADC Trigger 2 on Timer D compare 3 */\n#define HRTIM_ADC2R_AD2TDC4_Pos       (25U)\n#define HRTIM_ADC2R_AD2TDC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TDC4_Pos)       /*!< 0x02000000 */\n#define HRTIM_ADC2R_AD2TDC4           HRTIM_ADC2R_AD2TDC4_Msk                  /*!< ADC Trigger 2 on Timer D compare 4*/\n#define HRTIM_ADC2R_AD2TDPER_Pos      (26U)\n#define HRTIM_ADC2R_AD2TDPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TDPER_Pos)      /*!< 0x04000000 */\n#define HRTIM_ADC2R_AD2TDPER          HRTIM_ADC2R_AD2TDPER_Msk                 /*!< ADC Trigger 2 on Timer D period */\n#define HRTIM_ADC2R_AD2TDRST_Pos      (27U)\n#define HRTIM_ADC2R_AD2TDRST_Msk      (0x1UL << HRTIM_ADC2R_AD2TDRST_Pos)      /*!< 0x08000000 */\n#define HRTIM_ADC2R_AD2TDRST          HRTIM_ADC2R_AD2TDRST_Msk                 /*!< ADC Trigger 2 on Timer D reset */\n#define HRTIM_ADC2R_AD2TEC2_Pos       (28U)\n#define HRTIM_ADC2R_AD2TEC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TEC2_Pos)       /*!< 0x10000000 */\n#define HRTIM_ADC2R_AD2TEC2           HRTIM_ADC2R_AD2TEC2_Msk                  /*!< ADC Trigger 2 on Timer E compare 2 */\n#define HRTIM_ADC2R_AD2TEC3_Pos       (29U)\n#define HRTIM_ADC2R_AD2TEC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TEC3_Pos)       /*!< 0x20000000 */\n#define HRTIM_ADC2R_AD2TEC3           HRTIM_ADC2R_AD2TEC3_Msk                  /*!< ADC Trigger 2 on Timer E compare 3 */\n#define HRTIM_ADC2R_AD2TEC4_Pos       (30U)\n#define HRTIM_ADC2R_AD2TEC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TEC4_Pos)       /*!< 0x40000000 */\n#define HRTIM_ADC2R_AD2TEC4           HRTIM_ADC2R_AD2TEC4_Msk                  /*!< ADC Trigger 2 on Timer E compare 4 */\n#define HRTIM_ADC2R_AD2TERST_Pos      (31U)\n#define HRTIM_ADC2R_AD2TERST_Msk      (0x1UL << HRTIM_ADC2R_AD2TERST_Pos)      /*!< 0x80000000 */\n#define HRTIM_ADC2R_AD2TERST          HRTIM_ADC2R_AD2TERST_Msk                 /*!< ADC Trigger 2 on Timer E reset */\n\n/*******************  Bit definition for HRTIM_ADC3R register  ****************/\n#define HRTIM_ADC3R_AD3MC1_Pos        (0U)\n#define HRTIM_ADC3R_AD3MC1_Msk        (0x1UL << HRTIM_ADC3R_AD3MC1_Pos)        /*!< 0x00000001 */\n#define HRTIM_ADC3R_AD3MC1            HRTIM_ADC3R_AD3MC1_Msk                   /*!< ADC Trigger 3 on master compare 1 */\n#define HRTIM_ADC3R_AD3MC2_Pos        (1U)\n#define HRTIM_ADC3R_AD3MC2_Msk        (0x1UL << HRTIM_ADC3R_AD3MC2_Pos)        /*!< 0x00000002 */\n#define HRTIM_ADC3R_AD3MC2            HRTIM_ADC3R_AD3MC2_Msk                   /*!< ADC Trigger 3 on master compare 2 */\n#define HRTIM_ADC3R_AD3MC3_Pos        (2U)\n#define HRTIM_ADC3R_AD3MC3_Msk        (0x1UL << HRTIM_ADC3R_AD3MC3_Pos)        /*!< 0x00000004 */\n#define HRTIM_ADC3R_AD3MC3            HRTIM_ADC3R_AD3MC3_Msk                   /*!< ADC Trigger 3 on master compare 3 */\n#define HRTIM_ADC3R_AD3MC4_Pos        (3U)\n#define HRTIM_ADC3R_AD3MC4_Msk        (0x1UL << HRTIM_ADC3R_AD3MC4_Pos)        /*!< 0x00000008 */\n#define HRTIM_ADC3R_AD3MC4            HRTIM_ADC3R_AD3MC4_Msk                   /*!< ADC Trigger 3 on master compare 4 */\n#define HRTIM_ADC3R_AD3MPER_Pos       (4U)\n#define HRTIM_ADC3R_AD3MPER_Msk       (0x1UL << HRTIM_ADC3R_AD3MPER_Pos)       /*!< 0x00000010 */\n#define HRTIM_ADC3R_AD3MPER           HRTIM_ADC3R_AD3MPER_Msk                  /*!< ADC Trigger 3 on master period */\n#define HRTIM_ADC3R_AD3EEV1_Pos       (5U)\n#define HRTIM_ADC3R_AD3EEV1_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV1_Pos)       /*!< 0x00000020 */\n#define HRTIM_ADC3R_AD3EEV1           HRTIM_ADC3R_AD3EEV1_Msk                  /*!< ADC Trigger 3 on external event 1 */\n#define HRTIM_ADC3R_AD3EEV2_Pos       (6U)\n#define HRTIM_ADC3R_AD3EEV2_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV2_Pos)       /*!< 0x00000040 */\n#define HRTIM_ADC3R_AD3EEV2           HRTIM_ADC3R_AD3EEV2_Msk                  /*!< ADC Trigger 3 on external event 2 */\n#define HRTIM_ADC3R_AD3EEV3_Pos       (7U)\n#define HRTIM_ADC3R_AD3EEV3_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV3_Pos)       /*!< 0x00000080 */\n#define HRTIM_ADC3R_AD3EEV3           HRTIM_ADC3R_AD3EEV3_Msk                  /*!< ADC Trigger 3 on external event 3 */\n#define HRTIM_ADC3R_AD3EEV4_Pos       (8U)\n#define HRTIM_ADC3R_AD3EEV4_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV4_Pos)       /*!< 0x00000100 */\n#define HRTIM_ADC3R_AD3EEV4           HRTIM_ADC3R_AD3EEV4_Msk                  /*!< ADC Trigger 3 on external event 4 */\n#define HRTIM_ADC3R_AD3EEV5_Pos       (9U)\n#define HRTIM_ADC3R_AD3EEV5_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV5_Pos)       /*!< 0x00000200 */\n#define HRTIM_ADC3R_AD3EEV5           HRTIM_ADC3R_AD3EEV5_Msk                  /*!< ADC Trigger 3 on external event 5 */\n#define HRTIM_ADC3R_AD3TAC2_Pos       (10U)\n#define HRTIM_ADC3R_AD3TAC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TAC2_Pos)       /*!< 0x00000400 */\n#define HRTIM_ADC3R_AD3TAC2           HRTIM_ADC3R_AD3TAC2_Msk                  /*!< ADC Trigger 3 on Timer A compare 2 */\n#define HRTIM_ADC3R_AD3TAC3_Pos       (11U)\n#define HRTIM_ADC3R_AD3TAC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TAC3_Pos)       /*!< 0x00000800 */\n#define HRTIM_ADC3R_AD3TAC3           HRTIM_ADC3R_AD3TAC3_Msk                  /*!< ADC Trigger 3 on Timer A compare 3 */\n#define HRTIM_ADC3R_AD3TAC4_Pos       (12U)\n#define HRTIM_ADC3R_AD3TAC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TAC4_Pos)       /*!< 0x00001000 */\n#define HRTIM_ADC3R_AD3TAC4           HRTIM_ADC3R_AD3TAC4_Msk                  /*!< ADC Trigger 3 on Timer A compare 4 */\n#define HRTIM_ADC3R_AD3TAPER_Pos      (13U)\n#define HRTIM_ADC3R_AD3TAPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TAPER_Pos)      /*!< 0x00002000 */\n#define HRTIM_ADC3R_AD3TAPER          HRTIM_ADC3R_AD3TAPER_Msk                 /*!< ADC Trigger 3 on Timer A period */\n#define HRTIM_ADC3R_AD3TARST_Pos      (14U)\n#define HRTIM_ADC3R_AD3TARST_Msk      (0x1UL << HRTIM_ADC3R_AD3TARST_Pos)      /*!< 0x00004000 */\n#define HRTIM_ADC3R_AD3TARST          HRTIM_ADC3R_AD3TARST_Msk                 /*!< ADC Trigger 3 on Timer A reset */\n#define HRTIM_ADC3R_AD3TBC2_Pos       (15U)\n#define HRTIM_ADC3R_AD3TBC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TBC2_Pos)       /*!< 0x00008000 */\n#define HRTIM_ADC3R_AD3TBC2           HRTIM_ADC3R_AD3TBC2_Msk                  /*!< ADC Trigger 3 on Timer B compare 2 */\n#define HRTIM_ADC3R_AD3TBC3_Pos       (16U)\n#define HRTIM_ADC3R_AD3TBC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TBC3_Pos)       /*!< 0x00010000 */\n#define HRTIM_ADC3R_AD3TBC3           HRTIM_ADC3R_AD3TBC3_Msk                  /*!< ADC Trigger 3 on Timer B compare 3 */\n#define HRTIM_ADC3R_AD3TBC4_Pos       (17U)\n#define HRTIM_ADC3R_AD3TBC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TBC4_Pos)       /*!< 0x00020000 */\n#define HRTIM_ADC3R_AD3TBC4           HRTIM_ADC3R_AD3TBC4_Msk                  /*!< ADC Trigger 3 on Timer B compare 4 */\n#define HRTIM_ADC3R_AD3TBPER_Pos      (18U)\n#define HRTIM_ADC3R_AD3TBPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TBPER_Pos)      /*!< 0x00040000 */\n#define HRTIM_ADC3R_AD3TBPER          HRTIM_ADC3R_AD3TBPER_Msk                 /*!< ADC Trigger 3 on Timer B period */\n#define HRTIM_ADC3R_AD3TBRST_Pos      (19U)\n#define HRTIM_ADC3R_AD3TBRST_Msk      (0x1UL << HRTIM_ADC3R_AD3TBRST_Pos)      /*!< 0x00080000 */\n#define HRTIM_ADC3R_AD3TBRST          HRTIM_ADC3R_AD3TBRST_Msk                 /*!< ADC Trigger 3 on Timer B reset */\n#define HRTIM_ADC3R_AD3TCC2_Pos       (20U)\n#define HRTIM_ADC3R_AD3TCC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TCC2_Pos)       /*!< 0x00100000 */\n#define HRTIM_ADC3R_AD3TCC2           HRTIM_ADC3R_AD3TCC2_Msk                  /*!< ADC Trigger 3 on Timer C compare 2 */\n#define HRTIM_ADC3R_AD3TCC3_Pos       (21U)\n#define HRTIM_ADC3R_AD3TCC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TCC3_Pos)       /*!< 0x00200000 */\n#define HRTIM_ADC3R_AD3TCC3           HRTIM_ADC3R_AD3TCC3_Msk                  /*!< ADC Trigger 3 on Timer C compare 3 */\n#define HRTIM_ADC3R_AD3TCC4_Pos       (22U)\n#define HRTIM_ADC3R_AD3TCC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TCC4_Pos)       /*!< 0x00400000 */\n#define HRTIM_ADC3R_AD3TCC4           HRTIM_ADC3R_AD3TCC4_Msk                  /*!< ADC Trigger 3 on Timer C compare 4 */\n#define HRTIM_ADC3R_AD3TCPER_Pos      (23U)\n#define HRTIM_ADC3R_AD3TCPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TCPER_Pos)      /*!< 0x00800000 */\n#define HRTIM_ADC3R_AD3TCPER          HRTIM_ADC3R_AD3TCPER_Msk                 /*!< ADC Trigger 3 on Timer C period */\n#define HRTIM_ADC3R_AD3TDC2_Pos       (24U)\n#define HRTIM_ADC3R_AD3TDC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TDC2_Pos)       /*!< 0x01000000 */\n#define HRTIM_ADC3R_AD3TDC2           HRTIM_ADC3R_AD3TDC2_Msk                  /*!< ADC Trigger 3 on Timer D compare 2 */\n#define HRTIM_ADC3R_AD3TDC3_Pos       (25U)\n#define HRTIM_ADC3R_AD3TDC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TDC3_Pos)       /*!< 0x02000000 */\n#define HRTIM_ADC3R_AD3TDC3           HRTIM_ADC3R_AD3TDC3_Msk                  /*!< ADC Trigger 3 on Timer D compare 3 */\n#define HRTIM_ADC3R_AD3TDC4_Pos       (26U)\n#define HRTIM_ADC3R_AD3TDC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TDC4_Pos)       /*!< 0x04000000 */\n#define HRTIM_ADC3R_AD3TDC4           HRTIM_ADC3R_AD3TDC4_Msk                  /*!< ADC Trigger 3 on Timer D compare 4 */\n#define HRTIM_ADC3R_AD3TDPER_Pos      (27U)\n#define HRTIM_ADC3R_AD3TDPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TDPER_Pos)      /*!< 0x08000000 */\n#define HRTIM_ADC3R_AD3TDPER          HRTIM_ADC3R_AD3TDPER_Msk                 /*!< ADC Trigger 3 on Timer D period */\n#define HRTIM_ADC3R_AD3TEC2_Pos       (28U)\n#define HRTIM_ADC3R_AD3TEC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TEC2_Pos)       /*!< 0x10000000 */\n#define HRTIM_ADC3R_AD3TEC2           HRTIM_ADC3R_AD3TEC2_Msk                  /*!< ADC Trigger 3 on Timer E compare 2 */\n#define HRTIM_ADC3R_AD3TEC3_Pos       (29U)\n#define HRTIM_ADC3R_AD3TEC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TEC3_Pos)       /*!< 0x20000000 */\n#define HRTIM_ADC3R_AD3TEC3           HRTIM_ADC3R_AD3TEC3_Msk                  /*!< ADC Trigger 3 on Timer E compare 3 */\n#define HRTIM_ADC3R_AD3TEC4_Pos       (30U)\n#define HRTIM_ADC3R_AD3TEC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TEC4_Pos)       /*!< 0x40000000 */\n#define HRTIM_ADC3R_AD3TEC4           HRTIM_ADC3R_AD3TEC4_Msk                  /*!< ADC Trigger 3 on Timer E compare 4 */\n#define HRTIM_ADC3R_AD3TEPER_Pos      (31U)\n#define HRTIM_ADC3R_AD3TEPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TEPER_Pos)      /*!< 0x80000000 */\n#define HRTIM_ADC3R_AD3TEPER          HRTIM_ADC3R_AD3TEPER_Msk                 /*!< ADC Trigger 3 on Timer E period */\n\n/*******************  Bit definition for HRTIM_ADC4R register  ****************/\n#define HRTIM_ADC4R_AD4MC1_Pos        (0U)\n#define HRTIM_ADC4R_AD4MC1_Msk        (0x1UL << HRTIM_ADC4R_AD4MC1_Pos)        /*!< 0x00000001 */\n#define HRTIM_ADC4R_AD4MC1            HRTIM_ADC4R_AD4MC1_Msk                   /*!< ADC Trigger 4 on master compare 1 */\n#define HRTIM_ADC4R_AD4MC2_Pos        (1U)\n#define HRTIM_ADC4R_AD4MC2_Msk        (0x1UL << HRTIM_ADC4R_AD4MC2_Pos)        /*!< 0x00000002 */\n#define HRTIM_ADC4R_AD4MC2            HRTIM_ADC4R_AD4MC2_Msk                   /*!< ADC Trigger 4 on master compare 2 */\n#define HRTIM_ADC4R_AD4MC3_Pos        (2U)\n#define HRTIM_ADC4R_AD4MC3_Msk        (0x1UL << HRTIM_ADC4R_AD4MC3_Pos)        /*!< 0x00000004 */\n#define HRTIM_ADC4R_AD4MC3            HRTIM_ADC4R_AD4MC3_Msk                   /*!< ADC Trigger 4 on master compare 3 */\n#define HRTIM_ADC4R_AD4MC4_Pos        (3U)\n#define HRTIM_ADC4R_AD4MC4_Msk        (0x1UL << HRTIM_ADC4R_AD4MC4_Pos)        /*!< 0x00000008 */\n#define HRTIM_ADC4R_AD4MC4            HRTIM_ADC4R_AD4MC4_Msk                   /*!< ADC Trigger 4 on master compare 4 */\n#define HRTIM_ADC4R_AD4MPER_Pos       (4U)\n#define HRTIM_ADC4R_AD4MPER_Msk       (0x1UL << HRTIM_ADC4R_AD4MPER_Pos)       /*!< 0x00000010 */\n#define HRTIM_ADC4R_AD4MPER           HRTIM_ADC4R_AD4MPER_Msk                  /*!< ADC Trigger 4 on master period */\n#define HRTIM_ADC4R_AD4EEV6_Pos       (5U)\n#define HRTIM_ADC4R_AD4EEV6_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV6_Pos)       /*!< 0x00000020 */\n#define HRTIM_ADC4R_AD4EEV6           HRTIM_ADC4R_AD4EEV6_Msk                  /*!< ADC Trigger 4 on external event 6 */\n#define HRTIM_ADC4R_AD4EEV7_Pos       (6U)\n#define HRTIM_ADC4R_AD4EEV7_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV7_Pos)       /*!< 0x00000040 */\n#define HRTIM_ADC4R_AD4EEV7           HRTIM_ADC4R_AD4EEV7_Msk                  /*!< ADC Trigger 4 on external event 7 */\n#define HRTIM_ADC4R_AD4EEV8_Pos       (7U)\n#define HRTIM_ADC4R_AD4EEV8_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV8_Pos)       /*!< 0x00000080 */\n#define HRTIM_ADC4R_AD4EEV8           HRTIM_ADC4R_AD4EEV8_Msk                  /*!< ADC Trigger 4 on external event 8 */\n#define HRTIM_ADC4R_AD4EEV9_Pos       (8U)\n#define HRTIM_ADC4R_AD4EEV9_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV9_Pos)       /*!< 0x00000100 */\n#define HRTIM_ADC4R_AD4EEV9           HRTIM_ADC4R_AD4EEV9_Msk                  /*!< ADC Trigger 4 on external event 9 */\n#define HRTIM_ADC4R_AD4EEV10_Pos      (9U)\n#define HRTIM_ADC4R_AD4EEV10_Msk      (0x1UL << HRTIM_ADC4R_AD4EEV10_Pos)      /*!< 0x00000200 */\n#define HRTIM_ADC4R_AD4EEV10          HRTIM_ADC4R_AD4EEV10_Msk                 /*!< ADC Trigger 4 on external event 10 */\n#define HRTIM_ADC4R_AD4TAC2_Pos       (10U)\n#define HRTIM_ADC4R_AD4TAC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TAC2_Pos)       /*!< 0x00000400 */\n#define HRTIM_ADC4R_AD4TAC2           HRTIM_ADC4R_AD4TAC2_Msk                  /*!< ADC Trigger 4 on Timer A compare 2 */\n#define HRTIM_ADC4R_AD4TAC3_Pos       (11U)\n#define HRTIM_ADC4R_AD4TAC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TAC3_Pos)       /*!< 0x00000800 */\n#define HRTIM_ADC4R_AD4TAC3           HRTIM_ADC4R_AD4TAC3_Msk                  /*!< ADC Trigger 4 on Timer A compare 3 */\n#define HRTIM_ADC4R_AD4TAC4_Pos       (12U)\n#define HRTIM_ADC4R_AD4TAC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TAC4_Pos)       /*!< 0x00001000 */\n#define HRTIM_ADC4R_AD4TAC4           HRTIM_ADC4R_AD4TAC4_Msk                  /*!< ADC Trigger 4 on Timer A compare 4*/\n#define HRTIM_ADC4R_AD4TAPER_Pos      (13U)\n#define HRTIM_ADC4R_AD4TAPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TAPER_Pos)      /*!< 0x00002000 */\n#define HRTIM_ADC4R_AD4TAPER          HRTIM_ADC4R_AD4TAPER_Msk                 /*!< ADC Trigger 4 on Timer A period */\n#define HRTIM_ADC4R_AD4TBC2_Pos       (14U)\n#define HRTIM_ADC4R_AD4TBC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TBC2_Pos)       /*!< 0x00004000 */\n#define HRTIM_ADC4R_AD4TBC2           HRTIM_ADC4R_AD4TBC2_Msk                  /*!< ADC Trigger 4 on Timer B compare 2 */\n#define HRTIM_ADC4R_AD4TBC3_Pos       (15U)\n#define HRTIM_ADC4R_AD4TBC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TBC3_Pos)       /*!< 0x00008000 */\n#define HRTIM_ADC4R_AD4TBC3           HRTIM_ADC4R_AD4TBC3_Msk                  /*!< ADC Trigger 4 on Timer B compare 3 */\n#define HRTIM_ADC4R_AD4TBC4_Pos       (16U)\n#define HRTIM_ADC4R_AD4TBC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TBC4_Pos)       /*!< 0x00010000 */\n#define HRTIM_ADC4R_AD4TBC4           HRTIM_ADC4R_AD4TBC4_Msk                  /*!< ADC Trigger 4 on Timer B compare 4 */\n#define HRTIM_ADC4R_AD4TBPER_Pos      (17U)\n#define HRTIM_ADC4R_AD4TBPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TBPER_Pos)      /*!< 0x00020000 */\n#define HRTIM_ADC4R_AD4TBPER          HRTIM_ADC4R_AD4TBPER_Msk                 /*!< ADC Trigger 4 on Timer B period */\n#define HRTIM_ADC4R_AD4TCC2_Pos       (18U)\n#define HRTIM_ADC4R_AD4TCC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TCC2_Pos)       /*!< 0x00040000 */\n#define HRTIM_ADC4R_AD4TCC2           HRTIM_ADC4R_AD4TCC2_Msk                  /*!< ADC Trigger 4 on Timer C compare 2 */\n#define HRTIM_ADC4R_AD4TCC3_Pos       (19U)\n#define HRTIM_ADC4R_AD4TCC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TCC3_Pos)       /*!< 0x00080000 */\n#define HRTIM_ADC4R_AD4TCC3           HRTIM_ADC4R_AD4TCC3_Msk                  /*!< ADC Trigger 4 on Timer C compare 3 */\n#define HRTIM_ADC4R_AD4TCC4_Pos       (20U)\n#define HRTIM_ADC4R_AD4TCC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TCC4_Pos)       /*!< 0x00100000 */\n#define HRTIM_ADC4R_AD4TCC4           HRTIM_ADC4R_AD4TCC4_Msk                  /*!< ADC Trigger 4 on Timer C compare 4 */\n#define HRTIM_ADC4R_AD4TCPER_Pos      (21U)\n#define HRTIM_ADC4R_AD4TCPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TCPER_Pos)      /*!< 0x00200000 */\n#define HRTIM_ADC4R_AD4TCPER          HRTIM_ADC4R_AD4TCPER_Msk                 /*!< ADC Trigger 4 on Timer C period */\n#define HRTIM_ADC4R_AD4TCRST_Pos      (22U)\n#define HRTIM_ADC4R_AD4TCRST_Msk      (0x1UL << HRTIM_ADC4R_AD4TCRST_Pos)      /*!< 0x00400000 */\n#define HRTIM_ADC4R_AD4TCRST          HRTIM_ADC4R_AD4TCRST_Msk                 /*!< ADC Trigger 4 on Timer C reset */\n#define HRTIM_ADC4R_AD4TDC2_Pos       (23U)\n#define HRTIM_ADC4R_AD4TDC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TDC2_Pos)       /*!< 0x00800000 */\n#define HRTIM_ADC4R_AD4TDC2           HRTIM_ADC4R_AD4TDC2_Msk                  /*!< ADC Trigger 4 on Timer D compare 2 */\n#define HRTIM_ADC4R_AD4TDC3_Pos       (24U)\n#define HRTIM_ADC4R_AD4TDC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TDC3_Pos)       /*!< 0x01000000 */\n#define HRTIM_ADC4R_AD4TDC3           HRTIM_ADC4R_AD4TDC3_Msk                  /*!< ADC Trigger 4 on Timer D compare 3 */\n#define HRTIM_ADC4R_AD4TDC4_Pos       (25U)\n#define HRTIM_ADC4R_AD4TDC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TDC4_Pos)       /*!< 0x02000000 */\n#define HRTIM_ADC4R_AD4TDC4           HRTIM_ADC4R_AD4TDC4_Msk                  /*!< ADC Trigger 4 on Timer D compare 4*/\n#define HRTIM_ADC4R_AD4TDPER_Pos      (26U)\n#define HRTIM_ADC4R_AD4TDPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TDPER_Pos)      /*!< 0x04000000 */\n#define HRTIM_ADC4R_AD4TDPER          HRTIM_ADC4R_AD4TDPER_Msk                 /*!< ADC Trigger 4 on Timer D period */\n#define HRTIM_ADC4R_AD4TDRST_Pos      (27U)\n#define HRTIM_ADC4R_AD4TDRST_Msk      (0x1UL << HRTIM_ADC4R_AD4TDRST_Pos)      /*!< 0x08000000 */\n#define HRTIM_ADC4R_AD4TDRST          HRTIM_ADC4R_AD4TDRST_Msk                 /*!< ADC Trigger 4 on Timer D reset */\n#define HRTIM_ADC4R_AD4TEC2_Pos       (28U)\n#define HRTIM_ADC4R_AD4TEC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TEC2_Pos)       /*!< 0x10000000 */\n#define HRTIM_ADC4R_AD4TEC2           HRTIM_ADC4R_AD4TEC2_Msk                  /*!< ADC Trigger 4 on Timer E compare 2 */\n#define HRTIM_ADC4R_AD4TEC3_Pos       (29U)\n#define HRTIM_ADC4R_AD4TEC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TEC3_Pos)       /*!< 0x20000000 */\n#define HRTIM_ADC4R_AD4TEC3           HRTIM_ADC4R_AD4TEC3_Msk                  /*!< ADC Trigger 4 on Timer E compare 3 */\n#define HRTIM_ADC4R_AD4TEC4_Pos       (30U)\n#define HRTIM_ADC4R_AD4TEC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TEC4_Pos)       /*!< 0x40000000 */\n#define HRTIM_ADC4R_AD4TEC4           HRTIM_ADC4R_AD4TEC4_Msk                  /*!< ADC Trigger 4 on Timer E compare 4 */\n#define HRTIM_ADC4R_AD4TERST_Pos      (31U)\n#define HRTIM_ADC4R_AD4TERST_Msk      (0x1UL << HRTIM_ADC4R_AD4TERST_Pos)      /*!< 0x80000000 */\n#define HRTIM_ADC4R_AD4TERST          HRTIM_ADC4R_AD4TERST_Msk                 /*!< ADC Trigger 4 on Timer E reset */\n\n/*******************  Bit definition for HRTIM_FLTINR1 register  ***************/\n#define HRTIM_FLTINR1_FLT1E_Pos       (0U)\n#define HRTIM_FLTINR1_FLT1E_Msk       (0x1UL << HRTIM_FLTINR1_FLT1E_Pos)       /*!< 0x00000001 */\n#define HRTIM_FLTINR1_FLT1E           HRTIM_FLTINR1_FLT1E_Msk                  /*!< Fault 1 enable */\n#define HRTIM_FLTINR1_FLT1P_Pos       (1U)\n#define HRTIM_FLTINR1_FLT1P_Msk       (0x1UL << HRTIM_FLTINR1_FLT1P_Pos)       /*!< 0x00000002 */\n#define HRTIM_FLTINR1_FLT1P           HRTIM_FLTINR1_FLT1P_Msk                  /*!< Fault 1 polarity */\n#define HRTIM_FLTINR1_FLT1SRC_Pos     (2U)\n#define HRTIM_FLTINR1_FLT1SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT1SRC_Pos)     /*!< 0x00000004 */\n#define HRTIM_FLTINR1_FLT1SRC         HRTIM_FLTINR1_FLT1SRC_Msk                /*!< Fault 1 source */\n#define HRTIM_FLTINR1_FLT1F_Pos       (3U)\n#define HRTIM_FLTINR1_FLT1F_Msk       (0xFUL << HRTIM_FLTINR1_FLT1F_Pos)       /*!< 0x00000078 */\n#define HRTIM_FLTINR1_FLT1F           HRTIM_FLTINR1_FLT1F_Msk                  /*!< Fault 1 filter */\n#define HRTIM_FLTINR1_FLT1F_0         (0x1UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000008 */\n#define HRTIM_FLTINR1_FLT1F_1         (0x2UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000010 */\n#define HRTIM_FLTINR1_FLT1F_2         (0x4UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000020 */\n#define HRTIM_FLTINR1_FLT1F_3         (0x8UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000040 */\n#define HRTIM_FLTINR1_FLT1LCK_Pos     (7U)\n#define HRTIM_FLTINR1_FLT1LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT1LCK_Pos)     /*!< 0x00000080 */\n#define HRTIM_FLTINR1_FLT1LCK         HRTIM_FLTINR1_FLT1LCK_Msk                /*!< Fault 1 lock */\n\n#define HRTIM_FLTINR1_FLT2E_Pos       (8U)\n#define HRTIM_FLTINR1_FLT2E_Msk       (0x1UL << HRTIM_FLTINR1_FLT2E_Pos)       /*!< 0x00000100 */\n#define HRTIM_FLTINR1_FLT2E           HRTIM_FLTINR1_FLT2E_Msk                  /*!< Fault 2 enable */\n#define HRTIM_FLTINR1_FLT2P_Pos       (9U)\n#define HRTIM_FLTINR1_FLT2P_Msk       (0x1UL << HRTIM_FLTINR1_FLT2P_Pos)       /*!< 0x00000200 */\n#define HRTIM_FLTINR1_FLT2P           HRTIM_FLTINR1_FLT2P_Msk                  /*!< Fault 2 polarity */\n#define HRTIM_FLTINR1_FLT2SRC_Pos     (10U)\n#define HRTIM_FLTINR1_FLT2SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT2SRC_Pos)     /*!< 0x00000400 */\n#define HRTIM_FLTINR1_FLT2SRC         HRTIM_FLTINR1_FLT2SRC_Msk                /*!< Fault 2 source */\n#define HRTIM_FLTINR1_FLT2F_Pos       (11U)\n#define HRTIM_FLTINR1_FLT2F_Msk       (0xFUL << HRTIM_FLTINR1_FLT2F_Pos)       /*!< 0x00007800 */\n#define HRTIM_FLTINR1_FLT2F           HRTIM_FLTINR1_FLT2F_Msk                  /*!< Fault 2 filter */\n#define HRTIM_FLTINR1_FLT2F_0         (0x1UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00000800 */\n#define HRTIM_FLTINR1_FLT2F_1         (0x2UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00001000 */\n#define HRTIM_FLTINR1_FLT2F_2         (0x4UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00002000 */\n#define HRTIM_FLTINR1_FLT2F_3         (0x8UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00004000 */\n#define HRTIM_FLTINR1_FLT2LCK_Pos     (15U)\n#define HRTIM_FLTINR1_FLT2LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT2LCK_Pos)     /*!< 0x00008000 */\n#define HRTIM_FLTINR1_FLT2LCK         HRTIM_FLTINR1_FLT2LCK_Msk                /*!< Fault 2 lock */\n\n#define HRTIM_FLTINR1_FLT3E_Pos       (16U)\n#define HRTIM_FLTINR1_FLT3E_Msk       (0x1UL << HRTIM_FLTINR1_FLT3E_Pos)       /*!< 0x00010000 */\n#define HRTIM_FLTINR1_FLT3E           HRTIM_FLTINR1_FLT3E_Msk                  /*!< Fault 3 enable */\n#define HRTIM_FLTINR1_FLT3P_Pos       (17U)\n#define HRTIM_FLTINR1_FLT3P_Msk       (0x1UL << HRTIM_FLTINR1_FLT3P_Pos)       /*!< 0x00020000 */\n#define HRTIM_FLTINR1_FLT3P           HRTIM_FLTINR1_FLT3P_Msk                  /*!< Fault 3 polarity */\n#define HRTIM_FLTINR1_FLT3SRC_Pos     (18U)\n#define HRTIM_FLTINR1_FLT3SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT3SRC_Pos)     /*!< 0x00040000 */\n#define HRTIM_FLTINR1_FLT3SRC         HRTIM_FLTINR1_FLT3SRC_Msk                /*!< Fault 3 source */\n#define HRTIM_FLTINR1_FLT3F_Pos       (19U)\n#define HRTIM_FLTINR1_FLT3F_Msk       (0xFUL << HRTIM_FLTINR1_FLT3F_Pos)       /*!< 0x00780000 */\n#define HRTIM_FLTINR1_FLT3F           HRTIM_FLTINR1_FLT3F_Msk                  /*!< Fault 3 filter */\n#define HRTIM_FLTINR1_FLT3F_0         (0x1UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00080000 */\n#define HRTIM_FLTINR1_FLT3F_1         (0x2UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00100000 */\n#define HRTIM_FLTINR1_FLT3F_2         (0x4UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00200000 */\n#define HRTIM_FLTINR1_FLT3F_3         (0x8UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00400000 */\n#define HRTIM_FLTINR1_FLT3LCK_Pos     (23U)\n#define HRTIM_FLTINR1_FLT3LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT3LCK_Pos)     /*!< 0x00800000 */\n#define HRTIM_FLTINR1_FLT3LCK         HRTIM_FLTINR1_FLT3LCK_Msk                /*!< Fault 3 lock */\n\n#define HRTIM_FLTINR1_FLT4E_Pos       (24U)\n#define HRTIM_FLTINR1_FLT4E_Msk       (0x1UL << HRTIM_FLTINR1_FLT4E_Pos)       /*!< 0x01000000 */\n#define HRTIM_FLTINR1_FLT4E           HRTIM_FLTINR1_FLT4E_Msk                  /*!< Fault 4 enable */\n#define HRTIM_FLTINR1_FLT4P_Pos       (25U)\n#define HRTIM_FLTINR1_FLT4P_Msk       (0x1UL << HRTIM_FLTINR1_FLT4P_Pos)       /*!< 0x02000000 */\n#define HRTIM_FLTINR1_FLT4P           HRTIM_FLTINR1_FLT4P_Msk                  /*!< Fault 4 polarity */\n#define HRTIM_FLTINR1_FLT4SRC_Pos     (26U)\n#define HRTIM_FLTINR1_FLT4SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT4SRC_Pos)     /*!< 0x04000000 */\n#define HRTIM_FLTINR1_FLT4SRC         HRTIM_FLTINR1_FLT4SRC_Msk                /*!< Fault 4 source */\n#define HRTIM_FLTINR1_FLT4F_Pos       (27U)\n#define HRTIM_FLTINR1_FLT4F_Msk       (0xFUL << HRTIM_FLTINR1_FLT4F_Pos)       /*!< 0x78000000 */\n#define HRTIM_FLTINR1_FLT4F           HRTIM_FLTINR1_FLT4F_Msk                  /*!< Fault 4 filter */\n#define HRTIM_FLTINR1_FLT4F_0         (0x1UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x08000000 */\n#define HRTIM_FLTINR1_FLT4F_1         (0x2UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x10000000 */\n#define HRTIM_FLTINR1_FLT4F_2         (0x4UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x20000000 */\n#define HRTIM_FLTINR1_FLT4F_3         (0x8UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x40000000 */\n#define HRTIM_FLTINR1_FLT4LCK_Pos     (31U)\n#define HRTIM_FLTINR1_FLT4LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT4LCK_Pos)     /*!< 0x80000000 */\n#define HRTIM_FLTINR1_FLT4LCK         HRTIM_FLTINR1_FLT4LCK_Msk                /*!< Fault 4 lock */\n\n/*******************  Bit definition for HRTIM_FLTINR2 register  ***************/\n#define HRTIM_FLTINR2_FLT5E_Pos       (0U)\n#define HRTIM_FLTINR2_FLT5E_Msk       (0x1UL << HRTIM_FLTINR2_FLT5E_Pos)       /*!< 0x00000001 */\n#define HRTIM_FLTINR2_FLT5E           HRTIM_FLTINR2_FLT5E_Msk                  /*!< Fault 5 enable */\n#define HRTIM_FLTINR2_FLT5P_Pos       (1U)\n#define HRTIM_FLTINR2_FLT5P_Msk       (0x1UL << HRTIM_FLTINR2_FLT5P_Pos)       /*!< 0x00000002 */\n#define HRTIM_FLTINR2_FLT5P           HRTIM_FLTINR2_FLT5P_Msk                  /*!< Fault 5 polarity */\n#define HRTIM_FLTINR2_FLT5SRC_Pos     (2U)\n#define HRTIM_FLTINR2_FLT5SRC_Msk     (0x1UL << HRTIM_FLTINR2_FLT5SRC_Pos)     /*!< 0x00000004 */\n#define HRTIM_FLTINR2_FLT5SRC         HRTIM_FLTINR2_FLT5SRC_Msk                /*!< Fault 5 source */\n#define HRTIM_FLTINR2_FLT5F_Pos       (3U)\n#define HRTIM_FLTINR2_FLT5F_Msk       (0xFUL << HRTIM_FLTINR2_FLT5F_Pos)       /*!< 0x00000078 */\n#define HRTIM_FLTINR2_FLT5F           HRTIM_FLTINR2_FLT5F_Msk                  /*!< Fault 5 filter */\n#define HRTIM_FLTINR2_FLT5F_0         (0x1UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000008 */\n#define HRTIM_FLTINR2_FLT5F_1         (0x2UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000010 */\n#define HRTIM_FLTINR2_FLT5F_2         (0x4UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000020 */\n#define HRTIM_FLTINR2_FLT5F_3         (0x8UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000040 */\n#define HRTIM_FLTINR2_FLT5LCK_Pos     (7U)\n#define HRTIM_FLTINR2_FLT5LCK_Msk     (0x1UL << HRTIM_FLTINR2_FLT5LCK_Pos)     /*!< 0x00000080 */\n#define HRTIM_FLTINR2_FLT5LCK         HRTIM_FLTINR2_FLT5LCK_Msk                /*!< Fault 5 lock */\n#define HRTIM_FLTINR2_FLTSD_Pos       (24U)\n#define HRTIM_FLTINR2_FLTSD_Msk       (0x3UL << HRTIM_FLTINR2_FLTSD_Pos)       /*!< 0x03000000 */\n#define HRTIM_FLTINR2_FLTSD           HRTIM_FLTINR2_FLTSD_Msk                  /*!< Fault sampling clock division */\n#define HRTIM_FLTINR2_FLTSD_0         (0x1UL << HRTIM_FLTINR2_FLTSD_Pos)        /*!< 0x01000000 */\n#define HRTIM_FLTINR2_FLTSD_1         (0x2UL << HRTIM_FLTINR2_FLTSD_Pos)        /*!< 0x02000000 */\n\n/*******************  Bit definition for HRTIM_BDMUPR register  ***************/\n#define HRTIM_BDMUPR_MCR_Pos          (0U)\n#define HRTIM_BDMUPR_MCR_Msk          (0x1UL << HRTIM_BDMUPR_MCR_Pos)          /*!< 0x00000001 */\n#define HRTIM_BDMUPR_MCR              HRTIM_BDMUPR_MCR_Msk                     /*!< MCR register update enable */\n#define HRTIM_BDMUPR_MICR_Pos         (1U)\n#define HRTIM_BDMUPR_MICR_Msk         (0x1UL << HRTIM_BDMUPR_MICR_Pos)         /*!< 0x00000002 */\n#define HRTIM_BDMUPR_MICR             HRTIM_BDMUPR_MICR_Msk                    /*!< MICR register update enable */\n#define HRTIM_BDMUPR_MDIER_Pos        (2U)\n#define HRTIM_BDMUPR_MDIER_Msk        (0x1UL << HRTIM_BDMUPR_MDIER_Pos)        /*!< 0x00000004 */\n#define HRTIM_BDMUPR_MDIER            HRTIM_BDMUPR_MDIER_Msk                   /*!< MDIER register update enable */\n#define HRTIM_BDMUPR_MCNT_Pos         (3U)\n#define HRTIM_BDMUPR_MCNT_Msk         (0x1UL << HRTIM_BDMUPR_MCNT_Pos)         /*!< 0x00000008 */\n#define HRTIM_BDMUPR_MCNT             HRTIM_BDMUPR_MCNT_Msk                    /*!< MCNT register update enable */\n#define HRTIM_BDMUPR_MPER_Pos         (4U)\n#define HRTIM_BDMUPR_MPER_Msk         (0x1UL << HRTIM_BDMUPR_MPER_Pos)         /*!< 0x00000010 */\n#define HRTIM_BDMUPR_MPER             HRTIM_BDMUPR_MPER_Msk                    /*!< MPER register update enable */\n#define HRTIM_BDMUPR_MREP_Pos         (5U)\n#define HRTIM_BDMUPR_MREP_Msk         (0x1UL << HRTIM_BDMUPR_MREP_Pos)         /*!< 0x00000020 */\n#define HRTIM_BDMUPR_MREP             HRTIM_BDMUPR_MREP_Msk                    /*!< MREP register update enable */\n#define HRTIM_BDMUPR_MCMP1_Pos        (6U)\n#define HRTIM_BDMUPR_MCMP1_Msk        (0x1UL << HRTIM_BDMUPR_MCMP1_Pos)        /*!< 0x00000040 */\n#define HRTIM_BDMUPR_MCMP1            HRTIM_BDMUPR_MCMP1_Msk                   /*!< MCMP1 register update enable */\n#define HRTIM_BDMUPR_MCMP2_Pos        (7U)\n#define HRTIM_BDMUPR_MCMP2_Msk        (0x1UL << HRTIM_BDMUPR_MCMP2_Pos)        /*!< 0x00000080 */\n#define HRTIM_BDMUPR_MCMP2            HRTIM_BDMUPR_MCMP2_Msk                   /*!< MCMP2 register update enable */\n#define HRTIM_BDMUPR_MCMP3_Pos        (8U)\n#define HRTIM_BDMUPR_MCMP3_Msk        (0x1UL << HRTIM_BDMUPR_MCMP3_Pos)        /*!< 0x00000100 */\n#define HRTIM_BDMUPR_MCMP3            HRTIM_BDMUPR_MCMP3_Msk                   /*!< MCMP3 register update enable */\n#define HRTIM_BDMUPR_MCMP4_Pos        (9U)\n#define HRTIM_BDMUPR_MCMP4_Msk        (0x1UL << HRTIM_BDMUPR_MCMP4_Pos)        /*!< 0x00000200 */\n#define HRTIM_BDMUPR_MCMP4            HRTIM_BDMUPR_MCMP4_Msk                   /*!< MPCMP4 register update enable */\n\n/*******************  Bit definition for HRTIM_BDTUPR register  ***************/\n#define HRTIM_BDTUPR_TIMCR_Pos        (0U)\n#define HRTIM_BDTUPR_TIMCR_Msk        (0x1UL << HRTIM_BDTUPR_TIMCR_Pos)        /*!< 0x00000001 */\n#define HRTIM_BDTUPR_TIMCR            HRTIM_BDTUPR_TIMCR_Msk                   /*!<  TIMCR register update enable */\n#define HRTIM_BDTUPR_TIMICR_Pos       (1U)\n#define HRTIM_BDTUPR_TIMICR_Msk       (0x1UL << HRTIM_BDTUPR_TIMICR_Pos)       /*!< 0x00000002 */\n#define HRTIM_BDTUPR_TIMICR           HRTIM_BDTUPR_TIMICR_Msk                  /*!<  TIMICR register update enable */\n#define HRTIM_BDTUPR_TIMDIER_Pos      (2U)\n#define HRTIM_BDTUPR_TIMDIER_Msk      (0x1UL << HRTIM_BDTUPR_TIMDIER_Pos)      /*!< 0x00000004 */\n#define HRTIM_BDTUPR_TIMDIER          HRTIM_BDTUPR_TIMDIER_Msk                 /*!<  TIMDIER register update enable */\n#define HRTIM_BDTUPR_TIMCNT_Pos       (3U)\n#define HRTIM_BDTUPR_TIMCNT_Msk       (0x1UL << HRTIM_BDTUPR_TIMCNT_Pos)       /*!< 0x00000008 */\n#define HRTIM_BDTUPR_TIMCNT           HRTIM_BDTUPR_TIMCNT_Msk                  /*!<  TIMCNT register update enable */\n#define HRTIM_BDTUPR_TIMPER_Pos       (4U)\n#define HRTIM_BDTUPR_TIMPER_Msk       (0x1UL << HRTIM_BDTUPR_TIMPER_Pos)       /*!< 0x00000010 */\n#define HRTIM_BDTUPR_TIMPER           HRTIM_BDTUPR_TIMPER_Msk                  /*!<  TIMPER register update enable */\n#define HRTIM_BDTUPR_TIMREP_Pos       (5U)\n#define HRTIM_BDTUPR_TIMREP_Msk       (0x1UL << HRTIM_BDTUPR_TIMREP_Pos)       /*!< 0x00000020 */\n#define HRTIM_BDTUPR_TIMREP           HRTIM_BDTUPR_TIMREP_Msk                  /*!<  TIMREP register update enable */\n#define HRTIM_BDTUPR_TIMCMP1_Pos      (6U)\n#define HRTIM_BDTUPR_TIMCMP1_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP1_Pos)      /*!< 0x00000040 */\n#define HRTIM_BDTUPR_TIMCMP1          HRTIM_BDTUPR_TIMCMP1_Msk                 /*!<  TIMCMP1 register update enable */\n#define HRTIM_BDTUPR_TIMCMP2_Pos      (7U)\n#define HRTIM_BDTUPR_TIMCMP2_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP2_Pos)      /*!< 0x00000080 */\n#define HRTIM_BDTUPR_TIMCMP2          HRTIM_BDTUPR_TIMCMP2_Msk                 /*!<  TIMCMP2 register update enable */\n#define HRTIM_BDTUPR_TIMCMP3_Pos      (8U)\n#define HRTIM_BDTUPR_TIMCMP3_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP3_Pos)      /*!< 0x00000100 */\n#define HRTIM_BDTUPR_TIMCMP3          HRTIM_BDTUPR_TIMCMP3_Msk                 /*!<  TIMCMP3 register update enable */\n#define HRTIM_BDTUPR_TIMCMP4_Pos      (9U)\n#define HRTIM_BDTUPR_TIMCMP4_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP4_Pos)      /*!< 0x00000200 */\n#define HRTIM_BDTUPR_TIMCMP4          HRTIM_BDTUPR_TIMCMP4_Msk                 /*!<  TIMCMP4 register update enable */\n#define HRTIM_BDTUPR_TIMDTR_Pos       (10U)\n#define HRTIM_BDTUPR_TIMDTR_Msk       (0x1UL << HRTIM_BDTUPR_TIMDTR_Pos)       /*!< 0x00000400 */\n#define HRTIM_BDTUPR_TIMDTR           HRTIM_BDTUPR_TIMDTR_Msk                  /*!<  TIMDTR register update enable */\n#define HRTIM_BDTUPR_TIMSET1R_Pos     (11U)\n#define HRTIM_BDTUPR_TIMSET1R_Msk     (0x1UL << HRTIM_BDTUPR_TIMSET1R_Pos)     /*!< 0x00000800 */\n#define HRTIM_BDTUPR_TIMSET1R         HRTIM_BDTUPR_TIMSET1R_Msk                /*!<  TIMSET1R register update enable */\n#define HRTIM_BDTUPR_TIMRST1R_Pos     (12U)\n#define HRTIM_BDTUPR_TIMRST1R_Msk     (0x1UL << HRTIM_BDTUPR_TIMRST1R_Pos)     /*!< 0x00001000 */\n#define HRTIM_BDTUPR_TIMRST1R         HRTIM_BDTUPR_TIMRST1R_Msk                /*!<  TIMRST1R register update enable */\n#define HRTIM_BDTUPR_TIMSET2R_Pos     (13U)\n#define HRTIM_BDTUPR_TIMSET2R_Msk     (0x1UL << HRTIM_BDTUPR_TIMSET2R_Pos)     /*!< 0x00002000 */\n#define HRTIM_BDTUPR_TIMSET2R         HRTIM_BDTUPR_TIMSET2R_Msk                /*!<  TIMSET2R register update enable */\n#define HRTIM_BDTUPR_TIMRST2R_Pos     (14U)\n#define HRTIM_BDTUPR_TIMRST2R_Msk     (0x1UL << HRTIM_BDTUPR_TIMRST2R_Pos)     /*!< 0x00004000 */\n#define HRTIM_BDTUPR_TIMRST2R         HRTIM_BDTUPR_TIMRST2R_Msk                /*!<  TIMRST2R register update enable */\n#define HRTIM_BDTUPR_TIMEEFR1_Pos     (15U)\n#define HRTIM_BDTUPR_TIMEEFR1_Msk     (0x1UL << HRTIM_BDTUPR_TIMEEFR1_Pos)     /*!< 0x00008000 */\n#define HRTIM_BDTUPR_TIMEEFR1         HRTIM_BDTUPR_TIMEEFR1_Msk                /*!<  TIMEEFR1 register update enable */\n#define HRTIM_BDTUPR_TIMEEFR2_Pos     (16U)\n#define HRTIM_BDTUPR_TIMEEFR2_Msk     (0x1UL << HRTIM_BDTUPR_TIMEEFR2_Pos)     /*!< 0x00010000 */\n#define HRTIM_BDTUPR_TIMEEFR2         HRTIM_BDTUPR_TIMEEFR2_Msk                /*!<  TIMEEFR2 register update enable */\n#define HRTIM_BDTUPR_TIMRSTR_Pos      (17U)\n#define HRTIM_BDTUPR_TIMRSTR_Msk      (0x1UL << HRTIM_BDTUPR_TIMRSTR_Pos)      /*!< 0x00020000 */\n#define HRTIM_BDTUPR_TIMRSTR          HRTIM_BDTUPR_TIMRSTR_Msk                 /*!<  TIMRSTR register update enable */\n#define HRTIM_BDTUPR_TIMCHPR_Pos      (18U)\n#define HRTIM_BDTUPR_TIMCHPR_Msk      (0x1UL << HRTIM_BDTUPR_TIMCHPR_Pos)      /*!< 0x00040000 */\n#define HRTIM_BDTUPR_TIMCHPR          HRTIM_BDTUPR_TIMCHPR_Msk                 /*!<  TIMCHPR register update enable */\n#define HRTIM_BDTUPR_TIMOUTR_Pos      (19U)\n#define HRTIM_BDTUPR_TIMOUTR_Msk      (0x1UL << HRTIM_BDTUPR_TIMOUTR_Pos)      /*!< 0x00080000 */\n#define HRTIM_BDTUPR_TIMOUTR          HRTIM_BDTUPR_TIMOUTR_Msk                 /*!<  TIMOUTR register update enable */\n#define HRTIM_BDTUPR_TIMFLTR_Pos      (20U)\n#define HRTIM_BDTUPR_TIMFLTR_Msk      (0x1UL << HRTIM_BDTUPR_TIMFLTR_Pos)      /*!< 0x00100000 */\n#define HRTIM_BDTUPR_TIMFLTR          HRTIM_BDTUPR_TIMFLTR_Msk                 /*!<  TIMFLTR register update enable */\n\n/*******************  Bit definition for HRTIM_BDMADR register  ***************/\n#define HRTIM_BDMADR_BDMADR_Pos       (0U)\n#define HRTIM_BDMADR_BDMADR_Msk       (0xFFFFFFFFUL << HRTIM_BDMADR_BDMADR_Pos) /*!< 0xFFFFFFFF */\n#define HRTIM_BDMADR_BDMADR           HRTIM_BDMADR_BDMADR_Msk                  /*!<  Burst DMA Data register */\n\n/******************************************************************************/\n/*                                                                            */\n/*                             RAM ECC monitoring                             */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bit definition for RAMECC_IER register  ******************/\n#define RAMECC_IER_GECCDEBWIE_Pos         (3U)\n#define RAMECC_IER_GECCDEBWIE_Msk         (0x1UL << RAMECC_IER_GECCDEBWIE_Pos)  /*!< 0x00000008 */\n#define RAMECC_IER_GECCDEBWIE             RAMECC_IER_GECCDEBWIE_Msk             /*!< Global ECC double error on byte write (BW) interrupt enable */\n#define RAMECC_IER_GECCDEIE_Pos           (2U)\n#define RAMECC_IER_GECCDEIE_Msk           (0x1UL << RAMECC_IER_GECCDEIE_Pos)    /*!< 0x00000004 */\n#define RAMECC_IER_GECCDEIE               RAMECC_IER_GECCDEIE_Msk               /*!< Global ECC double error interrupt enable */\n#define RAMECC_IER_GECCSEIE_Pos           (1U)\n#define RAMECC_IER_GECCSEIE_Msk           (0x1UL << RAMECC_IER_GECCSEIE_Pos)    /*!< 0x00000002 */\n#define RAMECC_IER_GECCSEIE               RAMECC_IER_GECCSEIE_Msk               /*!< Global ECC single error interrupt enable */\n#define RAMECC_IER_GIE_Pos                (0U)\n#define RAMECC_IER_GIE_Msk                (0x1UL << RAMECC_IER_GIE_Pos)         /*!< 0x00000001 */\n#define RAMECC_IER_GIE                    RAMECC_IER_GIE_Msk                    /*!< Global interrupt enable */\n\n/*******************  Bit definition for RAMECC_CR register  ******************/\n#define RAMECC_CR_ECCELEN_Pos             (5U)\n#define RAMECC_CR_ECCELEN_Msk             (0x1UL << RAMECC_CR_ECCELEN_Pos)      /*!< 0x00000020 */\n#define RAMECC_CR_ECCELEN                 RAMECC_CR_ECCELEN_Msk                 /*!< ECC error latching enable */\n#define RAMECC_CR_ECCDEBWIE_Pos           (4U)\n#define RAMECC_CR_ECCDEBWIE_Msk           (0x1UL << RAMECC_CR_ECCDEBWIE_Pos)    /*!< 0x00000010 */\n#define RAMECC_CR_ECCDEBWIE               RAMECC_CR_ECCDEBWIE_Msk               /*!< ECC double error on byte write (BW) interrupt enable */\n#define RAMECC_CR_ECCDEIE_Pos             (3U)\n#define RAMECC_CR_ECCDEIE_Msk             (0x1UL << RAMECC_CR_ECCDEIE_Pos)      /*!< 0x00000008 */\n#define RAMECC_CR_ECCDEIE                 RAMECC_CR_ECCDEIE_Msk                 /*!< ECC double error interrupt enable */\n#define RAMECC_CR_ECCSEIE_Pos             (2U)\n#define RAMECC_CR_ECCSEIE_Msk             (0x1UL << RAMECC_CR_ECCSEIE_Pos)      /*!< 0x00000004 */\n#define RAMECC_CR_ECCSEIE                 RAMECC_CR_ECCSEIE_Msk                 /*!< ECC single error interrupt enable */\n\n/*******************  Bit definition for RAMECC_SR register  ******************/\n#define RAMECC_SR_DEBWDF_Pos             (2U)\n#define RAMECC_SR_DEBWDF_Msk             (0x1UL << RAMECC_SR_DEBWDF_Pos)        /*!< 0x00000004 */\n#define RAMECC_SR_DEBWDF                 RAMECC_SR_DEBWDF_Msk                   /*!< ECC double error on byte write (BW) detected flag */\n#define RAMECC_SR_DEDF_Pos               (1U)\n#define RAMECC_SR_DEDF_Msk               (0x1UL << RAMECC_SR_DEDF_Pos)          /*!< 0x00000002 */\n#define RAMECC_SR_DEDF                   RAMECC_SR_DEDF_Msk                     /*!< ECC double error detected flag */\n#define RAMECC_SR_SEDCF_Pos              (0U)\n#define RAMECC_SR_SEDCF_Msk              (0x1UL << RAMECC_SR_SEDCF_Pos)         /*!< 0x00000001 */\n#define RAMECC_SR_SEDCF                  RAMECC_SR_SEDCF_Msk                    /*!< ECC single error detected and corrected flag */\n\n/******************  Bit definition for RAMECC_FAR register  ******************/\n#define RAMECC_FAR_FADD_Pos              (0U)\n#define RAMECC_FAR_FADD_Msk              (0xFFFFFFFFUL << RAMECC_FAR_FADD_Pos)  /*!< 0xFFFFFFFF */\n#define RAMECC_FAR_FADD                  RAMECC_FAR_FADD_Msk                    /*!< ECC error failing address */\n\n/******************  Bit definition for RAMECC_FDRL register  *****************/\n#define RAMECC_FAR_FDATAL_Pos            (0U)\n#define RAMECC_FAR_FDATAL_Msk            (0xFFFFFFFFUL << RAMECC_FAR_FDATAL_Pos)/*!< 0xFFFFFFFF */\n#define RAMECC_FAR_FDATAL                RAMECC_FAR_FDATAL_Msk                  /*!< ECC error failing address */\n\n/******************  Bit definition for RAMECC_FDRH register  *****************/\n#define RAMECC_FAR_FDATAH_Pos            (0U)\n#define RAMECC_FAR_FDATAH_Msk            (0xFFFFFFFFUL << RAMECC_FAR_FDATAH_Pos)/*!< 0xFFFFFFFF */\n#define RAMECC_FAR_FDATAH                RAMECC_FAR_FDATAH_Msk                  /* Failing data high (64-bit memory) */\n\n/*****************  Bit definition for RAMECC_FECR register  ******************/\n#define RAMECC_FECR_FEC_Pos              (0U)\n#define RAMECC_FECR_FEC_Msk              (0xFFFFFFFFUL << RAMECC_FECR_FEC_Pos)  /*!< 0xFFFFFFFF */\n#define RAMECC_FECR_FEC                  RAMECC_FECR_FEC_Msk                    /*!< Failing error code */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                MDIOS                                        */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for MDIOS_CR register  *******************/\n#define MDIOS_CR_EN_Pos                (0U)\n#define MDIOS_CR_EN_Msk                (0x1UL << MDIOS_CR_EN_Pos)              /*!< 0x00000001 */\n#define MDIOS_CR_EN                    MDIOS_CR_EN_Msk                         /*!<  MDIOS slave peripheral enable */\n#define MDIOS_CR_WRIE_Pos              (1U)\n#define MDIOS_CR_WRIE_Msk              (0x1UL << MDIOS_CR_WRIE_Pos)            /*!< 0x00000002 */\n#define MDIOS_CR_WRIE                  MDIOS_CR_WRIE_Msk                       /*!<  MDIOS slave register write interrupt enable. */\n#define MDIOS_CR_RDIE_Pos              (2U)\n#define MDIOS_CR_RDIE_Msk              (0x1UL << MDIOS_CR_RDIE_Pos)            /*!< 0x00000004 */\n#define MDIOS_CR_RDIE                  MDIOS_CR_RDIE_Msk                       /*!<  MDIOS slave register read interrupt enable. */\n#define MDIOS_CR_EIE_Pos               (3U)\n#define MDIOS_CR_EIE_Msk               (0x1UL << MDIOS_CR_EIE_Pos)             /*!< 0x00000008 */\n#define MDIOS_CR_EIE                   MDIOS_CR_EIE_Msk                        /*!<  MDIOS slave register error interrupt enable. */\n#define MDIOS_CR_DPC_Pos               (7U)\n#define MDIOS_CR_DPC_Msk               (0x1UL << MDIOS_CR_DPC_Pos)             /*!< 0x00000080 */\n#define MDIOS_CR_DPC                   MDIOS_CR_DPC_Msk                        /*!<  MDIOS slave disable preamble check. */\n#define MDIOS_CR_PORT_ADDRESS_Pos      (8U)\n#define MDIOS_CR_PORT_ADDRESS_Msk      (0x1FUL << MDIOS_CR_PORT_ADDRESS_Pos)   /*!< 0x00001F00 */\n#define MDIOS_CR_PORT_ADDRESS          MDIOS_CR_PORT_ADDRESS_Msk               /*!<  MDIOS slave port address mask. */\n#define MDIOS_CR_PORT_ADDRESS_0        (0x01UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000100 */\n#define MDIOS_CR_PORT_ADDRESS_1        (0x02UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000200 */\n#define MDIOS_CR_PORT_ADDRESS_2        (0x04UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000400 */\n#define MDIOS_CR_PORT_ADDRESS_3        (0x08UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000800 */\n#define MDIOS_CR_PORT_ADDRESS_4        (0x10UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00001000 */\n\n/********************  Bit definition for MDIOS_SR register  *******************/\n#define MDIOS_SR_PERF_Pos              (0U)\n#define MDIOS_SR_PERF_Msk              (0x1UL << MDIOS_SR_PERF_Pos)            /*!< 0x00000001 */\n#define MDIOS_SR_PERF                  MDIOS_SR_PERF_Msk                       /*!<  MDIOS slave turnaround error flag*/\n#define MDIOS_SR_SERF_Pos              (1U)\n#define MDIOS_SR_SERF_Msk              (0x1UL << MDIOS_SR_SERF_Pos)            /*!< 0x00000002 */\n#define MDIOS_SR_SERF                  MDIOS_SR_SERF_Msk                       /*!<  MDIOS slave start error flag */\n#define MDIOS_SR_TERF_Pos              (2U)\n#define MDIOS_SR_TERF_Msk              (0x1UL << MDIOS_SR_TERF_Pos)            /*!< 0x00000004 */\n#define MDIOS_SR_TERF                  MDIOS_SR_TERF_Msk                       /*!<  MDIOS slave preamble error flag */\n\n/********************  Bit definition for MDIOS_CLRFR register  *******************/\n#define MDIOS_SR_CPERF_Pos             (0U)\n#define MDIOS_SR_CPERF_Msk             (0x1UL << MDIOS_SR_CPERF_Pos)           /*!< 0x00000001 */\n#define MDIOS_SR_CPERF                 MDIOS_SR_CPERF_Msk                      /*!<  MDIOS slave Clear the turnaround error flag */\n#define MDIOS_SR_CSERF_Pos             (1U)\n#define MDIOS_SR_CSERF_Msk             (0x1UL << MDIOS_SR_CSERF_Pos)           /*!< 0x00000002 */\n#define MDIOS_SR_CSERF                 MDIOS_SR_CSERF_Msk                      /*!<  MDIOS slave Clear the start error flag */\n#define MDIOS_SR_CTERF_Pos             (2U)\n#define MDIOS_SR_CTERF_Msk             (0x1UL << MDIOS_SR_CTERF_Pos)           /*!< 0x00000004 */\n#define MDIOS_SR_CTERF                 MDIOS_SR_CTERF_Msk                      /*!<  MDIOS slave Clear the preamble error flag */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                       USB_OTG                              */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition forUSB_OTG_GOTGCTL register  ********************/\n#define USB_OTG_GOTGCTL_SRQSCS_Pos               (0U)\n#define USB_OTG_GOTGCTL_SRQSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */\n#define USB_OTG_GOTGCTL_SRQSCS                   USB_OTG_GOTGCTL_SRQSCS_Msk    /*!< Session request success */\n#define USB_OTG_GOTGCTL_SRQ_Pos                  (1U)\n#define USB_OTG_GOTGCTL_SRQ_Msk                  (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */\n#define USB_OTG_GOTGCTL_SRQ                      USB_OTG_GOTGCTL_SRQ_Msk       /*!< Session request */\n#define USB_OTG_GOTGCTL_VBVALOEN_Pos             (2U)\n#define USB_OTG_GOTGCTL_VBVALOEN_Msk             (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */\n#define USB_OTG_GOTGCTL_VBVALOEN                 USB_OTG_GOTGCTL_VBVALOEN_Msk  /*!< VBUS valid override enable */\n#define USB_OTG_GOTGCTL_VBVALOVAL_Pos            (3U)\n#define USB_OTG_GOTGCTL_VBVALOVAL_Msk            (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */\n#define USB_OTG_GOTGCTL_VBVALOVAL                USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */\n#define USB_OTG_GOTGCTL_AVALOEN_Pos              (4U)\n#define USB_OTG_GOTGCTL_AVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */\n#define USB_OTG_GOTGCTL_AVALOEN                  USB_OTG_GOTGCTL_AVALOEN_Msk   /*!< A-peripheral session valid override enable */\n#define USB_OTG_GOTGCTL_AVALOVAL_Pos             (5U)\n#define USB_OTG_GOTGCTL_AVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */\n#define USB_OTG_GOTGCTL_AVALOVAL                 USB_OTG_GOTGCTL_AVALOVAL_Msk  /*!< A-peripheral session valid override value */\n#define USB_OTG_GOTGCTL_BVALOEN_Pos              (6U)\n#define USB_OTG_GOTGCTL_BVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */\n#define USB_OTG_GOTGCTL_BVALOEN                  USB_OTG_GOTGCTL_BVALOEN_Msk   /*!< B-peripheral session valid override enable */\n#define USB_OTG_GOTGCTL_BVALOVAL_Pos             (7U)\n#define USB_OTG_GOTGCTL_BVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */\n#define USB_OTG_GOTGCTL_BVALOVAL                 USB_OTG_GOTGCTL_BVALOVAL_Msk  /*!< B-peripheral session valid override value  */\n#define USB_OTG_GOTGCTL_HNGSCS_Pos               (8U)\n#define USB_OTG_GOTGCTL_HNGSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */\n#define USB_OTG_GOTGCTL_HNGSCS                   USB_OTG_GOTGCTL_HNGSCS_Msk    /*!< Host set HNP enable */\n#define USB_OTG_GOTGCTL_HNPRQ_Pos                (9U)\n#define USB_OTG_GOTGCTL_HNPRQ_Msk                (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */\n#define USB_OTG_GOTGCTL_HNPRQ                    USB_OTG_GOTGCTL_HNPRQ_Msk     /*!< HNP request */\n#define USB_OTG_GOTGCTL_HSHNPEN_Pos              (10U)\n#define USB_OTG_GOTGCTL_HSHNPEN_Msk              (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */\n#define USB_OTG_GOTGCTL_HSHNPEN                  USB_OTG_GOTGCTL_HSHNPEN_Msk   /*!< Host set HNP enable */\n#define USB_OTG_GOTGCTL_DHNPEN_Pos               (11U)\n#define USB_OTG_GOTGCTL_DHNPEN_Msk               (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */\n#define USB_OTG_GOTGCTL_DHNPEN                   USB_OTG_GOTGCTL_DHNPEN_Msk    /*!< Device HNP enabled */\n#define USB_OTG_GOTGCTL_EHEN_Pos                 (12U)\n#define USB_OTG_GOTGCTL_EHEN_Msk                 (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */\n#define USB_OTG_GOTGCTL_EHEN                     USB_OTG_GOTGCTL_EHEN_Msk      /*!< Embedded host enable */\n#define USB_OTG_GOTGCTL_CIDSTS_Pos               (16U)\n#define USB_OTG_GOTGCTL_CIDSTS_Msk               (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */\n#define USB_OTG_GOTGCTL_CIDSTS                   USB_OTG_GOTGCTL_CIDSTS_Msk    /*!< Connector ID status */\n#define USB_OTG_GOTGCTL_DBCT_Pos                 (17U)\n#define USB_OTG_GOTGCTL_DBCT_Msk                 (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */\n#define USB_OTG_GOTGCTL_DBCT                     USB_OTG_GOTGCTL_DBCT_Msk      /*!< Long/short debounce time */\n#define USB_OTG_GOTGCTL_ASVLD_Pos                (18U)\n#define USB_OTG_GOTGCTL_ASVLD_Msk                (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */\n#define USB_OTG_GOTGCTL_ASVLD                    USB_OTG_GOTGCTL_ASVLD_Msk     /*!< A-session valid  */\n#define USB_OTG_GOTGCTL_BSESVLD_Pos              (19U)\n#define USB_OTG_GOTGCTL_BSESVLD_Msk              (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */\n#define USB_OTG_GOTGCTL_BSESVLD                  USB_OTG_GOTGCTL_BSESVLD_Msk   /*!< B-session valid */\n#define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)\n#define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */\n#define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk    /*!< OTG version  */\n\n/********************  Bit definition forUSB_OTG_HCFG register  ********************/\n\n#define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)\n#define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */\n#define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select  */\n#define USB_OTG_HCFG_FSLSPCS_0                   (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */\n#define USB_OTG_HCFG_FSLSPCS_1                   (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */\n#define USB_OTG_HCFG_FSLSS_Pos                   (2U)\n#define USB_OTG_HCFG_FSLSS_Msk                   (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */\n#define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk        /*!< FS- and LS-only support */\n\n/********************  Bit definition forUSB_OTG_DCFG register  ********************/\n\n#define USB_OTG_DCFG_DSPD_Pos                    (0U)\n#define USB_OTG_DCFG_DSPD_Msk                    (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */\n#define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk         /*!< Device speed */\n#define USB_OTG_DCFG_DSPD_0                      (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */\n#define USB_OTG_DCFG_DSPD_1                      (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */\n#define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)\n#define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */\n#define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */\n\n#define USB_OTG_DCFG_DAD_Pos                     (4U)\n#define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */\n#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */\n#define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */\n#define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */\n#define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */\n#define USB_OTG_DCFG_DAD_3                       (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */\n#define USB_OTG_DCFG_DAD_4                       (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */\n#define USB_OTG_DCFG_DAD_5                       (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */\n#define USB_OTG_DCFG_DAD_6                       (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */\n\n#define USB_OTG_DCFG_PFIVL_Pos                   (11U)\n#define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */\n#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */\n#define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */\n#define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */\n\n#define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)\n#define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */\n#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */\n#define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */\n#define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */\n\n/********************  Bit definition forUSB_OTG_PCGCR register  ********************/\n#define USB_OTG_PCGCR_STPPCLK_Pos                (0U)\n#define USB_OTG_PCGCR_STPPCLK_Msk                (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */\n#define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCR_STPPCLK_Msk     /*!< Stop PHY clock */\n#define USB_OTG_PCGCR_GATEHCLK_Pos               (1U)\n#define USB_OTG_PCGCR_GATEHCLK_Msk               (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */\n#define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCR_GATEHCLK_Msk    /*!< Gate HCLK */\n#define USB_OTG_PCGCR_PHYSUSP_Pos                (4U)\n#define USB_OTG_PCGCR_PHYSUSP_Msk                (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */\n#define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCR_PHYSUSP_Msk     /*!< PHY suspended */\n\n/********************  Bit definition forUSB_OTG_GOTGINT register  ********************/\n#define USB_OTG_GOTGINT_SEDET_Pos                (2U)\n#define USB_OTG_GOTGINT_SEDET_Msk                (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */\n#define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk     /*!< Session end detected                   */\n#define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)\n#define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */\n#define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk   /*!< Session request success status change  */\n#define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)\n#define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */\n#define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */\n#define USB_OTG_GOTGINT_HNGDET_Pos               (17U)\n#define USB_OTG_GOTGINT_HNGDET_Msk               (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */\n#define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk    /*!< Host negotiation detected              */\n#define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)\n#define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */\n#define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change                */\n#define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)\n#define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */\n#define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk    /*!< Debounce done                          */\n\n/********************  Bit definition forUSB_OTG_DCTL register  ********************/\n#define USB_OTG_DCTL_RWUSIG_Pos                  (0U)\n#define USB_OTG_DCTL_RWUSIG_Msk                  (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */\n#define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */\n#define USB_OTG_DCTL_SDIS_Pos                    (1U)\n#define USB_OTG_DCTL_SDIS_Msk                    (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */\n#define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk         /*!< Soft disconnect         */\n#define USB_OTG_DCTL_GINSTS_Pos                  (2U)\n#define USB_OTG_DCTL_GINSTS_Msk                  (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */\n#define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk       /*!< Global IN NAK status    */\n#define USB_OTG_DCTL_GONSTS_Pos                  (3U)\n#define USB_OTG_DCTL_GONSTS_Msk                  (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */\n#define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk       /*!< Global OUT NAK status   */\n\n#define USB_OTG_DCTL_TCTL_Pos                    (4U)\n#define USB_OTG_DCTL_TCTL_Msk                    (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */\n#define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk         /*!< Test control */\n#define USB_OTG_DCTL_TCTL_0                      (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */\n#define USB_OTG_DCTL_TCTL_1                      (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */\n#define USB_OTG_DCTL_TCTL_2                      (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */\n#define USB_OTG_DCTL_SGINAK_Pos                  (7U)\n#define USB_OTG_DCTL_SGINAK_Msk                  (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */\n#define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk       /*!< Set global IN NAK         */\n#define USB_OTG_DCTL_CGINAK_Pos                  (8U)\n#define USB_OTG_DCTL_CGINAK_Msk                  (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */\n#define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk       /*!< Clear global IN NAK       */\n#define USB_OTG_DCTL_SGONAK_Pos                  (9U)\n#define USB_OTG_DCTL_SGONAK_Msk                  (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */\n#define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk       /*!< Set global OUT NAK        */\n#define USB_OTG_DCTL_CGONAK_Pos                  (10U)\n#define USB_OTG_DCTL_CGONAK_Msk                  (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */\n#define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk       /*!< Clear global OUT NAK      */\n#define USB_OTG_DCTL_POPRGDNE_Pos                (11U)\n#define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */\n#define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */\n\n/********************  Bit definition forUSB_OTG_HFIR register  ********************/\n#define USB_OTG_HFIR_FRIVL_Pos                   (0U)\n#define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk        /*!< Frame interval */\n\n/********************  Bit definition forUSB_OTG_HFNUM register  ********************/\n#define USB_OTG_HFNUM_FRNUM_Pos                  (0U)\n#define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk       /*!< Frame number         */\n#define USB_OTG_HFNUM_FTREM_Pos                  (16U)\n#define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk       /*!< Frame time remaining */\n\n/********************  Bit definition forUSB_OTG_DSTS register  ********************/\n#define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)\n#define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */\n#define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk      /*!< Suspend status   */\n\n#define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)\n#define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */\n#define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk      /*!< Enumerated speed */\n#define USB_OTG_DSTS_ENUMSPD_0                   (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */\n#define USB_OTG_DSTS_ENUMSPD_1                   (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */\n#define USB_OTG_DSTS_EERR_Pos                    (3U)\n#define USB_OTG_DSTS_EERR_Msk                    (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */\n#define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk         /*!< Erratic error     */\n#define USB_OTG_DSTS_FNSOF_Pos                   (8U)\n#define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */\n#define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */\n\n/********************  Bit definition forUSB_OTG_GAHBCFG register  ********************/\n#define USB_OTG_GAHBCFG_GINT_Pos                 (0U)\n#define USB_OTG_GAHBCFG_GINT_Msk                 (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */\n#define USB_OTG_GAHBCFG_GINT                     USB_OTG_GAHBCFG_GINT_Msk      /*!< Global interrupt mask */\n\n#define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)\n#define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */\n#define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */\n#define USB_OTG_GAHBCFG_HBSTLEN_0                (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */\n#define USB_OTG_GAHBCFG_HBSTLEN_1                (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */\n#define USB_OTG_GAHBCFG_HBSTLEN_2                (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */\n#define USB_OTG_GAHBCFG_HBSTLEN_3                (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */\n#define USB_OTG_GAHBCFG_HBSTLEN_4                (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */\n#define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)\n#define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */\n#define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk     /*!< DMA enable */\n#define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)\n#define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */\n#define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */\n#define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)\n#define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */\n#define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */\n\n/********************  Bit definition forUSB_OTG_GUSBCFG register  ********************/\n\n#define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)\n#define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */\n#define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */\n#define USB_OTG_GUSBCFG_TOCAL_0                  (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */\n#define USB_OTG_GUSBCFG_TOCAL_1                  (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */\n#define USB_OTG_GUSBCFG_TOCAL_2                  (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */\n#define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)\n#define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */\n#define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */\n#define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)\n#define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */\n#define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */\n#define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)\n#define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */\n#define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */\n\n#define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)\n#define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */\n#define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk      /*!< USB turnaround time */\n#define USB_OTG_GUSBCFG_TRDT_0                   (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */\n#define USB_OTG_GUSBCFG_TRDT_1                   (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */\n#define USB_OTG_GUSBCFG_TRDT_2                   (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */\n#define USB_OTG_GUSBCFG_TRDT_3                   (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */\n#define USB_OTG_GUSBCFG_PHYLPCS_Pos              (15U)\n#define USB_OTG_GUSBCFG_PHYLPCS_Msk              (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */\n#define USB_OTG_GUSBCFG_PHYLPCS                  USB_OTG_GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */\n#define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)\n#define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */\n#define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select               */\n#define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)\n#define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */\n#define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume                */\n#define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)\n#define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */\n#define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM             */\n#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)\n#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */\n#define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive        */\n#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)\n#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */\n#define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator    */\n#define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)\n#define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */\n#define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */\n#define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)\n#define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */\n#define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk      /*!< Indicator complement            */\n#define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)\n#define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */\n#define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk      /*!< Indicator pass through          */\n#define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)\n#define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */\n#define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable  */\n#define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)\n#define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */\n#define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk     /*!< Forced host mode                */\n#define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)\n#define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */\n#define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */\n#define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)\n#define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */\n#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */\n\n/********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/\n#define USB_OTG_GRSTCTL_CSRST_Pos                (0U)\n#define USB_OTG_GRSTCTL_CSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */\n#define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk     /*!< Core soft reset          */\n#define USB_OTG_GRSTCTL_HSRST_Pos                (1U)\n#define USB_OTG_GRSTCTL_HSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */\n#define USB_OTG_GRSTCTL_HSRST                    USB_OTG_GRSTCTL_HSRST_Msk     /*!< HCLK soft reset          */\n#define USB_OTG_GRSTCTL_FCRST_Pos                (2U)\n#define USB_OTG_GRSTCTL_FCRST_Msk                (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */\n#define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */\n#define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)\n#define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */\n#define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush             */\n#define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)\n#define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */\n#define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush             */\n\n#define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)\n#define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */\n#define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */\n#define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */\n#define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */\n#define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */\n#define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */\n#define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */\n#define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)\n#define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */\n#define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */\n#define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)\n#define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */\n#define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */\n\n/********************  Bit definition forUSB_OTG_DIEPMSK register  ********************/\n#define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)\n#define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask                 */\n#define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)\n#define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask                  */\n#define USB_OTG_DIEPMSK_TOM_Pos                  (3U)\n#define USB_OTG_DIEPMSK_TOM_Msk                  (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */\n#define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */\n#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)\n#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */\n#define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */\n#define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)\n#define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */\n#define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask           */\n#define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)\n#define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */\n#define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask                    */\n#define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)\n#define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */\n#define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask                                */\n#define USB_OTG_DIEPMSK_BIM_Pos                  (9U)\n#define USB_OTG_DIEPMSK_BIM_Msk                  (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */\n#define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk       /*!< BNA interrupt mask                                */\n\n/********************  Bit definition forUSB_OTG_HPTXSTS register  ********************/\n#define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)\n#define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available     */\n\n#define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)\n#define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */\n#define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */\n#define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */\n\n#define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)\n#define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */\n#define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */\n\n/********************  Bit definition forUSB_OTG_HAINT register  ********************/\n#define USB_OTG_HAINT_HAINT_Pos                  (0U)\n#define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk       /*!< Channel interrupts */\n\n/********************  Bit definition forUSB_OTG_DOEPMSK register  ********************/\n#define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)\n#define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask */\n#define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)\n#define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask               */\n#define USB_OTG_DOEPMSK_AHBERRM_Pos              (2U)\n#define USB_OTG_DOEPMSK_AHBERRM_Msk              (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */\n#define USB_OTG_DOEPMSK_AHBERRM                  USB_OTG_DOEPMSK_AHBERRM_Msk      /*!< OUT transaction AHB Error interrupt mask               */\n#define USB_OTG_DOEPMSK_STUPM_Pos                (3U)\n#define USB_OTG_DOEPMSK_STUPM_Msk                (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */\n#define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask                          */\n#define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)\n#define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */\n#define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */\n#define USB_OTG_DOEPMSK_OTEPSPRM_Pos             (5U)\n#define USB_OTG_DOEPMSK_OTEPSPRM_Msk             (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */\n#define USB_OTG_DOEPMSK_OTEPSPRM                 USB_OTG_DOEPMSK_OTEPSPRM_Msk  /*!< Status Phase Received mask                     */\n#define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)\n#define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */\n#define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask       */\n#define USB_OTG_DOEPMSK_OPEM_Pos                 (8U)\n#define USB_OTG_DOEPMSK_OPEM_Msk                 (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */\n#define USB_OTG_DOEPMSK_OPEM                     USB_OTG_DOEPMSK_OPEM_Msk      /*!< OUT packet error mask                          */\n#define USB_OTG_DOEPMSK_BOIM_Pos                 (9U)\n#define USB_OTG_DOEPMSK_BOIM_Msk                 (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */\n#define USB_OTG_DOEPMSK_BOIM                     USB_OTG_DOEPMSK_BOIM_Msk      /*!< BNA interrupt mask                             */\n#define USB_OTG_DOEPMSK_BERRM_Pos                (12U)\n#define USB_OTG_DOEPMSK_BERRM_Msk                (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */\n#define USB_OTG_DOEPMSK_BERRM                    USB_OTG_DOEPMSK_BERRM_Msk      /*!< Babble error interrupt mask               */\n#define USB_OTG_DOEPMSK_NAKM_Pos                 (13U)\n#define USB_OTG_DOEPMSK_NAKM_Msk                 (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */\n#define USB_OTG_DOEPMSK_NAKM                     USB_OTG_DOEPMSK_NAKM_Msk      /*!< OUT Packet NAK interrupt mask               */\n#define USB_OTG_DOEPMSK_NYETM_Pos                (14U)\n#define USB_OTG_DOEPMSK_NYETM_Msk                (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */\n#define USB_OTG_DOEPMSK_NYETM                    USB_OTG_DOEPMSK_NYETM_Msk      /*!< NYET interrupt mask                */\n\n/********************  Bit definition forUSB_OTG_GINTSTS register  ********************/\n#define USB_OTG_GINTSTS_CMOD_Pos                 (0U)\n#define USB_OTG_GINTSTS_CMOD_Msk                 (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */\n#define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk      /*!< Current mode of operation                      */\n#define USB_OTG_GINTSTS_MMIS_Pos                 (1U)\n#define USB_OTG_GINTSTS_MMIS_Msk                 (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */\n#define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt                        */\n#define USB_OTG_GINTSTS_OTGINT_Pos               (2U)\n#define USB_OTG_GINTSTS_OTGINT_Msk               (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */\n#define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk    /*!< OTG interrupt                                  */\n#define USB_OTG_GINTSTS_SOF_Pos                  (3U)\n#define USB_OTG_GINTSTS_SOF_Msk                  (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */\n#define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk       /*!< Start of frame                                 */\n#define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)\n#define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */\n#define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty                                */\n#define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)\n#define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */\n#define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty                       */\n#define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)\n#define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */\n#define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective            */\n#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos           (7U)\n#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk           (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */\n#define USB_OTG_GINTSTS_BOUTNAKEFF               USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective                       */\n#define USB_OTG_GINTSTS_ESUSP_Pos                (10U)\n#define USB_OTG_GINTSTS_ESUSP_Msk                (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */\n#define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk     /*!< Early suspend                                  */\n#define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)\n#define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */\n#define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk   /*!< USB suspend                                    */\n#define USB_OTG_GINTSTS_USBRST_Pos               (12U)\n#define USB_OTG_GINTSTS_USBRST_Msk               (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */\n#define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk    /*!< USB reset                                      */\n#define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)\n#define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */\n#define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk   /*!< Enumeration done                               */\n#define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)\n#define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */\n#define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt       */\n#define USB_OTG_GINTSTS_EOPF_Pos                 (15U)\n#define USB_OTG_GINTSTS_EOPF_Msk                 (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */\n#define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt                */\n#define USB_OTG_GINTSTS_IEPINT_Pos               (18U)\n#define USB_OTG_GINTSTS_IEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */\n#define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt                          */\n#define USB_OTG_GINTSTS_OEPINT_Pos               (19U)\n#define USB_OTG_GINTSTS_OEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */\n#define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt                         */\n#define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)\n#define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */\n#define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer             */\n#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)\n#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */\n#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer                   */\n#define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)\n#define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */\n#define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended                           */\n#define USB_OTG_GINTSTS_RSTDET_Pos               (23U)\n#define USB_OTG_GINTSTS_RSTDET_Msk               (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */\n#define USB_OTG_GINTSTS_RSTDET                   USB_OTG_GINTSTS_RSTDET_Msk    /*!< Reset detected interrupt                       */\n#define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)\n#define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */\n#define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk   /*!< Host port interrupt                            */\n#define USB_OTG_GINTSTS_HCINT_Pos                (25U)\n#define USB_OTG_GINTSTS_HCINT_Msk                (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */\n#define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk     /*!< Host channels interrupt                        */\n#define USB_OTG_GINTSTS_PTXFE_Pos                (26U)\n#define USB_OTG_GINTSTS_PTXFE_Msk                (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */\n#define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty                          */\n#define USB_OTG_GINTSTS_LPMINT_Pos               (27U)\n#define USB_OTG_GINTSTS_LPMINT_Msk               (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */\n#define USB_OTG_GINTSTS_LPMINT                   USB_OTG_GINTSTS_LPMINT_Msk    /*!< LPM interrupt                                  */\n#define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)\n#define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */\n#define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change                     */\n#define USB_OTG_GINTSTS_DISCINT_Pos              (29U)\n#define USB_OTG_GINTSTS_DISCINT_Msk              (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */\n#define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt                  */\n#define USB_OTG_GINTSTS_SRQINT_Pos               (30U)\n#define USB_OTG_GINTSTS_SRQINT_Msk               (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */\n#define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */\n#define USB_OTG_GINTSTS_WKUINT_Pos               (31U)\n#define USB_OTG_GINTSTS_WKUINT_Msk               (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */\n#define USB_OTG_GINTSTS_WKUINT                   USB_OTG_GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt        */\n\n/********************  Bit definition forUSB_OTG_GINTMSK register  ********************/\n#define USB_OTG_GINTMSK_MMISM_Pos                (1U)\n#define USB_OTG_GINTMSK_MMISM_Msk                (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */\n#define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask                        */\n#define USB_OTG_GINTMSK_OTGINT_Pos               (2U)\n#define USB_OTG_GINTMSK_OTGINT_Msk               (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */\n#define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask                                  */\n#define USB_OTG_GINTMSK_SOFM_Pos                 (3U)\n#define USB_OTG_GINTMSK_SOFM_Msk                 (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */\n#define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk      /*!< Start of frame mask                                 */\n#define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)\n#define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */\n#define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask                          */\n#define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)\n#define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */\n#define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask                       */\n#define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)\n#define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */\n#define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask            */\n#define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)\n#define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */\n#define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask                       */\n#define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)\n#define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */\n#define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk    /*!< Early suspend mask                                  */\n#define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)\n#define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */\n#define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask                                    */\n#define USB_OTG_GINTMSK_USBRST_Pos               (12U)\n#define USB_OTG_GINTMSK_USBRST_Msk               (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */\n#define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk    /*!< USB reset mask                                      */\n#define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)\n#define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */\n#define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask                               */\n#define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)\n#define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */\n#define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask       */\n#define USB_OTG_GINTMSK_EOPFM_Pos                (15U)\n#define USB_OTG_GINTMSK_EOPFM_Msk                (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */\n#define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask                */\n#define USB_OTG_GINTMSK_EPMISM_Pos               (17U)\n#define USB_OTG_GINTMSK_EPMISM_Msk               (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */\n#define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask                    */\n#define USB_OTG_GINTMSK_IEPINT_Pos               (18U)\n#define USB_OTG_GINTMSK_IEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */\n#define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask                         */\n#define USB_OTG_GINTMSK_OEPINT_Pos               (19U)\n#define USB_OTG_GINTMSK_OEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */\n#define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask                        */\n#define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)\n#define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */\n#define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask             */\n#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)\n#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */\n#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM          USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask                   */\n#define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)\n#define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */\n#define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask                           */\n#define USB_OTG_GINTMSK_RSTDEM_Pos               (23U)\n#define USB_OTG_GINTMSK_RSTDEM_Msk               (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */\n#define USB_OTG_GINTMSK_RSTDEM                   USB_OTG_GINTMSK_RSTDEM_Msk    /*!< Reset detected interrupt mask                      */\n#define USB_OTG_GINTMSK_PRTIM_Pos                (24U)\n#define USB_OTG_GINTMSK_PRTIM_Msk                (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */\n#define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask                            */\n#define USB_OTG_GINTMSK_HCIM_Pos                 (25U)\n#define USB_OTG_GINTMSK_HCIM_Msk                 (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */\n#define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask                        */\n#define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)\n#define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */\n#define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask                          */\n#define USB_OTG_GINTMSK_LPMINTM_Pos              (27U)\n#define USB_OTG_GINTMSK_LPMINTM_Msk              (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */\n#define USB_OTG_GINTMSK_LPMINTM                  USB_OTG_GINTMSK_LPMINTM_Msk   /*!< LPM interrupt Mask                                  */\n#define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)\n#define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */\n#define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask                     */\n#define USB_OTG_GINTMSK_DISCINT_Pos              (29U)\n#define USB_OTG_GINTMSK_DISCINT_Msk              (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */\n#define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask                  */\n#define USB_OTG_GINTMSK_SRQIM_Pos                (30U)\n#define USB_OTG_GINTMSK_SRQIM_Msk                (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */\n#define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */\n#define USB_OTG_GINTMSK_WUIM_Pos                 (31U)\n#define USB_OTG_GINTMSK_WUIM_Msk                 (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */\n#define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask        */\n\n/********************  Bit definition forUSB_OTG_DAINT register  ********************/\n#define USB_OTG_DAINT_IEPINT_Pos                 (0U)\n#define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits  */\n#define USB_OTG_DAINT_OEPINT_Pos                 (16U)\n#define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */\n\n/********************  Bit definition forUSB_OTG_HAINTMSK register  ********************/\n#define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)\n#define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */\n\n/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/\n#define USB_OTG_GRXSTSP_EPNUM_Pos                (0U)\n#define USB_OTG_GRXSTSP_EPNUM_Msk                (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */\n#define USB_OTG_GRXSTSP_EPNUM                    USB_OTG_GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits  */\n#define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)\n#define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */\n#define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */\n#define USB_OTG_GRXSTSP_DPID_Pos                 (15U)\n#define USB_OTG_GRXSTSP_DPID_Msk                 (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */\n#define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */\n#define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)\n#define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */\n#define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */\n\n/********************  Bit definition forUSB_OTG_DAINTMSK register  ********************/\n#define USB_OTG_DAINTMSK_IEPM_Pos                (0U)\n#define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */\n#define USB_OTG_DAINTMSK_OEPM_Pos                (16U)\n#define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */\n\n/********************  Bit definition for OTG register  ********************/\n\n#define USB_OTG_CHNUM_Pos                        (0U)\n#define USB_OTG_CHNUM_Msk                        (0xFUL << USB_OTG_CHNUM_Pos)  /*!< 0x0000000F */\n#define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */\n#define USB_OTG_CHNUM_0                          (0x1UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */\n#define USB_OTG_CHNUM_1                          (0x2UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */\n#define USB_OTG_CHNUM_2                          (0x4UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */\n#define USB_OTG_CHNUM_3                          (0x8UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */\n#define USB_OTG_BCNT_Pos                         (4U)\n#define USB_OTG_BCNT_Msk                         (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */\n#define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */\n\n#define USB_OTG_DPID_Pos                         (15U)\n#define USB_OTG_DPID_Msk                         (0x3UL << USB_OTG_DPID_Pos)   /*!< 0x00018000 */\n#define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */\n#define USB_OTG_DPID_0                           (0x1UL << USB_OTG_DPID_Pos)    /*!< 0x00008000 */\n#define USB_OTG_DPID_1                           (0x2UL << USB_OTG_DPID_Pos)    /*!< 0x00010000 */\n\n#define USB_OTG_PKTSTS_Pos                       (17U)\n#define USB_OTG_PKTSTS_Msk                       (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */\n#define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */\n#define USB_OTG_PKTSTS_0                         (0x1UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */\n#define USB_OTG_PKTSTS_1                         (0x2UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */\n#define USB_OTG_PKTSTS_2                         (0x4UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */\n#define USB_OTG_PKTSTS_3                         (0x8UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */\n\n#define USB_OTG_EPNUM_Pos                        (0U)\n#define USB_OTG_EPNUM_Msk                        (0xFUL << USB_OTG_EPNUM_Pos)  /*!< 0x0000000F */\n#define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */\n#define USB_OTG_EPNUM_0                          (0x1UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */\n#define USB_OTG_EPNUM_1                          (0x2UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */\n#define USB_OTG_EPNUM_2                          (0x4UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */\n#define USB_OTG_EPNUM_3                          (0x8UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */\n\n#define USB_OTG_FRMNUM_Pos                       (21U)\n#define USB_OTG_FRMNUM_Msk                       (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */\n#define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */\n#define USB_OTG_FRMNUM_0                         (0x1UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */\n#define USB_OTG_FRMNUM_1                         (0x2UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */\n#define USB_OTG_FRMNUM_2                         (0x4UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */\n#define USB_OTG_FRMNUM_3                         (0x8UL << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */\n\n/********************  Bit definition forUSB_OTG_GRXFSIZ register  ********************/\n#define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)\n#define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */\n\n/********************  Bit definition forUSB_OTG_DVBUSDIS register  ********************/\n#define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)\n#define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */\n\n/********************  Bit definition for OTG register  ********************/\n#define USB_OTG_NPTXFSA_Pos                      (0U)\n#define USB_OTG_NPTXFSA_Msk                      (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */\n#define USB_OTG_NPTXFD_Pos                       (16U)\n#define USB_OTG_NPTXFD_Msk                       (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth               */\n#define USB_OTG_TX0FSA_Pos                       (0U)\n#define USB_OTG_TX0FSA_Msk                       (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address  */\n#define USB_OTG_TX0FD_Pos                        (16U)\n#define USB_OTG_TX0FD_Msk                        (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth                */\n\n/********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/\n#define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)\n#define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */\n#define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */\n\n/********************  Bit definition forUSB_OTG_GNPTXSTS register  ********************/\n#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)\n#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */\n\n#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)\n#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */\n\n#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)\n#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */\n\n/********************  Bit definition forUSB_OTG_DTHRCTL register  ********************/\n#define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)\n#define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */\n#define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */\n#define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)\n#define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */\n#define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */\n\n#define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)\n#define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */\n#define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */\n#define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */\n#define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)\n#define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */\n#define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */\n\n#define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)\n#define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */\n#define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */\n#define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)\n#define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */\n#define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */\n\n/********************  Bit definition forUSB_OTG_DIEPEMPMSK register  ********************/\n#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)\n#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */\n\n/********************  Bit definition forUSB_OTG_DEACHINT register  ********************/\n#define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)\n#define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */\n#define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit   */\n#define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)\n#define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */\n#define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */\n\n/********************  Bit definition forUSB_OTG_GCCFG register  ********************/\n#define USB_OTG_GCCFG_DCDET_Pos                  (0U)\n#define USB_OTG_GCCFG_DCDET_Msk                  (0x1UL << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */\n#define USB_OTG_GCCFG_DCDET                      USB_OTG_GCCFG_DCDET_Msk       /*!< Data contact detection (DCD) status */\n#define USB_OTG_GCCFG_PDET_Pos                   (1U)\n#define USB_OTG_GCCFG_PDET_Msk                   (0x1UL << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */\n#define USB_OTG_GCCFG_PDET                       USB_OTG_GCCFG_PDET_Msk        /*!< Primary detection (PD) status */\n#define USB_OTG_GCCFG_SDET_Pos                   (2U)\n#define USB_OTG_GCCFG_SDET_Msk                   (0x1UL << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */\n#define USB_OTG_GCCFG_SDET                       USB_OTG_GCCFG_SDET_Msk        /*!< Secondary detection (SD) status */\n#define USB_OTG_GCCFG_PS2DET_Pos                 (3U)\n#define USB_OTG_GCCFG_PS2DET_Msk                 (0x1UL << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */\n#define USB_OTG_GCCFG_PS2DET                     USB_OTG_GCCFG_PS2DET_Msk      /*!< DM pull-up detection status */\n#define USB_OTG_GCCFG_PWRDWN_Pos                 (16U)\n#define USB_OTG_GCCFG_PWRDWN_Msk                 (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */\n#define USB_OTG_GCCFG_PWRDWN                     USB_OTG_GCCFG_PWRDWN_Msk      /*!< Power down */\n#define USB_OTG_GCCFG_BCDEN_Pos                  (17U)\n#define USB_OTG_GCCFG_BCDEN_Msk                  (0x1UL << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */\n#define USB_OTG_GCCFG_BCDEN                      USB_OTG_GCCFG_BCDEN_Msk       /*!< Battery charging detector (BCD) enable */\n#define USB_OTG_GCCFG_DCDEN_Pos                  (18U)\n#define USB_OTG_GCCFG_DCDEN_Msk                  (0x1UL << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */\n#define USB_OTG_GCCFG_DCDEN                      USB_OTG_GCCFG_DCDEN_Msk       /*!< Data contact detection (DCD) mode enable*/\n#define USB_OTG_GCCFG_PDEN_Pos                   (19U)\n#define USB_OTG_GCCFG_PDEN_Msk                   (0x1UL << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */\n#define USB_OTG_GCCFG_PDEN                       USB_OTG_GCCFG_PDEN_Msk        /*!< Primary detection (PD) mode enable*/\n#define USB_OTG_GCCFG_SDEN_Pos                   (20U)\n#define USB_OTG_GCCFG_SDEN_Msk                   (0x1UL << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */\n#define USB_OTG_GCCFG_SDEN                       USB_OTG_GCCFG_SDEN_Msk        /*!< Secondary detection (SD) mode enable */\n#define USB_OTG_GCCFG_VBDEN_Pos                  (21U)\n#define USB_OTG_GCCFG_VBDEN_Msk                  (0x1UL << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */\n#define USB_OTG_GCCFG_VBDEN                      USB_OTG_GCCFG_VBDEN_Msk       /*!< Secondary detection (SD) mode enable */\n\n/********************  Bit definition forUSB_OTG_GPWRDN) register  ********************/\n#define USB_OTG_GPWRDN_ADPMEN_Pos                (0U)\n#define USB_OTG_GPWRDN_ADPMEN_Msk                (0x1UL << USB_OTG_GPWRDN_ADPMEN_Pos) /*!< 0x00000001 */\n#define USB_OTG_GPWRDN_ADPMEN                    USB_OTG_GPWRDN_ADPMEN_Msk     /*!< ADP module enable */\n#define USB_OTG_GPWRDN_ADPIF_Pos                 (23U)\n#define USB_OTG_GPWRDN_ADPIF_Msk                 (0x1UL << USB_OTG_GPWRDN_ADPIF_Pos) /*!< 0x00800000 */\n#define USB_OTG_GPWRDN_ADPIF                     USB_OTG_GPWRDN_ADPIF_Msk      /*!< ADP Interrupt flag */\n\n/********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/\n#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)\n#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit  */\n#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)\n#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */\n#define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */\n\n/********************  Bit definition forUSB_OTG_CID register  ********************/\n#define USB_OTG_CID_PRODUCT_ID_Pos               (0U)\n#define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */\n#define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk    /*!< Product ID field */\n\n/********************  Bit definition for USB_OTG_GLPMCFG register  ********************/\n#define USB_OTG_GLPMCFG_LPMEN_Pos                (0U)\n#define USB_OTG_GLPMCFG_LPMEN_Msk                (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */\n#define USB_OTG_GLPMCFG_LPMEN                    USB_OTG_GLPMCFG_LPMEN_Msk     /*!< LPM support enable                                     */\n#define USB_OTG_GLPMCFG_LPMACK_Pos               (1U)\n#define USB_OTG_GLPMCFG_LPMACK_Msk               (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */\n#define USB_OTG_GLPMCFG_LPMACK                   USB_OTG_GLPMCFG_LPMACK_Msk    /*!< LPM Token acknowledge enable                           */\n#define USB_OTG_GLPMCFG_BESL_Pos                 (2U)\n#define USB_OTG_GLPMCFG_BESL_Msk                 (0xFUL << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */\n#define USB_OTG_GLPMCFG_BESL                     USB_OTG_GLPMCFG_BESL_Msk      /*!< BESL value received with last ACKed LPM Token          */\n#define USB_OTG_GLPMCFG_REMWAKE_Pos              (6U)\n#define USB_OTG_GLPMCFG_REMWAKE_Msk              (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */\n#define USB_OTG_GLPMCFG_REMWAKE                  USB_OTG_GLPMCFG_REMWAKE_Msk   /*!< bRemoteWake value received with last ACKed LPM Token   */\n#define USB_OTG_GLPMCFG_L1SSEN_Pos               (7U)\n#define USB_OTG_GLPMCFG_L1SSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */\n#define USB_OTG_GLPMCFG_L1SSEN                   USB_OTG_GLPMCFG_L1SSEN_Msk    /*!< L1 shallow sleep enable                                */\n#define USB_OTG_GLPMCFG_BESLTHRS_Pos             (8U)\n#define USB_OTG_GLPMCFG_BESLTHRS_Msk             (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */\n#define USB_OTG_GLPMCFG_BESLTHRS                 USB_OTG_GLPMCFG_BESLTHRS_Msk  /*!< BESL threshold                                         */\n#define USB_OTG_GLPMCFG_L1DSEN_Pos               (12U)\n#define USB_OTG_GLPMCFG_L1DSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */\n#define USB_OTG_GLPMCFG_L1DSEN                   USB_OTG_GLPMCFG_L1DSEN_Msk    /*!< L1 deep sleep enable                                   */\n#define USB_OTG_GLPMCFG_LPMRSP_Pos               (13U)\n#define USB_OTG_GLPMCFG_LPMRSP_Msk               (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */\n#define USB_OTG_GLPMCFG_LPMRSP                   USB_OTG_GLPMCFG_LPMRSP_Msk    /*!< LPM response                                           */\n#define USB_OTG_GLPMCFG_SLPSTS_Pos               (15U)\n#define USB_OTG_GLPMCFG_SLPSTS_Msk               (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */\n#define USB_OTG_GLPMCFG_SLPSTS                   USB_OTG_GLPMCFG_SLPSTS_Msk    /*!< Port sleep status                                      */\n#define USB_OTG_GLPMCFG_L1RSMOK_Pos              (16U)\n#define USB_OTG_GLPMCFG_L1RSMOK_Msk              (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */\n#define USB_OTG_GLPMCFG_L1RSMOK                  USB_OTG_GLPMCFG_L1RSMOK_Msk   /*!< Sleep State Resume OK                                  */\n#define USB_OTG_GLPMCFG_LPMCHIDX_Pos             (17U)\n#define USB_OTG_GLPMCFG_LPMCHIDX_Msk             (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */\n#define USB_OTG_GLPMCFG_LPMCHIDX                 USB_OTG_GLPMCFG_LPMCHIDX_Msk  /*!< LPM Channel Index                                      */\n#define USB_OTG_GLPMCFG_LPMRCNT_Pos              (21U)\n#define USB_OTG_GLPMCFG_LPMRCNT_Msk              (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */\n#define USB_OTG_GLPMCFG_LPMRCNT                  USB_OTG_GLPMCFG_LPMRCNT_Msk   /*!< LPM retry count                                        */\n#define USB_OTG_GLPMCFG_SNDLPM_Pos               (24U)\n#define USB_OTG_GLPMCFG_SNDLPM_Msk               (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */\n#define USB_OTG_GLPMCFG_SNDLPM                   USB_OTG_GLPMCFG_SNDLPM_Msk    /*!< Send LPM transaction                                   */\n#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos           (25U)\n#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk           (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */\n#define USB_OTG_GLPMCFG_LPMRCNTSTS               USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status                                 */\n#define USB_OTG_GLPMCFG_ENBESL_Pos               (28U)\n#define USB_OTG_GLPMCFG_ENBESL_Msk               (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */\n#define USB_OTG_GLPMCFG_ENBESL                   USB_OTG_GLPMCFG_ENBESL_Msk    /*!< Enable best effort service latency                     */\n\n/********************  Bit definition forUSB_OTG_DIEPEACHMSK1 register  ********************/\n#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           (0U)\n#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask                 */\n#define USB_OTG_DIEPEACHMSK1_EPDM_Pos            (1U)\n#define USB_OTG_DIEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask                  */\n#define USB_OTG_DIEPEACHMSK1_TOM_Pos             (3U)\n#define USB_OTG_DIEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */\n#define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask (nonisochronous endpoints) */\n#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)\n#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */\n#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */\n#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         (5U)\n#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */\n#define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask           */\n#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         (6U)\n#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */\n#define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask                    */\n#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          (8U)\n#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */\n#define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */\n#define USB_OTG_DIEPEACHMSK1_BIM_Pos             (9U)\n#define USB_OTG_DIEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */\n#define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */\n#define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)\n#define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */\n#define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */\n\n/********************  Bit definition forUSB_OTG_HPRT register  ********************/\n#define USB_OTG_HPRT_PCSTS_Pos                   (0U)\n#define USB_OTG_HPRT_PCSTS_Msk                   (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */\n#define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk        /*!< Port connect status        */\n#define USB_OTG_HPRT_PCDET_Pos                   (1U)\n#define USB_OTG_HPRT_PCDET_Msk                   (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */\n#define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk        /*!< Port connect detected      */\n#define USB_OTG_HPRT_PENA_Pos                    (2U)\n#define USB_OTG_HPRT_PENA_Msk                    (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */\n#define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk         /*!< Port enable                */\n#define USB_OTG_HPRT_PENCHNG_Pos                 (3U)\n#define USB_OTG_HPRT_PENCHNG_Msk                 (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */\n#define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk      /*!< Port enable/disable change */\n#define USB_OTG_HPRT_POCA_Pos                    (4U)\n#define USB_OTG_HPRT_POCA_Msk                    (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */\n#define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk         /*!< Port overcurrent active    */\n#define USB_OTG_HPRT_POCCHNG_Pos                 (5U)\n#define USB_OTG_HPRT_POCCHNG_Msk                 (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */\n#define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk      /*!< Port overcurrent change    */\n#define USB_OTG_HPRT_PRES_Pos                    (6U)\n#define USB_OTG_HPRT_PRES_Msk                    (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */\n#define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk         /*!< Port resume   */\n#define USB_OTG_HPRT_PSUSP_Pos                   (7U)\n#define USB_OTG_HPRT_PSUSP_Msk                   (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */\n#define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk        /*!< Port suspend  */\n#define USB_OTG_HPRT_PRST_Pos                    (8U)\n#define USB_OTG_HPRT_PRST_Msk                    (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */\n#define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk         /*!< Port reset    */\n\n#define USB_OTG_HPRT_PLSTS_Pos                   (10U)\n#define USB_OTG_HPRT_PLSTS_Msk                   (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */\n#define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk        /*!< Port line status */\n#define USB_OTG_HPRT_PLSTS_0                     (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */\n#define USB_OTG_HPRT_PLSTS_1                     (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */\n#define USB_OTG_HPRT_PPWR_Pos                    (12U)\n#define USB_OTG_HPRT_PPWR_Msk                    (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */\n#define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk         /*!< Port power */\n\n#define USB_OTG_HPRT_PTCTL_Pos                   (13U)\n#define USB_OTG_HPRT_PTCTL_Msk                   (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */\n#define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk        /*!< Port test control */\n#define USB_OTG_HPRT_PTCTL_0                     (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */\n#define USB_OTG_HPRT_PTCTL_1                     (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */\n#define USB_OTG_HPRT_PTCTL_2                     (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */\n#define USB_OTG_HPRT_PTCTL_3                     (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */\n\n#define USB_OTG_HPRT_PSPD_Pos                    (17U)\n#define USB_OTG_HPRT_PSPD_Msk                    (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */\n#define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk         /*!< Port speed */\n#define USB_OTG_HPRT_PSPD_0                      (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */\n#define USB_OTG_HPRT_PSPD_1                      (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */\n\n/********************  Bit definition forUSB_OTG_DOEPEACHMSK1 register  ********************/\n#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           (0U)\n#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */\n#define USB_OTG_DOEPEACHMSK1_EPDM_Pos            (1U)\n#define USB_OTG_DOEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */\n#define USB_OTG_DOEPEACHMSK1_TOM_Pos             (3U)\n#define USB_OTG_DOEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */\n#define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask */\n#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)\n#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */\n#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */\n#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)\n#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */\n#define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */\n#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         (6U)\n#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */\n#define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */\n#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          (8U)\n#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */\n#define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */\n#define USB_OTG_DOEPEACHMSK1_BIM_Pos             (9U)\n#define USB_OTG_DOEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */\n#define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */\n#define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)\n#define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */\n#define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */\n#define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)\n#define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */\n#define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */\n#define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)\n#define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */\n#define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */\n\n/********************  Bit definition forUSB_OTG_HPTXFSIZ register  ********************/\n#define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)\n#define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address */\n#define USB_OTG_HPTXFSIZ_PTXFD_Pos               (16U)\n#define USB_OTG_HPTXFSIZ_PTXFD_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_HPTXFSIZ_PTXFD                   USB_OTG_HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth */\n\n/********************  Bit definition forUSB_OTG_DIEPCTL register  ********************/\n#define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)\n#define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */\n#define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size */\n#define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)\n#define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */\n#define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk    /*!< USB active endpoint */\n#define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)\n#define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */\n#define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */\n#define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)\n#define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */\n#define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk    /*!< NAK status */\n\n#define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)\n#define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */\n#define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk     /*!< Endpoint type */\n#define USB_OTG_DIEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */\n#define USB_OTG_DIEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */\n#define USB_OTG_DIEPCTL_STALL_Pos                (21U)\n#define USB_OTG_DIEPCTL_STALL_Msk                (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */\n#define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk     /*!< STALL handshake */\n\n#define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)\n#define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */\n#define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number */\n#define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */\n#define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */\n#define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */\n#define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */\n#define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)\n#define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */\n#define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk      /*!< Clear NAK */\n#define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)\n#define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */\n#define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk      /*!< Set NAK */\n#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)\n#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */\n#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */\n#define USB_OTG_DIEPCTL_SODDFRM_Pos              (29U)\n#define USB_OTG_DIEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */\n#define USB_OTG_DIEPCTL_SODDFRM                  USB_OTG_DIEPCTL_SODDFRM_Msk   /*!< Set odd frame */\n#define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)\n#define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */\n#define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk     /*!< Endpoint disable */\n#define USB_OTG_DIEPCTL_EPENA_Pos                (31U)\n#define USB_OTG_DIEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */\n#define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk     /*!< Endpoint enable */\n\n/********************  Bit definition forUSB_OTG_HCCHAR register  ********************/\n#define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)\n#define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */\n#define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */\n\n#define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)\n#define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */\n#define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk      /*!< Endpoint number */\n#define USB_OTG_HCCHAR_EPNUM_0                   (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */\n#define USB_OTG_HCCHAR_EPNUM_1                   (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */\n#define USB_OTG_HCCHAR_EPNUM_2                   (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */\n#define USB_OTG_HCCHAR_EPNUM_3                   (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */\n#define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)\n#define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */\n#define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk      /*!< Endpoint direction */\n#define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)\n#define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */\n#define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk      /*!< Low-speed device */\n\n#define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)\n#define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */\n#define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk      /*!< Endpoint type */\n#define USB_OTG_HCCHAR_EPTYP_0                   (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */\n#define USB_OTG_HCCHAR_EPTYP_1                   (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */\n\n#define USB_OTG_HCCHAR_MC_Pos                    (20U)\n#define USB_OTG_HCCHAR_MC_Msk                    (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */\n#define USB_OTG_HCCHAR_MC                        USB_OTG_HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */\n#define USB_OTG_HCCHAR_MC_0                      (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */\n#define USB_OTG_HCCHAR_MC_1                      (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */\n\n#define USB_OTG_HCCHAR_DAD_Pos                   (22U)\n#define USB_OTG_HCCHAR_DAD_Msk                   (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */\n#define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk        /*!< Device address */\n#define USB_OTG_HCCHAR_DAD_0                     (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */\n#define USB_OTG_HCCHAR_DAD_1                     (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */\n#define USB_OTG_HCCHAR_DAD_2                     (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */\n#define USB_OTG_HCCHAR_DAD_3                     (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */\n#define USB_OTG_HCCHAR_DAD_4                     (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */\n#define USB_OTG_HCCHAR_DAD_5                     (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */\n#define USB_OTG_HCCHAR_DAD_6                     (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */\n#define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)\n#define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */\n#define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk     /*!< Odd frame */\n#define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)\n#define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */\n#define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk      /*!< Channel disable */\n#define USB_OTG_HCCHAR_CHENA_Pos                 (31U)\n#define USB_OTG_HCCHAR_CHENA_Msk                 (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */\n#define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk      /*!< Channel enable */\n\n/********************  Bit definition forUSB_OTG_HCSPLT register  ********************/\n\n#define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)\n#define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */\n#define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk    /*!< Port address */\n#define USB_OTG_HCSPLT_PRTADDR_0                 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */\n#define USB_OTG_HCSPLT_PRTADDR_1                 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */\n#define USB_OTG_HCSPLT_PRTADDR_2                 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */\n#define USB_OTG_HCSPLT_PRTADDR_3                 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */\n#define USB_OTG_HCSPLT_PRTADDR_4                 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */\n#define USB_OTG_HCSPLT_PRTADDR_5                 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */\n#define USB_OTG_HCSPLT_PRTADDR_6                 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */\n\n#define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)\n#define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */\n#define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk    /*!< Hub address */\n#define USB_OTG_HCSPLT_HUBADDR_0                 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */\n#define USB_OTG_HCSPLT_HUBADDR_1                 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */\n#define USB_OTG_HCSPLT_HUBADDR_2                 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */\n#define USB_OTG_HCSPLT_HUBADDR_3                 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */\n#define USB_OTG_HCSPLT_HUBADDR_4                 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */\n#define USB_OTG_HCSPLT_HUBADDR_5                 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */\n#define USB_OTG_HCSPLT_HUBADDR_6                 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */\n\n#define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)\n#define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */\n#define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk    /*!< XACTPOS */\n#define USB_OTG_HCSPLT_XACTPOS_0                 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */\n#define USB_OTG_HCSPLT_XACTPOS_1                 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */\n#define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)\n#define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */\n#define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */\n#define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)\n#define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */\n#define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk    /*!< Split enable */\n\n/********************  Bit definition forUSB_OTG_HCINT register  ********************/\n#define USB_OTG_HCINT_XFRC_Pos                   (0U)\n#define USB_OTG_HCINT_XFRC_Msk                   (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */\n#define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk        /*!< Transfer completed */\n#define USB_OTG_HCINT_CHH_Pos                    (1U)\n#define USB_OTG_HCINT_CHH_Msk                    (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */\n#define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk         /*!< Channel halted */\n#define USB_OTG_HCINT_AHBERR_Pos                 (2U)\n#define USB_OTG_HCINT_AHBERR_Msk                 (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */\n#define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk      /*!< AHB error */\n#define USB_OTG_HCINT_STALL_Pos                  (3U)\n#define USB_OTG_HCINT_STALL_Msk                  (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */\n#define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk       /*!< STALL response received interrupt */\n#define USB_OTG_HCINT_NAK_Pos                    (4U)\n#define USB_OTG_HCINT_NAK_Msk                    (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */\n#define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk         /*!< NAK response received interrupt */\n#define USB_OTG_HCINT_ACK_Pos                    (5U)\n#define USB_OTG_HCINT_ACK_Msk                    (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */\n#define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */\n#define USB_OTG_HCINT_NYET_Pos                   (6U)\n#define USB_OTG_HCINT_NYET_Msk                   (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */\n#define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk        /*!< Response received interrupt */\n#define USB_OTG_HCINT_TXERR_Pos                  (7U)\n#define USB_OTG_HCINT_TXERR_Msk                  (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */\n#define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk       /*!< Transaction error */\n#define USB_OTG_HCINT_BBERR_Pos                  (8U)\n#define USB_OTG_HCINT_BBERR_Msk                  (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */\n#define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk       /*!< Babble error */\n#define USB_OTG_HCINT_FRMOR_Pos                  (9U)\n#define USB_OTG_HCINT_FRMOR_Msk                  (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */\n#define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk       /*!< Frame overrun */\n#define USB_OTG_HCINT_DTERR_Pos                  (10U)\n#define USB_OTG_HCINT_DTERR_Msk                  (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */\n#define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk       /*!< Data toggle error */\n\n/********************  Bit definition forUSB_OTG_DIEPINT register  ********************/\n#define USB_OTG_DIEPINT_XFRC_Pos                 (0U)\n#define USB_OTG_DIEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */\n#define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */\n#define USB_OTG_DIEPINT_EPDISD_Pos               (1U)\n#define USB_OTG_DIEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */\n#define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */\n#define USB_OTG_DIEPINT_AHBERR_Pos               (2U)\n#define USB_OTG_DIEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */\n#define USB_OTG_DIEPINT_AHBERR                   USB_OTG_DIEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an IN transaction */\n#define USB_OTG_DIEPINT_TOC_Pos                  (3U)\n#define USB_OTG_DIEPINT_TOC_Msk                  (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */\n#define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk       /*!< Timeout condition */\n#define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)\n#define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */\n#define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */\n#define USB_OTG_DIEPINT_INEPNM_Pos               (5U)\n#define USB_OTG_DIEPINT_INEPNM_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */\n#define USB_OTG_DIEPINT_INEPNM                   USB_OTG_DIEPINT_INEPNM_Msk   /*!< IN token received with EP mismatch */\n#define USB_OTG_DIEPINT_INEPNE_Pos               (6U)\n#define USB_OTG_DIEPINT_INEPNE_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */\n#define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */\n#define USB_OTG_DIEPINT_TXFE_Pos                 (7U)\n#define USB_OTG_DIEPINT_TXFE_Msk                 (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */\n#define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */\n#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)\n#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */\n#define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */\n#define USB_OTG_DIEPINT_BNA_Pos                  (9U)\n#define USB_OTG_DIEPINT_BNA_Msk                  (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */\n#define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */\n#define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)\n#define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */\n#define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */\n#define USB_OTG_DIEPINT_BERR_Pos                 (12U)\n#define USB_OTG_DIEPINT_BERR_Msk                 (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */\n#define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk      /*!< Babble error interrupt */\n#define USB_OTG_DIEPINT_NAK_Pos                  (13U)\n#define USB_OTG_DIEPINT_NAK_Msk                  (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */\n#define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk       /*!< NAK interrupt */\n\n/********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/\n#define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)\n#define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */\n#define USB_OTG_HCINTMSK_CHHM_Pos                (1U)\n#define USB_OTG_HCINTMSK_CHHM_Msk                (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */\n#define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk     /*!< Channel halted mask */\n#define USB_OTG_HCINTMSK_AHBERR_Pos              (2U)\n#define USB_OTG_HCINTMSK_AHBERR_Msk              (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */\n#define USB_OTG_HCINTMSK_AHBERR                  USB_OTG_HCINTMSK_AHBERR_Msk   /*!< AHB error */\n#define USB_OTG_HCINTMSK_STALLM_Pos              (3U)\n#define USB_OTG_HCINTMSK_STALLM_Msk              (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */\n#define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */\n#define USB_OTG_HCINTMSK_NAKM_Pos                (4U)\n#define USB_OTG_HCINTMSK_NAKM_Msk                (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */\n#define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */\n#define USB_OTG_HCINTMSK_ACKM_Pos                (5U)\n#define USB_OTG_HCINTMSK_ACKM_Msk                (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */\n#define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */\n#define USB_OTG_HCINTMSK_NYET_Pos                (6U)\n#define USB_OTG_HCINTMSK_NYET_Msk                (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */\n#define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk     /*!< response received interrupt mask */\n#define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)\n#define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */\n#define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */\n#define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)\n#define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */\n#define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk   /*!< Babble error mask */\n#define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)\n#define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */\n#define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */\n#define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)\n#define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */\n#define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */\n\n/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/\n\n#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)\n#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\n#define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */\n#define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)\n#define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\n#define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */\n#define USB_OTG_DIEPTSIZ_MULCNT_Pos              (29U)\n#define USB_OTG_DIEPTSIZ_MULCNT_Msk              (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */\n#define USB_OTG_DIEPTSIZ_MULCNT                  USB_OTG_DIEPTSIZ_MULCNT_Msk   /*!< Packet count */\n/********************  Bit definition forUSB_OTG_HCTSIZ register  ********************/\n#define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)\n#define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\n#define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */\n#define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)\n#define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\n#define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk     /*!< Packet count */\n#define USB_OTG_HCTSIZ_DOPING_Pos                (31U)\n#define USB_OTG_HCTSIZ_DOPING_Msk                (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */\n#define USB_OTG_HCTSIZ_DOPING                    USB_OTG_HCTSIZ_DOPING_Msk     /*!< Do PING */\n#define USB_OTG_HCTSIZ_DPID_Pos                  (29U)\n#define USB_OTG_HCTSIZ_DPID_Msk                  (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */\n#define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk       /*!< Data PID */\n#define USB_OTG_HCTSIZ_DPID_0                    (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */\n#define USB_OTG_HCTSIZ_DPID_1                    (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */\n\n/********************  Bit definition forUSB_OTG_DIEPDMA register  ********************/\n#define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)\n#define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */\n#define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk   /*!< DMA address */\n\n/********************  Bit definition forUSB_OTG_HCDMA register  ********************/\n#define USB_OTG_HCDMA_DMAADDR_Pos                (0U)\n#define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */\n#define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk     /*!< DMA address */\n\n/********************  Bit definition forUSB_OTG_DTXFSTS register  ********************/\n#define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)\n#define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */\n\n/********************  Bit definition forUSB_OTG_DIEPTXF register  ********************/\n#define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)\n#define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */\n#define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)\n#define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */\n\n/********************  Bit definition forUSB_OTG_DOEPCTL register  ********************/\n\n#define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)\n#define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */\n#define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */\n#define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)\n#define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */\n#define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */\n#define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)\n#define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */\n#define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk    /*!< NAK status */\n#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)\n#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */\n#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */\n#define USB_OTG_DOEPCTL_SODDFRM_Pos              (29U)\n#define USB_OTG_DOEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */\n#define USB_OTG_DOEPCTL_SODDFRM                  USB_OTG_DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */\n#define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)\n#define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */\n#define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk     /*!< Endpoint type */\n#define USB_OTG_DOEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */\n#define USB_OTG_DOEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */\n#define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)\n#define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */\n#define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk      /*!< Snoop mode */\n#define USB_OTG_DOEPCTL_STALL_Pos                (21U)\n#define USB_OTG_DOEPCTL_STALL_Msk                (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */\n#define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk     /*!< STALL handshake */\n#define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)\n#define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */\n#define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk      /*!< Clear NAK */\n#define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)\n#define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */\n#define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk      /*!< Set NAK */\n#define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)\n#define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */\n#define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */\n#define USB_OTG_DOEPCTL_EPENA_Pos                (31U)\n#define USB_OTG_DOEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */\n#define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk     /*!< Endpoint enable */\n\n/********************  Bit definition forUSB_OTG_DOEPINT register  ********************/\n#define USB_OTG_DOEPINT_XFRC_Pos                 (0U)\n#define USB_OTG_DOEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */\n#define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */\n#define USB_OTG_DOEPINT_EPDISD_Pos               (1U)\n#define USB_OTG_DOEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */\n#define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */\n#define USB_OTG_DOEPINT_AHBERR_Pos               (2U)\n#define USB_OTG_DOEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */\n#define USB_OTG_DOEPINT_AHBERR                   USB_OTG_DOEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an OUT transaction */\n#define USB_OTG_DOEPINT_STUP_Pos                 (3U)\n#define USB_OTG_DOEPINT_STUP_Msk                 (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */\n#define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk      /*!< SETUP phase done */\n#define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)\n#define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */\n#define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */\n#define USB_OTG_DOEPINT_OTEPSPR_Pos              (5U)\n#define USB_OTG_DOEPINT_OTEPSPR_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */\n#define USB_OTG_DOEPINT_OTEPSPR                  USB_OTG_DOEPINT_OTEPSPR_Msk   /*!< OUT Status Phase Received interrupt */\n#define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)\n#define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */\n#define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */\n#define USB_OTG_DOEPINT_OUTPKTERR_Pos            (8U)\n#define USB_OTG_DOEPINT_OUTPKTERR_Msk            (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */\n#define USB_OTG_DOEPINT_OUTPKTERR                USB_OTG_DOEPINT_OUTPKTERR_Msk   /*!< OUT packet error */\n#define USB_OTG_DOEPINT_BERR_Pos                 (12U)\n#define USB_OTG_DOEPINT_BERR_Msk                 (0x1UL << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */\n#define USB_OTG_DOEPINT_BERR                      USB_OTG_DOEPINT_BERR_Msk   /*!< Babble error interrupt */\n#define USB_OTG_DOEPINT_NAK_Pos                  (13U)\n#define USB_OTG_DOEPINT_NAK_Msk                  (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */\n#define USB_OTG_DOEPINT_NAK                      USB_OTG_DOEPINT_NAK_Msk   /*!< NAK Packet is transmitted by the device */\n#define USB_OTG_DOEPINT_NYET_Pos                 (14U)\n#define USB_OTG_DOEPINT_NYET_Msk                 (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */\n#define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk      /*!< NYET interrupt */\n#define USB_OTG_DOEPINT_STPKTRX_Pos              (15U)\n#define USB_OTG_DOEPINT_STPKTRX_Msk              (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */\n#define USB_OTG_DOEPINT_STPKTRX                  USB_OTG_DOEPINT_STPKTRX_Msk   /*!< Setup Packet Received */\n\n/********************  Bit definition forUSB_OTG_DOEPTSIZ register  ********************/\n\n#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)\n#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\n#define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */\n#define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)\n#define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\n#define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */\n\n#define USB_OTG_DOEPTSIZ_STUPCNT_Pos             (29U)\n#define USB_OTG_DOEPTSIZ_STUPCNT_Msk             (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */\n#define USB_OTG_DOEPTSIZ_STUPCNT                 USB_OTG_DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */\n#define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */\n#define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */\n\n/********************  Bit definition for PCGCCTL register  ********************/\n#define USB_OTG_PCGCCTL_STOPCLK_Pos              (0U)\n#define USB_OTG_PCGCCTL_STOPCLK_Msk              (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */\n#define USB_OTG_PCGCCTL_STOPCLK                  USB_OTG_PCGCCTL_STOPCLK_Msk   /*!< SETUP packet count */\n#define USB_OTG_PCGCCTL_GATECLK_Pos              (1U)\n#define USB_OTG_PCGCCTL_GATECLK_Msk              (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */\n#define USB_OTG_PCGCCTL_GATECLK                  USB_OTG_PCGCCTL_GATECLK_Msk   /*!<Bit 0 */\n#define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)\n#define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */\n#define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup Exported_macros\n  * @{\n  */\n\n/******************************* ADC Instances ********************************/\n#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \\\n                                       ((INSTANCE) == ADC2) || \\\n                                       ((INSTANCE) == ADC3))\n\n#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)\n\n#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON) ||\\\n                                          ((INSTANCE) == ADC3_COMMON))\n\n/******************************** COMP Instances ******************************/\n#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \\\n                                       ((INSTANCE) == COMP2))\n\n#define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)\n/******************** COMP Instances with window mode capability **************/\n#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)\n\n\n/******************************* CRC Instances ********************************/\n#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)\n\n/******************************* DAC Instances ********************************/\n#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)\n/******************************* DCMI Instances *******************************/\n#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)\n\n/******************************* DELAYBLOCK Instances *******************************/\n#define IS_DLYB_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == DLYB_SDMMC1) || \\\n                                         ((INSTANCE) == DLYB_SDMMC2) || \\\n                                         ((INSTANCE) == DLYB_QUADSPI))\n/****************************** DFSDM Instances *******************************/\n#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \\\n                                               ((INSTANCE) == DFSDM1_Filter1) || \\\n                                               ((INSTANCE) == DFSDM1_Filter2) || \\\n                                               ((INSTANCE) == DFSDM1_Filter3))\n\n#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \\\n                                                 ((INSTANCE) == DFSDM1_Channel1) || \\\n                                                 ((INSTANCE) == DFSDM1_Channel2) || \\\n                                                 ((INSTANCE) == DFSDM1_Channel3) || \\\n                                                 ((INSTANCE) == DFSDM1_Channel4) || \\\n                                                 ((INSTANCE) == DFSDM1_Channel5) || \\\n                                                 ((INSTANCE) == DFSDM1_Channel6) || \\\n                                                 ((INSTANCE) == DFSDM1_Channel7))\n/****************************** RAMECC Instances ******************************/\n#define IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMECC1_Monitor1)   || \\\n                                                  ((INSTANCE) == RAMECC1_Monitor2)   || \\\n                                                  ((INSTANCE) == RAMECC1_Monitor3)   || \\\n                                                  ((INSTANCE) == RAMECC1_Monitor4)   || \\\n                                                  ((INSTANCE) == RAMECC1_Monitor5)   || \\\n                                                  ((INSTANCE) == RAMECC2_Monitor1)   || \\\n                                                  ((INSTANCE) == RAMECC2_Monitor2)   || \\\n                                                  ((INSTANCE) == RAMECC2_Monitor3)   || \\\n                                                  ((INSTANCE) == RAMECC2_Monitor4)   || \\\n                                                  ((INSTANCE) == RAMECC2_Monitor5)   || \\\n                                                  ((INSTANCE) == RAMECC3_Monitor1)   || \\\n                                                  ((INSTANCE) == RAMECC3_Monitor2))\n\n/******************************** DMA Instances *******************************/\n#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0)   || \\\n                                       ((INSTANCE) == DMA1_Stream1)   || \\\n                                       ((INSTANCE) == DMA1_Stream2)   || \\\n                                       ((INSTANCE) == DMA1_Stream3)   || \\\n                                       ((INSTANCE) == DMA1_Stream4)   || \\\n                                       ((INSTANCE) == DMA1_Stream5)   || \\\n                                       ((INSTANCE) == DMA1_Stream6)   || \\\n                                       ((INSTANCE) == DMA1_Stream7)   || \\\n                                       ((INSTANCE) == DMA2_Stream0)   || \\\n                                       ((INSTANCE) == DMA2_Stream1)   || \\\n                                       ((INSTANCE) == DMA2_Stream2)   || \\\n                                       ((INSTANCE) == DMA2_Stream3)   || \\\n                                       ((INSTANCE) == DMA2_Stream4)   || \\\n                                       ((INSTANCE) == DMA2_Stream5)   || \\\n                                       ((INSTANCE) == DMA2_Stream6)   || \\\n                                       ((INSTANCE) == DMA2_Stream7)   || \\\n                                       ((INSTANCE) == BDMA_Channel0) || \\\n                                       ((INSTANCE) == BDMA_Channel1) || \\\n                                       ((INSTANCE) == BDMA_Channel2) || \\\n                                       ((INSTANCE) == BDMA_Channel3) || \\\n                                       ((INSTANCE) == BDMA_Channel4) || \\\n                                       ((INSTANCE) == BDMA_Channel5) || \\\n                                       ((INSTANCE) == BDMA_Channel6) || \\\n                                       ((INSTANCE) == BDMA_Channel7))\n\n/****************************** BDMA CHANNEL Instances ***************************/\n#define IS_BDMA_CHANNEL_INSTANCE(INSTANCE) (((INSTANCE) == BDMA_Channel0) || \\\n                                            ((INSTANCE) == BDMA_Channel1) || \\\n                                            ((INSTANCE) == BDMA_Channel2) || \\\n                                            ((INSTANCE) == BDMA_Channel3) || \\\n                                            ((INSTANCE) == BDMA_Channel4) || \\\n                                            ((INSTANCE) == BDMA_Channel5) || \\\n                                            ((INSTANCE) == BDMA_Channel6) || \\\n                                            ((INSTANCE) == BDMA_Channel7))\n\n/****************************** DMA DMAMUX ALL Instances ***************************/\n#define IS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == DMA1_Stream0)    || \\\n                                               ((INSTANCE) == DMA1_Stream1)    || \\\n                                               ((INSTANCE) == DMA1_Stream2)    || \\\n                                               ((INSTANCE) == DMA1_Stream3)    || \\\n                                               ((INSTANCE) == DMA1_Stream4)    || \\\n                                               ((INSTANCE) == DMA1_Stream5)    || \\\n                                               ((INSTANCE) == DMA1_Stream6)    || \\\n                                               ((INSTANCE) == DMA1_Stream7)    || \\\n                                               ((INSTANCE) == DMA2_Stream0)    || \\\n                                               ((INSTANCE) == DMA2_Stream1)    || \\\n                                               ((INSTANCE) == DMA2_Stream2)    || \\\n                                               ((INSTANCE) == DMA2_Stream3)    || \\\n                                               ((INSTANCE) == DMA2_Stream4)    || \\\n                                               ((INSTANCE) == DMA2_Stream5)    || \\\n                                               ((INSTANCE) == DMA2_Stream6)    || \\\n                                               ((INSTANCE) == DMA2_Stream7)    || \\\n                                               ((INSTANCE) == BDMA_Channel0)   || \\\n                                               ((INSTANCE) == BDMA_Channel1)   || \\\n                                               ((INSTANCE) == BDMA_Channel2)   || \\\n                                               ((INSTANCE) == BDMA_Channel3)   || \\\n                                               ((INSTANCE) == BDMA_Channel4)   || \\\n                                               ((INSTANCE) == BDMA_Channel5)   || \\\n                                               ((INSTANCE) == BDMA_Channel6)   || \\\n                                               ((INSTANCE) == BDMA_Channel7))\n\n/****************************** BDMA DMAMUX Instances ***************************/\n#define IS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE)  (((INSTANCE) == BDMA_Channel0) || \\\n                                                    ((INSTANCE) == BDMA_Channel1) || \\\n                                                    ((INSTANCE) == BDMA_Channel2) || \\\n                                                    ((INSTANCE) == BDMA_Channel3) || \\\n                                                    ((INSTANCE) == BDMA_Channel4) || \\\n                                                    ((INSTANCE) == BDMA_Channel5) || \\\n                                                    ((INSTANCE) == BDMA_Channel6) || \\\n                                                    ((INSTANCE) == BDMA_Channel7))\n\n/****************************** DMA STREAM Instances ***************************/\n#define IS_DMA_STREAM_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0)   || \\\n                                          ((INSTANCE) == DMA1_Stream1)   || \\\n                                          ((INSTANCE) == DMA1_Stream2)   || \\\n                                          ((INSTANCE) == DMA1_Stream3)   || \\\n                                          ((INSTANCE) == DMA1_Stream4)   || \\\n                                          ((INSTANCE) == DMA1_Stream5)   || \\\n                                          ((INSTANCE) == DMA1_Stream6)   || \\\n                                          ((INSTANCE) == DMA1_Stream7)   || \\\n                                          ((INSTANCE) == DMA2_Stream0)   || \\\n                                          ((INSTANCE) == DMA2_Stream1)   || \\\n                                          ((INSTANCE) == DMA2_Stream2)   || \\\n                                          ((INSTANCE) == DMA2_Stream3)   || \\\n                                          ((INSTANCE) == DMA2_Stream4)   || \\\n                                          ((INSTANCE) == DMA2_Stream5)   || \\\n                                          ((INSTANCE) == DMA2_Stream6)   || \\\n                                          ((INSTANCE) == DMA2_Stream7))\n\n/****************************** DMA DMAMUX Instances ***************************/\n#define IS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE)  (((INSTANCE) == DMA1_Stream0)   || \\\n                                                  ((INSTANCE) == DMA1_Stream1)   || \\\n                                                  ((INSTANCE) == DMA1_Stream2)   || \\\n                                                  ((INSTANCE) == DMA1_Stream3)   || \\\n                                                  ((INSTANCE) == DMA1_Stream4)   || \\\n                                                  ((INSTANCE) == DMA1_Stream5)   || \\\n                                                  ((INSTANCE) == DMA1_Stream6)   || \\\n                                                  ((INSTANCE) == DMA1_Stream7)   || \\\n                                                  ((INSTANCE) == DMA2_Stream0)   || \\\n                                                  ((INSTANCE) == DMA2_Stream1)   || \\\n                                                  ((INSTANCE) == DMA2_Stream2)   || \\\n                                                  ((INSTANCE) == DMA2_Stream3)   || \\\n                                                  ((INSTANCE) == DMA2_Stream4)   || \\\n                                                  ((INSTANCE) == DMA2_Stream5)   || \\\n                                                  ((INSTANCE) == DMA2_Stream6)   || \\\n                                                  ((INSTANCE) == DMA2_Stream7))\n\n/******************************** DMA Request Generator Instances **************/\n#define IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \\\n                                                   ((INSTANCE) == DMAMUX1_RequestGenerator1) || \\\n                                                   ((INSTANCE) == DMAMUX1_RequestGenerator2) || \\\n                                                   ((INSTANCE) == DMAMUX1_RequestGenerator3) || \\\n                                                   ((INSTANCE) == DMAMUX1_RequestGenerator4) || \\\n                                                   ((INSTANCE) == DMAMUX1_RequestGenerator5) || \\\n                                                   ((INSTANCE) == DMAMUX1_RequestGenerator6) || \\\n                                                   ((INSTANCE) == DMAMUX1_RequestGenerator7) || \\\n                                                   ((INSTANCE) == DMAMUX2_RequestGenerator0) || \\\n                                                   ((INSTANCE) == DMAMUX2_RequestGenerator1) || \\\n                                                   ((INSTANCE) == DMAMUX2_RequestGenerator2) || \\\n                                                   ((INSTANCE) == DMAMUX2_RequestGenerator3) || \\\n                                                   ((INSTANCE) == DMAMUX2_RequestGenerator4) || \\\n                                                   ((INSTANCE) == DMAMUX2_RequestGenerator5) || \\\n                                                   ((INSTANCE) == DMAMUX2_RequestGenerator6) || \\\n                                                   ((INSTANCE) == DMAMUX2_RequestGenerator7))\n\n/******************************* DMA2D Instances *******************************/\n#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)\n\n/******************************** MDMA Request Generator Instances **************/\n#define IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDMA_Channel0)  || \\\n                                               ((INSTANCE) == MDMA_Channel1)  || \\\n                                               ((INSTANCE) == MDMA_Channel2)  || \\\n                                               ((INSTANCE) == MDMA_Channel3)  || \\\n                                               ((INSTANCE) == MDMA_Channel4)  || \\\n                                               ((INSTANCE) == MDMA_Channel5)  || \\\n                                               ((INSTANCE) == MDMA_Channel6)  || \\\n                                               ((INSTANCE) == MDMA_Channel7)  || \\\n                                               ((INSTANCE) == MDMA_Channel8)  || \\\n                                               ((INSTANCE) == MDMA_Channel9)  || \\\n                                               ((INSTANCE) == MDMA_Channel10) || \\\n                                               ((INSTANCE) == MDMA_Channel11) || \\\n                                               ((INSTANCE) == MDMA_Channel12) || \\\n                                               ((INSTANCE) == MDMA_Channel13) || \\\n                                               ((INSTANCE) == MDMA_Channel14) || \\\n                                               ((INSTANCE) == MDMA_Channel15))\n\n/******************************* QUADSPI Instances *******************************/\n#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)\n\n/******************************* FDCAN Instances ******************************/\n#define IS_FDCAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == FDCAN1) || \\\n                                             ((__INSTANCE__) == FDCAN2))\n\n#define IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1)\n\n/******************************* GPIO Instances *******************************/\n#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \\\n                                        ((INSTANCE) == GPIOB) || \\\n                                        ((INSTANCE) == GPIOC) || \\\n                                        ((INSTANCE) == GPIOD) || \\\n                                        ((INSTANCE) == GPIOE) || \\\n                                        ((INSTANCE) == GPIOF) || \\\n                                        ((INSTANCE) == GPIOG) || \\\n                                        ((INSTANCE) == GPIOH) || \\\n                                        ((INSTANCE) == GPIOI) || \\\n                                        ((INSTANCE) == GPIOJ) || \\\n                                        ((INSTANCE) == GPIOK))\n\n/******************************* GPIO AF Instances ****************************/\n#define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)\n\n/**************************** GPIO Lock Instances *****************************/\n/* On H7, all GPIO Bank support the Lock mechanism */\n#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)\n\n/******************************** HSEM Instances *******************************/\n#define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM)\n#define HSEM_CPU1_COREID         (0x00000003U) /* Semaphore Core CM7 ID */\n#define HSEM_CR_COREID_CPU1      (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)\n#define HSEM_CR_COREID_CURRENT   (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)\n\n#define HSEM_SEMID_MIN     (0U)       /* HSEM ID Min*/\n#define HSEM_SEMID_MAX     (31U)      /* HSEM ID Max */\n\n#define HSEM_PROCESSID_MIN (0U)       /* HSEM Process ID Min */\n#define HSEM_PROCESSID_MAX (255U)     /* HSEM Process ID Max */\n\n#define HSEM_CLEAR_KEY_MIN (0U)       /* HSEM clear Key Min value */\n#define HSEM_CLEAR_KEY_MAX (0xFFFFU)  /* HSEM clear Key Max value */\n\n/******************************** I2C Instances *******************************/\n#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \\\n                                       ((INSTANCE) == I2C2) || \\\n                                       ((INSTANCE) == I2C3) || \\\n                                       ((INSTANCE) == I2C4))\n\n/****************************** SMBUS Instances *******************************/\n#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \\\n                                         ((INSTANCE) == I2C2) || \\\n                                         ((INSTANCE) == I2C3) || \\\n                                         ((INSTANCE) == I2C4))\n\n/************** I2C Instances : wakeup capability from stop modes *************/\n#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)\n\n/******************************** I2S Instances *******************************/\n#define IS_I2S_ALL_INSTANCE(INSTANCE)   (((INSTANCE) == SPI1) || \\\n                                         ((INSTANCE) == SPI2) || \\\n                                         ((INSTANCE) == SPI3))\n\n/****************************** LTDC Instances ********************************/\n#define IS_LTDC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == LTDC)\n\n/******************************* RNG Instances ********************************/\n#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)\n\n/****************************** RTC Instances *********************************/\n#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)\n\n/****************************** SDMMC Instances *********************************/\n#define IS_SDMMC_ALL_INSTANCE(_INSTANCE_) (((_INSTANCE_) == SDMMC1) || \\\n                                           ((_INSTANCE_) == SDMMC2))\n\n/******************************** SPI Instances *******************************/\n#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \\\n                                       ((INSTANCE) == SPI2) || \\\n                                       ((INSTANCE) == SPI3) || \\\n                                       ((INSTANCE) == SPI4) || \\\n                                       ((INSTANCE) == SPI5) || \\\n                                       ((INSTANCE) == SPI6))\n\n#define IS_SPI_HIGHEND_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \\\n                                           ((INSTANCE) == SPI2) || \\\n                                           ((INSTANCE) == SPI3))\n\n/******************************** SWPMI Instances *****************************/\n#define IS_SWPMI_INSTANCE(INSTANCE)  ((INSTANCE) == SWPMI1)\n\n/****************** LPTIM Instances : All supported instances *****************/\n#define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \\\n                                         ((INSTANCE) == LPTIM2) || \\\n                                         ((INSTANCE) == LPTIM3) || \\\n                                         ((INSTANCE) == LPTIM4) || \\\n                                         ((INSTANCE) == LPTIM5))\n\n/****************** LPTIM Instances : supporting encoder interface **************/\n#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \\\n                                                           ((INSTANCE) == LPTIM2))\n\n/****************** TIM Instances : All supported instances *******************/\n#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \\\n                                         ((INSTANCE) == TIM2)   || \\\n                                         ((INSTANCE) == TIM3)   || \\\n                                         ((INSTANCE) == TIM4)   || \\\n                                         ((INSTANCE) == TIM5)   || \\\n                                         ((INSTANCE) == TIM6)   || \\\n                                         ((INSTANCE) == TIM7)   || \\\n                                         ((INSTANCE) == TIM8)   || \\\n                                         ((INSTANCE) == TIM12)  || \\\n                                         ((INSTANCE) == TIM13)  || \\\n                                         ((INSTANCE) == TIM14)  || \\\n                                         ((INSTANCE) == TIM15)  || \\\n                                         ((INSTANCE) == TIM16)  || \\\n                                         ((INSTANCE) == TIM17))\n\n/************* TIM Instances : at least 1 capture/compare channel *************/\n#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \\\n                                         ((INSTANCE) == TIM2)   || \\\n                                         ((INSTANCE) == TIM3)   || \\\n                                         ((INSTANCE) == TIM4)   || \\\n                                         ((INSTANCE) == TIM5)   || \\\n                                         ((INSTANCE) == TIM8)   || \\\n                                         ((INSTANCE) == TIM12)  || \\\n                                         ((INSTANCE) == TIM13)  || \\\n                                         ((INSTANCE) == TIM14)  || \\\n                                         ((INSTANCE) == TIM15)  || \\\n                                         ((INSTANCE) == TIM16)  || \\\n                                         ((INSTANCE) == TIM17))\n\n/************ TIM Instances : at least 2 capture/compare channels *************/\n#define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \\\n                                         ((INSTANCE) == TIM2)   || \\\n                                         ((INSTANCE) == TIM3)   || \\\n                                         ((INSTANCE) == TIM4)   || \\\n                                         ((INSTANCE) == TIM5)   || \\\n                                         ((INSTANCE) == TIM8)   || \\\n                                         ((INSTANCE) == TIM12)  || \\\n                                         ((INSTANCE) == TIM15))\n\n/************ TIM Instances : at least 3 capture/compare channels *************/\n#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \\\n                                         ((INSTANCE) == TIM2)   || \\\n                                         ((INSTANCE) == TIM3)   || \\\n                                         ((INSTANCE) == TIM4)   || \\\n                                         ((INSTANCE) == TIM5)   || \\\n                                         ((INSTANCE) == TIM8))\n\n/************ TIM Instances : at least 4 capture/compare channels *************/\n#define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \\\n                                         ((INSTANCE) == TIM2)   || \\\n                                         ((INSTANCE) == TIM3)   || \\\n                                         ((INSTANCE) == TIM4)   || \\\n                                         ((INSTANCE) == TIM5)   || \\\n                                         ((INSTANCE) == TIM8))\n\n/************ TIM Instances : at least 5 capture/compare channels *************/\n#define IS_TIM_CC5_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \\\n                                         ((INSTANCE) == TIM8))\n/************ TIM Instances : at least 6 capture/compare channels *************/\n#define IS_TIM_CC6_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \\\n                                         ((INSTANCE) == TIM8))\n\n/******************** TIM Instances : Advanced-control timers *****************/\n#define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\\n                                                ((__INSTANCE__) == TIM8))\n\n/******************** TIM Instances : Advanced-control timers *****************/\n\n/******************* TIM Instances : Timer input XOR function *****************/\n#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \\\n                                         ((INSTANCE) == TIM2)   || \\\n                                         ((INSTANCE) == TIM3)   || \\\n                                         ((INSTANCE) == TIM4)   || \\\n                                         ((INSTANCE) == TIM5)   || \\\n                                         ((INSTANCE) == TIM8)   || \\\n                                         ((INSTANCE) == TIM15))\n\n/****************** TIM Instances : DMA requests generation (UDE) *************/\n#define IS_TIM_DMA_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \\\n                                           ((INSTANCE) == TIM2)   || \\\n                                           ((INSTANCE) == TIM3)   || \\\n                                           ((INSTANCE) == TIM4)   || \\\n                                           ((INSTANCE) == TIM5)   || \\\n                                           ((INSTANCE) == TIM6)   || \\\n                                           ((INSTANCE) == TIM7)   || \\\n                                           ((INSTANCE) == TIM8)   || \\\n                                           ((INSTANCE) == TIM15)  || \\\n                                           ((INSTANCE) == TIM16)  || \\\n                                           ((INSTANCE) == TIM17))\n\n/************ TIM Instances : DMA requests generation (CCxDE) *****************/\n#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \\\n                                            ((INSTANCE) == TIM2)   || \\\n                                            ((INSTANCE) == TIM3)   || \\\n                                            ((INSTANCE) == TIM4)   || \\\n                                            ((INSTANCE) == TIM5)   || \\\n                                            ((INSTANCE) == TIM8)   || \\\n                                            ((INSTANCE) == TIM15)  || \\\n                                            ((INSTANCE) == TIM16)  || \\\n                                            ((INSTANCE) == TIM17))\n\n/************ TIM Instances : DMA requests generation (COMDE) *****************/\n#define IS_TIM_CCDMA_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)   || \\\n                                            ((INSTANCE) == TIM2)   || \\\n                                            ((INSTANCE) == TIM3)   || \\\n                                            ((INSTANCE) == TIM4)   || \\\n                                            ((INSTANCE) == TIM5)   || \\\n                                            ((INSTANCE) == TIM8)   || \\\n                                            ((INSTANCE) == TIM15))\n\n/******************** TIM Instances : DMA burst feature ***********************/\n#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \\\n                                            ((INSTANCE) == TIM2)   || \\\n                                            ((INSTANCE) == TIM3)   || \\\n                                            ((INSTANCE) == TIM4)   || \\\n                                            ((INSTANCE) == TIM5)   || \\\n                                            ((INSTANCE) == TIM8))\n\n/*************** TIM Instances : external trigger reamp input available *******/\n#define IS_TIM_ETR_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \\\n                                           ((INSTANCE) == TIM2)   || \\\n                                           ((INSTANCE) == TIM3)   || \\\n                                           ((INSTANCE) == TIM4)   || \\\n                                           ((INSTANCE) == TIM5)   || \\\n                                           ((INSTANCE) == TIM8))\n\n/****************** TIM Instances : remapping capability **********************/\n#define IS_TIM_REMAP_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \\\n                                          ((INSTANCE) == TIM2)  || \\\n                                          ((INSTANCE) == TIM3)  || \\\n                                          ((INSTANCE) == TIM5)  || \\\n                                          ((INSTANCE) == TIM8)  || \\\n                                          ((INSTANCE) == TIM16) || \\\n                                          ((INSTANCE) == TIM17))\n\n/*************** TIM Instances : external trigger reamp input available *******/\n#define IS_TIM_ETRSEL_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \\\n                                              ((INSTANCE) == TIM2)   || \\\n                                              ((INSTANCE) == TIM3)   || \\\n                                              ((INSTANCE) == TIM5)   || \\\n                                              ((INSTANCE) == TIM8))\n\n/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/\n#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \\\n                                            ((INSTANCE) == TIM2)   || \\\n                                            ((INSTANCE) == TIM3)   || \\\n                                            ((INSTANCE) == TIM4)   || \\\n                                            ((INSTANCE) == TIM5)   || \\\n                                            ((INSTANCE) == TIM6)   || \\\n                                            ((INSTANCE) == TIM7)   || \\\n                                            ((INSTANCE) == TIM8)   || \\\n                                            ((INSTANCE) == TIM12)  || \\\n                                            ((INSTANCE) == TIM15))\n\n/****** TIM Instances : Salve mode available (TIMx_SMCR.TS available )*********/\n#define IS_TIM_SLAVE_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \\\n                                           ((INSTANCE) == TIM2)   || \\\n                                           ((INSTANCE) == TIM3)   || \\\n                                           ((INSTANCE) == TIM4)   || \\\n                                           ((INSTANCE) == TIM5)   || \\\n                                           ((INSTANCE) == TIM8)   || \\\n                                           ((INSTANCE) == TIM12)  || \\\n                                           ((INSTANCE) == TIM15))\n\n/****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/\n#define IS_TIM_TRGO2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \\\n                                           ((INSTANCE) == TIM8))\n\n/****** TIM Instances : TISEL available (TIMx_TISEL available )*********/\n#define IS_TIM_TISEL_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)   || \\\n                                          ((INSTANCE) == TIM2)   || \\\n                                          ((INSTANCE) == TIM3)   || \\\n                                          ((INSTANCE) == TIM4)   || \\\n                                          ((INSTANCE) == TIM5)   || \\\n                                          ((INSTANCE) == TIM8)   || \\\n                                          ((INSTANCE) == TIM15)  || \\\n                                          ((INSTANCE) == TIM16)  || \\\n                                          ((INSTANCE) == TIM17))\n\n/****************** TIM Instances : supporting commutation event *************/\n#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)    || \\\n                                                     ((INSTANCE) == TIM8)    || \\\n                                                     ((INSTANCE) == TIM15)   || \\\n                                                     ((INSTANCE) == TIM16)   || \\\n                                                     ((INSTANCE) == TIM17))\n\n/****************** TIM Instances : supporting encoder interface **************/\n#define IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1)  || \\\n                                                      ((__INSTANCE__) == TIM2)      || \\\n                                                      ((__INSTANCE__) == TIM3)      || \\\n                                                      ((__INSTANCE__) == TIM4)      || \\\n                                                      ((__INSTANCE__) == TIM5)      || \\\n                                                      ((__INSTANCE__) == TIM8))\n\n/****** TIM Instances : TIM_CCR5_GC5C available (TIMx_CCR5.GC5C available )*********/\n#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \\\n                                                       ((INSTANCE) == TIM8))\n/******************* TIM Instances : output(s) available **********************/\n#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \\\n    ((((INSTANCE) == TIM1) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_5) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_6)))           \\\n     ||                                        \\\n     (((INSTANCE) == TIM2) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n  ||                                           \\\n      (((INSTANCE) == TIM3) &&                 \\\n      (((CHANNEL) == TIM_CHANNEL_1)||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n  ||                                           \\\n      (((INSTANCE) == TIM4) &&                 \\\n      (((CHANNEL) == TIM_CHANNEL_1) ||         \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n  ||                                           \\\n      (((INSTANCE) == TIM5) &&                 \\\n      (((CHANNEL) == TIM_CHANNEL_1) ||         \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n  ||                                           \\\n      (((INSTANCE) == TIM8) &&                 \\\n      (((CHANNEL) == TIM_CHANNEL_1) ||         \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_5) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_6)))           \\\n  ||                                           \\\n     (((INSTANCE) == TIM12) &&                 \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2)))           \\\n  ||                                           \\\n     (((INSTANCE) == TIM13) &&                 \\\n     (((CHANNEL) == TIM_CHANNEL_1)))           \\\n  ||                                           \\\n     (((INSTANCE) == TIM14) &&                 \\\n     (((CHANNEL) == TIM_CHANNEL_1)))           \\\n  ||                                           \\\n     (((INSTANCE) == TIM15) &&                 \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n     ((CHANNEL) == TIM_CHANNEL_2)))            \\\n  ||                                           \\\n     (((INSTANCE) == TIM16) &&                 \\\n     (((CHANNEL) == TIM_CHANNEL_1)))           \\\n  ||                                           \\\n     (((INSTANCE) == TIM17) &&                 \\\n     (((CHANNEL) == TIM_CHANNEL_1))))\n\n/****************** TIM Instances : supporting the break function *************/\n#define IS_TIM_BREAK_INSTANCE(INSTANCE)\\\n      (((INSTANCE) == TIM1)    || \\\n      ((INSTANCE) == TIM8)     || \\\n       ((INSTANCE) == TIM15)   || \\\n       ((INSTANCE) == TIM16)   || \\\n       ((INSTANCE) == TIM17))\n\n/************** TIM Instances : supporting Break source selection *************/\n#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \\\n                                               ((INSTANCE) == TIM8))\n\n/****************** TIM Instances : supporting complementary output(s) ********/\n#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \\\n   ((((INSTANCE) == TIM1) &&                    \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||           \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||           \\\n      ((CHANNEL) == TIM_CHANNEL_3)))            \\\n ||                                             \\\n      (((INSTANCE) == TIM8) &&                  \\\n      (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||           \\\n      ((CHANNEL) == TIM_CHANNEL_3)))            \\\n    ||                                          \\\n    (((INSTANCE) == TIM15) &&                   \\\n      ((CHANNEL) == TIM_CHANNEL_1))             \\\n    ||                                          \\\n    (((INSTANCE) == TIM16) &&                   \\\n     ((CHANNEL) == TIM_CHANNEL_1))              \\\n    ||                                          \\\n    (((INSTANCE) == TIM17) &&                   \\\n     ((CHANNEL) == TIM_CHANNEL_1)))\n\n/****************** TIM Instances : supporting counting mode selection ********/\n#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\\\n  (((INSTANCE) == TIM1)    || \\\n   ((INSTANCE) == TIM2)    || \\\n   ((INSTANCE) == TIM3)    || \\\n   ((INSTANCE) == TIM4)    || \\\n   ((INSTANCE) == TIM5)    || \\\n   ((INSTANCE) == TIM8))\n\n/****************** TIM Instances : supporting repetition counter *************/\n#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\\\n  (((INSTANCE) == TIM1)    || \\\n   ((INSTANCE) == TIM8)    || \\\n   ((INSTANCE) == TIM15)   || \\\n   ((INSTANCE) == TIM16)   || \\\n   ((INSTANCE) == TIM17))\n\n/****************** TIM Instances : supporting synchronization ****************/\n#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\\\n    (((__INSTANCE__) == TIM1)    || \\\n     ((__INSTANCE__) == TIM2)    || \\\n     ((__INSTANCE__) == TIM3)    || \\\n     ((__INSTANCE__) == TIM4)    || \\\n     ((__INSTANCE__) == TIM5)    || \\\n     ((__INSTANCE__) == TIM6)    || \\\n     ((__INSTANCE__) == TIM8)    || \\\n     ((__INSTANCE__) == TIM12)   || \\\n     ((__INSTANCE__) == TIM15))\n\n/****************** TIM Instances : supporting clock division *****************/\n#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\\\n  (((INSTANCE) == TIM1)    || \\\n   ((INSTANCE) == TIM2)    || \\\n   ((INSTANCE) == TIM3)    || \\\n   ((INSTANCE) == TIM4)    || \\\n   ((INSTANCE) == TIM5)    || \\\n   ((INSTANCE) == TIM8)    || \\\n   ((INSTANCE) == TIM15)   || \\\n   ((INSTANCE) == TIM16)   || \\\n   ((INSTANCE) == TIM17))\n\n/****************** TIM Instances : supporting external clock mode 1 for ETRF input */\n#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\\\n  (((INSTANCE) == TIM1)    || \\\n   ((INSTANCE) == TIM2)    || \\\n   ((INSTANCE) == TIM3)    || \\\n   ((INSTANCE) == TIM4)    || \\\n   ((INSTANCE) == TIM5)    || \\\n   ((INSTANCE) == TIM8))\n\n/****************** TIM Instances : supporting external clock mode 2 **********/\n#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\\\n (((INSTANCE) == TIM1)     || \\\n   ((INSTANCE) == TIM2)    || \\\n   ((INSTANCE) == TIM3)    || \\\n   ((INSTANCE) == TIM4)    || \\\n   ((INSTANCE) == TIM5)    || \\\n   ((INSTANCE) == TIM8))\n\n/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/\n#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\\\n  (((INSTANCE) == TIM1)    || \\\n   ((INSTANCE) == TIM2)    || \\\n   ((INSTANCE) == TIM3)    || \\\n   ((INSTANCE) == TIM4)    || \\\n   ((INSTANCE) == TIM5)    || \\\n   ((INSTANCE) == TIM8)    || \\\n   ((INSTANCE) == TIM12)   || \\\n   ((INSTANCE) == TIM15))\n\n/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/\n#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\\\n  (((INSTANCE) == TIM1)    || \\\n   ((INSTANCE) == TIM2)    || \\\n   ((INSTANCE) == TIM3)    || \\\n   ((INSTANCE) == TIM4)    || \\\n   ((INSTANCE) == TIM5)    || \\\n   ((INSTANCE) == TIM8)    || \\\n   ((INSTANCE) == TIM12)   || \\\n   ((INSTANCE) == TIM15))\n\n/****************** TIM Instances : supporting OCxREF clear *******************/\n#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\\\n  (((INSTANCE) == TIM1)    || \\\n   ((INSTANCE) == TIM2)    || \\\n   ((INSTANCE) == TIM3))\n\n/****************** TIM Instances : TIM_32B_COUNTER ***************************/\n#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\\\n  (((INSTANCE) == TIM2)    || \\\n   ((INSTANCE) == TIM5))\n\n/****************** TIM Instances : TIM_BKIN2 ***************************/\n#define IS_TIM_BKIN2_INSTANCE(INSTANCE)\\\n  (((INSTANCE) == TIM1)    || \\\n   ((INSTANCE) == TIM8))\n\n/****************** TIM Instances : supporting Hall sensor interface **********/\n#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1)  || \\\n                                                             ((__INSTANCE__) == TIM2)  || \\\n                                                             ((__INSTANCE__) == TIM3)  || \\\n                                                             ((__INSTANCE__) == TIM4)  || \\\n                                                             ((__INSTANCE__) == TIM5)  || \\\n                                                             ((__INSTANCE__) == TIM15) || \\\n                                                             ((__INSTANCE__) == TIM8))\n\n/****************************** HRTIM Instances *******************************/\n#define IS_HRTIM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HRTIM1))\n\n/******************** USART Instances : Synchronous mode **********************/\n#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                     ((INSTANCE) == USART2) || \\\n                                     ((INSTANCE) == USART3) || \\\n                                     ((INSTANCE) == USART6))\n\n/******************** USART Instances : SPI slave mode ************************/\n#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                              ((INSTANCE) == USART2) || \\\n                                              ((INSTANCE) == USART3) || \\\n                                              ((INSTANCE) == USART6))\n\n/******************** UART Instances : Asynchronous mode **********************/\n#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                    ((INSTANCE) == USART2) || \\\n                                    ((INSTANCE) == USART3) || \\\n                                    ((INSTANCE) == UART4)  || \\\n                                    ((INSTANCE) == UART5)  || \\\n                                    ((INSTANCE) == USART6) || \\\n                                    ((INSTANCE) == UART7)  || \\\n                                    ((INSTANCE) == UART8))\n\n/******************** UART Instances : FIFO mode.******************************/\n#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                         ((INSTANCE) == USART2) || \\\n                                         ((INSTANCE) == USART3) || \\\n                                         ((INSTANCE) == UART4)  || \\\n                                         ((INSTANCE) == UART5)  || \\\n                                         ((INSTANCE) == USART6) || \\\n                                         ((INSTANCE) == UART7)  || \\\n                                         ((INSTANCE) == UART8))\n\n/****************** UART Instances : Auto Baud Rate detection *****************/\n#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                                            ((INSTANCE) == USART2) || \\\n                                                            ((INSTANCE) == USART3) || \\\n                                                            ((INSTANCE) == UART4)  || \\\n                                                            ((INSTANCE) == UART5)  || \\\n                                                            ((INSTANCE) == USART6) || \\\n                                                            ((INSTANCE) == UART7)  || \\\n                                                            ((INSTANCE) == UART8))\n\n/*********************** UART Instances : Driver Enable ***********************/\n#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                                  ((INSTANCE) == USART2) || \\\n                                                  ((INSTANCE) == USART3) || \\\n                                                  ((INSTANCE) == UART4)  || \\\n                                                  ((INSTANCE) == UART5)  || \\\n                                                  ((INSTANCE) == USART6) || \\\n                                                  ((INSTANCE) == UART7)  || \\\n                                                  ((INSTANCE) == UART8)  || \\\n                                                  ((INSTANCE) == LPUART1))\n\n/********************* UART Instances : Half-Duplex mode **********************/\n#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                               ((INSTANCE) == USART2) || \\\n                                               ((INSTANCE) == USART3) || \\\n                                               ((INSTANCE) == UART4)  || \\\n                                               ((INSTANCE) == UART5)  || \\\n                                               ((INSTANCE) == USART6) || \\\n                                               ((INSTANCE) == UART7)  || \\\n                                               ((INSTANCE) == UART8)  || \\\n                                               ((INSTANCE) == LPUART1))\n\n/******************* UART Instances : Hardware Flow control *******************/\n#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                           ((INSTANCE) == USART2) || \\\n                                           ((INSTANCE) == USART3) || \\\n                                           ((INSTANCE) == UART4)  || \\\n                                           ((INSTANCE) == UART5)  || \\\n                                           ((INSTANCE) == USART6) || \\\n                                           ((INSTANCE) == UART7)  || \\\n                                           ((INSTANCE) == UART8)  || \\\n                                           ((INSTANCE) == LPUART1))\n\n/************************* UART Instances : LIN mode **************************/\n#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                        ((INSTANCE) == USART2) || \\\n                                        ((INSTANCE) == USART3) || \\\n                                        ((INSTANCE) == UART4)  || \\\n                                        ((INSTANCE) == UART5)  || \\\n                                        ((INSTANCE) == USART6) || \\\n                                        ((INSTANCE) == UART7)  || \\\n                                        ((INSTANCE) == UART8))\n\n/****************** UART Instances : Wake-up from Stop mode *******************/\n#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                                    ((INSTANCE) == USART2) || \\\n                                                    ((INSTANCE) == USART3) || \\\n                                                    ((INSTANCE) == UART4)  || \\\n                                                    ((INSTANCE) == UART5)  || \\\n                                                    ((INSTANCE) == USART6) || \\\n                                                    ((INSTANCE) == UART7)  || \\\n                                                    ((INSTANCE) == UART8)  || \\\n                                                    ((INSTANCE) == LPUART1))\n\n/************************* UART Instances : IRDA mode *************************/\n#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                    ((INSTANCE) == USART2) || \\\n                                    ((INSTANCE) == USART3) || \\\n                                    ((INSTANCE) == UART4)  || \\\n                                    ((INSTANCE) == UART5)  || \\\n                                    ((INSTANCE) == USART6) || \\\n                                    ((INSTANCE) == UART7)  || \\\n                                    ((INSTANCE) == UART8))\n\n/********************* USART Instances : Smard card mode **********************/\n#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                         ((INSTANCE) == USART2) || \\\n                                         ((INSTANCE) == USART3) || \\\n                                         ((INSTANCE) == USART6))\n\n/****************************** LPUART Instance *******************************/\n#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)\n\n/****************************** IWDG Instances ********************************/\n#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG1)\n/****************************** USB Instances ********************************/\n#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)\n\n/****************************** WWDG Instances ********************************/\n#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG1)\n/****************************** MDIOS Instances ********************************/\n#define IS_MDIOS_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == MDIOS)\n\n/****************************** CEC Instances *********************************/\n#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)\n\n/****************************** SAI Instances ********************************/\n#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \\\n                    ((INSTANCE) == SAI1_Block_B) || \\\n                     ((INSTANCE) == SAI2_Block_A) || \\\n                     ((INSTANCE) == SAI2_Block_B) || \\\n                     ((INSTANCE) == SAI3_Block_A) || \\\n                     ((INSTANCE) == SAI3_Block_B) || \\\n                     ((INSTANCE) == SAI4_Block_A) || \\\n                     ((INSTANCE) == SAI4_Block_B))\n\n/****************************** SPDIFRX Instances ********************************/\n#define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX)\n\n/****************************** OPAMP Instances *******************************/\n#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \\\n                                         ((INSTANCE) == OPAMP2))\n\n#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)\n\n/*********************** USB OTG PCD Instances ********************************/\n#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \\\n                                        ((INSTANCE) == USB_OTG_HS))\n\n/*********************** USB OTG HCD Instances ********************************/\n#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \\\n                                       ((INSTANCE) == USB_OTG_HS))\n\n/******************************************************************************/\n/*  For a painless codes migration between the STM32H7xx device product       */\n/*  lines, or with STM32F7xx devices the aliases defined below are put        */\n/*   in place to overcome the differences in the interrupt handlers and IRQn  */\n/*   definitions. No need to update developed interrupt code when moving      */\n/*  across product lines within the same STM32H7 Family                       */\n/******************************************************************************/\n\n/* Aliases for __IRQn */\n#define  HASH_RNG_IRQn                  RNG_IRQn\n#define  TIM1_BRK_TIM9_IRQn             TIM1_BRK_IRQn\n#define  TIM1_UP_TIM10_IRQn             TIM1_UP_IRQn\n#define  TIM1_TRG_COM_TIM11_IRQn        TIM1_TRG_COM_IRQn\n#define  PVD_IRQn                       PVD_AVD_IRQn\n\n\n\n/* Aliases for __IRQHandler */\n#define  HASH_RNG_IRQHandler           RNG_IRQHandler\n#define TIM1_BRK_TIM9_IRQHandler       TIM1_BRK_IRQHandler\n#define TIM1_UP_TIM9_IRQHandler        TIM1_UP_IRQHandler\n#define TIM1_TRG_COM_TIM11_IRQHandler  TIM1_TRG_COM_IRQHandler\n#define PVD_IRQHandler                 PVD_AVD_IRQHandler\n\n/* Aliases for COMP __IRQHandler */\n#define COMP_IRQHandler                COMP1_IRQHandler\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* STM32H743xx_H */\n\n"
  },
  {
    "path": "3rd_party/nucleo-h743zi/stm32h7xx.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32h7xx.h\n  * @author  MCD Application Team\n  * @brief   CMSIS STM32H7xx Device Peripheral Access Layer Header File.\n  *\n  *          The file is the unique include file that the application programmer\n  *          is using in the C source code, usually in main.c. This file contains:\n  *           - Configuration section that allows to select:\n  *              - The STM32H7xx device used in the target application\n  *              - To use or not the peripheral's drivers in application code(i.e.\n  *                code will be based on direct access to peripheral's registers\n  *                rather than drivers API), this option is controlled by\n  *                \"#define USE_HAL_DRIVER\"\n  *\n  ******************************************************************************\n  * @attention\n  *\n  * Copyright (c) 2017 STMicroelectronics.\n  * All rights reserved.\n  *\n  * This software is licensed under terms that can be found in the LICENSE file\n  * in the root directory of this software component.\n  * If no LICENSE file comes with this software, it is provided AS-IS.\n  *\n  ******************************************************************************\n  */\n\n/** @addtogroup CMSIS\n  * @{\n  */\n\n/** @addtogroup stm32h7xx\n  * @{\n  */\n\n#ifndef STM32H7xx_H\n#define STM32H7xx_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif /* __cplusplus */\n\n/** @addtogroup Library_configuration_section\n  * @{\n  */\n\n/**\n  * @brief STM32 Family\n  */\n#if !defined  (STM32H7)\n#define STM32H7\n#endif /* STM32H7 */\n\n\n/* Uncomment the line below according to the target STM32H7 device used in your\n   application\n  */\n\n#if !defined (STM32H743xx) && !defined (STM32H753xx)  && !defined (STM32H750xx) && !defined (STM32H742xx) && \\\n    !defined (STM32H745xx) && !defined (STM32H745xG)  && !defined (STM32H755xx)  && !defined (STM32H747xx) && !defined (STM32H747xG)&& !defined (STM32H757xx) && \\\n    !defined (STM32H7A3xx) && !defined (STM32H7A3xxQ) && !defined (STM32H7B3xx) && !defined (STM32H7B3xxQ) && !defined (STM32H7B0xx)  && !defined (STM32H7B0xxQ) && \\\n    !defined (STM32H735xx) && !defined (STM32H733xx)  && !defined (STM32H730xx) && !defined (STM32H730xxQ)  && !defined (STM32H725xx) && !defined (STM32H723xx)\n  /* #define STM32H742xx */   /*!< STM32H742VI, STM32H742ZI, STM32H742AI, STM32H742II, STM32H742BI, STM32H742XI Devices */\n  /* #define STM32H743xx */   /*!< STM32H743VI, STM32H743ZI, STM32H743AI, STM32H743II, STM32H743BI, STM32H743XI Devices */\n  /* #define STM32H753xx */   /*!< STM32H753VI, STM32H753ZI, STM32H753AI, STM32H753II, STM32H753BI, STM32H753XI Devices */\n  /* #define STM32H750xx */   /*!< STM32H750V, STM32H750I, STM32H750X Devices */\n  /* #define STM32H747xx */   /*!< STM32H747ZI, STM32H747AI, STM32H747II, STM32H747BI, STM32H747XI Devices */\n  /* #define STM32H747xG */   /*!< STM32H747AG, STM32H747IG, STM32H747BG, STM32H747XG */\n  /* #define STM32H757xx */   /*!< STM32H757ZI, STM32H757AI, STM32H757II, STM32H757BI, STM32H757XI Devices */\n  /* #define STM32H745xx */   /*!< STM32H745ZI, STM32H745II, STM32H745BI, STM32H745XI Devices  */\n  /* #define STM32H745xG */   /*!< STM32H745ZG, STM32H745IG, STM32H745BG, STM32H745XG Devices  */\n  /* #define STM32H755xx */   /*!< STM32H755ZI, STM32H755II, STM32H755BI, STM32H755XI Devices  */\n  /* #define STM32H7B0xx */   /*!< STM32H7B0ABIxQ, STM32H7B0IBTx, STM32H7B0RBTx, STM32H7B0VBTx, STM32H7B0ZBTx, STM32H7B0IBKxQ */\n  /* #define STM32H7A3xx */   /*!< STM32H7A3IIK6, STM32H7A3IIT6, STM32H7A3NIH6, STM32H7A3RIT6, STM32H7A3VIH6, STM32H7A3VIT6, STM32H7A3ZIT6 */\n  /* #define STM32H7A3xxQ */  /*!< STM32H7A3QIY6Q, STM32H7A3IIK6Q, STM32H7A3IIT6Q, STM32H7A3LIH6Q, STM32H7A3VIH6Q, STM32H7A3VIT6Q, STM32H7A3AII6Q, STM32H7A3ZIT6Q */\n  /* #define STM32H7B3xx */   /*!< STM32H7B3IIK6, STM32H7B3IIT6, STM32H7B3NIH6, STM32H7B3RIT6, STM32H7B3VIH6, STM32H7B3VIT6, STM32H7B3ZIT6 */\n  /* #define STM32H7B3xxQ */  /*!< STM32H7B3QIY6Q, STM32H7B3IIK6Q, STM32H7B3IIT6Q, STM32H7B3LIH6Q, STM32H7B3VIH6Q, STM32H7B3VIT6Q, STM32H7B3AII6Q, STM32H7B3ZIT6Q */\n  /* #define STM32H735xx */   /*!< STM32H735AGI6, STM32H735IGK6, STM32H735RGV6, STM32H735VGT6, STM32H735VGY6, STM32H735ZGT6 Devices */\n  /* #define STM32H733xx */   /*!< STM32H733VGH6, STM32H733VGT6, STM32H733ZGI6, STM32H733ZGT6, Devices */\n  /* #define STM32H730xx */   /*!< STM32H730VBH6, STM32H730VBT6, STM32H730ZBT6, STM32H730ZBI6 Devices */\n  /* #define STM32H730xxQ */  /*!< STM32H730IBT6Q, STM32H730ABI6Q, STM32H730IBK6Q Devices */\n  /* #define STM32H725xx */   /*!< STM32H725AGI6, STM32H725IGK6, STM32H725IGT6, STM32H725RGV6, STM32H725VGT6, STM32H725VGY6, STM32H725ZGT6, STM32H725REV6, SM32H725VET6, STM32H725ZET6, STM32H725AEI6, STM32H725IET6, STM32H725IEK6  Devices */\n  /* #define STM32H723xx */   /*!< STM32H723VGH6, STM32H723VGT6, STM32H723ZGI6, STM32H723ZGT6, STM32H723VET6, STM32H723VEH6, STM32H723ZET6, STM32H723ZEI6 Devices */\n#endif\n\n/*  Tip: To avoid modifying this file each time you need to switch between these\n        devices, you can define the device in your toolchain compiler preprocessor.\n  */\n\n#if defined(DUAL_CORE) && !defined(CORE_CM4) && !defined(CORE_CM7)\n #error \"Dual core device, please select CORE_CM4 or CORE_CM7\"\n#endif\n\n#if !defined  (USE_HAL_DRIVER)\n/**\n * @brief Comment the line below if you will not use the peripherals drivers.\n   In this case, these drivers will not be included and the application code will\n   be based on direct access to peripherals registers\n   */\n  /*#define USE_HAL_DRIVER */\n#endif /* USE_HAL_DRIVER */\n\n/**\n  * @brief CMSIS Device version number V1.10.1\n  */\n#define __STM32H7xx_CMSIS_DEVICE_VERSION_MAIN   (0x01) /*!< [31:24] main version */\n#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1   (0x0A) /*!< [23:16] sub1 version */\n#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB2   (0x01) /*!< [15:8]  sub2 version */\n#define __STM32H7xx_CMSIS_DEVICE_VERSION_RC     (0x00) /*!< [7:0]  release candidate */\n#define __STM32H7xx_CMSIS_DEVICE_VERSION        ((__STM32H7xx_CMSIS_DEVICE_VERSION_MAIN     << 24)\\\n                                      |(__STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 << 16)\\\n                                      |(__STM32H7xx_CMSIS_DEVICE_VERSION_SUB2 << 8 )\\\n                                      |(__STM32H7xx_CMSIS_DEVICE_VERSION_RC))\n\n/**\n  * @}\n  */\n\n/** @addtogroup Device_Included\n  * @{\n  */\n\n#if defined(STM32H743xx)\n  #include \"stm32h743xx.h\"\n#elif defined(STM32H753xx)\n  #include \"stm32h753xx.h\"\n#elif defined(STM32H750xx)\n  #include \"stm32h750xx.h\"\n#elif defined(STM32H742xx)\n  #include \"stm32h742xx.h\"\n#elif defined(STM32H745xx)\n  #include \"stm32h745xx.h\"\n#elif defined(STM32H745xG)\n  #include \"stm32h745xg.h\"\n#elif defined(STM32H755xx)\n  #include \"stm32h755xx.h\"\n#elif defined(STM32H747xx)\n  #include \"stm32h747xx.h\"\n#elif defined(STM32H747xG)\n  #include \"stm32h747xg.h\"\n#elif defined(STM32H757xx)\n  #include \"stm32h757xx.h\"\n#elif defined(STM32H7B0xx)\n  #include \"stm32h7b0xx.h\"\n#elif defined(STM32H7B0xxQ)\n  #include \"stm32h7b0xxq.h\"\n#elif defined(STM32H7A3xx)\n  #include \"stm32h7a3xx.h\"\n#elif defined(STM32H7B3xx)\n  #include \"stm32h7b3xx.h\"\n#elif defined(STM32H7A3xxQ)\n  #include \"stm32h7a3xxq.h\"\n#elif defined(STM32H7B3xxQ)\n  #include \"stm32h7b3xxq.h\"\n#elif defined(STM32H735xx)\n  #include \"stm32h735xx.h\"\n#elif defined(STM32H733xx)\n  #include \"stm32h733xx.h\"\n#elif defined(STM32H730xx)\n  #include \"stm32h730xx.h\"\n#elif defined(STM32H730xxQ)\n  #include \"stm32h730xxq.h\"\n#elif defined(STM32H725xx)\n  #include \"stm32h725xx.h\"\n#elif defined(STM32H723xx)\n  #include \"stm32h723xx.h\"\n#else\n #error \"Please select first the target STM32H7xx device used in your application (in stm32h7xx.h file)\"\n#endif\n\n/**\n  * @}\n  */\n\n/** @addtogroup Exported_types\n  * @{\n  */\ntypedef enum\n{\n  RESET = 0,\n  SET = !RESET\n} FlagStatus, ITStatus;\n\ntypedef enum\n{\n  DISABLE = 0,\n  ENABLE = !DISABLE\n} FunctionalState;\n#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))\n\ntypedef enum\n{\n  SUCCESS = 0,\n  ERROR = !SUCCESS\n} ErrorStatus;\n\n/**\n  * @}\n  */\n\n\n/** @addtogroup Exported_macros\n  * @{\n  */\n#define SET_BIT(REG, BIT)     ((REG) |= (BIT))\n\n#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))\n\n#define READ_BIT(REG, BIT)    ((REG) & (BIT))\n\n#define CLEAR_REG(REG)        ((REG) = (0x0))\n\n#define WRITE_REG(REG, VAL)   ((REG) = (VAL))\n\n#define READ_REG(REG)         ((REG))\n\n#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))\n\n#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL)))\n\n/* Use of CMSIS compiler intrinsics for register exclusive access */\n/* Atomic 32-bit register access macro to set one or several bits */\n#define ATOMIC_SET_BIT(REG, BIT)                             \\\n  do {                                                       \\\n    uint32_t val;                                            \\\n    do {                                                     \\\n      val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT);       \\\n    } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \\\n  } while(0)\n\n/* Atomic 32-bit register access macro to clear one or several bits */\n#define ATOMIC_CLEAR_BIT(REG, BIT)                           \\\n  do {                                                       \\\n    uint32_t val;                                            \\\n    do {                                                     \\\n      val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT);      \\\n    } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \\\n  } while(0)\n\n/* Atomic 32-bit register access macro to clear and set one or several bits */\n#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK)                          \\\n  do {                                                                     \\\n    uint32_t val;                                                          \\\n    do {                                                                   \\\n      val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \\\n    } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U);               \\\n  } while(0)\n\n/* Atomic 16-bit register access macro to set one or several bits */\n#define ATOMIC_SETH_BIT(REG, BIT)                            \\\n  do {                                                       \\\n    uint16_t val;                                            \\\n    do {                                                     \\\n      val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT);       \\\n    } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \\\n  } while(0)\n\n/* Atomic 16-bit register access macro to clear one or several bits */\n#define ATOMIC_CLEARH_BIT(REG, BIT)                          \\\n  do {                                                       \\\n    uint16_t val;                                            \\\n    do {                                                     \\\n      val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT);      \\\n    } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \\\n  } while(0)\n\n/* Atomic 16-bit register access macro to clear and set one or several bits */\n#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK)                         \\\n  do {                                                                     \\\n    uint16_t val;                                                          \\\n    do {                                                                   \\\n      val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \\\n    } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U);               \\\n  } while(0)\n\n/**\n  * @}\n  */\n\n#if defined (USE_HAL_DRIVER)\n #include \"stm32h7xx_hal.h\"\n#endif /* USE_HAL_DRIVER */\n\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* STM32H7xx_H */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n\n\n\n"
  },
  {
    "path": "3rd_party/nucleo-h743zi/system_stm32h7xx.c",
    "content": "/**\n  ******************************************************************************\n  * @file    system_stm32h7xx.c\n  * @author  MCD Application Team\n  * @brief   CMSIS Cortex-Mx Device Peripheral Access Layer System Source File.\n  *\n  *   This file provides two functions and one global variable to be called from\n  *   user application:\n  *      - SystemInit(): This function is called at startup just after reset and\n  *                      before branch to main program. This call is made inside\n  *                      the \"startup_stm32h7xx.s\" file.\n  *\n  *      - SystemCoreClock variable: Contains the core clock, it can be used\n  *                                  by the user application to setup the SysTick\n  *                                  timer or configure other parameters.\n  *\n  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must\n  *                                 be called whenever the core clock is changed\n  *                                 during program execution.\n  *\n  *\n  ******************************************************************************\n  * @attention\n  *\n  * Copyright (c) 2017 STMicroelectronics.\n  * All rights reserved.\n  *\n  * This software is licensed under terms that can be found in the LICENSE file\n  * in the root directory of this software component.\n  * If no LICENSE file comes with this software, it is provided AS-IS.\n  *\n  ******************************************************************************\n  */\n\n/** @addtogroup CMSIS\n  * @{\n  */\n\n/** @addtogroup stm32h7xx_system\n  * @{\n  */\n\n/** @addtogroup STM32H7xx_System_Private_Includes\n  * @{\n  */\n\n#include \"stm32h7xx.h\"\n#include <math.h>\n#if !defined  (HSE_VALUE)\n#define HSE_VALUE    ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */\n#endif /* HSE_VALUE */\n\n#if !defined  (CSI_VALUE)\n  #define CSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/\n#endif /* CSI_VALUE */\n\n#if !defined  (HSI_VALUE)\n  #define HSI_VALUE    ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/\n#endif /* HSI_VALUE */\n\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32H7xx_System_Private_TypesDefinitions\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32H7xx_System_Private_Defines\n  * @{\n  */\n\n/************************* Miscellaneous Configuration ************************/\n/*!< Uncomment the following line if you need to use initialized data in D2 domain SRAM (AHB SRAM) */\n/* #define DATA_IN_D2_SRAM */\n\n/* Note: Following vector table addresses must be defined in line with linker\n         configuration. */\n/*!< Uncomment the following line if you need to relocate the vector table\n     anywhere in FLASH BANK1 or AXI SRAM, else the vector table is kept at the automatic\n     remap of boot address selected */\n/* #define USER_VECT_TAB_ADDRESS */\n\n#if defined(USER_VECT_TAB_ADDRESS)\n#if defined(DUAL_CORE) && defined(CORE_CM4)\n/*!< Uncomment the following line if you need to relocate your vector Table\n     in D2 AXI SRAM else user remap will be done in FLASH BANK2. */\n/* #define VECT_TAB_SRAM */\n#if defined(VECT_TAB_SRAM)\n#define VECT_TAB_BASE_ADDRESS   D2_AXISRAM_BASE   /*!< Vector Table base address field.\n                                                       This value must be a multiple of 0x200. */\n#define VECT_TAB_OFFSET         0x00000000U       /*!< Vector Table base offset field.\n                                                       This value must be a multiple of 0x200. */\n#else\n#define VECT_TAB_BASE_ADDRESS   FLASH_BANK2_BASE  /*!< Vector Table base address field.\n                                                       This value must be a multiple of 0x200. */\n#define VECT_TAB_OFFSET         0x00000000U       /*!< Vector Table base offset field.\n                                                       This value must be a multiple of 0x200. */\n#endif /* VECT_TAB_SRAM */\n#else\n/*!< Uncomment the following line if you need to relocate your vector Table\n     in D1 AXI SRAM else user remap will be done in FLASH BANK1. */\n/* #define VECT_TAB_SRAM */\n#if defined(VECT_TAB_SRAM)\n#define VECT_TAB_BASE_ADDRESS   D1_AXISRAM_BASE   /*!< Vector Table base address field.\n                                                       This value must be a multiple of 0x200. */\n#define VECT_TAB_OFFSET         0x00000000U       /*!< Vector Table base offset field.\n                                                       This value must be a multiple of 0x200. */\n#else\n#define VECT_TAB_BASE_ADDRESS   FLASH_BANK1_BASE  /*!< Vector Table base address field.\n                                                       This value must be a multiple of 0x200. */\n#define VECT_TAB_OFFSET         0x00000000U       /*!< Vector Table base offset field.\n                                                       This value must be a multiple of 0x200. */\n#endif /* VECT_TAB_SRAM */\n#endif /* DUAL_CORE && CORE_CM4 */\n#endif /* USER_VECT_TAB_ADDRESS */\n/******************************************************************************/\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32H7xx_System_Private_Macros\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32H7xx_System_Private_Variables\n  * @{\n  */\n  /* This variable is updated in three ways:\n      1) by calling CMSIS function SystemCoreClockUpdate()\n      2) by calling HAL API function HAL_RCC_GetHCLKFreq()\n      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency\n         Note: If you use this function to configure the system clock; then there\n               is no need to call the 2 first functions listed above, since SystemCoreClock\n               variable is updated automatically.\n  */\n  uint32_t SystemCoreClock = 64000000;\n  uint32_t SystemD2Clock = 64000000;\n  const  uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32H7xx_System_Private_FunctionPrototypes\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32H7xx_System_Private_Functions\n  * @{\n  */\n\n/**\n  * @brief  Setup the microcontroller system\n  *         Initialize the FPU setting and  vector table location\n  *         configuration.\n  * @param  None\n  * @retval None\n  */\nvoid SystemInit (void)\n{\n#if defined (DATA_IN_D2_SRAM)\n __IO uint32_t tmpreg;\n#endif /* DATA_IN_D2_SRAM */\n\n  /* FPU settings ------------------------------------------------------------*/\n  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\n    SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2)));  /* set CP10 and CP11 Full Access */\n  #endif\n  /* Reset the RCC clock configuration to the default reset state ------------*/\n\n   /* Increasing the CPU frequency */\n  if(FLASH_LATENCY_DEFAULT  > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))\n  {\n    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */\n    MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));\n  }\n\n  /* Set HSION bit */\n  RCC->CR |= RCC_CR_HSION;\n\n  /* Reset CFGR register */\n  RCC->CFGR = 0x00000000;\n\n  /* Reset HSEON, HSECSSON, CSION, HSI48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */\n  RCC->CR &= 0xEAF6ED7FU;\n\n   /* Decreasing the number of wait states because of lower CPU frequency */\n  if(FLASH_LATENCY_DEFAULT  < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))\n  {\n    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */\n    MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));\n  }\n\n#if defined(D3_SRAM_BASE)\n  /* Reset D1CFGR register */\n  RCC->D1CFGR = 0x00000000;\n\n  /* Reset D2CFGR register */\n  RCC->D2CFGR = 0x00000000;\n\n  /* Reset D3CFGR register */\n  RCC->D3CFGR = 0x00000000;\n#else\n  /* Reset CDCFGR1 register */\n  RCC->CDCFGR1 = 0x00000000;\n\n  /* Reset CDCFGR2 register */\n  RCC->CDCFGR2 = 0x00000000;\n\n  /* Reset SRDCFGR register */\n  RCC->SRDCFGR = 0x00000000;\n#endif\n  /* Reset PLLCKSELR register */\n  RCC->PLLCKSELR = 0x02020200;\n\n  /* Reset PLLCFGR register */\n  RCC->PLLCFGR = 0x01FF0000;\n  /* Reset PLL1DIVR register */\n  RCC->PLL1DIVR = 0x01010280;\n  /* Reset PLL1FRACR register */\n  RCC->PLL1FRACR = 0x00000000;\n\n  /* Reset PLL2DIVR register */\n  RCC->PLL2DIVR = 0x01010280;\n\n  /* Reset PLL2FRACR register */\n\n  RCC->PLL2FRACR = 0x00000000;\n  /* Reset PLL3DIVR register */\n  RCC->PLL3DIVR = 0x01010280;\n\n  /* Reset PLL3FRACR register */\n  RCC->PLL3FRACR = 0x00000000;\n\n  /* Reset HSEBYP bit */\n  RCC->CR &= 0xFFFBFFFFU;\n\n  /* Disable all interrupts */\n  RCC->CIER = 0x00000000;\n\n#if (STM32H7_DEV_ID == 0x450UL)\n  /* dual core CM7 or single core line */\n  if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U)\n  {\n    /* if stm32h7 revY*/\n    /* Change  the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */\n    *((__IO uint32_t*)0x51008108) = 0x000000001U;\n  }\n#endif\n\n#if defined (DATA_IN_D2_SRAM)\n  /* in case of initialized data in D2 SRAM (AHB SRAM) , enable the D2 SRAM clock (AHB SRAM clock) */\n#if defined(RCC_AHB2ENR_D2SRAM3EN)\n  RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN);\n#elif defined(RCC_AHB2ENR_D2SRAM2EN)\n  RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN);\n#else\n  RCC->AHB2ENR |= (RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN);\n#endif /* RCC_AHB2ENR_D2SRAM3EN */\n\n  tmpreg = RCC->AHB2ENR;\n  (void) tmpreg;\n#endif /* DATA_IN_D2_SRAM */\n\n#if defined(DUAL_CORE) && defined(CORE_CM4)\n  /* Configure the Vector Table location add offset address for cortex-M4 ------------------*/\n#if defined(USER_VECT_TAB_ADDRESS)\n  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D2 AXI-RAM or in Internal FLASH */\n#endif /* USER_VECT_TAB_ADDRESS */\n\n#else\n\n  /*\n   * Disable the FMC bank1 (enabled after reset).\n   * This, prevents CPU speculation access on this bank which blocks the use of FMC during\n   * 24us. During this time the others FMC master (such as LTDC) cannot use it!\n   */\n  FMC_Bank1_R->BTCR[0] = 0x000030D2;\n\n  /* Configure the Vector Table location -------------------------------------*/\n#if defined(USER_VECT_TAB_ADDRESS)\n  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM or in Internal FLASH */\n#endif /* USER_VECT_TAB_ADDRESS */\n\n#endif /*DUAL_CORE && CORE_CM4*/\n\n}\n\n/**\n   * @brief  Update SystemCoreClock variable according to Clock Register Values.\n  *         The SystemCoreClock variable contains the core clock , it can\n  *         be used by the user application to setup the SysTick timer or configure\n  *         other parameters.\n  *\n  * @note   Each time the core clock changes, this function must be called\n  *         to update SystemCoreClock variable value. Otherwise, any configuration\n  *         based on this variable will be incorrect.\n  *\n  * @note   - The system frequency computed by this function is not the real\n  *           frequency in the chip. It is calculated based on the predefined\n  *           constant and the selected clock source:\n  *\n  *           - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*)\n  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)\n  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)\n  *           - If SYSCLK source is PLL, SystemCoreClock will contain the CSI_VALUE(*),\n  *             HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.\n  *\n  *         (*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value\n  *             4 MHz) but the real value may vary depending on the variations\n  *             in voltage and temperature.\n  *         (**) HSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value\n  *             64 MHz) but the real value may vary depending on the variations\n  *             in voltage and temperature.\n  *\n  *         (***)HSE_VALUE is a constant defined in stm32h7xx_hal.h file (default value\n  *              25 MHz), user has to ensure that HSE_VALUE is same as the real\n  *              frequency of the crystal used. Otherwise, this function may\n  *              have wrong result.\n  *\n  *         - The result of this function could be not correct when using fractional\n  *           value for HSE crystal.\n  * @param  None\n  * @retval None\n  */\nvoid SystemCoreClockUpdate (void)\n{\n  uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp;\n  uint32_t common_system_clock;\n  float_t fracn1, pllvco;\n\n\n  /* Get SYSCLK source -------------------------------------------------------*/\n\n  switch (RCC->CFGR & RCC_CFGR_SWS)\n  {\n  case RCC_CFGR_SWS_HSI:  /* HSI used as system clock source */\n    common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));\n    break;\n\n  case RCC_CFGR_SWS_CSI:  /* CSI used as system clock  source */\n    common_system_clock = CSI_VALUE;\n    break;\n\n  case RCC_CFGR_SWS_HSE:  /* HSE used as system clock  source */\n    common_system_clock = HSE_VALUE;\n    break;\n\n  case RCC_CFGR_SWS_PLL1:  /* PLL1 used as system clock  source */\n\n    /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN\n    SYSCLK = PLL_VCO / PLLR\n    */\n    pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);\n    pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4)  ;\n    pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos);\n    fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));\n\n    if (pllm != 0U)\n    {\n      switch (pllsource)\n      {\n        case RCC_PLLCKSELR_PLLSRC_HSI:  /* HSI used as PLL clock source */\n\n        hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;\n        pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );\n\n        break;\n\n        case RCC_PLLCKSELR_PLLSRC_CSI:  /* CSI used as PLL clock source */\n          pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );\n        break;\n\n        case RCC_PLLCKSELR_PLLSRC_HSE:  /* HSE used as PLL clock source */\n          pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );\n        break;\n\n      default:\n          hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;\n          pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );\n        break;\n      }\n      pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ;\n      common_system_clock =  (uint32_t)(float_t)(pllvco/(float_t)pllp);\n    }\n    else\n    {\n      common_system_clock = 0U;\n    }\n    break;\n\n  default:\n    common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));\n    break;\n  }\n\n  /* Compute SystemClock frequency --------------------------------------------------*/\n#if defined (RCC_D1CFGR_D1CPRE)\n  tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos];\n\n  /* common_system_clock frequency : CM7 CPU frequency  */\n  common_system_clock >>= tmp;\n\n  /* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency  */\n  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));\n\n#else\n  tmp = D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos];\n\n  /* common_system_clock frequency : CM7 CPU frequency  */\n  common_system_clock >>= tmp;\n\n  /* SystemD2Clock frequency : AXI and AHBs Clock frequency  */\n  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));\n\n#endif\n\n#if defined(DUAL_CORE) && defined(CORE_CM4)\n  SystemCoreClock = SystemD2Clock;\n#else\n  SystemCoreClock = common_system_clock;\n#endif /* DUAL_CORE && CORE_CM4 */\n}\n\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n"
  },
  {
    "path": "3rd_party/nucleo-h743zi/system_stm32h7xx.h",
    "content": "/**\n  ******************************************************************************\n  * @file    system_stm32h7xx.h\n  * @author  MCD Application Team\n  * @brief   CMSIS Cortex-Mx Device System Source File for STM32H7xx devices.\n  ******************************************************************************\n  * @attention\n  *\n  * Copyright (c) 2017 STMicroelectronics.\n  * All rights reserved.\n  *\n  * This software is licensed under terms that can be found in the LICENSE file\n  * in the root directory of this software component.\n  * If no LICENSE file comes with this software, it is provided AS-IS.\n  *\n  ******************************************************************************\n  */\n\n/** @addtogroup CMSIS\n  * @{\n  */\n\n/** @addtogroup stm32h7xx_system\n  * @{\n  */\n\n/**\n  * @brief Define to prevent recursive inclusion\n  */\n#ifndef SYSTEM_STM32H7XX_H\n#define SYSTEM_STM32H7XX_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/** @addtogroup STM32H7xx_System_Includes\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n\n/** @addtogroup STM32H7xx_System_Exported_types\n  * @{\n  */\n  /* This variable is updated in three ways:\n      1) by calling CMSIS function SystemCoreClockUpdate()\n      2) by calling HAL API function HAL_RCC_GetSysClockFreq()\n      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency\n         Note: If you use this function to configure the system clock; then there\n               is no need to call the 2 first functions listed above, since SystemCoreClock\n               variable is updated automatically.\n  */\nextern uint32_t SystemCoreClock;             /*!< System Domain1 Clock Frequency  */\nextern uint32_t SystemD2Clock;               /*!< System Domain2 Clock Frequency  */\nextern const  uint8_t D1CorePrescTable[16] ; /*!< D1CorePrescTable prescalers table values */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32H7xx_System_Exported_Constants\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32H7xx_System_Exported_Macros\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32H7xx_System_Exported_Functions\n  * @{\n  */\n\nextern void SystemInit(void);\nextern void SystemCoreClockUpdate(void);\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* SYSTEM_STM32H7XX_H */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n"
  },
  {
    "path": "3rd_party/nucleo-l053r8/README.txt",
    "content": "This folder contains the support code for the NUCLEO-L053R8 board.\n\n\nCMSIS-Compliant Device Files\n============================\nThe code also includes the CMSIS-compliant interface to the\nSTM32L053xx MCU files:\n\nstm32l0xx.h\nstm32l053xx.h\nsystem_stm32l0xx.h\nsystem_stm32l0xx.c\narm\\startup_stm32l053xx.s\ngnu\\startup_stm32l053xx.c\niar\\startup_stm32l053xx.s\n\n\nAdjusting the CPU Clock Speed\n=============================\nThe current setting is to run at 2MHz from the MSI (internal oscillator),\nbut the CPU clock speed can be modified by editing the file\nsystem_stm32l0xx.c. Ther file system_stm32l0xx.c.pll provides an example\nof clock setting using the PLL driven from the MSE.\n\n***\nNOTE:\nThe NUCLEO boards have a wide range of possible clock selections, depending\non the solder bridge configuration. Please see Chapter 5.7 \"OSC clock\" in\nthe STM32 NUCLEO Boards User Manual (ST document UM1724) for more information.\n***\n\n\n\n "
  },
  {
    "path": "3rd_party/nucleo-l053r8/arm/startup_stm32l053xx.s",
    "content": ";/***************************************************************************/\n; * @file     startup_stm32l053xx.s for ARM-KEIL ARM assembler\n; * @brief    CMSIS Cortex-M0+ Core Device Startup File for STM32L053xx\n; * @version  CMSIS 5.9.0\n; * @date     1 Feb 2023\n; *\n; * Modified by Quantum Leaps:\n; * - Added relocating of the Vector Table to free up the 256B region at 0x0\n; *   for NULL-pointer protection by the MPU.\n; * - Modified all exception handlers to branch to assert_failed()\n; *   instead of locking up the CPU inside an endless loop.\n; *\n; * @description\n; * Created from the CMSIS template for the specified device\n; * Quantum Leaps, www.state-machine.com\n; *\n; * @note\n; * The symbols Stack_Size and Heap_Size should be provided on the command-\n; * line options to the assembler, for example as:\n; *     --pd \"Stack_Size SETA 1024\" --pd \"Heap_Size SETA 0\"\n\n\n;******************************************************************************\n; Allocate space for the stack.\n;\n        AREA    STACK, NOINIT, READWRITE, ALIGN=3\n__stack_base\nStackMem\n        SPACE   Stack_Size    ; provided in command-line option, for example:\n                              ; --pd \"Stack_Size SETA 512\"\n__stack_limit\n__initial_sp\n\n;******************************************************************************\n; Allocate space for the heap.\n;\n        AREA    HEAP, NOINIT, READWRITE, ALIGN=3\n__heap_base\nHeapMem\n        SPACE   Heap_Size     ; provided in command-line option, for example:\n                              ; --pd \"Heap_Size SETA 0\"\n__heap_limit\n\n; Indicate that the code in this file preserves 8-byte alignment of the stack.\n        PRESERVE8\n\n;******************************************************************************\n; The vector table.\n;\n; Place code into the reset code section.\n        AREA   RESET, DATA, READONLY, ALIGN=8\n        EXPORT  __Vectors\n        EXPORT  __Vectors_End\n        EXPORT  __Vectors_Size\n\n__Vectors\n    ; Initial Vector Table before relocation\n        DCD     __initial_sp                ; Top of Stack\n        DCD     Reset_Handler               ; Reset Handler\n        DCD     NMI_Handler                 ; NMI Handler\n        DCD     HardFault_Handler           ; Hard Fault Handler\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     SVC_Handler                 ; SVCall handler\n        DCD     DebugMon_Handler            ; Debug Monitor handler\n        DCD     Default_Handler             ; Reserved\n        DCD     PendSV_Handler              ; PendSV handler\n        DCD     SysTick_Handler             ; SysTick handler\n\n        ; IRQ handlers...\n        DCD     WWDG_IRQHandler             ; [ 0] Window Watchdog\n        DCD     PVD_IRQHandler              ; [ 1] PVD through EXTI Line detect\n        DCD     RTC_IRQHandler              ; [ 2] RTC through EXTI Line\n        DCD     FLASH_IRQHandler            ; [ 3] FLASH\n        DCD     RCC_CRS_IRQHandler          ; [ 4] RCC and CRS\n        DCD     EXTI0_1_IRQHandler          ; [ 5] EXTI Line 0 and 1\n        DCD     EXTI2_3_IRQHandler          ; [ 6] EXTI Line 2 and 3\n        DCD     EXTI4_15_IRQHandler         ; [ 7] EXTI Line 4 to 15\n        DCD     TSC_IRQHandler              ; [ 8] TSC\n        DCD     DMA1_Channel1_IRQHandler    ; [ 9] DMA1 Channel 1\n        DCD     DMA1_Channel2_3_IRQHandler  ; [10] DMA1 Channel 2 and Channel 3\n        DCD     DMA1_Channel4_5_6_7_IRQHandler ; [11] DMA1 Channel 4, 5, 6 and 7\n        DCD     ADC1_COMP_IRQHandler        ; [12] ADC1, COMP1 and COMP2\n        DCD     LPTIM1_IRQHandler           ; [13] LPTIM1\n        DCD     Reserved14_IRQHandler       ; [14] Reserved\n        DCD     TIM2_IRQHandler             ; [15] TIM2\n        DCD     Reserved16_IRQHandler       ; [16] Reserved\n        DCD     TIM6_DAC_IRQHandler         ; [17] TIM6 and DAC\n        DCD     Reserved18_IRQHandler       ; [18] Reserved\n        DCD     Reserved19_IRQHandler       ; [19] Reserved\n        DCD     TIM21_IRQHandler            ; [20] TIM21\n        DCD     Reserved21_IRQHandler       ; [21] Reserved\n        DCD     TIM22_IRQHandler            ; [22] TIM22\n        DCD     I2C1_IRQHandler             ; [23] I2C1\n        DCD     I2C2_IRQHandler             ; [24] I2C2\n        DCD     SPI1_IRQHandler             ; [25] SPI1\n        DCD     SPI2_IRQHandler             ; [26] SPI2\n        DCD     USART1_IRQHandler           ; [27] USART1\n        DCD     USART2_IRQHandler           ; [28] USART2\n        DCD     RNG_LPUART1_IRQHandler      ; [29] RNG and LPUART1\n        DCD     LCD_IRQHandler              ; [30] LCD\n        DCD     USB_IRQHandler              ; [31] USB\n\n__Vectors_End\n\n__Vectors_Size  EQU   __Vectors_End - __Vectors\n\n\n;******************************************************************************\n; This is the code for exception handlers.\n;\n        AREA    |.text|, CODE, READONLY\n\n;******************************************************************************\n; This is the code that gets called when the processor first starts execution\n; following a reset event.\n;\nReset_Handler   PROC\n        EXPORT  Reset_Handler  [WEAK]\n        IMPORT  SystemInit\n        IMPORT  __main\n        IMPORT  assert_failed\n\n        LDR     r0,=SystemInit  ; CMSIS system initialization\n        BLX     r0\n\n        ; Call the C library enty point that handles startup. This will copy\n        ; the .data section initializers from flash to SRAM and zero fill the\n        ; .bss section.\n        ; NOTE: The __main function clears the C stack as well\n        LDR     r0,=__main\n        BX      r0\n\n        ; __main calls the main() function, which should not return,\n        ; but just in case jump to assert_failed() if main returns.\n        LDR     r0,=str_EXIT\n        MOVS    r1,#1\n        LDR     r2,=__initial_sp  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_EXIT\n        DCB     \"EXIT\"\n        ALIGN\n        ENDP\n\n;******************************************************************************\nNMI_Handler     PROC\n        EXPORT  NMI_Handler     [WEAK]\n        IMPORT  assert_failed\n        LDR     r0,=str_NMI\n        MOVS    r1,#1\n        LDR     r2,=__initial_sp  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_NMI\n        DCB     \"NMI\"\n        ALIGN\n        ENDP\n\n;******************************************************************************\nHardFault_Handler PROC\n        EXPORT  HardFault_Handler [WEAK]\n        IMPORT  assert_failed\n        LDR     r0,=str_HardFault\n        MOVS    r1,#1\n        LDR     r2,=__initial_sp  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_HardFault\n        DCB     \"HardFault\"\n        ALIGN\n        ENDP\n\n\n\n;******************************************************************************\n;\n; Weak non-fault handlers...\n;\n\n;******************************************************************************\nSVC_Handler PROC\n        EXPORT  SVC_Handler   [WEAK]\n        IMPORT  assert_failed\n        LDR     r0,=str_SVC\n        MOVS    r1,#1\n        LDR     r2,=__initial_sp  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_SVC\n        DCB     \"SVC\"\n        ALIGN\n        ENDP\n\n;******************************************************************************\nDebugMon_Handler PROC\n        EXPORT  DebugMon_Handler     [WEAK]\n        IMPORT  assert_failed\n        LDR     r0,=str_DebugMon\n        MOVS    r1,#1\n        LDR     r2,=__initial_sp  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_DebugMon\n        DCB     \"DebugMon\"\n        ALIGN\n        ENDP\n\n;******************************************************************************\nPendSV_Handler PROC\n        EXPORT  PendSV_Handler       [WEAK]\n        IMPORT  assert_failed\n        LDR     r0,=str_PendSV\n        MOVS    r1,#1\n        LDR     r2,=__initial_sp  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_PendSV\n        DCB     \"PendSV\"\n        ALIGN\n        ENDP\n\n;******************************************************************************\nSysTick_Handler PROC\n        EXPORT  SysTick_Handler     [WEAK]\n        IMPORT  assert_failed\n        LDR     r0,=str_SysTick\n        MOVS    r1,#1\n        LDR     r2,=__initial_sp  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_SysTick\n        DCB     \"SysTick\"\n        ALIGN\n        ENDP\n\n;******************************************************************************\nDefault_Handler PROC\n        EXPORT  WWDG_IRQHandler                [WEAK]\n        EXPORT  PVD_IRQHandler                 [WEAK]\n        EXPORT  RTC_IRQHandler                 [WEAK]\n        EXPORT  FLASH_IRQHandler               [WEAK]\n        EXPORT  RCC_CRS_IRQHandler             [WEAK]\n        EXPORT  EXTI0_1_IRQHandler             [WEAK]\n        EXPORT  EXTI2_3_IRQHandler             [WEAK]\n        EXPORT  EXTI4_15_IRQHandler            [WEAK]\n        EXPORT  TSC_IRQHandler                 [WEAK]\n        EXPORT  DMA1_Channel1_IRQHandler       [WEAK]\n        EXPORT  DMA1_Channel2_3_IRQHandler     [WEAK]\n        EXPORT  DMA1_Channel4_5_6_7_IRQHandler [WEAK]\n        EXPORT  ADC1_COMP_IRQHandler           [WEAK]\n        EXPORT  LPTIM1_IRQHandler              [WEAK]\n        EXPORT  TIM2_IRQHandler                [WEAK]\n        EXPORT  TIM6_DAC_IRQHandler            [WEAK]\n        EXPORT  TIM21_IRQHandler               [WEAK]\n        EXPORT  TIM22_IRQHandler               [WEAK]\n        EXPORT  I2C1_IRQHandler                [WEAK]\n        EXPORT  I2C2_IRQHandler                [WEAK]\n        EXPORT  SPI1_IRQHandler                [WEAK]\n        EXPORT  SPI2_IRQHandler                [WEAK]\n        EXPORT  USART1_IRQHandler              [WEAK]\n        EXPORT  USART2_IRQHandler              [WEAK]\n        EXPORT  RNG_LPUART1_IRQHandler         [WEAK]\n        EXPORT  LCD_IRQHandler                 [WEAK]\n        EXPORT  USB_IRQHandler                 [WEAK]\n        EXPORT  Reserved14_IRQHandler          [WEAK]\n        EXPORT  Reserved16_IRQHandler          [WEAK]\n        EXPORT  Reserved18_IRQHandler          [WEAK]\n        EXPORT  Reserved19_IRQHandler          [WEAK]\n        EXPORT  Reserved21_IRQHandler          [WEAK]\n\nWWDG_IRQHandler\nPVD_IRQHandler\nRTC_IRQHandler\nFLASH_IRQHandler\nRCC_CRS_IRQHandler\nEXTI0_1_IRQHandler\nEXTI2_3_IRQHandler\nEXTI4_15_IRQHandler\nTSC_IRQHandler\nDMA1_Channel1_IRQHandler\nDMA1_Channel2_3_IRQHandler\nDMA1_Channel4_5_6_7_IRQHandler\nADC1_COMP_IRQHandler\nLPTIM1_IRQHandler\nTIM2_IRQHandler\nTIM6_DAC_IRQHandler\nTIM21_IRQHandler\nTIM22_IRQHandler\nI2C1_IRQHandler\nI2C2_IRQHandler\nSPI1_IRQHandler\nSPI2_IRQHandler\nUSART1_IRQHandler\nUSART2_IRQHandler\nRNG_LPUART1_IRQHandler\nLCD_IRQHandler\nUSB_IRQHandler\nReserved14_IRQHandler\nReserved16_IRQHandler\nReserved18_IRQHandler\nReserved19_IRQHandler\nReserved21_IRQHandler\n        LDR     r0,=str_Undefined\n        MOVS    r1,#1\n        LDR     r2,=__initial_sp  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_Undefined\n        DCB     \"Undefined\"\n        ALIGN\n        ENDP\n\n        ALIGN               ; make sure the end of this section is aligned\n\n;******************************************************************************\n; The function expected of the C library startup code for defining the stack\n; and heap memory locations.  For the C library version of the startup code,\n; provide this function so that the C library initialization code can find out\n; the location of the stack and heap.\n;\n    IF :DEF: __MICROLIB\n        EXPORT  __initial_sp\n        EXPORT  __stack_limit\n        EXPORT  __heap_base\n        EXPORT  __heap_limit\n    ELSE\n        IMPORT  __use_two_region_memory\n        EXPORT  __user_initial_stackheap\n\n__user_initial_stackheap PROC\n        LDR     R0, =__heap_base\n        LDR     R1, =__stack_limit\n        LDR     R2, =__heap_limit\n        LDR     R3, =__stack_base\n        BX      LR\n        ENDP\n    ENDIF\n        ALIGN               ; make sure the end of this section is aligned\n\n    END                     ; end of module\n\n"
  },
  {
    "path": "3rd_party/nucleo-l053r8/gnu/nucleo-l053r8.ld",
    "content": "/*****************************************************************************\n* Linker script for for STM32L053R8, GNU-ARM linker\n*\n*                    Q u a n t u m  L e a P s\n*                    ------------------------\n*                    Modern Embedded Software\n*\n* Copyright (C) 2005 Quantum Leaps, LLC <state-machine.com>.\n*\n* SPDX-License-Identifier: GPL-3.0-or-later OR LicenseRef-QL-commercial\n*\n* This software is dual-licensed under the terms of the open source GNU\n* General Public License version 3 (or any later version), or alternatively,\n* under the terms of one of the closed source Quantum Leaps commercial\n* licenses.\n*\n* The terms of the open source GNU General Public License version 3\n* can be found at: <www.gnu.org/licenses/gpl-3.0>\n*\n* The terms of the closed source Quantum Leaps commercial licenses\n* can be found at: <www.state-machine.com/licensing>\n*\n* Redistributions in source code must retain this top-level comment block.\n* Plagiarizing this software to sidestep the license obligations is illegal.\n*\n* Contact information:\n* <www.state-machine.com/licensing>\n* <info@state-machine.com>\n*****************************************************************************/\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nENTRY(Reset_Handler) /* entry Point */\n\nMEMORY { /* memory map of STM32L053R8 */\n    ROM (rx)  : ORIGIN = 0x08000000, LENGTH = 64K\n    RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 8K\n}\n\n/* The size of the stack used by the application. NOTE: you need to adjust  */\nSTACK_SIZE = 2048;\n\n/* The size of the heap used by the application. NOTE: you need to adjust   */\nHEAP_SIZE = 0;\n\nSECTIONS {\n\n    .isr_vector : {        /* the vector table goes FIRST into ROM */\n        KEEP(*(.isr_vector)) /* vector table */\n        . = ALIGN(4);\n    } >ROM\n\n    .text : {              /* code and constants */\n        . = ALIGN(4);\n        *(.text)           /* .text sections (code) */\n        *(.text*)          /* .text* sections (code) */\n        *(.rodata)         /* .rodata sections (constants, strings, etc.) */\n        *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */\n\n        KEEP (*(.init))\n        KEEP (*(.fini))\n\n        . = ALIGN(4);\n    } >ROM\n\n    .preinit_array : {\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP (*(.preinit_array*))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n    } >ROM\n\n    .init_array : {\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array*))\n        PROVIDE_HIDDEN (__init_array_end = .);\n    } >ROM\n\n    .fini_array : {\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP (*(.fini_array*))\n        KEEP (*(SORT(.fini_array.*)))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n    } >ROM\n\n    _etext = .;            /* global symbols at end of code */\n\n    .stack : {\n        __stack_start__ = .;\n        . = . + STACK_SIZE;\n        . = ALIGN(4);\n        __stack_end__ = .;\n    } >RAM\n\n    .data :  AT (_etext) {\n        __data_load = LOADADDR (.data);\n        __data_start = .;\n        *(.data)           /* .data sections */\n        *(.data*)          /* .data* sections */\n        . = ALIGN(4);\n        __data_end__ = .;\n        _edata = __data_end__;\n    } >RAM\n\n    .bss : {\n        __bss_start__ = .;\n        *(.bss)\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = .;         /* define a global symbol at bss end */\n        __bss_end__ = .;\n    } >RAM\n\n    __exidx_start = .;\n    .ARM.exidx   : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } >RAM\n    __exidx_end = .;\n\n    PROVIDE ( end = _ebss );\n    PROVIDE ( _end = _ebss );\n    PROVIDE ( __end__ = _ebss );\n\n    .heap : {\n        __heap_start__ = .;\n        . = . + HEAP_SIZE;\n        . = ALIGN(4);\n        __heap_end__ = .;\n    } >RAM\n\n    /* Remove information from the standard libraries */\n    /DISCARD/ : {\n        libc.a ( * )\n        libm.a ( * )\n        libgcc.a ( * )\n    }\n}\n"
  },
  {
    "path": "3rd_party/nucleo-l053r8/gnu/startup_stm32l053xx.c",
    "content": "/* File: startup_stm32l053xx.c for GNU-ARM\n * Purpose: startup file for STM32L053xx Cortex-M0+ device.\n *          Should be used with GCC 'GNU Tools ARM Embedded'\n * Version: CMSIS 5.0.1\n * Date: 2017-09-13\n *\n * Modified by Quantum Leaps:\n * - Added relocating of the Vector Table to free up the 256B region at 0x0\n *   for NULL-pointer protection by the MPU.\n * - Modified all exception handlers to branch to assert_failed()\n *   instead of locking up the CPU inside an endless loop.\n *\n * Created from the CMSIS template for the specified device\n * Quantum Leaps, www.state-machine.com\n *\n * NOTE:\n * The function assert_failed defined at the end of this file defines\n * the error/assertion handling policy for the application and might\n * need to be customized for each project. This function is defined in\n * assembly to re-set the stack pointer, in case it is corrupted by the\n * time assert_failed is called.\n */\n\n/* start and end of stack defined in the linker script ---------------------*/\n/*extern int __stack_start__;*/\nextern int __stack_end__;\n\n/* Weak prototypes for error handlers --------------------------------------*/\n/**\n* \\note\n* The function assert_failed defined at the end of this file defines\n* the error/assertion handling policy for the application and might\n* need to be customized for each project. This function is defined in\n* assembly to avoid accessing the stack, which might be corrupted by\n* the time assert_failed is called.\n*/\n__attribute__ ((naked, noreturn))\nvoid assert_failed(char const *module, int loc);\n\n/* Function prototypes -----------------------------------------------------*/\nvoid Default_Handler(void);  /* Default empty handler */\nvoid Reset_Handler(void);    /* Reset Handler */\nvoid SystemInit(void);       /* CMSIS system initialization */\n\n/*----------------------------------------------------------------------------\n* weak aliases for each Exception handler to the Default_Handler.\n* Any function with the same name will override these definitions.\n*/\n/* Cortex-M Processor fault exceptions... */\nvoid NMI_Handler           (void) __attribute__ ((weak));\nvoid HardFault_Handler     (void) __attribute__ ((weak));\nvoid MemManage_Handler     (void) __attribute__ ((weak));\nvoid BusFault_Handler      (void) __attribute__ ((weak));\nvoid UsageFault_Handler    (void) __attribute__ ((weak));\n\n/* Cortex-M Processor non-fault exceptions... */\nvoid SVC_Handler           (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n/* external interrupts...   */\nvoid WWDG_IRQHandler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PVD_IRQHandler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid RTC_IRQHandler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid FLASH_IRQHandler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid RCC_CRS_IRQHandler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid EXTI0_1_IRQHandler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid EXTI2_3_IRQHandler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid EXTI4_15_IRQHandler   (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid TSC_IRQHandler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DMA1_Channel1_IRQHandler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DMA1_Channel2_3_IRQHandler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DMA1_Channel4_5_6_7_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid ADC1_COMP_IRQHandler  (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid LPTIM1_IRQHandler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid TIM2_IRQHandler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid TIM6_DAC_IRQHandler   (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid TIM21_IRQHandler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid TIM22_IRQHandler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid I2C1_IRQHandler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid I2C2_IRQHandler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SPI1_IRQHandler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SPI2_IRQHandler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid USART1_IRQHandler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid USART2_IRQHandler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid RNG_LPUART1_IRQHandler(void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid LCD_IRQHandler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid USB_IRQHandler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Reserved14_IRQHandler (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Reserved16_IRQHandler (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Reserved18_IRQHandler (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Reserved19_IRQHandler (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Reserved21_IRQHandler (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n/*..........................................................................*/\n__attribute__ ((section(\".isr_vector\")))\nint const g_pfnVectors[] = {\n    (int)&__stack_end__,          /* Top of Stack                   */\n    (int)&Reset_Handler,          /* Reset Handler                  */\n    (int)&NMI_Handler,            /* NMI Handler                    */\n    (int)&HardFault_Handler,      /* Hard Fault Handler             */\n    (int)&Default_Handler,        /* Reserved                       */\n    (int)&Default_Handler,        /* Reserved                       */\n    (int)&Default_Handler,        /* Reserved                       */\n    (int)&Default_Handler,        /* Reserved                       */\n    (int)&Default_Handler,        /* Reserved                       */\n    (int)&Default_Handler,        /* Reserved                       */\n    (int)&Default_Handler,        /* Reserved                       */\n    (int)&SVC_Handler,            /* SVCall handler                 */\n    (int)&DebugMon_Handler,       /* Debug monitor handler          */\n    (int)&Default_Handler,        /* Reserved                       */\n    (int)&PendSV_Handler,         /* The PendSV handler             */\n    (int)&SysTick_Handler,        /* The SysTick handler            */\n\n    /*IRQ handlers... */\n    (int)&WWDG_IRQHandler,        /* [ 0] Window Watchdog                */\n    (int)&PVD_IRQHandler,         /* [ 1] PVD through EXTI Line detect   */\n    (int)&RTC_IRQHandler,         /* [ 2] RTC through EXTI Line          */\n    (int)&FLASH_IRQHandler,       /* [ 3] FLASH                          */\n    (int)&RCC_CRS_IRQHandler,     /* [ 4] RCC and CRS                    */\n    (int)&EXTI0_1_IRQHandler,     /* [ 5] EXTI Line 0 and 1              */\n    (int)&EXTI2_3_IRQHandler,     /* [ 6] EXTI Line 2 and 3              */\n    (int)&EXTI4_15_IRQHandler,    /* [ 7] EXTI Line 4 to 15              */\n    (int)&TSC_IRQHandler,         /* [ 8] TSC                            */\n    (int)&DMA1_Channel1_IRQHandler,  /* [ 9] DMA1 Channel 1              */\n    (int)&DMA1_Channel2_3_IRQHandler,/* [10] DMA1 Channel 2 and Channel 3 */\n    (int)&DMA1_Channel4_5_6_7_IRQHandler, /* [11] DMA1 Channel 4, 5, 6 and 7   */\n    (int)&ADC1_COMP_IRQHandler,   /* [12] ADC1, COMP1 and COMP2          */\n    (int)&LPTIM1_IRQHandler,      /* [13] LPTIM1                         */\n    (int)&Reserved14_IRQHandler,  /* [14] Reserved                       */\n    (int)&TIM2_IRQHandler,        /* [15] TIM2                           */\n    (int)&Reserved16_IRQHandler,  /* [16] Reserved                       */\n    (int)&TIM6_DAC_IRQHandler,    /* [17] TIM6 and DAC                   */\n    (int)&Reserved18_IRQHandler,  /* [18] Reserved                       */\n    (int)&Reserved19_IRQHandler,  /* [19] Reserved                       */\n    (int)&TIM21_IRQHandler,       /* [20] TIM21                          */\n    (int)&Reserved21_IRQHandler,  /* [21] Reserved                       */\n    (int)&TIM22_IRQHandler,       /* [22] TIM22                          */\n    (int)&I2C1_IRQHandler,        /* [23] I2C1                           */\n    (int)&I2C2_IRQHandler,        /* [24] I2C2                           */\n    (int)&SPI1_IRQHandler,        /* [25] SPI1                           */\n    (int)&SPI2_IRQHandler,        /* [26] SPI2                           */\n    (int)&USART1_IRQHandler,      /* [27] USART1                         */\n    (int)&USART2_IRQHandler,      /* [28] USART2                         */\n    (int)&RNG_LPUART1_IRQHandler, /* [29] RNG and LPUART1                */\n    (int)&LCD_IRQHandler,         /* [30] LCD                            */\n    (int)&USB_IRQHandler,         /* [31] USB                            */\n};\n\n\n/* reset handler -----------------------------------------------------------*/\n__attribute__((naked)) void Reset_Handler(void);\nvoid Reset_Handler(void) {\n    extern int main(void);\n    extern int __libc_init_array(void);\n    extern unsigned __data_start;  /* start of .data in the linker script */\n    extern unsigned __data_end__;  /* end of .data in the linker script */\n    extern unsigned const __data_load; /* initialization values for .data  */\n    extern unsigned __bss_start__; /* start of .bss in the linker script */\n    extern unsigned __bss_end__;   /* end of .bss in the linker script */\n    extern void software_init_hook(void) __attribute__((weak));\n\n    SystemInit(); /* CMSIS system initialization */\n\n    /* copy the data segment initializers from flash to RAM... */\n    unsigned const *src = &__data_load;\n    unsigned *dst;\n    for (dst = &__data_start; dst < &__data_end__; ++dst, ++src) {\n        *dst = *src;\n    }\n\n    /* zero fill the .bss segment in RAM... */\n    for (dst = &__bss_start__; dst < &__bss_end__; ++dst) {\n        *dst = 0;\n    }\n\n    /* init hook provided? */\n    if (&software_init_hook != (void (*)(void))(0)) {\n        /* give control to the RTOS */\n        software_init_hook(); /* this will also call __libc_init_array */\n    }\n    else {\n        /* call all static constructors in C++ (harmless in C programs) */\n        __libc_init_array();\n        (void)main(); /* application's entry point; should never return! */\n    }\n\n    /* the previous code should not return, but assert just in case... */\n    assert_failed(\"Reset_Handler\", 1U);\n}\n\n\n/* fault exception handlers ------------------------------------------------*/\n__attribute__((naked)) void NMI_Handler(void);\nvoid NMI_Handler(void) {\n    /* reset the SP to the initial value in case of stack overflow */\n    __asm volatile (\"  MOV  sp,%0\" : : \"r\" (&__stack_end__));\n    assert_failed(\"NMI_Handler\", 1U);\n}\n/*..........................................................................*/\n__attribute__((naked)) void HardFault_Handler(void);\nvoid HardFault_Handler(void) {\n    /* reset the SP to the initial value in case of stack overflow */\n    __asm volatile (\"  MOV  sp,%0\" : : \"r\" (&__stack_end__));\n    assert_failed(\"HardFault_Handler\", 1U);\n}\n/*..........................................................................*/\n__attribute__((naked)) void Default_Handler(void);\nvoid Default_Handler(void) {\n    /* reset the SP to the initial value in case of stack overflow */\n    __asm volatile (\"  MOV  sp,%0\" : : \"r\" (&__stack_end__));\n    assert_failed(\"Default_Handler\", 1U);\n}\n"
  },
  {
    "path": "3rd_party/nucleo-l053r8/iar/startup_stm32l053xx.s",
    "content": ";/***************************************************************************/\n; * @file     startup_startup_stm32l053xx.s for IAR ARM assembler\n; * @brief    CMSIS Cortex-M0+ Core Device Startup File for STM32L053xx\n; * @version  CMSIS 5.9.0\n; * @date     1 Feb 2023\n; *\n; * Modified by Quantum Leaps:\n; * - Added relocating of the Vector Table to free up the 256B region at 0x0\n; *   for NULL-pointer protection by the MPU.\n; * - Modified all exception handlers to branch to assert_failed()\n; *   instead of locking up the CPU inside an endless loop.\n; *\n; * @description\n; * Created from the CMSIS template for the specified device\n; * Quantum Leaps, www.state-machine.com\n; *\n\n        MODULE  ?cstartup\n\n        ; Forward declaration of sections.\n        SECTION CSTACK:DATA:NOROOT(3)\n\n        SECTION .intvec:CODE:NOROOT(8)\n\n        PUBLIC  __vector_table\n        PUBLIC  __Vectors\n        PUBLIC  __Vectors_End\n        PUBLIC  __Vectors_Size\n\n;******************************************************************************\n; The vector table.\n;\n        DATA\n__vector_table\n    ; Initial Vector Table before relocation\n        DCD     sfe(CSTACK)\n        DCD     Reset_Handler               ; Reset Handler\n        DCD     NMI_Handler                 ; NMI Handler\n        DCD     HardFault_Handler           ; Hard Fault Handler\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     Default_Handler             ; Reserved\n        DCD     SVC_Handler                 ; SVCall handler\n        DCD     DebugMon_Handler            ; Debug Monitor handler\n        DCD     Default_Handler             ; Reserved\n        DCD     PendSV_Handler              ; PendSV handler\n        DCD     SysTick_Handler             ; SysTick handler\n\n        ; IRQ handlers...\n        DCD     WWDG_IRQHandler             ; [ 0] Window Watchdog\n        DCD     PVD_IRQHandler              ; [ 1] PVD through EXTI Line detect\n        DCD     RTC_IRQHandler              ; [ 2] RTC through EXTI Line\n        DCD     FLASH_IRQHandler            ; [ 3] FLASH\n        DCD     RCC_CRS_IRQHandler          ; [ 4] RCC and CRS\n        DCD     EXTI0_1_IRQHandler          ; [ 5] EXTI Line 0 and 1\n        DCD     EXTI2_3_IRQHandler          ; [ 6] EXTI Line 2 and 3\n        DCD     EXTI4_15_IRQHandler         ; [ 7] EXTI Line 4 to 15\n        DCD     TSC_IRQHandler              ; [ 8] TSC\n        DCD     DMA1_Channel1_IRQHandler    ; [ 9] DMA1 Channel 1\n        DCD     DMA1_Channel2_3_IRQHandler  ; [10] DMA1 Channel 2 and Channel 3\n        DCD     DMA1_Channel4_5_6_7_IRQHandler ; [11] DMA1 Channel 4, 5, 6 and 7\n        DCD     ADC1_COMP_IRQHandler        ; [12] ADC1, COMP1 and COMP2\n        DCD     LPTIM1_IRQHandler           ; [13] LPTIM1\n        DCD     Reserved14_IRQHandler       ; [14] Reserved\n        DCD     TIM2_IRQHandler             ; [15] TIM2\n        DCD     Reserved16_IRQHandler       ; [16] Reserved\n        DCD     TIM6_DAC_IRQHandler         ; [17] TIM6 and DAC\n        DCD     Reserved18_IRQHandler       ; [18] Reserved\n        DCD     Reserved19_IRQHandler       ; [19] Reserved\n        DCD     TIM21_IRQHandler            ; [20] TIM21\n        DCD     Reserved21_IRQHandler       ; [21] Reserved\n        DCD     TIM22_IRQHandler            ; [22] TIM22\n        DCD     I2C1_IRQHandler             ; [23] I2C1\n        DCD     I2C2_IRQHandler             ; [24] I2C2\n        DCD     SPI1_IRQHandler             ; [25] SPI1\n        DCD     SPI2_IRQHandler             ; [26] SPI2\n        DCD     USART1_IRQHandler           ; [27] USART1\n        DCD     USART2_IRQHandler           ; [28] USART2\n        DCD     RNG_LPUART1_IRQHandler      ; [29] RNG and LPUART1\n        DCD     LCD_IRQHandler              ; [30] LCD\n        DCD     USB_IRQHandler              ; [31] USB\n\n__Vectors_End\n\n__Vectors       EQU   __vector_table\n__Vectors_Size  EQU   __Vectors_End - __Vectors\n\n\n;******************************************************************************\n; This is the code for exception handlers.\n;\n        SECTION .text:CODE:REORDER:NOROOT(2)\n\n;******************************************************************************\n; This is the code that gets called when theessor first starts execution\n; following a reset event.\n;\n        PUBWEAK Reset_Handler\n        EXTERN  SystemInit\n        EXTERN  __iar_program_start\n        EXTERN  assert_failed\n\nReset_Handler\n        LDR     r0,=SystemInit  ; CMSIS system initialization\n        BLX     r0\n\n        ; pre-fill the CSTACK with 0xDEADBEEF...................\n        LDR     r0,=0xDEADBEEF\n        MOV     r1,r0\n        LDR     r2,=sfb(CSTACK)\n        LDR     r3,=sfe(CSTACK)\nReset_stackInit_fill:\n        STMIA   r2!,{r0,r1}\n        CMP     r2,r3\n        BLT.N   Reset_stackInit_fill\n\n        LDR     r0,=__iar_program_start ; IAR startup code\n        BLX     r0\n\n        ; __iar_program_start calls the main() function, which should not return,\n        ; but just in case jump to assert_failed() if main returns.\n        LDR     r0,=str_EXIT\n        MOVS    r1,#1\n        LDR     r2,=sfe(CSTACK)  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_EXIT\n        DCB     \"EXIT\"\n        ALIGNROM 2\n\n;******************************************************************************\n        PUBWEAK NMI_Handler\nNMI_Handler\n        LDR     r0,=str_NMI\n        MOVS    r1,#1\n        LDR     r2,=sfe(CSTACK)  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_NMI\n        DCB     \"NMI\"\n        ALIGNROM 2\n\n;******************************************************************************\n        PUBWEAK HardFault_Handler\nHardFault_Handler\n        LDR     r0,=str_HardFault\n        MOVS    r1,#1\n        LDR     r2,=sfe(CSTACK)  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_HardFault\n        DCB     \"HardFault\"\n        ALIGNROM 2\n\n\n;******************************************************************************\n;\n; Weak non-fault handlers...\n;\n\n;******************************************************************************\n        PUBWEAK SVC_Handler\nSVC_Handler\n        LDR     r0,=str_SVC\n        MOVS    r1,#1\n        LDR     r2,=sfe(CSTACK)  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_SVC\n        DCB     \"SVC\"\n        ALIGNROM 2\n\n;******************************************************************************\n        PUBWEAK DebugMon_Handler\nDebugMon_Handler\n        LDR     r0,=str_DebugMon\n        MOVS    r1,#1\n        LDR     r2,=sfe(CSTACK)  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_DebugMon\n        DCB     \"DebugMon\"\n        ALIGNROM 2\n\n;******************************************************************************\n        PUBWEAK PendSV_Handler\nPendSV_Handler\n        LDR     r0,=str_PendSV\n        MOVS    r1,#1\n        LDR     r2,=sfe(CSTACK)  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_PendSV\n        DCB     \"PendSV\"\n        ALIGNROM 2\n\n;******************************************************************************\n        PUBWEAK SysTick_Handler\nSysTick_Handler\n        LDR     r0,=str_SysTick\n        MOVS    r1,#1\n        LDR     r2,=sfe(CSTACK)  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_SysTick\n        DCB     \"SysTick\"\n        ALIGNROM 2\n\n;******************************************************************************\n; Weak IRQ handlers...\n;\n        PUBWEAK  Default_Handler\n        PUBWEAK  WWDG_IRQHandler\n        PUBWEAK  PVD_IRQHandler\n        PUBWEAK  RTC_IRQHandler\n        PUBWEAK  FLASH_IRQHandler\n        PUBWEAK  RCC_CRS_IRQHandler\n        PUBWEAK  EXTI0_1_IRQHandler\n        PUBWEAK  EXTI2_3_IRQHandler\n        PUBWEAK  EXTI4_15_IRQHandler\n        PUBWEAK  TSC_IRQHandler\n        PUBWEAK  DMA1_Channel1_IRQHandler\n        PUBWEAK  DMA1_Channel2_3_IRQHandler\n        PUBWEAK  DMA1_Channel4_5_6_7_IRQHandler\n        PUBWEAK  ADC1_COMP_IRQHandler\n        PUBWEAK  LPTIM1_IRQHandler\n        PUBWEAK  TIM2_IRQHandler\n        PUBWEAK  TIM6_DAC_IRQHandler\n        PUBWEAK  TIM21_IRQHandler\n        PUBWEAK  TIM22_IRQHandler\n        PUBWEAK  I2C1_IRQHandler\n        PUBWEAK  I2C2_IRQHandler\n        PUBWEAK  SPI1_IRQHandler\n        PUBWEAK  SPI2_IRQHandler\n        PUBWEAK  USART1_IRQHandler\n        PUBWEAK  USART2_IRQHandler\n        PUBWEAK  RNG_LPUART1_IRQHandler\n        PUBWEAK  LCD_IRQHandler\n        PUBWEAK  USB_IRQHandler\n        PUBWEAK  Reserved14_IRQHandler\n        PUBWEAK  Reserved16_IRQHandler\n        PUBWEAK  Reserved18_IRQHandler\n        PUBWEAK  Reserved19_IRQHandler\n        PUBWEAK  Reserved21_IRQHandler\n\nDefault_Handler\nWWDG_IRQHandler\nPVD_IRQHandler\nRTC_IRQHandler\nFLASH_IRQHandler\nRCC_CRS_IRQHandler\nEXTI0_1_IRQHandler\nEXTI2_3_IRQHandler\nEXTI4_15_IRQHandler\nTSC_IRQHandler\nDMA1_Channel1_IRQHandler\nDMA1_Channel2_3_IRQHandler\nDMA1_Channel4_5_6_7_IRQHandler\nADC1_COMP_IRQHandler\nLPTIM1_IRQHandler\nTIM2_IRQHandler\nTIM6_DAC_IRQHandler\nTIM21_IRQHandler\nTIM22_IRQHandler\nI2C1_IRQHandler\nI2C2_IRQHandler\nSPI1_IRQHandler\nSPI2_IRQHandler\nUSART1_IRQHandler\nUSART2_IRQHandler\nRNG_LPUART1_IRQHandler\nLCD_IRQHandler\nUSB_IRQHandler\nReserved14_IRQHandler\nReserved16_IRQHandler\nReserved18_IRQHandler\nReserved19_IRQHandler\nReserved21_IRQHandler\n        LDR     r0,=str_Undefined\n        MOVS    r1,#1\n        LDR     r2,=sfe(CSTACK)  ; re-set the SP in case of stack overflow\n        MOV     sp,r2\n        LDR     r2,=assert_failed\n        BX      r2\nstr_Undefined\n        DCB     \"Undefined\"\n        ALIGNROM 2\n\n        END                     ; end of module\n\n"
  },
  {
    "path": "3rd_party/nucleo-l053r8/stm32l053xx.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32l053xx.h\n  * @author  MCD Application Team\n  * @version V1.0.0RC1\n  * @date    15-April-2014\n  * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.\n  *          This file contains all the peripheral register's definitions, bits\n  *          definitions and memory mapping for STM32L0xx devices.\n  *\n  *          This file contains:\n  *           - Data structures and the address mapping for all peripherals\n  *           - Peripheral's registers declarations and bits definition\n  *           - Macros to access peripheral’s registers hardware\n  *\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/** @addtogroup CMSIS\n  * @{\n  */\n\n/** @addtogroup stm32l053xx\n  * @{\n  */\n\n#ifndef __STM32L053xx_H\n#define __STM32L053xx_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n\n/** @addtogroup Configuration_section_for_CMSIS\n  * @{\n  */\n/**\n  * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals\n  */\n#define __CM0PLUS_REV             0 /*!< Core Revision r0p0                            */\n#define __MPU_PRESENT             1 /*!< STM32L0xx  provides an MPU                    */\n#define __VTOR_PRESENT            1 /*!< Vector  Table  Register supported             */\n#define __NVIC_PRIO_BITS          2 /*!< STM32L0xx uses 2 Bits for the Priority Levels */\n#define __Vendor_SysTickConfig    0 /*!< Set to 1 if different SysTick Config is used  */\n\n\n/**\n  * @}\n  */\n\n/** @addtogroup Peripheral_interrupt_number_definition\n  * @{\n  */\n\n/**\n * @brief STM32L0xx Interrupt Number Definition, according to the selected device\n *        in @ref Library_configuration_section\n */\n\n/*!< Interrupt Number Definition */\ntypedef enum\n{\n/******  Cortex-M0 Processor Exceptions Numbers ******************************************************/\n  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */\n  HardFault_IRQn              = -13,    /*!< 3 Cortex-M0+ Hard Fault Interrupt                        */\n  SVC_IRQn                    = -5,     /*!< 11 Cortex-M0+ SV Call Interrupt                          */\n  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M0+ Pend SV Interrupt                          */\n  SysTick_IRQn                = -1,     /*!< 15 Cortex-M0+ System Tick Interrupt                      */\n\n/******  STM32L-0 specific Interrupt Numbers *********************************************************/\n  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                     */\n  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detect Interrupt                        */\n  RTC_IRQn                    = 2,      /*!< RTC through EXTI Line Interrupt                               */\n  FLASH_IRQn                  = 3,      /*!< FLASH Interrupt                                               */\n  RCC_CRS_IRQn                = 4,      /*!< RCC and CRS Interrupts                                        */\n  EXTI0_1_IRQn                = 5,      /*!< EXTI Line 0 and 1 Interrupts                                  */\n  EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupts                                  */\n  EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupts                                  */\n  TSC_IRQn                    = 8,      /*!< TSC Interrupt                                                  */\n  DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                      */\n  DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupts                       */\n  DMA1_Channel4_5_6_7_IRQn    = 11,     /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */\n  ADC1_COMP_IRQn              = 12,     /*!< ADC1, COMP1 and COMP2 Interrupts                              */\n  LPTIM1_IRQn                 = 13,     /*!< LPTIM1 Interrupt                                              */\n  TIM2_IRQn                   = 15,     /*!< TIM2 Interrupt                                                */\n  TIM6_DAC_IRQn               = 17,     /*!< TIM6 and DAC Interrupts                                       */\n  TIM21_IRQn                  = 20,     /*!< TIM21 Interrupt                                               */\n  TIM22_IRQn                  = 22,     /*!< TIM22 Interrupt                                               */\n  I2C1_IRQn                   = 23,     /*!< I2C1 Interrupt                                                */\n  I2C2_IRQn                   = 24,     /*!< I2C2 Interrupt                                                */\n  SPI1_IRQn                   = 25,     /*!< SPI1 Interrupt                                                */\n  SPI2_IRQn                   = 26,     /*!< SPI2 Interrupt                                                */\n  USART1_IRQn                 = 27,     /*!< USART1 Interrupt                                              */\n  USART2_IRQn                 = 28,     /*!< USART2 Interrupt                                              */\n  RNG_LPUART1_IRQn            = 29,     /*!< RNG and LPUART1 Interrupts                                    */\n  LCD_IRQn                    = 30,     /*!< LCD Interrupts                                                */\n  USB_IRQn                    = 31      /*!< USB global Interrupt                                          */\n} IRQn_Type;\n\n/*! Exception prototypes */\nvoid SVC_Handler(void);\nvoid PendSV_Handler(void);\nvoid SysTick_Handler(void);\n\n/*! IRQ prototypes */\nvoid WWDG_IRQHandler(void);\nvoid PVD_IRQHandler(void);\nvoid RTC_IRQHandler(void);\nvoid FLASH_IRQHandler(void);\nvoid RCC_CRS_IRQHandler(void);\nvoid EXTI0_1_IRQHandler(void);\nvoid EXTI2_3_IRQHandler(void);\nvoid EXTI4_15_IRQHandler(void);\nvoid TSC_IRQHandler(void);\nvoid DMA1_Channel1_IRQHandler(void);\nvoid DMA1_Channel2_3_IRQHandler(void);\nvoid DMA1_Channel4_5_6_7_IRQHandler(void);\nvoid ADC1_COMP_IRQHandler(void);\nvoid LPTIM1_IRQHandler(void);\nvoid TIM2_IRQHandler(void);\nvoid TIM6_DAC_IRQHandler(void);\nvoid TIM21_IRQHandler(void);\nvoid TIM22_IRQHandler(void);\nvoid I2C1_IRQHandler(void);\nvoid I2C2_IRQHandler(void);\nvoid SPI1_IRQHandler(void);\nvoid SPI2_IRQHandler(void);\nvoid USART1_IRQHandler(void);\nvoid USART2_IRQHandler(void);\nvoid RNG_LPUART1_IRQHandler(void);\nvoid LCD_IRQHandler(void);\nvoid USB_IRQHandler(void);\n\n/**\n  * @}\n  */\n\n#include \"core_cm0plus.h\"\n#include \"system_stm32l0xx.h\"\n#include <stdint.h>\n\n/** @addtogroup Peripheral_registers_structures\n  * @{\n  */\n\n/**\n  * @brief Analog to Digital Converter\n  */\n\ntypedef struct\n{\n  __IO uint32_t ISR;          /*!< ADC Interrupt and Status register,                          Address offset:0x00 */\n  __IO uint32_t IER;          /*!< ADC Interrupt Enable register,                              Address offset:0x04 */\n  __IO uint32_t CR;           /*!< ADC Control register,                                       Address offset:0x08 */\n  __IO uint32_t CFGR1;        /*!< ADC Configuration register 1,                               Address offset:0x0C */\n  __IO uint32_t CFGR2;        /*!< ADC Configuration register 2,                               Address offset:0x10 */\n  __IO uint32_t SMPR;         /*!< ADC Sampling time register,                                 Address offset:0x14 */\n  uint32_t   RESERVED1;       /*!< Reserved,                                                                  0x18 */\n  uint32_t   RESERVED2;       /*!< Reserved,                                                                  0x1C */\n  __IO uint32_t TR;           /*!< ADC watchdog threshold register,                            Address offset:0x20 */\n  uint32_t   RESERVED3;       /*!< Reserved,                                                                  0x24 */\n  __IO uint32_t CHSELR;       /*!< ADC channel selection register,                             Address offset:0x28 */\n  uint32_t   RESERVED4[5];    /*!< Reserved,                                                                  0x2C */\n  __IO uint32_t DR;           /*!< ADC data register,                                          Address offset:0x40 */\n  uint32_t   RESERVED5[28];    /*!< Reserved,                                                          0x44 - 0xB0 */\n  __IO uint32_t CALFACT;      /*!< ADC data register,                                          Address offset:0xB4 */\n} ADC_TypeDef;\n\ntypedef struct\n{\n  __IO uint32_t CCR;\n} ADC_Common_TypeDef;\n\n\n/**\n  * @brief Comparator\n  */\n\ntypedef struct\n{\n  __IO uint32_t CSR;     /*!< COMP comparator control and status register, Address offset: 0x18 */\n} COMP_TypeDef;\n\n\n/**\n  * @brief CRC calculation unit\n  */\n\ntypedef struct\n{\n  __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */\n  __IO uint8_t  IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */\n  uint8_t       RESERVED0;   /*!< Reserved,                                                    0x05 */\n  uint16_t      RESERVED1;   /*!< Reserved,                                                    0x06 */\n  __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */\n  uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */\n  __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */\n  __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */\n} CRC_TypeDef;\n\n/**\n  * @brief Clock Recovery System\n  */\ntypedef struct\n{\n__IO uint32_t CR;     /*!< CRS ccontrol register,              Address offset: 0x00 */\n__IO uint32_t CFGR;   /*!< CRS configuration register,         Address offset: 0x04 */\n__IO uint32_t ISR;    /*!< CRS interrupt and status register,  Address offset: 0x08 */\n__IO uint32_t ICR;    /*!< CRS interrupt flag clear register,  Address offset: 0x0C */\n} CRS_TypeDef;\n\n/**\n  * @brief Digital to Analog Converter\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;            /*!< DAC control register,                                    Address offset: 0x00 */\n  __IO uint32_t SWTRIGR;       /*!< DAC software trigger register,                           Address offset: 0x04 */\n  __IO uint32_t DHR12R1;       /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */\n  __IO uint32_t DHR12L1;       /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */\n  __IO uint32_t DHR8R1;        /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */\n  uint32_t      RESERVED0[6];  /*!<                                                                     0x14-0x28 */\n  __IO uint32_t DOR1;          /*!< DAC channel1 data output register,                       Address offset: 0x2C */\n  uint32_t      RESERVED1;     /*!<                                                                          0x30 */\n  __IO uint32_t SR;            /*!< DAC status register,                                     Address offset: 0x34 */\n} DAC_TypeDef;\n\n/**\n  * @brief Debug MCU\n  */\n\ntypedef struct\n{\n  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */\n  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */\n  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */\n  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */\n}DBGMCU_TypeDef;\n\n/**\n  * @brief DMA Controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t CCR;          /*!< DMA channel x configuration register                                           */\n  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register                                          */\n  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register                                      */\n  __IO uint32_t CMAR;         /*!< DMA channel x memory address register                                          */\n} DMA_Channel_TypeDef;\n\ntypedef struct\n{\n  __IO uint32_t ISR;          /*!< DMA interrupt status register,                            Address offset: 0x00 */\n  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,                        Address offset: 0x04 */\n} DMA_TypeDef;\n\ntypedef struct\n{\n  __IO uint32_t CSELR;           /*!< DMA channel selection register,                  Address offset: 0xA8 */\n} DMA_Request_TypeDef;\n\n/**\n  * @brief External Interrupt/Event Controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                             Address offset: 0x00 */\n  __IO uint32_t EMR;          /*!<EXTI Event mask register,                                 Address offset: 0x04 */\n  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,                  Address offset: 0x08 */\n  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,                  Address offset: 0x0C */\n  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,                   Address offset: 0x10 */\n  __IO uint32_t PR;           /*!<EXTI Pending register,                                    Address offset: 0x14 */\n}EXTI_TypeDef;\n\n/**\n  * @brief FLASH Registers\n  */\ntypedef struct\n{\n  __IO uint32_t ACR;          /*!< Access control register,                     Address offset: 0x00 */\n  __IO uint32_t PECR;         /*!< Program/erase control register,              Address offset: 0x04 */\n  __IO uint32_t PDKEYR;       /*!< Power down key register,                     Address offset: 0x08 */\n  __IO uint32_t PEKEYR;       /*!< Program/erase key register,                  Address offset: 0x0c */\n  __IO uint32_t PRGKEYR;      /*!< Program memory key register,                 Address offset: 0x10 */\n  __IO uint32_t OPTKEYR;      /*!< Option byte key register,                    Address offset: 0x14 */\n  __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x18 */\n  __IO uint32_t OBR;          /*!< Option byte register,                        Address offset: 0x1c */\n  __IO uint32_t WRPR;         /*!< Write protection register,                   Address offset: 0x20 */\n} FLASH_TypeDef;\n\n\n/**\n  * @brief Option Bytes Registers\n  */\ntypedef struct\n{\n  __IO uint32_t RDP;               /*!< Read protection register,               Address offset: 0x00 */\n  __IO uint32_t USER;              /*!< user register,                          Address offset: 0x04 */\n  __IO uint32_t WRP01;             /*!< write protection register 0 1,          Address offset: 0x08 */\n} OB_TypeDef;\n\n\n/**\n  * @brief General Purpose IO\n  */\n\ntypedef struct\n{\n  __IO uint32_t MODER;        /*!< GPIO port mode register,                                  Address offset: 0x00 */\n  __IO uint16_t OTYPER;       /*!< GPIO port output type register,                           Address offset: 0x04 */\n  uint16_t RESERVED0;         /*!< Reserved,                                                                 0x06 */\n  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,                          Address offset: 0x08 */\n  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,                     Address offset: 0x0C */\n  __IO uint16_t IDR;          /*!< GPIO port input data register,                            Address offset: 0x10 */\n  uint16_t RESERVED1;         /*!< Reserved,                                                                 0x12 */\n  __IO uint16_t ODR;          /*!< GPIO port output data register,                           Address offset: 0x14 */\n  uint16_t RESERVED2;         /*!< Reserved,                                                                 0x16 */\n  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,                     Address offset: 0x18 */\n  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,                    Address offset: 0x1C */\n  __IO uint32_t AFR[2];       /*!< GPIO alternate function register,                    Address offset: 0x20-0x24 */\n  __IO uint16_t BRR;          /*!< GPIO bit reset register,                                  Address offset: 0x28 */\n}GPIO_TypeDef;\n\n/**\n  * @brief LPTIMIMER\n  */\ntypedef struct\n{\n  __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,                Address offset: 0x00 */\n  __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,                     Address offset: 0x04 */\n  __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,                    Address offset: 0x08 */\n  __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                       Address offset: 0x0C */\n  __IO uint32_t CR;       /*!< LPTIM Control register,                             Address offset: 0x10 */\n  __IO uint32_t CMP;      /*!< LPTIM Compare register,                             Address offset: 0x14 */\n  __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                          Address offset: 0x18 */\n  __IO uint32_t CNT;      /*!< LPTIM Counter register,                             Address offset: 0x1C */\n} LPTIM_TypeDef;\n\n/**\n  * @brief SysTem Configuration\n  */\n\ntypedef struct\n{\n  __IO uint32_t CFGR1;         /*!< SYSCFG configuration register 1,                           Address offset: 0x00 */\n  __IO uint32_t CFGR2;         /*!< SYSCFG configuration register 2,                           Address offset: 0x04 */\n  __IO uint32_t EXTICR[4];     /*!< SYSCFG external interrupt configuration register,          Address offset: 0x14-0x08 */\n       uint32_t RESERVED[2];   /*!< Reserved,                                                  0x18-0x1C */\n  __IO uint32_t CFGR3;         /*!< SYSCFG configuration register 3,                           Address offset: 0x20 */\n} SYSCFG_TypeDef;\n\n\n\n/**\n  * @brief Inter-integrated Circuit Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */\n  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */\n  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */\n  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */\n  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */\n  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */\n  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */\n  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */\n  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */\n  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */\n  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */\n}I2C_TypeDef;\n\n\n/**\n  * @brief Independent WATCHDOG\n  */\ntypedef struct\n{\n  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */\n  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */\n  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */\n  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */\n  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */\n} IWDG_TypeDef;\n\n/**\n  * @brief LCD\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;        /*!< LCD control register,              Address offset: 0x00 */\n  __IO uint32_t FCR;       /*!< LCD frame control register,        Address offset: 0x04 */\n  __IO uint32_t SR;        /*!< LCD status register,               Address offset: 0x08 */\n  __IO uint32_t CLR;       /*!< LCD clear register,                Address offset: 0x0C */\n  uint32_t RESERVED;       /*!< Reserved,                          Address offset: 0x10 */\n  __IO uint32_t RAM[16];   /*!< LCD display memory,           Address offset: 0x14-0x50 */\n} LCD_TypeDef;\n\n/**\n  * @brief MIFARE Firewall\n  */\n\ntypedef struct\n{\n  __IO uint32_t CSSA;     /*!< Code Segment Start Address register,              Address offset: 0x00 */\n  __IO uint32_t CSL;      /*!< Code Segment Length register,                      Address offset: 0x04 */\n  __IO uint32_t NVDSSA;   /*!< NON volatile data Segment Start Address register,  Address offset: 0x08 */\n  __IO uint32_t NVDSL;    /*!< NON volatile data Segment Length register,         Address offset: 0x0C */\n  __IO uint32_t VDSSA ;   /*!< Volatile data Segment Start Address register,      Address offset: 0x10 */\n  __IO uint32_t VDSL ;    /*!< Volatile data Segment Length register,             Address offset: 0x14 */\n  __IO uint32_t LSSA ;    /*!< Library Segment Start Address register,            Address offset: 0x18 */\n  __IO uint32_t LSL ;     /*!< Library Segment Length register,                   Address offset: 0x1C */\n  __IO uint32_t CR ;      /*!< Configuration  register,                           Address offset: 0x20 */\n\n} FW_TypeDef;\n\n/**\n  * @brief Power Control\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */\n  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */\n} PWR_TypeDef;\n\n/**\n  * @brief Reset and Clock Control\n  */\ntypedef struct\n{\n  __IO uint32_t CR;            /*!< RCC clock control register,                                   Address offset: 0x00 */\n  __IO uint32_t ICSCR;         /*!< RCC Internal clock sources calibration register,              Address offset: 0x04 */\n  __IO uint32_t CRRCR;        /*!< RCC Clock recovery RC register,                               Address offset: 0x08 */\n  __IO uint32_t CFGR;          /*!< RCC Clock configuration register,                             Address offset: 0x0C */\n  __IO uint32_t CIER;          /*!< RCC Clock interrupt enable register,                          Address offset: 0x10 */\n  __IO uint32_t CIFR;          /*!< RCC Clock interrupt flag register,                            Address offset: 0x14 */\n  __IO uint32_t CICR;          /*!< RCC Clock interrupt clear register,                           Address offset: 0x18 */\n  __IO uint32_t IOPRSTR;       /*!< RCC IO port reset register,                                   Address offset: 0x1C */\n  __IO uint32_t AHBRSTR;       /*!< RCC AHB peripheral reset register,                            Address offset: 0x20 */\n  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                           Address offset: 0x24 */\n  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                           Address offset: 0x28 */\n  __IO uint32_t IOPENR;        /*!< RCC Clock IO port enable register,                            Address offset: 0x2C */\n  __IO uint32_t AHBENR;        /*!< RCC AHB peripheral clock enable register,                     Address offset: 0x30 */\n  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral enable register,                          Address offset: 0x34 */\n  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral enable register,                          Address offset: 0x38 */\n  __IO uint32_t IOPSMENR;      /*!< RCC IO port clock enable in sleep mode register,              Address offset: 0x3C */\n  __IO uint32_t AHBSMENR;      /*!< RCC AHB peripheral clock enable in sleep mode register,       Address offset: 0x40 */\n  __IO uint32_t APB2SMENR;     /*!< RCC APB2 peripheral clock enable in sleep mode register,      Address offset: 0x44 */\n  __IO uint32_t APB1SMENR;     /*!< RCC APB1 peripheral clock enable in sleep mode register,      Address offset: 0x48 */\n  __IO uint32_t CCIPR;         /*!< RCC clock configuration register,                             Address offset: 0x4C */\n  __IO uint32_t CSR;           /*!< RCC Control/status register,                                  Address offset: 0x50 */\n} RCC_TypeDef;\n\n\n/**\n  * @brief Random numbers generator\n  */\ntypedef struct\n{\n  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */\n  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */\n  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */\n} RNG_TypeDef;\n\n\n/**\n  * @brief Real-Time Clock\n  */\ntypedef struct\n{\n  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */\n  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */\n  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */\n  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */\n  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */\n  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */\n       uint32_t RESERVED;   /*!< Reserved,                                                  Address offset: 0x18 */\n  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */\n  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */\n  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */\n  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */\n  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */\n  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */\n  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */\n  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */\n  __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */\n  __IO uint32_t TAMPCR;     /*!< RTC tamper configuration register,                         Address offset: 0x40 */\n  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */\n  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */\n  __IO uint32_t OR;         /*!< RTC option register,                                       Address offset  0x4C */\n  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */\n  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */\n  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */\n  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */\n  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */\n} RTC_TypeDef;\n\n\n/**\n  * @brief Serial Peripheral Interface\n  */\n\ntypedef struct\n{\n  __IO uint16_t CR1;      /*!< SPI Control register 1 (not used in I2S mode),       Address offset: 0x00 */\n  uint16_t  RESERVED0;    /*!< Reserved, 0x02                                                            */\n  __IO uint16_t CR2;      /*!< SPI Control register 2,                              Address offset: 0x04 */\n  uint16_t  RESERVED1;    /*!< Reserved, 0x06                                                            */\n  __IO uint16_t SR;       /*!< SPI Status register,                                 Address offset: 0x08 */\n  uint16_t  RESERVED2;    /*!< Reserved, 0x0A                                                            */\n  __IO uint16_t DR;       /*!< SPI data register,                                   Address offset: 0x0C */\n  uint16_t  RESERVED3;    /*!< Reserved, 0x0E                                                            */\n  __IO uint16_t CRCPR;    /*!< SPI CRC polynomial register (not used in I2S mode),  Address offset: 0x10 */\n  uint16_t  RESERVED4;    /*!< Reserved, 0x12                                                            */\n  __IO uint16_t RXCRCR;   /*!< SPI Rx CRC register (not used in I2S mode),          Address offset: 0x14 */\n  uint16_t  RESERVED5;    /*!< Reserved, 0x16                                                            */\n  __IO uint16_t TXCRCR;   /*!< SPI Tx CRC register (not used in I2S mode),          Address offset: 0x18 */\n  uint16_t  RESERVED6;    /*!< Reserved, 0x1A                                                            */\n  __IO uint16_t I2SCFGR;  /*!< SPI_I2S configuration register,                      Address offset: 0x1C */\n  uint16_t  RESERVED7;    /*!< Reserved, 0x1E                                                            */\n  __IO uint16_t I2SPR;    /*!< SPI_I2S prescaler register,                          Address offset: 0x20 */\n  uint16_t  RESERVED8;    /*!< Reserved, 0x22                                                            */\n} SPI_TypeDef;\n\n/**\n  * @brief TIM\n  */\ntypedef struct\n{\n  __IO uint16_t CR1;             /*!< TIM control register 1,                      Address offset: 0x00 */\n  uint16_t      RESERVED0;       /*!< Reserved,                                                    0x02 */\n  __IO uint16_t CR2;             /*!< TIM control register 2,                      Address offset: 0x04 */\n  uint16_t      RESERVED1;       /*!< Reserved,                                                    0x06 */\n  __IO uint16_t SMCR;            /*!< TIM slave Mode Control register,             Address offset: 0x08 */\n  uint16_t      RESERVED2;       /*!< Reserved,                                                    0x0A */\n  __IO uint16_t DIER;            /*!< TIM DMA/interrupt enable register,           Address offset: 0x0C */\n  uint16_t      RESERVED3;       /*!< Reserved,                                                    0x0E */\n  __IO uint16_t SR;              /*!< TIM status register,                         Address offset: 0x10 */\n  uint16_t      RESERVED4;       /*!< Reserved,                                                    0x12 */\n  __IO uint16_t EGR;             /*!< TIM event generation register,               Address offset: 0x14 */\n  uint16_t      RESERVED5;       /*!< Reserved,                                                    0x16 */\n  __IO uint16_t CCMR1;           /*!< TIM  capture/compare mode register 1,        Address offset: 0x18 */\n  uint16_t      RESERVED6;       /*!< Reserved,                                                    0x1A */\n  __IO uint16_t CCMR2;           /*!< TIM  capture/compare mode register 2,        Address offset: 0x1C */\n  uint16_t      RESERVED7;       /*!< Reserved,                                                    0x1E */\n  __IO uint16_t CCER;            /*!< TIM capture/compare enable register,         Address offset: 0x20 */\n  uint16_t      RESERVED8;       /*!< Reserved,                                                    0x22 */\n  __IO uint32_t CNT;             /*!< TIM counter register,                        Address offset: 0x24 */\n  __IO uint16_t PSC;             /*!< TIM prescaler register,                      Address offset: 0x28 */\n  uint16_t      RESERVED10;      /*!< Reserved,                                                    0x2A */\n  __IO uint32_t ARR;             /*!< TIM auto-reload register,                    Address offset: 0x2C */\n  __IO uint16_t RCR;             /*!< TIM  repetition counter register,            Address offset: 0x30 */\n  uint16_t      RESERVED12;      /*!< Reserved,                                                    0x32 */\n  __IO uint32_t CCR1;            /*!< TIM capture/compare register 1,              Address offset: 0x34 */\n  __IO uint32_t CCR2;            /*!< TIM capture/compare register 2,              Address offset: 0x38 */\n  __IO uint32_t CCR3;            /*!< TIM capture/compare register 3,              Address offset: 0x3C */\n  __IO uint32_t CCR4;            /*!< TIM capture/compare register 4,              Address offset: 0x40 */\n  __IO uint16_t BDTR;            /*!< TIM break and dead-time register,            Address offset: 0x44 */\n  uint16_t      RESERVED17;      /*!< Reserved,                                                    0x26 */\n  __IO uint16_t DCR;             /*!< TIM DMA control register,                    Address offset: 0x48 */\n  uint16_t      RESERVED18;      /*!< Reserved,                                                    0x4A */\n  __IO uint16_t DMAR;            /*!< TIM DMA address for full transfer register,  Address offset: 0x4C */\n  uint16_t      RESERVED19;      /*!< Reserved,                                                    0x4E */\n  __IO uint16_t OR;              /*!< TIM option register,                         Address offset: 0x50 */\n  uint16_t      RESERVED20;      /*!< Reserved,                                                    0x52 */\n} TIM_TypeDef;\n\n/**\n  * @brief Touch Sensing Controller (TSC)\n  */\ntypedef struct\n{\n  __IO uint32_t CR;            /*!< TSC control register,                                     Address offset: 0x00 */\n  __IO uint32_t IER;           /*!< TSC interrupt enable register,                            Address offset: 0x04 */\n  __IO uint32_t ICR;           /*!< TSC interrupt clear register,                             Address offset: 0x08 */\n  __IO uint32_t ISR;           /*!< TSC interrupt status register,                            Address offset: 0x0C */\n  __IO uint32_t IOHCR;         /*!< TSC I/O hysteresis control register,                      Address offset: 0x10 */\n  uint32_t      RESERVED1;     /*!< Reserved,                                                 Address offset: 0x14 */\n  __IO uint32_t IOASCR;        /*!< TSC I/O analog switch control register,                   Address offset: 0x18 */\n  uint32_t      RESERVED2;     /*!< Reserved,                                                 Address offset: 0x1C */\n  __IO uint32_t IOSCR;         /*!< TSC I/O sampling control register,                        Address offset: 0x20 */\n  uint32_t      RESERVED3;     /*!< Reserved,                                                 Address offset: 0x24 */\n  __IO uint32_t IOCCR;         /*!< TSC I/O channel control register,                         Address offset: 0x28 */\n  uint32_t      RESERVED4;     /*!< Reserved,                                                 Address offset: 0x2C */\n  __IO uint32_t IOGCSR;        /*!< TSC I/O group control status register,                    Address offset: 0x30 */\n  __IO uint32_t IOGXCR[8];     /*!< TSC I/O group x counter register,                         Address offset: 0x34-50 */\n} TSC_TypeDef;\n\n/**\n  * @brief Universal Synchronous Asynchronous Receiver Transmitter\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */\n  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */\n  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */\n  __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */\n  __IO uint16_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */\n  uint16_t  RESERVED2;  /*!< Reserved, 0x12                                                 */\n  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */\n  __IO uint16_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */\n  uint16_t  RESERVED3;  /*!< Reserved, 0x1A                                                 */\n  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */\n  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */\n  __IO uint16_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */\n  uint16_t  RESERVED4;  /*!< Reserved, 0x26                                                 */\n  __IO uint16_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */\n  uint16_t  RESERVED5;  /*!< Reserved, 0x2A                                                 */\n} USART_TypeDef;\n\n/**\n  * @brief Window WATCHDOG\n  */\ntypedef struct\n{\n  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */\n  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */\n  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */\n} WWDG_TypeDef;\n\n/**\n  * @brief Universal Serial Bus Full Speed Device\n  */\n\ntypedef struct\n{\n  __IO uint16_t EP0R;            /*!< USB Endpoint 0 register,                Address offset: 0x00 */\n  __IO uint16_t RESERVED0;       /*!< Reserved */\n  __IO uint16_t EP1R;            /*!< USB Endpoint 1 register,                Address offset: 0x04 */\n  __IO uint16_t RESERVED1;       /*!< Reserved */\n  __IO uint16_t EP2R;            /*!< USB Endpoint 2 register,                Address offset: 0x08 */\n  __IO uint16_t RESERVED2;       /*!< Reserved */\n  __IO uint16_t EP3R;            /*!< USB Endpoint 3 register,                Address offset: 0x0C */\n  __IO uint16_t RESERVED3;       /*!< Reserved */\n  __IO uint16_t EP4R;            /*!< USB Endpoint 4 register,                Address offset: 0x10 */\n  __IO uint16_t RESERVED4;       /*!< Reserved */\n  __IO uint16_t EP5R;            /*!< USB Endpoint 5 register,                Address offset: 0x14 */\n  __IO uint16_t RESERVED5;       /*!< Reserved */\n  __IO uint16_t EP6R;            /*!< USB Endpoint 6 register,                Address offset: 0x18 */\n  __IO uint16_t RESERVED6;       /*!< Reserved */\n  __IO uint16_t EP7R;            /*!< USB Endpoint 7 register,                Address offset: 0x1C */\n  __IO uint16_t RESERVED7[17];   /*!< Reserved */\n  __IO uint16_t CNTR;            /*!< Control register,                       Address offset: 0x40 */\n  __IO uint16_t RESERVED8;       /*!< Reserved */\n  __IO uint16_t ISTR;            /*!< Interrupt status register,              Address offset: 0x44 */\n  __IO uint16_t RESERVED9;       /*!< Reserved */\n  __IO uint16_t FNR;             /*!< Frame number register,                  Address offset: 0x48 */\n  __IO uint16_t RESERVEDA;       /*!< Reserved */\n  __IO uint16_t DADDR;           /*!< Device address register,                Address offset: 0x4C */\n  __IO uint16_t RESERVEDB;       /*!< Reserved */\n  __IO uint16_t BTABLE;          /*!< Buffer Table address register,          Address offset: 0x50 */\n  __IO uint16_t RESERVEDC;       /*!< Reserved */\n  __IO uint16_t LPMCSR;          /*!< LPM Control and Status register,        Address offset: 0x54 */\n  __IO uint16_t RESERVEDD;       /*!< Reserved */\n  __IO uint16_t BCDR;            /*!< Battery Charging detector register,     Address offset: 0x58 */\n  __IO uint16_t RESERVEDE;       /*!< Reserved */\n} USB_TypeDef;\n\n\n/**\n  * @}\n  */\n\n/** @addtogroup Peripheral_memory_map\n  * @{\n  */\n\n#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */\n#define SRAM_BASE             ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */\n#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */\n\n/*!< Peripheral memory map */\n#define APBPERIPH_BASE        PERIPH_BASE\n#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000)\n#define IOPPERIPH_BASE       (PERIPH_BASE + 0x10000000)\n\n#define TIM2_BASE             (APBPERIPH_BASE + 0x00000000)\n#define TIM6_BASE             (APBPERIPH_BASE + 0x00001000)\n#define LCD_BASE              (APBPERIPH_BASE + 0x00002400)\n#define RTC_BASE              (APBPERIPH_BASE + 0x00002800)\n#define WWDG_BASE             (APBPERIPH_BASE + 0x00002C00)\n#define IWDG_BASE             (APBPERIPH_BASE + 0x00003000)\n#define SPI2_BASE             (APBPERIPH_BASE + 0x00003800)\n#define USART2_BASE           (APBPERIPH_BASE + 0x00004400)\n#define LPUART1_BASE          (APBPERIPH_BASE + 0x00004800)\n#define I2C1_BASE             (APBPERIPH_BASE + 0x00005400)\n#define I2C2_BASE             (APBPERIPH_BASE + 0x00005800)\n#define CRS_BASE              (APBPERIPH_BASE + 0x00006C00)\n#define PWR_BASE              (APBPERIPH_BASE + 0x00007000)\n#define DAC_BASE              (APBPERIPH_BASE + 0x00007400)\n#define LPTIM1_BASE           (APBPERIPH_BASE + 0x00007C00)\n\n#define SYSCFG_BASE           (APBPERIPH_BASE + 0x00010000)\n#define COMP1_BASE            (APBPERIPH_BASE + 0x00010018)\n#define COMP2_BASE            (APBPERIPH_BASE + 0x0001001C)\n#define EXTI_BASE             (APBPERIPH_BASE + 0x00010400)\n#define TIM21_BASE            (APBPERIPH_BASE + 0x00010800)\n#define TIM22_BASE            (APBPERIPH_BASE + 0x00011400)\n#define FW_BASE         (APBPERIPH_BASE + 0x00011C00)\n#define ADC1_BASE             (APBPERIPH_BASE + 0x00012400)\n#define ADC_BASE              (APBPERIPH_BASE + 0x00012708)\n#define SPI1_BASE             (APBPERIPH_BASE + 0x00013000)\n#define USART1_BASE           (APBPERIPH_BASE + 0x00013800)\n#define DBGMCU_BASE           (APBPERIPH_BASE + 0x00015800)\n\n#define DMA1_BASE             (AHBPERIPH_BASE + 0x00000000)\n#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008)\n#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001C)\n#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030)\n#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044)\n#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058)\n#define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006C)\n#define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080)\n#define DMA1_CSELR_BASE       (DMA1_BASE + 0x000000A8)\n\n\n#define RCC_BASE              (AHBPERIPH_BASE + 0x00001000)\n#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */\n#define OB_BASE               ((uint32_t)0x1FF80000)        /*!< FLASH Option Bytes base address */\n#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000)\n#define TSC_BASE              (AHBPERIPH_BASE + 0x00004000)\n#define RNG_BASE              (AHBPERIPH_BASE + 0x00005000)\n\n#define GPIOA_BASE            (IOPPERIPH_BASE + 0x00000000)\n#define GPIOB_BASE            (IOPPERIPH_BASE + 0x00000400)\n#define GPIOC_BASE            (IOPPERIPH_BASE + 0x00000800)\n#define GPIOD_BASE            (IOPPERIPH_BASE + 0x00000C00)\n#define GPIOH_BASE            (IOPPERIPH_BASE + 0x00001C00)\n\n/**\n  * @}\n  */\n\n/** @addtogroup Peripheral_declaration\n  * @{\n  */\n\n#define TIM2                ((TIM_TypeDef *) TIM2_BASE)\n#define TIM6                ((TIM_TypeDef *) TIM6_BASE)\n#define RTC                 ((RTC_TypeDef *) RTC_BASE)\n#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)\n#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)\n#define SPI2                ((SPI_TypeDef *) SPI2_BASE)\n#define USART2              ((USART_TypeDef *) USART2_BASE)\n#define LPUART1             ((USART_TypeDef *) LPUART1_BASE)\n#define I2C1                ((I2C_TypeDef *) I2C1_BASE)\n#define I2C2                ((I2C_TypeDef *) I2C2_BASE)\n#define CRS                 ((CRS_TypeDef *) CRS_BASE)\n#define PWR                 ((PWR_TypeDef *) PWR_BASE)\n#define DAC                 ((DAC_TypeDef *) DAC_BASE)\n#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)\n#define LCD                 ((LCD_TypeDef *) LCD_BASE)\n\n#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)\n#define COMP1               ((COMP_TypeDef *) COMP1_BASE)\n#define COMP2               ((COMP_TypeDef *) COMP2_BASE)\n#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)\n#define TIM21                ((TIM_TypeDef *) TIM21_BASE)\n#define TIM22               ((TIM_TypeDef *) TIM22_BASE)\n#define FW                ((FW_TypeDef *) FW_BASE)\n#define ADC1                ((ADC_TypeDef *) ADC1_BASE)\n#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)\n#define SPI1                ((SPI_TypeDef *) SPI1_BASE)\n#define USART1              ((USART_TypeDef *) USART1_BASE)\n#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)\n\n#define DMA1                ((DMA_TypeDef *) DMA1_BASE)\n#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)\n#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)\n#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)\n#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)\n#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)\n#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)\n#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)\n#define DMA1_CSELR          ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)\n\n\n#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)\n#define OB                  ((OB_TypeDef *) OB_BASE)\n#define RCC                 ((RCC_TypeDef *) RCC_BASE)\n#define CRC                 ((CRC_TypeDef *) CRC_BASE)\n#define TSC                 ((TSC_TypeDef *) TSC_BASE)\n#define RNG                 ((RNG_TypeDef *) RNG_BASE)\n\n#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)\n#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)\n#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)\n#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)\n#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)\n\n#define USB              ((USB_TypeDef *) USB_BASE)\n\n/**\n  * @}\n  */\n\n/** @addtogroup Exported_constants\n  * @{\n  */\n\n  /** @addtogroup Peripheral_Registers_Bits_Definition\n  * @{\n  */\n\n/******************************************************************************/\n/*                         Peripheral Registers Bits Definition               */\n/******************************************************************************/\n/******************************************************************************/\n/*                                                                            */\n/*                      Analog to Digital Converter (ADC)                     */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bits definition for ADC_ISR register  ******************/\n#define ADC_ISR_EOCAL                        ((uint32_t)0x00000800)        /*!< End of calibration flag */\n#define ADC_ISR_AWD                          ((uint32_t)0x00000080)        /*!< Analog watchdog flag */\n#define ADC_ISR_OVR                          ((uint32_t)0x00000010)        /*!< Overrun flag */\n#define ADC_ISR_EOSEQ                        ((uint32_t)0x00000008)        /*!< End of Sequence flag */\n#define ADC_ISR_EOC                          ((uint32_t)0x00000004)        /*!< End of Conversion */\n#define ADC_ISR_EOSMP                        ((uint32_t)0x00000002)        /*!< End of sampling flag */\n#define ADC_ISR_ADRDY                        ((uint32_t)0x00000001)        /*!< ADC Ready */\n\n/* Old EOSEQ bit definition, maintained for legacy purpose */\n#define ADC_ISR_EOS                          ADC_ISR_EOSEQ\n\n/********************  Bits definition for ADC_IER register  ******************/\n#define ADC_IER_EOCALIE                      ((uint32_t)0x00000800)        /*!< Enf Of Calibration interrupt enable */\n#define ADC_IER_AWDIE                        ((uint32_t)0x00000080)        /*!< Analog Watchdog interrupt enable */\n#define ADC_IER_OVRIE                        ((uint32_t)0x00000010)        /*!< Overrun interrupt enable */\n#define ADC_IER_EOSEQIE                      ((uint32_t)0x00000008)        /*!< End of Sequence of conversion interrupt enable */\n#define ADC_IER_EOCIE                        ((uint32_t)0x00000004)        /*!< End of Conversion interrupt enable */\n#define ADC_IER_EOSMPIE                      ((uint32_t)0x00000002)        /*!< End of sampling interrupt enable */\n#define ADC_IER_ADRDYIE                      ((uint32_t)0x00000001)        /*!< ADC Ready interrupt enable */\n\n/* Old EOSEQIE bit definition, maintained for legacy purpose */\n#define ADC_IER_EOSIE                        ADC_IER_EOSEQIE\n\n/********************  Bits definition for ADC_CR register  *******************/\n#define ADC_CR_ADCAL                         ((uint32_t)0x80000000)        /*!< ADC calibration */\n#define ADC_CR_ADVREGEN                      ((uint32_t)0x10000000)        /*!< ADC Voltage Regulator Enable */\n#define ADC_CR_ADSTP                         ((uint32_t)0x00000010)        /*!< ADC stop of conversion command */\n#define ADC_CR_ADSTART                       ((uint32_t)0x00000004)        /*!< ADC start of conversion */\n#define ADC_CR_ADDIS                         ((uint32_t)0x00000002)        /*!< ADC disable command */\n#define ADC_CR_ADEN                          ((uint32_t)0x00000001)        /*!< ADC enable control */ /*####   TBV  */\n\n/*******************  Bits definition for ADC_CFGR1 register  *****************/\n#define  ADC_CFGR1_AWDCH                      ((uint32_t)0x7C000000)       /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */\n#define  ADC_CFGR1_AWDCH_0                    ((uint32_t)0x04000000)       /*!< Bit 0 */\n#define  ADC_CFGR1_AWDCH_1                    ((uint32_t)0x08000000)       /*!< Bit 1 */\n#define  ADC_CFGR1_AWDCH_2                    ((uint32_t)0x10000000)       /*!< Bit 2 */\n#define  ADC_CFGR1_AWDCH_3                    ((uint32_t)0x20000000)       /*!< Bit 3 */\n#define  ADC_CFGR1_AWDCH_4                    ((uint32_t)0x40000000)       /*!< Bit 4 */\n#define  ADC_CFGR1_AWDEN                      ((uint32_t)0x00800000)       /*!< Analog watchdog enable on regular channels */\n#define  ADC_CFGR1_AWDSGL                     ((uint32_t)0x00400000)       /*!< Enable the watchdog on a single channel or on all channels  */\n#define  ADC_CFGR1_DISCEN                     ((uint32_t)0x00010000)       /*!< Discontinuous mode on regular channels */\n#define  ADC_CFGR1_AUTOFF                     ((uint32_t)0x00008000)       /*!< ADC auto power off */\n#define  ADC_CFGR1_WAIT                       ((uint32_t)0x00004000)       /*!< ADC wait conversion mode */\n#define  ADC_CFGR1_CONT                       ((uint32_t)0x00002000)       /*!< Continuous Conversion */\n#define  ADC_CFGR1_OVRMOD                     ((uint32_t)0x00001000)       /*!< Overrun mode */\n#define  ADC_CFGR1_EXTEN                      ((uint32_t)0x00000C00)       /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */\n#define  ADC_CFGR1_EXTEN_0                    ((uint32_t)0x00000400)       /*!< Bit 0 */\n#define  ADC_CFGR1_EXTEN_1                    ((uint32_t)0x00000800)       /*!< Bit 1 */\n#define  ADC_CFGR1_EXTSEL                     ((uint32_t)0x000001C0)       /*!< EXTSEL[2:0] bits (External Event Select for regular group) */\n#define  ADC_CFGR1_EXTSEL_0                   ((uint32_t)0x00000040)       /*!< Bit 0 */\n#define  ADC_CFGR1_EXTSEL_1                   ((uint32_t)0x00000080)       /*!< Bit 1 */\n#define  ADC_CFGR1_EXTSEL_2                   ((uint32_t)0x00000100)       /*!< Bit 2 */\n#define  ADC_CFGR1_ALIGN                      ((uint32_t)0x00000020)       /*!< Data Alignment */\n#define  ADC_CFGR1_RES                        ((uint32_t)0x00000018)       /*!< RES[1:0] bits (Resolution) */\n#define  ADC_CFGR1_RES_0                      ((uint32_t)0x00000008)       /*!< Bit 0 */\n#define  ADC_CFGR1_RES_1                      ((uint32_t)0x00000010)       /*!< Bit 1 */\n#define  ADC_CFGR1_SCANDIR                    ((uint32_t)0x00000004)       /*!< Sequence scan direction */\n#define  ADC_CFGR1_DMACFG                     ((uint32_t)0x00000002)       /*!< Direct memory access configuration */\n#define  ADC_CFGR1_DMAEN                      ((uint32_t)0x00000001)       /*!< Direct memory access enable */\n\n/* Old WAIT bit definition, maintained for legacy purpose */\n#define  ADC_CFGR1_AUTDLY                     ADC_CFGR1_WAIT\n\n/*******************  Bits definition for ADC_CFGR2 register  *****************/\n#define  ADC_CFGR2_TOVS                       ((uint32_t)0x80000200)        /*!< Triggered Oversampling */\n#define  ADC_CFGR2_OVSS                       ((uint32_t)0x000001E0)        /*!< OVSS [3:0] bits (Oversampling shift) */\n#define  ADC_CFGR2_OVSS_0                     ((uint32_t)0x00000020)        /*!< Bit 0 */\n#define  ADC_CFGR2_OVSS_1                     ((uint32_t)0x00000040)        /*!< Bit 1 */\n#define  ADC_CFGR2_OVSS_2                     ((uint32_t)0x00000080)        /*!< Bit 2 */\n#define  ADC_CFGR2_OVSS_3                     ((uint32_t)0x00000100)        /*!< Bit 3 */\n#define  ADC_CFGR2_OVSR                       ((uint32_t)0x0000001C)        /*!< OVSR  [2:0] bits (Oversampling ratio) */\n#define  ADC_CFGR2_OVSR_0                     ((uint32_t)0x00000004)        /*!< Bit 0 */\n#define  ADC_CFGR2_OVSR_1                     ((uint32_t)0x00000008)        /*!< Bit 1 */\n#define  ADC_CFGR2_OVSR_2                     ((uint32_t)0x00000010)        /*!< Bit 2 */\n#define  ADC_CFGR2_OVSE                       ((uint32_t)0x00000001)        /*!< Oversampler Enable */\n#define  ADC_CFGR2_CKMODE                     ((uint32_t)0xC0000000)        /*!< CKMODE [1:0] bits (ADC clock mode) */\n#define  ADC_CFGR2_CKMODE_0                   ((uint32_t)0x40000000)        /*!< Bit 0 */\n#define  ADC_CFGR2_CKMODE_1                   ((uint32_t)0x80000000)        /*!< Bit 1 */\n\n\n/******************  Bit definition for ADC_SMPR register  ********************/\n#define  ADC_SMPR_SMPR                      ((uint32_t)0x00000007)        /*!< SMPR[2:0] bits (Sampling time selection) */\n#define  ADC_SMPR_SMPR_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */\n#define  ADC_SMPR_SMPR_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */\n#define  ADC_SMPR_SMPR_2                    ((uint32_t)0x00000004)        /*!< Bit 2 */\n\n/*******************  Bit definition for ADC_TR register  ********************/\n#define  ADC_TR_HT                          ((uint32_t)0x0FFF0000)        /*!< Analog watchdog high threshold */\n#define  ADC_TR_LT                          ((uint32_t)0x00000FFF)        /*!< Analog watchdog low threshold */\n\n/******************  Bit definition for ADC_CHSELR register  ******************/\n#define  ADC_CHSELR_CHSEL18                   ((uint32_t)0x00040000)        /*!< Channel 18 selection */\n#define  ADC_CHSELR_CHSEL17                   ((uint32_t)0x00020000)        /*!< Channel 17 selection */\n#define  ADC_CHSELR_CHSEL16                   ((uint32_t)0x00010000)        /*!< Channel 16 selection */\n#define  ADC_CHSELR_CHSEL15                   ((uint32_t)0x00008000)        /*!< Channel 15 selection */\n#define  ADC_CHSELR_CHSEL14                   ((uint32_t)0x00004000)        /*!< Channel 14 selection */\n#define  ADC_CHSELR_CHSEL13                   ((uint32_t)0x00002000)        /*!< Channel 13 selection */\n#define  ADC_CHSELR_CHSEL12                   ((uint32_t)0x00001000)        /*!< Channel 12 selection */\n#define  ADC_CHSELR_CHSEL11                   ((uint32_t)0x00000800)        /*!< Channel 11 selection */\n#define  ADC_CHSELR_CHSEL10                   ((uint32_t)0x00000400)        /*!< Channel 10 selection */\n#define  ADC_CHSELR_CHSEL9                    ((uint32_t)0x00000200)        /*!< Channel 9 selection */\n#define  ADC_CHSELR_CHSEL8                    ((uint32_t)0x00000100)        /*!< Channel 8 selection */\n#define  ADC_CHSELR_CHSEL7                    ((uint32_t)0x00000080)        /*!< Channel 7 selection */\n#define  ADC_CHSELR_CHSEL6                    ((uint32_t)0x00000040)        /*!< Channel 6 selection */\n#define  ADC_CHSELR_CHSEL5                    ((uint32_t)0x00000020)        /*!< Channel 5 selection */\n#define  ADC_CHSELR_CHSEL4                    ((uint32_t)0x00000010)        /*!< Channel 4 selection */\n#define  ADC_CHSELR_CHSEL3                    ((uint32_t)0x00000008)        /*!< Channel 3 selection */\n#define  ADC_CHSELR_CHSEL2                    ((uint32_t)0x00000004)        /*!< Channel 2 selection */\n#define  ADC_CHSELR_CHSEL1                    ((uint32_t)0x00000002)        /*!< Channel 1 selection */\n#define  ADC_CHSELR_CHSEL0                    ((uint32_t)0x00000001)        /*!< Channel 0 selection */\n\n/********************  Bit definition for ADC_DR register  ********************/\n#define  ADC_DR_DATA                         ((uint32_t)0x0000FFFF)        /*!< Regular data */\n\n/********************  Bit definition for ADC_CALFACT register  ********************/\n#define  ADC_CALFACT_CALFACT       ((uint32_t)0x0000007F)        /*!< Regular data */\n\n/*******************  Bit definition for ADC_CCR register  ********************/\n#define  ADC_CCR_LFMEN                        ((uint32_t)0x02000000)       /*!< Low Frequency Mode enable */\n#define  ADC_CCR_VLCDEN                       ((uint32_t)0x01000000)       /*!< Voltage battery enable */\n#define  ADC_CCR_TSEN                         ((uint32_t)0x00800000)       /*!< Tempurature sensore enable */\n#define  ADC_CCR_VREFEN                       ((uint32_t)0x00400000)       /*!< Vrefint enable */\n#define  ADC_CCR_PRESC                        ((uint32_t)0x003C0000)       /*!< PRESC  [3:0] bits (ADC prescaler) */\n#define  ADC_CCR_PRESC_0                      ((uint32_t)0x00040000)       /*!< Bit 0 */\n#define  ADC_CCR_PRESC_1                      ((uint32_t)0x00080000)       /*!< Bit 1 */\n#define  ADC_CCR_PRESC_2                      ((uint32_t)0x00100000)       /*!< Bit 2 */\n#define  ADC_CCR_PRESC_3                      ((uint32_t)0x00200000)       /*!< Bit 3 */\n\n/******************************************************************************/\n/*                                                                            */\n/*                      Analog Comparators (COMP)                             */\n/*                                                                            */\n/******************************************************************************/\n/*************  Bit definition for COMP_CSR register (COMP1 and COMP2)  **************/\n/* COMP1 bits definition */\n#define COMP_CSR_COMP1EN                ((uint32_t)0x00000001) /*!< COMP1 enable */\n#define COMP_CSR_COMP1INNSEL            ((uint32_t)0x00000030) /*!< COMP1 inverting input select */\n#define COMP_CSR_COMP1INNSEL_0          ((uint32_t)0x00000010) /*!< COMP1 inverting input select bit 0 */\n#define COMP_CSR_COMP1INNSEL_1          ((uint32_t)0x00000020) /*!< COMP1 inverting input select bit 1 */\n#define COMP_CSR_COMP1WM                ((uint32_t)0x00000100) /*!< Comparators window mode enable */\n#define COMP_CSR_COMP1LPTIM1IN1         ((uint32_t)0x00001000) /*!< COMP1 LPTIM1 IN1 connection */\n#define COMP_CSR_COMP1POLARITY          ((uint32_t)0x00008000) /*!< COMP1 output polarity */\n#define COMP_CSR_COMP1VALUE             ((uint32_t)0x40000000) /*!< COMP1 output level */\n#define COMP_CSR_COMP1LOCK              ((uint32_t)0x80000000) /*!< COMP1 lock */\n/* COMP2 bits definition */\n#define COMP_CSR_COMP2EN                ((uint32_t)0x00000001) /*!< COMP2 enable */\n#define COMP_CSR_COMP2SPEED             ((uint32_t)0x000C0008) /*!< COMP2 power mode */\n#define COMP_CSR_COMP2INNSEL            ((uint32_t)0x00100070) /*!< COMP2 inverting input select */\n#define COMP_CSR_COMP2INNSEL_0          ((uint32_t)0x00100010) /*!< COMP2 inverting input select bit 0 */\n#define COMP_CSR_COMP2INNSEL_1          ((uint32_t)0x00200020) /*!< COMP2 inverting input select bit 1 */\n#define COMP_CSR_COMP2INNSEL_2          ((uint32_t)0x00400040) /*!< COMP2 inverting input select bit 2 */\n#define COMP_CSR_COMP2INPSEL            ((uint32_t)0x00000700) /*!< COMPx non inverting input select */\n#define COMP_CSR_COMP2INPSEL_0          ((uint32_t)0x00000100) /*!< COMPx non inverting input select */\n#define COMP_CSR_COMP2INPSEL_1          ((uint32_t)0x00000200) /*!< COMPx non inverting input select */\n#define COMP_CSR_COMP2INPSEL_2          ((uint32_t)0x00000400) /*!< COMPx non inverting input select */\n#define COMP_CSR_COMP2LPTIM1IN2         ((uint32_t)0x00001000) /*!< COMP2 LPTIM1 IN2 connection */\n#define COMP_CSR_COMP2POLARITY          ((uint32_t)0x00008000) /*!< COMP2 output polarity */\n#define COMP_CSR_COMP2VALUE             ((uint32_t)0x40000000) /*!< COMP2 output level */\n#define COMP_CSR_COMP2LOCK              ((uint32_t)0x80000000) /*!< COMP2 lock */\n\n/**********************  Bit definition for COMP_CSR register common  ****************/\n#define COMP_CSR_COMPxEN               ((uint32_t)0x00000001) /*!< COMPx enable */\n#define COMP_CSR_COMPxPOLARITY         ((uint32_t)0x00008000) /*!< COMPx output polarity */\n#define COMP_CSR_COMPxOUTVALUE         ((uint32_t)0x40000000) /*!< COMPx output level */\n#define COMP_CSR_COMPxLOCK             ((uint32_t)0x80000000) /*!< COMPx lock */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                       CRC calculation unit (CRC)                           */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for CRC_DR register  *********************/\n#define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFF) /*!< Data register bits */\n\n/*******************  Bit definition for CRC_IDR register  ********************/\n#define  CRC_IDR_IDR                         ((uint8_t)0xFF)        /*!< General-purpose 8-bit data register bits */\n\n/********************  Bit definition for CRC_CR register  ********************/\n#define  CRC_CR_RESET                        ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */\n#define  CRC_CR_POLYSIZE                     ((uint32_t)0x00000018) /*!< Polynomial size bits */\n#define  CRC_CR_POLYSIZE_0                   ((uint32_t)0x00000008) /*!< Polynomial size bit 0 */\n#define  CRC_CR_POLYSIZE_1                   ((uint32_t)0x00000010) /*!< Polynomial size bit 1 */\n#define  CRC_CR_REV_IN                       ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */\n#define  CRC_CR_REV_IN_0                     ((uint32_t)0x00000020) /*!< Bit 0 */\n#define  CRC_CR_REV_IN_1                     ((uint32_t)0x00000040) /*!< Bit 1 */\n#define  CRC_CR_REV_OUT                      ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */\n\n/*******************  Bit definition for CRC_INIT register  *******************/\n#define  CRC_INIT_INIT                       ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */\n\n/*******************  Bit definition for CRC_POL register  ********************/\n#define  CRC_POL_POL                         ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial */\n\n/******************************************************************************/\n/*                                                                            */\n/*                          CRS Clock Recovery System                         */\n/*                                                                            */\n/******************************************************************************/\n\n/*******************  Bit definition for CRS_CR register  *********************/\n#define  CRS_CR_SYNCOKIE                     ((uint32_t)0x00000001) /* SYNC event OK interrupt enable        */\n#define  CRS_CR_SYNCWARNIE                   ((uint32_t)0x00000002) /* SYNC warning interrupt enable         */\n#define  CRS_CR_ERRIE                        ((uint32_t)0x00000004) /* SYNC error interrupt enable           */\n#define  CRS_CR_ESYNCIE                      ((uint32_t)0x00000008) /* Expected SYNC(ESYNCF) interrupt Enable*/\n#define  CRS_CR_CEN                          ((uint32_t)0x00000020) /* Frequency error counter enable        */\n#define  CRS_CR_AUTOTRIMEN                   ((uint32_t)0x00000040) /* Automatic trimming enable             */\n#define  CRS_CR_SWSYNC                       ((uint32_t)0x00000080) /* A Software SYNC event is generated    */\n#define  CRS_CR_TRIM                         ((uint32_t)0x00003F00) /* HSI48 oscillator smooth trimming      */\n\n/*******************  Bit definition for CRS_CFGR register  *********************/\n#define  CRS_CFGR_RELOAD                     ((uint32_t)0x0000FFFF) /* Counter reload value               */\n#define  CRS_CFGR_FELIM                      ((uint32_t)0x00FF0000) /* Frequency error limit              */\n\n#define  CRS_CFGR_SYNCDIV                    ((uint32_t)0x07000000) /* SYNC divider                       */\n#define  CRS_CFGR_SYNCDIV_0                  ((uint32_t)0x01000000) /* Bit 0                              */\n#define  CRS_CFGR_SYNCDIV_1                  ((uint32_t)0x02000000) /* Bit 1                              */\n#define  CRS_CFGR_SYNCDIV_2                  ((uint32_t)0x04000000) /* Bit 2                              */\n\n#define  CRS_CFGR_SYNCSRC                    ((uint32_t)0x30000000) /* SYNC signal source selection       */\n#define  CRS_CFGR_SYNCSRC_0                  ((uint32_t)0x10000000) /* Bit 0                              */\n#define  CRS_CFGR_SYNCSRC_1                  ((uint32_t)0x20000000) /* Bit 1                              */\n\n#define  CRS_CFGR_SYNCPOL                    ((uint32_t)0x80000000) /* SYNC polarity selection            */\n\n/*******************  Bit definition for CRS_ISR register  *********************/\n#define  CRS_ISR_SYNCOKF                     ((uint32_t)0x00000001) /* SYNC event OK flag             */\n#define  CRS_ISR_SYNCWARNF                   ((uint32_t)0x00000002) /* SYNC warning                   */\n#define  CRS_ISR_ERRF                        ((uint32_t)0x00000004) /* SYNC error flag                */\n#define  CRS_ISR_ESYNCF                      ((uint32_t)0x00000008) /* Expected SYNC flag             */\n#define  CRS_ISR_SYNCERR                     ((uint32_t)0x00000100) /* SYNC error                     */\n#define  CRS_ISR_SYNCMISS                    ((uint32_t)0x00000200) /* SYNC missed                    */\n#define  CRS_ISR_TRIMOVF                     ((uint32_t)0x00000400) /* Trimming overflow or underflow */\n#define  CRS_ISR_FEDIR                       ((uint32_t)0x00008000) /* Frequency error direction      */\n#define  CRS_ISR_FECAP                       ((uint32_t)0xFFFF0000) /* Frequency error capture        */\n\n/*******************  Bit definition for CRS_ICR register  *********************/\n#define  CRS_ICR_SYNCOKC                     ((uint32_t)0x00000001) /* SYNC event OK clear flag     */\n#define  CRS_ICR_SYNCWARNC                   ((uint32_t)0x00000002) /* SYNC warning clear flag      */\n#define  CRS_ICR_ERRC                        ((uint32_t)0x00000004) /* Error clear flag             */\n#define  CRS_ICR_ESYNCC                      ((uint32_t)0x00000008) /* Expected SYNC clear flag     */\n\n/******************************************************************************/\n/*                                                                            */\n/*                 Digital to Analog Converter (DAC)                          */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for DAC_CR register  ********************/\n#define  DAC_CR_EN1                          ((uint32_t)0x00000001)        /*!< DAC channel1 enable */\n#define  DAC_CR_BOFF1                        ((uint32_t)0x00000002)        /*!< DAC channel1 output buffer disable */\n#define  DAC_CR_TEN1                         ((uint32_t)0x00000004)        /*!< DAC channel1 Trigger enable */\n\n#define  DAC_CR_TSEL1                        ((uint32_t)0x00000038)        /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */\n#define  DAC_CR_TSEL1_0                      ((uint32_t)0x00000008)        /*!< Bit 0 */\n#define  DAC_CR_TSEL1_1                      ((uint32_t)0x00000010)        /*!< Bit 1 */\n#define  DAC_CR_TSEL1_2                      ((uint32_t)0x00000020)        /*!< Bit 2 */\n\n#define  DAC_CR_WAVE1                        ((uint32_t)0x000000C0)        /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */\n#define  DAC_CR_WAVE1_0                      ((uint32_t)0x00000040)        /*!< Bit 0 */\n#define  DAC_CR_WAVE1_1                      ((uint32_t)0x00000080)        /*!< Bit 1 */\n\n#define  DAC_CR_MAMP1                        ((uint32_t)0x00000F00)        /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */\n#define  DAC_CR_MAMP1_0                      ((uint32_t)0x00000100)        /*!< Bit 0 */\n#define  DAC_CR_MAMP1_1                      ((uint32_t)0x00000200)        /*!< Bit 1 */\n#define  DAC_CR_MAMP1_2                      ((uint32_t)0x00000400)        /*!< Bit 2 */\n#define  DAC_CR_MAMP1_3                      ((uint32_t)0x00000800)        /*!< Bit 3 */\n\n#define  DAC_CR_DMAEN1                       ((uint32_t)0x00001000)        /*!< DAC channel1 DMA enable */\n#define  DAC_CR_DMAUDRIE1                    ((uint32_t)0x00002000)        /*!< DAC channel1 DMA Interrupt enable */\n\n/*****************  Bit definition for DAC_SWTRIGR register  ******************/\n#define  DAC_SWTRIGR_SWTRIG1                 ((uint8_t)0x01)               /*!< DAC channel1 software trigger */\n\n/*****************  Bit definition for DAC_DHR12R1 register  ******************/\n#define  DAC_DHR12R1_DACC1DHR                ((uint16_t)0x0FFF)            /*!< DAC channel1 12-bit Right aligned data */\n\n/*****************  Bit definition for DAC_DHR12L1 register  ******************/\n#define  DAC_DHR12L1_DACC1DHR                ((uint16_t)0xFFF0)            /*!< DAC channel1 12-bit Left aligned data */\n\n/******************  Bit definition for DAC_DHR8R1 register  ******************/\n#define  DAC_DHR8R1_DACC1DHR                 ((uint8_t)0xFF)               /*!< DAC channel1 8-bit Right aligned data */\n\n/*******************  Bit definition for DAC_DOR1 register  *******************/\n#define  DAC_DOR1_DACC1DOR                   ((uint16_t)0x0FFF)            /*!< DAC channel1 data output */\n\n/********************  Bit definition for DAC_SR register  ********************/\n#define  DAC_SR_DMAUDR1                      ((uint32_t)0x00002000)        /*!< DAC channel1 DMA underrun flag */\n\n/******************************************************************************/\n/*                                                                            */\n/*                           Debug MCU (DBGMCU)                               */\n/*                                                                            */\n/******************************************************************************/\n\n/****************  Bit definition for DBGMCU_IDCODE register  *****************/\n#define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFF)        /*!< Device Identifier */\n\n#define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000)        /*!< REV_ID[15:0] bits (Revision Identifier) */\n#define  DBGMCU_IDCODE_REV_ID_0              ((uint32_t)0x00010000)        /*!< Bit 0 */\n#define  DBGMCU_IDCODE_REV_ID_1              ((uint32_t)0x00020000)        /*!< Bit 1 */\n#define  DBGMCU_IDCODE_REV_ID_2              ((uint32_t)0x00040000)        /*!< Bit 2 */\n#define  DBGMCU_IDCODE_REV_ID_3              ((uint32_t)0x00080000)        /*!< Bit 3 */\n#define  DBGMCU_IDCODE_REV_ID_4              ((uint32_t)0x00100000)        /*!< Bit 4 */\n#define  DBGMCU_IDCODE_REV_ID_5              ((uint32_t)0x00200000)        /*!< Bit 5 */\n#define  DBGMCU_IDCODE_REV_ID_6              ((uint32_t)0x00400000)        /*!< Bit 6 */\n#define  DBGMCU_IDCODE_REV_ID_7              ((uint32_t)0x00800000)        /*!< Bit 7 */\n#define  DBGMCU_IDCODE_REV_ID_8              ((uint32_t)0x01000000)        /*!< Bit 8 */\n#define  DBGMCU_IDCODE_REV_ID_9              ((uint32_t)0x02000000)        /*!< Bit 9 */\n#define  DBGMCU_IDCODE_REV_ID_10             ((uint32_t)0x04000000)        /*!< Bit 10 */\n#define  DBGMCU_IDCODE_REV_ID_11             ((uint32_t)0x08000000)        /*!< Bit 11 */\n#define  DBGMCU_IDCODE_REV_ID_12             ((uint32_t)0x10000000)        /*!< Bit 12 */\n#define  DBGMCU_IDCODE_REV_ID_13             ((uint32_t)0x20000000)        /*!< Bit 13 */\n#define  DBGMCU_IDCODE_REV_ID_14             ((uint32_t)0x40000000)        /*!< Bit 14 */\n#define  DBGMCU_IDCODE_REV_ID_15             ((uint32_t)0x80000000)        /*!< Bit 15 */\n\n/******************  Bit definition for DBGMCU_CR register  *******************/\n#define  DBGMCU_CR_DBG_SLEEP                 ((uint32_t)0x00000001)        /*!< Debug Sleep Mode */\n#define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002)        /*!< Debug Stop Mode */\n#define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004)        /*!< Debug Standby mode */\n\n/******************  Bit definition for DBGMCU_APB1_FZ register  **************/\n#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP        ((uint32_t)0x00000001)        /*!< TIM2 counter stopped when core is halted */\n#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP        ((uint32_t)0x00000010)        /*!< TIM6 counter stopped when core is halted */\n#define  DBGMCU_APB1_FZ_DBG_RTC_STOP         ((uint32_t)0x00000400)        /*!< RTC Calendar frozen when core is halted */\n#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP        ((uint32_t)0x00000800)        /*!< Debug Window Watchdog stopped when Core is halted */\n#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP        ((uint32_t)0x00001000)        /*!< Debug Independent Watchdog stopped when Core is halted */\n#define  DBGMCU_APB1_FZ_DBG_I2C1_STOP        ((uint32_t)0x00200000)   /*!< I2C1 SMBUS timeout mode stopped when Core is halted */\n#define  DBGMCU_APB1_FZ_DBG_I2C2_STOP        ((uint32_t)0x00400000)   /*!< I2C2 SMBUS timeout mode stopped when Core is halted */\n#define  DBGMCU_APB1_FZ_DBG_LPTIMER_STOP     ((uint32_t)0x80000000)   /*!< LPTIM1 counter stopped when core is halted */\n/******************  Bit definition for DBGMCU_APB2_FZ register  **************/\n#define  DBGMCU_APB2_FZ_DBG_TIM22_STOP       ((uint32_t)0x00000020)        /*!< TIM22 counter stopped when core is halted */\n#define  DBGMCU_APB2_FZ_DBG_TIM21_STOP        ((uint32_t)0x00000004)        /*!< TIM21 counter stopped when core is halted */\n\n/******************************************************************************/\n/*                                                                            */\n/*                           DMA Controller (DMA)                             */\n/*                                                                            */\n/******************************************************************************/\n\n/*******************  Bit definition for DMA_ISR register  ********************/\n#define  DMA_ISR_GIF1                        ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt flag    */\n#define  DMA_ISR_TCIF1                       ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete flag   */\n#define  DMA_ISR_HTIF1                       ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer flag       */\n#define  DMA_ISR_TEIF1                       ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error flag      */\n#define  DMA_ISR_GIF2                        ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt flag    */\n#define  DMA_ISR_TCIF2                       ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete flag   */\n#define  DMA_ISR_HTIF2                       ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer flag       */\n#define  DMA_ISR_TEIF2                       ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error flag      */\n#define  DMA_ISR_GIF3                        ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt flag    */\n#define  DMA_ISR_TCIF3                       ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete flag   */\n#define  DMA_ISR_HTIF3                       ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer flag       */\n#define  DMA_ISR_TEIF3                       ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error flag      */\n#define  DMA_ISR_GIF4                        ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt flag    */\n#define  DMA_ISR_TCIF4                       ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete flag   */\n#define  DMA_ISR_HTIF4                       ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer flag       */\n#define  DMA_ISR_TEIF4                       ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error flag      */\n#define  DMA_ISR_GIF5                        ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt flag    */\n#define  DMA_ISR_TCIF5                       ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete flag   */\n#define  DMA_ISR_HTIF5                       ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer flag       */\n#define  DMA_ISR_TEIF5                       ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error flag      */\n#define  DMA_ISR_GIF6                        ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt flag */\n#define  DMA_ISR_TCIF6                       ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete flag */\n#define  DMA_ISR_HTIF6                       ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer flag */\n#define  DMA_ISR_TEIF6                       ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error flag */\n#define  DMA_ISR_GIF7                        ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt flag */\n#define  DMA_ISR_TCIF7                       ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete flag */\n#define  DMA_ISR_HTIF7                       ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer flag */\n#define  DMA_ISR_TEIF7                       ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error flag */\n\n/*******************  Bit definition for DMA_IFCR register  *******************/\n#define  DMA_IFCR_CGIF1                      ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt clear    */\n#define  DMA_IFCR_CTCIF1                     ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete clear   */\n#define  DMA_IFCR_CHTIF1                     ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer clear       */\n#define  DMA_IFCR_CTEIF1                     ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error clear      */\n#define  DMA_IFCR_CGIF2                      ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt clear    */\n#define  DMA_IFCR_CTCIF2                     ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete clear   */\n#define  DMA_IFCR_CHTIF2                     ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer clear       */\n#define  DMA_IFCR_CTEIF2                     ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error clear      */\n#define  DMA_IFCR_CGIF3                      ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt clear    */\n#define  DMA_IFCR_CTCIF3                     ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete clear   */\n#define  DMA_IFCR_CHTIF3                     ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer clear       */\n#define  DMA_IFCR_CTEIF3                     ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error clear      */\n#define  DMA_IFCR_CGIF4                      ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt clear    */\n#define  DMA_IFCR_CTCIF4                     ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete clear   */\n#define  DMA_IFCR_CHTIF4                     ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer clear       */\n#define  DMA_IFCR_CTEIF4                     ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error clear      */\n#define  DMA_IFCR_CGIF5                      ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt clear    */\n#define  DMA_IFCR_CTCIF5                     ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete clear   */\n#define  DMA_IFCR_CHTIF5                     ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer clear       */\n#define  DMA_IFCR_CTEIF5                     ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error clear      */\n#define  DMA_IFCR_CGIF6                      ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt clear */\n#define  DMA_IFCR_CTCIF6                     ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete clear */\n#define  DMA_IFCR_CHTIF6                     ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer clear */\n#define  DMA_IFCR_CTEIF6                     ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error clear */\n#define  DMA_IFCR_CGIF7                      ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt clear */\n#define  DMA_IFCR_CTCIF7                     ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete clear */\n#define  DMA_IFCR_CHTIF7                     ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer clear */\n#define  DMA_IFCR_CTEIF7                     ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error clear */\n\n/*******************  Bit definition for DMA_CCR register  ********************/\n#define  DMA_CCR_EN                          ((uint32_t)0x00000001)        /*!< Channel enable                      */\n#define  DMA_CCR_TCIE                        ((uint32_t)0x00000002)        /*!< Transfer complete interrupt enable  */\n#define  DMA_CCR_HTIE                        ((uint32_t)0x00000004)        /*!< Half Transfer interrupt enable      */\n#define  DMA_CCR_TEIE                        ((uint32_t)0x00000008)        /*!< Transfer error interrupt enable     */\n#define  DMA_CCR_DIR                         ((uint32_t)0x00000010)        /*!< Data transfer direction             */\n#define  DMA_CCR_CIRC                        ((uint32_t)0x00000020)        /*!< Circular mode                       */\n#define  DMA_CCR_PINC                        ((uint32_t)0x00000040)        /*!< Peripheral increment mode           */\n#define  DMA_CCR_MINC                        ((uint32_t)0x00000080)        /*!< Memory increment mode               */\n\n#define  DMA_CCR_PSIZE                       ((uint32_t)0x00000300)        /*!< PSIZE[1:0] bits (Peripheral size)   */\n#define  DMA_CCR_PSIZE_0                     ((uint32_t)0x00000100)        /*!< Bit 0                               */\n#define  DMA_CCR_PSIZE_1                     ((uint32_t)0x00000200)        /*!< Bit 1                               */\n\n#define  DMA_CCR_MSIZE                       ((uint32_t)0x00000C00)        /*!< MSIZE[1:0] bits (Memory size)       */\n#define  DMA_CCR_MSIZE_0                     ((uint32_t)0x00000400)        /*!< Bit 0                               */\n#define  DMA_CCR_MSIZE_1                     ((uint32_t)0x00000800)        /*!< Bit 1                               */\n\n#define  DMA_CCR_PL                          ((uint32_t)0x00003000)        /*!< PL[1:0] bits(Channel Priority level)*/\n#define  DMA_CCR_PL_0                        ((uint32_t)0x00001000)        /*!< Bit 0                               */\n#define  DMA_CCR_PL_1                        ((uint32_t)0x00002000)        /*!< Bit 1                               */\n\n#define  DMA_CCR_MEM2MEM                     ((uint32_t)0x00004000)        /*!< Memory to memory mode               */\n\n/******************  Bit definition for DMA_CNDTR register  *******************/\n#define  DMA_CNDTR_NDT                       ((uint32_t)0x0000FFFF)        /*!< Number of data to Transfer          */\n\n/******************  Bit definition for DMA_CPAR register  ********************/\n#define  DMA_CPAR_PA                         ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address                  */\n\n/******************  Bit definition for DMA_CMAR register  ********************/\n#define  DMA_CMAR_MA                         ((uint32_t)0xFFFFFFFF)        /*!< Memory Address                      */\n\n\n/*******************  Bit definition for DMA_CSELR register  *******************/\n#define  DMA_CSELR_C1S                          ((uint32_t)0x0000000F)          /*!< Channel 1 Selection */\n#define  DMA_CSELR_C2S                          ((uint32_t)0x000000F0)          /*!< Channel 2 Selection */\n#define  DMA_CSELR_C3S                          ((uint32_t)0x00000F00)          /*!< Channel 3 Selection */\n#define  DMA_CSELR_C4S                          ((uint32_t)0x0000F000)          /*!< Channel 4 Selection */\n#define  DMA_CSELR_C5S                          ((uint32_t)0x000F0000)          /*!< Channel 5 Selection */\n#define  DMA_CSELR_C6S                          ((uint32_t)0x00F00000)          /*!< Channel 6 Selection */\n#define  DMA_CSELR_C7S                          ((uint32_t)0x0F000000)          /*!< Channel 7 Selection */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                 External Interrupt/Event Controller (EXTI)                 */\n/*                                                                            */\n/******************************************************************************/\n\n/*******************  Bit definition for EXTI_IMR register  *******************/\n#define  EXTI_IMR_IM0                        ((uint32_t)0x00000001)        /*!< Interrupt Mask on line 0  */\n#define  EXTI_IMR_IM1                        ((uint32_t)0x00000002)        /*!< Interrupt Mask on line 1  */\n#define  EXTI_IMR_IM2                        ((uint32_t)0x00000004)        /*!< Interrupt Mask on line 2  */\n#define  EXTI_IMR_IM3                        ((uint32_t)0x00000008)        /*!< Interrupt Mask on line 3  */\n#define  EXTI_IMR_IM4                        ((uint32_t)0x00000010)        /*!< Interrupt Mask on line 4  */\n#define  EXTI_IMR_IM5                        ((uint32_t)0x00000020)        /*!< Interrupt Mask on line 5  */\n#define  EXTI_IMR_IM6                        ((uint32_t)0x00000040)        /*!< Interrupt Mask on line 6  */\n#define  EXTI_IMR_IM7                        ((uint32_t)0x00000080)        /*!< Interrupt Mask on line 7  */\n#define  EXTI_IMR_IM8                        ((uint32_t)0x00000100)        /*!< Interrupt Mask on line 8  */\n#define  EXTI_IMR_IM9                        ((uint32_t)0x00000200)        /*!< Interrupt Mask on line 9  */\n#define  EXTI_IMR_IM10                       ((uint32_t)0x00000400)        /*!< Interrupt Mask on line 10 */\n#define  EXTI_IMR_IM11                       ((uint32_t)0x00000800)        /*!< Interrupt Mask on line 11 */\n#define  EXTI_IMR_IM12                       ((uint32_t)0x00001000)        /*!< Interrupt Mask on line 12 */\n#define  EXTI_IMR_IM13                       ((uint32_t)0x00002000)        /*!< Interrupt Mask on line 13 */\n#define  EXTI_IMR_IM14                       ((uint32_t)0x00004000)        /*!< Interrupt Mask on line 14 */\n#define  EXTI_IMR_IM15                       ((uint32_t)0x00008000)        /*!< Interrupt Mask on line 15 */\n#define  EXTI_IMR_IM16                       ((uint32_t)0x00010000)        /*!< Interrupt Mask on line 16 */\n#define  EXTI_IMR_IM17                       ((uint32_t)0x00020000)        /*!< Interrupt Mask on line 17 */\n#define  EXTI_IMR_IM19                       ((uint32_t)0x00080000)        /*!< Interrupt Mask on line 19 */\n#define  EXTI_IMR_IM21                       ((uint32_t)0x00200000)        /*!< Interrupt Mask on line 21 */\n#define  EXTI_IMR_IM22                       ((uint32_t)0x00400000)        /*!< Interrupt Mask on line 22 */\n#define  EXTI_IMR_IM23                       ((uint32_t)0x00800000)        /*!< Interrupt Mask on line 23 */\n#define  EXTI_IMR_IM25                       ((uint32_t)0x02000000)        /*!< Interrupt Mask on line 25 */\n#define  EXTI_IMR_IM27                       ((uint32_t)0x08000000)        /*!< Interrupt Mask on line 27 */\n\n/******************  Bit definition for EXTI_EMR register  ********************/\n#define  EXTI_EMR_EM0                        ((uint32_t)0x00000001)        /*!< Event Mask on line 0  */\n#define  EXTI_EMR_EM1                        ((uint32_t)0x00000002)        /*!< Event Mask on line 1  */\n#define  EXTI_EMR_EM2                        ((uint32_t)0x00000004)        /*!< Event Mask on line 2  */\n#define  EXTI_EMR_EM3                        ((uint32_t)0x00000008)        /*!< Event Mask on line 3  */\n#define  EXTI_EMR_EM4                        ((uint32_t)0x00000010)        /*!< Event Mask on line 4  */\n#define  EXTI_EMR_EM5                        ((uint32_t)0x00000020)        /*!< Event Mask on line 5  */\n#define  EXTI_EMR_EM6                        ((uint32_t)0x00000040)        /*!< Event Mask on line 6  */\n#define  EXTI_EMR_EM7                        ((uint32_t)0x00000080)        /*!< Event Mask on line 7  */\n#define  EXTI_EMR_EM8                        ((uint32_t)0x00000100)        /*!< Event Mask on line 8  */\n#define  EXTI_EMR_EM9                        ((uint32_t)0x00000200)        /*!< Event Mask on line 9  */\n#define  EXTI_EMR_EM10                       ((uint32_t)0x00000400)        /*!< Event Mask on line 10 */\n#define  EXTI_EMR_EM11                       ((uint32_t)0x00000800)        /*!< Event Mask on line 11 */\n#define  EXTI_EMR_EM12                       ((uint32_t)0x00001000)        /*!< Event Mask on line 12 */\n#define  EXTI_EMR_EM13                       ((uint32_t)0x00002000)        /*!< Event Mask on line 13 */\n#define  EXTI_EMR_EM14                       ((uint32_t)0x00004000)        /*!< Event Mask on line 14 */\n#define  EXTI_EMR_EM15                       ((uint32_t)0x00008000)        /*!< Event Mask on line 15 */\n#define  EXTI_EMR_EM16                       ((uint32_t)0x00010000)        /*!< Event Mask on line 16 */\n#define  EXTI_EMR_EM17                       ((uint32_t)0x00020000)        /*!< Event Mask on line 17 */\n#define  EXTI_EMR_EM19                       ((uint32_t)0x00080000)        /*!< Event Mask on line 19 */\n#define  EXTI_EMR_EM21                       ((uint32_t)0x00200000)        /*!< Event Mask on line 21 */\n#define  EXTI_EMR_EM22                       ((uint32_t)0x00400000)        /*!< Event Mask on line 22 */\n#define  EXTI_EMR_EM23                       ((uint32_t)0x00800000)        /*!< Event Mask on line 23 */\n#define  EXTI_EMR_EM25                       ((uint32_t)0x02000000)        /*!< Event Mask on line 25 */\n#define  EXTI_EMR_EM27                       ((uint32_t)0x08000000)        /*!< Event Mask on line 27 */\n\n/*******************  Bit definition for EXTI_RTSR register  ******************/\n#define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001)        /*!< Rising trigger event configuration bit of line 0 */\n#define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002)        /*!< Rising trigger event configuration bit of line 1 */\n#define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004)        /*!< Rising trigger event configuration bit of line 2 */\n#define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008)        /*!< Rising trigger event configuration bit of line 3 */\n#define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010)        /*!< Rising trigger event configuration bit of line 4 */\n#define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020)        /*!< Rising trigger event configuration bit of line 5 */\n#define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040)        /*!< Rising trigger event configuration bit of line 6 */\n#define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080)        /*!< Rising trigger event configuration bit of line 7 */\n#define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100)        /*!< Rising trigger event configuration bit of line 8 */\n#define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200)        /*!< Rising trigger event configuration bit of line 9 */\n#define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400)        /*!< Rising trigger event configuration bit of line 10 */\n#define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800)        /*!< Rising trigger event configuration bit of line 11 */\n#define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000)        /*!< Rising trigger event configuration bit of line 12 */\n#define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000)        /*!< Rising trigger event configuration bit of line 13 */\n#define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000)        /*!< Rising trigger event configuration bit of line 14 */\n#define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000)        /*!< Rising trigger event configuration bit of line 15 */\n#define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000)        /*!< Rising trigger event configuration bit of line 16 */\n#define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000)        /*!< Rising trigger event configuration bit of line 17 */\n#define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000)        /*!< Rising trigger event configuration bit of line 19 */\n\n/*******************  Bit definition for EXTI_FTSR register *******************/\n#define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001)        /*!< Falling trigger event configuration bit of line 0 */\n#define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002)        /*!< Falling trigger event configuration bit of line 1 */\n#define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004)        /*!< Falling trigger event configuration bit of line 2 */\n#define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008)        /*!< Falling trigger event configuration bit of line 3 */\n#define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010)        /*!< Falling trigger event configuration bit of line 4 */\n#define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020)        /*!< Falling trigger event configuration bit of line 5 */\n#define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040)        /*!< Falling trigger event configuration bit of line 6 */\n#define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080)        /*!< Falling trigger event configuration bit of line 7 */\n#define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100)        /*!< Falling trigger event configuration bit of line 8 */\n#define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200)        /*!< Falling trigger event configuration bit of line 9 */\n#define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400)        /*!< Falling trigger event configuration bit of line 10 */\n#define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800)        /*!< Falling trigger event configuration bit of line 11 */\n#define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000)        /*!< Falling trigger event configuration bit of line 12 */\n#define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000)        /*!< Falling trigger event configuration bit of line 13 */\n#define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000)        /*!< Falling trigger event configuration bit of line 14 */\n#define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000)        /*!< Falling trigger event configuration bit of line 15 */\n#define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000)        /*!< Falling trigger event configuration bit of line 16 */\n#define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000)        /*!< Falling trigger event configuration bit of line 17 */\n#define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000)        /*!< Falling trigger event configuration bit of line 19 */\n\n/******************* Bit definition for EXTI_SWIER register *******************/\n#define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001)        /*!< Software Interrupt on line 0  */\n#define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002)        /*!< Software Interrupt on line 1  */\n#define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004)        /*!< Software Interrupt on line 2  */\n#define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008)        /*!< Software Interrupt on line 3  */\n#define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010)        /*!< Software Interrupt on line 4  */\n#define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020)        /*!< Software Interrupt on line 5  */\n#define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040)        /*!< Software Interrupt on line 6  */\n#define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080)        /*!< Software Interrupt on line 7  */\n#define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100)        /*!< Software Interrupt on line 8  */\n#define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200)        /*!< Software Interrupt on line 9  */\n#define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400)        /*!< Software Interrupt on line 10 */\n#define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800)        /*!< Software Interrupt on line 11 */\n#define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000)        /*!< Software Interrupt on line 12 */\n#define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000)        /*!< Software Interrupt on line 13 */\n#define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000)        /*!< Software Interrupt on line 14 */\n#define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000)        /*!< Software Interrupt on line 15 */\n#define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000)        /*!< Software Interrupt on line 16 */\n#define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000)        /*!< Software Interrupt on line 17 */\n#define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000)        /*!< Software Interrupt on line 19 */\n\n/******************  Bit definition for EXTI_PR register  *********************/\n#define  EXTI_PR_PR0                         ((uint32_t)0x00000001)        /*!< Pending bit 0  */\n#define  EXTI_PR_PR1                         ((uint32_t)0x00000002)        /*!< Pending bit 1  */\n#define  EXTI_PR_PR2                         ((uint32_t)0x00000004)        /*!< Pending bit 2  */\n#define  EXTI_PR_PR3                         ((uint32_t)0x00000008)        /*!< Pending bit 3  */\n#define  EXTI_PR_PR4                         ((uint32_t)0x00000010)        /*!< Pending bit 4  */\n#define  EXTI_PR_PR5                         ((uint32_t)0x00000020)        /*!< Pending bit 5  */\n#define  EXTI_PR_PR6                         ((uint32_t)0x00000040)        /*!< Pending bit 6  */\n#define  EXTI_PR_PR7                         ((uint32_t)0x00000080)        /*!< Pending bit 7  */\n#define  EXTI_PR_PR8                         ((uint32_t)0x00000100)        /*!< Pending bit 8  */\n#define  EXTI_PR_PR9                         ((uint32_t)0x00000200)        /*!< Pending bit 9  */\n#define  EXTI_PR_PR10                        ((uint32_t)0x00000400)        /*!< Pending bit 10 */\n#define  EXTI_PR_PR11                        ((uint32_t)0x00000800)        /*!< Pending bit 11 */\n#define  EXTI_PR_PR12                        ((uint32_t)0x00001000)        /*!< Pending bit 12 */\n#define  EXTI_PR_PR13                        ((uint32_t)0x00002000)        /*!< Pending bit 13 */\n#define  EXTI_PR_PR14                        ((uint32_t)0x00004000)        /*!< Pending bit 14 */\n#define  EXTI_PR_PR15                        ((uint32_t)0x00008000)        /*!< Pending bit 15 */\n#define  EXTI_PR_PR16                        ((uint32_t)0x00010000)        /*!< Pending bit 16 */\n#define  EXTI_PR_PR17                        ((uint32_t)0x00020000)        /*!< Pending bit 17 */\n#define  EXTI_PR_PR19                        ((uint32_t)0x00080000)        /*!< Pending bit 19 */\n\n/******************************************************************************/\n/*                                                                            */\n/*                      FLASH and Option Bytes Registers                      */\n/*                                                                            */\n/******************************************************************************/\n\n/*******************  Bit definition for FLASH_ACR register  ******************/\n#define  FLASH_ACR_LATENCY                   ((uint32_t)0x00000001)        /*!< LATENCY bit (Latency) */\n#define  FLASH_ACR_PRFTEN                    ((uint32_t)0x00000002)        /*!< Prefetch Buffer Enable */\n#define  FLASH_ACR_SLEEP_PD                  ((uint32_t)0x00000008)        /*!< Flash mode during sleep mode */\n#define  FLASH_ACR_RUN_PD                    ((uint32_t)0x00000010)        /*!< Flash mode during RUN mode */\n#define  FLASH_ACR_DISAB_BUF                 ((uint32_t)0x00000020)        /*!< Disable Buffer */\n#define  FLASH_ACR_PRE_READ                  ((uint32_t)0x00000040)        /*!< Pre-read data address */\n\n/*******************  Bit definition for FLASH_PECR register  ******************/\n#define FLASH_PECR_PELOCK                    ((uint32_t)0x00000001)        /*!< FLASH_PECR and Flash data Lock */\n#define FLASH_PECR_PRGLOCK                   ((uint32_t)0x00000002)        /*!< Program matrix Lock */\n#define FLASH_PECR_OPTLOCK                   ((uint32_t)0x00000004)        /*!< Option byte matrix Lock */\n#define FLASH_PECR_PROG                      ((uint32_t)0x00000008)        /*!< Program matrix selection */\n#define FLASH_PECR_DATA                      ((uint32_t)0x00000010)        /*!< Data matrix selection */\n#define FLASH_PECR_FTDW                      ((uint32_t)0x00000100)        /*!< Fixed Time Data write for Word/Half Word/Byte programming */\n#define FLASH_PECR_ERASE                     ((uint32_t)0x00000200)        /*!< Page erasing mode */\n#define FLASH_PECR_FPRG                      ((uint32_t)0x00000400)        /*!< Fast Page/Half Page programming mode */\n#define FLASH_PECR_EOPIE                     ((uint32_t)0x00010000)        /*!< End of programming interrupt */\n#define FLASH_PECR_ERRIE                     ((uint32_t)0x00020000)        /*!< Error interrupt */\n#define FLASH_PECR_OBL_LAUNCH                ((uint32_t)0x00040000)        /*!< Launch the option byte loading */\n#define FLASH_PECR_HALF_ARRAY                ((uint32_t)0x00080000)        /*!< Half array mode */\n\n/******************  Bit definition for FLASH_PDKEYR register  ******************/\n#define  FLASH_PDKEYR_PDKEYR                 ((uint32_t)0xFFFFFFFF)       /*!< FLASH_PEC and data matrix Key */\n\n/******************  Bit definition for FLASH_PEKEYR register  ******************/\n#define  FLASH_PEKEYR_PEKEYR                 ((uint32_t)0xFFFFFFFF)       /*!< FLASH_PEC and data matrix Key */\n\n/******************  Bit definition for FLASH_PRGKEYR register  ******************/\n#define  FLASH_PRGKEYR_PRGKEYR               ((uint32_t)0xFFFFFFFF)        /*!< Program matrix Key */\n\n/******************  Bit definition for FLASH_OPTKEYR register  ******************/\n#define  FLASH_OPTKEYR_OPTKEYR               ((uint32_t)0xFFFFFFFF)        /*!< Option bytes matrix Key */\n\n/******************  Bit definition for FLASH_SR register  *******************/\n#define  FLASH_SR_BSY                        ((uint32_t)0x00000001)        /*!< Busy */\n#define  FLASH_SR_EOP                        ((uint32_t)0x00000002)        /*!< End Of Programming*/\n#define  FLASH_SR_ENHV                       ((uint32_t)0x00000004)        /*!< End of high voltage */\n#define  FLASH_SR_READY                      ((uint32_t)0x00000008)        /*!< Flash ready after low power mode */\n\n#define  FLASH_SR_WRPERR                     ((uint32_t)0x00000100)        /*!< Write protection error */\n#define  FLASH_SR_PGAERR                     ((uint32_t)0x00000200)        /*!< Programming Alignment Error */\n#define  FLASH_SR_SIZERR                     ((uint32_t)0x00000400)        /*!< Size error */\n#define  FLASH_SR_OPTVERR                    ((uint32_t)0x00000800)        /*!< Option Valid error */\n#define  FLASH_SR_RDERR                      ((uint32_t)0x00002000)        /*!< Read protected error */\n#define  FLASH_SR_NOTZEROERR                 ((uint32_t)0x00010000)        /*!< Not Zero error */\n#define  FLASH_SR_FWWER                      ((uint32_t)0x00010000)        /*!<  */\n\n/******************  Bit definition for FLASH_OBR register  *******************/\n#define  FLASH_OBR_RDPRT                     ((uint32_t)0x000000AA)        /*!< Read Protection */\n#define  FLASH_OBR_SPRMOD                    ((uint32_t)0x00000100)        /*!< Selection of protection mode of WPR bits */\n#define  FLASH_OBR_BOR_LEV                   ((uint32_t)0x000F0000)        /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/\n\n/******************  Bit definition for FLASH_WRPR register  ******************/\n#define  FLASH_WRPR_WRP                      ((uint32_t)0x0000FFFF)        /*!< Write Protection bits */\n\n/******************************************************************************/\n/*                                                                            */\n/*                       General Purpose IOs (GPIO)                           */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for GPIO_MODER register  *****************/\n#define GPIO_MODER_MODE0          ((uint32_t)0x00000003)\n#define GPIO_MODER_MODE0_0        ((uint32_t)0x00000001)\n#define GPIO_MODER_MODE0_1        ((uint32_t)0x00000002)\n#define GPIO_MODER_MODE1          ((uint32_t)0x0000000C)\n#define GPIO_MODER_MODE1_0        ((uint32_t)0x00000004)\n#define GPIO_MODER_MODE1_1        ((uint32_t)0x00000008)\n#define GPIO_MODER_MODE2          ((uint32_t)0x00000030)\n#define GPIO_MODER_MODE2_0        ((uint32_t)0x00000010)\n#define GPIO_MODER_MODE2_1        ((uint32_t)0x00000020)\n#define GPIO_MODER_MODE3          ((uint32_t)0x000000C0)\n#define GPIO_MODER_MODE3_0        ((uint32_t)0x00000040)\n#define GPIO_MODER_MODE3_1        ((uint32_t)0x00000080)\n#define GPIO_MODER_MODE4          ((uint32_t)0x00000300)\n#define GPIO_MODER_MODE4_0        ((uint32_t)0x00000100)\n#define GPIO_MODER_MODE4_1        ((uint32_t)0x00000200)\n#define GPIO_MODER_MODE5          ((uint32_t)0x00000C00)\n#define GPIO_MODER_MODE5_0        ((uint32_t)0x00000400)\n#define GPIO_MODER_MODE5_1        ((uint32_t)0x00000800)\n#define GPIO_MODER_MODE6          ((uint32_t)0x00003000)\n#define GPIO_MODER_MODE6_0        ((uint32_t)0x00001000)\n#define GPIO_MODER_MODE6_1        ((uint32_t)0x00002000)\n#define GPIO_MODER_MODE7          ((uint32_t)0x0000C000)\n#define GPIO_MODER_MODE7_0        ((uint32_t)0x00004000)\n#define GPIO_MODER_MODE7_1        ((uint32_t)0x00008000)\n#define GPIO_MODER_MODE8          ((uint32_t)0x00030000)\n#define GPIO_MODER_MODE8_0        ((uint32_t)0x00010000)\n#define GPIO_MODER_MODE8_1        ((uint32_t)0x00020000)\n#define GPIO_MODER_MODE9          ((uint32_t)0x000C0000)\n#define GPIO_MODER_MODE9_0        ((uint32_t)0x00040000)\n#define GPIO_MODER_MODE9_1        ((uint32_t)0x00080000)\n#define GPIO_MODER_MODE10         ((uint32_t)0x00300000)\n#define GPIO_MODER_MODE10_0       ((uint32_t)0x00100000)\n#define GPIO_MODER_MODE10_1       ((uint32_t)0x00200000)\n#define GPIO_MODER_MODE11         ((uint32_t)0x00C00000)\n#define GPIO_MODER_MODE11_0       ((uint32_t)0x00400000)\n#define GPIO_MODER_MODE11_1       ((uint32_t)0x00800000)\n#define GPIO_MODER_MODE12         ((uint32_t)0x03000000)\n#define GPIO_MODER_MODE12_0       ((uint32_t)0x01000000)\n#define GPIO_MODER_MODE12_1       ((uint32_t)0x02000000)\n#define GPIO_MODER_MODE13         ((uint32_t)0x0C000000)\n#define GPIO_MODER_MODE13_0       ((uint32_t)0x04000000)\n#define GPIO_MODER_MODE13_1       ((uint32_t)0x08000000)\n#define GPIO_MODER_MODE14         ((uint32_t)0x30000000)\n#define GPIO_MODER_MODE14_0       ((uint32_t)0x10000000)\n#define GPIO_MODER_MODE14_1       ((uint32_t)0x20000000)\n#define GPIO_MODER_MODE15         ((uint32_t)0xC0000000)\n#define GPIO_MODER_MODE15_0       ((uint32_t)0x40000000)\n#define GPIO_MODER_MODE15_1       ((uint32_t)0x80000000)\n\n/******************  Bit definition for GPIO_OTYPER register  *****************/\n#define GPIO_OTYPER_OT_0           ((uint32_t)0x00000001)\n#define GPIO_OTYPER_OT_1           ((uint32_t)0x00000002)\n#define GPIO_OTYPER_OT_2           ((uint32_t)0x00000004)\n#define GPIO_OTYPER_OT_3           ((uint32_t)0x00000008)\n#define GPIO_OTYPER_OT_4           ((uint32_t)0x00000010)\n#define GPIO_OTYPER_OT_5           ((uint32_t)0x00000020)\n#define GPIO_OTYPER_OT_6           ((uint32_t)0x00000040)\n#define GPIO_OTYPER_OT_7           ((uint32_t)0x00000080)\n#define GPIO_OTYPER_OT_8           ((uint32_t)0x00000100)\n#define GPIO_OTYPER_OT_9           ((uint32_t)0x00000200)\n#define GPIO_OTYPER_OT_10          ((uint32_t)0x00000400)\n#define GPIO_OTYPER_OT_11          ((uint32_t)0x00000800)\n#define GPIO_OTYPER_OT_12          ((uint32_t)0x00001000)\n#define GPIO_OTYPER_OT_13          ((uint32_t)0x00002000)\n#define GPIO_OTYPER_OT_14          ((uint32_t)0x00004000)\n#define GPIO_OTYPER_OT_15          ((uint32_t)0x00008000)\n\n/****************  Bit definition for GPIO_OSPEEDR register  ******************/\n#define GPIO_OSPEEDER_OSPEED0     ((uint32_t)0x00000003)\n#define GPIO_OSPEEDER_OSPEED0_0   ((uint32_t)0x00000001)\n#define GPIO_OSPEEDER_OSPEED0_1   ((uint32_t)0x00000002)\n#define GPIO_OSPEEDER_OSPEED1     ((uint32_t)0x0000000C)\n#define GPIO_OSPEEDER_OSPEED1_0   ((uint32_t)0x00000004)\n#define GPIO_OSPEEDER_OSPEED1_1   ((uint32_t)0x00000008)\n#define GPIO_OSPEEDER_OSPEED2     ((uint32_t)0x00000030)\n#define GPIO_OSPEEDER_OSPEED2_0   ((uint32_t)0x00000010)\n#define GPIO_OSPEEDER_OSPEED2_1   ((uint32_t)0x00000020)\n#define GPIO_OSPEEDER_OSPEED3     ((uint32_t)0x000000C0)\n#define GPIO_OSPEEDER_OSPEED3_0   ((uint32_t)0x00000040)\n#define GPIO_OSPEEDER_OSPEED3_1   ((uint32_t)0x00000080)\n#define GPIO_OSPEEDER_OSPEED4     ((uint32_t)0x00000300)\n#define GPIO_OSPEEDER_OSPEED4_0   ((uint32_t)0x00000100)\n#define GPIO_OSPEEDER_OSPEED4_1   ((uint32_t)0x00000200)\n#define GPIO_OSPEEDER_OSPEED5     ((uint32_t)0x00000C00)\n#define GPIO_OSPEEDER_OSPEED5_0   ((uint32_t)0x00000400)\n#define GPIO_OSPEEDER_OSPEED5_1   ((uint32_t)0x00000800)\n#define GPIO_OSPEEDER_OSPEED6     ((uint32_t)0x00003000)\n#define GPIO_OSPEEDER_OSPEED6_0   ((uint32_t)0x00001000)\n#define GPIO_OSPEEDER_OSPEED6_1   ((uint32_t)0x00002000)\n#define GPIO_OSPEEDER_OSPEED7     ((uint32_t)0x0000C000)\n#define GPIO_OSPEEDER_OSPEED7_0   ((uint32_t)0x00004000)\n#define GPIO_OSPEEDER_OSPEED7_1   ((uint32_t)0x00008000)\n#define GPIO_OSPEEDER_OSPEED8     ((uint32_t)0x00030000)\n#define GPIO_OSPEEDER_OSPEED8_0   ((uint32_t)0x00010000)\n#define GPIO_OSPEEDER_OSPEED8_1   ((uint32_t)0x00020000)\n#define GPIO_OSPEEDER_OSPEED9     ((uint32_t)0x000C0000)\n#define GPIO_OSPEEDER_OSPEED9_0   ((uint32_t)0x00040000)\n#define GPIO_OSPEEDER_OSPEED9_1   ((uint32_t)0x00080000)\n#define GPIO_OSPEEDER_OSPEED10    ((uint32_t)0x00300000)\n#define GPIO_OSPEEDER_OSPEED10_0  ((uint32_t)0x00100000)\n#define GPIO_OSPEEDER_OSPEED10_1  ((uint32_t)0x00200000)\n#define GPIO_OSPEEDER_OSPEED11    ((uint32_t)0x00C00000)\n#define GPIO_OSPEEDER_OSPEED11_0  ((uint32_t)0x00400000)\n#define GPIO_OSPEEDER_OSPEED11_1  ((uint32_t)0x00800000)\n#define GPIO_OSPEEDER_OSPEED12    ((uint32_t)0x03000000)\n#define GPIO_OSPEEDER_OSPEED12_0  ((uint32_t)0x01000000)\n#define GPIO_OSPEEDER_OSPEED12_1  ((uint32_t)0x02000000)\n#define GPIO_OSPEEDER_OSPEED13    ((uint32_t)0x0C000000)\n#define GPIO_OSPEEDER_OSPEED13_0  ((uint32_t)0x04000000)\n#define GPIO_OSPEEDER_OSPEED13_1  ((uint32_t)0x08000000)\n#define GPIO_OSPEEDER_OSPEED14    ((uint32_t)0x30000000)\n#define GPIO_OSPEEDER_OSPEED14_0  ((uint32_t)0x10000000)\n#define GPIO_OSPEEDER_OSPEED14_1  ((uint32_t)0x20000000)\n#define GPIO_OSPEEDER_OSPEED15    ((uint32_t)0xC0000000)\n#define GPIO_OSPEEDER_OSPEED15_0  ((uint32_t)0x40000000)\n#define GPIO_OSPEEDER_OSPEED15_1  ((uint32_t)0x80000000)\n\n/*******************  Bit definition for GPIO_PUPDR register ******************/\n#define GPIO_PUPDR_PUPD0          ((uint32_t)0x00000003)\n#define GPIO_PUPDR_PUPD0_0        ((uint32_t)0x00000001)\n#define GPIO_PUPDR_PUPD0_1        ((uint32_t)0x00000002)\n#define GPIO_PUPDR_PUPD1          ((uint32_t)0x0000000C)\n#define GPIO_PUPDR_PUPD1_0        ((uint32_t)0x00000004)\n#define GPIO_PUPDR_PUPD1_1        ((uint32_t)0x00000008)\n#define GPIO_PUPDR_PUPD2          ((uint32_t)0x00000030)\n#define GPIO_PUPDR_PUPD2_0        ((uint32_t)0x00000010)\n#define GPIO_PUPDR_PUPD2_1        ((uint32_t)0x00000020)\n#define GPIO_PUPDR_PUPD3          ((uint32_t)0x000000C0)\n#define GPIO_PUPDR_PUPD3_0        ((uint32_t)0x00000040)\n#define GPIO_PUPDR_PUPD3_1        ((uint32_t)0x00000080)\n#define GPIO_PUPDR_PUPD4          ((uint32_t)0x00000300)\n#define GPIO_PUPDR_PUPD4_0        ((uint32_t)0x00000100)\n#define GPIO_PUPDR_PUPD4_1        ((uint32_t)0x00000200)\n#define GPIO_PUPDR_PUPD5          ((uint32_t)0x00000C00)\n#define GPIO_PUPDR_PUPD5_0        ((uint32_t)0x00000400)\n#define GPIO_PUPDR_PUPD5_1        ((uint32_t)0x00000800)\n#define GPIO_PUPDR_PUPD6          ((uint32_t)0x00003000)\n#define GPIO_PUPDR_PUPD6_0        ((uint32_t)0x00001000)\n#define GPIO_PUPDR_PUPD6_1        ((uint32_t)0x00002000)\n#define GPIO_PUPDR_PUPD7          ((uint32_t)0x0000C000)\n#define GPIO_PUPDR_PUPD7_0        ((uint32_t)0x00004000)\n#define GPIO_PUPDR_PUPD7_1        ((uint32_t)0x00008000)\n#define GPIO_PUPDR_PUPD8          ((uint32_t)0x00030000)\n#define GPIO_PUPDR_PUPD8_0        ((uint32_t)0x00010000)\n#define GPIO_PUPDR_PUPD8_1        ((uint32_t)0x00020000)\n#define GPIO_PUPDR_PUPD9          ((uint32_t)0x000C0000)\n#define GPIO_PUPDR_PUPD9_0        ((uint32_t)0x00040000)\n#define GPIO_PUPDR_PUPD9_1        ((uint32_t)0x00080000)\n#define GPIO_PUPDR_PUPD10         ((uint32_t)0x00300000)\n#define GPIO_PUPDR_PUPD10_0       ((uint32_t)0x00100000)\n#define GPIO_PUPDR_PUPD10_1       ((uint32_t)0x00200000)\n#define GPIO_PUPDR_PUPD11         ((uint32_t)0x00C00000)\n#define GPIO_PUPDR_PUPD11_0       ((uint32_t)0x00400000)\n#define GPIO_PUPDR_PUPD11_1       ((uint32_t)0x00800000)\n#define GPIO_PUPDR_PUPD12         ((uint32_t)0x03000000)\n#define GPIO_PUPDR_PUPD12_0       ((uint32_t)0x01000000)\n#define GPIO_PUPDR_PUPD12_1       ((uint32_t)0x02000000)\n#define GPIO_PUPDR_PUPD13         ((uint32_t)0x0C000000)\n#define GPIO_PUPDR_PUPD13_0       ((uint32_t)0x04000000)\n#define GPIO_PUPDR_PUPD13_1       ((uint32_t)0x08000000)\n#define GPIO_PUPDR_PUPD14         ((uint32_t)0x30000000)\n#define GPIO_PUPDR_PUPD14_0       ((uint32_t)0x10000000)\n#define GPIO_PUPDR_PUPD14_1       ((uint32_t)0x20000000)\n#define GPIO_PUPDR_PUPD15         ((uint32_t)0xC0000000)\n#define GPIO_PUPDR_PUPD15_0       ((uint32_t)0x40000000)\n#define GPIO_PUPDR_PUPD15_1       ((uint32_t)0x80000000)\n\n/*******************  Bit definition for GPIO_IDR register  *******************/\n#define GPIO_IDR_ID0                 ((uint32_t)0x00000001)\n#define GPIO_IDR_ID1                 ((uint32_t)0x00000002)\n#define GPIO_IDR_ID2                 ((uint32_t)0x00000004)\n#define GPIO_IDR_ID3                 ((uint32_t)0x00000008)\n#define GPIO_IDR_ID4                 ((uint32_t)0x00000010)\n#define GPIO_IDR_ID5                 ((uint32_t)0x00000020)\n#define GPIO_IDR_ID6                 ((uint32_t)0x00000040)\n#define GPIO_IDR_ID7                 ((uint32_t)0x00000080)\n#define GPIO_IDR_ID8                 ((uint32_t)0x00000100)\n#define GPIO_IDR_ID9                 ((uint32_t)0x00000200)\n#define GPIO_IDR_ID10                ((uint32_t)0x00000400)\n#define GPIO_IDR_ID11                ((uint32_t)0x00000800)\n#define GPIO_IDR_ID12                ((uint32_t)0x00001000)\n#define GPIO_IDR_ID13                ((uint32_t)0x00002000)\n#define GPIO_IDR_ID14                ((uint32_t)0x00004000)\n#define GPIO_IDR_ID15                ((uint32_t)0x00008000)\n\n/******************  Bit definition for GPIO_ODR register  ********************/\n#define GPIO_ODR_OD0                 ((uint32_t)0x00000001)\n#define GPIO_ODR_OD1                 ((uint32_t)0x00000002)\n#define GPIO_ODR_OD2                 ((uint32_t)0x00000004)\n#define GPIO_ODR_OD3                 ((uint32_t)0x00000008)\n#define GPIO_ODR_OD4                 ((uint32_t)0x00000010)\n#define GPIO_ODR_OD5                 ((uint32_t)0x00000020)\n#define GPIO_ODR_OD6                 ((uint32_t)0x00000040)\n#define GPIO_ODR_OD7                 ((uint32_t)0x00000080)\n#define GPIO_ODR_OD8                 ((uint32_t)0x00000100)\n#define GPIO_ODR_OD9                 ((uint32_t)0x00000200)\n#define GPIO_ODR_OD10                ((uint32_t)0x00000400)\n#define GPIO_ODR_OD11                ((uint32_t)0x00000800)\n#define GPIO_ODR_OD12                ((uint32_t)0x00001000)\n#define GPIO_ODR_OD13                ((uint32_t)0x00002000)\n#define GPIO_ODR_OD14                ((uint32_t)0x00004000)\n#define GPIO_ODR_OD15                ((uint32_t)0x00008000)\n\n/****************** Bit definition for GPIO_BSRR register  ********************/\n#define GPIO_BSRR_BS_0             ((uint32_t)0x00000001)\n#define GPIO_BSRR_BS_1             ((uint32_t)0x00000002)\n#define GPIO_BSRR_BS_2             ((uint32_t)0x00000004)\n#define GPIO_BSRR_BS_3             ((uint32_t)0x00000008)\n#define GPIO_BSRR_BS_4             ((uint32_t)0x00000010)\n#define GPIO_BSRR_BS_5             ((uint32_t)0x00000020)\n#define GPIO_BSRR_BS_6             ((uint32_t)0x00000040)\n#define GPIO_BSRR_BS_7             ((uint32_t)0x00000080)\n#define GPIO_BSRR_BS_8             ((uint32_t)0x00000100)\n#define GPIO_BSRR_BS_9             ((uint32_t)0x00000200)\n#define GPIO_BSRR_BS_10            ((uint32_t)0x00000400)\n#define GPIO_BSRR_BS_11            ((uint32_t)0x00000800)\n#define GPIO_BSRR_BS_12            ((uint32_t)0x00001000)\n#define GPIO_BSRR_BS_13            ((uint32_t)0x00002000)\n#define GPIO_BSRR_BS_14            ((uint32_t)0x00004000)\n#define GPIO_BSRR_BS_15            ((uint32_t)0x00008000)\n#define GPIO_BSRR_BR_0             ((uint32_t)0x00010000)\n#define GPIO_BSRR_BR_1             ((uint32_t)0x00020000)\n#define GPIO_BSRR_BR_2             ((uint32_t)0x00040000)\n#define GPIO_BSRR_BR_3             ((uint32_t)0x00080000)\n#define GPIO_BSRR_BR_4             ((uint32_t)0x00100000)\n#define GPIO_BSRR_BR_5             ((uint32_t)0x00200000)\n#define GPIO_BSRR_BR_6             ((uint32_t)0x00400000)\n#define GPIO_BSRR_BR_7             ((uint32_t)0x00800000)\n#define GPIO_BSRR_BR_8             ((uint32_t)0x01000000)\n#define GPIO_BSRR_BR_9             ((uint32_t)0x02000000)\n#define GPIO_BSRR_BR_10            ((uint32_t)0x04000000)\n#define GPIO_BSRR_BR_11            ((uint32_t)0x08000000)\n#define GPIO_BSRR_BR_12            ((uint32_t)0x10000000)\n#define GPIO_BSRR_BR_13            ((uint32_t)0x20000000)\n#define GPIO_BSRR_BR_14            ((uint32_t)0x40000000)\n#define GPIO_BSRR_BR_15            ((uint32_t)0x80000000)\n\n/****************** Bit definition for GPIO_LCKR register  ********************/\n#define GPIO_LCKR_LCK0             ((uint32_t)0x00000001)\n#define GPIO_LCKR_LCK1             ((uint32_t)0x00000002)\n#define GPIO_LCKR_LCK2             ((uint32_t)0x00000004)\n#define GPIO_LCKR_LCK3             ((uint32_t)0x00000008)\n#define GPIO_LCKR_LCK4             ((uint32_t)0x00000010)\n#define GPIO_LCKR_LCK5             ((uint32_t)0x00000020)\n#define GPIO_LCKR_LCK6             ((uint32_t)0x00000040)\n#define GPIO_LCKR_LCK7             ((uint32_t)0x00000080)\n#define GPIO_LCKR_LCK8             ((uint32_t)0x00000100)\n#define GPIO_LCKR_LCK9             ((uint32_t)0x00000200)\n#define GPIO_LCKR_LCK10            ((uint32_t)0x00000400)\n#define GPIO_LCKR_LCK11            ((uint32_t)0x00000800)\n#define GPIO_LCKR_LCK12            ((uint32_t)0x00001000)\n#define GPIO_LCKR_LCK13            ((uint32_t)0x00002000)\n#define GPIO_LCKR_LCK14            ((uint32_t)0x00004000)\n#define GPIO_LCKR_LCK15            ((uint32_t)0x00008000)\n#define GPIO_LCKR_LCKK             ((uint32_t)0x00010000)\n\n/****************** Bit definition for GPIO_BRR register  *********************/\n#define GPIO_BRR_BR_0              ((uint32_t)0x00000001)\n#define GPIO_BRR_BR_1              ((uint32_t)0x00000002)\n#define GPIO_BRR_BR_2              ((uint32_t)0x00000004)\n#define GPIO_BRR_BR_3              ((uint32_t)0x00000008)\n#define GPIO_BRR_BR_4              ((uint32_t)0x00000010)\n#define GPIO_BRR_BR_5              ((uint32_t)0x00000020)\n#define GPIO_BRR_BR_6              ((uint32_t)0x00000040)\n#define GPIO_BRR_BR_7              ((uint32_t)0x00000080)\n#define GPIO_BRR_BR_8              ((uint32_t)0x00000100)\n#define GPIO_BRR_BR_9              ((uint32_t)0x00000200)\n#define GPIO_BRR_BR_10             ((uint32_t)0x00000400)\n#define GPIO_BRR_BR_11             ((uint32_t)0x00000800)\n#define GPIO_BRR_BR_12             ((uint32_t)0x00001000)\n#define GPIO_BRR_BR_13             ((uint32_t)0x00002000)\n#define GPIO_BRR_BR_14             ((uint32_t)0x00004000)\n#define GPIO_BRR_BR_15             ((uint32_t)0x00008000)\n\n/******************************************************************************/\n/*                                                                            */\n/*                   Inter-integrated Circuit Interface (I2C)                 */\n/*                                                                            */\n/******************************************************************************/\n\n/*******************  Bit definition for I2C_CR1 register  *******************/\n#define  I2C_CR1_PE                          ((uint32_t)0x00000001)        /*!< Peripheral enable */\n#define  I2C_CR1_TXIE                        ((uint32_t)0x00000002)        /*!< TX interrupt enable */\n#define  I2C_CR1_RXIE                        ((uint32_t)0x00000004)        /*!< RX interrupt enable */\n#define  I2C_CR1_ADDRIE                      ((uint32_t)0x00000008)        /*!< Address match interrupt enable */\n#define  I2C_CR1_NACKIE                      ((uint32_t)0x00000010)        /*!< NACK received interrupt enable */\n#define  I2C_CR1_STOPIE                      ((uint32_t)0x00000020)        /*!< STOP detection interrupt enable */\n#define  I2C_CR1_TCIE                        ((uint32_t)0x00000040)        /*!< Transfer complete interrupt enable */\n#define  I2C_CR1_ERRIE                       ((uint32_t)0x00000080)        /*!< Errors interrupt enable */\n#define  I2C_CR1_DFN                         ((uint32_t)0x00000F00)        /*!< Digital noise filter */\n#define  I2C_CR1_ANFOFF                      ((uint32_t)0x00001000)        /*!< Analog noise filter OFF */\n#define  I2C_CR1_TXDMAEN                     ((uint32_t)0x00004000)        /*!< DMA transmission requests enable */\n#define  I2C_CR1_RXDMAEN                     ((uint32_t)0x00008000)        /*!< DMA reception requests enable */\n#define  I2C_CR1_SBC                         ((uint32_t)0x00010000)        /*!< Slave byte control */\n#define  I2C_CR1_NOSTRETCH                   ((uint32_t)0x00020000)        /*!< Clock stretching disable */\n#define  I2C_CR1_WUPEN                       ((uint32_t)0x00040000)        /*!< Wakeup from STOP enable */\n#define  I2C_CR1_GCEN                        ((uint32_t)0x00080000)        /*!< General call enable */\n#define  I2C_CR1_SMBHEN                      ((uint32_t)0x00100000)        /*!< SMBus host address enable */\n#define  I2C_CR1_SMBDEN                      ((uint32_t)0x00200000)        /*!< SMBus device default address enable */\n#define  I2C_CR1_ALERTEN                     ((uint32_t)0x00400000)        /*!< SMBus alert enable */\n#define  I2C_CR1_PECEN                       ((uint32_t)0x00800000)        /*!< PEC enable */\n\n/******************  Bit definition for I2C_CR2 register  ********************/\n#define  I2C_CR2_SADD                        ((uint32_t)0x000003FF)        /*!< Slave address (master mode) */\n#define  I2C_CR2_RD_WRN                      ((uint32_t)0x00000400)        /*!< Transfer direction (master mode) */\n#define  I2C_CR2_ADD10                       ((uint32_t)0x00000800)        /*!< 10-bit addressing mode (master mode) */\n#define  I2C_CR2_HEAD10R                     ((uint32_t)0x00001000)        /*!< 10-bit address header only read direction (master mode) */\n#define  I2C_CR2_START                       ((uint32_t)0x00002000)        /*!< START generation */\n#define  I2C_CR2_STOP                        ((uint32_t)0x00004000)        /*!< STOP generation (master mode) */\n#define  I2C_CR2_NACK                        ((uint32_t)0x00008000)        /*!< NACK generation (slave mode) */\n#define  I2C_CR2_NBYTES                      ((uint32_t)0x00FF0000)        /*!< Number of bytes */\n#define  I2C_CR2_RELOAD                      ((uint32_t)0x01000000)        /*!< NBYTES reload mode */\n#define  I2C_CR2_AUTOEND                     ((uint32_t)0x02000000)        /*!< Automatic end mode (master mode) */\n#define  I2C_CR2_PECBYTE                     ((uint32_t)0x04000000)        /*!< Packet error checking byte */\n\n/*******************  Bit definition for I2C_OAR1 register  ******************/\n#define  I2C_OAR1_OA1                        ((uint32_t)0x000003FF)        /*!< Interface own address 1 */\n#define  I2C_OAR1_OA1MODE                    ((uint32_t)0x00000400)        /*!< Own address 1 10-bit mode */\n#define  I2C_OAR1_OA1EN                      ((uint32_t)0x00008000)        /*!< Own address 1 enable */\n\n/*******************  Bit definition for I2C_OAR2 register  ******************/\n#define  I2C_OAR2_OA2                        ((uint32_t)0x000000FE)        /*!< Interface own address 2 */\n#define  I2C_OAR2_OA2MSK                     ((uint32_t)0x00000700)        /*!< Own address 2 masks */\n#define  I2C_OAR2_OA2EN                      ((uint32_t)0x00008000)        /*!< Own address 2 enable */\n\n/*******************  Bit definition for I2C_TIMINGR register *******************/\n#define  I2C_TIMINGR_SCLL                    ((uint32_t)0x000000FF)        /*!< SCL low period (master mode) */\n#define  I2C_TIMINGR_SCLH                    ((uint32_t)0x0000FF00)        /*!< SCL high period (master mode) */\n#define  I2C_TIMINGR_SDADEL                  ((uint32_t)0x000F0000)        /*!< Data hold time */\n#define  I2C_TIMINGR_SCLDEL                  ((uint32_t)0x00F00000)        /*!< Data setup time */\n#define  I2C_TIMINGR_PRESC                   ((uint32_t)0xF0000000)        /*!< Timings prescaler */\n\n/******************* Bit definition for I2C_TIMEOUTR register *******************/\n#define  I2C_TIMEOUTR_TIMEOUTA               ((uint32_t)0x00000FFF)        /*!< Bus timeout A */\n#define  I2C_TIMEOUTR_TIDLE                  ((uint32_t)0x00001000)        /*!< Idle clock timeout detection */\n#define  I2C_TIMEOUTR_TIMOUTEN               ((uint32_t)0x00008000)        /*!< Clock timeout enable */\n#define  I2C_TIMEOUTR_TIMEOUTB               ((uint32_t)0x0FFF0000)        /*!< Bus timeout B*/\n#define  I2C_TIMEOUTR_TEXTEN                 ((uint32_t)0x80000000)        /*!< Extended clock timeout enable */\n\n/******************  Bit definition for I2C_ISR register  *********************/\n#define  I2C_ISR_TXE                         ((uint32_t)0x00000001)        /*!< Transmit data register empty */\n#define  I2C_ISR_TXIS                        ((uint32_t)0x00000002)        /*!< Transmit interrupt status */\n#define  I2C_ISR_RXNE                        ((uint32_t)0x00000004)        /*!< Receive data register not empty */\n#define  I2C_ISR_ADDR                        ((uint32_t)0x00000008)        /*!< Address matched (slave mode)*/\n#define  I2C_ISR_NACKF                       ((uint32_t)0x00000010)        /*!< NACK received flag */\n#define  I2C_ISR_STOPF                       ((uint32_t)0x00000020)        /*!< STOP detection flag */\n#define  I2C_ISR_TC                          ((uint32_t)0x00000040)        /*!< Transfer complete (master mode) */\n#define  I2C_ISR_TCR                         ((uint32_t)0x00000080)        /*!< Transfer complete reload */\n#define  I2C_ISR_BERR                        ((uint32_t)0x00000100)        /*!< Bus error */\n#define  I2C_ISR_ARLO                        ((uint32_t)0x00000200)        /*!< Arbitration lost */\n#define  I2C_ISR_OVR                         ((uint32_t)0x00000400)        /*!< Overrun/Underrun */\n#define  I2C_ISR_PECERR                      ((uint32_t)0x00000800)        /*!< PEC error in reception */\n#define  I2C_ISR_TIMEOUT                     ((uint32_t)0x00001000)        /*!< Timeout or Tlow detection flag */\n#define  I2C_ISR_ALERT                       ((uint32_t)0x00002000)        /*!< SMBus alert */\n#define  I2C_ISR_BUSY                        ((uint32_t)0x00008000)        /*!< Bus busy */\n#define  I2C_ISR_DIR                         ((uint32_t)0x00010000)        /*!< Transfer direction (slave mode) */\n#define  I2C_ISR_ADDCODE                     ((uint32_t)0x00FE0000)        /*!< Address match code (slave mode) */\n\n/******************  Bit definition for I2C_ICR register  *********************/\n#define  I2C_ICR_ADDRCF                      ((uint32_t)0x00000008)        /*!< Address matched clear flag */\n#define  I2C_ICR_NACKCF                      ((uint32_t)0x00000010)        /*!< NACK clear flag */\n#define  I2C_ICR_STOPCF                      ((uint32_t)0x00000020)        /*!< STOP detection clear flag */\n#define  I2C_ICR_BERRCF                      ((uint32_t)0x00000100)        /*!< Bus error clear flag */\n#define  I2C_ICR_ARLOCF                      ((uint32_t)0x00000200)        /*!< Arbitration lost clear flag */\n#define  I2C_ICR_OVRCF                       ((uint32_t)0x00000400)        /*!< Overrun/Underrun clear flag */\n#define  I2C_ICR_PECCF                       ((uint32_t)0x00000800)        /*!< PAC error clear flag */\n#define  I2C_ICR_TIMOUTCF                    ((uint32_t)0x00001000)        /*!< Timeout clear flag */\n#define  I2C_ICR_ALERTCF                     ((uint32_t)0x00002000)        /*!< Alert clear flag */\n\n/******************  Bit definition for I2C_PECR register  *********************/\n#define  I2C_PECR_PEC                        ((uint32_t)0x000000FF)       /*!< PEC register */\n\n/******************  Bit definition for I2C_RXDR register  *********************/\n#define  I2C_RXDR_RXDATA                     ((uint32_t)0x000000FF)        /*!< 8-bit receive data */\n\n/******************  Bit definition for I2C_TXDR register  *********************/\n#define  I2C_TXDR_TXDATA                     ((uint32_t)0x000000FF)        /*!< 8-bit transmit data */\n\n/******************************************************************************/\n/*                                                                            */\n/*                        Independent WATCHDOG (IWDG)                         */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for IWDG_KR register  ********************/\n#define  IWDG_KR_KEY                         ((uint16_t)0xFFFF)            /*!< Key value (write only, read 0000h) */\n\n/*******************  Bit definition for IWDG_PR register  ********************/\n#define  IWDG_PR_PR                          ((uint8_t)0x07)               /*!< PR[2:0] (Prescaler divider) */\n#define  IWDG_PR_PR_0                        ((uint8_t)0x01)               /*!< Bit 0 */\n#define  IWDG_PR_PR_1                        ((uint8_t)0x02)               /*!< Bit 1 */\n#define  IWDG_PR_PR_2                        ((uint8_t)0x04)               /*!< Bit 2 */\n\n/*******************  Bit definition for IWDG_RLR register  *******************/\n#define  IWDG_RLR_RL                         ((uint16_t)0x0FFF)            /*!< Watchdog counter reload value */\n\n/*******************  Bit definition for IWDG_SR register  ********************/\n#define  IWDG_SR_PVU                         ((uint8_t)0x01)               /*!< Watchdog prescaler value update */\n#define  IWDG_SR_RVU                         ((uint8_t)0x02)               /*!< Watchdog counter reload value update */\n#define  IWDG_SR_WVU                         ((uint8_t)0x04)               /*!< Watchdog counter window value update */\n\n/*******************  Bit definition for IWDG_KR register  ********************/\n#define  IWDG_WINR_WIN                         ((uint16_t)0x0FFF)            /*!< Watchdog counter window value */\n\n/******************************************************************************/\n/*                                                                            */\n/*                          LCD Controller (LCD)                              */\n/*                                                                            */\n/******************************************************************************/\n\n/*******************  Bit definition for LCD_CR register  *********************/\n#define LCD_CR_LCDEN               ((uint32_t)0x00000001)     /*!< LCD Enable Bit */\n#define LCD_CR_VSEL                ((uint32_t)0x00000002)     /*!< Voltage source selector Bit */\n\n#define LCD_CR_DUTY                ((uint32_t)0x0000001C)     /*!< DUTY[2:0] bits (Duty selector) */\n#define LCD_CR_DUTY_0              ((uint32_t)0x00000004)     /*!< Duty selector Bit 0 */\n#define LCD_CR_DUTY_1              ((uint32_t)0x00000008)     /*!< Duty selector Bit 1 */\n#define LCD_CR_DUTY_2              ((uint32_t)0x00000010)     /*!< Duty selector Bit 2 */\n\n#define LCD_CR_BIAS                ((uint32_t)0x00000060)     /*!< BIAS[1:0] bits (Bias selector) */\n#define LCD_CR_BIAS_0              ((uint32_t)0x00000020)     /*!< Bias selector Bit 0 */\n#define LCD_CR_BIAS_1              ((uint32_t)0x00000040)     /*!< Bias selector Bit 1 */\n\n#define LCD_CR_MUX_SEG             ((uint32_t)0x00000080)     /*!< Mux Segment Enable Bit */\n\n/*******************  Bit definition for LCD_FCR register  ********************/\n#define LCD_FCR_HD                 ((uint32_t)0x00000001)     /*!< High Drive Enable Bit */\n#define LCD_FCR_SOFIE              ((uint32_t)0x00000002)     /*!< Start of Frame Interrupt Enable Bit */\n#define LCD_FCR_UDDIE              ((uint32_t)0x00000008)     /*!< Update Display Done Interrupt Enable Bit */\n\n#define LCD_FCR_PON                ((uint32_t)0x00000070)     /*!< PON[2:0] bits (Puls ON Duration) */\n#define LCD_FCR_PON_0              ((uint32_t)0x00000010)     /*!< Bit 0 */\n#define LCD_FCR_PON_1              ((uint32_t)0x00000020)     /*!< Bit 1 */\n#define LCD_FCR_PON_2              ((uint32_t)0x00000040)     /*!< Bit 2 */\n\n#define LCD_FCR_DEAD               ((uint32_t)0x00000380)     /*!< DEAD[2:0] bits (DEAD Time) */\n#define LCD_FCR_DEAD_0             ((uint32_t)0x00000080)     /*!< Bit 0 */\n#define LCD_FCR_DEAD_1             ((uint32_t)0x00000100)     /*!< Bit 1 */\n#define LCD_FCR_DEAD_2             ((uint32_t)0x00000200)     /*!< Bit 2 */\n\n#define LCD_FCR_CC                 ((uint32_t)0x00001C00)     /*!< CC[2:0] bits (Contrast Control) */\n#define LCD_FCR_CC_0               ((uint32_t)0x00000400)     /*!< Bit 0 */\n#define LCD_FCR_CC_1               ((uint32_t)0x00000800)     /*!< Bit 1 */\n#define LCD_FCR_CC_2               ((uint32_t)0x00001000)     /*!< Bit 2 */\n\n#define LCD_FCR_BLINKF             ((uint32_t)0x0000E000)     /*!< BLINKF[2:0] bits (Blink Frequency) */\n#define LCD_FCR_BLINKF_0           ((uint32_t)0x00002000)     /*!< Bit 0 */\n#define LCD_FCR_BLINKF_1           ((uint32_t)0x00004000)     /*!< Bit 1 */\n#define LCD_FCR_BLINKF_2           ((uint32_t)0x00008000)     /*!< Bit 2 */\n\n#define LCD_FCR_BLINK              ((uint32_t)0x00030000)     /*!< BLINK[1:0] bits (Blink Enable) */\n#define LCD_FCR_BLINK_0            ((uint32_t)0x00010000)     /*!< Bit 0 */\n#define LCD_FCR_BLINK_1            ((uint32_t)0x00020000)     /*!< Bit 1 */\n\n#define LCD_FCR_DIV                ((uint32_t)0x003C0000)     /*!< DIV[3:0] bits (Divider) */\n#define LCD_FCR_PS                 ((uint32_t)0x03C00000)     /*!< PS[3:0] bits (Prescaler) */\n\n/*******************  Bit definition for LCD_SR register  *********************/\n#define LCD_SR_ENS                 ((uint32_t)0x00000001)     /*!< LCD Enabled Bit */\n#define LCD_SR_SOF                 ((uint32_t)0x00000002)     /*!< Start Of Frame Flag Bit */\n#define LCD_SR_UDR                 ((uint32_t)0x00000004)     /*!< Update Display Request Bit */\n#define LCD_SR_UDD                 ((uint32_t)0x00000008)     /*!< Update Display Done Flag Bit */\n#define LCD_SR_RDY                 ((uint32_t)0x00000010)     /*!< Ready Flag Bit */\n#define LCD_SR_FCRSR               ((uint32_t)0x00000020)     /*!< LCD FCR Register Synchronization Flag Bit */\n\n/*******************  Bit definition for LCD_CLR register  ********************/\n#define LCD_CLR_SOFC               ((uint32_t)0x00000002)     /*!< Start Of Frame Flag Clear Bit */\n#define LCD_CLR_UDDC               ((uint32_t)0x00000008)     /*!< Update Display Done Flag Clear Bit */\n\n/*******************  Bit definition for LCD_RAM register  ********************/\n#define LCD_RAM_SEGMENT_DATA       ((uint32_t)0xFFFFFFFF)     /*!< Segment Data Bits */\n\n/******************************************************************************/\n/*                                                                            */\n/*                         Low Power Timer (LPTTIM)                           */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bit definition for LPTIM_ISR register  *******************/\n#define  LPTIM_ISR_CMPM                         ((uint32_t)0x00000001)            /*!< Compare match */\n#define  LPTIM_ISR_ARRM                         ((uint32_t)0x00000002)            /*!< Autoreload match */\n#define  LPTIM_ISR_EXTTRIG                      ((uint32_t)0x00000004)            /*!< External trigger edge event */\n#define  LPTIM_ISR_CMPOK                        ((uint32_t)0x00000008)            /*!< Compare register update OK */\n#define  LPTIM_ISR_ARROK                        ((uint32_t)0x00000010)            /*!< Autoreload register update OK */\n#define  LPTIM_ISR_UP                           ((uint32_t)0x00000020)            /*!< Counter direction change down to up */\n#define  LPTIM_ISR_DOWN                         ((uint32_t)0x00000040)            /*!< Counter direction change up to down */\n\n/******************  Bit definition for LPTIM_ICR register  *******************/\n#define  LPTIM_ICR_CMPMCF                       ((uint32_t)0x00000001)            /*!< Compare match Clear Flag */\n#define  LPTIM_ICR_ARRMCF                       ((uint32_t)0x00000002)            /*!< Autoreload match Clear Flag */\n#define  LPTIM_ICR_EXTTRIGCF                    ((uint32_t)0x00000004)            /*!< External trigger edge event Clear Flag */\n#define  LPTIM_ICR_CMPOKCF                      ((uint32_t)0x00000008)            /*!< Compare register update OK Clear Flag */\n#define  LPTIM_ICR_ARROKCF                      ((uint32_t)0x00000010)            /*!< Autoreload register update OK Clear Flag */\n#define  LPTIM_ICR_UPCF                         ((uint32_t)0x00000020)            /*!< Counter direction change down to up Clear Flag */\n#define  LPTIM_ICR_DOWNCF                       ((uint32_t)0x00000040)            /*!< Counter direction change up to down Clear Flag */\n\n/******************  Bit definition for LPTIM_IER register ********************/\n#define  LPTIM_IER_CMPMIE                       ((uint32_t)0x00000001)            /*!< Compare match Interrupt Enable */\n#define  LPTIM_IER_ARRMIE                       ((uint32_t)0x00000002)            /*!< Autoreload match Interrupt Enable */\n#define  LPTIM_IER_EXTTRIGIE                    ((uint32_t)0x00000004)            /*!< External trigger edge event Interrupt Enable */\n#define  LPTIM_IER_CMPOKIE                      ((uint32_t)0x00000008)            /*!< Compare register update OK Interrupt Enable */\n#define  LPTIM_IER_ARROKIE                      ((uint32_t)0x00000010)            /*!< Autoreload register update OK Interrupt Enable */\n#define  LPTIM_IER_UPIE                         ((uint32_t)0x00000020)            /*!< Counter direction change down to up Interrupt Enable */\n#define  LPTIM_IER_DOWNIE                       ((uint32_t)0x00000040)            /*!< Counter direction change up to down Interrupt Enable */\n\n/******************  Bit definition for LPTIM_CFGR register *******************/\n#define  LPTIM_CFGR_CKSEL                       ((uint32_t)0x00000001)             /*!< Clock selector */\n\n#define  LPTIM_CFGR_CKPOL                       ((uint32_t)0x00000006)             /*!< CKPOL[1:0] bits (Clock polarity) */\n#define  LPTIM_CFGR_CKPOL_0                     ((uint32_t)0x00000002)             /*!< Bit 0 */\n#define  LPTIM_CFGR_CKPOL_1                     ((uint32_t)0x00000004)             /*!< Bit 1 */\n\n#define  LPTIM_CFGR_CKFLT                       ((uint32_t)0x00000018)             /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */\n#define  LPTIM_CFGR_CKFLT_0                     ((uint32_t)0x00000008)             /*!< Bit 0 */\n#define  LPTIM_CFGR_CKFLT_1                     ((uint32_t)0x00000010)             /*!< Bit 1 */\n\n#define  LPTIM_CFGR_TRGFLT                      ((uint32_t)0x000000C0)             /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */\n#define  LPTIM_CFGR_TRGFLT_0                    ((uint32_t)0x00000040)             /*!< Bit 0 */\n#define  LPTIM_CFGR_TRGFLT_1                    ((uint32_t)0x00000080)             /*!< Bit 1 */\n\n#define  LPTIM_CFGR_PRESC                       ((uint32_t)0x00000E00)             /*!< PRESC[2:0] bits (Clock prescaler) */\n#define  LPTIM_CFGR_PRESC_0                     ((uint32_t)0x00000200)             /*!< Bit 0 */\n#define  LPTIM_CFGR_PRESC_1                     ((uint32_t)0x00000400)             /*!< Bit 1 */\n#define  LPTIM_CFGR_PRESC_2                     ((uint32_t)0x00000800)             /*!< Bit 2 */\n\n#define  LPTIM_CFGR_TRIGSEL                     ((uint32_t)0x0000E000)             /*!< TRIGSEL[2:0]] bits (Trigger selector) */\n#define  LPTIM_CFGR_TRIGSEL_0                   ((uint32_t)0x00002000)             /*!< Bit 0 */\n#define  LPTIM_CFGR_TRIGSEL_1                   ((uint32_t)0x00004000)             /*!< Bit 1 */\n#define  LPTIM_CFGR_TRIGSEL_2                   ((uint32_t)0x00008000)             /*!< Bit 2 */\n\n#define  LPTIM_CFGR_TRIGEN                      ((uint32_t)0x00060000)             /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */\n#define  LPTIM_CFGR_TRIGEN_0                    ((uint32_t)0x00020000)             /*!< Bit 0 */\n#define  LPTIM_CFGR_TRIGEN_1                    ((uint32_t)0x00040000)             /*!< Bit 1 */\n\n#define  LPTIM_CFGR_TIMOUT                      ((uint32_t)0x00080000)             /*!< Timout enable */\n#define  LPTIM_CFGR_WAVE                        ((uint32_t)0x00100000)             /*!< Waveform shape */\n#define  LPTIM_CFGR_WAVPOL                      ((uint32_t)0x00200000)             /*!< Waveform shape polarity */\n#define  LPTIM_CFGR_PRELOAD                     ((uint32_t)0x00400000)             /*!< Reg update mode */\n#define  LPTIM_CFGR_COUNTMODE                   ((uint32_t)0x00800000)             /*!< Counter mode enable */\n#define  LPTIM_CFGR_ENC                         ((uint32_t)0x01000000)             /*!< Encoder mode enable */\n\n/******************  Bit definition for LPTIM_CR register  ********************/\n#define  LPTIM_CR_ENABLE                        ((uint32_t)0x00000001)             /*!< LPTIMer enable */\n#define  LPTIM_CR_SNGSTRT                       ((uint32_t)0x00000002)             /*!< Timer start in single mode */\n#define  LPTIM_CR_CNTSTRT                       ((uint32_t)0x00000004)             /*!< Timer start in continuous mode */\n\n/******************  Bit definition for LPTIM_CMP register  *******************/\n#define  LPTIM_CMP_CMP                          ((uint32_t)0x0000FFFF)             /*!< Compare register */\n\n/******************  Bit definition for LPTIM_ARR register  *******************/\n#define  LPTIM_ARR_ARR                          ((uint32_t)0x0000FFFF)             /*!< Auto reload register */\n\n/******************  Bit definition for LPTIM_CNT register  *******************/\n#define  LPTIM_CNT_CNT                          ((uint32_t)0x0000FFFF)             /*!< Counter register */\n\n/******************************************************************************/\n/*                                                                            */\n/*                            MIFARE   Firewall                               */\n/*                                                                            */\n/******************************************************************************/\n\n/*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register */\n#define  FW_CSSA_ADD                        ((uint32_t)0x00FFFF00)        /*!< Code Segment Start Address */\n#define  FW_CSL_LENG                        ((uint32_t)0x003FFF00)        /*!< Code Segment Length        */\n#define  FW_NVDSSA_ADD                      ((uint32_t)0x00FFFF00)        /*!< Non Volatile Dat Segment Start Address */\n#define  FW_NVDSL_LENG                      ((uint32_t)0x003FFF00)        /*!< Non Volatile Data Segment Length */\n#define  FW_VDSSA_ADD                       ((uint32_t)0x0000FFC0)        /*!< Volatile Data Segment Start Address */\n#define  FW_VDSL_LENG                       ((uint32_t)0x0000FFC0)        /*!< Volatile Data Segment Length */\n\n/**************************Bit definition for CR register *********************/\n#define  FW_CR_FPA                          ((uint32_t)0x00000001)         /*!< Firewall Pre Arm*/\n#define  FW_CR_VDS                          ((uint32_t)0x00000002)         /*!< Volatile Data Sharing*/\n#define  FW_CR_VDE                          ((uint32_t)0x00000004)         /*!< Volatile Data Execution*/\n\n/******************************************************************************/\n/*                                                                            */\n/*                          Power Control (PWR)                               */\n/*                                                                            */\n/******************************************************************************/\n\n/********************  Bit definition for PWR_CR register  ********************/\n#define  PWR_CR_LPSDSR                       ((uint16_t)0x0001)     /*!< Low-power deepsleep/sleep/low power run */\n#define  PWR_CR_PDDS                         ((uint16_t)0x0002)     /*!< Power Down Deepsleep */\n#define  PWR_CR_CWUF                         ((uint16_t)0x0004)     /*!< Clear Wakeup Flag */\n#define  PWR_CR_CSBF                         ((uint16_t)0x0008)     /*!< Clear Standby Flag */\n#define  PWR_CR_PVDE                         ((uint16_t)0x0010)     /*!< Power Voltage Detector Enable */\n\n#define  PWR_CR_PLS                          ((uint16_t)0x00E0)     /*!< PLS[2:0] bits (PVD Level Selection) */\n#define  PWR_CR_PLS_0                        ((uint16_t)0x0020)     /*!< Bit 0 */\n#define  PWR_CR_PLS_1                        ((uint16_t)0x0040)     /*!< Bit 1 */\n#define  PWR_CR_PLS_2                        ((uint16_t)0x0080)     /*!< Bit 2 */\n\n/*!< PVD level configuration */\n#define  PWR_CR_PLS_LEV0                     ((uint16_t)0x0000)     /*!< PVD level 0 */\n#define  PWR_CR_PLS_LEV1                     ((uint16_t)0x0020)     /*!< PVD level 1 */\n#define  PWR_CR_PLS_LEV2                     ((uint16_t)0x0040)     /*!< PVD level 2 */\n#define  PWR_CR_PLS_LEV3                     ((uint16_t)0x0060)     /*!< PVD level 3 */\n#define  PWR_CR_PLS_LEV4                     ((uint16_t)0x0080)     /*!< PVD level 4 */\n#define  PWR_CR_PLS_LEV5                     ((uint16_t)0x00A0)     /*!< PVD level 5 */\n#define  PWR_CR_PLS_LEV6                     ((uint16_t)0x00C0)     /*!< PVD level 6 */\n#define  PWR_CR_PLS_LEV7                     ((uint16_t)0x00E0)     /*!< PVD level 7 */\n\n#define  PWR_CR_DBP                          ((uint16_t)0x0100)     /*!< Disable Backup Domain write protection */\n#define  PWR_CR_ULP                          ((uint16_t)0x0200)     /*!< Ultra Low Power mode */\n#define  PWR_CR_FWU                          ((uint16_t)0x0400)     /*!< Fast wakeup */\n\n#define  PWR_CR_VOS                          ((uint16_t)0x1800)     /*!< VOS[1:0] bits (Voltage scaling range selection) */\n#define  PWR_CR_VOS_0                        ((uint16_t)0x0800)     /*!< Bit 0 */\n#define  PWR_CR_VOS_1                        ((uint16_t)0x1000)     /*!< Bit 1 */\n#define  PWR_CR_DSEEKOFF                     ((uint16_t)0x2000)     /*!< Deep Sleep mode with EEPROM kept Off */\n#define  PWR_CR_LPRUN                        ((uint16_t)0x4000)     /*!< Low power run mode */\n\n/*******************  Bit definition for PWR_CSR register  ********************/\n#define  PWR_CSR_WUF                         ((uint16_t)0x0001)     /*!< Wakeup Flag */\n#define  PWR_CSR_SBF                         ((uint16_t)0x0002)     /*!< Standby Flag */\n#define  PWR_CSR_PVDO                        ((uint16_t)0x0004)     /*!< PVD Output */\n#define  PWR_CSR_VREFINTRDYF                 ((uint16_t)0x0008)     /*!< Internal voltage reference (VREFINT) ready flag */\n#define  PWR_CSR_VOSF                        ((uint16_t)0x0010)     /*!< Voltage Scaling select flag */\n#define  PWR_CSR_REGLPF                      ((uint16_t)0x0020)     /*!< Regulator LP flag */\n\n#define  PWR_CSR_EWUP1                       ((uint16_t)0x0100)     /*!< Enable WKUP pin 1 */\n#define  PWR_CSR_EWUP2                       ((uint16_t)0x0200)     /*!< Enable WKUP pin 2 */\n\n/******************************************************************************/\n/*                                                                            */\n/*                         Reset and Clock Control                            */\n/*                                                                            */\n/******************************************************************************/\n\n/********************  Bit definition for RCC_CR register  ********************/\n#define  RCC_CR_HSION                        ((uint32_t)0x00000001)        /*!< Internal High Speed clock enable */\n#define  RCC_CR_HSIKERON                     ((uint32_t)0x00000002)        /*!< Internal High Speed clock enable for some IPs Kernel */\n#define  RCC_CR_HSIRDY                       ((uint32_t)0x00000004)        /*!< Internal High Speed clock ready flag */\n#define  RCC_CR_HSIDIVEN                     ((uint32_t)0x00000008)        /*!< Internal High Speed clock divider enable */\n#define  RCC_CR_HSIDIVF                      ((uint32_t)0x00000010)        /*!< Internal High Speed clock divider flag */\n#define  RCC_CR_MSION                        ((uint32_t)0x00000100)        /*!< Internal Multi Speed clock enable */\n#define  RCC_CR_MSIRDY                       ((uint32_t)0x00000200)        /*!< Internal Multi Speed clock ready flag */\n#define  RCC_CR_HSEON                        ((uint32_t)0x00010000)        /*!< External High Speed clock enable */\n#define  RCC_CR_HSERDY                       ((uint32_t)0x00020000)        /*!< External High Speed clock ready flag */\n#define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000)        /*!< External High Speed clock Bypass */\n#define  RCC_CR_CSSHSEON                     ((uint32_t)0x00080000)        /*!< HSE Clock Security System enable */\n#define  RCC_CR_RTCPRE                       ((uint32_t)0x00300000)        /*!< RTC/LCD prescaler [1:0] bits */\n#define  RCC_CR_RTCPRE_0                     ((uint32_t)0x00100000)        /*!< RTC/LCD prescaler Bit 0 */\n#define  RCC_CR_RTCPRE_1                     ((uint32_t)0x00200000)        /*!< RTC/LCD prescaler Bit 1 */\n#define  RCC_CR_PLLON                        ((uint32_t)0x01000000)        /*!< PLL enable */\n#define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000)        /*!< PLL clock ready flag */\n\n/********************  Bit definition for RCC_ICSCR register  *****************/\n#define  RCC_ICSCR_HSICAL                    ((uint32_t)0x000000FF)        /*!< Internal High Speed clock Calibration */\n#define  RCC_ICSCR_HSITRIM                   ((uint32_t)0x00001F00)        /*!< Internal High Speed clock trimming */\n\n#define  RCC_ICSCR_MSIRANGE                  ((uint32_t)0x0000E000)        /*!< Internal Multi Speed clock Range */\n#define  RCC_ICSCR_MSIRANGE_0                ((uint32_t)0x00000000)        /*!< Internal Multi Speed clock Range 65.536 KHz */\n#define  RCC_ICSCR_MSIRANGE_1                ((uint32_t)0x00002000)        /*!< Internal Multi Speed clock Range 131.072 KHz */\n#define  RCC_ICSCR_MSIRANGE_2                ((uint32_t)0x00004000)        /*!< Internal Multi Speed clock Range 262.144 KHz */\n#define  RCC_ICSCR_MSIRANGE_3                ((uint32_t)0x00006000)        /*!< Internal Multi Speed clock Range 524.288 KHz */\n#define  RCC_ICSCR_MSIRANGE_4                ((uint32_t)0x00008000)        /*!< Internal Multi Speed clock Range 1.048 MHz */\n#define  RCC_ICSCR_MSIRANGE_5                ((uint32_t)0x0000A000)        /*!< Internal Multi Speed clock Range 2.097 MHz */\n#define  RCC_ICSCR_MSIRANGE_6                ((uint32_t)0x0000C000)        /*!< Internal Multi Speed clock Range 4.194 MHz */\n#define  RCC_ICSCR_MSICAL                    ((uint32_t)0x00FF0000)        /*!< Internal Multi Speed clock Calibration */\n#define  RCC_ICSCR_MSITRIM                   ((uint32_t)0xFF000000)        /*!< Internal Multi Speed clock trimming */\n\n/********************  Bit definition for RCC_CRRCR register  *****************/\n#define  RCC_CRRCR_HSI48ON                    ((uint32_t)0x00000001)        /*!< HSI 48MHz clock enable */\n#define  RCC_CRRCR_HSI48RDY                   ((uint32_t)0x00000002)        /*!< HSI 48MHz clock ready flag */\n#define  RCC_CRRCR_HSI48CAL                   ((uint32_t)0x0000FF00)        /*!< HSI 48MHz clock Calibration */\n\n/*******************  Bit definition for RCC_CFGR register  *******************/\n/*!< SW configuration */\n#define  RCC_CFGR_SW                         ((uint32_t)0x00000003)        /*!< SW[1:0] bits (System clock Switch) */\n#define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001)        /*!< Bit 0 */\n#define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002)        /*!< Bit 1 */\n\n#define  RCC_CFGR_SW_MSI                     ((uint32_t)0x00000000)        /*!< MSI selected as system clock */\n#define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000001)        /*!< HSI selected as system clock */\n#define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000002)        /*!< HSE selected as system clock */\n#define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000003)        /*!< PLL selected as system clock */\n\n/*!< SWS configuration */\n#define  RCC_CFGR_SWS                        ((uint32_t)0x0000000C)        /*!< SWS[1:0] bits (System Clock Switch Status) */\n#define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004)        /*!< Bit 0 */\n#define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008)        /*!< Bit 1 */\n\n#define  RCC_CFGR_SWS_MSI                    ((uint32_t)0x00000000)        /*!< MSI oscillator used as system clock */\n#define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000004)        /*!< HSI oscillator used as system clock */\n#define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000008)        /*!< HSE oscillator used as system clock */\n#define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x0000000C)        /*!< PLL used as system clock */\n\n/*!< HPRE configuration */\n#define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0)        /*!< HPRE[3:0] bits (AHB prescaler) */\n#define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010)        /*!< Bit 0 */\n#define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020)        /*!< Bit 1 */\n#define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040)        /*!< Bit 2 */\n#define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080)        /*!< Bit 3 */\n\n#define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000)        /*!< SYSCLK not divided */\n#define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080)        /*!< SYSCLK divided by 2 */\n#define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090)        /*!< SYSCLK divided by 4 */\n#define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0)        /*!< SYSCLK divided by 8 */\n#define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0)        /*!< SYSCLK divided by 16 */\n#define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0)        /*!< SYSCLK divided by 64 */\n#define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0)        /*!< SYSCLK divided by 128 */\n#define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0)        /*!< SYSCLK divided by 256 */\n#define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0)        /*!< SYSCLK divided by 512 */\n\n/*!< PPRE1 configuration */\n#define  RCC_CFGR_PPRE1                      ((uint32_t)0x00000700)        /*!< PRE1[2:0] bits (APB1 prescaler) */\n#define  RCC_CFGR_PPRE1_0                    ((uint32_t)0x00000100)        /*!< Bit 0 */\n#define  RCC_CFGR_PPRE1_1                    ((uint32_t)0x00000200)        /*!< Bit 1 */\n#define  RCC_CFGR_PPRE1_2                    ((uint32_t)0x00000400)        /*!< Bit 2 */\n\n#define  RCC_CFGR_PPRE1_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */\n#define  RCC_CFGR_PPRE1_DIV2                 ((uint32_t)0x00000400)        /*!< HCLK divided by 2 */\n#define  RCC_CFGR_PPRE1_DIV4                 ((uint32_t)0x00000500)        /*!< HCLK divided by 4 */\n#define  RCC_CFGR_PPRE1_DIV8                 ((uint32_t)0x00000600)        /*!< HCLK divided by 8 */\n#define  RCC_CFGR_PPRE1_DIV16                ((uint32_t)0x00000700)        /*!< HCLK divided by 16 */\n\n/*!< PPRE2 configuration */\n#define  RCC_CFGR_PPRE2                      ((uint32_t)0x00003800)        /*!< PRE2[2:0] bits (APB2 prescaler) */\n#define  RCC_CFGR_PPRE2_0                    ((uint32_t)0x00000800)        /*!< Bit 0 */\n#define  RCC_CFGR_PPRE2_1                    ((uint32_t)0x00001000)        /*!< Bit 1 */\n#define  RCC_CFGR_PPRE2_2                    ((uint32_t)0x00002000)        /*!< Bit 2 */\n\n#define  RCC_CFGR_PPRE2_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */\n#define  RCC_CFGR_PPRE2_DIV2                 ((uint32_t)0x00002000)        /*!< HCLK divided by 2 */\n#define  RCC_CFGR_PPRE2_DIV4                 ((uint32_t)0x00002800)        /*!< HCLK divided by 4 */\n#define  RCC_CFGR_PPRE2_DIV8                 ((uint32_t)0x00003000)        /*!< HCLK divided by 8 */\n#define  RCC_CFGR_PPRE2_DIV16                ((uint32_t)0x00003800)        /*!< HCLK divided by 16 */\n\n#define  RCC_CFGR_STOPWUCK                   ((uint32_t)0x00008000)        /*!< Wake Up from Stop Clock selection */\n\n/*!< PLL entry clock source*/\n#define  RCC_CFGR_PLLSRC                     ((uint32_t)0x00010000)        /*!< PLL entry clock source */\n\n#define  RCC_CFGR_PLLSRC_HSI                 ((uint32_t)0x00000000)        /*!< HSI as PLL entry clock source */\n#define  RCC_CFGR_PLLSRC_HSE                 ((uint32_t)0x00010000)        /*!< HSE as PLL entry clock source */\n\n\n/*!< PLLMUL configuration */\n#define  RCC_CFGR_PLLMUL                     ((uint32_t)0x003C0000)        /*!< PLLMUL[3:0] bits (PLL multiplication factor) */\n#define  RCC_CFGR_PLLMUL_0                   ((uint32_t)0x00040000)        /*!< Bit 0 */\n#define  RCC_CFGR_PLLMUL_1                   ((uint32_t)0x00080000)        /*!< Bit 1 */\n#define  RCC_CFGR_PLLMUL_2                   ((uint32_t)0x00100000)        /*!< Bit 2 */\n#define  RCC_CFGR_PLLMUL_3                   ((uint32_t)0x00200000)        /*!< Bit 3 */\n\n#define  RCC_CFGR_PLLMUL3                    ((uint32_t)0x00000000)        /*!< PLL input clock * 3 */\n#define  RCC_CFGR_PLLMUL4                    ((uint32_t)0x00040000)        /*!< PLL input clock * 4 */\n#define  RCC_CFGR_PLLMUL6                    ((uint32_t)0x00080000)        /*!< PLL input clock * 6 */\n#define  RCC_CFGR_PLLMUL8                    ((uint32_t)0x000C0000)        /*!< PLL input clock * 8 */\n#define  RCC_CFGR_PLLMUL12                   ((uint32_t)0x00100000)        /*!< PLL input clock * 12 */\n#define  RCC_CFGR_PLLMUL16                   ((uint32_t)0x00140000)        /*!< PLL input clock * 16 */\n#define  RCC_CFGR_PLLMUL24                   ((uint32_t)0x00180000)        /*!< PLL input clock * 24 */\n#define  RCC_CFGR_PLLMUL32                   ((uint32_t)0x001C0000)        /*!< PLL input clock * 32 */\n#define  RCC_CFGR_PLLMUL48                   ((uint32_t)0x00200000)        /*!< PLL input clock * 48 */\n\n/*!< PLLDIV configuration */\n#define  RCC_CFGR_PLLDIV                     ((uint32_t)0x00C00000)        /*!< PLLDIV[1:0] bits (PLL Output Division) */\n#define  RCC_CFGR_PLLDIV_0                   ((uint32_t)0x00400000)        /*!< Bit0 */\n#define  RCC_CFGR_PLLDIV_1                   ((uint32_t)0x00800000)        /*!< Bit1 */\n\n#define  RCC_CFGR_PLLDIV2                    ((uint32_t)0x00400000)        /*!< PLL clock output = CKVCO / 2 */\n#define  RCC_CFGR_PLLDIV3                    ((uint32_t)0x00800000)        /*!< PLL clock output = CKVCO / 3 */\n#define  RCC_CFGR_PLLDIV4                    ((uint32_t)0x00C00000)        /*!< PLL clock output = CKVCO / 4 */\n\n/*!< MCO configuration */\n#define  RCC_CFGR_MCOSEL                        ((uint32_t)0x07000000)        /*!< MCO[2:0] bits (Microcontroller Clock Output) */\n#define  RCC_CFGR_MCOSEL_0                      ((uint32_t)0x01000000)        /*!< Bit 0 */\n#define  RCC_CFGR_MCOSEL_1                      ((uint32_t)0x02000000)        /*!< Bit 1 */\n#define  RCC_CFGR_MCOSEL_2                      ((uint32_t)0x04000000)        /*!< Bit 2 */\n\n\n#define  RCC_CFGR_MCO_NOCLOCK                ((uint32_t)0x00000000)        /*!< No clock */\n#define  RCC_CFGR_MCO_SYSCLK                 ((uint32_t)0x01000000)        /*!< System clock selected as MCO source */\n#define  RCC_CFGR_MCO_HSI                    ((uint32_t)0x02000000)        /*!< Internal 16 MHz RC oscillator clock selected */\n#define  RCC_CFGR_MCO_MSI                    ((uint32_t)0x03000000)        /*!< Internal Medium Speed RC oscillator clock selected */\n#define  RCC_CFGR_MCO_HSE                    ((uint32_t)0x04000000)        /*!< External 1-25 MHz oscillator clock selected */\n#define  RCC_CFGR_MCO_PLL                    ((uint32_t)0x05000000)        /*!< PLL clock divided */\n#define  RCC_CFGR_MCO_LSI                    ((uint32_t)0x06000000)        /*!< LSI selected */\n#define  RCC_CFGR_MCO_LSE                    ((uint32_t)0x07000000)        /*!< LSE selected */\n#define  RCC_CFGR_MCO_HSI48                  ((uint32_t)0x08000000)        /*!< HSI48 clock selected as MCO source */\n\n#define  RCC_CFGR_MCO_PRE                    ((uint32_t)0x70000000)        /*!< MCO prescaler */\n#define  RCC_CFGR_MCO_PRE_1                  ((uint32_t)0x00000000)        /*!< MCO is divided by 1 */\n#define  RCC_CFGR_MCO_PRE_2                  ((uint32_t)0x10000000)        /*!< MCO is divided by 2 */\n#define  RCC_CFGR_MCO_PRE_4                  ((uint32_t)0x20000000)        /*!< MCO is divided by 4 */\n#define  RCC_CFGR_MCO_PRE_8                  ((uint32_t)0x30000000)        /*!< MCO is divided by 8 */\n#define  RCC_CFGR_MCO_PRE_16                 ((uint32_t)0x40000000)        /*!< MCO is divided by 16 */\n\n/*!<******************  Bit definition for RCC_CIER register  ********************/\n#define  RCC_CIER_LSIRDYIE                    ((uint32_t)0x00000001)        /*!< LSI Ready Interrupt Enable */\n#define  RCC_CIER_LSERDYIE                    ((uint32_t)0x00000002)        /*!< LSE Ready Interrupt Enable */\n#define  RCC_CIER_HSIRDYIE                    ((uint32_t)0x00000004)        /*!< HSI Ready Interrupt Enable */\n#define  RCC_CIER_HSERDYIE                    ((uint32_t)0x00000008)        /*!< HSE Ready Interrupt Enable */\n#define  RCC_CIER_PLLRDYIE                    ((uint32_t)0x00000010)        /*!< PLL Ready Interrupt Enable */\n#define  RCC_CIER_MSIRDYIE                    ((uint32_t)0x00000020)        /*!< MSI Ready Interrupt Enable */\n#define  RCC_CIER_HSI48RDYIE                  ((uint32_t)0x00000040)        /*!< HSI48 Ready Interrupt Enable */\n#define  RCC_CIER_LSECSSIE                    ((uint32_t)0x00000080)        /*!< LSE CSS Interrupt Enable */\n\n/*!<******************  Bit definition for RCC_CIFR register  ********************/\n#define  RCC_CIFR_LSIRDYF                     ((uint32_t)0x00000001)        /*!< LSI Ready Interrupt flag */\n#define  RCC_CIFR_LSERDYF                     ((uint32_t)0x00000002)        /*!< LSE Ready Interrupt flag */\n#define  RCC_CIFR_HSIRDYF                     ((uint32_t)0x00000004)        /*!< HSI Ready Interrupt flag */\n#define  RCC_CIFR_HSERDYF                     ((uint32_t)0x00000008)        /*!< HSE Ready Interrupt flag */\n#define  RCC_CIFR_PLLRDYF                     ((uint32_t)0x00000010)        /*!< PLL Ready Interrupt flag */\n#define  RCC_CIFR_MSIRDYF                     ((uint32_t)0x00000020)        /*!< MSI Ready Interrupt flag */\n#define  RCC_CIFR_HSI48RDYF                   ((uint32_t)0x00000040)        /*!< HSI48 Ready Interrupt flag */\n#define  RCC_CIFR_LSECSSF                     ((uint32_t)0x00000080)        /*!< LSE Clock Security System Interrupt flag */\n#define  RCC_CIFR_CSSF                        ((uint32_t)0x00000100)        /*!< Clock Security System Interrupt flag */\n\n/*!<******************  Bit definition for RCC_CICR register  ********************/\n#define  RCC_CICR_LSIRDYC                     ((uint32_t)0x00000001)        /*!< LSI Ready Interrupt Clear */\n#define  RCC_CICR_LSERDYC                     ((uint32_t)0x00000002)        /*!< LSE Ready Interrupt Clear */\n#define  RCC_CICR_HSIRDYC                     ((uint32_t)0x00000004)        /*!< HSI Ready Interrupt Clear */\n#define  RCC_CICR_HSERDYC                     ((uint32_t)0x00000008)        /*!< HSE Ready Interrupt Clear */\n#define  RCC_CICR_PLLRDYC                     ((uint32_t)0x00000010)        /*!< PLL Ready Interrupt Clear */\n#define  RCC_CICR_MSIRDYC                     ((uint32_t)0x00000020)        /*!< MSI Ready Interrupt Clear */\n#define  RCC_CICR_HSI48RDYC                   ((uint32_t)0x00000040)        /*!< HSI48 Ready Interrupt Clear */\n#define  RCC_CICR_LSECSSC                     ((uint32_t)0x00000080)        /*!< LSE Clock Security System Interrupt Clear */\n#define  RCC_CICR_CSSC                        ((uint32_t)0x00000100)        /*!< Clock Security System Interrupt Clear */\n\n/*****************  Bit definition for RCC_IOPRSTR register  ******************/\n#define  RCC_IOPRSTR_GPIOARST                ((uint32_t)0x00000001)        /*!< GPIO port A reset */\n#define  RCC_IOPRSTR_GPIOBRST                ((uint32_t)0x00000002)        /*!< GPIO port B reset */\n#define  RCC_IOPRSTR_GPIOCRST                ((uint32_t)0x00000004)        /*!< GPIO port C reset */\n#define  RCC_IOPRSTR_GPIODRST                ((uint32_t)0x00000008)        /*!< GPIO port D reset */\n#define  RCC_IOPRSTR_GPIOHRST                ((uint32_t)0x00000080)        /*!< GPIO port H reset */\n\n/******************  Bit definition for RCC_AHBRST register  ******************/\n#define  RCC_AHBRSTR_DMA1RST                 ((uint32_t)0x00000001)        /*!< DMA1 reset */\n#define  RCC_AHBRSTR_MIFRST                  ((uint32_t)0x00000100)        /*!< Memory interface reset reset */\n#define  RCC_AHBRSTR_CRCRST                  ((uint32_t)0x00001000)        /*!< CRC reset */\n#define  RCC_AHBRSTR_TSCRST                   ((uint32_t)0x00010000)        /*!< TSC reset */\n#define  RCC_AHBRSTR_RNGRST                  ((uint32_t)0x00100000)        /*!< RNG reset */\n\n/*****************  Bit definition for RCC_APB2RSTR register  *****************/\n#define  RCC_APB2RSTR_SYSCFGRST              ((uint32_t)0x00000001)        /*!< SYSCFG clock reset */\n#define  RCC_APB2RSTR_TIM21RST                ((uint32_t)0x00000004)        /*!< TIM21 clock reset */\n#define  RCC_APB2RSTR_TIM22RST               ((uint32_t)0x00000020)        /*!< TIM22 clock reset */\n#define  RCC_APB2RSTR_ADC1RST                ((uint32_t)0x00000200)        /*!< ADC1 clock reset */\n#define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000)        /*!< SPI1 clock reset */\n#define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00004000)        /*!< USART1 clock reset */\n#define  RCC_APB2RSTR_DBGMCURST              ((uint32_t)0x00400000)        /*!< DBGMCU clock reset */\n\n/*****************  Bit definition for RCC_APB1RSTR register  *****************/\n#define  RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001)        /*!< Timer 2 clock reset */\n#define  RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010)        /*!< Timer 6 clock reset */\n#define  RCC_APB1RSTR_LCDRST                 ((uint32_t)0x00000200)        /*!< LCD clock reset */\n#define  RCC_APB1RSTR_WWDGRST                ((uint32_t)0x00000800)        /*!< Window Watchdog clock reset */\n#define  RCC_APB1RSTR_SPI2RST                ((uint32_t)0x00004000)        /*!< SPI2 clock reset */\n#define  RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000)        /*!< USART 2 clock reset */\n#define  RCC_APB1RSTR_LPUART1RST             ((uint32_t)0x00040000)        /*!< LPUART1 clock reset */\n#define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000)        /*!< I2C 1 clock reset */\n#define  RCC_APB1RSTR_I2C2RST                ((uint32_t)0x00400000)        /*!< I2C 2 clock reset */\n#define  RCC_APB1RSTR_USBRST                 ((uint32_t)0x00800000)        /*!< USB clock reset */\n#define  RCC_APB1RSTR_CRSRST                 ((uint32_t)0x08000000)        /*!< CRS clock reset */\n#define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000)        /*!< PWR clock reset */\n#define  RCC_APB1RSTR_DACRST                 ((uint32_t)0x20000000)        /*!< DAC clock reset */\n#define  RCC_APB1RSTR_LPTIM1RST              ((uint32_t)0x80000000)        /*!< LPTIM1 clock reset */\n\n/*****************  Bit definition for RCC_IOPENR register  ******************/\n#define  RCC_IOPENR_GPIOAEN                ((uint32_t)0x00000001)        /*!< GPIO port A clock enable */\n#define  RCC_IOPENR_GPIOBEN                ((uint32_t)0x00000002)        /*!< GPIO port B clock enable */\n#define  RCC_IOPENR_GPIOCEN                ((uint32_t)0x00000004)        /*!< GPIO port C clock enable */\n#define  RCC_IOPENR_GPIODEN                ((uint32_t)0x00000008)        /*!< GPIO port D clock enable */\n#define  RCC_IOPENR_GPIOHEN                ((uint32_t)0x00000080)        /*!< GPIO port H clock enable */\n\n/*****************  Bit definition for RCC_AHBENR register  ******************/\n#define  RCC_AHBENR_DMA1EN                   ((uint32_t)0x00000001)        /*!< DMA1 clock enable */\n#define  RCC_AHBENR_MIFEN                    ((uint32_t)0x00000100)        /*!< NVM interface clock enable bit */\n#define  RCC_AHBENR_CRCEN                    ((uint32_t)0x00001000)        /*!< CRC clock enable */\n#define  RCC_AHBENR_TSCEN                     ((uint32_t)0x00010000)        /*!< TSC clock enable */\n#define  RCC_AHBENR_RNGEN                    ((uint32_t)0x00100000)        /*!< RNG clock enable */\n\n/*****************  Bit definition for RCC_APB2ENR register  ******************/\n#define  RCC_APB2ENR_SYSCFGEN                ((uint32_t)0x00000001)        /*!< SYSCFG clock enable */\n#define  RCC_APB2ENR_TIM21EN                  ((uint32_t)0x00000004)        /*!< TIM21 clock enable */\n#define  RCC_APB2ENR_TIM22EN                 ((uint32_t)0x00000020)        /*!< TIM22 clock enable */\n#define  RCC_APB2ENR_MIFIEN                  ((uint32_t)0x00000080)        /*!< MiFare Firewall clock enable */\n#define  RCC_APB2ENR_ADC1EN                  ((uint32_t)0x00000200)        /*!< ADC1 clock enable */\n#define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000)        /*!< SPI1 clock enable */\n#define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00004000)        /*!< USART1 clock enable */\n#define  RCC_APB2ENR_DBGMCUEN                ((uint32_t)0x00400000)        /*!< DBGMCU clock enable */\n\n/*****************  Bit definition for RCC_APB1ENR register  ******************/\n#define  RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001)        /*!< Timer 2 clock enable */\n#define  RCC_APB1ENR_TIM6EN                  ((uint32_t)0x00000010)        /*!< Timer 6 clock enable */\n#define  RCC_APB1ENR_LCDEN                   ((uint32_t)0x00000200)        /*!< LCD clock enable */\n#define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800)        /*!< Window Watchdog clock enable */\n#define  RCC_APB1ENR_SPI2EN                  ((uint32_t)0x00004000)        /*!< SPI2 clock enable */\n#define  RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000)        /*!< USART2 clock enable */\n#define  RCC_APB1ENR_LPUART1EN               ((uint32_t)0x00040000)        /*!< LPUART1 clock enable */\n#define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000)        /*!< I2C1 clock enable */\n#define  RCC_APB1ENR_I2C2EN                  ((uint32_t)0x00400000)        /*!< I2C2 clock enable */\n#define  RCC_APB1ENR_USBEN                   ((uint32_t)0x00800000)        /*!< USB clock enable */\n#define  RCC_APB1ENR_CRSEN                   ((uint32_t)0x08000000)        /*!< CRS clock enable */\n#define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000)        /*!< PWR clock enable */\n#define  RCC_APB1ENR_DACEN                   ((uint32_t)0x20000000)        /*!< DAC clock enable */\n#define  RCC_APB1ENR_LPTIM1EN                ((uint32_t)0x80000000)        /*!< LPTIM1 clock enable */\n\n/******************  Bit definition for RCC_IOPSMENR register  ****************/\n#define  RCC_IOPSMENR_GPIOASMEN              ((uint32_t)0x00000001)        /*!< GPIO port A clock enabled in sleep mode */\n#define  RCC_IOPSMENR_GPIOBSMEN              ((uint32_t)0x00000002)        /*!< GPIO port B clock enabled in sleep mode */\n#define  RCC_IOPSMENR_GPIOCSMEN              ((uint32_t)0x00000004)        /*!< GPIO port C clock enabled in sleep mode */\n#define  RCC_IOPSMENR_GPIODSMEN              ((uint32_t)0x00000008)        /*!< GPIO port D clock enabled in sleep mode */\n#define  RCC_IOPSMENR_GPIOHSMEN              ((uint32_t)0x00000080)        /*!< GPIO port H clock enabled in sleep mode */\n\n/*****************  Bit definition for RCC_AHBSMENR register  ******************/\n#define  RCC_AHBSMENR_DMA1SMEN                 ((uint32_t)0x00000001)        /*!< DMA1 clock enabled in sleep mode */\n#define  RCC_AHBSMENR_MIFSMEN                  ((uint32_t)0x00000100)        /*!< NVM interface clock enable during sleep mode */\n#define  RCC_AHBSMENR_SRAMSMEN                 ((uint32_t)0x00000200)        /*!< SRAM clock enabled in sleep mode */\n#define  RCC_AHBSMENR_CRCSMEN                  ((uint32_t)0x00001000)        /*!< CRC clock enabled in sleep mode */\n#define  RCC_AHBSMENR_TSCSMEN                   ((uint32_t)0x00010000)        /*!< TSC clock enabled in sleep mode */\n#define  RCC_AHBSMENR_RNGSMEN                  ((uint32_t)0x00100000)        /*!< RNG clock enabled in sleep mode */\n\n/*****************  Bit definition for RCC_APB2SMENR register  ******************/\n#define  RCC_APB2SMENR_SYSCFGSMEN              ((uint32_t)0x00000001)        /*!< SYSCFG clock enabled in sleep mode */\n#define  RCC_APB2SMENR_TIM21SMEN                ((uint32_t)0x00000004)        /*!< TIM21 clock enabled in sleep mode */\n#define  RCC_APB2SMENR_TIM22SMEN               ((uint32_t)0x00000020)        /*!< TIM22 clock enabled in sleep mode */\n#define  RCC_APB2SMENR_ADC1SMEN                ((uint32_t)0x00000200)        /*!< ADC1 clock enabled in sleep mode */\n#define  RCC_APB2SMENR_SPI1SMEN                ((uint32_t)0x00001000)        /*!< SPI1 clock enabled in sleep mode */\n#define  RCC_APB2SMENR_USART1SMEN              ((uint32_t)0x00004000)        /*!< USART1 clock enabled in sleep mode */\n#define  RCC_APB2SMENR_DBGMCUSMEN              ((uint32_t)0x00400000)        /*!< DBGMCU clock enabled in sleep mode */\n\n/*****************  Bit definition for RCC_APB1SMENR register  ******************/\n#define  RCC_APB1SMENR_TIM2SMEN                ((uint32_t)0x00000001)        /*!< Timer 2 clock enabled in sleep mode */\n#define  RCC_APB1SMENR_TIM6SMEN                ((uint32_t)0x00000010)        /*!< Timer 6 clock enabled in sleep mode */\n#define  RCC_APB1SMENR_LCDSMEN                 ((uint32_t)0x00000200)        /*!< LCD clock enabled in sleep mode */\n#define  RCC_APB1SMENR_WWDGSMEN                ((uint32_t)0x00000800)        /*!< Window Watchdog clock enabled in sleep mode */\n#define  RCC_APB1SMENR_SPI2SMEN                ((uint32_t)0x00004000)        /*!< SPI2 clock enabled in sleep mode */\n#define  RCC_APB1SMENR_USART2SMEN              ((uint32_t)0x00020000)        /*!< USART2 clock enabled in sleep mode */\n#define  RCC_APB1SMENR_LPUART1SMEN             ((uint32_t)0x00040000)        /*!< LPUART1 clock enabled in sleep mode */\n#define  RCC_APB1SMENR_I2C1SMEN                ((uint32_t)0x00200000)        /*!< I2C1 clock enabled in sleep mode */\n#define  RCC_APB1SMENR_I2C2SMEN                ((uint32_t)0x00400000)        /*!< I2C2 clock enabled in sleep mode */\n#define  RCC_APB1SMENR_USBSMEN                 ((uint32_t)0x00800000)        /*!< USB clock enabled in sleep mode */\n#define  RCC_APB1SMENR_CRSSMEN                 ((uint32_t)0x08000000)        /*!< CRS clock enabled in sleep mode */\n#define  RCC_APB1SMENR_PWRSMEN                 ((uint32_t)0x10000000)        /*!< PWR clock enabled in sleep mode */\n#define  RCC_APB1SMENR_DACSMEN                 ((uint32_t)0x20000000)        /*!< DAC clock enabled in sleep mode */\n#define  RCC_APB1SMENR_LPTIM1SMEN              ((uint32_t)0x80000000)        /*!< LPTIM1 clock enabled in sleep mode */\n\n/*******************  Bit definition for RCC_CCIPR register  *******************/\n/*!< USART1 Clock source selection */\n#define  RCC_CCIPR_USART1SEL                  ((uint32_t)0x00000003)        /*!< USART1SEL[1:0] bits */\n#define  RCC_CCIPR_USART1SEL_0                ((uint32_t)0x00000001)        /*!< Bit 0 */\n#define  RCC_CCIPR_USART1SEL_1                ((uint32_t)0x00000002)        /*!< Bit 1 */\n\n/*!< USART2 Clock source selection */\n#define  RCC_CCIPR_USART2SEL                  ((uint32_t)0x0000000C)        /*!< USART2SEL[1:0] bits */\n#define  RCC_CCIPR_USART2SEL_0                ((uint32_t)0x00000004)        /*!< Bit 0 */\n#define  RCC_CCIPR_USART2SEL_1                ((uint32_t)0x00000008)        /*!< Bit 1 */\n\n/*!< LPUART1 Clock source selection */\n#define  RCC_CCIPR_LPUART1SEL                  ((uint32_t)0x0000C00)        /*!< LPUART1SEL[1:0] bits */\n#define  RCC_CCIPR_LPUART1SEL_0                ((uint32_t)0x0000400)        /*!< Bit 0 */\n#define  RCC_CCIPR_LPUART1SEL_1                ((uint32_t)0x0000800)        /*!< Bit 1 */\n\n/*!< I2C2 Clock source selection */\n#define  RCC_CCIPR_I2C1SEL                    ((uint32_t)0x00003000)        /*!< I2C1SEL [1:0] bits */\n#define  RCC_CCIPR_I2C1SEL_0                  ((uint32_t)0x00001000)        /*!< Bit 0 */\n#define  RCC_CCIPR_I2C1SEL_1                  ((uint32_t)0x00002000)        /*!< Bit 1 */\n\n/*!< LPTIM1 Clock source selection */\n#define  RCC_CCIPR_LPTIM1SEL                  ((uint32_t)0x000C0000)        /*!< LPTIM1SEL [1:0] bits */\n#define  RCC_CCIPR_LPTIM1SEL_0                ((uint32_t)0x00040000)        /*!< Bit 0 */\n#define  RCC_CCIPR_LPTIM1SEL_1                ((uint32_t)0x00080000)        /*!< Bit 1 */\n\n/*!< HSI48 Clock source selection */\n#define  RCC_CCIPR_HSI48MSEL                  ((uint32_t)0x04000000)        /*!< HSI48 RC clock source selection bit for USB and RNG*/\n\n\n/*******************  Bit definition for RCC_CSR register  *******************/\n#define  RCC_CSR_LSION                       ((uint32_t)0x00000001)        /*!< Internal Low Speed oscillator enable */\n#define  RCC_CSR_LSIRDY                      ((uint32_t)0x00000002)        /*!< Internal Low Speed oscillator Ready */\n\n#define  RCC_CSR_LSEON                      ((uint32_t)0x00000100)        /*!< External Low Speed oscillator enable */\n#define  RCC_CSR_LSERDY                     ((uint32_t)0x00000200)        /*!< External Low Speed oscillator Ready */\n#define  RCC_CSR_LSEBYP                     ((uint32_t)0x00000400)        /*!< External Low Speed oscillator Bypass */\n\n#define  RCC_CSR_LSEDRV                     ((uint32_t)0x00001800)        /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */\n#define  RCC_CSR_LSEDRV_0                   ((uint32_t)0x00000800)        /*!< Bit 0 */\n#define  RCC_CSR_LSEDRV_1                   ((uint32_t)0x00001000)        /*!< Bit 1 */\n\n#define  RCC_CSR_LSECSSON                   ((uint32_t)0x00002000)        /*!< External Low Speed oscillator CSS Enable */\n#define  RCC_CSR_LSECSSD                    ((uint32_t)0x00004000)        /*!< External Low Speed oscillator CSS Detected */\n\n/*!< RTC congiguration */\n#define  RCC_CSR_RTCSEL                     ((uint32_t)0x00030000)        /*!< RTCSEL[1:0] bits (RTC clock source selection) */\n#define  RCC_CSR_RTCSEL_0                   ((uint32_t)0x00010000)        /*!< Bit 0 */\n#define  RCC_CSR_RTCSEL_1                   ((uint32_t)0x00020000)        /*!< Bit 1 */\n\n#define  RCC_CSR_RTCSEL_NOCLOCK             ((uint32_t)0x00000000)        /*!< No clock */\n#define  RCC_CSR_RTCSEL_LSE                 ((uint32_t)0x00010000)        /*!< LSE oscillator clock used as RTC clock */\n#define  RCC_CSR_RTCSEL_LSI                 ((uint32_t)0x00020000)        /*!< LSI oscillator clock used as RTC clock */\n#define  RCC_CSR_RTCSEL_HSE                 ((uint32_t)0x00030000)        /*!< HSE oscillator clock used as RTC clock */\n\n#define  RCC_CSR_RTCEN                      ((uint32_t)0x00040000)        /*!< RTC clock enable */\n#define  RCC_CSR_RTCRST                     ((uint32_t)0x00080000)        /*!< RTC software reset  */\n\n#define  RCC_CSR_RMVF                       ((uint32_t)0x00800000)        /*!< Remove reset flag */\n#define  RCC_CSR_FWRSTF                   ((uint32_t)0x01000000)        /*!< Mifare Firewall reset flag */\n#define  RCC_CSR_OBL                        ((uint32_t)0x02000000)        /*!< OBL reset flag */\n#define  RCC_CSR_PINRSTF                    ((uint32_t)0x04000000)        /*!< PIN reset flag */\n#define  RCC_CSR_PORRSTF                    ((uint32_t)0x08000000)        /*!< POR/PDR reset flag */\n#define  RCC_CSR_SFTRSTF                    ((uint32_t)0x10000000)        /*!< Software Reset flag */\n#define  RCC_CSR_IWDGRSTF                   ((uint32_t)0x20000000)        /*!< Independent Watchdog reset flag */\n#define  RCC_CSR_WWDGRSTF                   ((uint32_t)0x40000000)        /*!< Window watchdog reset flag */\n#define  RCC_CSR_LPWRRSTF                   ((uint32_t)0x80000000)        /*!< Low-Power reset flag */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                    RNG                                     */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bits definition for RNG_CR register  *******************/\n#define RNG_CR_RNGEN                         ((uint32_t)0x00000004)\n#define RNG_CR_IE                            ((uint32_t)0x00000008)\n\n/********************  Bits definition for RNG_SR register  *******************/\n#define RNG_SR_DRDY                          ((uint32_t)0x00000001)\n#define RNG_SR_CECS                          ((uint32_t)0x00000002)\n#define RNG_SR_SECS                          ((uint32_t)0x00000004)\n#define RNG_SR_CEIS                          ((uint32_t)0x00000020)\n#define RNG_SR_SEIS                          ((uint32_t)0x00000040)\n\n/******************************************************************************/\n/*                                                                            */\n/*                           Real-Time Clock (RTC)                            */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bits definition for RTC_TR register  *******************/\n#define RTC_TR_PM                            ((uint32_t)0x00400000)        /*!<  */\n#define RTC_TR_HT                            ((uint32_t)0x00300000)        /*!<  */\n#define RTC_TR_HT_0                          ((uint32_t)0x00100000)        /*!<  */\n#define RTC_TR_HT_1                          ((uint32_t)0x00200000)        /*!<  */\n#define RTC_TR_HU                            ((uint32_t)0x000F0000)        /*!<  */\n#define RTC_TR_HU_0                          ((uint32_t)0x00010000)        /*!<  */\n#define RTC_TR_HU_1                          ((uint32_t)0x00020000)        /*!<  */\n#define RTC_TR_HU_2                          ((uint32_t)0x00040000)        /*!<  */\n#define RTC_TR_HU_3                          ((uint32_t)0x00080000)        /*!<  */\n#define RTC_TR_MNT                           ((uint32_t)0x00007000)        /*!<  */\n#define RTC_TR_MNT_0                         ((uint32_t)0x00001000)        /*!<  */\n#define RTC_TR_MNT_1                         ((uint32_t)0x00002000)        /*!<  */\n#define RTC_TR_MNT_2                         ((uint32_t)0x00004000)        /*!<  */\n#define RTC_TR_MNU                           ((uint32_t)0x00000F00)        /*!<  */\n#define RTC_TR_MNU_0                         ((uint32_t)0x00000100)        /*!<  */\n#define RTC_TR_MNU_1                         ((uint32_t)0x00000200)        /*!<  */\n#define RTC_TR_MNU_2                         ((uint32_t)0x00000400)        /*!<  */\n#define RTC_TR_MNU_3                         ((uint32_t)0x00000800)        /*!<  */\n#define RTC_TR_ST                            ((uint32_t)0x00000070)        /*!<  */\n#define RTC_TR_ST_0                          ((uint32_t)0x00000010)        /*!<  */\n#define RTC_TR_ST_1                          ((uint32_t)0x00000020)        /*!<  */\n#define RTC_TR_ST_2                          ((uint32_t)0x00000040)        /*!<  */\n#define RTC_TR_SU                            ((uint32_t)0x0000000F)        /*!<  */\n#define RTC_TR_SU_0                          ((uint32_t)0x00000001)        /*!<  */\n#define RTC_TR_SU_1                          ((uint32_t)0x00000002)        /*!<  */\n#define RTC_TR_SU_2                          ((uint32_t)0x00000004)        /*!<  */\n#define RTC_TR_SU_3                          ((uint32_t)0x00000008)        /*!<  */\n\n/********************  Bits definition for RTC_DR register  *******************/\n#define RTC_DR_YT                            ((uint32_t)0x00F00000)        /*!<  */\n#define RTC_DR_YT_0                          ((uint32_t)0x00100000)        /*!<  */\n#define RTC_DR_YT_1                          ((uint32_t)0x00200000)        /*!<  */\n#define RTC_DR_YT_2                          ((uint32_t)0x00400000)        /*!<  */\n#define RTC_DR_YT_3                          ((uint32_t)0x00800000)        /*!<  */\n#define RTC_DR_YU                            ((uint32_t)0x000F0000)        /*!<  */\n#define RTC_DR_YU_0                          ((uint32_t)0x00010000)        /*!<  */\n#define RTC_DR_YU_1                          ((uint32_t)0x00020000)        /*!<  */\n#define RTC_DR_YU_2                          ((uint32_t)0x00040000)        /*!<  */\n#define RTC_DR_YU_3                          ((uint32_t)0x00080000)        /*!<  */\n#define RTC_DR_WDU                           ((uint32_t)0x0000E000)        /*!<  */\n#define RTC_DR_WDU_0                         ((uint32_t)0x00002000)        /*!<  */\n#define RTC_DR_WDU_1                         ((uint32_t)0x00004000)        /*!<  */\n#define RTC_DR_WDU_2                         ((uint32_t)0x00008000)        /*!<  */\n#define RTC_DR_MT                            ((uint32_t)0x00001000)        /*!<  */\n#define RTC_DR_MU                            ((uint32_t)0x00000F00)        /*!<  */\n#define RTC_DR_MU_0                          ((uint32_t)0x00000100)        /*!<  */\n#define RTC_DR_MU_1                          ((uint32_t)0x00000200)        /*!<  */\n#define RTC_DR_MU_2                          ((uint32_t)0x00000400)        /*!<  */\n#define RTC_DR_MU_3                          ((uint32_t)0x00000800)        /*!<  */\n#define RTC_DR_DT                            ((uint32_t)0x00000030)        /*!<  */\n#define RTC_DR_DT_0                          ((uint32_t)0x00000010)        /*!<  */\n#define RTC_DR_DT_1                          ((uint32_t)0x00000020)        /*!<  */\n#define RTC_DR_DU                            ((uint32_t)0x0000000F)        /*!<  */\n#define RTC_DR_DU_0                          ((uint32_t)0x00000001)        /*!<  */\n#define RTC_DR_DU_1                          ((uint32_t)0x00000002)        /*!<  */\n#define RTC_DR_DU_2                          ((uint32_t)0x00000004)        /*!<  */\n#define RTC_DR_DU_3                          ((uint32_t)0x00000008)        /*!<  */\n\n/********************  Bits definition for RTC_CR register  *******************/\n#define RTC_CR_COE                           ((uint32_t)0x00800000)        /*!<  */\n#define RTC_CR_OSEL                          ((uint32_t)0x00600000)        /*!<  */\n#define RTC_CR_OSEL_0                        ((uint32_t)0x00200000)        /*!<  */\n#define RTC_CR_OSEL_1                        ((uint32_t)0x00400000)        /*!<  */\n#define RTC_CR_POL                           ((uint32_t)0x00100000)        /*!<  */\n#define RTC_CR_COSEL                        ((uint32_t)0x00080000)        /*!<  */\n#define RTC_CR_BCK                           ((uint32_t)0x00040000)        /*!<  */\n#define RTC_CR_SUB1H                         ((uint32_t)0x00020000)        /*!<  */\n#define RTC_CR_ADD1H                         ((uint32_t)0x00010000)        /*!<  */\n#define RTC_CR_TSIE                          ((uint32_t)0x00008000)        /*!<  */\n#define RTC_CR_WUTIE                         ((uint32_t)0x00004000)        /*!<  */\n#define RTC_CR_ALRBIE                        ((uint32_t)0x00002000)        /*!<  */\n#define RTC_CR_ALRAIE                        ((uint32_t)0x00001000)        /*!<  */\n#define RTC_CR_TSE                           ((uint32_t)0x00000800)        /*!<  */\n#define RTC_CR_WUTE                          ((uint32_t)0x00000400)        /*!<  */\n#define RTC_CR_ALRBE                         ((uint32_t)0x00000200)        /*!<  */\n#define RTC_CR_ALRAE                         ((uint32_t)0x00000100)        /*!<  */\n#define RTC_CR_FMT                           ((uint32_t)0x00000040)        /*!<  */\n#define RTC_CR_BYPSHAD                       ((uint32_t)0x00000020)        /*!<  */\n#define RTC_CR_REFCKON                       ((uint32_t)0x00000010)        /*!<  */\n#define RTC_CR_TSEDGE                        ((uint32_t)0x00000008)        /*!<  */\n#define RTC_CR_WUCKSEL                       ((uint32_t)0x00000007)        /*!<  */\n#define RTC_CR_WUCKSEL_0                     ((uint32_t)0x00000001)        /*!<  */\n#define RTC_CR_WUCKSEL_1                     ((uint32_t)0x00000002)        /*!<  */\n#define RTC_CR_WUCKSEL_2                     ((uint32_t)0x00000004)        /*!<  */\n\n/********************  Bits definition for RTC_ISR register  ******************/\n#define RTC_ISR_RECALPF                      ((uint32_t)0x00010000)        /*!<  */\n#define RTC_ISR_TAMP2F                       ((uint32_t)0x00004000)        /*!<  */\n#define RTC_ISR_TAMP1F                       ((uint32_t)0x00002000)        /*!<  */\n#define RTC_ISR_TSOVF                        ((uint32_t)0x00001000)        /*!<  */\n#define RTC_ISR_TSF                          ((uint32_t)0x00000800)        /*!<  */\n#define RTC_ISR_WUTF                         ((uint32_t)0x00000400)        /*!<  */\n#define RTC_ISR_ALRBF                        ((uint32_t)0x00000200)        /*!<  */\n#define RTC_ISR_ALRAF                        ((uint32_t)0x00000100)        /*!<  */\n#define RTC_ISR_INIT                         ((uint32_t)0x00000080)        /*!<  */\n#define RTC_ISR_INITF                        ((uint32_t)0x00000040)        /*!<  */\n#define RTC_ISR_RSF                          ((uint32_t)0x00000020)        /*!<  */\n#define RTC_ISR_INITS                        ((uint32_t)0x00000010)        /*!<  */\n#define RTC_ISR_SHPF                         ((uint32_t)0x00000008)        /*!<  */\n#define RTC_ISR_WUTWF                        ((uint32_t)0x00000004)        /*!<  */\n#define RTC_ISR_ALRBWF                       ((uint32_t)0x00000002)        /*!<  */\n#define RTC_ISR_ALRAWF                       ((uint32_t)0x00000001)        /*!<  */\n\n/********************  Bits definition for RTC_PRER register  *****************/\n#define RTC_PRER_PREDIV_A                    ((uint32_t)0x007F0000)        /*!<  */\n#define RTC_PRER_PREDIV_S                    ((uint32_t)0x00007FFF)        /*!<  */\n\n/********************  Bits definition for RTC_WUTR register  *****************/\n#define RTC_WUTR_WUT                         ((uint32_t)0x0000FFFF)\n\n/********************  Bits definition for RTC_ALRMAR register  ***************/\n#define RTC_ALRMAR_MSK4                      ((uint32_t)0x80000000)        /*!<  */\n#define RTC_ALRMAR_WDSEL                     ((uint32_t)0x40000000)        /*!<  */\n#define RTC_ALRMAR_DT                        ((uint32_t)0x30000000)        /*!<  */\n#define RTC_ALRMAR_DT_0                      ((uint32_t)0x10000000)        /*!<  */\n#define RTC_ALRMAR_DT_1                      ((uint32_t)0x20000000)        /*!<  */\n#define RTC_ALRMAR_DU                        ((uint32_t)0x0F000000)        /*!<  */\n#define RTC_ALRMAR_DU_0                      ((uint32_t)0x01000000)        /*!<  */\n#define RTC_ALRMAR_DU_1                      ((uint32_t)0x02000000)        /*!<  */\n#define RTC_ALRMAR_DU_2                      ((uint32_t)0x04000000)        /*!<  */\n#define RTC_ALRMAR_DU_3                      ((uint32_t)0x08000000)        /*!<  */\n#define RTC_ALRMAR_MSK3                      ((uint32_t)0x00800000)        /*!<  */\n#define RTC_ALRMAR_PM                        ((uint32_t)0x00400000)        /*!<  */\n#define RTC_ALRMAR_HT                        ((uint32_t)0x00300000)        /*!<  */\n#define RTC_ALRMAR_HT_0                      ((uint32_t)0x00100000)        /*!<  */\n#define RTC_ALRMAR_HT_1                      ((uint32_t)0x00200000)        /*!<  */\n#define RTC_ALRMAR_HU                        ((uint32_t)0x000F0000)        /*!<  */\n#define RTC_ALRMAR_HU_0                      ((uint32_t)0x00010000)        /*!<  */\n#define RTC_ALRMAR_HU_1                      ((uint32_t)0x00020000)        /*!<  */\n#define RTC_ALRMAR_HU_2                      ((uint32_t)0x00040000)        /*!<  */\n#define RTC_ALRMAR_HU_3                      ((uint32_t)0x00080000)        /*!<  */\n#define RTC_ALRMAR_MSK2                      ((uint32_t)0x00008000)        /*!<  */\n#define RTC_ALRMAR_MNT                       ((uint32_t)0x00007000)        /*!<  */\n#define RTC_ALRMAR_MNT_0                     ((uint32_t)0x00001000)        /*!<  */\n#define RTC_ALRMAR_MNT_1                     ((uint32_t)0x00002000)        /*!<  */\n#define RTC_ALRMAR_MNT_2                     ((uint32_t)0x00004000)        /*!<  */\n#define RTC_ALRMAR_MNU                       ((uint32_t)0x00000F00)        /*!<  */\n#define RTC_ALRMAR_MNU_0                     ((uint32_t)0x00000100)        /*!<  */\n#define RTC_ALRMAR_MNU_1                     ((uint32_t)0x00000200)        /*!<  */\n#define RTC_ALRMAR_MNU_2                     ((uint32_t)0x00000400)        /*!<  */\n#define RTC_ALRMAR_MNU_3                     ((uint32_t)0x00000800)        /*!<  */\n#define RTC_ALRMAR_MSK1                      ((uint32_t)0x00000080)        /*!<  */\n#define RTC_ALRMAR_ST                        ((uint32_t)0x00000070)        /*!<  */\n#define RTC_ALRMAR_ST_0                      ((uint32_t)0x00000010)        /*!<  */\n#define RTC_ALRMAR_ST_1                      ((uint32_t)0x00000020)        /*!<  */\n#define RTC_ALRMAR_ST_2                      ((uint32_t)0x00000040)        /*!<  */\n#define RTC_ALRMAR_SU                        ((uint32_t)0x0000000F)        /*!<  */\n#define RTC_ALRMAR_SU_0                      ((uint32_t)0x00000001)        /*!<  */\n#define RTC_ALRMAR_SU_1                      ((uint32_t)0x00000002)        /*!<  */\n#define RTC_ALRMAR_SU_2                      ((uint32_t)0x00000004)        /*!<  */\n#define RTC_ALRMAR_SU_3                      ((uint32_t)0x00000008)        /*!<  */\n\n/********************  Bits definition for RTC_ALRMBR register  ***************/\n#define RTC_ALRMBR_MSK4                      ((uint32_t)0x80000000)        /*!<  */\n#define RTC_ALRMBR_WDSEL                     ((uint32_t)0x40000000)        /*!<  */\n#define RTC_ALRMBR_DT                        ((uint32_t)0x30000000)        /*!<  */\n#define RTC_ALRMBR_DT_0                      ((uint32_t)0x10000000)        /*!<  */\n#define RTC_ALRMBR_DT_1                      ((uint32_t)0x20000000)        /*!<  */\n#define RTC_ALRMBR_DU                        ((uint32_t)0x0F000000)        /*!<  */\n#define RTC_ALRMBR_DU_0                      ((uint32_t)0x01000000)        /*!<  */\n#define RTC_ALRMBR_DU_1                      ((uint32_t)0x02000000)        /*!<  */\n#define RTC_ALRMBR_DU_2                      ((uint32_t)0x04000000)        /*!<  */\n#define RTC_ALRMBR_DU_3                      ((uint32_t)0x08000000)        /*!<  */\n#define RTC_ALRMBR_MSK3                      ((uint32_t)0x00800000)        /*!<  */\n#define RTC_ALRMBR_PM                        ((uint32_t)0x00400000)        /*!<  */\n#define RTC_ALRMBR_HT                        ((uint32_t)0x00300000)        /*!<  */\n#define RTC_ALRMBR_HT_0                      ((uint32_t)0x00100000)        /*!<  */\n#define RTC_ALRMBR_HT_1                      ((uint32_t)0x00200000)        /*!<  */\n#define RTC_ALRMBR_HU                        ((uint32_t)0x000F0000)        /*!<  */\n#define RTC_ALRMBR_HU_0                      ((uint32_t)0x00010000)        /*!<  */\n#define RTC_ALRMBR_HU_1                      ((uint32_t)0x00020000)        /*!<  */\n#define RTC_ALRMBR_HU_2                      ((uint32_t)0x00040000)        /*!<  */\n#define RTC_ALRMBR_HU_3                      ((uint32_t)0x00080000)        /*!<  */\n#define RTC_ALRMBR_MSK2                      ((uint32_t)0x00008000)        /*!<  */\n#define RTC_ALRMBR_MNT                       ((uint32_t)0x00007000)        /*!<  */\n#define RTC_ALRMBR_MNT_0                     ((uint32_t)0x00001000)        /*!<  */\n#define RTC_ALRMBR_MNT_1                     ((uint32_t)0x00002000)        /*!<  */\n#define RTC_ALRMBR_MNT_2                     ((uint32_t)0x00004000)        /*!<  */\n#define RTC_ALRMBR_MNU                       ((uint32_t)0x00000F00)        /*!<  */\n#define RTC_ALRMBR_MNU_0                     ((uint32_t)0x00000100)        /*!<  */\n#define RTC_ALRMBR_MNU_1                     ((uint32_t)0x00000200)        /*!<  */\n#define RTC_ALRMBR_MNU_2                     ((uint32_t)0x00000400)        /*!<  */\n#define RTC_ALRMBR_MNU_3                     ((uint32_t)0x00000800)        /*!<  */\n#define RTC_ALRMBR_MSK1                      ((uint32_t)0x00000080)        /*!<  */\n#define RTC_ALRMBR_ST                        ((uint32_t)0x00000070)        /*!<  */\n#define RTC_ALRMBR_ST_0                      ((uint32_t)0x00000010)        /*!<  */\n#define RTC_ALRMBR_ST_1                      ((uint32_t)0x00000020)        /*!<  */\n#define RTC_ALRMBR_ST_2                      ((uint32_t)0x00000040)        /*!<  */\n#define RTC_ALRMBR_SU                        ((uint32_t)0x0000000F)        /*!<  */\n#define RTC_ALRMBR_SU_0                      ((uint32_t)0x00000001)        /*!<  */\n#define RTC_ALRMBR_SU_1                      ((uint32_t)0x00000002)        /*!<  */\n#define RTC_ALRMBR_SU_2                      ((uint32_t)0x00000004)        /*!<  */\n#define RTC_ALRMBR_SU_3                      ((uint32_t)0x00000008)        /*!<  */\n\n/********************  Bits definition for RTC_WPR register  ******************/\n#define RTC_WPR_KEY                          ((uint32_t)0x000000FF)        /*!<  */\n\n/********************  Bits definition for RTC_SSR register  ******************/\n#define RTC_SSR_SS                           ((uint32_t)0x0000FFFF)        /*!<  */\n\n/********************  Bits definition for RTC_SHIFTR register  ***************/\n#define RTC_SHIFTR_SUBFS                     ((uint32_t)0x00007FFF)        /*!<  */\n#define RTC_SHIFTR_ADD1S                     ((uint32_t)0x80000000)        /*!<  */\n\n/********************  Bits definition for RTC_TSTR register  *****************/\n#define RTC_TSTR_PM                          ((uint32_t)0x00400000)        /*!<  */\n#define RTC_TSTR_HT                          ((uint32_t)0x00300000)        /*!<  */\n#define RTC_TSTR_HT_0                        ((uint32_t)0x00100000)        /*!<  */\n#define RTC_TSTR_HT_1                        ((uint32_t)0x00200000)        /*!<  */\n#define RTC_TSTR_HU                          ((uint32_t)0x000F0000)        /*!<  */\n#define RTC_TSTR_HU_0                        ((uint32_t)0x00010000)        /*!<  */\n#define RTC_TSTR_HU_1                        ((uint32_t)0x00020000)        /*!<  */\n#define RTC_TSTR_HU_2                        ((uint32_t)0x00040000)        /*!<  */\n#define RTC_TSTR_HU_3                        ((uint32_t)0x00080000)        /*!<  */\n#define RTC_TSTR_MNT                         ((uint32_t)0x00007000)        /*!<  */\n#define RTC_TSTR_MNT_0                       ((uint32_t)0x00001000)        /*!<  */\n#define RTC_TSTR_MNT_1                       ((uint32_t)0x00002000)        /*!<  */\n#define RTC_TSTR_MNT_2                       ((uint32_t)0x00004000)        /*!<  */\n#define RTC_TSTR_MNU                         ((uint32_t)0x00000F00)        /*!<  */\n#define RTC_TSTR_MNU_0                       ((uint32_t)0x00000100)        /*!<  */\n#define RTC_TSTR_MNU_1                       ((uint32_t)0x00000200)        /*!<  */\n#define RTC_TSTR_MNU_2                       ((uint32_t)0x00000400)        /*!<  */\n#define RTC_TSTR_MNU_3                       ((uint32_t)0x00000800)        /*!<  */\n#define RTC_TSTR_ST                          ((uint32_t)0x00000070)        /*!<  */\n#define RTC_TSTR_ST_0                        ((uint32_t)0x00000010)        /*!<  */\n#define RTC_TSTR_ST_1                        ((uint32_t)0x00000020)        /*!<  */\n#define RTC_TSTR_ST_2                        ((uint32_t)0x00000040)        /*!<  */\n#define RTC_TSTR_SU                          ((uint32_t)0x0000000F)        /*!<  */\n#define RTC_TSTR_SU_0                        ((uint32_t)0x00000001)        /*!<  */\n#define RTC_TSTR_SU_1                        ((uint32_t)0x00000002)        /*!<  */\n#define RTC_TSTR_SU_2                        ((uint32_t)0x00000004)        /*!<  */\n#define RTC_TSTR_SU_3                        ((uint32_t)0x00000008)        /*!<  */\n\n/********************  Bits definition for RTC_TSDR register  *****************/\n#define RTC_TSDR_WDU                         ((uint32_t)0x0000E000)        /*!<  */\n#define RTC_TSDR_WDU_0                       ((uint32_t)0x00002000)        /*!<  */\n#define RTC_TSDR_WDU_1                       ((uint32_t)0x00004000)        /*!<  */\n#define RTC_TSDR_WDU_2                       ((uint32_t)0x00008000)        /*!<  */\n#define RTC_TSDR_MT                          ((uint32_t)0x00001000)        /*!<  */\n#define RTC_TSDR_MU                          ((uint32_t)0x00000F00)        /*!<  */\n#define RTC_TSDR_MU_0                        ((uint32_t)0x00000100)        /*!<  */\n#define RTC_TSDR_MU_1                        ((uint32_t)0x00000200)        /*!<  */\n#define RTC_TSDR_MU_2                        ((uint32_t)0x00000400)        /*!<  */\n#define RTC_TSDR_MU_3                        ((uint32_t)0x00000800)        /*!<  */\n#define RTC_TSDR_DT                          ((uint32_t)0x00000030)        /*!<  */\n#define RTC_TSDR_DT_0                        ((uint32_t)0x00000010)        /*!<  */\n#define RTC_TSDR_DT_1                        ((uint32_t)0x00000020)        /*!<  */\n#define RTC_TSDR_DU                          ((uint32_t)0x0000000F)        /*!<  */\n#define RTC_TSDR_DU_0                        ((uint32_t)0x00000001)        /*!<  */\n#define RTC_TSDR_DU_1                        ((uint32_t)0x00000002)        /*!<  */\n#define RTC_TSDR_DU_2                        ((uint32_t)0x00000004)        /*!<  */\n#define RTC_TSDR_DU_3                        ((uint32_t)0x00000008)        /*!<  */\n\n/********************  Bits definition for RTC_TSSSR register  ****************/\n#define RTC_TSSSR_SS                         ((uint32_t)0x0000FFFF)\n\n/********************  Bits definition for RTC_CAL register  *****************/\n#define RTC_CAL_CALP                         ((uint32_t)0x00008000)        /*!<  */\n#define RTC_CAL_CALW8                        ((uint32_t)0x00004000)        /*!<  */\n#define RTC_CAL_CALW16                       ((uint32_t)0x00002000)        /*!<  */\n#define RTC_CAL_CALM                         ((uint32_t)0x000001FF)        /*!<  */\n#define RTC_CAL_CALM_0                       ((uint32_t)0x00000001)        /*!<  */\n#define RTC_CAL_CALM_1                       ((uint32_t)0x00000002)        /*!<  */\n#define RTC_CAL_CALM_2                       ((uint32_t)0x00000004)        /*!<  */\n#define RTC_CAL_CALM_3                       ((uint32_t)0x00000008)        /*!<  */\n#define RTC_CAL_CALM_4                       ((uint32_t)0x00000010)        /*!<  */\n#define RTC_CAL_CALM_5                       ((uint32_t)0x00000020)        /*!<  */\n#define RTC_CAL_CALM_6                       ((uint32_t)0x00000040)        /*!<  */\n#define RTC_CAL_CALM_7                       ((uint32_t)0x00000080)        /*!<  */\n#define RTC_CAL_CALM_8                       ((uint32_t)0x00000100)        /*!<  */\n\n/********************  Bits definition for RTC_TAMPCR register  ****************/\n#define RTC_TAMPCR_TAMP2MF                   ((uint32_t)0x00200000)        /*!<  */\n#define RTC_TAMPCR_TAMP2NOERASE              ((uint32_t)0x00100000)        /*!<  */\n#define RTC_TAMPCR_TAMP2IE                   ((uint32_t)0x00080000)        /*!<  */\n#define RTC_TAMPCR_TAMP1MF                   ((uint32_t)0x00040000)        /*!<  */\n#define RTC_TAMPCR_TAMP1NOERASE              ((uint32_t)0x00020000)        /*!<  */\n#define RTC_TAMPCR_TAMP1IE                   ((uint32_t)0x00010000)        /*!<  */\n#define RTC_TAMPCR_TAMPPUDIS                 ((uint32_t)0x00008000)        /*!<  */\n#define RTC_TAMPCR_TAMPPRCH                  ((uint32_t)0x00006000)        /*!<  */\n#define RTC_TAMPCR_TAMPPRCH_0                ((uint32_t)0x00002000)        /*!<  */\n#define RTC_TAMPCR_TAMPPRCH_1                ((uint32_t)0x00004000)        /*!<  */\n#define RTC_TAMPCR_TAMPFLT                   ((uint32_t)0x00001800)        /*!<  */\n#define RTC_TAMPCR_TAMPFLT_0                 ((uint32_t)0x00000800)        /*!<  */\n#define RTC_TAMPCR_TAMPFLT_1                 ((uint32_t)0x00001000)        /*!<  */\n#define RTC_TAMPCR_TAMPFREQ                  ((uint32_t)0x00000700)        /*!<  */\n#define RTC_TAMPCR_TAMPFREQ_0                ((uint32_t)0x00000100)        /*!<  */\n#define RTC_TAMPCR_TAMPFREQ_1                ((uint32_t)0x00000200)        /*!<  */\n#define RTC_TAMPCR_TAMPFREQ_2                ((uint32_t)0x00000400)        /*!<  */\n#define RTC_TAMPCR_TAMPTS                    ((uint32_t)0x00000080)        /*!<  */\n#define RTC_TAMPCR_TAMP2TRG                  ((uint32_t)0x00000010)        /*!<  */\n#define RTC_TAMPCR_TAMP2E                    ((uint32_t)0x00000008)        /*!<  */\n#define RTC_TAMPCR_TAMPIE                    ((uint32_t)0x00000004)        /*!<  */\n#define RTC_TAMPCR_TAMP1TRG                  ((uint32_t)0x00000002)        /*!<  */\n#define RTC_TAMPCR_TAMP1E                    ((uint32_t)0x00000001)        /*!<  */\n\n/********************  Bits definition for RTC_ALRMASSR register  *************/\n#define RTC_ALRMASSR_MASKSS                  ((uint32_t)0x0F000000)\n#define RTC_ALRMASSR_MASKSS_0                ((uint32_t)0x01000000)\n#define RTC_ALRMASSR_MASKSS_1                ((uint32_t)0x02000000)\n#define RTC_ALRMASSR_MASKSS_2                ((uint32_t)0x04000000)\n#define RTC_ALRMASSR_MASKSS_3                ((uint32_t)0x08000000)\n#define RTC_ALRMASSR_SS                      ((uint32_t)0x00007FFF)\n\n/********************  Bits definition for RTC_ALRMBSSR register  *************/\n#define RTC_ALRMBSSR_MASKSS                  ((uint32_t)0x0F000000)\n#define RTC_ALRMBSSR_MASKSS_0                ((uint32_t)0x01000000)\n#define RTC_ALRMBSSR_MASKSS_1                ((uint32_t)0x02000000)\n#define RTC_ALRMBSSR_MASKSS_2                ((uint32_t)0x04000000)\n#define RTC_ALRMBSSR_MASKSS_3                ((uint32_t)0x08000000)\n#define RTC_ALRMBSSR_SS                      ((uint32_t)0x00007FFF)\n\n/********************  Bits definition for RTC_OR register  ****************/\n#define RTC_OR_RTC_OUT_RMP                   ((uint32_t)0x00000002)        /*!<  */\n#define RTC_OR_ALARMOUTTYPE                  ((uint32_t)0x00000001)        /*!<  */\n\n/********************  Bits definition for RTC_BKP0R register  ****************/\n#define RTC_BKP0R                            ((uint32_t)0xFFFFFFFF)        /*!<  */\n\n/********************  Bits definition for RTC_BKP1R register  ****************/\n#define RTC_BKP1R                            ((uint32_t)0xFFFFFFFF)        /*!<  */\n\n/********************  Bits definition for RTC_BKP2R register  ****************/\n#define RTC_BKP2R                            ((uint32_t)0xFFFFFFFF)        /*!<  */\n\n/********************  Bits definition for RTC_BKP3R register  ****************/\n#define RTC_BKP3R                            ((uint32_t)0xFFFFFFFF)        /*!<  */\n\n/********************  Bits definition for RTC_BKP4R register  ****************/\n#define RTC_BKP4R                            ((uint32_t)0xFFFFFFFF)        /*!<  */\n\n/******************************************************************************/\n/*                                                                            */\n/*                        Serial Peripheral Interface (SPI)                   */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for SPI_CR1 register  ********************/\n#define  SPI_CR1_CPHA                        ((uint16_t)0x0001)            /*!< Clock Phase */\n#define  SPI_CR1_CPOL                        ((uint16_t)0x0002)            /*!< Clock Polarity */\n#define  SPI_CR1_MSTR                        ((uint16_t)0x0004)            /*!< Master Selection */\n#define  SPI_CR1_BR                          ((uint16_t)0x0038)            /*!< BR[2:0] bits (Baud Rate Control) */\n#define  SPI_CR1_BR_0                        ((uint16_t)0x0008)            /*!< Bit 0 */\n#define  SPI_CR1_BR_1                        ((uint16_t)0x0010)            /*!< Bit 1 */\n#define  SPI_CR1_BR_2                        ((uint16_t)0x0020)            /*!< Bit 2 */\n#define  SPI_CR1_SPE                         ((uint16_t)0x0040)            /*!< SPI Enable */\n#define  SPI_CR1_LSBFIRST                    ((uint16_t)0x0080)            /*!< Frame Format */\n#define  SPI_CR1_SSI                         ((uint16_t)0x0100)            /*!< Internal slave select */\n#define  SPI_CR1_SSM                         ((uint16_t)0x0200)            /*!< Software slave management */\n#define  SPI_CR1_RXONLY                      ((uint16_t)0x0400)            /*!< Receive only */\n#define  SPI_CR1_DFF                         ((uint16_t)0x0800)            /*!< Data Frame Format */\n#define  SPI_CR1_CRCNEXT                     ((uint16_t)0x1000)            /*!< Transmit CRC next */\n#define  SPI_CR1_CRCEN                       ((uint16_t)0x2000)            /*!< Hardware CRC calculation enable */\n#define  SPI_CR1_BIDIOE                      ((uint16_t)0x4000)            /*!< Output enable in bidirectional mode */\n#define  SPI_CR1_BIDIMODE                    ((uint16_t)0x8000)            /*!< Bidirectional data mode enable */\n\n/*******************  Bit definition for SPI_CR2 register  ********************/\n#define  SPI_CR2_RXDMAEN                     ((uint16_t)0x0001)            /*!< Rx Buffer DMA Enable */\n#define  SPI_CR2_TXDMAEN                     ((uint16_t)0x0002)            /*!< Tx Buffer DMA Enable */\n#define  SPI_CR2_SSOE                        ((uint16_t)0x0004)            /*!< SS Output Enable */\n#define  SPI_CR2_FRF                         ((uint16_t)0x0010)            /*!< Frame Format Enable */\n#define  SPI_CR2_ERRIE                       ((uint16_t)0x0020)            /*!< Error Interrupt Enable */\n#define  SPI_CR2_RXNEIE                      ((uint16_t)0x0040)            /*!< RX buffer Not Empty Interrupt Enable */\n#define  SPI_CR2_TXEIE                       ((uint16_t)0x0080)            /*!< Tx buffer Empty Interrupt Enable */\n\n/********************  Bit definition for SPI_SR register  ********************/\n#define  SPI_SR_RXNE                         ((uint16_t)0x0001)            /*!< Receive buffer Not Empty */\n#define  SPI_SR_TXE                          ((uint16_t)0x0002)            /*!< Transmit buffer Empty */\n#define  SPI_SR_CHSIDE                       ((uint16_t)0x0004)            /*!< Channel side */\n#define  SPI_SR_UDR                          ((uint16_t)0x0008)            /*!< Underrun flag */\n#define  SPI_SR_CRCERR                       ((uint16_t)0x0010)            /*!< CRC Error flag */\n#define  SPI_SR_MODF                         ((uint16_t)0x0020)            /*!< Mode fault */\n#define  SPI_SR_OVR                          ((uint16_t)0x0040)            /*!< Overrun flag */\n#define  SPI_SR_BSY                          ((uint16_t)0x0080)            /*!< Busy flag */\n#define  SPI_SR_FRE                          ((uint16_t)0x0100)            /*!< TI frame format error */\n\n/********************  Bit definition for SPI_DR register  ********************/\n#define  SPI_DR_DR                           ((uint16_t)0xFFFF)            /*!< Data Register */\n\n/*******************  Bit definition for SPI_CRCPR register  ******************/\n#define  SPI_CRCPR_CRCPOLY                   ((uint16_t)0xFFFF)            /*!< CRC polynomial register */\n\n/******************  Bit definition for SPI_RXCRCR register  ******************/\n#define  SPI_RXCRCR_RXCRC                    ((uint16_t)0xFFFF)            /*!< Rx CRC Register */\n\n/******************  Bit definition for SPI_TXCRCR register  ******************/\n#define  SPI_TXCRCR_TXCRC                    ((uint16_t)0xFFFF)            /*!< Tx CRC Register */\n\n/******************  Bit definition for SPI_I2SCFGR register  *****************/\n#define  SPI_I2SCFGR_CHLEN                   ((uint16_t)0x0001)            /*!<Channel length (number of bits per audio channel) */\n#define  SPI_I2SCFGR_DATLEN                  ((uint16_t)0x0006)            /*!<DATLEN[1:0] bits (Data length to be transferred) */\n#define  SPI_I2SCFGR_DATLEN_0                ((uint16_t)0x0002)            /*!<Bit 0 */\n#define  SPI_I2SCFGR_DATLEN_1                ((uint16_t)0x0004)            /*!<Bit 1 */\n#define  SPI_I2SCFGR_CKPOL                   ((uint16_t)0x0008)            /*!<steady state clock polarity */\n#define  SPI_I2SCFGR_I2SSTD                  ((uint16_t)0x0030)            /*!<I2SSTD[1:0] bits (I2S standard selection) */\n#define  SPI_I2SCFGR_I2SSTD_0                ((uint16_t)0x0010)            /*!<Bit 0 */\n#define  SPI_I2SCFGR_I2SSTD_1                ((uint16_t)0x0020)            /*!<Bit 1 */\n#define  SPI_I2SCFGR_PCMSYNC                 ((uint16_t)0x0080)            /*!<PCM frame synchronization */\n#define  SPI_I2SCFGR_I2SCFG                  ((uint16_t)0x0300)            /*!<I2SCFG[1:0] bits (I2S configuration mode) */\n#define  SPI_I2SCFGR_I2SCFG_0                ((uint16_t)0x0100)            /*!<Bit 0 */\n#define  SPI_I2SCFGR_I2SCFG_1                ((uint16_t)0x0200)            /*!<Bit 1 */\n#define  SPI_I2SCFGR_I2SE                    ((uint16_t)0x0400)            /*!<I2S Enable */\n#define  SPI_I2SCFGR_I2SMOD                  ((uint16_t)0x0800)            /*!<I2S mode selection */\n\n/******************  Bit definition for SPI_I2SPR register  *******************/\n#define  SPI_I2SPR_I2SDIV                    ((uint16_t)0x00FF)            /*!<I2S Linear prescaler */\n#define  SPI_I2SPR_ODD                       ((uint16_t)0x0100)            /*!<Odd factor for the prescaler */\n#define  SPI_I2SPR_MCKOE                     ((uint16_t)0x0200)            /*!<Master Clock Output Enable */\n\n/******************************************************************************/\n/*                                                                            */\n/*                       System Configuration (SYSCFG)                        */\n/*                                                                            */\n/******************************************************************************/\n/*****************  Bit definition for SYSCFG_CFGR1 register  ****************/\n#define SYSCFG_CFGR1_MEM_MODE               ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */\n#define SYSCFG_CFGR1_MEM_MODE_0             ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */\n#define SYSCFG_CFGR1_MEM_MODE_1             ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */\n#define SYSCFG_CFGR1_BOOT_MODE              ((uint32_t)0x00000300) /*!< SYSCFG_Boot mode Config */\n#define SYSCFG_CFGR1_BOOT_MOD_0            ((uint32_t)0x00000100) /*!< SYSCFG_Boot mode Config Bit 0 */\n#define SYSCFG_CFGR1_BOOT_MODE_1            ((uint32_t)0x00000200) /*!< SYSCFG_Boot mode Config Bit 1 */\n\n/*****************  Bit definition for SYSCFG_CFGR2 register  ****************/\n#define SYSCFG_CFGR2_FWDISEN                ((uint32_t)0x00000001) /*!< Firewall disable bit */\n#define SYSCFG_CFGR2_CAPA                   ((uint32_t)0x0000000E) /*!< Connection of internal Vlcd rail to external capacitors */\n#define SYSCFG_CFGR2_CAPA_0                 ((uint32_t)0x00000002)\n#define SYSCFG_CFGR2_CAPA_1                 ((uint32_t)0x00000004)\n#define SYSCFG_CFGR2_CAPA_2                 ((uint32_t)0x00000008)\n#define SYSCFG_CFGR2_I2C_PB6_FMP            ((uint32_t)0x00000100) /*!< I2C PB6 Fast mode plus */\n#define SYSCFG_CFGR2_I2C_PB7_FMP            ((uint32_t)0x00000200) /*!< I2C PB7 Fast mode plus */\n#define SYSCFG_CFGR2_I2C_PB8_FMP            ((uint32_t)0x00000400) /*!< I2C PB8 Fast mode plus */\n#define SYSCFG_CFGR2_I2C_PB9_FMP            ((uint32_t)0x00000800) /*!< I2C PB9 Fast mode plus */\n#define SYSCFG_CFGR2_I2C1_FMP               ((uint32_t)0x00001000) /*!< I2C1 Fast mode plus */\n#define SYSCFG_CFGR2_I2C2_FMP               ((uint32_t)0x00002000) /*!< I2C2 Fast mode plus */\n\n/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/\n#define SYSCFG_EXTICR1_EXTI0            ((uint16_t)0x000F) /*!< EXTI 0 configuration */\n#define SYSCFG_EXTICR1_EXTI1            ((uint16_t)0x00F0) /*!< EXTI 1 configuration */\n#define SYSCFG_EXTICR1_EXTI2            ((uint16_t)0x0F00) /*!< EXTI 2 configuration */\n#define SYSCFG_EXTICR1_EXTI3            ((uint16_t)0xF000) /*!< EXTI 3 configuration */\n\n/**\n  * @brief  EXTI0 configuration\n  */\n#define SYSCFG_EXTICR1_EXTI0_PA         ((uint16_t)0x0000) /*!< PA[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PB         ((uint16_t)0x0001) /*!< PB[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PC         ((uint16_t)0x0002) /*!< PC[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PH         ((uint16_t)0x0005) /*!< PH[0] pin */\n\n/**\n  * @brief  EXTI1 configuration\n  */\n#define SYSCFG_EXTICR1_EXTI1_PA         ((uint16_t)0x0000) /*!< PA[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PB         ((uint16_t)0x0010) /*!< PB[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PC         ((uint16_t)0x0020) /*!< PC[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PH         ((uint16_t)0x0050) /*!< PH[1] pin */\n\n/**\n  * @brief  EXTI2 configuration\n  */\n#define SYSCFG_EXTICR1_EXTI2_PA         ((uint16_t)0x0000) /*!< PA[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PB         ((uint16_t)0x0100) /*!< PB[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PC         ((uint16_t)0x0200) /*!< PC[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PD         ((uint16_t)0x0300) /*!< PD[2] pin */\n\n/**\n  * @brief  EXTI3 configuration\n  */\n#define SYSCFG_EXTICR1_EXTI3_PA         ((uint16_t)0x0000) /*!< PA[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PB         ((uint16_t)0x1000) /*!< PB[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PC         ((uint16_t)0x2000) /*!< PC[3] pin */\n\n/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/\n#define SYSCFG_EXTICR2_EXTI4            ((uint16_t)0x000F) /*!< EXTI 4 configuration */\n#define SYSCFG_EXTICR2_EXTI5            ((uint16_t)0x00F0) /*!< EXTI 5 configuration */\n#define SYSCFG_EXTICR2_EXTI6            ((uint16_t)0x0F00) /*!< EXTI 6 configuration */\n#define SYSCFG_EXTICR2_EXTI7            ((uint16_t)0xF000) /*!< EXTI 7 configuration */\n\n/**\n  * @brief  EXTI4 configuration\n  */\n#define SYSCFG_EXTICR2_EXTI4_PA         ((uint16_t)0x0000) /*!< PA[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PB         ((uint16_t)0x0001) /*!< PB[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PC         ((uint16_t)0x0002) /*!< PC[4] pin */\n\n\n/**\n  * @brief  EXTI5 configuration\n  */\n#define SYSCFG_EXTICR2_EXTI5_PA         ((uint16_t)0x0000) /*!< PA[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PB         ((uint16_t)0x0010) /*!< PB[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PC         ((uint16_t)0x0020) /*!< PC[5] pin */\n\n/**\n  * @brief  EXTI6 configuration\n  */\n#define SYSCFG_EXTICR2_EXTI6_PA         ((uint16_t)0x0000) /*!< PA[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PB         ((uint16_t)0x0100) /*!< PB[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PC         ((uint16_t)0x0200) /*!< PC[6] pin */\n\n/**\n  * @brief  EXTI7 configuration\n  */\n#define SYSCFG_EXTICR2_EXTI7_PA         ((uint16_t)0x0000) /*!< PA[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PB         ((uint16_t)0x1000) /*!< PB[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PC         ((uint16_t)0x2000) /*!< PC[7] pin */\n\n/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/\n#define SYSCFG_EXTICR3_EXTI8            ((uint16_t)0x000F) /*!< EXTI 8 configuration */\n#define SYSCFG_EXTICR3_EXTI9            ((uint16_t)0x00F0) /*!< EXTI 9 configuration */\n#define SYSCFG_EXTICR3_EXTI10           ((uint16_t)0x0F00) /*!< EXTI 10 configuration */\n#define SYSCFG_EXTICR3_EXTI11           ((uint16_t)0xF000) /*!< EXTI 11 configuration */\n\n/**\n  * @brief  EXTI8 configuration\n  */\n#define SYSCFG_EXTICR3_EXTI8_PA         ((uint16_t)0x0000) /*!< PA[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PB         ((uint16_t)0x0001) /*!< PB[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PC         ((uint16_t)0x0002) /*!< PC[8] pin */\n\n/**\n  * @brief  EXTI9 configuration\n  */\n#define SYSCFG_EXTICR3_EXTI9_PA         ((uint16_t)0x0000) /*!< PA[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PB         ((uint16_t)0x0010) /*!< PB[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PC         ((uint16_t)0x0020) /*!< PC[9] pin */\n\n/**\n  * @brief  EXTI10 configuration\n  */\n#define SYSCFG_EXTICR3_EXTI10_PA        ((uint16_t)0x0000) /*!< PA[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PB        ((uint16_t)0x0100) /*!< PB[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PC        ((uint16_t)0x0200) /*!< PC[10] pin */\n\n/**\n  * @brief  EXTI11 configuration\n  */\n#define SYSCFG_EXTICR3_EXTI11_PA        ((uint16_t)0x0000) /*!< PA[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PB        ((uint16_t)0x1000) /*!< PB[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PC        ((uint16_t)0x2000) /*!< PC[11] pin */\n\n/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/\n#define SYSCFG_EXTICR4_EXTI12           ((uint16_t)0x000F) /*!< EXTI 12 configuration */\n#define SYSCFG_EXTICR4_EXTI13           ((uint16_t)0x00F0) /*!< EXTI 13 configuration */\n#define SYSCFG_EXTICR4_EXTI14           ((uint16_t)0x0F00) /*!< EXTI 14 configuration */\n#define SYSCFG_EXTICR4_EXTI15           ((uint16_t)0xF000) /*!< EXTI 15 configuration */\n\n/**\n  * @brief  EXTI12 configuration\n  */\n#define SYSCFG_EXTICR4_EXTI12_PA        ((uint16_t)0x0000) /*!< PA[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PB        ((uint16_t)0x0001) /*!< PB[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PC        ((uint16_t)0x0002) /*!< PC[12] pin */\n\n/**\n  * @brief  EXTI13 configuration\n  */\n#define SYSCFG_EXTICR4_EXTI13_PA        ((uint16_t)0x0000) /*!< PA[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PB        ((uint16_t)0x0010) /*!< PB[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PC        ((uint16_t)0x0020) /*!< PC[13] pin */\n\n/**\n  * @brief  EXTI14 configuration\n  */\n#define SYSCFG_EXTICR4_EXTI14_PA        ((uint16_t)0x0000) /*!< PA[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PB        ((uint16_t)0x0100) /*!< PB[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PC        ((uint16_t)0x0200) /*!< PC[14] pin */\n\n/**\n  * @brief  EXTI15 configuration\n  */\n#define SYSCFG_EXTICR4_EXTI15_PA        ((uint16_t)0x0000) /*!< PA[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PB        ((uint16_t)0x1000) /*!< PB[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PC        ((uint16_t)0x2000) /*!< PC[15] pin */\n\n\n/*****************  Bit definition for SYSCFG_CFGR3 register  ****************/\n#define SYSCFG_CFGR3_EN_BGAP                  ((uint32_t)0x00000001) /*!< Vref Enable bit*/\n#define SYSCFG_CFGR3_VREF_OUT                 ((uint32_t)0x00000030) /*!< BGAP_ADC connection bit */\n#define SYSCFG_CFGR3_VREF_OUT_0               ((uint32_t)0x00000010) /*!< Bit 0 */\n#define SYSCFG_CFGR3_VREF_OUT_1               ((uint32_t)0x00000020) /*!< Bit 1 */\n#define SYSCFG_CFGR3_ENBUF_BGAP_ADC           ((uint32_t)0x00000100) /*!< VREFINT reference for ADC enable bit */\n#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC         ((uint32_t)0x00000200) /*!< Sensor reference for ADC enable bit */\n#define SYSCFG_CFGR3_ENBUFLP_BGAP_COMP        ((uint32_t)0x00001000) /*!< VREFINT reference for comparator 2 enable bit */\n#define SYSCFG_CFGR3_ENREF_RC48MHz            ((uint32_t)0x00002000) /*!< VREFINT reference or 48 MHz RC oscillator enable bit */\n#define SYSCFG_CFGR3_REF_RC48MHz_RDYF         ((uint32_t)0x04000000) /*!< VREFINT for 48 MHz RC oscillator ready flag */\n#define SYSCFG_CFGR3_SENSOR_ADC_RDYF          ((uint32_t)0x08000000) /*!< Sensor for ADC ready flag */\n#define SYSCFG_VREFINT_ADC_RDYF              ((uint32_t)0x10000000) /*!< VREFINT for ADC ready flag */\n#define SYSCFG_CFGR3_VREFINT_COMP_RDYF        ((uint32_t)0x20000000) /*!< VREFINT for comparator ready flag */\n#define SYSCFG_CFGR3_VREFINT_RDYF             ((uint32_t)0x40000000) /*!< VREFINT ready flag */\n#define SYSCFG_CFGR3_REF_LOCK                 ((uint32_t)0x80000000) /*!< REF_CTRL lock bit */\n\n/******************************************************************************/\n/*                                                                            */\n/*                               Timers (TIM)                                 */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for TIM_CR1 register  ********************/\n#define  TIM_CR1_CEN                         ((uint32_t)0x00000001)            /*!<Counter enable */\n#define  TIM_CR1_UDIS                        ((uint32_t)0x00000002)            /*!<Update disable */\n#define  TIM_CR1_URS                         ((uint32_t)0x00000004)            /*!<Update request source */\n#define  TIM_CR1_OPM                         ((uint32_t)0x00000008)            /*!<One pulse mode */\n#define  TIM_CR1_DIR                         ((uint32_t)0x00000010)            /*!<Direction */\n\n#define  TIM_CR1_CMS                         ((uint32_t)0x00000060)            /*!<CMS[1:0] bits (Center-aligned mode selection) */\n#define  TIM_CR1_CMS_0                       ((uint32_t)0x00000020)            /*!<Bit 0 */\n#define  TIM_CR1_CMS_1                       ((uint32_t)0x00000040)            /*!<Bit 1 */\n\n#define  TIM_CR1_ARPE                        ((uint32_t)0x00000080)            /*!<Auto-reload preload enable */\n\n#define  TIM_CR1_CKD                         ((uint32_t)0x00000300)            /*!<CKD[1:0] bits (clock division) */\n#define  TIM_CR1_CKD_0                       ((uint32_t)0x00000100)            /*!<Bit 0 */\n#define  TIM_CR1_CKD_1                       ((uint32_t)0x00000200)            /*!<Bit 1 */\n\n/*******************  Bit definition for TIM_CR2 register  ********************/\n#define  TIM_CR2_CCPC                        ((uint32_t)0x00000001)            /*!<Capture/Compare Preloaded Control */\n#define  TIM_CR2_CCUS                        ((uint32_t)0x00000004)            /*!<Capture/Compare Control Update Selection */\n#define  TIM_CR2_CCDS                        ((uint32_t)0x00000008)            /*!<Capture/Compare DMA Selection */\n\n#define  TIM_CR2_MMS                         ((uint32_t)0x00000070)            /*!<MMS[2:0] bits (Master Mode Selection) */\n#define  TIM_CR2_MMS_0                       ((uint32_t)0x00000010)            /*!<Bit 0 */\n#define  TIM_CR2_MMS_1                       ((uint32_t)0x00000020)            /*!<Bit 1 */\n#define  TIM_CR2_MMS_2                       ((uint32_t)0x00000040)            /*!<Bit 2 */\n\n#define  TIM_CR2_TI1S                        ((uint32_t)0x00000080)            /*!<TI1 Selection */\n#define  TIM_CR2_OIS1                        ((uint32_t)0x00000100)            /*!<Output Idle state 1 (OC1 output) */\n#define  TIM_CR2_OIS1N                       ((uint32_t)0x00000200)            /*!<Output Idle state 1 (OC1N output) */\n#define  TIM_CR2_OIS2                        ((uint32_t)0x00000400)            /*!<Output Idle state 2 (OC2 output) */\n#define  TIM_CR2_OIS2N                       ((uint32_t)0x00000800)            /*!<Output Idle state 2 (OC2N output) */\n#define  TIM_CR2_OIS3                        ((uint32_t)0x00001000)            /*!<Output Idle state 3 (OC3 output) */\n#define  TIM_CR2_OIS3N                       ((uint32_t)0x00002000)            /*!<Output Idle state 3 (OC3N output) */\n#define  TIM_CR2_OIS4                        ((uint32_t)0x00004000)            /*!<Output Idle state 4 (OC4 output) */\n\n/*******************  Bit definition for TIM_SMCR register  *******************/\n#define  TIM_SMCR_SMS                        ((uint32_t)0x00000007)            /*!<SMS[2:0] bits (Slave mode selection) */\n#define  TIM_SMCR_SMS_0                      ((uint32_t)0x00000001)            /*!<Bit 0 */\n#define  TIM_SMCR_SMS_1                      ((uint32_t)0x00000002)            /*!<Bit 1 */\n#define  TIM_SMCR_SMS_2                      ((uint32_t)0x00000004)            /*!<Bit 2 */\n\n#define  TIM_SMCR_OCCS                       ((uint32_t)0x00000008)            /*!< OCREF clear selection */\n\n#define  TIM_SMCR_TS                         ((uint32_t)0x00000070)            /*!<TS[2:0] bits (Trigger selection) */\n#define  TIM_SMCR_TS_0                       ((uint32_t)0x00000010)            /*!<Bit 0 */\n#define  TIM_SMCR_TS_1                       ((uint32_t)0x00000020)            /*!<Bit 1 */\n#define  TIM_SMCR_TS_2                       ((uint32_t)0x00000040)            /*!<Bit 2 */\n\n#define  TIM_SMCR_MSM                        ((uint32_t)0x00000080)            /*!<Master/slave mode */\n\n#define  TIM_SMCR_ETF                        ((uint32_t)0x00000F00)            /*!<ETF[3:0] bits (External trigger filter) */\n#define  TIM_SMCR_ETF_0                      ((uint32_t)0x00000100)            /*!<Bit 0 */\n#define  TIM_SMCR_ETF_1                      ((uint32_t)0x00000200)            /*!<Bit 1 */\n#define  TIM_SMCR_ETF_2                      ((uint32_t)0x00000400)            /*!<Bit 2 */\n#define  TIM_SMCR_ETF_3                      ((uint32_t)0x00000800)            /*!<Bit 3 */\n\n#define  TIM_SMCR_ETPS                       ((uint32_t)0x00003000)            /*!<ETPS[1:0] bits (External trigger prescaler) */\n#define  TIM_SMCR_ETPS_0                     ((uint32_t)0x00001000)            /*!<Bit 0 */\n#define  TIM_SMCR_ETPS_1                     ((uint32_t)0x00002000)            /*!<Bit 1 */\n\n#define  TIM_SMCR_ECE                        ((uint32_t)0x00004000)            /*!<External clock enable */\n#define  TIM_SMCR_ETP                        ((uint32_t)0x00008000)            /*!<External trigger polarity */\n\n/*******************  Bit definition for TIM_DIER register  *******************/\n#define  TIM_DIER_UIE                        ((uint32_t)0x00000001)            /*!<Update interrupt enable */\n#define  TIM_DIER_CC1IE                      ((uint32_t)0x00000002)            /*!<Capture/Compare 1 interrupt enable */\n#define  TIM_DIER_CC2IE                      ((uint32_t)0x00000004)            /*!<Capture/Compare 2 interrupt enable */\n#define  TIM_DIER_CC3IE                      ((uint32_t)0x00000008)            /*!<Capture/Compare 3 interrupt enable */\n#define  TIM_DIER_CC4IE                      ((uint32_t)0x00000010)            /*!<Capture/Compare 4 interrupt enable */\n#define  TIM_DIER_COMIE                      ((uint32_t)0x00000020)            /*!<COM interrupt enable */\n#define  TIM_DIER_TIE                        ((uint32_t)0x00000040)            /*!<Trigger interrupt enable */\n#define  TIM_DIER_BIE                        ((uint32_t)0x00000080)            /*!<Break interrupt enable */\n#define  TIM_DIER_UDE                        ((uint32_t)0x00000100)            /*!<Update DMA request enable */\n#define  TIM_DIER_CC1DE                      ((uint32_t)0x00000200)            /*!<Capture/Compare 1 DMA request enable */\n#define  TIM_DIER_CC2DE                      ((uint32_t)0x00000400)            /*!<Capture/Compare 2 DMA request enable */\n#define  TIM_DIER_CC3DE                      ((uint32_t)0x00000800)            /*!<Capture/Compare 3 DMA request enable */\n#define  TIM_DIER_CC4DE                      ((uint32_t)0x00001000)            /*!<Capture/Compare 4 DMA request enable */\n#define  TIM_DIER_COMDE                      ((uint32_t)0x00002000)            /*!<COM DMA request enable */\n#define  TIM_DIER_TDE                        ((uint32_t)0x00004000)            /*!<Trigger DMA request enable */\n\n/********************  Bit definition for TIM_SR register  ********************/\n#define  TIM_SR_UIF                          ((uint32_t)0x00000001)            /*!<Update interrupt Flag */\n#define  TIM_SR_CC1IF                        ((uint32_t)0x00000002)            /*!<Capture/Compare 1 interrupt Flag */\n#define  TIM_SR_CC2IF                        ((uint32_t)0x00000004)            /*!<Capture/Compare 2 interrupt Flag */\n#define  TIM_SR_CC3IF                        ((uint32_t)0x00000008)            /*!<Capture/Compare 3 interrupt Flag */\n#define  TIM_SR_CC4IF                        ((uint32_t)0x00000010)            /*!<Capture/Compare 4 interrupt Flag */\n#define  TIM_SR_COMIF                        ((uint32_t)0x00000020)            /*!<COM interrupt Flag */\n#define  TIM_SR_TIF                          ((uint32_t)0x00000040)            /*!<Trigger interrupt Flag */\n#define  TIM_SR_BIF                          ((uint32_t)0x00000080)            /*!<Break interrupt Flag */\n#define  TIM_SR_CC1OF                        ((uint32_t)0x00000200)            /*!<Capture/Compare 1 Overcapture Flag */\n#define  TIM_SR_CC2OF                        ((uint32_t)0x00000400)            /*!<Capture/Compare 2 Overcapture Flag */\n#define  TIM_SR_CC3OF                        ((uint32_t)0x00000800)            /*!<Capture/Compare 3 Overcapture Flag */\n#define  TIM_SR_CC4OF                        ((uint32_t)0x00001000)            /*!<Capture/Compare 4 Overcapture Flag */\n\n/*******************  Bit definition for TIM_EGR register  ********************/\n#define  TIM_EGR_UG                          ((uint8_t)0x01)               /*!<Update Generation */\n#define  TIM_EGR_CC1G                        ((uint8_t)0x02)               /*!<Capture/Compare 1 Generation */\n#define  TIM_EGR_CC2G                        ((uint8_t)0x04)               /*!<Capture/Compare 2 Generation */\n#define  TIM_EGR_CC3G                        ((uint8_t)0x08)               /*!<Capture/Compare 3 Generation */\n#define  TIM_EGR_CC4G                        ((uint8_t)0x10)               /*!<Capture/Compare 4 Generation */\n#define  TIM_EGR_COMG                        ((uint8_t)0x20)               /*!<Capture/Compare Control Update Generation */\n#define  TIM_EGR_TG                          ((uint8_t)0x40)               /*!<Trigger Generation */\n#define  TIM_EGR_BG                          ((uint8_t)0x80)               /*!<Break Generation */\n\n/******************  Bit definition for TIM_CCMR1 register  *******************/\n#define  TIM_CCMR1_CC1S                      ((uint32_t)0x00000003)            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */\n#define  TIM_CCMR1_CC1S_0                    ((uint32_t)0x00000001)            /*!<Bit 0 */\n#define  TIM_CCMR1_CC1S_1                    ((uint32_t)0x00000002)            /*!<Bit 1 */\n\n#define  TIM_CCMR1_OC1FE                     ((uint32_t)0x00000004)            /*!<Output Compare 1 Fast enable */\n#define  TIM_CCMR1_OC1PE                     ((uint32_t)0x00000008)            /*!<Output Compare 1 Preload enable */\n\n#define  TIM_CCMR1_OC1M                      ((uint32_t)0x00000070)            /*!<OC1M[2:0] bits (Output Compare 1 Mode) */\n#define  TIM_CCMR1_OC1M_0                    ((uint32_t)0x00000010)            /*!<Bit 0 */\n#define  TIM_CCMR1_OC1M_1                    ((uint32_t)0x00000020)            /*!<Bit 1 */\n#define  TIM_CCMR1_OC1M_2                    ((uint32_t)0x00000040)            /*!<Bit 2 */\n\n#define  TIM_CCMR1_OC1CE                     ((uint32_t)0x00000080)            /*!<Output Compare 1Clear Enable */\n\n#define  TIM_CCMR1_CC2S                      ((uint32_t)0x00000300)            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */\n#define  TIM_CCMR1_CC2S_0                    ((uint32_t)0x00000100)            /*!<Bit 0 */\n#define  TIM_CCMR1_CC2S_1                    ((uint32_t)0x00000200)            /*!<Bit 1 */\n\n#define  TIM_CCMR1_OC2FE                     ((uint32_t)0x00000400)            /*!<Output Compare 2 Fast enable */\n#define  TIM_CCMR1_OC2PE                     ((uint32_t)0x00000800)            /*!<Output Compare 2 Preload enable */\n\n#define  TIM_CCMR1_OC2M                      ((uint32_t)0x00007000)            /*!<OC2M[2:0] bits (Output Compare 2 Mode) */\n#define  TIM_CCMR1_OC2M_0                    ((uint32_t)0x00001000)            /*!<Bit 0 */\n#define  TIM_CCMR1_OC2M_1                    ((uint32_t)0x00002000)            /*!<Bit 1 */\n#define  TIM_CCMR1_OC2M_2                    ((uint32_t)0x00004000)            /*!<Bit 2 */\n\n#define  TIM_CCMR1_OC2CE                     ((uint32_t)0x00008000)            /*!<Output Compare 2 Clear Enable */\n\n/*----------------------------------------------------------------------------*/\n\n#define  TIM_CCMR1_IC1PSC                    ((uint32_t)0x0000000C)            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */\n#define  TIM_CCMR1_IC1PSC_0                  ((uint32_t)0x00000004)            /*!<Bit 0 */\n#define  TIM_CCMR1_IC1PSC_1                  ((uint32_t)0x00000008)            /*!<Bit 1 */\n\n#define  TIM_CCMR1_IC1F                      ((uint32_t)0x000000F0)            /*!<IC1F[3:0] bits (Input Capture 1 Filter) */\n#define  TIM_CCMR1_IC1F_0                    ((uint32_t)0x00000010)            /*!<Bit 0 */\n#define  TIM_CCMR1_IC1F_1                    ((uint32_t)0x00000020)            /*!<Bit 1 */\n#define  TIM_CCMR1_IC1F_2                    ((uint32_t)0x00000040)            /*!<Bit 2 */\n#define  TIM_CCMR1_IC1F_3                    ((uint32_t)0x00000080)            /*!<Bit 3 */\n\n#define  TIM_CCMR1_IC2PSC                    ((uint32_t)0x00000C00)            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */\n#define  TIM_CCMR1_IC2PSC_0                  ((uint32_t)0x00000400)            /*!<Bit 0 */\n#define  TIM_CCMR1_IC2PSC_1                  ((uint32_t)0x00000800)            /*!<Bit 1 */\n\n#define  TIM_CCMR1_IC2F                      ((uint32_t)0x0000F000)            /*!<IC2F[3:0] bits (Input Capture 2 Filter) */\n#define  TIM_CCMR1_IC2F_0                    ((uint32_t)0x00001000)            /*!<Bit 0 */\n#define  TIM_CCMR1_IC2F_1                    ((uint32_t)0x00002000)            /*!<Bit 1 */\n#define  TIM_CCMR1_IC2F_2                    ((uint32_t)0x00004000)            /*!<Bit 2 */\n#define  TIM_CCMR1_IC2F_3                    ((uint32_t)0x00008000)            /*!<Bit 3 */\n\n/******************  Bit definition for TIM_CCMR2 register  *******************/\n#define  TIM_CCMR2_CC3S                      ((uint32_t)0x00000003)            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */\n#define  TIM_CCMR2_CC3S_0                    ((uint32_t)0x00000001)            /*!<Bit 0 */\n#define  TIM_CCMR2_CC3S_1                    ((uint32_t)0x00000002)            /*!<Bit 1 */\n\n#define  TIM_CCMR2_OC3FE                     ((uint32_t)0x00000004)            /*!<Output Compare 3 Fast enable */\n#define  TIM_CCMR2_OC3PE                     ((uint32_t)0x00000008)            /*!<Output Compare 3 Preload enable */\n\n#define  TIM_CCMR2_OC3M                      ((uint32_t)0x00000070)            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */\n#define  TIM_CCMR2_OC3M_0                    ((uint32_t)0x00000010)            /*!<Bit 0 */\n#define  TIM_CCMR2_OC3M_1                    ((uint32_t)0x00000020)            /*!<Bit 1 */\n#define  TIM_CCMR2_OC3M_2                    ((uint32_t)0x00000040)            /*!<Bit 2 */\n\n#define  TIM_CCMR2_OC3CE                     ((uint32_t)0x00000080)            /*!<Output Compare 3 Clear Enable */\n\n#define  TIM_CCMR2_CC4S                      ((uint32_t)0x00000300)            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */\n#define  TIM_CCMR2_CC4S_0                    ((uint32_t)0x00000100)            /*!<Bit 0 */\n#define  TIM_CCMR2_CC4S_1                    ((uint32_t)0x00000200)            /*!<Bit 1 */\n\n#define  TIM_CCMR2_OC4FE                     ((uint32_t)0x00000400)            /*!<Output Compare 4 Fast enable */\n#define  TIM_CCMR2_OC4PE                     ((uint32_t)0x00000800)            /*!<Output Compare 4 Preload enable */\n\n#define  TIM_CCMR2_OC4M                      ((uint32_t)0x00007000)            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */\n#define  TIM_CCMR2_OC4M_0                    ((uint32_t)0x00001000)            /*!<Bit 0 */\n#define  TIM_CCMR2_OC4M_1                    ((uint32_t)0x00002000)            /*!<Bit 1 */\n#define  TIM_CCMR2_OC4M_2                    ((uint32_t)0x00004000)            /*!<Bit 2 */\n\n#define  TIM_CCMR2_OC4CE                     ((uint32_t)0x00008000)            /*!<Output Compare 4 Clear Enable */\n\n/*----------------------------------------------------------------------------*/\n\n#define  TIM_CCMR2_IC3PSC                    ((uint32_t)0x0000000C)            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */\n#define  TIM_CCMR2_IC3PSC_0                  ((uint32_t)0x00000004)            /*!<Bit 0 */\n#define  TIM_CCMR2_IC3PSC_1                  ((uint32_t)0x00000008)            /*!<Bit 1 */\n\n#define  TIM_CCMR2_IC3F                      ((uint32_t)0x000000F0)            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */\n#define  TIM_CCMR2_IC3F_0                    ((uint32_t)0x00000010)            /*!<Bit 0 */\n#define  TIM_CCMR2_IC3F_1                    ((uint32_t)0x00000020)            /*!<Bit 1 */\n#define  TIM_CCMR2_IC3F_2                    ((uint32_t)0x00000040)            /*!<Bit 2 */\n#define  TIM_CCMR2_IC3F_3                    ((uint32_t)0x00000080)            /*!<Bit 3 */\n\n#define  TIM_CCMR2_IC4PSC                    ((uint32_t)0x00000C00)            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */\n#define  TIM_CCMR2_IC4PSC_0                  ((uint32_t)0x00000400)            /*!<Bit 0 */\n#define  TIM_CCMR2_IC4PSC_1                  ((uint32_t)0x00000800)            /*!<Bit 1 */\n\n#define  TIM_CCMR2_IC4F                      ((uint32_t)0x0000F000)            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */\n#define  TIM_CCMR2_IC4F_0                    ((uint32_t)0x00001000)            /*!<Bit 0 */\n#define  TIM_CCMR2_IC4F_1                    ((uint32_t)0x00002000)            /*!<Bit 1 */\n#define  TIM_CCMR2_IC4F_2                    ((uint32_t)0x00004000)            /*!<Bit 2 */\n#define  TIM_CCMR2_IC4F_3                    ((uint32_t)0x00008000)            /*!<Bit 3 */\n\n/*******************  Bit definition for TIM_CCER register  *******************/\n#define  TIM_CCER_CC1E                       ((uint32_t)0x00000001)            /*!<Capture/Compare 1 output enable */\n#define  TIM_CCER_CC1P                       ((uint32_t)0x00000002)            /*!<Capture/Compare 1 output Polarity */\n#define  TIM_CCER_CC1NE                      ((uint32_t)0x00000004)            /*!<Capture/Compare 1 Complementary output enable */\n#define  TIM_CCER_CC1NP                      ((uint32_t)0x00000008)            /*!<Capture/Compare 1 Complementary output Polarity */\n#define  TIM_CCER_CC2E                       ((uint32_t)0x00000010)            /*!<Capture/Compare 2 output enable */\n#define  TIM_CCER_CC2P                       ((uint32_t)0x00000020)            /*!<Capture/Compare 2 output Polarity */\n#define  TIM_CCER_CC2NE                      ((uint32_t)0x00000040)            /*!<Capture/Compare 2 Complementary output enable */\n#define  TIM_CCER_CC2NP                      ((uint32_t)0x00000080)            /*!<Capture/Compare 2 Complementary output Polarity */\n#define  TIM_CCER_CC3E                       ((uint32_t)0x00000100)            /*!<Capture/Compare 3 output enable */\n#define  TIM_CCER_CC3P                       ((uint32_t)0x00000200)            /*!<Capture/Compare 3 output Polarity */\n#define  TIM_CCER_CC3NE                      ((uint32_t)0x00000400)            /*!<Capture/Compare 3 Complementary output enable */\n#define  TIM_CCER_CC3NP                      ((uint32_t)0x00000800)            /*!<Capture/Compare 3 Complementary output Polarity */\n#define  TIM_CCER_CC4E                       ((uint32_t)0x00001000)            /*!<Capture/Compare 4 output enable */\n#define  TIM_CCER_CC4P                       ((uint32_t)0x00002000)            /*!<Capture/Compare 4 output Polarity */\n#define  TIM_CCER_CC4NP                      ((uint32_t)0x00008000)            /*!<Capture/Compare 4 Complementary output Polarity */\n\n/*******************  Bit definition for TIM_CNT register  ********************/\n#define  TIM_CNT_CNT                         ((uint32_t)0x0000FFFF)            /*!<Counter Value */\n\n/*******************  Bit definition for TIM_PSC register  ********************/\n#define  TIM_PSC_PSC                         ((uint32_t)0x0000FFFF)            /*!<Prescaler Value */\n\n/*******************  Bit definition for TIM_ARR register  ********************/\n#define  TIM_ARR_ARR                         ((uint32_t)0x0000FFFF)            /*!<actual auto-reload Value */\n\n/*******************  Bit definition for TIM_RCR register  ********************/\n#define  TIM_RCR_REP                         ((uint8_t)0xFF)               /*!<Repetition Counter Value */\n\n/*******************  Bit definition for TIM_CCR1 register  *******************/\n#define  TIM_CCR1_CCR1                       ((uint32_t)0x0000FFFF)            /*!<Capture/Compare 1 Value */\n\n/*******************  Bit definition for TIM_CCR2 register  *******************/\n#define  TIM_CCR2_CCR2                       ((uint32_t)0x0000FFFF)            /*!<Capture/Compare 2 Value */\n\n/*******************  Bit definition for TIM_CCR3 register  *******************/\n#define  TIM_CCR3_CCR3                       ((uint32_t)0x0000FFFF)            /*!<Capture/Compare 3 Value */\n\n/*******************  Bit definition for TIM_CCR4 register  *******************/\n#define  TIM_CCR4_CCR4                       ((uint32_t)0x0000FFFF)            /*!<Capture/Compare 4 Value */\n\n/*******************  Bit definition for TIM_BDTR register  *******************/\n#define  TIM_BDTR_DTG                        ((uint32_t)0x000000FF)            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */\n#define  TIM_BDTR_DTG_0                      ((uint32_t)0x00000001)            /*!<Bit 0 */\n#define  TIM_BDTR_DTG_1                      ((uint32_t)0x00000002)            /*!<Bit 1 */\n#define  TIM_BDTR_DTG_2                      ((uint32_t)0x00000004)            /*!<Bit 2 */\n#define  TIM_BDTR_DTG_3                      ((uint32_t)0x00000008)            /*!<Bit 3 */\n#define  TIM_BDTR_DTG_4                      ((uint32_t)0x00000010)            /*!<Bit 4 */\n#define  TIM_BDTR_DTG_5                      ((uint32_t)0x00000020)            /*!<Bit 5 */\n#define  TIM_BDTR_DTG_6                      ((uint32_t)0x00000040)            /*!<Bit 6 */\n#define  TIM_BDTR_DTG_7                      ((uint32_t)0x00000080)            /*!<Bit 7 */\n\n#define  TIM_BDTR_LOCK                       ((uint32_t)0x00000300)            /*!<LOCK[1:0] bits (Lock Configuration) */\n#define  TIM_BDTR_LOCK_0                     ((uint32_t)0x00000100)            /*!<Bit 0 */\n#define  TIM_BDTR_LOCK_1                     ((uint32_t)0x00000200)            /*!<Bit 1 */\n\n#define  TIM_BDTR_OSSI                       ((uint32_t)0x00000400)            /*!<Off-State Selection for Idle mode */\n#define  TIM_BDTR_OSSR                       ((uint32_t)0x00000800)            /*!<Off-State Selection for Run mode */\n#define  TIM_BDTR_BKE                        ((uint32_t)0x00001000)            /*!<Break enable */\n#define  TIM_BDTR_BKP                        ((uint32_t)0x00002000)            /*!<Break Polarity */\n#define  TIM_BDTR_AOE                        ((uint32_t)0x00004000)            /*!<Automatic Output enable */\n#define  TIM_BDTR_MOE                        ((uint32_t)0x00008000)            /*!<Main Output enable */\n\n/*******************  Bit definition for TIM_DCR register  ********************/\n#define  TIM_DCR_DBA                         ((uint32_t)0x0000001F)            /*!<DBA[4:0] bits (DMA Base Address) */\n#define  TIM_DCR_DBA_0                       ((uint32_t)0x00000001)            /*!<Bit 0 */\n#define  TIM_DCR_DBA_1                       ((uint32_t)0x00000002)            /*!<Bit 1 */\n#define  TIM_DCR_DBA_2                       ((uint32_t)0x00000004)            /*!<Bit 2 */\n#define  TIM_DCR_DBA_3                       ((uint32_t)0x00000008)            /*!<Bit 3 */\n#define  TIM_DCR_DBA_4                       ((uint32_t)0x00000010)            /*!<Bit 4 */\n\n#define  TIM_DCR_DBL                         ((uint32_t)0x00001F00)            /*!<DBL[4:0] bits (DMA Burst Length) */\n#define  TIM_DCR_DBL_0                       ((uint32_t)0x00000100)            /*!<Bit 0 */\n#define  TIM_DCR_DBL_1                       ((uint32_t)0x00000200)            /*!<Bit 1 */\n#define  TIM_DCR_DBL_2                       ((uint32_t)0x00000400)            /*!<Bit 2 */\n#define  TIM_DCR_DBL_3                       ((uint32_t)0x00000800)            /*!<Bit 3 */\n#define  TIM_DCR_DBL_4                       ((uint32_t)0x00001000)            /*!<Bit 4 */\n\n/*******************  Bit definition for TIM_DMAR register  *******************/\n#define  TIM_DMAR_DMAB                       ((uint32_t)0x0000FFFF)            /*!<DMA register for burst accesses */\n\n/*******************  Bit definition for TIM_OR register  *********************/\n/*******************  Bit definition for TIM_OR register  *********************/\n#define TIM2_OR_ETR_RMP                       ((uint32_t)0x00000007)            /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */\n#define TIM2_OR_ETR_RMP_0                     ((uint32_t)0x00000001)            /*!<Bit 0 */\n#define TIM2_OR_ETR_RMP_1                     ((uint32_t)0x00000002)            /*!<Bit 1 */\n#define TIM2_OR_ETR_RMP_2                     ((uint32_t)0x00000004)            /*!<Bit 2 */\n#define TIM2_OR_TI4_RMP                       ((uint32_t)0x0000018)            /*!<TI4_RMP[1:0] bits (TIM2 Input 4 remap) */\n#define TIM2_OR_TI4_RMP_0                     ((uint32_t)0x00000008)            /*!<Bit 0 */\n#define TIM2_OR_TI4_RMP_1                     ((uint32_t)0x00000010)            /*!<Bit 1 */\n\n#define TIM21_OR_ETR_RMP                      ((uint32_t)0x00000003)            /*!<ETR_RMP[1:0] bits (TIM21 ETR remap) */\n#define TIM21_OR_ETR_RMP_0                    ((uint32_t)0x00000001)            /*!<Bit 0 */\n#define TIM21_OR_ETR_RMP_1                    ((uint32_t)0x00000002)            /*!<Bit 1 */\n#define TIM21_OR_TI1_RMP                      ((uint32_t)0x0000001C)            /*!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) */\n#define TIM21_OR_TI1_RMP_0                    ((uint32_t)0x00000004)            /*!<Bit 0 */\n#define TIM21_OR_TI1_RMP_1                    ((uint32_t)0x00000008)            /*!<Bit 1 */\n#define TIM21_OR_TI1_RMP_2                    ((uint32_t)0x00000010)            /*!<Bit 2 */\n#define TIM21_OR_TI2_RMP                      ((uint32_t)0x00000020)            /*!<TI2_RMP bit (TIM21 Input 2 remap) */\n\n#define TIM22_OR_ETR_RMP                      ((uint32_t)0x00000003)            /*!<ETR_RMP[1:0] bits (TIM22 ETR remap) */\n#define TIM22_OR_ETR_RMP_0                    ((uint32_t)0x00000001)            /*!<Bit 0 */\n#define TIM22_OR_ETR_RMP_1                    ((uint32_t)0x00000002)            /*!<Bit 1 */\n#define TIM22_OR_TI1_RMP                      ((uint32_t)0x0000000C)            /*!<TI1_RMP[2:0] bits (TIM22 Input 1 remap) */\n#define TIM22_OR_TI1_RMP_0                    ((uint32_t)0x00000004)            /*!<Bit 0 */\n#define TIM22_OR_TI1_RMP_1                    ((uint32_t)0x00000008)            /*!<Bit 1 */\n\n/******************************************************************************/\n/*                                                                            */\n/*                          Touch Sensing Controller (TSC)                    */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for TSC_CR register  *********************/\n#define  TSC_CR_TSCE                         ((uint32_t)0x00000001)            /*!<Touch sensing controller enable */\n#define  TSC_CR_START                        ((uint32_t)0x00000002)            /*!<Start acquisition */\n#define  TSC_CR_AM                           ((uint32_t)0x00000004)            /*!<Acquisition mode */\n#define  TSC_CR_SYNCPOL                      ((uint32_t)0x00000008)            /*!<Synchronization pin polarity */\n#define  TSC_CR_IODEF                        ((uint32_t)0x00000010)            /*!<IO default mode */\n\n#define  TSC_CR_MCV                          ((uint32_t)0x000000E0)            /*!<MCV[2:0] bits (Max Count Value) */\n#define  TSC_CR_MCV_0                        ((uint32_t)0x00000020)            /*!<Bit 0 */\n#define  TSC_CR_MCV_1                        ((uint32_t)0x00000040)            /*!<Bit 1 */\n#define  TSC_CR_MCV_2                        ((uint32_t)0x00000080)            /*!<Bit 2 */\n\n#define  TSC_CR_PGPSC                        ((uint32_t)0x00007000)            /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */\n#define  TSC_CR_PGPSC_0                      ((uint32_t)0x00001000)            /*!<Bit 0 */\n#define  TSC_CR_PGPSC_1                      ((uint32_t)0x00002000)            /*!<Bit 1 */\n#define  TSC_CR_PGPSC_2                      ((uint32_t)0x00004000)            /*!<Bit 2 */\n\n#define  TSC_CR_SSPSC                        ((uint32_t)0x00008000)            /*!<Spread Spectrum Prescaler */\n#define  TSC_CR_SSE                          ((uint32_t)0x00010000)            /*!<Spread Spectrum Enable */\n\n#define  TSC_CR_SSD                          ((uint32_t)0x00FE0000)            /*!<SSD[6:0] bits (Spread Spectrum Deviation) */\n#define  TSC_CR_SSD_0                        ((uint32_t)0x00020000)            /*!<Bit 0 */\n#define  TSC_CR_SSD_1                        ((uint32_t)0x00040000)            /*!<Bit 1 */\n#define  TSC_CR_SSD_2                        ((uint32_t)0x00080000)            /*!<Bit 2 */\n#define  TSC_CR_SSD_3                        ((uint32_t)0x00100000)            /*!<Bit 3 */\n#define  TSC_CR_SSD_4                        ((uint32_t)0x00200000)            /*!<Bit 4 */\n#define  TSC_CR_SSD_5                        ((uint32_t)0x00400000)            /*!<Bit 5 */\n#define  TSC_CR_SSD_6                        ((uint32_t)0x00800000)            /*!<Bit 6 */\n\n#define  TSC_CR_CTPL                         ((uint32_t)0x0F000000)            /*!<CTPL[3:0] bits (Charge Transfer pulse low) */\n#define  TSC_CR_CTPL_0                       ((uint32_t)0x01000000)            /*!<Bit 0 */\n#define  TSC_CR_CTPL_1                       ((uint32_t)0x02000000)            /*!<Bit 1 */\n#define  TSC_CR_CTPL_2                       ((uint32_t)0x04000000)            /*!<Bit 2 */\n#define  TSC_CR_CTPL_3                       ((uint32_t)0x08000000)            /*!<Bit 3 */\n\n#define  TSC_CR_CTPH                         ((uint32_t)0xF0000000)            /*!<CTPH[3:0] bits (Charge Transfer pulse high) */\n#define  TSC_CR_CTPH_0                       ((uint32_t)0x10000000)            /*!<Bit 0 */\n#define  TSC_CR_CTPH_1                       ((uint32_t)0x20000000)            /*!<Bit 1 */\n#define  TSC_CR_CTPH_2                       ((uint32_t)0x40000000)            /*!<Bit 2 */\n#define  TSC_CR_CTPH_3                       ((uint32_t)0x80000000)            /*!<Bit 3 */\n\n/*******************  Bit definition for TSC_IER register  ********************/\n#define  TSC_IER_EOAIE                       ((uint32_t)0x00000001)            /*!<End of acquisition interrupt enable */\n#define  TSC_IER_MCEIE                       ((uint32_t)0x00000002)            /*!<Max count error interrupt enable */\n\n/*******************  Bit definition for TSC_ICR register  ********************/\n#define  TSC_ICR_EOAIC                       ((uint32_t)0x00000001)            /*!<End of acquisition interrupt clear */\n#define  TSC_ICR_MCEIC                       ((uint32_t)0x00000002)            /*!<Max count error interrupt clear */\n\n/*******************  Bit definition for TSC_ISR register  ********************/\n#define  TSC_ISR_EOAF                        ((uint32_t)0x00000001)            /*!<End of acquisition flag */\n#define  TSC_ISR_MCEF                        ((uint32_t)0x00000002)            /*!<Max count error flag */\n\n/*******************  Bit definition for TSC_IOHCR register  ******************/\n#define  TSC_IOHCR_G1_IO1                    ((uint32_t)0x00000001)            /*!<GROUP1_IO1 schmitt trigger hysteresis mode */\n#define  TSC_IOHCR_G1_IO2                    ((uint32_t)0x00000002)            /*!<GROUP1_IO2 schmitt trigger hysteresis mode */\n#define  TSC_IOHCR_G1_IO3                    ((uint32_t)0x00000004)            /*!<GROUP1_IO3 schmitt trigger hysteresis mode */\n#define  TSC_IOHCR_G1_IO4                    ((uint32_t)0x00000008)            /*!<GROUP1_IO4 schmitt trigger hysteresis mode */\n#define  TSC_IOHCR_G2_IO1                    ((uint32_t)0x00000010)            /*!<GROUP2_IO1 schmitt trigger hysteresis mode */\n#define  TSC_IOHCR_G2_IO2                    ((uint32_t)0x00000020)            /*!<GROUP2_IO2 schmitt trigger hysteresis mode */\n#define  TSC_IOHCR_G2_IO3                    ((uint32_t)0x00000040)            /*!<GROUP2_IO3 schmitt trigger hysteresis mode */\n#define  TSC_IOHCR_G2_IO4                    ((uint32_t)0x00000080)            /*!<GROUP2_IO4 schmitt trigger hysteresis mode */\n#define  TSC_IOHCR_G3_IO1                    ((uint32_t)0x00000100)            /*!<GROUP3_IO1 schmitt trigger hysteresis mode */\n#define  TSC_IOHCR_G3_IO2                    ((uint32_t)0x00000200)            /*!<GROUP3_IO2 schmitt trigger hysteresis mode */\n#define  TSC_IOHCR_G3_IO3                    ((uint32_t)0x00000400)            /*!<GROUP3_IO3 schmitt trigger hysteresis mode */\n#define  TSC_IOHCR_G3_IO4                    ((uint32_t)0x00000800)            /*!<GROUP3_IO4 schmitt trigger hysteresis mode */\n#define  TSC_IOHCR_G4_IO1                    ((uint32_t)0x00001000)            /*!<GROUP4_IO1 schmitt trigger hysteresis mode */\n#define  TSC_IOHCR_G4_IO2                    ((uint32_t)0x00002000)            /*!<GROUP4_IO2 schmitt trigger hysteresis mode */\n#define  TSC_IOHCR_G4_IO3                    ((uint32_t)0x00004000)            /*!<GROUP4_IO3 schmitt trigger hysteresis mode */\n#define  TSC_IOHCR_G4_IO4                    ((uint32_t)0x00008000)            /*!<GROUP4_IO4 schmitt trigger hysteresis mode */\n#define  TSC_IOHCR_G5_IO1                    ((uint32_t)0x00010000)            /*!<GROUP5_IO1 schmitt trigger hysteresis mode */\n#define  TSC_IOHCR_G5_IO2                    ((uint32_t)0x00020000)            /*!<GROUP5_IO2 schmitt trigger hysteresis mode */\n#define  TSC_IOHCR_G5_IO3                    ((uint32_t)0x00040000)            /*!<GROUP5_IO3 schmitt trigger hysteresis mode */\n#define  TSC_IOHCR_G5_IO4                    ((uint32_t)0x00080000)            /*!<GROUP5_IO4 schmitt trigger hysteresis mode */\n#define  TSC_IOHCR_G6_IO1                    ((uint32_t)0x00100000)            /*!<GROUP6_IO1 schmitt trigger hysteresis mode */\n#define  TSC_IOHCR_G6_IO2                    ((uint32_t)0x00200000)            /*!<GROUP6_IO2 schmitt trigger hysteresis mode */\n#define  TSC_IOHCR_G6_IO3                    ((uint32_t)0x00400000)            /*!<GROUP6_IO3 schmitt trigger hysteresis mode */\n#define  TSC_IOHCR_G6_IO4                    ((uint32_t)0x00800000)            /*!<GROUP6_IO4 schmitt trigger hysteresis mode */\n#define  TSC_IOHCR_G7_IO1                    ((uint32_t)0x01000000)            /*!<GROUP7_IO1 schmitt trigger hysteresis mode */\n#define  TSC_IOHCR_G7_IO2                    ((uint32_t)0x02000000)            /*!<GROUP7_IO2 schmitt trigger hysteresis mode */\n#define  TSC_IOHCR_G7_IO3                    ((uint32_t)0x04000000)            /*!<GROUP7_IO3 schmitt trigger hysteresis mode */\n#define  TSC_IOHCR_G7_IO4                    ((uint32_t)0x08000000)            /*!<GROUP7_IO4 schmitt trigger hysteresis mode */\n#define  TSC_IOHCR_G8_IO1                    ((uint32_t)0x10000000)            /*!<GROUP8_IO1 schmitt trigger hysteresis mode */\n#define  TSC_IOHCR_G8_IO2                    ((uint32_t)0x20000000)            /*!<GROUP8_IO2 schmitt trigger hysteresis mode */\n#define  TSC_IOHCR_G8_IO3                    ((uint32_t)0x40000000)            /*!<GROUP8_IO3 schmitt trigger hysteresis mode */\n#define  TSC_IOHCR_G8_IO4                    ((uint32_t)0x80000000)            /*!<GROUP8_IO4 schmitt trigger hysteresis mode */\n\n/*******************  Bit definition for TSC_IOASCR register  *****************/\n#define  TSC_IOASCR_G1_IO1                   ((uint32_t)0x00000001)            /*!<GROUP1_IO1 analog switch enable */\n#define  TSC_IOASCR_G1_IO2                   ((uint32_t)0x00000002)            /*!<GROUP1_IO2 analog switch enable */\n#define  TSC_IOASCR_G1_IO3                   ((uint32_t)0x00000004)            /*!<GROUP1_IO3 analog switch enable */\n#define  TSC_IOASCR_G1_IO4                   ((uint32_t)0x00000008)            /*!<GROUP1_IO4 analog switch enable */\n#define  TSC_IOASCR_G2_IO1                   ((uint32_t)0x00000010)            /*!<GROUP2_IO1 analog switch enable */\n#define  TSC_IOASCR_G2_IO2                   ((uint32_t)0x00000020)            /*!<GROUP2_IO2 analog switch enable */\n#define  TSC_IOASCR_G2_IO3                   ((uint32_t)0x00000040)            /*!<GROUP2_IO3 analog switch enable */\n#define  TSC_IOASCR_G2_IO4                   ((uint32_t)0x00000080)            /*!<GROUP2_IO4 analog switch enable */\n#define  TSC_IOASCR_G3_IO1                   ((uint32_t)0x00000100)            /*!<GROUP3_IO1 analog switch enable */\n#define  TSC_IOASCR_G3_IO2                   ((uint32_t)0x00000200)            /*!<GROUP3_IO2 analog switch enable */\n#define  TSC_IOASCR_G3_IO3                   ((uint32_t)0x00000400)            /*!<GROUP3_IO3 analog switch enable */\n#define  TSC_IOASCR_G3_IO4                   ((uint32_t)0x00000800)            /*!<GROUP3_IO4 analog switch enable */\n#define  TSC_IOASCR_G4_IO1                   ((uint32_t)0x00001000)            /*!<GROUP4_IO1 analog switch enable */\n#define  TSC_IOASCR_G4_IO2                   ((uint32_t)0x00002000)            /*!<GROUP4_IO2 analog switch enable */\n#define  TSC_IOASCR_G4_IO3                   ((uint32_t)0x00004000)            /*!<GROUP4_IO3 analog switch enable */\n#define  TSC_IOASCR_G4_IO4                   ((uint32_t)0x00008000)            /*!<GROUP4_IO4 analog switch enable */\n#define  TSC_IOASCR_G5_IO1                   ((uint32_t)0x00010000)            /*!<GROUP5_IO1 analog switch enable */\n#define  TSC_IOASCR_G5_IO2                   ((uint32_t)0x00020000)            /*!<GROUP5_IO2 analog switch enable */\n#define  TSC_IOASCR_G5_IO3                   ((uint32_t)0x00040000)            /*!<GROUP5_IO3 analog switch enable */\n#define  TSC_IOASCR_G5_IO4                   ((uint32_t)0x00080000)            /*!<GROUP5_IO4 analog switch enable */\n#define  TSC_IOASCR_G6_IO1                   ((uint32_t)0x00100000)            /*!<GROUP6_IO1 analog switch enable */\n#define  TSC_IOASCR_G6_IO2                   ((uint32_t)0x00200000)            /*!<GROUP6_IO2 analog switch enable */\n#define  TSC_IOASCR_G6_IO3                   ((uint32_t)0x00400000)            /*!<GROUP6_IO3 analog switch enable */\n#define  TSC_IOASCR_G6_IO4                   ((uint32_t)0x00800000)            /*!<GROUP6_IO4 analog switch enable */\n#define  TSC_IOASCR_G7_IO1                   ((uint32_t)0x01000000)            /*!<GROUP7_IO1 analog switch enable */\n#define  TSC_IOASCR_G7_IO2                   ((uint32_t)0x02000000)            /*!<GROUP7_IO2 analog switch enable */\n#define  TSC_IOASCR_G7_IO3                   ((uint32_t)0x04000000)            /*!<GROUP7_IO3 analog switch enable */\n#define  TSC_IOASCR_G7_IO4                   ((uint32_t)0x08000000)            /*!<GROUP7_IO4 analog switch enable */\n#define  TSC_IOASCR_G8_IO1                   ((uint32_t)0x10000000)            /*!<GROUP8_IO1 analog switch enable */\n#define  TSC_IOASCR_G8_IO2                   ((uint32_t)0x20000000)            /*!<GROUP8_IO2 analog switch enable */\n#define  TSC_IOASCR_G8_IO3                   ((uint32_t)0x40000000)            /*!<GROUP8_IO3 analog switch enable */\n#define  TSC_IOASCR_G8_IO4                   ((uint32_t)0x80000000)            /*!<GROUP8_IO4 analog switch enable */\n\n/*******************  Bit definition for TSC_IOSCR register  ******************/\n#define  TSC_IOSCR_G1_IO1                    ((uint32_t)0x00000001)            /*!<GROUP1_IO1 sampling mode */\n#define  TSC_IOSCR_G1_IO2                    ((uint32_t)0x00000002)            /*!<GROUP1_IO2 sampling mode */\n#define  TSC_IOSCR_G1_IO3                    ((uint32_t)0x00000004)            /*!<GROUP1_IO3 sampling mode */\n#define  TSC_IOSCR_G1_IO4                    ((uint32_t)0x00000008)            /*!<GROUP1_IO4 sampling mode */\n#define  TSC_IOSCR_G2_IO1                    ((uint32_t)0x00000010)            /*!<GROUP2_IO1 sampling mode */\n#define  TSC_IOSCR_G2_IO2                    ((uint32_t)0x00000020)            /*!<GROUP2_IO2 sampling mode */\n#define  TSC_IOSCR_G2_IO3                    ((uint32_t)0x00000040)            /*!<GROUP2_IO3 sampling mode */\n#define  TSC_IOSCR_G2_IO4                    ((uint32_t)0x00000080)            /*!<GROUP2_IO4 sampling mode */\n#define  TSC_IOSCR_G3_IO1                    ((uint32_t)0x00000100)            /*!<GROUP3_IO1 sampling mode */\n#define  TSC_IOSCR_G3_IO2                    ((uint32_t)0x00000200)            /*!<GROUP3_IO2 sampling mode */\n#define  TSC_IOSCR_G3_IO3                    ((uint32_t)0x00000400)            /*!<GROUP3_IO3 sampling mode */\n#define  TSC_IOSCR_G3_IO4                    ((uint32_t)0x00000800)            /*!<GROUP3_IO4 sampling mode */\n#define  TSC_IOSCR_G4_IO1                    ((uint32_t)0x00001000)            /*!<GROUP4_IO1 sampling mode */\n#define  TSC_IOSCR_G4_IO2                    ((uint32_t)0x00002000)            /*!<GROUP4_IO2 sampling mode */\n#define  TSC_IOSCR_G4_IO3                    ((uint32_t)0x00004000)            /*!<GROUP4_IO3 sampling mode */\n#define  TSC_IOSCR_G4_IO4                    ((uint32_t)0x00008000)            /*!<GROUP4_IO4 sampling mode */\n#define  TSC_IOSCR_G5_IO1                    ((uint32_t)0x00010000)            /*!<GROUP5_IO1 sampling mode */\n#define  TSC_IOSCR_G5_IO2                    ((uint32_t)0x00020000)            /*!<GROUP5_IO2 sampling mode */\n#define  TSC_IOSCR_G5_IO3                    ((uint32_t)0x00040000)            /*!<GROUP5_IO3 sampling mode */\n#define  TSC_IOSCR_G5_IO4                    ((uint32_t)0x00080000)            /*!<GROUP5_IO4 sampling mode */\n#define  TSC_IOSCR_G6_IO1                    ((uint32_t)0x00100000)            /*!<GROUP6_IO1 sampling mode */\n#define  TSC_IOSCR_G6_IO2                    ((uint32_t)0x00200000)            /*!<GROUP6_IO2 sampling mode */\n#define  TSC_IOSCR_G6_IO3                    ((uint32_t)0x00400000)            /*!<GROUP6_IO3 sampling mode */\n#define  TSC_IOSCR_G6_IO4                    ((uint32_t)0x00800000)            /*!<GROUP6_IO4 sampling mode */\n#define  TSC_IOSCR_G7_IO1                    ((uint32_t)0x01000000)            /*!<GROUP7_IO1 sampling mode */\n#define  TSC_IOSCR_G7_IO2                    ((uint32_t)0x02000000)            /*!<GROUP7_IO2 sampling mode */\n#define  TSC_IOSCR_G7_IO3                    ((uint32_t)0x04000000)            /*!<GROUP7_IO3 sampling mode */\n#define  TSC_IOSCR_G7_IO4                    ((uint32_t)0x08000000)            /*!<GROUP7_IO4 sampling mode */\n#define  TSC_IOSCR_G8_IO1                    ((uint32_t)0x10000000)            /*!<GROUP8_IO1 sampling mode */\n#define  TSC_IOSCR_G8_IO2                    ((uint32_t)0x20000000)            /*!<GROUP8_IO2 sampling mode */\n#define  TSC_IOSCR_G8_IO3                    ((uint32_t)0x40000000)            /*!<GROUP8_IO3 sampling mode */\n#define  TSC_IOSCR_G8_IO4                    ((uint32_t)0x80000000)            /*!<GROUP8_IO4 sampling mode */\n\n/*******************  Bit definition for TSC_IOCCR register  ******************/\n#define  TSC_IOCCR_G1_IO1                    ((uint32_t)0x00000001)            /*!<GROUP1_IO1 channel mode */\n#define  TSC_IOCCR_G1_IO2                    ((uint32_t)0x00000002)            /*!<GROUP1_IO2 channel mode */\n#define  TSC_IOCCR_G1_IO3                    ((uint32_t)0x00000004)            /*!<GROUP1_IO3 channel mode */\n#define  TSC_IOCCR_G1_IO4                    ((uint32_t)0x00000008)            /*!<GROUP1_IO4 channel mode */\n#define  TSC_IOCCR_G2_IO1                    ((uint32_t)0x00000010)            /*!<GROUP2_IO1 channel mode */\n#define  TSC_IOCCR_G2_IO2                    ((uint32_t)0x00000020)            /*!<GROUP2_IO2 channel mode */\n#define  TSC_IOCCR_G2_IO3                    ((uint32_t)0x00000040)            /*!<GROUP2_IO3 channel mode */\n#define  TSC_IOCCR_G2_IO4                    ((uint32_t)0x00000080)            /*!<GROUP2_IO4 channel mode */\n#define  TSC_IOCCR_G3_IO1                    ((uint32_t)0x00000100)            /*!<GROUP3_IO1 channel mode */\n#define  TSC_IOCCR_G3_IO2                    ((uint32_t)0x00000200)            /*!<GROUP3_IO2 channel mode */\n#define  TSC_IOCCR_G3_IO3                    ((uint32_t)0x00000400)            /*!<GROUP3_IO3 channel mode */\n#define  TSC_IOCCR_G3_IO4                    ((uint32_t)0x00000800)            /*!<GROUP3_IO4 channel mode */\n#define  TSC_IOCCR_G4_IO1                    ((uint32_t)0x00001000)            /*!<GROUP4_IO1 channel mode */\n#define  TSC_IOCCR_G4_IO2                    ((uint32_t)0x00002000)            /*!<GROUP4_IO2 channel mode */\n#define  TSC_IOCCR_G4_IO3                    ((uint32_t)0x00004000)            /*!<GROUP4_IO3 channel mode */\n#define  TSC_IOCCR_G4_IO4                    ((uint32_t)0x00008000)            /*!<GROUP4_IO4 channel mode */\n#define  TSC_IOCCR_G5_IO1                    ((uint32_t)0x00010000)            /*!<GROUP5_IO1 channel mode */\n#define  TSC_IOCCR_G5_IO2                    ((uint32_t)0x00020000)            /*!<GROUP5_IO2 channel mode */\n#define  TSC_IOCCR_G5_IO3                    ((uint32_t)0x00040000)            /*!<GROUP5_IO3 channel mode */\n#define  TSC_IOCCR_G5_IO4                    ((uint32_t)0x00080000)            /*!<GROUP5_IO4 channel mode */\n#define  TSC_IOCCR_G6_IO1                    ((uint32_t)0x00100000)            /*!<GROUP6_IO1 channel mode */\n#define  TSC_IOCCR_G6_IO2                    ((uint32_t)0x00200000)            /*!<GROUP6_IO2 channel mode */\n#define  TSC_IOCCR_G6_IO3                    ((uint32_t)0x00400000)            /*!<GROUP6_IO3 channel mode */\n#define  TSC_IOCCR_G6_IO4                    ((uint32_t)0x00800000)            /*!<GROUP6_IO4 channel mode */\n#define  TSC_IOCCR_G7_IO1                    ((uint32_t)0x01000000)            /*!<GROUP7_IO1 channel mode */\n#define  TSC_IOCCR_G7_IO2                    ((uint32_t)0x02000000)            /*!<GROUP7_IO2 channel mode */\n#define  TSC_IOCCR_G7_IO3                    ((uint32_t)0x04000000)            /*!<GROUP7_IO3 channel mode */\n#define  TSC_IOCCR_G7_IO4                    ((uint32_t)0x08000000)            /*!<GROUP7_IO4 channel mode */\n#define  TSC_IOCCR_G8_IO1                    ((uint32_t)0x10000000)            /*!<GROUP8_IO1 channel mode */\n#define  TSC_IOCCR_G8_IO2                    ((uint32_t)0x20000000)            /*!<GROUP8_IO2 channel mode */\n#define  TSC_IOCCR_G8_IO3                    ((uint32_t)0x40000000)            /*!<GROUP8_IO3 channel mode */\n#define  TSC_IOCCR_G8_IO4                    ((uint32_t)0x80000000)            /*!<GROUP8_IO4 channel mode */\n\n/*******************  Bit definition for TSC_IOGCSR register  *****************/\n#define  TSC_IOGCSR_G1E                      ((uint32_t)0x00000001)            /*!<Analog IO GROUP1 enable */\n#define  TSC_IOGCSR_G2E                      ((uint32_t)0x00000002)            /*!<Analog IO GROUP2 enable */\n#define  TSC_IOGCSR_G3E                      ((uint32_t)0x00000004)            /*!<Analog IO GROUP3 enable */\n#define  TSC_IOGCSR_G4E                      ((uint32_t)0x00000008)            /*!<Analog IO GROUP4 enable */\n#define  TSC_IOGCSR_G5E                      ((uint32_t)0x00000010)            /*!<Analog IO GROUP5 enable */\n#define  TSC_IOGCSR_G6E                      ((uint32_t)0x00000020)            /*!<Analog IO GROUP6 enable */\n#define  TSC_IOGCSR_G7E                      ((uint32_t)0x00000040)            /*!<Analog IO GROUP7 enable */\n#define  TSC_IOGCSR_G8E                      ((uint32_t)0x00000080)            /*!<Analog IO GROUP8 enable */\n#define  TSC_IOGCSR_G1S                      ((uint32_t)0x00010000)            /*!<Analog IO GROUP1 status */\n#define  TSC_IOGCSR_G2S                      ((uint32_t)0x00020000)            /*!<Analog IO GROUP2 status */\n#define  TSC_IOGCSR_G3S                      ((uint32_t)0x00040000)            /*!<Analog IO GROUP3 status */\n#define  TSC_IOGCSR_G4S                      ((uint32_t)0x00080000)            /*!<Analog IO GROUP4 status */\n#define  TSC_IOGCSR_G5S                      ((uint32_t)0x00100000)            /*!<Analog IO GROUP5 status */\n#define  TSC_IOGCSR_G6S                      ((uint32_t)0x00200000)            /*!<Analog IO GROUP6 status */\n#define  TSC_IOGCSR_G7S                      ((uint32_t)0x00400000)            /*!<Analog IO GROUP7 status */\n#define  TSC_IOGCSR_G8S                      ((uint32_t)0x00800000)            /*!<Analog IO GROUP8 status */\n\n/*******************  Bit definition for TSC_IOGXCR register  *****************/\n#define  TSC_IOGXCR_CNT                      ((uint32_t)0x00003FFF)            /*!<CNT[13:0] bits (Counter value) */\n\n/******************************************************************************/\n/*                                                                            */\n/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bit definition for USART_CR1 register  *******************/\n#define  USART_CR1_UE                        ((uint32_t)0x00000001)            /*!< USART Enable */\n#define  USART_CR1_UESM                      ((uint32_t)0x00000002)            /*!< USART Enable in STOP Mode */\n#define  USART_CR1_RE                        ((uint32_t)0x00000004)            /*!< Receiver Enable */\n#define  USART_CR1_TE                        ((uint32_t)0x00000008)            /*!< Transmitter Enable */\n#define  USART_CR1_IDLEIE                    ((uint32_t)0x00000010)            /*!< IDLE Interrupt Enable */\n#define  USART_CR1_RXNEIE                    ((uint32_t)0x00000020)            /*!< RXNE Interrupt Enable */\n#define  USART_CR1_TCIE                      ((uint32_t)0x00000040)            /*!< Transmission Complete Interrupt Enable */\n#define  USART_CR1_TXEIE                     ((uint32_t)0x00000080)            /*!< TXE Interrupt Enable */\n#define  USART_CR1_PEIE                      ((uint32_t)0x00000100)            /*!< PE Interrupt Enable */\n#define  USART_CR1_PS                        ((uint32_t)0x00000200)            /*!< Parity Selection */\n#define  USART_CR1_PCE                       ((uint32_t)0x00000400)            /*!< Parity Control Enable */\n#define  USART_CR1_WAKE                      ((uint32_t)0x00000800)            /*!< Receiver Wakeup method */\n#define  USART_CR1_M                         ((uint32_t)0x10001000)            /*!< Word length */\n#define  USART_CR1_M_0                       ((uint32_t)0x00001000)            /*!< Word length - Bit 0 */\n#define  USART_CR1_MME                       ((uint32_t)0x00002000)            /*!< Mute Mode Enable */\n#define  USART_CR1_CMIE                      ((uint32_t)0x00004000)            /*!< Character match interrupt enable */\n#define  USART_CR1_OVER8                     ((uint32_t)0x00008000)            /*!< Oversampling by 8-bit or 16-bit mode */\n#define  USART_CR1_DEDT                      ((uint32_t)0x001F0000)            /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */\n#define  USART_CR1_DEDT_0                    ((uint32_t)0x00010000)            /*!< Bit 0 */\n#define  USART_CR1_DEDT_1                    ((uint32_t)0x00020000)            /*!< Bit 1 */\n#define  USART_CR1_DEDT_2                    ((uint32_t)0x00040000)            /*!< Bit 2 */\n#define  USART_CR1_DEDT_3                    ((uint32_t)0x00080000)            /*!< Bit 3 */\n#define  USART_CR1_DEDT_4                    ((uint32_t)0x00100000)            /*!< Bit 4 */\n#define  USART_CR1_DEAT                      ((uint32_t)0x03E00000)            /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */\n#define  USART_CR1_DEAT_0                    ((uint32_t)0x00200000)            /*!< Bit 0 */\n#define  USART_CR1_DEAT_1                    ((uint32_t)0x00400000)            /*!< Bit 1 */\n#define  USART_CR1_DEAT_2                    ((uint32_t)0x00800000)            /*!< Bit 2 */\n#define  USART_CR1_DEAT_3                    ((uint32_t)0x01000000)            /*!< Bit 3 */\n#define  USART_CR1_DEAT_4                    ((uint32_t)0x02000000)            /*!< Bit 4 */\n#define  USART_CR1_RTOIE                     ((uint32_t)0x04000000)            /*!< Receive Time Out interrupt enable */\n#define  USART_CR1_EOBIE                     ((uint32_t)0x08000000)            /*!< End of Block interrupt enable */\n#define  USART_CR1_M_1                       ((uint32_t)0x10000000)            /*!< Word length - Bit 1 */\n/******************  Bit definition for USART_CR2 register  *******************/\n#define  USART_CR2_ADDM7                     ((uint32_t)0x00000010)            /*!< 7-bit or 4-bit Address Detection */\n#define  USART_CR2_LBDL                      ((uint32_t)0x00000020)            /*!< LIN Break Detection Length */\n#define  USART_CR2_LBDIE                     ((uint32_t)0x00000040)            /*!< LIN Break Detection Interrupt Enable */\n#define  USART_CR2_LBCL                      ((uint32_t)0x00000100)            /*!< Last Bit Clock pulse */\n#define  USART_CR2_CPHA                      ((uint32_t)0x00000200)            /*!< Clock Phase */\n#define  USART_CR2_CPOL                      ((uint32_t)0x00000400)            /*!< Clock Polarity */\n#define  USART_CR2_CLKEN                     ((uint32_t)0x00000800)            /*!< Clock Enable */\n#define  USART_CR2_STOP                      ((uint32_t)0x00003000)            /*!< STOP[1:0] bits (STOP bits) */\n#define  USART_CR2_STOP_0                    ((uint32_t)0x00001000)            /*!< Bit 0 */\n#define  USART_CR2_STOP_1                    ((uint32_t)0x00002000)            /*!< Bit 1 */\n#define  USART_CR2_LINEN                     ((uint32_t)0x00004000)            /*!< LIN mode enable */\n#define  USART_CR2_SWAP                      ((uint32_t)0x00008000)            /*!< SWAP TX/RX pins */\n#define  USART_CR2_RXINV                     ((uint32_t)0x00010000)            /*!< RX pin active level inversion */\n#define  USART_CR2_TXINV                     ((uint32_t)0x00020000)            /*!< TX pin active level inversion */\n#define  USART_CR2_DATAINV                   ((uint32_t)0x00040000)            /*!< Binary data inversion */\n#define  USART_CR2_MSBFIRST                  ((uint32_t)0x00080000)            /*!< Most Significant Bit First */\n#define  USART_CR2_ABREN                     ((uint32_t)0x00100000)            /*!< Auto Baud-Rate Enable*/\n#define  USART_CR2_ABRMODE                   ((uint32_t)0x00600000)            /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */\n#define  USART_CR2_ABRMODE_0                 ((uint32_t)0x00200000)            /*!< Bit 0 */\n#define  USART_CR2_ABRMODE_1                 ((uint32_t)0x00400000)            /*!< Bit 1 */\n#define  USART_CR2_RTOEN                     ((uint32_t)0x00800000)            /*!< Receiver Time-Out enable */\n#define  USART_CR2_ADD                       ((uint32_t)0xFF000000)            /*!< Address of the USART node */\n\n/******************  Bit definition for USART_CR3 register  *******************/\n#define  USART_CR3_EIE                       ((uint32_t)0x00000001)            /*!< Error Interrupt Enable */\n#define  USART_CR3_IREN                      ((uint32_t)0x00000002)            /*!< IrDA mode Enable */\n#define  USART_CR3_IRLP                      ((uint32_t)0x00000004)            /*!< IrDA Low-Power */\n#define  USART_CR3_HDSEL                     ((uint32_t)0x00000008)            /*!< Half-Duplex Selection */\n#define  USART_CR3_NACK                      ((uint32_t)0x00000010)            /*!< SmartCard NACK enable */\n#define  USART_CR3_SCEN                      ((uint32_t)0x00000020)            /*!< SmartCard mode enable */\n#define  USART_CR3_DMAR                      ((uint32_t)0x00000040)            /*!< DMA Enable Receiver */\n#define  USART_CR3_DMAT                      ((uint32_t)0x00000080)            /*!< DMA Enable Transmitter */\n#define  USART_CR3_RTSE                      ((uint32_t)0x00000100)            /*!< RTS Enable */\n#define  USART_CR3_CTSE                      ((uint32_t)0x00000200)            /*!< CTS Enable */\n#define  USART_CR3_CTSIE                     ((uint32_t)0x00000400)            /*!< CTS Interrupt Enable */\n#define  USART_CR3_ONEBIT                    ((uint32_t)0x00000800)            /*!< One sample bit method enable */\n#define  USART_CR3_OVRDIS                    ((uint32_t)0x00001000)            /*!< Overrun Disable */\n#define  USART_CR3_DDRE                      ((uint32_t)0x00002000)            /*!< DMA Disable on Reception Error */\n#define  USART_CR3_DEM                       ((uint32_t)0x00004000)            /*!< Driver Enable Mode */\n#define  USART_CR3_DEP                       ((uint32_t)0x00008000)            /*!< Driver Enable Polarity Selection */\n#define  USART_CR3_SCARCNT                   ((uint32_t)0x000E0000)            /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */\n#define  USART_CR3_SCARCNT_0                 ((uint32_t)0x00020000)            /*!< Bit 0 */\n#define  USART_CR3_SCARCNT_1                 ((uint32_t)0x00040000)            /*!< Bit 1 */\n#define  USART_CR3_SCARCNT_2                 ((uint32_t)0x00080000)            /*!< Bit 2 */\n#define  USART_CR3_WUS                       ((uint32_t)0x00300000)            /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */\n#define  USART_CR3_WUS_0                     ((uint32_t)0x00100000)            /*!< Bit 0 */\n#define  USART_CR3_WUS_1                     ((uint32_t)0x00200000)            /*!< Bit 1 */\n#define  USART_CR3_WUFIE                     ((uint32_t)0x00400000)            /*!< Wake Up Interrupt Enable */\n#define  USART_CR3_UCESM                     ((uint32_t)0x00800000)            /*!< Clock Enable in Stop mode */\n\n/******************  Bit definition for USART_BRR register  *******************/\n#define  USART_BRR_DIV_FRACTION              ((uint16_t)0x000F)                /*!< Fraction of USARTDIV */\n#define  USART_BRR_DIV_MANTISSA              ((uint16_t)0xFFF0)                /*!< Mantissa of USARTDIV */\n\n/******************  Bit definition for USART_GTPR register  ******************/\n#define  USART_GTPR_PSC                      ((uint16_t)0x00FF)                /*!< PSC[7:0] bits (Prescaler value) */\n#define  USART_GTPR_GT                       ((uint16_t)0xFF00)                /*!< GT[7:0] bits (Guard time value) */\n\n\n/*******************  Bit definition for USART_RTOR register  *****************/\n#define  USART_RTOR_RTO                      ((uint32_t)0x00FFFFFF)            /*!< Receiver Time Out Value */\n#define  USART_RTOR_BLEN                     ((uint32_t)0xFF000000)            /*!< Block Length */\n\n/*******************  Bit definition for USART_RQR register  ******************/\n#define  USART_RQR_ABRRQ                    ((uint16_t)0x0001)                /*!< Auto-Baud Rate Request */\n#define  USART_RQR_SBKRQ                    ((uint16_t)0x0002)                /*!< Send Break Request */\n#define  USART_RQR_MMRQ                     ((uint16_t)0x0004)                /*!< Mute Mode Request */\n#define  USART_RQR_RXFRQ                    ((uint16_t)0x0008)                /*!< Receive Data flush Request */\n#define  USART_RQR_TXFRQ                    ((uint16_t)0x0010)                /*!< Transmit data flush Request */\n\n/*******************  Bit definition for USART_ISR register  ******************/\n#define  USART_ISR_PE                        ((uint32_t)0x00000001)            /*!< Parity Error */\n#define  USART_ISR_FE                        ((uint32_t)0x00000002)            /*!< Framing Error */\n#define  USART_ISR_NE                        ((uint32_t)0x00000004)            /*!< Noise detected Flag */\n#define  USART_ISR_ORE                       ((uint32_t)0x00000008)            /*!< OverRun Error */\n#define  USART_ISR_IDLE                      ((uint32_t)0x00000010)            /*!< IDLE line detected */\n#define  USART_ISR_RXNE                      ((uint32_t)0x00000020)            /*!< Read Data Register Not Empty */\n#define  USART_ISR_TC                        ((uint32_t)0x00000040)            /*!< Transmission Complete */\n#define  USART_ISR_TXE                       ((uint32_t)0x00000080)            /*!< Transmit Data Register Empty */\n#define  USART_ISR_LBD                       ((uint32_t)0x00000100)            /*!< LIN Break Detection Flag */\n#define  USART_ISR_CTSIF                     ((uint32_t)0x00000200)            /*!< CTS interrupt flag */\n#define  USART_ISR_CTS                       ((uint32_t)0x00000400)            /*!< CTS flag */\n#define  USART_ISR_RTOF                      ((uint32_t)0x00000800)            /*!< Receiver Time Out */\n#define  USART_ISR_EOBF                      ((uint32_t)0x00001000)            /*!< End Of Block Flag */\n#define  USART_ISR_ABRE                      ((uint32_t)0x00004000)            /*!< Auto-Baud Rate Error */\n#define  USART_ISR_ABRF                      ((uint32_t)0x00008000)            /*!< Auto-Baud Rate Flag */\n#define  USART_ISR_BUSY                      ((uint32_t)0x00010000)            /*!< Busy Flag */\n#define  USART_ISR_CMF                       ((uint32_t)0x00020000)            /*!< Character Match Flag */\n#define  USART_ISR_SBKF                      ((uint32_t)0x00040000)            /*!< Send Break Flag */\n#define  USART_ISR_RWU                       ((uint32_t)0x00080000)            /*!< Receive Wake Up from mute mode Flag */\n#define  USART_ISR_WUF                       ((uint32_t)0x00100000)            /*!< Wake Up from stop mode Flag */\n#define  USART_ISR_TEACK                     ((uint32_t)0x00200000)            /*!< Transmit Enable Acknowledge Flag */\n#define  USART_ISR_REACK                     ((uint32_t)0x00400000)            /*!< Receive Enable Acknowledge Flag */\n\n/*******************  Bit definition for USART_ICR register  ******************/\n#define  USART_ICR_PECF                      ((uint32_t)0x00000001)            /*!< Parity Error Clear Flag */\n#define  USART_ICR_FECF                      ((uint32_t)0x00000002)            /*!< Framing Error Clear Flag */\n#define  USART_ICR_NCF                      ((uint32_t)0x00000004)             /*!< Noise detected Clear Flag */\n#define  USART_ICR_ORECF                     ((uint32_t)0x00000008)            /*!< OverRun Error Clear Flag */\n#define  USART_ICR_IDLECF                    ((uint32_t)0x00000010)            /*!< IDLE line detected Clear Flag */\n#define  USART_ICR_TCCF                      ((uint32_t)0x00000040)            /*!< Transmission Complete Clear Flag */\n#define  USART_ICR_LBDCF                     ((uint32_t)0x00000100)            /*!< LIN Break Detection Clear Flag */\n#define  USART_ICR_CTSCF                     ((uint32_t)0x00000200)            /*!< CTS Interrupt Clear Flag */\n#define  USART_ICR_RTOCF                     ((uint32_t)0x00000800)            /*!< Receiver Time Out Clear Flag */\n#define  USART_ICR_EOBCF                     ((uint32_t)0x00001000)            /*!< End Of Block Clear Flag */\n#define  USART_ICR_CMCF                      ((uint32_t)0x00020000)            /*!< Character Match Clear Flag */\n#define  USART_ICR_WUCF                      ((uint32_t)0x00100000)            /*!< Wake Up from stop mode Clear Flag */\n\n/*******************  Bit definition for USART_RDR register  ******************/\n#define  USART_RDR_RDR                       ((uint16_t)0x01FF)                /*!< RDR[8:0] bits (Receive Data value) */\n\n/*******************  Bit definition for USART_TDR register  ******************/\n#define  USART_TDR_TDR                       ((uint16_t)0x01FF)                /*!< TDR[8:0] bits (Transmit Data value) */\n\n/******************************************************************************/\n/*                                                                            */\n/*                         USB Device General registers                       */\n/*                                                                            */\n/******************************************************************************/\n#define USB_BASE                           ((uint32_t)0x40005C00)           /*!< USB_IP Peripheral Registers base address */\n#define USB_PMAADDR                        ((uint32_t)0x40006000)           /*!< USB_IP Packet Memory Area base address */\n\n#define USB_CNTR                           (USB_BASE + 0x40)             /*!< Control register */\n#define USB_ISTR                           (USB_BASE + 0x44)             /*!< Interrupt status register */\n#define USB_FNR                            (USB_BASE + 0x48)             /*!< Frame number register */\n#define USB_DADDR                          (USB_BASE + 0x4C)             /*!< Device address register */\n#define USB_BTABLE                         (USB_BASE + 0x50)             /*!< Buffer Table address register */\n#define USB_LPMCSR                         (USB_BASE + 0x54)             /*!< LPM Control and Status register */\n#define USB_BCDR                           (USB_BASE + 0x58)             /*!< Battery Charging detector register*/\n\n/****************************  ISTR interrupt events  *************************/\n#define USB_ISTR_CTR                         ((uint16_t)0x8000)             /*!< Correct TRansfer (clear-only bit) */\n#define USB_ISTR_PMAOVR                      ((uint16_t)0x4000)             /*!< DMA OVeR/underrun (clear-only bit) */\n#define USB_ISTR_ERR                         ((uint16_t)0x2000)             /*!< ERRor (clear-only bit) */\n#define USB_ISTR_WKUP                        ((uint16_t)0x1000)             /*!< WaKe UP (clear-only bit) */\n#define USB_ISTR_SUSP                        ((uint16_t)0x0800)             /*!< SUSPend (clear-only bit) */\n#define USB_ISTR_RESET                       ((uint16_t)0x0400)             /*!< RESET (clear-only bit) */\n#define USB_ISTR_SOF                         ((uint16_t)0x0200)             /*!< Start Of Frame (clear-only bit) */\n#define USB_ISTR_ESOF                        ((uint16_t)0x0100)             /*!< Expected Start Of Frame (clear-only bit) */\n#define USB_ISTR_L1REQ                       ((uint16_t)0x0080)             /*!< LPM L1 state request  */\n#define USB_ISTR_DIR                         ((uint16_t)0x0010)             /*!< DIRection of transaction (read-only bit)  */\n#define USB_ISTR_EP_ID                       ((uint16_t)0x000F)             /*!< EndPoint IDentifier (read-only bit)  */\n\n#define USB_CLR_CTR                          (~USB_ISTR_CTR)             /*!< clear Correct TRansfer bit */\n#define USB_CLR_PMAOVR                       (~USB_ISTR_PMAOVR)          /*!< clear DMA OVeR/underrun bit*/\n#define USB_CLR_ERR                          (~USB_ISTR_ERR)             /*!< clear ERRor bit */\n#define USB_CLR_WKUP                         (~USB_ISTR_WKUP)            /*!< clear WaKe UP bit */\n#define USB_CLR_SUSP                         (~USB_ISTR_SUSP)            /*!< clear SUSPend bit */\n#define USB_CLR_RESET                        (~USB_ISTR_RESET)           /*!< clear RESET bit */\n#define USB_CLR_SOF                          (~USB_ISTR_SOF)             /*!< clear Start Of Frame bit */\n#define USB_CLR_ESOF                         (~USB_ISTR_ESOF)            /*!< clear Expected Start Of Frame bit */\n#define USB_CLR_L1REQ                        (~USB_ISTR_L1REQ)           /*!< clear LPM L1  bit */\n/*************************  CNTR control register bits definitions  ***********/\n#define USB_CNTR_CTRM                        ((uint16_t)0x8000)             /*!< Correct TRansfer Mask */\n#define USB_CNTR_PMAOVRM                     ((uint16_t)0x4000)             /*!< DMA OVeR/underrun Mask */\n#define USB_CNTR_ERRM                        ((uint16_t)0x2000)             /*!< ERRor Mask */\n#define USB_CNTR_WKUPM                       ((uint16_t)0x1000)             /*!< WaKe UP Mask */\n#define USB_CNTR_SUSPM                       ((uint16_t)0x0800)             /*!< SUSPend Mask */\n#define USB_CNTR_RESETM                      ((uint16_t)0x0400)             /*!< RESET Mask   */\n#define USB_CNTR_SOFM                        ((uint16_t)0x0200)             /*!< Start Of Frame Mask */\n#define USB_CNTR_ESOFM                       ((uint16_t)0x0100)             /*!< Expected Start Of Frame Mask */\n#define USB_CNTR_L1REQM                      ((uint16_t)0x0080)             /*!< LPM L1 state request interrupt mask */\n#define USB_CNTR_L1RESUME                    ((uint16_t)0x0020)             /*!< LPM L1 Resume request */\n#define USB_CNTR_RESUME                      ((uint16_t)0x0010)             /*!< RESUME request */\n#define USB_CNTR_FSUSP                       ((uint16_t)0x0008)             /*!< Force SUSPend */\n#define USB_CNTR_LPMODE                      ((uint16_t)0x0004)             /*!< Low-power MODE */\n#define USB_CNTR_PDWN                        ((uint16_t)0x0002)             /*!< Power DoWN */\n#define USB_CNTR_FRES                        ((uint16_t)0x0001)             /*!< Force USB RESet */\n/*************************  BCDR control register bits definitions  ***********/\n#define  USB_BCDR_DPPU                       ((uint16_t)0x8000)             /*!< DP Pull-up Enable */\n#define  USB_BCDR_PS2DET                     ((uint16_t)0x0080)             /*!< PS2 port or proprietary charger detected */\n#define  USB_BCDR_SDET                       ((uint16_t)0x0040)             /*!< Secondary detection (SD) status */\n#define  USB_BCDR_PDET                       ((uint16_t)0x0020)             /*!< Primary detection (PD) status */\n#define  USB_BCDR_DCDET                      ((uint16_t)0x0010)             /*!< Data contact detection (DCD) status */\n#define  USB_BCDR_SDEN                       ((uint16_t)0x0008)             /*!< Secondary detection (SD) mode enable */\n#define  USB_BCDR_PDEN                       ((uint16_t)0x0004)             /*!< Primary detection (PD) mode enable */\n#define  USB_BCDR_DCDEN                      ((uint16_t)0x0002)             /*!< Data contact detection (DCD) mode enable */\n#define  USB_BCDR_BCDEN                      ((uint16_t)0x0001)             /*!< Battery charging detector (BCD) enable */\n/***************************  LPM register bits definitions  ******************/\n#define  USB_LPMCSR_BESL                     ((uint16_t)0x00F0)             /*!< BESL value received with last ACKed LPM Token  */\n#define  USB_LPMCSR_REMWAKE                  ((uint16_t)0x0008)             /*!< bRemoteWake value received with last ACKed LPM Token */\n#define  USB_LPMCSR_LPMACK                   ((uint16_t)0x0002)             /*!< LPM Token acknowledge enable*/\n#define  USB_LPMCSR_LMPEN                    ((uint16_t)0x0001)             /*!< LPM support enable  */\n/********************  FNR Frame Number Register bit definitions   ************/\n#define USB_FNR_RXDP                         ((uint16_t)0x8000)             /*!< status of D+ data line */\n#define USB_FNR_RXDM                         ((uint16_t)0x4000)             /*!< status of D- data line */\n#define USB_FNR_LCK                          ((uint16_t)0x2000)             /*!< LoCKed */\n#define USB_FNR_LSOF                         ((uint16_t)0x1800)             /*!< Lost SOF */\n#define USB_FNR_FN                           ((uint16_t)0x07FF)             /*!< Frame Number */\n/********************  DADDR Device ADDRess bit definitions    ****************/\n#define USB_DADDR_EF                         ((uint8_t)0x80)                /*!< USB device address Enable Function */\n#define USB_DADDR_ADD                        ((uint8_t)0x7F)                /*!< USB device address */\n/******************************  Endpoint register    *************************/\n#define USB_EP0R                              USB_BASE                   /*!< endpoint 0 register address */\n#define USB_EP1R                             (USB_BASE + 0x04)           /*!< endpoint 1 register address */\n#define USB_EP2R                             (USB_BASE + 0x08)           /*!< endpoint 2 register address */\n#define USB_EP3R                             (USB_BASE + 0x0C)           /*!< endpoint 3 register address */\n#define USB_EP4R                             (USB_BASE + 0x10)           /*!< endpoint 4 register address */\n#define USB_EP5R                             (USB_BASE + 0x14)           /*!< endpoint 5 register address */\n#define USB_EP6R                             (USB_BASE + 0x18)           /*!< endpoint 6 register address */\n#define USB_EP7R                             (USB_BASE + 0x1C)           /*!< endpoint 7 register address */\n/* bit positions */\n#define USB_EP_CTR_RX                        ((uint16_t)0x8000)             /*!<  EndPoint Correct TRansfer RX */\n#define USB_EP_DTOG_RX                       ((uint16_t)0x4000)             /*!<  EndPoint Data TOGGLE RX */\n#define USB_EPRX_STAT                        ((uint16_t)0x3000)             /*!<  EndPoint RX STATus bit field */\n#define USB_EP_SETUP                         ((uint16_t)0x0800)             /*!<  EndPoint SETUP */\n#define USB_EP_T_FIELD                       ((uint16_t)0x0600)             /*!<  EndPoint TYPE */\n#define USB_EP_KIND                          ((uint16_t)0x0100)             /*!<  EndPoint KIND */\n#define USB_EP_CTR_TX                        ((uint16_t)0x0080)             /*!<  EndPoint Correct TRansfer TX */\n#define USB_EP_DTOG_TX                       ((uint16_t)0x0040)             /*!<  EndPoint Data TOGGLE TX */\n#define USB_EPTX_STAT                        ((uint16_t)0x0030)             /*!<  EndPoint TX STATus bit field */\n#define USB_EPADDR_FIELD                     ((uint16_t)0x000F)             /*!<  EndPoint ADDRess FIELD */\n\n/* EndPoint REGister MASK (no toggle fields) */\n#define USB_EPREG_MASK     (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)\n                                                                               /*!< EP_TYPE[1:0] EndPoint TYPE */\n#define USB_EP_TYPE_MASK                     ((uint16_t)0x0600)             /*!< EndPoint TYPE Mask */\n#define USB_EP_BULK                          ((uint16_t)0x0000)             /*!< EndPoint BULK */\n#define USB_EP_CONTROL                       ((uint16_t)0x0200)             /*!< EndPoint CONTROL */\n#define USB_EP_ISOCHRONOUS                   ((uint16_t)0x0400)             /*!< EndPoint ISOCHRONOUS */\n#define USB_EP_INTERRUPT                     ((uint16_t)0x0600)             /*!< EndPoint INTERRUPT */\n#define USB_EP_T_MASK      (~USB_EP_T_FIELD & USB_EPREG_MASK)\n\n#define USB_EPKIND_MASK    (~USB_EP_KIND & USB_EPREG_MASK)            /*!< EP_KIND EndPoint KIND */\n                                                                               /*!< STAT_TX[1:0] STATus for TX transfer */\n#define USB_EP_TX_DIS                        ((uint16_t)0x0000)             /*!< EndPoint TX DISabled */\n#define USB_EP_TX_STALL                      ((uint16_t)0x0010)             /*!< EndPoint TX STALLed */\n#define USB_EP_TX_NAK                        ((uint16_t)0x0020)             /*!< EndPoint TX NAKed */\n#define USB_EP_TX_VALID                      ((uint16_t)0x0030)             /*!< EndPoint TX VALID */\n#define USB_EPTX_DTOG1                       ((uint16_t)0x0010)             /*!< EndPoint TX Data TOGgle bit1 */\n#define USB_EPTX_DTOG2                       ((uint16_t)0x0020)             /*!< EndPoint TX Data TOGgle bit2 */\n#define USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)\n                                                                               /*!< STAT_RX[1:0] STATus for RX transfer */\n#define USB_EP_RX_DIS                        ((uint16_t)0x0000)             /*!< EndPoint RX DISabled */\n#define USB_EP_RX_STALL                      ((uint16_t)0x1000)             /*!< EndPoint RX STALLed */\n#define USB_EP_RX_NAK                        ((uint16_t)0x2000)             /*!< EndPoint RX NAKed */\n#define USB_EP_RX_VALID                      ((uint16_t)0x3000)             /*!< EndPoint RX VALID */\n#define USB_EPRX_DTOG1                       ((uint16_t)0x1000)             /*!< EndPoint RX Data TOGgle bit1 */\n#define USB_EPRX_DTOG2                       ((uint16_t)0x2000)             /*!< EndPoint RX Data TOGgle bit1 */\n#define USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)\n\n/******************************************************************************/\n/*                                                                            */\n/*                         Window WATCHDOG (WWDG)                             */\n/*                                                                            */\n/******************************************************************************/\n\n/*******************  Bit definition for WWDG_CR register  ********************/\n#define  WWDG_CR_T                           ((uint8_t)0x7F)               /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */\n#define  WWDG_CR_T0                          ((uint8_t)0x01)               /*!< Bit 0 */\n#define  WWDG_CR_T1                          ((uint8_t)0x02)               /*!< Bit 1 */\n#define  WWDG_CR_T2                          ((uint8_t)0x04)               /*!< Bit 2 */\n#define  WWDG_CR_T3                          ((uint8_t)0x08)               /*!< Bit 3 */\n#define  WWDG_CR_T4                          ((uint8_t)0x10)               /*!< Bit 4 */\n#define  WWDG_CR_T5                          ((uint8_t)0x20)               /*!< Bit 5 */\n#define  WWDG_CR_T6                          ((uint8_t)0x40)               /*!< Bit 6 */\n\n#define  WWDG_CR_WDGA                        ((uint8_t)0x80)               /*!< Activation bit */\n\n/*******************  Bit definition for WWDG_CFR register  *******************/\n#define  WWDG_CFR_W                          ((uint16_t)0x007F)            /*!< W[6:0] bits (7-bit window value) */\n#define  WWDG_CFR_W0                         ((uint16_t)0x0001)            /*!< Bit 0 */\n#define  WWDG_CFR_W1                         ((uint16_t)0x0002)            /*!< Bit 1 */\n#define  WWDG_CFR_W2                         ((uint16_t)0x0004)            /*!< Bit 2 */\n#define  WWDG_CFR_W3                         ((uint16_t)0x0008)            /*!< Bit 3 */\n#define  WWDG_CFR_W4                         ((uint16_t)0x0010)            /*!< Bit 4 */\n#define  WWDG_CFR_W5                         ((uint16_t)0x0020)            /*!< Bit 5 */\n#define  WWDG_CFR_W6                         ((uint16_t)0x0040)            /*!< Bit 6 */\n\n#define  WWDG_CFR_WDGTB                      ((uint16_t)0x0180)            /*!< WDGTB[1:0] bits (Timer Base) */\n#define  WWDG_CFR_WDGTB0                     ((uint16_t)0x0080)            /*!< Bit 0 */\n#define  WWDG_CFR_WDGTB1                     ((uint16_t)0x0100)            /*!< Bit 1 */\n\n#define  WWDG_CFR_EWI                        ((uint16_t)0x0200)            /*!< Early Wakeup Interrupt */\n\n/*******************  Bit definition for WWDG_SR register  ********************/\n#define  WWDG_SR_EWIF                        ((uint8_t)0x01)               /*!< Early Wakeup Interrupt Flag */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup Exported_macros\n  * @{\n  */\n\n/******************************* ADC Instances ********************************/\n#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)\n\n/******************************** COMP Instances ******************************/\n#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \\\n                                       ((INSTANCE) == COMP2))\n\n/******************************* CRC Instances ********************************/\n#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)\n\n/******************************* DAC Instances ********************************/\n#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)\n\n/******************************** DMA Instances *******************************/\n#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \\\n                                              ((INSTANCE) == DMA1_Stream1) || \\\n                                              ((INSTANCE) == DMA1_Stream2) || \\\n                                              ((INSTANCE) == DMA1_Stream3) || \\\n                                              ((INSTANCE) == DMA1_Stream4) || \\\n                                              ((INSTANCE) == DMA1_Stream5) || \\\n                                              ((INSTANCE) == DMA1_Stream6) || \\\n                                              ((INSTANCE) == DMA1_Stream7))\n\n/******************************* GPIO Instances *******************************/\n#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \\\n                                        ((INSTANCE) == GPIOB) || \\\n                                        ((INSTANCE) == GPIOC) || \\\n                                        ((INSTANCE) == GPIOD) || \\\n                                        ((INSTANCE) == GPIOH))\n\n\n/******************************** I2C Instances *******************************/\n#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \\\n                                       ((INSTANCE) == I2C2))\n\n/******************************** I2S Instances *******************************/\n#define IS_I2S_INSTANCE(INSTANCE)  ((INSTANCE) == SPI2)\n\n/******************************* RNG Instances ********************************/\n#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)\n\n/****************************** RTC Instances *********************************/\n#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)\n\n/******************************** SMBUS Instances *****************************/\n#define IS_SMBUS_INSTANCE(INSTANCE)  ((INSTANCE) == I2C1)\n\n/******************************** SPI Instances *******************************/\n#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \\\n                                       ((INSTANCE) == SPI2))\n/****************** LPTIM Instances : All supported instances *****************/\n#define IS_LPTIM_INSTANCE(INSTANCE)       ((INSTANCE) == LPTIM1)\n\n/****************** TIM Instances : All supported instances *******************/\n#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \\\n                                         ((INSTANCE) == TIM6)   || \\\n                                         ((INSTANCE) == TIM21)  || \\\n                                         ((INSTANCE) == TIM22))\n\n/************* TIM Instances : at least 1 capture/compare channel *************/\n#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)  || \\\n                                         ((INSTANCE) == TIM21) || \\\n                                         ((INSTANCE) == TIM22))\n\n/************ TIM Instances : at least 2 capture/compare channels *************/\n#define IS_TIM_CC2_INSTANCE(INSTANCE)  (((INSTANCE) == TIM2)  || \\\n                                        ((INSTANCE) == TIM21) || \\\n                                        ((INSTANCE) == TIM22))\n\n/************ TIM Instances : at least 3 capture/compare channels *************/\n#define IS_TIM_CC3_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)\n\n/************ TIM Instances : at least 4 capture/compare channels *************/\n#define IS_TIM_CC4_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)\n\n/******************** TIM Instances : Advanced-control timers *****************/\n\n/******************* TIM Instances : Timer input XOR function *****************/\n#define IS_TIM_XOR_INSTANCE(INSTANCE)      ((INSTANCE) == TIM2)\n\n\n/****************** TIM Instances : DMA requests generation (UDE) *************/\n#define IS_TIM_DMA_INSTANCE(INSTANCE)      (((INSTANCE) == TIM2) || \\\n                                            ((INSTANCE) == TIM6))\n/************ TIM Instances : DMA requests generation (CCxDE) *****************/\n#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)\n\n/************ TIM Instances : DMA requests generation (COMDE) *****************/\n#define IS_TIM_CCDMA_INSTANCE(INSTANCE)    ((INSTANCE) == TIM2)\n\n/******************** TIM Instances : DMA burst feature ***********************/\n#define IS_TIM_DMABURST_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)\n\n/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/\n#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)   || \\\n                                             ((INSTANCE) == TIM6)  || \\\n                                             ((INSTANCE) == TIM21) || \\\n                                             ((INSTANCE) == TIM22))\n\n/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/\n#define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM2)  || \\\n                                            ((INSTANCE) == TIM21) || \\\n                                            ((INSTANCE) == TIM22))\n\n/********************** TIM Instances : 32 bit Counter ************************/\n\n/***************** TIM Instances : external trigger input availabe ************/\n#define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM2)  || \\\n                                            ((INSTANCE) == TIM21) || \\\n                                            ((INSTANCE) == TIM22))\n\n/****************** TIM Instances : remapping capability **********************/\n#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)   || \\\n                                         ((INSTANCE) == TIM21)  || \\\n                                         ((INSTANCE) == TIM22))\n\n/******************* TIM Instances : output(s) available **********************/\n#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \\\n    ((((INSTANCE) == TIM2) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n     ||                                        \\\n     (((INSTANCE) == TIM21) &&                 \\\n      (((CHANNEL) == TIM_CHANNEL_1) ||         \\\n       ((CHANNEL) == TIM_CHANNEL_2)))          \\\n     ||                                        \\\n     (((INSTANCE) == TIM22) &&                 \\\n      (((CHANNEL) == TIM_CHANNEL_1) ||         \\\n       ((CHANNEL) == TIM_CHANNEL_2))))\n\n/******************** UART Instances : Asynchronous mode **********************/\n#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                     ((INSTANCE) == USART2) || \\\n                                     ((INSTANCE) == LPUART1))\n\n/******************** USART Instances : Synchronous mode **********************/\n#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                    ((INSTANCE) == USART2))\n\n/****************** UART Instances : Hardware Flow control ********************/\n#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                           ((INSTANCE) == USART2) || \\\n                                           ((INSTANCE) == LPUART1))\n\n\n/********************* UART Instances : Smard card mode ***********************/\n#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                         ((INSTANCE) == USART2))\n\n/*********************** UART Instances : IRDA mode ***************************/\n#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                    ((INSTANCE) == USART2))\n\n/****************************** IWDG Instances ********************************/\n#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)\n\n/****************************** USB Instances ********************************/\n#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)\n\n/****************************** WWDG Instances ********************************/\n#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)\n\n/**\n  * @}\n  */\n\n/******************************************************************************/\n/*  For a painless codes migration between the STM32L0xx device product       */\n/*  lines, the aliases defined below are put in place to overcome the         */\n/*  differences in the interrupt handlers and IRQn definitions.               */\n/*  No need to update developed interrupt code when moving across             */\n/*  product lines within the same STM32L0 Family                              */\n/******************************************************************************/\n\n/* Aliases for __IRQn */\n\n#define LPUART1_IRQn             RNG_LPUART1_IRQn\n#define AES_LPUART1_IRQn         RNG_LPUART1_IRQn\n#define AES_RNG_LPUART1_IRQn     RNG_LPUART1_IRQn\n\n#define TIM6_IRQn                TIM6_DAC_IRQn\n\n#define RCC_IRQn      RCC_CRS_IRQn\n\n/* Aliases for __IRQHandler */\n#define LPUART1_IRQHandler             RNG_LPUART1_IRQHandler\n#define AES_LPUART1_IRQHandler         RNG_LPUART1_IRQHandler\n#define AES_RNG_LPUART1_IRQHandler     RNG_LPUART1_IRQHandler\n\n#define TIM6_IRQHandler                TIM6_DAC_IRQHandler\n\n#define RCC_IRQHandler             RCC_CRS_IRQHandler\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* __STM32L053xx_H */\n\n\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "3rd_party/nucleo-l053r8/stm32l0xx.h",
    "content": "/*=============================================================================\n* Modified from the original as follows:\n* - uncommented  #define STM32L053xx to select this group of devices\n*\n* Quantum Leaps, LLC, www.state-machine.com\n* 2015-03-25\n*=============================================================================*/\n/**\n  ******************************************************************************\n  * @file    stm32l0xx.h\n  * @author  MCD Application Team\n  * @version V1.0.0RC1\n  * @date    15-April-2014\n  * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.\n  *          This file contains all the peripheral register's definitions, bits\n  *          definitions and memory mapping for STM32L0xx devices.\n  *\n  *          The file is the unique include file that the application programmer\n  *          is using in the C source code, usually in main.c. This file contains:\n  *           - Configuration section that allows to select:\n  *              - The device used in the target application\n  *              - To use or not the peripheral’s drivers in application code(i.e.\n  *                code will be based on direct access to peripheral’s registers\n  *                rather than drivers API), this option is controlled by\n  *                \"#define USE_HAL_DRIVER\"\n  *\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/** @addtogroup CMSIS\n  * @{\n  */\n\n/** @addtogroup stm32l0xx\n  * @{\n  */\n\n#ifndef __STM32L0xx_H\n#define __STM32L0xx_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif /* __cplusplus */\n\n/** @addtogroup Library_configuration_section\n  * @{\n  */\n\n/* Uncomment the line below according to the target STM32 device used in your\n   application\n  */\n\n#if !defined (STM32L051xx) && !defined (STM32L052xx) && !defined (STM32L053xx) && !defined (STM32L062xx) && \\\n    !defined (STM32L063xx) && !defined (STM32L061xx)\n  /* #define STM32L051xx */   /*!< STM32L051K8, STM32L051C6,STM32L051C8,STM32L051R6 and STM32L051R8 Devices */\n  /* #define STM32L052xx */   /*!< STM32L052K6, STM32L052K8,STM32L052C6,STM32L052C8,STM32L052R6 and STM32L052R8 Devices */\n  #define STM32L053xx   /*!< STM32L053C6, STM32L053C8, STM32L053R6, and STM32L053R8 Devices */\n  /* #define STM32L062xx */   /*!< STM32L062K8 */\n  /* #define STM32L063xx */   /*!< STM32L063C8, STM32L063R8 */\n  /* #define STM32L061xx */\n#endif\n\n/*  Tip: To avoid modifying this file each time you need to switch between these\n        devices, you can define the device in your toolchain compiler preprocessor.\n  */\n#if !defined  (USE_HAL_DRIVER)\n/**\n * @brief Comment the line below if you will not use the peripherals drivers.\n   In this case, these drivers will not be included and the application code will\n   be based on direct access to peripherals registers\n   */\n  /*#define USE_HAL_DRIVER */\n#endif /* USE_HAL_DRIVER */\n\n/**\n  * @brief CMSIS Device version number V1.0.0RC1\n  */\n#define __STM32L0xx_CMSIS_DEVICE_VERSION_MAIN   (0x01) /*!< [31:24] main version */\n#define __STM32L0xx_CMSIS_DEVICE_VERSION_SUB1   (0x00) /*!< [23:16] sub1 version */\n#define __STM32L0xx_CMSIS_DEVICE_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */\n#define __STM32L0xx_CMSIS_DEVICE_VERSION_RC     (0x01) /*!< [7:0]  release candidate */\n#define __STM32L0xx_CMSIS_DEVICE_VERSION        ((__CMSIS_DEVICE_VERSION_MAIN     << 24)\\\n                                      |(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\\\n                                      |(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\\\n                                      |(__CMSIS_DEVICE_HAL_VERSION_RC))\n\n/**\n  * @}\n  */\n\n/** @addtogroup Device_Included\n  * @{\n  */\n\n#if defined(STM32L051xx)\n  #include \"stm32l051xx.h\"\n#elif defined(STM32L052xx)\n  #include \"stm32l052xx.h\"\n#elif defined(STM32L053xx)\n  #include \"stm32l053xx.h\"\n#elif defined(STM32L062xx)\n  #include \"stm32l062xx.h\"\n#elif defined(STM32L063xx)\n  #include \"stm32l063xx.h\"\n#elif defined(STM32L061xx)\n  #include \"stm32l061xx.h\"\n#else\n #error \"Please select first the target STM32L0xx device used in your application (in stm32l0xx.h file)\"\n#endif\n\n/**\n  * @}\n  */\n\n/** @addtogroup Exported_types\n  * @{\n  */\ntypedef enum\n{\n  RESET = 0,\n  SET = !RESET\n} FlagStatus, ITStatus;\n\ntypedef enum\n{\n  DISABLE = 0,\n  ENABLE = !DISABLE\n} FunctionalState;\n#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))\n\ntypedef enum\n{\n  ERROR = 0,\n  SUCCESS = !ERROR\n} ErrorStatus;\n\n/**\n  * @}\n  */\n\n\n/** @addtogroup Exported_macro\n  * @{\n  */\n#define SET_BIT(REG, BIT)     ((REG) |= (BIT))\n\n#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))\n\n#define READ_BIT(REG, BIT)    ((REG) & (BIT))\n\n#define CLEAR_REG(REG)        ((REG) = (0x0))\n\n#define WRITE_REG(REG, VAL)   ((REG) = (VAL))\n\n#define READ_REG(REG)         ((REG))\n\n#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))\n\n\n\n/**\n  * @}\n  */\n\n#if defined (USE_HAL_DRIVER)\n #include \"stm32l0xx_hal.h\"\n#endif /* USE_HAL_DRIVER */\n\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* __STM32L0xx_H */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n\n\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "3rd_party/nucleo-l053r8/system_stm32l0xx.c",
    "content": "/**\n  ******************************************************************************\n  * @file    system_stm32l0xx.c\n  * @author  MCD Application Team\n  * @version V1.0.0RC1\n  * @date    15-April-2014\n  * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File.\n  *\n  *   This file provides two functions and one global variable to be called from\n  *   user application:\n  *      - SystemInit(): This function is called at startup just after reset and\n  *                      before branch to main program. This call is made inside\n  *                      the \"startup_stm32l0xx.s\" file.\n  *\n  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used\n  *                                  by the user application to setup the SysTick\n  *                                  timer or configure other parameters.\n  *\n  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must\n  *                                 be called whenever the core clock is changed\n  *                                 during program execution.\n  *\n  *\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/** @addtogroup CMSIS\n  * @{\n  */\n\n/** @addtogroup stm32l0xx_system\n  * @{\n  */\n\n/** @addtogroup STM32L0xx_System_Private_Includes\n  * @{\n  */\n\n#include \"stm32l0xx.h\"\n\n#if !defined  (HSE_VALUE)\n  #define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */\n#endif /* HSE_VALUE */\n\n#if !defined  (MSI_VALUE)\n  #define MSI_VALUE    ((uint32_t)2000000) /*!< Value of the Internal oscillator in Hz*/\n#endif /* MSI_VALUE */\n\n#if !defined  (HSI_VALUE)\n  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/\n#endif /* HSI_VALUE */\n\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32L0xx_System_Private_TypesDefinitions\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32L0xx_System_Private_Defines\n  * @{\n  */\n/************************* Miscellaneous Configuration ************************/\n\n/*!< Uncomment the following line if you need to relocate your vector Table in\n     Internal SRAM. */\n/* #define VECT_TAB_SRAM */\n#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field.\n                                   This value must be a multiple of 0x200. */\n/******************************************************************************/\n/**\n  * @}\n  */\n\n/** @addtogroup STM32L0xx_System_Private_Macros\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32L0xx_System_Private_Variables\n  * @{\n  */\n/* This variable is updated in three ways:\n * 1) by calling CMSIS function SystemCoreClockUpdate()\n * 2) by calling HAL API function HAL_RCC_GetSysClockFreq()\n * 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency\n *    Note: If you use this function to configure the system clock; then there\n *          is no need to call the 2 first functions listed above, since SystemCoreClock\n *          variable is updated automatically.\n */\nuint32_t SystemCoreClock = 2000000;\n\n__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};\n__I uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32L0xx_System_Private_FunctionPrototypes\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32L0xx_System_Private_Functions\n  * @{\n  */\n\n/**\n  * @brief  Setup the microcontroller system.\n  * @param  None\n  * @retval None\n  */\nvoid SystemInit (void)\n{\n/*!< Set MSION bit */\n  RCC->CR |= (uint32_t)0x00000100;\n\n  /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */\n  RCC->CFGR &= (uint32_t)0x88FF400C;\n\n  /*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */\n  RCC->CR &= (uint32_t)0xFEF6FFF6;\n\n  /*!< Reset HSI48ON  bit */\n  RCC->CRRCR &= (uint32_t)0xFFFFFFFE;\n\n  /*!< Reset HSEBYP bit */\n  RCC->CR &= (uint32_t)0xFFFBFFFF;\n\n  /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */\n  RCC->CFGR &= (uint32_t)0xFF02FFFF;\n\n  /*!< Disable all interrupts */\n  RCC->CIER = 0x00000000;\n\n  /* Configure the Vector Table location add offset address ------------------*/\n#ifdef VECT_TAB_SRAM\n  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */\n#else\n  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */\n#endif\n}\n\n/**\n  * @brief  Update SystemCoreClock according to Clock Register Values\n  *         The SystemCoreClock variable contains the core clock (HCLK), it can\n  *         be used by the user application to setup the SysTick timer or configure\n  *         other parameters.\n  *\n  * @note   Each time the core clock (HCLK) changes, this function must be called\n  *         to update SystemCoreClock variable value. Otherwise, any configuration\n  *         based on this variable will be incorrect.\n  *\n  * @note   - The system frequency computed by this function is not the real\n  *           frequency in the chip. It is calculated based on the predefined\n  *           constant and the selected clock source:\n  *\n  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI\n  *             value as defined by the MSI range.\n  *\n  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)\n  *\n  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)\n  *\n  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)\n  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.\n  *\n  *         (*) HSI_VALUE is a constant defined in stm32l0xx_hal.h file (default value\n  *             16 MHz) but the real value may vary depending on the variations\n  *             in voltage and temperature.\n  *\n  *         (**) HSE_VALUE is a constant defined in stm32l0xx_hal.h file (default value\n  *              8 MHz), user has to ensure that HSE_VALUE is same as the real\n  *              frequency of the crystal used. Otherwise, this function may\n  *              have wrong result.\n  *\n  *         - The result of this function could be not correct when using fractional\n  *           value for HSE crystal.\n  * @param  None\n  * @retval None\n  */\nvoid SystemCoreClockUpdate (void)\n{\n  uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;\n\n  /* Get SYSCLK source -------------------------------------------------------*/\n  tmp = RCC->CFGR & RCC_CFGR_SWS;\n\n  switch (tmp)\n  {\n    case 0x00:  /* MSI used as system clock */\n      SystemCoreClock = ((1 <<((RCC->ICSCR & RCC_ICSCR_MSIRANGE)>>13 ))* 64000);\n      break;\n    case 0x04:  /* HSI used as system clock */\n      SystemCoreClock = HSI_VALUE;\n      break;\n    case 0x08:  /* HSE used as system clock */\n      SystemCoreClock = HSE_VALUE;\n      break;\n    case 0x0C:  /* PLL used as system clock */\n      /* Get PLL clock source and multiplication factor ----------------------*/\n      pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;\n      plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;\n      pllmul = PLLMulTable[(pllmul >> 18)];\n      plldiv = (plldiv >> 22) + 1;\n\n      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;\n\n      if (pllsource == 0x00)\n      {\n        /* HSI oscillator clock selected as PLL clock entry */\n        SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);\n      }\n      else\n      {\n        /* HSE selected as PLL clock entry */\n        SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);\n      }\n      break;\n    default: /* MSI used as system clock */\n      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;\n      SystemCoreClock = (32768 * (1 << (msirange + 1)));\n      break;\n  }\n  /* Compute HCLK clock frequency --------------------------------------------*/\n  /* Get HCLK prescaler */\n  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];\n  /* HCLK clock frequency */\n  SystemCoreClock >>= tmp;\n}\n\n\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "3rd_party/nucleo-l053r8/system_stm32l0xx.c.pll",
    "content": "/**\n  ******************************************************************************\n  * @file    system_stm32l0xx.c\n  * @author  MCD Application Team\n  * @version V1.0.0RC1\n  * @date    15-April-2014\n  * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File.\n  *\n  *   This file provides two functions and one global variable to be called from\n  *   user application:\n  *      - SystemInit(): This function is called at startup just after reset and\n  *                      before branch to main program. This call is made inside\n  *                      the \"startup_stm32l0xx.s\" file.\n  *\n  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used\n  *                                  by the user application to setup the SysTick\n  *                                  timer or configure other parameters.\n  *\n  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must\n  *                                 be called whenever the core clock is changed\n  *                                 during program execution.\n  *\n  *\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/** @addtogroup CMSIS\n  * @{\n  */\n\n/** @addtogroup stm32l0xx_system\n  * @{\n  */\n\n/** @addtogroup STM32L0xx_System_Private_Includes\n  * @{\n  */\n\n#include \"stm32l0xx.h\"\n\n#if !defined  (HSE_VALUE)\n  #define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */\n#endif /* HSE_VALUE */\n\n#if !defined  (MSI_VALUE)\n  #define MSI_VALUE    ((uint32_t)2000000) /*!< Value of the Internal oscillator in Hz*/\n#endif /* MSI_VALUE */\n\n#if !defined  (HSI_VALUE)\n  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/\n#endif /* HSI_VALUE */\n\n/**\n * @brief In the following line adjust the External High Speed oscillator (HSE) Startup\n   Timeout value\n   */\n#if !defined  (HSE_STARTUP_TIMEOUT)\n#define HSE_STARTUP_TIMEOUT   ((uint16_t)0x5000) /*!< Time out for HSE start up */\n#endif\n\n/**\n * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup\n   Timeout value\n   */\n#if !defined  (HSI_STARTUP_TIMEOUT)\n#define HSI_STARTUP_TIMEOUT   ((uint16_t)0x5000) /*!< Time out for HSI start up */\n#endif\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32L0xx_System_Private_TypesDefinitions\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32L0xx_System_Private_Defines\n  * @{\n  */\n/************************* Miscellaneous Configuration ************************/\n\n/*!< Uncomment the following line if you need to relocate your vector Table in\n     Internal SRAM. */\n/* #define VECT_TAB_SRAM */\n#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field.\n                                   This value must be a multiple of 0x200. */\n/******************************************************************************/\n/**\n  * @}\n  */\n\n/** @addtogroup STM32L0xx_System_Private_Macros\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32L0xx_System_Private_Variables\n  * @{\n  */\n  /* This variable is updated in three ways:\n      1) by calling CMSIS function SystemCoreClockUpdate()\n      2) by calling HAL API function HAL_RCC_GetHCLKFreq()\n      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency\n         Note: If you use this function to configure the system clock; then there\n               is no need to call the 2 first functions listed above, since SystemCoreClock\n               variable is updated automatically.\n  */\n  uint32_t SystemCoreClock = 2000000;\n__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};\n__I uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32L0xx_System_Private_FunctionPrototypes\n  * @{\n  */\nstatic void SetSysClock(void);\n/**\n  * @}\n  */\n\n/** @addtogroup STM32L0xx_System_Private_Functions\n  * @{\n  */\n\n/**\n  * @brief  Setup the microcontroller system.\n  * @param  None\n  * @retval None\n  */\nvoid SystemInit (void)\n{\n/*!< Set MSION bit */\n  RCC->CR |= (uint32_t)0x00000100;\n\n  /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */\n  RCC->CFGR &= (uint32_t) 0x88FF400C;\n\n  /*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */\n  RCC->CR &= (uint32_t)0xFEF6FFF6;\n\n  /*!< Reset HSI48ON  bit */\n  RCC->CRRCR &= (uint32_t)0xFFFFFFFE;\n\n  /*!< Reset HSEBYP bit */\n  RCC->CR &= (uint32_t)0xFFFBFFFF;\n\n  /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */\n  RCC->CFGR &= (uint32_t)0xFF02FFFF;\n\n  /*!< Disable all interrupts */\n  RCC->CIER = 0x00000000;\n\n  /* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */\n  SetSysClock();\n\n\n  /* Configure the Vector Table location add offset address ------------------*/\n#ifdef VECT_TAB_SRAM\n  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */\n#else\n  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */\n#endif\n}\n\n/**\n  * @brief  Update SystemCoreClock according to Clock Register Values\n  *         The SystemCoreClock variable contains the core clock (HCLK), it can\n  *         be used by the user application to setup the SysTick timer or configure\n  *         other parameters.\n  *\n  * @note   Each time the core clock (HCLK) changes, this function must be called\n  *         to update SystemCoreClock variable value. Otherwise, any configuration\n  *         based on this variable will be incorrect.\n  *\n  * @note   - The system frequency computed by this function is not the real\n  *           frequency in the chip. It is calculated based on the predefined\n  *           constant and the selected clock source:\n  *\n  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI\n  *             value as defined by the MSI range.\n  *\n  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)\n  *\n  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)\n  *\n  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)\n  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.\n  *\n  *         (*) HSI_VALUE is a constant defined in stm32l0xx_hal.h file (default value\n  *             16 MHz) but the real value may vary depending on the variations\n  *             in voltage and temperature.\n  *\n  *         (**) HSE_VALUE is a constant defined in stm32l0xx_hal.h file (default value\n  *              8 MHz), user has to ensure that HSE_VALUE is same as the real\n  *              frequency of the crystal used. Otherwise, this function may\n  *              have wrong result.\n  *\n  *         - The result of this function could be not correct when using fractional\n  *           value for HSE crystal.\n  * @param  None\n  * @retval None\n  */\nvoid SystemCoreClockUpdate (void)\n{\n  uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;\n\n  /* Get SYSCLK source -------------------------------------------------------*/\n  tmp = RCC->CFGR & RCC_CFGR_SWS;\n\n  switch (tmp)\n  {\n    case 0x00:  /* MSI used as system clock */\n      SystemCoreClock = ((1 <<((RCC->ICSCR & RCC_ICSCR_MSIRANGE)>>13 ))* 64000);\n      break;\n    case 0x04:  /* HSI used as system clock */\n      SystemCoreClock = HSI_VALUE;\n      break;\n    case 0x08:  /* HSE used as system clock */\n      SystemCoreClock = HSE_VALUE;\n      break;\n    case 0x0C:  /* PLL used as system clock */\n      /* Get PLL clock source and multiplication factor ----------------------*/\n      pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;\n      plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;\n      pllmul = PLLMulTable[(pllmul >> 18)];\n      plldiv = (plldiv >> 22) + 1;\n\n      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;\n\n      if (pllsource == 0x00)\n      {\n        /* HSI oscillator clock selected as PLL clock entry */\n        SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);\n      }\n      else\n      {\n        /* HSE selected as PLL clock entry */\n        SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);\n      }\n      break;\n    default: /* MSI used as system clock */\n      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;\n      SystemCoreClock = (32768 * (1 << (msirange + 1)));\n      break;\n  }\n  /* Compute HCLK clock frequency --------------------------------------------*/\n  /* Get HCLK prescaler */\n  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];\n  /* HCLK clock frequency */\n  SystemCoreClock >>= tmp;\n}\n\n/**\n  * @brief  Configures the System clock frequency, AHB/APBx prescalers and Flash\n  *         settings.\n  * @note   This function should be called only once the RCC clock configuration\n  *         is reset to the default reset state (done in SystemInit() function).\n  * @param  None\n  * @retval None\n  *\n  * This file configures the system clock as follows:\n  *=============================================================================\n  *                         System Clock Configuration\n  *=============================================================================\n  *        System Clock source          | PLL(HSE)\n  *-----------------------------------------------------------------------------\n  *        SYSCLK                       | 32000000 Hz\n  *-----------------------------------------------------------------------------\n  *        HCLK                         | 32000000 Hz\n  *-----------------------------------------------------------------------------\n  *        AHB Prescaler                | 1\n  *-----------------------------------------------------------------------------\n  *        APB1 Prescaler               | 1\n  *-----------------------------------------------------------------------------\n  *        APB2 Prescaler               | 1\n  *-----------------------------------------------------------------------------\n  *        HSE Frequency                | 8000000 Hz\n  *-----------------------------------------------------------------------------\n  *        PLL DIV                      | 3\n  *-----------------------------------------------------------------------------\n  *        PLL MUL                      | 12\n  *-----------------------------------------------------------------------------\n  *        VDD                          | 3.3 V\n  *-----------------------------------------------------------------------------\n  *        Vcore                        | 1.8 V (Range 1)\n  *-----------------------------------------------------------------------------\n  *        Flash Latency                | 1 WS\n  *-----------------------------------------------------------------------------\n  *        SDIO clock (SDIOCLK)         | 48000000 Hz\n  *-----------------------------------------------------------------------------\n  *        Require 48MHz for USB clock  | Disabled\n  *-----------------------------------------------------------------------------\n  *=============================================================================\n  */\nstatic void SetSysClock(void)\n{\n  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;\n\n  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/\n  /* Enable HSE */\n  RCC->CR |= ((uint32_t)RCC_CR_HSEON);\n\n  /* Wait till HSE is ready and if Time out is reached exit */\n  do\n  {\n    HSEStatus = RCC->CR & RCC_CR_HSERDY;\n    StartUpCounter++;\n  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));\n\n  if ((RCC->CR & RCC_CR_HSERDY) != RESET)\n  {\n    HSEStatus = (uint32_t)0x01;\n  }\n  else\n  {\n    HSEStatus = (uint32_t)0x00;\n  }\n\n  if (HSEStatus == (uint32_t)0x01)\n  {\n    /* Enable 64-bit access */\n    //???FLASH->ACR |= FLASH_ACR_ACC64;\n\n    /* Enable Prefetch Buffer */\n    FLASH->ACR |= FLASH_ACR_PRFTEN;\n\n    /* Flash 1 wait state */\n    FLASH->ACR |= FLASH_ACR_LATENCY;\n\n    /* Power enable */\n    RCC->APB1ENR |= RCC_APB1ENR_PWREN;\n\n    /* Select the Voltage Range 1 (1.8 V) */\n    PWR->CR = PWR_CR_VOS_0;\n\n    /* Wait Until the Voltage Regulator is ready */\n    while((PWR->CSR & PWR_CSR_VOSF) != RESET)\n    {\n    }\n\n    /* HCLK = SYSCLK /1*/\n    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;\n\n    /* PCLK2 = HCLK /1*/\n    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\n\n    /* PCLK1 = HCLK /1*/\n    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;\n\n    /*  PLL configuration */\n    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL |\n                                        RCC_CFGR_PLLDIV));\n    //RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMUL12 | RCC_CFGR_PLLDIV3);\n    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMUL4 | RCC_CFGR_PLLDIV4);\n\n    /* Enable PLL */\n    RCC->CR |= RCC_CR_PLLON;\n\n    /* Wait till PLL is ready */\n    while((RCC->CR & RCC_CR_PLLRDY) == 0)\n    {\n    }\n\n    /* Select PLL as system clock source */\n    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\n    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;\n\n    /* Wait till PLL is used as system clock source */\n    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)\n    {\n    }\n  }\n  else\n  {\n    /* If HSE fails to start-up, the application will have wrong clock\n       configuration. User can add here some code to deal with this error */\n  }\n}\n\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "3rd_party/nucleo-l053r8/system_stm32l0xx.h",
    "content": "/**\n  ******************************************************************************\n  * @file    system_stm32l0xx.h\n  * @author  MCD Application Team\n  * @version V1.0.0RC1\n  * @date    15-April-2014\n  * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/** @addtogroup CMSIS\n  * @{\n  */\n\n/** @addtogroup stm32l0xx_system\n  * @{\n  */\n\n/**\n  * @brief Define to prevent recursive inclusion\n  */\n#ifndef __SYSTEM_STM32L0XX_H\n#define __SYSTEM_STM32L0XX_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/** @addtogroup STM32L0xx_System_Includes\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n\n/** @addtogroup STM32L1xx_System_Exported_types\n  * @{\n  */\n/* This variable is updated in three ways:\n * 1) by calling CMSIS function SystemCoreClockUpdate()\n * 2) by calling HAL API function HAL_RCC_GetSysClockFreq()\n * 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency\n *    Note: If you use this function to configure the system clock; then there\n *          is no need to call the 2 first functions listed above, since SystemCoreClock\n *          variable is updated automatically.\n */\nextern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32L0xx_System_Exported_Constants\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32L0xx_System_Exported_Macros\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32L0xx_System_Exported_Functions\n  * @{\n  */\n\nextern void SystemInit(void);\nextern void SystemCoreClockUpdate(void);\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /*__SYSTEM_STM32L0XX_H */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "FreeRTOS-comparison/CMakeLists.txt",
    "content": "cmake_minimum_required(VERSION 3.15)\n\n# User is responsible to set two mandatory options:\n# FREERTOS_CONFIG_FILE_DIRECTORY\n# FREERTOS_PORT\n#\n# User can choose which heap implementation to use (either the implementations\n# included with FreeRTOS [1..5] or a custom implementation ) by providing the\n# option FREERTOS_HEAP. If the option is not set, the cmake will default to\n# using heap_4.c.\n\n# Absolute path to FreeRTOS config file directory\nset(FREERTOS_CONFIG_FILE_DIRECTORY \"\" CACHE STRING \"Absolute path to the directory with FreeRTOSConfig.h\")\n\nif(NOT FREERTOS_CONFIG_FILE_DIRECTORY)\n    message(FATAL_ERROR \" FreeRTOSConfig.h file directory not specified. Please specify absolute path to it from top-level CMake file:\\n\"\n        \"  set(FREERTOS_CONFIG_FILE_DIRECTORY <absolute path to FreeRTOSConfig.h directory> CACHE STRING \\\"\\\")\\n\"\n        \" or from CMake command line option:\\n\"\n        \"  -DFREERTOS_CONFIG_FILE_DIRECTORY='/absolute_path/to/FreeRTOSConfig.h/directory'\")\nelseif(NOT EXISTS ${FREERTOS_CONFIG_FILE_DIRECTORY}/FreeRTOSConfig.h)\n    message(FATAL_ERROR \" FreeRTOSConfig.h file not found in the directory specified (${FREERTOS_CONFIG_FILE_DIRECTORY})\\n\"\n        \" Please specify absolute path to it from top-level CMake file:\\n\"\n        \"  set(FREERTOS_CONFIG_FILE_DIRECTORY <absolute path to FreeRTOSConfig.h directory> CACHE STRING \\\"\\\")\\n\"\n        \" or from CMake command line option:\\n\"\n        \"  -DFREERTOS_CONFIG_FILE_DIRECTORY='/absolute_path/to/FreeRTOSConfig.h/directory'\")\nendif()\n\n# Heap number or absolute path to custom heap implementation provided by user\nset(FREERTOS_HEAP \"4\" CACHE STRING \"FreeRTOS heap model number. 1 .. 5. Or absolute path to custom heap source file\")\n\n# FreeRTOS port option\nset(FREERTOS_PORT \"\" CACHE STRING \"FreeRTOS port name\")\n\nif(NOT FREERTOS_PORT)\n    message(FATAL_ERROR \" FREERTOS_PORT is not set. Please specify it from top-level CMake file (example):\\n\"\n        \"  set(FREERTOS_PORT GCC_ARM_CM4F CACHE STRING \\\"\\\")\\n\"\n        \" or from CMake command line option:\\n\"\n        \"  -DFREERTOS_PORT=GCC_ARM_CM4F\\n\"\n        \" \\n\"\n        \" Available port options:\\n\"\n        \" BCC_16BIT_DOS_FLSH186            - Compiller: BCC           Target: 16 bit DOS Flsh186\\n\"\n        \" BCC_16BIT_DOS_PC                 - Compiller: BCC           Target: 16 bit DOS PC\\n\"\n        \" CCS_ARM_CM3                      - Compiller: CCS           Target: ARM Cortex-M3\\n\"\n        \" CCS_ARM_CM4F                     - Compiller: CCS           Target: ARM Cortex-M4 with FPU\\n\"\n        \" CCS_ARM_CR4                      - Compiller: CCS           Target: ARM Cortex-R4\\n\"\n        \" CCS_MSP430X                      - Compiller: CCS           Target: MSP430X\\n\"\n        \" CODEWARRIOR_COLDFIRE_V1          - Compiller: CoreWarrior   Target: ColdFire V1\\n\"\n        \" CODEWARRIOR_COLDFIRE_V2          - Compiller: CoreWarrior   Target: ColdFire V2\\n\"\n        \" CODEWARRIOR_HCS12                - Compiller: CoreWarrior   Target: HCS12\\n\"\n        \" GCC_ARM_CA9                      - Compiller: GCC           Target: ARM Cortex-A9\\n\"\n        \" GCC_ARM_CA53_64_BIT              - Compiller: GCC           Target: ARM Cortex-A53 64 bit\\n\"\n        \" GCC_ARM_CA53_64_BIT_SRE          - Compiller: GCC           Target: ARM Cortex-A53 64 bit SRE\\n\"\n        \" GCC_ARM_CM0                      - Compiller: GCC           Target: ARM Cortex-M0\\n\"\n        \" GCC_ARM_CM3                      - Compiller: GCC           Target: ARM Cortex-M3\\n\"\n        \" GCC_ARM_CM3_MPU                  - Compiller: GCC           Target: ARM Cortex-M3 with MPU\\n\"\n        \" GCC_ARM_CM4_MPU                  - Compiller: GCC           Target: ARM Cortex-M4 with MPU\\n\"\n        \" GCC_ARM_CM4F                     - Compiller: GCC           Target: ARM Cortex-M4 with FPU\\n\"\n        \" GCC_ARM_CM7                      - Compiller: GCC           Target: ARM Cortex-M7\\n\"\n        \" GCC_ARM_CM23_NONSECURE           - Compiller: GCC           Target: ARM Cortex-M23 non-secure\\n\"\n        \" GCC_ARM_CM23_SECURE              - Compiller: GCC           Target: ARM Cortex-M23 secure\\n\"\n        \" GCC_ARM_CM23_NTZ_NONSECURE       - Compiller: GCC           Target: ARM Cortex-M23 non-trustzone non-secure\\n\"\n        \" GCC_ARM_CM33_NONSECURE           - Compiller: GCC           Target: ARM Cortex-M33 non-secure\\n\"\n        \" GCC_ARM_CM33_SECURE              - Compiller: GCC           Target: ARM Cortex-M33 secure\\n\"\n        \" GCC_ARM_CM33_NTZ_NONSECURE       - Compiller: GCC           Target: ARM Cortex-M33 non-trustzone non-secure\\n\"\n        \" GCC_ARM_CM33_TFM                 - Compiller: GCC           Target: ARM Cortex-M33 non-secure for TF-M\\n\"\n        \" GCC_ARM_CM55_NONSECURE           - Compiller: GCC           Target: ARM Cortex-M55 non-secure\\n\"\n        \" GCC_ARM_CM55_SECURE              - Compiller: GCC           Target: ARM Cortex-M55 secure\\n\"\n        \" GCC_ARM_CM55_NTZ_NONSECURE       - Compiller: GCC           Target: ARM Cortex-M55 non-trustzone non-secure\\n\"\n        \" GCC_ARM_CM55_TFM                 - Compiller: GCC           Target: ARM Cortex-M55 non-secure for TF-M\\n\"\n        \" GCC_ARM_CM85_NONSECURE           - Compiller: GCC           Target: ARM Cortex-M85 non-secure\\n\"\n        \" GCC_ARM_CM85_SECURE              - Compiller: GCC           Target: ARM Cortex-M85 secure\\n\"\n        \" GCC_ARM_CM85_NTZ_NONSECURE       - Compiller: GCC           Target: ARM Cortex-M85 non-trustzone non-secure\\n\"\n        \" GCC_ARM_CM85_TFM                 - Compiller: GCC           Target: ARM Cortex-M85 non-secure for TF-M\\n\"\n        \" GCC_ARM_CR5                      - Compiller: GCC           Target: ARM Cortex-R5\\n\"\n        \" GCC_ARM_CRX_NOGIC                - Compiller: GCC           Target: ARM Cortex-Rx no GIC\\n\"\n        \" GCC_ARM7_AT91FR40008             - Compiller: GCC           Target: ARM7 Atmel AT91R40008\\n\"\n        \" GCC_ARM7_AT91SAM7S               - Compiller: GCC           Target: ARM7 Atmel AT91SAM7S\\n\"\n        \" GCC_ARM7_LPC2000                 - Compiller: GCC           Target: ARM7 LPC2000\\n\"\n        \" GCC_ARM7_LPC23XX                 - Compiller: GCC           Target: ARM7 LPC23xx\\n\"\n        \" GCC_ATMEGA323                    - Compiller: GCC           Target: ATMega323\\n\"\n        \" GCC_AVR32_UC3                    - Compiller: GCC           Target: AVR32 UC3\\n\"\n        \" GCC_COLDFIRE_V2                  - Compiller: GCC           Target: ColdFire V2\\n\"\n        \" GCC_CORTUS_APS3                  - Compiller: GCC           Target: CORTUS APS3\\n\"\n        \" GCC_H8S2329                      - Compiller: GCC           Target: H8S2329\\n\"\n        \" GCC_HCS12                        - Compiller: GCC           Target: HCS12\\n\"\n        \" GCC_IA32_FLAT                    - Compiller: GCC           Target: IA32 flat\\n\"\n        \" GCC_MICROBLAZE                   - Compiller: GCC           Target: MicroBlaze\\n\"\n        \" GCC_MICROBLAZE_V8                - Compiller: GCC           Target: MicroBlaze V8\\n\"\n        \" GCC_MICROBLAZE_V9                - Compiller: GCC           Target: MicroBlaze V9\\n\"\n        \" GCC_MSP430F449                   - Compiller: GCC           Target: MSP430F449\\n\"\n        \" GCC_NIOSII                       - Compiller: GCC           Target: NiosII\\n\"\n        \" GCC_PPC405_XILINX                - Compiller: GCC           Target: Xilinx PPC405\\n\"\n        \" GCC_PPC440_XILINX                - Compiller: GCC           Target: Xilinx PPC440\\n\"\n        \" GCC_RISC_V                       - Compiller: GCC           Target: RISC-V\\n\"\n        \" GCC_RISC_V_PULPINO_VEGA_RV32M1RM - Compiller: GCC           Target: RISC-V Pulpino Vega RV32M1RM\\n\"\n        \" GCC_RL78                         - Compiller: GCC           Target: Renesas RL78\\n\"\n        \" GCC_RX100                        - Compiller: GCC           Target: Renesas RX100\\n\"\n        \" GCC_RX200                        - Compiller: GCC           Target: Renesas RX200\\n\"\n        \" GCC_RX600                        - Compiller: GCC           Target: Renesas RX600\\n\"\n        \" GCC_RX600_V2                     - Compiller: GCC           Target: Renesas RX600 v2\\n\"\n        \" GCC_RX700_V3_DPFPU               - Compiller: GCC           Target: Renesas RX700 v3 with DPFPU\\n\"\n        \" GCC_STR75X                       - Compiller: GCC           Target: STR75x\\n\"\n        \" GCC_TRICORE_1782                 - Compiller: GCC           Target: TriCore 1782\\n\"\n        \" GCC_ARC_EM_HS                    - Compiller: GCC           Target: DesignWare ARC EM HS\\n\"\n        \" GCC_ARC_V1                       - Compiller: GCC           Target: DesignWare ARC v1\\n\"\n        \" GCC_ATMEGA                       - Compiller: GCC           Target: ATmega\\n\"\n        \" GCC_POSIX                        - Compiller: GCC           Target: Posix\\n\"\n        \" GCC_RP2040                       - Compiller: GCC           Target: RP2040 ARM Cortex-M0+\\n\"\n        \" GCC_XTENSA_ESP32                 - Compiller: GCC           Target: Xtensa ESP32\\n\"\n        \" GCC_AVRDX                        - Compiller: GCC           Target: AVRDx\\n\"\n        \" GCC_AVR_MEGA0                    - Compiller: GCC           Target: AVR Mega0\\n\"\n        \" IAR_78K0K                        - Compiller: IAR           Target: Renesas 78K0K\\n\"\n        \" IAR_ARM_CA5_NOGIC                - Compiller: IAR           Target: ARM Cortex-A5 no GIC\\n\"\n        \" IAR_ARM_CA9                      - Compiller: IAR           Target: ARM Cortex-A9\\n\"\n        \" IAR_ARM_CM0                      - Compiller: IAR           Target: ARM Cortex-M0\\n\"\n        \" IAR_ARM_CM3                      - Compiller: IAR           Target: ARM Cortex-M3\\n\"\n        \" IAR_ARM_CM4F                     - Compiller: IAR           Target: ARM Cortex-M4 with FPU\\n\"\n        \" IAR_ARM_CM4F_MPU                 - Compiller: IAR           Target: ARM Cortex-M4 with FPU and MPU\\n\"\n        \" IAR_ARM_CM7                      - Compiller: IAR           Target: ARM Cortex-M7\\n\"\n        \" IAR_ARM_CM23_NONSECURE           - Compiller: IAR           Target: ARM Cortex-M23 non-secure\\n\"\n        \" IAR_ARM_CM23_SECURE              - Compiller: IAR           Target: ARM Cortex-M23 secure\\n\"\n        \" IAR_ARM_CM23_NTZ_NONSECURE       - Compiller: IAR           Target: ARM Cortex-M23 non-trustzone non-secure\\n\"\n        \" IAR_ARM_CM33_NONSECURE           - Compiller: IAR           Target: ARM Cortex-M33 non-secure\\n\"\n        \" IAR_ARM_CM33_SECURE              - Compiller: IAR           Target: ARM Cortex-M33 secure\\n\"\n        \" IAR_ARM_CM33_NTZ_NONSECURE       - Compiller: IAR           Target: ARM Cortex-M33 non-trustzone non-secure\\n\"\n        \" IAR_ARM_CM55_NONSECURE           - Compiller: IAR           Target: ARM Cortex-M55 non-secure\\n\"\n        \" IAR_ARM_CM55_SECURE              - Compiller: IAR           Target: ARM Cortex-M55 secure\\n\"\n        \" IAR_ARM_CM55_NTZ_NONSECURE       - Compiller: IAR           Target: ARM Cortex-M55 non-trustzone non-secure\\n\"\n        \" IAR_ARM_CM85_NONSECURE           - Compiller: IAR           Target: ARM Cortex-M85 non-secure\\n\"\n        \" IAR_ARM_CM85_SECURE              - Compiller: IAR           Target: ARM Cortex-M85 secure\\n\"\n        \" IAR_ARM_CM85_NTZ_NONSECURE       - Compiller: IAR           Target: ARM Cortex-M85 non-trustzone non-secure\\n\"\n        \" IAR_ARM_CRX_NOGIC                - Compiller: IAR           Target: ARM Cortex-Rx no GIC\\n\"\n        \" IAR_ATMEGA323                    - Compiller: IAR           Target: ATMega323\\n\"\n        \" IAR_ATMEL_SAM7S64                - Compiller: IAR           Target: Atmel SAM7S64\\n\"\n        \" IAR_ATMEL_SAM9XE                 - Compiller: IAR           Target: Atmel SAM9XE\\n\"\n        \" IAR_AVR_AVRDX                    - Compiller: IAR           Target: AVRDx\\n\"\n        \" IAR_AVR_MEGA0                    - Compiller: IAR           Target: AVR Mega0\\n\"\n        \" IAR_AVR32_UC3                    - Compiller: IAR           Target: AVR32 UC3\\n\"\n        \" IAR_LPC2000                      - Compiller: IAR           Target: LPC2000\\n\"\n        \" IAR_MSP430                       - Compiller: IAR           Target: MSP430\\n\"\n        \" IAR_MSP430X                      - Compiller: IAR           Target: MSP430X\\n\"\n        \" IAR_RISC_V                       - Compiller: IAR           Target: RISC-V\\n\"\n        \" IAR_RL78                         - Compiller: IAR           Target: Renesas RL78\\n\"\n        \" IAR_RX100                        - Compiller: IAR           Target: Renesas RX100\\n\"\n        \" IAR_RX600                        - Compiller: IAR           Target: Renesas RX600\\n\"\n        \" IAR_RX700_V3_DPFPU               - Compiller: IAR           Target: Renesas RX700 v3 with DPFPU\\n\"\n        \" IAR_RX_V2                        - Compiller: IAR           Target: Renesas RX v2\\n\"\n        \" IAR_STR71X                       - Compiller: IAR           Target: STR71x\\n\"\n        \" IAR_STR75X                       - Compiller: IAR           Target: STR75x\\n\"\n        \" IAR_STR91X                       - Compiller: IAR           Target: STR91x\\n\"\n        \" IAR_V850ES_FX3                   - Compiller: IAR           Target: Renesas V850ES/Fx3\\n\"\n        \" IAR_V850ES_HX3                   - Compiller: IAR           Target: Renesas V850ES/Hx3\\n\"\n        \" MIKROC_ARM_CM4F                  - Compiller: MikroC        Target: ARM Cortex-M4 with FPU\\n\"\n        \" MPLAB_PIC18F                     - Compiller: MPLAB         Target: PIC18F\\n\"\n        \" MPLAB_PIC24                      - Compiller: MPLAB         Target: PIC24\\n\"\n        \" MPLAB_PIC32MEC14XX               - Compiller: MPLAB         Target: PIC32MEC14xx\\n\"\n        \" MPLAB_PIC32MX                    - Compiller: MPLAB         Target: PIC32MX\\n\"\n        \" MPLAB_PIC32MZ                    - Compiller: MPLAB         Target: PIC32MZ\\n\"\n        \" MSVC_MINGW                       - Compiller: MSVC or MinGW Target: x86\\n\"\n        \" OWATCOM_16BIT_DOS_FLSH186        - Compiller: Open Watcom   Target: 16 bit DOS Flsh186\\n\"\n        \" OWATCOM_16BIT_DOS_PC             - Compiller: Open Watcom   Target: 16 bit DOS PC\\n\"\n        \" PARADIGM_TERN_EE_LARGE           - Compiller: Paradigm      Target: Tern EE large\\n\"\n        \" PARADIGM_TERN_EE_SMALL           - Compiller: Paradigm      Target: Tern EE small\\n\"\n        \" RENESAS_RX100                    - Compiller: Renesas       Target: RX100\\n\"\n        \" RENESAS_RX200                    - Compiller: Renesas       Target: RX200\\n\"\n        \" RENESAS_RX600                    - Compiller: Renesas       Target: RX600\\n\"\n        \" RENESAS_RX600_V2                 - Compiller: Renesas       Target: RX600 v2\\n\"\n        \" RENESAS_RX700_V3_DPFPU           - Compiller: Renesas       Target: RX700 v3 with DPFPU\\n\"\n        \" RENESAS_SH2A_FPU                 - Compiller: Renesas       Target: SH2A with FPU\\n\"\n        \" ROWLEY_MSP430F449                - Compiller: Rowley        Target: MSP430F449\\n\"\n        \" RVDS_ARM_CA9                     - Compiller: RVDS          Target: ARM Cortex-A9\\n\"\n        \" RVDS_ARM_CM0                     - Compiller: RVDS          Target: ARM Cortex-M0\\n\"\n        \" RVDS_ARM_CM3                     - Compiller: RVDS          Target: ARM Cortex-M3\\n\"\n        \" RVDS_ARM_CM4_MPU                 - Compiller: RVDS          Target: ARM Cortex-M4 with MPU\\n\"\n        \" RVDS_ARM_CM4F                    - Compiller: RVDS          Target: ARM Cortex-M4 with FPU\\n\"\n        \" RVDS_ARM_CM7                     - Compiller: RVDS          Target: ARM Cortex-M7\\n\"\n        \" RVDS_ARM7_LPC21XX                - Compiller: RVDS          Target: ARM7 LPC21xx\\n\"\n        \" SDCC_CYGNAL                      - Compiller: SDCC          Target: Cygnal\\n\"\n        \" SOFTUNE_MB91460                  - Compiller: Softune       Target: MB91460\\n\"\n        \" SOFTUNE_MB96340                  - Compiller: Softune       Target: MB96340\\n\"\n        \" TASKING_ARM_CM4F                 - Compiller: Tasking       Target: ARM Cortex-M4 with FPU\\n\"\n        \" CDK_THEAD_CK802                  - Compiller: CDK           Target: T-head CK802\\n\"\n        \" XCC_XTENSA                       - Compiller: XCC           Target: Xtensa\\n\"\n        \" WIZC_PIC18                       - Compiller: WizC          Target: PIC18\")\nendif()\n\nadd_subdirectory(portable)\n\nadd_library(freertos_kernel STATIC\n    croutine.c\n    event_groups.c\n    list.c\n    queue.c\n    stream_buffer.c\n    tasks.c\n    timers.c\n\n    # If FREERTOS_HEAP is digit between 1 .. 5 - it is heap number, otherwise - it is path to custom heap source file\n    $<IF:$<BOOL:$<FILTER:${FREERTOS_HEAP},EXCLUDE,^[1-5]$>>,${FREERTOS_HEAP},portable/MemMang/heap_${FREERTOS_HEAP}.c>\n)\n\ntarget_include_directories(freertos_kernel\n    PUBLIC\n        include\n        ${FREERTOS_CONFIG_FILE_DIRECTORY}\n)\n\ntarget_link_libraries(freertos_kernel freertos_kernel_port)\n"
  },
  {
    "path": "FreeRTOS-comparison/GitHub-FreeRTOS-Kernel-Home.url",
    "content": "[{000214A0-0000-0000-C000-000000000046}]\nProp3=19,2\n[InternetShortcut]\nURL=https://github.com/FreeRTOS/FreeRTOS-Kernel\nIconIndex=0\nIDList=\nHotKey=0\n\n"
  },
  {
    "path": "FreeRTOS-comparison/History.txt",
    "content": "Documentation and download available at https://www.FreeRTOS.org/\n\nChanges between FreeRTOS V10.5.0 and FreeRTOS V10.5.1 released November 16 2022\n\t\n\t+ Updating the version in the manifest.yml file to be accurate. \n\nChanges between FreeRTOS V10.4.6 and FreeRTOS V10.5.0 released September 16 2022\n\n\t+ ARMv7-M and ARMv8-M MPU ports: It was possible for a third party that\n\t  already independently gained the ability to execute injected code to\n\t  read from or write to arbitrary addresses by passing a negative argument\n\t  as the xIndex parameter to pvTaskGetThreadLocalStoragePointer() or\n\t  vTaskSetThreadLocalStoragePointer respectively. A check has been added to\n\t  ensure that passing a negative argument as the xIndex parameter does not\n\t  cause arbitrary read or write.\n\t  We thank Certibit Consulting, LLC for reporting this issue.\n\t+ ARMv7-M and ARMv8-M MPU ports: It was possible for an unprivileged task\n\t  to invoke any function with privilege by passing it as a parameter to\n\t  MPU_xTaskCreate, MPU_xTaskCreateStatic, MPU_xTimerCreate,\n\t  MPU_xTimerCreateStatic, or MPU_xTimerPendFunctionCall. MPU_xTaskCreate\n\t  and MPU_xTaskCreateStatic have been updated to only allow creation of\n\t  unprivileged tasks. MPU_xTimerCreate, MPU_xTimerCreateStatic and\n\t  MPU_xTimerPendFunctionCall APIs have been removed.\n\t  We thank Huazhong University of Science and Technology for reporting\n\t  this issue.\n\t+ ARMv7-M and ARMv8-M MPU ports: It was possible for a third party that\n\t  already independently gained the ability to execute injected code to\n\t  achieve further privilege escalation by branching directly inside a\n\t  FreeRTOS MPU API wrapper function with a manually crafted stack frame.\n\t  The local stack variable `xRunningPrivileged` has been removed so that\n\t  a manually crafted stack frame cannot be used for privilege escalation\n\t  by branching directly inside a FreeRTOS MPU API wrapper.\n\t  We thank Certibit Consulting, LLC, Huazhong University of Science and\n\t  Technology and the SecLab team at Northeastern University for reporting\n\t  this issue.\n\t+ ARMv7-M MPU ports: It was possible to configure overlapping memory\n\t  protection unit (MPU) regions such that an unprivileged task could access\n\t  privileged data. The kernel now uses highest numbered MPU regions for\n\t  kernel protections to prevent such MPU configurations.\n\t  We thank the SecLab team at Northeastern University for reporting this\n\t  issue.\n\t+ Add support for ARM Cortex-M55.\n\t+ Add support for ARM Cortex-M85. Contributed by @gbrtth.\n\t+ Add vectored mode interrupt support to the RISC-V port.\n\t+ Add support for RV32E extension (Embedded Profile) in RISC-V GCC port.\n\t  Contributed by @Limoto.\n\t+ Heap improvements:\n\t  - Add a check to heap_2 to track if a memory block is allocated to\n\t    the application or not. The MSB of the size field is used for this\n\t    purpose. The same check already exists in heap_4 and heap_5. This\n\t    check prevents double free errors.\n\t  - Add a new flag configHEAP_CLEAR_MEMORY_ON_FREE to heap_2, heap_4\n\t    and heap_5. If the flag is set in FreeRTOSConfig.h then memory freed using\n\t    vPortFree() is automatically cleared to zero.\n\t  - Add a new API pvPortCalloc to heap_2, heap_4 and heap_5 which has the same\n\t    signature as the standard library calloc function.\n\t  - Update the pointer types to portPOINTER_SIZE_TYPE. Contributed by\n\t    @Octaviarius.\n\t+ Add the ability to override send and receive completed callbacks for each\n\t  instance of a stream buffer or message buffer. Earlier there could be\n\t  one send and one receive callback for all instances of stream and message\n\t  buffers. Having separate callbacks per instance allows different message\n\t  and stream buffers to be used differently - for example, some for inter core\n\t  communication and others for same core communication.\n\t  The feature can be controlled by setting  the configuration option\n\t  configUSE_SB_COMPLETED_CALLBACK in FreeRTOSConfig.h. When the option is set to 1,\n\t  APIs xStreamBufferCreateWithCallback() or xStreamBufferCreateStaticWithCallback()\n\t  (and likewise APIs for message buffer) can be used to create a stream buffer \n\t  or message buffer instance with application provided callback overrides. When\n\t  the option is set to 0, then the default callbacks as defined by\n\t  sbSEND_COMPLETED() and sbRECEIVE_COMPLETED() macros are invoked. To maintain \n\t  backwards compatibility, configUSE_SB_COMPLETED_CALLBACK defaults to 0. The \n\t  functionality is currently not supported for MPU enabled ports.\n\t+ Generalize the FreeRTOS's Thread Local Storage (TLS) support so that it\n\t  is not tied to newlib and can be used with other c-runtime libraries also.\n\t  The default behavior for newlib support is kept same for backward\n\t  compatibility.\n\t+ Add support to build and link FreeRTOS using CMake build system. Contributed\n\t  by @yhsb2k.\n\t+ Add support to generate Software Bill of Materials (SBOM) for every release.\n\t+ Add support for 16 MPU regions to the GCC Cortex-M33 ports.\n\t+ Add ARM Cortex-M7 r0p0/r0p1 Errata 837070 workaround to ARM CM4 MPU ports.\n\t  The application writer needs to define configENABLE_ERRATA_837070_WORKAROUND\n\t  when using CM4 MPU ports on a Cortex-M7 r0p0/r0p1 core.\n\t+ Add configSYSTICK_CLOCK_HZ to Cortex-M0 ports. This is needed to support\n\t  the case when the SysTick timer is not clocked from the same source as the CPU.\n\t+ Add hardware stack protection support to MicroBlazeV9 port. This ensures that\n\t  the CPU immediately raises Stack Protection Violation exception as soon as any\n\t  task violates its stack limits. Contributed by @uecasm.\n\t+ Introduce the configUSE_MINI_LIST_ITEM configuration option. When this\n\t  option is set to 1, ListItem_t and MiniLitItem_t remain separate types.\n\t  However, when configUSE_MINI_LIST_ITEM == 0, MiniLitItem_t and ListItem_t\n\t  are both typedefs of the same struct xLIST_ITEM. This addresses some issues\n\t  observed when strict-aliasing and link time optimization are enabled.\n\t  To maintain backwards compatibility, configUSE_MINI_LIST_ITEM defaults to 1.\n\t+ Simplify prvInitialiseNewTask to memset newly allocated TCB structures\n\t  to zero, and remove code that set individual structure members to zero.\n\t+ Add prototype for prvPortYieldFromISR to the POSIX port so that it builds\n\t  without any warning with -Wmissing-prototypes compiler option.\n\t+ Add top of stack and end of stack to the task info report obtained using\n\t  vTaskGetInfo(). Contributed by @shreyasbharath.\n\t+ Add a cap to the cRxLock and cTxLock members of the queue data structure.\n\t  These locks count the number items received and sent to the queue while\n\t  the queue was locked. These are later used to unblock tasks waiting on\n\t  the queue when the queue is unlocked. This PR caps the values of the\n\t  cRxLock and cTxLock to the number of tasks in the system because we cannot\n\t  unblock more tasks than there are in the system. Note that the same assert\n\t  could still be triggered is the application creates more than 127 tasks.\n\t+ Changed uxAutoReload parameter in timer functions to xAutoReload.  The\n\t  type is now BaseType_t.  This matches the type of pdTRUE and pdFALSE.\n\t  The new function xTimerGetAutoReload() provides the auto-reload state as\n\t  a BaseType_t.  The legacy function uxTimerGetAutoReload is retained with the\n\t  original UBaseType_t return value.\n\t+ Fix support for user implementations of tickless idle that call\n\t  vTaskStepTick() with xExpectedIdleTime ticks to step. The new code\n\t  ensures xTickCount reaches xNextTaskUnblockTime inside xTaskIncrementTick()\n\t  instead of inside vTaskStepTick(). This fixes the typical case where a task\n\t  wakes up one tick late and a rare case assertion failure when xTickCount\\\n\t  rolls over. Contributed by @jefftenney.\n\t+ Fix deadlock in event groups when pvPortMalloc and vPortFree functions\n\t  are protected with a mutex. Contributed by @clemenskresser.\n\t+ Fix a warning in tasks.c when compiled with -Wduplicated-branches\n\t  GCC option. Contributed by @pierrenoel-bouteville-act.\n\t+ Fix compilation error in tasks.c when configSUPPORT_DYNAMIC_ALLOCATION\n\t  is set to zero. Contributed by @rdpoor.\n\t+ Fix prvWriteMessageToBuffer() function in stream_buffer.c so that it correctly\n\t  copies length on big endian platforms too.\n\t+ Remove the need for  INCLUDE_vTaskSuspend to be set to 1\n\t  when configUSE_TICKLESS_IDLE is enabled. Contributed by @pramithkv.\n\t+ Update the RL78 IAR port to the latest version of IAR which uses the\n\t  industry standard ELF format as opposed to earlier UBROF object format.\n\t  Contributed by @felipe-iar.\n\t+ Add tick type is atomic flag when tick count is 16-bit to PIC24 port. This\n\t  allows the PIC24 family of 16 bit processors to read the tick count without\n\t  a critical section when the tick count is also 16 bits.\n\t+ Fix offset-out-of-range errors for GCC CM3/CM4 mpu ports when\n\t  Link Time Optimization is enabled. Contributed by @niniemann.\n\t+ Remove #error when RISC-V port is compiled on a 64-bit RISC-V platform.\n\t  Contributed by @cmdrf.\n\t+ Fix ullPortInterruptNesting alignment in Cortex-A53 port so that it is\n\t  8-byte aligned. This fixes the unaligned access exception. Contributed\n\t  by @Atomar25.\n\t+ Fix  Interrupt Handler Register Function and Exception Process in NiosII\n\t  Port. Contributed by @ghost.\n\t+ Change FreeRTOS IRQ Handler for Cortex-A53 SRE port to store and restore\n\t  interrupt acknowledge register. This ensures that the SRE port behavior\n\t  matches the Memory Mapped IO port. Contributed by @sviaunxp.\n\t+ Update the uncrustify config file to match the version of the uncrustify\n\t  used in the CI Action. Also, pin the version of uncrustify in CI. Contributed\n\t  by @swaldhoer.\n\nChanges between FreeRTOS V10.4.5 and FreeRTOS V10.4.6 released November 12 2021\n\n\t+ ARMv7-M and ARMv8-M MPU ports – prevent non-kernel code from calling the\n\t  internal functions xPortRaisePrivilege and vPortResetPrivilege by changing\n\t  them to macros.\n\t+ Introduce a new config configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS which\n\t  enables developers to prevent critical sections from unprivileged tasks.\n\t  It defaults to 1 for backward compatibility. Application should set it to\n\t  0 to disable critical sections from unprivileged tasks.\n\nChanges between FreeRTOS V10.4.4 and FreeRTOS V10.4.5 released September 10 2021\n\n\tSee https://www.FreeRTOS.org/FreeRTOS-V10.4.5.html\n\n\t+ Introduce configRUN_TIME_COUNTER_TYPE which enables developers to define\n\t  the type used to hold run time statistic counters. Defaults to uint32_t\n\t  for backward compatibility. #define configRUN_TIME_COUNTER_TYPE to a type\n\t  (for example, uint64_t) in FreeRTOSConfig.h to override the default.\n\t+ Introduce ulTaskGetIdleRunTimePercent() to complement the pre-existing\n\t  ulTaskGetIdleRunTimeCounter(). Whereas the pre-existing function returns\n\t  the raw run time counter value, the new function returns the percentage of\n\t  the entire run time consumed by the idle task. Note the amount of idle\n\t  time is only a good measure of the slack time in a system if there are no\n\t  other tasks executing at the idle priority, tickless idle is not used, and\n\t  configIDLE_SHOULD_YIELD is set to 0.\n\t+ ARMv8-M secure-side port:  Tasks that call secure functions from the\n\t  non-secure side of an ARMv8-M MCU (ARM Cortex-M23 and Cortex-M33) have two\n\t  contexts - one on the non-secure side and one on the secure-side. Previous\n\t  versions of the FreeRTOS ARMv8-M secure-side ports allocated the structures\n\t  that reference secure-side contexts at run time.  Now the structures are\n\t  allocated statically at compile time.  The change necessitates the\n\t  introduction of the secureconfigMAX_SECURE_CONTEXTS configuration constant,\n\t  which sets the number of statically allocated secure contexts.\n\t  secureconfigMAX_SECURE_CONTEXTS defaults to 8 if left undefined.\n\t  Applications that only use FreeRTOS code on the non-secure side, such as\n\t  those running third-party code on the secure side, are not affected by\n\t  this change.\n\nChanges between FreeRTOS V10.4.3 and FreeRTOS V10.4.4 released May 28 2021\n\t+ Minor performance improvements to xTaskIncrementTick() achieved by providing\n\t  macro versions of uxListRemove() and vListInsertEnd().\n\t+ Minor refactor of timers.c that obsoletes the need for the\n\t  tmrCOMMAND_START_DONT_TRACE macro and removes the need for timers.c to\n\t  post to its own event queue.  A consequence of this change is that auto-\n\t  reload timers that miss their intended next execution time will execute\n\t  again immediately rather than executing again the next time the command\n\t  queue is processed.  (thanks Jeff Tenney).\n\t+ Fix a race condition in the message buffer implementation.  The\n\t  underlying cause was that length and data bytes are written and read as\n\t  two distinct operations, which both modify the size of the buffer. If a\n\t  context switch occurs after adding or removing the length bytes, but\n\t  before adding or removing the data bytes, then another task may observe\n\t  the message buffer in an invalid state.\n\t+ The xTaskCreate() and xTaskCreateStatic() functions accept a task priority\n\t  as an input parameter.  The priority has always been silently capped to\n\t  (configMAX_PRIORITIES - 1) should it be set to a value above that priority.\n\t  Now values above that priority will also trigger a configASSERT() failure.\n\t+ Replace configASSERT( pcQueueName ) in vQueueAddToRegistry with a NULL\n\t  pointer check.\n\t+ Introduce the configSTACK_ALLOCATION_FROM_SEPARATE_HEAP configuration\n\t  constant that enables the stack allocated to tasks to come from a heap other\n\t  than the heap used by other memory allocations.  This enables stacks to be\n\t  placed within special regions, such as fast tightly coupled memory.\n\t+ If there is an attempt to add the same queue or semaphore handle to the\n\t  queue registry more than once then prior versions would create two separate\n\t  entries.  Now if this is done the first entry is overwritten rather than\n\t  duplicated.\n\t+ Update the ESP32 port and TF-M (Trusted Firmware M)code to the latest from\n\t  their respective repositories.\n\t+ Correct a build error in the POSIX port.\n\t+ Additional minor formatting updates, including replacing tabs with spaces\n\t  in more files.\n\t+ Other minor updates include adding additional configASSERT() checks and\n\t  correcting and improving code comments.\n\t+ Go look at the smp branch to see the progress towards the Symetric\n\t  Multiprocessing Kernel. https://github.com/FreeRTOS/FreeRTOS-Kernel/tree/smp\n\nChanges between FreeRTOS V10.4.2 and FreeRTOS V10.4.3 released December 14 2020\n\n\tV10.4.3 is included in the 202012.00 LTS release.  Learn more at https:/freertos.org/lts-libraries.html\n\n\tSee https://www.FreeRTOS.org/FreeRTOS-V10.4.x.html\n\n\t+ Changes to improve robustness and consistency for buffer allocation in\n\t  the heap, queue and stream buffer.\n\t+ The following functions can no longer be called from unprivileged code.\n\t  - xTaskCreateRestricted\n\t  - xTaskCreateRestrictedStatic\n\t  - vTaskAllocateMPURegions\n\n\nChanges between FreeRTOS V10.4.1 and FreeRTOS V10.4.2 released November 10 2020\n\n\tSee https://www.FreeRTOS.org/FreeRTOS-V10.4.x.html\n\n\t+ Fix an issue in the ARMv8-M ports that caused BASEPRI to be masked\n\t  between the first task starting to execute and that task making\n\t  a FreeRTOS API call.\n\t+ Introduced xTaskDelayUntil(), which is functionally equivalent to\n\t  vTaskDelayUntil(), with the addition of returning a value to\n\t  indicating whether or not the function placed the calling task into\n\t  the Blocked state or not.\n\t+ Update WolfSSL to 4.5.0 and add the FIPS ready demo.\n\t+ Add support for ESP IDF 4.2 to ThirdParty Xtensa port.\n\t+ Re-introduce uxTopUsedPriority to support OpenOCD debugging.\n\t+ Convert most dependent libraries in FreeRTOS/FreeRTOS to submodules.\n\t+ Various general maintenance and improvements to MISRA compliance.\n\n\nChanges between FreeRTOS V10.4.0 and FreeRTOS V10.4.1 released September 17 2020\n\n\tSee https://www.FreeRTOS.org/FreeRTOS-V10.4.x.html\n\n\t+ Fixed an incorrectly named parameter that prevented the\n\t  ulTaskNotifyTakeIndexed macro compiling, and the name space clash in the\n\t  test code that prevented this error causing test failures.\n\n\nChanges between FreeRTOS V10.3.1 and FreeRTOS V10.4.0 released September 10 2020\n\n\tSee https://www.FreeRTOS.org/FreeRTOS-V10.4.x.html\n\n\tMajor enhancements:\n\n\t+ Task notifications:  Prior to FreeRTOS V10.4.0 each created task had a\n\t  single direct to task notification.  From FreeRTOS V10.4.0 each task has\n\t  an array of notifications.  The direct to task notification API has been\n\t  extended with API functions postfixed with \"Indexed\" to enable the API to\n\t  operate on a task notification at any array index.  See\n\t  https://www.freertos.org/RTOS-task-notifications.html for more information.\n\t+ Kernel ports that support memory protection units (MPUs): The ARMv7-M and\n\t  ARMv8-M MPU ports now support a privilege access only heap. The ARMv7-M\n\t  MPU ports now support devices that have 16 MPU regions, have the ability\n\t  to override default memory attributes for privileged code and data\n\t  regions, and have the ability to place the FreeRTOS kernel code outside of\n\t  the Flash memory. The ARMv8-M MPU ports now support tickless idle mode.\n\t  See https://www.freertos.org/FreeRTOS-MPU-memory-protection-unit.html\n\t  for more information.\n\n\tAdditional noteworthy updates:\n\n\t+ Code formatting is now automated to facilitate the increase in\n\t  collaborative development in Git.  The auto-formated code is not identical\n\t  to the original formatting conventions.  Most notably spaces are now used\n\t  in place of tabs.\n\t+ The prototypes for callback functions (those that start with \"Application\",\n\t  such as vApplicationStackOverflowHook()) are now in the FreeRTOS header\n\t  files, removing the need for application writers to add prototypes into\n\t  the C files in which they define the functions.\n\t+ New Renesas RXv3 port layer.\n\t+ Updates to the Synopsys ARC code, including support for EM and HS cores,\n\t  and updated BSP.\n\t+ Added new POSIX port layer that allows FreeRTOS to run on Linux hosts in\n\t  the same way the Windows port layer enables FreeRTOS to run on Windows\n\t  hosts.\n\t+ Many other minor optimisations and enhancements. For full details\n\t  see https://github.com/FreeRTOS/FreeRTOS-Kernel/commits/main\n\n\nChanges between FreeRTOS V10.3.0 and FreeRTOS V10.3.1 released February 18 2020\n\n\tSee https://www.FreeRTOS.org/FreeRTOS-V10.3.x.html\n\n\t+ ./FreeRTOS-Labs directory was removed from this file. The libraries it\n\tcontained are now available as a separate download.\n\nChanges between FreeRTOS V10.2.1 and FreeRTOS V10.3.0 released February 7 2020\n\n\tSee https://www.FreeRTOS.org/FreeRTOS-V10.3.x.html\n\n\tNew and updated kernel ports:\n\n\t+ Added RISC-V port for the IAR compiler.\n\t+ Update the Windows simulator port to use a synchronous object to prevent\n\t  a user reported error whereby a task continues to run for a short time\n\t  after being moved to the Blocked state.  Note we were not able to\n\t  replicate the reported issue and it likely depends on your CPU model.\n\t+ Correct alignment of stack top in RISC-V port when\n\t  configISR_STACK_SIZE_WORDS is defined to a non zero value, which causes\n\t  the interrupt stack to be statically allocated.\n\t+ The RISC-V machine timer compare register can now be for any HART, whereas\n\t  previously it was always assumed FreeRTOS was running on HART 0.\n\t+ Update the sequence used to update the 64-bit machine timer\n\t  compare register on 32-bit cores to match that suggested in RISC-V\n\t  documentation.\n\t+ Added tickless low power modes into the ARM, IAR and GCC Cortex-M0 compiler\n\t  ports.\n\t+ Updated the behaviour of the ARMv7-M MPU (Memory Protection Unit) ports to\n\t  match that of the ARMv8-M ports whereby privilege escalations can only\n\t  originate from within the kernel's own memory segment.  Added\n\t  configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY configuration constant.\n\t+ Update existing MPU ports to correctly disable the MPU before it is\n\t  updated.\n\t+ Added contributed port and demo application for a T-Head (formally C-SKY)\n\t  microcontroller.\n\n\tNew API functions:\n\n\t+ Added the vPortGetHeapStats() API function which returns information on\n\t  the heap_4 and heap_5 state.\n\t+ Added xTaskCatchUpTicks(), which corrects the tick count value after the\n\t  application code has held interrupts disabled for an extended period.\n\t+ Added xTaskNotifyValueClear() API function.\n\t+ Added uxTimerGetReloadMode() API function.\n\n\tOther miscellaneous changes:\n\t+ Change type of uxPendedTicks from UBaseType_t to TickType_t to ensure it\n\t  has the same type as variables with which it is compared to, and therefore\n\t  also renamed the variable xPendingTicks.\n\t+ Update Keil projects that use the MPU so memory regions come from linker\n\t  script (scatter file) variables instead of being hard coded.\n\t+ Added LPC51U68 Cortex-M0+ demos for GCC (MCUXpresso), Keil and IAR\n\t  compilers.\n\t+ Added CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube demo.\n\t+ Added LPC54018 MPU demo.\n\t+ Rename xTaskGetIdleRunTimeCounter() to ulTaskGetIdleRunTimeCounter().\n\n\nChanges between FreeRTOS V10.2.1 and FreeRTOS V10.2.0 released May 13 2019:\n\n\t+ Added ARM Cortex-M23 port layer to complement the pre-existing ARM\n\t  Cortex-M33 port layer.\n\t+ The RISC-V port now automatically switches between 32-bit and 64-bit\n\t  cores.\n\t+ Introduced the portMEMORY_BARRIER macro to prevent instruction re-ordering\n\t  when GCC link time optimisation is used.\n\t+ Introduced the portDONT_DISCARD macro to the ARMv8-M ports to try and\n\t  prevent the secure side builds from removing symbols required by the\n\t  non secure side build.\n\t+ Introduced the portARCH_NAME to provide additional data to select semi-\n\t  automated build environments.\n\t+ Cortex-M33 and Cortex-M23 ports now correctly disable the MPU before\n\t  updating the MPU registers.\n\n\t+ Added Nuvoton NuMaker-PFM-M2351 ARM Cortex-M23 demo.\n\t+ Added LPC55S69 ARM Cortex-M33 demo.\n\t+ Added an STM32 dual core AMP stress test demo.\n\n\nChanges between FreeRTOS V10.1.1 and FreeRTOS V10.2.0 released February 25 2019:\n\n\t+ Added GCC RISC-V MCU port with three separate demo applications.\n\t+ Included pre-existing ARM Cortex-M33 (ARMv8-M) GCC/ARMclang and IAR ports\n\t  with Keil simulator demo.\n\t+ Update the method used to detect if a timer is active.  Previously the\n\t  timer was deemed to be inactive if it was not referenced from a list.\n\t  However, when a timer is updated it is temporarily removed from, then\n\t  re-added to a list, so now the timer's active status is stored separately.\n\t+ Add vTimerSetReloadMode(), xTaskGetIdleRunTimeCounter(), and\n\t  xTaskGetApplicationTaskTagFromISR() API functions.\n\t+ Updated third party Xtensa port so it is MIT licensed.\n\t+ Added configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H to the Renesas\n\t  compiler RX600v2 port to enable switching between platform.h and\n\t  iodefine.h includes within that port's port.c file.\n\t+ Removed the 'FromISR' functions from the MPU ports as ISRs run privileged\n\t  anyway.\n\t+ Added uxTaskGetStackHighWaterMark2() function to enable the return type to\n\t  be changed without breaking backward compatibility.\n\t  uxTaskGetStackHighWaterMark() returns a UBaseType_t as always,\n\t  uxTaskGetStackHighWaterMark2() returns configSTACK_DEPTH_TYPE to allow the\n\t  user to determine the return type.\n\t+ Fixed issues in memory protected ports related to different combinations\n\t  of static memory only and dynamic memory only builds.  As a result the\n\t  definition of tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE became more\n\t  complex and was moved to FreeRTOS.h with a table explaining its definition.\n\t+ Added a 'get task tag from ISR' function.\n\t+ Change the method used to determine if a timer is active or not from just\n\t  seeing if it is referenced from the active timer list to storing its\n\t  active state explicitly.  The change prevents the timer reporting that it\n\t  is inactive while it is being moved from one list to another.\n\t+ The pcName parameter passed into the task create functions can be NULL,\n\t  previously a name had to be provided.\n\t+ When using tickless idle, prvResetNextTaskUnblockTime() is now only called\n\t  in xTaskRemoveFromEventList() if the scheduler is not suspended.\n\t+ Introduced portHAS_STACK_OVERFLOW_CHECKING, which should be set to 1 for\n\t  FreeRTOS ports that run on architectures that have stack limit registers.\n\n\nChanges between FreeRTOS V10.1.0 and FreeRTOS V10.1.1 released 7 September 2018\n\n\t+ Reverted a few structure name changes that broke several kernel aware\n\t  debugger plug-ins.\n\t+ Updated to the latest trace recorder code.\n\t+ Fixed some formatting in the FreeRTOS+TCP TCP/IP stack code.\n\t+ Reverted moving some variables from file to function scope as doing so\n\t  broke debug scenarios that require the static qualifier to be removed.\n\nChanges between FreeRTOS V10.0.1 and FreeRTOS V10.1.0 released 22 August 2018\n\n\tFreeRTOS Kernel Changes:\n\n\t+ Update lint checked MISRA compliance to use the latest MISRA standard, was\n\t  previously using the original MISRA standard.\n\t+ Updated all object handles (TaskHandle_t, QueueHandle_t, etc.) to be\n\t  unique types instead of void pointers, improving type safety.  (this was\n\t  attempted some years back but had to be backed out due to bugs in some\n\t  debuggers).  Note this required the pvContainer member of a ListItem_t\n\t  struct to be renamed - set configENABLE_BACKWARD_COMPATIBILITY to 1 if\n\t  this causes an issue.\n\t+ Added configUSE_POSIX_ERRNO to enable per task POSIX style errno\n\t  functionality in a more user friendly way - previously the generic thread\n\t  local storage feature was used for this purpose.\n\t+ Added Xtensa port and demo application for the XCC compiler.\n\t+ Changed the implementation of vPortEndScheduler() for the Win32 port to\n\t  simply call exit( 0 ).\n\t+ Bug fix in vPortEnableInterrupt() for the GCC Microblaze port to protect\n\t  the read modify write access to an internal Microblaze register.\n\t+ Fix minor niggles when the MPU is used with regards to prototype\n\t  differences, static struct size differences, etc.\n\t+ The usStackHighWaterMark member of the TaskStatus_t structure now has type\n\t  configSTACK_DEPTH_TYPE in place of uint16_t - that change should have been\n\t  made when the configSTACK_DEPTH_TYPE type (which gets around the previous\n\t  16-bit limit on stack size specifications) was introduced.\n\t+ Added the xMessageBufferNextLengthBytes() API function and likewise stream\n\t  buffer equivalent.\n\t+ Introduce configMESSAGE_BUFFER_LENGTH_TYPE to allow the number of bytes\n\t  used to hold the length of a message in the message buffer to be reduced.\n\t  configMESSAGE_BUFFER_LENGTH_TYPE default to size_t, but if, for example,\n\t  messages can never be more than 255 bytes it could be set to uint8_t,\n\t  saving 3 bytes each time a message is written into the message buffer\n\t  (assuming sizeof( size_t ) is 4).\n\t+ Updated the StaticTimer_t structure to ensure it matches the size of the\n\t  Timer_t structure when the size of TaskFunction_t does not equal the size\n\t  of void *.\n\t+ Update various Xilinx demos to use 2018.1 version of the SDK tools.\n\t+ Various updates to demo tasks to maintain test coverage.\n\t+ FreeRTOS+UDP was removed in FreeRTOS V10.1.0 as it was replaced by\n\t  FreeRTOS+TCP, which was brought into the main download in FreeRTOS\n\t  V10.0.0.  FreeRTOS+TCP can be configured as a UDP only stack, and\n\t  FreeRTOS+UDP does not contain the patches applied to FreeRTOS+TCP.\n\n\tFreeRTOS+TCP Changes:\n\n\t+ Multiple security improvements and fixes in packet parsing routines, DNS\n\t  caching, and TCP sequence number and ID generation.\n\t+ Disable NBNS and LLMNR by default.\n\t+ Add TCP hang protection by default.\n\n\tWe thank Ori Karliner of Zimperium zLabs Team for reporting these issues.\n\n\nChanges between FreeRTOS V10.0.0 and FreeRTOS V10.0.1, released December 20 2017\n\n\t+ Fix position of \"#if defined( __cplusplus )\" in stream_buffer.h.\n\t+ Correct declarations of MPU_xQueuePeek() and MPU_xQueueSemaphoreTake() in\n\t  mpu_prototypes.h.\n\t+ Correct formatting in vTaskList() helper function when it prints the state\n\t  of the currently executing task.\n\t+ Introduce #error if stream_buffer.c is built without\n\t  configUSE_TASK_NOTIFICATIONS set to 1.\n\t+ Update FreeRTOS+TCP to V2.0.0\n\t\t- Improve the formatting of text that displays the available netword\n\t\t  interfaces when FreeRTOS+TCP is used on Windows with WinPCap.\n\t\t- Introduce ipconfigSOCKET_HAS_USER_WAKE_CALLBACK option to enable a user\n\t\t  definable callback to execute when data arrives on a socket.\n\nChanges between FreeRTOS V9.0.1 and FreeRTOS V10.0.0:\n\n\tThe FreeRTOS kernel is now MIT licensed: https://www.FreeRTOS.org/license\n\n\tNew Features and components:\n\n\t+ Stream Buffers - see https://www.FreeRTOS.org/RTOS-stream-buffer-example.html\n\t+ Message Buffers - see https://www.FreeRTOS.org//RTOS-message-buffer-example.html\n\t+ Move FreeRTOS+TCP into the main repository, along with the basic Win32\n\t  TCP demo FreeRTOS_Plus_TCP_Minimal_Windows_Simulator.\n\n\tNew ports or demos:\n\n\t+ Added demo for TI SimpleLink CC3220 MCU.\n\t+ Added MPU and non MPU projects for Microchip CEC and MEC 17xx and 51xx\n\t  MCUs.\n\t+ Added CORTEX_MPU_Static_Simulator_Keil_GCC demo to test static allocation\n\t  in the MPU port.\n\n\tFixes or enhancements:\n\n\t+ Cortex-M ports push additional register prior to calling\n\t  vTaskSwitchContext to ensure 8-byte alignment is maintained.  Only\n\t  important if a user defined tick hook function performs an operation that\n\t  requires 8-byte alignment.\n\t+ Optimisations to the implementation of the standard tickless idle mode on\n\t  Cortex-M devices.\n\t+ Improvements to the Win32 port including using higher priority threads.\n\t+ Ensure interrupt stack alignment on PIC32 ports.\n\t+ Updated GCC TriCore port to build with later compiler versions.\n\t+ Update mpu_wrappers.c to support static allocation.\n\t+ The uxNumberOfItems member of List_t is now volatile - solving an issue\n\t  when the IAR compiler was used with maximum optimization.\n\t+ Introduced configRECORD_STACK_HIGH_ADDRESS.  When set to 1 the stack start\n\t  address is saved into each task's TCB (assuming stack grows down).\n\t+ Introduced configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H to allow user defined\n\t  functionality, and user defined initialisation, to be added to FreeRTOS's\n\t  tasks.c source file.  When configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H is\n\t  set to 1 a user provided header file called freertos_task_c_additions.h\n\t  will be included at the bottom of tasks.c.  Functions defined in that\n\t  header file can call freertos_tasks_c_additions_init(), which in turn\n\t  calls a macro called FREERTOS_TASKS_C_ADDITIONS_INIT(), if it is defined.\n\t  FREERTOS_TASKS_C_ADDITIONS_INIT() can be defined in FreeRTOSConfig.h.\n\t+ Introduced configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( x ) which can be\n\t  defined by a user in FreeRTOSConfig.h.  The macro is called before\n\t  assessing whether to enter tickless idle mode or not.  If the macro sets\n\t  x to zero then tickless idle mode will not be entered.  This allows users\n\t  to abort tickless idle mode entry before the tickless idle function is\n\t  even called - previously it was only possible to abort from within the\n\t  tickless idle function itself.\n\t+ Added configPRINTF(), which can be defined by users to allow all libraries\n\t  to use the same print formatter.\n\t+ Introduced configMAX() and configMIN() macros which default to standard\n\t  max( x, y ) and min( x, y ) macro behaviour, but can be overridden if the\n\t  application writer defines the same macros in FreeRTOSConfig.h.\n\t+ Corrected the definition of StaticTask_t in the case where\n\t  INCLUDE_xTaskAbortDelay is set to 1.\n\t+ Introduced configTIMER_SERVICE_TASK_NAME and configIDLE_TASK_NAME, both of\n\t  which can be defined to strings in FreeRTOSConfig.h to change the default\n\t  names of the timer service and idle tasks respectively.\n\t+ Only fill the stack of a newly created task with a known value if stack\n\t  checking, or high water mark checking/viewing, is in use - removing the\n\t  dependency on memset() in other cases.\n\t+ Introduced xTaskCreateRestrictedStatic() so static allocation can be used\n\t  with the MPU.\n\t+ Ensure suspended tasks cannot be unsuspended by a received task\n\t  notification.\n\t+ Fix race condition in vTaskSetTimeOutState().\n\t+ Updated trace recorder files to the latest version.\n\nChanges since FreeRTOS V9.0.0:\n\n\t+ Priority dis-inheritance behaviour has been enhanced in the case where a\n\t  task that attempted to take a mutex that was held by a lower priority task\n\t  timed out before it was able to obtain the mutex (causing the task that\n\t  holds the mutex to have its priority raised, then lowered again, in\n\t  accordance with the priority inheritance protocol).\n\t+ Split the overloaded xQueueGenericReceive() function into three separate\n\t  dedicated functions.\n\t+ Allow the default human readable text names given to the Idle and Timer\n\t  tasks to be overridden by defining the configIDLE_TASK_NAME and\n\t  configTIMER_SERVICE_TASK_NAME definitions respectively in FreeRTOSConfig.h.\n\t+ Introduced configINITIAL_TICK_COUNT to allow the tick count to take a\n\t  value of than than 0 when the system boots.  This can be useful for\n\t  testing purposes - although setting configUSE_16_BIT_TICKS to 1 can also\n\t  be used to test frequent tick overflows.\n\t+ Ensure the Cortex-M SysTick count is cleared to zero before starting the\n\t  first task.\n\t+ Add configASSERT() into ARM Cortex-M ports to check the number of priority\n\t  bit settings.\n\t+ Clear the 'control' register before starting ARM Cortex-M4F ports in case\n\t  the FPU is used before the scheduler is started.  This just saves a few\n\t  bytes on the main stack as it prevents space being left for a later save\n\t  of FPU registers.\n\t+ Added xSemaphoreGetMutexHolderFromISR().\n\t+ Corrected use of portNVIC_PENDSVSET to portNVIC_PENDSVSET_BIT in MPU ports.\n\t+ Introduced configSTACK_DEPTH_TYPE to allow users to change the type used\n\t  to specify the stack size when using xTaskCreate().  For historic reasons,\n\t  when FreeRTOS was only used on small MCUs, the type was set to uint16_t,\n\t  but that can be too restrictive when FreeRTOS is used on larger\n\t  processors.  configSTACK_DEPTH_TYPE defaults to uint16_t.\n\t  xTaskCreateStatic(), being a newer function, used a uint32_t.\n\t+ Increase the priority of the Windows threads used by the Win32 port.  As\n\t  all the threads run on the same core, and the threads run with very high\n\t  priority, there is a risk that the host will become unresponsive, so also\n\t  prevent the Windows port executing on single core hosts.\n\nChanges between FreeRTOS V9.0.0 and FreeRTOS V9.0.0rc2 released May 25 2016:\n\n\tSee https://www.FreeRTOS.org/FreeRTOS-V9.html\n\n\tRTOS kernel updates:\n\n\t+ The prototype of the new xTaskCreateStatic() API function was modified to\n\t  remove a parameter and improve compatibility with other new\n\t  \"CreateStatic()\" API functions.  The stack size parameter in\n\t  xTaskCreateStatic() is now uint32_t, which changes the prototype of the\n\t  callback functions.  See the following URL:\n\t  https://www.FreeRTOS.org/xTaskCreateStatic.html\n\t+ GCC ARM Cortex-A port:  Introduced the configUSE_TASK_FPU_SUPPORT\n\t  constant.  When configUSE_TASK_FPU_SUPPORT is set to 2 every task is\n\t  automatically given a floating point (FPU) context.\n\t+ GCC ARM Cortex-A port:  It is now possible to automatically save and\n\t  restore all floating point (FPU) registers on entry to each potentially\n\t  nested interrupt by defining vApplicationFPUSafeIRQHandler() instead of\n\t  vApplicationIRQHandler().\n\t+ All ARM Cortex-M3/4F/7 ports:  Clear the least significant bit of the task\n\t  entry address placed onto the stack of a task when the task is created for\n\t  strict compliance with the ARM Cortex-M3/4/7 architecture documentation\n\t  (no noticeable effect unless using the QMEU emulator).\n\t+ Added GCC and Keil ARM Cortex-M4F MPU ports - previously the MPU was only\n\t  supported on ARM Cortex-M3.\n\t+ ARM Cortex-M3/4F MPU ports:  Update to fully support the FreeRTOS V9.0.0\n\t  API (other than static object creation) and added the\n\t  FreeRTOS/Demo/CORTEX_MPU_Simulator_Keil_GCC demo application to\n\t  demonstrate how to use the updated MPU port.\n\t+ All ARM Cortex-M3/4F/7 ports:  Add additional barrier instructions to the\n\t  default low power tickless implementation.\n\t+ All ARM Cortex-M0 ports:  Prevent an item being left on the stack of the\n\t  first task that executes.\n\t+ Win32 ports:  Reduce the amount of stack used and change the way Windows\n\t  threads are deleted to increase the maximum execution time.\n\t+ Add an ARM Cortex-M4F port for the MikroC compiler.  Ensure to read the\n\t  documentation page for this port before use.\n\t+ MPS430X IAR port:  Update to be compatible with the latest EW430 tools\n\t  release.\n\t+ IAR32 GCC port:  Correct vPortExitCritical() when\n\t  configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY.\n\t+ For consistency vTaskGetTaskInfo() now has the alias vTaskGetInfo(),\n\t  xTaskGetTaskHandle() now has the alias xTaskGetHandle() and\n\t  pcQueueGetQueueName() now has an alias pcQueueGetName().\n\t+ Fix various errors in comments and compiler warnings.\n\n\tDemo application updates:\n\n\t+ Update Atmel Studio projects to use Atmel Studio 7.\n\t+ Update Xilinx SDK projects to use the 2016.1 version of the SDK.\n\t+ Remove dependency on legacy IO libraries from the PIC32 demos.\n\t+ Move the Xilinx UltraScale Cortex-R5 demo into the main distribution.\n\t+ Update the MSP432 libraries to the latest version.\n\t+ Add Microchip CEC1302 (ARM Cortex-M4F) demos for GCC, Keil and MikroC\n\t  compilers.\n\t+ Move the Atmel SAMA5D2 demo into the main distribution.\n\nChanges between FreeRTOS V9.0.0rc1 and FreeRTOS V9.0.0rc2 (release candidate 2)\nreleased March 30 2016:\n\n\tNOTE - See https://www.FreeRTOS.org/FreeRTOS-V9.html for details\n\n\t+ The functions that create RTOS objects using static memory allocation have\n\t  been simplified and will not revert to using dynamic allocation if a\n\t  buffer is passed into a function as NULL.\n\t+ Introduced the configSUPPORT_DYNAMIC_ALLOCATION configuration constant to\n\t  allow a FreeRTOS application to be built without a heap even being being\n\t  defined. The Win32 example located in the\n\t  /FreeRTOS/demo/WIN32-MSVC-Static-Allocation-Only directory is provided as\n\t  a reference for projects that do not include a FreeRTOS heap.\n\t+ Minor run-time optimisations.\n\t+ Two new low power tickless implementations that target Silicon Labs EFM32\n\t  microcontrollers.\n\t+ Addition of the xTimerGetPeriod() and xTimerGetExpireTime() API functions.\n\nChanges between FreeRTOS V8.2.3 and FreeRTOS V9.0.0rc1 (release candidate 1)\nreleased February 19 2016:\n\n\tRTOS Kernel Updates:\n\n\t+ Major new feature - tasks, semaphores, queues, timers and event groups can\n\t  now be created using statically allocated memory, so without any calls to\n\t  pvPortMalloc().\n\t+ Major new features - Added the xTaskAbortDelay() API function which allows\n\t  one task to force another task to immediately leave the Blocked state,\n\t  even if the event the blocked task is waiting for has not occurred, or the\n\t  blocked task's timeout has not expired.\n\t+ Updates necessary to allow FreeRTOS to run on 64-bit architectures.\n\t+ Added vApplicationDaemonTaskStartupHook() which executes when the RTOS\n\t  daemon task (which used to be called the timer service task) starts\n\t  running.  This is useful if the application includes initialisation code\n\t  that would benefit from executing after the scheduler has been started.\n\t+ Added the xTaskGetTaskHandle() API function, which obtains a task handle\n\t  from the task's name.  xTaskGetTaskHandle() uses multiple string compare\n\t  operations, so it is recommended that it is called only once per task.\n\t  The handle returned by xTaskGetTaskHandle() can then be stored locally for\n\t  later re-use.\n\t+ Added the pcQueueGetQueueName() API function, which obtains the name of\n\t  a queue from the queue's handle.\n\t+ Tickless idling (for low power applications) can now also be used when\n\t  configUSE_PREEMPTION is 0.\n\t+ If one task deletes another task, then the stack and TCB of the deleted\n\t  task is now freed immediately.  If a task deletes itself, then the stack\n\t  and TCB of the deleted task are freed by the Idle task as before.\n\t+ If a task notification is used to unblock a task from an ISR, but the\n\t  xHigherPriorityTaskWoken parameter is not used, then pend a context switch\n\t  that will then occur during the next tick interrupt.\n\t+ Heap_1.c and Heap_2.c now use the configAPPLICATION_ALLOCATED_HEAP\n\t  settings, which previously was only used by heap_4.c.\n\t  configAPPLICATION_ALLOCATED_HEAP allows the application writer to declare\n\t  the array that will be used as the FreeRTOS heap, and in-so-doing, place\n\t  the heap at a specific memory location.\n\t+ TaskStatus_t structures are used to obtain details of a task.\n\t  TaskStatus_t now includes the bae address of the task's stack.\n\t+ Added the vTaskGetTaskInfo() API function, which returns a TaskStatus_t\n\t  structure that contains information about a single task.  Previously this\n\t  information could only be obtained for all the tasks at once, as an array\n\t  of TaskStatus_t structures.\n\t+ Added the uxSemaphoreGetCount() API function.\n\t+ Replicate previous Cortex-M4F and Cortex-M7 optimisations in some\n\t  Cortex-M3 port layers.\n\n\tDemo Application Updates:\n\n\tFurther demo applications will be added prior to the final FreeRTOS V9\n\trelease.\n\n\t+ Updated SAM4L Atmel Studio project to use Atmel Studio 7.\n\t+ Added ARM Cortex-A53 64-bit port.\n\t+ Added a port and demo for the ARM Cortex-A53 64-bit cores on the Xilinx\n\t  Ultrascale MPSoC.\n\t+ Added Cortex-M7 SAME70 GCC demo.\n\t+ Added EFM32 Giant and Wonder Gecko demos.\n\n\nChanges between V8.2.2 and V8.2.3 released October 16, 2015\n\n\tRTOS kernel updates:\n\n\t+ Fix bug identified in a modification made in V8.2.2 to the software timer\n\t  code that allows tickless low power applications to sleep indefinitely\n\t  when software timers are used.\n\t+ Simplify and improve efficiency of stack overflow checking.\n\t+ Add xTaskNotifyStateClear() API function.\n\t+ New IAR and GCC Cortex-R ports for microprocessors that do not use an ARM\n\t  generic interrupt controller (GIC).\n\t+ New PIC32MEC14xx port.\n\t+ Add support for PIC32MZ EF parts (with floating point) into the PIC32MZ\n\t  port.\n\t+ Zynq7000 port layer now declares the functions that setup and clear the\n\t  tick interrupt as weak symbols so they can be overridden by the\n\t  application, and uses a global XScuGic object so the same object can be\n\t  used by the application code.\n\t+ Introduced configUSE_TASK_FPU_SUPPORT, although the PIC32MZ EF port is\n\t  currently the only port that uses it.\n\t+ Updates to RL78 and 78K0 IAR port layers to improve support for\n\t  combinations of memory models.\n\t+ Minor updates to heap_5.c to remove compiler warnings generated by some\n\t  compilers.\n\t+ License simplifications.  See /FreeRTOS/License/license.txt in the\n\t  official distribution.\n\n\tFreeRTOS+ updates:\n\n\t+ Update directory names to use WolfSSL instead of CyaSSL, inline with\n\t  WolfSSL's re-branding.\n\t+ Update to latest WolfSSL code.\n\t+ Update to latest FreeRTOS+Trace recorder code.\n\t+ Add in the FreeRTOS+Trace recorder library required for streaming trace.\n\n\tDemo application changes:\n\n\t+ Add demo applications for Renesas RZ/T (Cortex-R), PIC32MZ EF (PIC32 with\n\t  floating point hardware), PIC32MEC14xx, RX71M, RX113 and RX231.\n\t+ General tidy up of spelling and compiler warnings.\n\n\nChanges between V8.2.1 and V8.2.2 released August 12, 2015\n\n\tRTOS kernel updates:\n\n\t+ Added Intel IA32/x86 32-bit port.\n\t+ General maintenance.\n\t+ PRIVILEGED_FUNCTION and PRIVILEGED_DATA macros, which are used in memory\n\t  protected systems, have been added to the newer event group and software\n\t  timer functions.\n\t+ Add the errno definitions used by FreeRTOS+ components into projdefs.h.\n\t+ Remove the restriction that prevented tick-less idle implementations\n\t  waiting indefinitely when software timers were used in the same\n\t  application.\n\t+ Introduce xTaskNotifyAndQueryFromISR() as the interrupt safe version of\n\t  xTaskNotifyAndQuery().\n\t+ Add additional NOPs to the MSP430X port layers to ensure strict compliance\n\t  with the hardware documentation.\n\t+ Microblaze port: Added option for port optimised task selection.\n\t+ Microblaze port: Previously tasks inherited the exception enable state\n\t  at the time the task was created.  Now all tasks are created with\n\t  exceptions enabled if the Microblaze design supports exceptions.\n\t+ Windows port: Add additional safe guards to ensure the correct start up\n\t  sequence and thread switching timing.\n\t+ Windows port: Improve the implementation of the port optimised task\n\t  selection assembly code.\n\t+ Update heap_4 and heap_5 to allow use on 64-bit processors.\n\t+ Simplify the code that creates a queue.\n\t+ General improved tick-less idle behaviour.\n\t+ Ensure none of the variables in the common kernel files are initialised to\n\t  anything other than zero.\n\t+ Correct calculation of xHeapStructSize in heap_4 and heap_5.\n\n\tDemo application updates:\n\n\t+ Added demo project for the new IA32/x86 port that targets the Galileo\n\t  hardware.\n\t+ Added MSP430FR5969 demos (previously provided as a separate download).\n\t+ Added FreeRTOS BSP repository for automatic creation of FreeRTOS\n\t  applications in the Xilinx SDK.\n\t+ Added Atmel Studio / GCC project for the SAMV71 (ARM Cortex-M7)\n\t+ Update Xilinx SDK projects to use version 2015.2 of the SDK.\n\t+ Remove Microblaze demos that were using obsolete tools.\n\t+ Add MSP43FR5969 IAR and CCS demos.\n\n\tFreeRTOS+ Updates:\n\n\t+ Updated FreeRTOS+Trace recorder library, which requires an update to the\n\t  FreeRTOS+Trace application.\n\t+ Added Reliance Edge source code and demo application.  Reliance edge is\n\t  a fail safe transactional file system ideal for applications that require\n\t  file storage, and especially when high reliability is essential.\n\t+ Introduce configAPPLICATION_PROVIDES_cOutputBuffer to allow FreeRTOS+CLI\n\t  users to place the output buffer at a fixed memory address.\n\t+ Improve the NetworkInterface.c file provided for the Windows port of\n\t  FreeRTOS+UDP.\n\nChanges between V8.2.0 and V8.2.1 released 24th March 2015.\n\n\tRTOS kernel updates:\n\n\t+ Added user definable and flexible thread local storage facility.\n\t+ Added vTimerSetTimerID() API function to complement the pvTimerGetTimerID()\n\t  function to allow the timer's ID to be used as timer local storage.\n\t+ Fixed a potential issue related to the use of queue sets from an ISR.\n\t+ Some updates to the Xilinx Microblaze GCC port.\n\t+ Added ARM Cortex-M4F port for Texas Instruments Code Composer Studio.\n\t+ Added ARM Cortex-M7 r0p1 port layer for IAR, GCC and Keil which contains a\n\t  minor errata work around.  All other ARM Cortex-M7 core revisions should\n\t  use the ARM Cortex-M4F port.\n\t+ Exclude the whole of croutine.c if configUSE_CO_ROUTINES is set to 0.\n\t+ Change some data types from uint32_t to size_t in preparation for 64-bit\n\t  Windows port.\n\t+ Update the PIC32 port to remove deprecation warnings output by the latest\n\t  XC32 compilers.\n\t+ Fix bug when xQueueOverwrite() and xQueueOverwrite() from ISR are used to\n\t  overwrite items in two queues that are part of the same set.\n\n\tDemo application updates:\n\n\t+ Added demo application for TI's ARM Cortex-M4F based MSP432\n\t  microcontroller using IAR, Keil and CCS compilers.\n\t+ Added demo application for STM32F ARM Cortex-M7 based microcontroller\n\t  using IAR and Keil.\n\t+ Added demo application for Atmel SAMV71 ARM Cortex-M7 based\n\t  microcontroller using IAR and Keil.\n\t+ Added Microblaze demo that uses the 2014.4 version of the Xilinx SDK and\n\t  runs on the KC705 evaluation board (Kintex FPGA).\n\nChanges between V8.1.2 and V8.2.0 released 16th January 2015\n\n\tChanges between release candidate 1 and the official release are restricted\n\tto maintenance only.\n\n\tSignificant RTOS kernel updates:\n\n\t+ MAJOR NEW FEATURE!  Task notifications.  Please see the following URL for\n\t  details: https://www.FreeRTOS.org/RTOS-task-notifications.html\n\t+ NEW HEADER FILE REQUIRED!  Obsolete definitions have been separated into\n\t  a new header file called FreeRTOS/Source/include/deprecated_definitions.h.\n\t  This header file must be present to build.  Note some of the obsolete\n\t  definitions are still used by very old demo application projects.\n\n\tOther RTOS kernel updates:\n\n\t+ Made xSemaphoreGiveFromISR() a function rather than a macro that calls\n\t  xQueueGenericSendFromISR().  This allows for major performance\n\t  enhancements at the expense of some additional code size if both functions\n\t  are used in the same application.  NOTE:  In most uses cases such use of\n\t  a semaphore can now be replaced with a task notification which is smaller\n\t  and faster still.\n\t+ The TCB is now always allocated such that the task's stack grows away from\n\t  the TCB (improves debugging of stack overflows as the overflow will not\n\t  overwrite the task's name).\n\t+ GCC, IAR and Keil Cortex-M4F ports now use more inlining (performance\n\t  enhancements at the cost of a little additional code space).\n\t+ Queues are now allocated with a single call to pvPortMalloc() which\n\t  allocates both the queue structure and the queue storage area.\n\t+ Introduced a new critical section macro for reading the tick count that\n\t  defines away to nothing in cases where the width of the tick allows the\n\t  tick count to be read atomically (performance benefits - especially when\n\t  optimisation is on).\n\t+ Introduced configAPPLICATION_ALLOCATED_HEAP in heap_4.c to allow the\n\t  application writer to provide their own heap array - and in so doing\n\t  control the location of the heap.\n\t+ Introduced configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES which, when set, will\n\t  include known values in both list and list item structures.  The values\n\t  are intended to assist debugging.  If the values get overwritten then it\n\t  is likely application code has written over RAM used by the kernel.\n\t+ configASSERT()s in all Cortex-M ports used to test the lowest 5 bits of\n\t  the interrupt control register to detect taskENTER_CRITICAL() being called\n\t  from an interrupt.  This has been changed to test all 8 bits.\n\t+ Introduced uxTaskPriorityGetFromISR().\n\t+ Microblze V8 port now tests XPAR_MICROBLAZE_0_USE_FPU for inequality to 0\n\t  rather than equality to 1, and 2 and 3 are also valid values.\n\t+ Cortex-A5 GIC-less port no longer passes the address of the interrupting\n\t  peripheral into the interrupt handler.\n\t+ Fix an issue in FreeRTOS-MPU where an attempt was made to free the stack\n\t  belonging to a task when the task was deleted, even when the stack was\n\t  allocated statically.\n\t+ Utility (helper) functions that format task statistic information into\n\t  human readable tables now pad task names with spaces to ensure columns\n\t  line up correctly even where task name lengths vary greatly.\n\t+ Update FreeRTOS+Trace recorder library to version 2.7.0.\n\n\tDemo application updates:\n\n\t+ Added two new standard demo task sets:  IntSemTest and TaskNotify.\n\t+ Added port and demo application for Atmel SAMA5D4 Cortex-A5 MPU.\n\t+ Added demo application for Altera Cyclone V Cortex-A9 MPU.\n\t+ Updated Zynq demo to use version 2014.4 of Xilinx's SDK and added in\n\t  demo tasks for new RTOS features.\n\t+ Updated Atmel SAM4E and SAM4S demos to include a lot of additional test\n\t  and demo tasks.\n\t+ Fixed a corner case issue in Atmel SAM4L low power tickless\n\t  implementation, and added button interrupt handling.\n\t+ Make the interrupt queue tests more tolerant to heave CPU loads.\n\t+ Updated MSVC FreeRTOS simulator demo to include the latest standard test\n\t  and demo tasks.\n\t+ Updated MingW/Eclipse FreeRTOS simulator demo to match the FreeRTOS MSVC\n\t  simulator demo.\n\t+ Updated all demos that use FreeRTOS+Trace to work with the latest trace\n\t  recorder code.\n\n\nChanges between V8.1.1 and V8.1.2 released September 2nd 2014\n\n\tMove the defaulting of configUSE_PORT_OPTIMISED_TASK_SELECTION into the\n\tindividual port layers where necessary so it does not affect ports that do\n\tnot support the definition.\n\nChanges between V8.1.0 and V8.1.1 released August 29th 2014\n\n\tBy popular requests - a minor patch to V8.1.0 to re-instate the ability to\n\tgive a mutex type semaphore (with priority inheritance) from an interrupt\n\thandler.\n\nChanges between V8.0.1 and V8.1.0 released August 26th 2014\n\n\tFreeRTOS scheduler, kernel, demo and test updates:\n\n\t+ Improved the priority inheritance algorithms to assist integration with\n\t  off the shelf middleware that may hold multiple mutexes simultaneously.\n\t+ Introduce heap_5.c, which is similar to heap_4.c but allows the heap to\n\t  span multiple non-contiguous memory regions.\n\t+ Updated all Cortex-A9 ports to help trap a couple of common usage errors -\n\t  the first being when a task incorrectly attempts to exit its implementing\n\t  function and the second being when a non interrupt safe API function is\n\t  called from an interrupt.\n\t+ Update all Cortex-A9 ports to remove obsolete mode switches prior to\n\t  restoring a task context.\n\t+ configUSE_PORT_OPTIMISED_TASK_SELECTION now defaults to 1 instead of 0.\n\t+ Update all Cortex-M3/4F ports to trap a non interrupt safe API function\n\t  being called from an interrupt handler.\n\t+ Simplify the alignment checks in heap_4.c.\n\t+ Update the MSVC Windows simulator demo to use heap_5.c in place of\n\t  heap_4.c to ensure end users have an example to refer to.\n\t+ Updated standard demo test code to test the new priority inheritance\n\t  algorithms.\n\t+ Updated the standard demo tasks to make use of stdint and the FreeRTOS\n\t  specific typedefs that were introduced in FreeRTOS V8.0.0.\n\t+ Introduce the pdMS_TO_TICKS() macro as a more user friendly and intuitive\n\t  alternative to pdTICKS_PER_MS - both of which can be used to convert a\n\t  time specified in milliseconds to a time specified in RTOS ticks.\n\t+ Fix a bug in the Tasking compiler's Cortex-M port that resulted in an\n\t  incorrect value being written to the basepri register.  This only effects\n\t  users of the Tasking compiler.\n\t+ Update the Zynq demo to use version 2014.2 of the SDK and add in an lwIP\n\t  example that demonstrates lwIP being used with both its raw and sockets\n\t  interfaces.\n\t+ Updated the CCS Cortex-R4 port to enable it to be built with the latest\n\t  CCS compiler.\n\n\tNew ports and demo applications:\n\n\t+ Two Renesas RX64M ports (RXv2 core) and demos introduced, one for the GCC\n\t  compiler and one for the Renesas compiler.  Both demos use e2 studio.\n\t+ Generic IAR Cortex-A5 port (without any reliance on a GIC) introduced.\n\t  The new port is demonstrated on an Atmel SAMA5D3 XPlained board.\n\n\tFreeRTOS+ component updates:\n\n\t+ Update CyaSSL to the latest version.\n\t+ Updated the FreeRTOS+ components supplied directly by Real Time Engineers\n\t  Ltd. to make use of stdint and the FreeRTOS specific typedefs that were\n\t  introduced in FreeRTOS V8.0.0.\n\t+ Rework and simplify the FreeRTOS+FAT SL RAM disk driver.\n\n\tMiscellaneous updates and maintenance:\n\n\t+ Update the IAR and DS-5/ARM RZ demos to target the official RZ RSK\n\t  hardware in place of the previously targeted Renesas internal (not\n\t  publicly available) hardware.\n\t+ Various other maintenance tasks.\n\n\nChanges between V8.0.0 and V8.0.1 released 2nd May 2014\n\n\t+ Minor fixes to the event group functionality that was released in V8.0.0.\n\t  The 'clear bits from ISR' functionality is now implemented using a\n\t  deferred interrupt callback instead of a function, and the 'wait bits' and\n\t  'task sync' functions now correctly clear internal control bits before\n\t  returning a value in every possible path through the respective functions.\n\t+ Ensure the updating of internal control data is protected by a critical\n\t  section after a task is deleted or suspended.\n\t+ Minor fixes to FreeRTOS+FAT SL - namely seeking beyond the end of a file\n\t  when the offset was not a multiple of the sector size.\n\t+ Ensure Cortex-A9 system registers are only ever accessed as 32-bit values,\n\t  even when only the lest significant byte of the register is implemented.\n\n\tOther updates:\n\n\t+ Updated the XMC4200 IAR project so it links with version 7.x of the IAR\n\t  tools.\n\t+ Add RL78L1C demo.\n\t+ Add pcTimerGetName() API function.\n\t+ Call _reclaim_reent() when a task is deleted if configUSE_NEWLIB_REENTRANT\n\t  is defined.\n\nChanges between V7.6.0 and V8.0.0 released 19th Feb 2014\n\n\thttps://www.FreeRTOS.org/upgrading-to-FreeRTOS-V8.html\n\n\tFreeRTOS V8.x.x is a drop-in compatible replacement for FreeRTOS V7.x.x,\n\talthough a change to the type used to reference character strings may result\n\tin application code generating a few (easily clearable) compiler warnings\n\tafter the upgrade, and an updated typedef naming convention means use of the\n\told typedef names is now discouraged.\n\tSee https://www.FreeRTOS.org/upgrading-to-FreeRTOS-V8.html for full\n\tinformation.\n\n\tNew features and functionality:\n\n\t+ Event groups - see https://www.FreeRTOS.org/FreeRTOS-Event-Groups.html\n\t+ Centralised deferred interrupt processing - see\n\t  https://www.FreeRTOS.org/xTimerPendFunctionCallFromISR.html\n\n\tOther updates:\n\n\t+ Previously, when a task left the Blocked state, a context switch was\n\t  performed if the priority of the unblocked task was greater than or equal\n\t  to the priority of the Running task.  Now a context switch is only\n\t  performed if the priority of the unblocked task is greater than the\n\t  priority of the Running task.\n\t+ New low power tickless demonstration project that targets the ST STM32L\n\t  microcontroller - see\n\t  https://www.FreeRTOS.org/STM32L-discovery-low-power-tickless-RTOS-demo.html\n\t+ Add xPortGetMinimumEverFreeHeapSize() to heap_4.c.\n\t+ Small change to the tickless low power implementation on the SAM4L to\n\t  ensure the alarm value (compare match value) cannot be set to zero when a\n\t  tickless period is exited due to an interrupt originating from a source\n\t  other than the RTOS tick.\n\t+ Update the GCC/Eclipse Win32 simulator demo to make better use of Eclipse\n\t  resource filters and match the functionality of the MSVC equivalent.\n\t+ xTaskIsTaskSuspended() is no longer a public function.  Use\n\t  eTaskGetState() in its place.\n\t+ Improved trace macros, including tracing of heap usage.\n\t+ Remove one level of indirection when accepting interrupts on the PIC32MZ.\n\t+ Add Cortex-A9 GCC port layer.\n\t+ Add Xilinx Zynq demo application.\n\n\nChanges between V7.5.3 and V7.6.0 released 18th November 2013\n\n\tV7.6.0 changes some behaviour when the co-operative scheduler is used (when\n\tconfigUSE_PREEMPTION is set to 0).  It is important to note that the\n\tbehaviour of the pre-emptive scheduler is unchanged - the following\n\tdescription only applies when configUSE_PREEMPTION is set to 0:\n\n\tWHEN configUSE_PREEMPTION IS SET TO 0 (which is in a small minority of\n\tcases) a context switch will now only occur when a task places itself into\n\tthe Blocked state, or explicitly calls taskYIELD().  This differs from\n\tprevious versions, where a context switch would also occur when implicitly\n\tmoving a higher priority task out of the Blocked state.  For example,\n\tpreviously, WHEN PREEMPTION WAS TURNED OFF, if task A unblocks task B by\n\twriting to a queue, then the scheduler would switch to the higher priority\n\ttask.  Now, WHEN PREEMPTION IS TURNED OFF, if task A unblocks task B by\n\twriting to a queue, task B will not start running until task A enters the\n\tBlocked state or task A calls taskYIELD().  [If configUSE_PREEMPTION is not\n\tset to 0, so the normal pre-emptive scheduler is being used, then task B\n\twill start running immediately that it is moved out of the Blocked state].\n\n\tOther changes:\n\n\t+ Added a port layer and a demo project for the new PIC32MZ architecture.\n\t+ Update the PIC32MX port layer to re-introduce some ehb instructions that\n\t  were previously removed, add the ability to catch interrupt stack\n\t  overflows (previously only task stack overflows were trapped), and also\n\t  add the ability to catch an application task incorrectly attempting to\n\t  return from its implementing function.\n\t+ Make dramatic improvements to the performance of the Win32 simulator port\n\t  layer.\n\t+ Ensure tasks that are blocked indefinitely report their state as Blocked\n\t  instead of Suspended.\n\t+ Slight improvement to the Cortex-M4F port layers where previously one\n\t  register was inadvertently being saved twice.\n\t+ Introduce the xSemaphoreCreateBinary() API function to ensure consistency\n\t  in the semantics of how each semaphore type is created.  It is no longer\n\t  recommended to use vSemaphoreCreateBinary() (the version prefixed with a\n\t  'v'), although it will remain in the code for backward compatibility.\n\t+ Update the Cortex-M0 port layers to allow the scheduler to be started\n\t  without using the SVC handler.\n\t+ Added a build configuration to the PIC32MX MPLAB X demo project that\n\t  targets the PIC32 USB II starter kit.  Previously all the build\n\t  configurations required the Explorer 16 hardware.\n\t+ Some of the standard demo tasks have been updated to ensure they execute\n\t  correctly with the updated co-operative scheduling behaviour.\n\t+ Added comprehensive demo for the Atmel SAM4E, including use of\n\t  FreeRTOS+UDP, FreeRTOS+FAT SL and FreeRTOS+CLI.\n\n\tFreeRTOS+ Changes:\n\n\t+ Minor maintenance on FreeRTOS+UDP.\n\nChanges between V7.5.2 and V7.5.3 released October 14 2013\n\n\tKernel changes:\n\n\t+ Prior to V7.5.x yields requested from the tick hook would occur in the\n\t  same tick interrupt - revert to that original behaviour.\n\t+ New API function uxQueueSpacesAvailable().\n\t+ Introduced the prvTaskExitError() function to Cortex-M0, Cortex-M3/4\n\t  and Cortex-M4F ports.  prvTaskExitError() is used to trap tasks that\n\t  attempt to return from their implementing functions (tasks should call\n\t  vTaskDelete( NULL ); if they want to exit).\n\t+ The Cortex-M0 version of portSET_INTERRUPT_MASK_FROM_ISR and\n\t  portCLEAR_INTERRUPT_MASK_FROM_ISR are now fully nestable.\n\t+ Improved behaviour and robustness of the default Cortex-M tickless idle\n\t  behaviour.\n\t+ Add workaround for silicon errata PMU_CM001 in Infineon XMC4000 devices to\n\t  all Cortex-M4F ports.\n\t+ Add Cortex-M0 port for Keil.\n\t+ Updated Cortus port.\n\t+ Ensure _impure_ptr is initialised before the scheduler is started.\n\t  Previously it was not set until the first context switch.\n\n\tFreeRTOS+ changes:\n\n\t+ Update FreeRTOS+UDP to V1.0.1 - including direct integration of the\n\t  FreeRTOS+Nabto task, improvements to the DHCP behaviour, and a correction\n\t  to the test that prevents the network event hook being called on the first\n\t  network down event.  The FreeRTOS+UDP change history is maintained\n\t  separately.\n\t+ Correct the __NVIC_PRIO_BITS setting in the LPC18xx.h header files\n\t  provided in the NXP CMSIS library, then update the interrupts used by the\n\t  LPC18xx demos accordingly.\n\t+ Replace double quotes (\") with single quotes (') in FreeRTOS+CLI help\n\t  strings to ensure the strings can be used with the JSON descriptions used\n\t  in the FreeRTOS+Nabto demos.\n\n\tDemo and miscellaneous changes:\n\n\t+ Added demo for the Atmel SAMD20 Cortex-M0+.  The demo includes\n\t  FreeRTOS+CLI\n\t+ Added a demo for the Infineon Cortex-M0 that can be built with the IAR\n\t  Keil and GCC tools.\n\t+ Updated the Infineon XMC4000 demos for IAR, Keil, GCC and Tasking tools,\n\t  with additional build configurations to directly support the XMC4200 and\n\t  XMC4400 devices, in addition to the previously supported XMC4500.\n\t+ Updated the demo application.\n\t+ Added additional trace macros traceMALLOC and traceFREE to track heap\n\t  usage.\n\nChanges between V7.5.0 and V7.5.2 released July 24 2013\n\n\tV7.5.2 makes the new Cortex-M vPortCheckInterruptPriority() function\n\tcompatible with the STM32 standard peripheral driver library, and adds\n\tan extra critical section to the default low power tickless mode\n\timplementation.  Only users of the STM32 peripheral library or the default\n\ttickless implementation need update from version 7.5.0.\n\nChanges between V7.4.2 and V7.5.0 released July 19 2013\n\n\tV7.5.0 is a major upgrade that includes multiple scheduling and efficiency\n\timprovements, and some new API functions.\n\n\tCompatibility information for FreeRTOS users:\n\t  FreeRTOS V7.5.0 is backward compatible with FreeRTOS V7.4.0 with one\n\t  exception; the vTaskList() and vTaskGetRunTimeStats() functions are now\n\t  considered legacy, having been replaced by the single uxTaskGetSystemState()\n\t  function.  configUSE_STATS_FORMATTING_FUNCTIONS must be set to 1 in\n\t  FreeRTOSConfig.h for vTaskList() and vTaskGetRunTimeStats() to be\n\t  available.\n\n\tCompatibility information for FreeRTOS port writers:\n\t  vTaskIncrementTick() is now called xTaskIncrementTick() (because it now\n\t  returns a value).\n\n\tHeadline changes:\n\n\t+ Multiple scheduling and efficiency improvements.\n\t+ Core kernel files now pass PC-Lint V8 static checking without outputting\n\t  any warnings (information on the test conditions will follow).\n\n\tNew API functions:\n\n\t+ uxTaskGetSystemState() https://www.FreeRTOS.org/uxTaskGetSystemState.html\n\t+ xQueueOverwrite() https://www.FreeRTOS.org/xQueueOverwrite.html\n\t+ xQueueOverwriteFromISR()\n\t+ xQueuePeekFromISR()\n\n\tThe following ports and demos, which were previously available separately,\n\tare now incorporated into the main FreeRTOS zip file download:\n\n\t+ ARM Cortex-A9 IAR\n\t+ ARM Cortex-A9 ARM compiler\n\t+ Renesas RZ\n\t+ Microsemi SmartFusion2\n\n\tNew FreeRTOSConfig.h settings\n\thttps://freertos.org/a00110.html\n\n\t+ configUSE_TIME_SLICING\n\t+ configUSE_NEWLIB_REENTRANT\n\t+ configUSE_STATS_FORMATTING_FUNCTIONS\n\t+ configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS\n\n\tOther changes:\n\n\t+ (MPU port only) The configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS\n\t  options provides a mechanism that allows application writers to execute\n\t  certain functions in privileged mode even when a task is running in user\n\t  mode.\n\t+ Ports that support interrupt nesting now include a configASSERT() that\n\t  will trigger if an interrupt safe FreeRTOS function is called from an\n\t  interrupt that has a priority designated as above the maximum system/API\n\t  call interrupt priority.\n\t+ The included FreeRTOS+Trace recorder code has been updated to the latest\n\t  version, and the demo applications that use the trace recorder code have\n\t  been updated accordingly.\n\t+ The FreeRTOS Windows Simulator (MSVC version only) has been updated to\n\t  include a new basic 'blinky' build option in addition to the original\n\t  comprehensive build option.\n\t+ Improve RAM usage efficiency of heap_4.c and heap_2.c.\n\t+ Prevent heap_4.c from attempting to free memory blocks that were not\n\t  allocated by heap_4.c, or have already been freed.\n\t+ As FreeRTOS now comes with FreeRTOS+FAT SL (donated by HCC) the Chan FATfs\n\t  files have been removed from FreeRTOS/Demo/Common.\n\t+ Fix build error when R4 port is build in co-operative mode.\n\t+ Multiple port and demo application maintenance activities.\n\nChanges between V7.4.1 and V7.4.2 released May 1 2013\n\n\tNOTE: There are no changes in the FreeRTOS kernel between V7.4.1 and V7.4.2\n\n\t+ Added FreeRTOS+FAT SL source code and demo project.  The demo project\n\t  runs in the FreeRTOS Windows simulator for easy and hardware independent\n\t  experimentation and evaluation.  See https://www.FreeRTOS.org/fat_sl\n\nChanges between V7.4.0 and V7.4.1 released April 18 2013\n\n\t+ To ensure strict conformance with the spec and ensure compatibility with\n\t  future chips data and instruction barrier instructions have been added to\n\t  the yield macros of Cortex-M and Cortex-R port layers.  For efficiency\n\t  the Cortex-M port layer \"yield\" and \"yield\" from ISR are now implemented\n\t  separately as the barrier instructions are not required in the ISR case.\n\t+ Added FreeRTOS+UDP into main download.\n\t+ Reorganised the FreeRTOS+ directory so it now matches the FreeRTOS\n\t  directory with Source and Demo subdirectories.\n\t+ Implemented the Berkeley sockets select() function in FreeRTOS+UDP.\n\t+ Changed (unsigned) casting in calls to standard library functions with\n\t  (size_t) casting.\n\t+ Added the Atmel SAM4L and Renesas RX100 demos that demonstrates the\n\t  tickless (tick suppression) low power FreeRTOS features.\n\t+ Add a new RL78 IAR demo that targets numerous new RL78 chips and\n\t  evaluation boards.\n\t+ Adjusted stack alignment on RX200 ports to ensure an assert was not\n\t  falsely triggered when configASSERT() is defined.\n\t+ Updated the Cortex_M4F_Infineon_XMC4500_IAR demo to build with the latest\n\t  version of EWARM.\n\t+ Corrected header comments in the het.c and het.h files (RM48/TMS570 demo).\n\n\nChanges between V7.3.0 and V7.4.0 released February 20 2013\n\n\t+ New feature:  Queue sets.  See:\n\t  https://www.FreeRTOS.org/Pend-on-multiple-rtos-objects.html\n\t+ Overhauled the default tickless idle mode implementation provided with the\n\t  ARM Cortex-M3 port layers.\n\t+ Enhanced tickless support in the core kernel code with the introduction of\n\t  the configEXPECTED_IDLE_TIME_BEFORE_SLEEP macro and the\n\t  eTaskConfirmSleepModeStatus() function.\n\t+ Added the QueueSet.c common demo/test file.  Several demo applications\n\t  have been updated to use the new demo/test tasks.\n\t+ Removed reliance on the PLIB libraries from the MPLAB PIC32 port layer and\n\t  demo applications.\n\t+ Added the FreeRTOS+Trace recorder code to the MSVC Win32 demo.\n\t+ Renamed eTaskStateGet() to eTaskGetState() for consistency, and added a\n\t  pre-processor macro for backward compatibility with the previous name.\n\t+ Updated functions implemented in the core queue.c source file to allow\n\t  queue.h to be included from the .c file directly (this prevents compiler\n\t  warnings that were generated by some compilers).\n\t+ Updated the CCS Cortex-R4 port layer to replace the CLZ assembler function\n\t  with the CLZ compiler intrinsic that is provided by the latest versions of\n\t  the CCS ARM compiler.\n\t+ Updated all heap_x.c implementations to replace the structure that was\n\t  used to ensure the start of the heap was aligned with a more portable\n\t  direct C code implementation.\n\t+ Added support for PIC24 devices that include EDS.\n\t+ Minor optimisations to the PIC32 port layer.\n\t+ Minor changes to tasks.c that allow the state viewer plug-ins to display\n\t  additional information.\n\t+ Bug fix:  Update prvProcessReceivedCommands() in timers.c to remove an\n\t  issue that could occur if the priority of the timer daemon task was set\n\t  below the priority of tasks that used timer services.\n\t+ Update the FreeRTOS+Trace recorder code to the latest version.\n\nChanges between V7.2.0 and V7.3.0 released October 31 2012\n\n\t+ Added ability to override the default scheduler task selection mechanism\n\t  with implementations that make use of architecture specific instructions.\n\t+ Added ability to suppress tick interrupts during idle time, and in so\n\t  doing, provide the ability to make use of architecture specific low power\n\t  functionality.\n\t+ Added the portSUPPRESS_TICKS_AND_SLEEP() macro and vTaskStepTick() helper\n\t  function.\n\t+ Added the configSYSTICK_CLOCK_HZ configuration constant.\n\t+ Reworked the Cortex-M3 and Cortex-M4F port layers for GCC, Keil and IAR to\n\t  directly support basic power saving functionality.\n\t+ Added hooks to allow basic power saving to be augmented in the application\n\t  by making use of chip specific functionality.\n\t+ Minor change to allow mutex type semaphores to be used from interrupts\n\t  (which would not be a normal usage model for a mutex).\n\t+ Change the behaviour of the interrupt safe interrupt mask save and restore\n\t  macros in the Cortex-M ports.  The save macro now returns the previous\n\t  mask value.  The restore macro now uses the previous mask value.  These\n\t  changes are not necessary for the kernel's own implementation, and are\n\t  made purely because the macros were being used by application writers.\n\t+ Added eTaskStateGet() API function.\n\t+ Added port specific optimisations to the PIC32 port layer, and updated the\n\t  PIC32 demo applications to make use of this new feature.\n\t+ Added port specific optimisations to the Win32 simulator port.\n\t+ Added new ports and demo applications for the TI Hercules RM48 and TMS570\n\t  safety microcontrollers.\n\t+ Added SAM3 demos targeting the ATSAM3S-EK2 and ATSAM3X-EK evaluation\n\t  boards.\n\t+ Updated the PIC32 MPLAB X project to manually set the compiler include\n\t  paths instead of using the IDE entry box following reports that the\n\t  include paths were somehow being deleted.\n\t+ Improved character handling in FreeRTOS+CLI.\n\nChanges between V7.1.1 and V7.2.0 released 14 August 2012\n\n\tFreeRTOS V7.2.0 is backward compatible with FreeRTOS V7.1.2.\n\n\t+ Added a FreeRTOS+ sub-directory.  The directory contains some FreeRTOS+\n\t  source code, and example projects that use the FreeRTOS Win32 simulator.\n\t+ Added a new example heap allocation implementation (heap_4.c) that\n\t  includes memory block coalescence.\n\t+ Added a demo that targets the Atmel SAM4S Cortex-M4 based microcontroller.\n\t  The demo is preconfigured to build using the free Atmel Studio 6 IDE and\n\t  GCC compiler.\n\t+ Added xSemaphoreTakeFromISR() implementation.\n\t+ The last parameter in ISR safe FreeRTOS queue and semaphore functions\n\t  (xHigherPriorityTaskWoken) is now optional and can be set to NULL if it\n\t  is not required.\n\t+ Update the IAR and MSP430X ports to clear all lower power mode bits before\n\t  exiting the tick interrupt [bug fix].\n\t+ Allow xQueueReset() to be used, even when the queues event lists are not\n\t  empty.\n\t+ Added a vQueueDelete() handler for the FreeRTOS MPU port (this was\n\t  previously missing).\n\t+ Updated the vPortSVCHandler() functions in the FreeRTOS MPU port layer to\n\t  ensure it compiles with the latest ARM GCC compilers from Linaro.\n\t+ Updated the prvReadGP() function in the NIOS II port to ensure the compiler\n\t  can choose any register for the functions parameter (required at high\n\t  compiler optimisation levels).\n\t+ Add #error macros into the Keil and IAR Cortex-M ports to ensure they\n\t  cannot be built if the user has set configMAX_SYSCALL_INTERRUPT_PRIORITY\n\t  to 0.\n\t+ Added comments in the FreeRTOSConfig.h files associated with Cortex-M3 and\n\t  Cortex-M4 demos stating that the configMAX_SYSCALL_INTERRUPT_PRIORITY\n\t  parameter must not be set to 0.\n\t+ Introduce new INCLUDE_xQueueGetMutexHolder configuration constant\n\t  (defaulted to 0).\n\t+ Added two new list handling macros - for internal use only in upcoming new\n\t  products.\n\t+ Removed all mention of the legacy vTaskStartTrace and ulTaskEndTrace\n\t  macros.  FreeRTOS+Trace supersedes the legacy trace.\n\t+ Added a configASSERT() into the vPortFree() function in heap_1.c as it is\n\t  invalid for the function to be called.\n\t+ Made the xRxLock and xTxLock members of the queue structure volatile.\n\t  This is probably not necessary, and is included as a precautionary\n\t  measure.\n\t+ Modify the assert() that checks to see if the priority passed into an\n\t  xTaskCreate() function is within valid bounds to permit the assert to be\n\t  used in the FreeRTOS MPU port.\n\t+ The software timer service (daemon) task is now created in a way that\n\t  to ensure compatibility with FreeRTOS MPU.\n\nChanges between V7.1.0 and V7.1.1 released May 1 2012\n\n\tNew ports:\n\n\tThe following ports are brand new:\n\t+ Cortex-M3 Tasking\n\n\tThe following ports have been available as separate downloads for a number\n\tof months, but are now included in the main FreeRTOS download.\n\t+ Cortex-M0 IAR\n\t+ Cortex-M0 GCC\n\t+ Cortex-M4F GCC (with full floating point support)\n\n\n\tNew demos:\n\n\tThe following demos are brand new:\n\t+ Renesas RX63N RDK (Renesas compiler)\n\n\tThe following demos have been available as separate downloads for a number\n\tof months, but are now included in the main FreeRTOS download.\n\t+ NXP LPC1114 GCC/LPCXpresso\n\t+ ST STM32F0518 IAR\n\t+ Infineon XMC4500 GCC/Atollic\n\t+ Infineon XMC4500 IAR\n\t+ Infineon XMC4500 Keil\n\t+ Infineon XMC4500 Tasking\n\n\n\tKernel miscellaneous / maintenance:\n\n\t+ Introduced the portSETUP_TCB() macro to remove the requirement for the\n\t  Windows simulator to use the traceTASK_CREATE() macro, leaving the trace\n\t  macro available for use by FreeRTOS+Trace (https://www.FreeRTOS.org/trace).\n\t+ Added a new trace macro, traceMOVE_TASK_TO_READY_STATE(), to allow future\n\t  FreeRTOS+Trace versions to provide even more information to users.\n\t+ Updated the FreeRTOS MPU port to be correct for changes that were\n\t  introduced in FreeRTOS V7.1.0.\n\t+ Introduced the xQueueReset() API function.\n\t+ Introduced the xSemaphoreGetMutexHolder() API function.\n\t+ Tidy up various port implementations to add the static key word where\n\t  appropriate, and remove obsolete code.\n\t+ Slight change to the initial stack frame given to the RX600 ports to allow\n\t  them to be used in the Eclipse based E2Studio IDE without confusing GDB.\n\t+ Correct the alignment given to the initial stack of Cortex-M4F tasks.\n\t+ Added a NOP following each DINT instruction on MSP430 devices for strict\n\t  conformance with the instructions on using DINT.\n\t+ Changed the implementation of thread deletes in the Win32 port to prevent\n\t  the port making use of the traceTASK_DELETE() trace macros - leaving this\n\t  macro free for use by FreeRTOS+Trace.\n\t+ Made some benign changes to the RX600 Renesas compiler port layer to\n\t  ensure the code can be built to a library without essential code being\n\t  removed by the linker.\n\t+ Reverted the change in the name of the uxTaskNumber variable made in\n\t  V7.1.0 as it broke the IAR plug-in.\n\n\n\tDemo miscellaneous / maintenance:\n\n\t+ The command interpreter has now been formally released as FreeRTOS+CLI,\n\t  and been moved out of the main FreeRTOS download, to instead be available\n\t  from the FreeRTOS+ Ecosystem site https://www.FreeRTOS.org/plus.\n\t+ flash_timer.c/h has been added to the list of standard demo tasks.  This\n\t  performs the same functionality as the flash.c tasks, but using software\n\t  timers in place of tasks.\n\t+ Upgraded the PIC32 demo as follows:  Changes to how the library functions\n\t  are called necessitated by the new compiler version, addition of MPLAB X\n\t  project with PIC32MX360, PIC32MX460 and PIC32MX795 configurations,\n\t  addition of simply blinky demo, updated FreeRTOSConfig.h to include more\n\t  parameters, addition of hook function stubs.\n\t+ The MSP430X IAR and CCS demos have been updated to ensure the power\n\t  settings are correct for the configured CPU frequency.\n\t+ Rowley CrossWorks projects have been updated to correct the \"multiple\n\t  definition of ...\" warnings introduced when the toolchain was updated.\n\t+ Updated various FreeRTOSConfig.h header files associated with projects\n\t  that build with Eclipse to include a #error statement informing the user\n\t  that the CreateProjectDirectoryStructure.bat batch file needs to be\n\t  executed before the projects can be opened.\n\t+ Renamed directories that included \"CCS4\" in their name to remove the '4'\n\t  and instead just be \"CCS\".  This is because the demo was updated and\n\t  tested to also work with later Code Composer Studio versions.\n\t+ Updated the TCP/IP periodic timer frequency in numerous uIP demos to be\n\t  50ms instead of 500ms.\n\nChanges between V7.0.2 and V7.1.0 released December 13 2011\n\n\tNew ports:\n\n\t+ Cortex-M4F IAR port.\n\t+ Cortex-M4F Keil/RVDS port.\n\t+ TriCore GCC port.\n\n\tNew demos:\n\n\t+ NXP LPC4350 using the Keil MDK, and demonstrated on a Hitex development\n\t  board.\n\t+ ST STM32F407 using the IAR Embedded Workbench for ARM, and demonstrated on\n\t  the IAR STM32F407ZG-SK starter kit.\n\t+ Infineon TriCore TC1782, using the GCC compiler, demonstrated on the\n\t  TriBoard TC1782 evaluation board.\n\t+ Renesas RX630, using the Renesas compiler and HEW, demonstrated on an\n\t  RX630 RSK (Renesas Starter Kit).\n\n\tMiscellaneous / maintenance:\n\n\t+ Removed all calls to printf() from the K60/IAR Kinetis demo so the project\n\t  can execute stand alone - without being connected to the debugger.\n\t+ Completed the command interpreter framework.  Command handlers now receive\n\t  the entire command string, giving them direct access to parameters.\n\t  Utility functions are provided to check the number of parameters, and\n\t  return parameter sub-strings.\n\t+ The previously documented fix for the bug in xTaskResumeFromISR() that\n\t  effected (only) ports supporting interrupt nesting has now been\n\t  incorporated into the main release.\n\t+ The portALIGNMENT_ASSERT_pxCurrentTCB() definition has been added to allow\n\t  specific ports to skip the second stack alignment check when a task is\n\t  created.  This is because the second check is not appropriate for some\n\t  ports - including the new TriCore port where the checked pointer does not\n\t  actually point to a stack.\n\t+ The portCLEAN_UP_TCB() macro has been added to allow port specific clean\n\t  up when a task is deleted - again this is required by the TriCore port.\n\t+ Various other minor changes to ensure warning free builds on a growing\n\t  number of microcontroller and toolchain platforms.  This includes a\n\t  (benign) correction to the prototype of the\n\t  vApplicationStackOverflowHook() definition found in lots of recent demos.\n\n\tTrace system:\n\n\t+ The legacy trace mechanism has been completely removed - it has been\n\t  obsolete for the years since the trace macros were introduced.  The\n\t  configuration constant configUSE_TRACE_FACILITY is now used to optionally\n\t  include additional queue and task information.  The additional information\n\t  is intended to make the trace mechanism more generic, and allow the trace\n\t  output to provide more information.  When configUSE_TRACE_FACILITY is set\n\t  to 1:\n\t\t- the queue structure includes an additional member to hold the queue\n\t\t  type, which can be base, mutex, counting semaphore, binary semaphore\n\t\t  or recursive mutex.\n\t\t- the queue structure includes an additional member to hold a queue\n\t\t  number.  A trace tool can set and query the queue number for its own\n\t\t  purposes.  The kernel does not use the queue number itself.\n\t\t- the TCB structure includes an additional member to hold a task number\n\t\t  number.  A trace tool can set and query the task number for its own\n\t\t  purposes.  The kernel does not use the task number itself.\n\t+ Queues and all types of semaphores are now automatically allocated their\n\t  type as they are created.\n\t+ Added two new trace macros - traceTASK_PRIORITY_INHERIT() and\n\t  traskTASK_PRIORITY_DISINHERIT().\n\t+ Updated the traceQUEUE_CREATE_FAILED() macro to take a parameter that\n\t  indicates the type of queue, mutex, or semaphore that failed to be\n\t  created.\n\t+ The position from which traceCREATE_MUTEX() is called has been moved from\n\t  after the call to xQueueGenericSend() [within the same function] to before\n\t  the call.  This ensures the trace events occur in the correct order.\n\t+ The value passed into tracePRIORITY_SET() has been corrected for the case\n\t  where vTaskPrioritySet() is called with a null parameter.\n\nChanges between V7.0.1 and V7.0.2 released September 20 2011\n\n\tNew ports:\n\n\t+ The official FreeRTOS Renesas RX200 port and demo application have been\n\t  incorporated into the main FreeRTOS zip file download.\n\t+ The official FreeRTOS Renesas RL78 port and demo application have been\n\t  incorporated into the main FreeRTOS zip file download.\n\t+ The official FreeRTOS Freescale Kinetis K60 tower demo application has\n\t  been incorporated into the main FreeRTOS zip file download.  This includes\n\t  an embedded web server example.\n\t+ A new Microblaze V8 port layer has been created to replace the older, now\n\t  deprecated, port layer.  The V8 port supports V8.x of the Microblaze IP,\n\t  including exceptions, caches, and the floating point unit.  A new\n\t  Microblaze demo has also been added to demonstrate the new Microblaze V8\n\t  port layer.  The demo application was created using V13.1 of the Xilinx\n\t  EDK, and includes a basic embedded web server that uses lwIP V1.4.0.\n\t+ The official FreeRTOS Fujitsu FM3 MB9A310 demo application has been\n\t  incorporated into the main FreeRTOS zip file download.  Projects are\n\t  provided for both the IAR and Keil toolchains.\n\n\n\tAPI additions:\n\n\t+ xTaskGetIdleTaskHandle() has been added.\n\t+ xTaskGetTimerDaemonTaskHandle() has been added.\n\t+ pcTaskGetTaskName() has been added.\n\t+ vSemaphoreDelete() macro has been added to make it obvious how to delete\n\t  a semaphore.  In previous versions vQueueDelete() had to be used.\n\t+ vTaskCleanUpResources() has been removed.  It has been obsolete for a\n\t  while.\n\t+ portPOINTER_SIZE_TYPE has been introduced to prevent compiler warnings\n\t  being generated when the size of a pointer does not match the size of\n\t  the stack type.  This will (has already) be used in new ports, but will\n\t  not be retrofitted to existing ports until the existing port itself is\n\t  updated.\n\n\tOther updates and news:\n\n\t+ The core files have all been modified to tighten the coding standard even\n\t  further.  These are style, not functional changes.\n\t+ All ARM7 port layers have been slightly modified to prevent erroneous\n\t  assert() failures when tasks are created and configASSERT() is defined.\n\t+ All ARM IAR projects have been updated to build with the latest V6.2.x\n\t  versions of the IAR Embedded Workbench for ARM tools (EWARM).  This was\n\t  necessary due to a change in the way EWARM uses the CMSIS libraries.\n\t+ The PIC32 port layer has been updated in preparation for V2 of the C32\n\t  compiler.\n\t+ The old Virtex-4 Microblaze demo has been marked as deprecated.  Please\n\t  use the brand new Spartan-6 port and demo in its place.\n\t+ The bones of a new generic command interpreter is located in\n\t  FreeRTOS/Demo/Common/Utils/CommandInterpreter.c.  This is still a work in\n\t  progress, and not documented.  It is however already in use.  It will be\n\t  documented in full when the projects that are already using it are\n\t  completed.\n\t+ A couple of new standard demos have been included.  First, a version of\n\t  flop.c called sp_flop.c.  This is similar to flop.c, but uses single\n\t  precision floats in place of double precision doubles.  This allows the\n\t  for testing ports to processors that have only single precision floating\n\t  point units, and revert to using emulated calculations whenever a double\n\t  is used.  Second, comtest_strings.c has been included to allow the test\n\t  of UART drivers when an entire string is transmitted at once.  The\n\t  previous comtest.c only used single character transmission and reception.\n\t+ lwIP V1.4.0 is now included in the FreeRTOS/Demo/Common directory, and\n\t  used by a couple of new demos.\n\nChanges between V7.0.0 and V7.0.1 released May 13 2011\n\n\t+ Added a Fujitsu FM3 demo application for both the IAR and Keil tool\n\t  chains.\n\t+ Added a SmartFusion demo application for all of the IAR, Keil and\n\t  SoftConsole (GCC/Eclipse) tool chains.\n\t+ Updated the RX600 port and demo applications to take into account the\n\t  different semantics required when using the latest (V1.0.2.0) version of\n\t  the Renesas compiler.\n\t+ Modified the RX600 Ethernet driver slightly to make it more robust under\n\t  heavy load, and updated the uIP handling task to make use of the FreeRTOS\n\t  software timers.\n\t+ Slightly changed the PIC32 port layer to move an ehb instruction in line\n\t  with the recommendations of the MIPS core manual, and ensure 8 byte stack\n\t  alignment is truly always obtained.\n\t+ Changed the behaviour when tasks are suspended before the scheduler has\n\t  been started.  Before, there needed to be at least one task that was not\n\t  in the suspended state.  This is no longer the case.\n\nChanges between V6.1.1 and V7.0.0 released April 8 2011\n\n\tFreeRTOS V7.0.0 is backward compatible with FreeRTOS V6.x.x\n\n\tMain changes:\n\n\t+ Introduced a new software timer implementation.\n\t+ Introduced a new common demo application file to exercise the new timer\n\t  implementation.\n\t+ Updated the Win32/MSVC simulator project to include the new software timer\n\t  demo tasks and software timer tick hook test.  Much simpler software timer\n\t  demonstrations are included in the demo projects for both of the new ports\n\t  (MSP430X with CCS4 and STM32 with TrueStudio).\n\t+ Various enhancements to the kernel implementation in tasks.c.  These are\n\t  transparent to users and do not effect the pre-existing API.\n\t+ Added calls to configASSERT() within the kernel code.  configASSERT() is\n\t  functionally equivalent to the standard C assert() macro, but does not\n\t  rely on the compiler providing assert.h.\n\n\tOther changes:\n\n\t+ Updated the MSP430X IAR port and demo project to include support for the\n\t  medium memory model.\n\t+ Added a demo project for the MSP430X that targets the MSP430X Discovery\n\t  board and uses the Code Composer Studio 4 tools.  This demo includes use\n\t  of the new software timer implementation.\n\t+ Added an STM32F100RB demo project that targets the STM32 Discovery Board\n\t  and uses the TrueStudio Eclipse based IDE from Atollic.\n\t+ Removed some compiler warnings from the PSoC demo application.\n\t+ Updated the PIC32 port layer to ensure the\n\t  configMAX_SYSCALL_INTERRUPT_PRIORITY constant works as expected no matter\n\t  what its value is (within the valid range set by the microcontroller\n\t  kernel).\n\t+ Updated the PIC24, dsPIC and PIC32 projects so they work with the latest\n\t  MPLAB compiler versions from Microchip.\n\t+ Various cosmetic changes to prepare for a standards compliance statement\n\t  that will be published after the software release.\n\n\nChanges between V6.1.0 and V6.1.1 released January 14 2011\n\n\t+ Added two new Windows simulator ports.  One uses the free Microsoft Visual\n\t  Studio 2010 express edition, and the other the free MingW/Eclipse\n\t  environment.  Demo projects are provided for both.\n\t+ Added three demo projects for the PSoC 5 (CYAC5588).  These are for the\n\t  GCC, Keil, and RVDS build tools, and all use the PSoC Creator IDE.\n\t+ Added a demo for the low power STM32L152 microcontroller using the IAR\n\t  Embedded Workbench.\n\t+ Added a new port for the MSP430X core using the IAR Embedded Workbench.\n\t+ Updated all the RX62N demo projects that target the Renesas Demonstration\n\t  Kit (RDK) to take into account the revered LED wiring on later hardware\n\t  revisions, and the new J-Link debug interface DLL.\n\t+ Updated all the RX62N demo projects so the IO page served by the example\n\t  embedded web server works with all web browsers.\n\t+ Updated the Red Suite projects to work with the up coming Red Suite\n\t  release, and to use a more recent version of the CMSIS libraries.\n\t+ Added the traceTAKE_MUTEX_RECURSIVE_FAILED() trace macro.\n\t+ Removed the (pointless) parameter from the traceTASK_CREATE_FAILED()\n\t  trace macro.\n\t+ Introduced the portALT_GET_RUN_TIME_COUNTER_VALUE() macro to compliment\n\t  the already existing portGET_RUN_TIME_COUNTER_VALUE().  This allows for\n\t  more flexibility in how the time base for the run time statistics feature\n\t  can be implemented.\n\t+ Added a \"cpsie i\" instruction before the \"svc 0\" instruction used to start\n\t  the scheduler in each of the Cortex M3 ports.  This is to ensure that\n\t  interrupts are globally enabled prior to the \"svc 0\" instruction being\n\t  executed in cases where interrupts are left disabled by the C start up\n\t  code.\n\t+ Slight optimisation in the run time stats calculation.\n\nChanges between V6.0.5 and V6.1.0 released October 6 2010\n\n\t+ Added xTaskGetTickCountFromISR() function.\n\t+ Modified vTaskSuspend() to allow tasks that have just been created to be\n\t  immediately suspended even when the kernel has not been started.  This\n\t  allows them to effectively start in the Suspended state - a feature that\n\t  has been asked for on numerous occasions to assist with initialisation\n\t  procedures.\n\t+ Added ports for the Renesas RX62N using IAR, GCC and Renesas tool suites.\n\t+ Added a STM32F103 demo application that uses the Rowley tools.\n\t+ Under specific conditions xFreeBytesRemaining within heap_2.c could end up\n\t  with an incorrect\tvalue.  This has been fixed.\n\t+ xTaskCreateGeneric() has a parameter that can be used to pass the handle\n\t  of the task just created out to the calling task.  The assignment to this\n\t  parameter has been moved to ensure it is assigned prior to the newly\n\t  created having any possibility of executing.  This takes into account the\n\t  case where the assignment is made to a global variable that is accessed by\n\t  the newly created task.\n\t+ Fixed some build time compiler warnings in various FreeTCPIP (based on\n\t  uIP) files.\n\t+ Fixed some build time compiler warnings in Demo/Common/Minimal/IntQueue.c.\n\nChanges between V6.0.4 and V6.0.5 released May 17 2010\n\n\t+ Added port and demo application for the Cortus APS3 processor.\n\nChanges between V6.0.3 and V6.0.4 released March 14 2010\n\n\t+ All the contributed files that were located in the Demo/Unsupported_Demos\n\t  directory have been removed.  These files are instead now available in the\n\t  new  Community Contributions section of the FreeRTOS website.  See\n\t  https://www.FreeRTOS.org/RTOS-contributed-ports.html\n\t+ The project file located in the Demo/CORTEX_STM32F107_GCC_Rowley directory\n\t  has been upgraded to use V2.x of the Rowley Crossworks STM32 support\n\t  package.\n\t+ An initial Energy Micro EFM32 demo has been included.  This will be\n\t  updated over the coming months to make better use of the low power modes\n\t  the EFM32 provides.\n\nChanges between V6.0.2 and V6.0.3 released February 26 2010\n\n\t+ SuperH SH7216 (SH2A-FPU) port and demo application added.\n\t+ Slight modification made to the default implementation of\n\t  pvPortMallocAligned() and vPortFreeAligned() macros so by default they\n\t  just call pvPortMalloc() and vPortFree().  The macros are only needed to\n\t  be defined when a memory protection unit (MPU) is being used - and then\n\t  only depending on other configuration settings.\n\nChanges between V6.0.1 and V6.0.2 released January 9th 2010\n\n\t+ Changed all GCC ARM 7 ports to use 0 as the SWI instruction parameter.\n\t  Previously the parameter was blank and therefore only an implicit 0 but\n\t  newer GCC releases do not permit this.\n\t+ Updated IAR SAM7S and SAM7X ports to work with IAR V5.40.\n\t+ Changed the stack alignment requirement for PIC32 from 4 bytes to 8 bytes.\n\t+ Updated prvListTaskWithinSingleList() is it works on processors where the\n\t  stack grows up from low memory.\n\t+ Corrected some comments.\n\t+ Updated the startup file for the RVDS LPC21xx demo.\n\nChanges between V6.0.0 and V6.0.1 released November 15th 2009\n\n\t+ Altered pxPortInitialiseStack() for all Cortex-M3 ports to ensure the\n\t  stack pointer is where the compiler expects it to be when a task first\n\t  starts executing.\n\n\t  The following minor changes only effect the Cortex-M3 MPU port:\n\n\t+ portRESET_PRIVILEGE() assembly macro updated to include a clobber list.\n\t+ Added prototypes for all the privileged function wrappers to ensure no\n\t  compile time warnings are generated no matter what the warning level\n\t  setting.\n\t+ Corrected the name of portSVC_prvRaisePrivilege to\n\t  portSVC_RAISE_PRIVILEGE.\n\t+ Added conditional compilation into xTaskGenericCreate() to prevent some\n\t  compilers issuing warnings when portPRIVILEGE_BIT is defined as zero.\n\n\nChanges between V5.4.2 and V6.0.0 released October 16th 2009\n\n\tFreeRTOS V6 is backward compatible with FreeRTOS V5.x.\n\n\tMain changes:\n\n\t+ FreeRTOS V6 is the first version to include memory protection unit (MPU)\n\t  support.  Two ports now exist for the Cortex M3, the standard FreeRTOS\n\t  which does not include MPU support, and FreeRTOS-MPU which does.\n\t+ xTaskCreateRestricted() and vTaskAllocateMPURegions() API functions added\n\t  in support of FreeRTOS-MPU.\n\t+ Wording for the GPL exception has been (hopefully) clarified.  Also the\n\t  license.txt file included in the download has been fixed (the previous\n\t  version contained some corruption).\n\n\tOther changes:\n\n\t+ New API function xPortGetFreeHeapSize() added to heap_1.c and heap_2.c.\n\t+ ARM7 GCC demo interrupt service routines wrappers have been modified to\n\t  call the C portion using an __asm statement.  This prevents the function\n\t  call being inlined at higher optimisation levels.\n\t+ ARM7 ports now automatically set the THUMB bit if necessary when\n\t  setting up the initial stack of a task - removing the need for\n\t  THUMB_INTERWORK to be defined.  This also allows THUMB mode and ARM mode\n\t  tasks to be mixed more easily.\n\t+ All ARM7/9 ports now have portBYTE_ALIGNMENT set to 8 by default.\n\t+ Various demo application project files have been updated to be up to date\n\t  with the latest IDE versions.\n\t+ The linker scripts used with command line GCC demos have been updated to\n\t  include an eh_frame section to allow their use with the latest Yagarto\n\t  release.  Likewise the demo makefiles have been updated to include\n\t  command line options to reduce or eliminate the eh_frame section all\n\t  together.\n\t+ The definition of portBYTE_ALIGNMENT_MASK has been moved out of the\n\t  various memory allocation files and into the common portable.h header\n\t  file.\n\t+ Removed unnecessary use of portLONG, portSHORT and portCHAR.\n\t+ Added LM3Sxxxx demo for Rowley CrossWorks.\n\t+ Posix simulator has been upgraded - see the corresponding WEB page on the\n\t  FreeRTOS.org site.\n\n\nChanges between V5.4.1 and V5.4.2 released August 9th 2009\n\n\t+ Added a new port and demo app for the Altera Nios2 soft core.\n\t+ Added LPC1768 demo for IAR.\n\t+ Added a USB CDC demo to all LPC1768 demos (Code Red, CrossWorks and IAR).\n\t+ Changed clock frequency of LPC1768 demos to 99MHz.\n\nChanges between V5.4.0 and V5.4.1 released July 25th 2009\n\n\t+ New hook function added.  vApplicationMallocFailedHook() is (optionally)\n\t  called if pvPortMalloc() returns NULL.\n\t+ Additional casting added to xTaskCheckForTimeOut().  This prevents\n\t  problems that can arise should configUSE_16_BIT_TICKS be set to 1 on a\n\t  32 bit architecture (which would probably be a mistake, anyway).\n\t+ Corrected the parameter passed to NVIC_SetPriority() to set the MAC\n\t  interrupt priority in both LPC1768 demos.\n\t+ Decreased the default setting of configMINIMAL_STACK_SIZE in the PIC32\n\t  demo application to ensure the heap space was not completely consumed\n\t  before the scheduler was started.\n\nChanges between V5.3.1 and V5.4.0 released July 13th 2009\n\n\t+ Added Virtex5 / PPC440 port and demos.\n\t+ Replaced the LPC1766 Red Suite demo with an LPC1768 Red Suite demo.  The\n\t  original demo was configured to use engineering samples of the CPU.  The\n\t  new demo has an improved Ethernet driver.\n\t+ Added LPC1768 Rowley demo with zero copy Ethernet driver.\n\t+ Reworked byte alignment code to ensure 8 byte alignment works correctly.\n\t+ Set configUSE_16_BIT_TICKS to 0 in the PPC405 demo projects.\n\t+ Changed the initial stack setup for the PPC405 to ensure the small data\n\t  area pointers are setup correctly.\n\nChanges between V5.3.0 and V5.3.1 released June 21st 2009\n\n\t+ Added ColdFire V1 MCF51CN128 port and WEB server demo.\n\t+ Added STM32 Connectivity Line STM32107 Cortex M3 WEB server demo.\n\t+ Changed the Cortex M3 port.c asm statements to __asm so it can be\n\t  compiled using Rowley CrossWorks V2 in its default configuration.\n\t+ Updated the Posix/Linux simulator contributed port.\n\nChanges between V5.2.0 and V5.3.0 released June 1st 2009\n\n\tMain changes:\n\n\t+ Added new (optional) feature that gathers statistics on the amount of CPU\n\t  time used by each task.\n\t+ Added a new demo application for the Atmel AT91SAM3U Cortex-M3 based\n\t  microcontroller.\n\t+ Added a new demo application for the NXP LPC1766 Cortex-M3 based\n\t  microcontroller.\n\t+ Added a contributed port/demo that allows FreeRTOS to be 'simulated' in a\n\t  Linux environment.\n\n\tMinor changes:\n\t+ Updated the Stellaris uIP WEB server demos to include the new run time\n\t  statistics gathering feature - and include a served WEB page that\n\t  presents the information in a tabular format.\n\t+ Added in the lwIP port layer for the Coldfire MCF52259.\n\t+ Updated the CrossWorks LPC2368 WEB server to include an image in the\n\t  served content.\n\t+ Changed some of the timing in the initialisation of the LPC2368 MAC to\n\t  permit its use on all part revisions.\n\t+ Minor modifications to the core uIP code to remove some compiler warnings.\n\t+ Added xTaskGetApplicationTaskTag() function and updated the OpenWatcom\n\t  demo to make use of the new function.\n\t+ Added contributed demos for AVR32 AP7000, STM32 Primer 2 and STM32 using\n\t  Rowley Crossworks.\n\t+ Heap_1.c and Heap_2.c used to define structures for the purpose of data\n\t  alignment.  These have been converted to unions to save a few bytes of\n\t  RAM that would otherwise be wasted.\n\t+ Remove the call to strncpy() used to copy the task name into the TCB when\n\t  the maximum task name is configured to be 1 byte long.\n\nChanges between V5.1.2 and V5.2.0 released March 14th 2009\n\n\t+ Optimised the queue send and receive functions (also used by semaphores).\n\t+ Replaced the standard critical sections used to protect BIOS calls in the\n\t  PC port to instead use scheduler locks.  This is because the BIOS calls\n\t  always return with interrupts enabled.\n\t+ Corrected unclosed comments in boot.s.\n\nChanges between V5.1.1 and V5.1.2 released February 9th 2009\n\n\t+ Added NEC V850ES port and demo.\n\t+ Added NEC 78K0R port and demo.\n\t+ Added MCF52259 port and demo.\n\t+ Added the AT91SAM9XE port and demo.\n\t+ Updated the MCF52233 FEC driver to work around a silicon bug that\n\t  prevents the part auto negotiating some network parameters.\n\t+ Minor modifications to the MCF52233 makefile to permit it to be used\n\t  on Linux hosts.\n\t+ Updated the STM32 primer files to allow them to be built with the latest\n\t  version of the RIDE tools.\n\t+ Updated the threads.js Java script used for kernel aware debugging in\n\t  the Rowley CrossWorks IDE.\n\n\nChanges between V5.1.0 and V5.1.1 released November 20, 2008\n\n\t+ Added Coldfire MCF52233 WEB server demo using GCC and Eclipse.\n\t+ Added IAR MSP430 port and demo.\n\t+ Corrected several compiler time issues that had crept in as tool versions\n\t  change.\n\t+ Included FreeRTOS-uIP - a faster uIP.  This is not yet complete.\n\nChanges between V5.0.4 and V5.1.0 released October 24, 2008\n\n\t+ Added a new port and demo application for the ColdFire V2 core using the\n\t  CodeWarrior development tools.\n\t+ Replaced the ARM7 demo that used the old (and now no longer supported)\n\t  Keil compiler with a new port that uses the new Keil/RVDS combo.\n\t+ Stack overflow checking now works for stacks that grow up from low\n\t  memory (PIC24 and dsPIC).\n\t+ BUG FIX - set the PIC32 definition of portSTACK_GROWTH to the correct\n\t  value of -1.\n\t+ MSP430 port layers have been updated to permit tasks to place the\n\t  microcontroller into power down modes 1 to 3.  The demo applications have\n\t  likewise been updated to demonstrate the new feature.\n\t+ Replaced the two separate MSP430/Rowley port layers with a single and more\n\t  flexible version.\n\t+ Added more contributed ports, including ports for NEC and SAM9\n\t  microcontrollers.\n\t+ Changed the linker script used in the LPC2368 Eclipse demo.\n\nChanges between V5.0.3 and V5.0.4 released September 22, 2008\n\n\t+ Completely re-written port for ColdFire GCC.\n\t+ Bug fix:  All Cortex M3 ports have a minor change to the code that sets\n\t  the pending interrupt.\n\t+ Some header files require that FreeRTOS.h be included prior to their\n\t  inclusion.  #error message have been added to all such header file\n\t  informing users to the cause of the compilation error should the headers\n\t  not be included in the correct order.\n\nChanges between V5.0.2 and V5.0.3 released July 31, 2008\n\n\tChanges relating to the Cortex M3:\n\n\t+ Added configMAX_SYSCALL_INTERRUPT_PRIORITY usage to all the Cortex M3\n\t  ports and demos.  See the port documentation pages on the FreeRTOS.org\n\t  WEB site for full usage information.\n\t+ Improved efficiency of Cortex M3 port even further.\n\t+ Ensure the Cortex M3 port works no matter where the vector table is\n\t  located.\n\t+ Added the IntQTimer demo/test tasks to a demo project for each CM3 port\n\t  (Keil, GCC and IAR) to test the new configMAX_SYSCALL_INTERRUPT_PRIORITY\n\t  functionality.\n\t+ Added the mainINCLUDE_WEB_SERVER definition to the LM3SXXXX IAR and Keil\n\t  projects to allow the WEB server to be conditionally excluded from the\n\t  build and therefore allow use of the KickStart (code size limited)\n\t  compiler version.\n\n\tOther changes:\n\n\t+ Moved the PIC24 and dsPIC versions of vPortYield() from the C file to\n\t  an assembly file to allow use with all MPLAB compiler versions.  This also\n\t  allows the omit-frame-pointer optimisation to be turned off.\n\nChanges between V5.0.0 and V5.0.2 released May 30, 2008\n\n\t+ Updated the PIC32 port to allow queue API calls to be used from\n\t  interrupts above the kernel interrupt priority, and to allow full\n\t  interrupt nesting.  Task stack usages has also been reduced.\n\t+ Added a new PowerPC port that demonstrates how the trace macros can be\n\t  used to allow the use of a floating point co-processor.  The\n\t  traceTASK_SWITCHED_OUT() and traceTASK_SWITCHED_INT() macros are used to\n\t  save and restore the floating point context respectively for those tasks\n\t  that actually use floating point operations.\n\t+ BUG FIX:  The first PPC405 port contained a bug in that it did not leave\n\t  adequate space above the stack for the backchain to be saved when a task\n\t  started to execute for the first time.\n\t+ Updated queue.c to add in the means to allow interrupt nesting and for\n\t  queue API functions to be called from interrupts that have a priority\n\t  above the kernel priority.  This is only supported on PIC32 ports thus\n\t  far.\n\t+ Fixed the compiler warnings that were generated when the latest version\n\t  of WinAVR was used.\n\t+ Remove all inline usage of 'inline' from the core kernel code.\n\t+ Added the queue registry feature.  The queue registry is provided as a\n\t  means for kernel aware debuggers to locate queue definitions.  It has no\n\t  purpose unless you are using a kernel aware debugger.  The queue registry\n\t  will only be used when configQUEUE_REGISTRY_SIZE is greater than zero.\n\t+ Added the ST Cortex-M3 drivers into the Demo/Common/Drivers directory to\n\t  prevent them from having to be included in multiple demos.\n\t+ Added a Keil STM32 demo application.\n\t+ Changed the blocktim.c test files as it is no longer legitimate for all\n\t  ports to call queue API functions from within a critical section.\n\t+ Added the IntQueue.c test file to test the calling of queue API functions\n\t  from different interrupt priority levels, and test interrupt nesting.\n\nChanges between V5.0.0 and V5.0.1\n\n\t+ V5.0.1 was a customer specific release.\n\nChanges between V4.8.0 and V5.0.0 released April 15, 2008\n\n\t*** VERY IMPORTANT INFORMATION ON UPGRADING TO FREERTOS.ORG V5.0.0 ***\n\n\tThe parameters to the functions xQueueSendFromISR(), xQueueSendToFrontFromISR(),\n\txQueueSendToBackFromISR() and xSemaphoreGiveFromISR() have changed.  You must\n\tupdate all calls to these functions to use the new calling convention!  Your\n\tcompiler might not issue any type mismatch warnings!\n\n\n\tOther changes:\n\n\t+ Support added for the new Luminary Micro LM3S3768 and LM3S3748 Cortex-M3\n\t  microcontrollers.\n\t+ New task hook feature added.\n\t+ PowerPC demo updated to use version 10.1 of the Xilinx EDK.\n\t+ Efficiency gains within the PIC32 port layer.\n\nChanges between V4.7.2 and V4.8.0 released March 26 2008\n\n\t+ Added a Virtex4 PowerPC 405 port and demo application.\n\t+ Added optional stack overflow checking and new\n\t  uxTaskGetStackHighWaterMark() function.\n\t+ Added new xQueueIsQueueEmptyFromISR(), xQueueIsQueueFullFromISR() and\n\t  uxQueueMessagesWaitingFromISR() API functions.\n\t+ Efficiency improvements to the Cortex-M3 port layer.  NOTE: This\n\t  requires that an SVC handler be installed in the application.\n\t+ Efficiency improvements to the queue send and receive functions.\n\t+ Added new trace macros.  These are application definable to provide\n\t  a flexible trace facility.\n\t+ Implemented the configKERNEL_INTERRUPT_PRIORITY within the Keil Cortex\n\t  M3 port layer (bringing it up to the same standard as the IAR and GCC\n\t  versions).\n\t+ Ports that used the arm-stellaris-eabi-gcc tools have been converted to\n\t  use the arm-non-eabi-gcc tools.\n\nChanges between V4.7.1 and V4.7.2 released February 21, 2008\n\n\t+ Added Fujitsu MB91460 port and demo.\n\t+ Added Fujitsu MB96340 port and demo.\n\t+ Tidied up the capitalisation of include files to facilitate builds on\n\t  Linux hosts.\n\t+ Removed some redundant casting that was generating warnings - but was\n\t  included to remove warnings on other compilers.\n\nChanges between V4.7.0 and V4.7.1 released February 3, 2008\n\n\t+ Updated all IAR ARM projects to use V5.11 of the IAR Embedded Workbench\n\t  for ARM.\n\t+ Introduced recursive semaphore feature.\n\t+ Updated LPC2368 demos to take into account silicon bugs in old chip\n\t  revisions.\n\t+ Updated STR9 uIP port to manually set the net mask and gateway addresses.\n\t+ Updating demos to allow more to run with the co-operative scheduler.\n\t+ Fixed co-operative scheduler behaviour upon the occurrence of a tick\n\t  interrupt while the scheduler was suspended.\n\t+ Updated documentation contained within semphr.h.\n\t+ ARM7 GCC ports no longer use the IRQ attribute.\n\nChanges between V4.6.1 and V4.7.0 released December 6, 2007\n\n\t+ Introduced the counting semaphore macros and demo source files.  The\n          Open Watcom PC project has been updated to include the new demo.  See\n          the online documentation for more information.\n\t+ Introduced the 'alternative' queue handling API and demo source files.\n\t  The Open Watcom PC project has been updated to include the new demo\n\t  source files.  See the online documentation for more information.\n\t+ Added AT91SAM7X Eclipse demo project.\n\t+ Added the STM32 primer demo project for the GCC compiler and Ride IDE.\n\t+ Removed the .lock files that were mistakenly included in the V4.6.1\n\t  eclipse workspaces.\n\nChanges between V4.6.0 and V4.6.1 released November 5 2007\n\n\t+ Added support for the MIPS M4K based PIC32.\n\t+ Added 'extern \"C\"' to all the header files to facilitate use with C++.\n\nChanges between V4.5.0 and V4.6.0 released October 28 2007\n\n\t+ Changed the method used to force a context switch within an ISR for the\n\t  ARM7/9 GCC ports only.  The portENTER_SWITCHING_ISR() and\n\t  portEXIT_SWITCHING_ISR() macros are no longer supported.  This is to\n\t  ensure correct behaviour no matter which GCC version is used, with or\n\t  without the -fomit-frame-pointer option, and at all optimisation levels.\n\t+ Corrected the prototype for xQueueGenericSend() within queue.h.\n\nChanges between V4.4.0 and V4.5.0 released September 17 2007\n\n\t+ Added the xQueueSendToFront(), xQueueSendToBack() and xQueuePeek()\n\t  functionality.  These should now be used in preference to the old\n\t  xQueueSend() function - which is maintained for backward compatibility.\n\t+ Added Mutex functionality.  The behaviour of mutexes is subtly different\n\t  to the already existing binary semaphores as mutexes automatically\n\t  include a priority inheritance mechanism.\n\t+ Added the GenQTest.c and QPeek.c to test and demonstrate the behaviour\n\t  of the new functionality.\n\t+ Updated the LM3Sxxxx and PC ports to include the new GenQTest.c and\n\t  QPeek.c files.\n\t+ Updated the GCC port for the Cortex M3 to include the\n\t  configKERNEL_INTERRUPT_PRIORITY functionality.  This was previously only\n\t  included in the IAR port.\n\t+ Optimised the GCC and IAR port layer code - specifically the context\n\t  switch code.\n\t+ Consolidated the LM3Sxxxx EK demos for all development tools into a\n\t  single project that automatically detects which version of the EK the\n\t  application is executing on.\n\t+ Added Eclipse support for LM3Sxxxx evaluation kits.\n\t+ Added Eclipse support for the Keil LPC2368 evaluation kit.\n\t+ Added the Demo/Drivers directory to hold code that is common to multiple\n\t  demo application projects.\n\t+ Included some minor bug fixes in the uIP 1.0 code.\n\t+ Added an lwIP demo for the STR9 - thanks ST for assistance.\n\t+ Updated the AVR32 port to ensure correct behaviour with full compiler\n\t  optimisation.\n\t+ Included binaries for OpenOCD FTDI and parallel port interfaces.\n\nChanges between V4.4.0 and V4.3.1 released July 31, 2007\n\n\t+ Added AVR32 UC3B demo application.\n\t+ Updated AVR32 UC3A port and demo applications.\n\t+ Added IAR lwIP demo for AVR32 UC3A.\n\t+ Updated listGET_OWNER_OF_NEXT_ENTRY() to assist compiler optimisation\n\t  (thanks Niu Yong for making the suggestion).\n\t+ Added xTaskGetSchedulerState() API function.\n\t+ BUG FIX:  Corrected behaviour when tasks that are blocked indefinitely\n\t  have their block time adjusted (within xQueueSend() and xQueueReceive()),\n\t  and are the subject of a call the vTaskResume() when they are not\n\t  actually in the Suspended state (thanks Dan Searles for reporting the\n\t  issues).\n\n\nChanges between V4.3.0 and V4.3.1 released June 11, 2007\n\n\t+ Added STMicroelectronics STM32 Cortex-M3 demo application.\n\t+ Updated ustdlib.c for the GCC LM3S6965 demo.\n\nChanges between V4.2.1 and V4.3.0 released June 5, 2007\n\n\t+ Introduced configKERNEL_INTERRUPT_PRIORITY to the IAR Cortex-M3, PIC24\n\t  and dsPIC ports.  See the LM3S6965 and PIC24 demo application\n\t  documentation pages for more information.\n\t+ Updated the PIC24 and dsPIC demos to build with V3.0 of the PIC30 GCC\n\t  tools, and changed the demo applications.\n\t+ Added demos for the new Ethernet and CAN enabled Luminary Micro Stellaris\n\t  microcontrollers.\n\t+ Corrected bug in uIP the demos that prevented frames of approximately 1480\n\t  bytes and over from being transmitted.\n\t+ Included the LPC2368/uIP/Rowley demo into the main FreeRTOS.org\n\t  download.\n\t+ Update to WizC PIC18 port to permit its use with version 14 of the\n\t  compiler.  Thanks Marcel!\n\nChanges between V4.2.1 and V4.2.0 released April 2, 2007\n\n\t+ Added AVR32 AT32UC3A ports for GCC and IAR.\n\t+ Added -fomit-frame-pointer option to lwIP SAM7X demo makefile.\n\t+ Moved location of call to LCD_Init() in STR9 demo to ensure it is only\n\t  called after the scheduler has been started.\n\nChanges between V4.1.3 and V4.2.0 released February 8, 2007\n\n\t+ Changes to both task.c and queue.c as a result of testing performed on\n\t  the SafeRTOS code base.\n\t+ Added Cortex-M3 LM3S811 demos for GCC and IAR tools.\n\nChanges between V4.1.2 and V4.1.3 released November 19, 2006\n\n\t+ Added STR750 ARM7 port using the Raisonance RIDE/GCC tools.\n\t+ Added -fomit-frame-pointer option to Rowley ARM7 demos as work around\n\t  to GCC bug at some optimisation levels.\n\t+ Altered the way the heap is defined in the LM3S811 Keil demo to prevent\n\t  the RAM usage from counting toward the code size limit calculation.\n\t+ CO-ROUTINE BUG FIX:  Removed the call to prvIsQueueEmpty from within\n\t  xQueueCRReceive as it exited with interrupts enabled.  Thanks Paul Katz.\n\t+ Tasks that block on events with a timeout of portMAX_DELAY are now\n\t  blocked indefinitely if configINCLUDE_vTaskSuspend is defined.\n\t  Previously portMAX_DELAY was just the longest block time possible. This\n\t  is still the case if configINCLUDE_vTaskSuspend is not defined.\n\t+ Minor changes to some demo application files.\n\nChanges between V4.1.1 and V4.1.2 released October 21, 2006\n\n\t+ Added 16bit PIC ports and demos.\n\t+ Added STR750 port and demo.\n\n\nChanges between V4.1.0 and V4.1.1 released September 24, 2006\n\n\t+ Added the Luminary Micro Stellaris LM3S811 demo application.\n\nChanges between V4.0.5 and V4.1.0 released August 28, 2006\n\n\t+ Prior to V4.1.0, under certain documented circumstances, it was possible\n\t  for xQueueSend() and xQueueReceive() to return without having completed\n\t  and without their block time expiring.  The block time effectively\n\t  stated a maximum block time, and the return value of the function needed\n\t  to be checked to determine the reason for returning.  This is no longer\n\t  the case as the functions will only return once the block time has\n\t  expired or they are able to complete their operation.  It is therefore no\n\t  longer necessary to wrap calls within loops.\n\t+ Changed the critical section handling in the IAR AVR port to correct the\n\t  behaviour when used with later compiler versions.\n\t+ Added the LPC2138 CrossWorks demo into the zip file.  Previously this was\n\t  only available as a separate download.\n\t+ Modified the AVR demo applications to demonstrate the use of co-routines.\n\nChanges between V4.0.4 and V4.0.5 released August 13, 2006\n\n\t+ Introduced API function xTaskResumeFromISR().  Same functionality as\n\t  xTaskResume(), but can be called from within an interrupt service routine.\n\t+ Optimised vListInsert() in the case when the wake time is the maximum\n\t  tick count value.\n\t+ Bug fix:  The 'value' of the event list item is updated when the priority\n\t  of a task is changed.  Previously only the priority of the TCB itself was\n\t  changed.\n\t+ vTaskPrioritySet() and vTaskResume() no longer use the event list item.\n\t  This has not been necessary since V4.0.1 when the xMissedYield handling\n\t  was added.\n\t+ Lowered the PCLK setting on the ARM9 STR9 demo from 96MHz to 48MHz.\n\t+ When ending the scheduler - do not try to attempt a context switch when\n\t  deleting the current task.\n\t+ SAM7X EMAC drivers:  Corrected the Rx frame length mask when obtaining\n\t  the length from the rx descriptor.\n\n\nChanges between V4.0.3 and V4.0.4 released June 22, 2006\n\n\t+ Added a port and demo application for the STR9 ARM9 based processors from\n\t  ST.\n\t+ Slight optimisation to the vTaskPrioritySet() function.\n\t+ Included the latest uIP version (1.0) in the demo/common/ethernet\n\t  directory.\n\nChanges between V4.0.2 and V4.0.3 released June 7, 2006\n\n\t+ Added a port and demo application for the Cortex-M3 target using the IAR\n\t  development tools.\n\t+ The ARM Cortex-m3 Rowley projects have been updated to use V1.6 of the\n\t  CrossStudio tools.\n\t+ The heap size defined for the lwIP Rowley demo has been reduced so that\n\t  the project will link correctly when using the command line GCC tools\n\t  also.  The makefile has also been modified to allow debugging.\n\t+ The lwIP Rowley demo not includes a 'kernel aware' debug window.\n\t+ The uIP Rowley project has been updated to build with V1.6 of CrossWorks.\n\t+ The second set of tasks in the blockQ demo were created the wrong way\n\t  around (inconsistent to the description in the file).  This has been\n\t  corrected.\n\nChanges between V4.0.1 and V4.0.2 released May 28, 2006\n\n\t+ Port and demo application added for the Tern Ethernet Engine controller.\n\t+ Port and demo application added for MC9S12 using GCC, thanks to\n\t  Jefferson \"imajeff\" Smith.\n\t+ The function vTaskList() now suspends the scheduler rather than disabling\n\t  interrupts during the creation of the task list.\n\t+ Allow a task to delete itself by passing in its own handle.  Previously\n\t  this could only be done by passing in NULL.\n\t+ Corrected the value passed to the WDG_PeriodValueConfig() library\n\t  function in the STR71x demo.\n\t+ The tick hook function is now called only within a tick isr.  Previously\n\t  it was also called when the tick function was called during the scheduler\n\t  unlocking process.\n\t+ The EMAC driver in the SAM7X lwIP demo has been made more robust as per\n\t  the thread: https://sourceforge.net/forum/message.php?msg_id=3714405\n\t+ In the PC ports:  Add function prvSetTickFrequencyDefault() to set the\n\t  DOS tick back to its proper value when the scheduler exits.  Thanks\n\t  Raynald!\n\t+ In the Borland x86 ports there was a mistake in the portFIRST_CONTEXT\n\t  macro where the BP register was not popped from the stack correctly.  The\n\t  BP value would never get used so this did not cause a problem, but it has\n\t  been corrected all the same.\n\n\nChanges between V4.0.0 and V4.0.1 released April 7 2006\n\n\t+ Improved the ARM CORTEX M3 ports so they now only have to service\n\t  pendSV interrupts.\n\t+ Added a Luminary Micro port and demo for use with Rowley CrossWorks.\n\t+ Added the xMissedYield handling to tasks.c.\n\nChanges between V3.2.4 and V4.0.0\n\n\tMajor changes:\n\n\t+ Added new RTOS port for Luminary Micros ARM CORTEX M3 microcontrollers.\n\t+ Added new co-routine functionality.\n\n\tOther kernel changes:\n\n\t+ An optional tick hook call is now included in the tick function.\n\t+ Introduced the xMiniListItem structure and removed the list pxHead\n\t  member in order to reduce RAM usage.\n\t+ Added the following definitions to the FreeRTOSConfig.h file included\n\t  with every port:\n\t\tconfigUSE_TICK_HOOK\n\t\tconfigUSE_CO_ROUTINES\n\t\tconfigMAX_CO_ROUTINE_PRIORITIES\n\t+ The volatile qualification has been changed on the list members to allow\n\t  the task.c code to be tidied up a bit.\n\t+ The scheduler can now be started even if no tasks have been created!\n\t  This is to allow co-routines to run when there are no tasks.\n\t+ A task being woken by an event will now preempt the currently running task\n\t  even if its priority is only equal to the currently running task.\n\n\tPort and demo application changes:\n\n\t+ Updated the WinAVR demo to compile with the latest version of WinAVR\n\t  with no warnings generated.\n\t+ Changed the WinAVR makefile to make chars signed - needed for the\n\t  co-routine code if BaseType_t is set to char.\n\t+ Added new demo application file crflash.c.  This demonstrates co-routine\n\t  functionality including passing data between co-routines.\n\t+ Added new demo application file crhook.c.  This demonstrates co-routine\n\t  and tick hook functionality including passing data between and ISR and\n\t  a co-routine.\n\t+ Some NOP's were missing following stmdb{}^ instructions in various ARM7\n\t  ports.  These have been added.\n\t+ Updated the Open Watcom PC demo project to include the crflash and crhook\n\t  demo co-routines as an example of their use.\n\t+ Updated the H8S demo to compile with the latest version of GCC.\n\t+ Updated the SAM7X EMAC drivers to take into account the hardware errata\n\t  regarding lost packets.\n\t+ Changed the default MAC address used by some WEB server demos as the\n\t  original addresses used was not liked by some routers.\n\t+ Modified the SAM7X/IAR startup code slightly to prevent it hanging on\n\t  some systems when the code is executed using a j-link debugger.  The\n\t  j-link macro file configures the PLL before the code executes so\n\t  attempting to configure it again in the startup code was causing a\n\t  problem for some user.  Now a check is performed first to see if the\n\t  PLL is already set up.\n\t+ GCC port now contain all assembler code in a single asm block rather than\n\t  individual blocks as before.\n\t+ GCC LPC2000 code now explicitly uses R0 rather than letting the assembler\n\t  choose the register to use as a temporary register during the context\n\t  switch.\n\t+ Added portNOP() macro.\n\t+ The compare match load value on LPC2000 ports now has 1 added to correct\n\t  the value used.\n\t+ The minimal stack depth has been increased slightly on the WIZC PIC18\n\t  port.\n\nChanges between V3.2.3 and V3.2.4\n\n\t+ Modified the GCC ARM7 port layer to allow use with GCC V4.0.0 and above.\n\t  Many thanks to Glen Biagioni for the provided update.\n\t+ Added a new Microblaze port and demo application.\n\t+ Modified the SAM7X EMAC demo to default to use the MII interface rather\n\t  than the RMII interface.\n\t+ Modified the startup sequence of the SAM7X demo slightly to allow the\n\t  EMAC longer to auto negotiate.\n\nChanges between V3.2.2 and V3.2.3\n\n\t+ Added MII interface support to the SAM7X EMAC peripheral driver.\n\t  Previously versions worked with the RMII interface only.\n\t+ Added command line GCC support to the SAM7X lwIP demo.  Previously the\n\t  project could only be built using the CrossWorks IDE.  Modifications to\n\t  this end include the addition of a standard makefile and linker script to\n\t  the download, and some adjustments to the stacks allocated to each task.\n\t+ Changed the page returned by the lwIP WEB server demo to display the\n\t  task status table rather than the TCP/IP statistics.\n\t+ Corrected the capitalisation of some header file includes and makefile\n\t  dependencies to facilitate use on Linux host computers.\n\t+ The various LPC2000 ports had a mistake in the timer setup where the\n\t  prescale value was written to T0_PC instead of T0_PR.  This would have\n\t  no effect unless a prescale value was actually required.  This has been\n\t  corrected.\n\nChanges between V3.2.1 and V3.2.2 - Released 23 September, 2005\n\n\t+ Added an IAR port for the Philips LPC2129\n\t+ The Atmel ARM7 IAR demo project files are now saved in the IAR Embedded\n\t  Workbench V4.30a format.\n\t+ Updated the J-Link macro file included with the SAM7X uIP demo project\n\t  to allow the demo board to be reset over the J-Link.\n\nChanges between V3.2.0 and V3.2.1 - Released 1 September, 2005\n\n\t+ Added lwIP demo for AT91SAM7X using Rowley tools.\n\t+ Added uIP demo for AT91SAM7X using IAR tools.\n\t+ Added function xTaskGetCurrentTaskHandle().\n\t+ Renamed events.h to mevents.h to prevent it conflicting with the events.h\n\t  generated automatically by the HCS12 processor expert utility.  events.h\n\t  is only used by the PC demo application.\n\t+ Both PIC18 ports now initialise the TBLPTRU to 0 as this is the value\n\t  expected by the compiler, and the compilers do not write to this\n\t  register.\n\t+ The HCS12 banked model demo now creates the 'suicide' tasks immediately\n\t  prior to starting the scheduler.  These tasks should be the last tasks to\n\t  get started in order for the test to function correctly.\n\nChanges between V3.1.1 and V3.2.0 - Released 29 June, 2005\n\n\tV3.2.0 introduces two new MSP430 ports and corrects a minor kernel\n\tissues.  Thanks to Ares.qi for his input.\n\n\t+ Added two MSP430 ports that use the Rowley CrossWorks development tools.\n\t  One port just mirrors the existing GCC port.  The other port was provided\n\t  by Milos Prokic.  Thanks!\n\t+ V3.2.0 corrects the behavior when vTaskPrioritySet() or vTaskResume()\n\t  are called while the scheduler is locked (by a call to\n\t  vTaskSuspendAll()).  When this is done the subject task now starts to\n\t  execute immediately when the scheduler is unlocked if it has the highest\n\t  priority that is ready to run.  Previously there was a possibility that\n\t  the task would not run until the next RTOS tick or call to portYIELD().\n\t+ Another similar small correction ensures that in the case where more than\n\t  one task is blocked on a semaphore or queue, the task with the highest\n\t  priority is guaranteed to be unblocked first.\n\t+ Added a couple of more test tasks to the PC demo which cover the points\n\t  above.\n\nChanges between V3.1.0 and V3.1.1 - Released 21st June, 2005\n\n\tThis release updates the HCS12 port.  The common kernel code\n\tremains unchanged.\n\n\t+ Updated the HCS12 port to support banking and introduced a demo\n\t  application for the MC9S12DP256.  The new demo application is\n\t  located in the Demo/HCS12_CodeWarrior_banked directory.\n\t+ The name of the directory containing the MC9S12F32 demo application\n\t  has been changed to Demo/HCS12_CodeWarrior_small (as in 'small'\n\t  memory model).\n\t+ MC9S12F32 demo updated slightly to use the PLL.  The CPU speed for the\n\t  demo application is now 24MHz.  Previously it was 8MHz.\n\t+ The demo application file Demo/Common/Minimal/death.c has a slight\n\t  alteration to prevent it using floating point variables.\n\n\nChanges between V3.0.0 and V3.1.0 - Released 11th June, 2005\n\n\t+ Added new ports for ST Microsystems STR71x, and Freescale HCS12\n\t  microcontrollers.  Currently the HCS12 port is limited to the small\n\t  memory model.  Large memory models will be supported in the next\n\t  release.\n\t+ PIC18 wizC port updated.  Thanks to Marcel van Lieshout for his\n\t  continuing contribution.\n\t+ The accuracy of the AVR port timer setup has been improved.  Thanks to\n\t  Thomas Krutmann for this contribution.\n\t+ Added a new conditional compilation macro configIDLE_SHOULD_YIELD.\n\t  See the WEB documentation for details.\n\t+ Updated the CrossWorks uIP demo to build with V1.4 of CrossWorks.\n\t+ Slight modification to the SAM7 release build configuration to correct\n\t  an include path definition.\n\t+ Updated the MPLAB PIC18 documentation to provide extra details on linker\n\t  file configuration.\n\nChanges between V3.0.0 and V2.6.1 - Released 23rd April, 2005\n\n\tV3.0.0 includes many enhancements, so this history list is broken into\n\tsubsections as follows:\n\n\t\tAPI changes\n\t\tNew ports\n\t\tDirectory name changes\n\t\tKernel and miscellaneous changes changes\n\n\t- API changes\n\n\t\t+ Each port now defines BaseType_t as the data type that is most\n\t\t  efficient for that architecture.  The type BaseType_t is used\n\t\t  extensively in API calls necessitating the following changes to the\n\t\t  FreeRTOS API function prototypes.\n\n\t\t  See the \"New for V3.0.0\" section of the FreeRTOS online\n\t\t  documentation for full details of API changes.\n\n\t- New ports\n\n\t\t+ The AT91FR40008 ARM7 port contributed by John Feller is now included\n\t\t  in the download (thanks John!).\n\t\t+ The PIC18 port for the wizC/fedC compiler contributed by Marcel van\n\t\t  Lieshout is now included in the download (thanks Marcel!).\n\t\t+ The IAR port for the AVR microcontroller has been upgraded to V3.0.0\n\t\t  and is now a supported port.\n\n\t- Directory name changes\n\n\t\tFor consistency, and to allow integration of the new ports, the\n\t\tfollowing directory names have been changed.\n\n\t\t+ The source/portable/GCC/ARM7 directory has been renamed\n\t\t  source/portable/GCC/ARM7_LPC2000 so it is compatible with the naming\n\t\t  of other GCC ARM7 ports.\n\t\t+ The Demo/PIC directory has been renamed Demo/PIC18_MPLAB to\n\t\t  accommodate the wizC/fedC PIC port.\n\t\t+ The demo applications for the two AVR ports no longer share the same\n\t\t  directory.  The WinAVR demo is in the Demo/AVR_ATMega323_WinAVR\n\t\t  directory and the IAR port in the Demo/AVR_ATMega323_IAR directory.\n\n\n\t- Kernel and miscellaneous changes changes\n\n\t\t  See the \"New for V3.0.0\" section of the FreeRTOS online\n\t\t  documentation for more information.\n\n\t\t+ Previously 'portmacro.h' contained some user editable definitions\n\t\t  relating to the user application, and some fixed definitions relating\n\t\t  specifically to the port being used.  The application specific\n\t\t  definitions have been removed from 'portmacro.h' and placed inside a\n\t\t  new header file called 'FreeRTOSConfig.h'.  'portmacro.h' should now\n\t\t  never be modified by the user.  A 'FreeRTOSConfig.h' is now included\n\t\t  in each of FreeRTOS/Demo subdirectories - as it's settings relate to\n\t\t  the demo application rather than being specific to the port.\n\t\t+ Introduced configUSE_IDLE_HOOK in idle task.\n\t\t+ The idle task will yield when another idle priority task is ready to\n\t\t  run. Previously the idle task would run to the end of its time slice\n\t\t  regardless.\n\t\t+ The idle task is now created when the scheduler is started.  This\n\t\t  requires less stack than the previous scheme where it was created upon\n\t\t  creation of the first application task.\n\t\t+ The function usPortCheckFreeStackSpace() has been renamed\n\t\t  usTaskCheckFreeStackSpace() and moved from the portable layer to\n\t\t  tasks.c.\n\t\t+ Corrected spelling of portMINMAL_STACK_SIZE to portMINIMAL_STACK_SIZE.\n\t\t+ The portheap.c file included with the AVR port has been deleted.  The\n\t\t  AVR demo now uses the standard heap1 sample memory allocator.\n\t\t+ The GCC AVR port is now build using the standard make utility.  The\n\t\t  batch files used previously have been deleted.  This means a recent\n\t\t  version of WinAVR is required in order to create a binary suitable for\n\t\t  source level debugging.\n\t\t+ vTaskStartScheduler() no longer takes the configUSE_PREEMPTION\n\t\t  constant as a parameter.  Instead the constant is used directly within\n\t\t  tasks.c  and no parameter is required.\n\t\t+ The header file 'FreeRTOS.h' has been created and is used to include\n\t\t  'projdefs.h', 'FreeRTOSConfig.h' and 'portable.h' in the necessary\n\t\t  order.  FreeRTOS.h can now be included in place of these other\n\t\t  headers.\n\t\t+ The header file 'errors.h' has been deleted.  The definitions it\n\t\t  contained are now located within 'projdefs.h'.\n\t\t+ pvPortMalloc() now takes a size_t parameter as per the ANSI malloc().\n\t\t  Previously an unsigned short was used.\n\t\t+ When resuming the scheduler a yield is performed if either a tick has\n\t\t  been missed, or a task is moved from the pending ready list into a\n\t\t  ready list.  Previously a yield was not performed on this second\n\t\t  condition.\n\t\t+ In heap1.c an overflow check has been added to ensure the next free\n\t\t  byte variable does not wrap around.\n\t\t+ Introduced the portTASK_FUNCTION() and portTASK_FUNCTION_PROTO()\n\t\t  macros.\n\t\t+ The MPLAB PIC port now saved the TABLAT register in interrupt service\n\t\t  routines.\n\nChanges between V2.6.0 and V2.6.1 - Released Feb 22, 2005\n\n\tThis version adds support for the H8 processor.\n\n\tOther changes:\n\n\t+ tskMAX_TASK_NAME_LEN removed from the task.h header and added to each\n\t  individual portmacro.h file as portMAX_TASK_NAME_LEN.  This allows RAM\n\t  limited ports to allocate fewer characters to the task name.\n\t+ AVR port - Replaced the inb() and outb() functions with direct memory\n\t  access.  This allows the port to be built with the 20050414 build of\n\t  WinAVR.\n\t+ GCC LPC2106 port - removed the 'static' from the definition of\n\t  vNonPreemptiveTick() to allow the demo to link when using the cooperative\n\t  scheduler.\n\t+ GCC LPC2106 port - Corrected the optimisation options in the batch files\n\t  ROM_THUMB.bat, RAM_THUMB.bat, ROM_ARM.bat and RAM_ARM.bat.  The lower case\n\t  -o is replaced by an uppercase -O.\n\t+ Tasks.c - The strcpy call has been removed when copying across the task\n\t  name into the TCB.\n\t+ Updated the trace visualisation to always be 4 byte aligned so it can be\n\t  used on ARM architectures.\n\t+ There are now two tracecon executables (that convert the trace file binary\n\t  into an ASCII file).  One for big endian targets and one for little endian\n\t  targets.\n\t+ Added ucTasksDeleted variable to prevent vTaskSuspendAll() being called\n\t  too often in the idle task.\n\t+ SAM7 USB driver - Replaced the duplicated RX_DATA_BK0 in the interrupt\n\t  mask with the RX_DATA_BK1.\n\n\nChanges between V2.5.5 and V2.6.0 - Released January 16, 2005\n\n\t+ Added the API function vTaskDelayUntil().  The demo app file\n\t  Demo/Common/Minimal/flash.c has been updated to demonstrate its use.\n\t+ Added INCLUDE_vTaskDelay conditional compilation.\n\t+ Changed the name of the Demo/ARM7_AtmelSAM7S64_IAR directory to\n\t  Demo/ARM7_AT91SAM7S64_IAR for consistency.\n\t+ Modified the AT91SAM7S USB driver to allow descriptors that have\n\t  a length that is an exact multiple of the FIFO to be transmitted.\n\nChanges between V2.5.4 and V2.5.5 - Released January 3, 2005\n\n\tThis version adds support for the Atmel SAM7 ARM7 microcontrollers\n\talong with the IAR development tools.\n\n\tOther changes:\n\n\t+ Renamed the Demo/ARM7 directory to Demo/ARM7_LPC2106_GCC.\n\t+ Renamed the Demo/ARM7_Keil directory to Demo/ARM7_LPC2129_Keil.\n\t+ Modified the Philips ARM7 serial interrupt service routines to only\n\t  process one interrupt per call.  This seems to enable the ISR to\n\t  operate more quickly.\n\t+ Removed the 'far' keyword from the Open Watcom portable layer source\n\t  files.  This allows their use with V1.3 of Open Watcom.\n\t+ Minor modifications to the SDCC build files to allow their use under\n\t  Linux.  Thanks to Frieder Ferlemann for this contribution.\n\t+ Small change to sTaskCreate() to allow a context switch even when\n\t  pxCreatedTask is NULL.  Thanks to Kamil for this contribution.\n\t+ inline keyword removed from vTaskSwitchContext() and VTaskIncrementTick()\n\t  definitions.\n\nChanges between V2.5.3 and V2.5.4 - Released Dec 1, 2004\n\n\tThis is an important maintenance release.\n\n\tThe function cTaskResumeAll() has been modified so it can be used safely\n\tprior to the kernel being initialised.  This was an issue as\n\tcTaskResumeAll() is called from pvPortMalloc().  Thanks to Daniel Braun\n\tfor highlighting this issue.\n\nChanges between V2.5.2 and V2.5.3 - Released Nov 2, 2004\n\n\tThe critical section handling functions have been changed for the GCC ARM7\n\tport.   Some optimisation levels use the stack differently to others.  This\n\tmeans the interrupt flags cannot always be stored on the stack and are\n\tinstead now stored in a variable, which is then saved as part of the\n\ttasks context.  This allows the GCC ARM7 port to be used at all\n\toptimisation levels - including -Os.\n\n\tOther minor changes:\n\n\t+ MSP430 definition of usCriticalNesting now uses the volatile qualifier.\n\t  This is probably not required but added just in case.\n\nChanges between V2.5.1 and V2.5.2 - Released Oct 26, 2004\n\n\t+ Added the Keil ARM7 port.\n\t+ Slight modification to comtest.c to make the delay periods more random.\n\t  This creates a better test condition.\n\nChanges between V2.5.0 and V2.5.1 - Released Oct 9, 2004\n\n\t+ Added the MSP430 port.\n\t+ Extra comments added to the GCC ARM7 port.c and portISR.c files.\n\t+ The memory pool allocated within heap_1.c has been placed within a\n\t  structure to ensure correct memory alignment on 32bit systems.\n\t+ Within the GCC ARM7 serial drivers an extra check is made to ensure\n\t  the post to the queue was successful if then attempting immediately\n\t  retrieve the posted character.\n\t+ Changed the name of the constant portTICKS_PER_MS to portTICK_PERIOD_MS\n\t  as the old name was misleading.\n\n\nChanges between V2.4.2 and V2.5.0 - Released Aug 12, 2004\n\n\tThe RTOS source code download now includes three separate memory allocation\n\tschemes - so you can choose the most appropriate for your application.\n\tThese are found in the Source/Portable/MemMang directory.  The demo\n\tapplication projects have also been updated to demonstrate the new schemes.\n\tSee the \"Memory Management\" page of the API documentation for more details.\n\n\t+ Added heap_1.c, heap_2.c and heap_3.c in the Source/Portable/MemMang\n\t  directory.\n\t+ Replaced the portheap.c files for each demo application with one of the\n\t  new memory allocation files.\n\t+ Updated the portmacro.h file for each demo application to include the\n\t  constants required for the new memory allocators: portTOTAL_HEAP_SIZE and\n\t  portBYTE_ALIGNMENT.\n\t+ Added a new test to the ARM7 demo application that tests the operation\n\t  of the heap_2 memory allocator.\n\n\nChanges between V2.4.1 and V2.4.2 - Released July 14, 2004\n\n\t+ The ARM7 port now supports THUMB mode.\n\t+ Modification to the ARM7 demo application serial port driver.\n\nChanges between V2.4.0 and V2.4.1 - Released July 2, 2004\n\n\t+ Rationalised the ARM7 port version of portEXIT_CRITICAL() -\n\t  improvements provided by Bill Knight.\n\t+ Made demo serial driver more complete and robust.\n\n\nChanges between V2.4.0 and V2.3.1 - Released June 30, 2004\n\n\t+ Added the first ARM7 port - thanks to Bill Knight for the assistance\n\t  provided.\n\t+ Added extra files to the Demo/Common/Minimal directory.  These are\n\t  equivalent to their Demo/Common/Full counterparts but with the\n\t  calls to the functions defined in print.c removed.\n\t+ Added TABLAT to the list of registers saved as part of a PIC18 context.\n\nChanges between V2.3.0 and V2.3.1 - Released June 25, 2004\n\n\t+ Changed the way the vector table is defined to be more portable.\n\t+ Corrected the definitions of SPH and SPL in portmacro.s90.\n\t  The previous definitions prevented V2.3.0 operating if the iom323.h\n\t  header file was included in portmacro.s90.\n\nChanges between V2.2.0 and V2.3.0 - Released June 19, 2004\n\n\t+ Added an AVR port that uses the IAR compiler.\n\t+ Explicit use of 'signed' qualifier on plain char types.\n\t+ Modified the Open Watcom project files to use 'signed' as the\n\t  default char type.\n\t+ Changed odd calculation of initial pxTopOfStack value when\n\t  portSTACK_GROWTH < 0.\n\t+ Added inline qualifier to context switch functions within task.c.\n\t  Ports that do not support the (non ANSI) inline keyword have the\n\t  inline #define'd away in  their respective portmacro.h files.\n\nChanges between V2.1.1 and V2.2.0 - Released May 18, 2004\n\n\t+ Added Cygnal 8051 port.\n\t+ PCLATU and PCLATH are now saved as part of the PIC18 context.  This\n\t  allows function pointers to be used within tasks.  Thanks to Javier\n\t  Espeche for the enhancement.\n\t+ Minor changes to demo application files to reduce stack usage.\n\t+ Minor changes to prevent compiler warnings when compiling the new port.\n\nChanges between V2.1.0 and V2.1.1 - Released March 12, 2004\n\n\t+ Bug fix - pxCurrentTCB is now initialised before the call to\n\t  prvInitialiseTaskLists().  Previously pxCurrentTCB could be accessed\n\t  while null during the initialisation sequence.  Thanks to Giuseppe\n\t  Franco for the correction.\n\nChanges between V2.0.0 and V2.1.0 - Released Feb 29, 2004\n\n\tV2.1.0 has significant reworks that greatly reduce the amount of time\n\tthe kernel has interrupts disabled.  The first section of modifications\n\tlisted here must be taken into account by users.  The second section\n\tare related to the kernel implementation and as such are transparent.\n\n\tSection1 :\n\n\t+ The typedef TickType_t has been introduced.  All delay times should\n\t  now use a variable of type TickType_t in place of the unsigned long's\n\t  used previously.  API function prototypes have been updated\n\t  appropriately.\n\t+ The configuration macro USE_16_BIT_TICKS has been introduced.  If set\n\t  to 1 TickType_t is defined as an unsigned short.  If set to 0\n\t  TickType_t is defined as an unsigned long.  See the configuration\n\t  section of the API documentation for more details.\n\t+ The configuration macro INCLUDE_vTaskSuspendAll is now obsolete.\n\t+ vTaskResumeAll() has been renamed cTaskResumeAll() as it now returns a\n\t  value (see the API documentation).\n\t+ ulTaskGetTickCount() has been renamed xTaskGetTickCount() as the type\n\t  it returns now depends on the USE_16_BIT_TICKS definition.\n\t+ cQueueReceive() must now >never< be used from within an ISR.  Use the new\n\t  cQueueReceiveFromISR() function instead.\n\n\tSection 2:\n\n\t+ A mechanism has been introduced that allows a queue to be accessed by\n\t  a task and ISR simultaneously.\n\t+ A \"pending ready\" queue has been introduced that enables interrupts to\n\t  be processed when the scheduler is suspended.\n\t+ The list implementation has been improved to provide faster item\n\t  removal.\n\t+ The scheduler now makes use of the scheduler suspend mechanism in places\n\t  where previously interrupts were disabled.\n\nChanges between V1.2.6 and V2.0.0 - Released Jan 31, 2004\n\n\t+ Introduced new API functions:\n\t\tvTaskPriorityGet ()\n\t\tvTaskPrioritySet ()\n\t\tvTaskSuspend ()\n\t\tvTaskResume ()\n\t\tvTaskSuspendAll ()\n\t\tvTaskResumeAll ()\n\t+ Added conditional compilation options that allow the components of the\n\t  kernel that are unused by an application to be excluded from the build.\n\t  See the Configuration section on the WEB site for more information (on\n\t  the API pages).  The macros have been added to each portmacro.h file (\n\t  sometimes called prtmacro.h).\n\t+ Rearranged tasks.c.\n\t+ Added demo application file dynamic.c.\n\t+ Updated the PC demo application to make use of dynamic.c.\n\t+ Updated the documentation contained in the kernel header files.\n\t+ Creating a task now causes a context switch if the task being created\n\t  has a higher priority than the calling task - assuming the kernel is\n\t  running.\n\t+ vTaskDelete() now only causes a context switch if the calling task is\n\t  the task being deleted.\n\nChanges between V1.2.5 and V1.2.6 - Released December 31, 2003\n\n\tBarring the change to the interrupt vector (PIC port) these are minor\n\tenhancements.\n\n\t+ The interrupt vector used for the PIC master ISR has been changed from\n\t  0x18 to 0x08 - where it should have always been.  The incorrect address\n\t  still works but probably executes a number of NOP's before getting to the\n\t  ISR.\n\t+ Changed the baud rate used by the AVR demo application to 38400.  This\n\t  has an error percentage of less than one percent with an 8MHz clock.\n\t+ Raised the priority of the Rx task in demo\\full\\comtest.c.  This only\n\t  affects the Flashlite and PC ports.  This was done to prevent the Rx\n\t  buffer becoming full.\n\t+ Reverted the Flashlite COM port driver back so it does not use the DMA.\n\t  The DMA appears to miss characters under stress.  The Borland Flashlite\n\t  port was also calculating a register value incorrectly resulting in the\n\t  wrong DMA source address being used.  The same code worked fine when\n\t  compiling with Open Watcom.  Other minor enhancements were made to the\n\t  interrupt handling.\n\t+ Modified the PIC serial Rx ISR to check for and clear overrun errors.\n\t  Overrun errors seem to prevent any further characters being received.\n\t+ The PIC demo projects now have some optimisation switched on.\n\n\nChanges between V1.2.4 and V1.2.5\n\n\tSmall fix made to the PIC specific port.c file described below.\n\n\t+ Introduced portGLOBAL_INTERRUPT_FLAG definition to test the global\n\t  interrupt flag setting.  Using the two bits defined within\n\t  portINITAL_INTERRUPT_STATE was causing the w register to get clobbered\n\t  before the test was performed.\n\nChanges between V1.2.3 and V1.2.4\n\n\tV1.2.4 contains a release version of the PIC18 port.\n\tAn optional exception has been included with the GPL.  See the licensing\n\tsection of www.FreeRTOS.org for details.\n\n\t+ The function xPortInitMinimal() has been renamed to\n\t  xSerialPortInitMinimal() and the function xPortInit() has been renamed\n\t  to xSerialPortInit().\n\t+ The function sSerialPutChar() has been renamed cSerialPutChar() and\n\t  the function return type chaned to portCHAR.\n\t+ The integer and flop tasks now include calls to tskYIELD(), allowing\n\t  them to be used with the cooperative scheduler.\n\t+ All the demo applications now use the integer and comtest tasks when the\n \t  cooperative scheduler is being used.  Previously they were only used with\n\t  the preemptive scheduler.\n\t+ Minor changes made to operation of minimal versions of comtest.c and\n\t  integer.c.\n\t+ The ATMega port definition of portCPU_CLOSK_HZ definition changed to\n\t  8MHz base 10, previously it base 16.\n\n\n\nChanges between V1.2.2a and V1.2.3\n\n\tThe only change of any significance is to the license, which has changed\n\tfrom the Open Software License to the GNU GPL.\n\n\tThe zip file also contains a pre-release version of the PIC18 port.  This\n\thas not yet completed testing and as such does not constitute part of the\n\tV1.2.3 release.  It is still however covered by the GNU GPL.\n\n\tThere are minor source code changes to accommodate the PIC C compiler.\n\tThese mainly involve more explicit casting.\n\n\t+ sTaskCreate() has been modified slightly to make use of the\n\t  portSTACK_GROWTH macro.  This is required for the PIC port where the\n\t  stack grows in the opposite direction to the other existing ports.\n\t+ prvCheckTasksWaitingTermination() has been modified slightly to bring\n\t  the decrementing of usCurrentNumberOfTasks within the critical section,\n\t  where it should have been since the creation of an eight bit port.\n\nChanges between V1.2.2 and V1.2.2a\n\n\tThe makefile and buildcoff.bat files included with the AVR demo application\n\thave been modified for use with the September 2003 build of WinAVR.  No\n\tsource files have changed.\n\nChanges between V1.2.1 and V1.2.2\n\n\tThere are only minor changes here to allow the PC and Flashlite 186 ports\n\tto use the Borland V4.52 compiler, as supplied with the Flashlite 186\n\tdevelopment kit.\n\n\t+ Introduced a BCC directory under source\\portable.  This contains all the\n\t  files specific to the Borland compiler port.\n\t+ Corrected the macro naming of portMS_PER_TICK to portTICKS_PER_MS.\n\t+ Modified comtest.c to increase the rate at which the string is\n\t  transmitted and received on the serial port.  The Flashlite 186 demo\n\t  app baud rate has also been increased.\n\t+ The values of the constants used in both integer.c files have been\n          increased to force the Borland compiler to use 32 bit values.  The\n          Borland optimiser placed the previous values in 16 bit registers, and in\n          So doing invalidated the test.\n\nChanges between V1.2.0 and V1.2.1\n\n\tThis version includes some minor changes to the list implementation aimed\n\tat improving the context switch time - with is now approximately 10% faster.\n\tChanges include the removal of some null pointer assignment checks.  These\n\twere redundant where the scheduler uses the list functions, but means any\n\tuser application choosing to use the same list functions must now check\n\tthat no NULL pointers are passed as a parameter.\n\n\tThe Flashlite 186 serial port driver has also been modified to use a DMA\n\tchannel for transmissions.  The serial driver is fully functional but still\n\tunder development.  Flashlite users may prefer to use V1.2.0 for now.\n\n\tDetails:\n\n\t+ Changed the baud rate for the ATMega323 serial test from 19200 to 57600.\n\t+ Use vSerialPutString() instead of single character puts in\n\t  Demo\\Full\\Comtest.c.  This allows the use of the flashlite DMA serial\n\t  driver.  Also the check variable only stops incrementing after two\n\t  consecutive failures.\n\t+ semtest.c creates four tasks, two of which operate at the idle priority.\n\t  The tasks that operate at the idle priority now use a lower expected\n\t  count than those running at a higher priority.  This prevents the low\n\t  priority tasks from signalling an error because they have not been\n\t  scheduled enough time for each of them to count the shared variable to\n\t  the higher original value.\n\t+ The flashlite 186 serial driver now uses a DMA channel for transmissions.\n\t+ Removed the volatile modifier from the list function parameters.  This was\n\t  only ever included to prevent compiler warnings.  Now warnings are\n\t  removed by casting parameters where the calls are made.\n\t+ prvListGetOwnerOfNextEntry() and prvListGetOwnerOfHeadEntry() have been\n\t  removed from list.c and added as macros in list.h.\n\t+ usNumberOfItems has been added to the list structure.  This removes the\n\t  need for a pointer comparison when checking if a list is empty, and so\n\t  is slightly faster.\n\t+ Removed the NULL check in vListRemove().  This makes the call faster but\n\t  necessitates any application code utilising the list implementation to\n\t  ensure NULL pointers are not passed.\n\t+ Renamed portTICKS_PER_MS definition to portMS_PER_TICK (milli seconds\n\t  per tick).  This is what it always should have been.\n\nChanges between V1.01 and V1.2.0\n\n\tThe majority of these changes were made to accommodate the 8bit AVR port.\n\tThe scheduler workings have not changed, but some of the data types used\n\thave been made more friendly to an eight bit environment.\n\n\tDetails:\n\n\t+ Changed the version numbering format.\n\t+ Added AVR port.\n\t+ Split the directory demo\\common into demo\\common\\minimal and\n\t  demo\\common\\full.  The files in the full directory are for systems with\n\t  a display (currently PC and Flashlite 186 demo's).  The files in the\n\t  minimal directory are for systems with limited RAM and no display\n\t  (currently MegaAVR).\n\t+ Minor changes to demo application function prototypes to make more use\n\t  of 8bit data types.\n\t+ Within the scheduler itself the following functions have slightly\n\t  modified declarations to make use of 8bit data types where possible:\n\t\txQueueCreate(),\n\t\tsQueueReceive(),\n\t\tsQUeueReceive(),\n\t\tusQueueMessageWaiting(),\n\t\tsQueueSendFromISR(),\n\t\tsSemaphoreTake(),\n\t\tsSemaphoreGive(),\n\t\tsSemaphoreGiveFromISR(),\n\t\tsTaskCreate(),\n\t\tsTaskMoveFromEventList().\n\n\t  Where the return type has changed the function name has also changed in\n\t  accordance with the naming convention.  For example\n\t  usQueueMessageWaiting() has become ucQueueMessageWaiting().\n\t+ The definition tskMAX_PRIORITIES has been moved from task.h to\n\t  portmacro.h and renamed portMAX_PRIORITIES.  This allows different\n\t  ports to allocate a different maximum number of priorities.\n\t+ By default the trace facility is off, previously USE_TRACE_FACILITY\n\t  was defined.\n\t+ comtest.c now uses a psuedo random delay between sends.  This allows for\n\t  better testing as the interrupts do not arrive at regular intervals.\n\t+ Minor change to the Flashlite serial port driver.  The driver is written\n\t  to demonstrate the scheduler and is not written to be efficient.\n\n\n\nChanges between V1.00 and V1.01\n\n\tThese changes improve the ports.  The scheduler itself has not changed.\n\n\tImproved context switch mechanism used when performing a context\n\tswitch from an ISR (both the tick ISR and the serial comms ISR's within\n\tthe demo application).  The new mechanism is faster and uses less stack.\n\n\tThe assembler file portasm.asm has been replaced by a header file\n\tportasm.h.  This includes a few assembler macro definitions.\n\n\tAll saving and restoring of registers onto/off of the stack is now handled\n\tby the compiler.  This means the initial stack setup for a task has to\n\tmimic the stack used by the compiler, which is different for debug and\n\trelease builds.\n\n\tSlightly changed the operation of the demo application, details below.\n\n\tDetails:\n\n\t+ portSWITCH_CONTEXT() replaced by vPortFirstContext().\n\t+ pxPortInitialiseStack() modified to replicate the stack used by the\n\t  compiler.\n\t+ portasm.asm file removed.\n\t+ portasm.h introduced.  This contains macro definitions for\n\t  portSWITCH_CONTEXT() and portFIRST_CONTEXT().\n\t+ Context switch from ISR now uses the compiler generated interrupt\n\t  mechanism.  This is done simply by calling portSWITCH_CONTEXT and leaving\n\t  the save/restore to compiler generated code.\n\t+ Calls to taskYIELD() during ISR's have been replaced by calling the\n\t  simpler and faster portSWITCH_CONTEXT().\n\t+ The Flashlite 186 port now uses 186 instruction set (used to use 80x86\n\t  instructions only).\n\t+ The blocking queue tasks within the demo application did not operate\n\t  quite as described.  This has been corrected.\n\t+ The priority of the comtest Rx task within the demo application has been\n\t  lowered.  Received characters are now processed (read from the queue) at\n\t  the idle priority, allowing low priority tasks to run evenly at times of\n\t  a high communications overhead.\n\t+ Prevent the call to kbhit() in main.c for debug builds as the debugger\n\t  seems to have problems stepping over the call.  This if for the PC port\n\t  only.\n\n\n\n"
  },
  {
    "path": "FreeRTOS-comparison/LICENSE.md",
    "content": "MIT License\n\nPermission is hereby granted, free of charge, to any person obtaining a copy\nof this software and associated documentation files (the \"Software\"), to deal\nin the Software without restriction, including without limitation the rights\nto use, copy, modify, merge, publish, distribute, sublicense, and/or sell\ncopies of the Software, and to permit persons to whom the Software is\nfurnished to do so, subject to the following conditions:\n\nThe above copyright notice and this permission notice shall be included in all\ncopies or substantial portions of the Software.\n\nTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\nIMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\nFITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\nAUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\nLIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\nOUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\nSOFTWARE.\n"
  },
  {
    "path": "FreeRTOS-comparison/Quick_Start_Guide.url",
    "content": "[InternetShortcut]\nURL=https://www.FreeRTOS.org/FreeRTOS-quick-start-guide.html\nIDList=\n[{000214A0-0000-0000-C000-000000000046}]\nProp3=19,2\n"
  },
  {
    "path": "FreeRTOS-comparison/README.md",
    "content": "> NOTE<br>\nThis directory is the FreeRTOS Kernel part of the <b>FreeRTOS 202210 LTS</b>\ndistribution. To reduce the size, the `portable` sub-directory has been\npruned and several FreeRTOS ports have been removed.\n\nQuantum Leaps, March 4, 2023\n\n## Getting started\nThis repository contains FreeRTOS kernel source/header files and kernel ports only. This repository is referenced as a submodule in [FreeRTOS/FreeRTOS](https://github.com/FreeRTOS/FreeRTOS) repository, which contains pre-configured demo application projects under ```FreeRTOS/Demo``` directory.\n\nThe easiest way to use FreeRTOS is to start with one of the pre-configured demo application projects.  That way you will have the correct FreeRTOS source files included, and the correct include paths configured.  Once a demo application is building and executing you can remove the demo application files, and start to add in your own application source files.  See the [FreeRTOS Kernel Quick Start Guide](https://www.FreeRTOS.org/FreeRTOS-quick-start-guide.html) for detailed instructions and other useful links.\n\nAdditionally, for FreeRTOS kernel feature information refer to the [Developer Documentation](https://www.FreeRTOS.org/features.html), and [API Reference](https://www.FreeRTOS.org/a00106.html).\n\n### Getting help\nIf you have any questions or need assistance troubleshooting your FreeRTOS project, we have an active community that can help on the [FreeRTOS Community Support Forum](https://forums.freertos.org).\n\n## Cloning this repository\n\nTo clone using HTTPS:\n```\ngit clone https://github.com/FreeRTOS/FreeRTOS-Kernel.git\n```\nUsing SSH:\n```\ngit clone git@github.com:FreeRTOS/FreeRTOS-Kernel.git\n```\n\n## Repository structure\n- The root of this repository contains the three files that are common to\nevery port - list.c, queue.c and tasks.c.  The kernel is contained within these\nthree files.  croutine.c implements the optional co-routine functionality - which\nis normally only used on very memory limited systems.\n\n- The ```./portable``` directory contains the files that are specific to a particular microcontroller and/or compiler.\nSee the readme file in the ```./portable``` directory for more information.\n\n- The ```./include``` directory contains the real time kernel header files.\n\n### Code Formatting\nFreeRTOS files are formatted using the \"uncrustify\" tool. The configuration file used by uncrustify can be found in the [FreeRTOS/FreeRTOS repository](https://github.com/FreeRTOS/FreeRTOS/blob/main/tools/uncrustify.cfg).\n\n### Spelling\n*lexicon.txt* contains words that are not traditionally found in an English dictionary. It is used by the spellchecker to verify the various jargon, variable names, and other odd words used in the FreeRTOS code base. If your pull request fails to pass the spelling and you believe this is a mistake, then add the word to *lexicon.txt*.\nNote that only the FreeRTOS Kernel source files are checked for proper spelling, the portable section is ignored.\n\n"
  },
  {
    "path": "FreeRTOS-comparison/croutine.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n#include \"croutine.h\"\n\n/* Remove the whole file is co-routines are not being used. */\n#if ( configUSE_CO_ROUTINES != 0 )\n\n/*\n * Some kernel aware debuggers require data to be viewed to be global, rather\n * than file scope.\n */\n    #ifdef portREMOVE_STATIC_QUALIFIER\n        #define static\n    #endif\n\n\n/* Lists for ready and blocked co-routines. --------------------*/\n    static List_t pxReadyCoRoutineLists[ configMAX_CO_ROUTINE_PRIORITIES ]; /*< Prioritised ready co-routines. */\n    static List_t xDelayedCoRoutineList1;                                   /*< Delayed co-routines. */\n    static List_t xDelayedCoRoutineList2;                                   /*< Delayed co-routines (two lists are used - one for delays that have overflowed the current tick count. */\n    static List_t * pxDelayedCoRoutineList = NULL;                          /*< Points to the delayed co-routine list currently being used. */\n    static List_t * pxOverflowDelayedCoRoutineList = NULL;                  /*< Points to the delayed co-routine list currently being used to hold co-routines that have overflowed the current tick count. */\n    static List_t xPendingReadyCoRoutineList;                               /*< Holds co-routines that have been readied by an external event.  They cannot be added directly to the ready lists as the ready lists cannot be accessed by interrupts. */\n\n/* Other file private variables. --------------------------------*/\n    CRCB_t * pxCurrentCoRoutine = NULL;\n    static UBaseType_t uxTopCoRoutineReadyPriority = 0;\n    static TickType_t xCoRoutineTickCount = 0, xLastTickCount = 0, xPassedTicks = 0;\n\n/* The initial state of the co-routine when it is created. */\n    #define corINITIAL_STATE    ( 0 )\n\n/*\n * Place the co-routine represented by pxCRCB into the appropriate ready queue\n * for the priority.  It is inserted at the end of the list.\n *\n * This macro accesses the co-routine ready lists and therefore must not be\n * used from within an ISR.\n */\n    #define prvAddCoRoutineToReadyQueue( pxCRCB )                                                                               \\\n    {                                                                                                                           \\\n        if( ( pxCRCB )->uxPriority > uxTopCoRoutineReadyPriority )                                                              \\\n        {                                                                                                                       \\\n            uxTopCoRoutineReadyPriority = ( pxCRCB )->uxPriority;                                                               \\\n        }                                                                                                                       \\\n        vListInsertEnd( ( List_t * ) &( pxReadyCoRoutineLists[ ( pxCRCB )->uxPriority ] ), &( ( pxCRCB )->xGenericListItem ) ); \\\n    }\n\n/*\n * Utility to ready all the lists used by the scheduler.  This is called\n * automatically upon the creation of the first co-routine.\n */\n    static void prvInitialiseCoRoutineLists( void );\n\n/*\n * Co-routines that are readied by an interrupt cannot be placed directly into\n * the ready lists (there is no mutual exclusion).  Instead they are placed in\n * in the pending ready list in order that they can later be moved to the ready\n * list by the co-routine scheduler.\n */\n    static void prvCheckPendingReadyList( void );\n\n/*\n * Macro that looks at the list of co-routines that are currently delayed to\n * see if any require waking.\n *\n * Co-routines are stored in the queue in the order of their wake time -\n * meaning once one co-routine has been found whose timer has not expired\n * we need not look any further down the list.\n */\n    static void prvCheckDelayedList( void );\n\n/*-----------------------------------------------------------*/\n\n    BaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode,\n                                 UBaseType_t uxPriority,\n                                 UBaseType_t uxIndex )\n    {\n        BaseType_t xReturn;\n        CRCB_t * pxCoRoutine;\n\n        /* Allocate the memory that will store the co-routine control block. */\n        pxCoRoutine = ( CRCB_t * ) pvPortMalloc( sizeof( CRCB_t ) );\n\n        if( pxCoRoutine )\n        {\n            /* If pxCurrentCoRoutine is NULL then this is the first co-routine to\n            * be created and the co-routine data structures need initialising. */\n            if( pxCurrentCoRoutine == NULL )\n            {\n                pxCurrentCoRoutine = pxCoRoutine;\n                prvInitialiseCoRoutineLists();\n            }\n\n            /* Check the priority is within limits. */\n            if( uxPriority >= configMAX_CO_ROUTINE_PRIORITIES )\n            {\n                uxPriority = configMAX_CO_ROUTINE_PRIORITIES - 1;\n            }\n\n            /* Fill out the co-routine control block from the function parameters. */\n            pxCoRoutine->uxState = corINITIAL_STATE;\n            pxCoRoutine->uxPriority = uxPriority;\n            pxCoRoutine->uxIndex = uxIndex;\n            pxCoRoutine->pxCoRoutineFunction = pxCoRoutineCode;\n\n            /* Initialise all the other co-routine control block parameters. */\n            vListInitialiseItem( &( pxCoRoutine->xGenericListItem ) );\n            vListInitialiseItem( &( pxCoRoutine->xEventListItem ) );\n\n            /* Set the co-routine control block as a link back from the ListItem_t.\n             * This is so we can get back to the containing CRCB from a generic item\n             * in a list. */\n            listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xGenericListItem ), pxCoRoutine );\n            listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xEventListItem ), pxCoRoutine );\n\n            /* Event lists are always in priority order. */\n            listSET_LIST_ITEM_VALUE( &( pxCoRoutine->xEventListItem ), ( ( TickType_t ) configMAX_CO_ROUTINE_PRIORITIES - ( TickType_t ) uxPriority ) );\n\n            /* Now the co-routine has been initialised it can be added to the ready\n             * list at the correct priority. */\n            prvAddCoRoutineToReadyQueue( pxCoRoutine );\n\n            xReturn = pdPASS;\n        }\n        else\n        {\n            xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;\n        }\n\n        return xReturn;\n    }\n/*-----------------------------------------------------------*/\n\n    void vCoRoutineAddToDelayedList( TickType_t xTicksToDelay,\n                                     List_t * pxEventList )\n    {\n        TickType_t xTimeToWake;\n\n        /* Calculate the time to wake - this may overflow but this is\n         * not a problem. */\n        xTimeToWake = xCoRoutineTickCount + xTicksToDelay;\n\n        /* We must remove ourselves from the ready list before adding\n         * ourselves to the blocked list as the same list item is used for\n         * both lists. */\n        ( void ) uxListRemove( ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) );\n\n        /* The list item will be inserted in wake time order. */\n        listSET_LIST_ITEM_VALUE( &( pxCurrentCoRoutine->xGenericListItem ), xTimeToWake );\n\n        if( xTimeToWake < xCoRoutineTickCount )\n        {\n            /* Wake time has overflowed.  Place this item in the\n             * overflow list. */\n            vListInsert( ( List_t * ) pxOverflowDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) );\n        }\n        else\n        {\n            /* The wake time has not overflowed, so we can use the\n             * current block list. */\n            vListInsert( ( List_t * ) pxDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) );\n        }\n\n        if( pxEventList )\n        {\n            /* Also add the co-routine to an event list.  If this is done then the\n             * function must be called with interrupts disabled. */\n            vListInsert( pxEventList, &( pxCurrentCoRoutine->xEventListItem ) );\n        }\n    }\n/*-----------------------------------------------------------*/\n\n    static void prvCheckPendingReadyList( void )\n    {\n        /* Are there any co-routines waiting to get moved to the ready list?  These\n         * are co-routines that have been readied by an ISR.  The ISR cannot access\n         * the ready lists itself. */\n        while( listLIST_IS_EMPTY( &xPendingReadyCoRoutineList ) == pdFALSE )\n        {\n            CRCB_t * pxUnblockedCRCB;\n\n            /* The pending ready list can be accessed by an ISR. */\n            portDISABLE_INTERRUPTS();\n            {\n                pxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyCoRoutineList ) );\n                ( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) );\n            }\n            portENABLE_INTERRUPTS();\n\n            ( void ) uxListRemove( &( pxUnblockedCRCB->xGenericListItem ) );\n            prvAddCoRoutineToReadyQueue( pxUnblockedCRCB );\n        }\n    }\n/*-----------------------------------------------------------*/\n\n    static void prvCheckDelayedList( void )\n    {\n        CRCB_t * pxCRCB;\n\n        xPassedTicks = xTaskGetTickCount() - xLastTickCount;\n\n        while( xPassedTicks )\n        {\n            xCoRoutineTickCount++;\n            xPassedTicks--;\n\n            /* If the tick count has overflowed we need to swap the ready lists. */\n            if( xCoRoutineTickCount == 0 )\n            {\n                List_t * pxTemp;\n\n                /* Tick count has overflowed so we need to swap the delay lists.  If there are\n                 * any items in pxDelayedCoRoutineList here then there is an error! */\n                pxTemp = pxDelayedCoRoutineList;\n                pxDelayedCoRoutineList = pxOverflowDelayedCoRoutineList;\n                pxOverflowDelayedCoRoutineList = pxTemp;\n            }\n\n            /* See if this tick has made a timeout expire. */\n            while( listLIST_IS_EMPTY( pxDelayedCoRoutineList ) == pdFALSE )\n            {\n                pxCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedCoRoutineList );\n\n                if( xCoRoutineTickCount < listGET_LIST_ITEM_VALUE( &( pxCRCB->xGenericListItem ) ) )\n                {\n                    /* Timeout not yet expired. */\n                    break;\n                }\n\n                portDISABLE_INTERRUPTS();\n                {\n                    /* The event could have occurred just before this critical\n                     *  section.  If this is the case then the generic list item will\n                     *  have been moved to the pending ready list and the following\n                     *  line is still valid.  Also the pvContainer parameter will have\n                     *  been set to NULL so the following lines are also valid. */\n                    ( void ) uxListRemove( &( pxCRCB->xGenericListItem ) );\n\n                    /* Is the co-routine waiting on an event also? */\n                    if( pxCRCB->xEventListItem.pxContainer )\n                    {\n                        ( void ) uxListRemove( &( pxCRCB->xEventListItem ) );\n                    }\n                }\n                portENABLE_INTERRUPTS();\n\n                prvAddCoRoutineToReadyQueue( pxCRCB );\n            }\n        }\n\n        xLastTickCount = xCoRoutineTickCount;\n    }\n/*-----------------------------------------------------------*/\n\n    void vCoRoutineSchedule( void )\n    {\n        /* Only run a co-routine after prvInitialiseCoRoutineLists() has been\n         * called.  prvInitialiseCoRoutineLists() is called automatically when a\n         * co-routine is created. */\n        if( pxDelayedCoRoutineList != NULL )\n        {\n            /* See if any co-routines readied by events need moving to the ready lists. */\n            prvCheckPendingReadyList();\n\n            /* See if any delayed co-routines have timed out. */\n            prvCheckDelayedList();\n\n            /* Find the highest priority queue that contains ready co-routines. */\n            while( listLIST_IS_EMPTY( &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ) )\n            {\n                if( uxTopCoRoutineReadyPriority == 0 )\n                {\n                    /* No more co-routines to check. */\n                    return;\n                }\n\n                --uxTopCoRoutineReadyPriority;\n            }\n\n            /* listGET_OWNER_OF_NEXT_ENTRY walks through the list, so the co-routines\n             * of the same priority get an equal share of the processor time. */\n            listGET_OWNER_OF_NEXT_ENTRY( pxCurrentCoRoutine, &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) );\n\n            /* Call the co-routine. */\n            ( pxCurrentCoRoutine->pxCoRoutineFunction )( pxCurrentCoRoutine, pxCurrentCoRoutine->uxIndex );\n        }\n    }\n/*-----------------------------------------------------------*/\n\n    static void prvInitialiseCoRoutineLists( void )\n    {\n        UBaseType_t uxPriority;\n\n        for( uxPriority = 0; uxPriority < configMAX_CO_ROUTINE_PRIORITIES; uxPriority++ )\n        {\n            vListInitialise( ( List_t * ) &( pxReadyCoRoutineLists[ uxPriority ] ) );\n        }\n\n        vListInitialise( ( List_t * ) &xDelayedCoRoutineList1 );\n        vListInitialise( ( List_t * ) &xDelayedCoRoutineList2 );\n        vListInitialise( ( List_t * ) &xPendingReadyCoRoutineList );\n\n        /* Start with pxDelayedCoRoutineList using list1 and the\n         * pxOverflowDelayedCoRoutineList using list2. */\n        pxDelayedCoRoutineList = &xDelayedCoRoutineList1;\n        pxOverflowDelayedCoRoutineList = &xDelayedCoRoutineList2;\n    }\n/*-----------------------------------------------------------*/\n\n    BaseType_t xCoRoutineRemoveFromEventList( const List_t * pxEventList )\n    {\n        CRCB_t * pxUnblockedCRCB;\n        BaseType_t xReturn;\n\n        /* This function is called from within an interrupt.  It can only access\n         * event lists and the pending ready list.  This function assumes that a\n         * check has already been made to ensure pxEventList is not empty. */\n        pxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList );\n        ( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) );\n        vListInsertEnd( ( List_t * ) &( xPendingReadyCoRoutineList ), &( pxUnblockedCRCB->xEventListItem ) );\n\n        if( pxUnblockedCRCB->uxPriority >= pxCurrentCoRoutine->uxPriority )\n        {\n            xReturn = pdTRUE;\n        }\n        else\n        {\n            xReturn = pdFALSE;\n        }\n\n        return xReturn;\n    }\n\n#endif /* configUSE_CO_ROUTINES == 0 */\n"
  },
  {
    "path": "FreeRTOS-comparison/event_groups.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Standard includes. */\n#include <stdlib.h>\n\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\n * all the API functions to use the MPU wrappers.  That should only be done when\n * task.h is included from an application file. */\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/* FreeRTOS includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n#include \"timers.h\"\n#include \"event_groups.h\"\n\n/* Lint e961, e750 and e9021 are suppressed as a MISRA exception justified\n * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined\n * for the header files above, but not in this file, in order to generate the\n * correct privileged Vs unprivileged linkage and placement. */\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021 See comment above. */\n\n/* The following bit fields convey control information in a task's event list\n * item value.  It is important they don't clash with the\n * taskEVENT_LIST_ITEM_VALUE_IN_USE definition. */\n#if configUSE_16_BIT_TICKS == 1\n    #define eventCLEAR_EVENTS_ON_EXIT_BIT    0x0100U\n    #define eventUNBLOCKED_DUE_TO_BIT_SET    0x0200U\n    #define eventWAIT_FOR_ALL_BITS           0x0400U\n    #define eventEVENT_BITS_CONTROL_BYTES    0xff00U\n#else\n    #define eventCLEAR_EVENTS_ON_EXIT_BIT    0x01000000UL\n    #define eventUNBLOCKED_DUE_TO_BIT_SET    0x02000000UL\n    #define eventWAIT_FOR_ALL_BITS           0x04000000UL\n    #define eventEVENT_BITS_CONTROL_BYTES    0xff000000UL\n#endif\n\ntypedef struct EventGroupDef_t\n{\n    EventBits_t uxEventBits;\n    List_t xTasksWaitingForBits; /*< List of tasks waiting for a bit to be set. */\n\n    #if ( configUSE_TRACE_FACILITY == 1 )\n        UBaseType_t uxEventGroupNumber;\n    #endif\n\n    #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )\n        uint8_t ucStaticallyAllocated; /*< Set to pdTRUE if the event group is statically allocated to ensure no attempt is made to free the memory. */\n    #endif\n} EventGroup_t;\n\n/*-----------------------------------------------------------*/\n\n/*\n * Test the bits set in uxCurrentEventBits to see if the wait condition is met.\n * The wait condition is defined by xWaitForAllBits.  If xWaitForAllBits is\n * pdTRUE then the wait condition is met if all the bits set in uxBitsToWaitFor\n * are also set in uxCurrentEventBits.  If xWaitForAllBits is pdFALSE then the\n * wait condition is met if any of the bits set in uxBitsToWait for are also set\n * in uxCurrentEventBits.\n */\nstatic BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits,\n                                        const EventBits_t uxBitsToWaitFor,\n                                        const BaseType_t xWaitForAllBits ) PRIVILEGED_FUNCTION;\n\n/*-----------------------------------------------------------*/\n\n#if ( configSUPPORT_STATIC_ALLOCATION == 1 )\n\n    EventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t * pxEventGroupBuffer )\n    {\n        EventGroup_t * pxEventBits;\n\n        /* A StaticEventGroup_t object must be provided. */\n        configASSERT( pxEventGroupBuffer );\n\n        #if ( configASSERT_DEFINED == 1 )\n        {\n            /* Sanity check that the size of the structure used to declare a\n             * variable of type StaticEventGroup_t equals the size of the real\n             * event group structure. */\n            volatile size_t xSize = sizeof( StaticEventGroup_t );\n            configASSERT( xSize == sizeof( EventGroup_t ) );\n        } /*lint !e529 xSize is referenced if configASSERT() is defined. */\n        #endif /* configASSERT_DEFINED */\n\n        /* The user has provided a statically allocated event group - use it. */\n        pxEventBits = ( EventGroup_t * ) pxEventGroupBuffer; /*lint !e740 !e9087 EventGroup_t and StaticEventGroup_t are deliberately aliased for data hiding purposes and guaranteed to have the same size and alignment requirement - checked by configASSERT(). */\n\n        if( pxEventBits != NULL )\n        {\n            pxEventBits->uxEventBits = 0;\n            vListInitialise( &( pxEventBits->xTasksWaitingForBits ) );\n\n            #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n            {\n                /* Both static and dynamic allocation can be used, so note that\n                 * this event group was created statically in case the event group\n                 * is later deleted. */\n                pxEventBits->ucStaticallyAllocated = pdTRUE;\n            }\n            #endif /* configSUPPORT_DYNAMIC_ALLOCATION */\n\n            traceEVENT_GROUP_CREATE( pxEventBits );\n        }\n        else\n        {\n            /* xEventGroupCreateStatic should only ever be called with\n             * pxEventGroupBuffer pointing to a pre-allocated (compile time\n             * allocated) StaticEventGroup_t variable. */\n            traceEVENT_GROUP_CREATE_FAILED();\n        }\n\n        return pxEventBits;\n    }\n\n#endif /* configSUPPORT_STATIC_ALLOCATION */\n/*-----------------------------------------------------------*/\n\n#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n\n    EventGroupHandle_t xEventGroupCreate( void )\n    {\n        EventGroup_t * pxEventBits;\n\n        /* Allocate the event group.  Justification for MISRA deviation as\n         * follows:  pvPortMalloc() always ensures returned memory blocks are\n         * aligned per the requirements of the MCU stack.  In this case\n         * pvPortMalloc() must return a pointer that is guaranteed to meet the\n         * alignment requirements of the EventGroup_t structure - which (if you\n         * follow it through) is the alignment requirements of the TickType_t type\n         * (EventBits_t being of TickType_t itself).  Therefore, whenever the\n         * stack alignment requirements are greater than or equal to the\n         * TickType_t alignment requirements the cast is safe.  In other cases,\n         * where the natural word size of the architecture is less than\n         * sizeof( TickType_t ), the TickType_t variables will be accessed in two\n         * or more reads operations, and the alignment requirements is only that\n         * of each individual read. */\n        pxEventBits = ( EventGroup_t * ) pvPortMalloc( sizeof( EventGroup_t ) ); /*lint !e9087 !e9079 see comment above. */\n\n        if( pxEventBits != NULL )\n        {\n            pxEventBits->uxEventBits = 0;\n            vListInitialise( &( pxEventBits->xTasksWaitingForBits ) );\n\n            #if ( configSUPPORT_STATIC_ALLOCATION == 1 )\n            {\n                /* Both static and dynamic allocation can be used, so note this\n                 * event group was allocated statically in case the event group is\n                 * later deleted. */\n                pxEventBits->ucStaticallyAllocated = pdFALSE;\n            }\n            #endif /* configSUPPORT_STATIC_ALLOCATION */\n\n            traceEVENT_GROUP_CREATE( pxEventBits );\n        }\n        else\n        {\n            traceEVENT_GROUP_CREATE_FAILED(); /*lint !e9063 Else branch only exists to allow tracing and does not generate code if trace macros are not defined. */\n        }\n\n        return pxEventBits;\n    }\n\n#endif /* configSUPPORT_DYNAMIC_ALLOCATION */\n/*-----------------------------------------------------------*/\n\nEventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup,\n                             const EventBits_t uxBitsToSet,\n                             const EventBits_t uxBitsToWaitFor,\n                             TickType_t xTicksToWait )\n{\n    EventBits_t uxOriginalBitValue, uxReturn;\n    EventGroup_t * pxEventBits = xEventGroup;\n    BaseType_t xAlreadyYielded;\n    BaseType_t xTimeoutOccurred = pdFALSE;\n\n    configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 );\n    configASSERT( uxBitsToWaitFor != 0 );\n    #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )\n    {\n        configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );\n    }\n    #endif\n\n    vTaskSuspendAll();\n    {\n        uxOriginalBitValue = pxEventBits->uxEventBits;\n\n        ( void ) xEventGroupSetBits( xEventGroup, uxBitsToSet );\n\n        if( ( ( uxOriginalBitValue | uxBitsToSet ) & uxBitsToWaitFor ) == uxBitsToWaitFor )\n        {\n            /* All the rendezvous bits are now set - no need to block. */\n            uxReturn = ( uxOriginalBitValue | uxBitsToSet );\n\n            /* Rendezvous always clear the bits.  They will have been cleared\n             * already unless this is the only task in the rendezvous. */\n            pxEventBits->uxEventBits &= ~uxBitsToWaitFor;\n\n            xTicksToWait = 0;\n        }\n        else\n        {\n            if( xTicksToWait != ( TickType_t ) 0 )\n            {\n                traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor );\n\n                /* Store the bits that the calling task is waiting for in the\n                 * task's event list item so the kernel knows when a match is\n                 * found.  Then enter the blocked state. */\n                vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | eventCLEAR_EVENTS_ON_EXIT_BIT | eventWAIT_FOR_ALL_BITS ), xTicksToWait );\n\n                /* This assignment is obsolete as uxReturn will get set after\n                 * the task unblocks, but some compilers mistakenly generate a\n                 * warning about uxReturn being returned without being set if the\n                 * assignment is omitted. */\n                uxReturn = 0;\n            }\n            else\n            {\n                /* The rendezvous bits were not set, but no block time was\n                 * specified - just return the current event bit value. */\n                uxReturn = pxEventBits->uxEventBits;\n                xTimeoutOccurred = pdTRUE;\n            }\n        }\n    }\n    xAlreadyYielded = xTaskResumeAll();\n\n    if( xTicksToWait != ( TickType_t ) 0 )\n    {\n        if( xAlreadyYielded == pdFALSE )\n        {\n            portYIELD_WITHIN_API();\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n\n        /* The task blocked to wait for its required bits to be set - at this\n         * point either the required bits were set or the block time expired.  If\n         * the required bits were set they will have been stored in the task's\n         * event list item, and they should now be retrieved then cleared. */\n        uxReturn = uxTaskResetEventItemValue();\n\n        if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 )\n        {\n            /* The task timed out, just return the current event bit value. */\n            taskENTER_CRITICAL();\n            {\n                uxReturn = pxEventBits->uxEventBits;\n\n                /* Although the task got here because it timed out before the\n                 * bits it was waiting for were set, it is possible that since it\n                 * unblocked another task has set the bits.  If this is the case\n                 * then it needs to clear the bits before exiting. */\n                if( ( uxReturn & uxBitsToWaitFor ) == uxBitsToWaitFor )\n                {\n                    pxEventBits->uxEventBits &= ~uxBitsToWaitFor;\n                }\n                else\n                {\n                    mtCOVERAGE_TEST_MARKER();\n                }\n            }\n            taskEXIT_CRITICAL();\n\n            xTimeoutOccurred = pdTRUE;\n        }\n        else\n        {\n            /* The task unblocked because the bits were set. */\n        }\n\n        /* Control bits might be set as the task had blocked should not be\n         * returned. */\n        uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES;\n    }\n\n    traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred );\n\n    /* Prevent compiler warnings when trace macros are not used. */\n    ( void ) xTimeoutOccurred;\n\n    return uxReturn;\n}\n/*-----------------------------------------------------------*/\n\nEventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup,\n                                 const EventBits_t uxBitsToWaitFor,\n                                 const BaseType_t xClearOnExit,\n                                 const BaseType_t xWaitForAllBits,\n                                 TickType_t xTicksToWait )\n{\n    EventGroup_t * pxEventBits = xEventGroup;\n    EventBits_t uxReturn, uxControlBits = 0;\n    BaseType_t xWaitConditionMet, xAlreadyYielded;\n    BaseType_t xTimeoutOccurred = pdFALSE;\n\n    /* Check the user is not attempting to wait on the bits used by the kernel\n     * itself, and that at least one bit is being requested. */\n    configASSERT( xEventGroup );\n    configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 );\n    configASSERT( uxBitsToWaitFor != 0 );\n    #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )\n    {\n        configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );\n    }\n    #endif\n\n    vTaskSuspendAll();\n    {\n        const EventBits_t uxCurrentEventBits = pxEventBits->uxEventBits;\n\n        /* Check to see if the wait condition is already met or not. */\n        xWaitConditionMet = prvTestWaitCondition( uxCurrentEventBits, uxBitsToWaitFor, xWaitForAllBits );\n\n        if( xWaitConditionMet != pdFALSE )\n        {\n            /* The wait condition has already been met so there is no need to\n             * block. */\n            uxReturn = uxCurrentEventBits;\n            xTicksToWait = ( TickType_t ) 0;\n\n            /* Clear the wait bits if requested to do so. */\n            if( xClearOnExit != pdFALSE )\n            {\n                pxEventBits->uxEventBits &= ~uxBitsToWaitFor;\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n        else if( xTicksToWait == ( TickType_t ) 0 )\n        {\n            /* The wait condition has not been met, but no block time was\n             * specified, so just return the current value. */\n            uxReturn = uxCurrentEventBits;\n            xTimeoutOccurred = pdTRUE;\n        }\n        else\n        {\n            /* The task is going to block to wait for its required bits to be\n             * set.  uxControlBits are used to remember the specified behaviour of\n             * this call to xEventGroupWaitBits() - for use when the event bits\n             * unblock the task. */\n            if( xClearOnExit != pdFALSE )\n            {\n                uxControlBits |= eventCLEAR_EVENTS_ON_EXIT_BIT;\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n\n            if( xWaitForAllBits != pdFALSE )\n            {\n                uxControlBits |= eventWAIT_FOR_ALL_BITS;\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n\n            /* Store the bits that the calling task is waiting for in the\n             * task's event list item so the kernel knows when a match is\n             * found.  Then enter the blocked state. */\n            vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | uxControlBits ), xTicksToWait );\n\n            /* This is obsolete as it will get set after the task unblocks, but\n             * some compilers mistakenly generate a warning about the variable\n             * being returned without being set if it is not done. */\n            uxReturn = 0;\n\n            traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor );\n        }\n    }\n    xAlreadyYielded = xTaskResumeAll();\n\n    if( xTicksToWait != ( TickType_t ) 0 )\n    {\n        if( xAlreadyYielded == pdFALSE )\n        {\n            portYIELD_WITHIN_API();\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n\n        /* The task blocked to wait for its required bits to be set - at this\n         * point either the required bits were set or the block time expired.  If\n         * the required bits were set they will have been stored in the task's\n         * event list item, and they should now be retrieved then cleared. */\n        uxReturn = uxTaskResetEventItemValue();\n\n        if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 )\n        {\n            taskENTER_CRITICAL();\n            {\n                /* The task timed out, just return the current event bit value. */\n                uxReturn = pxEventBits->uxEventBits;\n\n                /* It is possible that the event bits were updated between this\n                 * task leaving the Blocked state and running again. */\n                if( prvTestWaitCondition( uxReturn, uxBitsToWaitFor, xWaitForAllBits ) != pdFALSE )\n                {\n                    if( xClearOnExit != pdFALSE )\n                    {\n                        pxEventBits->uxEventBits &= ~uxBitsToWaitFor;\n                    }\n                    else\n                    {\n                        mtCOVERAGE_TEST_MARKER();\n                    }\n                }\n                else\n                {\n                    mtCOVERAGE_TEST_MARKER();\n                }\n\n                xTimeoutOccurred = pdTRUE;\n            }\n            taskEXIT_CRITICAL();\n        }\n        else\n        {\n            /* The task unblocked because the bits were set. */\n        }\n\n        /* The task blocked so control bits may have been set. */\n        uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES;\n    }\n\n    traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred );\n\n    /* Prevent compiler warnings when trace macros are not used. */\n    ( void ) xTimeoutOccurred;\n\n    return uxReturn;\n}\n/*-----------------------------------------------------------*/\n\nEventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup,\n                                  const EventBits_t uxBitsToClear )\n{\n    EventGroup_t * pxEventBits = xEventGroup;\n    EventBits_t uxReturn;\n\n    /* Check the user is not attempting to clear the bits used by the kernel\n     * itself. */\n    configASSERT( xEventGroup );\n    configASSERT( ( uxBitsToClear & eventEVENT_BITS_CONTROL_BYTES ) == 0 );\n\n    taskENTER_CRITICAL();\n    {\n        traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear );\n\n        /* The value returned is the event group value prior to the bits being\n         * cleared. */\n        uxReturn = pxEventBits->uxEventBits;\n\n        /* Clear the bits. */\n        pxEventBits->uxEventBits &= ~uxBitsToClear;\n    }\n    taskEXIT_CRITICAL();\n\n    return uxReturn;\n}\n/*-----------------------------------------------------------*/\n\n#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )\n\n    BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup,\n                                            const EventBits_t uxBitsToClear )\n    {\n        BaseType_t xReturn;\n\n        traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear );\n        xReturn = xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL ); /*lint !e9087 Can't avoid cast to void* as a generic callback function not specific to this use case. Callback casts back to original type so safe. */\n\n        return xReturn;\n    }\n\n#endif /* if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) */\n/*-----------------------------------------------------------*/\n\nEventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup )\n{\n    UBaseType_t uxSavedInterruptStatus;\n    EventGroup_t const * const pxEventBits = xEventGroup;\n    EventBits_t uxReturn;\n\n    uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();\n    {\n        uxReturn = pxEventBits->uxEventBits;\n    }\n    portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\n\n    return uxReturn;\n} /*lint !e818 EventGroupHandle_t is a typedef used in other functions to so can't be pointer to const. */\n/*-----------------------------------------------------------*/\n\nEventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup,\n                                const EventBits_t uxBitsToSet )\n{\n    ListItem_t * pxListItem;\n    ListItem_t * pxNext;\n    ListItem_t const * pxListEnd;\n    List_t const * pxList;\n    EventBits_t uxBitsToClear = 0, uxBitsWaitedFor, uxControlBits;\n    EventGroup_t * pxEventBits = xEventGroup;\n    BaseType_t xMatchFound = pdFALSE;\n\n    /* Check the user is not attempting to set the bits used by the kernel\n     * itself. */\n    configASSERT( xEventGroup );\n    configASSERT( ( uxBitsToSet & eventEVENT_BITS_CONTROL_BYTES ) == 0 );\n\n    pxList = &( pxEventBits->xTasksWaitingForBits );\n    pxListEnd = listGET_END_MARKER( pxList ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */\n    vTaskSuspendAll();\n    {\n        traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet );\n\n        pxListItem = listGET_HEAD_ENTRY( pxList );\n\n        /* Set the bits. */\n        pxEventBits->uxEventBits |= uxBitsToSet;\n\n        /* See if the new bit value should unblock any tasks. */\n        while( pxListItem != pxListEnd )\n        {\n            pxNext = listGET_NEXT( pxListItem );\n            uxBitsWaitedFor = listGET_LIST_ITEM_VALUE( pxListItem );\n            xMatchFound = pdFALSE;\n\n            /* Split the bits waited for from the control bits. */\n            uxControlBits = uxBitsWaitedFor & eventEVENT_BITS_CONTROL_BYTES;\n            uxBitsWaitedFor &= ~eventEVENT_BITS_CONTROL_BYTES;\n\n            if( ( uxControlBits & eventWAIT_FOR_ALL_BITS ) == ( EventBits_t ) 0 )\n            {\n                /* Just looking for single bit being set. */\n                if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) != ( EventBits_t ) 0 )\n                {\n                    xMatchFound = pdTRUE;\n                }\n                else\n                {\n                    mtCOVERAGE_TEST_MARKER();\n                }\n            }\n            else if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) == uxBitsWaitedFor )\n            {\n                /* All bits are set. */\n                xMatchFound = pdTRUE;\n            }\n            else\n            {\n                /* Need all bits to be set, but not all the bits were set. */\n            }\n\n            if( xMatchFound != pdFALSE )\n            {\n                /* The bits match.  Should the bits be cleared on exit? */\n                if( ( uxControlBits & eventCLEAR_EVENTS_ON_EXIT_BIT ) != ( EventBits_t ) 0 )\n                {\n                    uxBitsToClear |= uxBitsWaitedFor;\n                }\n                else\n                {\n                    mtCOVERAGE_TEST_MARKER();\n                }\n\n                /* Store the actual event flag value in the task's event list\n                 * item before removing the task from the event list.  The\n                 * eventUNBLOCKED_DUE_TO_BIT_SET bit is set so the task knows\n                 * that is was unblocked due to its required bits matching, rather\n                 * than because it timed out. */\n                vTaskRemoveFromUnorderedEventList( pxListItem, pxEventBits->uxEventBits | eventUNBLOCKED_DUE_TO_BIT_SET );\n            }\n\n            /* Move onto the next list item.  Note pxListItem->pxNext is not\n             * used here as the list item may have been removed from the event list\n             * and inserted into the ready/pending reading list. */\n            pxListItem = pxNext;\n        }\n\n        /* Clear any bits that matched when the eventCLEAR_EVENTS_ON_EXIT_BIT\n         * bit was set in the control word. */\n        pxEventBits->uxEventBits &= ~uxBitsToClear;\n    }\n    ( void ) xTaskResumeAll();\n\n    return pxEventBits->uxEventBits;\n}\n/*-----------------------------------------------------------*/\n\nvoid vEventGroupDelete( EventGroupHandle_t xEventGroup )\n{\n    EventGroup_t * pxEventBits = xEventGroup;\n    const List_t * pxTasksWaitingForBits;\n\n    configASSERT( pxEventBits );\n\n    pxTasksWaitingForBits = &( pxEventBits->xTasksWaitingForBits );\n\n    vTaskSuspendAll();\n    {\n        traceEVENT_GROUP_DELETE( xEventGroup );\n\n        while( listCURRENT_LIST_LENGTH( pxTasksWaitingForBits ) > ( UBaseType_t ) 0 )\n        {\n            /* Unblock the task, returning 0 as the event list is being deleted\n             * and cannot therefore have any bits set. */\n            configASSERT( pxTasksWaitingForBits->xListEnd.pxNext != ( const ListItem_t * ) &( pxTasksWaitingForBits->xListEnd ) );\n            vTaskRemoveFromUnorderedEventList( pxTasksWaitingForBits->xListEnd.pxNext, eventUNBLOCKED_DUE_TO_BIT_SET );\n        }\n    }\n    ( void ) xTaskResumeAll();\n\n    #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) )\n    {\n        /* The event group can only have been allocated dynamically - free\n         * it again. */\n        vPortFree( pxEventBits );\n    }\n    #elif ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )\n    {\n        /* The event group could have been allocated statically or\n         * dynamically, so check before attempting to free the memory. */\n        if( pxEventBits->ucStaticallyAllocated == ( uint8_t ) pdFALSE )\n        {\n            vPortFree( pxEventBits );\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n    }\n    #endif /* configSUPPORT_DYNAMIC_ALLOCATION */\n}\n/*-----------------------------------------------------------*/\n\n/* For internal use only - execute a 'set bits' command that was pended from\n * an interrupt. */\nvoid vEventGroupSetBitsCallback( void * pvEventGroup,\n                                 const uint32_t ulBitsToSet )\n{\n    ( void ) xEventGroupSetBits( pvEventGroup, ( EventBits_t ) ulBitsToSet ); /*lint !e9079 Can't avoid cast to void* as a generic timer callback prototype. Callback casts back to original type so safe. */\n}\n/*-----------------------------------------------------------*/\n\n/* For internal use only - execute a 'clear bits' command that was pended from\n * an interrupt. */\nvoid vEventGroupClearBitsCallback( void * pvEventGroup,\n                                   const uint32_t ulBitsToClear )\n{\n    ( void ) xEventGroupClearBits( pvEventGroup, ( EventBits_t ) ulBitsToClear ); /*lint !e9079 Can't avoid cast to void* as a generic timer callback prototype. Callback casts back to original type so safe. */\n}\n/*-----------------------------------------------------------*/\n\nstatic BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits,\n                                        const EventBits_t uxBitsToWaitFor,\n                                        const BaseType_t xWaitForAllBits )\n{\n    BaseType_t xWaitConditionMet = pdFALSE;\n\n    if( xWaitForAllBits == pdFALSE )\n    {\n        /* Task only has to wait for one bit within uxBitsToWaitFor to be\n         * set.  Is one already set? */\n        if( ( uxCurrentEventBits & uxBitsToWaitFor ) != ( EventBits_t ) 0 )\n        {\n            xWaitConditionMet = pdTRUE;\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n    }\n    else\n    {\n        /* Task has to wait for all the bits in uxBitsToWaitFor to be set.\n         * Are they set already? */\n        if( ( uxCurrentEventBits & uxBitsToWaitFor ) == uxBitsToWaitFor )\n        {\n            xWaitConditionMet = pdTRUE;\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n    }\n\n    return xWaitConditionMet;\n}\n/*-----------------------------------------------------------*/\n\n#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )\n\n    BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup,\n                                          const EventBits_t uxBitsToSet,\n                                          BaseType_t * pxHigherPriorityTaskWoken )\n    {\n        BaseType_t xReturn;\n\n        traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet );\n        xReturn = xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken ); /*lint !e9087 Can't avoid cast to void* as a generic callback function not specific to this use case. Callback casts back to original type so safe. */\n\n        return xReturn;\n    }\n\n#endif /* if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TRACE_FACILITY == 1 )\n\n    UBaseType_t uxEventGroupGetNumber( void * xEventGroup )\n    {\n        UBaseType_t xReturn;\n        EventGroup_t const * pxEventBits = ( EventGroup_t * ) xEventGroup; /*lint !e9087 !e9079 EventGroupHandle_t is a pointer to an EventGroup_t, but EventGroupHandle_t is kept opaque outside of this file for data hiding purposes. */\n\n        if( xEventGroup == NULL )\n        {\n            xReturn = 0;\n        }\n        else\n        {\n            xReturn = pxEventBits->uxEventGroupNumber;\n        }\n\n        return xReturn;\n    }\n\n#endif /* configUSE_TRACE_FACILITY */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TRACE_FACILITY == 1 )\n\n    void vEventGroupSetNumber( void * xEventGroup,\n                               UBaseType_t uxEventGroupNumber )\n    {\n        ( ( EventGroup_t * ) xEventGroup )->uxEventGroupNumber = uxEventGroupNumber; /*lint !e9087 !e9079 EventGroupHandle_t is a pointer to an EventGroup_t, but EventGroupHandle_t is kept opaque outside of this file for data hiding purposes. */\n    }\n\n#endif /* configUSE_TRACE_FACILITY */\n/*-----------------------------------------------------------*/\n"
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    "path": "FreeRTOS-comparison/examples/blinky/FreeRTOSConfig.h",
    "content": "/* Modified by Quantum Leaps\n */\n/*\n * FreeRTOS V202212.00\n * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef FREERTOS_CONFIG_H\n#define FREERTOS_CONFIG_H\n\n/*-----------------------------------------------------------\n * Application specific definitions.\n *\n * These definitions should be adjusted for your particular hardware and\n * application requirements.\n *\n * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\n * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\n *\n * See http://www.freertos.org/a00110.html\n *----------------------------------------------------------*/\n\n#define configUSE_PREEMPTION          1\n#define configUSE_IDLE_HOOK           1\n#define configUSE_TICK_HOOK           1\n#define configCPU_CLOCK_HZ            ( SystemCoreClock )\n#define configTICK_RATE_HZ            ( ( TickType_t )100 )\n#define configMAX_PRIORITIES          ( 32 )\n#define configMINIMAL_STACK_SIZE      ( ( unsigned short )128 )\n#define configTOTAL_HEAP_SIZE         ( ( size_t ) ( 0 ) )\n#define configMAX_TASK_NAME_LEN       ( 16 )\n#define configUSE_TRACE_FACILITY      0\n#define configUSE_16_BIT_TICKS        0\n#define configIDLE_SHOULD_YIELD       0\n#define configUSE_MUTEXES             0\n\n/* use only the static allocation */\n#define configSUPPORT_DYNAMIC_ALLOCATION 0\n#define configSUPPORT_STATIC_ALLOCATION  1\n\n/* Set the following definitions to 1 to include the API function, or zero\nto exclude the API function. */\n\n#define INCLUDE_vTaskPrioritySet      1\n#define INCLUDE_uxTaskPriorityGet     1\n#define INCLUDE_vTaskDelete           0\n#define INCLUDE_vTaskCleanUpResources 0\n#define INCLUDE_vTaskSuspend          0\n#define INCLUDE_vTaskDelayUntil       0\n#define INCLUDE_vTaskDelay            1\n\n/* This is the raw value as per the Cortex-M NVIC.  Values can be 255\n(lowest) to 0 (1?) (highest). */\n#define configKERNEL_INTERRUPT_PRIORITY         255\n/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!\nSee http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */\n#define configMAX_SYSCALL_INTERRUPT_PRIORITY    191 /* equivalent to 0xb0, or priority 11. */\n\n/* This is the value being used as per the ST library which permits 16\npriority values, 0 to 15.  This must correspond to the\nconfigKERNEL_INTERRUPT_PRIORITY setting.  Here 15 corresponds to the lowest\nNVIC value of 255. */\n#define configLIBRARY_KERNEL_INTERRUPT_PRIORITY 15\n\n/* Prevent the inclusion of items the assembler will not understand in assembly files. */\n#ifndef __IAR_SYSTEMS_ASM__\n    #define configASSERT( x ) if( ( x ) == 0 ) assert_failed( __FILE__, __LINE__ );\n\n    void assert_failed(char const * const module, int location);\n    extern uint32_t SystemCoreClock;\n#endif\n\n/* Map the FreeRTOS port interrupt handlers to their CMSIS standard names. */\n#define vPortSVCHandler     SVC_Handler\n#define xPortPendSVHandler  PendSV_Handler\n#define xPortSysTickHandler SysTick_Handler\n\n#endif /* FREERTOS_CONFIG_H */\n"
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<FilePath>..\\bsp.h</FilePath>\n            </File>\n            <File>\n              <FileName>main.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\main.c</FilePath>\n            </File>\n            <File>\n              <FileName>bsp_nucleo-l053r8.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\bsp_nucleo-l053r8.c</FilePath>\n            </File>\n            <File>\n              <FileName>blinky.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\blinky.c</FilePath>\n            </File>\n            <File>\n              <FileName>blinky.h</FileName>\n              <FileType>5</FileType>\n              <FilePath>..\\blinky.h</FilePath>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>nucleo-l053r8</GroupName>\n          <Files>\n            <File>\n              <FileName>startup_stm32l053xx.s</FileName>\n              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  },
  {
    "path": "FreeRTOS-comparison/examples/blinky/blinky.c",
    "content": "/*============================================================================\n* Blinky1 task (adapted for FreeRTOS)\n*\n* Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n*\n* SPDX-License-Identifier: MIT\n*\n* Permission is hereby granted, free of charge, to any person obtaining a\n* copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included in\n* all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n============================================================================*/\n#include \"FreeRTOS.h\"   /* FreeRTOS API */\n#include \"task.h\"       /* FreeRTOS task API */\n\n#include \"blinky.h\"     /* application shared interface */\n#include \"bsp.h\"        /* Board Support Package interface */\n\n/*..........................................................................*/\nvoid Blinky_task(void *pvParameters) {\n    (void)pvParameters; /* unused parameter */\n\n    while (1) {\n        BSP_ledOn();\n        vTaskDelay(BSP_TICKS_PER_SEC / 4U);\n        BSP_ledOff();\n        vTaskDelay(BSP_TICKS_PER_SEC * 3U/4U);\n    }\n}\n"
  },
  {
    "path": "FreeRTOS-comparison/examples/blinky/blinky.h",
    "content": "/*============================================================================\n* Super-Simple Tasker (SST/C) Example\n*\n* Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n*\n* SPDX-License-Identifier: MIT\n*\n* Permission is hereby granted, free of charge, to any person obtaining a\n* copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included in\n* all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n============================================================================*/\n#ifndef BLINKY_H_\n#define BLINKY_H_\n\n/*--------------------------------------------------------------------------*/\n/* Tasks and event queues for this application... */\n\nvoid Blinky_task(void *pvParameters);\n\n/* general convenience utilities -------------------------------------------*/\n#ifndef ARRAY_NELEM\n/*! convenience macro to provide the number of elements in the array a_ */\n#define ARRAY_NELEM(a_)  (sizeof(a_) / sizeof((a_)[0]))\n#endif /* ARRAY_NELEM */\n\n#endif /* BLINKY_BUTTON_H_ */\n"
  },
  {
    "path": "FreeRTOS-comparison/examples/blinky/bsp.h",
    "content": "/*============================================================================\n* FreeRTOS Example (adaptation of the SST blinky_button example)\n*\n* Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n*\n* SPDX-License-Identifier: MIT\n*\n* Permission is hereby granted, free of charge, to any person obtaining a\n* copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included in\n* all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n============================================================================*/\n#ifndef BSP_H_\n#define BSP_H_\n\n#define BSP_TICKS_PER_SEC configTICK_RATE_HZ\n\nvoid BSP_init(void);\n\nvoid BSP_ledOn(void);\nvoid BSP_ledOff(void);\n\n#endif /* BSP_H_ */\n"
  },
  {
    "path": "FreeRTOS-comparison/examples/blinky/bsp_nucleo-l053r8.c",
    "content": "/*============================================================================\n* FreeRTOS Example (adaptation of the SST blinky_button example)\n*\n* Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n*\n* SPDX-License-Identifier: MIT\n*\n* Permission is hereby granted, free of charge, to any person obtaining a\n* copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included in\n* all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n============================================================================*/\n#include \"FreeRTOS.h\"   /* FreeRTOS API */\n#include \"task.h\"       /* FreeRTOS task API */\n#include \"queue.h\"      /* FreeRTOS queue API */\n\n#include \"blinky.h\"\n#include \"bsp.h\"\n\n#include \"stm32l0xx.h\"  /* CMSIS-compliant header file for the MCU used */\n/* add other drivers if necessary... */\n\n/* Local-scope defines -----------------------------------------------------*/\n\n/* test pins on GPIO PA */\n#define LED_PIN   5U /* LED LD2-Green */\n\n/* Function Prototype ======================================================*/\nvoid vApplicationTickHook(void);\nvoid vApplicationIdleHook(void);\nvoid vApplicationStackOverflowHook(TaskHandle_t xTask, char *pcTaskName);\nvoid vApplicationGetIdleTaskMemory(StaticTask_t **ppxIdleTaskTCBBuffer,\n                                   StackType_t **ppxIdleTaskStackBuffer,\n                                   uint32_t *pulIdleTaskStackSize);\nvoid vApplicationGetTimerTaskMemory(StaticTask_t **ppxTimerTaskTCBBuffer,\n                                    StackType_t **ppxTimerTaskStackBuffer,\n                                    uint32_t *pulTimerTaskStackSize);\n\n/* Hooks ===================================================================*/\n/* Application hooks used in this project ==================================*/\n/* NOTE: only the \"FromISR\" API variants are allowed in vApplicationTickHook*/\nvoid vApplicationTickHook(void) {\n}\n\n/*..........................................................................*/\nvoid vApplicationIdleHook(void) {\n#ifdef NDEBUG\n    /* Put the CPU and peripherals to the low-power mode.\n    * you might need to customize the clock management for your application,\n    * see the datasheet for your particular Cortex-M3 MCU.\n    */\n    __WFI(); /* Wait-For-Interrupt */\n#endif\n}\n/*..........................................................................*/\nvoid vApplicationStackOverflowHook(TaskHandle_t xTask, char *pcTaskName) {\n    (void)xTask;\n    (void)pcTaskName;\n    /* ERROR!!! */\n}\n/*..........................................................................*/\n/* configSUPPORT_STATIC_ALLOCATION is set to 1, so the application must\n * provide an implementation of vApplicationGetIdleTaskMemory() to provide\n * the memory that is used by the Idle task.\n */\nvoid vApplicationGetIdleTaskMemory(StaticTask_t **ppxIdleTaskTCBBuffer,\n                                   StackType_t **ppxIdleTaskStackBuffer,\n                                   uint32_t *pulIdleTaskStackSize)\n{\n    /* If the buffers to be provided to the Idle task are declared inside\n     * this function then they must be declared static - otherwise they will\n     * be allocated on the stack and so not exists after this function exits.\n     */\n    static StaticTask_t xIdleTaskTCB;\n    static StackType_t  uxIdleTaskStack[configMINIMAL_STACK_SIZE];\n\n    /* Pass out a pointer to the StaticTask_t structure in which the\n     * Idle task's state will be stored.\n     */\n    *ppxIdleTaskTCBBuffer = &xIdleTaskTCB;\n\n    /* Pass out the array that will be used as the Idle task's stack. */\n    *ppxIdleTaskStackBuffer = &uxIdleTaskStack[0];\n\n    /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer.\n     * Note that, as the array is necessarily of type StackType_t,\n     * configMINIMAL_STACK_SIZE is specified in words, not bytes.\n     */\n    *pulIdleTaskStackSize = sizeof(uxIdleTaskStack) / sizeof(uxIdleTaskStack[0]);\n}\n/* BSP functions ===========================================================*/\nvoid BSP_init(void) {\n    /* Configure the MPU to prevent NULL-pointer dereferencing\n    * see: www.state-machine.com/null-pointer-protection-with-arm-cortex-m-mpu\n    */\n    MPU->RBAR = 0x0U                          /* base address (NULL) */\n                | MPU_RBAR_VALID_Msk          /* valid region */\n                | (MPU_RBAR_REGION_Msk & 7U); /* region #7 */\n    MPU->RASR = (7U << MPU_RASR_SIZE_Pos)     /* 2^(7+1) region */\n                | (0x0U << MPU_RASR_AP_Pos)   /* no-access region */\n                | MPU_RASR_ENABLE_Msk;        /* region enable */\n\n    MPU->CTRL = MPU_CTRL_PRIVDEFENA_Msk       /* enable background region */\n                | MPU_CTRL_ENABLE_Msk;        /* enable the MPU */\n    __ISB();\n    __DSB();\n\n    /* enable GPIO port PA clock */\n    RCC->IOPENR |= (1U << 0U);\n\n    /* set all used GPIOA pins as push-pull output, no pull-up, pull-down */\n    GPIOA->MODER  &= ~(3U << 2U*LED_PIN);\n    GPIOA->MODER  |=  (1U << 2U*LED_PIN);\n    GPIOA->OTYPER &= ~(1U <<    LED_PIN);\n    GPIOA->PUPDR  &= ~(3U << 2U*LED_PIN);\n}\n/*..........................................................................*/\nvoid BSP_ledOn(void)  { GPIOA->BSRR = (1U << LED_PIN);         } /* LED2 */\nvoid BSP_ledOff(void) { GPIOA->BSRR = (1U << (LED_PIN + 16U)); }\n\n/*..........................................................................*/\nvoid BSP_start(void) {\n    SystemCoreClockUpdate();\n\n    /* set up the SysTick timer to fire at BSP_TICKS_PER_SEC rate */\n    SysTick_Config((SystemCoreClock / BSP_TICKS_PER_SEC) + 1U);\n\n    /* set priorities of ISRs used in the system */\n    NVIC_SetPriority(SysTick_IRQn, 0U);\n    /* ... */\n}\n\n/* Assertion handler ======================================================*/\nvoid assert_failed(char const * const module, int const label);/* prototype */\nvoid assert_failed(char const * const module, int const label) {\n    /*\n    * NOTE: add here your application-specific error handling\n    */\n    (void)module;\n    (void)label;\n\n    /* set PRIMASK to disable interrupts and stop right here */\n    __asm volatile (\"cpsid i\");\n\n#ifndef NDEBUG\n    for (;;) { /* keep blinking LED2 */\n        BSP_ledOn();  /* turn LED2 on */\n        uint32_t volatile ctr;\n        for (ctr = 10000U; ctr > 0U; --ctr) {\n        }\n        BSP_ledOff(); /* turn LED2 off */\n        for (ctr = 10000U; ctr > 0U; --ctr) {\n        }\n    }\n#endif\n    NVIC_SystemReset();\n}\n\n/*****************************************************************************\n* NOTE1:\n* Only ISRs prioritized at or below the\n* configMAX_SYSCALL_INTERRUPT_PRIORITY level (i.e.,\n* with the numerical values of priorities equal or higher than\n* configMAX_SYSCALL_INTERRUPT_PRIORITY) are allowed to call any\n* QP/FreeRTOS services. These ISRs are \"kernel-aware\".\n*\n* Only ISRs prioritized at or below the configMAX_SYSCALL_INTERRUPT_PRIORITY\n* level (i.e., with the numerical values of priorities equal or higher than\n* configMAX_SYSCALL_INTERRUPT_PRIORITY) are allowed to call any QF services.\n* These ISRs are \"kernel-aware\".\n*\n* Conversely, any ISRs prioritized above the\n* configMAX_SYSCALL_INTERRUPT_PRIORITY priority level (i.e., with\n* the numerical values of priorities less than\n* configMAX_SYSCALL_INTERRUPT_PRIORITY) are never disabled and are\n* not aware of the kernel. Such \"kernel-unaware\" ISRs cannot call any\n* QP/FreeRTOS services. The only mechanism by which a \"kernel-unaware\" ISR\n* can communicate with the QF framework is by triggering a \"kernel-aware\"\n* ISR, which can post/publish events.\n*\n* For more information, see article \"Running the RTOS on a ARM Cortex-M Core\"\n* http://www.freertos.org/RTOS-Cortex-M3-M4.html\n*/\n\n"
  },
  {
    "path": "FreeRTOS-comparison/examples/blinky/main.c",
    "content": "/*============================================================================\n* FreeRTOS Example\n*\n* Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n*\n* SPDX-License-Identifier: MIT\n*\n* Permission is hereby granted, free of charge, to any person obtaining a\n* copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included in\n* all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n============================================================================*/\n#include \"FreeRTOS.h\"   /* FreeRTOS API */\n#include \"task.h\"       /* FreeRTOS task API */\n\n#include \"blinky.h\"     /* application shared interface */\n#include \"bsp.h\"        /* Board Support Package interface */\n\n/*..........................................................................*/\nint main() {\n    BSP_init(); /* initialize the Board Support Package */\n\n    /* instantiate and start all FreeRTOS tasks... */\n    TaskHandle_t th;\n\n    /* Blinky... */\n    static StaticTask_t Blinky_tcb;  /* task control block */\n    static StackType_t  Blinky_stack[configMINIMAL_STACK_SIZE];\n    th = xTaskCreateStatic(\n        &Blinky_task,                /* task function */\n        \"Blinky\",                    /* task priority */\n        ARRAY_NELEM(Blinky_stack),   /* stack length */\n        (void *)0,                   /* task param (not used) */\n        1U + tskIDLE_PRIORITY,       /* task priority */\n        Blinky_stack,                /* task stack */\n        &Blinky_tcb);                /* task control block */\n    configASSERT(th); /* task creation must succeed */\n\n    vTaskStartScheduler(); /* start the FreeRTOS scheduler... */\n    return 0; /* NOTE: the scheduler does NOT return */\n}\n\n"
  },
  {
    "path": "FreeRTOS-comparison/examples/blinky_button/FreeRTOSConfig.h",
    "content": "/* Modified by Quantum Leaps\n */\n/*\n * FreeRTOS V202212.00\n * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef FREERTOS_CONFIG_H\n#define FREERTOS_CONFIG_H\n\n/*-----------------------------------------------------------\n * Application specific definitions.\n *\n * These definitions should be adjusted for your particular hardware and\n * application requirements.\n *\n * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\n * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\n *\n * See http://www.freertos.org/a00110.html\n *----------------------------------------------------------*/\n\n#define configUSE_PREEMPTION          1\n#define configUSE_IDLE_HOOK           1\n#define configUSE_TICK_HOOK           1\n#define configCPU_CLOCK_HZ            ( SystemCoreClock )\n#define configTICK_RATE_HZ            ( ( TickType_t )100 )\n#define configMAX_PRIORITIES          ( 32 )\n#define configMINIMAL_STACK_SIZE      ( ( unsigned short )128 )\n#define configTOTAL_HEAP_SIZE         ( ( size_t ) ( 0 ) )\n#define configMAX_TASK_NAME_LEN       ( 16 )\n#define configUSE_TRACE_FACILITY      0\n#define configUSE_16_BIT_TICKS        0\n#define configIDLE_SHOULD_YIELD       0\n#define configUSE_MUTEXES             0\n\n/* use only the static allocation */\n#define configSUPPORT_DYNAMIC_ALLOCATION 0\n#define configSUPPORT_STATIC_ALLOCATION  1\n\n/* Set the following definitions to 1 to include the API function, or zero\nto exclude the API function. */\n\n#define INCLUDE_vTaskPrioritySet      1\n#define INCLUDE_uxTaskPriorityGet     1\n#define INCLUDE_vTaskDelete           0\n#define INCLUDE_vTaskCleanUpResources 0\n#define INCLUDE_vTaskSuspend          0\n#define INCLUDE_vTaskDelayUntil       0\n#define INCLUDE_vTaskDelay            1\n\n/* This is the raw value as per the Cortex-M NVIC.  Values can be 255\n(lowest) to 0 (1?) (highest). */\n#define configKERNEL_INTERRUPT_PRIORITY         255\n/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!\nSee http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */\n#define configMAX_SYSCALL_INTERRUPT_PRIORITY    191 /* equivalent to 0xb0, or priority 11. */\n\n/* This is the value being used as per the ST library which permits 16\npriority values, 0 to 15.  This must correspond to the\nconfigKERNEL_INTERRUPT_PRIORITY setting.  Here 15 corresponds to the lowest\nNVIC value of 255. */\n#define configLIBRARY_KERNEL_INTERRUPT_PRIORITY 15\n\n/* Prevent the inclusion of items the assembler will not understand in assembly files. */\n#ifndef __IAR_SYSTEMS_ASM__\n    #define configASSERT( x ) if( ( x ) == 0 ) assert_failed( __FILE__, __LINE__ );\n\n    void assert_failed(char const * const module, int location);\n    extern uint32_t SystemCoreClock;\n#endif\n\n/* Map the FreeRTOS port interrupt handlers to their CMSIS standard names. */\n#define vPortSVCHandler     SVC_Handler\n#define xPortPendSVHandler  PendSV_Handler\n#define xPortSysTickHandler SysTick_Handler\n\n#endif /* FREERTOS_CONFIG_H */\n"
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    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\" standalone=\"no\" ?>\n<Project xmlns:xsi=\"http://www.w3.org/2001/XMLSchema-instance\" xsi:noNamespaceSchemaLocation=\"project_projx.xsd\">\n\n  <SchemaVersion>2.1</SchemaVersion>\n\n  <Header>### uVision Project, (C) Keil Software</Header>\n\n  <Targets>\n    <Target>\n      <TargetName>nucleo-l053r8</TargetName>\n      <ToolsetNumber>0x4</ToolsetNumber>\n      <ToolsetName>ARM-ADS</ToolsetName>\n      <pCCUsed>6160000::V6.16::ARMCLANG</pCCUsed>\n      <uAC6>1</uAC6>\n      <TargetOption>\n        <TargetCommonOption>\n          <Device>STM32L053R8Tx</Device>\n          <Vendor>STMicroelectronics</Vendor>\n          <PackID>Keil.STM32L0xx_DFP.2.2.0</PackID>\n          <PackURL>http://www.keil.com/pack/</PackURL>\n          <Cpu>IRAM(0x20000000,0x00002000) IROM(0x08000000,0x00010000) CPUTYPE(\"Cortex-M0+\") CLOCK(12000000) ELITTLE</Cpu>\n          <FlashUtilSpec></FlashUtilSpec>\n          <StartupFile></StartupFile>\n          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  },
  {
    "path": "FreeRTOS-comparison/examples/blinky_button/blinky1.c",
    "content": "/*============================================================================\n* Blinky1 task (adapted for FreeRTOS)\n*\n* Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n*\n* SPDX-License-Identifier: MIT\n*\n* Permission is hereby granted, free of charge, to any person obtaining a\n* copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included in\n* all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n============================================================================*/\n#include \"FreeRTOS.h\"   /* FreeRTOS API */\n#include \"task.h\"       /* FreeRTOS task API */\n#include \"queue.h\"      /* FreeRTOS queue API */\n\n#include \"blinky_button.h\" /* application shared interface */\n#include \"bsp.h\"           /* Board Support Package interface */\n\n/*..........................................................................*/\ntypedef struct {    /* Blinky1 private data */\n    uint16_t toggles;\n    uint8_t ticks;\n    uint8_t tick_ctr;\n} Blinky1;\n\nstatic void Blinky1_init(Blinky1 * const me, Event const * const ie);\nstatic void Blinky1_dispatch(Blinky1 * const me, Event const * const e);\nstatic Blinky1 Blinky1_inst; /* the Blinky1 instance (Singleton) */\n\n/*..........................................................................*/\nvoid * const AO_Blinky1 = &Blinky1_inst; /* opaque AO pointer */\nQueueHandle_t QUEUE_Blinky1; /* FreeRTOS queue \"handle\" */\n\n/*..........................................................................*/\nvoid Blinky1_task(void *pvParameters) {\n    Blinky1 * const me = (Blinky1 *)pvParameters;\n    Blinky1_init(me, BSP_getWorkEvtBlinky1(0U));\n\n    while (1) {\n        /* wait for any event and receive it into object 'e' */\n        Event *e;\n        xQueueReceive(QUEUE_Blinky1, &e, portMAX_DELAY); /* BLOCKING! */\n        configASSERT(e != (Event *)0);\n        Blinky1_dispatch(me, e);\n    }\n}\n\n/*..........................................................................*/\nstatic void Blinky1_init(Blinky1 * const me, Event const * const ie) {\n    /* the initial event must be provided and must be WORKLOAD_SIG */\n    configPRECONDITION((ie != (Event const *)0)\n                       && (ie->sig == BLINKY_WORK_SIG));\n\n    me->toggles = EVT_DOWNCAST(BlinkyWorkEvt, ie)->toggles;\n    me->ticks = EVT_DOWNCAST(BlinkyWorkEvt, ie)->ticks;\n    me->tick_ctr = me->ticks;\n}\n/*..........................................................................*/\nstatic void Blinky1_dispatch(Blinky1 * const me, Event const * const e) {\n    switch (e->sig) {\n        case TICK_SIG: {\n            --me->tick_ctr;\n            if (me->tick_ctr == 0U) {\n                me->tick_ctr = me->ticks;\n                for (uint16_t i = me->toggles; i > 0U; --i) {\n                    BSP_d5on();\n                    BSP_d5off();\n                }\n            }\n            break;\n        }\n        case BLINKY_WORK_SIG: {\n            BSP_d5on();\n            me->toggles = EVT_DOWNCAST(BlinkyWorkEvt, e)->toggles;\n            me->ticks = EVT_DOWNCAST(BlinkyWorkEvt, e)->ticks;\n            BSP_d5off();\n            break;\n        }\n        default: {\n            configASSERT(0); /* unexpected event */\n            break;\n        }\n    }\n}\n"
  },
  {
    "path": "FreeRTOS-comparison/examples/blinky_button/blinky3.c",
    "content": "/*============================================================================\n* Blinky3 task (adapted for FreeRTOS)\n*\n* Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n*\n* SPDX-License-Identifier: MIT\n*\n* Permission is hereby granted, free of charge, to any person obtaining a\n* copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included in\n* all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n============================================================================*/\n#include \"FreeRTOS.h\"   /* FreeRTOS API */\n#include \"task.h\"       /* FreeRTOS task API */\n#include \"queue.h\"      /* FreeRTOS queue API */\n\n#include \"blinky_button.h\" /* application shared interface */\n#include \"bsp.h\"           /* Board Support Package interface */\n\n/*..........................................................................*/\ntypedef struct {    /* Blinky3 task */\n    uint16_t toggles;\n    uint8_t ticks;\n    uint8_t tick_ctr;\n} Blinky3;\n\nstatic void Blinky3_init(Blinky3 * const me, Event const * const ie);\nstatic void Blinky3_dispatch(Blinky3 * const me, Event const * const e);\nstatic Blinky3 Blinky3_inst; /* the Blinky3 instance (Singleton) */\n\n/*..........................................................................*/\nvoid * const AO_Blinky3 = &Blinky3_inst; /* opaque AO pointer */\nQueueHandle_t QUEUE_Blinky3; /* FreeRTOS queue \"handle\" */\n\n/*..........................................................................*/\nvoid Blinky3_task(void *pvParameters) {\n    Blinky3 * const me = (Blinky3 *)pvParameters;\n    Blinky3_init(me, BSP_getWorkEvtBlinky3(0U));\n\n    while (1) {\n        /* wait for any event and receive it into object 'e' */\n        Event *e;\n        xQueueReceive(QUEUE_Blinky3, &e, portMAX_DELAY); /* BLOCKING! */\n        configASSERT(e != (Event *)0);\n        Blinky3_dispatch(me, e);\n    }\n}\n\n/*..........................................................................*/\nstatic void Blinky3_init(Blinky3 * const me, Event const * const ie) {\n    /* the initial event must be provided and must be WORKLOAD_SIG */\n    configPRECONDITION((ie != (Event const *)0)\n                       && (ie->sig == BLINKY_WORK_SIG));\n\n    me->toggles = EVT_DOWNCAST(BlinkyWorkEvt, ie)->toggles;\n    me->ticks = EVT_DOWNCAST(BlinkyWorkEvt, ie)->ticks;\n    me->tick_ctr = me->ticks;\n}\n/*..........................................................................*/\nstatic void Blinky3_dispatch(Blinky3 * const me, Event const * const e) {\n    switch (e->sig) {\n        case TICK_SIG: {\n            --me->tick_ctr;\n            if (me->tick_ctr == 0U) {\n                me->tick_ctr = me->ticks;\n                for (uint16_t i = me->toggles; i > 0U; --i) {\n                    BSP_d2on();\n                    BSP_d2off();\n                }\n            }\n            break;\n        }\n        case BLINKY_WORK_SIG: {\n            BSP_d2on();\n            me->toggles = EVT_DOWNCAST(BlinkyWorkEvt, e)->toggles;\n            me->ticks = EVT_DOWNCAST(BlinkyWorkEvt, e)->ticks;\n            BSP_d2off();\n            break;\n        }\n        default: {\n            configASSERT(0); /* unexpected event */\n            break;\n        }\n    }\n}\n"
  },
  {
    "path": "FreeRTOS-comparison/examples/blinky_button/blinky_button.h",
    "content": "/*============================================================================\n* Super-Simple Tasker (SST/C) Example\n*\n* Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n*\n* SPDX-License-Identifier: MIT\n*\n* Permission is hereby granted, free of charge, to any person obtaining a\n* copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included in\n* all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n============================================================================*/\n#ifndef BLINKY_BUTTON_H_\n#define BLINKY_BUTTON_H_\n\n/*--------------------------------------------------------------------------*/\n/* Event facilities... */\n/*! Event signal */\ntypedef uint16_t Signal;\n\n/*! Event class */\ntypedef struct {\n    Signal sig;\n} Event;\n\n/*! macro for downcasting Events to specific Event \"subclasses\" */\n#define EVT_DOWNCAST(EVT_, e_) ((EVT_ const *)(e_))\n\n/*--------------------------------------------------------------------------*/\n/* Custom Events for this application... */\n\nenum Signals {\n    TICK_SIG,\n    BUTTON_PRESSED_SIG,\n    BUTTON_RELEASED_SIG,\n    BLINKY_WORK_SIG,\n    FORWARD_PRESSED_SIG,\n    FORWARD_RELEASED_SIG,\n    /* ... */\n    MAX_SIG  /* the last signal */\n};\n\ntypedef struct {\n    Event super;      /* inherit Event */\n    uint16_t toggles; /* number of toggles of the signal */\n    uint8_t ticks;    /* number of clock ticks between */\n} BlinkyWorkEvt;\n\ntypedef struct {\n    Event super;      /* inherit Event */\n    uint16_t toggles; /* number of toggles of the signal */\n} ButtonWorkEvt;\n\n/*--------------------------------------------------------------------------*/\n/* Tasks and event queues for this application... */\n\nvoid Blinky1_task(void *pvParameters);\nextern void * const AO_Blinky1;  /* opaque task pointer */\nextern QueueHandle_t QUEUE_Blinky1; /* queue handle */\n\nvoid Blinky3_task(void *pvParameters);\nextern void * const AO_Blinky3;  /* opaque task pointer */\nextern QueueHandle_t QUEUE_Blinky3; /* queue handle */\n\nvoid Button2a_task(void *pvParameters);\nextern void * const AO_Button2a;  /* opaque task pointer */\nextern QueueHandle_t QUEUE_Button2a; /* queue handle */\n\nvoid Button2b_task(void *pvParameters);\nextern void * const AO_Button2b;  /* opaque task pointer */\nextern QueueHandle_t QUEUE_Button2b; /* queue handle */\n\n/* general convenience utilities -------------------------------------------*/\n#ifndef ARRAY_NELEM\n/*! convenience macro to provide the number of elements in the array a_ */\n#define ARRAY_NELEM(a_)  (sizeof(a_) / sizeof((a_)[0]))\n#endif /* ARRAY_NELEM */\n\n#endif /* BLINKY_BUTTON_H_ */\n"
  },
  {
    "path": "FreeRTOS-comparison/examples/blinky_button/bsp.h",
    "content": "/*============================================================================\n* FreeRTOS Example (adaptation of the SST blinky_button example)\n*\n* Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n*\n* SPDX-License-Identifier: MIT\n*\n* Permission is hereby granted, free of charge, to any person obtaining a\n* copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included in\n* all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n============================================================================*/\n#ifndef BSP_H_\n#define BSP_H_\n\n#define BSP_TICKS_PER_SEC configTICK_RATE_HZ\n\nvoid BSP_init(void);\n\nvoid BSP_d1on(void);\nvoid BSP_d1off(void);\n\nvoid BSP_d2on(void);\nvoid BSP_d2off(void);\n\nvoid BSP_d3on(void);\nvoid BSP_d3off(void);\n\nvoid BSP_d4on(void);\nvoid BSP_d4off(void);\n\nvoid BSP_d5on(void);\nvoid BSP_d5off(void);\n\nvoid BSP_d6on(void);\nvoid BSP_d6off(void);\n\n/* immutable events for Blinky tasks */\nEvent const *BSP_getWorkEvtBlinky1(uint8_t num);\nEvent const *BSP_getWorkEvtBlinky3(uint8_t num);\n\n#endif /* BSP_H_ */\n"
  },
  {
    "path": "FreeRTOS-comparison/examples/blinky_button/bsp_nucleo-l053r8.c",
    "content": "/*============================================================================\n* FreeRTOS Example (adaptation of the SST blinky_button example)\n*\n* Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n*\n* SPDX-License-Identifier: MIT\n*\n* Permission is hereby granted, free of charge, to any person obtaining a\n* copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included in\n* all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n============================================================================*/\n#include \"FreeRTOS.h\"   /* FreeRTOS API */\n#include \"task.h\"       /* FreeRTOS task API */\n#include \"queue.h\"      /* FreeRTOS queue API */\n\n#include \"blinky_button.h\"\n#include \"bsp.h\"\n\n#include \"stm32l0xx.h\"  /* CMSIS-compliant header file for the MCU used */\n/* add other drivers if necessary... */\n\n/* Local-scope defines -----------------------------------------------------*/\n\n/* test pins on GPIO PA */\n#define TST1_PIN  7U\n#define TST2_PIN  6U\n#define TST3_PIN  4U\n#define TST4_PIN  1U\n#define TST5_PIN  0U\n#define TST6_PIN  5U /* LED LD2-Green */\n\n/* buttons on GPIO PC */\n#define B1_PIN    13U\n\n/* Function Prototype ======================================================*/\nvoid vApplicationTickHook(void);\nvoid vApplicationIdleHook(void);\nvoid vApplicationStackOverflowHook(TaskHandle_t xTask, char *pcTaskName);\nvoid vApplicationGetIdleTaskMemory(StaticTask_t **ppxIdleTaskTCBBuffer,\n                                   StackType_t **ppxIdleTaskStackBuffer,\n                                   uint32_t *pulIdleTaskStackSize);\nvoid vApplicationGetTimerTaskMemory(StaticTask_t **ppxTimerTaskTCBBuffer,\n                                    StackType_t **ppxTimerTaskStackBuffer,\n                                    uint32_t *pulTimerTaskStackSize);\n\n/* Hooks ===================================================================*/\n/* Application hooks used in this project ==================================*/\n/* NOTE: only the \"FromISR\" API variants are allowed in vApplicationTickHook*/\nvoid vApplicationTickHook(void) {\n    BSP_d1on();\n\n    BaseType_t xHigherPriorityTaskWoken = pdFALSE;\n    BaseType_t qStatus;\n\n    /* immutable timeout event */\n    static Event const tickEvt = { TICK_SIG };\n    static Event const * const p_tickEvt = &tickEvt;\n    qStatus = xQueueSendFromISR(QUEUE_Blinky1,\n                  (void const *)&p_tickEvt,\n                  &xHigherPriorityTaskWoken);\n    configASSERT(qStatus == pdTRUE);\n    qStatus = xQueueSendFromISR(QUEUE_Blinky3,\n                  (void const *)&p_tickEvt,\n                  &xHigherPriorityTaskWoken);\n    configASSERT(qStatus == pdTRUE);\n\n    /* Perform the debouncing of buttons. The algorithm for debouncing\n    * adapted from the book \"Embedded Systems Dictionary\" by Jack Ganssle\n    * and Michael Barr, page 71.\n    */\n    static struct ButtonsDebouncing {\n        uint32_t depressed;\n        uint32_t previous;\n    } buttons = { 0U, 0U };\n    uint32_t current = ~GPIOC->IDR; /* read GPIO PortC */\n    uint32_t tmp = buttons.depressed; /* save the debounced depressed */\n    buttons.depressed |= (buttons.previous & current); /* set depressed */\n    buttons.depressed &= (buttons.previous | current); /* clear released */\n    buttons.previous   = current; /* update the history */\n    tmp ^= buttons.depressed;     /* changed debounced depressed */\n    if ((tmp & (1U << B1_PIN)) != 0U) { /* debounced B1 state changed? */\n        if ((buttons.depressed & (1U << B1_PIN)) != 0U) { /* depressed? */\n            /* immutable button-press event */\n            static ButtonWorkEvt const pressEvt = {\n                .super.sig = BUTTON_PRESSED_SIG,\n                .toggles = 60U\n            };\n            static Event const * const p_pressEvt = &pressEvt.super;\n            /* immutable forward-press event */\n            static ButtonWorkEvt const fPressEvt = {\n                .super.sig = FORWARD_PRESSED_SIG,\n                .toggles = 60U\n            };\n            static Event const * const p_fPressEvt = &fPressEvt.super;\n            qStatus = xQueueSendFromISR(QUEUE_Button2a,\n                          (void const *)&p_fPressEvt,\n                          &xHigherPriorityTaskWoken);\n            configASSERT(qStatus == pdTRUE);\n            qStatus = xQueueSendFromISR(QUEUE_Button2a,\n                          (void const *)&p_pressEvt,\n                          &xHigherPriorityTaskWoken);\n            configASSERT(qStatus == pdTRUE);\n        }\n        else { /* B1 is released */\n            /* immutable button-release event */\n            static ButtonWorkEvt const releaseEvt = {\n                .super.sig = BUTTON_RELEASED_SIG,\n                .toggles = 80U\n            };\n            static Event const * const p_releaseEvt = &releaseEvt.super;\n            /* immutable forward-release event */\n            static ButtonWorkEvt const fReleaseEvt = {\n                .super.sig = FORWARD_RELEASED_SIG,\n                .toggles = 80U\n            };\n            static Event const * const p_fReleaseEvt = &fReleaseEvt.super;\n            qStatus = xQueueSendFromISR(QUEUE_Button2a,\n                          (void *)&p_fReleaseEvt,\n                          &xHigherPriorityTaskWoken);\n            configASSERT(qStatus == pdTRUE);\n            qStatus = xQueueSendFromISR(QUEUE_Button2a,\n                          (void *)&p_releaseEvt,\n                          &xHigherPriorityTaskWoken);\n            configASSERT(qStatus == pdTRUE);\n        }\n    }\n\n    /* notify FreeRTOS to perform context switch from ISR, if needed */\n    portEND_SWITCHING_ISR(xHigherPriorityTaskWoken);\n\n    BSP_d1off();\n}\n\n/*..........................................................................*/\nvoid vApplicationIdleHook(void) {\n    BSP_d6on();  /* turn LED2 on */\n#ifdef NDEBUG\n    /* Put the CPU and peripherals to the low-power mode.\n    * you might need to customize the clock management for your application,\n    * see the datasheet for your particular Cortex-M3 MCU.\n    */\n    BSP_d6off(); /* turn LED2 off */\n    __WFI(); /* Wait-For-Interrupt */\n    BSP_d6on();  /* turn LED2 on */\n#endif\n    BSP_d6off(); /* turn LED2 off */\n}\n/*..........................................................................*/\nvoid vApplicationStackOverflowHook(TaskHandle_t xTask, char *pcTaskName) {\n    (void)xTask;\n    (void)pcTaskName;\n    /* ERROR!!! */\n}\n/*..........................................................................*/\n/* configSUPPORT_STATIC_ALLOCATION is set to 1, so the application must\n * provide an implementation of vApplicationGetIdleTaskMemory() to provide\n * the memory that is used by the Idle task.\n */\nvoid vApplicationGetIdleTaskMemory(StaticTask_t **ppxIdleTaskTCBBuffer,\n                                   StackType_t **ppxIdleTaskStackBuffer,\n                                   uint32_t *pulIdleTaskStackSize)\n{\n    /* If the buffers to be provided to the Idle task are declared inside\n     * this function then they must be declared static - otherwise they will\n     * be allocated on the stack and so not exists after this function exits.\n     */\n    static StaticTask_t xIdleTaskTCB;\n    static StackType_t  uxIdleTaskStack[configMINIMAL_STACK_SIZE];\n\n    /* Pass out a pointer to the StaticTask_t structure in which the\n     * Idle task's state will be stored.\n     */\n    *ppxIdleTaskTCBBuffer = &xIdleTaskTCB;\n\n    /* Pass out the array that will be used as the Idle task's stack. */\n    *ppxIdleTaskStackBuffer = &uxIdleTaskStack[0];\n\n    /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer.\n     * Note that, as the array is necessarily of type StackType_t,\n     * configMINIMAL_STACK_SIZE is specified in words, not bytes.\n     */\n    *pulIdleTaskStackSize = sizeof(uxIdleTaskStack) / sizeof(uxIdleTaskStack[0]);\n}\n/* BSP functions ===========================================================*/\nvoid BSP_init(void) {\n    /* Configure the MPU to prevent NULL-pointer dereferencing\n    * see: www.state-machine.com/null-pointer-protection-with-arm-cortex-m-mpu\n    */\n    MPU->RBAR = 0x0U                          /* base address (NULL) */\n                | MPU_RBAR_VALID_Msk          /* valid region */\n                | (MPU_RBAR_REGION_Msk & 7U); /* region #7 */\n    MPU->RASR = (7U << MPU_RASR_SIZE_Pos)     /* 2^(7+1) region */\n                | (0x0U << MPU_RASR_AP_Pos)   /* no-access region */\n                | MPU_RASR_ENABLE_Msk;        /* region enable */\n\n    MPU->CTRL = MPU_CTRL_PRIVDEFENA_Msk       /* enable background region */\n                | MPU_CTRL_ENABLE_Msk;        /* enable the MPU */\n    __ISB();\n    __DSB();\n\n    /* enable GPIO port PA clock */\n    RCC->IOPENR |= (1U << 0U);\n\n    /* set all used GPIOA pins as push-pull output, no pull-up, pull-down */\n    GPIOA->MODER &=\n        ~((3U << 2U*TST1_PIN) | (3U << 2U*TST2_PIN) | (3U << 2U*TST3_PIN) |\n          (3U << 2U*TST4_PIN) | (3U << 2U*TST5_PIN) | (3U << 2U*TST6_PIN));\n    GPIOA->MODER |=\n         ((1U << 2U*TST1_PIN) | (1U << 2U*TST2_PIN) | (1U << 2U*TST3_PIN) |\n          (1U << 2U*TST4_PIN) | (1U << 2U*TST5_PIN) | (1U << 2U*TST6_PIN));\n    GPIOA->OTYPER &=\n        ~((1U <<    TST1_PIN) | (1U <<    TST2_PIN) | (1U <<    TST3_PIN) |\n          (1U <<    TST4_PIN) | (1U <<    TST5_PIN) | (1U <<    TST6_PIN));\n    GPIOA->PUPDR &=\n        ~((3U << 2U*TST1_PIN) | (3U << 2U*TST2_PIN) | (3U << 2U*TST3_PIN) |\n          (3U << 2U*TST4_PIN) | (3U << 2U*TST5_PIN) | (3U << 2U*TST6_PIN));\n\n    /* enable GPIOC clock port for the Button B1 */\n    RCC->IOPENR |=  (1U << 2U);\n\n    /* configure Button B1 pin on GPIOC as input, no pull-up, pull-down */\n    GPIOC->MODER &= ~(3U << 2U*B1_PIN);\n    GPIOC->PUPDR &= ~(3U << 2U*B1_PIN);\n}\n/*..........................................................................*/\nvoid BSP_d1on(void)  { GPIOA->BSRR = (1U << TST1_PIN);         }\nvoid BSP_d1off(void) { GPIOA->BSRR = (1U << (TST1_PIN + 16U)); }\n/*..........................................................................*/\nvoid BSP_d2on(void)  { GPIOA->BSRR = (1U << TST2_PIN);         }\nvoid BSP_d2off(void) { GPIOA->BSRR = (1U << (TST2_PIN + 16U)); }\n/*..........................................................................*/\nvoid BSP_d3on(void)  { GPIOA->BSRR = (1U << TST3_PIN);         }\nvoid BSP_d3off(void) { GPIOA->BSRR = (1U << (TST3_PIN + 16U)); }\n/*..........................................................................*/\nvoid BSP_d4on(void)  { GPIOA->BSRR = (1U << TST4_PIN);         }\nvoid BSP_d4off(void) { GPIOA->BSRR = (1U << (TST4_PIN + 16U)); }\n/*..........................................................................*/\nvoid BSP_d5on(void)  { GPIOA->BSRR = (1U << TST5_PIN);         }\nvoid BSP_d5off(void) { GPIOA->BSRR = (1U << (TST5_PIN + 16U)); }\n/*..........................................................................*/\nvoid BSP_d6on(void)  { GPIOA->BSRR = (1U << TST6_PIN);         } /* LED2 */\nvoid BSP_d6off(void) { GPIOA->BSRR = (1U << (TST6_PIN + 16U)); }\n\n/*..........................................................................*/\nEvent const *BSP_getWorkEvtBlinky1(uint8_t num) {\n    /* immutable work events for Blinky1 */\n    static BlinkyWorkEvt const workBlinky1[] = {\n        {\n            .super.sig = BLINKY_WORK_SIG,\n            .toggles = 40U,\n            .ticks = 5U,\n        },\n        {\n            .super.sig = BLINKY_WORK_SIG,\n            .toggles = 30U,\n            .ticks = 7U,\n        }\n    };\n    /* must be in range */\n    configPRECONDITION(num < sizeof(workBlinky1)/sizeof(workBlinky1[0]));\n    return &workBlinky1[num].super;\n}\n/*..........................................................................*/\nEvent const *BSP_getWorkEvtBlinky3(uint8_t num) {\n    /* immutable work events for Blinky3 */\n    static BlinkyWorkEvt const workBlinky3[] = {\n        {\n            .super.sig = BLINKY_WORK_SIG,\n            .toggles = 20U,\n            .ticks = 5U,\n        },\n        {\n            .super.sig = BLINKY_WORK_SIG,\n            .toggles = 10U,\n            .ticks = 3U,\n        }\n    };\n    /* must be in range */\n    configPRECONDITION(num < sizeof(workBlinky3)/sizeof(workBlinky3[0]));\n    return &workBlinky3[num].super;\n}\n\n/*..........................................................................*/\nvoid BSP_start(void) {\n    SystemCoreClockUpdate();\n\n    /* set up the SysTick timer to fire at BSP_TICKS_PER_SEC rate */\n    SysTick_Config((SystemCoreClock / BSP_TICKS_PER_SEC) + 1U);\n\n    /* set priorities of ISRs used in the system */\n    NVIC_SetPriority(SysTick_IRQn, 0U);\n    /* ... */\n}\n\n/* Assertion handler ======================================================*/\nvoid assert_failed(char const * const module, int const label);/* prototype */\nvoid assert_failed(char const * const module, int const label) {\n    /*\n    * NOTE: add here your application-specific error handling\n    */\n    (void)module;\n    (void)label;\n\n    /* set PRIMASK to disable interrupts and stop right here */\n    __asm volatile (\"cpsid i\");\n\n#ifndef NDEBUG\n    for (;;) { /* keep blinking LED2 */\n        BSP_d6on();  /* turn LED2 on */\n        uint32_t volatile ctr;\n        for (ctr = 10000U; ctr > 0U; --ctr) {\n        }\n        BSP_d6off(); /* turn LED2 off */\n        for (ctr = 10000U; ctr > 0U; --ctr) {\n        }\n    }\n#endif\n    NVIC_SystemReset();\n}\n\n/*****************************************************************************\n* NOTE1:\n* Only ISRs prioritized at or below the\n* configMAX_SYSCALL_INTERRUPT_PRIORITY level (i.e.,\n* with the numerical values of priorities equal or higher than\n* configMAX_SYSCALL_INTERRUPT_PRIORITY) are allowed to call any\n* QP/FreeRTOS services. These ISRs are \"kernel-aware\".\n*\n* Only ISRs prioritized at or below the configMAX_SYSCALL_INTERRUPT_PRIORITY\n* level (i.e., with the numerical values of priorities equal or higher than\n* configMAX_SYSCALL_INTERRUPT_PRIORITY) are allowed to call any QF services.\n* These ISRs are \"kernel-aware\".\n*\n* Conversely, any ISRs prioritized above the\n* configMAX_SYSCALL_INTERRUPT_PRIORITY priority level (i.e., with\n* the numerical values of priorities less than\n* configMAX_SYSCALL_INTERRUPT_PRIORITY) are never disabled and are\n* not aware of the kernel. Such \"kernel-unaware\" ISRs cannot call any\n* QP/FreeRTOS services. The only mechanism by which a \"kernel-unaware\" ISR\n* can communicate with the QF framework is by triggering a \"kernel-aware\"\n* ISR, which can post/publish events.\n*\n* For more information, see article \"Running the RTOS on a ARM Cortex-M Core\"\n* http://www.freertos.org/RTOS-Cortex-M3-M4.html\n*/\n\n"
  },
  {
    "path": "FreeRTOS-comparison/examples/blinky_button/button2a.c",
    "content": "/*============================================================================\n* Button2a task (adapted for FreeRTOS)\n*\n* Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n*\n* SPDX-License-Identifier: MIT\n*\n* Permission is hereby granted, free of charge, to any person obtaining a\n* copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included in\n* all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n============================================================================*/\n#include \"FreeRTOS.h\"   /* FreeRTOS API */\n#include \"task.h\"       /* FreeRTOS task API */\n#include \"queue.h\"      /* FreeRTOS queue API */\n\n#include \"blinky_button.h\" /* application shared interface */\n#include \"bsp.h\"           /* Board Support Package interface */\n\n/*..........................................................................*/\ntypedef struct {    /* Button2a task */\n    /* add internal variables for this AO... */\n} Button2a;\n\nstatic void Button2a_init(Button2a * const me, Event const * const ie);\nstatic void Button2a_dispatch(Button2a * const me, Event const * const e);\nstatic Button2a Button2a_inst; /* the Button2a instance (Singleton) */\n\n/*..........................................................................*/\nvoid * const AO_Button2a = &Button2a_inst; /* opaque AO pointer */\nQueueHandle_t QUEUE_Button2a; /* FreeRTOS queue \"handle\" */\n\n/*..........................................................................*/\nvoid Button2a_task(void *pvParameters) {\n    Button2a * const me = (Button2a *)pvParameters;\n    Button2a_init(me, (Event const *)0);\n\n    while (1) {\n        /* wait for any event and receive it into object 'e' */\n        Event *e;\n        xQueueReceive(QUEUE_Button2a, &e, portMAX_DELAY); /* BLOCKING! */\n        configASSERT(e != (Event *)0);\n        Button2a_dispatch(me, e);\n    }\n}\n\n/*..........................................................................*/\nstatic void Button2a_init(Button2a * const me, Event const * const ie) {\n    (void)me;\n    (void)ie;\n}\n/*..........................................................................*/\nstatic void Button2a_dispatch(Button2a * const me, Event const * const e) {\n    (void)me;\n    BaseType_t qStatus;\n    Event const *pe;\n    switch (e->sig) {\n        case BUTTON_PRESSED_SIG: {\n            BSP_d4on();\n            /* Button2a --> Blinky1 */\n            pe = BSP_getWorkEvtBlinky1(1U);\n            qStatus = xQueueSend(QUEUE_Blinky1,\n                                 (void const *)&pe, (TickType_t)0);\n            configASSERT(qStatus == pdTRUE);\n            BSP_d4off();\n\n            for (uint16_t i = EVT_DOWNCAST(ButtonWorkEvt, e)->toggles;\n                 i > 0U; --i)\n            {\n                BSP_d4on();\n                BSP_d4off();\n            }\n            break;\n        }\n        case FORWARD_PRESSED_SIG: {\n            BSP_d4on();\n            /* immutable event can be forwarded to another Task */\n            /* Button2a --> Button2b */\n            qStatus = xQueueSend(QUEUE_Button2b,\n                                 (void const *)&e, (TickType_t)0);\n            configASSERT(qStatus == pdTRUE);\n            BSP_d4off();\n            break;\n        }\n        case BUTTON_RELEASED_SIG: {\n            BSP_d4on();\n            /* Button2a --> Blinky1 */\n            pe = BSP_getWorkEvtBlinky1(0U);\n            qStatus = xQueueSend(QUEUE_Blinky1,\n                                 (void const *)&pe, (TickType_t)0);\n            configASSERT(qStatus == pdTRUE);\n            BSP_d4off();\n\n            for (uint16_t i = EVT_DOWNCAST(ButtonWorkEvt, e)->toggles;\n                 i > 0U; --i)\n            {\n                BSP_d4on();\n                BSP_d4off();\n            }\n            break;\n        }\n        case FORWARD_RELEASED_SIG: {\n            BSP_d4on();\n            /* immutable event can be forwarded to another Task */\n            /* Button2a --> Button2b */\n            qStatus = xQueueSend(QUEUE_Button2b,\n                                 (void const *)&e, (TickType_t)0);\n            configASSERT(qStatus == pdTRUE);\n            BSP_d4off();\n            break;\n        }\n        default: {\n            configASSERT(0); /* unexpected event */\n            break;\n        }\n    }\n}\n"
  },
  {
    "path": "FreeRTOS-comparison/examples/blinky_button/button2b.c",
    "content": "/*============================================================================\n* Button2b task (adapted for FreeRTOS)\n*\n* Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n*\n* SPDX-License-Identifier: MIT\n*\n* Permission is hereby granted, free of charge, to any person obtaining a\n* copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included in\n* all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n============================================================================*/\n#include \"FreeRTOS.h\"   /* FreeRTOS API */\n#include \"task.h\"       /* FreeRTOS task API */\n#include \"queue.h\"      /* FreeRTOS queue API */\n\n#include \"blinky_button.h\" /* application shared interface */\n#include \"bsp.h\"           /* Board Support Package interface */\n\n/*..........................................................................*/\ntypedef struct {    /* Button2b task */\n    /* add internal variables for this AO... */\n} Button2b;\n\nstatic void Button2b_init(Button2b * const me, Event const * const e);\nstatic void Button2b_dispatch(Button2b * const me, Event const * const e);\nstatic Button2b Button2b_inst; /* the Button2b instance */\n\n/*..........................................................................*/\nvoid * const AO_Button2b = &Button2b_inst; /* opaque AO pointer */\nQueueHandle_t QUEUE_Button2b; /* FreeRTOS queue \"handle\" */\n\n/*..........................................................................*/\nvoid Button2b_task(void *pvParameters) {\n    Button2b * const me = (Button2b *)pvParameters;\n    Button2b_init(me, (Event const *)0);\n\n    while (1) {\n        /* wait for any event and receive it into object 'e' */\n        Event *e;\n        xQueueReceive(QUEUE_Button2b, &e, portMAX_DELAY); /* BLOCKING! */\n\n        Button2b_dispatch(me, e);\n    }\n}\n\n/*..........................................................................*/\nstatic void Button2b_init(Button2b * const me, Event const * const ie) {\n    (void)me;\n    (void)ie;\n}\n/*..........................................................................*/\nstatic void Button2b_dispatch(Button2b * const me, Event const * const e) {\n    BaseType_t qStatus;\n    Event const *pe;\n    switch (e->sig) {\n        case FORWARD_PRESSED_SIG: {\n            BSP_d3on();\n            /* Button2b --> Blinky3 */\n            pe = BSP_getWorkEvtBlinky3(1U);\n            qStatus = xQueueSend(QUEUE_Blinky3,\n                                 (void const *)&pe, (TickType_t)0);\n            configASSERT(qStatus == pdTRUE);\n            BSP_d3off();\n\n            for (uint16_t i = EVT_DOWNCAST(ButtonWorkEvt, e)->toggles;\n                 i > 0U; --i)\n            {\n                BSP_d3on();\n                BSP_d3off();\n            }\n            break;\n        }\n        case FORWARD_RELEASED_SIG: {\n            BSP_d3on();\n            /* Button2b --> Blinky3 */\n            pe = BSP_getWorkEvtBlinky3(0U);\n            qStatus = xQueueSend(QUEUE_Blinky3,\n                                 (void const *)&pe, (TickType_t)0);\n            configASSERT(qStatus == pdTRUE);\n            BSP_d3off();\n\n            for (uint16_t i = EVT_DOWNCAST(ButtonWorkEvt, e)->toggles;\n                 i > 0U; --i)\n            {\n                BSP_d3on();\n                BSP_d3off();\n            }\n            break;\n        }\n        default: {\n            configASSERT(0); /* unexpected event */\n            break;\n        }\n    }\n}\n"
  },
  {
    "path": "FreeRTOS-comparison/examples/blinky_button/main.c",
    "content": "/*============================================================================\n* FreeRTOS Example\n*\n* Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n*\n* SPDX-License-Identifier: MIT\n*\n* Permission is hereby granted, free of charge, to any person obtaining a\n* copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included in\n* all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n============================================================================*/\n#include \"FreeRTOS.h\"   /* FreeRTOS API */\n#include \"task.h\"       /* FreeRTOS task API */\n#include \"queue.h\"      /* FreeRTOS queue API */\n\n#include \"blinky_button.h\" /* application shared interface */\n#include \"bsp.h\"           /* Board Support Package interface */\n\n/*..........................................................................*/\nint main() {\n    BSP_init(); /* initialize the Board Support Package */\n\n    /* instantiate and start all FreeRTOS tasks and queues... */\n    TaskHandle_t th;\n\n    /* Blinky1... */\n    static StaticQueue_t Blinky1_qcb; /* queue control block */\n    static Event *Blinky1_QSto[10];   /* queue storage */\n    QUEUE_Blinky1 = xQueueCreateStatic(\n        ARRAY_NELEM(Blinky1_QSto),    /* queue length */\n        sizeof(Event *),              /* item size */\n        (uint8_t *)Blinky1_QSto,      /* queue storage */\n        &Blinky1_qcb);                /* queue control block */\n    configASSERT(QUEUE_Blinky1);\n\n    static StaticTask_t Blinky1_tcb;  /* task control block */\n    static StackType_t  Blinky1_stack[configMINIMAL_STACK_SIZE];\n    th = xTaskCreateStatic(\n        &Blinky1_task,                /* task function */\n        \"Blinky1\",                    /* task priority */\n        ARRAY_NELEM(Blinky1_stack),   /* stack length */\n        AO_Blinky1,                   /* task param */\n        1U + tskIDLE_PRIORITY,        /* task priority */\n        Blinky1_stack,                /* task stack */\n        &Blinky1_tcb);                /* task control block */\n    configASSERT(th);\n\n    /* Button2a... */\n    static StaticQueue_t Button2a_qcb;/* queue control block */\n    static Event *Button2a_QSto[10];  /* queue storage */\n    QUEUE_Button2a = xQueueCreateStatic(\n        ARRAY_NELEM(Button2a_QSto),   /* queue length */\n        sizeof(Event *),              /* item size */\n        (uint8_t *)Button2a_QSto,     /* queue storage */\n        &Button2a_qcb);               /* queue control block */\n    configASSERT(QUEUE_Button2a);\n\n    static StaticTask_t Button2a_tcb; /* task control block */\n    static StackType_t  Button2a_stack[configMINIMAL_STACK_SIZE];\n    th = xTaskCreateStatic(\n        &Button2a_task,               /* task function */\n        \"Button2a\",                   /* task priority */\n        ARRAY_NELEM(Button2a_stack),  /* stack length */\n        AO_Button2a,                  /* task param */\n        2U + tskIDLE_PRIORITY,        /* task priority */\n        Button2a_stack,               /* task stack */\n        &Button2a_tcb);               /* task control block */\n    configASSERT(th);\n\n    /* Button2b... */\n    static StaticQueue_t Button2b_qcb;/* queue control block */\n    static Event *Button2b_QSto[10];  /* queue storage */\n    QUEUE_Button2b = xQueueCreateStatic(\n        ARRAY_NELEM(Button2b_QSto),   /* queue length */\n        sizeof(Event *),              /* item size */\n        (uint8_t *)Button2b_QSto,     /* queue storage */\n        &Button2b_qcb);               /* queue control block */\n    configASSERT(QUEUE_Button2b);\n\n    static StaticTask_t Button2b_tcb; /* task control block */\n    static StackType_t  Button2b_stack[configMINIMAL_STACK_SIZE];\n    th = xTaskCreateStatic(\n        &Button2b_task,               /* task function */\n        \"Button2b\",                   /* task priority */\n        ARRAY_NELEM(Button2b_stack),  /* stack length */\n        AO_Button2b,                  /* task param */\n        2U + tskIDLE_PRIORITY,        /* task priority */\n        Button2b_stack,               /* task stack */\n        &Button2b_tcb);               /* task control block */\n    configASSERT(th);\n\n    /* Blinky3... */\n    static StaticQueue_t Blinky3_qcb; /* queue control block */\n    static Event *Blinky3_QSto[10];   /* queue storage */\n    QUEUE_Blinky3 = xQueueCreateStatic(\n        ARRAY_NELEM(Blinky3_QSto),    /* queue length */\n        sizeof(Event *),              /* item size */\n        (uint8_t *)Blinky3_QSto,      /* queue storage */\n        &Blinky3_qcb);                /* queue control block */\n    configASSERT(QUEUE_Blinky3);\n\n    static StaticTask_t Blinky3_tcb;  /* task control block */\n    static StackType_t  Blinky3_stack[configMINIMAL_STACK_SIZE];\n    th = xTaskCreateStatic(\n        &Blinky3_task,                /* task function */\n        \"Blinky3\",                    /* task priority */\n        ARRAY_NELEM(Blinky3_stack),   /* stack length */\n        AO_Blinky3,                   /* task param */\n        3U + tskIDLE_PRIORITY,        /* task priority */\n        Blinky3_stack,                /* task stack */\n        &Blinky3_tcb);                /* task control block */\n    configASSERT(th);\n\n    vTaskStartScheduler(); /* start the FreeRTOS scheduler... */\n    return 0; /* NOTE: the scheduler does NOT return */\n}\n\n"
  },
  {
    "path": "FreeRTOS-comparison/include/FreeRTOS.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef INC_FREERTOS_H\n#define INC_FREERTOS_H\n\n/*\n * Include the generic headers required for the FreeRTOS port being used.\n */\n#include <stddef.h>\n\n/*\n * If stdint.h cannot be located then:\n *   + If using GCC ensure the -nostdint options is *not* being used.\n *   + Ensure the project's include path includes the directory in which your\n *     compiler stores stdint.h.\n *   + Set any compiler options necessary for it to support C99, as technically\n *     stdint.h is only mandatory with C99 (FreeRTOS does not require C99 in any\n *     other way).\n *   + The FreeRTOS download includes a simple stdint.h definition that can be\n *     used in cases where none is provided by the compiler.  The files only\n *     contains the typedefs required to build FreeRTOS.  Read the instructions\n *     in FreeRTOS/source/stdint.readme for more information.\n */\n#include <stdint.h> /* READ COMMENT ABOVE. */\n\n/* *INDENT-OFF* */\n#ifdef __cplusplus\n    extern \"C\" {\n#endif\n/* *INDENT-ON* */\n\n/* Application specific configuration options. */\n#include \"FreeRTOSConfig.h\"\n\n/* Basic FreeRTOS definitions. */\n#include \"projdefs.h\"\n\n/* Definitions specific to the port being used. */\n#include \"portable.h\"\n\n/* Must be defaulted before configUSE_NEWLIB_REENTRANT is used below. */\n#ifndef configUSE_NEWLIB_REENTRANT\n    #define configUSE_NEWLIB_REENTRANT    0\n#endif\n\n/* Required if struct _reent is used. */\n#if ( configUSE_NEWLIB_REENTRANT == 1 )\n\n/* Note Newlib support has been included by popular demand, but is not\n * used by the FreeRTOS maintainers themselves.  FreeRTOS is not\n * responsible for resulting newlib operation.  User must be familiar with\n * newlib and must provide system-wide implementations of the necessary\n * stubs. Be warned that (at the time of writing) the current newlib design\n * implements a system-wide malloc() that must be provided with locks.\n *\n * See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html\n * for additional information. */\n    #include <reent.h>\n\n    #define configUSE_C_RUNTIME_TLS_SUPPORT    1\n\n    #ifndef configTLS_BLOCK_TYPE\n        #define configTLS_BLOCK_TYPE           struct _reent\n    #endif\n\n    #ifndef configINIT_TLS_BLOCK\n        #define configINIT_TLS_BLOCK( xTLSBlock )    _REENT_INIT_PTR( &( xTLSBlock ) )\n    #endif\n\n    #ifndef configSET_TLS_BLOCK\n        #define configSET_TLS_BLOCK( xTLSBlock )    _impure_ptr = &( xTLSBlock )\n    #endif\n\n    #ifndef configDEINIT_TLS_BLOCK\n        #define configDEINIT_TLS_BLOCK( xTLSBlock )    _reclaim_reent( &( xTLSBlock ) )\n    #endif\n#endif /* if ( configUSE_NEWLIB_REENTRANT == 1 ) */\n\n#ifndef configUSE_C_RUNTIME_TLS_SUPPORT\n    #define configUSE_C_RUNTIME_TLS_SUPPORT    0\n#endif\n\n#if ( ( configUSE_NEWLIB_REENTRANT == 0 ) && ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 ) )\n\n    #ifndef configTLS_BLOCK_TYPE\n        #error Missing definition:  configTLS_BLOCK_TYPE must be defined in FreeRTOSConfig.h when configUSE_C_RUNTIME_TLS_SUPPORT is set to 1.\n    #endif\n\n    #ifndef configINIT_TLS_BLOCK\n        #error Missing definition:  configINIT_TLS_BLOCK must be defined in FreeRTOSConfig.h when configUSE_C_RUNTIME_TLS_SUPPORT is set to 1.\n    #endif\n\n    #ifndef configSET_TLS_BLOCK\n        #error Missing definition:  configSET_TLS_BLOCK must be defined in FreeRTOSConfig.h when configUSE_C_RUNTIME_TLS_SUPPORT is set to 1.\n    #endif\n\n    #ifndef configDEINIT_TLS_BLOCK\n        #error Missing definition:  configDEINIT_TLS_BLOCK must be defined in FreeRTOSConfig.h when configUSE_C_RUNTIME_TLS_SUPPORT is set to 1.\n    #endif\n#endif /* if ( ( configUSE_NEWLIB_REENTRANT == 0 ) && ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 ) ) */\n\n/*\n * Check all the required application specific macros have been defined.\n * These macros are application specific and (as downloaded) are defined\n * within FreeRTOSConfig.h.\n */\n\n#ifndef configMINIMAL_STACK_SIZE\n    #error Missing definition:  configMINIMAL_STACK_SIZE must be defined in FreeRTOSConfig.h.  configMINIMAL_STACK_SIZE defines the size (in words) of the stack allocated to the idle task.  Refer to the demo project provided for your port for a suitable value.\n#endif\n\n#ifndef configMAX_PRIORITIES\n    #error Missing definition:  configMAX_PRIORITIES must be defined in FreeRTOSConfig.h.  See the Configuration section of the FreeRTOS API documentation for details.\n#endif\n\n#if configMAX_PRIORITIES < 1\n    #error configMAX_PRIORITIES must be defined to be greater than or equal to 1.\n#endif\n\n#ifndef configUSE_PREEMPTION\n    #error Missing definition:  configUSE_PREEMPTION must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.\n#endif\n\n#ifndef configUSE_IDLE_HOOK\n    #error Missing definition:  configUSE_IDLE_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.\n#endif\n\n#ifndef configUSE_TICK_HOOK\n    #error Missing definition:  configUSE_TICK_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.\n#endif\n\n#ifndef configUSE_16_BIT_TICKS\n    #error Missing definition:  configUSE_16_BIT_TICKS must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.\n#endif\n\n#ifndef configUSE_CO_ROUTINES\n    #define configUSE_CO_ROUTINES    0\n#endif\n\n#ifndef INCLUDE_vTaskPrioritySet\n    #define INCLUDE_vTaskPrioritySet    0\n#endif\n\n#ifndef INCLUDE_uxTaskPriorityGet\n    #define INCLUDE_uxTaskPriorityGet    0\n#endif\n\n#ifndef INCLUDE_vTaskDelete\n    #define INCLUDE_vTaskDelete    0\n#endif\n\n#ifndef INCLUDE_vTaskSuspend\n    #define INCLUDE_vTaskSuspend    0\n#endif\n\n#ifdef INCLUDE_xTaskDelayUntil\n    #ifdef INCLUDE_vTaskDelayUntil\n\n/* INCLUDE_vTaskDelayUntil was replaced by INCLUDE_xTaskDelayUntil.  Backward\n * compatibility is maintained if only one or the other is defined, but\n * there is a conflict if both are defined. */\n        #error INCLUDE_vTaskDelayUntil and INCLUDE_xTaskDelayUntil are both defined.  INCLUDE_vTaskDelayUntil is no longer required and should be removed\n    #endif\n#endif\n\n#ifndef INCLUDE_xTaskDelayUntil\n    #ifdef INCLUDE_vTaskDelayUntil\n\n/* If INCLUDE_vTaskDelayUntil is set but INCLUDE_xTaskDelayUntil is not then\n * the project's FreeRTOSConfig.h probably pre-dates the introduction of\n * xTaskDelayUntil and setting INCLUDE_xTaskDelayUntil to whatever\n * INCLUDE_vTaskDelayUntil is set to will ensure backward compatibility.\n */\n        #define INCLUDE_xTaskDelayUntil    INCLUDE_vTaskDelayUntil\n    #endif\n#endif\n\n#ifndef INCLUDE_xTaskDelayUntil\n    #define INCLUDE_xTaskDelayUntil    0\n#endif\n\n#ifndef INCLUDE_vTaskDelay\n    #define INCLUDE_vTaskDelay    0\n#endif\n\n#ifndef INCLUDE_xTaskGetIdleTaskHandle\n    #define INCLUDE_xTaskGetIdleTaskHandle    0\n#endif\n\n#ifndef INCLUDE_xTaskAbortDelay\n    #define INCLUDE_xTaskAbortDelay    0\n#endif\n\n#ifndef INCLUDE_xQueueGetMutexHolder\n    #define INCLUDE_xQueueGetMutexHolder    0\n#endif\n\n#ifndef INCLUDE_xSemaphoreGetMutexHolder\n    #define INCLUDE_xSemaphoreGetMutexHolder    INCLUDE_xQueueGetMutexHolder\n#endif\n\n#ifndef INCLUDE_xTaskGetHandle\n    #define INCLUDE_xTaskGetHandle    0\n#endif\n\n#ifndef INCLUDE_uxTaskGetStackHighWaterMark\n    #define INCLUDE_uxTaskGetStackHighWaterMark    0\n#endif\n\n#ifndef INCLUDE_uxTaskGetStackHighWaterMark2\n    #define INCLUDE_uxTaskGetStackHighWaterMark2    0\n#endif\n\n#ifndef INCLUDE_eTaskGetState\n    #define INCLUDE_eTaskGetState    0\n#endif\n\n#ifndef INCLUDE_xTaskResumeFromISR\n    #define INCLUDE_xTaskResumeFromISR    1\n#endif\n\n#ifndef INCLUDE_xTimerPendFunctionCall\n    #define INCLUDE_xTimerPendFunctionCall    0\n#endif\n\n#ifndef INCLUDE_xTaskGetSchedulerState\n    #define INCLUDE_xTaskGetSchedulerState    0\n#endif\n\n#ifndef INCLUDE_xTaskGetCurrentTaskHandle\n    #define INCLUDE_xTaskGetCurrentTaskHandle    1\n#endif\n\n#if configUSE_CO_ROUTINES != 0\n    #ifndef configMAX_CO_ROUTINE_PRIORITIES\n        #error configMAX_CO_ROUTINE_PRIORITIES must be greater than or equal to 1.\n    #endif\n#endif\n\n#ifndef configUSE_DAEMON_TASK_STARTUP_HOOK\n    #define configUSE_DAEMON_TASK_STARTUP_HOOK    0\n#endif\n\n#ifndef configUSE_APPLICATION_TASK_TAG\n    #define configUSE_APPLICATION_TASK_TAG    0\n#endif\n\n#ifndef configNUM_THREAD_LOCAL_STORAGE_POINTERS\n    #define configNUM_THREAD_LOCAL_STORAGE_POINTERS    0\n#endif\n\n#ifndef configUSE_RECURSIVE_MUTEXES\n    #define configUSE_RECURSIVE_MUTEXES    0\n#endif\n\n#ifndef configUSE_MUTEXES\n    #define configUSE_MUTEXES    0\n#endif\n\n#ifndef configUSE_TIMERS\n    #define configUSE_TIMERS    0\n#endif\n\n#ifndef configUSE_COUNTING_SEMAPHORES\n    #define configUSE_COUNTING_SEMAPHORES    0\n#endif\n\n#ifndef configUSE_ALTERNATIVE_API\n    #define configUSE_ALTERNATIVE_API    0\n#endif\n\n#ifndef portCRITICAL_NESTING_IN_TCB\n    #define portCRITICAL_NESTING_IN_TCB    0\n#endif\n\n#ifndef configMAX_TASK_NAME_LEN\n    #define configMAX_TASK_NAME_LEN    16\n#endif\n\n#ifndef configIDLE_SHOULD_YIELD\n    #define configIDLE_SHOULD_YIELD    1\n#endif\n\n#if configMAX_TASK_NAME_LEN < 1\n    #error configMAX_TASK_NAME_LEN must be set to a minimum of 1 in FreeRTOSConfig.h\n#endif\n\n#ifndef configASSERT\n    #define configASSERT( x )\n    #define configASSERT_DEFINED    0\n#else\n    #define configASSERT_DEFINED    1\n#endif\n\n/* configPRECONDITION should be defined as configASSERT.\n * The CBMC proofs need a way to track assumptions and assertions.\n * A configPRECONDITION statement should express an implicit invariant or\n * assumption made.  A configASSERT statement should express an invariant that must\n * hold explicit before calling the code. */\n#ifndef configPRECONDITION\n    #define configPRECONDITION( X )    configASSERT( X )\n    #define configPRECONDITION_DEFINED    0\n#else\n    #define configPRECONDITION_DEFINED    1\n#endif\n\n#ifndef portMEMORY_BARRIER\n    #define portMEMORY_BARRIER()\n#endif\n\n#ifndef portSOFTWARE_BARRIER\n    #define portSOFTWARE_BARRIER()\n#endif\n\n/* The timers module relies on xTaskGetSchedulerState(). */\n#if configUSE_TIMERS == 1\n\n    #ifndef configTIMER_TASK_PRIORITY\n        #error If configUSE_TIMERS is set to 1 then configTIMER_TASK_PRIORITY must also be defined.\n    #endif /* configTIMER_TASK_PRIORITY */\n\n    #ifndef configTIMER_QUEUE_LENGTH\n        #error If configUSE_TIMERS is set to 1 then configTIMER_QUEUE_LENGTH must also be defined.\n    #endif /* configTIMER_QUEUE_LENGTH */\n\n    #ifndef configTIMER_TASK_STACK_DEPTH\n        #error If configUSE_TIMERS is set to 1 then configTIMER_TASK_STACK_DEPTH must also be defined.\n    #endif /* configTIMER_TASK_STACK_DEPTH */\n\n#endif /* configUSE_TIMERS */\n\n#ifndef portSET_INTERRUPT_MASK_FROM_ISR\n    #define portSET_INTERRUPT_MASK_FROM_ISR()    0\n#endif\n\n#ifndef portCLEAR_INTERRUPT_MASK_FROM_ISR\n    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue )    ( void ) ( uxSavedStatusValue )\n#endif\n\n#ifndef portCLEAN_UP_TCB\n    #define portCLEAN_UP_TCB( pxTCB )    ( void ) ( pxTCB )\n#endif\n\n#ifndef portPRE_TASK_DELETE_HOOK\n    #define portPRE_TASK_DELETE_HOOK( pvTaskToDelete, pxYieldPending )\n#endif\n\n#ifndef portSETUP_TCB\n    #define portSETUP_TCB( pxTCB )    ( void ) ( pxTCB )\n#endif\n\n#ifndef configQUEUE_REGISTRY_SIZE\n    #define configQUEUE_REGISTRY_SIZE    0U\n#endif\n\n#if ( configQUEUE_REGISTRY_SIZE < 1 )\n    #define vQueueAddToRegistry( xQueue, pcName )\n    #define vQueueUnregisterQueue( xQueue )\n    #define pcQueueGetName( xQueue )\n#endif\n\n#ifndef configUSE_MINI_LIST_ITEM\n    #define configUSE_MINI_LIST_ITEM    1\n#endif\n\n#ifndef portPOINTER_SIZE_TYPE\n    #define portPOINTER_SIZE_TYPE    uint32_t\n#endif\n\n/* Remove any unused trace macros. */\n#ifndef traceSTART\n\n/* Used to perform any necessary initialisation - for example, open a file\n * into which trace is to be written. */\n    #define traceSTART()\n#endif\n\n#ifndef traceEND\n\n/* Use to close a trace, for example close a file into which trace has been\n * written. */\n    #define traceEND()\n#endif\n\n#ifndef traceTASK_SWITCHED_IN\n\n/* Called after a task has been selected to run.  pxCurrentTCB holds a pointer\n * to the task control block of the selected task. */\n    #define traceTASK_SWITCHED_IN()\n#endif\n\n#ifndef traceINCREASE_TICK_COUNT\n\n/* Called before stepping the tick count after waking from tickless idle\n * sleep. */\n    #define traceINCREASE_TICK_COUNT( x )\n#endif\n\n#ifndef traceLOW_POWER_IDLE_BEGIN\n    /* Called immediately before entering tickless idle. */\n    #define traceLOW_POWER_IDLE_BEGIN()\n#endif\n\n#ifndef traceLOW_POWER_IDLE_END\n    /* Called when returning to the Idle task after a tickless idle. */\n    #define traceLOW_POWER_IDLE_END()\n#endif\n\n#ifndef traceTASK_SWITCHED_OUT\n\n/* Called before a task has been selected to run.  pxCurrentTCB holds a pointer\n * to the task control block of the task being switched out. */\n    #define traceTASK_SWITCHED_OUT()\n#endif\n\n#ifndef traceTASK_PRIORITY_INHERIT\n\n/* Called when a task attempts to take a mutex that is already held by a\n * lower priority task.  pxTCBOfMutexHolder is a pointer to the TCB of the task\n * that holds the mutex.  uxInheritedPriority is the priority the mutex holder\n * will inherit (the priority of the task that is attempting to obtain the\n * muted. */\n    #define traceTASK_PRIORITY_INHERIT( pxTCBOfMutexHolder, uxInheritedPriority )\n#endif\n\n#ifndef traceTASK_PRIORITY_DISINHERIT\n\n/* Called when a task releases a mutex, the holding of which had resulted in\n * the task inheriting the priority of a higher priority task.\n * pxTCBOfMutexHolder is a pointer to the TCB of the task that is releasing the\n * mutex.  uxOriginalPriority is the task's configured (base) priority. */\n    #define traceTASK_PRIORITY_DISINHERIT( pxTCBOfMutexHolder, uxOriginalPriority )\n#endif\n\n#ifndef traceBLOCKING_ON_QUEUE_RECEIVE\n\n/* Task is about to block because it cannot read from a\n * queue/mutex/semaphore.  pxQueue is a pointer to the queue/mutex/semaphore\n * upon which the read was attempted.  pxCurrentTCB points to the TCB of the\n * task that attempted the read. */\n    #define traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue )\n#endif\n\n#ifndef traceBLOCKING_ON_QUEUE_PEEK\n\n/* Task is about to block because it cannot read from a\n * queue/mutex/semaphore.  pxQueue is a pointer to the queue/mutex/semaphore\n * upon which the read was attempted.  pxCurrentTCB points to the TCB of the\n * task that attempted the read. */\n    #define traceBLOCKING_ON_QUEUE_PEEK( pxQueue )\n#endif\n\n#ifndef traceBLOCKING_ON_QUEUE_SEND\n\n/* Task is about to block because it cannot write to a\n * queue/mutex/semaphore.  pxQueue is a pointer to the queue/mutex/semaphore\n * upon which the write was attempted.  pxCurrentTCB points to the TCB of the\n * task that attempted the write. */\n    #define traceBLOCKING_ON_QUEUE_SEND( pxQueue )\n#endif\n\n#ifndef configCHECK_FOR_STACK_OVERFLOW\n    #define configCHECK_FOR_STACK_OVERFLOW    0\n#endif\n\n#ifndef configRECORD_STACK_HIGH_ADDRESS\n    #define configRECORD_STACK_HIGH_ADDRESS    0\n#endif\n\n#ifndef configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H\n    #define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H    0\n#endif\n\n/* The following event macros are embedded in the kernel API calls. */\n\n#ifndef traceMOVED_TASK_TO_READY_STATE\n    #define traceMOVED_TASK_TO_READY_STATE( pxTCB )\n#endif\n\n#ifndef tracePOST_MOVED_TASK_TO_READY_STATE\n    #define tracePOST_MOVED_TASK_TO_READY_STATE( pxTCB )\n#endif\n\n#ifndef traceQUEUE_CREATE\n    #define traceQUEUE_CREATE( pxNewQueue )\n#endif\n\n#ifndef traceQUEUE_CREATE_FAILED\n    #define traceQUEUE_CREATE_FAILED( ucQueueType )\n#endif\n\n#ifndef traceCREATE_MUTEX\n    #define traceCREATE_MUTEX( pxNewQueue )\n#endif\n\n#ifndef traceCREATE_MUTEX_FAILED\n    #define traceCREATE_MUTEX_FAILED()\n#endif\n\n#ifndef traceGIVE_MUTEX_RECURSIVE\n    #define traceGIVE_MUTEX_RECURSIVE( pxMutex )\n#endif\n\n#ifndef traceGIVE_MUTEX_RECURSIVE_FAILED\n    #define traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex )\n#endif\n\n#ifndef traceTAKE_MUTEX_RECURSIVE\n    #define traceTAKE_MUTEX_RECURSIVE( pxMutex )\n#endif\n\n#ifndef traceTAKE_MUTEX_RECURSIVE_FAILED\n    #define traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex )\n#endif\n\n#ifndef traceCREATE_COUNTING_SEMAPHORE\n    #define traceCREATE_COUNTING_SEMAPHORE()\n#endif\n\n#ifndef traceCREATE_COUNTING_SEMAPHORE_FAILED\n    #define traceCREATE_COUNTING_SEMAPHORE_FAILED()\n#endif\n\n#ifndef traceQUEUE_SET_SEND\n    #define traceQUEUE_SET_SEND    traceQUEUE_SEND\n#endif\n\n#ifndef traceQUEUE_SEND\n    #define traceQUEUE_SEND( pxQueue )\n#endif\n\n#ifndef traceQUEUE_SEND_FAILED\n    #define traceQUEUE_SEND_FAILED( pxQueue )\n#endif\n\n#ifndef traceQUEUE_RECEIVE\n    #define traceQUEUE_RECEIVE( pxQueue )\n#endif\n\n#ifndef traceQUEUE_PEEK\n    #define traceQUEUE_PEEK( pxQueue )\n#endif\n\n#ifndef traceQUEUE_PEEK_FAILED\n    #define traceQUEUE_PEEK_FAILED( pxQueue )\n#endif\n\n#ifndef traceQUEUE_PEEK_FROM_ISR\n    #define traceQUEUE_PEEK_FROM_ISR( pxQueue )\n#endif\n\n#ifndef traceQUEUE_RECEIVE_FAILED\n    #define traceQUEUE_RECEIVE_FAILED( pxQueue )\n#endif\n\n#ifndef traceQUEUE_SEND_FROM_ISR\n    #define traceQUEUE_SEND_FROM_ISR( pxQueue )\n#endif\n\n#ifndef traceQUEUE_SEND_FROM_ISR_FAILED\n    #define traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue )\n#endif\n\n#ifndef traceQUEUE_RECEIVE_FROM_ISR\n    #define traceQUEUE_RECEIVE_FROM_ISR( pxQueue )\n#endif\n\n#ifndef traceQUEUE_RECEIVE_FROM_ISR_FAILED\n    #define traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue )\n#endif\n\n#ifndef traceQUEUE_PEEK_FROM_ISR_FAILED\n    #define traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue )\n#endif\n\n#ifndef traceQUEUE_DELETE\n    #define traceQUEUE_DELETE( pxQueue )\n#endif\n\n#ifndef traceTASK_CREATE\n    #define traceTASK_CREATE( pxNewTCB )\n#endif\n\n#ifndef traceTASK_CREATE_FAILED\n    #define traceTASK_CREATE_FAILED()\n#endif\n\n#ifndef traceTASK_DELETE\n    #define traceTASK_DELETE( pxTaskToDelete )\n#endif\n\n#ifndef traceTASK_DELAY_UNTIL\n    #define traceTASK_DELAY_UNTIL( x )\n#endif\n\n#ifndef traceTASK_DELAY\n    #define traceTASK_DELAY()\n#endif\n\n#ifndef traceTASK_PRIORITY_SET\n    #define traceTASK_PRIORITY_SET( pxTask, uxNewPriority )\n#endif\n\n#ifndef traceTASK_SUSPEND\n    #define traceTASK_SUSPEND( pxTaskToSuspend )\n#endif\n\n#ifndef traceTASK_RESUME\n    #define traceTASK_RESUME( pxTaskToResume )\n#endif\n\n#ifndef traceTASK_RESUME_FROM_ISR\n    #define traceTASK_RESUME_FROM_ISR( pxTaskToResume )\n#endif\n\n#ifndef traceTASK_INCREMENT_TICK\n    #define traceTASK_INCREMENT_TICK( xTickCount )\n#endif\n\n#ifndef traceTIMER_CREATE\n    #define traceTIMER_CREATE( pxNewTimer )\n#endif\n\n#ifndef traceTIMER_CREATE_FAILED\n    #define traceTIMER_CREATE_FAILED()\n#endif\n\n#ifndef traceTIMER_COMMAND_SEND\n    #define traceTIMER_COMMAND_SEND( xTimer, xMessageID, xMessageValueValue, xReturn )\n#endif\n\n#ifndef traceTIMER_EXPIRED\n    #define traceTIMER_EXPIRED( pxTimer )\n#endif\n\n#ifndef traceTIMER_COMMAND_RECEIVED\n    #define traceTIMER_COMMAND_RECEIVED( pxTimer, xMessageID, xMessageValue )\n#endif\n\n#ifndef traceMALLOC\n    #define traceMALLOC( pvAddress, uiSize )\n#endif\n\n#ifndef traceFREE\n    #define traceFREE( pvAddress, uiSize )\n#endif\n\n#ifndef traceEVENT_GROUP_CREATE\n    #define traceEVENT_GROUP_CREATE( xEventGroup )\n#endif\n\n#ifndef traceEVENT_GROUP_CREATE_FAILED\n    #define traceEVENT_GROUP_CREATE_FAILED()\n#endif\n\n#ifndef traceEVENT_GROUP_SYNC_BLOCK\n    #define traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor )\n#endif\n\n#ifndef traceEVENT_GROUP_SYNC_END\n    #define traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred )    ( void ) ( xTimeoutOccurred )\n#endif\n\n#ifndef traceEVENT_GROUP_WAIT_BITS_BLOCK\n    #define traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor )\n#endif\n\n#ifndef traceEVENT_GROUP_WAIT_BITS_END\n    #define traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred )    ( void ) ( xTimeoutOccurred )\n#endif\n\n#ifndef traceEVENT_GROUP_CLEAR_BITS\n    #define traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear )\n#endif\n\n#ifndef traceEVENT_GROUP_CLEAR_BITS_FROM_ISR\n    #define traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear )\n#endif\n\n#ifndef traceEVENT_GROUP_SET_BITS\n    #define traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet )\n#endif\n\n#ifndef traceEVENT_GROUP_SET_BITS_FROM_ISR\n    #define traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet )\n#endif\n\n#ifndef traceEVENT_GROUP_DELETE\n    #define traceEVENT_GROUP_DELETE( xEventGroup )\n#endif\n\n#ifndef tracePEND_FUNC_CALL\n    #define tracePEND_FUNC_CALL( xFunctionToPend, pvParameter1, ulParameter2, ret )\n#endif\n\n#ifndef tracePEND_FUNC_CALL_FROM_ISR\n    #define tracePEND_FUNC_CALL_FROM_ISR( xFunctionToPend, pvParameter1, ulParameter2, ret )\n#endif\n\n#ifndef traceQUEUE_REGISTRY_ADD\n    #define traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName )\n#endif\n\n#ifndef traceTASK_NOTIFY_TAKE_BLOCK\n    #define traceTASK_NOTIFY_TAKE_BLOCK( uxIndexToWait )\n#endif\n\n#ifndef traceTASK_NOTIFY_TAKE\n    #define traceTASK_NOTIFY_TAKE( uxIndexToWait )\n#endif\n\n#ifndef traceTASK_NOTIFY_WAIT_BLOCK\n    #define traceTASK_NOTIFY_WAIT_BLOCK( uxIndexToWait )\n#endif\n\n#ifndef traceTASK_NOTIFY_WAIT\n    #define traceTASK_NOTIFY_WAIT( uxIndexToWait )\n#endif\n\n#ifndef traceTASK_NOTIFY\n    #define traceTASK_NOTIFY( uxIndexToNotify )\n#endif\n\n#ifndef traceTASK_NOTIFY_FROM_ISR\n    #define traceTASK_NOTIFY_FROM_ISR( uxIndexToNotify )\n#endif\n\n#ifndef traceTASK_NOTIFY_GIVE_FROM_ISR\n    #define traceTASK_NOTIFY_GIVE_FROM_ISR( uxIndexToNotify )\n#endif\n\n#ifndef traceSTREAM_BUFFER_CREATE_FAILED\n    #define traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer )\n#endif\n\n#ifndef traceSTREAM_BUFFER_CREATE_STATIC_FAILED\n    #define traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer )\n#endif\n\n#ifndef traceSTREAM_BUFFER_CREATE\n    #define traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xIsMessageBuffer )\n#endif\n\n#ifndef traceSTREAM_BUFFER_DELETE\n    #define traceSTREAM_BUFFER_DELETE( xStreamBuffer )\n#endif\n\n#ifndef traceSTREAM_BUFFER_RESET\n    #define traceSTREAM_BUFFER_RESET( xStreamBuffer )\n#endif\n\n#ifndef traceBLOCKING_ON_STREAM_BUFFER_SEND\n    #define traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer )\n#endif\n\n#ifndef traceSTREAM_BUFFER_SEND\n    #define traceSTREAM_BUFFER_SEND( xStreamBuffer, xBytesSent )\n#endif\n\n#ifndef traceSTREAM_BUFFER_SEND_FAILED\n    #define traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer )\n#endif\n\n#ifndef traceSTREAM_BUFFER_SEND_FROM_ISR\n    #define traceSTREAM_BUFFER_SEND_FROM_ISR( xStreamBuffer, xBytesSent )\n#endif\n\n#ifndef traceBLOCKING_ON_STREAM_BUFFER_RECEIVE\n    #define traceBLOCKING_ON_STREAM_BUFFER_RECEIVE( xStreamBuffer )\n#endif\n\n#ifndef traceSTREAM_BUFFER_RECEIVE\n    #define traceSTREAM_BUFFER_RECEIVE( xStreamBuffer, xReceivedLength )\n#endif\n\n#ifndef traceSTREAM_BUFFER_RECEIVE_FAILED\n    #define traceSTREAM_BUFFER_RECEIVE_FAILED( xStreamBuffer )\n#endif\n\n#ifndef traceSTREAM_BUFFER_RECEIVE_FROM_ISR\n    #define traceSTREAM_BUFFER_RECEIVE_FROM_ISR( xStreamBuffer, xReceivedLength )\n#endif\n\n#ifndef configGENERATE_RUN_TIME_STATS\n    #define configGENERATE_RUN_TIME_STATS    0\n#endif\n\n#if ( configGENERATE_RUN_TIME_STATS == 1 )\n\n    #ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS\n        #error If configGENERATE_RUN_TIME_STATS is defined then portCONFIGURE_TIMER_FOR_RUN_TIME_STATS must also be defined.  portCONFIGURE_TIMER_FOR_RUN_TIME_STATS should call a port layer function to setup a peripheral timer/counter that can then be used as the run time counter time base.\n    #endif /* portCONFIGURE_TIMER_FOR_RUN_TIME_STATS */\n\n    #ifndef portGET_RUN_TIME_COUNTER_VALUE\n        #ifndef portALT_GET_RUN_TIME_COUNTER_VALUE\n            #error If configGENERATE_RUN_TIME_STATS is defined then either portGET_RUN_TIME_COUNTER_VALUE or portALT_GET_RUN_TIME_COUNTER_VALUE must also be defined.  See the examples provided and the FreeRTOS web site for more information.\n        #endif /* portALT_GET_RUN_TIME_COUNTER_VALUE */\n    #endif /* portGET_RUN_TIME_COUNTER_VALUE */\n\n#endif /* configGENERATE_RUN_TIME_STATS */\n\n#ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS\n    #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS()\n#endif\n\n#ifndef configUSE_MALLOC_FAILED_HOOK\n    #define configUSE_MALLOC_FAILED_HOOK    0\n#endif\n\n#ifndef portPRIVILEGE_BIT\n    #define portPRIVILEGE_BIT    ( ( UBaseType_t ) 0x00 )\n#endif\n\n#ifndef portYIELD_WITHIN_API\n    #define portYIELD_WITHIN_API    portYIELD\n#endif\n\n#ifndef portSUPPRESS_TICKS_AND_SLEEP\n    #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )\n#endif\n\n#ifndef configEXPECTED_IDLE_TIME_BEFORE_SLEEP\n    #define configEXPECTED_IDLE_TIME_BEFORE_SLEEP    2\n#endif\n\n#if configEXPECTED_IDLE_TIME_BEFORE_SLEEP < 2\n    #error configEXPECTED_IDLE_TIME_BEFORE_SLEEP must not be less than 2\n#endif\n\n#ifndef configUSE_TICKLESS_IDLE\n    #define configUSE_TICKLESS_IDLE    0\n#endif\n\n#ifndef configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING\n    #define configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( x )\n#endif\n\n#ifndef configPRE_SLEEP_PROCESSING\n    #define configPRE_SLEEP_PROCESSING( x )\n#endif\n\n#ifndef configPOST_SLEEP_PROCESSING\n    #define configPOST_SLEEP_PROCESSING( x )\n#endif\n\n#ifndef configUSE_QUEUE_SETS\n    #define configUSE_QUEUE_SETS    0\n#endif\n\n#ifndef portTASK_USES_FLOATING_POINT\n    #define portTASK_USES_FLOATING_POINT()\n#endif\n\n#ifndef portALLOCATE_SECURE_CONTEXT\n    #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )\n#endif\n\n#ifndef portDONT_DISCARD\n    #define portDONT_DISCARD\n#endif\n\n#ifndef configUSE_TIME_SLICING\n    #define configUSE_TIME_SLICING    1\n#endif\n\n#ifndef configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS\n    #define configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS    0\n#endif\n\n#ifndef configUSE_STATS_FORMATTING_FUNCTIONS\n    #define configUSE_STATS_FORMATTING_FUNCTIONS    0\n#endif\n\n#ifndef portASSERT_IF_INTERRUPT_PRIORITY_INVALID\n    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()\n#endif\n\n#ifndef configUSE_TRACE_FACILITY\n    #define configUSE_TRACE_FACILITY    0\n#endif\n\n#ifndef mtCOVERAGE_TEST_MARKER\n    #define mtCOVERAGE_TEST_MARKER()\n#endif\n\n#ifndef mtCOVERAGE_TEST_DELAY\n    #define mtCOVERAGE_TEST_DELAY()\n#endif\n\n#ifndef portASSERT_IF_IN_ISR\n    #define portASSERT_IF_IN_ISR()\n#endif\n\n#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION\n    #define configUSE_PORT_OPTIMISED_TASK_SELECTION    0\n#endif\n\n#ifndef configAPPLICATION_ALLOCATED_HEAP\n    #define configAPPLICATION_ALLOCATED_HEAP    0\n#endif\n\n#ifndef configUSE_TASK_NOTIFICATIONS\n    #define configUSE_TASK_NOTIFICATIONS    1\n#endif\n\n#ifndef configTASK_NOTIFICATION_ARRAY_ENTRIES\n    #define configTASK_NOTIFICATION_ARRAY_ENTRIES    1\n#endif\n\n#if configTASK_NOTIFICATION_ARRAY_ENTRIES < 1\n    #error configTASK_NOTIFICATION_ARRAY_ENTRIES must be at least 1\n#endif\n\n#ifndef configUSE_POSIX_ERRNO\n    #define configUSE_POSIX_ERRNO    0\n#endif\n\n#ifndef configUSE_SB_COMPLETED_CALLBACK\n\n/* By default per-instance callbacks are not enabled for stream buffer or message buffer. */\n    #define configUSE_SB_COMPLETED_CALLBACK    0\n#endif\n\n#ifndef portTICK_TYPE_IS_ATOMIC\n    #define portTICK_TYPE_IS_ATOMIC    0\n#endif\n\n#ifndef configSUPPORT_STATIC_ALLOCATION\n    /* Defaults to 0 for backward compatibility. */\n    #define configSUPPORT_STATIC_ALLOCATION    0\n#endif\n\n#ifndef configSUPPORT_DYNAMIC_ALLOCATION\n    /* Defaults to 1 for backward compatibility. */\n    #define configSUPPORT_DYNAMIC_ALLOCATION    1\n#endif\n\n#if ( ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION != 1 ) )\n    #error configUSE_STATS_FORMATTING_FUNCTIONS cannot be used without dynamic allocation, but configSUPPORT_DYNAMIC_ALLOCATION is not set to 1.\n#endif\n\n#if ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 )\n    #if ( ( configUSE_TRACE_FACILITY != 1 ) && ( configGENERATE_RUN_TIME_STATS != 1 ) )\n        #error configUSE_STATS_FORMATTING_FUNCTIONS is 1 but the functions it enables are not used because neither configUSE_TRACE_FACILITY or configGENERATE_RUN_TIME_STATS are 1.  Set configUSE_STATS_FORMATTING_FUNCTIONS to 0 in FreeRTOSConfig.h.\n    #endif\n#endif\n\n#ifndef configSTACK_DEPTH_TYPE\n\n/* Defaults to uint16_t for backward compatibility, but can be overridden\n * in FreeRTOSConfig.h if uint16_t is too restrictive. */\n    #define configSTACK_DEPTH_TYPE    uint16_t\n#endif\n\n#ifndef configRUN_TIME_COUNTER_TYPE\n\n/* Defaults to uint32_t for backward compatibility, but can be overridden in\n * FreeRTOSConfig.h if uint32_t is too restrictive. */\n\n    #define configRUN_TIME_COUNTER_TYPE    uint32_t\n#endif\n\n#ifndef configMESSAGE_BUFFER_LENGTH_TYPE\n\n/* Defaults to size_t for backward compatibility, but can be overridden\n * in FreeRTOSConfig.h if lengths will always be less than the number of bytes\n * in a size_t. */\n    #define configMESSAGE_BUFFER_LENGTH_TYPE    size_t\n#endif\n\n/* Sanity check the configuration. */\n#if ( ( configSUPPORT_STATIC_ALLOCATION == 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) )\n    #error configSUPPORT_STATIC_ALLOCATION and configSUPPORT_DYNAMIC_ALLOCATION cannot both be 0, but can both be 1.\n#endif\n\n#if ( ( configUSE_RECURSIVE_MUTEXES == 1 ) && ( configUSE_MUTEXES != 1 ) )\n    #error configUSE_MUTEXES must be set to 1 to use recursive mutexes\n#endif\n\n#ifndef configINITIAL_TICK_COUNT\n    #define configINITIAL_TICK_COUNT    0\n#endif\n\n#if ( portTICK_TYPE_IS_ATOMIC == 0 )\n\n/* Either variables of tick type cannot be read atomically, or\n * portTICK_TYPE_IS_ATOMIC was not set - map the critical sections used when\n * the tick count is returned to the standard critical section macros. */\n    #define portTICK_TYPE_ENTER_CRITICAL()                      portENTER_CRITICAL()\n    #define portTICK_TYPE_EXIT_CRITICAL()                       portEXIT_CRITICAL()\n    #define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR()         portSET_INTERRUPT_MASK_FROM_ISR()\n    #define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x )    portCLEAR_INTERRUPT_MASK_FROM_ISR( ( x ) )\n#else\n\n/* The tick type can be read atomically, so critical sections used when the\n * tick count is returned can be defined away. */\n    #define portTICK_TYPE_ENTER_CRITICAL()\n    #define portTICK_TYPE_EXIT_CRITICAL()\n    #define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR()         0\n    #define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x )    ( void ) ( x )\n#endif /* if ( portTICK_TYPE_IS_ATOMIC == 0 ) */\n\n/* Definitions to allow backward compatibility with FreeRTOS versions prior to\n * V8 if desired. */\n#ifndef configENABLE_BACKWARD_COMPATIBILITY\n    #define configENABLE_BACKWARD_COMPATIBILITY    1\n#endif\n\n#ifndef configPRINTF\n\n/* configPRINTF() was not defined, so define it away to nothing.  To use\n * configPRINTF() then define it as follows (where MyPrintFunction() is\n * provided by the application writer):\n *\n * void MyPrintFunction(const char *pcFormat, ... );\n #define configPRINTF( X )   MyPrintFunction X\n *\n * Then call like a standard printf() function, but placing brackets around\n * all parameters so they are passed as a single parameter.  For example:\n * configPRINTF( (\"Value = %d\", MyVariable) ); */\n    #define configPRINTF( X )\n#endif\n\n#ifndef configMAX\n\n/* The application writer has not provided their own MAX macro, so define\n * the following generic implementation. */\n    #define configMAX( a, b )    ( ( ( a ) > ( b ) ) ? ( a ) : ( b ) )\n#endif\n\n#ifndef configMIN\n\n/* The application writer has not provided their own MIN macro, so define\n * the following generic implementation. */\n    #define configMIN( a, b )    ( ( ( a ) < ( b ) ) ? ( a ) : ( b ) )\n#endif\n\n#if configENABLE_BACKWARD_COMPATIBILITY == 1\n    #define eTaskStateGet                 eTaskGetState\n    #define portTickType                  TickType_t\n    #define xTaskHandle                   TaskHandle_t\n    #define xQueueHandle                  QueueHandle_t\n    #define xSemaphoreHandle              SemaphoreHandle_t\n    #define xQueueSetHandle               QueueSetHandle_t\n    #define xQueueSetMemberHandle         QueueSetMemberHandle_t\n    #define xTimeOutType                  TimeOut_t\n    #define xMemoryRegion                 MemoryRegion_t\n    #define xTaskParameters               TaskParameters_t\n    #define xTaskStatusType               TaskStatus_t\n    #define xTimerHandle                  TimerHandle_t\n    #define xCoRoutineHandle              CoRoutineHandle_t\n    #define pdTASK_HOOK_CODE              TaskHookFunction_t\n    #define portTICK_RATE_MS              portTICK_PERIOD_MS\n    #define pcTaskGetTaskName             pcTaskGetName\n    #define pcTimerGetTimerName           pcTimerGetName\n    #define pcQueueGetQueueName           pcQueueGetName\n    #define vTaskGetTaskInfo              vTaskGetInfo\n    #define xTaskGetIdleRunTimeCounter    ulTaskGetIdleRunTimeCounter\n\n/* Backward compatibility within the scheduler code only - these definitions\n * are not really required but are included for completeness. */\n    #define tmrTIMER_CALLBACK             TimerCallbackFunction_t\n    #define pdTASK_CODE                   TaskFunction_t\n    #define xListItem                     ListItem_t\n    #define xList                         List_t\n\n/* For libraries that break the list data hiding, and access list structure\n * members directly (which is not supposed to be done). */\n    #define pxContainer                   pvContainer\n#endif /* configENABLE_BACKWARD_COMPATIBILITY */\n\n#if ( configUSE_ALTERNATIVE_API != 0 )\n    #error The alternative API was deprecated some time ago, and was removed in FreeRTOS V9.0 0\n#endif\n\n/* Set configUSE_TASK_FPU_SUPPORT to 0 to omit floating point support even\n * if floating point hardware is otherwise supported by the FreeRTOS port in use.\n * This constant is not supported by all FreeRTOS ports that include floating\n * point support. */\n#ifndef configUSE_TASK_FPU_SUPPORT\n    #define configUSE_TASK_FPU_SUPPORT    1\n#endif\n\n/* Set configENABLE_MPU to 1 to enable MPU support and 0 to disable it. This is\n * currently used in ARMv8M ports. */\n#ifndef configENABLE_MPU\n    #define configENABLE_MPU    0\n#endif\n\n/* Set configENABLE_FPU to 1 to enable FPU support and 0 to disable it. This is\n * currently used in ARMv8M ports. */\n#ifndef configENABLE_FPU\n    #define configENABLE_FPU    1\n#endif\n\n/* Set configENABLE_MVE to 1 to enable MVE support and 0 to disable it. This is\n * currently used in ARMv8M ports. */\n#ifndef configENABLE_MVE\n    #define configENABLE_MVE    0\n#endif\n\n/* Set configENABLE_TRUSTZONE to 1 enable TrustZone support and 0 to disable it.\n * This is currently used in ARMv8M ports. */\n#ifndef configENABLE_TRUSTZONE\n    #define configENABLE_TRUSTZONE    1\n#endif\n\n/* Set configRUN_FREERTOS_SECURE_ONLY to 1 to run the FreeRTOS ARMv8M port on\n * the Secure Side only. */\n#ifndef configRUN_FREERTOS_SECURE_ONLY\n    #define configRUN_FREERTOS_SECURE_ONLY    0\n#endif\n\n#ifndef configRUN_ADDITIONAL_TESTS\n    #define configRUN_ADDITIONAL_TESTS    0\n#endif\n\n\n/* Sometimes the FreeRTOSConfig.h settings only allow a task to be created using\n * dynamically allocated RAM, in which case when any task is deleted it is known\n * that both the task's stack and TCB need to be freed.  Sometimes the\n * FreeRTOSConfig.h settings only allow a task to be created using statically\n * allocated RAM, in which case when any task is deleted it is known that neither\n * the task's stack or TCB should be freed.  Sometimes the FreeRTOSConfig.h\n * settings allow a task to be created using either statically or dynamically\n * allocated RAM, in which case a member of the TCB is used to record whether the\n * stack and/or TCB were allocated statically or dynamically, so when a task is\n * deleted the RAM that was allocated dynamically is freed again and no attempt is\n * made to free the RAM that was allocated statically.\n * tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE is only true if it is possible for a\n * task to be created using either statically or dynamically allocated RAM.  Note\n * that if portUSING_MPU_WRAPPERS is 1 then a protected task can be created with\n * a statically allocated stack and a dynamically allocated TCB.\n *\n * The following table lists various combinations of portUSING_MPU_WRAPPERS,\n * configSUPPORT_DYNAMIC_ALLOCATION and configSUPPORT_STATIC_ALLOCATION and\n * when it is possible to have both static and dynamic allocation:\n *  +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+\n * | MPU | Dynamic | Static |     Available Functions     |       Possible Allocations        | Both Dynamic and | Need Free |\n * |     |         |        |                             |                                   | Static Possible  |           |\n * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+\n * | 0   | 0       | 1      | xTaskCreateStatic           | TCB - Static, Stack - Static      | No               | No        |\n * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|\n * | 0   | 1       | 0      | xTaskCreate                 | TCB - Dynamic, Stack - Dynamic    | No               | Yes       |\n * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|\n * | 0   | 1       | 1      | xTaskCreate,                | 1. TCB - Dynamic, Stack - Dynamic | Yes              | Yes       |\n * |     |         |        | xTaskCreateStatic           | 2. TCB - Static, Stack - Static   |                  |           |\n * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|\n * | 1   | 0       | 1      | xTaskCreateStatic,          | TCB - Static, Stack - Static      | No               | No        |\n * |     |         |        | xTaskCreateRestrictedStatic |                                   |                  |           |\n * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|\n * | 1   | 1       | 0      | xTaskCreate,                | 1. TCB - Dynamic, Stack - Dynamic | Yes              | Yes       |\n * |     |         |        | xTaskCreateRestricted       | 2. TCB - Dynamic, Stack - Static  |                  |           |\n * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|\n * | 1   | 1       | 1      | xTaskCreate,                | 1. TCB - Dynamic, Stack - Dynamic | Yes              | Yes       |\n * |     |         |        | xTaskCreateStatic,          | 2. TCB - Dynamic, Stack - Static  |                  |           |\n * |     |         |        | xTaskCreateRestricted,      | 3. TCB - Static, Stack - Static   |                  |           |\n * |     |         |        | xTaskCreateRestrictedStatic |                                   |                  |           |\n * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+\n */\n#define tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE                                                                                     \\\n    ( ( ( portUSING_MPU_WRAPPERS == 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) || \\\n      ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) )\n\n/*\n * In line with software engineering best practice, FreeRTOS implements a strict\n * data hiding policy, so the real structures used by FreeRTOS to maintain the\n * state of tasks, queues, semaphores, etc. are not accessible to the application\n * code.  However, if the application writer wants to statically allocate such\n * an object then the size of the object needs to be known.  Dummy structures\n * that are guaranteed to have the same size and alignment requirements of the\n * real objects are used for this purpose.  The dummy list and list item\n * structures below are used for inclusion in such a dummy structure.\n */\nstruct xSTATIC_LIST_ITEM\n{\n    #if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )\n        TickType_t xDummy1;\n    #endif\n    TickType_t xDummy2;\n    void * pvDummy3[ 4 ];\n    #if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )\n        TickType_t xDummy4;\n    #endif\n};\ntypedef struct xSTATIC_LIST_ITEM StaticListItem_t;\n\n#if ( configUSE_MINI_LIST_ITEM == 1 )\n    /* See the comments above the struct xSTATIC_LIST_ITEM definition. */\n    struct xSTATIC_MINI_LIST_ITEM\n    {\n        #if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )\n            TickType_t xDummy1;\n        #endif\n        TickType_t xDummy2;\n        void * pvDummy3[ 2 ];\n    };\n    typedef struct xSTATIC_MINI_LIST_ITEM StaticMiniListItem_t;\n#else /* if ( configUSE_MINI_LIST_ITEM == 1 ) */\n    typedef struct xSTATIC_LIST_ITEM      StaticMiniListItem_t;\n#endif /* if ( configUSE_MINI_LIST_ITEM == 1 ) */\n\n/* See the comments above the struct xSTATIC_LIST_ITEM definition. */\ntypedef struct xSTATIC_LIST\n{\n    #if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )\n        TickType_t xDummy1;\n    #endif\n    UBaseType_t uxDummy2;\n    void * pvDummy3;\n    StaticMiniListItem_t xDummy4;\n    #if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )\n        TickType_t xDummy5;\n    #endif\n} StaticList_t;\n\n/*\n * In line with software engineering best practice, especially when supplying a\n * library that is likely to change in future versions, FreeRTOS implements a\n * strict data hiding policy.  This means the Task structure used internally by\n * FreeRTOS is not accessible to application code.  However, if the application\n * writer wants to statically allocate the memory required to create a task then\n * the size of the task object needs to be known.  The StaticTask_t structure\n * below is provided for this purpose.  Its sizes and alignment requirements are\n * guaranteed to match those of the genuine structure, no matter which\n * architecture is being used, and no matter how the values in FreeRTOSConfig.h\n * are set.  Its contents are somewhat obfuscated in the hope users will\n * recognise that it would be unwise to make direct use of the structure members.\n */\ntypedef struct xSTATIC_TCB\n{\n    void * pxDummy1;\n    #if ( portUSING_MPU_WRAPPERS == 1 )\n        xMPU_SETTINGS xDummy2;\n    #endif\n    StaticListItem_t xDummy3[ 2 ];\n    UBaseType_t uxDummy5;\n    void * pxDummy6;\n    uint8_t ucDummy7[ configMAX_TASK_NAME_LEN ];\n    #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) )\n        void * pxDummy8;\n    #endif\n    #if ( portCRITICAL_NESTING_IN_TCB == 1 )\n        UBaseType_t uxDummy9;\n    #endif\n    #if ( configUSE_TRACE_FACILITY == 1 )\n        UBaseType_t uxDummy10[ 2 ];\n    #endif\n    #if ( configUSE_MUTEXES == 1 )\n        UBaseType_t uxDummy12[ 2 ];\n    #endif\n    #if ( configUSE_APPLICATION_TASK_TAG == 1 )\n        void * pxDummy14;\n    #endif\n    #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )\n        void * pvDummy15[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ];\n    #endif\n    #if ( configGENERATE_RUN_TIME_STATS == 1 )\n        configRUN_TIME_COUNTER_TYPE ulDummy16;\n    #endif\n    #if ( ( configUSE_NEWLIB_REENTRANT == 1 ) || ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 ) )\n        configTLS_BLOCK_TYPE xDummy17;\n    #endif\n    #if ( configUSE_TASK_NOTIFICATIONS == 1 )\n        uint32_t ulDummy18[ configTASK_NOTIFICATION_ARRAY_ENTRIES ];\n        uint8_t ucDummy19[ configTASK_NOTIFICATION_ARRAY_ENTRIES ];\n    #endif\n    #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )\n        uint8_t uxDummy20;\n    #endif\n\n    #if ( INCLUDE_xTaskAbortDelay == 1 )\n        uint8_t ucDummy21;\n    #endif\n    #if ( configUSE_POSIX_ERRNO == 1 )\n        int iDummy22;\n    #endif\n} StaticTask_t;\n\n/*\n * In line with software engineering best practice, especially when supplying a\n * library that is likely to change in future versions, FreeRTOS implements a\n * strict data hiding policy.  This means the Queue structure used internally by\n * FreeRTOS is not accessible to application code.  However, if the application\n * writer wants to statically allocate the memory required to create a queue\n * then the size of the queue object needs to be known.  The StaticQueue_t\n * structure below is provided for this purpose.  Its sizes and alignment\n * requirements are guaranteed to match those of the genuine structure, no\n * matter which architecture is being used, and no matter how the values in\n * FreeRTOSConfig.h are set.  Its contents are somewhat obfuscated in the hope\n * users will recognise that it would be unwise to make direct use of the\n * structure members.\n */\ntypedef struct xSTATIC_QUEUE\n{\n    void * pvDummy1[ 3 ];\n\n    union\n    {\n        void * pvDummy2;\n        UBaseType_t uxDummy2;\n    } u;\n\n    StaticList_t xDummy3[ 2 ];\n    UBaseType_t uxDummy4[ 3 ];\n    uint8_t ucDummy5[ 2 ];\n\n    #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )\n        uint8_t ucDummy6;\n    #endif\n\n    #if ( configUSE_QUEUE_SETS == 1 )\n        void * pvDummy7;\n    #endif\n\n    #if ( configUSE_TRACE_FACILITY == 1 )\n        UBaseType_t uxDummy8;\n        uint8_t ucDummy9;\n    #endif\n} StaticQueue_t;\ntypedef StaticQueue_t StaticSemaphore_t;\n\n/*\n * In line with software engineering best practice, especially when supplying a\n * library that is likely to change in future versions, FreeRTOS implements a\n * strict data hiding policy.  This means the event group structure used\n * internally by FreeRTOS is not accessible to application code.  However, if\n * the application writer wants to statically allocate the memory required to\n * create an event group then the size of the event group object needs to be\n * know.  The StaticEventGroup_t structure below is provided for this purpose.\n * Its sizes and alignment requirements are guaranteed to match those of the\n * genuine structure, no matter which architecture is being used, and no matter\n * how the values in FreeRTOSConfig.h are set.  Its contents are somewhat\n * obfuscated in the hope users will recognise that it would be unwise to make\n * direct use of the structure members.\n */\ntypedef struct xSTATIC_EVENT_GROUP\n{\n    TickType_t xDummy1;\n    StaticList_t xDummy2;\n\n    #if ( configUSE_TRACE_FACILITY == 1 )\n        UBaseType_t uxDummy3;\n    #endif\n\n    #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )\n        uint8_t ucDummy4;\n    #endif\n} StaticEventGroup_t;\n\n/*\n * In line with software engineering best practice, especially when supplying a\n * library that is likely to change in future versions, FreeRTOS implements a\n * strict data hiding policy.  This means the software timer structure used\n * internally by FreeRTOS is not accessible to application code.  However, if\n * the application writer wants to statically allocate the memory required to\n * create a software timer then the size of the queue object needs to be known.\n * The StaticTimer_t structure below is provided for this purpose.  Its sizes\n * and alignment requirements are guaranteed to match those of the genuine\n * structure, no matter which architecture is being used, and no matter how the\n * values in FreeRTOSConfig.h are set.  Its contents are somewhat obfuscated in\n * the hope users will recognise that it would be unwise to make direct use of\n * the structure members.\n */\ntypedef struct xSTATIC_TIMER\n{\n    void * pvDummy1;\n    StaticListItem_t xDummy2;\n    TickType_t xDummy3;\n    void * pvDummy5;\n    TaskFunction_t pvDummy6;\n    #if ( configUSE_TRACE_FACILITY == 1 )\n        UBaseType_t uxDummy7;\n    #endif\n    uint8_t ucDummy8;\n} StaticTimer_t;\n\n/*\n * In line with software engineering best practice, especially when supplying a\n * library that is likely to change in future versions, FreeRTOS implements a\n * strict data hiding policy.  This means the stream buffer structure used\n * internally by FreeRTOS is not accessible to application code.  However, if\n * the application writer wants to statically allocate the memory required to\n * create a stream buffer then the size of the stream buffer object needs to be\n * known.  The StaticStreamBuffer_t structure below is provided for this\n * purpose.  Its size and alignment requirements are guaranteed to match those\n * of the genuine structure, no matter which architecture is being used, and\n * no matter how the values in FreeRTOSConfig.h are set.  Its contents are\n * somewhat obfuscated in the hope users will recognise that it would be unwise\n * to make direct use of the structure members.\n */\ntypedef struct xSTATIC_STREAM_BUFFER\n{\n    size_t uxDummy1[ 4 ];\n    void * pvDummy2[ 3 ];\n    uint8_t ucDummy3;\n    #if ( configUSE_TRACE_FACILITY == 1 )\n        UBaseType_t uxDummy4;\n    #endif\n    #if ( configUSE_SB_COMPLETED_CALLBACK == 1 )\n        void * pvDummy5[ 2 ];\n    #endif\n} StaticStreamBuffer_t;\n\n/* Message buffers are built on stream buffers. */\ntypedef StaticStreamBuffer_t StaticMessageBuffer_t;\n\n/* *INDENT-OFF* */\n#ifdef __cplusplus\n    }\n#endif\n/* *INDENT-ON* */\n\n#endif /* INC_FREERTOS_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/include/StackMacros.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n\n#ifndef _MSC_VER /* Visual Studio doesn't support #warning. */\n    #warning The name of this file has changed to stack_macros.h.  Please update your code accordingly.  This source file (which has the original name) will be removed in a future release.\n#endif\n\n#include \"stack_macros.h\"\n"
  },
  {
    "path": "FreeRTOS-comparison/include/atomic.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/**\n * @file atomic.h\n * @brief FreeRTOS atomic operation support.\n *\n * This file implements atomic functions by disabling interrupts globally.\n * Implementations with architecture specific atomic instructions can be\n * provided under each compiler directory.\n */\n\n#ifndef ATOMIC_H\n#define ATOMIC_H\n\n#ifndef INC_FREERTOS_H\n    #error \"include FreeRTOS.h must appear in source files before include atomic.h\"\n#endif\n\n/* Standard includes. */\n#include <stdint.h>\n\n/* *INDENT-OFF* */\n#ifdef __cplusplus\n    extern \"C\" {\n#endif\n/* *INDENT-ON* */\n\n/*\n * Port specific definitions -- entering/exiting critical section.\n * Refer template -- ./lib/FreeRTOS/portable/Compiler/Arch/portmacro.h\n *\n * Every call to ATOMIC_EXIT_CRITICAL() must be closely paired with\n * ATOMIC_ENTER_CRITICAL().\n *\n */\n#if defined( portSET_INTERRUPT_MASK_FROM_ISR )\n\n/* Nested interrupt scheme is supported in this port. */\n    #define ATOMIC_ENTER_CRITICAL() \\\n    UBaseType_t uxCriticalSectionType = portSET_INTERRUPT_MASK_FROM_ISR()\n\n    #define ATOMIC_EXIT_CRITICAL() \\\n    portCLEAR_INTERRUPT_MASK_FROM_ISR( uxCriticalSectionType )\n\n#else\n\n/* Nested interrupt scheme is NOT supported in this port. */\n    #define ATOMIC_ENTER_CRITICAL()    portENTER_CRITICAL()\n    #define ATOMIC_EXIT_CRITICAL()     portEXIT_CRITICAL()\n\n#endif /* portSET_INTERRUPT_MASK_FROM_ISR() */\n\n/*\n * Port specific definition -- \"always inline\".\n * Inline is compiler specific, and may not always get inlined depending on your\n * optimization level.  Also, inline is considered as performance optimization\n * for atomic.  Thus, if portFORCE_INLINE is not provided by portmacro.h,\n * instead of resulting error, simply define it away.\n */\n#ifndef portFORCE_INLINE\n    #define portFORCE_INLINE\n#endif\n\n#define ATOMIC_COMPARE_AND_SWAP_SUCCESS    0x1U     /**< Compare and swap succeeded, swapped. */\n#define ATOMIC_COMPARE_AND_SWAP_FAILURE    0x0U     /**< Compare and swap failed, did not swap. */\n\n/*----------------------------- Swap && CAS ------------------------------*/\n\n/**\n * Atomic compare-and-swap\n *\n * @brief Performs an atomic compare-and-swap operation on the specified values.\n *\n * @param[in, out] pulDestination  Pointer to memory location from where value is\n *                               to be loaded and checked.\n * @param[in] ulExchange         If condition meets, write this value to memory.\n * @param[in] ulComparand        Swap condition.\n *\n * @return Unsigned integer of value 1 or 0. 1 for swapped, 0 for not swapped.\n *\n * @note This function only swaps *pulDestination with ulExchange, if previous\n *       *pulDestination value equals ulComparand.\n */\nstatic portFORCE_INLINE uint32_t Atomic_CompareAndSwap_u32( uint32_t volatile * pulDestination,\n                                                            uint32_t ulExchange,\n                                                            uint32_t ulComparand )\n{\n    uint32_t ulReturnValue;\n\n    ATOMIC_ENTER_CRITICAL();\n    {\n        if( *pulDestination == ulComparand )\n        {\n            *pulDestination = ulExchange;\n            ulReturnValue = ATOMIC_COMPARE_AND_SWAP_SUCCESS;\n        }\n        else\n        {\n            ulReturnValue = ATOMIC_COMPARE_AND_SWAP_FAILURE;\n        }\n    }\n    ATOMIC_EXIT_CRITICAL();\n\n    return ulReturnValue;\n}\n/*-----------------------------------------------------------*/\n\n/**\n * Atomic swap (pointers)\n *\n * @brief Atomically sets the address pointed to by *ppvDestination to the value\n *        of *pvExchange.\n *\n * @param[in, out] ppvDestination  Pointer to memory location from where a pointer\n *                                 value is to be loaded and written back to.\n * @param[in] pvExchange           Pointer value to be written to *ppvDestination.\n *\n * @return The initial value of *ppvDestination.\n */\nstatic portFORCE_INLINE void * Atomic_SwapPointers_p32( void * volatile * ppvDestination,\n                                                        void * pvExchange )\n{\n    void * pReturnValue;\n\n    ATOMIC_ENTER_CRITICAL();\n    {\n        pReturnValue = *ppvDestination;\n        *ppvDestination = pvExchange;\n    }\n    ATOMIC_EXIT_CRITICAL();\n\n    return pReturnValue;\n}\n/*-----------------------------------------------------------*/\n\n/**\n * Atomic compare-and-swap (pointers)\n *\n * @brief Performs an atomic compare-and-swap operation on the specified pointer\n *        values.\n *\n * @param[in, out] ppvDestination  Pointer to memory location from where a pointer\n *                                 value is to be loaded and checked.\n * @param[in] pvExchange           If condition meets, write this value to memory.\n * @param[in] pvComparand          Swap condition.\n *\n * @return Unsigned integer of value 1 or 0. 1 for swapped, 0 for not swapped.\n *\n * @note This function only swaps *ppvDestination with pvExchange, if previous\n *       *ppvDestination value equals pvComparand.\n */\nstatic portFORCE_INLINE uint32_t Atomic_CompareAndSwapPointers_p32( void * volatile * ppvDestination,\n                                                                    void * pvExchange,\n                                                                    void * pvComparand )\n{\n    uint32_t ulReturnValue = ATOMIC_COMPARE_AND_SWAP_FAILURE;\n\n    ATOMIC_ENTER_CRITICAL();\n    {\n        if( *ppvDestination == pvComparand )\n        {\n            *ppvDestination = pvExchange;\n            ulReturnValue = ATOMIC_COMPARE_AND_SWAP_SUCCESS;\n        }\n    }\n    ATOMIC_EXIT_CRITICAL();\n\n    return ulReturnValue;\n}\n\n\n/*----------------------------- Arithmetic ------------------------------*/\n\n/**\n * Atomic add\n *\n * @brief Atomically adds count to the value of the specified pointer points to.\n *\n * @param[in,out] pulAddend  Pointer to memory location from where value is to be\n *                         loaded and written back to.\n * @param[in] ulCount      Value to be added to *pulAddend.\n *\n * @return previous *pulAddend value.\n */\nstatic portFORCE_INLINE uint32_t Atomic_Add_u32( uint32_t volatile * pulAddend,\n                                                 uint32_t ulCount )\n{\n    uint32_t ulCurrent;\n\n    ATOMIC_ENTER_CRITICAL();\n    {\n        ulCurrent = *pulAddend;\n        *pulAddend += ulCount;\n    }\n    ATOMIC_EXIT_CRITICAL();\n\n    return ulCurrent;\n}\n/*-----------------------------------------------------------*/\n\n/**\n * Atomic subtract\n *\n * @brief Atomically subtracts count from the value of the specified pointer\n *        pointers to.\n *\n * @param[in,out] pulAddend  Pointer to memory location from where value is to be\n *                         loaded and written back to.\n * @param[in] ulCount      Value to be subtract from *pulAddend.\n *\n * @return previous *pulAddend value.\n */\nstatic portFORCE_INLINE uint32_t Atomic_Subtract_u32( uint32_t volatile * pulAddend,\n                                                      uint32_t ulCount )\n{\n    uint32_t ulCurrent;\n\n    ATOMIC_ENTER_CRITICAL();\n    {\n        ulCurrent = *pulAddend;\n        *pulAddend -= ulCount;\n    }\n    ATOMIC_EXIT_CRITICAL();\n\n    return ulCurrent;\n}\n/*-----------------------------------------------------------*/\n\n/**\n * Atomic increment\n *\n * @brief Atomically increments the value of the specified pointer points to.\n *\n * @param[in,out] pulAddend  Pointer to memory location from where value is to be\n *                         loaded and written back to.\n *\n * @return *pulAddend value before increment.\n */\nstatic portFORCE_INLINE uint32_t Atomic_Increment_u32( uint32_t volatile * pulAddend )\n{\n    uint32_t ulCurrent;\n\n    ATOMIC_ENTER_CRITICAL();\n    {\n        ulCurrent = *pulAddend;\n        *pulAddend += 1;\n    }\n    ATOMIC_EXIT_CRITICAL();\n\n    return ulCurrent;\n}\n/*-----------------------------------------------------------*/\n\n/**\n * Atomic decrement\n *\n * @brief Atomically decrements the value of the specified pointer points to\n *\n * @param[in,out] pulAddend  Pointer to memory location from where value is to be\n *                         loaded and written back to.\n *\n * @return *pulAddend value before decrement.\n */\nstatic portFORCE_INLINE uint32_t Atomic_Decrement_u32( uint32_t volatile * pulAddend )\n{\n    uint32_t ulCurrent;\n\n    ATOMIC_ENTER_CRITICAL();\n    {\n        ulCurrent = *pulAddend;\n        *pulAddend -= 1;\n    }\n    ATOMIC_EXIT_CRITICAL();\n\n    return ulCurrent;\n}\n\n/*----------------------------- Bitwise Logical ------------------------------*/\n\n/**\n * Atomic OR\n *\n * @brief Performs an atomic OR operation on the specified values.\n *\n * @param [in, out] pulDestination  Pointer to memory location from where value is\n *                                to be loaded and written back to.\n * @param [in] ulValue            Value to be ORed with *pulDestination.\n *\n * @return The original value of *pulDestination.\n */\nstatic portFORCE_INLINE uint32_t Atomic_OR_u32( uint32_t volatile * pulDestination,\n                                                uint32_t ulValue )\n{\n    uint32_t ulCurrent;\n\n    ATOMIC_ENTER_CRITICAL();\n    {\n        ulCurrent = *pulDestination;\n        *pulDestination |= ulValue;\n    }\n    ATOMIC_EXIT_CRITICAL();\n\n    return ulCurrent;\n}\n/*-----------------------------------------------------------*/\n\n/**\n * Atomic AND\n *\n * @brief Performs an atomic AND operation on the specified values.\n *\n * @param [in, out] pulDestination  Pointer to memory location from where value is\n *                                to be loaded and written back to.\n * @param [in] ulValue            Value to be ANDed with *pulDestination.\n *\n * @return The original value of *pulDestination.\n */\nstatic portFORCE_INLINE uint32_t Atomic_AND_u32( uint32_t volatile * pulDestination,\n                                                 uint32_t ulValue )\n{\n    uint32_t ulCurrent;\n\n    ATOMIC_ENTER_CRITICAL();\n    {\n        ulCurrent = *pulDestination;\n        *pulDestination &= ulValue;\n    }\n    ATOMIC_EXIT_CRITICAL();\n\n    return ulCurrent;\n}\n/*-----------------------------------------------------------*/\n\n/**\n * Atomic NAND\n *\n * @brief Performs an atomic NAND operation on the specified values.\n *\n * @param [in, out] pulDestination  Pointer to memory location from where value is\n *                                to be loaded and written back to.\n * @param [in] ulValue            Value to be NANDed with *pulDestination.\n *\n * @return The original value of *pulDestination.\n */\nstatic portFORCE_INLINE uint32_t Atomic_NAND_u32( uint32_t volatile * pulDestination,\n                                                  uint32_t ulValue )\n{\n    uint32_t ulCurrent;\n\n    ATOMIC_ENTER_CRITICAL();\n    {\n        ulCurrent = *pulDestination;\n        *pulDestination = ~( ulCurrent & ulValue );\n    }\n    ATOMIC_EXIT_CRITICAL();\n\n    return ulCurrent;\n}\n/*-----------------------------------------------------------*/\n\n/**\n * Atomic XOR\n *\n * @brief Performs an atomic XOR operation on the specified values.\n *\n * @param [in, out] pulDestination  Pointer to memory location from where value is\n *                                to be loaded and written back to.\n * @param [in] ulValue            Value to be XORed with *pulDestination.\n *\n * @return The original value of *pulDestination.\n */\nstatic portFORCE_INLINE uint32_t Atomic_XOR_u32( uint32_t volatile * pulDestination,\n                                                 uint32_t ulValue )\n{\n    uint32_t ulCurrent;\n\n    ATOMIC_ENTER_CRITICAL();\n    {\n        ulCurrent = *pulDestination;\n        *pulDestination ^= ulValue;\n    }\n    ATOMIC_EXIT_CRITICAL();\n\n    return ulCurrent;\n}\n\n/* *INDENT-OFF* */\n#ifdef __cplusplus\n    }\n#endif\n/* *INDENT-ON* */\n\n#endif /* ATOMIC_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/include/croutine.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef CO_ROUTINE_H\n#define CO_ROUTINE_H\n\n#ifndef INC_FREERTOS_H\n    #error \"include FreeRTOS.h must appear in source files before include croutine.h\"\n#endif\n\n#include \"list.h\"\n\n/* *INDENT-OFF* */\n#ifdef __cplusplus\n    extern \"C\" {\n#endif\n/* *INDENT-ON* */\n\n/* Used to hide the implementation of the co-routine control block.  The\n * control block structure however has to be included in the header due to\n * the macro implementation of the co-routine functionality. */\ntypedef void * CoRoutineHandle_t;\n\n/* Defines the prototype to which co-routine functions must conform. */\ntypedef void (* crCOROUTINE_CODE)( CoRoutineHandle_t,\n                                   UBaseType_t );\n\ntypedef struct corCoRoutineControlBlock\n{\n    crCOROUTINE_CODE pxCoRoutineFunction;\n    ListItem_t xGenericListItem; /*< List item used to place the CRCB in ready and blocked queues. */\n    ListItem_t xEventListItem;   /*< List item used to place the CRCB in event lists. */\n    UBaseType_t uxPriority;      /*< The priority of the co-routine in relation to other co-routines. */\n    UBaseType_t uxIndex;         /*< Used to distinguish between co-routines when multiple co-routines use the same co-routine function. */\n    uint16_t uxState;            /*< Used internally by the co-routine implementation. */\n} CRCB_t;                        /* Co-routine control block.  Note must be identical in size down to uxPriority with TCB_t. */\n\n/**\n * croutine. h\n * @code{c}\n * BaseType_t xCoRoutineCreate(\n *                               crCOROUTINE_CODE pxCoRoutineCode,\n *                               UBaseType_t uxPriority,\n *                               UBaseType_t uxIndex\n *                             );\n * @endcode\n *\n * Create a new co-routine and add it to the list of co-routines that are\n * ready to run.\n *\n * @param pxCoRoutineCode Pointer to the co-routine function.  Co-routine\n * functions require special syntax - see the co-routine section of the WEB\n * documentation for more information.\n *\n * @param uxPriority The priority with respect to other co-routines at which\n *  the co-routine will run.\n *\n * @param uxIndex Used to distinguish between different co-routines that\n * execute the same function.  See the example below and the co-routine section\n * of the WEB documentation for further information.\n *\n * @return pdPASS if the co-routine was successfully created and added to a ready\n * list, otherwise an error code defined with ProjDefs.h.\n *\n * Example usage:\n * @code{c}\n * // Co-routine to be created.\n * void vFlashCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )\n * {\n * // Variables in co-routines must be declared static if they must maintain value across a blocking call.\n * // This may not be necessary for const variables.\n * static const char cLedToFlash[ 2 ] = { 5, 6 };\n * static const TickType_t uxFlashRates[ 2 ] = { 200, 400 };\n *\n *   // Must start every co-routine with a call to crSTART();\n *   crSTART( xHandle );\n *\n *   for( ;; )\n *   {\n *       // This co-routine just delays for a fixed period, then toggles\n *       // an LED.  Two co-routines are created using this function, so\n *       // the uxIndex parameter is used to tell the co-routine which\n *       // LED to flash and how int32_t to delay.  This assumes xQueue has\n *       // already been created.\n *       vParTestToggleLED( cLedToFlash[ uxIndex ] );\n *       crDELAY( xHandle, uxFlashRates[ uxIndex ] );\n *   }\n *\n *   // Must end every co-routine with a call to crEND();\n *   crEND();\n * }\n *\n * // Function that creates two co-routines.\n * void vOtherFunction( void )\n * {\n * uint8_t ucParameterToPass;\n * TaskHandle_t xHandle;\n *\n *   // Create two co-routines at priority 0.  The first is given index 0\n *   // so (from the code above) toggles LED 5 every 200 ticks.  The second\n *   // is given index 1 so toggles LED 6 every 400 ticks.\n *   for( uxIndex = 0; uxIndex < 2; uxIndex++ )\n *   {\n *       xCoRoutineCreate( vFlashCoRoutine, 0, uxIndex );\n *   }\n * }\n * @endcode\n * \\defgroup xCoRoutineCreate xCoRoutineCreate\n * \\ingroup Tasks\n */\nBaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode,\n                             UBaseType_t uxPriority,\n                             UBaseType_t uxIndex );\n\n\n/**\n * croutine. h\n * @code{c}\n * void vCoRoutineSchedule( void );\n * @endcode\n *\n * Run a co-routine.\n *\n * vCoRoutineSchedule() executes the highest priority co-routine that is able\n * to run.  The co-routine will execute until it either blocks, yields or is\n * preempted by a task.  Co-routines execute cooperatively so one\n * co-routine cannot be preempted by another, but can be preempted by a task.\n *\n * If an application comprises of both tasks and co-routines then\n * vCoRoutineSchedule should be called from the idle task (in an idle task\n * hook).\n *\n * Example usage:\n * @code{c}\n * // This idle task hook will schedule a co-routine each time it is called.\n * // The rest of the idle task will execute between co-routine calls.\n * void vApplicationIdleHook( void )\n * {\n *  vCoRoutineSchedule();\n * }\n *\n * // Alternatively, if you do not require any other part of the idle task to\n * // execute, the idle task hook can call vCoRoutineSchedule() within an\n * // infinite loop.\n * void vApplicationIdleHook( void )\n * {\n *  for( ;; )\n *  {\n *      vCoRoutineSchedule();\n *  }\n * }\n * @endcode\n * \\defgroup vCoRoutineSchedule vCoRoutineSchedule\n * \\ingroup Tasks\n */\nvoid vCoRoutineSchedule( void );\n\n/**\n * croutine. h\n * @code{c}\n * crSTART( CoRoutineHandle_t xHandle );\n * @endcode\n *\n * This macro MUST always be called at the start of a co-routine function.\n *\n * Example usage:\n * @code{c}\n * // Co-routine to be created.\n * void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )\n * {\n * // Variables in co-routines must be declared static if they must maintain value across a blocking call.\n * static int32_t ulAVariable;\n *\n *   // Must start every co-routine with a call to crSTART();\n *   crSTART( xHandle );\n *\n *   for( ;; )\n *   {\n *        // Co-routine functionality goes here.\n *   }\n *\n *   // Must end every co-routine with a call to crEND();\n *   crEND();\n * }\n * @endcode\n * \\defgroup crSTART crSTART\n * \\ingroup Tasks\n */\n#define crSTART( pxCRCB )                            \\\n    switch( ( ( CRCB_t * ) ( pxCRCB ) )->uxState ) { \\\n        case 0:\n\n/**\n * croutine. h\n * @code{c}\n * crEND();\n * @endcode\n *\n * This macro MUST always be called at the end of a co-routine function.\n *\n * Example usage:\n * @code{c}\n * // Co-routine to be created.\n * void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )\n * {\n * // Variables in co-routines must be declared static if they must maintain value across a blocking call.\n * static int32_t ulAVariable;\n *\n *   // Must start every co-routine with a call to crSTART();\n *   crSTART( xHandle );\n *\n *   for( ;; )\n *   {\n *        // Co-routine functionality goes here.\n *   }\n *\n *   // Must end every co-routine with a call to crEND();\n *   crEND();\n * }\n * @endcode\n * \\defgroup crSTART crSTART\n * \\ingroup Tasks\n */\n#define crEND()    }\n\n/*\n * These macros are intended for internal use by the co-routine implementation\n * only.  The macros should not be used directly by application writers.\n */\n#define crSET_STATE0( xHandle )                                       \\\n    ( ( CRCB_t * ) ( xHandle ) )->uxState = ( __LINE__ * 2 ); return; \\\n    case ( __LINE__ * 2 ):\n#define crSET_STATE1( xHandle )                                               \\\n    ( ( CRCB_t * ) ( xHandle ) )->uxState = ( ( __LINE__ * 2 ) + 1 ); return; \\\n    case ( ( __LINE__ * 2 ) + 1 ):\n\n/**\n * croutine. h\n * @code{c}\n * crDELAY( CoRoutineHandle_t xHandle, TickType_t xTicksToDelay );\n * @endcode\n *\n * Delay a co-routine for a fixed period of time.\n *\n * crDELAY can only be called from the co-routine function itself - not\n * from within a function called by the co-routine function.  This is because\n * co-routines do not maintain their own stack.\n *\n * @param xHandle The handle of the co-routine to delay.  This is the xHandle\n * parameter of the co-routine function.\n *\n * @param xTickToDelay The number of ticks that the co-routine should delay\n * for.  The actual amount of time this equates to is defined by\n * configTICK_RATE_HZ (set in FreeRTOSConfig.h).  The constant portTICK_PERIOD_MS\n * can be used to convert ticks to milliseconds.\n *\n * Example usage:\n * @code{c}\n * // Co-routine to be created.\n * void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )\n * {\n * // Variables in co-routines must be declared static if they must maintain value across a blocking call.\n * // This may not be necessary for const variables.\n * // We are to delay for 200ms.\n * static const xTickType xDelayTime = 200 / portTICK_PERIOD_MS;\n *\n *   // Must start every co-routine with a call to crSTART();\n *   crSTART( xHandle );\n *\n *   for( ;; )\n *   {\n *      // Delay for 200ms.\n *      crDELAY( xHandle, xDelayTime );\n *\n *      // Do something here.\n *   }\n *\n *   // Must end every co-routine with a call to crEND();\n *   crEND();\n * }\n * @endcode\n * \\defgroup crDELAY crDELAY\n * \\ingroup Tasks\n */\n#define crDELAY( xHandle, xTicksToDelay )                      \\\n    if( ( xTicksToDelay ) > 0 )                                \\\n    {                                                          \\\n        vCoRoutineAddToDelayedList( ( xTicksToDelay ), NULL ); \\\n    }                                                          \\\n    crSET_STATE0( ( xHandle ) );\n\n/**\n * @code{c}\n * crQUEUE_SEND(\n *                CoRoutineHandle_t xHandle,\n *                QueueHandle_t pxQueue,\n *                void *pvItemToQueue,\n *                TickType_t xTicksToWait,\n *                BaseType_t *pxResult\n *           )\n * @endcode\n *\n * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine\n * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks.\n *\n * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas\n * xQueueSend() and xQueueReceive() can only be used from tasks.\n *\n * crQUEUE_SEND can only be called from the co-routine function itself - not\n * from within a function called by the co-routine function.  This is because\n * co-routines do not maintain their own stack.\n *\n * See the co-routine section of the WEB documentation for information on\n * passing data between tasks and co-routines and between ISR's and\n * co-routines.\n *\n * @param xHandle The handle of the calling co-routine.  This is the xHandle\n * parameter of the co-routine function.\n *\n * @param pxQueue The handle of the queue on which the data will be posted.\n * The handle is obtained as the return value when the queue is created using\n * the xQueueCreate() API function.\n *\n * @param pvItemToQueue A pointer to the data being posted onto the queue.\n * The number of bytes of each queued item is specified when the queue is\n * created.  This number of bytes is copied from pvItemToQueue into the queue\n * itself.\n *\n * @param xTickToDelay The number of ticks that the co-routine should block\n * to wait for space to become available on the queue, should space not be\n * available immediately. The actual amount of time this equates to is defined\n * by configTICK_RATE_HZ (set in FreeRTOSConfig.h).  The constant\n * portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see example\n * below).\n *\n * @param pxResult The variable pointed to by pxResult will be set to pdPASS if\n * data was successfully posted onto the queue, otherwise it will be set to an\n * error defined within ProjDefs.h.\n *\n * Example usage:\n * @code{c}\n * // Co-routine function that blocks for a fixed period then posts a number onto\n * // a queue.\n * static void prvCoRoutineFlashTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )\n * {\n * // Variables in co-routines must be declared static if they must maintain value across a blocking call.\n * static BaseType_t xNumberToPost = 0;\n * static BaseType_t xResult;\n *\n *  // Co-routines must begin with a call to crSTART().\n *  crSTART( xHandle );\n *\n *  for( ;; )\n *  {\n *      // This assumes the queue has already been created.\n *      crQUEUE_SEND( xHandle, xCoRoutineQueue, &xNumberToPost, NO_DELAY, &xResult );\n *\n *      if( xResult != pdPASS )\n *      {\n *          // The message was not posted!\n *      }\n *\n *      // Increment the number to be posted onto the queue.\n *      xNumberToPost++;\n *\n *      // Delay for 100 ticks.\n *      crDELAY( xHandle, 100 );\n *  }\n *\n *  // Co-routines must end with a call to crEND().\n *  crEND();\n * }\n * @endcode\n * \\defgroup crQUEUE_SEND crQUEUE_SEND\n * \\ingroup Tasks\n */\n#define crQUEUE_SEND( xHandle, pxQueue, pvItemToQueue, xTicksToWait, pxResult )           \\\n    {                                                                                     \\\n        *( pxResult ) = xQueueCRSend( ( pxQueue ), ( pvItemToQueue ), ( xTicksToWait ) ); \\\n        if( *( pxResult ) == errQUEUE_BLOCKED )                                           \\\n        {                                                                                 \\\n            crSET_STATE0( ( xHandle ) );                                                  \\\n            *pxResult = xQueueCRSend( ( pxQueue ), ( pvItemToQueue ), 0 );                \\\n        }                                                                                 \\\n        if( *pxResult == errQUEUE_YIELD )                                                 \\\n        {                                                                                 \\\n            crSET_STATE1( ( xHandle ) );                                                  \\\n            *pxResult = pdPASS;                                                           \\\n        }                                                                                 \\\n    }\n\n/**\n * croutine. h\n * @code{c}\n * crQUEUE_RECEIVE(\n *                   CoRoutineHandle_t xHandle,\n *                   QueueHandle_t pxQueue,\n *                   void *pvBuffer,\n *                   TickType_t xTicksToWait,\n *                   BaseType_t *pxResult\n *               )\n * @endcode\n *\n * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine\n * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks.\n *\n * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas\n * xQueueSend() and xQueueReceive() can only be used from tasks.\n *\n * crQUEUE_RECEIVE can only be called from the co-routine function itself - not\n * from within a function called by the co-routine function.  This is because\n * co-routines do not maintain their own stack.\n *\n * See the co-routine section of the WEB documentation for information on\n * passing data between tasks and co-routines and between ISR's and\n * co-routines.\n *\n * @param xHandle The handle of the calling co-routine.  This is the xHandle\n * parameter of the co-routine function.\n *\n * @param pxQueue The handle of the queue from which the data will be received.\n * The handle is obtained as the return value when the queue is created using\n * the xQueueCreate() API function.\n *\n * @param pvBuffer The buffer into which the received item is to be copied.\n * The number of bytes of each queued item is specified when the queue is\n * created.  This number of bytes is copied into pvBuffer.\n *\n * @param xTickToDelay The number of ticks that the co-routine should block\n * to wait for data to become available from the queue, should data not be\n * available immediately. The actual amount of time this equates to is defined\n * by configTICK_RATE_HZ (set in FreeRTOSConfig.h).  The constant\n * portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see the\n * crQUEUE_SEND example).\n *\n * @param pxResult The variable pointed to by pxResult will be set to pdPASS if\n * data was successfully retrieved from the queue, otherwise it will be set to\n * an error code as defined within ProjDefs.h.\n *\n * Example usage:\n * @code{c}\n * // A co-routine receives the number of an LED to flash from a queue.  It\n * // blocks on the queue until the number is received.\n * static void prvCoRoutineFlashWorkTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )\n * {\n * // Variables in co-routines must be declared static if they must maintain value across a blocking call.\n * static BaseType_t xResult;\n * static UBaseType_t uxLEDToFlash;\n *\n *  // All co-routines must start with a call to crSTART().\n *  crSTART( xHandle );\n *\n *  for( ;; )\n *  {\n *      // Wait for data to become available on the queue.\n *      crQUEUE_RECEIVE( xHandle, xCoRoutineQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );\n *\n *      if( xResult == pdPASS )\n *      {\n *          // We received the LED to flash - flash it!\n *          vParTestToggleLED( uxLEDToFlash );\n *      }\n *  }\n *\n *  crEND();\n * }\n * @endcode\n * \\defgroup crQUEUE_RECEIVE crQUEUE_RECEIVE\n * \\ingroup Tasks\n */\n#define crQUEUE_RECEIVE( xHandle, pxQueue, pvBuffer, xTicksToWait, pxResult )           \\\n    {                                                                                   \\\n        *( pxResult ) = xQueueCRReceive( ( pxQueue ), ( pvBuffer ), ( xTicksToWait ) ); \\\n        if( *( pxResult ) == errQUEUE_BLOCKED )                                         \\\n        {                                                                               \\\n            crSET_STATE0( ( xHandle ) );                                                \\\n            *( pxResult ) = xQueueCRReceive( ( pxQueue ), ( pvBuffer ), 0 );            \\\n        }                                                                               \\\n        if( *( pxResult ) == errQUEUE_YIELD )                                           \\\n        {                                                                               \\\n            crSET_STATE1( ( xHandle ) );                                                \\\n            *( pxResult ) = pdPASS;                                                     \\\n        }                                                                               \\\n    }\n\n/**\n * croutine. h\n * @code{c}\n * crQUEUE_SEND_FROM_ISR(\n *                          QueueHandle_t pxQueue,\n *                          void *pvItemToQueue,\n *                          BaseType_t xCoRoutinePreviouslyWoken\n *                     )\n * @endcode\n *\n * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the\n * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR()\n * functions used by tasks.\n *\n * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to\n * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and\n * xQueueReceiveFromISR() can only be used to pass data between a task and and\n * ISR.\n *\n * crQUEUE_SEND_FROM_ISR can only be called from an ISR to send data to a queue\n * that is being used from within a co-routine.\n *\n * See the co-routine section of the WEB documentation for information on\n * passing data between tasks and co-routines and between ISR's and\n * co-routines.\n *\n * @param xQueue The handle to the queue on which the item is to be posted.\n *\n * @param pvItemToQueue A pointer to the item that is to be placed on the\n * queue.  The size of the items the queue will hold was defined when the\n * queue was created, so this many bytes will be copied from pvItemToQueue\n * into the queue storage area.\n *\n * @param xCoRoutinePreviouslyWoken This is included so an ISR can post onto\n * the same queue multiple times from a single interrupt.  The first call\n * should always pass in pdFALSE.  Subsequent calls should pass in\n * the value returned from the previous call.\n *\n * @return pdTRUE if a co-routine was woken by posting onto the queue.  This is\n * used by the ISR to determine if a context switch may be required following\n * the ISR.\n *\n * Example usage:\n * @code{c}\n * // A co-routine that blocks on a queue waiting for characters to be received.\n * static void vReceivingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )\n * {\n * char cRxedChar;\n * BaseType_t xResult;\n *\n *   // All co-routines must start with a call to crSTART().\n *   crSTART( xHandle );\n *\n *   for( ;; )\n *   {\n *       // Wait for data to become available on the queue.  This assumes the\n *       // queue xCommsRxQueue has already been created!\n *       crQUEUE_RECEIVE( xHandle, xCommsRxQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );\n *\n *       // Was a character received?\n *       if( xResult == pdPASS )\n *       {\n *           // Process the character here.\n *       }\n *   }\n *\n *   // All co-routines must end with a call to crEND().\n *   crEND();\n * }\n *\n * // An ISR that uses a queue to send characters received on a serial port to\n * // a co-routine.\n * void vUART_ISR( void )\n * {\n * char cRxedChar;\n * BaseType_t xCRWokenByPost = pdFALSE;\n *\n *   // We loop around reading characters until there are none left in the UART.\n *   while( UART_RX_REG_NOT_EMPTY() )\n *   {\n *       // Obtain the character from the UART.\n *       cRxedChar = UART_RX_REG;\n *\n *       // Post the character onto a queue.  xCRWokenByPost will be pdFALSE\n *       // the first time around the loop.  If the post causes a co-routine\n *       // to be woken (unblocked) then xCRWokenByPost will be set to pdTRUE.\n *       // In this manner we can ensure that if more than one co-routine is\n *       // blocked on the queue only one is woken by this ISR no matter how\n *       // many characters are posted to the queue.\n *       xCRWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsRxQueue, &cRxedChar, xCRWokenByPost );\n *   }\n * }\n * @endcode\n * \\defgroup crQUEUE_SEND_FROM_ISR crQUEUE_SEND_FROM_ISR\n * \\ingroup Tasks\n */\n#define crQUEUE_SEND_FROM_ISR( pxQueue, pvItemToQueue, xCoRoutinePreviouslyWoken ) \\\n    xQueueCRSendFromISR( ( pxQueue ), ( pvItemToQueue ), ( xCoRoutinePreviouslyWoken ) )\n\n\n/**\n * croutine. h\n * @code{c}\n * crQUEUE_SEND_FROM_ISR(\n *                          QueueHandle_t pxQueue,\n *                          void *pvBuffer,\n *                          BaseType_t * pxCoRoutineWoken\n *                     )\n * @endcode\n *\n * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the\n * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR()\n * functions used by tasks.\n *\n * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to\n * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and\n * xQueueReceiveFromISR() can only be used to pass data between a task and and\n * ISR.\n *\n * crQUEUE_RECEIVE_FROM_ISR can only be called from an ISR to receive data\n * from a queue that is being used from within a co-routine (a co-routine\n * posted to the queue).\n *\n * See the co-routine section of the WEB documentation for information on\n * passing data between tasks and co-routines and between ISR's and\n * co-routines.\n *\n * @param xQueue The handle to the queue on which the item is to be posted.\n *\n * @param pvBuffer A pointer to a buffer into which the received item will be\n * placed.  The size of the items the queue will hold was defined when the\n * queue was created, so this many bytes will be copied from the queue into\n * pvBuffer.\n *\n * @param pxCoRoutineWoken A co-routine may be blocked waiting for space to become\n * available on the queue.  If crQUEUE_RECEIVE_FROM_ISR causes such a\n * co-routine to unblock *pxCoRoutineWoken will get set to pdTRUE, otherwise\n * *pxCoRoutineWoken will remain unchanged.\n *\n * @return pdTRUE an item was successfully received from the queue, otherwise\n * pdFALSE.\n *\n * Example usage:\n * @code{c}\n * // A co-routine that posts a character to a queue then blocks for a fixed\n * // period.  The character is incremented each time.\n * static void vSendingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )\n * {\n * // cChar holds its value while this co-routine is blocked and must therefore\n * // be declared static.\n * static char cCharToTx = 'a';\n * BaseType_t xResult;\n *\n *   // All co-routines must start with a call to crSTART().\n *   crSTART( xHandle );\n *\n *   for( ;; )\n *   {\n *       // Send the next character to the queue.\n *       crQUEUE_SEND( xHandle, xCoRoutineQueue, &cCharToTx, NO_DELAY, &xResult );\n *\n *       if( xResult == pdPASS )\n *       {\n *           // The character was successfully posted to the queue.\n *       }\n *       else\n *       {\n *          // Could not post the character to the queue.\n *       }\n *\n *       // Enable the UART Tx interrupt to cause an interrupt in this\n *       // hypothetical UART.  The interrupt will obtain the character\n *       // from the queue and send it.\n *       ENABLE_RX_INTERRUPT();\n *\n *       // Increment to the next character then block for a fixed period.\n *       // cCharToTx will maintain its value across the delay as it is\n *       // declared static.\n *       cCharToTx++;\n *       if( cCharToTx > 'x' )\n *       {\n *          cCharToTx = 'a';\n *       }\n *       crDELAY( 100 );\n *   }\n *\n *   // All co-routines must end with a call to crEND().\n *   crEND();\n * }\n *\n * // An ISR that uses a queue to receive characters to send on a UART.\n * void vUART_ISR( void )\n * {\n * char cCharToTx;\n * BaseType_t xCRWokenByPost = pdFALSE;\n *\n *   while( UART_TX_REG_EMPTY() )\n *   {\n *       // Are there any characters in the queue waiting to be sent?\n *       // xCRWokenByPost will automatically be set to pdTRUE if a co-routine\n *       // is woken by the post - ensuring that only a single co-routine is\n *       // woken no matter how many times we go around this loop.\n *       if( crQUEUE_RECEIVE_FROM_ISR( pxQueue, &cCharToTx, &xCRWokenByPost ) )\n *       {\n *           SEND_CHARACTER( cCharToTx );\n *       }\n *   }\n * }\n * @endcode\n * \\defgroup crQUEUE_RECEIVE_FROM_ISR crQUEUE_RECEIVE_FROM_ISR\n * \\ingroup Tasks\n */\n#define crQUEUE_RECEIVE_FROM_ISR( pxQueue, pvBuffer, pxCoRoutineWoken ) \\\n    xQueueCRReceiveFromISR( ( pxQueue ), ( pvBuffer ), ( pxCoRoutineWoken ) )\n\n/*\n * This function is intended for internal use by the co-routine macros only.\n * The macro nature of the co-routine implementation requires that the\n * prototype appears here.  The function should not be used by application\n * writers.\n *\n * Removes the current co-routine from its ready list and places it in the\n * appropriate delayed list.\n */\nvoid vCoRoutineAddToDelayedList( TickType_t xTicksToDelay,\n                                 List_t * pxEventList );\n\n/*\n * This function is intended for internal use by the queue implementation only.\n * The function should not be used by application writers.\n *\n * Removes the highest priority co-routine from the event list and places it in\n * the pending ready list.\n */\nBaseType_t xCoRoutineRemoveFromEventList( const List_t * pxEventList );\n\n/* *INDENT-OFF* */\n#ifdef __cplusplus\n    }\n#endif\n/* *INDENT-ON* */\n\n#endif /* CO_ROUTINE_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/include/deprecated_definitions.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef DEPRECATED_DEFINITIONS_H\n#define DEPRECATED_DEFINITIONS_H\n\n\n/* Each FreeRTOS port has a unique portmacro.h header file.  Originally a\n * pre-processor definition was used to ensure the pre-processor found the correct\n * portmacro.h file for the port being used.  That scheme was deprecated in favour\n * of setting the compiler's include path such that it found the correct\n * portmacro.h file - removing the need for the constant and allowing the\n * portmacro.h file to be located anywhere in relation to the port being used.  The\n * definitions below remain in the code for backward compatibility only.  New\n * projects should not use them. */\n\n#ifdef OPEN_WATCOM_INDUSTRIAL_PC_PORT\n    #include \"..\\..\\Source\\portable\\owatcom\\16bitdos\\pc\\portmacro.h\"\n    typedef void ( __interrupt __far * pxISR )();\n#endif\n\n#ifdef OPEN_WATCOM_FLASH_LITE_186_PORT\n    #include \"..\\..\\Source\\portable\\owatcom\\16bitdos\\flsh186\\portmacro.h\"\n    typedef void ( __interrupt __far * pxISR )();\n#endif\n\n#ifdef GCC_MEGA_AVR\n    #include \"../portable/GCC/ATMega323/portmacro.h\"\n#endif\n\n#ifdef IAR_MEGA_AVR\n    #include \"../portable/IAR/ATMega323/portmacro.h\"\n#endif\n\n#ifdef MPLAB_PIC24_PORT\n    #include \"../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h\"\n#endif\n\n#ifdef MPLAB_DSPIC_PORT\n    #include \"../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h\"\n#endif\n\n#ifdef MPLAB_PIC18F_PORT\n    #include \"../../Source/portable/MPLAB/PIC18F/portmacro.h\"\n#endif\n\n#ifdef MPLAB_PIC32MX_PORT\n    #include \"../../Source/portable/MPLAB/PIC32MX/portmacro.h\"\n#endif\n\n#ifdef _FEDPICC\n    #include \"libFreeRTOS/Include/portmacro.h\"\n#endif\n\n#ifdef SDCC_CYGNAL\n    #include \"../../Source/portable/SDCC/Cygnal/portmacro.h\"\n#endif\n\n#ifdef GCC_ARM7\n    #include \"../../Source/portable/GCC/ARM7_LPC2000/portmacro.h\"\n#endif\n\n#ifdef GCC_ARM7_ECLIPSE\n    #include \"portmacro.h\"\n#endif\n\n#ifdef ROWLEY_LPC23xx\n    #include \"../../Source/portable/GCC/ARM7_LPC23xx/portmacro.h\"\n#endif\n\n#ifdef IAR_MSP430\n    #include \"..\\..\\Source\\portable\\IAR\\MSP430\\portmacro.h\"\n#endif\n\n#ifdef GCC_MSP430\n    #include \"../../Source/portable/GCC/MSP430F449/portmacro.h\"\n#endif\n\n#ifdef ROWLEY_MSP430\n    #include \"../../Source/portable/Rowley/MSP430F449/portmacro.h\"\n#endif\n\n#ifdef ARM7_LPC21xx_KEIL_RVDS\n    #include \"..\\..\\Source\\portable\\RVDS\\ARM7_LPC21xx\\portmacro.h\"\n#endif\n\n#ifdef SAM7_GCC\n    #include \"../../Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h\"\n#endif\n\n#ifdef SAM7_IAR\n    #include \"..\\..\\Source\\portable\\IAR\\AtmelSAM7S64\\portmacro.h\"\n#endif\n\n#ifdef SAM9XE_IAR\n    #include \"..\\..\\Source\\portable\\IAR\\AtmelSAM9XE\\portmacro.h\"\n#endif\n\n#ifdef LPC2000_IAR\n    #include \"..\\..\\Source\\portable\\IAR\\LPC2000\\portmacro.h\"\n#endif\n\n#ifdef STR71X_IAR\n    #include \"..\\..\\Source\\portable\\IAR\\STR71x\\portmacro.h\"\n#endif\n\n#ifdef STR75X_IAR\n    #include \"..\\..\\Source\\portable\\IAR\\STR75x\\portmacro.h\"\n#endif\n\n#ifdef STR75X_GCC\n    #include \"..\\..\\Source\\portable\\GCC\\STR75x\\portmacro.h\"\n#endif\n\n#ifdef STR91X_IAR\n    #include \"..\\..\\Source\\portable\\IAR\\STR91x\\portmacro.h\"\n#endif\n\n#ifdef GCC_H8S\n    #include \"../../Source/portable/GCC/H8S2329/portmacro.h\"\n#endif\n\n#ifdef GCC_AT91FR40008\n    #include \"../../Source/portable/GCC/ARM7_AT91FR40008/portmacro.h\"\n#endif\n\n#ifdef RVDS_ARMCM3_LM3S102\n    #include \"../../Source/portable/RVDS/ARM_CM3/portmacro.h\"\n#endif\n\n#ifdef GCC_ARMCM3_LM3S102\n    #include \"../../Source/portable/GCC/ARM_CM3/portmacro.h\"\n#endif\n\n#ifdef GCC_ARMCM3\n    #include \"../../Source/portable/GCC/ARM_CM3/portmacro.h\"\n#endif\n\n#ifdef IAR_ARM_CM3\n    #include \"../../Source/portable/IAR/ARM_CM3/portmacro.h\"\n#endif\n\n#ifdef IAR_ARMCM3_LM\n    #include \"../../Source/portable/IAR/ARM_CM3/portmacro.h\"\n#endif\n\n#ifdef HCS12_CODE_WARRIOR\n    #include \"../../Source/portable/CodeWarrior/HCS12/portmacro.h\"\n#endif\n\n#ifdef MICROBLAZE_GCC\n    #include \"../../Source/portable/GCC/MicroBlaze/portmacro.h\"\n#endif\n\n#ifdef TERN_EE\n    #include \"..\\..\\Source\\portable\\Paradigm\\Tern_EE\\small\\portmacro.h\"\n#endif\n\n#ifdef GCC_HCS12\n    #include \"../../Source/portable/GCC/HCS12/portmacro.h\"\n#endif\n\n#ifdef GCC_MCF5235\n    #include \"../../Source/portable/GCC/MCF5235/portmacro.h\"\n#endif\n\n#ifdef COLDFIRE_V2_GCC\n    #include \"../../../Source/portable/GCC/ColdFire_V2/portmacro.h\"\n#endif\n\n#ifdef COLDFIRE_V2_CODEWARRIOR\n    #include \"../../Source/portable/CodeWarrior/ColdFire_V2/portmacro.h\"\n#endif\n\n#ifdef GCC_PPC405\n    #include \"../../Source/portable/GCC/PPC405_Xilinx/portmacro.h\"\n#endif\n\n#ifdef GCC_PPC440\n    #include \"../../Source/portable/GCC/PPC440_Xilinx/portmacro.h\"\n#endif\n\n#ifdef _16FX_SOFTUNE\n    #include \"..\\..\\Source\\portable\\Softune\\MB96340\\portmacro.h\"\n#endif\n\n#ifdef BCC_INDUSTRIAL_PC_PORT\n\n/* A short file name has to be used in place of the normal\n * FreeRTOSConfig.h when using the Borland compiler. */\n    #include \"frconfig.h\"\n    #include \"..\\portable\\BCC\\16BitDOS\\PC\\prtmacro.h\"\n    typedef void ( __interrupt __far * pxISR )();\n#endif\n\n#ifdef BCC_FLASH_LITE_186_PORT\n\n/* A short file name has to be used in place of the normal\n * FreeRTOSConfig.h when using the Borland compiler. */\n    #include \"frconfig.h\"\n    #include \"..\\portable\\BCC\\16BitDOS\\flsh186\\prtmacro.h\"\n    typedef void ( __interrupt __far * pxISR )();\n#endif\n\n#ifdef __GNUC__\n    #ifdef __AVR32_AVR32A__\n        #include \"portmacro.h\"\n    #endif\n#endif\n\n#ifdef __ICCAVR32__\n    #ifdef __CORE__\n        #if __CORE__ == __AVR32A__\n            #include \"portmacro.h\"\n        #endif\n    #endif\n#endif\n\n#ifdef __91467D\n    #include \"portmacro.h\"\n#endif\n\n#ifdef __96340\n    #include \"portmacro.h\"\n#endif\n\n\n#ifdef __IAR_V850ES_Fx3__\n    #include \"../../Source/portable/IAR/V850ES/portmacro.h\"\n#endif\n\n#ifdef __IAR_V850ES_Jx3__\n    #include \"../../Source/portable/IAR/V850ES/portmacro.h\"\n#endif\n\n#ifdef __IAR_V850ES_Jx3_L__\n    #include \"../../Source/portable/IAR/V850ES/portmacro.h\"\n#endif\n\n#ifdef __IAR_V850ES_Jx2__\n    #include \"../../Source/portable/IAR/V850ES/portmacro.h\"\n#endif\n\n#ifdef __IAR_V850ES_Hx2__\n    #include \"../../Source/portable/IAR/V850ES/portmacro.h\"\n#endif\n\n#ifdef __IAR_78K0R_Kx3__\n    #include \"../../Source/portable/IAR/78K0R/portmacro.h\"\n#endif\n\n#ifdef __IAR_78K0R_Kx3L__\n    #include \"../../Source/portable/IAR/78K0R/portmacro.h\"\n#endif\n\n#endif /* DEPRECATED_DEFINITIONS_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/include/event_groups.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef EVENT_GROUPS_H\n#define EVENT_GROUPS_H\n\n#ifndef INC_FREERTOS_H\n    #error \"include FreeRTOS.h\" must appear in source files before \"include event_groups.h\"\n#endif\n\n/* FreeRTOS includes. */\n#include \"timers.h\"\n\n/* *INDENT-OFF* */\n#ifdef __cplusplus\n    extern \"C\" {\n#endif\n/* *INDENT-ON* */\n\n/**\n * An event group is a collection of bits to which an application can assign a\n * meaning.  For example, an application may create an event group to convey\n * the status of various CAN bus related events in which bit 0 might mean \"A CAN\n * message has been received and is ready for processing\", bit 1 might mean \"The\n * application has queued a message that is ready for sending onto the CAN\n * network\", and bit 2 might mean \"It is time to send a SYNC message onto the\n * CAN network\" etc.  A task can then test the bit values to see which events\n * are active, and optionally enter the Blocked state to wait for a specified\n * bit or a group of specified bits to be active.  To continue the CAN bus\n * example, a CAN controlling task can enter the Blocked state (and therefore\n * not consume any processing time) until either bit 0, bit 1 or bit 2 are\n * active, at which time the bit that was actually active would inform the task\n * which action it had to take (process a received message, send a message, or\n * send a SYNC).\n *\n * The event groups implementation contains intelligence to avoid race\n * conditions that would otherwise occur were an application to use a simple\n * variable for the same purpose.  This is particularly important with respect\n * to when a bit within an event group is to be cleared, and when bits have to\n * be set and then tested atomically - as is the case where event groups are\n * used to create a synchronisation point between multiple tasks (a\n * 'rendezvous').\n */\n\n\n\n/**\n * event_groups.h\n *\n * Type by which event groups are referenced.  For example, a call to\n * xEventGroupCreate() returns an EventGroupHandle_t variable that can then\n * be used as a parameter to other event group functions.\n *\n * \\defgroup EventGroupHandle_t EventGroupHandle_t\n * \\ingroup EventGroup\n */\nstruct EventGroupDef_t;\ntypedef struct EventGroupDef_t   * EventGroupHandle_t;\n\n/*\n * The type that holds event bits always matches TickType_t - therefore the\n * number of bits it holds is set by configUSE_16_BIT_TICKS (16 bits if set to 1,\n * 32 bits if set to 0.\n *\n * \\defgroup EventBits_t EventBits_t\n * \\ingroup EventGroup\n */\ntypedef TickType_t               EventBits_t;\n\n/**\n * event_groups.h\n * @code{c}\n * EventGroupHandle_t xEventGroupCreate( void );\n * @endcode\n *\n * Create a new event group.\n *\n * Internally, within the FreeRTOS implementation, event groups use a [small]\n * block of memory, in which the event group's structure is stored.  If an event\n * groups is created using xEventGroupCreate() then the required memory is\n * automatically dynamically allocated inside the xEventGroupCreate() function.\n * (see https://www.FreeRTOS.org/a00111.html).  If an event group is created\n * using xEventGroupCreateStatic() then the application writer must instead\n * provide the memory that will get used by the event group.\n * xEventGroupCreateStatic() therefore allows an event group to be created\n * without using any dynamic memory allocation.\n *\n * Although event groups are not related to ticks, for internal implementation\n * reasons the number of bits available for use in an event group is dependent\n * on the configUSE_16_BIT_TICKS setting in FreeRTOSConfig.h.  If\n * configUSE_16_BIT_TICKS is 1 then each event group contains 8 usable bits (bit\n * 0 to bit 7).  If configUSE_16_BIT_TICKS is set to 0 then each event group has\n * 24 usable bits (bit 0 to bit 23).  The EventBits_t type is used to store\n * event bits within an event group.\n *\n * @return If the event group was created then a handle to the event group is\n * returned.  If there was insufficient FreeRTOS heap available to create the\n * event group then NULL is returned.  See https://www.FreeRTOS.org/a00111.html\n *\n * Example usage:\n * @code{c}\n *  // Declare a variable to hold the created event group.\n *  EventGroupHandle_t xCreatedEventGroup;\n *\n *  // Attempt to create the event group.\n *  xCreatedEventGroup = xEventGroupCreate();\n *\n *  // Was the event group created successfully?\n *  if( xCreatedEventGroup == NULL )\n *  {\n *      // The event group was not created because there was insufficient\n *      // FreeRTOS heap available.\n *  }\n *  else\n *  {\n *      // The event group was created.\n *  }\n * @endcode\n * \\defgroup xEventGroupCreate xEventGroupCreate\n * \\ingroup EventGroup\n */\n#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n    EventGroupHandle_t xEventGroupCreate( void ) PRIVILEGED_FUNCTION;\n#endif\n\n/**\n * event_groups.h\n * @code{c}\n * EventGroupHandle_t xEventGroupCreateStatic( EventGroupHandle_t * pxEventGroupBuffer );\n * @endcode\n *\n * Create a new event group.\n *\n * Internally, within the FreeRTOS implementation, event groups use a [small]\n * block of memory, in which the event group's structure is stored.  If an event\n * groups is created using xEventGroupCreate() then the required memory is\n * automatically dynamically allocated inside the xEventGroupCreate() function.\n * (see https://www.FreeRTOS.org/a00111.html).  If an event group is created\n * using xEventGroupCreateStatic() then the application writer must instead\n * provide the memory that will get used by the event group.\n * xEventGroupCreateStatic() therefore allows an event group to be created\n * without using any dynamic memory allocation.\n *\n * Although event groups are not related to ticks, for internal implementation\n * reasons the number of bits available for use in an event group is dependent\n * on the configUSE_16_BIT_TICKS setting in FreeRTOSConfig.h.  If\n * configUSE_16_BIT_TICKS is 1 then each event group contains 8 usable bits (bit\n * 0 to bit 7).  If configUSE_16_BIT_TICKS is set to 0 then each event group has\n * 24 usable bits (bit 0 to bit 23).  The EventBits_t type is used to store\n * event bits within an event group.\n *\n * @param pxEventGroupBuffer pxEventGroupBuffer must point to a variable of type\n * StaticEventGroup_t, which will be then be used to hold the event group's data\n * structures, removing the need for the memory to be allocated dynamically.\n *\n * @return If the event group was created then a handle to the event group is\n * returned.  If pxEventGroupBuffer was NULL then NULL is returned.\n *\n * Example usage:\n * @code{c}\n *  // StaticEventGroup_t is a publicly accessible structure that has the same\n *  // size and alignment requirements as the real event group structure.  It is\n *  // provided as a mechanism for applications to know the size of the event\n *  // group (which is dependent on the architecture and configuration file\n *  // settings) without breaking the strict data hiding policy by exposing the\n *  // real event group internals.  This StaticEventGroup_t variable is passed\n *  // into the xSemaphoreCreateEventGroupStatic() function and is used to store\n *  // the event group's data structures\n *  StaticEventGroup_t xEventGroupBuffer;\n *\n *  // Create the event group without dynamically allocating any memory.\n *  xEventGroup = xEventGroupCreateStatic( &xEventGroupBuffer );\n * @endcode\n */\n#if ( configSUPPORT_STATIC_ALLOCATION == 1 )\n    EventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t * pxEventGroupBuffer ) PRIVILEGED_FUNCTION;\n#endif\n\n/**\n * event_groups.h\n * @code{c}\n *  EventBits_t xEventGroupWaitBits(    EventGroupHandle_t xEventGroup,\n *                                      const EventBits_t uxBitsToWaitFor,\n *                                      const BaseType_t xClearOnExit,\n *                                      const BaseType_t xWaitForAllBits,\n *                                      const TickType_t xTicksToWait );\n * @endcode\n *\n * [Potentially] block to wait for one or more bits to be set within a\n * previously created event group.\n *\n * This function cannot be called from an interrupt.\n *\n * @param xEventGroup The event group in which the bits are being tested.  The\n * event group must have previously been created using a call to\n * xEventGroupCreate().\n *\n * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test\n * inside the event group.  For example, to wait for bit 0 and/or bit 2 set\n * uxBitsToWaitFor to 0x05.  To wait for bits 0 and/or bit 1 and/or bit 2 set\n * uxBitsToWaitFor to 0x07.  Etc.\n *\n * @param xClearOnExit If xClearOnExit is set to pdTRUE then any bits within\n * uxBitsToWaitFor that are set within the event group will be cleared before\n * xEventGroupWaitBits() returns if the wait condition was met (if the function\n * returns for a reason other than a timeout).  If xClearOnExit is set to\n * pdFALSE then the bits set in the event group are not altered when the call to\n * xEventGroupWaitBits() returns.\n *\n * @param xWaitForAllBits If xWaitForAllBits is set to pdTRUE then\n * xEventGroupWaitBits() will return when either all the bits in uxBitsToWaitFor\n * are set or the specified block time expires.  If xWaitForAllBits is set to\n * pdFALSE then xEventGroupWaitBits() will return when any one of the bits set\n * in uxBitsToWaitFor is set or the specified block time expires.  The block\n * time is specified by the xTicksToWait parameter.\n *\n * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait\n * for one/all (depending on the xWaitForAllBits value) of the bits specified by\n * uxBitsToWaitFor to become set. A value of portMAX_DELAY can be used to block\n * indefinitely (provided INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h).\n *\n * @return The value of the event group at the time either the bits being waited\n * for became set, or the block time expired.  Test the return value to know\n * which bits were set.  If xEventGroupWaitBits() returned because its timeout\n * expired then not all the bits being waited for will be set.  If\n * xEventGroupWaitBits() returned because the bits it was waiting for were set\n * then the returned value is the event group value before any bits were\n * automatically cleared in the case that xClearOnExit parameter was set to\n * pdTRUE.\n *\n * Example usage:\n * @code{c}\n * #define BIT_0 ( 1 << 0 )\n * #define BIT_4 ( 1 << 4 )\n *\n * void aFunction( EventGroupHandle_t xEventGroup )\n * {\n * EventBits_t uxBits;\n * const TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS;\n *\n *      // Wait a maximum of 100ms for either bit 0 or bit 4 to be set within\n *      // the event group.  Clear the bits before exiting.\n *      uxBits = xEventGroupWaitBits(\n *                  xEventGroup,    // The event group being tested.\n *                  BIT_0 | BIT_4,  // The bits within the event group to wait for.\n *                  pdTRUE,         // BIT_0 and BIT_4 should be cleared before returning.\n *                  pdFALSE,        // Don't wait for both bits, either bit will do.\n *                  xTicksToWait ); // Wait a maximum of 100ms for either bit to be set.\n *\n *      if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )\n *      {\n *          // xEventGroupWaitBits() returned because both bits were set.\n *      }\n *      else if( ( uxBits & BIT_0 ) != 0 )\n *      {\n *          // xEventGroupWaitBits() returned because just BIT_0 was set.\n *      }\n *      else if( ( uxBits & BIT_4 ) != 0 )\n *      {\n *          // xEventGroupWaitBits() returned because just BIT_4 was set.\n *      }\n *      else\n *      {\n *          // xEventGroupWaitBits() returned because xTicksToWait ticks passed\n *          // without either BIT_0 or BIT_4 becoming set.\n *      }\n * }\n * @endcode\n * \\defgroup xEventGroupWaitBits xEventGroupWaitBits\n * \\ingroup EventGroup\n */\nEventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup,\n                                 const EventBits_t uxBitsToWaitFor,\n                                 const BaseType_t xClearOnExit,\n                                 const BaseType_t xWaitForAllBits,\n                                 TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;\n\n/**\n * event_groups.h\n * @code{c}\n *  EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear );\n * @endcode\n *\n * Clear bits within an event group.  This function cannot be called from an\n * interrupt.\n *\n * @param xEventGroup The event group in which the bits are to be cleared.\n *\n * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear\n * in the event group.  For example, to clear bit 3 only, set uxBitsToClear to\n * 0x08.  To clear bit 3 and bit 0 set uxBitsToClear to 0x09.\n *\n * @return The value of the event group before the specified bits were cleared.\n *\n * Example usage:\n * @code{c}\n * #define BIT_0 ( 1 << 0 )\n * #define BIT_4 ( 1 << 4 )\n *\n * void aFunction( EventGroupHandle_t xEventGroup )\n * {\n * EventBits_t uxBits;\n *\n *      // Clear bit 0 and bit 4 in xEventGroup.\n *      uxBits = xEventGroupClearBits(\n *                              xEventGroup,    // The event group being updated.\n *                              BIT_0 | BIT_4 );// The bits being cleared.\n *\n *      if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )\n *      {\n *          // Both bit 0 and bit 4 were set before xEventGroupClearBits() was\n *          // called.  Both will now be clear (not set).\n *      }\n *      else if( ( uxBits & BIT_0 ) != 0 )\n *      {\n *          // Bit 0 was set before xEventGroupClearBits() was called.  It will\n *          // now be clear.\n *      }\n *      else if( ( uxBits & BIT_4 ) != 0 )\n *      {\n *          // Bit 4 was set before xEventGroupClearBits() was called.  It will\n *          // now be clear.\n *      }\n *      else\n *      {\n *          // Neither bit 0 nor bit 4 were set in the first place.\n *      }\n * }\n * @endcode\n * \\defgroup xEventGroupClearBits xEventGroupClearBits\n * \\ingroup EventGroup\n */\nEventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup,\n                                  const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION;\n\n/**\n * event_groups.h\n * @code{c}\n *  BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );\n * @endcode\n *\n * A version of xEventGroupClearBits() that can be called from an interrupt.\n *\n * Setting bits in an event group is not a deterministic operation because there\n * are an unknown number of tasks that may be waiting for the bit or bits being\n * set.  FreeRTOS does not allow nondeterministic operations to be performed\n * while interrupts are disabled, so protects event groups that are accessed\n * from tasks by suspending the scheduler rather than disabling interrupts.  As\n * a result event groups cannot be accessed directly from an interrupt service\n * routine.  Therefore xEventGroupClearBitsFromISR() sends a message to the\n * timer task to have the clear operation performed in the context of the timer\n * task.\n *\n * @note If this function returns pdPASS then the timer task is ready to run\n * and a portYIELD_FROM_ISR(pdTRUE) should be executed to perform the needed\n * clear on the event group.  This behavior is different from\n * xEventGroupSetBitsFromISR because the parameter xHigherPriorityTaskWoken is\n * not present.\n *\n * @param xEventGroup The event group in which the bits are to be cleared.\n *\n * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear.\n * For example, to clear bit 3 only, set uxBitsToClear to 0x08.  To clear bit 3\n * and bit 0 set uxBitsToClear to 0x09.\n *\n * @return If the request to execute the function was posted successfully then\n * pdPASS is returned, otherwise pdFALSE is returned.  pdFALSE will be returned\n * if the timer service queue was full.\n *\n * Example usage:\n * @code{c}\n * #define BIT_0 ( 1 << 0 )\n * #define BIT_4 ( 1 << 4 )\n *\n * // An event group which it is assumed has already been created by a call to\n * // xEventGroupCreate().\n * EventGroupHandle_t xEventGroup;\n *\n * void anInterruptHandler( void )\n * {\n *      // Clear bit 0 and bit 4 in xEventGroup.\n *      xResult = xEventGroupClearBitsFromISR(\n *                          xEventGroup,     // The event group being updated.\n *                          BIT_0 | BIT_4 ); // The bits being set.\n *\n *      if( xResult == pdPASS )\n *      {\n *          // The message was posted successfully.\n *          portYIELD_FROM_ISR(pdTRUE);\n *      }\n * }\n * @endcode\n * \\defgroup xEventGroupClearBitsFromISR xEventGroupClearBitsFromISR\n * \\ingroup EventGroup\n */\n#if ( configUSE_TRACE_FACILITY == 1 )\n    BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup,\n                                            const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION;\n#else\n    #define xEventGroupClearBitsFromISR( xEventGroup, uxBitsToClear ) \\\n    xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) ( xEventGroup ), ( uint32_t ) ( uxBitsToClear ), NULL )\n#endif\n\n/**\n * event_groups.h\n * @code{c}\n *  EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );\n * @endcode\n *\n * Set bits within an event group.\n * This function cannot be called from an interrupt.  xEventGroupSetBitsFromISR()\n * is a version that can be called from an interrupt.\n *\n * Setting bits in an event group will automatically unblock tasks that are\n * blocked waiting for the bits.\n *\n * @param xEventGroup The event group in which the bits are to be set.\n *\n * @param uxBitsToSet A bitwise value that indicates the bit or bits to set.\n * For example, to set bit 3 only, set uxBitsToSet to 0x08.  To set bit 3\n * and bit 0 set uxBitsToSet to 0x09.\n *\n * @return The value of the event group at the time the call to\n * xEventGroupSetBits() returns.  There are two reasons why the returned value\n * might have the bits specified by the uxBitsToSet parameter cleared.  First,\n * if setting a bit results in a task that was waiting for the bit leaving the\n * blocked state then it is possible the bit will be cleared automatically\n * (see the xClearBitOnExit parameter of xEventGroupWaitBits()).  Second, any\n * unblocked (or otherwise Ready state) task that has a priority above that of\n * the task that called xEventGroupSetBits() will execute and may change the\n * event group value before the call to xEventGroupSetBits() returns.\n *\n * Example usage:\n * @code{c}\n * #define BIT_0 ( 1 << 0 )\n * #define BIT_4 ( 1 << 4 )\n *\n * void aFunction( EventGroupHandle_t xEventGroup )\n * {\n * EventBits_t uxBits;\n *\n *      // Set bit 0 and bit 4 in xEventGroup.\n *      uxBits = xEventGroupSetBits(\n *                          xEventGroup,    // The event group being updated.\n *                          BIT_0 | BIT_4 );// The bits being set.\n *\n *      if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )\n *      {\n *          // Both bit 0 and bit 4 remained set when the function returned.\n *      }\n *      else if( ( uxBits & BIT_0 ) != 0 )\n *      {\n *          // Bit 0 remained set when the function returned, but bit 4 was\n *          // cleared.  It might be that bit 4 was cleared automatically as a\n *          // task that was waiting for bit 4 was removed from the Blocked\n *          // state.\n *      }\n *      else if( ( uxBits & BIT_4 ) != 0 )\n *      {\n *          // Bit 4 remained set when the function returned, but bit 0 was\n *          // cleared.  It might be that bit 0 was cleared automatically as a\n *          // task that was waiting for bit 0 was removed from the Blocked\n *          // state.\n *      }\n *      else\n *      {\n *          // Neither bit 0 nor bit 4 remained set.  It might be that a task\n *          // was waiting for both of the bits to be set, and the bits were\n *          // cleared as the task left the Blocked state.\n *      }\n * }\n * @endcode\n * \\defgroup xEventGroupSetBits xEventGroupSetBits\n * \\ingroup EventGroup\n */\nEventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup,\n                                const EventBits_t uxBitsToSet ) PRIVILEGED_FUNCTION;\n\n/**\n * event_groups.h\n * @code{c}\n *  BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken );\n * @endcode\n *\n * A version of xEventGroupSetBits() that can be called from an interrupt.\n *\n * Setting bits in an event group is not a deterministic operation because there\n * are an unknown number of tasks that may be waiting for the bit or bits being\n * set.  FreeRTOS does not allow nondeterministic operations to be performed in\n * interrupts or from critical sections.  Therefore xEventGroupSetBitsFromISR()\n * sends a message to the timer task to have the set operation performed in the\n * context of the timer task - where a scheduler lock is used in place of a\n * critical section.\n *\n * @param xEventGroup The event group in which the bits are to be set.\n *\n * @param uxBitsToSet A bitwise value that indicates the bit or bits to set.\n * For example, to set bit 3 only, set uxBitsToSet to 0x08.  To set bit 3\n * and bit 0 set uxBitsToSet to 0x09.\n *\n * @param pxHigherPriorityTaskWoken As mentioned above, calling this function\n * will result in a message being sent to the timer daemon task.  If the\n * priority of the timer daemon task is higher than the priority of the\n * currently running task (the task the interrupt interrupted) then\n * *pxHigherPriorityTaskWoken will be set to pdTRUE by\n * xEventGroupSetBitsFromISR(), indicating that a context switch should be\n * requested before the interrupt exits.  For that reason\n * *pxHigherPriorityTaskWoken must be initialised to pdFALSE.  See the\n * example code below.\n *\n * @return If the request to execute the function was posted successfully then\n * pdPASS is returned, otherwise pdFALSE is returned.  pdFALSE will be returned\n * if the timer service queue was full.\n *\n * Example usage:\n * @code{c}\n * #define BIT_0 ( 1 << 0 )\n * #define BIT_4 ( 1 << 4 )\n *\n * // An event group which it is assumed has already been created by a call to\n * // xEventGroupCreate().\n * EventGroupHandle_t xEventGroup;\n *\n * void anInterruptHandler( void )\n * {\n * BaseType_t xHigherPriorityTaskWoken, xResult;\n *\n *      // xHigherPriorityTaskWoken must be initialised to pdFALSE.\n *      xHigherPriorityTaskWoken = pdFALSE;\n *\n *      // Set bit 0 and bit 4 in xEventGroup.\n *      xResult = xEventGroupSetBitsFromISR(\n *                          xEventGroup,    // The event group being updated.\n *                          BIT_0 | BIT_4   // The bits being set.\n *                          &xHigherPriorityTaskWoken );\n *\n *      // Was the message posted successfully?\n *      if( xResult == pdPASS )\n *      {\n *          // If xHigherPriorityTaskWoken is now set to pdTRUE then a context\n *          // switch should be requested.  The macro used is port specific and\n *          // will be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() -\n *          // refer to the documentation page for the port being used.\n *          portYIELD_FROM_ISR( xHigherPriorityTaskWoken );\n *      }\n * }\n * @endcode\n * \\defgroup xEventGroupSetBitsFromISR xEventGroupSetBitsFromISR\n * \\ingroup EventGroup\n */\n#if ( configUSE_TRACE_FACILITY == 1 )\n    BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup,\n                                          const EventBits_t uxBitsToSet,\n                                          BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;\n#else\n    #define xEventGroupSetBitsFromISR( xEventGroup, uxBitsToSet, pxHigherPriorityTaskWoken ) \\\n    xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) ( xEventGroup ), ( uint32_t ) ( uxBitsToSet ), ( pxHigherPriorityTaskWoken ) )\n#endif\n\n/**\n * event_groups.h\n * @code{c}\n *  EventBits_t xEventGroupSync(    EventGroupHandle_t xEventGroup,\n *                                  const EventBits_t uxBitsToSet,\n *                                  const EventBits_t uxBitsToWaitFor,\n *                                  TickType_t xTicksToWait );\n * @endcode\n *\n * Atomically set bits within an event group, then wait for a combination of\n * bits to be set within the same event group.  This functionality is typically\n * used to synchronise multiple tasks, where each task has to wait for the other\n * tasks to reach a synchronisation point before proceeding.\n *\n * This function cannot be used from an interrupt.\n *\n * The function will return before its block time expires if the bits specified\n * by the uxBitsToWait parameter are set, or become set within that time.  In\n * this case all the bits specified by uxBitsToWait will be automatically\n * cleared before the function returns.\n *\n * @param xEventGroup The event group in which the bits are being tested.  The\n * event group must have previously been created using a call to\n * xEventGroupCreate().\n *\n * @param uxBitsToSet The bits to set in the event group before determining\n * if, and possibly waiting for, all the bits specified by the uxBitsToWait\n * parameter are set.\n *\n * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test\n * inside the event group.  For example, to wait for bit 0 and bit 2 set\n * uxBitsToWaitFor to 0x05.  To wait for bits 0 and bit 1 and bit 2 set\n * uxBitsToWaitFor to 0x07.  Etc.\n *\n * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait\n * for all of the bits specified by uxBitsToWaitFor to become set.\n *\n * @return The value of the event group at the time either the bits being waited\n * for became set, or the block time expired.  Test the return value to know\n * which bits were set.  If xEventGroupSync() returned because its timeout\n * expired then not all the bits being waited for will be set.  If\n * xEventGroupSync() returned because all the bits it was waiting for were\n * set then the returned value is the event group value before any bits were\n * automatically cleared.\n *\n * Example usage:\n * @code{c}\n * // Bits used by the three tasks.\n * #define TASK_0_BIT     ( 1 << 0 )\n * #define TASK_1_BIT     ( 1 << 1 )\n * #define TASK_2_BIT     ( 1 << 2 )\n *\n * #define ALL_SYNC_BITS ( TASK_0_BIT | TASK_1_BIT | TASK_2_BIT )\n *\n * // Use an event group to synchronise three tasks.  It is assumed this event\n * // group has already been created elsewhere.\n * EventGroupHandle_t xEventBits;\n *\n * void vTask0( void *pvParameters )\n * {\n * EventBits_t uxReturn;\n * TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS;\n *\n *   for( ;; )\n *   {\n *      // Perform task functionality here.\n *\n *      // Set bit 0 in the event flag to note this task has reached the\n *      // sync point.  The other two tasks will set the other two bits defined\n *      // by ALL_SYNC_BITS.  All three tasks have reached the synchronisation\n *      // point when all the ALL_SYNC_BITS are set.  Wait a maximum of 100ms\n *      // for this to happen.\n *      uxReturn = xEventGroupSync( xEventBits, TASK_0_BIT, ALL_SYNC_BITS, xTicksToWait );\n *\n *      if( ( uxReturn & ALL_SYNC_BITS ) == ALL_SYNC_BITS )\n *      {\n *          // All three tasks reached the synchronisation point before the call\n *          // to xEventGroupSync() timed out.\n *      }\n *  }\n * }\n *\n * void vTask1( void *pvParameters )\n * {\n *   for( ;; )\n *   {\n *      // Perform task functionality here.\n *\n *      // Set bit 1 in the event flag to note this task has reached the\n *      // synchronisation point.  The other two tasks will set the other two\n *      // bits defined by ALL_SYNC_BITS.  All three tasks have reached the\n *      // synchronisation point when all the ALL_SYNC_BITS are set.  Wait\n *      // indefinitely for this to happen.\n *      xEventGroupSync( xEventBits, TASK_1_BIT, ALL_SYNC_BITS, portMAX_DELAY );\n *\n *      // xEventGroupSync() was called with an indefinite block time, so\n *      // this task will only reach here if the synchronisation was made by all\n *      // three tasks, so there is no need to test the return value.\n *   }\n * }\n *\n * void vTask2( void *pvParameters )\n * {\n *   for( ;; )\n *   {\n *      // Perform task functionality here.\n *\n *      // Set bit 2 in the event flag to note this task has reached the\n *      // synchronisation point.  The other two tasks will set the other two\n *      // bits defined by ALL_SYNC_BITS.  All three tasks have reached the\n *      // synchronisation point when all the ALL_SYNC_BITS are set.  Wait\n *      // indefinitely for this to happen.\n *      xEventGroupSync( xEventBits, TASK_2_BIT, ALL_SYNC_BITS, portMAX_DELAY );\n *\n *      // xEventGroupSync() was called with an indefinite block time, so\n *      // this task will only reach here if the synchronisation was made by all\n *      // three tasks, so there is no need to test the return value.\n *  }\n * }\n *\n * @endcode\n * \\defgroup xEventGroupSync xEventGroupSync\n * \\ingroup EventGroup\n */\nEventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup,\n                             const EventBits_t uxBitsToSet,\n                             const EventBits_t uxBitsToWaitFor,\n                             TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;\n\n\n/**\n * event_groups.h\n * @code{c}\n *  EventBits_t xEventGroupGetBits( EventGroupHandle_t xEventGroup );\n * @endcode\n *\n * Returns the current value of the bits in an event group.  This function\n * cannot be used from an interrupt.\n *\n * @param xEventGroup The event group being queried.\n *\n * @return The event group bits at the time xEventGroupGetBits() was called.\n *\n * \\defgroup xEventGroupGetBits xEventGroupGetBits\n * \\ingroup EventGroup\n */\n#define xEventGroupGetBits( xEventGroup )    xEventGroupClearBits( ( xEventGroup ), 0 )\n\n/**\n * event_groups.h\n * @code{c}\n *  EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup );\n * @endcode\n *\n * A version of xEventGroupGetBits() that can be called from an ISR.\n *\n * @param xEventGroup The event group being queried.\n *\n * @return The event group bits at the time xEventGroupGetBitsFromISR() was called.\n *\n * \\defgroup xEventGroupGetBitsFromISR xEventGroupGetBitsFromISR\n * \\ingroup EventGroup\n */\nEventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION;\n\n/**\n * event_groups.h\n * @code{c}\n *  void xEventGroupDelete( EventGroupHandle_t xEventGroup );\n * @endcode\n *\n * Delete an event group that was previously created by a call to\n * xEventGroupCreate().  Tasks that are blocked on the event group will be\n * unblocked and obtain 0 as the event group's value.\n *\n * @param xEventGroup The event group being deleted.\n */\nvoid vEventGroupDelete( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION;\n\n/* For internal use only. */\nvoid vEventGroupSetBitsCallback( void * pvEventGroup,\n                                 const uint32_t ulBitsToSet ) PRIVILEGED_FUNCTION;\nvoid vEventGroupClearBitsCallback( void * pvEventGroup,\n                                   const uint32_t ulBitsToClear ) PRIVILEGED_FUNCTION;\n\n\n#if ( configUSE_TRACE_FACILITY == 1 )\n    UBaseType_t uxEventGroupGetNumber( void * xEventGroup ) PRIVILEGED_FUNCTION;\n    void vEventGroupSetNumber( void * xEventGroup,\n                               UBaseType_t uxEventGroupNumber ) PRIVILEGED_FUNCTION;\n#endif\n\n/* *INDENT-OFF* */\n#ifdef __cplusplus\n    }\n#endif\n/* *INDENT-ON* */\n\n#endif /* EVENT_GROUPS_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/include/list.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/*\n * This is the list implementation used by the scheduler.  While it is tailored\n * heavily for the schedulers needs, it is also available for use by\n * application code.\n *\n * list_ts can only store pointers to list_item_ts.  Each ListItem_t contains a\n * numeric value (xItemValue).  Most of the time the lists are sorted in\n * ascending item value order.\n *\n * Lists are created already containing one list item.  The value of this\n * item is the maximum possible that can be stored, it is therefore always at\n * the end of the list and acts as a marker.  The list member pxHead always\n * points to this marker - even though it is at the tail of the list.  This\n * is because the tail contains a wrap back pointer to the true head of\n * the list.\n *\n * In addition to it's value, each list item contains a pointer to the next\n * item in the list (pxNext), a pointer to the list it is in (pxContainer)\n * and a pointer to back to the object that contains it.  These later two\n * pointers are included for efficiency of list manipulation.  There is\n * effectively a two way link between the object containing the list item and\n * the list item itself.\n *\n *\n * \\page ListIntroduction List Implementation\n * \\ingroup FreeRTOSIntro\n */\n\n\n#ifndef LIST_H\n#define LIST_H\n\n#ifndef INC_FREERTOS_H\n    #error \"FreeRTOS.h must be included before list.h\"\n#endif\n\n/*\n * The list structure members are modified from within interrupts, and therefore\n * by rights should be declared volatile.  However, they are only modified in a\n * functionally atomic way (within critical sections of with the scheduler\n * suspended) and are either passed by reference into a function or indexed via\n * a volatile variable.  Therefore, in all use cases tested so far, the volatile\n * qualifier can be omitted in order to provide a moderate performance\n * improvement without adversely affecting functional behaviour.  The assembly\n * instructions generated by the IAR, ARM and GCC compilers when the respective\n * compiler's options were set for maximum optimisation has been inspected and\n * deemed to be as intended.  That said, as compiler technology advances, and\n * especially if aggressive cross module optimisation is used (a use case that\n * has not been exercised to any great extend) then it is feasible that the\n * volatile qualifier will be needed for correct optimisation.  It is expected\n * that a compiler removing essential code because, without the volatile\n * qualifier on the list structure members and with aggressive cross module\n * optimisation, the compiler deemed the code unnecessary will result in\n * complete and obvious failure of the scheduler.  If this is ever experienced\n * then the volatile qualifier can be inserted in the relevant places within the\n * list structures by simply defining configLIST_VOLATILE to volatile in\n * FreeRTOSConfig.h (as per the example at the bottom of this comment block).\n * If configLIST_VOLATILE is not defined then the preprocessor directives below\n * will simply #define configLIST_VOLATILE away completely.\n *\n * To use volatile list structure members then add the following line to\n * FreeRTOSConfig.h (without the quotes):\n * \"#define configLIST_VOLATILE volatile\"\n */\n#ifndef configLIST_VOLATILE\n    #define configLIST_VOLATILE\n#endif /* configSUPPORT_CROSS_MODULE_OPTIMISATION */\n\n/* *INDENT-OFF* */\n#ifdef __cplusplus\n    extern \"C\" {\n#endif\n/* *INDENT-ON* */\n\n/* Macros that can be used to place known values within the list structures,\n * then check that the known values do not get corrupted during the execution of\n * the application.   These may catch the list data structures being overwritten in\n * memory.  They will not catch data errors caused by incorrect configuration or\n * use of FreeRTOS.*/\n#if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 0 )\n    /* Define the macros to do nothing. */\n    #define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE\n    #define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE\n    #define listFIRST_LIST_INTEGRITY_CHECK_VALUE\n    #define listSECOND_LIST_INTEGRITY_CHECK_VALUE\n    #define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )\n    #define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )\n    #define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList )\n    #define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList )\n    #define listTEST_LIST_ITEM_INTEGRITY( pxItem )\n    #define listTEST_LIST_INTEGRITY( pxList )\n#else /* if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 0 ) */\n    /* Define macros that add new members into the list structures. */\n    #define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE     TickType_t xListItemIntegrityValue1;\n    #define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE    TickType_t xListItemIntegrityValue2;\n    #define listFIRST_LIST_INTEGRITY_CHECK_VALUE          TickType_t xListIntegrityValue1;\n    #define listSECOND_LIST_INTEGRITY_CHECK_VALUE         TickType_t xListIntegrityValue2;\n\n/* Define macros that set the new structure members to known values. */\n    #define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )     ( pxItem )->xListItemIntegrityValue1 = pdINTEGRITY_CHECK_VALUE\n    #define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )    ( pxItem )->xListItemIntegrityValue2 = pdINTEGRITY_CHECK_VALUE\n    #define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList )              ( pxList )->xListIntegrityValue1 = pdINTEGRITY_CHECK_VALUE\n    #define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList )              ( pxList )->xListIntegrityValue2 = pdINTEGRITY_CHECK_VALUE\n\n/* Define macros that will assert if one of the structure members does not\n * contain its expected value. */\n    #define listTEST_LIST_ITEM_INTEGRITY( pxItem )                      configASSERT( ( ( pxItem )->xListItemIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxItem )->xListItemIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) )\n    #define listTEST_LIST_INTEGRITY( pxList )                           configASSERT( ( ( pxList )->xListIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxList )->xListIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) )\n#endif /* configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES */\n\n\n/*\n * Definition of the only type of object that a list can contain.\n */\nstruct xLIST;\nstruct xLIST_ITEM\n{\n    listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE           /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */\n    configLIST_VOLATILE TickType_t xItemValue;          /*< The value being listed.  In most cases this is used to sort the list in ascending order. */\n    struct xLIST_ITEM * configLIST_VOLATILE pxNext;     /*< Pointer to the next ListItem_t in the list. */\n    struct xLIST_ITEM * configLIST_VOLATILE pxPrevious; /*< Pointer to the previous ListItem_t in the list. */\n    void * pvOwner;                                     /*< Pointer to the object (normally a TCB) that contains the list item.  There is therefore a two way link between the object containing the list item and the list item itself. */\n    struct xLIST * configLIST_VOLATILE pxContainer;     /*< Pointer to the list in which this list item is placed (if any). */\n    listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE          /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */\n};\ntypedef struct xLIST_ITEM ListItem_t;                   /* For some reason lint wants this as two separate definitions. */\n\n#if ( configUSE_MINI_LIST_ITEM == 1 )\n    struct xMINI_LIST_ITEM\n    {\n        listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */\n        configLIST_VOLATILE TickType_t xItemValue;\n        struct xLIST_ITEM * configLIST_VOLATILE pxNext;\n        struct xLIST_ITEM * configLIST_VOLATILE pxPrevious;\n    };\n    typedef struct xMINI_LIST_ITEM MiniListItem_t;\n#else\n    typedef struct xLIST_ITEM      MiniListItem_t;\n#endif\n\n/*\n * Definition of the type of queue used by the scheduler.\n */\ntypedef struct xLIST\n{\n    listFIRST_LIST_INTEGRITY_CHECK_VALUE      /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */\n    volatile UBaseType_t uxNumberOfItems;\n    ListItem_t * configLIST_VOLATILE pxIndex; /*< Used to walk through the list.  Points to the last item returned by a call to listGET_OWNER_OF_NEXT_ENTRY (). */\n    MiniListItem_t xListEnd;                  /*< List item that contains the maximum possible item value meaning it is always at the end of the list and is therefore used as a marker. */\n    listSECOND_LIST_INTEGRITY_CHECK_VALUE     /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */\n} List_t;\n\n/*\n * Access macro to set the owner of a list item.  The owner of a list item\n * is the object (usually a TCB) that contains the list item.\n *\n * \\page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER\n * \\ingroup LinkedList\n */\n#define listSET_LIST_ITEM_OWNER( pxListItem, pxOwner )    ( ( pxListItem )->pvOwner = ( void * ) ( pxOwner ) )\n\n/*\n * Access macro to get the owner of a list item.  The owner of a list item\n * is the object (usually a TCB) that contains the list item.\n *\n * \\page listGET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER\n * \\ingroup LinkedList\n */\n#define listGET_LIST_ITEM_OWNER( pxListItem )             ( ( pxListItem )->pvOwner )\n\n/*\n * Access macro to set the value of the list item.  In most cases the value is\n * used to sort the list in ascending order.\n *\n * \\page listSET_LIST_ITEM_VALUE listSET_LIST_ITEM_VALUE\n * \\ingroup LinkedList\n */\n#define listSET_LIST_ITEM_VALUE( pxListItem, xValue )     ( ( pxListItem )->xItemValue = ( xValue ) )\n\n/*\n * Access macro to retrieve the value of the list item.  The value can\n * represent anything - for example the priority of a task, or the time at\n * which a task should be unblocked.\n *\n * \\page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE\n * \\ingroup LinkedList\n */\n#define listGET_LIST_ITEM_VALUE( pxListItem )             ( ( pxListItem )->xItemValue )\n\n/*\n * Access macro to retrieve the value of the list item at the head of a given\n * list.\n *\n * \\page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE\n * \\ingroup LinkedList\n */\n#define listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxList )        ( ( ( pxList )->xListEnd ).pxNext->xItemValue )\n\n/*\n * Return the list item at the head of the list.\n *\n * \\page listGET_HEAD_ENTRY listGET_HEAD_ENTRY\n * \\ingroup LinkedList\n */\n#define listGET_HEAD_ENTRY( pxList )                      ( ( ( pxList )->xListEnd ).pxNext )\n\n/*\n * Return the next list item.\n *\n * \\page listGET_NEXT listGET_NEXT\n * \\ingroup LinkedList\n */\n#define listGET_NEXT( pxListItem )                        ( ( pxListItem )->pxNext )\n\n/*\n * Return the list item that marks the end of the list\n *\n * \\page listGET_END_MARKER listGET_END_MARKER\n * \\ingroup LinkedList\n */\n#define listGET_END_MARKER( pxList )                      ( ( ListItem_t const * ) ( &( ( pxList )->xListEnd ) ) )\n\n/*\n * Access macro to determine if a list contains any items.  The macro will\n * only have the value true if the list is empty.\n *\n * \\page listLIST_IS_EMPTY listLIST_IS_EMPTY\n * \\ingroup LinkedList\n */\n#define listLIST_IS_EMPTY( pxList )                       ( ( ( pxList )->uxNumberOfItems == ( UBaseType_t ) 0 ) ? pdTRUE : pdFALSE )\n\n/*\n * Access macro to return the number of items in the list.\n */\n#define listCURRENT_LIST_LENGTH( pxList )                 ( ( pxList )->uxNumberOfItems )\n\n/*\n * Access function to obtain the owner of the next entry in a list.\n *\n * The list member pxIndex is used to walk through a list.  Calling\n * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list\n * and returns that entry's pxOwner parameter.  Using multiple calls to this\n * function it is therefore possible to move through every item contained in\n * a list.\n *\n * The pxOwner parameter of a list item is a pointer to the object that owns\n * the list item.  In the scheduler this is normally a task control block.\n * The pxOwner parameter effectively creates a two way link between the list\n * item and its owner.\n *\n * @param pxTCB pxTCB is set to the address of the owner of the next list item.\n * @param pxList The list from which the next item owner is to be returned.\n *\n * \\page listGET_OWNER_OF_NEXT_ENTRY listGET_OWNER_OF_NEXT_ENTRY\n * \\ingroup LinkedList\n */\n#define listGET_OWNER_OF_NEXT_ENTRY( pxTCB, pxList )                                           \\\n    {                                                                                          \\\n        List_t * const pxConstList = ( pxList );                                               \\\n        /* Increment the index to the next item and return the item, ensuring */               \\\n        /* we don't return the marker used at the end of the list.  */                         \\\n        ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext;                           \\\n        if( ( void * ) ( pxConstList )->pxIndex == ( void * ) &( ( pxConstList )->xListEnd ) ) \\\n        {                                                                                      \\\n            ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext;                       \\\n        }                                                                                      \\\n        ( pxTCB ) = ( pxConstList )->pxIndex->pvOwner;                                         \\\n    }\n\n/*\n * Version of uxListRemove() that does not return a value.  Provided as a slight\n * optimisation for xTaskIncrementTick() by being inline.\n *\n * Remove an item from a list.  The list item has a pointer to the list that\n * it is in, so only the list item need be passed into the function.\n *\n * @param uxListRemove The item to be removed.  The item will remove itself from\n * the list pointed to by it's pxContainer parameter.\n *\n * @return The number of items that remain in the list after the list item has\n * been removed.\n *\n * \\page listREMOVE_ITEM listREMOVE_ITEM\n * \\ingroup LinkedList\n */\n#define listREMOVE_ITEM( pxItemToRemove ) \\\n    {                                     \\\n        /* The list item knows which list it is in.  Obtain the list from the list \\\n         * item. */                                                              \\\n        List_t * const pxList = ( pxItemToRemove )->pxContainer;                 \\\n                                                                                 \\\n        ( pxItemToRemove )->pxNext->pxPrevious = ( pxItemToRemove )->pxPrevious; \\\n        ( pxItemToRemove )->pxPrevious->pxNext = ( pxItemToRemove )->pxNext;     \\\n        /* Make sure the index is left pointing to a valid item. */              \\\n        if( pxList->pxIndex == ( pxItemToRemove ) )                              \\\n        {                                                                        \\\n            pxList->pxIndex = ( pxItemToRemove )->pxPrevious;                    \\\n        }                                                                        \\\n                                                                                 \\\n        ( pxItemToRemove )->pxContainer = NULL;                                  \\\n        ( pxList->uxNumberOfItems )--;                                           \\\n    }\n\n/*\n * Inline version of vListInsertEnd() to provide slight optimisation for\n * xTaskIncrementTick().\n *\n * Insert a list item into a list.  The item will be inserted in a position\n * such that it will be the last item within the list returned by multiple\n * calls to listGET_OWNER_OF_NEXT_ENTRY.\n *\n * The list member pxIndex is used to walk through a list.  Calling\n * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list.\n * Placing an item in a list using vListInsertEnd effectively places the item\n * in the list position pointed to by pxIndex.  This means that every other\n * item within the list will be returned by listGET_OWNER_OF_NEXT_ENTRY before\n * the pxIndex parameter again points to the item being inserted.\n *\n * @param pxList The list into which the item is to be inserted.\n *\n * @param pxNewListItem The list item to be inserted into the list.\n *\n * \\page listINSERT_END listINSERT_END\n * \\ingroup LinkedList\n */\n#define listINSERT_END( pxList, pxNewListItem )           \\\n    {                                                     \\\n        ListItem_t * const pxIndex = ( pxList )->pxIndex; \\\n                                                          \\\n        /* Only effective when configASSERT() is also defined, these tests may catch \\\n         * the list data structures being overwritten in memory.  They will not catch \\\n         * data errors caused by incorrect configuration or use of FreeRTOS. */ \\\n        listTEST_LIST_INTEGRITY( ( pxList ) );                                  \\\n        listTEST_LIST_ITEM_INTEGRITY( ( pxNewListItem ) );                      \\\n                                                                                \\\n        /* Insert a new list item into ( pxList ), but rather than sort the list, \\\n         * makes the new list item the last item to be removed by a call to \\\n         * listGET_OWNER_OF_NEXT_ENTRY(). */                 \\\n        ( pxNewListItem )->pxNext = pxIndex;                 \\\n        ( pxNewListItem )->pxPrevious = pxIndex->pxPrevious; \\\n                                                             \\\n        pxIndex->pxPrevious->pxNext = ( pxNewListItem );     \\\n        pxIndex->pxPrevious = ( pxNewListItem );             \\\n                                                             \\\n        /* Remember which list the item is in. */            \\\n        ( pxNewListItem )->pxContainer = ( pxList );         \\\n                                                             \\\n        ( ( pxList )->uxNumberOfItems )++;                   \\\n    }\n\n/*\n * Access function to obtain the owner of the first entry in a list.  Lists\n * are normally sorted in ascending item value order.\n *\n * This function returns the pxOwner member of the first item in the list.\n * The pxOwner parameter of a list item is a pointer to the object that owns\n * the list item.  In the scheduler this is normally a task control block.\n * The pxOwner parameter effectively creates a two way link between the list\n * item and its owner.\n *\n * @param pxList The list from which the owner of the head item is to be\n * returned.\n *\n * \\page listGET_OWNER_OF_HEAD_ENTRY listGET_OWNER_OF_HEAD_ENTRY\n * \\ingroup LinkedList\n */\n#define listGET_OWNER_OF_HEAD_ENTRY( pxList )            ( ( &( ( pxList )->xListEnd ) )->pxNext->pvOwner )\n\n/*\n * Check to see if a list item is within a list.  The list item maintains a\n * \"container\" pointer that points to the list it is in.  All this macro does\n * is check to see if the container and the list match.\n *\n * @param pxList The list we want to know if the list item is within.\n * @param pxListItem The list item we want to know if is in the list.\n * @return pdTRUE if the list item is in the list, otherwise pdFALSE.\n */\n#define listIS_CONTAINED_WITHIN( pxList, pxListItem )    ( ( ( pxListItem )->pxContainer == ( pxList ) ) ? ( pdTRUE ) : ( pdFALSE ) )\n\n/*\n * Return the list a list item is contained within (referenced from).\n *\n * @param pxListItem The list item being queried.\n * @return A pointer to the List_t object that references the pxListItem\n */\n#define listLIST_ITEM_CONTAINER( pxListItem )            ( ( pxListItem )->pxContainer )\n\n/*\n * This provides a crude means of knowing if a list has been initialised, as\n * pxList->xListEnd.xItemValue is set to portMAX_DELAY by the vListInitialise()\n * function.\n */\n#define listLIST_IS_INITIALISED( pxList )                ( ( pxList )->xListEnd.xItemValue == portMAX_DELAY )\n\n/*\n * Must be called before a list is used!  This initialises all the members\n * of the list structure and inserts the xListEnd item into the list as a\n * marker to the back of the list.\n *\n * @param pxList Pointer to the list being initialised.\n *\n * \\page vListInitialise vListInitialise\n * \\ingroup LinkedList\n */\nvoid vListInitialise( List_t * const pxList ) PRIVILEGED_FUNCTION;\n\n/*\n * Must be called before a list item is used.  This sets the list container to\n * null so the item does not think that it is already contained in a list.\n *\n * @param pxItem Pointer to the list item being initialised.\n *\n * \\page vListInitialiseItem vListInitialiseItem\n * \\ingroup LinkedList\n */\nvoid vListInitialiseItem( ListItem_t * const pxItem ) PRIVILEGED_FUNCTION;\n\n/*\n * Insert a list item into a list.  The item will be inserted into the list in\n * a position determined by its item value (ascending item value order).\n *\n * @param pxList The list into which the item is to be inserted.\n *\n * @param pxNewListItem The item that is to be placed in the list.\n *\n * \\page vListInsert vListInsert\n * \\ingroup LinkedList\n */\nvoid vListInsert( List_t * const pxList,\n                  ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION;\n\n/*\n * Insert a list item into a list.  The item will be inserted in a position\n * such that it will be the last item within the list returned by multiple\n * calls to listGET_OWNER_OF_NEXT_ENTRY.\n *\n * The list member pxIndex is used to walk through a list.  Calling\n * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list.\n * Placing an item in a list using vListInsertEnd effectively places the item\n * in the list position pointed to by pxIndex.  This means that every other\n * item within the list will be returned by listGET_OWNER_OF_NEXT_ENTRY before\n * the pxIndex parameter again points to the item being inserted.\n *\n * @param pxList The list into which the item is to be inserted.\n *\n * @param pxNewListItem The list item to be inserted into the list.\n *\n * \\page vListInsertEnd vListInsertEnd\n * \\ingroup LinkedList\n */\nvoid vListInsertEnd( List_t * const pxList,\n                     ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION;\n\n/*\n * Remove an item from a list.  The list item has a pointer to the list that\n * it is in, so only the list item need be passed into the function.\n *\n * @param uxListRemove The item to be removed.  The item will remove itself from\n * the list pointed to by it's pxContainer parameter.\n *\n * @return The number of items that remain in the list after the list item has\n * been removed.\n *\n * \\page uxListRemove uxListRemove\n * \\ingroup LinkedList\n */\nUBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) PRIVILEGED_FUNCTION;\n\n/* *INDENT-OFF* */\n#ifdef __cplusplus\n    }\n#endif\n/* *INDENT-ON* */\n\n#endif /* ifndef LIST_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/include/message_buffer.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n\n/*\n * Message buffers build functionality on top of FreeRTOS stream buffers.\n * Whereas stream buffers are used to send a continuous stream of data from one\n * task or interrupt to another, message buffers are used to send variable\n * length discrete messages from one task or interrupt to another.  Their\n * implementation is light weight, making them particularly suited for interrupt\n * to task and core to core communication scenarios.\n *\n * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer\n * implementation (so also the message buffer implementation, as message buffers\n * are built on top of stream buffers) assumes there is only one task or\n * interrupt that will write to the buffer (the writer), and only one task or\n * interrupt that will read from the buffer (the reader).  It is safe for the\n * writer and reader to be different tasks or interrupts, but, unlike other\n * FreeRTOS objects, it is not safe to have multiple different writers or\n * multiple different readers.  If there are to be multiple different writers\n * then the application writer must place each call to a writing API function\n * (such as xMessageBufferSend()) inside a critical section and set the send\n * block time to 0.  Likewise, if there are to be multiple different readers\n * then the application writer must place each call to a reading API function\n * (such as xMessageBufferRead()) inside a critical section and set the receive\n * timeout to 0.\n *\n * Message buffers hold variable length messages.  To enable that, when a\n * message is written to the message buffer an additional sizeof( size_t ) bytes\n * are also written to store the message's length (that happens internally, with\n * the API function).  sizeof( size_t ) is typically 4 bytes on a 32-bit\n * architecture, so writing a 10 byte message to a message buffer on a 32-bit\n * architecture will actually reduce the available space in the message buffer\n * by 14 bytes (10 byte are used by the message, and 4 bytes to hold the length\n * of the message).\n */\n\n#ifndef FREERTOS_MESSAGE_BUFFER_H\n#define FREERTOS_MESSAGE_BUFFER_H\n\n#ifndef INC_FREERTOS_H\n    #error \"include FreeRTOS.h must appear in source files before include message_buffer.h\"\n#endif\n\n/* Message buffers are built onto of stream buffers. */\n#include \"stream_buffer.h\"\n\n/* *INDENT-OFF* */\n#if defined( __cplusplus )\n    extern \"C\" {\n#endif\n/* *INDENT-ON* */\n\n/**\n * Type by which message buffers are referenced.  For example, a call to\n * xMessageBufferCreate() returns an MessageBufferHandle_t variable that can\n * then be used as a parameter to xMessageBufferSend(), xMessageBufferReceive(),\n * etc. Message buffer is essentially built as a stream buffer hence its handle\n * is also set to same type as a stream buffer handle.\n */\ntypedef StreamBufferHandle_t MessageBufferHandle_t;\n\n/*-----------------------------------------------------------*/\n\n/**\n * message_buffer.h\n *\n * @code{c}\n * MessageBufferHandle_t xMessageBufferCreate( size_t xBufferSizeBytes );\n * @endcode\n *\n * Creates a new message buffer using dynamically allocated memory.  See\n * xMessageBufferCreateStatic() for a version that uses statically allocated\n * memory (memory that is allocated at compile time).\n *\n * configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in\n * FreeRTOSConfig.h for xMessageBufferCreate() to be available.\n *\n * @param xBufferSizeBytes The total number of bytes (not messages) the message\n * buffer will be able to hold at any one time.  When a message is written to\n * the message buffer an additional sizeof( size_t ) bytes are also written to\n * store the message's length.  sizeof( size_t ) is typically 4 bytes on a\n * 32-bit architecture, so on most 32-bit architectures a 10 byte message will\n * take up 14 bytes of message buffer space.\n *\n * @param pxSendCompletedCallback Callback invoked when a send operation to the\n * message buffer is complete. If the parameter is NULL or xMessageBufferCreate()\n * is called without the parameter, then it will use the default implementation\n * provided by sbSEND_COMPLETED macro. To enable the callback,\n * configUSE_SB_COMPLETED_CALLBACK must be set to 1 in FreeRTOSConfig.h.\n *\n * @param pxReceiveCompletedCallback Callback invoked when a receive operation from\n * the message buffer is complete. If the parameter is NULL or xMessageBufferCreate()\n * is called without the parameter, it will use the default implementation provided\n * by sbRECEIVE_COMPLETED macro. To enable the callback,\n * configUSE_SB_COMPLETED_CALLBACK must be set to 1 in FreeRTOSConfig.h.\n *\n * @return If NULL is returned, then the message buffer cannot be created\n * because there is insufficient heap memory available for FreeRTOS to allocate\n * the message buffer data structures and storage area.  A non-NULL value being\n * returned indicates that the message buffer has been created successfully -\n * the returned value should be stored as the handle to the created message\n * buffer.\n *\n * Example use:\n * @code{c}\n *\n * void vAFunction( void )\n * {\n * MessageBufferHandle_t xMessageBuffer;\n * const size_t xMessageBufferSizeBytes = 100;\n *\n *  // Create a message buffer that can hold 100 bytes.  The memory used to hold\n *  // both the message buffer structure and the messages themselves is allocated\n *  // dynamically.  Each message added to the buffer consumes an additional 4\n *  // bytes which are used to hold the length of the message.\n *  xMessageBuffer = xMessageBufferCreate( xMessageBufferSizeBytes );\n *\n *  if( xMessageBuffer == NULL )\n *  {\n *      // There was not enough heap memory space available to create the\n *      // message buffer.\n *  }\n *  else\n *  {\n *      // The message buffer was created successfully and can now be used.\n *  }\n *\n * @endcode\n * \\defgroup xMessageBufferCreate xMessageBufferCreate\n * \\ingroup MessageBufferManagement\n */\n#define xMessageBufferCreate( xBufferSizeBytes ) \\\n    xStreamBufferGenericCreate( ( xBufferSizeBytes ), ( size_t ) 0, pdTRUE, NULL, NULL )\n\n#if ( configUSE_SB_COMPLETED_CALLBACK == 1 )\n    #define xMessageBufferCreateWithCallback( xBufferSizeBytes, pxSendCompletedCallback, pxReceiveCompletedCallback ) \\\n    xStreamBufferGenericCreate( ( xBufferSizeBytes ), ( size_t ) 0, pdTRUE, ( pxSendCompletedCallback ), ( pxReceiveCompletedCallback ) )\n#endif\n\n/**\n * message_buffer.h\n *\n * @code{c}\n * MessageBufferHandle_t xMessageBufferCreateStatic( size_t xBufferSizeBytes,\n *                                                uint8_t *pucMessageBufferStorageArea,\n *                                                StaticMessageBuffer_t *pxStaticMessageBuffer );\n * @endcode\n * Creates a new message buffer using statically allocated memory.  See\n * xMessageBufferCreate() for a version that uses dynamically allocated memory.\n *\n * @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the\n * pucMessageBufferStorageArea parameter.  When a message is written to the\n * message buffer an additional sizeof( size_t ) bytes are also written to store\n * the message's length.  sizeof( size_t ) is typically 4 bytes on a 32-bit\n * architecture, so on most 32-bit architecture a 10 byte message will take up\n * 14 bytes of message buffer space.  The maximum number of bytes that can be\n * stored in the message buffer is actually (xBufferSizeBytes - 1).\n *\n * @param pucMessageBufferStorageArea Must point to a uint8_t array that is at\n * least xBufferSizeBytes big.  This is the array to which messages are\n * copied when they are written to the message buffer.\n *\n * @param pxStaticMessageBuffer Must point to a variable of type\n * StaticMessageBuffer_t, which will be used to hold the message buffer's data\n * structure.\n *\n * @param pxSendCompletedCallback Callback invoked when a new message is sent to the message buffer.\n * If the parameter is NULL or xMessageBufferCreate() is called without the parameter, then it will use the default\n * implementation provided by sbSEND_COMPLETED macro. To enable the callback,\n * configUSE_SB_COMPLETED_CALLBACK must be set to 1 in FreeRTOSConfig.h.\n *\n * @param pxReceiveCompletedCallback Callback invoked when a message is read from a\n * message buffer. If the parameter is NULL or xMessageBufferCreate() is called without the parameter, it will\n * use the default implementation provided by sbRECEIVE_COMPLETED macro. To enable the callback,\n * configUSE_SB_COMPLETED_CALLBACK must be set to 1 in FreeRTOSConfig.h.\n *\n * @return If the message buffer is created successfully then a handle to the\n * created message buffer is returned. If either pucMessageBufferStorageArea or\n * pxStaticmessageBuffer are NULL then NULL is returned.\n *\n * Example use:\n * @code{c}\n *\n * // Used to dimension the array used to hold the messages.  The available space\n * // will actually be one less than this, so 999.\n #define STORAGE_SIZE_BYTES 1000\n *\n * // Defines the memory that will actually hold the messages within the message\n * // buffer.\n * static uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ];\n *\n * // The variable used to hold the message buffer structure.\n * StaticMessageBuffer_t xMessageBufferStruct;\n *\n * void MyFunction( void )\n * {\n * MessageBufferHandle_t xMessageBuffer;\n *\n *  xMessageBuffer = xMessageBufferCreateStatic( sizeof( ucStorageBuffer ),\n *                                               ucStorageBuffer,\n *                                               &xMessageBufferStruct );\n *\n *  // As neither the pucMessageBufferStorageArea or pxStaticMessageBuffer\n *  // parameters were NULL, xMessageBuffer will not be NULL, and can be used to\n *  // reference the created message buffer in other message buffer API calls.\n *\n *  // Other code that uses the message buffer can go here.\n * }\n *\n * @endcode\n * \\defgroup xMessageBufferCreateStatic xMessageBufferCreateStatic\n * \\ingroup MessageBufferManagement\n */\n#define xMessageBufferCreateStatic( xBufferSizeBytes, pucMessageBufferStorageArea, pxStaticMessageBuffer ) \\\n    xStreamBufferGenericCreateStatic( ( xBufferSizeBytes ), 0, pdTRUE, ( pucMessageBufferStorageArea ), ( pxStaticMessageBuffer ), NULL, NULL )\n\n#if ( configUSE_SB_COMPLETED_CALLBACK == 1 )\n    #define xMessageBufferCreateStaticWithCallback( xBufferSizeBytes, pucMessageBufferStorageArea, pxStaticMessageBuffer, pxSendCompletedCallback, pxReceiveCompletedCallback ) \\\n    xStreamBufferGenericCreateStatic( ( xBufferSizeBytes ), 0, pdTRUE, ( pucMessageBufferStorageArea ), ( pxStaticMessageBuffer ), ( pxSendCompletedCallback ), ( pxReceiveCompletedCallback ) )\n#endif\n\n/**\n * message_buffer.h\n *\n * @code{c}\n * size_t xMessageBufferSend( MessageBufferHandle_t xMessageBuffer,\n *                         const void *pvTxData,\n *                         size_t xDataLengthBytes,\n *                         TickType_t xTicksToWait );\n * @endcode\n *\n * Sends a discrete message to the message buffer.  The message can be any\n * length that fits within the buffer's free space, and is copied into the\n * buffer.\n *\n * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer\n * implementation (so also the message buffer implementation, as message buffers\n * are built on top of stream buffers) assumes there is only one task or\n * interrupt that will write to the buffer (the writer), and only one task or\n * interrupt that will read from the buffer (the reader).  It is safe for the\n * writer and reader to be different tasks or interrupts, but, unlike other\n * FreeRTOS objects, it is not safe to have multiple different writers or\n * multiple different readers.  If there are to be multiple different writers\n * then the application writer must place each call to a writing API function\n * (such as xMessageBufferSend()) inside a critical section and set the send\n * block time to 0.  Likewise, if there are to be multiple different readers\n * then the application writer must place each call to a reading API function\n * (such as xMessageBufferRead()) inside a critical section and set the receive\n * block time to 0.\n *\n * Use xMessageBufferSend() to write to a message buffer from a task.  Use\n * xMessageBufferSendFromISR() to write to a message buffer from an interrupt\n * service routine (ISR).\n *\n * @param xMessageBuffer The handle of the message buffer to which a message is\n * being sent.\n *\n * @param pvTxData A pointer to the message that is to be copied into the\n * message buffer.\n *\n * @param xDataLengthBytes The length of the message.  That is, the number of\n * bytes to copy from pvTxData into the message buffer.  When a message is\n * written to the message buffer an additional sizeof( size_t ) bytes are also\n * written to store the message's length.  sizeof( size_t ) is typically 4 bytes\n * on a 32-bit architecture, so on most 32-bit architecture setting\n * xDataLengthBytes to 20 will reduce the free space in the message buffer by 24\n * bytes (20 bytes of message data and 4 bytes to hold the message length).\n *\n * @param xTicksToWait The maximum amount of time the calling task should remain\n * in the Blocked state to wait for enough space to become available in the\n * message buffer, should the message buffer have insufficient space when\n * xMessageBufferSend() is called.  The calling task will never block if\n * xTicksToWait is zero.  The block time is specified in tick periods, so the\n * absolute time it represents is dependent on the tick frequency.  The macro\n * pdMS_TO_TICKS() can be used to convert a time specified in milliseconds into\n * a time specified in ticks.  Setting xTicksToWait to portMAX_DELAY will cause\n * the task to wait indefinitely (without timing out), provided\n * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h.  Tasks do not use any\n * CPU time when they are in the Blocked state.\n *\n * @return The number of bytes written to the message buffer.  If the call to\n * xMessageBufferSend() times out before there was enough space to write the\n * message into the message buffer then zero is returned.  If the call did not\n * time out then xDataLengthBytes is returned.\n *\n * Example use:\n * @code{c}\n * void vAFunction( MessageBufferHandle_t xMessageBuffer )\n * {\n * size_t xBytesSent;\n * uint8_t ucArrayToSend[] = { 0, 1, 2, 3 };\n * char *pcStringToSend = \"String to send\";\n * const TickType_t x100ms = pdMS_TO_TICKS( 100 );\n *\n *  // Send an array to the message buffer, blocking for a maximum of 100ms to\n *  // wait for enough space to be available in the message buffer.\n *  xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) ucArrayToSend, sizeof( ucArrayToSend ), x100ms );\n *\n *  if( xBytesSent != sizeof( ucArrayToSend ) )\n *  {\n *      // The call to xMessageBufferSend() times out before there was enough\n *      // space in the buffer for the data to be written.\n *  }\n *\n *  // Send the string to the message buffer.  Return immediately if there is\n *  // not enough space in the buffer.\n *  xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) pcStringToSend, strlen( pcStringToSend ), 0 );\n *\n *  if( xBytesSent != strlen( pcStringToSend ) )\n *  {\n *      // The string could not be added to the message buffer because there was\n *      // not enough free space in the buffer.\n *  }\n * }\n * @endcode\n * \\defgroup xMessageBufferSend xMessageBufferSend\n * \\ingroup MessageBufferManagement\n */\n#define xMessageBufferSend( xMessageBuffer, pvTxData, xDataLengthBytes, xTicksToWait ) \\\n    xStreamBufferSend( ( xMessageBuffer ), ( pvTxData ), ( xDataLengthBytes ), ( xTicksToWait ) )\n\n/**\n * message_buffer.h\n *\n * @code{c}\n * size_t xMessageBufferSendFromISR( MessageBufferHandle_t xMessageBuffer,\n *                                const void *pvTxData,\n *                                size_t xDataLengthBytes,\n *                                BaseType_t *pxHigherPriorityTaskWoken );\n * @endcode\n *\n * Interrupt safe version of the API function that sends a discrete message to\n * the message buffer.  The message can be any length that fits within the\n * buffer's free space, and is copied into the buffer.\n *\n * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer\n * implementation (so also the message buffer implementation, as message buffers\n * are built on top of stream buffers) assumes there is only one task or\n * interrupt that will write to the buffer (the writer), and only one task or\n * interrupt that will read from the buffer (the reader).  It is safe for the\n * writer and reader to be different tasks or interrupts, but, unlike other\n * FreeRTOS objects, it is not safe to have multiple different writers or\n * multiple different readers.  If there are to be multiple different writers\n * then the application writer must place each call to a writing API function\n * (such as xMessageBufferSend()) inside a critical section and set the send\n * block time to 0.  Likewise, if there are to be multiple different readers\n * then the application writer must place each call to a reading API function\n * (such as xMessageBufferRead()) inside a critical section and set the receive\n * block time to 0.\n *\n * Use xMessageBufferSend() to write to a message buffer from a task.  Use\n * xMessageBufferSendFromISR() to write to a message buffer from an interrupt\n * service routine (ISR).\n *\n * @param xMessageBuffer The handle of the message buffer to which a message is\n * being sent.\n *\n * @param pvTxData A pointer to the message that is to be copied into the\n * message buffer.\n *\n * @param xDataLengthBytes The length of the message.  That is, the number of\n * bytes to copy from pvTxData into the message buffer.  When a message is\n * written to the message buffer an additional sizeof( size_t ) bytes are also\n * written to store the message's length.  sizeof( size_t ) is typically 4 bytes\n * on a 32-bit architecture, so on most 32-bit architecture setting\n * xDataLengthBytes to 20 will reduce the free space in the message buffer by 24\n * bytes (20 bytes of message data and 4 bytes to hold the message length).\n *\n * @param pxHigherPriorityTaskWoken  It is possible that a message buffer will\n * have a task blocked on it waiting for data.  Calling\n * xMessageBufferSendFromISR() can make data available, and so cause a task that\n * was waiting for data to leave the Blocked state.  If calling\n * xMessageBufferSendFromISR() causes a task to leave the Blocked state, and the\n * unblocked task has a priority higher than the currently executing task (the\n * task that was interrupted), then, internally, xMessageBufferSendFromISR()\n * will set *pxHigherPriorityTaskWoken to pdTRUE.  If\n * xMessageBufferSendFromISR() sets this value to pdTRUE, then normally a\n * context switch should be performed before the interrupt is exited.  This will\n * ensure that the interrupt returns directly to the highest priority Ready\n * state task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it\n * is passed into the function.  See the code example below for an example.\n *\n * @return The number of bytes actually written to the message buffer.  If the\n * message buffer didn't have enough free space for the message to be stored\n * then 0 is returned, otherwise xDataLengthBytes is returned.\n *\n * Example use:\n * @code{c}\n * // A message buffer that has already been created.\n * MessageBufferHandle_t xMessageBuffer;\n *\n * void vAnInterruptServiceRoutine( void )\n * {\n * size_t xBytesSent;\n * char *pcStringToSend = \"String to send\";\n * BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE.\n *\n *  // Attempt to send the string to the message buffer.\n *  xBytesSent = xMessageBufferSendFromISR( xMessageBuffer,\n *                                          ( void * ) pcStringToSend,\n *                                          strlen( pcStringToSend ),\n *                                          &xHigherPriorityTaskWoken );\n *\n *  if( xBytesSent != strlen( pcStringToSend ) )\n *  {\n *      // The string could not be added to the message buffer because there was\n *      // not enough free space in the buffer.\n *  }\n *\n *  // If xHigherPriorityTaskWoken was set to pdTRUE inside\n *  // xMessageBufferSendFromISR() then a task that has a priority above the\n *  // priority of the currently executing task was unblocked and a context\n *  // switch should be performed to ensure the ISR returns to the unblocked\n *  // task.  In most FreeRTOS ports this is done by simply passing\n *  // xHigherPriorityTaskWoken into portYIELD_FROM_ISR(), which will test the\n *  // variables value, and perform the context switch if necessary.  Check the\n *  // documentation for the port in use for port specific instructions.\n *  portYIELD_FROM_ISR( xHigherPriorityTaskWoken );\n * }\n * @endcode\n * \\defgroup xMessageBufferSendFromISR xMessageBufferSendFromISR\n * \\ingroup MessageBufferManagement\n */\n#define xMessageBufferSendFromISR( xMessageBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken ) \\\n    xStreamBufferSendFromISR( ( xMessageBuffer ), ( pvTxData ), ( xDataLengthBytes ), ( pxHigherPriorityTaskWoken ) )\n\n/**\n * message_buffer.h\n *\n * @code{c}\n * size_t xMessageBufferReceive( MessageBufferHandle_t xMessageBuffer,\n *                            void *pvRxData,\n *                            size_t xBufferLengthBytes,\n *                            TickType_t xTicksToWait );\n * @endcode\n *\n * Receives a discrete message from a message buffer.  Messages can be of\n * variable length and are copied out of the buffer.\n *\n * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer\n * implementation (so also the message buffer implementation, as message buffers\n * are built on top of stream buffers) assumes there is only one task or\n * interrupt that will write to the buffer (the writer), and only one task or\n * interrupt that will read from the buffer (the reader).  It is safe for the\n * writer and reader to be different tasks or interrupts, but, unlike other\n * FreeRTOS objects, it is not safe to have multiple different writers or\n * multiple different readers.  If there are to be multiple different writers\n * then the application writer must place each call to a writing API function\n * (such as xMessageBufferSend()) inside a critical section and set the send\n * block time to 0.  Likewise, if there are to be multiple different readers\n * then the application writer must place each call to a reading API function\n * (such as xMessageBufferRead()) inside a critical section and set the receive\n * block time to 0.\n *\n * Use xMessageBufferReceive() to read from a message buffer from a task.  Use\n * xMessageBufferReceiveFromISR() to read from a message buffer from an\n * interrupt service routine (ISR).\n *\n * @param xMessageBuffer The handle of the message buffer from which a message\n * is being received.\n *\n * @param pvRxData A pointer to the buffer into which the received message is\n * to be copied.\n *\n * @param xBufferLengthBytes The length of the buffer pointed to by the pvRxData\n * parameter.  This sets the maximum length of the message that can be received.\n * If xBufferLengthBytes is too small to hold the next message then the message\n * will be left in the message buffer and 0 will be returned.\n *\n * @param xTicksToWait The maximum amount of time the task should remain in the\n * Blocked state to wait for a message, should the message buffer be empty.\n * xMessageBufferReceive() will return immediately if xTicksToWait is zero and\n * the message buffer is empty.  The block time is specified in tick periods, so\n * the absolute time it represents is dependent on the tick frequency.  The\n * macro pdMS_TO_TICKS() can be used to convert a time specified in milliseconds\n * into a time specified in ticks.  Setting xTicksToWait to portMAX_DELAY will\n * cause the task to wait indefinitely (without timing out), provided\n * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h.  Tasks do not use any\n * CPU time when they are in the Blocked state.\n *\n * @return The length, in bytes, of the message read from the message buffer, if\n * any.  If xMessageBufferReceive() times out before a message became available\n * then zero is returned.  If the length of the message is greater than\n * xBufferLengthBytes then the message will be left in the message buffer and\n * zero is returned.\n *\n * Example use:\n * @code{c}\n * void vAFunction( MessageBuffer_t xMessageBuffer )\n * {\n * uint8_t ucRxData[ 20 ];\n * size_t xReceivedBytes;\n * const TickType_t xBlockTime = pdMS_TO_TICKS( 20 );\n *\n *  // Receive the next message from the message buffer.  Wait in the Blocked\n *  // state (so not using any CPU processing time) for a maximum of 100ms for\n *  // a message to become available.\n *  xReceivedBytes = xMessageBufferReceive( xMessageBuffer,\n *                                          ( void * ) ucRxData,\n *                                          sizeof( ucRxData ),\n *                                          xBlockTime );\n *\n *  if( xReceivedBytes > 0 )\n *  {\n *      // A ucRxData contains a message that is xReceivedBytes long.  Process\n *      // the message here....\n *  }\n * }\n * @endcode\n * \\defgroup xMessageBufferReceive xMessageBufferReceive\n * \\ingroup MessageBufferManagement\n */\n#define xMessageBufferReceive( xMessageBuffer, pvRxData, xBufferLengthBytes, xTicksToWait ) \\\n    xStreamBufferReceive( ( xMessageBuffer ), ( pvRxData ), ( xBufferLengthBytes ), ( xTicksToWait ) )\n\n\n/**\n * message_buffer.h\n *\n * @code{c}\n * size_t xMessageBufferReceiveFromISR( MessageBufferHandle_t xMessageBuffer,\n *                                   void *pvRxData,\n *                                   size_t xBufferLengthBytes,\n *                                   BaseType_t *pxHigherPriorityTaskWoken );\n * @endcode\n *\n * An interrupt safe version of the API function that receives a discrete\n * message from a message buffer.  Messages can be of variable length and are\n * copied out of the buffer.\n *\n * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer\n * implementation (so also the message buffer implementation, as message buffers\n * are built on top of stream buffers) assumes there is only one task or\n * interrupt that will write to the buffer (the writer), and only one task or\n * interrupt that will read from the buffer (the reader).  It is safe for the\n * writer and reader to be different tasks or interrupts, but, unlike other\n * FreeRTOS objects, it is not safe to have multiple different writers or\n * multiple different readers.  If there are to be multiple different writers\n * then the application writer must place each call to a writing API function\n * (such as xMessageBufferSend()) inside a critical section and set the send\n * block time to 0.  Likewise, if there are to be multiple different readers\n * then the application writer must place each call to a reading API function\n * (such as xMessageBufferRead()) inside a critical section and set the receive\n * block time to 0.\n *\n * Use xMessageBufferReceive() to read from a message buffer from a task.  Use\n * xMessageBufferReceiveFromISR() to read from a message buffer from an\n * interrupt service routine (ISR).\n *\n * @param xMessageBuffer The handle of the message buffer from which a message\n * is being received.\n *\n * @param pvRxData A pointer to the buffer into which the received message is\n * to be copied.\n *\n * @param xBufferLengthBytes The length of the buffer pointed to by the pvRxData\n * parameter.  This sets the maximum length of the message that can be received.\n * If xBufferLengthBytes is too small to hold the next message then the message\n * will be left in the message buffer and 0 will be returned.\n *\n * @param pxHigherPriorityTaskWoken  It is possible that a message buffer will\n * have a task blocked on it waiting for space to become available.  Calling\n * xMessageBufferReceiveFromISR() can make space available, and so cause a task\n * that is waiting for space to leave the Blocked state.  If calling\n * xMessageBufferReceiveFromISR() causes a task to leave the Blocked state, and\n * the unblocked task has a priority higher than the currently executing task\n * (the task that was interrupted), then, internally,\n * xMessageBufferReceiveFromISR() will set *pxHigherPriorityTaskWoken to pdTRUE.\n * If xMessageBufferReceiveFromISR() sets this value to pdTRUE, then normally a\n * context switch should be performed before the interrupt is exited.  That will\n * ensure the interrupt returns directly to the highest priority Ready state\n * task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it is\n * passed into the function.  See the code example below for an example.\n *\n * @return The length, in bytes, of the message read from the message buffer, if\n * any.\n *\n * Example use:\n * @code{c}\n * // A message buffer that has already been created.\n * MessageBuffer_t xMessageBuffer;\n *\n * void vAnInterruptServiceRoutine( void )\n * {\n * uint8_t ucRxData[ 20 ];\n * size_t xReceivedBytes;\n * BaseType_t xHigherPriorityTaskWoken = pdFALSE;  // Initialised to pdFALSE.\n *\n *  // Receive the next message from the message buffer.\n *  xReceivedBytes = xMessageBufferReceiveFromISR( xMessageBuffer,\n *                                                ( void * ) ucRxData,\n *                                                sizeof( ucRxData ),\n *                                                &xHigherPriorityTaskWoken );\n *\n *  if( xReceivedBytes > 0 )\n *  {\n *      // A ucRxData contains a message that is xReceivedBytes long.  Process\n *      // the message here....\n *  }\n *\n *  // If xHigherPriorityTaskWoken was set to pdTRUE inside\n *  // xMessageBufferReceiveFromISR() then a task that has a priority above the\n *  // priority of the currently executing task was unblocked and a context\n *  // switch should be performed to ensure the ISR returns to the unblocked\n *  // task.  In most FreeRTOS ports this is done by simply passing\n *  // xHigherPriorityTaskWoken into portYIELD_FROM_ISR(), which will test the\n *  // variables value, and perform the context switch if necessary.  Check the\n *  // documentation for the port in use for port specific instructions.\n *  portYIELD_FROM_ISR( xHigherPriorityTaskWoken );\n * }\n * @endcode\n * \\defgroup xMessageBufferReceiveFromISR xMessageBufferReceiveFromISR\n * \\ingroup MessageBufferManagement\n */\n#define xMessageBufferReceiveFromISR( xMessageBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken ) \\\n    xStreamBufferReceiveFromISR( ( xMessageBuffer ), ( pvRxData ), ( xBufferLengthBytes ), ( pxHigherPriorityTaskWoken ) )\n\n/**\n * message_buffer.h\n *\n * @code{c}\n * void vMessageBufferDelete( MessageBufferHandle_t xMessageBuffer );\n * @endcode\n *\n * Deletes a message buffer that was previously created using a call to\n * xMessageBufferCreate() or xMessageBufferCreateStatic().  If the message\n * buffer was created using dynamic memory (that is, by xMessageBufferCreate()),\n * then the allocated memory is freed.\n *\n * A message buffer handle must not be used after the message buffer has been\n * deleted.\n *\n * @param xMessageBuffer The handle of the message buffer to be deleted.\n *\n */\n#define vMessageBufferDelete( xMessageBuffer ) \\\n    vStreamBufferDelete( xMessageBuffer )\n\n/**\n * message_buffer.h\n * @code{c}\n * BaseType_t xMessageBufferIsFull( MessageBufferHandle_t xMessageBuffer );\n * @endcode\n *\n * Tests to see if a message buffer is full.  A message buffer is full if it\n * cannot accept any more messages, of any size, until space is made available\n * by a message being removed from the message buffer.\n *\n * @param xMessageBuffer The handle of the message buffer being queried.\n *\n * @return If the message buffer referenced by xMessageBuffer is full then\n * pdTRUE is returned.  Otherwise pdFALSE is returned.\n */\n#define xMessageBufferIsFull( xMessageBuffer ) \\\n    xStreamBufferIsFull( xMessageBuffer )\n\n/**\n * message_buffer.h\n * @code{c}\n * BaseType_t xMessageBufferIsEmpty( MessageBufferHandle_t xMessageBuffer );\n * @endcode\n *\n * Tests to see if a message buffer is empty (does not contain any messages).\n *\n * @param xMessageBuffer The handle of the message buffer being queried.\n *\n * @return If the message buffer referenced by xMessageBuffer is empty then\n * pdTRUE is returned.  Otherwise pdFALSE is returned.\n *\n */\n#define xMessageBufferIsEmpty( xMessageBuffer ) \\\n    xStreamBufferIsEmpty( xMessageBuffer )\n\n/**\n * message_buffer.h\n * @code{c}\n * BaseType_t xMessageBufferReset( MessageBufferHandle_t xMessageBuffer );\n * @endcode\n *\n * Resets a message buffer to its initial empty state, discarding any message it\n * contained.\n *\n * A message buffer can only be reset if there are no tasks blocked on it.\n *\n * @param xMessageBuffer The handle of the message buffer being reset.\n *\n * @return If the message buffer was reset then pdPASS is returned.  If the\n * message buffer could not be reset because either there was a task blocked on\n * the message queue to wait for space to become available, or to wait for a\n * a message to be available, then pdFAIL is returned.\n *\n * \\defgroup xMessageBufferReset xMessageBufferReset\n * \\ingroup MessageBufferManagement\n */\n#define xMessageBufferReset( xMessageBuffer ) \\\n    xStreamBufferReset( xMessageBuffer )\n\n\n/**\n * message_buffer.h\n * @code{c}\n * size_t xMessageBufferSpaceAvailable( MessageBufferHandle_t xMessageBuffer );\n * @endcode\n * Returns the number of bytes of free space in the message buffer.\n *\n * @param xMessageBuffer The handle of the message buffer being queried.\n *\n * @return The number of bytes that can be written to the message buffer before\n * the message buffer would be full.  When a message is written to the message\n * buffer an additional sizeof( size_t ) bytes are also written to store the\n * message's length.  sizeof( size_t ) is typically 4 bytes on a 32-bit\n * architecture, so if xMessageBufferSpacesAvailable() returns 10, then the size\n * of the largest message that can be written to the message buffer is 6 bytes.\n *\n * \\defgroup xMessageBufferSpaceAvailable xMessageBufferSpaceAvailable\n * \\ingroup MessageBufferManagement\n */\n#define xMessageBufferSpaceAvailable( xMessageBuffer ) \\\n    xStreamBufferSpacesAvailable( xMessageBuffer )\n#define xMessageBufferSpacesAvailable( xMessageBuffer ) \\\n    xStreamBufferSpacesAvailable( xMessageBuffer ) /* Corrects typo in original macro name. */\n\n/**\n * message_buffer.h\n * @code{c}\n * size_t xMessageBufferNextLengthBytes( MessageBufferHandle_t xMessageBuffer );\n * @endcode\n * Returns the length (in bytes) of the next message in a message buffer.\n * Useful if xMessageBufferReceive() returned 0 because the size of the buffer\n * passed into xMessageBufferReceive() was too small to hold the next message.\n *\n * @param xMessageBuffer The handle of the message buffer being queried.\n *\n * @return The length (in bytes) of the next message in the message buffer, or 0\n * if the message buffer is empty.\n *\n * \\defgroup xMessageBufferNextLengthBytes xMessageBufferNextLengthBytes\n * \\ingroup MessageBufferManagement\n */\n#define xMessageBufferNextLengthBytes( xMessageBuffer ) \\\n    xStreamBufferNextMessageLengthBytes( xMessageBuffer ) PRIVILEGED_FUNCTION;\n\n/**\n * message_buffer.h\n *\n * @code{c}\n * BaseType_t xMessageBufferSendCompletedFromISR( MessageBufferHandle_t xMessageBuffer, BaseType_t *pxHigherPriorityTaskWoken );\n * @endcode\n *\n * For advanced users only.\n *\n * The sbSEND_COMPLETED() macro is called from within the FreeRTOS APIs when\n * data is sent to a message buffer or stream buffer.  If there was a task that\n * was blocked on the message or stream buffer waiting for data to arrive then\n * the sbSEND_COMPLETED() macro sends a notification to the task to remove it\n * from the Blocked state.  xMessageBufferSendCompletedFromISR() does the same\n * thing.  It is provided to enable application writers to implement their own\n * version of sbSEND_COMPLETED(), and MUST NOT BE USED AT ANY OTHER TIME.\n *\n * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for\n * additional information.\n *\n * @param xMessageBuffer The handle of the stream buffer to which data was\n * written.\n *\n * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be\n * initialised to pdFALSE before it is passed into\n * xMessageBufferSendCompletedFromISR().  If calling\n * xMessageBufferSendCompletedFromISR() removes a task from the Blocked state,\n * and the task has a priority above the priority of the currently running task,\n * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a\n * context switch should be performed before exiting the ISR.\n *\n * @return If a task was removed from the Blocked state then pdTRUE is returned.\n * Otherwise pdFALSE is returned.\n *\n * \\defgroup xMessageBufferSendCompletedFromISR xMessageBufferSendCompletedFromISR\n * \\ingroup StreamBufferManagement\n */\n#define xMessageBufferSendCompletedFromISR( xMessageBuffer, pxHigherPriorityTaskWoken ) \\\n    xStreamBufferSendCompletedFromISR( ( xMessageBuffer ), ( pxHigherPriorityTaskWoken ) )\n\n/**\n * message_buffer.h\n *\n * @code{c}\n * BaseType_t xMessageBufferReceiveCompletedFromISR( MessageBufferHandle_t xMessageBuffer, BaseType_t *pxHigherPriorityTaskWoken );\n * @endcode\n *\n * For advanced users only.\n *\n * The sbRECEIVE_COMPLETED() macro is called from within the FreeRTOS APIs when\n * data is read out of a message buffer or stream buffer.  If there was a task\n * that was blocked on the message or stream buffer waiting for data to arrive\n * then the sbRECEIVE_COMPLETED() macro sends a notification to the task to\n * remove it from the Blocked state.  xMessageBufferReceiveCompletedFromISR()\n * does the same thing.  It is provided to enable application writers to\n * implement their own version of sbRECEIVE_COMPLETED(), and MUST NOT BE USED AT\n * ANY OTHER TIME.\n *\n * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for\n * additional information.\n *\n * @param xMessageBuffer The handle of the stream buffer from which data was\n * read.\n *\n * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be\n * initialised to pdFALSE before it is passed into\n * xMessageBufferReceiveCompletedFromISR().  If calling\n * xMessageBufferReceiveCompletedFromISR() removes a task from the Blocked state,\n * and the task has a priority above the priority of the currently running task,\n * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a\n * context switch should be performed before exiting the ISR.\n *\n * @return If a task was removed from the Blocked state then pdTRUE is returned.\n * Otherwise pdFALSE is returned.\n *\n * \\defgroup xMessageBufferReceiveCompletedFromISR xMessageBufferReceiveCompletedFromISR\n * \\ingroup StreamBufferManagement\n */\n#define xMessageBufferReceiveCompletedFromISR( xMessageBuffer, pxHigherPriorityTaskWoken ) \\\n    xStreamBufferReceiveCompletedFromISR( ( xMessageBuffer ), ( pxHigherPriorityTaskWoken ) )\n\n/* *INDENT-OFF* */\n#if defined( __cplusplus )\n    } /* extern \"C\" */\n#endif\n/* *INDENT-ON* */\n\n#endif /* !defined( FREERTOS_MESSAGE_BUFFER_H ) */\n"
  },
  {
    "path": "FreeRTOS-comparison/include/mpu_prototypes.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/*\n * When the MPU is used the standard (non MPU) API functions are mapped to\n * equivalents that start \"MPU_\", the prototypes for which are defined in this\n * header files.  This will cause the application code to call the MPU_ version\n * which wraps the non-MPU version with privilege promoting then demoting code,\n * so the kernel code always runs will full privileges.\n */\n\n\n#ifndef MPU_PROTOTYPES_H\n#define MPU_PROTOTYPES_H\n\n/* MPU versions of task.h API functions. */\nBaseType_t MPU_xTaskCreate( TaskFunction_t pxTaskCode,\n                            const char * const pcName,\n                            const uint16_t usStackDepth,\n                            void * const pvParameters,\n                            UBaseType_t uxPriority,\n                            TaskHandle_t * const pxCreatedTask ) FREERTOS_SYSTEM_CALL;\nTaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode,\n                                    const char * const pcName,\n                                    const uint32_t ulStackDepth,\n                                    void * const pvParameters,\n                                    UBaseType_t uxPriority,\n                                    StackType_t * const puxStackBuffer,\n                                    StaticTask_t * const pxTaskBuffer ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vTaskDelete( TaskHandle_t xTaskToDelete ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vTaskDelay( const TickType_t xTicksToDelay ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,\n                                const TickType_t xTimeIncrement ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;\nUBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;\neTaskState MPU_eTaskGetState( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vTaskGetInfo( TaskHandle_t xTask,\n                       TaskStatus_t * pxTaskStatus,\n                       BaseType_t xGetFreeStackSpace,\n                       eTaskState eState ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vTaskPrioritySet( TaskHandle_t xTask,\n                           UBaseType_t uxNewPriority ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vTaskResume( TaskHandle_t xTaskToResume ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vTaskStartScheduler( void ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vTaskSuspendAll( void ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xTaskResumeAll( void ) FREERTOS_SYSTEM_CALL;\nTickType_t MPU_xTaskGetTickCount( void ) FREERTOS_SYSTEM_CALL;\nUBaseType_t MPU_uxTaskGetNumberOfTasks( void ) FREERTOS_SYSTEM_CALL;\nchar * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) FREERTOS_SYSTEM_CALL;\nTaskHandle_t MPU_xTaskGetHandle( const char * pcNameToQuery ) FREERTOS_SYSTEM_CALL;\nUBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;\nconfigSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,\n                                     TaskHookFunction_t pxHookFunction ) FREERTOS_SYSTEM_CALL;\nTaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,\n                                            BaseType_t xIndex,\n                                            void * pvValue ) FREERTOS_SYSTEM_CALL;\nvoid * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,\n                                               BaseType_t xIndex ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask,\n                                             void * pvParameter ) FREERTOS_SYSTEM_CALL;\nTaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) FREERTOS_SYSTEM_CALL;\nUBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,\n                                      const UBaseType_t uxArraySize,\n                                      configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) FREERTOS_SYSTEM_CALL;\nconfigRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) FREERTOS_SYSTEM_CALL;\nconfigRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vTaskList( char * pcWriteBuffer ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vTaskGetRunTimeStats( char * pcWriteBuffer ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,\n                                   UBaseType_t uxIndexToNotify,\n                                   uint32_t ulValue,\n                                   eNotifyAction eAction,\n                                   uint32_t * pulPreviousNotificationValue ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,\n                                       uint32_t ulBitsToClearOnEntry,\n                                       uint32_t ulBitsToClearOnExit,\n                                       uint32_t * pulNotificationValue,\n                                       TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;\nuint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,\n                                      BaseType_t xClearCountOnExit,\n                                      TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,\n                                             UBaseType_t uxIndexToClear ) FREERTOS_SYSTEM_CALL;\nuint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,\n                                            UBaseType_t uxIndexToClear,\n                                            uint32_t ulBitsToClear ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xTaskIncrementTick( void ) FREERTOS_SYSTEM_CALL;\nTaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,\n                                     TickType_t * const pxTicksToWait ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vTaskMissedYield( void ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xTaskGetSchedulerState( void ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) FREERTOS_SYSTEM_CALL;\n\n/* MPU versions of queue.h API functions. */\nBaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,\n                                  const void * const pvItemToQueue,\n                                  TickType_t xTicksToWait,\n                                  const BaseType_t xCopyPosition ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,\n                              void * const pvBuffer,\n                              TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,\n                           void * const pvBuffer,\n                           TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,\n                                    TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;\nUBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;\nUBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vQueueDelete( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;\nQueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;\nQueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType,\n                                           StaticQueue_t * pxStaticQueue ) FREERTOS_SYSTEM_CALL;\nQueueHandle_t MPU_xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount,\n                                                 const UBaseType_t uxInitialCount ) FREERTOS_SYSTEM_CALL;\nQueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount,\n                                                       const UBaseType_t uxInitialCount,\n                                                       StaticQueue_t * pxStaticQueue ) FREERTOS_SYSTEM_CALL;\nTaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,\n                                         TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vQueueAddToRegistry( QueueHandle_t xQueue,\n                              const char * pcName ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;\nconst char * MPU_pcQueueGetName( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;\nQueueHandle_t MPU_xQueueGenericCreate( const UBaseType_t uxQueueLength,\n                                       const UBaseType_t uxItemSize,\n                                       const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;\nQueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength,\n                                             const UBaseType_t uxItemSize,\n                                             uint8_t * pucQueueStorage,\n                                             StaticQueue_t * pxStaticQueue,\n                                             const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;\nQueueSetHandle_t MPU_xQueueCreateSet( const UBaseType_t uxEventQueueLength ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,\n                               QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore,\n                                    QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL;\nQueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,\n                                                const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xQueueGenericReset( QueueHandle_t xQueue,\n                                   BaseType_t xNewQueue ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vQueueSetQueueNumber( QueueHandle_t xQueue,\n                               UBaseType_t uxQueueNumber ) FREERTOS_SYSTEM_CALL;\nUBaseType_t MPU_uxQueueGetQueueNumber( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;\nuint8_t MPU_ucQueueGetQueueType( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;\n\n/* MPU versions of timers.h API functions. */\nTimerHandle_t MPU_xTimerCreate( const char * const pcTimerName,\n                                const TickType_t xTimerPeriodInTicks,\n                                const UBaseType_t uxAutoReload,\n                                void * const pvTimerID,\n                                TimerCallbackFunction_t pxCallbackFunction ) FREERTOS_SYSTEM_CALL;\nTimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName,\n                                      const TickType_t xTimerPeriodInTicks,\n                                      const UBaseType_t uxAutoReload,\n                                      void * const pvTimerID,\n                                      TimerCallbackFunction_t pxCallbackFunction,\n                                      StaticTimer_t * pxTimerBuffer ) FREERTOS_SYSTEM_CALL;\nvoid * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vTimerSetTimerID( TimerHandle_t xTimer,\n                           void * pvNewID ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;\nTaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xTimerPendFunctionCall( PendedFunction_t xFunctionToPend,\n                                       void * pvParameter1,\n                                       uint32_t ulParameter2,\n                                       TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;\nconst char * MPU_pcTimerGetName( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vTimerSetReloadMode( TimerHandle_t xTimer,\n                              const UBaseType_t uxAutoReload ) FREERTOS_SYSTEM_CALL;\nUBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;\nTickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;\nTickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xTimerCreateTimerTask( void ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer,\n                                     const BaseType_t xCommandID,\n                                     const TickType_t xOptionalValue,\n                                     BaseType_t * const pxHigherPriorityTaskWoken,\n                                     const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;\n\n/* MPU versions of event_group.h API functions. */\nEventGroupHandle_t MPU_xEventGroupCreate( void ) FREERTOS_SYSTEM_CALL;\nEventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t * pxEventGroupBuffer ) FREERTOS_SYSTEM_CALL;\nEventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,\n                                     const EventBits_t uxBitsToWaitFor,\n                                     const BaseType_t xClearOnExit,\n                                     const BaseType_t xWaitForAllBits,\n                                     TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;\nEventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,\n                                      const EventBits_t uxBitsToClear ) FREERTOS_SYSTEM_CALL;\nEventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,\n                                    const EventBits_t uxBitsToSet ) FREERTOS_SYSTEM_CALL;\nEventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,\n                                 const EventBits_t uxBitsToSet,\n                                 const EventBits_t uxBitsToWaitFor,\n                                 TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) FREERTOS_SYSTEM_CALL;\nUBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) FREERTOS_SYSTEM_CALL;\n\n/* MPU versions of message/stream_buffer.h API functions. */\nsize_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,\n                              const void * pvTxData,\n                              size_t xDataLengthBytes,\n                              TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;\nsize_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,\n                                 void * pvRxData,\n                                 size_t xBufferLengthBytes,\n                                 TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;\nsize_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;\nsize_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;\nsize_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,\n                                             size_t xTriggerLevel ) FREERTOS_SYSTEM_CALL;\nStreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes,\n                                                     size_t xTriggerLevelBytes,\n                                                     BaseType_t xIsMessageBuffer,\n                                                     StreamBufferCallbackFunction_t pxSendCompletedCallback,\n                                                     StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) FREERTOS_SYSTEM_CALL;\nStreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,\n                                                           size_t xTriggerLevelBytes,\n                                                           BaseType_t xIsMessageBuffer,\n                                                           uint8_t * const pucStreamBufferStorageArea,\n                                                           StaticStreamBuffer_t * const pxStaticStreamBuffer,\n                                                           StreamBufferCallbackFunction_t pxSendCompletedCallback,\n                                                           StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) FREERTOS_SYSTEM_CALL;\n\n\n\n#endif /* MPU_PROTOTYPES_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/include/mpu_wrappers.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef MPU_WRAPPERS_H\n#define MPU_WRAPPERS_H\n\n/* This file redefines API functions to be called through a wrapper macro, but\n * only for ports that are using the MPU. */\n#if ( portUSING_MPU_WRAPPERS == 1 )\n\n/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE will be defined when this file is\n * included from queue.c or task.c to prevent it from having an effect within\n * those files. */\n    #ifndef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/*\n * Map standard (non MPU) API functions to equivalents that start\n * \"MPU_\".  This will cause the application code to call the MPU_\n * version, which wraps the non-MPU version with privilege promoting\n * then demoting code, so the kernel code always runs will full\n * privileges.\n */\n\n/* Map standard task.h API functions to the MPU equivalents. */\n        #define xTaskCreate                            MPU_xTaskCreate\n        #define xTaskCreateStatic                      MPU_xTaskCreateStatic\n        #define vTaskDelete                            MPU_vTaskDelete\n        #define vTaskDelay                             MPU_vTaskDelay\n        #define xTaskDelayUntil                        MPU_xTaskDelayUntil\n        #define xTaskAbortDelay                        MPU_xTaskAbortDelay\n        #define uxTaskPriorityGet                      MPU_uxTaskPriorityGet\n        #define eTaskGetState                          MPU_eTaskGetState\n        #define vTaskGetInfo                           MPU_vTaskGetInfo\n        #define vTaskPrioritySet                       MPU_vTaskPrioritySet\n        #define vTaskSuspend                           MPU_vTaskSuspend\n        #define vTaskResume                            MPU_vTaskResume\n        #define vTaskSuspendAll                        MPU_vTaskSuspendAll\n        #define xTaskResumeAll                         MPU_xTaskResumeAll\n        #define xTaskGetTickCount                      MPU_xTaskGetTickCount\n        #define uxTaskGetNumberOfTasks                 MPU_uxTaskGetNumberOfTasks\n        #define pcTaskGetName                          MPU_pcTaskGetName\n        #define xTaskGetHandle                         MPU_xTaskGetHandle\n        #define uxTaskGetStackHighWaterMark            MPU_uxTaskGetStackHighWaterMark\n        #define uxTaskGetStackHighWaterMark2           MPU_uxTaskGetStackHighWaterMark2\n        #define vTaskSetApplicationTaskTag             MPU_vTaskSetApplicationTaskTag\n        #define xTaskGetApplicationTaskTag             MPU_xTaskGetApplicationTaskTag\n        #define vTaskSetThreadLocalStoragePointer      MPU_vTaskSetThreadLocalStoragePointer\n        #define pvTaskGetThreadLocalStoragePointer     MPU_pvTaskGetThreadLocalStoragePointer\n        #define xTaskCallApplicationTaskHook           MPU_xTaskCallApplicationTaskHook\n        #define xTaskGetIdleTaskHandle                 MPU_xTaskGetIdleTaskHandle\n        #define uxTaskGetSystemState                   MPU_uxTaskGetSystemState\n        #define vTaskList                              MPU_vTaskList\n        #define vTaskGetRunTimeStats                   MPU_vTaskGetRunTimeStats\n        #define ulTaskGetIdleRunTimeCounter            MPU_ulTaskGetIdleRunTimeCounter\n        #define ulTaskGetIdleRunTimePercent            MPU_ulTaskGetIdleRunTimePercent\n        #define xTaskGenericNotify                     MPU_xTaskGenericNotify\n        #define xTaskGenericNotifyWait                 MPU_xTaskGenericNotifyWait\n        #define ulTaskGenericNotifyTake                MPU_ulTaskGenericNotifyTake\n        #define xTaskGenericNotifyStateClear           MPU_xTaskGenericNotifyStateClear\n        #define ulTaskGenericNotifyValueClear          MPU_ulTaskGenericNotifyValueClear\n        #define xTaskCatchUpTicks                      MPU_xTaskCatchUpTicks\n\n        #define xTaskGetCurrentTaskHandle              MPU_xTaskGetCurrentTaskHandle\n        #define vTaskSetTimeOutState                   MPU_vTaskSetTimeOutState\n        #define xTaskCheckForTimeOut                   MPU_xTaskCheckForTimeOut\n        #define xTaskGetSchedulerState                 MPU_xTaskGetSchedulerState\n\n/* Map standard queue.h API functions to the MPU equivalents. */\n        #define xQueueGenericSend                      MPU_xQueueGenericSend\n        #define xQueueReceive                          MPU_xQueueReceive\n        #define xQueuePeek                             MPU_xQueuePeek\n        #define xQueueSemaphoreTake                    MPU_xQueueSemaphoreTake\n        #define uxQueueMessagesWaiting                 MPU_uxQueueMessagesWaiting\n        #define uxQueueSpacesAvailable                 MPU_uxQueueSpacesAvailable\n        #define vQueueDelete                           MPU_vQueueDelete\n        #define xQueueCreateMutex                      MPU_xQueueCreateMutex\n        #define xQueueCreateMutexStatic                MPU_xQueueCreateMutexStatic\n        #define xQueueCreateCountingSemaphore          MPU_xQueueCreateCountingSemaphore\n        #define xQueueCreateCountingSemaphoreStatic    MPU_xQueueCreateCountingSemaphoreStatic\n        #define xQueueGetMutexHolder                   MPU_xQueueGetMutexHolder\n        #define xQueueTakeMutexRecursive               MPU_xQueueTakeMutexRecursive\n        #define xQueueGiveMutexRecursive               MPU_xQueueGiveMutexRecursive\n        #define xQueueGenericCreate                    MPU_xQueueGenericCreate\n        #define xQueueGenericCreateStatic              MPU_xQueueGenericCreateStatic\n        #define xQueueCreateSet                        MPU_xQueueCreateSet\n        #define xQueueAddToSet                         MPU_xQueueAddToSet\n        #define xQueueRemoveFromSet                    MPU_xQueueRemoveFromSet\n        #define xQueueSelectFromSet                    MPU_xQueueSelectFromSet\n        #define xQueueGenericReset                     MPU_xQueueGenericReset\n\n        #if ( configQUEUE_REGISTRY_SIZE > 0 )\n            #define vQueueAddToRegistry                MPU_vQueueAddToRegistry\n            #define vQueueUnregisterQueue              MPU_vQueueUnregisterQueue\n            #define pcQueueGetName                     MPU_pcQueueGetName\n        #endif\n\n/* Map standard timer.h API functions to the MPU equivalents. */\n        #define pvTimerGetTimerID                      MPU_pvTimerGetTimerID\n        #define vTimerSetTimerID                       MPU_vTimerSetTimerID\n        #define xTimerIsTimerActive                    MPU_xTimerIsTimerActive\n        #define xTimerGetTimerDaemonTaskHandle         MPU_xTimerGetTimerDaemonTaskHandle\n        #define pcTimerGetName                         MPU_pcTimerGetName\n        #define vTimerSetReloadMode                    MPU_vTimerSetReloadMode\n        #define uxTimerGetReloadMode                   MPU_uxTimerGetReloadMode\n        #define xTimerGetPeriod                        MPU_xTimerGetPeriod\n        #define xTimerGetExpiryTime                    MPU_xTimerGetExpiryTime\n        #define xTimerGenericCommand                   MPU_xTimerGenericCommand\n\n/* Map standard event_group.h API functions to the MPU equivalents. */\n        #define xEventGroupCreate                      MPU_xEventGroupCreate\n        #define xEventGroupCreateStatic                MPU_xEventGroupCreateStatic\n        #define xEventGroupWaitBits                    MPU_xEventGroupWaitBits\n        #define xEventGroupClearBits                   MPU_xEventGroupClearBits\n        #define xEventGroupSetBits                     MPU_xEventGroupSetBits\n        #define xEventGroupSync                        MPU_xEventGroupSync\n        #define vEventGroupDelete                      MPU_vEventGroupDelete\n\n/* Map standard message/stream_buffer.h API functions to the MPU\n * equivalents. */\n        #define xStreamBufferSend                      MPU_xStreamBufferSend\n        #define xStreamBufferReceive                   MPU_xStreamBufferReceive\n        #define xStreamBufferNextMessageLengthBytes    MPU_xStreamBufferNextMessageLengthBytes\n        #define vStreamBufferDelete                    MPU_vStreamBufferDelete\n        #define xStreamBufferIsFull                    MPU_xStreamBufferIsFull\n        #define xStreamBufferIsEmpty                   MPU_xStreamBufferIsEmpty\n        #define xStreamBufferReset                     MPU_xStreamBufferReset\n        #define xStreamBufferSpacesAvailable           MPU_xStreamBufferSpacesAvailable\n        #define xStreamBufferBytesAvailable            MPU_xStreamBufferBytesAvailable\n        #define xStreamBufferSetTriggerLevel           MPU_xStreamBufferSetTriggerLevel\n        #define xStreamBufferGenericCreate             MPU_xStreamBufferGenericCreate\n        #define xStreamBufferGenericCreateStatic       MPU_xStreamBufferGenericCreateStatic\n\n\n/* Remove the privileged function macro, but keep the PRIVILEGED_DATA\n * macro so applications can place data in privileged access sections\n * (useful when using statically allocated objects). */\n        #define PRIVILEGED_FUNCTION\n        #define PRIVILEGED_DATA    __attribute__( ( section( \"privileged_data\" ) ) )\n        #define FREERTOS_SYSTEM_CALL\n\n    #else /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */\n\n/* Ensure API functions go in the privileged execution section. */\n        #define PRIVILEGED_FUNCTION     __attribute__( ( section( \"privileged_functions\" ) ) )\n        #define PRIVILEGED_DATA         __attribute__( ( section( \"privileged_data\" ) ) )\n        #define FREERTOS_SYSTEM_CALL    __attribute__( ( section( \"freertos_system_calls\" ) ) )\n\n    #endif /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */\n\n#else /* portUSING_MPU_WRAPPERS */\n\n    #define PRIVILEGED_FUNCTION\n    #define PRIVILEGED_DATA\n    #define FREERTOS_SYSTEM_CALL\n\n#endif /* portUSING_MPU_WRAPPERS */\n\n\n#endif /* MPU_WRAPPERS_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/include/portable.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/*-----------------------------------------------------------\n* Portable layer API.  Each function must be defined for each port.\n*----------------------------------------------------------*/\n\n#ifndef PORTABLE_H\n#define PORTABLE_H\n\n/* Each FreeRTOS port has a unique portmacro.h header file.  Originally a\n * pre-processor definition was used to ensure the pre-processor found the correct\n * portmacro.h file for the port being used.  That scheme was deprecated in favour\n * of setting the compiler's include path such that it found the correct\n * portmacro.h file - removing the need for the constant and allowing the\n * portmacro.h file to be located anywhere in relation to the port being used.\n * Purely for reasons of backward compatibility the old method is still valid, but\n * to make it clear that new projects should not use it, support for the port\n * specific constants has been moved into the deprecated_definitions.h header\n * file. */\n#include \"deprecated_definitions.h\"\n\n/* If portENTER_CRITICAL is not defined then including deprecated_definitions.h\n * did not result in a portmacro.h header file being included - and it should be\n * included here.  In this case the path to the correct portmacro.h header file\n * must be set in the compiler's include path. */\n#ifndef portENTER_CRITICAL\n    #include \"portmacro.h\"\n#endif\n\n#if portBYTE_ALIGNMENT == 32\n    #define portBYTE_ALIGNMENT_MASK    ( 0x001f )\n#elif portBYTE_ALIGNMENT == 16\n    #define portBYTE_ALIGNMENT_MASK    ( 0x000f )\n#elif portBYTE_ALIGNMENT == 8\n    #define portBYTE_ALIGNMENT_MASK    ( 0x0007 )\n#elif portBYTE_ALIGNMENT == 4\n    #define portBYTE_ALIGNMENT_MASK    ( 0x0003 )\n#elif portBYTE_ALIGNMENT == 2\n    #define portBYTE_ALIGNMENT_MASK    ( 0x0001 )\n#elif portBYTE_ALIGNMENT == 1\n    #define portBYTE_ALIGNMENT_MASK    ( 0x0000 )\n#else /* if portBYTE_ALIGNMENT == 32 */\n    #error \"Invalid portBYTE_ALIGNMENT definition\"\n#endif /* if portBYTE_ALIGNMENT == 32 */\n\n#ifndef portUSING_MPU_WRAPPERS\n    #define portUSING_MPU_WRAPPERS    0\n#endif\n\n#ifndef portNUM_CONFIGURABLE_REGIONS\n    #define portNUM_CONFIGURABLE_REGIONS    1\n#endif\n\n#ifndef portHAS_STACK_OVERFLOW_CHECKING\n    #define portHAS_STACK_OVERFLOW_CHECKING    0\n#endif\n\n#ifndef portARCH_NAME\n    #define portARCH_NAME    NULL\n#endif\n\n#ifndef configSTACK_ALLOCATION_FROM_SEPARATE_HEAP\n    /* Defaults to 0 for backward compatibility. */\n    #define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP    0\n#endif\n\n/* *INDENT-OFF* */\n#ifdef __cplusplus\n    extern \"C\" {\n#endif\n/* *INDENT-ON* */\n\n#include \"mpu_wrappers.h\"\n\n/*\n * Setup the stack of a new task so it is ready to be placed under the\n * scheduler control.  The registers have to be placed on the stack in\n * the order that the port expects to find them.\n *\n */\n#if ( portUSING_MPU_WRAPPERS == 1 )\n    #if ( portHAS_STACK_OVERFLOW_CHECKING == 1 )\n        StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,\n                                             StackType_t * pxEndOfStack,\n                                             TaskFunction_t pxCode,\n                                             void * pvParameters,\n                                             BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION;\n    #else\n        StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,\n                                             TaskFunction_t pxCode,\n                                             void * pvParameters,\n                                             BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION;\n    #endif\n#else /* if ( portUSING_MPU_WRAPPERS == 1 ) */\n    #if ( portHAS_STACK_OVERFLOW_CHECKING == 1 )\n        StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,\n                                             StackType_t * pxEndOfStack,\n                                             TaskFunction_t pxCode,\n                                             void * pvParameters ) PRIVILEGED_FUNCTION;\n    #else\n        StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,\n                                             TaskFunction_t pxCode,\n                                             void * pvParameters ) PRIVILEGED_FUNCTION;\n    #endif\n#endif /* if ( portUSING_MPU_WRAPPERS == 1 ) */\n\n/* Used by heap_5.c to define the start address and size of each memory region\n * that together comprise the total FreeRTOS heap space. */\ntypedef struct HeapRegion\n{\n    uint8_t * pucStartAddress;\n    size_t xSizeInBytes;\n} HeapRegion_t;\n\n/* Used to pass information about the heap out of vPortGetHeapStats(). */\ntypedef struct xHeapStats\n{\n    size_t xAvailableHeapSpaceInBytes;      /* The total heap size currently available - this is the sum of all the free blocks, not the largest block that can be allocated. */\n    size_t xSizeOfLargestFreeBlockInBytes;  /* The maximum size, in bytes, of all the free blocks within the heap at the time vPortGetHeapStats() is called. */\n    size_t xSizeOfSmallestFreeBlockInBytes; /* The minimum size, in bytes, of all the free blocks within the heap at the time vPortGetHeapStats() is called. */\n    size_t xNumberOfFreeBlocks;             /* The number of free memory blocks within the heap at the time vPortGetHeapStats() is called. */\n    size_t xMinimumEverFreeBytesRemaining;  /* The minimum amount of total free memory (sum of all free blocks) there has been in the heap since the system booted. */\n    size_t xNumberOfSuccessfulAllocations;  /* The number of calls to pvPortMalloc() that have returned a valid memory block. */\n    size_t xNumberOfSuccessfulFrees;        /* The number of calls to vPortFree() that has successfully freed a block of memory. */\n} HeapStats_t;\n\n/*\n * Used to define multiple heap regions for use by heap_5.c.  This function\n * must be called before any calls to pvPortMalloc() - not creating a task,\n * queue, semaphore, mutex, software timer, event group, etc. will result in\n * pvPortMalloc being called.\n *\n * pxHeapRegions passes in an array of HeapRegion_t structures - each of which\n * defines a region of memory that can be used as the heap.  The array is\n * terminated by a HeapRegions_t structure that has a size of 0.  The region\n * with the lowest start address must appear first in the array.\n */\nvoid vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions ) PRIVILEGED_FUNCTION;\n\n/*\n * Returns a HeapStats_t structure filled with information about the current\n * heap state.\n */\nvoid vPortGetHeapStats( HeapStats_t * pxHeapStats );\n\n/*\n * Map to the memory management routines required for the port.\n */\nvoid * pvPortMalloc( size_t xSize ) PRIVILEGED_FUNCTION;\nvoid * pvPortCalloc( size_t xNum,\n                     size_t xSize ) PRIVILEGED_FUNCTION;\nvoid vPortFree( void * pv ) PRIVILEGED_FUNCTION;\nvoid vPortInitialiseBlocks( void ) PRIVILEGED_FUNCTION;\nsize_t xPortGetFreeHeapSize( void ) PRIVILEGED_FUNCTION;\nsize_t xPortGetMinimumEverFreeHeapSize( void ) PRIVILEGED_FUNCTION;\n\n#if ( configSTACK_ALLOCATION_FROM_SEPARATE_HEAP == 1 )\n    void * pvPortMallocStack( size_t xSize ) PRIVILEGED_FUNCTION;\n    void vPortFreeStack( void * pv ) PRIVILEGED_FUNCTION;\n#else\n    #define pvPortMallocStack    pvPortMalloc\n    #define vPortFreeStack       vPortFree\n#endif\n\n#if ( configUSE_MALLOC_FAILED_HOOK == 1 )\n\n/**\n * task.h\n * @code{c}\n * void vApplicationMallocFailedHook( void )\n * @endcode\n *\n * This hook function is called when allocation failed.\n */\n    void vApplicationMallocFailedHook( void ); /*lint !e526 Symbol not defined as it is an application callback. */\n#endif\n\n/*\n * Setup the hardware ready for the scheduler to take control.  This generally\n * sets up a tick interrupt and sets timers for the correct tick frequency.\n */\nBaseType_t xPortStartScheduler( void ) PRIVILEGED_FUNCTION;\n\n/*\n * Undo any hardware/ISR setup that was performed by xPortStartScheduler() so\n * the hardware is left in its original condition after the scheduler stops\n * executing.\n */\nvoid vPortEndScheduler( void ) PRIVILEGED_FUNCTION;\n\n/*\n * The structures and methods of manipulating the MPU are contained within the\n * port layer.\n *\n * Fills the xMPUSettings structure with the memory region information\n * contained in xRegions.\n */\n#if ( portUSING_MPU_WRAPPERS == 1 )\n    struct xMEMORY_REGION;\n    void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,\n                                    const struct xMEMORY_REGION * const xRegions,\n                                    StackType_t * pxBottomOfStack,\n                                    uint32_t ulStackDepth ) PRIVILEGED_FUNCTION;\n#endif\n\n/* *INDENT-OFF* */\n#ifdef __cplusplus\n    }\n#endif\n/* *INDENT-ON* */\n\n#endif /* PORTABLE_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/include/projdefs.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef PROJDEFS_H\n#define PROJDEFS_H\n\n/*\n * Defines the prototype to which task functions must conform.  Defined in this\n * file to ensure the type is known before portable.h is included.\n */\ntypedef void (* TaskFunction_t)( void * );\n\n/* Converts a time in milliseconds to a time in ticks.  This macro can be\n * overridden by a macro of the same name defined in FreeRTOSConfig.h in case the\n * definition here is not suitable for your application. */\n#ifndef pdMS_TO_TICKS\n    #define pdMS_TO_TICKS( xTimeInMs )    ( ( TickType_t ) ( ( ( TickType_t ) ( xTimeInMs ) * ( TickType_t ) configTICK_RATE_HZ ) / ( TickType_t ) 1000U ) )\n#endif\n\n#define pdFALSE                                  ( ( BaseType_t ) 0 )\n#define pdTRUE                                   ( ( BaseType_t ) 1 )\n\n#define pdPASS                                   ( pdTRUE )\n#define pdFAIL                                   ( pdFALSE )\n#define errQUEUE_EMPTY                           ( ( BaseType_t ) 0 )\n#define errQUEUE_FULL                            ( ( BaseType_t ) 0 )\n\n/* FreeRTOS error definitions. */\n#define errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY    ( -1 )\n#define errQUEUE_BLOCKED                         ( -4 )\n#define errQUEUE_YIELD                           ( -5 )\n\n/* Macros used for basic data corruption checks. */\n#ifndef configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES\n    #define configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES    0\n#endif\n\n#if ( configUSE_16_BIT_TICKS == 1 )\n    #define pdINTEGRITY_CHECK_VALUE    0x5a5a\n#else\n    #define pdINTEGRITY_CHECK_VALUE    0x5a5a5a5aUL\n#endif\n\n/* The following errno values are used by FreeRTOS+ components, not FreeRTOS\n * itself. */\n#define pdFREERTOS_ERRNO_NONE             0   /* No errors */\n#define pdFREERTOS_ERRNO_ENOENT           2   /* No such file or directory */\n#define pdFREERTOS_ERRNO_EINTR            4   /* Interrupted system call */\n#define pdFREERTOS_ERRNO_EIO              5   /* I/O error */\n#define pdFREERTOS_ERRNO_ENXIO            6   /* No such device or address */\n#define pdFREERTOS_ERRNO_EBADF            9   /* Bad file number */\n#define pdFREERTOS_ERRNO_EAGAIN           11  /* No more processes */\n#define pdFREERTOS_ERRNO_EWOULDBLOCK      11  /* Operation would block */\n#define pdFREERTOS_ERRNO_ENOMEM           12  /* Not enough memory */\n#define pdFREERTOS_ERRNO_EACCES           13  /* Permission denied */\n#define pdFREERTOS_ERRNO_EFAULT           14  /* Bad address */\n#define pdFREERTOS_ERRNO_EBUSY            16  /* Mount device busy */\n#define pdFREERTOS_ERRNO_EEXIST           17  /* File exists */\n#define pdFREERTOS_ERRNO_EXDEV            18  /* Cross-device link */\n#define pdFREERTOS_ERRNO_ENODEV           19  /* No such device */\n#define pdFREERTOS_ERRNO_ENOTDIR          20  /* Not a directory */\n#define pdFREERTOS_ERRNO_EISDIR           21  /* Is a directory */\n#define pdFREERTOS_ERRNO_EINVAL           22  /* Invalid argument */\n#define pdFREERTOS_ERRNO_ENOSPC           28  /* No space left on device */\n#define pdFREERTOS_ERRNO_ESPIPE           29  /* Illegal seek */\n#define pdFREERTOS_ERRNO_EROFS            30  /* Read only file system */\n#define pdFREERTOS_ERRNO_EUNATCH          42  /* Protocol driver not attached */\n#define pdFREERTOS_ERRNO_EBADE            50  /* Invalid exchange */\n#define pdFREERTOS_ERRNO_EFTYPE           79  /* Inappropriate file type or format */\n#define pdFREERTOS_ERRNO_ENMFILE          89  /* No more files */\n#define pdFREERTOS_ERRNO_ENOTEMPTY        90  /* Directory not empty */\n#define pdFREERTOS_ERRNO_ENAMETOOLONG     91  /* File or path name too long */\n#define pdFREERTOS_ERRNO_EOPNOTSUPP       95  /* Operation not supported on transport endpoint */\n#define pdFREERTOS_ERRNO_ENOBUFS          105 /* No buffer space available */\n#define pdFREERTOS_ERRNO_ENOPROTOOPT      109 /* Protocol not available */\n#define pdFREERTOS_ERRNO_EADDRINUSE       112 /* Address already in use */\n#define pdFREERTOS_ERRNO_ETIMEDOUT        116 /* Connection timed out */\n#define pdFREERTOS_ERRNO_EINPROGRESS      119 /* Connection already in progress */\n#define pdFREERTOS_ERRNO_EALREADY         120 /* Socket already connected */\n#define pdFREERTOS_ERRNO_EADDRNOTAVAIL    125 /* Address not available */\n#define pdFREERTOS_ERRNO_EISCONN          127 /* Socket is already connected */\n#define pdFREERTOS_ERRNO_ENOTCONN         128 /* Socket is not connected */\n#define pdFREERTOS_ERRNO_ENOMEDIUM        135 /* No medium inserted */\n#define pdFREERTOS_ERRNO_EILSEQ           138 /* An invalid UTF-16 sequence was encountered. */\n#define pdFREERTOS_ERRNO_ECANCELED        140 /* Operation canceled. */\n\n/* The following endian values are used by FreeRTOS+ components, not FreeRTOS\n * itself. */\n#define pdFREERTOS_LITTLE_ENDIAN          0\n#define pdFREERTOS_BIG_ENDIAN             1\n\n/* Re-defining endian values for generic naming. */\n#define pdLITTLE_ENDIAN                   pdFREERTOS_LITTLE_ENDIAN\n#define pdBIG_ENDIAN                      pdFREERTOS_BIG_ENDIAN\n\n\n#endif /* PROJDEFS_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/include/queue.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n\n#ifndef QUEUE_H\n#define QUEUE_H\n\n#ifndef INC_FREERTOS_H\n    #error \"include FreeRTOS.h\" must appear in source files before \"include queue.h\"\n#endif\n\n/* *INDENT-OFF* */\n#ifdef __cplusplus\n    extern \"C\" {\n#endif\n/* *INDENT-ON* */\n\n#include \"task.h\"\n\n/**\n * Type by which queues are referenced.  For example, a call to xQueueCreate()\n * returns an QueueHandle_t variable that can then be used as a parameter to\n * xQueueSend(), xQueueReceive(), etc.\n */\nstruct QueueDefinition; /* Using old naming convention so as not to break kernel aware debuggers. */\ntypedef struct QueueDefinition   * QueueHandle_t;\n\n/**\n * Type by which queue sets are referenced.  For example, a call to\n * xQueueCreateSet() returns an xQueueSet variable that can then be used as a\n * parameter to xQueueSelectFromSet(), xQueueAddToSet(), etc.\n */\ntypedef struct QueueDefinition   * QueueSetHandle_t;\n\n/**\n * Queue sets can contain both queues and semaphores, so the\n * QueueSetMemberHandle_t is defined as a type to be used where a parameter or\n * return value can be either an QueueHandle_t or an SemaphoreHandle_t.\n */\ntypedef struct QueueDefinition   * QueueSetMemberHandle_t;\n\n/* For internal use only. */\n#define queueSEND_TO_BACK                     ( ( BaseType_t ) 0 )\n#define queueSEND_TO_FRONT                    ( ( BaseType_t ) 1 )\n#define queueOVERWRITE                        ( ( BaseType_t ) 2 )\n\n/* For internal use only.  These definitions *must* match those in queue.c. */\n#define queueQUEUE_TYPE_BASE                  ( ( uint8_t ) 0U )\n#define queueQUEUE_TYPE_SET                   ( ( uint8_t ) 0U )\n#define queueQUEUE_TYPE_MUTEX                 ( ( uint8_t ) 1U )\n#define queueQUEUE_TYPE_COUNTING_SEMAPHORE    ( ( uint8_t ) 2U )\n#define queueQUEUE_TYPE_BINARY_SEMAPHORE      ( ( uint8_t ) 3U )\n#define queueQUEUE_TYPE_RECURSIVE_MUTEX       ( ( uint8_t ) 4U )\n\n/**\n * queue. h\n * @code{c}\n * QueueHandle_t xQueueCreate(\n *                            UBaseType_t uxQueueLength,\n *                            UBaseType_t uxItemSize\n *                        );\n * @endcode\n *\n * Creates a new queue instance, and returns a handle by which the new queue\n * can be referenced.\n *\n * Internally, within the FreeRTOS implementation, queues use two blocks of\n * memory.  The first block is used to hold the queue's data structures.  The\n * second block is used to hold items placed into the queue.  If a queue is\n * created using xQueueCreate() then both blocks of memory are automatically\n * dynamically allocated inside the xQueueCreate() function.  (see\n * https://www.FreeRTOS.org/a00111.html).  If a queue is created using\n * xQueueCreateStatic() then the application writer must provide the memory that\n * will get used by the queue.  xQueueCreateStatic() therefore allows a queue to\n * be created without using any dynamic memory allocation.\n *\n * https://www.FreeRTOS.org/Embedded-RTOS-Queues.html\n *\n * @param uxQueueLength The maximum number of items that the queue can contain.\n *\n * @param uxItemSize The number of bytes each item in the queue will require.\n * Items are queued by copy, not by reference, so this is the number of bytes\n * that will be copied for each posted item.  Each item on the queue must be\n * the same size.\n *\n * @return If the queue is successfully create then a handle to the newly\n * created queue is returned.  If the queue cannot be created then 0 is\n * returned.\n *\n * Example usage:\n * @code{c}\n * struct AMessage\n * {\n *  char ucMessageID;\n *  char ucData[ 20 ];\n * };\n *\n * void vATask( void *pvParameters )\n * {\n * QueueHandle_t xQueue1, xQueue2;\n *\n *  // Create a queue capable of containing 10 uint32_t values.\n *  xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );\n *  if( xQueue1 == 0 )\n *  {\n *      // Queue was not created and must not be used.\n *  }\n *\n *  // Create a queue capable of containing 10 pointers to AMessage structures.\n *  // These should be passed by pointer as they contain a lot of data.\n *  xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );\n *  if( xQueue2 == 0 )\n *  {\n *      // Queue was not created and must not be used.\n *  }\n *\n *  // ... Rest of task code.\n * }\n * @endcode\n * \\defgroup xQueueCreate xQueueCreate\n * \\ingroup QueueManagement\n */\n#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n    #define xQueueCreate( uxQueueLength, uxItemSize )    xQueueGenericCreate( ( uxQueueLength ), ( uxItemSize ), ( queueQUEUE_TYPE_BASE ) )\n#endif\n\n/**\n * queue. h\n * @code{c}\n * QueueHandle_t xQueueCreateStatic(\n *                            UBaseType_t uxQueueLength,\n *                            UBaseType_t uxItemSize,\n *                            uint8_t *pucQueueStorage,\n *                            StaticQueue_t *pxQueueBuffer\n *                        );\n * @endcode\n *\n * Creates a new queue instance, and returns a handle by which the new queue\n * can be referenced.\n *\n * Internally, within the FreeRTOS implementation, queues use two blocks of\n * memory.  The first block is used to hold the queue's data structures.  The\n * second block is used to hold items placed into the queue.  If a queue is\n * created using xQueueCreate() then both blocks of memory are automatically\n * dynamically allocated inside the xQueueCreate() function.  (see\n * https://www.FreeRTOS.org/a00111.html).  If a queue is created using\n * xQueueCreateStatic() then the application writer must provide the memory that\n * will get used by the queue.  xQueueCreateStatic() therefore allows a queue to\n * be created without using any dynamic memory allocation.\n *\n * https://www.FreeRTOS.org/Embedded-RTOS-Queues.html\n *\n * @param uxQueueLength The maximum number of items that the queue can contain.\n *\n * @param uxItemSize The number of bytes each item in the queue will require.\n * Items are queued by copy, not by reference, so this is the number of bytes\n * that will be copied for each posted item.  Each item on the queue must be\n * the same size.\n *\n * @param pucQueueStorage If uxItemSize is not zero then\n * pucQueueStorage must point to a uint8_t array that is at least large\n * enough to hold the maximum number of items that can be in the queue at any\n * one time - which is ( uxQueueLength * uxItemsSize ) bytes.  If uxItemSize is\n * zero then pucQueueStorage can be NULL.\n *\n * @param pxQueueBuffer Must point to a variable of type StaticQueue_t, which\n * will be used to hold the queue's data structure.\n *\n * @return If the queue is created then a handle to the created queue is\n * returned.  If pxQueueBuffer is NULL then NULL is returned.\n *\n * Example usage:\n * @code{c}\n * struct AMessage\n * {\n *  char ucMessageID;\n *  char ucData[ 20 ];\n * };\n *\n #define QUEUE_LENGTH 10\n #define ITEM_SIZE sizeof( uint32_t )\n *\n * // xQueueBuffer will hold the queue structure.\n * StaticQueue_t xQueueBuffer;\n *\n * // ucQueueStorage will hold the items posted to the queue.  Must be at least\n * // [(queue length) * ( queue item size)] bytes long.\n * uint8_t ucQueueStorage[ QUEUE_LENGTH * ITEM_SIZE ];\n *\n * void vATask( void *pvParameters )\n * {\n *  QueueHandle_t xQueue1;\n *\n *  // Create a queue capable of containing 10 uint32_t values.\n *  xQueue1 = xQueueCreate( QUEUE_LENGTH, // The number of items the queue can hold.\n *                          ITEM_SIZE     // The size of each item in the queue\n *                          &( ucQueueStorage[ 0 ] ), // The buffer that will hold the items in the queue.\n *                          &xQueueBuffer ); // The buffer that will hold the queue structure.\n *\n *  // The queue is guaranteed to be created successfully as no dynamic memory\n *  // allocation is used.  Therefore xQueue1 is now a handle to a valid queue.\n *\n *  // ... Rest of task code.\n * }\n * @endcode\n * \\defgroup xQueueCreateStatic xQueueCreateStatic\n * \\ingroup QueueManagement\n */\n#if ( configSUPPORT_STATIC_ALLOCATION == 1 )\n    #define xQueueCreateStatic( uxQueueLength, uxItemSize, pucQueueStorage, pxQueueBuffer )    xQueueGenericCreateStatic( ( uxQueueLength ), ( uxItemSize ), ( pucQueueStorage ), ( pxQueueBuffer ), ( queueQUEUE_TYPE_BASE ) )\n#endif /* configSUPPORT_STATIC_ALLOCATION */\n\n/**\n * queue. h\n * @code{c}\n * BaseType_t xQueueSendToToFront(\n *                                 QueueHandle_t    xQueue,\n *                                 const void       *pvItemToQueue,\n *                                 TickType_t       xTicksToWait\n *                             );\n * @endcode\n *\n * Post an item to the front of a queue.  The item is queued by copy, not by\n * reference.  This function must not be called from an interrupt service\n * routine.  See xQueueSendFromISR () for an alternative which may be used\n * in an ISR.\n *\n * @param xQueue The handle to the queue on which the item is to be posted.\n *\n * @param pvItemToQueue A pointer to the item that is to be placed on the\n * queue.  The size of the items the queue will hold was defined when the\n * queue was created, so this many bytes will be copied from pvItemToQueue\n * into the queue storage area.\n *\n * @param xTicksToWait The maximum amount of time the task should block\n * waiting for space to become available on the queue, should it already\n * be full.  The call will return immediately if this is set to 0 and the\n * queue is full.  The time is defined in tick periods so the constant\n * portTICK_PERIOD_MS should be used to convert to real time if this is required.\n *\n * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.\n *\n * Example usage:\n * @code{c}\n * struct AMessage\n * {\n *  char ucMessageID;\n *  char ucData[ 20 ];\n * } xMessage;\n *\n * uint32_t ulVar = 10UL;\n *\n * void vATask( void *pvParameters )\n * {\n * QueueHandle_t xQueue1, xQueue2;\n * struct AMessage *pxMessage;\n *\n *  // Create a queue capable of containing 10 uint32_t values.\n *  xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );\n *\n *  // Create a queue capable of containing 10 pointers to AMessage structures.\n *  // These should be passed by pointer as they contain a lot of data.\n *  xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );\n *\n *  // ...\n *\n *  if( xQueue1 != 0 )\n *  {\n *      // Send an uint32_t.  Wait for 10 ticks for space to become\n *      // available if necessary.\n *      if( xQueueSendToFront( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )\n *      {\n *          // Failed to post the message, even after 10 ticks.\n *      }\n *  }\n *\n *  if( xQueue2 != 0 )\n *  {\n *      // Send a pointer to a struct AMessage object.  Don't block if the\n *      // queue is already full.\n *      pxMessage = & xMessage;\n *      xQueueSendToFront( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );\n *  }\n *\n *  // ... Rest of task code.\n * }\n * @endcode\n * \\defgroup xQueueSend xQueueSend\n * \\ingroup QueueManagement\n */\n#define xQueueSendToFront( xQueue, pvItemToQueue, xTicksToWait ) \\\n    xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_FRONT )\n\n/**\n * queue. h\n * @code{c}\n * BaseType_t xQueueSendToBack(\n *                                 QueueHandle_t    xQueue,\n *                                 const void       *pvItemToQueue,\n *                                 TickType_t       xTicksToWait\n *                             );\n * @endcode\n *\n * This is a macro that calls xQueueGenericSend().\n *\n * Post an item to the back of a queue.  The item is queued by copy, not by\n * reference.  This function must not be called from an interrupt service\n * routine.  See xQueueSendFromISR () for an alternative which may be used\n * in an ISR.\n *\n * @param xQueue The handle to the queue on which the item is to be posted.\n *\n * @param pvItemToQueue A pointer to the item that is to be placed on the\n * queue.  The size of the items the queue will hold was defined when the\n * queue was created, so this many bytes will be copied from pvItemToQueue\n * into the queue storage area.\n *\n * @param xTicksToWait The maximum amount of time the task should block\n * waiting for space to become available on the queue, should it already\n * be full.  The call will return immediately if this is set to 0 and the queue\n * is full.  The  time is defined in tick periods so the constant\n * portTICK_PERIOD_MS should be used to convert to real time if this is required.\n *\n * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.\n *\n * Example usage:\n * @code{c}\n * struct AMessage\n * {\n *  char ucMessageID;\n *  char ucData[ 20 ];\n * } xMessage;\n *\n * uint32_t ulVar = 10UL;\n *\n * void vATask( void *pvParameters )\n * {\n * QueueHandle_t xQueue1, xQueue2;\n * struct AMessage *pxMessage;\n *\n *  // Create a queue capable of containing 10 uint32_t values.\n *  xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );\n *\n *  // Create a queue capable of containing 10 pointers to AMessage structures.\n *  // These should be passed by pointer as they contain a lot of data.\n *  xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );\n *\n *  // ...\n *\n *  if( xQueue1 != 0 )\n *  {\n *      // Send an uint32_t.  Wait for 10 ticks for space to become\n *      // available if necessary.\n *      if( xQueueSendToBack( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )\n *      {\n *          // Failed to post the message, even after 10 ticks.\n *      }\n *  }\n *\n *  if( xQueue2 != 0 )\n *  {\n *      // Send a pointer to a struct AMessage object.  Don't block if the\n *      // queue is already full.\n *      pxMessage = & xMessage;\n *      xQueueSendToBack( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );\n *  }\n *\n *  // ... Rest of task code.\n * }\n * @endcode\n * \\defgroup xQueueSend xQueueSend\n * \\ingroup QueueManagement\n */\n#define xQueueSendToBack( xQueue, pvItemToQueue, xTicksToWait ) \\\n    xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )\n\n/**\n * queue. h\n * @code{c}\n * BaseType_t xQueueSend(\n *                            QueueHandle_t xQueue,\n *                            const void * pvItemToQueue,\n *                            TickType_t xTicksToWait\n *                       );\n * @endcode\n *\n * This is a macro that calls xQueueGenericSend().  It is included for\n * backward compatibility with versions of FreeRTOS.org that did not\n * include the xQueueSendToFront() and xQueueSendToBack() macros.  It is\n * equivalent to xQueueSendToBack().\n *\n * Post an item on a queue.  The item is queued by copy, not by reference.\n * This function must not be called from an interrupt service routine.\n * See xQueueSendFromISR () for an alternative which may be used in an ISR.\n *\n * @param xQueue The handle to the queue on which the item is to be posted.\n *\n * @param pvItemToQueue A pointer to the item that is to be placed on the\n * queue.  The size of the items the queue will hold was defined when the\n * queue was created, so this many bytes will be copied from pvItemToQueue\n * into the queue storage area.\n *\n * @param xTicksToWait The maximum amount of time the task should block\n * waiting for space to become available on the queue, should it already\n * be full.  The call will return immediately if this is set to 0 and the\n * queue is full.  The time is defined in tick periods so the constant\n * portTICK_PERIOD_MS should be used to convert to real time if this is required.\n *\n * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.\n *\n * Example usage:\n * @code{c}\n * struct AMessage\n * {\n *  char ucMessageID;\n *  char ucData[ 20 ];\n * } xMessage;\n *\n * uint32_t ulVar = 10UL;\n *\n * void vATask( void *pvParameters )\n * {\n * QueueHandle_t xQueue1, xQueue2;\n * struct AMessage *pxMessage;\n *\n *  // Create a queue capable of containing 10 uint32_t values.\n *  xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );\n *\n *  // Create a queue capable of containing 10 pointers to AMessage structures.\n *  // These should be passed by pointer as they contain a lot of data.\n *  xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );\n *\n *  // ...\n *\n *  if( xQueue1 != 0 )\n *  {\n *      // Send an uint32_t.  Wait for 10 ticks for space to become\n *      // available if necessary.\n *      if( xQueueSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )\n *      {\n *          // Failed to post the message, even after 10 ticks.\n *      }\n *  }\n *\n *  if( xQueue2 != 0 )\n *  {\n *      // Send a pointer to a struct AMessage object.  Don't block if the\n *      // queue is already full.\n *      pxMessage = & xMessage;\n *      xQueueSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );\n *  }\n *\n *  // ... Rest of task code.\n * }\n * @endcode\n * \\defgroup xQueueSend xQueueSend\n * \\ingroup QueueManagement\n */\n#define xQueueSend( xQueue, pvItemToQueue, xTicksToWait ) \\\n    xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )\n\n/**\n * queue. h\n * @code{c}\n * BaseType_t xQueueOverwrite(\n *                            QueueHandle_t xQueue,\n *                            const void * pvItemToQueue\n *                       );\n * @endcode\n *\n * Only for use with queues that have a length of one - so the queue is either\n * empty or full.\n *\n * Post an item on a queue.  If the queue is already full then overwrite the\n * value held in the queue.  The item is queued by copy, not by reference.\n *\n * This function must not be called from an interrupt service routine.\n * See xQueueOverwriteFromISR () for an alternative which may be used in an ISR.\n *\n * @param xQueue The handle of the queue to which the data is being sent.\n *\n * @param pvItemToQueue A pointer to the item that is to be placed on the\n * queue.  The size of the items the queue will hold was defined when the\n * queue was created, so this many bytes will be copied from pvItemToQueue\n * into the queue storage area.\n *\n * @return xQueueOverwrite() is a macro that calls xQueueGenericSend(), and\n * therefore has the same return values as xQueueSendToFront().  However, pdPASS\n * is the only value that can be returned because xQueueOverwrite() will write\n * to the queue even when the queue is already full.\n *\n * Example usage:\n * @code{c}\n *\n * void vFunction( void *pvParameters )\n * {\n * QueueHandle_t xQueue;\n * uint32_t ulVarToSend, ulValReceived;\n *\n *  // Create a queue to hold one uint32_t value.  It is strongly\n *  // recommended *not* to use xQueueOverwrite() on queues that can\n *  // contain more than one value, and doing so will trigger an assertion\n *  // if configASSERT() is defined.\n *  xQueue = xQueueCreate( 1, sizeof( uint32_t ) );\n *\n *  // Write the value 10 to the queue using xQueueOverwrite().\n *  ulVarToSend = 10;\n *  xQueueOverwrite( xQueue, &ulVarToSend );\n *\n *  // Peeking the queue should now return 10, but leave the value 10 in\n *  // the queue.  A block time of zero is used as it is known that the\n *  // queue holds a value.\n *  ulValReceived = 0;\n *  xQueuePeek( xQueue, &ulValReceived, 0 );\n *\n *  if( ulValReceived != 10 )\n *  {\n *      // Error unless the item was removed by a different task.\n *  }\n *\n *  // The queue is still full.  Use xQueueOverwrite() to overwrite the\n *  // value held in the queue with 100.\n *  ulVarToSend = 100;\n *  xQueueOverwrite( xQueue, &ulVarToSend );\n *\n *  // This time read from the queue, leaving the queue empty once more.\n *  // A block time of 0 is used again.\n *  xQueueReceive( xQueue, &ulValReceived, 0 );\n *\n *  // The value read should be the last value written, even though the\n *  // queue was already full when the value was written.\n *  if( ulValReceived != 100 )\n *  {\n *      // Error!\n *  }\n *\n *  // ...\n * }\n * @endcode\n * \\defgroup xQueueOverwrite xQueueOverwrite\n * \\ingroup QueueManagement\n */\n#define xQueueOverwrite( xQueue, pvItemToQueue ) \\\n    xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), 0, queueOVERWRITE )\n\n\n/**\n * queue. h\n * @code{c}\n * BaseType_t xQueueGenericSend(\n *                                  QueueHandle_t xQueue,\n *                                  const void * pvItemToQueue,\n *                                  TickType_t xTicksToWait\n *                                  BaseType_t xCopyPosition\n *                              );\n * @endcode\n *\n * It is preferred that the macros xQueueSend(), xQueueSendToFront() and\n * xQueueSendToBack() are used in place of calling this function directly.\n *\n * Post an item on a queue.  The item is queued by copy, not by reference.\n * This function must not be called from an interrupt service routine.\n * See xQueueSendFromISR () for an alternative which may be used in an ISR.\n *\n * @param xQueue The handle to the queue on which the item is to be posted.\n *\n * @param pvItemToQueue A pointer to the item that is to be placed on the\n * queue.  The size of the items the queue will hold was defined when the\n * queue was created, so this many bytes will be copied from pvItemToQueue\n * into the queue storage area.\n *\n * @param xTicksToWait The maximum amount of time the task should block\n * waiting for space to become available on the queue, should it already\n * be full.  The call will return immediately if this is set to 0 and the\n * queue is full.  The time is defined in tick periods so the constant\n * portTICK_PERIOD_MS should be used to convert to real time if this is required.\n *\n * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the\n * item at the back of the queue, or queueSEND_TO_FRONT to place the item\n * at the front of the queue (for high priority messages).\n *\n * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.\n *\n * Example usage:\n * @code{c}\n * struct AMessage\n * {\n *  char ucMessageID;\n *  char ucData[ 20 ];\n * } xMessage;\n *\n * uint32_t ulVar = 10UL;\n *\n * void vATask( void *pvParameters )\n * {\n * QueueHandle_t xQueue1, xQueue2;\n * struct AMessage *pxMessage;\n *\n *  // Create a queue capable of containing 10 uint32_t values.\n *  xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );\n *\n *  // Create a queue capable of containing 10 pointers to AMessage structures.\n *  // These should be passed by pointer as they contain a lot of data.\n *  xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );\n *\n *  // ...\n *\n *  if( xQueue1 != 0 )\n *  {\n *      // Send an uint32_t.  Wait for 10 ticks for space to become\n *      // available if necessary.\n *      if( xQueueGenericSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10, queueSEND_TO_BACK ) != pdPASS )\n *      {\n *          // Failed to post the message, even after 10 ticks.\n *      }\n *  }\n *\n *  if( xQueue2 != 0 )\n *  {\n *      // Send a pointer to a struct AMessage object.  Don't block if the\n *      // queue is already full.\n *      pxMessage = & xMessage;\n *      xQueueGenericSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0, queueSEND_TO_BACK );\n *  }\n *\n *  // ... Rest of task code.\n * }\n * @endcode\n * \\defgroup xQueueSend xQueueSend\n * \\ingroup QueueManagement\n */\nBaseType_t xQueueGenericSend( QueueHandle_t xQueue,\n                              const void * const pvItemToQueue,\n                              TickType_t xTicksToWait,\n                              const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;\n\n/**\n * queue. h\n * @code{c}\n * BaseType_t xQueuePeek(\n *                           QueueHandle_t xQueue,\n *                           void * const pvBuffer,\n *                           TickType_t xTicksToWait\n *                       );\n * @endcode\n *\n * Receive an item from a queue without removing the item from the queue.\n * The item is received by copy so a buffer of adequate size must be\n * provided.  The number of bytes copied into the buffer was defined when\n * the queue was created.\n *\n * Successfully received items remain on the queue so will be returned again\n * by the next call, or a call to xQueueReceive().\n *\n * This macro must not be used in an interrupt service routine.  See\n * xQueuePeekFromISR() for an alternative that can be called from an interrupt\n * service routine.\n *\n * @param xQueue The handle to the queue from which the item is to be\n * received.\n *\n * @param pvBuffer Pointer to the buffer into which the received item will\n * be copied.\n *\n * @param xTicksToWait The maximum amount of time the task should block\n * waiting for an item to receive should the queue be empty at the time\n * of the call. The time is defined in tick periods so the constant\n * portTICK_PERIOD_MS should be used to convert to real time if this is required.\n * xQueuePeek() will return immediately if xTicksToWait is 0 and the queue\n * is empty.\n *\n * @return pdTRUE if an item was successfully received from the queue,\n * otherwise pdFALSE.\n *\n * Example usage:\n * @code{c}\n * struct AMessage\n * {\n *  char ucMessageID;\n *  char ucData[ 20 ];\n * } xMessage;\n *\n * QueueHandle_t xQueue;\n *\n * // Task to create a queue and post a value.\n * void vATask( void *pvParameters )\n * {\n * struct AMessage *pxMessage;\n *\n *  // Create a queue capable of containing 10 pointers to AMessage structures.\n *  // These should be passed by pointer as they contain a lot of data.\n *  xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );\n *  if( xQueue == 0 )\n *  {\n *      // Failed to create the queue.\n *  }\n *\n *  // ...\n *\n *  // Send a pointer to a struct AMessage object.  Don't block if the\n *  // queue is already full.\n *  pxMessage = & xMessage;\n *  xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );\n *\n *  // ... Rest of task code.\n * }\n *\n * // Task to peek the data from the queue.\n * void vADifferentTask( void *pvParameters )\n * {\n * struct AMessage *pxRxedMessage;\n *\n *  if( xQueue != 0 )\n *  {\n *      // Peek a message on the created queue.  Block for 10 ticks if a\n *      // message is not immediately available.\n *      if( xQueuePeek( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )\n *      {\n *          // pcRxedMessage now points to the struct AMessage variable posted\n *          // by vATask, but the item still remains on the queue.\n *      }\n *  }\n *\n *  // ... Rest of task code.\n * }\n * @endcode\n * \\defgroup xQueuePeek xQueuePeek\n * \\ingroup QueueManagement\n */\nBaseType_t xQueuePeek( QueueHandle_t xQueue,\n                       void * const pvBuffer,\n                       TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;\n\n/**\n * queue. h\n * @code{c}\n * BaseType_t xQueuePeekFromISR(\n *                                  QueueHandle_t xQueue,\n *                                  void *pvBuffer,\n *                              );\n * @endcode\n *\n * A version of xQueuePeek() that can be called from an interrupt service\n * routine (ISR).\n *\n * Receive an item from a queue without removing the item from the queue.\n * The item is received by copy so a buffer of adequate size must be\n * provided.  The number of bytes copied into the buffer was defined when\n * the queue was created.\n *\n * Successfully received items remain on the queue so will be returned again\n * by the next call, or a call to xQueueReceive().\n *\n * @param xQueue The handle to the queue from which the item is to be\n * received.\n *\n * @param pvBuffer Pointer to the buffer into which the received item will\n * be copied.\n *\n * @return pdTRUE if an item was successfully received from the queue,\n * otherwise pdFALSE.\n *\n * \\defgroup xQueuePeekFromISR xQueuePeekFromISR\n * \\ingroup QueueManagement\n */\nBaseType_t xQueuePeekFromISR( QueueHandle_t xQueue,\n                              void * const pvBuffer ) PRIVILEGED_FUNCTION;\n\n/**\n * queue. h\n * @code{c}\n * BaseType_t xQueueReceive(\n *                               QueueHandle_t xQueue,\n *                               void *pvBuffer,\n *                               TickType_t xTicksToWait\n *                          );\n * @endcode\n *\n * Receive an item from a queue.  The item is received by copy so a buffer of\n * adequate size must be provided.  The number of bytes copied into the buffer\n * was defined when the queue was created.\n *\n * Successfully received items are removed from the queue.\n *\n * This function must not be used in an interrupt service routine.  See\n * xQueueReceiveFromISR for an alternative that can.\n *\n * @param xQueue The handle to the queue from which the item is to be\n * received.\n *\n * @param pvBuffer Pointer to the buffer into which the received item will\n * be copied.\n *\n * @param xTicksToWait The maximum amount of time the task should block\n * waiting for an item to receive should the queue be empty at the time\n * of the call. xQueueReceive() will return immediately if xTicksToWait\n * is zero and the queue is empty.  The time is defined in tick periods so the\n * constant portTICK_PERIOD_MS should be used to convert to real time if this is\n * required.\n *\n * @return pdTRUE if an item was successfully received from the queue,\n * otherwise pdFALSE.\n *\n * Example usage:\n * @code{c}\n * struct AMessage\n * {\n *  char ucMessageID;\n *  char ucData[ 20 ];\n * } xMessage;\n *\n * QueueHandle_t xQueue;\n *\n * // Task to create a queue and post a value.\n * void vATask( void *pvParameters )\n * {\n * struct AMessage *pxMessage;\n *\n *  // Create a queue capable of containing 10 pointers to AMessage structures.\n *  // These should be passed by pointer as they contain a lot of data.\n *  xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );\n *  if( xQueue == 0 )\n *  {\n *      // Failed to create the queue.\n *  }\n *\n *  // ...\n *\n *  // Send a pointer to a struct AMessage object.  Don't block if the\n *  // queue is already full.\n *  pxMessage = & xMessage;\n *  xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );\n *\n *  // ... Rest of task code.\n * }\n *\n * // Task to receive from the queue.\n * void vADifferentTask( void *pvParameters )\n * {\n * struct AMessage *pxRxedMessage;\n *\n *  if( xQueue != 0 )\n *  {\n *      // Receive a message on the created queue.  Block for 10 ticks if a\n *      // message is not immediately available.\n *      if( xQueueReceive( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )\n *      {\n *          // pcRxedMessage now points to the struct AMessage variable posted\n *          // by vATask.\n *      }\n *  }\n *\n *  // ... Rest of task code.\n * }\n * @endcode\n * \\defgroup xQueueReceive xQueueReceive\n * \\ingroup QueueManagement\n */\nBaseType_t xQueueReceive( QueueHandle_t xQueue,\n                          void * const pvBuffer,\n                          TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;\n\n/**\n * queue. h\n * @code{c}\n * UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue );\n * @endcode\n *\n * Return the number of messages stored in a queue.\n *\n * @param xQueue A handle to the queue being queried.\n *\n * @return The number of messages available in the queue.\n *\n * \\defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting\n * \\ingroup QueueManagement\n */\nUBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;\n\n/**\n * queue. h\n * @code{c}\n * UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue );\n * @endcode\n *\n * Return the number of free spaces available in a queue.  This is equal to the\n * number of items that can be sent to the queue before the queue becomes full\n * if no items are removed.\n *\n * @param xQueue A handle to the queue being queried.\n *\n * @return The number of spaces available in the queue.\n *\n * \\defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting\n * \\ingroup QueueManagement\n */\nUBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;\n\n/**\n * queue. h\n * @code{c}\n * void vQueueDelete( QueueHandle_t xQueue );\n * @endcode\n *\n * Delete a queue - freeing all the memory allocated for storing of items\n * placed on the queue.\n *\n * @param xQueue A handle to the queue to be deleted.\n *\n * \\defgroup vQueueDelete vQueueDelete\n * \\ingroup QueueManagement\n */\nvoid vQueueDelete( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;\n\n/**\n * queue. h\n * @code{c}\n * BaseType_t xQueueSendToFrontFromISR(\n *                                       QueueHandle_t xQueue,\n *                                       const void *pvItemToQueue,\n *                                       BaseType_t *pxHigherPriorityTaskWoken\n *                                    );\n * @endcode\n *\n * This is a macro that calls xQueueGenericSendFromISR().\n *\n * Post an item to the front of a queue.  It is safe to use this macro from\n * within an interrupt service routine.\n *\n * Items are queued by copy not reference so it is preferable to only\n * queue small items, especially when called from an ISR.  In most cases\n * it would be preferable to store a pointer to the item being queued.\n *\n * @param xQueue The handle to the queue on which the item is to be posted.\n *\n * @param pvItemToQueue A pointer to the item that is to be placed on the\n * queue.  The size of the items the queue will hold was defined when the\n * queue was created, so this many bytes will be copied from pvItemToQueue\n * into the queue storage area.\n *\n * @param pxHigherPriorityTaskWoken xQueueSendToFrontFromISR() will set\n * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task\n * to unblock, and the unblocked task has a priority higher than the currently\n * running task.  If xQueueSendToFromFromISR() sets this value to pdTRUE then\n * a context switch should be requested before the interrupt is exited.\n *\n * @return pdTRUE if the data was successfully sent to the queue, otherwise\n * errQUEUE_FULL.\n *\n * Example usage for buffered IO (where the ISR can obtain more than one value\n * per call):\n * @code{c}\n * void vBufferISR( void )\n * {\n * char cIn;\n * BaseType_t xHigherPriorityTaskWoken;\n *\n *  // We have not woken a task at the start of the ISR.\n *  xHigherPriorityTaskWoken = pdFALSE;\n *\n *  // Loop until the buffer is empty.\n *  do\n *  {\n *      // Obtain a byte from the buffer.\n *      cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );\n *\n *      // Post the byte.\n *      xQueueSendToFrontFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );\n *\n *  } while( portINPUT_BYTE( BUFFER_COUNT ) );\n *\n *  // Now the buffer is empty we can switch context if necessary.\n *  if( xHigherPriorityTaskWoken )\n *  {\n *      taskYIELD ();\n *  }\n * }\n * @endcode\n *\n * \\defgroup xQueueSendFromISR xQueueSendFromISR\n * \\ingroup QueueManagement\n */\n#define xQueueSendToFrontFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) \\\n    xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_FRONT )\n\n\n/**\n * queue. h\n * @code{c}\n * BaseType_t xQueueSendToBackFromISR(\n *                                       QueueHandle_t xQueue,\n *                                       const void *pvItemToQueue,\n *                                       BaseType_t *pxHigherPriorityTaskWoken\n *                                    );\n * @endcode\n *\n * This is a macro that calls xQueueGenericSendFromISR().\n *\n * Post an item to the back of a queue.  It is safe to use this macro from\n * within an interrupt service routine.\n *\n * Items are queued by copy not reference so it is preferable to only\n * queue small items, especially when called from an ISR.  In most cases\n * it would be preferable to store a pointer to the item being queued.\n *\n * @param xQueue The handle to the queue on which the item is to be posted.\n *\n * @param pvItemToQueue A pointer to the item that is to be placed on the\n * queue.  The size of the items the queue will hold was defined when the\n * queue was created, so this many bytes will be copied from pvItemToQueue\n * into the queue storage area.\n *\n * @param pxHigherPriorityTaskWoken xQueueSendToBackFromISR() will set\n * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task\n * to unblock, and the unblocked task has a priority higher than the currently\n * running task.  If xQueueSendToBackFromISR() sets this value to pdTRUE then\n * a context switch should be requested before the interrupt is exited.\n *\n * @return pdTRUE if the data was successfully sent to the queue, otherwise\n * errQUEUE_FULL.\n *\n * Example usage for buffered IO (where the ISR can obtain more than one value\n * per call):\n * @code{c}\n * void vBufferISR( void )\n * {\n * char cIn;\n * BaseType_t xHigherPriorityTaskWoken;\n *\n *  // We have not woken a task at the start of the ISR.\n *  xHigherPriorityTaskWoken = pdFALSE;\n *\n *  // Loop until the buffer is empty.\n *  do\n *  {\n *      // Obtain a byte from the buffer.\n *      cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );\n *\n *      // Post the byte.\n *      xQueueSendToBackFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );\n *\n *  } while( portINPUT_BYTE( BUFFER_COUNT ) );\n *\n *  // Now the buffer is empty we can switch context if necessary.\n *  if( xHigherPriorityTaskWoken )\n *  {\n *      taskYIELD ();\n *  }\n * }\n * @endcode\n *\n * \\defgroup xQueueSendFromISR xQueueSendFromISR\n * \\ingroup QueueManagement\n */\n#define xQueueSendToBackFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) \\\n    xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK )\n\n/**\n * queue. h\n * @code{c}\n * BaseType_t xQueueOverwriteFromISR(\n *                            QueueHandle_t xQueue,\n *                            const void * pvItemToQueue,\n *                            BaseType_t *pxHigherPriorityTaskWoken\n *                       );\n * @endcode\n *\n * A version of xQueueOverwrite() that can be used in an interrupt service\n * routine (ISR).\n *\n * Only for use with queues that can hold a single item - so the queue is either\n * empty or full.\n *\n * Post an item on a queue.  If the queue is already full then overwrite the\n * value held in the queue.  The item is queued by copy, not by reference.\n *\n * @param xQueue The handle to the queue on which the item is to be posted.\n *\n * @param pvItemToQueue A pointer to the item that is to be placed on the\n * queue.  The size of the items the queue will hold was defined when the\n * queue was created, so this many bytes will be copied from pvItemToQueue\n * into the queue storage area.\n *\n * @param pxHigherPriorityTaskWoken xQueueOverwriteFromISR() will set\n * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task\n * to unblock, and the unblocked task has a priority higher than the currently\n * running task.  If xQueueOverwriteFromISR() sets this value to pdTRUE then\n * a context switch should be requested before the interrupt is exited.\n *\n * @return xQueueOverwriteFromISR() is a macro that calls\n * xQueueGenericSendFromISR(), and therefore has the same return values as\n * xQueueSendToFrontFromISR().  However, pdPASS is the only value that can be\n * returned because xQueueOverwriteFromISR() will write to the queue even when\n * the queue is already full.\n *\n * Example usage:\n * @code{c}\n *\n * QueueHandle_t xQueue;\n *\n * void vFunction( void *pvParameters )\n * {\n *  // Create a queue to hold one uint32_t value.  It is strongly\n *  // recommended *not* to use xQueueOverwriteFromISR() on queues that can\n *  // contain more than one value, and doing so will trigger an assertion\n *  // if configASSERT() is defined.\n *  xQueue = xQueueCreate( 1, sizeof( uint32_t ) );\n * }\n *\n * void vAnInterruptHandler( void )\n * {\n * // xHigherPriorityTaskWoken must be set to pdFALSE before it is used.\n * BaseType_t xHigherPriorityTaskWoken = pdFALSE;\n * uint32_t ulVarToSend, ulValReceived;\n *\n *  // Write the value 10 to the queue using xQueueOverwriteFromISR().\n *  ulVarToSend = 10;\n *  xQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken );\n *\n *  // The queue is full, but calling xQueueOverwriteFromISR() again will still\n *  // pass because the value held in the queue will be overwritten with the\n *  // new value.\n *  ulVarToSend = 100;\n *  xQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken );\n *\n *  // Reading from the queue will now return 100.\n *\n *  // ...\n *\n *  if( xHigherPrioritytaskWoken == pdTRUE )\n *  {\n *      // Writing to the queue caused a task to unblock and the unblocked task\n *      // has a priority higher than or equal to the priority of the currently\n *      // executing task (the task this interrupt interrupted).  Perform a context\n *      // switch so this interrupt returns directly to the unblocked task.\n *      portYIELD_FROM_ISR(); // or portEND_SWITCHING_ISR() depending on the port.\n *  }\n * }\n * @endcode\n * \\defgroup xQueueOverwriteFromISR xQueueOverwriteFromISR\n * \\ingroup QueueManagement\n */\n#define xQueueOverwriteFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) \\\n    xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueOVERWRITE )\n\n/**\n * queue. h\n * @code{c}\n * BaseType_t xQueueSendFromISR(\n *                                   QueueHandle_t xQueue,\n *                                   const void *pvItemToQueue,\n *                                   BaseType_t *pxHigherPriorityTaskWoken\n *                              );\n * @endcode\n *\n * This is a macro that calls xQueueGenericSendFromISR().  It is included\n * for backward compatibility with versions of FreeRTOS.org that did not\n * include the xQueueSendToBackFromISR() and xQueueSendToFrontFromISR()\n * macros.\n *\n * Post an item to the back of a queue.  It is safe to use this function from\n * within an interrupt service routine.\n *\n * Items are queued by copy not reference so it is preferable to only\n * queue small items, especially when called from an ISR.  In most cases\n * it would be preferable to store a pointer to the item being queued.\n *\n * @param xQueue The handle to the queue on which the item is to be posted.\n *\n * @param pvItemToQueue A pointer to the item that is to be placed on the\n * queue.  The size of the items the queue will hold was defined when the\n * queue was created, so this many bytes will be copied from pvItemToQueue\n * into the queue storage area.\n *\n * @param pxHigherPriorityTaskWoken xQueueSendFromISR() will set\n * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task\n * to unblock, and the unblocked task has a priority higher than the currently\n * running task.  If xQueueSendFromISR() sets this value to pdTRUE then\n * a context switch should be requested before the interrupt is exited.\n *\n * @return pdTRUE if the data was successfully sent to the queue, otherwise\n * errQUEUE_FULL.\n *\n * Example usage for buffered IO (where the ISR can obtain more than one value\n * per call):\n * @code{c}\n * void vBufferISR( void )\n * {\n * char cIn;\n * BaseType_t xHigherPriorityTaskWoken;\n *\n *  // We have not woken a task at the start of the ISR.\n *  xHigherPriorityTaskWoken = pdFALSE;\n *\n *  // Loop until the buffer is empty.\n *  do\n *  {\n *      // Obtain a byte from the buffer.\n *      cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );\n *\n *      // Post the byte.\n *      xQueueSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );\n *\n *  } while( portINPUT_BYTE( BUFFER_COUNT ) );\n *\n *  // Now the buffer is empty we can switch context if necessary.\n *  if( xHigherPriorityTaskWoken )\n *  {\n *      // Actual macro used here is port specific.\n *      portYIELD_FROM_ISR ();\n *  }\n * }\n * @endcode\n *\n * \\defgroup xQueueSendFromISR xQueueSendFromISR\n * \\ingroup QueueManagement\n */\n#define xQueueSendFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) \\\n    xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK )\n\n/**\n * queue. h\n * @code{c}\n * BaseType_t xQueueGenericSendFromISR(\n *                                         QueueHandle_t    xQueue,\n *                                         const    void    *pvItemToQueue,\n *                                         BaseType_t  *pxHigherPriorityTaskWoken,\n *                                         BaseType_t  xCopyPosition\n *                                     );\n * @endcode\n *\n * It is preferred that the macros xQueueSendFromISR(),\n * xQueueSendToFrontFromISR() and xQueueSendToBackFromISR() be used in place\n * of calling this function directly.  xQueueGiveFromISR() is an\n * equivalent for use by semaphores that don't actually copy any data.\n *\n * Post an item on a queue.  It is safe to use this function from within an\n * interrupt service routine.\n *\n * Items are queued by copy not reference so it is preferable to only\n * queue small items, especially when called from an ISR.  In most cases\n * it would be preferable to store a pointer to the item being queued.\n *\n * @param xQueue The handle to the queue on which the item is to be posted.\n *\n * @param pvItemToQueue A pointer to the item that is to be placed on the\n * queue.  The size of the items the queue will hold was defined when the\n * queue was created, so this many bytes will be copied from pvItemToQueue\n * into the queue storage area.\n *\n * @param pxHigherPriorityTaskWoken xQueueGenericSendFromISR() will set\n * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task\n * to unblock, and the unblocked task has a priority higher than the currently\n * running task.  If xQueueGenericSendFromISR() sets this value to pdTRUE then\n * a context switch should be requested before the interrupt is exited.\n *\n * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the\n * item at the back of the queue, or queueSEND_TO_FRONT to place the item\n * at the front of the queue (for high priority messages).\n *\n * @return pdTRUE if the data was successfully sent to the queue, otherwise\n * errQUEUE_FULL.\n *\n * Example usage for buffered IO (where the ISR can obtain more than one value\n * per call):\n * @code{c}\n * void vBufferISR( void )\n * {\n * char cIn;\n * BaseType_t xHigherPriorityTaskWokenByPost;\n *\n *  // We have not woken a task at the start of the ISR.\n *  xHigherPriorityTaskWokenByPost = pdFALSE;\n *\n *  // Loop until the buffer is empty.\n *  do\n *  {\n *      // Obtain a byte from the buffer.\n *      cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );\n *\n *      // Post each byte.\n *      xQueueGenericSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWokenByPost, queueSEND_TO_BACK );\n *\n *  } while( portINPUT_BYTE( BUFFER_COUNT ) );\n *\n *  // Now the buffer is empty we can switch context if necessary.  Note that the\n *  // name of the yield function required is port specific.\n *  if( xHigherPriorityTaskWokenByPost )\n *  {\n *      portYIELD_FROM_ISR();\n *  }\n * }\n * @endcode\n *\n * \\defgroup xQueueSendFromISR xQueueSendFromISR\n * \\ingroup QueueManagement\n */\nBaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue,\n                                     const void * const pvItemToQueue,\n                                     BaseType_t * const pxHigherPriorityTaskWoken,\n                                     const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;\nBaseType_t xQueueGiveFromISR( QueueHandle_t xQueue,\n                              BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;\n\n/**\n * queue. h\n * @code{c}\n * BaseType_t xQueueReceiveFromISR(\n *                                     QueueHandle_t    xQueue,\n *                                     void             *pvBuffer,\n *                                     BaseType_t       *pxTaskWoken\n *                                 );\n * @endcode\n *\n * Receive an item from a queue.  It is safe to use this function from within an\n * interrupt service routine.\n *\n * @param xQueue The handle to the queue from which the item is to be\n * received.\n *\n * @param pvBuffer Pointer to the buffer into which the received item will\n * be copied.\n *\n * @param pxTaskWoken A task may be blocked waiting for space to become\n * available on the queue.  If xQueueReceiveFromISR causes such a task to\n * unblock *pxTaskWoken will get set to pdTRUE, otherwise *pxTaskWoken will\n * remain unchanged.\n *\n * @return pdTRUE if an item was successfully received from the queue,\n * otherwise pdFALSE.\n *\n * Example usage:\n * @code{c}\n *\n * QueueHandle_t xQueue;\n *\n * // Function to create a queue and post some values.\n * void vAFunction( void *pvParameters )\n * {\n * char cValueToPost;\n * const TickType_t xTicksToWait = ( TickType_t )0xff;\n *\n *  // Create a queue capable of containing 10 characters.\n *  xQueue = xQueueCreate( 10, sizeof( char ) );\n *  if( xQueue == 0 )\n *  {\n *      // Failed to create the queue.\n *  }\n *\n *  // ...\n *\n *  // Post some characters that will be used within an ISR.  If the queue\n *  // is full then this task will block for xTicksToWait ticks.\n *  cValueToPost = 'a';\n *  xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );\n *  cValueToPost = 'b';\n *  xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );\n *\n *  // ... keep posting characters ... this task may block when the queue\n *  // becomes full.\n *\n *  cValueToPost = 'c';\n *  xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );\n * }\n *\n * // ISR that outputs all the characters received on the queue.\n * void vISR_Routine( void )\n * {\n * BaseType_t xTaskWokenByReceive = pdFALSE;\n * char cRxedChar;\n *\n *  while( xQueueReceiveFromISR( xQueue, ( void * ) &cRxedChar, &xTaskWokenByReceive) )\n *  {\n *      // A character was received.  Output the character now.\n *      vOutputCharacter( cRxedChar );\n *\n *      // If removing the character from the queue woke the task that was\n *      // posting onto the queue xTaskWokenByReceive will have been set to\n *      // pdTRUE.  No matter how many times this loop iterates only one\n *      // task will be woken.\n *  }\n *\n *  if( xTaskWokenByReceive != ( char ) pdFALSE;\n *  {\n *      taskYIELD ();\n *  }\n * }\n * @endcode\n * \\defgroup xQueueReceiveFromISR xQueueReceiveFromISR\n * \\ingroup QueueManagement\n */\nBaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue,\n                                 void * const pvBuffer,\n                                 BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;\n\n/*\n * Utilities to query queues that are safe to use from an ISR.  These utilities\n * should be used only from within an ISR, or within a critical section.\n */\nBaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;\nBaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;\nUBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;\n\n/*\n * The functions defined above are for passing data to and from tasks.  The\n * functions below are the equivalents for passing data to and from\n * co-routines.\n *\n * These functions are called from the co-routine macro implementation and\n * should not be called directly from application code.  Instead use the macro\n * wrappers defined within croutine.h.\n */\nBaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue,\n                                const void * pvItemToQueue,\n                                BaseType_t xCoRoutinePreviouslyWoken );\nBaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue,\n                                   void * pvBuffer,\n                                   BaseType_t * pxTaskWoken );\nBaseType_t xQueueCRSend( QueueHandle_t xQueue,\n                         const void * pvItemToQueue,\n                         TickType_t xTicksToWait );\nBaseType_t xQueueCRReceive( QueueHandle_t xQueue,\n                            void * pvBuffer,\n                            TickType_t xTicksToWait );\n\n/*\n * For internal use only.  Use xSemaphoreCreateMutex(),\n * xSemaphoreCreateCounting() or xSemaphoreGetMutexHolder() instead of calling\n * these functions directly.\n */\nQueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;\nQueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType,\n                                       StaticQueue_t * pxStaticQueue ) PRIVILEGED_FUNCTION;\nQueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount,\n                                             const UBaseType_t uxInitialCount ) PRIVILEGED_FUNCTION;\nQueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount,\n                                                   const UBaseType_t uxInitialCount,\n                                                   StaticQueue_t * pxStaticQueue ) PRIVILEGED_FUNCTION;\nBaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue,\n                                TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;\nTaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;\nTaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;\n\n/*\n * For internal use only.  Use xSemaphoreTakeMutexRecursive() or\n * xSemaphoreGiveMutexRecursive() instead of calling these functions directly.\n */\nBaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex,\n                                     TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;\nBaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex ) PRIVILEGED_FUNCTION;\n\n/*\n * Reset a queue back to its original empty state.  The return value is now\n * obsolete and is always set to pdPASS.\n */\n#define xQueueReset( xQueue )    xQueueGenericReset( ( xQueue ), pdFALSE )\n\n/*\n * The registry is provided as a means for kernel aware debuggers to\n * locate queues, semaphores and mutexes.  Call vQueueAddToRegistry() add\n * a queue, semaphore or mutex handle to the registry if you want the handle\n * to be available to a kernel aware debugger.  If you are not using a kernel\n * aware debugger then this function can be ignored.\n *\n * configQUEUE_REGISTRY_SIZE defines the maximum number of handles the\n * registry can hold.  configQUEUE_REGISTRY_SIZE must be greater than 0\n * within FreeRTOSConfig.h for the registry to be available.  Its value\n * does not affect the number of queues, semaphores and mutexes that can be\n * created - just the number that the registry can hold.\n *\n * If vQueueAddToRegistry is called more than once with the same xQueue\n * parameter, the registry will store the pcQueueName parameter from the\n * most recent call to vQueueAddToRegistry.\n *\n * @param xQueue The handle of the queue being added to the registry.  This\n * is the handle returned by a call to xQueueCreate().  Semaphore and mutex\n * handles can also be passed in here.\n *\n * @param pcQueueName The name to be associated with the handle.  This is the\n * name that the kernel aware debugger will display.  The queue registry only\n * stores a pointer to the string - so the string must be persistent (global or\n * preferably in ROM/Flash), not on the stack.\n */\n#if ( configQUEUE_REGISTRY_SIZE > 0 )\n    void vQueueAddToRegistry( QueueHandle_t xQueue,\n                              const char * pcQueueName ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n#endif\n\n/*\n * The registry is provided as a means for kernel aware debuggers to\n * locate queues, semaphores and mutexes.  Call vQueueAddToRegistry() add\n * a queue, semaphore or mutex handle to the registry if you want the handle\n * to be available to a kernel aware debugger, and vQueueUnregisterQueue() to\n * remove the queue, semaphore or mutex from the register.  If you are not using\n * a kernel aware debugger then this function can be ignored.\n *\n * @param xQueue The handle of the queue being removed from the registry.\n */\n#if ( configQUEUE_REGISTRY_SIZE > 0 )\n    void vQueueUnregisterQueue( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;\n#endif\n\n/*\n * The queue registry is provided as a means for kernel aware debuggers to\n * locate queues, semaphores and mutexes.  Call pcQueueGetName() to look\n * up and return the name of a queue in the queue registry from the queue's\n * handle.\n *\n * @param xQueue The handle of the queue the name of which will be returned.\n * @return If the queue is in the registry then a pointer to the name of the\n * queue is returned.  If the queue is not in the registry then NULL is\n * returned.\n */\n#if ( configQUEUE_REGISTRY_SIZE > 0 )\n    const char * pcQueueGetName( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n#endif\n\n/*\n * Generic version of the function used to create a queue using dynamic memory\n * allocation.  This is called by other functions and macros that create other\n * RTOS objects that use the queue structure as their base.\n */\n#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n    QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength,\n                                       const UBaseType_t uxItemSize,\n                                       const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;\n#endif\n\n/*\n * Generic version of the function used to create a queue using dynamic memory\n * allocation.  This is called by other functions and macros that create other\n * RTOS objects that use the queue structure as their base.\n */\n#if ( configSUPPORT_STATIC_ALLOCATION == 1 )\n    QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength,\n                                             const UBaseType_t uxItemSize,\n                                             uint8_t * pucQueueStorage,\n                                             StaticQueue_t * pxStaticQueue,\n                                             const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;\n#endif\n\n/*\n * Queue sets provide a mechanism to allow a task to block (pend) on a read\n * operation from multiple queues or semaphores simultaneously.\n *\n * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this\n * function.\n *\n * A queue set must be explicitly created using a call to xQueueCreateSet()\n * before it can be used.  Once created, standard FreeRTOS queues and semaphores\n * can be added to the set using calls to xQueueAddToSet().\n * xQueueSelectFromSet() is then used to determine which, if any, of the queues\n * or semaphores contained in the set is in a state where a queue read or\n * semaphore take operation would be successful.\n *\n * Note 1:  See the documentation on https://www.FreeRTOS.org/RTOS-queue-sets.html\n * for reasons why queue sets are very rarely needed in practice as there are\n * simpler methods of blocking on multiple objects.\n *\n * Note 2:  Blocking on a queue set that contains a mutex will not cause the\n * mutex holder to inherit the priority of the blocked task.\n *\n * Note 3:  An additional 4 bytes of RAM is required for each space in a every\n * queue added to a queue set.  Therefore counting semaphores that have a high\n * maximum count value should not be added to a queue set.\n *\n * Note 4:  A receive (in the case of a queue) or take (in the case of a\n * semaphore) operation must not be performed on a member of a queue set unless\n * a call to xQueueSelectFromSet() has first returned a handle to that set member.\n *\n * @param uxEventQueueLength Queue sets store events that occur on\n * the queues and semaphores contained in the set.  uxEventQueueLength specifies\n * the maximum number of events that can be queued at once.  To be absolutely\n * certain that events are not lost uxEventQueueLength should be set to the\n * total sum of the length of the queues added to the set, where binary\n * semaphores and mutexes have a length of 1, and counting semaphores have a\n * length set by their maximum count value.  Examples:\n *  + If a queue set is to hold a queue of length 5, another queue of length 12,\n *    and a binary semaphore, then uxEventQueueLength should be set to\n *    (5 + 12 + 1), or 18.\n *  + If a queue set is to hold three binary semaphores then uxEventQueueLength\n *    should be set to (1 + 1 + 1 ), or 3.\n *  + If a queue set is to hold a counting semaphore that has a maximum count of\n *    5, and a counting semaphore that has a maximum count of 3, then\n *    uxEventQueueLength should be set to (5 + 3), or 8.\n *\n * @return If the queue set is created successfully then a handle to the created\n * queue set is returned.  Otherwise NULL is returned.\n */\nQueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength ) PRIVILEGED_FUNCTION;\n\n/*\n * Adds a queue or semaphore to a queue set that was previously created by a\n * call to xQueueCreateSet().\n *\n * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this\n * function.\n *\n * Note 1:  A receive (in the case of a queue) or take (in the case of a\n * semaphore) operation must not be performed on a member of a queue set unless\n * a call to xQueueSelectFromSet() has first returned a handle to that set member.\n *\n * @param xQueueOrSemaphore The handle of the queue or semaphore being added to\n * the queue set (cast to an QueueSetMemberHandle_t type).\n *\n * @param xQueueSet The handle of the queue set to which the queue or semaphore\n * is being added.\n *\n * @return If the queue or semaphore was successfully added to the queue set\n * then pdPASS is returned.  If the queue could not be successfully added to the\n * queue set because it is already a member of a different queue set then pdFAIL\n * is returned.\n */\nBaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,\n                           QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;\n\n/*\n * Removes a queue or semaphore from a queue set.  A queue or semaphore can only\n * be removed from a set if the queue or semaphore is empty.\n *\n * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this\n * function.\n *\n * @param xQueueOrSemaphore The handle of the queue or semaphore being removed\n * from the queue set (cast to an QueueSetMemberHandle_t type).\n *\n * @param xQueueSet The handle of the queue set in which the queue or semaphore\n * is included.\n *\n * @return If the queue or semaphore was successfully removed from the queue set\n * then pdPASS is returned.  If the queue was not in the queue set, or the\n * queue (or semaphore) was not empty, then pdFAIL is returned.\n */\nBaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore,\n                                QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;\n\n/*\n * xQueueSelectFromSet() selects from the members of a queue set a queue or\n * semaphore that either contains data (in the case of a queue) or is available\n * to take (in the case of a semaphore).  xQueueSelectFromSet() effectively\n * allows a task to block (pend) on a read operation on all the queues and\n * semaphores in a queue set simultaneously.\n *\n * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this\n * function.\n *\n * Note 1:  See the documentation on https://www.FreeRTOS.org/RTOS-queue-sets.html\n * for reasons why queue sets are very rarely needed in practice as there are\n * simpler methods of blocking on multiple objects.\n *\n * Note 2:  Blocking on a queue set that contains a mutex will not cause the\n * mutex holder to inherit the priority of the blocked task.\n *\n * Note 3:  A receive (in the case of a queue) or take (in the case of a\n * semaphore) operation must not be performed on a member of a queue set unless\n * a call to xQueueSelectFromSet() has first returned a handle to that set member.\n *\n * @param xQueueSet The queue set on which the task will (potentially) block.\n *\n * @param xTicksToWait The maximum time, in ticks, that the calling task will\n * remain in the Blocked state (with other tasks executing) to wait for a member\n * of the queue set to be ready for a successful queue read or semaphore take\n * operation.\n *\n * @return xQueueSelectFromSet() will return the handle of a queue (cast to\n * a QueueSetMemberHandle_t type) contained in the queue set that contains data,\n * or the handle of a semaphore (cast to a QueueSetMemberHandle_t type) contained\n * in the queue set that is available, or NULL if no such queue or semaphore\n * exists before before the specified block time expires.\n */\nQueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet,\n                                            const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;\n\n/*\n * A version of xQueueSelectFromSet() that can be used from an ISR.\n */\nQueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;\n\n/* Not public API functions. */\nvoid vQueueWaitForMessageRestricted( QueueHandle_t xQueue,\n                                     TickType_t xTicksToWait,\n                                     const BaseType_t xWaitIndefinitely ) PRIVILEGED_FUNCTION;\nBaseType_t xQueueGenericReset( QueueHandle_t xQueue,\n                               BaseType_t xNewQueue ) PRIVILEGED_FUNCTION;\nvoid vQueueSetQueueNumber( QueueHandle_t xQueue,\n                           UBaseType_t uxQueueNumber ) PRIVILEGED_FUNCTION;\nUBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;\nuint8_t ucQueueGetQueueType( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;\n\n\n/* *INDENT-OFF* */\n#ifdef __cplusplus\n    }\n#endif\n/* *INDENT-ON* */\n\n#endif /* QUEUE_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/include/semphr.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef SEMAPHORE_H\n#define SEMAPHORE_H\n\n#ifndef INC_FREERTOS_H\n    #error \"include FreeRTOS.h\" must appear in source files before \"include semphr.h\"\n#endif\n\n#include \"queue.h\"\n\ntypedef QueueHandle_t SemaphoreHandle_t;\n\n#define semBINARY_SEMAPHORE_QUEUE_LENGTH    ( ( uint8_t ) 1U )\n#define semSEMAPHORE_QUEUE_ITEM_LENGTH      ( ( uint8_t ) 0U )\n#define semGIVE_BLOCK_TIME                  ( ( TickType_t ) 0U )\n\n\n/**\n * semphr. h\n * @code{c}\n * vSemaphoreCreateBinary( SemaphoreHandle_t xSemaphore );\n * @endcode\n *\n * In many usage scenarios it is faster and more memory efficient to use a\n * direct to task notification in place of a binary semaphore!\n * https://www.FreeRTOS.org/RTOS-task-notifications.html\n *\n * This old vSemaphoreCreateBinary() macro is now deprecated in favour of the\n * xSemaphoreCreateBinary() function.  Note that binary semaphores created using\n * the vSemaphoreCreateBinary() macro are created in a state such that the\n * first call to 'take' the semaphore would pass, whereas binary semaphores\n * created using xSemaphoreCreateBinary() are created in a state such that the\n * the semaphore must first be 'given' before it can be 'taken'.\n *\n * <i>Macro</i> that implements a semaphore by using the existing queue mechanism.\n * The queue length is 1 as this is a binary semaphore.  The data size is 0\n * as we don't want to actually store any data - we just want to know if the\n * queue is empty or full.\n *\n * This type of semaphore can be used for pure synchronisation between tasks or\n * between an interrupt and a task.  The semaphore need not be given back once\n * obtained, so one task/interrupt can continuously 'give' the semaphore while\n * another continuously 'takes' the semaphore.  For this reason this type of\n * semaphore does not use a priority inheritance mechanism.  For an alternative\n * that does use priority inheritance see xSemaphoreCreateMutex().\n *\n * @param xSemaphore Handle to the created semaphore.  Should be of type SemaphoreHandle_t.\n *\n * Example usage:\n * @code{c}\n * SemaphoreHandle_t xSemaphore = NULL;\n *\n * void vATask( void * pvParameters )\n * {\n *  // Semaphore cannot be used before a call to vSemaphoreCreateBinary ().\n *  // This is a macro so pass the variable in directly.\n *  vSemaphoreCreateBinary( xSemaphore );\n *\n *  if( xSemaphore != NULL )\n *  {\n *      // The semaphore was created successfully.\n *      // The semaphore can now be used.\n *  }\n * }\n * @endcode\n * \\defgroup vSemaphoreCreateBinary vSemaphoreCreateBinary\n * \\ingroup Semaphores\n */\n#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n    #define vSemaphoreCreateBinary( xSemaphore )                                                                                     \\\n    {                                                                                                                                \\\n        ( xSemaphore ) = xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE ); \\\n        if( ( xSemaphore ) != NULL )                                                                                                 \\\n        {                                                                                                                            \\\n            ( void ) xSemaphoreGive( ( xSemaphore ) );                                                                               \\\n        }                                                                                                                            \\\n    }\n#endif\n\n/**\n * semphr. h\n * @code{c}\n * SemaphoreHandle_t xSemaphoreCreateBinary( void );\n * @endcode\n *\n * Creates a new binary semaphore instance, and returns a handle by which the\n * new semaphore can be referenced.\n *\n * In many usage scenarios it is faster and more memory efficient to use a\n * direct to task notification in place of a binary semaphore!\n * https://www.FreeRTOS.org/RTOS-task-notifications.html\n *\n * Internally, within the FreeRTOS implementation, binary semaphores use a block\n * of memory, in which the semaphore structure is stored.  If a binary semaphore\n * is created using xSemaphoreCreateBinary() then the required memory is\n * automatically dynamically allocated inside the xSemaphoreCreateBinary()\n * function.  (see https://www.FreeRTOS.org/a00111.html).  If a binary semaphore\n * is created using xSemaphoreCreateBinaryStatic() then the application writer\n * must provide the memory.  xSemaphoreCreateBinaryStatic() therefore allows a\n * binary semaphore to be created without using any dynamic memory allocation.\n *\n * The old vSemaphoreCreateBinary() macro is now deprecated in favour of this\n * xSemaphoreCreateBinary() function.  Note that binary semaphores created using\n * the vSemaphoreCreateBinary() macro are created in a state such that the\n * first call to 'take' the semaphore would pass, whereas binary semaphores\n * created using xSemaphoreCreateBinary() are created in a state such that the\n * the semaphore must first be 'given' before it can be 'taken'.\n *\n * This type of semaphore can be used for pure synchronisation between tasks or\n * between an interrupt and a task.  The semaphore need not be given back once\n * obtained, so one task/interrupt can continuously 'give' the semaphore while\n * another continuously 'takes' the semaphore.  For this reason this type of\n * semaphore does not use a priority inheritance mechanism.  For an alternative\n * that does use priority inheritance see xSemaphoreCreateMutex().\n *\n * @return Handle to the created semaphore, or NULL if the memory required to\n * hold the semaphore's data structures could not be allocated.\n *\n * Example usage:\n * @code{c}\n * SemaphoreHandle_t xSemaphore = NULL;\n *\n * void vATask( void * pvParameters )\n * {\n *  // Semaphore cannot be used before a call to xSemaphoreCreateBinary().\n *  // This is a macro so pass the variable in directly.\n *  xSemaphore = xSemaphoreCreateBinary();\n *\n *  if( xSemaphore != NULL )\n *  {\n *      // The semaphore was created successfully.\n *      // The semaphore can now be used.\n *  }\n * }\n * @endcode\n * \\defgroup xSemaphoreCreateBinary xSemaphoreCreateBinary\n * \\ingroup Semaphores\n */\n#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n    #define xSemaphoreCreateBinary()    xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE )\n#endif\n\n/**\n * semphr. h\n * @code{c}\n * SemaphoreHandle_t xSemaphoreCreateBinaryStatic( StaticSemaphore_t *pxSemaphoreBuffer );\n * @endcode\n *\n * Creates a new binary semaphore instance, and returns a handle by which the\n * new semaphore can be referenced.\n *\n * NOTE: In many usage scenarios it is faster and more memory efficient to use a\n * direct to task notification in place of a binary semaphore!\n * https://www.FreeRTOS.org/RTOS-task-notifications.html\n *\n * Internally, within the FreeRTOS implementation, binary semaphores use a block\n * of memory, in which the semaphore structure is stored.  If a binary semaphore\n * is created using xSemaphoreCreateBinary() then the required memory is\n * automatically dynamically allocated inside the xSemaphoreCreateBinary()\n * function.  (see https://www.FreeRTOS.org/a00111.html).  If a binary semaphore\n * is created using xSemaphoreCreateBinaryStatic() then the application writer\n * must provide the memory.  xSemaphoreCreateBinaryStatic() therefore allows a\n * binary semaphore to be created without using any dynamic memory allocation.\n *\n * This type of semaphore can be used for pure synchronisation between tasks or\n * between an interrupt and a task.  The semaphore need not be given back once\n * obtained, so one task/interrupt can continuously 'give' the semaphore while\n * another continuously 'takes' the semaphore.  For this reason this type of\n * semaphore does not use a priority inheritance mechanism.  For an alternative\n * that does use priority inheritance see xSemaphoreCreateMutex().\n *\n * @param pxSemaphoreBuffer Must point to a variable of type StaticSemaphore_t,\n * which will then be used to hold the semaphore's data structure, removing the\n * need for the memory to be allocated dynamically.\n *\n * @return If the semaphore is created then a handle to the created semaphore is\n * returned.  If pxSemaphoreBuffer is NULL then NULL is returned.\n *\n * Example usage:\n * @code{c}\n * SemaphoreHandle_t xSemaphore = NULL;\n * StaticSemaphore_t xSemaphoreBuffer;\n *\n * void vATask( void * pvParameters )\n * {\n *  // Semaphore cannot be used before a call to xSemaphoreCreateBinary().\n *  // The semaphore's data structures will be placed in the xSemaphoreBuffer\n *  // variable, the address of which is passed into the function.  The\n *  // function's parameter is not NULL, so the function will not attempt any\n *  // dynamic memory allocation, and therefore the function will not return\n *  // return NULL.\n *  xSemaphore = xSemaphoreCreateBinary( &xSemaphoreBuffer );\n *\n *  // Rest of task code goes here.\n * }\n * @endcode\n * \\defgroup xSemaphoreCreateBinaryStatic xSemaphoreCreateBinaryStatic\n * \\ingroup Semaphores\n */\n#if ( configSUPPORT_STATIC_ALLOCATION == 1 )\n    #define xSemaphoreCreateBinaryStatic( pxStaticSemaphore )    xQueueGenericCreateStatic( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, ( pxStaticSemaphore ), queueQUEUE_TYPE_BINARY_SEMAPHORE )\n#endif /* configSUPPORT_STATIC_ALLOCATION */\n\n/**\n * semphr. h\n * @code{c}\n * xSemaphoreTake(\n *                   SemaphoreHandle_t xSemaphore,\n *                   TickType_t xBlockTime\n *               );\n * @endcode\n *\n * <i>Macro</i> to obtain a semaphore.  The semaphore must have previously been\n * created with a call to xSemaphoreCreateBinary(), xSemaphoreCreateMutex() or\n * xSemaphoreCreateCounting().\n *\n * @param xSemaphore A handle to the semaphore being taken - obtained when\n * the semaphore was created.\n *\n * @param xBlockTime The time in ticks to wait for the semaphore to become\n * available.  The macro portTICK_PERIOD_MS can be used to convert this to a\n * real time.  A block time of zero can be used to poll the semaphore.  A block\n * time of portMAX_DELAY can be used to block indefinitely (provided\n * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h).\n *\n * @return pdTRUE if the semaphore was obtained.  pdFALSE\n * if xBlockTime expired without the semaphore becoming available.\n *\n * Example usage:\n * @code{c}\n * SemaphoreHandle_t xSemaphore = NULL;\n *\n * // A task that creates a semaphore.\n * void vATask( void * pvParameters )\n * {\n *  // Create the semaphore to guard a shared resource.\n *  xSemaphore = xSemaphoreCreateBinary();\n * }\n *\n * // A task that uses the semaphore.\n * void vAnotherTask( void * pvParameters )\n * {\n *  // ... Do other things.\n *\n *  if( xSemaphore != NULL )\n *  {\n *      // See if we can obtain the semaphore.  If the semaphore is not available\n *      // wait 10 ticks to see if it becomes free.\n *      if( xSemaphoreTake( xSemaphore, ( TickType_t ) 10 ) == pdTRUE )\n *      {\n *          // We were able to obtain the semaphore and can now access the\n *          // shared resource.\n *\n *          // ...\n *\n *          // We have finished accessing the shared resource.  Release the\n *          // semaphore.\n *          xSemaphoreGive( xSemaphore );\n *      }\n *      else\n *      {\n *          // We could not obtain the semaphore and can therefore not access\n *          // the shared resource safely.\n *      }\n *  }\n * }\n * @endcode\n * \\defgroup xSemaphoreTake xSemaphoreTake\n * \\ingroup Semaphores\n */\n#define xSemaphoreTake( xSemaphore, xBlockTime )    xQueueSemaphoreTake( ( xSemaphore ), ( xBlockTime ) )\n\n/**\n * semphr. h\n * @code{c}\n * xSemaphoreTakeRecursive(\n *                          SemaphoreHandle_t xMutex,\n *                          TickType_t xBlockTime\n *                        );\n * @endcode\n *\n * <i>Macro</i> to recursively obtain, or 'take', a mutex type semaphore.\n * The mutex must have previously been created using a call to\n * xSemaphoreCreateRecursiveMutex();\n *\n * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this\n * macro to be available.\n *\n * This macro must not be used on mutexes created using xSemaphoreCreateMutex().\n *\n * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex\n * doesn't become available again until the owner has called\n * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,\n * if a task successfully 'takes' the same mutex 5 times then the mutex will\n * not be available to any other task until it has also  'given' the mutex back\n * exactly five times.\n *\n * @param xMutex A handle to the mutex being obtained.  This is the\n * handle returned by xSemaphoreCreateRecursiveMutex();\n *\n * @param xBlockTime The time in ticks to wait for the semaphore to become\n * available.  The macro portTICK_PERIOD_MS can be used to convert this to a\n * real time.  A block time of zero can be used to poll the semaphore.  If\n * the task already owns the semaphore then xSemaphoreTakeRecursive() will\n * return immediately no matter what the value of xBlockTime.\n *\n * @return pdTRUE if the semaphore was obtained.  pdFALSE if xBlockTime\n * expired without the semaphore becoming available.\n *\n * Example usage:\n * @code{c}\n * SemaphoreHandle_t xMutex = NULL;\n *\n * // A task that creates a mutex.\n * void vATask( void * pvParameters )\n * {\n *  // Create the mutex to guard a shared resource.\n *  xMutex = xSemaphoreCreateRecursiveMutex();\n * }\n *\n * // A task that uses the mutex.\n * void vAnotherTask( void * pvParameters )\n * {\n *  // ... Do other things.\n *\n *  if( xMutex != NULL )\n *  {\n *      // See if we can obtain the mutex.  If the mutex is not available\n *      // wait 10 ticks to see if it becomes free.\n *      if( xSemaphoreTakeRecursive( xSemaphore, ( TickType_t ) 10 ) == pdTRUE )\n *      {\n *          // We were able to obtain the mutex and can now access the\n *          // shared resource.\n *\n *          // ...\n *          // For some reason due to the nature of the code further calls to\n *          // xSemaphoreTakeRecursive() are made on the same mutex.  In real\n *          // code these would not be just sequential calls as this would make\n *          // no sense.  Instead the calls are likely to be buried inside\n *          // a more complex call structure.\n *          xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );\n *          xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );\n *\n *          // The mutex has now been 'taken' three times, so will not be\n *          // available to another task until it has also been given back\n *          // three times.  Again it is unlikely that real code would have\n *          // these calls sequentially, but instead buried in a more complex\n *          // call structure.  This is just for illustrative purposes.\n *          xSemaphoreGiveRecursive( xMutex );\n *          xSemaphoreGiveRecursive( xMutex );\n *          xSemaphoreGiveRecursive( xMutex );\n *\n *          // Now the mutex can be taken by other tasks.\n *      }\n *      else\n *      {\n *          // We could not obtain the mutex and can therefore not access\n *          // the shared resource safely.\n *      }\n *  }\n * }\n * @endcode\n * \\defgroup xSemaphoreTakeRecursive xSemaphoreTakeRecursive\n * \\ingroup Semaphores\n */\n#if ( configUSE_RECURSIVE_MUTEXES == 1 )\n    #define xSemaphoreTakeRecursive( xMutex, xBlockTime )    xQueueTakeMutexRecursive( ( xMutex ), ( xBlockTime ) )\n#endif\n\n/**\n * semphr. h\n * @code{c}\n * xSemaphoreGive( SemaphoreHandle_t xSemaphore );\n * @endcode\n *\n * <i>Macro</i> to release a semaphore.  The semaphore must have previously been\n * created with a call to xSemaphoreCreateBinary(), xSemaphoreCreateMutex() or\n * xSemaphoreCreateCounting(). and obtained using sSemaphoreTake().\n *\n * This macro must not be used from an ISR.  See xSemaphoreGiveFromISR () for\n * an alternative which can be used from an ISR.\n *\n * This macro must also not be used on semaphores created using\n * xSemaphoreCreateRecursiveMutex().\n *\n * @param xSemaphore A handle to the semaphore being released.  This is the\n * handle returned when the semaphore was created.\n *\n * @return pdTRUE if the semaphore was released.  pdFALSE if an error occurred.\n * Semaphores are implemented using queues.  An error can occur if there is\n * no space on the queue to post a message - indicating that the\n * semaphore was not first obtained correctly.\n *\n * Example usage:\n * @code{c}\n * SemaphoreHandle_t xSemaphore = NULL;\n *\n * void vATask( void * pvParameters )\n * {\n *  // Create the semaphore to guard a shared resource.\n *  xSemaphore = vSemaphoreCreateBinary();\n *\n *  if( xSemaphore != NULL )\n *  {\n *      if( xSemaphoreGive( xSemaphore ) != pdTRUE )\n *      {\n *          // We would expect this call to fail because we cannot give\n *          // a semaphore without first \"taking\" it!\n *      }\n *\n *      // Obtain the semaphore - don't block if the semaphore is not\n *      // immediately available.\n *      if( xSemaphoreTake( xSemaphore, ( TickType_t ) 0 ) )\n *      {\n *          // We now have the semaphore and can access the shared resource.\n *\n *          // ...\n *\n *          // We have finished accessing the shared resource so can free the\n *          // semaphore.\n *          if( xSemaphoreGive( xSemaphore ) != pdTRUE )\n *          {\n *              // We would not expect this call to fail because we must have\n *              // obtained the semaphore to get here.\n *          }\n *      }\n *  }\n * }\n * @endcode\n * \\defgroup xSemaphoreGive xSemaphoreGive\n * \\ingroup Semaphores\n */\n#define xSemaphoreGive( xSemaphore )    xQueueGenericSend( ( QueueHandle_t ) ( xSemaphore ), NULL, semGIVE_BLOCK_TIME, queueSEND_TO_BACK )\n\n/**\n * semphr. h\n * @code{c}\n * xSemaphoreGiveRecursive( SemaphoreHandle_t xMutex );\n * @endcode\n *\n * <i>Macro</i> to recursively release, or 'give', a mutex type semaphore.\n * The mutex must have previously been created using a call to\n * xSemaphoreCreateRecursiveMutex();\n *\n * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this\n * macro to be available.\n *\n * This macro must not be used on mutexes created using xSemaphoreCreateMutex().\n *\n * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex\n * doesn't become available again until the owner has called\n * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,\n * if a task successfully 'takes' the same mutex 5 times then the mutex will\n * not be available to any other task until it has also  'given' the mutex back\n * exactly five times.\n *\n * @param xMutex A handle to the mutex being released, or 'given'.  This is the\n * handle returned by xSemaphoreCreateMutex();\n *\n * @return pdTRUE if the semaphore was given.\n *\n * Example usage:\n * @code{c}\n * SemaphoreHandle_t xMutex = NULL;\n *\n * // A task that creates a mutex.\n * void vATask( void * pvParameters )\n * {\n *  // Create the mutex to guard a shared resource.\n *  xMutex = xSemaphoreCreateRecursiveMutex();\n * }\n *\n * // A task that uses the mutex.\n * void vAnotherTask( void * pvParameters )\n * {\n *  // ... Do other things.\n *\n *  if( xMutex != NULL )\n *  {\n *      // See if we can obtain the mutex.  If the mutex is not available\n *      // wait 10 ticks to see if it becomes free.\n *      if( xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 ) == pdTRUE )\n *      {\n *          // We were able to obtain the mutex and can now access the\n *          // shared resource.\n *\n *          // ...\n *          // For some reason due to the nature of the code further calls to\n *          // xSemaphoreTakeRecursive() are made on the same mutex.  In real\n *          // code these would not be just sequential calls as this would make\n *          // no sense.  Instead the calls are likely to be buried inside\n *          // a more complex call structure.\n *          xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );\n *          xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );\n *\n *          // The mutex has now been 'taken' three times, so will not be\n *          // available to another task until it has also been given back\n *          // three times.  Again it is unlikely that real code would have\n *          // these calls sequentially, it would be more likely that the calls\n *          // to xSemaphoreGiveRecursive() would be called as a call stack\n *          // unwound.  This is just for demonstrative purposes.\n *          xSemaphoreGiveRecursive( xMutex );\n *          xSemaphoreGiveRecursive( xMutex );\n *          xSemaphoreGiveRecursive( xMutex );\n *\n *          // Now the mutex can be taken by other tasks.\n *      }\n *      else\n *      {\n *          // We could not obtain the mutex and can therefore not access\n *          // the shared resource safely.\n *      }\n *  }\n * }\n * @endcode\n * \\defgroup xSemaphoreGiveRecursive xSemaphoreGiveRecursive\n * \\ingroup Semaphores\n */\n#if ( configUSE_RECURSIVE_MUTEXES == 1 )\n    #define xSemaphoreGiveRecursive( xMutex )    xQueueGiveMutexRecursive( ( xMutex ) )\n#endif\n\n/**\n * semphr. h\n * @code{c}\n * xSemaphoreGiveFromISR(\n *                        SemaphoreHandle_t xSemaphore,\n *                        BaseType_t *pxHigherPriorityTaskWoken\n *                    );\n * @endcode\n *\n * <i>Macro</i> to  release a semaphore.  The semaphore must have previously been\n * created with a call to xSemaphoreCreateBinary() or xSemaphoreCreateCounting().\n *\n * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex())\n * must not be used with this macro.\n *\n * This macro can be used from an ISR.\n *\n * @param xSemaphore A handle to the semaphore being released.  This is the\n * handle returned when the semaphore was created.\n *\n * @param pxHigherPriorityTaskWoken xSemaphoreGiveFromISR() will set\n * *pxHigherPriorityTaskWoken to pdTRUE if giving the semaphore caused a task\n * to unblock, and the unblocked task has a priority higher than the currently\n * running task.  If xSemaphoreGiveFromISR() sets this value to pdTRUE then\n * a context switch should be requested before the interrupt is exited.\n *\n * @return pdTRUE if the semaphore was successfully given, otherwise errQUEUE_FULL.\n *\n * Example usage:\n * @code{c}\n \\#define LONG_TIME 0xffff\n \\#define TICKS_TO_WAIT 10\n * SemaphoreHandle_t xSemaphore = NULL;\n *\n * // Repetitive task.\n * void vATask( void * pvParameters )\n * {\n *  for( ;; )\n *  {\n *      // We want this task to run every 10 ticks of a timer.  The semaphore\n *      // was created before this task was started.\n *\n *      // Block waiting for the semaphore to become available.\n *      if( xSemaphoreTake( xSemaphore, LONG_TIME ) == pdTRUE )\n *      {\n *          // It is time to execute.\n *\n *          // ...\n *\n *          // We have finished our task.  Return to the top of the loop where\n *          // we will block on the semaphore until it is time to execute\n *          // again.  Note when using the semaphore for synchronisation with an\n *          // ISR in this manner there is no need to 'give' the semaphore back.\n *      }\n *  }\n * }\n *\n * // Timer ISR\n * void vTimerISR( void * pvParameters )\n * {\n * static uint8_t ucLocalTickCount = 0;\n * static BaseType_t xHigherPriorityTaskWoken;\n *\n *  // A timer tick has occurred.\n *\n *  // ... Do other time functions.\n *\n *  // Is it time for vATask () to run?\n *  xHigherPriorityTaskWoken = pdFALSE;\n *  ucLocalTickCount++;\n *  if( ucLocalTickCount >= TICKS_TO_WAIT )\n *  {\n *      // Unblock the task by releasing the semaphore.\n *      xSemaphoreGiveFromISR( xSemaphore, &xHigherPriorityTaskWoken );\n *\n *      // Reset the count so we release the semaphore again in 10 ticks time.\n *      ucLocalTickCount = 0;\n *  }\n *\n *  if( xHigherPriorityTaskWoken != pdFALSE )\n *  {\n *      // We can force a context switch here.  Context switching from an\n *      // ISR uses port specific syntax.  Check the demo task for your port\n *      // to find the syntax required.\n *  }\n * }\n * @endcode\n * \\defgroup xSemaphoreGiveFromISR xSemaphoreGiveFromISR\n * \\ingroup Semaphores\n */\n#define xSemaphoreGiveFromISR( xSemaphore, pxHigherPriorityTaskWoken )    xQueueGiveFromISR( ( QueueHandle_t ) ( xSemaphore ), ( pxHigherPriorityTaskWoken ) )\n\n/**\n * semphr. h\n * @code{c}\n * xSemaphoreTakeFromISR(\n *                        SemaphoreHandle_t xSemaphore,\n *                        BaseType_t *pxHigherPriorityTaskWoken\n *                    );\n * @endcode\n *\n * <i>Macro</i> to  take a semaphore from an ISR.  The semaphore must have\n * previously been created with a call to xSemaphoreCreateBinary() or\n * xSemaphoreCreateCounting().\n *\n * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex())\n * must not be used with this macro.\n *\n * This macro can be used from an ISR, however taking a semaphore from an ISR\n * is not a common operation.  It is likely to only be useful when taking a\n * counting semaphore when an interrupt is obtaining an object from a resource\n * pool (when the semaphore count indicates the number of resources available).\n *\n * @param xSemaphore A handle to the semaphore being taken.  This is the\n * handle returned when the semaphore was created.\n *\n * @param pxHigherPriorityTaskWoken xSemaphoreTakeFromISR() will set\n * *pxHigherPriorityTaskWoken to pdTRUE if taking the semaphore caused a task\n * to unblock, and the unblocked task has a priority higher than the currently\n * running task.  If xSemaphoreTakeFromISR() sets this value to pdTRUE then\n * a context switch should be requested before the interrupt is exited.\n *\n * @return pdTRUE if the semaphore was successfully taken, otherwise\n * pdFALSE\n */\n#define xSemaphoreTakeFromISR( xSemaphore, pxHigherPriorityTaskWoken )    xQueueReceiveFromISR( ( QueueHandle_t ) ( xSemaphore ), NULL, ( pxHigherPriorityTaskWoken ) )\n\n/**\n * semphr. h\n * @code{c}\n * SemaphoreHandle_t xSemaphoreCreateMutex( void );\n * @endcode\n *\n * Creates a new mutex type semaphore instance, and returns a handle by which\n * the new mutex can be referenced.\n *\n * Internally, within the FreeRTOS implementation, mutex semaphores use a block\n * of memory, in which the mutex structure is stored.  If a mutex is created\n * using xSemaphoreCreateMutex() then the required memory is automatically\n * dynamically allocated inside the xSemaphoreCreateMutex() function.  (see\n * https://www.FreeRTOS.org/a00111.html).  If a mutex is created using\n * xSemaphoreCreateMutexStatic() then the application writer must provided the\n * memory.  xSemaphoreCreateMutexStatic() therefore allows a mutex to be created\n * without using any dynamic memory allocation.\n *\n * Mutexes created using this function can be accessed using the xSemaphoreTake()\n * and xSemaphoreGive() macros.  The xSemaphoreTakeRecursive() and\n * xSemaphoreGiveRecursive() macros must not be used.\n *\n * This type of semaphore uses a priority inheritance mechanism so a task\n * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the\n * semaphore it is no longer required.\n *\n * Mutex type semaphores cannot be used from within interrupt service routines.\n *\n * See xSemaphoreCreateBinary() for an alternative implementation that can be\n * used for pure synchronisation (where one task or interrupt always 'gives' the\n * semaphore and another always 'takes' the semaphore) and from within interrupt\n * service routines.\n *\n * @return If the mutex was successfully created then a handle to the created\n * semaphore is returned.  If there was not enough heap to allocate the mutex\n * data structures then NULL is returned.\n *\n * Example usage:\n * @code{c}\n * SemaphoreHandle_t xSemaphore;\n *\n * void vATask( void * pvParameters )\n * {\n *  // Semaphore cannot be used before a call to xSemaphoreCreateMutex().\n *  // This is a macro so pass the variable in directly.\n *  xSemaphore = xSemaphoreCreateMutex();\n *\n *  if( xSemaphore != NULL )\n *  {\n *      // The semaphore was created successfully.\n *      // The semaphore can now be used.\n *  }\n * }\n * @endcode\n * \\defgroup xSemaphoreCreateMutex xSemaphoreCreateMutex\n * \\ingroup Semaphores\n */\n#if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_MUTEXES == 1 ) )\n    #define xSemaphoreCreateMutex()    xQueueCreateMutex( queueQUEUE_TYPE_MUTEX )\n#endif\n\n/**\n * semphr. h\n * @code{c}\n * SemaphoreHandle_t xSemaphoreCreateMutexStatic( StaticSemaphore_t *pxMutexBuffer );\n * @endcode\n *\n * Creates a new mutex type semaphore instance, and returns a handle by which\n * the new mutex can be referenced.\n *\n * Internally, within the FreeRTOS implementation, mutex semaphores use a block\n * of memory, in which the mutex structure is stored.  If a mutex is created\n * using xSemaphoreCreateMutex() then the required memory is automatically\n * dynamically allocated inside the xSemaphoreCreateMutex() function.  (see\n * https://www.FreeRTOS.org/a00111.html).  If a mutex is created using\n * xSemaphoreCreateMutexStatic() then the application writer must provided the\n * memory.  xSemaphoreCreateMutexStatic() therefore allows a mutex to be created\n * without using any dynamic memory allocation.\n *\n * Mutexes created using this function can be accessed using the xSemaphoreTake()\n * and xSemaphoreGive() macros.  The xSemaphoreTakeRecursive() and\n * xSemaphoreGiveRecursive() macros must not be used.\n *\n * This type of semaphore uses a priority inheritance mechanism so a task\n * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the\n * semaphore it is no longer required.\n *\n * Mutex type semaphores cannot be used from within interrupt service routines.\n *\n * See xSemaphoreCreateBinary() for an alternative implementation that can be\n * used for pure synchronisation (where one task or interrupt always 'gives' the\n * semaphore and another always 'takes' the semaphore) and from within interrupt\n * service routines.\n *\n * @param pxMutexBuffer Must point to a variable of type StaticSemaphore_t,\n * which will be used to hold the mutex's data structure, removing the need for\n * the memory to be allocated dynamically.\n *\n * @return If the mutex was successfully created then a handle to the created\n * mutex is returned.  If pxMutexBuffer was NULL then NULL is returned.\n *\n * Example usage:\n * @code{c}\n * SemaphoreHandle_t xSemaphore;\n * StaticSemaphore_t xMutexBuffer;\n *\n * void vATask( void * pvParameters )\n * {\n *  // A mutex cannot be used before it has been created.  xMutexBuffer is\n *  // into xSemaphoreCreateMutexStatic() so no dynamic memory allocation is\n *  // attempted.\n *  xSemaphore = xSemaphoreCreateMutexStatic( &xMutexBuffer );\n *\n *  // As no dynamic memory allocation was performed, xSemaphore cannot be NULL,\n *  // so there is no need to check it.\n * }\n * @endcode\n * \\defgroup xSemaphoreCreateMutexStatic xSemaphoreCreateMutexStatic\n * \\ingroup Semaphores\n */\n#if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_MUTEXES == 1 ) )\n    #define xSemaphoreCreateMutexStatic( pxMutexBuffer )    xQueueCreateMutexStatic( queueQUEUE_TYPE_MUTEX, ( pxMutexBuffer ) )\n#endif\n\n\n/**\n * semphr. h\n * @code{c}\n * SemaphoreHandle_t xSemaphoreCreateRecursiveMutex( void );\n * @endcode\n *\n * Creates a new recursive mutex type semaphore instance, and returns a handle\n * by which the new recursive mutex can be referenced.\n *\n * Internally, within the FreeRTOS implementation, recursive mutexes use a block\n * of memory, in which the mutex structure is stored.  If a recursive mutex is\n * created using xSemaphoreCreateRecursiveMutex() then the required memory is\n * automatically dynamically allocated inside the\n * xSemaphoreCreateRecursiveMutex() function.  (see\n * https://www.FreeRTOS.org/a00111.html).  If a recursive mutex is created using\n * xSemaphoreCreateRecursiveMutexStatic() then the application writer must\n * provide the memory that will get used by the mutex.\n * xSemaphoreCreateRecursiveMutexStatic() therefore allows a recursive mutex to\n * be created without using any dynamic memory allocation.\n *\n * Mutexes created using this macro can be accessed using the\n * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros.  The\n * xSemaphoreTake() and xSemaphoreGive() macros must not be used.\n *\n * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex\n * doesn't become available again until the owner has called\n * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,\n * if a task successfully 'takes' the same mutex 5 times then the mutex will\n * not be available to any other task until it has also  'given' the mutex back\n * exactly five times.\n *\n * This type of semaphore uses a priority inheritance mechanism so a task\n * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the\n * semaphore it is no longer required.\n *\n * Mutex type semaphores cannot be used from within interrupt service routines.\n *\n * See xSemaphoreCreateBinary() for an alternative implementation that can be\n * used for pure synchronisation (where one task or interrupt always 'gives' the\n * semaphore and another always 'takes' the semaphore) and from within interrupt\n * service routines.\n *\n * @return xSemaphore Handle to the created mutex semaphore.  Should be of type\n * SemaphoreHandle_t.\n *\n * Example usage:\n * @code{c}\n * SemaphoreHandle_t xSemaphore;\n *\n * void vATask( void * pvParameters )\n * {\n *  // Semaphore cannot be used before a call to xSemaphoreCreateMutex().\n *  // This is a macro so pass the variable in directly.\n *  xSemaphore = xSemaphoreCreateRecursiveMutex();\n *\n *  if( xSemaphore != NULL )\n *  {\n *      // The semaphore was created successfully.\n *      // The semaphore can now be used.\n *  }\n * }\n * @endcode\n * \\defgroup xSemaphoreCreateRecursiveMutex xSemaphoreCreateRecursiveMutex\n * \\ingroup Semaphores\n */\n#if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_RECURSIVE_MUTEXES == 1 ) )\n    #define xSemaphoreCreateRecursiveMutex()    xQueueCreateMutex( queueQUEUE_TYPE_RECURSIVE_MUTEX )\n#endif\n\n/**\n * semphr. h\n * @code{c}\n * SemaphoreHandle_t xSemaphoreCreateRecursiveMutexStatic( StaticSemaphore_t *pxMutexBuffer );\n * @endcode\n *\n * Creates a new recursive mutex type semaphore instance, and returns a handle\n * by which the new recursive mutex can be referenced.\n *\n * Internally, within the FreeRTOS implementation, recursive mutexes use a block\n * of memory, in which the mutex structure is stored.  If a recursive mutex is\n * created using xSemaphoreCreateRecursiveMutex() then the required memory is\n * automatically dynamically allocated inside the\n * xSemaphoreCreateRecursiveMutex() function.  (see\n * https://www.FreeRTOS.org/a00111.html).  If a recursive mutex is created using\n * xSemaphoreCreateRecursiveMutexStatic() then the application writer must\n * provide the memory that will get used by the mutex.\n * xSemaphoreCreateRecursiveMutexStatic() therefore allows a recursive mutex to\n * be created without using any dynamic memory allocation.\n *\n * Mutexes created using this macro can be accessed using the\n * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros.  The\n * xSemaphoreTake() and xSemaphoreGive() macros must not be used.\n *\n * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex\n * doesn't become available again until the owner has called\n * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,\n * if a task successfully 'takes' the same mutex 5 times then the mutex will\n * not be available to any other task until it has also  'given' the mutex back\n * exactly five times.\n *\n * This type of semaphore uses a priority inheritance mechanism so a task\n * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the\n * semaphore it is no longer required.\n *\n * Mutex type semaphores cannot be used from within interrupt service routines.\n *\n * See xSemaphoreCreateBinary() for an alternative implementation that can be\n * used for pure synchronisation (where one task or interrupt always 'gives' the\n * semaphore and another always 'takes' the semaphore) and from within interrupt\n * service routines.\n *\n * @param pxMutexBuffer Must point to a variable of type StaticSemaphore_t,\n * which will then be used to hold the recursive mutex's data structure,\n * removing the need for the memory to be allocated dynamically.\n *\n * @return If the recursive mutex was successfully created then a handle to the\n * created recursive mutex is returned.  If pxMutexBuffer was NULL then NULL is\n * returned.\n *\n * Example usage:\n * @code{c}\n * SemaphoreHandle_t xSemaphore;\n * StaticSemaphore_t xMutexBuffer;\n *\n * void vATask( void * pvParameters )\n * {\n *  // A recursive semaphore cannot be used before it is created.  Here a\n *  // recursive mutex is created using xSemaphoreCreateRecursiveMutexStatic().\n *  // The address of xMutexBuffer is passed into the function, and will hold\n *  // the mutexes data structures - so no dynamic memory allocation will be\n *  // attempted.\n *  xSemaphore = xSemaphoreCreateRecursiveMutexStatic( &xMutexBuffer );\n *\n *  // As no dynamic memory allocation was performed, xSemaphore cannot be NULL,\n *  // so there is no need to check it.\n * }\n * @endcode\n * \\defgroup xSemaphoreCreateRecursiveMutexStatic xSemaphoreCreateRecursiveMutexStatic\n * \\ingroup Semaphores\n */\n#if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_RECURSIVE_MUTEXES == 1 ) )\n    #define xSemaphoreCreateRecursiveMutexStatic( pxStaticSemaphore )    xQueueCreateMutexStatic( queueQUEUE_TYPE_RECURSIVE_MUTEX, ( pxStaticSemaphore ) )\n#endif /* configSUPPORT_STATIC_ALLOCATION */\n\n/**\n * semphr. h\n * @code{c}\n * SemaphoreHandle_t xSemaphoreCreateCounting( UBaseType_t uxMaxCount, UBaseType_t uxInitialCount );\n * @endcode\n *\n * Creates a new counting semaphore instance, and returns a handle by which the\n * new counting semaphore can be referenced.\n *\n * In many usage scenarios it is faster and more memory efficient to use a\n * direct to task notification in place of a counting semaphore!\n * https://www.FreeRTOS.org/RTOS-task-notifications.html\n *\n * Internally, within the FreeRTOS implementation, counting semaphores use a\n * block of memory, in which the counting semaphore structure is stored.  If a\n * counting semaphore is created using xSemaphoreCreateCounting() then the\n * required memory is automatically dynamically allocated inside the\n * xSemaphoreCreateCounting() function.  (see\n * https://www.FreeRTOS.org/a00111.html).  If a counting semaphore is created\n * using xSemaphoreCreateCountingStatic() then the application writer can\n * instead optionally provide the memory that will get used by the counting\n * semaphore.  xSemaphoreCreateCountingStatic() therefore allows a counting\n * semaphore to be created without using any dynamic memory allocation.\n *\n * Counting semaphores are typically used for two things:\n *\n * 1) Counting events.\n *\n *    In this usage scenario an event handler will 'give' a semaphore each time\n *    an event occurs (incrementing the semaphore count value), and a handler\n *    task will 'take' a semaphore each time it processes an event\n *    (decrementing the semaphore count value).  The count value is therefore\n *    the difference between the number of events that have occurred and the\n *    number that have been processed.  In this case it is desirable for the\n *    initial count value to be zero.\n *\n * 2) Resource management.\n *\n *    In this usage scenario the count value indicates the number of resources\n *    available.  To obtain control of a resource a task must first obtain a\n *    semaphore - decrementing the semaphore count value.  When the count value\n *    reaches zero there are no free resources.  When a task finishes with the\n *    resource it 'gives' the semaphore back - incrementing the semaphore count\n *    value.  In this case it is desirable for the initial count value to be\n *    equal to the maximum count value, indicating that all resources are free.\n *\n * @param uxMaxCount The maximum count value that can be reached.  When the\n *        semaphore reaches this value it can no longer be 'given'.\n *\n * @param uxInitialCount The count value assigned to the semaphore when it is\n *        created.\n *\n * @return Handle to the created semaphore.  Null if the semaphore could not be\n *         created.\n *\n * Example usage:\n * @code{c}\n * SemaphoreHandle_t xSemaphore;\n *\n * void vATask( void * pvParameters )\n * {\n * SemaphoreHandle_t xSemaphore = NULL;\n *\n *  // Semaphore cannot be used before a call to xSemaphoreCreateCounting().\n *  // The max value to which the semaphore can count should be 10, and the\n *  // initial value assigned to the count should be 0.\n *  xSemaphore = xSemaphoreCreateCounting( 10, 0 );\n *\n *  if( xSemaphore != NULL )\n *  {\n *      // The semaphore was created successfully.\n *      // The semaphore can now be used.\n *  }\n * }\n * @endcode\n * \\defgroup xSemaphoreCreateCounting xSemaphoreCreateCounting\n * \\ingroup Semaphores\n */\n#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n    #define xSemaphoreCreateCounting( uxMaxCount, uxInitialCount )    xQueueCreateCountingSemaphore( ( uxMaxCount ), ( uxInitialCount ) )\n#endif\n\n/**\n * semphr. h\n * @code{c}\n * SemaphoreHandle_t xSemaphoreCreateCountingStatic( UBaseType_t uxMaxCount, UBaseType_t uxInitialCount, StaticSemaphore_t *pxSemaphoreBuffer );\n * @endcode\n *\n * Creates a new counting semaphore instance, and returns a handle by which the\n * new counting semaphore can be referenced.\n *\n * In many usage scenarios it is faster and more memory efficient to use a\n * direct to task notification in place of a counting semaphore!\n * https://www.FreeRTOS.org/RTOS-task-notifications.html\n *\n * Internally, within the FreeRTOS implementation, counting semaphores use a\n * block of memory, in which the counting semaphore structure is stored.  If a\n * counting semaphore is created using xSemaphoreCreateCounting() then the\n * required memory is automatically dynamically allocated inside the\n * xSemaphoreCreateCounting() function.  (see\n * https://www.FreeRTOS.org/a00111.html).  If a counting semaphore is created\n * using xSemaphoreCreateCountingStatic() then the application writer must\n * provide the memory.  xSemaphoreCreateCountingStatic() therefore allows a\n * counting semaphore to be created without using any dynamic memory allocation.\n *\n * Counting semaphores are typically used for two things:\n *\n * 1) Counting events.\n *\n *    In this usage scenario an event handler will 'give' a semaphore each time\n *    an event occurs (incrementing the semaphore count value), and a handler\n *    task will 'take' a semaphore each time it processes an event\n *    (decrementing the semaphore count value).  The count value is therefore\n *    the difference between the number of events that have occurred and the\n *    number that have been processed.  In this case it is desirable for the\n *    initial count value to be zero.\n *\n * 2) Resource management.\n *\n *    In this usage scenario the count value indicates the number of resources\n *    available.  To obtain control of a resource a task must first obtain a\n *    semaphore - decrementing the semaphore count value.  When the count value\n *    reaches zero there are no free resources.  When a task finishes with the\n *    resource it 'gives' the semaphore back - incrementing the semaphore count\n *    value.  In this case it is desirable for the initial count value to be\n *    equal to the maximum count value, indicating that all resources are free.\n *\n * @param uxMaxCount The maximum count value that can be reached.  When the\n *        semaphore reaches this value it can no longer be 'given'.\n *\n * @param uxInitialCount The count value assigned to the semaphore when it is\n *        created.\n *\n * @param pxSemaphoreBuffer Must point to a variable of type StaticSemaphore_t,\n * which will then be used to hold the semaphore's data structure, removing the\n * need for the memory to be allocated dynamically.\n *\n * @return If the counting semaphore was successfully created then a handle to\n * the created counting semaphore is returned.  If pxSemaphoreBuffer was NULL\n * then NULL is returned.\n *\n * Example usage:\n * @code{c}\n * SemaphoreHandle_t xSemaphore;\n * StaticSemaphore_t xSemaphoreBuffer;\n *\n * void vATask( void * pvParameters )\n * {\n * SemaphoreHandle_t xSemaphore = NULL;\n *\n *  // Counting semaphore cannot be used before they have been created.  Create\n *  // a counting semaphore using xSemaphoreCreateCountingStatic().  The max\n *  // value to which the semaphore can count is 10, and the initial value\n *  // assigned to the count will be 0.  The address of xSemaphoreBuffer is\n *  // passed in and will be used to hold the semaphore structure, so no dynamic\n *  // memory allocation will be used.\n *  xSemaphore = xSemaphoreCreateCounting( 10, 0, &xSemaphoreBuffer );\n *\n *  // No memory allocation was attempted so xSemaphore cannot be NULL, so there\n *  // is no need to check its value.\n * }\n * @endcode\n * \\defgroup xSemaphoreCreateCountingStatic xSemaphoreCreateCountingStatic\n * \\ingroup Semaphores\n */\n#if ( configSUPPORT_STATIC_ALLOCATION == 1 )\n    #define xSemaphoreCreateCountingStatic( uxMaxCount, uxInitialCount, pxSemaphoreBuffer )    xQueueCreateCountingSemaphoreStatic( ( uxMaxCount ), ( uxInitialCount ), ( pxSemaphoreBuffer ) )\n#endif /* configSUPPORT_STATIC_ALLOCATION */\n\n/**\n * semphr. h\n * @code{c}\n * void vSemaphoreDelete( SemaphoreHandle_t xSemaphore );\n * @endcode\n *\n * Delete a semaphore.  This function must be used with care.  For example,\n * do not delete a mutex type semaphore if the mutex is held by a task.\n *\n * @param xSemaphore A handle to the semaphore to be deleted.\n *\n * \\defgroup vSemaphoreDelete vSemaphoreDelete\n * \\ingroup Semaphores\n */\n#define vSemaphoreDelete( xSemaphore )    vQueueDelete( ( QueueHandle_t ) ( xSemaphore ) )\n\n/**\n * semphr.h\n * @code{c}\n * TaskHandle_t xSemaphoreGetMutexHolder( SemaphoreHandle_t xMutex );\n * @endcode\n *\n * If xMutex is indeed a mutex type semaphore, return the current mutex holder.\n * If xMutex is not a mutex type semaphore, or the mutex is available (not held\n * by a task), return NULL.\n *\n * Note: This is a good way of determining if the calling task is the mutex\n * holder, but not a good way of determining the identity of the mutex holder as\n * the holder may change between the function exiting and the returned value\n * being tested.\n */\n#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )\n    #define xSemaphoreGetMutexHolder( xSemaphore )    xQueueGetMutexHolder( ( xSemaphore ) )\n#endif\n\n/**\n * semphr.h\n * @code{c}\n * TaskHandle_t xSemaphoreGetMutexHolderFromISR( SemaphoreHandle_t xMutex );\n * @endcode\n *\n * If xMutex is indeed a mutex type semaphore, return the current mutex holder.\n * If xMutex is not a mutex type semaphore, or the mutex is available (not held\n * by a task), return NULL.\n *\n */\n#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )\n    #define xSemaphoreGetMutexHolderFromISR( xSemaphore )    xQueueGetMutexHolderFromISR( ( xSemaphore ) )\n#endif\n\n/**\n * semphr.h\n * @code{c}\n * UBaseType_t uxSemaphoreGetCount( SemaphoreHandle_t xSemaphore );\n * @endcode\n *\n * If the semaphore is a counting semaphore then uxSemaphoreGetCount() returns\n * its current count value.  If the semaphore is a binary semaphore then\n * uxSemaphoreGetCount() returns 1 if the semaphore is available, and 0 if the\n * semaphore is not available.\n *\n */\n#define uxSemaphoreGetCount( xSemaphore )           uxQueueMessagesWaiting( ( QueueHandle_t ) ( xSemaphore ) )\n\n/**\n * semphr.h\n * @code{c}\n * UBaseType_t uxSemaphoreGetCountFromISR( SemaphoreHandle_t xSemaphore );\n * @endcode\n *\n * If the semaphore is a counting semaphore then uxSemaphoreGetCountFromISR() returns\n * its current count value.  If the semaphore is a binary semaphore then\n * uxSemaphoreGetCountFromISR() returns 1 if the semaphore is available, and 0 if the\n * semaphore is not available.\n *\n */\n#define uxSemaphoreGetCountFromISR( xSemaphore )    uxQueueMessagesWaitingFromISR( ( QueueHandle_t ) ( xSemaphore ) )\n\n#endif /* SEMAPHORE_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/include/stack_macros.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef STACK_MACROS_H\n#define STACK_MACROS_H\n\n/*\n * Call the stack overflow hook function if the stack of the task being swapped\n * out is currently overflowed, or looks like it might have overflowed in the\n * past.\n *\n * Setting configCHECK_FOR_STACK_OVERFLOW to 1 will cause the macro to check\n * the current stack state only - comparing the current top of stack value to\n * the stack limit.  Setting configCHECK_FOR_STACK_OVERFLOW to greater than 1\n * will also cause the last few stack bytes to be checked to ensure the value\n * to which the bytes were set when the task was created have not been\n * overwritten.  Note this second test does not guarantee that an overflowed\n * stack will always be recognised.\n */\n\n/*-----------------------------------------------------------*/\n\n/*\n * portSTACK_LIMIT_PADDING is a number of extra words to consider to be in\n * use on the stack.\n */\n#ifndef portSTACK_LIMIT_PADDING\n    #define portSTACK_LIMIT_PADDING    0\n#endif\n\n#if ( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH < 0 ) )\n\n/* Only the current stack state is to be checked. */\n    #define taskCHECK_FOR_STACK_OVERFLOW()                                                            \\\n    {                                                                                                 \\\n        /* Is the currently saved stack pointer within the stack limit? */                            \\\n        if( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack + portSTACK_LIMIT_PADDING )           \\\n        {                                                                                             \\\n            vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \\\n        }                                                                                             \\\n    }\n\n#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */\n/*-----------------------------------------------------------*/\n\n#if ( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH > 0 ) )\n\n/* Only the current stack state is to be checked. */\n    #define taskCHECK_FOR_STACK_OVERFLOW()                                                            \\\n    {                                                                                                 \\\n                                                                                                      \\\n        /* Is the currently saved stack pointer within the stack limit? */                            \\\n        if( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack - portSTACK_LIMIT_PADDING )      \\\n        {                                                                                             \\\n            vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \\\n        }                                                                                             \\\n    }\n\n#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */\n/*-----------------------------------------------------------*/\n\n#if ( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) )\n\n    #define taskCHECK_FOR_STACK_OVERFLOW()                                                            \\\n    {                                                                                                 \\\n        const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack;                       \\\n        const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5;                                        \\\n                                                                                                      \\\n        if( ( pulStack[ 0 ] != ulCheckValue ) ||                                                      \\\n            ( pulStack[ 1 ] != ulCheckValue ) ||                                                      \\\n            ( pulStack[ 2 ] != ulCheckValue ) ||                                                      \\\n            ( pulStack[ 3 ] != ulCheckValue ) )                                                       \\\n        {                                                                                             \\\n            vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \\\n        }                                                                                             \\\n    }\n\n#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */\n/*-----------------------------------------------------------*/\n\n#if ( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) )\n\n    #define taskCHECK_FOR_STACK_OVERFLOW()                                                                                                \\\n    {                                                                                                                                     \\\n        int8_t * pcEndOfStack = ( int8_t * ) pxCurrentTCB->pxEndOfStack;                                                                  \\\n        static const uint8_t ucExpectedStackBytes[] = { tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,   \\\n                                                        tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,   \\\n                                                        tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,   \\\n                                                        tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,   \\\n                                                        tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE }; \\\n                                                                                                                                          \\\n                                                                                                                                          \\\n        pcEndOfStack -= sizeof( ucExpectedStackBytes );                                                                                   \\\n                                                                                                                                          \\\n        /* Has the extremity of the task stack ever been written over? */                                                                 \\\n        if( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 )                     \\\n        {                                                                                                                                 \\\n            vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );                                     \\\n        }                                                                                                                                 \\\n    }\n\n#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */\n/*-----------------------------------------------------------*/\n\n/* Remove stack overflow macro if not being used. */\n#ifndef taskCHECK_FOR_STACK_OVERFLOW\n    #define taskCHECK_FOR_STACK_OVERFLOW()\n#endif\n\n\n\n#endif /* STACK_MACROS_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/include/stdint.readme",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef FREERTOS_STDINT\n#define FREERTOS_STDINT\n\n/*******************************************************************************\n * THIS IS NOT A FULL stdint.h IMPLEMENTATION - It only contains the definitions\n * necessary to build the FreeRTOS code.  It is provided to allow FreeRTOS to be\n * built using compilers that do not provide their own stdint.h definition.\n *\n * To use this file:\n *\n *    1) Copy this file into the directory that contains your FreeRTOSConfig.h\n *       header file, as that directory will already be in the compiler's include\n *       path.\n *\n *    2) Rename the copied file stdint.h.\n *\n */\n\ntypedef signed char int8_t;\ntypedef unsigned char uint8_t;\ntypedef short int16_t;\ntypedef unsigned short uint16_t;\ntypedef long int32_t;\ntypedef unsigned long uint32_t;\n\n#ifndef SIZE_MAX\n    #define SIZE_MAX    ( ( size_t ) -1 )\n#endif\n\n#endif /* FREERTOS_STDINT */\n"
  },
  {
    "path": "FreeRTOS-comparison/include/stream_buffer.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/*\n * Stream buffers are used to send a continuous stream of data from one task or\n * interrupt to another.  Their implementation is light weight, making them\n * particularly suited for interrupt to task and core to core communication\n * scenarios.\n *\n * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer\n * implementation (so also the message buffer implementation, as message buffers\n * are built on top of stream buffers) assumes there is only one task or\n * interrupt that will write to the buffer (the writer), and only one task or\n * interrupt that will read from the buffer (the reader).  It is safe for the\n * writer and reader to be different tasks or interrupts, but, unlike other\n * FreeRTOS objects, it is not safe to have multiple different writers or\n * multiple different readers.  If there are to be multiple different writers\n * then the application writer must place each call to a writing API function\n * (such as xStreamBufferSend()) inside a critical section and set the send\n * block time to 0.  Likewise, if there are to be multiple different readers\n * then the application writer must place each call to a reading API function\n * (such as xStreamBufferReceive()) inside a critical section section and set the\n * receive block time to 0.\n *\n */\n\n#ifndef STREAM_BUFFER_H\n#define STREAM_BUFFER_H\n\n#ifndef INC_FREERTOS_H\n    #error \"include FreeRTOS.h must appear in source files before include stream_buffer.h\"\n#endif\n\n/* *INDENT-OFF* */\n#if defined( __cplusplus )\n    extern \"C\" {\n#endif\n/* *INDENT-ON* */\n\n/**\n * Type by which stream buffers are referenced.  For example, a call to\n * xStreamBufferCreate() returns an StreamBufferHandle_t variable that can\n * then be used as a parameter to xStreamBufferSend(), xStreamBufferReceive(),\n * etc.\n */\nstruct StreamBufferDef_t;\ntypedef struct StreamBufferDef_t * StreamBufferHandle_t;\n\n/**\n *  Type used as a stream buffer's optional callback.\n */\ntypedef void (* StreamBufferCallbackFunction_t)( StreamBufferHandle_t xStreamBuffer,\n                                                 BaseType_t xIsInsideISR,\n                                                 BaseType_t * const pxHigherPriorityTaskWoken );\n\n/**\n * stream_buffer.h\n *\n * @code{c}\n * StreamBufferHandle_t xStreamBufferCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes );\n * @endcode\n *\n * Creates a new stream buffer using dynamically allocated memory.  See\n * xStreamBufferCreateStatic() for a version that uses statically allocated\n * memory (memory that is allocated at compile time).\n *\n * configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in\n * FreeRTOSConfig.h for xStreamBufferCreate() to be available.\n *\n * @param xBufferSizeBytes The total number of bytes the stream buffer will be\n * able to hold at any one time.\n *\n * @param xTriggerLevelBytes The number of bytes that must be in the stream\n * buffer before a task that is blocked on the stream buffer to wait for data is\n * moved out of the blocked state.  For example, if a task is blocked on a read\n * of an empty stream buffer that has a trigger level of 1 then the task will be\n * unblocked when a single byte is written to the buffer or the task's block\n * time expires.  As another example, if a task is blocked on a read of an empty\n * stream buffer that has a trigger level of 10 then the task will not be\n * unblocked until the stream buffer contains at least 10 bytes or the task's\n * block time expires.  If a reading task's block time expires before the\n * trigger level is reached then the task will still receive however many bytes\n * are actually available.  Setting a trigger level of 0 will result in a\n * trigger level of 1 being used.  It is not valid to specify a trigger level\n * that is greater than the buffer size.\n *\n * @param pxSendCompletedCallback Callback invoked when number of bytes at least equal to\n * trigger level is sent to the stream buffer. If the parameter is NULL, it will use the default\n * implementation provided by sbSEND_COMPLETED macro. To enable the callback,\n * configUSE_SB_COMPLETED_CALLBACK must be set to 1 in FreeRTOSConfig.h.\n *\n * @param pxReceiveCompletedCallback Callback invoked when more than zero bytes are read from a\n * stream buffer. If the parameter is NULL, it will use the default\n * implementation provided by sbRECEIVE_COMPLETED macro. To enable the callback,\n * configUSE_SB_COMPLETED_CALLBACK must be set to 1 in FreeRTOSConfig.h.\n *\n * @return If NULL is returned, then the stream buffer cannot be created\n * because there is insufficient heap memory available for FreeRTOS to allocate\n * the stream buffer data structures and storage area.  A non-NULL value being\n * returned indicates that the stream buffer has been created successfully -\n * the returned value should be stored as the handle to the created stream\n * buffer.\n *\n * Example use:\n * @code{c}\n *\n * void vAFunction( void )\n * {\n * StreamBufferHandle_t xStreamBuffer;\n * const size_t xStreamBufferSizeBytes = 100, xTriggerLevel = 10;\n *\n *  // Create a stream buffer that can hold 100 bytes.  The memory used to hold\n *  // both the stream buffer structure and the data in the stream buffer is\n *  // allocated dynamically.\n *  xStreamBuffer = xStreamBufferCreate( xStreamBufferSizeBytes, xTriggerLevel );\n *\n *  if( xStreamBuffer == NULL )\n *  {\n *      // There was not enough heap memory space available to create the\n *      // stream buffer.\n *  }\n *  else\n *  {\n *      // The stream buffer was created successfully and can now be used.\n *  }\n * }\n * @endcode\n * \\defgroup xStreamBufferCreate xStreamBufferCreate\n * \\ingroup StreamBufferManagement\n */\n\n#define xStreamBufferCreate( xBufferSizeBytes, xTriggerLevelBytes ) \\\n    xStreamBufferGenericCreate( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), pdFALSE, NULL, NULL )\n\n#if ( configUSE_SB_COMPLETED_CALLBACK == 1 )\n    #define xStreamBufferCreateWithCallback( xBufferSizeBytes, xTriggerLevelBytes, pxSendCompletedCallback, pxReceiveCompletedCallback ) \\\n    xStreamBufferGenericCreate( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), pdFALSE, ( pxSendCompletedCallback ), ( pxReceiveCompletedCallback ) )\n#endif\n\n/**\n * stream_buffer.h\n *\n * @code{c}\n * StreamBufferHandle_t xStreamBufferCreateStatic( size_t xBufferSizeBytes,\n *                                              size_t xTriggerLevelBytes,\n *                                              uint8_t *pucStreamBufferStorageArea,\n *                                              StaticStreamBuffer_t *pxStaticStreamBuffer );\n * @endcode\n * Creates a new stream buffer using statically allocated memory.  See\n * xStreamBufferCreate() for a version that uses dynamically allocated memory.\n *\n * configSUPPORT_STATIC_ALLOCATION must be set to 1 in FreeRTOSConfig.h for\n * xStreamBufferCreateStatic() to be available.\n *\n * @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the\n * pucStreamBufferStorageArea parameter.\n *\n * @param xTriggerLevelBytes The number of bytes that must be in the stream\n * buffer before a task that is blocked on the stream buffer to wait for data is\n * moved out of the blocked state.  For example, if a task is blocked on a read\n * of an empty stream buffer that has a trigger level of 1 then the task will be\n * unblocked when a single byte is written to the buffer or the task's block\n * time expires.  As another example, if a task is blocked on a read of an empty\n * stream buffer that has a trigger level of 10 then the task will not be\n * unblocked until the stream buffer contains at least 10 bytes or the task's\n * block time expires.  If a reading task's block time expires before the\n * trigger level is reached then the task will still receive however many bytes\n * are actually available.  Setting a trigger level of 0 will result in a\n * trigger level of 1 being used.  It is not valid to specify a trigger level\n * that is greater than the buffer size.\n *\n * @param pucStreamBufferStorageArea Must point to a uint8_t array that is at\n * least xBufferSizeBytes big.  This is the array to which streams are\n * copied when they are written to the stream buffer.\n *\n * @param pxStaticStreamBuffer Must point to a variable of type\n * StaticStreamBuffer_t, which will be used to hold the stream buffer's data\n * structure.\n *\n * @param pxSendCompletedCallback Callback invoked when number of bytes at least equal to\n * trigger level is sent to the stream buffer. If the parameter is NULL, it will use the default\n * implementation provided by sbSEND_COMPLETED macro. To enable the callback,\n * configUSE_SB_COMPLETED_CALLBACK must be set to 1 in FreeRTOSConfig.h.\n *\n * @param pxReceiveCompletedCallback Callback invoked when more than zero bytes are read from a\n * stream buffer. If the parameter is NULL, it will use the default\n * implementation provided by sbRECEIVE_COMPLETED macro. To enable the callback,\n * configUSE_SB_COMPLETED_CALLBACK must be set to 1 in FreeRTOSConfig.h.\n *\n * @return If the stream buffer is created successfully then a handle to the\n * created stream buffer is returned. If either pucStreamBufferStorageArea or\n * pxStaticstreamBuffer are NULL then NULL is returned.\n *\n * Example use:\n * @code{c}\n *\n * // Used to dimension the array used to hold the streams.  The available space\n * // will actually be one less than this, so 999.\n #define STORAGE_SIZE_BYTES 1000\n *\n * // Defines the memory that will actually hold the streams within the stream\n * // buffer.\n * static uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ];\n *\n * // The variable used to hold the stream buffer structure.\n * StaticStreamBuffer_t xStreamBufferStruct;\n *\n * void MyFunction( void )\n * {\n * StreamBufferHandle_t xStreamBuffer;\n * const size_t xTriggerLevel = 1;\n *\n *  xStreamBuffer = xStreamBufferCreateStatic( sizeof( ucStorageBuffer ),\n *                                             xTriggerLevel,\n *                                             ucStorageBuffer,\n *                                             &xStreamBufferStruct );\n *\n *  // As neither the pucStreamBufferStorageArea or pxStaticStreamBuffer\n *  // parameters were NULL, xStreamBuffer will not be NULL, and can be used to\n *  // reference the created stream buffer in other stream buffer API calls.\n *\n *  // Other code that uses the stream buffer can go here.\n * }\n *\n * @endcode\n * \\defgroup xStreamBufferCreateStatic xStreamBufferCreateStatic\n * \\ingroup StreamBufferManagement\n */\n\n#define xStreamBufferCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pucStreamBufferStorageArea, pxStaticStreamBuffer ) \\\n    xStreamBufferGenericCreateStatic( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), pdFALSE, ( pucStreamBufferStorageArea ), ( pxStaticStreamBuffer ), NULL, NULL )\n\n#if ( configUSE_SB_COMPLETED_CALLBACK == 1 )\n    #define xStreamBufferCreateStaticWithCallback( xBufferSizeBytes, xTriggerLevelBytes, pucStreamBufferStorageArea, pxStaticStreamBuffer, pxSendCompletedCallback, pxReceiveCompletedCallback ) \\\n    xStreamBufferGenericCreateStatic( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), pdFALSE, ( pucStreamBufferStorageArea ), ( pxStaticStreamBuffer ), ( pxSendCompletedCallback ), ( pxReceiveCompletedCallback ) )\n#endif\n\n/**\n * stream_buffer.h\n *\n * @code{c}\n * size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,\n *                        const void *pvTxData,\n *                        size_t xDataLengthBytes,\n *                        TickType_t xTicksToWait );\n * @endcode\n *\n * Sends bytes to a stream buffer.  The bytes are copied into the stream buffer.\n *\n * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer\n * implementation (so also the message buffer implementation, as message buffers\n * are built on top of stream buffers) assumes there is only one task or\n * interrupt that will write to the buffer (the writer), and only one task or\n * interrupt that will read from the buffer (the reader).  It is safe for the\n * writer and reader to be different tasks or interrupts, but, unlike other\n * FreeRTOS objects, it is not safe to have multiple different writers or\n * multiple different readers.  If there are to be multiple different writers\n * then the application writer must place each call to a writing API function\n * (such as xStreamBufferSend()) inside a critical section and set the send\n * block time to 0.  Likewise, if there are to be multiple different readers\n * then the application writer must place each call to a reading API function\n * (such as xStreamBufferReceive()) inside a critical section and set the receive\n * block time to 0.\n *\n * Use xStreamBufferSend() to write to a stream buffer from a task.  Use\n * xStreamBufferSendFromISR() to write to a stream buffer from an interrupt\n * service routine (ISR).\n *\n * @param xStreamBuffer The handle of the stream buffer to which a stream is\n * being sent.\n *\n * @param pvTxData A pointer to the buffer that holds the bytes to be copied\n * into the stream buffer.\n *\n * @param xDataLengthBytes   The maximum number of bytes to copy from pvTxData\n * into the stream buffer.\n *\n * @param xTicksToWait The maximum amount of time the task should remain in the\n * Blocked state to wait for enough space to become available in the stream\n * buffer, should the stream buffer contain too little space to hold the\n * another xDataLengthBytes bytes.  The block time is specified in tick periods,\n * so the absolute time it represents is dependent on the tick frequency.  The\n * macro pdMS_TO_TICKS() can be used to convert a time specified in milliseconds\n * into a time specified in ticks.  Setting xTicksToWait to portMAX_DELAY will\n * cause the task to wait indefinitely (without timing out), provided\n * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h.  If a task times out\n * before it can write all xDataLengthBytes into the buffer it will still write\n * as many bytes as possible.  A task does not use any CPU time when it is in\n * the blocked state.\n *\n * @return The number of bytes written to the stream buffer.  If a task times\n * out before it can write all xDataLengthBytes into the buffer it will still\n * write as many bytes as possible.\n *\n * Example use:\n * @code{c}\n * void vAFunction( StreamBufferHandle_t xStreamBuffer )\n * {\n * size_t xBytesSent;\n * uint8_t ucArrayToSend[] = { 0, 1, 2, 3 };\n * char *pcStringToSend = \"String to send\";\n * const TickType_t x100ms = pdMS_TO_TICKS( 100 );\n *\n *  // Send an array to the stream buffer, blocking for a maximum of 100ms to\n *  // wait for enough space to be available in the stream buffer.\n *  xBytesSent = xStreamBufferSend( xStreamBuffer, ( void * ) ucArrayToSend, sizeof( ucArrayToSend ), x100ms );\n *\n *  if( xBytesSent != sizeof( ucArrayToSend ) )\n *  {\n *      // The call to xStreamBufferSend() times out before there was enough\n *      // space in the buffer for the data to be written, but it did\n *      // successfully write xBytesSent bytes.\n *  }\n *\n *  // Send the string to the stream buffer.  Return immediately if there is not\n *  // enough space in the buffer.\n *  xBytesSent = xStreamBufferSend( xStreamBuffer, ( void * ) pcStringToSend, strlen( pcStringToSend ), 0 );\n *\n *  if( xBytesSent != strlen( pcStringToSend ) )\n *  {\n *      // The entire string could not be added to the stream buffer because\n *      // there was not enough free space in the buffer, but xBytesSent bytes\n *      // were sent.  Could try again to send the remaining bytes.\n *  }\n * }\n * @endcode\n * \\defgroup xStreamBufferSend xStreamBufferSend\n * \\ingroup StreamBufferManagement\n */\nsize_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,\n                          const void * pvTxData,\n                          size_t xDataLengthBytes,\n                          TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;\n\n/**\n * stream_buffer.h\n *\n * @code{c}\n * size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,\n *                               const void *pvTxData,\n *                               size_t xDataLengthBytes,\n *                               BaseType_t *pxHigherPriorityTaskWoken );\n * @endcode\n *\n * Interrupt safe version of the API function that sends a stream of bytes to\n * the stream buffer.\n *\n * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer\n * implementation (so also the message buffer implementation, as message buffers\n * are built on top of stream buffers) assumes there is only one task or\n * interrupt that will write to the buffer (the writer), and only one task or\n * interrupt that will read from the buffer (the reader).  It is safe for the\n * writer and reader to be different tasks or interrupts, but, unlike other\n * FreeRTOS objects, it is not safe to have multiple different writers or\n * multiple different readers.  If there are to be multiple different writers\n * then the application writer must place each call to a writing API function\n * (such as xStreamBufferSend()) inside a critical section and set the send\n * block time to 0.  Likewise, if there are to be multiple different readers\n * then the application writer must place each call to a reading API function\n * (such as xStreamBufferReceive()) inside a critical section and set the receive\n * block time to 0.\n *\n * Use xStreamBufferSend() to write to a stream buffer from a task.  Use\n * xStreamBufferSendFromISR() to write to a stream buffer from an interrupt\n * service routine (ISR).\n *\n * @param xStreamBuffer The handle of the stream buffer to which a stream is\n * being sent.\n *\n * @param pvTxData A pointer to the data that is to be copied into the stream\n * buffer.\n *\n * @param xDataLengthBytes The maximum number of bytes to copy from pvTxData\n * into the stream buffer.\n *\n * @param pxHigherPriorityTaskWoken  It is possible that a stream buffer will\n * have a task blocked on it waiting for data.  Calling\n * xStreamBufferSendFromISR() can make data available, and so cause a task that\n * was waiting for data to leave the Blocked state.  If calling\n * xStreamBufferSendFromISR() causes a task to leave the Blocked state, and the\n * unblocked task has a priority higher than the currently executing task (the\n * task that was interrupted), then, internally, xStreamBufferSendFromISR()\n * will set *pxHigherPriorityTaskWoken to pdTRUE.  If\n * xStreamBufferSendFromISR() sets this value to pdTRUE, then normally a\n * context switch should be performed before the interrupt is exited.  This will\n * ensure that the interrupt returns directly to the highest priority Ready\n * state task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it\n * is passed into the function.  See the example code below for an example.\n *\n * @return The number of bytes actually written to the stream buffer, which will\n * be less than xDataLengthBytes if the stream buffer didn't have enough free\n * space for all the bytes to be written.\n *\n * Example use:\n * @code{c}\n * // A stream buffer that has already been created.\n * StreamBufferHandle_t xStreamBuffer;\n *\n * void vAnInterruptServiceRoutine( void )\n * {\n * size_t xBytesSent;\n * char *pcStringToSend = \"String to send\";\n * BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE.\n *\n *  // Attempt to send the string to the stream buffer.\n *  xBytesSent = xStreamBufferSendFromISR( xStreamBuffer,\n *                                         ( void * ) pcStringToSend,\n *                                         strlen( pcStringToSend ),\n *                                         &xHigherPriorityTaskWoken );\n *\n *  if( xBytesSent != strlen( pcStringToSend ) )\n *  {\n *      // There was not enough free space in the stream buffer for the entire\n *      // string to be written, ut xBytesSent bytes were written.\n *  }\n *\n *  // If xHigherPriorityTaskWoken was set to pdTRUE inside\n *  // xStreamBufferSendFromISR() then a task that has a priority above the\n *  // priority of the currently executing task was unblocked and a context\n *  // switch should be performed to ensure the ISR returns to the unblocked\n *  // task.  In most FreeRTOS ports this is done by simply passing\n *  // xHigherPriorityTaskWoken into portYIELD_FROM_ISR(), which will test the\n *  // variables value, and perform the context switch if necessary.  Check the\n *  // documentation for the port in use for port specific instructions.\n *  portYIELD_FROM_ISR( xHigherPriorityTaskWoken );\n * }\n * @endcode\n * \\defgroup xStreamBufferSendFromISR xStreamBufferSendFromISR\n * \\ingroup StreamBufferManagement\n */\nsize_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,\n                                 const void * pvTxData,\n                                 size_t xDataLengthBytes,\n                                 BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;\n\n/**\n * stream_buffer.h\n *\n * @code{c}\n * size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,\n *                           void *pvRxData,\n *                           size_t xBufferLengthBytes,\n *                           TickType_t xTicksToWait );\n * @endcode\n *\n * Receives bytes from a stream buffer.\n *\n * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer\n * implementation (so also the message buffer implementation, as message buffers\n * are built on top of stream buffers) assumes there is only one task or\n * interrupt that will write to the buffer (the writer), and only one task or\n * interrupt that will read from the buffer (the reader).  It is safe for the\n * writer and reader to be different tasks or interrupts, but, unlike other\n * FreeRTOS objects, it is not safe to have multiple different writers or\n * multiple different readers.  If there are to be multiple different writers\n * then the application writer must place each call to a writing API function\n * (such as xStreamBufferSend()) inside a critical section and set the send\n * block time to 0.  Likewise, if there are to be multiple different readers\n * then the application writer must place each call to a reading API function\n * (such as xStreamBufferReceive()) inside a critical section and set the receive\n * block time to 0.\n *\n * Use xStreamBufferReceive() to read from a stream buffer from a task.  Use\n * xStreamBufferReceiveFromISR() to read from a stream buffer from an\n * interrupt service routine (ISR).\n *\n * @param xStreamBuffer The handle of the stream buffer from which bytes are to\n * be received.\n *\n * @param pvRxData A pointer to the buffer into which the received bytes will be\n * copied.\n *\n * @param xBufferLengthBytes The length of the buffer pointed to by the\n * pvRxData parameter.  This sets the maximum number of bytes to receive in one\n * call.  xStreamBufferReceive will return as many bytes as possible up to a\n * maximum set by xBufferLengthBytes.\n *\n * @param xTicksToWait The maximum amount of time the task should remain in the\n * Blocked state to wait for data to become available if the stream buffer is\n * empty.  xStreamBufferReceive() will return immediately if xTicksToWait is\n * zero.  The block time is specified in tick periods, so the absolute time it\n * represents is dependent on the tick frequency.  The macro pdMS_TO_TICKS() can\n * be used to convert a time specified in milliseconds into a time specified in\n * ticks.  Setting xTicksToWait to portMAX_DELAY will cause the task to wait\n * indefinitely (without timing out), provided INCLUDE_vTaskSuspend is set to 1\n * in FreeRTOSConfig.h.  A task does not use any CPU time when it is in the\n * Blocked state.\n *\n * @return The number of bytes actually read from the stream buffer, which will\n * be less than xBufferLengthBytes if the call to xStreamBufferReceive() timed\n * out before xBufferLengthBytes were available.\n *\n * Example use:\n * @code{c}\n * void vAFunction( StreamBuffer_t xStreamBuffer )\n * {\n * uint8_t ucRxData[ 20 ];\n * size_t xReceivedBytes;\n * const TickType_t xBlockTime = pdMS_TO_TICKS( 20 );\n *\n *  // Receive up to another sizeof( ucRxData ) bytes from the stream buffer.\n *  // Wait in the Blocked state (so not using any CPU processing time) for a\n *  // maximum of 100ms for the full sizeof( ucRxData ) number of bytes to be\n *  // available.\n *  xReceivedBytes = xStreamBufferReceive( xStreamBuffer,\n *                                         ( void * ) ucRxData,\n *                                         sizeof( ucRxData ),\n *                                         xBlockTime );\n *\n *  if( xReceivedBytes > 0 )\n *  {\n *      // A ucRxData contains another xReceivedBytes bytes of data, which can\n *      // be processed here....\n *  }\n * }\n * @endcode\n * \\defgroup xStreamBufferReceive xStreamBufferReceive\n * \\ingroup StreamBufferManagement\n */\nsize_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,\n                             void * pvRxData,\n                             size_t xBufferLengthBytes,\n                             TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;\n\n/**\n * stream_buffer.h\n *\n * @code{c}\n * size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,\n *                                  void *pvRxData,\n *                                  size_t xBufferLengthBytes,\n *                                  BaseType_t *pxHigherPriorityTaskWoken );\n * @endcode\n *\n * An interrupt safe version of the API function that receives bytes from a\n * stream buffer.\n *\n * Use xStreamBufferReceive() to read bytes from a stream buffer from a task.\n * Use xStreamBufferReceiveFromISR() to read bytes from a stream buffer from an\n * interrupt service routine (ISR).\n *\n * @param xStreamBuffer The handle of the stream buffer from which a stream\n * is being received.\n *\n * @param pvRxData A pointer to the buffer into which the received bytes are\n * copied.\n *\n * @param xBufferLengthBytes The length of the buffer pointed to by the\n * pvRxData parameter.  This sets the maximum number of bytes to receive in one\n * call.  xStreamBufferReceive will return as many bytes as possible up to a\n * maximum set by xBufferLengthBytes.\n *\n * @param pxHigherPriorityTaskWoken  It is possible that a stream buffer will\n * have a task blocked on it waiting for space to become available.  Calling\n * xStreamBufferReceiveFromISR() can make space available, and so cause a task\n * that is waiting for space to leave the Blocked state.  If calling\n * xStreamBufferReceiveFromISR() causes a task to leave the Blocked state, and\n * the unblocked task has a priority higher than the currently executing task\n * (the task that was interrupted), then, internally,\n * xStreamBufferReceiveFromISR() will set *pxHigherPriorityTaskWoken to pdTRUE.\n * If xStreamBufferReceiveFromISR() sets this value to pdTRUE, then normally a\n * context switch should be performed before the interrupt is exited.  That will\n * ensure the interrupt returns directly to the highest priority Ready state\n * task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it is\n * passed into the function.  See the code example below for an example.\n *\n * @return The number of bytes read from the stream buffer, if any.\n *\n * Example use:\n * @code{c}\n * // A stream buffer that has already been created.\n * StreamBuffer_t xStreamBuffer;\n *\n * void vAnInterruptServiceRoutine( void )\n * {\n * uint8_t ucRxData[ 20 ];\n * size_t xReceivedBytes;\n * BaseType_t xHigherPriorityTaskWoken = pdFALSE;  // Initialised to pdFALSE.\n *\n *  // Receive the next stream from the stream buffer.\n *  xReceivedBytes = xStreamBufferReceiveFromISR( xStreamBuffer,\n *                                                ( void * ) ucRxData,\n *                                                sizeof( ucRxData ),\n *                                                &xHigherPriorityTaskWoken );\n *\n *  if( xReceivedBytes > 0 )\n *  {\n *      // ucRxData contains xReceivedBytes read from the stream buffer.\n *      // Process the stream here....\n *  }\n *\n *  // If xHigherPriorityTaskWoken was set to pdTRUE inside\n *  // xStreamBufferReceiveFromISR() then a task that has a priority above the\n *  // priority of the currently executing task was unblocked and a context\n *  // switch should be performed to ensure the ISR returns to the unblocked\n *  // task.  In most FreeRTOS ports this is done by simply passing\n *  // xHigherPriorityTaskWoken into portYIELD_FROM_ISR(), which will test the\n *  // variables value, and perform the context switch if necessary.  Check the\n *  // documentation for the port in use for port specific instructions.\n *  portYIELD_FROM_ISR( xHigherPriorityTaskWoken );\n * }\n * @endcode\n * \\defgroup xStreamBufferReceiveFromISR xStreamBufferReceiveFromISR\n * \\ingroup StreamBufferManagement\n */\nsize_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,\n                                    void * pvRxData,\n                                    size_t xBufferLengthBytes,\n                                    BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;\n\n/**\n * stream_buffer.h\n *\n * @code{c}\n * void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer );\n * @endcode\n *\n * Deletes a stream buffer that was previously created using a call to\n * xStreamBufferCreate() or xStreamBufferCreateStatic().  If the stream\n * buffer was created using dynamic memory (that is, by xStreamBufferCreate()),\n * then the allocated memory is freed.\n *\n * A stream buffer handle must not be used after the stream buffer has been\n * deleted.\n *\n * @param xStreamBuffer The handle of the stream buffer to be deleted.\n *\n * \\defgroup vStreamBufferDelete vStreamBufferDelete\n * \\ingroup StreamBufferManagement\n */\nvoid vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;\n\n/**\n * stream_buffer.h\n *\n * @code{c}\n * BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer );\n * @endcode\n *\n * Queries a stream buffer to see if it is full.  A stream buffer is full if it\n * does not have any free space, and therefore cannot accept any more data.\n *\n * @param xStreamBuffer The handle of the stream buffer being queried.\n *\n * @return If the stream buffer is full then pdTRUE is returned.  Otherwise\n * pdFALSE is returned.\n *\n * \\defgroup xStreamBufferIsFull xStreamBufferIsFull\n * \\ingroup StreamBufferManagement\n */\nBaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;\n\n/**\n * stream_buffer.h\n *\n * @code{c}\n * BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer );\n * @endcode\n *\n * Queries a stream buffer to see if it is empty.  A stream buffer is empty if\n * it does not contain any data.\n *\n * @param xStreamBuffer The handle of the stream buffer being queried.\n *\n * @return If the stream buffer is empty then pdTRUE is returned.  Otherwise\n * pdFALSE is returned.\n *\n * \\defgroup xStreamBufferIsEmpty xStreamBufferIsEmpty\n * \\ingroup StreamBufferManagement\n */\nBaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;\n\n/**\n * stream_buffer.h\n *\n * @code{c}\n * BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer );\n * @endcode\n *\n * Resets a stream buffer to its initial, empty, state.  Any data that was in\n * the stream buffer is discarded.  A stream buffer can only be reset if there\n * are no tasks blocked waiting to either send to or receive from the stream\n * buffer.\n *\n * @param xStreamBuffer The handle of the stream buffer being reset.\n *\n * @return If the stream buffer is reset then pdPASS is returned.  If there was\n * a task blocked waiting to send to or read from the stream buffer then the\n * stream buffer is not reset and pdFAIL is returned.\n *\n * \\defgroup xStreamBufferReset xStreamBufferReset\n * \\ingroup StreamBufferManagement\n */\nBaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;\n\n/**\n * stream_buffer.h\n *\n * @code{c}\n * size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer );\n * @endcode\n *\n * Queries a stream buffer to see how much free space it contains, which is\n * equal to the amount of data that can be sent to the stream buffer before it\n * is full.\n *\n * @param xStreamBuffer The handle of the stream buffer being queried.\n *\n * @return The number of bytes that can be written to the stream buffer before\n * the stream buffer would be full.\n *\n * \\defgroup xStreamBufferSpacesAvailable xStreamBufferSpacesAvailable\n * \\ingroup StreamBufferManagement\n */\nsize_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;\n\n/**\n * stream_buffer.h\n *\n * @code{c}\n * size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer );\n * @endcode\n *\n * Queries a stream buffer to see how much data it contains, which is equal to\n * the number of bytes that can be read from the stream buffer before the stream\n * buffer would be empty.\n *\n * @param xStreamBuffer The handle of the stream buffer being queried.\n *\n * @return The number of bytes that can be read from the stream buffer before\n * the stream buffer would be empty.\n *\n * \\defgroup xStreamBufferBytesAvailable xStreamBufferBytesAvailable\n * \\ingroup StreamBufferManagement\n */\nsize_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;\n\n/**\n * stream_buffer.h\n *\n * @code{c}\n * BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel );\n * @endcode\n *\n * A stream buffer's trigger level is the number of bytes that must be in the\n * stream buffer before a task that is blocked on the stream buffer to\n * wait for data is moved out of the blocked state.  For example, if a task is\n * blocked on a read of an empty stream buffer that has a trigger level of 1\n * then the task will be unblocked when a single byte is written to the buffer\n * or the task's block time expires.  As another example, if a task is blocked\n * on a read of an empty stream buffer that has a trigger level of 10 then the\n * task will not be unblocked until the stream buffer contains at least 10 bytes\n * or the task's block time expires.  If a reading task's block time expires\n * before the trigger level is reached then the task will still receive however\n * many bytes are actually available.  Setting a trigger level of 0 will result\n * in a trigger level of 1 being used.  It is not valid to specify a trigger\n * level that is greater than the buffer size.\n *\n * A trigger level is set when the stream buffer is created, and can be modified\n * using xStreamBufferSetTriggerLevel().\n *\n * @param xStreamBuffer The handle of the stream buffer being updated.\n *\n * @param xTriggerLevel The new trigger level for the stream buffer.\n *\n * @return If xTriggerLevel was less than or equal to the stream buffer's length\n * then the trigger level will be updated and pdTRUE is returned.  Otherwise\n * pdFALSE is returned.\n *\n * \\defgroup xStreamBufferSetTriggerLevel xStreamBufferSetTriggerLevel\n * \\ingroup StreamBufferManagement\n */\nBaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,\n                                         size_t xTriggerLevel ) PRIVILEGED_FUNCTION;\n\n/**\n * stream_buffer.h\n *\n * @code{c}\n * BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );\n * @endcode\n *\n * For advanced users only.\n *\n * The sbSEND_COMPLETED() macro is called from within the FreeRTOS APIs when\n * data is sent to a message buffer or stream buffer.  If there was a task that\n * was blocked on the message or stream buffer waiting for data to arrive then\n * the sbSEND_COMPLETED() macro sends a notification to the task to remove it\n * from the Blocked state.  xStreamBufferSendCompletedFromISR() does the same\n * thing.  It is provided to enable application writers to implement their own\n * version of sbSEND_COMPLETED(), and MUST NOT BE USED AT ANY OTHER TIME.\n *\n * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for\n * additional information.\n *\n * @param xStreamBuffer The handle of the stream buffer to which data was\n * written.\n *\n * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be\n * initialised to pdFALSE before it is passed into\n * xStreamBufferSendCompletedFromISR().  If calling\n * xStreamBufferSendCompletedFromISR() removes a task from the Blocked state,\n * and the task has a priority above the priority of the currently running task,\n * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a\n * context switch should be performed before exiting the ISR.\n *\n * @return If a task was removed from the Blocked state then pdTRUE is returned.\n * Otherwise pdFALSE is returned.\n *\n * \\defgroup xStreamBufferSendCompletedFromISR xStreamBufferSendCompletedFromISR\n * \\ingroup StreamBufferManagement\n */\nBaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer,\n                                              BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;\n\n/**\n * stream_buffer.h\n *\n * @code{c}\n * BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );\n * @endcode\n *\n * For advanced users only.\n *\n * The sbRECEIVE_COMPLETED() macro is called from within the FreeRTOS APIs when\n * data is read out of a message buffer or stream buffer.  If there was a task\n * that was blocked on the message or stream buffer waiting for data to arrive\n * then the sbRECEIVE_COMPLETED() macro sends a notification to the task to\n * remove it from the Blocked state.  xStreamBufferReceiveCompletedFromISR()\n * does the same thing.  It is provided to enable application writers to\n * implement their own version of sbRECEIVE_COMPLETED(), and MUST NOT BE USED AT\n * ANY OTHER TIME.\n *\n * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for\n * additional information.\n *\n * @param xStreamBuffer The handle of the stream buffer from which data was\n * read.\n *\n * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be\n * initialised to pdFALSE before it is passed into\n * xStreamBufferReceiveCompletedFromISR().  If calling\n * xStreamBufferReceiveCompletedFromISR() removes a task from the Blocked state,\n * and the task has a priority above the priority of the currently running task,\n * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a\n * context switch should be performed before exiting the ISR.\n *\n * @return If a task was removed from the Blocked state then pdTRUE is returned.\n * Otherwise pdFALSE is returned.\n *\n * \\defgroup xStreamBufferReceiveCompletedFromISR xStreamBufferReceiveCompletedFromISR\n * \\ingroup StreamBufferManagement\n */\nBaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer,\n                                                 BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;\n\n/* Functions below here are not part of the public API. */\nStreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes,\n                                                 size_t xTriggerLevelBytes,\n                                                 BaseType_t xIsMessageBuffer,\n                                                 StreamBufferCallbackFunction_t pxSendCompletedCallback,\n                                                 StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) PRIVILEGED_FUNCTION;\n\n\nStreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,\n                                                       size_t xTriggerLevelBytes,\n                                                       BaseType_t xIsMessageBuffer,\n                                                       uint8_t * const pucStreamBufferStorageArea,\n                                                       StaticStreamBuffer_t * const pxStaticStreamBuffer,\n                                                       StreamBufferCallbackFunction_t pxSendCompletedCallback,\n                                                       StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) PRIVILEGED_FUNCTION;\n\nsize_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;\n\n#if ( configUSE_TRACE_FACILITY == 1 )\n    void vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer,\n                                             UBaseType_t uxStreamBufferNumber ) PRIVILEGED_FUNCTION;\n    UBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;\n    uint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;\n#endif\n\n/* *INDENT-OFF* */\n#if defined( __cplusplus )\n    }\n#endif\n/* *INDENT-ON* */\n\n#endif /* !defined( STREAM_BUFFER_H ) */\n"
  },
  {
    "path": "FreeRTOS-comparison/include/task.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n\n#ifndef INC_TASK_H\n#define INC_TASK_H\n\n#ifndef INC_FREERTOS_H\n    #error \"include FreeRTOS.h must appear in source files before include task.h\"\n#endif\n\n#include \"list.h\"\n\n/* *INDENT-OFF* */\n#ifdef __cplusplus\n    extern \"C\" {\n#endif\n/* *INDENT-ON* */\n\n/*-----------------------------------------------------------\n* MACROS AND DEFINITIONS\n*----------------------------------------------------------*/\n\n/*\n * If tskKERNEL_VERSION_NUMBER ends with + it represents the version in development\n * after the numbered release.\n *\n * The tskKERNEL_VERSION_MAJOR, tskKERNEL_VERSION_MINOR, tskKERNEL_VERSION_BUILD\n * values will reflect the last released version number.\n */\n#define tskKERNEL_VERSION_NUMBER       \"V10.5.1\"\n#define tskKERNEL_VERSION_MAJOR        10\n#define tskKERNEL_VERSION_MINOR        5\n#define tskKERNEL_VERSION_BUILD        1\n\n/* MPU region parameters passed in ulParameters\n * of MemoryRegion_t struct. */\n#define tskMPU_REGION_READ_ONLY        ( 1UL << 0UL )\n#define tskMPU_REGION_READ_WRITE       ( 1UL << 1UL )\n#define tskMPU_REGION_EXECUTE_NEVER    ( 1UL << 2UL )\n#define tskMPU_REGION_NORMAL_MEMORY    ( 1UL << 3UL )\n#define tskMPU_REGION_DEVICE_MEMORY    ( 1UL << 4UL )\n\n/* The direct to task notification feature used to have only a single notification\n * per task.  Now there is an array of notifications per task that is dimensioned by\n * configTASK_NOTIFICATION_ARRAY_ENTRIES.  For backward compatibility, any use of the\n * original direct to task notification defaults to using the first index in the\n * array. */\n#define tskDEFAULT_INDEX_TO_NOTIFY     ( 0 )\n\n/**\n * task. h\n *\n * Type by which tasks are referenced.  For example, a call to xTaskCreate\n * returns (via a pointer parameter) an TaskHandle_t variable that can then\n * be used as a parameter to vTaskDelete to delete the task.\n *\n * \\defgroup TaskHandle_t TaskHandle_t\n * \\ingroup Tasks\n */\nstruct tskTaskControlBlock; /* The old naming convention is used to prevent breaking kernel aware debuggers. */\ntypedef struct tskTaskControlBlock * TaskHandle_t;\n\n/*\n * Defines the prototype to which the application task hook function must\n * conform.\n */\ntypedef BaseType_t (* TaskHookFunction_t)( void * );\n\n/* Task states returned by eTaskGetState. */\ntypedef enum\n{\n    eRunning = 0, /* A task is querying the state of itself, so must be running. */\n    eReady,       /* The task being queried is in a ready or pending ready list. */\n    eBlocked,     /* The task being queried is in the Blocked state. */\n    eSuspended,   /* The task being queried is in the Suspended state, or is in the Blocked state with an infinite time out. */\n    eDeleted,     /* The task being queried has been deleted, but its TCB has not yet been freed. */\n    eInvalid      /* Used as an 'invalid state' value. */\n} eTaskState;\n\n/* Actions that can be performed when vTaskNotify() is called. */\ntypedef enum\n{\n    eNoAction = 0,            /* Notify the task without updating its notify value. */\n    eSetBits,                 /* Set bits in the task's notification value. */\n    eIncrement,               /* Increment the task's notification value. */\n    eSetValueWithOverwrite,   /* Set the task's notification value to a specific value even if the previous value has not yet been read by the task. */\n    eSetValueWithoutOverwrite /* Set the task's notification value if the previous value has been read by the task. */\n} eNotifyAction;\n\n/*\n * Used internally only.\n */\ntypedef struct xTIME_OUT\n{\n    BaseType_t xOverflowCount;\n    TickType_t xTimeOnEntering;\n} TimeOut_t;\n\n/*\n * Defines the memory ranges allocated to the task when an MPU is used.\n */\ntypedef struct xMEMORY_REGION\n{\n    void * pvBaseAddress;\n    uint32_t ulLengthInBytes;\n    uint32_t ulParameters;\n} MemoryRegion_t;\n\n/*\n * Parameters required to create an MPU protected task.\n */\ntypedef struct xTASK_PARAMETERS\n{\n    TaskFunction_t pvTaskCode;\n    const char * pcName; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n    configSTACK_DEPTH_TYPE usStackDepth;\n    void * pvParameters;\n    UBaseType_t uxPriority;\n    StackType_t * puxStackBuffer;\n    MemoryRegion_t xRegions[ portNUM_CONFIGURABLE_REGIONS ];\n    #if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )\n        StaticTask_t * const pxTaskBuffer;\n    #endif\n} TaskParameters_t;\n\n/* Used with the uxTaskGetSystemState() function to return the state of each task\n * in the system. */\ntypedef struct xTASK_STATUS\n{\n    TaskHandle_t xHandle;                         /* The handle of the task to which the rest of the information in the structure relates. */\n    const char * pcTaskName;                      /* A pointer to the task's name.  This value will be invalid if the task was deleted since the structure was populated! */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n    UBaseType_t xTaskNumber;                      /* A number unique to the task. */\n    eTaskState eCurrentState;                     /* The state in which the task existed when the structure was populated. */\n    UBaseType_t uxCurrentPriority;                /* The priority at which the task was running (may be inherited) when the structure was populated. */\n    UBaseType_t uxBasePriority;                   /* The priority to which the task will return if the task's current priority has been inherited to avoid unbounded priority inversion when obtaining a mutex.  Only valid if configUSE_MUTEXES is defined as 1 in FreeRTOSConfig.h. */\n    configRUN_TIME_COUNTER_TYPE ulRunTimeCounter; /* The total run time allocated to the task so far, as defined by the run time stats clock.  See https://www.FreeRTOS.org/rtos-run-time-stats.html.  Only valid when configGENERATE_RUN_TIME_STATS is defined as 1 in FreeRTOSConfig.h. */\n    StackType_t * pxStackBase;                    /* Points to the lowest address of the task's stack area. */\n    #if ( ( portSTACK_GROWTH > 0 ) && ( configRECORD_STACK_HIGH_ADDRESS == 1 ) )\n        StackType_t * pxTopOfStack;               /* Points to the top address of the task's stack area. */\n        StackType_t * pxEndOfStack;               /* Points to the end address of the task's stack area. */\n    #endif\n    configSTACK_DEPTH_TYPE usStackHighWaterMark;  /* The minimum amount of stack space that has remained for the task since the task was created.  The closer this value is to zero the closer the task has come to overflowing its stack. */\n} TaskStatus_t;\n\n/* Possible return values for eTaskConfirmSleepModeStatus(). */\ntypedef enum\n{\n    eAbortSleep = 0,           /* A task has been made ready or a context switch pended since portSUPPRESS_TICKS_AND_SLEEP() was called - abort entering a sleep mode. */\n    eStandardSleep,            /* Enter a sleep mode that will not last any longer than the expected idle time. */\n    #if ( INCLUDE_vTaskSuspend == 1 )\n        eNoTasksWaitingTimeout /* No tasks are waiting for a timeout so it is safe to enter a sleep mode that can only be exited by an external interrupt. */\n    #endif /* INCLUDE_vTaskSuspend */\n} eSleepModeStatus;\n\n/**\n * Defines the priority used by the idle task.  This must not be modified.\n *\n * \\ingroup TaskUtils\n */\n#define tskIDLE_PRIORITY    ( ( UBaseType_t ) 0U )\n\n/**\n * task. h\n *\n * Macro for forcing a context switch.\n *\n * \\defgroup taskYIELD taskYIELD\n * \\ingroup SchedulerControl\n */\n#define taskYIELD()                        portYIELD()\n\n/**\n * task. h\n *\n * Macro to mark the start of a critical code region.  Preemptive context\n * switches cannot occur when in a critical region.\n *\n * NOTE: This may alter the stack (depending on the portable implementation)\n * so must be used with care!\n *\n * \\defgroup taskENTER_CRITICAL taskENTER_CRITICAL\n * \\ingroup SchedulerControl\n */\n#define taskENTER_CRITICAL()               portENTER_CRITICAL()\n#define taskENTER_CRITICAL_FROM_ISR()      portSET_INTERRUPT_MASK_FROM_ISR()\n\n/**\n * task. h\n *\n * Macro to mark the end of a critical code region.  Preemptive context\n * switches cannot occur when in a critical region.\n *\n * NOTE: This may alter the stack (depending on the portable implementation)\n * so must be used with care!\n *\n * \\defgroup taskEXIT_CRITICAL taskEXIT_CRITICAL\n * \\ingroup SchedulerControl\n */\n#define taskEXIT_CRITICAL()                portEXIT_CRITICAL()\n#define taskEXIT_CRITICAL_FROM_ISR( x )    portCLEAR_INTERRUPT_MASK_FROM_ISR( x )\n\n/**\n * task. h\n *\n * Macro to disable all maskable interrupts.\n *\n * \\defgroup taskDISABLE_INTERRUPTS taskDISABLE_INTERRUPTS\n * \\ingroup SchedulerControl\n */\n#define taskDISABLE_INTERRUPTS()           portDISABLE_INTERRUPTS()\n\n/**\n * task. h\n *\n * Macro to enable microcontroller interrupts.\n *\n * \\defgroup taskENABLE_INTERRUPTS taskENABLE_INTERRUPTS\n * \\ingroup SchedulerControl\n */\n#define taskENABLE_INTERRUPTS()            portENABLE_INTERRUPTS()\n\n/* Definitions returned by xTaskGetSchedulerState().  taskSCHEDULER_SUSPENDED is\n * 0 to generate more optimal code when configASSERT() is defined as the constant\n * is used in assert() statements. */\n#define taskSCHEDULER_SUSPENDED      ( ( BaseType_t ) 0 )\n#define taskSCHEDULER_NOT_STARTED    ( ( BaseType_t ) 1 )\n#define taskSCHEDULER_RUNNING        ( ( BaseType_t ) 2 )\n\n\n/*-----------------------------------------------------------\n* TASK CREATION API\n*----------------------------------------------------------*/\n\n/**\n * task. h\n * @code{c}\n * BaseType_t xTaskCreate(\n *                            TaskFunction_t pxTaskCode,\n *                            const char *pcName,\n *                            configSTACK_DEPTH_TYPE usStackDepth,\n *                            void *pvParameters,\n *                            UBaseType_t uxPriority,\n *                            TaskHandle_t *pxCreatedTask\n *                        );\n * @endcode\n *\n * Create a new task and add it to the list of tasks that are ready to run.\n *\n * Internally, within the FreeRTOS implementation, tasks use two blocks of\n * memory.  The first block is used to hold the task's data structures.  The\n * second block is used by the task as its stack.  If a task is created using\n * xTaskCreate() then both blocks of memory are automatically dynamically\n * allocated inside the xTaskCreate() function.  (see\n * https://www.FreeRTOS.org/a00111.html).  If a task is created using\n * xTaskCreateStatic() then the application writer must provide the required\n * memory.  xTaskCreateStatic() therefore allows a task to be created without\n * using any dynamic memory allocation.\n *\n * See xTaskCreateStatic() for a version that does not use any dynamic memory\n * allocation.\n *\n * xTaskCreate() can only be used to create a task that has unrestricted\n * access to the entire microcontroller memory map.  Systems that include MPU\n * support can alternatively create an MPU constrained task using\n * xTaskCreateRestricted().\n *\n * @param pxTaskCode Pointer to the task entry function.  Tasks\n * must be implemented to never return (i.e. continuous loop).\n *\n * @param pcName A descriptive name for the task.  This is mainly used to\n * facilitate debugging.  Max length defined by configMAX_TASK_NAME_LEN - default\n * is 16.\n *\n * @param usStackDepth The size of the task stack specified as the number of\n * variables the stack can hold - not the number of bytes.  For example, if\n * the stack is 16 bits wide and usStackDepth is defined as 100, 200 bytes\n * will be allocated for stack storage.\n *\n * @param pvParameters Pointer that will be used as the parameter for the task\n * being created.\n *\n * @param uxPriority The priority at which the task should run.  Systems that\n * include MPU support can optionally create tasks in a privileged (system)\n * mode by setting bit portPRIVILEGE_BIT of the priority parameter.  For\n * example, to create a privileged task at priority 2 the uxPriority parameter\n * should be set to ( 2 | portPRIVILEGE_BIT ).\n *\n * @param pxCreatedTask Used to pass back a handle by which the created task\n * can be referenced.\n *\n * @return pdPASS if the task was successfully created and added to a ready\n * list, otherwise an error code defined in the file projdefs.h\n *\n * Example usage:\n * @code{c}\n * // Task to be created.\n * void vTaskCode( void * pvParameters )\n * {\n *   for( ;; )\n *   {\n *       // Task code goes here.\n *   }\n * }\n *\n * // Function that creates a task.\n * void vOtherFunction( void )\n * {\n * static uint8_t ucParameterToPass;\n * TaskHandle_t xHandle = NULL;\n *\n *   // Create the task, storing the handle.  Note that the passed parameter ucParameterToPass\n *   // must exist for the lifetime of the task, so in this case is declared static.  If it was just an\n *   // an automatic stack variable it might no longer exist, or at least have been corrupted, by the time\n *   // the new task attempts to access it.\n *   xTaskCreate( vTaskCode, \"NAME\", STACK_SIZE, &ucParameterToPass, tskIDLE_PRIORITY, &xHandle );\n *   configASSERT( xHandle );\n *\n *   // Use the handle to delete the task.\n *   if( xHandle != NULL )\n *   {\n *      vTaskDelete( xHandle );\n *   }\n * }\n * @endcode\n * \\defgroup xTaskCreate xTaskCreate\n * \\ingroup Tasks\n */\n#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n    BaseType_t xTaskCreate( TaskFunction_t pxTaskCode,\n                            const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n                            const configSTACK_DEPTH_TYPE usStackDepth,\n                            void * const pvParameters,\n                            UBaseType_t uxPriority,\n                            TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION;\n#endif\n\n/**\n * task. h\n * @code{c}\n * TaskHandle_t xTaskCreateStatic( TaskFunction_t pxTaskCode,\n *                               const char *pcName,\n *                               uint32_t ulStackDepth,\n *                               void *pvParameters,\n *                               UBaseType_t uxPriority,\n *                               StackType_t *puxStackBuffer,\n *                               StaticTask_t *pxTaskBuffer );\n * @endcode\n *\n * Create a new task and add it to the list of tasks that are ready to run.\n *\n * Internally, within the FreeRTOS implementation, tasks use two blocks of\n * memory.  The first block is used to hold the task's data structures.  The\n * second block is used by the task as its stack.  If a task is created using\n * xTaskCreate() then both blocks of memory are automatically dynamically\n * allocated inside the xTaskCreate() function.  (see\n * https://www.FreeRTOS.org/a00111.html).  If a task is created using\n * xTaskCreateStatic() then the application writer must provide the required\n * memory.  xTaskCreateStatic() therefore allows a task to be created without\n * using any dynamic memory allocation.\n *\n * @param pxTaskCode Pointer to the task entry function.  Tasks\n * must be implemented to never return (i.e. continuous loop).\n *\n * @param pcName A descriptive name for the task.  This is mainly used to\n * facilitate debugging.  The maximum length of the string is defined by\n * configMAX_TASK_NAME_LEN in FreeRTOSConfig.h.\n *\n * @param ulStackDepth The size of the task stack specified as the number of\n * variables the stack can hold - not the number of bytes.  For example, if\n * the stack is 32-bits wide and ulStackDepth is defined as 100 then 400 bytes\n * will be allocated for stack storage.\n *\n * @param pvParameters Pointer that will be used as the parameter for the task\n * being created.\n *\n * @param uxPriority The priority at which the task will run.\n *\n * @param puxStackBuffer Must point to a StackType_t array that has at least\n * ulStackDepth indexes - the array will then be used as the task's stack,\n * removing the need for the stack to be allocated dynamically.\n *\n * @param pxTaskBuffer Must point to a variable of type StaticTask_t, which will\n * then be used to hold the task's data structures, removing the need for the\n * memory to be allocated dynamically.\n *\n * @return If neither puxStackBuffer nor pxTaskBuffer are NULL, then the task\n * will be created and a handle to the created task is returned.  If either\n * puxStackBuffer or pxTaskBuffer are NULL then the task will not be created and\n * NULL is returned.\n *\n * Example usage:\n * @code{c}\n *\n *  // Dimensions of the buffer that the task being created will use as its stack.\n *  // NOTE:  This is the number of words the stack will hold, not the number of\n *  // bytes.  For example, if each stack item is 32-bits, and this is set to 100,\n *  // then 400 bytes (100 * 32-bits) will be allocated.\n #define STACK_SIZE 200\n *\n *  // Structure that will hold the TCB of the task being created.\n *  StaticTask_t xTaskBuffer;\n *\n *  // Buffer that the task being created will use as its stack.  Note this is\n *  // an array of StackType_t variables.  The size of StackType_t is dependent on\n *  // the RTOS port.\n *  StackType_t xStack[ STACK_SIZE ];\n *\n *  // Function that implements the task being created.\n *  void vTaskCode( void * pvParameters )\n *  {\n *      // The parameter value is expected to be 1 as 1 is passed in the\n *      // pvParameters value in the call to xTaskCreateStatic().\n *      configASSERT( ( uint32_t ) pvParameters == 1UL );\n *\n *      for( ;; )\n *      {\n *          // Task code goes here.\n *      }\n *  }\n *\n *  // Function that creates a task.\n *  void vOtherFunction( void )\n *  {\n *      TaskHandle_t xHandle = NULL;\n *\n *      // Create the task without using any dynamic memory allocation.\n *      xHandle = xTaskCreateStatic(\n *                    vTaskCode,       // Function that implements the task.\n *                    \"NAME\",          // Text name for the task.\n *                    STACK_SIZE,      // Stack size in words, not bytes.\n *                    ( void * ) 1,    // Parameter passed into the task.\n *                    tskIDLE_PRIORITY,// Priority at which the task is created.\n *                    xStack,          // Array to use as the task's stack.\n *                    &xTaskBuffer );  // Variable to hold the task's data structure.\n *\n *      // puxStackBuffer and pxTaskBuffer were not NULL, so the task will have\n *      // been created, and xHandle will be the task's handle.  Use the handle\n *      // to suspend the task.\n *      vTaskSuspend( xHandle );\n *  }\n * @endcode\n * \\defgroup xTaskCreateStatic xTaskCreateStatic\n * \\ingroup Tasks\n */\n#if ( configSUPPORT_STATIC_ALLOCATION == 1 )\n    TaskHandle_t xTaskCreateStatic( TaskFunction_t pxTaskCode,\n                                    const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n                                    const uint32_t ulStackDepth,\n                                    void * const pvParameters,\n                                    UBaseType_t uxPriority,\n                                    StackType_t * const puxStackBuffer,\n                                    StaticTask_t * const pxTaskBuffer ) PRIVILEGED_FUNCTION;\n#endif /* configSUPPORT_STATIC_ALLOCATION */\n\n/**\n * task. h\n * @code{c}\n * BaseType_t xTaskCreateRestricted( TaskParameters_t *pxTaskDefinition, TaskHandle_t *pxCreatedTask );\n * @endcode\n *\n * Only available when configSUPPORT_DYNAMIC_ALLOCATION is set to 1.\n *\n * xTaskCreateRestricted() should only be used in systems that include an MPU\n * implementation.\n *\n * Create a new task and add it to the list of tasks that are ready to run.\n * The function parameters define the memory regions and associated access\n * permissions allocated to the task.\n *\n * See xTaskCreateRestrictedStatic() for a version that does not use any\n * dynamic memory allocation.\n *\n * @param pxTaskDefinition Pointer to a structure that contains a member\n * for each of the normal xTaskCreate() parameters (see the xTaskCreate() API\n * documentation) plus an optional stack buffer and the memory region\n * definitions.\n *\n * @param pxCreatedTask Used to pass back a handle by which the created task\n * can be referenced.\n *\n * @return pdPASS if the task was successfully created and added to a ready\n * list, otherwise an error code defined in the file projdefs.h\n *\n * Example usage:\n * @code{c}\n * // Create an TaskParameters_t structure that defines the task to be created.\n * static const TaskParameters_t xCheckTaskParameters =\n * {\n *  vATask,     // pvTaskCode - the function that implements the task.\n *  \"ATask\",    // pcName - just a text name for the task to assist debugging.\n *  100,        // usStackDepth - the stack size DEFINED IN WORDS.\n *  NULL,       // pvParameters - passed into the task function as the function parameters.\n *  ( 1UL | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.\n *  cStackBuffer,// puxStackBuffer - the buffer to be used as the task stack.\n *\n *  // xRegions - Allocate up to three separate memory regions for access by\n *  // the task, with appropriate access permissions.  Different processors have\n *  // different memory alignment requirements - refer to the FreeRTOS documentation\n *  // for full information.\n *  {\n *      // Base address                 Length  Parameters\n *      { cReadWriteArray,              32,     portMPU_REGION_READ_WRITE },\n *      { cReadOnlyArray,               32,     portMPU_REGION_READ_ONLY },\n *      { cPrivilegedOnlyAccessArray,   128,    portMPU_REGION_PRIVILEGED_READ_WRITE }\n *  }\n * };\n *\n * int main( void )\n * {\n * TaskHandle_t xHandle;\n *\n *  // Create a task from the const structure defined above.  The task handle\n *  // is requested (the second parameter is not NULL) but in this case just for\n *  // demonstration purposes as its not actually used.\n *  xTaskCreateRestricted( &xRegTest1Parameters, &xHandle );\n *\n *  // Start the scheduler.\n *  vTaskStartScheduler();\n *\n *  // Will only get here if there was insufficient memory to create the idle\n *  // and/or timer task.\n *  for( ;; );\n * }\n * @endcode\n * \\defgroup xTaskCreateRestricted xTaskCreateRestricted\n * \\ingroup Tasks\n */\n#if ( portUSING_MPU_WRAPPERS == 1 )\n    BaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition,\n                                      TaskHandle_t * pxCreatedTask ) PRIVILEGED_FUNCTION;\n#endif\n\n/**\n * task. h\n * @code{c}\n * BaseType_t xTaskCreateRestrictedStatic( TaskParameters_t *pxTaskDefinition, TaskHandle_t *pxCreatedTask );\n * @endcode\n *\n * Only available when configSUPPORT_STATIC_ALLOCATION is set to 1.\n *\n * xTaskCreateRestrictedStatic() should only be used in systems that include an\n * MPU implementation.\n *\n * Internally, within the FreeRTOS implementation, tasks use two blocks of\n * memory.  The first block is used to hold the task's data structures.  The\n * second block is used by the task as its stack.  If a task is created using\n * xTaskCreateRestricted() then the stack is provided by the application writer,\n * and the memory used to hold the task's data structure is automatically\n * dynamically allocated inside the xTaskCreateRestricted() function.  If a task\n * is created using xTaskCreateRestrictedStatic() then the application writer\n * must provide the memory used to hold the task's data structures too.\n * xTaskCreateRestrictedStatic() therefore allows a memory protected task to be\n * created without using any dynamic memory allocation.\n *\n * @param pxTaskDefinition Pointer to a structure that contains a member\n * for each of the normal xTaskCreate() parameters (see the xTaskCreate() API\n * documentation) plus an optional stack buffer and the memory region\n * definitions.  If configSUPPORT_STATIC_ALLOCATION is set to 1 the structure\n * contains an additional member, which is used to point to a variable of type\n * StaticTask_t - which is then used to hold the task's data structure.\n *\n * @param pxCreatedTask Used to pass back a handle by which the created task\n * can be referenced.\n *\n * @return pdPASS if the task was successfully created and added to a ready\n * list, otherwise an error code defined in the file projdefs.h\n *\n * Example usage:\n * @code{c}\n * // Create an TaskParameters_t structure that defines the task to be created.\n * // The StaticTask_t variable is only included in the structure when\n * // configSUPPORT_STATIC_ALLOCATION is set to 1.  The PRIVILEGED_DATA macro can\n * // be used to force the variable into the RTOS kernel's privileged data area.\n * static PRIVILEGED_DATA StaticTask_t xTaskBuffer;\n * static const TaskParameters_t xCheckTaskParameters =\n * {\n *  vATask,     // pvTaskCode - the function that implements the task.\n *  \"ATask\",    // pcName - just a text name for the task to assist debugging.\n *  100,        // usStackDepth - the stack size DEFINED IN WORDS.\n *  NULL,       // pvParameters - passed into the task function as the function parameters.\n *  ( 1UL | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.\n *  cStackBuffer,// puxStackBuffer - the buffer to be used as the task stack.\n *\n *  // xRegions - Allocate up to three separate memory regions for access by\n *  // the task, with appropriate access permissions.  Different processors have\n *  // different memory alignment requirements - refer to the FreeRTOS documentation\n *  // for full information.\n *  {\n *      // Base address                 Length  Parameters\n *      { cReadWriteArray,              32,     portMPU_REGION_READ_WRITE },\n *      { cReadOnlyArray,               32,     portMPU_REGION_READ_ONLY },\n *      { cPrivilegedOnlyAccessArray,   128,    portMPU_REGION_PRIVILEGED_READ_WRITE }\n *  }\n *\n *  &xTaskBuffer; // Holds the task's data structure.\n * };\n *\n * int main( void )\n * {\n * TaskHandle_t xHandle;\n *\n *  // Create a task from the const structure defined above.  The task handle\n *  // is requested (the second parameter is not NULL) but in this case just for\n *  // demonstration purposes as its not actually used.\n *  xTaskCreateRestrictedStatic( &xRegTest1Parameters, &xHandle );\n *\n *  // Start the scheduler.\n *  vTaskStartScheduler();\n *\n *  // Will only get here if there was insufficient memory to create the idle\n *  // and/or timer task.\n *  for( ;; );\n * }\n * @endcode\n * \\defgroup xTaskCreateRestrictedStatic xTaskCreateRestrictedStatic\n * \\ingroup Tasks\n */\n#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )\n    BaseType_t xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition,\n                                            TaskHandle_t * pxCreatedTask ) PRIVILEGED_FUNCTION;\n#endif\n\n/**\n * task. h\n * @code{c}\n * void vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions );\n * @endcode\n *\n * Memory regions are assigned to a restricted task when the task is created by\n * a call to xTaskCreateRestricted().  These regions can be redefined using\n * vTaskAllocateMPURegions().\n *\n * @param xTask The handle of the task being updated.\n *\n * @param xRegions A pointer to a MemoryRegion_t structure that contains the\n * new memory region definitions.\n *\n * Example usage:\n * @code{c}\n * // Define an array of MemoryRegion_t structures that configures an MPU region\n * // allowing read/write access for 1024 bytes starting at the beginning of the\n * // ucOneKByte array.  The other two of the maximum 3 definable regions are\n * // unused so set to zero.\n * static const MemoryRegion_t xAltRegions[ portNUM_CONFIGURABLE_REGIONS ] =\n * {\n *  // Base address     Length      Parameters\n *  { ucOneKByte,       1024,       portMPU_REGION_READ_WRITE },\n *  { 0,                0,          0 },\n *  { 0,                0,          0 }\n * };\n *\n * void vATask( void *pvParameters )\n * {\n *  // This task was created such that it has access to certain regions of\n *  // memory as defined by the MPU configuration.  At some point it is\n *  // desired that these MPU regions are replaced with that defined in the\n *  // xAltRegions const struct above.  Use a call to vTaskAllocateMPURegions()\n *  // for this purpose.  NULL is used as the task handle to indicate that this\n *  // function should modify the MPU regions of the calling task.\n *  vTaskAllocateMPURegions( NULL, xAltRegions );\n *\n *  // Now the task can continue its function, but from this point on can only\n *  // access its stack and the ucOneKByte array (unless any other statically\n *  // defined or shared regions have been declared elsewhere).\n * }\n * @endcode\n * \\defgroup vTaskAllocateMPURegions vTaskAllocateMPURegions\n * \\ingroup Tasks\n */\nvoid vTaskAllocateMPURegions( TaskHandle_t xTask,\n                              const MemoryRegion_t * const pxRegions ) PRIVILEGED_FUNCTION;\n\n/**\n * task. h\n * @code{c}\n * void vTaskDelete( TaskHandle_t xTaskToDelete );\n * @endcode\n *\n * INCLUDE_vTaskDelete must be defined as 1 for this function to be available.\n * See the configuration section for more information.\n *\n * Remove a task from the RTOS real time kernel's management.  The task being\n * deleted will be removed from all ready, blocked, suspended and event lists.\n *\n * NOTE:  The idle task is responsible for freeing the kernel allocated\n * memory from tasks that have been deleted.  It is therefore important that\n * the idle task is not starved of microcontroller processing time if your\n * application makes any calls to vTaskDelete ().  Memory allocated by the\n * task code is not automatically freed, and should be freed before the task\n * is deleted.\n *\n * See the demo application file death.c for sample code that utilises\n * vTaskDelete ().\n *\n * @param xTaskToDelete The handle of the task to be deleted.  Passing NULL will\n * cause the calling task to be deleted.\n *\n * Example usage:\n * @code{c}\n * void vOtherFunction( void )\n * {\n * TaskHandle_t xHandle;\n *\n *   // Create the task, storing the handle.\n *   xTaskCreate( vTaskCode, \"NAME\", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );\n *\n *   // Use the handle to delete the task.\n *   vTaskDelete( xHandle );\n * }\n * @endcode\n * \\defgroup vTaskDelete vTaskDelete\n * \\ingroup Tasks\n */\nvoid vTaskDelete( TaskHandle_t xTaskToDelete ) PRIVILEGED_FUNCTION;\n\n/*-----------------------------------------------------------\n* TASK CONTROL API\n*----------------------------------------------------------*/\n\n/**\n * task. h\n * @code{c}\n * void vTaskDelay( const TickType_t xTicksToDelay );\n * @endcode\n *\n * Delay a task for a given number of ticks.  The actual time that the\n * task remains blocked depends on the tick rate.  The constant\n * portTICK_PERIOD_MS can be used to calculate real time from the tick\n * rate - with the resolution of one tick period.\n *\n * INCLUDE_vTaskDelay must be defined as 1 for this function to be available.\n * See the configuration section for more information.\n *\n *\n * vTaskDelay() specifies a time at which the task wishes to unblock relative to\n * the time at which vTaskDelay() is called.  For example, specifying a block\n * period of 100 ticks will cause the task to unblock 100 ticks after\n * vTaskDelay() is called.  vTaskDelay() does not therefore provide a good method\n * of controlling the frequency of a periodic task as the path taken through the\n * code, as well as other task and interrupt activity, will affect the frequency\n * at which vTaskDelay() gets called and therefore the time at which the task\n * next executes.  See xTaskDelayUntil() for an alternative API function designed\n * to facilitate fixed frequency execution.  It does this by specifying an\n * absolute time (rather than a relative time) at which the calling task should\n * unblock.\n *\n * @param xTicksToDelay The amount of time, in tick periods, that\n * the calling task should block.\n *\n * Example usage:\n *\n * void vTaskFunction( void * pvParameters )\n * {\n * // Block for 500ms.\n * const TickType_t xDelay = 500 / portTICK_PERIOD_MS;\n *\n *   for( ;; )\n *   {\n *       // Simply toggle the LED every 500ms, blocking between each toggle.\n *       vToggleLED();\n *       vTaskDelay( xDelay );\n *   }\n * }\n *\n * \\defgroup vTaskDelay vTaskDelay\n * \\ingroup TaskCtrl\n */\nvoid vTaskDelay( const TickType_t xTicksToDelay ) PRIVILEGED_FUNCTION;\n\n/**\n * task. h\n * @code{c}\n * BaseType_t xTaskDelayUntil( TickType_t *pxPreviousWakeTime, const TickType_t xTimeIncrement );\n * @endcode\n *\n * INCLUDE_xTaskDelayUntil must be defined as 1 for this function to be available.\n * See the configuration section for more information.\n *\n * Delay a task until a specified time.  This function can be used by periodic\n * tasks to ensure a constant execution frequency.\n *\n * This function differs from vTaskDelay () in one important aspect:  vTaskDelay () will\n * cause a task to block for the specified number of ticks from the time vTaskDelay () is\n * called.  It is therefore difficult to use vTaskDelay () by itself to generate a fixed\n * execution frequency as the time between a task starting to execute and that task\n * calling vTaskDelay () may not be fixed [the task may take a different path though the\n * code between calls, or may get interrupted or preempted a different number of times\n * each time it executes].\n *\n * Whereas vTaskDelay () specifies a wake time relative to the time at which the function\n * is called, xTaskDelayUntil () specifies the absolute (exact) time at which it wishes to\n * unblock.\n *\n * The macro pdMS_TO_TICKS() can be used to calculate the number of ticks from a\n * time specified in milliseconds with a resolution of one tick period.\n *\n * @param pxPreviousWakeTime Pointer to a variable that holds the time at which the\n * task was last unblocked.  The variable must be initialised with the current time\n * prior to its first use (see the example below).  Following this the variable is\n * automatically updated within xTaskDelayUntil ().\n *\n * @param xTimeIncrement The cycle time period.  The task will be unblocked at\n * time *pxPreviousWakeTime + xTimeIncrement.  Calling xTaskDelayUntil with the\n * same xTimeIncrement parameter value will cause the task to execute with\n * a fixed interface period.\n *\n * @return Value which can be used to check whether the task was actually delayed.\n * Will be pdTRUE if the task way delayed and pdFALSE otherwise.  A task will not\n * be delayed if the next expected wake time is in the past.\n *\n * Example usage:\n * @code{c}\n * // Perform an action every 10 ticks.\n * void vTaskFunction( void * pvParameters )\n * {\n * TickType_t xLastWakeTime;\n * const TickType_t xFrequency = 10;\n * BaseType_t xWasDelayed;\n *\n *     // Initialise the xLastWakeTime variable with the current time.\n *     xLastWakeTime = xTaskGetTickCount ();\n *     for( ;; )\n *     {\n *         // Wait for the next cycle.\n *         xWasDelayed = xTaskDelayUntil( &xLastWakeTime, xFrequency );\n *\n *         // Perform action here. xWasDelayed value can be used to determine\n *         // whether a deadline was missed if the code here took too long.\n *     }\n * }\n * @endcode\n * \\defgroup xTaskDelayUntil xTaskDelayUntil\n * \\ingroup TaskCtrl\n */\nBaseType_t xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,\n                            const TickType_t xTimeIncrement ) PRIVILEGED_FUNCTION;\n\n/*\n * vTaskDelayUntil() is the older version of xTaskDelayUntil() and does not\n * return a value.\n */\n#define vTaskDelayUntil( pxPreviousWakeTime, xTimeIncrement )                   \\\n    do {                                                                        \\\n        ( void ) xTaskDelayUntil( ( pxPreviousWakeTime ), ( xTimeIncrement ) ); \\\n    } while( 0 )\n\n\n/**\n * task. h\n * @code{c}\n * BaseType_t xTaskAbortDelay( TaskHandle_t xTask );\n * @endcode\n *\n * INCLUDE_xTaskAbortDelay must be defined as 1 in FreeRTOSConfig.h for this\n * function to be available.\n *\n * A task will enter the Blocked state when it is waiting for an event.  The\n * event it is waiting for can be a temporal event (waiting for a time), such\n * as when vTaskDelay() is called, or an event on an object, such as when\n * xQueueReceive() or ulTaskNotifyTake() is called.  If the handle of a task\n * that is in the Blocked state is used in a call to xTaskAbortDelay() then the\n * task will leave the Blocked state, and return from whichever function call\n * placed the task into the Blocked state.\n *\n * There is no 'FromISR' version of this function as an interrupt would need to\n * know which object a task was blocked on in order to know which actions to\n * take.  For example, if the task was blocked on a queue the interrupt handler\n * would then need to know if the queue was locked.\n *\n * @param xTask The handle of the task to remove from the Blocked state.\n *\n * @return If the task referenced by xTask was not in the Blocked state then\n * pdFAIL is returned.  Otherwise pdPASS is returned.\n *\n * \\defgroup xTaskAbortDelay xTaskAbortDelay\n * \\ingroup TaskCtrl\n */\nBaseType_t xTaskAbortDelay( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;\n\n/**\n * task. h\n * @code{c}\n * UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask );\n * @endcode\n *\n * INCLUDE_uxTaskPriorityGet must be defined as 1 for this function to be available.\n * See the configuration section for more information.\n *\n * Obtain the priority of any task.\n *\n * @param xTask Handle of the task to be queried.  Passing a NULL\n * handle results in the priority of the calling task being returned.\n *\n * @return The priority of xTask.\n *\n * Example usage:\n * @code{c}\n * void vAFunction( void )\n * {\n * TaskHandle_t xHandle;\n *\n *   // Create a task, storing the handle.\n *   xTaskCreate( vTaskCode, \"NAME\", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );\n *\n *   // ...\n *\n *   // Use the handle to obtain the priority of the created task.\n *   // It was created with tskIDLE_PRIORITY, but may have changed\n *   // it itself.\n *   if( uxTaskPriorityGet( xHandle ) != tskIDLE_PRIORITY )\n *   {\n *       // The task has changed it's priority.\n *   }\n *\n *   // ...\n *\n *   // Is our priority higher than the created task?\n *   if( uxTaskPriorityGet( xHandle ) < uxTaskPriorityGet( NULL ) )\n *   {\n *       // Our priority (obtained using NULL handle) is higher.\n *   }\n * }\n * @endcode\n * \\defgroup uxTaskPriorityGet uxTaskPriorityGet\n * \\ingroup TaskCtrl\n */\nUBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;\n\n/**\n * task. h\n * @code{c}\n * UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask );\n * @endcode\n *\n * A version of uxTaskPriorityGet() that can be used from an ISR.\n */\nUBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;\n\n/**\n * task. h\n * @code{c}\n * eTaskState eTaskGetState( TaskHandle_t xTask );\n * @endcode\n *\n * INCLUDE_eTaskGetState must be defined as 1 for this function to be available.\n * See the configuration section for more information.\n *\n * Obtain the state of any task.  States are encoded by the eTaskState\n * enumerated type.\n *\n * @param xTask Handle of the task to be queried.\n *\n * @return The state of xTask at the time the function was called.  Note the\n * state of the task might change between the function being called, and the\n * functions return value being tested by the calling task.\n */\neTaskState eTaskGetState( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;\n\n/**\n * task. h\n * @code{c}\n * void vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState );\n * @endcode\n *\n * configUSE_TRACE_FACILITY must be defined as 1 for this function to be\n * available.  See the configuration section for more information.\n *\n * Populates a TaskStatus_t structure with information about a task.\n *\n * @param xTask Handle of the task being queried.  If xTask is NULL then\n * information will be returned about the calling task.\n *\n * @param pxTaskStatus A pointer to the TaskStatus_t structure that will be\n * filled with information about the task referenced by the handle passed using\n * the xTask parameter.\n *\n * @param xGetFreeStackSpace The TaskStatus_t structure contains a member to report\n * the stack high water mark of the task being queried.  Calculating the stack\n * high water mark takes a relatively long time, and can make the system\n * temporarily unresponsive - so the xGetFreeStackSpace parameter is provided to\n * allow the high water mark checking to be skipped.  The high watermark value\n * will only be written to the TaskStatus_t structure if xGetFreeStackSpace is\n * not set to pdFALSE;\n *\n * @param eState The TaskStatus_t structure contains a member to report the\n * state of the task being queried.  Obtaining the task state is not as fast as\n * a simple assignment - so the eState parameter is provided to allow the state\n * information to be omitted from the TaskStatus_t structure.  To obtain state\n * information then set eState to eInvalid - otherwise the value passed in\n * eState will be reported as the task state in the TaskStatus_t structure.\n *\n * Example usage:\n * @code{c}\n * void vAFunction( void )\n * {\n * TaskHandle_t xHandle;\n * TaskStatus_t xTaskDetails;\n *\n *  // Obtain the handle of a task from its name.\n *  xHandle = xTaskGetHandle( \"Task_Name\" );\n *\n *  // Check the handle is not NULL.\n *  configASSERT( xHandle );\n *\n *  // Use the handle to obtain further information about the task.\n *  vTaskGetInfo( xHandle,\n *                &xTaskDetails,\n *                pdTRUE, // Include the high water mark in xTaskDetails.\n *                eInvalid ); // Include the task state in xTaskDetails.\n * }\n * @endcode\n * \\defgroup vTaskGetInfo vTaskGetInfo\n * \\ingroup TaskCtrl\n */\nvoid vTaskGetInfo( TaskHandle_t xTask,\n                   TaskStatus_t * pxTaskStatus,\n                   BaseType_t xGetFreeStackSpace,\n                   eTaskState eState ) PRIVILEGED_FUNCTION;\n\n/**\n * task. h\n * @code{c}\n * void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority );\n * @endcode\n *\n * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be available.\n * See the configuration section for more information.\n *\n * Set the priority of any task.\n *\n * A context switch will occur before the function returns if the priority\n * being set is higher than the currently executing task.\n *\n * @param xTask Handle to the task for which the priority is being set.\n * Passing a NULL handle results in the priority of the calling task being set.\n *\n * @param uxNewPriority The priority to which the task will be set.\n *\n * Example usage:\n * @code{c}\n * void vAFunction( void )\n * {\n * TaskHandle_t xHandle;\n *\n *   // Create a task, storing the handle.\n *   xTaskCreate( vTaskCode, \"NAME\", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );\n *\n *   // ...\n *\n *   // Use the handle to raise the priority of the created task.\n *   vTaskPrioritySet( xHandle, tskIDLE_PRIORITY + 1 );\n *\n *   // ...\n *\n *   // Use a NULL handle to raise our priority to the same value.\n *   vTaskPrioritySet( NULL, tskIDLE_PRIORITY + 1 );\n * }\n * @endcode\n * \\defgroup vTaskPrioritySet vTaskPrioritySet\n * \\ingroup TaskCtrl\n */\nvoid vTaskPrioritySet( TaskHandle_t xTask,\n                       UBaseType_t uxNewPriority ) PRIVILEGED_FUNCTION;\n\n/**\n * task. h\n * @code{c}\n * void vTaskSuspend( TaskHandle_t xTaskToSuspend );\n * @endcode\n *\n * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available.\n * See the configuration section for more information.\n *\n * Suspend any task.  When suspended a task will never get any microcontroller\n * processing time, no matter what its priority.\n *\n * Calls to vTaskSuspend are not accumulative -\n * i.e. calling vTaskSuspend () twice on the same task still only requires one\n * call to vTaskResume () to ready the suspended task.\n *\n * @param xTaskToSuspend Handle to the task being suspended.  Passing a NULL\n * handle will cause the calling task to be suspended.\n *\n * Example usage:\n * @code{c}\n * void vAFunction( void )\n * {\n * TaskHandle_t xHandle;\n *\n *   // Create a task, storing the handle.\n *   xTaskCreate( vTaskCode, \"NAME\", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );\n *\n *   // ...\n *\n *   // Use the handle to suspend the created task.\n *   vTaskSuspend( xHandle );\n *\n *   // ...\n *\n *   // The created task will not run during this period, unless\n *   // another task calls vTaskResume( xHandle ).\n *\n *   //...\n *\n *\n *   // Suspend ourselves.\n *   vTaskSuspend( NULL );\n *\n *   // We cannot get here unless another task calls vTaskResume\n *   // with our handle as the parameter.\n * }\n * @endcode\n * \\defgroup vTaskSuspend vTaskSuspend\n * \\ingroup TaskCtrl\n */\nvoid vTaskSuspend( TaskHandle_t xTaskToSuspend ) PRIVILEGED_FUNCTION;\n\n/**\n * task. h\n * @code{c}\n * void vTaskResume( TaskHandle_t xTaskToResume );\n * @endcode\n *\n * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available.\n * See the configuration section for more information.\n *\n * Resumes a suspended task.\n *\n * A task that has been suspended by one or more calls to vTaskSuspend ()\n * will be made available for running again by a single call to\n * vTaskResume ().\n *\n * @param xTaskToResume Handle to the task being readied.\n *\n * Example usage:\n * @code{c}\n * void vAFunction( void )\n * {\n * TaskHandle_t xHandle;\n *\n *   // Create a task, storing the handle.\n *   xTaskCreate( vTaskCode, \"NAME\", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );\n *\n *   // ...\n *\n *   // Use the handle to suspend the created task.\n *   vTaskSuspend( xHandle );\n *\n *   // ...\n *\n *   // The created task will not run during this period, unless\n *   // another task calls vTaskResume( xHandle ).\n *\n *   //...\n *\n *\n *   // Resume the suspended task ourselves.\n *   vTaskResume( xHandle );\n *\n *   // The created task will once again get microcontroller processing\n *   // time in accordance with its priority within the system.\n * }\n * @endcode\n * \\defgroup vTaskResume vTaskResume\n * \\ingroup TaskCtrl\n */\nvoid vTaskResume( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION;\n\n/**\n * task. h\n * @code{c}\n * void xTaskResumeFromISR( TaskHandle_t xTaskToResume );\n * @endcode\n *\n * INCLUDE_xTaskResumeFromISR must be defined as 1 for this function to be\n * available.  See the configuration section for more information.\n *\n * An implementation of vTaskResume() that can be called from within an ISR.\n *\n * A task that has been suspended by one or more calls to vTaskSuspend ()\n * will be made available for running again by a single call to\n * xTaskResumeFromISR ().\n *\n * xTaskResumeFromISR() should not be used to synchronise a task with an\n * interrupt if there is a chance that the interrupt could arrive prior to the\n * task being suspended - as this can lead to interrupts being missed. Use of a\n * semaphore as a synchronisation mechanism would avoid this eventuality.\n *\n * @param xTaskToResume Handle to the task being readied.\n *\n * @return pdTRUE if resuming the task should result in a context switch,\n * otherwise pdFALSE. This is used by the ISR to determine if a context switch\n * may be required following the ISR.\n *\n * \\defgroup vTaskResumeFromISR vTaskResumeFromISR\n * \\ingroup TaskCtrl\n */\nBaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION;\n\n/*-----------------------------------------------------------\n* SCHEDULER CONTROL\n*----------------------------------------------------------*/\n\n/**\n * task. h\n * @code{c}\n * void vTaskStartScheduler( void );\n * @endcode\n *\n * Starts the real time kernel tick processing.  After calling the kernel\n * has control over which tasks are executed and when.\n *\n * See the demo application file main.c for an example of creating\n * tasks and starting the kernel.\n *\n * Example usage:\n * @code{c}\n * void vAFunction( void )\n * {\n *   // Create at least one task before starting the kernel.\n *   xTaskCreate( vTaskCode, \"NAME\", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );\n *\n *   // Start the real time kernel with preemption.\n *   vTaskStartScheduler ();\n *\n *   // Will not get here unless a task calls vTaskEndScheduler ()\n * }\n * @endcode\n *\n * \\defgroup vTaskStartScheduler vTaskStartScheduler\n * \\ingroup SchedulerControl\n */\nvoid vTaskStartScheduler( void ) PRIVILEGED_FUNCTION;\n\n/**\n * task. h\n * @code{c}\n * void vTaskEndScheduler( void );\n * @endcode\n *\n * NOTE:  At the time of writing only the x86 real mode port, which runs on a PC\n * in place of DOS, implements this function.\n *\n * Stops the real time kernel tick.  All created tasks will be automatically\n * deleted and multitasking (either preemptive or cooperative) will\n * stop.  Execution then resumes from the point where vTaskStartScheduler ()\n * was called, as if vTaskStartScheduler () had just returned.\n *\n * See the demo application file main. c in the demo/PC directory for an\n * example that uses vTaskEndScheduler ().\n *\n * vTaskEndScheduler () requires an exit function to be defined within the\n * portable layer (see vPortEndScheduler () in port. c for the PC port).  This\n * performs hardware specific operations such as stopping the kernel tick.\n *\n * vTaskEndScheduler () will cause all of the resources allocated by the\n * kernel to be freed - but will not free resources allocated by application\n * tasks.\n *\n * Example usage:\n * @code{c}\n * void vTaskCode( void * pvParameters )\n * {\n *   for( ;; )\n *   {\n *       // Task code goes here.\n *\n *       // At some point we want to end the real time kernel processing\n *       // so call ...\n *       vTaskEndScheduler ();\n *   }\n * }\n *\n * void vAFunction( void )\n * {\n *   // Create at least one task before starting the kernel.\n *   xTaskCreate( vTaskCode, \"NAME\", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );\n *\n *   // Start the real time kernel with preemption.\n *   vTaskStartScheduler ();\n *\n *   // Will only get here when the vTaskCode () task has called\n *   // vTaskEndScheduler ().  When we get here we are back to single task\n *   // execution.\n * }\n * @endcode\n *\n * \\defgroup vTaskEndScheduler vTaskEndScheduler\n * \\ingroup SchedulerControl\n */\nvoid vTaskEndScheduler( void ) PRIVILEGED_FUNCTION;\n\n/**\n * task. h\n * @code{c}\n * void vTaskSuspendAll( void );\n * @endcode\n *\n * Suspends the scheduler without disabling interrupts.  Context switches will\n * not occur while the scheduler is suspended.\n *\n * After calling vTaskSuspendAll () the calling task will continue to execute\n * without risk of being swapped out until a call to xTaskResumeAll () has been\n * made.\n *\n * API functions that have the potential to cause a context switch (for example,\n * xTaskDelayUntil(), xQueueSend(), etc.) must not be called while the scheduler\n * is suspended.\n *\n * Example usage:\n * @code{c}\n * void vTask1( void * pvParameters )\n * {\n *   for( ;; )\n *   {\n *       // Task code goes here.\n *\n *       // ...\n *\n *       // At some point the task wants to perform a long operation during\n *       // which it does not want to get swapped out.  It cannot use\n *       // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the\n *       // operation may cause interrupts to be missed - including the\n *       // ticks.\n *\n *       // Prevent the real time kernel swapping out the task.\n *       vTaskSuspendAll ();\n *\n *       // Perform the operation here.  There is no need to use critical\n *       // sections as we have all the microcontroller processing time.\n *       // During this time interrupts will still operate and the kernel\n *       // tick count will be maintained.\n *\n *       // ...\n *\n *       // The operation is complete.  Restart the kernel.\n *       xTaskResumeAll ();\n *   }\n * }\n * @endcode\n * \\defgroup vTaskSuspendAll vTaskSuspendAll\n * \\ingroup SchedulerControl\n */\nvoid vTaskSuspendAll( void ) PRIVILEGED_FUNCTION;\n\n/**\n * task. h\n * @code{c}\n * BaseType_t xTaskResumeAll( void );\n * @endcode\n *\n * Resumes scheduler activity after it was suspended by a call to\n * vTaskSuspendAll().\n *\n * xTaskResumeAll() only resumes the scheduler.  It does not unsuspend tasks\n * that were previously suspended by a call to vTaskSuspend().\n *\n * @return If resuming the scheduler caused a context switch then pdTRUE is\n *         returned, otherwise pdFALSE is returned.\n *\n * Example usage:\n * @code{c}\n * void vTask1( void * pvParameters )\n * {\n *   for( ;; )\n *   {\n *       // Task code goes here.\n *\n *       // ...\n *\n *       // At some point the task wants to perform a long operation during\n *       // which it does not want to get swapped out.  It cannot use\n *       // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the\n *       // operation may cause interrupts to be missed - including the\n *       // ticks.\n *\n *       // Prevent the real time kernel swapping out the task.\n *       vTaskSuspendAll ();\n *\n *       // Perform the operation here.  There is no need to use critical\n *       // sections as we have all the microcontroller processing time.\n *       // During this time interrupts will still operate and the real\n *       // time kernel tick count will be maintained.\n *\n *       // ...\n *\n *       // The operation is complete.  Restart the kernel.  We want to force\n *       // a context switch - but there is no point if resuming the scheduler\n *       // caused a context switch already.\n *       if( !xTaskResumeAll () )\n *       {\n *            taskYIELD ();\n *       }\n *   }\n * }\n * @endcode\n * \\defgroup xTaskResumeAll xTaskResumeAll\n * \\ingroup SchedulerControl\n */\nBaseType_t xTaskResumeAll( void ) PRIVILEGED_FUNCTION;\n\n/*-----------------------------------------------------------\n* TASK UTILITIES\n*----------------------------------------------------------*/\n\n/**\n * task. h\n * @code{c}\n * TickType_t xTaskGetTickCount( void );\n * @endcode\n *\n * @return The count of ticks since vTaskStartScheduler was called.\n *\n * \\defgroup xTaskGetTickCount xTaskGetTickCount\n * \\ingroup TaskUtils\n */\nTickType_t xTaskGetTickCount( void ) PRIVILEGED_FUNCTION;\n\n/**\n * task. h\n * @code{c}\n * TickType_t xTaskGetTickCountFromISR( void );\n * @endcode\n *\n * @return The count of ticks since vTaskStartScheduler was called.\n *\n * This is a version of xTaskGetTickCount() that is safe to be called from an\n * ISR - provided that TickType_t is the natural word size of the\n * microcontroller being used or interrupt nesting is either not supported or\n * not being used.\n *\n * \\defgroup xTaskGetTickCountFromISR xTaskGetTickCountFromISR\n * \\ingroup TaskUtils\n */\nTickType_t xTaskGetTickCountFromISR( void ) PRIVILEGED_FUNCTION;\n\n/**\n * task. h\n * @code{c}\n * uint16_t uxTaskGetNumberOfTasks( void );\n * @endcode\n *\n * @return The number of tasks that the real time kernel is currently managing.\n * This includes all ready, blocked and suspended tasks.  A task that\n * has been deleted but not yet freed by the idle task will also be\n * included in the count.\n *\n * \\defgroup uxTaskGetNumberOfTasks uxTaskGetNumberOfTasks\n * \\ingroup TaskUtils\n */\nUBaseType_t uxTaskGetNumberOfTasks( void ) PRIVILEGED_FUNCTION;\n\n/**\n * task. h\n * @code{c}\n * char *pcTaskGetName( TaskHandle_t xTaskToQuery );\n * @endcode\n *\n * @return The text (human readable) name of the task referenced by the handle\n * xTaskToQuery.  A task can query its own name by either passing in its own\n * handle, or by setting xTaskToQuery to NULL.\n *\n * \\defgroup pcTaskGetName pcTaskGetName\n * \\ingroup TaskUtils\n */\nchar * pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n\n/**\n * task. h\n * @code{c}\n * TaskHandle_t xTaskGetHandle( const char *pcNameToQuery );\n * @endcode\n *\n * NOTE:  This function takes a relatively long time to complete and should be\n * used sparingly.\n *\n * @return The handle of the task that has the human readable name pcNameToQuery.\n * NULL is returned if no matching name is found.  INCLUDE_xTaskGetHandle\n * must be set to 1 in FreeRTOSConfig.h for pcTaskGetHandle() to be available.\n *\n * \\defgroup pcTaskGetHandle pcTaskGetHandle\n * \\ingroup TaskUtils\n */\nTaskHandle_t xTaskGetHandle( const char * pcNameToQuery ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n\n/**\n * task.h\n * @code{c}\n * UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask );\n * @endcode\n *\n * INCLUDE_uxTaskGetStackHighWaterMark must be set to 1 in FreeRTOSConfig.h for\n * this function to be available.\n *\n * Returns the high water mark of the stack associated with xTask.  That is,\n * the minimum free stack space there has been (in words, so on a 32 bit machine\n * a value of 1 means 4 bytes) since the task started.  The smaller the returned\n * number the closer the task has come to overflowing its stack.\n *\n * uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the\n * same except for their return type.  Using configSTACK_DEPTH_TYPE allows the\n * user to determine the return type.  It gets around the problem of the value\n * overflowing on 8-bit types without breaking backward compatibility for\n * applications that expect an 8-bit return type.\n *\n * @param xTask Handle of the task associated with the stack to be checked.\n * Set xTask to NULL to check the stack of the calling task.\n *\n * @return The smallest amount of free stack space there has been (in words, so\n * actual spaces on the stack rather than bytes) since the task referenced by\n * xTask was created.\n */\nUBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;\n\n/**\n * task.h\n * @code{c}\n * configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask );\n * @endcode\n *\n * INCLUDE_uxTaskGetStackHighWaterMark2 must be set to 1 in FreeRTOSConfig.h for\n * this function to be available.\n *\n * Returns the high water mark of the stack associated with xTask.  That is,\n * the minimum free stack space there has been (in words, so on a 32 bit machine\n * a value of 1 means 4 bytes) since the task started.  The smaller the returned\n * number the closer the task has come to overflowing its stack.\n *\n * uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the\n * same except for their return type.  Using configSTACK_DEPTH_TYPE allows the\n * user to determine the return type.  It gets around the problem of the value\n * overflowing on 8-bit types without breaking backward compatibility for\n * applications that expect an 8-bit return type.\n *\n * @param xTask Handle of the task associated with the stack to be checked.\n * Set xTask to NULL to check the stack of the calling task.\n *\n * @return The smallest amount of free stack space there has been (in words, so\n * actual spaces on the stack rather than bytes) since the task referenced by\n * xTask was created.\n */\nconfigSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;\n\n/* When using trace macros it is sometimes necessary to include task.h before\n * FreeRTOS.h.  When this is done TaskHookFunction_t will not yet have been defined,\n * so the following two prototypes will cause a compilation error.  This can be\n * fixed by simply guarding against the inclusion of these two prototypes unless\n * they are explicitly required by the configUSE_APPLICATION_TASK_TAG configuration\n * constant. */\n#ifdef configUSE_APPLICATION_TASK_TAG\n    #if configUSE_APPLICATION_TASK_TAG == 1\n\n/**\n * task.h\n * @code{c}\n * void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction );\n * @endcode\n *\n * Sets pxHookFunction to be the task hook function used by the task xTask.\n * Passing xTask as NULL has the effect of setting the calling tasks hook\n * function.\n */\n        void vTaskSetApplicationTaskTag( TaskHandle_t xTask,\n                                         TaskHookFunction_t pxHookFunction ) PRIVILEGED_FUNCTION;\n\n/**\n * task.h\n * @code{c}\n * void xTaskGetApplicationTaskTag( TaskHandle_t xTask );\n * @endcode\n *\n * Returns the pxHookFunction value assigned to the task xTask.  Do not\n * call from an interrupt service routine - call\n * xTaskGetApplicationTaskTagFromISR() instead.\n */\n        TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;\n\n/**\n * task.h\n * @code{c}\n * void xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask );\n * @endcode\n *\n * Returns the pxHookFunction value assigned to the task xTask.  Can\n * be called from an interrupt service routine.\n */\n        TaskHookFunction_t xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;\n    #endif /* configUSE_APPLICATION_TASK_TAG ==1 */\n#endif /* ifdef configUSE_APPLICATION_TASK_TAG */\n\n#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )\n\n/* Each task contains an array of pointers that is dimensioned by the\n * configNUM_THREAD_LOCAL_STORAGE_POINTERS setting in FreeRTOSConfig.h.  The\n * kernel does not use the pointers itself, so the application writer can use\n * the pointers for any purpose they wish.  The following two functions are\n * used to set and query a pointer respectively. */\n    void vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,\n                                            BaseType_t xIndex,\n                                            void * pvValue ) PRIVILEGED_FUNCTION;\n    void * pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,\n                                               BaseType_t xIndex ) PRIVILEGED_FUNCTION;\n\n#endif\n\n#if ( configCHECK_FOR_STACK_OVERFLOW > 0 )\n\n/**\n * task.h\n * @code{c}\n * void vApplicationStackOverflowHook( TaskHandle_t xTask char *pcTaskName);\n * @endcode\n *\n * The application stack overflow hook is called when a stack overflow is detected for a task.\n *\n * Details on stack overflow detection can be found here: https://www.FreeRTOS.org/Stacks-and-stack-overflow-checking.html\n *\n * @param xTask the task that just exceeded its stack boundaries.\n * @param pcTaskName A character string containing the name of the offending task.\n */\n    void vApplicationStackOverflowHook( TaskHandle_t xTask,\n                                        char * pcTaskName );\n\n#endif\n\n#if  ( configUSE_TICK_HOOK > 0 )\n\n/**\n *  task.h\n * @code{c}\n * void vApplicationTickHook( void );\n * @endcode\n *\n * This hook function is called in the system tick handler after any OS work is completed.\n */\n    void vApplicationTickHook( void ); /*lint !e526 Symbol not defined as it is an application callback. */\n\n#endif\n\n#if ( configSUPPORT_STATIC_ALLOCATION == 1 )\n\n/**\n * task.h\n * @code{c}\n * void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, StackType_t ** ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize )\n * @endcode\n *\n * This function is used to provide a statically allocated block of memory to FreeRTOS to hold the Idle Task TCB.  This function is required when\n * configSUPPORT_STATIC_ALLOCATION is set.  For more information see this URI: https://www.FreeRTOS.org/a00110.html#configSUPPORT_STATIC_ALLOCATION\n *\n * @param ppxIdleTaskTCBBuffer A handle to a statically allocated TCB buffer\n * @param ppxIdleTaskStackBuffer A handle to a statically allocated Stack buffer for the idle task\n * @param pulIdleTaskStackSize A pointer to the number of elements that will fit in the allocated stack buffer\n */\n    void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer,\n                                        StackType_t ** ppxIdleTaskStackBuffer,\n                                        uint32_t * pulIdleTaskStackSize ); /*lint !e526 Symbol not defined as it is an application callback. */\n#endif\n\n/**\n * task.h\n * @code{c}\n * BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter );\n * @endcode\n *\n * Calls the hook function associated with xTask.  Passing xTask as NULL has\n * the effect of calling the Running tasks (the calling task) hook function.\n *\n * pvParameter is passed to the hook function for the task to interpret as it\n * wants.  The return value is the value returned by the task hook function\n * registered by the user.\n */\nBaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask,\n                                         void * pvParameter ) PRIVILEGED_FUNCTION;\n\n/**\n * xTaskGetIdleTaskHandle() is only available if\n * INCLUDE_xTaskGetIdleTaskHandle is set to 1 in FreeRTOSConfig.h.\n *\n * Simply returns the handle of the idle task.  It is not valid to call\n * xTaskGetIdleTaskHandle() before the scheduler has been started.\n */\nTaskHandle_t xTaskGetIdleTaskHandle( void ) PRIVILEGED_FUNCTION;\n\n/**\n * configUSE_TRACE_FACILITY must be defined as 1 in FreeRTOSConfig.h for\n * uxTaskGetSystemState() to be available.\n *\n * uxTaskGetSystemState() populates an TaskStatus_t structure for each task in\n * the system.  TaskStatus_t structures contain, among other things, members\n * for the task handle, task name, task priority, task state, and total amount\n * of run time consumed by the task.  See the TaskStatus_t structure\n * definition in this file for the full member list.\n *\n * NOTE:  This function is intended for debugging use only as its use results in\n * the scheduler remaining suspended for an extended period.\n *\n * @param pxTaskStatusArray A pointer to an array of TaskStatus_t structures.\n * The array must contain at least one TaskStatus_t structure for each task\n * that is under the control of the RTOS.  The number of tasks under the control\n * of the RTOS can be determined using the uxTaskGetNumberOfTasks() API function.\n *\n * @param uxArraySize The size of the array pointed to by the pxTaskStatusArray\n * parameter.  The size is specified as the number of indexes in the array, or\n * the number of TaskStatus_t structures contained in the array, not by the\n * number of bytes in the array.\n *\n * @param pulTotalRunTime If configGENERATE_RUN_TIME_STATS is set to 1 in\n * FreeRTOSConfig.h then *pulTotalRunTime is set by uxTaskGetSystemState() to the\n * total run time (as defined by the run time stats clock, see\n * https://www.FreeRTOS.org/rtos-run-time-stats.html) since the target booted.\n * pulTotalRunTime can be set to NULL to omit the total run time information.\n *\n * @return The number of TaskStatus_t structures that were populated by\n * uxTaskGetSystemState().  This should equal the number returned by the\n * uxTaskGetNumberOfTasks() API function, but will be zero if the value passed\n * in the uxArraySize parameter was too small.\n *\n * Example usage:\n * @code{c}\n *  // This example demonstrates how a human readable table of run time stats\n *  // information is generated from raw data provided by uxTaskGetSystemState().\n *  // The human readable table is written to pcWriteBuffer\n *  void vTaskGetRunTimeStats( char *pcWriteBuffer )\n *  {\n *  TaskStatus_t *pxTaskStatusArray;\n *  volatile UBaseType_t uxArraySize, x;\n *  configRUN_TIME_COUNTER_TYPE ulTotalRunTime, ulStatsAsPercentage;\n *\n *      // Make sure the write buffer does not contain a string.\n * pcWriteBuffer = 0x00;\n *\n *      // Take a snapshot of the number of tasks in case it changes while this\n *      // function is executing.\n *      uxArraySize = uxTaskGetNumberOfTasks();\n *\n *      // Allocate a TaskStatus_t structure for each task.  An array could be\n *      // allocated statically at compile time.\n *      pxTaskStatusArray = pvPortMalloc( uxArraySize * sizeof( TaskStatus_t ) );\n *\n *      if( pxTaskStatusArray != NULL )\n *      {\n *          // Generate raw status information about each task.\n *          uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalRunTime );\n *\n *          // For percentage calculations.\n *          ulTotalRunTime /= 100UL;\n *\n *          // Avoid divide by zero errors.\n *          if( ulTotalRunTime > 0 )\n *          {\n *              // For each populated position in the pxTaskStatusArray array,\n *              // format the raw data as human readable ASCII data\n *              for( x = 0; x < uxArraySize; x++ )\n *              {\n *                  // What percentage of the total run time has the task used?\n *                  // This will always be rounded down to the nearest integer.\n *                  // ulTotalRunTimeDiv100 has already been divided by 100.\n *                  ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalRunTime;\n *\n *                  if( ulStatsAsPercentage > 0UL )\n *                  {\n *                      sprintf( pcWriteBuffer, \"%s\\t\\t%lu\\t\\t%lu%%\\r\\n\", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage );\n *                  }\n *                  else\n *                  {\n *                      // If the percentage is zero here then the task has\n *                      // consumed less than 1% of the total run time.\n *                      sprintf( pcWriteBuffer, \"%s\\t\\t%lu\\t\\t<1%%\\r\\n\", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter );\n *                  }\n *\n *                  pcWriteBuffer += strlen( ( char * ) pcWriteBuffer );\n *              }\n *          }\n *\n *          // The array is no longer needed, free the memory it consumes.\n *          vPortFree( pxTaskStatusArray );\n *      }\n *  }\n *  @endcode\n */\nUBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,\n                                  const UBaseType_t uxArraySize,\n                                  configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) PRIVILEGED_FUNCTION;\n\n/**\n * task. h\n * @code{c}\n * void vTaskList( char *pcWriteBuffer );\n * @endcode\n *\n * configUSE_TRACE_FACILITY and configUSE_STATS_FORMATTING_FUNCTIONS must\n * both be defined as 1 for this function to be available.  See the\n * configuration section of the FreeRTOS.org website for more information.\n *\n * NOTE 1: This function will disable interrupts for its duration.  It is\n * not intended for normal application runtime use but as a debug aid.\n *\n * Lists all the current tasks, along with their current state and stack\n * usage high water mark.\n *\n * Tasks are reported as blocked ('B'), ready ('R'), deleted ('D') or\n * suspended ('S').\n *\n * PLEASE NOTE:\n *\n * This function is provided for convenience only, and is used by many of the\n * demo applications.  Do not consider it to be part of the scheduler.\n *\n * vTaskList() calls uxTaskGetSystemState(), then formats part of the\n * uxTaskGetSystemState() output into a human readable table that displays task:\n * names, states, priority, stack usage and task number.\n * Stack usage specified as the number of unused StackType_t words stack can hold\n * on top of stack - not the number of bytes.\n *\n * vTaskList() has a dependency on the sprintf() C library function that might\n * bloat the code size, use a lot of stack, and provide different results on\n * different platforms.  An alternative, tiny, third party, and limited\n * functionality implementation of sprintf() is provided in many of the\n * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note\n * printf-stdarg.c does not provide a full snprintf() implementation!).\n *\n * It is recommended that production systems call uxTaskGetSystemState()\n * directly to get access to raw stats data, rather than indirectly through a\n * call to vTaskList().\n *\n * @param pcWriteBuffer A buffer into which the above mentioned details\n * will be written, in ASCII form.  This buffer is assumed to be large\n * enough to contain the generated report.  Approximately 40 bytes per\n * task should be sufficient.\n *\n * \\defgroup vTaskList vTaskList\n * \\ingroup TaskUtils\n */\nvoid vTaskList( char * pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n\n/**\n * task. h\n * @code{c}\n * void vTaskGetRunTimeStats( char *pcWriteBuffer );\n * @endcode\n *\n * configGENERATE_RUN_TIME_STATS and configUSE_STATS_FORMATTING_FUNCTIONS\n * must both be defined as 1 for this function to be available.  The application\n * must also then provide definitions for\n * portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE()\n * to configure a peripheral timer/counter and return the timers current count\n * value respectively.  The counter should be at least 10 times the frequency of\n * the tick count.\n *\n * NOTE 1: This function will disable interrupts for its duration.  It is\n * not intended for normal application runtime use but as a debug aid.\n *\n * Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total\n * accumulated execution time being stored for each task.  The resolution\n * of the accumulated time value depends on the frequency of the timer\n * configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro.\n * Calling vTaskGetRunTimeStats() writes the total execution time of each\n * task into a buffer, both as an absolute count value and as a percentage\n * of the total system execution time.\n *\n * NOTE 2:\n *\n * This function is provided for convenience only, and is used by many of the\n * demo applications.  Do not consider it to be part of the scheduler.\n *\n * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part of the\n * uxTaskGetSystemState() output into a human readable table that displays the\n * amount of time each task has spent in the Running state in both absolute and\n * percentage terms.\n *\n * vTaskGetRunTimeStats() has a dependency on the sprintf() C library function\n * that might bloat the code size, use a lot of stack, and provide different\n * results on different platforms.  An alternative, tiny, third party, and\n * limited functionality implementation of sprintf() is provided in many of the\n * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note\n * printf-stdarg.c does not provide a full snprintf() implementation!).\n *\n * It is recommended that production systems call uxTaskGetSystemState() directly\n * to get access to raw stats data, rather than indirectly through a call to\n * vTaskGetRunTimeStats().\n *\n * @param pcWriteBuffer A buffer into which the execution times will be\n * written, in ASCII form.  This buffer is assumed to be large enough to\n * contain the generated report.  Approximately 40 bytes per task should\n * be sufficient.\n *\n * \\defgroup vTaskGetRunTimeStats vTaskGetRunTimeStats\n * \\ingroup TaskUtils\n */\nvoid vTaskGetRunTimeStats( char * pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n\n/**\n * task. h\n * @code{c}\n * configRUN_TIME_COUNTER_TYPE ulTaskGetIdleRunTimeCounter( void );\n * configRUN_TIME_COUNTER_TYPE ulTaskGetIdleRunTimePercent( void );\n * @endcode\n *\n * configGENERATE_RUN_TIME_STATS, configUSE_STATS_FORMATTING_FUNCTIONS and\n * INCLUDE_xTaskGetIdleTaskHandle must all be defined as 1 for these functions\n * to be available.  The application must also then provide definitions for\n * portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE()\n * to configure a peripheral timer/counter and return the timers current count\n * value respectively.  The counter should be at least 10 times the frequency of\n * the tick count.\n *\n * Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total\n * accumulated execution time being stored for each task.  The resolution\n * of the accumulated time value depends on the frequency of the timer\n * configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro.\n * While uxTaskGetSystemState() and vTaskGetRunTimeStats() writes the total\n * execution time of each task into a buffer, ulTaskGetIdleRunTimeCounter()\n * returns the total execution time of just the idle task and\n * ulTaskGetIdleRunTimePercent() returns the percentage of the CPU time used by\n * just the idle task.\n *\n * Note the amount of idle time is only a good measure of the slack time in a\n * system if there are no other tasks executing at the idle priority, tickless\n * idle is not used, and configIDLE_SHOULD_YIELD is set to 0.\n *\n * @return The total run time of the idle task or the percentage of the total\n * run time consumed by the idle task.  This is the amount of time the\n * idle task has actually been executing.  The unit of time is dependent on the\n * frequency configured using the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and\n * portGET_RUN_TIME_COUNTER_VALUE() macros.\n *\n * \\defgroup ulTaskGetIdleRunTimeCounter ulTaskGetIdleRunTimeCounter\n * \\ingroup TaskUtils\n */\nconfigRUN_TIME_COUNTER_TYPE ulTaskGetIdleRunTimeCounter( void ) PRIVILEGED_FUNCTION;\nconfigRUN_TIME_COUNTER_TYPE ulTaskGetIdleRunTimePercent( void ) PRIVILEGED_FUNCTION;\n\n/**\n * task. h\n * @code{c}\n * BaseType_t xTaskNotifyIndexed( TaskHandle_t xTaskToNotify, UBaseType_t uxIndexToNotify, uint32_t ulValue, eNotifyAction eAction );\n * BaseType_t xTaskNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction );\n * @endcode\n *\n * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details.\n *\n * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for these\n * functions to be available.\n *\n * Sends a direct to task notification to a task, with an optional value and\n * action.\n *\n * Each task has a private array of \"notification values\" (or 'notifications'),\n * each of which is a 32-bit unsigned integer (uint32_t).  The constant\n * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the\n * array, and (for backward compatibility) defaults to 1 if left undefined.\n * Prior to FreeRTOS V10.4.0 there was only one notification value per task.\n *\n * Events can be sent to a task using an intermediary object.  Examples of such\n * objects are queues, semaphores, mutexes and event groups.  Task notifications\n * are a method of sending an event directly to a task without the need for such\n * an intermediary object.\n *\n * A notification sent to a task can optionally perform an action, such as\n * update, overwrite or increment one of the task's notification values.  In\n * that way task notifications can be used to send data to a task, or be used as\n * light weight and fast binary or counting semaphores.\n *\n * A task can use xTaskNotifyWaitIndexed() or ulTaskNotifyTakeIndexed() to\n * [optionally] block to wait for a notification to be pending.  The task does\n * not consume any CPU time while it is in the Blocked state.\n *\n * A notification sent to a task will remain pending until it is cleared by the\n * task calling xTaskNotifyWaitIndexed() or ulTaskNotifyTakeIndexed() (or their\n * un-indexed equivalents).  If the task was already in the Blocked state to\n * wait for a notification when the notification arrives then the task will\n * automatically be removed from the Blocked state (unblocked) and the\n * notification cleared.\n *\n * **NOTE** Each notification within the array operates independently - a task\n * can only block on one notification within the array at a time and will not be\n * unblocked by a notification sent to any other array index.\n *\n * Backward compatibility information:\n * Prior to FreeRTOS V10.4.0 each task had a single \"notification value\", and\n * all task notification API functions operated on that value. Replacing the\n * single notification value with an array of notification values necessitated a\n * new set of API functions that could address specific notifications within the\n * array.  xTaskNotify() is the original API function, and remains backward\n * compatible by always operating on the notification value at index 0 in the\n * array. Calling xTaskNotify() is equivalent to calling xTaskNotifyIndexed()\n * with the uxIndexToNotify parameter set to 0.\n *\n * @param xTaskToNotify The handle of the task being notified.  The handle to a\n * task can be returned from the xTaskCreate() API function used to create the\n * task, and the handle of the currently running task can be obtained by calling\n * xTaskGetCurrentTaskHandle().\n *\n * @param uxIndexToNotify The index within the target task's array of\n * notification values to which the notification is to be sent.  uxIndexToNotify\n * must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES.  xTaskNotify() does\n * not have this parameter and always sends notifications to index 0.\n *\n * @param ulValue Data that can be sent with the notification.  How the data is\n * used depends on the value of the eAction parameter.\n *\n * @param eAction Specifies how the notification updates the task's notification\n * value, if at all.  Valid values for eAction are as follows:\n *\n * eSetBits -\n * The target notification value is bitwise ORed with ulValue.\n * xTaskNotifyIndexed() always returns pdPASS in this case.\n *\n * eIncrement -\n * The target notification value is incremented.  ulValue is not used and\n * xTaskNotifyIndexed() always returns pdPASS in this case.\n *\n * eSetValueWithOverwrite -\n * The target notification value is set to the value of ulValue, even if the\n * task being notified had not yet processed the previous notification at the\n * same array index (the task already had a notification pending at that index).\n * xTaskNotifyIndexed() always returns pdPASS in this case.\n *\n * eSetValueWithoutOverwrite -\n * If the task being notified did not already have a notification pending at the\n * same array index then the target notification value is set to ulValue and\n * xTaskNotifyIndexed() will return pdPASS.  If the task being notified already\n * had a notification pending at the same array index then no action is\n * performed and pdFAIL is returned.\n *\n * eNoAction -\n * The task receives a notification at the specified array index without the\n * notification value at that index being updated.  ulValue is not used and\n * xTaskNotifyIndexed() always returns pdPASS in this case.\n *\n * pulPreviousNotificationValue -\n * Can be used to pass out the subject task's notification value before any\n * bits are modified by the notify function.\n *\n * @return Dependent on the value of eAction.  See the description of the\n * eAction parameter.\n *\n * \\defgroup xTaskNotifyIndexed xTaskNotifyIndexed\n * \\ingroup TaskNotifications\n */\nBaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify,\n                               UBaseType_t uxIndexToNotify,\n                               uint32_t ulValue,\n                               eNotifyAction eAction,\n                               uint32_t * pulPreviousNotificationValue ) PRIVILEGED_FUNCTION;\n#define xTaskNotify( xTaskToNotify, ulValue, eAction ) \\\n    xTaskGenericNotify( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulValue ), ( eAction ), NULL )\n#define xTaskNotifyIndexed( xTaskToNotify, uxIndexToNotify, ulValue, eAction ) \\\n    xTaskGenericNotify( ( xTaskToNotify ), ( uxIndexToNotify ), ( ulValue ), ( eAction ), NULL )\n\n/**\n * task. h\n * @code{c}\n * BaseType_t xTaskNotifyAndQueryIndexed( TaskHandle_t xTaskToNotify, UBaseType_t uxIndexToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotifyValue );\n * BaseType_t xTaskNotifyAndQuery( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotifyValue );\n * @endcode\n *\n * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details.\n *\n * xTaskNotifyAndQueryIndexed() performs the same operation as\n * xTaskNotifyIndexed() with the addition that it also returns the subject\n * task's prior notification value (the notification value at the time the\n * function is called rather than when the function returns) in the additional\n * pulPreviousNotifyValue parameter.\n *\n * xTaskNotifyAndQuery() performs the same operation as xTaskNotify() with the\n * addition that it also returns the subject task's prior notification value\n * (the notification value as it was at the time the function is called, rather\n * than when the function returns) in the additional pulPreviousNotifyValue\n * parameter.\n *\n * \\defgroup xTaskNotifyAndQueryIndexed xTaskNotifyAndQueryIndexed\n * \\ingroup TaskNotifications\n */\n#define xTaskNotifyAndQuery( xTaskToNotify, ulValue, eAction, pulPreviousNotifyValue ) \\\n    xTaskGenericNotify( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulValue ), ( eAction ), ( pulPreviousNotifyValue ) )\n#define xTaskNotifyAndQueryIndexed( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pulPreviousNotifyValue ) \\\n    xTaskGenericNotify( ( xTaskToNotify ), ( uxIndexToNotify ), ( ulValue ), ( eAction ), ( pulPreviousNotifyValue ) )\n\n/**\n * task. h\n * @code{c}\n * BaseType_t xTaskNotifyIndexedFromISR( TaskHandle_t xTaskToNotify, UBaseType_t uxIndexToNotify, uint32_t ulValue, eNotifyAction eAction, BaseType_t *pxHigherPriorityTaskWoken );\n * BaseType_t xTaskNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, BaseType_t *pxHigherPriorityTaskWoken );\n * @endcode\n *\n * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details.\n *\n * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for these\n * functions to be available.\n *\n * A version of xTaskNotifyIndexed() that can be used from an interrupt service\n * routine (ISR).\n *\n * Each task has a private array of \"notification values\" (or 'notifications'),\n * each of which is a 32-bit unsigned integer (uint32_t).  The constant\n * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the\n * array, and (for backward compatibility) defaults to 1 if left undefined.\n * Prior to FreeRTOS V10.4.0 there was only one notification value per task.\n *\n * Events can be sent to a task using an intermediary object.  Examples of such\n * objects are queues, semaphores, mutexes and event groups.  Task notifications\n * are a method of sending an event directly to a task without the need for such\n * an intermediary object.\n *\n * A notification sent to a task can optionally perform an action, such as\n * update, overwrite or increment one of the task's notification values.  In\n * that way task notifications can be used to send data to a task, or be used as\n * light weight and fast binary or counting semaphores.\n *\n * A task can use xTaskNotifyWaitIndexed() to [optionally] block to wait for a\n * notification to be pending, or ulTaskNotifyTakeIndexed() to [optionally] block\n * to wait for a notification value to have a non-zero value.  The task does\n * not consume any CPU time while it is in the Blocked state.\n *\n * A notification sent to a task will remain pending until it is cleared by the\n * task calling xTaskNotifyWaitIndexed() or ulTaskNotifyTakeIndexed() (or their\n * un-indexed equivalents).  If the task was already in the Blocked state to\n * wait for a notification when the notification arrives then the task will\n * automatically be removed from the Blocked state (unblocked) and the\n * notification cleared.\n *\n * **NOTE** Each notification within the array operates independently - a task\n * can only block on one notification within the array at a time and will not be\n * unblocked by a notification sent to any other array index.\n *\n * Backward compatibility information:\n * Prior to FreeRTOS V10.4.0 each task had a single \"notification value\", and\n * all task notification API functions operated on that value. Replacing the\n * single notification value with an array of notification values necessitated a\n * new set of API functions that could address specific notifications within the\n * array.  xTaskNotifyFromISR() is the original API function, and remains\n * backward compatible by always operating on the notification value at index 0\n * within the array. Calling xTaskNotifyFromISR() is equivalent to calling\n * xTaskNotifyIndexedFromISR() with the uxIndexToNotify parameter set to 0.\n *\n * @param uxIndexToNotify The index within the target task's array of\n * notification values to which the notification is to be sent.  uxIndexToNotify\n * must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES.  xTaskNotifyFromISR()\n * does not have this parameter and always sends notifications to index 0.\n *\n * @param xTaskToNotify The handle of the task being notified.  The handle to a\n * task can be returned from the xTaskCreate() API function used to create the\n * task, and the handle of the currently running task can be obtained by calling\n * xTaskGetCurrentTaskHandle().\n *\n * @param ulValue Data that can be sent with the notification.  How the data is\n * used depends on the value of the eAction parameter.\n *\n * @param eAction Specifies how the notification updates the task's notification\n * value, if at all.  Valid values for eAction are as follows:\n *\n * eSetBits -\n * The task's notification value is bitwise ORed with ulValue.  xTaskNotify()\n * always returns pdPASS in this case.\n *\n * eIncrement -\n * The task's notification value is incremented.  ulValue is not used and\n * xTaskNotify() always returns pdPASS in this case.\n *\n * eSetValueWithOverwrite -\n * The task's notification value is set to the value of ulValue, even if the\n * task being notified had not yet processed the previous notification (the\n * task already had a notification pending).  xTaskNotify() always returns\n * pdPASS in this case.\n *\n * eSetValueWithoutOverwrite -\n * If the task being notified did not already have a notification pending then\n * the task's notification value is set to ulValue and xTaskNotify() will\n * return pdPASS.  If the task being notified already had a notification\n * pending then no action is performed and pdFAIL is returned.\n *\n * eNoAction -\n * The task receives a notification without its notification value being\n * updated.  ulValue is not used and xTaskNotify() always returns pdPASS in\n * this case.\n *\n * @param pxHigherPriorityTaskWoken  xTaskNotifyFromISR() will set\n * *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the\n * task to which the notification was sent to leave the Blocked state, and the\n * unblocked task has a priority higher than the currently running task.  If\n * xTaskNotifyFromISR() sets this value to pdTRUE then a context switch should\n * be requested before the interrupt is exited.  How a context switch is\n * requested from an ISR is dependent on the port - see the documentation page\n * for the port in use.\n *\n * @return Dependent on the value of eAction.  See the description of the\n * eAction parameter.\n *\n * \\defgroup xTaskNotifyIndexedFromISR xTaskNotifyIndexedFromISR\n * \\ingroup TaskNotifications\n */\nBaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify,\n                                      UBaseType_t uxIndexToNotify,\n                                      uint32_t ulValue,\n                                      eNotifyAction eAction,\n                                      uint32_t * pulPreviousNotificationValue,\n                                      BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;\n#define xTaskNotifyFromISR( xTaskToNotify, ulValue, eAction, pxHigherPriorityTaskWoken ) \\\n    xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulValue ), ( eAction ), NULL, ( pxHigherPriorityTaskWoken ) )\n#define xTaskNotifyIndexedFromISR( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pxHigherPriorityTaskWoken ) \\\n    xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( uxIndexToNotify ), ( ulValue ), ( eAction ), NULL, ( pxHigherPriorityTaskWoken ) )\n\n/**\n * task. h\n * @code{c}\n * BaseType_t xTaskNotifyAndQueryIndexedFromISR( TaskHandle_t xTaskToNotify, UBaseType_t uxIndexToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken );\n * BaseType_t xTaskNotifyAndQueryFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken );\n * @endcode\n *\n * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details.\n *\n * xTaskNotifyAndQueryIndexedFromISR() performs the same operation as\n * xTaskNotifyIndexedFromISR() with the addition that it also returns the\n * subject task's prior notification value (the notification value at the time\n * the function is called rather than at the time the function returns) in the\n * additional pulPreviousNotifyValue parameter.\n *\n * xTaskNotifyAndQueryFromISR() performs the same operation as\n * xTaskNotifyFromISR() with the addition that it also returns the subject\n * task's prior notification value (the notification value at the time the\n * function is called rather than at the time the function returns) in the\n * additional pulPreviousNotifyValue parameter.\n *\n * \\defgroup xTaskNotifyAndQueryIndexedFromISR xTaskNotifyAndQueryIndexedFromISR\n * \\ingroup TaskNotifications\n */\n#define xTaskNotifyAndQueryIndexedFromISR( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pulPreviousNotificationValue, pxHigherPriorityTaskWoken ) \\\n    xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( uxIndexToNotify ), ( ulValue ), ( eAction ), ( pulPreviousNotificationValue ), ( pxHigherPriorityTaskWoken ) )\n#define xTaskNotifyAndQueryFromISR( xTaskToNotify, ulValue, eAction, pulPreviousNotificationValue, pxHigherPriorityTaskWoken ) \\\n    xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulValue ), ( eAction ), ( pulPreviousNotificationValue ), ( pxHigherPriorityTaskWoken ) )\n\n/**\n * task. h\n * @code{c}\n * BaseType_t xTaskNotifyWaitIndexed( UBaseType_t uxIndexToWaitOn, uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait );\n *\n * BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait );\n * @endcode\n *\n * Waits for a direct to task notification to be pending at a given index within\n * an array of direct to task notifications.\n *\n * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details.\n *\n * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this\n * function to be available.\n *\n * Each task has a private array of \"notification values\" (or 'notifications'),\n * each of which is a 32-bit unsigned integer (uint32_t).  The constant\n * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the\n * array, and (for backward compatibility) defaults to 1 if left undefined.\n * Prior to FreeRTOS V10.4.0 there was only one notification value per task.\n *\n * Events can be sent to a task using an intermediary object.  Examples of such\n * objects are queues, semaphores, mutexes and event groups.  Task notifications\n * are a method of sending an event directly to a task without the need for such\n * an intermediary object.\n *\n * A notification sent to a task can optionally perform an action, such as\n * update, overwrite or increment one of the task's notification values.  In\n * that way task notifications can be used to send data to a task, or be used as\n * light weight and fast binary or counting semaphores.\n *\n * A notification sent to a task will remain pending until it is cleared by the\n * task calling xTaskNotifyWaitIndexed() or ulTaskNotifyTakeIndexed() (or their\n * un-indexed equivalents).  If the task was already in the Blocked state to\n * wait for a notification when the notification arrives then the task will\n * automatically be removed from the Blocked state (unblocked) and the\n * notification cleared.\n *\n * A task can use xTaskNotifyWaitIndexed() to [optionally] block to wait for a\n * notification to be pending, or ulTaskNotifyTakeIndexed() to [optionally] block\n * to wait for a notification value to have a non-zero value.  The task does\n * not consume any CPU time while it is in the Blocked state.\n *\n * **NOTE** Each notification within the array operates independently - a task\n * can only block on one notification within the array at a time and will not be\n * unblocked by a notification sent to any other array index.\n *\n * Backward compatibility information:\n * Prior to FreeRTOS V10.4.0 each task had a single \"notification value\", and\n * all task notification API functions operated on that value. Replacing the\n * single notification value with an array of notification values necessitated a\n * new set of API functions that could address specific notifications within the\n * array.  xTaskNotifyWait() is the original API function, and remains backward\n * compatible by always operating on the notification value at index 0 in the\n * array. Calling xTaskNotifyWait() is equivalent to calling\n * xTaskNotifyWaitIndexed() with the uxIndexToWaitOn parameter set to 0.\n *\n * @param uxIndexToWaitOn The index within the calling task's array of\n * notification values on which the calling task will wait for a notification to\n * be received.  uxIndexToWaitOn must be less than\n * configTASK_NOTIFICATION_ARRAY_ENTRIES.  xTaskNotifyWait() does\n * not have this parameter and always waits for notifications on index 0.\n *\n * @param ulBitsToClearOnEntry Bits that are set in ulBitsToClearOnEntry value\n * will be cleared in the calling task's notification value before the task\n * checks to see if any notifications are pending, and optionally blocks if no\n * notifications are pending.  Setting ulBitsToClearOnEntry to ULONG_MAX (if\n * limits.h is included) or 0xffffffffUL (if limits.h is not included) will have\n * the effect of resetting the task's notification value to 0.  Setting\n * ulBitsToClearOnEntry to 0 will leave the task's notification value unchanged.\n *\n * @param ulBitsToClearOnExit If a notification is pending or received before\n * the calling task exits the xTaskNotifyWait() function then the task's\n * notification value (see the xTaskNotify() API function) is passed out using\n * the pulNotificationValue parameter.  Then any bits that are set in\n * ulBitsToClearOnExit will be cleared in the task's notification value (note\n * *pulNotificationValue is set before any bits are cleared).  Setting\n * ulBitsToClearOnExit to ULONG_MAX (if limits.h is included) or 0xffffffffUL\n * (if limits.h is not included) will have the effect of resetting the task's\n * notification value to 0 before the function exits.  Setting\n * ulBitsToClearOnExit to 0 will leave the task's notification value unchanged\n * when the function exits (in which case the value passed out in\n * pulNotificationValue will match the task's notification value).\n *\n * @param pulNotificationValue Used to pass the task's notification value out\n * of the function.  Note the value passed out will not be effected by the\n * clearing of any bits caused by ulBitsToClearOnExit being non-zero.\n *\n * @param xTicksToWait The maximum amount of time that the task should wait in\n * the Blocked state for a notification to be received, should a notification\n * not already be pending when xTaskNotifyWait() was called.  The task\n * will not consume any processing time while it is in the Blocked state.  This\n * is specified in kernel ticks, the macro pdMS_TO_TICKS( value_in_ms ) can be\n * used to convert a time specified in milliseconds to a time specified in\n * ticks.\n *\n * @return If a notification was received (including notifications that were\n * already pending when xTaskNotifyWait was called) then pdPASS is\n * returned.  Otherwise pdFAIL is returned.\n *\n * \\defgroup xTaskNotifyWaitIndexed xTaskNotifyWaitIndexed\n * \\ingroup TaskNotifications\n */\nBaseType_t xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,\n                                   uint32_t ulBitsToClearOnEntry,\n                                   uint32_t ulBitsToClearOnExit,\n                                   uint32_t * pulNotificationValue,\n                                   TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;\n#define xTaskNotifyWait( ulBitsToClearOnEntry, ulBitsToClearOnExit, pulNotificationValue, xTicksToWait ) \\\n    xTaskGenericNotifyWait( tskDEFAULT_INDEX_TO_NOTIFY, ( ulBitsToClearOnEntry ), ( ulBitsToClearOnExit ), ( pulNotificationValue ), ( xTicksToWait ) )\n#define xTaskNotifyWaitIndexed( uxIndexToWaitOn, ulBitsToClearOnEntry, ulBitsToClearOnExit, pulNotificationValue, xTicksToWait ) \\\n    xTaskGenericNotifyWait( ( uxIndexToWaitOn ), ( ulBitsToClearOnEntry ), ( ulBitsToClearOnExit ), ( pulNotificationValue ), ( xTicksToWait ) )\n\n/**\n * task. h\n * @code{c}\n * BaseType_t xTaskNotifyGiveIndexed( TaskHandle_t xTaskToNotify, UBaseType_t uxIndexToNotify );\n * BaseType_t xTaskNotifyGive( TaskHandle_t xTaskToNotify );\n * @endcode\n *\n * Sends a direct to task notification to a particular index in the target\n * task's notification array in a manner similar to giving a counting semaphore.\n *\n * See https://www.FreeRTOS.org/RTOS-task-notifications.html for more details.\n *\n * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for these\n * macros to be available.\n *\n * Each task has a private array of \"notification values\" (or 'notifications'),\n * each of which is a 32-bit unsigned integer (uint32_t).  The constant\n * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the\n * array, and (for backward compatibility) defaults to 1 if left undefined.\n * Prior to FreeRTOS V10.4.0 there was only one notification value per task.\n *\n * Events can be sent to a task using an intermediary object.  Examples of such\n * objects are queues, semaphores, mutexes and event groups.  Task notifications\n * are a method of sending an event directly to a task without the need for such\n * an intermediary object.\n *\n * A notification sent to a task can optionally perform an action, such as\n * update, overwrite or increment one of the task's notification values.  In\n * that way task notifications can be used to send data to a task, or be used as\n * light weight and fast binary or counting semaphores.\n *\n * xTaskNotifyGiveIndexed() is a helper macro intended for use when task\n * notifications are used as light weight and faster binary or counting\n * semaphore equivalents.  Actual FreeRTOS semaphores are given using the\n * xSemaphoreGive() API function, the equivalent action that instead uses a task\n * notification is xTaskNotifyGiveIndexed().\n *\n * When task notifications are being used as a binary or counting semaphore\n * equivalent then the task being notified should wait for the notification\n * using the ulTaskNotifyTakeIndexed() API function rather than the\n * xTaskNotifyWaitIndexed() API function.\n *\n * **NOTE** Each notification within the array operates independently - a task\n * can only block on one notification within the array at a time and will not be\n * unblocked by a notification sent to any other array index.\n *\n * Backward compatibility information:\n * Prior to FreeRTOS V10.4.0 each task had a single \"notification value\", and\n * all task notification API functions operated on that value. Replacing the\n * single notification value with an array of notification values necessitated a\n * new set of API functions that could address specific notifications within the\n * array.  xTaskNotifyGive() is the original API function, and remains backward\n * compatible by always operating on the notification value at index 0 in the\n * array. Calling xTaskNotifyGive() is equivalent to calling\n * xTaskNotifyGiveIndexed() with the uxIndexToNotify parameter set to 0.\n *\n * @param xTaskToNotify The handle of the task being notified.  The handle to a\n * task can be returned from the xTaskCreate() API function used to create the\n * task, and the handle of the currently running task can be obtained by calling\n * xTaskGetCurrentTaskHandle().\n *\n * @param uxIndexToNotify The index within the target task's array of\n * notification values to which the notification is to be sent.  uxIndexToNotify\n * must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES.  xTaskNotifyGive()\n * does not have this parameter and always sends notifications to index 0.\n *\n * @return xTaskNotifyGive() is a macro that calls xTaskNotify() with the\n * eAction parameter set to eIncrement - so pdPASS is always returned.\n *\n * \\defgroup xTaskNotifyGiveIndexed xTaskNotifyGiveIndexed\n * \\ingroup TaskNotifications\n */\n#define xTaskNotifyGive( xTaskToNotify ) \\\n    xTaskGenericNotify( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( 0 ), eIncrement, NULL )\n#define xTaskNotifyGiveIndexed( xTaskToNotify, uxIndexToNotify ) \\\n    xTaskGenericNotify( ( xTaskToNotify ), ( uxIndexToNotify ), ( 0 ), eIncrement, NULL )\n\n/**\n * task. h\n * @code{c}\n * void vTaskNotifyGiveIndexedFromISR( TaskHandle_t xTaskHandle, UBaseType_t uxIndexToNotify, BaseType_t *pxHigherPriorityTaskWoken );\n * void vTaskNotifyGiveFromISR( TaskHandle_t xTaskHandle, BaseType_t *pxHigherPriorityTaskWoken );\n * @endcode\n *\n * A version of xTaskNotifyGiveIndexed() that can be called from an interrupt\n * service routine (ISR).\n *\n * See https://www.FreeRTOS.org/RTOS-task-notifications.html for more details.\n *\n * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this macro\n * to be available.\n *\n * Each task has a private array of \"notification values\" (or 'notifications'),\n * each of which is a 32-bit unsigned integer (uint32_t).  The constant\n * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the\n * array, and (for backward compatibility) defaults to 1 if left undefined.\n * Prior to FreeRTOS V10.4.0 there was only one notification value per task.\n *\n * Events can be sent to a task using an intermediary object.  Examples of such\n * objects are queues, semaphores, mutexes and event groups.  Task notifications\n * are a method of sending an event directly to a task without the need for such\n * an intermediary object.\n *\n * A notification sent to a task can optionally perform an action, such as\n * update, overwrite or increment one of the task's notification values.  In\n * that way task notifications can be used to send data to a task, or be used as\n * light weight and fast binary or counting semaphores.\n *\n * vTaskNotifyGiveIndexedFromISR() is intended for use when task notifications\n * are used as light weight and faster binary or counting semaphore equivalents.\n * Actual FreeRTOS semaphores are given from an ISR using the\n * xSemaphoreGiveFromISR() API function, the equivalent action that instead uses\n * a task notification is vTaskNotifyGiveIndexedFromISR().\n *\n * When task notifications are being used as a binary or counting semaphore\n * equivalent then the task being notified should wait for the notification\n * using the ulTaskNotifyTakeIndexed() API function rather than the\n * xTaskNotifyWaitIndexed() API function.\n *\n * **NOTE** Each notification within the array operates independently - a task\n * can only block on one notification within the array at a time and will not be\n * unblocked by a notification sent to any other array index.\n *\n * Backward compatibility information:\n * Prior to FreeRTOS V10.4.0 each task had a single \"notification value\", and\n * all task notification API functions operated on that value. Replacing the\n * single notification value with an array of notification values necessitated a\n * new set of API functions that could address specific notifications within the\n * array.  xTaskNotifyFromISR() is the original API function, and remains\n * backward compatible by always operating on the notification value at index 0\n * within the array. Calling xTaskNotifyGiveFromISR() is equivalent to calling\n * xTaskNotifyGiveIndexedFromISR() with the uxIndexToNotify parameter set to 0.\n *\n * @param xTaskToNotify The handle of the task being notified.  The handle to a\n * task can be returned from the xTaskCreate() API function used to create the\n * task, and the handle of the currently running task can be obtained by calling\n * xTaskGetCurrentTaskHandle().\n *\n * @param uxIndexToNotify The index within the target task's array of\n * notification values to which the notification is to be sent.  uxIndexToNotify\n * must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES.\n * xTaskNotifyGiveFromISR() does not have this parameter and always sends\n * notifications to index 0.\n *\n * @param pxHigherPriorityTaskWoken  vTaskNotifyGiveFromISR() will set\n * *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the\n * task to which the notification was sent to leave the Blocked state, and the\n * unblocked task has a priority higher than the currently running task.  If\n * vTaskNotifyGiveFromISR() sets this value to pdTRUE then a context switch\n * should be requested before the interrupt is exited.  How a context switch is\n * requested from an ISR is dependent on the port - see the documentation page\n * for the port in use.\n *\n * \\defgroup vTaskNotifyGiveIndexedFromISR vTaskNotifyGiveIndexedFromISR\n * \\ingroup TaskNotifications\n */\nvoid vTaskGenericNotifyGiveFromISR( TaskHandle_t xTaskToNotify,\n                                    UBaseType_t uxIndexToNotify,\n                                    BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;\n#define vTaskNotifyGiveFromISR( xTaskToNotify, pxHigherPriorityTaskWoken ) \\\n    vTaskGenericNotifyGiveFromISR( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( pxHigherPriorityTaskWoken ) )\n#define vTaskNotifyGiveIndexedFromISR( xTaskToNotify, uxIndexToNotify, pxHigherPriorityTaskWoken ) \\\n    vTaskGenericNotifyGiveFromISR( ( xTaskToNotify ), ( uxIndexToNotify ), ( pxHigherPriorityTaskWoken ) )\n\n/**\n * task. h\n * @code{c}\n * uint32_t ulTaskNotifyTakeIndexed( UBaseType_t uxIndexToWaitOn, BaseType_t xClearCountOnExit, TickType_t xTicksToWait );\n *\n * uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait );\n * @endcode\n *\n * Waits for a direct to task notification on a particular index in the calling\n * task's notification array in a manner similar to taking a counting semaphore.\n *\n * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details.\n *\n * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this\n * function to be available.\n *\n * Each task has a private array of \"notification values\" (or 'notifications'),\n * each of which is a 32-bit unsigned integer (uint32_t).  The constant\n * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the\n * array, and (for backward compatibility) defaults to 1 if left undefined.\n * Prior to FreeRTOS V10.4.0 there was only one notification value per task.\n *\n * Events can be sent to a task using an intermediary object.  Examples of such\n * objects are queues, semaphores, mutexes and event groups.  Task notifications\n * are a method of sending an event directly to a task without the need for such\n * an intermediary object.\n *\n * A notification sent to a task can optionally perform an action, such as\n * update, overwrite or increment one of the task's notification values.  In\n * that way task notifications can be used to send data to a task, or be used as\n * light weight and fast binary or counting semaphores.\n *\n * ulTaskNotifyTakeIndexed() is intended for use when a task notification is\n * used as a faster and lighter weight binary or counting semaphore alternative.\n * Actual FreeRTOS semaphores are taken using the xSemaphoreTake() API function,\n * the equivalent action that instead uses a task notification is\n * ulTaskNotifyTakeIndexed().\n *\n * When a task is using its notification value as a binary or counting semaphore\n * other tasks should send notifications to it using the xTaskNotifyGiveIndexed()\n * macro, or xTaskNotifyIndex() function with the eAction parameter set to\n * eIncrement.\n *\n * ulTaskNotifyTakeIndexed() can either clear the task's notification value at\n * the array index specified by the uxIndexToWaitOn parameter to zero on exit,\n * in which case the notification value acts like a binary semaphore, or\n * decrement the notification value on exit, in which case the notification\n * value acts like a counting semaphore.\n *\n * A task can use ulTaskNotifyTakeIndexed() to [optionally] block to wait for\n * a notification.  The task does not consume any CPU time while it is in the\n * Blocked state.\n *\n * Where as xTaskNotifyWaitIndexed() will return when a notification is pending,\n * ulTaskNotifyTakeIndexed() will return when the task's notification value is\n * not zero.\n *\n * **NOTE** Each notification within the array operates independently - a task\n * can only block on one notification within the array at a time and will not be\n * unblocked by a notification sent to any other array index.\n *\n * Backward compatibility information:\n * Prior to FreeRTOS V10.4.0 each task had a single \"notification value\", and\n * all task notification API functions operated on that value. Replacing the\n * single notification value with an array of notification values necessitated a\n * new set of API functions that could address specific notifications within the\n * array.  ulTaskNotifyTake() is the original API function, and remains backward\n * compatible by always operating on the notification value at index 0 in the\n * array. Calling ulTaskNotifyTake() is equivalent to calling\n * ulTaskNotifyTakeIndexed() with the uxIndexToWaitOn parameter set to 0.\n *\n * @param uxIndexToWaitOn The index within the calling task's array of\n * notification values on which the calling task will wait for a notification to\n * be non-zero.  uxIndexToWaitOn must be less than\n * configTASK_NOTIFICATION_ARRAY_ENTRIES.  xTaskNotifyTake() does\n * not have this parameter and always waits for notifications on index 0.\n *\n * @param xClearCountOnExit if xClearCountOnExit is pdFALSE then the task's\n * notification value is decremented when the function exits.  In this way the\n * notification value acts like a counting semaphore.  If xClearCountOnExit is\n * not pdFALSE then the task's notification value is cleared to zero when the\n * function exits.  In this way the notification value acts like a binary\n * semaphore.\n *\n * @param xTicksToWait The maximum amount of time that the task should wait in\n * the Blocked state for the task's notification value to be greater than zero,\n * should the count not already be greater than zero when\n * ulTaskNotifyTake() was called.  The task will not consume any processing\n * time while it is in the Blocked state.  This is specified in kernel ticks,\n * the macro pdMS_TO_TICKS( value_in_ms ) can be used to convert a time\n * specified in milliseconds to a time specified in ticks.\n *\n * @return The task's notification count before it is either cleared to zero or\n * decremented (see the xClearCountOnExit parameter).\n *\n * \\defgroup ulTaskNotifyTakeIndexed ulTaskNotifyTakeIndexed\n * \\ingroup TaskNotifications\n */\nuint32_t ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,\n                                  BaseType_t xClearCountOnExit,\n                                  TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;\n#define ulTaskNotifyTake( xClearCountOnExit, xTicksToWait ) \\\n    ulTaskGenericNotifyTake( ( tskDEFAULT_INDEX_TO_NOTIFY ), ( xClearCountOnExit ), ( xTicksToWait ) )\n#define ulTaskNotifyTakeIndexed( uxIndexToWaitOn, xClearCountOnExit, xTicksToWait ) \\\n    ulTaskGenericNotifyTake( ( uxIndexToWaitOn ), ( xClearCountOnExit ), ( xTicksToWait ) )\n\n/**\n * task. h\n * @code{c}\n * BaseType_t xTaskNotifyStateClearIndexed( TaskHandle_t xTask, UBaseType_t uxIndexToCLear );\n *\n * BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask );\n * @endcode\n *\n * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details.\n *\n * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for these\n * functions to be available.\n *\n * Each task has a private array of \"notification values\" (or 'notifications'),\n * each of which is a 32-bit unsigned integer (uint32_t).  The constant\n * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the\n * array, and (for backward compatibility) defaults to 1 if left undefined.\n * Prior to FreeRTOS V10.4.0 there was only one notification value per task.\n *\n * If a notification is sent to an index within the array of notifications then\n * the notification at that index is said to be 'pending' until it is read or\n * explicitly cleared by the receiving task.  xTaskNotifyStateClearIndexed()\n * is the function that clears a pending notification without reading the\n * notification value.  The notification value at the same array index is not\n * altered.  Set xTask to NULL to clear the notification state of the calling\n * task.\n *\n * Backward compatibility information:\n * Prior to FreeRTOS V10.4.0 each task had a single \"notification value\", and\n * all task notification API functions operated on that value. Replacing the\n * single notification value with an array of notification values necessitated a\n * new set of API functions that could address specific notifications within the\n * array.  xTaskNotifyStateClear() is the original API function, and remains\n * backward compatible by always operating on the notification value at index 0\n * within the array. Calling xTaskNotifyStateClear() is equivalent to calling\n * xTaskNotifyStateClearIndexed() with the uxIndexToNotify parameter set to 0.\n *\n * @param xTask The handle of the RTOS task that will have a notification state\n * cleared.  Set xTask to NULL to clear a notification state in the calling\n * task.  To obtain a task's handle create the task using xTaskCreate() and\n * make use of the pxCreatedTask parameter, or create the task using\n * xTaskCreateStatic() and store the returned value, or use the task's name in\n * a call to xTaskGetHandle().\n *\n * @param uxIndexToClear The index within the target task's array of\n * notification values to act upon.  For example, setting uxIndexToClear to 1\n * will clear the state of the notification at index 1 within the array.\n * uxIndexToClear must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES.\n * ulTaskNotifyStateClear() does not have this parameter and always acts on the\n * notification at index 0.\n *\n * @return pdTRUE if the task's notification state was set to\n * eNotWaitingNotification, otherwise pdFALSE.\n *\n * \\defgroup xTaskNotifyStateClearIndexed xTaskNotifyStateClearIndexed\n * \\ingroup TaskNotifications\n */\nBaseType_t xTaskGenericNotifyStateClear( TaskHandle_t xTask,\n                                         UBaseType_t uxIndexToClear ) PRIVILEGED_FUNCTION;\n#define xTaskNotifyStateClear( xTask ) \\\n    xTaskGenericNotifyStateClear( ( xTask ), ( tskDEFAULT_INDEX_TO_NOTIFY ) )\n#define xTaskNotifyStateClearIndexed( xTask, uxIndexToClear ) \\\n    xTaskGenericNotifyStateClear( ( xTask ), ( uxIndexToClear ) )\n\n/**\n * task. h\n * @code{c}\n * uint32_t ulTaskNotifyValueClearIndexed( TaskHandle_t xTask, UBaseType_t uxIndexToClear, uint32_t ulBitsToClear );\n *\n * uint32_t ulTaskNotifyValueClear( TaskHandle_t xTask, uint32_t ulBitsToClear );\n * @endcode\n *\n * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details.\n *\n * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for these\n * functions to be available.\n *\n * Each task has a private array of \"notification values\" (or 'notifications'),\n * each of which is a 32-bit unsigned integer (uint32_t).  The constant\n * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the\n * array, and (for backward compatibility) defaults to 1 if left undefined.\n * Prior to FreeRTOS V10.4.0 there was only one notification value per task.\n *\n * ulTaskNotifyValueClearIndexed() clears the bits specified by the\n * ulBitsToClear bit mask in the notification value at array index uxIndexToClear\n * of the task referenced by xTask.\n *\n * Backward compatibility information:\n * Prior to FreeRTOS V10.4.0 each task had a single \"notification value\", and\n * all task notification API functions operated on that value. Replacing the\n * single notification value with an array of notification values necessitated a\n * new set of API functions that could address specific notifications within the\n * array.  ulTaskNotifyValueClear() is the original API function, and remains\n * backward compatible by always operating on the notification value at index 0\n * within the array. Calling ulTaskNotifyValueClear() is equivalent to calling\n * ulTaskNotifyValueClearIndexed() with the uxIndexToClear parameter set to 0.\n *\n * @param xTask The handle of the RTOS task that will have bits in one of its\n * notification values cleared. Set xTask to NULL to clear bits in a\n * notification value of the calling task.  To obtain a task's handle create the\n * task using xTaskCreate() and make use of the pxCreatedTask parameter, or\n * create the task using xTaskCreateStatic() and store the returned value, or\n * use the task's name in a call to xTaskGetHandle().\n *\n * @param uxIndexToClear The index within the target task's array of\n * notification values in which to clear the bits.  uxIndexToClear\n * must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES.\n * ulTaskNotifyValueClear() does not have this parameter and always clears bits\n * in the notification value at index 0.\n *\n * @param ulBitsToClear Bit mask of the bits to clear in the notification value of\n * xTask. Set a bit to 1 to clear the corresponding bits in the task's notification\n * value. Set ulBitsToClear to 0xffffffff (UINT_MAX on 32-bit architectures) to clear\n * the notification value to 0.  Set ulBitsToClear to 0 to query the task's\n * notification value without clearing any bits.\n *\n *\n * @return The value of the target task's notification value before the bits\n * specified by ulBitsToClear were cleared.\n * \\defgroup ulTaskNotifyValueClear ulTaskNotifyValueClear\n * \\ingroup TaskNotifications\n */\nuint32_t ulTaskGenericNotifyValueClear( TaskHandle_t xTask,\n                                        UBaseType_t uxIndexToClear,\n                                        uint32_t ulBitsToClear ) PRIVILEGED_FUNCTION;\n#define ulTaskNotifyValueClear( xTask, ulBitsToClear ) \\\n    ulTaskGenericNotifyValueClear( ( xTask ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulBitsToClear ) )\n#define ulTaskNotifyValueClearIndexed( xTask, uxIndexToClear, ulBitsToClear ) \\\n    ulTaskGenericNotifyValueClear( ( xTask ), ( uxIndexToClear ), ( ulBitsToClear ) )\n\n/**\n * task.h\n * @code{c}\n * void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut );\n * @endcode\n *\n * Capture the current time for future use with xTaskCheckForTimeOut().\n *\n * @param pxTimeOut Pointer to a timeout object into which the current time\n * is to be captured.  The captured time includes the tick count and the number\n * of times the tick count has overflowed since the system first booted.\n * \\defgroup vTaskSetTimeOutState vTaskSetTimeOutState\n * \\ingroup TaskCtrl\n */\nvoid vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION;\n\n/**\n * task.h\n * @code{c}\n * BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait );\n * @endcode\n *\n * Determines if pxTicksToWait ticks has passed since a time was captured\n * using a call to vTaskSetTimeOutState().  The captured time includes the tick\n * count and the number of times the tick count has overflowed.\n *\n * @param pxTimeOut The time status as captured previously using\n * vTaskSetTimeOutState. If the timeout has not yet occurred, it is updated\n * to reflect the current time status.\n * @param pxTicksToWait The number of ticks to check for timeout i.e. if\n * pxTicksToWait ticks have passed since pxTimeOut was last updated (either by\n * vTaskSetTimeOutState() or xTaskCheckForTimeOut()), the timeout has occurred.\n * If the timeout has not occurred, pxTicksToWait is updated to reflect the\n * number of remaining ticks.\n *\n * @return If timeout has occurred, pdTRUE is returned. Otherwise pdFALSE is\n * returned and pxTicksToWait is updated to reflect the number of remaining\n * ticks.\n *\n * @see https://www.FreeRTOS.org/xTaskCheckForTimeOut.html\n *\n * Example Usage:\n * @code{c}\n *  // Driver library function used to receive uxWantedBytes from an Rx buffer\n *  // that is filled by a UART interrupt. If there are not enough bytes in the\n *  // Rx buffer then the task enters the Blocked state until it is notified that\n *  // more data has been placed into the buffer. If there is still not enough\n *  // data then the task re-enters the Blocked state, and xTaskCheckForTimeOut()\n *  // is used to re-calculate the Block time to ensure the total amount of time\n *  // spent in the Blocked state does not exceed MAX_TIME_TO_WAIT. This\n *  // continues until either the buffer contains at least uxWantedBytes bytes,\n *  // or the total amount of time spent in the Blocked state reaches\n *  // MAX_TIME_TO_WAIT - at which point the task reads however many bytes are\n *  // available up to a maximum of uxWantedBytes.\n *\n *  size_t xUART_Receive( uint8_t *pucBuffer, size_t uxWantedBytes )\n *  {\n *  size_t uxReceived = 0;\n *  TickType_t xTicksToWait = MAX_TIME_TO_WAIT;\n *  TimeOut_t xTimeOut;\n *\n *      // Initialize xTimeOut.  This records the time at which this function\n *      // was entered.\n *      vTaskSetTimeOutState( &xTimeOut );\n *\n *      // Loop until the buffer contains the wanted number of bytes, or a\n *      // timeout occurs.\n *      while( UART_bytes_in_rx_buffer( pxUARTInstance ) < uxWantedBytes )\n *      {\n *          // The buffer didn't contain enough data so this task is going to\n *          // enter the Blocked state. Adjusting xTicksToWait to account for\n *          // any time that has been spent in the Blocked state within this\n *          // function so far to ensure the total amount of time spent in the\n *          // Blocked state does not exceed MAX_TIME_TO_WAIT.\n *          if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) != pdFALSE )\n *          {\n *              //Timed out before the wanted number of bytes were available,\n *              // exit the loop.\n *              break;\n *          }\n *\n *          // Wait for a maximum of xTicksToWait ticks to be notified that the\n *          // receive interrupt has placed more data into the buffer.\n *          ulTaskNotifyTake( pdTRUE, xTicksToWait );\n *      }\n *\n *      // Attempt to read uxWantedBytes from the receive buffer into pucBuffer.\n *      // The actual number of bytes read (which might be less than\n *      // uxWantedBytes) is returned.\n *      uxReceived = UART_read_from_receive_buffer( pxUARTInstance,\n *                                                  pucBuffer,\n *                                                  uxWantedBytes );\n *\n *      return uxReceived;\n *  }\n * @endcode\n * \\defgroup xTaskCheckForTimeOut xTaskCheckForTimeOut\n * \\ingroup TaskCtrl\n */\nBaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,\n                                 TickType_t * const pxTicksToWait ) PRIVILEGED_FUNCTION;\n\n/**\n * task.h\n * @code{c}\n * BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp );\n * @endcode\n *\n * This function corrects the tick count value after the application code has held\n * interrupts disabled for an extended period resulting in tick interrupts having\n * been missed.\n *\n * This function is similar to vTaskStepTick(), however, unlike\n * vTaskStepTick(), xTaskCatchUpTicks() may move the tick count forward past a\n * time at which a task should be removed from the blocked state.  That means\n * tasks may have to be removed from the blocked state as the tick count is\n * moved.\n *\n * @param xTicksToCatchUp The number of tick interrupts that have been missed due to\n * interrupts being disabled.  Its value is not computed automatically, so must be\n * computed by the application writer.\n *\n * @return pdTRUE if moving the tick count forward resulted in a task leaving the\n * blocked state and a context switch being performed.  Otherwise pdFALSE.\n *\n * \\defgroup xTaskCatchUpTicks xTaskCatchUpTicks\n * \\ingroup TaskCtrl\n */\nBaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) PRIVILEGED_FUNCTION;\n\n\n/*-----------------------------------------------------------\n* SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES\n*----------------------------------------------------------*/\n\n/*\n * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS ONLY\n * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS\n * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.\n *\n * Called from the real time kernel tick (either preemptive or cooperative),\n * this increments the tick count and checks if any tasks that are blocked\n * for a finite period required removing from a blocked list and placing on\n * a ready list.  If a non-zero value is returned then a context switch is\n * required because either:\n *   + A task was removed from a blocked list because its timeout had expired,\n *     or\n *   + Time slicing is in use and there is a task of equal priority to the\n *     currently running task.\n */\nBaseType_t xTaskIncrementTick( void ) PRIVILEGED_FUNCTION;\n\n/*\n * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN\n * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.\n *\n * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.\n *\n * Removes the calling task from the ready list and places it both\n * on the list of tasks waiting for a particular event, and the\n * list of delayed tasks.  The task will be removed from both lists\n * and replaced on the ready list should either the event occur (and\n * there be no higher priority tasks waiting on the same event) or\n * the delay period expires.\n *\n * The 'unordered' version replaces the event list item value with the\n * xItemValue value, and inserts the list item at the end of the list.\n *\n * The 'ordered' version uses the existing event list item value (which is the\n * owning task's priority) to insert the list item into the event list in task\n * priority order.\n *\n * @param pxEventList The list containing tasks that are blocked waiting\n * for the event to occur.\n *\n * @param xItemValue The item value to use for the event list item when the\n * event list is not ordered by task priority.\n *\n * @param xTicksToWait The maximum amount of time that the task should wait\n * for the event to occur.  This is specified in kernel ticks, the constant\n * portTICK_PERIOD_MS can be used to convert kernel ticks into a real time\n * period.\n */\nvoid vTaskPlaceOnEventList( List_t * const pxEventList,\n                            const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;\nvoid vTaskPlaceOnUnorderedEventList( List_t * pxEventList,\n                                     const TickType_t xItemValue,\n                                     const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;\n\n/*\n * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN\n * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.\n *\n * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.\n *\n * This function performs nearly the same function as vTaskPlaceOnEventList().\n * The difference being that this function does not permit tasks to block\n * indefinitely, whereas vTaskPlaceOnEventList() does.\n *\n */\nvoid vTaskPlaceOnEventListRestricted( List_t * const pxEventList,\n                                      TickType_t xTicksToWait,\n                                      const BaseType_t xWaitIndefinitely ) PRIVILEGED_FUNCTION;\n\n/*\n * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN\n * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.\n *\n * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.\n *\n * Removes a task from both the specified event list and the list of blocked\n * tasks, and places it on a ready queue.\n *\n * xTaskRemoveFromEventList()/vTaskRemoveFromUnorderedEventList() will be called\n * if either an event occurs to unblock a task, or the block timeout period\n * expires.\n *\n * xTaskRemoveFromEventList() is used when the event list is in task priority\n * order.  It removes the list item from the head of the event list as that will\n * have the highest priority owning task of all the tasks on the event list.\n * vTaskRemoveFromUnorderedEventList() is used when the event list is not\n * ordered and the event list items hold something other than the owning tasks\n * priority.  In this case the event list item value is updated to the value\n * passed in the xItemValue parameter.\n *\n * @return pdTRUE if the task being removed has a higher priority than the task\n * making the call, otherwise pdFALSE.\n */\nBaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList ) PRIVILEGED_FUNCTION;\nvoid vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem,\n                                        const TickType_t xItemValue ) PRIVILEGED_FUNCTION;\n\n/*\n * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS ONLY\n * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS\n * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.\n *\n * Sets the pointer to the current TCB to the TCB of the highest priority task\n * that is ready to run.\n */\nportDONT_DISCARD void vTaskSwitchContext( void ) PRIVILEGED_FUNCTION;\n\n/*\n * THESE FUNCTIONS MUST NOT BE USED FROM APPLICATION CODE.  THEY ARE USED BY\n * THE EVENT BITS MODULE.\n */\nTickType_t uxTaskResetEventItemValue( void ) PRIVILEGED_FUNCTION;\n\n/*\n * Return the handle of the calling task.\n */\nTaskHandle_t xTaskGetCurrentTaskHandle( void ) PRIVILEGED_FUNCTION;\n\n/*\n * Shortcut used by the queue implementation to prevent unnecessary call to\n * taskYIELD();\n */\nvoid vTaskMissedYield( void ) PRIVILEGED_FUNCTION;\n\n/*\n * Returns the scheduler state as taskSCHEDULER_RUNNING,\n * taskSCHEDULER_NOT_STARTED or taskSCHEDULER_SUSPENDED.\n */\nBaseType_t xTaskGetSchedulerState( void ) PRIVILEGED_FUNCTION;\n\n/*\n * Raises the priority of the mutex holder to that of the calling task should\n * the mutex holder have a priority less than the calling task.\n */\nBaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION;\n\n/*\n * Set the priority of a task back to its proper priority in the case that it\n * inherited a higher priority while it was holding a semaphore.\n */\nBaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION;\n\n/*\n * If a higher priority task attempting to obtain a mutex caused a lower\n * priority task to inherit the higher priority task's priority - but the higher\n * priority task then timed out without obtaining the mutex, then the lower\n * priority task will disinherit the priority again - but only down as far as\n * the highest priority task that is still waiting for the mutex (if there were\n * more than one task waiting for the mutex).\n */\nvoid vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder,\n                                          UBaseType_t uxHighestPriorityWaitingTask ) PRIVILEGED_FUNCTION;\n\n/*\n * Get the uxTaskNumber assigned to the task referenced by the xTask parameter.\n */\nUBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;\n\n/*\n * Set the uxTaskNumber of the task referenced by the xTask parameter to\n * uxHandle.\n */\nvoid vTaskSetTaskNumber( TaskHandle_t xTask,\n                         const UBaseType_t uxHandle ) PRIVILEGED_FUNCTION;\n\n/*\n * Only available when configUSE_TICKLESS_IDLE is set to 1.\n * If tickless mode is being used, or a low power mode is implemented, then\n * the tick interrupt will not execute during idle periods.  When this is the\n * case, the tick count value maintained by the scheduler needs to be kept up\n * to date with the actual execution time by being skipped forward by a time\n * equal to the idle period.\n */\nvoid vTaskStepTick( TickType_t xTicksToJump ) PRIVILEGED_FUNCTION;\n\n/*\n * Only available when configUSE_TICKLESS_IDLE is set to 1.\n * Provided for use within portSUPPRESS_TICKS_AND_SLEEP() to allow the port\n * specific sleep function to determine if it is ok to proceed with the sleep,\n * and if it is ok to proceed, if it is ok to sleep indefinitely.\n *\n * This function is necessary because portSUPPRESS_TICKS_AND_SLEEP() is only\n * called with the scheduler suspended, not from within a critical section.  It\n * is therefore possible for an interrupt to request a context switch between\n * portSUPPRESS_TICKS_AND_SLEEP() and the low power mode actually being\n * entered.  eTaskConfirmSleepModeStatus() should be called from a short\n * critical section between the timer being stopped and the sleep mode being\n * entered to ensure it is ok to proceed into the sleep mode.\n */\neSleepModeStatus eTaskConfirmSleepModeStatus( void ) PRIVILEGED_FUNCTION;\n\n/*\n * For internal use only.  Increment the mutex held count when a mutex is\n * taken and return the handle of the task that has taken the mutex.\n */\nTaskHandle_t pvTaskIncrementMutexHeldCount( void ) PRIVILEGED_FUNCTION;\n\n/*\n * For internal use only.  Same as vTaskSetTimeOutState(), but without a critical\n * section.\n */\nvoid vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION;\n\n\n/* *INDENT-OFF* */\n#ifdef __cplusplus\n    }\n#endif\n/* *INDENT-ON* */\n#endif /* INC_TASK_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/include/timers.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n\n#ifndef TIMERS_H\n#define TIMERS_H\n\n#ifndef INC_FREERTOS_H\n    #error \"include FreeRTOS.h must appear in source files before include timers.h\"\n#endif\n\n/*lint -save -e537 This headers are only multiply included if the application code\n * happens to also be including task.h. */\n#include \"task.h\"\n/*lint -restore */\n\n/* *INDENT-OFF* */\n#ifdef __cplusplus\n    extern \"C\" {\n#endif\n/* *INDENT-ON* */\n\n/*-----------------------------------------------------------\n* MACROS AND DEFINITIONS\n*----------------------------------------------------------*/\n\n/* IDs for commands that can be sent/received on the timer queue.  These are to\n * be used solely through the macros that make up the public software timer API,\n * as defined below.  The commands that are sent from interrupts must use the\n * highest numbers as tmrFIRST_FROM_ISR_COMMAND is used to determine if the task\n * or interrupt version of the queue send function should be used. */\n#define tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR    ( ( BaseType_t ) -2 )\n#define tmrCOMMAND_EXECUTE_CALLBACK             ( ( BaseType_t ) -1 )\n#define tmrCOMMAND_START_DONT_TRACE             ( ( BaseType_t ) 0 )\n#define tmrCOMMAND_START                        ( ( BaseType_t ) 1 )\n#define tmrCOMMAND_RESET                        ( ( BaseType_t ) 2 )\n#define tmrCOMMAND_STOP                         ( ( BaseType_t ) 3 )\n#define tmrCOMMAND_CHANGE_PERIOD                ( ( BaseType_t ) 4 )\n#define tmrCOMMAND_DELETE                       ( ( BaseType_t ) 5 )\n\n#define tmrFIRST_FROM_ISR_COMMAND               ( ( BaseType_t ) 6 )\n#define tmrCOMMAND_START_FROM_ISR               ( ( BaseType_t ) 6 )\n#define tmrCOMMAND_RESET_FROM_ISR               ( ( BaseType_t ) 7 )\n#define tmrCOMMAND_STOP_FROM_ISR                ( ( BaseType_t ) 8 )\n#define tmrCOMMAND_CHANGE_PERIOD_FROM_ISR       ( ( BaseType_t ) 9 )\n\n\n/**\n * Type by which software timers are referenced.  For example, a call to\n * xTimerCreate() returns an TimerHandle_t variable that can then be used to\n * reference the subject timer in calls to other software timer API functions\n * (for example, xTimerStart(), xTimerReset(), etc.).\n */\nstruct tmrTimerControl; /* The old naming convention is used to prevent breaking kernel aware debuggers. */\ntypedef struct tmrTimerControl * TimerHandle_t;\n\n/*\n * Defines the prototype to which timer callback functions must conform.\n */\ntypedef void (* TimerCallbackFunction_t)( TimerHandle_t xTimer );\n\n/*\n * Defines the prototype to which functions used with the\n * xTimerPendFunctionCallFromISR() function must conform.\n */\ntypedef void (* PendedFunction_t)( void *,\n                                   uint32_t );\n\n/**\n * TimerHandle_t xTimerCreate(  const char * const pcTimerName,\n *                              TickType_t xTimerPeriodInTicks,\n *                              BaseType_t xAutoReload,\n *                              void * pvTimerID,\n *                              TimerCallbackFunction_t pxCallbackFunction );\n *\n * Creates a new software timer instance, and returns a handle by which the\n * created software timer can be referenced.\n *\n * Internally, within the FreeRTOS implementation, software timers use a block\n * of memory, in which the timer data structure is stored.  If a software timer\n * is created using xTimerCreate() then the required memory is automatically\n * dynamically allocated inside the xTimerCreate() function.  (see\n * https://www.FreeRTOS.org/a00111.html).  If a software timer is created using\n * xTimerCreateStatic() then the application writer must provide the memory that\n * will get used by the software timer.  xTimerCreateStatic() therefore allows a\n * software timer to be created without using any dynamic memory allocation.\n *\n * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),\n * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and\n * xTimerChangePeriodFromISR() API functions can all be used to transition a\n * timer into the active state.\n *\n * @param pcTimerName A text name that is assigned to the timer.  This is done\n * purely to assist debugging.  The kernel itself only ever references a timer\n * by its handle, and never by its name.\n *\n * @param xTimerPeriodInTicks The timer period.  The time is defined in tick\n * periods so the constant portTICK_PERIOD_MS can be used to convert a time that\n * has been specified in milliseconds.  For example, if the timer must expire\n * after 100 ticks, then xTimerPeriodInTicks should be set to 100.\n * Alternatively, if the timer must expire after 500ms, then xPeriod can be set\n * to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or\n * equal to 1000.  Time timer period must be greater than 0.\n *\n * @param xAutoReload If xAutoReload is set to pdTRUE then the timer will\n * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter.\n * If xAutoReload is set to pdFALSE then the timer will be a one-shot timer and\n * enter the dormant state after it expires.\n *\n * @param pvTimerID An identifier that is assigned to the timer being created.\n * Typically this would be used in the timer callback function to identify which\n * timer expired when the same callback function is assigned to more than one\n * timer.\n *\n * @param pxCallbackFunction The function to call when the timer expires.\n * Callback functions must have the prototype defined by TimerCallbackFunction_t,\n * which is \"void vCallbackFunction( TimerHandle_t xTimer );\".\n *\n * @return If the timer is successfully created then a handle to the newly\n * created timer is returned.  If the timer cannot be created because there is\n * insufficient FreeRTOS heap remaining to allocate the timer\n * structures then NULL is returned.\n *\n * Example usage:\n * @verbatim\n * #define NUM_TIMERS 5\n *\n * // An array to hold handles to the created timers.\n * TimerHandle_t xTimers[ NUM_TIMERS ];\n *\n * // An array to hold a count of the number of times each timer expires.\n * int32_t lExpireCounters[ NUM_TIMERS ] = { 0 };\n *\n * // Define a callback function that will be used by multiple timer instances.\n * // The callback function does nothing but count the number of times the\n * // associated timer expires, and stop the timer once the timer has expired\n * // 10 times.\n * void vTimerCallback( TimerHandle_t pxTimer )\n * {\n * int32_t lArrayIndex;\n * const int32_t xMaxExpiryCountBeforeStopping = 10;\n *\n *     // Optionally do something if the pxTimer parameter is NULL.\n *     configASSERT( pxTimer );\n *\n *     // Which timer expired?\n *     lArrayIndex = ( int32_t ) pvTimerGetTimerID( pxTimer );\n *\n *     // Increment the number of times that pxTimer has expired.\n *     lExpireCounters[ lArrayIndex ] += 1;\n *\n *     // If the timer has expired 10 times then stop it from running.\n *     if( lExpireCounters[ lArrayIndex ] == xMaxExpiryCountBeforeStopping )\n *     {\n *         // Do not use a block time if calling a timer API function from a\n *         // timer callback function, as doing so could cause a deadlock!\n *         xTimerStop( pxTimer, 0 );\n *     }\n * }\n *\n * void main( void )\n * {\n * int32_t x;\n *\n *     // Create then start some timers.  Starting the timers before the scheduler\n *     // has been started means the timers will start running immediately that\n *     // the scheduler starts.\n *     for( x = 0; x < NUM_TIMERS; x++ )\n *     {\n *         xTimers[ x ] = xTimerCreate(    \"Timer\",             // Just a text name, not used by the kernel.\n *                                         ( 100 * ( x + 1 ) ), // The timer period in ticks.\n *                                         pdTRUE,              // The timers will auto-reload themselves when they expire.\n *                                         ( void * ) x,        // Assign each timer a unique id equal to its array index.\n *                                         vTimerCallback       // Each timer calls the same callback when it expires.\n *                                     );\n *\n *         if( xTimers[ x ] == NULL )\n *         {\n *             // The timer was not created.\n *         }\n *         else\n *         {\n *             // Start the timer.  No block time is specified, and even if one was\n *             // it would be ignored because the scheduler has not yet been\n *             // started.\n *             if( xTimerStart( xTimers[ x ], 0 ) != pdPASS )\n *             {\n *                 // The timer could not be set into the Active state.\n *             }\n *         }\n *     }\n *\n *     // ...\n *     // Create tasks here.\n *     // ...\n *\n *     // Starting the scheduler will start the timers running as they have already\n *     // been set into the active state.\n *     vTaskStartScheduler();\n *\n *     // Should not reach here.\n *     for( ;; );\n * }\n * @endverbatim\n */\n#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n    TimerHandle_t xTimerCreate( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n                                const TickType_t xTimerPeriodInTicks,\n                                const BaseType_t xAutoReload,\n                                void * const pvTimerID,\n                                TimerCallbackFunction_t pxCallbackFunction ) PRIVILEGED_FUNCTION;\n#endif\n\n/**\n * TimerHandle_t xTimerCreateStatic(const char * const pcTimerName,\n *                                  TickType_t xTimerPeriodInTicks,\n *                                  BaseType_t xAutoReload,\n *                                  void * pvTimerID,\n *                                  TimerCallbackFunction_t pxCallbackFunction,\n *                                  StaticTimer_t *pxTimerBuffer );\n *\n * Creates a new software timer instance, and returns a handle by which the\n * created software timer can be referenced.\n *\n * Internally, within the FreeRTOS implementation, software timers use a block\n * of memory, in which the timer data structure is stored.  If a software timer\n * is created using xTimerCreate() then the required memory is automatically\n * dynamically allocated inside the xTimerCreate() function.  (see\n * https://www.FreeRTOS.org/a00111.html).  If a software timer is created using\n * xTimerCreateStatic() then the application writer must provide the memory that\n * will get used by the software timer.  xTimerCreateStatic() therefore allows a\n * software timer to be created without using any dynamic memory allocation.\n *\n * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),\n * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and\n * xTimerChangePeriodFromISR() API functions can all be used to transition a\n * timer into the active state.\n *\n * @param pcTimerName A text name that is assigned to the timer.  This is done\n * purely to assist debugging.  The kernel itself only ever references a timer\n * by its handle, and never by its name.\n *\n * @param xTimerPeriodInTicks The timer period.  The time is defined in tick\n * periods so the constant portTICK_PERIOD_MS can be used to convert a time that\n * has been specified in milliseconds.  For example, if the timer must expire\n * after 100 ticks, then xTimerPeriodInTicks should be set to 100.\n * Alternatively, if the timer must expire after 500ms, then xPeriod can be set\n * to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or\n * equal to 1000.  The timer period must be greater than 0.\n *\n * @param xAutoReload If xAutoReload is set to pdTRUE then the timer will\n * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter.\n * If xAutoReload is set to pdFALSE then the timer will be a one-shot timer and\n * enter the dormant state after it expires.\n *\n * @param pvTimerID An identifier that is assigned to the timer being created.\n * Typically this would be used in the timer callback function to identify which\n * timer expired when the same callback function is assigned to more than one\n * timer.\n *\n * @param pxCallbackFunction The function to call when the timer expires.\n * Callback functions must have the prototype defined by TimerCallbackFunction_t,\n * which is \"void vCallbackFunction( TimerHandle_t xTimer );\".\n *\n * @param pxTimerBuffer Must point to a variable of type StaticTimer_t, which\n * will be then be used to hold the software timer's data structures, removing\n * the need for the memory to be allocated dynamically.\n *\n * @return If the timer is created then a handle to the created timer is\n * returned.  If pxTimerBuffer was NULL then NULL is returned.\n *\n * Example usage:\n * @verbatim\n *\n * // The buffer used to hold the software timer's data structure.\n * static StaticTimer_t xTimerBuffer;\n *\n * // A variable that will be incremented by the software timer's callback\n * // function.\n * UBaseType_t uxVariableToIncrement = 0;\n *\n * // A software timer callback function that increments a variable passed to\n * // it when the software timer was created.  After the 5th increment the\n * // callback function stops the software timer.\n * static void prvTimerCallback( TimerHandle_t xExpiredTimer )\n * {\n * UBaseType_t *puxVariableToIncrement;\n * BaseType_t xReturned;\n *\n *     // Obtain the address of the variable to increment from the timer ID.\n *     puxVariableToIncrement = ( UBaseType_t * ) pvTimerGetTimerID( xExpiredTimer );\n *\n *     // Increment the variable to show the timer callback has executed.\n *     ( *puxVariableToIncrement )++;\n *\n *     // If this callback has executed the required number of times, stop the\n *     // timer.\n *     if( *puxVariableToIncrement == 5 )\n *     {\n *         // This is called from a timer callback so must not block.\n *         xTimerStop( xExpiredTimer, staticDONT_BLOCK );\n *     }\n * }\n *\n *\n * void main( void )\n * {\n *     // Create the software time.  xTimerCreateStatic() has an extra parameter\n *     // than the normal xTimerCreate() API function.  The parameter is a pointer\n *     // to the StaticTimer_t structure that will hold the software timer\n *     // structure.  If the parameter is passed as NULL then the structure will be\n *     // allocated dynamically, just as if xTimerCreate() had been called.\n *     xTimer = xTimerCreateStatic( \"T1\",             // Text name for the task.  Helps debugging only.  Not used by FreeRTOS.\n *                                  xTimerPeriod,     // The period of the timer in ticks.\n *                                  pdTRUE,           // This is an auto-reload timer.\n *                                  ( void * ) &uxVariableToIncrement,    // A variable incremented by the software timer's callback function\n *                                  prvTimerCallback, // The function to execute when the timer expires.\n *                                  &xTimerBuffer );  // The buffer that will hold the software timer structure.\n *\n *     // The scheduler has not started yet so a block time is not used.\n *     xReturned = xTimerStart( xTimer, 0 );\n *\n *     // ...\n *     // Create tasks here.\n *     // ...\n *\n *     // Starting the scheduler will start the timers running as they have already\n *     // been set into the active state.\n *     vTaskStartScheduler();\n *\n *     // Should not reach here.\n *     for( ;; );\n * }\n * @endverbatim\n */\n#if ( configSUPPORT_STATIC_ALLOCATION == 1 )\n    TimerHandle_t xTimerCreateStatic( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n                                      const TickType_t xTimerPeriodInTicks,\n                                      const BaseType_t xAutoReload,\n                                      void * const pvTimerID,\n                                      TimerCallbackFunction_t pxCallbackFunction,\n                                      StaticTimer_t * pxTimerBuffer ) PRIVILEGED_FUNCTION;\n#endif /* configSUPPORT_STATIC_ALLOCATION */\n\n/**\n * void *pvTimerGetTimerID( TimerHandle_t xTimer );\n *\n * Returns the ID assigned to the timer.\n *\n * IDs are assigned to timers using the pvTimerID parameter of the call to\n * xTimerCreated() that was used to create the timer, and by calling the\n * vTimerSetTimerID() API function.\n *\n * If the same callback function is assigned to multiple timers then the timer\n * ID can be used as time specific (timer local) storage.\n *\n * @param xTimer The timer being queried.\n *\n * @return The ID assigned to the timer being queried.\n *\n * Example usage:\n *\n * See the xTimerCreate() API function example usage scenario.\n */\nvoid * pvTimerGetTimerID( const TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;\n\n/**\n * void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID );\n *\n * Sets the ID assigned to the timer.\n *\n * IDs are assigned to timers using the pvTimerID parameter of the call to\n * xTimerCreated() that was used to create the timer.\n *\n * If the same callback function is assigned to multiple timers then the timer\n * ID can be used as time specific (timer local) storage.\n *\n * @param xTimer The timer being updated.\n *\n * @param pvNewID The ID to assign to the timer.\n *\n * Example usage:\n *\n * See the xTimerCreate() API function example usage scenario.\n */\nvoid vTimerSetTimerID( TimerHandle_t xTimer,\n                       void * pvNewID ) PRIVILEGED_FUNCTION;\n\n/**\n * BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer );\n *\n * Queries a timer to see if it is active or dormant.\n *\n * A timer will be dormant if:\n *     1) It has been created but not started, or\n *     2) It is an expired one-shot timer that has not been restarted.\n *\n * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),\n * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and\n * xTimerChangePeriodFromISR() API functions can all be used to transition a timer into the\n * active state.\n *\n * @param xTimer The timer being queried.\n *\n * @return pdFALSE will be returned if the timer is dormant.  A value other than\n * pdFALSE will be returned if the timer is active.\n *\n * Example usage:\n * @verbatim\n * // This function assumes xTimer has already been created.\n * void vAFunction( TimerHandle_t xTimer )\n * {\n *     if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently \"if( xTimerIsTimerActive( xTimer ) )\"\n *     {\n *         // xTimer is active, do something.\n *     }\n *     else\n *     {\n *         // xTimer is not active, do something else.\n *     }\n * }\n * @endverbatim\n */\nBaseType_t xTimerIsTimerActive( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;\n\n/**\n * TaskHandle_t xTimerGetTimerDaemonTaskHandle( void );\n *\n * Simply returns the handle of the timer service/daemon task.  It it not valid\n * to call xTimerGetTimerDaemonTaskHandle() before the scheduler has been started.\n */\nTaskHandle_t xTimerGetTimerDaemonTaskHandle( void ) PRIVILEGED_FUNCTION;\n\n/**\n * BaseType_t xTimerStart( TimerHandle_t xTimer, TickType_t xTicksToWait );\n *\n * Timer functionality is provided by a timer service/daemon task.  Many of the\n * public FreeRTOS timer API functions send commands to the timer service task\n * through a queue called the timer command queue.  The timer command queue is\n * private to the kernel itself and is not directly accessible to application\n * code.  The length of the timer command queue is set by the\n * configTIMER_QUEUE_LENGTH configuration constant.\n *\n * xTimerStart() starts a timer that was previously created using the\n * xTimerCreate() API function.  If the timer had already been started and was\n * already in the active state, then xTimerStart() has equivalent functionality\n * to the xTimerReset() API function.\n *\n * Starting a timer ensures the timer is in the active state.  If the timer\n * is not stopped, deleted, or reset in the mean time, the callback function\n * associated with the timer will get called 'n' ticks after xTimerStart() was\n * called, where 'n' is the timers defined period.\n *\n * It is valid to call xTimerStart() before the scheduler has been started, but\n * when this is done the timer will not actually start until the scheduler is\n * started, and the timers expiry time will be relative to when the scheduler is\n * started, not relative to when xTimerStart() was called.\n *\n * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStart()\n * to be available.\n *\n * @param xTimer The handle of the timer being started/restarted.\n *\n * @param xTicksToWait Specifies the time, in ticks, that the calling task should\n * be held in the Blocked state to wait for the start command to be successfully\n * sent to the timer command queue, should the queue already be full when\n * xTimerStart() was called.  xTicksToWait is ignored if xTimerStart() is called\n * before the scheduler is started.\n *\n * @return pdFAIL will be returned if the start command could not be sent to\n * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will\n * be returned if the command was successfully sent to the timer command queue.\n * When the command is actually processed will depend on the priority of the\n * timer service/daemon task relative to other tasks in the system, although the\n * timers expiry time is relative to when xTimerStart() is actually called.  The\n * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY\n * configuration constant.\n *\n * Example usage:\n *\n * See the xTimerCreate() API function example usage scenario.\n *\n */\n#define xTimerStart( xTimer, xTicksToWait ) \\\n    xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) )\n\n/**\n * BaseType_t xTimerStop( TimerHandle_t xTimer, TickType_t xTicksToWait );\n *\n * Timer functionality is provided by a timer service/daemon task.  Many of the\n * public FreeRTOS timer API functions send commands to the timer service task\n * through a queue called the timer command queue.  The timer command queue is\n * private to the kernel itself and is not directly accessible to application\n * code.  The length of the timer command queue is set by the\n * configTIMER_QUEUE_LENGTH configuration constant.\n *\n * xTimerStop() stops a timer that was previously started using either of the\n * The xTimerStart(), xTimerReset(), xTimerStartFromISR(), xTimerResetFromISR(),\n * xTimerChangePeriod() or xTimerChangePeriodFromISR() API functions.\n *\n * Stopping a timer ensures the timer is not in the active state.\n *\n * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStop()\n * to be available.\n *\n * @param xTimer The handle of the timer being stopped.\n *\n * @param xTicksToWait Specifies the time, in ticks, that the calling task should\n * be held in the Blocked state to wait for the stop command to be successfully\n * sent to the timer command queue, should the queue already be full when\n * xTimerStop() was called.  xTicksToWait is ignored if xTimerStop() is called\n * before the scheduler is started.\n *\n * @return pdFAIL will be returned if the stop command could not be sent to\n * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will\n * be returned if the command was successfully sent to the timer command queue.\n * When the command is actually processed will depend on the priority of the\n * timer service/daemon task relative to other tasks in the system.  The timer\n * service/daemon task priority is set by the configTIMER_TASK_PRIORITY\n * configuration constant.\n *\n * Example usage:\n *\n * See the xTimerCreate() API function example usage scenario.\n *\n */\n#define xTimerStop( xTimer, xTicksToWait ) \\\n    xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP, 0U, NULL, ( xTicksToWait ) )\n\n/**\n * BaseType_t xTimerChangePeriod(   TimerHandle_t xTimer,\n *                                  TickType_t xNewPeriod,\n *                                  TickType_t xTicksToWait );\n *\n * Timer functionality is provided by a timer service/daemon task.  Many of the\n * public FreeRTOS timer API functions send commands to the timer service task\n * through a queue called the timer command queue.  The timer command queue is\n * private to the kernel itself and is not directly accessible to application\n * code.  The length of the timer command queue is set by the\n * configTIMER_QUEUE_LENGTH configuration constant.\n *\n * xTimerChangePeriod() changes the period of a timer that was previously\n * created using the xTimerCreate() API function.\n *\n * xTimerChangePeriod() can be called to change the period of an active or\n * dormant state timer.\n *\n * The configUSE_TIMERS configuration constant must be set to 1 for\n * xTimerChangePeriod() to be available.\n *\n * @param xTimer The handle of the timer that is having its period changed.\n *\n * @param xNewPeriod The new period for xTimer. Timer periods are specified in\n * tick periods, so the constant portTICK_PERIOD_MS can be used to convert a time\n * that has been specified in milliseconds.  For example, if the timer must\n * expire after 100 ticks, then xNewPeriod should be set to 100.  Alternatively,\n * if the timer must expire after 500ms, then xNewPeriod can be set to\n * ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than\n * or equal to 1000.\n *\n * @param xTicksToWait Specifies the time, in ticks, that the calling task should\n * be held in the Blocked state to wait for the change period command to be\n * successfully sent to the timer command queue, should the queue already be\n * full when xTimerChangePeriod() was called.  xTicksToWait is ignored if\n * xTimerChangePeriod() is called before the scheduler is started.\n *\n * @return pdFAIL will be returned if the change period command could not be\n * sent to the timer command queue even after xTicksToWait ticks had passed.\n * pdPASS will be returned if the command was successfully sent to the timer\n * command queue.  When the command is actually processed will depend on the\n * priority of the timer service/daemon task relative to other tasks in the\n * system.  The timer service/daemon task priority is set by the\n * configTIMER_TASK_PRIORITY configuration constant.\n *\n * Example usage:\n * @verbatim\n * // This function assumes xTimer has already been created.  If the timer\n * // referenced by xTimer is already active when it is called, then the timer\n * // is deleted.  If the timer referenced by xTimer is not active when it is\n * // called, then the period of the timer is set to 500ms and the timer is\n * // started.\n * void vAFunction( TimerHandle_t xTimer )\n * {\n *     if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently \"if( xTimerIsTimerActive( xTimer ) )\"\n *     {\n *         // xTimer is already active - delete it.\n *         xTimerDelete( xTimer );\n *     }\n *     else\n *     {\n *         // xTimer is not active, change its period to 500ms.  This will also\n *         // cause the timer to start.  Block for a maximum of 100 ticks if the\n *         // change period command cannot immediately be sent to the timer\n *         // command queue.\n *         if( xTimerChangePeriod( xTimer, 500 / portTICK_PERIOD_MS, 100 ) == pdPASS )\n *         {\n *             // The command was successfully sent.\n *         }\n *         else\n *         {\n *             // The command could not be sent, even after waiting for 100 ticks\n *             // to pass.  Take appropriate action here.\n *         }\n *     }\n * }\n * @endverbatim\n */\n#define xTimerChangePeriod( xTimer, xNewPeriod, xTicksToWait ) \\\n    xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD, ( xNewPeriod ), NULL, ( xTicksToWait ) )\n\n/**\n * BaseType_t xTimerDelete( TimerHandle_t xTimer, TickType_t xTicksToWait );\n *\n * Timer functionality is provided by a timer service/daemon task.  Many of the\n * public FreeRTOS timer API functions send commands to the timer service task\n * through a queue called the timer command queue.  The timer command queue is\n * private to the kernel itself and is not directly accessible to application\n * code.  The length of the timer command queue is set by the\n * configTIMER_QUEUE_LENGTH configuration constant.\n *\n * xTimerDelete() deletes a timer that was previously created using the\n * xTimerCreate() API function.\n *\n * The configUSE_TIMERS configuration constant must be set to 1 for\n * xTimerDelete() to be available.\n *\n * @param xTimer The handle of the timer being deleted.\n *\n * @param xTicksToWait Specifies the time, in ticks, that the calling task should\n * be held in the Blocked state to wait for the delete command to be\n * successfully sent to the timer command queue, should the queue already be\n * full when xTimerDelete() was called.  xTicksToWait is ignored if xTimerDelete()\n * is called before the scheduler is started.\n *\n * @return pdFAIL will be returned if the delete command could not be sent to\n * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will\n * be returned if the command was successfully sent to the timer command queue.\n * When the command is actually processed will depend on the priority of the\n * timer service/daemon task relative to other tasks in the system.  The timer\n * service/daemon task priority is set by the configTIMER_TASK_PRIORITY\n * configuration constant.\n *\n * Example usage:\n *\n * See the xTimerChangePeriod() API function example usage scenario.\n */\n#define xTimerDelete( xTimer, xTicksToWait ) \\\n    xTimerGenericCommand( ( xTimer ), tmrCOMMAND_DELETE, 0U, NULL, ( xTicksToWait ) )\n\n/**\n * BaseType_t xTimerReset( TimerHandle_t xTimer, TickType_t xTicksToWait );\n *\n * Timer functionality is provided by a timer service/daemon task.  Many of the\n * public FreeRTOS timer API functions send commands to the timer service task\n * through a queue called the timer command queue.  The timer command queue is\n * private to the kernel itself and is not directly accessible to application\n * code.  The length of the timer command queue is set by the\n * configTIMER_QUEUE_LENGTH configuration constant.\n *\n * xTimerReset() re-starts a timer that was previously created using the\n * xTimerCreate() API function.  If the timer had already been started and was\n * already in the active state, then xTimerReset() will cause the timer to\n * re-evaluate its expiry time so that it is relative to when xTimerReset() was\n * called.  If the timer was in the dormant state then xTimerReset() has\n * equivalent functionality to the xTimerStart() API function.\n *\n * Resetting a timer ensures the timer is in the active state.  If the timer\n * is not stopped, deleted, or reset in the mean time, the callback function\n * associated with the timer will get called 'n' ticks after xTimerReset() was\n * called, where 'n' is the timers defined period.\n *\n * It is valid to call xTimerReset() before the scheduler has been started, but\n * when this is done the timer will not actually start until the scheduler is\n * started, and the timers expiry time will be relative to when the scheduler is\n * started, not relative to when xTimerReset() was called.\n *\n * The configUSE_TIMERS configuration constant must be set to 1 for xTimerReset()\n * to be available.\n *\n * @param xTimer The handle of the timer being reset/started/restarted.\n *\n * @param xTicksToWait Specifies the time, in ticks, that the calling task should\n * be held in the Blocked state to wait for the reset command to be successfully\n * sent to the timer command queue, should the queue already be full when\n * xTimerReset() was called.  xTicksToWait is ignored if xTimerReset() is called\n * before the scheduler is started.\n *\n * @return pdFAIL will be returned if the reset command could not be sent to\n * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will\n * be returned if the command was successfully sent to the timer command queue.\n * When the command is actually processed will depend on the priority of the\n * timer service/daemon task relative to other tasks in the system, although the\n * timers expiry time is relative to when xTimerStart() is actually called.  The\n * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY\n * configuration constant.\n *\n * Example usage:\n * @verbatim\n * // When a key is pressed, an LCD back-light is switched on.  If 5 seconds pass\n * // without a key being pressed, then the LCD back-light is switched off.  In\n * // this case, the timer is a one-shot timer.\n *\n * TimerHandle_t xBacklightTimer = NULL;\n *\n * // The callback function assigned to the one-shot timer.  In this case the\n * // parameter is not used.\n * void vBacklightTimerCallback( TimerHandle_t pxTimer )\n * {\n *     // The timer expired, therefore 5 seconds must have passed since a key\n *     // was pressed.  Switch off the LCD back-light.\n *     vSetBacklightState( BACKLIGHT_OFF );\n * }\n *\n * // The key press event handler.\n * void vKeyPressEventHandler( char cKey )\n * {\n *     // Ensure the LCD back-light is on, then reset the timer that is\n *     // responsible for turning the back-light off after 5 seconds of\n *     // key inactivity.  Wait 10 ticks for the command to be successfully sent\n *     // if it cannot be sent immediately.\n *     vSetBacklightState( BACKLIGHT_ON );\n *     if( xTimerReset( xBacklightTimer, 100 ) != pdPASS )\n *     {\n *         // The reset command was not executed successfully.  Take appropriate\n *         // action here.\n *     }\n *\n *     // Perform the rest of the key processing here.\n * }\n *\n * void main( void )\n * {\n * int32_t x;\n *\n *     // Create then start the one-shot timer that is responsible for turning\n *     // the back-light off if no keys are pressed within a 5 second period.\n *     xBacklightTimer = xTimerCreate( \"BacklightTimer\",           // Just a text name, not used by the kernel.\n *                                     ( 5000 / portTICK_PERIOD_MS), // The timer period in ticks.\n *                                     pdFALSE,                    // The timer is a one-shot timer.\n *                                     0,                          // The id is not used by the callback so can take any value.\n *                                     vBacklightTimerCallback     // The callback function that switches the LCD back-light off.\n *                                   );\n *\n *     if( xBacklightTimer == NULL )\n *     {\n *         // The timer was not created.\n *     }\n *     else\n *     {\n *         // Start the timer.  No block time is specified, and even if one was\n *         // it would be ignored because the scheduler has not yet been\n *         // started.\n *         if( xTimerStart( xBacklightTimer, 0 ) != pdPASS )\n *         {\n *             // The timer could not be set into the Active state.\n *         }\n *     }\n *\n *     // ...\n *     // Create tasks here.\n *     // ...\n *\n *     // Starting the scheduler will start the timer running as it has already\n *     // been set into the active state.\n *     vTaskStartScheduler();\n *\n *     // Should not reach here.\n *     for( ;; );\n * }\n * @endverbatim\n */\n#define xTimerReset( xTimer, xTicksToWait ) \\\n    xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) )\n\n/**\n * BaseType_t xTimerStartFromISR(   TimerHandle_t xTimer,\n *                                  BaseType_t *pxHigherPriorityTaskWoken );\n *\n * A version of xTimerStart() that can be called from an interrupt service\n * routine.\n *\n * @param xTimer The handle of the timer being started/restarted.\n *\n * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most\n * of its time in the Blocked state, waiting for messages to arrive on the timer\n * command queue.  Calling xTimerStartFromISR() writes a message to the timer\n * command queue, so has the potential to transition the timer service/daemon\n * task out of the Blocked state.  If calling xTimerStartFromISR() causes the\n * timer service/daemon task to leave the Blocked state, and the timer service/\n * daemon task has a priority equal to or greater than the currently executing\n * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will\n * get set to pdTRUE internally within the xTimerStartFromISR() function.  If\n * xTimerStartFromISR() sets this value to pdTRUE then a context switch should\n * be performed before the interrupt exits.\n *\n * @return pdFAIL will be returned if the start command could not be sent to\n * the timer command queue.  pdPASS will be returned if the command was\n * successfully sent to the timer command queue.  When the command is actually\n * processed will depend on the priority of the timer service/daemon task\n * relative to other tasks in the system, although the timers expiry time is\n * relative to when xTimerStartFromISR() is actually called.  The timer\n * service/daemon task priority is set by the configTIMER_TASK_PRIORITY\n * configuration constant.\n *\n * Example usage:\n * @verbatim\n * // This scenario assumes xBacklightTimer has already been created.  When a\n * // key is pressed, an LCD back-light is switched on.  If 5 seconds pass\n * // without a key being pressed, then the LCD back-light is switched off.  In\n * // this case, the timer is a one-shot timer, and unlike the example given for\n * // the xTimerReset() function, the key press event handler is an interrupt\n * // service routine.\n *\n * // The callback function assigned to the one-shot timer.  In this case the\n * // parameter is not used.\n * void vBacklightTimerCallback( TimerHandle_t pxTimer )\n * {\n *     // The timer expired, therefore 5 seconds must have passed since a key\n *     // was pressed.  Switch off the LCD back-light.\n *     vSetBacklightState( BACKLIGHT_OFF );\n * }\n *\n * // The key press interrupt service routine.\n * void vKeyPressEventInterruptHandler( void )\n * {\n * BaseType_t xHigherPriorityTaskWoken = pdFALSE;\n *\n *     // Ensure the LCD back-light is on, then restart the timer that is\n *     // responsible for turning the back-light off after 5 seconds of\n *     // key inactivity.  This is an interrupt service routine so can only\n *     // call FreeRTOS API functions that end in \"FromISR\".\n *     vSetBacklightState( BACKLIGHT_ON );\n *\n *     // xTimerStartFromISR() or xTimerResetFromISR() could be called here\n *     // as both cause the timer to re-calculate its expiry time.\n *     // xHigherPriorityTaskWoken was initialised to pdFALSE when it was\n *     // declared (in this function).\n *     if( xTimerStartFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS )\n *     {\n *         // The start command was not executed successfully.  Take appropriate\n *         // action here.\n *     }\n *\n *     // Perform the rest of the key processing here.\n *\n *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch\n *     // should be performed.  The syntax required to perform a context switch\n *     // from inside an ISR varies from port to port, and from compiler to\n *     // compiler.  Inspect the demos for the port you are using to find the\n *     // actual syntax required.\n *     if( xHigherPriorityTaskWoken != pdFALSE )\n *     {\n *         // Call the interrupt safe yield function here (actual function\n *         // depends on the FreeRTOS port being used).\n *     }\n * }\n * @endverbatim\n */\n#define xTimerStartFromISR( xTimer, pxHigherPriorityTaskWoken ) \\\n    xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U )\n\n/**\n * BaseType_t xTimerStopFromISR(    TimerHandle_t xTimer,\n *                                  BaseType_t *pxHigherPriorityTaskWoken );\n *\n * A version of xTimerStop() that can be called from an interrupt service\n * routine.\n *\n * @param xTimer The handle of the timer being stopped.\n *\n * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most\n * of its time in the Blocked state, waiting for messages to arrive on the timer\n * command queue.  Calling xTimerStopFromISR() writes a message to the timer\n * command queue, so has the potential to transition the timer service/daemon\n * task out of the Blocked state.  If calling xTimerStopFromISR() causes the\n * timer service/daemon task to leave the Blocked state, and the timer service/\n * daemon task has a priority equal to or greater than the currently executing\n * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will\n * get set to pdTRUE internally within the xTimerStopFromISR() function.  If\n * xTimerStopFromISR() sets this value to pdTRUE then a context switch should\n * be performed before the interrupt exits.\n *\n * @return pdFAIL will be returned if the stop command could not be sent to\n * the timer command queue.  pdPASS will be returned if the command was\n * successfully sent to the timer command queue.  When the command is actually\n * processed will depend on the priority of the timer service/daemon task\n * relative to other tasks in the system.  The timer service/daemon task\n * priority is set by the configTIMER_TASK_PRIORITY configuration constant.\n *\n * Example usage:\n * @verbatim\n * // This scenario assumes xTimer has already been created and started.  When\n * // an interrupt occurs, the timer should be simply stopped.\n *\n * // The interrupt service routine that stops the timer.\n * void vAnExampleInterruptServiceRoutine( void )\n * {\n * BaseType_t xHigherPriorityTaskWoken = pdFALSE;\n *\n *     // The interrupt has occurred - simply stop the timer.\n *     // xHigherPriorityTaskWoken was set to pdFALSE where it was defined\n *     // (within this function).  As this is an interrupt service routine, only\n *     // FreeRTOS API functions that end in \"FromISR\" can be used.\n *     if( xTimerStopFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS )\n *     {\n *         // The stop command was not executed successfully.  Take appropriate\n *         // action here.\n *     }\n *\n *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch\n *     // should be performed.  The syntax required to perform a context switch\n *     // from inside an ISR varies from port to port, and from compiler to\n *     // compiler.  Inspect the demos for the port you are using to find the\n *     // actual syntax required.\n *     if( xHigherPriorityTaskWoken != pdFALSE )\n *     {\n *         // Call the interrupt safe yield function here (actual function\n *         // depends on the FreeRTOS port being used).\n *     }\n * }\n * @endverbatim\n */\n#define xTimerStopFromISR( xTimer, pxHigherPriorityTaskWoken ) \\\n    xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP_FROM_ISR, 0, ( pxHigherPriorityTaskWoken ), 0U )\n\n/**\n * BaseType_t xTimerChangePeriodFromISR( TimerHandle_t xTimer,\n *                                       TickType_t xNewPeriod,\n *                                       BaseType_t *pxHigherPriorityTaskWoken );\n *\n * A version of xTimerChangePeriod() that can be called from an interrupt\n * service routine.\n *\n * @param xTimer The handle of the timer that is having its period changed.\n *\n * @param xNewPeriod The new period for xTimer. Timer periods are specified in\n * tick periods, so the constant portTICK_PERIOD_MS can be used to convert a time\n * that has been specified in milliseconds.  For example, if the timer must\n * expire after 100 ticks, then xNewPeriod should be set to 100.  Alternatively,\n * if the timer must expire after 500ms, then xNewPeriod can be set to\n * ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than\n * or equal to 1000.\n *\n * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most\n * of its time in the Blocked state, waiting for messages to arrive on the timer\n * command queue.  Calling xTimerChangePeriodFromISR() writes a message to the\n * timer command queue, so has the potential to transition the timer service/\n * daemon task out of the Blocked state.  If calling xTimerChangePeriodFromISR()\n * causes the timer service/daemon task to leave the Blocked state, and the\n * timer service/daemon task has a priority equal to or greater than the\n * currently executing task (the task that was interrupted), then\n * *pxHigherPriorityTaskWoken will get set to pdTRUE internally within the\n * xTimerChangePeriodFromISR() function.  If xTimerChangePeriodFromISR() sets\n * this value to pdTRUE then a context switch should be performed before the\n * interrupt exits.\n *\n * @return pdFAIL will be returned if the command to change the timers period\n * could not be sent to the timer command queue.  pdPASS will be returned if the\n * command was successfully sent to the timer command queue.  When the command\n * is actually processed will depend on the priority of the timer service/daemon\n * task relative to other tasks in the system.  The timer service/daemon task\n * priority is set by the configTIMER_TASK_PRIORITY configuration constant.\n *\n * Example usage:\n * @verbatim\n * // This scenario assumes xTimer has already been created and started.  When\n * // an interrupt occurs, the period of xTimer should be changed to 500ms.\n *\n * // The interrupt service routine that changes the period of xTimer.\n * void vAnExampleInterruptServiceRoutine( void )\n * {\n * BaseType_t xHigherPriorityTaskWoken = pdFALSE;\n *\n *     // The interrupt has occurred - change the period of xTimer to 500ms.\n *     // xHigherPriorityTaskWoken was set to pdFALSE where it was defined\n *     // (within this function).  As this is an interrupt service routine, only\n *     // FreeRTOS API functions that end in \"FromISR\" can be used.\n *     if( xTimerChangePeriodFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS )\n *     {\n *         // The command to change the timers period was not executed\n *         // successfully.  Take appropriate action here.\n *     }\n *\n *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch\n *     // should be performed.  The syntax required to perform a context switch\n *     // from inside an ISR varies from port to port, and from compiler to\n *     // compiler.  Inspect the demos for the port you are using to find the\n *     // actual syntax required.\n *     if( xHigherPriorityTaskWoken != pdFALSE )\n *     {\n *         // Call the interrupt safe yield function here (actual function\n *         // depends on the FreeRTOS port being used).\n *     }\n * }\n * @endverbatim\n */\n#define xTimerChangePeriodFromISR( xTimer, xNewPeriod, pxHigherPriorityTaskWoken ) \\\n    xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD_FROM_ISR, ( xNewPeriod ), ( pxHigherPriorityTaskWoken ), 0U )\n\n/**\n * BaseType_t xTimerResetFromISR(   TimerHandle_t xTimer,\n *                                  BaseType_t *pxHigherPriorityTaskWoken );\n *\n * A version of xTimerReset() that can be called from an interrupt service\n * routine.\n *\n * @param xTimer The handle of the timer that is to be started, reset, or\n * restarted.\n *\n * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most\n * of its time in the Blocked state, waiting for messages to arrive on the timer\n * command queue.  Calling xTimerResetFromISR() writes a message to the timer\n * command queue, so has the potential to transition the timer service/daemon\n * task out of the Blocked state.  If calling xTimerResetFromISR() causes the\n * timer service/daemon task to leave the Blocked state, and the timer service/\n * daemon task has a priority equal to or greater than the currently executing\n * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will\n * get set to pdTRUE internally within the xTimerResetFromISR() function.  If\n * xTimerResetFromISR() sets this value to pdTRUE then a context switch should\n * be performed before the interrupt exits.\n *\n * @return pdFAIL will be returned if the reset command could not be sent to\n * the timer command queue.  pdPASS will be returned if the command was\n * successfully sent to the timer command queue.  When the command is actually\n * processed will depend on the priority of the timer service/daemon task\n * relative to other tasks in the system, although the timers expiry time is\n * relative to when xTimerResetFromISR() is actually called.  The timer service/daemon\n * task priority is set by the configTIMER_TASK_PRIORITY configuration constant.\n *\n * Example usage:\n * @verbatim\n * // This scenario assumes xBacklightTimer has already been created.  When a\n * // key is pressed, an LCD back-light is switched on.  If 5 seconds pass\n * // without a key being pressed, then the LCD back-light is switched off.  In\n * // this case, the timer is a one-shot timer, and unlike the example given for\n * // the xTimerReset() function, the key press event handler is an interrupt\n * // service routine.\n *\n * // The callback function assigned to the one-shot timer.  In this case the\n * // parameter is not used.\n * void vBacklightTimerCallback( TimerHandle_t pxTimer )\n * {\n *     // The timer expired, therefore 5 seconds must have passed since a key\n *     // was pressed.  Switch off the LCD back-light.\n *     vSetBacklightState( BACKLIGHT_OFF );\n * }\n *\n * // The key press interrupt service routine.\n * void vKeyPressEventInterruptHandler( void )\n * {\n * BaseType_t xHigherPriorityTaskWoken = pdFALSE;\n *\n *     // Ensure the LCD back-light is on, then reset the timer that is\n *     // responsible for turning the back-light off after 5 seconds of\n *     // key inactivity.  This is an interrupt service routine so can only\n *     // call FreeRTOS API functions that end in \"FromISR\".\n *     vSetBacklightState( BACKLIGHT_ON );\n *\n *     // xTimerStartFromISR() or xTimerResetFromISR() could be called here\n *     // as both cause the timer to re-calculate its expiry time.\n *     // xHigherPriorityTaskWoken was initialised to pdFALSE when it was\n *     // declared (in this function).\n *     if( xTimerResetFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS )\n *     {\n *         // The reset command was not executed successfully.  Take appropriate\n *         // action here.\n *     }\n *\n *     // Perform the rest of the key processing here.\n *\n *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch\n *     // should be performed.  The syntax required to perform a context switch\n *     // from inside an ISR varies from port to port, and from compiler to\n *     // compiler.  Inspect the demos for the port you are using to find the\n *     // actual syntax required.\n *     if( xHigherPriorityTaskWoken != pdFALSE )\n *     {\n *         // Call the interrupt safe yield function here (actual function\n *         // depends on the FreeRTOS port being used).\n *     }\n * }\n * @endverbatim\n */\n#define xTimerResetFromISR( xTimer, pxHigherPriorityTaskWoken ) \\\n    xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U )\n\n\n/**\n * BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend,\n *                                          void *pvParameter1,\n *                                          uint32_t ulParameter2,\n *                                          BaseType_t *pxHigherPriorityTaskWoken );\n *\n *\n * Used from application interrupt service routines to defer the execution of a\n * function to the RTOS daemon task (the timer service task, hence this function\n * is implemented in timers.c and is prefixed with 'Timer').\n *\n * Ideally an interrupt service routine (ISR) is kept as short as possible, but\n * sometimes an ISR either has a lot of processing to do, or needs to perform\n * processing that is not deterministic.  In these cases\n * xTimerPendFunctionCallFromISR() can be used to defer processing of a function\n * to the RTOS daemon task.\n *\n * A mechanism is provided that allows the interrupt to return directly to the\n * task that will subsequently execute the pended callback function.  This\n * allows the callback function to execute contiguously in time with the\n * interrupt - just as if the callback had executed in the interrupt itself.\n *\n * @param xFunctionToPend The function to execute from the timer service/\n * daemon task.  The function must conform to the PendedFunction_t\n * prototype.\n *\n * @param pvParameter1 The value of the callback function's first parameter.\n * The parameter has a void * type to allow it to be used to pass any type.\n * For example, unsigned longs can be cast to a void *, or the void * can be\n * used to point to a structure.\n *\n * @param ulParameter2 The value of the callback function's second parameter.\n *\n * @param pxHigherPriorityTaskWoken As mentioned above, calling this function\n * will result in a message being sent to the timer daemon task.  If the\n * priority of the timer daemon task (which is set using\n * configTIMER_TASK_PRIORITY in FreeRTOSConfig.h) is higher than the priority of\n * the currently running task (the task the interrupt interrupted) then\n * *pxHigherPriorityTaskWoken will be set to pdTRUE within\n * xTimerPendFunctionCallFromISR(), indicating that a context switch should be\n * requested before the interrupt exits.  For that reason\n * *pxHigherPriorityTaskWoken must be initialised to pdFALSE.  See the\n * example code below.\n *\n * @return pdPASS is returned if the message was successfully sent to the\n * timer daemon task, otherwise pdFALSE is returned.\n *\n * Example usage:\n * @verbatim\n *\n *  // The callback function that will execute in the context of the daemon task.\n *  // Note callback functions must all use this same prototype.\n *  void vProcessInterface( void *pvParameter1, uint32_t ulParameter2 )\n *  {\n *      BaseType_t xInterfaceToService;\n *\n *      // The interface that requires servicing is passed in the second\n *      // parameter.  The first parameter is not used in this case.\n *      xInterfaceToService = ( BaseType_t ) ulParameter2;\n *\n *      // ...Perform the processing here...\n *  }\n *\n *  // An ISR that receives data packets from multiple interfaces\n *  void vAnISR( void )\n *  {\n *      BaseType_t xInterfaceToService, xHigherPriorityTaskWoken;\n *\n *      // Query the hardware to determine which interface needs processing.\n *      xInterfaceToService = prvCheckInterfaces();\n *\n *      // The actual processing is to be deferred to a task.  Request the\n *      // vProcessInterface() callback function is executed, passing in the\n *      // number of the interface that needs processing.  The interface to\n *      // service is passed in the second parameter.  The first parameter is\n *      // not used in this case.\n *      xHigherPriorityTaskWoken = pdFALSE;\n *      xTimerPendFunctionCallFromISR( vProcessInterface, NULL, ( uint32_t ) xInterfaceToService, &xHigherPriorityTaskWoken );\n *\n *      // If xHigherPriorityTaskWoken is now set to pdTRUE then a context\n *      // switch should be requested.  The macro used is port specific and will\n *      // be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() - refer to\n *      // the documentation page for the port being used.\n *      portYIELD_FROM_ISR( xHigherPriorityTaskWoken );\n *\n *  }\n * @endverbatim\n */\nBaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend,\n                                          void * pvParameter1,\n                                          uint32_t ulParameter2,\n                                          BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;\n\n/**\n * BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend,\n *                                    void *pvParameter1,\n *                                    uint32_t ulParameter2,\n *                                    TickType_t xTicksToWait );\n *\n *\n * Used to defer the execution of a function to the RTOS daemon task (the timer\n * service task, hence this function is implemented in timers.c and is prefixed\n * with 'Timer').\n *\n * @param xFunctionToPend The function to execute from the timer service/\n * daemon task.  The function must conform to the PendedFunction_t\n * prototype.\n *\n * @param pvParameter1 The value of the callback function's first parameter.\n * The parameter has a void * type to allow it to be used to pass any type.\n * For example, unsigned longs can be cast to a void *, or the void * can be\n * used to point to a structure.\n *\n * @param ulParameter2 The value of the callback function's second parameter.\n *\n * @param xTicksToWait Calling this function will result in a message being\n * sent to the timer daemon task on a queue.  xTicksToWait is the amount of\n * time the calling task should remain in the Blocked state (so not using any\n * processing time) for space to become available on the timer queue if the\n * queue is found to be full.\n *\n * @return pdPASS is returned if the message was successfully sent to the\n * timer daemon task, otherwise pdFALSE is returned.\n *\n */\nBaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend,\n                                   void * pvParameter1,\n                                   uint32_t ulParameter2,\n                                   TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;\n\n/**\n * const char * const pcTimerGetName( TimerHandle_t xTimer );\n *\n * Returns the name that was assigned to a timer when the timer was created.\n *\n * @param xTimer The handle of the timer being queried.\n *\n * @return The name assigned to the timer specified by the xTimer parameter.\n */\nconst char * pcTimerGetName( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n\n/**\n * void vTimerSetReloadMode( TimerHandle_t xTimer, const BaseType_t xAutoReload );\n *\n * Updates a timer to be either an auto-reload timer, in which case the timer\n * automatically resets itself each time it expires, or a one-shot timer, in\n * which case the timer will only expire once unless it is manually restarted.\n *\n * @param xTimer The handle of the timer being updated.\n *\n * @param xAutoReload If xAutoReload is set to pdTRUE then the timer will\n * expire repeatedly with a frequency set by the timer's period (see the\n * xTimerPeriodInTicks parameter of the xTimerCreate() API function).  If\n * xAutoReload is set to pdFALSE then the timer will be a one-shot timer and\n * enter the dormant state after it expires.\n */\nvoid vTimerSetReloadMode( TimerHandle_t xTimer,\n                          const BaseType_t xAutoReload ) PRIVILEGED_FUNCTION;\n\n/**\n * BaseType_t xTimerGetReloadMode( TimerHandle_t xTimer );\n *\n * Queries a timer to determine if it is an auto-reload timer, in which case the timer\n * automatically resets itself each time it expires, or a one-shot timer, in\n * which case the timer will only expire once unless it is manually restarted.\n *\n * @param xTimer The handle of the timer being queried.\n *\n * @return If the timer is an auto-reload timer then pdTRUE is returned, otherwise\n * pdFALSE is returned.\n */\nBaseType_t xTimerGetReloadMode( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;\n\n/**\n * UBaseType_t uxTimerGetReloadMode( TimerHandle_t xTimer );\n *\n * Queries a timer to determine if it is an auto-reload timer, in which case the timer\n * automatically resets itself each time it expires, or a one-shot timer, in\n * which case the timer will only expire once unless it is manually restarted.\n *\n * @param xTimer The handle of the timer being queried.\n *\n * @return If the timer is an auto-reload timer then pdTRUE is returned, otherwise\n * pdFALSE is returned.\n */\nUBaseType_t uxTimerGetReloadMode( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;\n\n/**\n * TickType_t xTimerGetPeriod( TimerHandle_t xTimer );\n *\n * Returns the period of a timer.\n *\n * @param xTimer The handle of the timer being queried.\n *\n * @return The period of the timer in ticks.\n */\nTickType_t xTimerGetPeriod( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;\n\n/**\n * TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer );\n *\n * Returns the time in ticks at which the timer will expire.  If this is less\n * than the current tick count then the expiry time has overflowed from the\n * current time.\n *\n * @param xTimer The handle of the timer being queried.\n *\n * @return If the timer is running then the time in ticks at which the timer\n * will next expire is returned.  If the timer is not running then the return\n * value is undefined.\n */\nTickType_t xTimerGetExpiryTime( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;\n\n/*\n * Functions beyond this part are not part of the public API and are intended\n * for use by the kernel only.\n */\nBaseType_t xTimerCreateTimerTask( void ) PRIVILEGED_FUNCTION;\nBaseType_t xTimerGenericCommand( TimerHandle_t xTimer,\n                                 const BaseType_t xCommandID,\n                                 const TickType_t xOptionalValue,\n                                 BaseType_t * const pxHigherPriorityTaskWoken,\n                                 const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;\n\n#if ( configUSE_TRACE_FACILITY == 1 )\n    void vTimerSetTimerNumber( TimerHandle_t xTimer,\n                               UBaseType_t uxTimerNumber ) PRIVILEGED_FUNCTION;\n    UBaseType_t uxTimerGetTimerNumber( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;\n#endif\n\n#if ( configSUPPORT_STATIC_ALLOCATION == 1 )\n\n/**\n * task.h\n * @code{c}\n * void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer, StackType_t ** ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize )\n * @endcode\n *\n * This function is used to provide a statically allocated block of memory to FreeRTOS to hold the Timer Task TCB.  This function is required when\n * configSUPPORT_STATIC_ALLOCATION is set.  For more information see this URI: https://www.FreeRTOS.org/a00110.html#configSUPPORT_STATIC_ALLOCATION\n *\n * @param ppxTimerTaskTCBBuffer   A handle to a statically allocated TCB buffer\n * @param ppxTimerTaskStackBuffer A handle to a statically allocated Stack buffer for the idle task\n * @param pulTimerTaskStackSize   A pointer to the number of elements that will fit in the allocated stack buffer\n */\n    void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer,\n                                         StackType_t ** ppxTimerTaskStackBuffer,\n                                         uint32_t * pulTimerTaskStackSize );\n\n#endif\n\n/* *INDENT-OFF* */\n#ifdef __cplusplus\n    }\n#endif\n/* *INDENT-ON* */\n#endif /* TIMERS_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/list.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n\n#include <stdlib.h>\n\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\n * all the API functions to use the MPU wrappers.  That should only be done when\n * task.h is included from an application file. */\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n#include \"FreeRTOS.h\"\n#include \"list.h\"\n\n/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified\n * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be\n * defined for the header files above, but not in this file, in order to\n * generate the correct privileged Vs unprivileged linkage and placement. */\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */\n\n/*-----------------------------------------------------------\n* PUBLIC LIST API documented in list.h\n*----------------------------------------------------------*/\n\nvoid vListInitialise( List_t * const pxList )\n{\n    /* The list structure contains a list item which is used to mark the\n     * end of the list.  To initialise the list the list end is inserted\n     * as the only list entry. */\n    pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */\n\n    listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( &( pxList->xListEnd ) );\n\n    /* The list end value is the highest possible value in the list to\n     * ensure it remains at the end of the list. */\n    pxList->xListEnd.xItemValue = portMAX_DELAY;\n\n    /* The list end next and previous pointers point to itself so we know\n     * when the list is empty. */\n    pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd );     /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */\n    pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */\n\n    /* Initialize the remaining fields of xListEnd when it is a proper ListItem_t */\n    #if ( configUSE_MINI_LIST_ITEM == 0 )\n    {\n        pxList->xListEnd.pvOwner = NULL;\n        pxList->xListEnd.pxContainer = NULL;\n        listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( &( pxList->xListEnd ) );\n    }\n    #endif\n\n    pxList->uxNumberOfItems = ( UBaseType_t ) 0U;\n\n    /* Write known values into the list if\n     * configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */\n    listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList );\n    listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList );\n}\n/*-----------------------------------------------------------*/\n\nvoid vListInitialiseItem( ListItem_t * const pxItem )\n{\n    /* Make sure the list item is not recorded as being on a list. */\n    pxItem->pxContainer = NULL;\n\n    /* Write known values into the list item if\n     * configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */\n    listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );\n    listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );\n}\n/*-----------------------------------------------------------*/\n\nvoid vListInsertEnd( List_t * const pxList,\n                     ListItem_t * const pxNewListItem )\n{\n    ListItem_t * const pxIndex = pxList->pxIndex;\n\n    /* Only effective when configASSERT() is also defined, these tests may catch\n     * the list data structures being overwritten in memory.  They will not catch\n     * data errors caused by incorrect configuration or use of FreeRTOS. */\n    listTEST_LIST_INTEGRITY( pxList );\n    listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );\n\n    /* Insert a new list item into pxList, but rather than sort the list,\n     * makes the new list item the last item to be removed by a call to\n     * listGET_OWNER_OF_NEXT_ENTRY(). */\n    pxNewListItem->pxNext = pxIndex;\n    pxNewListItem->pxPrevious = pxIndex->pxPrevious;\n\n    /* Only used during decision coverage testing. */\n    mtCOVERAGE_TEST_DELAY();\n\n    pxIndex->pxPrevious->pxNext = pxNewListItem;\n    pxIndex->pxPrevious = pxNewListItem;\n\n    /* Remember which list the item is in. */\n    pxNewListItem->pxContainer = pxList;\n\n    ( pxList->uxNumberOfItems )++;\n}\n/*-----------------------------------------------------------*/\n\nvoid vListInsert( List_t * const pxList,\n                  ListItem_t * const pxNewListItem )\n{\n    ListItem_t * pxIterator;\n    const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;\n\n    /* Only effective when configASSERT() is also defined, these tests may catch\n     * the list data structures being overwritten in memory.  They will not catch\n     * data errors caused by incorrect configuration or use of FreeRTOS. */\n    listTEST_LIST_INTEGRITY( pxList );\n    listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );\n\n    /* Insert the new list item into the list, sorted in xItemValue order.\n     *\n     * If the list already contains a list item with the same item value then the\n     * new list item should be placed after it.  This ensures that TCBs which are\n     * stored in ready lists (all of which have the same xItemValue value) get a\n     * share of the CPU.  However, if the xItemValue is the same as the back marker\n     * the iteration loop below will not end.  Therefore the value is checked\n     * first, and the algorithm slightly modified if necessary. */\n    if( xValueOfInsertion == portMAX_DELAY )\n    {\n        pxIterator = pxList->xListEnd.pxPrevious;\n    }\n    else\n    {\n        /* *** NOTE ***********************************************************\n        *  If you find your application is crashing here then likely causes are\n        *  listed below.  In addition see https://www.FreeRTOS.org/FAQHelp.html for\n        *  more tips, and ensure configASSERT() is defined!\n        *  https://www.FreeRTOS.org/a00110.html#configASSERT\n        *\n        *   1) Stack overflow -\n        *      see https://www.FreeRTOS.org/Stacks-and-stack-overflow-checking.html\n        *   2) Incorrect interrupt priority assignment, especially on Cortex-M\n        *      parts where numerically high priority values denote low actual\n        *      interrupt priorities, which can seem counter intuitive.  See\n        *      https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html and the definition\n        *      of configMAX_SYSCALL_INTERRUPT_PRIORITY on\n        *      https://www.FreeRTOS.org/a00110.html\n        *   3) Calling an API function from within a critical section or when\n        *      the scheduler is suspended, or calling an API function that does\n        *      not end in \"FromISR\" from an interrupt.\n        *   4) Using a queue or semaphore before it has been initialised or\n        *      before the scheduler has been started (are interrupts firing\n        *      before vTaskStartScheduler() has been called?).\n        *   5) If the FreeRTOS port supports interrupt nesting then ensure that\n        *      the priority of the tick interrupt is at or below\n        *      configMAX_SYSCALL_INTERRUPT_PRIORITY.\n        **********************************************************************/\n\n        for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */\n        {\n            /* There is nothing to do here, just iterating to the wanted\n             * insertion position. */\n        }\n    }\n\n    pxNewListItem->pxNext = pxIterator->pxNext;\n    pxNewListItem->pxNext->pxPrevious = pxNewListItem;\n    pxNewListItem->pxPrevious = pxIterator;\n    pxIterator->pxNext = pxNewListItem;\n\n    /* Remember which list the item is in.  This allows fast removal of the\n     * item later. */\n    pxNewListItem->pxContainer = pxList;\n\n    ( pxList->uxNumberOfItems )++;\n}\n/*-----------------------------------------------------------*/\n\nUBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )\n{\n/* The list item knows which list it is in.  Obtain the list from the list\n * item. */\n    List_t * const pxList = pxItemToRemove->pxContainer;\n\n    pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;\n    pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;\n\n    /* Only used during decision coverage testing. */\n    mtCOVERAGE_TEST_DELAY();\n\n    /* Make sure the index is left pointing to a valid item. */\n    if( pxList->pxIndex == pxItemToRemove )\n    {\n        pxList->pxIndex = pxItemToRemove->pxPrevious;\n    }\n    else\n    {\n        mtCOVERAGE_TEST_MARKER();\n    }\n\n    pxItemToRemove->pxContainer = NULL;\n    ( pxList->uxNumberOfItems )--;\n\n    return pxList->uxNumberOfItems;\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/manifest.yml",
    "content": "name : \"FreeRTOS-Kernel\"\nversion: \"v10.5.1\"\ndescription: \"FreeRTOS Kernel.\"\nlicense: \"MIT\"\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/ARMClang/Use-the-GCC-ports.txt",
    "content": "The FreeRTOS GCC port layer also builds and works with the ARMClang compiler.\nTo use the ARMClang compiler build the port files from FreeRTOS/Source/portable/GCC."
  },
  {
    "path": "FreeRTOS-comparison/portable/ARMv8M/ReadMe.txt",
    "content": "This directory tree contains the master copy of the FreeeRTOS Armv8-M and\nArmv8.1-M ports.\nDo not use the files located here!  These file are copied into separate\nFreeRTOS/Source/portable/[compiler]/ARM_CM[23|33|55|85]_NNN directories prior to each\nFreeRTOS release.\n\nIf your Armv8-M and Armv8.1-M application uses TrustZone then use the files from the\nFreeRTOS/Source/portable/[compiler]/ARM_CM[23|33|55|85] directories.\n\nIf your Armv8-M and Armv8.1-M application does not use TrustZone then use the files from\nthe FreeRTOS/Source/portable/[compiler]/ARM_CM[23|33|55|85]_NTZ directories.\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/ARMv8M/copy_files.py",
    "content": "#/*\n# * FreeRTOS Kernel V10.5.1\n# * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n# *\n# * SPDX-License-Identifier: MIT\n# *\n# * Permission is hereby granted, free of charge, to any person obtaining a copy of\n# * this software and associated documentation files (the \"Software\"), to deal in\n# * the Software without restriction, including without limitation the rights to\n# * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n# * the Software, and to permit persons to whom the Software is furnished to do so,\n# * subject to the following conditions:\n# *\n# * The above copyright notice and this permission notice shall be included in all\n# * copies or substantial portions of the Software.\n# *\n# * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n# * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n# * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n# * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n# * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n# * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n# *\n# * https://www.FreeRTOS.org\n# * https://github.com/FreeRTOS\n# *\n# */\n\nimport os\nimport shutil\n\n_THIS_FILE_DIRECTORY_ = os.path.dirname(os.path.realpath(__file__))\n_FREERTOS_PORTABLE_DIRECTORY_ = os.path.dirname(_THIS_FILE_DIRECTORY_)\n\n_COMPILERS_ = ['GCC', 'IAR']\n_ARCH_NS_ = ['ARM_CM85', 'ARM_CM85_NTZ', 'ARM_CM55', 'ARM_CM55_NTZ', 'ARM_CM33', 'ARM_CM33_NTZ', 'ARM_CM23', 'ARM_CM23_NTZ']\n_ARCH_S_ = ['ARM_CM85', 'ARM_CM55', 'ARM_CM33', 'ARM_CM23']\n\n# Files to be compiled in the Secure Project\n_SECURE_COMMON_FILE_PATHS_ = [\n    os.path.join('secure', 'context'),\n    os.path.join('secure', 'heap'),\n    os.path.join('secure', 'init'),\n    os.path.join('secure', 'macros')\n]\n\n_SECURE_PORTABLE_FILE_PATHS_ = {\n    'GCC':{\n        'ARM_CM23':[os.path.join('secure', 'context', 'portable', 'GCC', 'ARM_CM23')],\n        'ARM_CM33':[os.path.join('secure', 'context', 'portable', 'GCC', 'ARM_CM33')],\n        'ARM_CM55':[os.path.join('secure', 'context', 'portable', 'GCC', 'ARM_CM33')],\n        'ARM_CM85':[os.path.join('secure', 'context', 'portable', 'GCC', 'ARM_CM33')]\n    },\n    'IAR':{\n        'ARM_CM23':[os.path.join('secure', 'context', 'portable', 'IAR', 'ARM_CM23')],\n        'ARM_CM33':[os.path.join('secure', 'context', 'portable', 'IAR', 'ARM_CM33')],\n        'ARM_CM55':[os.path.join('secure', 'context', 'portable', 'IAR', 'ARM_CM33')],\n        'ARM_CM85':[os.path.join('secure', 'context', 'portable', 'IAR', 'ARM_CM33')]\n    }\n}\n\n# Files to be compiled in the Non-Secure Project\n_NONSECURE_COMMON_FILE_PATHS_ = [\n    'non_secure'\n]\n\n_NONSECURE_PORTABLE_FILE_PATHS_ = {\n    'GCC':{\n        'ARM_CM23'      : [os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM23')],\n        'ARM_CM23_NTZ'  : [os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM23_NTZ')],\n        'ARM_CM33'      : [os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM33')],\n        'ARM_CM33_NTZ'  : [os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM33_NTZ')],\n        'ARM_CM55'      : [os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM33', 'portasm.c'),\n                           os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM55', 'portmacro.h')],\n        'ARM_CM55_NTZ'  : [os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM33_NTZ', 'portasm.c'),\n                           os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM55', 'portmacro.h')],\n        'ARM_CM85'      : [os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM33', 'portasm.c'),\n                           os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM85', 'portmacro.h')],\n        'ARM_CM85_NTZ'  : [os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM33_NTZ', 'portasm.c'),\n                           os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM85', 'portmacro.h')]\n    },\n    'IAR':{\n        'ARM_CM23'      : [os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM23')],\n        'ARM_CM23_NTZ'  : [os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM23_NTZ')],\n        'ARM_CM33'      : [os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33')],\n        'ARM_CM33_NTZ'  : [os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33_NTZ')],\n        'ARM_CM55'      : [os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33', 'portasm.s'),\n                           os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM55', 'portmacro.h')],\n        'ARM_CM55_NTZ'  : [os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33_NTZ', 'portasm.s'),\n                           os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM55', 'portmacro.h')],\n        'ARM_CM85'      : [os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33', 'portasm.s'),\n                           os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM85', 'portmacro.h')],\n        'ARM_CM85_NTZ'  : [os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33_NTZ', 'portasm.s'),\n                           os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM85', 'portmacro.h')]\n    },\n}\n\n\ndef copy_files_in_dir(src_abs_path, dst_abs_path):\n    if os.path.isfile(src_abs_path):\n        print('Src: {}'.format(src_abs_path))\n        print('Dst: {}\\n'.format(dst_abs_path))\n        shutil.copy2(src_abs_path, dst_abs_path)\n    else:\n        for src_file in os.listdir(src_abs_path):\n            src_file_abs_path = os.path.join(src_abs_path, src_file)\n            if os.path.isfile(src_file_abs_path) and src_file != 'ReadMe.txt':\n                if not os.path.exists(dst_abs_path):\n                    os.makedirs(dst_abs_path)\n                print('Src: {}'.format(src_file_abs_path))\n                print('Dst: {}\\n'.format(dst_abs_path))\n                shutil.copy2(src_file_abs_path, dst_abs_path)\n\n\ndef copy_common_files_for_compiler_and_arch(compiler, arch, src_paths, dst_path):\n    for src_path in src_paths:\n\n        src_abs_path = os.path.join(_THIS_FILE_DIRECTORY_, src_path)\n        dst_abs_path = os.path.join(_FREERTOS_PORTABLE_DIRECTORY_, compiler, arch, dst_path)\n\n        copy_files_in_dir(src_abs_path, dst_abs_path)\n\n\ndef copy_portable_files_for_compiler_and_arch(compiler, arch, src_paths, dst_path):\n    for src_path in src_paths[compiler][arch]:\n\n        src_abs_path = os.path.join(_THIS_FILE_DIRECTORY_, src_path)\n        dst_abs_path = os.path.join(_FREERTOS_PORTABLE_DIRECTORY_, compiler, arch, dst_path)\n\n        copy_files_in_dir(src_abs_path, dst_abs_path)\n\n\ndef copy_files():\n    # Copy Secure Files\n    for compiler in _COMPILERS_:\n        for arch in _ARCH_S_:\n            copy_common_files_for_compiler_and_arch(compiler, arch, _SECURE_COMMON_FILE_PATHS_, 'secure')\n            copy_portable_files_for_compiler_and_arch(compiler, arch, _SECURE_PORTABLE_FILE_PATHS_, 'secure')\n\n    # Copy Non-Secure Files\n    for compiler in _COMPILERS_:\n        for arch in _ARCH_NS_:\n            copy_common_files_for_compiler_and_arch(compiler, arch, _NONSECURE_COMMON_FILE_PATHS_, 'non_secure')\n            copy_portable_files_for_compiler_and_arch(compiler, arch, _NONSECURE_PORTABLE_FILE_PATHS_, 'non_secure')\n\n\ndef main():\n    copy_files()\n\n\nif __name__ == '__main__':\n    main()\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/ARMv8M/non_secure/ReadMe.txt",
    "content": "This directory tree contains the master copy of the FreeRTOS Armv8-M and\nArmv8.1-M ports.\nDo not use the files located here!  These file are copied into separate\nFreeRTOS/Source/portable/[compiler]/ARM_CM[23|33|55|85]_NNN directories prior to\neach FreeRTOS release.\n\nIf your Armv8-M/Armv8.1-M application uses TrustZone then use the files from the\nFreeRTOS/Source/portable/[compiler]/ARM_CM[23|33|55|85] directories.\n\nIf your Armv8-M/Armv8.1-M application does not use TrustZone then use the files from\nthe FreeRTOS/Source/portable/[compiler]/ARM_CM[23|33|55|85]_NTZ directories.\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/ARMv8M/non_secure/port.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\n * all the API functions to use the MPU wrappers. That should only be done when\n * task.h is included from an application file. */\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n/* MPU wrappers includes. */\n#include \"mpu_wrappers.h\"\n\n/* Portasm includes. */\n#include \"portasm.h\"\n\n#if ( configENABLE_TRUSTZONE == 1 )\n    /* Secure components includes. */\n    #include \"secure_context.h\"\n    #include \"secure_init.h\"\n#endif /* configENABLE_TRUSTZONE */\n\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/**\n * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only\n * i.e. the processor boots as secure and never jumps to the non-secure side.\n * The Trust Zone support in the port must be disabled in order to run FreeRTOS\n * on the secure side. The following are the valid configuration seetings:\n *\n * 1. Run FreeRTOS on the Secure Side:\n *    configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0\n *\n * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:\n *    configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1\n *\n * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:\n *    configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0\n */\n#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )\n    #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.\n#endif\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the NVIC.\n */\n#define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )\n#define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )\n#define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )\n#define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )\n#define portNVIC_SYSTICK_ENABLE_BIT           ( 1UL << 0UL )\n#define portNVIC_SYSTICK_INT_BIT              ( 1UL << 1UL )\n#define portNVIC_SYSTICK_CLK_BIT              ( 1UL << 2UL )\n#define portNVIC_SYSTICK_COUNT_FLAG_BIT       ( 1UL << 16UL )\n#define portNVIC_PEND_SYSTICK_CLEAR_BIT       ( 1UL << 25UL )\n#define portNVIC_PEND_SYSTICK_SET_BIT         ( 1UL << 26UL )\n#define portMIN_INTERRUPT_PRIORITY            ( 255UL )\n#define portNVIC_PENDSV_PRI                   ( portMIN_INTERRUPT_PRIORITY << 16UL )\n#define portNVIC_SYSTICK_PRI                  ( portMIN_INTERRUPT_PRIORITY << 24UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the SCB.\n */\n#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( volatile uint32_t * ) 0xe000ed24 )\n#define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the FPU.\n */\n#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 )              /* Coprocessor Access Control Register. */\n#define portCPACR_CP10_VALUE    ( 3UL )\n#define portCPACR_CP11_VALUE    portCPACR_CP10_VALUE\n#define portCPACR_CP10_POS      ( 20UL )\n#define portCPACR_CP11_POS      ( 22UL )\n\n#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 )              /* Floating Point Context Control Register. */\n#define portFPCCR_ASPEN_POS     ( 31UL )\n#define portFPCCR_ASPEN_MASK    ( 1UL << portFPCCR_ASPEN_POS )\n#define portFPCCR_LSPEN_POS     ( 30UL )\n#define portFPCCR_LSPEN_MASK    ( 1UL << portFPCCR_LSPEN_POS )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the MPU.\n */\n#define portMPU_TYPE_REG                      ( *( ( volatile uint32_t * ) 0xe000ed90 ) )\n#define portMPU_CTRL_REG                      ( *( ( volatile uint32_t * ) 0xe000ed94 ) )\n#define portMPU_RNR_REG                       ( *( ( volatile uint32_t * ) 0xe000ed98 ) )\n\n#define portMPU_RBAR_REG                      ( *( ( volatile uint32_t * ) 0xe000ed9c ) )\n#define portMPU_RLAR_REG                      ( *( ( volatile uint32_t * ) 0xe000eda0 ) )\n\n#define portMPU_RBAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda4 ) )\n#define portMPU_RLAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda8 ) )\n\n#define portMPU_RBAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edac ) )\n#define portMPU_RLAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edb0 ) )\n\n#define portMPU_RBAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb4 ) )\n#define portMPU_RLAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb8 ) )\n\n#define portMPU_MAIR0_REG                     ( *( ( volatile uint32_t * ) 0xe000edc0 ) )\n#define portMPU_MAIR1_REG                     ( *( ( volatile uint32_t * ) 0xe000edc4 ) )\n\n#define portMPU_RBAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */\n#define portMPU_RLAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */\n\n#define portMPU_MAIR_ATTR0_POS                ( 0UL )\n#define portMPU_MAIR_ATTR0_MASK               ( 0x000000ff )\n\n#define portMPU_MAIR_ATTR1_POS                ( 8UL )\n#define portMPU_MAIR_ATTR1_MASK               ( 0x0000ff00 )\n\n#define portMPU_MAIR_ATTR2_POS                ( 16UL )\n#define portMPU_MAIR_ATTR2_MASK               ( 0x00ff0000 )\n\n#define portMPU_MAIR_ATTR3_POS                ( 24UL )\n#define portMPU_MAIR_ATTR3_MASK               ( 0xff000000 )\n\n#define portMPU_MAIR_ATTR4_POS                ( 0UL )\n#define portMPU_MAIR_ATTR4_MASK               ( 0x000000ff )\n\n#define portMPU_MAIR_ATTR5_POS                ( 8UL )\n#define portMPU_MAIR_ATTR5_MASK               ( 0x0000ff00 )\n\n#define portMPU_MAIR_ATTR6_POS                ( 16UL )\n#define portMPU_MAIR_ATTR6_MASK               ( 0x00ff0000 )\n\n#define portMPU_MAIR_ATTR7_POS                ( 24UL )\n#define portMPU_MAIR_ATTR7_MASK               ( 0xff000000 )\n\n#define portMPU_RLAR_ATTR_INDEX0              ( 0UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX1              ( 1UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX2              ( 2UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX3              ( 3UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX4              ( 4UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX5              ( 5UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX6              ( 6UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX7              ( 7UL << 1UL )\n\n#define portMPU_RLAR_REGION_ENABLE            ( 1UL )\n\n/* Enable privileged access to unmapped region. */\n#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )\n\n/* Enable MPU. */\n#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )\n\n/* Expected value of the portMPU_TYPE register. */\n#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief The maximum 24-bit number.\n *\n * It is needed because the systick is a 24-bit counter.\n */\n#define portMAX_24_BIT_NUMBER       ( 0xffffffUL )\n\n/**\n * @brief A fiddle factor to estimate the number of SysTick counts that would\n * have occurred while the SysTick counter is stopped during tickless idle\n * calculations.\n */\n#define portMISSED_COUNTS_FACTOR    ( 94UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to set up the initial stack.\n */\n#define portINITIAL_XPSR    ( 0x01000000 )\n\n#if ( configRUN_FREERTOS_SECURE_ONLY == 1 )\n\n/**\n * @brief Initial EXC_RETURN value.\n *\n *     FF         FF         FF         FD\n * 1111 1111  1111 1111  1111 1111  1111 1101\n *\n * Bit[6] - 1 --> The exception was taken from the Secure state.\n * Bit[5] - 1 --> Do not skip stacking of additional state context.\n * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\n * Bit[3] - 1 --> Return to the Thread mode.\n * Bit[2] - 1 --> Restore registers from the process stack.\n * Bit[1] - 0 --> Reserved, 0.\n * Bit[0] - 1 --> The exception was taken to the Secure state.\n */\n    #define portINITIAL_EXC_RETURN    ( 0xfffffffd )\n#else\n\n/**\n * @brief Initial EXC_RETURN value.\n *\n *     FF         FF         FF         BC\n * 1111 1111  1111 1111  1111 1111  1011 1100\n *\n * Bit[6] - 0 --> The exception was taken from the Non-Secure state.\n * Bit[5] - 1 --> Do not skip stacking of additional state context.\n * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\n * Bit[3] - 1 --> Return to the Thread mode.\n * Bit[2] - 1 --> Restore registers from the process stack.\n * Bit[1] - 0 --> Reserved, 0.\n * Bit[0] - 0 --> The exception was taken to the Non-Secure state.\n */\n    #define portINITIAL_EXC_RETURN    ( 0xffffffbc )\n#endif /* configRUN_FREERTOS_SECURE_ONLY */\n\n/**\n * @brief CONTROL register privileged bit mask.\n *\n * Bit[0] in CONTROL register tells the privilege:\n *  Bit[0] = 0 ==> The task is privileged.\n *  Bit[0] = 1 ==> The task is not privileged.\n */\n#define portCONTROL_PRIVILEGED_MASK         ( 1UL << 0UL )\n\n/**\n * @brief Initial CONTROL register values.\n */\n#define portINITIAL_CONTROL_UNPRIVILEGED    ( 0x3 )\n#define portINITIAL_CONTROL_PRIVILEGED      ( 0x2 )\n\n/**\n * @brief Let the user override the default SysTick clock rate.  If defined by the\n * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the\n * configuration register.\n */\n#ifndef configSYSTICK_CLOCK_HZ\n    #define configSYSTICK_CLOCK_HZ             ( configCPU_CLOCK_HZ )\n    /* Ensure the SysTick is clocked at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( portNVIC_SYSTICK_CLK_BIT )\n#else\n    /* Select the option to clock SysTick not at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( 0 )\n#endif\n\n/**\n * @brief Let the user override the pre-loading of the initial LR with the\n * address of prvTaskExitError() in case it messes up unwinding of the stack\n * in the debugger.\n */\n#ifdef configTASK_RETURN_ADDRESS\n    #define portTASK_RETURN_ADDRESS    configTASK_RETURN_ADDRESS\n#else\n    #define portTASK_RETURN_ADDRESS    prvTaskExitError\n#endif\n\n/**\n * @brief If portPRELOAD_REGISTERS then registers will be given an initial value\n * when a task is created. This helps in debugging at the cost of code size.\n */\n#define portPRELOAD_REGISTERS    1\n\n/**\n * @brief A task is created without a secure context, and must call\n * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes\n * any secure calls.\n */\n#define portNO_SECURE_CONTEXT    0\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Used to catch tasks that attempt to return from their implementing\n * function.\n */\nstatic void prvTaskExitError( void );\n\n#if ( configENABLE_MPU == 1 )\n\n/**\n * @brief Setup the Memory Protection Unit (MPU).\n */\n    static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\n#endif /* configENABLE_MPU */\n\n#if ( configENABLE_FPU == 1 )\n\n/**\n * @brief Setup the Floating Point Unit (FPU).\n */\n    static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;\n#endif /* configENABLE_FPU */\n\n/**\n * @brief Setup the timer to generate the tick interrupts.\n *\n * The implementation in this file is weak to allow application writers to\n * change the timer used to generate the tick interrupt.\n */\nvoid vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Checks whether the current execution context is interrupt.\n *\n * @return pdTRUE if the current execution context is interrupt, pdFALSE\n * otherwise.\n */\nBaseType_t xPortIsInsideInterrupt( void );\n\n/**\n * @brief Yield the processor.\n */\nvoid vPortYield( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Enter critical section.\n */\nvoid vPortEnterCritical( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Exit from critical section.\n */\nvoid vPortExitCritical( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief SysTick handler.\n */\nvoid SysTick_Handler( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief C part of SVC handler.\n */\nportDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION;\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Each task maintains its own interrupt status in the critical nesting\n * variable.\n */\nPRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;\n\n#if ( configENABLE_TRUSTZONE == 1 )\n\n/**\n * @brief Saved as part of the task context to indicate which context the\n * task is using on the secure side.\n */\n    PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;\n#endif /* configENABLE_TRUSTZONE */\n\n#if ( configUSE_TICKLESS_IDLE == 1 )\n\n/**\n * @brief The number of SysTick increments that make up one tick period.\n */\n    PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0;\n\n/**\n * @brief The maximum number of tick periods that can be suppressed is\n * limited by the 24 bit resolution of the SysTick timer.\n */\n    PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0;\n\n/**\n * @brief Compensate for the CPU cycles that pass while the SysTick is\n * stopped (low power functionality only).\n */\n    PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TICKLESS_IDLE == 1 )\n    __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )\n    {\n        uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;\n        TickType_t xModifiableIdleTime;\n\n        /* Make sure the SysTick reload value does not overflow the counter. */\n        if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\n        {\n            xExpectedIdleTime = xMaximumPossibleSuppressedTicks;\n        }\n\n        /* Enter a critical section but don't use the taskENTER_CRITICAL()\n         * method as that will mask interrupts that should exit sleep mode. */\n        __asm volatile ( \"cpsid i\" ::: \"memory\" );\n        __asm volatile ( \"dsb\" );\n        __asm volatile ( \"isb\" );\n\n        /* If a context switch is pending or a task is waiting for the scheduler\n         * to be unsuspended then abandon the low power entry. */\n        if( eTaskConfirmSleepModeStatus() == eAbortSleep )\n        {\n            /* Re-enable interrupts - see comments above the cpsid instruction\n             * above. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n        }\n        else\n        {\n            /* Stop the SysTick momentarily.  The time the SysTick is stopped for\n             * is accounted for as best it can be, but using the tickless mode will\n             * inevitably result in some tiny drift of the time maintained by the\n             * kernel with respect to calendar time. */\n            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );\n\n            /* Use the SysTick current-value register to determine the number of\n             * SysTick decrements remaining until the next tick interrupt.  If the\n             * current-value register is zero, then there are actually\n             * ulTimerCountsForOneTick decrements remaining, not zero, because the\n             * SysTick requests the interrupt when decrementing from 1 to 0. */\n            ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n\n            if( ulSysTickDecrementsLeft == 0 )\n            {\n                ulSysTickDecrementsLeft = ulTimerCountsForOneTick;\n            }\n\n            /* Calculate the reload value required to wait xExpectedIdleTime\n             * tick periods.  -1 is used because this code normally executes part\n             * way through the first tick period.  But if the SysTick IRQ is now\n             * pending, then clear the IRQ, suppressing the first tick, and correct\n             * the reload value to reflect that the second tick period is already\n             * underway.  The expected idle time is always at least two ticks. */\n            ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );\n\n            if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )\n            {\n                portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;\n                ulReloadValue -= ulTimerCountsForOneTick;\n            }\n\n            if( ulReloadValue > ulStoppedTimerCompensation )\n            {\n                ulReloadValue -= ulStoppedTimerCompensation;\n            }\n\n            /* Set the new reload value. */\n            portNVIC_SYSTICK_LOAD_REG = ulReloadValue;\n\n            /* Clear the SysTick count flag and set the count value back to\n             * zero. */\n            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n            /* Restart SysTick. */\n            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\n\n            /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can\n             * set its parameter to 0 to indicate that its implementation contains\n             * its own wait for interrupt or wait for event instruction, and so wfi\n             * should not be executed again.  However, the original expected idle\n             * time variable must remain unmodified, so a copy is taken. */\n            xModifiableIdleTime = xExpectedIdleTime;\n            configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\n\n            if( xModifiableIdleTime > 0 )\n            {\n                __asm volatile ( \"dsb\" ::: \"memory\" );\n                __asm volatile ( \"wfi\" );\n                __asm volatile ( \"isb\" );\n            }\n\n            configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\n\n            /* Re-enable interrupts to allow the interrupt that brought the MCU\n             * out of sleep mode to execute immediately.  See comments above\n             * the cpsid instruction above. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n            __asm volatile ( \"dsb\" );\n            __asm volatile ( \"isb\" );\n\n            /* Disable interrupts again because the clock is about to be stopped\n             * and interrupts that execute while the clock is stopped will increase\n             * any slippage between the time maintained by the RTOS and calendar\n             * time. */\n            __asm volatile ( \"cpsid i\" ::: \"memory\" );\n            __asm volatile ( \"dsb\" );\n            __asm volatile ( \"isb\" );\n\n            /* Disable the SysTick clock without reading the\n             * portNVIC_SYSTICK_CTRL_REG register to ensure the\n             * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,\n             * the time the SysTick is stopped for is accounted for as best it can\n             * be, but using the tickless mode will inevitably result in some tiny\n             * drift of the time maintained by the kernel with respect to calendar\n             * time*/\n            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );\n\n            /* Determine whether the SysTick has already counted to zero. */\n            if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n            {\n                uint32_t ulCalculatedLoadValue;\n\n                /* The tick interrupt ended the sleep (or is now pending), and\n                 * a new tick period has started.  Reset portNVIC_SYSTICK_LOAD_REG\n                 * with whatever remains of the new tick period. */\n                ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\n\n                /* Don't allow a tiny value, or values that have somehow\n                 * underflowed because the post sleep hook did something\n                 * that took too long or because the SysTick current-value register\n                 * is zero. */\n                if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )\n                {\n                    ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );\n                }\n\n                portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;\n\n                /* As the pending tick will be processed as soon as this\n                 * function exits, the tick value maintained by the tick is stepped\n                 * forward by one less than the time spent waiting. */\n                ulCompleteTickPeriods = xExpectedIdleTime - 1UL;\n            }\n            else\n            {\n                /* Something other than the tick interrupt ended the sleep. */\n\n                /* Use the SysTick current-value register to determine the\n                 * number of SysTick decrements remaining until the expected idle\n                 * time would have ended. */\n                ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n                #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )\n                {\n                    /* If the SysTick is not using the core clock, the current-\n                     * value register might still be zero here.  In that case, the\n                     * SysTick didn't load from the reload register, and there are\n                     * ulReloadValue decrements remaining in the expected idle\n                     * time, not zero. */\n                    if( ulSysTickDecrementsLeft == 0 )\n                    {\n                        ulSysTickDecrementsLeft = ulReloadValue;\n                    }\n                }\n                #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */\n\n                /* Work out how long the sleep lasted rounded to complete tick\n                 * periods (not the ulReload value which accounted for part\n                 * ticks). */\n                ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;\n\n                /* How many complete tick periods passed while the processor\n                 * was waiting? */\n                ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;\n\n                /* The reload value is set to whatever fraction of a single tick\n                 * period remains. */\n                portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;\n            }\n\n            /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,\n             * then set portNVIC_SYSTICK_LOAD_REG back to its standard value.  If\n             * the SysTick is not using the core clock, temporarily configure it to\n             * use the core clock.  This configuration forces the SysTick to load\n             * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next\n             * cycle of the other clock.  Then portNVIC_SYSTICK_LOAD_REG is ready\n             * to receive the standard value immediately. */\n            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n            portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n            #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )\n            {\n                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n            }\n            #else\n            {\n                /* The temporary usage of the core clock has served its purpose,\n                 * as described above.  Resume usage of the other clock. */\n                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\n\n                if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n                {\n                    /* The partial tick period already ended.  Be sure the SysTick\n                     * counts it only once. */\n                    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;\n                }\n\n                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n            }\n            #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */\n\n            /* Step the tick to account for any tick periods that elapsed. */\n            vTaskStepTick( ulCompleteTickPeriods );\n\n            /* Exit with interrupts enabled. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n        }\n    }\n#endif /* configUSE_TICKLESS_IDLE */\n/*-----------------------------------------------------------*/\n\n__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Calculate the constants required to configure the tick interrupt. */\n    #if ( configUSE_TICKLESS_IDLE == 1 )\n    {\n        ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );\n        xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;\n        ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\n    }\n    #endif /* configUSE_TICKLESS_IDLE */\n\n    /* Stop and reset the SysTick. */\n    portNVIC_SYSTICK_CTRL_REG = 0UL;\n    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n    /* Configure SysTick to interrupt at the requested rate. */\n    portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\n    portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvTaskExitError( void )\n{\n    volatile uint32_t ulDummy = 0UL;\n\n    /* A function that implements a task must not exit or attempt to return to\n     * its caller as there is nothing to return to. If a task wants to exit it\n     * should instead call vTaskDelete( NULL ). Artificially force an assert()\n     * to be triggered if configASSERT() is defined, then stop here so\n     * application writers can catch the error. */\n    configASSERT( ulCriticalNesting == ~0UL );\n    portDISABLE_INTERRUPTS();\n\n    while( ulDummy == 0 )\n    {\n        /* This file calls prvTaskExitError() after the scheduler has been\n         * started to remove a compiler warning about the function being\n         * defined but never called.  ulDummy is used purely to quieten other\n         * warnings about code appearing after this function is called - making\n         * ulDummy volatile makes the compiler think the function could return\n         * and therefore not output an 'unreachable code' warning for code that\n         * appears after it. */\n    }\n}\n/*-----------------------------------------------------------*/\n\n#if ( configENABLE_MPU == 1 )\n    static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */\n    {\n        #if defined( __ARMCC_VERSION )\n\n            /* Declaration when these variable are defined in code instead of being\n             * exported from linker scripts. */\n            extern uint32_t * __privileged_functions_start__;\n            extern uint32_t * __privileged_functions_end__;\n            extern uint32_t * __syscalls_flash_start__;\n            extern uint32_t * __syscalls_flash_end__;\n            extern uint32_t * __unprivileged_flash_start__;\n            extern uint32_t * __unprivileged_flash_end__;\n            extern uint32_t * __privileged_sram_start__;\n            extern uint32_t * __privileged_sram_end__;\n        #else /* if defined( __ARMCC_VERSION ) */\n            /* Declaration when these variable are exported from linker scripts. */\n            extern uint32_t __privileged_functions_start__[];\n            extern uint32_t __privileged_functions_end__[];\n            extern uint32_t __syscalls_flash_start__[];\n            extern uint32_t __syscalls_flash_end__[];\n            extern uint32_t __unprivileged_flash_start__[];\n            extern uint32_t __unprivileged_flash_end__[];\n            extern uint32_t __privileged_sram_start__[];\n            extern uint32_t __privileged_sram_end__[];\n        #endif /* defined( __ARMCC_VERSION ) */\n\n        /* The only permitted number of regions are 8 or 16. */\n        configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );\n\n        /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */\n        configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );\n\n        /* Check that the MPU is present. */\n        if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )\n        {\n            /* MAIR0 - Index 0. */\n            portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\n            /* MAIR0 - Index 1. */\n            portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\n\n            /* Setup privileged flash as Read Only so that privileged tasks can\n             * read it but not modify. */\n            portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_PRIVILEGED_READ_ONLY );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Setup unprivileged flash as Read Only by both privileged and\n             * unprivileged tasks. All tasks can read it but no-one can modify. */\n            portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_READ_ONLY );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Setup unprivileged syscalls flash as Read Only by both privileged\n             * and unprivileged tasks. All tasks can read it but no-one can modify. */\n            portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_READ_ONLY );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Setup RAM containing kernel data for privileged access only. */\n            portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\n                               ( portMPU_REGION_EXECUTE_NEVER );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Enable mem fault. */\n            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;\n\n            /* Enable MPU with privileged background access i.e. unmapped\n             * regions have privileged access. */\n            portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );\n        }\n    }\n#endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\n#if ( configENABLE_FPU == 1 )\n    static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */\n    {\n        #if ( configENABLE_TRUSTZONE == 1 )\n        {\n            /* Enable non-secure access to the FPU. */\n            SecureInit_EnableNSFPUAccess();\n        }\n        #endif /* configENABLE_TRUSTZONE */\n\n        /* CP10 = 11 ==> Full access to FPU i.e. both privileged and\n         * unprivileged code should be able to access FPU. CP11 should be\n         * programmed to the same value as CP10. */\n        *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |\n                            ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )\n                            );\n\n        /* ASPEN = 1 ==> Hardware should automatically preserve floating point\n         * context on exception entry and restore on exception return.\n         * LSPEN = 1 ==> Enable lazy context save of FP state. */\n        *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );\n    }\n#endif /* configENABLE_FPU */\n/*-----------------------------------------------------------*/\n\nvoid vPortYield( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Set a PendSV to request a context switch. */\n    portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\n\n    /* Barriers are normally not required but do ensure the code is\n     * completely within the specified behaviour for the architecture. */\n    __asm volatile ( \"dsb\" ::: \"memory\" );\n    __asm volatile ( \"isb\" );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */\n{\n    portDISABLE_INTERRUPTS();\n    ulCriticalNesting++;\n\n    /* Barriers are normally not required but do ensure the code is\n     * completely within the specified behaviour for the architecture. */\n    __asm volatile ( \"dsb\" ::: \"memory\" );\n    __asm volatile ( \"isb\" );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */\n{\n    configASSERT( ulCriticalNesting );\n    ulCriticalNesting--;\n\n    if( ulCriticalNesting == 0 )\n    {\n        portENABLE_INTERRUPTS();\n    }\n}\n/*-----------------------------------------------------------*/\n\nvoid SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */\n{\n    uint32_t ulPreviousMask;\n\n    ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();\n    {\n        /* Increment the RTOS tick. */\n        if( xTaskIncrementTick() != pdFALSE )\n        {\n            /* Pend a context switch. */\n            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\n        }\n    }\n    portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */\n{\n    #if ( configENABLE_MPU == 1 )\n        #if defined( __ARMCC_VERSION )\n\n            /* Declaration when these variable are defined in code instead of being\n             * exported from linker scripts. */\n            extern uint32_t * __syscalls_flash_start__;\n            extern uint32_t * __syscalls_flash_end__;\n        #else\n            /* Declaration when these variable are exported from linker scripts. */\n            extern uint32_t __syscalls_flash_start__[];\n            extern uint32_t __syscalls_flash_end__[];\n        #endif /* defined( __ARMCC_VERSION ) */\n    #endif /* configENABLE_MPU */\n\n    uint32_t ulPC;\n\n    #if ( configENABLE_TRUSTZONE == 1 )\n        uint32_t ulR0, ulR1;\n        extern TaskHandle_t pxCurrentTCB;\n        #if ( configENABLE_MPU == 1 )\n            uint32_t ulControl, ulIsTaskPrivileged;\n        #endif /* configENABLE_MPU */\n    #endif /* configENABLE_TRUSTZONE */\n    uint8_t ucSVCNumber;\n\n    /* Register are stored on the stack in the following order - R0, R1, R2, R3,\n     * R12, LR, PC, xPSR. */\n    ulPC = pulCallerStackAddress[ 6 ];\n    ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];\n\n    switch( ucSVCNumber )\n    {\n        #if ( configENABLE_TRUSTZONE == 1 )\n            case portSVC_ALLOCATE_SECURE_CONTEXT:\n\n                /* R0 contains the stack size passed as parameter to the\n                 * vPortAllocateSecureContext function. */\n                ulR0 = pulCallerStackAddress[ 0 ];\n\n                #if ( configENABLE_MPU == 1 )\n                {\n                    /* Read the CONTROL register value. */\n                    __asm volatile ( \"mrs %0, control\"  : \"=r\" ( ulControl ) );\n\n                    /* The task that raised the SVC is privileged if Bit[0]\n                     * in the CONTROL register is 0. */\n                    ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );\n\n                    /* Allocate and load a context for the secure task. */\n                    xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );\n                }\n                #else /* if ( configENABLE_MPU == 1 ) */\n                {\n                    /* Allocate and load a context for the secure task. */\n                    xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );\n                }\n                #endif /* configENABLE_MPU */\n\n                configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );\n                SecureContext_LoadContext( xSecureContext, pxCurrentTCB );\n                break;\n\n            case portSVC_FREE_SECURE_CONTEXT:\n\n                /* R0 contains TCB being freed and R1 contains the secure\n                 * context handle to be freed. */\n                ulR0 = pulCallerStackAddress[ 0 ];\n                ulR1 = pulCallerStackAddress[ 1 ];\n\n                /* Free the secure context. */\n                SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );\n                break;\n        #endif /* configENABLE_TRUSTZONE */\n\n        case portSVC_START_SCHEDULER:\n            #if ( configENABLE_TRUSTZONE == 1 )\n            {\n                /* De-prioritize the non-secure exceptions so that the\n                 * non-secure pendSV runs at the lowest priority. */\n                SecureInit_DePrioritizeNSExceptions();\n\n                /* Initialize the secure context management system. */\n                SecureContext_Init();\n            }\n            #endif /* configENABLE_TRUSTZONE */\n\n            #if ( configENABLE_FPU == 1 )\n            {\n                /* Setup the Floating Point Unit (FPU). */\n                prvSetupFPU();\n            }\n            #endif /* configENABLE_FPU */\n\n            /* Setup the context of the first task so that the first task starts\n             * executing. */\n            vRestoreContextOfFirstTask();\n            break;\n\n            #if ( configENABLE_MPU == 1 )\n                case portSVC_RAISE_PRIVILEGE:\n\n                    /* Only raise the privilege, if the svc was raised from any of\n                     * the system calls. */\n                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&\n                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )\n                    {\n                        vRaisePrivilege();\n                    }\n                    break;\n            #endif /* configENABLE_MPU */\n\n        default:\n            /* Incorrect SVC call. */\n            configASSERT( pdFALSE );\n    }\n}\n/*-----------------------------------------------------------*/\n/* *INDENT-OFF* */\n#if ( configENABLE_MPU == 1 )\n    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,\n                                         StackType_t * pxEndOfStack,\n                                         TaskFunction_t pxCode,\n                                         void * pvParameters,\n                                         BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */\n#else\n    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,\n                                         StackType_t * pxEndOfStack,\n                                         TaskFunction_t pxCode,\n                                         void * pvParameters ) /* PRIVILEGED_FUNCTION */\n#endif /* configENABLE_MPU */\n/* *INDENT-ON* */\n{\n    /* Simulate the stack frame as it would be created by a context switch\n     * interrupt. */\n    #if ( portPRELOAD_REGISTERS == 0 )\n    {\n        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\n        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\n        pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */\n        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */\n        pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */\n        *pxTopOfStack = portINITIAL_EXC_RETURN;\n\n        #if ( configENABLE_MPU == 1 )\n        {\n            pxTopOfStack--;\n\n            if( xRunPrivileged == pdTRUE )\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n            else\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n        }\n        #endif /* configENABLE_MPU */\n\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\n\n        #if ( configENABLE_TRUSTZONE == 1 )\n        {\n            pxTopOfStack--;\n            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\n        }\n        #endif /* configENABLE_TRUSTZONE */\n    }\n    #else /* portPRELOAD_REGISTERS */\n    {\n        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\n        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04 */\n        pxTopOfStack--;\n        *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN */\n\n        #if ( configENABLE_MPU == 1 )\n        {\n            pxTopOfStack--;\n\n            if( xRunPrivileged == pdTRUE )\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n            else\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n        }\n        #endif /* configENABLE_MPU */\n\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\n\n        #if ( configENABLE_TRUSTZONE == 1 )\n        {\n            pxTopOfStack--;\n            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\n        }\n        #endif /* configENABLE_TRUSTZONE */\n    }\n    #endif /* portPRELOAD_REGISTERS */\n\n    return pxTopOfStack;\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Make PendSV, CallSV and SysTick the same priority as the kernel. */\n    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;\n    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;\n\n    #if ( configENABLE_MPU == 1 )\n    {\n        /* Setup the Memory Protection Unit (MPU). */\n        prvSetupMPU();\n    }\n    #endif /* configENABLE_MPU */\n\n    /* Start the timer that generates the tick ISR. Interrupts are disabled\n     * here already. */\n    vPortSetupTimerInterrupt();\n\n    /* Initialize the critical nesting count ready for the first task. */\n    ulCriticalNesting = 0;\n\n    /* Start the first task. */\n    vStartFirstTask();\n\n    /* Should never get here as the tasks will now be executing. Call the task\n     * exit error function to prevent compiler warnings about a static function\n     * not being called in the case that the application writer overrides this\n     * functionality by defining configTASK_RETURN_ADDRESS. Call\n     * vTaskSwitchContext() so link time optimization does not remove the\n     * symbol. */\n    vTaskSwitchContext();\n    prvTaskExitError();\n\n    /* Should not get here. */\n    return 0;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Not implemented in ports where there is nothing to return to.\n     * Artificially force an assert. */\n    configASSERT( ulCriticalNesting == 1000UL );\n}\n/*-----------------------------------------------------------*/\n\n#if ( configENABLE_MPU == 1 )\n    void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,\n                                    const struct xMEMORY_REGION * const xRegions,\n                                    StackType_t * pxBottomOfStack,\n                                    uint32_t ulStackDepth )\n    {\n        uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;\n        int32_t lIndex = 0;\n\n        #if defined( __ARMCC_VERSION )\n\n            /* Declaration when these variable are defined in code instead of being\n             * exported from linker scripts. */\n            extern uint32_t * __privileged_sram_start__;\n            extern uint32_t * __privileged_sram_end__;\n        #else\n            /* Declaration when these variable are exported from linker scripts. */\n            extern uint32_t __privileged_sram_start__[];\n            extern uint32_t __privileged_sram_end__[];\n        #endif /* defined( __ARMCC_VERSION ) */\n\n        /* Setup MAIR0. */\n        xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\n        xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\n\n        /* This function is called automatically when the task is created - in\n         * which case the stack region parameters will be valid.  At all other\n         * times the stack parameters will not be valid and it is assumed that\n         * the stack region has already been configured. */\n        if( ulStackDepth > 0 )\n        {\n            ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;\n            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;\n\n            /* If the stack is within the privileged SRAM, do not protect it\n             * using a separate MPU region. This is needed because privileged\n             * SRAM is already protected using an MPU region and ARMv8-M does\n             * not allow overlapping MPU regions. */\n            if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) &&\n                ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) )\n            {\n                xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0;\n                xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0;\n            }\n            else\n            {\n                /* Define the region that allows access to the stack. */\n                ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK;\n                ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\n\n                xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |\n                                                             ( portMPU_REGION_NON_SHAREABLE ) |\n                                                             ( portMPU_REGION_READ_WRITE ) |\n                                                             ( portMPU_REGION_EXECUTE_NEVER );\n\n                xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) |\n                                                             ( portMPU_RLAR_ATTR_INDEX0 ) |\n                                                             ( portMPU_RLAR_REGION_ENABLE );\n            }\n        }\n\n        /* User supplied configurable regions. */\n        for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )\n        {\n            /* If xRegions is NULL i.e. the task has not specified any MPU\n             * region, the else part ensures that all the configurable MPU\n             * regions are invalidated. */\n            if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )\n            {\n                /* Translate the generic region definition contained in xRegions\n                 * into the ARMv8 specific MPU settings that are then stored in\n                 * xMPUSettings. */\n                ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;\n                ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;\n                ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\n\n                /* Start address. */\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |\n                                                                          ( portMPU_REGION_NON_SHAREABLE );\n\n                /* RO/RW. */\n                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )\n                {\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );\n                }\n                else\n                {\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );\n                }\n\n                /* XN. */\n                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )\n                {\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );\n                }\n\n                /* End Address. */\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |\n                                                                          ( portMPU_RLAR_REGION_ENABLE );\n\n                /* Normal memory/ Device memory. */\n                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )\n                {\n                    /* Attr1 in MAIR0 is configured as device memory. */\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;\n                }\n                else\n                {\n                    /* Attr0 in MAIR0 is configured as normal memory. */\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;\n                }\n            }\n            else\n            {\n                /* Invalidate the region. */\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;\n            }\n\n            lIndex++;\n        }\n    }\n#endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\nBaseType_t xPortIsInsideInterrupt( void )\n{\n    uint32_t ulCurrentInterrupt;\n    BaseType_t xReturn;\n\n    /* Obtain the number of the currently executing interrupt. Interrupt Program\n     * Status Register (IPSR) holds the exception number of the currently-executing\n     * exception or zero for Thread mode.*/\n    __asm volatile ( \"mrs %0, ipsr\" : \"=r\" ( ulCurrentInterrupt )::\"memory\" );\n\n    if( ulCurrentInterrupt == 0 )\n    {\n        xReturn = pdFALSE;\n    }\n    else\n    {\n        xReturn = pdTRUE;\n    }\n\n    return xReturn;\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portasm.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Standard includes. */\n#include <stdint.h>\n\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION\n * is defined correctly and privileged functions are placed in correct sections. */\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/* Portasm includes. */\n#include \"portasm.h\"\n\n/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the\n * header files. */\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n#if ( configENABLE_FPU == 1 )\n    #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.\n#endif\n\nvoid vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr  r2, pxCurrentTCBConst2\t\t\t\t\t\t\\n\"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n        \"\tldr  r3, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Read pxCurrentTCB. */\n        \"\tldr  r0, [r3]\t\t\t\t\t\t\t\t\t\\n\"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"\tdmb\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Complete outstanding transfers before disabling MPU. */\n            \"\tldr r2, xMPUCTRLConst2\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n            \"\tldr r4, [r2]\t\t\t\t\t\t\t\t\\n\"/* Read the value of MPU_CTRL. */\n            \"\tmovs r5, #1\t\t\t\t\t\t\t\t\t\\n\"/* r5 = 1. */\n            \"\tbics r4, r5\t\t\t\t\t\t\t\t\t\\n\"/* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */\n            \"\tstr r4, [r2]\t\t\t\t\t\t\t\t\\n\"/* Disable MPU. */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tadds r3, #4\t\t\t\t\t\t\t\t\t\\n\"/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\n            \"\tldr  r4, [r3]\t\t\t\t\t\t\t\t\\n\"/* r4 = *r3 i.e. r4 = MAIR0. */\n            \"\tldr  r2, xMAIR0Const2\t\t\t\t\t\t\\n\"/* r2 = 0xe000edc0 [Location of MAIR0]. */\n            \"\tstr  r4, [r2]\t\t\t\t\t\t\t\t\\n\"/* Program MAIR0. */\n            \"\tldr  r2, xRNRConst2\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed98 [Location of RNR]. */\n            \"\tadds r3, #4\t\t\t\t\t\t\t\t\t\\n\"/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */\n            \"\tmovs r5, #4\t\t\t\t\t\t\t\t\t\\n\"/* r5 = 4. */\n            \"\tstr  r5, [r2]\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 4. */\n            \"\tldmia r3!, {r6,r7}\t\t\t\t\t\t\t\\n\"/* Read first set of RBAR/RLAR from TCB. */\n            \"\tldr  r4, xRBARConst2\t\t\t\t\t\t\\n\"/* r4 = 0xe000ed9c [Location of RBAR]. */\n            \"\tstmia r4!, {r6,r7}\t\t\t\t\t\t\t\\n\"/* Write first set of RBAR/RLAR registers. */\n            \"\tmovs r5, #5\t\t\t\t\t\t\t\t\t\\n\"/* r5 = 5. */\n            \"\tstr  r5, [r2]\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 5. */\n            \"\tldmia r3!, {r6,r7}\t\t\t\t\t\t\t\\n\"/* Read second set of RBAR/RLAR from TCB. */\n            \"\tldr  r4, xRBARConst2\t\t\t\t\t\t\\n\"/* r4 = 0xe000ed9c [Location of RBAR]. */\n            \"\tstmia r4!, {r6,r7}\t\t\t\t\t\t\t\\n\"/* Write second set of RBAR/RLAR registers. */\n            \"\tmovs r5, #6\t\t\t\t\t\t\t\t\t\\n\"/* r5 = 6. */\n            \"\tstr  r5, [r2]\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 6. */\n            \"\tldmia r3!, {r6,r7}\t\t\t\t\t\t\t\\n\"/* Read third set of RBAR/RLAR from TCB. */\n            \"\tldr  r4, xRBARConst2\t\t\t\t\t\t\\n\"/* r4 = 0xe000ed9c [Location of RBAR]. */\n            \"\tstmia r4!, {r6,r7}\t\t\t\t\t\t\t\\n\"/* Write third set of RBAR/RLAR registers. */\n            \"\tmovs r5, #7\t\t\t\t\t\t\t\t\t\\n\"/* r5 = 7. */\n            \"\tstr  r5, [r2]\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 7. */\n            \"\tldmia r3!, {r6,r7}\t\t\t\t\t\t\t\\n\"/* Read fourth set of RBAR/RLAR from TCB. */\n            \"\tldr  r4, xRBARConst2\t\t\t\t\t\t\\n\"/* r4 = 0xe000ed9c [Location of RBAR]. */\n            \"\tstmia r4!, {r6,r7}\t\t\t\t\t\t\t\\n\"/* Write fourth set of RBAR/RLAR registers. */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tldr r2, xMPUCTRLConst2\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n            \"\tldr r4, [r2]\t\t\t\t\t\t\t\t\\n\"/* Read the value of MPU_CTRL. */\n            \"\tmovs r5, #1\t\t\t\t\t\t\t\t\t\\n\"/* r5 = 1. */\n            \"\torrs r4, r5\t\t\t\t\t\t\t\t\t\\n\"/* r4 = r4 | r5 i.e. Set the bit 0 in r4. */\n            \"\tstr r4, [r2]\t\t\t\t\t\t\t\t\\n\"/* Enable MPU. */\n            \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Force memory writes before continuing. */\n        #endif /* configENABLE_MPU */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"\tldm  r0!, {r1-r4}\t\t\t\t\t\t\t\\n\"/* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */\n            \"\tldr  r5, xSecureContextConst2\t\t\t\t\\n\"\n            \"\tstr  r1, [r5]\t\t\t\t\t\t\t\t\\n\"/* Set xSecureContext to this task's value for the same. */\n            \"\tmsr  psplim, r2\t\t\t\t\t\t\t\t\\n\"/* Set this task's PSPLIM value. */\n            \"\tmsr  control, r3\t\t\t\t\t\t\t\\n\"/* Set this task's CONTROL value. */\n            \"\tadds r0, #32\t\t\t\t\t\t\t\t\\n\"/* Discard everything up to r0. */\n            \"\tmsr  psp, r0\t\t\t\t\t\t\t\t\\n\"/* This is now the new top of stack to use in the task. */\n            \"\tisb\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tbx   r4\t\t\t\t\t\t\t\t\t\t\\n\"/* Finally, branch to EXC_RETURN. */\n        #else /* configENABLE_MPU */\n            \"\tldm  r0!, {r1-r3}\t\t\t\t\t\t\t\\n\"/* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */\n            \"\tldr  r4, xSecureContextConst2\t\t\t\t\\n\"\n            \"\tstr  r1, [r4]\t\t\t\t\t\t\t\t\\n\"/* Set xSecureContext to this task's value for the same. */\n            \"\tmsr  psplim, r2\t\t\t\t\t\t\t\t\\n\"/* Set this task's PSPLIM value. */\n            \"\tmovs r1, #2\t\t\t\t\t\t\t\t\t\\n\"/* r1 = 2. */\n            \"\tmsr  CONTROL, r1\t\t\t\t\t\t\t\\n\"/* Switch to use PSP in the thread mode. */\n            \"\tadds r0, #32\t\t\t\t\t\t\t\t\\n\"/* Discard everything up to r0. */\n            \"\tmsr  psp, r0\t\t\t\t\t\t\t\t\\n\"/* This is now the new top of stack to use in the task. */\n            \"\tisb\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tbx   r3\t\t\t\t\t\t\t\t\t\t\\n\"/* Finally, branch to EXC_RETURN. */\n        #endif /* configENABLE_MPU */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.align 4\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"pxCurrentTCBConst2: .word pxCurrentTCB\t\t\t\t\\n\"\n        \"xSecureContextConst2: .word xSecureContext\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"xMPUCTRLConst2: .word 0xe000ed94\t\t\t\t\\n\"\n            \"xMAIR0Const2: .word 0xe000edc0\t\t\t\t\t\\n\"\n            \"xRNRConst2: .word 0xe000ed98\t\t\t\t\t\\n\"\n            \"xRBARConst2: .word 0xe000ed9c\t\t\t\t\t\\n\"\n        #endif /* configENABLE_MPU */\n    );\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrs r0, control\t\t\t\t\t\t\t\t\t\\n\"/* r0 = CONTROL. */\n        \"\tmovs r1, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* r1 = 1. */\n        \"\ttst r0, r1\t\t\t\t\t\t\t\t\t\t\\n\"/* Perform r0 & r1 (bitwise AND) and update the conditions flag. */\n        \"\tbeq running_privileged\t\t\t\t\t\t\t\\n\"/* If the result of previous AND operation was 0, branch. */\n        \"\tmovs r0, #0\t\t\t\t\t\t\t\t\t\t\\n\"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return. */\n        \" running_privileged:\t\t\t\t\t\t\t\t\\n\"\n        \"\tmovs r0, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return. */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.align 4\t\t\t\t\t\t\t\t\t\t\\n\"\n        ::: \"r0\", \"r1\", \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrs r0, control\t\t\t\t\t\t\t\t\t\\n\"/* Read the CONTROL register. */\n        \"\tmovs r1, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* r1 = 1. */\n        \"\tbics r0, r1\t\t\t\t\t\t\t\t\t\t\\n\"/* Clear the bit 0. */\n        \"\tmsr control, r0\t\t\t\t\t\t\t\t\t\\n\"/* Write back the new CONTROL value. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return to the caller. */\n        ::: \"r0\", \"r1\", \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vResetPrivilege( void ) /* __attribute__ (( naked )) */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrs r0, control\t\t\t\t\t\t\t\t\t\\n\"/* r0 = CONTROL. */\n        \"\tmovs r1, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* r1 = 1. */\n        \"\torrs r0, r1\t\t\t\t\t\t\t\t\t\t\\n\"/* r0 = r0 | r1. */\n        \"\tmsr control, r0\t\t\t\t\t\t\t\t\t\\n\"/* CONTROL = r0. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return to the caller. */\n        ::: \"r0\", \"r1\", \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r0, xVTORConst\t\t\t\t\t\t\t\t\\n\"/* Use the NVIC offset register to locate the stack. */\n        \"\tldr r0, [r0]\t\t\t\t\t\t\t\t\t\\n\"/* Read the VTOR register which gives the address of vector table. */\n        \"\tldr r0, [r0]\t\t\t\t\t\t\t\t\t\\n\"/* The first entry in vector table is stack pointer. */\n        \"\tmsr msp, r0\t\t\t\t\t\t\t\t\t\t\\n\"/* Set the MSP back to the start of the stack. */\n        \"\tcpsie i\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Globally enable interrupts. */\n        \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tsvc %0\t\t\t\t\t\t\t\t\t\t\t\\n\"/* System call to start the first task. */\n        \"\tnop\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"   .align 4\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"xVTORConst: .word 0xe000ed08\t\t\t\t\t\t\\n\"\n        ::\"i\" ( portSVC_START_SCHEDULER ) : \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nuint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrs r0, PRIMASK\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tcpsid i\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        ::: \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmsr PRIMASK, r0\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        ::: \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.extern SecureContext_SaveContext\t\t\t\t\\n\"\n        \"\t.extern SecureContext_LoadContext\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r3, xSecureContextConst\t\t\t\t\t\t\\n\"/* Read the location of xSecureContext i.e. &( xSecureContext ). */\n        \"\tldr r0, [r3]\t\t\t\t\t\t\t\t\t\\n\"/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */\n        \"\tldr r3, pxCurrentTCBConst\t\t\t\t\t\t\\n\"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n        \"\tldr r1, [r3]\t\t\t\t\t\t\t\t\t\\n\"/* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later.*/\n        \"\tmrs r2, psp\t\t\t\t\t\t\t\t\t\t\\n\"/* Read PSP in r2. */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tcbz r0, save_ns_context\t\t\t\t\t\t\t\\n\"/* No secure context to save. */\n        \"\tpush {r0-r2, r14}\t\t\t\t\t\t\t\t\\n\"\n        \"\tbl SecureContext_SaveContext\t\t\t\t\t\\n\"/* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */\n        \"\tpop {r0-r3}\t\t\t\t\t\t\t\t\t\t\\n\"/* LR is now in r3. */\n        \"\tmov lr, r3\t\t\t\t\t\t\t\t\t\t\\n\"/* LR = r3. */\n        \"\tlsls r1, r3, #25\t\t\t\t\t\t\t\t\\n\"/* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\n        \"\tbpl save_ns_context\t\t\t\t\t\t\t\t\\n\"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\n        \"\tldr r3, pxCurrentTCBConst\t\t\t\t\t\t\\n\"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n        \"\tldr r1, [r3]\t\t\t\t\t\t\t\t\t\\n\"/* Read pxCurrentTCB. */\n        #if ( configENABLE_MPU == 1 )\n            \"\tsubs r2, r2, #16\t\t\t\t\t\t\t\\n\"/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */\n            \"\tstr r2, [r1]\t\t\t\t\t\t\t\t\\n\"/* Save the new top of stack in TCB. */\n            \"\tmrs r1, psplim\t\t\t\t\t\t\t\t\\n\"/* r1 = PSPLIM. */\n            \"\tmrs r3, control\t\t\t\t\t\t\t\t\\n\"/* r3 = CONTROL. */\n            \"\tmov r4, lr\t\t\t\t\t\t\t\t\t\\n\"/* r4 = LR/EXC_RETURN. */\n            \"\tstmia r2!, {r0, r1, r3, r4}\t\t\t\t\t\\n\"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\n        #else /* configENABLE_MPU */\n            \"\tsubs r2, r2, #12\t\t\t\t\t\t\t\\n\"/* Make space for xSecureContext, PSPLIM and LR on the stack. */\n            \"\tstr r2, [r1]\t\t\t\t\t\t\t\t\\n\"/* Save the new top of stack in TCB. */\n            \"\tmrs r1, psplim\t\t\t\t\t\t\t\t\\n\"/* r1 = PSPLIM. */\n            \"\tmov r3, lr\t\t\t\t\t\t\t\t\t\\n\"/* r3 = LR/EXC_RETURN. */\n            \"\tstmia r2!, {r0, r1, r3}\t\t\t\t\t\t\\n\"/* Store xSecureContext, PSPLIM and LR on the stack. */\n        #endif /* configENABLE_MPU */\n        \"\tb select_next_task\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \" save_ns_context:\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r3, pxCurrentTCBConst\t\t\t\t\t\t\\n\"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n        \"\tldr r1, [r3]\t\t\t\t\t\t\t\t\t\\n\"/* Read pxCurrentTCB. */\n        #if ( configENABLE_MPU == 1 )\n            \"\tsubs r2, r2, #48\t\t\t\t\t\t\t\\n\"/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */\n            \"\tstr r2, [r1]\t\t\t\t\t\t\t\t\\n\"/* Save the new top of stack in TCB. */\n            \"\tadds r2, r2, #16\t\t\t\t\t\t\t\\n\"/* r2 = r2 + 16. */\n            \"\tstmia r2!, {r4-r7}\t\t\t\t\t\t\t\\n\"/* Store the low registers that are not saved automatically. */\n            \"\tmov r4, r8\t\t\t\t\t\t\t\t\t\\n\"/* r4 = r8. */\n            \"\tmov r5, r9\t\t\t\t\t\t\t\t\t\\n\"/* r5 = r9. */\n            \"\tmov r6, r10\t\t\t\t\t\t\t\t\t\\n\"/* r6 = r10. */\n            \"\tmov r7, r11\t\t\t\t\t\t\t\t\t\\n\"/* r7 = r11. */\n            \"\tstmia r2!, {r4-r7}\t\t\t\t\t\t\t\\n\"/* Store the high registers that are not saved automatically. */\n            \"\tmrs r1, psplim\t\t\t\t\t\t\t\t\\n\"/* r1 = PSPLIM. */\n            \"\tmrs r3, control\t\t\t\t\t\t\t\t\\n\"/* r3 = CONTROL. */\n            \"\tmov r4, lr\t\t\t\t\t\t\t\t\t\\n\"/* r4 = LR/EXC_RETURN. */\n            \"\tsubs r2, r2, #48\t\t\t\t\t\t\t\\n\"/* r2 = r2 - 48. */\n            \"\tstmia r2!, {r0, r1, r3, r4}\t\t\t\t\t\\n\"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\n        #else /* configENABLE_MPU */\n            \"\tsubs r2, r2, #44\t\t\t\t\t\t\t\\n\"/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */\n            \"\tstr r2, [r1]\t\t\t\t\t\t\t\t\\n\"/* Save the new top of stack in TCB. */\n            \"\tmrs r1, psplim\t\t\t\t\t\t\t\t\\n\"/* r1 = PSPLIM. */\n            \"\tmov r3, lr\t\t\t\t\t\t\t\t\t\\n\"/* r3 = LR/EXC_RETURN. */\n            \"\tstmia r2!, {r0, r1, r3-r7}\t\t\t\t\t\\n\"/* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */\n            \"\tmov r4, r8\t\t\t\t\t\t\t\t\t\\n\"/* r4 = r8. */\n            \"\tmov r5, r9\t\t\t\t\t\t\t\t\t\\n\"/* r5 = r9. */\n            \"\tmov r6, r10\t\t\t\t\t\t\t\t\t\\n\"/* r6 = r10. */\n            \"\tmov r7, r11\t\t\t\t\t\t\t\t\t\\n\"/* r7 = r11. */\n            \"\tstmia r2!, {r4-r7}\t\t\t\t\t\t\t\\n\"/* Store the high registers that are not saved automatically. */\n        #endif /* configENABLE_MPU */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \" select_next_task:\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tcpsid i\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tbl vTaskSwitchContext\t\t\t\t\t\t\t\\n\"\n        \"\tcpsie i\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r3, pxCurrentTCBConst\t\t\t\t\t\t\\n\"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n        \"\tldr r1, [r3]\t\t\t\t\t\t\t\t\t\\n\"/* Read pxCurrentTCB. */\n        \"\tldr r2, [r1]\t\t\t\t\t\t\t\t\t\\n\"/* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"\tdmb\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Complete outstanding transfers before disabling MPU. */\n            \"\tldr r3, xMPUCTRLConst\t\t\t\t\t\t\\n\"/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */\n            \"\tldr r4, [r3]\t\t\t\t\t\t\t\t\\n\"/* Read the value of MPU_CTRL. */\n            \"\tmovs r5, #1\t\t\t\t\t\t\t\t\t\\n\"/* r5 = 1. */\n            \"\tbics r4, r5\t\t\t\t\t\t\t\t\t\\n\"/* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */\n            \"\tstr r4, [r3]\t\t\t\t\t\t\t\t\\n\"/* Disable MPU. */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tadds r1, #4\t\t\t\t\t\t\t\t\t\\n\"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\n            \"\tldr r4, [r1]\t\t\t\t\t\t\t\t\\n\"/* r4 = *r1 i.e. r4 = MAIR0. */\n            \"\tldr r3, xMAIR0Const\t\t\t\t\t\t\t\\n\"/* r3 = 0xe000edc0 [Location of MAIR0]. */\n            \"\tstr r4, [r3]\t\t\t\t\t\t\t\t\\n\"/* Program MAIR0. */\n            \"\tldr r4, xRNRConst\t\t\t\t\t\t\t\\n\"/* r4 = 0xe000ed98 [Location of RNR]. */\n            \"\tadds r1, #4\t\t\t\t\t\t\t\t\t\\n\"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\n            \"\tmovs r5, #4\t\t\t\t\t\t\t\t\t\\n\"/* r5 = 4. */\n            \"\tstr  r5, [r4]\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 4. */\n            \"\tldmia r1!, {r6,r7}\t\t\t\t\t\t\t\\n\"/* Read first set of RBAR/RLAR from TCB. */\n            \"\tldr  r3, xRBARConst\t\t\t\t\t\t\t\\n\"/* r3 = 0xe000ed9c [Location of RBAR]. */\n            \"\tstmia r3!, {r6,r7}\t\t\t\t\t\t\t\\n\"/* Write first set of RBAR/RLAR registers. */\n            \"\tmovs r5, #5\t\t\t\t\t\t\t\t\t\\n\"/* r5 = 5. */\n            \"\tstr  r5, [r4]\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 5. */\n            \"\tldmia r1!, {r6,r7}\t\t\t\t\t\t\t\\n\"/* Read second set of RBAR/RLAR from TCB. */\n            \"\tldr  r3, xRBARConst\t\t\t\t\t\t\t\\n\"/* r3 = 0xe000ed9c [Location of RBAR]. */\n            \"\tstmia r3!, {r6,r7}\t\t\t\t\t\t\t\\n\"/* Write second set of RBAR/RLAR registers. */\n            \"\tmovs r5, #6\t\t\t\t\t\t\t\t\t\\n\"/* r5 = 6. */\n            \"\tstr  r5, [r4]\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 6. */\n            \"\tldmia r1!, {r6,r7}\t\t\t\t\t\t\t\\n\"/* Read third set of RBAR/RLAR from TCB. */\n            \"\tldr  r3, xRBARConst\t\t\t\t\t\t\t\\n\"/* r3 = 0xe000ed9c [Location of RBAR]. */\n            \"\tstmia r3!, {r6,r7}\t\t\t\t\t\t\t\\n\"/* Write third set of RBAR/RLAR registers. */\n            \"\tmovs r5, #7\t\t\t\t\t\t\t\t\t\\n\"/* r5 = 7. */\n            \"\tstr  r5, [r4]\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 7. */\n            \"\tldmia r1!, {r6,r7}\t\t\t\t\t\t\t\\n\"/* Read fourth set of RBAR/RLAR from TCB. */\n            \"\tldr  r3, xRBARConst\t\t\t\t\t\t\t\\n\"/* r3 = 0xe000ed9c [Location of RBAR]. */\n            \"\tstmia r3!, {r6,r7}\t\t\t\t\t\t\t\\n\"/* Write fourth set of RBAR/RLAR registers. */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tldr r3, xMPUCTRLConst\t\t\t\t\t\t\\n\"/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */\n            \"\tldr r4, [r3]\t\t\t\t\t\t\t\t\\n\"/* Read the value of MPU_CTRL. */\n            \"\tmovs r5, #1\t\t\t\t\t\t\t\t\t\\n\"/* r5 = 1. */\n            \"\torrs r4, r5\t\t\t\t\t\t\t\t\t\\n\"/* r4 = r4 | r5 i.e. Set the bit 0 in r4. */\n            \"\tstr r4, [r3]\t\t\t\t\t\t\t\t\\n\"/* Enable MPU. */\n            \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Force memory writes before continuing. */\n        #endif /* configENABLE_MPU */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"\tldmia r2!, {r0, r1, r3, r4}\t\t\t\t\t\\n\"/* Read from stack - r0 = xSecureContext, r1 = PSPLIM, r3 = CONTROL and r4 = LR. */\n            \"\tmsr psplim, r1\t\t\t\t\t\t\t\t\\n\"/* Restore the PSPLIM register value for the task. */\n            \"\tmsr control, r3\t\t\t\t\t\t\t\t\\n\"/* Restore the CONTROL register value for the task. */\n            \"\tmov lr, r4\t\t\t\t\t\t\t\t\t\\n\"/* LR = r4. */\n            \"\tldr r3, xSecureContextConst\t\t\t\t\t\\n\"/* Read the location of xSecureContext i.e. &( xSecureContext ). */\n            \"\tstr r0, [r3]\t\t\t\t\t\t\t\t\\n\"/* Restore the task's xSecureContext. */\n            \"\tcbz r0, restore_ns_context\t\t\t\t\t\\n\"/* If there is no secure context for the task, restore the non-secure context. */\n             \"\tldr r3, pxCurrentTCBConst\t\t\t\t\t\\n\"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n            \"\tldr r1, [r3]\t\t\t\t\t\t\t\t\\n\"/* Read pxCurrentTCB. */\n            \"\tpush {r2, r4}\t\t\t\t\t\t\t\t\\n\"\n            \"\tbl SecureContext_LoadContext\t\t\t\t\\n\"/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */\n            \"\tpop {r2, r4}\t\t\t\t\t\t\t\t\\n\"\n            \"\tmov lr, r4\t\t\t\t\t\t\t\t\t\\n\"/* LR = r4. */\n            \"\tlsls r1, r4, #25\t\t\t\t\t\t\t\\n\"/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\n            \"\tbpl restore_ns_context\t\t\t\t\t\t\\n\"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\n            \"\tmsr psp, r2\t\t\t\t\t\t\t\t\t\\n\"/* Remember the new top of stack for the task. */\n            \"\tbx lr\t\t\t\t\t\t\t\t\t\t\\n\"\n        #else /* configENABLE_MPU */\n            \"\tldmia r2!, {r0, r1, r4}\t\t\t\t\t\t\\n\"/* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */\n            \"\tmsr psplim, r1\t\t\t\t\t\t\t\t\\n\"/* Restore the PSPLIM register value for the task. */\n            \"\tmov lr, r4\t\t\t\t\t\t\t\t\t\\n\"/* LR = r4. */\n            \"\tldr r3, xSecureContextConst\t\t\t\t\t\\n\"/* Read the location of xSecureContext i.e. &( xSecureContext ). */\n            \"\tstr r0, [r3]\t\t\t\t\t\t\t\t\\n\"/* Restore the task's xSecureContext. */\n            \"\tcbz r0, restore_ns_context\t\t\t\t\t\\n\"/* If there is no secure context for the task, restore the non-secure context. */\n            \"\tldr r3, pxCurrentTCBConst\t\t\t\t\t\\n\"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n            \"\tldr r1, [r3]\t\t\t\t\t\t\t\t\\n\"/* Read pxCurrentTCB. */\n            \"\tpush {r2, r4}\t\t\t\t\t\t\t\t\\n\"\n            \"\tbl SecureContext_LoadContext\t\t\t\t\\n\"/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */\n            \"\tpop {r2, r4}\t\t\t\t\t\t\t\t\\n\"\n            \"\tmov lr, r4\t\t\t\t\t\t\t\t\t\\n\"/* LR = r4. */\n            \"\tlsls r1, r4, #25\t\t\t\t\t\t\t\\n\"/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\n            \"\tbpl restore_ns_context\t\t\t\t\t\t\\n\"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\n            \"\tmsr psp, r2\t\t\t\t\t\t\t\t\t\\n\"/* Remember the new top of stack for the task. */\n            \"\tbx lr\t\t\t\t\t\t\t\t\t\t\\n\"\n        #endif /* configENABLE_MPU */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \" restore_ns_context:\t\t\t\t\t\t\t\t\\n\"\n        \"\tadds r2, r2, #16\t\t\t\t\t\t\t\t\\n\"/* Move to the high registers. */\n        \"\tldmia r2!, {r4-r7}\t\t\t\t\t\t\t\t\\n\"/* Restore the high registers that are not automatically restored. */\n        \"\tmov r8, r4\t\t\t\t\t\t\t\t\t\t\\n\"/* r8 = r4. */\n        \"\tmov r9, r5\t\t\t\t\t\t\t\t\t\t\\n\"/* r9 = r5. */\n        \"\tmov r10, r6\t\t\t\t\t\t\t\t\t\t\\n\"/* r10 = r6. */\n        \"\tmov r11, r7\t\t\t\t\t\t\t\t\t\t\\n\"/* r11 = r7. */\n        \"\tmsr psp, r2\t\t\t\t\t\t\t\t\t\t\\n\"/* Remember the new top of stack for the task. */\n        \"\tsubs r2, r2, #32\t\t\t\t\t\t\t\t\\n\"/* Go back to the low registers. */\n        \"\tldmia r2!, {r4-r7}\t\t\t\t\t\t\t\t\\n\"/* Restore the low registers that are not automatically restored. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.align 4\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"pxCurrentTCBConst: .word pxCurrentTCB\t\t\t\t\\n\"\n        \"xSecureContextConst: .word xSecureContext\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"xMPUCTRLConst: .word 0xe000ed94\t\t\t\t\\n\"\n            \"xMAIR0Const: .word 0xe000edc0\t\t\t\t\t\\n\"\n            \"xRNRConst: .word 0xe000ed98\t\t\t\t\t\\n\"\n            \"xRBARConst: .word 0xe000ed9c\t\t\t\t\t\\n\"\n        #endif /* configENABLE_MPU */\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmovs r0, #4\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmov r1, lr\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\ttst r0, r1\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tbeq stacking_used_msp\t\t\t\t\t\t\t\\n\"\n        \"\tmrs r0, psp\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r2, svchandler_address_const\t\t\t\t\\n\"\n        \"\tbx r2\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \" stacking_used_msp:\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrs r0, msp\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r2, svchandler_address_const\t\t\t\t\\n\"\n        \"\tbx r2\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.align 4\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"svchandler_address_const: .word vPortSVCHandler_C\t\\n\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tsvc %0\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Secure context is allocated in the supervisor call. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return. */\n        ::\"i\" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r2, [r0]\t\t\t\t\t\t\t\t\t\\n\"/* The first item in the TCB is the top of the stack. */\n        \"\tldr r1, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* The first item on the stack is the task's xSecureContext. */\n        \"\tcmp r1, #0\t\t\t\t\t\t\t\t\t\t\\n\"/* Raise svc if task's xSecureContext is not NULL. */\n        \"\tbne free_secure_context\t\t\t\t\t\t\t\\n\"/* Branch if r1 != 0. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* There is no secure context (xSecureContext is NULL). */\n        \" free_secure_context:\t\t\t\t\t\t\t\t\\n\"\n        \"\tsvc %0\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Secure context is freed in the supervisor call. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return. */\n        ::\"i\" ( portSVC_FREE_SECURE_CONTEXT ) : \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef PORTMACRO_H\n#define PORTMACRO_H\n\n#ifdef __cplusplus\n    extern \"C\" {\n#endif\n\n#include \"portmacrocommon.h\"\n\n/*------------------------------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the given hardware\n * and compiler.\n *\n * These settings should not be altered.\n *------------------------------------------------------------------------------\n */\n\n/**\n * Architecture specifics.\n */\n#define portARCH_NAME                       \"Cortex-M23\"\n#define portDONT_DISCARD                    __attribute__( ( used ) )\n/*-----------------------------------------------------------*/\n\n#if( configTOTAL_MPU_REGIONS == 16 )\n    #error 16 MPU regions are not yet supported for this port.\n#endif\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Critical section management.\n */\n#define portDISABLE_INTERRUPTS()            __asm volatile ( \" cpsid i \" ::: \"memory\" )\n#define portENABLE_INTERRUPTS()             __asm volatile ( \" cpsie i \" ::: \"memory\" )\n/*-----------------------------------------------------------*/\n\n#ifdef __cplusplus\n    }\n#endif\n\n#endif /* PORTMACRO_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portasm.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Standard includes. */\n#include <stdint.h>\n\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION\n * is defined correctly and privileged functions are placed in correct sections. */\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/* Portasm includes. */\n#include \"portasm.h\"\n\n/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the\n * header files. */\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n#if ( configENABLE_FPU == 1 )\n    #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.\n#endif\n\nvoid vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr  r2, pxCurrentTCBConst2\t\t\t\t\t\t\\n\"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n        \"\tldr  r1, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Read pxCurrentTCB. */\n        \"\tldr  r0, [r1]\t\t\t\t\t\t\t\t\t\\n\"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"\tdmb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Complete outstanding transfers before disabling MPU. */\n            \"\tldr r2, xMPUCTRLConst2\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n            \"\tldr r3, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Read the value of MPU_CTRL. */\n            \"\tmovs r4, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* r4 = 1. */\n            \"\tbics r3, r4\t\t\t\t\t\t\t\t\t\t\\n\"/* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */\n            \"\tstr r3, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Disable MPU. */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tadds r1, #4\t\t\t\t\t\t\t\t\t\t\\n\"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\n            \"\tldr  r4, [r1]\t\t\t\t\t\t\t\t\t\\n\"/* r4 = *r1 i.e. r4 = MAIR0. */\n            \"\tldr  r2, xMAIR0Const2\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000edc0 [Location of MAIR0]. */\n            \"\tstr  r4, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Program MAIR0. */\n            \"\tldr  r2, xRNRConst2\t\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed98 [Location of RNR]. */\n            \"\tadds r1, #4\t\t\t\t\t\t\t\t\t\t\\n\"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\n            \"\tmovs r4, #4\t\t\t\t\t\t\t\t\t\t\\n\"/* r4 = 4. */\n            \"\tstr  r4, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 4. */\n            \"\tldmia r1!, {r5,r6}\t\t\t\t\t\t\t\t\\n\"/* Read first set of RBAR/RLAR from TCB. */\n            \"\tldr  r3, xRBARConst2\t\t\t\t\t\t\t\\n\"/* r3 = 0xe000ed9c [Location of RBAR]. */\n            \"\tstmia r3!, {r5,r6}\t\t\t\t\t\t\t\t\\n\"/* Write first set of RBAR/RLAR registers. */\n            \"\tmovs r4, #5\t\t\t\t\t\t\t\t\t\t\\n\"/* r4 = 5. */\n            \"\tstr  r4, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 5. */\n            \"\tldmia r1!, {r5,r6}\t\t\t\t\t\t\t\t\\n\"/* Read second set of RBAR/RLAR from TCB. */\n            \"\tldr  r3, xRBARConst2\t\t\t\t\t\t\t\\n\"/* r3 = 0xe000ed9c [Location of RBAR]. */\n            \"\tstmia r3!, {r5,r6}\t\t\t\t\t\t\t\t\\n\"/* Write second set of RBAR/RLAR registers. */\n            \"\tmovs r4, #6\t\t\t\t\t\t\t\t\t\t\\n\"/* r4 = 6. */\n            \"\tstr  r4, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 6. */\n            \"\tldmia r1!, {r5,r6}\t\t\t\t\t\t\t\t\\n\"/* Read third set of RBAR/RLAR from TCB. */\n            \"\tldr  r3, xRBARConst2\t\t\t\t\t\t\t\\n\"/* r3 = 0xe000ed9c [Location of RBAR]. */\n            \"\tstmia r3!, {r5,r6}\t\t\t\t\t\t\t\t\\n\"/* Write third set of RBAR/RLAR registers. */\n            \"\tmovs r4, #7\t\t\t\t\t\t\t\t\t\t\\n\"/* r4 = 7. */\n            \"\tstr  r4, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 7. */\n            \"\tldmia r1!, {r5,r6}\t\t\t\t\t\t\t\t\\n\"/* Read fourth set of RBAR/RLAR from TCB. */\n            \"\tldr  r3, xRBARConst2\t\t\t\t\t\t\t\\n\"/* r3 = 0xe000ed9c [Location of RBAR]. */\n            \"\tstmia r3!, {r5,r6}\t\t\t\t\t\t\t\t\\n\"/* Write fourth set of RBAR/RLAR registers. */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tldr r2, xMPUCTRLConst2\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n            \"\tldr r3, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Read the value of MPU_CTRL. */\n            \"\tmovs r4, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* r4 = 1. */\n            \"\torrs r3, r4\t\t\t\t\t\t\t\t\t\t\\n\"/* r3 = r3 | r4 i.e. Set the bit 0 in r3. */\n            \"\tstr r3, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Enable MPU. */\n            \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Force memory writes before continuing. */\n        #endif /* configENABLE_MPU */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"\tldm  r0!, {r1-r3}\t\t\t\t\t\t\t\t\\n\"/* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */\n            \"\tmsr  psplim, r1\t\t\t\t\t\t\t\t\t\\n\"/* Set this task's PSPLIM value. */\n            \"\tmsr  control, r2\t\t\t\t\t\t\t\t\\n\"/* Set this task's CONTROL value. */\n            \"\tadds r0, #32\t\t\t\t\t\t\t\t\t\\n\"/* Discard everything up to r0. */\n            \"\tmsr  psp, r0\t\t\t\t\t\t\t\t\t\\n\"/* This is now the new top of stack to use in the task. */\n            \"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tbx   r3\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Finally, branch to EXC_RETURN. */\n        #else /* configENABLE_MPU */\n            \"\tldm  r0!, {r1-r2}\t\t\t\t\t\t\t\t\\n\"/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */\n            \"\tmsr  psplim, r1\t\t\t\t\t\t\t\t\t\\n\"/* Set this task's PSPLIM value. */\n            \"\tmovs r1, #2\t\t\t\t\t\t\t\t\t\t\\n\"/* r1 = 2. */\n            \"\tmsr  CONTROL, r1\t\t\t\t\t\t\t\t\\n\"/* Switch to use PSP in the thread mode. */\n            \"\tadds r0, #32\t\t\t\t\t\t\t\t\t\\n\"/* Discard everything up to r0. */\n            \"\tmsr  psp, r0\t\t\t\t\t\t\t\t\t\\n\"/* This is now the new top of stack to use in the task. */\n            \"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tbx   r2\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Finally, branch to EXC_RETURN. */\n        #endif /* configENABLE_MPU */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.align 4\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"pxCurrentTCBConst2: .word pxCurrentTCB\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"xMPUCTRLConst2: .word 0xe000ed94\t\t\t\t\t\\n\"\n            \"xMAIR0Const2: .word 0xe000edc0\t\t\t\t\t\t\\n\"\n            \"xRNRConst2: .word 0xe000ed98\t\t\t\t\t\t\\n\"\n            \"xRBARConst2: .word 0xe000ed9c\t\t\t\t\t\t\\n\"\n        #endif /* configENABLE_MPU */\n    );\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrs r0, control\t\t\t\t\t\t\t\t\t\\n\"/* r0 = CONTROL. */\n        \"\tmovs r1, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* r1 = 1. */\n        \"\ttst r0, r1\t\t\t\t\t\t\t\t\t\t\\n\"/* Perform r0 & r1 (bitwise AND) and update the conditions flag. */\n        \"\tbeq running_privileged\t\t\t\t\t\t\t\\n\"/* If the result of previous AND operation was 0, branch. */\n        \"\tmovs r0, #0\t\t\t\t\t\t\t\t\t\t\\n\"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return. */\n        \" running_privileged:\t\t\t\t\t\t\t\t\\n\"\n        \"\tmovs r0, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return. */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.align 4\t\t\t\t\t\t\t\t\t\t\\n\"\n        ::: \"r0\", \"r1\", \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrs  r0, control\t\t\t\t\t\t\t\t\\n\"/* Read the CONTROL register. */\n        \"\tmovs r1, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* r1 = 1. */\n        \"\tbics r0, r1\t\t\t\t\t\t\t\t\t\t\\n\"/* Clear the bit 0. */\n        \"\tmsr  control, r0\t\t\t\t\t\t\t\t\\n\"/* Write back the new CONTROL value. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return to the caller. */\n        ::: \"r0\", \"r1\", \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vResetPrivilege( void ) /* __attribute__ (( naked )) */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrs r0, control\t\t\t\t\t\t\t\t\t\\n\"/* r0 = CONTROL. */\n        \"\tmovs r1, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* r1 = 1. */\n        \"\torrs r0, r1\t\t\t\t\t\t\t\t\t\t\\n\"/* r0 = r0 | r1. */\n        \"\tmsr control, r0\t\t\t\t\t\t\t\t\t\\n\"/* CONTROL = r0. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return to the caller. */\n        ::: \"r0\", \"r1\", \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r0, xVTORConst\t\t\t\t\t\t\t\t\\n\"/* Use the NVIC offset register to locate the stack. */\n        \"\tldr r0, [r0]\t\t\t\t\t\t\t\t\t\\n\"/* Read the VTOR register which gives the address of vector table. */\n        \"\tldr r0, [r0]\t\t\t\t\t\t\t\t\t\\n\"/* The first entry in vector table is stack pointer. */\n        \"\tmsr msp, r0\t\t\t\t\t\t\t\t\t\t\\n\"/* Set the MSP back to the start of the stack. */\n        \"\tcpsie i\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Globally enable interrupts. */\n        \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tsvc %0\t\t\t\t\t\t\t\t\t\t\t\\n\"/* System call to start the first task. */\n        \"\tnop\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"   .align 4\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"xVTORConst: .word 0xe000ed08\t\t\t\t\t\t\\n\"\n        ::\"i\" ( portSVC_START_SCHEDULER ) : \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nuint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrs r0, PRIMASK\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tcpsid i\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        ::: \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmsr PRIMASK, r0\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        ::: \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrs r0, psp\t\t\t\t\t\t\t\t\t\t\\n\"/* Read PSP in r0. */\n        \"\tldr r2, pxCurrentTCBConst\t\t\t\t\t\t\\n\"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n        \"\tldr r1, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Read pxCurrentTCB. */\n        #if ( configENABLE_MPU == 1 )\n            \"\tsubs r0, r0, #44\t\t\t\t\t\t\t\t\\n\"/* Make space for PSPLIM, CONTROL, LR and the remaining registers on the stack. */\n            \"\tstr r0, [r1]\t\t\t\t\t\t\t\t\t\\n\"/* Save the new top of stack in TCB. */\n            \"\tmrs r1, psplim\t\t\t\t\t\t\t\t\t\\n\"/* r1 = PSPLIM. */\n            \"\tmrs r2, control\t\t\t\t\t\t\t\t\t\\n\"/* r2 = CONTROL. */\n            \"\tmov r3, lr\t\t\t\t\t\t\t\t\t\t\\n\"/* r3 = LR/EXC_RETURN. */\n            \"\tstmia r0!, {r1-r7}\t\t\t\t\t\t\t\t\\n\"/* Store on the stack - PSPLIM, CONTROL, LR and low registers that are not automatically saved. */\n            \"\tmov r4, r8\t\t\t\t\t\t\t\t\t\t\\n\"/* r4 = r8. */\n            \"\tmov r5, r9\t\t\t\t\t\t\t\t\t\t\\n\"/* r5 = r9. */\n            \"\tmov r6, r10\t\t\t\t\t\t\t\t\t\t\\n\"/* r6 = r10. */\n            \"\tmov r7, r11\t\t\t\t\t\t\t\t\t\t\\n\"/* r7 = r11. */\n            \"\tstmia r0!, {r4-r7}\t\t\t\t\t\t\t\t\\n\"/* Store the high registers that are not saved automatically. */\n        #else /* configENABLE_MPU */\n            \"\tsubs r0, r0, #40\t\t\t\t\t\t\t\t\\n\"/* Make space for PSPLIM, LR and the remaining registers on the stack. */\n            \"\tstr r0, [r1]\t\t\t\t\t\t\t\t\t\\n\"/* Save the new top of stack in TCB. */\n            \"\tmrs r2, psplim\t\t\t\t\t\t\t\t\t\\n\"/* r2 = PSPLIM. */\n            \"\tmov r3, lr\t\t\t\t\t\t\t\t\t\t\\n\"/* r3 = LR/EXC_RETURN. */\n            \"\tstmia r0!, {r2-r7}\t\t\t\t\t\t\t\t\\n\"/* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */\n            \"\tmov r4, r8\t\t\t\t\t\t\t\t\t\t\\n\"/* r4 = r8. */\n            \"\tmov r5, r9\t\t\t\t\t\t\t\t\t\t\\n\"/* r5 = r9. */\n            \"\tmov r6, r10\t\t\t\t\t\t\t\t\t\t\\n\"/* r6 = r10. */\n            \"\tmov r7, r11\t\t\t\t\t\t\t\t\t\t\\n\"/* r7 = r11. */\n            \"\tstmia r0!, {r4-r7}\t\t\t\t\t\t\t\t\\n\"/* Store the high registers that are not saved automatically. */\n        #endif /* configENABLE_MPU */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tcpsid i\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tbl vTaskSwitchContext\t\t\t\t\t\t\t\\n\"\n        \"\tcpsie i\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r2, pxCurrentTCBConst\t\t\t\t\t\t\\n\"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n        \"\tldr r1, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Read pxCurrentTCB. */\n        \"\tldr r0, [r1]\t\t\t\t\t\t\t\t\t\\n\"/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"\tdmb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Complete outstanding transfers before disabling MPU. */\n            \"\tldr r2, xMPUCTRLConst\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n            \"\tldr r3, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Read the value of MPU_CTRL. */\n            \"\tmovs r4, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* r4 = 1. */\n            \"\tbics r3, r4\t\t\t\t\t\t\t\t\t\t\\n\"/* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */\n            \"\tstr r3, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Disable MPU. */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tadds r1, #4\t\t\t\t\t\t\t\t\t\t\\n\"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\n            \"\tldr  r4, [r1]\t\t\t\t\t\t\t\t\t\\n\"/* r4 = *r1 i.e. r4 = MAIR0. */\n            \"\tldr  r2, xMAIR0Const\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000edc0 [Location of MAIR0]. */\n            \"\tstr  r4, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Program MAIR0. */\n            \"\tldr  r2, xRNRConst\t\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed98 [Location of RNR]. */\n            \"\tadds r1, #4\t\t\t\t\t\t\t\t\t\t\\n\"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\n            \"\tmovs r4, #4\t\t\t\t\t\t\t\t\t\t\\n\"/* r4 = 4. */\n            \"\tstr  r4, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 4. */\n            \"\tldmia r1!, {r5,r6}\t\t\t\t\t\t\t\t\\n\"/* Read first set of RBAR/RLAR from TCB. */\n            \"\tldr  r3, xRBARConst\t\t\t\t\t\t\t\t\\n\"/* r3 = 0xe000ed9c [Location of RBAR]. */\n            \"\tstmia r3!, {r5,r6}\t\t\t\t\t\t\t\t\\n\"/* Write first set of RBAR/RLAR registers. */\n            \"\tmovs r4, #5\t\t\t\t\t\t\t\t\t\t\\n\"/* r4 = 5. */\n            \"\tstr  r4, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 5. */\n            \"\tldmia r1!, {r5,r6}\t\t\t\t\t\t\t\t\\n\"/* Read second set of RBAR/RLAR from TCB. */\n            \"\tldr  r3, xRBARConst\t\t\t\t\t\t\t\t\\n\"/* r3 = 0xe000ed9c [Location of RBAR]. */\n            \"\tstmia r3!, {r5,r6}\t\t\t\t\t\t\t\t\\n\"/* Write second set of RBAR/RLAR registers. */\n            \"\tmovs r4, #6\t\t\t\t\t\t\t\t\t\t\\n\"/* r4 = 6. */\n            \"\tstr  r4, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 6. */\n            \"\tldmia r1!, {r5,r6}\t\t\t\t\t\t\t\t\\n\"/* Read third set of RBAR/RLAR from TCB. */\n            \"\tldr  r3, xRBARConst\t\t\t\t\t\t\t\t\\n\"/* r3 = 0xe000ed9c [Location of RBAR]. */\n            \"\tstmia r3!, {r5,r6}\t\t\t\t\t\t\t\t\\n\"/* Write third set of RBAR/RLAR registers. */\n            \"\tmovs r4, #7\t\t\t\t\t\t\t\t\t\t\\n\"/* r4 = 7. */\n            \"\tstr  r4, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 7. */\n            \"\tldmia r1!, {r5,r6}\t\t\t\t\t\t\t\t\\n\"/* Read fourth set of RBAR/RLAR from TCB. */\n            \"\tldr  r3, xRBARConst\t\t\t\t\t\t\t\t\\n\"/* r3 = 0xe000ed9c [Location of RBAR]. */\n            \"\tstmia r3!, {r5,r6}\t\t\t\t\t\t\t\t\\n\"/* Write fourth set of RBAR/RLAR registers. */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tldr r2, xMPUCTRLConst\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n            \"\tldr r3, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Read the value of MPU_CTRL. */\n            \"\tmovs r4, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* r4 = 1. */\n            \"\torrs r3, r4\t\t\t\t\t\t\t\t\t\t\\n\"/* r3 = r3 | r4 i.e. Set the bit 0 in r3. */\n            \"\tstr r3, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Enable MPU. */\n            \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Force memory writes before continuing. */\n        #endif /* configENABLE_MPU */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"\tadds r0, r0, #28\t\t\t\t\t\t\t\t\\n\"/* Move to the high registers. */\n            \"\tldmia r0!, {r4-r7}\t\t\t\t\t\t\t\t\\n\"/* Restore the high registers that are not automatically restored. */\n            \"\tmov r8, r4\t\t\t\t\t\t\t\t\t\t\\n\"/* r8 = r4. */\n            \"\tmov r9, r5\t\t\t\t\t\t\t\t\t\t\\n\"/* r9 = r5. */\n            \"\tmov r10, r6\t\t\t\t\t\t\t\t\t\t\\n\"/* r10 = r6. */\n            \"\tmov r11, r7\t\t\t\t\t\t\t\t\t\t\\n\"/* r11 = r7. */\n            \"\tmsr psp, r0\t\t\t\t\t\t\t\t\t\t\\n\"/* Remember the new top of stack for the task. */\n            \"\tsubs r0, r0, #44\t\t\t\t\t\t\t\t\\n\"/* Move to the starting of the saved context. */\n            \"\tldmia r0!, {r1-r7}\t\t\t\t\t\t\t\t\\n\"/* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r7 restored. */\n            \"\tmsr psplim, r1\t\t\t\t\t\t\t\t\t\\n\"/* Restore the PSPLIM register value for the task. */\n            \"\tmsr control, r2\t\t\t\t\t\t\t\t\t\\n\"/* Restore the CONTROL register value for the task. */\n            \"\tbx r3\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #else /* configENABLE_MPU */\n            \"\tadds r0, r0, #24\t\t\t\t\t\t\t\t\\n\"/* Move to the high registers. */\n            \"\tldmia r0!, {r4-r7}\t\t\t\t\t\t\t\t\\n\"/* Restore the high registers that are not automatically restored. */\n            \"\tmov r8, r4\t\t\t\t\t\t\t\t\t\t\\n\"/* r8 = r4. */\n            \"\tmov r9, r5\t\t\t\t\t\t\t\t\t\t\\n\"/* r9 = r5. */\n            \"\tmov r10, r6\t\t\t\t\t\t\t\t\t\t\\n\"/* r10 = r6. */\n            \"\tmov r11, r7\t\t\t\t\t\t\t\t\t\t\\n\"/* r11 = r7. */\n            \"\tmsr psp, r0\t\t\t\t\t\t\t\t\t\t\\n\"/* Remember the new top of stack for the task. */\n            \"\tsubs r0, r0, #40\t\t\t\t\t\t\t\t\\n\"/* Move to the starting of the saved context. */\n            \"\tldmia r0!, {r2-r7}\t\t\t\t\t\t\t\t\\n\"/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */\n            \"\tmsr psplim, r2\t\t\t\t\t\t\t\t\t\\n\"/* Restore the PSPLIM register value for the task. */\n            \"\tbx r3\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #endif /* configENABLE_MPU */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.align 4\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"pxCurrentTCBConst: .word pxCurrentTCB\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"xMPUCTRLConst: .word 0xe000ed94\t\t\t\t\t\\n\"\n            \"xMAIR0Const: .word 0xe000edc0\t\t\t\t\t\t\\n\"\n            \"xRNRConst: .word 0xe000ed98\t\t\t\t\t\t\\n\"\n            \"xRBARConst: .word 0xe000ed9c\t\t\t\t\t\t\\n\"\n        #endif /* configENABLE_MPU */\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmovs r0, #4\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmov r1, lr\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\ttst r0, r1\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tbeq stacking_used_msp\t\t\t\t\t\t\t\\n\"\n        \"\tmrs r0, psp\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r2, svchandler_address_const\t\t\t\t\\n\"\n        \"\tbx r2\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \" stacking_used_msp:\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrs r0, msp\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r2, svchandler_address_const\t\t\t\t\\n\"\n        \"\tbx r2\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.align 4\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"svchandler_address_const: .word vPortSVCHandler_C\t\\n\"\n    );\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef PORTMACRO_H\n#define PORTMACRO_H\n\n#ifdef __cplusplus\n    extern \"C\" {\n#endif\n\n#include \"portmacrocommon.h\"\n\n/*------------------------------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the given hardware\n * and compiler.\n *\n * These settings should not be altered.\n *------------------------------------------------------------------------------\n */\n\n/**\n * Architecture specifics.\n */\n#define portARCH_NAME                       \"Cortex-M23\"\n#define portDONT_DISCARD                    __attribute__( ( used ) )\n/*-----------------------------------------------------------*/\n\n#if( configTOTAL_MPU_REGIONS == 16 )\n    #error 16 MPU regions are not yet supported for this port.\n#endif\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Critical section management.\n */\n#define portDISABLE_INTERRUPTS()            __asm volatile ( \" cpsid i \" ::: \"memory\" )\n#define portENABLE_INTERRUPTS()             __asm volatile ( \" cpsie i \" ::: \"memory\" )\n/*-----------------------------------------------------------*/\n\n#ifdef __cplusplus\n    }\n#endif\n\n#endif /* PORTMACRO_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Standard includes. */\n#include <stdint.h>\n\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION\n * is defined correctly and privileged functions are placed in correct sections. */\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/* Portasm includes. */\n#include \"portasm.h\"\n\n/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the\n * header files. */\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\nvoid vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr  r2, pxCurrentTCBConst2\t\t\t\t\t\t\\n\"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n        \"\tldr  r3, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Read pxCurrentTCB. */\n        \"\tldr  r0, [r3]\t\t\t\t\t\t\t\t\t\\n\"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"\tdmb\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Complete outstanding transfers before disabling MPU. */\n            \"\tldr r2, xMPUCTRLConst2\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n            \"\tldr r4, [r2]\t\t\t\t\t\t\t\t\\n\"/* Read the value of MPU_CTRL. */\n            \"\tbic r4, #1\t\t\t\t\t\t\t\t\t\\n\"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\n            \"\tstr r4, [r2]\t\t\t\t\t\t\t\t\\n\"/* Disable MPU. */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tadds r3, #4\t\t\t\t\t\t\t\t\t\\n\"/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\n            \"\tldr  r4, [r3]\t\t\t\t\t\t\t\t\\n\"/* r4 = *r3 i.e. r4 = MAIR0. */\n            \"\tldr  r2, xMAIR0Const2\t\t\t\t\t\t\\n\"/* r2 = 0xe000edc0 [Location of MAIR0]. */\n            \"\tstr  r4, [r2]\t\t\t\t\t\t\t\t\\n\"/* Program MAIR0. */\n            \"\tldr  r2, xRNRConst2\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed98 [Location of RNR]. */\n            \"\tmovs r4, #4\t\t\t\t\t\t\t\t\t\\n\"/* r4 = 4. */\n            \"\tstr  r4, [r2]\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 4. */\n            \"\tadds r3, #4\t\t\t\t\t\t\t\t\t\\n\"/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */\n            \"\tldr  r2, xRBARConst2\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed9c [Location of RBAR]. */\n            \"\tldmia r3!, {r4-r11}\t\t\t\t\t\t\t\\n\"/* Read 4 set of RBAR/RLAR registers from TCB. */\n            \"\tstmia r2!, {r4-r11}\t\t\t\t\t\t\t\\n\"/* Write 4 set of RBAR/RLAR registers using alias registers. */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configTOTAL_MPU_REGIONS == 16 )\n            \"\tldr  r2, xRNRConst2\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed98 [Location of RNR]. */\n            \"\tmovs r4, #8\t\t\t\t\t\t\t\t\t\\n\"/* r4 = 8. */\n            \"\tstr  r4, [r2]\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 8. */\n            \"\tldr  r2, xRBARConst2\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed9c [Location of RBAR]. */\n            \"\tldmia r3!, {r4-r11}\t\t\t\t\t\t\t\\n\"/* Read 4 set of RBAR/RLAR registers from TCB. */\n            \"\tstmia r2!, {r4-r11}\t\t\t\t\t\t\t\\n\"/* Write 4 set of RBAR/RLAR registers using alias registers. */\n            \"\tldr  r2, xRNRConst2\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed98 [Location of RNR]. */\n            \"\tmovs r4, #12\t\t\t\t\t\t\t\t\\n\"/* r4 = 12. */\n            \"\tstr  r4, [r2]\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 12. */\n            \"\tldr  r2, xRBARConst2\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed9c [Location of RBAR]. */\n            \"\tldmia r3!, {r4-r11}\t\t\t\t\t\t\t\\n\"/* Read 4 set of RBAR/RLAR registers from TCB. */\n            \"\tstmia r2!, {r4-r11}\t\t\t\t\t\t\t\\n\"/* Write 4 set of RBAR/RLAR registers using alias registers. */\n        #endif /* configTOTAL_MPU_REGIONS == 16 */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tldr r2, xMPUCTRLConst2\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n            \"\tldr r4, [r2]\t\t\t\t\t\t\t\t\\n\"/* Read the value of MPU_CTRL. */\n            \"\torr r4, #1\t\t\t\t\t\t\t\t\t\\n\"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\n            \"\tstr r4, [r2]\t\t\t\t\t\t\t\t\\n\"/* Enable MPU. */\n            \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Force memory writes before continuing. */\n        #endif /* configENABLE_MPU */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"\tldm  r0!, {r1-r4}\t\t\t\t\t\t\t\\n\"/* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */\n            \"\tldr  r5, xSecureContextConst2\t\t\t\t\\n\"\n            \"\tstr  r1, [r5]\t\t\t\t\t\t\t\t\\n\"/* Set xSecureContext to this task's value for the same. */\n            \"\tmsr  psplim, r2\t\t\t\t\t\t\t\t\\n\"/* Set this task's PSPLIM value. */\n            \"\tmsr  control, r3\t\t\t\t\t\t\t\\n\"/* Set this task's CONTROL value. */\n            \"\tadds r0, #32\t\t\t\t\t\t\t\t\\n\"/* Discard everything up to r0. */\n            \"\tmsr  psp, r0\t\t\t\t\t\t\t\t\\n\"/* This is now the new top of stack to use in the task. */\n            \"\tisb\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tmov  r0, #0\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tmsr  basepri, r0\t\t\t\t\t\t\t\\n\"/* Ensure that interrupts are enabled when the first task starts. */\n            \"\tbx   r4\t\t\t\t\t\t\t\t\t\t\\n\"/* Finally, branch to EXC_RETURN. */\n        #else /* configENABLE_MPU */\n            \"\tldm  r0!, {r1-r3}\t\t\t\t\t\t\t\\n\"/* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */\n            \"\tldr  r4, xSecureContextConst2\t\t\t\t\\n\"\n            \"\tstr  r1, [r4]\t\t\t\t\t\t\t\t\\n\"/* Set xSecureContext to this task's value for the same. */\n            \"\tmsr  psplim, r2\t\t\t\t\t\t\t\t\\n\"/* Set this task's PSPLIM value. */\n            \"\tmovs r1, #2\t\t\t\t\t\t\t\t\t\\n\"/* r1 = 2. */\n            \"\tmsr  CONTROL, r1\t\t\t\t\t\t\t\\n\"/* Switch to use PSP in the thread mode. */\n            \"\tadds r0, #32\t\t\t\t\t\t\t\t\\n\"/* Discard everything up to r0. */\n            \"\tmsr  psp, r0\t\t\t\t\t\t\t\t\\n\"/* This is now the new top of stack to use in the task. */\n            \"\tisb\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tmov  r0, #0\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tmsr  basepri, r0\t\t\t\t\t\t\t\\n\"/* Ensure that interrupts are enabled when the first task starts. */\n            \"\tbx   r3\t\t\t\t\t\t\t\t\t\t\\n\"/* Finally, branch to EXC_RETURN. */\n        #endif /* configENABLE_MPU */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.align 4\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"pxCurrentTCBConst2: .word pxCurrentTCB\t\t\t\t\\n\"\n        \"xSecureContextConst2: .word xSecureContext\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"xMPUCTRLConst2: .word 0xe000ed94\t\t\t\t\\n\"\n            \"xMAIR0Const2: .word 0xe000edc0\t\t\t\t\t\\n\"\n            \"xRNRConst2: .word 0xe000ed98\t\t\t\t\t\\n\"\n            \"xRBARConst2: .word 0xe000ed9c\t\t\t\t\t\\n\"\n        #endif /* configENABLE_MPU */\n    );\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrs r0, control\t\t\t\t\t\t\t\t\t\\n\"/* r0 = CONTROL. */\n        \"\ttst r0, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\n        \"\tite ne\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmovne r0, #0\t\t\t\t\t\t\t\t\t\\n\"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\n        \"\tmoveq r0, #1\t\t\t\t\t\t\t\t\t\\n\"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return. */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.align 4\t\t\t\t\t\t\t\t\t\t\\n\"\n        ::: \"r0\", \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrs r0, control\t\t\t\t\t\t\t\t\t\\n\"/* Read the CONTROL register. */\n        \"\tbic r0, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* Clear the bit 0. */\n        \"\tmsr control, r0\t\t\t\t\t\t\t\t\t\\n\"/* Write back the new CONTROL value. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return to the caller. */\n        ::: \"r0\", \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vResetPrivilege( void ) /* __attribute__ (( naked )) */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrs r0, control\t\t\t\t\t\t\t\t\t\\n\"/* r0 = CONTROL. */\n        \"\torr r0, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* r0 = r0 | 1. */\n        \"\tmsr control, r0\t\t\t\t\t\t\t\t\t\\n\"/* CONTROL = r0. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return to the caller. */\n        ::: \"r0\", \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r0, xVTORConst\t\t\t\t\t\t\t\t\\n\"/* Use the NVIC offset register to locate the stack. */\n        \"\tldr r0, [r0]\t\t\t\t\t\t\t\t\t\\n\"/* Read the VTOR register which gives the address of vector table. */\n        \"\tldr r0, [r0]\t\t\t\t\t\t\t\t\t\\n\"/* The first entry in vector table is stack pointer. */\n        \"\tmsr msp, r0\t\t\t\t\t\t\t\t\t\t\\n\"/* Set the MSP back to the start of the stack. */\n        \"\tcpsie i\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Globally enable interrupts. */\n        \"\tcpsie f\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tsvc %0\t\t\t\t\t\t\t\t\t\t\t\\n\"/* System call to start the first task. */\n        \"\tnop\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"   .align 4\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"xVTORConst: .word 0xe000ed08\t\t\t\t\t\t\\n\"\n        ::\"i\" ( portSVC_START_SCHEDULER ) : \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nuint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrs r0, basepri\t\t\t\t\t\t\t\t\t\\n\"/* r0 = basepri. Return original basepri value. */\n        \"\tmov r1, %0\t\t\t\t\t\t\t\t\t\t\\n\"/* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */\n        \"\tmsr basepri, r1\t\t\t\t\t\t\t\t\t\\n\"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */\n        \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return. */\n        ::\"i\" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmsr basepri, r0\t\t\t\t\t\t\t\t\t\\n\"/* basepri = ulMask. */\n        \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return. */\n        ::: \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.extern SecureContext_SaveContext\t\t\t\t\\n\"\n        \"\t.extern SecureContext_LoadContext\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r3, xSecureContextConst\t\t\t\t\t\t\\n\"/* Read the location of xSecureContext i.e. &( xSecureContext ). */\n        \"\tldr r0, [r3]\t\t\t\t\t\t\t\t\t\\n\"/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */\n        \"\tldr r3, pxCurrentTCBConst\t\t\t\t\t\t\\n\"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n        \"\tldr r1, [r3]\t\t\t\t\t\t\t\t\t\\n\"/* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */\n        \"\tmrs r2, psp\t\t\t\t\t\t\t\t\t\t\\n\"/* Read PSP in r2. */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tcbz r0, save_ns_context\t\t\t\t\t\t\t\\n\"/* No secure context to save. */\n        \"\tpush {r0-r2, r14}\t\t\t\t\t\t\t\t\\n\"\n        \"\tbl SecureContext_SaveContext\t\t\t\t\t\\n\"/* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */\n        \"\tpop {r0-r3}\t\t\t\t\t\t\t\t\t\t\\n\"/* LR is now in r3. */\n        \"\tmov lr, r3\t\t\t\t\t\t\t\t\t\t\\n\"/* LR = r3. */\n        \"\tlsls r1, r3, #25\t\t\t\t\t\t\t\t\\n\"/* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\n        \"\tbpl save_ns_context\t\t\t\t\t\t\t\t\\n\"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r3, pxCurrentTCBConst\t\t\t\t\t\t\\n\"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n        \"\tldr r1, [r3]\t\t\t\t\t\t\t\t\t\\n\"/* Read pxCurrentTCB.*/\n        #if ( configENABLE_MPU == 1 )\n            \"\tsubs r2, r2, #16\t\t\t\t\t\t\t\\n\"/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */\n            \"\tstr r2, [r1]\t\t\t\t\t\t\t\t\\n\"/* Save the new top of stack in TCB. */\n            \"\tmrs r1, psplim\t\t\t\t\t\t\t\t\\n\"/* r1 = PSPLIM. */\n            \"\tmrs r3, control\t\t\t\t\t\t\t\t\\n\"/* r3 = CONTROL. */\n            \"\tmov r4, lr\t\t\t\t\t\t\t\t\t\\n\"/* r4 = LR/EXC_RETURN. */\n            \"\tstmia r2!, {r0, r1, r3, r4}\t\t\t\t\t\\n\"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\n        #else /* configENABLE_MPU */\n            \"\tsubs r2, r2, #12\t\t\t\t\t\t\t\\n\"/* Make space for xSecureContext, PSPLIM and LR on the stack. */\n            \"\tstr r2, [r1]\t\t\t\t\t\t\t\t\\n\"/* Save the new top of stack in TCB. */\n            \"\tmrs r1, psplim\t\t\t\t\t\t\t\t\\n\"/* r1 = PSPLIM. */\n            \"\tmov r3, lr\t\t\t\t\t\t\t\t\t\\n\"/* r3 = LR/EXC_RETURN. */\n            \"\tstmia r2!, {r0, r1, r3}\t\t\t\t\t\t\\n\"/* Store xSecureContext, PSPLIM and LR on the stack. */\n        #endif /* configENABLE_MPU */\n        \"\tb select_next_task\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \" save_ns_context:\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r3, pxCurrentTCBConst\t\t\t\t\t\t\\n\"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n        \"\tldr r1, [r3]\t\t\t\t\t\t\t\t\t\\n\"/* Read pxCurrentTCB. */\n        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )\n            \"\ttst lr, #0x10\t\t\t\t\t\t\t\t\\n\"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */\n            \"\tit eq\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tvstmdbeq r2!, {s16-s31}\t\t\t\t\t\t\\n\"/* Store the additional FP context registers which are not saved automatically. */\n        #endif /* configENABLE_FPU || configENABLE_MVE */\n        #if ( configENABLE_MPU == 1 )\n            \"\tsubs r2, r2, #48\t\t\t\t\t\t\t\\n\"/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */\n            \"\tstr r2, [r1]\t\t\t\t\t\t\t\t\\n\"/* Save the new top of stack in TCB. */\n            \"\tadds r2, r2, #16\t\t\t\t\t\t\t\\n\"/* r2 = r2 + 16. */\n            \"\tstm r2, {r4-r11}\t\t\t\t\t\t\t\\n\"/* Store the registers that are not saved automatically. */\n            \"\tmrs r1, psplim\t\t\t\t\t\t\t\t\\n\"/* r1 = PSPLIM. */\n            \"\tmrs r3, control\t\t\t\t\t\t\t\t\\n\"/* r3 = CONTROL. */\n            \"\tmov r4, lr\t\t\t\t\t\t\t\t\t\\n\"/* r4 = LR/EXC_RETURN. */\n            \"\tsubs r2, r2, #16\t\t\t\t\t\t\t\\n\"/* r2 = r2 - 16. */\n            \"\tstmia r2!, {r0, r1, r3, r4}\t\t\t\t\t\\n\"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\n        #else /* configENABLE_MPU */\n            \"\tsubs r2, r2, #44\t\t\t\t\t\t\t\\n\"/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */\n            \"\tstr r2, [r1]\t\t\t\t\t\t\t\t\\n\"/* Save the new top of stack in TCB. */\n            \"\tadds r2, r2, #12\t\t\t\t\t\t\t\\n\"/* r2 = r2 + 12. */\n            \"\tstm r2, {r4-r11}\t\t\t\t\t\t\t\\n\"/* Store the registers that are not saved automatically. */\n            \"\tmrs r1, psplim\t\t\t\t\t\t\t\t\\n\"/* r1 = PSPLIM. */\n            \"\tmov r3, lr\t\t\t\t\t\t\t\t\t\\n\"/* r3 = LR/EXC_RETURN. */\n            \"\tsubs r2, r2, #12\t\t\t\t\t\t\t\\n\"/* r2 = r2 - 12. */\n            \"\tstmia r2!, {r0, r1, r3}\t\t\t\t\t\t\\n\"/* Store xSecureContext, PSPLIM and LR on the stack. */\n        #endif /* configENABLE_MPU */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \" select_next_task:\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmov r0, %0\t\t\t\t\t\t\t\t\t\t\\n\"/* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */\n        \"\tmsr basepri, r0\t\t\t\t\t\t\t\t\t\\n\"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */\n        \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tbl vTaskSwitchContext\t\t\t\t\t\t\t\\n\"\n        \"\tmov r0, #0\t\t\t\t\t\t\t\t\t\t\\n\"/* r0 = 0. */\n        \"\tmsr basepri, r0\t\t\t\t\t\t\t\t\t\\n\"/* Enable interrupts. */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r3, pxCurrentTCBConst\t\t\t\t\t\t\\n\"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n        \"\tldr r1, [r3]\t\t\t\t\t\t\t\t\t\\n\"/* Read pxCurrentTCB. */\n        \"\tldr r2, [r1]\t\t\t\t\t\t\t\t\t\\n\"/* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"\tdmb\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Complete outstanding transfers before disabling MPU. */\n            \"\tldr r3, xMPUCTRLConst\t\t\t\t\t\t\\n\"/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */\n            \"\tldr r4, [r3]\t\t\t\t\t\t\t\t\\n\"/* Read the value of MPU_CTRL. */\n            \"\tbic r4, #1\t\t\t\t\t\t\t\t\t\\n\"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\n            \"\tstr r4, [r3]\t\t\t\t\t\t\t\t\\n\"/* Disable MPU. */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tadds r1, #4\t\t\t\t\t\t\t\t\t\\n\"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\n            \"\tldr r4, [r1]\t\t\t\t\t\t\t\t\\n\"/* r4 = *r1 i.e. r4 = MAIR0. */\n            \"\tldr r3, xMAIR0Const\t\t\t\t\t\t\t\\n\"/* r3 = 0xe000edc0 [Location of MAIR0]. */\n            \"\tstr r4, [r3]\t\t\t\t\t\t\t\t\\n\"/* Program MAIR0. */\n            \"\tldr r3, xRNRConst\t\t\t\t\t\t\t\\n\"/* r3 = 0xe000ed98 [Location of RNR]. */\n            \"\tmovs r4, #4\t\t\t\t\t\t\t\t\t\\n\"/* r4 = 4. */\n            \"\tstr r4, [r3]\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 4. */\n            \"\tadds r1, #4\t\t\t\t\t\t\t\t\t\\n\"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\n            \"\tldr r3, xRBARConst\t\t\t\t\t\t\t\\n\"/* r3 = 0xe000ed9c [Location of RBAR]. */\n            \"\tldmia r1!, {r4-r11}\t\t\t\t\t\t\t\\n\"/* Read 4 sets of RBAR/RLAR registers from TCB. */\n            \"\tstmia r3!, {r4-r11}\t\t\t\t\t\t\t\\n\"/* Write 4 set of RBAR/RLAR registers using alias registers. */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            #if ( configTOTAL_MPU_REGIONS == 16 )\n            \"\tldr r3, xRNRConst\t\t\t\t\t\t\t\\n\"/* r3 = 0xe000ed98 [Location of RNR]. */\n            \"\tmovs r4, #8\t\t\t\t\t\t\t\t\t\\n\"/* r4 = 8. */\n            \"\tstr r4, [r3]\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 8. */\n            \"\tldr r3, xRBARConst\t\t\t\t\t\t\t\\n\"/* r3 = 0xe000ed9c [Location of RBAR]. */\n            \"\tldmia r1!, {r4-r11}\t\t\t\t\t\t\t\\n\"/* Read 4 sets of RBAR/RLAR registers from TCB. */\n            \"\tstmia r3!, {r4-r11}\t\t\t\t\t\t\t\\n\"/* Write 4 set of RBAR/RLAR registers using alias registers. */\n            \"\tldr r3, xRNRConst\t\t\t\t\t\t\t\\n\"/* r3 = 0xe000ed98 [Location of RNR]. */\n            \"\tmovs r4, #12\t\t\t\t\t\t\t\t\\n\"/* r4 = 12. */\n            \"\tstr r4, [r3]\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 12. */\n            \"\tldr r3, xRBARConst\t\t\t\t\t\t\t\\n\"/* r3 = 0xe000ed9c [Location of RBAR]. */\n            \"\tldmia r1!, {r4-r11}\t\t\t\t\t\t\t\\n\"/* Read 4 sets of RBAR/RLAR registers from TCB. */\n            \"\tstmia r3!, {r4-r11}\t\t\t\t\t\t\t\\n\"/* Write 4 set of RBAR/RLAR registers using alias registers. */\n            #endif /* configTOTAL_MPU_REGIONS == 16 */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tldr r3, xMPUCTRLConst\t\t\t\t\t\t\\n\"/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */\n            \"\tldr r4, [r3]\t\t\t\t\t\t\t\t\\n\"/* Read the value of MPU_CTRL. */\n            \"\torr r4, #1\t\t\t\t\t\t\t\t\t\\n\"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\n            \"\tstr r4, [r3]\t\t\t\t\t\t\t\t\\n\"/* Enable MPU. */\n            \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Force memory writes before continuing. */\n        #endif /* configENABLE_MPU */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"\tldmia r2!, {r0, r1, r3, r4}\t\t\t\t\t\\n\"/* Read from stack - r0 = xSecureContext, r1 = PSPLIM, r3 = CONTROL and r4 = LR. */\n            \"\tmsr psplim, r1\t\t\t\t\t\t\t\t\\n\"/* Restore the PSPLIM register value for the task. */\n            \"\tmsr control, r3\t\t\t\t\t\t\t\t\\n\"/* Restore the CONTROL register value for the task. */\n            \"\tmov lr, r4\t\t\t\t\t\t\t\t\t\\n\"/* LR = r4. */\n            \"\tldr r3, xSecureContextConst\t\t\t\t\t\\n\"/* Read the location of xSecureContext i.e. &( xSecureContext ). */\n            \"\tstr r0, [r3]\t\t\t\t\t\t\t\t\\n\"/* Restore the task's xSecureContext. */\n            \"\tcbz r0, restore_ns_context\t\t\t\t\t\\n\"/* If there is no secure context for the task, restore the non-secure context. */\n            \"\tldr r3, pxCurrentTCBConst\t\t\t\t\t\\n\"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n            \"\tldr r1, [r3]\t\t\t\t\t\t\t\t\\n\"/* Read pxCurrentTCB. */\n            \"\tpush {r2, r4}\t\t\t\t\t\t\t\t\\n\"\n            \"\tbl SecureContext_LoadContext\t\t\t\t\\n\"/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */\n            \"\tpop {r2, r4}\t\t\t\t\t\t\t\t\\n\"\n            \"\tmov lr, r4\t\t\t\t\t\t\t\t\t\\n\"/* LR = r4. */\n            \"\tlsls r1, r4, #25\t\t\t\t\t\t\t\\n\"/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\n            \"\tbpl restore_ns_context\t\t\t\t\t\t\\n\"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\n            \"\tmsr psp, r2\t\t\t\t\t\t\t\t\t\\n\"/* Remember the new top of stack for the task. */\n            \"\tbx lr\t\t\t\t\t\t\t\t\t\t\\n\"\n        #else /* configENABLE_MPU */\n            \"\tldmia r2!, {r0, r1, r4}\t\t\t\t\t\t\\n\"/* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */\n            \"\tmsr psplim, r1\t\t\t\t\t\t\t\t\\n\"/* Restore the PSPLIM register value for the task. */\n            \"\tmov lr, r4\t\t\t\t\t\t\t\t\t\\n\"/* LR = r4. */\n            \"\tldr r3, xSecureContextConst\t\t\t\t\t\\n\"/* Read the location of xSecureContext i.e. &( xSecureContext ). */\n            \"\tstr r0, [r3]\t\t\t\t\t\t\t\t\\n\"/* Restore the task's xSecureContext. */\n            \"\tcbz r0, restore_ns_context\t\t\t\t\t\\n\"/* If there is no secure context for the task, restore the non-secure context. */\n            \"\tldr r3, pxCurrentTCBConst\t\t\t\t\t\\n\"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n            \"\tldr r1, [r3]\t\t\t\t\t\t\t\t\\n\"/* Read pxCurrentTCB. */\n            \"\tpush {r2, r4}\t\t\t\t\t\t\t\t\\n\"\n            \"\tbl SecureContext_LoadContext\t\t\t\t\\n\"/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */\n            \"\tpop {r2, r4}\t\t\t\t\t\t\t\t\\n\"\n            \"\tmov lr, r4\t\t\t\t\t\t\t\t\t\\n\"/* LR = r4. */\n            \"\tlsls r1, r4, #25\t\t\t\t\t\t\t\\n\"/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\n            \"\tbpl restore_ns_context\t\t\t\t\t\t\\n\"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\n            \"\tmsr psp, r2\t\t\t\t\t\t\t\t\t\\n\"/* Remember the new top of stack for the task. */\n            \"\tbx lr\t\t\t\t\t\t\t\t\t\t\\n\"\n        #endif /* configENABLE_MPU */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \" restore_ns_context:\t\t\t\t\t\t\t\t\\n\"\n        \"\tldmia r2!, {r4-r11}\t\t\t\t\t\t\t\t\\n\"/* Restore the registers that are not automatically restored. */\n        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )\n            \"\ttst lr, #0x10\t\t\t\t\t\t\t\t\\n\"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */\n            \"\tit eq\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tvldmiaeq r2!, {s16-s31}\t\t\t\t\t\t\\n\"/* Restore the additional FP context registers which are not restored automatically. */\n        #endif /* configENABLE_FPU || configENABLE_MVE */\n        \"\tmsr psp, r2\t\t\t\t\t\t\t\t\t\t\\n\"/* Remember the new top of stack for the task. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.align 4\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"pxCurrentTCBConst: .word pxCurrentTCB\t\t\t\t\\n\"\n        \"xSecureContextConst: .word xSecureContext\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"xMPUCTRLConst: .word 0xe000ed94\t\t\t\t\\n\"\n            \"xMAIR0Const: .word 0xe000edc0\t\t\t\t\t\\n\"\n            \"xRNRConst: .word 0xe000ed98\t\t\t\t\t\\n\"\n            \"xRBARConst: .word 0xe000ed9c\t\t\t\t\t\\n\"\n        #endif /* configENABLE_MPU */\n        ::\"i\" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\ttst lr, #4\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tite eq\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrseq r0, msp\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrsne r0, psp\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r1, svchandler_address_const\t\t\t\t\\n\"\n        \"\tbx r1\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.align 4\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"svchandler_address_const: .word vPortSVCHandler_C\t\\n\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tsvc %0\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Secure context is allocated in the supervisor call. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return. */\n        ::\"i\" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r2, [r0]\t\t\t\t\t\t\t\t\t\\n\"/* The first item in the TCB is the top of the stack. */\n        \"\tldr r1, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* The first item on the stack is the task's xSecureContext. */\n        \"\tcmp r1, #0\t\t\t\t\t\t\t\t\t\t\\n\"/* Raise svc if task's xSecureContext is not NULL. */\n        \"\tit ne\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tsvcne %0\t\t\t\t\t\t\t\t\t\t\\n\"/* Secure context is freed in the supervisor call. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return. */\n        ::\"i\" ( portSVC_FREE_SECURE_CONTEXT ) : \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef PORTMACRO_H\n#define PORTMACRO_H\n\n#ifdef __cplusplus\n    extern \"C\" {\n#endif\n\n#include \"portmacrocommon.h\"\n\n/*------------------------------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the given hardware\n * and compiler.\n *\n * These settings should not be altered.\n *------------------------------------------------------------------------------\n */\n\n/**\n * Architecture specifics.\n */\n#define portARCH_NAME                       \"Cortex-M33\"\n#define portDONT_DISCARD                    __attribute__( ( used ) )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Critical section management.\n */\n#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()\n#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )\n/*-----------------------------------------------------------*/\n\n#ifdef __cplusplus\n    }\n#endif\n\n#endif /* PORTMACRO_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Standard includes. */\n#include <stdint.h>\n\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION\n * is defined correctly and privileged functions are placed in correct sections. */\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/* Portasm includes. */\n#include \"portasm.h\"\n\n/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the\n * header files. */\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\nvoid vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr  r2, pxCurrentTCBConst2\t\t\t\t\t\t\\n\"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n        \"\tldr  r1, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Read pxCurrentTCB. */\n        \"\tldr  r0, [r1]\t\t\t\t\t\t\t\t\t\\n\"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"\tdmb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Complete outstanding transfers before disabling MPU. */\n            \"\tldr r2, xMPUCTRLConst2\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n            \"\tldr r4, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Read the value of MPU_CTRL. */\n            \"\tbic r4, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\n            \"\tstr r4, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Disable MPU. */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tadds r1, #4\t\t\t\t\t\t\t\t\t\t\\n\"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\n            \"\tldr  r3, [r1]\t\t\t\t\t\t\t\t\t\\n\"/* r3 = *r1 i.e. r3 = MAIR0. */\n            \"\tldr  r2, xMAIR0Const2\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000edc0 [Location of MAIR0]. */\n            \"\tstr  r3, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Program MAIR0. */\n            \"\tldr  r2, xRNRConst2\t\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed98 [Location of RNR]. */\n            \"\tmovs r3, #4\t\t\t\t\t\t\t\t\t\t\\n\"/* r3 = 4. */\n            \"\tstr  r3, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 4. */\n            \"\tadds r1, #4\t\t\t\t\t\t\t\t\t\t\\n\"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\n            \"\tldr  r2, xRBARConst2\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed9c [Location of RBAR]. */\n            \"\tldmia r1!, {r4-r11}\t\t\t\t\t\t\t\t\\n\"/* Read 4 set of RBAR/RLAR registers from TCB. */\n            \"\tstmia r2!, {r4-r11}\t\t\t\t\t\t\t\t\\n\"/* Write 4 set of RBAR/RLAR registers using alias registers. */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            #if ( configTOTAL_MPU_REGIONS == 16 )\n            \"\tldr  r2, xRNRConst2\t\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed98 [Location of RNR]. */\n            \"\tmovs r3, #8\t\t\t\t\t\t\t\t\t\t\\n\"/* r3 = 8. */\n            \"\tstr  r3, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 8. */\n            \"\tldr  r2, xRBARConst2\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed9c [Location of RBAR]. */\n            \"\tldmia r1!, {r4-r11}\t\t\t\t\t\t\t\t\\n\"/* Read 4 set of RBAR/RLAR registers from TCB. */\n            \"\tstmia r2!, {r4-r11}\t\t\t\t\t\t\t\t\\n\"/* Write 4 set of RBAR/RLAR registers using alias registers. */\n            \"\tldr  r2, xRNRConst2\t\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed98 [Location of RNR]. */\n            \"\tmovs r3, #12\t\t\t\t\t\t\t\t\t\\n\"/* r3 = 12. */\n            \"\tstr  r3, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 12. */\n            \"\tldr  r2, xRBARConst2\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed9c [Location of RBAR]. */\n            \"\tldmia r1!, {r4-r11}\t\t\t\t\t\t\t\t\\n\"/* Read 4 set of RBAR/RLAR registers from TCB. */\n            \"\tstmia r2!, {r4-r11}\t\t\t\t\t\t\t\t\\n\"/* Write 4 set of RBAR/RLAR registers using alias registers. */\n            #endif /* configTOTAL_MPU_REGIONS == 16 */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tldr r2, xMPUCTRLConst2\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n            \"\tldr r4, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Read the value of MPU_CTRL. */\n            \"\torr r4, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\n            \"\tstr r4, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Enable MPU. */\n            \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Force memory writes before continuing. */\n        #endif /* configENABLE_MPU */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"\tldm  r0!, {r1-r3}\t\t\t\t\t\t\t\t\\n\"/* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */\n            \"\tmsr  psplim, r1\t\t\t\t\t\t\t\t\t\\n\"/* Set this task's PSPLIM value. */\n            \"\tmsr  control, r2\t\t\t\t\t\t\t\t\\n\"/* Set this task's CONTROL value. */\n            \"\tadds r0, #32\t\t\t\t\t\t\t\t\t\\n\"/* Discard everything up to r0. */\n            \"\tmsr  psp, r0\t\t\t\t\t\t\t\t\t\\n\"/* This is now the new top of stack to use in the task. */\n            \"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tmov  r0, #0\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tmsr  basepri, r0\t\t\t\t\t\t\t\t\\n\"/* Ensure that interrupts are enabled when the first task starts. */\n            \"\tbx   r3\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Finally, branch to EXC_RETURN. */\n        #else /* configENABLE_MPU */\n            \"\tldm  r0!, {r1-r2}\t\t\t\t\t\t\t\t\\n\"/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */\n            \"\tmsr  psplim, r1\t\t\t\t\t\t\t\t\t\\n\"/* Set this task's PSPLIM value. */\n            \"\tmovs r1, #2\t\t\t\t\t\t\t\t\t\t\\n\"/* r1 = 2. */\n            \"\tmsr  CONTROL, r1\t\t\t\t\t\t\t\t\\n\"/* Switch to use PSP in the thread mode. */\n            \"\tadds r0, #32\t\t\t\t\t\t\t\t\t\\n\"/* Discard everything up to r0. */\n            \"\tmsr  psp, r0\t\t\t\t\t\t\t\t\t\\n\"/* This is now the new top of stack to use in the task. */\n            \"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tmov  r0, #0\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tmsr  basepri, r0\t\t\t\t\t\t\t\t\\n\"/* Ensure that interrupts are enabled when the first task starts. */\n            \"\tbx   r2\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Finally, branch to EXC_RETURN. */\n        #endif /* configENABLE_MPU */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.align 4\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"pxCurrentTCBConst2: .word pxCurrentTCB\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"xMPUCTRLConst2: .word 0xe000ed94\t\t\t\t\t\\n\"\n            \"xMAIR0Const2: .word 0xe000edc0\t\t\t\t\t\t\\n\"\n            \"xRNRConst2: .word 0xe000ed98\t\t\t\t\t\t\\n\"\n            \"xRBARConst2: .word 0xe000ed9c\t\t\t\t\t\t\\n\"\n        #endif /* configENABLE_MPU */\n    );\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrs r0, control\t\t\t\t\t\t\t\t\t\\n\"/* r0 = CONTROL. */\n        \"\ttst r0, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\n        \"\tite ne\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmovne r0, #0\t\t\t\t\t\t\t\t\t\\n\"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\n        \"\tmoveq r0, #1\t\t\t\t\t\t\t\t\t\\n\"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return. */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.align 4\t\t\t\t\t\t\t\t\t\t\\n\"\n        ::: \"r0\", \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrs  r0, control\t\t\t\t\t\t\t\t\\n\"/* Read the CONTROL register. */\n        \"\tbic r0, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* Clear the bit 0. */\n        \"\tmsr  control, r0\t\t\t\t\t\t\t\t\\n\"/* Write back the new CONTROL value. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return to the caller. */\n        ::: \"r0\", \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vResetPrivilege( void ) /* __attribute__ (( naked )) */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrs r0, control\t\t\t\t\t\t\t\t\t\\n\"/* r0 = CONTROL. */\n        \"\torr r0, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* r0 = r0 | 1. */\n        \"\tmsr control, r0\t\t\t\t\t\t\t\t\t\\n\"/* CONTROL = r0. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return to the caller. */\n        ::: \"r0\", \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r0, xVTORConst\t\t\t\t\t\t\t\t\\n\"/* Use the NVIC offset register to locate the stack. */\n        \"\tldr r0, [r0]\t\t\t\t\t\t\t\t\t\\n\"/* Read the VTOR register which gives the address of vector table. */\n        \"\tldr r0, [r0]\t\t\t\t\t\t\t\t\t\\n\"/* The first entry in vector table is stack pointer. */\n        \"\tmsr msp, r0\t\t\t\t\t\t\t\t\t\t\\n\"/* Set the MSP back to the start of the stack. */\n        \"\tcpsie i\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Globally enable interrupts. */\n        \"\tcpsie f\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tsvc %0\t\t\t\t\t\t\t\t\t\t\t\\n\"/* System call to start the first task. */\n        \"\tnop\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"   .align 4\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"xVTORConst: .word 0xe000ed08\t\t\t\t\t\t\\n\"\n        ::\"i\" ( portSVC_START_SCHEDULER ) : \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nuint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrs r0, basepri\t\t\t\t\t\t\t\t\t\\n\"/* r0 = basepri. Return original basepri value. */\n        \"\tmov r1, %0\t\t\t\t\t\t\t\t\t\t\\n\"/* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */\n        \"\tmsr basepri, r1\t\t\t\t\t\t\t\t\t\\n\"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */\n        \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return. */\n        ::\"i\" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmsr basepri, r0\t\t\t\t\t\t\t\t\t\\n\"/* basepri = ulMask. */\n        \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return. */\n        ::: \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrs r0, psp\t\t\t\t\t\t\t\t\t\t\\n\"/* Read PSP in r0. */\n        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )\n            \"\ttst lr, #0x10\t\t\t\t\t\t\t\t\t\\n\"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */\n            \"\tit eq\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tvstmdbeq r0!, {s16-s31}\t\t\t\t\t\t\t\\n\"/* Store the additional FP context registers which are not saved automatically. */\n        #endif /* configENABLE_FPU || configENABLE_MVE */\n        #if ( configENABLE_MPU == 1 )\n            \"\tmrs r1, psplim\t\t\t\t\t\t\t\t\t\\n\"/* r1 = PSPLIM. */\n            \"\tmrs r2, control\t\t\t\t\t\t\t\t\t\\n\"/* r2 = CONTROL. */\n            \"\tmov r3, lr\t\t\t\t\t\t\t\t\t\t\\n\"/* r3 = LR/EXC_RETURN. */\n            \"\tstmdb r0!, {r1-r11}\t\t\t\t\t\t\t\t\\n\"/* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */\n        #else /* configENABLE_MPU */\n            \"\tmrs r2, psplim\t\t\t\t\t\t\t\t\t\\n\"/* r2 = PSPLIM. */\n            \"\tmov r3, lr\t\t\t\t\t\t\t\t\t\t\\n\"/* r3 = LR/EXC_RETURN. */\n            \"\tstmdb r0!, {r2-r11}\t\t\t\t\t\t\t\t\\n\"/* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */\n        #endif /* configENABLE_MPU */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r2, pxCurrentTCBConst\t\t\t\t\t\t\\n\"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n        \"\tldr r1, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Read pxCurrentTCB. */\n        \"\tstr r0, [r1]\t\t\t\t\t\t\t\t\t\\n\"/* Save the new top of stack in TCB. */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmov r0, %0\t\t\t\t\t\t\t\t\t\t\\n\"/* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */\n        \"\tmsr basepri, r0\t\t\t\t\t\t\t\t\t\\n\"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */\n        \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tbl vTaskSwitchContext\t\t\t\t\t\t\t\\n\"\n        \"\tmov r0, #0\t\t\t\t\t\t\t\t\t\t\\n\"/* r0 = 0. */\n        \"\tmsr basepri, r0\t\t\t\t\t\t\t\t\t\\n\"/* Enable interrupts. */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r2, pxCurrentTCBConst\t\t\t\t\t\t\\n\"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n        \"\tldr r1, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Read pxCurrentTCB. */\n        \"\tldr r0, [r1]\t\t\t\t\t\t\t\t\t\\n\"/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"\tdmb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Complete outstanding transfers before disabling MPU. */\n            \"\tldr r2, xMPUCTRLConst\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n            \"\tldr r4, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Read the value of MPU_CTRL. */\n            \"\tbic r4, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\n            \"\tstr r4, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Disable MPU. */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tadds r1, #4\t\t\t\t\t\t\t\t\t\t\\n\"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\n            \"\tldr r3, [r1]\t\t\t\t\t\t\t\t\t\\n\"/* r3 = *r1 i.e. r3 = MAIR0. */\n            \"\tldr r2, xMAIR0Const\t\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000edc0 [Location of MAIR0]. */\n            \"\tstr r3, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Program MAIR0. */\n            \"\tldr r2, xRNRConst\t\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed98 [Location of RNR]. */\n            \"\tmovs r3, #4\t\t\t\t\t\t\t\t\t\t\\n\"/* r3 = 4. */\n            \"\tstr r3, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 4. */\n            \"\tadds r1, #4\t\t\t\t\t\t\t\t\t\t\\n\"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\n            \"\tldr r2, xRBARConst\t\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed9c [Location of RBAR]. */\n            \"\tldmia r1!, {r4-r11}\t\t\t\t\t\t\t\t\\n\"/* Read 4 sets of RBAR/RLAR registers from TCB. */\n            \"\tstmia r2!, {r4-r11}\t\t\t\t\t\t\t\t\\n\"/* Write 4 set of RBAR/RLAR registers using alias registers. */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            #if ( configTOTAL_MPU_REGIONS == 16 )\n            \"\tldr r2, xRNRConst\t\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed98 [Location of RNR]. */\n            \"\tmovs r3, #8\t\t\t\t\t\t\t\t\t\t\\n\"/* r3 = 8. */\n            \"\tstr r3, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 8. */\n            \"\tldr r2, xRBARConst\t\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed9c [Location of RBAR]. */\n            \"\tldmia r1!, {r4-r11}\t\t\t\t\t\t\t\t\\n\"/* Read 4 sets of RBAR/RLAR registers from TCB. */\n            \"\tstmia r2!, {r4-r11}\t\t\t\t\t\t\t\t\\n\"/* Write 4 set of RBAR/RLAR registers using alias registers. */\n            \"\tldr r2, xRNRConst\t\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed98 [Location of RNR]. */\n            \"\tmovs r3, #12\t\t\t\t\t\t\t\t\t\\n\"/* r3 = 12. */\n            \"\tstr r3, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 12. */\n            \"\tldr r2, xRBARConst\t\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed9c [Location of RBAR]. */\n            \"\tldmia r1!, {r4-r11}\t\t\t\t\t\t\t\t\\n\"/* Read 4 sets of RBAR/RLAR registers from TCB. */\n            \"\tstmia r2!, {r4-r11}\t\t\t\t\t\t\t\t\\n\"/* Write 4 set of RBAR/RLAR registers using alias registers. */\n            #endif /* configTOTAL_MPU_REGIONS == 16 */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tldr r2, xMPUCTRLConst\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n            \"\tldr r4, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Read the value of MPU_CTRL. */\n            \"\torr r4, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\n            \"\tstr r4, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Enable MPU. */\n            \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Force memory writes before continuing. */\n        #endif /* configENABLE_MPU */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"\tldmia r0!, {r1-r11}\t\t\t\t\t\t\t\t\\n\"/* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */\n        #else /* configENABLE_MPU */\n            \"\tldmia r0!, {r2-r11}\t\t\t\t\t\t\t\t\\n\"/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */\n        #endif /* configENABLE_MPU */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )\n            \"\ttst r3, #0x10\t\t\t\t\t\t\t\t\t\\n\"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */\n            \"\tit eq\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tvldmiaeq r0!, {s16-s31}\t\t\t\t\t\t\t\\n\"/* Restore the additional FP context registers which are not restored automatically. */\n        #endif /* configENABLE_FPU || configENABLE_MVE */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"\tmsr psplim, r1\t\t\t\t\t\t\t\t\t\\n\"/* Restore the PSPLIM register value for the task. */\n            \"\tmsr control, r2\t\t\t\t\t\t\t\t\t\\n\"/* Restore the CONTROL register value for the task. */\n        #else /* configENABLE_MPU */\n            \"\tmsr psplim, r2\t\t\t\t\t\t\t\t\t\\n\"/* Restore the PSPLIM register value for the task. */\n        #endif /* configENABLE_MPU */\n        \"\tmsr psp, r0\t\t\t\t\t\t\t\t\t\t\\n\"/* Remember the new top of stack for the task. */\n        \"\tbx r3\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.align 4\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"pxCurrentTCBConst: .word pxCurrentTCB\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"xMPUCTRLConst: .word 0xe000ed94\t\t\t\t\t\\n\"\n            \"xMAIR0Const: .word 0xe000edc0\t\t\t\t\t\t\\n\"\n            \"xRNRConst: .word 0xe000ed98\t\t\t\t\t\t\\n\"\n            \"xRBARConst: .word 0xe000ed9c\t\t\t\t\t\t\\n\"\n        #endif /* configENABLE_MPU */\n        ::\"i\" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\ttst lr, #4\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tite eq\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrseq r0, msp\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrsne r0, psp\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r1, svchandler_address_const\t\t\t\t\\n\"\n        \"\tbx r1\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.align 4\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"svchandler_address_const: .word vPortSVCHandler_C\t\\n\"\n    );\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef PORTMACRO_H\n#define PORTMACRO_H\n\n#ifdef __cplusplus\n    extern \"C\" {\n#endif\n\n#include \"portmacrocommon.h\"\n\n/*------------------------------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the given hardware\n * and compiler.\n *\n * These settings should not be altered.\n *------------------------------------------------------------------------------\n */\n\n/**\n * Architecture specifics.\n */\n#define portARCH_NAME                       \"Cortex-M33\"\n#define portDONT_DISCARD                    __attribute__( ( used ) )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Critical section management.\n */\n#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()\n#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )\n/*-----------------------------------------------------------*/\n\n#ifdef __cplusplus\n    }\n#endif\n\n#endif /* PORTMACRO_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/ARMv8M/non_secure/portable/GCC/ARM_CM55/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef PORTMACRO_H\n#define PORTMACRO_H\n\n#ifdef __cplusplus\n    extern \"C\" {\n#endif\n\n#include \"portmacrocommon.h\"\n\n/*------------------------------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the given hardware\n * and compiler.\n *\n * These settings should not be altered.\n *------------------------------------------------------------------------------\n */\n\n#ifndef configENABLE_MVE\n    #error configENABLE_MVE must be defined in FreeRTOSConfig.h. Set configENABLE_MVE to 1 to enable the MVE or 0 to disable the MVE.\n#endif /* configENABLE_MVE */\n/*-----------------------------------------------------------*/\n\n/**\n * Architecture specifics.\n */\n#define portARCH_NAME                       \"Cortex-M55\"\n#define portDONT_DISCARD                    __attribute__( ( used ) )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Critical section management.\n */\n#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()\n#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )\n/*-----------------------------------------------------------*/\n\n#ifdef __cplusplus\n    }\n#endif\n\n#endif /* PORTMACRO_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/ARMv8M/non_secure/portable/GCC/ARM_CM85/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef PORTMACRO_H\n#define PORTMACRO_H\n\n#ifdef __cplusplus\n    extern \"C\" {\n#endif\n\n#include \"portmacrocommon.h\"\n\n/*------------------------------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the given hardware\n * and compiler.\n *\n * These settings should not be altered.\n *------------------------------------------------------------------------------\n */\n\n#ifndef configENABLE_MVE\n    #error configENABLE_MVE must be defined in FreeRTOSConfig.h. Set configENABLE_MVE to 1 to enable the MVE or 0 to disable the MVE.\n#endif /* configENABLE_MVE */\n/*-----------------------------------------------------------*/\n\n/**\n * Architecture specifics.\n */\n#define portARCH_NAME                       \"Cortex-M85\"\n#define portDONT_DISCARD                    __attribute__( ( used ) )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Critical section management.\n */\n#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()\n#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )\n/*-----------------------------------------------------------*/\n\n#ifdef __cplusplus\n    }\n#endif\n\n#endif /* PORTMACRO_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portasm.s",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Including FreeRTOSConfig.h here will cause build errors if the header file\ncontains code not understood by the assembler - for example the 'extern' keyword.\nTo avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so\nthe code is included in C files but excluded by the preprocessor in assembly\nfiles (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */\n#include \"FreeRTOSConfig.h\"\n\n\tEXTERN pxCurrentTCB\n\tEXTERN xSecureContext\n\tEXTERN vTaskSwitchContext\n\tEXTERN vPortSVCHandler_C\n\tEXTERN SecureContext_SaveContext\n\tEXTERN SecureContext_LoadContext\n\n\tPUBLIC xIsPrivileged\n\tPUBLIC vResetPrivilege\n\tPUBLIC vPortAllocateSecureContext\n\tPUBLIC vRestoreContextOfFirstTask\n\tPUBLIC vRaisePrivilege\n\tPUBLIC vStartFirstTask\n\tPUBLIC ulSetInterruptMask\n\tPUBLIC vClearInterruptMask\n\tPUBLIC PendSV_Handler\n\tPUBLIC SVC_Handler\n\tPUBLIC vPortFreeSecureContext\n\n#if ( configENABLE_FPU == 1 )\n\t#error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.\n#endif\n/*-----------------------------------------------------------*/\n\n/*---------------- Unprivileged Functions -------------------*/\n\n/*-----------------------------------------------------------*/\n\n\tSECTION .text:CODE:NOROOT(2)\n\tTHUMB\n/*-----------------------------------------------------------*/\n\nxIsPrivileged:\n\tmrs r0, control\t\t\t\t\t\t\t/* r0 = CONTROL. */\n\tmovs r1, #1\t\t\t\t\t\t\t\t/* r1 = 1. */\n\ttst r0, r1\t\t\t\t\t\t\t\t/* Perform r0 & r1 (bitwise AND) and update the conditions flag. */\n\tbeq running_privileged\t\t\t\t\t/* If the result of previous AND operation was 0, branch. */\n\tmovs r0, #0\t\t\t\t\t\t\t\t/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\n\tbx lr\t\t\t\t\t\t\t\t\t/* Return. */\n\trunning_privileged:\n\t\tmovs r0, #1\t\t\t\t\t\t\t/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */\n\t\tbx lr\t\t\t\t\t\t\t\t/* Return. */\n/*-----------------------------------------------------------*/\n\nvResetPrivilege:\n\tmrs r0, control\t\t\t\t\t\t\t/* r0 = CONTROL. */\n\tmovs r1, #1\t\t\t\t\t\t\t\t/* r1 = 1. */\n\torrs r0, r1\t\t\t\t\t\t\t\t/* r0 = r0 | r1. */\n\tmsr control, r0\t\t\t\t\t\t\t/* CONTROL = r0. */\n\tbx lr\t\t\t\t\t\t\t\t\t/* Return to the caller. */\n/*-----------------------------------------------------------*/\n\nvPortAllocateSecureContext:\n\tsvc 0\t\t\t\t\t\t\t\t\t/* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 0. */\n\tbx lr\t\t\t\t\t\t\t\t\t/* Return. */\n/*-----------------------------------------------------------*/\n\n/*----------------- Privileged Functions --------------------*/\n\n/*-----------------------------------------------------------*/\n\n\tSECTION privileged_functions:CODE:NOROOT(2)\n\tTHUMB\n/*-----------------------------------------------------------*/\n\nvRestoreContextOfFirstTask:\n\tldr  r2, =pxCurrentTCB\t\t\t\t\t/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n\tldr  r3, [r2]\t\t\t\t\t\t\t/* Read pxCurrentTCB. */\n\tldr  r0, [r3]\t\t\t\t\t\t\t/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\n\n#if ( configENABLE_MPU == 1 )\n\tdmb\t\t\t\t\t\t\t\t\t\t/* Complete outstanding transfers before disabling MPU. */\n\tldr r2, =0xe000ed94\t\t\t\t\t\t/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n\tldr r4, [r2]\t\t\t\t\t\t\t/* Read the value of MPU_CTRL. */\n\tmovs r5, #1\t\t\t\t\t\t\t\t/* r5 = 1. */\n\tbics r4, r5\t\t\t\t\t\t\t\t/* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */\n\tstr r4, [r2]\t\t\t\t\t\t\t/* Disable MPU. */\n\n\tadds r3, #4\t\t\t\t\t\t\t\t/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\n\tldr  r4, [r3]\t\t\t\t\t\t\t/* r4 = *r3 i.e. r4 = MAIR0. */\n\tldr  r2, =0xe000edc0\t\t\t\t\t/* r2 = 0xe000edc0 [Location of MAIR0]. */\n\tstr  r4, [r2]\t\t\t\t\t\t\t/* Program MAIR0. */\n\tldr  r2, =0xe000ed98\t\t\t\t\t/* r2 = 0xe000ed98 [Location of RNR]. */\n\tadds r3, #4\t\t\t\t\t\t\t\t/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */\n\tmovs r5, #4\t\t\t\t\t\t\t\t/* r5 = 4. */\n\tstr  r5, [r2]\t\t\t\t\t\t\t/* Program RNR = 4. */\n\tldmia r3!, {r6,r7}\t\t\t\t\t\t/* Read first set of RBAR/RLAR from TCB. */\n\tldr  r4, =0xe000ed9c\t\t\t\t\t/* r4 = 0xe000ed9c [Location of RBAR]. */\n\tstmia r4!, {r6,r7}\t\t\t\t\t\t/* Write first set of RBAR/RLAR registers. */\n\tmovs r5, #5\t\t\t\t\t\t\t\t/* r5 = 5. */\n\tstr  r5, [r2]\t\t\t\t\t\t\t/* Program RNR = 5. */\n\tldmia r3!, {r6,r7}\t\t\t\t\t\t/* Read second set of RBAR/RLAR from TCB. */\n\tldr  r4, =0xe000ed9c\t\t\t\t\t/* r4 = 0xe000ed9c [Location of RBAR]. */\n\tstmia r4!, {r6,r7}\t\t\t\t\t\t/* Write second set of RBAR/RLAR registers. */\n\tmovs r5, #6\t\t\t\t\t\t\t\t/* r5 = 6. */\n\tstr  r5, [r2]\t\t\t\t\t\t\t/* Program RNR = 6. */\n\tldmia r3!, {r6,r7}\t\t\t\t\t\t/* Read third set of RBAR/RLAR from TCB. */\n\tldr  r4, =0xe000ed9c\t\t\t\t\t/* r4 = 0xe000ed9c [Location of RBAR]. */\n\tstmia r4!, {r6,r7}\t\t\t\t\t\t/* Write third set of RBAR/RLAR registers. */\n\tmovs r5, #7\t\t\t\t\t\t\t\t/* r5 = 7. */\n\tstr  r5, [r2]\t\t\t\t\t\t\t/* Program RNR = 7. */\n\tldmia r3!, {r6,r7}\t\t\t\t\t\t/* Read fourth set of RBAR/RLAR from TCB. */\n\tldr  r4, =0xe000ed9c\t\t\t\t\t/* r4 = 0xe000ed9c [Location of RBAR]. */\n\tstmia r4!, {r6,r7}\t\t\t\t\t\t/* Write fourth set of RBAR/RLAR registers. */\n\n\tldr r2, =0xe000ed94\t\t\t\t\t\t/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n\tldr r4, [r2]\t\t\t\t\t\t\t/* Read the value of MPU_CTRL. */\n\tmovs r5, #1\t\t\t\t\t\t\t\t/* r5 = 1. */\n\torrs r4, r5\t\t\t\t\t\t\t\t/* r4 = r4 | r5 i.e. Set the bit 0 in r4. */\n\tstr r4, [r2]\t\t\t\t\t\t\t/* Enable MPU. */\n\tdsb\t\t\t\t\t\t\t\t\t\t/* Force memory writes before continuing. */\n#endif /* configENABLE_MPU */\n\n#if ( configENABLE_MPU == 1 )\n\tldm  r0!, {r1-r4}\t\t\t\t\t\t/* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */\n\tldr  r5, =xSecureContext\n\tstr  r1, [r5]\t\t\t\t\t\t\t/* Set xSecureContext to this task's value for the same. */\n\tmsr  psplim, r2\t\t\t\t\t\t\t/* Set this task's PSPLIM value. */\n\tmsr  control, r3\t\t\t\t\t\t/* Set this task's CONTROL value. */\n\tadds r0, #32\t\t\t\t\t\t\t/* Discard everything up to r0. */\n\tmsr  psp, r0\t\t\t\t\t\t\t/* This is now the new top of stack to use in the task. */\n\tisb\n\tbx   r4\t\t\t\t\t\t\t\t\t/* Finally, branch to EXC_RETURN. */\n#else /* configENABLE_MPU */\n\tldm  r0!, {r1-r3}\t\t\t\t\t\t/* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */\n\tldr  r4, =xSecureContext\n\tstr  r1, [r4]\t\t\t\t\t\t\t/* Set xSecureContext to this task's value for the same. */\n\tmsr  psplim, r2\t\t\t\t\t\t\t/* Set this task's PSPLIM value. */\n\tmovs r1, #2\t\t\t\t\t\t\t\t/* r1 = 2. */\n\tmsr  CONTROL, r1\t\t\t\t\t\t/* Switch to use PSP in the thread mode. */\n\tadds r0, #32\t\t\t\t\t\t\t/* Discard everything up to r0. */\n\tmsr  psp, r0\t\t\t\t\t\t\t/* This is now the new top of stack to use in the task. */\n\tisb\n\tbx   r3\t\t\t\t\t\t\t\t\t/* Finally, branch to EXC_RETURN. */\n#endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\nvRaisePrivilege:\n\tmrs r0, control\t\t\t\t\t\t\t/* Read the CONTROL register. */\n\tmovs r1, #1\t\t\t\t\t\t\t\t/* r1 = 1. */\n\tbics r0, r1\t\t\t\t\t\t\t\t/* Clear the bit 0. */\n\tmsr control, r0\t\t\t\t\t\t\t/* Write back the new CONTROL value. */\n\tbx lr\t\t\t\t\t\t\t\t\t/* Return to the caller. */\n/*-----------------------------------------------------------*/\n\nvStartFirstTask:\n\tldr r0, =0xe000ed08\t\t\t\t\t\t/* Use the NVIC offset register to locate the stack. */\n\tldr r0, [r0]\t\t\t\t\t\t\t/* Read the VTOR register which gives the address of vector table. */\n\tldr r0, [r0]\t\t\t\t\t\t\t/* The first entry in vector table is stack pointer. */\n\tmsr msp, r0\t\t\t\t\t\t\t\t/* Set the MSP back to the start of the stack. */\n\tcpsie i\t\t\t\t\t\t\t\t\t/* Globally enable interrupts. */\n\tdsb\n\tisb\n\tsvc 2\t\t\t\t\t\t\t\t\t/* System call to start the first task. portSVC_START_SCHEDULER = 2. */\n/*-----------------------------------------------------------*/\n\nulSetInterruptMask:\n\tmrs r0, PRIMASK\n\tcpsid i\n\tbx lr\n/*-----------------------------------------------------------*/\n\nvClearInterruptMask:\n\tmsr PRIMASK, r0\n\tbx lr\n/*-----------------------------------------------------------*/\n\nPendSV_Handler:\n\tldr r3, =xSecureContext\t\t\t\t\t/* Read the location of xSecureContext i.e. &( xSecureContext ). */\n\tldr r0, [r3]\t\t\t\t\t\t\t/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */\n\tldr r3, =pxCurrentTCB\t\t\t\t\t/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n\tldr r1, [r3]\t\t\t\t\t\t\t/* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */\n\tmrs r2, psp\t\t\t\t\t\t\t\t/* Read PSP in r2. */\n\n\tcbz r0, save_ns_context\t\t\t\t\t/* No secure context to save. */\n\tpush {r0-r2, r14}\n\tbl SecureContext_SaveContext\t\t\t/* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */\n\tpop {r0-r3}\t\t\t\t\t\t\t\t/* LR is now in r3. */\n\tmov lr, r3\t\t\t\t\t\t\t\t/* LR = r3. */\n\tlsls r1, r3, #25\t\t\t\t\t\t/* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\n\tbpl save_ns_context\t\t\t\t\t\t/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\n\tldr r3, =pxCurrentTCB\t\t\t\t\t/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n\tldr r1, [r3]\t\t\t\t\t\t\t/* Read pxCurrentTCB. */\n#if ( configENABLE_MPU == 1 )\n\tsubs r2, r2, #16\t\t\t\t\t\t/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */\n\tstr r2, [r1]\t\t\t\t\t\t\t/* Save the new top of stack in TCB. */\n\tmrs r1, psplim\t\t\t\t\t\t\t/* r1 = PSPLIM. */\n\tmrs r3, control\t\t\t\t\t\t\t/* r3 = CONTROL. */\n\tmov r4, lr\t\t\t\t\t\t\t\t/* r4 = LR/EXC_RETURN. */\n\tstmia r2!, {r0, r1, r3, r4}\t\t\t\t/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\n#else /* configENABLE_MPU */\n\tsubs r2, r2, #12\t\t\t\t\t\t/* Make space for xSecureContext, PSPLIM and LR on the stack. */\n\tstr r2, [r1]\t\t\t\t\t\t\t/* Save the new top of stack in TCB. */\n\tmrs r1, psplim\t\t\t\t\t\t\t/* r1 = PSPLIM. */\n\tmov r3, lr\t\t\t\t\t\t\t\t/* r3 = LR/EXC_RETURN. */\n\tstmia r2!, {r0, r1, r3}\t\t\t\t\t/* Store xSecureContext, PSPLIM and LR on the stack. */\n#endif /* configENABLE_MPU */\n\tb select_next_task\n\n\tsave_ns_context:\n\t\tldr r3, =pxCurrentTCB\t\t\t\t/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n\t\tldr r1, [r3]\t\t\t\t\t\t/* Read pxCurrentTCB. */\n\t#if ( configENABLE_MPU == 1 )\n\t\tsubs r2, r2, #48\t\t\t\t\t/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */\n\t\tstr r2, [r1]\t\t\t\t\t\t/* Save the new top of stack in TCB. */\n\t\tadds r2, r2, #16\t\t\t\t\t/* r2 = r2 + 16. */\n\t\tstmia r2!, {r4-r7}\t\t\t\t\t/* Store the low registers that are not saved automatically. */\n\t\tmov r4, r8\t\t\t\t\t\t\t/* r4 = r8. */\n\t\tmov r5, r9\t\t\t\t\t\t\t/* r5 = r9. */\n\t\tmov r6, r10\t\t\t\t\t\t\t/* r6 = r10. */\n\t\tmov r7, r11\t\t\t\t\t\t\t/* r7 = r11. */\n\t\tstmia r2!, {r4-r7}\t\t\t\t\t/* Store the high registers that are not saved automatically. */\n\t\tmrs r1, psplim\t\t\t\t\t\t/* r1 = PSPLIM. */\n\t\tmrs r3, control\t\t\t\t\t\t/* r3 = CONTROL. */\n\t\tmov r4, lr\t\t\t\t\t\t\t/* r4 = LR/EXC_RETURN. */\n\t\tsubs r2, r2, #48\t\t\t\t\t/* r2 = r2 - 48. */\n\t\tstmia r2!, {r0, r1, r3, r4}\t\t\t/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\n\t#else /* configENABLE_MPU */\n\t\tsubs r2, r2, #44\t\t\t\t\t/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */\n\t\tstr r2, [r1]\t\t\t\t\t\t/* Save the new top of stack in TCB. */\n\t\tmrs r1, psplim\t\t\t\t\t\t/* r1 = PSPLIM. */\n\t\tmov r3, lr\t\t\t\t\t\t\t/* r3 = LR/EXC_RETURN. */\n\t\tstmia r2!, {r0, r1, r3-r7}\t\t\t/* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */\n\t\tmov r4, r8\t\t\t\t\t\t\t/* r4 = r8. */\n\t\tmov r5, r9\t\t\t\t\t\t\t/* r5 = r9. */\n\t\tmov r6, r10\t\t\t\t\t\t\t/* r6 = r10. */\n\t\tmov r7, r11\t\t\t\t\t\t\t/* r7 = r11. */\n\t\tstmia r2!, {r4-r7}\t\t\t\t\t/* Store the high registers that are not saved automatically. */\n\t#endif /* configENABLE_MPU */\n\n\tselect_next_task:\n\t\tcpsid i\n\t\tbl vTaskSwitchContext\n\t\tcpsie i\n\n\t\tldr r3, =pxCurrentTCB\t\t\t\t/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n\t\tldr r1, [r3]\t\t\t\t\t\t/* Read pxCurrentTCB. */\n\t\tldr r2, [r1]\t\t\t\t\t\t/* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */\n\n\t#if ( configENABLE_MPU == 1 )\n\t\tdmb\t\t\t\t\t\t\t\t\t/* Complete outstanding transfers before disabling MPU. */\n\t\tldr r3, =0xe000ed94\t\t\t\t\t/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */\n\t\tldr r4, [r3]\t\t\t\t\t\t/* Read the value of MPU_CTRL. */\n\t\tmovs r5, #1\t\t\t\t\t\t\t/* r5 = 1. */\n\t\tbics r4, r5\t\t\t\t\t\t\t/* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */\n\t\tstr r4, [r3]\t\t\t\t\t\t/* Disable MPU. */\n\n\t\tadds r1, #4\t\t\t\t\t\t\t/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\n\t\tldr r4, [r1]\t\t\t\t\t\t/* r4 = *r1 i.e. r4 = MAIR0. */\n\t\tldr r3, =0xe000edc0\t\t\t\t\t/* r3 = 0xe000edc0 [Location of MAIR0]. */\n\t\tstr r4, [r3]\t\t\t\t\t\t/* Program MAIR0. */\n\t\tldr r4, =0xe000ed98\t\t\t\t\t/* r4 = 0xe000ed98 [Location of RNR]. */\n\t\tadds r1, #4\t\t\t\t\t\t\t/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\n\t\tmovs r5, #4\t\t\t\t\t\t\t/* r5 = 4. */\n\t\tstr  r5, [r4]\t\t\t\t\t\t/* Program RNR = 4. */\n\t\tldmia r1!, {r6,r7}\t\t\t\t\t/* Read first set of RBAR/RLAR from TCB. */\n\t\tldr  r3, =0xe000ed9c\t\t\t\t/* r3 = 0xe000ed9c [Location of RBAR]. */\n\t\tstmia r3!, {r6,r7}\t\t\t\t\t/* Write first set of RBAR/RLAR registers. */\n\t\tmovs r5, #5\t\t\t\t\t\t\t/* r5 = 5. */\n\t\tstr  r5, [r4]\t\t\t\t\t\t/* Program RNR = 5. */\n\t\tldmia r1!, {r6,r7}\t\t\t\t\t/* Read second set of RBAR/RLAR from TCB. */\n\t\tldr  r3, =0xe000ed9c\t\t\t\t/* r3 = 0xe000ed9c [Location of RBAR]. */\n\t\tstmia r3!, {r6,r7}\t\t\t\t\t/* Write second set of RBAR/RLAR registers. */\n\t\tmovs r5, #6\t\t\t\t\t\t\t/* r5 = 6. */\n\t\tstr  r5, [r4]\t\t\t\t\t\t/* Program RNR = 6. */\n\t\tldmia r1!, {r6,r7}\t\t\t\t\t/* Read third set of RBAR/RLAR from TCB. */\n\t\tldr  r3, =0xe000ed9c\t\t\t\t/* r3 = 0xe000ed9c [Location of RBAR]. */\n\t\tstmia r3!, {r6,r7}\t\t\t\t\t/* Write third set of RBAR/RLAR registers. */\n\t\tmovs r5, #7\t\t\t\t\t\t\t/* r5 = 7. */\n\t\tstr  r5, [r4]\t\t\t\t\t\t/* Program RNR = 7. */\n\t\tldmia r1!, {r6,r7}\t\t\t\t\t/* Read fourth set of RBAR/RLAR from TCB. */\n\t\tldr  r3, =0xe000ed9c\t\t\t\t/* r3 = 0xe000ed9c [Location of RBAR]. */\n\t\tstmia r3!, {r6,r7}\t\t\t\t\t/* Write fourth set of RBAR/RLAR registers. */\n\n\t\tldr r3, =0xe000ed94\t\t\t\t\t/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */\n\t\tldr r4, [r3]\t\t\t\t\t\t/* Read the value of MPU_CTRL. */\n\t\tmovs r5, #1\t\t\t\t\t\t\t/* r5 = 1. */\n\t\torrs r4, r5\t\t\t\t\t\t\t/* r4 = r4 | r5 i.e. Set the bit 0 in r4. */\n\t\tstr r4, [r3]\t\t\t\t\t\t/* Enable MPU. */\n\t\tdsb\t\t\t\t\t\t\t\t\t/* Force memory writes before continuing. */\n\t#endif /* configENABLE_MPU */\n\n\t#if ( configENABLE_MPU == 1 )\n\t\tldmia r2!, {r0, r1, r3, r4}\t\t\t/* Read from stack - r0 = xSecureContext, r1 = PSPLIM, r3 = CONTROL and r4 = LR. */\n\t\tmsr psplim, r1\t\t\t\t\t\t/* Restore the PSPLIM register value for the task. */\n\t\tmsr control, r3\t\t\t\t\t\t/* Restore the CONTROL register value for the task. */\n\t\tmov lr, r4\t\t\t\t\t\t\t/* LR = r4. */\n\t\tldr r3, =xSecureContext\t\t\t\t/* Read the location of xSecureContext i.e. &( xSecureContext ). */\n\t\tstr r0, [r3]\t\t\t\t\t\t/* Restore the task's xSecureContext. */\n\t\tcbz r0, restore_ns_context\t\t\t/* If there is no secure context for the task, restore the non-secure context. */\n\t\tldr r3, =pxCurrentTCB\t\t\t\t/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n\t\tldr r1, [r3]\t\t\t\t\t\t/* Read pxCurrentTCB. */\n\t\tpush {r2, r4}\n\t\tbl SecureContext_LoadContext\t\t/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */\n\t\tpop {r2, r4}\n\t\tmov lr, r4\t\t\t\t\t\t\t/* LR = r4. */\n\t\tlsls r1, r4, #25\t\t\t\t\t/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\n\t\tbpl restore_ns_context\t\t\t\t/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\n\t\tmsr psp, r2\t\t\t\t\t\t\t/* Remember the new top of stack for the task. */\n\t\tbx lr\n\t#else /* configENABLE_MPU */\n\t\tldmia r2!, {r0, r1, r4}\t\t\t\t/* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */\n\t\tmsr psplim, r1\t\t\t\t\t\t/* Restore the PSPLIM register value for the task. */\n\t\tmov lr, r4\t\t\t\t\t\t\t/* LR = r4. */\n\t\tldr r3, =xSecureContext\t\t\t\t/* Read the location of xSecureContext i.e. &( xSecureContext ). */\n\t\tstr r0, [r3]\t\t\t\t\t\t/* Restore the task's xSecureContext. */\n\t\tcbz r0, restore_ns_context\t\t\t/* If there is no secure context for the task, restore the non-secure context. */\n\t\tldr r3, =pxCurrentTCB\t\t\t\t/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n\t\tldr r1, [r3]\t\t\t\t\t\t/* Read pxCurrentTCB. */\n\t\tpush {r2, r4}\n\t\tbl SecureContext_LoadContext\t\t/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */\n\t\tpop {r2, r4}\n\t\tmov lr, r4\t\t\t\t\t\t\t/* LR = r4. */\n\t\tlsls r1, r4, #25\t\t\t\t\t/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\n\t\tbpl restore_ns_context\t\t\t\t/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\n\t\tmsr psp, r2\t\t\t\t\t\t\t/* Remember the new top of stack for the task. */\n\t\tbx lr\n\t#endif /* configENABLE_MPU */\n\n\trestore_ns_context:\n\t\tadds r2, r2, #16\t\t\t\t\t/* Move to the high registers. */\n\t\tldmia r2!, {r4-r7}\t\t\t\t\t/* Restore the high registers that are not automatically restored. */\n\t\tmov r8, r4\t\t\t\t\t\t\t/* r8 = r4. */\n\t\tmov r9, r5\t\t\t\t\t\t\t/* r9 = r5. */\n\t\tmov r10, r6\t\t\t\t\t\t\t/* r10 = r6. */\n\t\tmov r11, r7\t\t\t\t\t\t\t/* r11 = r7. */\n\t\tmsr psp, r2\t\t\t\t\t\t\t/* Remember the new top of stack for the task. */\n\t\tsubs r2, r2, #32\t\t\t\t\t/* Go back to the low registers. */\n\t\tldmia r2!, {r4-r7}\t\t\t\t\t/* Restore the low registers that are not automatically restored. */\n\t\tbx lr\n/*-----------------------------------------------------------*/\n\nSVC_Handler:\n\tmovs r0, #4\n\tmov r1, lr\n\ttst r0, r1\n\tbeq stacking_used_msp\n\tmrs r0, psp\n\tb vPortSVCHandler_C\n\tstacking_used_msp:\n\t\tmrs r0, msp\n\t\tb vPortSVCHandler_C\n/*-----------------------------------------------------------*/\n\nvPortFreeSecureContext:\n\tldr r2, [r0]\t\t\t\t\t\t\t/* The first item in the TCB is the top of the stack. */\n\tldr r1, [r2]\t\t\t\t\t\t\t/* The first item on the stack is the task's xSecureContext. */\n\tcmp r1, #0\t\t\t\t\t\t\t\t/* Raise svc if task's xSecureContext is not NULL. */\n\tbne free_secure_context\t\t\t\t\t/* Branch if r1 != 0. */\n\tbx lr\t\t\t\t\t\t\t\t\t/* There is no secure context (xSecureContext is NULL). */\n\tfree_secure_context:\n\t\tsvc 1\t\t\t\t\t\t\t\t/* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */\n\t\tbx lr\t\t\t\t\t\t\t\t/* Return. */\n/*-----------------------------------------------------------*/\n\n\tEND\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef PORTMACRO_H\n#define PORTMACRO_H\n\n#ifdef __cplusplus\n    extern \"C\" {\n#endif\n\n#include \"portmacrocommon.h\"\n\n/*------------------------------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the given hardware\n * and compiler.\n *\n * These settings should not be altered.\n *------------------------------------------------------------------------------\n */\n\n/**\n * Architecture specifics.\n */\n#define portARCH_NAME                       \"Cortex-M23\"\n#define portDONT_DISCARD                    __root\n/*-----------------------------------------------------------*/\n\n#if( configTOTAL_MPU_REGIONS == 16 )\n    #error 16 MPU regions are not yet supported for this port.\n#endif\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Critical section management.\n */\n#define portDISABLE_INTERRUPTS()            __asm volatile ( \" cpsid i \" ::: \"memory\" )\n#define portENABLE_INTERRUPTS()             __asm volatile ( \" cpsie i \" ::: \"memory\" )\n/*-----------------------------------------------------------*/\n\n/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in\n * the source code because to do so would cause other compilers to generate\n * warnings. */\n#pragma diag_suppress=Be006\n#pragma diag_suppress=Pa082\n/*-----------------------------------------------------------*/\n\n#ifdef __cplusplus\n    }\n#endif\n\n#endif /* PORTMACRO_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portasm.s",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n/* Including FreeRTOSConfig.h here will cause build errors if the header file\ncontains code not understood by the assembler - for example the 'extern' keyword.\nTo avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so\nthe code is included in C files but excluded by the preprocessor in assembly\nfiles (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */\n#include \"FreeRTOSConfig.h\"\n\n\tEXTERN pxCurrentTCB\n\tEXTERN vTaskSwitchContext\n\tEXTERN vPortSVCHandler_C\n\n\tPUBLIC xIsPrivileged\n\tPUBLIC vResetPrivilege\n\tPUBLIC vRestoreContextOfFirstTask\n\tPUBLIC vRaisePrivilege\n\tPUBLIC vStartFirstTask\n\tPUBLIC ulSetInterruptMask\n\tPUBLIC vClearInterruptMask\n\tPUBLIC PendSV_Handler\n\tPUBLIC SVC_Handler\n\n#if ( configENABLE_FPU == 1 )\n\t#error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.\n#endif\n/*-----------------------------------------------------------*/\n\n/*---------------- Unprivileged Functions -------------------*/\n\n/*-----------------------------------------------------------*/\n\n\tSECTION .text:CODE:NOROOT(2)\n\tTHUMB\n/*-----------------------------------------------------------*/\n\nxIsPrivileged:\n\tmrs r0, control\t\t\t\t\t\t\t/* r0 = CONTROL. */\n\tmovs r1, #1\t\t\t\t\t\t\t\t/* r1 = 1. */\n\ttst r0, r1\t\t\t\t\t\t\t\t/* Perform r0 & r1 (bitwise AND) and update the conditions flag. */\n\tbeq running_privileged\t\t\t\t\t/* If the result of previous AND operation was 0, branch. */\n\tmovs r0, #0\t\t\t\t\t\t\t\t/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\n\tbx lr\t\t\t\t\t\t\t\t\t/* Return. */\n\trunning_privileged:\n\t\tmovs r0, #1\t\t\t\t\t\t\t/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */\n\t\tbx lr\t\t\t\t\t\t\t\t/* Return. */\n\n/*-----------------------------------------------------------*/\n\nvResetPrivilege:\n\tmrs r0, control\t\t\t\t\t\t\t/* r0 = CONTROL. */\n\tmovs r1, #1\t\t\t\t\t\t\t\t/* r1 = 1. */\n\torrs r0, r1\t\t\t\t\t\t\t\t/* r0 = r0 | r1. */\n\tmsr control, r0\t\t\t\t\t\t\t/* CONTROL = r0. */\n\tbx lr\t\t\t\t\t\t\t\t\t/* Return to the caller. */\n/*-----------------------------------------------------------*/\n\n/*----------------- Privileged Functions --------------------*/\n\n/*-----------------------------------------------------------*/\n\n\tSECTION privileged_functions:CODE:NOROOT(2)\n\tTHUMB\n/*-----------------------------------------------------------*/\n\nvRestoreContextOfFirstTask:\n\tldr  r2, =pxCurrentTCB\t\t\t\t\t/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n\tldr  r1, [r2]\t\t\t\t\t\t\t/* Read pxCurrentTCB. */\n\tldr  r0, [r1]\t\t\t\t\t\t\t/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\n\n#if ( configENABLE_MPU == 1 )\n\tdmb\t\t\t\t\t\t\t\t\t\t/* Complete outstanding transfers before disabling MPU. */\n\tldr r2, =0xe000ed94\t\t\t\t\t\t/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n\tldr r3, [r2]\t\t\t\t\t\t\t/* Read the value of MPU_CTRL. */\n\tmovs r4, #1\t\t\t\t\t\t\t\t/* r4 = 1. */\n\tbics r3, r4\t\t\t\t\t\t\t\t/* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */\n\tstr r3, [r2]\t\t\t\t\t\t\t/* Disable MPU. */\n\n\tadds r1, #4\t\t\t\t\t\t\t\t/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\n\tldr  r4, [r1]\t\t\t\t\t\t\t/* r4 = *r1 i.e. r4 = MAIR0. */\n\tldr  r2, =0xe000edc0\t\t\t\t\t/* r2 = 0xe000edc0 [Location of MAIR0]. */\n\tstr  r4, [r2]\t\t\t\t\t\t\t/* Program MAIR0. */\n\tldr  r2, =0xe000ed98\t\t\t\t\t/* r2 = 0xe000ed98 [Location of RNR]. */\n\tadds r1, #4\t\t\t\t\t\t\t\t/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\n\tmovs r4, #4\t\t\t\t\t\t\t\t/* r4 = 4. */\n\tstr  r4, [r2]\t\t\t\t\t\t\t/* Program RNR = 4. */\n\tldmia r1!, {r5,r6}\t\t\t\t\t\t/* Read first set of RBAR/RLAR from TCB. */\n\tldr  r3, =0xe000ed9c\t\t\t\t\t/* r3 = 0xe000ed9c [Location of RBAR]. */\n\tstmia r3!, {r5,r6}\t\t\t\t\t\t/* Write first set of RBAR/RLAR registers. */\n\tmovs r4, #5\t\t\t\t\t\t\t\t/* r4 = 5. */\n\tstr  r4, [r2]\t\t\t\t\t\t\t/* Program RNR = 5. */\n\tldmia r1!, {r5,r6}\t\t\t\t\t\t/* Read second set of RBAR/RLAR from TCB. */\n\tldr  r3, =0xe000ed9c\t\t\t\t\t/* r3 = 0xe000ed9c [Location of RBAR]. */\n\tstmia r3!, {r5,r6}\t\t\t\t\t\t/* Write second set of RBAR/RLAR registers. */\n\tmovs r4, #6\t\t\t\t\t\t\t\t/* r4 = 6. */\n\tstr  r4, [r2]\t\t\t\t\t\t\t/* Program RNR = 6. */\n\tldmia r1!, {r5,r6}\t\t\t\t\t\t/* Read third set of RBAR/RLAR from TCB. */\n\tldr  r3, =0xe000ed9c\t\t\t\t\t/* r3 = 0xe000ed9c [Location of RBAR]. */\n\tstmia r3!, {r5,r6}\t\t\t\t\t\t/* Write third set of RBAR/RLAR registers. */\n\tmovs r4, #7\t\t\t\t\t\t\t\t/* r4 = 7. */\n\tstr  r4, [r2]\t\t\t\t\t\t\t/* Program RNR = 7. */\n\tldmia r1!, {r5,r6}\t\t\t\t\t\t/* Read fourth set of RBAR/RLAR from TCB. */\n\tldr  r3, =0xe000ed9c\t\t\t\t\t/* r3 = 0xe000ed9c [Location of RBAR]. */\n\tstmia r3!, {r5,r6}\t\t\t\t\t\t/* Write fourth set of RBAR/RLAR registers. */\n\n\tldr r2, =0xe000ed94\t\t\t\t\t\t/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n\tldr r3, [r2]\t\t\t\t\t\t\t/* Read the value of MPU_CTRL. */\n\tmovs r4, #1\t\t\t\t\t\t\t\t/* r4 = 1. */\n\torrs r3, r4\t\t\t\t\t\t\t\t/* r3 = r3 | r4 i.e. Set the bit 0 in r3. */\n\tstr r3, [r2]\t\t\t\t\t\t\t/* Enable MPU. */\n\tdsb\t\t\t\t\t\t\t\t\t\t/* Force memory writes before continuing. */\n#endif /* configENABLE_MPU */\n\n#if ( configENABLE_MPU == 1 )\n\tldm  r0!, {r1-r3}\t\t\t\t\t\t/* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */\n\tmsr  psplim, r1\t\t\t\t\t\t\t/* Set this task's PSPLIM value. */\n\tmsr  control, r2\t\t\t\t\t\t/* Set this task's CONTROL value. */\n\tadds r0, #32\t\t\t\t\t\t\t/* Discard everything up to r0. */\n\tmsr  psp, r0\t\t\t\t\t\t\t/* This is now the new top of stack to use in the task. */\n\tisb\n\tbx   r3\t\t\t\t\t\t\t\t\t/* Finally, branch to EXC_RETURN. */\n#else /* configENABLE_MPU */\n\tldm  r0!, {r1-r2}\t\t\t\t\t\t/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */\n\tmsr  psplim, r1\t\t\t\t\t\t\t/* Set this task's PSPLIM value. */\n\tmovs r1, #2\t\t\t\t\t\t\t\t/* r1 = 2. */\n\tmsr  CONTROL, r1\t\t\t\t\t\t/* Switch to use PSP in the thread mode. */\n\tadds r0, #32\t\t\t\t\t\t\t/* Discard everything up to r0. */\n\tmsr  psp, r0\t\t\t\t\t\t\t/* This is now the new top of stack to use in the task. */\n\tisb\n\tbx   r2\t\t\t\t\t\t\t\t\t/* Finally, branch to EXC_RETURN. */\n#endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\nvRaisePrivilege:\n\tmrs  r0, control\t\t\t\t\t\t/* Read the CONTROL register. */\n\tmovs r1, #1\t\t\t\t\t\t\t\t/* r1 = 1. */\n\tbics r0, r1\t\t\t\t\t\t\t\t/* Clear the bit 0. */\n\tmsr  control, r0\t\t\t\t\t\t/* Write back the new CONTROL value. */\n\tbx lr\t\t\t\t\t\t\t\t\t/* Return to the caller. */\n/*-----------------------------------------------------------*/\n\nvStartFirstTask:\n\tldr r0, =0xe000ed08\t\t\t\t\t\t/* Use the NVIC offset register to locate the stack. */\n\tldr r0, [r0]\t\t\t\t\t\t\t/* Read the VTOR register which gives the address of vector table. */\n\tldr r0, [r0]\t\t\t\t\t\t\t/* The first entry in vector table is stack pointer. */\n\tmsr msp, r0\t\t\t\t\t\t\t\t/* Set the MSP back to the start of the stack. */\n\tcpsie i\t\t\t\t\t\t\t\t\t/* Globally enable interrupts. */\n\tdsb\n\tisb\n\tsvc 2\t\t\t\t\t\t\t\t\t/* System call to start the first task. portSVC_START_SCHEDULER = 2. */\n\tnop\n/*-----------------------------------------------------------*/\n\nulSetInterruptMask:\n\tmrs r0, PRIMASK\n\tcpsid i\n\tbx lr\n/*-----------------------------------------------------------*/\n\nvClearInterruptMask:\n\tmsr PRIMASK, r0\n\tbx lr\n/*-----------------------------------------------------------*/\n\nPendSV_Handler:\n\tmrs r0, psp\t\t\t\t\t\t\t\t/* Read PSP in r0. */\n\tldr r2, =pxCurrentTCB\t\t\t\t\t/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n\tldr r1, [r2]\t\t\t\t\t\t\t/* Read pxCurrentTCB. */\n#if ( configENABLE_MPU == 1 )\n\tsubs r0, r0, #44\t\t\t\t\t\t/* Make space for PSPLIM, CONTROL, LR and the remaining registers on the stack. */\n\tstr r0, [r1]\t\t\t\t\t\t\t/* Save the new top of stack in TCB. */\n\tmrs r1, psplim\t\t\t\t\t\t\t/* r1 = PSPLIM. */\n\tmrs r2, control\t\t\t\t\t\t\t/* r2 = CONTROL. */\n\tmov r3, lr\t\t\t\t\t\t\t\t/* r3 = LR/EXC_RETURN. */\n\tstmia r0!, {r1-r7}\t\t\t\t\t\t/* Store on the stack - PSPLIM, CONTROL, LR and low registers that are not automatically saved. */\n\tmov r4, r8\t\t\t\t\t\t\t\t/* r4 = r8. */\n\tmov r5, r9\t\t\t\t\t\t\t\t/* r5 = r9. */\n\tmov r6, r10\t\t\t\t\t\t\t\t/* r6 = r10. */\n\tmov r7, r11\t\t\t\t\t\t\t\t/* r7 = r11. */\n\tstmia r0!, {r4-r7}\t\t\t\t\t\t/* Store the high registers that are not saved automatically. */\n#else /* configENABLE_MPU */\n\tsubs r0, r0, #40\t\t\t\t\t\t/* Make space for PSPLIM, LR and the remaining registers on the stack. */\n\tstr r0, [r1]\t\t\t\t\t\t\t/* Save the new top of stack in TCB. */\n\tmrs r2, psplim\t\t\t\t\t\t\t/* r2 = PSPLIM. */\n\tmov r3, lr\t\t\t\t\t\t\t\t/* r3 = LR/EXC_RETURN. */\n\tstmia r0!, {r2-r7}\t\t\t\t\t\t/* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */\n\tmov r4, r8\t\t\t\t\t\t\t\t/* r4 = r8. */\n\tmov r5, r9\t\t\t\t\t\t\t\t/* r5 = r9. */\n\tmov r6, r10\t\t\t\t\t\t\t\t/* r6 = r10. */\n\tmov r7, r11\t\t\t\t\t\t\t\t/* r7 = r11. */\n\tstmia r0!, {r4-r7}\t\t\t\t\t\t/* Store the high registers that are not saved automatically. */\n#endif /* configENABLE_MPU */\n\n\tcpsid i\n\tbl vTaskSwitchContext\n\tcpsie i\n\n\tldr r2, =pxCurrentTCB\t\t\t\t\t/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n\tldr r1, [r2]\t\t\t\t\t\t\t/* Read pxCurrentTCB. */\n\tldr r0, [r1]\t\t\t\t\t\t\t/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */\n\n#if ( configENABLE_MPU == 1 )\n\tdmb\t\t\t\t\t\t\t\t\t\t/* Complete outstanding transfers before disabling MPU. */\n\tldr r2, =0xe000ed94\t\t\t\t\t\t/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n\tldr r3, [r2]\t\t\t\t\t\t\t/* Read the value of MPU_CTRL. */\n\tmovs r4, #1\t\t\t\t\t\t\t\t/* r4 = 1. */\n\tbics r3, r4\t\t\t\t\t\t\t\t/* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */\n\tstr r3, [r2]\t\t\t\t\t\t\t/* Disable MPU. */\n\n\tadds r1, #4\t\t\t\t\t\t\t\t/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\n\tldr  r4, [r1]\t\t\t\t\t\t\t/* r4 = *r1 i.e. r4 = MAIR0. */\n\tldr  r2, =0xe000edc0\t\t\t\t\t/* r2 = 0xe000edc0 [Location of MAIR0]. */\n\tstr  r4, [r2]\t\t\t\t\t\t\t/* Program MAIR0. */\n\tldr  r2, =0xe000ed98\t\t\t\t\t/* r2 = 0xe000ed98 [Location of RNR]. */\n\tadds r1, #4\t\t\t\t\t\t\t\t/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\n\tmovs r4, #4\t\t\t\t\t\t\t\t/* r4 = 4. */\n\tstr  r4, [r2]\t\t\t\t\t\t\t/* Program RNR = 4. */\n\tldmia r1!, {r5,r6}\t\t\t\t\t\t/* Read first set of RBAR/RLAR from TCB. */\n\tldr  r3, =0xe000ed9c\t\t\t\t\t/* r3 = 0xe000ed9c [Location of RBAR]. */\n\tstmia r3!, {r5,r6}\t\t\t\t\t\t/* Write first set of RBAR/RLAR registers. */\n\tmovs r4, #5\t\t\t\t\t\t\t\t/* r4 = 5. */\n\tstr  r4, [r2]\t\t\t\t\t\t\t/* Program RNR = 5. */\n\tldmia r1!, {r5,r6}\t\t\t\t\t\t/* Read second set of RBAR/RLAR from TCB. */\n\tldr  r3, =0xe000ed9c\t\t\t\t\t/* r3 = 0xe000ed9c [Location of RBAR]. */\n\tstmia r3!, {r5,r6}\t\t\t\t\t\t/* Write second set of RBAR/RLAR registers. */\n\tmovs r4, #6\t\t\t\t\t\t\t\t/* r4 = 6. */\n\tstr  r4, [r2]\t\t\t\t\t\t\t/* Program RNR = 6. */\n\tldmia r1!, {r5,r6}\t\t\t\t\t\t/* Read third set of RBAR/RLAR from TCB. */\n\tldr  r3, =0xe000ed9c\t\t\t\t\t/* r3 = 0xe000ed9c [Location of RBAR]. */\n\tstmia r3!, {r5,r6}\t\t\t\t\t\t/* Write third set of RBAR/RLAR registers. */\n\tmovs r4, #7\t\t\t\t\t\t\t\t/* r4 = 7. */\n\tstr  r4, [r2]\t\t\t\t\t\t\t/* Program RNR = 7. */\n\tldmia r1!, {r5,r6}\t\t\t\t\t\t/* Read fourth set of RBAR/RLAR from TCB. */\n\tldr  r3, =0xe000ed9c\t\t\t\t\t/* r3 = 0xe000ed9c [Location of RBAR]. */\n\tstmia r3!, {r5,r6}\t\t\t\t\t\t/* Write fourth set of RBAR/RLAR registers. */\n\n\tldr r2, =0xe000ed94\t\t\t\t\t\t/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n\tldr r3, [r2]\t\t\t\t\t\t\t/* Read the value of MPU_CTRL. */\n\tmovs r4, #1\t\t\t\t\t\t\t\t/* r4 = 1. */\n\torrs r3, r4\t\t\t\t\t\t\t\t/* r3 = r3 | r4 i.e. Set the bit 0 in r3. */\n\tstr r3, [r2]\t\t\t\t\t\t\t/* Enable MPU. */\n\tdsb\t\t\t\t\t\t\t\t\t\t/* Force memory writes before continuing. */\n#endif /* configENABLE_MPU */\n\n#if ( configENABLE_MPU == 1 )\n\tadds r0, r0, #28\t\t\t\t\t\t/* Move to the high registers. */\n\tldmia r0!, {r4-r7}\t\t\t\t\t\t/* Restore the high registers that are not automatically restored. */\n\tmov r8, r4\t\t\t\t\t\t\t\t/* r8 = r4. */\n\tmov r9, r5\t\t\t\t\t\t\t\t/* r9 = r5. */\n\tmov r10, r6\t\t\t\t\t\t\t\t/* r10 = r6. */\n\tmov r11, r7\t\t\t\t\t\t\t\t/* r11 = r7. */\n\tmsr psp, r0\t\t\t\t\t\t\t\t/* Remember the new top of stack for the task. */\n\tsubs r0, r0, #44\t\t\t\t\t\t/* Move to the starting of the saved context. */\n\tldmia r0!, {r1-r7}\t\t\t\t\t\t/* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r7 restored. */\n\tmsr psplim, r1\t\t\t\t\t\t\t/* Restore the PSPLIM register value for the task. */\n\tmsr control, r2\t\t\t\t\t\t\t/* Restore the CONTROL register value for the task. */\n\tbx r3\n#else /* configENABLE_MPU */\n\tadds r0, r0, #24\t\t\t\t\t\t/* Move to the high registers. */\n\tldmia r0!, {r4-r7}\t\t\t\t\t\t/* Restore the high registers that are not automatically restored. */\n\tmov r8, r4\t\t\t\t\t\t\t\t/* r8 = r4. */\n\tmov r9, r5\t\t\t\t\t\t\t\t/* r9 = r5. */\n\tmov r10, r6\t\t\t\t\t\t\t\t/* r10 = r6. */\n\tmov r11, r7\t\t\t\t\t\t\t\t/* r11 = r7. */\n\tmsr psp, r0\t\t\t\t\t\t\t\t/* Remember the new top of stack for the task. */\n\tsubs r0, r0, #40\t\t\t\t\t\t/* Move to the starting of the saved context. */\n\tldmia r0!, {r2-r7}\t\t\t\t\t\t/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */\n\tmsr psplim, r2\t\t\t\t\t\t\t/* Restore the PSPLIM register value for the task. */\n\tbx r3\n#endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\nSVC_Handler:\n\tmovs r0, #4\n\tmov r1, lr\n\ttst r0, r1\n\tbeq stacking_used_msp\n\tmrs r0, psp\n\tb vPortSVCHandler_C\n\tstacking_used_msp:\n\t\tmrs r0, msp\n\t\tb vPortSVCHandler_C\n/*-----------------------------------------------------------*/\n\n\tEND\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef PORTMACRO_H\n#define PORTMACRO_H\n\n#ifdef __cplusplus\n    extern \"C\" {\n#endif\n\n#include \"portmacrocommon.h\"\n\n/*------------------------------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the given hardware\n * and compiler.\n *\n * These settings should not be altered.\n *------------------------------------------------------------------------------\n */\n\n/**\n * Architecture specifics.\n */\n#define portARCH_NAME                       \"Cortex-M23\"\n#define portDONT_DISCARD                    __root\n/*-----------------------------------------------------------*/\n\n#if( configTOTAL_MPU_REGIONS == 16 )\n    #error 16 MPU regions are not yet supported for this port.\n#endif\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Critical section management.\n */\n#define portDISABLE_INTERRUPTS()            __asm volatile ( \" cpsid i \" ::: \"memory\" )\n#define portENABLE_INTERRUPTS()             __asm volatile ( \" cpsie i \" ::: \"memory\" )\n/*-----------------------------------------------------------*/\n\n/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in\n * the source code because to do so would cause other compilers to generate\n * warnings. */\n#pragma diag_suppress=Be006\n#pragma diag_suppress=Pa082\n/*-----------------------------------------------------------*/\n\n#ifdef __cplusplus\n    }\n#endif\n\n#endif /* PORTMACRO_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n/* Including FreeRTOSConfig.h here will cause build errors if the header file\ncontains code not understood by the assembler - for example the 'extern' keyword.\nTo avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so\nthe code is included in C files but excluded by the preprocessor in assembly\nfiles (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */\n#include \"FreeRTOSConfig.h\"\n\n\tEXTERN pxCurrentTCB\n\tEXTERN xSecureContext\n\tEXTERN vTaskSwitchContext\n\tEXTERN vPortSVCHandler_C\n\tEXTERN SecureContext_SaveContext\n\tEXTERN SecureContext_LoadContext\n\n\tPUBLIC xIsPrivileged\n\tPUBLIC vResetPrivilege\n\tPUBLIC vPortAllocateSecureContext\n\tPUBLIC vRestoreContextOfFirstTask\n\tPUBLIC vRaisePrivilege\n\tPUBLIC vStartFirstTask\n\tPUBLIC ulSetInterruptMask\n\tPUBLIC vClearInterruptMask\n\tPUBLIC PendSV_Handler\n\tPUBLIC SVC_Handler\n\tPUBLIC vPortFreeSecureContext\n/*-----------------------------------------------------------*/\n\n/*---------------- Unprivileged Functions -------------------*/\n\n/*-----------------------------------------------------------*/\n\n\tSECTION .text:CODE:NOROOT(2)\n\tTHUMB\n/*-----------------------------------------------------------*/\n\nxIsPrivileged:\n\tmrs r0, control\t\t\t\t\t\t\t/* r0 = CONTROL. */\n\ttst r0, #1\t\t\t\t\t\t\t\t/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\n\tite ne\n\tmovne r0, #0\t\t\t\t\t\t\t/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\n\tmoveq r0, #1\t\t\t\t\t\t\t/* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */\n\tbx lr\t\t\t\t\t\t\t\t\t/* Return. */\n/*-----------------------------------------------------------*/\n\nvResetPrivilege:\n\tmrs r0, control\t\t\t\t\t\t\t/* r0 = CONTROL. */\n\torr r0, r0, #1\t\t\t\t\t\t\t/* r0 = r0 | 1. */\n\tmsr control, r0\t\t\t\t\t\t\t/* CONTROL = r0. */\n\tbx lr\t\t\t\t\t\t\t\t\t/* Return to the caller. */\n/*-----------------------------------------------------------*/\n\nvPortAllocateSecureContext:\n\tsvc 0\t\t\t\t\t\t\t\t\t/* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 0. */\n\tbx lr\t\t\t\t\t\t\t\t\t/* Return. */\n/*-----------------------------------------------------------*/\n\n/*----------------- Privileged Functions --------------------*/\n\n/*-----------------------------------------------------------*/\n\n\tSECTION privileged_functions:CODE:NOROOT(2)\n\tTHUMB\n/*-----------------------------------------------------------*/\n\nvRestoreContextOfFirstTask:\n\tldr  r2, =pxCurrentTCB\t\t\t\t\t/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n\tldr  r3, [r2]\t\t\t\t\t\t\t/* Read pxCurrentTCB. */\n\tldr  r0, [r3]\t\t\t\t\t\t\t/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\n\n#if ( configENABLE_MPU == 1 )\n\tdmb\t\t\t\t\t\t\t\t\t\t/* Complete outstanding transfers before disabling MPU. */\n\tldr r2, =0xe000ed94\t\t\t\t\t\t/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n\tldr r4, [r2]\t\t\t\t\t\t\t/* Read the value of MPU_CTRL. */\n\tbic r4, r4, #1\t\t\t\t\t\t\t/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\n\tstr r4, [r2]\t\t\t\t\t\t\t/* Disable MPU. */\n\n\tadds r3, #4\t\t\t\t\t\t\t\t/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\n\tldr  r4, [r3]\t\t\t\t\t\t\t/* r4 = *r3 i.e. r4 = MAIR0. */\n\tldr  r2, =0xe000edc0\t\t\t\t\t/* r2 = 0xe000edc0 [Location of MAIR0]. */\n\tstr  r4, [r2]\t\t\t\t\t\t\t/* Program MAIR0. */\n\tldr  r2, =0xe000ed98\t\t\t\t\t/* r2 = 0xe000ed98 [Location of RNR]. */\n\tmovs r4, #4\t\t\t\t\t\t\t\t/* r4 = 4. */\n\tstr  r4, [r2]\t\t\t\t\t\t\t/* Program RNR = 4. */\n\tadds r3, #4\t\t\t\t\t\t\t\t/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */\n\tldr  r2, =0xe000ed9c\t\t\t\t\t/* r2 = 0xe000ed9c [Location of RBAR]. */\n\tldmia r3!, {r4-r11}\t\t\t\t\t\t/* Read 4 set of RBAR/RLAR registers from TCB. */\n\tstmia r2!, {r4-r11}\t\t\t\t\t\t/* Write 4 set of RBAR/RLAR registers using alias registers. */\n\n\tldr r2, =0xe000ed94\t\t\t\t\t\t/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n\tldr r4, [r2]\t\t\t\t\t\t\t/* Read the value of MPU_CTRL. */\n\torr r4, r4, #1\t\t\t\t\t\t\t/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\n\tstr r4, [r2]\t\t\t\t\t\t\t/* Enable MPU. */\n\tdsb\t\t\t\t\t\t\t\t\t\t/* Force memory writes before continuing. */\n#endif /* configENABLE_MPU */\n\n#if ( configENABLE_MPU == 1 )\n\tldm  r0!, {r1-r4}\t\t\t\t\t\t/* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */\n\tldr  r5, =xSecureContext\n\tstr  r1, [r5]\t\t\t\t\t\t\t/* Set xSecureContext to this task's value for the same. */\n\tmsr  psplim, r2\t\t\t\t\t\t\t/* Set this task's PSPLIM value. */\n\tmsr  control, r3\t\t\t\t\t\t/* Set this task's CONTROL value. */\n\tadds r0, #32\t\t\t\t\t\t\t/* Discard everything up to r0. */\n\tmsr  psp, r0\t\t\t\t\t\t\t/* This is now the new top of stack to use in the task. */\n\tisb\n\tmov  r0, #0\n\tmsr  basepri, r0\t\t\t\t\t\t/* Ensure that interrupts are enabled when the first task starts. */\n\tbx   r4\t\t\t\t\t\t\t\t\t/* Finally, branch to EXC_RETURN. */\n#else /* configENABLE_MPU */\n\tldm  r0!, {r1-r3}\t\t\t\t\t\t/* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */\n\tldr  r4, =xSecureContext\n\tstr  r1, [r4]\t\t\t\t\t\t\t/* Set xSecureContext to this task's value for the same. */\n\tmsr  psplim, r2\t\t\t\t\t\t\t/* Set this task's PSPLIM value. */\n\tmovs r1, #2\t\t\t\t\t\t\t\t/* r1 = 2. */\n\tmsr  CONTROL, r1\t\t\t\t\t\t/* Switch to use PSP in the thread mode. */\n\tadds r0, #32\t\t\t\t\t\t\t/* Discard everything up to r0. */\n\tmsr  psp, r0\t\t\t\t\t\t\t/* This is now the new top of stack to use in the task. */\n\tisb\n\tmov  r0, #0\n\tmsr  basepri, r0\t\t\t\t\t\t/* Ensure that interrupts are enabled when the first task starts. */\n\tbx   r3\t\t\t\t\t\t\t\t\t/* Finally, branch to EXC_RETURN. */\n#endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\nvRaisePrivilege:\n\tmrs  r0, control\t\t\t\t\t\t/* Read the CONTROL register. */\n\tbic r0, r0, #1\t\t\t\t\t\t\t/* Clear the bit 0. */\n\tmsr  control, r0\t\t\t\t\t\t/* Write back the new CONTROL value. */\n\tbx lr\t\t\t\t\t\t\t\t\t/* Return to the caller. */\n/*-----------------------------------------------------------*/\n\nvStartFirstTask:\n\tldr r0, =0xe000ed08\t\t\t\t\t\t/* Use the NVIC offset register to locate the stack. */\n\tldr r0, [r0]\t\t\t\t\t\t\t/* Read the VTOR register which gives the address of vector table. */\n\tldr r0, [r0]\t\t\t\t\t\t\t/* The first entry in vector table is stack pointer. */\n\tmsr msp, r0\t\t\t\t\t\t\t\t/* Set the MSP back to the start of the stack. */\n\tcpsie i\t\t\t\t\t\t\t\t\t/* Globally enable interrupts. */\n\tcpsie f\n\tdsb\n\tisb\n\tsvc 2\t\t\t\t\t\t\t\t\t/* System call to start the first task. portSVC_START_SCHEDULER = 2. */\n/*-----------------------------------------------------------*/\n\nulSetInterruptMask:\n\tmrs r0, basepri\t\t\t\t\t\t\t/* r0 = basepri. Return original basepri value. */\n\tmov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY\n\tmsr basepri, r1\t\t\t\t\t\t\t/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */\n\tdsb\n\tisb\n\tbx lr\t\t\t\t\t\t\t\t\t/* Return. */\n/*-----------------------------------------------------------*/\n\nvClearInterruptMask:\n\tmsr basepri, r0\t\t\t\t\t\t\t/* basepri = ulMask. */\n\tdsb\n\tisb\n\tbx lr\t\t\t\t\t\t\t\t\t/* Return. */\n/*-----------------------------------------------------------*/\n\nPendSV_Handler:\n\tldr r3, =xSecureContext\t\t\t\t\t/* Read the location of xSecureContext i.e. &( xSecureContext ). */\n\tldr r0, [r3]\t\t\t\t\t\t\t/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */\n\tldr r3, =pxCurrentTCB\t\t\t\t\t/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n\tldr r1, [r3]\t\t\t\t\t\t\t/* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */\n\tmrs r2, psp\t\t\t\t\t\t\t\t/* Read PSP in r2. */\n\n\tcbz r0, save_ns_context\t\t\t\t\t/* No secure context to save. */\n\tpush {r0-r2, r14}\n\tbl SecureContext_SaveContext\t\t\t/* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */\n\tpop {r0-r3}\t\t\t\t\t\t\t\t/* LR is now in r3. */\n\tmov lr, r3\t\t\t\t\t\t\t\t/* LR = r3. */\n\tlsls r1, r3, #25\t\t\t\t\t\t/* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\n\tbpl save_ns_context\t\t\t\t\t\t/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\n\n\tldr r3, =pxCurrentTCB\t\t\t\t\t/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n\tldr r1, [r3]\t\t\t\t\t\t\t/* Read pxCurrentTCB. */\n#if ( configENABLE_MPU == 1 )\n\tsubs r2, r2, #16\t\t\t\t\t\t/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */\n\tstr r2, [r1]\t\t\t\t\t\t\t/* Save the new top of stack in TCB. */\n\tmrs r1, psplim\t\t\t\t\t\t\t/* r1 = PSPLIM. */\n\tmrs r3, control\t\t\t\t\t\t\t/* r3 = CONTROL. */\n\tmov r4, lr\t\t\t\t\t\t\t\t/* r4 = LR/EXC_RETURN. */\n\tstmia r2!, {r0, r1, r3, r4}\t\t\t\t/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\n#else /* configENABLE_MPU */\n\tsubs r2, r2, #12\t\t\t\t\t\t/* Make space for xSecureContext, PSPLIM and LR on the stack. */\n\tstr r2, [r1]\t\t\t\t\t\t\t/* Save the new top of stack in TCB. */\n\tmrs r1, psplim\t\t\t\t\t\t\t/* r1 = PSPLIM. */\n\tmov r3, lr\t\t\t\t\t\t\t\t/* r3 = LR/EXC_RETURN. */\n\tstmia r2!, {r0, r1, r3}\t\t\t\t\t/* Store xSecureContext, PSPLIM and LR on the stack. */\n#endif /* configENABLE_MPU */\n\tb select_next_task\n\n\tsave_ns_context:\n\t\tldr r3, =pxCurrentTCB\t\t\t\t/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n\t\tldr r1, [r3]\t\t\t\t\t\t/* Read pxCurrentTCB. */\n\t#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )\n\t\ttst lr, #0x10\t\t\t\t\t\t/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */\n\t\tit eq\n\t\tvstmdbeq r2!, {s16-s31}\t\t\t\t/* Store the additional FP context registers which are not saved automatically. */\n\t#endif /* configENABLE_FPU || configENABLE_MVE */\n\t#if ( configENABLE_MPU == 1 )\n\t\tsubs r2, r2, #48\t\t\t\t\t/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */\n\t\tstr r2, [r1]\t\t\t\t\t\t/* Save the new top of stack in TCB. */\n\t\tadds r2, r2, #16\t\t\t\t\t/* r2 = r2 + 16. */\n\t\tstm r2, {r4-r11}\t\t\t\t\t/* Store the registers that are not saved automatically. */\n\t\tmrs r1, psplim\t\t\t\t\t\t/* r1 = PSPLIM. */\n\t\tmrs r3, control\t\t\t\t\t\t/* r3 = CONTROL. */\n\t\tmov r4, lr\t\t\t\t\t\t\t/* r4 = LR/EXC_RETURN. */\n\t\tsubs r2, r2, #16\t\t\t\t\t/* r2 = r2 - 16. */\n\t\tstmia r2!, {r0, r1, r3, r4}\t\t\t/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\n\t#else /* configENABLE_MPU */\n\t\tsubs r2, r2, #44\t\t\t\t\t/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */\n\t\tstr r2, [r1]\t\t\t\t\t\t/* Save the new top of stack in TCB. */\n\t\tadds r2, r2, #12\t\t\t\t\t/* r2 = r2 + 12. */\n\t\tstm r2, {r4-r11}\t\t\t\t\t/* Store the registers that are not saved automatically. */\n\t\tmrs r1, psplim\t\t\t\t\t\t/* r1 = PSPLIM. */\n\t\tmov r3, lr\t\t\t\t\t\t\t/* r3 = LR/EXC_RETURN. */\n\t\tsubs r2, r2, #12\t\t\t\t\t/* r2 = r2 - 12. */\n\t\tstmia r2!, {r0, r1, r3}\t\t\t\t/* Store xSecureContext, PSPLIM and LR on the stack. */\n\t#endif /* configENABLE_MPU */\n\n\tselect_next_task:\n\t\tmov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY\n\t\tmsr basepri, r0\t\t\t\t\t\t/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */\n\t\tdsb\n\t\tisb\n\t\tbl vTaskSwitchContext\n\t\tmov r0, #0\t\t\t\t\t\t\t/* r0 = 0. */\n\t\tmsr basepri, r0\t\t\t\t\t\t/* Enable interrupts. */\n\n\t\tldr r3, =pxCurrentTCB\t\t\t\t/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n\t\tldr r1, [r3]\t\t\t\t\t\t/* Read pxCurrentTCB. */\n\t\tldr r2, [r1]\t\t\t\t\t\t/* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */\n\n\t#if ( configENABLE_MPU == 1 )\n\t\tdmb\t\t\t\t\t\t\t\t\t/* Complete outstanding transfers before disabling MPU. */\n\t\tldr r3, =0xe000ed94\t\t\t\t\t/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */\n\t\tldr r4, [r3]\t\t\t\t\t\t/* Read the value of MPU_CTRL. */\n\t\tbic r4, r4, #1\t\t\t\t\t\t/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\n\t\tstr r4, [r3]\t\t\t\t\t\t/* Disable MPU. */\n\n\t\tadds r1, #4\t\t\t\t\t\t\t/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\n\t\tldr r4, [r1]\t\t\t\t\t\t/* r4 = *r1 i.e. r4 = MAIR0. */\n\t\tldr r3, =0xe000edc0\t\t\t\t\t/* r3 = 0xe000edc0 [Location of MAIR0]. */\n\t\tstr r4, [r3]\t\t\t\t\t\t/* Program MAIR0. */\n\t\tldr r3, =0xe000ed98\t\t\t\t\t/* r3 = 0xe000ed98 [Location of RNR]. */\n\t\tmovs r4, #4\t\t\t\t\t\t\t/* r4 = 4. */\n\t\tstr r4, [r3]\t\t\t\t\t\t/* Program RNR = 4. */\n\t\tadds r1, #4\t\t\t\t\t\t\t/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\n\t\tldr  r3, =0xe000ed9c\t\t\t\t/* r3 = 0xe000ed9c [Location of RBAR]. */\n\t\tldmia r1!, {r4-r11}\t\t\t\t\t/* Read 4 sets of RBAR/RLAR registers from TCB. */\n\t\tstmia r3!, {r4-r11}\t\t\t\t\t/* Write 4 set of RBAR/RLAR registers using alias registers. */\n\n\t\tldr r3, =0xe000ed94\t\t\t\t\t/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */\n\t\tldr r4, [r3]\t\t\t\t\t\t/* Read the value of MPU_CTRL. */\n\t\torr r4, r4, #1\t\t\t\t\t\t/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\n\t\tstr r4, [r3]\t\t\t\t\t\t/* Enable MPU. */\n\t\tdsb\t\t\t\t\t\t\t\t\t/* Force memory writes before continuing. */\n\t#endif /* configENABLE_MPU */\n\n\t#if ( configENABLE_MPU == 1 )\n\t\tldmia r2!, {r0, r1, r3, r4}\t\t\t/* Read from stack - r0 = xSecureContext, r1 = PSPLIM, r3 = CONTROL and r4 = LR. */\n\t\tmsr psplim, r1\t\t\t\t\t\t/* Restore the PSPLIM register value for the task. */\n\t\tmsr control, r3\t\t\t\t\t\t/* Restore the CONTROL register value for the task. */\n\t\tmov lr, r4\t\t\t\t\t\t\t/* LR = r4. */\n\t\tldr r3, =xSecureContext\t\t\t\t/* Read the location of xSecureContext i.e. &( xSecureContext ). */\n\t\tstr r0, [r3]\t\t\t\t\t\t/* Restore the task's xSecureContext. */\n\t\tcbz r0, restore_ns_context\t\t\t/* If there is no secure context for the task, restore the non-secure context. */\n\t\tldr r3, =pxCurrentTCB\t\t\t\t/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n\t\tldr r1, [r3]\t\t\t\t\t\t/* Read pxCurrentTCB. */\n\t\tpush {r2, r4}\n\t\tbl SecureContext_LoadContext\t\t/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */\n\t\tpop {r2, r4}\n\t\tmov lr, r4\t\t\t\t\t\t\t/* LR = r4. */\n\t\tlsls r1, r4, #25\t\t\t\t\t/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\n\t\tbpl restore_ns_context\t\t\t\t/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\n\t\tmsr psp, r2\t\t\t\t\t\t\t/* Remember the new top of stack for the task. */\n\t\tbx lr\n\t#else /* configENABLE_MPU */\n\t\tldmia r2!, {r0, r1, r4}\t\t\t\t/* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */\n\t\tmsr psplim, r1\t\t\t\t\t\t/* Restore the PSPLIM register value for the task. */\n\t\tmov lr, r4\t\t\t\t\t\t\t/* LR = r4. */\n\t\tldr r3, =xSecureContext\t\t\t\t/* Read the location of xSecureContext i.e. &( xSecureContext ). */\n\t\tstr r0, [r3]\t\t\t\t\t\t/* Restore the task's xSecureContext. */\n\t\tcbz r0, restore_ns_context\t\t\t/* If there is no secure context for the task, restore the non-secure context. */\n\t\tldr r3, =pxCurrentTCB\t\t\t\t/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n\t\tldr r1, [r3]\t\t\t\t\t\t/* Read pxCurrentTCB. */\n\t\tpush {r2, r4}\n\t\tbl SecureContext_LoadContext\t\t/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */\n\t\tpop {r2, r4}\n\t\tmov lr, r4\t\t\t\t\t\t\t/* LR = r4. */\n\t\tlsls r1, r4, #25\t\t\t\t\t/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\n\t\tbpl restore_ns_context\t\t\t\t/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\n\t\tmsr psp, r2\t\t\t\t\t\t\t/* Remember the new top of stack for the task. */\n\t\tbx lr\n\t#endif /* configENABLE_MPU */\n\n\trestore_ns_context:\n\t\tldmia r2!, {r4-r11}\t\t\t\t\t/* Restore the registers that are not automatically restored. */\n\t#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )\n\t\ttst lr, #0x10\t\t\t\t\t\t/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */\n\t\tit eq\n\t\tvldmiaeq r2!, {s16-s31}\t\t\t\t/* Restore the additional FP context registers which are not restored automatically. */\n\t#endif /* configENABLE_FPU || configENABLE_MVE */\n\t\tmsr psp, r2\t\t\t\t\t\t\t/* Remember the new top of stack for the task. */\n\t\tbx lr\n/*-----------------------------------------------------------*/\n\nSVC_Handler:\n\ttst lr, #4\n\tite eq\n\tmrseq r0, msp\n\tmrsne r0, psp\n\tb vPortSVCHandler_C\n/*-----------------------------------------------------------*/\n\nvPortFreeSecureContext:\n\t/* r0 = uint32_t *pulTCB. */\n\tldr r2, [r0]\t\t\t\t\t\t\t/* The first item in the TCB is the top of the stack. */\n\tldr r1, [r2]\t\t\t\t\t\t\t/* The first item on the stack is the task's xSecureContext. */\n\tcmp r1, #0\t\t\t\t\t\t\t\t/* Raise svc if task's xSecureContext is not NULL. */\n\tit ne\n\tsvcne 1\t\t\t\t\t\t\t\t\t/* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */\n\tbx lr\t\t\t\t\t\t\t\t\t/* Return. */\n/*-----------------------------------------------------------*/\n\n\tEND\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef PORTMACRO_H\n#define PORTMACRO_H\n\n#ifdef __cplusplus\n    extern \"C\" {\n#endif\n\n#include \"portmacrocommon.h\"\n\n/*------------------------------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the given hardware\n * and compiler.\n *\n * These settings should not be altered.\n *------------------------------------------------------------------------------\n */\n\n/**\n * Architecture specifics.\n */\n#define portARCH_NAME                       \"Cortex-M33\"\n#define portDONT_DISCARD                    __root\n/*-----------------------------------------------------------*/\n\n#if( configTOTAL_MPU_REGIONS == 16 )\n    #error 16 MPU regions are not yet supported for this port.\n#endif\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Critical section management.\n */\n#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()\n#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )\n/*-----------------------------------------------------------*/\n\n/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in\n * the source code because to do so would cause other compilers to generate\n * warnings. */\n#pragma diag_suppress=Be006\n#pragma diag_suppress=Pa082\n/*-----------------------------------------------------------*/\n\n#ifdef __cplusplus\n    }\n#endif\n\n#endif /* PORTMACRO_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n/* Including FreeRTOSConfig.h here will cause build errors if the header file\ncontains code not understood by the assembler - for example the 'extern' keyword.\nTo avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so\nthe code is included in C files but excluded by the preprocessor in assembly\nfiles (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */\n#include \"FreeRTOSConfig.h\"\n\n\tEXTERN pxCurrentTCB\n\tEXTERN vTaskSwitchContext\n\tEXTERN vPortSVCHandler_C\n\n\tPUBLIC xIsPrivileged\n\tPUBLIC vResetPrivilege\n\tPUBLIC vRestoreContextOfFirstTask\n\tPUBLIC vRaisePrivilege\n\tPUBLIC vStartFirstTask\n\tPUBLIC ulSetInterruptMask\n\tPUBLIC vClearInterruptMask\n\tPUBLIC PendSV_Handler\n\tPUBLIC SVC_Handler\n/*-----------------------------------------------------------*/\n\n/*---------------- Unprivileged Functions -------------------*/\n\n/*-----------------------------------------------------------*/\n\n\tSECTION .text:CODE:NOROOT(2)\n\tTHUMB\n/*-----------------------------------------------------------*/\n\nxIsPrivileged:\n\tmrs r0, control\t\t\t\t\t\t\t/* r0 = CONTROL. */\n\ttst r0, #1\t\t\t\t\t\t\t\t/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\n\tite ne\n\tmovne r0, #0\t\t\t\t\t\t\t/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\n\tmoveq r0, #1\t\t\t\t\t\t\t/* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */\n\tbx lr\t\t\t\t\t\t\t\t\t/* Return. */\n/*-----------------------------------------------------------*/\n\nvResetPrivilege:\n\tmrs r0, control\t\t\t\t\t\t\t/* r0 = CONTROL. */\n\torr r0, r0, #1\t\t\t\t\t\t\t/* r0 = r0 | 1. */\n\tmsr control, r0\t\t\t\t\t\t\t/* CONTROL = r0. */\n\tbx lr\t\t\t\t\t\t\t\t\t/* Return to the caller. */\n/*-----------------------------------------------------------*/\n\n/*----------------- Privileged Functions --------------------*/\n\n/*-----------------------------------------------------------*/\n\n\tSECTION privileged_functions:CODE:NOROOT(2)\n\tTHUMB\n/*-----------------------------------------------------------*/\n\nvRestoreContextOfFirstTask:\n\tldr  r2, =pxCurrentTCB\t\t\t\t\t/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n\tldr  r1, [r2]\t\t\t\t\t\t\t/* Read pxCurrentTCB. */\n\tldr  r0, [r1]\t\t\t\t\t\t\t/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\n\n#if ( configENABLE_MPU == 1 )\n\tdmb\t\t\t\t\t\t\t\t\t\t/* Complete outstanding transfers before disabling MPU. */\n\tldr r2, =0xe000ed94\t\t\t\t\t\t/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n\tldr r4, [r2]\t\t\t\t\t\t\t/* Read the value of MPU_CTRL. */\n\tbic r4, r4, #1\t\t\t\t\t\t\t/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\n\tstr r4, [r2]\t\t\t\t\t\t\t/* Disable MPU. */\n\n\tadds r1, #4\t\t\t\t\t\t\t\t/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\n\tldr r3, [r1]\t\t\t\t\t\t\t/* r3 = *r1 i.e. r3 = MAIR0. */\n\tldr r2, =0xe000edc0\t\t\t\t\t\t/* r2 = 0xe000edc0 [Location of MAIR0]. */\n\tstr r3, [r2]\t\t\t\t\t\t\t/* Program MAIR0. */\n\tldr r2, =0xe000ed98\t\t\t\t\t\t/* r2 = 0xe000ed98 [Location of RNR]. */\n\tmovs r3, #4\t\t\t\t\t\t\t\t/* r3 = 4. */\n\tstr r3, [r2]\t\t\t\t\t\t\t/* Program RNR = 4. */\n\tadds r1, #4\t\t\t\t\t\t\t\t/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\n\tldr r2, =0xe000ed9c\t\t\t\t\t\t/* r2 = 0xe000ed9c [Location of RBAR]. */\n\tldmia r1!, {r4-r11}\t\t\t\t\t\t/* Read 4 sets of RBAR/RLAR registers from TCB. */\n\tstmia r2!, {r4-r11}\t\t\t\t\t\t/* Write 4 set of RBAR/RLAR registers using alias registers. */\n\n\tldr r2, =0xe000ed94\t\t\t\t\t\t/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n\tldr r4, [r2]\t\t\t\t\t\t\t/* Read the value of MPU_CTRL. */\n\torr r4, r4, #1\t\t\t\t\t\t\t/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\n\tstr r4, [r2]\t\t\t\t\t\t\t/* Enable MPU. */\n\tdsb\t\t\t\t\t\t\t\t\t\t/* Force memory writes before continuing. */\n#endif /* configENABLE_MPU */\n\n#if ( configENABLE_MPU == 1 )\n\tldm  r0!, {r1-r3}\t\t\t\t\t\t/* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */\n\tmsr  psplim, r1\t\t\t\t\t\t\t/* Set this task's PSPLIM value. */\n\tmsr  control, r2\t\t\t\t\t\t/* Set this task's CONTROL value. */\n\tadds r0, #32\t\t\t\t\t\t\t/* Discard everything up to r0. */\n\tmsr  psp, r0\t\t\t\t\t\t\t/* This is now the new top of stack to use in the task. */\n\tisb\n\tmov  r0, #0\n\tmsr  basepri, r0\t\t\t\t\t\t/* Ensure that interrupts are enabled when the first task starts. */\n\tbx   r3\t\t\t\t\t\t\t\t\t/* Finally, branch to EXC_RETURN. */\n#else /* configENABLE_MPU */\n\tldm  r0!, {r1-r2}\t\t\t\t\t\t/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */\n\tmsr  psplim, r1\t\t\t\t\t\t\t/* Set this task's PSPLIM value. */\n\tmovs r1, #2\t\t\t\t\t\t\t\t/* r1 = 2. */\n\tmsr  CONTROL, r1\t\t\t\t\t\t/* Switch to use PSP in the thread mode. */\n\tadds r0, #32\t\t\t\t\t\t\t/* Discard everything up to r0. */\n\tmsr  psp, r0\t\t\t\t\t\t\t/* This is now the new top of stack to use in the task. */\n\tisb\n\tmov  r0, #0\n\tmsr  basepri, r0\t\t\t\t\t\t/* Ensure that interrupts are enabled when the first task starts. */\n\tbx   r2\t\t\t\t\t\t\t\t\t/* Finally, branch to EXC_RETURN. */\n#endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\nvRaisePrivilege:\n\tmrs  r0, control\t\t\t\t\t\t/* Read the CONTROL register. */\n\tbic r0, r0, #1\t\t\t\t\t\t\t/* Clear the bit 0. */\n\tmsr  control, r0\t\t\t\t\t\t/* Write back the new CONTROL value. */\n\tbx lr\t\t\t\t\t\t\t\t\t/* Return to the caller. */\n/*-----------------------------------------------------------*/\n\nvStartFirstTask:\n\tldr r0, =0xe000ed08\t\t\t\t\t\t/* Use the NVIC offset register to locate the stack. */\n\tldr r0, [r0]\t\t\t\t\t\t\t/* Read the VTOR register which gives the address of vector table. */\n\tldr r0, [r0]\t\t\t\t\t\t\t/* The first entry in vector table is stack pointer. */\n\tmsr msp, r0\t\t\t\t\t\t\t\t/* Set the MSP back to the start of the stack. */\n\tcpsie i\t\t\t\t\t\t\t\t\t/* Globally enable interrupts. */\n\tcpsie f\n\tdsb\n\tisb\n\tsvc 2\t\t\t\t\t\t\t\t\t/* System call to start the first task. portSVC_START_SCHEDULER = 2. */\n/*-----------------------------------------------------------*/\n\nulSetInterruptMask:\n\tmrs r0, basepri\t\t\t\t\t\t\t/* r0 = basepri. Return original basepri value. */\n\tmov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY\n\tmsr basepri, r1\t\t\t\t\t\t\t/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */\n\tdsb\n\tisb\n\tbx lr\t\t\t\t\t\t\t\t\t/* Return. */\n/*-----------------------------------------------------------*/\n\nvClearInterruptMask:\n\tmsr basepri, r0\t\t\t\t\t\t\t/* basepri = ulMask. */\n\tdsb\n\tisb\n\tbx lr\t\t\t\t\t\t\t\t\t/* Return. */\n/*-----------------------------------------------------------*/\n\nPendSV_Handler:\n\tmrs r0, psp\t\t\t\t\t\t\t\t/* Read PSP in r0. */\n#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )\n\ttst lr, #0x10\t\t\t\t\t\t\t/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */\n\tit eq\n\tvstmdbeq r0!, {s16-s31}\t\t\t\t\t/* Store the additional FP context registers which are not saved automatically. */\n#endif /* configENABLE_FPU || configENABLE_MVE */\n#if ( configENABLE_MPU == 1 )\n\tmrs r1, psplim\t\t\t\t\t\t\t/* r1 = PSPLIM. */\n\tmrs r2, control\t\t\t\t\t\t\t/* r2 = CONTROL. */\n\tmov r3, lr\t\t\t\t\t\t\t\t/* r3 = LR/EXC_RETURN. */\n\tstmdb r0!, {r1-r11}\t\t\t\t\t\t/* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */\n#else /* configENABLE_MPU */\n\tmrs r2, psplim\t\t\t\t\t\t\t/* r2 = PSPLIM. */\n\tmov r3, lr\t\t\t\t\t\t\t\t/* r3 = LR/EXC_RETURN. */\n\tstmdb r0!, {r2-r11}\t\t\t\t\t\t/* Store on the stack - PSPLIM, LR and registers that are not automatically. */\n#endif /* configENABLE_MPU */\n\n\tldr r2, =pxCurrentTCB\t\t\t\t\t/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n\tldr r1, [r2]\t\t\t\t\t\t\t/* Read pxCurrentTCB. */\n\tstr r0, [r1]\t\t\t\t\t\t\t/* Save the new top of stack in TCB. */\n\n\tmov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY\n\tmsr basepri, r0\t\t\t\t\t\t\t/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */\n\tdsb\n\tisb\n\tbl vTaskSwitchContext\n\tmov r0, #0\t\t\t\t\t\t\t\t/* r0 = 0. */\n\tmsr basepri, r0\t\t\t\t\t\t\t/* Enable interrupts. */\n\n\tldr r2, =pxCurrentTCB\t\t\t\t\t/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n\tldr r1, [r2]\t\t\t\t\t\t\t/* Read pxCurrentTCB. */\n\tldr r0, [r1]\t\t\t\t\t\t\t/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */\n\n#if ( configENABLE_MPU == 1 )\n\tdmb\t\t\t\t\t\t\t\t\t\t/* Complete outstanding transfers before disabling MPU. */\n\tldr r2, =0xe000ed94\t\t\t\t\t\t/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n\tldr r4, [r2]\t\t\t\t\t\t\t/* Read the value of MPU_CTRL. */\n\tbic r4, r4, #1\t\t\t\t\t\t\t/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\n\tstr r4, [r2]\t\t\t\t\t\t\t/* Disable MPU. */\n\n\tadds r1, #4\t\t\t\t\t\t\t\t/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\n\tldr r3, [r1]\t\t\t\t\t\t\t/* r3 = *r1 i.e. r3 = MAIR0. */\n\tldr r2, =0xe000edc0\t\t\t\t\t\t/* r2 = 0xe000edc0 [Location of MAIR0]. */\n\tstr r3, [r2]\t\t\t\t\t\t\t/* Program MAIR0. */\n\tldr r2, =0xe000ed98\t\t\t\t\t\t/* r2 = 0xe000ed98 [Location of RNR]. */\n\tmovs r3, #4\t\t\t\t\t\t\t\t/* r3 = 4. */\n\tstr r3, [r2]\t\t\t\t\t\t\t/* Program RNR = 4. */\n\tadds r1, #4\t\t\t\t\t\t\t\t/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\n\tldr r2, =0xe000ed9c\t\t\t\t\t\t/* r2 = 0xe000ed9c [Location of RBAR]. */\n\tldmia r1!, {r4-r11}\t\t\t\t\t\t/* Read 4 sets of RBAR/RLAR registers from TCB. */\n\tstmia r2!, {r4-r11}\t\t\t\t\t\t/* Write 4 set of RBAR/RLAR registers using alias registers. */\n\n\tldr r2, =0xe000ed94\t\t\t\t\t\t/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n\tldr r4, [r2]\t\t\t\t\t\t\t/* Read the value of MPU_CTRL. */\n\torr r4, r4, #1\t\t\t\t\t\t\t/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\n\tstr r4, [r2]\t\t\t\t\t\t\t/* Enable MPU. */\n\tdsb\t\t\t\t\t\t\t\t\t\t/* Force memory writes before continuing. */\n#endif /* configENABLE_MPU */\n\n#if ( configENABLE_MPU == 1 )\n\tldmia r0!, {r1-r11}\t\t\t\t\t\t/* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */\n#else /* configENABLE_MPU */\n\tldmia r0!, {r2-r11}\t\t\t\t\t\t/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */\n#endif /* configENABLE_MPU */\n\n#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )\n\ttst r3, #0x10\t\t\t\t\t\t\t/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */\n\tit eq\n\tvldmiaeq r0!, {s16-s31}\t\t\t\t\t/* Restore the additional FP context registers which are not restored automatically. */\n#endif /* configENABLE_FPU || configENABLE_MVE */\n\n #if ( configENABLE_MPU == 1 )\n\tmsr psplim, r1\t\t\t\t\t\t\t/* Restore the PSPLIM register value for the task. */\n\tmsr control, r2\t\t\t\t\t\t\t/* Restore the CONTROL register value for the task. */\n#else /* configENABLE_MPU */\n\tmsr psplim, r2\t\t\t\t\t\t\t/* Restore the PSPLIM register value for the task. */\n#endif /* configENABLE_MPU */\n\tmsr psp, r0\t\t\t\t\t\t\t\t/* Remember the new top of stack for the task. */\n\tbx r3\n/*-----------------------------------------------------------*/\n\nSVC_Handler:\n\ttst lr, #4\n\tite eq\n\tmrseq r0, msp\n\tmrsne r0, psp\n\tb vPortSVCHandler_C\n/*-----------------------------------------------------------*/\n\n\tEND\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef PORTMACRO_H\n#define PORTMACRO_H\n\n#ifdef __cplusplus\n    extern \"C\" {\n#endif\n\n#include \"portmacrocommon.h\"\n\n/*------------------------------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the given hardware\n * and compiler.\n *\n * These settings should not be altered.\n *------------------------------------------------------------------------------\n */\n\n/**\n * Architecture specifics.\n */\n#define portARCH_NAME                       \"Cortex-M33\"\n#define portDONT_DISCARD                    __root\n/*-----------------------------------------------------------*/\n\n#if( configTOTAL_MPU_REGIONS == 16 )\n    #error 16 MPU regions are not yet supported for this port.\n#endif\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Critical section management.\n */\n#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()\n#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )\n/*-----------------------------------------------------------*/\n\n/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in\n * the source code because to do so would cause other compilers to generate\n * warnings. */\n#pragma diag_suppress=Be006\n#pragma diag_suppress=Pa082\n/*-----------------------------------------------------------*/\n\n#ifdef __cplusplus\n    }\n#endif\n\n#endif /* PORTMACRO_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/ARMv8M/non_secure/portable/IAR/ARM_CM55/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef PORTMACRO_H\n#define PORTMACRO_H\n\n#ifdef __cplusplus\n    extern \"C\" {\n#endif\n\n#include \"portmacrocommon.h\"\n\n/*------------------------------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the given hardware\n * and compiler.\n *\n * These settings should not be altered.\n *------------------------------------------------------------------------------\n */\n\n#ifndef configENABLE_MVE\n    #error configENABLE_MVE must be defined in FreeRTOSConfig.h. Set configENABLE_MVE to 1 to enable the MVE or 0 to disable the MVE.\n#endif /* configENABLE_MVE */\n/*-----------------------------------------------------------*/\n\n/**\n * Architecture specifics.\n */\n#define portARCH_NAME                       \"Cortex-M55\"\n#define portDONT_DISCARD                    __root\n/*-----------------------------------------------------------*/\n\n#if( configTOTAL_MPU_REGIONS == 16 )\n    #error 16 MPU regions are not yet supported for this port.\n#endif\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Critical section management.\n */\n#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()\n#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )\n/*-----------------------------------------------------------*/\n\n/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in\n * the source code because to do so would cause other compilers to generate\n * warnings. */\n#pragma diag_suppress=Be006\n#pragma diag_suppress=Pa082\n/*-----------------------------------------------------------*/\n\n#ifdef __cplusplus\n    }\n#endif\n\n#endif /* PORTMACRO_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/ARMv8M/non_secure/portable/IAR/ARM_CM85/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef PORTMACRO_H\n#define PORTMACRO_H\n\n#ifdef __cplusplus\n    extern \"C\" {\n#endif\n\n#include \"portmacrocommon.h\"\n\n/*------------------------------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the given hardware\n * and compiler.\n *\n * These settings should not be altered.\n *------------------------------------------------------------------------------\n */\n\n#ifndef configENABLE_MVE\n    #error configENABLE_MVE must be defined in FreeRTOSConfig.h. Set configENABLE_MVE to 1 to enable the MVE or 0 to disable the MVE.\n#endif /* configENABLE_MVE */\n/*-----------------------------------------------------------*/\n\n/**\n * Architecture specifics.\n */\n#define portARCH_NAME                       \"Cortex-M85\"\n#define portDONT_DISCARD                    __root\n/*-----------------------------------------------------------*/\n\n#if( configTOTAL_MPU_REGIONS == 16 )\n    #error 16 MPU regions are not yet supported for this port.\n#endif\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Critical section management.\n */\n#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()\n#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )\n/*-----------------------------------------------------------*/\n\n/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in\n * the source code because to do so would cause other compilers to generate\n * warnings. */\n#pragma diag_suppress=Be006\n#pragma diag_suppress=Pa082\n/*-----------------------------------------------------------*/\n\n#ifdef __cplusplus\n    }\n#endif\n\n#endif /* PORTMACRO_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/ARMv8M/non_secure/portasm.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef __PORT_ASM_H__\n#define __PORT_ASM_H__\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n\n/* MPU wrappers includes. */\n#include \"mpu_wrappers.h\"\n\n/**\n * @brief Restore the context of the first task so that the first task starts\n * executing.\n */\nvoid vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Checks whether or not the processor is privileged.\n *\n * @return 1 if the processor is already privileged, 0 otherwise.\n */\nBaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );\n\n/**\n * @brief Raises the privilege level by clearing the bit 0 of the CONTROL\n * register.\n *\n * @note This is a privileged function and should only be called from the kenrel\n * code.\n *\n * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.\n *  Bit[0] = 0 --> The processor is running privileged\n *  Bit[0] = 1 --> The processor is running unprivileged.\n */\nvoid vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\n * register.\n *\n * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.\n *  Bit[0] = 0 --> The processor is running privileged\n *  Bit[0] = 1 --> The processor is running unprivileged.\n */\nvoid vResetPrivilege( void ) __attribute__( ( naked ) );\n\n/**\n * @brief Starts the first task.\n */\nvoid vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Disables interrupts.\n */\nuint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Enables interrupts.\n */\nvoid vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief PendSV Exception handler.\n */\nvoid PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief SVC Handler.\n */\nvoid SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Allocate a Secure context for the calling task.\n *\n * @param[in] ulSecureStackSize The size of the stack to be allocated on the\n * secure side for the calling task.\n */\nvoid vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) );\n\n/**\n * @brief Free the task's secure context.\n *\n * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.\n */\nvoid vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n#endif /* __PORT_ASM_H__ */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/ARMv8M/non_secure/portmacrocommon.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef PORTMACROCOMMON_H\n    #define PORTMACROCOMMON_H\n\n    #ifdef __cplusplus\n        extern \"C\" {\n    #endif\n\n/*------------------------------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the given hardware\n * and compiler.\n *\n * These settings should not be altered.\n *------------------------------------------------------------------------------\n */\n\n    #ifndef configENABLE_FPU\n        #error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.\n    #endif /* configENABLE_FPU */\n\n    #ifndef configENABLE_MPU\n        #error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.\n    #endif /* configENABLE_MPU */\n\n    #ifndef configENABLE_TRUSTZONE\n        #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.\n    #endif /* configENABLE_TRUSTZONE */\n\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Type definitions.\n */\n    #define portCHAR          char\n    #define portFLOAT         float\n    #define portDOUBLE        double\n    #define portLONG          long\n    #define portSHORT         short\n    #define portSTACK_TYPE    uint32_t\n    #define portBASE_TYPE     long\n\n    typedef portSTACK_TYPE   StackType_t;\n    typedef long             BaseType_t;\n    typedef unsigned long    UBaseType_t;\n\n    #if ( configUSE_16_BIT_TICKS == 1 )\n        typedef uint16_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffff\n    #else\n        typedef uint32_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL\n\n/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\n * not need to be guarded with a critical section. */\n        #define portTICK_TYPE_IS_ATOMIC    1\n    #endif\n/*-----------------------------------------------------------*/\n\n/**\n * Architecture specifics.\n */\n    #define portSTACK_GROWTH                   ( -1 )\n    #define portTICK_PERIOD_MS                 ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\n    #define portBYTE_ALIGNMENT                 8\n    #define portNOP()\n    #define portINLINE                         __inline\n    #ifndef portFORCE_INLINE\n        #define portFORCE_INLINE               inline __attribute__( ( always_inline ) )\n    #endif\n    #define portHAS_STACK_OVERFLOW_CHECKING    1\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Extern declarations.\n */\n    extern BaseType_t xPortIsInsideInterrupt( void );\n\n    extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;\n\n    extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;\n    extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;\n\n    extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\n    extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\n\n    #if ( configENABLE_TRUSTZONE == 1 )\n        extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */\n        extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;\n    #endif /* configENABLE_TRUSTZONE */\n\n    #if ( configENABLE_MPU == 1 )\n        extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;\n        extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;\n    #endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\n/**\n * @brief MPU specific constants.\n */\n    #if ( configENABLE_MPU == 1 )\n        #define portUSING_MPU_WRAPPERS    1\n        #define portPRIVILEGE_BIT         ( 0x80000000UL )\n    #else\n        #define portPRIVILEGE_BIT         ( 0x0UL )\n    #endif /* configENABLE_MPU */\n\n/* MPU settings that can be overriden in FreeRTOSConfig.h. */\n#ifndef configTOTAL_MPU_REGIONS\n    /* Define to 8 for backward compatibility. */\n    #define configTOTAL_MPU_REGIONS       ( 8UL )\n#endif\n\n/* MPU regions. */\n    #define portPRIVILEGED_FLASH_REGION                   ( 0UL )\n    #define portUNPRIVILEGED_FLASH_REGION                 ( 1UL )\n    #define portUNPRIVILEGED_SYSCALLS_REGION              ( 2UL )\n    #define portPRIVILEGED_RAM_REGION                     ( 3UL )\n    #define portSTACK_REGION                              ( 4UL )\n    #define portFIRST_CONFIGURABLE_REGION                 ( 5UL )\n    #define portLAST_CONFIGURABLE_REGION                  ( configTOTAL_MPU_REGIONS - 1UL )\n    #define portNUM_CONFIGURABLE_REGIONS                  ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )\n    #define portTOTAL_NUM_REGIONS                         ( portNUM_CONFIGURABLE_REGIONS + 1 )   /* Plus one to make space for the stack region. */\n\n/* Device memory attributes used in MPU_MAIR registers.\n *\n * 8-bit values encoded as follows:\n *  Bit[7:4] - 0000 - Device Memory\n *  Bit[3:2] - 00 --> Device-nGnRnE\n *\t\t\t\t01 --> Device-nGnRE\n *\t\t\t\t10 --> Device-nGRE\n *\t\t\t\t11 --> Device-GRE\n *  Bit[1:0] - 00, Reserved.\n */\n    #define portMPU_DEVICE_MEMORY_nGnRnE                  ( 0x00 )   /* 0000 0000 */\n    #define portMPU_DEVICE_MEMORY_nGnRE                   ( 0x04 )   /* 0000 0100 */\n    #define portMPU_DEVICE_MEMORY_nGRE                    ( 0x08 )   /* 0000 1000 */\n    #define portMPU_DEVICE_MEMORY_GRE                     ( 0x0C )   /* 0000 1100 */\n\n/* Normal memory attributes used in MPU_MAIR registers. */\n    #define portMPU_NORMAL_MEMORY_NON_CACHEABLE           ( 0x44 )   /* Non-cacheable. */\n    #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE    ( 0xFF )   /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */\n\n/* Attributes used in MPU_RBAR registers. */\n    #define portMPU_REGION_NON_SHAREABLE                  ( 0UL << 3UL )\n    #define portMPU_REGION_INNER_SHAREABLE                ( 1UL << 3UL )\n    #define portMPU_REGION_OUTER_SHAREABLE                ( 2UL << 3UL )\n\n    #define portMPU_REGION_PRIVILEGED_READ_WRITE          ( 0UL << 1UL )\n    #define portMPU_REGION_READ_WRITE                     ( 1UL << 1UL )\n    #define portMPU_REGION_PRIVILEGED_READ_ONLY           ( 2UL << 1UL )\n    #define portMPU_REGION_READ_ONLY                      ( 3UL << 1UL )\n\n    #define portMPU_REGION_EXECUTE_NEVER                  ( 1UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Settings to define an MPU region.\n */\n    typedef struct MPURegionSettings\n    {\n        uint32_t ulRBAR; /**< RBAR for the region. */\n        uint32_t ulRLAR; /**< RLAR for the region. */\n    } MPURegionSettings_t;\n\n/**\n * @brief MPU settings as stored in the TCB.\n */\n    typedef struct MPU_SETTINGS\n    {\n        uint32_t ulMAIR0;                                              /**< MAIR0 for the task containing attributes for all the 4 per task regions. */\n        MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */\n    } xMPU_SETTINGS;\n/*-----------------------------------------------------------*/\n\n/**\n * @brief SVC numbers.\n */\n    #define portSVC_ALLOCATE_SECURE_CONTEXT    0\n    #define portSVC_FREE_SECURE_CONTEXT        1\n    #define portSVC_START_SCHEDULER            2\n    #define portSVC_RAISE_PRIVILEGE            3\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Scheduler utilities.\n */\n    #define portYIELD()                                 vPortYield()\n    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )\n    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )\n    #define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )\n    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Critical section management.\n */\n    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulSetInterruptMask()\n    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vClearInterruptMask( x )\n    #define portENTER_CRITICAL()                      vPortEnterCritical()\n    #define portEXIT_CRITICAL()                       vPortExitCritical()\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Tickless idle/low power functionality.\n */\n    #ifndef portSUPPRESS_TICKS_AND_SLEEP\n        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );\n        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )\n    #endif\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Task function macros as described on the FreeRTOS.org WEB site.\n */\n    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )\n    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )\n/*-----------------------------------------------------------*/\n\n    #if ( configENABLE_TRUSTZONE == 1 )\n\n/**\n * @brief Allocate a secure context for the task.\n *\n * Tasks are not created with a secure context. Any task that is going to call\n * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a\n * secure context before it calls any secure function.\n *\n * @param[in] ulSecureStackSize The size of the secure stack to be allocated.\n */\n        #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )\n\n/**\n * @brief Called when a task is deleted to delete the task's secure context,\n * if it has one.\n *\n * @param[in] pxTCB The TCB of the task being deleted.\n */\n        #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )\n    #endif /* configENABLE_TRUSTZONE */\n/*-----------------------------------------------------------*/\n\n    #if ( configENABLE_MPU == 1 )\n\n/**\n * @brief Checks whether or not the processor is privileged.\n *\n * @return 1 if the processor is already privileged, 0 otherwise.\n */\n        #define portIS_PRIVILEGED()      xIsPrivileged()\n\n/**\n * @brief Raise an SVC request to raise privilege.\n *\n * The SVC handler checks that the SVC was raised from a system call and only\n * then it raises the privilege. If this is called from any other place,\n * the privilege is not raised.\n */\n        #define portRAISE_PRIVILEGE()    __asm volatile ( \"svc %0 \\n\" ::\"i\" ( portSVC_RAISE_PRIVILEGE ) : \"memory\" );\n\n/**\n * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\n * register.\n */\n        #define portRESET_PRIVILEGE()    vResetPrivilege()\n    #else\n        #define portIS_PRIVILEGED()\n        #define portRAISE_PRIVILEGE()\n        #define portRESET_PRIVILEGE()\n    #endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Barriers.\n */\n    #define portMEMORY_BARRIER()    __asm volatile ( \"\" ::: \"memory\" )\n/*-----------------------------------------------------------*/\n\n    #ifdef __cplusplus\n        }\n    #endif\n\n#endif /* PORTMACROCOMMON_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/ARMv8M/secure/ReadMe.txt",
    "content": "This directory tree contains the master copy of the FreeRTOS Armv8-M and\nArmv8.1-M ports.\nDo not use the files located here!  These file are copied into separate\nFreeRTOS/Source/portable/[compiler]/ARM_CM[23|33|55|85]_NNN directories prior to\neach FreeRTOS release.\n\nIf your Armv8-M/Armv8.1-M application uses TrustZone then use the files from the\nFreeRTOS/Source/portable/[compiler]/ARM_CM[23|33|55|85] directories.\n\nIf your Armv8-M/Armv8.1-M application does not use TrustZone then use the files from\nthe FreeRTOS/Source/portable/[compiler]/ARM_CM[23|33|55|85]_NTZ directories.\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/ARMv8M/secure/context/portable/GCC/ARM_CM23/secure_context_port.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Secure context includes. */\n#include \"secure_context.h\"\n\n/* Secure port macros. */\n#include \"secure_port_macros.h\"\n\n#if ( configENABLE_FPU == 1 )\n    #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.\n#endif\n\nvoid SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) );\nvoid SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) );\n\nvoid SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext )\n{\n    /* pxSecureContext value is in r0. */\n    __asm volatile\n    (\n        \" .syntax unified                   \\n\"\n        \"                                   \\n\"\n        \" mrs r1, ipsr                      \\n\" /* r1 = IPSR. */\n        \" cbz r1, load_ctx_therad_mode      \\n\" /* Do nothing if the processor is running in the Thread Mode. */\n        \" ldmia r0!, {r1, r2}               \\n\" /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */\n        \"                                   \\n\"\n        #if ( configENABLE_MPU == 1 )\n            \" ldmia r1!, {r3}               \\n\" /* Read CONTROL register value from task's stack. r3 = CONTROL. */\n            \" msr control, r3               \\n\" /* CONTROL = r3. */\n        #endif /* configENABLE_MPU */\n        \"                                   \\n\"\n        \" msr psplim, r2                    \\n\" /* PSPLIM = r2. */\n        \" msr psp, r1                       \\n\" /* PSP = r1. */\n        \"                                   \\n\"\n        \" load_ctx_therad_mode:             \\n\"\n        \"    bx lr                          \\n\"\n        \"                                   \\n\"\n        ::: \"r0\", \"r1\", \"r2\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext )\n{\n    /* pxSecureContext value is in r0. */\n    __asm volatile\n    (\n        \" .syntax unified                   \\n\"\n        \"                                   \\n\"\n        \" mrs r1, ipsr                      \\n\" /* r1 = IPSR. */\n        \" cbz r1, save_ctx_therad_mode      \\n\" /* Do nothing if the processor is running in the Thread Mode. */\n        \" mrs r1, psp                       \\n\" /* r1 = PSP. */\n        \"                                   \\n\"\n        #if ( configENABLE_MPU == 1 )\n            \" mrs r2, control               \\n\" /* r2 = CONTROL. */\n            \" subs r1, r1, #4               \\n\" /* Make space for the CONTROL value on the stack. */\n            \" str r1, [r0]                  \\n\" /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */\n            \" stmia r1!, {r2}               \\n\" /* Store CONTROL value on the stack. */\n        #else /* configENABLE_MPU */\n            \" str r1, [r0]                  \\n\" /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */\n        #endif /* configENABLE_MPU */\n        \"                                   \\n\"\n        \" movs r1, %0                       \\n\" /* r1 = securecontextNO_STACK. */\n        \" msr psplim, r1                    \\n\" /* PSPLIM = securecontextNO_STACK. */\n        \" msr psp, r1                       \\n\" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */\n        \"                                   \\n\"\n        \" save_ctx_therad_mode:             \\n\"\n        \"   bx lr                           \\n\"\n        \"                                   \\n\"\n        ::\"i\" ( securecontextNO_STACK ) : \"r1\", \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/ARMv8M/secure/context/portable/GCC/ARM_CM33/secure_context_port.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Secure context includes. */\n#include \"secure_context.h\"\n\n/* Secure port macros. */\n#include \"secure_port_macros.h\"\n\nvoid SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) );\nvoid SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) );\n\nvoid SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext )\n{\n    /* pxSecureContext value is in r0. */\n    __asm volatile\n    (\n        \" .syntax unified                   \\n\"\n        \"                                   \\n\"\n        \" mrs r1, ipsr                      \\n\" /* r1 = IPSR. */\n        \" cbz r1, load_ctx_therad_mode      \\n\" /* Do nothing if the processor is running in the Thread Mode. */\n        \" ldmia r0!, {r1, r2}               \\n\" /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */\n        \"                                   \\n\"\n        #if ( configENABLE_MPU == 1 )\n            \" ldmia r1!, {r3}               \\n\" /* Read CONTROL register value from task's stack. r3 = CONTROL. */\n            \" msr control, r3               \\n\" /* CONTROL = r3. */\n        #endif /* configENABLE_MPU */\n        \"                                   \\n\"\n        \" msr psplim, r2                    \\n\" /* PSPLIM = r2. */\n        \" msr psp, r1                       \\n\" /* PSP = r1. */\n        \"                                   \\n\"\n        \" load_ctx_therad_mode:             \\n\"\n        \"    bx lr                          \\n\"\n        \"                                   \\n\"\n        ::: \"r0\", \"r1\", \"r2\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext )\n{\n    /* pxSecureContext value is in r0. */\n    __asm volatile\n    (\n        \" .syntax unified                   \\n\"\n        \"                                   \\n\"\n        \" mrs r1, ipsr                      \\n\" /* r1 = IPSR. */\n        \" cbz r1, save_ctx_therad_mode      \\n\" /* Do nothing if the processor is running in the Thread Mode. */\n        \" mrs r1, psp                       \\n\" /* r1 = PSP. */\n        \"                                   \\n\"\n        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )\n            \" vstmdb r1!, {s0}              \\n\" /* Trigger the deferred stacking of FPU registers. */\n            \" vldmia r1!, {s0}              \\n\" /* Nullify the effect of the previous statement. */\n        #endif /* configENABLE_FPU || configENABLE_MVE */\n        \"                                   \\n\"\n        #if ( configENABLE_MPU == 1 )\n            \" mrs r2, control               \\n\" /* r2 = CONTROL. */\n            \" stmdb r1!, {r2}               \\n\" /* Store CONTROL value on the stack. */\n        #endif /* configENABLE_MPU */\n        \"                                   \\n\"\n        \" str r1, [r0]                      \\n\" /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */\n        \" movs r1, %0                       \\n\" /* r1 = securecontextNO_STACK. */\n        \" msr psplim, r1                    \\n\" /* PSPLIM = securecontextNO_STACK. */\n        \" msr psp, r1                       \\n\" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */\n        \"                                   \\n\"\n        \" save_ctx_therad_mode:             \\n\"\n        \"    bx lr                          \\n\"\n        \"                                   \\n\"\n        ::\"i\" ( securecontextNO_STACK ) : \"r1\", \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/ARMv8M/secure/context/portable/IAR/ARM_CM23/secure_context_port_asm.s",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n    SECTION .text:CODE:NOROOT(2)\n    THUMB\n\n/* Including FreeRTOSConfig.h here will cause build errors if the header file\ncontains code not understood by the assembler - for example the 'extern' keyword.\nTo avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so\nthe code is included in C files but excluded by the preprocessor in assembly\nfiles (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */\n#include \"FreeRTOSConfig.h\"\n\n    PUBLIC SecureContext_LoadContextAsm\n    PUBLIC SecureContext_SaveContextAsm\n\n#if ( configENABLE_FPU == 1 )\n    #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.\n#endif\n/*-----------------------------------------------------------*/\n\nSecureContext_LoadContextAsm:\n    /* pxSecureContext value is in r0. */\n    mrs r1, ipsr                    /* r1 = IPSR. */\n    cbz r1, load_ctx_therad_mode    /* Do nothing if the processor is running in the Thread Mode. */\n    ldmia r0!, {r1, r2}             /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */\n\n#if ( configENABLE_MPU == 1 )\n    ldmia r1!, {r3}                 /* Read CONTROL register value from task's stack. r3 = CONTROL. */\n    msr control, r3                 /* CONTROL = r3. */\n#endif /* configENABLE_MPU */\n\n    msr psplim, r2                  /* PSPLIM = r2. */\n    msr psp, r1                     /* PSP = r1. */\n\n    load_ctx_therad_mode:\n        bx lr\n/*-----------------------------------------------------------*/\n\nSecureContext_SaveContextAsm:\n    /* pxSecureContext value is in r0. */\n    mrs r1, ipsr                    /* r1 = IPSR. */\n    cbz r1, save_ctx_therad_mode    /* Do nothing if the processor is running in the Thread Mode. */\n    mrs r1, psp                     /* r1 = PSP. */\n\n#if ( configENABLE_MPU == 1 )\n    mrs r2, control                 /* r2 = CONTROL. */\n    subs r1, r1, #4                 /* Make space for the CONTROL value on the stack. */\n    str r1, [r0]                    /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */\n    stmia r1!, {r2}                 /* Store CONTROL value on the stack. */\n#else /* configENABLE_MPU */\n    str r1, [r0]                    /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */\n#endif /* configENABLE_MPU */\n\n    movs r1, #0                     /* r1 = securecontextNO_STACK. */\n    msr psplim, r1                  /* PSPLIM = securecontextNO_STACK. */\n    msr psp, r1                     /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */\n\n    save_ctx_therad_mode:\n        bx lr\n/*-----------------------------------------------------------*/\n\n    END\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/ARMv8M/secure/context/portable/IAR/ARM_CM33/secure_context_port_asm.s",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n    SECTION .text:CODE:NOROOT(2)\n    THUMB\n\n/* Including FreeRTOSConfig.h here will cause build errors if the header file\ncontains code not understood by the assembler - for example the 'extern' keyword.\nTo avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so\nthe code is included in C files but excluded by the preprocessor in assembly\nfiles (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */\n#include \"FreeRTOSConfig.h\"\n\n    PUBLIC SecureContext_LoadContextAsm\n    PUBLIC SecureContext_SaveContextAsm\n/*-----------------------------------------------------------*/\n\nSecureContext_LoadContextAsm:\n    /* pxSecureContext value is in r0. */\n    mrs r1, ipsr                        /* r1 = IPSR. */\n    cbz r1, load_ctx_therad_mode        /* Do nothing if the processor is running in the Thread Mode. */\n    ldmia r0!, {r1, r2}                 /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */\n\n#if ( configENABLE_MPU == 1 )\n    ldmia r1!, {r3}                     /* Read CONTROL register value from task's stack. r3 = CONTROL. */\n    msr control, r3                     /* CONTROL = r3. */\n#endif /* configENABLE_MPU */\n\n    msr psplim, r2                      /* PSPLIM = r2. */\n    msr psp, r1                         /* PSP = r1. */\n\n    load_ctx_therad_mode:\n        bx lr\n/*-----------------------------------------------------------*/\n\nSecureContext_SaveContextAsm:\n    /* pxSecureContext value is in r0. */\n    mrs r1, ipsr                        /* r1 = IPSR. */\n    cbz r1, save_ctx_therad_mode        /* Do nothing if the processor is running in the Thread Mode. */\n    mrs r1, psp                         /* r1 = PSP. */\n\n#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )\n    vstmdb r1!, {s0}                    /* Trigger the deferred stacking of FPU registers. */\n    vldmia r1!, {s0}                    /* Nullify the effect of the previous statement. */\n#endif /* configENABLE_FPU || configENABLE_MVE */\n\n#if ( configENABLE_MPU == 1 )\n    mrs r2, control                     /* r2 = CONTROL. */\n    stmdb r1!, {r2}                     /* Store CONTROL value on the stack. */\n#endif /* configENABLE_MPU */\n\n    str r1, [r0]                        /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */\n    movs r1, #0                         /* r1 = securecontextNO_STACK. */\n    msr psplim, r1                      /* PSPLIM = securecontextNO_STACK. */\n    msr psp, r1                         /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */\n\n    save_ctx_therad_mode:\n        bx lr\n/*-----------------------------------------------------------*/\n\n    END\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/ARMv8M/secure/context/secure_context.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Secure context includes. */\n#include \"secure_context.h\"\n\n/* Secure heap includes. */\n#include \"secure_heap.h\"\n\n/* Secure port macros. */\n#include \"secure_port_macros.h\"\n\n/**\n * @brief CONTROL value for privileged tasks.\n *\n * Bit[0] - 0 --> Thread mode is privileged.\n * Bit[1] - 1 --> Thread mode uses PSP.\n */\n#define securecontextCONTROL_VALUE_PRIVILEGED      0x02\n\n/**\n * @brief CONTROL value for un-privileged tasks.\n *\n * Bit[0] - 1 --> Thread mode is un-privileged.\n * Bit[1] - 1 --> Thread mode uses PSP.\n */\n#define securecontextCONTROL_VALUE_UNPRIVILEGED    0x03\n\n/**\n * @brief Size of stack seal values in bytes.\n */\n#define securecontextSTACK_SEAL_SIZE               8\n\n/**\n * @brief Stack seal value as recommended by ARM.\n */\n#define securecontextSTACK_SEAL_VALUE              0xFEF5EDA5\n\n/**\n * @brief Maximum number of secure contexts.\n */\n#ifndef secureconfigMAX_SECURE_CONTEXTS\n    #define secureconfigMAX_SECURE_CONTEXTS        8UL\n#endif\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Pre-allocated array of secure contexts.\n */\nSecureContext_t xSecureContexts[ secureconfigMAX_SECURE_CONTEXTS ];\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Get a free secure context for a task from the secure context pool (xSecureContexts).\n *\n * This function ensures that only one secure context is allocated for a task.\n *\n * @param[in] pvTaskHandle The task handle for which the secure context is allocated.\n *\n * @return Index of a free secure context in the xSecureContexts array.\n */\nstatic uint32_t ulGetSecureContext( void * pvTaskHandle );\n\n/**\n * @brief Return the secure context to the secure context pool (xSecureContexts).\n *\n * @param[in] ulSecureContextIndex Index of the context in the xSecureContexts array.\n */\nstatic void vReturnSecureContext( uint32_t ulSecureContextIndex );\n\n/* These are implemented in assembly. */\nextern void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext );\nextern void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext );\n/*-----------------------------------------------------------*/\n\nstatic uint32_t ulGetSecureContext( void * pvTaskHandle )\n{\n    /* Start with invalid index. */\n    uint32_t i, ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS;\n\n    for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ )\n    {\n        if( ( xSecureContexts[ i ].pucCurrentStackPointer == NULL ) &&\n            ( xSecureContexts[ i ].pucStackLimit == NULL ) &&\n            ( xSecureContexts[ i ].pucStackStart == NULL ) &&\n            ( xSecureContexts[ i ].pvTaskHandle == NULL ) &&\n            ( ulSecureContextIndex == secureconfigMAX_SECURE_CONTEXTS ) )\n        {\n            ulSecureContextIndex = i;\n        }\n        else if( xSecureContexts[ i ].pvTaskHandle == pvTaskHandle )\n        {\n            /* A task can only have one secure context. Do not allocate a second\n             * context for the same task. */\n            ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS;\n            break;\n        }\n    }\n\n    return ulSecureContextIndex;\n}\n/*-----------------------------------------------------------*/\n\nstatic void vReturnSecureContext( uint32_t ulSecureContextIndex )\n{\n    xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = NULL;\n    xSecureContexts[ ulSecureContextIndex ].pucStackLimit = NULL;\n    xSecureContexts[ ulSecureContextIndex ].pucStackStart = NULL;\n    xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = NULL;\n}\n/*-----------------------------------------------------------*/\n\nsecureportNON_SECURE_CALLABLE void SecureContext_Init( void )\n{\n    uint32_t ulIPSR, i;\n    static uint32_t ulSecureContextsInitialized = 0;\n\n    /* Read the Interrupt Program Status Register (IPSR) value. */\n    secureportREAD_IPSR( ulIPSR );\n\n    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\n     * when the processor is running in the Thread Mode. */\n    if( ( ulIPSR != 0 ) && ( ulSecureContextsInitialized == 0 ) )\n    {\n        /* Ensure to initialize secure contexts only once. */\n        ulSecureContextsInitialized = 1;\n\n        /* No stack for thread mode until a task's context is loaded. */\n        secureportSET_PSPLIM( securecontextNO_STACK );\n        secureportSET_PSP( securecontextNO_STACK );\n\n        /* Initialize all secure contexts. */\n        for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ )\n        {\n            xSecureContexts[ i ].pucCurrentStackPointer = NULL;\n            xSecureContexts[ i ].pucStackLimit = NULL;\n            xSecureContexts[ i ].pucStackStart = NULL;\n            xSecureContexts[ i ].pvTaskHandle = NULL;\n        }\n\n        #if ( configENABLE_MPU == 1 )\n            {\n                /* Configure thread mode to use PSP and to be unprivileged. */\n                secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );\n            }\n        #else /* configENABLE_MPU */\n            {\n                /* Configure thread mode to use PSP and to be privileged. */\n                secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );\n            }\n        #endif /* configENABLE_MPU */\n    }\n}\n/*-----------------------------------------------------------*/\n\n#if ( configENABLE_MPU == 1 )\n    secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,\n                                                                                       uint32_t ulIsTaskPrivileged,\n                                                                                       void * pvTaskHandle )\n#else /* configENABLE_MPU */\n    secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,\n                                                                                       void * pvTaskHandle )\n#endif /* configENABLE_MPU */\n{\n    uint8_t * pucStackMemory = NULL;\n    uint8_t * pucStackLimit;\n    uint32_t ulIPSR, ulSecureContextIndex;\n    SecureContextHandle_t xSecureContextHandle = securecontextINVALID_CONTEXT_ID;\n\n    #if ( configENABLE_MPU == 1 )\n        uint32_t * pulCurrentStackPointer = NULL;\n    #endif /* configENABLE_MPU */\n\n    /* Read the Interrupt Program Status Register (IPSR) and Process Stack Limit\n     * Register (PSPLIM) value. */\n    secureportREAD_IPSR( ulIPSR );\n    secureportREAD_PSPLIM( pucStackLimit );\n\n    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\n     * when the processor is running in the Thread Mode.\n     * Also do nothing, if a secure context us already loaded. PSPLIM is set to\n     * securecontextNO_STACK when no secure context is loaded. */\n    if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) )\n    {\n        /* Ontain a free secure context. */\n        ulSecureContextIndex = ulGetSecureContext( pvTaskHandle );\n\n        /* Were we able to get a free context? */\n        if( ulSecureContextIndex < secureconfigMAX_SECURE_CONTEXTS )\n        {\n            /* Allocate the stack space. */\n            pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE );\n\n            if( pucStackMemory != NULL )\n            {\n                /* Since stack grows down, the starting point will be the last\n                 * location. Note that this location is next to the last\n                 * allocated byte for stack (excluding the space for seal values)\n                 * because the hardware decrements the stack pointer before\n                 * writing i.e. if stack pointer is 0x2, a push operation will\n                 * decrement the stack pointer to 0x1 and then write at 0x1. */\n                xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize;\n\n                /* Seal the created secure process stack. */\n                *( uint32_t * )( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE;\n                *( uint32_t * )( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE;\n\n                /* The stack cannot go beyond this location. This value is\n                 * programmed in the PSPLIM register on context switch.*/\n                xSecureContexts[ ulSecureContextIndex ].pucStackLimit = pucStackMemory;\n\n                xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle;\n\n                #if ( configENABLE_MPU == 1 )\n                    {\n                        /* Store the correct CONTROL value for the task on the stack.\n                         * This value is programmed in the CONTROL register on\n                         * context switch. */\n                        pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart;\n                        pulCurrentStackPointer--;\n\n                        if( ulIsTaskPrivileged )\n                        {\n                            *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;\n                        }\n                        else\n                        {\n                            *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;\n                        }\n\n                        /* Store the current stack pointer. This value is programmed in\n                         * the PSP register on context switch. */\n                        xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;\n                    }\n                #else /* configENABLE_MPU */\n                    {\n                        /* Current SP is set to the starting of the stack. This\n                         * value programmed in the PSP register on context switch. */\n                        xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart;\n                    }\n                #endif /* configENABLE_MPU */\n\n                /* Ensure to never return 0 as a valid context handle. */\n                xSecureContextHandle = ulSecureContextIndex + 1UL;\n            }\n        }\n    }\n\n    return xSecureContextHandle;\n}\n/*-----------------------------------------------------------*/\n\nsecureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )\n{\n    uint32_t ulIPSR, ulSecureContextIndex;\n\n    /* Read the Interrupt Program Status Register (IPSR) value. */\n    secureportREAD_IPSR( ulIPSR );\n\n    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\n     * when the processor is running in the Thread Mode. */\n    if( ulIPSR != 0 )\n    {\n        /* Only free if a valid context handle is passed. */\n        if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) )\n        {\n            ulSecureContextIndex = xSecureContextHandle - 1UL;\n\n            /* Ensure that the secure context being deleted is associated with\n             * the task. */\n            if( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle )\n            {\n                /* Free the stack space. */\n                vPortFree( xSecureContexts[ ulSecureContextIndex ].pucStackLimit );\n\n                /* Return the secure context back to the free secure contexts pool. */\n                vReturnSecureContext( ulSecureContextIndex );\n            }\n        }\n    }\n}\n/*-----------------------------------------------------------*/\n\nsecureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )\n{\n    uint8_t * pucStackLimit;\n    uint32_t ulSecureContextIndex;\n\n    if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) )\n    {\n        ulSecureContextIndex = xSecureContextHandle - 1UL;\n\n        secureportREAD_PSPLIM( pucStackLimit );\n\n        /* Ensure that no secure context is loaded and the task is loading it's\n         * own context. */\n        if( ( pucStackLimit == securecontextNO_STACK ) &&\n            ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) )\n        {\n            SecureContext_LoadContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) );\n        }\n    }\n}\n/*-----------------------------------------------------------*/\n\nsecureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )\n{\n    uint8_t * pucStackLimit;\n    uint32_t ulSecureContextIndex;\n\n    if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) )\n    {\n        ulSecureContextIndex = xSecureContextHandle - 1UL;\n\n        secureportREAD_PSPLIM( pucStackLimit );\n\n        /* Ensure that task's context is loaded and the task is saving it's own\n         * context. */\n        if( ( xSecureContexts[ ulSecureContextIndex ].pucStackLimit == pucStackLimit ) &&\n            ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) )\n        {\n            SecureContext_SaveContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) );\n        }\n    }\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/ARMv8M/secure/context/secure_context.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef __SECURE_CONTEXT_H__\n#define __SECURE_CONTEXT_H__\n\n/* Standard includes. */\n#include <stdint.h>\n\n/* FreeRTOS includes. */\n#include \"FreeRTOSConfig.h\"\n\n/**\n * @brief PSP value when no secure context is loaded.\n */\n#define securecontextNO_STACK               0x0\n\n/**\n * @brief Invalid context ID.\n */\n#define securecontextINVALID_CONTEXT_ID     0UL\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Structure to represent a secure context.\n *\n * @note Since stack grows down, pucStackStart is the highest address while\n * pucStackLimit is the first address of the allocated memory.\n */\ntypedef struct SecureContext\n{\n    uint8_t * pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */\n    uint8_t * pucStackLimit;          /**< Last location of the stack memory (PSPLIM). */\n    uint8_t * pucStackStart;          /**< First location of the stack memory. */\n    void * pvTaskHandle;              /**< Task handle of the task this context is associated with. */\n} SecureContext_t;\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Opaque handle for a secure context.\n */\ntypedef uint32_t SecureContextHandle_t;\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Initializes the secure context management system.\n *\n * PSP is set to NULL and therefore a task must allocate and load a context\n * before calling any secure side function in the thread mode.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n */\nvoid SecureContext_Init( void );\n\n/**\n * @brief Allocates a context on the secure side.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n *\n * @param[in] ulSecureStackSize Size of the stack to allocate on secure side.\n * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise.\n *\n * @return Opaque context handle if context is successfully allocated, NULL\n * otherwise.\n */\n#if ( configENABLE_MPU == 1 )\n    SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,\n                                                         uint32_t ulIsTaskPrivileged,\n                                                         void * pvTaskHandle );\n#else /* configENABLE_MPU */\n    SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,\n                                                         void * pvTaskHandle );\n#endif /* configENABLE_MPU */\n\n/**\n * @brief Frees the given context.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n *\n * @param[in] xSecureContextHandle Context handle corresponding to the\n * context to be freed.\n */\nvoid SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );\n\n/**\n * @brief Loads the given context.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n *\n * @param[in] xSecureContextHandle Context handle corresponding to the context\n * to be loaded.\n */\nvoid SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );\n\n/**\n * @brief Saves the given context.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n *\n * @param[in] xSecureContextHandle Context handle corresponding to the context\n * to be saved.\n */\nvoid SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );\n\n#endif /* __SECURE_CONTEXT_H__ */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/ARMv8M/secure/heap/secure_heap.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Standard includes. */\n#include <stdint.h>\n\n/* Secure context heap includes. */\n#include \"secure_heap.h\"\n\n/* Secure port macros. */\n#include \"secure_port_macros.h\"\n\n/**\n * @brief Total heap size.\n */\n#ifndef secureconfigTOTAL_HEAP_SIZE\n    #define secureconfigTOTAL_HEAP_SIZE    ( ( ( size_t ) ( 10 * 1024 ) ) )\n#endif\n\n/* No test marker by default. */\n#ifndef mtCOVERAGE_TEST_MARKER\n    #define mtCOVERAGE_TEST_MARKER()\n#endif\n\n/* No tracing by default. */\n#ifndef traceMALLOC\n    #define traceMALLOC( pvReturn, xWantedSize )\n#endif\n\n/* No tracing by default. */\n#ifndef traceFREE\n    #define traceFREE( pv, xBlockSize )\n#endif\n\n/* Block sizes must not get too small. */\n#define secureheapMINIMUM_BLOCK_SIZE    ( ( size_t ) ( xHeapStructSize << 1 ) )\n\n/* Assumes 8bit bytes! */\n#define secureheapBITS_PER_BYTE         ( ( size_t ) 8 )\n/*-----------------------------------------------------------*/\n\n/* Allocate the memory for the heap. */\n#if ( configAPPLICATION_ALLOCATED_HEAP == 1 )\n\n/* The application writer has already defined the array used for the RTOS\n* heap - probably so it can be placed in a special segment or address. */\n    extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];\n#else /* configAPPLICATION_ALLOCATED_HEAP */\n    static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];\n#endif /* configAPPLICATION_ALLOCATED_HEAP */\n\n/**\n * @brief The linked list structure.\n *\n * This is used to link free blocks in order of their memory address.\n */\ntypedef struct A_BLOCK_LINK\n{\n    struct A_BLOCK_LINK * pxNextFreeBlock; /**< The next free block in the list. */\n    size_t xBlockSize;                     /**< The size of the free block. */\n} BlockLink_t;\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Called automatically to setup the required heap structures the first\n * time pvPortMalloc() is called.\n */\nstatic void prvHeapInit( void );\n\n/**\n * @brief Inserts a block of memory that is being freed into the correct\n * position in the list of free memory blocks.\n *\n * The block being freed will be merged with the block in front it and/or the\n * block behind it if the memory blocks are adjacent to each other.\n *\n * @param[in] pxBlockToInsert The block being freed.\n */\nstatic void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert );\n/*-----------------------------------------------------------*/\n\n/**\n * @brief The size of the structure placed at the beginning of each allocated\n * memory block must by correctly byte aligned.\n */\nstatic const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );\n\n/**\n * @brief Create a couple of list links to mark the start and end of the list.\n */\nstatic BlockLink_t xStart;\nstatic BlockLink_t * pxEnd = NULL;\n\n/**\n * @brief Keeps track of the number of free bytes remaining, but says nothing\n * about fragmentation.\n */\nstatic size_t xFreeBytesRemaining = 0U;\nstatic size_t xMinimumEverFreeBytesRemaining = 0U;\n\n/**\n * @brief Gets set to the top bit of an size_t type.\n *\n * When this bit in the xBlockSize member of an BlockLink_t structure is set\n * then the block belongs to the application. When the bit is free the block is\n * still part of the free heap space.\n */\nstatic size_t xBlockAllocatedBit = 0;\n/*-----------------------------------------------------------*/\n\nstatic void prvHeapInit( void )\n{\n    BlockLink_t * pxFirstFreeBlock;\n    uint8_t * pucAlignedHeap;\n    size_t uxAddress;\n    size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE;\n\n    /* Ensure the heap starts on a correctly aligned boundary. */\n    uxAddress = ( size_t ) ucHeap;\n\n    if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 )\n    {\n        uxAddress += ( secureportBYTE_ALIGNMENT - 1 );\n        uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );\n        xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;\n    }\n\n    pucAlignedHeap = ( uint8_t * ) uxAddress;\n\n    /* xStart is used to hold a pointer to the first item in the list of free\n     * blocks.  The void cast is used to prevent compiler warnings. */\n    xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;\n    xStart.xBlockSize = ( size_t ) 0;\n\n    /* pxEnd is used to mark the end of the list of free blocks and is inserted\n     * at the end of the heap space. */\n    uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;\n    uxAddress -= xHeapStructSize;\n    uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );\n    pxEnd = ( void * ) uxAddress;\n    pxEnd->xBlockSize = 0;\n    pxEnd->pxNextFreeBlock = NULL;\n\n    /* To start with there is a single free block that is sized to take up the\n     * entire heap space, minus the space taken by pxEnd. */\n    pxFirstFreeBlock = ( void * ) pucAlignedHeap;\n    pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;\n    pxFirstFreeBlock->pxNextFreeBlock = pxEnd;\n\n    /* Only one block exists - and it covers the entire usable heap space. */\n    xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;\n    xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;\n\n    /* Work out the position of the top bit in a size_t variable. */\n    xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert )\n{\n    BlockLink_t * pxIterator;\n    uint8_t * puc;\n\n    /* Iterate through the list until a block is found that has a higher address\n     * than the block being inserted. */\n    for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )\n    {\n        /* Nothing to do here, just iterate to the right position. */\n    }\n\n    /* Do the block being inserted, and the block it is being inserted after\n     * make a contiguous block of memory? */\n    puc = ( uint8_t * ) pxIterator;\n\n    if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )\n    {\n        pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;\n        pxBlockToInsert = pxIterator;\n    }\n    else\n    {\n        mtCOVERAGE_TEST_MARKER();\n    }\n\n    /* Do the block being inserted, and the block it is being inserted before\n     * make a contiguous block of memory? */\n    puc = ( uint8_t * ) pxBlockToInsert;\n\n    if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )\n    {\n        if( pxIterator->pxNextFreeBlock != pxEnd )\n        {\n            /* Form one big block from the two blocks. */\n            pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;\n            pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;\n        }\n        else\n        {\n            pxBlockToInsert->pxNextFreeBlock = pxEnd;\n        }\n    }\n    else\n    {\n        pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;\n    }\n\n    /* If the block being inserted plugged a gab, so was merged with the block\n     * before and the block after, then it's pxNextFreeBlock pointer will have\n     * already been set, and should not be set here as that would make it point\n     * to itself. */\n    if( pxIterator != pxBlockToInsert )\n    {\n        pxIterator->pxNextFreeBlock = pxBlockToInsert;\n    }\n    else\n    {\n        mtCOVERAGE_TEST_MARKER();\n    }\n}\n/*-----------------------------------------------------------*/\n\nvoid * pvPortMalloc( size_t xWantedSize )\n{\n    BlockLink_t * pxBlock;\n    BlockLink_t * pxPreviousBlock;\n    BlockLink_t * pxNewBlockLink;\n    void * pvReturn = NULL;\n\n    /* If this is the first call to malloc then the heap will require\n     * initialisation to setup the list of free blocks. */\n    if( pxEnd == NULL )\n    {\n        prvHeapInit();\n    }\n    else\n    {\n        mtCOVERAGE_TEST_MARKER();\n    }\n\n    /* Check the requested block size is not so large that the top bit is set.\n     * The top bit of the block size member of the BlockLink_t structure is used\n     * to determine who owns the block - the application or the kernel, so it\n     * must be free. */\n    if( ( xWantedSize & xBlockAllocatedBit ) == 0 )\n    {\n        /* The wanted size is increased so it can contain a BlockLink_t\n         * structure in addition to the requested amount of bytes. */\n        if( xWantedSize > 0 )\n        {\n            xWantedSize += xHeapStructSize;\n\n            /* Ensure that blocks are always aligned to the required number of\n             * bytes. */\n            if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )\n            {\n                /* Byte alignment required. */\n                xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );\n                secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n\n        if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )\n        {\n            /* Traverse the list from the start (lowest address) block until\n             * one of adequate size is found. */\n            pxPreviousBlock = &xStart;\n            pxBlock = xStart.pxNextFreeBlock;\n\n            while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )\n            {\n                pxPreviousBlock = pxBlock;\n                pxBlock = pxBlock->pxNextFreeBlock;\n            }\n\n            /* If the end marker was reached then a block of adequate size was\n             * not found. */\n            if( pxBlock != pxEnd )\n            {\n                /* Return the memory space pointed to - jumping over the\n                 * BlockLink_t structure at its start. */\n                pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );\n\n                /* This block is being returned for use so must be taken out\n                 * of the list of free blocks. */\n                pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;\n\n                /* If the block is larger than required it can be split into\n                 * two. */\n                if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE )\n                {\n                    /* This block is to be split into two.  Create a new\n                     * block following the number of bytes requested. The void\n                     * cast is used to prevent byte alignment warnings from the\n                     * compiler. */\n                    pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );\n                    secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 );\n\n                    /* Calculate the sizes of two blocks split from the single\n                     * block. */\n                    pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;\n                    pxBlock->xBlockSize = xWantedSize;\n\n                    /* Insert the new block into the list of free blocks. */\n                    prvInsertBlockIntoFreeList( pxNewBlockLink );\n                }\n                else\n                {\n                    mtCOVERAGE_TEST_MARKER();\n                }\n\n                xFreeBytesRemaining -= pxBlock->xBlockSize;\n\n                if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )\n                {\n                    xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;\n                }\n                else\n                {\n                    mtCOVERAGE_TEST_MARKER();\n                }\n\n                /* The block is being returned - it is allocated and owned by\n                 * the application and has no \"next\" block. */\n                pxBlock->xBlockSize |= xBlockAllocatedBit;\n                pxBlock->pxNextFreeBlock = NULL;\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n    }\n    else\n    {\n        mtCOVERAGE_TEST_MARKER();\n    }\n\n    traceMALLOC( pvReturn, xWantedSize );\n\n    #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )\n        {\n            if( pvReturn == NULL )\n            {\n                extern void vApplicationMallocFailedHook( void );\n                vApplicationMallocFailedHook();\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n    #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */\n\n    secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );\n    return pvReturn;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortFree( void * pv )\n{\n    uint8_t * puc = ( uint8_t * ) pv;\n    BlockLink_t * pxLink;\n\n    if( pv != NULL )\n    {\n        /* The memory being freed will have an BlockLink_t structure immediately\n         * before it. */\n        puc -= xHeapStructSize;\n\n        /* This casting is to keep the compiler from issuing warnings. */\n        pxLink = ( void * ) puc;\n\n        /* Check the block is actually allocated. */\n        secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );\n        secureportASSERT( pxLink->pxNextFreeBlock == NULL );\n\n        if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )\n        {\n            if( pxLink->pxNextFreeBlock == NULL )\n            {\n                /* The block is being returned to the heap - it is no longer\n                 * allocated. */\n                pxLink->xBlockSize &= ~xBlockAllocatedBit;\n\n                secureportDISABLE_NON_SECURE_INTERRUPTS();\n                {\n                    /* Add this block to the list of free blocks. */\n                    xFreeBytesRemaining += pxLink->xBlockSize;\n                    traceFREE( pv, pxLink->xBlockSize );\n                    prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );\n                }\n                secureportENABLE_NON_SECURE_INTERRUPTS();\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n    }\n}\n/*-----------------------------------------------------------*/\n\nsize_t xPortGetFreeHeapSize( void )\n{\n    return xFreeBytesRemaining;\n}\n/*-----------------------------------------------------------*/\n\nsize_t xPortGetMinimumEverFreeHeapSize( void )\n{\n    return xMinimumEverFreeBytesRemaining;\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/ARMv8M/secure/heap/secure_heap.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef __SECURE_HEAP_H__\n#define __SECURE_HEAP_H__\n\n/* Standard includes. */\n#include <stdlib.h>\n\n/**\n * @brief Allocates memory from heap.\n *\n * @param[in] xWantedSize The size of the memory to be allocated.\n *\n * @return Pointer to the memory region if the allocation is successful, NULL\n * otherwise.\n */\nvoid * pvPortMalloc( size_t xWantedSize );\n\n/**\n * @brief Frees the previously allocated memory.\n *\n * @param[in] pv Pointer to the memory to be freed.\n */\nvoid vPortFree( void * pv );\n\n/**\n * @brief Get the free heap size.\n *\n * @return Free heap size.\n */\nsize_t xPortGetFreeHeapSize( void );\n\n/**\n * @brief Get the minimum ever free heap size.\n *\n * @return Minimum ever free heap size.\n */\nsize_t xPortGetMinimumEverFreeHeapSize( void );\n\n#endif /* __SECURE_HEAP_H__ */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/ARMv8M/secure/init/secure_init.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Standard includes. */\n#include <stdint.h>\n\n/* Secure init includes. */\n#include \"secure_init.h\"\n\n/* Secure port macros. */\n#include \"secure_port_macros.h\"\n\n/**\n * @brief Constants required to manipulate the SCB.\n */\n#define secureinitSCB_AIRCR                 ( ( volatile uint32_t * ) 0xe000ed0c )  /* Application Interrupt and Reset Control Register. */\n#define secureinitSCB_AIRCR_VECTKEY_POS     ( 16UL )\n#define secureinitSCB_AIRCR_VECTKEY_MASK    ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )\n#define secureinitSCB_AIRCR_PRIS_POS        ( 14UL )\n#define secureinitSCB_AIRCR_PRIS_MASK       ( 1UL << secureinitSCB_AIRCR_PRIS_POS )\n\n/**\n * @brief Constants required to manipulate the FPU.\n */\n#define secureinitFPCCR                     ( ( volatile uint32_t * ) 0xe000ef34 )  /* Floating Point Context Control Register. */\n#define secureinitFPCCR_LSPENS_POS          ( 29UL )\n#define secureinitFPCCR_LSPENS_MASK         ( 1UL << secureinitFPCCR_LSPENS_POS )\n#define secureinitFPCCR_TS_POS              ( 26UL )\n#define secureinitFPCCR_TS_MASK             ( 1UL << secureinitFPCCR_TS_POS )\n\n#define secureinitNSACR                     ( ( volatile uint32_t * ) 0xe000ed8c )  /* Non-secure Access Control Register. */\n#define secureinitNSACR_CP10_POS            ( 10UL )\n#define secureinitNSACR_CP10_MASK           ( 1UL << secureinitNSACR_CP10_POS )\n#define secureinitNSACR_CP11_POS            ( 11UL )\n#define secureinitNSACR_CP11_MASK           ( 1UL << secureinitNSACR_CP11_POS )\n/*-----------------------------------------------------------*/\n\nsecureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void )\n{\n    uint32_t ulIPSR;\n\n    /* Read the Interrupt Program Status Register (IPSR) value. */\n    secureportREAD_IPSR( ulIPSR );\n\n    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\n     * when the processor is running in the Thread Mode. */\n    if( ulIPSR != 0 )\n    {\n        *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |\n                                   ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |\n                                   ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK );\n    }\n}\n/*-----------------------------------------------------------*/\n\nsecureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )\n{\n    uint32_t ulIPSR;\n\n    /* Read the Interrupt Program Status Register (IPSR) value. */\n    secureportREAD_IPSR( ulIPSR );\n\n    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\n     * when the processor is running in the Thread Mode. */\n    if( ulIPSR != 0 )\n    {\n        /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is\n         * permitted. CP11 should be programmed to the same value as CP10. */\n        *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );\n\n        /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures\n         * that we can enable/disable lazy stacking in port.c file. */\n        *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK );\n\n        /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP\n         * registers (S16-S31) are also pushed to stack on exception entry and\n         * restored on exception return. */\n        *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );\n    }\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/ARMv8M/secure/init/secure_init.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef __SECURE_INIT_H__\n#define __SECURE_INIT_H__\n\n/**\n * @brief De-prioritizes the non-secure exceptions.\n *\n * This is needed to ensure that the non-secure PendSV runs at the lowest\n * priority. Context switch is done in the non-secure PendSV handler.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n */\nvoid SecureInit_DePrioritizeNSExceptions( void );\n\n/**\n * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access.\n *\n * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point\n * Registers are not leaked to the non-secure side.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n */\nvoid SecureInit_EnableNSFPUAccess( void );\n\n#endif /* __SECURE_INIT_H__ */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/ARMv8M/secure/macros/secure_port_macros.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef __SECURE_PORT_MACROS_H__\n#define __SECURE_PORT_MACROS_H__\n\n/**\n * @brief Byte alignment requirements.\n */\n#define secureportBYTE_ALIGNMENT         8\n#define secureportBYTE_ALIGNMENT_MASK    ( 0x0007 )\n\n/**\n * @brief Macro to declare a function as non-secure callable.\n */\n#if defined( __IAR_SYSTEMS_ICC__ )\n    #define secureportNON_SECURE_CALLABLE    __cmse_nonsecure_entry __root\n#else\n    #define secureportNON_SECURE_CALLABLE    __attribute__( ( cmse_nonsecure_entry ) ) __attribute__( ( used ) )\n#endif\n\n/**\n * @brief Set the secure PRIMASK value.\n */\n#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \\\n    __asm volatile ( \"msr primask, %0\" : : \"r\" ( ulPrimaskValue ) : \"memory\" )\n\n/**\n * @brief Set the non-secure PRIMASK value.\n */\n#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \\\n    __asm volatile ( \"msr primask_ns, %0\" : : \"r\" ( ulPrimaskValue ) : \"memory\" )\n\n/**\n * @brief Read the PSP value in the given variable.\n */\n#define secureportREAD_PSP( pucOutCurrentStackPointer ) \\\n    __asm volatile ( \"mrs %0, psp\"  : \"=r\" ( pucOutCurrentStackPointer ) )\n\n/**\n * @brief Set the PSP to the given value.\n */\n#define secureportSET_PSP( pucCurrentStackPointer ) \\\n    __asm volatile ( \"msr psp, %0\" : : \"r\" ( pucCurrentStackPointer ) )\n\n/**\n * @brief Read the PSPLIM value in the given variable.\n */\n#define secureportREAD_PSPLIM( pucOutStackLimit ) \\\n    __asm volatile ( \"mrs %0, psplim\"  : \"=r\" ( pucOutStackLimit ) )\n\n/**\n * @brief Set the PSPLIM to the given value.\n */\n#define secureportSET_PSPLIM( pucStackLimit ) \\\n    __asm volatile ( \"msr psplim, %0\" : : \"r\" ( pucStackLimit ) )\n\n/**\n * @brief Set the NonSecure MSP to the given value.\n */\n#define secureportSET_MSP_NS( pucMainStackPointer ) \\\n    __asm volatile ( \"msr msp_ns, %0\" : : \"r\" ( pucMainStackPointer ) )\n\n/**\n * @brief Set the CONTROL register to the given value.\n */\n#define secureportSET_CONTROL( ulControl ) \\\n    __asm volatile ( \"msr control, %0\" : : \"r\" ( ulControl ) : \"memory\" )\n\n/**\n * @brief Read the Interrupt Program Status Register (IPSR) value in the given\n * variable.\n */\n#define secureportREAD_IPSR( ulIPSR ) \\\n    __asm volatile ( \"mrs %0, ipsr\"  : \"=r\" ( ulIPSR ) )\n\n/**\n * @brief PRIMASK value to enable interrupts.\n */\n#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL     0\n\n/**\n * @brief PRIMASK value to disable interrupts.\n */\n#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL    1\n\n/**\n * @brief Disable secure interrupts.\n */\n#define secureportDISABLE_SECURE_INTERRUPTS()        secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )\n\n/**\n * @brief Disable non-secure interrupts.\n *\n * This effectively disables context switches.\n */\n#define secureportDISABLE_NON_SECURE_INTERRUPTS()    secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )\n\n/**\n * @brief Enable non-secure interrupts.\n */\n#define secureportENABLE_NON_SECURE_INTERRUPTS()     secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL )\n\n/**\n * @brief Assert definition.\n */\n#define secureportASSERT( x )                      \\\n    if( ( x ) == 0 )                               \\\n    {                                              \\\n        secureportDISABLE_SECURE_INTERRUPTS();     \\\n        secureportDISABLE_NON_SECURE_INTERRUPTS(); \\\n        for( ; ; ) {; }                            \\\n    }\n\n#endif /* __SECURE_PORT_MACROS_H__ */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/CCS/ARM_CM3/port.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/*-----------------------------------------------------------\n* Implementation of functions defined in portable.h for the ARM CM3 port.\n*----------------------------------------------------------*/\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n#if ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 )\n    #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\n#endif\n\n/* Constants required to manipulate the core.  Registers first... */\n#define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )\n#define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )\n#define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )\n#define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )\n/* ...then bits in the registers. */\n#define portNVIC_SYSTICK_CLK_BIT              ( 1UL << 2UL )\n#define portNVIC_SYSTICK_INT_BIT              ( 1UL << 1UL )\n#define portNVIC_SYSTICK_ENABLE_BIT           ( 1UL << 0UL )\n#define portNVIC_SYSTICK_COUNT_FLAG_BIT       ( 1UL << 16UL )\n#define portNVIC_PENDSVCLEAR_BIT              ( 1UL << 27UL )\n#define portNVIC_PEND_SYSTICK_SET_BIT         ( 1UL << 26UL )\n#define portNVIC_PEND_SYSTICK_CLEAR_BIT       ( 1UL << 25UL )\n\n#define portNVIC_PENDSV_PRI                   ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\n#define portNVIC_SYSTICK_PRI                  ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\n\n/* Constants required to check the validity of an interrupt priority. */\n#define portFIRST_USER_INTERRUPT_NUMBER       ( 16 )\n#define portNVIC_IP_REGISTERS_OFFSET_16       ( 0xE000E3F0 )\n#define portAIRCR_REG                         ( *( ( volatile uint32_t * ) 0xE000ED0C ) )\n#define portMAX_8_BIT_VALUE                   ( ( uint8_t ) 0xff )\n#define portTOP_BIT_OF_BYTE                   ( ( uint8_t ) 0x80 )\n#define portMAX_PRIGROUP_BITS                 ( ( uint8_t ) 7 )\n#define portPRIORITY_GROUP_MASK               ( 0x07UL << 8UL )\n#define portPRIGROUP_SHIFT                    ( 8UL )\n\n/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */\n#define portVECTACTIVE_MASK                   ( 0xFFUL )\n\n/* Constants required to set up the initial stack. */\n#define portINITIAL_XPSR                      ( 0x01000000 )\n\n/* The systick is a 24-bit counter. */\n#define portMAX_24_BIT_NUMBER                 ( 0xffffffUL )\n\n/* A fiddle factor to estimate the number of SysTick counts that would have\n * occurred while the SysTick counter is stopped during tickless idle\n * calculations. */\n#define portMISSED_COUNTS_FACTOR              ( 94UL )\n\n/* For strict compliance with the Cortex-M spec the task start address should\n * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */\n#define portSTART_ADDRESS_MASK                ( ( StackType_t ) 0xfffffffeUL )\n\n/* Let the user override the default SysTick clock rate.  If defined by the\n * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the\n * configuration register. */\n#ifndef configSYSTICK_CLOCK_HZ\n    #define configSYSTICK_CLOCK_HZ             ( configCPU_CLOCK_HZ )\n    /* Ensure the SysTick is clocked at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( portNVIC_SYSTICK_CLK_BIT )\n#else\n    /* Select the option to clock SysTick not at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( 0 )\n#endif\n\n/*\n * Setup the timer to generate the tick interrupts.  The implementation in this\n * file is weak to allow application writers to change the timer used to\n * generate the tick interrupt.\n */\nvoid vPortSetupTimerInterrupt( void );\n\n/*\n * Exception handlers.\n */\nvoid xPortSysTickHandler( void );\n\n/*\n * Start first task is a separate function so it can be tested in isolation.\n */\nextern void vPortStartFirstTask( void );\n\n/*\n * Used to catch tasks that attempt to return from their implementing function.\n */\nstatic void prvTaskExitError( void );\n\n/*-----------------------------------------------------------*/\n\n/* Required to allow portasm.asm access the configMAX_SYSCALL_INTERRUPT_PRIORITY\n * setting. */\nconst uint32_t ulMaxSyscallInterruptPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY;\n\n/* Each task maintains its own interrupt status in the critical nesting\n * variable. */\nstatic UBaseType_t uxCriticalNesting = 0xaaaaaaaa;\n\n/*\n * The number of SysTick increments that make up one tick period.\n */\n#if ( configUSE_TICKLESS_IDLE == 1 )\n    static uint32_t ulTimerCountsForOneTick = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n\n/*\n * The maximum number of tick periods that can be suppressed is limited by the\n * 24 bit resolution of the SysTick timer.\n */\n#if ( configUSE_TICKLESS_IDLE == 1 )\n    static uint32_t xMaximumPossibleSuppressedTicks = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n\n/*\n * Compensate for the CPU cycles that pass while the SysTick is stopped (low\n * power functionality only.\n */\n#if ( configUSE_TICKLESS_IDLE == 1 )\n    static uint32_t ulStoppedTimerCompensation = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n\n/*\n * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure\n * FreeRTOS API functions are not called from interrupts that have been assigned\n * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.\n */\n#if ( configASSERT_DEFINED == 1 )\n    static uint8_t ucMaxSysCallPriority = 0;\n    static uint32_t ulMaxPRIGROUPValue = 0;\n    static const volatile uint8_t * const pcInterruptPriorityRegisters = ( uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;\n#endif /* configASSERT_DEFINED */\n\n/*-----------------------------------------------------------*/\n\n/*\n * See header file for description.\n */\nStackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,\n                                     TaskFunction_t pxCode,\n                                     void * pvParameters )\n{\n    /* Simulate the stack frame as it would be created by a context switch\n     * interrupt. */\n\n    /* Offset added to account for the way the MCU uses the stack on entry/exit\n     * of interrupts, and to ensure alignment. */\n    pxTopOfStack--;\n\n    *pxTopOfStack = portINITIAL_XPSR;                                    /* xPSR */\n    pxTopOfStack--;\n    *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */\n    pxTopOfStack--;\n    *pxTopOfStack = ( StackType_t ) prvTaskExitError;                    /* LR */\n\n    /* Save code space by skipping register initialisation. */\n    pxTopOfStack -= 5;                            /* R12, R3, R2 and R1. */\n    *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\n\n    pxTopOfStack -= 8;                            /* R11, R10, R9, R8, R7, R6, R5 and R4. */\n\n    return pxTopOfStack;\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvTaskExitError( void )\n{\n    /* A function that implements a task must not exit or attempt to return to\n     * its caller as there is nothing to return to.  If a task wants to exit it\n     * should instead call vTaskDelete( NULL ).\n     *\n     * Artificially force an assert() to be triggered if configASSERT() is\n     * defined, then stop here so application writers can catch the error. */\n    configASSERT( uxCriticalNesting == ~0UL );\n    portDISABLE_INTERRUPTS();\n\n    for( ; ; )\n    {\n    }\n}\n/*-----------------------------------------------------------*/\n\n/*\n * See header file for description.\n */\nBaseType_t xPortStartScheduler( void )\n{\n    #if ( configASSERT_DEFINED == 1 )\n    {\n        volatile uint32_t ulOriginalPriority;\n        volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\n        volatile uint8_t ucMaxPriorityValue;\n\n        /* Determine the maximum priority from which ISR safe FreeRTOS API\n         * functions can be called.  ISR safe functions are those that end in\n         * \"FromISR\".  FreeRTOS maintains separate thread and ISR API functions to\n         * ensure interrupt entry is as fast and simple as possible.\n         *\n         * Save the interrupt priority value that is about to be clobbered. */\n        ulOriginalPriority = *pucFirstUserPriorityRegister;\n\n        /* Determine the number of priority bits available.  First write to all\n         * possible bits. */\n        *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\n\n        /* Read the value back to see how many bits stuck. */\n        ucMaxPriorityValue = *pucFirstUserPriorityRegister;\n\n        /* Use the same mask on the maximum system call priority. */\n        ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;\n\n        /* Calculate the maximum acceptable priority group value for the number\n         * of bits read back. */\n        ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;\n\n        while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )\n        {\n            ulMaxPRIGROUPValue--;\n            ucMaxPriorityValue <<= ( uint8_t ) 0x01;\n        }\n\n        #ifdef __NVIC_PRIO_BITS\n        {\n            /* Check the CMSIS configuration that defines the number of\n             * priority bits matches the number of priority bits actually queried\n             * from the hardware. */\n            configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );\n        }\n        #endif\n\n        #ifdef configPRIO_BITS\n        {\n            /* Check the FreeRTOS configuration that defines the number of\n             * priority bits matches the number of priority bits actually queried\n             * from the hardware. */\n            configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );\n        }\n        #endif\n\n        /* Shift the priority group value back to its position within the AIRCR\n         * register. */\n        ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;\n        ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;\n\n        /* Restore the clobbered interrupt priority register to its original\n         * value. */\n        *pucFirstUserPriorityRegister = ulOriginalPriority;\n    }\n    #endif /* configASSERT_DEFINED */\n\n    /* Make PendSV and SysTick the lowest priority interrupts. */\n    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;\n    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;\n\n    /* Start the timer that generates the tick ISR.  Interrupts are disabled\n     * here already. */\n    vPortSetupTimerInterrupt();\n\n    /* Initialise the critical nesting count ready for the first task. */\n    uxCriticalNesting = 0;\n\n    /* Start the first task. */\n    vPortStartFirstTask();\n\n    /* Should not get here! */\n    return 0;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEndScheduler( void )\n{\n    /* Not implemented in ports where there is nothing to return to.\n     * Artificially force an assert. */\n    configASSERT( uxCriticalNesting == 1000UL );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEnterCritical( void )\n{\n    portDISABLE_INTERRUPTS();\n    uxCriticalNesting++;\n\n    /* This is not the interrupt safe version of the enter critical function so\n     * assert() if it is being called from an interrupt context.  Only API\n     * functions that end in \"FromISR\" can be used in an interrupt.  Only assert if\n     * the critical nesting count is 1 to protect against recursive calls if the\n     * assert function also uses a critical section. */\n    if( uxCriticalNesting == 1 )\n    {\n        configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );\n    }\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortExitCritical( void )\n{\n    configASSERT( uxCriticalNesting );\n    uxCriticalNesting--;\n\n    if( uxCriticalNesting == 0 )\n    {\n        portENABLE_INTERRUPTS();\n    }\n}\n/*-----------------------------------------------------------*/\n\nvoid xPortSysTickHandler( void )\n{\n    /* The SysTick runs at the lowest interrupt priority, so when this interrupt\n     * executes all interrupts must be unmasked.  There is therefore no need to\n     * save and then restore the interrupt mask value as its value is already\n     * known. */\n    ( void ) portSET_INTERRUPT_MASK_FROM_ISR();\n    {\n        /* Increment the RTOS tick. */\n        if( xTaskIncrementTick() != pdFALSE )\n        {\n            /* A context switch is required.  Context switching is performed in\n             * the PendSV interrupt.  Pend the PendSV interrupt. */\n            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\n        }\n    }\n    portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );\n}\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TICKLESS_IDLE == 1 )\n\n    #pragma WEAK( vPortSuppressTicksAndSleep )\n    void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )\n    {\n        uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;\n        TickType_t xModifiableIdleTime;\n\n        /* Make sure the SysTick reload value does not overflow the counter. */\n        if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\n        {\n            xExpectedIdleTime = xMaximumPossibleSuppressedTicks;\n        }\n\n        /* Enter a critical section but don't use the taskENTER_CRITICAL()\n         * method as that will mask interrupts that should exit sleep mode. */\n        __asm( \"\tcpsid i\");\n        __asm( \"\tdsb\");\n        __asm( \"\tisb\");\n\n        /* If a context switch is pending or a task is waiting for the scheduler\n         * to be unsuspended then abandon the low power entry. */\n        if( eTaskConfirmSleepModeStatus() == eAbortSleep )\n        {\n            /* Re-enable interrupts - see comments above the cpsid instruction\n             * above. */\n            __asm( \"\tcpsie i\");\n        }\n        else\n        {\n            /* Stop the SysTick momentarily.  The time the SysTick is stopped for\n             * is accounted for as best it can be, but using the tickless mode will\n             * inevitably result in some tiny drift of the time maintained by the\n             * kernel with respect to calendar time. */\n            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );\n\n            /* Use the SysTick current-value register to determine the number of\n             * SysTick decrements remaining until the next tick interrupt.  If the\n             * current-value register is zero, then there are actually\n             * ulTimerCountsForOneTick decrements remaining, not zero, because the\n             * SysTick requests the interrupt when decrementing from 1 to 0. */\n            ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n\n            if( ulSysTickDecrementsLeft == 0 )\n            {\n                ulSysTickDecrementsLeft = ulTimerCountsForOneTick;\n            }\n\n            /* Calculate the reload value required to wait xExpectedIdleTime\n             * tick periods.  -1 is used because this code normally executes part\n             * way through the first tick period.  But if the SysTick IRQ is now\n             * pending, then clear the IRQ, suppressing the first tick, and correct\n             * the reload value to reflect that the second tick period is already\n             * underway.  The expected idle time is always at least two ticks. */\n            ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );\n\n            if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )\n            {\n                portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;\n                ulReloadValue -= ulTimerCountsForOneTick;\n            }\n\n            if( ulReloadValue > ulStoppedTimerCompensation )\n            {\n                ulReloadValue -= ulStoppedTimerCompensation;\n            }\n\n            /* Set the new reload value. */\n            portNVIC_SYSTICK_LOAD_REG = ulReloadValue;\n\n            /* Clear the SysTick count flag and set the count value back to\n             * zero. */\n            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n            /* Restart SysTick. */\n            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\n\n            /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can\n             * set its parameter to 0 to indicate that its implementation contains\n             * its own wait for interrupt or wait for event instruction, and so wfi\n             * should not be executed again.  However, the original expected idle\n             * time variable must remain unmodified, so a copy is taken. */\n            xModifiableIdleTime = xExpectedIdleTime;\n            configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\n\n            if( xModifiableIdleTime > 0 )\n            {\n                __asm( \"\tdsb\");\n                __asm( \"\twfi\");\n                __asm( \"\tisb\");\n            }\n\n            configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\n\n            /* Re-enable interrupts to allow the interrupt that brought the MCU\n             * out of sleep mode to execute immediately.  See comments above\n             * the cpsid instruction above. */\n            __asm( \"\tcpsie i\");\n            __asm( \"\tdsb\");\n            __asm( \"\tisb\");\n\n            /* Disable interrupts again because the clock is about to be stopped\n             * and interrupts that execute while the clock is stopped will increase\n             * any slippage between the time maintained by the RTOS and calendar\n             * time. */\n            __asm( \"\tcpsid i\");\n            __asm( \"\tdsb\");\n            __asm( \"\tisb\");\n\n            /* Disable the SysTick clock without reading the\n             * portNVIC_SYSTICK_CTRL_REG register to ensure the\n             * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,\n             * the time the SysTick is stopped for is accounted for as best it can\n             * be, but using the tickless mode will inevitably result in some tiny\n             * drift of the time maintained by the kernel with respect to calendar\n             * time*/\n            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );\n\n            /* Determine whether the SysTick has already counted to zero. */\n            if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n            {\n                uint32_t ulCalculatedLoadValue;\n\n                /* The tick interrupt ended the sleep (or is now pending), and\n                 * a new tick period has started.  Reset portNVIC_SYSTICK_LOAD_REG\n                 * with whatever remains of the new tick period. */\n                ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\n\n                /* Don't allow a tiny value, or values that have somehow\n                 * underflowed because the post sleep hook did something\n                 * that took too long or because the SysTick current-value register\n                 * is zero. */\n                if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )\n                {\n                    ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );\n                }\n\n                portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;\n\n                /* As the pending tick will be processed as soon as this\n                 * function exits, the tick value maintained by the tick is stepped\n                 * forward by one less than the time spent waiting. */\n                ulCompleteTickPeriods = xExpectedIdleTime - 1UL;\n            }\n            else\n            {\n                /* Something other than the tick interrupt ended the sleep. */\n\n                /* Use the SysTick current-value register to determine the\n                 * number of SysTick decrements remaining until the expected idle\n                 * time would have ended. */\n                ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n                #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )\n                {\n                    /* If the SysTick is not using the core clock, the current-\n                     * value register might still be zero here.  In that case, the\n                     * SysTick didn't load from the reload register, and there are\n                     * ulReloadValue decrements remaining in the expected idle\n                     * time, not zero. */\n                    if( ulSysTickDecrementsLeft == 0 )\n                    {\n                        ulSysTickDecrementsLeft = ulReloadValue;\n                    }\n                }\n                #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */\n\n                /* Work out how long the sleep lasted rounded to complete tick\n                 * periods (not the ulReload value which accounted for part\n                 * ticks). */\n                ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;\n\n                /* How many complete tick periods passed while the processor\n                 * was waiting? */\n                ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;\n\n                /* The reload value is set to whatever fraction of a single tick\n                 * period remains. */\n                portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;\n            }\n\n            /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,\n             * then set portNVIC_SYSTICK_LOAD_REG back to its standard value.  If\n             * the SysTick is not using the core clock, temporarily configure it to\n             * use the core clock.  This configuration forces the SysTick to load\n             * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next\n             * cycle of the other clock.  Then portNVIC_SYSTICK_LOAD_REG is ready\n             * to receive the standard value immediately. */\n            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n            portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n            #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )\n            {\n                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n            }\n            #else\n            {\n                /* The temporary usage of the core clock has served its purpose,\n                 * as described above.  Resume usage of the other clock. */\n                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\n\n                if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n                {\n                    /* The partial tick period already ended.  Be sure the SysTick\n                     * counts it only once. */\n                    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;\n                }\n\n                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n            }\n            #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */\n\n            /* Step the tick to account for any tick periods that elapsed. */\n            vTaskStepTick( ulCompleteTickPeriods );\n\n            /* Exit with interrupts enabled. */\n            __asm( \"\tcpsie i\");\n        }\n    }\n\n#endif /* configUSE_TICKLESS_IDLE */\n/*-----------------------------------------------------------*/\n\n/*\n * Setup the systick timer to generate the tick interrupts at the required\n * frequency.\n */\n#pragma WEAK( vPortSetupTimerInterrupt )\nvoid vPortSetupTimerInterrupt( void )\n{\n    /* Calculate the constants required to configure the tick interrupt. */\n    #if ( configUSE_TICKLESS_IDLE == 1 )\n    {\n        ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );\n        xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;\n        ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\n    }\n    #endif /* configUSE_TICKLESS_IDLE */\n\n    /* Stop and clear the SysTick. */\n    portNVIC_SYSTICK_CTRL_REG = 0UL;\n    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n    /* Configure SysTick to interrupt at the requested rate. */\n    portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\n    portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );\n}\n/*-----------------------------------------------------------*/\n\n#if ( configASSERT_DEFINED == 1 )\n\n    void vPortValidateInterruptPriority( void )\n    {\n        extern uint32_t ulPortGetIPSR( void );\n        uint32_t ulCurrentInterrupt;\n        uint8_t ucCurrentPriority;\n\n        ulCurrentInterrupt = ulPortGetIPSR();\n\n        /* Is the interrupt number a user defined interrupt? */\n        if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )\n        {\n            /* Look up the interrupt's priority. */\n            ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];\n\n            /* The following assertion will fail if a service routine (ISR) for\n             * an interrupt that has been assigned a priority above\n             * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\n             * function.  ISR safe FreeRTOS API functions must *only* be called\n             * from interrupts that have been assigned a priority at or below\n             * configMAX_SYSCALL_INTERRUPT_PRIORITY.\n             *\n             * Numerically low interrupt priority numbers represent logically high\n             * interrupt priorities, therefore the priority of the interrupt must\n             * be set to a value equal to or numerically *higher* than\n             * configMAX_SYSCALL_INTERRUPT_PRIORITY.\n             *\n             * Interrupts that\tuse the FreeRTOS API must not be left at their\n             * default priority of\tzero as that is the highest possible priority,\n             * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,\n             * and\ttherefore also guaranteed to be invalid.\n             *\n             * FreeRTOS maintains separate thread and ISR API functions to ensure\n             * interrupt entry is as fast and simple as possible.\n             *\n             * The following links provide detailed information:\n             * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html\n             * https://www.FreeRTOS.org/FAQHelp.html */\n            configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );\n        }\n\n        /* Priority grouping:  The interrupt controller (NVIC) allows the bits\n         * that define each interrupt's priority to be split between bits that\n         * define the interrupt's pre-emption priority bits and bits that define\n         * the interrupt's sub-priority.  For simplicity all bits must be defined\n         * to be pre-emption priority bits.  The following assertion will fail if\n         * this is not the case (if some bits represent a sub-priority).\n         *\n         * If the application only uses CMSIS libraries for interrupt\n         * configuration then the correct setting can be achieved on all Cortex-M\n         * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the\n         * scheduler.  Note however that some vendor specific peripheral libraries\n         * assume a non-zero priority group setting, in which cases using a value\n         * of zero will result in unpredictable behaviour. */\n        configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );\n    }\n\n#endif /* configASSERT_DEFINED */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/CCS/ARM_CM3/portasm.asm",
    "content": ";/*\n; * FreeRTOS Kernel V10.5.1\n; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n; *\n; * SPDX-License-Identifier: MIT\n; *\n; * Permission is hereby granted, free of charge, to any person obtaining a copy of\n; * this software and associated documentation files (the \"Software\"), to deal in\n; * the Software without restriction, including without limitation the rights to\n; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n; * the Software, and to permit persons to whom the Software is furnished to do so,\n; * subject to the following conditions:\n; *\n; * The above copyright notice and this permission notice shall be included in all\n; * copies or substantial portions of the Software.\n; *\n; * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n; *\n; * https://www.FreeRTOS.org\n; * https://github.com/FreeRTOS\n; *\n; */\n\n\t.thumb\n\n\t.ref pxCurrentTCB\n\t.ref vTaskSwitchContext\n\t.ref ulMaxSyscallInterruptPriority\n\n\t.def xPortPendSVHandler\n\t.def ulPortGetIPSR\n\t.def vPortSVCHandler\n\t.def vPortStartFirstTask\n\nNVICOffsetConst:\t\t\t\t\t.word \t0xE000ED08\nCPACRConst:\t\t\t\t\t\t\t.word \t0xE000ED88\npxCurrentTCBConst:\t\t\t\t\t.word\tpxCurrentTCB\nulMaxSyscallInterruptPriorityConst: .word ulMaxSyscallInterruptPriority\n\n; -----------------------------------------------------------\n\n\t.align 4\nulPortGetIPSR: .asmfunc\n \tmrs r0, ipsr\n \tbx r14\n \t.endasmfunc\n ; -----------------------------------------------------------\n\n\t.align 4\nvPortSetInterruptMask: .asmfunc\n\tpush {r0}\n\tldr r0, ulMaxSyscallInterruptPriorityConst\n\tmsr basepri, r0\n\tpop {r0}\n\tbx r14\n\t.endasmfunc\n; -----------------------------------------------------------\n\n\t.align 4\nxPortPendSVHandler: .asmfunc\n\tmrs r0, psp\n\tisb\n\n\t;/* Get the location of the current TCB. */\n\tldr\tr3, pxCurrentTCBConst\n\tldr\tr2, [r3]\n\n\t;/* Save the core registers. */\n\tstmdb r0!, {r4-r11}\n\n\t;/* Save the new top of stack into the first member of the TCB. */\n\tstr r0, [r2]\n\n\tstmdb sp!, {r3, r14}\n\tldr r0, ulMaxSyscallInterruptPriorityConst\n\tldr r1, [r0]\n\tmsr basepri, r1\n\tdsb\n\tisb\n\tbl vTaskSwitchContext\n\tmov r0, #0\n\tmsr basepri, r0\n\tldmia sp!, {r3, r14}\n\n\t;/* The first item in pxCurrentTCB is the task top of stack. */\n\tldr r1, [r3]\n\tldr r0, [r1]\n\n\t;/* Pop the core registers. */\n\tldmia r0!, {r4-r11}\n\n\tmsr psp, r0\n\tisb\n\tbx r14\n\t.endasmfunc\n\n; -----------------------------------------------------------\n\n\t.align 4\nvPortSVCHandler: .asmfunc\n\t;/* Get the location of the current TCB. */\n\tldr\tr3, pxCurrentTCBConst\n\tldr r1, [r3]\n\tldr r0, [r1]\n\t;/* Pop the core registers. */\n\tldmia r0!, {r4-r11}\n\tmsr psp, r0\n\tisb\n\tmov r0, #0\n\tmsr\tbasepri, r0\n\torr r14, #0xd\n\tbx r14\n\t.endasmfunc\n\n; -----------------------------------------------------------\n\n\t.align 4\nvPortStartFirstTask: .asmfunc\n\t;/* Use the NVIC offset register to locate the stack. */\n\tldr r0, NVICOffsetConst\n\tldr r0, [r0]\n\tldr r0, [r0]\n\t;/* Set the msp back to the start of the stack. */\n\tmsr msp, r0\n\t;/* Clear the bit that indicates the FPU is in use in case the FPU was used\n\t;before the scheduler was started - which would otherwise result in the\n\t;unnecessary leaving of space in the SVC stack for lazy saving of FPU\n\t;registers. */\n\tmov r0, #0\n\tmsr control, r0\n\t;/* Call SVC to start the first task. */\n\tcpsie i\n\tcpsie f\n\tdsb\n\tisb\n\tsvc #0\n\t.endasmfunc\n\n; -----------------------------------------------------------\n\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/CCS/ARM_CM3/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n\n#ifndef PORTMACRO_H\n    #define PORTMACRO_H\n\n    #ifdef __cplusplus\n        extern \"C\" {\n    #endif\n\n/*-----------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the\n * given hardware and compiler.\n *\n * These settings should not be altered.\n *-----------------------------------------------------------\n */\n\n/* Type definitions. */\n    #define portCHAR          char\n    #define portFLOAT         float\n    #define portDOUBLE        double\n    #define portLONG          long\n    #define portSHORT         short\n    #define portSTACK_TYPE    uint32_t\n    #define portBASE_TYPE     long\n\n    typedef portSTACK_TYPE   StackType_t;\n    typedef long             BaseType_t;\n    typedef unsigned long    UBaseType_t;\n\n    #if ( configUSE_16_BIT_TICKS == 1 )\n        typedef uint16_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffff\n    #else\n        typedef uint32_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL\n\n/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\n * not need to be guarded with a critical section. */\n        #define portTICK_TYPE_IS_ATOMIC    1\n    #endif\n/*-----------------------------------------------------------*/\n\n/* Architecture specifics. */\n    #define portSTACK_GROWTH      ( -1 )\n    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\n    #define portBYTE_ALIGNMENT    8\n\n/*-----------------------------------------------------------*/\n\n/* Compiler directives. */\n    #define portWEAK_SYMBOL    __attribute__( ( weak ) )\n\n/*-----------------------------------------------------------*/\n\n/* Scheduler utilities. */\n    #define portYIELD()                                 \\\n    {                                                   \\\n        /* Set a PendSV to request a context switch. */ \\\n        portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \\\n        __asm( \"\tdsb\");                                \\\n        __asm( \"\tisb\");                                \\\n    }\n\n    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )\n    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )\n    #define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 )\n    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )\n\n/*-----------------------------------------------------------*/\n\n/* Architecture specific optimisations. */\n    #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION\n        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1\n    #endif\n\n    #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1\n\n/* Check the configuration. */\n        #if ( configMAX_PRIORITIES > 32 )\n            #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.\n        #endif\n\n/* Store/clear the ready priorities in a bit map. */\n        #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )\n        #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )\n\n/*-----------------------------------------------------------*/\n\n        #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31 - __clz( ( uxReadyPriorities ) ) )\n\n    #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */\n/*-----------------------------------------------------------*/\n\n/* Critical section management. */\n    extern void vPortEnterCritical( void );\n    extern void vPortExitCritical( void );\n\n    #define portDISABLE_INTERRUPTS()                                     \\\n    {                                                                    \\\n        _set_interrupt_priority( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \\\n        __asm( \"\tdsb\");                                                 \\\n        __asm( \"\tisb\");                                                 \\\n    }\n\n    #define portENABLE_INTERRUPTS()                   _set_interrupt_priority( 0 )\n    #define portENTER_CRITICAL()                      vPortEnterCritical()\n    #define portEXIT_CRITICAL()                       vPortExitCritical()\n    #define portSET_INTERRUPT_MASK_FROM_ISR()         _set_interrupt_priority( configMAX_SYSCALL_INTERRUPT_PRIORITY ); __asm( \"\tdsb\" ); __asm( \"\tisb\")\n    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    _set_interrupt_priority( x )\n/*-----------------------------------------------------------*/\n\n/* Tickless idle/low power functionality. */\n    #ifndef portSUPPRESS_TICKS_AND_SLEEP\n        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );\n        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )\n    #endif\n\n/*-----------------------------------------------------------*/\n\n/* Task function macros as described on the FreeRTOS.org WEB site.  These are\n * not necessary for to use this port.  They are defined so the common demo files\n * (which build with all the ports) will build. */\n    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )\n    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )\n/*-----------------------------------------------------------*/\n\n    #ifdef configASSERT\n        void vPortValidateInterruptPriority( void );\n        #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()\n    #endif\n\n/* portNOP() is not required by this port. */\n    #define portNOP()\n\n/*-----------------------------------------------------------*/\n\n    #ifdef __cplusplus\n        }\n    #endif\n\n#endif /* PORTMACRO_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/CCS/ARM_CM4F/port.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/*-----------------------------------------------------------\n* Implementation of functions defined in portable.h for the ARM CM4F port.\n*----------------------------------------------------------*/\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n#ifndef __TI_VFP_SUPPORT__\n    #error This port can only be used when the project options are configured to enable hardware floating point support.\n#endif\n\n#if ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 )\n    #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\n#endif\n\n/* Constants required to manipulate the core.  Registers first... */\n#define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )\n#define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )\n#define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )\n#define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )\n/* ...then bits in the registers. */\n#define portNVIC_SYSTICK_CLK_BIT              ( 1UL << 2UL )\n#define portNVIC_SYSTICK_INT_BIT              ( 1UL << 1UL )\n#define portNVIC_SYSTICK_ENABLE_BIT           ( 1UL << 0UL )\n#define portNVIC_SYSTICK_COUNT_FLAG_BIT       ( 1UL << 16UL )\n#define portNVIC_PENDSVCLEAR_BIT              ( 1UL << 27UL )\n#define portNVIC_PEND_SYSTICK_SET_BIT         ( 1UL << 26UL )\n#define portNVIC_PEND_SYSTICK_CLEAR_BIT       ( 1UL << 25UL )\n\n#define portNVIC_PENDSV_PRI                   ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\n#define portNVIC_SYSTICK_PRI                  ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\n\n/* Constants required to check the validity of an interrupt priority. */\n#define portFIRST_USER_INTERRUPT_NUMBER       ( 16 )\n#define portNVIC_IP_REGISTERS_OFFSET_16       ( 0xE000E3F0 )\n#define portAIRCR_REG                         ( *( ( volatile uint32_t * ) 0xE000ED0C ) )\n#define portMAX_8_BIT_VALUE                   ( ( uint8_t ) 0xff )\n#define portTOP_BIT_OF_BYTE                   ( ( uint8_t ) 0x80 )\n#define portMAX_PRIGROUP_BITS                 ( ( uint8_t ) 7 )\n#define portPRIORITY_GROUP_MASK               ( 0x07UL << 8UL )\n#define portPRIGROUP_SHIFT                    ( 8UL )\n\n/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */\n#define portVECTACTIVE_MASK                   ( 0xFFUL )\n\n/* Constants required to manipulate the VFP. */\n#define portFPCCR                             ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */\n#define portASPEN_AND_LSPEN_BITS              ( 0x3UL << 30UL )\n\n/* Constants required to set up the initial stack. */\n#define portINITIAL_XPSR                      ( 0x01000000 )\n#define portINITIAL_EXC_RETURN                ( 0xfffffffd )\n\n/* The systick is a 24-bit counter. */\n#define portMAX_24_BIT_NUMBER                 ( 0xffffffUL )\n\n/* A fiddle factor to estimate the number of SysTick counts that would have\n * occurred while the SysTick counter is stopped during tickless idle\n * calculations. */\n#define portMISSED_COUNTS_FACTOR              ( 94UL )\n\n/* For strict compliance with the Cortex-M spec the task start address should\n * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */\n#define portSTART_ADDRESS_MASK                ( ( StackType_t ) 0xfffffffeUL )\n\n/* Let the user override the default SysTick clock rate.  If defined by the\n * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the\n * configuration register. */\n#ifndef configSYSTICK_CLOCK_HZ\n    #define configSYSTICK_CLOCK_HZ             ( configCPU_CLOCK_HZ )\n    /* Ensure the SysTick is clocked at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( portNVIC_SYSTICK_CLK_BIT )\n#else\n    /* Select the option to clock SysTick not at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( 0 )\n#endif\n\n/*\n * Setup the timer to generate the tick interrupts.  The implementation in this\n * file is weak to allow application writers to change the timer used to\n * generate the tick interrupt.\n */\nvoid vPortSetupTimerInterrupt( void );\n\n/*\n * Exception handlers.\n */\nvoid xPortSysTickHandler( void );\n\n/*\n * Start first task is a separate function so it can be tested in isolation.\n */\nextern void vPortStartFirstTask( void );\n\n/*\n * Turn the VFP on.\n */\nextern void vPortEnableVFP( void );\n\n/*\n * Used to catch tasks that attempt to return from their implementing function.\n */\nstatic void prvTaskExitError( void );\n\n/*-----------------------------------------------------------*/\n\n/* Required to allow portasm.asm access the configMAX_SYSCALL_INTERRUPT_PRIORITY\n * setting. */\nconst uint32_t ulMaxSyscallInterruptPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY;\n\n/* Each task maintains its own interrupt status in the critical nesting\n * variable. */\nstatic UBaseType_t uxCriticalNesting = 0xaaaaaaaa;\n\n/*\n * The number of SysTick increments that make up one tick period.\n */\n#if ( configUSE_TICKLESS_IDLE == 1 )\n    static uint32_t ulTimerCountsForOneTick = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n\n/*\n * The maximum number of tick periods that can be suppressed is limited by the\n * 24 bit resolution of the SysTick timer.\n */\n#if ( configUSE_TICKLESS_IDLE == 1 )\n    static uint32_t xMaximumPossibleSuppressedTicks = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n\n/*\n * Compensate for the CPU cycles that pass while the SysTick is stopped (low\n * power functionality only.\n */\n#if ( configUSE_TICKLESS_IDLE == 1 )\n    static uint32_t ulStoppedTimerCompensation = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n\n/*\n * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure\n * FreeRTOS API functions are not called from interrupts that have been assigned\n * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.\n */\n#if ( configASSERT_DEFINED == 1 )\n    static uint8_t ucMaxSysCallPriority = 0;\n    static uint32_t ulMaxPRIGROUPValue = 0;\n    static const volatile uint8_t * const pcInterruptPriorityRegisters = ( uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;\n#endif /* configASSERT_DEFINED */\n\n/*-----------------------------------------------------------*/\n\n/*\n * See header file for description.\n */\nStackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,\n                                     TaskFunction_t pxCode,\n                                     void * pvParameters )\n{\n    /* Simulate the stack frame as it would be created by a context switch\n     * interrupt. */\n\n    /* Offset added to account for the way the MCU uses the stack on entry/exit\n     * of interrupts, and to ensure alignment. */\n    pxTopOfStack--;\n\n    *pxTopOfStack = portINITIAL_XPSR;                                    /* xPSR */\n    pxTopOfStack--;\n    *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */\n    pxTopOfStack--;\n    *pxTopOfStack = ( StackType_t ) prvTaskExitError;                    /* LR */\n\n    /* Save code space by skipping register initialisation. */\n    pxTopOfStack -= 5;                            /* R12, R3, R2 and R1. */\n    *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\n\n    /* A save method is being used that requires each task to maintain its\n     * own exec return value. */\n    pxTopOfStack--;\n    *pxTopOfStack = portINITIAL_EXC_RETURN;\n\n    pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */\n\n    return pxTopOfStack;\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvTaskExitError( void )\n{\n    /* A function that implements a task must not exit or attempt to return to\n     * its caller as there is nothing to return to.  If a task wants to exit it\n     * should instead call vTaskDelete( NULL ).\n     *\n     * Artificially force an assert() to be triggered if configASSERT() is\n     * defined, then stop here so application writers can catch the error. */\n    configASSERT( uxCriticalNesting == ~0UL );\n    portDISABLE_INTERRUPTS();\n\n    for( ; ; )\n    {\n    }\n}\n/*-----------------------------------------------------------*/\n\n/*\n * See header file for description.\n */\nBaseType_t xPortStartScheduler( void )\n{\n    #if ( configASSERT_DEFINED == 1 )\n    {\n        volatile uint32_t ulOriginalPriority;\n        volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\n        volatile uint8_t ucMaxPriorityValue;\n\n        /* Determine the maximum priority from which ISR safe FreeRTOS API\n         * functions can be called.  ISR safe functions are those that end in\n         * \"FromISR\".  FreeRTOS maintains separate thread and ISR API functions to\n         * ensure interrupt entry is as fast and simple as possible.\n         *\n         * Save the interrupt priority value that is about to be clobbered. */\n        ulOriginalPriority = *pucFirstUserPriorityRegister;\n\n        /* Determine the number of priority bits available.  First write to all\n         * possible bits. */\n        *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\n\n        /* Read the value back to see how many bits stuck. */\n        ucMaxPriorityValue = *pucFirstUserPriorityRegister;\n\n        /* Use the same mask on the maximum system call priority. */\n        ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;\n\n        /* Calculate the maximum acceptable priority group value for the number\n         * of bits read back. */\n        ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;\n\n        while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )\n        {\n            ulMaxPRIGROUPValue--;\n            ucMaxPriorityValue <<= ( uint8_t ) 0x01;\n        }\n\n        #ifdef __NVIC_PRIO_BITS\n        {\n            /* Check the CMSIS configuration that defines the number of\n             * priority bits matches the number of priority bits actually queried\n             * from the hardware. */\n            configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );\n        }\n        #endif\n\n        #ifdef configPRIO_BITS\n        {\n            /* Check the FreeRTOS configuration that defines the number of\n             * priority bits matches the number of priority bits actually queried\n             * from the hardware. */\n            configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );\n        }\n        #endif\n\n        /* Shift the priority group value back to its position within the AIRCR\n         * register. */\n        ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;\n        ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;\n\n        /* Restore the clobbered interrupt priority register to its original\n         * value. */\n        *pucFirstUserPriorityRegister = ulOriginalPriority;\n    }\n    #endif /* configASSERT_DEFINED */\n\n    /* Make PendSV and SysTick the lowest priority interrupts. */\n    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;\n    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;\n\n    /* Start the timer that generates the tick ISR.  Interrupts are disabled\n     * here already. */\n    vPortSetupTimerInterrupt();\n\n    /* Initialise the critical nesting count ready for the first task. */\n    uxCriticalNesting = 0;\n\n    /* Ensure the VFP is enabled - it should be anyway. */\n    vPortEnableVFP();\n\n    /* Lazy save always. */\n    *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;\n\n    /* Start the first task. */\n    vPortStartFirstTask();\n\n    /* Should not get here! */\n    return 0;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEndScheduler( void )\n{\n    /* Not implemented in ports where there is nothing to return to.\n     * Artificially force an assert. */\n    configASSERT( uxCriticalNesting == 1000UL );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEnterCritical( void )\n{\n    portDISABLE_INTERRUPTS();\n    uxCriticalNesting++;\n\n    /* This is not the interrupt safe version of the enter critical function so\n     * assert() if it is being called from an interrupt context.  Only API\n     * functions that end in \"FromISR\" can be used in an interrupt.  Only assert if\n     * the critical nesting count is 1 to protect against recursive calls if the\n     * assert function also uses a critical section. */\n    if( uxCriticalNesting == 1 )\n    {\n        configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );\n    }\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortExitCritical( void )\n{\n    configASSERT( uxCriticalNesting );\n    uxCriticalNesting--;\n\n    if( uxCriticalNesting == 0 )\n    {\n        portENABLE_INTERRUPTS();\n    }\n}\n/*-----------------------------------------------------------*/\n\nvoid xPortSysTickHandler( void )\n{\n    /* The SysTick runs at the lowest interrupt priority, so when this interrupt\n     * executes all interrupts must be unmasked.  There is therefore no need to\n     * save and then restore the interrupt mask value as its value is already\n     * known. */\n    ( void ) portSET_INTERRUPT_MASK_FROM_ISR();\n    {\n        /* Increment the RTOS tick. */\n        if( xTaskIncrementTick() != pdFALSE )\n        {\n            /* A context switch is required.  Context switching is performed in\n             * the PendSV interrupt.  Pend the PendSV interrupt. */\n            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\n        }\n    }\n    portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );\n}\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TICKLESS_IDLE == 1 )\n\n    #pragma WEAK( vPortSuppressTicksAndSleep )\n    void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )\n    {\n        uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;\n        TickType_t xModifiableIdleTime;\n\n        /* Make sure the SysTick reload value does not overflow the counter. */\n        if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\n        {\n            xExpectedIdleTime = xMaximumPossibleSuppressedTicks;\n        }\n\n        /* Enter a critical section but don't use the taskENTER_CRITICAL()\n         * method as that will mask interrupts that should exit sleep mode. */\n        __asm( \"\tcpsid i\");\n        __asm( \"\tdsb\");\n        __asm( \"\tisb\");\n\n        /* If a context switch is pending or a task is waiting for the scheduler\n         * to be unsuspended then abandon the low power entry. */\n        if( eTaskConfirmSleepModeStatus() == eAbortSleep )\n        {\n            /* Re-enable interrupts - see comments above the cpsid instruction\n             * above. */\n            __asm( \"\tcpsie i\");\n        }\n        else\n        {\n            /* Stop the SysTick momentarily.  The time the SysTick is stopped for\n             * is accounted for as best it can be, but using the tickless mode will\n             * inevitably result in some tiny drift of the time maintained by the\n             * kernel with respect to calendar time. */\n            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );\n\n            /* Use the SysTick current-value register to determine the number of\n             * SysTick decrements remaining until the next tick interrupt.  If the\n             * current-value register is zero, then there are actually\n             * ulTimerCountsForOneTick decrements remaining, not zero, because the\n             * SysTick requests the interrupt when decrementing from 1 to 0. */\n            ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n\n            if( ulSysTickDecrementsLeft == 0 )\n            {\n                ulSysTickDecrementsLeft = ulTimerCountsForOneTick;\n            }\n\n            /* Calculate the reload value required to wait xExpectedIdleTime\n             * tick periods.  -1 is used because this code normally executes part\n             * way through the first tick period.  But if the SysTick IRQ is now\n             * pending, then clear the IRQ, suppressing the first tick, and correct\n             * the reload value to reflect that the second tick period is already\n             * underway.  The expected idle time is always at least two ticks. */\n            ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );\n\n            if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )\n            {\n                portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;\n                ulReloadValue -= ulTimerCountsForOneTick;\n            }\n\n            if( ulReloadValue > ulStoppedTimerCompensation )\n            {\n                ulReloadValue -= ulStoppedTimerCompensation;\n            }\n\n            /* Set the new reload value. */\n            portNVIC_SYSTICK_LOAD_REG = ulReloadValue;\n\n            /* Clear the SysTick count flag and set the count value back to\n             * zero. */\n            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n            /* Restart SysTick. */\n            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\n\n            /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can\n             * set its parameter to 0 to indicate that its implementation contains\n             * its own wait for interrupt or wait for event instruction, and so wfi\n             * should not be executed again.  However, the original expected idle\n             * time variable must remain unmodified, so a copy is taken. */\n            xModifiableIdleTime = xExpectedIdleTime;\n            configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\n\n            if( xModifiableIdleTime > 0 )\n            {\n                __asm( \"\tdsb\");\n                __asm( \"\twfi\");\n                __asm( \"\tisb\");\n            }\n\n            configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\n\n            /* Re-enable interrupts to allow the interrupt that brought the MCU\n             * out of sleep mode to execute immediately.  See comments above\n             * the cpsid instruction above. */\n            __asm( \"\tcpsie i\");\n            __asm( \"\tdsb\");\n            __asm( \"\tisb\");\n\n            /* Disable interrupts again because the clock is about to be stopped\n             * and interrupts that execute while the clock is stopped will increase\n             * any slippage between the time maintained by the RTOS and calendar\n             * time. */\n            __asm( \"\tcpsid i\");\n            __asm( \"\tdsb\");\n            __asm( \"\tisb\");\n\n            /* Disable the SysTick clock without reading the\n             * portNVIC_SYSTICK_CTRL_REG register to ensure the\n             * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,\n             * the time the SysTick is stopped for is accounted for as best it can\n             * be, but using the tickless mode will inevitably result in some tiny\n             * drift of the time maintained by the kernel with respect to calendar\n             * time*/\n            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );\n\n            /* Determine whether the SysTick has already counted to zero. */\n            if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n            {\n                uint32_t ulCalculatedLoadValue;\n\n                /* The tick interrupt ended the sleep (or is now pending), and\n                 * a new tick period has started.  Reset portNVIC_SYSTICK_LOAD_REG\n                 * with whatever remains of the new tick period. */\n                ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\n\n                /* Don't allow a tiny value, or values that have somehow\n                 * underflowed because the post sleep hook did something\n                 * that took too long or because the SysTick current-value register\n                 * is zero. */\n                if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )\n                {\n                    ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );\n                }\n\n                portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;\n\n                /* As the pending tick will be processed as soon as this\n                 * function exits, the tick value maintained by the tick is stepped\n                 * forward by one less than the time spent waiting. */\n                ulCompleteTickPeriods = xExpectedIdleTime - 1UL;\n            }\n            else\n            {\n                /* Something other than the tick interrupt ended the sleep. */\n\n                /* Use the SysTick current-value register to determine the\n                 * number of SysTick decrements remaining until the expected idle\n                 * time would have ended. */\n                ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n                #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )\n                {\n                    /* If the SysTick is not using the core clock, the current-\n                     * value register might still be zero here.  In that case, the\n                     * SysTick didn't load from the reload register, and there are\n                     * ulReloadValue decrements remaining in the expected idle\n                     * time, not zero. */\n                    if( ulSysTickDecrementsLeft == 0 )\n                    {\n                        ulSysTickDecrementsLeft = ulReloadValue;\n                    }\n                }\n                #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */\n\n                /* Work out how long the sleep lasted rounded to complete tick\n                 * periods (not the ulReload value which accounted for part\n                 * ticks). */\n                ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;\n\n                /* How many complete tick periods passed while the processor\n                 * was waiting? */\n                ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;\n\n                /* The reload value is set to whatever fraction of a single tick\n                 * period remains. */\n                portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;\n            }\n\n            /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,\n             * then set portNVIC_SYSTICK_LOAD_REG back to its standard value.  If\n             * the SysTick is not using the core clock, temporarily configure it to\n             * use the core clock.  This configuration forces the SysTick to load\n             * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next\n             * cycle of the other clock.  Then portNVIC_SYSTICK_LOAD_REG is ready\n             * to receive the standard value immediately. */\n            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n            portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n            #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )\n            {\n                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n            }\n            #else\n            {\n                /* The temporary usage of the core clock has served its purpose,\n                 * as described above.  Resume usage of the other clock. */\n                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\n\n                if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n                {\n                    /* The partial tick period already ended.  Be sure the SysTick\n                     * counts it only once. */\n                    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;\n                }\n\n                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n            }\n            #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */\n\n            /* Step the tick to account for any tick periods that elapsed. */\n            vTaskStepTick( ulCompleteTickPeriods );\n\n            /* Exit with interrupts enabled. */\n            __asm( \"\tcpsie i\");\n        }\n    }\n\n#endif /* configUSE_TICKLESS_IDLE */\n/*-----------------------------------------------------------*/\n\n/*\n * Setup the systick timer to generate the tick interrupts at the required\n * frequency.\n */\n#pragma WEAK( vPortSetupTimerInterrupt )\nvoid vPortSetupTimerInterrupt( void )\n{\n    /* Calculate the constants required to configure the tick interrupt. */\n    #if ( configUSE_TICKLESS_IDLE == 1 )\n    {\n        ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );\n        xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;\n        ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\n    }\n    #endif /* configUSE_TICKLESS_IDLE */\n\n    /* Stop and clear the SysTick. */\n    portNVIC_SYSTICK_CTRL_REG = 0UL;\n    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n    /* Configure SysTick to interrupt at the requested rate. */\n    portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\n    portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );\n}\n/*-----------------------------------------------------------*/\n\n#if ( configASSERT_DEFINED == 1 )\n\n    void vPortValidateInterruptPriority( void )\n    {\n        extern uint32_t ulPortGetIPSR( void );\n        uint32_t ulCurrentInterrupt;\n        uint8_t ucCurrentPriority;\n\n        ulCurrentInterrupt = ulPortGetIPSR();\n\n        /* Is the interrupt number a user defined interrupt? */\n        if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )\n        {\n            /* Look up the interrupt's priority. */\n            ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];\n\n            /* The following assertion will fail if a service routine (ISR) for\n             * an interrupt that has been assigned a priority above\n             * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\n             * function.  ISR safe FreeRTOS API functions must *only* be called\n             * from interrupts that have been assigned a priority at or below\n             * configMAX_SYSCALL_INTERRUPT_PRIORITY.\n             *\n             * Numerically low interrupt priority numbers represent logically high\n             * interrupt priorities, therefore the priority of the interrupt must\n             * be set to a value equal to or numerically *higher* than\n             * configMAX_SYSCALL_INTERRUPT_PRIORITY.\n             *\n             * Interrupts that\tuse the FreeRTOS API must not be left at their\n             * default priority of\tzero as that is the highest possible priority,\n             * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,\n             * and\ttherefore also guaranteed to be invalid.\n             *\n             * FreeRTOS maintains separate thread and ISR API functions to ensure\n             * interrupt entry is as fast and simple as possible.\n             *\n             * The following links provide detailed information:\n             * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html\n             * https://www.FreeRTOS.org/FAQHelp.html */\n            configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );\n        }\n\n        /* Priority grouping:  The interrupt controller (NVIC) allows the bits\n         * that define each interrupt's priority to be split between bits that\n         * define the interrupt's pre-emption priority bits and bits that define\n         * the interrupt's sub-priority.  For simplicity all bits must be defined\n         * to be pre-emption priority bits.  The following assertion will fail if\n         * this is not the case (if some bits represent a sub-priority).\n         *\n         * If the application only uses CMSIS libraries for interrupt\n         * configuration then the correct setting can be achieved on all Cortex-M\n         * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the\n         * scheduler.  Note however that some vendor specific peripheral libraries\n         * assume a non-zero priority group setting, in which cases using a value\n         * of zero will result in unpredictable behaviour. */\n        configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );\n    }\n\n#endif /* configASSERT_DEFINED */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/CCS/ARM_CM4F/portasm.asm",
    "content": ";/*\n; * FreeRTOS Kernel V10.5.1\n; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n; *\n; * SPDX-License-Identifier: MIT\n; *\n; * Permission is hereby granted, free of charge, to any person obtaining a copy of\n; * this software and associated documentation files (the \"Software\"), to deal in\n; * the Software without restriction, including without limitation the rights to\n; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n; * the Software, and to permit persons to whom the Software is furnished to do so,\n; * subject to the following conditions:\n; *\n; * The above copyright notice and this permission notice shall be included in all\n; * copies or substantial portions of the Software.\n; *\n; * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n; *\n; * https://www.FreeRTOS.org\n; * https://github.com/FreeRTOS\n; *\n; */\n\n\t.thumb\n\n\t.ref pxCurrentTCB\n\t.ref vTaskSwitchContext\n\t.ref ulMaxSyscallInterruptPriority\n\n\t.def xPortPendSVHandler\n\t.def ulPortGetIPSR\n\t.def vPortSVCHandler\n\t.def vPortStartFirstTask\n\t.def vPortEnableVFP\n\nNVICOffsetConst:\t\t\t\t\t.word \t0xE000ED08\nCPACRConst:\t\t\t\t\t\t\t.word \t0xE000ED88\npxCurrentTCBConst:\t\t\t\t\t.word\tpxCurrentTCB\nulMaxSyscallInterruptPriorityConst: .word ulMaxSyscallInterruptPriority\n\n; -----------------------------------------------------------\n\n\t.align 4\nulPortGetIPSR: .asmfunc\n \tmrs r0, ipsr\n \tbx r14\n \t.endasmfunc\n ; -----------------------------------------------------------\n\n\t.align 4\nvPortSetInterruptMask: .asmfunc\n\tpush {r0}\n\tldr r0, ulMaxSyscallInterruptPriorityConst\n\tmsr basepri, r0\n\tpop {r0}\n\tbx r14\n\t.endasmfunc\n; -----------------------------------------------------------\n\n\t.align 4\nxPortPendSVHandler: .asmfunc\n\tmrs r0, psp\n\tisb\n\n\t;/* Get the location of the current TCB. */\n\tldr\tr3, pxCurrentTCBConst\n\tldr\tr2, [r3]\n\n\t;/* Is the task using the FPU context?  If so, push high vfp registers. */\n\ttst r14, #0x10\n\tit eq\n\tvstmdbeq r0!, {s16-s31}\n\n\t;/* Save the core registers. */\n\tstmdb r0!, {r4-r11, r14}\n\n\t;/* Save the new top of stack into the first member of the TCB. */\n\tstr r0, [r2]\n\n\tstmdb sp!, {r0, r3}\n\tldr r0, ulMaxSyscallInterruptPriorityConst\n\tldr r1, [r0]\n\tmsr basepri, r1\n\tdsb\n\tisb\n\tbl vTaskSwitchContext\n\tmov r0, #0\n\tmsr basepri, r0\n\tldmia sp!, {r0, r3}\n\n\t;/* The first item in pxCurrentTCB is the task top of stack. */\n\tldr r1, [r3]\n\tldr r0, [r1]\n\n\t;/* Pop the core registers. */\n\tldmia r0!, {r4-r11, r14}\n\n\t;/* Is the task using the FPU context?  If so, pop the high vfp registers\n\t;too. */\n\ttst r14, #0x10\n\tit eq\n\tvldmiaeq r0!, {s16-s31}\n\n\tmsr psp, r0\n\tisb\n\tbx r14\n\t.endasmfunc\n\n; -----------------------------------------------------------\n\n\t.align 4\nvPortSVCHandler: .asmfunc\n\t;/* Get the location of the current TCB. */\n\tldr\tr3, pxCurrentTCBConst\n\tldr r1, [r3]\n\tldr r0, [r1]\n\t;/* Pop the core registers. */\n\tldmia r0!, {r4-r11, r14}\n\tmsr psp, r0\n\tisb\n\tmov r0, #0\n\tmsr\tbasepri, r0\n\tbx r14\n\t.endasmfunc\n\n; -----------------------------------------------------------\n\n\t.align 4\nvPortStartFirstTask: .asmfunc\n\t;/* Use the NVIC offset register to locate the stack. */\n\tldr r0, NVICOffsetConst\n\tldr r0, [r0]\n\tldr r0, [r0]\n\t;/* Set the msp back to the start of the stack. */\n\tmsr msp, r0\n\t;/* Clear the bit that indicates the FPU is in use in case the FPU was used\n\t;before the scheduler was started - which would otherwise result in the\n\t;unnecessary leaving of space in the SVC stack for lazy saving of FPU\n\t;registers. */\n\tmov r0, #0\n\tmsr control, r0\n\t;/* Call SVC to start the first task. */\n\tcpsie i\n\tcpsie f\n\tdsb\n\tisb\n\tsvc #0\n\t.endasmfunc\n\n; -----------------------------------------------------------\n\n\t.align 4\nvPortEnableVFP: .asmfunc\n\t;/* The FPU enable bits are in the CPACR. */\n\tldr.w r0, CPACRConst\n\tldr\tr1, [r0]\n\n\t;/* Enable CP10 and CP11 coprocessors, then save back. */\n\torr\tr1, r1, #( 0xf << 20 )\n\tstr r1, [r0]\n\tbx\tr14\n\t.endasmfunc\n\n\t.end\n\n; -----------------------------------------------------------\n\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/CCS/ARM_CM4F/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n\n#ifndef PORTMACRO_H\n    #define PORTMACRO_H\n\n    #ifdef __cplusplus\n        extern \"C\" {\n    #endif\n\n/*-----------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the\n * given hardware and compiler.\n *\n * These settings should not be altered.\n *-----------------------------------------------------------\n */\n\n/* Type definitions. */\n    #define portCHAR          char\n    #define portFLOAT         float\n    #define portDOUBLE        double\n    #define portLONG          long\n    #define portSHORT         short\n    #define portSTACK_TYPE    uint32_t\n    #define portBASE_TYPE     long\n\n    typedef portSTACK_TYPE   StackType_t;\n    typedef long             BaseType_t;\n    typedef unsigned long    UBaseType_t;\n\n    #if ( configUSE_16_BIT_TICKS == 1 )\n        typedef uint16_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffff\n    #else\n        typedef uint32_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL\n\n/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\n * not need to be guarded with a critical section. */\n        #define portTICK_TYPE_IS_ATOMIC    1\n    #endif\n/*-----------------------------------------------------------*/\n\n/* Architecture specifics. */\n    #define portSTACK_GROWTH      ( -1 )\n    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\n    #define portBYTE_ALIGNMENT    8\n/*-----------------------------------------------------------*/\n\n/* Scheduler utilities. */\n    #define portYIELD()                                 \\\n    {                                                   \\\n        /* Set a PendSV to request a context switch. */ \\\n        portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \\\n        __asm( \"\tdsb\");                                \\\n        __asm( \"\tisb\");                                \\\n    }\n\n    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )\n    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )\n    #define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 )\n    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )\n\n/*-----------------------------------------------------------*/\n\n/* Architecture specific optimisations. */\n    #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION\n        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1\n    #endif\n\n    #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1\n\n/* Check the configuration. */\n        #if ( configMAX_PRIORITIES > 32 )\n            #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.\n        #endif\n\n/* Store/clear the ready priorities in a bit map. */\n        #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )\n        #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )\n\n/*-----------------------------------------------------------*/\n\n        #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31 - __clz( ( uxReadyPriorities ) ) )\n\n    #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */\n/*-----------------------------------------------------------*/\n\n/* Critical section management. */\n    extern void vPortEnterCritical( void );\n    extern void vPortExitCritical( void );\n\n    #define portDISABLE_INTERRUPTS()                                     \\\n    {                                                                    \\\n        _set_interrupt_priority( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \\\n        __asm( \"\tdsb\");                                                 \\\n        __asm( \"\tisb\");                                                 \\\n    }\n\n    #define portENABLE_INTERRUPTS()                   _set_interrupt_priority( 0 )\n    #define portENTER_CRITICAL()                      vPortEnterCritical()\n    #define portEXIT_CRITICAL()                       vPortExitCritical()\n    #define portSET_INTERRUPT_MASK_FROM_ISR()         _set_interrupt_priority( configMAX_SYSCALL_INTERRUPT_PRIORITY ); __asm( \"\tdsb\" ); __asm( \"\tisb\")\n    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    _set_interrupt_priority( x )\n/*-----------------------------------------------------------*/\n\n/* Tickless idle/low power functionality. */\n    #ifndef portSUPPRESS_TICKS_AND_SLEEP\n        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );\n        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )\n    #endif\n\n/*-----------------------------------------------------------*/\n\n/* Task function macros as described on the FreeRTOS.org WEB site.  These are\n * not necessary for to use this port.  They are defined so the common demo files\n * (which build with all the ports) will build. */\n    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )\n    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )\n/*-----------------------------------------------------------*/\n\n    #ifdef configASSERT\n        void vPortValidateInterruptPriority( void );\n        #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()\n    #endif\n\n/* portNOP() is not required by this port. */\n    #define portNOP()\n\n/*-----------------------------------------------------------*/\n\n    #ifdef __cplusplus\n        }\n    #endif\n\n#endif /* PORTMACRO_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/CCS/ARM_Cortex-R4/port.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* FreeRTOS includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n/*-----------------------------------------------------------*/\n\n/* Count of the critical section nesting depth. */\nuint32_t ulCriticalNesting = 9999;\n\n/*-----------------------------------------------------------*/\n\n/* Registers required to configure the RTI. */\n#define portRTI_GCTRL_REG  \t\t( * ( ( volatile uint32_t * ) 0xFFFFFC00 ) )\n#define portRTI_TBCTRL_REG  \t( * ( ( volatile uint32_t * ) 0xFFFFFC04 ) )\n#define portRTI_COMPCTRL_REG  \t( * ( ( volatile uint32_t * ) 0xFFFFFC0C ) )\n#define portRTI_CNT0_FRC0_REG  \t( * ( ( volatile uint32_t * ) 0xFFFFFC10 ) )\n#define portRTI_CNT0_UC0_REG  \t( * ( ( volatile uint32_t * ) 0xFFFFFC14 ) )\n#define portRTI_CNT0_CPUC0_REG  ( * ( ( volatile uint32_t * ) 0xFFFFFC18 ) )\n#define portRTI_CNT0_COMP0_REG  ( * ( ( volatile uint32_t * ) 0xFFFFFC50 ) )\n#define portRTI_CNT0_UDCP0_REG  ( * ( ( volatile uint32_t * ) 0xFFFFFC54 ) )\n#define portRTI_SETINTENA_REG  \t( * ( ( volatile uint32_t * ) 0xFFFFFC80 ) )\n#define portRTI_CLEARINTENA_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC84 ) )\n#define portRTI_INTFLAG_REG  \t( * ( ( volatile uint32_t * ) 0xFFFFFC88 ) )\n\n\n/* Constants required to set up the initial stack of each task. */\n#define portINITIAL_SPSR\t   \t( ( StackType_t ) 0x1F )\n#define portINITIAL_FPSCR\t  \t( ( StackType_t ) 0x00 )\n#define portINSTRUCTION_SIZE   \t( ( StackType_t ) 0x04 )\n#define portTHUMB_MODE_BIT\t\t( ( StackType_t ) 0x20 )\n\n/* The number of words on the stack frame between the saved Top Of Stack and\nR0 (in which the parameters are passed. */\n#define portSPACE_BETWEEN_TOS_AND_PARAMETERS\t( 12 )\n\n/*-----------------------------------------------------------*/\n\n/* vPortStartFirstSTask() is defined in portASM.asm */\nextern void vPortStartFirstTask( void );\n\n/*-----------------------------------------------------------*/\n\n/* Saved as part of the task context.  Set to pdFALSE if the task does not\nrequire an FPU context. */\nuint32_t ulTaskHasFPUContext = 0;\n\n/*-----------------------------------------------------------*/\n\n\n/*\n * See header file for description.\n */\nStackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )\n{\nStackType_t *pxOriginalTOS;\n\n\tpxOriginalTOS = pxTopOfStack;\n\n\t#if __TI_VFP_SUPPORT__\n\t{\n\t\t/* Ensure the stack is correctly aligned on exit. */\n\t\tpxTopOfStack--;\n\t}\n\t#endif\n\n\t/* Setup the initial stack of the task.  The stack is set exactly as\n\texpected by the portRESTORE_CONTEXT() macro. */\n\n\t/* First on the stack is the return address - which is the start of the as\n\tthe task has not executed yet.  The offset is added to make the return\n\taddress appear as it would within an IRQ ISR. */\n\t*pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;\n\tpxTopOfStack--;\n\n\t*pxTopOfStack = ( StackType_t ) 0x00000000;\t/* R14 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */\n\tpxTopOfStack--;\n\n\t#ifdef portPRELOAD_TASK_REGISTERS\n\t{\n\t\t*pxTopOfStack = ( StackType_t ) 0x12121212;\t/* R12 */\n\t\tpxTopOfStack--;\n\t\t*pxTopOfStack = ( StackType_t ) 0x11111111;\t/* R11 */\n\t\tpxTopOfStack--;\n\t\t*pxTopOfStack = ( StackType_t ) 0x10101010;\t/* R10 */\n\t\tpxTopOfStack--;\n\t\t*pxTopOfStack = ( StackType_t ) 0x09090909;\t/* R9 */\n\t\tpxTopOfStack--;\n\t\t*pxTopOfStack = ( StackType_t ) 0x08080808;\t/* R8 */\n\t\tpxTopOfStack--;\n\t\t*pxTopOfStack = ( StackType_t ) 0x07070707;\t/* R7 */\n\t\tpxTopOfStack--;\n\t\t*pxTopOfStack = ( StackType_t ) 0x06060606;\t/* R6 */\n\t\tpxTopOfStack--;\n\t\t*pxTopOfStack = ( StackType_t ) 0x05050505;\t/* R5 */\n\t\tpxTopOfStack--;\n\t\t*pxTopOfStack = ( StackType_t ) 0x04040404;\t/* R4 */\n\t\tpxTopOfStack--;\n\t\t*pxTopOfStack = ( StackType_t ) 0x03030303;\t/* R3 */\n\t\tpxTopOfStack--;\n\t\t*pxTopOfStack = ( StackType_t ) 0x02020202;\t/* R2 */\n\t\tpxTopOfStack--;\n\t\t*pxTopOfStack = ( StackType_t ) 0x01010101;\t/* R1 */\n\t\tpxTopOfStack--;\n\t}\n\t#else\n\t{\n\t\tpxTopOfStack -= portSPACE_BETWEEN_TOS_AND_PARAMETERS;\n\t}\n\t#endif\n\n\t/* Function parameters are passed in R0. */\n\t*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\n\tpxTopOfStack--;\n\n\t/* Set the status register for system mode, with interrupts enabled. */\n\t*pxTopOfStack = ( StackType_t ) ( ( _get_CPSR() & ~0xFF ) | portINITIAL_SPSR );\n\n\tif( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00 )\n\t{\n\t\t/* The task will start in thumb mode. */\n\t\t*pxTopOfStack |= portTHUMB_MODE_BIT;\n\t}\n\n\t#ifdef __TI_VFP_SUPPORT__\n\t{\n\t\tpxTopOfStack--;\n\n\t\t/* The last thing on the stack is the tasks ulUsingFPU value, which by\n\t\tdefault is set to indicate that the stack frame does not include FPU\n\t\tregisters. */\n\t\t*pxTopOfStack = pdFALSE;\n\t}\n\t#endif\n\n\treturn pxTopOfStack;\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvSetupTimerInterrupt(void)\n{\n\t/* Disable timer 0. */\n\tportRTI_GCTRL_REG &= 0xFFFFFFFEUL;\n\n\t/* Use the internal counter. */\n\tportRTI_TBCTRL_REG = 0x00000000U;\n\n\t/* COMPSEL0 will use the RTIFRC0 counter. */\n\tportRTI_COMPCTRL_REG = 0x00000000U;\n\n\t/* Initialise the counter and the prescale counter registers. */\n\tportRTI_CNT0_UC0_REG =  0x00000000U;\n\tportRTI_CNT0_FRC0_REG =  0x00000000U;\n\n\t/* Set Prescalar for RTI clock. */\n\tportRTI_CNT0_CPUC0_REG = 0x00000001U;\n\tportRTI_CNT0_COMP0_REG = ( configCPU_CLOCK_HZ / 2 ) / configTICK_RATE_HZ;\n\tportRTI_CNT0_UDCP0_REG = ( configCPU_CLOCK_HZ / 2 ) / configTICK_RATE_HZ;\n\n\t/* Clear interrupts. */\n\tportRTI_INTFLAG_REG =  0x0007000FU;\n\tportRTI_CLEARINTENA_REG\t= 0x00070F0FU;\n\n\t/* Enable the compare 0 interrupt. */\n\tportRTI_SETINTENA_REG = 0x00000001U;\n\tportRTI_GCTRL_REG |= 0x00000001U;\n}\n/*-----------------------------------------------------------*/\n\n/*\n * See header file for description.\n */\nBaseType_t xPortStartScheduler(void)\n{\n\t/* Start the timer that generates the tick ISR. */\n\tprvSetupTimerInterrupt();\n\n\t/* Reset the critical section nesting count read to execute the first task. */\n\tulCriticalNesting = 0;\n\n\t/* Start the first task.  This is done from portASM.asm as ARM mode must be\n\tused. */\n\tvPortStartFirstTask();\n\n\t/* Should not get here! */\n\treturn pdFAIL;\n}\n/*-----------------------------------------------------------*/\n\n/*\n * See header file for description.\n */\nvoid vPortEndScheduler(void)\n{\n\t/* Not implemented in ports where there is nothing to return to.\n\tArtificially force an assert. */\n\tconfigASSERT( ulCriticalNesting == 1000UL );\n}\n/*-----------------------------------------------------------*/\n\n#if configUSE_PREEMPTION == 0\n\n\t/* The cooperative scheduler requires a normal IRQ service routine to\n\t * simply increment the system tick. */\n\t__interrupt void vPortNonPreemptiveTick( void )\n\t{\n\t\t/* clear clock interrupt flag */\n\t\tportRTI_INTFLAG_REG = 0x00000001;\n\n\t\t/* Increment the tick count - this may make a delaying task ready\n\t\tto run - but a context switch is not performed. */\n\t\txTaskIncrementTick();\n\t}\n\n #else\n\n\t/*\n\t **************************************************************************\n\t * The preemptive scheduler ISR is written in assembler and can be found\n\t * in the portASM.asm file. This will only get used if portUSE_PREEMPTION\n\t * is set to 1 in portmacro.h\n\t **************************************************************************\n\t */\n\tvoid vPortPreemptiveTick( void );\n\n#endif\n/*-----------------------------------------------------------*/\n\n\n/*\n * Disable interrupts, and keep a count of the nesting depth.\n */\nvoid vPortEnterCritical( void )\n{\n\t/* Disable interrupts as per portDISABLE_INTERRUPTS(); */\n\tportDISABLE_INTERRUPTS();\n\n\t/* Now interrupts are disabled ulCriticalNesting can be accessed\n\tdirectly.  Increment ulCriticalNesting to keep a count of how many times\n\tportENTER_CRITICAL() has been called. */\n\tulCriticalNesting++;\n}\n/*-----------------------------------------------------------*/\n\n/*\n * Decrement the critical nesting count, and if it has reached zero, re-enable\n * interrupts.\n */\nvoid vPortExitCritical( void )\n{\n\tif( ulCriticalNesting > 0 )\n\t{\n\t\t/* Decrement the nesting count as we are leaving a critical section. */\n\t\tulCriticalNesting--;\n\n\t\t/* If the nesting level has reached zero then interrupts should be\n\t\tre-enabled. */\n\t\tif( ulCriticalNesting == 0 )\n\t\t{\n\t\t\t/* Enable interrupts as per portENABLE_INTERRUPTS(). */\n\t\t\tportENABLE_INTERRUPTS();\n\t\t}\n\t}\n}\n/*-----------------------------------------------------------*/\n\n#if __TI_VFP_SUPPORT__\n\n\tvoid vPortTaskUsesFPU( void )\n\t{\n\textern void vPortInitialiseFPSCR( void );\n\n\t\t/* A task is registering the fact that it needs an FPU context.  Set the\n\t\tFPU flag (saved as part of the task context. */\n\t\tulTaskHasFPUContext = pdTRUE;\n\n\t\t/* Initialise the floating point status register. */\n\t\tvPortInitialiseFPSCR();\n\t}\n\n#endif /* __TI_VFP_SUPPORT__ */\n\n/*-----------------------------------------------------------*/\n\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/CCS/ARM_Cortex-R4/portASM.asm",
    "content": ";/*\n; * FreeRTOS Kernel V10.5.1\n; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n; *\n; * SPDX-License-Identifier: MIT\n; *\n; * Permission is hereby granted, free of charge, to any person obtaining a copy of\n; * this software and associated documentation files (the \"Software\"), to deal in\n; * the Software without restriction, including without limitation the rights to\n; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n; * the Software, and to permit persons to whom the Software is furnished to do so,\n; * subject to the following conditions:\n; *\n; * The above copyright notice and this permission notice shall be included in all\n; * copies or substantial portions of the Software.\n; *\n; * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n; *\n; * https://www.FreeRTOS.org\n; * https://github.com/FreeRTOS\n; *\n; */\n\n        .text\n        .arm\n        .ref vTaskSwitchContext\n        .ref xTaskIncrementTick\n        .ref ulTaskHasFPUContext\n\t\t.ref pxCurrentTCB\n\n;/*-----------------------------------------------------------*/\n;\n; Save Task Context\n;\nportSAVE_CONTEXT .macro\n\t\tDSB\n\n\t\t; Push R0 as we are going to use it\n\t\tSTMDB\tSP!, {R0}\n\n\t\t; Set R0 to point to the task stack pointer.\n\t\tSTMDB\tSP,{SP}^\n\t\tSUB\tSP, SP, #4\n\t\tLDMIA\tSP!,{R0}\n\n\t\t; Push the return address onto the stack.\n\t\tSTMDB\tR0!, {LR}\n\n\t\t; Now LR has been saved, it can be used instead of R0.\n\t\tMOV\tLR, R0\n\n\t\t; Pop R0 so it can be saved onto the task stack.\n\t\tLDMIA\tSP!, {R0}\n\n\t\t; Push all the system mode registers onto the task stack.\n\t\tSTMDB\tLR,{R0-LR}^\n\t\tSUB\tLR, LR, #60\n\n\t\t; Push the SPSR onto the task stack.\n\t\tMRS\tR0, SPSR\n\t\tSTMDB\tLR!, {R0}\n\n    .if (__TI_VFP_SUPPORT__)\n\t\t;Determine if the task maintains an FPU context.\n\t\tLDR\tR0, ulFPUContextConst\n\t\tLDR\tR0, [R0]\n\n\t\t; Test the flag\n\t\tCMP\t\tR0, #0\n\n\t\t; If the task is not using a floating point context then skip the\n\t\t; saving of the FPU registers.\n\t\tBEQ\t\t$+16\n\t\tFSTMDBD\tLR!, {D0-D15}\n\t\tFMRX    R1,  FPSCR\n\t\tSTMFD   LR!, {R1}\n\n\t\t; Save the flag\n\t\tSTMDB\tLR!, {R0}\n\t.endif\n\n\t\t; Store the new top of stack for the task.\n\t\tLDR\tR0, pxCurrentTCBConst\n\t\tLDR\tR0, [R0]\n\t\tSTR\tLR, [R0]\n\n        .endm\n\n;/*-----------------------------------------------------------*/\n;\n; Restore Task Context\n;\nportRESTORE_CONTEXT .macro\n\t\tLDR\t\tR0, pxCurrentTCBConst\n\t\tLDR\t\tR0, [R0]\n\t\tLDR\t\tLR, [R0]\n\n\t.if (__TI_VFP_SUPPORT__)\n\t\t; The floating point context flag is the first thing on the stack.\n\t\tLDR\t\tR0, ulFPUContextConst\n\t\tLDMFD\tLR!, {R1}\n\t\tSTR\t\tR1, [R0]\n\n\t\t; Test the flag\n\t\tCMP\t\tR1, #0\n\n\t\t; If the task is not using a floating point context then skip the\n\t\t; VFP register loads.\n\t\tBEQ\t\t$+16\n\n\t\t; Restore the floating point context.\n\t\tLDMFD   LR!, {R0}\n\t\tFLDMIAD\tLR!, {D0-D15}\n\t\tFMXR    FPSCR, R0\n\t.endif\n\n\t\t; Get the SPSR from the stack.\n\t\tLDMFD\tLR!, {R0}\n\t\tMSR\t\tSPSR_CSXF, R0\n\n\t\t; Restore all system mode registers for the task.\n\t\tLDMFD\tLR, {R0-R14}^\n\n\t\t; Restore the return address.\n\t\tLDR\t\tLR, [LR, #+60]\n\n\t\t; And return - correcting the offset in the LR to obtain the\n\t\t; correct address.\n\t\tSUBS\tPC, LR, #4\n        .endm\n\n;/*-----------------------------------------------------------*/\n; Start the first task by restoring its context.\n\n        .def vPortStartFirstTask\n\nvPortStartFirstTask:\n        portRESTORE_CONTEXT\n\n;/*-----------------------------------------------------------*/\n; Yield to another task.\n\n        .def vPortYieldProcessor\n\nvPortYieldProcessor:\n\t\t; Within an IRQ ISR the link register has an offset from the true return\n\t\t; address.  SWI doesn't do this. Add the offset manually so the ISR\n\t\t; return code can be used.\n        ADD     LR, LR, #4\n\n        ; First save the context of the current task.\n        portSAVE_CONTEXT\n\n        ; Select the next task to execute. */\n        BL      vTaskSwitchContext\n\n        ; Restore the context of the task selected to execute.\n        portRESTORE_CONTEXT\n\n;/*-----------------------------------------------------------*/\n; Yield to another task from within the FreeRTOS API\n\n\t\t.def vPortYeildWithinAPI\n\nvPortYeildWithinAPI:\n\t\t; Save the context of the current task.\n\n        portSAVE_CONTEXT\n\t\t; Clear SSI flag.\n\t\tMOVW    R0, #0xFFF4\n\t\tMOVT \tR0, #0xFFFF\n\t\tLDR     R0, [R0]\n\n\t\t; Select the next task to execute. */\n        BL      vTaskSwitchContext\n\n        ; Restore the context of the task selected to execute.\n        portRESTORE_CONTEXT\n\n;/*-----------------------------------------------------------*/\n; Preemptive Tick\n\n        .def vPortPreemptiveTick\n\nvPortPreemptiveTick:\n\n\t\t; Save the context of the current task.\n        portSAVE_CONTEXT\n\n        ; Clear interrupt flag\n        MOVW    R0, #0xFC88\n        MOVT    R0, #0xFFFF\n        MOV     R1, #1\n        STR     R1, [R0]\n\n        ; Increment the tick count, making any adjustments to the blocked lists\n        ; that may be necessary.\n        BL      xTaskIncrementTick\n\n        ; Select the next task to execute.\n        CMP\tR0, #0\n        BLNE    vTaskSwitchContext\n\n        ; Restore the context of the task selected to execute.\n        portRESTORE_CONTEXT\n\n;-------------------------------------------------------------------------------\n\n\t.if (__TI_VFP_SUPPORT__)\n\n\t\t.def vPortInitialiseFPSCR\n\nvPortInitialiseFPSCR:\n\n\t\tMOV\t\tR0, #0\n\t\tFMXR    FPSCR, R0\n\t\tBX\t\tLR\n\n\t.endif ;__TI_VFP_SUPPORT__\n\n\npxCurrentTCBConst\t.word\tpxCurrentTCB\nulFPUContextConst \t.word   ulTaskHasFPUContext\n;-------------------------------------------------------------------------------\n\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/CCS/ARM_Cortex-R4/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef __PORTMACRO_H__\n#define __PORTMACRO_H__\n\n/*-----------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the\n * given hardware and compiler.\n *\n * These settings should not be altered.\n *-----------------------------------------------------------\n */\n\n/* Type definitions. */\n#define portCHAR        char\n#define portFLOAT       float\n#define portDOUBLE      double\n#define portLONG        long\n#define portSHORT       short\n#define portSTACK_TYPE  uint32_t\n#define portBASE_TYPE   long\n\ntypedef portSTACK_TYPE StackType_t;\ntypedef long BaseType_t;\ntypedef unsigned long UBaseType_t;\n\n#if (configUSE_16_BIT_TICKS == 1)\n    typedef uint16_t TickType_t;\n    #define portMAX_DELAY (TickType_t) 0xFFFF\n#else\n    typedef uint32_t TickType_t;\n    #define portMAX_DELAY (TickType_t) 0xFFFFFFFFF\n\n\t/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\n\tnot need to be guarded with a critical section. */\n\t#define portTICK_TYPE_IS_ATOMIC 1\n#endif\n\n\n/* Architecture specifics. */\n#define portSTACK_GROWTH    (-1)\n#define portTICK_PERIOD_MS    ((TickType_t) 1000 / configTICK_RATE_HZ)\n#define portBYTE_ALIGNMENT  8\n\n/* Critical section handling. */\nextern void vPortEnterCritical(void);\nextern void vPortExitCritical(void);\n#define portENTER_CRITICAL()\t\tvPortEnterCritical()\n#define portEXIT_CRITICAL()\t\t\tvPortExitCritical()\n#define portDISABLE_INTERRUPTS()\tasm( \" CPSID I\" )\n#define portENABLE_INTERRUPTS()\t\tasm( \" CPSIE I\" )\n\n/* Scheduler utilities. */\n#pragma SWI_ALIAS( vPortYield, 0 )\nextern void vPortYield( void );\n#define portYIELD()             \tvPortYield()\n#define portSYS_SSIR1_REG\t\t\t( * ( ( volatile uint32_t * ) 0xFFFFFFB0 ) )\n#define portSYS_SSIR1_SSKEY\t\t\t( 0x7500UL )\n#define portYIELD_WITHIN_API()\t\t{ portSYS_SSIR1_REG = portSYS_SSIR1_SSKEY;  asm( \" DSB \" ); asm( \" ISB \" ); }\n#define portYIELD_FROM_ISR( x )\t\tdo { if( x != pdFALSE ) { portSYS_SSIR1_REG = portSYS_SSIR1_SSKEY;  ( void ) portSYS_SSIR1_REG; } } while( 0 )\n\n#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION\n\t#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1\n#endif\n\n/* Architecture specific optimisations. */\n#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1\n\n\t/* Check the configuration. */\n\t#if( configMAX_PRIORITIES > 32 )\n\t\t#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.\n\t#endif\n\n\t/* Store/clear the ready priorities in a bit map. */\n\t#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )\n\t#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )\n\n\t/*-----------------------------------------------------------*/\n\n\t#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __clz( ( uxReadyPriorities ) ) )\n\n#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */\n\n\n/* Task function macros as described on the FreeRTOS.org WEB site. */\n#define portTASK_FUNCTION(vFunction, pvParameters)       void vFunction(void *pvParameters)\n#define portTASK_FUNCTION_PROTO(vFunction, pvParameters) void vFunction(void *pvParameters)\n\n#endif /* __PORTMACRO_H__ */\n\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/CCS/MSP430X/data_model.h",
    "content": ";/*\n; * FreeRTOS Kernel V10.5.1\n; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n; *\n; * SPDX-License-Identifier: MIT\n; *\n; * Permission is hereby granted, free of charge, to any person obtaining a copy of\n; * this software and associated documentation files (the \"Software\"), to deal in\n; * the Software without restriction, including without limitation the rights to\n; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n; * the Software, and to permit persons to whom the Software is furnished to do so,\n; * subject to the following conditions:\n; *\n; * The above copyright notice and this permission notice shall be included in all\n; * copies or substantial portions of the Software.\n; *\n; * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n; *\n; * https://www.FreeRTOS.org\n; * https://github.com/FreeRTOS\n; *\n; */\n\n\t.if $DEFINED( __LARGE_DATA_MODEL__ )\n\t\t.define \"pushm.a\", pushm_x\n\t\t.define \"popm.a\", popm_x\n\t\t.define \"push.a\", push_x\n\t\t.define \"pop.a\", pop_x\n\t\t.define \"mov.a\", mov_x\n\t.else\n\t\t.define \"pushm.w\", pushm_x\n\t\t.define \"popm.w\", popm_x\n\t\t.define \"push.w\", push_x\n\t\t.define \"pop.w\", pop_x\n\t\t.define \"mov.w\", mov_x\n\t.endif\n\n\t.if $DEFINED( __LARGE_CODE_MODEL__ )\n\t\t.define \"calla\", call_x\n\t\t.define \"reta\", ret_x\n\t.else\n\t\t.define \"call\", call_x\n\t\t.define \"ret\", ret_x\n\t.endif\n\n\n\n\n\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/CCS/MSP430X/port.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n/*-----------------------------------------------------------\n * Implementation of functions defined in portable.h for the MSP430X port.\n *----------------------------------------------------------*/\n\n/* Constants required for hardware setup.  The tick ISR runs off the ACLK,\nnot the MCLK. */\n#define portACLK_FREQUENCY_HZ\t\t\t( ( TickType_t ) 32768 )\n#define portINITIAL_CRITICAL_NESTING\t( ( uint16_t ) 10 )\n#define portFLAGS_INT_ENABLED\t\t\t( ( StackType_t ) 0x08 )\n\n/* We require the address of the pxCurrentTCB variable, but don't want to know\nany details of its type. */\ntypedef void TCB_t;\nextern volatile TCB_t * volatile pxCurrentTCB;\n\n/* Each task maintains a count of the critical section nesting depth.  Each\ntime a critical section is entered the count is incremented.  Each time a\ncritical section is exited the count is decremented - with interrupts only\nbeing re-enabled if the count is zero.\n\nusCriticalNesting will get set to zero when the scheduler starts, but must\nnot be initialised to zero as this will cause problems during the startup\nsequence. */\nvolatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;\n/*-----------------------------------------------------------*/\n\n\n/*\n * Sets up the periodic ISR used for the RTOS tick.  This uses timer 0, but\n * could have alternatively used the watchdog timer or timer 1.\n */\nvoid vPortSetupTimerInterrupt( void );\n/*-----------------------------------------------------------*/\n\n/*\n * Initialise the stack of a task to look exactly as if a call to\n * portSAVE_CONTEXT had been called.\n *\n * See the header file portable.h.\n */\nStackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )\n{\nuint16_t *pusTopOfStack;\nuint32_t *pulTopOfStack, ulTemp;\n\n\t/*\n\t\tPlace a few bytes of known values on the bottom of the stack.\n\t\tThis is just useful for debugging and can be included if required.\n\n\t\t*pxTopOfStack = ( StackType_t ) 0x1111;\n\t\tpxTopOfStack--;\n\t\t*pxTopOfStack = ( StackType_t ) 0x2222;\n\t\tpxTopOfStack--;\n\t\t*pxTopOfStack = ( StackType_t ) 0x3333;\n\t\tpxTopOfStack--;\n\t*/\n\n\t/* Data types are need either 16 bits or 32 bits depending on the data \n\tand code model used. */\n\tif( sizeof( pxCode ) == sizeof( uint16_t ) )\n\t{\n\t\tpusTopOfStack = ( uint16_t * ) pxTopOfStack;\n\t\tulTemp = ( uint32_t ) pxCode;\n\t\t*pusTopOfStack = ( uint16_t ) ulTemp;\n\t}\n\telse\n\t{\n\t\t/* Make room for a 20 bit value stored as a 32 bit value. */\n\t\tpusTopOfStack = ( uint16_t * ) pxTopOfStack;\t\t\n\t\tpusTopOfStack--;\n\t\tpulTopOfStack = ( uint32_t * ) pusTopOfStack;\n\t\t*pulTopOfStack = ( uint32_t ) pxCode;\n\t}\n\n\tpusTopOfStack--;\n\t*pusTopOfStack = portFLAGS_INT_ENABLED;\n\tpusTopOfStack -= ( sizeof( StackType_t ) / 2 );\n\t\n\t/* From here on the size of stacked items depends on the memory model. */\n\tpxTopOfStack = ( StackType_t * ) pusTopOfStack;\n\n\t/* Next the general purpose registers. */\n\t#ifdef PRELOAD_REGISTER_VALUES\n\t\t*pxTopOfStack = ( StackType_t ) 0xffff;\n\t\tpxTopOfStack--;\n\t\t*pxTopOfStack = ( StackType_t ) 0xeeee;\n\t\tpxTopOfStack--;\n\t\t*pxTopOfStack = ( StackType_t ) 0xdddd;\n\t\tpxTopOfStack--;\n\t\t*pxTopOfStack = ( StackType_t ) pvParameters;\n\t\tpxTopOfStack--;\n\t\t*pxTopOfStack = ( StackType_t ) 0xbbbb;\n\t\tpxTopOfStack--;\n\t\t*pxTopOfStack = ( StackType_t ) 0xaaaa;\n\t\tpxTopOfStack--;\n\t\t*pxTopOfStack = ( StackType_t ) 0x9999;\n\t\tpxTopOfStack--;\n\t\t*pxTopOfStack = ( StackType_t ) 0x8888;\n\t\tpxTopOfStack--;\t\n\t\t*pxTopOfStack = ( StackType_t ) 0x5555;\n\t\tpxTopOfStack--;\n\t\t*pxTopOfStack = ( StackType_t ) 0x6666;\n\t\tpxTopOfStack--;\n\t\t*pxTopOfStack = ( StackType_t ) 0x5555;\n\t\tpxTopOfStack--;\n\t\t*pxTopOfStack = ( StackType_t ) 0x4444;\n\t\tpxTopOfStack--;\n\t#else\n\t\tpxTopOfStack -= 3;\n\t\t*pxTopOfStack = ( StackType_t ) pvParameters;\n\t\tpxTopOfStack -= 9;\n\t#endif\n\n\t/* A variable is used to keep track of the critical section nesting.\n\tThis variable has to be stored as part of the task context and is\n\tinitially set to zero. */\n\t*pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;\t\n\n\t/* Return a pointer to the top of the stack we have generated so this can\n\tbe stored in the task control block for the task. */\n\treturn pxTopOfStack;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEndScheduler( void )\n{\n\t/* It is unlikely that the MSP430 port will get stopped.  If required simply\n\tdisable the tick interrupt here. */\n}\n/*-----------------------------------------------------------*/\n\n/*\n * Hardware initialisation to generate the RTOS tick.\n */\nvoid vPortSetupTimerInterrupt( void )\n{\n\tvApplicationSetupTimerInterrupt();\n}\n/*-----------------------------------------------------------*/\n\n#pragma vector=configTICK_VECTOR\ninterrupt void vTickISREntry( void )\n{\nextern void vPortTickISR( void );\n\n\t__bic_SR_register_on_exit( SCG1 + SCG0 + OSCOFF + CPUOFF );\n\t#if configUSE_PREEMPTION == 1\n\t\textern void vPortPreemptiveTickISR( void );\n\t\tvPortPreemptiveTickISR();\n\t#else\n\t\textern void vPortCooperativeTickISR( void );\n\t\tvPortCooperativeTickISR();\n\t#endif\n}\n\n\t\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/CCS/MSP430X/portext.asm",
    "content": ";/*\n; * FreeRTOS Kernel V10.5.1\n; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n; *\n; * SPDX-License-Identifier: MIT\n; *\n; * Permission is hereby granted, free of charge, to any person obtaining a copy of\n; * this software and associated documentation files (the \"Software\"), to deal in\n; * the Software without restriction, including without limitation the rights to\n; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n; * the Software, and to permit persons to whom the Software is furnished to do so,\n; * subject to the following conditions:\n; *\n; * The above copyright notice and this permission notice shall be included in all\n; * copies or substantial portions of the Software.\n; *\n; * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n; *\n; * https://www.FreeRTOS.org\n; * https://github.com/FreeRTOS\n; *\n; */\n\n; * The definition of the \"register test\" tasks, as described at the top of\n; * main.c\n\n\t.include data_model.h\n\n\t.global xTaskIncrementTick\n\t.global vTaskSwitchContext\n\t.global vPortSetupTimerInterrupt\n\t.global pxCurrentTCB\n\t.global usCriticalNesting\n\n\t.def vPortPreemptiveTickISR\n\t.def vPortCooperativeTickISR\n\t.def vPortYield\n\t.def xPortStartScheduler\n\n;-----------------------------------------------------------\n\nportSAVE_CONTEXT .macro\n\n\t;Save the remaining registers.\n\tpushm_x\t#12, r15\n\tmov.w\t&usCriticalNesting, r14\n\tpush_x r14\n\tmov_x\t&pxCurrentTCB, r12\n\tmov_x\tsp, 0( r12 )\n\t.endm\n;-----------------------------------------------------------\n\nportRESTORE_CONTEXT .macro\n\n\tmov_x\t&pxCurrentTCB, r12\n\tmov_x\t@r12, sp\n\tpop_x\tr15\n\tmov.w\tr15, &usCriticalNesting\n\tpopm_x\t#12, r15\n\tnop\n\tpop.w\tsr\n\tnop\n\tret_x\n\t.endm\n;-----------------------------------------------------------\n\n;*\n;* The RTOS tick ISR.\n;*\n;* If the cooperative scheduler is in use this simply increments the tick\n;* count.\n;*\n;* If the preemptive scheduler is in use a context switch can also occur.\n;*/\n\n\t.text\n\t.align 2\n\nvPortPreemptiveTickISR: .asmfunc\n\n\t; The sr is not saved in portSAVE_CONTEXT() because vPortYield() needs\n\t;to save it manually before it gets modified (interrupts get disabled).\n\tpush.w sr\n\tportSAVE_CONTEXT\n\n\tcall_x\t#xTaskIncrementTick\n\tcall_x\t#vTaskSwitchContext\n\n\tportRESTORE_CONTEXT\n\t.endasmfunc\n;-----------------------------------------------------------\n\n\t.align 2\n\nvPortCooperativeTickISR: .asmfunc\n\n\t; The sr is not saved in portSAVE_CONTEXT() because vPortYield() needs\n\t;to save it manually before it gets modified (interrupts get disabled).\n\tpush.w sr\n\tportSAVE_CONTEXT\n\n\tcall_x\t#xTaskIncrementTick\n\n\tportRESTORE_CONTEXT\n\n\t.endasmfunc\n;-----------------------------------------------------------\n\n;\n; Manual context switch called by the portYIELD() macro.\n;\n\n\t.align 2\n\nvPortYield: .asmfunc\n\n\t; The sr needs saving before it is modified.\n\tpush.w\tsr\n\n\t; Now the SR is stacked we can disable interrupts.\n\tdint\n\tnop\n\n\t; Save the context of the current task.\n\tportSAVE_CONTEXT\n\n\t; Select the next task to run.\n\tcall_x\t#vTaskSwitchContext\n\n\t; Restore the context of the new task.\n\tportRESTORE_CONTEXT\n\t.endasmfunc\n;-----------------------------------------------------------\n\n\n;\n; Start off the scheduler by initialising the RTOS tick timer, then restoring\n; the context of the first task.\n;\n\n\t.align 2\n\nxPortStartScheduler: .asmfunc\n\n\t; Setup the hardware to generate the tick.  Interrupts are disabled\n\t; when this function is called.\n\tcall_x\t#vPortSetupTimerInterrupt\n\n\t; Restore the context of the first task that is going to run.\n\tportRESTORE_CONTEXT\n\t.endasmfunc\n;-----------------------------------------------------------\n\n\t.end\n\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/CCS/MSP430X/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef PORTMACRO_H\n#define PORTMACRO_H\n\n/*-----------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the\n * given hardware and compiler.\n *\n * These settings should not be altered.\n *-----------------------------------------------------------\n */\n\n/* Hardware includes. */\n#include \"msp430.h\"\n\n/* Type definitions. */\n#define portCHAR\t\tchar\n#define portFLOAT\t\tfloat\n#define portDOUBLE\t\tdouble\n#define portLONG\t\tlong\n#define portSHORT\t\tint\n#define portBASE_TYPE\tportSHORT\n\n/* The stack type changes depending on the data model. */\n#ifdef __LARGE_DATA_MODEL__\n\t#define portSTACK_TYPE uint32_t\n#else\n\t#define portSTACK_TYPE uint16_t\n\t#define portPOINTER_SIZE_TYPE uint16_t\n#endif\n\ntypedef portSTACK_TYPE StackType_t;\ntypedef short BaseType_t;\ntypedef unsigned short UBaseType_t;\n\n#if( configUSE_16_BIT_TICKS == 1 )\n\ttypedef uint16_t TickType_t;\n\t#define portMAX_DELAY ( TickType_t ) 0xffff\n#else\n\ttypedef uint32_t TickType_t;\n\t#define portMAX_DELAY ( TickType_t ) 0xffffffffUL\n#endif\n\n/*-----------------------------------------------------------*/\n\n/* Interrupt control macros. */\n#define portDISABLE_INTERRUPTS()\t_disable_interrupt(); _nop()\n#define portENABLE_INTERRUPTS()\t\t_enable_interrupt(); _nop()\n/*-----------------------------------------------------------*/\n\n/* Critical section control macros. */\n#define portNO_CRITICAL_SECTION_NESTING\t\t( ( uint16_t ) 0 )\n\n#define portENTER_CRITICAL()\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\nextern volatile uint16_t usCriticalNesting;\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tportDISABLE_INTERRUPTS();\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* Now interrupts are disabled usCriticalNesting can be accessed */\t\t\t\\\n\t/* directly.  Increment ulCriticalNesting to keep a count of how many */\t\\\n\t/* times portENTER_CRITICAL() has been called. */\t\t\t\t\t\t\t\\\n\tusCriticalNesting++;\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n}\n\n#define portEXIT_CRITICAL()\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\nextern volatile uint16_t usCriticalNesting;\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tif( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING )\t\t\t\t\t\\\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t/* Decrement the nesting count as we are leaving a critical section. */\t\\\n\t\tusCriticalNesting--;\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t/* If the nesting level has reached zero then interrupts should be */\t\\\n\t\t/* re-enabled. */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tif( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING )\t\t\t\t\\\n\t\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\tportENABLE_INTERRUPTS();\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n}\n/*-----------------------------------------------------------*/\n\n/* Task utilities. */\n\n/*\n * Manual context switch called by portYIELD or taskYIELD.\n */\nextern void vPortYield( void );\n#define portYIELD() vPortYield()\n/*-----------------------------------------------------------*/\n\n/* Hardware specifics. */\n#define portBYTE_ALIGNMENT\t\t\t2\n#define portSTACK_GROWTH\t\t\t( -1 )\n#define portTICK_PERIOD_MS\t\t\t( ( TickType_t ) 1000 / configTICK_RATE_HZ )\n#define portNOP()\t\t\t\t\t__no_operation()\n/*-----------------------------------------------------------*/\n\n/* Task function macros as described on the FreeRTOS.org WEB site. */\n#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\n#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\n\nextern void vTaskSwitchContext( void );\n#define portYIELD_FROM_ISR( x ) do { if( x ) vPortYield(); } while( 0 )\n\nvoid vApplicationSetupTimerInterrupt( void );\n\n/* sizeof( int ) != sizeof( long ) so a full printf() library is required if\nrun time stats information is to be displayed. */\n#define portLU_PRINTF_SPECIFIER_REQUIRED\n\n#endif /* PORTMACRO_H */\n\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/CMakeLists.txt",
    "content": "# FreeRTOS internal cmake file. Do not use it in user top-level project\n\nadd_library(freertos_kernel_port STATIC\n    # 16-Bit DOS ports for BCC\n    $<$<STREQUAL:${FREERTOS_PORT},BCC_16BIT_DOS_FLSH186>:\n        BCC/16BitDOS/common/portcomn.c\n        BCC/16BitDOS/Flsh186/port.c>\n\n    $<$<STREQUAL:${FREERTOS_PORT},BCC_16BIT_DOS_PC>:\n        BCC/16BitDOS/common/portcomn.c\n        BCC/16BitDOS/PC/port.c>\n\n    # ARMv7-M port for Texas Instruments Code Composer Studio\n    $<$<STREQUAL:${FREERTOS_PORT},CCS_ARM_CM3>:\n        CCS/ARM_CM3/port.c\n        CCS/ARM_CM3/portasm.asm>\n\n    # ARMv7E-M port for Texas Instruments Code Composer Studio\n    $<$<STREQUAL:${FREERTOS_PORT},CCS_ARM_CM4F>:\n        CCS/ARM_CM4F/port.c\n        CCS/ARM_CM4F/portasm.asm>\n\n    # ARMv7-R port for Texas Instruments Code Composer Studio\n    $<$<STREQUAL:${FREERTOS_PORT},CCS_ARM_CR4>:\n        CCS/ARM_Cortex-R4/port.c\n        CCS/ARM_Cortex-R4/portASM.asm>\n\n    # Texas Instruments MSP430 port for Texas Instruments Code Composer Studio\n    $<$<STREQUAL:${FREERTOS_PORT},CCS_MSP430X>:\n        CCS/MSP430X/port.c\n        CCS/MSP430X/portext.asm>\n\n    # NXP (formerly Motorola, Freescale) Cold Fire and 68HCS12 ports for Code Warrior\n    $<$<STREQUAL:${FREERTOS_PORT},CODEWARRIOR_COLDFIRE_V1>:\n        CodeWarrior/ColdFire_V1/port.c\n        CodeWarrior/ColdFire_V1/portasm.S>\n\n    $<$<STREQUAL:${FREERTOS_PORT},CODEWARRIOR_COLDFIRE_V2>:\n        CodeWarrior/ColdFire_V2/port.c\n        CodeWarrior/ColdFire_V2/portasm.S>\n\n    $<$<STREQUAL:${FREERTOS_PORT},CODEWARRIOR_HCS12>:\n        CodeWarrior/HCS12/port.c>\n\n    # ARMv7-A port for GCC\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CA9>:\n        GCC/ARM_CA9/port.c\n        GCC/ARM_CA9/portASM.S>\n\n    # ARMv8-A ports for GCC\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CA53_64_BIT>:\n        GCC/ARM_CA53_64_BIT/port.c\n        GCC/ARM_CA53_64_BIT/portASM.S>\n\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CA53_64_BIT_SRE>:\n        GCC/ARM_CA53_64_BIT_SRE/port.c\n        GCC/ARM_CA53_64_BIT_SRE/portASM.S>\n\n    # ARMv6-M port for GCC\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM0>:\n        GCC/ARM_CM0/port.c>\n\n    # ARMv6-M / Cortex-M0 Raspberry PI RP2040 port for GCC\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_RP2040>:\n        ThirdParty/GCC/RP2040/idle_task_static_memory.c\n        ThirdParty/GCC/RP2040/port.c>\n\n    # ARMv7-M ports for GCC\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM3>:\n        GCC/ARM_CM3/port.c>\n\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM3_MPU>:\n        GCC/ARM_CM3_MPU/port.c>\n\n    # ARMv7E-M ports for GCC\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM4_MPU>:\n        GCC/ARM_CM4_MPU/port.c>\n\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM4F>:\n        GCC/ARM_CM4F/port.c>\n\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM7>:\n        GCC/ARM_CM7/r0p1/port.c>\n\n    # ARMv8-M ports for GCC\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM23_NONSECURE>:\n        GCC/ARM_CM23/non_secure/port.c\n        GCC/ARM_CM23/non_secure/portasm.c>\n\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM23_SECURE>:\n        GCC/ARM_CM23/secure/secure_context_port.c\n        GCC/ARM_CM23/secure/secure_context.c\n        GCC/ARM_CM23/secure/secure_heap.c\n        GCC/ARM_CM23/secure/secure_init.c>\n\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM23_NTZ_NONSECURE>:\n        GCC/ARM_CM23_NTZ/non_secure/port.c\n        GCC/ARM_CM23_NTZ/non_secure/portasm.c>\n\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM33_NONSECURE>:\n        GCC/ARM_CM33/non_secure/port.c\n        GCC/ARM_CM33/non_secure/portasm.c>\n\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM33_SECURE>:\n        GCC/ARM_CM33/secure/secure_context_port.c\n        GCC/ARM_CM33/secure/secure_context.c\n        GCC/ARM_CM33/secure/secure_heap.c\n        GCC/ARM_CM33/secure/secure_init.c>\n\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM33_NTZ_NONSECURE>:\n        GCC/ARM_CM33_NTZ/non_secure/port.c\n        GCC/ARM_CM33_NTZ/non_secure/portasm.c>\n\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM33_TFM>:\n        GCC/ARM_CM33_NTZ/non_secure/port.c\n        GCC/ARM_CM33_NTZ/non_secure/portasm.c\n        ThirdParty/GCC/ARM_TFM/os_wrapper_freertos.c>\n\n    # ARMv8.1-M ports for GCC\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM55_NONSECURE>:\n        GCC/ARM_CM55/non_secure/port.c\n        GCC/ARM_CM55/non_secure/portasm.c>\n\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM55_SECURE>:\n        GCC/ARM_CM55/secure/secure_context_port.c\n        GCC/ARM_CM55/secure/secure_context.c\n        GCC/ARM_CM55/secure/secure_heap.c\n        GCC/ARM_CM55/secure/secure_init.c>\n\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM55_NTZ_NONSECURE>:\n        GCC/ARM_CM55_NTZ/non_secure/port.c\n        GCC/ARM_CM55_NTZ/non_secure/portasm.c>\n\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM55_TFM>:\n        GCC/ARM_CM55_NTZ/non_secure/port.c\n        GCC/ARM_CM55_NTZ/non_secure/portasm.c\n        ThirdParty/GCC/ARM_TFM/os_wrapper_freertos.c>\n\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM85_NONSECURE>:\n        GCC/ARM_CM85/non_secure/port.c\n        GCC/ARM_CM85/non_secure/portasm.c>\n\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM85_SECURE>:\n        GCC/ARM_CM85/secure/secure_context_port.c\n        GCC/ARM_CM85/secure/secure_context.c\n        GCC/ARM_CM85/secure/secure_heap.c\n        GCC/ARM_CM85/secure/secure_init.c>\n\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM85_NTZ_NONSECURE>:\n        GCC/ARM_CM85_NTZ/non_secure/port.c\n        GCC/ARM_CM85_NTZ/non_secure/portasm.c>\n\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM85_TFM>:\n        GCC/ARM_CM85_NTZ/non_secure/port.c\n        GCC/ARM_CM85_NTZ/non_secure/portasm.c\n        ThirdParty/GCC/ARM_TFM/os_wrapper_freertos.c>\n\n    # ARMv7-R ports for GCC\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CR5>:\n        GCC/ARM_CR5/port.c\n        GCC/ARM_CR5/portASM.S>\n\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CRX_NOGIC>:\n        GCC/ARM_CRx_No_GIC/port.c\n        GCC/ARM_CRx_No_GIC/portASM.S>\n\n    # ARMv4T ARM7TDMI ports for GCC\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM7_AT91FR40008>:\n        GCC/ARM7_AT91FR40008/port.c\n        GCC/ARM7_AT91FR40008/portISR.c>\n\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM7_AT91SAM7S>:\n        GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.c\n        GCC/ARM7_AT91SAM7S/port.c\n        GCC/ARM7_AT91SAM7S/portISR.c>\n\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM7_LPC2000>:\n        GCC/ARM7_LPC2000/port.c\n        GCC/ARM7_LPC2000/portISR.c>\n\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM7_LPC23XX>:\n        GCC/ARM7_LPC23xx/port.c\n        GCC/ARM7_LPC23xx/portISR.c>\n\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_STR75X>:\n        GCC/STR75x/port.c\n        GCC/STR75x/portISR.c>\n\n    # Microchip (formerly Ateml) AVR8 ports for GCC\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ATMEGA323>:\n        GCC/ATMega323/port.c>\n\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ATMEGA>:\n        ThirdParty/GCC/ATmega/port.c>\n\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_AVRDX>:\n        ThirdParty/Partner-Supported-Ports/GCC/AVR_AVRDx/port.c>\n\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_AVR_MEGA0>:\n        ThirdParty/Partner-Supported-Ports/GCC/AVR_Mega0/port.c>\n\n    # Microchip (formerly Ateml) AVR32 port for GCC\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_AVR32_UC3>:\n        GCC/AVR32_UC3/exception.S\n        GCC/AVR32_UC3/port.c>\n\n    # NXP (formerly Motorola, Freescale) Cold Fire and 68HCS12 ports for GCC\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_COLDFIRE_V2>:\n        GCC/ColdFire_V2/port.c\n        GCC/ColdFire_V2/portasm.S>\n\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_HCS12>:\n        GCC/HCS12/port.c>\n\n    # Cortus APS3 soft core port for GCC\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_CORTUS_APS3>:\n        GCC/CORTUS_APS3/port.c>\n\n    # Renesas (formerly Hitach) H8S port for GCC\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_H8S2329>:\n        GCC/H8S2329/port.c>\n\n    # x86 / IA32 flat memory model port for GCC\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_IA32_FLAT>:\n        GCC/IA32_flat/port.c\n        GCC/IA32_flat/portASM.S>\n\n    # Xilinx MicroBlaze soft core ports for GCC\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_MICROBLAZE>:\n        GCC/MicroBlaze/port.c\n        GCC/MicroBlaze/portasm.s>\n\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_MICROBLAZE_V8>:\n        GCC/MicroBlazeV8/port.c\n        GCC/MicroBlazeV8/port_exceptions.c\n        GCC/MicroBlazeV8/portasm.S>\n\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_MICROBLAZE_V9>:\n        GCC/MicroBlazeV9/port.c\n        GCC/MicroBlazeV9/port_exceptions.c\n        GCC/MicroBlazeV9/portasm.S>\n\n    # Xilinx PCC4XX soft core ports for GCC\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_PPC405_XILINX>:\n        GCC/PPC405_Xilinx/port.c\n        GCC/PPC405_Xilinx/portasm.S>\n\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_PPC440_XILINX>:\n        GCC/PPC440_Xilinx/port.c\n        GCC/PPC440_Xilinx/portasm.S>\n\n     # Texas Instruments MSP430 port for GCC\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_MSP430F449>:\n        GCC/MSP430F449/port.c>\n\n    # Intel (formerly Altera) NIOS II soft core port for GCC\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_NIOSII>:\n        GCC/NiosII/port.c\n        GCC/NiosII/port_asm.S>\n\n    # RISC-V architecture ports for GCC\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_RISC_V>:\n        GCC/RISC-V/port.c\n        GCC/RISC-V/portASM.S>\n\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_RISC_V_PULPINO_VEGA_RV32M1RM>:\n        GCC/RISC-V/port.c\n        GCC/RISC-V/portASM.S>\n\n    # Renesas RL78 port for GCC\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_RL78>:\n        GCC/RL78/port.c\n        GCC/RL78/portasm.S>\n\n    # Renesas RX architecture ports for GCC\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_RX100>:\n        GCC/RX100/port.c>\n\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_RX200>:\n        GCC/RX200/port.c>\n\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_RX600>:\n        GCC/RX600/port.c>\n\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_RX600_V2>:\n        GCC/RX600v2/port.c>\n\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_RX700_V3_DPFPU>:\n        GCC/RX700v3_DPFPU/port.c>\n\n    # Infineon TriCore 1782 port for GCC\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_TRICORE_1782>:\n        GCC/TriCore_1782/port.c\n        GCC/TriCore_1782/porttrap.c>\n\n    # Synopsys ARC architecture ports for GCC\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARC_EM_HS>:\n        ThirdParty/GCC/ARC_EM_HS/arc_freertos_exceptions.c\n        ThirdParty/GCC/ARC_EM_HS/arc_support.s\n        ThirdParty/GCC/ARC_EM_HS/freertos_tls.c\n        ThirdParty/GCC/ARC_EM_HS/port.c>\n\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARC_V1>:\n        ThirdParty/GCC/ARC_v1/arc_freertos_exceptions.c\n        ThirdParty/GCC/ARC_v1/arc_support.s\n        ThirdParty/GCC/ARC_v1/port.c>\n\n    # Posix Simulator port for GCC\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_POSIX>:\n        ThirdParty/GCC/Posix/port.c\n        ThirdParty/GCC/Posix/utils/wait_for_event.c>\n\n    # Xtensa LX / Espressif ESP32 port for GCC\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_XTENSA_ESP32>:\n        ThirdParty/GCC/Xtensa_ESP32/FreeRTOS-openocd.c\n        ThirdParty/GCC/Xtensa_ESP32/port.c\n        ThirdParty/GCC/Xtensa_ESP32/portasm.S\n        ThirdParty/GCC/Xtensa_ESP32/xtensa_context.S\n        ThirdParty/GCC/Xtensa_ESP32/xtensa_init.c\n        ThirdParty/GCC/Xtensa_ESP32/xtensa_intr_asm.S\n        ThirdParty/GCC/Xtensa_ESP32/xtensa_intr.c\n        ThirdParty/GCC/Xtensa_ESP32/xtensa_loadstore_handler.S\n        ThirdParty/GCC/Xtensa_ESP32/xtensa_overlay_os_hook.c\n        ThirdParty/GCC/Xtensa_ESP32/xtensa_vector_defaults.S\n        ThirdParty/GCC/Xtensa_ESP32/xtensa_vectors.S>\n\n    # Renesas (formerly NEC) 78K port for IAR EW78K\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_78K0K>:\n        IAR/78K0R/port.c\n        IAR/78K0R/portasm.s26>\n\n    # ARMv7-A ports for IAR EWARM\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CA5_NOGIC>:\n        IAR/ARM_CA5_No_GIC/port.c\n        IAR/ARM_CA5_No_GIC/portASM.s>\n\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CA9>:\n        IAR/ARM_CA9/port.c\n        IAR/ARM_CA9/portASM.s>\n\n    # ARMv6-M port for IAR EWARM\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM0>:\n        IAR/ARM_CM0/port.c\n        IAR/ARM_CM0/portasm.s>\n\n    # ARMv7-M port for IAR EWARM\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM3>:\n        IAR/ARM_CM3/port.c\n        IAR/ARM_CM3/portasm.s>\n\n    # ARMv7E-M ports for IAR EWARM\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM4F>:\n        IAR/ARM_CM4F/port.c\n        IAR/ARM_CM4F/portasm.s>\n\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM4F_MPU>:\n        IAR/ARM_CM4F_MPU/port.c\n        IAR/ARM_CM4F_MPU/portasm.s>\n\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM7>:\n        IAR/ARM_CM7/r0p1/port.c\n        IAR/ARM_CM7/r0p1/portasm.s>\n\n    # ARMv8-M Ports for IAR EWARM\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM23_NONSECURE>:\n        IAR/ARM_CM23/non_secure/port.c\n        IAR/ARM_CM23/non_secure/portasm.s>\n\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM23_SECURE>:\n        IAR/ARM_CM23/secure/secure_context_port_asm.s\n        IAR/ARM_CM23/secure/secure_context.c\n        IAR/ARM_CM23/secure/secure_heap.c\n        IAR/ARM_CM23/secure/secure_init.c>\n\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM23_NTZ_NONSECURE>:\n        IAR/ARM_CM23_NTZ/non_secure/port.c\n        IAR/ARM_CM23_NTZ/non_secure/portasm.s>\n\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM33_NONSECURE>:\n        IAR/ARM_CM33/non_secure/port.c\n        IAR/ARM_CM33/non_secure/portasm.s>\n\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM33_SECURE>:\n        IAR/ARM_CM33/secure/secure_context_port_asm.s\n        IAR/ARM_CM33/secure/secure_context.c\n        IAR/ARM_CM33/secure/secure_heap.c\n        IAR/ARM_CM33/secure/secure_init.c>\n\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM33_NTZ_NONSECURE>:\n        IAR/ARM_CM33_NTZ/non_secure/port.c\n        IAR/ARM_CM33_NTZ/non_secure/portasm.s>\n\n    # ARMv8.1-M ports for IAR EWARM\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM55_NONSECURE>:\n        IAR/ARM_CM55/non_secure/port.c\n        IAR/ARM_CM55/non_secure/portasm.s>\n\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM55_SECURE>:\n        IAR/ARM_CM55/secure/secure_context_port_asm.s\n        IAR/ARM_CM55/secure/secure_context.c\n        IAR/ARM_CM55/secure/secure_heap.c\n        IAR/ARM_CM55/secure/secure_init.c>\n\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM55_NTZ_NONSECURE>:\n        IAR/ARM_CM55_NTZ/non_secure/port.c\n        IAR/ARM_CM55_NTZ/non_secure/portasm.s>\n\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM85_NONSECURE>:\n        IAR/ARM_CM85/non_secure/port.c\n        IAR/ARM_CM85/non_secure/portasm.s>\n\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM85_SECURE>:\n        IAR/ARM_CM85/secure/secure_context_port_asm.s\n        IAR/ARM_CM85/secure/secure_context.c\n        IAR/ARM_CM85/secure/secure_heap.c\n        IAR/ARM_CM85/secure/secure_init.c>\n\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM85_NTZ_NONSECURE>:\n        IAR/ARM_CM85_NTZ/non_secure/port.c\n        IAR/ARM_CM85_NTZ/non_secure/portasm.s>\n\n    # ARMv7-R Ports for IAR EWARM\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CRX_NOGIC>:\n        IAR/ARM_CRx_No_GIC/port.c\n        IAR/ARM_CRx_No_GIC/portASM.s>\n\n    # Microchip (formerly Atmel) AVR8 ports for IAR EWAVR\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_ATMEGA323>:\n        IAR/ATMega323/port.c\n        IAR/ATMega323/portmacro.s90>\n\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_AVR_AVRDX>:\n        IAR/AVR_AVRDx/port.c\n        IAR/AVR_AVRDx/portmacro.s90>\n\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_AVR_MEGA0>:\n        IAR/AVR_Mega0/port.c\n        IAR/AVR_Mega0/portmacro.s90>\n\n    # Microchip (formerly Atmel) AVR32 port for IAR Embedded Workbench for AVR32\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_AVR32_UC3>:\n        IAR/AVR32_UC3/exception.s82\n        IAR/AVR32_UC3/port.c\n        IAR/AVR32_UC3/read.c\n        IAR/AVR32_UC3/write.c>\n\n    # Texas Instruments MSP430 ports for IAR Embedded Workbench for MSP430\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_MSP430>:\n        IAR/MSP430/port.c\n        IAR/MSP430/portext.s43>\n\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_MSP430X>:\n        IAR/MSP430X/port.c\n        IAR/MSP430X/portext.s43>\n\n    # RISC-V architecture port for IAR Embedded Workbench for RISC-V\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_RISC_V>:\n        IAR/RISC-V/port.c\n        IAR/RISC-V/portASM.s>\n\n    # Renesas RL78 port for IAR EWRL78\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_RL78>:\n        IAR/RL78/port.c\n        IAR/RL78/portasm.s87>\n\n    # Renesas RX architecture ports for IAR EWRX\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_RX100>:\n        IAR/RX100/port.c\n        IAR/RX100/port_asm.s>\n\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_RX600>:\n        IAR/RX600/port.c\n        IAR/RX600/port_asm.s>\n\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_RX700_V3_DPFPU>:\n        IAR/RX700v3_DPFPU/port.c>\n\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_RX_V2>:\n        IAR/RXv2/port.c\n        IAR/RXv2/port_asm.s>\n\n    # Renesas (formerly NEC) V850ES port for IAR EWV850\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_V850ES_FX3>:\n        IAR/V850ES/port.c\n        IAR/V850ES/portasm_Fx3.s85>\n\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_V850ES_HX3>:\n        IAR/V850ES/port.c\n        IAR/V850ES/portasm_Hx2.s85>\n\n    # ARMv4T ARM7TDMI ports for IAR Embedded Workbench for ARM\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_STR71X>:\n        IAR/STR71x/port.c\n        IAR/STR71x/portasm.s79>\n\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_STR75X>:\n        IAR/STR75x/port.c\n        IAR/STR75x/portasm.s79>\n\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_LPC2000>:\n        IAR/LPC2000/port.c\n        IAR/LPC2000/portasm.s79>\n\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_ATMEL_SAM7S64>:\n        IAR/AtmelSAM7S64/port.c\n        IAR/AtmelSAM7S64/portasm.s79>\n\n    # ARMv5TE ARM926 ports for IAR Embedded Workbench for ARM\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_STR91X>:\n        IAR/STR91x/port.c\n        IAR/STR91x/portasm.s79>\n\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_ATMEL_SAM9XE>:\n        IAR/AtmelSAM9XE/port.c\n        IAR/AtmelSAM9XE/portasm.s79>\n\n    # ARM Cortex-M4F port for the MikroElektronika MikroC compiler\n    $<$<STREQUAL:${FREERTOS_PORT},MIKROC_ARM_CM4F>:\n        MikroC/ARM_CM4F/port.c>\n\n    # Microchip PIC18 8-bit MCU port for MPLAB XC8\n    $<$<STREQUAL:${FREERTOS_PORT},MPLAB_PIC18F>:\n        MPLAB/PIC18F/port.c>\n\n    # Microchip PIC24 16-bit MCU port for MPLAB XC16\n    $<$<STREQUAL:${FREERTOS_PORT},MPLAB_PIC24>:\n        MPLAB/PIC24_dsPIC/port.c\n        MPLAB/PIC24_dsPIC/portasm_PIC24.S> # TODO: What to do with portasm_dsPIC.S ?\n\n    # Microchip MIPS 32-Bit MCU ports for MPLAB XC32\n    $<$<STREQUAL:${FREERTOS_PORT},MPLAB_PIC32MEC14XX>:\n        MPLAB/PIC32MEC14xx/port.c\n        MPLAB/PIC32MEC14xx/port_asm.S>\n\n    $<$<STREQUAL:${FREERTOS_PORT},MPLAB_PIC32MX>:\n        MPLAB/PIC32MX/port.c\n        MPLAB/PIC32MX/port_asm.S>\n\n    $<$<STREQUAL:${FREERTOS_PORT},MPLAB_PIC32MZ>:\n        MPLAB/PIC32MZ/port.c\n        MPLAB/PIC32MZ/port_asm.S>\n\n    # Windows Simulator for Microsoft Visual C Compiler and MinGW GCC\n    $<$<STREQUAL:${FREERTOS_PORT},MSVC_MINGW>:\n        MSVC-MingW/port.c>\n\n    # 16 bit DOS ports for Open Watcom\n    $<$<STREQUAL:${FREERTOS_PORT},OWATCOM_16BIT_DOS_FLSH186>:\n        oWatcom/16BitDOS/common/portcomn.c\n        oWatcom/16BitDOS/Flsh186/port.c>\n\n    $<$<STREQUAL:${FREERTOS_PORT},OWATCOM_16BIT_DOS_PC>:\n        oWatcom/16BitDOS/common/portcomn.c\n        oWatcom/16BitDOS/PC/port.c>\n\n    $<$<STREQUAL:${FREERTOS_PORT},PARADIGM_TERN_EE_LARGE>:\n        Paradigm/Tern_EE/large_untested/port.c>\n\n    $<$<STREQUAL:${FREERTOS_PORT},PARADIGM_TERN_EE_SMALL>:\n        Paradigm/Tern_EE/small/port.c>\n\n    # Renesas RX mcu ports for Renesas CC-RX\n    $<$<STREQUAL:${FREERTOS_PORT},RENESAS_RX100>:\n        Renesas/RX100/port.c\n        Renesas/RX100/port_asm.src>\n\n    $<$<STREQUAL:${FREERTOS_PORT},RENESAS_RX200>:\n        Renesas/RX200/port.c\n        Renesas/RX200/port_asm.src>\n\n    $<$<STREQUAL:${FREERTOS_PORT},RENESAS_RX600>:\n        Renesas/RX600/port.c\n        Renesas/RX600/port_asm.src>\n\n    $<$<STREQUAL:${FREERTOS_PORT},RENESAS_RX600_V2>:\n        Renesas/RX600v2/port.c\n        Renesas/RX600v2/port_asm.src>\n\n    $<$<STREQUAL:${FREERTOS_PORT},RENESAS_RX700_V3_DPFPU>:\n        Renesas/RX700v3_DPFPU/port.c\n        Renesas/RX700v3_DPFPU/port_asm.src>\n\n    # Renesas (formerly  Hitach) SHA2 SuperH port for the Renesas SH C Compiler\n    $<$<STREQUAL:${FREERTOS_PORT},RENESAS_SH2A_FPU>:\n        Renesas/SH2A_FPU/port.c\n        Renesas/SH2A_FPU/portasm.src>\n\n    # Texas Instruments MSP430 port for Rowley CrossWorks\n    $<$<STREQUAL:${FREERTOS_PORT},ROWLEY_MSP430F449>:\n        Rowley/MSP430F449/port.c\n        Rowley/MSP430F449/portext.asm>\n\n    # ARMv7-A Cortex-A9 port for ARM RVDS / armcc\n    $<$<STREQUAL:${FREERTOS_PORT},RVDS_ARM_CA9>:\n        RVDS/ARM_CA9/port.c\n        RVDS/ARM_CA9/portASM.s>\n\n    # ARMv6-M port for ARM RVDS / armcc\n    $<$<STREQUAL:${FREERTOS_PORT},RVDS_ARM_CM0>:\n        RVDS/ARM_CM0/port.c>\n\n    # ARMv7-M port for ARM RVDS / armcc\n    $<$<STREQUAL:${FREERTOS_PORT},RVDS_ARM_CM3>:\n        RVDS/ARM_CM3/port.c>\n\n    # ARMv7E-M ports for ARM RVDS / armcc\n    $<$<STREQUAL:${FREERTOS_PORT},RVDS_ARM_CM4_MPU>:\n        RVDS/ARM_CM4_MPU/port.c>\n\n    $<$<STREQUAL:${FREERTOS_PORT},RVDS_ARM_CM4F>:\n        RVDS/ARM_CM4F/port.c>\n\n    $<$<STREQUAL:${FREERTOS_PORT},RVDS_ARM_CM7>:\n        RVDS/ARM_CM7/r0p1/port.c>\n\n    # ARMv4T / ARM7TDMI LPC21XX port for ARM RVDS / armcc\n    $<$<STREQUAL:${FREERTOS_PORT},RVDS_ARM7_LPC21XX>:\n        RVDS/ARM7_LPC21xx/port.c\n        RVDS/ARM7_LPC21xx/portASM.s>\n\n    # Cygnal c8051 port for SDCC (Small Device C Compiler)\n    $<$<STREQUAL:${FREERTOS_PORT},SDCC_CYGNAL>:\n        SDCC/Cygnal/port.c>\n\n    # Infineon (formerly Fujitsu, Spansion, Cypress) MB9x ports for Softune C Compiler\n    $<$<STREQUAL:${FREERTOS_PORT},SOFTUNE_MB91460>:\n        Softune/MB91460/__STD_LIB_sbrk.c\n        Softune/MB91460/port.c>\n\n    $<$<STREQUAL:${FREERTOS_PORT},SOFTUNE_MB96340>:\n        Softune/MB96340/__STD_LIB_sbrk.c\n        Softune/MB96340/port.c>\n\n    # ARMv7E-M (Cortex-M4F) port for TASKING VX-toolset for ARM\n    $<$<STREQUAL:${FREERTOS_PORT},TASKING_ARM_CM4F>:\n        Tasking/ARM_CM4F/port.c\n        Tasking/ARM_CM4F/port_asm.asm>\n\n    # Port for C-SKY T-HEAD CK802\n    $<$<STREQUAL:${FREERTOS_PORT},CDK_THEAD_CK802>:\n        ThirdParty/CDK/T-HEAD_CK802/port.c\n        ThirdParty/CDK/T-HEAD_CK802/portasm.S>\n\n    # Tensilica Xtensa port for XCC\n    $<$<STREQUAL:${FREERTOS_PORT},XCC_XTENSA>:\n        ThirdParty/XCC/Xtensa/port.c\n        ThirdParty/XCC/Xtensa/portasm.S\n        ThirdParty/XCC/Xtensa/portclib.c\n        ThirdParty/XCC/Xtensa/xtensa_context.S\n        ThirdParty/XCC/Xtensa/xtensa_init.c\n        ThirdParty/XCC/Xtensa/xtensa_intr_asm.S\n        ThirdParty/XCC/Xtensa/xtensa_intr.c\n        ThirdParty/XCC/Xtensa/xtensa_overlay_os_hook.c\n        ThirdParty/XCC/Xtensa/xtensa_vectors.S>\n\n    # Microchip PIC18 port for WIZ-C\n    $<$<STREQUAL:${FREERTOS_PORT},WIZC_PIC18>:\n        WizC/PIC18/port.c\n        WizC/PIC18/Drivers/Tick/isrTick.c\n        WizC/PIC18/Drivers/Tick/Tick.c>\n)\n\nif( FREERTOS_PORT MATCHES \"GCC_ARM_CM(3|4)_MPU\" OR\n    FREERTOS_PORT STREQUAL \"IAR_ARM_CM4F_MPU\" OR\n    FREERTOS_PORT STREQUAL \"RVDS_ARM_CM4_MPU\" OR\n    FREERTOS_PORT MATCHES \"GCC_ARM_CM(23|33|55|85)_NTZ_NONSECURE\" OR\n    FREERTOS_PORT MATCHES \"GCC_ARM_CM(23|33|55|85)_NONSECURE\" OR\n    FREERTOS_PORT MATCHES \"GCC_ARM_CM(33|55|85)_TFM\" OR\n    FREERTOS_PORT MATCHES \"IAR_ARM_CM(23|33|55|85)_NTZ_NONSECURE\" OR\n    FREERTOS_PORT MATCHES \"IAR_ARM_CM(23|33|55|85)_NONSECURE\"\n)\n    target_sources(freertos_kernel_port PRIVATE Common/mpu_wrappers.c)\nendif()\n\ntarget_include_directories(freertos_kernel_port PUBLIC\n    # 16-Bit DOS ports for BCC\n    $<$<STREQUAL:${FREERTOS_PORT},BCC_16BIT_DOS_FLSH186>:\n        ${CMAKE_CURRENT_LIST_DIR}/BCC/16BitDOS/common\n        ${CMAKE_CURRENT_LIST_DIR}/BCC/16BitDOS/Flsh186>\n\n    $<$<STREQUAL:${FREERTOS_PORT},BCC_16BIT_DOS_PC>:\n        ${CMAKE_CURRENT_LIST_DIR}/BCC/16BitDOS/common\n        ${CMAKE_CURRENT_LIST_DIR}/BCC/16BitDOS/PC>\n\n    # ARMv7-M port for Texas Instruments Code Composer Studio\n    $<$<STREQUAL:${FREERTOS_PORT},CCS_ARM_CM3>:${CMAKE_CURRENT_LIST_DIR}/CCS/ARM_CM3>\n\n    # ARMv7E-M port for Texas Instruments Code Composer Studio\n    $<$<STREQUAL:${FREERTOS_PORT},CCS_ARM_CM4F>:${CMAKE_CURRENT_LIST_DIR}/CCS/ARM_CM4F>\n\n    # ARMv7-R port for Texas Instruments Code Composer Studio\n    $<$<STREQUAL:${FREERTOS_PORT},CCS_ARM_CR4>:${CMAKE_CURRENT_LIST_DIR}/CCS/ARM_Cortex-R4>\n\n    # Texas Instruments MSP430 port for Texas Instruments Code Composer Studio\n    $<$<STREQUAL:${FREERTOS_PORT},CCS_MSP430X>:${CMAKE_CURRENT_LIST_DIR}/CCS/MSP430X>\n\n    # NXP (formerly Motorola, Freescale) Cold Fire and 68HCS12 ports for Code Warrior\n    $<$<STREQUAL:${FREERTOS_PORT},CODEWARRIOR_COLDFIRE_V1>:${CMAKE_CURRENT_LIST_DIR}/CodeWarrior/ColdFire_V1>\n    $<$<STREQUAL:${FREERTOS_PORT},CODEWARRIOR_COLDFIRE_V2>:${CMAKE_CURRENT_LIST_DIR}/CodeWarrior/ColdFire_V2>\n    $<$<STREQUAL:${FREERTOS_PORT},CODEWARRIOR_HCS12>:${CMAKE_CURRENT_LIST_DIR}/CodeWarrior/HCS12>\n\n    # ARMv7-A port for GCC\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CA9>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CA9>\n\n    # ARMv8-A ports for GCC\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CA53_64_BIT>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CA53_64_BIT>\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CA53_64_BIT_SRE>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CA53_64_BIT_SRE>\n\n    # ARMv6-M port for GCC\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM0>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM0>\n\n    # ARMv6-M / Cortex-M0 Raspberry PI RP2040 port for GCC\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_RP2040>:${CMAKE_CURRENT_LIST_DIR}/ThirdParty/GCC/RP2040/include>\n\n    # ARMv7-M ports for GCC\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM3>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM3>\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM3_MPU>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM3_MPU>\n\n    # ARMv7E-M ports for GCC\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM4_MPU>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM4_MPU>\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM4F>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM4F>\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM7>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM7/r0p1>\n\n    # ARMv8-M ports for GCC\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM23_NONSECURE>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM23/non_secure>\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM23_SECURE>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM23/secure>\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM23_NTZ_NONSECURE>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM23_NTZ/non_secure>\n\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM33_NONSECURE>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM33/non_secure>\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM33_SECURE>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM33/secure>\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM33_NTZ_NONSECURE>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM33_NTZ/non_secure>\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM33_TFM>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM33_NTZ/non_secure>\n\n    # ARMv8.1-M ports for GCC\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM55_NONSECURE>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM55/non_secure>\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM55_SECURE>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM55/secure>\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM55_NTZ_NONSECURE>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM55_NTZ/non_secure>\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM55_TFM>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM85_NTZ/non_secure>\n\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM85_NONSECURE>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM85/non_secure>\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM85_SECURE>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM85/secure>\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM85_NTZ_NONSECURE>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM85_NTZ/non_secure>\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM85_TFM>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM85_NTZ/non_secure>\n\n    # ARMv7-R ports for GCC\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CR5>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CR5>\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CRX_NOGIC>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CRx_No_GIC>\n\n    # ARMv4T ARM7TDMI ports for GCC\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM7_AT91FR40008>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM7_AT91FR40008>\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM7_AT91SAM7S>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM7_AT91SAM7S>\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM7_LPC2000>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM7_LPC2000>\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM7_LPC23XX>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM7_LPC23xx>\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_STR75X>:${CMAKE_CURRENT_LIST_DIR}/GCC/STR75x>\n\n    # Microchip (formerly Ateml) AVR8 ports for GCC\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ATMEGA323>:${CMAKE_CURRENT_LIST_DIR}/GCC/ATMega323>\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ATMEGA>:${CMAKE_CURRENT_LIST_DIR}/ThirdParty/GCC/ATmega>\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_AVRDX>:${CMAKE_CURRENT_LIST_DIR}/ThirdParty/Partner-Supported-Ports/GCC/AVR_AVRDx>\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_AVR_MEGA0>:${CMAKE_CURRENT_LIST_DIR}/ThirdParty/Partner-Supported-Ports/GCC/AVR_Mega0>\n\n    # Microchip (formerly Ateml) AVR32 port for GCC\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_AVR32_UC3>:${CMAKE_CURRENT_LIST_DIR}/GCC/AVR32_UC3>\n\n    # NXP (formerly Motorola, Freescale) Cold Fire and 68HCS12 ports for GCC\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_COLDFIRE_V2>:${CMAKE_CURRENT_LIST_DIR}/GCC/ColdFire_V2>\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_HCS12>:${CMAKE_CURRENT_LIST_DIR}/GCC/HCS12>\n\n    # Cortus APS3 soft core port for GCC\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_CORTUS_APS3>:${CMAKE_CURRENT_LIST_DIR}/GCC/CORTUS_APS3>\n\n    # Renesas (formerly Hitach) H8S port for GCC\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_H8S2329>:${CMAKE_CURRENT_LIST_DIR}/GCC/H8S2329>\n\n    # x86 / IA32 flat memory model port for GCC\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_IA32_FLAT>:${CMAKE_CURRENT_LIST_DIR}/GCC/IA32_flat>\n\n    # Intel (formerly Altera) NIOS II soft core port for GCC\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_NIOSII>:${CMAKE_CURRENT_LIST_DIR}/GCC/NiosII>\n\n    # Texas Instruments MSP430 port for GCC\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_MSP430F449>:${CMAKE_CURRENT_LIST_DIR}/GCC/MSP430F449>\n\n    # Xilinx MicroBlaze soft core ports for GCC\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_MICROBLAZE>:${CMAKE_CURRENT_LIST_DIR}/GCC/MicroBlaze>\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_MICROBLAZE_V8>:${CMAKE_CURRENT_LIST_DIR}/GCC/MicroBlazeV8>\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_MICROBLAZE_V9>:${CMAKE_CURRENT_LIST_DIR}/GCC/MicroBlazeV9>\n\n    # Xilinx PCC4XX soft core ports for GCC\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_PPC405_XILINX>:${CMAKE_CURRENT_LIST_DIR}/GCC/PPC405_Xilinx>\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_PPC440_XILINX>:${CMAKE_CURRENT_LIST_DIR}/GCC/PPC440_Xilinx>\n\n    # RISC-V architecture ports for GCC\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_RISC_V>:\n        ${CMAKE_CURRENT_LIST_DIR}/GCC/RISC-V\n        ${CMAKE_CURRENT_LIST_DIR}/GCC/RISC-V/chip_specific_extensions/RISCV_MTIME_CLINT_no_extensions>\n\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_RISC_V_PULPINO_VEGA_RV32M1RM>:\n        ${CMAKE_CURRENT_LIST_DIR}/GCC/RISC-V\n        ${CMAKE_CURRENT_LIST_DIR}/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM>\n\n    # Renesas RL78 port for GCC\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_RL78>:${CMAKE_CURRENT_LIST_DIR}/GCC/RL78>\n\n    # Renesas RX architecture ports for GCC\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_RX100>:${CMAKE_CURRENT_LIST_DIR}/GCC/RX100>\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_RX200>:${CMAKE_CURRENT_LIST_DIR}/GCC/RX200>\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_RX600>:${CMAKE_CURRENT_LIST_DIR}/GCC/RX600>\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_RX600_V2>:${CMAKE_CURRENT_LIST_DIR}/GCC/RX600v2>\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_RX700_V3_DPFPU>:${CMAKE_CURRENT_LIST_DIR}/GCC/RX700v3_DPFPU>\n\n    # Infineon TriCore 1782 port for GCC\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_TRICORE_1782>:${CMAKE_CURRENT_LIST_DIR}/GCC/TriCore_1782>\n\n    # Synopsys ARC architecture ports for GCC\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARC_EM_HS>:${CMAKE_CURRENT_LIST_DIR}/ThirdParty/GCC/ARC_EM_HS>\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARC_V1>:${CMAKE_CURRENT_LIST_DIR}/ThirdParty/GCC/ARC_v1>\n\n    # Posix Simulator port for GCC\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_POSIX>:\n        ${CMAKE_CURRENT_LIST_DIR}/ThirdParty/GCC/Posix\n        ${CMAKE_CURRENT_LIST_DIR}/ThirdParty/GCC/Posix/utils>\n\n    # Xtensa LX / Espressif ESP32 port for GCC\n    $<$<STREQUAL:${FREERTOS_PORT},GCC_XTENSA_ESP32>:\n        ${CMAKE_CURRENT_LIST_DIR}/ThirdParty/GCC/Xtensa_ESP32\n        ${CMAKE_CURRENT_LIST_DIR}/ThirdParty/GCC/Xtensa_ESP32/include>\n\n    # Renesas (formerly NEC) 78K port for IAR EW78K\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_78K0K>:${CMAKE_CURRENT_LIST_DIR}/IAR/78K0R>\n\n    # ARMv7-A ports for IAR EWARM\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CA5_NOGIC>:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CA5_No_GIC>\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CA9>:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CA9>\n\n    # ARMv6-M port for IAR EWARM\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM0>:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM0>\n\n    # ARMv7-M port for IAR EWARM\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM3>:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM3>\n\n    # ARMv7E-M ports for IAR EWARM\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM4F>:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM4F>\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM4F_MPU>:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM4F_MPU>\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM7>:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM7/r0p1>\n\n    # ARMv8-M Ports for IAR EWARM\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM23_NONSECURE>:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM23/non_secure>\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM23_SECURE>:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM23/secure>\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM23_NTZ_NONSECURE>:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM23_NTZ/non_secure>\n\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM33_NONSECURE>:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM33/non_secure>\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM33_SECURE>:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM33/secure>\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM33_NTZ_NONSECURE>:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM33_NTZ/non_secure>\n\n    # ARMv8.1-M ports for IAR EWARM\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM55_NONSECURE>:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM55/non_secure>\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM55_SECURE>:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM55/secure>\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM55_NTZ_NONSECURE>:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM55_NTZ/non_secure>\n\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM85_NONSECURE>:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM85/non_secure>\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM85_SECURE>:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM85/secure>\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM85_NTZ_NONSECURE>:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM85_NTZ/non_secure>\n\n    # ARMv7-R Ports for IAR EWARM\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CRX_NOGIC>:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CRx_No_GIC>\n\n    # ARMv4T ARM7TDMI ports for IAR Embedded Workbench for ARM\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_STR71X>:${CMAKE_CURRENT_LIST_DIR}/IAR/STR71x>\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_STR75X>:${CMAKE_CURRENT_LIST_DIR}/IAR/STR75x>\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_LPC2000>:${CMAKE_CURRENT_LIST_DIR}/IAR/LPC2000>\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_ATMEL_SAM7S64>:${CMAKE_CURRENT_LIST_DIR}/IAR/AtmelSAM7S64>\n\n    # ARMv5TE ARM926 ports for IAR Embedded Workbench for ARM\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_STR91X>:${CMAKE_CURRENT_LIST_DIR}/IAR/STR91x>\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_ATMEL_SAM9XE>:${CMAKE_CURRENT_LIST_DIR}/IAR/AtmelSAM9XE>\n\n    # Microchip (formerly Atmel) AVR8 ports for IAR EWAVR\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_ATMEGA323>:${CMAKE_CURRENT_LIST_DIR}/IAR/ATMega323>\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_AVR_AVRDX>:${CMAKE_CURRENT_LIST_DIR}/IAR/AVR_AVRDx>\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_AVR_MEGA0>:${CMAKE_CURRENT_LIST_DIR}/IAR/AVR_Mega0>\n\n    # Microchip (formerly Atmel) AVR32 port for IAR Embedded Workbench for AVR32\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_AVR32_UC3>:${CMAKE_CURRENT_LIST_DIR}/IAR/AVR32_UC3>\n\n    # Texas Instruments MSP430 ports for IAR Embedded Workbench for MSP430\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_MSP430>:${CMAKE_CURRENT_LIST_DIR}/IAR/MSP430>\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_MSP430X>:${CMAKE_CURRENT_LIST_DIR}/IAR/MSP430X>\n\n    # RISC-V architecture port for IAR Embedded Workbench for RISC-V\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_RISC_V>:\n        ${CMAKE_CURRENT_LIST_DIR}/IAR/RISC-V\n        ${CMAKE_CURRENT_LIST_DIR}/IAR/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions>\n\n    # Renesas RL78 port for IAR EWRL78\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_RL78>:${CMAKE_CURRENT_LIST_DIR}/IAR/RL78>\n\n    # Renesas RX architecture ports for IAR EWRX\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_RX100>:${CMAKE_CURRENT_LIST_DIR}/IAR/RX100>\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_RX600>:${CMAKE_CURRENT_LIST_DIR}/IAR/RX600>\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_RX700_V3_DPFPU>:${CMAKE_CURRENT_LIST_DIR}/IAR/RX700v3_DPFPU>\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_RX_V2>:${CMAKE_CURRENT_LIST_DIR}/IAR/RXv2>\n\n    # Renesas (formerly NEC) V850ES port for IAR EWV850\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_V850ES_FX3>:${CMAKE_CURRENT_LIST_DIR}/IAR/V850ES>\n    $<$<STREQUAL:${FREERTOS_PORT},IAR_V850ES_HX3>:${CMAKE_CURRENT_LIST_DIR}/IAR/V850ES>\n\n    # ARM Cortex-M4F port for the MikroElektronika MikroC compiler\n    $<$<STREQUAL:${FREERTOS_PORT},MIKROC_ARM_CM4F>:${CMAKE_CURRENT_LIST_DIR}/MikroC/ARM_CM4F>\n\n    # Microchip PIC18 8-bit MCU port for MPLAB XC8\n    $<$<STREQUAL:${FREERTOS_PORT},MPLAB_PIC18F>:${CMAKE_CURRENT_LIST_DIR}/MPLAB/PIC18F>\n\n    # Microchip PIC24 16-bit MCU port for MPLAB XC16\n    $<$<STREQUAL:${FREERTOS_PORT},MPLAB_PIC24>:${CMAKE_CURRENT_LIST_DIR}/MPLAB/PIC24_dsPIC>\n\n    # Microchip MIPS 32-Bit MCU ports for MPLAB XC32\n    $<$<STREQUAL:${FREERTOS_PORT},MPLAB_PIC32MEC14XX>:${CMAKE_CURRENT_LIST_DIR}/MPLAB/PIC32MEC14xx>\n    $<$<STREQUAL:${FREERTOS_PORT},MPLAB_PIC32MX>:${CMAKE_CURRENT_LIST_DIR}/MPLAB/PIC32MX>\n    $<$<STREQUAL:${FREERTOS_PORT},MPLAB_PIC32MZ>:${CMAKE_CURRENT_LIST_DIR}/MPLAB/PIC32MZ>\n\n    # Windows Simulator for Microsoft Visual C Compiler and MinGW GCC\n    $<$<STREQUAL:${FREERTOS_PORT},MSVC_MINGW>:${CMAKE_CURRENT_LIST_DIR}/MSVC-MingW>\n\n    # 16 bit DOS ports for Open Watcom\n    $<$<STREQUAL:${FREERTOS_PORT},OWATCOM_16BIT_DOS_FLSH186>:\n        ${CMAKE_CURRENT_LIST_DIR}/oWatcom/16BitDOS/common\n        ${CMAKE_CURRENT_LIST_DIR}/oWatcom/16BitDOS/Flsh186>\n    $<$<STREQUAL:${FREERTOS_PORT},OWATCOM_16BIT_DOS_PC>:\n        ${CMAKE_CURRENT_LIST_DIR}/oWatcom/16BitDOS/common\n        ${CMAKE_CURRENT_LIST_DIR}/oWatcom/16BitDOS/PC>\n\n    $<$<STREQUAL:${FREERTOS_PORT},PARADIGM_TERN_EE_LARGE>:${CMAKE_CURRENT_LIST_DIR}/Paradigm/Tern_EE/large_untested>\n    $<$<STREQUAL:${FREERTOS_PORT},PARADIGM_TERN_EE_SMALL>:${CMAKE_CURRENT_LIST_DIR}/Paradigm/Tern_EE/small>\n\n    # Renesas RX mcu ports for Renesas CC-RX\n    $<$<STREQUAL:${FREERTOS_PORT},RENESAS_RX100>:${CMAKE_CURRENT_LIST_DIR}/Renesas/RX100>\n    $<$<STREQUAL:${FREERTOS_PORT},RENESAS_RX200>:${CMAKE_CURRENT_LIST_DIR}/Renesas/RX200>\n    $<$<STREQUAL:${FREERTOS_PORT},RENESAS_RX600>:${CMAKE_CURRENT_LIST_DIR}/Renesas/RX600>\n    $<$<STREQUAL:${FREERTOS_PORT},RENESAS_RX600_V2>:${CMAKE_CURRENT_LIST_DIR}/Renesas/RX600v2>\n    $<$<STREQUAL:${FREERTOS_PORT},RENESAS_RX700_V3_DPFPU>:${CMAKE_CURRENT_LIST_DIR}/Renesas/RX700v3_DPFPU>\n\n    # Renesas (formerly  Hitach) SHA2 SuperH port for the Renesas SH C Compiler\n    $<$<STREQUAL:${FREERTOS_PORT},RENESAS_SH2A_FPU>:${CMAKE_CURRENT_LIST_DIR}/Renesas/SH2A_FPU>\n\n    # Texas Instruments MSP430 port for Rowley CrossWorks\n    $<$<STREQUAL:${FREERTOS_PORT},ROWLEY_MSP430F449>:${CMAKE_CURRENT_LIST_DIR}/Rowley/MSP430F449>\n\n    # ARMv7-A Cortex-A9 port for ARM RVDS / armcc\n    $<$<STREQUAL:${FREERTOS_PORT},RVDS_ARM_CA9>:${CMAKE_CURRENT_LIST_DIR}/RVDS/ARM_CA9>\n\n    # ARMv6-M port for ARM RVDS / armcc\n    $<$<STREQUAL:${FREERTOS_PORT},RVDS_ARM_CM0>:${CMAKE_CURRENT_LIST_DIR}/RVDS/ARM_CM0>\n\n    # ARMv7-M port for ARM RVDS / armcc\n    $<$<STREQUAL:${FREERTOS_PORT},RVDS_ARM_CM3>:${CMAKE_CURRENT_LIST_DIR}/RVDS/ARM_CM3>\n\n    # ARMv7E-M ports for ARM RVDS / armcc\n    $<$<STREQUAL:${FREERTOS_PORT},RVDS_ARM_CM4_MPU>:${CMAKE_CURRENT_LIST_DIR}/RVDS/ARM_CM4_MPU>\n    $<$<STREQUAL:${FREERTOS_PORT},RVDS_ARM_CM4F>:${CMAKE_CURRENT_LIST_DIR}/RVDS/ARM_CM4F>\n    $<$<STREQUAL:${FREERTOS_PORT},RVDS_ARM_CM7>:${CMAKE_CURRENT_LIST_DIR}/RVDS/ARM_CM7/r0p1>\n\n    # ARMv4T / ARM7TDMI LPC21XX port for ARM RVDS / armcc\n    $<$<STREQUAL:${FREERTOS_PORT},RVDS_ARM7_LPC21XX>:${CMAKE_CURRENT_LIST_DIR}/RVDS/ARM7_LPC21xx>\n\n    # Cygnal c8051 port for SDCC (Small Device C Compiler)\n    $<$<STREQUAL:${FREERTOS_PORT},SDCC_CYGNAL>:${CMAKE_CURRENT_LIST_DIR}/SDCC/Cygnal>\n\n    # Infineon (formerly Fujitsu, Spansion, Cypress) MB9x ports for Softune C Compiler\n    $<$<STREQUAL:${FREERTOS_PORT},SOFTUNE_MB91460>:${CMAKE_CURRENT_LIST_DIR}/Softune/MB91460>\n    $<$<STREQUAL:${FREERTOS_PORT},SOFTUNE_MB96340>:${CMAKE_CURRENT_LIST_DIR}/Softune/MB96340>\n\n    # ARMv7E-M (Cortex-M4F) port for TASKING VX-toolset for ARM\n    $<$<STREQUAL:${FREERTOS_PORT},TASKING_ARM_CM4F>:${CMAKE_CURRENT_LIST_DIR}/Tasking/ARM_CM4F>\n\n    # Port for C-SKY T-HEAD CK802\n    $<$<STREQUAL:${FREERTOS_PORT},CDK_THEAD_CK802>:${CMAKE_CURRENT_LIST_DIR}/ThirdParty/CDK/T-HEAD_CK802>\n\n    # Tensilica Xtensa port for XCC\n    $<$<STREQUAL:${FREERTOS_PORT},XCC_XTENSA>:${CMAKE_CURRENT_LIST_DIR}/ThirdParty/XCC/Xtensa>\n\n    # Microchip PIC18 port for WIZ-C\n    $<$<STREQUAL:${FREERTOS_PORT},WIZC_PIC18>:${CMAKE_CURRENT_LIST_DIR}/WizC/PIC18>\n)\n\ntarget_link_libraries(freertos_kernel_port\n    PUBLIC\n        $<$<STREQUAL:${FREERTOS_PORT},GCC_RP2040>:pico_base_headers>\n        $<$<STREQUAL:${FREERTOS_PORT},GCC_XTENSA_ESP32>:idf::esp32>\n    PRIVATE\n        freertos_kernel\n        \"$<$<STREQUAL:${FREERTOS_PORT},GCC_RP2040>:hardware_clocks;hardware_exception>\"\n        $<$<STREQUAL:${FREERTOS_PORT},MSVC_MINGW>:winmm> # Windows library which implements timers\n)\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/Common/mpu_wrappers.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/*\n * Implementation of the wrapper functions used to raise the processor privilege\n * before calling a standard FreeRTOS API function.\n */\n\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\n * all the API functions to use the MPU wrappers.  That should only be done when\n * task.h is included from an application file. */\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n#include \"queue.h\"\n#include \"timers.h\"\n#include \"event_groups.h\"\n#include \"stream_buffer.h\"\n#include \"mpu_prototypes.h\"\n\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n/*-----------------------------------------------------------*/\n\n#if ( portUSING_MPU_WRAPPERS == 1 )\n\n    #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n        BaseType_t MPU_xTaskCreate( TaskFunction_t pvTaskCode,\n                                    const char * const pcName,\n                                    uint16_t usStackDepth,\n                                    void * pvParameters,\n                                    UBaseType_t uxPriority,\n                                    TaskHandle_t * pxCreatedTask ) /* FREERTOS_SYSTEM_CALL */\n        {\n            BaseType_t xReturn;\n\n            if( portIS_PRIVILEGED() == pdFALSE )\n            {\n                portRAISE_PRIVILEGE();\n                portMEMORY_BARRIER();\n\n                uxPriority = uxPriority & ~( portPRIVILEGE_BIT );\n                portMEMORY_BARRIER();\n\n                xReturn = xTaskCreate( pvTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask );\n                portMEMORY_BARRIER();\n\n                portRESET_PRIVILEGE();\n                portMEMORY_BARRIER();\n            }\n            else\n            {\n                xReturn = xTaskCreate( pvTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask );\n            }\n\n            return xReturn;\n        }\n    #endif /* configSUPPORT_DYNAMIC_ALLOCATION */\n/*-----------------------------------------------------------*/\n\n    #if ( configSUPPORT_STATIC_ALLOCATION == 1 )\n        TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode,\n                                            const char * const pcName,\n                                            const uint32_t ulStackDepth,\n                                            void * const pvParameters,\n                                            UBaseType_t uxPriority,\n                                            StackType_t * const puxStackBuffer,\n                                            StaticTask_t * const pxTaskBuffer ) /* FREERTOS_SYSTEM_CALL */\n        {\n            TaskHandle_t xReturn;\n\n            if( portIS_PRIVILEGED() == pdFALSE )\n            {\n                portRAISE_PRIVILEGE();\n                portMEMORY_BARRIER();\n\n                uxPriority = uxPriority & ~( portPRIVILEGE_BIT );\n                portMEMORY_BARRIER();\n\n                xReturn = xTaskCreateStatic( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer );\n                portMEMORY_BARRIER();\n\n                portRESET_PRIVILEGE();\n                portMEMORY_BARRIER();\n            }\n            else\n            {\n                xReturn = xTaskCreateStatic( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer );\n            }\n\n            return xReturn;\n        }\n    #endif /* configSUPPORT_STATIC_ALLOCATION */\n/*-----------------------------------------------------------*/\n\n    #if ( INCLUDE_vTaskDelete == 1 )\n        void MPU_vTaskDelete( TaskHandle_t pxTaskToDelete ) /* FREERTOS_SYSTEM_CALL */\n        {\n            if( portIS_PRIVILEGED() == pdFALSE )\n            {\n                portRAISE_PRIVILEGE();\n                portMEMORY_BARRIER();\n\n                vTaskDelete( pxTaskToDelete );\n                portMEMORY_BARRIER();\n\n                portRESET_PRIVILEGE();\n                portMEMORY_BARRIER();\n            }\n            else\n            {\n                vTaskDelete( pxTaskToDelete );\n            }\n        }\n    #endif /* if ( INCLUDE_vTaskDelete == 1 ) */\n/*-----------------------------------------------------------*/\n\n    #if ( INCLUDE_xTaskDelayUntil == 1 )\n        BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,\n                                        TickType_t xTimeIncrement ) /* FREERTOS_SYSTEM_CALL */\n        {\n            BaseType_t xReturn;\n\n            if( portIS_PRIVILEGED() == pdFALSE )\n            {\n                portRAISE_PRIVILEGE();\n                portMEMORY_BARRIER();\n\n                xReturn = xTaskDelayUntil( pxPreviousWakeTime, xTimeIncrement );\n                portMEMORY_BARRIER();\n\n                portRESET_PRIVILEGE();\n                portMEMORY_BARRIER();\n            }\n            else\n            {\n                xReturn = xTaskDelayUntil( pxPreviousWakeTime, xTimeIncrement );\n            }\n\n            return xReturn;\n        }\n    #endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */\n/*-----------------------------------------------------------*/\n\n    #if ( INCLUDE_xTaskAbortDelay == 1 )\n        BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */\n        {\n            BaseType_t xReturn;\n\n            if( portIS_PRIVILEGED() == pdFALSE )\n            {\n                portRAISE_PRIVILEGE();\n                portMEMORY_BARRIER();\n\n                xReturn = xTaskAbortDelay( xTask );\n                portMEMORY_BARRIER();\n\n                portRESET_PRIVILEGE();\n                portMEMORY_BARRIER();\n            }\n            else\n            {\n                xReturn = xTaskAbortDelay( xTask );\n            }\n\n            return xReturn;\n        }\n    #endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */\n/*-----------------------------------------------------------*/\n\n    #if ( INCLUDE_vTaskDelay == 1 )\n        void MPU_vTaskDelay( TickType_t xTicksToDelay ) /* FREERTOS_SYSTEM_CALL */\n        {\n            if( portIS_PRIVILEGED() == pdFALSE )\n            {\n                portRAISE_PRIVILEGE();\n                portMEMORY_BARRIER();\n\n                vTaskDelay( xTicksToDelay );\n                portMEMORY_BARRIER();\n\n                portRESET_PRIVILEGE();\n                portMEMORY_BARRIER();\n            }\n            else\n            {\n                vTaskDelay( xTicksToDelay );\n            }\n        }\n    #endif /* if ( INCLUDE_vTaskDelay == 1 ) */\n/*-----------------------------------------------------------*/\n\n    #if ( INCLUDE_uxTaskPriorityGet == 1 )\n        UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t pxTask ) /* FREERTOS_SYSTEM_CALL */\n        {\n            UBaseType_t uxReturn;\n\n            if( portIS_PRIVILEGED() == pdFALSE )\n            {\n                portRAISE_PRIVILEGE();\n                portMEMORY_BARRIER();\n\n                uxReturn = uxTaskPriorityGet( pxTask );\n                portMEMORY_BARRIER();\n\n                portRESET_PRIVILEGE();\n                portMEMORY_BARRIER();\n            }\n            else\n            {\n                uxReturn = uxTaskPriorityGet( pxTask );\n            }\n\n            return uxReturn;\n        }\n    #endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */\n/*-----------------------------------------------------------*/\n\n    #if ( INCLUDE_vTaskPrioritySet == 1 )\n        void MPU_vTaskPrioritySet( TaskHandle_t pxTask,\n                                   UBaseType_t uxNewPriority ) /* FREERTOS_SYSTEM_CALL */\n        {\n            if( portIS_PRIVILEGED() == pdFALSE )\n            {\n                portRAISE_PRIVILEGE();\n                portMEMORY_BARRIER();\n\n                vTaskPrioritySet( pxTask, uxNewPriority );\n                portMEMORY_BARRIER();\n\n                portRESET_PRIVILEGE();\n                portMEMORY_BARRIER();\n            }\n            else\n            {\n                vTaskPrioritySet( pxTask, uxNewPriority );\n            }\n        }\n    #endif /* if ( INCLUDE_vTaskPrioritySet == 1 ) */\n/*-----------------------------------------------------------*/\n\n    #if ( INCLUDE_eTaskGetState == 1 )\n        eTaskState MPU_eTaskGetState( TaskHandle_t pxTask ) /* FREERTOS_SYSTEM_CALL */\n        {\n            eTaskState eReturn;\n\n            if( portIS_PRIVILEGED() == pdFALSE )\n            {\n                portRAISE_PRIVILEGE();\n                portMEMORY_BARRIER();\n\n                eReturn = eTaskGetState( pxTask );\n                portMEMORY_BARRIER();\n\n                portRESET_PRIVILEGE();\n                portMEMORY_BARRIER();\n            }\n            else\n            {\n                eReturn = eTaskGetState( pxTask );\n            }\n\n            return eReturn;\n        }\n    #endif /* if ( INCLUDE_eTaskGetState == 1 ) */\n/*-----------------------------------------------------------*/\n\n    #if ( configUSE_TRACE_FACILITY == 1 )\n        void MPU_vTaskGetInfo( TaskHandle_t xTask,\n                               TaskStatus_t * pxTaskStatus,\n                               BaseType_t xGetFreeStackSpace,\n                               eTaskState eState ) /* FREERTOS_SYSTEM_CALL */\n        {\n            if( portIS_PRIVILEGED() == pdFALSE )\n            {\n                portRAISE_PRIVILEGE();\n                portMEMORY_BARRIER();\n\n                vTaskGetInfo( xTask, pxTaskStatus, xGetFreeStackSpace, eState );\n                portMEMORY_BARRIER();\n\n                portRESET_PRIVILEGE();\n                portMEMORY_BARRIER();\n            }\n            else\n            {\n                vTaskGetInfo( xTask, pxTaskStatus, xGetFreeStackSpace, eState );\n            }\n        }\n    #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */\n/*-----------------------------------------------------------*/\n\n    #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )\n        TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* FREERTOS_SYSTEM_CALL */\n        {\n            TaskHandle_t xReturn;\n\n            if( portIS_PRIVILEGED() == pdFALSE )\n            {\n                portRAISE_PRIVILEGE();\n                portMEMORY_BARRIER();\n                xReturn = xTaskGetIdleTaskHandle();\n                portMEMORY_BARRIER();\n\n                portRESET_PRIVILEGE();\n                portMEMORY_BARRIER();\n            }\n            else\n            {\n                xReturn = xTaskGetIdleTaskHandle();\n            }\n\n            return xReturn;\n        }\n    #endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */\n/*-----------------------------------------------------------*/\n\n    #if ( INCLUDE_vTaskSuspend == 1 )\n        void MPU_vTaskSuspend( TaskHandle_t pxTaskToSuspend ) /* FREERTOS_SYSTEM_CALL */\n        {\n            if( portIS_PRIVILEGED() == pdFALSE )\n            {\n                portRAISE_PRIVILEGE();\n                portMEMORY_BARRIER();\n\n                vTaskSuspend( pxTaskToSuspend );\n                portMEMORY_BARRIER();\n\n                portRESET_PRIVILEGE();\n                portMEMORY_BARRIER();\n            }\n            else\n            {\n                vTaskSuspend( pxTaskToSuspend );\n            }\n        }\n    #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */\n/*-----------------------------------------------------------*/\n\n    #if ( INCLUDE_vTaskSuspend == 1 )\n        void MPU_vTaskResume( TaskHandle_t pxTaskToResume ) /* FREERTOS_SYSTEM_CALL */\n        {\n            if( portIS_PRIVILEGED() == pdFALSE )\n            {\n                portRAISE_PRIVILEGE();\n                portMEMORY_BARRIER();\n\n                vTaskResume( pxTaskToResume );\n                portMEMORY_BARRIER();\n\n                portRESET_PRIVILEGE();\n                portMEMORY_BARRIER();\n            }\n            else\n            {\n                vTaskResume( pxTaskToResume );\n            }\n        }\n    #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */\n/*-----------------------------------------------------------*/\n\n    void MPU_vTaskSuspendAll( void ) /* FREERTOS_SYSTEM_CALL */\n    {\n        if( portIS_PRIVILEGED() == pdFALSE )\n        {\n            portRAISE_PRIVILEGE();\n            portMEMORY_BARRIER();\n\n            vTaskSuspendAll();\n            portMEMORY_BARRIER();\n\n            portRESET_PRIVILEGE();\n            portMEMORY_BARRIER();\n        }\n        else\n        {\n            vTaskSuspendAll();\n        }\n    }\n/*-----------------------------------------------------------*/\n\n    BaseType_t MPU_xTaskResumeAll( void ) /* FREERTOS_SYSTEM_CALL */\n    {\n        BaseType_t xReturn;\n\n        if( portIS_PRIVILEGED() == pdFALSE )\n        {\n            portRAISE_PRIVILEGE();\n            portMEMORY_BARRIER();\n\n            xReturn = xTaskResumeAll();\n            portMEMORY_BARRIER();\n\n            portRESET_PRIVILEGE();\n            portMEMORY_BARRIER();\n        }\n        else\n        {\n            xReturn = xTaskResumeAll();\n        }\n\n        return xReturn;\n    }\n/*-----------------------------------------------------------*/\n\n    TickType_t MPU_xTaskGetTickCount( void ) /* FREERTOS_SYSTEM_CALL */\n    {\n        TickType_t xReturn;\n\n        if( portIS_PRIVILEGED() == pdFALSE )\n        {\n            portRAISE_PRIVILEGE();\n            portMEMORY_BARRIER();\n\n            xReturn = xTaskGetTickCount();\n            portMEMORY_BARRIER();\n\n            portRESET_PRIVILEGE();\n            portMEMORY_BARRIER();\n        }\n        else\n        {\n            xReturn = xTaskGetTickCount();\n        }\n\n        return xReturn;\n    }\n/*-----------------------------------------------------------*/\n\n    UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* FREERTOS_SYSTEM_CALL */\n    {\n        UBaseType_t uxReturn;\n\n        if( portIS_PRIVILEGED() == pdFALSE )\n        {\n            portRAISE_PRIVILEGE();\n            portMEMORY_BARRIER();\n\n            uxReturn = uxTaskGetNumberOfTasks();\n            portMEMORY_BARRIER();\n\n            portRESET_PRIVILEGE();\n            portMEMORY_BARRIER();\n        }\n        else\n        {\n            uxReturn = uxTaskGetNumberOfTasks();\n        }\n\n        return uxReturn;\n    }\n/*-----------------------------------------------------------*/\n\n    char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* FREERTOS_SYSTEM_CALL */\n    {\n        char * pcReturn;\n\n        if( portIS_PRIVILEGED() == pdFALSE )\n        {\n            portRAISE_PRIVILEGE();\n            portMEMORY_BARRIER();\n\n            pcReturn = pcTaskGetName( xTaskToQuery );\n            portMEMORY_BARRIER();\n\n            portRESET_PRIVILEGE();\n            portMEMORY_BARRIER();\n        }\n        else\n        {\n            pcReturn = pcTaskGetName( xTaskToQuery );\n        }\n\n        return pcReturn;\n    }\n/*-----------------------------------------------------------*/\n\n    #if ( INCLUDE_xTaskGetHandle == 1 )\n        TaskHandle_t MPU_xTaskGetHandle( const char * pcNameToQuery ) /* FREERTOS_SYSTEM_CALL */\n        {\n            TaskHandle_t xReturn;\n\n            if( portIS_PRIVILEGED() == pdFALSE )\n            {\n                portRAISE_PRIVILEGE();\n                portMEMORY_BARRIER();\n\n                xReturn = xTaskGetHandle( pcNameToQuery );\n                portMEMORY_BARRIER();\n\n                portRESET_PRIVILEGE();\n                portMEMORY_BARRIER();\n            }\n            else\n            {\n                xReturn = xTaskGetHandle( pcNameToQuery );\n            }\n\n            return xReturn;\n        }\n    #endif /* if ( INCLUDE_xTaskGetHandle == 1 ) */\n/*-----------------------------------------------------------*/\n\n    #if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )\n        void MPU_vTaskList( char * pcWriteBuffer ) /* FREERTOS_SYSTEM_CALL */\n        {\n            if( portIS_PRIVILEGED() == pdFALSE )\n            {\n                portRAISE_PRIVILEGE();\n                portMEMORY_BARRIER();\n\n                vTaskList( pcWriteBuffer );\n                portMEMORY_BARRIER();\n\n                portRESET_PRIVILEGE();\n                portMEMORY_BARRIER();\n            }\n            else\n            {\n                vTaskList( pcWriteBuffer );\n            }\n        }\n    #endif /* if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */\n/*-----------------------------------------------------------*/\n\n    #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )\n        void MPU_vTaskGetRunTimeStats( char * pcWriteBuffer ) /* FREERTOS_SYSTEM_CALL */\n        {\n            if( portIS_PRIVILEGED() == pdFALSE )\n            {\n                portRAISE_PRIVILEGE();\n                portMEMORY_BARRIER();\n\n                vTaskGetRunTimeStats( pcWriteBuffer );\n                portMEMORY_BARRIER();\n\n                portRESET_PRIVILEGE();\n                portMEMORY_BARRIER();\n            }\n            else\n            {\n                vTaskGetRunTimeStats( pcWriteBuffer );\n            }\n        }\n    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */\n/*-----------------------------------------------------------*/\n\n    #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )\n        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* FREERTOS_SYSTEM_CALL */\n        {\n            configRUN_TIME_COUNTER_TYPE xReturn;\n\n            if( portIS_PRIVILEGED() == pdFALSE )\n            {\n                portRAISE_PRIVILEGE();\n                portMEMORY_BARRIER();\n\n                xReturn = ulTaskGetIdleRunTimePercent();\n                portMEMORY_BARRIER();\n\n                portRESET_PRIVILEGE();\n                portMEMORY_BARRIER();\n            }\n            else\n            {\n                xReturn = ulTaskGetIdleRunTimePercent();\n            }\n\n            return xReturn;\n        }\n    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */\n/*-----------------------------------------------------------*/\n\n    #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )\n        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* FREERTOS_SYSTEM_CALL */\n        {\n            configRUN_TIME_COUNTER_TYPE xReturn;\n\n            if( portIS_PRIVILEGED() == pdFALSE )\n            {\n                portRAISE_PRIVILEGE();\n                portMEMORY_BARRIER();\n\n                xReturn = ulTaskGetIdleRunTimeCounter();\n                portMEMORY_BARRIER();\n\n                portRESET_PRIVILEGE();\n                portMEMORY_BARRIER();\n            }\n            else\n            {\n                xReturn = ulTaskGetIdleRunTimeCounter();\n            }\n\n            return xReturn;\n        }\n    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */\n/*-----------------------------------------------------------*/\n\n    #if ( configUSE_APPLICATION_TASK_TAG == 1 )\n        void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,\n                                             TaskHookFunction_t pxTagValue ) /* FREERTOS_SYSTEM_CALL */\n        {\n            if( portIS_PRIVILEGED() == pdFALSE )\n            {\n                portRAISE_PRIVILEGE();\n                portMEMORY_BARRIER();\n\n                vTaskSetApplicationTaskTag( xTask, pxTagValue );\n                portMEMORY_BARRIER();\n\n                portRESET_PRIVILEGE();\n                portMEMORY_BARRIER();\n            }\n            else\n            {\n                vTaskSetApplicationTaskTag( xTask, pxTagValue );\n            }\n        }\n    #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */\n/*-----------------------------------------------------------*/\n\n    #if ( configUSE_APPLICATION_TASK_TAG == 1 )\n        TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */\n        {\n            TaskHookFunction_t xReturn;\n\n            if( portIS_PRIVILEGED() == pdFALSE )\n            {\n                portRAISE_PRIVILEGE();\n                portMEMORY_BARRIER();\n\n                xReturn = xTaskGetApplicationTaskTag( xTask );\n                portMEMORY_BARRIER();\n\n                portRESET_PRIVILEGE();\n                portMEMORY_BARRIER();\n            }\n            else\n            {\n                xReturn = xTaskGetApplicationTaskTag( xTask );\n            }\n\n            return xReturn;\n        }\n    #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */\n/*-----------------------------------------------------------*/\n\n    #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )\n        void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,\n                                                    BaseType_t xIndex,\n                                                    void * pvValue ) /* FREERTOS_SYSTEM_CALL */\n        {\n            if( portIS_PRIVILEGED() == pdFALSE )\n            {\n                portRAISE_PRIVILEGE();\n                portMEMORY_BARRIER();\n\n                vTaskSetThreadLocalStoragePointer( xTaskToSet, xIndex, pvValue );\n                portMEMORY_BARRIER();\n\n                portRESET_PRIVILEGE();\n                portMEMORY_BARRIER();\n            }\n            else\n            {\n                vTaskSetThreadLocalStoragePointer( xTaskToSet, xIndex, pvValue );\n            }\n        }\n    #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */\n/*-----------------------------------------------------------*/\n\n    #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )\n        void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,\n                                                       BaseType_t xIndex ) /* FREERTOS_SYSTEM_CALL */\n        {\n            void * pvReturn;\n\n            if( portIS_PRIVILEGED() == pdFALSE )\n            {\n                portRAISE_PRIVILEGE();\n                portMEMORY_BARRIER();\n\n                pvReturn = pvTaskGetThreadLocalStoragePointer( xTaskToQuery, xIndex );\n                portMEMORY_BARRIER();\n\n                portRESET_PRIVILEGE();\n                portMEMORY_BARRIER();\n            }\n            else\n            {\n                pvReturn = pvTaskGetThreadLocalStoragePointer( xTaskToQuery, xIndex );\n            }\n\n            return pvReturn;\n        }\n    #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */\n/*-----------------------------------------------------------*/\n\n    #if ( configUSE_APPLICATION_TASK_TAG == 1 )\n        BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask,\n                                                     void * pvParameter ) /* FREERTOS_SYSTEM_CALL */\n        {\n            BaseType_t xReturn;\n\n            if( portIS_PRIVILEGED() == pdFALSE )\n            {\n                portRAISE_PRIVILEGE();\n                portMEMORY_BARRIER();\n\n                xReturn = xTaskCallApplicationTaskHook( xTask, pvParameter );\n                portMEMORY_BARRIER();\n\n                portRESET_PRIVILEGE();\n                portMEMORY_BARRIER();\n            }\n            else\n            {\n                xReturn = xTaskCallApplicationTaskHook( xTask, pvParameter );\n            }\n\n            return xReturn;\n        }\n    #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */\n/*-----------------------------------------------------------*/\n\n    #if ( configUSE_TRACE_FACILITY == 1 )\n        UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * pxTaskStatusArray,\n                                              UBaseType_t uxArraySize,\n                                              configRUN_TIME_COUNTER_TYPE * pulTotalRunTime ) /* FREERTOS_SYSTEM_CALL */\n        {\n            UBaseType_t uxReturn;\n\n            if( portIS_PRIVILEGED() == pdFALSE )\n            {\n                portRAISE_PRIVILEGE();\n                portMEMORY_BARRIER();\n\n                uxReturn = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, pulTotalRunTime );\n                portMEMORY_BARRIER();\n\n                portRESET_PRIVILEGE();\n                portMEMORY_BARRIER();\n            }\n            else\n            {\n                uxReturn = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, pulTotalRunTime );\n            }\n\n            return uxReturn;\n        }\n    #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */\n/*-----------------------------------------------------------*/\n\n    BaseType_t MPU_xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) /* FREERTOS_SYSTEM_CALL */\n    {\n        BaseType_t xReturn;\n\n        if( portIS_PRIVILEGED() == pdFALSE )\n        {\n            portRAISE_PRIVILEGE();\n            portMEMORY_BARRIER();\n\n            xReturn = xTaskCatchUpTicks( xTicksToCatchUp );\n            portMEMORY_BARRIER();\n\n            portRESET_PRIVILEGE();\n            portMEMORY_BARRIER();\n        }\n        else\n        {\n            xReturn = xTaskCatchUpTicks( xTicksToCatchUp );\n        }\n\n        return xReturn;\n    }\n/*-----------------------------------------------------------*/\n\n    #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )\n        UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */\n        {\n            UBaseType_t uxReturn;\n\n            if( portIS_PRIVILEGED() == pdFALSE )\n            {\n                portRAISE_PRIVILEGE();\n                portMEMORY_BARRIER();\n\n                uxReturn = uxTaskGetStackHighWaterMark( xTask );\n                portMEMORY_BARRIER();\n\n                portRESET_PRIVILEGE();\n                portMEMORY_BARRIER();\n            }\n            else\n            {\n                uxReturn = uxTaskGetStackHighWaterMark( xTask );\n            }\n\n            return uxReturn;\n        }\n    #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */\n/*-----------------------------------------------------------*/\n\n    #if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )\n        configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */\n        {\n            configSTACK_DEPTH_TYPE uxReturn;\n\n            if( portIS_PRIVILEGED() == pdFALSE )\n            {\n                portRAISE_PRIVILEGE();\n                portMEMORY_BARRIER();\n\n                uxReturn = uxTaskGetStackHighWaterMark2( xTask );\n                portMEMORY_BARRIER();\n\n                portRESET_PRIVILEGE();\n                portMEMORY_BARRIER();\n            }\n            else\n            {\n                uxReturn = uxTaskGetStackHighWaterMark2( xTask );\n            }\n\n            return uxReturn;\n        }\n    #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */\n/*-----------------------------------------------------------*/\n\n    #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )\n        TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* FREERTOS_SYSTEM_CALL */\n        {\n            TaskHandle_t xReturn;\n\n            if( portIS_PRIVILEGED() == pdFALSE )\n            {\n                portRAISE_PRIVILEGE();\n                portMEMORY_BARRIER();\n                xReturn = xTaskGetCurrentTaskHandle();\n                portMEMORY_BARRIER();\n\n                portRESET_PRIVILEGE();\n                portMEMORY_BARRIER();\n            }\n            else\n            {\n                xReturn = xTaskGetCurrentTaskHandle();\n            }\n\n            return xReturn;\n        }\n    #endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */\n/*-----------------------------------------------------------*/\n\n    #if ( INCLUDE_xTaskGetSchedulerState == 1 )\n        BaseType_t MPU_xTaskGetSchedulerState( void ) /* FREERTOS_SYSTEM_CALL */\n        {\n            BaseType_t xReturn;\n\n            if( portIS_PRIVILEGED() == pdFALSE )\n            {\n                portRAISE_PRIVILEGE();\n                portMEMORY_BARRIER();\n\n                xReturn = xTaskGetSchedulerState();\n                portMEMORY_BARRIER();\n\n                portRESET_PRIVILEGE();\n                portMEMORY_BARRIER();\n            }\n            else\n            {\n                xReturn = xTaskGetSchedulerState();\n            }\n\n            return xReturn;\n        }\n    #endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */\n/*-----------------------------------------------------------*/\n\n    void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* FREERTOS_SYSTEM_CALL */\n    {\n        if( portIS_PRIVILEGED() == pdFALSE )\n        {\n            portRAISE_PRIVILEGE();\n            portMEMORY_BARRIER();\n\n            vTaskSetTimeOutState( pxTimeOut );\n            portMEMORY_BARRIER();\n\n            portRESET_PRIVILEGE();\n            portMEMORY_BARRIER();\n        }\n        else\n        {\n            vTaskSetTimeOutState( pxTimeOut );\n        }\n    }\n/*-----------------------------------------------------------*/\n\n    BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,\n                                         TickType_t * const pxTicksToWait ) /* FREERTOS_SYSTEM_CALL */\n    {\n        BaseType_t xReturn;\n\n        if( portIS_PRIVILEGED() == pdFALSE )\n        {\n            portRAISE_PRIVILEGE();\n            portMEMORY_BARRIER();\n\n            xReturn = xTaskCheckForTimeOut( pxTimeOut, pxTicksToWait );\n            portMEMORY_BARRIER();\n\n            portRESET_PRIVILEGE();\n            portMEMORY_BARRIER();\n        }\n        else\n        {\n            xReturn = xTaskCheckForTimeOut( pxTimeOut, pxTicksToWait );\n        }\n\n        return xReturn;\n    }\n/*-----------------------------------------------------------*/\n\n    #if ( configUSE_TASK_NOTIFICATIONS == 1 )\n        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,\n                                           UBaseType_t uxIndexToNotify,\n                                           uint32_t ulValue,\n                                           eNotifyAction eAction,\n                                           uint32_t * pulPreviousNotificationValue ) /* FREERTOS_SYSTEM_CALL */\n        {\n            BaseType_t xReturn;\n\n            if( portIS_PRIVILEGED() == pdFALSE )\n            {\n                portRAISE_PRIVILEGE();\n                portMEMORY_BARRIER();\n\n                xReturn = xTaskGenericNotify( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pulPreviousNotificationValue );\n                portMEMORY_BARRIER();\n\n                portRESET_PRIVILEGE();\n                portMEMORY_BARRIER();\n            }\n            else\n            {\n                xReturn = xTaskGenericNotify( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pulPreviousNotificationValue );\n            }\n\n            return xReturn;\n        }\n    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */\n/*-----------------------------------------------------------*/\n\n    #if ( configUSE_TASK_NOTIFICATIONS == 1 )\n        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,\n                                               uint32_t ulBitsToClearOnEntry,\n                                               uint32_t ulBitsToClearOnExit,\n                                               uint32_t * pulNotificationValue,\n                                               TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */\n        {\n            BaseType_t xReturn;\n\n            if( portIS_PRIVILEGED() == pdFALSE )\n            {\n                portRAISE_PRIVILEGE();\n                portMEMORY_BARRIER();\n\n                xReturn = xTaskGenericNotifyWait( uxIndexToWaitOn, ulBitsToClearOnEntry, ulBitsToClearOnExit, pulNotificationValue, xTicksToWait );\n                portMEMORY_BARRIER();\n\n                portRESET_PRIVILEGE();\n                portMEMORY_BARRIER();\n            }\n            else\n            {\n                xReturn = xTaskGenericNotifyWait( uxIndexToWaitOn, ulBitsToClearOnEntry, ulBitsToClearOnExit, pulNotificationValue, xTicksToWait );\n            }\n\n            return xReturn;\n        }\n    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */\n/*-----------------------------------------------------------*/\n\n    #if ( configUSE_TASK_NOTIFICATIONS == 1 )\n        uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,\n                                              BaseType_t xClearCountOnExit,\n                                              TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */\n        {\n            uint32_t ulReturn;\n\n            if( portIS_PRIVILEGED() == pdFALSE )\n            {\n                portRAISE_PRIVILEGE();\n                portMEMORY_BARRIER();\n\n                ulReturn = ulTaskGenericNotifyTake( uxIndexToWaitOn, xClearCountOnExit, xTicksToWait );\n                portMEMORY_BARRIER();\n\n                portRESET_PRIVILEGE();\n                portMEMORY_BARRIER();\n            }\n            else\n            {\n                ulReturn = ulTaskGenericNotifyTake( uxIndexToWaitOn, xClearCountOnExit, xTicksToWait );\n            }\n\n            return ulReturn;\n        }\n    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */\n/*-----------------------------------------------------------*/\n\n    #if ( configUSE_TASK_NOTIFICATIONS == 1 )\n        BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,\n                                                     UBaseType_t uxIndexToClear ) /* FREERTOS_SYSTEM_CALL */\n        {\n            BaseType_t xReturn;\n\n            if( portIS_PRIVILEGED() == pdFALSE )\n            {\n                portRAISE_PRIVILEGE();\n                portMEMORY_BARRIER();\n\n                xReturn = xTaskGenericNotifyStateClear( xTask, uxIndexToClear );\n                portMEMORY_BARRIER();\n\n                portRESET_PRIVILEGE();\n                portMEMORY_BARRIER();\n            }\n            else\n            {\n                xReturn = xTaskGenericNotifyStateClear( xTask, uxIndexToClear );\n            }\n\n            return xReturn;\n        }\n    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */\n/*-----------------------------------------------------------*/\n\n    #if ( configUSE_TASK_NOTIFICATIONS == 1 )\n        uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,\n                                                    UBaseType_t uxIndexToClear,\n                                                    uint32_t ulBitsToClear ) /* FREERTOS_SYSTEM_CALL */\n        {\n            uint32_t ulReturn;\n\n            if( portIS_PRIVILEGED() == pdFALSE )\n            {\n                portRAISE_PRIVILEGE();\n                portMEMORY_BARRIER();\n\n                ulReturn = ulTaskGenericNotifyValueClear( xTask, uxIndexToClear, ulBitsToClear );\n                portMEMORY_BARRIER();\n\n                portRESET_PRIVILEGE();\n                portMEMORY_BARRIER();\n            }\n            else\n            {\n                ulReturn = ulTaskGenericNotifyValueClear( xTask, uxIndexToClear, ulBitsToClear );\n            }\n\n            return ulReturn;\n        }\n    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */\n/*-----------------------------------------------------------*/\n\n    #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n        QueueHandle_t MPU_xQueueGenericCreate( UBaseType_t uxQueueLength,\n                                               UBaseType_t uxItemSize,\n                                               uint8_t ucQueueType ) /* FREERTOS_SYSTEM_CALL */\n        {\n            QueueHandle_t xReturn;\n\n            if( portIS_PRIVILEGED() == pdFALSE )\n            {\n                portRAISE_PRIVILEGE();\n                portMEMORY_BARRIER();\n\n                xReturn = xQueueGenericCreate( uxQueueLength, uxItemSize, ucQueueType );\n                portMEMORY_BARRIER();\n\n                portRESET_PRIVILEGE();\n                portMEMORY_BARRIER();\n            }\n            else\n            {\n                xReturn = xQueueGenericCreate( uxQueueLength, uxItemSize, ucQueueType );\n            }\n\n            return xReturn;\n        }\n    #endif /* if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) */\n/*-----------------------------------------------------------*/\n\n    #if ( configSUPPORT_STATIC_ALLOCATION == 1 )\n        QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength,\n                                                     const UBaseType_t uxItemSize,\n                                                     uint8_t * pucQueueStorage,\n                                                     StaticQueue_t * pxStaticQueue,\n                                                     const uint8_t ucQueueType ) /* FREERTOS_SYSTEM_CALL */\n        {\n            QueueHandle_t xReturn;\n\n            if( portIS_PRIVILEGED() == pdFALSE )\n            {\n                portRAISE_PRIVILEGE();\n                portMEMORY_BARRIER();\n\n                xReturn = xQueueGenericCreateStatic( uxQueueLength, uxItemSize, pucQueueStorage, pxStaticQueue, ucQueueType );\n                portMEMORY_BARRIER();\n\n                portRESET_PRIVILEGE();\n                portMEMORY_BARRIER();\n            }\n            else\n            {\n                xReturn = xQueueGenericCreateStatic( uxQueueLength, uxItemSize, pucQueueStorage, pxStaticQueue, ucQueueType );\n            }\n\n            return xReturn;\n        }\n    #endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */\n/*-----------------------------------------------------------*/\n\n    BaseType_t MPU_xQueueGenericReset( QueueHandle_t pxQueue,\n                                       BaseType_t xNewQueue ) /* FREERTOS_SYSTEM_CALL */\n    {\n        BaseType_t xReturn;\n\n        if( portIS_PRIVILEGED() == pdFALSE )\n        {\n            portRAISE_PRIVILEGE();\n            portMEMORY_BARRIER();\n\n            xReturn = xQueueGenericReset( pxQueue, xNewQueue );\n            portMEMORY_BARRIER();\n\n            portRESET_PRIVILEGE();\n            portMEMORY_BARRIER();\n        }\n        else\n        {\n            xReturn = xQueueGenericReset( pxQueue, xNewQueue );\n        }\n\n        return xReturn;\n    }\n/*-----------------------------------------------------------*/\n\n    BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,\n                                      const void * const pvItemToQueue,\n                                      TickType_t xTicksToWait,\n                                      BaseType_t xCopyPosition ) /* FREERTOS_SYSTEM_CALL */\n    {\n        BaseType_t xReturn;\n\n        if( portIS_PRIVILEGED() == pdFALSE )\n        {\n            portRAISE_PRIVILEGE();\n            portMEMORY_BARRIER();\n\n            xReturn = xQueueGenericSend( xQueue, pvItemToQueue, xTicksToWait, xCopyPosition );\n            portMEMORY_BARRIER();\n\n            portRESET_PRIVILEGE();\n            portMEMORY_BARRIER();\n        }\n        else\n        {\n            xReturn = xQueueGenericSend( xQueue, pvItemToQueue, xTicksToWait, xCopyPosition );\n        }\n\n        return xReturn;\n    }\n/*-----------------------------------------------------------*/\n\n    UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t pxQueue ) /* FREERTOS_SYSTEM_CALL */\n    {\n        UBaseType_t uxReturn;\n\n        if( portIS_PRIVILEGED() == pdFALSE )\n        {\n            portRAISE_PRIVILEGE();\n            portMEMORY_BARRIER();\n\n            uxReturn = uxQueueMessagesWaiting( pxQueue );\n            portMEMORY_BARRIER();\n\n            portRESET_PRIVILEGE();\n            portMEMORY_BARRIER();\n        }\n        else\n        {\n            uxReturn = uxQueueMessagesWaiting( pxQueue );\n        }\n\n        return uxReturn;\n    }\n/*-----------------------------------------------------------*/\n\n    UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */\n    {\n        UBaseType_t uxReturn;\n\n        if( portIS_PRIVILEGED() == pdFALSE )\n        {\n            portRAISE_PRIVILEGE();\n            portMEMORY_BARRIER();\n\n            uxReturn = uxQueueSpacesAvailable( xQueue );\n            portMEMORY_BARRIER();\n\n            portRESET_PRIVILEGE();\n            portMEMORY_BARRIER();\n        }\n        else\n        {\n            uxReturn = uxQueueSpacesAvailable( xQueue );\n        }\n\n        return uxReturn;\n    }\n/*-----------------------------------------------------------*/\n\n    BaseType_t MPU_xQueueReceive( QueueHandle_t pxQueue,\n                                  void * const pvBuffer,\n                                  TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */\n    {\n        BaseType_t xReturn;\n\n        if( portIS_PRIVILEGED() == pdFALSE )\n        {\n            portRAISE_PRIVILEGE();\n            portMEMORY_BARRIER();\n\n            xReturn = xQueueReceive( pxQueue, pvBuffer, xTicksToWait );\n            portMEMORY_BARRIER();\n\n            portRESET_PRIVILEGE();\n            portMEMORY_BARRIER();\n        }\n        else\n        {\n            xReturn = xQueueReceive( pxQueue, pvBuffer, xTicksToWait );\n        }\n\n        return xReturn;\n    }\n/*-----------------------------------------------------------*/\n\n    BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,\n                               void * const pvBuffer,\n                               TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */\n    {\n        BaseType_t xReturn;\n\n        if( portIS_PRIVILEGED() == pdFALSE )\n        {\n            portRAISE_PRIVILEGE();\n            portMEMORY_BARRIER();\n\n            xReturn = xQueuePeek( xQueue, pvBuffer, xTicksToWait );\n            portMEMORY_BARRIER();\n\n            portRESET_PRIVILEGE();\n            portMEMORY_BARRIER();\n        }\n        else\n        {\n            xReturn = xQueuePeek( xQueue, pvBuffer, xTicksToWait );\n        }\n\n        return xReturn;\n    }\n/*-----------------------------------------------------------*/\n\n    BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,\n                                        TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */\n    {\n        BaseType_t xReturn;\n\n        if( portIS_PRIVILEGED() == pdFALSE )\n        {\n            portRAISE_PRIVILEGE();\n            portMEMORY_BARRIER();\n\n            xReturn = xQueueSemaphoreTake( xQueue, xTicksToWait );\n            portMEMORY_BARRIER();\n\n            portRESET_PRIVILEGE();\n            portMEMORY_BARRIER();\n        }\n        else\n        {\n            xReturn = xQueueSemaphoreTake( xQueue, xTicksToWait );\n        }\n\n        return xReturn;\n    }\n/*-----------------------------------------------------------*/\n\n    #if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )\n        TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* FREERTOS_SYSTEM_CALL */\n        {\n            void * xReturn;\n\n            if( portIS_PRIVILEGED() == pdFALSE )\n            {\n                portRAISE_PRIVILEGE();\n                portMEMORY_BARRIER();\n\n                xReturn = xQueueGetMutexHolder( xSemaphore );\n                portMEMORY_BARRIER();\n\n                portRESET_PRIVILEGE();\n                portMEMORY_BARRIER();\n            }\n            else\n            {\n                xReturn = xQueueGetMutexHolder( xSemaphore );\n            }\n\n            return xReturn;\n        }\n    #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */\n/*-----------------------------------------------------------*/\n\n    #if ( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )\n        QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType ) /* FREERTOS_SYSTEM_CALL */\n        {\n            QueueHandle_t xReturn;\n\n            if( portIS_PRIVILEGED() == pdFALSE )\n            {\n                portRAISE_PRIVILEGE();\n                portMEMORY_BARRIER();\n\n                xReturn = xQueueCreateMutex( ucQueueType );\n                portMEMORY_BARRIER();\n\n                portRESET_PRIVILEGE();\n                portMEMORY_BARRIER();\n            }\n            else\n            {\n                xReturn = xQueueCreateMutex( ucQueueType );\n            }\n\n            return xReturn;\n        }\n    #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */\n/*-----------------------------------------------------------*/\n\n    #if ( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )\n        QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType,\n                                                   StaticQueue_t * pxStaticQueue ) /* FREERTOS_SYSTEM_CALL */\n        {\n            QueueHandle_t xReturn;\n\n            if( portIS_PRIVILEGED() == pdFALSE )\n            {\n                portRAISE_PRIVILEGE();\n                portMEMORY_BARRIER();\n\n                xReturn = xQueueCreateMutexStatic( ucQueueType, pxStaticQueue );\n                portMEMORY_BARRIER();\n\n                portRESET_PRIVILEGE();\n                portMEMORY_BARRIER();\n            }\n            else\n            {\n                xReturn = xQueueCreateMutexStatic( ucQueueType, pxStaticQueue );\n            }\n\n            return xReturn;\n        }\n    #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) */\n/*-----------------------------------------------------------*/\n\n    #if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )\n        QueueHandle_t MPU_xQueueCreateCountingSemaphore( UBaseType_t uxCountValue,\n                                                         UBaseType_t uxInitialCount ) /* FREERTOS_SYSTEM_CALL */\n        {\n            QueueHandle_t xReturn;\n\n            if( portIS_PRIVILEGED() == pdFALSE )\n            {\n                portRAISE_PRIVILEGE();\n                portMEMORY_BARRIER();\n\n                xReturn = xQueueCreateCountingSemaphore( uxCountValue, uxInitialCount );\n                portMEMORY_BARRIER();\n\n                portRESET_PRIVILEGE();\n                portMEMORY_BARRIER();\n            }\n            else\n            {\n                xReturn = xQueueCreateCountingSemaphore( uxCountValue, uxInitialCount );\n            }\n\n            return xReturn;\n        }\n    #endif /* if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */\n/*-----------------------------------------------------------*/\n\n    #if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )\n\n        QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount,\n                                                               const UBaseType_t uxInitialCount,\n                                                               StaticQueue_t * pxStaticQueue ) /* FREERTOS_SYSTEM_CALL */\n        {\n            QueueHandle_t xReturn;\n\n            if( portIS_PRIVILEGED() == pdFALSE )\n            {\n                portRAISE_PRIVILEGE();\n                portMEMORY_BARRIER();\n\n                xReturn = xQueueCreateCountingSemaphoreStatic( uxMaxCount, uxInitialCount, pxStaticQueue );\n                portMEMORY_BARRIER();\n\n                portRESET_PRIVILEGE();\n                portMEMORY_BARRIER();\n            }\n            else\n            {\n                xReturn = xQueueCreateCountingSemaphoreStatic( uxMaxCount, uxInitialCount, pxStaticQueue );\n            }\n\n            return xReturn;\n        }\n    #endif /* if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) */\n/*-----------------------------------------------------------*/\n\n    #if ( configUSE_RECURSIVE_MUTEXES == 1 )\n        BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,\n                                                 TickType_t xBlockTime ) /* FREERTOS_SYSTEM_CALL */\n        {\n            BaseType_t xReturn;\n\n            if( portIS_PRIVILEGED() == pdFALSE )\n            {\n                portRAISE_PRIVILEGE();\n                portMEMORY_BARRIER();\n\n                xReturn = xQueueTakeMutexRecursive( xMutex, xBlockTime );\n                portMEMORY_BARRIER();\n\n                portRESET_PRIVILEGE();\n                portMEMORY_BARRIER();\n            }\n            else\n            {\n                xReturn = xQueueTakeMutexRecursive( xMutex, xBlockTime );\n            }\n\n            return xReturn;\n        }\n    #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */\n/*-----------------------------------------------------------*/\n\n    #if ( configUSE_RECURSIVE_MUTEXES == 1 )\n        BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t xMutex ) /* FREERTOS_SYSTEM_CALL */\n        {\n            BaseType_t xReturn;\n\n            if( portIS_PRIVILEGED() == pdFALSE )\n            {\n                portRAISE_PRIVILEGE();\n                portMEMORY_BARRIER();\n\n                xReturn = xQueueGiveMutexRecursive( xMutex );\n                portMEMORY_BARRIER();\n\n                portRESET_PRIVILEGE();\n                portMEMORY_BARRIER();\n            }\n            else\n            {\n                xReturn = xQueueGiveMutexRecursive( xMutex );\n            }\n\n            return xReturn;\n        }\n    #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */\n/*-----------------------------------------------------------*/\n\n    #if ( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )\n        QueueSetHandle_t MPU_xQueueCreateSet( UBaseType_t uxEventQueueLength ) /* FREERTOS_SYSTEM_CALL */\n        {\n            QueueSetHandle_t xReturn;\n\n            if( portIS_PRIVILEGED() == pdFALSE )\n            {\n                portRAISE_PRIVILEGE();\n                portMEMORY_BARRIER();\n\n                xReturn = xQueueCreateSet( uxEventQueueLength );\n                portMEMORY_BARRIER();\n\n                portRESET_PRIVILEGE();\n                portMEMORY_BARRIER();\n            }\n            else\n            {\n                xReturn = xQueueCreateSet( uxEventQueueLength );\n            }\n\n            return xReturn;\n        }\n    #endif /* if ( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */\n/*-----------------------------------------------------------*/\n\n    #if ( configUSE_QUEUE_SETS == 1 )\n        QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,\n                                                        TickType_t xBlockTimeTicks ) /* FREERTOS_SYSTEM_CALL */\n        {\n            QueueSetMemberHandle_t xReturn;\n\n            if( portIS_PRIVILEGED() == pdFALSE )\n            {\n                portRAISE_PRIVILEGE();\n                portMEMORY_BARRIER();\n\n                xReturn = xQueueSelectFromSet( xQueueSet, xBlockTimeTicks );\n                portMEMORY_BARRIER();\n\n                portRESET_PRIVILEGE();\n                portMEMORY_BARRIER();\n            }\n            else\n            {\n                xReturn = xQueueSelectFromSet( xQueueSet, xBlockTimeTicks );\n            }\n\n            return xReturn;\n        }\n    #endif /* if ( configUSE_QUEUE_SETS == 1 ) */\n/*-----------------------------------------------------------*/\n\n    #if ( configUSE_QUEUE_SETS == 1 )\n        BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,\n                                       QueueSetHandle_t xQueueSet ) /* FREERTOS_SYSTEM_CALL */\n        {\n            BaseType_t xReturn;\n\n            if( portIS_PRIVILEGED() == pdFALSE )\n            {\n                portRAISE_PRIVILEGE();\n                portMEMORY_BARRIER();\n\n                xReturn = xQueueAddToSet( xQueueOrSemaphore, xQueueSet );\n                portMEMORY_BARRIER();\n\n                portRESET_PRIVILEGE();\n                portMEMORY_BARRIER();\n            }\n            else\n            {\n                xReturn = xQueueAddToSet( xQueueOrSemaphore, xQueueSet );\n            }\n\n            return xReturn;\n        }\n    #endif /* if ( configUSE_QUEUE_SETS == 1 ) */\n/*-----------------------------------------------------------*/\n\n    #if ( configUSE_QUEUE_SETS == 1 )\n        BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore,\n                                            QueueSetHandle_t xQueueSet ) /* FREERTOS_SYSTEM_CALL */\n        {\n            BaseType_t xReturn;\n\n            if( portIS_PRIVILEGED() == pdFALSE )\n            {\n                portRAISE_PRIVILEGE();\n                portMEMORY_BARRIER();\n\n                xReturn = xQueueRemoveFromSet( xQueueOrSemaphore, xQueueSet );\n                portMEMORY_BARRIER();\n\n                portRESET_PRIVILEGE();\n                portMEMORY_BARRIER();\n            }\n            else\n            {\n                xReturn = xQueueRemoveFromSet( xQueueOrSemaphore, xQueueSet );\n            }\n\n            return xReturn;\n        }\n    #endif /* if ( configUSE_QUEUE_SETS == 1 ) */\n/*-----------------------------------------------------------*/\n\n    #if configQUEUE_REGISTRY_SIZE > 0\n        void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,\n                                      const char * pcName ) /* FREERTOS_SYSTEM_CALL */\n        {\n            if( portIS_PRIVILEGED() == pdFALSE )\n            {\n                portRAISE_PRIVILEGE();\n                portMEMORY_BARRIER();\n\n                vQueueAddToRegistry( xQueue, pcName );\n                portMEMORY_BARRIER();\n\n                portRESET_PRIVILEGE();\n                portMEMORY_BARRIER();\n            }\n            else\n            {\n                vQueueAddToRegistry( xQueue, pcName );\n            }\n        }\n    #endif /* if configQUEUE_REGISTRY_SIZE > 0 */\n/*-----------------------------------------------------------*/\n\n    #if configQUEUE_REGISTRY_SIZE > 0\n        void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */\n        {\n            if( portIS_PRIVILEGED() == pdFALSE )\n            {\n                portRAISE_PRIVILEGE();\n                portMEMORY_BARRIER();\n\n                vQueueUnregisterQueue( xQueue );\n                portMEMORY_BARRIER();\n\n                portRESET_PRIVILEGE();\n                portMEMORY_BARRIER();\n            }\n            else\n            {\n                vQueueUnregisterQueue( xQueue );\n            }\n        }\n    #endif /* if configQUEUE_REGISTRY_SIZE > 0 */\n/*-----------------------------------------------------------*/\n\n    #if configQUEUE_REGISTRY_SIZE > 0\n        const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */\n        {\n            const char * pcReturn;\n\n            if( portIS_PRIVILEGED() == pdFALSE )\n            {\n                portRAISE_PRIVILEGE();\n                portMEMORY_BARRIER();\n\n                pcReturn = pcQueueGetName( xQueue );\n                portMEMORY_BARRIER();\n\n                portRESET_PRIVILEGE();\n                portMEMORY_BARRIER();\n            }\n            else\n            {\n                pcReturn = pcQueueGetName( xQueue );\n            }\n\n            return pcReturn;\n        }\n    #endif /* if configQUEUE_REGISTRY_SIZE > 0 */\n/*-----------------------------------------------------------*/\n\n    void MPU_vQueueDelete( QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */\n    {\n        if( portIS_PRIVILEGED() == pdFALSE )\n        {\n            portRAISE_PRIVILEGE();\n            portMEMORY_BARRIER();\n\n            vQueueDelete( xQueue );\n            portMEMORY_BARRIER();\n\n            portRESET_PRIVILEGE();\n            portMEMORY_BARRIER();\n        }\n        else\n        {\n            vQueueDelete( xQueue );\n        }\n    }\n/*-----------------------------------------------------------*/\n\n    #if ( configUSE_TIMERS == 1 )\n        void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */\n        {\n            void * pvReturn;\n\n            if( portIS_PRIVILEGED() == pdFALSE )\n            {\n                portRAISE_PRIVILEGE();\n                portMEMORY_BARRIER();\n\n                pvReturn = pvTimerGetTimerID( xTimer );\n                portMEMORY_BARRIER();\n\n                portRESET_PRIVILEGE();\n                portMEMORY_BARRIER();\n            }\n            else\n            {\n                pvReturn = pvTimerGetTimerID( xTimer );\n            }\n\n            return pvReturn;\n        }\n    #endif /* if ( configUSE_TIMERS == 1 ) */\n/*-----------------------------------------------------------*/\n\n    #if ( configUSE_TIMERS == 1 )\n        void MPU_vTimerSetTimerID( TimerHandle_t xTimer,\n                                   void * pvNewID ) /* FREERTOS_SYSTEM_CALL */\n        {\n            if( portIS_PRIVILEGED() == pdFALSE )\n            {\n                portRAISE_PRIVILEGE();\n                portMEMORY_BARRIER();\n\n                vTimerSetTimerID( xTimer, pvNewID );\n                portMEMORY_BARRIER();\n\n                portRESET_PRIVILEGE();\n                portMEMORY_BARRIER();\n            }\n            else\n            {\n                vTimerSetTimerID( xTimer, pvNewID );\n            }\n        }\n    #endif /* if ( configUSE_TIMERS == 1 ) */\n/*-----------------------------------------------------------*/\n\n    #if ( configUSE_TIMERS == 1 )\n        BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */\n        {\n            BaseType_t xReturn;\n\n            if( portIS_PRIVILEGED() == pdFALSE )\n            {\n                portRAISE_PRIVILEGE();\n                portMEMORY_BARRIER();\n\n                xReturn = xTimerIsTimerActive( xTimer );\n                portMEMORY_BARRIER();\n\n                portRESET_PRIVILEGE();\n                portMEMORY_BARRIER();\n            }\n            else\n            {\n                xReturn = xTimerIsTimerActive( xTimer );\n            }\n\n            return xReturn;\n        }\n    #endif /* if ( configUSE_TIMERS == 1 ) */\n/*-----------------------------------------------------------*/\n\n    #if ( configUSE_TIMERS == 1 )\n        TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* FREERTOS_SYSTEM_CALL */\n        {\n            TaskHandle_t xReturn;\n\n            if( portIS_PRIVILEGED() == pdFALSE )\n            {\n                portRAISE_PRIVILEGE();\n                portMEMORY_BARRIER();\n\n                xReturn = xTimerGetTimerDaemonTaskHandle();\n                portMEMORY_BARRIER();\n\n                portRESET_PRIVILEGE();\n                portMEMORY_BARRIER();\n            }\n            else\n            {\n                xReturn = xTimerGetTimerDaemonTaskHandle();\n            }\n\n            return xReturn;\n        }\n    #endif /* if ( configUSE_TIMERS == 1 ) */\n/*-----------------------------------------------------------*/\n\n    #if ( configUSE_TIMERS == 1 )\n        void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,\n                                      const UBaseType_t uxAutoReload ) /* FREERTOS_SYSTEM_CALL */\n        {\n            if( portIS_PRIVILEGED() == pdFALSE )\n            {\n                portRAISE_PRIVILEGE();\n                portMEMORY_BARRIER();\n\n                vTimerSetReloadMode( xTimer, uxAutoReload );\n                portMEMORY_BARRIER();\n\n                portRESET_PRIVILEGE();\n                portMEMORY_BARRIER();\n            }\n            else\n            {\n                vTimerSetReloadMode( xTimer, uxAutoReload );\n            }\n        }\n    #endif /* if ( configUSE_TIMERS == 1 ) */\n/*-----------------------------------------------------------*/\n\n    #if ( configUSE_TIMERS == 1 )\n        UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer )\n        {\n            UBaseType_t uxReturn;\n\n            if( portIS_PRIVILEGED() == pdFALSE )\n            {\n                portRAISE_PRIVILEGE();\n                portMEMORY_BARRIER();\n\n                uxReturn = uxTimerGetReloadMode( xTimer );\n                portMEMORY_BARRIER();\n\n                portRESET_PRIVILEGE();\n                portMEMORY_BARRIER();\n            }\n            else\n            {\n                uxReturn = uxTimerGetReloadMode( xTimer );\n            }\n\n            return uxReturn;\n        }\n    #endif /* if ( configUSE_TIMERS == 1 ) */\n/*-----------------------------------------------------------*/\n\n    #if ( configUSE_TIMERS == 1 )\n        const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */\n        {\n            const char * pcReturn;\n\n            if( portIS_PRIVILEGED() == pdFALSE )\n            {\n                portRAISE_PRIVILEGE();\n                portMEMORY_BARRIER();\n\n                pcReturn = pcTimerGetName( xTimer );\n                portMEMORY_BARRIER();\n\n                portRESET_PRIVILEGE();\n                portMEMORY_BARRIER();\n            }\n            else\n            {\n                pcReturn = pcTimerGetName( xTimer );\n            }\n\n            return pcReturn;\n        }\n    #endif /* if ( configUSE_TIMERS == 1 ) */\n/*-----------------------------------------------------------*/\n\n    #if ( configUSE_TIMERS == 1 )\n        TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */\n        {\n            TickType_t xReturn;\n\n            if( portIS_PRIVILEGED() == pdFALSE )\n            {\n                portRAISE_PRIVILEGE();\n                portMEMORY_BARRIER();\n\n                xReturn = xTimerGetPeriod( xTimer );\n                portMEMORY_BARRIER();\n\n                portRESET_PRIVILEGE();\n                portMEMORY_BARRIER();\n            }\n            else\n            {\n                xReturn = xTimerGetPeriod( xTimer );\n            }\n\n            return xReturn;\n        }\n    #endif /* if ( configUSE_TIMERS == 1 ) */\n/*-----------------------------------------------------------*/\n\n    #if ( configUSE_TIMERS == 1 )\n        TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */\n        {\n            TickType_t xReturn;\n\n            if( portIS_PRIVILEGED() == pdFALSE )\n            {\n                portRAISE_PRIVILEGE();\n                portMEMORY_BARRIER();\n\n                xReturn = xTimerGetExpiryTime( xTimer );\n                portMEMORY_BARRIER();\n\n                portRESET_PRIVILEGE();\n                portMEMORY_BARRIER();\n            }\n            else\n            {\n                xReturn = xTimerGetExpiryTime( xTimer );\n            }\n\n            return xReturn;\n        }\n    #endif /* if ( configUSE_TIMERS == 1 ) */\n/*-----------------------------------------------------------*/\n\n    #if ( configUSE_TIMERS == 1 )\n        BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer,\n                                             const BaseType_t xCommandID,\n                                             const TickType_t xOptionalValue,\n                                             BaseType_t * const pxHigherPriorityTaskWoken,\n                                             const TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */\n        {\n            BaseType_t xReturn;\n\n            if( portIS_PRIVILEGED() == pdFALSE )\n            {\n                portRAISE_PRIVILEGE();\n                portMEMORY_BARRIER();\n\n                xReturn = xTimerGenericCommand( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait );\n                portMEMORY_BARRIER();\n\n                portRESET_PRIVILEGE();\n                portMEMORY_BARRIER();\n            }\n            else\n            {\n                xReturn = xTimerGenericCommand( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait );\n            }\n\n            return xReturn;\n        }\n    #endif /* if ( configUSE_TIMERS == 1 ) */\n/*-----------------------------------------------------------*/\n\n    #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n        EventGroupHandle_t MPU_xEventGroupCreate( void ) /* FREERTOS_SYSTEM_CALL */\n        {\n            EventGroupHandle_t xReturn;\n\n            if( portIS_PRIVILEGED() == pdFALSE )\n            {\n                portRAISE_PRIVILEGE();\n                portMEMORY_BARRIER();\n\n                xReturn = xEventGroupCreate();\n                portMEMORY_BARRIER();\n\n                portRESET_PRIVILEGE();\n                portMEMORY_BARRIER();\n            }\n            else\n            {\n                xReturn = xEventGroupCreate();\n            }\n\n            return xReturn;\n        }\n    #endif /* if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) */\n/*-----------------------------------------------------------*/\n\n    #if ( configSUPPORT_STATIC_ALLOCATION == 1 )\n        EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t * pxEventGroupBuffer ) /* FREERTOS_SYSTEM_CALL */\n        {\n            EventGroupHandle_t xReturn;\n\n            if( portIS_PRIVILEGED() == pdFALSE )\n            {\n                portRAISE_PRIVILEGE();\n                portMEMORY_BARRIER();\n\n                xReturn = xEventGroupCreateStatic( pxEventGroupBuffer );\n                portMEMORY_BARRIER();\n\n                portRESET_PRIVILEGE();\n                portMEMORY_BARRIER();\n            }\n            else\n            {\n                xReturn = xEventGroupCreateStatic( pxEventGroupBuffer );\n            }\n\n            return xReturn;\n        }\n    #endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */\n/*-----------------------------------------------------------*/\n\n    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,\n                                         const EventBits_t uxBitsToWaitFor,\n                                         const BaseType_t xClearOnExit,\n                                         const BaseType_t xWaitForAllBits,\n                                         TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */\n    {\n        EventBits_t xReturn;\n\n        if( portIS_PRIVILEGED() == pdFALSE )\n        {\n            portRAISE_PRIVILEGE();\n            portMEMORY_BARRIER();\n\n            xReturn = xEventGroupWaitBits( xEventGroup, uxBitsToWaitFor, xClearOnExit, xWaitForAllBits, xTicksToWait );\n            portMEMORY_BARRIER();\n\n            portRESET_PRIVILEGE();\n            portMEMORY_BARRIER();\n        }\n        else\n        {\n            xReturn = xEventGroupWaitBits( xEventGroup, uxBitsToWaitFor, xClearOnExit, xWaitForAllBits, xTicksToWait );\n        }\n\n        return xReturn;\n    }\n/*-----------------------------------------------------------*/\n\n    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,\n                                          const EventBits_t uxBitsToClear ) /* FREERTOS_SYSTEM_CALL */\n    {\n        EventBits_t xReturn;\n\n        if( portIS_PRIVILEGED() == pdFALSE )\n        {\n            portRAISE_PRIVILEGE();\n            portMEMORY_BARRIER();\n\n            xReturn = xEventGroupClearBits( xEventGroup, uxBitsToClear );\n            portMEMORY_BARRIER();\n\n            portRESET_PRIVILEGE();\n            portMEMORY_BARRIER();\n        }\n        else\n        {\n            xReturn = xEventGroupClearBits( xEventGroup, uxBitsToClear );\n        }\n\n        return xReturn;\n    }\n/*-----------------------------------------------------------*/\n\n    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,\n                                        const EventBits_t uxBitsToSet ) /* FREERTOS_SYSTEM_CALL */\n    {\n        EventBits_t xReturn;\n\n        if( portIS_PRIVILEGED() == pdFALSE )\n        {\n            portRAISE_PRIVILEGE();\n            portMEMORY_BARRIER();\n\n            xReturn = xEventGroupSetBits( xEventGroup, uxBitsToSet );\n            portMEMORY_BARRIER();\n\n            portRESET_PRIVILEGE();\n            portMEMORY_BARRIER();\n        }\n        else\n        {\n            xReturn = xEventGroupSetBits( xEventGroup, uxBitsToSet );\n        }\n\n        return xReturn;\n    }\n/*-----------------------------------------------------------*/\n\n    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,\n                                     const EventBits_t uxBitsToSet,\n                                     const EventBits_t uxBitsToWaitFor,\n                                     TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */\n    {\n        EventBits_t xReturn;\n\n        if( portIS_PRIVILEGED() == pdFALSE )\n        {\n            portRAISE_PRIVILEGE();\n            portMEMORY_BARRIER();\n\n            xReturn = xEventGroupSync( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTicksToWait );\n            portMEMORY_BARRIER();\n\n            portRESET_PRIVILEGE();\n            portMEMORY_BARRIER();\n        }\n        else\n        {\n            xReturn = xEventGroupSync( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTicksToWait );\n        }\n\n        return xReturn;\n    }\n/*-----------------------------------------------------------*/\n\n    void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) /* FREERTOS_SYSTEM_CALL */\n    {\n        if( portIS_PRIVILEGED() == pdFALSE )\n        {\n            portRAISE_PRIVILEGE();\n            portMEMORY_BARRIER();\n\n            vEventGroupDelete( xEventGroup );\n            portMEMORY_BARRIER();\n\n            portRESET_PRIVILEGE();\n            portMEMORY_BARRIER();\n        }\n        else\n        {\n            vEventGroupDelete( xEventGroup );\n        }\n    }\n/*-----------------------------------------------------------*/\n\n    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,\n                                  const void * pvTxData,\n                                  size_t xDataLengthBytes,\n                                  TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */\n    {\n        size_t xReturn;\n\n        if( portIS_PRIVILEGED() == pdFALSE )\n        {\n            portRAISE_PRIVILEGE();\n            portMEMORY_BARRIER();\n\n            xReturn = xStreamBufferSend( xStreamBuffer, pvTxData, xDataLengthBytes, xTicksToWait );\n            portMEMORY_BARRIER();\n\n            portRESET_PRIVILEGE();\n            portMEMORY_BARRIER();\n        }\n        else\n        {\n            xReturn = xStreamBufferSend( xStreamBuffer, pvTxData, xDataLengthBytes, xTicksToWait );\n        }\n\n        return xReturn;\n    }\n/*-----------------------------------------------------------*/\n\n    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */\n    {\n        size_t xReturn;\n\n        if( portIS_PRIVILEGED() == pdFALSE )\n        {\n            portRAISE_PRIVILEGE();\n            portMEMORY_BARRIER();\n\n            xReturn = xStreamBufferNextMessageLengthBytes( xStreamBuffer );\n            portMEMORY_BARRIER();\n\n            portRESET_PRIVILEGE();\n            portMEMORY_BARRIER();\n        }\n        else\n        {\n            xReturn = xStreamBufferNextMessageLengthBytes( xStreamBuffer );\n        }\n\n        return xReturn;\n    }\n/*-----------------------------------------------------------*/\n\n    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,\n                                     void * pvRxData,\n                                     size_t xBufferLengthBytes,\n                                     TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */\n    {\n        size_t xReturn;\n\n        if( portIS_PRIVILEGED() == pdFALSE )\n        {\n            portRAISE_PRIVILEGE();\n            portMEMORY_BARRIER();\n\n            xReturn = xStreamBufferReceive( xStreamBuffer, pvRxData, xBufferLengthBytes, xTicksToWait );\n            portMEMORY_BARRIER();\n\n            portRESET_PRIVILEGE();\n            portMEMORY_BARRIER();\n        }\n        else\n        {\n            xReturn = xStreamBufferReceive( xStreamBuffer, pvRxData, xBufferLengthBytes, xTicksToWait );\n        }\n\n        return xReturn;\n    }\n/*-----------------------------------------------------------*/\n\n    void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */\n    {\n        if( portIS_PRIVILEGED() == pdFALSE )\n        {\n            portRAISE_PRIVILEGE();\n            portMEMORY_BARRIER();\n\n            vStreamBufferDelete( xStreamBuffer );\n            portMEMORY_BARRIER();\n\n            portRESET_PRIVILEGE();\n            portMEMORY_BARRIER();\n        }\n        else\n        {\n            vStreamBufferDelete( xStreamBuffer );\n        }\n    }\n/*-----------------------------------------------------------*/\n\n    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */\n    {\n        BaseType_t xReturn;\n\n        if( portIS_PRIVILEGED() == pdFALSE )\n        {\n            portRAISE_PRIVILEGE();\n            portMEMORY_BARRIER();\n\n            xReturn = xStreamBufferIsFull( xStreamBuffer );\n            portMEMORY_BARRIER();\n\n            portRESET_PRIVILEGE();\n            portMEMORY_BARRIER();\n        }\n        else\n        {\n            xReturn = xStreamBufferIsFull( xStreamBuffer );\n        }\n\n        return xReturn;\n    }\n/*-----------------------------------------------------------*/\n\n    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */\n    {\n        BaseType_t xReturn;\n\n        if( portIS_PRIVILEGED() == pdFALSE )\n        {\n            portRAISE_PRIVILEGE();\n            portMEMORY_BARRIER();\n\n            xReturn = xStreamBufferIsEmpty( xStreamBuffer );\n            portMEMORY_BARRIER();\n\n            portRESET_PRIVILEGE();\n            portMEMORY_BARRIER();\n        }\n        else\n        {\n            xReturn = xStreamBufferIsEmpty( xStreamBuffer );\n        }\n\n        return xReturn;\n    }\n/*-----------------------------------------------------------*/\n\n    BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */\n    {\n        BaseType_t xReturn;\n\n        if( portIS_PRIVILEGED() == pdFALSE )\n        {\n            portRAISE_PRIVILEGE();\n            portMEMORY_BARRIER();\n\n            xReturn = xStreamBufferReset( xStreamBuffer );\n            portMEMORY_BARRIER();\n\n            portRESET_PRIVILEGE();\n            portMEMORY_BARRIER();\n        }\n        else\n        {\n            xReturn = xStreamBufferReset( xStreamBuffer );\n        }\n\n        return xReturn;\n    }\n/*-----------------------------------------------------------*/\n\n    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */\n    {\n        size_t xReturn;\n\n        if( portIS_PRIVILEGED() == pdFALSE )\n        {\n            portRAISE_PRIVILEGE();\n            portMEMORY_BARRIER();\n            xReturn = xStreamBufferSpacesAvailable( xStreamBuffer );\n            portMEMORY_BARRIER();\n\n            portRESET_PRIVILEGE();\n            portMEMORY_BARRIER();\n        }\n        else\n        {\n            xReturn = xStreamBufferSpacesAvailable( xStreamBuffer );\n        }\n\n        return xReturn;\n    }\n/*-----------------------------------------------------------*/\n\n    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */\n    {\n        size_t xReturn;\n\n        if( portIS_PRIVILEGED() == pdFALSE )\n        {\n            portRAISE_PRIVILEGE();\n            portMEMORY_BARRIER();\n\n            xReturn = xStreamBufferBytesAvailable( xStreamBuffer );\n            portMEMORY_BARRIER();\n\n            portRESET_PRIVILEGE();\n            portMEMORY_BARRIER();\n        }\n        else\n        {\n            xReturn = xStreamBufferBytesAvailable( xStreamBuffer );\n        }\n\n        return xReturn;\n    }\n/*-----------------------------------------------------------*/\n\n    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,\n                                                 size_t xTriggerLevel ) /* FREERTOS_SYSTEM_CALL */\n    {\n        BaseType_t xReturn;\n\n        if( portIS_PRIVILEGED() == pdFALSE )\n        {\n            portRAISE_PRIVILEGE();\n            portMEMORY_BARRIER();\n\n            xReturn = xStreamBufferSetTriggerLevel( xStreamBuffer, xTriggerLevel );\n            portMEMORY_BARRIER();\n\n            portRESET_PRIVILEGE();\n            portMEMORY_BARRIER();\n        }\n        else\n        {\n            xReturn = xStreamBufferSetTriggerLevel( xStreamBuffer, xTriggerLevel );\n        }\n\n        return xReturn;\n    }\n/*-----------------------------------------------------------*/\n\n    #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n        StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes,\n                                                             size_t xTriggerLevelBytes,\n                                                             BaseType_t xIsMessageBuffer,\n                                                             StreamBufferCallbackFunction_t pxSendCompletedCallback,\n                                                             StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) /* FREERTOS_SYSTEM_CALL */\n        {\n            StreamBufferHandle_t xReturn;\n\n            /**\n             * Streambuffer application level callback functionality is disabled for MPU\n             * enabled ports.\n             */\n            configASSERT( ( pxSendCompletedCallback == NULL ) &&\n                          ( pxReceiveCompletedCallback == NULL ) );\n\n            if( ( pxSendCompletedCallback == NULL ) &&\n                ( pxReceiveCompletedCallback == NULL ) )\n            {\n                if( portIS_PRIVILEGED() == pdFALSE )\n                {\n                    portRAISE_PRIVILEGE();\n                    portMEMORY_BARRIER();\n\n                    xReturn = xStreamBufferGenericCreate( xBufferSizeBytes,\n                                                          xTriggerLevelBytes,\n                                                          xIsMessageBuffer,\n                                                          NULL,\n                                                          NULL );\n                    portMEMORY_BARRIER();\n\n                    portRESET_PRIVILEGE();\n                    portMEMORY_BARRIER();\n                }\n                else\n                {\n                    xReturn = xStreamBufferGenericCreate( xBufferSizeBytes,\n                                                          xTriggerLevelBytes,\n                                                          xIsMessageBuffer,\n                                                          NULL,\n                                                          NULL );\n                }\n            }\n            else\n            {\n                traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer );\n                xReturn = NULL;\n            }\n\n            return xReturn;\n        }\n    #endif /* configSUPPORT_DYNAMIC_ALLOCATION */\n/*-----------------------------------------------------------*/\n\n    #if ( configSUPPORT_STATIC_ALLOCATION == 1 )\n        StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,\n                                                                   size_t xTriggerLevelBytes,\n                                                                   BaseType_t xIsMessageBuffer,\n                                                                   uint8_t * const pucStreamBufferStorageArea,\n                                                                   StaticStreamBuffer_t * const pxStaticStreamBuffer,\n                                                                   StreamBufferCallbackFunction_t pxSendCompletedCallback,\n                                                                   StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) /* FREERTOS_SYSTEM_CALL */\n        {\n            StreamBufferHandle_t xReturn;\n\n            /**\n             * Streambuffer application level callback functionality is disabled for MPU\n             * enabled ports.\n             */\n            configASSERT( ( pxSendCompletedCallback == NULL ) &&\n                          ( pxReceiveCompletedCallback == NULL ) );\n\n            if( ( pxSendCompletedCallback == NULL ) &&\n                ( pxReceiveCompletedCallback == NULL ) )\n            {\n                if( portIS_PRIVILEGED() == pdFALSE )\n                {\n                    portRAISE_PRIVILEGE();\n                    portMEMORY_BARRIER();\n\n                    xReturn = xStreamBufferGenericCreateStatic( xBufferSizeBytes,\n                                                                xTriggerLevelBytes,\n                                                                xIsMessageBuffer,\n                                                                pucStreamBufferStorageArea,\n                                                                pxStaticStreamBuffer,\n                                                                NULL,\n                                                                NULL );\n                    portMEMORY_BARRIER();\n\n                    portRESET_PRIVILEGE();\n                    portMEMORY_BARRIER();\n                }\n                else\n                {\n                    xReturn = xStreamBufferGenericCreateStatic( xBufferSizeBytes,\n                                                                xTriggerLevelBytes,\n                                                                xIsMessageBuffer,\n                                                                pucStreamBufferStorageArea,\n                                                                pxStaticStreamBuffer,\n                                                                NULL,\n                                                                NULL );\n                }\n            }\n            else\n            {\n                traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer );\n                xReturn = NULL;\n            }\n\n            return xReturn;\n        }\n    #endif /* configSUPPORT_STATIC_ALLOCATION */\n/*-----------------------------------------------------------*/\n\n\n/* Functions that the application writer wants to execute in privileged mode\n * can be defined in application_defined_privileged_functions.h.  The functions\n * must take the same format as those above whereby the privilege state on exit\n * equals the privilege state on entry.  For example:\n *\n * void MPU_FunctionName( [parameters ] ) FREERTOS_SYSTEM_CALL;\n * void MPU_FunctionName( [parameters ] )\n * {\n *      if( portIS_PRIVILEGED() == pdFALSE )\n *      {\n *          portRAISE_PRIVILEGE();\n *          portMEMORY_BARRIER();\n *\n *          FunctionName( [parameters ] );\n *          portMEMORY_BARRIER();\n *\n *          portRESET_PRIVILEGE();\n *          portMEMORY_BARRIER();\n *      }\n *      else\n *      {\n *          FunctionName( [parameters ] );\n *      }\n * }\n */\n\n    #if configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS == 1\n        #include \"application_defined_privileged_functions.h\"\n    #endif\n/*-----------------------------------------------------------*/\n\n#endif /* portUSING_MPU_WRAPPERS == 1 */\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CA53_64_BIT/port.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Standard includes. */\n#include <stdlib.h>\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n#ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS\n\t#error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html\n#endif\n\n#ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET\n\t#error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html\n#endif\n\n#ifndef configUNIQUE_INTERRUPT_PRIORITIES\n\t#error configUNIQUE_INTERRUPT_PRIORITIES must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html\n#endif\n\n#ifndef configSETUP_TICK_INTERRUPT\n\t#error configSETUP_TICK_INTERRUPT() must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html\n#endif /* configSETUP_TICK_INTERRUPT */\n\n#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY\n\t#error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html\n#endif\n\n#if configMAX_API_CALL_INTERRUPT_PRIORITY == 0\n\t#error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0\n#endif\n\n#if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES\n\t#error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority\n#endif\n\n#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1\n\t/* Check the configuration. */\n\t#if( configMAX_PRIORITIES > 32 )\n\t\t#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.\n\t#endif\n#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */\n\n/* In case security extensions are implemented. */\n#if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )\n\t#error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )\n#endif\n\n/* Some vendor specific files default configCLEAR_TICK_INTERRUPT() in\nportmacro.h. */\n#ifndef configCLEAR_TICK_INTERRUPT\n\t#define configCLEAR_TICK_INTERRUPT()\n#endif\n\n/* A critical section is exited when the critical section nesting count reaches\nthis value. */\n#define portNO_CRITICAL_NESTING\t\t\t( ( size_t ) 0 )\n\n/* In all GICs 255 can be written to the priority mask register to unmask all\n(but the lowest) interrupt priority. */\n#define portUNMASK_VALUE\t\t\t\t( 0xFFUL )\n\n/* Tasks are not created with a floating point context, but can be given a\nfloating point context after they have been created.  A variable is stored as\npart of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task\ndoes not have an FPU context, or any other value if the task does have an FPU\ncontext. */\n#define portNO_FLOATING_POINT_CONTEXT\t( ( StackType_t ) 0 )\n\n/* Constants required to setup the initial task context. */\n#define portSP_ELx\t\t\t\t\t\t( ( StackType_t ) 0x01 )\n#define portSP_EL0\t\t\t\t\t\t( ( StackType_t ) 0x00 )\n\n#if defined( GUEST )\n\t#define portEL1\t\t\t\t\t\t( ( StackType_t ) 0x04 )\n\t#define portINITIAL_PSTATE\t\t\t\t( portEL1 | portSP_EL0 )\n#else\n\t#define portEL3\t\t\t\t\t\t( ( StackType_t ) 0x0c )\n\t/* At the time of writing, the BSP only supports EL3. */\n\t#define portINITIAL_PSTATE\t\t\t( portEL3 | portSP_EL0 )\n#endif\n\n\n/* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary\npoint is zero. */\n#define portBINARY_POINT_BITS\t\t\t( ( uint8_t ) 0x03 )\n\n/* Masks all bits in the APSR other than the mode bits. */\n#define portAPSR_MODE_BITS_MASK\t\t\t( 0x0C )\n\n/* The I bit in the DAIF bits. */\n#define portDAIF_I\t\t\t\t\t\t( 0x80 )\n\n/* Macro to unmask all interrupt priorities. */\n#define portCLEAR_INTERRUPT_MASK()\t\t\t\t\t\t\t\t\t\\\n{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tportDISABLE_INTERRUPTS();\t\t\t\t\t\t\t\t\t\t\\\n\tportICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE;\t\t\t\\\n\t__asm volatile (\t\"DSB SY\t\t\\n\"\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\"ISB SY\t\t\\n\" );\t\t\t\t\t\t\t\\\n\tportENABLE_INTERRUPTS();\t\t\t\t\t\t\t\t\t\t\\\n}\n\n/* Hardware specifics used when sanity checking the configuration. */\n#define portINTERRUPT_PRIORITY_REGISTER_OFFSET\t\t0x400UL\n#define portMAX_8_BIT_VALUE\t\t\t\t\t\t\t( ( uint8_t ) 0xff )\n#define portBIT_0_SET\t\t\t\t\t\t\t\t( ( uint8_t ) 0x01 )\n\n/*-----------------------------------------------------------*/\n\n/*\n * Starts the first task executing.  This function is necessarily written in\n * assembly code so is implemented in portASM.s.\n */\nextern void vPortRestoreTaskContext( void );\n\n/*-----------------------------------------------------------*/\n\n/* A variable is used to keep track of the critical section nesting.  This\nvariable has to be stored as part of the task context and must be initialised to\na non zero value to ensure interrupts don't inadvertently become unmasked before\nthe scheduler starts.  As it is stored as part of the task context it will\nautomatically be set to 0 when the first task is started. */\nvolatile uint64_t ullCriticalNesting = 9999ULL;\n\n/* Saved as part of the task context.  If ullPortTaskHasFPUContext is non-zero\nthen floating point context must be saved and restored for the task. */\nuint64_t ullPortTaskHasFPUContext = pdFALSE;\n\n/* Set to 1 to pend a context switch from an ISR. */\nuint64_t ullPortYieldRequired = pdFALSE;\n\n/* Counts the interrupt nesting depth.  A context switch is only performed if\nif the nesting depth is 0. */\nuint64_t ullPortInterruptNesting = 0;\n\n/* Used in the ASM code. */\n__attribute__(( used )) const uint64_t ullICCEOIR = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS;\n__attribute__(( used )) const uint64_t ullICCIAR = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS;\n__attribute__(( used )) const uint64_t ullICCPMR = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS;\n__attribute__(( used )) const uint64_t ullMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );\n\n/*-----------------------------------------------------------*/\n\n/*\n * See header file for description.\n */\nStackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )\n{\n\t/* Setup the initial stack of the task.  The stack is set exactly as\n\texpected by the portRESTORE_CONTEXT() macro. */\n\n\t/* First all the general purpose registers. */\n\tpxTopOfStack--;\n\t*pxTopOfStack = 0x0101010101010101ULL;\t/* R1 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = 0x0303030303030303ULL;\t/* R3 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = 0x0202020202020202ULL;\t/* R2 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = 0x0505050505050505ULL;\t/* R5 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = 0x0404040404040404ULL;\t/* R4 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = 0x0707070707070707ULL;\t/* R7 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = 0x0606060606060606ULL;\t/* R6 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = 0x0909090909090909ULL;\t/* R9 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = 0x0808080808080808ULL;\t/* R8 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = 0x1111111111111111ULL;\t/* R11 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = 0x1010101010101010ULL;\t/* R10 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = 0x1313131313131313ULL;\t/* R13 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = 0x1212121212121212ULL;\t/* R12 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = 0x1515151515151515ULL;\t/* R15 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = 0x1414141414141414ULL;\t/* R14 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = 0x1717171717171717ULL;\t/* R17 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = 0x1616161616161616ULL;\t/* R16 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = 0x1919191919191919ULL;\t/* R19 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = 0x1818181818181818ULL;\t/* R18 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = 0x2121212121212121ULL;\t/* R21 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = 0x2020202020202020ULL;\t/* R20 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = 0x2323232323232323ULL;\t/* R23 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = 0x2222222222222222ULL;\t/* R22 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = 0x2525252525252525ULL;\t/* R25 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = 0x2424242424242424ULL;\t/* R24 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = 0x2727272727272727ULL;\t/* R27 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = 0x2626262626262626ULL;\t/* R26 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = 0x2929292929292929ULL;\t/* R29 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = 0x2828282828282828ULL;\t/* R28 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x00;\t/* XZR - has no effect, used so there are an even number of registers. */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x00;\t/* R30 - procedure call link register. */\n\tpxTopOfStack--;\n\n\t*pxTopOfStack = portINITIAL_PSTATE;\n\tpxTopOfStack--;\n\n\t*pxTopOfStack = ( StackType_t ) pxCode; /* Exception return address. */\n\tpxTopOfStack--;\n\n\t/* The task will start with a critical nesting count of 0 as interrupts are\n\tenabled. */\n\t*pxTopOfStack = portNO_CRITICAL_NESTING;\n\tpxTopOfStack--;\n\n\t/* The task will start without a floating point context.  A task that uses\n\tthe floating point hardware must call vPortTaskUsesFPU() before executing\n\tany floating point instructions. */\n\t*pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;\n\n\treturn pxTopOfStack;\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xPortStartScheduler( void )\n{\nuint32_t ulAPSR;\n\n\t#if( configASSERT_DEFINED == 1 )\n\t{\n\t\tvolatile uint32_t ulOriginalPriority;\n\t\tvolatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + portINTERRUPT_PRIORITY_REGISTER_OFFSET );\n\t\tvolatile uint8_t ucMaxPriorityValue;\n\n\t\t/* Determine how many priority bits are implemented in the GIC.\n\n\t\tSave the interrupt priority value that is about to be clobbered. */\n\t\tulOriginalPriority = *pucFirstUserPriorityRegister;\n\n\t\t/* Determine the number of priority bits available.  First write to\n\t\tall possible bits. */\n\t\t*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\n\n\t\t/* Read the value back to see how many bits stuck. */\n\t\tucMaxPriorityValue = *pucFirstUserPriorityRegister;\n\n\t\t/* Shift to the least significant bits. */\n\t\twhile( ( ucMaxPriorityValue & portBIT_0_SET ) != portBIT_0_SET )\n\t\t{\n\t\t\tucMaxPriorityValue >>= ( uint8_t ) 0x01;\n\t\t}\n\n\t\t/* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read\n\t\tvalue. */\n\n\t\tconfigASSERT( ucMaxPriorityValue >= portLOWEST_INTERRUPT_PRIORITY );\n\n\n\t\t/* Restore the clobbered interrupt priority register to its original\n\t\tvalue. */\n\t\t*pucFirstUserPriorityRegister = ulOriginalPriority;\n\t}\n\t#endif /* configASSERT_DEFINED */\n\n\n\t/* At the time of writing, the BSP only supports EL3. */\n\t__asm volatile ( \"MRS %0, CurrentEL\" : \"=r\" ( ulAPSR ) );\n\tulAPSR &= portAPSR_MODE_BITS_MASK;\n\n#if defined( GUEST )\n\t#warning Building for execution as a guest under XEN. THIS IS NOT A FULLY TESTED PATH.\n\tconfigASSERT( ulAPSR == portEL1 );\n\tif( ulAPSR == portEL1 )\n#else\n\tconfigASSERT( ulAPSR == portEL3 );\n\tif( ulAPSR == portEL3 )\n#endif\n\t{\n\t\t/* Only continue if the binary point value is set to its lowest possible\n\t\tsetting.  See the comments in vPortValidateInterruptPriority() below for\n\t\tmore information. */\n\t\tconfigASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );\n\n\t\tif( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )\n\t\t{\n\t\t\t/* Interrupts are turned off in the CPU itself to ensure a tick does\n\t\t\tnot execute\twhile the scheduler is being started.  Interrupts are\n\t\t\tautomatically turned back on in the CPU when the first task starts\n\t\t\texecuting. */\n\t\t\tportDISABLE_INTERRUPTS();\n\n\t\t\t/* Start the timer that generates the tick ISR. */\n\t\t\tconfigSETUP_TICK_INTERRUPT();\n\n\t\t\t/* Start the first task executing. */\n\t\t\tvPortRestoreTaskContext();\n\t\t}\n\t}\n\n\treturn 0;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEndScheduler( void )\n{\n\t/* Not implemented in ports where there is nothing to return to.\n\tArtificially force an assert. */\n\tconfigASSERT( ullCriticalNesting == 1000ULL );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEnterCritical( void )\n{\n\t/* Mask interrupts up to the max syscall interrupt priority. */\n\tuxPortSetInterruptMask();\n\n\t/* Now interrupts are disabled ullCriticalNesting can be accessed\n\tdirectly.  Increment ullCriticalNesting to keep a count of how many times\n\tportENTER_CRITICAL() has been called. */\n\tullCriticalNesting++;\n\n\t/* This is not the interrupt safe version of the enter critical function so\n\tassert() if it is being called from an interrupt context.  Only API\n\tfunctions that end in \"FromISR\" can be used in an interrupt.  Only assert if\n\tthe critical nesting count is 1 to protect against recursive calls if the\n\tassert function also uses a critical section. */\n\tif( ullCriticalNesting == 1ULL )\n\t{\n\t\tconfigASSERT( ullPortInterruptNesting == 0 );\n\t}\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortExitCritical( void )\n{\n\tif( ullCriticalNesting > portNO_CRITICAL_NESTING )\n\t{\n\t\t/* Decrement the nesting count as the critical section is being\n\t\texited. */\n\t\tullCriticalNesting--;\n\n\t\t/* If the nesting level has reached zero then all interrupt\n\t\tpriorities must be re-enabled. */\n\t\tif( ullCriticalNesting == portNO_CRITICAL_NESTING )\n\t\t{\n\t\t\t/* Critical nesting has reached zero so all interrupt priorities\n\t\t\tshould be unmasked. */\n\t\t\tportCLEAR_INTERRUPT_MASK();\n\t\t}\n\t}\n}\n/*-----------------------------------------------------------*/\n\nvoid FreeRTOS_Tick_Handler( void )\n{\n\t/* Must be the lowest possible priority. */\n\t#if !defined( QEMU )\n\t{\n\t\tconfigASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER == ( uint32_t ) ( portLOWEST_USABLE_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );\n\t}\n\t#endif\n\n\t/* Interrupts should not be enabled before this point. */\n\t#if( configASSERT_DEFINED == 1 )\n\t{\n\t\tuint32_t ulMaskBits;\n\n\t\t__asm volatile( \"mrs %0, daif\" : \"=r\"( ulMaskBits ) :: \"memory\" );\n\t\tconfigASSERT( ( ulMaskBits & portDAIF_I ) != 0 );\n\t}\n\t#endif /* configASSERT_DEFINED */\n\n\t/* Set interrupt mask before altering scheduler structures.   The tick\n\thandler runs at the lowest priority, so interrupts cannot already be masked,\n\tso there is no need to save and restore the current mask value.  It is\n\tnecessary to turn off interrupts in the CPU itself while the ICCPMR is being\n\tupdated. */\n\tportICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );\n\t__asm volatile (\t\"dsb sy\t\t\\n\"\n\t\t\t\t\t\t\"isb sy\t\t\\n\" ::: \"memory\" );\n\n\t/* Ok to enable interrupts after the interrupt source has been cleared. */\n\tconfigCLEAR_TICK_INTERRUPT();\n\tportENABLE_INTERRUPTS();\n\n\t/* Increment the RTOS tick. */\n\tif( xTaskIncrementTick() != pdFALSE )\n\t{\n\t\tullPortYieldRequired = pdTRUE;\n\t}\n\n\t/* Ensure all interrupt priorities are active again. */\n\tportCLEAR_INTERRUPT_MASK();\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortTaskUsesFPU( void )\n{\n\t/* A task is registering the fact that it needs an FPU context.  Set the\n\tFPU flag (which is saved as part of the task context). */\n\tullPortTaskHasFPUContext = pdTRUE;\n\n\t/* Consider initialising the FPSR here - but probably not necessary in\n\tAArch64. */\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortClearInterruptMask( UBaseType_t uxNewMaskValue )\n{\n\tif( uxNewMaskValue == pdFALSE )\n\t{\n\t\tportCLEAR_INTERRUPT_MASK();\n\t}\n}\n/*-----------------------------------------------------------*/\n\nUBaseType_t uxPortSetInterruptMask( void )\n{\nuint32_t ulReturn;\n\n\t/* Interrupt in the CPU must be turned off while the ICCPMR is being\n\tupdated. */\n\tportDISABLE_INTERRUPTS();\n\tif( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )\n\t{\n\t\t/* Interrupts were already masked. */\n\t\tulReturn = pdTRUE;\n\t}\n\telse\n\t{\n\t\tulReturn = pdFALSE;\n\t\tportICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );\n\t\t__asm volatile (\t\"dsb sy\t\t\\n\"\n\t\t\t\t\t\t\t\"isb sy\t\t\\n\" ::: \"memory\" );\n\t}\n\tportENABLE_INTERRUPTS();\n\n\treturn ulReturn;\n}\n/*-----------------------------------------------------------*/\n\n#if( configASSERT_DEFINED == 1 )\n\n\tvoid vPortValidateInterruptPriority( void )\n\t{\n\t\t/* The following assertion will fail if a service routine (ISR) for\n\t\tan interrupt that has been assigned a priority above\n\t\tconfigMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\n\t\tfunction.  ISR safe FreeRTOS API functions must *only* be called\n\t\tfrom interrupts that have been assigned a priority at or below\n\t\tconfigMAX_SYSCALL_INTERRUPT_PRIORITY.\n\n\t\tNumerically low interrupt priority numbers represent logically high\n\t\tinterrupt priorities, therefore the priority of the interrupt must\n\t\tbe set to a value equal to or numerically *higher* than\n\t\tconfigMAX_SYSCALL_INTERRUPT_PRIORITY.\n\n\t\tFreeRTOS maintains separate thread and ISR API functions to ensure\n\t\tinterrupt entry is as fast and simple as possible. */\n\t\tconfigASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );\n\n\t\t/* Priority grouping:  The interrupt controller (GIC) allows the bits\n\t\tthat define each interrupt's priority to be split between bits that\n\t\tdefine the interrupt's pre-emption priority bits and bits that define\n\t\tthe interrupt's sub-priority.  For simplicity all bits must be defined\n\t\tto be pre-emption priority bits.  The following assertion will fail if\n\t\tthis is not the case (if some bits represent a sub-priority).\n\n\t\tThe priority grouping is configured by the GIC's binary point register\n\t\t(ICCBPR).  Writting 0 to ICCBPR will ensure it is set to its lowest\n\t\tpossible value (which may be above 0). */\n\t\tconfigASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );\n\t}\n\n#endif /* configASSERT_DEFINED */\n/*-----------------------------------------------------------*/\n\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CA53_64_BIT/portASM.S",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n\t.text\n\n\t/* Variables and functions. */\n\t.extern ullMaxAPIPriorityMask\n\t.extern pxCurrentTCB\n\t.extern vTaskSwitchContext\n\t.extern vApplicationIRQHandler\n\t.extern ullPortInterruptNesting\n\t.extern ullPortTaskHasFPUContext\n\t.extern ullCriticalNesting\n\t.extern ullPortYieldRequired\n\t.extern ullICCEOIR\n\t.extern ullICCIAR\n\t.extern _freertos_vector_table\n\n\t.global FreeRTOS_IRQ_Handler\n\t.global FreeRTOS_SWI_Handler\n\t.global vPortRestoreTaskContext\n\n\n.macro portSAVE_CONTEXT\n\n\t/* Switch to use the EL0 stack pointer. */\n\tMSR \tSPSEL, #0\n\n\t/* Save the entire context. */\n\tSTP \tX0, X1, [SP, #-0x10]!\n\tSTP \tX2, X3, [SP, #-0x10]!\n\tSTP \tX4, X5, [SP, #-0x10]!\n\tSTP \tX6, X7, [SP, #-0x10]!\n\tSTP \tX8, X9, [SP, #-0x10]!\n\tSTP \tX10, X11, [SP, #-0x10]!\n\tSTP \tX12, X13, [SP, #-0x10]!\n\tSTP \tX14, X15, [SP, #-0x10]!\n\tSTP \tX16, X17, [SP, #-0x10]!\n\tSTP \tX18, X19, [SP, #-0x10]!\n\tSTP \tX20, X21, [SP, #-0x10]!\n\tSTP \tX22, X23, [SP, #-0x10]!\n\tSTP \tX24, X25, [SP, #-0x10]!\n\tSTP \tX26, X27, [SP, #-0x10]!\n\tSTP \tX28, X29, [SP, #-0x10]!\n\tSTP \tX30, XZR, [SP, #-0x10]!\n\n\t/* Save the SPSR. */\n#if defined( GUEST )\n\tMRS\t\tX3, SPSR_EL1\n\tMRS\t\tX2, ELR_EL1\n#else\n\tMRS\t\tX3, SPSR_EL3\n\t/* Save the ELR. */\n\tMRS\t\tX2, ELR_EL3\n#endif\n\n\tSTP \tX2, X3, [SP, #-0x10]!\n\n\t/* Save the critical section nesting depth. */\n\tLDR\t\tX0, ullCriticalNestingConst\n\tLDR\t\tX3, [X0]\n\n\t/* Save the FPU context indicator. */\n\tLDR\t\tX0, ullPortTaskHasFPUContextConst\n\tLDR\t\tX2, [X0]\n\n\t/* Save the FPU context, if any (32 128-bit registers). */\n\tCMP\t\tX2, #0\n\tB.EQ\t1f\n\tSTP\t\tQ0, Q1, [SP,#-0x20]!\n\tSTP\t\tQ2, Q3, [SP,#-0x20]!\n\tSTP\t\tQ4, Q5, [SP,#-0x20]!\n\tSTP\t\tQ6, Q7, [SP,#-0x20]!\n\tSTP\t\tQ8, Q9, [SP,#-0x20]!\n\tSTP\t\tQ10, Q11, [SP,#-0x20]!\n\tSTP\t\tQ12, Q13, [SP,#-0x20]!\n\tSTP\t\tQ14, Q15, [SP,#-0x20]!\n\tSTP\t\tQ16, Q17, [SP,#-0x20]!\n\tSTP\t\tQ18, Q19, [SP,#-0x20]!\n\tSTP\t\tQ20, Q21, [SP,#-0x20]!\n\tSTP\t\tQ22, Q23, [SP,#-0x20]!\n\tSTP\t\tQ24, Q25, [SP,#-0x20]!\n\tSTP\t\tQ26, Q27, [SP,#-0x20]!\n\tSTP\t\tQ28, Q29, [SP,#-0x20]!\n\tSTP\t\tQ30, Q31, [SP,#-0x20]!\n\n1:\n\t/* Store the critical nesting count and FPU context indicator. */\n\tSTP \tX2, X3, [SP, #-0x10]!\n\n\tLDR \tX0, pxCurrentTCBConst\n\tLDR \tX1, [X0]\n\tMOV \tX0, SP   /* Move SP into X0 for saving. */\n\tSTR \tX0, [X1]\n\n\t/* Switch to use the ELx stack pointer. */\n\tMSR \tSPSEL, #1\n\n\t.endm\n\n; /**********************************************************************/\n\n.macro portRESTORE_CONTEXT\n\n\t/* Switch to use the EL0 stack pointer. */\n\tMSR \tSPSEL, #0\n\n\t/* Set the SP to point to the stack of the task being restored. */\n\tLDR\t\tX0, pxCurrentTCBConst\n\tLDR\t\tX1, [X0]\n\tLDR\t\tX0, [X1]\n\tMOV\t\tSP, X0\n\n\tLDP \tX2, X3, [SP], #0x10  /* Critical nesting and FPU context. */\n\n\t/* Set the PMR register to be correct for the current critical nesting\n\tdepth. */\n\tLDR\t\tX0, ullCriticalNestingConst /* X0 holds the address of ullCriticalNesting. */\n\tMOV\t\tX1, #255\t\t\t\t\t/* X1 holds the unmask value. */\n\tLDR\t\tX4, ullICCPMRConst\t\t\t/* X4 holds the address of the ICCPMR constant. */\n\tCMP\t\tX3, #0\n\tLDR\t\tX5, [X4] \t\t\t\t\t/* X5 holds the address of the ICCPMR register. */\n\tB.EQ\t1f\n\tLDR\t\tX6, ullMaxAPIPriorityMaskConst\n\tLDR\t\tX1, [X6]\t\t\t\t\t/* X1 holds the mask value. */\n1:\n\tSTR\t\tW1, [X5]\t\t\t\t\t/* Write the mask value to ICCPMR. */\n\tDSB \tSY\t\t\t\t\t\t\t/* _RB_Barriers probably not required here. */\n\tISB \tSY\n\tSTR\t\tX3, [X0]\t\t\t\t\t/* Restore the task's critical nesting count. */\n\n\t/* Restore the FPU context indicator. */\n\tLDR\t\tX0, ullPortTaskHasFPUContextConst\n\tSTR\t\tX2, [X0]\n\n\t/* Restore the FPU context, if any. */\n\tCMP\t\tX2, #0\n\tB.EQ\t1f\n\tLDP\t\tQ30, Q31, [SP], #0x20\n\tLDP\t\tQ28, Q29, [SP], #0x20\n\tLDP\t\tQ26, Q27, [SP], #0x20\n\tLDP\t\tQ24, Q25, [SP], #0x20\n\tLDP\t\tQ22, Q23, [SP], #0x20\n\tLDP\t\tQ20, Q21, [SP], #0x20\n\tLDP\t\tQ18, Q19, [SP], #0x20\n\tLDP\t\tQ16, Q17, [SP], #0x20\n\tLDP\t\tQ14, Q15, [SP], #0x20\n\tLDP\t\tQ12, Q13, [SP], #0x20\n\tLDP\t\tQ10, Q11, [SP], #0x20\n\tLDP\t\tQ8, Q9, [SP], #0x20\n\tLDP\t\tQ6, Q7, [SP], #0x20\n\tLDP\t\tQ4, Q5, [SP], #0x20\n\tLDP\t\tQ2, Q3, [SP], #0x20\n\tLDP\t\tQ0, Q1, [SP], #0x20\n1:\n\tLDP \tX2, X3, [SP], #0x10  /* SPSR and ELR. */\n\n#if defined( GUEST )\n\t/* Restore the SPSR. */\n\tMSR\t\tSPSR_EL1, X3\n\t/* Restore the ELR. */\n\tMSR\t\tELR_EL1, X2\n#else\n\t/* Restore the SPSR. */\n\tMSR\t\tSPSR_EL3, X3 /*_RB_ Assumes started in EL3. */\n\t/* Restore the ELR. */\n\tMSR\t\tELR_EL3, X2\n#endif\n\n\tLDP \tX30, XZR, [SP], #0x10\n\tLDP \tX28, X29, [SP], #0x10\n\tLDP \tX26, X27, [SP], #0x10\n\tLDP \tX24, X25, [SP], #0x10\n\tLDP \tX22, X23, [SP], #0x10\n\tLDP \tX20, X21, [SP], #0x10\n\tLDP \tX18, X19, [SP], #0x10\n\tLDP \tX16, X17, [SP], #0x10\n\tLDP \tX14, X15, [SP], #0x10\n\tLDP \tX12, X13, [SP], #0x10\n\tLDP \tX10, X11, [SP], #0x10\n\tLDP \tX8, X9, [SP], #0x10\n\tLDP \tX6, X7, [SP], #0x10\n\tLDP \tX4, X5, [SP], #0x10\n\tLDP \tX2, X3, [SP], #0x10\n\tLDP \tX0, X1, [SP], #0x10\n\n\t/* Switch to use the ELx stack pointer.  _RB_ Might not be required. */\n\tMSR \tSPSEL, #1\n\n\tERET\n\n\t.endm\n\n\n/******************************************************************************\n * FreeRTOS_SWI_Handler handler is used to perform a context switch.\n *****************************************************************************/\n.align 8\n.type FreeRTOS_SWI_Handler, %function\nFreeRTOS_SWI_Handler:\n\t/* Save the context of the current task and select a new task to run. */\n\tportSAVE_CONTEXT\n#if defined( GUEST )\n\tMRS\t\tX0, ESR_EL1\n#else\n\tMRS\t\tX0, ESR_EL3\n#endif\n\n\tLSR\t\tX1, X0, #26\n\n#if defined( GUEST )\n\tCMP\t\tX1, #0x15 \t/* 0x15 = SVC instruction. */\n#else\n\tCMP\t\tX1, #0x17 \t/* 0x17 = SMC instruction. */\n#endif\n\tB.NE\tFreeRTOS_Abort\n\tBL \t\tvTaskSwitchContext\n\n\tportRESTORE_CONTEXT\n\nFreeRTOS_Abort:\n\t/* Full ESR is in X0, exception class code is in X1. */\n\tB\t\t.\n\n/******************************************************************************\n * vPortRestoreTaskContext is used to start the scheduler.\n *****************************************************************************/\n.align 8\n.type vPortRestoreTaskContext, %function\nvPortRestoreTaskContext:\n.set freertos_vector_base,\t_freertos_vector_table\n\n\t/* Install the FreeRTOS interrupt handlers. */\n\tLDR\t\tX1, =freertos_vector_base\n#if defined( GUEST )\n\tMSR\t\tVBAR_EL1, X1\n#else\n\tMSR\t\tVBAR_EL3, X1\n#endif\n\tDSB\t\tSY\n\tISB\t\tSY\n\n\t/* Start the first task. */\n\tportRESTORE_CONTEXT\n\n\n/******************************************************************************\n * FreeRTOS_IRQ_Handler handles IRQ entry and exit.\n *****************************************************************************/\n.align 8\n.type FreeRTOS_IRQ_Handler, %function\nFreeRTOS_IRQ_Handler:\n\t/* Save volatile registers. */\n\tSTP\t\tX0, X1, [SP, #-0x10]!\n\tSTP\t\tX2, X3, [SP, #-0x10]!\n\tSTP\t\tX4, X5, [SP, #-0x10]!\n\tSTP\t\tX6, X7, [SP, #-0x10]!\n\tSTP\t\tX8, X9, [SP, #-0x10]!\n\tSTP\t\tX10, X11, [SP, #-0x10]!\n\tSTP\t\tX12, X13, [SP, #-0x10]!\n\tSTP\t\tX14, X15, [SP, #-0x10]!\n\tSTP\t\tX16, X17, [SP, #-0x10]!\n\tSTP\t\tX18, X19, [SP, #-0x10]!\n\tSTP\t\tX29, X30, [SP, #-0x10]!\n\n\t/* Save the SPSR and ELR. */\n#if defined( GUEST )\n\tMRS\t\tX3, SPSR_EL1\n\tMRS\t\tX2, ELR_EL1\n#else\n\tMRS\t\tX3, SPSR_EL3\n\tMRS\t\tX2, ELR_EL3\n#endif\n\tSTP \tX2, X3, [SP, #-0x10]!\n\n\t/* Increment the interrupt nesting counter. */\n\tLDR\t\tX5, ullPortInterruptNestingConst\n\tLDR\t\tX1, [X5]\t/* Old nesting count in X1. */\n\tADD\t\tX6, X1, #1\n\tSTR\t\tX6, [X5]\t/* Address of nesting count variable in X5. */\n\n\t/* Maintain the interrupt nesting information across the function call. */\n\tSTP\t\tX1, X5, [SP, #-0x10]!\n\n\t/* Read value from the interrupt acknowledge register, which is stored in W0\n\tfor future parameter and interrupt clearing use. */\n\tLDR \tX2, ullICCIARConst\n\tLDR\t\tX3, [X2]\n\tLDR\t\tW0, [X3]\t/* ICCIAR in W0 as parameter. */\n\n\t/* Maintain the ICCIAR value across the function call. */\n\tSTP\t\tX0, X1, [SP, #-0x10]!\n\n\t/* Call the C handler. */\n\tBL vApplicationIRQHandler\n\n\t/* Disable interrupts. */\n\tMSR \tDAIFSET, #2\n\tDSB\t\tSY\n\tISB\t\tSY\n\n\t/* Restore the ICCIAR value. */\n\tLDP\t\tX0, X1, [SP], #0x10\n\n\t/* End IRQ processing by writing ICCIAR to the EOI register. */\n\tLDR \tX4, ullICCEOIRConst\n\tLDR\t\tX4, [X4]\n\tSTR\t\tW0, [X4]\n\n\t/* Restore the critical nesting count. */\n\tLDP\t\tX1, X5, [SP], #0x10\n\tSTR\t\tX1, [X5]\n\n\t/* Has interrupt nesting unwound? */\n\tCMP\t\tX1, #0\n\tB.NE\tExit_IRQ_No_Context_Switch\n\n\t/* Is a context switch required? */\n\tLDR\t\tX0, ullPortYieldRequiredConst\n\tLDR\t\tX1, [X0]\n\tCMP\t\tX1, #0\n\tB.EQ\tExit_IRQ_No_Context_Switch\n\n\t/* Reset ullPortYieldRequired to 0. */\n\tMOV\t\tX2, #0\n\tSTR\t\tX2, [X0]\n\n\t/* Restore volatile registers. */\n\tLDP \tX4, X5, [SP], #0x10  /* SPSR and ELR. */\n#if defined( GUEST )\n\tMSR\t\tSPSR_EL1, X5\n\tMSR\t\tELR_EL1, X4\n#else\n\tMSR\t\tSPSR_EL3, X5 /*_RB_ Assumes started in EL3. */\n\tMSR\t\tELR_EL3, X4\n#endif\n\tDSB\t\tSY\n\tISB\t\tSY\n\n\tLDP\t\tX29, X30, [SP], #0x10\n\tLDP\t\tX18, X19, [SP], #0x10\n\tLDP\t\tX16, X17, [SP], #0x10\n\tLDP\t\tX14, X15, [SP], #0x10\n\tLDP\t\tX12, X13, [SP], #0x10\n\tLDP\t\tX10, X11, [SP], #0x10\n\tLDP\t\tX8, X9, [SP], #0x10\n\tLDP\t\tX6, X7, [SP], #0x10\n\tLDP\t\tX4, X5, [SP], #0x10\n\tLDP\t\tX2, X3, [SP], #0x10\n\tLDP\t\tX0, X1, [SP], #0x10\n\n\t/* Save the context of the current task and select a new task to run. */\n\tportSAVE_CONTEXT\n\tBL vTaskSwitchContext\n\tportRESTORE_CONTEXT\n\nExit_IRQ_No_Context_Switch:\n\t/* Restore volatile registers. */\n\tLDP \tX4, X5, [SP], #0x10  /* SPSR and ELR. */\n#if defined( GUEST )\n\tMSR\t\tSPSR_EL1, X5\n\tMSR\t\tELR_EL1, X4\n#else\n\tMSR\t\tSPSR_EL3, X5 /*_RB_ Assumes started in EL3. */\n\tMSR\t\tELR_EL3, X4\n#endif\n\tDSB\t\tSY\n\tISB\t\tSY\n\n\tLDP\t\tX29, X30, [SP], #0x10\n\tLDP\t\tX18, X19, [SP], #0x10\n\tLDP\t\tX16, X17, [SP], #0x10\n\tLDP\t\tX14, X15, [SP], #0x10\n\tLDP\t\tX12, X13, [SP], #0x10\n\tLDP\t\tX10, X11, [SP], #0x10\n\tLDP\t\tX8, X9, [SP], #0x10\n\tLDP\t\tX6, X7, [SP], #0x10\n\tLDP\t\tX4, X5, [SP], #0x10\n\tLDP\t\tX2, X3, [SP], #0x10\n\tLDP\t\tX0, X1, [SP], #0x10\n\n\tERET\n\n\n\n\n.align 8\npxCurrentTCBConst: .dword pxCurrentTCB\nullCriticalNestingConst: .dword ullCriticalNesting\nullPortTaskHasFPUContextConst: .dword ullPortTaskHasFPUContext\n\nullICCPMRConst: .dword ullICCPMR\nullMaxAPIPriorityMaskConst: .dword ullMaxAPIPriorityMask\nullPortInterruptNestingConst: .dword ullPortInterruptNesting\nullPortYieldRequiredConst: .dword ullPortYieldRequired\nullICCIARConst:\t.dword ullICCIAR\nullICCEOIRConst: .dword ullICCEOIR\nvApplicationIRQHandlerConst: .word vApplicationIRQHandler\n\n\n\n.end\n\n\n\n\n\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CA53_64_BIT/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef PORTMACRO_H\n#define PORTMACRO_H\n\n#ifdef __cplusplus\n\textern \"C\" {\n#endif\n\n/*-----------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the given hardware\n * and compiler.\n *\n * These settings should not be altered.\n *-----------------------------------------------------------\n */\n\n/* Type definitions. */\n#define portCHAR\t\tchar\n#define portFLOAT\t\tfloat\n#define portDOUBLE\t\tdouble\n#define portLONG\t\tlong\n#define portSHORT\t\tshort\n#define portSTACK_TYPE\tsize_t\n#define portBASE_TYPE\tlong\n\ntypedef portSTACK_TYPE StackType_t;\ntypedef portBASE_TYPE BaseType_t;\ntypedef uint64_t UBaseType_t;\n\ntypedef uint64_t TickType_t;\n#define portMAX_DELAY ( ( TickType_t ) 0xffffffffffffffff )\n\n/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\nnot need to be guarded with a critical section. */\n#define portTICK_TYPE_IS_ATOMIC 1\n\n/*-----------------------------------------------------------*/\n\n/* Hardware specifics. */\n#define portSTACK_GROWTH\t\t\t( -1 )\n#define portTICK_PERIOD_MS\t\t\t( ( TickType_t ) 1000 / configTICK_RATE_HZ )\n#define portBYTE_ALIGNMENT\t\t\t16\n#define portPOINTER_SIZE_TYPE \t\tuint64_t\n\n/*-----------------------------------------------------------*/\n\n/* Task utilities. */\n\n/* Called at the end of an ISR that can cause a context switch. */\n#define portEND_SWITCHING_ISR( xSwitchRequired )\\\n{\t\t\t\t\t\t\t\t\t\t\t\t\\\nextern uint64_t ullPortYieldRequired;\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tif( xSwitchRequired != pdFALSE )\t\t\t\\\n\t{\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tullPortYieldRequired = pdTRUE;\t\t\t\\\n\t}\t\t\t\t\t\t\t\t\t\t\t\\\n}\n\n#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\n#if defined( GUEST )\n\t#define portYIELD() __asm volatile ( \"SVC 0\" ::: \"memory\" )\n#else\n\t#define portYIELD() __asm volatile ( \"SMC 0\" ::: \"memory\" )\n#endif\n/*-----------------------------------------------------------\n * Critical section control\n *----------------------------------------------------------*/\n\nextern void vPortEnterCritical( void );\nextern void vPortExitCritical( void );\nextern UBaseType_t uxPortSetInterruptMask( void );\nextern void vPortClearInterruptMask( UBaseType_t uxNewMaskValue );\nextern void vPortInstallFreeRTOSVectorTable( void );\n\n#define portDISABLE_INTERRUPTS()\t\t\t\t\t\t\t\t\t\\\n\t__asm volatile ( \"MSR DAIFSET, #2\" ::: \"memory\" );\t\t\t\t\\\n\t__asm volatile ( \"DSB SY\" );\t\t\t\t\t\t\t\t\t\\\n\t__asm volatile ( \"ISB SY\" );\n\n#define portENABLE_INTERRUPTS()\t\t\t\t\t\t\t\t\t\t\\\n\t__asm volatile ( \"MSR DAIFCLR, #2\" ::: \"memory\" );\t\t\t\t\\\n\t__asm volatile ( \"DSB SY\" );\t\t\t\t\t\t\t\t\t\\\n\t__asm volatile ( \"ISB SY\" );\n\n\n/* These macros do not globally disable/enable interrupts.  They do mask off\ninterrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */\n#define portENTER_CRITICAL()\t\tvPortEnterCritical();\n#define portEXIT_CRITICAL()\t\t\tvPortExitCritical();\n#define portSET_INTERRUPT_MASK_FROM_ISR()\t\tuxPortSetInterruptMask()\n#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)\tvPortClearInterruptMask(x)\n\n/*-----------------------------------------------------------*/\n\n/* Task function macros as described on the FreeRTOS.org WEB site.  These are\nnot required for this port but included in case common demo code that uses these\nmacros is used. */\n#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )\tvoid vFunction( void *pvParameters )\n#define portTASK_FUNCTION( vFunction, pvParameters )\tvoid vFunction( void *pvParameters )\n\n/* Prototype of the FreeRTOS tick handler.  This must be installed as the\nhandler for whichever peripheral is used to generate the RTOS tick. */\nvoid FreeRTOS_Tick_Handler( void );\n\n/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()\nbefore any floating point instructions are executed. */\nvoid vPortTaskUsesFPU( void );\n#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()\n\n#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )\n#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )\n\n/* Architecture specific optimisations. */\n#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION\n\t#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1\n#endif\n\n#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1\n\n\t/* Store/clear the ready priorities in a bit map. */\n\t#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )\n\t#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )\n\n\t/*-----------------------------------------------------------*/\n\n\t#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __builtin_clz( uxReadyPriorities ) )\n\n#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */\n\n#ifdef configASSERT\n\tvoid vPortValidateInterruptPriority( void );\n\t#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() \tvPortValidateInterruptPriority()\n#endif /* configASSERT */\n\n#define portNOP() __asm volatile( \"NOP\" )\n#define portINLINE __inline\n\n#ifdef __cplusplus\n\t} /* extern C */\n#endif\n\n\n/* The number of bits to shift for an interrupt priority is dependent on the\nnumber of bits implemented by the interrupt controller. */\n#if configUNIQUE_INTERRUPT_PRIORITIES == 16\n\t#define portPRIORITY_SHIFT 4\n\t#define portMAX_BINARY_POINT_VALUE\t3\n#elif configUNIQUE_INTERRUPT_PRIORITIES == 32\n\t#define portPRIORITY_SHIFT 3\n\t#define portMAX_BINARY_POINT_VALUE\t2\n#elif configUNIQUE_INTERRUPT_PRIORITIES == 64\n\t#define portPRIORITY_SHIFT 2\n\t#define portMAX_BINARY_POINT_VALUE\t1\n#elif configUNIQUE_INTERRUPT_PRIORITIES == 128\n\t#define portPRIORITY_SHIFT 1\n\t#define portMAX_BINARY_POINT_VALUE\t0\n#elif configUNIQUE_INTERRUPT_PRIORITIES == 256\n\t#define portPRIORITY_SHIFT 0\n\t#define portMAX_BINARY_POINT_VALUE\t0\n#else\n\t#error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting.  configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware\n#endif\n\n/* Interrupt controller access addresses. */\n#define portICCPMR_PRIORITY_MASK_OFFSET  \t\t\t\t\t\t( 0x04 )\n#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET \t\t\t\t( 0x0C )\n#define portICCEOIR_END_OF_INTERRUPT_OFFSET \t\t\t\t\t( 0x10 )\n#define portICCBPR_BINARY_POINT_OFFSET\t\t\t\t\t\t\t( 0x08 )\n#define portICCRPR_RUNNING_PRIORITY_OFFSET\t\t\t\t\t\t( 0x14 )\n\n#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS \t\t( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )\n#define portICCPMR_PRIORITY_MASK_REGISTER \t\t\t\t\t( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )\n#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS \t( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )\n#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS \t\t( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )\n#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS \t\t\t( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )\n#define portICCBPR_BINARY_POINT_REGISTER \t\t\t\t\t( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )\n#define portICCRPR_RUNNING_PRIORITY_REGISTER \t\t\t\t( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )\n\n#define portMEMORY_BARRIER() __asm volatile( \"\" ::: \"memory\" )\n\n#endif /* PORTMACRO_H */\n\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CA53_64_BIT_SRE/port.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Standard includes. */\n#include <stdlib.h>\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n#ifndef configUNIQUE_INTERRUPT_PRIORITIES\n\t#error configUNIQUE_INTERRUPT_PRIORITIES must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html\n#endif\n\n#ifndef configSETUP_TICK_INTERRUPT\n\t#error configSETUP_TICK_INTERRUPT() must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html\n#endif /* configSETUP_TICK_INTERRUPT */\n\n#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY\n\t#error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html\n#endif\n\n#if configMAX_API_CALL_INTERRUPT_PRIORITY == 0\n\t#error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0\n#endif\n\n#if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES\n\t#error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority\n#endif\n\n#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1\n\t/* Check the configuration. */\n\t#if( configMAX_PRIORITIES > 32 )\n\t\t#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.\n\t#endif\n#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */\n\n/* In case security extensions are implemented. */\n#if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )\n\t#error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )\n#endif\n\n/* Some vendor specific files default configCLEAR_TICK_INTERRUPT() in\nportmacro.h. */\n#ifndef configCLEAR_TICK_INTERRUPT\n\t#define configCLEAR_TICK_INTERRUPT()\n#endif\n\n/* A critical section is exited when the critical section nesting count reaches\nthis value. */\n#define portNO_CRITICAL_NESTING\t\t\t( ( size_t ) 0 )\n\n/* In all GICs 255 can be written to the priority mask register to unmask all\n(but the lowest) interrupt priority. */\n#define portUNMASK_VALUE\t\t\t\t( 0xFFUL )\n\n/* Tasks are not created with a floating point context, but can be given a\nfloating point context after they have been created.  A variable is stored as\npart of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task\ndoes not have an FPU context, or any other value if the task does have an FPU\ncontext. */\n#define portNO_FLOATING_POINT_CONTEXT\t( ( StackType_t ) 0 )\n\n/* Constants required to setup the initial task context. */\n#define portSP_ELx\t\t\t\t\t\t( ( StackType_t ) 0x01 )\n#define portSP_EL0\t\t\t\t\t\t( ( StackType_t ) 0x00 )\n\n#if defined( GUEST )\n\t#define portEL1\t\t\t\t\t\t( ( StackType_t ) 0x04 )\n\t#define portINITIAL_PSTATE\t\t\t\t( portEL1 | portSP_EL0 )\n#else\n\t#define portEL3\t\t\t\t\t\t( ( StackType_t ) 0x0c )\n\t/* At the time of writing, the BSP only supports EL3. */\n\t#define portINITIAL_PSTATE\t\t\t( portEL3 | portSP_EL0 )\n#endif\n\n/* Masks all bits in the APSR other than the mode bits. */\n#define portAPSR_MODE_BITS_MASK\t\t\t( 0x0C )\n\n/* The I bit in the DAIF bits. */\n#define portDAIF_I\t\t\t\t\t\t( 0x80 )\n\n/* Macro to unmask all interrupt priorities. */\n/* s3_0_c4_c6_0 is ICC_PMR_EL1. */\n#define portCLEAR_INTERRUPT_MASK()\t\t\t\t\t\t\\\n{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t__asm volatile (\t\"MSR DAIFSET, #2 \t\t\\n\"\t\t\\\n\t\t\t\t\t\t\"DSB SY\t\t\t\t\t\\n\"\t\t\\\n\t\t\t\t\t\t\"ISB SY\t\t\t\t\t\\n\"\t\t\\\n\t\t\t\t\t\t\"MSR s3_0_c4_c6_0, %0 \t\\n\"\t\t\\\n\t\t\t\t\t\t\"DSB SY\t\t\t\t\t\\n\"\t\t\\\n\t\t\t\t\t\t\"ISB SY\t\t\t\t\t\\n\"\t\t\\\n\t\t\t\t\t\t\"MSR DAIFCLR, #2 \t\t\\n\"\t\t\\\n\t\t\t\t\t\t\"DSB SY\t\t\t\t\t\\n\"\t\t\\\n\t\t\t\t\t\t\"ISB SY\t\t\t\t\t\\n\"\t\t\\\n\t\t\t\t\t\t::\"r\"( portUNMASK_VALUE ) );\t\\\n}\n\n/*-----------------------------------------------------------*/\n\n/*\n * Starts the first task executing.  This function is necessarily written in\n * assembly code so is implemented in portASM.s.\n */\nextern void vPortRestoreTaskContext( void );\n\n/*-----------------------------------------------------------*/\n\n/* A variable is used to keep track of the critical section nesting.  This\nvariable has to be stored as part of the task context and must be initialised to\na non zero value to ensure interrupts don't inadvertently become unmasked before\nthe scheduler starts.  As it is stored as part of the task context it will\nautomatically be set to 0 when the first task is started. */\nvolatile uint64_t ullCriticalNesting = 9999ULL;\n\n/* Saved as part of the task context.  If ullPortTaskHasFPUContext is non-zero\nthen floating point context must be saved and restored for the task. */\nuint64_t ullPortTaskHasFPUContext = pdFALSE;\n\n/* Set to 1 to pend a context switch from an ISR. */\nuint64_t ullPortYieldRequired = pdFALSE;\n\n/* Counts the interrupt nesting depth.  A context switch is only performed if\nif the nesting depth is 0. */\nuint64_t ullPortInterruptNesting = 0;\n\n/* Used in the ASM code. */\n__attribute__(( used )) const uint64_t ullMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );\n\n/*-----------------------------------------------------------*/\n\n/*\n * See header file for description.\n */\nStackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )\n{\n\t/* Setup the initial stack of the task.  The stack is set exactly as\n\texpected by the portRESTORE_CONTEXT() macro. */\n\n\t/* First all the general purpose registers. */\n\tpxTopOfStack--;\n\t*pxTopOfStack = 0x0101010101010101ULL;\t/* R1 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = 0x0303030303030303ULL;\t/* R3 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = 0x0202020202020202ULL;\t/* R2 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = 0x0505050505050505ULL;\t/* R5 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = 0x0404040404040404ULL;\t/* R4 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = 0x0707070707070707ULL;\t/* R7 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = 0x0606060606060606ULL;\t/* R6 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = 0x0909090909090909ULL;\t/* R9 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = 0x0808080808080808ULL;\t/* R8 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = 0x1111111111111111ULL;\t/* R11 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = 0x1010101010101010ULL;\t/* R10 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = 0x1313131313131313ULL;\t/* R13 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = 0x1212121212121212ULL;\t/* R12 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = 0x1515151515151515ULL;\t/* R15 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = 0x1414141414141414ULL;\t/* R14 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = 0x1717171717171717ULL;\t/* R17 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = 0x1616161616161616ULL;\t/* R16 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = 0x1919191919191919ULL;\t/* R19 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = 0x1818181818181818ULL;\t/* R18 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = 0x2121212121212121ULL;\t/* R21 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = 0x2020202020202020ULL;\t/* R20 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = 0x2323232323232323ULL;\t/* R23 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = 0x2222222222222222ULL;\t/* R22 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = 0x2525252525252525ULL;\t/* R25 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = 0x2424242424242424ULL;\t/* R24 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = 0x2727272727272727ULL;\t/* R27 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = 0x2626262626262626ULL;\t/* R26 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = 0x2929292929292929ULL;\t/* R29 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = 0x2828282828282828ULL;\t/* R28 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x00;\t/* XZR - has no effect, used so there are an even number of registers. */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x00;\t/* R30 - procedure call link register. */\n\tpxTopOfStack--;\n\n\t*pxTopOfStack = portINITIAL_PSTATE;\n\tpxTopOfStack--;\n\n\t*pxTopOfStack = ( StackType_t ) pxCode; /* Exception return address. */\n\tpxTopOfStack--;\n\n\t/* The task will start with a critical nesting count of 0 as interrupts are\n\tenabled. */\n\t*pxTopOfStack = portNO_CRITICAL_NESTING;\n\tpxTopOfStack--;\n\n\t/* The task will start without a floating point context.  A task that uses\n\tthe floating point hardware must call vPortTaskUsesFPU() before executing\n\tany floating point instructions. */\n\t*pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;\n\n\treturn pxTopOfStack;\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xPortStartScheduler( void )\n{\nuint32_t ulAPSR;\n\n\t__asm volatile ( \"MRS %0, CurrentEL\" : \"=r\" ( ulAPSR ) );\n\tulAPSR &= portAPSR_MODE_BITS_MASK;\n\n#if defined( GUEST )\n\tconfigASSERT( ulAPSR == portEL1 );\n\tif( ulAPSR == portEL1 )\n#else\n\tconfigASSERT( ulAPSR == portEL3 );\n\tif( ulAPSR == portEL3 )\n#endif\n\t{\n\t\t/* Interrupts are turned off in the CPU itself to ensure a tick does\n\t\tnot execute\twhile the scheduler is being started.  Interrupts are\n\t\tautomatically turned back on in the CPU when the first task starts\n\t\texecuting. */\n\t\tportDISABLE_INTERRUPTS();\n\n\t\t/* Start the timer that generates the tick ISR. */\n\t\tconfigSETUP_TICK_INTERRUPT();\n\n\t\t/* Start the first task executing. */\n\t\tvPortRestoreTaskContext();\n\t}\n\n\treturn 0;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEndScheduler( void )\n{\n\t/* Not implemented in ports where there is nothing to return to.\n\tArtificially force an assert. */\n\tconfigASSERT( ullCriticalNesting == 1000ULL );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEnterCritical( void )\n{\n\t/* Mask interrupts up to the max syscall interrupt priority. */\n\tuxPortSetInterruptMask();\n\n\t/* Now interrupts are disabled ullCriticalNesting can be accessed\n\tdirectly.  Increment ullCriticalNesting to keep a count of how many times\n\tportENTER_CRITICAL() has been called. */\n\tullCriticalNesting++;\n\n\t/* This is not the interrupt safe version of the enter critical function so\n\tassert() if it is being called from an interrupt context.  Only API\n\tfunctions that end in \"FromISR\" can be used in an interrupt.  Only assert if\n\tthe critical nesting count is 1 to protect against recursive calls if the\n\tassert function also uses a critical section. */\n\tif( ullCriticalNesting == 1ULL )\n\t{\n\t\tconfigASSERT( ullPortInterruptNesting == 0 );\n\t}\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortExitCritical( void )\n{\n\tif( ullCriticalNesting > portNO_CRITICAL_NESTING )\n\t{\n\t\t/* Decrement the nesting count as the critical section is being\n\t\texited. */\n\t\tullCriticalNesting--;\n\n\t\t/* If the nesting level has reached zero then all interrupt\n\t\tpriorities must be re-enabled. */\n\t\tif( ullCriticalNesting == portNO_CRITICAL_NESTING )\n\t\t{\n\t\t\t/* Critical nesting has reached zero so all interrupt priorities\n\t\t\tshould be unmasked. */\n\t\t\tportCLEAR_INTERRUPT_MASK();\n\t\t}\n\t}\n}\n/*-----------------------------------------------------------*/\n\nvoid FreeRTOS_Tick_Handler( void )\n{\n\t/* Must be the lowest possible priority. */\n\t#if !defined( QEMU )\n\t{\n\t\tuint64_t ullRunningInterruptPriority;\n\t\t/* s3_0_c12_c11_3 is ICC_RPR_EL1. */\n\t\t__asm volatile ( \"MRS %0, s3_0_c12_c11_3\" : \"=r\" ( ullRunningInterruptPriority ) );\n\t\tconfigASSERT( ullRunningInterruptPriority == ( portLOWEST_USABLE_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );\n\t}\n\t#endif\n\n\t/* Interrupts should not be enabled before this point. */\n\t#if( configASSERT_DEFINED == 1 )\n\t{\n\t\tuint32_t ulMaskBits;\n\n\t\t__asm volatile( \"MRS %0, DAIF\" : \"=r\"( ulMaskBits ) :: \"memory\" );\n\t\tconfigASSERT( ( ulMaskBits & portDAIF_I ) != 0 );\n\t}\n\t#endif /* configASSERT_DEFINED */\n\n\t/* Set interrupt mask before altering scheduler structures.   The tick\n\thandler runs at the lowest priority, so interrupts cannot already be masked,\n\tso there is no need to save and restore the current mask value.  It is\n\tnecessary to turn off interrupts in the CPU itself while the ICCPMR is being\n\tupdated. */\n\t/* s3_0_c4_c6_0 is ICC_PMR_EL1. */\n\t__asm volatile ( \"MSR s3_0_c4_c6_0, %0\t\t\\n\"\n\t\t\t\t\t \"DSB SY\t\t\t\t\t\\n\"\n\t\t\t\t\t \"ISB SY\t\t\t\t\t\\n\"\n\t\t\t\t\t :: \"r\" ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) : \"memory\" );\n\n\t/* Ok to enable interrupts after the interrupt source has been cleared. */\n\tconfigCLEAR_TICK_INTERRUPT();\n\tportENABLE_INTERRUPTS();\n\n\t/* Increment the RTOS tick. */\n\tif( xTaskIncrementTick() != pdFALSE )\n\t{\n\t\tullPortYieldRequired = pdTRUE;\n\t}\n\n\t/* Ensure all interrupt priorities are active again. */\n\tportCLEAR_INTERRUPT_MASK();\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortTaskUsesFPU( void )\n{\n\t/* A task is registering the fact that it needs an FPU context.  Set the\n\tFPU flag (which is saved as part of the task context). */\n\tullPortTaskHasFPUContext = pdTRUE;\n\n\t/* Consider initialising the FPSR here - but probably not necessary in\n\tAArch64. */\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortClearInterruptMask( UBaseType_t uxNewMaskValue )\n{\n\tif( uxNewMaskValue == pdFALSE )\n\t{\n\t\tportCLEAR_INTERRUPT_MASK();\n\t}\n}\n/*-----------------------------------------------------------*/\n\nUBaseType_t uxPortSetInterruptMask( void )\n{\nuint32_t ulReturn;\nuint64_t ullPMRValue;\n\n\t/* Interrupt in the CPU must be turned off while the ICCPMR is being\n\tupdated. */\n\tportDISABLE_INTERRUPTS();\n\t/* s3_0_c4_c6_0 is ICC_PMR_EL1. */\n\t__asm volatile ( \"MRS %0, s3_0_c4_c6_0\" : \"=r\" ( ullPMRValue ) );\n\tif( ullPMRValue == ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )\n\t{\n\t\t/* Interrupts were already masked. */\n\t\tulReturn = pdTRUE;\n\t}\n\telse\n\t{\n\t\tulReturn = pdFALSE;\n\t\t/* s3_0_c4_c6_0 is ICC_PMR_EL1. */\n\t\t__asm volatile ( \"MSR s3_0_c4_c6_0, %0\t\t\\n\"\n\t\t\t\t\t\t \"DSB SY\t\t\t\t\t\\n\"\n\t\t\t\t\t\t \"ISB SY\t\t\t\t\t\\n\"\n\t\t\t\t\t\t :: \"r\" ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) : \"memory\" );\n\t}\n\n\tportENABLE_INTERRUPTS();\n\n\treturn ulReturn;\n}\n/*-----------------------------------------------------------*/\n\n#if( configASSERT_DEFINED == 1 )\n\n\tvoid vPortValidateInterruptPriority( void )\n\t{\n\t\t/* The following assertion will fail if a service routine (ISR) for\n\t\tan interrupt that has been assigned a priority above\n\t\tconfigMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\n\t\tfunction.  ISR safe FreeRTOS API functions must *only* be called\n\t\tfrom interrupts that have been assigned a priority at or below\n\t\tconfigMAX_SYSCALL_INTERRUPT_PRIORITY.\n\n\t\tNumerically low interrupt priority numbers represent logically high\n\t\tinterrupt priorities, therefore the priority of the interrupt must\n\t\tbe set to a value equal to or numerically *higher* than\n\t\tconfigMAX_SYSCALL_INTERRUPT_PRIORITY.\n\n\t\tFreeRTOS maintains separate thread and ISR API functions to ensure\n\t\tinterrupt entry is as fast and simple as possible. */\n\t\tuint64_t ullRunningInterruptPriority;\n\t\t/* s3_0_c12_c11_3 is ICC_RPR_EL1. */\n\t\t__asm volatile ( \"MRS %0, s3_0_c12_c11_3\" : \"=r\" ( ullRunningInterruptPriority ) );\n\t\tconfigASSERT( ullRunningInterruptPriority >= ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );\n\t}\n\n#endif /* configASSERT_DEFINED */\n/*-----------------------------------------------------------*/\n\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CA53_64_BIT_SRE/portASM.S",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n\t.text\n\n\t/* Variables and functions. */\n\t.extern ullMaxAPIPriorityMask\n\t.extern pxCurrentTCB\n\t.extern vTaskSwitchContext\n\t.extern vApplicationIRQHandler\n\t.extern ullPortInterruptNesting\n\t.extern ullPortTaskHasFPUContext\n\t.extern ullCriticalNesting\n\t.extern ullPortYieldRequired\n\t.extern _freertos_vector_table\n\n\t.global FreeRTOS_IRQ_Handler\n\t.global FreeRTOS_SWI_Handler\n\t.global vPortRestoreTaskContext\n\n\n.macro portSAVE_CONTEXT\n\n\t/* Switch to use the EL0 stack pointer. */\n\tMSR \tSPSEL, #0\n\n\t/* Save the entire context. */\n\tSTP \tX0, X1, [SP, #-0x10]!\n\tSTP \tX2, X3, [SP, #-0x10]!\n\tSTP \tX4, X5, [SP, #-0x10]!\n\tSTP \tX6, X7, [SP, #-0x10]!\n\tSTP \tX8, X9, [SP, #-0x10]!\n\tSTP \tX10, X11, [SP, #-0x10]!\n\tSTP \tX12, X13, [SP, #-0x10]!\n\tSTP \tX14, X15, [SP, #-0x10]!\n\tSTP \tX16, X17, [SP, #-0x10]!\n\tSTP \tX18, X19, [SP, #-0x10]!\n\tSTP \tX20, X21, [SP, #-0x10]!\n\tSTP \tX22, X23, [SP, #-0x10]!\n\tSTP \tX24, X25, [SP, #-0x10]!\n\tSTP \tX26, X27, [SP, #-0x10]!\n\tSTP \tX28, X29, [SP, #-0x10]!\n\tSTP \tX30, XZR, [SP, #-0x10]!\n\n\t/* Save the SPSR. */\n#if defined( GUEST )\n\tMRS\t\tX3, SPSR_EL1\n\tMRS\t\tX2, ELR_EL1\n#else\n\tMRS\t\tX3, SPSR_EL3\n\t/* Save the ELR. */\n\tMRS\t\tX2, ELR_EL3\n#endif\n\n\tSTP \tX2, X3, [SP, #-0x10]!\n\n\t/* Save the critical section nesting depth. */\n\tLDR\t\tX0, ullCriticalNestingConst\n\tLDR\t\tX3, [X0]\n\n\t/* Save the FPU context indicator. */\n\tLDR\t\tX0, ullPortTaskHasFPUContextConst\n\tLDR\t\tX2, [X0]\n\n\t/* Save the FPU context, if any (32 128-bit registers). */\n\tCMP\t\tX2, #0\n\tB.EQ\t1f\n\tSTP\t\tQ0, Q1, [SP,#-0x20]!\n\tSTP\t\tQ2, Q3, [SP,#-0x20]!\n\tSTP\t\tQ4, Q5, [SP,#-0x20]!\n\tSTP\t\tQ6, Q7, [SP,#-0x20]!\n\tSTP\t\tQ8, Q9, [SP,#-0x20]!\n\tSTP\t\tQ10, Q11, [SP,#-0x20]!\n\tSTP\t\tQ12, Q13, [SP,#-0x20]!\n\tSTP\t\tQ14, Q15, [SP,#-0x20]!\n\tSTP\t\tQ16, Q17, [SP,#-0x20]!\n\tSTP\t\tQ18, Q19, [SP,#-0x20]!\n\tSTP\t\tQ20, Q21, [SP,#-0x20]!\n\tSTP\t\tQ22, Q23, [SP,#-0x20]!\n\tSTP\t\tQ24, Q25, [SP,#-0x20]!\n\tSTP\t\tQ26, Q27, [SP,#-0x20]!\n\tSTP\t\tQ28, Q29, [SP,#-0x20]!\n\tSTP\t\tQ30, Q31, [SP,#-0x20]!\n\n1:\n\t/* Store the critical nesting count and FPU context indicator. */\n\tSTP \tX2, X3, [SP, #-0x10]!\n\n\tLDR \tX0, pxCurrentTCBConst\n\tLDR \tX1, [X0]\n\tMOV \tX0, SP   /* Move SP into X0 for saving. */\n\tSTR \tX0, [X1]\n\n\t/* Switch to use the ELx stack pointer. */\n\tMSR \tSPSEL, #1\n\n\t.endm\n\n; /**********************************************************************/\n\n.macro portRESTORE_CONTEXT\n\n\t/* Switch to use the EL0 stack pointer. */\n\tMSR \tSPSEL, #0\n\n\t/* Set the SP to point to the stack of the task being restored. */\n\tLDR\t\tX0, pxCurrentTCBConst\n\tLDR\t\tX1, [X0]\n\tLDR\t\tX0, [X1]\n\tMOV\t\tSP, X0\n\n\tLDP \tX2, X3, [SP], #0x10  /* Critical nesting and FPU context. */\n\n\t/* Set the PMR register to be correct for the current critical nesting\n\tdepth. */\n\tLDR\t\tX0, ullCriticalNestingConst /* X0 holds the address of ullCriticalNesting. */\n\tMOV\t\tX1, #255\t\t\t\t\t/* X1 holds the unmask value. */\n\tCMP\t\tX3, #0\n\tB.EQ\t1f\n\tLDR\t\tX6, ullMaxAPIPriorityMaskConst\n\tLDR\t\tX1, [X6]\t\t\t\t\t/* X1 holds the mask value. */\n1:\n\tMSR\t\ts3_0_c4_c6_0, X1\t\t\t/* Write the mask value to ICCPMR. s3_0_c4_c6_0 is ICC_PMR_EL1. */\n\tDSB \tSY\t\t\t\t\t\t\t/* _RB_Barriers probably not required here. */\n\tISB \tSY\n\tSTR\t\tX3, [X0]\t\t\t\t\t/* Restore the task's critical nesting count. */\n\n\t/* Restore the FPU context indicator. */\n\tLDR\t\tX0, ullPortTaskHasFPUContextConst\n\tSTR\t\tX2, [X0]\n\n\t/* Restore the FPU context, if any. */\n\tCMP\t\tX2, #0\n\tB.EQ\t1f\n\tLDP\t\tQ30, Q31, [SP], #0x20\n\tLDP\t\tQ28, Q29, [SP], #0x20\n\tLDP\t\tQ26, Q27, [SP], #0x20\n\tLDP\t\tQ24, Q25, [SP], #0x20\n\tLDP\t\tQ22, Q23, [SP], #0x20\n\tLDP\t\tQ20, Q21, [SP], #0x20\n\tLDP\t\tQ18, Q19, [SP], #0x20\n\tLDP\t\tQ16, Q17, [SP], #0x20\n\tLDP\t\tQ14, Q15, [SP], #0x20\n\tLDP\t\tQ12, Q13, [SP], #0x20\n\tLDP\t\tQ10, Q11, [SP], #0x20\n\tLDP\t\tQ8, Q9, [SP], #0x20\n\tLDP\t\tQ6, Q7, [SP], #0x20\n\tLDP\t\tQ4, Q5, [SP], #0x20\n\tLDP\t\tQ2, Q3, [SP], #0x20\n\tLDP\t\tQ0, Q1, [SP], #0x20\n1:\n\tLDP \tX2, X3, [SP], #0x10  /* SPSR and ELR. */\n\n#if defined( GUEST )\n\t/* Restore the SPSR. */\n\tMSR\t\tSPSR_EL1, X3\n\t/* Restore the ELR. */\n\tMSR\t\tELR_EL1, X2\n#else\n\t/* Restore the SPSR. */\n\tMSR\t\tSPSR_EL3, X3 /*_RB_ Assumes started in EL3. */\n\t/* Restore the ELR. */\n\tMSR\t\tELR_EL3, X2\n#endif\n\n\tLDP \tX30, XZR, [SP], #0x10\n\tLDP \tX28, X29, [SP], #0x10\n\tLDP \tX26, X27, [SP], #0x10\n\tLDP \tX24, X25, [SP], #0x10\n\tLDP \tX22, X23, [SP], #0x10\n\tLDP \tX20, X21, [SP], #0x10\n\tLDP \tX18, X19, [SP], #0x10\n\tLDP \tX16, X17, [SP], #0x10\n\tLDP \tX14, X15, [SP], #0x10\n\tLDP \tX12, X13, [SP], #0x10\n\tLDP \tX10, X11, [SP], #0x10\n\tLDP \tX8, X9, [SP], #0x10\n\tLDP \tX6, X7, [SP], #0x10\n\tLDP \tX4, X5, [SP], #0x10\n\tLDP \tX2, X3, [SP], #0x10\n\tLDP \tX0, X1, [SP], #0x10\n\n\t/* Switch to use the ELx stack pointer.  _RB_ Might not be required. */\n\tMSR \tSPSEL, #1\n\n\tERET\n\n\t.endm\n\n\n/******************************************************************************\n * FreeRTOS_SWI_Handler handler is used to perform a context switch.\n *****************************************************************************/\n.align 8\n.type FreeRTOS_SWI_Handler, %function\nFreeRTOS_SWI_Handler:\n\t/* Save the context of the current task and select a new task to run. */\n\tportSAVE_CONTEXT\n#if defined( GUEST )\n\tMRS\t\tX0, ESR_EL1\n#else\n\tMRS\t\tX0, ESR_EL3\n#endif\n\n\tLSR\t\tX1, X0, #26\n\n#if defined( GUEST )\n\tCMP\t\tX1, #0x15 \t/* 0x15 = SVC instruction. */\n#else\n\tCMP\t\tX1, #0x17 \t/* 0x17 = SMC instruction. */\n#endif\n\tB.NE\tFreeRTOS_Abort\n\tBL \t\tvTaskSwitchContext\n\n\tportRESTORE_CONTEXT\n\nFreeRTOS_Abort:\n\t/* Full ESR is in X0, exception class code is in X1. */\n\tB\t\t.\n\n/******************************************************************************\n * vPortRestoreTaskContext is used to start the scheduler.\n *****************************************************************************/\n.align 8\n.type vPortRestoreTaskContext, %function\nvPortRestoreTaskContext:\n.set freertos_vector_base,\t_freertos_vector_table\n\n\t/* Install the FreeRTOS interrupt handlers. */\n\tLDR\t\tX1, =freertos_vector_base\n#if defined( GUEST )\n\tMSR\t\tVBAR_EL1, X1\n#else\n\tMSR\t\tVBAR_EL3, X1\n#endif\n\tDSB\t\tSY\n\tISB\t\tSY\n\n\t/* Start the first task. */\n\tportRESTORE_CONTEXT\n\n\n/******************************************************************************\n * FreeRTOS_IRQ_Handler handles IRQ entry and exit.\n\n * This handler is supposed to be used only for IRQs and never for FIQs. Per ARM\n * GIC documentation [1], Group 0 interrupts are always signaled as FIQs. Since\n * this handler is only for IRQs, We can safely assume Group 1 while accessing\n * Interrupt Acknowledge and End Of Interrupt registers and therefore, use\n * ICC_IAR1_EL1 and ICC_EOIR1_EL1.\n *\n * [1] https://developer.arm.com/documentation/198123/0300/Arm-CoreLink-GIC-fundamentals\n *****************************************************************************/\n.align 8\n.type FreeRTOS_IRQ_Handler, %function\nFreeRTOS_IRQ_Handler:\n\t/* Save volatile registers. */\n\tSTP\t\tX0, X1, [SP, #-0x10]!\n\tSTP\t\tX2, X3, [SP, #-0x10]!\n\tSTP\t\tX4, X5, [SP, #-0x10]!\n\tSTP\t\tX6, X7, [SP, #-0x10]!\n\tSTP\t\tX8, X9, [SP, #-0x10]!\n\tSTP\t\tX10, X11, [SP, #-0x10]!\n\tSTP\t\tX12, X13, [SP, #-0x10]!\n\tSTP\t\tX14, X15, [SP, #-0x10]!\n\tSTP\t\tX16, X17, [SP, #-0x10]!\n\tSTP\t\tX18, X19, [SP, #-0x10]!\n\tSTP\t\tX29, X30, [SP, #-0x10]!\n\n\t/* Save the SPSR and ELR. */\n#if defined( GUEST )\n\tMRS\t\tX3, SPSR_EL1\n\tMRS\t\tX2, ELR_EL1\n#else\n\tMRS\t\tX3, SPSR_EL3\n\tMRS\t\tX2, ELR_EL3\n#endif\n\tSTP \tX2, X3, [SP, #-0x10]!\n\n\t/* Increment the interrupt nesting counter. */\n\tLDR\t\tX5, ullPortInterruptNestingConst\n\tLDR\t\tX1, [X5]\t/* Old nesting count in X1. */\n\tADD\t\tX6, X1, #1\n\tSTR\t\tX6, [X5]\t/* Address of nesting count variable in X5. */\n\n\t/* Maintain the interrupt nesting information across the function call. */\n\tSTP\t\tX1, X5, [SP, #-0x10]!\n\n\t/* Read interrupt ID from the interrupt acknowledge register and store it\n\tin X0 for future parameter and interrupt clearing use. */\n\tMRS\t\tX0, S3_0_C12_C12_0\t/* S3_0_C12_C12_0 is ICC_IAR1_EL1. */\n\n\t/* Maintain the interrupt ID value across the function call. */\n\tSTP\t\tX0, X1, [SP, #-0x10]!\n\n\t/* Call the C handler. */\n\tBL vApplicationIRQHandler\n\n\t/* Disable interrupts. */\n\tMSR \tDAIFSET, #2\n\tDSB\t\tSY\n\tISB\t\tSY\n\n\t/* Restore the interrupt ID value. */\n\tLDP\t\tX0, X1, [SP], #0x10\n\n\t/* End IRQ processing by writing interrupt ID value to the EOI register. */\n\tMSR\t\tS3_0_C12_C12_1, X0\t/* S3_0_C12_C12_1 is ICC_EOIR1_EL1. */\n\n\t/* Restore the critical nesting count. */\n\tLDP\t\tX1, X5, [SP], #0x10\n\tSTR\t\tX1, [X5]\n\n\t/* Has interrupt nesting unwound? */\n\tCMP\t\tX1, #0\n\tB.NE\tExit_IRQ_No_Context_Switch\n\n\t/* Is a context switch required? */\n\tLDR\t\tX0, ullPortYieldRequiredConst\n\tLDR\t\tX1, [X0]\n\tCMP\t\tX1, #0\n\tB.EQ\tExit_IRQ_No_Context_Switch\n\n\t/* Reset ullPortYieldRequired to 0. */\n\tMOV\t\tX2, #0\n\tSTR\t\tX2, [X0]\n\n\t/* Restore volatile registers. */\n\tLDP \tX4, X5, [SP], #0x10  /* SPSR and ELR. */\n#if defined( GUEST )\n\tMSR\t\tSPSR_EL1, X5\n\tMSR\t\tELR_EL1, X4\n#else\n\tMSR\t\tSPSR_EL3, X5 /*_RB_ Assumes started in EL3. */\n\tMSR\t\tELR_EL3, X4\n#endif\n\tDSB\t\tSY\n\tISB\t\tSY\n\n\tLDP\t\tX29, X30, [SP], #0x10\n\tLDP\t\tX18, X19, [SP], #0x10\n\tLDP\t\tX16, X17, [SP], #0x10\n\tLDP\t\tX14, X15, [SP], #0x10\n\tLDP\t\tX12, X13, [SP], #0x10\n\tLDP\t\tX10, X11, [SP], #0x10\n\tLDP\t\tX8, X9, [SP], #0x10\n\tLDP\t\tX6, X7, [SP], #0x10\n\tLDP\t\tX4, X5, [SP], #0x10\n\tLDP\t\tX2, X3, [SP], #0x10\n\tLDP\t\tX0, X1, [SP], #0x10\n\n\t/* Save the context of the current task and select a new task to run. */\n\tportSAVE_CONTEXT\n\tBL vTaskSwitchContext\n\tportRESTORE_CONTEXT\n\nExit_IRQ_No_Context_Switch:\n\t/* Restore volatile registers. */\n\tLDP \tX4, X5, [SP], #0x10  /* SPSR and ELR. */\n#if defined( GUEST )\n\tMSR\t\tSPSR_EL1, X5\n\tMSR\t\tELR_EL1, X4\n#else\n\tMSR\t\tSPSR_EL3, X5 /*_RB_ Assumes started in EL3. */\n\tMSR\t\tELR_EL3, X4\n#endif\n\tDSB\t\tSY\n\tISB\t\tSY\n\n\tLDP\t\tX29, X30, [SP], #0x10\n\tLDP\t\tX18, X19, [SP], #0x10\n\tLDP\t\tX16, X17, [SP], #0x10\n\tLDP\t\tX14, X15, [SP], #0x10\n\tLDP\t\tX12, X13, [SP], #0x10\n\tLDP\t\tX10, X11, [SP], #0x10\n\tLDP\t\tX8, X9, [SP], #0x10\n\tLDP\t\tX6, X7, [SP], #0x10\n\tLDP\t\tX4, X5, [SP], #0x10\n\tLDP\t\tX2, X3, [SP], #0x10\n\tLDP\t\tX0, X1, [SP], #0x10\n\n\tERET\n\n\n\n\n.align 8\npxCurrentTCBConst: .dword pxCurrentTCB\nullCriticalNestingConst: .dword ullCriticalNesting\nullPortTaskHasFPUContextConst: .dword ullPortTaskHasFPUContext\n\nullMaxAPIPriorityMaskConst: .dword ullMaxAPIPriorityMask\nullPortInterruptNestingConst: .dword ullPortInterruptNesting\nullPortYieldRequiredConst: .dword ullPortYieldRequired\n\n.end\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CA53_64_BIT_SRE/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef PORTMACRO_H\n#define PORTMACRO_H\n\n#ifdef __cplusplus\n\textern \"C\" {\n#endif\n\n/*-----------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the given hardware\n * and compiler.\n *\n * These settings should not be altered.\n *-----------------------------------------------------------\n */\n\n/* Type definitions. */\n#define portCHAR\t\tchar\n#define portFLOAT\t\tfloat\n#define portDOUBLE\t\tdouble\n#define portLONG\t\tlong\n#define portSHORT\t\tshort\n#define portSTACK_TYPE\tsize_t\n#define portBASE_TYPE\tlong\n\ntypedef portSTACK_TYPE StackType_t;\ntypedef portBASE_TYPE BaseType_t;\ntypedef uint64_t UBaseType_t;\n\ntypedef uint64_t TickType_t;\n#define portMAX_DELAY ( ( TickType_t ) 0xffffffffffffffff )\n\n/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\nnot need to be guarded with a critical section. */\n#define portTICK_TYPE_IS_ATOMIC 1\n\n/*-----------------------------------------------------------*/\n\n/* Hardware specifics. */\n#define portSTACK_GROWTH\t\t\t( -1 )\n#define portTICK_PERIOD_MS\t\t\t( ( TickType_t ) 1000 / configTICK_RATE_HZ )\n#define portBYTE_ALIGNMENT\t\t\t16\n#define portPOINTER_SIZE_TYPE \t\tuint64_t\n\n/*-----------------------------------------------------------*/\n\n/* Task utilities. */\n\n/* Called at the end of an ISR that can cause a context switch. */\n#define portEND_SWITCHING_ISR( xSwitchRequired )\\\n{\t\t\t\t\t\t\t\t\t\t\t\t\\\nextern uint64_t ullPortYieldRequired;\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tif( xSwitchRequired != pdFALSE )\t\t\t\\\n\t{\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tullPortYieldRequired = pdTRUE;\t\t\t\\\n\t}\t\t\t\t\t\t\t\t\t\t\t\\\n}\n\n#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\n#if defined( GUEST )\n\t#define portYIELD() __asm volatile ( \"SVC 0\" ::: \"memory\" )\n#else\n\t#define portYIELD() __asm volatile ( \"SMC 0\" ::: \"memory\" )\n#endif\n/*-----------------------------------------------------------\n * Critical section control\n *----------------------------------------------------------*/\n\nextern void vPortEnterCritical( void );\nextern void vPortExitCritical( void );\nextern UBaseType_t uxPortSetInterruptMask( void );\nextern void vPortClearInterruptMask( UBaseType_t uxNewMaskValue );\nextern void vPortInstallFreeRTOSVectorTable( void );\n\n#define portDISABLE_INTERRUPTS()\t\t\t\t\t\t\t\t\t\\\n\t__asm volatile ( \"MSR DAIFSET, #2\" ::: \"memory\" );\t\t\t\t\\\n\t__asm volatile ( \"DSB SY\" );\t\t\t\t\t\t\t\t\t\\\n\t__asm volatile ( \"ISB SY\" );\n\n#define portENABLE_INTERRUPTS()\t\t\t\t\t\t\t\t\t\t\\\n\t__asm volatile ( \"MSR DAIFCLR, #2\" ::: \"memory\" );\t\t\t\t\\\n\t__asm volatile ( \"DSB SY\" );\t\t\t\t\t\t\t\t\t\\\n\t__asm volatile ( \"ISB SY\" );\n\n\n/* These macros do not globally disable/enable interrupts.  They do mask off\ninterrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */\n#define portENTER_CRITICAL()\t\tvPortEnterCritical();\n#define portEXIT_CRITICAL()\t\t\tvPortExitCritical();\n#define portSET_INTERRUPT_MASK_FROM_ISR()\t\tuxPortSetInterruptMask()\n#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)\tvPortClearInterruptMask(x)\n\n/*-----------------------------------------------------------*/\n\n/* Task function macros as described on the FreeRTOS.org WEB site.  These are\nnot required for this port but included in case common demo code that uses these\nmacros is used. */\n#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )\tvoid vFunction( void *pvParameters )\n#define portTASK_FUNCTION( vFunction, pvParameters )\tvoid vFunction( void *pvParameters )\n\n/* Prototype of the FreeRTOS tick handler.  This must be installed as the\nhandler for whichever peripheral is used to generate the RTOS tick. */\nvoid FreeRTOS_Tick_Handler( void );\n\n/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()\nbefore any floating point instructions are executed. */\nvoid vPortTaskUsesFPU( void );\n#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()\n\n#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )\n#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )\n\n/* Architecture specific optimisations. */\n#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION\n\t#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1\n#endif\n\n#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1\n\n\t/* Store/clear the ready priorities in a bit map. */\n\t#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )\n\t#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )\n\n\t/*-----------------------------------------------------------*/\n\n\t#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __builtin_clz( uxReadyPriorities ) )\n\n#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */\n\n#ifdef configASSERT\n\tvoid vPortValidateInterruptPriority( void );\n\t#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() \tvPortValidateInterruptPriority()\n#endif /* configASSERT */\n\n#define portNOP() __asm volatile( \"NOP\" )\n#define portINLINE __inline\n\n#ifdef __cplusplus\n\t} /* extern C */\n#endif\n\n\n/* The number of bits to shift for an interrupt priority is dependent on the\nnumber of bits implemented by the interrupt controller. */\n#if configUNIQUE_INTERRUPT_PRIORITIES == 16\n\t#define portPRIORITY_SHIFT 4\n\t#define portMAX_BINARY_POINT_VALUE\t3\n#elif configUNIQUE_INTERRUPT_PRIORITIES == 32\n\t#define portPRIORITY_SHIFT 3\n\t#define portMAX_BINARY_POINT_VALUE\t2\n#elif configUNIQUE_INTERRUPT_PRIORITIES == 64\n\t#define portPRIORITY_SHIFT 2\n\t#define portMAX_BINARY_POINT_VALUE\t1\n#elif configUNIQUE_INTERRUPT_PRIORITIES == 128\n\t#define portPRIORITY_SHIFT 1\n\t#define portMAX_BINARY_POINT_VALUE\t0\n#elif configUNIQUE_INTERRUPT_PRIORITIES == 256\n\t#define portPRIORITY_SHIFT 0\n\t#define portMAX_BINARY_POINT_VALUE\t0\n#else\n\t#error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting.  configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware\n#endif\n\n#define portMEMORY_BARRIER() __asm volatile( \"\" ::: \"memory\" )\n\n#endif /* PORTMACRO_H */\n\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CA9/port.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Standard includes. */\n#include <stdlib.h>\n#include <string.h>\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n#ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS\n\t#error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html\n#endif\n\n#ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET\n\t#error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html\n#endif\n\n#ifndef configUNIQUE_INTERRUPT_PRIORITIES\n\t#error configUNIQUE_INTERRUPT_PRIORITIES must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html\n#endif\n\n#ifndef configSETUP_TICK_INTERRUPT\n\t#error configSETUP_TICK_INTERRUPT() must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html\n#endif /* configSETUP_TICK_INTERRUPT */\n\n#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY\n\t#error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html\n#endif\n\n#if configMAX_API_CALL_INTERRUPT_PRIORITY == 0\n\t#error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0\n#endif\n\n#if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES\n\t#error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority\n#endif\n\n#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1\n\t/* Check the configuration. */\n\t#if( configMAX_PRIORITIES > 32 )\n\t\t#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.\n\t#endif\n#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */\n\n/* In case security extensions are implemented. */\n#if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )\n\t#error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )\n#endif\n\n/* Some vendor specific files default configCLEAR_TICK_INTERRUPT() in\nportmacro.h. */\n#ifndef configCLEAR_TICK_INTERRUPT\n\t#define configCLEAR_TICK_INTERRUPT()\n#endif\n\n/* A critical section is exited when the critical section nesting count reaches\nthis value. */\n#define portNO_CRITICAL_NESTING\t\t\t( ( uint32_t ) 0 )\n\n/* In all GICs 255 can be written to the priority mask register to unmask all\n(but the lowest) interrupt priority. */\n#define portUNMASK_VALUE\t\t\t\t( 0xFFUL )\n\n/* Tasks are not created with a floating point context, but can be given a\nfloating point context after they have been created.  A variable is stored as\npart of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task\ndoes not have an FPU context, or any other value if the task does have an FPU\ncontext. */\n#define portNO_FLOATING_POINT_CONTEXT\t( ( StackType_t ) 0 )\n\n/* Constants required to setup the initial task context. */\n#define portINITIAL_SPSR\t\t\t\t( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */\n#define portTHUMB_MODE_BIT\t\t\t\t( ( StackType_t ) 0x20 )\n#define portINTERRUPT_ENABLE_BIT\t\t( 0x80UL )\n#define portTHUMB_MODE_ADDRESS\t\t\t( 0x01UL )\n\n/* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary\npoint is zero. */\n#define portBINARY_POINT_BITS\t\t\t( ( uint8_t ) 0x03 )\n\n/* Masks all bits in the APSR other than the mode bits. */\n#define portAPSR_MODE_BITS_MASK\t\t\t( 0x1F )\n\n/* The value of the mode bits in the APSR when the CPU is executing in user\nmode. */\n#define portAPSR_USER_MODE\t\t\t\t( 0x10 )\n\n/* The critical section macros only mask interrupts up to an application\ndetermined priority level.  Sometimes it is necessary to turn interrupt off in\nthe CPU itself before modifying certain hardware registers. */\n#define portCPU_IRQ_DISABLE()\t\t\t\t\t\t\t\t\t\t\\\n\t__asm volatile ( \"CPSID i\" ::: \"memory\" );\t\t\t\t\t\t\\\n\t__asm volatile ( \"DSB\" );\t\t\t\t\t\t\t\t\t\t\\\n\t__asm volatile ( \"ISB\" );\n\n#define portCPU_IRQ_ENABLE()\t\t\t\t\t\t\t\t\t\t\\\n\t__asm volatile ( \"CPSIE i\" ::: \"memory\" );\t\t\t\t\t\t\\\n\t__asm volatile ( \"DSB\" );\t\t\t\t\t\t\t\t\t\t\\\n\t__asm volatile ( \"ISB\" );\n\n\n/* Macro to unmask all interrupt priorities. */\n#define portCLEAR_INTERRUPT_MASK()\t\t\t\t\t\t\t\t\t\\\n{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tportCPU_IRQ_DISABLE();\t\t\t\t\t\t\t\t\t\t\t\\\n\tportICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE;\t\t\t\\\n\t__asm volatile (\t\"DSB\t\t\\n\"\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\"ISB\t\t\\n\" );\t\t\t\t\t\t\t\\\n\tportCPU_IRQ_ENABLE();\t\t\t\t\t\t\t\t\t\t\t\\\n}\n\n#define portINTERRUPT_PRIORITY_REGISTER_OFFSET\t\t0x400UL\n#define portMAX_8_BIT_VALUE\t\t\t\t\t\t\t( ( uint8_t ) 0xff )\n#define portBIT_0_SET\t\t\t\t\t\t\t\t( ( uint8_t ) 0x01 )\n\n/* Let the user override the pre-loading of the initial LR with the address of\nprvTaskExitError() in case it messes up unwinding of the stack in the\ndebugger. */\n#ifdef configTASK_RETURN_ADDRESS\n\t#define portTASK_RETURN_ADDRESS\tconfigTASK_RETURN_ADDRESS\n#else\n\t#define portTASK_RETURN_ADDRESS\tprvTaskExitError\n#endif\n\n/* The space on the stack required to hold the FPU registers.  This is 32 64-bit\nregisters, plus a 32-bit status register. */\n#define portFPU_REGISTER_WORDS\t( ( 32 * 2 ) + 1 )\n\n/*-----------------------------------------------------------*/\n\n/*\n * Starts the first task executing.  This function is necessarily written in\n * assembly code so is implemented in portASM.s.\n */\nextern void vPortRestoreTaskContext( void );\n\n/*\n * Used to catch tasks that attempt to return from their implementing function.\n */\nstatic void prvTaskExitError( void );\n\n/*\n * If the application provides an implementation of vApplicationIRQHandler(),\n * then it will get called directly without saving the FPU registers on\n * interrupt entry, and this weak implementation of\n * vApplicationFPUSafeIRQHandler() is just provided to remove linkage errors -\n * it should never actually get called so its implementation contains a\n * call to configASSERT() that will always fail.\n *\n * If the application provides its own implementation of\n * vApplicationFPUSafeIRQHandler() then the implementation of\n * vApplicationIRQHandler() provided in portASM.S will save the FPU registers\n * before calling it.\n *\n * Therefore, if the application writer wants FPU registers to be saved on\n * interrupt entry their IRQ handler must be called\n * vApplicationFPUSafeIRQHandler(), and if the application writer does not want\n * FPU registers to be saved on interrupt entry their IRQ handler must be\n * called vApplicationIRQHandler().\n */\nvoid vApplicationFPUSafeIRQHandler( uint32_t ulICCIAR ) __attribute__((weak) );\n\n/*-----------------------------------------------------------*/\n\n/* A variable is used to keep track of the critical section nesting.  This\nvariable has to be stored as part of the task context and must be initialised to\na non zero value to ensure interrupts don't inadvertently become unmasked before\nthe scheduler starts.  As it is stored as part of the task context it will\nautomatically be set to 0 when the first task is started. */\nvolatile uint32_t ulCriticalNesting = 9999UL;\n\n/* Saved as part of the task context.  If ulPortTaskHasFPUContext is non-zero then\na floating point context must be saved and restored for the task. */\nvolatile uint32_t ulPortTaskHasFPUContext = pdFALSE;\n\n/* Set to 1 to pend a context switch from an ISR. */\nvolatile uint32_t ulPortYieldRequired = pdFALSE;\n\n/* Counts the interrupt nesting depth.  A context switch is only performed if\nif the nesting depth is 0. */\nvolatile uint32_t ulPortInterruptNesting = 0UL;\n\n/* Used in the asm file. */\n__attribute__(( used )) const uint32_t ulICCIAR = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS;\n__attribute__(( used )) const uint32_t ulICCEOIR = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS;\n__attribute__(( used )) const uint32_t ulICCPMR\t= portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS;\n__attribute__(( used )) const uint32_t ulMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );\n\n/*-----------------------------------------------------------*/\n\n/*\n * See header file for description.\n */\nStackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )\n{\n\t/* Setup the initial stack of the task.  The stack is set exactly as\n\texpected by the portRESTORE_CONTEXT() macro.\n\n\tThe fist real value on the stack is the status register, which is set for\n\tsystem mode, with interrupts enabled.  A few NULLs are added first to ensure\n\tGDB does not try decoding a non-existent return address. */\n\t*pxTopOfStack = ( StackType_t ) NULL;\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) NULL;\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) NULL;\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;\n\n\tif( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )\n\t{\n\t\t/* The task will start in THUMB mode. */\n\t\t*pxTopOfStack |= portTHUMB_MODE_BIT;\n\t}\n\n\tpxTopOfStack--;\n\n\t/* Next the return address, which in this case is the start of the task. */\n\t*pxTopOfStack = ( StackType_t ) pxCode;\n\tpxTopOfStack--;\n\n\t/* Next all the registers other than the stack pointer. */\n\t*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;\t/* R14 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x12121212;\t/* R12 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x11111111;\t/* R11 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x10101010;\t/* R10 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x09090909;\t/* R9 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x08080808;\t/* R8 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x07070707;\t/* R7 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x06060606;\t/* R6 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x05050505;\t/* R5 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x04040404;\t/* R4 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x03030303;\t/* R3 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x02020202;\t/* R2 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x01010101;\t/* R1 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\n\tpxTopOfStack--;\n\n\t/* The task will start with a critical nesting count of 0 as interrupts are\n\tenabled. */\n\t*pxTopOfStack = portNO_CRITICAL_NESTING;\n\n\t#if( configUSE_TASK_FPU_SUPPORT == 1 )\n\t{\n\t\t/* The task will start without a floating point context.  A task that\n\t\tuses the floating point hardware must call vPortTaskUsesFPU() before\n\t\texecuting any floating point instructions. */\n\t\tpxTopOfStack--;\n\t\t*pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;\n\t}\n\t#elif( configUSE_TASK_FPU_SUPPORT == 2 )\n\t{\n\t\t/* The task will start with a floating point context.  Leave enough\n\t\tspace for the registers - and ensure they are initialised to 0. */\n\t\tpxTopOfStack -= portFPU_REGISTER_WORDS;\n\t\tmemset( pxTopOfStack, 0x00, portFPU_REGISTER_WORDS * sizeof( StackType_t ) );\n\n\t\tpxTopOfStack--;\n\t\t*pxTopOfStack = pdTRUE;\n\t\tulPortTaskHasFPUContext = pdTRUE;\n\t}\n\t#else\n\t{\n\t\t#error Invalid configUSE_TASK_FPU_SUPPORT setting - configUSE_TASK_FPU_SUPPORT must be set to 1, 2, or left undefined.\n\t}\n\t#endif\n\n\treturn pxTopOfStack;\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvTaskExitError( void )\n{\n\t/* A function that implements a task must not exit or attempt to return to\n\tits caller as there is nothing to return to.  If a task wants to exit it\n\tshould instead call vTaskDelete( NULL ).\n\n\tArtificially force an assert() to be triggered if configASSERT() is\n\tdefined, then stop here so application writers can catch the error. */\n\tconfigASSERT( ulPortInterruptNesting == ~0UL );\n\tportDISABLE_INTERRUPTS();\n\tfor( ;; );\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xPortStartScheduler( void )\n{\nuint32_t ulAPSR;\n\n\t#if( configASSERT_DEFINED == 1 )\n\t{\n\t\tvolatile uint32_t ulOriginalPriority;\n\t\tvolatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + portINTERRUPT_PRIORITY_REGISTER_OFFSET );\n\t\tvolatile uint8_t ucMaxPriorityValue;\n\n\t\t/* Determine how many priority bits are implemented in the GIC.\n\n\t\tSave the interrupt priority value that is about to be clobbered. */\n\t\tulOriginalPriority = *pucFirstUserPriorityRegister;\n\n\t\t/* Determine the number of priority bits available.  First write to\n\t\tall possible bits. */\n\t\t*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\n\n\t\t/* Read the value back to see how many bits stuck. */\n\t\tucMaxPriorityValue = *pucFirstUserPriorityRegister;\n\n\t\t/* Shift to the least significant bits. */\n\t\twhile( ( ucMaxPriorityValue & portBIT_0_SET ) != portBIT_0_SET )\n\t\t{\n\t\t\tucMaxPriorityValue >>= ( uint8_t ) 0x01;\n\t\t}\n\n\t\t/* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read\n\t\tvalue. */\n\t\tconfigASSERT( ucMaxPriorityValue == portLOWEST_INTERRUPT_PRIORITY );\n\n\t\t/* Restore the clobbered interrupt priority register to its original\n\t\tvalue. */\n\t\t*pucFirstUserPriorityRegister = ulOriginalPriority;\n\t}\n\t#endif /* configASSERT_DEFINED */\n\n\n\t/* Only continue if the CPU is not in User mode.  The CPU must be in a\n\tPrivileged mode for the scheduler to start. */\n\t__asm volatile ( \"MRS %0, APSR\" : \"=r\" ( ulAPSR ) :: \"memory\" );\n\tulAPSR &= portAPSR_MODE_BITS_MASK;\n\tconfigASSERT( ulAPSR != portAPSR_USER_MODE );\n\n\tif( ulAPSR != portAPSR_USER_MODE )\n\t{\n\t\t/* Only continue if the binary point value is set to its lowest possible\n\t\tsetting.  See the comments in vPortValidateInterruptPriority() below for\n\t\tmore information. */\n\t\tconfigASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );\n\n\t\tif( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )\n\t\t{\n\t\t\t/* Interrupts are turned off in the CPU itself to ensure tick does\n\t\t\tnot execute\twhile the scheduler is being started.  Interrupts are\n\t\t\tautomatically turned back on in the CPU when the first task starts\n\t\t\texecuting. */\n\t\t\tportCPU_IRQ_DISABLE();\n\n\t\t\t/* Start the timer that generates the tick ISR. */\n\t\t\tconfigSETUP_TICK_INTERRUPT();\n\n\t\t\t/* Start the first task executing. */\n\t\t\tvPortRestoreTaskContext();\n\t\t}\n\t}\n\n\t/* Will only get here if vTaskStartScheduler() was called with the CPU in\n\ta non-privileged mode or the binary point register was not set to its lowest\n\tpossible value.  prvTaskExitError() is referenced to prevent a compiler\n\twarning about it being defined but not referenced in the case that the user\n\tdefines their own exit address. */\n\t( void ) prvTaskExitError;\n\treturn 0;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEndScheduler( void )\n{\n\t/* Not implemented in ports where there is nothing to return to.\n\tArtificially force an assert. */\n\tconfigASSERT( ulCriticalNesting == 1000UL );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEnterCritical( void )\n{\n\t/* Mask interrupts up to the max syscall interrupt priority. */\n\tulPortSetInterruptMask();\n\n\t/* Now interrupts are disabled ulCriticalNesting can be accessed\n\tdirectly.  Increment ulCriticalNesting to keep a count of how many times\n\tportENTER_CRITICAL() has been called. */\n\tulCriticalNesting++;\n\n\t/* This is not the interrupt safe version of the enter critical function so\n\tassert() if it is being called from an interrupt context.  Only API\n\tfunctions that end in \"FromISR\" can be used in an interrupt.  Only assert if\n\tthe critical nesting count is 1 to protect against recursive calls if the\n\tassert function also uses a critical section. */\n\tif( ulCriticalNesting == 1 )\n\t{\n\t\tconfigASSERT( ulPortInterruptNesting == 0 );\n\t}\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortExitCritical( void )\n{\n\tif( ulCriticalNesting > portNO_CRITICAL_NESTING )\n\t{\n\t\t/* Decrement the nesting count as the critical section is being\n\t\texited. */\n\t\tulCriticalNesting--;\n\n\t\t/* If the nesting level has reached zero then all interrupt\n\t\tpriorities must be re-enabled. */\n\t\tif( ulCriticalNesting == portNO_CRITICAL_NESTING )\n\t\t{\n\t\t\t/* Critical nesting has reached zero so all interrupt priorities\n\t\t\tshould be unmasked. */\n\t\t\tportCLEAR_INTERRUPT_MASK();\n\t\t}\n\t}\n}\n/*-----------------------------------------------------------*/\n\nvoid FreeRTOS_Tick_Handler( void )\n{\n\t/* Set interrupt mask before altering scheduler structures.   The tick\n\thandler runs at the lowest priority, so interrupts cannot already be masked,\n\tso there is no need to save and restore the current mask value.  It is\n\tnecessary to turn off interrupts in the CPU itself while the ICCPMR is being\n\tupdated. */\n\tportCPU_IRQ_DISABLE();\n\tportICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );\n\t__asm volatile (\t\"dsb\t\t\\n\"\n\t\t\t\t\t\t\"isb\t\t\\n\" ::: \"memory\" );\n\tportCPU_IRQ_ENABLE();\n\n\t/* Increment the RTOS tick. */\n\tif( xTaskIncrementTick() != pdFALSE )\n\t{\n\t\tulPortYieldRequired = pdTRUE;\n\t}\n\n\t/* Ensure all interrupt priorities are active again. */\n\tportCLEAR_INTERRUPT_MASK();\n\tconfigCLEAR_TICK_INTERRUPT();\n}\n/*-----------------------------------------------------------*/\n\n#if( configUSE_TASK_FPU_SUPPORT != 2 )\n\n\tvoid vPortTaskUsesFPU( void )\n\t{\n\tuint32_t ulInitialFPSCR = 0;\n\n\t\t/* A task is registering the fact that it needs an FPU context.  Set the\n\t\tFPU flag (which is saved as part of the task context). */\n\t\tulPortTaskHasFPUContext = pdTRUE;\n\n\t\t/* Initialise the floating point status register. */\n\t\t__asm volatile ( \"FMXR \tFPSCR, %0\" :: \"r\" (ulInitialFPSCR) : \"memory\" );\n\t}\n\n#endif /* configUSE_TASK_FPU_SUPPORT */\n/*-----------------------------------------------------------*/\n\nvoid vPortClearInterruptMask( uint32_t ulNewMaskValue )\n{\n\tif( ulNewMaskValue == pdFALSE )\n\t{\n\t\tportCLEAR_INTERRUPT_MASK();\n\t}\n}\n/*-----------------------------------------------------------*/\n\nuint32_t ulPortSetInterruptMask( void )\n{\nuint32_t ulReturn;\n\n\t/* Interrupt in the CPU must be turned off while the ICCPMR is being\n\tupdated. */\n\tportCPU_IRQ_DISABLE();\n\tif( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )\n\t{\n\t\t/* Interrupts were already masked. */\n\t\tulReturn = pdTRUE;\n\t}\n\telse\n\t{\n\t\tulReturn = pdFALSE;\n\t\tportICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );\n\t\t__asm volatile (\t\"dsb\t\t\\n\"\n\t\t\t\t\t\t\t\"isb\t\t\\n\" ::: \"memory\" );\n\t}\n\tportCPU_IRQ_ENABLE();\n\n\treturn ulReturn;\n}\n/*-----------------------------------------------------------*/\n\n#if( configASSERT_DEFINED == 1 )\n\n\tvoid vPortValidateInterruptPriority( void )\n\t{\n\t\t/* The following assertion will fail if a service routine (ISR) for\n\t\tan interrupt that has been assigned a priority above\n\t\tconfigMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\n\t\tfunction.  ISR safe FreeRTOS API functions must *only* be called\n\t\tfrom interrupts that have been assigned a priority at or below\n\t\tconfigMAX_SYSCALL_INTERRUPT_PRIORITY.\n\n\t\tNumerically low interrupt priority numbers represent logically high\n\t\tinterrupt priorities, therefore the priority of the interrupt must\n\t\tbe set to a value equal to or numerically *higher* than\n\t\tconfigMAX_SYSCALL_INTERRUPT_PRIORITY.\n\n\t\tFreeRTOS maintains separate thread and ISR API functions to ensure\n\t\tinterrupt entry is as fast and simple as possible. */\n\t\tconfigASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );\n\n\t\t/* Priority grouping:  The interrupt controller (GIC) allows the bits\n\t\tthat define each interrupt's priority to be split between bits that\n\t\tdefine the interrupt's pre-emption priority bits and bits that define\n\t\tthe interrupt's sub-priority.  For simplicity all bits must be defined\n\t\tto be pre-emption priority bits.  The following assertion will fail if\n\t\tthis is not the case (if some bits represent a sub-priority).\n\n\t\tThe priority grouping is configured by the GIC's binary point register\n\t\t(ICCBPR).  Writting 0 to ICCBPR will ensure it is set to its lowest\n\t\tpossible value (which may be above 0). */\n\t\tconfigASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );\n\t}\n\n#endif /* configASSERT_DEFINED */\n/*-----------------------------------------------------------*/\n\nvoid vApplicationFPUSafeIRQHandler( uint32_t ulICCIAR )\n{\n\t( void ) ulICCIAR;\n\tconfigASSERT( ( volatile void * ) NULL );\n}\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CA9/portASM.S",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\t.eabi_attribute Tag_ABI_align_preserved, 1\n\t.text\n\t.arm\n\n\t.set SYS_MODE,\t0x1f\n\t.set SVC_MODE,\t0x13\n\t.set IRQ_MODE,\t0x12\n\n\t/* Hardware registers. */\n\t.extern ulICCIAR\n\t.extern ulICCEOIR\n\t.extern ulICCPMR\n\n\t/* Variables and functions. */\n\t.extern ulMaxAPIPriorityMask\n\t.extern _freertos_vector_table\n\t.extern pxCurrentTCB\n\t.extern vTaskSwitchContext\n\t.extern vApplicationIRQHandler\n\t.extern ulPortInterruptNesting\n\t.extern ulPortTaskHasFPUContext\n\n\t.global FreeRTOS_IRQ_Handler\n\t.global FreeRTOS_SWI_Handler\n\t.global vPortRestoreTaskContext\n\n\n\n\n.macro portSAVE_CONTEXT\n\n\t/* Save the LR and SPSR onto the system mode stack before switching to\n\tsystem mode to save the remaining system mode registers. */\n\tSRSDB\tsp!, #SYS_MODE\n\tCPS\t\t#SYS_MODE\n\tPUSH\t{R0-R12, R14}\n\n\t/* Push the critical nesting count. */\n\tLDR\t\tR2, ulCriticalNestingConst\n\tLDR\t\tR1, [R2]\n\tPUSH\t{R1}\n\n\t/* Does the task have a floating point context that needs saving?  If\n\tulPortTaskHasFPUContext is 0 then no. */\n\tLDR\t\tR2, ulPortTaskHasFPUContextConst\n\tLDR\t\tR3, [R2]\n\tCMP\t\tR3, #0\n\n\t/* Save the floating point context, if any. */\n\tFMRXNE  R1,  FPSCR\n\tVPUSHNE {D0-D15}\n\tVPUSHNE\t{D16-D31}\n\tPUSHNE\t{R1}\n\n\t/* Save ulPortTaskHasFPUContext itself. */\n\tPUSH\t{R3}\n\n\t/* Save the stack pointer in the TCB. */\n\tLDR\t\tR0, pxCurrentTCBConst\n\tLDR\t\tR1, [R0]\n\tSTR\t\tSP, [R1]\n\n\t.endm\n\n; /**********************************************************************/\n\n.macro portRESTORE_CONTEXT\n\n\t/* Set the SP to point to the stack of the task being restored. */\n\tLDR\t\tR0, pxCurrentTCBConst\n\tLDR\t\tR1, [R0]\n\tLDR\t\tSP, [R1]\n\n\t/* Is there a floating point context to restore?  If the restored\n\tulPortTaskHasFPUContext is zero then no. */\n\tLDR\t\tR0, ulPortTaskHasFPUContextConst\n\tPOP\t\t{R1}\n\tSTR\t\tR1, [R0]\n\tCMP\t\tR1, #0\n\n\t/* Restore the floating point context, if any. */\n\tPOPNE \t{R0}\n\tVPOPNE\t{D16-D31}\n\tVPOPNE\t{D0-D15}\n\tVMSRNE  FPSCR, R0\n\n\t/* Restore the critical section nesting depth. */\n\tLDR\t\tR0, ulCriticalNestingConst\n\tPOP\t\t{R1}\n\tSTR\t\tR1, [R0]\n\n\t/* Ensure the priority mask is correct for the critical nesting depth. */\n\tLDR\t\tR2, ulICCPMRConst\n\tLDR\t\tR2, [R2]\n\tCMP\t\tR1, #0\n\tMOVEQ\tR4, #255\n\tLDRNE\tR4, ulMaxAPIPriorityMaskConst\n\tLDRNE\tR4, [R4]\n\tSTR\t\tR4, [R2]\n\n\t/* Restore all system mode registers other than the SP (which is already\n\tbeing used). */\n\tPOP\t\t{R0-R12, R14}\n\n\t/* Return to the task code, loading CPSR on the way. */\n\tRFEIA\tsp!\n\n\t.endm\n\n\n\n\n/******************************************************************************\n * SVC handler is used to start the scheduler.\n *****************************************************************************/\n.align 4\n.type FreeRTOS_SWI_Handler, %function\nFreeRTOS_SWI_Handler:\n\t/* Save the context of the current task and select a new task to run. */\n\tportSAVE_CONTEXT\n\tLDR R0, vTaskSwitchContextConst\n\tBLX\tR0\n\tportRESTORE_CONTEXT\n\n\n/******************************************************************************\n * vPortRestoreTaskContext is used to start the scheduler.\n *****************************************************************************/\n.type vPortRestoreTaskContext, %function\nvPortRestoreTaskContext:\n\t/* Switch to system mode. */\n\tCPS\t\t#SYS_MODE\n\tportRESTORE_CONTEXT\n\n.align 4\n.type FreeRTOS_IRQ_Handler, %function\nFreeRTOS_IRQ_Handler:\n\t/* Return to the interrupted instruction. */\n\tSUB\t\tlr, lr, #4\n\n\t/* Push the return address and SPSR. */\n\tPUSH\t{lr}\n\tMRS\t\tlr, SPSR\n\tPUSH\t{lr}\n\n\t/* Change to supervisor mode to allow reentry. */\n\tCPS\t\t#SVC_MODE\n\n\t/* Push used registers. */\n\tPUSH\t{r0-r4, r12}\n\n\t/* Increment nesting count.  r3 holds the address of ulPortInterruptNesting\n\tfor future use.  r1 holds the original ulPortInterruptNesting value for\n\tfuture use. */\n\tLDR\t\tr3, ulPortInterruptNestingConst\n\tLDR\t\tr1, [r3]\n\tADD\t\tr4, r1, #1\n\tSTR\t\tr4, [r3]\n\n\t/* Read value from the interrupt acknowledge register, which is stored in r0\n\tfor future parameter and interrupt clearing use. */\n\tLDR \tr2, ulICCIARConst\n\tLDR\t\tr2, [r2]\n\tLDR\t\tr0, [r2]\n\n\t/* Ensure bit 2 of the stack pointer is clear.  r2 holds the bit 2 value for\n\tfuture use.  _RB_ Does this ever actually need to be done provided the start\n\tof the stack is 8-byte aligned? */\n\tMOV\t\tr2, sp\n\tAND\t\tr2, r2, #4\n\tSUB\t\tsp, sp, r2\n\n\t/* Call the interrupt handler.  r4 pushed to maintain alignment. */\n\tPUSH\t{r0-r4, lr}\n\tLDR\t\tr1, vApplicationIRQHandlerConst\n\tBLX\t\tr1\n\tPOP\t\t{r0-r4, lr}\n\tADD\t\tsp, sp, r2\n\n\tCPSID\ti\n\tDSB\n\tISB\n\n\t/* Write the value read from ICCIAR to ICCEOIR. */\n\tLDR \tr4, ulICCEOIRConst\n\tLDR\t\tr4, [r4]\n\tSTR\t\tr0, [r4]\n\n\t/* Restore the old nesting count. */\n\tSTR\t\tr1, [r3]\n\n\t/* A context switch is never performed if the nesting count is not 0. */\n\tCMP\t\tr1, #0\n\tBNE\t\texit_without_switch\n\n\t/* Did the interrupt request a context switch?  r1 holds the address of\n\tulPortYieldRequired and r0 the value of ulPortYieldRequired for future\n\tuse. */\n\tLDR\t\tr1, =ulPortYieldRequired\n\tLDR\t\tr0, [r1]\n\tCMP\t\tr0, #0\n\tBNE\t\tswitch_before_exit\n\nexit_without_switch:\n\t/* No context switch.  Restore used registers, LR_irq and SPSR before\n\treturning. */\n\tPOP\t\t{r0-r4, r12}\n\tCPS\t\t#IRQ_MODE\n\tPOP\t\t{LR}\n\tMSR\t\tSPSR_cxsf, LR\n\tPOP\t\t{LR}\n\tMOVS\tPC, LR\n\nswitch_before_exit:\n\t/* A context swtich is to be performed.  Clear the context switch pending\n\tflag. */\n\tMOV\t\tr0, #0\n\tSTR\t\tr0, [r1]\n\n\t/* Restore used registers, LR-irq and SPSR before saving the context\n\tto the task stack. */\n\tPOP\t\t{r0-r4, r12}\n\tCPS\t\t#IRQ_MODE\n\tPOP\t\t{LR}\n\tMSR\t\tSPSR_cxsf, LR\n\tPOP\t\t{LR}\n\tportSAVE_CONTEXT\n\n\t/* Call the function that selects the new task to execute.\n\tvTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD\n\tinstructions, or 8 byte aligned stack allocated data.  LR does not need\n\tsaving as a new LR will be loaded by portRESTORE_CONTEXT anyway. */\n\tLDR\t\tR0, vTaskSwitchContextConst\n\tBLX\t\tR0\n\n\t/* Restore the context of, and branch to, the task selected to execute\n\tnext. */\n\tportRESTORE_CONTEXT\n\n\n/******************************************************************************\n * If the application provides an implementation of vApplicationIRQHandler(),\n * then it will get called directly without saving the FPU registers on\n * interrupt entry, and this weak implementation of\n * vApplicationIRQHandler() will not get called.\n *\n * If the application provides its own implementation of\n * vApplicationFPUSafeIRQHandler() then this implementation of\n * vApplicationIRQHandler() will be called, save the FPU registers, and then\n * call vApplicationFPUSafeIRQHandler().\n *\n * Therefore, if the application writer wants FPU registers to be saved on\n * interrupt entry their IRQ handler must be called\n * vApplicationFPUSafeIRQHandler(), and if the application writer does not want\n * FPU registers to be saved on interrupt entry their IRQ handler must be\n * called vApplicationIRQHandler().\n *****************************************************************************/\n\n.align 4\n.weak vApplicationIRQHandler\n.type vApplicationIRQHandler, %function\nvApplicationIRQHandler:\n\tPUSH\t{LR}\n\tFMRX\tR1,  FPSCR\n\tVPUSH\t{D0-D15}\n\tVPUSH\t{D16-D31}\n\tPUSH\t{R1}\n\n\tLDR\t\tr1, vApplicationFPUSafeIRQHandlerConst\n\tBLX\t\tr1\n\n\tPOP\t\t{R0}\n\tVPOP\t{D16-D31}\n\tVPOP\t{D0-D15}\n\tVMSR\tFPSCR, R0\n\n\tPOP {PC}\n\n\nulICCIARConst:\t.word ulICCIAR\nulICCEOIRConst:\t.word ulICCEOIR\nulICCPMRConst: .word ulICCPMR\npxCurrentTCBConst: .word pxCurrentTCB\nulCriticalNestingConst: .word ulCriticalNesting\nulPortTaskHasFPUContextConst: .word ulPortTaskHasFPUContext\nulMaxAPIPriorityMaskConst: .word ulMaxAPIPriorityMask\nvTaskSwitchContextConst: .word vTaskSwitchContext\nvApplicationIRQHandlerConst: .word vApplicationIRQHandler\nulPortInterruptNestingConst: .word ulPortInterruptNesting\nvApplicationFPUSafeIRQHandlerConst: .word vApplicationFPUSafeIRQHandler\n\n.end\n\n\n\n\n\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CA9/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef PORTMACRO_H\n#define PORTMACRO_H\n\n#ifdef __cplusplus\n\textern \"C\" {\n#endif\n\n/*-----------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the given hardware\n * and compiler.\n *\n * These settings should not be altered.\n *-----------------------------------------------------------\n */\n\n/* Type definitions. */\n#define portCHAR\t\tchar\n#define portFLOAT\t\tfloat\n#define portDOUBLE\t\tdouble\n#define portLONG\t\tlong\n#define portSHORT\t\tshort\n#define portSTACK_TYPE\tuint32_t\n#define portBASE_TYPE\tlong\n\ntypedef portSTACK_TYPE StackType_t;\ntypedef long BaseType_t;\ntypedef unsigned long UBaseType_t;\n\ntypedef uint32_t TickType_t;\n#define portMAX_DELAY ( TickType_t ) 0xffffffffUL\n\n/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\nnot need to be guarded with a critical section. */\n#define portTICK_TYPE_IS_ATOMIC 1\n\n/*-----------------------------------------------------------*/\n\n/* Hardware specifics. */\n#define portSTACK_GROWTH\t\t\t( -1 )\n#define portTICK_PERIOD_MS\t\t\t( ( TickType_t ) 1000 / configTICK_RATE_HZ )\n#define portBYTE_ALIGNMENT\t\t\t8\n\n/*-----------------------------------------------------------*/\n\n/* Task utilities. */\n\n/* Called at the end of an ISR that can cause a context switch. */\n#define portEND_SWITCHING_ISR( xSwitchRequired )\\\n{\t\t\t\t\t\t\t\t\t\t\t\t\\\nextern uint32_t ulPortYieldRequired;\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tif( xSwitchRequired != pdFALSE )\t\t\t\\\n\t{\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tulPortYieldRequired = pdTRUE;\t\t\t\\\n\t}\t\t\t\t\t\t\t\t\t\t\t\\\n}\n\n#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\n#define portYIELD() __asm volatile ( \"SWI 0\" ::: \"memory\" );\n\n\n/*-----------------------------------------------------------\n * Critical section control\n *----------------------------------------------------------*/\n\nextern void vPortEnterCritical( void );\nextern void vPortExitCritical( void );\nextern uint32_t ulPortSetInterruptMask( void );\nextern void vPortClearInterruptMask( uint32_t ulNewMaskValue );\nextern void vPortInstallFreeRTOSVectorTable( void );\n\n/* These macros do not globally disable/enable interrupts.  They do mask off\ninterrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */\n#define portENTER_CRITICAL()\t\tvPortEnterCritical();\n#define portEXIT_CRITICAL()\t\t\tvPortExitCritical();\n#define portDISABLE_INTERRUPTS()\tulPortSetInterruptMask()\n#define portENABLE_INTERRUPTS()\t\tvPortClearInterruptMask( 0 )\n#define portSET_INTERRUPT_MASK_FROM_ISR()\t\tulPortSetInterruptMask()\n#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)\tvPortClearInterruptMask(x)\n\n/*-----------------------------------------------------------*/\n\n/* Task function macros as described on the FreeRTOS.org WEB site.  These are\nnot required for this port but included in case common demo code that uses these\nmacros is used. */\n#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )\tvoid vFunction( void *pvParameters )\n#define portTASK_FUNCTION( vFunction, pvParameters )\tvoid vFunction( void *pvParameters )\n\n/* Prototype of the FreeRTOS tick handler.  This must be installed as the\nhandler for whichever peripheral is used to generate the RTOS tick. */\nvoid FreeRTOS_Tick_Handler( void );\n\n/* If configUSE_TASK_FPU_SUPPORT is set to 1 (or left undefined) then tasks are\ncreated without an FPU context and must call vPortTaskUsesFPU() to give\nthemselves an FPU context before using any FPU instructions.  If\nconfigUSE_TASK_FPU_SUPPORT is set to 2 then all tasks will have an FPU context\nby default. */\n#if( configUSE_TASK_FPU_SUPPORT != 2 )\n\tvoid vPortTaskUsesFPU( void );\n#else\n\t/* Each task has an FPU context already, so define this function away to\n\tnothing to prevent it being called accidentally. */\n\t#define vPortTaskUsesFPU()\n#endif\n#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()\n\n#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )\n#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )\n\n/* Architecture specific optimisations. */\n#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION\n\t#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1\n#endif\n\n#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1\n\n\t/* Store/clear the ready priorities in a bit map. */\n\t#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )\n\t#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )\n\n\t/*-----------------------------------------------------------*/\n\n\t#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __builtin_clz( uxReadyPriorities ) )\n\n#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */\n\n#ifdef configASSERT\n\tvoid vPortValidateInterruptPriority( void );\n\t#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() \tvPortValidateInterruptPriority()\n#endif /* configASSERT */\n\n#define portNOP() __asm volatile( \"NOP\" )\n#define portINLINE __inline\n\n#ifdef __cplusplus\n\t} /* extern C */\n#endif\n\n\n/* The number of bits to shift for an interrupt priority is dependent on the\nnumber of bits implemented by the interrupt controller. */\n#if configUNIQUE_INTERRUPT_PRIORITIES == 16\n\t#define portPRIORITY_SHIFT 4\n\t#define portMAX_BINARY_POINT_VALUE\t3\n#elif configUNIQUE_INTERRUPT_PRIORITIES == 32\n\t#define portPRIORITY_SHIFT 3\n\t#define portMAX_BINARY_POINT_VALUE\t2\n#elif configUNIQUE_INTERRUPT_PRIORITIES == 64\n\t#define portPRIORITY_SHIFT 2\n\t#define portMAX_BINARY_POINT_VALUE\t1\n#elif configUNIQUE_INTERRUPT_PRIORITIES == 128\n\t#define portPRIORITY_SHIFT 1\n\t#define portMAX_BINARY_POINT_VALUE\t0\n#elif configUNIQUE_INTERRUPT_PRIORITIES == 256\n\t#define portPRIORITY_SHIFT 0\n\t#define portMAX_BINARY_POINT_VALUE\t0\n#else\n\t#error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting.  configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware\n#endif\n\n/* Interrupt controller access addresses. */\n#define portICCPMR_PRIORITY_MASK_OFFSET  \t\t\t\t\t\t( 0x04 )\n#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET \t\t\t\t( 0x0C )\n#define portICCEOIR_END_OF_INTERRUPT_OFFSET \t\t\t\t\t( 0x10 )\n#define portICCBPR_BINARY_POINT_OFFSET\t\t\t\t\t\t\t( 0x08 )\n#define portICCRPR_RUNNING_PRIORITY_OFFSET\t\t\t\t\t\t( 0x14 )\n\n#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS \t\t( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )\n#define portICCPMR_PRIORITY_MASK_REGISTER \t\t\t\t\t( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )\n#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS \t( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )\n#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS \t\t( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )\n#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS \t\t\t( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )\n#define portICCBPR_BINARY_POINT_REGISTER \t\t\t\t\t( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )\n#define portICCRPR_RUNNING_PRIORITY_REGISTER \t\t\t\t( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )\n\n#define portMEMORY_BARRIER() __asm volatile( \"\" ::: \"memory\" )\n\n#endif /* PORTMACRO_H */\n\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM0/port.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/*-----------------------------------------------------------\n* Implementation of functions defined in portable.h for the ARM CM0 port.\n*----------------------------------------------------------*/\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n/* Constants required to manipulate the NVIC. */\n#define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )\n#define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )\n#define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )\n#define portNVIC_INT_CTRL_REG                 ( *( ( volatile uint32_t * ) 0xe000ed04 ) )\n#define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )\n#define portNVIC_SYSTICK_CLK_BIT              ( 1UL << 2UL )\n#define portNVIC_SYSTICK_INT_BIT              ( 1UL << 1UL )\n#define portNVIC_SYSTICK_ENABLE_BIT           ( 1UL << 0UL )\n#define portNVIC_SYSTICK_COUNT_FLAG_BIT       ( 1UL << 16UL )\n#define portNVIC_PENDSVSET_BIT                ( 1UL << 28UL )\n#define portNVIC_PEND_SYSTICK_SET_BIT         ( 1UL << 26UL )\n#define portNVIC_PEND_SYSTICK_CLEAR_BIT       ( 1UL << 25UL )\n#define portMIN_INTERRUPT_PRIORITY            ( 255UL )\n#define portNVIC_PENDSV_PRI                   ( portMIN_INTERRUPT_PRIORITY << 16UL )\n#define portNVIC_SYSTICK_PRI                  ( portMIN_INTERRUPT_PRIORITY << 24UL )\n\n/* Constants required to set up the initial stack. */\n#define portINITIAL_XPSR                      ( 0x01000000 )\n\n/* The systick is a 24-bit counter. */\n#define portMAX_24_BIT_NUMBER                 ( 0xffffffUL )\n\n/* A fiddle factor to estimate the number of SysTick counts that would have\n * occurred while the SysTick counter is stopped during tickless idle\n * calculations. */\n#ifndef portMISSED_COUNTS_FACTOR\n    #define portMISSED_COUNTS_FACTOR    ( 94UL )\n#endif\n\n/* Let the user override the default SysTick clock rate.  If defined by the\n * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the\n * configuration register. */\n#ifndef configSYSTICK_CLOCK_HZ\n    #define configSYSTICK_CLOCK_HZ             ( configCPU_CLOCK_HZ )\n    /* Ensure the SysTick is clocked at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( portNVIC_SYSTICK_CLK_BIT )\n#else\n    /* Select the option to clock SysTick not at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( 0 )\n#endif\n\n/* Let the user override the pre-loading of the initial LR with the address of\n * prvTaskExitError() in case it messes up unwinding of the stack in the\n * debugger. */\n#ifdef configTASK_RETURN_ADDRESS\n    #define portTASK_RETURN_ADDRESS    configTASK_RETURN_ADDRESS\n#else\n    #define portTASK_RETURN_ADDRESS    prvTaskExitError\n#endif\n\n/*\n * Setup the timer to generate the tick interrupts.  The implementation in this\n * file is weak to allow application writers to change the timer used to\n * generate the tick interrupt.\n */\nvoid vPortSetupTimerInterrupt( void );\n\n/*\n * Exception handlers.\n */\nvoid xPortPendSVHandler( void ) __attribute__( ( naked ) );\nvoid xPortSysTickHandler( void );\nvoid vPortSVCHandler( void );\n\n/*\n * Start first task is a separate function so it can be tested in isolation.\n */\nstatic void vPortStartFirstTask( void ) __attribute__( ( naked ) );\n\n/*\n * Used to catch tasks that attempt to return from their implementing function.\n */\nstatic void prvTaskExitError( void );\n\n/*-----------------------------------------------------------*/\n\n/* Each task maintains its own interrupt status in the critical nesting\n * variable. */\nstatic UBaseType_t uxCriticalNesting = 0xaaaaaaaa;\n\n/*-----------------------------------------------------------*/\n\n/*\n * The number of SysTick increments that make up one tick period.\n */\n#if ( configUSE_TICKLESS_IDLE == 1 )\n    static uint32_t ulTimerCountsForOneTick = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n\n/*\n * The maximum number of tick periods that can be suppressed is limited by the\n * 24 bit resolution of the SysTick timer.\n */\n#if ( configUSE_TICKLESS_IDLE == 1 )\n    static uint32_t xMaximumPossibleSuppressedTicks = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n\n/*\n * Compensate for the CPU cycles that pass while the SysTick is stopped (low\n * power functionality only.\n */\n#if ( configUSE_TICKLESS_IDLE == 1 )\n    static uint32_t ulStoppedTimerCompensation = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n\n/*-----------------------------------------------------------*/\n\n/*\n * See header file for description.\n */\nStackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,\n                                     TaskFunction_t pxCode,\n                                     void * pvParameters )\n{\n    /* Simulate the stack frame as it would be created by a context switch\n     * interrupt. */\n    pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\n    *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR */\n    pxTopOfStack--;\n    *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC */\n    pxTopOfStack--;\n    *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\n    pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */\n    *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */\n    pxTopOfStack -= 8;                                       /* R11..R4. */\n\n    return pxTopOfStack;\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvTaskExitError( void )\n{\n    volatile uint32_t ulDummy = 0UL;\n\n    /* A function that implements a task must not exit or attempt to return to\n     * its caller as there is nothing to return to.  If a task wants to exit it\n     * should instead call vTaskDelete( NULL ).\n     *\n     * Artificially force an assert() to be triggered if configASSERT() is\n     * defined, then stop here so application writers can catch the error. */\n    configASSERT( uxCriticalNesting == ~0UL );\n    portDISABLE_INTERRUPTS();\n\n    while( ulDummy == 0 )\n    {\n        /* This file calls prvTaskExitError() after the scheduler has been\n         * started to remove a compiler warning about the function being defined\n         * but never called.  ulDummy is used purely to quieten other warnings\n         * about code appearing after this function is called - making ulDummy\n         * volatile makes the compiler think the function could return and\n         * therefore not output an 'unreachable code' warning for code that appears\n         * after it. */\n    }\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortSVCHandler( void )\n{\n    /* This function is no longer used, but retained for backward\n     * compatibility. */\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortStartFirstTask( void )\n{\n    /* The MSP stack is not reset as, unlike on M3/4 parts, there is no vector\n     * table offset register that can be used to locate the initial stack value.\n     * Not all M0 parts have the application vector table at address 0. */\n    __asm volatile (\n        \"\t.syntax unified\t\t\t\t\\n\"\n        \"\tldr  r2, pxCurrentTCBConst2\t\\n\"/* Obtain location of pxCurrentTCB. */\n        \"\tldr  r3, [r2]\t\t\t\t\\n\"\n        \"\tldr  r0, [r3]\t\t\t\t\\n\"/* The first item in pxCurrentTCB is the task top of stack. */\n        \"\tadds r0, #32\t\t\t\t\t\\n\"/* Discard everything up to r0. */\n        \"\tmsr  psp, r0\t\t\t\t\t\\n\"/* This is now the new top of stack to use in the task. */\n        \"\tmovs r0, #2\t\t\t\t\t\\n\"/* Switch to the psp stack. */\n        \"\tmsr  CONTROL, r0\t\t\t\t\\n\"\n        \"\tisb\t\t\t\t\t\t\t\\n\"\n        \"\tpop  {r0-r5}\t\t\t\t\t\\n\"/* Pop the registers that are saved automatically. */\n        \"\tmov  lr, r5\t\t\t\t\t\\n\"/* lr is now in r5. */\n        \"\tpop  {r3}\t\t\t\t\t\\n\"/* Return address is now in r3. */\n        \"\tpop  {r2}\t\t\t\t\t\\n\"/* Pop and discard XPSR. */\n        \"\tcpsie i\t\t\t\t\t\t\\n\"/* The first task has its context and interrupts can be enabled. */\n        \"\tbx   r3\t\t\t\t\t\t\\n\"/* Finally, jump to the user defined task code. */\n        \"\t\t\t\t\t\t\t\t\\n\"\n        \"\t.align 4\t\t\t\t\t\\n\"\n        \"pxCurrentTCBConst2: .word pxCurrentTCB\t  \"\n        );\n}\n/*-----------------------------------------------------------*/\n\n/*\n * See header file for description.\n */\nBaseType_t xPortStartScheduler( void )\n{\n    /* Make PendSV, CallSV and SysTick the same priority as the kernel. */\n    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;\n    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;\n\n    /* Start the timer that generates the tick ISR.  Interrupts are disabled\n     * here already. */\n    vPortSetupTimerInterrupt();\n\n    /* Initialise the critical nesting count ready for the first task. */\n    uxCriticalNesting = 0;\n\n    /* Start the first task. */\n    vPortStartFirstTask();\n\n    /* Should never get here as the tasks will now be executing!  Call the task\n     * exit error function to prevent compiler warnings about a static function\n     * not being called in the case that the application writer overrides this\n     * functionality by defining configTASK_RETURN_ADDRESS.  Call\n     * vTaskSwitchContext() so link time optimisation does not remove the\n     * symbol. */\n    vTaskSwitchContext();\n    prvTaskExitError();\n\n    /* Should not get here! */\n    return 0;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEndScheduler( void )\n{\n    /* Not implemented in ports where there is nothing to return to.\n     * Artificially force an assert. */\n    configASSERT( uxCriticalNesting == 1000UL );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortYield( void )\n{\n    /* Set a PendSV to request a context switch. */\n    portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\n\n    /* Barriers are normally not required but do ensure the code is completely\n     * within the specified behaviour for the architecture. */\n    __asm volatile ( \"dsb\" ::: \"memory\" );\n    __asm volatile ( \"isb\" );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEnterCritical( void )\n{\n    portDISABLE_INTERRUPTS();\n    uxCriticalNesting++;\n    __asm volatile ( \"dsb\" ::: \"memory\" );\n    __asm volatile ( \"isb\" );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortExitCritical( void )\n{\n    configASSERT( uxCriticalNesting );\n    uxCriticalNesting--;\n\n    if( uxCriticalNesting == 0 )\n    {\n        portENABLE_INTERRUPTS();\n    }\n}\n/*-----------------------------------------------------------*/\n\nuint32_t ulSetInterruptMaskFromISR( void )\n{\n    __asm volatile (\n        \" mrs r0, PRIMASK\t\\n\"\n        \" cpsid i\t\t\t\\n\"\n        \" bx lr\t\t\t\t  \"\n        ::: \"memory\"\n        );\n}\n/*-----------------------------------------------------------*/\n\nvoid vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask )\n{\n    __asm volatile (\n        \" msr PRIMASK, r0\t\\n\"\n        \" bx lr\t\t\t\t  \"\n        ::: \"memory\"\n        );\n}\n/*-----------------------------------------------------------*/\n\nvoid xPortPendSVHandler( void )\n{\n    /* This is a naked function. */\n\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\\n\"\n        \"\tmrs r0, psp\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr\tr3, pxCurrentTCBConst\t\t\t\\n\"/* Get the location of the current TCB. */\n        \"\tldr\tr2, [r3]\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tsubs r0, r0, #32\t\t\t\t\t\\n\"/* Make space for the remaining low registers. */\n        \"\tstr r0, [r2]\t\t\t\t\t\t\\n\"/* Save the new top of stack. */\n        \"\tstmia r0!, {r4-r7}\t\t\t\t\t\\n\"/* Store the low registers that are not saved automatically. */\n        \" \tmov r4, r8\t\t\t\t\t\t\t\\n\"/* Store the high registers. */\n        \" \tmov r5, r9\t\t\t\t\t\t\t\\n\"\n        \" \tmov r6, r10\t\t\t\t\t\t\t\\n\"\n        \" \tmov r7, r11\t\t\t\t\t\t\t\\n\"\n        \" \tstmia r0!, {r4-r7}\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tpush {r3, r14}\t\t\t\t\t\t\\n\"\n        \"\tcpsid i\t\t\t\t\t\t\t\t\\n\"\n        \"\tbl vTaskSwitchContext\t\t\t\t\\n\"\n        \"\tcpsie i\t\t\t\t\t\t\t\t\\n\"\n        \"\tpop {r2, r3}\t\t\t\t\t\t\\n\"/* lr goes in r3. r2 now holds tcb pointer. */\n        \"\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r1, [r2]\t\t\t\t\t\t\\n\"\n        \"\tldr r0, [r1]\t\t\t\t\t\t\\n\"/* The first item in pxCurrentTCB is the task top of stack. */\n        \"\tadds r0, r0, #16\t\t\t\t\t\\n\"/* Move to the high registers. */\n        \"\tldmia r0!, {r4-r7}\t\t\t\t\t\\n\"/* Pop the high registers. */\n        \" \tmov r8, r4\t\t\t\t\t\t\t\\n\"\n        \" \tmov r9, r5\t\t\t\t\t\t\t\\n\"\n        \" \tmov r10, r6\t\t\t\t\t\t\t\\n\"\n        \" \tmov r11, r7\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmsr psp, r0\t\t\t\t\t\t\t\\n\"/* Remember the new top of stack for the task. */\n        \"\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tsubs r0, r0, #32\t\t\t\t\t\\n\"/* Go back for the low registers that are not automatically restored. */\n        \" \tldmia r0!, {r4-r7}\t\t\t\t\t\\n\"/* Pop low registers.  */\n        \"\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tbx r3\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.align 4\t\t\t\t\t\t\t\\n\"\n        \"pxCurrentTCBConst: .word pxCurrentTCB\t  \"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid xPortSysTickHandler( void )\n{\n    uint32_t ulPreviousMask;\n\n    ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();\n    {\n        /* Increment the RTOS tick. */\n        if( xTaskIncrementTick() != pdFALSE )\n        {\n            /* Pend a context switch. */\n            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\n        }\n    }\n    portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );\n}\n/*-----------------------------------------------------------*/\n\n/*\n * Setup the systick timer to generate the tick interrupts at the required\n * frequency.\n */\n__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )\n{\n    /* Calculate the constants required to configure the tick interrupt. */\n    #if ( configUSE_TICKLESS_IDLE == 1 )\n    {\n        ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );\n        xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;\n        ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\n    }\n    #endif /* configUSE_TICKLESS_IDLE */\n\n    /* Stop and reset the SysTick. */\n    portNVIC_SYSTICK_CTRL_REG = 0UL;\n    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n    /* Configure SysTick to interrupt at the requested rate. */\n    portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\n    portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );\n}\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TICKLESS_IDLE == 1 )\n\n    __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )\n    {\n        uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;\n        TickType_t xModifiableIdleTime;\n\n        /* Make sure the SysTick reload value does not overflow the counter. */\n        if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\n        {\n            xExpectedIdleTime = xMaximumPossibleSuppressedTicks;\n        }\n\n        /* Enter a critical section but don't use the taskENTER_CRITICAL()\n         * method as that will mask interrupts that should exit sleep mode. */\n        __asm volatile ( \"cpsid i\" ::: \"memory\" );\n        __asm volatile ( \"dsb\" );\n        __asm volatile ( \"isb\" );\n\n        /* If a context switch is pending or a task is waiting for the scheduler\n         * to be unsuspended then abandon the low power entry. */\n        if( eTaskConfirmSleepModeStatus() == eAbortSleep )\n        {\n            /* Re-enable interrupts - see comments above the cpsid instruction\n             * above. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n        }\n        else\n        {\n            /* Stop the SysTick momentarily.  The time the SysTick is stopped for\n             * is accounted for as best it can be, but using the tickless mode will\n             * inevitably result in some tiny drift of the time maintained by the\n             * kernel with respect to calendar time. */\n            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );\n\n            /* Use the SysTick current-value register to determine the number of\n             * SysTick decrements remaining until the next tick interrupt.  If the\n             * current-value register is zero, then there are actually\n             * ulTimerCountsForOneTick decrements remaining, not zero, because the\n             * SysTick requests the interrupt when decrementing from 1 to 0. */\n            ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n\n            if( ulSysTickDecrementsLeft == 0 )\n            {\n                ulSysTickDecrementsLeft = ulTimerCountsForOneTick;\n            }\n\n            /* Calculate the reload value required to wait xExpectedIdleTime\n             * tick periods.  -1 is used because this code normally executes part\n             * way through the first tick period.  But if the SysTick IRQ is now\n             * pending, then clear the IRQ, suppressing the first tick, and correct\n             * the reload value to reflect that the second tick period is already\n             * underway.  The expected idle time is always at least two ticks. */\n            ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );\n\n            if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )\n            {\n                portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;\n                ulReloadValue -= ulTimerCountsForOneTick;\n            }\n\n            if( ulReloadValue > ulStoppedTimerCompensation )\n            {\n                ulReloadValue -= ulStoppedTimerCompensation;\n            }\n\n            /* Set the new reload value. */\n            portNVIC_SYSTICK_LOAD_REG = ulReloadValue;\n\n            /* Clear the SysTick count flag and set the count value back to\n             * zero. */\n            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n            /* Restart SysTick. */\n            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\n\n            /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can\n             * set its parameter to 0 to indicate that its implementation contains\n             * its own wait for interrupt or wait for event instruction, and so wfi\n             * should not be executed again.  However, the original expected idle\n             * time variable must remain unmodified, so a copy is taken. */\n            xModifiableIdleTime = xExpectedIdleTime;\n            configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\n\n            if( xModifiableIdleTime > 0 )\n            {\n                __asm volatile ( \"dsb\" ::: \"memory\" );\n                __asm volatile ( \"wfi\" );\n                __asm volatile ( \"isb\" );\n            }\n\n            configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\n\n            /* Re-enable interrupts to allow the interrupt that brought the MCU\n             * out of sleep mode to execute immediately.  See comments above\n             * the cpsid instruction above. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n            __asm volatile ( \"dsb\" );\n            __asm volatile ( \"isb\" );\n\n            /* Disable interrupts again because the clock is about to be stopped\n             * and interrupts that execute while the clock is stopped will increase\n             * any slippage between the time maintained by the RTOS and calendar\n             * time. */\n            __asm volatile ( \"cpsid i\" ::: \"memory\" );\n            __asm volatile ( \"dsb\" );\n            __asm volatile ( \"isb\" );\n\n            /* Disable the SysTick clock without reading the\n             * portNVIC_SYSTICK_CTRL_REG register to ensure the\n             * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,\n             * the time the SysTick is stopped for is accounted for as best it can\n             * be, but using the tickless mode will inevitably result in some tiny\n             * drift of the time maintained by the kernel with respect to calendar\n             * time*/\n            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );\n\n            /* Determine whether the SysTick has already counted to zero. */\n            if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n            {\n                uint32_t ulCalculatedLoadValue;\n\n                /* The tick interrupt ended the sleep (or is now pending), and\n                 * a new tick period has started.  Reset portNVIC_SYSTICK_LOAD_REG\n                 * with whatever remains of the new tick period. */\n                ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\n\n                /* Don't allow a tiny value, or values that have somehow\n                 * underflowed because the post sleep hook did something\n                 * that took too long or because the SysTick current-value register\n                 * is zero. */\n                if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )\n                {\n                    ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );\n                }\n\n                portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;\n\n                /* As the pending tick will be processed as soon as this\n                 * function exits, the tick value maintained by the tick is stepped\n                 * forward by one less than the time spent waiting. */\n                ulCompleteTickPeriods = xExpectedIdleTime - 1UL;\n            }\n            else\n            {\n                /* Something other than the tick interrupt ended the sleep. */\n\n                /* Use the SysTick current-value register to determine the\n                 * number of SysTick decrements remaining until the expected idle\n                 * time would have ended. */\n                ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n                #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )\n                {\n                    /* If the SysTick is not using the core clock, the current-\n                     * value register might still be zero here.  In that case, the\n                     * SysTick didn't load from the reload register, and there are\n                     * ulReloadValue decrements remaining in the expected idle\n                     * time, not zero. */\n                    if( ulSysTickDecrementsLeft == 0 )\n                    {\n                        ulSysTickDecrementsLeft = ulReloadValue;\n                    }\n                }\n                #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */\n\n                /* Work out how long the sleep lasted rounded to complete tick\n                 * periods (not the ulReload value which accounted for part\n                 * ticks). */\n                ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;\n\n                /* How many complete tick periods passed while the processor\n                 * was waiting? */\n                ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;\n\n                /* The reload value is set to whatever fraction of a single tick\n                 * period remains. */\n                portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;\n            }\n\n            /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,\n             * then set portNVIC_SYSTICK_LOAD_REG back to its standard value.  If\n             * the SysTick is not using the core clock, temporarily configure it to\n             * use the core clock.  This configuration forces the SysTick to load\n             * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next\n             * cycle of the other clock.  Then portNVIC_SYSTICK_LOAD_REG is ready\n             * to receive the standard value immediately. */\n            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n            portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n            #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )\n            {\n                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n            }\n            #else\n            {\n                /* The temporary usage of the core clock has served its purpose,\n                 * as described above.  Resume usage of the other clock. */\n                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\n\n                if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n                {\n                    /* The partial tick period already ended.  Be sure the SysTick\n                     * counts it only once. */\n                    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;\n                }\n\n                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n            }\n            #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */\n\n            /* Step the tick to account for any tick periods that elapsed. */\n            vTaskStepTick( ulCompleteTickPeriods );\n\n            /* Exit with interrupts enabled. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n        }\n    }\n\n#endif /* configUSE_TICKLESS_IDLE */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM0/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n\n#ifndef PORTMACRO_H\n    #define PORTMACRO_H\n\n    #ifdef __cplusplus\n        extern \"C\" {\n    #endif\n\n/*-----------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the\n * given hardware and compiler.\n *\n * These settings should not be altered.\n *-----------------------------------------------------------\n */\n\n/* Type definitions. */\n    #define portCHAR          char\n    #define portFLOAT         float\n    #define portDOUBLE        double\n    #define portLONG          long\n    #define portSHORT         short\n    #define portSTACK_TYPE    uint32_t\n    #define portBASE_TYPE     long\n\n    typedef portSTACK_TYPE   StackType_t;\n    typedef long             BaseType_t;\n    typedef unsigned long    UBaseType_t;\n\n    #if ( configUSE_16_BIT_TICKS == 1 )\n        typedef uint16_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffff\n    #else\n        typedef uint32_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL\n\n/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\n * not need to be guarded with a critical section. */\n        #define portTICK_TYPE_IS_ATOMIC    1\n    #endif\n/*-----------------------------------------------------------*/\n\n/* Architecture specifics. */\n    #define portSTACK_GROWTH      ( -1 )\n    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\n    #define portBYTE_ALIGNMENT    8\n    #define portDONT_DISCARD      __attribute__( ( used ) )\n/*-----------------------------------------------------------*/\n\n\n/* Scheduler utilities. */\n    extern void vPortYield( void );\n    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )\n    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )\n    #define portYIELD()                                 vPortYield()\n    #define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )\n    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )\n/*-----------------------------------------------------------*/\n\n\n/* Critical section management. */\n    extern void vPortEnterCritical( void );\n    extern void vPortExitCritical( void );\n    extern uint32_t ulSetInterruptMaskFromISR( void ) __attribute__( ( naked ) );\n    extern void vClearInterruptMaskFromISR( uint32_t ulMask )  __attribute__( ( naked ) );\n\n    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulSetInterruptMaskFromISR()\n    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vClearInterruptMaskFromISR( x )\n    #define portDISABLE_INTERRUPTS()                  __asm volatile ( \" cpsid i \" ::: \"memory\" )\n    #define portENABLE_INTERRUPTS()                   __asm volatile ( \" cpsie i \" ::: \"memory\" )\n    #define portENTER_CRITICAL()                      vPortEnterCritical()\n    #define portEXIT_CRITICAL()                       vPortExitCritical()\n\n/*-----------------------------------------------------------*/\n\n/* Tickless idle/low power functionality. */\n    #ifndef portSUPPRESS_TICKS_AND_SLEEP\n        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );\n        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )\n    #endif\n/*-----------------------------------------------------------*/\n\n/* Task function macros as described on the FreeRTOS.org WEB site. */\n    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )\n    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )\n\n    #define portNOP()\n\n    #define portMEMORY_BARRIER()    __asm volatile ( \"\" ::: \"memory\" )\n\n    #ifdef __cplusplus\n        }\n    #endif\n\n#endif /* PORTMACRO_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM23/non_secure/port.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\n * all the API functions to use the MPU wrappers. That should only be done when\n * task.h is included from an application file. */\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n/* MPU wrappers includes. */\n#include \"mpu_wrappers.h\"\n\n/* Portasm includes. */\n#include \"portasm.h\"\n\n#if ( configENABLE_TRUSTZONE == 1 )\n    /* Secure components includes. */\n    #include \"secure_context.h\"\n    #include \"secure_init.h\"\n#endif /* configENABLE_TRUSTZONE */\n\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/**\n * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only\n * i.e. the processor boots as secure and never jumps to the non-secure side.\n * The Trust Zone support in the port must be disabled in order to run FreeRTOS\n * on the secure side. The following are the valid configuration seetings:\n *\n * 1. Run FreeRTOS on the Secure Side:\n *    configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0\n *\n * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:\n *    configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1\n *\n * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:\n *    configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0\n */\n#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )\n    #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.\n#endif\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the NVIC.\n */\n#define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )\n#define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )\n#define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )\n#define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )\n#define portNVIC_SYSTICK_ENABLE_BIT           ( 1UL << 0UL )\n#define portNVIC_SYSTICK_INT_BIT              ( 1UL << 1UL )\n#define portNVIC_SYSTICK_CLK_BIT              ( 1UL << 2UL )\n#define portNVIC_SYSTICK_COUNT_FLAG_BIT       ( 1UL << 16UL )\n#define portNVIC_PEND_SYSTICK_CLEAR_BIT       ( 1UL << 25UL )\n#define portNVIC_PEND_SYSTICK_SET_BIT         ( 1UL << 26UL )\n#define portMIN_INTERRUPT_PRIORITY            ( 255UL )\n#define portNVIC_PENDSV_PRI                   ( portMIN_INTERRUPT_PRIORITY << 16UL )\n#define portNVIC_SYSTICK_PRI                  ( portMIN_INTERRUPT_PRIORITY << 24UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the SCB.\n */\n#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( volatile uint32_t * ) 0xe000ed24 )\n#define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the FPU.\n */\n#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 )              /* Coprocessor Access Control Register. */\n#define portCPACR_CP10_VALUE    ( 3UL )\n#define portCPACR_CP11_VALUE    portCPACR_CP10_VALUE\n#define portCPACR_CP10_POS      ( 20UL )\n#define portCPACR_CP11_POS      ( 22UL )\n\n#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 )              /* Floating Point Context Control Register. */\n#define portFPCCR_ASPEN_POS     ( 31UL )\n#define portFPCCR_ASPEN_MASK    ( 1UL << portFPCCR_ASPEN_POS )\n#define portFPCCR_LSPEN_POS     ( 30UL )\n#define portFPCCR_LSPEN_MASK    ( 1UL << portFPCCR_LSPEN_POS )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the MPU.\n */\n#define portMPU_TYPE_REG                      ( *( ( volatile uint32_t * ) 0xe000ed90 ) )\n#define portMPU_CTRL_REG                      ( *( ( volatile uint32_t * ) 0xe000ed94 ) )\n#define portMPU_RNR_REG                       ( *( ( volatile uint32_t * ) 0xe000ed98 ) )\n\n#define portMPU_RBAR_REG                      ( *( ( volatile uint32_t * ) 0xe000ed9c ) )\n#define portMPU_RLAR_REG                      ( *( ( volatile uint32_t * ) 0xe000eda0 ) )\n\n#define portMPU_RBAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda4 ) )\n#define portMPU_RLAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda8 ) )\n\n#define portMPU_RBAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edac ) )\n#define portMPU_RLAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edb0 ) )\n\n#define portMPU_RBAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb4 ) )\n#define portMPU_RLAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb8 ) )\n\n#define portMPU_MAIR0_REG                     ( *( ( volatile uint32_t * ) 0xe000edc0 ) )\n#define portMPU_MAIR1_REG                     ( *( ( volatile uint32_t * ) 0xe000edc4 ) )\n\n#define portMPU_RBAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */\n#define portMPU_RLAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */\n\n#define portMPU_MAIR_ATTR0_POS                ( 0UL )\n#define portMPU_MAIR_ATTR0_MASK               ( 0x000000ff )\n\n#define portMPU_MAIR_ATTR1_POS                ( 8UL )\n#define portMPU_MAIR_ATTR1_MASK               ( 0x0000ff00 )\n\n#define portMPU_MAIR_ATTR2_POS                ( 16UL )\n#define portMPU_MAIR_ATTR2_MASK               ( 0x00ff0000 )\n\n#define portMPU_MAIR_ATTR3_POS                ( 24UL )\n#define portMPU_MAIR_ATTR3_MASK               ( 0xff000000 )\n\n#define portMPU_MAIR_ATTR4_POS                ( 0UL )\n#define portMPU_MAIR_ATTR4_MASK               ( 0x000000ff )\n\n#define portMPU_MAIR_ATTR5_POS                ( 8UL )\n#define portMPU_MAIR_ATTR5_MASK               ( 0x0000ff00 )\n\n#define portMPU_MAIR_ATTR6_POS                ( 16UL )\n#define portMPU_MAIR_ATTR6_MASK               ( 0x00ff0000 )\n\n#define portMPU_MAIR_ATTR7_POS                ( 24UL )\n#define portMPU_MAIR_ATTR7_MASK               ( 0xff000000 )\n\n#define portMPU_RLAR_ATTR_INDEX0              ( 0UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX1              ( 1UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX2              ( 2UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX3              ( 3UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX4              ( 4UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX5              ( 5UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX6              ( 6UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX7              ( 7UL << 1UL )\n\n#define portMPU_RLAR_REGION_ENABLE            ( 1UL )\n\n/* Enable privileged access to unmapped region. */\n#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )\n\n/* Enable MPU. */\n#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )\n\n/* Expected value of the portMPU_TYPE register. */\n#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief The maximum 24-bit number.\n *\n * It is needed because the systick is a 24-bit counter.\n */\n#define portMAX_24_BIT_NUMBER       ( 0xffffffUL )\n\n/**\n * @brief A fiddle factor to estimate the number of SysTick counts that would\n * have occurred while the SysTick counter is stopped during tickless idle\n * calculations.\n */\n#define portMISSED_COUNTS_FACTOR    ( 94UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to set up the initial stack.\n */\n#define portINITIAL_XPSR    ( 0x01000000 )\n\n#if ( configRUN_FREERTOS_SECURE_ONLY == 1 )\n\n/**\n * @brief Initial EXC_RETURN value.\n *\n *     FF         FF         FF         FD\n * 1111 1111  1111 1111  1111 1111  1111 1101\n *\n * Bit[6] - 1 --> The exception was taken from the Secure state.\n * Bit[5] - 1 --> Do not skip stacking of additional state context.\n * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\n * Bit[3] - 1 --> Return to the Thread mode.\n * Bit[2] - 1 --> Restore registers from the process stack.\n * Bit[1] - 0 --> Reserved, 0.\n * Bit[0] - 1 --> The exception was taken to the Secure state.\n */\n    #define portINITIAL_EXC_RETURN    ( 0xfffffffd )\n#else\n\n/**\n * @brief Initial EXC_RETURN value.\n *\n *     FF         FF         FF         BC\n * 1111 1111  1111 1111  1111 1111  1011 1100\n *\n * Bit[6] - 0 --> The exception was taken from the Non-Secure state.\n * Bit[5] - 1 --> Do not skip stacking of additional state context.\n * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\n * Bit[3] - 1 --> Return to the Thread mode.\n * Bit[2] - 1 --> Restore registers from the process stack.\n * Bit[1] - 0 --> Reserved, 0.\n * Bit[0] - 0 --> The exception was taken to the Non-Secure state.\n */\n    #define portINITIAL_EXC_RETURN    ( 0xffffffbc )\n#endif /* configRUN_FREERTOS_SECURE_ONLY */\n\n/**\n * @brief CONTROL register privileged bit mask.\n *\n * Bit[0] in CONTROL register tells the privilege:\n *  Bit[0] = 0 ==> The task is privileged.\n *  Bit[0] = 1 ==> The task is not privileged.\n */\n#define portCONTROL_PRIVILEGED_MASK         ( 1UL << 0UL )\n\n/**\n * @brief Initial CONTROL register values.\n */\n#define portINITIAL_CONTROL_UNPRIVILEGED    ( 0x3 )\n#define portINITIAL_CONTROL_PRIVILEGED      ( 0x2 )\n\n/**\n * @brief Let the user override the default SysTick clock rate.  If defined by the\n * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the\n * configuration register.\n */\n#ifndef configSYSTICK_CLOCK_HZ\n    #define configSYSTICK_CLOCK_HZ             ( configCPU_CLOCK_HZ )\n    /* Ensure the SysTick is clocked at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( portNVIC_SYSTICK_CLK_BIT )\n#else\n    /* Select the option to clock SysTick not at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( 0 )\n#endif\n\n/**\n * @brief Let the user override the pre-loading of the initial LR with the\n * address of prvTaskExitError() in case it messes up unwinding of the stack\n * in the debugger.\n */\n#ifdef configTASK_RETURN_ADDRESS\n    #define portTASK_RETURN_ADDRESS    configTASK_RETURN_ADDRESS\n#else\n    #define portTASK_RETURN_ADDRESS    prvTaskExitError\n#endif\n\n/**\n * @brief If portPRELOAD_REGISTERS then registers will be given an initial value\n * when a task is created. This helps in debugging at the cost of code size.\n */\n#define portPRELOAD_REGISTERS    1\n\n/**\n * @brief A task is created without a secure context, and must call\n * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes\n * any secure calls.\n */\n#define portNO_SECURE_CONTEXT    0\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Used to catch tasks that attempt to return from their implementing\n * function.\n */\nstatic void prvTaskExitError( void );\n\n#if ( configENABLE_MPU == 1 )\n\n/**\n * @brief Setup the Memory Protection Unit (MPU).\n */\n    static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\n#endif /* configENABLE_MPU */\n\n#if ( configENABLE_FPU == 1 )\n\n/**\n * @brief Setup the Floating Point Unit (FPU).\n */\n    static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;\n#endif /* configENABLE_FPU */\n\n/**\n * @brief Setup the timer to generate the tick interrupts.\n *\n * The implementation in this file is weak to allow application writers to\n * change the timer used to generate the tick interrupt.\n */\nvoid vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Checks whether the current execution context is interrupt.\n *\n * @return pdTRUE if the current execution context is interrupt, pdFALSE\n * otherwise.\n */\nBaseType_t xPortIsInsideInterrupt( void );\n\n/**\n * @brief Yield the processor.\n */\nvoid vPortYield( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Enter critical section.\n */\nvoid vPortEnterCritical( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Exit from critical section.\n */\nvoid vPortExitCritical( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief SysTick handler.\n */\nvoid SysTick_Handler( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief C part of SVC handler.\n */\nportDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION;\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Each task maintains its own interrupt status in the critical nesting\n * variable.\n */\nPRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;\n\n#if ( configENABLE_TRUSTZONE == 1 )\n\n/**\n * @brief Saved as part of the task context to indicate which context the\n * task is using on the secure side.\n */\n    PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;\n#endif /* configENABLE_TRUSTZONE */\n\n#if ( configUSE_TICKLESS_IDLE == 1 )\n\n/**\n * @brief The number of SysTick increments that make up one tick period.\n */\n    PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0;\n\n/**\n * @brief The maximum number of tick periods that can be suppressed is\n * limited by the 24 bit resolution of the SysTick timer.\n */\n    PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0;\n\n/**\n * @brief Compensate for the CPU cycles that pass while the SysTick is\n * stopped (low power functionality only).\n */\n    PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TICKLESS_IDLE == 1 )\n    __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )\n    {\n        uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;\n        TickType_t xModifiableIdleTime;\n\n        /* Make sure the SysTick reload value does not overflow the counter. */\n        if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\n        {\n            xExpectedIdleTime = xMaximumPossibleSuppressedTicks;\n        }\n\n        /* Enter a critical section but don't use the taskENTER_CRITICAL()\n         * method as that will mask interrupts that should exit sleep mode. */\n        __asm volatile ( \"cpsid i\" ::: \"memory\" );\n        __asm volatile ( \"dsb\" );\n        __asm volatile ( \"isb\" );\n\n        /* If a context switch is pending or a task is waiting for the scheduler\n         * to be unsuspended then abandon the low power entry. */\n        if( eTaskConfirmSleepModeStatus() == eAbortSleep )\n        {\n            /* Re-enable interrupts - see comments above the cpsid instruction\n             * above. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n        }\n        else\n        {\n            /* Stop the SysTick momentarily.  The time the SysTick is stopped for\n             * is accounted for as best it can be, but using the tickless mode will\n             * inevitably result in some tiny drift of the time maintained by the\n             * kernel with respect to calendar time. */\n            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );\n\n            /* Use the SysTick current-value register to determine the number of\n             * SysTick decrements remaining until the next tick interrupt.  If the\n             * current-value register is zero, then there are actually\n             * ulTimerCountsForOneTick decrements remaining, not zero, because the\n             * SysTick requests the interrupt when decrementing from 1 to 0. */\n            ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n\n            if( ulSysTickDecrementsLeft == 0 )\n            {\n                ulSysTickDecrementsLeft = ulTimerCountsForOneTick;\n            }\n\n            /* Calculate the reload value required to wait xExpectedIdleTime\n             * tick periods.  -1 is used because this code normally executes part\n             * way through the first tick period.  But if the SysTick IRQ is now\n             * pending, then clear the IRQ, suppressing the first tick, and correct\n             * the reload value to reflect that the second tick period is already\n             * underway.  The expected idle time is always at least two ticks. */\n            ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );\n\n            if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )\n            {\n                portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;\n                ulReloadValue -= ulTimerCountsForOneTick;\n            }\n\n            if( ulReloadValue > ulStoppedTimerCompensation )\n            {\n                ulReloadValue -= ulStoppedTimerCompensation;\n            }\n\n            /* Set the new reload value. */\n            portNVIC_SYSTICK_LOAD_REG = ulReloadValue;\n\n            /* Clear the SysTick count flag and set the count value back to\n             * zero. */\n            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n            /* Restart SysTick. */\n            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\n\n            /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can\n             * set its parameter to 0 to indicate that its implementation contains\n             * its own wait for interrupt or wait for event instruction, and so wfi\n             * should not be executed again.  However, the original expected idle\n             * time variable must remain unmodified, so a copy is taken. */\n            xModifiableIdleTime = xExpectedIdleTime;\n            configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\n\n            if( xModifiableIdleTime > 0 )\n            {\n                __asm volatile ( \"dsb\" ::: \"memory\" );\n                __asm volatile ( \"wfi\" );\n                __asm volatile ( \"isb\" );\n            }\n\n            configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\n\n            /* Re-enable interrupts to allow the interrupt that brought the MCU\n             * out of sleep mode to execute immediately.  See comments above\n             * the cpsid instruction above. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n            __asm volatile ( \"dsb\" );\n            __asm volatile ( \"isb\" );\n\n            /* Disable interrupts again because the clock is about to be stopped\n             * and interrupts that execute while the clock is stopped will increase\n             * any slippage between the time maintained by the RTOS and calendar\n             * time. */\n            __asm volatile ( \"cpsid i\" ::: \"memory\" );\n            __asm volatile ( \"dsb\" );\n            __asm volatile ( \"isb\" );\n\n            /* Disable the SysTick clock without reading the\n             * portNVIC_SYSTICK_CTRL_REG register to ensure the\n             * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,\n             * the time the SysTick is stopped for is accounted for as best it can\n             * be, but using the tickless mode will inevitably result in some tiny\n             * drift of the time maintained by the kernel with respect to calendar\n             * time*/\n            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );\n\n            /* Determine whether the SysTick has already counted to zero. */\n            if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n            {\n                uint32_t ulCalculatedLoadValue;\n\n                /* The tick interrupt ended the sleep (or is now pending), and\n                 * a new tick period has started.  Reset portNVIC_SYSTICK_LOAD_REG\n                 * with whatever remains of the new tick period. */\n                ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\n\n                /* Don't allow a tiny value, or values that have somehow\n                 * underflowed because the post sleep hook did something\n                 * that took too long or because the SysTick current-value register\n                 * is zero. */\n                if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )\n                {\n                    ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );\n                }\n\n                portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;\n\n                /* As the pending tick will be processed as soon as this\n                 * function exits, the tick value maintained by the tick is stepped\n                 * forward by one less than the time spent waiting. */\n                ulCompleteTickPeriods = xExpectedIdleTime - 1UL;\n            }\n            else\n            {\n                /* Something other than the tick interrupt ended the sleep. */\n\n                /* Use the SysTick current-value register to determine the\n                 * number of SysTick decrements remaining until the expected idle\n                 * time would have ended. */\n                ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n                #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )\n                {\n                    /* If the SysTick is not using the core clock, the current-\n                     * value register might still be zero here.  In that case, the\n                     * SysTick didn't load from the reload register, and there are\n                     * ulReloadValue decrements remaining in the expected idle\n                     * time, not zero. */\n                    if( ulSysTickDecrementsLeft == 0 )\n                    {\n                        ulSysTickDecrementsLeft = ulReloadValue;\n                    }\n                }\n                #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */\n\n                /* Work out how long the sleep lasted rounded to complete tick\n                 * periods (not the ulReload value which accounted for part\n                 * ticks). */\n                ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;\n\n                /* How many complete tick periods passed while the processor\n                 * was waiting? */\n                ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;\n\n                /* The reload value is set to whatever fraction of a single tick\n                 * period remains. */\n                portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;\n            }\n\n            /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,\n             * then set portNVIC_SYSTICK_LOAD_REG back to its standard value.  If\n             * the SysTick is not using the core clock, temporarily configure it to\n             * use the core clock.  This configuration forces the SysTick to load\n             * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next\n             * cycle of the other clock.  Then portNVIC_SYSTICK_LOAD_REG is ready\n             * to receive the standard value immediately. */\n            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n            portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n            #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )\n            {\n                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n            }\n            #else\n            {\n                /* The temporary usage of the core clock has served its purpose,\n                 * as described above.  Resume usage of the other clock. */\n                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\n\n                if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n                {\n                    /* The partial tick period already ended.  Be sure the SysTick\n                     * counts it only once. */\n                    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;\n                }\n\n                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n            }\n            #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */\n\n            /* Step the tick to account for any tick periods that elapsed. */\n            vTaskStepTick( ulCompleteTickPeriods );\n\n            /* Exit with interrupts enabled. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n        }\n    }\n#endif /* configUSE_TICKLESS_IDLE */\n/*-----------------------------------------------------------*/\n\n__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Calculate the constants required to configure the tick interrupt. */\n    #if ( configUSE_TICKLESS_IDLE == 1 )\n    {\n        ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );\n        xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;\n        ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\n    }\n    #endif /* configUSE_TICKLESS_IDLE */\n\n    /* Stop and reset the SysTick. */\n    portNVIC_SYSTICK_CTRL_REG = 0UL;\n    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n    /* Configure SysTick to interrupt at the requested rate. */\n    portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\n    portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvTaskExitError( void )\n{\n    volatile uint32_t ulDummy = 0UL;\n\n    /* A function that implements a task must not exit or attempt to return to\n     * its caller as there is nothing to return to. If a task wants to exit it\n     * should instead call vTaskDelete( NULL ). Artificially force an assert()\n     * to be triggered if configASSERT() is defined, then stop here so\n     * application writers can catch the error. */\n    configASSERT( ulCriticalNesting == ~0UL );\n    portDISABLE_INTERRUPTS();\n\n    while( ulDummy == 0 )\n    {\n        /* This file calls prvTaskExitError() after the scheduler has been\n         * started to remove a compiler warning about the function being\n         * defined but never called.  ulDummy is used purely to quieten other\n         * warnings about code appearing after this function is called - making\n         * ulDummy volatile makes the compiler think the function could return\n         * and therefore not output an 'unreachable code' warning for code that\n         * appears after it. */\n    }\n}\n/*-----------------------------------------------------------*/\n\n#if ( configENABLE_MPU == 1 )\n    static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */\n    {\n        #if defined( __ARMCC_VERSION )\n\n            /* Declaration when these variable are defined in code instead of being\n             * exported from linker scripts. */\n            extern uint32_t * __privileged_functions_start__;\n            extern uint32_t * __privileged_functions_end__;\n            extern uint32_t * __syscalls_flash_start__;\n            extern uint32_t * __syscalls_flash_end__;\n            extern uint32_t * __unprivileged_flash_start__;\n            extern uint32_t * __unprivileged_flash_end__;\n            extern uint32_t * __privileged_sram_start__;\n            extern uint32_t * __privileged_sram_end__;\n        #else /* if defined( __ARMCC_VERSION ) */\n            /* Declaration when these variable are exported from linker scripts. */\n            extern uint32_t __privileged_functions_start__[];\n            extern uint32_t __privileged_functions_end__[];\n            extern uint32_t __syscalls_flash_start__[];\n            extern uint32_t __syscalls_flash_end__[];\n            extern uint32_t __unprivileged_flash_start__[];\n            extern uint32_t __unprivileged_flash_end__[];\n            extern uint32_t __privileged_sram_start__[];\n            extern uint32_t __privileged_sram_end__[];\n        #endif /* defined( __ARMCC_VERSION ) */\n\n        /* The only permitted number of regions are 8 or 16. */\n        configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );\n\n        /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */\n        configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );\n\n        /* Check that the MPU is present. */\n        if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )\n        {\n            /* MAIR0 - Index 0. */\n            portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\n            /* MAIR0 - Index 1. */\n            portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\n\n            /* Setup privileged flash as Read Only so that privileged tasks can\n             * read it but not modify. */\n            portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_PRIVILEGED_READ_ONLY );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Setup unprivileged flash as Read Only by both privileged and\n             * unprivileged tasks. All tasks can read it but no-one can modify. */\n            portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_READ_ONLY );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Setup unprivileged syscalls flash as Read Only by both privileged\n             * and unprivileged tasks. All tasks can read it but no-one can modify. */\n            portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_READ_ONLY );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Setup RAM containing kernel data for privileged access only. */\n            portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\n                               ( portMPU_REGION_EXECUTE_NEVER );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Enable mem fault. */\n            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;\n\n            /* Enable MPU with privileged background access i.e. unmapped\n             * regions have privileged access. */\n            portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );\n        }\n    }\n#endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\n#if ( configENABLE_FPU == 1 )\n    static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */\n    {\n        #if ( configENABLE_TRUSTZONE == 1 )\n        {\n            /* Enable non-secure access to the FPU. */\n            SecureInit_EnableNSFPUAccess();\n        }\n        #endif /* configENABLE_TRUSTZONE */\n\n        /* CP10 = 11 ==> Full access to FPU i.e. both privileged and\n         * unprivileged code should be able to access FPU. CP11 should be\n         * programmed to the same value as CP10. */\n        *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |\n                            ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )\n                            );\n\n        /* ASPEN = 1 ==> Hardware should automatically preserve floating point\n         * context on exception entry and restore on exception return.\n         * LSPEN = 1 ==> Enable lazy context save of FP state. */\n        *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );\n    }\n#endif /* configENABLE_FPU */\n/*-----------------------------------------------------------*/\n\nvoid vPortYield( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Set a PendSV to request a context switch. */\n    portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\n\n    /* Barriers are normally not required but do ensure the code is\n     * completely within the specified behaviour for the architecture. */\n    __asm volatile ( \"dsb\" ::: \"memory\" );\n    __asm volatile ( \"isb\" );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */\n{\n    portDISABLE_INTERRUPTS();\n    ulCriticalNesting++;\n\n    /* Barriers are normally not required but do ensure the code is\n     * completely within the specified behaviour for the architecture. */\n    __asm volatile ( \"dsb\" ::: \"memory\" );\n    __asm volatile ( \"isb\" );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */\n{\n    configASSERT( ulCriticalNesting );\n    ulCriticalNesting--;\n\n    if( ulCriticalNesting == 0 )\n    {\n        portENABLE_INTERRUPTS();\n    }\n}\n/*-----------------------------------------------------------*/\n\nvoid SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */\n{\n    uint32_t ulPreviousMask;\n\n    ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();\n    {\n        /* Increment the RTOS tick. */\n        if( xTaskIncrementTick() != pdFALSE )\n        {\n            /* Pend a context switch. */\n            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\n        }\n    }\n    portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */\n{\n    #if ( configENABLE_MPU == 1 )\n        #if defined( __ARMCC_VERSION )\n\n            /* Declaration when these variable are defined in code instead of being\n             * exported from linker scripts. */\n            extern uint32_t * __syscalls_flash_start__;\n            extern uint32_t * __syscalls_flash_end__;\n        #else\n            /* Declaration when these variable are exported from linker scripts. */\n            extern uint32_t __syscalls_flash_start__[];\n            extern uint32_t __syscalls_flash_end__[];\n        #endif /* defined( __ARMCC_VERSION ) */\n    #endif /* configENABLE_MPU */\n\n    uint32_t ulPC;\n\n    #if ( configENABLE_TRUSTZONE == 1 )\n        uint32_t ulR0, ulR1;\n        extern TaskHandle_t pxCurrentTCB;\n        #if ( configENABLE_MPU == 1 )\n            uint32_t ulControl, ulIsTaskPrivileged;\n        #endif /* configENABLE_MPU */\n    #endif /* configENABLE_TRUSTZONE */\n    uint8_t ucSVCNumber;\n\n    /* Register are stored on the stack in the following order - R0, R1, R2, R3,\n     * R12, LR, PC, xPSR. */\n    ulPC = pulCallerStackAddress[ 6 ];\n    ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];\n\n    switch( ucSVCNumber )\n    {\n        #if ( configENABLE_TRUSTZONE == 1 )\n            case portSVC_ALLOCATE_SECURE_CONTEXT:\n\n                /* R0 contains the stack size passed as parameter to the\n                 * vPortAllocateSecureContext function. */\n                ulR0 = pulCallerStackAddress[ 0 ];\n\n                #if ( configENABLE_MPU == 1 )\n                {\n                    /* Read the CONTROL register value. */\n                    __asm volatile ( \"mrs %0, control\"  : \"=r\" ( ulControl ) );\n\n                    /* The task that raised the SVC is privileged if Bit[0]\n                     * in the CONTROL register is 0. */\n                    ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );\n\n                    /* Allocate and load a context for the secure task. */\n                    xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );\n                }\n                #else /* if ( configENABLE_MPU == 1 ) */\n                {\n                    /* Allocate and load a context for the secure task. */\n                    xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );\n                }\n                #endif /* configENABLE_MPU */\n\n                configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );\n                SecureContext_LoadContext( xSecureContext, pxCurrentTCB );\n                break;\n\n            case portSVC_FREE_SECURE_CONTEXT:\n\n                /* R0 contains TCB being freed and R1 contains the secure\n                 * context handle to be freed. */\n                ulR0 = pulCallerStackAddress[ 0 ];\n                ulR1 = pulCallerStackAddress[ 1 ];\n\n                /* Free the secure context. */\n                SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );\n                break;\n        #endif /* configENABLE_TRUSTZONE */\n\n        case portSVC_START_SCHEDULER:\n            #if ( configENABLE_TRUSTZONE == 1 )\n            {\n                /* De-prioritize the non-secure exceptions so that the\n                 * non-secure pendSV runs at the lowest priority. */\n                SecureInit_DePrioritizeNSExceptions();\n\n                /* Initialize the secure context management system. */\n                SecureContext_Init();\n            }\n            #endif /* configENABLE_TRUSTZONE */\n\n            #if ( configENABLE_FPU == 1 )\n            {\n                /* Setup the Floating Point Unit (FPU). */\n                prvSetupFPU();\n            }\n            #endif /* configENABLE_FPU */\n\n            /* Setup the context of the first task so that the first task starts\n             * executing. */\n            vRestoreContextOfFirstTask();\n            break;\n\n            #if ( configENABLE_MPU == 1 )\n                case portSVC_RAISE_PRIVILEGE:\n\n                    /* Only raise the privilege, if the svc was raised from any of\n                     * the system calls. */\n                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&\n                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )\n                    {\n                        vRaisePrivilege();\n                    }\n                    break;\n            #endif /* configENABLE_MPU */\n\n        default:\n            /* Incorrect SVC call. */\n            configASSERT( pdFALSE );\n    }\n}\n/*-----------------------------------------------------------*/\n/* *INDENT-OFF* */\n#if ( configENABLE_MPU == 1 )\n    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,\n                                         StackType_t * pxEndOfStack,\n                                         TaskFunction_t pxCode,\n                                         void * pvParameters,\n                                         BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */\n#else\n    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,\n                                         StackType_t * pxEndOfStack,\n                                         TaskFunction_t pxCode,\n                                         void * pvParameters ) /* PRIVILEGED_FUNCTION */\n#endif /* configENABLE_MPU */\n/* *INDENT-ON* */\n{\n    /* Simulate the stack frame as it would be created by a context switch\n     * interrupt. */\n    #if ( portPRELOAD_REGISTERS == 0 )\n    {\n        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\n        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\n        pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */\n        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */\n        pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */\n        *pxTopOfStack = portINITIAL_EXC_RETURN;\n\n        #if ( configENABLE_MPU == 1 )\n        {\n            pxTopOfStack--;\n\n            if( xRunPrivileged == pdTRUE )\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n            else\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n        }\n        #endif /* configENABLE_MPU */\n\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\n\n        #if ( configENABLE_TRUSTZONE == 1 )\n        {\n            pxTopOfStack--;\n            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\n        }\n        #endif /* configENABLE_TRUSTZONE */\n    }\n    #else /* portPRELOAD_REGISTERS */\n    {\n        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\n        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04 */\n        pxTopOfStack--;\n        *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN */\n\n        #if ( configENABLE_MPU == 1 )\n        {\n            pxTopOfStack--;\n\n            if( xRunPrivileged == pdTRUE )\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n            else\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n        }\n        #endif /* configENABLE_MPU */\n\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\n\n        #if ( configENABLE_TRUSTZONE == 1 )\n        {\n            pxTopOfStack--;\n            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\n        }\n        #endif /* configENABLE_TRUSTZONE */\n    }\n    #endif /* portPRELOAD_REGISTERS */\n\n    return pxTopOfStack;\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Make PendSV, CallSV and SysTick the same priority as the kernel. */\n    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;\n    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;\n\n    #if ( configENABLE_MPU == 1 )\n    {\n        /* Setup the Memory Protection Unit (MPU). */\n        prvSetupMPU();\n    }\n    #endif /* configENABLE_MPU */\n\n    /* Start the timer that generates the tick ISR. Interrupts are disabled\n     * here already. */\n    vPortSetupTimerInterrupt();\n\n    /* Initialize the critical nesting count ready for the first task. */\n    ulCriticalNesting = 0;\n\n    /* Start the first task. */\n    vStartFirstTask();\n\n    /* Should never get here as the tasks will now be executing. Call the task\n     * exit error function to prevent compiler warnings about a static function\n     * not being called in the case that the application writer overrides this\n     * functionality by defining configTASK_RETURN_ADDRESS. Call\n     * vTaskSwitchContext() so link time optimization does not remove the\n     * symbol. */\n    vTaskSwitchContext();\n    prvTaskExitError();\n\n    /* Should not get here. */\n    return 0;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Not implemented in ports where there is nothing to return to.\n     * Artificially force an assert. */\n    configASSERT( ulCriticalNesting == 1000UL );\n}\n/*-----------------------------------------------------------*/\n\n#if ( configENABLE_MPU == 1 )\n    void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,\n                                    const struct xMEMORY_REGION * const xRegions,\n                                    StackType_t * pxBottomOfStack,\n                                    uint32_t ulStackDepth )\n    {\n        uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;\n        int32_t lIndex = 0;\n\n        #if defined( __ARMCC_VERSION )\n\n            /* Declaration when these variable are defined in code instead of being\n             * exported from linker scripts. */\n            extern uint32_t * __privileged_sram_start__;\n            extern uint32_t * __privileged_sram_end__;\n        #else\n            /* Declaration when these variable are exported from linker scripts. */\n            extern uint32_t __privileged_sram_start__[];\n            extern uint32_t __privileged_sram_end__[];\n        #endif /* defined( __ARMCC_VERSION ) */\n\n        /* Setup MAIR0. */\n        xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\n        xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\n\n        /* This function is called automatically when the task is created - in\n         * which case the stack region parameters will be valid.  At all other\n         * times the stack parameters will not be valid and it is assumed that\n         * the stack region has already been configured. */\n        if( ulStackDepth > 0 )\n        {\n            ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;\n            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;\n\n            /* If the stack is within the privileged SRAM, do not protect it\n             * using a separate MPU region. This is needed because privileged\n             * SRAM is already protected using an MPU region and ARMv8-M does\n             * not allow overlapping MPU regions. */\n            if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) &&\n                ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) )\n            {\n                xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0;\n                xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0;\n            }\n            else\n            {\n                /* Define the region that allows access to the stack. */\n                ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK;\n                ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\n\n                xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |\n                                                             ( portMPU_REGION_NON_SHAREABLE ) |\n                                                             ( portMPU_REGION_READ_WRITE ) |\n                                                             ( portMPU_REGION_EXECUTE_NEVER );\n\n                xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) |\n                                                             ( portMPU_RLAR_ATTR_INDEX0 ) |\n                                                             ( portMPU_RLAR_REGION_ENABLE );\n            }\n        }\n\n        /* User supplied configurable regions. */\n        for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )\n        {\n            /* If xRegions is NULL i.e. the task has not specified any MPU\n             * region, the else part ensures that all the configurable MPU\n             * regions are invalidated. */\n            if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )\n            {\n                /* Translate the generic region definition contained in xRegions\n                 * into the ARMv8 specific MPU settings that are then stored in\n                 * xMPUSettings. */\n                ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;\n                ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;\n                ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\n\n                /* Start address. */\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |\n                                                                          ( portMPU_REGION_NON_SHAREABLE );\n\n                /* RO/RW. */\n                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )\n                {\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );\n                }\n                else\n                {\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );\n                }\n\n                /* XN. */\n                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )\n                {\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );\n                }\n\n                /* End Address. */\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |\n                                                                          ( portMPU_RLAR_REGION_ENABLE );\n\n                /* Normal memory/ Device memory. */\n                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )\n                {\n                    /* Attr1 in MAIR0 is configured as device memory. */\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;\n                }\n                else\n                {\n                    /* Attr0 in MAIR0 is configured as normal memory. */\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;\n                }\n            }\n            else\n            {\n                /* Invalidate the region. */\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;\n            }\n\n            lIndex++;\n        }\n    }\n#endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\nBaseType_t xPortIsInsideInterrupt( void )\n{\n    uint32_t ulCurrentInterrupt;\n    BaseType_t xReturn;\n\n    /* Obtain the number of the currently executing interrupt. Interrupt Program\n     * Status Register (IPSR) holds the exception number of the currently-executing\n     * exception or zero for Thread mode.*/\n    __asm volatile ( \"mrs %0, ipsr\" : \"=r\" ( ulCurrentInterrupt )::\"memory\" );\n\n    if( ulCurrentInterrupt == 0 )\n    {\n        xReturn = pdFALSE;\n    }\n    else\n    {\n        xReturn = pdTRUE;\n    }\n\n    return xReturn;\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM23/non_secure/portasm.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Standard includes. */\n#include <stdint.h>\n\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION\n * is defined correctly and privileged functions are placed in correct sections. */\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/* Portasm includes. */\n#include \"portasm.h\"\n\n/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the\n * header files. */\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n#if ( configENABLE_FPU == 1 )\n    #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.\n#endif\n\nvoid vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr  r2, pxCurrentTCBConst2\t\t\t\t\t\t\\n\"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n        \"\tldr  r3, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Read pxCurrentTCB. */\n        \"\tldr  r0, [r3]\t\t\t\t\t\t\t\t\t\\n\"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"\tdmb\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Complete outstanding transfers before disabling MPU. */\n            \"\tldr r2, xMPUCTRLConst2\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n            \"\tldr r4, [r2]\t\t\t\t\t\t\t\t\\n\"/* Read the value of MPU_CTRL. */\n            \"\tmovs r5, #1\t\t\t\t\t\t\t\t\t\\n\"/* r5 = 1. */\n            \"\tbics r4, r5\t\t\t\t\t\t\t\t\t\\n\"/* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */\n            \"\tstr r4, [r2]\t\t\t\t\t\t\t\t\\n\"/* Disable MPU. */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tadds r3, #4\t\t\t\t\t\t\t\t\t\\n\"/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\n            \"\tldr  r4, [r3]\t\t\t\t\t\t\t\t\\n\"/* r4 = *r3 i.e. r4 = MAIR0. */\n            \"\tldr  r2, xMAIR0Const2\t\t\t\t\t\t\\n\"/* r2 = 0xe000edc0 [Location of MAIR0]. */\n            \"\tstr  r4, [r2]\t\t\t\t\t\t\t\t\\n\"/* Program MAIR0. */\n            \"\tldr  r2, xRNRConst2\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed98 [Location of RNR]. */\n            \"\tadds r3, #4\t\t\t\t\t\t\t\t\t\\n\"/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */\n            \"\tmovs r5, #4\t\t\t\t\t\t\t\t\t\\n\"/* r5 = 4. */\n            \"\tstr  r5, [r2]\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 4. */\n            \"\tldmia r3!, {r6,r7}\t\t\t\t\t\t\t\\n\"/* Read first set of RBAR/RLAR from TCB. */\n            \"\tldr  r4, xRBARConst2\t\t\t\t\t\t\\n\"/* r4 = 0xe000ed9c [Location of RBAR]. */\n            \"\tstmia r4!, {r6,r7}\t\t\t\t\t\t\t\\n\"/* Write first set of RBAR/RLAR registers. */\n            \"\tmovs r5, #5\t\t\t\t\t\t\t\t\t\\n\"/* r5 = 5. */\n            \"\tstr  r5, [r2]\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 5. */\n            \"\tldmia r3!, {r6,r7}\t\t\t\t\t\t\t\\n\"/* Read second set of RBAR/RLAR from TCB. */\n            \"\tldr  r4, xRBARConst2\t\t\t\t\t\t\\n\"/* r4 = 0xe000ed9c [Location of RBAR]. */\n            \"\tstmia r4!, {r6,r7}\t\t\t\t\t\t\t\\n\"/* Write second set of RBAR/RLAR registers. */\n            \"\tmovs r5, #6\t\t\t\t\t\t\t\t\t\\n\"/* r5 = 6. */\n            \"\tstr  r5, [r2]\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 6. */\n            \"\tldmia r3!, {r6,r7}\t\t\t\t\t\t\t\\n\"/* Read third set of RBAR/RLAR from TCB. */\n            \"\tldr  r4, xRBARConst2\t\t\t\t\t\t\\n\"/* r4 = 0xe000ed9c [Location of RBAR]. */\n            \"\tstmia r4!, {r6,r7}\t\t\t\t\t\t\t\\n\"/* Write third set of RBAR/RLAR registers. */\n            \"\tmovs r5, #7\t\t\t\t\t\t\t\t\t\\n\"/* r5 = 7. */\n            \"\tstr  r5, [r2]\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 7. */\n            \"\tldmia r3!, {r6,r7}\t\t\t\t\t\t\t\\n\"/* Read fourth set of RBAR/RLAR from TCB. */\n            \"\tldr  r4, xRBARConst2\t\t\t\t\t\t\\n\"/* r4 = 0xe000ed9c [Location of RBAR]. */\n            \"\tstmia r4!, {r6,r7}\t\t\t\t\t\t\t\\n\"/* Write fourth set of RBAR/RLAR registers. */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tldr r2, xMPUCTRLConst2\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n            \"\tldr r4, [r2]\t\t\t\t\t\t\t\t\\n\"/* Read the value of MPU_CTRL. */\n            \"\tmovs r5, #1\t\t\t\t\t\t\t\t\t\\n\"/* r5 = 1. */\n            \"\torrs r4, r5\t\t\t\t\t\t\t\t\t\\n\"/* r4 = r4 | r5 i.e. Set the bit 0 in r4. */\n            \"\tstr r4, [r2]\t\t\t\t\t\t\t\t\\n\"/* Enable MPU. */\n            \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Force memory writes before continuing. */\n        #endif /* configENABLE_MPU */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"\tldm  r0!, {r1-r4}\t\t\t\t\t\t\t\\n\"/* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */\n            \"\tldr  r5, xSecureContextConst2\t\t\t\t\\n\"\n            \"\tstr  r1, [r5]\t\t\t\t\t\t\t\t\\n\"/* Set xSecureContext to this task's value for the same. */\n            \"\tmsr  psplim, r2\t\t\t\t\t\t\t\t\\n\"/* Set this task's PSPLIM value. */\n            \"\tmsr  control, r3\t\t\t\t\t\t\t\\n\"/* Set this task's CONTROL value. */\n            \"\tadds r0, #32\t\t\t\t\t\t\t\t\\n\"/* Discard everything up to r0. */\n            \"\tmsr  psp, r0\t\t\t\t\t\t\t\t\\n\"/* This is now the new top of stack to use in the task. */\n            \"\tisb\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tbx   r4\t\t\t\t\t\t\t\t\t\t\\n\"/* Finally, branch to EXC_RETURN. */\n        #else /* configENABLE_MPU */\n            \"\tldm  r0!, {r1-r3}\t\t\t\t\t\t\t\\n\"/* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */\n            \"\tldr  r4, xSecureContextConst2\t\t\t\t\\n\"\n            \"\tstr  r1, [r4]\t\t\t\t\t\t\t\t\\n\"/* Set xSecureContext to this task's value for the same. */\n            \"\tmsr  psplim, r2\t\t\t\t\t\t\t\t\\n\"/* Set this task's PSPLIM value. */\n            \"\tmovs r1, #2\t\t\t\t\t\t\t\t\t\\n\"/* r1 = 2. */\n            \"\tmsr  CONTROL, r1\t\t\t\t\t\t\t\\n\"/* Switch to use PSP in the thread mode. */\n            \"\tadds r0, #32\t\t\t\t\t\t\t\t\\n\"/* Discard everything up to r0. */\n            \"\tmsr  psp, r0\t\t\t\t\t\t\t\t\\n\"/* This is now the new top of stack to use in the task. */\n            \"\tisb\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tbx   r3\t\t\t\t\t\t\t\t\t\t\\n\"/* Finally, branch to EXC_RETURN. */\n        #endif /* configENABLE_MPU */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.align 4\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"pxCurrentTCBConst2: .word pxCurrentTCB\t\t\t\t\\n\"\n        \"xSecureContextConst2: .word xSecureContext\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"xMPUCTRLConst2: .word 0xe000ed94\t\t\t\t\\n\"\n            \"xMAIR0Const2: .word 0xe000edc0\t\t\t\t\t\\n\"\n            \"xRNRConst2: .word 0xe000ed98\t\t\t\t\t\\n\"\n            \"xRBARConst2: .word 0xe000ed9c\t\t\t\t\t\\n\"\n        #endif /* configENABLE_MPU */\n    );\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrs r0, control\t\t\t\t\t\t\t\t\t\\n\"/* r0 = CONTROL. */\n        \"\tmovs r1, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* r1 = 1. */\n        \"\ttst r0, r1\t\t\t\t\t\t\t\t\t\t\\n\"/* Perform r0 & r1 (bitwise AND) and update the conditions flag. */\n        \"\tbeq running_privileged\t\t\t\t\t\t\t\\n\"/* If the result of previous AND operation was 0, branch. */\n        \"\tmovs r0, #0\t\t\t\t\t\t\t\t\t\t\\n\"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return. */\n        \" running_privileged:\t\t\t\t\t\t\t\t\\n\"\n        \"\tmovs r0, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return. */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.align 4\t\t\t\t\t\t\t\t\t\t\\n\"\n        ::: \"r0\", \"r1\", \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrs r0, control\t\t\t\t\t\t\t\t\t\\n\"/* Read the CONTROL register. */\n        \"\tmovs r1, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* r1 = 1. */\n        \"\tbics r0, r1\t\t\t\t\t\t\t\t\t\t\\n\"/* Clear the bit 0. */\n        \"\tmsr control, r0\t\t\t\t\t\t\t\t\t\\n\"/* Write back the new CONTROL value. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return to the caller. */\n        ::: \"r0\", \"r1\", \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vResetPrivilege( void ) /* __attribute__ (( naked )) */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrs r0, control\t\t\t\t\t\t\t\t\t\\n\"/* r0 = CONTROL. */\n        \"\tmovs r1, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* r1 = 1. */\n        \"\torrs r0, r1\t\t\t\t\t\t\t\t\t\t\\n\"/* r0 = r0 | r1. */\n        \"\tmsr control, r0\t\t\t\t\t\t\t\t\t\\n\"/* CONTROL = r0. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return to the caller. */\n        ::: \"r0\", \"r1\", \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r0, xVTORConst\t\t\t\t\t\t\t\t\\n\"/* Use the NVIC offset register to locate the stack. */\n        \"\tldr r0, [r0]\t\t\t\t\t\t\t\t\t\\n\"/* Read the VTOR register which gives the address of vector table. */\n        \"\tldr r0, [r0]\t\t\t\t\t\t\t\t\t\\n\"/* The first entry in vector table is stack pointer. */\n        \"\tmsr msp, r0\t\t\t\t\t\t\t\t\t\t\\n\"/* Set the MSP back to the start of the stack. */\n        \"\tcpsie i\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Globally enable interrupts. */\n        \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tsvc %0\t\t\t\t\t\t\t\t\t\t\t\\n\"/* System call to start the first task. */\n        \"\tnop\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"   .align 4\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"xVTORConst: .word 0xe000ed08\t\t\t\t\t\t\\n\"\n        ::\"i\" ( portSVC_START_SCHEDULER ) : \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nuint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrs r0, PRIMASK\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tcpsid i\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        ::: \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmsr PRIMASK, r0\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        ::: \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.extern SecureContext_SaveContext\t\t\t\t\\n\"\n        \"\t.extern SecureContext_LoadContext\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r3, xSecureContextConst\t\t\t\t\t\t\\n\"/* Read the location of xSecureContext i.e. &( xSecureContext ). */\n        \"\tldr r0, [r3]\t\t\t\t\t\t\t\t\t\\n\"/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */\n        \"\tldr r3, pxCurrentTCBConst\t\t\t\t\t\t\\n\"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n        \"\tldr r1, [r3]\t\t\t\t\t\t\t\t\t\\n\"/* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later.*/\n        \"\tmrs r2, psp\t\t\t\t\t\t\t\t\t\t\\n\"/* Read PSP in r2. */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tcbz r0, save_ns_context\t\t\t\t\t\t\t\\n\"/* No secure context to save. */\n        \"\tpush {r0-r2, r14}\t\t\t\t\t\t\t\t\\n\"\n        \"\tbl SecureContext_SaveContext\t\t\t\t\t\\n\"/* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */\n        \"\tpop {r0-r3}\t\t\t\t\t\t\t\t\t\t\\n\"/* LR is now in r3. */\n        \"\tmov lr, r3\t\t\t\t\t\t\t\t\t\t\\n\"/* LR = r3. */\n        \"\tlsls r1, r3, #25\t\t\t\t\t\t\t\t\\n\"/* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\n        \"\tbpl save_ns_context\t\t\t\t\t\t\t\t\\n\"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\n        \"\tldr r3, pxCurrentTCBConst\t\t\t\t\t\t\\n\"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n        \"\tldr r1, [r3]\t\t\t\t\t\t\t\t\t\\n\"/* Read pxCurrentTCB. */\n        #if ( configENABLE_MPU == 1 )\n            \"\tsubs r2, r2, #16\t\t\t\t\t\t\t\\n\"/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */\n            \"\tstr r2, [r1]\t\t\t\t\t\t\t\t\\n\"/* Save the new top of stack in TCB. */\n            \"\tmrs r1, psplim\t\t\t\t\t\t\t\t\\n\"/* r1 = PSPLIM. */\n            \"\tmrs r3, control\t\t\t\t\t\t\t\t\\n\"/* r3 = CONTROL. */\n            \"\tmov r4, lr\t\t\t\t\t\t\t\t\t\\n\"/* r4 = LR/EXC_RETURN. */\n            \"\tstmia r2!, {r0, r1, r3, r4}\t\t\t\t\t\\n\"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\n        #else /* configENABLE_MPU */\n            \"\tsubs r2, r2, #12\t\t\t\t\t\t\t\\n\"/* Make space for xSecureContext, PSPLIM and LR on the stack. */\n            \"\tstr r2, [r1]\t\t\t\t\t\t\t\t\\n\"/* Save the new top of stack in TCB. */\n            \"\tmrs r1, psplim\t\t\t\t\t\t\t\t\\n\"/* r1 = PSPLIM. */\n            \"\tmov r3, lr\t\t\t\t\t\t\t\t\t\\n\"/* r3 = LR/EXC_RETURN. */\n            \"\tstmia r2!, {r0, r1, r3}\t\t\t\t\t\t\\n\"/* Store xSecureContext, PSPLIM and LR on the stack. */\n        #endif /* configENABLE_MPU */\n        \"\tb select_next_task\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \" save_ns_context:\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r3, pxCurrentTCBConst\t\t\t\t\t\t\\n\"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n        \"\tldr r1, [r3]\t\t\t\t\t\t\t\t\t\\n\"/* Read pxCurrentTCB. */\n        #if ( configENABLE_MPU == 1 )\n            \"\tsubs r2, r2, #48\t\t\t\t\t\t\t\\n\"/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */\n            \"\tstr r2, [r1]\t\t\t\t\t\t\t\t\\n\"/* Save the new top of stack in TCB. */\n            \"\tadds r2, r2, #16\t\t\t\t\t\t\t\\n\"/* r2 = r2 + 16. */\n            \"\tstmia r2!, {r4-r7}\t\t\t\t\t\t\t\\n\"/* Store the low registers that are not saved automatically. */\n            \"\tmov r4, r8\t\t\t\t\t\t\t\t\t\\n\"/* r4 = r8. */\n            \"\tmov r5, r9\t\t\t\t\t\t\t\t\t\\n\"/* r5 = r9. */\n            \"\tmov r6, r10\t\t\t\t\t\t\t\t\t\\n\"/* r6 = r10. */\n            \"\tmov r7, r11\t\t\t\t\t\t\t\t\t\\n\"/* r7 = r11. */\n            \"\tstmia r2!, {r4-r7}\t\t\t\t\t\t\t\\n\"/* Store the high registers that are not saved automatically. */\n            \"\tmrs r1, psplim\t\t\t\t\t\t\t\t\\n\"/* r1 = PSPLIM. */\n            \"\tmrs r3, control\t\t\t\t\t\t\t\t\\n\"/* r3 = CONTROL. */\n            \"\tmov r4, lr\t\t\t\t\t\t\t\t\t\\n\"/* r4 = LR/EXC_RETURN. */\n            \"\tsubs r2, r2, #48\t\t\t\t\t\t\t\\n\"/* r2 = r2 - 48. */\n            \"\tstmia r2!, {r0, r1, r3, r4}\t\t\t\t\t\\n\"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\n        #else /* configENABLE_MPU */\n            \"\tsubs r2, r2, #44\t\t\t\t\t\t\t\\n\"/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */\n            \"\tstr r2, [r1]\t\t\t\t\t\t\t\t\\n\"/* Save the new top of stack in TCB. */\n            \"\tmrs r1, psplim\t\t\t\t\t\t\t\t\\n\"/* r1 = PSPLIM. */\n            \"\tmov r3, lr\t\t\t\t\t\t\t\t\t\\n\"/* r3 = LR/EXC_RETURN. */\n            \"\tstmia r2!, {r0, r1, r3-r7}\t\t\t\t\t\\n\"/* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */\n            \"\tmov r4, r8\t\t\t\t\t\t\t\t\t\\n\"/* r4 = r8. */\n            \"\tmov r5, r9\t\t\t\t\t\t\t\t\t\\n\"/* r5 = r9. */\n            \"\tmov r6, r10\t\t\t\t\t\t\t\t\t\\n\"/* r6 = r10. */\n            \"\tmov r7, r11\t\t\t\t\t\t\t\t\t\\n\"/* r7 = r11. */\n            \"\tstmia r2!, {r4-r7}\t\t\t\t\t\t\t\\n\"/* Store the high registers that are not saved automatically. */\n        #endif /* configENABLE_MPU */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \" select_next_task:\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tcpsid i\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tbl vTaskSwitchContext\t\t\t\t\t\t\t\\n\"\n        \"\tcpsie i\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r3, pxCurrentTCBConst\t\t\t\t\t\t\\n\"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n        \"\tldr r1, [r3]\t\t\t\t\t\t\t\t\t\\n\"/* Read pxCurrentTCB. */\n        \"\tldr r2, [r1]\t\t\t\t\t\t\t\t\t\\n\"/* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"\tdmb\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Complete outstanding transfers before disabling MPU. */\n            \"\tldr r3, xMPUCTRLConst\t\t\t\t\t\t\\n\"/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */\n            \"\tldr r4, [r3]\t\t\t\t\t\t\t\t\\n\"/* Read the value of MPU_CTRL. */\n            \"\tmovs r5, #1\t\t\t\t\t\t\t\t\t\\n\"/* r5 = 1. */\n            \"\tbics r4, r5\t\t\t\t\t\t\t\t\t\\n\"/* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */\n            \"\tstr r4, [r3]\t\t\t\t\t\t\t\t\\n\"/* Disable MPU. */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tadds r1, #4\t\t\t\t\t\t\t\t\t\\n\"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\n            \"\tldr r4, [r1]\t\t\t\t\t\t\t\t\\n\"/* r4 = *r1 i.e. r4 = MAIR0. */\n            \"\tldr r3, xMAIR0Const\t\t\t\t\t\t\t\\n\"/* r3 = 0xe000edc0 [Location of MAIR0]. */\n            \"\tstr r4, [r3]\t\t\t\t\t\t\t\t\\n\"/* Program MAIR0. */\n            \"\tldr r4, xRNRConst\t\t\t\t\t\t\t\\n\"/* r4 = 0xe000ed98 [Location of RNR]. */\n            \"\tadds r1, #4\t\t\t\t\t\t\t\t\t\\n\"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\n            \"\tmovs r5, #4\t\t\t\t\t\t\t\t\t\\n\"/* r5 = 4. */\n            \"\tstr  r5, [r4]\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 4. */\n            \"\tldmia r1!, {r6,r7}\t\t\t\t\t\t\t\\n\"/* Read first set of RBAR/RLAR from TCB. */\n            \"\tldr  r3, xRBARConst\t\t\t\t\t\t\t\\n\"/* r3 = 0xe000ed9c [Location of RBAR]. */\n            \"\tstmia r3!, {r6,r7}\t\t\t\t\t\t\t\\n\"/* Write first set of RBAR/RLAR registers. */\n            \"\tmovs r5, #5\t\t\t\t\t\t\t\t\t\\n\"/* r5 = 5. */\n            \"\tstr  r5, [r4]\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 5. */\n            \"\tldmia r1!, {r6,r7}\t\t\t\t\t\t\t\\n\"/* Read second set of RBAR/RLAR from TCB. */\n            \"\tldr  r3, xRBARConst\t\t\t\t\t\t\t\\n\"/* r3 = 0xe000ed9c [Location of RBAR]. */\n            \"\tstmia r3!, {r6,r7}\t\t\t\t\t\t\t\\n\"/* Write second set of RBAR/RLAR registers. */\n            \"\tmovs r5, #6\t\t\t\t\t\t\t\t\t\\n\"/* r5 = 6. */\n            \"\tstr  r5, [r4]\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 6. */\n            \"\tldmia r1!, {r6,r7}\t\t\t\t\t\t\t\\n\"/* Read third set of RBAR/RLAR from TCB. */\n            \"\tldr  r3, xRBARConst\t\t\t\t\t\t\t\\n\"/* r3 = 0xe000ed9c [Location of RBAR]. */\n            \"\tstmia r3!, {r6,r7}\t\t\t\t\t\t\t\\n\"/* Write third set of RBAR/RLAR registers. */\n            \"\tmovs r5, #7\t\t\t\t\t\t\t\t\t\\n\"/* r5 = 7. */\n            \"\tstr  r5, [r4]\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 7. */\n            \"\tldmia r1!, {r6,r7}\t\t\t\t\t\t\t\\n\"/* Read fourth set of RBAR/RLAR from TCB. */\n            \"\tldr  r3, xRBARConst\t\t\t\t\t\t\t\\n\"/* r3 = 0xe000ed9c [Location of RBAR]. */\n            \"\tstmia r3!, {r6,r7}\t\t\t\t\t\t\t\\n\"/* Write fourth set of RBAR/RLAR registers. */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tldr r3, xMPUCTRLConst\t\t\t\t\t\t\\n\"/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */\n            \"\tldr r4, [r3]\t\t\t\t\t\t\t\t\\n\"/* Read the value of MPU_CTRL. */\n            \"\tmovs r5, #1\t\t\t\t\t\t\t\t\t\\n\"/* r5 = 1. */\n            \"\torrs r4, r5\t\t\t\t\t\t\t\t\t\\n\"/* r4 = r4 | r5 i.e. Set the bit 0 in r4. */\n            \"\tstr r4, [r3]\t\t\t\t\t\t\t\t\\n\"/* Enable MPU. */\n            \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Force memory writes before continuing. */\n        #endif /* configENABLE_MPU */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"\tldmia r2!, {r0, r1, r3, r4}\t\t\t\t\t\\n\"/* Read from stack - r0 = xSecureContext, r1 = PSPLIM, r3 = CONTROL and r4 = LR. */\n            \"\tmsr psplim, r1\t\t\t\t\t\t\t\t\\n\"/* Restore the PSPLIM register value for the task. */\n            \"\tmsr control, r3\t\t\t\t\t\t\t\t\\n\"/* Restore the CONTROL register value for the task. */\n            \"\tmov lr, r4\t\t\t\t\t\t\t\t\t\\n\"/* LR = r4. */\n            \"\tldr r3, xSecureContextConst\t\t\t\t\t\\n\"/* Read the location of xSecureContext i.e. &( xSecureContext ). */\n            \"\tstr r0, [r3]\t\t\t\t\t\t\t\t\\n\"/* Restore the task's xSecureContext. */\n            \"\tcbz r0, restore_ns_context\t\t\t\t\t\\n\"/* If there is no secure context for the task, restore the non-secure context. */\n             \"\tldr r3, pxCurrentTCBConst\t\t\t\t\t\\n\"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n            \"\tldr r1, [r3]\t\t\t\t\t\t\t\t\\n\"/* Read pxCurrentTCB. */\n            \"\tpush {r2, r4}\t\t\t\t\t\t\t\t\\n\"\n            \"\tbl SecureContext_LoadContext\t\t\t\t\\n\"/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */\n            \"\tpop {r2, r4}\t\t\t\t\t\t\t\t\\n\"\n            \"\tmov lr, r4\t\t\t\t\t\t\t\t\t\\n\"/* LR = r4. */\n            \"\tlsls r1, r4, #25\t\t\t\t\t\t\t\\n\"/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\n            \"\tbpl restore_ns_context\t\t\t\t\t\t\\n\"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\n            \"\tmsr psp, r2\t\t\t\t\t\t\t\t\t\\n\"/* Remember the new top of stack for the task. */\n            \"\tbx lr\t\t\t\t\t\t\t\t\t\t\\n\"\n        #else /* configENABLE_MPU */\n            \"\tldmia r2!, {r0, r1, r4}\t\t\t\t\t\t\\n\"/* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */\n            \"\tmsr psplim, r1\t\t\t\t\t\t\t\t\\n\"/* Restore the PSPLIM register value for the task. */\n            \"\tmov lr, r4\t\t\t\t\t\t\t\t\t\\n\"/* LR = r4. */\n            \"\tldr r3, xSecureContextConst\t\t\t\t\t\\n\"/* Read the location of xSecureContext i.e. &( xSecureContext ). */\n            \"\tstr r0, [r3]\t\t\t\t\t\t\t\t\\n\"/* Restore the task's xSecureContext. */\n            \"\tcbz r0, restore_ns_context\t\t\t\t\t\\n\"/* If there is no secure context for the task, restore the non-secure context. */\n            \"\tldr r3, pxCurrentTCBConst\t\t\t\t\t\\n\"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n            \"\tldr r1, [r3]\t\t\t\t\t\t\t\t\\n\"/* Read pxCurrentTCB. */\n            \"\tpush {r2, r4}\t\t\t\t\t\t\t\t\\n\"\n            \"\tbl SecureContext_LoadContext\t\t\t\t\\n\"/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */\n            \"\tpop {r2, r4}\t\t\t\t\t\t\t\t\\n\"\n            \"\tmov lr, r4\t\t\t\t\t\t\t\t\t\\n\"/* LR = r4. */\n            \"\tlsls r1, r4, #25\t\t\t\t\t\t\t\\n\"/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\n            \"\tbpl restore_ns_context\t\t\t\t\t\t\\n\"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\n            \"\tmsr psp, r2\t\t\t\t\t\t\t\t\t\\n\"/* Remember the new top of stack for the task. */\n            \"\tbx lr\t\t\t\t\t\t\t\t\t\t\\n\"\n        #endif /* configENABLE_MPU */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \" restore_ns_context:\t\t\t\t\t\t\t\t\\n\"\n        \"\tadds r2, r2, #16\t\t\t\t\t\t\t\t\\n\"/* Move to the high registers. */\n        \"\tldmia r2!, {r4-r7}\t\t\t\t\t\t\t\t\\n\"/* Restore the high registers that are not automatically restored. */\n        \"\tmov r8, r4\t\t\t\t\t\t\t\t\t\t\\n\"/* r8 = r4. */\n        \"\tmov r9, r5\t\t\t\t\t\t\t\t\t\t\\n\"/* r9 = r5. */\n        \"\tmov r10, r6\t\t\t\t\t\t\t\t\t\t\\n\"/* r10 = r6. */\n        \"\tmov r11, r7\t\t\t\t\t\t\t\t\t\t\\n\"/* r11 = r7. */\n        \"\tmsr psp, r2\t\t\t\t\t\t\t\t\t\t\\n\"/* Remember the new top of stack for the task. */\n        \"\tsubs r2, r2, #32\t\t\t\t\t\t\t\t\\n\"/* Go back to the low registers. */\n        \"\tldmia r2!, {r4-r7}\t\t\t\t\t\t\t\t\\n\"/* Restore the low registers that are not automatically restored. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.align 4\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"pxCurrentTCBConst: .word pxCurrentTCB\t\t\t\t\\n\"\n        \"xSecureContextConst: .word xSecureContext\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"xMPUCTRLConst: .word 0xe000ed94\t\t\t\t\\n\"\n            \"xMAIR0Const: .word 0xe000edc0\t\t\t\t\t\\n\"\n            \"xRNRConst: .word 0xe000ed98\t\t\t\t\t\\n\"\n            \"xRBARConst: .word 0xe000ed9c\t\t\t\t\t\\n\"\n        #endif /* configENABLE_MPU */\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmovs r0, #4\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmov r1, lr\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\ttst r0, r1\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tbeq stacking_used_msp\t\t\t\t\t\t\t\\n\"\n        \"\tmrs r0, psp\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r2, svchandler_address_const\t\t\t\t\\n\"\n        \"\tbx r2\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \" stacking_used_msp:\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrs r0, msp\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r2, svchandler_address_const\t\t\t\t\\n\"\n        \"\tbx r2\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.align 4\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"svchandler_address_const: .word vPortSVCHandler_C\t\\n\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tsvc %0\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Secure context is allocated in the supervisor call. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return. */\n        ::\"i\" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r2, [r0]\t\t\t\t\t\t\t\t\t\\n\"/* The first item in the TCB is the top of the stack. */\n        \"\tldr r1, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* The first item on the stack is the task's xSecureContext. */\n        \"\tcmp r1, #0\t\t\t\t\t\t\t\t\t\t\\n\"/* Raise svc if task's xSecureContext is not NULL. */\n        \"\tbne free_secure_context\t\t\t\t\t\t\t\\n\"/* Branch if r1 != 0. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* There is no secure context (xSecureContext is NULL). */\n        \" free_secure_context:\t\t\t\t\t\t\t\t\\n\"\n        \"\tsvc %0\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Secure context is freed in the supervisor call. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return. */\n        ::\"i\" ( portSVC_FREE_SECURE_CONTEXT ) : \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM23/non_secure/portasm.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef __PORT_ASM_H__\n#define __PORT_ASM_H__\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n\n/* MPU wrappers includes. */\n#include \"mpu_wrappers.h\"\n\n/**\n * @brief Restore the context of the first task so that the first task starts\n * executing.\n */\nvoid vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Checks whether or not the processor is privileged.\n *\n * @return 1 if the processor is already privileged, 0 otherwise.\n */\nBaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );\n\n/**\n * @brief Raises the privilege level by clearing the bit 0 of the CONTROL\n * register.\n *\n * @note This is a privileged function and should only be called from the kenrel\n * code.\n *\n * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.\n *  Bit[0] = 0 --> The processor is running privileged\n *  Bit[0] = 1 --> The processor is running unprivileged.\n */\nvoid vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\n * register.\n *\n * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.\n *  Bit[0] = 0 --> The processor is running privileged\n *  Bit[0] = 1 --> The processor is running unprivileged.\n */\nvoid vResetPrivilege( void ) __attribute__( ( naked ) );\n\n/**\n * @brief Starts the first task.\n */\nvoid vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Disables interrupts.\n */\nuint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Enables interrupts.\n */\nvoid vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief PendSV Exception handler.\n */\nvoid PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief SVC Handler.\n */\nvoid SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Allocate a Secure context for the calling task.\n *\n * @param[in] ulSecureStackSize The size of the stack to be allocated on the\n * secure side for the calling task.\n */\nvoid vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) );\n\n/**\n * @brief Free the task's secure context.\n *\n * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.\n */\nvoid vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n#endif /* __PORT_ASM_H__ */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM23/non_secure/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef PORTMACRO_H\n#define PORTMACRO_H\n\n#ifdef __cplusplus\n    extern \"C\" {\n#endif\n\n#include \"portmacrocommon.h\"\n\n/*------------------------------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the given hardware\n * and compiler.\n *\n * These settings should not be altered.\n *------------------------------------------------------------------------------\n */\n\n/**\n * Architecture specifics.\n */\n#define portARCH_NAME                       \"Cortex-M23\"\n#define portDONT_DISCARD                    __attribute__( ( used ) )\n/*-----------------------------------------------------------*/\n\n#if( configTOTAL_MPU_REGIONS == 16 )\n    #error 16 MPU regions are not yet supported for this port.\n#endif\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Critical section management.\n */\n#define portDISABLE_INTERRUPTS()            __asm volatile ( \" cpsid i \" ::: \"memory\" )\n#define portENABLE_INTERRUPTS()             __asm volatile ( \" cpsie i \" ::: \"memory\" )\n/*-----------------------------------------------------------*/\n\n#ifdef __cplusplus\n    }\n#endif\n\n#endif /* PORTMACRO_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef PORTMACROCOMMON_H\n    #define PORTMACROCOMMON_H\n\n    #ifdef __cplusplus\n        extern \"C\" {\n    #endif\n\n/*------------------------------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the given hardware\n * and compiler.\n *\n * These settings should not be altered.\n *------------------------------------------------------------------------------\n */\n\n    #ifndef configENABLE_FPU\n        #error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.\n    #endif /* configENABLE_FPU */\n\n    #ifndef configENABLE_MPU\n        #error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.\n    #endif /* configENABLE_MPU */\n\n    #ifndef configENABLE_TRUSTZONE\n        #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.\n    #endif /* configENABLE_TRUSTZONE */\n\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Type definitions.\n */\n    #define portCHAR          char\n    #define portFLOAT         float\n    #define portDOUBLE        double\n    #define portLONG          long\n    #define portSHORT         short\n    #define portSTACK_TYPE    uint32_t\n    #define portBASE_TYPE     long\n\n    typedef portSTACK_TYPE   StackType_t;\n    typedef long             BaseType_t;\n    typedef unsigned long    UBaseType_t;\n\n    #if ( configUSE_16_BIT_TICKS == 1 )\n        typedef uint16_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffff\n    #else\n        typedef uint32_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL\n\n/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\n * not need to be guarded with a critical section. */\n        #define portTICK_TYPE_IS_ATOMIC    1\n    #endif\n/*-----------------------------------------------------------*/\n\n/**\n * Architecture specifics.\n */\n    #define portSTACK_GROWTH                   ( -1 )\n    #define portTICK_PERIOD_MS                 ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\n    #define portBYTE_ALIGNMENT                 8\n    #define portNOP()\n    #define portINLINE                         __inline\n    #ifndef portFORCE_INLINE\n        #define portFORCE_INLINE               inline __attribute__( ( always_inline ) )\n    #endif\n    #define portHAS_STACK_OVERFLOW_CHECKING    1\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Extern declarations.\n */\n    extern BaseType_t xPortIsInsideInterrupt( void );\n\n    extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;\n\n    extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;\n    extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;\n\n    extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\n    extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\n\n    #if ( configENABLE_TRUSTZONE == 1 )\n        extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */\n        extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;\n    #endif /* configENABLE_TRUSTZONE */\n\n    #if ( configENABLE_MPU == 1 )\n        extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;\n        extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;\n    #endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\n/**\n * @brief MPU specific constants.\n */\n    #if ( configENABLE_MPU == 1 )\n        #define portUSING_MPU_WRAPPERS    1\n        #define portPRIVILEGE_BIT         ( 0x80000000UL )\n    #else\n        #define portPRIVILEGE_BIT         ( 0x0UL )\n    #endif /* configENABLE_MPU */\n\n/* MPU settings that can be overriden in FreeRTOSConfig.h. */\n#ifndef configTOTAL_MPU_REGIONS\n    /* Define to 8 for backward compatibility. */\n    #define configTOTAL_MPU_REGIONS       ( 8UL )\n#endif\n\n/* MPU regions. */\n    #define portPRIVILEGED_FLASH_REGION                   ( 0UL )\n    #define portUNPRIVILEGED_FLASH_REGION                 ( 1UL )\n    #define portUNPRIVILEGED_SYSCALLS_REGION              ( 2UL )\n    #define portPRIVILEGED_RAM_REGION                     ( 3UL )\n    #define portSTACK_REGION                              ( 4UL )\n    #define portFIRST_CONFIGURABLE_REGION                 ( 5UL )\n    #define portLAST_CONFIGURABLE_REGION                  ( configTOTAL_MPU_REGIONS - 1UL )\n    #define portNUM_CONFIGURABLE_REGIONS                  ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )\n    #define portTOTAL_NUM_REGIONS                         ( portNUM_CONFIGURABLE_REGIONS + 1 )   /* Plus one to make space for the stack region. */\n\n/* Device memory attributes used in MPU_MAIR registers.\n *\n * 8-bit values encoded as follows:\n *  Bit[7:4] - 0000 - Device Memory\n *  Bit[3:2] - 00 --> Device-nGnRnE\n *\t\t\t\t01 --> Device-nGnRE\n *\t\t\t\t10 --> Device-nGRE\n *\t\t\t\t11 --> Device-GRE\n *  Bit[1:0] - 00, Reserved.\n */\n    #define portMPU_DEVICE_MEMORY_nGnRnE                  ( 0x00 )   /* 0000 0000 */\n    #define portMPU_DEVICE_MEMORY_nGnRE                   ( 0x04 )   /* 0000 0100 */\n    #define portMPU_DEVICE_MEMORY_nGRE                    ( 0x08 )   /* 0000 1000 */\n    #define portMPU_DEVICE_MEMORY_GRE                     ( 0x0C )   /* 0000 1100 */\n\n/* Normal memory attributes used in MPU_MAIR registers. */\n    #define portMPU_NORMAL_MEMORY_NON_CACHEABLE           ( 0x44 )   /* Non-cacheable. */\n    #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE    ( 0xFF )   /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */\n\n/* Attributes used in MPU_RBAR registers. */\n    #define portMPU_REGION_NON_SHAREABLE                  ( 0UL << 3UL )\n    #define portMPU_REGION_INNER_SHAREABLE                ( 1UL << 3UL )\n    #define portMPU_REGION_OUTER_SHAREABLE                ( 2UL << 3UL )\n\n    #define portMPU_REGION_PRIVILEGED_READ_WRITE          ( 0UL << 1UL )\n    #define portMPU_REGION_READ_WRITE                     ( 1UL << 1UL )\n    #define portMPU_REGION_PRIVILEGED_READ_ONLY           ( 2UL << 1UL )\n    #define portMPU_REGION_READ_ONLY                      ( 3UL << 1UL )\n\n    #define portMPU_REGION_EXECUTE_NEVER                  ( 1UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Settings to define an MPU region.\n */\n    typedef struct MPURegionSettings\n    {\n        uint32_t ulRBAR; /**< RBAR for the region. */\n        uint32_t ulRLAR; /**< RLAR for the region. */\n    } MPURegionSettings_t;\n\n/**\n * @brief MPU settings as stored in the TCB.\n */\n    typedef struct MPU_SETTINGS\n    {\n        uint32_t ulMAIR0;                                              /**< MAIR0 for the task containing attributes for all the 4 per task regions. */\n        MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */\n    } xMPU_SETTINGS;\n/*-----------------------------------------------------------*/\n\n/**\n * @brief SVC numbers.\n */\n    #define portSVC_ALLOCATE_SECURE_CONTEXT    0\n    #define portSVC_FREE_SECURE_CONTEXT        1\n    #define portSVC_START_SCHEDULER            2\n    #define portSVC_RAISE_PRIVILEGE            3\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Scheduler utilities.\n */\n    #define portYIELD()                                 vPortYield()\n    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )\n    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )\n    #define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )\n    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Critical section management.\n */\n    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulSetInterruptMask()\n    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vClearInterruptMask( x )\n    #define portENTER_CRITICAL()                      vPortEnterCritical()\n    #define portEXIT_CRITICAL()                       vPortExitCritical()\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Tickless idle/low power functionality.\n */\n    #ifndef portSUPPRESS_TICKS_AND_SLEEP\n        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );\n        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )\n    #endif\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Task function macros as described on the FreeRTOS.org WEB site.\n */\n    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )\n    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )\n/*-----------------------------------------------------------*/\n\n    #if ( configENABLE_TRUSTZONE == 1 )\n\n/**\n * @brief Allocate a secure context for the task.\n *\n * Tasks are not created with a secure context. Any task that is going to call\n * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a\n * secure context before it calls any secure function.\n *\n * @param[in] ulSecureStackSize The size of the secure stack to be allocated.\n */\n        #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )\n\n/**\n * @brief Called when a task is deleted to delete the task's secure context,\n * if it has one.\n *\n * @param[in] pxTCB The TCB of the task being deleted.\n */\n        #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )\n    #endif /* configENABLE_TRUSTZONE */\n/*-----------------------------------------------------------*/\n\n    #if ( configENABLE_MPU == 1 )\n\n/**\n * @brief Checks whether or not the processor is privileged.\n *\n * @return 1 if the processor is already privileged, 0 otherwise.\n */\n        #define portIS_PRIVILEGED()      xIsPrivileged()\n\n/**\n * @brief Raise an SVC request to raise privilege.\n *\n * The SVC handler checks that the SVC was raised from a system call and only\n * then it raises the privilege. If this is called from any other place,\n * the privilege is not raised.\n */\n        #define portRAISE_PRIVILEGE()    __asm volatile ( \"svc %0 \\n\" ::\"i\" ( portSVC_RAISE_PRIVILEGE ) : \"memory\" );\n\n/**\n * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\n * register.\n */\n        #define portRESET_PRIVILEGE()    vResetPrivilege()\n    #else\n        #define portIS_PRIVILEGED()\n        #define portRAISE_PRIVILEGE()\n        #define portRESET_PRIVILEGE()\n    #endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Barriers.\n */\n    #define portMEMORY_BARRIER()    __asm volatile ( \"\" ::: \"memory\" )\n/*-----------------------------------------------------------*/\n\n    #ifdef __cplusplus\n        }\n    #endif\n\n#endif /* PORTMACROCOMMON_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM23/secure/secure_context.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Secure context includes. */\n#include \"secure_context.h\"\n\n/* Secure heap includes. */\n#include \"secure_heap.h\"\n\n/* Secure port macros. */\n#include \"secure_port_macros.h\"\n\n/**\n * @brief CONTROL value for privileged tasks.\n *\n * Bit[0] - 0 --> Thread mode is privileged.\n * Bit[1] - 1 --> Thread mode uses PSP.\n */\n#define securecontextCONTROL_VALUE_PRIVILEGED      0x02\n\n/**\n * @brief CONTROL value for un-privileged tasks.\n *\n * Bit[0] - 1 --> Thread mode is un-privileged.\n * Bit[1] - 1 --> Thread mode uses PSP.\n */\n#define securecontextCONTROL_VALUE_UNPRIVILEGED    0x03\n\n/**\n * @brief Size of stack seal values in bytes.\n */\n#define securecontextSTACK_SEAL_SIZE               8\n\n/**\n * @brief Stack seal value as recommended by ARM.\n */\n#define securecontextSTACK_SEAL_VALUE              0xFEF5EDA5\n\n/**\n * @brief Maximum number of secure contexts.\n */\n#ifndef secureconfigMAX_SECURE_CONTEXTS\n    #define secureconfigMAX_SECURE_CONTEXTS        8UL\n#endif\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Pre-allocated array of secure contexts.\n */\nSecureContext_t xSecureContexts[ secureconfigMAX_SECURE_CONTEXTS ];\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Get a free secure context for a task from the secure context pool (xSecureContexts).\n *\n * This function ensures that only one secure context is allocated for a task.\n *\n * @param[in] pvTaskHandle The task handle for which the secure context is allocated.\n *\n * @return Index of a free secure context in the xSecureContexts array.\n */\nstatic uint32_t ulGetSecureContext( void * pvTaskHandle );\n\n/**\n * @brief Return the secure context to the secure context pool (xSecureContexts).\n *\n * @param[in] ulSecureContextIndex Index of the context in the xSecureContexts array.\n */\nstatic void vReturnSecureContext( uint32_t ulSecureContextIndex );\n\n/* These are implemented in assembly. */\nextern void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext );\nextern void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext );\n/*-----------------------------------------------------------*/\n\nstatic uint32_t ulGetSecureContext( void * pvTaskHandle )\n{\n    /* Start with invalid index. */\n    uint32_t i, ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS;\n\n    for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ )\n    {\n        if( ( xSecureContexts[ i ].pucCurrentStackPointer == NULL ) &&\n            ( xSecureContexts[ i ].pucStackLimit == NULL ) &&\n            ( xSecureContexts[ i ].pucStackStart == NULL ) &&\n            ( xSecureContexts[ i ].pvTaskHandle == NULL ) &&\n            ( ulSecureContextIndex == secureconfigMAX_SECURE_CONTEXTS ) )\n        {\n            ulSecureContextIndex = i;\n        }\n        else if( xSecureContexts[ i ].pvTaskHandle == pvTaskHandle )\n        {\n            /* A task can only have one secure context. Do not allocate a second\n             * context for the same task. */\n            ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS;\n            break;\n        }\n    }\n\n    return ulSecureContextIndex;\n}\n/*-----------------------------------------------------------*/\n\nstatic void vReturnSecureContext( uint32_t ulSecureContextIndex )\n{\n    xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = NULL;\n    xSecureContexts[ ulSecureContextIndex ].pucStackLimit = NULL;\n    xSecureContexts[ ulSecureContextIndex ].pucStackStart = NULL;\n    xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = NULL;\n}\n/*-----------------------------------------------------------*/\n\nsecureportNON_SECURE_CALLABLE void SecureContext_Init( void )\n{\n    uint32_t ulIPSR, i;\n    static uint32_t ulSecureContextsInitialized = 0;\n\n    /* Read the Interrupt Program Status Register (IPSR) value. */\n    secureportREAD_IPSR( ulIPSR );\n\n    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\n     * when the processor is running in the Thread Mode. */\n    if( ( ulIPSR != 0 ) && ( ulSecureContextsInitialized == 0 ) )\n    {\n        /* Ensure to initialize secure contexts only once. */\n        ulSecureContextsInitialized = 1;\n\n        /* No stack for thread mode until a task's context is loaded. */\n        secureportSET_PSPLIM( securecontextNO_STACK );\n        secureportSET_PSP( securecontextNO_STACK );\n\n        /* Initialize all secure contexts. */\n        for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ )\n        {\n            xSecureContexts[ i ].pucCurrentStackPointer = NULL;\n            xSecureContexts[ i ].pucStackLimit = NULL;\n            xSecureContexts[ i ].pucStackStart = NULL;\n            xSecureContexts[ i ].pvTaskHandle = NULL;\n        }\n\n        #if ( configENABLE_MPU == 1 )\n            {\n                /* Configure thread mode to use PSP and to be unprivileged. */\n                secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );\n            }\n        #else /* configENABLE_MPU */\n            {\n                /* Configure thread mode to use PSP and to be privileged. */\n                secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );\n            }\n        #endif /* configENABLE_MPU */\n    }\n}\n/*-----------------------------------------------------------*/\n\n#if ( configENABLE_MPU == 1 )\n    secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,\n                                                                                       uint32_t ulIsTaskPrivileged,\n                                                                                       void * pvTaskHandle )\n#else /* configENABLE_MPU */\n    secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,\n                                                                                       void * pvTaskHandle )\n#endif /* configENABLE_MPU */\n{\n    uint8_t * pucStackMemory = NULL;\n    uint8_t * pucStackLimit;\n    uint32_t ulIPSR, ulSecureContextIndex;\n    SecureContextHandle_t xSecureContextHandle = securecontextINVALID_CONTEXT_ID;\n\n    #if ( configENABLE_MPU == 1 )\n        uint32_t * pulCurrentStackPointer = NULL;\n    #endif /* configENABLE_MPU */\n\n    /* Read the Interrupt Program Status Register (IPSR) and Process Stack Limit\n     * Register (PSPLIM) value. */\n    secureportREAD_IPSR( ulIPSR );\n    secureportREAD_PSPLIM( pucStackLimit );\n\n    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\n     * when the processor is running in the Thread Mode.\n     * Also do nothing, if a secure context us already loaded. PSPLIM is set to\n     * securecontextNO_STACK when no secure context is loaded. */\n    if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) )\n    {\n        /* Ontain a free secure context. */\n        ulSecureContextIndex = ulGetSecureContext( pvTaskHandle );\n\n        /* Were we able to get a free context? */\n        if( ulSecureContextIndex < secureconfigMAX_SECURE_CONTEXTS )\n        {\n            /* Allocate the stack space. */\n            pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE );\n\n            if( pucStackMemory != NULL )\n            {\n                /* Since stack grows down, the starting point will be the last\n                 * location. Note that this location is next to the last\n                 * allocated byte for stack (excluding the space for seal values)\n                 * because the hardware decrements the stack pointer before\n                 * writing i.e. if stack pointer is 0x2, a push operation will\n                 * decrement the stack pointer to 0x1 and then write at 0x1. */\n                xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize;\n\n                /* Seal the created secure process stack. */\n                *( uint32_t * )( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE;\n                *( uint32_t * )( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE;\n\n                /* The stack cannot go beyond this location. This value is\n                 * programmed in the PSPLIM register on context switch.*/\n                xSecureContexts[ ulSecureContextIndex ].pucStackLimit = pucStackMemory;\n\n                xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle;\n\n                #if ( configENABLE_MPU == 1 )\n                    {\n                        /* Store the correct CONTROL value for the task on the stack.\n                         * This value is programmed in the CONTROL register on\n                         * context switch. */\n                        pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart;\n                        pulCurrentStackPointer--;\n\n                        if( ulIsTaskPrivileged )\n                        {\n                            *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;\n                        }\n                        else\n                        {\n                            *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;\n                        }\n\n                        /* Store the current stack pointer. This value is programmed in\n                         * the PSP register on context switch. */\n                        xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;\n                    }\n                #else /* configENABLE_MPU */\n                    {\n                        /* Current SP is set to the starting of the stack. This\n                         * value programmed in the PSP register on context switch. */\n                        xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart;\n                    }\n                #endif /* configENABLE_MPU */\n\n                /* Ensure to never return 0 as a valid context handle. */\n                xSecureContextHandle = ulSecureContextIndex + 1UL;\n            }\n        }\n    }\n\n    return xSecureContextHandle;\n}\n/*-----------------------------------------------------------*/\n\nsecureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )\n{\n    uint32_t ulIPSR, ulSecureContextIndex;\n\n    /* Read the Interrupt Program Status Register (IPSR) value. */\n    secureportREAD_IPSR( ulIPSR );\n\n    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\n     * when the processor is running in the Thread Mode. */\n    if( ulIPSR != 0 )\n    {\n        /* Only free if a valid context handle is passed. */\n        if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) )\n        {\n            ulSecureContextIndex = xSecureContextHandle - 1UL;\n\n            /* Ensure that the secure context being deleted is associated with\n             * the task. */\n            if( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle )\n            {\n                /* Free the stack space. */\n                vPortFree( xSecureContexts[ ulSecureContextIndex ].pucStackLimit );\n\n                /* Return the secure context back to the free secure contexts pool. */\n                vReturnSecureContext( ulSecureContextIndex );\n            }\n        }\n    }\n}\n/*-----------------------------------------------------------*/\n\nsecureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )\n{\n    uint8_t * pucStackLimit;\n    uint32_t ulSecureContextIndex;\n\n    if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) )\n    {\n        ulSecureContextIndex = xSecureContextHandle - 1UL;\n\n        secureportREAD_PSPLIM( pucStackLimit );\n\n        /* Ensure that no secure context is loaded and the task is loading it's\n         * own context. */\n        if( ( pucStackLimit == securecontextNO_STACK ) &&\n            ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) )\n        {\n            SecureContext_LoadContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) );\n        }\n    }\n}\n/*-----------------------------------------------------------*/\n\nsecureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )\n{\n    uint8_t * pucStackLimit;\n    uint32_t ulSecureContextIndex;\n\n    if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) )\n    {\n        ulSecureContextIndex = xSecureContextHandle - 1UL;\n\n        secureportREAD_PSPLIM( pucStackLimit );\n\n        /* Ensure that task's context is loaded and the task is saving it's own\n         * context. */\n        if( ( xSecureContexts[ ulSecureContextIndex ].pucStackLimit == pucStackLimit ) &&\n            ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) )\n        {\n            SecureContext_SaveContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) );\n        }\n    }\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM23/secure/secure_context.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef __SECURE_CONTEXT_H__\n#define __SECURE_CONTEXT_H__\n\n/* Standard includes. */\n#include <stdint.h>\n\n/* FreeRTOS includes. */\n#include \"FreeRTOSConfig.h\"\n\n/**\n * @brief PSP value when no secure context is loaded.\n */\n#define securecontextNO_STACK               0x0\n\n/**\n * @brief Invalid context ID.\n */\n#define securecontextINVALID_CONTEXT_ID     0UL\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Structure to represent a secure context.\n *\n * @note Since stack grows down, pucStackStart is the highest address while\n * pucStackLimit is the first address of the allocated memory.\n */\ntypedef struct SecureContext\n{\n    uint8_t * pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */\n    uint8_t * pucStackLimit;          /**< Last location of the stack memory (PSPLIM). */\n    uint8_t * pucStackStart;          /**< First location of the stack memory. */\n    void * pvTaskHandle;              /**< Task handle of the task this context is associated with. */\n} SecureContext_t;\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Opaque handle for a secure context.\n */\ntypedef uint32_t SecureContextHandle_t;\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Initializes the secure context management system.\n *\n * PSP is set to NULL and therefore a task must allocate and load a context\n * before calling any secure side function in the thread mode.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n */\nvoid SecureContext_Init( void );\n\n/**\n * @brief Allocates a context on the secure side.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n *\n * @param[in] ulSecureStackSize Size of the stack to allocate on secure side.\n * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise.\n *\n * @return Opaque context handle if context is successfully allocated, NULL\n * otherwise.\n */\n#if ( configENABLE_MPU == 1 )\n    SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,\n                                                         uint32_t ulIsTaskPrivileged,\n                                                         void * pvTaskHandle );\n#else /* configENABLE_MPU */\n    SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,\n                                                         void * pvTaskHandle );\n#endif /* configENABLE_MPU */\n\n/**\n * @brief Frees the given context.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n *\n * @param[in] xSecureContextHandle Context handle corresponding to the\n * context to be freed.\n */\nvoid SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );\n\n/**\n * @brief Loads the given context.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n *\n * @param[in] xSecureContextHandle Context handle corresponding to the context\n * to be loaded.\n */\nvoid SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );\n\n/**\n * @brief Saves the given context.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n *\n * @param[in] xSecureContextHandle Context handle corresponding to the context\n * to be saved.\n */\nvoid SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );\n\n#endif /* __SECURE_CONTEXT_H__ */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM23/secure/secure_context_port.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Secure context includes. */\n#include \"secure_context.h\"\n\n/* Secure port macros. */\n#include \"secure_port_macros.h\"\n\n#if ( configENABLE_FPU == 1 )\n    #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.\n#endif\n\nvoid SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) );\nvoid SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) );\n\nvoid SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext )\n{\n    /* pxSecureContext value is in r0. */\n    __asm volatile\n    (\n        \" .syntax unified                   \\n\"\n        \"                                   \\n\"\n        \" mrs r1, ipsr                      \\n\" /* r1 = IPSR. */\n        \" cbz r1, load_ctx_therad_mode      \\n\" /* Do nothing if the processor is running in the Thread Mode. */\n        \" ldmia r0!, {r1, r2}               \\n\" /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */\n        \"                                   \\n\"\n        #if ( configENABLE_MPU == 1 )\n            \" ldmia r1!, {r3}               \\n\" /* Read CONTROL register value from task's stack. r3 = CONTROL. */\n            \" msr control, r3               \\n\" /* CONTROL = r3. */\n        #endif /* configENABLE_MPU */\n        \"                                   \\n\"\n        \" msr psplim, r2                    \\n\" /* PSPLIM = r2. */\n        \" msr psp, r1                       \\n\" /* PSP = r1. */\n        \"                                   \\n\"\n        \" load_ctx_therad_mode:             \\n\"\n        \"    bx lr                          \\n\"\n        \"                                   \\n\"\n        ::: \"r0\", \"r1\", \"r2\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext )\n{\n    /* pxSecureContext value is in r0. */\n    __asm volatile\n    (\n        \" .syntax unified                   \\n\"\n        \"                                   \\n\"\n        \" mrs r1, ipsr                      \\n\" /* r1 = IPSR. */\n        \" cbz r1, save_ctx_therad_mode      \\n\" /* Do nothing if the processor is running in the Thread Mode. */\n        \" mrs r1, psp                       \\n\" /* r1 = PSP. */\n        \"                                   \\n\"\n        #if ( configENABLE_MPU == 1 )\n            \" mrs r2, control               \\n\" /* r2 = CONTROL. */\n            \" subs r1, r1, #4               \\n\" /* Make space for the CONTROL value on the stack. */\n            \" str r1, [r0]                  \\n\" /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */\n            \" stmia r1!, {r2}               \\n\" /* Store CONTROL value on the stack. */\n        #else /* configENABLE_MPU */\n            \" str r1, [r0]                  \\n\" /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */\n        #endif /* configENABLE_MPU */\n        \"                                   \\n\"\n        \" movs r1, %0                       \\n\" /* r1 = securecontextNO_STACK. */\n        \" msr psplim, r1                    \\n\" /* PSPLIM = securecontextNO_STACK. */\n        \" msr psp, r1                       \\n\" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */\n        \"                                   \\n\"\n        \" save_ctx_therad_mode:             \\n\"\n        \"   bx lr                           \\n\"\n        \"                                   \\n\"\n        ::\"i\" ( securecontextNO_STACK ) : \"r1\", \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM23/secure/secure_heap.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Standard includes. */\n#include <stdint.h>\n\n/* Secure context heap includes. */\n#include \"secure_heap.h\"\n\n/* Secure port macros. */\n#include \"secure_port_macros.h\"\n\n/**\n * @brief Total heap size.\n */\n#ifndef secureconfigTOTAL_HEAP_SIZE\n    #define secureconfigTOTAL_HEAP_SIZE    ( ( ( size_t ) ( 10 * 1024 ) ) )\n#endif\n\n/* No test marker by default. */\n#ifndef mtCOVERAGE_TEST_MARKER\n    #define mtCOVERAGE_TEST_MARKER()\n#endif\n\n/* No tracing by default. */\n#ifndef traceMALLOC\n    #define traceMALLOC( pvReturn, xWantedSize )\n#endif\n\n/* No tracing by default. */\n#ifndef traceFREE\n    #define traceFREE( pv, xBlockSize )\n#endif\n\n/* Block sizes must not get too small. */\n#define secureheapMINIMUM_BLOCK_SIZE    ( ( size_t ) ( xHeapStructSize << 1 ) )\n\n/* Assumes 8bit bytes! */\n#define secureheapBITS_PER_BYTE         ( ( size_t ) 8 )\n/*-----------------------------------------------------------*/\n\n/* Allocate the memory for the heap. */\n#if ( configAPPLICATION_ALLOCATED_HEAP == 1 )\n\n/* The application writer has already defined the array used for the RTOS\n* heap - probably so it can be placed in a special segment or address. */\n    extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];\n#else /* configAPPLICATION_ALLOCATED_HEAP */\n    static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];\n#endif /* configAPPLICATION_ALLOCATED_HEAP */\n\n/**\n * @brief The linked list structure.\n *\n * This is used to link free blocks in order of their memory address.\n */\ntypedef struct A_BLOCK_LINK\n{\n    struct A_BLOCK_LINK * pxNextFreeBlock; /**< The next free block in the list. */\n    size_t xBlockSize;                     /**< The size of the free block. */\n} BlockLink_t;\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Called automatically to setup the required heap structures the first\n * time pvPortMalloc() is called.\n */\nstatic void prvHeapInit( void );\n\n/**\n * @brief Inserts a block of memory that is being freed into the correct\n * position in the list of free memory blocks.\n *\n * The block being freed will be merged with the block in front it and/or the\n * block behind it if the memory blocks are adjacent to each other.\n *\n * @param[in] pxBlockToInsert The block being freed.\n */\nstatic void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert );\n/*-----------------------------------------------------------*/\n\n/**\n * @brief The size of the structure placed at the beginning of each allocated\n * memory block must by correctly byte aligned.\n */\nstatic const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );\n\n/**\n * @brief Create a couple of list links to mark the start and end of the list.\n */\nstatic BlockLink_t xStart;\nstatic BlockLink_t * pxEnd = NULL;\n\n/**\n * @brief Keeps track of the number of free bytes remaining, but says nothing\n * about fragmentation.\n */\nstatic size_t xFreeBytesRemaining = 0U;\nstatic size_t xMinimumEverFreeBytesRemaining = 0U;\n\n/**\n * @brief Gets set to the top bit of an size_t type.\n *\n * When this bit in the xBlockSize member of an BlockLink_t structure is set\n * then the block belongs to the application. When the bit is free the block is\n * still part of the free heap space.\n */\nstatic size_t xBlockAllocatedBit = 0;\n/*-----------------------------------------------------------*/\n\nstatic void prvHeapInit( void )\n{\n    BlockLink_t * pxFirstFreeBlock;\n    uint8_t * pucAlignedHeap;\n    size_t uxAddress;\n    size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE;\n\n    /* Ensure the heap starts on a correctly aligned boundary. */\n    uxAddress = ( size_t ) ucHeap;\n\n    if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 )\n    {\n        uxAddress += ( secureportBYTE_ALIGNMENT - 1 );\n        uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );\n        xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;\n    }\n\n    pucAlignedHeap = ( uint8_t * ) uxAddress;\n\n    /* xStart is used to hold a pointer to the first item in the list of free\n     * blocks.  The void cast is used to prevent compiler warnings. */\n    xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;\n    xStart.xBlockSize = ( size_t ) 0;\n\n    /* pxEnd is used to mark the end of the list of free blocks and is inserted\n     * at the end of the heap space. */\n    uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;\n    uxAddress -= xHeapStructSize;\n    uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );\n    pxEnd = ( void * ) uxAddress;\n    pxEnd->xBlockSize = 0;\n    pxEnd->pxNextFreeBlock = NULL;\n\n    /* To start with there is a single free block that is sized to take up the\n     * entire heap space, minus the space taken by pxEnd. */\n    pxFirstFreeBlock = ( void * ) pucAlignedHeap;\n    pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;\n    pxFirstFreeBlock->pxNextFreeBlock = pxEnd;\n\n    /* Only one block exists - and it covers the entire usable heap space. */\n    xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;\n    xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;\n\n    /* Work out the position of the top bit in a size_t variable. */\n    xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert )\n{\n    BlockLink_t * pxIterator;\n    uint8_t * puc;\n\n    /* Iterate through the list until a block is found that has a higher address\n     * than the block being inserted. */\n    for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )\n    {\n        /* Nothing to do here, just iterate to the right position. */\n    }\n\n    /* Do the block being inserted, and the block it is being inserted after\n     * make a contiguous block of memory? */\n    puc = ( uint8_t * ) pxIterator;\n\n    if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )\n    {\n        pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;\n        pxBlockToInsert = pxIterator;\n    }\n    else\n    {\n        mtCOVERAGE_TEST_MARKER();\n    }\n\n    /* Do the block being inserted, and the block it is being inserted before\n     * make a contiguous block of memory? */\n    puc = ( uint8_t * ) pxBlockToInsert;\n\n    if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )\n    {\n        if( pxIterator->pxNextFreeBlock != pxEnd )\n        {\n            /* Form one big block from the two blocks. */\n            pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;\n            pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;\n        }\n        else\n        {\n            pxBlockToInsert->pxNextFreeBlock = pxEnd;\n        }\n    }\n    else\n    {\n        pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;\n    }\n\n    /* If the block being inserted plugged a gab, so was merged with the block\n     * before and the block after, then it's pxNextFreeBlock pointer will have\n     * already been set, and should not be set here as that would make it point\n     * to itself. */\n    if( pxIterator != pxBlockToInsert )\n    {\n        pxIterator->pxNextFreeBlock = pxBlockToInsert;\n    }\n    else\n    {\n        mtCOVERAGE_TEST_MARKER();\n    }\n}\n/*-----------------------------------------------------------*/\n\nvoid * pvPortMalloc( size_t xWantedSize )\n{\n    BlockLink_t * pxBlock;\n    BlockLink_t * pxPreviousBlock;\n    BlockLink_t * pxNewBlockLink;\n    void * pvReturn = NULL;\n\n    /* If this is the first call to malloc then the heap will require\n     * initialisation to setup the list of free blocks. */\n    if( pxEnd == NULL )\n    {\n        prvHeapInit();\n    }\n    else\n    {\n        mtCOVERAGE_TEST_MARKER();\n    }\n\n    /* Check the requested block size is not so large that the top bit is set.\n     * The top bit of the block size member of the BlockLink_t structure is used\n     * to determine who owns the block - the application or the kernel, so it\n     * must be free. */\n    if( ( xWantedSize & xBlockAllocatedBit ) == 0 )\n    {\n        /* The wanted size is increased so it can contain a BlockLink_t\n         * structure in addition to the requested amount of bytes. */\n        if( xWantedSize > 0 )\n        {\n            xWantedSize += xHeapStructSize;\n\n            /* Ensure that blocks are always aligned to the required number of\n             * bytes. */\n            if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )\n            {\n                /* Byte alignment required. */\n                xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );\n                secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n\n        if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )\n        {\n            /* Traverse the list from the start (lowest address) block until\n             * one of adequate size is found. */\n            pxPreviousBlock = &xStart;\n            pxBlock = xStart.pxNextFreeBlock;\n\n            while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )\n            {\n                pxPreviousBlock = pxBlock;\n                pxBlock = pxBlock->pxNextFreeBlock;\n            }\n\n            /* If the end marker was reached then a block of adequate size was\n             * not found. */\n            if( pxBlock != pxEnd )\n            {\n                /* Return the memory space pointed to - jumping over the\n                 * BlockLink_t structure at its start. */\n                pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );\n\n                /* This block is being returned for use so must be taken out\n                 * of the list of free blocks. */\n                pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;\n\n                /* If the block is larger than required it can be split into\n                 * two. */\n                if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE )\n                {\n                    /* This block is to be split into two.  Create a new\n                     * block following the number of bytes requested. The void\n                     * cast is used to prevent byte alignment warnings from the\n                     * compiler. */\n                    pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );\n                    secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 );\n\n                    /* Calculate the sizes of two blocks split from the single\n                     * block. */\n                    pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;\n                    pxBlock->xBlockSize = xWantedSize;\n\n                    /* Insert the new block into the list of free blocks. */\n                    prvInsertBlockIntoFreeList( pxNewBlockLink );\n                }\n                else\n                {\n                    mtCOVERAGE_TEST_MARKER();\n                }\n\n                xFreeBytesRemaining -= pxBlock->xBlockSize;\n\n                if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )\n                {\n                    xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;\n                }\n                else\n                {\n                    mtCOVERAGE_TEST_MARKER();\n                }\n\n                /* The block is being returned - it is allocated and owned by\n                 * the application and has no \"next\" block. */\n                pxBlock->xBlockSize |= xBlockAllocatedBit;\n                pxBlock->pxNextFreeBlock = NULL;\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n    }\n    else\n    {\n        mtCOVERAGE_TEST_MARKER();\n    }\n\n    traceMALLOC( pvReturn, xWantedSize );\n\n    #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )\n        {\n            if( pvReturn == NULL )\n            {\n                extern void vApplicationMallocFailedHook( void );\n                vApplicationMallocFailedHook();\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n    #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */\n\n    secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );\n    return pvReturn;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortFree( void * pv )\n{\n    uint8_t * puc = ( uint8_t * ) pv;\n    BlockLink_t * pxLink;\n\n    if( pv != NULL )\n    {\n        /* The memory being freed will have an BlockLink_t structure immediately\n         * before it. */\n        puc -= xHeapStructSize;\n\n        /* This casting is to keep the compiler from issuing warnings. */\n        pxLink = ( void * ) puc;\n\n        /* Check the block is actually allocated. */\n        secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );\n        secureportASSERT( pxLink->pxNextFreeBlock == NULL );\n\n        if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )\n        {\n            if( pxLink->pxNextFreeBlock == NULL )\n            {\n                /* The block is being returned to the heap - it is no longer\n                 * allocated. */\n                pxLink->xBlockSize &= ~xBlockAllocatedBit;\n\n                secureportDISABLE_NON_SECURE_INTERRUPTS();\n                {\n                    /* Add this block to the list of free blocks. */\n                    xFreeBytesRemaining += pxLink->xBlockSize;\n                    traceFREE( pv, pxLink->xBlockSize );\n                    prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );\n                }\n                secureportENABLE_NON_SECURE_INTERRUPTS();\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n    }\n}\n/*-----------------------------------------------------------*/\n\nsize_t xPortGetFreeHeapSize( void )\n{\n    return xFreeBytesRemaining;\n}\n/*-----------------------------------------------------------*/\n\nsize_t xPortGetMinimumEverFreeHeapSize( void )\n{\n    return xMinimumEverFreeBytesRemaining;\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM23/secure/secure_heap.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef __SECURE_HEAP_H__\n#define __SECURE_HEAP_H__\n\n/* Standard includes. */\n#include <stdlib.h>\n\n/**\n * @brief Allocates memory from heap.\n *\n * @param[in] xWantedSize The size of the memory to be allocated.\n *\n * @return Pointer to the memory region if the allocation is successful, NULL\n * otherwise.\n */\nvoid * pvPortMalloc( size_t xWantedSize );\n\n/**\n * @brief Frees the previously allocated memory.\n *\n * @param[in] pv Pointer to the memory to be freed.\n */\nvoid vPortFree( void * pv );\n\n/**\n * @brief Get the free heap size.\n *\n * @return Free heap size.\n */\nsize_t xPortGetFreeHeapSize( void );\n\n/**\n * @brief Get the minimum ever free heap size.\n *\n * @return Minimum ever free heap size.\n */\nsize_t xPortGetMinimumEverFreeHeapSize( void );\n\n#endif /* __SECURE_HEAP_H__ */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM23/secure/secure_init.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Standard includes. */\n#include <stdint.h>\n\n/* Secure init includes. */\n#include \"secure_init.h\"\n\n/* Secure port macros. */\n#include \"secure_port_macros.h\"\n\n/**\n * @brief Constants required to manipulate the SCB.\n */\n#define secureinitSCB_AIRCR                 ( ( volatile uint32_t * ) 0xe000ed0c )  /* Application Interrupt and Reset Control Register. */\n#define secureinitSCB_AIRCR_VECTKEY_POS     ( 16UL )\n#define secureinitSCB_AIRCR_VECTKEY_MASK    ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )\n#define secureinitSCB_AIRCR_PRIS_POS        ( 14UL )\n#define secureinitSCB_AIRCR_PRIS_MASK       ( 1UL << secureinitSCB_AIRCR_PRIS_POS )\n\n/**\n * @brief Constants required to manipulate the FPU.\n */\n#define secureinitFPCCR                     ( ( volatile uint32_t * ) 0xe000ef34 )  /* Floating Point Context Control Register. */\n#define secureinitFPCCR_LSPENS_POS          ( 29UL )\n#define secureinitFPCCR_LSPENS_MASK         ( 1UL << secureinitFPCCR_LSPENS_POS )\n#define secureinitFPCCR_TS_POS              ( 26UL )\n#define secureinitFPCCR_TS_MASK             ( 1UL << secureinitFPCCR_TS_POS )\n\n#define secureinitNSACR                     ( ( volatile uint32_t * ) 0xe000ed8c )  /* Non-secure Access Control Register. */\n#define secureinitNSACR_CP10_POS            ( 10UL )\n#define secureinitNSACR_CP10_MASK           ( 1UL << secureinitNSACR_CP10_POS )\n#define secureinitNSACR_CP11_POS            ( 11UL )\n#define secureinitNSACR_CP11_MASK           ( 1UL << secureinitNSACR_CP11_POS )\n/*-----------------------------------------------------------*/\n\nsecureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void )\n{\n    uint32_t ulIPSR;\n\n    /* Read the Interrupt Program Status Register (IPSR) value. */\n    secureportREAD_IPSR( ulIPSR );\n\n    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\n     * when the processor is running in the Thread Mode. */\n    if( ulIPSR != 0 )\n    {\n        *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |\n                                   ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |\n                                   ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK );\n    }\n}\n/*-----------------------------------------------------------*/\n\nsecureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )\n{\n    uint32_t ulIPSR;\n\n    /* Read the Interrupt Program Status Register (IPSR) value. */\n    secureportREAD_IPSR( ulIPSR );\n\n    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\n     * when the processor is running in the Thread Mode. */\n    if( ulIPSR != 0 )\n    {\n        /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is\n         * permitted. CP11 should be programmed to the same value as CP10. */\n        *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );\n\n        /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures\n         * that we can enable/disable lazy stacking in port.c file. */\n        *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK );\n\n        /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP\n         * registers (S16-S31) are also pushed to stack on exception entry and\n         * restored on exception return. */\n        *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );\n    }\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM23/secure/secure_init.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef __SECURE_INIT_H__\n#define __SECURE_INIT_H__\n\n/**\n * @brief De-prioritizes the non-secure exceptions.\n *\n * This is needed to ensure that the non-secure PendSV runs at the lowest\n * priority. Context switch is done in the non-secure PendSV handler.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n */\nvoid SecureInit_DePrioritizeNSExceptions( void );\n\n/**\n * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access.\n *\n * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point\n * Registers are not leaked to the non-secure side.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n */\nvoid SecureInit_EnableNSFPUAccess( void );\n\n#endif /* __SECURE_INIT_H__ */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM23/secure/secure_port_macros.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef __SECURE_PORT_MACROS_H__\n#define __SECURE_PORT_MACROS_H__\n\n/**\n * @brief Byte alignment requirements.\n */\n#define secureportBYTE_ALIGNMENT         8\n#define secureportBYTE_ALIGNMENT_MASK    ( 0x0007 )\n\n/**\n * @brief Macro to declare a function as non-secure callable.\n */\n#if defined( __IAR_SYSTEMS_ICC__ )\n    #define secureportNON_SECURE_CALLABLE    __cmse_nonsecure_entry __root\n#else\n    #define secureportNON_SECURE_CALLABLE    __attribute__( ( cmse_nonsecure_entry ) ) __attribute__( ( used ) )\n#endif\n\n/**\n * @brief Set the secure PRIMASK value.\n */\n#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \\\n    __asm volatile ( \"msr primask, %0\" : : \"r\" ( ulPrimaskValue ) : \"memory\" )\n\n/**\n * @brief Set the non-secure PRIMASK value.\n */\n#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \\\n    __asm volatile ( \"msr primask_ns, %0\" : : \"r\" ( ulPrimaskValue ) : \"memory\" )\n\n/**\n * @brief Read the PSP value in the given variable.\n */\n#define secureportREAD_PSP( pucOutCurrentStackPointer ) \\\n    __asm volatile ( \"mrs %0, psp\"  : \"=r\" ( pucOutCurrentStackPointer ) )\n\n/**\n * @brief Set the PSP to the given value.\n */\n#define secureportSET_PSP( pucCurrentStackPointer ) \\\n    __asm volatile ( \"msr psp, %0\" : : \"r\" ( pucCurrentStackPointer ) )\n\n/**\n * @brief Read the PSPLIM value in the given variable.\n */\n#define secureportREAD_PSPLIM( pucOutStackLimit ) \\\n    __asm volatile ( \"mrs %0, psplim\"  : \"=r\" ( pucOutStackLimit ) )\n\n/**\n * @brief Set the PSPLIM to the given value.\n */\n#define secureportSET_PSPLIM( pucStackLimit ) \\\n    __asm volatile ( \"msr psplim, %0\" : : \"r\" ( pucStackLimit ) )\n\n/**\n * @brief Set the NonSecure MSP to the given value.\n */\n#define secureportSET_MSP_NS( pucMainStackPointer ) \\\n    __asm volatile ( \"msr msp_ns, %0\" : : \"r\" ( pucMainStackPointer ) )\n\n/**\n * @brief Set the CONTROL register to the given value.\n */\n#define secureportSET_CONTROL( ulControl ) \\\n    __asm volatile ( \"msr control, %0\" : : \"r\" ( ulControl ) : \"memory\" )\n\n/**\n * @brief Read the Interrupt Program Status Register (IPSR) value in the given\n * variable.\n */\n#define secureportREAD_IPSR( ulIPSR ) \\\n    __asm volatile ( \"mrs %0, ipsr\"  : \"=r\" ( ulIPSR ) )\n\n/**\n * @brief PRIMASK value to enable interrupts.\n */\n#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL     0\n\n/**\n * @brief PRIMASK value to disable interrupts.\n */\n#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL    1\n\n/**\n * @brief Disable secure interrupts.\n */\n#define secureportDISABLE_SECURE_INTERRUPTS()        secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )\n\n/**\n * @brief Disable non-secure interrupts.\n *\n * This effectively disables context switches.\n */\n#define secureportDISABLE_NON_SECURE_INTERRUPTS()    secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )\n\n/**\n * @brief Enable non-secure interrupts.\n */\n#define secureportENABLE_NON_SECURE_INTERRUPTS()     secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL )\n\n/**\n * @brief Assert definition.\n */\n#define secureportASSERT( x )                      \\\n    if( ( x ) == 0 )                               \\\n    {                                              \\\n        secureportDISABLE_SECURE_INTERRUPTS();     \\\n        secureportDISABLE_NON_SECURE_INTERRUPTS(); \\\n        for( ; ; ) {; }                            \\\n    }\n\n#endif /* __SECURE_PORT_MACROS_H__ */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM23_NTZ/non_secure/port.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\n * all the API functions to use the MPU wrappers. That should only be done when\n * task.h is included from an application file. */\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n/* MPU wrappers includes. */\n#include \"mpu_wrappers.h\"\n\n/* Portasm includes. */\n#include \"portasm.h\"\n\n#if ( configENABLE_TRUSTZONE == 1 )\n    /* Secure components includes. */\n    #include \"secure_context.h\"\n    #include \"secure_init.h\"\n#endif /* configENABLE_TRUSTZONE */\n\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/**\n * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only\n * i.e. the processor boots as secure and never jumps to the non-secure side.\n * The Trust Zone support in the port must be disabled in order to run FreeRTOS\n * on the secure side. The following are the valid configuration seetings:\n *\n * 1. Run FreeRTOS on the Secure Side:\n *    configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0\n *\n * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:\n *    configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1\n *\n * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:\n *    configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0\n */\n#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )\n    #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.\n#endif\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the NVIC.\n */\n#define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )\n#define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )\n#define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )\n#define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )\n#define portNVIC_SYSTICK_ENABLE_BIT           ( 1UL << 0UL )\n#define portNVIC_SYSTICK_INT_BIT              ( 1UL << 1UL )\n#define portNVIC_SYSTICK_CLK_BIT              ( 1UL << 2UL )\n#define portNVIC_SYSTICK_COUNT_FLAG_BIT       ( 1UL << 16UL )\n#define portNVIC_PEND_SYSTICK_CLEAR_BIT       ( 1UL << 25UL )\n#define portNVIC_PEND_SYSTICK_SET_BIT         ( 1UL << 26UL )\n#define portMIN_INTERRUPT_PRIORITY            ( 255UL )\n#define portNVIC_PENDSV_PRI                   ( portMIN_INTERRUPT_PRIORITY << 16UL )\n#define portNVIC_SYSTICK_PRI                  ( portMIN_INTERRUPT_PRIORITY << 24UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the SCB.\n */\n#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( volatile uint32_t * ) 0xe000ed24 )\n#define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the FPU.\n */\n#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 )              /* Coprocessor Access Control Register. */\n#define portCPACR_CP10_VALUE    ( 3UL )\n#define portCPACR_CP11_VALUE    portCPACR_CP10_VALUE\n#define portCPACR_CP10_POS      ( 20UL )\n#define portCPACR_CP11_POS      ( 22UL )\n\n#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 )              /* Floating Point Context Control Register. */\n#define portFPCCR_ASPEN_POS     ( 31UL )\n#define portFPCCR_ASPEN_MASK    ( 1UL << portFPCCR_ASPEN_POS )\n#define portFPCCR_LSPEN_POS     ( 30UL )\n#define portFPCCR_LSPEN_MASK    ( 1UL << portFPCCR_LSPEN_POS )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the MPU.\n */\n#define portMPU_TYPE_REG                      ( *( ( volatile uint32_t * ) 0xe000ed90 ) )\n#define portMPU_CTRL_REG                      ( *( ( volatile uint32_t * ) 0xe000ed94 ) )\n#define portMPU_RNR_REG                       ( *( ( volatile uint32_t * ) 0xe000ed98 ) )\n\n#define portMPU_RBAR_REG                      ( *( ( volatile uint32_t * ) 0xe000ed9c ) )\n#define portMPU_RLAR_REG                      ( *( ( volatile uint32_t * ) 0xe000eda0 ) )\n\n#define portMPU_RBAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda4 ) )\n#define portMPU_RLAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda8 ) )\n\n#define portMPU_RBAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edac ) )\n#define portMPU_RLAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edb0 ) )\n\n#define portMPU_RBAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb4 ) )\n#define portMPU_RLAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb8 ) )\n\n#define portMPU_MAIR0_REG                     ( *( ( volatile uint32_t * ) 0xe000edc0 ) )\n#define portMPU_MAIR1_REG                     ( *( ( volatile uint32_t * ) 0xe000edc4 ) )\n\n#define portMPU_RBAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */\n#define portMPU_RLAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */\n\n#define portMPU_MAIR_ATTR0_POS                ( 0UL )\n#define portMPU_MAIR_ATTR0_MASK               ( 0x000000ff )\n\n#define portMPU_MAIR_ATTR1_POS                ( 8UL )\n#define portMPU_MAIR_ATTR1_MASK               ( 0x0000ff00 )\n\n#define portMPU_MAIR_ATTR2_POS                ( 16UL )\n#define portMPU_MAIR_ATTR2_MASK               ( 0x00ff0000 )\n\n#define portMPU_MAIR_ATTR3_POS                ( 24UL )\n#define portMPU_MAIR_ATTR3_MASK               ( 0xff000000 )\n\n#define portMPU_MAIR_ATTR4_POS                ( 0UL )\n#define portMPU_MAIR_ATTR4_MASK               ( 0x000000ff )\n\n#define portMPU_MAIR_ATTR5_POS                ( 8UL )\n#define portMPU_MAIR_ATTR5_MASK               ( 0x0000ff00 )\n\n#define portMPU_MAIR_ATTR6_POS                ( 16UL )\n#define portMPU_MAIR_ATTR6_MASK               ( 0x00ff0000 )\n\n#define portMPU_MAIR_ATTR7_POS                ( 24UL )\n#define portMPU_MAIR_ATTR7_MASK               ( 0xff000000 )\n\n#define portMPU_RLAR_ATTR_INDEX0              ( 0UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX1              ( 1UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX2              ( 2UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX3              ( 3UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX4              ( 4UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX5              ( 5UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX6              ( 6UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX7              ( 7UL << 1UL )\n\n#define portMPU_RLAR_REGION_ENABLE            ( 1UL )\n\n/* Enable privileged access to unmapped region. */\n#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )\n\n/* Enable MPU. */\n#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )\n\n/* Expected value of the portMPU_TYPE register. */\n#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief The maximum 24-bit number.\n *\n * It is needed because the systick is a 24-bit counter.\n */\n#define portMAX_24_BIT_NUMBER       ( 0xffffffUL )\n\n/**\n * @brief A fiddle factor to estimate the number of SysTick counts that would\n * have occurred while the SysTick counter is stopped during tickless idle\n * calculations.\n */\n#define portMISSED_COUNTS_FACTOR    ( 94UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to set up the initial stack.\n */\n#define portINITIAL_XPSR    ( 0x01000000 )\n\n#if ( configRUN_FREERTOS_SECURE_ONLY == 1 )\n\n/**\n * @brief Initial EXC_RETURN value.\n *\n *     FF         FF         FF         FD\n * 1111 1111  1111 1111  1111 1111  1111 1101\n *\n * Bit[6] - 1 --> The exception was taken from the Secure state.\n * Bit[5] - 1 --> Do not skip stacking of additional state context.\n * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\n * Bit[3] - 1 --> Return to the Thread mode.\n * Bit[2] - 1 --> Restore registers from the process stack.\n * Bit[1] - 0 --> Reserved, 0.\n * Bit[0] - 1 --> The exception was taken to the Secure state.\n */\n    #define portINITIAL_EXC_RETURN    ( 0xfffffffd )\n#else\n\n/**\n * @brief Initial EXC_RETURN value.\n *\n *     FF         FF         FF         BC\n * 1111 1111  1111 1111  1111 1111  1011 1100\n *\n * Bit[6] - 0 --> The exception was taken from the Non-Secure state.\n * Bit[5] - 1 --> Do not skip stacking of additional state context.\n * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\n * Bit[3] - 1 --> Return to the Thread mode.\n * Bit[2] - 1 --> Restore registers from the process stack.\n * Bit[1] - 0 --> Reserved, 0.\n * Bit[0] - 0 --> The exception was taken to the Non-Secure state.\n */\n    #define portINITIAL_EXC_RETURN    ( 0xffffffbc )\n#endif /* configRUN_FREERTOS_SECURE_ONLY */\n\n/**\n * @brief CONTROL register privileged bit mask.\n *\n * Bit[0] in CONTROL register tells the privilege:\n *  Bit[0] = 0 ==> The task is privileged.\n *  Bit[0] = 1 ==> The task is not privileged.\n */\n#define portCONTROL_PRIVILEGED_MASK         ( 1UL << 0UL )\n\n/**\n * @brief Initial CONTROL register values.\n */\n#define portINITIAL_CONTROL_UNPRIVILEGED    ( 0x3 )\n#define portINITIAL_CONTROL_PRIVILEGED      ( 0x2 )\n\n/**\n * @brief Let the user override the default SysTick clock rate.  If defined by the\n * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the\n * configuration register.\n */\n#ifndef configSYSTICK_CLOCK_HZ\n    #define configSYSTICK_CLOCK_HZ             ( configCPU_CLOCK_HZ )\n    /* Ensure the SysTick is clocked at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( portNVIC_SYSTICK_CLK_BIT )\n#else\n    /* Select the option to clock SysTick not at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( 0 )\n#endif\n\n/**\n * @brief Let the user override the pre-loading of the initial LR with the\n * address of prvTaskExitError() in case it messes up unwinding of the stack\n * in the debugger.\n */\n#ifdef configTASK_RETURN_ADDRESS\n    #define portTASK_RETURN_ADDRESS    configTASK_RETURN_ADDRESS\n#else\n    #define portTASK_RETURN_ADDRESS    prvTaskExitError\n#endif\n\n/**\n * @brief If portPRELOAD_REGISTERS then registers will be given an initial value\n * when a task is created. This helps in debugging at the cost of code size.\n */\n#define portPRELOAD_REGISTERS    1\n\n/**\n * @brief A task is created without a secure context, and must call\n * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes\n * any secure calls.\n */\n#define portNO_SECURE_CONTEXT    0\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Used to catch tasks that attempt to return from their implementing\n * function.\n */\nstatic void prvTaskExitError( void );\n\n#if ( configENABLE_MPU == 1 )\n\n/**\n * @brief Setup the Memory Protection Unit (MPU).\n */\n    static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\n#endif /* configENABLE_MPU */\n\n#if ( configENABLE_FPU == 1 )\n\n/**\n * @brief Setup the Floating Point Unit (FPU).\n */\n    static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;\n#endif /* configENABLE_FPU */\n\n/**\n * @brief Setup the timer to generate the tick interrupts.\n *\n * The implementation in this file is weak to allow application writers to\n * change the timer used to generate the tick interrupt.\n */\nvoid vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Checks whether the current execution context is interrupt.\n *\n * @return pdTRUE if the current execution context is interrupt, pdFALSE\n * otherwise.\n */\nBaseType_t xPortIsInsideInterrupt( void );\n\n/**\n * @brief Yield the processor.\n */\nvoid vPortYield( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Enter critical section.\n */\nvoid vPortEnterCritical( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Exit from critical section.\n */\nvoid vPortExitCritical( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief SysTick handler.\n */\nvoid SysTick_Handler( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief C part of SVC handler.\n */\nportDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION;\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Each task maintains its own interrupt status in the critical nesting\n * variable.\n */\nPRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;\n\n#if ( configENABLE_TRUSTZONE == 1 )\n\n/**\n * @brief Saved as part of the task context to indicate which context the\n * task is using on the secure side.\n */\n    PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;\n#endif /* configENABLE_TRUSTZONE */\n\n#if ( configUSE_TICKLESS_IDLE == 1 )\n\n/**\n * @brief The number of SysTick increments that make up one tick period.\n */\n    PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0;\n\n/**\n * @brief The maximum number of tick periods that can be suppressed is\n * limited by the 24 bit resolution of the SysTick timer.\n */\n    PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0;\n\n/**\n * @brief Compensate for the CPU cycles that pass while the SysTick is\n * stopped (low power functionality only).\n */\n    PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TICKLESS_IDLE == 1 )\n    __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )\n    {\n        uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;\n        TickType_t xModifiableIdleTime;\n\n        /* Make sure the SysTick reload value does not overflow the counter. */\n        if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\n        {\n            xExpectedIdleTime = xMaximumPossibleSuppressedTicks;\n        }\n\n        /* Enter a critical section but don't use the taskENTER_CRITICAL()\n         * method as that will mask interrupts that should exit sleep mode. */\n        __asm volatile ( \"cpsid i\" ::: \"memory\" );\n        __asm volatile ( \"dsb\" );\n        __asm volatile ( \"isb\" );\n\n        /* If a context switch is pending or a task is waiting for the scheduler\n         * to be unsuspended then abandon the low power entry. */\n        if( eTaskConfirmSleepModeStatus() == eAbortSleep )\n        {\n            /* Re-enable interrupts - see comments above the cpsid instruction\n             * above. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n        }\n        else\n        {\n            /* Stop the SysTick momentarily.  The time the SysTick is stopped for\n             * is accounted for as best it can be, but using the tickless mode will\n             * inevitably result in some tiny drift of the time maintained by the\n             * kernel with respect to calendar time. */\n            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );\n\n            /* Use the SysTick current-value register to determine the number of\n             * SysTick decrements remaining until the next tick interrupt.  If the\n             * current-value register is zero, then there are actually\n             * ulTimerCountsForOneTick decrements remaining, not zero, because the\n             * SysTick requests the interrupt when decrementing from 1 to 0. */\n            ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n\n            if( ulSysTickDecrementsLeft == 0 )\n            {\n                ulSysTickDecrementsLeft = ulTimerCountsForOneTick;\n            }\n\n            /* Calculate the reload value required to wait xExpectedIdleTime\n             * tick periods.  -1 is used because this code normally executes part\n             * way through the first tick period.  But if the SysTick IRQ is now\n             * pending, then clear the IRQ, suppressing the first tick, and correct\n             * the reload value to reflect that the second tick period is already\n             * underway.  The expected idle time is always at least two ticks. */\n            ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );\n\n            if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )\n            {\n                portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;\n                ulReloadValue -= ulTimerCountsForOneTick;\n            }\n\n            if( ulReloadValue > ulStoppedTimerCompensation )\n            {\n                ulReloadValue -= ulStoppedTimerCompensation;\n            }\n\n            /* Set the new reload value. */\n            portNVIC_SYSTICK_LOAD_REG = ulReloadValue;\n\n            /* Clear the SysTick count flag and set the count value back to\n             * zero. */\n            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n            /* Restart SysTick. */\n            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\n\n            /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can\n             * set its parameter to 0 to indicate that its implementation contains\n             * its own wait for interrupt or wait for event instruction, and so wfi\n             * should not be executed again.  However, the original expected idle\n             * time variable must remain unmodified, so a copy is taken. */\n            xModifiableIdleTime = xExpectedIdleTime;\n            configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\n\n            if( xModifiableIdleTime > 0 )\n            {\n                __asm volatile ( \"dsb\" ::: \"memory\" );\n                __asm volatile ( \"wfi\" );\n                __asm volatile ( \"isb\" );\n            }\n\n            configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\n\n            /* Re-enable interrupts to allow the interrupt that brought the MCU\n             * out of sleep mode to execute immediately.  See comments above\n             * the cpsid instruction above. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n            __asm volatile ( \"dsb\" );\n            __asm volatile ( \"isb\" );\n\n            /* Disable interrupts again because the clock is about to be stopped\n             * and interrupts that execute while the clock is stopped will increase\n             * any slippage between the time maintained by the RTOS and calendar\n             * time. */\n            __asm volatile ( \"cpsid i\" ::: \"memory\" );\n            __asm volatile ( \"dsb\" );\n            __asm volatile ( \"isb\" );\n\n            /* Disable the SysTick clock without reading the\n             * portNVIC_SYSTICK_CTRL_REG register to ensure the\n             * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,\n             * the time the SysTick is stopped for is accounted for as best it can\n             * be, but using the tickless mode will inevitably result in some tiny\n             * drift of the time maintained by the kernel with respect to calendar\n             * time*/\n            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );\n\n            /* Determine whether the SysTick has already counted to zero. */\n            if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n            {\n                uint32_t ulCalculatedLoadValue;\n\n                /* The tick interrupt ended the sleep (or is now pending), and\n                 * a new tick period has started.  Reset portNVIC_SYSTICK_LOAD_REG\n                 * with whatever remains of the new tick period. */\n                ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\n\n                /* Don't allow a tiny value, or values that have somehow\n                 * underflowed because the post sleep hook did something\n                 * that took too long or because the SysTick current-value register\n                 * is zero. */\n                if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )\n                {\n                    ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );\n                }\n\n                portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;\n\n                /* As the pending tick will be processed as soon as this\n                 * function exits, the tick value maintained by the tick is stepped\n                 * forward by one less than the time spent waiting. */\n                ulCompleteTickPeriods = xExpectedIdleTime - 1UL;\n            }\n            else\n            {\n                /* Something other than the tick interrupt ended the sleep. */\n\n                /* Use the SysTick current-value register to determine the\n                 * number of SysTick decrements remaining until the expected idle\n                 * time would have ended. */\n                ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n                #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )\n                {\n                    /* If the SysTick is not using the core clock, the current-\n                     * value register might still be zero here.  In that case, the\n                     * SysTick didn't load from the reload register, and there are\n                     * ulReloadValue decrements remaining in the expected idle\n                     * time, not zero. */\n                    if( ulSysTickDecrementsLeft == 0 )\n                    {\n                        ulSysTickDecrementsLeft = ulReloadValue;\n                    }\n                }\n                #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */\n\n                /* Work out how long the sleep lasted rounded to complete tick\n                 * periods (not the ulReload value which accounted for part\n                 * ticks). */\n                ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;\n\n                /* How many complete tick periods passed while the processor\n                 * was waiting? */\n                ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;\n\n                /* The reload value is set to whatever fraction of a single tick\n                 * period remains. */\n                portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;\n            }\n\n            /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,\n             * then set portNVIC_SYSTICK_LOAD_REG back to its standard value.  If\n             * the SysTick is not using the core clock, temporarily configure it to\n             * use the core clock.  This configuration forces the SysTick to load\n             * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next\n             * cycle of the other clock.  Then portNVIC_SYSTICK_LOAD_REG is ready\n             * to receive the standard value immediately. */\n            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n            portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n            #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )\n            {\n                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n            }\n            #else\n            {\n                /* The temporary usage of the core clock has served its purpose,\n                 * as described above.  Resume usage of the other clock. */\n                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\n\n                if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n                {\n                    /* The partial tick period already ended.  Be sure the SysTick\n                     * counts it only once. */\n                    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;\n                }\n\n                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n            }\n            #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */\n\n            /* Step the tick to account for any tick periods that elapsed. */\n            vTaskStepTick( ulCompleteTickPeriods );\n\n            /* Exit with interrupts enabled. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n        }\n    }\n#endif /* configUSE_TICKLESS_IDLE */\n/*-----------------------------------------------------------*/\n\n__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Calculate the constants required to configure the tick interrupt. */\n    #if ( configUSE_TICKLESS_IDLE == 1 )\n    {\n        ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );\n        xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;\n        ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\n    }\n    #endif /* configUSE_TICKLESS_IDLE */\n\n    /* Stop and reset the SysTick. */\n    portNVIC_SYSTICK_CTRL_REG = 0UL;\n    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n    /* Configure SysTick to interrupt at the requested rate. */\n    portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\n    portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvTaskExitError( void )\n{\n    volatile uint32_t ulDummy = 0UL;\n\n    /* A function that implements a task must not exit or attempt to return to\n     * its caller as there is nothing to return to. If a task wants to exit it\n     * should instead call vTaskDelete( NULL ). Artificially force an assert()\n     * to be triggered if configASSERT() is defined, then stop here so\n     * application writers can catch the error. */\n    configASSERT( ulCriticalNesting == ~0UL );\n    portDISABLE_INTERRUPTS();\n\n    while( ulDummy == 0 )\n    {\n        /* This file calls prvTaskExitError() after the scheduler has been\n         * started to remove a compiler warning about the function being\n         * defined but never called.  ulDummy is used purely to quieten other\n         * warnings about code appearing after this function is called - making\n         * ulDummy volatile makes the compiler think the function could return\n         * and therefore not output an 'unreachable code' warning for code that\n         * appears after it. */\n    }\n}\n/*-----------------------------------------------------------*/\n\n#if ( configENABLE_MPU == 1 )\n    static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */\n    {\n        #if defined( __ARMCC_VERSION )\n\n            /* Declaration when these variable are defined in code instead of being\n             * exported from linker scripts. */\n            extern uint32_t * __privileged_functions_start__;\n            extern uint32_t * __privileged_functions_end__;\n            extern uint32_t * __syscalls_flash_start__;\n            extern uint32_t * __syscalls_flash_end__;\n            extern uint32_t * __unprivileged_flash_start__;\n            extern uint32_t * __unprivileged_flash_end__;\n            extern uint32_t * __privileged_sram_start__;\n            extern uint32_t * __privileged_sram_end__;\n        #else /* if defined( __ARMCC_VERSION ) */\n            /* Declaration when these variable are exported from linker scripts. */\n            extern uint32_t __privileged_functions_start__[];\n            extern uint32_t __privileged_functions_end__[];\n            extern uint32_t __syscalls_flash_start__[];\n            extern uint32_t __syscalls_flash_end__[];\n            extern uint32_t __unprivileged_flash_start__[];\n            extern uint32_t __unprivileged_flash_end__[];\n            extern uint32_t __privileged_sram_start__[];\n            extern uint32_t __privileged_sram_end__[];\n        #endif /* defined( __ARMCC_VERSION ) */\n\n        /* The only permitted number of regions are 8 or 16. */\n        configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );\n\n        /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */\n        configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );\n\n        /* Check that the MPU is present. */\n        if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )\n        {\n            /* MAIR0 - Index 0. */\n            portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\n            /* MAIR0 - Index 1. */\n            portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\n\n            /* Setup privileged flash as Read Only so that privileged tasks can\n             * read it but not modify. */\n            portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_PRIVILEGED_READ_ONLY );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Setup unprivileged flash as Read Only by both privileged and\n             * unprivileged tasks. All tasks can read it but no-one can modify. */\n            portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_READ_ONLY );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Setup unprivileged syscalls flash as Read Only by both privileged\n             * and unprivileged tasks. All tasks can read it but no-one can modify. */\n            portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_READ_ONLY );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Setup RAM containing kernel data for privileged access only. */\n            portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\n                               ( portMPU_REGION_EXECUTE_NEVER );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Enable mem fault. */\n            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;\n\n            /* Enable MPU with privileged background access i.e. unmapped\n             * regions have privileged access. */\n            portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );\n        }\n    }\n#endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\n#if ( configENABLE_FPU == 1 )\n    static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */\n    {\n        #if ( configENABLE_TRUSTZONE == 1 )\n        {\n            /* Enable non-secure access to the FPU. */\n            SecureInit_EnableNSFPUAccess();\n        }\n        #endif /* configENABLE_TRUSTZONE */\n\n        /* CP10 = 11 ==> Full access to FPU i.e. both privileged and\n         * unprivileged code should be able to access FPU. CP11 should be\n         * programmed to the same value as CP10. */\n        *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |\n                            ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )\n                            );\n\n        /* ASPEN = 1 ==> Hardware should automatically preserve floating point\n         * context on exception entry and restore on exception return.\n         * LSPEN = 1 ==> Enable lazy context save of FP state. */\n        *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );\n    }\n#endif /* configENABLE_FPU */\n/*-----------------------------------------------------------*/\n\nvoid vPortYield( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Set a PendSV to request a context switch. */\n    portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\n\n    /* Barriers are normally not required but do ensure the code is\n     * completely within the specified behaviour for the architecture. */\n    __asm volatile ( \"dsb\" ::: \"memory\" );\n    __asm volatile ( \"isb\" );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */\n{\n    portDISABLE_INTERRUPTS();\n    ulCriticalNesting++;\n\n    /* Barriers are normally not required but do ensure the code is\n     * completely within the specified behaviour for the architecture. */\n    __asm volatile ( \"dsb\" ::: \"memory\" );\n    __asm volatile ( \"isb\" );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */\n{\n    configASSERT( ulCriticalNesting );\n    ulCriticalNesting--;\n\n    if( ulCriticalNesting == 0 )\n    {\n        portENABLE_INTERRUPTS();\n    }\n}\n/*-----------------------------------------------------------*/\n\nvoid SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */\n{\n    uint32_t ulPreviousMask;\n\n    ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();\n    {\n        /* Increment the RTOS tick. */\n        if( xTaskIncrementTick() != pdFALSE )\n        {\n            /* Pend a context switch. */\n            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\n        }\n    }\n    portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */\n{\n    #if ( configENABLE_MPU == 1 )\n        #if defined( __ARMCC_VERSION )\n\n            /* Declaration when these variable are defined in code instead of being\n             * exported from linker scripts. */\n            extern uint32_t * __syscalls_flash_start__;\n            extern uint32_t * __syscalls_flash_end__;\n        #else\n            /* Declaration when these variable are exported from linker scripts. */\n            extern uint32_t __syscalls_flash_start__[];\n            extern uint32_t __syscalls_flash_end__[];\n        #endif /* defined( __ARMCC_VERSION ) */\n    #endif /* configENABLE_MPU */\n\n    uint32_t ulPC;\n\n    #if ( configENABLE_TRUSTZONE == 1 )\n        uint32_t ulR0, ulR1;\n        extern TaskHandle_t pxCurrentTCB;\n        #if ( configENABLE_MPU == 1 )\n            uint32_t ulControl, ulIsTaskPrivileged;\n        #endif /* configENABLE_MPU */\n    #endif /* configENABLE_TRUSTZONE */\n    uint8_t ucSVCNumber;\n\n    /* Register are stored on the stack in the following order - R0, R1, R2, R3,\n     * R12, LR, PC, xPSR. */\n    ulPC = pulCallerStackAddress[ 6 ];\n    ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];\n\n    switch( ucSVCNumber )\n    {\n        #if ( configENABLE_TRUSTZONE == 1 )\n            case portSVC_ALLOCATE_SECURE_CONTEXT:\n\n                /* R0 contains the stack size passed as parameter to the\n                 * vPortAllocateSecureContext function. */\n                ulR0 = pulCallerStackAddress[ 0 ];\n\n                #if ( configENABLE_MPU == 1 )\n                {\n                    /* Read the CONTROL register value. */\n                    __asm volatile ( \"mrs %0, control\"  : \"=r\" ( ulControl ) );\n\n                    /* The task that raised the SVC is privileged if Bit[0]\n                     * in the CONTROL register is 0. */\n                    ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );\n\n                    /* Allocate and load a context for the secure task. */\n                    xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );\n                }\n                #else /* if ( configENABLE_MPU == 1 ) */\n                {\n                    /* Allocate and load a context for the secure task. */\n                    xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );\n                }\n                #endif /* configENABLE_MPU */\n\n                configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );\n                SecureContext_LoadContext( xSecureContext, pxCurrentTCB );\n                break;\n\n            case portSVC_FREE_SECURE_CONTEXT:\n\n                /* R0 contains TCB being freed and R1 contains the secure\n                 * context handle to be freed. */\n                ulR0 = pulCallerStackAddress[ 0 ];\n                ulR1 = pulCallerStackAddress[ 1 ];\n\n                /* Free the secure context. */\n                SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );\n                break;\n        #endif /* configENABLE_TRUSTZONE */\n\n        case portSVC_START_SCHEDULER:\n            #if ( configENABLE_TRUSTZONE == 1 )\n            {\n                /* De-prioritize the non-secure exceptions so that the\n                 * non-secure pendSV runs at the lowest priority. */\n                SecureInit_DePrioritizeNSExceptions();\n\n                /* Initialize the secure context management system. */\n                SecureContext_Init();\n            }\n            #endif /* configENABLE_TRUSTZONE */\n\n            #if ( configENABLE_FPU == 1 )\n            {\n                /* Setup the Floating Point Unit (FPU). */\n                prvSetupFPU();\n            }\n            #endif /* configENABLE_FPU */\n\n            /* Setup the context of the first task so that the first task starts\n             * executing. */\n            vRestoreContextOfFirstTask();\n            break;\n\n            #if ( configENABLE_MPU == 1 )\n                case portSVC_RAISE_PRIVILEGE:\n\n                    /* Only raise the privilege, if the svc was raised from any of\n                     * the system calls. */\n                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&\n                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )\n                    {\n                        vRaisePrivilege();\n                    }\n                    break;\n            #endif /* configENABLE_MPU */\n\n        default:\n            /* Incorrect SVC call. */\n            configASSERT( pdFALSE );\n    }\n}\n/*-----------------------------------------------------------*/\n/* *INDENT-OFF* */\n#if ( configENABLE_MPU == 1 )\n    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,\n                                         StackType_t * pxEndOfStack,\n                                         TaskFunction_t pxCode,\n                                         void * pvParameters,\n                                         BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */\n#else\n    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,\n                                         StackType_t * pxEndOfStack,\n                                         TaskFunction_t pxCode,\n                                         void * pvParameters ) /* PRIVILEGED_FUNCTION */\n#endif /* configENABLE_MPU */\n/* *INDENT-ON* */\n{\n    /* Simulate the stack frame as it would be created by a context switch\n     * interrupt. */\n    #if ( portPRELOAD_REGISTERS == 0 )\n    {\n        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\n        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\n        pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */\n        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */\n        pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */\n        *pxTopOfStack = portINITIAL_EXC_RETURN;\n\n        #if ( configENABLE_MPU == 1 )\n        {\n            pxTopOfStack--;\n\n            if( xRunPrivileged == pdTRUE )\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n            else\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n        }\n        #endif /* configENABLE_MPU */\n\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\n\n        #if ( configENABLE_TRUSTZONE == 1 )\n        {\n            pxTopOfStack--;\n            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\n        }\n        #endif /* configENABLE_TRUSTZONE */\n    }\n    #else /* portPRELOAD_REGISTERS */\n    {\n        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\n        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04 */\n        pxTopOfStack--;\n        *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN */\n\n        #if ( configENABLE_MPU == 1 )\n        {\n            pxTopOfStack--;\n\n            if( xRunPrivileged == pdTRUE )\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n            else\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n        }\n        #endif /* configENABLE_MPU */\n\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\n\n        #if ( configENABLE_TRUSTZONE == 1 )\n        {\n            pxTopOfStack--;\n            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\n        }\n        #endif /* configENABLE_TRUSTZONE */\n    }\n    #endif /* portPRELOAD_REGISTERS */\n\n    return pxTopOfStack;\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Make PendSV, CallSV and SysTick the same priority as the kernel. */\n    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;\n    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;\n\n    #if ( configENABLE_MPU == 1 )\n    {\n        /* Setup the Memory Protection Unit (MPU). */\n        prvSetupMPU();\n    }\n    #endif /* configENABLE_MPU */\n\n    /* Start the timer that generates the tick ISR. Interrupts are disabled\n     * here already. */\n    vPortSetupTimerInterrupt();\n\n    /* Initialize the critical nesting count ready for the first task. */\n    ulCriticalNesting = 0;\n\n    /* Start the first task. */\n    vStartFirstTask();\n\n    /* Should never get here as the tasks will now be executing. Call the task\n     * exit error function to prevent compiler warnings about a static function\n     * not being called in the case that the application writer overrides this\n     * functionality by defining configTASK_RETURN_ADDRESS. Call\n     * vTaskSwitchContext() so link time optimization does not remove the\n     * symbol. */\n    vTaskSwitchContext();\n    prvTaskExitError();\n\n    /* Should not get here. */\n    return 0;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Not implemented in ports where there is nothing to return to.\n     * Artificially force an assert. */\n    configASSERT( ulCriticalNesting == 1000UL );\n}\n/*-----------------------------------------------------------*/\n\n#if ( configENABLE_MPU == 1 )\n    void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,\n                                    const struct xMEMORY_REGION * const xRegions,\n                                    StackType_t * pxBottomOfStack,\n                                    uint32_t ulStackDepth )\n    {\n        uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;\n        int32_t lIndex = 0;\n\n        #if defined( __ARMCC_VERSION )\n\n            /* Declaration when these variable are defined in code instead of being\n             * exported from linker scripts. */\n            extern uint32_t * __privileged_sram_start__;\n            extern uint32_t * __privileged_sram_end__;\n        #else\n            /* Declaration when these variable are exported from linker scripts. */\n            extern uint32_t __privileged_sram_start__[];\n            extern uint32_t __privileged_sram_end__[];\n        #endif /* defined( __ARMCC_VERSION ) */\n\n        /* Setup MAIR0. */\n        xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\n        xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\n\n        /* This function is called automatically when the task is created - in\n         * which case the stack region parameters will be valid.  At all other\n         * times the stack parameters will not be valid and it is assumed that\n         * the stack region has already been configured. */\n        if( ulStackDepth > 0 )\n        {\n            ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;\n            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;\n\n            /* If the stack is within the privileged SRAM, do not protect it\n             * using a separate MPU region. This is needed because privileged\n             * SRAM is already protected using an MPU region and ARMv8-M does\n             * not allow overlapping MPU regions. */\n            if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) &&\n                ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) )\n            {\n                xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0;\n                xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0;\n            }\n            else\n            {\n                /* Define the region that allows access to the stack. */\n                ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK;\n                ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\n\n                xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |\n                                                             ( portMPU_REGION_NON_SHAREABLE ) |\n                                                             ( portMPU_REGION_READ_WRITE ) |\n                                                             ( portMPU_REGION_EXECUTE_NEVER );\n\n                xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) |\n                                                             ( portMPU_RLAR_ATTR_INDEX0 ) |\n                                                             ( portMPU_RLAR_REGION_ENABLE );\n            }\n        }\n\n        /* User supplied configurable regions. */\n        for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )\n        {\n            /* If xRegions is NULL i.e. the task has not specified any MPU\n             * region, the else part ensures that all the configurable MPU\n             * regions are invalidated. */\n            if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )\n            {\n                /* Translate the generic region definition contained in xRegions\n                 * into the ARMv8 specific MPU settings that are then stored in\n                 * xMPUSettings. */\n                ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;\n                ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;\n                ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\n\n                /* Start address. */\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |\n                                                                          ( portMPU_REGION_NON_SHAREABLE );\n\n                /* RO/RW. */\n                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )\n                {\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );\n                }\n                else\n                {\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );\n                }\n\n                /* XN. */\n                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )\n                {\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );\n                }\n\n                /* End Address. */\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |\n                                                                          ( portMPU_RLAR_REGION_ENABLE );\n\n                /* Normal memory/ Device memory. */\n                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )\n                {\n                    /* Attr1 in MAIR0 is configured as device memory. */\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;\n                }\n                else\n                {\n                    /* Attr0 in MAIR0 is configured as normal memory. */\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;\n                }\n            }\n            else\n            {\n                /* Invalidate the region. */\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;\n            }\n\n            lIndex++;\n        }\n    }\n#endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\nBaseType_t xPortIsInsideInterrupt( void )\n{\n    uint32_t ulCurrentInterrupt;\n    BaseType_t xReturn;\n\n    /* Obtain the number of the currently executing interrupt. Interrupt Program\n     * Status Register (IPSR) holds the exception number of the currently-executing\n     * exception or zero for Thread mode.*/\n    __asm volatile ( \"mrs %0, ipsr\" : \"=r\" ( ulCurrentInterrupt )::\"memory\" );\n\n    if( ulCurrentInterrupt == 0 )\n    {\n        xReturn = pdFALSE;\n    }\n    else\n    {\n        xReturn = pdTRUE;\n    }\n\n    return xReturn;\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Standard includes. */\n#include <stdint.h>\n\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION\n * is defined correctly and privileged functions are placed in correct sections. */\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/* Portasm includes. */\n#include \"portasm.h\"\n\n/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the\n * header files. */\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n#if ( configENABLE_FPU == 1 )\n    #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.\n#endif\n\nvoid vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr  r2, pxCurrentTCBConst2\t\t\t\t\t\t\\n\"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n        \"\tldr  r1, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Read pxCurrentTCB. */\n        \"\tldr  r0, [r1]\t\t\t\t\t\t\t\t\t\\n\"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"\tdmb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Complete outstanding transfers before disabling MPU. */\n            \"\tldr r2, xMPUCTRLConst2\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n            \"\tldr r3, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Read the value of MPU_CTRL. */\n            \"\tmovs r4, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* r4 = 1. */\n            \"\tbics r3, r4\t\t\t\t\t\t\t\t\t\t\\n\"/* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */\n            \"\tstr r3, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Disable MPU. */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tadds r1, #4\t\t\t\t\t\t\t\t\t\t\\n\"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\n            \"\tldr  r4, [r1]\t\t\t\t\t\t\t\t\t\\n\"/* r4 = *r1 i.e. r4 = MAIR0. */\n            \"\tldr  r2, xMAIR0Const2\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000edc0 [Location of MAIR0]. */\n            \"\tstr  r4, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Program MAIR0. */\n            \"\tldr  r2, xRNRConst2\t\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed98 [Location of RNR]. */\n            \"\tadds r1, #4\t\t\t\t\t\t\t\t\t\t\\n\"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\n            \"\tmovs r4, #4\t\t\t\t\t\t\t\t\t\t\\n\"/* r4 = 4. */\n            \"\tstr  r4, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 4. */\n            \"\tldmia r1!, {r5,r6}\t\t\t\t\t\t\t\t\\n\"/* Read first set of RBAR/RLAR from TCB. */\n            \"\tldr  r3, xRBARConst2\t\t\t\t\t\t\t\\n\"/* r3 = 0xe000ed9c [Location of RBAR]. */\n            \"\tstmia r3!, {r5,r6}\t\t\t\t\t\t\t\t\\n\"/* Write first set of RBAR/RLAR registers. */\n            \"\tmovs r4, #5\t\t\t\t\t\t\t\t\t\t\\n\"/* r4 = 5. */\n            \"\tstr  r4, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 5. */\n            \"\tldmia r1!, {r5,r6}\t\t\t\t\t\t\t\t\\n\"/* Read second set of RBAR/RLAR from TCB. */\n            \"\tldr  r3, xRBARConst2\t\t\t\t\t\t\t\\n\"/* r3 = 0xe000ed9c [Location of RBAR]. */\n            \"\tstmia r3!, {r5,r6}\t\t\t\t\t\t\t\t\\n\"/* Write second set of RBAR/RLAR registers. */\n            \"\tmovs r4, #6\t\t\t\t\t\t\t\t\t\t\\n\"/* r4 = 6. */\n            \"\tstr  r4, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 6. */\n            \"\tldmia r1!, {r5,r6}\t\t\t\t\t\t\t\t\\n\"/* Read third set of RBAR/RLAR from TCB. */\n            \"\tldr  r3, xRBARConst2\t\t\t\t\t\t\t\\n\"/* r3 = 0xe000ed9c [Location of RBAR]. */\n            \"\tstmia r3!, {r5,r6}\t\t\t\t\t\t\t\t\\n\"/* Write third set of RBAR/RLAR registers. */\n            \"\tmovs r4, #7\t\t\t\t\t\t\t\t\t\t\\n\"/* r4 = 7. */\n            \"\tstr  r4, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 7. */\n            \"\tldmia r1!, {r5,r6}\t\t\t\t\t\t\t\t\\n\"/* Read fourth set of RBAR/RLAR from TCB. */\n            \"\tldr  r3, xRBARConst2\t\t\t\t\t\t\t\\n\"/* r3 = 0xe000ed9c [Location of RBAR]. */\n            \"\tstmia r3!, {r5,r6}\t\t\t\t\t\t\t\t\\n\"/* Write fourth set of RBAR/RLAR registers. */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tldr r2, xMPUCTRLConst2\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n            \"\tldr r3, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Read the value of MPU_CTRL. */\n            \"\tmovs r4, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* r4 = 1. */\n            \"\torrs r3, r4\t\t\t\t\t\t\t\t\t\t\\n\"/* r3 = r3 | r4 i.e. Set the bit 0 in r3. */\n            \"\tstr r3, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Enable MPU. */\n            \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Force memory writes before continuing. */\n        #endif /* configENABLE_MPU */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"\tldm  r0!, {r1-r3}\t\t\t\t\t\t\t\t\\n\"/* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */\n            \"\tmsr  psplim, r1\t\t\t\t\t\t\t\t\t\\n\"/* Set this task's PSPLIM value. */\n            \"\tmsr  control, r2\t\t\t\t\t\t\t\t\\n\"/* Set this task's CONTROL value. */\n            \"\tadds r0, #32\t\t\t\t\t\t\t\t\t\\n\"/* Discard everything up to r0. */\n            \"\tmsr  psp, r0\t\t\t\t\t\t\t\t\t\\n\"/* This is now the new top of stack to use in the task. */\n            \"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tbx   r3\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Finally, branch to EXC_RETURN. */\n        #else /* configENABLE_MPU */\n            \"\tldm  r0!, {r1-r2}\t\t\t\t\t\t\t\t\\n\"/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */\n            \"\tmsr  psplim, r1\t\t\t\t\t\t\t\t\t\\n\"/* Set this task's PSPLIM value. */\n            \"\tmovs r1, #2\t\t\t\t\t\t\t\t\t\t\\n\"/* r1 = 2. */\n            \"\tmsr  CONTROL, r1\t\t\t\t\t\t\t\t\\n\"/* Switch to use PSP in the thread mode. */\n            \"\tadds r0, #32\t\t\t\t\t\t\t\t\t\\n\"/* Discard everything up to r0. */\n            \"\tmsr  psp, r0\t\t\t\t\t\t\t\t\t\\n\"/* This is now the new top of stack to use in the task. */\n            \"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tbx   r2\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Finally, branch to EXC_RETURN. */\n        #endif /* configENABLE_MPU */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.align 4\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"pxCurrentTCBConst2: .word pxCurrentTCB\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"xMPUCTRLConst2: .word 0xe000ed94\t\t\t\t\t\\n\"\n            \"xMAIR0Const2: .word 0xe000edc0\t\t\t\t\t\t\\n\"\n            \"xRNRConst2: .word 0xe000ed98\t\t\t\t\t\t\\n\"\n            \"xRBARConst2: .word 0xe000ed9c\t\t\t\t\t\t\\n\"\n        #endif /* configENABLE_MPU */\n    );\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrs r0, control\t\t\t\t\t\t\t\t\t\\n\"/* r0 = CONTROL. */\n        \"\tmovs r1, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* r1 = 1. */\n        \"\ttst r0, r1\t\t\t\t\t\t\t\t\t\t\\n\"/* Perform r0 & r1 (bitwise AND) and update the conditions flag. */\n        \"\tbeq running_privileged\t\t\t\t\t\t\t\\n\"/* If the result of previous AND operation was 0, branch. */\n        \"\tmovs r0, #0\t\t\t\t\t\t\t\t\t\t\\n\"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return. */\n        \" running_privileged:\t\t\t\t\t\t\t\t\\n\"\n        \"\tmovs r0, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return. */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.align 4\t\t\t\t\t\t\t\t\t\t\\n\"\n        ::: \"r0\", \"r1\", \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrs  r0, control\t\t\t\t\t\t\t\t\\n\"/* Read the CONTROL register. */\n        \"\tmovs r1, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* r1 = 1. */\n        \"\tbics r0, r1\t\t\t\t\t\t\t\t\t\t\\n\"/* Clear the bit 0. */\n        \"\tmsr  control, r0\t\t\t\t\t\t\t\t\\n\"/* Write back the new CONTROL value. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return to the caller. */\n        ::: \"r0\", \"r1\", \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vResetPrivilege( void ) /* __attribute__ (( naked )) */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrs r0, control\t\t\t\t\t\t\t\t\t\\n\"/* r0 = CONTROL. */\n        \"\tmovs r1, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* r1 = 1. */\n        \"\torrs r0, r1\t\t\t\t\t\t\t\t\t\t\\n\"/* r0 = r0 | r1. */\n        \"\tmsr control, r0\t\t\t\t\t\t\t\t\t\\n\"/* CONTROL = r0. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return to the caller. */\n        ::: \"r0\", \"r1\", \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r0, xVTORConst\t\t\t\t\t\t\t\t\\n\"/* Use the NVIC offset register to locate the stack. */\n        \"\tldr r0, [r0]\t\t\t\t\t\t\t\t\t\\n\"/* Read the VTOR register which gives the address of vector table. */\n        \"\tldr r0, [r0]\t\t\t\t\t\t\t\t\t\\n\"/* The first entry in vector table is stack pointer. */\n        \"\tmsr msp, r0\t\t\t\t\t\t\t\t\t\t\\n\"/* Set the MSP back to the start of the stack. */\n        \"\tcpsie i\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Globally enable interrupts. */\n        \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tsvc %0\t\t\t\t\t\t\t\t\t\t\t\\n\"/* System call to start the first task. */\n        \"\tnop\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"   .align 4\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"xVTORConst: .word 0xe000ed08\t\t\t\t\t\t\\n\"\n        ::\"i\" ( portSVC_START_SCHEDULER ) : \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nuint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrs r0, PRIMASK\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tcpsid i\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        ::: \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmsr PRIMASK, r0\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        ::: \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrs r0, psp\t\t\t\t\t\t\t\t\t\t\\n\"/* Read PSP in r0. */\n        \"\tldr r2, pxCurrentTCBConst\t\t\t\t\t\t\\n\"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n        \"\tldr r1, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Read pxCurrentTCB. */\n        #if ( configENABLE_MPU == 1 )\n            \"\tsubs r0, r0, #44\t\t\t\t\t\t\t\t\\n\"/* Make space for PSPLIM, CONTROL, LR and the remaining registers on the stack. */\n            \"\tstr r0, [r1]\t\t\t\t\t\t\t\t\t\\n\"/* Save the new top of stack in TCB. */\n            \"\tmrs r1, psplim\t\t\t\t\t\t\t\t\t\\n\"/* r1 = PSPLIM. */\n            \"\tmrs r2, control\t\t\t\t\t\t\t\t\t\\n\"/* r2 = CONTROL. */\n            \"\tmov r3, lr\t\t\t\t\t\t\t\t\t\t\\n\"/* r3 = LR/EXC_RETURN. */\n            \"\tstmia r0!, {r1-r7}\t\t\t\t\t\t\t\t\\n\"/* Store on the stack - PSPLIM, CONTROL, LR and low registers that are not automatically saved. */\n            \"\tmov r4, r8\t\t\t\t\t\t\t\t\t\t\\n\"/* r4 = r8. */\n            \"\tmov r5, r9\t\t\t\t\t\t\t\t\t\t\\n\"/* r5 = r9. */\n            \"\tmov r6, r10\t\t\t\t\t\t\t\t\t\t\\n\"/* r6 = r10. */\n            \"\tmov r7, r11\t\t\t\t\t\t\t\t\t\t\\n\"/* r7 = r11. */\n            \"\tstmia r0!, {r4-r7}\t\t\t\t\t\t\t\t\\n\"/* Store the high registers that are not saved automatically. */\n        #else /* configENABLE_MPU */\n            \"\tsubs r0, r0, #40\t\t\t\t\t\t\t\t\\n\"/* Make space for PSPLIM, LR and the remaining registers on the stack. */\n            \"\tstr r0, [r1]\t\t\t\t\t\t\t\t\t\\n\"/* Save the new top of stack in TCB. */\n            \"\tmrs r2, psplim\t\t\t\t\t\t\t\t\t\\n\"/* r2 = PSPLIM. */\n            \"\tmov r3, lr\t\t\t\t\t\t\t\t\t\t\\n\"/* r3 = LR/EXC_RETURN. */\n            \"\tstmia r0!, {r2-r7}\t\t\t\t\t\t\t\t\\n\"/* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */\n            \"\tmov r4, r8\t\t\t\t\t\t\t\t\t\t\\n\"/* r4 = r8. */\n            \"\tmov r5, r9\t\t\t\t\t\t\t\t\t\t\\n\"/* r5 = r9. */\n            \"\tmov r6, r10\t\t\t\t\t\t\t\t\t\t\\n\"/* r6 = r10. */\n            \"\tmov r7, r11\t\t\t\t\t\t\t\t\t\t\\n\"/* r7 = r11. */\n            \"\tstmia r0!, {r4-r7}\t\t\t\t\t\t\t\t\\n\"/* Store the high registers that are not saved automatically. */\n        #endif /* configENABLE_MPU */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tcpsid i\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tbl vTaskSwitchContext\t\t\t\t\t\t\t\\n\"\n        \"\tcpsie i\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r2, pxCurrentTCBConst\t\t\t\t\t\t\\n\"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n        \"\tldr r1, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Read pxCurrentTCB. */\n        \"\tldr r0, [r1]\t\t\t\t\t\t\t\t\t\\n\"/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"\tdmb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Complete outstanding transfers before disabling MPU. */\n            \"\tldr r2, xMPUCTRLConst\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n            \"\tldr r3, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Read the value of MPU_CTRL. */\n            \"\tmovs r4, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* r4 = 1. */\n            \"\tbics r3, r4\t\t\t\t\t\t\t\t\t\t\\n\"/* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */\n            \"\tstr r3, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Disable MPU. */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tadds r1, #4\t\t\t\t\t\t\t\t\t\t\\n\"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\n            \"\tldr  r4, [r1]\t\t\t\t\t\t\t\t\t\\n\"/* r4 = *r1 i.e. r4 = MAIR0. */\n            \"\tldr  r2, xMAIR0Const\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000edc0 [Location of MAIR0]. */\n            \"\tstr  r4, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Program MAIR0. */\n            \"\tldr  r2, xRNRConst\t\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed98 [Location of RNR]. */\n            \"\tadds r1, #4\t\t\t\t\t\t\t\t\t\t\\n\"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\n            \"\tmovs r4, #4\t\t\t\t\t\t\t\t\t\t\\n\"/* r4 = 4. */\n            \"\tstr  r4, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 4. */\n            \"\tldmia r1!, {r5,r6}\t\t\t\t\t\t\t\t\\n\"/* Read first set of RBAR/RLAR from TCB. */\n            \"\tldr  r3, xRBARConst\t\t\t\t\t\t\t\t\\n\"/* r3 = 0xe000ed9c [Location of RBAR]. */\n            \"\tstmia r3!, {r5,r6}\t\t\t\t\t\t\t\t\\n\"/* Write first set of RBAR/RLAR registers. */\n            \"\tmovs r4, #5\t\t\t\t\t\t\t\t\t\t\\n\"/* r4 = 5. */\n            \"\tstr  r4, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 5. */\n            \"\tldmia r1!, {r5,r6}\t\t\t\t\t\t\t\t\\n\"/* Read second set of RBAR/RLAR from TCB. */\n            \"\tldr  r3, xRBARConst\t\t\t\t\t\t\t\t\\n\"/* r3 = 0xe000ed9c [Location of RBAR]. */\n            \"\tstmia r3!, {r5,r6}\t\t\t\t\t\t\t\t\\n\"/* Write second set of RBAR/RLAR registers. */\n            \"\tmovs r4, #6\t\t\t\t\t\t\t\t\t\t\\n\"/* r4 = 6. */\n            \"\tstr  r4, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 6. */\n            \"\tldmia r1!, {r5,r6}\t\t\t\t\t\t\t\t\\n\"/* Read third set of RBAR/RLAR from TCB. */\n            \"\tldr  r3, xRBARConst\t\t\t\t\t\t\t\t\\n\"/* r3 = 0xe000ed9c [Location of RBAR]. */\n            \"\tstmia r3!, {r5,r6}\t\t\t\t\t\t\t\t\\n\"/* Write third set of RBAR/RLAR registers. */\n            \"\tmovs r4, #7\t\t\t\t\t\t\t\t\t\t\\n\"/* r4 = 7. */\n            \"\tstr  r4, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 7. */\n            \"\tldmia r1!, {r5,r6}\t\t\t\t\t\t\t\t\\n\"/* Read fourth set of RBAR/RLAR from TCB. */\n            \"\tldr  r3, xRBARConst\t\t\t\t\t\t\t\t\\n\"/* r3 = 0xe000ed9c [Location of RBAR]. */\n            \"\tstmia r3!, {r5,r6}\t\t\t\t\t\t\t\t\\n\"/* Write fourth set of RBAR/RLAR registers. */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tldr r2, xMPUCTRLConst\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n            \"\tldr r3, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Read the value of MPU_CTRL. */\n            \"\tmovs r4, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* r4 = 1. */\n            \"\torrs r3, r4\t\t\t\t\t\t\t\t\t\t\\n\"/* r3 = r3 | r4 i.e. Set the bit 0 in r3. */\n            \"\tstr r3, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Enable MPU. */\n            \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Force memory writes before continuing. */\n        #endif /* configENABLE_MPU */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"\tadds r0, r0, #28\t\t\t\t\t\t\t\t\\n\"/* Move to the high registers. */\n            \"\tldmia r0!, {r4-r7}\t\t\t\t\t\t\t\t\\n\"/* Restore the high registers that are not automatically restored. */\n            \"\tmov r8, r4\t\t\t\t\t\t\t\t\t\t\\n\"/* r8 = r4. */\n            \"\tmov r9, r5\t\t\t\t\t\t\t\t\t\t\\n\"/* r9 = r5. */\n            \"\tmov r10, r6\t\t\t\t\t\t\t\t\t\t\\n\"/* r10 = r6. */\n            \"\tmov r11, r7\t\t\t\t\t\t\t\t\t\t\\n\"/* r11 = r7. */\n            \"\tmsr psp, r0\t\t\t\t\t\t\t\t\t\t\\n\"/* Remember the new top of stack for the task. */\n            \"\tsubs r0, r0, #44\t\t\t\t\t\t\t\t\\n\"/* Move to the starting of the saved context. */\n            \"\tldmia r0!, {r1-r7}\t\t\t\t\t\t\t\t\\n\"/* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r7 restored. */\n            \"\tmsr psplim, r1\t\t\t\t\t\t\t\t\t\\n\"/* Restore the PSPLIM register value for the task. */\n            \"\tmsr control, r2\t\t\t\t\t\t\t\t\t\\n\"/* Restore the CONTROL register value for the task. */\n            \"\tbx r3\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #else /* configENABLE_MPU */\n            \"\tadds r0, r0, #24\t\t\t\t\t\t\t\t\\n\"/* Move to the high registers. */\n            \"\tldmia r0!, {r4-r7}\t\t\t\t\t\t\t\t\\n\"/* Restore the high registers that are not automatically restored. */\n            \"\tmov r8, r4\t\t\t\t\t\t\t\t\t\t\\n\"/* r8 = r4. */\n            \"\tmov r9, r5\t\t\t\t\t\t\t\t\t\t\\n\"/* r9 = r5. */\n            \"\tmov r10, r6\t\t\t\t\t\t\t\t\t\t\\n\"/* r10 = r6. */\n            \"\tmov r11, r7\t\t\t\t\t\t\t\t\t\t\\n\"/* r11 = r7. */\n            \"\tmsr psp, r0\t\t\t\t\t\t\t\t\t\t\\n\"/* Remember the new top of stack for the task. */\n            \"\tsubs r0, r0, #40\t\t\t\t\t\t\t\t\\n\"/* Move to the starting of the saved context. */\n            \"\tldmia r0!, {r2-r7}\t\t\t\t\t\t\t\t\\n\"/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */\n            \"\tmsr psplim, r2\t\t\t\t\t\t\t\t\t\\n\"/* Restore the PSPLIM register value for the task. */\n            \"\tbx r3\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #endif /* configENABLE_MPU */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.align 4\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"pxCurrentTCBConst: .word pxCurrentTCB\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"xMPUCTRLConst: .word 0xe000ed94\t\t\t\t\t\\n\"\n            \"xMAIR0Const: .word 0xe000edc0\t\t\t\t\t\t\\n\"\n            \"xRNRConst: .word 0xe000ed98\t\t\t\t\t\t\\n\"\n            \"xRBARConst: .word 0xe000ed9c\t\t\t\t\t\t\\n\"\n        #endif /* configENABLE_MPU */\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmovs r0, #4\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmov r1, lr\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\ttst r0, r1\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tbeq stacking_used_msp\t\t\t\t\t\t\t\\n\"\n        \"\tmrs r0, psp\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r2, svchandler_address_const\t\t\t\t\\n\"\n        \"\tbx r2\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \" stacking_used_msp:\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrs r0, msp\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r2, svchandler_address_const\t\t\t\t\\n\"\n        \"\tbx r2\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.align 4\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"svchandler_address_const: .word vPortSVCHandler_C\t\\n\"\n    );\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef __PORT_ASM_H__\n#define __PORT_ASM_H__\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n\n/* MPU wrappers includes. */\n#include \"mpu_wrappers.h\"\n\n/**\n * @brief Restore the context of the first task so that the first task starts\n * executing.\n */\nvoid vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Checks whether or not the processor is privileged.\n *\n * @return 1 if the processor is already privileged, 0 otherwise.\n */\nBaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );\n\n/**\n * @brief Raises the privilege level by clearing the bit 0 of the CONTROL\n * register.\n *\n * @note This is a privileged function and should only be called from the kenrel\n * code.\n *\n * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.\n *  Bit[0] = 0 --> The processor is running privileged\n *  Bit[0] = 1 --> The processor is running unprivileged.\n */\nvoid vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\n * register.\n *\n * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.\n *  Bit[0] = 0 --> The processor is running privileged\n *  Bit[0] = 1 --> The processor is running unprivileged.\n */\nvoid vResetPrivilege( void ) __attribute__( ( naked ) );\n\n/**\n * @brief Starts the first task.\n */\nvoid vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Disables interrupts.\n */\nuint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Enables interrupts.\n */\nvoid vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief PendSV Exception handler.\n */\nvoid PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief SVC Handler.\n */\nvoid SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Allocate a Secure context for the calling task.\n *\n * @param[in] ulSecureStackSize The size of the stack to be allocated on the\n * secure side for the calling task.\n */\nvoid vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) );\n\n/**\n * @brief Free the task's secure context.\n *\n * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.\n */\nvoid vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n#endif /* __PORT_ASM_H__ */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef PORTMACRO_H\n#define PORTMACRO_H\n\n#ifdef __cplusplus\n    extern \"C\" {\n#endif\n\n#include \"portmacrocommon.h\"\n\n/*------------------------------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the given hardware\n * and compiler.\n *\n * These settings should not be altered.\n *------------------------------------------------------------------------------\n */\n\n/**\n * Architecture specifics.\n */\n#define portARCH_NAME                       \"Cortex-M23\"\n#define portDONT_DISCARD                    __attribute__( ( used ) )\n/*-----------------------------------------------------------*/\n\n#if( configTOTAL_MPU_REGIONS == 16 )\n    #error 16 MPU regions are not yet supported for this port.\n#endif\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Critical section management.\n */\n#define portDISABLE_INTERRUPTS()            __asm volatile ( \" cpsid i \" ::: \"memory\" )\n#define portENABLE_INTERRUPTS()             __asm volatile ( \" cpsie i \" ::: \"memory\" )\n/*-----------------------------------------------------------*/\n\n#ifdef __cplusplus\n    }\n#endif\n\n#endif /* PORTMACRO_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef PORTMACROCOMMON_H\n    #define PORTMACROCOMMON_H\n\n    #ifdef __cplusplus\n        extern \"C\" {\n    #endif\n\n/*------------------------------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the given hardware\n * and compiler.\n *\n * These settings should not be altered.\n *------------------------------------------------------------------------------\n */\n\n    #ifndef configENABLE_FPU\n        #error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.\n    #endif /* configENABLE_FPU */\n\n    #ifndef configENABLE_MPU\n        #error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.\n    #endif /* configENABLE_MPU */\n\n    #ifndef configENABLE_TRUSTZONE\n        #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.\n    #endif /* configENABLE_TRUSTZONE */\n\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Type definitions.\n */\n    #define portCHAR          char\n    #define portFLOAT         float\n    #define portDOUBLE        double\n    #define portLONG          long\n    #define portSHORT         short\n    #define portSTACK_TYPE    uint32_t\n    #define portBASE_TYPE     long\n\n    typedef portSTACK_TYPE   StackType_t;\n    typedef long             BaseType_t;\n    typedef unsigned long    UBaseType_t;\n\n    #if ( configUSE_16_BIT_TICKS == 1 )\n        typedef uint16_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffff\n    #else\n        typedef uint32_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL\n\n/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\n * not need to be guarded with a critical section. */\n        #define portTICK_TYPE_IS_ATOMIC    1\n    #endif\n/*-----------------------------------------------------------*/\n\n/**\n * Architecture specifics.\n */\n    #define portSTACK_GROWTH                   ( -1 )\n    #define portTICK_PERIOD_MS                 ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\n    #define portBYTE_ALIGNMENT                 8\n    #define portNOP()\n    #define portINLINE                         __inline\n    #ifndef portFORCE_INLINE\n        #define portFORCE_INLINE               inline __attribute__( ( always_inline ) )\n    #endif\n    #define portHAS_STACK_OVERFLOW_CHECKING    1\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Extern declarations.\n */\n    extern BaseType_t xPortIsInsideInterrupt( void );\n\n    extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;\n\n    extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;\n    extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;\n\n    extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\n    extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\n\n    #if ( configENABLE_TRUSTZONE == 1 )\n        extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */\n        extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;\n    #endif /* configENABLE_TRUSTZONE */\n\n    #if ( configENABLE_MPU == 1 )\n        extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;\n        extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;\n    #endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\n/**\n * @brief MPU specific constants.\n */\n    #if ( configENABLE_MPU == 1 )\n        #define portUSING_MPU_WRAPPERS    1\n        #define portPRIVILEGE_BIT         ( 0x80000000UL )\n    #else\n        #define portPRIVILEGE_BIT         ( 0x0UL )\n    #endif /* configENABLE_MPU */\n\n/* MPU settings that can be overriden in FreeRTOSConfig.h. */\n#ifndef configTOTAL_MPU_REGIONS\n    /* Define to 8 for backward compatibility. */\n    #define configTOTAL_MPU_REGIONS       ( 8UL )\n#endif\n\n/* MPU regions. */\n    #define portPRIVILEGED_FLASH_REGION                   ( 0UL )\n    #define portUNPRIVILEGED_FLASH_REGION                 ( 1UL )\n    #define portUNPRIVILEGED_SYSCALLS_REGION              ( 2UL )\n    #define portPRIVILEGED_RAM_REGION                     ( 3UL )\n    #define portSTACK_REGION                              ( 4UL )\n    #define portFIRST_CONFIGURABLE_REGION                 ( 5UL )\n    #define portLAST_CONFIGURABLE_REGION                  ( configTOTAL_MPU_REGIONS - 1UL )\n    #define portNUM_CONFIGURABLE_REGIONS                  ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )\n    #define portTOTAL_NUM_REGIONS                         ( portNUM_CONFIGURABLE_REGIONS + 1 )   /* Plus one to make space for the stack region. */\n\n/* Device memory attributes used in MPU_MAIR registers.\n *\n * 8-bit values encoded as follows:\n *  Bit[7:4] - 0000 - Device Memory\n *  Bit[3:2] - 00 --> Device-nGnRnE\n *\t\t\t\t01 --> Device-nGnRE\n *\t\t\t\t10 --> Device-nGRE\n *\t\t\t\t11 --> Device-GRE\n *  Bit[1:0] - 00, Reserved.\n */\n    #define portMPU_DEVICE_MEMORY_nGnRnE                  ( 0x00 )   /* 0000 0000 */\n    #define portMPU_DEVICE_MEMORY_nGnRE                   ( 0x04 )   /* 0000 0100 */\n    #define portMPU_DEVICE_MEMORY_nGRE                    ( 0x08 )   /* 0000 1000 */\n    #define portMPU_DEVICE_MEMORY_GRE                     ( 0x0C )   /* 0000 1100 */\n\n/* Normal memory attributes used in MPU_MAIR registers. */\n    #define portMPU_NORMAL_MEMORY_NON_CACHEABLE           ( 0x44 )   /* Non-cacheable. */\n    #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE    ( 0xFF )   /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */\n\n/* Attributes used in MPU_RBAR registers. */\n    #define portMPU_REGION_NON_SHAREABLE                  ( 0UL << 3UL )\n    #define portMPU_REGION_INNER_SHAREABLE                ( 1UL << 3UL )\n    #define portMPU_REGION_OUTER_SHAREABLE                ( 2UL << 3UL )\n\n    #define portMPU_REGION_PRIVILEGED_READ_WRITE          ( 0UL << 1UL )\n    #define portMPU_REGION_READ_WRITE                     ( 1UL << 1UL )\n    #define portMPU_REGION_PRIVILEGED_READ_ONLY           ( 2UL << 1UL )\n    #define portMPU_REGION_READ_ONLY                      ( 3UL << 1UL )\n\n    #define portMPU_REGION_EXECUTE_NEVER                  ( 1UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Settings to define an MPU region.\n */\n    typedef struct MPURegionSettings\n    {\n        uint32_t ulRBAR; /**< RBAR for the region. */\n        uint32_t ulRLAR; /**< RLAR for the region. */\n    } MPURegionSettings_t;\n\n/**\n * @brief MPU settings as stored in the TCB.\n */\n    typedef struct MPU_SETTINGS\n    {\n        uint32_t ulMAIR0;                                              /**< MAIR0 for the task containing attributes for all the 4 per task regions. */\n        MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */\n    } xMPU_SETTINGS;\n/*-----------------------------------------------------------*/\n\n/**\n * @brief SVC numbers.\n */\n    #define portSVC_ALLOCATE_SECURE_CONTEXT    0\n    #define portSVC_FREE_SECURE_CONTEXT        1\n    #define portSVC_START_SCHEDULER            2\n    #define portSVC_RAISE_PRIVILEGE            3\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Scheduler utilities.\n */\n    #define portYIELD()                                 vPortYield()\n    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )\n    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )\n    #define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )\n    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Critical section management.\n */\n    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulSetInterruptMask()\n    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vClearInterruptMask( x )\n    #define portENTER_CRITICAL()                      vPortEnterCritical()\n    #define portEXIT_CRITICAL()                       vPortExitCritical()\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Tickless idle/low power functionality.\n */\n    #ifndef portSUPPRESS_TICKS_AND_SLEEP\n        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );\n        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )\n    #endif\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Task function macros as described on the FreeRTOS.org WEB site.\n */\n    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )\n    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )\n/*-----------------------------------------------------------*/\n\n    #if ( configENABLE_TRUSTZONE == 1 )\n\n/**\n * @brief Allocate a secure context for the task.\n *\n * Tasks are not created with a secure context. Any task that is going to call\n * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a\n * secure context before it calls any secure function.\n *\n * @param[in] ulSecureStackSize The size of the secure stack to be allocated.\n */\n        #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )\n\n/**\n * @brief Called when a task is deleted to delete the task's secure context,\n * if it has one.\n *\n * @param[in] pxTCB The TCB of the task being deleted.\n */\n        #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )\n    #endif /* configENABLE_TRUSTZONE */\n/*-----------------------------------------------------------*/\n\n    #if ( configENABLE_MPU == 1 )\n\n/**\n * @brief Checks whether or not the processor is privileged.\n *\n * @return 1 if the processor is already privileged, 0 otherwise.\n */\n        #define portIS_PRIVILEGED()      xIsPrivileged()\n\n/**\n * @brief Raise an SVC request to raise privilege.\n *\n * The SVC handler checks that the SVC was raised from a system call and only\n * then it raises the privilege. If this is called from any other place,\n * the privilege is not raised.\n */\n        #define portRAISE_PRIVILEGE()    __asm volatile ( \"svc %0 \\n\" ::\"i\" ( portSVC_RAISE_PRIVILEGE ) : \"memory\" );\n\n/**\n * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\n * register.\n */\n        #define portRESET_PRIVILEGE()    vResetPrivilege()\n    #else\n        #define portIS_PRIVILEGED()\n        #define portRAISE_PRIVILEGE()\n        #define portRESET_PRIVILEGE()\n    #endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Barriers.\n */\n    #define portMEMORY_BARRIER()    __asm volatile ( \"\" ::: \"memory\" )\n/*-----------------------------------------------------------*/\n\n    #ifdef __cplusplus\n        }\n    #endif\n\n#endif /* PORTMACROCOMMON_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM3/port.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/*-----------------------------------------------------------\n* Implementation of functions defined in portable.h for the ARM CM3 port.\n*----------------------------------------------------------*/\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n/* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is\n * defined.  The value should also ensure backward compatibility.\n * FreeRTOS.org versions prior to V4.4.0 did not include this definition. */\n#ifndef configKERNEL_INTERRUPT_PRIORITY\n    #define configKERNEL_INTERRUPT_PRIORITY    255\n#endif\n\n/* Constants required to manipulate the core.  Registers first... */\n#define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )\n#define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )\n#define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )\n#define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )\n/* ...then bits in the registers. */\n#define portNVIC_SYSTICK_CLK_BIT              ( 1UL << 2UL )\n#define portNVIC_SYSTICK_INT_BIT              ( 1UL << 1UL )\n#define portNVIC_SYSTICK_ENABLE_BIT           ( 1UL << 0UL )\n#define portNVIC_SYSTICK_COUNT_FLAG_BIT       ( 1UL << 16UL )\n#define portNVIC_PENDSVCLEAR_BIT              ( 1UL << 27UL )\n#define portNVIC_PEND_SYSTICK_SET_BIT         ( 1UL << 26UL )\n#define portNVIC_PEND_SYSTICK_CLEAR_BIT       ( 1UL << 25UL )\n\n#define portNVIC_PENDSV_PRI                   ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\n#define portNVIC_SYSTICK_PRI                  ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\n\n/* Constants required to check the validity of an interrupt priority. */\n#define portFIRST_USER_INTERRUPT_NUMBER       ( 16 )\n#define portNVIC_IP_REGISTERS_OFFSET_16       ( 0xE000E3F0 )\n#define portAIRCR_REG                         ( *( ( volatile uint32_t * ) 0xE000ED0C ) )\n#define portMAX_8_BIT_VALUE                   ( ( uint8_t ) 0xff )\n#define portTOP_BIT_OF_BYTE                   ( ( uint8_t ) 0x80 )\n#define portMAX_PRIGROUP_BITS                 ( ( uint8_t ) 7 )\n#define portPRIORITY_GROUP_MASK               ( 0x07UL << 8UL )\n#define portPRIGROUP_SHIFT                    ( 8UL )\n\n/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */\n#define portVECTACTIVE_MASK                   ( 0xFFUL )\n\n/* Constants required to set up the initial stack. */\n#define portINITIAL_XPSR                      ( 0x01000000UL )\n\n/* The systick is a 24-bit counter. */\n#define portMAX_24_BIT_NUMBER                 ( 0xffffffUL )\n\n/* A fiddle factor to estimate the number of SysTick counts that would have\n * occurred while the SysTick counter is stopped during tickless idle\n * calculations. */\n#define portMISSED_COUNTS_FACTOR              ( 94UL )\n\n/* For strict compliance with the Cortex-M spec the task start address should\n * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */\n#define portSTART_ADDRESS_MASK                ( ( StackType_t ) 0xfffffffeUL )\n\n/* Let the user override the default SysTick clock rate.  If defined by the\n * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the\n * configuration register. */\n#ifndef configSYSTICK_CLOCK_HZ\n    #define configSYSTICK_CLOCK_HZ             ( configCPU_CLOCK_HZ )\n    /* Ensure the SysTick is clocked at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( portNVIC_SYSTICK_CLK_BIT )\n#else\n    /* Select the option to clock SysTick not at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( 0 )\n#endif\n\n/* Let the user override the pre-loading of the initial LR with the address of\n * prvTaskExitError() in case it messes up unwinding of the stack in the\n * debugger. */\n#ifdef configTASK_RETURN_ADDRESS\n    #define portTASK_RETURN_ADDRESS    configTASK_RETURN_ADDRESS\n#else\n    #define portTASK_RETURN_ADDRESS    prvTaskExitError\n#endif\n\n/*\n * Setup the timer to generate the tick interrupts.  The implementation in this\n * file is weak to allow application writers to change the timer used to\n * generate the tick interrupt.\n */\nvoid vPortSetupTimerInterrupt( void );\n\n/*\n * Exception handlers.\n */\nvoid xPortPendSVHandler( void ) __attribute__( ( naked ) );\nvoid xPortSysTickHandler( void );\nvoid vPortSVCHandler( void ) __attribute__( ( naked ) );\n\n/*\n * Start first task is a separate function so it can be tested in isolation.\n */\nstatic void prvPortStartFirstTask( void ) __attribute__( ( naked ) );\n\n/*\n * Used to catch tasks that attempt to return from their implementing function.\n */\nstatic void prvTaskExitError( void );\n\n/*-----------------------------------------------------------*/\n\n/* Each task maintains its own interrupt status in the critical nesting\n * variable. */\nstatic UBaseType_t uxCriticalNesting = 0xaaaaaaaa;\n\n/*\n * The number of SysTick increments that make up one tick period.\n */\n#if ( configUSE_TICKLESS_IDLE == 1 )\n    static uint32_t ulTimerCountsForOneTick = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n\n/*\n * The maximum number of tick periods that can be suppressed is limited by the\n * 24 bit resolution of the SysTick timer.\n */\n#if ( configUSE_TICKLESS_IDLE == 1 )\n    static uint32_t xMaximumPossibleSuppressedTicks = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n\n/*\n * Compensate for the CPU cycles that pass while the SysTick is stopped (low\n * power functionality only.\n */\n#if ( configUSE_TICKLESS_IDLE == 1 )\n    static uint32_t ulStoppedTimerCompensation = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n\n/*\n * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure\n * FreeRTOS API functions are not called from interrupts that have been assigned\n * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.\n */\n#if ( configASSERT_DEFINED == 1 )\n    static uint8_t ucMaxSysCallPriority = 0;\n    static uint32_t ulMaxPRIGROUPValue = 0;\n    static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;\n#endif /* configASSERT_DEFINED */\n\n/*-----------------------------------------------------------*/\n\n/*\n * See header file for description.\n */\nStackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,\n                                     TaskFunction_t pxCode,\n                                     void * pvParameters )\n{\n    /* Simulate the stack frame as it would be created by a context switch\n     * interrupt. */\n    pxTopOfStack--;                                                      /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\n    *pxTopOfStack = portINITIAL_XPSR;                                    /* xPSR */\n    pxTopOfStack--;\n    *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */\n    pxTopOfStack--;\n    *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;             /* LR */\n    pxTopOfStack -= 5;                                                   /* R12, R3, R2 and R1. */\n    *pxTopOfStack = ( StackType_t ) pvParameters;                        /* R0 */\n    pxTopOfStack -= 8;                                                   /* R11, R10, R9, R8, R7, R6, R5 and R4. */\n\n    return pxTopOfStack;\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvTaskExitError( void )\n{\n    volatile uint32_t ulDummy = 0UL;\n\n    /* A function that implements a task must not exit or attempt to return to\n     * its caller as there is nothing to return to.  If a task wants to exit it\n     * should instead call vTaskDelete( NULL ).\n     *\n     * Artificially force an assert() to be triggered if configASSERT() is\n     * defined, then stop here so application writers can catch the error. */\n    configASSERT( uxCriticalNesting == ~0UL );\n    portDISABLE_INTERRUPTS();\n\n    while( ulDummy == 0 )\n    {\n        /* This file calls prvTaskExitError() after the scheduler has been\n         * started to remove a compiler warning about the function being defined\n         * but never called.  ulDummy is used purely to quieten other warnings\n         * about code appearing after this function is called - making ulDummy\n         * volatile makes the compiler think the function could return and\n         * therefore not output an 'unreachable code' warning for code that appears\n         * after it. */\n    }\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortSVCHandler( void )\n{\n    __asm volatile (\n        \"\tldr\tr3, pxCurrentTCBConst2\t\t\\n\"/* Restore the context. */\n        \"\tldr r1, [r3]\t\t\t\t\t\\n\"/* Use pxCurrentTCBConst to get the pxCurrentTCB address. */\n        \"\tldr r0, [r1]\t\t\t\t\t\\n\"/* The first item in pxCurrentTCB is the task top of stack. */\n        \"\tldmia r0!, {r4-r11}\t\t\t\t\\n\"/* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */\n        \"\tmsr psp, r0\t\t\t\t\t\t\\n\"/* Restore the task stack pointer. */\n        \"\tisb\t\t\t\t\t\t\t\t\\n\"\n        \"\tmov r0, #0 \t\t\t\t\t\t\\n\"\n        \"\tmsr\tbasepri, r0\t\t\t\t\t\\n\"\n        \"\torr r14, #0xd\t\t\t\t\t\\n\"\n        \"\tbx r14\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.align 4\t\t\t\t\t\t\\n\"\n        \"pxCurrentTCBConst2: .word pxCurrentTCB\t\t\t\t\\n\"\n        );\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvPortStartFirstTask( void )\n{\n    __asm volatile (\n        \" ldr r0, =0xE000ED08 \t\\n\"/* Use the NVIC offset register to locate the stack. */\n        \" ldr r0, [r0] \t\t\t\\n\"\n        \" ldr r0, [r0] \t\t\t\\n\"\n        \" msr msp, r0\t\t\t\\n\"/* Set the msp back to the start of the stack. */\n        \" cpsie i\t\t\t\t\\n\"/* Globally enable interrupts. */\n        \" cpsie f\t\t\t\t\\n\"\n        \" dsb\t\t\t\t\t\\n\"\n        \" isb\t\t\t\t\t\\n\"\n        \" svc 0\t\t\t\t\t\\n\"/* System call to start first task. */\n        \" nop\t\t\t\t\t\\n\"\n        \" .ltorg\t\t\t\t\\n\"\n        );\n}\n/*-----------------------------------------------------------*/\n\n/*\n * See header file for description.\n */\nBaseType_t xPortStartScheduler( void )\n{\n    /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.\n     * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\n    configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );\n\n    #if ( configASSERT_DEFINED == 1 )\n    {\n        volatile uint32_t ulOriginalPriority;\n        volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\n        volatile uint8_t ucMaxPriorityValue;\n\n        /* Determine the maximum priority from which ISR safe FreeRTOS API\n         * functions can be called.  ISR safe functions are those that end in\n         * \"FromISR\".  FreeRTOS maintains separate thread and ISR API functions to\n         * ensure interrupt entry is as fast and simple as possible.\n         *\n         * Save the interrupt priority value that is about to be clobbered. */\n        ulOriginalPriority = *pucFirstUserPriorityRegister;\n\n        /* Determine the number of priority bits available.  First write to all\n         * possible bits. */\n        *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\n\n        /* Read the value back to see how many bits stuck. */\n        ucMaxPriorityValue = *pucFirstUserPriorityRegister;\n\n        /* Use the same mask on the maximum system call priority. */\n        ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;\n\n        /* Calculate the maximum acceptable priority group value for the number\n         * of bits read back. */\n        ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;\n\n        while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )\n        {\n            ulMaxPRIGROUPValue--;\n            ucMaxPriorityValue <<= ( uint8_t ) 0x01;\n        }\n\n        #ifdef __NVIC_PRIO_BITS\n        {\n            /* Check the CMSIS configuration that defines the number of\n             * priority bits matches the number of priority bits actually queried\n             * from the hardware. */\n            configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );\n        }\n        #endif\n\n        #ifdef configPRIO_BITS\n        {\n            /* Check the FreeRTOS configuration that defines the number of\n             * priority bits matches the number of priority bits actually queried\n             * from the hardware. */\n            configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );\n        }\n        #endif\n\n        /* Shift the priority group value back to its position within the AIRCR\n         * register. */\n        ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;\n        ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;\n\n        /* Restore the clobbered interrupt priority register to its original\n         * value. */\n        *pucFirstUserPriorityRegister = ulOriginalPriority;\n    }\n    #endif /* configASSERT_DEFINED */\n\n    /* Make PendSV and SysTick the lowest priority interrupts. */\n    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;\n    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;\n\n    /* Start the timer that generates the tick ISR.  Interrupts are disabled\n     * here already. */\n    vPortSetupTimerInterrupt();\n\n    /* Initialise the critical nesting count ready for the first task. */\n    uxCriticalNesting = 0;\n\n    /* Start the first task. */\n    prvPortStartFirstTask();\n\n    /* Should never get here as the tasks will now be executing!  Call the task\n     * exit error function to prevent compiler warnings about a static function\n     * not being called in the case that the application writer overrides this\n     * functionality by defining configTASK_RETURN_ADDRESS.  Call\n     * vTaskSwitchContext() so link time optimisation does not remove the\n     * symbol. */\n    vTaskSwitchContext();\n    prvTaskExitError();\n\n    /* Should not get here! */\n    return 0;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEndScheduler( void )\n{\n    /* Not implemented in ports where there is nothing to return to.\n     * Artificially force an assert. */\n    configASSERT( uxCriticalNesting == 1000UL );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEnterCritical( void )\n{\n    portDISABLE_INTERRUPTS();\n    uxCriticalNesting++;\n\n    /* This is not the interrupt safe version of the enter critical function so\n     * assert() if it is being called from an interrupt context.  Only API\n     * functions that end in \"FromISR\" can be used in an interrupt.  Only assert if\n     * the critical nesting count is 1 to protect against recursive calls if the\n     * assert function also uses a critical section. */\n    if( uxCriticalNesting == 1 )\n    {\n        configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );\n    }\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortExitCritical( void )\n{\n    configASSERT( uxCriticalNesting );\n    uxCriticalNesting--;\n\n    if( uxCriticalNesting == 0 )\n    {\n        portENABLE_INTERRUPTS();\n    }\n}\n/*-----------------------------------------------------------*/\n\nvoid xPortPendSVHandler( void )\n{\n    /* This is a naked function. */\n\n    __asm volatile\n    (\n        \"\tmrs r0, psp\t\t\t\t\t\t\t\\n\"\n        \"\tisb\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr\tr3, pxCurrentTCBConst\t\t\t\\n\"/* Get the location of the current TCB. */\n        \"\tldr\tr2, [r3]\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tstmdb r0!, {r4-r11}\t\t\t\t\t\\n\"/* Save the remaining registers. */\n        \"\tstr r0, [r2]\t\t\t\t\t\t\\n\"/* Save the new top of stack into the first member of the TCB. */\n        \"\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tstmdb sp!, {r3, r14}\t\t\t\t\\n\"\n        \"\tmov r0, %0\t\t\t\t\t\t\t\\n\"\n        \"\tmsr basepri, r0\t\t\t\t\t\t\\n\"\n        \"\tbl vTaskSwitchContext\t\t\t\t\\n\"\n        \"\tmov r0, #0\t\t\t\t\t\t\t\\n\"\n        \"\tmsr basepri, r0\t\t\t\t\t\t\\n\"\n        \"\tldmia sp!, {r3, r14}\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\\n\"/* Restore the context, including the critical nesting count. */\n        \"\tldr r1, [r3]\t\t\t\t\t\t\\n\"\n        \"\tldr r0, [r1]\t\t\t\t\t\t\\n\"/* The first item in pxCurrentTCB is the task top of stack. */\n        \"\tldmia r0!, {r4-r11}\t\t\t\t\t\\n\"/* Pop the registers. */\n        \"\tmsr psp, r0\t\t\t\t\t\t\t\\n\"\n        \"\tisb\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tbx r14\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.align 4\t\t\t\t\t\t\t\\n\"\n        \"pxCurrentTCBConst: .word pxCurrentTCB\t\\n\"\n        ::\"i\" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid xPortSysTickHandler( void )\n{\n    /* The SysTick runs at the lowest interrupt priority, so when this interrupt\n     * executes all interrupts must be unmasked.  There is therefore no need to\n     * save and then restore the interrupt mask value as its value is already\n     * known. */\n    portDISABLE_INTERRUPTS();\n    {\n        /* Increment the RTOS tick. */\n        if( xTaskIncrementTick() != pdFALSE )\n        {\n            /* A context switch is required.  Context switching is performed in\n             * the PendSV interrupt.  Pend the PendSV interrupt. */\n            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\n        }\n    }\n    portENABLE_INTERRUPTS();\n}\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TICKLESS_IDLE == 1 )\n\n    __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )\n    {\n        uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;\n        TickType_t xModifiableIdleTime;\n\n        /* Make sure the SysTick reload value does not overflow the counter. */\n        if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\n        {\n            xExpectedIdleTime = xMaximumPossibleSuppressedTicks;\n        }\n\n        /* Enter a critical section but don't use the taskENTER_CRITICAL()\n         * method as that will mask interrupts that should exit sleep mode. */\n        __asm volatile ( \"cpsid i\" ::: \"memory\" );\n        __asm volatile ( \"dsb\" );\n        __asm volatile ( \"isb\" );\n\n        /* If a context switch is pending or a task is waiting for the scheduler\n         * to be unsuspended then abandon the low power entry. */\n        if( eTaskConfirmSleepModeStatus() == eAbortSleep )\n        {\n            /* Re-enable interrupts - see comments above the cpsid instruction\n             * above. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n        }\n        else\n        {\n            /* Stop the SysTick momentarily.  The time the SysTick is stopped for\n             * is accounted for as best it can be, but using the tickless mode will\n             * inevitably result in some tiny drift of the time maintained by the\n             * kernel with respect to calendar time. */\n            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );\n\n            /* Use the SysTick current-value register to determine the number of\n             * SysTick decrements remaining until the next tick interrupt.  If the\n             * current-value register is zero, then there are actually\n             * ulTimerCountsForOneTick decrements remaining, not zero, because the\n             * SysTick requests the interrupt when decrementing from 1 to 0. */\n            ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n\n            if( ulSysTickDecrementsLeft == 0 )\n            {\n                ulSysTickDecrementsLeft = ulTimerCountsForOneTick;\n            }\n\n            /* Calculate the reload value required to wait xExpectedIdleTime\n             * tick periods.  -1 is used because this code normally executes part\n             * way through the first tick period.  But if the SysTick IRQ is now\n             * pending, then clear the IRQ, suppressing the first tick, and correct\n             * the reload value to reflect that the second tick period is already\n             * underway.  The expected idle time is always at least two ticks. */\n            ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );\n\n            if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )\n            {\n                portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;\n                ulReloadValue -= ulTimerCountsForOneTick;\n            }\n\n            if( ulReloadValue > ulStoppedTimerCompensation )\n            {\n                ulReloadValue -= ulStoppedTimerCompensation;\n            }\n\n            /* Set the new reload value. */\n            portNVIC_SYSTICK_LOAD_REG = ulReloadValue;\n\n            /* Clear the SysTick count flag and set the count value back to\n             * zero. */\n            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n            /* Restart SysTick. */\n            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\n\n            /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can\n             * set its parameter to 0 to indicate that its implementation contains\n             * its own wait for interrupt or wait for event instruction, and so wfi\n             * should not be executed again.  However, the original expected idle\n             * time variable must remain unmodified, so a copy is taken. */\n            xModifiableIdleTime = xExpectedIdleTime;\n            configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\n\n            if( xModifiableIdleTime > 0 )\n            {\n                __asm volatile ( \"dsb\" ::: \"memory\" );\n                __asm volatile ( \"wfi\" );\n                __asm volatile ( \"isb\" );\n            }\n\n            configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\n\n            /* Re-enable interrupts to allow the interrupt that brought the MCU\n             * out of sleep mode to execute immediately.  See comments above\n             * the cpsid instruction above. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n            __asm volatile ( \"dsb\" );\n            __asm volatile ( \"isb\" );\n\n            /* Disable interrupts again because the clock is about to be stopped\n             * and interrupts that execute while the clock is stopped will increase\n             * any slippage between the time maintained by the RTOS and calendar\n             * time. */\n            __asm volatile ( \"cpsid i\" ::: \"memory\" );\n            __asm volatile ( \"dsb\" );\n            __asm volatile ( \"isb\" );\n\n            /* Disable the SysTick clock without reading the\n             * portNVIC_SYSTICK_CTRL_REG register to ensure the\n             * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,\n             * the time the SysTick is stopped for is accounted for as best it can\n             * be, but using the tickless mode will inevitably result in some tiny\n             * drift of the time maintained by the kernel with respect to calendar\n             * time*/\n            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );\n\n            /* Determine whether the SysTick has already counted to zero. */\n            if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n            {\n                uint32_t ulCalculatedLoadValue;\n\n                /* The tick interrupt ended the sleep (or is now pending), and\n                 * a new tick period has started.  Reset portNVIC_SYSTICK_LOAD_REG\n                 * with whatever remains of the new tick period. */\n                ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\n\n                /* Don't allow a tiny value, or values that have somehow\n                 * underflowed because the post sleep hook did something\n                 * that took too long or because the SysTick current-value register\n                 * is zero. */\n                if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )\n                {\n                    ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );\n                }\n\n                portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;\n\n                /* As the pending tick will be processed as soon as this\n                 * function exits, the tick value maintained by the tick is stepped\n                 * forward by one less than the time spent waiting. */\n                ulCompleteTickPeriods = xExpectedIdleTime - 1UL;\n            }\n            else\n            {\n                /* Something other than the tick interrupt ended the sleep. */\n\n                /* Use the SysTick current-value register to determine the\n                 * number of SysTick decrements remaining until the expected idle\n                 * time would have ended. */\n                ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n                #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )\n                {\n                    /* If the SysTick is not using the core clock, the current-\n                     * value register might still be zero here.  In that case, the\n                     * SysTick didn't load from the reload register, and there are\n                     * ulReloadValue decrements remaining in the expected idle\n                     * time, not zero. */\n                    if( ulSysTickDecrementsLeft == 0 )\n                    {\n                        ulSysTickDecrementsLeft = ulReloadValue;\n                    }\n                }\n                #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */\n\n                /* Work out how long the sleep lasted rounded to complete tick\n                 * periods (not the ulReload value which accounted for part\n                 * ticks). */\n                ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;\n\n                /* How many complete tick periods passed while the processor\n                 * was waiting? */\n                ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;\n\n                /* The reload value is set to whatever fraction of a single tick\n                 * period remains. */\n                portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;\n            }\n\n            /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,\n             * then set portNVIC_SYSTICK_LOAD_REG back to its standard value.  If\n             * the SysTick is not using the core clock, temporarily configure it to\n             * use the core clock.  This configuration forces the SysTick to load\n             * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next\n             * cycle of the other clock.  Then portNVIC_SYSTICK_LOAD_REG is ready\n             * to receive the standard value immediately. */\n            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n            portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n            #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )\n            {\n                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n            }\n            #else\n            {\n                /* The temporary usage of the core clock has served its purpose,\n                 * as described above.  Resume usage of the other clock. */\n                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\n\n                if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n                {\n                    /* The partial tick period already ended.  Be sure the SysTick\n                     * counts it only once. */\n                    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;\n                }\n\n                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n            }\n            #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */\n\n            /* Step the tick to account for any tick periods that elapsed. */\n            vTaskStepTick( ulCompleteTickPeriods );\n\n            /* Exit with interrupts enabled. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n        }\n    }\n\n#endif /* configUSE_TICKLESS_IDLE */\n/*-----------------------------------------------------------*/\n\n/*\n * Setup the systick timer to generate the tick interrupts at the required\n * frequency.\n */\n__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )\n{\n    /* Calculate the constants required to configure the tick interrupt. */\n    #if ( configUSE_TICKLESS_IDLE == 1 )\n    {\n        ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );\n        xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;\n        ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\n    }\n    #endif /* configUSE_TICKLESS_IDLE */\n\n    /* Stop and clear the SysTick. */\n    portNVIC_SYSTICK_CTRL_REG = 0UL;\n    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n    /* Configure SysTick to interrupt at the requested rate. */\n    portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\n    portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );\n}\n/*-----------------------------------------------------------*/\n\n#if ( configASSERT_DEFINED == 1 )\n\n    void vPortValidateInterruptPriority( void )\n    {\n        uint32_t ulCurrentInterrupt;\n        uint8_t ucCurrentPriority;\n\n        /* Obtain the number of the currently executing interrupt. */\n        __asm volatile ( \"mrs %0, ipsr\" : \"=r\" ( ulCurrentInterrupt )::\"memory\" );\n\n        /* Is the interrupt number a user defined interrupt? */\n        if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )\n        {\n            /* Look up the interrupt's priority. */\n            ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];\n\n            /* The following assertion will fail if a service routine (ISR) for\n             * an interrupt that has been assigned a priority above\n             * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\n             * function.  ISR safe FreeRTOS API functions must *only* be called\n             * from interrupts that have been assigned a priority at or below\n             * configMAX_SYSCALL_INTERRUPT_PRIORITY.\n             *\n             * Numerically low interrupt priority numbers represent logically high\n             * interrupt priorities, therefore the priority of the interrupt must\n             * be set to a value equal to or numerically *higher* than\n             * configMAX_SYSCALL_INTERRUPT_PRIORITY.\n             *\n             * Interrupts that\tuse the FreeRTOS API must not be left at their\n             * default priority of\tzero as that is the highest possible priority,\n             * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,\n             * and\ttherefore also guaranteed to be invalid.\n             *\n             * FreeRTOS maintains separate thread and ISR API functions to ensure\n             * interrupt entry is as fast and simple as possible.\n             *\n             * The following links provide detailed information:\n             * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html\n             * https://www.FreeRTOS.org/FAQHelp.html */\n            configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );\n        }\n\n        /* Priority grouping:  The interrupt controller (NVIC) allows the bits\n         * that define each interrupt's priority to be split between bits that\n         * define the interrupt's pre-emption priority bits and bits that define\n         * the interrupt's sub-priority.  For simplicity all bits must be defined\n         * to be pre-emption priority bits.  The following assertion will fail if\n         * this is not the case (if some bits represent a sub-priority).\n         *\n         * If the application only uses CMSIS libraries for interrupt\n         * configuration then the correct setting can be achieved on all Cortex-M\n         * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the\n         * scheduler.  Note however that some vendor specific peripheral libraries\n         * assume a non-zero priority group setting, in which cases using a value\n         * of zero will result in unpredictable behaviour. */\n        configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );\n    }\n\n#endif /* configASSERT_DEFINED */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM3/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n\n#ifndef PORTMACRO_H\n    #define PORTMACRO_H\n\n    #ifdef __cplusplus\n        extern \"C\" {\n    #endif\n\n/*-----------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the\n * given hardware and compiler.\n *\n * These settings should not be altered.\n *-----------------------------------------------------------\n */\n\n/* Type definitions. */\n    #define portCHAR          char\n    #define portFLOAT         float\n    #define portDOUBLE        double\n    #define portLONG          long\n    #define portSHORT         short\n    #define portSTACK_TYPE    uint32_t\n    #define portBASE_TYPE     long\n\n    typedef portSTACK_TYPE   StackType_t;\n    typedef long             BaseType_t;\n    typedef unsigned long    UBaseType_t;\n\n    #if ( configUSE_16_BIT_TICKS == 1 )\n        typedef uint16_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffff\n    #else\n        typedef uint32_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL\n\n/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\n * not need to be guarded with a critical section. */\n        #define portTICK_TYPE_IS_ATOMIC    1\n    #endif\n/*-----------------------------------------------------------*/\n\n/* Architecture specifics. */\n    #define portSTACK_GROWTH      ( -1 )\n    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\n    #define portBYTE_ALIGNMENT    8\n    #define portDONT_DISCARD      __attribute__( ( used ) )\n/*-----------------------------------------------------------*/\n\n/* Scheduler utilities. */\n    #define portYIELD()                                 \\\n    {                                                   \\\n        /* Set a PendSV to request a context switch. */ \\\n        portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \\\n                                                        \\\n        /* Barriers are normally not required but do ensure the code is completely \\\n         * within the specified behaviour for the architecture. */ \\\n        __asm volatile ( \"dsb\" ::: \"memory\" );                     \\\n        __asm volatile ( \"isb\" );                                  \\\n    }\n\n    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )\n    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )\n    #define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 )\n    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )\n/*-----------------------------------------------------------*/\n\n/* Critical section management. */\n    extern void vPortEnterCritical( void );\n    extern void vPortExitCritical( void );\n    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulPortRaiseBASEPRI()\n    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vPortSetBASEPRI( x )\n    #define portDISABLE_INTERRUPTS()                  vPortRaiseBASEPRI()\n    #define portENABLE_INTERRUPTS()                   vPortSetBASEPRI( 0 )\n    #define portENTER_CRITICAL()                      vPortEnterCritical()\n    #define portEXIT_CRITICAL()                       vPortExitCritical()\n\n/*-----------------------------------------------------------*/\n\n/* Task function macros as described on the FreeRTOS.org WEB site.  These are\n * not necessary for to use this port.  They are defined so the common demo files\n * (which build with all the ports) will build. */\n    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )\n    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )\n/*-----------------------------------------------------------*/\n\n/* Tickless idle/low power functionality. */\n    #ifndef portSUPPRESS_TICKS_AND_SLEEP\n        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );\n        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )\n    #endif\n/*-----------------------------------------------------------*/\n\n/* Architecture specific optimisations. */\n    #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION\n        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1\n    #endif\n\n    #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1\n\n/* Generic helper function. */\n        __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )\n        {\n            uint8_t ucReturn;\n\n            __asm volatile ( \"clz %0, %1\" : \"=r\" ( ucReturn ) : \"r\" ( ulBitmap ) : \"memory\" );\n\n            return ucReturn;\n        }\n\n/* Check the configuration. */\n        #if ( configMAX_PRIORITIES > 32 )\n            #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.\n        #endif\n\n/* Store/clear the ready priorities in a bit map. */\n        #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )\n        #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )\n\n/*-----------------------------------------------------------*/\n\n        #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )\n\n    #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */\n\n/*-----------------------------------------------------------*/\n\n    #ifdef configASSERT\n        void vPortValidateInterruptPriority( void );\n        #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()\n    #endif\n\n/* portNOP() is not required by this port. */\n    #define portNOP()\n\n    #define portINLINE              __inline\n\n    #ifndef portFORCE_INLINE\n        #define portFORCE_INLINE    inline __attribute__( ( always_inline ) )\n    #endif\n\n/*-----------------------------------------------------------*/\n\n    portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )\n    {\n        uint32_t ulCurrentInterrupt;\n        BaseType_t xReturn;\n\n        /* Obtain the number of the currently executing interrupt. */\n        __asm volatile ( \"mrs %0, ipsr\" : \"=r\" ( ulCurrentInterrupt )::\"memory\" );\n\n        if( ulCurrentInterrupt == 0 )\n        {\n            xReturn = pdFALSE;\n        }\n        else\n        {\n            xReturn = pdTRUE;\n        }\n\n        return xReturn;\n    }\n\n/*-----------------------------------------------------------*/\n\n    portFORCE_INLINE static void vPortRaiseBASEPRI( void )\n    {\n        uint32_t ulNewBASEPRI;\n\n        __asm volatile\n        (\n            \"\tmov %0, %1\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\\\n            \"\tmsr basepri, %0\t\t\t\t\t\t\t\t\t\t\t\\n\"\\\n            \"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\\\n            \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\\\n            : \"=r\" ( ulNewBASEPRI ) : \"i\" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : \"memory\"\n        );\n    }\n\n/*-----------------------------------------------------------*/\n\n    portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )\n    {\n        uint32_t ulOriginalBASEPRI, ulNewBASEPRI;\n\n        __asm volatile\n        (\n            \"\tmrs %0, basepri\t\t\t\t\t\t\t\t\t\t\t\\n\"\\\n            \"\tmov %1, %2\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\\\n            \"\tmsr basepri, %1\t\t\t\t\t\t\t\t\t\t\t\\n\"\\\n            \"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\\\n            \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\\\n            : \"=r\" ( ulOriginalBASEPRI ), \"=r\" ( ulNewBASEPRI ) : \"i\" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : \"memory\"\n        );\n\n        /* This return will not be reached but is necessary to prevent compiler\n         * warnings. */\n        return ulOriginalBASEPRI;\n    }\n/*-----------------------------------------------------------*/\n\n    portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )\n    {\n        __asm volatile\n        (\n            \"\tmsr basepri, %0\t\"::\"r\" ( ulNewMaskValue ) : \"memory\"\n        );\n    }\n/*-----------------------------------------------------------*/\n\n    #define portMEMORY_BARRIER()    __asm volatile ( \"\" ::: \"memory\" )\n\n    #ifdef __cplusplus\n        }\n    #endif\n\n#endif /* PORTMACRO_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM33/non_secure/port.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\n * all the API functions to use the MPU wrappers. That should only be done when\n * task.h is included from an application file. */\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n/* MPU wrappers includes. */\n#include \"mpu_wrappers.h\"\n\n/* Portasm includes. */\n#include \"portasm.h\"\n\n#if ( configENABLE_TRUSTZONE == 1 )\n    /* Secure components includes. */\n    #include \"secure_context.h\"\n    #include \"secure_init.h\"\n#endif /* configENABLE_TRUSTZONE */\n\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/**\n * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only\n * i.e. the processor boots as secure and never jumps to the non-secure side.\n * The Trust Zone support in the port must be disabled in order to run FreeRTOS\n * on the secure side. The following are the valid configuration seetings:\n *\n * 1. Run FreeRTOS on the Secure Side:\n *    configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0\n *\n * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:\n *    configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1\n *\n * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:\n *    configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0\n */\n#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )\n    #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.\n#endif\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the NVIC.\n */\n#define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )\n#define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )\n#define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )\n#define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )\n#define portNVIC_SYSTICK_ENABLE_BIT           ( 1UL << 0UL )\n#define portNVIC_SYSTICK_INT_BIT              ( 1UL << 1UL )\n#define portNVIC_SYSTICK_CLK_BIT              ( 1UL << 2UL )\n#define portNVIC_SYSTICK_COUNT_FLAG_BIT       ( 1UL << 16UL )\n#define portNVIC_PEND_SYSTICK_CLEAR_BIT       ( 1UL << 25UL )\n#define portNVIC_PEND_SYSTICK_SET_BIT         ( 1UL << 26UL )\n#define portMIN_INTERRUPT_PRIORITY            ( 255UL )\n#define portNVIC_PENDSV_PRI                   ( portMIN_INTERRUPT_PRIORITY << 16UL )\n#define portNVIC_SYSTICK_PRI                  ( portMIN_INTERRUPT_PRIORITY << 24UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the SCB.\n */\n#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( volatile uint32_t * ) 0xe000ed24 )\n#define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the FPU.\n */\n#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 )              /* Coprocessor Access Control Register. */\n#define portCPACR_CP10_VALUE    ( 3UL )\n#define portCPACR_CP11_VALUE    portCPACR_CP10_VALUE\n#define portCPACR_CP10_POS      ( 20UL )\n#define portCPACR_CP11_POS      ( 22UL )\n\n#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 )              /* Floating Point Context Control Register. */\n#define portFPCCR_ASPEN_POS     ( 31UL )\n#define portFPCCR_ASPEN_MASK    ( 1UL << portFPCCR_ASPEN_POS )\n#define portFPCCR_LSPEN_POS     ( 30UL )\n#define portFPCCR_LSPEN_MASK    ( 1UL << portFPCCR_LSPEN_POS )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the MPU.\n */\n#define portMPU_TYPE_REG                      ( *( ( volatile uint32_t * ) 0xe000ed90 ) )\n#define portMPU_CTRL_REG                      ( *( ( volatile uint32_t * ) 0xe000ed94 ) )\n#define portMPU_RNR_REG                       ( *( ( volatile uint32_t * ) 0xe000ed98 ) )\n\n#define portMPU_RBAR_REG                      ( *( ( volatile uint32_t * ) 0xe000ed9c ) )\n#define portMPU_RLAR_REG                      ( *( ( volatile uint32_t * ) 0xe000eda0 ) )\n\n#define portMPU_RBAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda4 ) )\n#define portMPU_RLAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda8 ) )\n\n#define portMPU_RBAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edac ) )\n#define portMPU_RLAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edb0 ) )\n\n#define portMPU_RBAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb4 ) )\n#define portMPU_RLAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb8 ) )\n\n#define portMPU_MAIR0_REG                     ( *( ( volatile uint32_t * ) 0xe000edc0 ) )\n#define portMPU_MAIR1_REG                     ( *( ( volatile uint32_t * ) 0xe000edc4 ) )\n\n#define portMPU_RBAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */\n#define portMPU_RLAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */\n\n#define portMPU_MAIR_ATTR0_POS                ( 0UL )\n#define portMPU_MAIR_ATTR0_MASK               ( 0x000000ff )\n\n#define portMPU_MAIR_ATTR1_POS                ( 8UL )\n#define portMPU_MAIR_ATTR1_MASK               ( 0x0000ff00 )\n\n#define portMPU_MAIR_ATTR2_POS                ( 16UL )\n#define portMPU_MAIR_ATTR2_MASK               ( 0x00ff0000 )\n\n#define portMPU_MAIR_ATTR3_POS                ( 24UL )\n#define portMPU_MAIR_ATTR3_MASK               ( 0xff000000 )\n\n#define portMPU_MAIR_ATTR4_POS                ( 0UL )\n#define portMPU_MAIR_ATTR4_MASK               ( 0x000000ff )\n\n#define portMPU_MAIR_ATTR5_POS                ( 8UL )\n#define portMPU_MAIR_ATTR5_MASK               ( 0x0000ff00 )\n\n#define portMPU_MAIR_ATTR6_POS                ( 16UL )\n#define portMPU_MAIR_ATTR6_MASK               ( 0x00ff0000 )\n\n#define portMPU_MAIR_ATTR7_POS                ( 24UL )\n#define portMPU_MAIR_ATTR7_MASK               ( 0xff000000 )\n\n#define portMPU_RLAR_ATTR_INDEX0              ( 0UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX1              ( 1UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX2              ( 2UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX3              ( 3UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX4              ( 4UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX5              ( 5UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX6              ( 6UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX7              ( 7UL << 1UL )\n\n#define portMPU_RLAR_REGION_ENABLE            ( 1UL )\n\n/* Enable privileged access to unmapped region. */\n#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )\n\n/* Enable MPU. */\n#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )\n\n/* Expected value of the portMPU_TYPE register. */\n#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief The maximum 24-bit number.\n *\n * It is needed because the systick is a 24-bit counter.\n */\n#define portMAX_24_BIT_NUMBER       ( 0xffffffUL )\n\n/**\n * @brief A fiddle factor to estimate the number of SysTick counts that would\n * have occurred while the SysTick counter is stopped during tickless idle\n * calculations.\n */\n#define portMISSED_COUNTS_FACTOR    ( 94UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to set up the initial stack.\n */\n#define portINITIAL_XPSR    ( 0x01000000 )\n\n#if ( configRUN_FREERTOS_SECURE_ONLY == 1 )\n\n/**\n * @brief Initial EXC_RETURN value.\n *\n *     FF         FF         FF         FD\n * 1111 1111  1111 1111  1111 1111  1111 1101\n *\n * Bit[6] - 1 --> The exception was taken from the Secure state.\n * Bit[5] - 1 --> Do not skip stacking of additional state context.\n * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\n * Bit[3] - 1 --> Return to the Thread mode.\n * Bit[2] - 1 --> Restore registers from the process stack.\n * Bit[1] - 0 --> Reserved, 0.\n * Bit[0] - 1 --> The exception was taken to the Secure state.\n */\n    #define portINITIAL_EXC_RETURN    ( 0xfffffffd )\n#else\n\n/**\n * @brief Initial EXC_RETURN value.\n *\n *     FF         FF         FF         BC\n * 1111 1111  1111 1111  1111 1111  1011 1100\n *\n * Bit[6] - 0 --> The exception was taken from the Non-Secure state.\n * Bit[5] - 1 --> Do not skip stacking of additional state context.\n * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\n * Bit[3] - 1 --> Return to the Thread mode.\n * Bit[2] - 1 --> Restore registers from the process stack.\n * Bit[1] - 0 --> Reserved, 0.\n * Bit[0] - 0 --> The exception was taken to the Non-Secure state.\n */\n    #define portINITIAL_EXC_RETURN    ( 0xffffffbc )\n#endif /* configRUN_FREERTOS_SECURE_ONLY */\n\n/**\n * @brief CONTROL register privileged bit mask.\n *\n * Bit[0] in CONTROL register tells the privilege:\n *  Bit[0] = 0 ==> The task is privileged.\n *  Bit[0] = 1 ==> The task is not privileged.\n */\n#define portCONTROL_PRIVILEGED_MASK         ( 1UL << 0UL )\n\n/**\n * @brief Initial CONTROL register values.\n */\n#define portINITIAL_CONTROL_UNPRIVILEGED    ( 0x3 )\n#define portINITIAL_CONTROL_PRIVILEGED      ( 0x2 )\n\n/**\n * @brief Let the user override the default SysTick clock rate.  If defined by the\n * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the\n * configuration register.\n */\n#ifndef configSYSTICK_CLOCK_HZ\n    #define configSYSTICK_CLOCK_HZ             ( configCPU_CLOCK_HZ )\n    /* Ensure the SysTick is clocked at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( portNVIC_SYSTICK_CLK_BIT )\n#else\n    /* Select the option to clock SysTick not at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( 0 )\n#endif\n\n/**\n * @brief Let the user override the pre-loading of the initial LR with the\n * address of prvTaskExitError() in case it messes up unwinding of the stack\n * in the debugger.\n */\n#ifdef configTASK_RETURN_ADDRESS\n    #define portTASK_RETURN_ADDRESS    configTASK_RETURN_ADDRESS\n#else\n    #define portTASK_RETURN_ADDRESS    prvTaskExitError\n#endif\n\n/**\n * @brief If portPRELOAD_REGISTERS then registers will be given an initial value\n * when a task is created. This helps in debugging at the cost of code size.\n */\n#define portPRELOAD_REGISTERS    1\n\n/**\n * @brief A task is created without a secure context, and must call\n * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes\n * any secure calls.\n */\n#define portNO_SECURE_CONTEXT    0\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Used to catch tasks that attempt to return from their implementing\n * function.\n */\nstatic void prvTaskExitError( void );\n\n#if ( configENABLE_MPU == 1 )\n\n/**\n * @brief Setup the Memory Protection Unit (MPU).\n */\n    static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\n#endif /* configENABLE_MPU */\n\n#if ( configENABLE_FPU == 1 )\n\n/**\n * @brief Setup the Floating Point Unit (FPU).\n */\n    static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;\n#endif /* configENABLE_FPU */\n\n/**\n * @brief Setup the timer to generate the tick interrupts.\n *\n * The implementation in this file is weak to allow application writers to\n * change the timer used to generate the tick interrupt.\n */\nvoid vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Checks whether the current execution context is interrupt.\n *\n * @return pdTRUE if the current execution context is interrupt, pdFALSE\n * otherwise.\n */\nBaseType_t xPortIsInsideInterrupt( void );\n\n/**\n * @brief Yield the processor.\n */\nvoid vPortYield( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Enter critical section.\n */\nvoid vPortEnterCritical( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Exit from critical section.\n */\nvoid vPortExitCritical( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief SysTick handler.\n */\nvoid SysTick_Handler( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief C part of SVC handler.\n */\nportDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION;\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Each task maintains its own interrupt status in the critical nesting\n * variable.\n */\nPRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;\n\n#if ( configENABLE_TRUSTZONE == 1 )\n\n/**\n * @brief Saved as part of the task context to indicate which context the\n * task is using on the secure side.\n */\n    PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;\n#endif /* configENABLE_TRUSTZONE */\n\n#if ( configUSE_TICKLESS_IDLE == 1 )\n\n/**\n * @brief The number of SysTick increments that make up one tick period.\n */\n    PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0;\n\n/**\n * @brief The maximum number of tick periods that can be suppressed is\n * limited by the 24 bit resolution of the SysTick timer.\n */\n    PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0;\n\n/**\n * @brief Compensate for the CPU cycles that pass while the SysTick is\n * stopped (low power functionality only).\n */\n    PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TICKLESS_IDLE == 1 )\n    __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )\n    {\n        uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;\n        TickType_t xModifiableIdleTime;\n\n        /* Make sure the SysTick reload value does not overflow the counter. */\n        if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\n        {\n            xExpectedIdleTime = xMaximumPossibleSuppressedTicks;\n        }\n\n        /* Enter a critical section but don't use the taskENTER_CRITICAL()\n         * method as that will mask interrupts that should exit sleep mode. */\n        __asm volatile ( \"cpsid i\" ::: \"memory\" );\n        __asm volatile ( \"dsb\" );\n        __asm volatile ( \"isb\" );\n\n        /* If a context switch is pending or a task is waiting for the scheduler\n         * to be unsuspended then abandon the low power entry. */\n        if( eTaskConfirmSleepModeStatus() == eAbortSleep )\n        {\n            /* Re-enable interrupts - see comments above the cpsid instruction\n             * above. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n        }\n        else\n        {\n            /* Stop the SysTick momentarily.  The time the SysTick is stopped for\n             * is accounted for as best it can be, but using the tickless mode will\n             * inevitably result in some tiny drift of the time maintained by the\n             * kernel with respect to calendar time. */\n            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );\n\n            /* Use the SysTick current-value register to determine the number of\n             * SysTick decrements remaining until the next tick interrupt.  If the\n             * current-value register is zero, then there are actually\n             * ulTimerCountsForOneTick decrements remaining, not zero, because the\n             * SysTick requests the interrupt when decrementing from 1 to 0. */\n            ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n\n            if( ulSysTickDecrementsLeft == 0 )\n            {\n                ulSysTickDecrementsLeft = ulTimerCountsForOneTick;\n            }\n\n            /* Calculate the reload value required to wait xExpectedIdleTime\n             * tick periods.  -1 is used because this code normally executes part\n             * way through the first tick period.  But if the SysTick IRQ is now\n             * pending, then clear the IRQ, suppressing the first tick, and correct\n             * the reload value to reflect that the second tick period is already\n             * underway.  The expected idle time is always at least two ticks. */\n            ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );\n\n            if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )\n            {\n                portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;\n                ulReloadValue -= ulTimerCountsForOneTick;\n            }\n\n            if( ulReloadValue > ulStoppedTimerCompensation )\n            {\n                ulReloadValue -= ulStoppedTimerCompensation;\n            }\n\n            /* Set the new reload value. */\n            portNVIC_SYSTICK_LOAD_REG = ulReloadValue;\n\n            /* Clear the SysTick count flag and set the count value back to\n             * zero. */\n            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n            /* Restart SysTick. */\n            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\n\n            /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can\n             * set its parameter to 0 to indicate that its implementation contains\n             * its own wait for interrupt or wait for event instruction, and so wfi\n             * should not be executed again.  However, the original expected idle\n             * time variable must remain unmodified, so a copy is taken. */\n            xModifiableIdleTime = xExpectedIdleTime;\n            configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\n\n            if( xModifiableIdleTime > 0 )\n            {\n                __asm volatile ( \"dsb\" ::: \"memory\" );\n                __asm volatile ( \"wfi\" );\n                __asm volatile ( \"isb\" );\n            }\n\n            configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\n\n            /* Re-enable interrupts to allow the interrupt that brought the MCU\n             * out of sleep mode to execute immediately.  See comments above\n             * the cpsid instruction above. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n            __asm volatile ( \"dsb\" );\n            __asm volatile ( \"isb\" );\n\n            /* Disable interrupts again because the clock is about to be stopped\n             * and interrupts that execute while the clock is stopped will increase\n             * any slippage between the time maintained by the RTOS and calendar\n             * time. */\n            __asm volatile ( \"cpsid i\" ::: \"memory\" );\n            __asm volatile ( \"dsb\" );\n            __asm volatile ( \"isb\" );\n\n            /* Disable the SysTick clock without reading the\n             * portNVIC_SYSTICK_CTRL_REG register to ensure the\n             * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,\n             * the time the SysTick is stopped for is accounted for as best it can\n             * be, but using the tickless mode will inevitably result in some tiny\n             * drift of the time maintained by the kernel with respect to calendar\n             * time*/\n            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );\n\n            /* Determine whether the SysTick has already counted to zero. */\n            if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n            {\n                uint32_t ulCalculatedLoadValue;\n\n                /* The tick interrupt ended the sleep (or is now pending), and\n                 * a new tick period has started.  Reset portNVIC_SYSTICK_LOAD_REG\n                 * with whatever remains of the new tick period. */\n                ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\n\n                /* Don't allow a tiny value, or values that have somehow\n                 * underflowed because the post sleep hook did something\n                 * that took too long or because the SysTick current-value register\n                 * is zero. */\n                if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )\n                {\n                    ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );\n                }\n\n                portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;\n\n                /* As the pending tick will be processed as soon as this\n                 * function exits, the tick value maintained by the tick is stepped\n                 * forward by one less than the time spent waiting. */\n                ulCompleteTickPeriods = xExpectedIdleTime - 1UL;\n            }\n            else\n            {\n                /* Something other than the tick interrupt ended the sleep. */\n\n                /* Use the SysTick current-value register to determine the\n                 * number of SysTick decrements remaining until the expected idle\n                 * time would have ended. */\n                ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n                #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )\n                {\n                    /* If the SysTick is not using the core clock, the current-\n                     * value register might still be zero here.  In that case, the\n                     * SysTick didn't load from the reload register, and there are\n                     * ulReloadValue decrements remaining in the expected idle\n                     * time, not zero. */\n                    if( ulSysTickDecrementsLeft == 0 )\n                    {\n                        ulSysTickDecrementsLeft = ulReloadValue;\n                    }\n                }\n                #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */\n\n                /* Work out how long the sleep lasted rounded to complete tick\n                 * periods (not the ulReload value which accounted for part\n                 * ticks). */\n                ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;\n\n                /* How many complete tick periods passed while the processor\n                 * was waiting? */\n                ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;\n\n                /* The reload value is set to whatever fraction of a single tick\n                 * period remains. */\n                portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;\n            }\n\n            /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,\n             * then set portNVIC_SYSTICK_LOAD_REG back to its standard value.  If\n             * the SysTick is not using the core clock, temporarily configure it to\n             * use the core clock.  This configuration forces the SysTick to load\n             * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next\n             * cycle of the other clock.  Then portNVIC_SYSTICK_LOAD_REG is ready\n             * to receive the standard value immediately. */\n            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n            portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n            #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )\n            {\n                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n            }\n            #else\n            {\n                /* The temporary usage of the core clock has served its purpose,\n                 * as described above.  Resume usage of the other clock. */\n                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\n\n                if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n                {\n                    /* The partial tick period already ended.  Be sure the SysTick\n                     * counts it only once. */\n                    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;\n                }\n\n                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n            }\n            #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */\n\n            /* Step the tick to account for any tick periods that elapsed. */\n            vTaskStepTick( ulCompleteTickPeriods );\n\n            /* Exit with interrupts enabled. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n        }\n    }\n#endif /* configUSE_TICKLESS_IDLE */\n/*-----------------------------------------------------------*/\n\n__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Calculate the constants required to configure the tick interrupt. */\n    #if ( configUSE_TICKLESS_IDLE == 1 )\n    {\n        ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );\n        xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;\n        ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\n    }\n    #endif /* configUSE_TICKLESS_IDLE */\n\n    /* Stop and reset the SysTick. */\n    portNVIC_SYSTICK_CTRL_REG = 0UL;\n    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n    /* Configure SysTick to interrupt at the requested rate. */\n    portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\n    portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvTaskExitError( void )\n{\n    volatile uint32_t ulDummy = 0UL;\n\n    /* A function that implements a task must not exit or attempt to return to\n     * its caller as there is nothing to return to. If a task wants to exit it\n     * should instead call vTaskDelete( NULL ). Artificially force an assert()\n     * to be triggered if configASSERT() is defined, then stop here so\n     * application writers can catch the error. */\n    configASSERT( ulCriticalNesting == ~0UL );\n    portDISABLE_INTERRUPTS();\n\n    while( ulDummy == 0 )\n    {\n        /* This file calls prvTaskExitError() after the scheduler has been\n         * started to remove a compiler warning about the function being\n         * defined but never called.  ulDummy is used purely to quieten other\n         * warnings about code appearing after this function is called - making\n         * ulDummy volatile makes the compiler think the function could return\n         * and therefore not output an 'unreachable code' warning for code that\n         * appears after it. */\n    }\n}\n/*-----------------------------------------------------------*/\n\n#if ( configENABLE_MPU == 1 )\n    static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */\n    {\n        #if defined( __ARMCC_VERSION )\n\n            /* Declaration when these variable are defined in code instead of being\n             * exported from linker scripts. */\n            extern uint32_t * __privileged_functions_start__;\n            extern uint32_t * __privileged_functions_end__;\n            extern uint32_t * __syscalls_flash_start__;\n            extern uint32_t * __syscalls_flash_end__;\n            extern uint32_t * __unprivileged_flash_start__;\n            extern uint32_t * __unprivileged_flash_end__;\n            extern uint32_t * __privileged_sram_start__;\n            extern uint32_t * __privileged_sram_end__;\n        #else /* if defined( __ARMCC_VERSION ) */\n            /* Declaration when these variable are exported from linker scripts. */\n            extern uint32_t __privileged_functions_start__[];\n            extern uint32_t __privileged_functions_end__[];\n            extern uint32_t __syscalls_flash_start__[];\n            extern uint32_t __syscalls_flash_end__[];\n            extern uint32_t __unprivileged_flash_start__[];\n            extern uint32_t __unprivileged_flash_end__[];\n            extern uint32_t __privileged_sram_start__[];\n            extern uint32_t __privileged_sram_end__[];\n        #endif /* defined( __ARMCC_VERSION ) */\n\n        /* The only permitted number of regions are 8 or 16. */\n        configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );\n\n        /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */\n        configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );\n\n        /* Check that the MPU is present. */\n        if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )\n        {\n            /* MAIR0 - Index 0. */\n            portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\n            /* MAIR0 - Index 1. */\n            portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\n\n            /* Setup privileged flash as Read Only so that privileged tasks can\n             * read it but not modify. */\n            portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_PRIVILEGED_READ_ONLY );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Setup unprivileged flash as Read Only by both privileged and\n             * unprivileged tasks. All tasks can read it but no-one can modify. */\n            portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_READ_ONLY );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Setup unprivileged syscalls flash as Read Only by both privileged\n             * and unprivileged tasks. All tasks can read it but no-one can modify. */\n            portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_READ_ONLY );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Setup RAM containing kernel data for privileged access only. */\n            portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\n                               ( portMPU_REGION_EXECUTE_NEVER );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Enable mem fault. */\n            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;\n\n            /* Enable MPU with privileged background access i.e. unmapped\n             * regions have privileged access. */\n            portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );\n        }\n    }\n#endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\n#if ( configENABLE_FPU == 1 )\n    static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */\n    {\n        #if ( configENABLE_TRUSTZONE == 1 )\n        {\n            /* Enable non-secure access to the FPU. */\n            SecureInit_EnableNSFPUAccess();\n        }\n        #endif /* configENABLE_TRUSTZONE */\n\n        /* CP10 = 11 ==> Full access to FPU i.e. both privileged and\n         * unprivileged code should be able to access FPU. CP11 should be\n         * programmed to the same value as CP10. */\n        *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |\n                            ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )\n                            );\n\n        /* ASPEN = 1 ==> Hardware should automatically preserve floating point\n         * context on exception entry and restore on exception return.\n         * LSPEN = 1 ==> Enable lazy context save of FP state. */\n        *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );\n    }\n#endif /* configENABLE_FPU */\n/*-----------------------------------------------------------*/\n\nvoid vPortYield( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Set a PendSV to request a context switch. */\n    portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\n\n    /* Barriers are normally not required but do ensure the code is\n     * completely within the specified behaviour for the architecture. */\n    __asm volatile ( \"dsb\" ::: \"memory\" );\n    __asm volatile ( \"isb\" );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */\n{\n    portDISABLE_INTERRUPTS();\n    ulCriticalNesting++;\n\n    /* Barriers are normally not required but do ensure the code is\n     * completely within the specified behaviour for the architecture. */\n    __asm volatile ( \"dsb\" ::: \"memory\" );\n    __asm volatile ( \"isb\" );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */\n{\n    configASSERT( ulCriticalNesting );\n    ulCriticalNesting--;\n\n    if( ulCriticalNesting == 0 )\n    {\n        portENABLE_INTERRUPTS();\n    }\n}\n/*-----------------------------------------------------------*/\n\nvoid SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */\n{\n    uint32_t ulPreviousMask;\n\n    ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();\n    {\n        /* Increment the RTOS tick. */\n        if( xTaskIncrementTick() != pdFALSE )\n        {\n            /* Pend a context switch. */\n            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\n        }\n    }\n    portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */\n{\n    #if ( configENABLE_MPU == 1 )\n        #if defined( __ARMCC_VERSION )\n\n            /* Declaration when these variable are defined in code instead of being\n             * exported from linker scripts. */\n            extern uint32_t * __syscalls_flash_start__;\n            extern uint32_t * __syscalls_flash_end__;\n        #else\n            /* Declaration when these variable are exported from linker scripts. */\n            extern uint32_t __syscalls_flash_start__[];\n            extern uint32_t __syscalls_flash_end__[];\n        #endif /* defined( __ARMCC_VERSION ) */\n    #endif /* configENABLE_MPU */\n\n    uint32_t ulPC;\n\n    #if ( configENABLE_TRUSTZONE == 1 )\n        uint32_t ulR0, ulR1;\n        extern TaskHandle_t pxCurrentTCB;\n        #if ( configENABLE_MPU == 1 )\n            uint32_t ulControl, ulIsTaskPrivileged;\n        #endif /* configENABLE_MPU */\n    #endif /* configENABLE_TRUSTZONE */\n    uint8_t ucSVCNumber;\n\n    /* Register are stored on the stack in the following order - R0, R1, R2, R3,\n     * R12, LR, PC, xPSR. */\n    ulPC = pulCallerStackAddress[ 6 ];\n    ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];\n\n    switch( ucSVCNumber )\n    {\n        #if ( configENABLE_TRUSTZONE == 1 )\n            case portSVC_ALLOCATE_SECURE_CONTEXT:\n\n                /* R0 contains the stack size passed as parameter to the\n                 * vPortAllocateSecureContext function. */\n                ulR0 = pulCallerStackAddress[ 0 ];\n\n                #if ( configENABLE_MPU == 1 )\n                {\n                    /* Read the CONTROL register value. */\n                    __asm volatile ( \"mrs %0, control\"  : \"=r\" ( ulControl ) );\n\n                    /* The task that raised the SVC is privileged if Bit[0]\n                     * in the CONTROL register is 0. */\n                    ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );\n\n                    /* Allocate and load a context for the secure task. */\n                    xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );\n                }\n                #else /* if ( configENABLE_MPU == 1 ) */\n                {\n                    /* Allocate and load a context for the secure task. */\n                    xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );\n                }\n                #endif /* configENABLE_MPU */\n\n                configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );\n                SecureContext_LoadContext( xSecureContext, pxCurrentTCB );\n                break;\n\n            case portSVC_FREE_SECURE_CONTEXT:\n\n                /* R0 contains TCB being freed and R1 contains the secure\n                 * context handle to be freed. */\n                ulR0 = pulCallerStackAddress[ 0 ];\n                ulR1 = pulCallerStackAddress[ 1 ];\n\n                /* Free the secure context. */\n                SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );\n                break;\n        #endif /* configENABLE_TRUSTZONE */\n\n        case portSVC_START_SCHEDULER:\n            #if ( configENABLE_TRUSTZONE == 1 )\n            {\n                /* De-prioritize the non-secure exceptions so that the\n                 * non-secure pendSV runs at the lowest priority. */\n                SecureInit_DePrioritizeNSExceptions();\n\n                /* Initialize the secure context management system. */\n                SecureContext_Init();\n            }\n            #endif /* configENABLE_TRUSTZONE */\n\n            #if ( configENABLE_FPU == 1 )\n            {\n                /* Setup the Floating Point Unit (FPU). */\n                prvSetupFPU();\n            }\n            #endif /* configENABLE_FPU */\n\n            /* Setup the context of the first task so that the first task starts\n             * executing. */\n            vRestoreContextOfFirstTask();\n            break;\n\n            #if ( configENABLE_MPU == 1 )\n                case portSVC_RAISE_PRIVILEGE:\n\n                    /* Only raise the privilege, if the svc was raised from any of\n                     * the system calls. */\n                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&\n                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )\n                    {\n                        vRaisePrivilege();\n                    }\n                    break;\n            #endif /* configENABLE_MPU */\n\n        default:\n            /* Incorrect SVC call. */\n            configASSERT( pdFALSE );\n    }\n}\n/*-----------------------------------------------------------*/\n/* *INDENT-OFF* */\n#if ( configENABLE_MPU == 1 )\n    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,\n                                         StackType_t * pxEndOfStack,\n                                         TaskFunction_t pxCode,\n                                         void * pvParameters,\n                                         BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */\n#else\n    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,\n                                         StackType_t * pxEndOfStack,\n                                         TaskFunction_t pxCode,\n                                         void * pvParameters ) /* PRIVILEGED_FUNCTION */\n#endif /* configENABLE_MPU */\n/* *INDENT-ON* */\n{\n    /* Simulate the stack frame as it would be created by a context switch\n     * interrupt. */\n    #if ( portPRELOAD_REGISTERS == 0 )\n    {\n        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\n        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\n        pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */\n        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */\n        pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */\n        *pxTopOfStack = portINITIAL_EXC_RETURN;\n\n        #if ( configENABLE_MPU == 1 )\n        {\n            pxTopOfStack--;\n\n            if( xRunPrivileged == pdTRUE )\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n            else\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n        }\n        #endif /* configENABLE_MPU */\n\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\n\n        #if ( configENABLE_TRUSTZONE == 1 )\n        {\n            pxTopOfStack--;\n            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\n        }\n        #endif /* configENABLE_TRUSTZONE */\n    }\n    #else /* portPRELOAD_REGISTERS */\n    {\n        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\n        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04 */\n        pxTopOfStack--;\n        *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN */\n\n        #if ( configENABLE_MPU == 1 )\n        {\n            pxTopOfStack--;\n\n            if( xRunPrivileged == pdTRUE )\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n            else\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n        }\n        #endif /* configENABLE_MPU */\n\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\n\n        #if ( configENABLE_TRUSTZONE == 1 )\n        {\n            pxTopOfStack--;\n            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\n        }\n        #endif /* configENABLE_TRUSTZONE */\n    }\n    #endif /* portPRELOAD_REGISTERS */\n\n    return pxTopOfStack;\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Make PendSV, CallSV and SysTick the same priority as the kernel. */\n    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;\n    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;\n\n    #if ( configENABLE_MPU == 1 )\n    {\n        /* Setup the Memory Protection Unit (MPU). */\n        prvSetupMPU();\n    }\n    #endif /* configENABLE_MPU */\n\n    /* Start the timer that generates the tick ISR. Interrupts are disabled\n     * here already. */\n    vPortSetupTimerInterrupt();\n\n    /* Initialize the critical nesting count ready for the first task. */\n    ulCriticalNesting = 0;\n\n    /* Start the first task. */\n    vStartFirstTask();\n\n    /* Should never get here as the tasks will now be executing. Call the task\n     * exit error function to prevent compiler warnings about a static function\n     * not being called in the case that the application writer overrides this\n     * functionality by defining configTASK_RETURN_ADDRESS. Call\n     * vTaskSwitchContext() so link time optimization does not remove the\n     * symbol. */\n    vTaskSwitchContext();\n    prvTaskExitError();\n\n    /* Should not get here. */\n    return 0;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Not implemented in ports where there is nothing to return to.\n     * Artificially force an assert. */\n    configASSERT( ulCriticalNesting == 1000UL );\n}\n/*-----------------------------------------------------------*/\n\n#if ( configENABLE_MPU == 1 )\n    void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,\n                                    const struct xMEMORY_REGION * const xRegions,\n                                    StackType_t * pxBottomOfStack,\n                                    uint32_t ulStackDepth )\n    {\n        uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;\n        int32_t lIndex = 0;\n\n        #if defined( __ARMCC_VERSION )\n\n            /* Declaration when these variable are defined in code instead of being\n             * exported from linker scripts. */\n            extern uint32_t * __privileged_sram_start__;\n            extern uint32_t * __privileged_sram_end__;\n        #else\n            /* Declaration when these variable are exported from linker scripts. */\n            extern uint32_t __privileged_sram_start__[];\n            extern uint32_t __privileged_sram_end__[];\n        #endif /* defined( __ARMCC_VERSION ) */\n\n        /* Setup MAIR0. */\n        xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\n        xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\n\n        /* This function is called automatically when the task is created - in\n         * which case the stack region parameters will be valid.  At all other\n         * times the stack parameters will not be valid and it is assumed that\n         * the stack region has already been configured. */\n        if( ulStackDepth > 0 )\n        {\n            ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;\n            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;\n\n            /* If the stack is within the privileged SRAM, do not protect it\n             * using a separate MPU region. This is needed because privileged\n             * SRAM is already protected using an MPU region and ARMv8-M does\n             * not allow overlapping MPU regions. */\n            if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) &&\n                ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) )\n            {\n                xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0;\n                xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0;\n            }\n            else\n            {\n                /* Define the region that allows access to the stack. */\n                ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK;\n                ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\n\n                xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |\n                                                             ( portMPU_REGION_NON_SHAREABLE ) |\n                                                             ( portMPU_REGION_READ_WRITE ) |\n                                                             ( portMPU_REGION_EXECUTE_NEVER );\n\n                xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) |\n                                                             ( portMPU_RLAR_ATTR_INDEX0 ) |\n                                                             ( portMPU_RLAR_REGION_ENABLE );\n            }\n        }\n\n        /* User supplied configurable regions. */\n        for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )\n        {\n            /* If xRegions is NULL i.e. the task has not specified any MPU\n             * region, the else part ensures that all the configurable MPU\n             * regions are invalidated. */\n            if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )\n            {\n                /* Translate the generic region definition contained in xRegions\n                 * into the ARMv8 specific MPU settings that are then stored in\n                 * xMPUSettings. */\n                ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;\n                ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;\n                ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\n\n                /* Start address. */\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |\n                                                                          ( portMPU_REGION_NON_SHAREABLE );\n\n                /* RO/RW. */\n                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )\n                {\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );\n                }\n                else\n                {\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );\n                }\n\n                /* XN. */\n                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )\n                {\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );\n                }\n\n                /* End Address. */\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |\n                                                                          ( portMPU_RLAR_REGION_ENABLE );\n\n                /* Normal memory/ Device memory. */\n                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )\n                {\n                    /* Attr1 in MAIR0 is configured as device memory. */\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;\n                }\n                else\n                {\n                    /* Attr0 in MAIR0 is configured as normal memory. */\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;\n                }\n            }\n            else\n            {\n                /* Invalidate the region. */\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;\n            }\n\n            lIndex++;\n        }\n    }\n#endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\nBaseType_t xPortIsInsideInterrupt( void )\n{\n    uint32_t ulCurrentInterrupt;\n    BaseType_t xReturn;\n\n    /* Obtain the number of the currently executing interrupt. Interrupt Program\n     * Status Register (IPSR) holds the exception number of the currently-executing\n     * exception or zero for Thread mode.*/\n    __asm volatile ( \"mrs %0, ipsr\" : \"=r\" ( ulCurrentInterrupt )::\"memory\" );\n\n    if( ulCurrentInterrupt == 0 )\n    {\n        xReturn = pdFALSE;\n    }\n    else\n    {\n        xReturn = pdTRUE;\n    }\n\n    return xReturn;\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM33/non_secure/portasm.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Standard includes. */\n#include <stdint.h>\n\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION\n * is defined correctly and privileged functions are placed in correct sections. */\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/* Portasm includes. */\n#include \"portasm.h\"\n\n/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the\n * header files. */\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\nvoid vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr  r2, pxCurrentTCBConst2\t\t\t\t\t\t\\n\"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n        \"\tldr  r3, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Read pxCurrentTCB. */\n        \"\tldr  r0, [r3]\t\t\t\t\t\t\t\t\t\\n\"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"\tdmb\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Complete outstanding transfers before disabling MPU. */\n            \"\tldr r2, xMPUCTRLConst2\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n            \"\tldr r4, [r2]\t\t\t\t\t\t\t\t\\n\"/* Read the value of MPU_CTRL. */\n            \"\tbic r4, #1\t\t\t\t\t\t\t\t\t\\n\"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\n            \"\tstr r4, [r2]\t\t\t\t\t\t\t\t\\n\"/* Disable MPU. */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tadds r3, #4\t\t\t\t\t\t\t\t\t\\n\"/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\n            \"\tldr  r4, [r3]\t\t\t\t\t\t\t\t\\n\"/* r4 = *r3 i.e. r4 = MAIR0. */\n            \"\tldr  r2, xMAIR0Const2\t\t\t\t\t\t\\n\"/* r2 = 0xe000edc0 [Location of MAIR0]. */\n            \"\tstr  r4, [r2]\t\t\t\t\t\t\t\t\\n\"/* Program MAIR0. */\n            \"\tldr  r2, xRNRConst2\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed98 [Location of RNR]. */\n            \"\tmovs r4, #4\t\t\t\t\t\t\t\t\t\\n\"/* r4 = 4. */\n            \"\tstr  r4, [r2]\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 4. */\n            \"\tadds r3, #4\t\t\t\t\t\t\t\t\t\\n\"/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */\n            \"\tldr  r2, xRBARConst2\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed9c [Location of RBAR]. */\n            \"\tldmia r3!, {r4-r11}\t\t\t\t\t\t\t\\n\"/* Read 4 set of RBAR/RLAR registers from TCB. */\n            \"\tstmia r2!, {r4-r11}\t\t\t\t\t\t\t\\n\"/* Write 4 set of RBAR/RLAR registers using alias registers. */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configTOTAL_MPU_REGIONS == 16 )\n            \"\tldr  r2, xRNRConst2\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed98 [Location of RNR]. */\n            \"\tmovs r4, #8\t\t\t\t\t\t\t\t\t\\n\"/* r4 = 8. */\n            \"\tstr  r4, [r2]\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 8. */\n            \"\tldr  r2, xRBARConst2\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed9c [Location of RBAR]. */\n            \"\tldmia r3!, {r4-r11}\t\t\t\t\t\t\t\\n\"/* Read 4 set of RBAR/RLAR registers from TCB. */\n            \"\tstmia r2!, {r4-r11}\t\t\t\t\t\t\t\\n\"/* Write 4 set of RBAR/RLAR registers using alias registers. */\n            \"\tldr  r2, xRNRConst2\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed98 [Location of RNR]. */\n            \"\tmovs r4, #12\t\t\t\t\t\t\t\t\\n\"/* r4 = 12. */\n            \"\tstr  r4, [r2]\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 12. */\n            \"\tldr  r2, xRBARConst2\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed9c [Location of RBAR]. */\n            \"\tldmia r3!, {r4-r11}\t\t\t\t\t\t\t\\n\"/* Read 4 set of RBAR/RLAR registers from TCB. */\n            \"\tstmia r2!, {r4-r11}\t\t\t\t\t\t\t\\n\"/* Write 4 set of RBAR/RLAR registers using alias registers. */\n        #endif /* configTOTAL_MPU_REGIONS == 16 */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tldr r2, xMPUCTRLConst2\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n            \"\tldr r4, [r2]\t\t\t\t\t\t\t\t\\n\"/* Read the value of MPU_CTRL. */\n            \"\torr r4, #1\t\t\t\t\t\t\t\t\t\\n\"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\n            \"\tstr r4, [r2]\t\t\t\t\t\t\t\t\\n\"/* Enable MPU. */\n            \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Force memory writes before continuing. */\n        #endif /* configENABLE_MPU */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"\tldm  r0!, {r1-r4}\t\t\t\t\t\t\t\\n\"/* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */\n            \"\tldr  r5, xSecureContextConst2\t\t\t\t\\n\"\n            \"\tstr  r1, [r5]\t\t\t\t\t\t\t\t\\n\"/* Set xSecureContext to this task's value for the same. */\n            \"\tmsr  psplim, r2\t\t\t\t\t\t\t\t\\n\"/* Set this task's PSPLIM value. */\n            \"\tmsr  control, r3\t\t\t\t\t\t\t\\n\"/* Set this task's CONTROL value. */\n            \"\tadds r0, #32\t\t\t\t\t\t\t\t\\n\"/* Discard everything up to r0. */\n            \"\tmsr  psp, r0\t\t\t\t\t\t\t\t\\n\"/* This is now the new top of stack to use in the task. */\n            \"\tisb\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tmov  r0, #0\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tmsr  basepri, r0\t\t\t\t\t\t\t\\n\"/* Ensure that interrupts are enabled when the first task starts. */\n            \"\tbx   r4\t\t\t\t\t\t\t\t\t\t\\n\"/* Finally, branch to EXC_RETURN. */\n        #else /* configENABLE_MPU */\n            \"\tldm  r0!, {r1-r3}\t\t\t\t\t\t\t\\n\"/* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */\n            \"\tldr  r4, xSecureContextConst2\t\t\t\t\\n\"\n            \"\tstr  r1, [r4]\t\t\t\t\t\t\t\t\\n\"/* Set xSecureContext to this task's value for the same. */\n            \"\tmsr  psplim, r2\t\t\t\t\t\t\t\t\\n\"/* Set this task's PSPLIM value. */\n            \"\tmovs r1, #2\t\t\t\t\t\t\t\t\t\\n\"/* r1 = 2. */\n            \"\tmsr  CONTROL, r1\t\t\t\t\t\t\t\\n\"/* Switch to use PSP in the thread mode. */\n            \"\tadds r0, #32\t\t\t\t\t\t\t\t\\n\"/* Discard everything up to r0. */\n            \"\tmsr  psp, r0\t\t\t\t\t\t\t\t\\n\"/* This is now the new top of stack to use in the task. */\n            \"\tisb\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tmov  r0, #0\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tmsr  basepri, r0\t\t\t\t\t\t\t\\n\"/* Ensure that interrupts are enabled when the first task starts. */\n            \"\tbx   r3\t\t\t\t\t\t\t\t\t\t\\n\"/* Finally, branch to EXC_RETURN. */\n        #endif /* configENABLE_MPU */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.align 4\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"pxCurrentTCBConst2: .word pxCurrentTCB\t\t\t\t\\n\"\n        \"xSecureContextConst2: .word xSecureContext\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"xMPUCTRLConst2: .word 0xe000ed94\t\t\t\t\\n\"\n            \"xMAIR0Const2: .word 0xe000edc0\t\t\t\t\t\\n\"\n            \"xRNRConst2: .word 0xe000ed98\t\t\t\t\t\\n\"\n            \"xRBARConst2: .word 0xe000ed9c\t\t\t\t\t\\n\"\n        #endif /* configENABLE_MPU */\n    );\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrs r0, control\t\t\t\t\t\t\t\t\t\\n\"/* r0 = CONTROL. */\n        \"\ttst r0, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\n        \"\tite ne\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmovne r0, #0\t\t\t\t\t\t\t\t\t\\n\"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\n        \"\tmoveq r0, #1\t\t\t\t\t\t\t\t\t\\n\"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return. */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.align 4\t\t\t\t\t\t\t\t\t\t\\n\"\n        ::: \"r0\", \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrs r0, control\t\t\t\t\t\t\t\t\t\\n\"/* Read the CONTROL register. */\n        \"\tbic r0, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* Clear the bit 0. */\n        \"\tmsr control, r0\t\t\t\t\t\t\t\t\t\\n\"/* Write back the new CONTROL value. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return to the caller. */\n        ::: \"r0\", \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vResetPrivilege( void ) /* __attribute__ (( naked )) */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrs r0, control\t\t\t\t\t\t\t\t\t\\n\"/* r0 = CONTROL. */\n        \"\torr r0, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* r0 = r0 | 1. */\n        \"\tmsr control, r0\t\t\t\t\t\t\t\t\t\\n\"/* CONTROL = r0. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return to the caller. */\n        ::: \"r0\", \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r0, xVTORConst\t\t\t\t\t\t\t\t\\n\"/* Use the NVIC offset register to locate the stack. */\n        \"\tldr r0, [r0]\t\t\t\t\t\t\t\t\t\\n\"/* Read the VTOR register which gives the address of vector table. */\n        \"\tldr r0, [r0]\t\t\t\t\t\t\t\t\t\\n\"/* The first entry in vector table is stack pointer. */\n        \"\tmsr msp, r0\t\t\t\t\t\t\t\t\t\t\\n\"/* Set the MSP back to the start of the stack. */\n        \"\tcpsie i\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Globally enable interrupts. */\n        \"\tcpsie f\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tsvc %0\t\t\t\t\t\t\t\t\t\t\t\\n\"/* System call to start the first task. */\n        \"\tnop\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"   .align 4\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"xVTORConst: .word 0xe000ed08\t\t\t\t\t\t\\n\"\n        ::\"i\" ( portSVC_START_SCHEDULER ) : \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nuint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrs r0, basepri\t\t\t\t\t\t\t\t\t\\n\"/* r0 = basepri. Return original basepri value. */\n        \"\tmov r1, %0\t\t\t\t\t\t\t\t\t\t\\n\"/* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */\n        \"\tmsr basepri, r1\t\t\t\t\t\t\t\t\t\\n\"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */\n        \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return. */\n        ::\"i\" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmsr basepri, r0\t\t\t\t\t\t\t\t\t\\n\"/* basepri = ulMask. */\n        \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return. */\n        ::: \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.extern SecureContext_SaveContext\t\t\t\t\\n\"\n        \"\t.extern SecureContext_LoadContext\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r3, xSecureContextConst\t\t\t\t\t\t\\n\"/* Read the location of xSecureContext i.e. &( xSecureContext ). */\n        \"\tldr r0, [r3]\t\t\t\t\t\t\t\t\t\\n\"/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */\n        \"\tldr r3, pxCurrentTCBConst\t\t\t\t\t\t\\n\"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n        \"\tldr r1, [r3]\t\t\t\t\t\t\t\t\t\\n\"/* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */\n        \"\tmrs r2, psp\t\t\t\t\t\t\t\t\t\t\\n\"/* Read PSP in r2. */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tcbz r0, save_ns_context\t\t\t\t\t\t\t\\n\"/* No secure context to save. */\n        \"\tpush {r0-r2, r14}\t\t\t\t\t\t\t\t\\n\"\n        \"\tbl SecureContext_SaveContext\t\t\t\t\t\\n\"/* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */\n        \"\tpop {r0-r3}\t\t\t\t\t\t\t\t\t\t\\n\"/* LR is now in r3. */\n        \"\tmov lr, r3\t\t\t\t\t\t\t\t\t\t\\n\"/* LR = r3. */\n        \"\tlsls r1, r3, #25\t\t\t\t\t\t\t\t\\n\"/* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\n        \"\tbpl save_ns_context\t\t\t\t\t\t\t\t\\n\"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r3, pxCurrentTCBConst\t\t\t\t\t\t\\n\"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n        \"\tldr r1, [r3]\t\t\t\t\t\t\t\t\t\\n\"/* Read pxCurrentTCB.*/\n        #if ( configENABLE_MPU == 1 )\n            \"\tsubs r2, r2, #16\t\t\t\t\t\t\t\\n\"/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */\n            \"\tstr r2, [r1]\t\t\t\t\t\t\t\t\\n\"/* Save the new top of stack in TCB. */\n            \"\tmrs r1, psplim\t\t\t\t\t\t\t\t\\n\"/* r1 = PSPLIM. */\n            \"\tmrs r3, control\t\t\t\t\t\t\t\t\\n\"/* r3 = CONTROL. */\n            \"\tmov r4, lr\t\t\t\t\t\t\t\t\t\\n\"/* r4 = LR/EXC_RETURN. */\n            \"\tstmia r2!, {r0, r1, r3, r4}\t\t\t\t\t\\n\"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\n        #else /* configENABLE_MPU */\n            \"\tsubs r2, r2, #12\t\t\t\t\t\t\t\\n\"/* Make space for xSecureContext, PSPLIM and LR on the stack. */\n            \"\tstr r2, [r1]\t\t\t\t\t\t\t\t\\n\"/* Save the new top of stack in TCB. */\n            \"\tmrs r1, psplim\t\t\t\t\t\t\t\t\\n\"/* r1 = PSPLIM. */\n            \"\tmov r3, lr\t\t\t\t\t\t\t\t\t\\n\"/* r3 = LR/EXC_RETURN. */\n            \"\tstmia r2!, {r0, r1, r3}\t\t\t\t\t\t\\n\"/* Store xSecureContext, PSPLIM and LR on the stack. */\n        #endif /* configENABLE_MPU */\n        \"\tb select_next_task\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \" save_ns_context:\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r3, pxCurrentTCBConst\t\t\t\t\t\t\\n\"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n        \"\tldr r1, [r3]\t\t\t\t\t\t\t\t\t\\n\"/* Read pxCurrentTCB. */\n        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )\n            \"\ttst lr, #0x10\t\t\t\t\t\t\t\t\\n\"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */\n            \"\tit eq\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tvstmdbeq r2!, {s16-s31}\t\t\t\t\t\t\\n\"/* Store the additional FP context registers which are not saved automatically. */\n        #endif /* configENABLE_FPU || configENABLE_MVE */\n        #if ( configENABLE_MPU == 1 )\n            \"\tsubs r2, r2, #48\t\t\t\t\t\t\t\\n\"/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */\n            \"\tstr r2, [r1]\t\t\t\t\t\t\t\t\\n\"/* Save the new top of stack in TCB. */\n            \"\tadds r2, r2, #16\t\t\t\t\t\t\t\\n\"/* r2 = r2 + 16. */\n            \"\tstm r2, {r4-r11}\t\t\t\t\t\t\t\\n\"/* Store the registers that are not saved automatically. */\n            \"\tmrs r1, psplim\t\t\t\t\t\t\t\t\\n\"/* r1 = PSPLIM. */\n            \"\tmrs r3, control\t\t\t\t\t\t\t\t\\n\"/* r3 = CONTROL. */\n            \"\tmov r4, lr\t\t\t\t\t\t\t\t\t\\n\"/* r4 = LR/EXC_RETURN. */\n            \"\tsubs r2, r2, #16\t\t\t\t\t\t\t\\n\"/* r2 = r2 - 16. */\n            \"\tstmia r2!, {r0, r1, r3, r4}\t\t\t\t\t\\n\"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\n        #else /* configENABLE_MPU */\n            \"\tsubs r2, r2, #44\t\t\t\t\t\t\t\\n\"/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */\n            \"\tstr r2, [r1]\t\t\t\t\t\t\t\t\\n\"/* Save the new top of stack in TCB. */\n            \"\tadds r2, r2, #12\t\t\t\t\t\t\t\\n\"/* r2 = r2 + 12. */\n            \"\tstm r2, {r4-r11}\t\t\t\t\t\t\t\\n\"/* Store the registers that are not saved automatically. */\n            \"\tmrs r1, psplim\t\t\t\t\t\t\t\t\\n\"/* r1 = PSPLIM. */\n            \"\tmov r3, lr\t\t\t\t\t\t\t\t\t\\n\"/* r3 = LR/EXC_RETURN. */\n            \"\tsubs r2, r2, #12\t\t\t\t\t\t\t\\n\"/* r2 = r2 - 12. */\n            \"\tstmia r2!, {r0, r1, r3}\t\t\t\t\t\t\\n\"/* Store xSecureContext, PSPLIM and LR on the stack. */\n        #endif /* configENABLE_MPU */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \" select_next_task:\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmov r0, %0\t\t\t\t\t\t\t\t\t\t\\n\"/* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */\n        \"\tmsr basepri, r0\t\t\t\t\t\t\t\t\t\\n\"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */\n        \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tbl vTaskSwitchContext\t\t\t\t\t\t\t\\n\"\n        \"\tmov r0, #0\t\t\t\t\t\t\t\t\t\t\\n\"/* r0 = 0. */\n        \"\tmsr basepri, r0\t\t\t\t\t\t\t\t\t\\n\"/* Enable interrupts. */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r3, pxCurrentTCBConst\t\t\t\t\t\t\\n\"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n        \"\tldr r1, [r3]\t\t\t\t\t\t\t\t\t\\n\"/* Read pxCurrentTCB. */\n        \"\tldr r2, [r1]\t\t\t\t\t\t\t\t\t\\n\"/* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"\tdmb\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Complete outstanding transfers before disabling MPU. */\n            \"\tldr r3, xMPUCTRLConst\t\t\t\t\t\t\\n\"/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */\n            \"\tldr r4, [r3]\t\t\t\t\t\t\t\t\\n\"/* Read the value of MPU_CTRL. */\n            \"\tbic r4, #1\t\t\t\t\t\t\t\t\t\\n\"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\n            \"\tstr r4, [r3]\t\t\t\t\t\t\t\t\\n\"/* Disable MPU. */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tadds r1, #4\t\t\t\t\t\t\t\t\t\\n\"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\n            \"\tldr r4, [r1]\t\t\t\t\t\t\t\t\\n\"/* r4 = *r1 i.e. r4 = MAIR0. */\n            \"\tldr r3, xMAIR0Const\t\t\t\t\t\t\t\\n\"/* r3 = 0xe000edc0 [Location of MAIR0]. */\n            \"\tstr r4, [r3]\t\t\t\t\t\t\t\t\\n\"/* Program MAIR0. */\n            \"\tldr r3, xRNRConst\t\t\t\t\t\t\t\\n\"/* r3 = 0xe000ed98 [Location of RNR]. */\n            \"\tmovs r4, #4\t\t\t\t\t\t\t\t\t\\n\"/* r4 = 4. */\n            \"\tstr r4, [r3]\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 4. */\n            \"\tadds r1, #4\t\t\t\t\t\t\t\t\t\\n\"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\n            \"\tldr r3, xRBARConst\t\t\t\t\t\t\t\\n\"/* r3 = 0xe000ed9c [Location of RBAR]. */\n            \"\tldmia r1!, {r4-r11}\t\t\t\t\t\t\t\\n\"/* Read 4 sets of RBAR/RLAR registers from TCB. */\n            \"\tstmia r3!, {r4-r11}\t\t\t\t\t\t\t\\n\"/* Write 4 set of RBAR/RLAR registers using alias registers. */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            #if ( configTOTAL_MPU_REGIONS == 16 )\n            \"\tldr r3, xRNRConst\t\t\t\t\t\t\t\\n\"/* r3 = 0xe000ed98 [Location of RNR]. */\n            \"\tmovs r4, #8\t\t\t\t\t\t\t\t\t\\n\"/* r4 = 8. */\n            \"\tstr r4, [r3]\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 8. */\n            \"\tldr r3, xRBARConst\t\t\t\t\t\t\t\\n\"/* r3 = 0xe000ed9c [Location of RBAR]. */\n            \"\tldmia r1!, {r4-r11}\t\t\t\t\t\t\t\\n\"/* Read 4 sets of RBAR/RLAR registers from TCB. */\n            \"\tstmia r3!, {r4-r11}\t\t\t\t\t\t\t\\n\"/* Write 4 set of RBAR/RLAR registers using alias registers. */\n            \"\tldr r3, xRNRConst\t\t\t\t\t\t\t\\n\"/* r3 = 0xe000ed98 [Location of RNR]. */\n            \"\tmovs r4, #12\t\t\t\t\t\t\t\t\\n\"/* r4 = 12. */\n            \"\tstr r4, [r3]\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 12. */\n            \"\tldr r3, xRBARConst\t\t\t\t\t\t\t\\n\"/* r3 = 0xe000ed9c [Location of RBAR]. */\n            \"\tldmia r1!, {r4-r11}\t\t\t\t\t\t\t\\n\"/* Read 4 sets of RBAR/RLAR registers from TCB. */\n            \"\tstmia r3!, {r4-r11}\t\t\t\t\t\t\t\\n\"/* Write 4 set of RBAR/RLAR registers using alias registers. */\n            #endif /* configTOTAL_MPU_REGIONS == 16 */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tldr r3, xMPUCTRLConst\t\t\t\t\t\t\\n\"/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */\n            \"\tldr r4, [r3]\t\t\t\t\t\t\t\t\\n\"/* Read the value of MPU_CTRL. */\n            \"\torr r4, #1\t\t\t\t\t\t\t\t\t\\n\"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\n            \"\tstr r4, [r3]\t\t\t\t\t\t\t\t\\n\"/* Enable MPU. */\n            \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Force memory writes before continuing. */\n        #endif /* configENABLE_MPU */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"\tldmia r2!, {r0, r1, r3, r4}\t\t\t\t\t\\n\"/* Read from stack - r0 = xSecureContext, r1 = PSPLIM, r3 = CONTROL and r4 = LR. */\n            \"\tmsr psplim, r1\t\t\t\t\t\t\t\t\\n\"/* Restore the PSPLIM register value for the task. */\n            \"\tmsr control, r3\t\t\t\t\t\t\t\t\\n\"/* Restore the CONTROL register value for the task. */\n            \"\tmov lr, r4\t\t\t\t\t\t\t\t\t\\n\"/* LR = r4. */\n            \"\tldr r3, xSecureContextConst\t\t\t\t\t\\n\"/* Read the location of xSecureContext i.e. &( xSecureContext ). */\n            \"\tstr r0, [r3]\t\t\t\t\t\t\t\t\\n\"/* Restore the task's xSecureContext. */\n            \"\tcbz r0, restore_ns_context\t\t\t\t\t\\n\"/* If there is no secure context for the task, restore the non-secure context. */\n            \"\tldr r3, pxCurrentTCBConst\t\t\t\t\t\\n\"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n            \"\tldr r1, [r3]\t\t\t\t\t\t\t\t\\n\"/* Read pxCurrentTCB. */\n            \"\tpush {r2, r4}\t\t\t\t\t\t\t\t\\n\"\n            \"\tbl SecureContext_LoadContext\t\t\t\t\\n\"/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */\n            \"\tpop {r2, r4}\t\t\t\t\t\t\t\t\\n\"\n            \"\tmov lr, r4\t\t\t\t\t\t\t\t\t\\n\"/* LR = r4. */\n            \"\tlsls r1, r4, #25\t\t\t\t\t\t\t\\n\"/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\n            \"\tbpl restore_ns_context\t\t\t\t\t\t\\n\"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\n            \"\tmsr psp, r2\t\t\t\t\t\t\t\t\t\\n\"/* Remember the new top of stack for the task. */\n            \"\tbx lr\t\t\t\t\t\t\t\t\t\t\\n\"\n        #else /* configENABLE_MPU */\n            \"\tldmia r2!, {r0, r1, r4}\t\t\t\t\t\t\\n\"/* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */\n            \"\tmsr psplim, r1\t\t\t\t\t\t\t\t\\n\"/* Restore the PSPLIM register value for the task. */\n            \"\tmov lr, r4\t\t\t\t\t\t\t\t\t\\n\"/* LR = r4. */\n            \"\tldr r3, xSecureContextConst\t\t\t\t\t\\n\"/* Read the location of xSecureContext i.e. &( xSecureContext ). */\n            \"\tstr r0, [r3]\t\t\t\t\t\t\t\t\\n\"/* Restore the task's xSecureContext. */\n            \"\tcbz r0, restore_ns_context\t\t\t\t\t\\n\"/* If there is no secure context for the task, restore the non-secure context. */\n            \"\tldr r3, pxCurrentTCBConst\t\t\t\t\t\\n\"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n            \"\tldr r1, [r3]\t\t\t\t\t\t\t\t\\n\"/* Read pxCurrentTCB. */\n            \"\tpush {r2, r4}\t\t\t\t\t\t\t\t\\n\"\n            \"\tbl SecureContext_LoadContext\t\t\t\t\\n\"/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */\n            \"\tpop {r2, r4}\t\t\t\t\t\t\t\t\\n\"\n            \"\tmov lr, r4\t\t\t\t\t\t\t\t\t\\n\"/* LR = r4. */\n            \"\tlsls r1, r4, #25\t\t\t\t\t\t\t\\n\"/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\n            \"\tbpl restore_ns_context\t\t\t\t\t\t\\n\"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\n            \"\tmsr psp, r2\t\t\t\t\t\t\t\t\t\\n\"/* Remember the new top of stack for the task. */\n            \"\tbx lr\t\t\t\t\t\t\t\t\t\t\\n\"\n        #endif /* configENABLE_MPU */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \" restore_ns_context:\t\t\t\t\t\t\t\t\\n\"\n        \"\tldmia r2!, {r4-r11}\t\t\t\t\t\t\t\t\\n\"/* Restore the registers that are not automatically restored. */\n        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )\n            \"\ttst lr, #0x10\t\t\t\t\t\t\t\t\\n\"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */\n            \"\tit eq\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tvldmiaeq r2!, {s16-s31}\t\t\t\t\t\t\\n\"/* Restore the additional FP context registers which are not restored automatically. */\n        #endif /* configENABLE_FPU || configENABLE_MVE */\n        \"\tmsr psp, r2\t\t\t\t\t\t\t\t\t\t\\n\"/* Remember the new top of stack for the task. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.align 4\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"pxCurrentTCBConst: .word pxCurrentTCB\t\t\t\t\\n\"\n        \"xSecureContextConst: .word xSecureContext\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"xMPUCTRLConst: .word 0xe000ed94\t\t\t\t\\n\"\n            \"xMAIR0Const: .word 0xe000edc0\t\t\t\t\t\\n\"\n            \"xRNRConst: .word 0xe000ed98\t\t\t\t\t\\n\"\n            \"xRBARConst: .word 0xe000ed9c\t\t\t\t\t\\n\"\n        #endif /* configENABLE_MPU */\n        ::\"i\" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\ttst lr, #4\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tite eq\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrseq r0, msp\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrsne r0, psp\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r1, svchandler_address_const\t\t\t\t\\n\"\n        \"\tbx r1\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.align 4\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"svchandler_address_const: .word vPortSVCHandler_C\t\\n\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tsvc %0\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Secure context is allocated in the supervisor call. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return. */\n        ::\"i\" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r2, [r0]\t\t\t\t\t\t\t\t\t\\n\"/* The first item in the TCB is the top of the stack. */\n        \"\tldr r1, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* The first item on the stack is the task's xSecureContext. */\n        \"\tcmp r1, #0\t\t\t\t\t\t\t\t\t\t\\n\"/* Raise svc if task's xSecureContext is not NULL. */\n        \"\tit ne\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tsvcne %0\t\t\t\t\t\t\t\t\t\t\\n\"/* Secure context is freed in the supervisor call. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return. */\n        ::\"i\" ( portSVC_FREE_SECURE_CONTEXT ) : \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM33/non_secure/portasm.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef __PORT_ASM_H__\n#define __PORT_ASM_H__\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n\n/* MPU wrappers includes. */\n#include \"mpu_wrappers.h\"\n\n/**\n * @brief Restore the context of the first task so that the first task starts\n * executing.\n */\nvoid vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Checks whether or not the processor is privileged.\n *\n * @return 1 if the processor is already privileged, 0 otherwise.\n */\nBaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );\n\n/**\n * @brief Raises the privilege level by clearing the bit 0 of the CONTROL\n * register.\n *\n * @note This is a privileged function and should only be called from the kenrel\n * code.\n *\n * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.\n *  Bit[0] = 0 --> The processor is running privileged\n *  Bit[0] = 1 --> The processor is running unprivileged.\n */\nvoid vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\n * register.\n *\n * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.\n *  Bit[0] = 0 --> The processor is running privileged\n *  Bit[0] = 1 --> The processor is running unprivileged.\n */\nvoid vResetPrivilege( void ) __attribute__( ( naked ) );\n\n/**\n * @brief Starts the first task.\n */\nvoid vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Disables interrupts.\n */\nuint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Enables interrupts.\n */\nvoid vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief PendSV Exception handler.\n */\nvoid PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief SVC Handler.\n */\nvoid SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Allocate a Secure context for the calling task.\n *\n * @param[in] ulSecureStackSize The size of the stack to be allocated on the\n * secure side for the calling task.\n */\nvoid vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) );\n\n/**\n * @brief Free the task's secure context.\n *\n * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.\n */\nvoid vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n#endif /* __PORT_ASM_H__ */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM33/non_secure/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef PORTMACRO_H\n#define PORTMACRO_H\n\n#ifdef __cplusplus\n    extern \"C\" {\n#endif\n\n#include \"portmacrocommon.h\"\n\n/*------------------------------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the given hardware\n * and compiler.\n *\n * These settings should not be altered.\n *------------------------------------------------------------------------------\n */\n\n/**\n * Architecture specifics.\n */\n#define portARCH_NAME                       \"Cortex-M33\"\n#define portDONT_DISCARD                    __attribute__( ( used ) )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Critical section management.\n */\n#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()\n#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )\n/*-----------------------------------------------------------*/\n\n#ifdef __cplusplus\n    }\n#endif\n\n#endif /* PORTMACRO_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef PORTMACROCOMMON_H\n    #define PORTMACROCOMMON_H\n\n    #ifdef __cplusplus\n        extern \"C\" {\n    #endif\n\n/*------------------------------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the given hardware\n * and compiler.\n *\n * These settings should not be altered.\n *------------------------------------------------------------------------------\n */\n\n    #ifndef configENABLE_FPU\n        #error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.\n    #endif /* configENABLE_FPU */\n\n    #ifndef configENABLE_MPU\n        #error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.\n    #endif /* configENABLE_MPU */\n\n    #ifndef configENABLE_TRUSTZONE\n        #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.\n    #endif /* configENABLE_TRUSTZONE */\n\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Type definitions.\n */\n    #define portCHAR          char\n    #define portFLOAT         float\n    #define portDOUBLE        double\n    #define portLONG          long\n    #define portSHORT         short\n    #define portSTACK_TYPE    uint32_t\n    #define portBASE_TYPE     long\n\n    typedef portSTACK_TYPE   StackType_t;\n    typedef long             BaseType_t;\n    typedef unsigned long    UBaseType_t;\n\n    #if ( configUSE_16_BIT_TICKS == 1 )\n        typedef uint16_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffff\n    #else\n        typedef uint32_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL\n\n/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\n * not need to be guarded with a critical section. */\n        #define portTICK_TYPE_IS_ATOMIC    1\n    #endif\n/*-----------------------------------------------------------*/\n\n/**\n * Architecture specifics.\n */\n    #define portSTACK_GROWTH                   ( -1 )\n    #define portTICK_PERIOD_MS                 ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\n    #define portBYTE_ALIGNMENT                 8\n    #define portNOP()\n    #define portINLINE                         __inline\n    #ifndef portFORCE_INLINE\n        #define portFORCE_INLINE               inline __attribute__( ( always_inline ) )\n    #endif\n    #define portHAS_STACK_OVERFLOW_CHECKING    1\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Extern declarations.\n */\n    extern BaseType_t xPortIsInsideInterrupt( void );\n\n    extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;\n\n    extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;\n    extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;\n\n    extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\n    extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\n\n    #if ( configENABLE_TRUSTZONE == 1 )\n        extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */\n        extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;\n    #endif /* configENABLE_TRUSTZONE */\n\n    #if ( configENABLE_MPU == 1 )\n        extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;\n        extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;\n    #endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\n/**\n * @brief MPU specific constants.\n */\n    #if ( configENABLE_MPU == 1 )\n        #define portUSING_MPU_WRAPPERS    1\n        #define portPRIVILEGE_BIT         ( 0x80000000UL )\n    #else\n        #define portPRIVILEGE_BIT         ( 0x0UL )\n    #endif /* configENABLE_MPU */\n\n/* MPU settings that can be overriden in FreeRTOSConfig.h. */\n#ifndef configTOTAL_MPU_REGIONS\n    /* Define to 8 for backward compatibility. */\n    #define configTOTAL_MPU_REGIONS       ( 8UL )\n#endif\n\n/* MPU regions. */\n    #define portPRIVILEGED_FLASH_REGION                   ( 0UL )\n    #define portUNPRIVILEGED_FLASH_REGION                 ( 1UL )\n    #define portUNPRIVILEGED_SYSCALLS_REGION              ( 2UL )\n    #define portPRIVILEGED_RAM_REGION                     ( 3UL )\n    #define portSTACK_REGION                              ( 4UL )\n    #define portFIRST_CONFIGURABLE_REGION                 ( 5UL )\n    #define portLAST_CONFIGURABLE_REGION                  ( configTOTAL_MPU_REGIONS - 1UL )\n    #define portNUM_CONFIGURABLE_REGIONS                  ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )\n    #define portTOTAL_NUM_REGIONS                         ( portNUM_CONFIGURABLE_REGIONS + 1 )   /* Plus one to make space for the stack region. */\n\n/* Device memory attributes used in MPU_MAIR registers.\n *\n * 8-bit values encoded as follows:\n *  Bit[7:4] - 0000 - Device Memory\n *  Bit[3:2] - 00 --> Device-nGnRnE\n *\t\t\t\t01 --> Device-nGnRE\n *\t\t\t\t10 --> Device-nGRE\n *\t\t\t\t11 --> Device-GRE\n *  Bit[1:0] - 00, Reserved.\n */\n    #define portMPU_DEVICE_MEMORY_nGnRnE                  ( 0x00 )   /* 0000 0000 */\n    #define portMPU_DEVICE_MEMORY_nGnRE                   ( 0x04 )   /* 0000 0100 */\n    #define portMPU_DEVICE_MEMORY_nGRE                    ( 0x08 )   /* 0000 1000 */\n    #define portMPU_DEVICE_MEMORY_GRE                     ( 0x0C )   /* 0000 1100 */\n\n/* Normal memory attributes used in MPU_MAIR registers. */\n    #define portMPU_NORMAL_MEMORY_NON_CACHEABLE           ( 0x44 )   /* Non-cacheable. */\n    #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE    ( 0xFF )   /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */\n\n/* Attributes used in MPU_RBAR registers. */\n    #define portMPU_REGION_NON_SHAREABLE                  ( 0UL << 3UL )\n    #define portMPU_REGION_INNER_SHAREABLE                ( 1UL << 3UL )\n    #define portMPU_REGION_OUTER_SHAREABLE                ( 2UL << 3UL )\n\n    #define portMPU_REGION_PRIVILEGED_READ_WRITE          ( 0UL << 1UL )\n    #define portMPU_REGION_READ_WRITE                     ( 1UL << 1UL )\n    #define portMPU_REGION_PRIVILEGED_READ_ONLY           ( 2UL << 1UL )\n    #define portMPU_REGION_READ_ONLY                      ( 3UL << 1UL )\n\n    #define portMPU_REGION_EXECUTE_NEVER                  ( 1UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Settings to define an MPU region.\n */\n    typedef struct MPURegionSettings\n    {\n        uint32_t ulRBAR; /**< RBAR for the region. */\n        uint32_t ulRLAR; /**< RLAR for the region. */\n    } MPURegionSettings_t;\n\n/**\n * @brief MPU settings as stored in the TCB.\n */\n    typedef struct MPU_SETTINGS\n    {\n        uint32_t ulMAIR0;                                              /**< MAIR0 for the task containing attributes for all the 4 per task regions. */\n        MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */\n    } xMPU_SETTINGS;\n/*-----------------------------------------------------------*/\n\n/**\n * @brief SVC numbers.\n */\n    #define portSVC_ALLOCATE_SECURE_CONTEXT    0\n    #define portSVC_FREE_SECURE_CONTEXT        1\n    #define portSVC_START_SCHEDULER            2\n    #define portSVC_RAISE_PRIVILEGE            3\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Scheduler utilities.\n */\n    #define portYIELD()                                 vPortYield()\n    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )\n    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )\n    #define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )\n    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Critical section management.\n */\n    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulSetInterruptMask()\n    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vClearInterruptMask( x )\n    #define portENTER_CRITICAL()                      vPortEnterCritical()\n    #define portEXIT_CRITICAL()                       vPortExitCritical()\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Tickless idle/low power functionality.\n */\n    #ifndef portSUPPRESS_TICKS_AND_SLEEP\n        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );\n        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )\n    #endif\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Task function macros as described on the FreeRTOS.org WEB site.\n */\n    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )\n    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )\n/*-----------------------------------------------------------*/\n\n    #if ( configENABLE_TRUSTZONE == 1 )\n\n/**\n * @brief Allocate a secure context for the task.\n *\n * Tasks are not created with a secure context. Any task that is going to call\n * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a\n * secure context before it calls any secure function.\n *\n * @param[in] ulSecureStackSize The size of the secure stack to be allocated.\n */\n        #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )\n\n/**\n * @brief Called when a task is deleted to delete the task's secure context,\n * if it has one.\n *\n * @param[in] pxTCB The TCB of the task being deleted.\n */\n        #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )\n    #endif /* configENABLE_TRUSTZONE */\n/*-----------------------------------------------------------*/\n\n    #if ( configENABLE_MPU == 1 )\n\n/**\n * @brief Checks whether or not the processor is privileged.\n *\n * @return 1 if the processor is already privileged, 0 otherwise.\n */\n        #define portIS_PRIVILEGED()      xIsPrivileged()\n\n/**\n * @brief Raise an SVC request to raise privilege.\n *\n * The SVC handler checks that the SVC was raised from a system call and only\n * then it raises the privilege. If this is called from any other place,\n * the privilege is not raised.\n */\n        #define portRAISE_PRIVILEGE()    __asm volatile ( \"svc %0 \\n\" ::\"i\" ( portSVC_RAISE_PRIVILEGE ) : \"memory\" );\n\n/**\n * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\n * register.\n */\n        #define portRESET_PRIVILEGE()    vResetPrivilege()\n    #else\n        #define portIS_PRIVILEGED()\n        #define portRAISE_PRIVILEGE()\n        #define portRESET_PRIVILEGE()\n    #endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Barriers.\n */\n    #define portMEMORY_BARRIER()    __asm volatile ( \"\" ::: \"memory\" )\n/*-----------------------------------------------------------*/\n\n    #ifdef __cplusplus\n        }\n    #endif\n\n#endif /* PORTMACROCOMMON_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM33/secure/secure_context.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Secure context includes. */\n#include \"secure_context.h\"\n\n/* Secure heap includes. */\n#include \"secure_heap.h\"\n\n/* Secure port macros. */\n#include \"secure_port_macros.h\"\n\n/**\n * @brief CONTROL value for privileged tasks.\n *\n * Bit[0] - 0 --> Thread mode is privileged.\n * Bit[1] - 1 --> Thread mode uses PSP.\n */\n#define securecontextCONTROL_VALUE_PRIVILEGED      0x02\n\n/**\n * @brief CONTROL value for un-privileged tasks.\n *\n * Bit[0] - 1 --> Thread mode is un-privileged.\n * Bit[1] - 1 --> Thread mode uses PSP.\n */\n#define securecontextCONTROL_VALUE_UNPRIVILEGED    0x03\n\n/**\n * @brief Size of stack seal values in bytes.\n */\n#define securecontextSTACK_SEAL_SIZE               8\n\n/**\n * @brief Stack seal value as recommended by ARM.\n */\n#define securecontextSTACK_SEAL_VALUE              0xFEF5EDA5\n\n/**\n * @brief Maximum number of secure contexts.\n */\n#ifndef secureconfigMAX_SECURE_CONTEXTS\n    #define secureconfigMAX_SECURE_CONTEXTS        8UL\n#endif\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Pre-allocated array of secure contexts.\n */\nSecureContext_t xSecureContexts[ secureconfigMAX_SECURE_CONTEXTS ];\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Get a free secure context for a task from the secure context pool (xSecureContexts).\n *\n * This function ensures that only one secure context is allocated for a task.\n *\n * @param[in] pvTaskHandle The task handle for which the secure context is allocated.\n *\n * @return Index of a free secure context in the xSecureContexts array.\n */\nstatic uint32_t ulGetSecureContext( void * pvTaskHandle );\n\n/**\n * @brief Return the secure context to the secure context pool (xSecureContexts).\n *\n * @param[in] ulSecureContextIndex Index of the context in the xSecureContexts array.\n */\nstatic void vReturnSecureContext( uint32_t ulSecureContextIndex );\n\n/* These are implemented in assembly. */\nextern void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext );\nextern void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext );\n/*-----------------------------------------------------------*/\n\nstatic uint32_t ulGetSecureContext( void * pvTaskHandle )\n{\n    /* Start with invalid index. */\n    uint32_t i, ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS;\n\n    for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ )\n    {\n        if( ( xSecureContexts[ i ].pucCurrentStackPointer == NULL ) &&\n            ( xSecureContexts[ i ].pucStackLimit == NULL ) &&\n            ( xSecureContexts[ i ].pucStackStart == NULL ) &&\n            ( xSecureContexts[ i ].pvTaskHandle == NULL ) &&\n            ( ulSecureContextIndex == secureconfigMAX_SECURE_CONTEXTS ) )\n        {\n            ulSecureContextIndex = i;\n        }\n        else if( xSecureContexts[ i ].pvTaskHandle == pvTaskHandle )\n        {\n            /* A task can only have one secure context. Do not allocate a second\n             * context for the same task. */\n            ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS;\n            break;\n        }\n    }\n\n    return ulSecureContextIndex;\n}\n/*-----------------------------------------------------------*/\n\nstatic void vReturnSecureContext( uint32_t ulSecureContextIndex )\n{\n    xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = NULL;\n    xSecureContexts[ ulSecureContextIndex ].pucStackLimit = NULL;\n    xSecureContexts[ ulSecureContextIndex ].pucStackStart = NULL;\n    xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = NULL;\n}\n/*-----------------------------------------------------------*/\n\nsecureportNON_SECURE_CALLABLE void SecureContext_Init( void )\n{\n    uint32_t ulIPSR, i;\n    static uint32_t ulSecureContextsInitialized = 0;\n\n    /* Read the Interrupt Program Status Register (IPSR) value. */\n    secureportREAD_IPSR( ulIPSR );\n\n    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\n     * when the processor is running in the Thread Mode. */\n    if( ( ulIPSR != 0 ) && ( ulSecureContextsInitialized == 0 ) )\n    {\n        /* Ensure to initialize secure contexts only once. */\n        ulSecureContextsInitialized = 1;\n\n        /* No stack for thread mode until a task's context is loaded. */\n        secureportSET_PSPLIM( securecontextNO_STACK );\n        secureportSET_PSP( securecontextNO_STACK );\n\n        /* Initialize all secure contexts. */\n        for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ )\n        {\n            xSecureContexts[ i ].pucCurrentStackPointer = NULL;\n            xSecureContexts[ i ].pucStackLimit = NULL;\n            xSecureContexts[ i ].pucStackStart = NULL;\n            xSecureContexts[ i ].pvTaskHandle = NULL;\n        }\n\n        #if ( configENABLE_MPU == 1 )\n            {\n                /* Configure thread mode to use PSP and to be unprivileged. */\n                secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );\n            }\n        #else /* configENABLE_MPU */\n            {\n                /* Configure thread mode to use PSP and to be privileged. */\n                secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );\n            }\n        #endif /* configENABLE_MPU */\n    }\n}\n/*-----------------------------------------------------------*/\n\n#if ( configENABLE_MPU == 1 )\n    secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,\n                                                                                       uint32_t ulIsTaskPrivileged,\n                                                                                       void * pvTaskHandle )\n#else /* configENABLE_MPU */\n    secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,\n                                                                                       void * pvTaskHandle )\n#endif /* configENABLE_MPU */\n{\n    uint8_t * pucStackMemory = NULL;\n    uint8_t * pucStackLimit;\n    uint32_t ulIPSR, ulSecureContextIndex;\n    SecureContextHandle_t xSecureContextHandle = securecontextINVALID_CONTEXT_ID;\n\n    #if ( configENABLE_MPU == 1 )\n        uint32_t * pulCurrentStackPointer = NULL;\n    #endif /* configENABLE_MPU */\n\n    /* Read the Interrupt Program Status Register (IPSR) and Process Stack Limit\n     * Register (PSPLIM) value. */\n    secureportREAD_IPSR( ulIPSR );\n    secureportREAD_PSPLIM( pucStackLimit );\n\n    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\n     * when the processor is running in the Thread Mode.\n     * Also do nothing, if a secure context us already loaded. PSPLIM is set to\n     * securecontextNO_STACK when no secure context is loaded. */\n    if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) )\n    {\n        /* Ontain a free secure context. */\n        ulSecureContextIndex = ulGetSecureContext( pvTaskHandle );\n\n        /* Were we able to get a free context? */\n        if( ulSecureContextIndex < secureconfigMAX_SECURE_CONTEXTS )\n        {\n            /* Allocate the stack space. */\n            pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE );\n\n            if( pucStackMemory != NULL )\n            {\n                /* Since stack grows down, the starting point will be the last\n                 * location. Note that this location is next to the last\n                 * allocated byte for stack (excluding the space for seal values)\n                 * because the hardware decrements the stack pointer before\n                 * writing i.e. if stack pointer is 0x2, a push operation will\n                 * decrement the stack pointer to 0x1 and then write at 0x1. */\n                xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize;\n\n                /* Seal the created secure process stack. */\n                *( uint32_t * )( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE;\n                *( uint32_t * )( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE;\n\n                /* The stack cannot go beyond this location. This value is\n                 * programmed in the PSPLIM register on context switch.*/\n                xSecureContexts[ ulSecureContextIndex ].pucStackLimit = pucStackMemory;\n\n                xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle;\n\n                #if ( configENABLE_MPU == 1 )\n                    {\n                        /* Store the correct CONTROL value for the task on the stack.\n                         * This value is programmed in the CONTROL register on\n                         * context switch. */\n                        pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart;\n                        pulCurrentStackPointer--;\n\n                        if( ulIsTaskPrivileged )\n                        {\n                            *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;\n                        }\n                        else\n                        {\n                            *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;\n                        }\n\n                        /* Store the current stack pointer. This value is programmed in\n                         * the PSP register on context switch. */\n                        xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;\n                    }\n                #else /* configENABLE_MPU */\n                    {\n                        /* Current SP is set to the starting of the stack. This\n                         * value programmed in the PSP register on context switch. */\n                        xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart;\n                    }\n                #endif /* configENABLE_MPU */\n\n                /* Ensure to never return 0 as a valid context handle. */\n                xSecureContextHandle = ulSecureContextIndex + 1UL;\n            }\n        }\n    }\n\n    return xSecureContextHandle;\n}\n/*-----------------------------------------------------------*/\n\nsecureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )\n{\n    uint32_t ulIPSR, ulSecureContextIndex;\n\n    /* Read the Interrupt Program Status Register (IPSR) value. */\n    secureportREAD_IPSR( ulIPSR );\n\n    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\n     * when the processor is running in the Thread Mode. */\n    if( ulIPSR != 0 )\n    {\n        /* Only free if a valid context handle is passed. */\n        if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) )\n        {\n            ulSecureContextIndex = xSecureContextHandle - 1UL;\n\n            /* Ensure that the secure context being deleted is associated with\n             * the task. */\n            if( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle )\n            {\n                /* Free the stack space. */\n                vPortFree( xSecureContexts[ ulSecureContextIndex ].pucStackLimit );\n\n                /* Return the secure context back to the free secure contexts pool. */\n                vReturnSecureContext( ulSecureContextIndex );\n            }\n        }\n    }\n}\n/*-----------------------------------------------------------*/\n\nsecureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )\n{\n    uint8_t * pucStackLimit;\n    uint32_t ulSecureContextIndex;\n\n    if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) )\n    {\n        ulSecureContextIndex = xSecureContextHandle - 1UL;\n\n        secureportREAD_PSPLIM( pucStackLimit );\n\n        /* Ensure that no secure context is loaded and the task is loading it's\n         * own context. */\n        if( ( pucStackLimit == securecontextNO_STACK ) &&\n            ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) )\n        {\n            SecureContext_LoadContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) );\n        }\n    }\n}\n/*-----------------------------------------------------------*/\n\nsecureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )\n{\n    uint8_t * pucStackLimit;\n    uint32_t ulSecureContextIndex;\n\n    if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) )\n    {\n        ulSecureContextIndex = xSecureContextHandle - 1UL;\n\n        secureportREAD_PSPLIM( pucStackLimit );\n\n        /* Ensure that task's context is loaded and the task is saving it's own\n         * context. */\n        if( ( xSecureContexts[ ulSecureContextIndex ].pucStackLimit == pucStackLimit ) &&\n            ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) )\n        {\n            SecureContext_SaveContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) );\n        }\n    }\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM33/secure/secure_context.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef __SECURE_CONTEXT_H__\n#define __SECURE_CONTEXT_H__\n\n/* Standard includes. */\n#include <stdint.h>\n\n/* FreeRTOS includes. */\n#include \"FreeRTOSConfig.h\"\n\n/**\n * @brief PSP value when no secure context is loaded.\n */\n#define securecontextNO_STACK               0x0\n\n/**\n * @brief Invalid context ID.\n */\n#define securecontextINVALID_CONTEXT_ID     0UL\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Structure to represent a secure context.\n *\n * @note Since stack grows down, pucStackStart is the highest address while\n * pucStackLimit is the first address of the allocated memory.\n */\ntypedef struct SecureContext\n{\n    uint8_t * pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */\n    uint8_t * pucStackLimit;          /**< Last location of the stack memory (PSPLIM). */\n    uint8_t * pucStackStart;          /**< First location of the stack memory. */\n    void * pvTaskHandle;              /**< Task handle of the task this context is associated with. */\n} SecureContext_t;\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Opaque handle for a secure context.\n */\ntypedef uint32_t SecureContextHandle_t;\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Initializes the secure context management system.\n *\n * PSP is set to NULL and therefore a task must allocate and load a context\n * before calling any secure side function in the thread mode.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n */\nvoid SecureContext_Init( void );\n\n/**\n * @brief Allocates a context on the secure side.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n *\n * @param[in] ulSecureStackSize Size of the stack to allocate on secure side.\n * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise.\n *\n * @return Opaque context handle if context is successfully allocated, NULL\n * otherwise.\n */\n#if ( configENABLE_MPU == 1 )\n    SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,\n                                                         uint32_t ulIsTaskPrivileged,\n                                                         void * pvTaskHandle );\n#else /* configENABLE_MPU */\n    SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,\n                                                         void * pvTaskHandle );\n#endif /* configENABLE_MPU */\n\n/**\n * @brief Frees the given context.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n *\n * @param[in] xSecureContextHandle Context handle corresponding to the\n * context to be freed.\n */\nvoid SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );\n\n/**\n * @brief Loads the given context.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n *\n * @param[in] xSecureContextHandle Context handle corresponding to the context\n * to be loaded.\n */\nvoid SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );\n\n/**\n * @brief Saves the given context.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n *\n * @param[in] xSecureContextHandle Context handle corresponding to the context\n * to be saved.\n */\nvoid SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );\n\n#endif /* __SECURE_CONTEXT_H__ */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM33/secure/secure_context_port.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Secure context includes. */\n#include \"secure_context.h\"\n\n/* Secure port macros. */\n#include \"secure_port_macros.h\"\n\nvoid SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) );\nvoid SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) );\n\nvoid SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext )\n{\n    /* pxSecureContext value is in r0. */\n    __asm volatile\n    (\n        \" .syntax unified                   \\n\"\n        \"                                   \\n\"\n        \" mrs r1, ipsr                      \\n\" /* r1 = IPSR. */\n        \" cbz r1, load_ctx_therad_mode      \\n\" /* Do nothing if the processor is running in the Thread Mode. */\n        \" ldmia r0!, {r1, r2}               \\n\" /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */\n        \"                                   \\n\"\n        #if ( configENABLE_MPU == 1 )\n            \" ldmia r1!, {r3}               \\n\" /* Read CONTROL register value from task's stack. r3 = CONTROL. */\n            \" msr control, r3               \\n\" /* CONTROL = r3. */\n        #endif /* configENABLE_MPU */\n        \"                                   \\n\"\n        \" msr psplim, r2                    \\n\" /* PSPLIM = r2. */\n        \" msr psp, r1                       \\n\" /* PSP = r1. */\n        \"                                   \\n\"\n        \" load_ctx_therad_mode:             \\n\"\n        \"    bx lr                          \\n\"\n        \"                                   \\n\"\n        ::: \"r0\", \"r1\", \"r2\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext )\n{\n    /* pxSecureContext value is in r0. */\n    __asm volatile\n    (\n        \" .syntax unified                   \\n\"\n        \"                                   \\n\"\n        \" mrs r1, ipsr                      \\n\" /* r1 = IPSR. */\n        \" cbz r1, save_ctx_therad_mode      \\n\" /* Do nothing if the processor is running in the Thread Mode. */\n        \" mrs r1, psp                       \\n\" /* r1 = PSP. */\n        \"                                   \\n\"\n        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )\n            \" vstmdb r1!, {s0}              \\n\" /* Trigger the deferred stacking of FPU registers. */\n            \" vldmia r1!, {s0}              \\n\" /* Nullify the effect of the previous statement. */\n        #endif /* configENABLE_FPU || configENABLE_MVE */\n        \"                                   \\n\"\n        #if ( configENABLE_MPU == 1 )\n            \" mrs r2, control               \\n\" /* r2 = CONTROL. */\n            \" stmdb r1!, {r2}               \\n\" /* Store CONTROL value on the stack. */\n        #endif /* configENABLE_MPU */\n        \"                                   \\n\"\n        \" str r1, [r0]                      \\n\" /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */\n        \" movs r1, %0                       \\n\" /* r1 = securecontextNO_STACK. */\n        \" msr psplim, r1                    \\n\" /* PSPLIM = securecontextNO_STACK. */\n        \" msr psp, r1                       \\n\" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */\n        \"                                   \\n\"\n        \" save_ctx_therad_mode:             \\n\"\n        \"    bx lr                          \\n\"\n        \"                                   \\n\"\n        ::\"i\" ( securecontextNO_STACK ) : \"r1\", \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM33/secure/secure_heap.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Standard includes. */\n#include <stdint.h>\n\n/* Secure context heap includes. */\n#include \"secure_heap.h\"\n\n/* Secure port macros. */\n#include \"secure_port_macros.h\"\n\n/**\n * @brief Total heap size.\n */\n#ifndef secureconfigTOTAL_HEAP_SIZE\n    #define secureconfigTOTAL_HEAP_SIZE    ( ( ( size_t ) ( 10 * 1024 ) ) )\n#endif\n\n/* No test marker by default. */\n#ifndef mtCOVERAGE_TEST_MARKER\n    #define mtCOVERAGE_TEST_MARKER()\n#endif\n\n/* No tracing by default. */\n#ifndef traceMALLOC\n    #define traceMALLOC( pvReturn, xWantedSize )\n#endif\n\n/* No tracing by default. */\n#ifndef traceFREE\n    #define traceFREE( pv, xBlockSize )\n#endif\n\n/* Block sizes must not get too small. */\n#define secureheapMINIMUM_BLOCK_SIZE    ( ( size_t ) ( xHeapStructSize << 1 ) )\n\n/* Assumes 8bit bytes! */\n#define secureheapBITS_PER_BYTE         ( ( size_t ) 8 )\n/*-----------------------------------------------------------*/\n\n/* Allocate the memory for the heap. */\n#if ( configAPPLICATION_ALLOCATED_HEAP == 1 )\n\n/* The application writer has already defined the array used for the RTOS\n* heap - probably so it can be placed in a special segment or address. */\n    extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];\n#else /* configAPPLICATION_ALLOCATED_HEAP */\n    static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];\n#endif /* configAPPLICATION_ALLOCATED_HEAP */\n\n/**\n * @brief The linked list structure.\n *\n * This is used to link free blocks in order of their memory address.\n */\ntypedef struct A_BLOCK_LINK\n{\n    struct A_BLOCK_LINK * pxNextFreeBlock; /**< The next free block in the list. */\n    size_t xBlockSize;                     /**< The size of the free block. */\n} BlockLink_t;\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Called automatically to setup the required heap structures the first\n * time pvPortMalloc() is called.\n */\nstatic void prvHeapInit( void );\n\n/**\n * @brief Inserts a block of memory that is being freed into the correct\n * position in the list of free memory blocks.\n *\n * The block being freed will be merged with the block in front it and/or the\n * block behind it if the memory blocks are adjacent to each other.\n *\n * @param[in] pxBlockToInsert The block being freed.\n */\nstatic void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert );\n/*-----------------------------------------------------------*/\n\n/**\n * @brief The size of the structure placed at the beginning of each allocated\n * memory block must by correctly byte aligned.\n */\nstatic const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );\n\n/**\n * @brief Create a couple of list links to mark the start and end of the list.\n */\nstatic BlockLink_t xStart;\nstatic BlockLink_t * pxEnd = NULL;\n\n/**\n * @brief Keeps track of the number of free bytes remaining, but says nothing\n * about fragmentation.\n */\nstatic size_t xFreeBytesRemaining = 0U;\nstatic size_t xMinimumEverFreeBytesRemaining = 0U;\n\n/**\n * @brief Gets set to the top bit of an size_t type.\n *\n * When this bit in the xBlockSize member of an BlockLink_t structure is set\n * then the block belongs to the application. When the bit is free the block is\n * still part of the free heap space.\n */\nstatic size_t xBlockAllocatedBit = 0;\n/*-----------------------------------------------------------*/\n\nstatic void prvHeapInit( void )\n{\n    BlockLink_t * pxFirstFreeBlock;\n    uint8_t * pucAlignedHeap;\n    size_t uxAddress;\n    size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE;\n\n    /* Ensure the heap starts on a correctly aligned boundary. */\n    uxAddress = ( size_t ) ucHeap;\n\n    if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 )\n    {\n        uxAddress += ( secureportBYTE_ALIGNMENT - 1 );\n        uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );\n        xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;\n    }\n\n    pucAlignedHeap = ( uint8_t * ) uxAddress;\n\n    /* xStart is used to hold a pointer to the first item in the list of free\n     * blocks.  The void cast is used to prevent compiler warnings. */\n    xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;\n    xStart.xBlockSize = ( size_t ) 0;\n\n    /* pxEnd is used to mark the end of the list of free blocks and is inserted\n     * at the end of the heap space. */\n    uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;\n    uxAddress -= xHeapStructSize;\n    uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );\n    pxEnd = ( void * ) uxAddress;\n    pxEnd->xBlockSize = 0;\n    pxEnd->pxNextFreeBlock = NULL;\n\n    /* To start with there is a single free block that is sized to take up the\n     * entire heap space, minus the space taken by pxEnd. */\n    pxFirstFreeBlock = ( void * ) pucAlignedHeap;\n    pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;\n    pxFirstFreeBlock->pxNextFreeBlock = pxEnd;\n\n    /* Only one block exists - and it covers the entire usable heap space. */\n    xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;\n    xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;\n\n    /* Work out the position of the top bit in a size_t variable. */\n    xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert )\n{\n    BlockLink_t * pxIterator;\n    uint8_t * puc;\n\n    /* Iterate through the list until a block is found that has a higher address\n     * than the block being inserted. */\n    for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )\n    {\n        /* Nothing to do here, just iterate to the right position. */\n    }\n\n    /* Do the block being inserted, and the block it is being inserted after\n     * make a contiguous block of memory? */\n    puc = ( uint8_t * ) pxIterator;\n\n    if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )\n    {\n        pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;\n        pxBlockToInsert = pxIterator;\n    }\n    else\n    {\n        mtCOVERAGE_TEST_MARKER();\n    }\n\n    /* Do the block being inserted, and the block it is being inserted before\n     * make a contiguous block of memory? */\n    puc = ( uint8_t * ) pxBlockToInsert;\n\n    if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )\n    {\n        if( pxIterator->pxNextFreeBlock != pxEnd )\n        {\n            /* Form one big block from the two blocks. */\n            pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;\n            pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;\n        }\n        else\n        {\n            pxBlockToInsert->pxNextFreeBlock = pxEnd;\n        }\n    }\n    else\n    {\n        pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;\n    }\n\n    /* If the block being inserted plugged a gab, so was merged with the block\n     * before and the block after, then it's pxNextFreeBlock pointer will have\n     * already been set, and should not be set here as that would make it point\n     * to itself. */\n    if( pxIterator != pxBlockToInsert )\n    {\n        pxIterator->pxNextFreeBlock = pxBlockToInsert;\n    }\n    else\n    {\n        mtCOVERAGE_TEST_MARKER();\n    }\n}\n/*-----------------------------------------------------------*/\n\nvoid * pvPortMalloc( size_t xWantedSize )\n{\n    BlockLink_t * pxBlock;\n    BlockLink_t * pxPreviousBlock;\n    BlockLink_t * pxNewBlockLink;\n    void * pvReturn = NULL;\n\n    /* If this is the first call to malloc then the heap will require\n     * initialisation to setup the list of free blocks. */\n    if( pxEnd == NULL )\n    {\n        prvHeapInit();\n    }\n    else\n    {\n        mtCOVERAGE_TEST_MARKER();\n    }\n\n    /* Check the requested block size is not so large that the top bit is set.\n     * The top bit of the block size member of the BlockLink_t structure is used\n     * to determine who owns the block - the application or the kernel, so it\n     * must be free. */\n    if( ( xWantedSize & xBlockAllocatedBit ) == 0 )\n    {\n        /* The wanted size is increased so it can contain a BlockLink_t\n         * structure in addition to the requested amount of bytes. */\n        if( xWantedSize > 0 )\n        {\n            xWantedSize += xHeapStructSize;\n\n            /* Ensure that blocks are always aligned to the required number of\n             * bytes. */\n            if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )\n            {\n                /* Byte alignment required. */\n                xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );\n                secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n\n        if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )\n        {\n            /* Traverse the list from the start (lowest address) block until\n             * one of adequate size is found. */\n            pxPreviousBlock = &xStart;\n            pxBlock = xStart.pxNextFreeBlock;\n\n            while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )\n            {\n                pxPreviousBlock = pxBlock;\n                pxBlock = pxBlock->pxNextFreeBlock;\n            }\n\n            /* If the end marker was reached then a block of adequate size was\n             * not found. */\n            if( pxBlock != pxEnd )\n            {\n                /* Return the memory space pointed to - jumping over the\n                 * BlockLink_t structure at its start. */\n                pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );\n\n                /* This block is being returned for use so must be taken out\n                 * of the list of free blocks. */\n                pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;\n\n                /* If the block is larger than required it can be split into\n                 * two. */\n                if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE )\n                {\n                    /* This block is to be split into two.  Create a new\n                     * block following the number of bytes requested. The void\n                     * cast is used to prevent byte alignment warnings from the\n                     * compiler. */\n                    pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );\n                    secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 );\n\n                    /* Calculate the sizes of two blocks split from the single\n                     * block. */\n                    pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;\n                    pxBlock->xBlockSize = xWantedSize;\n\n                    /* Insert the new block into the list of free blocks. */\n                    prvInsertBlockIntoFreeList( pxNewBlockLink );\n                }\n                else\n                {\n                    mtCOVERAGE_TEST_MARKER();\n                }\n\n                xFreeBytesRemaining -= pxBlock->xBlockSize;\n\n                if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )\n                {\n                    xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;\n                }\n                else\n                {\n                    mtCOVERAGE_TEST_MARKER();\n                }\n\n                /* The block is being returned - it is allocated and owned by\n                 * the application and has no \"next\" block. */\n                pxBlock->xBlockSize |= xBlockAllocatedBit;\n                pxBlock->pxNextFreeBlock = NULL;\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n    }\n    else\n    {\n        mtCOVERAGE_TEST_MARKER();\n    }\n\n    traceMALLOC( pvReturn, xWantedSize );\n\n    #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )\n        {\n            if( pvReturn == NULL )\n            {\n                extern void vApplicationMallocFailedHook( void );\n                vApplicationMallocFailedHook();\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n    #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */\n\n    secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );\n    return pvReturn;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortFree( void * pv )\n{\n    uint8_t * puc = ( uint8_t * ) pv;\n    BlockLink_t * pxLink;\n\n    if( pv != NULL )\n    {\n        /* The memory being freed will have an BlockLink_t structure immediately\n         * before it. */\n        puc -= xHeapStructSize;\n\n        /* This casting is to keep the compiler from issuing warnings. */\n        pxLink = ( void * ) puc;\n\n        /* Check the block is actually allocated. */\n        secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );\n        secureportASSERT( pxLink->pxNextFreeBlock == NULL );\n\n        if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )\n        {\n            if( pxLink->pxNextFreeBlock == NULL )\n            {\n                /* The block is being returned to the heap - it is no longer\n                 * allocated. */\n                pxLink->xBlockSize &= ~xBlockAllocatedBit;\n\n                secureportDISABLE_NON_SECURE_INTERRUPTS();\n                {\n                    /* Add this block to the list of free blocks. */\n                    xFreeBytesRemaining += pxLink->xBlockSize;\n                    traceFREE( pv, pxLink->xBlockSize );\n                    prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );\n                }\n                secureportENABLE_NON_SECURE_INTERRUPTS();\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n    }\n}\n/*-----------------------------------------------------------*/\n\nsize_t xPortGetFreeHeapSize( void )\n{\n    return xFreeBytesRemaining;\n}\n/*-----------------------------------------------------------*/\n\nsize_t xPortGetMinimumEverFreeHeapSize( void )\n{\n    return xMinimumEverFreeBytesRemaining;\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM33/secure/secure_heap.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef __SECURE_HEAP_H__\n#define __SECURE_HEAP_H__\n\n/* Standard includes. */\n#include <stdlib.h>\n\n/**\n * @brief Allocates memory from heap.\n *\n * @param[in] xWantedSize The size of the memory to be allocated.\n *\n * @return Pointer to the memory region if the allocation is successful, NULL\n * otherwise.\n */\nvoid * pvPortMalloc( size_t xWantedSize );\n\n/**\n * @brief Frees the previously allocated memory.\n *\n * @param[in] pv Pointer to the memory to be freed.\n */\nvoid vPortFree( void * pv );\n\n/**\n * @brief Get the free heap size.\n *\n * @return Free heap size.\n */\nsize_t xPortGetFreeHeapSize( void );\n\n/**\n * @brief Get the minimum ever free heap size.\n *\n * @return Minimum ever free heap size.\n */\nsize_t xPortGetMinimumEverFreeHeapSize( void );\n\n#endif /* __SECURE_HEAP_H__ */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM33/secure/secure_init.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Standard includes. */\n#include <stdint.h>\n\n/* Secure init includes. */\n#include \"secure_init.h\"\n\n/* Secure port macros. */\n#include \"secure_port_macros.h\"\n\n/**\n * @brief Constants required to manipulate the SCB.\n */\n#define secureinitSCB_AIRCR                 ( ( volatile uint32_t * ) 0xe000ed0c )  /* Application Interrupt and Reset Control Register. */\n#define secureinitSCB_AIRCR_VECTKEY_POS     ( 16UL )\n#define secureinitSCB_AIRCR_VECTKEY_MASK    ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )\n#define secureinitSCB_AIRCR_PRIS_POS        ( 14UL )\n#define secureinitSCB_AIRCR_PRIS_MASK       ( 1UL << secureinitSCB_AIRCR_PRIS_POS )\n\n/**\n * @brief Constants required to manipulate the FPU.\n */\n#define secureinitFPCCR                     ( ( volatile uint32_t * ) 0xe000ef34 )  /* Floating Point Context Control Register. */\n#define secureinitFPCCR_LSPENS_POS          ( 29UL )\n#define secureinitFPCCR_LSPENS_MASK         ( 1UL << secureinitFPCCR_LSPENS_POS )\n#define secureinitFPCCR_TS_POS              ( 26UL )\n#define secureinitFPCCR_TS_MASK             ( 1UL << secureinitFPCCR_TS_POS )\n\n#define secureinitNSACR                     ( ( volatile uint32_t * ) 0xe000ed8c )  /* Non-secure Access Control Register. */\n#define secureinitNSACR_CP10_POS            ( 10UL )\n#define secureinitNSACR_CP10_MASK           ( 1UL << secureinitNSACR_CP10_POS )\n#define secureinitNSACR_CP11_POS            ( 11UL )\n#define secureinitNSACR_CP11_MASK           ( 1UL << secureinitNSACR_CP11_POS )\n/*-----------------------------------------------------------*/\n\nsecureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void )\n{\n    uint32_t ulIPSR;\n\n    /* Read the Interrupt Program Status Register (IPSR) value. */\n    secureportREAD_IPSR( ulIPSR );\n\n    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\n     * when the processor is running in the Thread Mode. */\n    if( ulIPSR != 0 )\n    {\n        *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |\n                                   ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |\n                                   ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK );\n    }\n}\n/*-----------------------------------------------------------*/\n\nsecureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )\n{\n    uint32_t ulIPSR;\n\n    /* Read the Interrupt Program Status Register (IPSR) value. */\n    secureportREAD_IPSR( ulIPSR );\n\n    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\n     * when the processor is running in the Thread Mode. */\n    if( ulIPSR != 0 )\n    {\n        /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is\n         * permitted. CP11 should be programmed to the same value as CP10. */\n        *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );\n\n        /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures\n         * that we can enable/disable lazy stacking in port.c file. */\n        *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK );\n\n        /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP\n         * registers (S16-S31) are also pushed to stack on exception entry and\n         * restored on exception return. */\n        *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );\n    }\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM33/secure/secure_init.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef __SECURE_INIT_H__\n#define __SECURE_INIT_H__\n\n/**\n * @brief De-prioritizes the non-secure exceptions.\n *\n * This is needed to ensure that the non-secure PendSV runs at the lowest\n * priority. Context switch is done in the non-secure PendSV handler.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n */\nvoid SecureInit_DePrioritizeNSExceptions( void );\n\n/**\n * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access.\n *\n * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point\n * Registers are not leaked to the non-secure side.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n */\nvoid SecureInit_EnableNSFPUAccess( void );\n\n#endif /* __SECURE_INIT_H__ */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM33/secure/secure_port_macros.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef __SECURE_PORT_MACROS_H__\n#define __SECURE_PORT_MACROS_H__\n\n/**\n * @brief Byte alignment requirements.\n */\n#define secureportBYTE_ALIGNMENT         8\n#define secureportBYTE_ALIGNMENT_MASK    ( 0x0007 )\n\n/**\n * @brief Macro to declare a function as non-secure callable.\n */\n#if defined( __IAR_SYSTEMS_ICC__ )\n    #define secureportNON_SECURE_CALLABLE    __cmse_nonsecure_entry __root\n#else\n    #define secureportNON_SECURE_CALLABLE    __attribute__( ( cmse_nonsecure_entry ) ) __attribute__( ( used ) )\n#endif\n\n/**\n * @brief Set the secure PRIMASK value.\n */\n#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \\\n    __asm volatile ( \"msr primask, %0\" : : \"r\" ( ulPrimaskValue ) : \"memory\" )\n\n/**\n * @brief Set the non-secure PRIMASK value.\n */\n#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \\\n    __asm volatile ( \"msr primask_ns, %0\" : : \"r\" ( ulPrimaskValue ) : \"memory\" )\n\n/**\n * @brief Read the PSP value in the given variable.\n */\n#define secureportREAD_PSP( pucOutCurrentStackPointer ) \\\n    __asm volatile ( \"mrs %0, psp\"  : \"=r\" ( pucOutCurrentStackPointer ) )\n\n/**\n * @brief Set the PSP to the given value.\n */\n#define secureportSET_PSP( pucCurrentStackPointer ) \\\n    __asm volatile ( \"msr psp, %0\" : : \"r\" ( pucCurrentStackPointer ) )\n\n/**\n * @brief Read the PSPLIM value in the given variable.\n */\n#define secureportREAD_PSPLIM( pucOutStackLimit ) \\\n    __asm volatile ( \"mrs %0, psplim\"  : \"=r\" ( pucOutStackLimit ) )\n\n/**\n * @brief Set the PSPLIM to the given value.\n */\n#define secureportSET_PSPLIM( pucStackLimit ) \\\n    __asm volatile ( \"msr psplim, %0\" : : \"r\" ( pucStackLimit ) )\n\n/**\n * @brief Set the NonSecure MSP to the given value.\n */\n#define secureportSET_MSP_NS( pucMainStackPointer ) \\\n    __asm volatile ( \"msr msp_ns, %0\" : : \"r\" ( pucMainStackPointer ) )\n\n/**\n * @brief Set the CONTROL register to the given value.\n */\n#define secureportSET_CONTROL( ulControl ) \\\n    __asm volatile ( \"msr control, %0\" : : \"r\" ( ulControl ) : \"memory\" )\n\n/**\n * @brief Read the Interrupt Program Status Register (IPSR) value in the given\n * variable.\n */\n#define secureportREAD_IPSR( ulIPSR ) \\\n    __asm volatile ( \"mrs %0, ipsr\"  : \"=r\" ( ulIPSR ) )\n\n/**\n * @brief PRIMASK value to enable interrupts.\n */\n#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL     0\n\n/**\n * @brief PRIMASK value to disable interrupts.\n */\n#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL    1\n\n/**\n * @brief Disable secure interrupts.\n */\n#define secureportDISABLE_SECURE_INTERRUPTS()        secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )\n\n/**\n * @brief Disable non-secure interrupts.\n *\n * This effectively disables context switches.\n */\n#define secureportDISABLE_NON_SECURE_INTERRUPTS()    secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )\n\n/**\n * @brief Enable non-secure interrupts.\n */\n#define secureportENABLE_NON_SECURE_INTERRUPTS()     secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL )\n\n/**\n * @brief Assert definition.\n */\n#define secureportASSERT( x )                      \\\n    if( ( x ) == 0 )                               \\\n    {                                              \\\n        secureportDISABLE_SECURE_INTERRUPTS();     \\\n        secureportDISABLE_NON_SECURE_INTERRUPTS(); \\\n        for( ; ; ) {; }                            \\\n    }\n\n#endif /* __SECURE_PORT_MACROS_H__ */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM33_NTZ/non_secure/port.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\n * all the API functions to use the MPU wrappers. That should only be done when\n * task.h is included from an application file. */\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n/* MPU wrappers includes. */\n#include \"mpu_wrappers.h\"\n\n/* Portasm includes. */\n#include \"portasm.h\"\n\n#if ( configENABLE_TRUSTZONE == 1 )\n    /* Secure components includes. */\n    #include \"secure_context.h\"\n    #include \"secure_init.h\"\n#endif /* configENABLE_TRUSTZONE */\n\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/**\n * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only\n * i.e. the processor boots as secure and never jumps to the non-secure side.\n * The Trust Zone support in the port must be disabled in order to run FreeRTOS\n * on the secure side. The following are the valid configuration seetings:\n *\n * 1. Run FreeRTOS on the Secure Side:\n *    configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0\n *\n * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:\n *    configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1\n *\n * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:\n *    configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0\n */\n#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )\n    #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.\n#endif\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the NVIC.\n */\n#define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )\n#define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )\n#define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )\n#define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )\n#define portNVIC_SYSTICK_ENABLE_BIT           ( 1UL << 0UL )\n#define portNVIC_SYSTICK_INT_BIT              ( 1UL << 1UL )\n#define portNVIC_SYSTICK_CLK_BIT              ( 1UL << 2UL )\n#define portNVIC_SYSTICK_COUNT_FLAG_BIT       ( 1UL << 16UL )\n#define portNVIC_PEND_SYSTICK_CLEAR_BIT       ( 1UL << 25UL )\n#define portNVIC_PEND_SYSTICK_SET_BIT         ( 1UL << 26UL )\n#define portMIN_INTERRUPT_PRIORITY            ( 255UL )\n#define portNVIC_PENDSV_PRI                   ( portMIN_INTERRUPT_PRIORITY << 16UL )\n#define portNVIC_SYSTICK_PRI                  ( portMIN_INTERRUPT_PRIORITY << 24UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the SCB.\n */\n#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( volatile uint32_t * ) 0xe000ed24 )\n#define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the FPU.\n */\n#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 )              /* Coprocessor Access Control Register. */\n#define portCPACR_CP10_VALUE    ( 3UL )\n#define portCPACR_CP11_VALUE    portCPACR_CP10_VALUE\n#define portCPACR_CP10_POS      ( 20UL )\n#define portCPACR_CP11_POS      ( 22UL )\n\n#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 )              /* Floating Point Context Control Register. */\n#define portFPCCR_ASPEN_POS     ( 31UL )\n#define portFPCCR_ASPEN_MASK    ( 1UL << portFPCCR_ASPEN_POS )\n#define portFPCCR_LSPEN_POS     ( 30UL )\n#define portFPCCR_LSPEN_MASK    ( 1UL << portFPCCR_LSPEN_POS )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the MPU.\n */\n#define portMPU_TYPE_REG                      ( *( ( volatile uint32_t * ) 0xe000ed90 ) )\n#define portMPU_CTRL_REG                      ( *( ( volatile uint32_t * ) 0xe000ed94 ) )\n#define portMPU_RNR_REG                       ( *( ( volatile uint32_t * ) 0xe000ed98 ) )\n\n#define portMPU_RBAR_REG                      ( *( ( volatile uint32_t * ) 0xe000ed9c ) )\n#define portMPU_RLAR_REG                      ( *( ( volatile uint32_t * ) 0xe000eda0 ) )\n\n#define portMPU_RBAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda4 ) )\n#define portMPU_RLAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda8 ) )\n\n#define portMPU_RBAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edac ) )\n#define portMPU_RLAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edb0 ) )\n\n#define portMPU_RBAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb4 ) )\n#define portMPU_RLAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb8 ) )\n\n#define portMPU_MAIR0_REG                     ( *( ( volatile uint32_t * ) 0xe000edc0 ) )\n#define portMPU_MAIR1_REG                     ( *( ( volatile uint32_t * ) 0xe000edc4 ) )\n\n#define portMPU_RBAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */\n#define portMPU_RLAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */\n\n#define portMPU_MAIR_ATTR0_POS                ( 0UL )\n#define portMPU_MAIR_ATTR0_MASK               ( 0x000000ff )\n\n#define portMPU_MAIR_ATTR1_POS                ( 8UL )\n#define portMPU_MAIR_ATTR1_MASK               ( 0x0000ff00 )\n\n#define portMPU_MAIR_ATTR2_POS                ( 16UL )\n#define portMPU_MAIR_ATTR2_MASK               ( 0x00ff0000 )\n\n#define portMPU_MAIR_ATTR3_POS                ( 24UL )\n#define portMPU_MAIR_ATTR3_MASK               ( 0xff000000 )\n\n#define portMPU_MAIR_ATTR4_POS                ( 0UL )\n#define portMPU_MAIR_ATTR4_MASK               ( 0x000000ff )\n\n#define portMPU_MAIR_ATTR5_POS                ( 8UL )\n#define portMPU_MAIR_ATTR5_MASK               ( 0x0000ff00 )\n\n#define portMPU_MAIR_ATTR6_POS                ( 16UL )\n#define portMPU_MAIR_ATTR6_MASK               ( 0x00ff0000 )\n\n#define portMPU_MAIR_ATTR7_POS                ( 24UL )\n#define portMPU_MAIR_ATTR7_MASK               ( 0xff000000 )\n\n#define portMPU_RLAR_ATTR_INDEX0              ( 0UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX1              ( 1UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX2              ( 2UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX3              ( 3UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX4              ( 4UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX5              ( 5UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX6              ( 6UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX7              ( 7UL << 1UL )\n\n#define portMPU_RLAR_REGION_ENABLE            ( 1UL )\n\n/* Enable privileged access to unmapped region. */\n#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )\n\n/* Enable MPU. */\n#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )\n\n/* Expected value of the portMPU_TYPE register. */\n#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief The maximum 24-bit number.\n *\n * It is needed because the systick is a 24-bit counter.\n */\n#define portMAX_24_BIT_NUMBER       ( 0xffffffUL )\n\n/**\n * @brief A fiddle factor to estimate the number of SysTick counts that would\n * have occurred while the SysTick counter is stopped during tickless idle\n * calculations.\n */\n#define portMISSED_COUNTS_FACTOR    ( 94UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to set up the initial stack.\n */\n#define portINITIAL_XPSR    ( 0x01000000 )\n\n#if ( configRUN_FREERTOS_SECURE_ONLY == 1 )\n\n/**\n * @brief Initial EXC_RETURN value.\n *\n *     FF         FF         FF         FD\n * 1111 1111  1111 1111  1111 1111  1111 1101\n *\n * Bit[6] - 1 --> The exception was taken from the Secure state.\n * Bit[5] - 1 --> Do not skip stacking of additional state context.\n * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\n * Bit[3] - 1 --> Return to the Thread mode.\n * Bit[2] - 1 --> Restore registers from the process stack.\n * Bit[1] - 0 --> Reserved, 0.\n * Bit[0] - 1 --> The exception was taken to the Secure state.\n */\n    #define portINITIAL_EXC_RETURN    ( 0xfffffffd )\n#else\n\n/**\n * @brief Initial EXC_RETURN value.\n *\n *     FF         FF         FF         BC\n * 1111 1111  1111 1111  1111 1111  1011 1100\n *\n * Bit[6] - 0 --> The exception was taken from the Non-Secure state.\n * Bit[5] - 1 --> Do not skip stacking of additional state context.\n * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\n * Bit[3] - 1 --> Return to the Thread mode.\n * Bit[2] - 1 --> Restore registers from the process stack.\n * Bit[1] - 0 --> Reserved, 0.\n * Bit[0] - 0 --> The exception was taken to the Non-Secure state.\n */\n    #define portINITIAL_EXC_RETURN    ( 0xffffffbc )\n#endif /* configRUN_FREERTOS_SECURE_ONLY */\n\n/**\n * @brief CONTROL register privileged bit mask.\n *\n * Bit[0] in CONTROL register tells the privilege:\n *  Bit[0] = 0 ==> The task is privileged.\n *  Bit[0] = 1 ==> The task is not privileged.\n */\n#define portCONTROL_PRIVILEGED_MASK         ( 1UL << 0UL )\n\n/**\n * @brief Initial CONTROL register values.\n */\n#define portINITIAL_CONTROL_UNPRIVILEGED    ( 0x3 )\n#define portINITIAL_CONTROL_PRIVILEGED      ( 0x2 )\n\n/**\n * @brief Let the user override the default SysTick clock rate.  If defined by the\n * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the\n * configuration register.\n */\n#ifndef configSYSTICK_CLOCK_HZ\n    #define configSYSTICK_CLOCK_HZ             ( configCPU_CLOCK_HZ )\n    /* Ensure the SysTick is clocked at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( portNVIC_SYSTICK_CLK_BIT )\n#else\n    /* Select the option to clock SysTick not at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( 0 )\n#endif\n\n/**\n * @brief Let the user override the pre-loading of the initial LR with the\n * address of prvTaskExitError() in case it messes up unwinding of the stack\n * in the debugger.\n */\n#ifdef configTASK_RETURN_ADDRESS\n    #define portTASK_RETURN_ADDRESS    configTASK_RETURN_ADDRESS\n#else\n    #define portTASK_RETURN_ADDRESS    prvTaskExitError\n#endif\n\n/**\n * @brief If portPRELOAD_REGISTERS then registers will be given an initial value\n * when a task is created. This helps in debugging at the cost of code size.\n */\n#define portPRELOAD_REGISTERS    1\n\n/**\n * @brief A task is created without a secure context, and must call\n * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes\n * any secure calls.\n */\n#define portNO_SECURE_CONTEXT    0\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Used to catch tasks that attempt to return from their implementing\n * function.\n */\nstatic void prvTaskExitError( void );\n\n#if ( configENABLE_MPU == 1 )\n\n/**\n * @brief Setup the Memory Protection Unit (MPU).\n */\n    static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\n#endif /* configENABLE_MPU */\n\n#if ( configENABLE_FPU == 1 )\n\n/**\n * @brief Setup the Floating Point Unit (FPU).\n */\n    static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;\n#endif /* configENABLE_FPU */\n\n/**\n * @brief Setup the timer to generate the tick interrupts.\n *\n * The implementation in this file is weak to allow application writers to\n * change the timer used to generate the tick interrupt.\n */\nvoid vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Checks whether the current execution context is interrupt.\n *\n * @return pdTRUE if the current execution context is interrupt, pdFALSE\n * otherwise.\n */\nBaseType_t xPortIsInsideInterrupt( void );\n\n/**\n * @brief Yield the processor.\n */\nvoid vPortYield( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Enter critical section.\n */\nvoid vPortEnterCritical( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Exit from critical section.\n */\nvoid vPortExitCritical( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief SysTick handler.\n */\nvoid SysTick_Handler( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief C part of SVC handler.\n */\nportDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION;\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Each task maintains its own interrupt status in the critical nesting\n * variable.\n */\nPRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;\n\n#if ( configENABLE_TRUSTZONE == 1 )\n\n/**\n * @brief Saved as part of the task context to indicate which context the\n * task is using on the secure side.\n */\n    PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;\n#endif /* configENABLE_TRUSTZONE */\n\n#if ( configUSE_TICKLESS_IDLE == 1 )\n\n/**\n * @brief The number of SysTick increments that make up one tick period.\n */\n    PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0;\n\n/**\n * @brief The maximum number of tick periods that can be suppressed is\n * limited by the 24 bit resolution of the SysTick timer.\n */\n    PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0;\n\n/**\n * @brief Compensate for the CPU cycles that pass while the SysTick is\n * stopped (low power functionality only).\n */\n    PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TICKLESS_IDLE == 1 )\n    __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )\n    {\n        uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;\n        TickType_t xModifiableIdleTime;\n\n        /* Make sure the SysTick reload value does not overflow the counter. */\n        if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\n        {\n            xExpectedIdleTime = xMaximumPossibleSuppressedTicks;\n        }\n\n        /* Enter a critical section but don't use the taskENTER_CRITICAL()\n         * method as that will mask interrupts that should exit sleep mode. */\n        __asm volatile ( \"cpsid i\" ::: \"memory\" );\n        __asm volatile ( \"dsb\" );\n        __asm volatile ( \"isb\" );\n\n        /* If a context switch is pending or a task is waiting for the scheduler\n         * to be unsuspended then abandon the low power entry. */\n        if( eTaskConfirmSleepModeStatus() == eAbortSleep )\n        {\n            /* Re-enable interrupts - see comments above the cpsid instruction\n             * above. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n        }\n        else\n        {\n            /* Stop the SysTick momentarily.  The time the SysTick is stopped for\n             * is accounted for as best it can be, but using the tickless mode will\n             * inevitably result in some tiny drift of the time maintained by the\n             * kernel with respect to calendar time. */\n            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );\n\n            /* Use the SysTick current-value register to determine the number of\n             * SysTick decrements remaining until the next tick interrupt.  If the\n             * current-value register is zero, then there are actually\n             * ulTimerCountsForOneTick decrements remaining, not zero, because the\n             * SysTick requests the interrupt when decrementing from 1 to 0. */\n            ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n\n            if( ulSysTickDecrementsLeft == 0 )\n            {\n                ulSysTickDecrementsLeft = ulTimerCountsForOneTick;\n            }\n\n            /* Calculate the reload value required to wait xExpectedIdleTime\n             * tick periods.  -1 is used because this code normally executes part\n             * way through the first tick period.  But if the SysTick IRQ is now\n             * pending, then clear the IRQ, suppressing the first tick, and correct\n             * the reload value to reflect that the second tick period is already\n             * underway.  The expected idle time is always at least two ticks. */\n            ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );\n\n            if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )\n            {\n                portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;\n                ulReloadValue -= ulTimerCountsForOneTick;\n            }\n\n            if( ulReloadValue > ulStoppedTimerCompensation )\n            {\n                ulReloadValue -= ulStoppedTimerCompensation;\n            }\n\n            /* Set the new reload value. */\n            portNVIC_SYSTICK_LOAD_REG = ulReloadValue;\n\n            /* Clear the SysTick count flag and set the count value back to\n             * zero. */\n            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n            /* Restart SysTick. */\n            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\n\n            /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can\n             * set its parameter to 0 to indicate that its implementation contains\n             * its own wait for interrupt or wait for event instruction, and so wfi\n             * should not be executed again.  However, the original expected idle\n             * time variable must remain unmodified, so a copy is taken. */\n            xModifiableIdleTime = xExpectedIdleTime;\n            configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\n\n            if( xModifiableIdleTime > 0 )\n            {\n                __asm volatile ( \"dsb\" ::: \"memory\" );\n                __asm volatile ( \"wfi\" );\n                __asm volatile ( \"isb\" );\n            }\n\n            configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\n\n            /* Re-enable interrupts to allow the interrupt that brought the MCU\n             * out of sleep mode to execute immediately.  See comments above\n             * the cpsid instruction above. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n            __asm volatile ( \"dsb\" );\n            __asm volatile ( \"isb\" );\n\n            /* Disable interrupts again because the clock is about to be stopped\n             * and interrupts that execute while the clock is stopped will increase\n             * any slippage between the time maintained by the RTOS and calendar\n             * time. */\n            __asm volatile ( \"cpsid i\" ::: \"memory\" );\n            __asm volatile ( \"dsb\" );\n            __asm volatile ( \"isb\" );\n\n            /* Disable the SysTick clock without reading the\n             * portNVIC_SYSTICK_CTRL_REG register to ensure the\n             * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,\n             * the time the SysTick is stopped for is accounted for as best it can\n             * be, but using the tickless mode will inevitably result in some tiny\n             * drift of the time maintained by the kernel with respect to calendar\n             * time*/\n            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );\n\n            /* Determine whether the SysTick has already counted to zero. */\n            if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n            {\n                uint32_t ulCalculatedLoadValue;\n\n                /* The tick interrupt ended the sleep (or is now pending), and\n                 * a new tick period has started.  Reset portNVIC_SYSTICK_LOAD_REG\n                 * with whatever remains of the new tick period. */\n                ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\n\n                /* Don't allow a tiny value, or values that have somehow\n                 * underflowed because the post sleep hook did something\n                 * that took too long or because the SysTick current-value register\n                 * is zero. */\n                if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )\n                {\n                    ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );\n                }\n\n                portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;\n\n                /* As the pending tick will be processed as soon as this\n                 * function exits, the tick value maintained by the tick is stepped\n                 * forward by one less than the time spent waiting. */\n                ulCompleteTickPeriods = xExpectedIdleTime - 1UL;\n            }\n            else\n            {\n                /* Something other than the tick interrupt ended the sleep. */\n\n                /* Use the SysTick current-value register to determine the\n                 * number of SysTick decrements remaining until the expected idle\n                 * time would have ended. */\n                ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n                #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )\n                {\n                    /* If the SysTick is not using the core clock, the current-\n                     * value register might still be zero here.  In that case, the\n                     * SysTick didn't load from the reload register, and there are\n                     * ulReloadValue decrements remaining in the expected idle\n                     * time, not zero. */\n                    if( ulSysTickDecrementsLeft == 0 )\n                    {\n                        ulSysTickDecrementsLeft = ulReloadValue;\n                    }\n                }\n                #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */\n\n                /* Work out how long the sleep lasted rounded to complete tick\n                 * periods (not the ulReload value which accounted for part\n                 * ticks). */\n                ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;\n\n                /* How many complete tick periods passed while the processor\n                 * was waiting? */\n                ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;\n\n                /* The reload value is set to whatever fraction of a single tick\n                 * period remains. */\n                portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;\n            }\n\n            /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,\n             * then set portNVIC_SYSTICK_LOAD_REG back to its standard value.  If\n             * the SysTick is not using the core clock, temporarily configure it to\n             * use the core clock.  This configuration forces the SysTick to load\n             * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next\n             * cycle of the other clock.  Then portNVIC_SYSTICK_LOAD_REG is ready\n             * to receive the standard value immediately. */\n            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n            portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n            #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )\n            {\n                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n            }\n            #else\n            {\n                /* The temporary usage of the core clock has served its purpose,\n                 * as described above.  Resume usage of the other clock. */\n                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\n\n                if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n                {\n                    /* The partial tick period already ended.  Be sure the SysTick\n                     * counts it only once. */\n                    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;\n                }\n\n                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n            }\n            #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */\n\n            /* Step the tick to account for any tick periods that elapsed. */\n            vTaskStepTick( ulCompleteTickPeriods );\n\n            /* Exit with interrupts enabled. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n        }\n    }\n#endif /* configUSE_TICKLESS_IDLE */\n/*-----------------------------------------------------------*/\n\n__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Calculate the constants required to configure the tick interrupt. */\n    #if ( configUSE_TICKLESS_IDLE == 1 )\n    {\n        ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );\n        xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;\n        ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\n    }\n    #endif /* configUSE_TICKLESS_IDLE */\n\n    /* Stop and reset the SysTick. */\n    portNVIC_SYSTICK_CTRL_REG = 0UL;\n    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n    /* Configure SysTick to interrupt at the requested rate. */\n    portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\n    portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvTaskExitError( void )\n{\n    volatile uint32_t ulDummy = 0UL;\n\n    /* A function that implements a task must not exit or attempt to return to\n     * its caller as there is nothing to return to. If a task wants to exit it\n     * should instead call vTaskDelete( NULL ). Artificially force an assert()\n     * to be triggered if configASSERT() is defined, then stop here so\n     * application writers can catch the error. */\n    configASSERT( ulCriticalNesting == ~0UL );\n    portDISABLE_INTERRUPTS();\n\n    while( ulDummy == 0 )\n    {\n        /* This file calls prvTaskExitError() after the scheduler has been\n         * started to remove a compiler warning about the function being\n         * defined but never called.  ulDummy is used purely to quieten other\n         * warnings about code appearing after this function is called - making\n         * ulDummy volatile makes the compiler think the function could return\n         * and therefore not output an 'unreachable code' warning for code that\n         * appears after it. */\n    }\n}\n/*-----------------------------------------------------------*/\n\n#if ( configENABLE_MPU == 1 )\n    static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */\n    {\n        #if defined( __ARMCC_VERSION )\n\n            /* Declaration when these variable are defined in code instead of being\n             * exported from linker scripts. */\n            extern uint32_t * __privileged_functions_start__;\n            extern uint32_t * __privileged_functions_end__;\n            extern uint32_t * __syscalls_flash_start__;\n            extern uint32_t * __syscalls_flash_end__;\n            extern uint32_t * __unprivileged_flash_start__;\n            extern uint32_t * __unprivileged_flash_end__;\n            extern uint32_t * __privileged_sram_start__;\n            extern uint32_t * __privileged_sram_end__;\n        #else /* if defined( __ARMCC_VERSION ) */\n            /* Declaration when these variable are exported from linker scripts. */\n            extern uint32_t __privileged_functions_start__[];\n            extern uint32_t __privileged_functions_end__[];\n            extern uint32_t __syscalls_flash_start__[];\n            extern uint32_t __syscalls_flash_end__[];\n            extern uint32_t __unprivileged_flash_start__[];\n            extern uint32_t __unprivileged_flash_end__[];\n            extern uint32_t __privileged_sram_start__[];\n            extern uint32_t __privileged_sram_end__[];\n        #endif /* defined( __ARMCC_VERSION ) */\n\n        /* The only permitted number of regions are 8 or 16. */\n        configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );\n\n        /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */\n        configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );\n\n        /* Check that the MPU is present. */\n        if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )\n        {\n            /* MAIR0 - Index 0. */\n            portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\n            /* MAIR0 - Index 1. */\n            portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\n\n            /* Setup privileged flash as Read Only so that privileged tasks can\n             * read it but not modify. */\n            portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_PRIVILEGED_READ_ONLY );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Setup unprivileged flash as Read Only by both privileged and\n             * unprivileged tasks. All tasks can read it but no-one can modify. */\n            portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_READ_ONLY );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Setup unprivileged syscalls flash as Read Only by both privileged\n             * and unprivileged tasks. All tasks can read it but no-one can modify. */\n            portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_READ_ONLY );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Setup RAM containing kernel data for privileged access only. */\n            portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\n                               ( portMPU_REGION_EXECUTE_NEVER );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Enable mem fault. */\n            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;\n\n            /* Enable MPU with privileged background access i.e. unmapped\n             * regions have privileged access. */\n            portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );\n        }\n    }\n#endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\n#if ( configENABLE_FPU == 1 )\n    static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */\n    {\n        #if ( configENABLE_TRUSTZONE == 1 )\n        {\n            /* Enable non-secure access to the FPU. */\n            SecureInit_EnableNSFPUAccess();\n        }\n        #endif /* configENABLE_TRUSTZONE */\n\n        /* CP10 = 11 ==> Full access to FPU i.e. both privileged and\n         * unprivileged code should be able to access FPU. CP11 should be\n         * programmed to the same value as CP10. */\n        *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |\n                            ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )\n                            );\n\n        /* ASPEN = 1 ==> Hardware should automatically preserve floating point\n         * context on exception entry and restore on exception return.\n         * LSPEN = 1 ==> Enable lazy context save of FP state. */\n        *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );\n    }\n#endif /* configENABLE_FPU */\n/*-----------------------------------------------------------*/\n\nvoid vPortYield( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Set a PendSV to request a context switch. */\n    portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\n\n    /* Barriers are normally not required but do ensure the code is\n     * completely within the specified behaviour for the architecture. */\n    __asm volatile ( \"dsb\" ::: \"memory\" );\n    __asm volatile ( \"isb\" );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */\n{\n    portDISABLE_INTERRUPTS();\n    ulCriticalNesting++;\n\n    /* Barriers are normally not required but do ensure the code is\n     * completely within the specified behaviour for the architecture. */\n    __asm volatile ( \"dsb\" ::: \"memory\" );\n    __asm volatile ( \"isb\" );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */\n{\n    configASSERT( ulCriticalNesting );\n    ulCriticalNesting--;\n\n    if( ulCriticalNesting == 0 )\n    {\n        portENABLE_INTERRUPTS();\n    }\n}\n/*-----------------------------------------------------------*/\n\nvoid SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */\n{\n    uint32_t ulPreviousMask;\n\n    ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();\n    {\n        /* Increment the RTOS tick. */\n        if( xTaskIncrementTick() != pdFALSE )\n        {\n            /* Pend a context switch. */\n            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\n        }\n    }\n    portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */\n{\n    #if ( configENABLE_MPU == 1 )\n        #if defined( __ARMCC_VERSION )\n\n            /* Declaration when these variable are defined in code instead of being\n             * exported from linker scripts. */\n            extern uint32_t * __syscalls_flash_start__;\n            extern uint32_t * __syscalls_flash_end__;\n        #else\n            /* Declaration when these variable are exported from linker scripts. */\n            extern uint32_t __syscalls_flash_start__[];\n            extern uint32_t __syscalls_flash_end__[];\n        #endif /* defined( __ARMCC_VERSION ) */\n    #endif /* configENABLE_MPU */\n\n    uint32_t ulPC;\n\n    #if ( configENABLE_TRUSTZONE == 1 )\n        uint32_t ulR0, ulR1;\n        extern TaskHandle_t pxCurrentTCB;\n        #if ( configENABLE_MPU == 1 )\n            uint32_t ulControl, ulIsTaskPrivileged;\n        #endif /* configENABLE_MPU */\n    #endif /* configENABLE_TRUSTZONE */\n    uint8_t ucSVCNumber;\n\n    /* Register are stored on the stack in the following order - R0, R1, R2, R3,\n     * R12, LR, PC, xPSR. */\n    ulPC = pulCallerStackAddress[ 6 ];\n    ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];\n\n    switch( ucSVCNumber )\n    {\n        #if ( configENABLE_TRUSTZONE == 1 )\n            case portSVC_ALLOCATE_SECURE_CONTEXT:\n\n                /* R0 contains the stack size passed as parameter to the\n                 * vPortAllocateSecureContext function. */\n                ulR0 = pulCallerStackAddress[ 0 ];\n\n                #if ( configENABLE_MPU == 1 )\n                {\n                    /* Read the CONTROL register value. */\n                    __asm volatile ( \"mrs %0, control\"  : \"=r\" ( ulControl ) );\n\n                    /* The task that raised the SVC is privileged if Bit[0]\n                     * in the CONTROL register is 0. */\n                    ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );\n\n                    /* Allocate and load a context for the secure task. */\n                    xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );\n                }\n                #else /* if ( configENABLE_MPU == 1 ) */\n                {\n                    /* Allocate and load a context for the secure task. */\n                    xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );\n                }\n                #endif /* configENABLE_MPU */\n\n                configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );\n                SecureContext_LoadContext( xSecureContext, pxCurrentTCB );\n                break;\n\n            case portSVC_FREE_SECURE_CONTEXT:\n\n                /* R0 contains TCB being freed and R1 contains the secure\n                 * context handle to be freed. */\n                ulR0 = pulCallerStackAddress[ 0 ];\n                ulR1 = pulCallerStackAddress[ 1 ];\n\n                /* Free the secure context. */\n                SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );\n                break;\n        #endif /* configENABLE_TRUSTZONE */\n\n        case portSVC_START_SCHEDULER:\n            #if ( configENABLE_TRUSTZONE == 1 )\n            {\n                /* De-prioritize the non-secure exceptions so that the\n                 * non-secure pendSV runs at the lowest priority. */\n                SecureInit_DePrioritizeNSExceptions();\n\n                /* Initialize the secure context management system. */\n                SecureContext_Init();\n            }\n            #endif /* configENABLE_TRUSTZONE */\n\n            #if ( configENABLE_FPU == 1 )\n            {\n                /* Setup the Floating Point Unit (FPU). */\n                prvSetupFPU();\n            }\n            #endif /* configENABLE_FPU */\n\n            /* Setup the context of the first task so that the first task starts\n             * executing. */\n            vRestoreContextOfFirstTask();\n            break;\n\n            #if ( configENABLE_MPU == 1 )\n                case portSVC_RAISE_PRIVILEGE:\n\n                    /* Only raise the privilege, if the svc was raised from any of\n                     * the system calls. */\n                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&\n                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )\n                    {\n                        vRaisePrivilege();\n                    }\n                    break;\n            #endif /* configENABLE_MPU */\n\n        default:\n            /* Incorrect SVC call. */\n            configASSERT( pdFALSE );\n    }\n}\n/*-----------------------------------------------------------*/\n/* *INDENT-OFF* */\n#if ( configENABLE_MPU == 1 )\n    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,\n                                         StackType_t * pxEndOfStack,\n                                         TaskFunction_t pxCode,\n                                         void * pvParameters,\n                                         BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */\n#else\n    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,\n                                         StackType_t * pxEndOfStack,\n                                         TaskFunction_t pxCode,\n                                         void * pvParameters ) /* PRIVILEGED_FUNCTION */\n#endif /* configENABLE_MPU */\n/* *INDENT-ON* */\n{\n    /* Simulate the stack frame as it would be created by a context switch\n     * interrupt. */\n    #if ( portPRELOAD_REGISTERS == 0 )\n    {\n        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\n        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\n        pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */\n        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */\n        pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */\n        *pxTopOfStack = portINITIAL_EXC_RETURN;\n\n        #if ( configENABLE_MPU == 1 )\n        {\n            pxTopOfStack--;\n\n            if( xRunPrivileged == pdTRUE )\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n            else\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n        }\n        #endif /* configENABLE_MPU */\n\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\n\n        #if ( configENABLE_TRUSTZONE == 1 )\n        {\n            pxTopOfStack--;\n            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\n        }\n        #endif /* configENABLE_TRUSTZONE */\n    }\n    #else /* portPRELOAD_REGISTERS */\n    {\n        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\n        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04 */\n        pxTopOfStack--;\n        *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN */\n\n        #if ( configENABLE_MPU == 1 )\n        {\n            pxTopOfStack--;\n\n            if( xRunPrivileged == pdTRUE )\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n            else\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n        }\n        #endif /* configENABLE_MPU */\n\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\n\n        #if ( configENABLE_TRUSTZONE == 1 )\n        {\n            pxTopOfStack--;\n            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\n        }\n        #endif /* configENABLE_TRUSTZONE */\n    }\n    #endif /* portPRELOAD_REGISTERS */\n\n    return pxTopOfStack;\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Make PendSV, CallSV and SysTick the same priority as the kernel. */\n    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;\n    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;\n\n    #if ( configENABLE_MPU == 1 )\n    {\n        /* Setup the Memory Protection Unit (MPU). */\n        prvSetupMPU();\n    }\n    #endif /* configENABLE_MPU */\n\n    /* Start the timer that generates the tick ISR. Interrupts are disabled\n     * here already. */\n    vPortSetupTimerInterrupt();\n\n    /* Initialize the critical nesting count ready for the first task. */\n    ulCriticalNesting = 0;\n\n    /* Start the first task. */\n    vStartFirstTask();\n\n    /* Should never get here as the tasks will now be executing. Call the task\n     * exit error function to prevent compiler warnings about a static function\n     * not being called in the case that the application writer overrides this\n     * functionality by defining configTASK_RETURN_ADDRESS. Call\n     * vTaskSwitchContext() so link time optimization does not remove the\n     * symbol. */\n    vTaskSwitchContext();\n    prvTaskExitError();\n\n    /* Should not get here. */\n    return 0;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Not implemented in ports where there is nothing to return to.\n     * Artificially force an assert. */\n    configASSERT( ulCriticalNesting == 1000UL );\n}\n/*-----------------------------------------------------------*/\n\n#if ( configENABLE_MPU == 1 )\n    void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,\n                                    const struct xMEMORY_REGION * const xRegions,\n                                    StackType_t * pxBottomOfStack,\n                                    uint32_t ulStackDepth )\n    {\n        uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;\n        int32_t lIndex = 0;\n\n        #if defined( __ARMCC_VERSION )\n\n            /* Declaration when these variable are defined in code instead of being\n             * exported from linker scripts. */\n            extern uint32_t * __privileged_sram_start__;\n            extern uint32_t * __privileged_sram_end__;\n        #else\n            /* Declaration when these variable are exported from linker scripts. */\n            extern uint32_t __privileged_sram_start__[];\n            extern uint32_t __privileged_sram_end__[];\n        #endif /* defined( __ARMCC_VERSION ) */\n\n        /* Setup MAIR0. */\n        xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\n        xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\n\n        /* This function is called automatically when the task is created - in\n         * which case the stack region parameters will be valid.  At all other\n         * times the stack parameters will not be valid and it is assumed that\n         * the stack region has already been configured. */\n        if( ulStackDepth > 0 )\n        {\n            ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;\n            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;\n\n            /* If the stack is within the privileged SRAM, do not protect it\n             * using a separate MPU region. This is needed because privileged\n             * SRAM is already protected using an MPU region and ARMv8-M does\n             * not allow overlapping MPU regions. */\n            if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) &&\n                ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) )\n            {\n                xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0;\n                xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0;\n            }\n            else\n            {\n                /* Define the region that allows access to the stack. */\n                ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK;\n                ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\n\n                xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |\n                                                             ( portMPU_REGION_NON_SHAREABLE ) |\n                                                             ( portMPU_REGION_READ_WRITE ) |\n                                                             ( portMPU_REGION_EXECUTE_NEVER );\n\n                xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) |\n                                                             ( portMPU_RLAR_ATTR_INDEX0 ) |\n                                                             ( portMPU_RLAR_REGION_ENABLE );\n            }\n        }\n\n        /* User supplied configurable regions. */\n        for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )\n        {\n            /* If xRegions is NULL i.e. the task has not specified any MPU\n             * region, the else part ensures that all the configurable MPU\n             * regions are invalidated. */\n            if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )\n            {\n                /* Translate the generic region definition contained in xRegions\n                 * into the ARMv8 specific MPU settings that are then stored in\n                 * xMPUSettings. */\n                ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;\n                ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;\n                ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\n\n                /* Start address. */\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |\n                                                                          ( portMPU_REGION_NON_SHAREABLE );\n\n                /* RO/RW. */\n                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )\n                {\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );\n                }\n                else\n                {\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );\n                }\n\n                /* XN. */\n                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )\n                {\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );\n                }\n\n                /* End Address. */\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |\n                                                                          ( portMPU_RLAR_REGION_ENABLE );\n\n                /* Normal memory/ Device memory. */\n                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )\n                {\n                    /* Attr1 in MAIR0 is configured as device memory. */\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;\n                }\n                else\n                {\n                    /* Attr0 in MAIR0 is configured as normal memory. */\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;\n                }\n            }\n            else\n            {\n                /* Invalidate the region. */\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;\n            }\n\n            lIndex++;\n        }\n    }\n#endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\nBaseType_t xPortIsInsideInterrupt( void )\n{\n    uint32_t ulCurrentInterrupt;\n    BaseType_t xReturn;\n\n    /* Obtain the number of the currently executing interrupt. Interrupt Program\n     * Status Register (IPSR) holds the exception number of the currently-executing\n     * exception or zero for Thread mode.*/\n    __asm volatile ( \"mrs %0, ipsr\" : \"=r\" ( ulCurrentInterrupt )::\"memory\" );\n\n    if( ulCurrentInterrupt == 0 )\n    {\n        xReturn = pdFALSE;\n    }\n    else\n    {\n        xReturn = pdTRUE;\n    }\n\n    return xReturn;\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Standard includes. */\n#include <stdint.h>\n\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION\n * is defined correctly and privileged functions are placed in correct sections. */\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/* Portasm includes. */\n#include \"portasm.h\"\n\n/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the\n * header files. */\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\nvoid vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr  r2, pxCurrentTCBConst2\t\t\t\t\t\t\\n\"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n        \"\tldr  r1, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Read pxCurrentTCB. */\n        \"\tldr  r0, [r1]\t\t\t\t\t\t\t\t\t\\n\"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"\tdmb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Complete outstanding transfers before disabling MPU. */\n            \"\tldr r2, xMPUCTRLConst2\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n            \"\tldr r4, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Read the value of MPU_CTRL. */\n            \"\tbic r4, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\n            \"\tstr r4, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Disable MPU. */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tadds r1, #4\t\t\t\t\t\t\t\t\t\t\\n\"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\n            \"\tldr  r3, [r1]\t\t\t\t\t\t\t\t\t\\n\"/* r3 = *r1 i.e. r3 = MAIR0. */\n            \"\tldr  r2, xMAIR0Const2\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000edc0 [Location of MAIR0]. */\n            \"\tstr  r3, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Program MAIR0. */\n            \"\tldr  r2, xRNRConst2\t\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed98 [Location of RNR]. */\n            \"\tmovs r3, #4\t\t\t\t\t\t\t\t\t\t\\n\"/* r3 = 4. */\n            \"\tstr  r3, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 4. */\n            \"\tadds r1, #4\t\t\t\t\t\t\t\t\t\t\\n\"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\n            \"\tldr  r2, xRBARConst2\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed9c [Location of RBAR]. */\n            \"\tldmia r1!, {r4-r11}\t\t\t\t\t\t\t\t\\n\"/* Read 4 set of RBAR/RLAR registers from TCB. */\n            \"\tstmia r2!, {r4-r11}\t\t\t\t\t\t\t\t\\n\"/* Write 4 set of RBAR/RLAR registers using alias registers. */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            #if ( configTOTAL_MPU_REGIONS == 16 )\n            \"\tldr  r2, xRNRConst2\t\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed98 [Location of RNR]. */\n            \"\tmovs r3, #8\t\t\t\t\t\t\t\t\t\t\\n\"/* r3 = 8. */\n            \"\tstr  r3, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 8. */\n            \"\tldr  r2, xRBARConst2\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed9c [Location of RBAR]. */\n            \"\tldmia r1!, {r4-r11}\t\t\t\t\t\t\t\t\\n\"/* Read 4 set of RBAR/RLAR registers from TCB. */\n            \"\tstmia r2!, {r4-r11}\t\t\t\t\t\t\t\t\\n\"/* Write 4 set of RBAR/RLAR registers using alias registers. */\n            \"\tldr  r2, xRNRConst2\t\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed98 [Location of RNR]. */\n            \"\tmovs r3, #12\t\t\t\t\t\t\t\t\t\\n\"/* r3 = 12. */\n            \"\tstr  r3, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 12. */\n            \"\tldr  r2, xRBARConst2\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed9c [Location of RBAR]. */\n            \"\tldmia r1!, {r4-r11}\t\t\t\t\t\t\t\t\\n\"/* Read 4 set of RBAR/RLAR registers from TCB. */\n            \"\tstmia r2!, {r4-r11}\t\t\t\t\t\t\t\t\\n\"/* Write 4 set of RBAR/RLAR registers using alias registers. */\n            #endif /* configTOTAL_MPU_REGIONS == 16 */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tldr r2, xMPUCTRLConst2\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n            \"\tldr r4, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Read the value of MPU_CTRL. */\n            \"\torr r4, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\n            \"\tstr r4, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Enable MPU. */\n            \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Force memory writes before continuing. */\n        #endif /* configENABLE_MPU */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"\tldm  r0!, {r1-r3}\t\t\t\t\t\t\t\t\\n\"/* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */\n            \"\tmsr  psplim, r1\t\t\t\t\t\t\t\t\t\\n\"/* Set this task's PSPLIM value. */\n            \"\tmsr  control, r2\t\t\t\t\t\t\t\t\\n\"/* Set this task's CONTROL value. */\n            \"\tadds r0, #32\t\t\t\t\t\t\t\t\t\\n\"/* Discard everything up to r0. */\n            \"\tmsr  psp, r0\t\t\t\t\t\t\t\t\t\\n\"/* This is now the new top of stack to use in the task. */\n            \"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tmov  r0, #0\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tmsr  basepri, r0\t\t\t\t\t\t\t\t\\n\"/* Ensure that interrupts are enabled when the first task starts. */\n            \"\tbx   r3\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Finally, branch to EXC_RETURN. */\n        #else /* configENABLE_MPU */\n            \"\tldm  r0!, {r1-r2}\t\t\t\t\t\t\t\t\\n\"/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */\n            \"\tmsr  psplim, r1\t\t\t\t\t\t\t\t\t\\n\"/* Set this task's PSPLIM value. */\n            \"\tmovs r1, #2\t\t\t\t\t\t\t\t\t\t\\n\"/* r1 = 2. */\n            \"\tmsr  CONTROL, r1\t\t\t\t\t\t\t\t\\n\"/* Switch to use PSP in the thread mode. */\n            \"\tadds r0, #32\t\t\t\t\t\t\t\t\t\\n\"/* Discard everything up to r0. */\n            \"\tmsr  psp, r0\t\t\t\t\t\t\t\t\t\\n\"/* This is now the new top of stack to use in the task. */\n            \"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tmov  r0, #0\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tmsr  basepri, r0\t\t\t\t\t\t\t\t\\n\"/* Ensure that interrupts are enabled when the first task starts. */\n            \"\tbx   r2\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Finally, branch to EXC_RETURN. */\n        #endif /* configENABLE_MPU */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.align 4\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"pxCurrentTCBConst2: .word pxCurrentTCB\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"xMPUCTRLConst2: .word 0xe000ed94\t\t\t\t\t\\n\"\n            \"xMAIR0Const2: .word 0xe000edc0\t\t\t\t\t\t\\n\"\n            \"xRNRConst2: .word 0xe000ed98\t\t\t\t\t\t\\n\"\n            \"xRBARConst2: .word 0xe000ed9c\t\t\t\t\t\t\\n\"\n        #endif /* configENABLE_MPU */\n    );\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrs r0, control\t\t\t\t\t\t\t\t\t\\n\"/* r0 = CONTROL. */\n        \"\ttst r0, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\n        \"\tite ne\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmovne r0, #0\t\t\t\t\t\t\t\t\t\\n\"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\n        \"\tmoveq r0, #1\t\t\t\t\t\t\t\t\t\\n\"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return. */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.align 4\t\t\t\t\t\t\t\t\t\t\\n\"\n        ::: \"r0\", \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrs  r0, control\t\t\t\t\t\t\t\t\\n\"/* Read the CONTROL register. */\n        \"\tbic r0, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* Clear the bit 0. */\n        \"\tmsr  control, r0\t\t\t\t\t\t\t\t\\n\"/* Write back the new CONTROL value. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return to the caller. */\n        ::: \"r0\", \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vResetPrivilege( void ) /* __attribute__ (( naked )) */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrs r0, control\t\t\t\t\t\t\t\t\t\\n\"/* r0 = CONTROL. */\n        \"\torr r0, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* r0 = r0 | 1. */\n        \"\tmsr control, r0\t\t\t\t\t\t\t\t\t\\n\"/* CONTROL = r0. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return to the caller. */\n        ::: \"r0\", \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r0, xVTORConst\t\t\t\t\t\t\t\t\\n\"/* Use the NVIC offset register to locate the stack. */\n        \"\tldr r0, [r0]\t\t\t\t\t\t\t\t\t\\n\"/* Read the VTOR register which gives the address of vector table. */\n        \"\tldr r0, [r0]\t\t\t\t\t\t\t\t\t\\n\"/* The first entry in vector table is stack pointer. */\n        \"\tmsr msp, r0\t\t\t\t\t\t\t\t\t\t\\n\"/* Set the MSP back to the start of the stack. */\n        \"\tcpsie i\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Globally enable interrupts. */\n        \"\tcpsie f\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tsvc %0\t\t\t\t\t\t\t\t\t\t\t\\n\"/* System call to start the first task. */\n        \"\tnop\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"   .align 4\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"xVTORConst: .word 0xe000ed08\t\t\t\t\t\t\\n\"\n        ::\"i\" ( portSVC_START_SCHEDULER ) : \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nuint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrs r0, basepri\t\t\t\t\t\t\t\t\t\\n\"/* r0 = basepri. Return original basepri value. */\n        \"\tmov r1, %0\t\t\t\t\t\t\t\t\t\t\\n\"/* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */\n        \"\tmsr basepri, r1\t\t\t\t\t\t\t\t\t\\n\"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */\n        \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return. */\n        ::\"i\" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmsr basepri, r0\t\t\t\t\t\t\t\t\t\\n\"/* basepri = ulMask. */\n        \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return. */\n        ::: \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrs r0, psp\t\t\t\t\t\t\t\t\t\t\\n\"/* Read PSP in r0. */\n        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )\n            \"\ttst lr, #0x10\t\t\t\t\t\t\t\t\t\\n\"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */\n            \"\tit eq\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tvstmdbeq r0!, {s16-s31}\t\t\t\t\t\t\t\\n\"/* Store the additional FP context registers which are not saved automatically. */\n        #endif /* configENABLE_FPU || configENABLE_MVE */\n        #if ( configENABLE_MPU == 1 )\n            \"\tmrs r1, psplim\t\t\t\t\t\t\t\t\t\\n\"/* r1 = PSPLIM. */\n            \"\tmrs r2, control\t\t\t\t\t\t\t\t\t\\n\"/* r2 = CONTROL. */\n            \"\tmov r3, lr\t\t\t\t\t\t\t\t\t\t\\n\"/* r3 = LR/EXC_RETURN. */\n            \"\tstmdb r0!, {r1-r11}\t\t\t\t\t\t\t\t\\n\"/* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */\n        #else /* configENABLE_MPU */\n            \"\tmrs r2, psplim\t\t\t\t\t\t\t\t\t\\n\"/* r2 = PSPLIM. */\n            \"\tmov r3, lr\t\t\t\t\t\t\t\t\t\t\\n\"/* r3 = LR/EXC_RETURN. */\n            \"\tstmdb r0!, {r2-r11}\t\t\t\t\t\t\t\t\\n\"/* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */\n        #endif /* configENABLE_MPU */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r2, pxCurrentTCBConst\t\t\t\t\t\t\\n\"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n        \"\tldr r1, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Read pxCurrentTCB. */\n        \"\tstr r0, [r1]\t\t\t\t\t\t\t\t\t\\n\"/* Save the new top of stack in TCB. */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmov r0, %0\t\t\t\t\t\t\t\t\t\t\\n\"/* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */\n        \"\tmsr basepri, r0\t\t\t\t\t\t\t\t\t\\n\"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */\n        \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tbl vTaskSwitchContext\t\t\t\t\t\t\t\\n\"\n        \"\tmov r0, #0\t\t\t\t\t\t\t\t\t\t\\n\"/* r0 = 0. */\n        \"\tmsr basepri, r0\t\t\t\t\t\t\t\t\t\\n\"/* Enable interrupts. */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r2, pxCurrentTCBConst\t\t\t\t\t\t\\n\"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n        \"\tldr r1, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Read pxCurrentTCB. */\n        \"\tldr r0, [r1]\t\t\t\t\t\t\t\t\t\\n\"/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"\tdmb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Complete outstanding transfers before disabling MPU. */\n            \"\tldr r2, xMPUCTRLConst\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n            \"\tldr r4, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Read the value of MPU_CTRL. */\n            \"\tbic r4, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\n            \"\tstr r4, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Disable MPU. */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tadds r1, #4\t\t\t\t\t\t\t\t\t\t\\n\"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\n            \"\tldr r3, [r1]\t\t\t\t\t\t\t\t\t\\n\"/* r3 = *r1 i.e. r3 = MAIR0. */\n            \"\tldr r2, xMAIR0Const\t\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000edc0 [Location of MAIR0]. */\n            \"\tstr r3, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Program MAIR0. */\n            \"\tldr r2, xRNRConst\t\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed98 [Location of RNR]. */\n            \"\tmovs r3, #4\t\t\t\t\t\t\t\t\t\t\\n\"/* r3 = 4. */\n            \"\tstr r3, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 4. */\n            \"\tadds r1, #4\t\t\t\t\t\t\t\t\t\t\\n\"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\n            \"\tldr r2, xRBARConst\t\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed9c [Location of RBAR]. */\n            \"\tldmia r1!, {r4-r11}\t\t\t\t\t\t\t\t\\n\"/* Read 4 sets of RBAR/RLAR registers from TCB. */\n            \"\tstmia r2!, {r4-r11}\t\t\t\t\t\t\t\t\\n\"/* Write 4 set of RBAR/RLAR registers using alias registers. */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            #if ( configTOTAL_MPU_REGIONS == 16 )\n            \"\tldr r2, xRNRConst\t\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed98 [Location of RNR]. */\n            \"\tmovs r3, #8\t\t\t\t\t\t\t\t\t\t\\n\"/* r3 = 8. */\n            \"\tstr r3, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 8. */\n            \"\tldr r2, xRBARConst\t\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed9c [Location of RBAR]. */\n            \"\tldmia r1!, {r4-r11}\t\t\t\t\t\t\t\t\\n\"/* Read 4 sets of RBAR/RLAR registers from TCB. */\n            \"\tstmia r2!, {r4-r11}\t\t\t\t\t\t\t\t\\n\"/* Write 4 set of RBAR/RLAR registers using alias registers. */\n            \"\tldr r2, xRNRConst\t\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed98 [Location of RNR]. */\n            \"\tmovs r3, #12\t\t\t\t\t\t\t\t\t\\n\"/* r3 = 12. */\n            \"\tstr r3, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 12. */\n            \"\tldr r2, xRBARConst\t\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed9c [Location of RBAR]. */\n            \"\tldmia r1!, {r4-r11}\t\t\t\t\t\t\t\t\\n\"/* Read 4 sets of RBAR/RLAR registers from TCB. */\n            \"\tstmia r2!, {r4-r11}\t\t\t\t\t\t\t\t\\n\"/* Write 4 set of RBAR/RLAR registers using alias registers. */\n            #endif /* configTOTAL_MPU_REGIONS == 16 */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tldr r2, xMPUCTRLConst\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n            \"\tldr r4, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Read the value of MPU_CTRL. */\n            \"\torr r4, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\n            \"\tstr r4, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Enable MPU. */\n            \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Force memory writes before continuing. */\n        #endif /* configENABLE_MPU */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"\tldmia r0!, {r1-r11}\t\t\t\t\t\t\t\t\\n\"/* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */\n        #else /* configENABLE_MPU */\n            \"\tldmia r0!, {r2-r11}\t\t\t\t\t\t\t\t\\n\"/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */\n        #endif /* configENABLE_MPU */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )\n            \"\ttst r3, #0x10\t\t\t\t\t\t\t\t\t\\n\"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */\n            \"\tit eq\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tvldmiaeq r0!, {s16-s31}\t\t\t\t\t\t\t\\n\"/* Restore the additional FP context registers which are not restored automatically. */\n        #endif /* configENABLE_FPU || configENABLE_MVE */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"\tmsr psplim, r1\t\t\t\t\t\t\t\t\t\\n\"/* Restore the PSPLIM register value for the task. */\n            \"\tmsr control, r2\t\t\t\t\t\t\t\t\t\\n\"/* Restore the CONTROL register value for the task. */\n        #else /* configENABLE_MPU */\n            \"\tmsr psplim, r2\t\t\t\t\t\t\t\t\t\\n\"/* Restore the PSPLIM register value for the task. */\n        #endif /* configENABLE_MPU */\n        \"\tmsr psp, r0\t\t\t\t\t\t\t\t\t\t\\n\"/* Remember the new top of stack for the task. */\n        \"\tbx r3\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.align 4\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"pxCurrentTCBConst: .word pxCurrentTCB\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"xMPUCTRLConst: .word 0xe000ed94\t\t\t\t\t\\n\"\n            \"xMAIR0Const: .word 0xe000edc0\t\t\t\t\t\t\\n\"\n            \"xRNRConst: .word 0xe000ed98\t\t\t\t\t\t\\n\"\n            \"xRBARConst: .word 0xe000ed9c\t\t\t\t\t\t\\n\"\n        #endif /* configENABLE_MPU */\n        ::\"i\" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\ttst lr, #4\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tite eq\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrseq r0, msp\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrsne r0, psp\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r1, svchandler_address_const\t\t\t\t\\n\"\n        \"\tbx r1\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.align 4\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"svchandler_address_const: .word vPortSVCHandler_C\t\\n\"\n    );\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef __PORT_ASM_H__\n#define __PORT_ASM_H__\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n\n/* MPU wrappers includes. */\n#include \"mpu_wrappers.h\"\n\n/**\n * @brief Restore the context of the first task so that the first task starts\n * executing.\n */\nvoid vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Checks whether or not the processor is privileged.\n *\n * @return 1 if the processor is already privileged, 0 otherwise.\n */\nBaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );\n\n/**\n * @brief Raises the privilege level by clearing the bit 0 of the CONTROL\n * register.\n *\n * @note This is a privileged function and should only be called from the kenrel\n * code.\n *\n * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.\n *  Bit[0] = 0 --> The processor is running privileged\n *  Bit[0] = 1 --> The processor is running unprivileged.\n */\nvoid vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\n * register.\n *\n * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.\n *  Bit[0] = 0 --> The processor is running privileged\n *  Bit[0] = 1 --> The processor is running unprivileged.\n */\nvoid vResetPrivilege( void ) __attribute__( ( naked ) );\n\n/**\n * @brief Starts the first task.\n */\nvoid vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Disables interrupts.\n */\nuint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Enables interrupts.\n */\nvoid vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief PendSV Exception handler.\n */\nvoid PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief SVC Handler.\n */\nvoid SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Allocate a Secure context for the calling task.\n *\n * @param[in] ulSecureStackSize The size of the stack to be allocated on the\n * secure side for the calling task.\n */\nvoid vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) );\n\n/**\n * @brief Free the task's secure context.\n *\n * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.\n */\nvoid vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n#endif /* __PORT_ASM_H__ */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef PORTMACRO_H\n#define PORTMACRO_H\n\n#ifdef __cplusplus\n    extern \"C\" {\n#endif\n\n#include \"portmacrocommon.h\"\n\n/*------------------------------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the given hardware\n * and compiler.\n *\n * These settings should not be altered.\n *------------------------------------------------------------------------------\n */\n\n/**\n * Architecture specifics.\n */\n#define portARCH_NAME                       \"Cortex-M33\"\n#define portDONT_DISCARD                    __attribute__( ( used ) )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Critical section management.\n */\n#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()\n#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )\n/*-----------------------------------------------------------*/\n\n#ifdef __cplusplus\n    }\n#endif\n\n#endif /* PORTMACRO_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef PORTMACROCOMMON_H\n    #define PORTMACROCOMMON_H\n\n    #ifdef __cplusplus\n        extern \"C\" {\n    #endif\n\n/*------------------------------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the given hardware\n * and compiler.\n *\n * These settings should not be altered.\n *------------------------------------------------------------------------------\n */\n\n    #ifndef configENABLE_FPU\n        #error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.\n    #endif /* configENABLE_FPU */\n\n    #ifndef configENABLE_MPU\n        #error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.\n    #endif /* configENABLE_MPU */\n\n    #ifndef configENABLE_TRUSTZONE\n        #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.\n    #endif /* configENABLE_TRUSTZONE */\n\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Type definitions.\n */\n    #define portCHAR          char\n    #define portFLOAT         float\n    #define portDOUBLE        double\n    #define portLONG          long\n    #define portSHORT         short\n    #define portSTACK_TYPE    uint32_t\n    #define portBASE_TYPE     long\n\n    typedef portSTACK_TYPE   StackType_t;\n    typedef long             BaseType_t;\n    typedef unsigned long    UBaseType_t;\n\n    #if ( configUSE_16_BIT_TICKS == 1 )\n        typedef uint16_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffff\n    #else\n        typedef uint32_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL\n\n/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\n * not need to be guarded with a critical section. */\n        #define portTICK_TYPE_IS_ATOMIC    1\n    #endif\n/*-----------------------------------------------------------*/\n\n/**\n * Architecture specifics.\n */\n    #define portSTACK_GROWTH                   ( -1 )\n    #define portTICK_PERIOD_MS                 ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\n    #define portBYTE_ALIGNMENT                 8\n    #define portNOP()\n    #define portINLINE                         __inline\n    #ifndef portFORCE_INLINE\n        #define portFORCE_INLINE               inline __attribute__( ( always_inline ) )\n    #endif\n    #define portHAS_STACK_OVERFLOW_CHECKING    1\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Extern declarations.\n */\n    extern BaseType_t xPortIsInsideInterrupt( void );\n\n    extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;\n\n    extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;\n    extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;\n\n    extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\n    extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\n\n    #if ( configENABLE_TRUSTZONE == 1 )\n        extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */\n        extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;\n    #endif /* configENABLE_TRUSTZONE */\n\n    #if ( configENABLE_MPU == 1 )\n        extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;\n        extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;\n    #endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\n/**\n * @brief MPU specific constants.\n */\n    #if ( configENABLE_MPU == 1 )\n        #define portUSING_MPU_WRAPPERS    1\n        #define portPRIVILEGE_BIT         ( 0x80000000UL )\n    #else\n        #define portPRIVILEGE_BIT         ( 0x0UL )\n    #endif /* configENABLE_MPU */\n\n/* MPU settings that can be overriden in FreeRTOSConfig.h. */\n#ifndef configTOTAL_MPU_REGIONS\n    /* Define to 8 for backward compatibility. */\n    #define configTOTAL_MPU_REGIONS       ( 8UL )\n#endif\n\n/* MPU regions. */\n    #define portPRIVILEGED_FLASH_REGION                   ( 0UL )\n    #define portUNPRIVILEGED_FLASH_REGION                 ( 1UL )\n    #define portUNPRIVILEGED_SYSCALLS_REGION              ( 2UL )\n    #define portPRIVILEGED_RAM_REGION                     ( 3UL )\n    #define portSTACK_REGION                              ( 4UL )\n    #define portFIRST_CONFIGURABLE_REGION                 ( 5UL )\n    #define portLAST_CONFIGURABLE_REGION                  ( configTOTAL_MPU_REGIONS - 1UL )\n    #define portNUM_CONFIGURABLE_REGIONS                  ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )\n    #define portTOTAL_NUM_REGIONS                         ( portNUM_CONFIGURABLE_REGIONS + 1 )   /* Plus one to make space for the stack region. */\n\n/* Device memory attributes used in MPU_MAIR registers.\n *\n * 8-bit values encoded as follows:\n *  Bit[7:4] - 0000 - Device Memory\n *  Bit[3:2] - 00 --> Device-nGnRnE\n *\t\t\t\t01 --> Device-nGnRE\n *\t\t\t\t10 --> Device-nGRE\n *\t\t\t\t11 --> Device-GRE\n *  Bit[1:0] - 00, Reserved.\n */\n    #define portMPU_DEVICE_MEMORY_nGnRnE                  ( 0x00 )   /* 0000 0000 */\n    #define portMPU_DEVICE_MEMORY_nGnRE                   ( 0x04 )   /* 0000 0100 */\n    #define portMPU_DEVICE_MEMORY_nGRE                    ( 0x08 )   /* 0000 1000 */\n    #define portMPU_DEVICE_MEMORY_GRE                     ( 0x0C )   /* 0000 1100 */\n\n/* Normal memory attributes used in MPU_MAIR registers. */\n    #define portMPU_NORMAL_MEMORY_NON_CACHEABLE           ( 0x44 )   /* Non-cacheable. */\n    #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE    ( 0xFF )   /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */\n\n/* Attributes used in MPU_RBAR registers. */\n    #define portMPU_REGION_NON_SHAREABLE                  ( 0UL << 3UL )\n    #define portMPU_REGION_INNER_SHAREABLE                ( 1UL << 3UL )\n    #define portMPU_REGION_OUTER_SHAREABLE                ( 2UL << 3UL )\n\n    #define portMPU_REGION_PRIVILEGED_READ_WRITE          ( 0UL << 1UL )\n    #define portMPU_REGION_READ_WRITE                     ( 1UL << 1UL )\n    #define portMPU_REGION_PRIVILEGED_READ_ONLY           ( 2UL << 1UL )\n    #define portMPU_REGION_READ_ONLY                      ( 3UL << 1UL )\n\n    #define portMPU_REGION_EXECUTE_NEVER                  ( 1UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Settings to define an MPU region.\n */\n    typedef struct MPURegionSettings\n    {\n        uint32_t ulRBAR; /**< RBAR for the region. */\n        uint32_t ulRLAR; /**< RLAR for the region. */\n    } MPURegionSettings_t;\n\n/**\n * @brief MPU settings as stored in the TCB.\n */\n    typedef struct MPU_SETTINGS\n    {\n        uint32_t ulMAIR0;                                              /**< MAIR0 for the task containing attributes for all the 4 per task regions. */\n        MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */\n    } xMPU_SETTINGS;\n/*-----------------------------------------------------------*/\n\n/**\n * @brief SVC numbers.\n */\n    #define portSVC_ALLOCATE_SECURE_CONTEXT    0\n    #define portSVC_FREE_SECURE_CONTEXT        1\n    #define portSVC_START_SCHEDULER            2\n    #define portSVC_RAISE_PRIVILEGE            3\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Scheduler utilities.\n */\n    #define portYIELD()                                 vPortYield()\n    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )\n    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )\n    #define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )\n    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Critical section management.\n */\n    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulSetInterruptMask()\n    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vClearInterruptMask( x )\n    #define portENTER_CRITICAL()                      vPortEnterCritical()\n    #define portEXIT_CRITICAL()                       vPortExitCritical()\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Tickless idle/low power functionality.\n */\n    #ifndef portSUPPRESS_TICKS_AND_SLEEP\n        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );\n        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )\n    #endif\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Task function macros as described on the FreeRTOS.org WEB site.\n */\n    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )\n    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )\n/*-----------------------------------------------------------*/\n\n    #if ( configENABLE_TRUSTZONE == 1 )\n\n/**\n * @brief Allocate a secure context for the task.\n *\n * Tasks are not created with a secure context. Any task that is going to call\n * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a\n * secure context before it calls any secure function.\n *\n * @param[in] ulSecureStackSize The size of the secure stack to be allocated.\n */\n        #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )\n\n/**\n * @brief Called when a task is deleted to delete the task's secure context,\n * if it has one.\n *\n * @param[in] pxTCB The TCB of the task being deleted.\n */\n        #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )\n    #endif /* configENABLE_TRUSTZONE */\n/*-----------------------------------------------------------*/\n\n    #if ( configENABLE_MPU == 1 )\n\n/**\n * @brief Checks whether or not the processor is privileged.\n *\n * @return 1 if the processor is already privileged, 0 otherwise.\n */\n        #define portIS_PRIVILEGED()      xIsPrivileged()\n\n/**\n * @brief Raise an SVC request to raise privilege.\n *\n * The SVC handler checks that the SVC was raised from a system call and only\n * then it raises the privilege. If this is called from any other place,\n * the privilege is not raised.\n */\n        #define portRAISE_PRIVILEGE()    __asm volatile ( \"svc %0 \\n\" ::\"i\" ( portSVC_RAISE_PRIVILEGE ) : \"memory\" );\n\n/**\n * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\n * register.\n */\n        #define portRESET_PRIVILEGE()    vResetPrivilege()\n    #else\n        #define portIS_PRIVILEGED()\n        #define portRAISE_PRIVILEGE()\n        #define portRESET_PRIVILEGE()\n    #endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Barriers.\n */\n    #define portMEMORY_BARRIER()    __asm volatile ( \"\" ::: \"memory\" )\n/*-----------------------------------------------------------*/\n\n    #ifdef __cplusplus\n        }\n    #endif\n\n#endif /* PORTMACROCOMMON_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM3_MPU/port.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/*-----------------------------------------------------------\n* Implementation of functions defined in portable.h for the ARM CM3 MPU port.\n*----------------------------------------------------------*/\n\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\n * all the API functions to use the MPU wrappers.  That should only be done when\n * task.h is included from an application file. */\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n#ifndef configSYSTICK_CLOCK_HZ\n    #define configSYSTICK_CLOCK_HZ    configCPU_CLOCK_HZ\n    /* Ensure the SysTick is clocked at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK      ( 1UL << 2UL )\n#else\n\n/* The way the SysTick is clocked is not modified in case it is not the same\n * as the core. */\n    #define portNVIC_SYSTICK_CLK    ( 0 )\n#endif\n\n#ifndef configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS\n    #warning \"configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS is not defined. We recommend defining it to 0 in FreeRTOSConfig.h for better security.\"\n    #define configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS    1\n#endif\n\n/* Constants required to access and manipulate the NVIC. */\n#define portNVIC_SYSTICK_CTRL_REG                 ( *( ( volatile uint32_t * ) 0xe000e010 ) )\n#define portNVIC_SYSTICK_LOAD_REG                 ( *( ( volatile uint32_t * ) 0xe000e014 ) )\n#define portNVIC_SYSTICK_CURRENT_VALUE_REG        ( *( ( volatile uint32_t * ) 0xe000e018 ) )\n#define portNVIC_SHPR3_REG                        ( *( ( volatile uint32_t * ) 0xe000ed20 ) )\n#define portNVIC_SHPR2_REG                        ( *( ( volatile uint32_t * ) 0xe000ed1c ) )\n#define portNVIC_SYS_CTRL_STATE_REG               ( *( ( volatile uint32_t * ) 0xe000ed24 ) )\n#define portNVIC_MEM_FAULT_ENABLE                 ( 1UL << 16UL )\n\n/* Constants required to access and manipulate the MPU. */\n#define portMPU_TYPE_REG                          ( *( ( volatile uint32_t * ) 0xe000ed90 ) )\n#define portMPU_REGION_BASE_ADDRESS_REG           ( *( ( volatile uint32_t * ) 0xe000ed9C ) )\n#define portMPU_REGION_ATTRIBUTE_REG              ( *( ( volatile uint32_t * ) 0xe000edA0 ) )\n#define portMPU_CTRL_REG                          ( *( ( volatile uint32_t * ) 0xe000ed94 ) )\n#define portEXPECTED_MPU_TYPE_VALUE               ( 8UL << 8UL ) /* 8 regions, unified. */\n#define portMPU_ENABLE                            ( 0x01UL )\n#define portMPU_BACKGROUND_ENABLE                 ( 1UL << 2UL )\n#define portPRIVILEGED_EXECUTION_START_ADDRESS    ( 0UL )\n#define portMPU_REGION_VALID                      ( 0x10UL )\n#define portMPU_REGION_ENABLE                     ( 0x01UL )\n#define portPERIPHERALS_START_ADDRESS             0x40000000UL\n#define portPERIPHERALS_END_ADDRESS               0x5FFFFFFFUL\n\n/* Constants required to access and manipulate the SysTick. */\n#define portNVIC_SYSTICK_INT                      ( 0x00000002UL )\n#define portNVIC_SYSTICK_ENABLE                   ( 0x00000001UL )\n#define portNVIC_PENDSV_PRI                       ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\n#define portNVIC_SYSTICK_PRI                      ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\n#define portNVIC_SVC_PRI                          ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )\n\n/* Constants required to set up the initial stack. */\n#define portINITIAL_XPSR                          ( 0x01000000 )\n#define portINITIAL_CONTROL_IF_UNPRIVILEGED       ( 0x03 )\n#define portINITIAL_CONTROL_IF_PRIVILEGED         ( 0x02 )\n\n/* Constants required to check the validity of an interrupt priority. */\n#define portFIRST_USER_INTERRUPT_NUMBER           ( 16 )\n#define portNVIC_IP_REGISTERS_OFFSET_16           ( 0xE000E3F0 )\n#define portAIRCR_REG                             ( *( ( volatile uint32_t * ) 0xE000ED0C ) )\n#define portMAX_8_BIT_VALUE                       ( ( uint8_t ) 0xff )\n#define portTOP_BIT_OF_BYTE                       ( ( uint8_t ) 0x80 )\n#define portMAX_PRIGROUP_BITS                     ( ( uint8_t ) 7 )\n#define portPRIORITY_GROUP_MASK                   ( 0x07UL << 8UL )\n#define portPRIGROUP_SHIFT                        ( 8UL )\n\n/* Offsets in the stack to the parameters when inside the SVC handler. */\n#define portOFFSET_TO_PC                          ( 6 )\n\n/* For strict compliance with the Cortex-M spec the task start address should\n * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */\n#define portSTART_ADDRESS_MASK                    ( ( StackType_t ) 0xfffffffeUL )\n/*-----------------------------------------------------------*/\n\n/*\n * Configure a number of standard MPU regions that are used by all tasks.\n */\nstatic void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\n\n/*\n * Return the smallest MPU region size that a given number of bytes will fit\n * into.  The region size is returned as the value that should be programmed\n * into the region attribute register for that region.\n */\nstatic uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;\n\n/*\n * Setup the timer to generate the tick interrupts.  The implementation in this\n * file is weak to allow application writers to change the timer used to\n * generate the tick interrupt.\n */\nvoid vPortSetupTimerInterrupt( void );\n\n/*\n * Standard FreeRTOS exception handlers.\n */\nvoid xPortPendSVHandler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\nvoid xPortSysTickHandler( void )  __attribute__( ( optimize( \"3\" ) ) ) PRIVILEGED_FUNCTION;\nvoid vPortSVCHandler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/*\n * Starts the scheduler by restoring the context of the first task to run.\n */\nstatic void prvRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/*\n * C portion of the SVC handler.  The SVC handler is split between an asm entry\n * and a C wrapper for simplicity of coding and maintenance.\n */\nstatic void prvSVCHandler( uint32_t * pulRegisters ) __attribute__( ( noinline ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Checks whether or not the processor is privileged.\n *\n * @return 1 if the processor is already privileged, 0 otherwise.\n */\nBaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );\n\n/**\n * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\n * register.\n *\n * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.\n *  Bit[0] = 0 --> The processor is running privileged\n *  Bit[0] = 1 --> The processor is running unprivileged.\n */\nvoid vResetPrivilege( void ) __attribute__( ( naked ) );\n\n/**\n * @brief Enter critical section.\n */\n#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )\n    void vPortEnterCritical( void ) FREERTOS_SYSTEM_CALL;\n#else\n    void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;\n#endif\n\n/**\n * @brief Exit from critical section.\n */\n#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )\n    void vPortExitCritical( void ) FREERTOS_SYSTEM_CALL;\n#else\n    void vPortExitCritical( void ) PRIVILEGED_FUNCTION;\n#endif\n/*-----------------------------------------------------------*/\n\n/* Each task maintains its own interrupt status in the critical nesting\n * variable.  Note this is not saved as part of the task context as context\n * switches can only occur when uxCriticalNesting is zero. */\nstatic UBaseType_t uxCriticalNesting = 0xaaaaaaaa;\n\n/*\n * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure\n * FreeRTOS API functions are not called from interrupts that have been assigned\n * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.\n */\n#if ( configASSERT_DEFINED == 1 )\n    static uint8_t ucMaxSysCallPriority = 0;\n    static uint32_t ulMaxPRIGROUPValue = 0;\n    static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;\n#endif /* configASSERT_DEFINED */\n/*-----------------------------------------------------------*/\n\n/*\n * See header file for description.\n */\nStackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,\n                                     TaskFunction_t pxCode,\n                                     void * pvParameters,\n                                     BaseType_t xRunPrivileged )\n{\n    /* Simulate the stack frame as it would be created by a context switch\n     * interrupt. */\n    pxTopOfStack--;                                                      /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\n    *pxTopOfStack = portINITIAL_XPSR;                                    /* xPSR */\n    pxTopOfStack--;\n    *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */\n    pxTopOfStack--;\n    *pxTopOfStack = 0;                                                   /* LR */\n    pxTopOfStack -= 5;                                                   /* R12, R3, R2 and R1. */\n    *pxTopOfStack = ( StackType_t ) pvParameters;                        /* R0 */\n    pxTopOfStack -= 9;                                                   /* R11, R10, R9, R8, R7, R6, R5 and R4. */\n\n    if( xRunPrivileged == pdTRUE )\n    {\n        *pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED;\n    }\n    else\n    {\n        *pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED;\n    }\n\n    return pxTopOfStack;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortSVCHandler( void )\n{\n    /* Assumes psp was in use. */\n    __asm volatile\n    (\n        #ifndef USE_PROCESS_STACK   /* Code should not be required if a main() is using the process stack. */\n            \"\ttst lr, #4\t\t\t\t\t\t\\n\"\n            \"\tite eq\t\t\t\t\t\t\t\\n\"\n            \"\tmrseq r0, msp\t\t\t\t\t\\n\"\n            \"\tmrsne r0, psp\t\t\t\t\t\\n\"\n        #else\n            \"\tmrs r0, psp\t\t\t\t\t\t\\n\"\n        #endif\n        \"\tb %0\t\t\t\t\t\t\t\\n\"\n        ::\"i\" ( prvSVCHandler ) : \"r0\", \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvSVCHandler( uint32_t * pulParam )\n{\n    uint8_t ucSVCNumber;\n    uint32_t ulPC;\n\n    #if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )\n        #if defined( __ARMCC_VERSION )\n\n            /* Declaration when these variable are defined in code instead of being\n             * exported from linker scripts. */\n            extern uint32_t * __syscalls_flash_start__;\n            extern uint32_t * __syscalls_flash_end__;\n        #else\n            /* Declaration when these variable are exported from linker scripts. */\n            extern uint32_t __syscalls_flash_start__[];\n            extern uint32_t __syscalls_flash_end__[];\n        #endif /* #if defined( __ARMCC_VERSION ) */\n    #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */\n\n    /* The stack contains: r0, r1, r2, r3, r12, LR, PC and xPSR.  The first\n     * argument (r0) is pulParam[ 0 ]. */\n    ulPC = pulParam[ portOFFSET_TO_PC ];\n    ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];\n\n    switch( ucSVCNumber )\n    {\n        case portSVC_START_SCHEDULER:\n            portNVIC_SHPR2_REG |= portNVIC_SVC_PRI;\n            prvRestoreContextOfFirstTask();\n            break;\n\n        case portSVC_YIELD:\n            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\n\n            /* Barriers are normally not required\n             * but do ensure the code is completely\n             * within the specified behaviour for the\n             * architecture. */\n            __asm volatile ( \"dsb\" ::: \"memory\" );\n            __asm volatile ( \"isb\" );\n\n            break;\n\n\n            #if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )\n                case portSVC_RAISE_PRIVILEGE: /* Only raise the privilege, if the\n                                               * svc was raised from any of the\n                                               * system calls. */\n\n                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&\n                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )\n                    {\n                        __asm volatile\n                        (\n                            \"\tmrs r1, control\t\t\\n\"/* Obtain current control value. */\n                            \"\tbic r1, #1\t\t\t\\n\"/* Set privilege bit. */\n                            \"\tmsr control, r1\t\t\\n\"/* Write back new control value. */\n                            ::: \"r1\", \"memory\"\n                        );\n                    }\n\n                    break;\n            #else /* if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */\n                case portSVC_RAISE_PRIVILEGE:\n                    __asm volatile\n                    (\n                        \"\tmrs r1, control\t\t\\n\"/* Obtain current control value. */\n                        \"\tbic r1, #1\t\t\t\\n\"/* Set privilege bit. */\n                        \"\tmsr control, r1\t\t\\n\"/* Write back new control value. */\n                        ::: \"r1\", \"memory\"\n                    );\n                    break;\n                    #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */\n\n                default: /* Unknown SVC call. */\n                    break;\n    }\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvRestoreContextOfFirstTask( void )\n{\n    __asm volatile\n    (\n        \"\tldr r0, =0xE000ED08\t\t\t\t\\n\"/* Use the NVIC offset register to locate the stack. */\n        \"\tldr r0, [r0]\t\t\t\t\t\\n\"\n        \"\tldr r0, [r0]\t\t\t\t\t\\n\"\n        \"\tmsr msp, r0\t\t\t\t\t\t\\n\"/* Set the msp back to the start of the stack. */\n        \"\tldr\tr3, pxCurrentTCBConst2\t\t\\n\"/* Restore the context. */\n        \"\tldr r1, [r3]\t\t\t\t\t\\n\"\n        \"\tldr r0, [r1]\t\t\t\t\t\\n\"/* The first item in the TCB is the task top of stack. */\n        \"\tadd r1, r1, #4\t\t\t\t\t\\n\"/* Move onto the second item in the TCB... */\n        \"\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tdmb\t\t\t\t\t\t\t\t\\n\"/* Complete outstanding transfers before disabling MPU. */\n        \"\tldr r2, =0xe000ed94\t\t\t\t\\n\"/* MPU_CTRL register. */\n        \"\tldr r3, [r2]\t\t\t\t\t\\n\"/* Read the value of MPU_CTRL. */\n        \"\tbic r3, #1\t\t\t\t\t\t\\n\"/* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */\n        \"\tstr r3, [r2]\t\t\t\t\t\\n\"/* Disable MPU. */\n        \"\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r2, =0xe000ed9c\t\t\t\t\\n\"/* Region Base Address register. */\n        \"\tldmia r1!, {r4-r11}\t\t\t\t\\n\"/* Read 4 sets of MPU registers. */\n        \"\tstmia r2!, {r4-r11}\t\t\t\t\\n\"/* Write 4 sets of MPU registers. */\n        \"\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r2, =0xe000ed94\t\t\t\t\\n\"/* MPU_CTRL register. */\n        \"\tldr r3, [r2]\t\t\t\t\t\\n\"/* Read the value of MPU_CTRL. */\n        \"\torr r3, #1\t\t\t\t\t\t\\n\"/* r3 = r3 | 1 i.e. Set the bit 0 in r3. */\n        \"\tstr r3, [r2]\t\t\t\t\t\\n\"/* Enable MPU. */\n        \"\tdsb\t\t\t\t\t\t\t\t\\n\"/* Force memory writes before continuing. */\n        \"\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldmia r0!, {r3, r4-r11}\t\t\t\\n\"/* Pop the registers that are not automatically saved on exception entry. */\n        \"\tmsr control, r3\t\t\t\t\t\\n\"\n        \"\tmsr psp, r0\t\t\t\t\t\t\\n\"/* Restore the task stack pointer. */\n        \"\tmov r0, #0\t\t\t\t\t\t\\n\"\n        \"\tmsr\tbasepri, r0\t\t\t\t\t\\n\"\n        \"\tldr r14, =0xfffffffd\t\t\t\\n\"/* Load exec return code. */\n        \"\tbx r14\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.ltorg\t\t\t\t\t\t\t\\n\"/* Assemble current literal pool to avoid offset-out-of-bound errors with lto. */\n        \"\t.align 4\t\t\t\t\t\t\\n\"\n        \"pxCurrentTCBConst2: .word pxCurrentTCB\t\\n\"\n    );\n}\n/*-----------------------------------------------------------*/\n\n/*\n * See header file for description.\n */\nBaseType_t xPortStartScheduler( void )\n{\n    /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See\n     * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\n    configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) );\n\n    #if ( configASSERT_DEFINED == 1 )\n        {\n            volatile uint32_t ulOriginalPriority;\n            volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\n            volatile uint8_t ucMaxPriorityValue;\n\n            /* Determine the maximum priority from which ISR safe FreeRTOS API\n             * functions can be called.  ISR safe functions are those that end in\n             * \"FromISR\".  FreeRTOS maintains separate thread and ISR API functions\n             * to ensure interrupt entry is as fast and simple as possible.\n             *\n             * Save the interrupt priority value that is about to be clobbered. */\n            ulOriginalPriority = *pucFirstUserPriorityRegister;\n\n            /* Determine the number of priority bits available.  First write to all\n             * possible bits. */\n            *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\n\n            /* Read the value back to see how many bits stuck. */\n            ucMaxPriorityValue = *pucFirstUserPriorityRegister;\n\n            /* Use the same mask on the maximum system call priority. */\n            ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;\n\n            /* Calculate the maximum acceptable priority group value for the number\n             * of bits read back. */\n            ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;\n\n            while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )\n            {\n                ulMaxPRIGROUPValue--;\n                ucMaxPriorityValue <<= ( uint8_t ) 0x01;\n            }\n\n            #ifdef __NVIC_PRIO_BITS\n                {\n                    /* Check the CMSIS configuration that defines the number of\n                     * priority bits matches the number of priority bits actually queried\n                     * from the hardware. */\n                    configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );\n                }\n            #endif\n\n            #ifdef configPRIO_BITS\n                {\n                    /* Check the FreeRTOS configuration that defines the number of\n                     * priority bits matches the number of priority bits actually queried\n                     * from the hardware. */\n                    configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );\n                }\n            #endif\n\n            /* Shift the priority group value back to its position within the AIRCR\n             * register. */\n            ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;\n            ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;\n\n            /* Restore the clobbered interrupt priority register to its original\n             * value. */\n            *pucFirstUserPriorityRegister = ulOriginalPriority;\n        }\n    #endif /* configASSERT_DEFINED */\n\n    /* Make PendSV and SysTick the same priority as the kernel, and the SVC\n     * handler higher priority so it can be used to exit a critical section (where\n     * lower priorities are masked). */\n    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;\n    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;\n\n    /* Configure the regions in the MPU that are common to all tasks. */\n    prvSetupMPU();\n\n    /* Start the timer that generates the tick ISR.  Interrupts are disabled\n     * here already. */\n    vPortSetupTimerInterrupt();\n\n    /* Initialise the critical nesting count ready for the first task. */\n    uxCriticalNesting = 0;\n\n    /* Start the first task. */\n    __asm volatile (\n        \" ldr r0, =0xE000ED08 \t\\n\"/* Use the NVIC offset register to locate the stack. */\n        \" ldr r0, [r0] \t\t\t\\n\"\n        \" ldr r0, [r0] \t\t\t\\n\"\n        \" msr msp, r0\t\t\t\\n\"/* Set the msp back to the start of the stack. */\n        \" cpsie i\t\t\t\t\\n\"/* Globally enable interrupts. */\n        \" cpsie f\t\t\t\t\\n\"\n        \" dsb\t\t\t\t\t\\n\"\n        \" isb\t\t\t\t\t\\n\"\n        \" svc %0\t\t\t\t\\n\"/* System call to start first task. */\n        \" nop\t\t\t\t\t\\n\"\n        \" .ltorg\t\t\t\t\\n\"\n        ::\"i\" ( portSVC_START_SCHEDULER ) : \"memory\" );\n\n    /* Should not get here! */\n    return 0;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEndScheduler( void )\n{\n    /* Not implemented in ports where there is nothing to return to.\n     * Artificially force an assert. */\n    configASSERT( uxCriticalNesting == 1000UL );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEnterCritical( void )\n{\n#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )\n    if( portIS_PRIVILEGED() == pdFALSE )\n    {\n        portRAISE_PRIVILEGE();\n        portMEMORY_BARRIER();\n\n        portDISABLE_INTERRUPTS();\n        uxCriticalNesting++;\n        portMEMORY_BARRIER();\n\n        portRESET_PRIVILEGE();\n        portMEMORY_BARRIER();\n    }\n    else\n    {\n        portDISABLE_INTERRUPTS();\n        uxCriticalNesting++;\n    }\n#else\n    portDISABLE_INTERRUPTS();\n    uxCriticalNesting++;\n#endif\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortExitCritical( void )\n{\n#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )\n    if( portIS_PRIVILEGED() == pdFALSE )\n    {\n        portRAISE_PRIVILEGE();\n        portMEMORY_BARRIER();\n\n        configASSERT( uxCriticalNesting );\n        uxCriticalNesting--;\n\n        if( uxCriticalNesting == 0 )\n        {\n            portENABLE_INTERRUPTS();\n        }\n        portMEMORY_BARRIER();\n\n        portRESET_PRIVILEGE();\n        portMEMORY_BARRIER();\n    }\n    else\n    {\n        configASSERT( uxCriticalNesting );\n        uxCriticalNesting--;\n\n        if( uxCriticalNesting == 0 )\n        {\n            portENABLE_INTERRUPTS();\n        }\n    }\n#else\n    configASSERT( uxCriticalNesting );\n    uxCriticalNesting--;\n\n    if( uxCriticalNesting == 0 )\n    {\n        portENABLE_INTERRUPTS();\n    }\n#endif\n}\n/*-----------------------------------------------------------*/\n\nvoid xPortPendSVHandler( void )\n{\n    /* This is a naked function. */\n\n    __asm volatile\n    (\n        \"\tmrs r0, psp\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr\tr3, pxCurrentTCBConst\t\t\t\\n\"/* Get the location of the current TCB. */\n        \"\tldr\tr2, [r3]\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrs r1, control\t\t\t\t\t\t\\n\"\n        \"\tstmdb r0!, {r1, r4-r11}\t\t\t\t\\n\"/* Save the remaining registers. */\n        \"\tstr r0, [r2]\t\t\t\t\t\t\\n\"/* Save the new top of stack into the first member of the TCB. */\n        \"\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tstmdb sp!, {r3, r14}\t\t\t\t\\n\"\n        \"\tmov r0, %0\t\t\t\t\t\t\t\\n\"\n        \"\tmsr basepri, r0\t\t\t\t\t\t\\n\"\n        \"\tdsb\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tisb\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tbl vTaskSwitchContext\t\t\t\t\\n\"\n        \"\tmov r0, #0\t\t\t\t\t\t\t\\n\"\n        \"\tmsr basepri, r0\t\t\t\t\t\t\\n\"\n        \"\tldmia sp!, {r3, r14}\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\\n\"/* Restore the context. */\n        \"\tldr r1, [r3]\t\t\t\t\t\t\\n\"\n        \"\tldr r0, [r1]\t\t\t\t\t\t\\n\"/* The first item in the TCB is the task top of stack. */\n        \"\tadd r1, r1, #4\t\t\t\t\t\t\\n\"/* Move onto the second item in the TCB... */\n        \"\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tdmb\t\t\t\t\t\t\t\t\t\\n\"/* Complete outstanding transfers before disabling MPU. */\n        \"\tldr r2, =0xe000ed94\t\t\t\t\t\\n\"/* MPU_CTRL register. */\n        \"\tldr r3, [r2]\t\t\t\t\t\t\\n\"/* Read the value of MPU_CTRL. */\n        \"\tbic r3, #1\t\t\t\t\t\t\t\\n\"/* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */\n        \"\tstr r3, [r2]\t\t\t\t\t\t\\n\"/* Disable MPU. */\n        \"\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r2, =0xe000ed9c\t\t\t\t\t\\n\"/* Region Base Address register. */\n        \"\tldmia r1!, {r4-r11}\t\t\t\t\t\\n\"/* Read 4 sets of MPU registers. */\n        \"\tstmia r2!, {r4-r11}\t\t\t\t\t\\n\"/* Write 4 sets of MPU registers. */\n        \"\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r2, =0xe000ed94\t\t\t\t\t\\n\"/* MPU_CTRL register. */\n        \"\tldr r3, [r2]\t\t\t\t\t\t\\n\"/* Read the value of MPU_CTRL. */\n        \"\torr r3, #1\t\t\t\t\t\t\t\\n\"/* r3 = r3 | 1 i.e. Set the bit 0 in r3. */\n        \"\tstr r3, [r2]\t\t\t\t\t\t\\n\"/* Enable MPU. */\n        \"\tdsb\t\t\t\t\t\t\t\t\t\\n\"/* Force memory writes before continuing. */\n        \"\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldmia r0!, {r3, r4-r11}\t\t\t\t\\n\"/* Pop the registers that are not automatically saved on exception entry. */\n        \"\tmsr control, r3\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmsr psp, r0\t\t\t\t\t\t\t\\n\"\n        \"\tbx r14\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.ltorg\t\t\t\t\t\t\t\t\\n\"/* Assemble current literal pool to avoid offset-out-of-bound errors with lto. */\n        \"\t.align 4\t\t\t\t\t\t\t\\n\"\n        \"pxCurrentTCBConst: .word pxCurrentTCB\t\\n\"\n        ::\"i\" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid xPortSysTickHandler( void )\n{\n    uint32_t ulDummy;\n\n    ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();\n    {\n        /* Increment the RTOS tick. */\n        if( xTaskIncrementTick() != pdFALSE )\n        {\n            /* Pend a context switch. */\n            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\n        }\n    }\n    portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );\n}\n/*-----------------------------------------------------------*/\n\n/*\n * Setup the systick timer to generate the tick interrupts at the required\n * frequency.\n */\n__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )\n{\n    /* Stop and clear the SysTick. */\n    portNVIC_SYSTICK_CTRL_REG = 0UL;\n    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n    /* Configure SysTick to interrupt at the requested rate. */\n    portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\n    portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE );\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvSetupMPU( void )\n{\n    extern uint32_t __privileged_functions_start__[];\n    extern uint32_t __privileged_functions_end__[];\n    extern uint32_t __FLASH_segment_start__[];\n    extern uint32_t __FLASH_segment_end__[];\n    extern uint32_t __privileged_data_start__[];\n    extern uint32_t __privileged_data_end__[];\n\n    /* Check the expected MPU is present. */\n    if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )\n    {\n        /* First setup the unprivileged flash for unprivileged read only access. */\n        portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */\n                                          ( portMPU_REGION_VALID ) |\n                                          ( portUNPRIVILEGED_FLASH_REGION );\n\n        portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_ONLY ) |\n                                       ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\n                                       ( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |\n                                       ( portMPU_REGION_ENABLE );\n\n        /* Setup the privileged flash for privileged only access.  This is where\n         * the kernel code is * placed. */\n        portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_functions_start__ ) | /* Base address. */\n                                          ( portMPU_REGION_VALID ) |\n                                          ( portPRIVILEGED_FLASH_REGION );\n\n        portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_ONLY ) |\n                                       ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\n                                       ( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __privileged_functions_start__ ) ) |\n                                       ( portMPU_REGION_ENABLE );\n\n        /* Setup the privileged data RAM region.  This is where the kernel data\n         * is placed. */\n        portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */\n                                          ( portMPU_REGION_VALID ) |\n                                          ( portPRIVILEGED_RAM_REGION );\n\n        portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\n                                       ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\n                                       ( portMPU_REGION_EXECUTE_NEVER ) |\n                                       prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |\n                                       ( portMPU_REGION_ENABLE );\n\n        /* By default allow everything to access the general peripherals.  The\n         * system peripherals and registers are protected. */\n        portMPU_REGION_BASE_ADDRESS_REG = ( portPERIPHERALS_START_ADDRESS ) |\n                                          ( portMPU_REGION_VALID ) |\n                                          ( portGENERAL_PERIPHERALS_REGION );\n\n        portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |\n                                       ( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |\n                                       ( portMPU_REGION_ENABLE );\n\n        /* Enable the memory fault exception. */\n        portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE;\n\n        /* Enable the MPU with the background region configured. */\n        portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );\n    }\n}\n/*-----------------------------------------------------------*/\n\nstatic uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )\n{\n    uint32_t ulRegionSize, ulReturnValue = 4;\n\n    /* 32 is the smallest region size, 31 is the largest valid value for\n     * ulReturnValue. */\n    for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )\n    {\n        if( ulActualSizeInBytes <= ulRegionSize )\n        {\n            break;\n        }\n        else\n        {\n            ulReturnValue++;\n        }\n    }\n\n    /* Shift the code by one before returning so it can be written directly\n     * into the the correct bit position of the attribute register. */\n    return( ulReturnValue << 1UL );\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */\n{\n    __asm volatile\n    (\n        \"\tmrs r0, control\t\t\t\t\t\t\t\\n\"/* r0 = CONTROL. */\n        \"\ttst r0, #1\t\t\t\t\t\t\t\t\\n\"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\n        \"\tite ne\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmovne r0, #0\t\t\t\t\t\t\t\\n\"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\n        \"\tmoveq r0, #1\t\t\t\t\t\t\t\\n\"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\\n\"/* Return. */\n        \"\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.align 4\t\t\t\t\t\t\t\t\\n\"\n        ::: \"r0\", \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vResetPrivilege( void ) /* __attribute__ (( naked )) */\n{\n    __asm volatile\n    (\n        \"\tmrs r0, control\t\t\t\t\t\t\t\\n\"/* r0 = CONTROL. */\n        \"\torr r0, #1\t\t\t\t\t\t\t\t\\n\"/* r0 = r0 | 1. */\n        \"\tmsr control, r0\t\t\t\t\t\t\t\\n\"/* CONTROL = r0. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\\n\"/* Return to the caller. */\n        ::: \"r0\", \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,\n                                const struct xMEMORY_REGION * const xRegions,\n                                StackType_t * pxBottomOfStack,\n                                uint32_t ulStackDepth )\n{\n    extern uint32_t __SRAM_segment_start__[];\n    extern uint32_t __SRAM_segment_end__[];\n    extern uint32_t __privileged_data_start__[];\n    extern uint32_t __privileged_data_end__[];\n    int32_t lIndex;\n    uint32_t ul;\n\n    if( xRegions == NULL )\n    {\n        /* No MPU regions are specified so allow access to all RAM. */\n        xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =\n            ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */\n            ( portMPU_REGION_VALID ) |\n            ( portSTACK_REGION ); /* Region number. */\n\n        xMPUSettings->xRegion[ 0 ].ulRegionAttribute =\n            ( portMPU_REGION_READ_WRITE ) |\n            ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\n            ( portMPU_REGION_EXECUTE_NEVER ) |\n            ( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |\n            ( portMPU_REGION_ENABLE );\n\n        /* Invalidate user configurable regions. */\n        for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )\n        {\n            xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( ul - 1UL ) | portMPU_REGION_VALID );\n            xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;\n        }\n    }\n    else\n    {\n        /* This function is called automatically when the task is created - in\n         * which case the stack region parameters will be valid.  At all other\n         * times the stack parameters will not be valid and it is assumed that the\n         * stack region has already been configured. */\n        if( ulStackDepth > 0 )\n        {\n            /* Define the region that allows access to the stack. */\n            xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =\n                ( ( uint32_t ) pxBottomOfStack ) |\n                ( portMPU_REGION_VALID ) |\n                ( portSTACK_REGION ); /* Region number. */\n\n            xMPUSettings->xRegion[ 0 ].ulRegionAttribute =\n                ( portMPU_REGION_READ_WRITE ) |\n                ( portMPU_REGION_EXECUTE_NEVER ) |\n                ( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |\n                ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\n                ( portMPU_REGION_ENABLE );\n        }\n\n        lIndex = 0;\n\n        for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )\n        {\n            if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )\n            {\n                /* Translate the generic region definition contained in\n                 * xRegions into the CM3 specific MPU settings that are then\n                 * stored in xMPUSettings. */\n                xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =\n                    ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |\n                    ( portMPU_REGION_VALID ) |\n                    ( ul - 1UL ); /* Region number. */\n\n                xMPUSettings->xRegion[ ul ].ulRegionAttribute =\n                    ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |\n                    ( xRegions[ lIndex ].ulParameters ) |\n                    ( portMPU_REGION_ENABLE );\n            }\n            else\n            {\n                /* Invalidate the region. */\n                xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( ul - 1UL ) | portMPU_REGION_VALID );\n                xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;\n            }\n\n            lIndex++;\n        }\n    }\n}\n/*-----------------------------------------------------------*/\n\n#if ( configASSERT_DEFINED == 1 )\n\n    void vPortValidateInterruptPriority( void )\n    {\n        uint32_t ulCurrentInterrupt;\n        uint8_t ucCurrentPriority;\n\n        /* Obtain the number of the currently executing interrupt. */\n        __asm volatile ( \"mrs %0, ipsr\" : \"=r\" ( ulCurrentInterrupt )::\"memory\" );\n\n        /* Is the interrupt number a user defined interrupt? */\n        if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )\n        {\n            /* Look up the interrupt's priority. */\n            ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];\n\n            /* The following assertion will fail if a service routine (ISR) for\n             * an interrupt that has been assigned a priority above\n             * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\n             * function.  ISR safe FreeRTOS API functions must *only* be called\n             * from interrupts that have been assigned a priority at or below\n             * configMAX_SYSCALL_INTERRUPT_PRIORITY.\n             *\n             * Numerically low interrupt priority numbers represent logically high\n             * interrupt priorities, therefore the priority of the interrupt must\n             * be set to a value equal to or numerically *higher* than\n             * configMAX_SYSCALL_INTERRUPT_PRIORITY.\n             *\n             * Interrupts that\tuse the FreeRTOS API must not be left at their\n             * default priority of\tzero as that is the highest possible priority,\n             * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,\n             * and\ttherefore also guaranteed to be invalid.\n             *\n             * FreeRTOS maintains separate thread and ISR API functions to ensure\n             * interrupt entry is as fast and simple as possible.\n             *\n             * The following links provide detailed information:\n             * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html\n             * https://www.FreeRTOS.org/FAQHelp.html */\n            configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );\n        }\n\n        /* Priority grouping:  The interrupt controller (NVIC) allows the bits\n         * that define each interrupt's priority to be split between bits that\n         * define the interrupt's pre-emption priority bits and bits that define\n         * the interrupt's sub-priority.  For simplicity all bits must be defined\n         * to be pre-emption priority bits.  The following assertion will fail if\n         * this is not the case (if some bits represent a sub-priority).\n         *\n         * If the application only uses CMSIS libraries for interrupt\n         * configuration then the correct setting can be achieved on all Cortex-M\n         * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the\n         * scheduler.  Note however that some vendor specific peripheral libraries\n         * assume a non-zero priority group setting, in which cases using a value\n         * of zero will result in unpredicable behaviour. */\n        configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );\n    }\n\n#endif /* configASSERT_DEFINED */\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM3_MPU/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n\n#ifndef PORTMACRO_H\n    #define PORTMACRO_H\n\n    #ifdef __cplusplus\n        extern \"C\" {\n    #endif\n\n/*-----------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the\n * given hardware and compiler.\n *\n * These settings should not be altered.\n *-----------------------------------------------------------\n */\n\n/* Type definitions. */\n    #define portCHAR          char\n    #define portFLOAT         float\n    #define portDOUBLE        double\n    #define portLONG          long\n    #define portSHORT         short\n    #define portSTACK_TYPE    uint32_t\n    #define portBASE_TYPE     long\n\n    typedef portSTACK_TYPE   StackType_t;\n    typedef long             BaseType_t;\n    typedef unsigned long    UBaseType_t;\n\n    #if ( configUSE_16_BIT_TICKS == 1 )\n        typedef uint16_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffff\n    #else\n        typedef uint32_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL\n\n/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\n * not need to be guarded with a critical section. */\n        #define portTICK_TYPE_IS_ATOMIC    1\n    #endif\n/*-----------------------------------------------------------*/\n\n/* MPU specific constants. */\n    #define portUSING_MPU_WRAPPERS                                   1\n    #define portPRIVILEGE_BIT                                        ( 0x80000000UL )\n\n    #define portMPU_REGION_READ_WRITE                                ( 0x03UL << 24UL )\n    #define portMPU_REGION_PRIVILEGED_READ_ONLY                      ( 0x05UL << 24UL )\n    #define portMPU_REGION_READ_ONLY                                 ( 0x06UL << 24UL )\n    #define portMPU_REGION_PRIVILEGED_READ_WRITE                     ( 0x01UL << 24UL )\n    #define portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY    ( 0x02UL << 24UL )\n    #define portMPU_REGION_CACHEABLE_BUFFERABLE                      ( 0x07UL << 16UL )\n    #define portMPU_REGION_EXECUTE_NEVER                             ( 0x01UL << 28UL )\n\n    #define portGENERAL_PERIPHERALS_REGION                           ( 3UL )\n    #define portSTACK_REGION                                         ( 4UL )\n    #define portUNPRIVILEGED_FLASH_REGION                            ( 5UL )\n    #define portPRIVILEGED_FLASH_REGION                              ( 6UL )\n    #define portPRIVILEGED_RAM_REGION                                ( 7UL )\n    #define portFIRST_CONFIGURABLE_REGION                            ( 0UL )\n    #define portLAST_CONFIGURABLE_REGION                             ( 2UL )\n    #define portNUM_CONFIGURABLE_REGIONS                             ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )\n    #define portTOTAL_NUM_REGIONS_IN_TCB                             ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */\n\n    #define portSWITCH_TO_USER_MODE()    __asm volatile ( \" mrs r0, control \\n orr r0, #1 \\n msr control, r0 \" ::: \"r0\", \"memory\" )\n\n    typedef struct MPU_REGION_REGISTERS\n    {\n        uint32_t ulRegionBaseAddress;\n        uint32_t ulRegionAttribute;\n    } xMPU_REGION_REGISTERS;\n\n/* Plus 1 to create space for the stack region. */\n    typedef struct MPU_SETTINGS\n    {\n        xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS_IN_TCB ];\n    } xMPU_SETTINGS;\n\n/* Architecture specifics. */\n    #define portSTACK_GROWTH      ( -1 )\n    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\n    #define portBYTE_ALIGNMENT    8\n    #define portDONT_DISCARD      __attribute__( ( used ) )\n/*-----------------------------------------------------------*/\n\n/* SVC numbers for various services. */\n    #define portSVC_START_SCHEDULER    0\n    #define portSVC_YIELD              1\n    #define portSVC_RAISE_PRIVILEGE    2\n\n/* Scheduler utilities. */\n\n    #define portYIELD()    __asm volatile ( \"\tSVC\t%0\t\\n\"::\"i\" ( portSVC_YIELD ) : \"memory\" )\n    #define portYIELD_WITHIN_API()                      \\\n    {                                                   \\\n        /* Set a PendSV to request a context switch. */ \\\n        portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \\\n                                                        \\\n        /* Barriers are normally not required but do ensure the code is completely \\\n         * within the specified behaviour for the architecture. */ \\\n        __asm volatile ( \"dsb\" ::: \"memory\" );                     \\\n        __asm volatile ( \"isb\" );                                  \\\n    }\n\n    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )\n    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )\n    #define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )\n    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )\n/*-----------------------------------------------------------*/\n\n/* Critical section management. */\n    extern void vPortEnterCritical( void );\n    extern void vPortExitCritical( void );\n    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulPortRaiseBASEPRI()\n    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vPortSetBASEPRI( x )\n    #define portDISABLE_INTERRUPTS()                  vPortRaiseBASEPRI()\n    #define portENABLE_INTERRUPTS()                   vPortSetBASEPRI( 0 )\n    #define portENTER_CRITICAL()                      vPortEnterCritical()\n    #define portEXIT_CRITICAL()                       vPortExitCritical()\n\n/*-----------------------------------------------------------*/\n\n/* Task function macros as described on the FreeRTOS.org WEB site.  These are\n * not necessary for to use this port.  They are defined so the common demo files\n * (which build with all the ports) will build. */\n    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )\n    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )\n/*-----------------------------------------------------------*/\n\n/* Architecture specific optimisations. */\n    #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION\n        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1\n    #endif\n\n    #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1\n\n/* Generic helper function. */\n        __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )\n        {\n            uint8_t ucReturn;\n\n            __asm volatile ( \"clz %0, %1\" : \"=r\" ( ucReturn ) : \"r\" ( ulBitmap ) : \"memory\" );\n\n            return ucReturn;\n        }\n\n/* Check the configuration. */\n        #if ( configMAX_PRIORITIES > 32 )\n            #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.\n        #endif\n\n/* Store/clear the ready priorities in a bit map. */\n        #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )\n        #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )\n\n/*-----------------------------------------------------------*/\n\n        #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )\n\n    #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */\n\n/*-----------------------------------------------------------*/\n\n    #ifdef configASSERT\n        void vPortValidateInterruptPriority( void );\n        #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()\n    #endif\n\n/* portNOP() is not required by this port. */\n    #define portNOP()\n\n    #define portINLINE              __inline\n\n    #ifndef portFORCE_INLINE\n        #define portFORCE_INLINE    inline __attribute__( ( always_inline ) )\n    #endif\n/*-----------------------------------------------------------*/\n\n    extern BaseType_t xIsPrivileged( void );\n    extern void vResetPrivilege( void );\n\n/**\n * @brief Checks whether or not the processor is privileged.\n *\n * @return 1 if the processor is already privileged, 0 otherwise.\n */\n    #define portIS_PRIVILEGED()      xIsPrivileged()\n\n/**\n * @brief Raise an SVC request to raise privilege.\n */\n    #define portRAISE_PRIVILEGE()    __asm volatile ( \"svc %0 \\n\" ::\"i\" ( portSVC_RAISE_PRIVILEGE ) : \"memory\" );\n\n/**\n * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\n * register.\n */\n    #define portRESET_PRIVILEGE()    vResetPrivilege()\n/*-----------------------------------------------------------*/\n\n    portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )\n    {\n        uint32_t ulCurrentInterrupt;\n        BaseType_t xReturn;\n\n        /* Obtain the number of the currently executing interrupt. */\n        __asm volatile ( \"mrs %0, ipsr\" : \"=r\" ( ulCurrentInterrupt )::\"memory\" );\n\n        if( ulCurrentInterrupt == 0 )\n        {\n            xReturn = pdFALSE;\n        }\n        else\n        {\n            xReturn = pdTRUE;\n        }\n\n        return xReturn;\n    }\n\n/*-----------------------------------------------------------*/\n\n    portFORCE_INLINE static void vPortRaiseBASEPRI( void )\n    {\n        uint32_t ulNewBASEPRI;\n\n        __asm volatile\n        (\n            \"\tmov %0, %1\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\\\n            \"\tmsr basepri, %0\t\t\t\t\t\t\t\t\t\t\t\\n\"\\\n            \"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\\\n            \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\\\n            : \"=r\" ( ulNewBASEPRI ) : \"i\" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : \"memory\"\n        );\n    }\n\n/*-----------------------------------------------------------*/\n\n    portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )\n    {\n        uint32_t ulOriginalBASEPRI, ulNewBASEPRI;\n\n        __asm volatile\n        (\n            \"\tmrs %0, basepri\t\t\t\t\t\t\t\t\t\t\t\\n\"\\\n            \"\tmov %1, %2\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\\\n            \"\tmsr basepri, %1\t\t\t\t\t\t\t\t\t\t\t\\n\"\\\n            \"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\\\n            \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\\\n            : \"=r\" ( ulOriginalBASEPRI ), \"=r\" ( ulNewBASEPRI ) : \"i\" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : \"memory\"\n        );\n\n        /* This return will not be reached but is necessary to prevent compiler\n         * warnings. */\n        return ulOriginalBASEPRI;\n    }\n/*-----------------------------------------------------------*/\n\n    portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )\n    {\n        __asm volatile\n        (\n            \"\tmsr basepri, %0\t\"::\"r\" ( ulNewMaskValue ) : \"memory\"\n        );\n    }\n/*-----------------------------------------------------------*/\n\n    #define portMEMORY_BARRIER()    __asm volatile ( \"\" ::: \"memory\" )\n\n    #ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY\n        #warning \"configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. https://www.FreeRTOS.org/FreeRTOS-V10.3.x.html\"\n        #define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY    0\n    #endif\n/*-----------------------------------------------------------*/\n    #ifdef __cplusplus\n        }\n    #endif\n\n#endif /* PORTMACRO_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM4F/port.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/*-----------------------------------------------------------\n* Implementation of functions defined in portable.h for the ARM CM4F port.\n*----------------------------------------------------------*/\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n#ifndef __VFP_FP__\n    #error This port can only be used when the project options are configured to enable hardware floating point support.\n#endif\n\n/* Constants required to manipulate the core.  Registers first... */\n#define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )\n#define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )\n#define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )\n#define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )\n/* ...then bits in the registers. */\n#define portNVIC_SYSTICK_CLK_BIT              ( 1UL << 2UL )\n#define portNVIC_SYSTICK_INT_BIT              ( 1UL << 1UL )\n#define portNVIC_SYSTICK_ENABLE_BIT           ( 1UL << 0UL )\n#define portNVIC_SYSTICK_COUNT_FLAG_BIT       ( 1UL << 16UL )\n#define portNVIC_PENDSVCLEAR_BIT              ( 1UL << 27UL )\n#define portNVIC_PEND_SYSTICK_SET_BIT         ( 1UL << 26UL )\n#define portNVIC_PEND_SYSTICK_CLEAR_BIT       ( 1UL << 25UL )\n\n/* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7\n * r0p1 port. */\n#define portCPUID                             ( *( ( volatile uint32_t * ) 0xE000ed00 ) )\n#define portCORTEX_M7_r0p1_ID                 ( 0x410FC271UL )\n#define portCORTEX_M7_r0p0_ID                 ( 0x410FC270UL )\n\n#define portNVIC_PENDSV_PRI                   ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\n#define portNVIC_SYSTICK_PRI                  ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\n\n/* Constants required to check the validity of an interrupt priority. */\n#define portFIRST_USER_INTERRUPT_NUMBER       ( 16 )\n#define portNVIC_IP_REGISTERS_OFFSET_16       ( 0xE000E3F0 )\n#define portAIRCR_REG                         ( *( ( volatile uint32_t * ) 0xE000ED0C ) )\n#define portMAX_8_BIT_VALUE                   ( ( uint8_t ) 0xff )\n#define portTOP_BIT_OF_BYTE                   ( ( uint8_t ) 0x80 )\n#define portMAX_PRIGROUP_BITS                 ( ( uint8_t ) 7 )\n#define portPRIORITY_GROUP_MASK               ( 0x07UL << 8UL )\n#define portPRIGROUP_SHIFT                    ( 8UL )\n\n/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */\n#define portVECTACTIVE_MASK                   ( 0xFFUL )\n\n/* Constants required to manipulate the VFP. */\n#define portFPCCR                             ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */\n#define portASPEN_AND_LSPEN_BITS              ( 0x3UL << 30UL )\n\n/* Constants required to set up the initial stack. */\n#define portINITIAL_XPSR                      ( 0x01000000 )\n#define portINITIAL_EXC_RETURN                ( 0xfffffffd )\n\n/* The systick is a 24-bit counter. */\n#define portMAX_24_BIT_NUMBER                 ( 0xffffffUL )\n\n/* For strict compliance with the Cortex-M spec the task start address should\n * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */\n#define portSTART_ADDRESS_MASK                ( ( StackType_t ) 0xfffffffeUL )\n\n/* A fiddle factor to estimate the number of SysTick counts that would have\n * occurred while the SysTick counter is stopped during tickless idle\n * calculations. */\n#define portMISSED_COUNTS_FACTOR              ( 94UL )\n\n/* Let the user override the default SysTick clock rate.  If defined by the\n * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the\n * configuration register. */\n#ifndef configSYSTICK_CLOCK_HZ\n    #define configSYSTICK_CLOCK_HZ             ( configCPU_CLOCK_HZ )\n    /* Ensure the SysTick is clocked at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( portNVIC_SYSTICK_CLK_BIT )\n#else\n    /* Select the option to clock SysTick not at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( 0 )\n#endif\n\n/* Let the user override the pre-loading of the initial LR with the address of\n * prvTaskExitError() in case it messes up unwinding of the stack in the\n * debugger. */\n#ifdef configTASK_RETURN_ADDRESS\n    #define portTASK_RETURN_ADDRESS    configTASK_RETURN_ADDRESS\n#else\n    #define portTASK_RETURN_ADDRESS    prvTaskExitError\n#endif\n\n/*\n * Setup the timer to generate the tick interrupts.  The implementation in this\n * file is weak to allow application writers to change the timer used to\n * generate the tick interrupt.\n */\nvoid vPortSetupTimerInterrupt( void );\n\n/*\n * Exception handlers.\n */\nvoid xPortPendSVHandler( void ) __attribute__( ( naked ) );\nvoid xPortSysTickHandler( void );\nvoid vPortSVCHandler( void ) __attribute__( ( naked ) );\n\n/*\n * Start first task is a separate function so it can be tested in isolation.\n */\nstatic void prvPortStartFirstTask( void ) __attribute__( ( naked ) );\n\n/*\n * Function to enable the VFP.\n */\nstatic void vPortEnableVFP( void ) __attribute__( ( naked ) );\n\n/*\n * Used to catch tasks that attempt to return from their implementing function.\n */\nstatic void prvTaskExitError( void );\n\n/*-----------------------------------------------------------*/\n\n/* Each task maintains its own interrupt status in the critical nesting\n * variable. */\nstatic UBaseType_t uxCriticalNesting = 0xaaaaaaaa;\n\n/*\n * The number of SysTick increments that make up one tick period.\n */\n#if ( configUSE_TICKLESS_IDLE == 1 )\n    static uint32_t ulTimerCountsForOneTick = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n\n/*\n * The maximum number of tick periods that can be suppressed is limited by the\n * 24 bit resolution of the SysTick timer.\n */\n#if ( configUSE_TICKLESS_IDLE == 1 )\n    static uint32_t xMaximumPossibleSuppressedTicks = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n\n/*\n * Compensate for the CPU cycles that pass while the SysTick is stopped (low\n * power functionality only.\n */\n#if ( configUSE_TICKLESS_IDLE == 1 )\n    static uint32_t ulStoppedTimerCompensation = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n\n/*\n * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure\n * FreeRTOS API functions are not called from interrupts that have been assigned\n * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.\n */\n#if ( configASSERT_DEFINED == 1 )\n    static uint8_t ucMaxSysCallPriority = 0;\n    static uint32_t ulMaxPRIGROUPValue = 0;\n    static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;\n#endif /* configASSERT_DEFINED */\n\n/*-----------------------------------------------------------*/\n\n/*\n * See header file for description.\n */\nStackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,\n                                     TaskFunction_t pxCode,\n                                     void * pvParameters )\n{\n    /* Simulate the stack frame as it would be created by a context switch\n     * interrupt. */\n\n    /* Offset added to account for the way the MCU uses the stack on entry/exit\n     * of interrupts, and to ensure alignment. */\n    pxTopOfStack--;\n\n    *pxTopOfStack = portINITIAL_XPSR;                                    /* xPSR */\n    pxTopOfStack--;\n    *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */\n    pxTopOfStack--;\n    *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;             /* LR */\n\n    /* Save code space by skipping register initialisation. */\n    pxTopOfStack -= 5;                            /* R12, R3, R2 and R1. */\n    *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\n\n    /* A save method is being used that requires each task to maintain its\n     * own exec return value. */\n    pxTopOfStack--;\n    *pxTopOfStack = portINITIAL_EXC_RETURN;\n\n    pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */\n\n    return pxTopOfStack;\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvTaskExitError( void )\n{\n    volatile uint32_t ulDummy = 0;\n\n    /* A function that implements a task must not exit or attempt to return to\n     * its caller as there is nothing to return to.  If a task wants to exit it\n     * should instead call vTaskDelete( NULL ).\n     *\n     * Artificially force an assert() to be triggered if configASSERT() is\n     * defined, then stop here so application writers can catch the error. */\n    configASSERT( uxCriticalNesting == ~0UL );\n    portDISABLE_INTERRUPTS();\n\n    while( ulDummy == 0 )\n    {\n        /* This file calls prvTaskExitError() after the scheduler has been\n         * started to remove a compiler warning about the function being defined\n         * but never called.  ulDummy is used purely to quieten other warnings\n         * about code appearing after this function is called - making ulDummy\n         * volatile makes the compiler think the function could return and\n         * therefore not output an 'unreachable code' warning for code that appears\n         * after it. */\n    }\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortSVCHandler( void )\n{\n    __asm volatile (\n        \"\tldr\tr3, pxCurrentTCBConst2\t\t\\n\"/* Restore the context. */\n        \"\tldr r1, [r3]\t\t\t\t\t\\n\"/* Use pxCurrentTCBConst to get the pxCurrentTCB address. */\n        \"\tldr r0, [r1]\t\t\t\t\t\\n\"/* The first item in pxCurrentTCB is the task top of stack. */\n        \"\tldmia r0!, {r4-r11, r14}\t\t\\n\"/* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */\n        \"\tmsr psp, r0\t\t\t\t\t\t\\n\"/* Restore the task stack pointer. */\n        \"\tisb\t\t\t\t\t\t\t\t\\n\"\n        \"\tmov r0, #0 \t\t\t\t\t\t\\n\"\n        \"\tmsr\tbasepri, r0\t\t\t\t\t\\n\"\n        \"\tbx r14\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.align 4\t\t\t\t\t\t\\n\"\n        \"pxCurrentTCBConst2: .word pxCurrentTCB\t\t\t\t\\n\"\n        );\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvPortStartFirstTask( void )\n{\n    /* Start the first task.  This also clears the bit that indicates the FPU is\n     * in use in case the FPU was used before the scheduler was started - which\n     * would otherwise result in the unnecessary leaving of space in the SVC stack\n     * for lazy saving of FPU registers. */\n    __asm volatile (\n        \" ldr r0, =0xE000ED08 \t\\n\"/* Use the NVIC offset register to locate the stack. */\n        \" ldr r0, [r0] \t\t\t\\n\"\n        \" ldr r0, [r0] \t\t\t\\n\"\n        \" msr msp, r0\t\t\t\\n\"/* Set the msp back to the start of the stack. */\n        \" mov r0, #0\t\t\t\\n\"/* Clear the bit that indicates the FPU is in use, see comment above. */\n        \" msr control, r0\t\t\\n\"\n        \" cpsie i\t\t\t\t\\n\"/* Globally enable interrupts. */\n        \" cpsie f\t\t\t\t\\n\"\n        \" dsb\t\t\t\t\t\\n\"\n        \" isb\t\t\t\t\t\\n\"\n        \" svc 0\t\t\t\t\t\\n\"/* System call to start first task. */\n        \" nop\t\t\t\t\t\\n\"\n        \" .ltorg\t\t\t\t\\n\"\n        );\n}\n/*-----------------------------------------------------------*/\n\n/*\n * See header file for description.\n */\nBaseType_t xPortStartScheduler( void )\n{\n    /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.\n     * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\n    configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );\n\n    /* This port can be used on all revisions of the Cortex-M7 core other than\n     * the r0p1 parts.  r0p1 parts should use the port from the\n     * /source/portable/GCC/ARM_CM7/r0p1 directory. */\n    configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );\n    configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );\n\n    #if ( configASSERT_DEFINED == 1 )\n    {\n        volatile uint32_t ulOriginalPriority;\n        volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\n        volatile uint8_t ucMaxPriorityValue;\n\n        /* Determine the maximum priority from which ISR safe FreeRTOS API\n         * functions can be called.  ISR safe functions are those that end in\n         * \"FromISR\".  FreeRTOS maintains separate thread and ISR API functions to\n         * ensure interrupt entry is as fast and simple as possible.\n         *\n         * Save the interrupt priority value that is about to be clobbered. */\n        ulOriginalPriority = *pucFirstUserPriorityRegister;\n\n        /* Determine the number of priority bits available.  First write to all\n         * possible bits. */\n        *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\n\n        /* Read the value back to see how many bits stuck. */\n        ucMaxPriorityValue = *pucFirstUserPriorityRegister;\n\n        /* Use the same mask on the maximum system call priority. */\n        ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;\n\n        /* Calculate the maximum acceptable priority group value for the number\n         * of bits read back. */\n        ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;\n\n        while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )\n        {\n            ulMaxPRIGROUPValue--;\n            ucMaxPriorityValue <<= ( uint8_t ) 0x01;\n        }\n\n        #ifdef __NVIC_PRIO_BITS\n        {\n            /* Check the CMSIS configuration that defines the number of\n             * priority bits matches the number of priority bits actually queried\n             * from the hardware. */\n            configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );\n        }\n        #endif\n\n        #ifdef configPRIO_BITS\n        {\n            /* Check the FreeRTOS configuration that defines the number of\n             * priority bits matches the number of priority bits actually queried\n             * from the hardware. */\n            configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );\n        }\n        #endif\n\n        /* Shift the priority group value back to its position within the AIRCR\n         * register. */\n        ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;\n        ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;\n\n        /* Restore the clobbered interrupt priority register to its original\n         * value. */\n        *pucFirstUserPriorityRegister = ulOriginalPriority;\n    }\n    #endif /* configASSERT_DEFINED */\n\n    /* Make PendSV and SysTick the lowest priority interrupts. */\n    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;\n    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;\n\n    /* Start the timer that generates the tick ISR.  Interrupts are disabled\n     * here already. */\n    vPortSetupTimerInterrupt();\n\n    /* Initialise the critical nesting count ready for the first task. */\n    uxCriticalNesting = 0;\n\n    /* Ensure the VFP is enabled - it should be anyway. */\n    vPortEnableVFP();\n\n    /* Lazy save always. */\n    *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;\n\n    /* Start the first task. */\n    prvPortStartFirstTask();\n\n    /* Should never get here as the tasks will now be executing!  Call the task\n     * exit error function to prevent compiler warnings about a static function\n     * not being called in the case that the application writer overrides this\n     * functionality by defining configTASK_RETURN_ADDRESS.  Call\n     * vTaskSwitchContext() so link time optimisation does not remove the\n     * symbol. */\n    vTaskSwitchContext();\n    prvTaskExitError();\n\n    /* Should not get here! */\n    return 0;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEndScheduler( void )\n{\n    /* Not implemented in ports where there is nothing to return to.\n     * Artificially force an assert. */\n    configASSERT( uxCriticalNesting == 1000UL );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEnterCritical( void )\n{\n    portDISABLE_INTERRUPTS();\n    uxCriticalNesting++;\n\n    /* This is not the interrupt safe version of the enter critical function so\n     * assert() if it is being called from an interrupt context.  Only API\n     * functions that end in \"FromISR\" can be used in an interrupt.  Only assert if\n     * the critical nesting count is 1 to protect against recursive calls if the\n     * assert function also uses a critical section. */\n    if( uxCriticalNesting == 1 )\n    {\n        configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );\n    }\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortExitCritical( void )\n{\n    configASSERT( uxCriticalNesting );\n    uxCriticalNesting--;\n\n    if( uxCriticalNesting == 0 )\n    {\n        portENABLE_INTERRUPTS();\n    }\n}\n/*-----------------------------------------------------------*/\n\nvoid xPortPendSVHandler( void )\n{\n    /* This is a naked function. */\n\n    __asm volatile\n    (\n        \"\tmrs r0, psp\t\t\t\t\t\t\t\\n\"\n        \"\tisb\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr\tr3, pxCurrentTCBConst\t\t\t\\n\"/* Get the location of the current TCB. */\n        \"\tldr\tr2, [r3]\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\ttst r14, #0x10\t\t\t\t\t\t\\n\"/* Is the task using the FPU context?  If so, push high vfp registers. */\n        \"\tit eq\t\t\t\t\t\t\t\t\\n\"\n        \"\tvstmdbeq r0!, {s16-s31}\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tstmdb r0!, {r4-r11, r14}\t\t\t\\n\"/* Save the core registers. */\n        \"\tstr r0, [r2]\t\t\t\t\t\t\\n\"/* Save the new top of stack into the first member of the TCB. */\n        \"\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tstmdb sp!, {r0, r3}\t\t\t\t\t\\n\"\n        \"\tmov r0, %0 \t\t\t\t\t\t\t\\n\"\n        \"\tmsr basepri, r0\t\t\t\t\t\t\\n\"\n        \"\tdsb\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tisb\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tbl vTaskSwitchContext\t\t\t\t\\n\"\n        \"\tmov r0, #0\t\t\t\t\t\t\t\\n\"\n        \"\tmsr basepri, r0\t\t\t\t\t\t\\n\"\n        \"\tldmia sp!, {r0, r3}\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r1, [r3]\t\t\t\t\t\t\\n\"/* The first item in pxCurrentTCB is the task top of stack. */\n        \"\tldr r0, [r1]\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldmia r0!, {r4-r11, r14}\t\t\t\\n\"/* Pop the core registers. */\n        \"\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\ttst r14, #0x10\t\t\t\t\t\t\\n\"/* Is the task using the FPU context?  If so, pop the high vfp registers too. */\n        \"\tit eq\t\t\t\t\t\t\t\t\\n\"\n        \"\tvldmiaeq r0!, {s16-s31}\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmsr psp, r0\t\t\t\t\t\t\t\\n\"\n        \"\tisb\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\\n\"\n        #ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata workaround. */\n            #if WORKAROUND_PMU_CM001 == 1\n                \"\t\t\tpush { r14 }\t\t\t\t\\n\"\n                \"\t\t\tpop { pc }\t\t\t\t\t\\n\"\n            #endif\n        #endif\n        \"\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tbx r14\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.align 4\t\t\t\t\t\t\t\\n\"\n        \"pxCurrentTCBConst: .word pxCurrentTCB\t\\n\"\n        ::\"i\" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid xPortSysTickHandler( void )\n{\n    /* The SysTick runs at the lowest interrupt priority, so when this interrupt\n     * executes all interrupts must be unmasked.  There is therefore no need to\n     * save and then restore the interrupt mask value as its value is already\n     * known. */\n    portDISABLE_INTERRUPTS();\n    {\n        /* Increment the RTOS tick. */\n        if( xTaskIncrementTick() != pdFALSE )\n        {\n            /* A context switch is required.  Context switching is performed in\n             * the PendSV interrupt.  Pend the PendSV interrupt. */\n            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\n        }\n    }\n    portENABLE_INTERRUPTS();\n}\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TICKLESS_IDLE == 1 )\n\n    __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )\n    {\n        uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;\n        TickType_t xModifiableIdleTime;\n\n        /* Make sure the SysTick reload value does not overflow the counter. */\n        if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\n        {\n            xExpectedIdleTime = xMaximumPossibleSuppressedTicks;\n        }\n\n        /* Enter a critical section but don't use the taskENTER_CRITICAL()\n         * method as that will mask interrupts that should exit sleep mode. */\n        __asm volatile ( \"cpsid i\" ::: \"memory\" );\n        __asm volatile ( \"dsb\" );\n        __asm volatile ( \"isb\" );\n\n        /* If a context switch is pending or a task is waiting for the scheduler\n         * to be unsuspended then abandon the low power entry. */\n        if( eTaskConfirmSleepModeStatus() == eAbortSleep )\n        {\n            /* Re-enable interrupts - see comments above the cpsid instruction\n             * above. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n        }\n        else\n        {\n            /* Stop the SysTick momentarily.  The time the SysTick is stopped for\n             * is accounted for as best it can be, but using the tickless mode will\n             * inevitably result in some tiny drift of the time maintained by the\n             * kernel with respect to calendar time. */\n            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );\n\n            /* Use the SysTick current-value register to determine the number of\n             * SysTick decrements remaining until the next tick interrupt.  If the\n             * current-value register is zero, then there are actually\n             * ulTimerCountsForOneTick decrements remaining, not zero, because the\n             * SysTick requests the interrupt when decrementing from 1 to 0. */\n            ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n\n            if( ulSysTickDecrementsLeft == 0 )\n            {\n                ulSysTickDecrementsLeft = ulTimerCountsForOneTick;\n            }\n\n            /* Calculate the reload value required to wait xExpectedIdleTime\n             * tick periods.  -1 is used because this code normally executes part\n             * way through the first tick period.  But if the SysTick IRQ is now\n             * pending, then clear the IRQ, suppressing the first tick, and correct\n             * the reload value to reflect that the second tick period is already\n             * underway.  The expected idle time is always at least two ticks. */\n            ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );\n\n            if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )\n            {\n                portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;\n                ulReloadValue -= ulTimerCountsForOneTick;\n            }\n\n            if( ulReloadValue > ulStoppedTimerCompensation )\n            {\n                ulReloadValue -= ulStoppedTimerCompensation;\n            }\n\n            /* Set the new reload value. */\n            portNVIC_SYSTICK_LOAD_REG = ulReloadValue;\n\n            /* Clear the SysTick count flag and set the count value back to\n             * zero. */\n            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n            /* Restart SysTick. */\n            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\n\n            /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can\n             * set its parameter to 0 to indicate that its implementation contains\n             * its own wait for interrupt or wait for event instruction, and so wfi\n             * should not be executed again.  However, the original expected idle\n             * time variable must remain unmodified, so a copy is taken. */\n            xModifiableIdleTime = xExpectedIdleTime;\n            configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\n\n            if( xModifiableIdleTime > 0 )\n            {\n                __asm volatile ( \"dsb\" ::: \"memory\" );\n                __asm volatile ( \"wfi\" );\n                __asm volatile ( \"isb\" );\n            }\n\n            configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\n\n            /* Re-enable interrupts to allow the interrupt that brought the MCU\n             * out of sleep mode to execute immediately.  See comments above\n             * the cpsid instruction above. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n            __asm volatile ( \"dsb\" );\n            __asm volatile ( \"isb\" );\n\n            /* Disable interrupts again because the clock is about to be stopped\n             * and interrupts that execute while the clock is stopped will increase\n             * any slippage between the time maintained by the RTOS and calendar\n             * time. */\n            __asm volatile ( \"cpsid i\" ::: \"memory\" );\n            __asm volatile ( \"dsb\" );\n            __asm volatile ( \"isb\" );\n\n            /* Disable the SysTick clock without reading the\n             * portNVIC_SYSTICK_CTRL_REG register to ensure the\n             * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,\n             * the time the SysTick is stopped for is accounted for as best it can\n             * be, but using the tickless mode will inevitably result in some tiny\n             * drift of the time maintained by the kernel with respect to calendar\n             * time*/\n            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );\n\n            /* Determine whether the SysTick has already counted to zero. */\n            if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n            {\n                uint32_t ulCalculatedLoadValue;\n\n                /* The tick interrupt ended the sleep (or is now pending), and\n                 * a new tick period has started.  Reset portNVIC_SYSTICK_LOAD_REG\n                 * with whatever remains of the new tick period. */\n                ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\n\n                /* Don't allow a tiny value, or values that have somehow\n                 * underflowed because the post sleep hook did something\n                 * that took too long or because the SysTick current-value register\n                 * is zero. */\n                if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )\n                {\n                    ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );\n                }\n\n                portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;\n\n                /* As the pending tick will be processed as soon as this\n                 * function exits, the tick value maintained by the tick is stepped\n                 * forward by one less than the time spent waiting. */\n                ulCompleteTickPeriods = xExpectedIdleTime - 1UL;\n            }\n            else\n            {\n                /* Something other than the tick interrupt ended the sleep. */\n\n                /* Use the SysTick current-value register to determine the\n                 * number of SysTick decrements remaining until the expected idle\n                 * time would have ended. */\n                ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n                #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )\n                {\n                    /* If the SysTick is not using the core clock, the current-\n                     * value register might still be zero here.  In that case, the\n                     * SysTick didn't load from the reload register, and there are\n                     * ulReloadValue decrements remaining in the expected idle\n                     * time, not zero. */\n                    if( ulSysTickDecrementsLeft == 0 )\n                    {\n                        ulSysTickDecrementsLeft = ulReloadValue;\n                    }\n                }\n                #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */\n\n                /* Work out how long the sleep lasted rounded to complete tick\n                 * periods (not the ulReload value which accounted for part\n                 * ticks). */\n                ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;\n\n                /* How many complete tick periods passed while the processor\n                 * was waiting? */\n                ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;\n\n                /* The reload value is set to whatever fraction of a single tick\n                 * period remains. */\n                portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;\n            }\n\n            /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,\n             * then set portNVIC_SYSTICK_LOAD_REG back to its standard value.  If\n             * the SysTick is not using the core clock, temporarily configure it to\n             * use the core clock.  This configuration forces the SysTick to load\n             * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next\n             * cycle of the other clock.  Then portNVIC_SYSTICK_LOAD_REG is ready\n             * to receive the standard value immediately. */\n            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n            portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n            #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )\n            {\n                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n            }\n            #else\n            {\n                /* The temporary usage of the core clock has served its purpose,\n                 * as described above.  Resume usage of the other clock. */\n                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\n\n                if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n                {\n                    /* The partial tick period already ended.  Be sure the SysTick\n                     * counts it only once. */\n                    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;\n                }\n\n                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n            }\n            #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */\n\n            /* Step the tick to account for any tick periods that elapsed. */\n            vTaskStepTick( ulCompleteTickPeriods );\n\n            /* Exit with interrupts enabled. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n        }\n    }\n\n#endif /* #if configUSE_TICKLESS_IDLE */\n/*-----------------------------------------------------------*/\n\n/*\n * Setup the systick timer to generate the tick interrupts at the required\n * frequency.\n */\n__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )\n{\n    /* Calculate the constants required to configure the tick interrupt. */\n    #if ( configUSE_TICKLESS_IDLE == 1 )\n    {\n        ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );\n        xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;\n        ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\n    }\n    #endif /* configUSE_TICKLESS_IDLE */\n\n    /* Stop and clear the SysTick. */\n    portNVIC_SYSTICK_CTRL_REG = 0UL;\n    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n    /* Configure SysTick to interrupt at the requested rate. */\n    portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\n    portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );\n}\n/*-----------------------------------------------------------*/\n\n/* This is a naked function. */\nstatic void vPortEnableVFP( void )\n{\n    __asm volatile\n    (\n        \"\tldr.w r0, =0xE000ED88\t\t\\n\"/* The FPU enable bits are in the CPACR. */\n        \"\tldr r1, [r0]\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\\n\"\n        \"\torr r1, r1, #( 0xf << 20 )\t\\n\"/* Enable CP10 and CP11 coprocessors, then save back. */\n        \"\tstr r1, [r0]\t\t\t\t\\n\"\n        \"\tbx r14\t\t\t\t\t\t\\n\"\n        \"\t.ltorg\t\t\t\t\t\t\\n\"\n    );\n}\n/*-----------------------------------------------------------*/\n\n#if ( configASSERT_DEFINED == 1 )\n\n    void vPortValidateInterruptPriority( void )\n    {\n        uint32_t ulCurrentInterrupt;\n        uint8_t ucCurrentPriority;\n\n        /* Obtain the number of the currently executing interrupt. */\n        __asm volatile ( \"mrs %0, ipsr\" : \"=r\" ( ulCurrentInterrupt )::\"memory\" );\n\n        /* Is the interrupt number a user defined interrupt? */\n        if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )\n        {\n            /* Look up the interrupt's priority. */\n            ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];\n\n            /* The following assertion will fail if a service routine (ISR) for\n             * an interrupt that has been assigned a priority above\n             * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\n             * function.  ISR safe FreeRTOS API functions must *only* be called\n             * from interrupts that have been assigned a priority at or below\n             * configMAX_SYSCALL_INTERRUPT_PRIORITY.\n             *\n             * Numerically low interrupt priority numbers represent logically high\n             * interrupt priorities, therefore the priority of the interrupt must\n             * be set to a value equal to or numerically *higher* than\n             * configMAX_SYSCALL_INTERRUPT_PRIORITY.\n             *\n             * Interrupts that\tuse the FreeRTOS API must not be left at their\n             * default priority of\tzero as that is the highest possible priority,\n             * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,\n             * and\ttherefore also guaranteed to be invalid.\n             *\n             * FreeRTOS maintains separate thread and ISR API functions to ensure\n             * interrupt entry is as fast and simple as possible.\n             *\n             * The following links provide detailed information:\n             * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html\n             * https://www.FreeRTOS.org/FAQHelp.html */\n            configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );\n        }\n\n        /* Priority grouping:  The interrupt controller (NVIC) allows the bits\n         * that define each interrupt's priority to be split between bits that\n         * define the interrupt's pre-emption priority bits and bits that define\n         * the interrupt's sub-priority.  For simplicity all bits must be defined\n         * to be pre-emption priority bits.  The following assertion will fail if\n         * this is not the case (if some bits represent a sub-priority).\n         *\n         * If the application only uses CMSIS libraries for interrupt\n         * configuration then the correct setting can be achieved on all Cortex-M\n         * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the\n         * scheduler.  Note however that some vendor specific peripheral libraries\n         * assume a non-zero priority group setting, in which cases using a value\n         * of zero will result in unpredictable behaviour. */\n        configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );\n    }\n\n#endif /* configASSERT_DEFINED */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM4F/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n\n#ifndef PORTMACRO_H\n    #define PORTMACRO_H\n\n    #ifdef __cplusplus\n        extern \"C\" {\n    #endif\n\n/*-----------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the\n * given hardware and compiler.\n *\n * These settings should not be altered.\n *-----------------------------------------------------------\n */\n\n/* Type definitions. */\n    #define portCHAR          char\n    #define portFLOAT         float\n    #define portDOUBLE        double\n    #define portLONG          long\n    #define portSHORT         short\n    #define portSTACK_TYPE    uint32_t\n    #define portBASE_TYPE     long\n\n    typedef portSTACK_TYPE   StackType_t;\n    typedef long             BaseType_t;\n    typedef unsigned long    UBaseType_t;\n\n    #if ( configUSE_16_BIT_TICKS == 1 )\n        typedef uint16_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffff\n    #else\n        typedef uint32_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL\n\n/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\n * not need to be guarded with a critical section. */\n        #define portTICK_TYPE_IS_ATOMIC    1\n    #endif\n/*-----------------------------------------------------------*/\n\n/* Architecture specifics. */\n    #define portSTACK_GROWTH      ( -1 )\n    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\n    #define portBYTE_ALIGNMENT    8\n    #define portDONT_DISCARD      __attribute__( ( used ) )\n/*-----------------------------------------------------------*/\n\n/* Scheduler utilities. */\n    #define portYIELD()                                 \\\n    {                                                   \\\n        /* Set a PendSV to request a context switch. */ \\\n        portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \\\n                                                        \\\n        /* Barriers are normally not required but do ensure the code is completely \\\n         * within the specified behaviour for the architecture. */ \\\n        __asm volatile ( \"dsb\" ::: \"memory\" );                     \\\n        __asm volatile ( \"isb\" );                                  \\\n    }\n\n    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )\n    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )\n    #define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 )\n    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )\n/*-----------------------------------------------------------*/\n\n/* Critical section management. */\n    extern void vPortEnterCritical( void );\n    extern void vPortExitCritical( void );\n    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulPortRaiseBASEPRI()\n    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vPortSetBASEPRI( x )\n    #define portDISABLE_INTERRUPTS()                  vPortRaiseBASEPRI()\n    #define portENABLE_INTERRUPTS()                   vPortSetBASEPRI( 0 )\n    #define portENTER_CRITICAL()                      vPortEnterCritical()\n    #define portEXIT_CRITICAL()                       vPortExitCritical()\n\n/*-----------------------------------------------------------*/\n\n/* Task function macros as described on the FreeRTOS.org WEB site.  These are\n * not necessary for to use this port.  They are defined so the common demo files\n * (which build with all the ports) will build. */\n    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )\n    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )\n/*-----------------------------------------------------------*/\n\n/* Tickless idle/low power functionality. */\n    #ifndef portSUPPRESS_TICKS_AND_SLEEP\n        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );\n        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )\n    #endif\n/*-----------------------------------------------------------*/\n\n/* Architecture specific optimisations. */\n    #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION\n        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1\n    #endif\n\n    #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1\n\n/* Generic helper function. */\n        __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )\n        {\n            uint8_t ucReturn;\n\n            __asm volatile ( \"clz %0, %1\" : \"=r\" ( ucReturn ) : \"r\" ( ulBitmap ) : \"memory\" );\n\n            return ucReturn;\n        }\n\n/* Check the configuration. */\n        #if ( configMAX_PRIORITIES > 32 )\n            #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.\n        #endif\n\n/* Store/clear the ready priorities in a bit map. */\n        #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )\n        #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )\n\n/*-----------------------------------------------------------*/\n\n        #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )\n\n    #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */\n\n/*-----------------------------------------------------------*/\n\n    #ifdef configASSERT\n        void vPortValidateInterruptPriority( void );\n        #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()\n    #endif\n\n/* portNOP() is not required by this port. */\n    #define portNOP()\n\n    #define portINLINE              __inline\n\n    #ifndef portFORCE_INLINE\n        #define portFORCE_INLINE    inline __attribute__( ( always_inline ) )\n    #endif\n\n    portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )\n    {\n        uint32_t ulCurrentInterrupt;\n        BaseType_t xReturn;\n\n        /* Obtain the number of the currently executing interrupt. */\n        __asm volatile ( \"mrs %0, ipsr\" : \"=r\" ( ulCurrentInterrupt )::\"memory\" );\n\n        if( ulCurrentInterrupt == 0 )\n        {\n            xReturn = pdFALSE;\n        }\n        else\n        {\n            xReturn = pdTRUE;\n        }\n\n        return xReturn;\n    }\n\n/*-----------------------------------------------------------*/\n\n    portFORCE_INLINE static void vPortRaiseBASEPRI( void )\n    {\n        uint32_t ulNewBASEPRI;\n\n        __asm volatile\n        (\n            \"\tmov %0, %1\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\\\n            \"\tmsr basepri, %0\t\t\t\t\t\t\t\t\t\t\t\\n\"\\\n            \"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\\\n            \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\\\n            : \"=r\" ( ulNewBASEPRI ) : \"i\" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : \"memory\"\n        );\n    }\n\n/*-----------------------------------------------------------*/\n\n    portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )\n    {\n        uint32_t ulOriginalBASEPRI, ulNewBASEPRI;\n\n        __asm volatile\n        (\n            \"\tmrs %0, basepri\t\t\t\t\t\t\t\t\t\t\t\\n\"\\\n            \"\tmov %1, %2\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\\\n            \"\tmsr basepri, %1\t\t\t\t\t\t\t\t\t\t\t\\n\"\\\n            \"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\\\n            \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\\\n            : \"=r\" ( ulOriginalBASEPRI ), \"=r\" ( ulNewBASEPRI ) : \"i\" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : \"memory\"\n        );\n\n        /* This return will not be reached but is necessary to prevent compiler\n         * warnings. */\n        return ulOriginalBASEPRI;\n    }\n/*-----------------------------------------------------------*/\n\n    portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )\n    {\n        __asm volatile\n        (\n            \"\tmsr basepri, %0\t\"::\"r\" ( ulNewMaskValue ) : \"memory\"\n        );\n    }\n/*-----------------------------------------------------------*/\n\n    #define portMEMORY_BARRIER()    __asm volatile ( \"\" ::: \"memory\" )\n\n    #ifdef __cplusplus\n        }\n    #endif\n\n#endif /* PORTMACRO_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM4_MPU/port.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/*-----------------------------------------------------------\n* Implementation of functions defined in portable.h for the ARM CM4 MPU port.\n*----------------------------------------------------------*/\n\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\n * all the API functions to use the MPU wrappers.  That should only be done when\n * task.h is included from an application file. */\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n#ifndef __VFP_FP__\n    #error This port can only be used when the project options are configured to enable hardware floating point support.\n#endif\n\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n#ifndef configSYSTICK_CLOCK_HZ\n    #define configSYSTICK_CLOCK_HZ    configCPU_CLOCK_HZ\n    /* Ensure the SysTick is clocked at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK      ( 1UL << 2UL )\n#else\n\n/* The way the SysTick is clocked is not modified in case it is not the same\n * as the core. */\n    #define portNVIC_SYSTICK_CLK    ( 0 )\n#endif\n\n#ifndef configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS\n    #warning \"configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS is not defined. We recommend defining it to 0 in FreeRTOSConfig.h for better security.\"\n    #define configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS    1\n#endif\n\n/* Constants required to access and manipulate the NVIC. */\n#define portNVIC_SYSTICK_CTRL_REG                 ( *( ( volatile uint32_t * ) 0xe000e010 ) )\n#define portNVIC_SYSTICK_LOAD_REG                 ( *( ( volatile uint32_t * ) 0xe000e014 ) )\n#define portNVIC_SYSTICK_CURRENT_VALUE_REG        ( *( ( volatile uint32_t * ) 0xe000e018 ) )\n#define portNVIC_SHPR3_REG                        ( *( ( volatile uint32_t * ) 0xe000ed20 ) )\n#define portNVIC_SHPR2_REG                        ( *( ( volatile uint32_t * ) 0xe000ed1c ) )\n#define portNVIC_SYS_CTRL_STATE_REG               ( *( ( volatile uint32_t * ) 0xe000ed24 ) )\n#define portNVIC_MEM_FAULT_ENABLE                 ( 1UL << 16UL )\n\n/* Constants used to detect Cortex-M7 r0p0 and r0p1 cores, and ensure\n * that a work around is active for errata 837070. */\n#define portCPUID                                 ( *( ( volatile uint32_t * ) 0xE000ed00 ) )\n#define portCORTEX_M7_r0p1_ID                     ( 0x410FC271UL )\n#define portCORTEX_M7_r0p0_ID                     ( 0x410FC270UL )\n\n/* Constants required to access and manipulate the MPU. */\n#define portMPU_TYPE_REG                          ( *( ( volatile uint32_t * ) 0xe000ed90 ) )\n#define portMPU_REGION_BASE_ADDRESS_REG           ( *( ( volatile uint32_t * ) 0xe000ed9C ) )\n#define portMPU_REGION_ATTRIBUTE_REG              ( *( ( volatile uint32_t * ) 0xe000edA0 ) )\n#define portMPU_CTRL_REG                          ( *( ( volatile uint32_t * ) 0xe000ed94 ) )\n#define portEXPECTED_MPU_TYPE_VALUE               ( configTOTAL_MPU_REGIONS << 8UL )\n#define portMPU_ENABLE                            ( 0x01UL )\n#define portMPU_BACKGROUND_ENABLE                 ( 1UL << 2UL )\n#define portPRIVILEGED_EXECUTION_START_ADDRESS    ( 0UL )\n#define portMPU_REGION_VALID                      ( 0x10UL )\n#define portMPU_REGION_ENABLE                     ( 0x01UL )\n#define portPERIPHERALS_START_ADDRESS             0x40000000UL\n#define portPERIPHERALS_END_ADDRESS               0x5FFFFFFFUL\n\n/* Constants required to access and manipulate the SysTick. */\n#define portNVIC_SYSTICK_INT                      ( 0x00000002UL )\n#define portNVIC_SYSTICK_ENABLE                   ( 0x00000001UL )\n#define portNVIC_PENDSV_PRI                       ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\n#define portNVIC_SYSTICK_PRI                      ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\n#define portNVIC_SVC_PRI                          ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )\n\n/* Constants required to manipulate the VFP. */\n#define portFPCCR                                 ( ( volatile uint32_t * ) 0xe000ef34UL ) /* Floating point context control register. */\n#define portASPEN_AND_LSPEN_BITS                  ( 0x3UL << 30UL )\n\n/* Constants required to set up the initial stack. */\n#define portINITIAL_XPSR                          ( 0x01000000UL )\n#define portINITIAL_EXC_RETURN                    ( 0xfffffffdUL )\n#define portINITIAL_CONTROL_IF_UNPRIVILEGED       ( 0x03 )\n#define portINITIAL_CONTROL_IF_PRIVILEGED         ( 0x02 )\n\n/* Constants required to check the validity of an interrupt priority. */\n#define portFIRST_USER_INTERRUPT_NUMBER           ( 16 )\n#define portNVIC_IP_REGISTERS_OFFSET_16           ( 0xE000E3F0 )\n#define portAIRCR_REG                             ( *( ( volatile uint32_t * ) 0xE000ED0C ) )\n#define portMAX_8_BIT_VALUE                       ( ( uint8_t ) 0xff )\n#define portTOP_BIT_OF_BYTE                       ( ( uint8_t ) 0x80 )\n#define portMAX_PRIGROUP_BITS                     ( ( uint8_t ) 7 )\n#define portPRIORITY_GROUP_MASK                   ( 0x07UL << 8UL )\n#define portPRIGROUP_SHIFT                        ( 8UL )\n\n/* Offsets in the stack to the parameters when inside the SVC handler. */\n#define portOFFSET_TO_PC                          ( 6 )\n\n/* For strict compliance with the Cortex-M spec the task start address should\n * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */\n#define portSTART_ADDRESS_MASK                    ( ( StackType_t ) 0xfffffffeUL )\n\n/*\n * Configure a number of standard MPU regions that are used by all tasks.\n */\nstatic void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\n\n/*\n * Return the smallest MPU region size that a given number of bytes will fit\n * into.  The region size is returned as the value that should be programmed\n * into the region attribute register for that region.\n */\nstatic uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;\n\n/*\n * Setup the timer to generate the tick interrupts.  The implementation in this\n * file is weak to allow application writers to change the timer used to\n * generate the tick interrupt.\n */\nvoid vPortSetupTimerInterrupt( void );\n\n/*\n * Standard FreeRTOS exception handlers.\n */\nvoid xPortPendSVHandler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\nvoid xPortSysTickHandler( void ) PRIVILEGED_FUNCTION;\nvoid vPortSVCHandler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/*\n * Starts the scheduler by restoring the context of the first task to run.\n */\nstatic void prvRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/*\n * C portion of the SVC handler.  The SVC handler is split between an asm entry\n * and a C wrapper for simplicity of coding and maintenance.\n */\nstatic void prvSVCHandler( uint32_t * pulRegisters ) __attribute__( ( noinline ) ) PRIVILEGED_FUNCTION;\n\n/*\n * Function to enable the VFP.\n */\nstatic void vPortEnableVFP( void ) __attribute__( ( naked ) );\n\n/**\n * @brief Checks whether or not the processor is privileged.\n *\n * @return 1 if the processor is already privileged, 0 otherwise.\n */\nBaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );\n\n/**\n * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\n * register.\n *\n * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.\n *  Bit[0] = 0 --> The processor is running privileged\n *  Bit[0] = 1 --> The processor is running unprivileged.\n */\nvoid vResetPrivilege( void ) __attribute__( ( naked ) );\n\n/**\n * @brief Enter critical section.\n */\n#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )\n    void vPortEnterCritical( void ) FREERTOS_SYSTEM_CALL;\n#else\n    void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;\n#endif\n\n/**\n * @brief Exit from critical section.\n */\n#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )\n    void vPortExitCritical( void ) FREERTOS_SYSTEM_CALL;\n#else\n    void vPortExitCritical( void ) PRIVILEGED_FUNCTION;\n#endif\n/*-----------------------------------------------------------*/\n\n/* Each task maintains its own interrupt status in the critical nesting\n * variable.  Note this is not saved as part of the task context as context\n * switches can only occur when uxCriticalNesting is zero. */\nstatic UBaseType_t uxCriticalNesting = 0xaaaaaaaa;\n\n/*\n * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure\n * FreeRTOS API functions are not called from interrupts that have been assigned\n * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.\n */\n#if ( configASSERT_DEFINED == 1 )\n    static uint8_t ucMaxSysCallPriority = 0;\n    static uint32_t ulMaxPRIGROUPValue = 0;\n    static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;\n#endif /* configASSERT_DEFINED */\n\n/*-----------------------------------------------------------*/\n\n/*\n * See header file for description.\n */\nStackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,\n                                     TaskFunction_t pxCode,\n                                     void * pvParameters,\n                                     BaseType_t xRunPrivileged )\n{\n    /* Simulate the stack frame as it would be created by a context switch\n     * interrupt. */\n    pxTopOfStack--;                                                      /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\n    *pxTopOfStack = portINITIAL_XPSR;                                    /* xPSR */\n    pxTopOfStack--;\n    *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */\n    pxTopOfStack--;\n    *pxTopOfStack = 0;                                                   /* LR */\n    pxTopOfStack -= 5;                                                   /* R12, R3, R2 and R1. */\n    *pxTopOfStack = ( StackType_t ) pvParameters;                        /* R0 */\n\n    /* A save method is being used that requires each task to maintain its\n     * own exec return value. */\n    pxTopOfStack--;\n    *pxTopOfStack = portINITIAL_EXC_RETURN;\n\n    pxTopOfStack -= 9; /* R11, R10, R9, R8, R7, R6, R5 and R4. */\n\n    if( xRunPrivileged == pdTRUE )\n    {\n        *pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED;\n    }\n    else\n    {\n        *pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED;\n    }\n\n    return pxTopOfStack;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortSVCHandler( void )\n{\n    /* Assumes psp was in use. */\n    __asm volatile\n    (\n        #ifndef USE_PROCESS_STACK   /* Code should not be required if a main() is using the process stack. */\n            \"\ttst lr, #4\t\t\t\t\t\t\\n\"\n            \"\tite eq\t\t\t\t\t\t\t\\n\"\n            \"\tmrseq r0, msp\t\t\t\t\t\\n\"\n            \"\tmrsne r0, psp\t\t\t\t\t\\n\"\n        #else\n            \"\tmrs r0, psp\t\t\t\t\t\t\\n\"\n        #endif\n        \"\tb %0\t\t\t\t\t\t\t\\n\"\n        ::\"i\" ( prvSVCHandler ) : \"r0\", \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvSVCHandler( uint32_t * pulParam )\n{\n    uint8_t ucSVCNumber;\n    uint32_t ulPC;\n\n    #if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )\n        #if defined( __ARMCC_VERSION )\n\n            /* Declaration when these variable are defined in code instead of being\n             * exported from linker scripts. */\n            extern uint32_t * __syscalls_flash_start__;\n            extern uint32_t * __syscalls_flash_end__;\n        #else\n            /* Declaration when these variable are exported from linker scripts. */\n            extern uint32_t __syscalls_flash_start__[];\n            extern uint32_t __syscalls_flash_end__[];\n        #endif /* #if defined( __ARMCC_VERSION ) */\n    #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */\n\n    /* The stack contains: r0, r1, r2, r3, r12, LR, PC and xPSR.  The first\n     * argument (r0) is pulParam[ 0 ]. */\n    ulPC = pulParam[ portOFFSET_TO_PC ];\n    ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];\n\n    switch( ucSVCNumber )\n    {\n        case portSVC_START_SCHEDULER:\n            portNVIC_SHPR2_REG |= portNVIC_SVC_PRI;\n            prvRestoreContextOfFirstTask();\n            break;\n\n        case portSVC_YIELD:\n            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\n\n            /* Barriers are normally not required\n             * but do ensure the code is completely\n             * within the specified behaviour for the\n             * architecture. */\n            __asm volatile ( \"dsb\" ::: \"memory\" );\n            __asm volatile ( \"isb\" );\n\n            break;\n\n            #if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )\n                case portSVC_RAISE_PRIVILEGE: /* Only raise the privilege, if the\n                                               * svc was raised from any of the\n                                               * system calls. */\n\n                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&\n                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )\n                    {\n                        __asm volatile\n                        (\n                            \"\tmrs r1, control\t\t\\n\"/* Obtain current control value. */\n                            \"\tbic r1, #1\t\t\t\\n\"/* Set privilege bit. */\n                            \"\tmsr control, r1\t\t\\n\"/* Write back new control value. */\n                            ::: \"r1\", \"memory\"\n                        );\n                    }\n\n                    break;\n            #else /* if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */\n                case portSVC_RAISE_PRIVILEGE:\n                    __asm volatile\n                    (\n                        \"\tmrs r1, control\t\t\\n\"/* Obtain current control value. */\n                        \"\tbic r1, #1\t\t\t\\n\"/* Set privilege bit. */\n                        \"\tmsr control, r1\t\t\\n\"/* Write back new control value. */\n                        ::: \"r1\", \"memory\"\n                    );\n                    break;\n                    #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */\n\n                default: /* Unknown SVC call. */\n                    break;\n    }\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvRestoreContextOfFirstTask( void )\n{\n    __asm volatile\n    (\n        \"\tldr r0, =0xE000ED08\t\t\t\t\\n\"/* Use the NVIC offset register to locate the stack. */\n        \"\tldr r0, [r0]\t\t\t\t\t\\n\"\n        \"\tldr r0, [r0]\t\t\t\t\t\\n\"\n        \"\tmsr msp, r0\t\t\t\t\t\t\\n\"/* Set the msp back to the start of the stack. */\n        \"\tldr\tr3, pxCurrentTCBConst2\t\t\\n\"/* Restore the context. */\n        \"\tldr r1, [r3]\t\t\t\t\t\\n\"\n        \"\tldr r0, [r1]\t\t\t\t\t\\n\"/* The first item in the TCB is the task top of stack. */\n        \"\tadd r1, r1, #4\t\t\t\t\t\\n\"/* Move onto the second item in the TCB... */\n        \"\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tdmb\t\t\t\t\t\t\t\t\\n\"/* Complete outstanding transfers before disabling MPU. */\n        \"\tldr r2, =0xe000ed94\t\t\t\t\\n\"/* MPU_CTRL register. */\n        \"\tldr r3, [r2]\t\t\t\t\t\\n\"/* Read the value of MPU_CTRL. */\n        \"\tbic r3, #1\t\t\t\t\t\t\\n\"/* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */\n        \"\tstr r3, [r2]\t\t\t\t\t\\n\"/* Disable MPU. */\n        \"\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r2, =0xe000ed9c\t\t\t\t\\n\"/* Region Base Address register. */\n        \"\tldmia r1!, {r4-r11}\t\t\t\t\\n\"/* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */\n        \"\tstmia r2, {r4-r11}\t\t\t\t\\n\"/* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */\n        \"\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configTOTAL_MPU_REGIONS == 16 )\n            \"\tldmia r1!, {r4-r11}\t\t\t\t\\n\"/* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */\n            \"\tstmia r2, {r4-r11}\t\t\t\t\\n\"/* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */\n            \"\tldmia r1!, {r4-r11}\t\t\t\t\\n\"/* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */\n            \"\tstmia r2, {r4-r11}\t\t\t\t\\n\"/* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */\n        #endif /* configTOTAL_MPU_REGIONS == 16. */\n        \"\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r2, =0xe000ed94\t\t\t\t\\n\"/* MPU_CTRL register. */\n        \"\tldr r3, [r2]\t\t\t\t\t\\n\"/* Read the value of MPU_CTRL. */\n        \"\torr r3, #1\t\t\t\t\t\t\\n\"/* r3 = r3 | 1 i.e. Set the bit 0 in r3. */\n        \"\tstr r3, [r2]\t\t\t\t\t\\n\"/* Enable MPU. */\n        \"\tdsb\t\t\t\t\t\t\t\t\\n\"/* Force memory writes before continuing. */\n        \"\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldmia r0!, {r3-r11, r14}\t\t\\n\"/* Pop the registers that are not automatically saved on exception entry. */\n        \"\tmsr control, r3\t\t\t\t\t\\n\"\n        \"\tmsr psp, r0\t\t\t\t\t\t\\n\"/* Restore the task stack pointer. */\n        \"\tmov r0, #0\t\t\t\t\t\t\\n\"\n        \"\tmsr\tbasepri, r0\t\t\t\t\t\\n\"\n        \"\tbx r14\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.ltorg\t\t\t\t\t\t\t\\n\"/* Assemble current literal pool to avoid offset-out-of-bound errors with lto. */\n        \"\t.align 4\t\t\t\t\t\t\\n\"\n        \"pxCurrentTCBConst2: .word pxCurrentTCB\t\\n\"\n    );\n}\n/*-----------------------------------------------------------*/\n\n/*\n * See header file for description.\n */\nBaseType_t xPortStartScheduler( void )\n{\n    /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See\n     * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\n    configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) );\n\n    /* Errata 837070 workaround must only be enabled on Cortex-M7 r0p0\n     * and r0p1 cores. */\n    #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )\n        configASSERT( ( portCPUID == portCORTEX_M7_r0p1_ID ) || ( portCPUID == portCORTEX_M7_r0p0_ID ) );\n    #else\n        /* When using this port on a Cortex-M7 r0p0 or r0p1 core, define\n         * configENABLE_ERRATA_837070_WORKAROUND to 1 in your\n         * FreeRTOSConfig.h. */\n        configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );\n        configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );\n    #endif\n\n    #if ( configASSERT_DEFINED == 1 )\n        {\n            volatile uint32_t ulOriginalPriority;\n            volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\n            volatile uint8_t ucMaxPriorityValue;\n\n            /* Determine the maximum priority from which ISR safe FreeRTOS API\n             * functions can be called.  ISR safe functions are those that end in\n             * \"FromISR\".  FreeRTOS maintains separate thread and ISR API functions to\n             * ensure interrupt entry is as fast and simple as possible.\n             *\n             * Save the interrupt priority value that is about to be clobbered. */\n            ulOriginalPriority = *pucFirstUserPriorityRegister;\n\n            /* Determine the number of priority bits available.  First write to all\n             * possible bits. */\n            *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\n\n            /* Read the value back to see how many bits stuck. */\n            ucMaxPriorityValue = *pucFirstUserPriorityRegister;\n\n            /* Use the same mask on the maximum system call priority. */\n            ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;\n\n            /* Calculate the maximum acceptable priority group value for the number\n             * of bits read back. */\n            ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;\n\n            while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )\n            {\n                ulMaxPRIGROUPValue--;\n                ucMaxPriorityValue <<= ( uint8_t ) 0x01;\n            }\n\n            #ifdef __NVIC_PRIO_BITS\n                {\n                    /* Check the CMSIS configuration that defines the number of\n                     * priority bits matches the number of priority bits actually queried\n                     * from the hardware. */\n                    configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );\n                }\n            #endif\n\n            #ifdef configPRIO_BITS\n                {\n                    /* Check the FreeRTOS configuration that defines the number of\n                     * priority bits matches the number of priority bits actually queried\n                     * from the hardware. */\n                    configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );\n                }\n            #endif\n\n            /* Shift the priority group value back to its position within the AIRCR\n             * register. */\n            ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;\n            ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;\n\n            /* Restore the clobbered interrupt priority register to its original\n             * value. */\n            *pucFirstUserPriorityRegister = ulOriginalPriority;\n        }\n    #endif /* configASSERT_DEFINED */\n\n    /* Make PendSV and SysTick the same priority as the kernel, and the SVC\n     * handler higher priority so it can be used to exit a critical section (where\n     * lower priorities are masked). */\n    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;\n    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;\n\n    /* Configure the regions in the MPU that are common to all tasks. */\n    prvSetupMPU();\n\n    /* Start the timer that generates the tick ISR.  Interrupts are disabled\n     * here already. */\n    vPortSetupTimerInterrupt();\n\n    /* Initialise the critical nesting count ready for the first task. */\n    uxCriticalNesting = 0;\n\n    /* Ensure the VFP is enabled - it should be anyway. */\n    vPortEnableVFP();\n\n    /* Lazy save always. */\n    *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;\n\n    /* Start the first task.  This also clears the bit that indicates the FPU is\n     * in use in case the FPU was used before the scheduler was started - which\n     * would otherwise result in the unnecessary leaving of space in the SVC stack\n     * for lazy saving of FPU registers. */\n    __asm volatile (\n        \" ldr r0, =0xE000ED08 \t\\n\"/* Use the NVIC offset register to locate the stack. */\n        \" ldr r0, [r0] \t\t\t\\n\"\n        \" ldr r0, [r0] \t\t\t\\n\"\n        \" msr msp, r0\t\t\t\\n\"/* Set the msp back to the start of the stack. */\n        \" mov r0, #0\t\t\t\\n\"/* Clear the bit that indicates the FPU is in use, see comment above. */\n        \" msr control, r0\t\t\\n\"\n        \" cpsie i\t\t\t\t\\n\"/* Globally enable interrupts. */\n        \" cpsie f\t\t\t\t\\n\"\n        \" dsb\t\t\t\t\t\\n\"\n        \" isb\t\t\t\t\t\\n\"\n        \" svc %0\t\t\t\t\\n\"/* System call to start first task. */\n        \" nop\t\t\t\t\t\\n\"\n        \" .ltorg\t\t\t\t\\n\"\n        ::\"i\" ( portSVC_START_SCHEDULER ) : \"memory\" );\n\n    /* Should not get here! */\n    return 0;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEndScheduler( void )\n{\n    /* Not implemented in ports where there is nothing to return to.\n     * Artificially force an assert. */\n    configASSERT( uxCriticalNesting == 1000UL );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEnterCritical( void )\n{\n#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )\n    if( portIS_PRIVILEGED() == pdFALSE )\n    {\n        portRAISE_PRIVILEGE();\n        portMEMORY_BARRIER();\n\n        portDISABLE_INTERRUPTS();\n        uxCriticalNesting++;\n        portMEMORY_BARRIER();\n\n        portRESET_PRIVILEGE();\n        portMEMORY_BARRIER();\n    }\n    else\n    {\n        portDISABLE_INTERRUPTS();\n        uxCriticalNesting++;\n    }\n#else\n    portDISABLE_INTERRUPTS();\n    uxCriticalNesting++;\n#endif\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortExitCritical( void )\n{\n#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )\n    if( portIS_PRIVILEGED() == pdFALSE )\n    {\n        portRAISE_PRIVILEGE();\n        portMEMORY_BARRIER();\n\n        configASSERT( uxCriticalNesting );\n        uxCriticalNesting--;\n\n        if( uxCriticalNesting == 0 )\n        {\n            portENABLE_INTERRUPTS();\n        }\n        portMEMORY_BARRIER();\n\n        portRESET_PRIVILEGE();\n        portMEMORY_BARRIER();\n    }\n    else\n    {\n        configASSERT( uxCriticalNesting );\n        uxCriticalNesting--;\n\n        if( uxCriticalNesting == 0 )\n        {\n            portENABLE_INTERRUPTS();\n        }\n    }\n#else\n    configASSERT( uxCriticalNesting );\n    uxCriticalNesting--;\n\n    if( uxCriticalNesting == 0 )\n    {\n        portENABLE_INTERRUPTS();\n    }\n#endif\n}\n/*-----------------------------------------------------------*/\n\nvoid xPortPendSVHandler( void )\n{\n    /* This is a naked function. */\n\n    __asm volatile\n    (\n        \"\tmrs r0, psp\t\t\t\t\t\t\t\\n\"\n        \"\tisb\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr\tr3, pxCurrentTCBConst\t\t\t\\n\"/* Get the location of the current TCB. */\n        \"\tldr\tr2, [r3]\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\ttst r14, #0x10\t\t\t\t\t\t\\n\"/* Is the task using the FPU context?  If so, push high vfp registers. */\n        \"\tit eq\t\t\t\t\t\t\t\t\\n\"\n        \"\tvstmdbeq r0!, {s16-s31}\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrs r1, control\t\t\t\t\t\t\\n\"\n        \"\tstmdb r0!, {r1, r4-r11, r14}\t\t\\n\"/* Save the remaining registers. */\n        \"\tstr r0, [r2]\t\t\t\t\t\t\\n\"/* Save the new top of stack into the first member of the TCB. */\n        \"\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tstmdb sp!, {r0, r3}\t\t\t\t\t\\n\"\n        \"\tmov r0, %0\t\t\t\t\t\t\t\\n\"\n       #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )\n            \"\tcpsid i\t\t\t\t\t\t\t\\n\"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */\n        #endif\n        \"\tmsr basepri, r0\t\t\t\t\t\t\\n\"\n        \"\tdsb\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tisb\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )\n            \"\tcpsie i\t\t\t\t\t\t\t\\n\"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */\n        #endif\n        \"\tbl vTaskSwitchContext\t\t\t\t\\n\"\n        \"\tmov r0, #0\t\t\t\t\t\t\t\\n\"\n        \"\tmsr basepri, r0\t\t\t\t\t\t\\n\"\n        \"\tldmia sp!, {r0, r3}\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\\n\"/* Restore the context. */\n        \"\tldr r1, [r3]\t\t\t\t\t\t\\n\"\n        \"\tldr r0, [r1]\t\t\t\t\t\t\\n\"/* The first item in the TCB is the task top of stack. */\n        \"\tadd r1, r1, #4\t\t\t\t\t\t\\n\"/* Move onto the second item in the TCB... */\n        \"\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tdmb\t\t\t\t\t\t\t\t\t\\n\"/* Complete outstanding transfers before disabling MPU. */\n        \"\tldr r2, =0xe000ed94\t\t\t\t\t\\n\"/* MPU_CTRL register. */\n        \"\tldr r3, [r2]\t\t\t\t\t\t\\n\"/* Read the value of MPU_CTRL. */\n        \"\tbic r3, #1\t\t\t\t\t\t\t\\n\"/* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */\n        \"\tstr r3, [r2]\t\t\t\t\t\t\\n\"/* Disable MPU. */\n        \"\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r2, =0xe000ed9c\t\t\t\t\t\\n\"/* Region Base Address register. */\n        \"\tldmia r1!, {r4-r11}\t\t\t\t\t\\n\"/* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */\n        \"\tstmia r2, {r4-r11}\t\t\t\t\t\\n\"/* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */\n        \"\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configTOTAL_MPU_REGIONS == 16 )\n            \"\tldmia r1!, {r4-r11}\t\t\t\t\t\\n\"/* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */\n            \"\tstmia r2, {r4-r11}\t\t\t\t\t\\n\"/* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */\n            \"\tldmia r1!, {r4-r11}\t\t\t\t\t\\n\"/* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */\n            \"\tstmia r2, {r4-r11}\t\t\t\t\t\\n\"/* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */\n        #endif /* configTOTAL_MPU_REGIONS == 16. */\n        \"\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r2, =0xe000ed94\t\t\t\t\t\\n\"/* MPU_CTRL register. */\n        \"\tldr r3, [r2]\t\t\t\t\t\t\\n\"/* Read the value of MPU_CTRL. */\n        \"\torr r3, #1\t\t\t\t\t\t\t\\n\"/* r3 = r3 | 1 i.e. Set the bit 0 in r3. */\n        \"\tstr r3, [r2]\t\t\t\t\t\t\\n\"/* Enable MPU. */\n        \"\tdsb\t\t\t\t\t\t\t\t\t\\n\"/* Force memory writes before continuing. */\n        \"\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldmia r0!, {r3-r11, r14}\t\t\t\\n\"/* Pop the registers that are not automatically saved on exception entry. */\n        \"\tmsr control, r3\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\ttst r14, #0x10\t\t\t\t\t\t\\n\"/* Is the task using the FPU context?  If so, pop the high vfp registers too. */\n        \"\tit eq\t\t\t\t\t\t\t\t\\n\"\n        \"\tvldmiaeq r0!, {s16-s31}\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmsr psp, r0\t\t\t\t\t\t\t\\n\"\n        \"\tbx r14\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.ltorg\t\t\t\t\t\t\t\t\\n\"/* Assemble the current literal pool to avoid offset-out-of-bound errors with lto. */\n        \"\t.align 4\t\t\t\t\t\t\t\\n\"\n        \"pxCurrentTCBConst: .word pxCurrentTCB\t\\n\"\n        ::\"i\" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid xPortSysTickHandler( void )\n{\n    uint32_t ulDummy;\n\n    ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();\n    {\n        /* Increment the RTOS tick. */\n        if( xTaskIncrementTick() != pdFALSE )\n        {\n            /* Pend a context switch. */\n            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\n        }\n    }\n    portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );\n}\n/*-----------------------------------------------------------*/\n\n/*\n * Setup the systick timer to generate the tick interrupts at the required\n * frequency.\n */\n__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )\n{\n    /* Stop and clear the SysTick. */\n    portNVIC_SYSTICK_CTRL_REG = 0UL;\n    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n    /* Configure SysTick to interrupt at the requested rate. */\n    portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\n    portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE );\n}\n/*-----------------------------------------------------------*/\n\n/* This is a naked function. */\nstatic void vPortEnableVFP( void )\n{\n    __asm volatile\n    (\n        \"\tldr.w r0, =0xE000ED88\t\t\\n\"/* The FPU enable bits are in the CPACR. */\n        \"\tldr r1, [r0]\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\\n\"\n        \"\torr r1, r1, #( 0xf << 20 )\t\\n\"/* Enable CP10 and CP11 coprocessors, then save back. */\n        \"\tstr r1, [r0]\t\t\t\t\\n\"\n        \"\tbx r14\t\t\t\t\t\t\\n\"\n        \"\t.ltorg\t\t\t\t\t\t\\n\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvSetupMPU( void )\n{\n    #if defined( __ARMCC_VERSION )\n\n        /* Declaration when these variable are defined in code instead of being\n         * exported from linker scripts. */\n        extern uint32_t * __privileged_functions_start__;\n        extern uint32_t * __privileged_functions_end__;\n        extern uint32_t * __FLASH_segment_start__;\n        extern uint32_t * __FLASH_segment_end__;\n        extern uint32_t * __privileged_data_start__;\n        extern uint32_t * __privileged_data_end__;\n    #else\n        /* Declaration when these variable are exported from linker scripts. */\n        extern uint32_t __privileged_functions_start__[];\n        extern uint32_t __privileged_functions_end__[];\n        extern uint32_t __FLASH_segment_start__[];\n        extern uint32_t __FLASH_segment_end__[];\n        extern uint32_t __privileged_data_start__[];\n        extern uint32_t __privileged_data_end__[];\n    #endif /* if defined( __ARMCC_VERSION ) */\n\n    /* The only permitted number of regions are 8 or 16. */\n    configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );\n\n    /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */\n    configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );\n\n    /* Check the expected MPU is present. */\n    if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )\n    {\n        /* First setup the unprivileged flash for unprivileged read only access. */\n        portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */\n                                          ( portMPU_REGION_VALID ) |\n                                          ( portUNPRIVILEGED_FLASH_REGION );\n\n        portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_ONLY ) |\n                                       ( ( configTEX_S_C_B_FLASH & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |\n                                       ( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |\n                                       ( portMPU_REGION_ENABLE );\n\n        /* Setup the privileged flash for privileged only access.  This is where\n         * the kernel code is placed. */\n        portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_functions_start__ ) | /* Base address. */\n                                          ( portMPU_REGION_VALID ) |\n                                          ( portPRIVILEGED_FLASH_REGION );\n\n        portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_ONLY ) |\n                                       ( ( configTEX_S_C_B_FLASH & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |\n                                       ( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __privileged_functions_start__ ) ) |\n                                       ( portMPU_REGION_ENABLE );\n\n        /* Setup the privileged data RAM region.  This is where the kernel data\n         * is placed. */\n        portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */\n                                          ( portMPU_REGION_VALID ) |\n                                          ( portPRIVILEGED_RAM_REGION );\n\n        portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\n                                       ( portMPU_REGION_EXECUTE_NEVER ) |\n                                       ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |\n                                       prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |\n                                       ( portMPU_REGION_ENABLE );\n\n        /* By default allow everything to access the general peripherals.  The\n         * system peripherals and registers are protected. */\n        portMPU_REGION_BASE_ADDRESS_REG = ( portPERIPHERALS_START_ADDRESS ) |\n                                          ( portMPU_REGION_VALID ) |\n                                          ( portGENERAL_PERIPHERALS_REGION );\n\n        portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |\n                                       ( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |\n                                       ( portMPU_REGION_ENABLE );\n\n        /* Enable the memory fault exception. */\n        portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE;\n\n        /* Enable the MPU with the background region configured. */\n        portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );\n    }\n}\n/*-----------------------------------------------------------*/\n\nstatic uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )\n{\n    uint32_t ulRegionSize, ulReturnValue = 4;\n\n    /* 32 is the smallest region size, 31 is the largest valid value for\n     * ulReturnValue. */\n    for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )\n    {\n        if( ulActualSizeInBytes <= ulRegionSize )\n        {\n            break;\n        }\n        else\n        {\n            ulReturnValue++;\n        }\n    }\n\n    /* Shift the code by one before returning so it can be written directly\n     * into the the correct bit position of the attribute register. */\n    return( ulReturnValue << 1UL );\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */\n{\n    __asm volatile\n    (\n        \"\tmrs r0, control\t\t\t\t\t\t\t\\n\"/* r0 = CONTROL. */\n        \"\ttst r0, #1\t\t\t\t\t\t\t\t\\n\"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\n        \"\tite ne\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmovne r0, #0\t\t\t\t\t\t\t\\n\"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\n        \"\tmoveq r0, #1\t\t\t\t\t\t\t\\n\"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\\n\"/* Return. */\n        \"\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.align 4\t\t\t\t\t\t\t\t\\n\"\n        ::: \"r0\", \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vResetPrivilege( void ) /* __attribute__ (( naked )) */\n{\n    __asm volatile\n    (\n        \"\tmrs r0, control\t\t\t\t\t\t\t\\n\"/* r0 = CONTROL. */\n        \"\torr r0, #1\t\t\t\t\t\t\t\t\\n\"/* r0 = r0 | 1. */\n        \"\tmsr control, r0\t\t\t\t\t\t\t\\n\"/* CONTROL = r0. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\\n\"/* Return to the caller. */\n        ::: \"r0\", \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,\n                                const struct xMEMORY_REGION * const xRegions,\n                                StackType_t * pxBottomOfStack,\n                                uint32_t ulStackDepth )\n{\n    #if defined( __ARMCC_VERSION )\n\n        /* Declaration when these variable are defined in code instead of being\n         * exported from linker scripts. */\n        extern uint32_t * __SRAM_segment_start__;\n        extern uint32_t * __SRAM_segment_end__;\n        extern uint32_t * __privileged_data_start__;\n        extern uint32_t * __privileged_data_end__;\n    #else\n        /* Declaration when these variable are exported from linker scripts. */\n        extern uint32_t __SRAM_segment_start__[];\n        extern uint32_t __SRAM_segment_end__[];\n        extern uint32_t __privileged_data_start__[];\n        extern uint32_t __privileged_data_end__[];\n    #endif /* if defined( __ARMCC_VERSION ) */\n\n    int32_t lIndex;\n    uint32_t ul;\n\n    if( xRegions == NULL )\n    {\n        /* No MPU regions are specified so allow access to all RAM. */\n        xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =\n            ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */\n            ( portMPU_REGION_VALID ) |\n            ( portSTACK_REGION ); /* Region number. */\n\n        xMPUSettings->xRegion[ 0 ].ulRegionAttribute =\n            ( portMPU_REGION_READ_WRITE ) |\n            ( portMPU_REGION_EXECUTE_NEVER ) |\n            ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |\n            ( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |\n            ( portMPU_REGION_ENABLE );\n\n        /* Invalidate user configurable regions. */\n        for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )\n        {\n            xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( ul - 1UL ) | portMPU_REGION_VALID );\n            xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;\n        }\n    }\n    else\n    {\n        /* This function is called automatically when the task is created - in\n         * which case the stack region parameters will be valid.  At all other\n         * times the stack parameters will not be valid and it is assumed that the\n         * stack region has already been configured. */\n        if( ulStackDepth > 0 )\n        {\n            /* Define the region that allows access to the stack. */\n            xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =\n                ( ( uint32_t ) pxBottomOfStack ) |\n                ( portMPU_REGION_VALID ) |\n                ( portSTACK_REGION ); /* Region number. */\n\n            xMPUSettings->xRegion[ 0 ].ulRegionAttribute =\n                ( portMPU_REGION_READ_WRITE ) |\n                ( portMPU_REGION_EXECUTE_NEVER ) |\n                ( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |\n                ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |\n                ( portMPU_REGION_ENABLE );\n        }\n\n        lIndex = 0;\n\n        for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )\n        {\n            if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )\n            {\n                /* Translate the generic region definition contained in\n                 * xRegions into the CM4 specific MPU settings that are then\n                 * stored in xMPUSettings. */\n                xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =\n                    ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |\n                    ( portMPU_REGION_VALID ) |\n                    ( ul - 1UL ); /* Region number. */\n\n                xMPUSettings->xRegion[ ul ].ulRegionAttribute =\n                    ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |\n                    ( xRegions[ lIndex ].ulParameters ) |\n                    ( portMPU_REGION_ENABLE );\n            }\n            else\n            {\n                /* Invalidate the region. */\n                xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( ul - 1UL ) | portMPU_REGION_VALID );\n                xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;\n            }\n\n            lIndex++;\n        }\n    }\n}\n/*-----------------------------------------------------------*/\n\n#if ( configASSERT_DEFINED == 1 )\n\n    void vPortValidateInterruptPriority( void )\n    {\n        uint32_t ulCurrentInterrupt;\n        uint8_t ucCurrentPriority;\n\n        /* Obtain the number of the currently executing interrupt. */\n        __asm volatile ( \"mrs %0, ipsr\" : \"=r\" ( ulCurrentInterrupt )::\"memory\" );\n\n        /* Is the interrupt number a user defined interrupt? */\n        if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )\n        {\n            /* Look up the interrupt's priority. */\n            ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];\n\n            /* The following assertion will fail if a service routine (ISR) for\n             * an interrupt that has been assigned a priority above\n             * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\n             * function.  ISR safe FreeRTOS API functions must *only* be called\n             * from interrupts that have been assigned a priority at or below\n             * configMAX_SYSCALL_INTERRUPT_PRIORITY.\n             *\n             * Numerically low interrupt priority numbers represent logically high\n             * interrupt priorities, therefore the priority of the interrupt must\n             * be set to a value equal to or numerically *higher* than\n             * configMAX_SYSCALL_INTERRUPT_PRIORITY.\n             *\n             * Interrupts that use the FreeRTOS API must not be left at their\n             * default priority of zero as that is the highest possible priority,\n             * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,\n             * and therefore also guaranteed to be invalid.\n             *\n             * FreeRTOS maintains separate thread and ISR API functions to ensure\n             * interrupt entry is as fast and simple as possible.\n             *\n             * The following links provide detailed information:\n             * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html\n             * https://www.FreeRTOS.org/FAQHelp.html */\n            configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );\n        }\n\n        /* Priority grouping:  The interrupt controller (NVIC) allows the bits\n         * that define each interrupt's priority to be split between bits that\n         * define the interrupt's pre-emption priority bits and bits that define\n         * the interrupt's sub-priority.  For simplicity all bits must be defined\n         * to be pre-emption priority bits.  The following assertion will fail if\n         * this is not the case (if some bits represent a sub-priority).\n         *\n         * If the application only uses CMSIS libraries for interrupt\n         * configuration then the correct setting can be achieved on all Cortex-M\n         * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the\n         * scheduler.  Note however that some vendor specific peripheral libraries\n         * assume a non-zero priority group setting, in which cases using a value\n         * of zero will result in unpredicable behaviour. */\n        configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );\n    }\n\n#endif /* configASSERT_DEFINED */\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM4_MPU/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n\n#ifndef PORTMACRO_H\n#define PORTMACRO_H\n\n\n/* *INDENT-OFF* */\n#ifdef __cplusplus\n    extern \"C\" {\n#endif\n/* *INDENT-ON* */\n\n/*-----------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the\n * given hardware and compiler.\n *\n * These settings should not be altered.\n *-----------------------------------------------------------\n */\n\n/* Type definitions. */\n#define portCHAR          char\n#define portFLOAT         float\n#define portDOUBLE        double\n#define portLONG          long\n#define portSHORT         short\n#define portSTACK_TYPE    uint32_t\n#define portBASE_TYPE     long\n\ntypedef portSTACK_TYPE   StackType_t;\ntypedef long             BaseType_t;\ntypedef unsigned long    UBaseType_t;\n\n#if ( configUSE_16_BIT_TICKS == 1 )\n    typedef uint16_t     TickType_t;\n    #define portMAX_DELAY              ( TickType_t ) 0xffff\n#else\n    typedef uint32_t     TickType_t;\n    #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL\n\n/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\n * not need to be guarded with a critical section. */\n    #define portTICK_TYPE_IS_ATOMIC    1\n#endif\n\n/*-----------------------------------------------------------*/\n\n/* MPU specific constants. */\n#define portUSING_MPU_WRAPPERS                                   1\n#define portPRIVILEGE_BIT                                        ( 0x80000000UL )\n\n#define portMPU_REGION_READ_WRITE                                ( 0x03UL << 24UL )\n#define portMPU_REGION_PRIVILEGED_READ_ONLY                      ( 0x05UL << 24UL )\n#define portMPU_REGION_READ_ONLY                                 ( 0x06UL << 24UL )\n#define portMPU_REGION_PRIVILEGED_READ_WRITE                     ( 0x01UL << 24UL )\n#define portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY    ( 0x02UL << 24UL )\n#define portMPU_REGION_CACHEABLE_BUFFERABLE                      ( 0x07UL << 16UL )\n#define portMPU_REGION_EXECUTE_NEVER                             ( 0x01UL << 28UL )\n\n/* Location of the TEX,S,C,B bits in the MPU Region Attribute and Size\n * Register (RASR). */\n#define portMPU_RASR_TEX_S_C_B_LOCATION                          ( 16UL )\n#define portMPU_RASR_TEX_S_C_B_MASK                              ( 0x3FUL )\n\n/* MPU settings that can be overriden in FreeRTOSConfig.h. */\n#ifndef configTOTAL_MPU_REGIONS\n    /* Define to 8 for backward compatibility. */\n    #define configTOTAL_MPU_REGIONS    ( 8UL )\n#endif\n\n/*\n * The TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits define the\n * memory type, and where necessary the cacheable and shareable properties\n * of the memory region.\n *\n * The TEX, C, and B bits together indicate the memory type of the region,\n * and:\n * - For Normal memory, the cacheable properties of the region.\n * - For Device memory, whether the region is shareable.\n *\n * For Normal memory regions, the S bit indicates whether the region is\n * shareable. For Strongly-ordered and Device memory, the S bit is ignored.\n *\n * See the following two tables for setting TEX, S, C and B bits for\n * unprivileged flash, privileged flash and privileged RAM regions.\n *\n +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+\n | TEX | C | B | Memory type            |  Description or Normal region cacheability             |  Shareable?             |\n +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+\n | 000 | 0 | 0 | Strongly-ordered       |  Strongly ordered                                      |  Shareable              |\n +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+\n | 000 | 0 | 1 | Device                 |  Shared device                                         |  Shareable              |\n +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+\n | 000 | 1 | 0 | Normal                 |  Outer and inner   write-through; no write allocate    |  S bit                  |\n +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+\n | 000 | 1 | 1 | Normal                 |  Outer and inner   write-back; no write allocate       |  S bit                  |\n +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+\n | 001 | 0 | 0 | Normal                 |  Outer and inner   Non-cacheable                       |  S bit                  |\n +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+\n | 001 | 0 | 1 | Reserved               |  Reserved                                              |  Reserved               |\n +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+\n | 001 | 1 | 0 | IMPLEMENTATION DEFINED |  IMPLEMENTATION DEFINED                                |  IMPLEMENTATION DEFINED |\n +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+\n | 001 | 1 | 1 | Normal                 |  Outer and inner   write-back; write and read allocate |  S bit                  |\n +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+\n | 010 | 0 | 0 | Device                 |  Non-shared device                                     |  Not shareable          |\n +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+\n | 010 | 0 | 1 | Reserved               |  Reserved                                              |  Reserved               |\n +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+\n | 010 | 1 | X | Reserved               |  Reserved                                              |  Reserved               |\n +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+\n | 011 | X | X | Reserved               |  Reserved                                              |  Reserved               |\n +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+\n | 1BB | A | A | Normal                 | Cached memory, with AA and BB indicating the inner and |  Reserved               |\n |     |   |   |                        | outer cacheability rules that must be exported on the  |                         |\n |     |   |   |                        | bus. See the table below for the cacheability policy   |                         |\n |     |   |   |                        | encoding. memory, BB=Outer policy, AA=Inner policy.    |                         |\n +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+\n |\n +-----------------------------------------+----------------------------------------+\n | AA or BB subfield of {TEX,C,B} encoding |  Cacheability policy                   |\n +-----------------------------------------+----------------------------------------+\n | 00                                      |  Non-cacheable                         |\n +-----------------------------------------+----------------------------------------+\n | 01                                      |  Write-back, write and   read allocate |\n +-----------------------------------------+----------------------------------------+\n | 10                                      |  Write-through, no write   allocate    |\n +-----------------------------------------+----------------------------------------+\n | 11                                      |  Write-back, no write   allocate       |\n +-----------------------------------------+----------------------------------------+\n */\n\n/* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for flash\n * region. */\n#ifndef configTEX_S_C_B_FLASH\n    /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */\n    #define configTEX_S_C_B_FLASH    ( 0x07UL )\n#endif\n\n/* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for RAM\n * region. */\n#ifndef configTEX_S_C_B_SRAM\n    /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */\n    #define configTEX_S_C_B_SRAM          ( 0x07UL )\n#endif\n\n#define portGENERAL_PERIPHERALS_REGION    ( configTOTAL_MPU_REGIONS - 5UL )\n#define portSTACK_REGION                  ( configTOTAL_MPU_REGIONS - 4UL )\n#define portUNPRIVILEGED_FLASH_REGION     ( configTOTAL_MPU_REGIONS - 3UL )\n#define portPRIVILEGED_FLASH_REGION       ( configTOTAL_MPU_REGIONS - 2UL )\n#define portPRIVILEGED_RAM_REGION         ( configTOTAL_MPU_REGIONS - 1UL )\n#define portFIRST_CONFIGURABLE_REGION     ( 0UL )\n#define portLAST_CONFIGURABLE_REGION      ( configTOTAL_MPU_REGIONS - 6UL )\n#define portNUM_CONFIGURABLE_REGIONS      ( configTOTAL_MPU_REGIONS - 5UL )\n#define portTOTAL_NUM_REGIONS_IN_TCB      ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus 1 to create space for the stack region. */\n\n#define portSWITCH_TO_USER_MODE()    __asm volatile ( \" mrs r0, control \\n orr r0, #1 \\n msr control, r0 \" ::: \"r0\", \"memory\" )\n\ntypedef struct MPU_REGION_REGISTERS\n{\n    uint32_t ulRegionBaseAddress;\n    uint32_t ulRegionAttribute;\n} xMPU_REGION_REGISTERS;\n\ntypedef struct MPU_SETTINGS\n{\n    xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS_IN_TCB ];\n} xMPU_SETTINGS;\n\n/* Architecture specifics. */\n#define portSTACK_GROWTH      ( -1 )\n#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\n#define portBYTE_ALIGNMENT    8\n#define portDONT_DISCARD      __attribute__( ( used ) )\n/*-----------------------------------------------------------*/\n\n/* SVC numbers for various services. */\n#define portSVC_START_SCHEDULER    0\n#define portSVC_YIELD              1\n#define portSVC_RAISE_PRIVILEGE    2\n\n/* Scheduler utilities. */\n\n#define portYIELD()    __asm volatile ( \"\tSVC\t%0\t\\n\"::\"i\" ( portSVC_YIELD ) : \"memory\" )\n#define portYIELD_WITHIN_API()                          \\\n    {                                                   \\\n        /* Set a PendSV to request a context switch. */ \\\n        portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \\\n                                                        \\\n        /* Barriers are normally not required but do ensure the code is completely \\\n         * within the specified behaviour for the architecture. */ \\\n        __asm volatile ( \"dsb\" ::: \"memory\" );                     \\\n        __asm volatile ( \"isb\" );                                  \\\n    }\n\n#define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )\n#define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )\n#define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )\n#define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )\n/*-----------------------------------------------------------*/\n\n/* Critical section management. */\nextern void vPortEnterCritical( void );\nextern void vPortExitCritical( void );\n#define portSET_INTERRUPT_MASK_FROM_ISR()         ulPortRaiseBASEPRI()\n#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vPortSetBASEPRI( x )\n#define portDISABLE_INTERRUPTS()                  vPortRaiseBASEPRI()\n#define portENABLE_INTERRUPTS()                   vPortSetBASEPRI( 0 )\n#define portENTER_CRITICAL()                      vPortEnterCritical()\n#define portEXIT_CRITICAL()                       vPortExitCritical()\n\n/*-----------------------------------------------------------*/\n\n/* Task function macros as described on the FreeRTOS.org WEB site.  These are\n * not necessary for to use this port.  They are defined so the common demo files\n * (which build with all the ports) will build. */\n#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )\n#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )\n/*-----------------------------------------------------------*/\n\n/* Architecture specific optimisations. */\n#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION\n    #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1\n#endif\n\n#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1\n\n/* Generic helper function. */\n    __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )\n    {\n        uint8_t ucReturn;\n\n        __asm volatile ( \"clz %0, %1\" : \"=r\" ( ucReturn ) : \"r\" ( ulBitmap ) : \"memory\" );\n\n        return ucReturn;\n    }\n\n/* Check the configuration. */\n    #if ( configMAX_PRIORITIES > 32 )\n        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.\n    #endif\n\n/* Store/clear the ready priorities in a bit map. */\n    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )\n    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )\n\n/*-----------------------------------------------------------*/\n\n    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )\n\n#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */\n\n/*-----------------------------------------------------------*/\n\n#ifdef configASSERT\n    void vPortValidateInterruptPriority( void );\n    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()\n#endif\n\n/* portNOP() is not required by this port. */\n#define portNOP()\n\n#define portINLINE              __inline\n\n#ifndef portFORCE_INLINE\n    #define portFORCE_INLINE    inline __attribute__( ( always_inline ) )\n#endif\n/*-----------------------------------------------------------*/\n\nextern BaseType_t xIsPrivileged( void );\nextern void vResetPrivilege( void );\n\n/**\n * @brief Checks whether or not the processor is privileged.\n *\n * @return 1 if the processor is already privileged, 0 otherwise.\n */\n#define portIS_PRIVILEGED()      xIsPrivileged()\n\n/**\n * @brief Raise an SVC request to raise privilege.\n */\n#define portRAISE_PRIVILEGE()    __asm volatile ( \"svc %0 \\n\" ::\"i\" ( portSVC_RAISE_PRIVILEGE ) : \"memory\" );\n\n/**\n * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\n * register.\n */\n#define portRESET_PRIVILEGE()    vResetPrivilege()\n/*-----------------------------------------------------------*/\n\nportFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )\n{\n    uint32_t ulCurrentInterrupt;\n    BaseType_t xReturn;\n\n    /* Obtain the number of the currently executing interrupt. */\n    __asm volatile ( \"mrs %0, ipsr\" : \"=r\" ( ulCurrentInterrupt )::\"memory\" );\n\n    if( ulCurrentInterrupt == 0 )\n    {\n        xReturn = pdFALSE;\n    }\n    else\n    {\n        xReturn = pdTRUE;\n    }\n\n    return xReturn;\n}\n\n/*-----------------------------------------------------------*/\n\nportFORCE_INLINE static void vPortRaiseBASEPRI( void )\n{\n    uint32_t ulNewBASEPRI;\n\n    __asm volatile\n    (\n        \"\tmov %0, %1\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )\n            \"\tcpsid i\t\t\t\t\t\t\t\t\t\t\t\t\\n\"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */\n        #endif\n        \"\tmsr basepri, %0\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )\n            \"\tcpsie i\t\t\t\t\t\t\t\t\t\t\t\t\\n\"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */\n        #endif\n        : \"=r\" ( ulNewBASEPRI ) : \"i\" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : \"memory\"\n    );\n}\n\n/*-----------------------------------------------------------*/\n\nportFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )\n{\n    uint32_t ulOriginalBASEPRI, ulNewBASEPRI;\n\n    __asm volatile\n    (\n        \"\tmrs %0, basepri\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmov %1, %2\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )\n            \"\tcpsid i\t\t\t\t\t\t\t\t\t\t\t\t\\n\"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */\n        #endif\n        \"\tmsr basepri, %1\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )\n            \"\tcpsie i\t\t\t\t\t\t\t\t\t\t\t\t\\n\"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */\n        #endif\n        : \"=r\" ( ulOriginalBASEPRI ), \"=r\" ( ulNewBASEPRI ) : \"i\" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : \"memory\"\n    );\n\n    /* This return will not be reached but is necessary to prevent compiler\n     * warnings. */\n    return ulOriginalBASEPRI;\n}\n/*-----------------------------------------------------------*/\n\nportFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )\n{\n    __asm volatile\n    (\n        \"\tmsr basepri, %0\t\"::\"r\" ( ulNewMaskValue ) : \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\n#define portMEMORY_BARRIER()    __asm volatile ( \"\" ::: \"memory\" )\n\n#ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY\n    #warning \"configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. https://www.FreeRTOS.org/FreeRTOS-V10.3.x.html\"\n    #define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY    0\n#endif\n/*-----------------------------------------------------------*/\n\n/* *INDENT-OFF* */\n    #ifdef __cplusplus\n        }\n    #endif\n/* *INDENT-ON* */\n\n#endif /* PORTMACRO_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM55/non_secure/port.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\n * all the API functions to use the MPU wrappers. That should only be done when\n * task.h is included from an application file. */\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n/* MPU wrappers includes. */\n#include \"mpu_wrappers.h\"\n\n/* Portasm includes. */\n#include \"portasm.h\"\n\n#if ( configENABLE_TRUSTZONE == 1 )\n    /* Secure components includes. */\n    #include \"secure_context.h\"\n    #include \"secure_init.h\"\n#endif /* configENABLE_TRUSTZONE */\n\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/**\n * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only\n * i.e. the processor boots as secure and never jumps to the non-secure side.\n * The Trust Zone support in the port must be disabled in order to run FreeRTOS\n * on the secure side. The following are the valid configuration seetings:\n *\n * 1. Run FreeRTOS on the Secure Side:\n *    configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0\n *\n * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:\n *    configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1\n *\n * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:\n *    configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0\n */\n#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )\n    #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.\n#endif\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the NVIC.\n */\n#define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )\n#define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )\n#define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )\n#define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )\n#define portNVIC_SYSTICK_ENABLE_BIT           ( 1UL << 0UL )\n#define portNVIC_SYSTICK_INT_BIT              ( 1UL << 1UL )\n#define portNVIC_SYSTICK_CLK_BIT              ( 1UL << 2UL )\n#define portNVIC_SYSTICK_COUNT_FLAG_BIT       ( 1UL << 16UL )\n#define portNVIC_PEND_SYSTICK_CLEAR_BIT       ( 1UL << 25UL )\n#define portNVIC_PEND_SYSTICK_SET_BIT         ( 1UL << 26UL )\n#define portMIN_INTERRUPT_PRIORITY            ( 255UL )\n#define portNVIC_PENDSV_PRI                   ( portMIN_INTERRUPT_PRIORITY << 16UL )\n#define portNVIC_SYSTICK_PRI                  ( portMIN_INTERRUPT_PRIORITY << 24UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the SCB.\n */\n#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( volatile uint32_t * ) 0xe000ed24 )\n#define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the FPU.\n */\n#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 )              /* Coprocessor Access Control Register. */\n#define portCPACR_CP10_VALUE    ( 3UL )\n#define portCPACR_CP11_VALUE    portCPACR_CP10_VALUE\n#define portCPACR_CP10_POS      ( 20UL )\n#define portCPACR_CP11_POS      ( 22UL )\n\n#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 )              /* Floating Point Context Control Register. */\n#define portFPCCR_ASPEN_POS     ( 31UL )\n#define portFPCCR_ASPEN_MASK    ( 1UL << portFPCCR_ASPEN_POS )\n#define portFPCCR_LSPEN_POS     ( 30UL )\n#define portFPCCR_LSPEN_MASK    ( 1UL << portFPCCR_LSPEN_POS )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the MPU.\n */\n#define portMPU_TYPE_REG                      ( *( ( volatile uint32_t * ) 0xe000ed90 ) )\n#define portMPU_CTRL_REG                      ( *( ( volatile uint32_t * ) 0xe000ed94 ) )\n#define portMPU_RNR_REG                       ( *( ( volatile uint32_t * ) 0xe000ed98 ) )\n\n#define portMPU_RBAR_REG                      ( *( ( volatile uint32_t * ) 0xe000ed9c ) )\n#define portMPU_RLAR_REG                      ( *( ( volatile uint32_t * ) 0xe000eda0 ) )\n\n#define portMPU_RBAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda4 ) )\n#define portMPU_RLAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda8 ) )\n\n#define portMPU_RBAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edac ) )\n#define portMPU_RLAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edb0 ) )\n\n#define portMPU_RBAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb4 ) )\n#define portMPU_RLAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb8 ) )\n\n#define portMPU_MAIR0_REG                     ( *( ( volatile uint32_t * ) 0xe000edc0 ) )\n#define portMPU_MAIR1_REG                     ( *( ( volatile uint32_t * ) 0xe000edc4 ) )\n\n#define portMPU_RBAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */\n#define portMPU_RLAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */\n\n#define portMPU_MAIR_ATTR0_POS                ( 0UL )\n#define portMPU_MAIR_ATTR0_MASK               ( 0x000000ff )\n\n#define portMPU_MAIR_ATTR1_POS                ( 8UL )\n#define portMPU_MAIR_ATTR1_MASK               ( 0x0000ff00 )\n\n#define portMPU_MAIR_ATTR2_POS                ( 16UL )\n#define portMPU_MAIR_ATTR2_MASK               ( 0x00ff0000 )\n\n#define portMPU_MAIR_ATTR3_POS                ( 24UL )\n#define portMPU_MAIR_ATTR3_MASK               ( 0xff000000 )\n\n#define portMPU_MAIR_ATTR4_POS                ( 0UL )\n#define portMPU_MAIR_ATTR4_MASK               ( 0x000000ff )\n\n#define portMPU_MAIR_ATTR5_POS                ( 8UL )\n#define portMPU_MAIR_ATTR5_MASK               ( 0x0000ff00 )\n\n#define portMPU_MAIR_ATTR6_POS                ( 16UL )\n#define portMPU_MAIR_ATTR6_MASK               ( 0x00ff0000 )\n\n#define portMPU_MAIR_ATTR7_POS                ( 24UL )\n#define portMPU_MAIR_ATTR7_MASK               ( 0xff000000 )\n\n#define portMPU_RLAR_ATTR_INDEX0              ( 0UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX1              ( 1UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX2              ( 2UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX3              ( 3UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX4              ( 4UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX5              ( 5UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX6              ( 6UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX7              ( 7UL << 1UL )\n\n#define portMPU_RLAR_REGION_ENABLE            ( 1UL )\n\n/* Enable privileged access to unmapped region. */\n#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )\n\n/* Enable MPU. */\n#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )\n\n/* Expected value of the portMPU_TYPE register. */\n#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief The maximum 24-bit number.\n *\n * It is needed because the systick is a 24-bit counter.\n */\n#define portMAX_24_BIT_NUMBER       ( 0xffffffUL )\n\n/**\n * @brief A fiddle factor to estimate the number of SysTick counts that would\n * have occurred while the SysTick counter is stopped during tickless idle\n * calculations.\n */\n#define portMISSED_COUNTS_FACTOR    ( 94UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to set up the initial stack.\n */\n#define portINITIAL_XPSR    ( 0x01000000 )\n\n#if ( configRUN_FREERTOS_SECURE_ONLY == 1 )\n\n/**\n * @brief Initial EXC_RETURN value.\n *\n *     FF         FF         FF         FD\n * 1111 1111  1111 1111  1111 1111  1111 1101\n *\n * Bit[6] - 1 --> The exception was taken from the Secure state.\n * Bit[5] - 1 --> Do not skip stacking of additional state context.\n * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\n * Bit[3] - 1 --> Return to the Thread mode.\n * Bit[2] - 1 --> Restore registers from the process stack.\n * Bit[1] - 0 --> Reserved, 0.\n * Bit[0] - 1 --> The exception was taken to the Secure state.\n */\n    #define portINITIAL_EXC_RETURN    ( 0xfffffffd )\n#else\n\n/**\n * @brief Initial EXC_RETURN value.\n *\n *     FF         FF         FF         BC\n * 1111 1111  1111 1111  1111 1111  1011 1100\n *\n * Bit[6] - 0 --> The exception was taken from the Non-Secure state.\n * Bit[5] - 1 --> Do not skip stacking of additional state context.\n * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\n * Bit[3] - 1 --> Return to the Thread mode.\n * Bit[2] - 1 --> Restore registers from the process stack.\n * Bit[1] - 0 --> Reserved, 0.\n * Bit[0] - 0 --> The exception was taken to the Non-Secure state.\n */\n    #define portINITIAL_EXC_RETURN    ( 0xffffffbc )\n#endif /* configRUN_FREERTOS_SECURE_ONLY */\n\n/**\n * @brief CONTROL register privileged bit mask.\n *\n * Bit[0] in CONTROL register tells the privilege:\n *  Bit[0] = 0 ==> The task is privileged.\n *  Bit[0] = 1 ==> The task is not privileged.\n */\n#define portCONTROL_PRIVILEGED_MASK         ( 1UL << 0UL )\n\n/**\n * @brief Initial CONTROL register values.\n */\n#define portINITIAL_CONTROL_UNPRIVILEGED    ( 0x3 )\n#define portINITIAL_CONTROL_PRIVILEGED      ( 0x2 )\n\n/**\n * @brief Let the user override the default SysTick clock rate.  If defined by the\n * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the\n * configuration register.\n */\n#ifndef configSYSTICK_CLOCK_HZ\n    #define configSYSTICK_CLOCK_HZ             ( configCPU_CLOCK_HZ )\n    /* Ensure the SysTick is clocked at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( portNVIC_SYSTICK_CLK_BIT )\n#else\n    /* Select the option to clock SysTick not at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( 0 )\n#endif\n\n/**\n * @brief Let the user override the pre-loading of the initial LR with the\n * address of prvTaskExitError() in case it messes up unwinding of the stack\n * in the debugger.\n */\n#ifdef configTASK_RETURN_ADDRESS\n    #define portTASK_RETURN_ADDRESS    configTASK_RETURN_ADDRESS\n#else\n    #define portTASK_RETURN_ADDRESS    prvTaskExitError\n#endif\n\n/**\n * @brief If portPRELOAD_REGISTERS then registers will be given an initial value\n * when a task is created. This helps in debugging at the cost of code size.\n */\n#define portPRELOAD_REGISTERS    1\n\n/**\n * @brief A task is created without a secure context, and must call\n * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes\n * any secure calls.\n */\n#define portNO_SECURE_CONTEXT    0\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Used to catch tasks that attempt to return from their implementing\n * function.\n */\nstatic void prvTaskExitError( void );\n\n#if ( configENABLE_MPU == 1 )\n\n/**\n * @brief Setup the Memory Protection Unit (MPU).\n */\n    static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\n#endif /* configENABLE_MPU */\n\n#if ( configENABLE_FPU == 1 )\n\n/**\n * @brief Setup the Floating Point Unit (FPU).\n */\n    static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;\n#endif /* configENABLE_FPU */\n\n/**\n * @brief Setup the timer to generate the tick interrupts.\n *\n * The implementation in this file is weak to allow application writers to\n * change the timer used to generate the tick interrupt.\n */\nvoid vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Checks whether the current execution context is interrupt.\n *\n * @return pdTRUE if the current execution context is interrupt, pdFALSE\n * otherwise.\n */\nBaseType_t xPortIsInsideInterrupt( void );\n\n/**\n * @brief Yield the processor.\n */\nvoid vPortYield( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Enter critical section.\n */\nvoid vPortEnterCritical( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Exit from critical section.\n */\nvoid vPortExitCritical( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief SysTick handler.\n */\nvoid SysTick_Handler( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief C part of SVC handler.\n */\nportDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION;\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Each task maintains its own interrupt status in the critical nesting\n * variable.\n */\nPRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;\n\n#if ( configENABLE_TRUSTZONE == 1 )\n\n/**\n * @brief Saved as part of the task context to indicate which context the\n * task is using on the secure side.\n */\n    PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;\n#endif /* configENABLE_TRUSTZONE */\n\n#if ( configUSE_TICKLESS_IDLE == 1 )\n\n/**\n * @brief The number of SysTick increments that make up one tick period.\n */\n    PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0;\n\n/**\n * @brief The maximum number of tick periods that can be suppressed is\n * limited by the 24 bit resolution of the SysTick timer.\n */\n    PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0;\n\n/**\n * @brief Compensate for the CPU cycles that pass while the SysTick is\n * stopped (low power functionality only).\n */\n    PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TICKLESS_IDLE == 1 )\n    __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )\n    {\n        uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;\n        TickType_t xModifiableIdleTime;\n\n        /* Make sure the SysTick reload value does not overflow the counter. */\n        if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\n        {\n            xExpectedIdleTime = xMaximumPossibleSuppressedTicks;\n        }\n\n        /* Enter a critical section but don't use the taskENTER_CRITICAL()\n         * method as that will mask interrupts that should exit sleep mode. */\n        __asm volatile ( \"cpsid i\" ::: \"memory\" );\n        __asm volatile ( \"dsb\" );\n        __asm volatile ( \"isb\" );\n\n        /* If a context switch is pending or a task is waiting for the scheduler\n         * to be unsuspended then abandon the low power entry. */\n        if( eTaskConfirmSleepModeStatus() == eAbortSleep )\n        {\n            /* Re-enable interrupts - see comments above the cpsid instruction\n             * above. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n        }\n        else\n        {\n            /* Stop the SysTick momentarily.  The time the SysTick is stopped for\n             * is accounted for as best it can be, but using the tickless mode will\n             * inevitably result in some tiny drift of the time maintained by the\n             * kernel with respect to calendar time. */\n            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );\n\n            /* Use the SysTick current-value register to determine the number of\n             * SysTick decrements remaining until the next tick interrupt.  If the\n             * current-value register is zero, then there are actually\n             * ulTimerCountsForOneTick decrements remaining, not zero, because the\n             * SysTick requests the interrupt when decrementing from 1 to 0. */\n            ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n\n            if( ulSysTickDecrementsLeft == 0 )\n            {\n                ulSysTickDecrementsLeft = ulTimerCountsForOneTick;\n            }\n\n            /* Calculate the reload value required to wait xExpectedIdleTime\n             * tick periods.  -1 is used because this code normally executes part\n             * way through the first tick period.  But if the SysTick IRQ is now\n             * pending, then clear the IRQ, suppressing the first tick, and correct\n             * the reload value to reflect that the second tick period is already\n             * underway.  The expected idle time is always at least two ticks. */\n            ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );\n\n            if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )\n            {\n                portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;\n                ulReloadValue -= ulTimerCountsForOneTick;\n            }\n\n            if( ulReloadValue > ulStoppedTimerCompensation )\n            {\n                ulReloadValue -= ulStoppedTimerCompensation;\n            }\n\n            /* Set the new reload value. */\n            portNVIC_SYSTICK_LOAD_REG = ulReloadValue;\n\n            /* Clear the SysTick count flag and set the count value back to\n             * zero. */\n            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n            /* Restart SysTick. */\n            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\n\n            /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can\n             * set its parameter to 0 to indicate that its implementation contains\n             * its own wait for interrupt or wait for event instruction, and so wfi\n             * should not be executed again.  However, the original expected idle\n             * time variable must remain unmodified, so a copy is taken. */\n            xModifiableIdleTime = xExpectedIdleTime;\n            configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\n\n            if( xModifiableIdleTime > 0 )\n            {\n                __asm volatile ( \"dsb\" ::: \"memory\" );\n                __asm volatile ( \"wfi\" );\n                __asm volatile ( \"isb\" );\n            }\n\n            configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\n\n            /* Re-enable interrupts to allow the interrupt that brought the MCU\n             * out of sleep mode to execute immediately.  See comments above\n             * the cpsid instruction above. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n            __asm volatile ( \"dsb\" );\n            __asm volatile ( \"isb\" );\n\n            /* Disable interrupts again because the clock is about to be stopped\n             * and interrupts that execute while the clock is stopped will increase\n             * any slippage between the time maintained by the RTOS and calendar\n             * time. */\n            __asm volatile ( \"cpsid i\" ::: \"memory\" );\n            __asm volatile ( \"dsb\" );\n            __asm volatile ( \"isb\" );\n\n            /* Disable the SysTick clock without reading the\n             * portNVIC_SYSTICK_CTRL_REG register to ensure the\n             * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,\n             * the time the SysTick is stopped for is accounted for as best it can\n             * be, but using the tickless mode will inevitably result in some tiny\n             * drift of the time maintained by the kernel with respect to calendar\n             * time*/\n            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );\n\n            /* Determine whether the SysTick has already counted to zero. */\n            if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n            {\n                uint32_t ulCalculatedLoadValue;\n\n                /* The tick interrupt ended the sleep (or is now pending), and\n                 * a new tick period has started.  Reset portNVIC_SYSTICK_LOAD_REG\n                 * with whatever remains of the new tick period. */\n                ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\n\n                /* Don't allow a tiny value, or values that have somehow\n                 * underflowed because the post sleep hook did something\n                 * that took too long or because the SysTick current-value register\n                 * is zero. */\n                if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )\n                {\n                    ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );\n                }\n\n                portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;\n\n                /* As the pending tick will be processed as soon as this\n                 * function exits, the tick value maintained by the tick is stepped\n                 * forward by one less than the time spent waiting. */\n                ulCompleteTickPeriods = xExpectedIdleTime - 1UL;\n            }\n            else\n            {\n                /* Something other than the tick interrupt ended the sleep. */\n\n                /* Use the SysTick current-value register to determine the\n                 * number of SysTick decrements remaining until the expected idle\n                 * time would have ended. */\n                ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n                #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )\n                {\n                    /* If the SysTick is not using the core clock, the current-\n                     * value register might still be zero here.  In that case, the\n                     * SysTick didn't load from the reload register, and there are\n                     * ulReloadValue decrements remaining in the expected idle\n                     * time, not zero. */\n                    if( ulSysTickDecrementsLeft == 0 )\n                    {\n                        ulSysTickDecrementsLeft = ulReloadValue;\n                    }\n                }\n                #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */\n\n                /* Work out how long the sleep lasted rounded to complete tick\n                 * periods (not the ulReload value which accounted for part\n                 * ticks). */\n                ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;\n\n                /* How many complete tick periods passed while the processor\n                 * was waiting? */\n                ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;\n\n                /* The reload value is set to whatever fraction of a single tick\n                 * period remains. */\n                portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;\n            }\n\n            /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,\n             * then set portNVIC_SYSTICK_LOAD_REG back to its standard value.  If\n             * the SysTick is not using the core clock, temporarily configure it to\n             * use the core clock.  This configuration forces the SysTick to load\n             * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next\n             * cycle of the other clock.  Then portNVIC_SYSTICK_LOAD_REG is ready\n             * to receive the standard value immediately. */\n            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n            portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n            #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )\n            {\n                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n            }\n            #else\n            {\n                /* The temporary usage of the core clock has served its purpose,\n                 * as described above.  Resume usage of the other clock. */\n                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\n\n                if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n                {\n                    /* The partial tick period already ended.  Be sure the SysTick\n                     * counts it only once. */\n                    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;\n                }\n\n                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n            }\n            #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */\n\n            /* Step the tick to account for any tick periods that elapsed. */\n            vTaskStepTick( ulCompleteTickPeriods );\n\n            /* Exit with interrupts enabled. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n        }\n    }\n#endif /* configUSE_TICKLESS_IDLE */\n/*-----------------------------------------------------------*/\n\n__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Calculate the constants required to configure the tick interrupt. */\n    #if ( configUSE_TICKLESS_IDLE == 1 )\n    {\n        ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );\n        xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;\n        ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\n    }\n    #endif /* configUSE_TICKLESS_IDLE */\n\n    /* Stop and reset the SysTick. */\n    portNVIC_SYSTICK_CTRL_REG = 0UL;\n    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n    /* Configure SysTick to interrupt at the requested rate. */\n    portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\n    portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvTaskExitError( void )\n{\n    volatile uint32_t ulDummy = 0UL;\n\n    /* A function that implements a task must not exit or attempt to return to\n     * its caller as there is nothing to return to. If a task wants to exit it\n     * should instead call vTaskDelete( NULL ). Artificially force an assert()\n     * to be triggered if configASSERT() is defined, then stop here so\n     * application writers can catch the error. */\n    configASSERT( ulCriticalNesting == ~0UL );\n    portDISABLE_INTERRUPTS();\n\n    while( ulDummy == 0 )\n    {\n        /* This file calls prvTaskExitError() after the scheduler has been\n         * started to remove a compiler warning about the function being\n         * defined but never called.  ulDummy is used purely to quieten other\n         * warnings about code appearing after this function is called - making\n         * ulDummy volatile makes the compiler think the function could return\n         * and therefore not output an 'unreachable code' warning for code that\n         * appears after it. */\n    }\n}\n/*-----------------------------------------------------------*/\n\n#if ( configENABLE_MPU == 1 )\n    static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */\n    {\n        #if defined( __ARMCC_VERSION )\n\n            /* Declaration when these variable are defined in code instead of being\n             * exported from linker scripts. */\n            extern uint32_t * __privileged_functions_start__;\n            extern uint32_t * __privileged_functions_end__;\n            extern uint32_t * __syscalls_flash_start__;\n            extern uint32_t * __syscalls_flash_end__;\n            extern uint32_t * __unprivileged_flash_start__;\n            extern uint32_t * __unprivileged_flash_end__;\n            extern uint32_t * __privileged_sram_start__;\n            extern uint32_t * __privileged_sram_end__;\n        #else /* if defined( __ARMCC_VERSION ) */\n            /* Declaration when these variable are exported from linker scripts. */\n            extern uint32_t __privileged_functions_start__[];\n            extern uint32_t __privileged_functions_end__[];\n            extern uint32_t __syscalls_flash_start__[];\n            extern uint32_t __syscalls_flash_end__[];\n            extern uint32_t __unprivileged_flash_start__[];\n            extern uint32_t __unprivileged_flash_end__[];\n            extern uint32_t __privileged_sram_start__[];\n            extern uint32_t __privileged_sram_end__[];\n        #endif /* defined( __ARMCC_VERSION ) */\n\n        /* The only permitted number of regions are 8 or 16. */\n        configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );\n\n        /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */\n        configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );\n\n        /* Check that the MPU is present. */\n        if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )\n        {\n            /* MAIR0 - Index 0. */\n            portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\n            /* MAIR0 - Index 1. */\n            portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\n\n            /* Setup privileged flash as Read Only so that privileged tasks can\n             * read it but not modify. */\n            portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_PRIVILEGED_READ_ONLY );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Setup unprivileged flash as Read Only by both privileged and\n             * unprivileged tasks. All tasks can read it but no-one can modify. */\n            portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_READ_ONLY );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Setup unprivileged syscalls flash as Read Only by both privileged\n             * and unprivileged tasks. All tasks can read it but no-one can modify. */\n            portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_READ_ONLY );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Setup RAM containing kernel data for privileged access only. */\n            portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\n                               ( portMPU_REGION_EXECUTE_NEVER );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Enable mem fault. */\n            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;\n\n            /* Enable MPU with privileged background access i.e. unmapped\n             * regions have privileged access. */\n            portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );\n        }\n    }\n#endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\n#if ( configENABLE_FPU == 1 )\n    static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */\n    {\n        #if ( configENABLE_TRUSTZONE == 1 )\n        {\n            /* Enable non-secure access to the FPU. */\n            SecureInit_EnableNSFPUAccess();\n        }\n        #endif /* configENABLE_TRUSTZONE */\n\n        /* CP10 = 11 ==> Full access to FPU i.e. both privileged and\n         * unprivileged code should be able to access FPU. CP11 should be\n         * programmed to the same value as CP10. */\n        *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |\n                            ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )\n                            );\n\n        /* ASPEN = 1 ==> Hardware should automatically preserve floating point\n         * context on exception entry and restore on exception return.\n         * LSPEN = 1 ==> Enable lazy context save of FP state. */\n        *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );\n    }\n#endif /* configENABLE_FPU */\n/*-----------------------------------------------------------*/\n\nvoid vPortYield( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Set a PendSV to request a context switch. */\n    portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\n\n    /* Barriers are normally not required but do ensure the code is\n     * completely within the specified behaviour for the architecture. */\n    __asm volatile ( \"dsb\" ::: \"memory\" );\n    __asm volatile ( \"isb\" );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */\n{\n    portDISABLE_INTERRUPTS();\n    ulCriticalNesting++;\n\n    /* Barriers are normally not required but do ensure the code is\n     * completely within the specified behaviour for the architecture. */\n    __asm volatile ( \"dsb\" ::: \"memory\" );\n    __asm volatile ( \"isb\" );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */\n{\n    configASSERT( ulCriticalNesting );\n    ulCriticalNesting--;\n\n    if( ulCriticalNesting == 0 )\n    {\n        portENABLE_INTERRUPTS();\n    }\n}\n/*-----------------------------------------------------------*/\n\nvoid SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */\n{\n    uint32_t ulPreviousMask;\n\n    ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();\n    {\n        /* Increment the RTOS tick. */\n        if( xTaskIncrementTick() != pdFALSE )\n        {\n            /* Pend a context switch. */\n            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\n        }\n    }\n    portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */\n{\n    #if ( configENABLE_MPU == 1 )\n        #if defined( __ARMCC_VERSION )\n\n            /* Declaration when these variable are defined in code instead of being\n             * exported from linker scripts. */\n            extern uint32_t * __syscalls_flash_start__;\n            extern uint32_t * __syscalls_flash_end__;\n        #else\n            /* Declaration when these variable are exported from linker scripts. */\n            extern uint32_t __syscalls_flash_start__[];\n            extern uint32_t __syscalls_flash_end__[];\n        #endif /* defined( __ARMCC_VERSION ) */\n    #endif /* configENABLE_MPU */\n\n    uint32_t ulPC;\n\n    #if ( configENABLE_TRUSTZONE == 1 )\n        uint32_t ulR0, ulR1;\n        extern TaskHandle_t pxCurrentTCB;\n        #if ( configENABLE_MPU == 1 )\n            uint32_t ulControl, ulIsTaskPrivileged;\n        #endif /* configENABLE_MPU */\n    #endif /* configENABLE_TRUSTZONE */\n    uint8_t ucSVCNumber;\n\n    /* Register are stored on the stack in the following order - R0, R1, R2, R3,\n     * R12, LR, PC, xPSR. */\n    ulPC = pulCallerStackAddress[ 6 ];\n    ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];\n\n    switch( ucSVCNumber )\n    {\n        #if ( configENABLE_TRUSTZONE == 1 )\n            case portSVC_ALLOCATE_SECURE_CONTEXT:\n\n                /* R0 contains the stack size passed as parameter to the\n                 * vPortAllocateSecureContext function. */\n                ulR0 = pulCallerStackAddress[ 0 ];\n\n                #if ( configENABLE_MPU == 1 )\n                {\n                    /* Read the CONTROL register value. */\n                    __asm volatile ( \"mrs %0, control\"  : \"=r\" ( ulControl ) );\n\n                    /* The task that raised the SVC is privileged if Bit[0]\n                     * in the CONTROL register is 0. */\n                    ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );\n\n                    /* Allocate and load a context for the secure task. */\n                    xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );\n                }\n                #else /* if ( configENABLE_MPU == 1 ) */\n                {\n                    /* Allocate and load a context for the secure task. */\n                    xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );\n                }\n                #endif /* configENABLE_MPU */\n\n                configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );\n                SecureContext_LoadContext( xSecureContext, pxCurrentTCB );\n                break;\n\n            case portSVC_FREE_SECURE_CONTEXT:\n\n                /* R0 contains TCB being freed and R1 contains the secure\n                 * context handle to be freed. */\n                ulR0 = pulCallerStackAddress[ 0 ];\n                ulR1 = pulCallerStackAddress[ 1 ];\n\n                /* Free the secure context. */\n                SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );\n                break;\n        #endif /* configENABLE_TRUSTZONE */\n\n        case portSVC_START_SCHEDULER:\n            #if ( configENABLE_TRUSTZONE == 1 )\n            {\n                /* De-prioritize the non-secure exceptions so that the\n                 * non-secure pendSV runs at the lowest priority. */\n                SecureInit_DePrioritizeNSExceptions();\n\n                /* Initialize the secure context management system. */\n                SecureContext_Init();\n            }\n            #endif /* configENABLE_TRUSTZONE */\n\n            #if ( configENABLE_FPU == 1 )\n            {\n                /* Setup the Floating Point Unit (FPU). */\n                prvSetupFPU();\n            }\n            #endif /* configENABLE_FPU */\n\n            /* Setup the context of the first task so that the first task starts\n             * executing. */\n            vRestoreContextOfFirstTask();\n            break;\n\n            #if ( configENABLE_MPU == 1 )\n                case portSVC_RAISE_PRIVILEGE:\n\n                    /* Only raise the privilege, if the svc was raised from any of\n                     * the system calls. */\n                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&\n                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )\n                    {\n                        vRaisePrivilege();\n                    }\n                    break;\n            #endif /* configENABLE_MPU */\n\n        default:\n            /* Incorrect SVC call. */\n            configASSERT( pdFALSE );\n    }\n}\n/*-----------------------------------------------------------*/\n/* *INDENT-OFF* */\n#if ( configENABLE_MPU == 1 )\n    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,\n                                         StackType_t * pxEndOfStack,\n                                         TaskFunction_t pxCode,\n                                         void * pvParameters,\n                                         BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */\n#else\n    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,\n                                         StackType_t * pxEndOfStack,\n                                         TaskFunction_t pxCode,\n                                         void * pvParameters ) /* PRIVILEGED_FUNCTION */\n#endif /* configENABLE_MPU */\n/* *INDENT-ON* */\n{\n    /* Simulate the stack frame as it would be created by a context switch\n     * interrupt. */\n    #if ( portPRELOAD_REGISTERS == 0 )\n    {\n        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\n        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\n        pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */\n        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */\n        pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */\n        *pxTopOfStack = portINITIAL_EXC_RETURN;\n\n        #if ( configENABLE_MPU == 1 )\n        {\n            pxTopOfStack--;\n\n            if( xRunPrivileged == pdTRUE )\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n            else\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n        }\n        #endif /* configENABLE_MPU */\n\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\n\n        #if ( configENABLE_TRUSTZONE == 1 )\n        {\n            pxTopOfStack--;\n            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\n        }\n        #endif /* configENABLE_TRUSTZONE */\n    }\n    #else /* portPRELOAD_REGISTERS */\n    {\n        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\n        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04 */\n        pxTopOfStack--;\n        *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN */\n\n        #if ( configENABLE_MPU == 1 )\n        {\n            pxTopOfStack--;\n\n            if( xRunPrivileged == pdTRUE )\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n            else\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n        }\n        #endif /* configENABLE_MPU */\n\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\n\n        #if ( configENABLE_TRUSTZONE == 1 )\n        {\n            pxTopOfStack--;\n            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\n        }\n        #endif /* configENABLE_TRUSTZONE */\n    }\n    #endif /* portPRELOAD_REGISTERS */\n\n    return pxTopOfStack;\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Make PendSV, CallSV and SysTick the same priority as the kernel. */\n    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;\n    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;\n\n    #if ( configENABLE_MPU == 1 )\n    {\n        /* Setup the Memory Protection Unit (MPU). */\n        prvSetupMPU();\n    }\n    #endif /* configENABLE_MPU */\n\n    /* Start the timer that generates the tick ISR. Interrupts are disabled\n     * here already. */\n    vPortSetupTimerInterrupt();\n\n    /* Initialize the critical nesting count ready for the first task. */\n    ulCriticalNesting = 0;\n\n    /* Start the first task. */\n    vStartFirstTask();\n\n    /* Should never get here as the tasks will now be executing. Call the task\n     * exit error function to prevent compiler warnings about a static function\n     * not being called in the case that the application writer overrides this\n     * functionality by defining configTASK_RETURN_ADDRESS. Call\n     * vTaskSwitchContext() so link time optimization does not remove the\n     * symbol. */\n    vTaskSwitchContext();\n    prvTaskExitError();\n\n    /* Should not get here. */\n    return 0;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Not implemented in ports where there is nothing to return to.\n     * Artificially force an assert. */\n    configASSERT( ulCriticalNesting == 1000UL );\n}\n/*-----------------------------------------------------------*/\n\n#if ( configENABLE_MPU == 1 )\n    void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,\n                                    const struct xMEMORY_REGION * const xRegions,\n                                    StackType_t * pxBottomOfStack,\n                                    uint32_t ulStackDepth )\n    {\n        uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;\n        int32_t lIndex = 0;\n\n        #if defined( __ARMCC_VERSION )\n\n            /* Declaration when these variable are defined in code instead of being\n             * exported from linker scripts. */\n            extern uint32_t * __privileged_sram_start__;\n            extern uint32_t * __privileged_sram_end__;\n        #else\n            /* Declaration when these variable are exported from linker scripts. */\n            extern uint32_t __privileged_sram_start__[];\n            extern uint32_t __privileged_sram_end__[];\n        #endif /* defined( __ARMCC_VERSION ) */\n\n        /* Setup MAIR0. */\n        xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\n        xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\n\n        /* This function is called automatically when the task is created - in\n         * which case the stack region parameters will be valid.  At all other\n         * times the stack parameters will not be valid and it is assumed that\n         * the stack region has already been configured. */\n        if( ulStackDepth > 0 )\n        {\n            ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;\n            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;\n\n            /* If the stack is within the privileged SRAM, do not protect it\n             * using a separate MPU region. This is needed because privileged\n             * SRAM is already protected using an MPU region and ARMv8-M does\n             * not allow overlapping MPU regions. */\n            if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) &&\n                ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) )\n            {\n                xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0;\n                xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0;\n            }\n            else\n            {\n                /* Define the region that allows access to the stack. */\n                ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK;\n                ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\n\n                xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |\n                                                             ( portMPU_REGION_NON_SHAREABLE ) |\n                                                             ( portMPU_REGION_READ_WRITE ) |\n                                                             ( portMPU_REGION_EXECUTE_NEVER );\n\n                xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) |\n                                                             ( portMPU_RLAR_ATTR_INDEX0 ) |\n                                                             ( portMPU_RLAR_REGION_ENABLE );\n            }\n        }\n\n        /* User supplied configurable regions. */\n        for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )\n        {\n            /* If xRegions is NULL i.e. the task has not specified any MPU\n             * region, the else part ensures that all the configurable MPU\n             * regions are invalidated. */\n            if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )\n            {\n                /* Translate the generic region definition contained in xRegions\n                 * into the ARMv8 specific MPU settings that are then stored in\n                 * xMPUSettings. */\n                ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;\n                ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;\n                ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\n\n                /* Start address. */\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |\n                                                                          ( portMPU_REGION_NON_SHAREABLE );\n\n                /* RO/RW. */\n                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )\n                {\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );\n                }\n                else\n                {\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );\n                }\n\n                /* XN. */\n                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )\n                {\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );\n                }\n\n                /* End Address. */\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |\n                                                                          ( portMPU_RLAR_REGION_ENABLE );\n\n                /* Normal memory/ Device memory. */\n                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )\n                {\n                    /* Attr1 in MAIR0 is configured as device memory. */\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;\n                }\n                else\n                {\n                    /* Attr0 in MAIR0 is configured as normal memory. */\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;\n                }\n            }\n            else\n            {\n                /* Invalidate the region. */\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;\n            }\n\n            lIndex++;\n        }\n    }\n#endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\nBaseType_t xPortIsInsideInterrupt( void )\n{\n    uint32_t ulCurrentInterrupt;\n    BaseType_t xReturn;\n\n    /* Obtain the number of the currently executing interrupt. Interrupt Program\n     * Status Register (IPSR) holds the exception number of the currently-executing\n     * exception or zero for Thread mode.*/\n    __asm volatile ( \"mrs %0, ipsr\" : \"=r\" ( ulCurrentInterrupt )::\"memory\" );\n\n    if( ulCurrentInterrupt == 0 )\n    {\n        xReturn = pdFALSE;\n    }\n    else\n    {\n        xReturn = pdTRUE;\n    }\n\n    return xReturn;\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM55/non_secure/portasm.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Standard includes. */\n#include <stdint.h>\n\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION\n * is defined correctly and privileged functions are placed in correct sections. */\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/* Portasm includes. */\n#include \"portasm.h\"\n\n/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the\n * header files. */\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\nvoid vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr  r2, pxCurrentTCBConst2\t\t\t\t\t\t\\n\"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n        \"\tldr  r3, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Read pxCurrentTCB. */\n        \"\tldr  r0, [r3]\t\t\t\t\t\t\t\t\t\\n\"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"\tdmb\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Complete outstanding transfers before disabling MPU. */\n            \"\tldr r2, xMPUCTRLConst2\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n            \"\tldr r4, [r2]\t\t\t\t\t\t\t\t\\n\"/* Read the value of MPU_CTRL. */\n            \"\tbic r4, #1\t\t\t\t\t\t\t\t\t\\n\"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\n            \"\tstr r4, [r2]\t\t\t\t\t\t\t\t\\n\"/* Disable MPU. */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tadds r3, #4\t\t\t\t\t\t\t\t\t\\n\"/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\n            \"\tldr  r4, [r3]\t\t\t\t\t\t\t\t\\n\"/* r4 = *r3 i.e. r4 = MAIR0. */\n            \"\tldr  r2, xMAIR0Const2\t\t\t\t\t\t\\n\"/* r2 = 0xe000edc0 [Location of MAIR0]. */\n            \"\tstr  r4, [r2]\t\t\t\t\t\t\t\t\\n\"/* Program MAIR0. */\n            \"\tldr  r2, xRNRConst2\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed98 [Location of RNR]. */\n            \"\tmovs r4, #4\t\t\t\t\t\t\t\t\t\\n\"/* r4 = 4. */\n            \"\tstr  r4, [r2]\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 4. */\n            \"\tadds r3, #4\t\t\t\t\t\t\t\t\t\\n\"/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */\n            \"\tldr  r2, xRBARConst2\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed9c [Location of RBAR]. */\n            \"\tldmia r3!, {r4-r11}\t\t\t\t\t\t\t\\n\"/* Read 4 set of RBAR/RLAR registers from TCB. */\n            \"\tstmia r2!, {r4-r11}\t\t\t\t\t\t\t\\n\"/* Write 4 set of RBAR/RLAR registers using alias registers. */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configTOTAL_MPU_REGIONS == 16 )\n            \"\tldr  r2, xRNRConst2\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed98 [Location of RNR]. */\n            \"\tmovs r4, #8\t\t\t\t\t\t\t\t\t\\n\"/* r4 = 8. */\n            \"\tstr  r4, [r2]\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 8. */\n            \"\tldr  r2, xRBARConst2\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed9c [Location of RBAR]. */\n            \"\tldmia r3!, {r4-r11}\t\t\t\t\t\t\t\\n\"/* Read 4 set of RBAR/RLAR registers from TCB. */\n            \"\tstmia r2!, {r4-r11}\t\t\t\t\t\t\t\\n\"/* Write 4 set of RBAR/RLAR registers using alias registers. */\n            \"\tldr  r2, xRNRConst2\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed98 [Location of RNR]. */\n            \"\tmovs r4, #12\t\t\t\t\t\t\t\t\\n\"/* r4 = 12. */\n            \"\tstr  r4, [r2]\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 12. */\n            \"\tldr  r2, xRBARConst2\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed9c [Location of RBAR]. */\n            \"\tldmia r3!, {r4-r11}\t\t\t\t\t\t\t\\n\"/* Read 4 set of RBAR/RLAR registers from TCB. */\n            \"\tstmia r2!, {r4-r11}\t\t\t\t\t\t\t\\n\"/* Write 4 set of RBAR/RLAR registers using alias registers. */\n        #endif /* configTOTAL_MPU_REGIONS == 16 */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tldr r2, xMPUCTRLConst2\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n            \"\tldr r4, [r2]\t\t\t\t\t\t\t\t\\n\"/* Read the value of MPU_CTRL. */\n            \"\torr r4, #1\t\t\t\t\t\t\t\t\t\\n\"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\n            \"\tstr r4, [r2]\t\t\t\t\t\t\t\t\\n\"/* Enable MPU. */\n            \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Force memory writes before continuing. */\n        #endif /* configENABLE_MPU */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"\tldm  r0!, {r1-r4}\t\t\t\t\t\t\t\\n\"/* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */\n            \"\tldr  r5, xSecureContextConst2\t\t\t\t\\n\"\n            \"\tstr  r1, [r5]\t\t\t\t\t\t\t\t\\n\"/* Set xSecureContext to this task's value for the same. */\n            \"\tmsr  psplim, r2\t\t\t\t\t\t\t\t\\n\"/* Set this task's PSPLIM value. */\n            \"\tmsr  control, r3\t\t\t\t\t\t\t\\n\"/* Set this task's CONTROL value. */\n            \"\tadds r0, #32\t\t\t\t\t\t\t\t\\n\"/* Discard everything up to r0. */\n            \"\tmsr  psp, r0\t\t\t\t\t\t\t\t\\n\"/* This is now the new top of stack to use in the task. */\n            \"\tisb\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tmov  r0, #0\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tmsr  basepri, r0\t\t\t\t\t\t\t\\n\"/* Ensure that interrupts are enabled when the first task starts. */\n            \"\tbx   r4\t\t\t\t\t\t\t\t\t\t\\n\"/* Finally, branch to EXC_RETURN. */\n        #else /* configENABLE_MPU */\n            \"\tldm  r0!, {r1-r3}\t\t\t\t\t\t\t\\n\"/* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */\n            \"\tldr  r4, xSecureContextConst2\t\t\t\t\\n\"\n            \"\tstr  r1, [r4]\t\t\t\t\t\t\t\t\\n\"/* Set xSecureContext to this task's value for the same. */\n            \"\tmsr  psplim, r2\t\t\t\t\t\t\t\t\\n\"/* Set this task's PSPLIM value. */\n            \"\tmovs r1, #2\t\t\t\t\t\t\t\t\t\\n\"/* r1 = 2. */\n            \"\tmsr  CONTROL, r1\t\t\t\t\t\t\t\\n\"/* Switch to use PSP in the thread mode. */\n            \"\tadds r0, #32\t\t\t\t\t\t\t\t\\n\"/* Discard everything up to r0. */\n            \"\tmsr  psp, r0\t\t\t\t\t\t\t\t\\n\"/* This is now the new top of stack to use in the task. */\n            \"\tisb\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tmov  r0, #0\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tmsr  basepri, r0\t\t\t\t\t\t\t\\n\"/* Ensure that interrupts are enabled when the first task starts. */\n            \"\tbx   r3\t\t\t\t\t\t\t\t\t\t\\n\"/* Finally, branch to EXC_RETURN. */\n        #endif /* configENABLE_MPU */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.align 4\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"pxCurrentTCBConst2: .word pxCurrentTCB\t\t\t\t\\n\"\n        \"xSecureContextConst2: .word xSecureContext\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"xMPUCTRLConst2: .word 0xe000ed94\t\t\t\t\\n\"\n            \"xMAIR0Const2: .word 0xe000edc0\t\t\t\t\t\\n\"\n            \"xRNRConst2: .word 0xe000ed98\t\t\t\t\t\\n\"\n            \"xRBARConst2: .word 0xe000ed9c\t\t\t\t\t\\n\"\n        #endif /* configENABLE_MPU */\n    );\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrs r0, control\t\t\t\t\t\t\t\t\t\\n\"/* r0 = CONTROL. */\n        \"\ttst r0, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\n        \"\tite ne\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmovne r0, #0\t\t\t\t\t\t\t\t\t\\n\"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\n        \"\tmoveq r0, #1\t\t\t\t\t\t\t\t\t\\n\"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return. */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.align 4\t\t\t\t\t\t\t\t\t\t\\n\"\n        ::: \"r0\", \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrs r0, control\t\t\t\t\t\t\t\t\t\\n\"/* Read the CONTROL register. */\n        \"\tbic r0, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* Clear the bit 0. */\n        \"\tmsr control, r0\t\t\t\t\t\t\t\t\t\\n\"/* Write back the new CONTROL value. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return to the caller. */\n        ::: \"r0\", \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vResetPrivilege( void ) /* __attribute__ (( naked )) */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrs r0, control\t\t\t\t\t\t\t\t\t\\n\"/* r0 = CONTROL. */\n        \"\torr r0, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* r0 = r0 | 1. */\n        \"\tmsr control, r0\t\t\t\t\t\t\t\t\t\\n\"/* CONTROL = r0. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return to the caller. */\n        ::: \"r0\", \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r0, xVTORConst\t\t\t\t\t\t\t\t\\n\"/* Use the NVIC offset register to locate the stack. */\n        \"\tldr r0, [r0]\t\t\t\t\t\t\t\t\t\\n\"/* Read the VTOR register which gives the address of vector table. */\n        \"\tldr r0, [r0]\t\t\t\t\t\t\t\t\t\\n\"/* The first entry in vector table is stack pointer. */\n        \"\tmsr msp, r0\t\t\t\t\t\t\t\t\t\t\\n\"/* Set the MSP back to the start of the stack. */\n        \"\tcpsie i\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Globally enable interrupts. */\n        \"\tcpsie f\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tsvc %0\t\t\t\t\t\t\t\t\t\t\t\\n\"/* System call to start the first task. */\n        \"\tnop\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"   .align 4\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"xVTORConst: .word 0xe000ed08\t\t\t\t\t\t\\n\"\n        ::\"i\" ( portSVC_START_SCHEDULER ) : \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nuint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrs r0, basepri\t\t\t\t\t\t\t\t\t\\n\"/* r0 = basepri. Return original basepri value. */\n        \"\tmov r1, %0\t\t\t\t\t\t\t\t\t\t\\n\"/* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */\n        \"\tmsr basepri, r1\t\t\t\t\t\t\t\t\t\\n\"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */\n        \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return. */\n        ::\"i\" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmsr basepri, r0\t\t\t\t\t\t\t\t\t\\n\"/* basepri = ulMask. */\n        \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return. */\n        ::: \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.extern SecureContext_SaveContext\t\t\t\t\\n\"\n        \"\t.extern SecureContext_LoadContext\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r3, xSecureContextConst\t\t\t\t\t\t\\n\"/* Read the location of xSecureContext i.e. &( xSecureContext ). */\n        \"\tldr r0, [r3]\t\t\t\t\t\t\t\t\t\\n\"/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */\n        \"\tldr r3, pxCurrentTCBConst\t\t\t\t\t\t\\n\"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n        \"\tldr r1, [r3]\t\t\t\t\t\t\t\t\t\\n\"/* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */\n        \"\tmrs r2, psp\t\t\t\t\t\t\t\t\t\t\\n\"/* Read PSP in r2. */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tcbz r0, save_ns_context\t\t\t\t\t\t\t\\n\"/* No secure context to save. */\n        \"\tpush {r0-r2, r14}\t\t\t\t\t\t\t\t\\n\"\n        \"\tbl SecureContext_SaveContext\t\t\t\t\t\\n\"/* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */\n        \"\tpop {r0-r3}\t\t\t\t\t\t\t\t\t\t\\n\"/* LR is now in r3. */\n        \"\tmov lr, r3\t\t\t\t\t\t\t\t\t\t\\n\"/* LR = r3. */\n        \"\tlsls r1, r3, #25\t\t\t\t\t\t\t\t\\n\"/* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\n        \"\tbpl save_ns_context\t\t\t\t\t\t\t\t\\n\"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r3, pxCurrentTCBConst\t\t\t\t\t\t\\n\"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n        \"\tldr r1, [r3]\t\t\t\t\t\t\t\t\t\\n\"/* Read pxCurrentTCB.*/\n        #if ( configENABLE_MPU == 1 )\n            \"\tsubs r2, r2, #16\t\t\t\t\t\t\t\\n\"/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */\n            \"\tstr r2, [r1]\t\t\t\t\t\t\t\t\\n\"/* Save the new top of stack in TCB. */\n            \"\tmrs r1, psplim\t\t\t\t\t\t\t\t\\n\"/* r1 = PSPLIM. */\n            \"\tmrs r3, control\t\t\t\t\t\t\t\t\\n\"/* r3 = CONTROL. */\n            \"\tmov r4, lr\t\t\t\t\t\t\t\t\t\\n\"/* r4 = LR/EXC_RETURN. */\n            \"\tstmia r2!, {r0, r1, r3, r4}\t\t\t\t\t\\n\"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\n        #else /* configENABLE_MPU */\n            \"\tsubs r2, r2, #12\t\t\t\t\t\t\t\\n\"/* Make space for xSecureContext, PSPLIM and LR on the stack. */\n            \"\tstr r2, [r1]\t\t\t\t\t\t\t\t\\n\"/* Save the new top of stack in TCB. */\n            \"\tmrs r1, psplim\t\t\t\t\t\t\t\t\\n\"/* r1 = PSPLIM. */\n            \"\tmov r3, lr\t\t\t\t\t\t\t\t\t\\n\"/* r3 = LR/EXC_RETURN. */\n            \"\tstmia r2!, {r0, r1, r3}\t\t\t\t\t\t\\n\"/* Store xSecureContext, PSPLIM and LR on the stack. */\n        #endif /* configENABLE_MPU */\n        \"\tb select_next_task\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \" save_ns_context:\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r3, pxCurrentTCBConst\t\t\t\t\t\t\\n\"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n        \"\tldr r1, [r3]\t\t\t\t\t\t\t\t\t\\n\"/* Read pxCurrentTCB. */\n        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )\n            \"\ttst lr, #0x10\t\t\t\t\t\t\t\t\\n\"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */\n            \"\tit eq\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tvstmdbeq r2!, {s16-s31}\t\t\t\t\t\t\\n\"/* Store the additional FP context registers which are not saved automatically. */\n        #endif /* configENABLE_FPU || configENABLE_MVE */\n        #if ( configENABLE_MPU == 1 )\n            \"\tsubs r2, r2, #48\t\t\t\t\t\t\t\\n\"/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */\n            \"\tstr r2, [r1]\t\t\t\t\t\t\t\t\\n\"/* Save the new top of stack in TCB. */\n            \"\tadds r2, r2, #16\t\t\t\t\t\t\t\\n\"/* r2 = r2 + 16. */\n            \"\tstm r2, {r4-r11}\t\t\t\t\t\t\t\\n\"/* Store the registers that are not saved automatically. */\n            \"\tmrs r1, psplim\t\t\t\t\t\t\t\t\\n\"/* r1 = PSPLIM. */\n            \"\tmrs r3, control\t\t\t\t\t\t\t\t\\n\"/* r3 = CONTROL. */\n            \"\tmov r4, lr\t\t\t\t\t\t\t\t\t\\n\"/* r4 = LR/EXC_RETURN. */\n            \"\tsubs r2, r2, #16\t\t\t\t\t\t\t\\n\"/* r2 = r2 - 16. */\n            \"\tstmia r2!, {r0, r1, r3, r4}\t\t\t\t\t\\n\"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\n        #else /* configENABLE_MPU */\n            \"\tsubs r2, r2, #44\t\t\t\t\t\t\t\\n\"/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */\n            \"\tstr r2, [r1]\t\t\t\t\t\t\t\t\\n\"/* Save the new top of stack in TCB. */\n            \"\tadds r2, r2, #12\t\t\t\t\t\t\t\\n\"/* r2 = r2 + 12. */\n            \"\tstm r2, {r4-r11}\t\t\t\t\t\t\t\\n\"/* Store the registers that are not saved automatically. */\n            \"\tmrs r1, psplim\t\t\t\t\t\t\t\t\\n\"/* r1 = PSPLIM. */\n            \"\tmov r3, lr\t\t\t\t\t\t\t\t\t\\n\"/* r3 = LR/EXC_RETURN. */\n            \"\tsubs r2, r2, #12\t\t\t\t\t\t\t\\n\"/* r2 = r2 - 12. */\n            \"\tstmia r2!, {r0, r1, r3}\t\t\t\t\t\t\\n\"/* Store xSecureContext, PSPLIM and LR on the stack. */\n        #endif /* configENABLE_MPU */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \" select_next_task:\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmov r0, %0\t\t\t\t\t\t\t\t\t\t\\n\"/* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */\n        \"\tmsr basepri, r0\t\t\t\t\t\t\t\t\t\\n\"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */\n        \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tbl vTaskSwitchContext\t\t\t\t\t\t\t\\n\"\n        \"\tmov r0, #0\t\t\t\t\t\t\t\t\t\t\\n\"/* r0 = 0. */\n        \"\tmsr basepri, r0\t\t\t\t\t\t\t\t\t\\n\"/* Enable interrupts. */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r3, pxCurrentTCBConst\t\t\t\t\t\t\\n\"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n        \"\tldr r1, [r3]\t\t\t\t\t\t\t\t\t\\n\"/* Read pxCurrentTCB. */\n        \"\tldr r2, [r1]\t\t\t\t\t\t\t\t\t\\n\"/* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"\tdmb\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Complete outstanding transfers before disabling MPU. */\n            \"\tldr r3, xMPUCTRLConst\t\t\t\t\t\t\\n\"/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */\n            \"\tldr r4, [r3]\t\t\t\t\t\t\t\t\\n\"/* Read the value of MPU_CTRL. */\n            \"\tbic r4, #1\t\t\t\t\t\t\t\t\t\\n\"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\n            \"\tstr r4, [r3]\t\t\t\t\t\t\t\t\\n\"/* Disable MPU. */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tadds r1, #4\t\t\t\t\t\t\t\t\t\\n\"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\n            \"\tldr r4, [r1]\t\t\t\t\t\t\t\t\\n\"/* r4 = *r1 i.e. r4 = MAIR0. */\n            \"\tldr r3, xMAIR0Const\t\t\t\t\t\t\t\\n\"/* r3 = 0xe000edc0 [Location of MAIR0]. */\n            \"\tstr r4, [r3]\t\t\t\t\t\t\t\t\\n\"/* Program MAIR0. */\n            \"\tldr r3, xRNRConst\t\t\t\t\t\t\t\\n\"/* r3 = 0xe000ed98 [Location of RNR]. */\n            \"\tmovs r4, #4\t\t\t\t\t\t\t\t\t\\n\"/* r4 = 4. */\n            \"\tstr r4, [r3]\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 4. */\n            \"\tadds r1, #4\t\t\t\t\t\t\t\t\t\\n\"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\n            \"\tldr r3, xRBARConst\t\t\t\t\t\t\t\\n\"/* r3 = 0xe000ed9c [Location of RBAR]. */\n            \"\tldmia r1!, {r4-r11}\t\t\t\t\t\t\t\\n\"/* Read 4 sets of RBAR/RLAR registers from TCB. */\n            \"\tstmia r3!, {r4-r11}\t\t\t\t\t\t\t\\n\"/* Write 4 set of RBAR/RLAR registers using alias registers. */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            #if ( configTOTAL_MPU_REGIONS == 16 )\n            \"\tldr r3, xRNRConst\t\t\t\t\t\t\t\\n\"/* r3 = 0xe000ed98 [Location of RNR]. */\n            \"\tmovs r4, #8\t\t\t\t\t\t\t\t\t\\n\"/* r4 = 8. */\n            \"\tstr r4, [r3]\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 8. */\n            \"\tldr r3, xRBARConst\t\t\t\t\t\t\t\\n\"/* r3 = 0xe000ed9c [Location of RBAR]. */\n            \"\tldmia r1!, {r4-r11}\t\t\t\t\t\t\t\\n\"/* Read 4 sets of RBAR/RLAR registers from TCB. */\n            \"\tstmia r3!, {r4-r11}\t\t\t\t\t\t\t\\n\"/* Write 4 set of RBAR/RLAR registers using alias registers. */\n            \"\tldr r3, xRNRConst\t\t\t\t\t\t\t\\n\"/* r3 = 0xe000ed98 [Location of RNR]. */\n            \"\tmovs r4, #12\t\t\t\t\t\t\t\t\\n\"/* r4 = 12. */\n            \"\tstr r4, [r3]\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 12. */\n            \"\tldr r3, xRBARConst\t\t\t\t\t\t\t\\n\"/* r3 = 0xe000ed9c [Location of RBAR]. */\n            \"\tldmia r1!, {r4-r11}\t\t\t\t\t\t\t\\n\"/* Read 4 sets of RBAR/RLAR registers from TCB. */\n            \"\tstmia r3!, {r4-r11}\t\t\t\t\t\t\t\\n\"/* Write 4 set of RBAR/RLAR registers using alias registers. */\n            #endif /* configTOTAL_MPU_REGIONS == 16 */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tldr r3, xMPUCTRLConst\t\t\t\t\t\t\\n\"/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */\n            \"\tldr r4, [r3]\t\t\t\t\t\t\t\t\\n\"/* Read the value of MPU_CTRL. */\n            \"\torr r4, #1\t\t\t\t\t\t\t\t\t\\n\"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\n            \"\tstr r4, [r3]\t\t\t\t\t\t\t\t\\n\"/* Enable MPU. */\n            \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Force memory writes before continuing. */\n        #endif /* configENABLE_MPU */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"\tldmia r2!, {r0, r1, r3, r4}\t\t\t\t\t\\n\"/* Read from stack - r0 = xSecureContext, r1 = PSPLIM, r3 = CONTROL and r4 = LR. */\n            \"\tmsr psplim, r1\t\t\t\t\t\t\t\t\\n\"/* Restore the PSPLIM register value for the task. */\n            \"\tmsr control, r3\t\t\t\t\t\t\t\t\\n\"/* Restore the CONTROL register value for the task. */\n            \"\tmov lr, r4\t\t\t\t\t\t\t\t\t\\n\"/* LR = r4. */\n            \"\tldr r3, xSecureContextConst\t\t\t\t\t\\n\"/* Read the location of xSecureContext i.e. &( xSecureContext ). */\n            \"\tstr r0, [r3]\t\t\t\t\t\t\t\t\\n\"/* Restore the task's xSecureContext. */\n            \"\tcbz r0, restore_ns_context\t\t\t\t\t\\n\"/* If there is no secure context for the task, restore the non-secure context. */\n            \"\tldr r3, pxCurrentTCBConst\t\t\t\t\t\\n\"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n            \"\tldr r1, [r3]\t\t\t\t\t\t\t\t\\n\"/* Read pxCurrentTCB. */\n            \"\tpush {r2, r4}\t\t\t\t\t\t\t\t\\n\"\n            \"\tbl SecureContext_LoadContext\t\t\t\t\\n\"/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */\n            \"\tpop {r2, r4}\t\t\t\t\t\t\t\t\\n\"\n            \"\tmov lr, r4\t\t\t\t\t\t\t\t\t\\n\"/* LR = r4. */\n            \"\tlsls r1, r4, #25\t\t\t\t\t\t\t\\n\"/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\n            \"\tbpl restore_ns_context\t\t\t\t\t\t\\n\"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\n            \"\tmsr psp, r2\t\t\t\t\t\t\t\t\t\\n\"/* Remember the new top of stack for the task. */\n            \"\tbx lr\t\t\t\t\t\t\t\t\t\t\\n\"\n        #else /* configENABLE_MPU */\n            \"\tldmia r2!, {r0, r1, r4}\t\t\t\t\t\t\\n\"/* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */\n            \"\tmsr psplim, r1\t\t\t\t\t\t\t\t\\n\"/* Restore the PSPLIM register value for the task. */\n            \"\tmov lr, r4\t\t\t\t\t\t\t\t\t\\n\"/* LR = r4. */\n            \"\tldr r3, xSecureContextConst\t\t\t\t\t\\n\"/* Read the location of xSecureContext i.e. &( xSecureContext ). */\n            \"\tstr r0, [r3]\t\t\t\t\t\t\t\t\\n\"/* Restore the task's xSecureContext. */\n            \"\tcbz r0, restore_ns_context\t\t\t\t\t\\n\"/* If there is no secure context for the task, restore the non-secure context. */\n            \"\tldr r3, pxCurrentTCBConst\t\t\t\t\t\\n\"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n            \"\tldr r1, [r3]\t\t\t\t\t\t\t\t\\n\"/* Read pxCurrentTCB. */\n            \"\tpush {r2, r4}\t\t\t\t\t\t\t\t\\n\"\n            \"\tbl SecureContext_LoadContext\t\t\t\t\\n\"/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */\n            \"\tpop {r2, r4}\t\t\t\t\t\t\t\t\\n\"\n            \"\tmov lr, r4\t\t\t\t\t\t\t\t\t\\n\"/* LR = r4. */\n            \"\tlsls r1, r4, #25\t\t\t\t\t\t\t\\n\"/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\n            \"\tbpl restore_ns_context\t\t\t\t\t\t\\n\"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\n            \"\tmsr psp, r2\t\t\t\t\t\t\t\t\t\\n\"/* Remember the new top of stack for the task. */\n            \"\tbx lr\t\t\t\t\t\t\t\t\t\t\\n\"\n        #endif /* configENABLE_MPU */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \" restore_ns_context:\t\t\t\t\t\t\t\t\\n\"\n        \"\tldmia r2!, {r4-r11}\t\t\t\t\t\t\t\t\\n\"/* Restore the registers that are not automatically restored. */\n        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )\n            \"\ttst lr, #0x10\t\t\t\t\t\t\t\t\\n\"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */\n            \"\tit eq\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tvldmiaeq r2!, {s16-s31}\t\t\t\t\t\t\\n\"/* Restore the additional FP context registers which are not restored automatically. */\n        #endif /* configENABLE_FPU || configENABLE_MVE */\n        \"\tmsr psp, r2\t\t\t\t\t\t\t\t\t\t\\n\"/* Remember the new top of stack for the task. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.align 4\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"pxCurrentTCBConst: .word pxCurrentTCB\t\t\t\t\\n\"\n        \"xSecureContextConst: .word xSecureContext\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"xMPUCTRLConst: .word 0xe000ed94\t\t\t\t\\n\"\n            \"xMAIR0Const: .word 0xe000edc0\t\t\t\t\t\\n\"\n            \"xRNRConst: .word 0xe000ed98\t\t\t\t\t\\n\"\n            \"xRBARConst: .word 0xe000ed9c\t\t\t\t\t\\n\"\n        #endif /* configENABLE_MPU */\n        ::\"i\" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\ttst lr, #4\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tite eq\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrseq r0, msp\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrsne r0, psp\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r1, svchandler_address_const\t\t\t\t\\n\"\n        \"\tbx r1\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.align 4\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"svchandler_address_const: .word vPortSVCHandler_C\t\\n\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tsvc %0\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Secure context is allocated in the supervisor call. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return. */\n        ::\"i\" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r2, [r0]\t\t\t\t\t\t\t\t\t\\n\"/* The first item in the TCB is the top of the stack. */\n        \"\tldr r1, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* The first item on the stack is the task's xSecureContext. */\n        \"\tcmp r1, #0\t\t\t\t\t\t\t\t\t\t\\n\"/* Raise svc if task's xSecureContext is not NULL. */\n        \"\tit ne\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tsvcne %0\t\t\t\t\t\t\t\t\t\t\\n\"/* Secure context is freed in the supervisor call. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return. */\n        ::\"i\" ( portSVC_FREE_SECURE_CONTEXT ) : \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM55/non_secure/portasm.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef __PORT_ASM_H__\n#define __PORT_ASM_H__\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n\n/* MPU wrappers includes. */\n#include \"mpu_wrappers.h\"\n\n/**\n * @brief Restore the context of the first task so that the first task starts\n * executing.\n */\nvoid vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Checks whether or not the processor is privileged.\n *\n * @return 1 if the processor is already privileged, 0 otherwise.\n */\nBaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );\n\n/**\n * @brief Raises the privilege level by clearing the bit 0 of the CONTROL\n * register.\n *\n * @note This is a privileged function and should only be called from the kenrel\n * code.\n *\n * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.\n *  Bit[0] = 0 --> The processor is running privileged\n *  Bit[0] = 1 --> The processor is running unprivileged.\n */\nvoid vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\n * register.\n *\n * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.\n *  Bit[0] = 0 --> The processor is running privileged\n *  Bit[0] = 1 --> The processor is running unprivileged.\n */\nvoid vResetPrivilege( void ) __attribute__( ( naked ) );\n\n/**\n * @brief Starts the first task.\n */\nvoid vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Disables interrupts.\n */\nuint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Enables interrupts.\n */\nvoid vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief PendSV Exception handler.\n */\nvoid PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief SVC Handler.\n */\nvoid SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Allocate a Secure context for the calling task.\n *\n * @param[in] ulSecureStackSize The size of the stack to be allocated on the\n * secure side for the calling task.\n */\nvoid vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) );\n\n/**\n * @brief Free the task's secure context.\n *\n * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.\n */\nvoid vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n#endif /* __PORT_ASM_H__ */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM55/non_secure/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef PORTMACRO_H\n#define PORTMACRO_H\n\n#ifdef __cplusplus\n    extern \"C\" {\n#endif\n\n#include \"portmacrocommon.h\"\n\n/*------------------------------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the given hardware\n * and compiler.\n *\n * These settings should not be altered.\n *------------------------------------------------------------------------------\n */\n\n#ifndef configENABLE_MVE\n    #error configENABLE_MVE must be defined in FreeRTOSConfig.h. Set configENABLE_MVE to 1 to enable the MVE or 0 to disable the MVE.\n#endif /* configENABLE_MVE */\n/*-----------------------------------------------------------*/\n\n/**\n * Architecture specifics.\n */\n#define portARCH_NAME                       \"Cortex-M55\"\n#define portDONT_DISCARD                    __attribute__( ( used ) )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Critical section management.\n */\n#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()\n#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )\n/*-----------------------------------------------------------*/\n\n#ifdef __cplusplus\n    }\n#endif\n\n#endif /* PORTMACRO_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef PORTMACROCOMMON_H\n    #define PORTMACROCOMMON_H\n\n    #ifdef __cplusplus\n        extern \"C\" {\n    #endif\n\n/*------------------------------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the given hardware\n * and compiler.\n *\n * These settings should not be altered.\n *------------------------------------------------------------------------------\n */\n\n    #ifndef configENABLE_FPU\n        #error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.\n    #endif /* configENABLE_FPU */\n\n    #ifndef configENABLE_MPU\n        #error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.\n    #endif /* configENABLE_MPU */\n\n    #ifndef configENABLE_TRUSTZONE\n        #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.\n    #endif /* configENABLE_TRUSTZONE */\n\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Type definitions.\n */\n    #define portCHAR          char\n    #define portFLOAT         float\n    #define portDOUBLE        double\n    #define portLONG          long\n    #define portSHORT         short\n    #define portSTACK_TYPE    uint32_t\n    #define portBASE_TYPE     long\n\n    typedef portSTACK_TYPE   StackType_t;\n    typedef long             BaseType_t;\n    typedef unsigned long    UBaseType_t;\n\n    #if ( configUSE_16_BIT_TICKS == 1 )\n        typedef uint16_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffff\n    #else\n        typedef uint32_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL\n\n/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\n * not need to be guarded with a critical section. */\n        #define portTICK_TYPE_IS_ATOMIC    1\n    #endif\n/*-----------------------------------------------------------*/\n\n/**\n * Architecture specifics.\n */\n    #define portSTACK_GROWTH                   ( -1 )\n    #define portTICK_PERIOD_MS                 ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\n    #define portBYTE_ALIGNMENT                 8\n    #define portNOP()\n    #define portINLINE                         __inline\n    #ifndef portFORCE_INLINE\n        #define portFORCE_INLINE               inline __attribute__( ( always_inline ) )\n    #endif\n    #define portHAS_STACK_OVERFLOW_CHECKING    1\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Extern declarations.\n */\n    extern BaseType_t xPortIsInsideInterrupt( void );\n\n    extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;\n\n    extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;\n    extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;\n\n    extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\n    extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\n\n    #if ( configENABLE_TRUSTZONE == 1 )\n        extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */\n        extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;\n    #endif /* configENABLE_TRUSTZONE */\n\n    #if ( configENABLE_MPU == 1 )\n        extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;\n        extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;\n    #endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\n/**\n * @brief MPU specific constants.\n */\n    #if ( configENABLE_MPU == 1 )\n        #define portUSING_MPU_WRAPPERS    1\n        #define portPRIVILEGE_BIT         ( 0x80000000UL )\n    #else\n        #define portPRIVILEGE_BIT         ( 0x0UL )\n    #endif /* configENABLE_MPU */\n\n/* MPU settings that can be overriden in FreeRTOSConfig.h. */\n#ifndef configTOTAL_MPU_REGIONS\n    /* Define to 8 for backward compatibility. */\n    #define configTOTAL_MPU_REGIONS       ( 8UL )\n#endif\n\n/* MPU regions. */\n    #define portPRIVILEGED_FLASH_REGION                   ( 0UL )\n    #define portUNPRIVILEGED_FLASH_REGION                 ( 1UL )\n    #define portUNPRIVILEGED_SYSCALLS_REGION              ( 2UL )\n    #define portPRIVILEGED_RAM_REGION                     ( 3UL )\n    #define portSTACK_REGION                              ( 4UL )\n    #define portFIRST_CONFIGURABLE_REGION                 ( 5UL )\n    #define portLAST_CONFIGURABLE_REGION                  ( configTOTAL_MPU_REGIONS - 1UL )\n    #define portNUM_CONFIGURABLE_REGIONS                  ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )\n    #define portTOTAL_NUM_REGIONS                         ( portNUM_CONFIGURABLE_REGIONS + 1 )   /* Plus one to make space for the stack region. */\n\n/* Device memory attributes used in MPU_MAIR registers.\n *\n * 8-bit values encoded as follows:\n *  Bit[7:4] - 0000 - Device Memory\n *  Bit[3:2] - 00 --> Device-nGnRnE\n *\t\t\t\t01 --> Device-nGnRE\n *\t\t\t\t10 --> Device-nGRE\n *\t\t\t\t11 --> Device-GRE\n *  Bit[1:0] - 00, Reserved.\n */\n    #define portMPU_DEVICE_MEMORY_nGnRnE                  ( 0x00 )   /* 0000 0000 */\n    #define portMPU_DEVICE_MEMORY_nGnRE                   ( 0x04 )   /* 0000 0100 */\n    #define portMPU_DEVICE_MEMORY_nGRE                    ( 0x08 )   /* 0000 1000 */\n    #define portMPU_DEVICE_MEMORY_GRE                     ( 0x0C )   /* 0000 1100 */\n\n/* Normal memory attributes used in MPU_MAIR registers. */\n    #define portMPU_NORMAL_MEMORY_NON_CACHEABLE           ( 0x44 )   /* Non-cacheable. */\n    #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE    ( 0xFF )   /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */\n\n/* Attributes used in MPU_RBAR registers. */\n    #define portMPU_REGION_NON_SHAREABLE                  ( 0UL << 3UL )\n    #define portMPU_REGION_INNER_SHAREABLE                ( 1UL << 3UL )\n    #define portMPU_REGION_OUTER_SHAREABLE                ( 2UL << 3UL )\n\n    #define portMPU_REGION_PRIVILEGED_READ_WRITE          ( 0UL << 1UL )\n    #define portMPU_REGION_READ_WRITE                     ( 1UL << 1UL )\n    #define portMPU_REGION_PRIVILEGED_READ_ONLY           ( 2UL << 1UL )\n    #define portMPU_REGION_READ_ONLY                      ( 3UL << 1UL )\n\n    #define portMPU_REGION_EXECUTE_NEVER                  ( 1UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Settings to define an MPU region.\n */\n    typedef struct MPURegionSettings\n    {\n        uint32_t ulRBAR; /**< RBAR for the region. */\n        uint32_t ulRLAR; /**< RLAR for the region. */\n    } MPURegionSettings_t;\n\n/**\n * @brief MPU settings as stored in the TCB.\n */\n    typedef struct MPU_SETTINGS\n    {\n        uint32_t ulMAIR0;                                              /**< MAIR0 for the task containing attributes for all the 4 per task regions. */\n        MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */\n    } xMPU_SETTINGS;\n/*-----------------------------------------------------------*/\n\n/**\n * @brief SVC numbers.\n */\n    #define portSVC_ALLOCATE_SECURE_CONTEXT    0\n    #define portSVC_FREE_SECURE_CONTEXT        1\n    #define portSVC_START_SCHEDULER            2\n    #define portSVC_RAISE_PRIVILEGE            3\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Scheduler utilities.\n */\n    #define portYIELD()                                 vPortYield()\n    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )\n    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )\n    #define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )\n    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Critical section management.\n */\n    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulSetInterruptMask()\n    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vClearInterruptMask( x )\n    #define portENTER_CRITICAL()                      vPortEnterCritical()\n    #define portEXIT_CRITICAL()                       vPortExitCritical()\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Tickless idle/low power functionality.\n */\n    #ifndef portSUPPRESS_TICKS_AND_SLEEP\n        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );\n        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )\n    #endif\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Task function macros as described on the FreeRTOS.org WEB site.\n */\n    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )\n    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )\n/*-----------------------------------------------------------*/\n\n    #if ( configENABLE_TRUSTZONE == 1 )\n\n/**\n * @brief Allocate a secure context for the task.\n *\n * Tasks are not created with a secure context. Any task that is going to call\n * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a\n * secure context before it calls any secure function.\n *\n * @param[in] ulSecureStackSize The size of the secure stack to be allocated.\n */\n        #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )\n\n/**\n * @brief Called when a task is deleted to delete the task's secure context,\n * if it has one.\n *\n * @param[in] pxTCB The TCB of the task being deleted.\n */\n        #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )\n    #endif /* configENABLE_TRUSTZONE */\n/*-----------------------------------------------------------*/\n\n    #if ( configENABLE_MPU == 1 )\n\n/**\n * @brief Checks whether or not the processor is privileged.\n *\n * @return 1 if the processor is already privileged, 0 otherwise.\n */\n        #define portIS_PRIVILEGED()      xIsPrivileged()\n\n/**\n * @brief Raise an SVC request to raise privilege.\n *\n * The SVC handler checks that the SVC was raised from a system call and only\n * then it raises the privilege. If this is called from any other place,\n * the privilege is not raised.\n */\n        #define portRAISE_PRIVILEGE()    __asm volatile ( \"svc %0 \\n\" ::\"i\" ( portSVC_RAISE_PRIVILEGE ) : \"memory\" );\n\n/**\n * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\n * register.\n */\n        #define portRESET_PRIVILEGE()    vResetPrivilege()\n    #else\n        #define portIS_PRIVILEGED()\n        #define portRAISE_PRIVILEGE()\n        #define portRESET_PRIVILEGE()\n    #endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Barriers.\n */\n    #define portMEMORY_BARRIER()    __asm volatile ( \"\" ::: \"memory\" )\n/*-----------------------------------------------------------*/\n\n    #ifdef __cplusplus\n        }\n    #endif\n\n#endif /* PORTMACROCOMMON_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM55/secure/secure_context.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Secure context includes. */\n#include \"secure_context.h\"\n\n/* Secure heap includes. */\n#include \"secure_heap.h\"\n\n/* Secure port macros. */\n#include \"secure_port_macros.h\"\n\n/**\n * @brief CONTROL value for privileged tasks.\n *\n * Bit[0] - 0 --> Thread mode is privileged.\n * Bit[1] - 1 --> Thread mode uses PSP.\n */\n#define securecontextCONTROL_VALUE_PRIVILEGED      0x02\n\n/**\n * @brief CONTROL value for un-privileged tasks.\n *\n * Bit[0] - 1 --> Thread mode is un-privileged.\n * Bit[1] - 1 --> Thread mode uses PSP.\n */\n#define securecontextCONTROL_VALUE_UNPRIVILEGED    0x03\n\n/**\n * @brief Size of stack seal values in bytes.\n */\n#define securecontextSTACK_SEAL_SIZE               8\n\n/**\n * @brief Stack seal value as recommended by ARM.\n */\n#define securecontextSTACK_SEAL_VALUE              0xFEF5EDA5\n\n/**\n * @brief Maximum number of secure contexts.\n */\n#ifndef secureconfigMAX_SECURE_CONTEXTS\n    #define secureconfigMAX_SECURE_CONTEXTS        8UL\n#endif\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Pre-allocated array of secure contexts.\n */\nSecureContext_t xSecureContexts[ secureconfigMAX_SECURE_CONTEXTS ];\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Get a free secure context for a task from the secure context pool (xSecureContexts).\n *\n * This function ensures that only one secure context is allocated for a task.\n *\n * @param[in] pvTaskHandle The task handle for which the secure context is allocated.\n *\n * @return Index of a free secure context in the xSecureContexts array.\n */\nstatic uint32_t ulGetSecureContext( void * pvTaskHandle );\n\n/**\n * @brief Return the secure context to the secure context pool (xSecureContexts).\n *\n * @param[in] ulSecureContextIndex Index of the context in the xSecureContexts array.\n */\nstatic void vReturnSecureContext( uint32_t ulSecureContextIndex );\n\n/* These are implemented in assembly. */\nextern void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext );\nextern void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext );\n/*-----------------------------------------------------------*/\n\nstatic uint32_t ulGetSecureContext( void * pvTaskHandle )\n{\n    /* Start with invalid index. */\n    uint32_t i, ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS;\n\n    for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ )\n    {\n        if( ( xSecureContexts[ i ].pucCurrentStackPointer == NULL ) &&\n            ( xSecureContexts[ i ].pucStackLimit == NULL ) &&\n            ( xSecureContexts[ i ].pucStackStart == NULL ) &&\n            ( xSecureContexts[ i ].pvTaskHandle == NULL ) &&\n            ( ulSecureContextIndex == secureconfigMAX_SECURE_CONTEXTS ) )\n        {\n            ulSecureContextIndex = i;\n        }\n        else if( xSecureContexts[ i ].pvTaskHandle == pvTaskHandle )\n        {\n            /* A task can only have one secure context. Do not allocate a second\n             * context for the same task. */\n            ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS;\n            break;\n        }\n    }\n\n    return ulSecureContextIndex;\n}\n/*-----------------------------------------------------------*/\n\nstatic void vReturnSecureContext( uint32_t ulSecureContextIndex )\n{\n    xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = NULL;\n    xSecureContexts[ ulSecureContextIndex ].pucStackLimit = NULL;\n    xSecureContexts[ ulSecureContextIndex ].pucStackStart = NULL;\n    xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = NULL;\n}\n/*-----------------------------------------------------------*/\n\nsecureportNON_SECURE_CALLABLE void SecureContext_Init( void )\n{\n    uint32_t ulIPSR, i;\n    static uint32_t ulSecureContextsInitialized = 0;\n\n    /* Read the Interrupt Program Status Register (IPSR) value. */\n    secureportREAD_IPSR( ulIPSR );\n\n    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\n     * when the processor is running in the Thread Mode. */\n    if( ( ulIPSR != 0 ) && ( ulSecureContextsInitialized == 0 ) )\n    {\n        /* Ensure to initialize secure contexts only once. */\n        ulSecureContextsInitialized = 1;\n\n        /* No stack for thread mode until a task's context is loaded. */\n        secureportSET_PSPLIM( securecontextNO_STACK );\n        secureportSET_PSP( securecontextNO_STACK );\n\n        /* Initialize all secure contexts. */\n        for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ )\n        {\n            xSecureContexts[ i ].pucCurrentStackPointer = NULL;\n            xSecureContexts[ i ].pucStackLimit = NULL;\n            xSecureContexts[ i ].pucStackStart = NULL;\n            xSecureContexts[ i ].pvTaskHandle = NULL;\n        }\n\n        #if ( configENABLE_MPU == 1 )\n            {\n                /* Configure thread mode to use PSP and to be unprivileged. */\n                secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );\n            }\n        #else /* configENABLE_MPU */\n            {\n                /* Configure thread mode to use PSP and to be privileged. */\n                secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );\n            }\n        #endif /* configENABLE_MPU */\n    }\n}\n/*-----------------------------------------------------------*/\n\n#if ( configENABLE_MPU == 1 )\n    secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,\n                                                                                       uint32_t ulIsTaskPrivileged,\n                                                                                       void * pvTaskHandle )\n#else /* configENABLE_MPU */\n    secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,\n                                                                                       void * pvTaskHandle )\n#endif /* configENABLE_MPU */\n{\n    uint8_t * pucStackMemory = NULL;\n    uint8_t * pucStackLimit;\n    uint32_t ulIPSR, ulSecureContextIndex;\n    SecureContextHandle_t xSecureContextHandle = securecontextINVALID_CONTEXT_ID;\n\n    #if ( configENABLE_MPU == 1 )\n        uint32_t * pulCurrentStackPointer = NULL;\n    #endif /* configENABLE_MPU */\n\n    /* Read the Interrupt Program Status Register (IPSR) and Process Stack Limit\n     * Register (PSPLIM) value. */\n    secureportREAD_IPSR( ulIPSR );\n    secureportREAD_PSPLIM( pucStackLimit );\n\n    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\n     * when the processor is running in the Thread Mode.\n     * Also do nothing, if a secure context us already loaded. PSPLIM is set to\n     * securecontextNO_STACK when no secure context is loaded. */\n    if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) )\n    {\n        /* Ontain a free secure context. */\n        ulSecureContextIndex = ulGetSecureContext( pvTaskHandle );\n\n        /* Were we able to get a free context? */\n        if( ulSecureContextIndex < secureconfigMAX_SECURE_CONTEXTS )\n        {\n            /* Allocate the stack space. */\n            pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE );\n\n            if( pucStackMemory != NULL )\n            {\n                /* Since stack grows down, the starting point will be the last\n                 * location. Note that this location is next to the last\n                 * allocated byte for stack (excluding the space for seal values)\n                 * because the hardware decrements the stack pointer before\n                 * writing i.e. if stack pointer is 0x2, a push operation will\n                 * decrement the stack pointer to 0x1 and then write at 0x1. */\n                xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize;\n\n                /* Seal the created secure process stack. */\n                *( uint32_t * )( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE;\n                *( uint32_t * )( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE;\n\n                /* The stack cannot go beyond this location. This value is\n                 * programmed in the PSPLIM register on context switch.*/\n                xSecureContexts[ ulSecureContextIndex ].pucStackLimit = pucStackMemory;\n\n                xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle;\n\n                #if ( configENABLE_MPU == 1 )\n                    {\n                        /* Store the correct CONTROL value for the task on the stack.\n                         * This value is programmed in the CONTROL register on\n                         * context switch. */\n                        pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart;\n                        pulCurrentStackPointer--;\n\n                        if( ulIsTaskPrivileged )\n                        {\n                            *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;\n                        }\n                        else\n                        {\n                            *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;\n                        }\n\n                        /* Store the current stack pointer. This value is programmed in\n                         * the PSP register on context switch. */\n                        xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;\n                    }\n                #else /* configENABLE_MPU */\n                    {\n                        /* Current SP is set to the starting of the stack. This\n                         * value programmed in the PSP register on context switch. */\n                        xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart;\n                    }\n                #endif /* configENABLE_MPU */\n\n                /* Ensure to never return 0 as a valid context handle. */\n                xSecureContextHandle = ulSecureContextIndex + 1UL;\n            }\n        }\n    }\n\n    return xSecureContextHandle;\n}\n/*-----------------------------------------------------------*/\n\nsecureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )\n{\n    uint32_t ulIPSR, ulSecureContextIndex;\n\n    /* Read the Interrupt Program Status Register (IPSR) value. */\n    secureportREAD_IPSR( ulIPSR );\n\n    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\n     * when the processor is running in the Thread Mode. */\n    if( ulIPSR != 0 )\n    {\n        /* Only free if a valid context handle is passed. */\n        if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) )\n        {\n            ulSecureContextIndex = xSecureContextHandle - 1UL;\n\n            /* Ensure that the secure context being deleted is associated with\n             * the task. */\n            if( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle )\n            {\n                /* Free the stack space. */\n                vPortFree( xSecureContexts[ ulSecureContextIndex ].pucStackLimit );\n\n                /* Return the secure context back to the free secure contexts pool. */\n                vReturnSecureContext( ulSecureContextIndex );\n            }\n        }\n    }\n}\n/*-----------------------------------------------------------*/\n\nsecureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )\n{\n    uint8_t * pucStackLimit;\n    uint32_t ulSecureContextIndex;\n\n    if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) )\n    {\n        ulSecureContextIndex = xSecureContextHandle - 1UL;\n\n        secureportREAD_PSPLIM( pucStackLimit );\n\n        /* Ensure that no secure context is loaded and the task is loading it's\n         * own context. */\n        if( ( pucStackLimit == securecontextNO_STACK ) &&\n            ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) )\n        {\n            SecureContext_LoadContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) );\n        }\n    }\n}\n/*-----------------------------------------------------------*/\n\nsecureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )\n{\n    uint8_t * pucStackLimit;\n    uint32_t ulSecureContextIndex;\n\n    if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) )\n    {\n        ulSecureContextIndex = xSecureContextHandle - 1UL;\n\n        secureportREAD_PSPLIM( pucStackLimit );\n\n        /* Ensure that task's context is loaded and the task is saving it's own\n         * context. */\n        if( ( xSecureContexts[ ulSecureContextIndex ].pucStackLimit == pucStackLimit ) &&\n            ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) )\n        {\n            SecureContext_SaveContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) );\n        }\n    }\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM55/secure/secure_context.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef __SECURE_CONTEXT_H__\n#define __SECURE_CONTEXT_H__\n\n/* Standard includes. */\n#include <stdint.h>\n\n/* FreeRTOS includes. */\n#include \"FreeRTOSConfig.h\"\n\n/**\n * @brief PSP value when no secure context is loaded.\n */\n#define securecontextNO_STACK               0x0\n\n/**\n * @brief Invalid context ID.\n */\n#define securecontextINVALID_CONTEXT_ID     0UL\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Structure to represent a secure context.\n *\n * @note Since stack grows down, pucStackStart is the highest address while\n * pucStackLimit is the first address of the allocated memory.\n */\ntypedef struct SecureContext\n{\n    uint8_t * pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */\n    uint8_t * pucStackLimit;          /**< Last location of the stack memory (PSPLIM). */\n    uint8_t * pucStackStart;          /**< First location of the stack memory. */\n    void * pvTaskHandle;              /**< Task handle of the task this context is associated with. */\n} SecureContext_t;\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Opaque handle for a secure context.\n */\ntypedef uint32_t SecureContextHandle_t;\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Initializes the secure context management system.\n *\n * PSP is set to NULL and therefore a task must allocate and load a context\n * before calling any secure side function in the thread mode.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n */\nvoid SecureContext_Init( void );\n\n/**\n * @brief Allocates a context on the secure side.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n *\n * @param[in] ulSecureStackSize Size of the stack to allocate on secure side.\n * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise.\n *\n * @return Opaque context handle if context is successfully allocated, NULL\n * otherwise.\n */\n#if ( configENABLE_MPU == 1 )\n    SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,\n                                                         uint32_t ulIsTaskPrivileged,\n                                                         void * pvTaskHandle );\n#else /* configENABLE_MPU */\n    SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,\n                                                         void * pvTaskHandle );\n#endif /* configENABLE_MPU */\n\n/**\n * @brief Frees the given context.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n *\n * @param[in] xSecureContextHandle Context handle corresponding to the\n * context to be freed.\n */\nvoid SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );\n\n/**\n * @brief Loads the given context.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n *\n * @param[in] xSecureContextHandle Context handle corresponding to the context\n * to be loaded.\n */\nvoid SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );\n\n/**\n * @brief Saves the given context.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n *\n * @param[in] xSecureContextHandle Context handle corresponding to the context\n * to be saved.\n */\nvoid SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );\n\n#endif /* __SECURE_CONTEXT_H__ */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM55/secure/secure_context_port.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Secure context includes. */\n#include \"secure_context.h\"\n\n/* Secure port macros. */\n#include \"secure_port_macros.h\"\n\nvoid SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) );\nvoid SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) );\n\nvoid SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext )\n{\n    /* pxSecureContext value is in r0. */\n    __asm volatile\n    (\n        \" .syntax unified                   \\n\"\n        \"                                   \\n\"\n        \" mrs r1, ipsr                      \\n\" /* r1 = IPSR. */\n        \" cbz r1, load_ctx_therad_mode      \\n\" /* Do nothing if the processor is running in the Thread Mode. */\n        \" ldmia r0!, {r1, r2}               \\n\" /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */\n        \"                                   \\n\"\n        #if ( configENABLE_MPU == 1 )\n            \" ldmia r1!, {r3}               \\n\" /* Read CONTROL register value from task's stack. r3 = CONTROL. */\n            \" msr control, r3               \\n\" /* CONTROL = r3. */\n        #endif /* configENABLE_MPU */\n        \"                                   \\n\"\n        \" msr psplim, r2                    \\n\" /* PSPLIM = r2. */\n        \" msr psp, r1                       \\n\" /* PSP = r1. */\n        \"                                   \\n\"\n        \" load_ctx_therad_mode:             \\n\"\n        \"    bx lr                          \\n\"\n        \"                                   \\n\"\n        ::: \"r0\", \"r1\", \"r2\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext )\n{\n    /* pxSecureContext value is in r0. */\n    __asm volatile\n    (\n        \" .syntax unified                   \\n\"\n        \"                                   \\n\"\n        \" mrs r1, ipsr                      \\n\" /* r1 = IPSR. */\n        \" cbz r1, save_ctx_therad_mode      \\n\" /* Do nothing if the processor is running in the Thread Mode. */\n        \" mrs r1, psp                       \\n\" /* r1 = PSP. */\n        \"                                   \\n\"\n        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )\n            \" vstmdb r1!, {s0}              \\n\" /* Trigger the deferred stacking of FPU registers. */\n            \" vldmia r1!, {s0}              \\n\" /* Nullify the effect of the previous statement. */\n        #endif /* configENABLE_FPU || configENABLE_MVE */\n        \"                                   \\n\"\n        #if ( configENABLE_MPU == 1 )\n            \" mrs r2, control               \\n\" /* r2 = CONTROL. */\n            \" stmdb r1!, {r2}               \\n\" /* Store CONTROL value on the stack. */\n        #endif /* configENABLE_MPU */\n        \"                                   \\n\"\n        \" str r1, [r0]                      \\n\" /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */\n        \" movs r1, %0                       \\n\" /* r1 = securecontextNO_STACK. */\n        \" msr psplim, r1                    \\n\" /* PSPLIM = securecontextNO_STACK. */\n        \" msr psp, r1                       \\n\" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */\n        \"                                   \\n\"\n        \" save_ctx_therad_mode:             \\n\"\n        \"    bx lr                          \\n\"\n        \"                                   \\n\"\n        ::\"i\" ( securecontextNO_STACK ) : \"r1\", \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM55/secure/secure_heap.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Standard includes. */\n#include <stdint.h>\n\n/* Secure context heap includes. */\n#include \"secure_heap.h\"\n\n/* Secure port macros. */\n#include \"secure_port_macros.h\"\n\n/**\n * @brief Total heap size.\n */\n#ifndef secureconfigTOTAL_HEAP_SIZE\n    #define secureconfigTOTAL_HEAP_SIZE    ( ( ( size_t ) ( 10 * 1024 ) ) )\n#endif\n\n/* No test marker by default. */\n#ifndef mtCOVERAGE_TEST_MARKER\n    #define mtCOVERAGE_TEST_MARKER()\n#endif\n\n/* No tracing by default. */\n#ifndef traceMALLOC\n    #define traceMALLOC( pvReturn, xWantedSize )\n#endif\n\n/* No tracing by default. */\n#ifndef traceFREE\n    #define traceFREE( pv, xBlockSize )\n#endif\n\n/* Block sizes must not get too small. */\n#define secureheapMINIMUM_BLOCK_SIZE    ( ( size_t ) ( xHeapStructSize << 1 ) )\n\n/* Assumes 8bit bytes! */\n#define secureheapBITS_PER_BYTE         ( ( size_t ) 8 )\n/*-----------------------------------------------------------*/\n\n/* Allocate the memory for the heap. */\n#if ( configAPPLICATION_ALLOCATED_HEAP == 1 )\n\n/* The application writer has already defined the array used for the RTOS\n* heap - probably so it can be placed in a special segment or address. */\n    extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];\n#else /* configAPPLICATION_ALLOCATED_HEAP */\n    static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];\n#endif /* configAPPLICATION_ALLOCATED_HEAP */\n\n/**\n * @brief The linked list structure.\n *\n * This is used to link free blocks in order of their memory address.\n */\ntypedef struct A_BLOCK_LINK\n{\n    struct A_BLOCK_LINK * pxNextFreeBlock; /**< The next free block in the list. */\n    size_t xBlockSize;                     /**< The size of the free block. */\n} BlockLink_t;\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Called automatically to setup the required heap structures the first\n * time pvPortMalloc() is called.\n */\nstatic void prvHeapInit( void );\n\n/**\n * @brief Inserts a block of memory that is being freed into the correct\n * position in the list of free memory blocks.\n *\n * The block being freed will be merged with the block in front it and/or the\n * block behind it if the memory blocks are adjacent to each other.\n *\n * @param[in] pxBlockToInsert The block being freed.\n */\nstatic void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert );\n/*-----------------------------------------------------------*/\n\n/**\n * @brief The size of the structure placed at the beginning of each allocated\n * memory block must by correctly byte aligned.\n */\nstatic const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );\n\n/**\n * @brief Create a couple of list links to mark the start and end of the list.\n */\nstatic BlockLink_t xStart;\nstatic BlockLink_t * pxEnd = NULL;\n\n/**\n * @brief Keeps track of the number of free bytes remaining, but says nothing\n * about fragmentation.\n */\nstatic size_t xFreeBytesRemaining = 0U;\nstatic size_t xMinimumEverFreeBytesRemaining = 0U;\n\n/**\n * @brief Gets set to the top bit of an size_t type.\n *\n * When this bit in the xBlockSize member of an BlockLink_t structure is set\n * then the block belongs to the application. When the bit is free the block is\n * still part of the free heap space.\n */\nstatic size_t xBlockAllocatedBit = 0;\n/*-----------------------------------------------------------*/\n\nstatic void prvHeapInit( void )\n{\n    BlockLink_t * pxFirstFreeBlock;\n    uint8_t * pucAlignedHeap;\n    size_t uxAddress;\n    size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE;\n\n    /* Ensure the heap starts on a correctly aligned boundary. */\n    uxAddress = ( size_t ) ucHeap;\n\n    if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 )\n    {\n        uxAddress += ( secureportBYTE_ALIGNMENT - 1 );\n        uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );\n        xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;\n    }\n\n    pucAlignedHeap = ( uint8_t * ) uxAddress;\n\n    /* xStart is used to hold a pointer to the first item in the list of free\n     * blocks.  The void cast is used to prevent compiler warnings. */\n    xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;\n    xStart.xBlockSize = ( size_t ) 0;\n\n    /* pxEnd is used to mark the end of the list of free blocks and is inserted\n     * at the end of the heap space. */\n    uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;\n    uxAddress -= xHeapStructSize;\n    uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );\n    pxEnd = ( void * ) uxAddress;\n    pxEnd->xBlockSize = 0;\n    pxEnd->pxNextFreeBlock = NULL;\n\n    /* To start with there is a single free block that is sized to take up the\n     * entire heap space, minus the space taken by pxEnd. */\n    pxFirstFreeBlock = ( void * ) pucAlignedHeap;\n    pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;\n    pxFirstFreeBlock->pxNextFreeBlock = pxEnd;\n\n    /* Only one block exists - and it covers the entire usable heap space. */\n    xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;\n    xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;\n\n    /* Work out the position of the top bit in a size_t variable. */\n    xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert )\n{\n    BlockLink_t * pxIterator;\n    uint8_t * puc;\n\n    /* Iterate through the list until a block is found that has a higher address\n     * than the block being inserted. */\n    for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )\n    {\n        /* Nothing to do here, just iterate to the right position. */\n    }\n\n    /* Do the block being inserted, and the block it is being inserted after\n     * make a contiguous block of memory? */\n    puc = ( uint8_t * ) pxIterator;\n\n    if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )\n    {\n        pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;\n        pxBlockToInsert = pxIterator;\n    }\n    else\n    {\n        mtCOVERAGE_TEST_MARKER();\n    }\n\n    /* Do the block being inserted, and the block it is being inserted before\n     * make a contiguous block of memory? */\n    puc = ( uint8_t * ) pxBlockToInsert;\n\n    if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )\n    {\n        if( pxIterator->pxNextFreeBlock != pxEnd )\n        {\n            /* Form one big block from the two blocks. */\n            pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;\n            pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;\n        }\n        else\n        {\n            pxBlockToInsert->pxNextFreeBlock = pxEnd;\n        }\n    }\n    else\n    {\n        pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;\n    }\n\n    /* If the block being inserted plugged a gab, so was merged with the block\n     * before and the block after, then it's pxNextFreeBlock pointer will have\n     * already been set, and should not be set here as that would make it point\n     * to itself. */\n    if( pxIterator != pxBlockToInsert )\n    {\n        pxIterator->pxNextFreeBlock = pxBlockToInsert;\n    }\n    else\n    {\n        mtCOVERAGE_TEST_MARKER();\n    }\n}\n/*-----------------------------------------------------------*/\n\nvoid * pvPortMalloc( size_t xWantedSize )\n{\n    BlockLink_t * pxBlock;\n    BlockLink_t * pxPreviousBlock;\n    BlockLink_t * pxNewBlockLink;\n    void * pvReturn = NULL;\n\n    /* If this is the first call to malloc then the heap will require\n     * initialisation to setup the list of free blocks. */\n    if( pxEnd == NULL )\n    {\n        prvHeapInit();\n    }\n    else\n    {\n        mtCOVERAGE_TEST_MARKER();\n    }\n\n    /* Check the requested block size is not so large that the top bit is set.\n     * The top bit of the block size member of the BlockLink_t structure is used\n     * to determine who owns the block - the application or the kernel, so it\n     * must be free. */\n    if( ( xWantedSize & xBlockAllocatedBit ) == 0 )\n    {\n        /* The wanted size is increased so it can contain a BlockLink_t\n         * structure in addition to the requested amount of bytes. */\n        if( xWantedSize > 0 )\n        {\n            xWantedSize += xHeapStructSize;\n\n            /* Ensure that blocks are always aligned to the required number of\n             * bytes. */\n            if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )\n            {\n                /* Byte alignment required. */\n                xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );\n                secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n\n        if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )\n        {\n            /* Traverse the list from the start (lowest address) block until\n             * one of adequate size is found. */\n            pxPreviousBlock = &xStart;\n            pxBlock = xStart.pxNextFreeBlock;\n\n            while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )\n            {\n                pxPreviousBlock = pxBlock;\n                pxBlock = pxBlock->pxNextFreeBlock;\n            }\n\n            /* If the end marker was reached then a block of adequate size was\n             * not found. */\n            if( pxBlock != pxEnd )\n            {\n                /* Return the memory space pointed to - jumping over the\n                 * BlockLink_t structure at its start. */\n                pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );\n\n                /* This block is being returned for use so must be taken out\n                 * of the list of free blocks. */\n                pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;\n\n                /* If the block is larger than required it can be split into\n                 * two. */\n                if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE )\n                {\n                    /* This block is to be split into two.  Create a new\n                     * block following the number of bytes requested. The void\n                     * cast is used to prevent byte alignment warnings from the\n                     * compiler. */\n                    pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );\n                    secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 );\n\n                    /* Calculate the sizes of two blocks split from the single\n                     * block. */\n                    pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;\n                    pxBlock->xBlockSize = xWantedSize;\n\n                    /* Insert the new block into the list of free blocks. */\n                    prvInsertBlockIntoFreeList( pxNewBlockLink );\n                }\n                else\n                {\n                    mtCOVERAGE_TEST_MARKER();\n                }\n\n                xFreeBytesRemaining -= pxBlock->xBlockSize;\n\n                if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )\n                {\n                    xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;\n                }\n                else\n                {\n                    mtCOVERAGE_TEST_MARKER();\n                }\n\n                /* The block is being returned - it is allocated and owned by\n                 * the application and has no \"next\" block. */\n                pxBlock->xBlockSize |= xBlockAllocatedBit;\n                pxBlock->pxNextFreeBlock = NULL;\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n    }\n    else\n    {\n        mtCOVERAGE_TEST_MARKER();\n    }\n\n    traceMALLOC( pvReturn, xWantedSize );\n\n    #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )\n        {\n            if( pvReturn == NULL )\n            {\n                extern void vApplicationMallocFailedHook( void );\n                vApplicationMallocFailedHook();\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n    #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */\n\n    secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );\n    return pvReturn;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortFree( void * pv )\n{\n    uint8_t * puc = ( uint8_t * ) pv;\n    BlockLink_t * pxLink;\n\n    if( pv != NULL )\n    {\n        /* The memory being freed will have an BlockLink_t structure immediately\n         * before it. */\n        puc -= xHeapStructSize;\n\n        /* This casting is to keep the compiler from issuing warnings. */\n        pxLink = ( void * ) puc;\n\n        /* Check the block is actually allocated. */\n        secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );\n        secureportASSERT( pxLink->pxNextFreeBlock == NULL );\n\n        if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )\n        {\n            if( pxLink->pxNextFreeBlock == NULL )\n            {\n                /* The block is being returned to the heap - it is no longer\n                 * allocated. */\n                pxLink->xBlockSize &= ~xBlockAllocatedBit;\n\n                secureportDISABLE_NON_SECURE_INTERRUPTS();\n                {\n                    /* Add this block to the list of free blocks. */\n                    xFreeBytesRemaining += pxLink->xBlockSize;\n                    traceFREE( pv, pxLink->xBlockSize );\n                    prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );\n                }\n                secureportENABLE_NON_SECURE_INTERRUPTS();\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n    }\n}\n/*-----------------------------------------------------------*/\n\nsize_t xPortGetFreeHeapSize( void )\n{\n    return xFreeBytesRemaining;\n}\n/*-----------------------------------------------------------*/\n\nsize_t xPortGetMinimumEverFreeHeapSize( void )\n{\n    return xMinimumEverFreeBytesRemaining;\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM55/secure/secure_heap.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef __SECURE_HEAP_H__\n#define __SECURE_HEAP_H__\n\n/* Standard includes. */\n#include <stdlib.h>\n\n/**\n * @brief Allocates memory from heap.\n *\n * @param[in] xWantedSize The size of the memory to be allocated.\n *\n * @return Pointer to the memory region if the allocation is successful, NULL\n * otherwise.\n */\nvoid * pvPortMalloc( size_t xWantedSize );\n\n/**\n * @brief Frees the previously allocated memory.\n *\n * @param[in] pv Pointer to the memory to be freed.\n */\nvoid vPortFree( void * pv );\n\n/**\n * @brief Get the free heap size.\n *\n * @return Free heap size.\n */\nsize_t xPortGetFreeHeapSize( void );\n\n/**\n * @brief Get the minimum ever free heap size.\n *\n * @return Minimum ever free heap size.\n */\nsize_t xPortGetMinimumEverFreeHeapSize( void );\n\n#endif /* __SECURE_HEAP_H__ */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM55/secure/secure_init.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Standard includes. */\n#include <stdint.h>\n\n/* Secure init includes. */\n#include \"secure_init.h\"\n\n/* Secure port macros. */\n#include \"secure_port_macros.h\"\n\n/**\n * @brief Constants required to manipulate the SCB.\n */\n#define secureinitSCB_AIRCR                 ( ( volatile uint32_t * ) 0xe000ed0c )  /* Application Interrupt and Reset Control Register. */\n#define secureinitSCB_AIRCR_VECTKEY_POS     ( 16UL )\n#define secureinitSCB_AIRCR_VECTKEY_MASK    ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )\n#define secureinitSCB_AIRCR_PRIS_POS        ( 14UL )\n#define secureinitSCB_AIRCR_PRIS_MASK       ( 1UL << secureinitSCB_AIRCR_PRIS_POS )\n\n/**\n * @brief Constants required to manipulate the FPU.\n */\n#define secureinitFPCCR                     ( ( volatile uint32_t * ) 0xe000ef34 )  /* Floating Point Context Control Register. */\n#define secureinitFPCCR_LSPENS_POS          ( 29UL )\n#define secureinitFPCCR_LSPENS_MASK         ( 1UL << secureinitFPCCR_LSPENS_POS )\n#define secureinitFPCCR_TS_POS              ( 26UL )\n#define secureinitFPCCR_TS_MASK             ( 1UL << secureinitFPCCR_TS_POS )\n\n#define secureinitNSACR                     ( ( volatile uint32_t * ) 0xe000ed8c )  /* Non-secure Access Control Register. */\n#define secureinitNSACR_CP10_POS            ( 10UL )\n#define secureinitNSACR_CP10_MASK           ( 1UL << secureinitNSACR_CP10_POS )\n#define secureinitNSACR_CP11_POS            ( 11UL )\n#define secureinitNSACR_CP11_MASK           ( 1UL << secureinitNSACR_CP11_POS )\n/*-----------------------------------------------------------*/\n\nsecureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void )\n{\n    uint32_t ulIPSR;\n\n    /* Read the Interrupt Program Status Register (IPSR) value. */\n    secureportREAD_IPSR( ulIPSR );\n\n    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\n     * when the processor is running in the Thread Mode. */\n    if( ulIPSR != 0 )\n    {\n        *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |\n                                   ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |\n                                   ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK );\n    }\n}\n/*-----------------------------------------------------------*/\n\nsecureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )\n{\n    uint32_t ulIPSR;\n\n    /* Read the Interrupt Program Status Register (IPSR) value. */\n    secureportREAD_IPSR( ulIPSR );\n\n    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\n     * when the processor is running in the Thread Mode. */\n    if( ulIPSR != 0 )\n    {\n        /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is\n         * permitted. CP11 should be programmed to the same value as CP10. */\n        *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );\n\n        /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures\n         * that we can enable/disable lazy stacking in port.c file. */\n        *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK );\n\n        /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP\n         * registers (S16-S31) are also pushed to stack on exception entry and\n         * restored on exception return. */\n        *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );\n    }\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM55/secure/secure_init.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef __SECURE_INIT_H__\n#define __SECURE_INIT_H__\n\n/**\n * @brief De-prioritizes the non-secure exceptions.\n *\n * This is needed to ensure that the non-secure PendSV runs at the lowest\n * priority. Context switch is done in the non-secure PendSV handler.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n */\nvoid SecureInit_DePrioritizeNSExceptions( void );\n\n/**\n * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access.\n *\n * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point\n * Registers are not leaked to the non-secure side.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n */\nvoid SecureInit_EnableNSFPUAccess( void );\n\n#endif /* __SECURE_INIT_H__ */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM55/secure/secure_port_macros.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef __SECURE_PORT_MACROS_H__\n#define __SECURE_PORT_MACROS_H__\n\n/**\n * @brief Byte alignment requirements.\n */\n#define secureportBYTE_ALIGNMENT         8\n#define secureportBYTE_ALIGNMENT_MASK    ( 0x0007 )\n\n/**\n * @brief Macro to declare a function as non-secure callable.\n */\n#if defined( __IAR_SYSTEMS_ICC__ )\n    #define secureportNON_SECURE_CALLABLE    __cmse_nonsecure_entry __root\n#else\n    #define secureportNON_SECURE_CALLABLE    __attribute__( ( cmse_nonsecure_entry ) ) __attribute__( ( used ) )\n#endif\n\n/**\n * @brief Set the secure PRIMASK value.\n */\n#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \\\n    __asm volatile ( \"msr primask, %0\" : : \"r\" ( ulPrimaskValue ) : \"memory\" )\n\n/**\n * @brief Set the non-secure PRIMASK value.\n */\n#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \\\n    __asm volatile ( \"msr primask_ns, %0\" : : \"r\" ( ulPrimaskValue ) : \"memory\" )\n\n/**\n * @brief Read the PSP value in the given variable.\n */\n#define secureportREAD_PSP( pucOutCurrentStackPointer ) \\\n    __asm volatile ( \"mrs %0, psp\"  : \"=r\" ( pucOutCurrentStackPointer ) )\n\n/**\n * @brief Set the PSP to the given value.\n */\n#define secureportSET_PSP( pucCurrentStackPointer ) \\\n    __asm volatile ( \"msr psp, %0\" : : \"r\" ( pucCurrentStackPointer ) )\n\n/**\n * @brief Read the PSPLIM value in the given variable.\n */\n#define secureportREAD_PSPLIM( pucOutStackLimit ) \\\n    __asm volatile ( \"mrs %0, psplim\"  : \"=r\" ( pucOutStackLimit ) )\n\n/**\n * @brief Set the PSPLIM to the given value.\n */\n#define secureportSET_PSPLIM( pucStackLimit ) \\\n    __asm volatile ( \"msr psplim, %0\" : : \"r\" ( pucStackLimit ) )\n\n/**\n * @brief Set the NonSecure MSP to the given value.\n */\n#define secureportSET_MSP_NS( pucMainStackPointer ) \\\n    __asm volatile ( \"msr msp_ns, %0\" : : \"r\" ( pucMainStackPointer ) )\n\n/**\n * @brief Set the CONTROL register to the given value.\n */\n#define secureportSET_CONTROL( ulControl ) \\\n    __asm volatile ( \"msr control, %0\" : : \"r\" ( ulControl ) : \"memory\" )\n\n/**\n * @brief Read the Interrupt Program Status Register (IPSR) value in the given\n * variable.\n */\n#define secureportREAD_IPSR( ulIPSR ) \\\n    __asm volatile ( \"mrs %0, ipsr\"  : \"=r\" ( ulIPSR ) )\n\n/**\n * @brief PRIMASK value to enable interrupts.\n */\n#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL     0\n\n/**\n * @brief PRIMASK value to disable interrupts.\n */\n#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL    1\n\n/**\n * @brief Disable secure interrupts.\n */\n#define secureportDISABLE_SECURE_INTERRUPTS()        secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )\n\n/**\n * @brief Disable non-secure interrupts.\n *\n * This effectively disables context switches.\n */\n#define secureportDISABLE_NON_SECURE_INTERRUPTS()    secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )\n\n/**\n * @brief Enable non-secure interrupts.\n */\n#define secureportENABLE_NON_SECURE_INTERRUPTS()     secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL )\n\n/**\n * @brief Assert definition.\n */\n#define secureportASSERT( x )                      \\\n    if( ( x ) == 0 )                               \\\n    {                                              \\\n        secureportDISABLE_SECURE_INTERRUPTS();     \\\n        secureportDISABLE_NON_SECURE_INTERRUPTS(); \\\n        for( ; ; ) {; }                            \\\n    }\n\n#endif /* __SECURE_PORT_MACROS_H__ */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM55_NTZ/non_secure/port.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\n * all the API functions to use the MPU wrappers. That should only be done when\n * task.h is included from an application file. */\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n/* MPU wrappers includes. */\n#include \"mpu_wrappers.h\"\n\n/* Portasm includes. */\n#include \"portasm.h\"\n\n#if ( configENABLE_TRUSTZONE == 1 )\n    /* Secure components includes. */\n    #include \"secure_context.h\"\n    #include \"secure_init.h\"\n#endif /* configENABLE_TRUSTZONE */\n\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/**\n * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only\n * i.e. the processor boots as secure and never jumps to the non-secure side.\n * The Trust Zone support in the port must be disabled in order to run FreeRTOS\n * on the secure side. The following are the valid configuration seetings:\n *\n * 1. Run FreeRTOS on the Secure Side:\n *    configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0\n *\n * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:\n *    configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1\n *\n * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:\n *    configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0\n */\n#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )\n    #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.\n#endif\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the NVIC.\n */\n#define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )\n#define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )\n#define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )\n#define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )\n#define portNVIC_SYSTICK_ENABLE_BIT           ( 1UL << 0UL )\n#define portNVIC_SYSTICK_INT_BIT              ( 1UL << 1UL )\n#define portNVIC_SYSTICK_CLK_BIT              ( 1UL << 2UL )\n#define portNVIC_SYSTICK_COUNT_FLAG_BIT       ( 1UL << 16UL )\n#define portNVIC_PEND_SYSTICK_CLEAR_BIT       ( 1UL << 25UL )\n#define portNVIC_PEND_SYSTICK_SET_BIT         ( 1UL << 26UL )\n#define portMIN_INTERRUPT_PRIORITY            ( 255UL )\n#define portNVIC_PENDSV_PRI                   ( portMIN_INTERRUPT_PRIORITY << 16UL )\n#define portNVIC_SYSTICK_PRI                  ( portMIN_INTERRUPT_PRIORITY << 24UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the SCB.\n */\n#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( volatile uint32_t * ) 0xe000ed24 )\n#define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the FPU.\n */\n#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 )              /* Coprocessor Access Control Register. */\n#define portCPACR_CP10_VALUE    ( 3UL )\n#define portCPACR_CP11_VALUE    portCPACR_CP10_VALUE\n#define portCPACR_CP10_POS      ( 20UL )\n#define portCPACR_CP11_POS      ( 22UL )\n\n#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 )              /* Floating Point Context Control Register. */\n#define portFPCCR_ASPEN_POS     ( 31UL )\n#define portFPCCR_ASPEN_MASK    ( 1UL << portFPCCR_ASPEN_POS )\n#define portFPCCR_LSPEN_POS     ( 30UL )\n#define portFPCCR_LSPEN_MASK    ( 1UL << portFPCCR_LSPEN_POS )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the MPU.\n */\n#define portMPU_TYPE_REG                      ( *( ( volatile uint32_t * ) 0xe000ed90 ) )\n#define portMPU_CTRL_REG                      ( *( ( volatile uint32_t * ) 0xe000ed94 ) )\n#define portMPU_RNR_REG                       ( *( ( volatile uint32_t * ) 0xe000ed98 ) )\n\n#define portMPU_RBAR_REG                      ( *( ( volatile uint32_t * ) 0xe000ed9c ) )\n#define portMPU_RLAR_REG                      ( *( ( volatile uint32_t * ) 0xe000eda0 ) )\n\n#define portMPU_RBAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda4 ) )\n#define portMPU_RLAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda8 ) )\n\n#define portMPU_RBAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edac ) )\n#define portMPU_RLAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edb0 ) )\n\n#define portMPU_RBAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb4 ) )\n#define portMPU_RLAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb8 ) )\n\n#define portMPU_MAIR0_REG                     ( *( ( volatile uint32_t * ) 0xe000edc0 ) )\n#define portMPU_MAIR1_REG                     ( *( ( volatile uint32_t * ) 0xe000edc4 ) )\n\n#define portMPU_RBAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */\n#define portMPU_RLAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */\n\n#define portMPU_MAIR_ATTR0_POS                ( 0UL )\n#define portMPU_MAIR_ATTR0_MASK               ( 0x000000ff )\n\n#define portMPU_MAIR_ATTR1_POS                ( 8UL )\n#define portMPU_MAIR_ATTR1_MASK               ( 0x0000ff00 )\n\n#define portMPU_MAIR_ATTR2_POS                ( 16UL )\n#define portMPU_MAIR_ATTR2_MASK               ( 0x00ff0000 )\n\n#define portMPU_MAIR_ATTR3_POS                ( 24UL )\n#define portMPU_MAIR_ATTR3_MASK               ( 0xff000000 )\n\n#define portMPU_MAIR_ATTR4_POS                ( 0UL )\n#define portMPU_MAIR_ATTR4_MASK               ( 0x000000ff )\n\n#define portMPU_MAIR_ATTR5_POS                ( 8UL )\n#define portMPU_MAIR_ATTR5_MASK               ( 0x0000ff00 )\n\n#define portMPU_MAIR_ATTR6_POS                ( 16UL )\n#define portMPU_MAIR_ATTR6_MASK               ( 0x00ff0000 )\n\n#define portMPU_MAIR_ATTR7_POS                ( 24UL )\n#define portMPU_MAIR_ATTR7_MASK               ( 0xff000000 )\n\n#define portMPU_RLAR_ATTR_INDEX0              ( 0UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX1              ( 1UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX2              ( 2UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX3              ( 3UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX4              ( 4UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX5              ( 5UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX6              ( 6UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX7              ( 7UL << 1UL )\n\n#define portMPU_RLAR_REGION_ENABLE            ( 1UL )\n\n/* Enable privileged access to unmapped region. */\n#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )\n\n/* Enable MPU. */\n#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )\n\n/* Expected value of the portMPU_TYPE register. */\n#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief The maximum 24-bit number.\n *\n * It is needed because the systick is a 24-bit counter.\n */\n#define portMAX_24_BIT_NUMBER       ( 0xffffffUL )\n\n/**\n * @brief A fiddle factor to estimate the number of SysTick counts that would\n * have occurred while the SysTick counter is stopped during tickless idle\n * calculations.\n */\n#define portMISSED_COUNTS_FACTOR    ( 94UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to set up the initial stack.\n */\n#define portINITIAL_XPSR    ( 0x01000000 )\n\n#if ( configRUN_FREERTOS_SECURE_ONLY == 1 )\n\n/**\n * @brief Initial EXC_RETURN value.\n *\n *     FF         FF         FF         FD\n * 1111 1111  1111 1111  1111 1111  1111 1101\n *\n * Bit[6] - 1 --> The exception was taken from the Secure state.\n * Bit[5] - 1 --> Do not skip stacking of additional state context.\n * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\n * Bit[3] - 1 --> Return to the Thread mode.\n * Bit[2] - 1 --> Restore registers from the process stack.\n * Bit[1] - 0 --> Reserved, 0.\n * Bit[0] - 1 --> The exception was taken to the Secure state.\n */\n    #define portINITIAL_EXC_RETURN    ( 0xfffffffd )\n#else\n\n/**\n * @brief Initial EXC_RETURN value.\n *\n *     FF         FF         FF         BC\n * 1111 1111  1111 1111  1111 1111  1011 1100\n *\n * Bit[6] - 0 --> The exception was taken from the Non-Secure state.\n * Bit[5] - 1 --> Do not skip stacking of additional state context.\n * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\n * Bit[3] - 1 --> Return to the Thread mode.\n * Bit[2] - 1 --> Restore registers from the process stack.\n * Bit[1] - 0 --> Reserved, 0.\n * Bit[0] - 0 --> The exception was taken to the Non-Secure state.\n */\n    #define portINITIAL_EXC_RETURN    ( 0xffffffbc )\n#endif /* configRUN_FREERTOS_SECURE_ONLY */\n\n/**\n * @brief CONTROL register privileged bit mask.\n *\n * Bit[0] in CONTROL register tells the privilege:\n *  Bit[0] = 0 ==> The task is privileged.\n *  Bit[0] = 1 ==> The task is not privileged.\n */\n#define portCONTROL_PRIVILEGED_MASK         ( 1UL << 0UL )\n\n/**\n * @brief Initial CONTROL register values.\n */\n#define portINITIAL_CONTROL_UNPRIVILEGED    ( 0x3 )\n#define portINITIAL_CONTROL_PRIVILEGED      ( 0x2 )\n\n/**\n * @brief Let the user override the default SysTick clock rate.  If defined by the\n * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the\n * configuration register.\n */\n#ifndef configSYSTICK_CLOCK_HZ\n    #define configSYSTICK_CLOCK_HZ             ( configCPU_CLOCK_HZ )\n    /* Ensure the SysTick is clocked at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( portNVIC_SYSTICK_CLK_BIT )\n#else\n    /* Select the option to clock SysTick not at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( 0 )\n#endif\n\n/**\n * @brief Let the user override the pre-loading of the initial LR with the\n * address of prvTaskExitError() in case it messes up unwinding of the stack\n * in the debugger.\n */\n#ifdef configTASK_RETURN_ADDRESS\n    #define portTASK_RETURN_ADDRESS    configTASK_RETURN_ADDRESS\n#else\n    #define portTASK_RETURN_ADDRESS    prvTaskExitError\n#endif\n\n/**\n * @brief If portPRELOAD_REGISTERS then registers will be given an initial value\n * when a task is created. This helps in debugging at the cost of code size.\n */\n#define portPRELOAD_REGISTERS    1\n\n/**\n * @brief A task is created without a secure context, and must call\n * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes\n * any secure calls.\n */\n#define portNO_SECURE_CONTEXT    0\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Used to catch tasks that attempt to return from their implementing\n * function.\n */\nstatic void prvTaskExitError( void );\n\n#if ( configENABLE_MPU == 1 )\n\n/**\n * @brief Setup the Memory Protection Unit (MPU).\n */\n    static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\n#endif /* configENABLE_MPU */\n\n#if ( configENABLE_FPU == 1 )\n\n/**\n * @brief Setup the Floating Point Unit (FPU).\n */\n    static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;\n#endif /* configENABLE_FPU */\n\n/**\n * @brief Setup the timer to generate the tick interrupts.\n *\n * The implementation in this file is weak to allow application writers to\n * change the timer used to generate the tick interrupt.\n */\nvoid vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Checks whether the current execution context is interrupt.\n *\n * @return pdTRUE if the current execution context is interrupt, pdFALSE\n * otherwise.\n */\nBaseType_t xPortIsInsideInterrupt( void );\n\n/**\n * @brief Yield the processor.\n */\nvoid vPortYield( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Enter critical section.\n */\nvoid vPortEnterCritical( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Exit from critical section.\n */\nvoid vPortExitCritical( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief SysTick handler.\n */\nvoid SysTick_Handler( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief C part of SVC handler.\n */\nportDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION;\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Each task maintains its own interrupt status in the critical nesting\n * variable.\n */\nPRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;\n\n#if ( configENABLE_TRUSTZONE == 1 )\n\n/**\n * @brief Saved as part of the task context to indicate which context the\n * task is using on the secure side.\n */\n    PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;\n#endif /* configENABLE_TRUSTZONE */\n\n#if ( configUSE_TICKLESS_IDLE == 1 )\n\n/**\n * @brief The number of SysTick increments that make up one tick period.\n */\n    PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0;\n\n/**\n * @brief The maximum number of tick periods that can be suppressed is\n * limited by the 24 bit resolution of the SysTick timer.\n */\n    PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0;\n\n/**\n * @brief Compensate for the CPU cycles that pass while the SysTick is\n * stopped (low power functionality only).\n */\n    PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TICKLESS_IDLE == 1 )\n    __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )\n    {\n        uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;\n        TickType_t xModifiableIdleTime;\n\n        /* Make sure the SysTick reload value does not overflow the counter. */\n        if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\n        {\n            xExpectedIdleTime = xMaximumPossibleSuppressedTicks;\n        }\n\n        /* Enter a critical section but don't use the taskENTER_CRITICAL()\n         * method as that will mask interrupts that should exit sleep mode. */\n        __asm volatile ( \"cpsid i\" ::: \"memory\" );\n        __asm volatile ( \"dsb\" );\n        __asm volatile ( \"isb\" );\n\n        /* If a context switch is pending or a task is waiting for the scheduler\n         * to be unsuspended then abandon the low power entry. */\n        if( eTaskConfirmSleepModeStatus() == eAbortSleep )\n        {\n            /* Re-enable interrupts - see comments above the cpsid instruction\n             * above. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n        }\n        else\n        {\n            /* Stop the SysTick momentarily.  The time the SysTick is stopped for\n             * is accounted for as best it can be, but using the tickless mode will\n             * inevitably result in some tiny drift of the time maintained by the\n             * kernel with respect to calendar time. */\n            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );\n\n            /* Use the SysTick current-value register to determine the number of\n             * SysTick decrements remaining until the next tick interrupt.  If the\n             * current-value register is zero, then there are actually\n             * ulTimerCountsForOneTick decrements remaining, not zero, because the\n             * SysTick requests the interrupt when decrementing from 1 to 0. */\n            ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n\n            if( ulSysTickDecrementsLeft == 0 )\n            {\n                ulSysTickDecrementsLeft = ulTimerCountsForOneTick;\n            }\n\n            /* Calculate the reload value required to wait xExpectedIdleTime\n             * tick periods.  -1 is used because this code normally executes part\n             * way through the first tick period.  But if the SysTick IRQ is now\n             * pending, then clear the IRQ, suppressing the first tick, and correct\n             * the reload value to reflect that the second tick period is already\n             * underway.  The expected idle time is always at least two ticks. */\n            ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );\n\n            if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )\n            {\n                portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;\n                ulReloadValue -= ulTimerCountsForOneTick;\n            }\n\n            if( ulReloadValue > ulStoppedTimerCompensation )\n            {\n                ulReloadValue -= ulStoppedTimerCompensation;\n            }\n\n            /* Set the new reload value. */\n            portNVIC_SYSTICK_LOAD_REG = ulReloadValue;\n\n            /* Clear the SysTick count flag and set the count value back to\n             * zero. */\n            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n            /* Restart SysTick. */\n            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\n\n            /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can\n             * set its parameter to 0 to indicate that its implementation contains\n             * its own wait for interrupt or wait for event instruction, and so wfi\n             * should not be executed again.  However, the original expected idle\n             * time variable must remain unmodified, so a copy is taken. */\n            xModifiableIdleTime = xExpectedIdleTime;\n            configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\n\n            if( xModifiableIdleTime > 0 )\n            {\n                __asm volatile ( \"dsb\" ::: \"memory\" );\n                __asm volatile ( \"wfi\" );\n                __asm volatile ( \"isb\" );\n            }\n\n            configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\n\n            /* Re-enable interrupts to allow the interrupt that brought the MCU\n             * out of sleep mode to execute immediately.  See comments above\n             * the cpsid instruction above. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n            __asm volatile ( \"dsb\" );\n            __asm volatile ( \"isb\" );\n\n            /* Disable interrupts again because the clock is about to be stopped\n             * and interrupts that execute while the clock is stopped will increase\n             * any slippage between the time maintained by the RTOS and calendar\n             * time. */\n            __asm volatile ( \"cpsid i\" ::: \"memory\" );\n            __asm volatile ( \"dsb\" );\n            __asm volatile ( \"isb\" );\n\n            /* Disable the SysTick clock without reading the\n             * portNVIC_SYSTICK_CTRL_REG register to ensure the\n             * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,\n             * the time the SysTick is stopped for is accounted for as best it can\n             * be, but using the tickless mode will inevitably result in some tiny\n             * drift of the time maintained by the kernel with respect to calendar\n             * time*/\n            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );\n\n            /* Determine whether the SysTick has already counted to zero. */\n            if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n            {\n                uint32_t ulCalculatedLoadValue;\n\n                /* The tick interrupt ended the sleep (or is now pending), and\n                 * a new tick period has started.  Reset portNVIC_SYSTICK_LOAD_REG\n                 * with whatever remains of the new tick period. */\n                ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\n\n                /* Don't allow a tiny value, or values that have somehow\n                 * underflowed because the post sleep hook did something\n                 * that took too long or because the SysTick current-value register\n                 * is zero. */\n                if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )\n                {\n                    ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );\n                }\n\n                portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;\n\n                /* As the pending tick will be processed as soon as this\n                 * function exits, the tick value maintained by the tick is stepped\n                 * forward by one less than the time spent waiting. */\n                ulCompleteTickPeriods = xExpectedIdleTime - 1UL;\n            }\n            else\n            {\n                /* Something other than the tick interrupt ended the sleep. */\n\n                /* Use the SysTick current-value register to determine the\n                 * number of SysTick decrements remaining until the expected idle\n                 * time would have ended. */\n                ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n                #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )\n                {\n                    /* If the SysTick is not using the core clock, the current-\n                     * value register might still be zero here.  In that case, the\n                     * SysTick didn't load from the reload register, and there are\n                     * ulReloadValue decrements remaining in the expected idle\n                     * time, not zero. */\n                    if( ulSysTickDecrementsLeft == 0 )\n                    {\n                        ulSysTickDecrementsLeft = ulReloadValue;\n                    }\n                }\n                #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */\n\n                /* Work out how long the sleep lasted rounded to complete tick\n                 * periods (not the ulReload value which accounted for part\n                 * ticks). */\n                ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;\n\n                /* How many complete tick periods passed while the processor\n                 * was waiting? */\n                ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;\n\n                /* The reload value is set to whatever fraction of a single tick\n                 * period remains. */\n                portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;\n            }\n\n            /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,\n             * then set portNVIC_SYSTICK_LOAD_REG back to its standard value.  If\n             * the SysTick is not using the core clock, temporarily configure it to\n             * use the core clock.  This configuration forces the SysTick to load\n             * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next\n             * cycle of the other clock.  Then portNVIC_SYSTICK_LOAD_REG is ready\n             * to receive the standard value immediately. */\n            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n            portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n            #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )\n            {\n                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n            }\n            #else\n            {\n                /* The temporary usage of the core clock has served its purpose,\n                 * as described above.  Resume usage of the other clock. */\n                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\n\n                if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n                {\n                    /* The partial tick period already ended.  Be sure the SysTick\n                     * counts it only once. */\n                    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;\n                }\n\n                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n            }\n            #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */\n\n            /* Step the tick to account for any tick periods that elapsed. */\n            vTaskStepTick( ulCompleteTickPeriods );\n\n            /* Exit with interrupts enabled. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n        }\n    }\n#endif /* configUSE_TICKLESS_IDLE */\n/*-----------------------------------------------------------*/\n\n__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Calculate the constants required to configure the tick interrupt. */\n    #if ( configUSE_TICKLESS_IDLE == 1 )\n    {\n        ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );\n        xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;\n        ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\n    }\n    #endif /* configUSE_TICKLESS_IDLE */\n\n    /* Stop and reset the SysTick. */\n    portNVIC_SYSTICK_CTRL_REG = 0UL;\n    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n    /* Configure SysTick to interrupt at the requested rate. */\n    portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\n    portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvTaskExitError( void )\n{\n    volatile uint32_t ulDummy = 0UL;\n\n    /* A function that implements a task must not exit or attempt to return to\n     * its caller as there is nothing to return to. If a task wants to exit it\n     * should instead call vTaskDelete( NULL ). Artificially force an assert()\n     * to be triggered if configASSERT() is defined, then stop here so\n     * application writers can catch the error. */\n    configASSERT( ulCriticalNesting == ~0UL );\n    portDISABLE_INTERRUPTS();\n\n    while( ulDummy == 0 )\n    {\n        /* This file calls prvTaskExitError() after the scheduler has been\n         * started to remove a compiler warning about the function being\n         * defined but never called.  ulDummy is used purely to quieten other\n         * warnings about code appearing after this function is called - making\n         * ulDummy volatile makes the compiler think the function could return\n         * and therefore not output an 'unreachable code' warning for code that\n         * appears after it. */\n    }\n}\n/*-----------------------------------------------------------*/\n\n#if ( configENABLE_MPU == 1 )\n    static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */\n    {\n        #if defined( __ARMCC_VERSION )\n\n            /* Declaration when these variable are defined in code instead of being\n             * exported from linker scripts. */\n            extern uint32_t * __privileged_functions_start__;\n            extern uint32_t * __privileged_functions_end__;\n            extern uint32_t * __syscalls_flash_start__;\n            extern uint32_t * __syscalls_flash_end__;\n            extern uint32_t * __unprivileged_flash_start__;\n            extern uint32_t * __unprivileged_flash_end__;\n            extern uint32_t * __privileged_sram_start__;\n            extern uint32_t * __privileged_sram_end__;\n        #else /* if defined( __ARMCC_VERSION ) */\n            /* Declaration when these variable are exported from linker scripts. */\n            extern uint32_t __privileged_functions_start__[];\n            extern uint32_t __privileged_functions_end__[];\n            extern uint32_t __syscalls_flash_start__[];\n            extern uint32_t __syscalls_flash_end__[];\n            extern uint32_t __unprivileged_flash_start__[];\n            extern uint32_t __unprivileged_flash_end__[];\n            extern uint32_t __privileged_sram_start__[];\n            extern uint32_t __privileged_sram_end__[];\n        #endif /* defined( __ARMCC_VERSION ) */\n\n        /* The only permitted number of regions are 8 or 16. */\n        configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );\n\n        /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */\n        configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );\n\n        /* Check that the MPU is present. */\n        if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )\n        {\n            /* MAIR0 - Index 0. */\n            portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\n            /* MAIR0 - Index 1. */\n            portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\n\n            /* Setup privileged flash as Read Only so that privileged tasks can\n             * read it but not modify. */\n            portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_PRIVILEGED_READ_ONLY );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Setup unprivileged flash as Read Only by both privileged and\n             * unprivileged tasks. All tasks can read it but no-one can modify. */\n            portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_READ_ONLY );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Setup unprivileged syscalls flash as Read Only by both privileged\n             * and unprivileged tasks. All tasks can read it but no-one can modify. */\n            portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_READ_ONLY );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Setup RAM containing kernel data for privileged access only. */\n            portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\n                               ( portMPU_REGION_EXECUTE_NEVER );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Enable mem fault. */\n            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;\n\n            /* Enable MPU with privileged background access i.e. unmapped\n             * regions have privileged access. */\n            portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );\n        }\n    }\n#endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\n#if ( configENABLE_FPU == 1 )\n    static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */\n    {\n        #if ( configENABLE_TRUSTZONE == 1 )\n        {\n            /* Enable non-secure access to the FPU. */\n            SecureInit_EnableNSFPUAccess();\n        }\n        #endif /* configENABLE_TRUSTZONE */\n\n        /* CP10 = 11 ==> Full access to FPU i.e. both privileged and\n         * unprivileged code should be able to access FPU. CP11 should be\n         * programmed to the same value as CP10. */\n        *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |\n                            ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )\n                            );\n\n        /* ASPEN = 1 ==> Hardware should automatically preserve floating point\n         * context on exception entry and restore on exception return.\n         * LSPEN = 1 ==> Enable lazy context save of FP state. */\n        *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );\n    }\n#endif /* configENABLE_FPU */\n/*-----------------------------------------------------------*/\n\nvoid vPortYield( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Set a PendSV to request a context switch. */\n    portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\n\n    /* Barriers are normally not required but do ensure the code is\n     * completely within the specified behaviour for the architecture. */\n    __asm volatile ( \"dsb\" ::: \"memory\" );\n    __asm volatile ( \"isb\" );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */\n{\n    portDISABLE_INTERRUPTS();\n    ulCriticalNesting++;\n\n    /* Barriers are normally not required but do ensure the code is\n     * completely within the specified behaviour for the architecture. */\n    __asm volatile ( \"dsb\" ::: \"memory\" );\n    __asm volatile ( \"isb\" );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */\n{\n    configASSERT( ulCriticalNesting );\n    ulCriticalNesting--;\n\n    if( ulCriticalNesting == 0 )\n    {\n        portENABLE_INTERRUPTS();\n    }\n}\n/*-----------------------------------------------------------*/\n\nvoid SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */\n{\n    uint32_t ulPreviousMask;\n\n    ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();\n    {\n        /* Increment the RTOS tick. */\n        if( xTaskIncrementTick() != pdFALSE )\n        {\n            /* Pend a context switch. */\n            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\n        }\n    }\n    portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */\n{\n    #if ( configENABLE_MPU == 1 )\n        #if defined( __ARMCC_VERSION )\n\n            /* Declaration when these variable are defined in code instead of being\n             * exported from linker scripts. */\n            extern uint32_t * __syscalls_flash_start__;\n            extern uint32_t * __syscalls_flash_end__;\n        #else\n            /* Declaration when these variable are exported from linker scripts. */\n            extern uint32_t __syscalls_flash_start__[];\n            extern uint32_t __syscalls_flash_end__[];\n        #endif /* defined( __ARMCC_VERSION ) */\n    #endif /* configENABLE_MPU */\n\n    uint32_t ulPC;\n\n    #if ( configENABLE_TRUSTZONE == 1 )\n        uint32_t ulR0, ulR1;\n        extern TaskHandle_t pxCurrentTCB;\n        #if ( configENABLE_MPU == 1 )\n            uint32_t ulControl, ulIsTaskPrivileged;\n        #endif /* configENABLE_MPU */\n    #endif /* configENABLE_TRUSTZONE */\n    uint8_t ucSVCNumber;\n\n    /* Register are stored on the stack in the following order - R0, R1, R2, R3,\n     * R12, LR, PC, xPSR. */\n    ulPC = pulCallerStackAddress[ 6 ];\n    ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];\n\n    switch( ucSVCNumber )\n    {\n        #if ( configENABLE_TRUSTZONE == 1 )\n            case portSVC_ALLOCATE_SECURE_CONTEXT:\n\n                /* R0 contains the stack size passed as parameter to the\n                 * vPortAllocateSecureContext function. */\n                ulR0 = pulCallerStackAddress[ 0 ];\n\n                #if ( configENABLE_MPU == 1 )\n                {\n                    /* Read the CONTROL register value. */\n                    __asm volatile ( \"mrs %0, control\"  : \"=r\" ( ulControl ) );\n\n                    /* The task that raised the SVC is privileged if Bit[0]\n                     * in the CONTROL register is 0. */\n                    ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );\n\n                    /* Allocate and load a context for the secure task. */\n                    xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );\n                }\n                #else /* if ( configENABLE_MPU == 1 ) */\n                {\n                    /* Allocate and load a context for the secure task. */\n                    xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );\n                }\n                #endif /* configENABLE_MPU */\n\n                configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );\n                SecureContext_LoadContext( xSecureContext, pxCurrentTCB );\n                break;\n\n            case portSVC_FREE_SECURE_CONTEXT:\n\n                /* R0 contains TCB being freed and R1 contains the secure\n                 * context handle to be freed. */\n                ulR0 = pulCallerStackAddress[ 0 ];\n                ulR1 = pulCallerStackAddress[ 1 ];\n\n                /* Free the secure context. */\n                SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );\n                break;\n        #endif /* configENABLE_TRUSTZONE */\n\n        case portSVC_START_SCHEDULER:\n            #if ( configENABLE_TRUSTZONE == 1 )\n            {\n                /* De-prioritize the non-secure exceptions so that the\n                 * non-secure pendSV runs at the lowest priority. */\n                SecureInit_DePrioritizeNSExceptions();\n\n                /* Initialize the secure context management system. */\n                SecureContext_Init();\n            }\n            #endif /* configENABLE_TRUSTZONE */\n\n            #if ( configENABLE_FPU == 1 )\n            {\n                /* Setup the Floating Point Unit (FPU). */\n                prvSetupFPU();\n            }\n            #endif /* configENABLE_FPU */\n\n            /* Setup the context of the first task so that the first task starts\n             * executing. */\n            vRestoreContextOfFirstTask();\n            break;\n\n            #if ( configENABLE_MPU == 1 )\n                case portSVC_RAISE_PRIVILEGE:\n\n                    /* Only raise the privilege, if the svc was raised from any of\n                     * the system calls. */\n                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&\n                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )\n                    {\n                        vRaisePrivilege();\n                    }\n                    break;\n            #endif /* configENABLE_MPU */\n\n        default:\n            /* Incorrect SVC call. */\n            configASSERT( pdFALSE );\n    }\n}\n/*-----------------------------------------------------------*/\n/* *INDENT-OFF* */\n#if ( configENABLE_MPU == 1 )\n    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,\n                                         StackType_t * pxEndOfStack,\n                                         TaskFunction_t pxCode,\n                                         void * pvParameters,\n                                         BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */\n#else\n    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,\n                                         StackType_t * pxEndOfStack,\n                                         TaskFunction_t pxCode,\n                                         void * pvParameters ) /* PRIVILEGED_FUNCTION */\n#endif /* configENABLE_MPU */\n/* *INDENT-ON* */\n{\n    /* Simulate the stack frame as it would be created by a context switch\n     * interrupt. */\n    #if ( portPRELOAD_REGISTERS == 0 )\n    {\n        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\n        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\n        pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */\n        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */\n        pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */\n        *pxTopOfStack = portINITIAL_EXC_RETURN;\n\n        #if ( configENABLE_MPU == 1 )\n        {\n            pxTopOfStack--;\n\n            if( xRunPrivileged == pdTRUE )\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n            else\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n        }\n        #endif /* configENABLE_MPU */\n\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\n\n        #if ( configENABLE_TRUSTZONE == 1 )\n        {\n            pxTopOfStack--;\n            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\n        }\n        #endif /* configENABLE_TRUSTZONE */\n    }\n    #else /* portPRELOAD_REGISTERS */\n    {\n        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\n        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04 */\n        pxTopOfStack--;\n        *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN */\n\n        #if ( configENABLE_MPU == 1 )\n        {\n            pxTopOfStack--;\n\n            if( xRunPrivileged == pdTRUE )\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n            else\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n        }\n        #endif /* configENABLE_MPU */\n\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\n\n        #if ( configENABLE_TRUSTZONE == 1 )\n        {\n            pxTopOfStack--;\n            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\n        }\n        #endif /* configENABLE_TRUSTZONE */\n    }\n    #endif /* portPRELOAD_REGISTERS */\n\n    return pxTopOfStack;\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Make PendSV, CallSV and SysTick the same priority as the kernel. */\n    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;\n    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;\n\n    #if ( configENABLE_MPU == 1 )\n    {\n        /* Setup the Memory Protection Unit (MPU). */\n        prvSetupMPU();\n    }\n    #endif /* configENABLE_MPU */\n\n    /* Start the timer that generates the tick ISR. Interrupts are disabled\n     * here already. */\n    vPortSetupTimerInterrupt();\n\n    /* Initialize the critical nesting count ready for the first task. */\n    ulCriticalNesting = 0;\n\n    /* Start the first task. */\n    vStartFirstTask();\n\n    /* Should never get here as the tasks will now be executing. Call the task\n     * exit error function to prevent compiler warnings about a static function\n     * not being called in the case that the application writer overrides this\n     * functionality by defining configTASK_RETURN_ADDRESS. Call\n     * vTaskSwitchContext() so link time optimization does not remove the\n     * symbol. */\n    vTaskSwitchContext();\n    prvTaskExitError();\n\n    /* Should not get here. */\n    return 0;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Not implemented in ports where there is nothing to return to.\n     * Artificially force an assert. */\n    configASSERT( ulCriticalNesting == 1000UL );\n}\n/*-----------------------------------------------------------*/\n\n#if ( configENABLE_MPU == 1 )\n    void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,\n                                    const struct xMEMORY_REGION * const xRegions,\n                                    StackType_t * pxBottomOfStack,\n                                    uint32_t ulStackDepth )\n    {\n        uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;\n        int32_t lIndex = 0;\n\n        #if defined( __ARMCC_VERSION )\n\n            /* Declaration when these variable are defined in code instead of being\n             * exported from linker scripts. */\n            extern uint32_t * __privileged_sram_start__;\n            extern uint32_t * __privileged_sram_end__;\n        #else\n            /* Declaration when these variable are exported from linker scripts. */\n            extern uint32_t __privileged_sram_start__[];\n            extern uint32_t __privileged_sram_end__[];\n        #endif /* defined( __ARMCC_VERSION ) */\n\n        /* Setup MAIR0. */\n        xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\n        xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\n\n        /* This function is called automatically when the task is created - in\n         * which case the stack region parameters will be valid.  At all other\n         * times the stack parameters will not be valid and it is assumed that\n         * the stack region has already been configured. */\n        if( ulStackDepth > 0 )\n        {\n            ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;\n            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;\n\n            /* If the stack is within the privileged SRAM, do not protect it\n             * using a separate MPU region. This is needed because privileged\n             * SRAM is already protected using an MPU region and ARMv8-M does\n             * not allow overlapping MPU regions. */\n            if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) &&\n                ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) )\n            {\n                xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0;\n                xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0;\n            }\n            else\n            {\n                /* Define the region that allows access to the stack. */\n                ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK;\n                ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\n\n                xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |\n                                                             ( portMPU_REGION_NON_SHAREABLE ) |\n                                                             ( portMPU_REGION_READ_WRITE ) |\n                                                             ( portMPU_REGION_EXECUTE_NEVER );\n\n                xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) |\n                                                             ( portMPU_RLAR_ATTR_INDEX0 ) |\n                                                             ( portMPU_RLAR_REGION_ENABLE );\n            }\n        }\n\n        /* User supplied configurable regions. */\n        for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )\n        {\n            /* If xRegions is NULL i.e. the task has not specified any MPU\n             * region, the else part ensures that all the configurable MPU\n             * regions are invalidated. */\n            if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )\n            {\n                /* Translate the generic region definition contained in xRegions\n                 * into the ARMv8 specific MPU settings that are then stored in\n                 * xMPUSettings. */\n                ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;\n                ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;\n                ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\n\n                /* Start address. */\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |\n                                                                          ( portMPU_REGION_NON_SHAREABLE );\n\n                /* RO/RW. */\n                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )\n                {\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );\n                }\n                else\n                {\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );\n                }\n\n                /* XN. */\n                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )\n                {\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );\n                }\n\n                /* End Address. */\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |\n                                                                          ( portMPU_RLAR_REGION_ENABLE );\n\n                /* Normal memory/ Device memory. */\n                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )\n                {\n                    /* Attr1 in MAIR0 is configured as device memory. */\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;\n                }\n                else\n                {\n                    /* Attr0 in MAIR0 is configured as normal memory. */\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;\n                }\n            }\n            else\n            {\n                /* Invalidate the region. */\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;\n            }\n\n            lIndex++;\n        }\n    }\n#endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\nBaseType_t xPortIsInsideInterrupt( void )\n{\n    uint32_t ulCurrentInterrupt;\n    BaseType_t xReturn;\n\n    /* Obtain the number of the currently executing interrupt. Interrupt Program\n     * Status Register (IPSR) holds the exception number of the currently-executing\n     * exception or zero for Thread mode.*/\n    __asm volatile ( \"mrs %0, ipsr\" : \"=r\" ( ulCurrentInterrupt )::\"memory\" );\n\n    if( ulCurrentInterrupt == 0 )\n    {\n        xReturn = pdFALSE;\n    }\n    else\n    {\n        xReturn = pdTRUE;\n    }\n\n    return xReturn;\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Standard includes. */\n#include <stdint.h>\n\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION\n * is defined correctly and privileged functions are placed in correct sections. */\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/* Portasm includes. */\n#include \"portasm.h\"\n\n/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the\n * header files. */\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\nvoid vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr  r2, pxCurrentTCBConst2\t\t\t\t\t\t\\n\"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n        \"\tldr  r1, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Read pxCurrentTCB. */\n        \"\tldr  r0, [r1]\t\t\t\t\t\t\t\t\t\\n\"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"\tdmb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Complete outstanding transfers before disabling MPU. */\n            \"\tldr r2, xMPUCTRLConst2\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n            \"\tldr r4, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Read the value of MPU_CTRL. */\n            \"\tbic r4, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\n            \"\tstr r4, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Disable MPU. */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tadds r1, #4\t\t\t\t\t\t\t\t\t\t\\n\"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\n            \"\tldr  r3, [r1]\t\t\t\t\t\t\t\t\t\\n\"/* r3 = *r1 i.e. r3 = MAIR0. */\n            \"\tldr  r2, xMAIR0Const2\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000edc0 [Location of MAIR0]. */\n            \"\tstr  r3, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Program MAIR0. */\n            \"\tldr  r2, xRNRConst2\t\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed98 [Location of RNR]. */\n            \"\tmovs r3, #4\t\t\t\t\t\t\t\t\t\t\\n\"/* r3 = 4. */\n            \"\tstr  r3, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 4. */\n            \"\tadds r1, #4\t\t\t\t\t\t\t\t\t\t\\n\"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\n            \"\tldr  r2, xRBARConst2\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed9c [Location of RBAR]. */\n            \"\tldmia r1!, {r4-r11}\t\t\t\t\t\t\t\t\\n\"/* Read 4 set of RBAR/RLAR registers from TCB. */\n            \"\tstmia r2!, {r4-r11}\t\t\t\t\t\t\t\t\\n\"/* Write 4 set of RBAR/RLAR registers using alias registers. */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            #if ( configTOTAL_MPU_REGIONS == 16 )\n            \"\tldr  r2, xRNRConst2\t\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed98 [Location of RNR]. */\n            \"\tmovs r3, #8\t\t\t\t\t\t\t\t\t\t\\n\"/* r3 = 8. */\n            \"\tstr  r3, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 8. */\n            \"\tldr  r2, xRBARConst2\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed9c [Location of RBAR]. */\n            \"\tldmia r1!, {r4-r11}\t\t\t\t\t\t\t\t\\n\"/* Read 4 set of RBAR/RLAR registers from TCB. */\n            \"\tstmia r2!, {r4-r11}\t\t\t\t\t\t\t\t\\n\"/* Write 4 set of RBAR/RLAR registers using alias registers. */\n            \"\tldr  r2, xRNRConst2\t\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed98 [Location of RNR]. */\n            \"\tmovs r3, #12\t\t\t\t\t\t\t\t\t\\n\"/* r3 = 12. */\n            \"\tstr  r3, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 12. */\n            \"\tldr  r2, xRBARConst2\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed9c [Location of RBAR]. */\n            \"\tldmia r1!, {r4-r11}\t\t\t\t\t\t\t\t\\n\"/* Read 4 set of RBAR/RLAR registers from TCB. */\n            \"\tstmia r2!, {r4-r11}\t\t\t\t\t\t\t\t\\n\"/* Write 4 set of RBAR/RLAR registers using alias registers. */\n            #endif /* configTOTAL_MPU_REGIONS == 16 */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tldr r2, xMPUCTRLConst2\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n            \"\tldr r4, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Read the value of MPU_CTRL. */\n            \"\torr r4, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\n            \"\tstr r4, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Enable MPU. */\n            \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Force memory writes before continuing. */\n        #endif /* configENABLE_MPU */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"\tldm  r0!, {r1-r3}\t\t\t\t\t\t\t\t\\n\"/* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */\n            \"\tmsr  psplim, r1\t\t\t\t\t\t\t\t\t\\n\"/* Set this task's PSPLIM value. */\n            \"\tmsr  control, r2\t\t\t\t\t\t\t\t\\n\"/* Set this task's CONTROL value. */\n            \"\tadds r0, #32\t\t\t\t\t\t\t\t\t\\n\"/* Discard everything up to r0. */\n            \"\tmsr  psp, r0\t\t\t\t\t\t\t\t\t\\n\"/* This is now the new top of stack to use in the task. */\n            \"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tmov  r0, #0\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tmsr  basepri, r0\t\t\t\t\t\t\t\t\\n\"/* Ensure that interrupts are enabled when the first task starts. */\n            \"\tbx   r3\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Finally, branch to EXC_RETURN. */\n        #else /* configENABLE_MPU */\n            \"\tldm  r0!, {r1-r2}\t\t\t\t\t\t\t\t\\n\"/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */\n            \"\tmsr  psplim, r1\t\t\t\t\t\t\t\t\t\\n\"/* Set this task's PSPLIM value. */\n            \"\tmovs r1, #2\t\t\t\t\t\t\t\t\t\t\\n\"/* r1 = 2. */\n            \"\tmsr  CONTROL, r1\t\t\t\t\t\t\t\t\\n\"/* Switch to use PSP in the thread mode. */\n            \"\tadds r0, #32\t\t\t\t\t\t\t\t\t\\n\"/* Discard everything up to r0. */\n            \"\tmsr  psp, r0\t\t\t\t\t\t\t\t\t\\n\"/* This is now the new top of stack to use in the task. */\n            \"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tmov  r0, #0\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tmsr  basepri, r0\t\t\t\t\t\t\t\t\\n\"/* Ensure that interrupts are enabled when the first task starts. */\n            \"\tbx   r2\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Finally, branch to EXC_RETURN. */\n        #endif /* configENABLE_MPU */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.align 4\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"pxCurrentTCBConst2: .word pxCurrentTCB\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"xMPUCTRLConst2: .word 0xe000ed94\t\t\t\t\t\\n\"\n            \"xMAIR0Const2: .word 0xe000edc0\t\t\t\t\t\t\\n\"\n            \"xRNRConst2: .word 0xe000ed98\t\t\t\t\t\t\\n\"\n            \"xRBARConst2: .word 0xe000ed9c\t\t\t\t\t\t\\n\"\n        #endif /* configENABLE_MPU */\n    );\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrs r0, control\t\t\t\t\t\t\t\t\t\\n\"/* r0 = CONTROL. */\n        \"\ttst r0, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\n        \"\tite ne\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmovne r0, #0\t\t\t\t\t\t\t\t\t\\n\"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\n        \"\tmoveq r0, #1\t\t\t\t\t\t\t\t\t\\n\"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return. */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.align 4\t\t\t\t\t\t\t\t\t\t\\n\"\n        ::: \"r0\", \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrs  r0, control\t\t\t\t\t\t\t\t\\n\"/* Read the CONTROL register. */\n        \"\tbic r0, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* Clear the bit 0. */\n        \"\tmsr  control, r0\t\t\t\t\t\t\t\t\\n\"/* Write back the new CONTROL value. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return to the caller. */\n        ::: \"r0\", \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vResetPrivilege( void ) /* __attribute__ (( naked )) */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrs r0, control\t\t\t\t\t\t\t\t\t\\n\"/* r0 = CONTROL. */\n        \"\torr r0, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* r0 = r0 | 1. */\n        \"\tmsr control, r0\t\t\t\t\t\t\t\t\t\\n\"/* CONTROL = r0. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return to the caller. */\n        ::: \"r0\", \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r0, xVTORConst\t\t\t\t\t\t\t\t\\n\"/* Use the NVIC offset register to locate the stack. */\n        \"\tldr r0, [r0]\t\t\t\t\t\t\t\t\t\\n\"/* Read the VTOR register which gives the address of vector table. */\n        \"\tldr r0, [r0]\t\t\t\t\t\t\t\t\t\\n\"/* The first entry in vector table is stack pointer. */\n        \"\tmsr msp, r0\t\t\t\t\t\t\t\t\t\t\\n\"/* Set the MSP back to the start of the stack. */\n        \"\tcpsie i\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Globally enable interrupts. */\n        \"\tcpsie f\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tsvc %0\t\t\t\t\t\t\t\t\t\t\t\\n\"/* System call to start the first task. */\n        \"\tnop\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"   .align 4\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"xVTORConst: .word 0xe000ed08\t\t\t\t\t\t\\n\"\n        ::\"i\" ( portSVC_START_SCHEDULER ) : \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nuint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrs r0, basepri\t\t\t\t\t\t\t\t\t\\n\"/* r0 = basepri. Return original basepri value. */\n        \"\tmov r1, %0\t\t\t\t\t\t\t\t\t\t\\n\"/* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */\n        \"\tmsr basepri, r1\t\t\t\t\t\t\t\t\t\\n\"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */\n        \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return. */\n        ::\"i\" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmsr basepri, r0\t\t\t\t\t\t\t\t\t\\n\"/* basepri = ulMask. */\n        \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return. */\n        ::: \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrs r0, psp\t\t\t\t\t\t\t\t\t\t\\n\"/* Read PSP in r0. */\n        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )\n            \"\ttst lr, #0x10\t\t\t\t\t\t\t\t\t\\n\"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */\n            \"\tit eq\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tvstmdbeq r0!, {s16-s31}\t\t\t\t\t\t\t\\n\"/* Store the additional FP context registers which are not saved automatically. */\n        #endif /* configENABLE_FPU || configENABLE_MVE */\n        #if ( configENABLE_MPU == 1 )\n            \"\tmrs r1, psplim\t\t\t\t\t\t\t\t\t\\n\"/* r1 = PSPLIM. */\n            \"\tmrs r2, control\t\t\t\t\t\t\t\t\t\\n\"/* r2 = CONTROL. */\n            \"\tmov r3, lr\t\t\t\t\t\t\t\t\t\t\\n\"/* r3 = LR/EXC_RETURN. */\n            \"\tstmdb r0!, {r1-r11}\t\t\t\t\t\t\t\t\\n\"/* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */\n        #else /* configENABLE_MPU */\n            \"\tmrs r2, psplim\t\t\t\t\t\t\t\t\t\\n\"/* r2 = PSPLIM. */\n            \"\tmov r3, lr\t\t\t\t\t\t\t\t\t\t\\n\"/* r3 = LR/EXC_RETURN. */\n            \"\tstmdb r0!, {r2-r11}\t\t\t\t\t\t\t\t\\n\"/* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */\n        #endif /* configENABLE_MPU */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r2, pxCurrentTCBConst\t\t\t\t\t\t\\n\"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n        \"\tldr r1, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Read pxCurrentTCB. */\n        \"\tstr r0, [r1]\t\t\t\t\t\t\t\t\t\\n\"/* Save the new top of stack in TCB. */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmov r0, %0\t\t\t\t\t\t\t\t\t\t\\n\"/* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */\n        \"\tmsr basepri, r0\t\t\t\t\t\t\t\t\t\\n\"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */\n        \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tbl vTaskSwitchContext\t\t\t\t\t\t\t\\n\"\n        \"\tmov r0, #0\t\t\t\t\t\t\t\t\t\t\\n\"/* r0 = 0. */\n        \"\tmsr basepri, r0\t\t\t\t\t\t\t\t\t\\n\"/* Enable interrupts. */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r2, pxCurrentTCBConst\t\t\t\t\t\t\\n\"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n        \"\tldr r1, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Read pxCurrentTCB. */\n        \"\tldr r0, [r1]\t\t\t\t\t\t\t\t\t\\n\"/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"\tdmb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Complete outstanding transfers before disabling MPU. */\n            \"\tldr r2, xMPUCTRLConst\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n            \"\tldr r4, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Read the value of MPU_CTRL. */\n            \"\tbic r4, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\n            \"\tstr r4, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Disable MPU. */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tadds r1, #4\t\t\t\t\t\t\t\t\t\t\\n\"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\n            \"\tldr r3, [r1]\t\t\t\t\t\t\t\t\t\\n\"/* r3 = *r1 i.e. r3 = MAIR0. */\n            \"\tldr r2, xMAIR0Const\t\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000edc0 [Location of MAIR0]. */\n            \"\tstr r3, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Program MAIR0. */\n            \"\tldr r2, xRNRConst\t\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed98 [Location of RNR]. */\n            \"\tmovs r3, #4\t\t\t\t\t\t\t\t\t\t\\n\"/* r3 = 4. */\n            \"\tstr r3, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 4. */\n            \"\tadds r1, #4\t\t\t\t\t\t\t\t\t\t\\n\"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\n            \"\tldr r2, xRBARConst\t\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed9c [Location of RBAR]. */\n            \"\tldmia r1!, {r4-r11}\t\t\t\t\t\t\t\t\\n\"/* Read 4 sets of RBAR/RLAR registers from TCB. */\n            \"\tstmia r2!, {r4-r11}\t\t\t\t\t\t\t\t\\n\"/* Write 4 set of RBAR/RLAR registers using alias registers. */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            #if ( configTOTAL_MPU_REGIONS == 16 )\n            \"\tldr r2, xRNRConst\t\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed98 [Location of RNR]. */\n            \"\tmovs r3, #8\t\t\t\t\t\t\t\t\t\t\\n\"/* r3 = 8. */\n            \"\tstr r3, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 8. */\n            \"\tldr r2, xRBARConst\t\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed9c [Location of RBAR]. */\n            \"\tldmia r1!, {r4-r11}\t\t\t\t\t\t\t\t\\n\"/* Read 4 sets of RBAR/RLAR registers from TCB. */\n            \"\tstmia r2!, {r4-r11}\t\t\t\t\t\t\t\t\\n\"/* Write 4 set of RBAR/RLAR registers using alias registers. */\n            \"\tldr r2, xRNRConst\t\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed98 [Location of RNR]. */\n            \"\tmovs r3, #12\t\t\t\t\t\t\t\t\t\\n\"/* r3 = 12. */\n            \"\tstr r3, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 12. */\n            \"\tldr r2, xRBARConst\t\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed9c [Location of RBAR]. */\n            \"\tldmia r1!, {r4-r11}\t\t\t\t\t\t\t\t\\n\"/* Read 4 sets of RBAR/RLAR registers from TCB. */\n            \"\tstmia r2!, {r4-r11}\t\t\t\t\t\t\t\t\\n\"/* Write 4 set of RBAR/RLAR registers using alias registers. */\n            #endif /* configTOTAL_MPU_REGIONS == 16 */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tldr r2, xMPUCTRLConst\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n            \"\tldr r4, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Read the value of MPU_CTRL. */\n            \"\torr r4, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\n            \"\tstr r4, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Enable MPU. */\n            \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Force memory writes before continuing. */\n        #endif /* configENABLE_MPU */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"\tldmia r0!, {r1-r11}\t\t\t\t\t\t\t\t\\n\"/* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */\n        #else /* configENABLE_MPU */\n            \"\tldmia r0!, {r2-r11}\t\t\t\t\t\t\t\t\\n\"/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */\n        #endif /* configENABLE_MPU */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )\n            \"\ttst r3, #0x10\t\t\t\t\t\t\t\t\t\\n\"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */\n            \"\tit eq\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tvldmiaeq r0!, {s16-s31}\t\t\t\t\t\t\t\\n\"/* Restore the additional FP context registers which are not restored automatically. */\n        #endif /* configENABLE_FPU || configENABLE_MVE */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"\tmsr psplim, r1\t\t\t\t\t\t\t\t\t\\n\"/* Restore the PSPLIM register value for the task. */\n            \"\tmsr control, r2\t\t\t\t\t\t\t\t\t\\n\"/* Restore the CONTROL register value for the task. */\n        #else /* configENABLE_MPU */\n            \"\tmsr psplim, r2\t\t\t\t\t\t\t\t\t\\n\"/* Restore the PSPLIM register value for the task. */\n        #endif /* configENABLE_MPU */\n        \"\tmsr psp, r0\t\t\t\t\t\t\t\t\t\t\\n\"/* Remember the new top of stack for the task. */\n        \"\tbx r3\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.align 4\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"pxCurrentTCBConst: .word pxCurrentTCB\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"xMPUCTRLConst: .word 0xe000ed94\t\t\t\t\t\\n\"\n            \"xMAIR0Const: .word 0xe000edc0\t\t\t\t\t\t\\n\"\n            \"xRNRConst: .word 0xe000ed98\t\t\t\t\t\t\\n\"\n            \"xRBARConst: .word 0xe000ed9c\t\t\t\t\t\t\\n\"\n        #endif /* configENABLE_MPU */\n        ::\"i\" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\ttst lr, #4\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tite eq\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrseq r0, msp\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrsne r0, psp\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r1, svchandler_address_const\t\t\t\t\\n\"\n        \"\tbx r1\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.align 4\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"svchandler_address_const: .word vPortSVCHandler_C\t\\n\"\n    );\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef __PORT_ASM_H__\n#define __PORT_ASM_H__\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n\n/* MPU wrappers includes. */\n#include \"mpu_wrappers.h\"\n\n/**\n * @brief Restore the context of the first task so that the first task starts\n * executing.\n */\nvoid vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Checks whether or not the processor is privileged.\n *\n * @return 1 if the processor is already privileged, 0 otherwise.\n */\nBaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );\n\n/**\n * @brief Raises the privilege level by clearing the bit 0 of the CONTROL\n * register.\n *\n * @note This is a privileged function and should only be called from the kenrel\n * code.\n *\n * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.\n *  Bit[0] = 0 --> The processor is running privileged\n *  Bit[0] = 1 --> The processor is running unprivileged.\n */\nvoid vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\n * register.\n *\n * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.\n *  Bit[0] = 0 --> The processor is running privileged\n *  Bit[0] = 1 --> The processor is running unprivileged.\n */\nvoid vResetPrivilege( void ) __attribute__( ( naked ) );\n\n/**\n * @brief Starts the first task.\n */\nvoid vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Disables interrupts.\n */\nuint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Enables interrupts.\n */\nvoid vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief PendSV Exception handler.\n */\nvoid PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief SVC Handler.\n */\nvoid SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Allocate a Secure context for the calling task.\n *\n * @param[in] ulSecureStackSize The size of the stack to be allocated on the\n * secure side for the calling task.\n */\nvoid vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) );\n\n/**\n * @brief Free the task's secure context.\n *\n * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.\n */\nvoid vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n#endif /* __PORT_ASM_H__ */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM55_NTZ/non_secure/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef PORTMACRO_H\n#define PORTMACRO_H\n\n#ifdef __cplusplus\n    extern \"C\" {\n#endif\n\n#include \"portmacrocommon.h\"\n\n/*------------------------------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the given hardware\n * and compiler.\n *\n * These settings should not be altered.\n *------------------------------------------------------------------------------\n */\n\n#ifndef configENABLE_MVE\n    #error configENABLE_MVE must be defined in FreeRTOSConfig.h. Set configENABLE_MVE to 1 to enable the MVE or 0 to disable the MVE.\n#endif /* configENABLE_MVE */\n/*-----------------------------------------------------------*/\n\n/**\n * Architecture specifics.\n */\n#define portARCH_NAME                       \"Cortex-M55\"\n#define portDONT_DISCARD                    __attribute__( ( used ) )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Critical section management.\n */\n#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()\n#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )\n/*-----------------------------------------------------------*/\n\n#ifdef __cplusplus\n    }\n#endif\n\n#endif /* PORTMACRO_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef PORTMACROCOMMON_H\n    #define PORTMACROCOMMON_H\n\n    #ifdef __cplusplus\n        extern \"C\" {\n    #endif\n\n/*------------------------------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the given hardware\n * and compiler.\n *\n * These settings should not be altered.\n *------------------------------------------------------------------------------\n */\n\n    #ifndef configENABLE_FPU\n        #error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.\n    #endif /* configENABLE_FPU */\n\n    #ifndef configENABLE_MPU\n        #error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.\n    #endif /* configENABLE_MPU */\n\n    #ifndef configENABLE_TRUSTZONE\n        #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.\n    #endif /* configENABLE_TRUSTZONE */\n\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Type definitions.\n */\n    #define portCHAR          char\n    #define portFLOAT         float\n    #define portDOUBLE        double\n    #define portLONG          long\n    #define portSHORT         short\n    #define portSTACK_TYPE    uint32_t\n    #define portBASE_TYPE     long\n\n    typedef portSTACK_TYPE   StackType_t;\n    typedef long             BaseType_t;\n    typedef unsigned long    UBaseType_t;\n\n    #if ( configUSE_16_BIT_TICKS == 1 )\n        typedef uint16_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffff\n    #else\n        typedef uint32_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL\n\n/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\n * not need to be guarded with a critical section. */\n        #define portTICK_TYPE_IS_ATOMIC    1\n    #endif\n/*-----------------------------------------------------------*/\n\n/**\n * Architecture specifics.\n */\n    #define portSTACK_GROWTH                   ( -1 )\n    #define portTICK_PERIOD_MS                 ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\n    #define portBYTE_ALIGNMENT                 8\n    #define portNOP()\n    #define portINLINE                         __inline\n    #ifndef portFORCE_INLINE\n        #define portFORCE_INLINE               inline __attribute__( ( always_inline ) )\n    #endif\n    #define portHAS_STACK_OVERFLOW_CHECKING    1\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Extern declarations.\n */\n    extern BaseType_t xPortIsInsideInterrupt( void );\n\n    extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;\n\n    extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;\n    extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;\n\n    extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\n    extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\n\n    #if ( configENABLE_TRUSTZONE == 1 )\n        extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */\n        extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;\n    #endif /* configENABLE_TRUSTZONE */\n\n    #if ( configENABLE_MPU == 1 )\n        extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;\n        extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;\n    #endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\n/**\n * @brief MPU specific constants.\n */\n    #if ( configENABLE_MPU == 1 )\n        #define portUSING_MPU_WRAPPERS    1\n        #define portPRIVILEGE_BIT         ( 0x80000000UL )\n    #else\n        #define portPRIVILEGE_BIT         ( 0x0UL )\n    #endif /* configENABLE_MPU */\n\n/* MPU settings that can be overriden in FreeRTOSConfig.h. */\n#ifndef configTOTAL_MPU_REGIONS\n    /* Define to 8 for backward compatibility. */\n    #define configTOTAL_MPU_REGIONS       ( 8UL )\n#endif\n\n/* MPU regions. */\n    #define portPRIVILEGED_FLASH_REGION                   ( 0UL )\n    #define portUNPRIVILEGED_FLASH_REGION                 ( 1UL )\n    #define portUNPRIVILEGED_SYSCALLS_REGION              ( 2UL )\n    #define portPRIVILEGED_RAM_REGION                     ( 3UL )\n    #define portSTACK_REGION                              ( 4UL )\n    #define portFIRST_CONFIGURABLE_REGION                 ( 5UL )\n    #define portLAST_CONFIGURABLE_REGION                  ( configTOTAL_MPU_REGIONS - 1UL )\n    #define portNUM_CONFIGURABLE_REGIONS                  ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )\n    #define portTOTAL_NUM_REGIONS                         ( portNUM_CONFIGURABLE_REGIONS + 1 )   /* Plus one to make space for the stack region. */\n\n/* Device memory attributes used in MPU_MAIR registers.\n *\n * 8-bit values encoded as follows:\n *  Bit[7:4] - 0000 - Device Memory\n *  Bit[3:2] - 00 --> Device-nGnRnE\n *\t\t\t\t01 --> Device-nGnRE\n *\t\t\t\t10 --> Device-nGRE\n *\t\t\t\t11 --> Device-GRE\n *  Bit[1:0] - 00, Reserved.\n */\n    #define portMPU_DEVICE_MEMORY_nGnRnE                  ( 0x00 )   /* 0000 0000 */\n    #define portMPU_DEVICE_MEMORY_nGnRE                   ( 0x04 )   /* 0000 0100 */\n    #define portMPU_DEVICE_MEMORY_nGRE                    ( 0x08 )   /* 0000 1000 */\n    #define portMPU_DEVICE_MEMORY_GRE                     ( 0x0C )   /* 0000 1100 */\n\n/* Normal memory attributes used in MPU_MAIR registers. */\n    #define portMPU_NORMAL_MEMORY_NON_CACHEABLE           ( 0x44 )   /* Non-cacheable. */\n    #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE    ( 0xFF )   /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */\n\n/* Attributes used in MPU_RBAR registers. */\n    #define portMPU_REGION_NON_SHAREABLE                  ( 0UL << 3UL )\n    #define portMPU_REGION_INNER_SHAREABLE                ( 1UL << 3UL )\n    #define portMPU_REGION_OUTER_SHAREABLE                ( 2UL << 3UL )\n\n    #define portMPU_REGION_PRIVILEGED_READ_WRITE          ( 0UL << 1UL )\n    #define portMPU_REGION_READ_WRITE                     ( 1UL << 1UL )\n    #define portMPU_REGION_PRIVILEGED_READ_ONLY           ( 2UL << 1UL )\n    #define portMPU_REGION_READ_ONLY                      ( 3UL << 1UL )\n\n    #define portMPU_REGION_EXECUTE_NEVER                  ( 1UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Settings to define an MPU region.\n */\n    typedef struct MPURegionSettings\n    {\n        uint32_t ulRBAR; /**< RBAR for the region. */\n        uint32_t ulRLAR; /**< RLAR for the region. */\n    } MPURegionSettings_t;\n\n/**\n * @brief MPU settings as stored in the TCB.\n */\n    typedef struct MPU_SETTINGS\n    {\n        uint32_t ulMAIR0;                                              /**< MAIR0 for the task containing attributes for all the 4 per task regions. */\n        MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */\n    } xMPU_SETTINGS;\n/*-----------------------------------------------------------*/\n\n/**\n * @brief SVC numbers.\n */\n    #define portSVC_ALLOCATE_SECURE_CONTEXT    0\n    #define portSVC_FREE_SECURE_CONTEXT        1\n    #define portSVC_START_SCHEDULER            2\n    #define portSVC_RAISE_PRIVILEGE            3\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Scheduler utilities.\n */\n    #define portYIELD()                                 vPortYield()\n    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )\n    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )\n    #define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )\n    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Critical section management.\n */\n    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulSetInterruptMask()\n    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vClearInterruptMask( x )\n    #define portENTER_CRITICAL()                      vPortEnterCritical()\n    #define portEXIT_CRITICAL()                       vPortExitCritical()\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Tickless idle/low power functionality.\n */\n    #ifndef portSUPPRESS_TICKS_AND_SLEEP\n        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );\n        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )\n    #endif\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Task function macros as described on the FreeRTOS.org WEB site.\n */\n    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )\n    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )\n/*-----------------------------------------------------------*/\n\n    #if ( configENABLE_TRUSTZONE == 1 )\n\n/**\n * @brief Allocate a secure context for the task.\n *\n * Tasks are not created with a secure context. Any task that is going to call\n * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a\n * secure context before it calls any secure function.\n *\n * @param[in] ulSecureStackSize The size of the secure stack to be allocated.\n */\n        #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )\n\n/**\n * @brief Called when a task is deleted to delete the task's secure context,\n * if it has one.\n *\n * @param[in] pxTCB The TCB of the task being deleted.\n */\n        #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )\n    #endif /* configENABLE_TRUSTZONE */\n/*-----------------------------------------------------------*/\n\n    #if ( configENABLE_MPU == 1 )\n\n/**\n * @brief Checks whether or not the processor is privileged.\n *\n * @return 1 if the processor is already privileged, 0 otherwise.\n */\n        #define portIS_PRIVILEGED()      xIsPrivileged()\n\n/**\n * @brief Raise an SVC request to raise privilege.\n *\n * The SVC handler checks that the SVC was raised from a system call and only\n * then it raises the privilege. If this is called from any other place,\n * the privilege is not raised.\n */\n        #define portRAISE_PRIVILEGE()    __asm volatile ( \"svc %0 \\n\" ::\"i\" ( portSVC_RAISE_PRIVILEGE ) : \"memory\" );\n\n/**\n * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\n * register.\n */\n        #define portRESET_PRIVILEGE()    vResetPrivilege()\n    #else\n        #define portIS_PRIVILEGED()\n        #define portRAISE_PRIVILEGE()\n        #define portRESET_PRIVILEGE()\n    #endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Barriers.\n */\n    #define portMEMORY_BARRIER()    __asm volatile ( \"\" ::: \"memory\" )\n/*-----------------------------------------------------------*/\n\n    #ifdef __cplusplus\n        }\n    #endif\n\n#endif /* PORTMACROCOMMON_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM7/ReadMe.txt",
    "content": "There are two options for running FreeRTOS on ARM Cortex-M7 microcontrollers.\nThe best option depends on the revision of the ARM Cortex-M7 core in use.  The\nrevision is specified by an 'r' number, and a 'p' number, so will look something\nlike 'r0p1'.  Check the documentation for the microcontroller in use to find the \nrevision of the Cortex-M7 core used in that microcontroller.  If in doubt, use \nthe FreeRTOS port provided specifically for r0p1 revisions, as that can be used\nwith all core revisions.\n\nThe first option is to use the ARM Cortex-M4F port, and the second option is to\nuse the Cortex-M7 r0p1 port - the latter containing a minor errata workaround.\n\nIf the revision of the ARM Cortex-M7 core is not r0p1 then either option can be\nused, but it is recommended to use the FreeRTOS ARM Cortex-M4F port located in \nthe /FreeRTOS/Source/portable/GCC/ARM_CM4F directory.\n\nIf the revision of the ARM Cortex-M7 core is r0p1 then use the FreeRTOS ARM\nCortex-M7 r0p1 port located in the /FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1\ndirectory."
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM7/r0p1/port.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/*-----------------------------------------------------------\n* Implementation of functions defined in portable.h for the ARM CM7 port.\n*----------------------------------------------------------*/\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n#ifndef __VFP_FP__\n    #error This port can only be used when the project options are configured to enable hardware floating point support.\n#endif\n\n/* Constants required to manipulate the core.  Registers first... */\n#define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )\n#define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )\n#define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )\n#define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )\n/* ...then bits in the registers. */\n#define portNVIC_SYSTICK_CLK_BIT              ( 1UL << 2UL )\n#define portNVIC_SYSTICK_INT_BIT              ( 1UL << 1UL )\n#define portNVIC_SYSTICK_ENABLE_BIT           ( 1UL << 0UL )\n#define portNVIC_SYSTICK_COUNT_FLAG_BIT       ( 1UL << 16UL )\n#define portNVIC_PENDSVCLEAR_BIT              ( 1UL << 27UL )\n#define portNVIC_PEND_SYSTICK_SET_BIT         ( 1UL << 26UL )\n#define portNVIC_PEND_SYSTICK_CLEAR_BIT       ( 1UL << 25UL )\n\n#define portNVIC_PENDSV_PRI                   ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\n#define portNVIC_SYSTICK_PRI                  ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\n\n/* Constants required to check the validity of an interrupt priority. */\n#define portFIRST_USER_INTERRUPT_NUMBER       ( 16 )\n#define portNVIC_IP_REGISTERS_OFFSET_16       ( 0xE000E3F0 )\n#define portAIRCR_REG                         ( *( ( volatile uint32_t * ) 0xE000ED0C ) )\n#define portMAX_8_BIT_VALUE                   ( ( uint8_t ) 0xff )\n#define portTOP_BIT_OF_BYTE                   ( ( uint8_t ) 0x80 )\n#define portMAX_PRIGROUP_BITS                 ( ( uint8_t ) 7 )\n#define portPRIORITY_GROUP_MASK               ( 0x07UL << 8UL )\n#define portPRIGROUP_SHIFT                    ( 8UL )\n\n/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */\n#define portVECTACTIVE_MASK                   ( 0xFFUL )\n\n/* Constants required to manipulate the VFP. */\n#define portFPCCR                             ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */\n#define portASPEN_AND_LSPEN_BITS              ( 0x3UL << 30UL )\n\n/* Constants required to set up the initial stack. */\n#define portINITIAL_XPSR                      ( 0x01000000 )\n#define portINITIAL_EXC_RETURN                ( 0xfffffffd )\n\n/* The systick is a 24-bit counter. */\n#define portMAX_24_BIT_NUMBER                 ( 0xffffffUL )\n\n/* For strict compliance with the Cortex-M spec the task start address should\n * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */\n#define portSTART_ADDRESS_MASK                ( ( StackType_t ) 0xfffffffeUL )\n\n/* A fiddle factor to estimate the number of SysTick counts that would have\n * occurred while the SysTick counter is stopped during tickless idle\n * calculations. */\n#define portMISSED_COUNTS_FACTOR              ( 94UL )\n\n/* Let the user override the default SysTick clock rate.  If defined by the\n * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the\n * configuration register. */\n#ifndef configSYSTICK_CLOCK_HZ\n    #define configSYSTICK_CLOCK_HZ             ( configCPU_CLOCK_HZ )\n    /* Ensure the SysTick is clocked at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( portNVIC_SYSTICK_CLK_BIT )\n#else\n    /* Select the option to clock SysTick not at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( 0 )\n#endif\n\n/* Let the user override the pre-loading of the initial LR with the address of\n * prvTaskExitError() in case it messes up unwinding of the stack in the\n * debugger. */\n#ifdef configTASK_RETURN_ADDRESS\n    #define portTASK_RETURN_ADDRESS    configTASK_RETURN_ADDRESS\n#else\n    #define portTASK_RETURN_ADDRESS    prvTaskExitError\n#endif\n\n/*\n * Setup the timer to generate the tick interrupts.  The implementation in this\n * file is weak to allow application writers to change the timer used to\n * generate the tick interrupt.\n */\nvoid vPortSetupTimerInterrupt( void );\n\n/*\n * Exception handlers.\n */\nvoid xPortPendSVHandler( void ) __attribute__( ( naked ) );\nvoid xPortSysTickHandler( void );\nvoid vPortSVCHandler( void ) __attribute__( ( naked ) );\n\n/*\n * Start first task is a separate function so it can be tested in isolation.\n */\nstatic void prvPortStartFirstTask( void ) __attribute__( ( naked ) );\n\n/*\n * Function to enable the VFP.\n */\nstatic void vPortEnableVFP( void ) __attribute__( ( naked ) );\n\n/*\n * Used to catch tasks that attempt to return from their implementing function.\n */\nstatic void prvTaskExitError( void );\n\n/*-----------------------------------------------------------*/\n\n/* Each task maintains its own interrupt status in the critical nesting\n * variable. */\nstatic UBaseType_t uxCriticalNesting = 0xaaaaaaaa;\n\n/*\n * The number of SysTick increments that make up one tick period.\n */\n#if ( configUSE_TICKLESS_IDLE == 1 )\n    static uint32_t ulTimerCountsForOneTick = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n\n/*\n * The maximum number of tick periods that can be suppressed is limited by the\n * 24 bit resolution of the SysTick timer.\n */\n#if ( configUSE_TICKLESS_IDLE == 1 )\n    static uint32_t xMaximumPossibleSuppressedTicks = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n\n/*\n * Compensate for the CPU cycles that pass while the SysTick is stopped (low\n * power functionality only.\n */\n#if ( configUSE_TICKLESS_IDLE == 1 )\n    static uint32_t ulStoppedTimerCompensation = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n\n/*\n * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure\n * FreeRTOS API functions are not called from interrupts that have been assigned\n * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.\n */\n#if ( configASSERT_DEFINED == 1 )\n    static uint8_t ucMaxSysCallPriority = 0;\n    static uint32_t ulMaxPRIGROUPValue = 0;\n    static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;\n#endif /* configASSERT_DEFINED */\n\n/*-----------------------------------------------------------*/\n\n/*\n * See header file for description.\n */\nStackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,\n                                     TaskFunction_t pxCode,\n                                     void * pvParameters )\n{\n    /* Simulate the stack frame as it would be created by a context switch\n     * interrupt. */\n\n    /* Offset added to account for the way the MCU uses the stack on entry/exit\n     * of interrupts, and to ensure alignment. */\n    pxTopOfStack--;\n\n    *pxTopOfStack = portINITIAL_XPSR;                                    /* xPSR */\n    pxTopOfStack--;\n    *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */\n    pxTopOfStack--;\n    *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;             /* LR */\n\n    /* Save code space by skipping register initialisation. */\n    pxTopOfStack -= 5;                            /* R12, R3, R2 and R1. */\n    *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\n\n    /* A save method is being used that requires each task to maintain its\n     * own exec return value. */\n    pxTopOfStack--;\n    *pxTopOfStack = portINITIAL_EXC_RETURN;\n\n    pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */\n\n    return pxTopOfStack;\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvTaskExitError( void )\n{\n    volatile uint32_t ulDummy = 0;\n\n    /* A function that implements a task must not exit or attempt to return to\n     * its caller as there is nothing to return to.  If a task wants to exit it\n     * should instead call vTaskDelete( NULL ).\n     *\n     * Artificially force an assert() to be triggered if configASSERT() is\n     * defined, then stop here so application writers can catch the error. */\n    configASSERT( uxCriticalNesting == ~0UL );\n    portDISABLE_INTERRUPTS();\n\n    while( ulDummy == 0 )\n    {\n        /* This file calls prvTaskExitError() after the scheduler has been\n         * started to remove a compiler warning about the function being defined\n         * but never called.  ulDummy is used purely to quieten other warnings\n         * about code appearing after this function is called - making ulDummy\n         * volatile makes the compiler think the function could return and\n         * therefore not output an 'unreachable code' warning for code that appears\n         * after it. */\n    }\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortSVCHandler( void )\n{\n    __asm volatile (\n        \"\tldr\tr3, pxCurrentTCBConst2\t\t\\n\"/* Restore the context. */\n        \"\tldr r1, [r3]\t\t\t\t\t\\n\"/* Use pxCurrentTCBConst to get the pxCurrentTCB address. */\n        \"\tldr r0, [r1]\t\t\t\t\t\\n\"/* The first item in pxCurrentTCB is the task top of stack. */\n        \"\tldmia r0!, {r4-r11, r14}\t\t\\n\"/* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */\n        \"\tmsr psp, r0\t\t\t\t\t\t\\n\"/* Restore the task stack pointer. */\n        \"\tisb\t\t\t\t\t\t\t\t\\n\"\n        \"\tmov r0, #0 \t\t\t\t\t\t\\n\"\n        \"\tmsr\tbasepri, r0\t\t\t\t\t\\n\"\n        \"\tbx r14\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.align 4\t\t\t\t\t\t\\n\"\n        \"pxCurrentTCBConst2: .word pxCurrentTCB\t\t\t\t\\n\"\n        );\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvPortStartFirstTask( void )\n{\n    /* Start the first task.  This also clears the bit that indicates the FPU is\n     * in use in case the FPU was used before the scheduler was started - which\n     * would otherwise result in the unnecessary leaving of space in the SVC stack\n     * for lazy saving of FPU registers. */\n    __asm volatile (\n        \" ldr r0, =0xE000ED08 \t\\n\"/* Use the NVIC offset register to locate the stack. */\n        \" ldr r0, [r0] \t\t\t\\n\"\n        \" ldr r0, [r0] \t\t\t\\n\"\n        \" msr msp, r0\t\t\t\\n\"/* Set the msp back to the start of the stack. */\n        \" mov r0, #0\t\t\t\\n\"/* Clear the bit that indicates the FPU is in use, see comment above. */\n        \" msr control, r0\t\t\\n\"\n        \" cpsie i\t\t\t\t\\n\"/* Globally enable interrupts. */\n        \" cpsie f\t\t\t\t\\n\"\n        \" dsb\t\t\t\t\t\\n\"\n        \" isb\t\t\t\t\t\\n\"\n        \" svc 0\t\t\t\t\t\\n\"/* System call to start first task. */\n        \" nop\t\t\t\t\t\\n\"\n        \" .ltorg\t\t\t\t\\n\"\n        );\n}\n/*-----------------------------------------------------------*/\n\n/*\n * See header file for description.\n */\nBaseType_t xPortStartScheduler( void )\n{\n    /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.\n     * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\n    configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );\n\n    #if ( configASSERT_DEFINED == 1 )\n    {\n        volatile uint32_t ulOriginalPriority;\n        volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\n        volatile uint8_t ucMaxPriorityValue;\n\n        /* Determine the maximum priority from which ISR safe FreeRTOS API\n         * functions can be called.  ISR safe functions are those that end in\n         * \"FromISR\".  FreeRTOS maintains separate thread and ISR API functions to\n         * ensure interrupt entry is as fast and simple as possible.\n         *\n         * Save the interrupt priority value that is about to be clobbered. */\n        ulOriginalPriority = *pucFirstUserPriorityRegister;\n\n        /* Determine the number of priority bits available.  First write to all\n         * possible bits. */\n        *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\n\n        /* Read the value back to see how many bits stuck. */\n        ucMaxPriorityValue = *pucFirstUserPriorityRegister;\n\n        /* Use the same mask on the maximum system call priority. */\n        ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;\n\n        /* Calculate the maximum acceptable priority group value for the number\n         * of bits read back. */\n        ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;\n\n        while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )\n        {\n            ulMaxPRIGROUPValue--;\n            ucMaxPriorityValue <<= ( uint8_t ) 0x01;\n        }\n\n        #ifdef __NVIC_PRIO_BITS\n        {\n            /* Check the CMSIS configuration that defines the number of\n             * priority bits matches the number of priority bits actually queried\n             * from the hardware. */\n            configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );\n        }\n        #endif\n\n        #ifdef configPRIO_BITS\n        {\n            /* Check the FreeRTOS configuration that defines the number of\n             * priority bits matches the number of priority bits actually queried\n             * from the hardware. */\n            configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );\n        }\n        #endif\n\n        /* Shift the priority group value back to its position within the AIRCR\n         * register. */\n        ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;\n        ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;\n\n        /* Restore the clobbered interrupt priority register to its original\n         * value. */\n        *pucFirstUserPriorityRegister = ulOriginalPriority;\n    }\n    #endif /* configASSERT_DEFINED */\n\n    /* Make PendSV and SysTick the lowest priority interrupts. */\n    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;\n    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;\n\n    /* Start the timer that generates the tick ISR.  Interrupts are disabled\n     * here already. */\n    vPortSetupTimerInterrupt();\n\n    /* Initialise the critical nesting count ready for the first task. */\n    uxCriticalNesting = 0;\n\n    /* Ensure the VFP is enabled - it should be anyway. */\n    vPortEnableVFP();\n\n    /* Lazy save always. */\n    *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;\n\n    /* Start the first task. */\n    prvPortStartFirstTask();\n\n    /* Should never get here as the tasks will now be executing!  Call the task\n     * exit error function to prevent compiler warnings about a static function\n     * not being called in the case that the application writer overrides this\n     * functionality by defining configTASK_RETURN_ADDRESS.  Call\n     * vTaskSwitchContext() so link time optimisation does not remove the\n     * symbol. */\n    vTaskSwitchContext();\n    prvTaskExitError();\n\n    /* Should not get here! */\n    return 0;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEndScheduler( void )\n{\n    /* Not implemented in ports where there is nothing to return to.\n     * Artificially force an assert. */\n    configASSERT( uxCriticalNesting == 1000UL );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEnterCritical( void )\n{\n    portDISABLE_INTERRUPTS();\n    uxCriticalNesting++;\n\n    /* This is not the interrupt safe version of the enter critical function so\n     * assert() if it is being called from an interrupt context.  Only API\n     * functions that end in \"FromISR\" can be used in an interrupt.  Only assert if\n     * the critical nesting count is 1 to protect against recursive calls if the\n     * assert function also uses a critical section. */\n    if( uxCriticalNesting == 1 )\n    {\n        configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );\n    }\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortExitCritical( void )\n{\n    configASSERT( uxCriticalNesting );\n    uxCriticalNesting--;\n\n    if( uxCriticalNesting == 0 )\n    {\n        portENABLE_INTERRUPTS();\n    }\n}\n/*-----------------------------------------------------------*/\n\nvoid xPortPendSVHandler( void )\n{\n    /* This is a naked function. */\n\n    __asm volatile\n    (\n        \"\tmrs r0, psp\t\t\t\t\t\t\t\\n\"\n        \"\tisb\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr\tr3, pxCurrentTCBConst\t\t\t\\n\"/* Get the location of the current TCB. */\n        \"\tldr\tr2, [r3]\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\ttst r14, #0x10\t\t\t\t\t\t\\n\"/* Is the task using the FPU context?  If so, push high vfp registers. */\n        \"\tit eq\t\t\t\t\t\t\t\t\\n\"\n        \"\tvstmdbeq r0!, {s16-s31}\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tstmdb r0!, {r4-r11, r14}\t\t\t\\n\"/* Save the core registers. */\n        \"\tstr r0, [r2]\t\t\t\t\t\t\\n\"/* Save the new top of stack into the first member of the TCB. */\n        \"\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tstmdb sp!, {r0, r3}\t\t\t\t\t\\n\"\n        \"\tmov r0, %0 \t\t\t\t\t\t\t\\n\"\n        \"\tcpsid i\t\t\t\t\t\t\t\t\\n\"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */\n        \"\tmsr basepri, r0\t\t\t\t\t\t\\n\"\n        \"\tdsb\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tisb\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tcpsie i\t\t\t\t\t\t\t\t\\n\"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */\n        \"\tbl vTaskSwitchContext\t\t\t\t\\n\"\n        \"\tmov r0, #0\t\t\t\t\t\t\t\\n\"\n        \"\tmsr basepri, r0\t\t\t\t\t\t\\n\"\n        \"\tldmia sp!, {r0, r3}\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r1, [r3]\t\t\t\t\t\t\\n\"/* The first item in pxCurrentTCB is the task top of stack. */\n        \"\tldr r0, [r1]\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldmia r0!, {r4-r11, r14}\t\t\t\\n\"/* Pop the core registers. */\n        \"\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\ttst r14, #0x10\t\t\t\t\t\t\\n\"/* Is the task using the FPU context?  If so, pop the high vfp registers too. */\n        \"\tit eq\t\t\t\t\t\t\t\t\\n\"\n        \"\tvldmiaeq r0!, {s16-s31}\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmsr psp, r0\t\t\t\t\t\t\t\\n\"\n        \"\tisb\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\\n\"\n        #ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata workaround. */\n            #if WORKAROUND_PMU_CM001 == 1\n                \"\t\t\tpush { r14 }\t\t\t\t\\n\"\n                \"\t\t\tpop { pc }\t\t\t\t\t\\n\"\n            #endif\n        #endif\n        \"\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tbx r14\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.align 4\t\t\t\t\t\t\t\\n\"\n        \"pxCurrentTCBConst: .word pxCurrentTCB\t\\n\"\n        ::\"i\" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid xPortSysTickHandler( void )\n{\n    /* The SysTick runs at the lowest interrupt priority, so when this interrupt\n     * executes all interrupts must be unmasked.  There is therefore no need to\n     * save and then restore the interrupt mask value as its value is already\n     * known. */\n    portDISABLE_INTERRUPTS();\n    {\n        /* Increment the RTOS tick. */\n        if( xTaskIncrementTick() != pdFALSE )\n        {\n            /* A context switch is required.  Context switching is performed in\n             * the PendSV interrupt.  Pend the PendSV interrupt. */\n            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\n        }\n    }\n    portENABLE_INTERRUPTS();\n}\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TICKLESS_IDLE == 1 )\n\n    __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )\n    {\n        uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;\n        TickType_t xModifiableIdleTime;\n\n        /* Make sure the SysTick reload value does not overflow the counter. */\n        if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\n        {\n            xExpectedIdleTime = xMaximumPossibleSuppressedTicks;\n        }\n\n        /* Enter a critical section but don't use the taskENTER_CRITICAL()\n         * method as that will mask interrupts that should exit sleep mode. */\n        __asm volatile ( \"cpsid i\" ::: \"memory\" );\n        __asm volatile ( \"dsb\" );\n        __asm volatile ( \"isb\" );\n\n        /* If a context switch is pending or a task is waiting for the scheduler\n         * to be unsuspended then abandon the low power entry. */\n        if( eTaskConfirmSleepModeStatus() == eAbortSleep )\n        {\n            /* Re-enable interrupts - see comments above the cpsid instruction\n             * above. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n        }\n        else\n        {\n            /* Stop the SysTick momentarily.  The time the SysTick is stopped for\n             * is accounted for as best it can be, but using the tickless mode will\n             * inevitably result in some tiny drift of the time maintained by the\n             * kernel with respect to calendar time. */\n            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );\n\n            /* Use the SysTick current-value register to determine the number of\n             * SysTick decrements remaining until the next tick interrupt.  If the\n             * current-value register is zero, then there are actually\n             * ulTimerCountsForOneTick decrements remaining, not zero, because the\n             * SysTick requests the interrupt when decrementing from 1 to 0. */\n            ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n\n            if( ulSysTickDecrementsLeft == 0 )\n            {\n                ulSysTickDecrementsLeft = ulTimerCountsForOneTick;\n            }\n\n            /* Calculate the reload value required to wait xExpectedIdleTime\n             * tick periods.  -1 is used because this code normally executes part\n             * way through the first tick period.  But if the SysTick IRQ is now\n             * pending, then clear the IRQ, suppressing the first tick, and correct\n             * the reload value to reflect that the second tick period is already\n             * underway.  The expected idle time is always at least two ticks. */\n            ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );\n\n            if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )\n            {\n                portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;\n                ulReloadValue -= ulTimerCountsForOneTick;\n            }\n\n            if( ulReloadValue > ulStoppedTimerCompensation )\n            {\n                ulReloadValue -= ulStoppedTimerCompensation;\n            }\n\n            /* Set the new reload value. */\n            portNVIC_SYSTICK_LOAD_REG = ulReloadValue;\n\n            /* Clear the SysTick count flag and set the count value back to\n             * zero. */\n            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n            /* Restart SysTick. */\n            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\n\n            /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can\n             * set its parameter to 0 to indicate that its implementation contains\n             * its own wait for interrupt or wait for event instruction, and so wfi\n             * should not be executed again.  However, the original expected idle\n             * time variable must remain unmodified, so a copy is taken. */\n            xModifiableIdleTime = xExpectedIdleTime;\n            configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\n\n            if( xModifiableIdleTime > 0 )\n            {\n                __asm volatile ( \"dsb\" ::: \"memory\" );\n                __asm volatile ( \"wfi\" );\n                __asm volatile ( \"isb\" );\n            }\n\n            configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\n\n            /* Re-enable interrupts to allow the interrupt that brought the MCU\n             * out of sleep mode to execute immediately.  See comments above\n             * the cpsid instruction above. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n            __asm volatile ( \"dsb\" );\n            __asm volatile ( \"isb\" );\n\n            /* Disable interrupts again because the clock is about to be stopped\n             * and interrupts that execute while the clock is stopped will increase\n             * any slippage between the time maintained by the RTOS and calendar\n             * time. */\n            __asm volatile ( \"cpsid i\" ::: \"memory\" );\n            __asm volatile ( \"dsb\" );\n            __asm volatile ( \"isb\" );\n\n            /* Disable the SysTick clock without reading the\n             * portNVIC_SYSTICK_CTRL_REG register to ensure the\n             * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,\n             * the time the SysTick is stopped for is accounted for as best it can\n             * be, but using the tickless mode will inevitably result in some tiny\n             * drift of the time maintained by the kernel with respect to calendar\n             * time*/\n            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );\n\n            /* Determine whether the SysTick has already counted to zero. */\n            if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n            {\n                uint32_t ulCalculatedLoadValue;\n\n                /* The tick interrupt ended the sleep (or is now pending), and\n                 * a new tick period has started.  Reset portNVIC_SYSTICK_LOAD_REG\n                 * with whatever remains of the new tick period. */\n                ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\n\n                /* Don't allow a tiny value, or values that have somehow\n                 * underflowed because the post sleep hook did something\n                 * that took too long or because the SysTick current-value register\n                 * is zero. */\n                if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )\n                {\n                    ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );\n                }\n\n                portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;\n\n                /* As the pending tick will be processed as soon as this\n                 * function exits, the tick value maintained by the tick is stepped\n                 * forward by one less than the time spent waiting. */\n                ulCompleteTickPeriods = xExpectedIdleTime - 1UL;\n            }\n            else\n            {\n                /* Something other than the tick interrupt ended the sleep. */\n\n                /* Use the SysTick current-value register to determine the\n                 * number of SysTick decrements remaining until the expected idle\n                 * time would have ended. */\n                ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n                #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )\n                {\n                    /* If the SysTick is not using the core clock, the current-\n                     * value register might still be zero here.  In that case, the\n                     * SysTick didn't load from the reload register, and there are\n                     * ulReloadValue decrements remaining in the expected idle\n                     * time, not zero. */\n                    if( ulSysTickDecrementsLeft == 0 )\n                    {\n                        ulSysTickDecrementsLeft = ulReloadValue;\n                    }\n                }\n                #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */\n\n                /* Work out how long the sleep lasted rounded to complete tick\n                 * periods (not the ulReload value which accounted for part\n                 * ticks). */\n                ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;\n\n                /* How many complete tick periods passed while the processor\n                 * was waiting? */\n                ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;\n\n                /* The reload value is set to whatever fraction of a single tick\n                 * period remains. */\n                portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;\n            }\n\n            /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,\n             * then set portNVIC_SYSTICK_LOAD_REG back to its standard value.  If\n             * the SysTick is not using the core clock, temporarily configure it to\n             * use the core clock.  This configuration forces the SysTick to load\n             * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next\n             * cycle of the other clock.  Then portNVIC_SYSTICK_LOAD_REG is ready\n             * to receive the standard value immediately. */\n            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n            portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n            #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )\n            {\n                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n            }\n            #else\n            {\n                /* The temporary usage of the core clock has served its purpose,\n                 * as described above.  Resume usage of the other clock. */\n                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\n\n                if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n                {\n                    /* The partial tick period already ended.  Be sure the SysTick\n                     * counts it only once. */\n                    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;\n                }\n\n                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n            }\n            #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */\n\n            /* Step the tick to account for any tick periods that elapsed. */\n            vTaskStepTick( ulCompleteTickPeriods );\n\n            /* Exit with interrupts enabled. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n        }\n    }\n\n#endif /* #if configUSE_TICKLESS_IDLE */\n/*-----------------------------------------------------------*/\n\n/*\n * Setup the systick timer to generate the tick interrupts at the required\n * frequency.\n */\n__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )\n{\n    /* Calculate the constants required to configure the tick interrupt. */\n    #if ( configUSE_TICKLESS_IDLE == 1 )\n    {\n        ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );\n        xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;\n        ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\n    }\n    #endif /* configUSE_TICKLESS_IDLE */\n\n    /* Stop and clear the SysTick. */\n    portNVIC_SYSTICK_CTRL_REG = 0UL;\n    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n    /* Configure SysTick to interrupt at the requested rate. */\n    portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\n    portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );\n}\n/*-----------------------------------------------------------*/\n\n/* This is a naked function. */\nstatic void vPortEnableVFP( void )\n{\n    __asm volatile\n    (\n        \"\tldr.w r0, =0xE000ED88\t\t\\n\"/* The FPU enable bits are in the CPACR. */\n        \"\tldr r1, [r0]\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\\n\"\n        \"\torr r1, r1, #( 0xf << 20 )\t\\n\"/* Enable CP10 and CP11 coprocessors, then save back. */\n        \"\tstr r1, [r0]\t\t\t\t\\n\"\n        \"\tbx r14\t\t\t\t\t\t\\n\"\n        \"\t.ltorg\t\t\t\t\t\t\\n\"\n    );\n}\n/*-----------------------------------------------------------*/\n\n#if ( configASSERT_DEFINED == 1 )\n\n    void vPortValidateInterruptPriority( void )\n    {\n        uint32_t ulCurrentInterrupt;\n        uint8_t ucCurrentPriority;\n\n        /* Obtain the number of the currently executing interrupt. */\n        __asm volatile ( \"mrs %0, ipsr\" : \"=r\" ( ulCurrentInterrupt )::\"memory\" );\n\n        /* Is the interrupt number a user defined interrupt? */\n        if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )\n        {\n            /* Look up the interrupt's priority. */\n            ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];\n\n            /* The following assertion will fail if a service routine (ISR) for\n             * an interrupt that has been assigned a priority above\n             * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\n             * function.  ISR safe FreeRTOS API functions must *only* be called\n             * from interrupts that have been assigned a priority at or below\n             * configMAX_SYSCALL_INTERRUPT_PRIORITY.\n             *\n             * Numerically low interrupt priority numbers represent logically high\n             * interrupt priorities, therefore the priority of the interrupt must\n             * be set to a value equal to or numerically *higher* than\n             * configMAX_SYSCALL_INTERRUPT_PRIORITY.\n             *\n             * Interrupts that\tuse the FreeRTOS API must not be left at their\n             * default priority of\tzero as that is the highest possible priority,\n             * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,\n             * and\ttherefore also guaranteed to be invalid.\n             *\n             * FreeRTOS maintains separate thread and ISR API functions to ensure\n             * interrupt entry is as fast and simple as possible.\n             *\n             * The following links provide detailed information:\n             * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html\n             * https://www.FreeRTOS.org/FAQHelp.html */\n            configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );\n        }\n\n        /* Priority grouping:  The interrupt controller (NVIC) allows the bits\n         * that define each interrupt's priority to be split between bits that\n         * define the interrupt's pre-emption priority bits and bits that define\n         * the interrupt's sub-priority.  For simplicity all bits must be defined\n         * to be pre-emption priority bits.  The following assertion will fail if\n         * this is not the case (if some bits represent a sub-priority).\n         *\n         * If the application only uses CMSIS libraries for interrupt\n         * configuration then the correct setting can be achieved on all Cortex-M\n         * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the\n         * scheduler.  Note however that some vendor specific peripheral libraries\n         * assume a non-zero priority group setting, in which cases using a value\n         * of zero will result in unpredictable behaviour. */\n        configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );\n    }\n\n#endif /* configASSERT_DEFINED */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM7/r0p1/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n\n#ifndef PORTMACRO_H\n    #define PORTMACRO_H\n\n    #ifdef __cplusplus\n        extern \"C\" {\n    #endif\n\n/*-----------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the\n * given hardware and compiler.\n *\n * These settings should not be altered.\n *-----------------------------------------------------------\n */\n\n/* Type definitions. */\n    #define portCHAR          char\n    #define portFLOAT         float\n    #define portDOUBLE        double\n    #define portLONG          long\n    #define portSHORT         short\n    #define portSTACK_TYPE    uint32_t\n    #define portBASE_TYPE     long\n\n    typedef portSTACK_TYPE   StackType_t;\n    typedef long             BaseType_t;\n    typedef unsigned long    UBaseType_t;\n\n    #if ( configUSE_16_BIT_TICKS == 1 )\n        typedef uint16_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffff\n    #else\n        typedef uint32_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL\n\n/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\n * not need to be guarded with a critical section. */\n        #define portTICK_TYPE_IS_ATOMIC    1\n    #endif\n/*-----------------------------------------------------------*/\n\n/* Architecture specifics. */\n    #define portSTACK_GROWTH      ( -1 )\n    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\n    #define portBYTE_ALIGNMENT    8\n    #define portDONT_DISCARD      __attribute__( ( used ) )\n/*-----------------------------------------------------------*/\n\n/* Scheduler utilities. */\n    #define portYIELD()                                 \\\n    {                                                   \\\n        /* Set a PendSV to request a context switch. */ \\\n        portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \\\n                                                        \\\n        /* Barriers are normally not required but do ensure the code is completely \\\n         * within the specified behaviour for the architecture. */ \\\n        __asm volatile ( \"dsb\" ::: \"memory\" );                     \\\n        __asm volatile ( \"isb\" );                                  \\\n    }\n\n    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )\n    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )\n    #define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 )\n    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )\n/*-----------------------------------------------------------*/\n\n/* Critical section management. */\n    extern void vPortEnterCritical( void );\n    extern void vPortExitCritical( void );\n    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulPortRaiseBASEPRI()\n    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vPortSetBASEPRI( x )\n    #define portDISABLE_INTERRUPTS()                  vPortRaiseBASEPRI()\n    #define portENABLE_INTERRUPTS()                   vPortSetBASEPRI( 0 )\n    #define portENTER_CRITICAL()                      vPortEnterCritical()\n    #define portEXIT_CRITICAL()                       vPortExitCritical()\n\n/*-----------------------------------------------------------*/\n\n/* Task function macros as described on the FreeRTOS.org WEB site.  These are\n * not necessary for to use this port.  They are defined so the common demo files\n * (which build with all the ports) will build. */\n    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )\n    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )\n/*-----------------------------------------------------------*/\n\n/* Tickless idle/low power functionality. */\n    #ifndef portSUPPRESS_TICKS_AND_SLEEP\n        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );\n        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )\n    #endif\n/*-----------------------------------------------------------*/\n\n/* Architecture specific optimisations. */\n    #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION\n        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1\n    #endif\n\n    #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1\n\n/* Generic helper function. */\n        __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )\n        {\n            uint8_t ucReturn;\n\n            __asm volatile ( \"clz %0, %1\" : \"=r\" ( ucReturn ) : \"r\" ( ulBitmap ) : \"memory\" );\n\n            return ucReturn;\n        }\n\n/* Check the configuration. */\n        #if ( configMAX_PRIORITIES > 32 )\n            #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.\n        #endif\n\n/* Store/clear the ready priorities in a bit map. */\n        #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )\n        #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )\n\n/*-----------------------------------------------------------*/\n\n        #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )\n\n    #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */\n\n/*-----------------------------------------------------------*/\n\n    #ifdef configASSERT\n        void vPortValidateInterruptPriority( void );\n        #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()\n    #endif\n\n/* portNOP() is not required by this port. */\n    #define portNOP()\n\n    #define portINLINE              __inline\n\n    #ifndef portFORCE_INLINE\n        #define portFORCE_INLINE    inline __attribute__( ( always_inline ) )\n    #endif\n\n    portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )\n    {\n        uint32_t ulCurrentInterrupt;\n        BaseType_t xReturn;\n\n        /* Obtain the number of the currently executing interrupt. */\n        __asm volatile ( \"mrs %0, ipsr\" : \"=r\" ( ulCurrentInterrupt )::\"memory\" );\n\n        if( ulCurrentInterrupt == 0 )\n        {\n            xReturn = pdFALSE;\n        }\n        else\n        {\n            xReturn = pdTRUE;\n        }\n\n        return xReturn;\n    }\n\n/*-----------------------------------------------------------*/\n\n    portFORCE_INLINE static void vPortRaiseBASEPRI( void )\n    {\n        uint32_t ulNewBASEPRI;\n\n        __asm volatile\n        (\n            \"\tmov %0, %1\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\\\n            \"\tcpsid i\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\\\n            \"\tmsr basepri, %0\t\t\t\t\t\t\t\t\t\t\t\\n\"\\\n            \"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\\\n            \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\\\n            \"\tcpsie i\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\\\n            : \"=r\" ( ulNewBASEPRI ) : \"i\" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : \"memory\"\n        );\n    }\n\n/*-----------------------------------------------------------*/\n\n    portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )\n    {\n        uint32_t ulOriginalBASEPRI, ulNewBASEPRI;\n\n        __asm volatile\n        (\n            \"\tmrs %0, basepri\t\t\t\t\t\t\t\t\t\t\t\\n\"\\\n            \"\tmov %1, %2\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\\\n            \"\tcpsid i\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\\\n            \"\tmsr basepri, %1\t\t\t\t\t\t\t\t\t\t\t\\n\"\\\n            \"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\\\n            \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\\\n            \"\tcpsie i\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\\\n            : \"=r\" ( ulOriginalBASEPRI ), \"=r\" ( ulNewBASEPRI ) : \"i\" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : \"memory\"\n        );\n\n        /* This return will not be reached but is necessary to prevent compiler\n         * warnings. */\n        return ulOriginalBASEPRI;\n    }\n/*-----------------------------------------------------------*/\n\n    portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )\n    {\n        __asm volatile\n        (\n            \"\tmsr basepri, %0\t\"::\"r\" ( ulNewMaskValue ) : \"memory\"\n        );\n    }\n/*-----------------------------------------------------------*/\n\n    #define portMEMORY_BARRIER()    __asm volatile ( \"\" ::: \"memory\" )\n\n    #ifdef __cplusplus\n        }\n    #endif\n\n#endif /* PORTMACRO_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM85/non_secure/port.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\n * all the API functions to use the MPU wrappers. That should only be done when\n * task.h is included from an application file. */\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n/* MPU wrappers includes. */\n#include \"mpu_wrappers.h\"\n\n/* Portasm includes. */\n#include \"portasm.h\"\n\n#if ( configENABLE_TRUSTZONE == 1 )\n    /* Secure components includes. */\n    #include \"secure_context.h\"\n    #include \"secure_init.h\"\n#endif /* configENABLE_TRUSTZONE */\n\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/**\n * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only\n * i.e. the processor boots as secure and never jumps to the non-secure side.\n * The Trust Zone support in the port must be disabled in order to run FreeRTOS\n * on the secure side. The following are the valid configuration seetings:\n *\n * 1. Run FreeRTOS on the Secure Side:\n *    configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0\n *\n * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:\n *    configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1\n *\n * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:\n *    configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0\n */\n#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )\n    #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.\n#endif\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the NVIC.\n */\n#define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )\n#define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )\n#define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )\n#define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )\n#define portNVIC_SYSTICK_ENABLE_BIT           ( 1UL << 0UL )\n#define portNVIC_SYSTICK_INT_BIT              ( 1UL << 1UL )\n#define portNVIC_SYSTICK_CLK_BIT              ( 1UL << 2UL )\n#define portNVIC_SYSTICK_COUNT_FLAG_BIT       ( 1UL << 16UL )\n#define portNVIC_PEND_SYSTICK_CLEAR_BIT       ( 1UL << 25UL )\n#define portNVIC_PEND_SYSTICK_SET_BIT         ( 1UL << 26UL )\n#define portMIN_INTERRUPT_PRIORITY            ( 255UL )\n#define portNVIC_PENDSV_PRI                   ( portMIN_INTERRUPT_PRIORITY << 16UL )\n#define portNVIC_SYSTICK_PRI                  ( portMIN_INTERRUPT_PRIORITY << 24UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the SCB.\n */\n#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( volatile uint32_t * ) 0xe000ed24 )\n#define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the FPU.\n */\n#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 )              /* Coprocessor Access Control Register. */\n#define portCPACR_CP10_VALUE    ( 3UL )\n#define portCPACR_CP11_VALUE    portCPACR_CP10_VALUE\n#define portCPACR_CP10_POS      ( 20UL )\n#define portCPACR_CP11_POS      ( 22UL )\n\n#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 )              /* Floating Point Context Control Register. */\n#define portFPCCR_ASPEN_POS     ( 31UL )\n#define portFPCCR_ASPEN_MASK    ( 1UL << portFPCCR_ASPEN_POS )\n#define portFPCCR_LSPEN_POS     ( 30UL )\n#define portFPCCR_LSPEN_MASK    ( 1UL << portFPCCR_LSPEN_POS )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the MPU.\n */\n#define portMPU_TYPE_REG                      ( *( ( volatile uint32_t * ) 0xe000ed90 ) )\n#define portMPU_CTRL_REG                      ( *( ( volatile uint32_t * ) 0xe000ed94 ) )\n#define portMPU_RNR_REG                       ( *( ( volatile uint32_t * ) 0xe000ed98 ) )\n\n#define portMPU_RBAR_REG                      ( *( ( volatile uint32_t * ) 0xe000ed9c ) )\n#define portMPU_RLAR_REG                      ( *( ( volatile uint32_t * ) 0xe000eda0 ) )\n\n#define portMPU_RBAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda4 ) )\n#define portMPU_RLAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda8 ) )\n\n#define portMPU_RBAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edac ) )\n#define portMPU_RLAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edb0 ) )\n\n#define portMPU_RBAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb4 ) )\n#define portMPU_RLAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb8 ) )\n\n#define portMPU_MAIR0_REG                     ( *( ( volatile uint32_t * ) 0xe000edc0 ) )\n#define portMPU_MAIR1_REG                     ( *( ( volatile uint32_t * ) 0xe000edc4 ) )\n\n#define portMPU_RBAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */\n#define portMPU_RLAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */\n\n#define portMPU_MAIR_ATTR0_POS                ( 0UL )\n#define portMPU_MAIR_ATTR0_MASK               ( 0x000000ff )\n\n#define portMPU_MAIR_ATTR1_POS                ( 8UL )\n#define portMPU_MAIR_ATTR1_MASK               ( 0x0000ff00 )\n\n#define portMPU_MAIR_ATTR2_POS                ( 16UL )\n#define portMPU_MAIR_ATTR2_MASK               ( 0x00ff0000 )\n\n#define portMPU_MAIR_ATTR3_POS                ( 24UL )\n#define portMPU_MAIR_ATTR3_MASK               ( 0xff000000 )\n\n#define portMPU_MAIR_ATTR4_POS                ( 0UL )\n#define portMPU_MAIR_ATTR4_MASK               ( 0x000000ff )\n\n#define portMPU_MAIR_ATTR5_POS                ( 8UL )\n#define portMPU_MAIR_ATTR5_MASK               ( 0x0000ff00 )\n\n#define portMPU_MAIR_ATTR6_POS                ( 16UL )\n#define portMPU_MAIR_ATTR6_MASK               ( 0x00ff0000 )\n\n#define portMPU_MAIR_ATTR7_POS                ( 24UL )\n#define portMPU_MAIR_ATTR7_MASK               ( 0xff000000 )\n\n#define portMPU_RLAR_ATTR_INDEX0              ( 0UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX1              ( 1UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX2              ( 2UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX3              ( 3UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX4              ( 4UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX5              ( 5UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX6              ( 6UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX7              ( 7UL << 1UL )\n\n#define portMPU_RLAR_REGION_ENABLE            ( 1UL )\n\n/* Enable privileged access to unmapped region. */\n#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )\n\n/* Enable MPU. */\n#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )\n\n/* Expected value of the portMPU_TYPE register. */\n#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief The maximum 24-bit number.\n *\n * It is needed because the systick is a 24-bit counter.\n */\n#define portMAX_24_BIT_NUMBER       ( 0xffffffUL )\n\n/**\n * @brief A fiddle factor to estimate the number of SysTick counts that would\n * have occurred while the SysTick counter is stopped during tickless idle\n * calculations.\n */\n#define portMISSED_COUNTS_FACTOR    ( 94UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to set up the initial stack.\n */\n#define portINITIAL_XPSR    ( 0x01000000 )\n\n#if ( configRUN_FREERTOS_SECURE_ONLY == 1 )\n\n/**\n * @brief Initial EXC_RETURN value.\n *\n *     FF         FF         FF         FD\n * 1111 1111  1111 1111  1111 1111  1111 1101\n *\n * Bit[6] - 1 --> The exception was taken from the Secure state.\n * Bit[5] - 1 --> Do not skip stacking of additional state context.\n * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\n * Bit[3] - 1 --> Return to the Thread mode.\n * Bit[2] - 1 --> Restore registers from the process stack.\n * Bit[1] - 0 --> Reserved, 0.\n * Bit[0] - 1 --> The exception was taken to the Secure state.\n */\n    #define portINITIAL_EXC_RETURN    ( 0xfffffffd )\n#else\n\n/**\n * @brief Initial EXC_RETURN value.\n *\n *     FF         FF         FF         BC\n * 1111 1111  1111 1111  1111 1111  1011 1100\n *\n * Bit[6] - 0 --> The exception was taken from the Non-Secure state.\n * Bit[5] - 1 --> Do not skip stacking of additional state context.\n * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\n * Bit[3] - 1 --> Return to the Thread mode.\n * Bit[2] - 1 --> Restore registers from the process stack.\n * Bit[1] - 0 --> Reserved, 0.\n * Bit[0] - 0 --> The exception was taken to the Non-Secure state.\n */\n    #define portINITIAL_EXC_RETURN    ( 0xffffffbc )\n#endif /* configRUN_FREERTOS_SECURE_ONLY */\n\n/**\n * @brief CONTROL register privileged bit mask.\n *\n * Bit[0] in CONTROL register tells the privilege:\n *  Bit[0] = 0 ==> The task is privileged.\n *  Bit[0] = 1 ==> The task is not privileged.\n */\n#define portCONTROL_PRIVILEGED_MASK         ( 1UL << 0UL )\n\n/**\n * @brief Initial CONTROL register values.\n */\n#define portINITIAL_CONTROL_UNPRIVILEGED    ( 0x3 )\n#define portINITIAL_CONTROL_PRIVILEGED      ( 0x2 )\n\n/**\n * @brief Let the user override the default SysTick clock rate.  If defined by the\n * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the\n * configuration register.\n */\n#ifndef configSYSTICK_CLOCK_HZ\n    #define configSYSTICK_CLOCK_HZ             ( configCPU_CLOCK_HZ )\n    /* Ensure the SysTick is clocked at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( portNVIC_SYSTICK_CLK_BIT )\n#else\n    /* Select the option to clock SysTick not at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( 0 )\n#endif\n\n/**\n * @brief Let the user override the pre-loading of the initial LR with the\n * address of prvTaskExitError() in case it messes up unwinding of the stack\n * in the debugger.\n */\n#ifdef configTASK_RETURN_ADDRESS\n    #define portTASK_RETURN_ADDRESS    configTASK_RETURN_ADDRESS\n#else\n    #define portTASK_RETURN_ADDRESS    prvTaskExitError\n#endif\n\n/**\n * @brief If portPRELOAD_REGISTERS then registers will be given an initial value\n * when a task is created. This helps in debugging at the cost of code size.\n */\n#define portPRELOAD_REGISTERS    1\n\n/**\n * @brief A task is created without a secure context, and must call\n * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes\n * any secure calls.\n */\n#define portNO_SECURE_CONTEXT    0\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Used to catch tasks that attempt to return from their implementing\n * function.\n */\nstatic void prvTaskExitError( void );\n\n#if ( configENABLE_MPU == 1 )\n\n/**\n * @brief Setup the Memory Protection Unit (MPU).\n */\n    static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\n#endif /* configENABLE_MPU */\n\n#if ( configENABLE_FPU == 1 )\n\n/**\n * @brief Setup the Floating Point Unit (FPU).\n */\n    static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;\n#endif /* configENABLE_FPU */\n\n/**\n * @brief Setup the timer to generate the tick interrupts.\n *\n * The implementation in this file is weak to allow application writers to\n * change the timer used to generate the tick interrupt.\n */\nvoid vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Checks whether the current execution context is interrupt.\n *\n * @return pdTRUE if the current execution context is interrupt, pdFALSE\n * otherwise.\n */\nBaseType_t xPortIsInsideInterrupt( void );\n\n/**\n * @brief Yield the processor.\n */\nvoid vPortYield( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Enter critical section.\n */\nvoid vPortEnterCritical( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Exit from critical section.\n */\nvoid vPortExitCritical( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief SysTick handler.\n */\nvoid SysTick_Handler( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief C part of SVC handler.\n */\nportDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION;\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Each task maintains its own interrupt status in the critical nesting\n * variable.\n */\nPRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;\n\n#if ( configENABLE_TRUSTZONE == 1 )\n\n/**\n * @brief Saved as part of the task context to indicate which context the\n * task is using on the secure side.\n */\n    PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;\n#endif /* configENABLE_TRUSTZONE */\n\n#if ( configUSE_TICKLESS_IDLE == 1 )\n\n/**\n * @brief The number of SysTick increments that make up one tick period.\n */\n    PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0;\n\n/**\n * @brief The maximum number of tick periods that can be suppressed is\n * limited by the 24 bit resolution of the SysTick timer.\n */\n    PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0;\n\n/**\n * @brief Compensate for the CPU cycles that pass while the SysTick is\n * stopped (low power functionality only).\n */\n    PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TICKLESS_IDLE == 1 )\n    __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )\n    {\n        uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;\n        TickType_t xModifiableIdleTime;\n\n        /* Make sure the SysTick reload value does not overflow the counter. */\n        if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\n        {\n            xExpectedIdleTime = xMaximumPossibleSuppressedTicks;\n        }\n\n        /* Enter a critical section but don't use the taskENTER_CRITICAL()\n         * method as that will mask interrupts that should exit sleep mode. */\n        __asm volatile ( \"cpsid i\" ::: \"memory\" );\n        __asm volatile ( \"dsb\" );\n        __asm volatile ( \"isb\" );\n\n        /* If a context switch is pending or a task is waiting for the scheduler\n         * to be unsuspended then abandon the low power entry. */\n        if( eTaskConfirmSleepModeStatus() == eAbortSleep )\n        {\n            /* Re-enable interrupts - see comments above the cpsid instruction\n             * above. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n        }\n        else\n        {\n            /* Stop the SysTick momentarily.  The time the SysTick is stopped for\n             * is accounted for as best it can be, but using the tickless mode will\n             * inevitably result in some tiny drift of the time maintained by the\n             * kernel with respect to calendar time. */\n            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );\n\n            /* Use the SysTick current-value register to determine the number of\n             * SysTick decrements remaining until the next tick interrupt.  If the\n             * current-value register is zero, then there are actually\n             * ulTimerCountsForOneTick decrements remaining, not zero, because the\n             * SysTick requests the interrupt when decrementing from 1 to 0. */\n            ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n\n            if( ulSysTickDecrementsLeft == 0 )\n            {\n                ulSysTickDecrementsLeft = ulTimerCountsForOneTick;\n            }\n\n            /* Calculate the reload value required to wait xExpectedIdleTime\n             * tick periods.  -1 is used because this code normally executes part\n             * way through the first tick period.  But if the SysTick IRQ is now\n             * pending, then clear the IRQ, suppressing the first tick, and correct\n             * the reload value to reflect that the second tick period is already\n             * underway.  The expected idle time is always at least two ticks. */\n            ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );\n\n            if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )\n            {\n                portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;\n                ulReloadValue -= ulTimerCountsForOneTick;\n            }\n\n            if( ulReloadValue > ulStoppedTimerCompensation )\n            {\n                ulReloadValue -= ulStoppedTimerCompensation;\n            }\n\n            /* Set the new reload value. */\n            portNVIC_SYSTICK_LOAD_REG = ulReloadValue;\n\n            /* Clear the SysTick count flag and set the count value back to\n             * zero. */\n            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n            /* Restart SysTick. */\n            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\n\n            /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can\n             * set its parameter to 0 to indicate that its implementation contains\n             * its own wait for interrupt or wait for event instruction, and so wfi\n             * should not be executed again.  However, the original expected idle\n             * time variable must remain unmodified, so a copy is taken. */\n            xModifiableIdleTime = xExpectedIdleTime;\n            configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\n\n            if( xModifiableIdleTime > 0 )\n            {\n                __asm volatile ( \"dsb\" ::: \"memory\" );\n                __asm volatile ( \"wfi\" );\n                __asm volatile ( \"isb\" );\n            }\n\n            configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\n\n            /* Re-enable interrupts to allow the interrupt that brought the MCU\n             * out of sleep mode to execute immediately.  See comments above\n             * the cpsid instruction above. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n            __asm volatile ( \"dsb\" );\n            __asm volatile ( \"isb\" );\n\n            /* Disable interrupts again because the clock is about to be stopped\n             * and interrupts that execute while the clock is stopped will increase\n             * any slippage between the time maintained by the RTOS and calendar\n             * time. */\n            __asm volatile ( \"cpsid i\" ::: \"memory\" );\n            __asm volatile ( \"dsb\" );\n            __asm volatile ( \"isb\" );\n\n            /* Disable the SysTick clock without reading the\n             * portNVIC_SYSTICK_CTRL_REG register to ensure the\n             * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,\n             * the time the SysTick is stopped for is accounted for as best it can\n             * be, but using the tickless mode will inevitably result in some tiny\n             * drift of the time maintained by the kernel with respect to calendar\n             * time*/\n            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );\n\n            /* Determine whether the SysTick has already counted to zero. */\n            if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n            {\n                uint32_t ulCalculatedLoadValue;\n\n                /* The tick interrupt ended the sleep (or is now pending), and\n                 * a new tick period has started.  Reset portNVIC_SYSTICK_LOAD_REG\n                 * with whatever remains of the new tick period. */\n                ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\n\n                /* Don't allow a tiny value, or values that have somehow\n                 * underflowed because the post sleep hook did something\n                 * that took too long or because the SysTick current-value register\n                 * is zero. */\n                if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )\n                {\n                    ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );\n                }\n\n                portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;\n\n                /* As the pending tick will be processed as soon as this\n                 * function exits, the tick value maintained by the tick is stepped\n                 * forward by one less than the time spent waiting. */\n                ulCompleteTickPeriods = xExpectedIdleTime - 1UL;\n            }\n            else\n            {\n                /* Something other than the tick interrupt ended the sleep. */\n\n                /* Use the SysTick current-value register to determine the\n                 * number of SysTick decrements remaining until the expected idle\n                 * time would have ended. */\n                ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n                #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )\n                {\n                    /* If the SysTick is not using the core clock, the current-\n                     * value register might still be zero here.  In that case, the\n                     * SysTick didn't load from the reload register, and there are\n                     * ulReloadValue decrements remaining in the expected idle\n                     * time, not zero. */\n                    if( ulSysTickDecrementsLeft == 0 )\n                    {\n                        ulSysTickDecrementsLeft = ulReloadValue;\n                    }\n                }\n                #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */\n\n                /* Work out how long the sleep lasted rounded to complete tick\n                 * periods (not the ulReload value which accounted for part\n                 * ticks). */\n                ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;\n\n                /* How many complete tick periods passed while the processor\n                 * was waiting? */\n                ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;\n\n                /* The reload value is set to whatever fraction of a single tick\n                 * period remains. */\n                portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;\n            }\n\n            /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,\n             * then set portNVIC_SYSTICK_LOAD_REG back to its standard value.  If\n             * the SysTick is not using the core clock, temporarily configure it to\n             * use the core clock.  This configuration forces the SysTick to load\n             * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next\n             * cycle of the other clock.  Then portNVIC_SYSTICK_LOAD_REG is ready\n             * to receive the standard value immediately. */\n            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n            portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n            #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )\n            {\n                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n            }\n            #else\n            {\n                /* The temporary usage of the core clock has served its purpose,\n                 * as described above.  Resume usage of the other clock. */\n                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\n\n                if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n                {\n                    /* The partial tick period already ended.  Be sure the SysTick\n                     * counts it only once. */\n                    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;\n                }\n\n                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n            }\n            #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */\n\n            /* Step the tick to account for any tick periods that elapsed. */\n            vTaskStepTick( ulCompleteTickPeriods );\n\n            /* Exit with interrupts enabled. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n        }\n    }\n#endif /* configUSE_TICKLESS_IDLE */\n/*-----------------------------------------------------------*/\n\n__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Calculate the constants required to configure the tick interrupt. */\n    #if ( configUSE_TICKLESS_IDLE == 1 )\n    {\n        ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );\n        xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;\n        ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\n    }\n    #endif /* configUSE_TICKLESS_IDLE */\n\n    /* Stop and reset the SysTick. */\n    portNVIC_SYSTICK_CTRL_REG = 0UL;\n    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n    /* Configure SysTick to interrupt at the requested rate. */\n    portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\n    portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvTaskExitError( void )\n{\n    volatile uint32_t ulDummy = 0UL;\n\n    /* A function that implements a task must not exit or attempt to return to\n     * its caller as there is nothing to return to. If a task wants to exit it\n     * should instead call vTaskDelete( NULL ). Artificially force an assert()\n     * to be triggered if configASSERT() is defined, then stop here so\n     * application writers can catch the error. */\n    configASSERT( ulCriticalNesting == ~0UL );\n    portDISABLE_INTERRUPTS();\n\n    while( ulDummy == 0 )\n    {\n        /* This file calls prvTaskExitError() after the scheduler has been\n         * started to remove a compiler warning about the function being\n         * defined but never called.  ulDummy is used purely to quieten other\n         * warnings about code appearing after this function is called - making\n         * ulDummy volatile makes the compiler think the function could return\n         * and therefore not output an 'unreachable code' warning for code that\n         * appears after it. */\n    }\n}\n/*-----------------------------------------------------------*/\n\n#if ( configENABLE_MPU == 1 )\n    static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */\n    {\n        #if defined( __ARMCC_VERSION )\n\n            /* Declaration when these variable are defined in code instead of being\n             * exported from linker scripts. */\n            extern uint32_t * __privileged_functions_start__;\n            extern uint32_t * __privileged_functions_end__;\n            extern uint32_t * __syscalls_flash_start__;\n            extern uint32_t * __syscalls_flash_end__;\n            extern uint32_t * __unprivileged_flash_start__;\n            extern uint32_t * __unprivileged_flash_end__;\n            extern uint32_t * __privileged_sram_start__;\n            extern uint32_t * __privileged_sram_end__;\n        #else /* if defined( __ARMCC_VERSION ) */\n            /* Declaration when these variable are exported from linker scripts. */\n            extern uint32_t __privileged_functions_start__[];\n            extern uint32_t __privileged_functions_end__[];\n            extern uint32_t __syscalls_flash_start__[];\n            extern uint32_t __syscalls_flash_end__[];\n            extern uint32_t __unprivileged_flash_start__[];\n            extern uint32_t __unprivileged_flash_end__[];\n            extern uint32_t __privileged_sram_start__[];\n            extern uint32_t __privileged_sram_end__[];\n        #endif /* defined( __ARMCC_VERSION ) */\n\n        /* The only permitted number of regions are 8 or 16. */\n        configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );\n\n        /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */\n        configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );\n\n        /* Check that the MPU is present. */\n        if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )\n        {\n            /* MAIR0 - Index 0. */\n            portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\n            /* MAIR0 - Index 1. */\n            portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\n\n            /* Setup privileged flash as Read Only so that privileged tasks can\n             * read it but not modify. */\n            portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_PRIVILEGED_READ_ONLY );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Setup unprivileged flash as Read Only by both privileged and\n             * unprivileged tasks. All tasks can read it but no-one can modify. */\n            portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_READ_ONLY );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Setup unprivileged syscalls flash as Read Only by both privileged\n             * and unprivileged tasks. All tasks can read it but no-one can modify. */\n            portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_READ_ONLY );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Setup RAM containing kernel data for privileged access only. */\n            portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\n                               ( portMPU_REGION_EXECUTE_NEVER );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Enable mem fault. */\n            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;\n\n            /* Enable MPU with privileged background access i.e. unmapped\n             * regions have privileged access. */\n            portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );\n        }\n    }\n#endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\n#if ( configENABLE_FPU == 1 )\n    static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */\n    {\n        #if ( configENABLE_TRUSTZONE == 1 )\n        {\n            /* Enable non-secure access to the FPU. */\n            SecureInit_EnableNSFPUAccess();\n        }\n        #endif /* configENABLE_TRUSTZONE */\n\n        /* CP10 = 11 ==> Full access to FPU i.e. both privileged and\n         * unprivileged code should be able to access FPU. CP11 should be\n         * programmed to the same value as CP10. */\n        *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |\n                            ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )\n                            );\n\n        /* ASPEN = 1 ==> Hardware should automatically preserve floating point\n         * context on exception entry and restore on exception return.\n         * LSPEN = 1 ==> Enable lazy context save of FP state. */\n        *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );\n    }\n#endif /* configENABLE_FPU */\n/*-----------------------------------------------------------*/\n\nvoid vPortYield( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Set a PendSV to request a context switch. */\n    portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\n\n    /* Barriers are normally not required but do ensure the code is\n     * completely within the specified behaviour for the architecture. */\n    __asm volatile ( \"dsb\" ::: \"memory\" );\n    __asm volatile ( \"isb\" );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */\n{\n    portDISABLE_INTERRUPTS();\n    ulCriticalNesting++;\n\n    /* Barriers are normally not required but do ensure the code is\n     * completely within the specified behaviour for the architecture. */\n    __asm volatile ( \"dsb\" ::: \"memory\" );\n    __asm volatile ( \"isb\" );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */\n{\n    configASSERT( ulCriticalNesting );\n    ulCriticalNesting--;\n\n    if( ulCriticalNesting == 0 )\n    {\n        portENABLE_INTERRUPTS();\n    }\n}\n/*-----------------------------------------------------------*/\n\nvoid SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */\n{\n    uint32_t ulPreviousMask;\n\n    ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();\n    {\n        /* Increment the RTOS tick. */\n        if( xTaskIncrementTick() != pdFALSE )\n        {\n            /* Pend a context switch. */\n            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\n        }\n    }\n    portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */\n{\n    #if ( configENABLE_MPU == 1 )\n        #if defined( __ARMCC_VERSION )\n\n            /* Declaration when these variable are defined in code instead of being\n             * exported from linker scripts. */\n            extern uint32_t * __syscalls_flash_start__;\n            extern uint32_t * __syscalls_flash_end__;\n        #else\n            /* Declaration when these variable are exported from linker scripts. */\n            extern uint32_t __syscalls_flash_start__[];\n            extern uint32_t __syscalls_flash_end__[];\n        #endif /* defined( __ARMCC_VERSION ) */\n    #endif /* configENABLE_MPU */\n\n    uint32_t ulPC;\n\n    #if ( configENABLE_TRUSTZONE == 1 )\n        uint32_t ulR0, ulR1;\n        extern TaskHandle_t pxCurrentTCB;\n        #if ( configENABLE_MPU == 1 )\n            uint32_t ulControl, ulIsTaskPrivileged;\n        #endif /* configENABLE_MPU */\n    #endif /* configENABLE_TRUSTZONE */\n    uint8_t ucSVCNumber;\n\n    /* Register are stored on the stack in the following order - R0, R1, R2, R3,\n     * R12, LR, PC, xPSR. */\n    ulPC = pulCallerStackAddress[ 6 ];\n    ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];\n\n    switch( ucSVCNumber )\n    {\n        #if ( configENABLE_TRUSTZONE == 1 )\n            case portSVC_ALLOCATE_SECURE_CONTEXT:\n\n                /* R0 contains the stack size passed as parameter to the\n                 * vPortAllocateSecureContext function. */\n                ulR0 = pulCallerStackAddress[ 0 ];\n\n                #if ( configENABLE_MPU == 1 )\n                {\n                    /* Read the CONTROL register value. */\n                    __asm volatile ( \"mrs %0, control\"  : \"=r\" ( ulControl ) );\n\n                    /* The task that raised the SVC is privileged if Bit[0]\n                     * in the CONTROL register is 0. */\n                    ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );\n\n                    /* Allocate and load a context for the secure task. */\n                    xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );\n                }\n                #else /* if ( configENABLE_MPU == 1 ) */\n                {\n                    /* Allocate and load a context for the secure task. */\n                    xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );\n                }\n                #endif /* configENABLE_MPU */\n\n                configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );\n                SecureContext_LoadContext( xSecureContext, pxCurrentTCB );\n                break;\n\n            case portSVC_FREE_SECURE_CONTEXT:\n\n                /* R0 contains TCB being freed and R1 contains the secure\n                 * context handle to be freed. */\n                ulR0 = pulCallerStackAddress[ 0 ];\n                ulR1 = pulCallerStackAddress[ 1 ];\n\n                /* Free the secure context. */\n                SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );\n                break;\n        #endif /* configENABLE_TRUSTZONE */\n\n        case portSVC_START_SCHEDULER:\n            #if ( configENABLE_TRUSTZONE == 1 )\n            {\n                /* De-prioritize the non-secure exceptions so that the\n                 * non-secure pendSV runs at the lowest priority. */\n                SecureInit_DePrioritizeNSExceptions();\n\n                /* Initialize the secure context management system. */\n                SecureContext_Init();\n            }\n            #endif /* configENABLE_TRUSTZONE */\n\n            #if ( configENABLE_FPU == 1 )\n            {\n                /* Setup the Floating Point Unit (FPU). */\n                prvSetupFPU();\n            }\n            #endif /* configENABLE_FPU */\n\n            /* Setup the context of the first task so that the first task starts\n             * executing. */\n            vRestoreContextOfFirstTask();\n            break;\n\n            #if ( configENABLE_MPU == 1 )\n                case portSVC_RAISE_PRIVILEGE:\n\n                    /* Only raise the privilege, if the svc was raised from any of\n                     * the system calls. */\n                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&\n                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )\n                    {\n                        vRaisePrivilege();\n                    }\n                    break;\n            #endif /* configENABLE_MPU */\n\n        default:\n            /* Incorrect SVC call. */\n            configASSERT( pdFALSE );\n    }\n}\n/*-----------------------------------------------------------*/\n/* *INDENT-OFF* */\n#if ( configENABLE_MPU == 1 )\n    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,\n                                         StackType_t * pxEndOfStack,\n                                         TaskFunction_t pxCode,\n                                         void * pvParameters,\n                                         BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */\n#else\n    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,\n                                         StackType_t * pxEndOfStack,\n                                         TaskFunction_t pxCode,\n                                         void * pvParameters ) /* PRIVILEGED_FUNCTION */\n#endif /* configENABLE_MPU */\n/* *INDENT-ON* */\n{\n    /* Simulate the stack frame as it would be created by a context switch\n     * interrupt. */\n    #if ( portPRELOAD_REGISTERS == 0 )\n    {\n        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\n        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\n        pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */\n        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */\n        pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */\n        *pxTopOfStack = portINITIAL_EXC_RETURN;\n\n        #if ( configENABLE_MPU == 1 )\n        {\n            pxTopOfStack--;\n\n            if( xRunPrivileged == pdTRUE )\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n            else\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n        }\n        #endif /* configENABLE_MPU */\n\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\n\n        #if ( configENABLE_TRUSTZONE == 1 )\n        {\n            pxTopOfStack--;\n            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\n        }\n        #endif /* configENABLE_TRUSTZONE */\n    }\n    #else /* portPRELOAD_REGISTERS */\n    {\n        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\n        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04 */\n        pxTopOfStack--;\n        *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN */\n\n        #if ( configENABLE_MPU == 1 )\n        {\n            pxTopOfStack--;\n\n            if( xRunPrivileged == pdTRUE )\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n            else\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n        }\n        #endif /* configENABLE_MPU */\n\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\n\n        #if ( configENABLE_TRUSTZONE == 1 )\n        {\n            pxTopOfStack--;\n            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\n        }\n        #endif /* configENABLE_TRUSTZONE */\n    }\n    #endif /* portPRELOAD_REGISTERS */\n\n    return pxTopOfStack;\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Make PendSV, CallSV and SysTick the same priority as the kernel. */\n    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;\n    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;\n\n    #if ( configENABLE_MPU == 1 )\n    {\n        /* Setup the Memory Protection Unit (MPU). */\n        prvSetupMPU();\n    }\n    #endif /* configENABLE_MPU */\n\n    /* Start the timer that generates the tick ISR. Interrupts are disabled\n     * here already. */\n    vPortSetupTimerInterrupt();\n\n    /* Initialize the critical nesting count ready for the first task. */\n    ulCriticalNesting = 0;\n\n    /* Start the first task. */\n    vStartFirstTask();\n\n    /* Should never get here as the tasks will now be executing. Call the task\n     * exit error function to prevent compiler warnings about a static function\n     * not being called in the case that the application writer overrides this\n     * functionality by defining configTASK_RETURN_ADDRESS. Call\n     * vTaskSwitchContext() so link time optimization does not remove the\n     * symbol. */\n    vTaskSwitchContext();\n    prvTaskExitError();\n\n    /* Should not get here. */\n    return 0;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Not implemented in ports where there is nothing to return to.\n     * Artificially force an assert. */\n    configASSERT( ulCriticalNesting == 1000UL );\n}\n/*-----------------------------------------------------------*/\n\n#if ( configENABLE_MPU == 1 )\n    void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,\n                                    const struct xMEMORY_REGION * const xRegions,\n                                    StackType_t * pxBottomOfStack,\n                                    uint32_t ulStackDepth )\n    {\n        uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;\n        int32_t lIndex = 0;\n\n        #if defined( __ARMCC_VERSION )\n\n            /* Declaration when these variable are defined in code instead of being\n             * exported from linker scripts. */\n            extern uint32_t * __privileged_sram_start__;\n            extern uint32_t * __privileged_sram_end__;\n        #else\n            /* Declaration when these variable are exported from linker scripts. */\n            extern uint32_t __privileged_sram_start__[];\n            extern uint32_t __privileged_sram_end__[];\n        #endif /* defined( __ARMCC_VERSION ) */\n\n        /* Setup MAIR0. */\n        xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\n        xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\n\n        /* This function is called automatically when the task is created - in\n         * which case the stack region parameters will be valid.  At all other\n         * times the stack parameters will not be valid and it is assumed that\n         * the stack region has already been configured. */\n        if( ulStackDepth > 0 )\n        {\n            ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;\n            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;\n\n            /* If the stack is within the privileged SRAM, do not protect it\n             * using a separate MPU region. This is needed because privileged\n             * SRAM is already protected using an MPU region and ARMv8-M does\n             * not allow overlapping MPU regions. */\n            if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) &&\n                ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) )\n            {\n                xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0;\n                xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0;\n            }\n            else\n            {\n                /* Define the region that allows access to the stack. */\n                ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK;\n                ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\n\n                xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |\n                                                             ( portMPU_REGION_NON_SHAREABLE ) |\n                                                             ( portMPU_REGION_READ_WRITE ) |\n                                                             ( portMPU_REGION_EXECUTE_NEVER );\n\n                xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) |\n                                                             ( portMPU_RLAR_ATTR_INDEX0 ) |\n                                                             ( portMPU_RLAR_REGION_ENABLE );\n            }\n        }\n\n        /* User supplied configurable regions. */\n        for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )\n        {\n            /* If xRegions is NULL i.e. the task has not specified any MPU\n             * region, the else part ensures that all the configurable MPU\n             * regions are invalidated. */\n            if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )\n            {\n                /* Translate the generic region definition contained in xRegions\n                 * into the ARMv8 specific MPU settings that are then stored in\n                 * xMPUSettings. */\n                ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;\n                ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;\n                ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\n\n                /* Start address. */\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |\n                                                                          ( portMPU_REGION_NON_SHAREABLE );\n\n                /* RO/RW. */\n                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )\n                {\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );\n                }\n                else\n                {\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );\n                }\n\n                /* XN. */\n                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )\n                {\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );\n                }\n\n                /* End Address. */\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |\n                                                                          ( portMPU_RLAR_REGION_ENABLE );\n\n                /* Normal memory/ Device memory. */\n                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )\n                {\n                    /* Attr1 in MAIR0 is configured as device memory. */\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;\n                }\n                else\n                {\n                    /* Attr0 in MAIR0 is configured as normal memory. */\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;\n                }\n            }\n            else\n            {\n                /* Invalidate the region. */\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;\n            }\n\n            lIndex++;\n        }\n    }\n#endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\nBaseType_t xPortIsInsideInterrupt( void )\n{\n    uint32_t ulCurrentInterrupt;\n    BaseType_t xReturn;\n\n    /* Obtain the number of the currently executing interrupt. Interrupt Program\n     * Status Register (IPSR) holds the exception number of the currently-executing\n     * exception or zero for Thread mode.*/\n    __asm volatile ( \"mrs %0, ipsr\" : \"=r\" ( ulCurrentInterrupt )::\"memory\" );\n\n    if( ulCurrentInterrupt == 0 )\n    {\n        xReturn = pdFALSE;\n    }\n    else\n    {\n        xReturn = pdTRUE;\n    }\n\n    return xReturn;\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM85/non_secure/portasm.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Standard includes. */\n#include <stdint.h>\n\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION\n * is defined correctly and privileged functions are placed in correct sections. */\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/* Portasm includes. */\n#include \"portasm.h\"\n\n/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the\n * header files. */\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\nvoid vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr  r2, pxCurrentTCBConst2\t\t\t\t\t\t\\n\"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n        \"\tldr  r3, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Read pxCurrentTCB. */\n        \"\tldr  r0, [r3]\t\t\t\t\t\t\t\t\t\\n\"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"\tdmb\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Complete outstanding transfers before disabling MPU. */\n            \"\tldr r2, xMPUCTRLConst2\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n            \"\tldr r4, [r2]\t\t\t\t\t\t\t\t\\n\"/* Read the value of MPU_CTRL. */\n            \"\tbic r4, #1\t\t\t\t\t\t\t\t\t\\n\"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\n            \"\tstr r4, [r2]\t\t\t\t\t\t\t\t\\n\"/* Disable MPU. */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tadds r3, #4\t\t\t\t\t\t\t\t\t\\n\"/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\n            \"\tldr  r4, [r3]\t\t\t\t\t\t\t\t\\n\"/* r4 = *r3 i.e. r4 = MAIR0. */\n            \"\tldr  r2, xMAIR0Const2\t\t\t\t\t\t\\n\"/* r2 = 0xe000edc0 [Location of MAIR0]. */\n            \"\tstr  r4, [r2]\t\t\t\t\t\t\t\t\\n\"/* Program MAIR0. */\n            \"\tldr  r2, xRNRConst2\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed98 [Location of RNR]. */\n            \"\tmovs r4, #4\t\t\t\t\t\t\t\t\t\\n\"/* r4 = 4. */\n            \"\tstr  r4, [r2]\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 4. */\n            \"\tadds r3, #4\t\t\t\t\t\t\t\t\t\\n\"/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */\n            \"\tldr  r2, xRBARConst2\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed9c [Location of RBAR]. */\n            \"\tldmia r3!, {r4-r11}\t\t\t\t\t\t\t\\n\"/* Read 4 set of RBAR/RLAR registers from TCB. */\n            \"\tstmia r2!, {r4-r11}\t\t\t\t\t\t\t\\n\"/* Write 4 set of RBAR/RLAR registers using alias registers. */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configTOTAL_MPU_REGIONS == 16 )\n            \"\tldr  r2, xRNRConst2\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed98 [Location of RNR]. */\n            \"\tmovs r4, #8\t\t\t\t\t\t\t\t\t\\n\"/* r4 = 8. */\n            \"\tstr  r4, [r2]\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 8. */\n            \"\tldr  r2, xRBARConst2\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed9c [Location of RBAR]. */\n            \"\tldmia r3!, {r4-r11}\t\t\t\t\t\t\t\\n\"/* Read 4 set of RBAR/RLAR registers from TCB. */\n            \"\tstmia r2!, {r4-r11}\t\t\t\t\t\t\t\\n\"/* Write 4 set of RBAR/RLAR registers using alias registers. */\n            \"\tldr  r2, xRNRConst2\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed98 [Location of RNR]. */\n            \"\tmovs r4, #12\t\t\t\t\t\t\t\t\\n\"/* r4 = 12. */\n            \"\tstr  r4, [r2]\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 12. */\n            \"\tldr  r2, xRBARConst2\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed9c [Location of RBAR]. */\n            \"\tldmia r3!, {r4-r11}\t\t\t\t\t\t\t\\n\"/* Read 4 set of RBAR/RLAR registers from TCB. */\n            \"\tstmia r2!, {r4-r11}\t\t\t\t\t\t\t\\n\"/* Write 4 set of RBAR/RLAR registers using alias registers. */\n        #endif /* configTOTAL_MPU_REGIONS == 16 */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tldr r2, xMPUCTRLConst2\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n            \"\tldr r4, [r2]\t\t\t\t\t\t\t\t\\n\"/* Read the value of MPU_CTRL. */\n            \"\torr r4, #1\t\t\t\t\t\t\t\t\t\\n\"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\n            \"\tstr r4, [r2]\t\t\t\t\t\t\t\t\\n\"/* Enable MPU. */\n            \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Force memory writes before continuing. */\n        #endif /* configENABLE_MPU */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"\tldm  r0!, {r1-r4}\t\t\t\t\t\t\t\\n\"/* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */\n            \"\tldr  r5, xSecureContextConst2\t\t\t\t\\n\"\n            \"\tstr  r1, [r5]\t\t\t\t\t\t\t\t\\n\"/* Set xSecureContext to this task's value for the same. */\n            \"\tmsr  psplim, r2\t\t\t\t\t\t\t\t\\n\"/* Set this task's PSPLIM value. */\n            \"\tmsr  control, r3\t\t\t\t\t\t\t\\n\"/* Set this task's CONTROL value. */\n            \"\tadds r0, #32\t\t\t\t\t\t\t\t\\n\"/* Discard everything up to r0. */\n            \"\tmsr  psp, r0\t\t\t\t\t\t\t\t\\n\"/* This is now the new top of stack to use in the task. */\n            \"\tisb\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tmov  r0, #0\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tmsr  basepri, r0\t\t\t\t\t\t\t\\n\"/* Ensure that interrupts are enabled when the first task starts. */\n            \"\tbx   r4\t\t\t\t\t\t\t\t\t\t\\n\"/* Finally, branch to EXC_RETURN. */\n        #else /* configENABLE_MPU */\n            \"\tldm  r0!, {r1-r3}\t\t\t\t\t\t\t\\n\"/* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */\n            \"\tldr  r4, xSecureContextConst2\t\t\t\t\\n\"\n            \"\tstr  r1, [r4]\t\t\t\t\t\t\t\t\\n\"/* Set xSecureContext to this task's value for the same. */\n            \"\tmsr  psplim, r2\t\t\t\t\t\t\t\t\\n\"/* Set this task's PSPLIM value. */\n            \"\tmovs r1, #2\t\t\t\t\t\t\t\t\t\\n\"/* r1 = 2. */\n            \"\tmsr  CONTROL, r1\t\t\t\t\t\t\t\\n\"/* Switch to use PSP in the thread mode. */\n            \"\tadds r0, #32\t\t\t\t\t\t\t\t\\n\"/* Discard everything up to r0. */\n            \"\tmsr  psp, r0\t\t\t\t\t\t\t\t\\n\"/* This is now the new top of stack to use in the task. */\n            \"\tisb\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tmov  r0, #0\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tmsr  basepri, r0\t\t\t\t\t\t\t\\n\"/* Ensure that interrupts are enabled when the first task starts. */\n            \"\tbx   r3\t\t\t\t\t\t\t\t\t\t\\n\"/* Finally, branch to EXC_RETURN. */\n        #endif /* configENABLE_MPU */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.align 4\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"pxCurrentTCBConst2: .word pxCurrentTCB\t\t\t\t\\n\"\n        \"xSecureContextConst2: .word xSecureContext\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"xMPUCTRLConst2: .word 0xe000ed94\t\t\t\t\\n\"\n            \"xMAIR0Const2: .word 0xe000edc0\t\t\t\t\t\\n\"\n            \"xRNRConst2: .word 0xe000ed98\t\t\t\t\t\\n\"\n            \"xRBARConst2: .word 0xe000ed9c\t\t\t\t\t\\n\"\n        #endif /* configENABLE_MPU */\n    );\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrs r0, control\t\t\t\t\t\t\t\t\t\\n\"/* r0 = CONTROL. */\n        \"\ttst r0, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\n        \"\tite ne\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmovne r0, #0\t\t\t\t\t\t\t\t\t\\n\"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\n        \"\tmoveq r0, #1\t\t\t\t\t\t\t\t\t\\n\"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return. */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.align 4\t\t\t\t\t\t\t\t\t\t\\n\"\n        ::: \"r0\", \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrs r0, control\t\t\t\t\t\t\t\t\t\\n\"/* Read the CONTROL register. */\n        \"\tbic r0, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* Clear the bit 0. */\n        \"\tmsr control, r0\t\t\t\t\t\t\t\t\t\\n\"/* Write back the new CONTROL value. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return to the caller. */\n        ::: \"r0\", \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vResetPrivilege( void ) /* __attribute__ (( naked )) */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrs r0, control\t\t\t\t\t\t\t\t\t\\n\"/* r0 = CONTROL. */\n        \"\torr r0, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* r0 = r0 | 1. */\n        \"\tmsr control, r0\t\t\t\t\t\t\t\t\t\\n\"/* CONTROL = r0. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return to the caller. */\n        ::: \"r0\", \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r0, xVTORConst\t\t\t\t\t\t\t\t\\n\"/* Use the NVIC offset register to locate the stack. */\n        \"\tldr r0, [r0]\t\t\t\t\t\t\t\t\t\\n\"/* Read the VTOR register which gives the address of vector table. */\n        \"\tldr r0, [r0]\t\t\t\t\t\t\t\t\t\\n\"/* The first entry in vector table is stack pointer. */\n        \"\tmsr msp, r0\t\t\t\t\t\t\t\t\t\t\\n\"/* Set the MSP back to the start of the stack. */\n        \"\tcpsie i\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Globally enable interrupts. */\n        \"\tcpsie f\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tsvc %0\t\t\t\t\t\t\t\t\t\t\t\\n\"/* System call to start the first task. */\n        \"\tnop\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"   .align 4\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"xVTORConst: .word 0xe000ed08\t\t\t\t\t\t\\n\"\n        ::\"i\" ( portSVC_START_SCHEDULER ) : \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nuint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrs r0, basepri\t\t\t\t\t\t\t\t\t\\n\"/* r0 = basepri. Return original basepri value. */\n        \"\tmov r1, %0\t\t\t\t\t\t\t\t\t\t\\n\"/* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */\n        \"\tmsr basepri, r1\t\t\t\t\t\t\t\t\t\\n\"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */\n        \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return. */\n        ::\"i\" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmsr basepri, r0\t\t\t\t\t\t\t\t\t\\n\"/* basepri = ulMask. */\n        \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return. */\n        ::: \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.extern SecureContext_SaveContext\t\t\t\t\\n\"\n        \"\t.extern SecureContext_LoadContext\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r3, xSecureContextConst\t\t\t\t\t\t\\n\"/* Read the location of xSecureContext i.e. &( xSecureContext ). */\n        \"\tldr r0, [r3]\t\t\t\t\t\t\t\t\t\\n\"/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */\n        \"\tldr r3, pxCurrentTCBConst\t\t\t\t\t\t\\n\"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n        \"\tldr r1, [r3]\t\t\t\t\t\t\t\t\t\\n\"/* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */\n        \"\tmrs r2, psp\t\t\t\t\t\t\t\t\t\t\\n\"/* Read PSP in r2. */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tcbz r0, save_ns_context\t\t\t\t\t\t\t\\n\"/* No secure context to save. */\n        \"\tpush {r0-r2, r14}\t\t\t\t\t\t\t\t\\n\"\n        \"\tbl SecureContext_SaveContext\t\t\t\t\t\\n\"/* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */\n        \"\tpop {r0-r3}\t\t\t\t\t\t\t\t\t\t\\n\"/* LR is now in r3. */\n        \"\tmov lr, r3\t\t\t\t\t\t\t\t\t\t\\n\"/* LR = r3. */\n        \"\tlsls r1, r3, #25\t\t\t\t\t\t\t\t\\n\"/* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\n        \"\tbpl save_ns_context\t\t\t\t\t\t\t\t\\n\"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r3, pxCurrentTCBConst\t\t\t\t\t\t\\n\"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n        \"\tldr r1, [r3]\t\t\t\t\t\t\t\t\t\\n\"/* Read pxCurrentTCB.*/\n        #if ( configENABLE_MPU == 1 )\n            \"\tsubs r2, r2, #16\t\t\t\t\t\t\t\\n\"/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */\n            \"\tstr r2, [r1]\t\t\t\t\t\t\t\t\\n\"/* Save the new top of stack in TCB. */\n            \"\tmrs r1, psplim\t\t\t\t\t\t\t\t\\n\"/* r1 = PSPLIM. */\n            \"\tmrs r3, control\t\t\t\t\t\t\t\t\\n\"/* r3 = CONTROL. */\n            \"\tmov r4, lr\t\t\t\t\t\t\t\t\t\\n\"/* r4 = LR/EXC_RETURN. */\n            \"\tstmia r2!, {r0, r1, r3, r4}\t\t\t\t\t\\n\"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\n        #else /* configENABLE_MPU */\n            \"\tsubs r2, r2, #12\t\t\t\t\t\t\t\\n\"/* Make space for xSecureContext, PSPLIM and LR on the stack. */\n            \"\tstr r2, [r1]\t\t\t\t\t\t\t\t\\n\"/* Save the new top of stack in TCB. */\n            \"\tmrs r1, psplim\t\t\t\t\t\t\t\t\\n\"/* r1 = PSPLIM. */\n            \"\tmov r3, lr\t\t\t\t\t\t\t\t\t\\n\"/* r3 = LR/EXC_RETURN. */\n            \"\tstmia r2!, {r0, r1, r3}\t\t\t\t\t\t\\n\"/* Store xSecureContext, PSPLIM and LR on the stack. */\n        #endif /* configENABLE_MPU */\n        \"\tb select_next_task\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \" save_ns_context:\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r3, pxCurrentTCBConst\t\t\t\t\t\t\\n\"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n        \"\tldr r1, [r3]\t\t\t\t\t\t\t\t\t\\n\"/* Read pxCurrentTCB. */\n        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )\n            \"\ttst lr, #0x10\t\t\t\t\t\t\t\t\\n\"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */\n            \"\tit eq\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tvstmdbeq r2!, {s16-s31}\t\t\t\t\t\t\\n\"/* Store the additional FP context registers which are not saved automatically. */\n        #endif /* configENABLE_FPU || configENABLE_MVE */\n        #if ( configENABLE_MPU == 1 )\n            \"\tsubs r2, r2, #48\t\t\t\t\t\t\t\\n\"/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */\n            \"\tstr r2, [r1]\t\t\t\t\t\t\t\t\\n\"/* Save the new top of stack in TCB. */\n            \"\tadds r2, r2, #16\t\t\t\t\t\t\t\\n\"/* r2 = r2 + 16. */\n            \"\tstm r2, {r4-r11}\t\t\t\t\t\t\t\\n\"/* Store the registers that are not saved automatically. */\n            \"\tmrs r1, psplim\t\t\t\t\t\t\t\t\\n\"/* r1 = PSPLIM. */\n            \"\tmrs r3, control\t\t\t\t\t\t\t\t\\n\"/* r3 = CONTROL. */\n            \"\tmov r4, lr\t\t\t\t\t\t\t\t\t\\n\"/* r4 = LR/EXC_RETURN. */\n            \"\tsubs r2, r2, #16\t\t\t\t\t\t\t\\n\"/* r2 = r2 - 16. */\n            \"\tstmia r2!, {r0, r1, r3, r4}\t\t\t\t\t\\n\"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\n        #else /* configENABLE_MPU */\n            \"\tsubs r2, r2, #44\t\t\t\t\t\t\t\\n\"/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */\n            \"\tstr r2, [r1]\t\t\t\t\t\t\t\t\\n\"/* Save the new top of stack in TCB. */\n            \"\tadds r2, r2, #12\t\t\t\t\t\t\t\\n\"/* r2 = r2 + 12. */\n            \"\tstm r2, {r4-r11}\t\t\t\t\t\t\t\\n\"/* Store the registers that are not saved automatically. */\n            \"\tmrs r1, psplim\t\t\t\t\t\t\t\t\\n\"/* r1 = PSPLIM. */\n            \"\tmov r3, lr\t\t\t\t\t\t\t\t\t\\n\"/* r3 = LR/EXC_RETURN. */\n            \"\tsubs r2, r2, #12\t\t\t\t\t\t\t\\n\"/* r2 = r2 - 12. */\n            \"\tstmia r2!, {r0, r1, r3}\t\t\t\t\t\t\\n\"/* Store xSecureContext, PSPLIM and LR on the stack. */\n        #endif /* configENABLE_MPU */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \" select_next_task:\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmov r0, %0\t\t\t\t\t\t\t\t\t\t\\n\"/* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */\n        \"\tmsr basepri, r0\t\t\t\t\t\t\t\t\t\\n\"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */\n        \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tbl vTaskSwitchContext\t\t\t\t\t\t\t\\n\"\n        \"\tmov r0, #0\t\t\t\t\t\t\t\t\t\t\\n\"/* r0 = 0. */\n        \"\tmsr basepri, r0\t\t\t\t\t\t\t\t\t\\n\"/* Enable interrupts. */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r3, pxCurrentTCBConst\t\t\t\t\t\t\\n\"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n        \"\tldr r1, [r3]\t\t\t\t\t\t\t\t\t\\n\"/* Read pxCurrentTCB. */\n        \"\tldr r2, [r1]\t\t\t\t\t\t\t\t\t\\n\"/* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"\tdmb\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Complete outstanding transfers before disabling MPU. */\n            \"\tldr r3, xMPUCTRLConst\t\t\t\t\t\t\\n\"/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */\n            \"\tldr r4, [r3]\t\t\t\t\t\t\t\t\\n\"/* Read the value of MPU_CTRL. */\n            \"\tbic r4, #1\t\t\t\t\t\t\t\t\t\\n\"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\n            \"\tstr r4, [r3]\t\t\t\t\t\t\t\t\\n\"/* Disable MPU. */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tadds r1, #4\t\t\t\t\t\t\t\t\t\\n\"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\n            \"\tldr r4, [r1]\t\t\t\t\t\t\t\t\\n\"/* r4 = *r1 i.e. r4 = MAIR0. */\n            \"\tldr r3, xMAIR0Const\t\t\t\t\t\t\t\\n\"/* r3 = 0xe000edc0 [Location of MAIR0]. */\n            \"\tstr r4, [r3]\t\t\t\t\t\t\t\t\\n\"/* Program MAIR0. */\n            \"\tldr r3, xRNRConst\t\t\t\t\t\t\t\\n\"/* r3 = 0xe000ed98 [Location of RNR]. */\n            \"\tmovs r4, #4\t\t\t\t\t\t\t\t\t\\n\"/* r4 = 4. */\n            \"\tstr r4, [r3]\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 4. */\n            \"\tadds r1, #4\t\t\t\t\t\t\t\t\t\\n\"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\n            \"\tldr r3, xRBARConst\t\t\t\t\t\t\t\\n\"/* r3 = 0xe000ed9c [Location of RBAR]. */\n            \"\tldmia r1!, {r4-r11}\t\t\t\t\t\t\t\\n\"/* Read 4 sets of RBAR/RLAR registers from TCB. */\n            \"\tstmia r3!, {r4-r11}\t\t\t\t\t\t\t\\n\"/* Write 4 set of RBAR/RLAR registers using alias registers. */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            #if ( configTOTAL_MPU_REGIONS == 16 )\n            \"\tldr r3, xRNRConst\t\t\t\t\t\t\t\\n\"/* r3 = 0xe000ed98 [Location of RNR]. */\n            \"\tmovs r4, #8\t\t\t\t\t\t\t\t\t\\n\"/* r4 = 8. */\n            \"\tstr r4, [r3]\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 8. */\n            \"\tldr r3, xRBARConst\t\t\t\t\t\t\t\\n\"/* r3 = 0xe000ed9c [Location of RBAR]. */\n            \"\tldmia r1!, {r4-r11}\t\t\t\t\t\t\t\\n\"/* Read 4 sets of RBAR/RLAR registers from TCB. */\n            \"\tstmia r3!, {r4-r11}\t\t\t\t\t\t\t\\n\"/* Write 4 set of RBAR/RLAR registers using alias registers. */\n            \"\tldr r3, xRNRConst\t\t\t\t\t\t\t\\n\"/* r3 = 0xe000ed98 [Location of RNR]. */\n            \"\tmovs r4, #12\t\t\t\t\t\t\t\t\\n\"/* r4 = 12. */\n            \"\tstr r4, [r3]\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 12. */\n            \"\tldr r3, xRBARConst\t\t\t\t\t\t\t\\n\"/* r3 = 0xe000ed9c [Location of RBAR]. */\n            \"\tldmia r1!, {r4-r11}\t\t\t\t\t\t\t\\n\"/* Read 4 sets of RBAR/RLAR registers from TCB. */\n            \"\tstmia r3!, {r4-r11}\t\t\t\t\t\t\t\\n\"/* Write 4 set of RBAR/RLAR registers using alias registers. */\n            #endif /* configTOTAL_MPU_REGIONS == 16 */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tldr r3, xMPUCTRLConst\t\t\t\t\t\t\\n\"/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */\n            \"\tldr r4, [r3]\t\t\t\t\t\t\t\t\\n\"/* Read the value of MPU_CTRL. */\n            \"\torr r4, #1\t\t\t\t\t\t\t\t\t\\n\"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\n            \"\tstr r4, [r3]\t\t\t\t\t\t\t\t\\n\"/* Enable MPU. */\n            \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Force memory writes before continuing. */\n        #endif /* configENABLE_MPU */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"\tldmia r2!, {r0, r1, r3, r4}\t\t\t\t\t\\n\"/* Read from stack - r0 = xSecureContext, r1 = PSPLIM, r3 = CONTROL and r4 = LR. */\n            \"\tmsr psplim, r1\t\t\t\t\t\t\t\t\\n\"/* Restore the PSPLIM register value for the task. */\n            \"\tmsr control, r3\t\t\t\t\t\t\t\t\\n\"/* Restore the CONTROL register value for the task. */\n            \"\tmov lr, r4\t\t\t\t\t\t\t\t\t\\n\"/* LR = r4. */\n            \"\tldr r3, xSecureContextConst\t\t\t\t\t\\n\"/* Read the location of xSecureContext i.e. &( xSecureContext ). */\n            \"\tstr r0, [r3]\t\t\t\t\t\t\t\t\\n\"/* Restore the task's xSecureContext. */\n            \"\tcbz r0, restore_ns_context\t\t\t\t\t\\n\"/* If there is no secure context for the task, restore the non-secure context. */\n            \"\tldr r3, pxCurrentTCBConst\t\t\t\t\t\\n\"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n            \"\tldr r1, [r3]\t\t\t\t\t\t\t\t\\n\"/* Read pxCurrentTCB. */\n            \"\tpush {r2, r4}\t\t\t\t\t\t\t\t\\n\"\n            \"\tbl SecureContext_LoadContext\t\t\t\t\\n\"/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */\n            \"\tpop {r2, r4}\t\t\t\t\t\t\t\t\\n\"\n            \"\tmov lr, r4\t\t\t\t\t\t\t\t\t\\n\"/* LR = r4. */\n            \"\tlsls r1, r4, #25\t\t\t\t\t\t\t\\n\"/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\n            \"\tbpl restore_ns_context\t\t\t\t\t\t\\n\"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\n            \"\tmsr psp, r2\t\t\t\t\t\t\t\t\t\\n\"/* Remember the new top of stack for the task. */\n            \"\tbx lr\t\t\t\t\t\t\t\t\t\t\\n\"\n        #else /* configENABLE_MPU */\n            \"\tldmia r2!, {r0, r1, r4}\t\t\t\t\t\t\\n\"/* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */\n            \"\tmsr psplim, r1\t\t\t\t\t\t\t\t\\n\"/* Restore the PSPLIM register value for the task. */\n            \"\tmov lr, r4\t\t\t\t\t\t\t\t\t\\n\"/* LR = r4. */\n            \"\tldr r3, xSecureContextConst\t\t\t\t\t\\n\"/* Read the location of xSecureContext i.e. &( xSecureContext ). */\n            \"\tstr r0, [r3]\t\t\t\t\t\t\t\t\\n\"/* Restore the task's xSecureContext. */\n            \"\tcbz r0, restore_ns_context\t\t\t\t\t\\n\"/* If there is no secure context for the task, restore the non-secure context. */\n            \"\tldr r3, pxCurrentTCBConst\t\t\t\t\t\\n\"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n            \"\tldr r1, [r3]\t\t\t\t\t\t\t\t\\n\"/* Read pxCurrentTCB. */\n            \"\tpush {r2, r4}\t\t\t\t\t\t\t\t\\n\"\n            \"\tbl SecureContext_LoadContext\t\t\t\t\\n\"/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */\n            \"\tpop {r2, r4}\t\t\t\t\t\t\t\t\\n\"\n            \"\tmov lr, r4\t\t\t\t\t\t\t\t\t\\n\"/* LR = r4. */\n            \"\tlsls r1, r4, #25\t\t\t\t\t\t\t\\n\"/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\n            \"\tbpl restore_ns_context\t\t\t\t\t\t\\n\"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\n            \"\tmsr psp, r2\t\t\t\t\t\t\t\t\t\\n\"/* Remember the new top of stack for the task. */\n            \"\tbx lr\t\t\t\t\t\t\t\t\t\t\\n\"\n        #endif /* configENABLE_MPU */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \" restore_ns_context:\t\t\t\t\t\t\t\t\\n\"\n        \"\tldmia r2!, {r4-r11}\t\t\t\t\t\t\t\t\\n\"/* Restore the registers that are not automatically restored. */\n        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )\n            \"\ttst lr, #0x10\t\t\t\t\t\t\t\t\\n\"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */\n            \"\tit eq\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tvldmiaeq r2!, {s16-s31}\t\t\t\t\t\t\\n\"/* Restore the additional FP context registers which are not restored automatically. */\n        #endif /* configENABLE_FPU || configENABLE_MVE */\n        \"\tmsr psp, r2\t\t\t\t\t\t\t\t\t\t\\n\"/* Remember the new top of stack for the task. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.align 4\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"pxCurrentTCBConst: .word pxCurrentTCB\t\t\t\t\\n\"\n        \"xSecureContextConst: .word xSecureContext\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"xMPUCTRLConst: .word 0xe000ed94\t\t\t\t\\n\"\n            \"xMAIR0Const: .word 0xe000edc0\t\t\t\t\t\\n\"\n            \"xRNRConst: .word 0xe000ed98\t\t\t\t\t\\n\"\n            \"xRBARConst: .word 0xe000ed9c\t\t\t\t\t\\n\"\n        #endif /* configENABLE_MPU */\n        ::\"i\" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\ttst lr, #4\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tite eq\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrseq r0, msp\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrsne r0, psp\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r1, svchandler_address_const\t\t\t\t\\n\"\n        \"\tbx r1\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.align 4\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"svchandler_address_const: .word vPortSVCHandler_C\t\\n\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tsvc %0\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Secure context is allocated in the supervisor call. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return. */\n        ::\"i\" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r2, [r0]\t\t\t\t\t\t\t\t\t\\n\"/* The first item in the TCB is the top of the stack. */\n        \"\tldr r1, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* The first item on the stack is the task's xSecureContext. */\n        \"\tcmp r1, #0\t\t\t\t\t\t\t\t\t\t\\n\"/* Raise svc if task's xSecureContext is not NULL. */\n        \"\tit ne\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tsvcne %0\t\t\t\t\t\t\t\t\t\t\\n\"/* Secure context is freed in the supervisor call. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return. */\n        ::\"i\" ( portSVC_FREE_SECURE_CONTEXT ) : \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM85/non_secure/portasm.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef __PORT_ASM_H__\n#define __PORT_ASM_H__\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n\n/* MPU wrappers includes. */\n#include \"mpu_wrappers.h\"\n\n/**\n * @brief Restore the context of the first task so that the first task starts\n * executing.\n */\nvoid vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Checks whether or not the processor is privileged.\n *\n * @return 1 if the processor is already privileged, 0 otherwise.\n */\nBaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );\n\n/**\n * @brief Raises the privilege level by clearing the bit 0 of the CONTROL\n * register.\n *\n * @note This is a privileged function and should only be called from the kenrel\n * code.\n *\n * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.\n *  Bit[0] = 0 --> The processor is running privileged\n *  Bit[0] = 1 --> The processor is running unprivileged.\n */\nvoid vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\n * register.\n *\n * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.\n *  Bit[0] = 0 --> The processor is running privileged\n *  Bit[0] = 1 --> The processor is running unprivileged.\n */\nvoid vResetPrivilege( void ) __attribute__( ( naked ) );\n\n/**\n * @brief Starts the first task.\n */\nvoid vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Disables interrupts.\n */\nuint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Enables interrupts.\n */\nvoid vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief PendSV Exception handler.\n */\nvoid PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief SVC Handler.\n */\nvoid SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Allocate a Secure context for the calling task.\n *\n * @param[in] ulSecureStackSize The size of the stack to be allocated on the\n * secure side for the calling task.\n */\nvoid vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) );\n\n/**\n * @brief Free the task's secure context.\n *\n * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.\n */\nvoid vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n#endif /* __PORT_ASM_H__ */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM85/non_secure/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef PORTMACRO_H\n#define PORTMACRO_H\n\n#ifdef __cplusplus\n    extern \"C\" {\n#endif\n\n#include \"portmacrocommon.h\"\n\n/*------------------------------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the given hardware\n * and compiler.\n *\n * These settings should not be altered.\n *------------------------------------------------------------------------------\n */\n\n#ifndef configENABLE_MVE\n    #error configENABLE_MVE must be defined in FreeRTOSConfig.h. Set configENABLE_MVE to 1 to enable the MVE or 0 to disable the MVE.\n#endif /* configENABLE_MVE */\n/*-----------------------------------------------------------*/\n\n/**\n * Architecture specifics.\n */\n#define portARCH_NAME                       \"Cortex-M85\"\n#define portDONT_DISCARD                    __attribute__( ( used ) )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Critical section management.\n */\n#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()\n#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )\n/*-----------------------------------------------------------*/\n\n#ifdef __cplusplus\n    }\n#endif\n\n#endif /* PORTMACRO_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef PORTMACROCOMMON_H\n    #define PORTMACROCOMMON_H\n\n    #ifdef __cplusplus\n        extern \"C\" {\n    #endif\n\n/*------------------------------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the given hardware\n * and compiler.\n *\n * These settings should not be altered.\n *------------------------------------------------------------------------------\n */\n\n    #ifndef configENABLE_FPU\n        #error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.\n    #endif /* configENABLE_FPU */\n\n    #ifndef configENABLE_MPU\n        #error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.\n    #endif /* configENABLE_MPU */\n\n    #ifndef configENABLE_TRUSTZONE\n        #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.\n    #endif /* configENABLE_TRUSTZONE */\n\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Type definitions.\n */\n    #define portCHAR          char\n    #define portFLOAT         float\n    #define portDOUBLE        double\n    #define portLONG          long\n    #define portSHORT         short\n    #define portSTACK_TYPE    uint32_t\n    #define portBASE_TYPE     long\n\n    typedef portSTACK_TYPE   StackType_t;\n    typedef long             BaseType_t;\n    typedef unsigned long    UBaseType_t;\n\n    #if ( configUSE_16_BIT_TICKS == 1 )\n        typedef uint16_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffff\n    #else\n        typedef uint32_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL\n\n/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\n * not need to be guarded with a critical section. */\n        #define portTICK_TYPE_IS_ATOMIC    1\n    #endif\n/*-----------------------------------------------------------*/\n\n/**\n * Architecture specifics.\n */\n    #define portSTACK_GROWTH                   ( -1 )\n    #define portTICK_PERIOD_MS                 ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\n    #define portBYTE_ALIGNMENT                 8\n    #define portNOP()\n    #define portINLINE                         __inline\n    #ifndef portFORCE_INLINE\n        #define portFORCE_INLINE               inline __attribute__( ( always_inline ) )\n    #endif\n    #define portHAS_STACK_OVERFLOW_CHECKING    1\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Extern declarations.\n */\n    extern BaseType_t xPortIsInsideInterrupt( void );\n\n    extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;\n\n    extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;\n    extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;\n\n    extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\n    extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\n\n    #if ( configENABLE_TRUSTZONE == 1 )\n        extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */\n        extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;\n    #endif /* configENABLE_TRUSTZONE */\n\n    #if ( configENABLE_MPU == 1 )\n        extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;\n        extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;\n    #endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\n/**\n * @brief MPU specific constants.\n */\n    #if ( configENABLE_MPU == 1 )\n        #define portUSING_MPU_WRAPPERS    1\n        #define portPRIVILEGE_BIT         ( 0x80000000UL )\n    #else\n        #define portPRIVILEGE_BIT         ( 0x0UL )\n    #endif /* configENABLE_MPU */\n\n/* MPU settings that can be overriden in FreeRTOSConfig.h. */\n#ifndef configTOTAL_MPU_REGIONS\n    /* Define to 8 for backward compatibility. */\n    #define configTOTAL_MPU_REGIONS       ( 8UL )\n#endif\n\n/* MPU regions. */\n    #define portPRIVILEGED_FLASH_REGION                   ( 0UL )\n    #define portUNPRIVILEGED_FLASH_REGION                 ( 1UL )\n    #define portUNPRIVILEGED_SYSCALLS_REGION              ( 2UL )\n    #define portPRIVILEGED_RAM_REGION                     ( 3UL )\n    #define portSTACK_REGION                              ( 4UL )\n    #define portFIRST_CONFIGURABLE_REGION                 ( 5UL )\n    #define portLAST_CONFIGURABLE_REGION                  ( configTOTAL_MPU_REGIONS - 1UL )\n    #define portNUM_CONFIGURABLE_REGIONS                  ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )\n    #define portTOTAL_NUM_REGIONS                         ( portNUM_CONFIGURABLE_REGIONS + 1 )   /* Plus one to make space for the stack region. */\n\n/* Device memory attributes used in MPU_MAIR registers.\n *\n * 8-bit values encoded as follows:\n *  Bit[7:4] - 0000 - Device Memory\n *  Bit[3:2] - 00 --> Device-nGnRnE\n *\t\t\t\t01 --> Device-nGnRE\n *\t\t\t\t10 --> Device-nGRE\n *\t\t\t\t11 --> Device-GRE\n *  Bit[1:0] - 00, Reserved.\n */\n    #define portMPU_DEVICE_MEMORY_nGnRnE                  ( 0x00 )   /* 0000 0000 */\n    #define portMPU_DEVICE_MEMORY_nGnRE                   ( 0x04 )   /* 0000 0100 */\n    #define portMPU_DEVICE_MEMORY_nGRE                    ( 0x08 )   /* 0000 1000 */\n    #define portMPU_DEVICE_MEMORY_GRE                     ( 0x0C )   /* 0000 1100 */\n\n/* Normal memory attributes used in MPU_MAIR registers. */\n    #define portMPU_NORMAL_MEMORY_NON_CACHEABLE           ( 0x44 )   /* Non-cacheable. */\n    #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE    ( 0xFF )   /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */\n\n/* Attributes used in MPU_RBAR registers. */\n    #define portMPU_REGION_NON_SHAREABLE                  ( 0UL << 3UL )\n    #define portMPU_REGION_INNER_SHAREABLE                ( 1UL << 3UL )\n    #define portMPU_REGION_OUTER_SHAREABLE                ( 2UL << 3UL )\n\n    #define portMPU_REGION_PRIVILEGED_READ_WRITE          ( 0UL << 1UL )\n    #define portMPU_REGION_READ_WRITE                     ( 1UL << 1UL )\n    #define portMPU_REGION_PRIVILEGED_READ_ONLY           ( 2UL << 1UL )\n    #define portMPU_REGION_READ_ONLY                      ( 3UL << 1UL )\n\n    #define portMPU_REGION_EXECUTE_NEVER                  ( 1UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Settings to define an MPU region.\n */\n    typedef struct MPURegionSettings\n    {\n        uint32_t ulRBAR; /**< RBAR for the region. */\n        uint32_t ulRLAR; /**< RLAR for the region. */\n    } MPURegionSettings_t;\n\n/**\n * @brief MPU settings as stored in the TCB.\n */\n    typedef struct MPU_SETTINGS\n    {\n        uint32_t ulMAIR0;                                              /**< MAIR0 for the task containing attributes for all the 4 per task regions. */\n        MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */\n    } xMPU_SETTINGS;\n/*-----------------------------------------------------------*/\n\n/**\n * @brief SVC numbers.\n */\n    #define portSVC_ALLOCATE_SECURE_CONTEXT    0\n    #define portSVC_FREE_SECURE_CONTEXT        1\n    #define portSVC_START_SCHEDULER            2\n    #define portSVC_RAISE_PRIVILEGE            3\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Scheduler utilities.\n */\n    #define portYIELD()                                 vPortYield()\n    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )\n    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )\n    #define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )\n    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Critical section management.\n */\n    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulSetInterruptMask()\n    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vClearInterruptMask( x )\n    #define portENTER_CRITICAL()                      vPortEnterCritical()\n    #define portEXIT_CRITICAL()                       vPortExitCritical()\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Tickless idle/low power functionality.\n */\n    #ifndef portSUPPRESS_TICKS_AND_SLEEP\n        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );\n        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )\n    #endif\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Task function macros as described on the FreeRTOS.org WEB site.\n */\n    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )\n    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )\n/*-----------------------------------------------------------*/\n\n    #if ( configENABLE_TRUSTZONE == 1 )\n\n/**\n * @brief Allocate a secure context for the task.\n *\n * Tasks are not created with a secure context. Any task that is going to call\n * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a\n * secure context before it calls any secure function.\n *\n * @param[in] ulSecureStackSize The size of the secure stack to be allocated.\n */\n        #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )\n\n/**\n * @brief Called when a task is deleted to delete the task's secure context,\n * if it has one.\n *\n * @param[in] pxTCB The TCB of the task being deleted.\n */\n        #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )\n    #endif /* configENABLE_TRUSTZONE */\n/*-----------------------------------------------------------*/\n\n    #if ( configENABLE_MPU == 1 )\n\n/**\n * @brief Checks whether or not the processor is privileged.\n *\n * @return 1 if the processor is already privileged, 0 otherwise.\n */\n        #define portIS_PRIVILEGED()      xIsPrivileged()\n\n/**\n * @brief Raise an SVC request to raise privilege.\n *\n * The SVC handler checks that the SVC was raised from a system call and only\n * then it raises the privilege. If this is called from any other place,\n * the privilege is not raised.\n */\n        #define portRAISE_PRIVILEGE()    __asm volatile ( \"svc %0 \\n\" ::\"i\" ( portSVC_RAISE_PRIVILEGE ) : \"memory\" );\n\n/**\n * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\n * register.\n */\n        #define portRESET_PRIVILEGE()    vResetPrivilege()\n    #else\n        #define portIS_PRIVILEGED()\n        #define portRAISE_PRIVILEGE()\n        #define portRESET_PRIVILEGE()\n    #endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Barriers.\n */\n    #define portMEMORY_BARRIER()    __asm volatile ( \"\" ::: \"memory\" )\n/*-----------------------------------------------------------*/\n\n    #ifdef __cplusplus\n        }\n    #endif\n\n#endif /* PORTMACROCOMMON_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM85/secure/secure_context.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Secure context includes. */\n#include \"secure_context.h\"\n\n/* Secure heap includes. */\n#include \"secure_heap.h\"\n\n/* Secure port macros. */\n#include \"secure_port_macros.h\"\n\n/**\n * @brief CONTROL value for privileged tasks.\n *\n * Bit[0] - 0 --> Thread mode is privileged.\n * Bit[1] - 1 --> Thread mode uses PSP.\n */\n#define securecontextCONTROL_VALUE_PRIVILEGED      0x02\n\n/**\n * @brief CONTROL value for un-privileged tasks.\n *\n * Bit[0] - 1 --> Thread mode is un-privileged.\n * Bit[1] - 1 --> Thread mode uses PSP.\n */\n#define securecontextCONTROL_VALUE_UNPRIVILEGED    0x03\n\n/**\n * @brief Size of stack seal values in bytes.\n */\n#define securecontextSTACK_SEAL_SIZE               8\n\n/**\n * @brief Stack seal value as recommended by ARM.\n */\n#define securecontextSTACK_SEAL_VALUE              0xFEF5EDA5\n\n/**\n * @brief Maximum number of secure contexts.\n */\n#ifndef secureconfigMAX_SECURE_CONTEXTS\n    #define secureconfigMAX_SECURE_CONTEXTS        8UL\n#endif\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Pre-allocated array of secure contexts.\n */\nSecureContext_t xSecureContexts[ secureconfigMAX_SECURE_CONTEXTS ];\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Get a free secure context for a task from the secure context pool (xSecureContexts).\n *\n * This function ensures that only one secure context is allocated for a task.\n *\n * @param[in] pvTaskHandle The task handle for which the secure context is allocated.\n *\n * @return Index of a free secure context in the xSecureContexts array.\n */\nstatic uint32_t ulGetSecureContext( void * pvTaskHandle );\n\n/**\n * @brief Return the secure context to the secure context pool (xSecureContexts).\n *\n * @param[in] ulSecureContextIndex Index of the context in the xSecureContexts array.\n */\nstatic void vReturnSecureContext( uint32_t ulSecureContextIndex );\n\n/* These are implemented in assembly. */\nextern void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext );\nextern void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext );\n/*-----------------------------------------------------------*/\n\nstatic uint32_t ulGetSecureContext( void * pvTaskHandle )\n{\n    /* Start with invalid index. */\n    uint32_t i, ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS;\n\n    for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ )\n    {\n        if( ( xSecureContexts[ i ].pucCurrentStackPointer == NULL ) &&\n            ( xSecureContexts[ i ].pucStackLimit == NULL ) &&\n            ( xSecureContexts[ i ].pucStackStart == NULL ) &&\n            ( xSecureContexts[ i ].pvTaskHandle == NULL ) &&\n            ( ulSecureContextIndex == secureconfigMAX_SECURE_CONTEXTS ) )\n        {\n            ulSecureContextIndex = i;\n        }\n        else if( xSecureContexts[ i ].pvTaskHandle == pvTaskHandle )\n        {\n            /* A task can only have one secure context. Do not allocate a second\n             * context for the same task. */\n            ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS;\n            break;\n        }\n    }\n\n    return ulSecureContextIndex;\n}\n/*-----------------------------------------------------------*/\n\nstatic void vReturnSecureContext( uint32_t ulSecureContextIndex )\n{\n    xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = NULL;\n    xSecureContexts[ ulSecureContextIndex ].pucStackLimit = NULL;\n    xSecureContexts[ ulSecureContextIndex ].pucStackStart = NULL;\n    xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = NULL;\n}\n/*-----------------------------------------------------------*/\n\nsecureportNON_SECURE_CALLABLE void SecureContext_Init( void )\n{\n    uint32_t ulIPSR, i;\n    static uint32_t ulSecureContextsInitialized = 0;\n\n    /* Read the Interrupt Program Status Register (IPSR) value. */\n    secureportREAD_IPSR( ulIPSR );\n\n    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\n     * when the processor is running in the Thread Mode. */\n    if( ( ulIPSR != 0 ) && ( ulSecureContextsInitialized == 0 ) )\n    {\n        /* Ensure to initialize secure contexts only once. */\n        ulSecureContextsInitialized = 1;\n\n        /* No stack for thread mode until a task's context is loaded. */\n        secureportSET_PSPLIM( securecontextNO_STACK );\n        secureportSET_PSP( securecontextNO_STACK );\n\n        /* Initialize all secure contexts. */\n        for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ )\n        {\n            xSecureContexts[ i ].pucCurrentStackPointer = NULL;\n            xSecureContexts[ i ].pucStackLimit = NULL;\n            xSecureContexts[ i ].pucStackStart = NULL;\n            xSecureContexts[ i ].pvTaskHandle = NULL;\n        }\n\n        #if ( configENABLE_MPU == 1 )\n            {\n                /* Configure thread mode to use PSP and to be unprivileged. */\n                secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );\n            }\n        #else /* configENABLE_MPU */\n            {\n                /* Configure thread mode to use PSP and to be privileged. */\n                secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );\n            }\n        #endif /* configENABLE_MPU */\n    }\n}\n/*-----------------------------------------------------------*/\n\n#if ( configENABLE_MPU == 1 )\n    secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,\n                                                                                       uint32_t ulIsTaskPrivileged,\n                                                                                       void * pvTaskHandle )\n#else /* configENABLE_MPU */\n    secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,\n                                                                                       void * pvTaskHandle )\n#endif /* configENABLE_MPU */\n{\n    uint8_t * pucStackMemory = NULL;\n    uint8_t * pucStackLimit;\n    uint32_t ulIPSR, ulSecureContextIndex;\n    SecureContextHandle_t xSecureContextHandle = securecontextINVALID_CONTEXT_ID;\n\n    #if ( configENABLE_MPU == 1 )\n        uint32_t * pulCurrentStackPointer = NULL;\n    #endif /* configENABLE_MPU */\n\n    /* Read the Interrupt Program Status Register (IPSR) and Process Stack Limit\n     * Register (PSPLIM) value. */\n    secureportREAD_IPSR( ulIPSR );\n    secureportREAD_PSPLIM( pucStackLimit );\n\n    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\n     * when the processor is running in the Thread Mode.\n     * Also do nothing, if a secure context us already loaded. PSPLIM is set to\n     * securecontextNO_STACK when no secure context is loaded. */\n    if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) )\n    {\n        /* Ontain a free secure context. */\n        ulSecureContextIndex = ulGetSecureContext( pvTaskHandle );\n\n        /* Were we able to get a free context? */\n        if( ulSecureContextIndex < secureconfigMAX_SECURE_CONTEXTS )\n        {\n            /* Allocate the stack space. */\n            pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE );\n\n            if( pucStackMemory != NULL )\n            {\n                /* Since stack grows down, the starting point will be the last\n                 * location. Note that this location is next to the last\n                 * allocated byte for stack (excluding the space for seal values)\n                 * because the hardware decrements the stack pointer before\n                 * writing i.e. if stack pointer is 0x2, a push operation will\n                 * decrement the stack pointer to 0x1 and then write at 0x1. */\n                xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize;\n\n                /* Seal the created secure process stack. */\n                *( uint32_t * )( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE;\n                *( uint32_t * )( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE;\n\n                /* The stack cannot go beyond this location. This value is\n                 * programmed in the PSPLIM register on context switch.*/\n                xSecureContexts[ ulSecureContextIndex ].pucStackLimit = pucStackMemory;\n\n                xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle;\n\n                #if ( configENABLE_MPU == 1 )\n                    {\n                        /* Store the correct CONTROL value for the task on the stack.\n                         * This value is programmed in the CONTROL register on\n                         * context switch. */\n                        pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart;\n                        pulCurrentStackPointer--;\n\n                        if( ulIsTaskPrivileged )\n                        {\n                            *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;\n                        }\n                        else\n                        {\n                            *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;\n                        }\n\n                        /* Store the current stack pointer. This value is programmed in\n                         * the PSP register on context switch. */\n                        xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;\n                    }\n                #else /* configENABLE_MPU */\n                    {\n                        /* Current SP is set to the starting of the stack. This\n                         * value programmed in the PSP register on context switch. */\n                        xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart;\n                    }\n                #endif /* configENABLE_MPU */\n\n                /* Ensure to never return 0 as a valid context handle. */\n                xSecureContextHandle = ulSecureContextIndex + 1UL;\n            }\n        }\n    }\n\n    return xSecureContextHandle;\n}\n/*-----------------------------------------------------------*/\n\nsecureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )\n{\n    uint32_t ulIPSR, ulSecureContextIndex;\n\n    /* Read the Interrupt Program Status Register (IPSR) value. */\n    secureportREAD_IPSR( ulIPSR );\n\n    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\n     * when the processor is running in the Thread Mode. */\n    if( ulIPSR != 0 )\n    {\n        /* Only free if a valid context handle is passed. */\n        if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) )\n        {\n            ulSecureContextIndex = xSecureContextHandle - 1UL;\n\n            /* Ensure that the secure context being deleted is associated with\n             * the task. */\n            if( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle )\n            {\n                /* Free the stack space. */\n                vPortFree( xSecureContexts[ ulSecureContextIndex ].pucStackLimit );\n\n                /* Return the secure context back to the free secure contexts pool. */\n                vReturnSecureContext( ulSecureContextIndex );\n            }\n        }\n    }\n}\n/*-----------------------------------------------------------*/\n\nsecureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )\n{\n    uint8_t * pucStackLimit;\n    uint32_t ulSecureContextIndex;\n\n    if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) )\n    {\n        ulSecureContextIndex = xSecureContextHandle - 1UL;\n\n        secureportREAD_PSPLIM( pucStackLimit );\n\n        /* Ensure that no secure context is loaded and the task is loading it's\n         * own context. */\n        if( ( pucStackLimit == securecontextNO_STACK ) &&\n            ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) )\n        {\n            SecureContext_LoadContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) );\n        }\n    }\n}\n/*-----------------------------------------------------------*/\n\nsecureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )\n{\n    uint8_t * pucStackLimit;\n    uint32_t ulSecureContextIndex;\n\n    if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) )\n    {\n        ulSecureContextIndex = xSecureContextHandle - 1UL;\n\n        secureportREAD_PSPLIM( pucStackLimit );\n\n        /* Ensure that task's context is loaded and the task is saving it's own\n         * context. */\n        if( ( xSecureContexts[ ulSecureContextIndex ].pucStackLimit == pucStackLimit ) &&\n            ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) )\n        {\n            SecureContext_SaveContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) );\n        }\n    }\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM85/secure/secure_context.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef __SECURE_CONTEXT_H__\n#define __SECURE_CONTEXT_H__\n\n/* Standard includes. */\n#include <stdint.h>\n\n/* FreeRTOS includes. */\n#include \"FreeRTOSConfig.h\"\n\n/**\n * @brief PSP value when no secure context is loaded.\n */\n#define securecontextNO_STACK               0x0\n\n/**\n * @brief Invalid context ID.\n */\n#define securecontextINVALID_CONTEXT_ID     0UL\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Structure to represent a secure context.\n *\n * @note Since stack grows down, pucStackStart is the highest address while\n * pucStackLimit is the first address of the allocated memory.\n */\ntypedef struct SecureContext\n{\n    uint8_t * pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */\n    uint8_t * pucStackLimit;          /**< Last location of the stack memory (PSPLIM). */\n    uint8_t * pucStackStart;          /**< First location of the stack memory. */\n    void * pvTaskHandle;              /**< Task handle of the task this context is associated with. */\n} SecureContext_t;\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Opaque handle for a secure context.\n */\ntypedef uint32_t SecureContextHandle_t;\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Initializes the secure context management system.\n *\n * PSP is set to NULL and therefore a task must allocate and load a context\n * before calling any secure side function in the thread mode.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n */\nvoid SecureContext_Init( void );\n\n/**\n * @brief Allocates a context on the secure side.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n *\n * @param[in] ulSecureStackSize Size of the stack to allocate on secure side.\n * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise.\n *\n * @return Opaque context handle if context is successfully allocated, NULL\n * otherwise.\n */\n#if ( configENABLE_MPU == 1 )\n    SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,\n                                                         uint32_t ulIsTaskPrivileged,\n                                                         void * pvTaskHandle );\n#else /* configENABLE_MPU */\n    SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,\n                                                         void * pvTaskHandle );\n#endif /* configENABLE_MPU */\n\n/**\n * @brief Frees the given context.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n *\n * @param[in] xSecureContextHandle Context handle corresponding to the\n * context to be freed.\n */\nvoid SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );\n\n/**\n * @brief Loads the given context.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n *\n * @param[in] xSecureContextHandle Context handle corresponding to the context\n * to be loaded.\n */\nvoid SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );\n\n/**\n * @brief Saves the given context.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n *\n * @param[in] xSecureContextHandle Context handle corresponding to the context\n * to be saved.\n */\nvoid SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );\n\n#endif /* __SECURE_CONTEXT_H__ */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM85/secure/secure_context_port.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Secure context includes. */\n#include \"secure_context.h\"\n\n/* Secure port macros. */\n#include \"secure_port_macros.h\"\n\nvoid SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) );\nvoid SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) );\n\nvoid SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext )\n{\n    /* pxSecureContext value is in r0. */\n    __asm volatile\n    (\n        \" .syntax unified                   \\n\"\n        \"                                   \\n\"\n        \" mrs r1, ipsr                      \\n\" /* r1 = IPSR. */\n        \" cbz r1, load_ctx_therad_mode      \\n\" /* Do nothing if the processor is running in the Thread Mode. */\n        \" ldmia r0!, {r1, r2}               \\n\" /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */\n        \"                                   \\n\"\n        #if ( configENABLE_MPU == 1 )\n            \" ldmia r1!, {r3}               \\n\" /* Read CONTROL register value from task's stack. r3 = CONTROL. */\n            \" msr control, r3               \\n\" /* CONTROL = r3. */\n        #endif /* configENABLE_MPU */\n        \"                                   \\n\"\n        \" msr psplim, r2                    \\n\" /* PSPLIM = r2. */\n        \" msr psp, r1                       \\n\" /* PSP = r1. */\n        \"                                   \\n\"\n        \" load_ctx_therad_mode:             \\n\"\n        \"    bx lr                          \\n\"\n        \"                                   \\n\"\n        ::: \"r0\", \"r1\", \"r2\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext )\n{\n    /* pxSecureContext value is in r0. */\n    __asm volatile\n    (\n        \" .syntax unified                   \\n\"\n        \"                                   \\n\"\n        \" mrs r1, ipsr                      \\n\" /* r1 = IPSR. */\n        \" cbz r1, save_ctx_therad_mode      \\n\" /* Do nothing if the processor is running in the Thread Mode. */\n        \" mrs r1, psp                       \\n\" /* r1 = PSP. */\n        \"                                   \\n\"\n        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )\n            \" vstmdb r1!, {s0}              \\n\" /* Trigger the deferred stacking of FPU registers. */\n            \" vldmia r1!, {s0}              \\n\" /* Nullify the effect of the previous statement. */\n        #endif /* configENABLE_FPU || configENABLE_MVE */\n        \"                                   \\n\"\n        #if ( configENABLE_MPU == 1 )\n            \" mrs r2, control               \\n\" /* r2 = CONTROL. */\n            \" stmdb r1!, {r2}               \\n\" /* Store CONTROL value on the stack. */\n        #endif /* configENABLE_MPU */\n        \"                                   \\n\"\n        \" str r1, [r0]                      \\n\" /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */\n        \" movs r1, %0                       \\n\" /* r1 = securecontextNO_STACK. */\n        \" msr psplim, r1                    \\n\" /* PSPLIM = securecontextNO_STACK. */\n        \" msr psp, r1                       \\n\" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */\n        \"                                   \\n\"\n        \" save_ctx_therad_mode:             \\n\"\n        \"    bx lr                          \\n\"\n        \"                                   \\n\"\n        ::\"i\" ( securecontextNO_STACK ) : \"r1\", \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM85/secure/secure_heap.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Standard includes. */\n#include <stdint.h>\n\n/* Secure context heap includes. */\n#include \"secure_heap.h\"\n\n/* Secure port macros. */\n#include \"secure_port_macros.h\"\n\n/**\n * @brief Total heap size.\n */\n#ifndef secureconfigTOTAL_HEAP_SIZE\n    #define secureconfigTOTAL_HEAP_SIZE    ( ( ( size_t ) ( 10 * 1024 ) ) )\n#endif\n\n/* No test marker by default. */\n#ifndef mtCOVERAGE_TEST_MARKER\n    #define mtCOVERAGE_TEST_MARKER()\n#endif\n\n/* No tracing by default. */\n#ifndef traceMALLOC\n    #define traceMALLOC( pvReturn, xWantedSize )\n#endif\n\n/* No tracing by default. */\n#ifndef traceFREE\n    #define traceFREE( pv, xBlockSize )\n#endif\n\n/* Block sizes must not get too small. */\n#define secureheapMINIMUM_BLOCK_SIZE    ( ( size_t ) ( xHeapStructSize << 1 ) )\n\n/* Assumes 8bit bytes! */\n#define secureheapBITS_PER_BYTE         ( ( size_t ) 8 )\n/*-----------------------------------------------------------*/\n\n/* Allocate the memory for the heap. */\n#if ( configAPPLICATION_ALLOCATED_HEAP == 1 )\n\n/* The application writer has already defined the array used for the RTOS\n* heap - probably so it can be placed in a special segment or address. */\n    extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];\n#else /* configAPPLICATION_ALLOCATED_HEAP */\n    static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];\n#endif /* configAPPLICATION_ALLOCATED_HEAP */\n\n/**\n * @brief The linked list structure.\n *\n * This is used to link free blocks in order of their memory address.\n */\ntypedef struct A_BLOCK_LINK\n{\n    struct A_BLOCK_LINK * pxNextFreeBlock; /**< The next free block in the list. */\n    size_t xBlockSize;                     /**< The size of the free block. */\n} BlockLink_t;\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Called automatically to setup the required heap structures the first\n * time pvPortMalloc() is called.\n */\nstatic void prvHeapInit( void );\n\n/**\n * @brief Inserts a block of memory that is being freed into the correct\n * position in the list of free memory blocks.\n *\n * The block being freed will be merged with the block in front it and/or the\n * block behind it if the memory blocks are adjacent to each other.\n *\n * @param[in] pxBlockToInsert The block being freed.\n */\nstatic void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert );\n/*-----------------------------------------------------------*/\n\n/**\n * @brief The size of the structure placed at the beginning of each allocated\n * memory block must by correctly byte aligned.\n */\nstatic const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );\n\n/**\n * @brief Create a couple of list links to mark the start and end of the list.\n */\nstatic BlockLink_t xStart;\nstatic BlockLink_t * pxEnd = NULL;\n\n/**\n * @brief Keeps track of the number of free bytes remaining, but says nothing\n * about fragmentation.\n */\nstatic size_t xFreeBytesRemaining = 0U;\nstatic size_t xMinimumEverFreeBytesRemaining = 0U;\n\n/**\n * @brief Gets set to the top bit of an size_t type.\n *\n * When this bit in the xBlockSize member of an BlockLink_t structure is set\n * then the block belongs to the application. When the bit is free the block is\n * still part of the free heap space.\n */\nstatic size_t xBlockAllocatedBit = 0;\n/*-----------------------------------------------------------*/\n\nstatic void prvHeapInit( void )\n{\n    BlockLink_t * pxFirstFreeBlock;\n    uint8_t * pucAlignedHeap;\n    size_t uxAddress;\n    size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE;\n\n    /* Ensure the heap starts on a correctly aligned boundary. */\n    uxAddress = ( size_t ) ucHeap;\n\n    if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 )\n    {\n        uxAddress += ( secureportBYTE_ALIGNMENT - 1 );\n        uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );\n        xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;\n    }\n\n    pucAlignedHeap = ( uint8_t * ) uxAddress;\n\n    /* xStart is used to hold a pointer to the first item in the list of free\n     * blocks.  The void cast is used to prevent compiler warnings. */\n    xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;\n    xStart.xBlockSize = ( size_t ) 0;\n\n    /* pxEnd is used to mark the end of the list of free blocks and is inserted\n     * at the end of the heap space. */\n    uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;\n    uxAddress -= xHeapStructSize;\n    uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );\n    pxEnd = ( void * ) uxAddress;\n    pxEnd->xBlockSize = 0;\n    pxEnd->pxNextFreeBlock = NULL;\n\n    /* To start with there is a single free block that is sized to take up the\n     * entire heap space, minus the space taken by pxEnd. */\n    pxFirstFreeBlock = ( void * ) pucAlignedHeap;\n    pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;\n    pxFirstFreeBlock->pxNextFreeBlock = pxEnd;\n\n    /* Only one block exists - and it covers the entire usable heap space. */\n    xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;\n    xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;\n\n    /* Work out the position of the top bit in a size_t variable. */\n    xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert )\n{\n    BlockLink_t * pxIterator;\n    uint8_t * puc;\n\n    /* Iterate through the list until a block is found that has a higher address\n     * than the block being inserted. */\n    for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )\n    {\n        /* Nothing to do here, just iterate to the right position. */\n    }\n\n    /* Do the block being inserted, and the block it is being inserted after\n     * make a contiguous block of memory? */\n    puc = ( uint8_t * ) pxIterator;\n\n    if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )\n    {\n        pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;\n        pxBlockToInsert = pxIterator;\n    }\n    else\n    {\n        mtCOVERAGE_TEST_MARKER();\n    }\n\n    /* Do the block being inserted, and the block it is being inserted before\n     * make a contiguous block of memory? */\n    puc = ( uint8_t * ) pxBlockToInsert;\n\n    if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )\n    {\n        if( pxIterator->pxNextFreeBlock != pxEnd )\n        {\n            /* Form one big block from the two blocks. */\n            pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;\n            pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;\n        }\n        else\n        {\n            pxBlockToInsert->pxNextFreeBlock = pxEnd;\n        }\n    }\n    else\n    {\n        pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;\n    }\n\n    /* If the block being inserted plugged a gab, so was merged with the block\n     * before and the block after, then it's pxNextFreeBlock pointer will have\n     * already been set, and should not be set here as that would make it point\n     * to itself. */\n    if( pxIterator != pxBlockToInsert )\n    {\n        pxIterator->pxNextFreeBlock = pxBlockToInsert;\n    }\n    else\n    {\n        mtCOVERAGE_TEST_MARKER();\n    }\n}\n/*-----------------------------------------------------------*/\n\nvoid * pvPortMalloc( size_t xWantedSize )\n{\n    BlockLink_t * pxBlock;\n    BlockLink_t * pxPreviousBlock;\n    BlockLink_t * pxNewBlockLink;\n    void * pvReturn = NULL;\n\n    /* If this is the first call to malloc then the heap will require\n     * initialisation to setup the list of free blocks. */\n    if( pxEnd == NULL )\n    {\n        prvHeapInit();\n    }\n    else\n    {\n        mtCOVERAGE_TEST_MARKER();\n    }\n\n    /* Check the requested block size is not so large that the top bit is set.\n     * The top bit of the block size member of the BlockLink_t structure is used\n     * to determine who owns the block - the application or the kernel, so it\n     * must be free. */\n    if( ( xWantedSize & xBlockAllocatedBit ) == 0 )\n    {\n        /* The wanted size is increased so it can contain a BlockLink_t\n         * structure in addition to the requested amount of bytes. */\n        if( xWantedSize > 0 )\n        {\n            xWantedSize += xHeapStructSize;\n\n            /* Ensure that blocks are always aligned to the required number of\n             * bytes. */\n            if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )\n            {\n                /* Byte alignment required. */\n                xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );\n                secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n\n        if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )\n        {\n            /* Traverse the list from the start (lowest address) block until\n             * one of adequate size is found. */\n            pxPreviousBlock = &xStart;\n            pxBlock = xStart.pxNextFreeBlock;\n\n            while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )\n            {\n                pxPreviousBlock = pxBlock;\n                pxBlock = pxBlock->pxNextFreeBlock;\n            }\n\n            /* If the end marker was reached then a block of adequate size was\n             * not found. */\n            if( pxBlock != pxEnd )\n            {\n                /* Return the memory space pointed to - jumping over the\n                 * BlockLink_t structure at its start. */\n                pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );\n\n                /* This block is being returned for use so must be taken out\n                 * of the list of free blocks. */\n                pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;\n\n                /* If the block is larger than required it can be split into\n                 * two. */\n                if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE )\n                {\n                    /* This block is to be split into two.  Create a new\n                     * block following the number of bytes requested. The void\n                     * cast is used to prevent byte alignment warnings from the\n                     * compiler. */\n                    pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );\n                    secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 );\n\n                    /* Calculate the sizes of two blocks split from the single\n                     * block. */\n                    pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;\n                    pxBlock->xBlockSize = xWantedSize;\n\n                    /* Insert the new block into the list of free blocks. */\n                    prvInsertBlockIntoFreeList( pxNewBlockLink );\n                }\n                else\n                {\n                    mtCOVERAGE_TEST_MARKER();\n                }\n\n                xFreeBytesRemaining -= pxBlock->xBlockSize;\n\n                if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )\n                {\n                    xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;\n                }\n                else\n                {\n                    mtCOVERAGE_TEST_MARKER();\n                }\n\n                /* The block is being returned - it is allocated and owned by\n                 * the application and has no \"next\" block. */\n                pxBlock->xBlockSize |= xBlockAllocatedBit;\n                pxBlock->pxNextFreeBlock = NULL;\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n    }\n    else\n    {\n        mtCOVERAGE_TEST_MARKER();\n    }\n\n    traceMALLOC( pvReturn, xWantedSize );\n\n    #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )\n        {\n            if( pvReturn == NULL )\n            {\n                extern void vApplicationMallocFailedHook( void );\n                vApplicationMallocFailedHook();\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n    #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */\n\n    secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );\n    return pvReturn;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortFree( void * pv )\n{\n    uint8_t * puc = ( uint8_t * ) pv;\n    BlockLink_t * pxLink;\n\n    if( pv != NULL )\n    {\n        /* The memory being freed will have an BlockLink_t structure immediately\n         * before it. */\n        puc -= xHeapStructSize;\n\n        /* This casting is to keep the compiler from issuing warnings. */\n        pxLink = ( void * ) puc;\n\n        /* Check the block is actually allocated. */\n        secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );\n        secureportASSERT( pxLink->pxNextFreeBlock == NULL );\n\n        if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )\n        {\n            if( pxLink->pxNextFreeBlock == NULL )\n            {\n                /* The block is being returned to the heap - it is no longer\n                 * allocated. */\n                pxLink->xBlockSize &= ~xBlockAllocatedBit;\n\n                secureportDISABLE_NON_SECURE_INTERRUPTS();\n                {\n                    /* Add this block to the list of free blocks. */\n                    xFreeBytesRemaining += pxLink->xBlockSize;\n                    traceFREE( pv, pxLink->xBlockSize );\n                    prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );\n                }\n                secureportENABLE_NON_SECURE_INTERRUPTS();\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n    }\n}\n/*-----------------------------------------------------------*/\n\nsize_t xPortGetFreeHeapSize( void )\n{\n    return xFreeBytesRemaining;\n}\n/*-----------------------------------------------------------*/\n\nsize_t xPortGetMinimumEverFreeHeapSize( void )\n{\n    return xMinimumEverFreeBytesRemaining;\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM85/secure/secure_heap.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef __SECURE_HEAP_H__\n#define __SECURE_HEAP_H__\n\n/* Standard includes. */\n#include <stdlib.h>\n\n/**\n * @brief Allocates memory from heap.\n *\n * @param[in] xWantedSize The size of the memory to be allocated.\n *\n * @return Pointer to the memory region if the allocation is successful, NULL\n * otherwise.\n */\nvoid * pvPortMalloc( size_t xWantedSize );\n\n/**\n * @brief Frees the previously allocated memory.\n *\n * @param[in] pv Pointer to the memory to be freed.\n */\nvoid vPortFree( void * pv );\n\n/**\n * @brief Get the free heap size.\n *\n * @return Free heap size.\n */\nsize_t xPortGetFreeHeapSize( void );\n\n/**\n * @brief Get the minimum ever free heap size.\n *\n * @return Minimum ever free heap size.\n */\nsize_t xPortGetMinimumEverFreeHeapSize( void );\n\n#endif /* __SECURE_HEAP_H__ */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM85/secure/secure_init.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Standard includes. */\n#include <stdint.h>\n\n/* Secure init includes. */\n#include \"secure_init.h\"\n\n/* Secure port macros. */\n#include \"secure_port_macros.h\"\n\n/**\n * @brief Constants required to manipulate the SCB.\n */\n#define secureinitSCB_AIRCR                 ( ( volatile uint32_t * ) 0xe000ed0c )  /* Application Interrupt and Reset Control Register. */\n#define secureinitSCB_AIRCR_VECTKEY_POS     ( 16UL )\n#define secureinitSCB_AIRCR_VECTKEY_MASK    ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )\n#define secureinitSCB_AIRCR_PRIS_POS        ( 14UL )\n#define secureinitSCB_AIRCR_PRIS_MASK       ( 1UL << secureinitSCB_AIRCR_PRIS_POS )\n\n/**\n * @brief Constants required to manipulate the FPU.\n */\n#define secureinitFPCCR                     ( ( volatile uint32_t * ) 0xe000ef34 )  /* Floating Point Context Control Register. */\n#define secureinitFPCCR_LSPENS_POS          ( 29UL )\n#define secureinitFPCCR_LSPENS_MASK         ( 1UL << secureinitFPCCR_LSPENS_POS )\n#define secureinitFPCCR_TS_POS              ( 26UL )\n#define secureinitFPCCR_TS_MASK             ( 1UL << secureinitFPCCR_TS_POS )\n\n#define secureinitNSACR                     ( ( volatile uint32_t * ) 0xe000ed8c )  /* Non-secure Access Control Register. */\n#define secureinitNSACR_CP10_POS            ( 10UL )\n#define secureinitNSACR_CP10_MASK           ( 1UL << secureinitNSACR_CP10_POS )\n#define secureinitNSACR_CP11_POS            ( 11UL )\n#define secureinitNSACR_CP11_MASK           ( 1UL << secureinitNSACR_CP11_POS )\n/*-----------------------------------------------------------*/\n\nsecureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void )\n{\n    uint32_t ulIPSR;\n\n    /* Read the Interrupt Program Status Register (IPSR) value. */\n    secureportREAD_IPSR( ulIPSR );\n\n    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\n     * when the processor is running in the Thread Mode. */\n    if( ulIPSR != 0 )\n    {\n        *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |\n                                   ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |\n                                   ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK );\n    }\n}\n/*-----------------------------------------------------------*/\n\nsecureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )\n{\n    uint32_t ulIPSR;\n\n    /* Read the Interrupt Program Status Register (IPSR) value. */\n    secureportREAD_IPSR( ulIPSR );\n\n    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\n     * when the processor is running in the Thread Mode. */\n    if( ulIPSR != 0 )\n    {\n        /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is\n         * permitted. CP11 should be programmed to the same value as CP10. */\n        *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );\n\n        /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures\n         * that we can enable/disable lazy stacking in port.c file. */\n        *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK );\n\n        /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP\n         * registers (S16-S31) are also pushed to stack on exception entry and\n         * restored on exception return. */\n        *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );\n    }\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM85/secure/secure_init.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef __SECURE_INIT_H__\n#define __SECURE_INIT_H__\n\n/**\n * @brief De-prioritizes the non-secure exceptions.\n *\n * This is needed to ensure that the non-secure PendSV runs at the lowest\n * priority. Context switch is done in the non-secure PendSV handler.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n */\nvoid SecureInit_DePrioritizeNSExceptions( void );\n\n/**\n * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access.\n *\n * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point\n * Registers are not leaked to the non-secure side.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n */\nvoid SecureInit_EnableNSFPUAccess( void );\n\n#endif /* __SECURE_INIT_H__ */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM85/secure/secure_port_macros.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef __SECURE_PORT_MACROS_H__\n#define __SECURE_PORT_MACROS_H__\n\n/**\n * @brief Byte alignment requirements.\n */\n#define secureportBYTE_ALIGNMENT         8\n#define secureportBYTE_ALIGNMENT_MASK    ( 0x0007 )\n\n/**\n * @brief Macro to declare a function as non-secure callable.\n */\n#if defined( __IAR_SYSTEMS_ICC__ )\n    #define secureportNON_SECURE_CALLABLE    __cmse_nonsecure_entry __root\n#else\n    #define secureportNON_SECURE_CALLABLE    __attribute__( ( cmse_nonsecure_entry ) ) __attribute__( ( used ) )\n#endif\n\n/**\n * @brief Set the secure PRIMASK value.\n */\n#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \\\n    __asm volatile ( \"msr primask, %0\" : : \"r\" ( ulPrimaskValue ) : \"memory\" )\n\n/**\n * @brief Set the non-secure PRIMASK value.\n */\n#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \\\n    __asm volatile ( \"msr primask_ns, %0\" : : \"r\" ( ulPrimaskValue ) : \"memory\" )\n\n/**\n * @brief Read the PSP value in the given variable.\n */\n#define secureportREAD_PSP( pucOutCurrentStackPointer ) \\\n    __asm volatile ( \"mrs %0, psp\"  : \"=r\" ( pucOutCurrentStackPointer ) )\n\n/**\n * @brief Set the PSP to the given value.\n */\n#define secureportSET_PSP( pucCurrentStackPointer ) \\\n    __asm volatile ( \"msr psp, %0\" : : \"r\" ( pucCurrentStackPointer ) )\n\n/**\n * @brief Read the PSPLIM value in the given variable.\n */\n#define secureportREAD_PSPLIM( pucOutStackLimit ) \\\n    __asm volatile ( \"mrs %0, psplim\"  : \"=r\" ( pucOutStackLimit ) )\n\n/**\n * @brief Set the PSPLIM to the given value.\n */\n#define secureportSET_PSPLIM( pucStackLimit ) \\\n    __asm volatile ( \"msr psplim, %0\" : : \"r\" ( pucStackLimit ) )\n\n/**\n * @brief Set the NonSecure MSP to the given value.\n */\n#define secureportSET_MSP_NS( pucMainStackPointer ) \\\n    __asm volatile ( \"msr msp_ns, %0\" : : \"r\" ( pucMainStackPointer ) )\n\n/**\n * @brief Set the CONTROL register to the given value.\n */\n#define secureportSET_CONTROL( ulControl ) \\\n    __asm volatile ( \"msr control, %0\" : : \"r\" ( ulControl ) : \"memory\" )\n\n/**\n * @brief Read the Interrupt Program Status Register (IPSR) value in the given\n * variable.\n */\n#define secureportREAD_IPSR( ulIPSR ) \\\n    __asm volatile ( \"mrs %0, ipsr\"  : \"=r\" ( ulIPSR ) )\n\n/**\n * @brief PRIMASK value to enable interrupts.\n */\n#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL     0\n\n/**\n * @brief PRIMASK value to disable interrupts.\n */\n#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL    1\n\n/**\n * @brief Disable secure interrupts.\n */\n#define secureportDISABLE_SECURE_INTERRUPTS()        secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )\n\n/**\n * @brief Disable non-secure interrupts.\n *\n * This effectively disables context switches.\n */\n#define secureportDISABLE_NON_SECURE_INTERRUPTS()    secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )\n\n/**\n * @brief Enable non-secure interrupts.\n */\n#define secureportENABLE_NON_SECURE_INTERRUPTS()     secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL )\n\n/**\n * @brief Assert definition.\n */\n#define secureportASSERT( x )                      \\\n    if( ( x ) == 0 )                               \\\n    {                                              \\\n        secureportDISABLE_SECURE_INTERRUPTS();     \\\n        secureportDISABLE_NON_SECURE_INTERRUPTS(); \\\n        for( ; ; ) {; }                            \\\n    }\n\n#endif /* __SECURE_PORT_MACROS_H__ */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM85_NTZ/non_secure/port.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\n * all the API functions to use the MPU wrappers. That should only be done when\n * task.h is included from an application file. */\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n/* MPU wrappers includes. */\n#include \"mpu_wrappers.h\"\n\n/* Portasm includes. */\n#include \"portasm.h\"\n\n#if ( configENABLE_TRUSTZONE == 1 )\n    /* Secure components includes. */\n    #include \"secure_context.h\"\n    #include \"secure_init.h\"\n#endif /* configENABLE_TRUSTZONE */\n\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/**\n * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only\n * i.e. the processor boots as secure and never jumps to the non-secure side.\n * The Trust Zone support in the port must be disabled in order to run FreeRTOS\n * on the secure side. The following are the valid configuration seetings:\n *\n * 1. Run FreeRTOS on the Secure Side:\n *    configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0\n *\n * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:\n *    configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1\n *\n * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:\n *    configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0\n */\n#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )\n    #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.\n#endif\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the NVIC.\n */\n#define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )\n#define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )\n#define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )\n#define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )\n#define portNVIC_SYSTICK_ENABLE_BIT           ( 1UL << 0UL )\n#define portNVIC_SYSTICK_INT_BIT              ( 1UL << 1UL )\n#define portNVIC_SYSTICK_CLK_BIT              ( 1UL << 2UL )\n#define portNVIC_SYSTICK_COUNT_FLAG_BIT       ( 1UL << 16UL )\n#define portNVIC_PEND_SYSTICK_CLEAR_BIT       ( 1UL << 25UL )\n#define portNVIC_PEND_SYSTICK_SET_BIT         ( 1UL << 26UL )\n#define portMIN_INTERRUPT_PRIORITY            ( 255UL )\n#define portNVIC_PENDSV_PRI                   ( portMIN_INTERRUPT_PRIORITY << 16UL )\n#define portNVIC_SYSTICK_PRI                  ( portMIN_INTERRUPT_PRIORITY << 24UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the SCB.\n */\n#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( volatile uint32_t * ) 0xe000ed24 )\n#define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the FPU.\n */\n#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 )              /* Coprocessor Access Control Register. */\n#define portCPACR_CP10_VALUE    ( 3UL )\n#define portCPACR_CP11_VALUE    portCPACR_CP10_VALUE\n#define portCPACR_CP10_POS      ( 20UL )\n#define portCPACR_CP11_POS      ( 22UL )\n\n#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 )              /* Floating Point Context Control Register. */\n#define portFPCCR_ASPEN_POS     ( 31UL )\n#define portFPCCR_ASPEN_MASK    ( 1UL << portFPCCR_ASPEN_POS )\n#define portFPCCR_LSPEN_POS     ( 30UL )\n#define portFPCCR_LSPEN_MASK    ( 1UL << portFPCCR_LSPEN_POS )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the MPU.\n */\n#define portMPU_TYPE_REG                      ( *( ( volatile uint32_t * ) 0xe000ed90 ) )\n#define portMPU_CTRL_REG                      ( *( ( volatile uint32_t * ) 0xe000ed94 ) )\n#define portMPU_RNR_REG                       ( *( ( volatile uint32_t * ) 0xe000ed98 ) )\n\n#define portMPU_RBAR_REG                      ( *( ( volatile uint32_t * ) 0xe000ed9c ) )\n#define portMPU_RLAR_REG                      ( *( ( volatile uint32_t * ) 0xe000eda0 ) )\n\n#define portMPU_RBAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda4 ) )\n#define portMPU_RLAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda8 ) )\n\n#define portMPU_RBAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edac ) )\n#define portMPU_RLAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edb0 ) )\n\n#define portMPU_RBAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb4 ) )\n#define portMPU_RLAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb8 ) )\n\n#define portMPU_MAIR0_REG                     ( *( ( volatile uint32_t * ) 0xe000edc0 ) )\n#define portMPU_MAIR1_REG                     ( *( ( volatile uint32_t * ) 0xe000edc4 ) )\n\n#define portMPU_RBAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */\n#define portMPU_RLAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */\n\n#define portMPU_MAIR_ATTR0_POS                ( 0UL )\n#define portMPU_MAIR_ATTR0_MASK               ( 0x000000ff )\n\n#define portMPU_MAIR_ATTR1_POS                ( 8UL )\n#define portMPU_MAIR_ATTR1_MASK               ( 0x0000ff00 )\n\n#define portMPU_MAIR_ATTR2_POS                ( 16UL )\n#define portMPU_MAIR_ATTR2_MASK               ( 0x00ff0000 )\n\n#define portMPU_MAIR_ATTR3_POS                ( 24UL )\n#define portMPU_MAIR_ATTR3_MASK               ( 0xff000000 )\n\n#define portMPU_MAIR_ATTR4_POS                ( 0UL )\n#define portMPU_MAIR_ATTR4_MASK               ( 0x000000ff )\n\n#define portMPU_MAIR_ATTR5_POS                ( 8UL )\n#define portMPU_MAIR_ATTR5_MASK               ( 0x0000ff00 )\n\n#define portMPU_MAIR_ATTR6_POS                ( 16UL )\n#define portMPU_MAIR_ATTR6_MASK               ( 0x00ff0000 )\n\n#define portMPU_MAIR_ATTR7_POS                ( 24UL )\n#define portMPU_MAIR_ATTR7_MASK               ( 0xff000000 )\n\n#define portMPU_RLAR_ATTR_INDEX0              ( 0UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX1              ( 1UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX2              ( 2UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX3              ( 3UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX4              ( 4UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX5              ( 5UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX6              ( 6UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX7              ( 7UL << 1UL )\n\n#define portMPU_RLAR_REGION_ENABLE            ( 1UL )\n\n/* Enable privileged access to unmapped region. */\n#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )\n\n/* Enable MPU. */\n#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )\n\n/* Expected value of the portMPU_TYPE register. */\n#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief The maximum 24-bit number.\n *\n * It is needed because the systick is a 24-bit counter.\n */\n#define portMAX_24_BIT_NUMBER       ( 0xffffffUL )\n\n/**\n * @brief A fiddle factor to estimate the number of SysTick counts that would\n * have occurred while the SysTick counter is stopped during tickless idle\n * calculations.\n */\n#define portMISSED_COUNTS_FACTOR    ( 94UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to set up the initial stack.\n */\n#define portINITIAL_XPSR    ( 0x01000000 )\n\n#if ( configRUN_FREERTOS_SECURE_ONLY == 1 )\n\n/**\n * @brief Initial EXC_RETURN value.\n *\n *     FF         FF         FF         FD\n * 1111 1111  1111 1111  1111 1111  1111 1101\n *\n * Bit[6] - 1 --> The exception was taken from the Secure state.\n * Bit[5] - 1 --> Do not skip stacking of additional state context.\n * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\n * Bit[3] - 1 --> Return to the Thread mode.\n * Bit[2] - 1 --> Restore registers from the process stack.\n * Bit[1] - 0 --> Reserved, 0.\n * Bit[0] - 1 --> The exception was taken to the Secure state.\n */\n    #define portINITIAL_EXC_RETURN    ( 0xfffffffd )\n#else\n\n/**\n * @brief Initial EXC_RETURN value.\n *\n *     FF         FF         FF         BC\n * 1111 1111  1111 1111  1111 1111  1011 1100\n *\n * Bit[6] - 0 --> The exception was taken from the Non-Secure state.\n * Bit[5] - 1 --> Do not skip stacking of additional state context.\n * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\n * Bit[3] - 1 --> Return to the Thread mode.\n * Bit[2] - 1 --> Restore registers from the process stack.\n * Bit[1] - 0 --> Reserved, 0.\n * Bit[0] - 0 --> The exception was taken to the Non-Secure state.\n */\n    #define portINITIAL_EXC_RETURN    ( 0xffffffbc )\n#endif /* configRUN_FREERTOS_SECURE_ONLY */\n\n/**\n * @brief CONTROL register privileged bit mask.\n *\n * Bit[0] in CONTROL register tells the privilege:\n *  Bit[0] = 0 ==> The task is privileged.\n *  Bit[0] = 1 ==> The task is not privileged.\n */\n#define portCONTROL_PRIVILEGED_MASK         ( 1UL << 0UL )\n\n/**\n * @brief Initial CONTROL register values.\n */\n#define portINITIAL_CONTROL_UNPRIVILEGED    ( 0x3 )\n#define portINITIAL_CONTROL_PRIVILEGED      ( 0x2 )\n\n/**\n * @brief Let the user override the default SysTick clock rate.  If defined by the\n * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the\n * configuration register.\n */\n#ifndef configSYSTICK_CLOCK_HZ\n    #define configSYSTICK_CLOCK_HZ             ( configCPU_CLOCK_HZ )\n    /* Ensure the SysTick is clocked at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( portNVIC_SYSTICK_CLK_BIT )\n#else\n    /* Select the option to clock SysTick not at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( 0 )\n#endif\n\n/**\n * @brief Let the user override the pre-loading of the initial LR with the\n * address of prvTaskExitError() in case it messes up unwinding of the stack\n * in the debugger.\n */\n#ifdef configTASK_RETURN_ADDRESS\n    #define portTASK_RETURN_ADDRESS    configTASK_RETURN_ADDRESS\n#else\n    #define portTASK_RETURN_ADDRESS    prvTaskExitError\n#endif\n\n/**\n * @brief If portPRELOAD_REGISTERS then registers will be given an initial value\n * when a task is created. This helps in debugging at the cost of code size.\n */\n#define portPRELOAD_REGISTERS    1\n\n/**\n * @brief A task is created without a secure context, and must call\n * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes\n * any secure calls.\n */\n#define portNO_SECURE_CONTEXT    0\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Used to catch tasks that attempt to return from their implementing\n * function.\n */\nstatic void prvTaskExitError( void );\n\n#if ( configENABLE_MPU == 1 )\n\n/**\n * @brief Setup the Memory Protection Unit (MPU).\n */\n    static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\n#endif /* configENABLE_MPU */\n\n#if ( configENABLE_FPU == 1 )\n\n/**\n * @brief Setup the Floating Point Unit (FPU).\n */\n    static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;\n#endif /* configENABLE_FPU */\n\n/**\n * @brief Setup the timer to generate the tick interrupts.\n *\n * The implementation in this file is weak to allow application writers to\n * change the timer used to generate the tick interrupt.\n */\nvoid vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Checks whether the current execution context is interrupt.\n *\n * @return pdTRUE if the current execution context is interrupt, pdFALSE\n * otherwise.\n */\nBaseType_t xPortIsInsideInterrupt( void );\n\n/**\n * @brief Yield the processor.\n */\nvoid vPortYield( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Enter critical section.\n */\nvoid vPortEnterCritical( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Exit from critical section.\n */\nvoid vPortExitCritical( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief SysTick handler.\n */\nvoid SysTick_Handler( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief C part of SVC handler.\n */\nportDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION;\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Each task maintains its own interrupt status in the critical nesting\n * variable.\n */\nPRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;\n\n#if ( configENABLE_TRUSTZONE == 1 )\n\n/**\n * @brief Saved as part of the task context to indicate which context the\n * task is using on the secure side.\n */\n    PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;\n#endif /* configENABLE_TRUSTZONE */\n\n#if ( configUSE_TICKLESS_IDLE == 1 )\n\n/**\n * @brief The number of SysTick increments that make up one tick period.\n */\n    PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0;\n\n/**\n * @brief The maximum number of tick periods that can be suppressed is\n * limited by the 24 bit resolution of the SysTick timer.\n */\n    PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0;\n\n/**\n * @brief Compensate for the CPU cycles that pass while the SysTick is\n * stopped (low power functionality only).\n */\n    PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TICKLESS_IDLE == 1 )\n    __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )\n    {\n        uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;\n        TickType_t xModifiableIdleTime;\n\n        /* Make sure the SysTick reload value does not overflow the counter. */\n        if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\n        {\n            xExpectedIdleTime = xMaximumPossibleSuppressedTicks;\n        }\n\n        /* Enter a critical section but don't use the taskENTER_CRITICAL()\n         * method as that will mask interrupts that should exit sleep mode. */\n        __asm volatile ( \"cpsid i\" ::: \"memory\" );\n        __asm volatile ( \"dsb\" );\n        __asm volatile ( \"isb\" );\n\n        /* If a context switch is pending or a task is waiting for the scheduler\n         * to be unsuspended then abandon the low power entry. */\n        if( eTaskConfirmSleepModeStatus() == eAbortSleep )\n        {\n            /* Re-enable interrupts - see comments above the cpsid instruction\n             * above. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n        }\n        else\n        {\n            /* Stop the SysTick momentarily.  The time the SysTick is stopped for\n             * is accounted for as best it can be, but using the tickless mode will\n             * inevitably result in some tiny drift of the time maintained by the\n             * kernel with respect to calendar time. */\n            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );\n\n            /* Use the SysTick current-value register to determine the number of\n             * SysTick decrements remaining until the next tick interrupt.  If the\n             * current-value register is zero, then there are actually\n             * ulTimerCountsForOneTick decrements remaining, not zero, because the\n             * SysTick requests the interrupt when decrementing from 1 to 0. */\n            ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n\n            if( ulSysTickDecrementsLeft == 0 )\n            {\n                ulSysTickDecrementsLeft = ulTimerCountsForOneTick;\n            }\n\n            /* Calculate the reload value required to wait xExpectedIdleTime\n             * tick periods.  -1 is used because this code normally executes part\n             * way through the first tick period.  But if the SysTick IRQ is now\n             * pending, then clear the IRQ, suppressing the first tick, and correct\n             * the reload value to reflect that the second tick period is already\n             * underway.  The expected idle time is always at least two ticks. */\n            ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );\n\n            if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )\n            {\n                portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;\n                ulReloadValue -= ulTimerCountsForOneTick;\n            }\n\n            if( ulReloadValue > ulStoppedTimerCompensation )\n            {\n                ulReloadValue -= ulStoppedTimerCompensation;\n            }\n\n            /* Set the new reload value. */\n            portNVIC_SYSTICK_LOAD_REG = ulReloadValue;\n\n            /* Clear the SysTick count flag and set the count value back to\n             * zero. */\n            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n            /* Restart SysTick. */\n            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\n\n            /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can\n             * set its parameter to 0 to indicate that its implementation contains\n             * its own wait for interrupt or wait for event instruction, and so wfi\n             * should not be executed again.  However, the original expected idle\n             * time variable must remain unmodified, so a copy is taken. */\n            xModifiableIdleTime = xExpectedIdleTime;\n            configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\n\n            if( xModifiableIdleTime > 0 )\n            {\n                __asm volatile ( \"dsb\" ::: \"memory\" );\n                __asm volatile ( \"wfi\" );\n                __asm volatile ( \"isb\" );\n            }\n\n            configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\n\n            /* Re-enable interrupts to allow the interrupt that brought the MCU\n             * out of sleep mode to execute immediately.  See comments above\n             * the cpsid instruction above. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n            __asm volatile ( \"dsb\" );\n            __asm volatile ( \"isb\" );\n\n            /* Disable interrupts again because the clock is about to be stopped\n             * and interrupts that execute while the clock is stopped will increase\n             * any slippage between the time maintained by the RTOS and calendar\n             * time. */\n            __asm volatile ( \"cpsid i\" ::: \"memory\" );\n            __asm volatile ( \"dsb\" );\n            __asm volatile ( \"isb\" );\n\n            /* Disable the SysTick clock without reading the\n             * portNVIC_SYSTICK_CTRL_REG register to ensure the\n             * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,\n             * the time the SysTick is stopped for is accounted for as best it can\n             * be, but using the tickless mode will inevitably result in some tiny\n             * drift of the time maintained by the kernel with respect to calendar\n             * time*/\n            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );\n\n            /* Determine whether the SysTick has already counted to zero. */\n            if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n            {\n                uint32_t ulCalculatedLoadValue;\n\n                /* The tick interrupt ended the sleep (or is now pending), and\n                 * a new tick period has started.  Reset portNVIC_SYSTICK_LOAD_REG\n                 * with whatever remains of the new tick period. */\n                ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\n\n                /* Don't allow a tiny value, or values that have somehow\n                 * underflowed because the post sleep hook did something\n                 * that took too long or because the SysTick current-value register\n                 * is zero. */\n                if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )\n                {\n                    ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );\n                }\n\n                portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;\n\n                /* As the pending tick will be processed as soon as this\n                 * function exits, the tick value maintained by the tick is stepped\n                 * forward by one less than the time spent waiting. */\n                ulCompleteTickPeriods = xExpectedIdleTime - 1UL;\n            }\n            else\n            {\n                /* Something other than the tick interrupt ended the sleep. */\n\n                /* Use the SysTick current-value register to determine the\n                 * number of SysTick decrements remaining until the expected idle\n                 * time would have ended. */\n                ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n                #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )\n                {\n                    /* If the SysTick is not using the core clock, the current-\n                     * value register might still be zero here.  In that case, the\n                     * SysTick didn't load from the reload register, and there are\n                     * ulReloadValue decrements remaining in the expected idle\n                     * time, not zero. */\n                    if( ulSysTickDecrementsLeft == 0 )\n                    {\n                        ulSysTickDecrementsLeft = ulReloadValue;\n                    }\n                }\n                #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */\n\n                /* Work out how long the sleep lasted rounded to complete tick\n                 * periods (not the ulReload value which accounted for part\n                 * ticks). */\n                ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;\n\n                /* How many complete tick periods passed while the processor\n                 * was waiting? */\n                ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;\n\n                /* The reload value is set to whatever fraction of a single tick\n                 * period remains. */\n                portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;\n            }\n\n            /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,\n             * then set portNVIC_SYSTICK_LOAD_REG back to its standard value.  If\n             * the SysTick is not using the core clock, temporarily configure it to\n             * use the core clock.  This configuration forces the SysTick to load\n             * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next\n             * cycle of the other clock.  Then portNVIC_SYSTICK_LOAD_REG is ready\n             * to receive the standard value immediately. */\n            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n            portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n            #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )\n            {\n                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n            }\n            #else\n            {\n                /* The temporary usage of the core clock has served its purpose,\n                 * as described above.  Resume usage of the other clock. */\n                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\n\n                if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n                {\n                    /* The partial tick period already ended.  Be sure the SysTick\n                     * counts it only once. */\n                    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;\n                }\n\n                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n            }\n            #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */\n\n            /* Step the tick to account for any tick periods that elapsed. */\n            vTaskStepTick( ulCompleteTickPeriods );\n\n            /* Exit with interrupts enabled. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n        }\n    }\n#endif /* configUSE_TICKLESS_IDLE */\n/*-----------------------------------------------------------*/\n\n__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Calculate the constants required to configure the tick interrupt. */\n    #if ( configUSE_TICKLESS_IDLE == 1 )\n    {\n        ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );\n        xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;\n        ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\n    }\n    #endif /* configUSE_TICKLESS_IDLE */\n\n    /* Stop and reset the SysTick. */\n    portNVIC_SYSTICK_CTRL_REG = 0UL;\n    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n    /* Configure SysTick to interrupt at the requested rate. */\n    portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\n    portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvTaskExitError( void )\n{\n    volatile uint32_t ulDummy = 0UL;\n\n    /* A function that implements a task must not exit or attempt to return to\n     * its caller as there is nothing to return to. If a task wants to exit it\n     * should instead call vTaskDelete( NULL ). Artificially force an assert()\n     * to be triggered if configASSERT() is defined, then stop here so\n     * application writers can catch the error. */\n    configASSERT( ulCriticalNesting == ~0UL );\n    portDISABLE_INTERRUPTS();\n\n    while( ulDummy == 0 )\n    {\n        /* This file calls prvTaskExitError() after the scheduler has been\n         * started to remove a compiler warning about the function being\n         * defined but never called.  ulDummy is used purely to quieten other\n         * warnings about code appearing after this function is called - making\n         * ulDummy volatile makes the compiler think the function could return\n         * and therefore not output an 'unreachable code' warning for code that\n         * appears after it. */\n    }\n}\n/*-----------------------------------------------------------*/\n\n#if ( configENABLE_MPU == 1 )\n    static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */\n    {\n        #if defined( __ARMCC_VERSION )\n\n            /* Declaration when these variable are defined in code instead of being\n             * exported from linker scripts. */\n            extern uint32_t * __privileged_functions_start__;\n            extern uint32_t * __privileged_functions_end__;\n            extern uint32_t * __syscalls_flash_start__;\n            extern uint32_t * __syscalls_flash_end__;\n            extern uint32_t * __unprivileged_flash_start__;\n            extern uint32_t * __unprivileged_flash_end__;\n            extern uint32_t * __privileged_sram_start__;\n            extern uint32_t * __privileged_sram_end__;\n        #else /* if defined( __ARMCC_VERSION ) */\n            /* Declaration when these variable are exported from linker scripts. */\n            extern uint32_t __privileged_functions_start__[];\n            extern uint32_t __privileged_functions_end__[];\n            extern uint32_t __syscalls_flash_start__[];\n            extern uint32_t __syscalls_flash_end__[];\n            extern uint32_t __unprivileged_flash_start__[];\n            extern uint32_t __unprivileged_flash_end__[];\n            extern uint32_t __privileged_sram_start__[];\n            extern uint32_t __privileged_sram_end__[];\n        #endif /* defined( __ARMCC_VERSION ) */\n\n        /* The only permitted number of regions are 8 or 16. */\n        configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );\n\n        /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */\n        configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );\n\n        /* Check that the MPU is present. */\n        if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )\n        {\n            /* MAIR0 - Index 0. */\n            portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\n            /* MAIR0 - Index 1. */\n            portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\n\n            /* Setup privileged flash as Read Only so that privileged tasks can\n             * read it but not modify. */\n            portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_PRIVILEGED_READ_ONLY );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Setup unprivileged flash as Read Only by both privileged and\n             * unprivileged tasks. All tasks can read it but no-one can modify. */\n            portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_READ_ONLY );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Setup unprivileged syscalls flash as Read Only by both privileged\n             * and unprivileged tasks. All tasks can read it but no-one can modify. */\n            portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_READ_ONLY );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Setup RAM containing kernel data for privileged access only. */\n            portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\n                               ( portMPU_REGION_EXECUTE_NEVER );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Enable mem fault. */\n            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;\n\n            /* Enable MPU with privileged background access i.e. unmapped\n             * regions have privileged access. */\n            portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );\n        }\n    }\n#endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\n#if ( configENABLE_FPU == 1 )\n    static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */\n    {\n        #if ( configENABLE_TRUSTZONE == 1 )\n        {\n            /* Enable non-secure access to the FPU. */\n            SecureInit_EnableNSFPUAccess();\n        }\n        #endif /* configENABLE_TRUSTZONE */\n\n        /* CP10 = 11 ==> Full access to FPU i.e. both privileged and\n         * unprivileged code should be able to access FPU. CP11 should be\n         * programmed to the same value as CP10. */\n        *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |\n                            ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )\n                            );\n\n        /* ASPEN = 1 ==> Hardware should automatically preserve floating point\n         * context on exception entry and restore on exception return.\n         * LSPEN = 1 ==> Enable lazy context save of FP state. */\n        *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );\n    }\n#endif /* configENABLE_FPU */\n/*-----------------------------------------------------------*/\n\nvoid vPortYield( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Set a PendSV to request a context switch. */\n    portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\n\n    /* Barriers are normally not required but do ensure the code is\n     * completely within the specified behaviour for the architecture. */\n    __asm volatile ( \"dsb\" ::: \"memory\" );\n    __asm volatile ( \"isb\" );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */\n{\n    portDISABLE_INTERRUPTS();\n    ulCriticalNesting++;\n\n    /* Barriers are normally not required but do ensure the code is\n     * completely within the specified behaviour for the architecture. */\n    __asm volatile ( \"dsb\" ::: \"memory\" );\n    __asm volatile ( \"isb\" );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */\n{\n    configASSERT( ulCriticalNesting );\n    ulCriticalNesting--;\n\n    if( ulCriticalNesting == 0 )\n    {\n        portENABLE_INTERRUPTS();\n    }\n}\n/*-----------------------------------------------------------*/\n\nvoid SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */\n{\n    uint32_t ulPreviousMask;\n\n    ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();\n    {\n        /* Increment the RTOS tick. */\n        if( xTaskIncrementTick() != pdFALSE )\n        {\n            /* Pend a context switch. */\n            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\n        }\n    }\n    portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */\n{\n    #if ( configENABLE_MPU == 1 )\n        #if defined( __ARMCC_VERSION )\n\n            /* Declaration when these variable are defined in code instead of being\n             * exported from linker scripts. */\n            extern uint32_t * __syscalls_flash_start__;\n            extern uint32_t * __syscalls_flash_end__;\n        #else\n            /* Declaration when these variable are exported from linker scripts. */\n            extern uint32_t __syscalls_flash_start__[];\n            extern uint32_t __syscalls_flash_end__[];\n        #endif /* defined( __ARMCC_VERSION ) */\n    #endif /* configENABLE_MPU */\n\n    uint32_t ulPC;\n\n    #if ( configENABLE_TRUSTZONE == 1 )\n        uint32_t ulR0, ulR1;\n        extern TaskHandle_t pxCurrentTCB;\n        #if ( configENABLE_MPU == 1 )\n            uint32_t ulControl, ulIsTaskPrivileged;\n        #endif /* configENABLE_MPU */\n    #endif /* configENABLE_TRUSTZONE */\n    uint8_t ucSVCNumber;\n\n    /* Register are stored on the stack in the following order - R0, R1, R2, R3,\n     * R12, LR, PC, xPSR. */\n    ulPC = pulCallerStackAddress[ 6 ];\n    ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];\n\n    switch( ucSVCNumber )\n    {\n        #if ( configENABLE_TRUSTZONE == 1 )\n            case portSVC_ALLOCATE_SECURE_CONTEXT:\n\n                /* R0 contains the stack size passed as parameter to the\n                 * vPortAllocateSecureContext function. */\n                ulR0 = pulCallerStackAddress[ 0 ];\n\n                #if ( configENABLE_MPU == 1 )\n                {\n                    /* Read the CONTROL register value. */\n                    __asm volatile ( \"mrs %0, control\"  : \"=r\" ( ulControl ) );\n\n                    /* The task that raised the SVC is privileged if Bit[0]\n                     * in the CONTROL register is 0. */\n                    ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );\n\n                    /* Allocate and load a context for the secure task. */\n                    xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );\n                }\n                #else /* if ( configENABLE_MPU == 1 ) */\n                {\n                    /* Allocate and load a context for the secure task. */\n                    xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );\n                }\n                #endif /* configENABLE_MPU */\n\n                configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );\n                SecureContext_LoadContext( xSecureContext, pxCurrentTCB );\n                break;\n\n            case portSVC_FREE_SECURE_CONTEXT:\n\n                /* R0 contains TCB being freed and R1 contains the secure\n                 * context handle to be freed. */\n                ulR0 = pulCallerStackAddress[ 0 ];\n                ulR1 = pulCallerStackAddress[ 1 ];\n\n                /* Free the secure context. */\n                SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );\n                break;\n        #endif /* configENABLE_TRUSTZONE */\n\n        case portSVC_START_SCHEDULER:\n            #if ( configENABLE_TRUSTZONE == 1 )\n            {\n                /* De-prioritize the non-secure exceptions so that the\n                 * non-secure pendSV runs at the lowest priority. */\n                SecureInit_DePrioritizeNSExceptions();\n\n                /* Initialize the secure context management system. */\n                SecureContext_Init();\n            }\n            #endif /* configENABLE_TRUSTZONE */\n\n            #if ( configENABLE_FPU == 1 )\n            {\n                /* Setup the Floating Point Unit (FPU). */\n                prvSetupFPU();\n            }\n            #endif /* configENABLE_FPU */\n\n            /* Setup the context of the first task so that the first task starts\n             * executing. */\n            vRestoreContextOfFirstTask();\n            break;\n\n            #if ( configENABLE_MPU == 1 )\n                case portSVC_RAISE_PRIVILEGE:\n\n                    /* Only raise the privilege, if the svc was raised from any of\n                     * the system calls. */\n                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&\n                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )\n                    {\n                        vRaisePrivilege();\n                    }\n                    break;\n            #endif /* configENABLE_MPU */\n\n        default:\n            /* Incorrect SVC call. */\n            configASSERT( pdFALSE );\n    }\n}\n/*-----------------------------------------------------------*/\n/* *INDENT-OFF* */\n#if ( configENABLE_MPU == 1 )\n    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,\n                                         StackType_t * pxEndOfStack,\n                                         TaskFunction_t pxCode,\n                                         void * pvParameters,\n                                         BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */\n#else\n    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,\n                                         StackType_t * pxEndOfStack,\n                                         TaskFunction_t pxCode,\n                                         void * pvParameters ) /* PRIVILEGED_FUNCTION */\n#endif /* configENABLE_MPU */\n/* *INDENT-ON* */\n{\n    /* Simulate the stack frame as it would be created by a context switch\n     * interrupt. */\n    #if ( portPRELOAD_REGISTERS == 0 )\n    {\n        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\n        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\n        pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */\n        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */\n        pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */\n        *pxTopOfStack = portINITIAL_EXC_RETURN;\n\n        #if ( configENABLE_MPU == 1 )\n        {\n            pxTopOfStack--;\n\n            if( xRunPrivileged == pdTRUE )\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n            else\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n        }\n        #endif /* configENABLE_MPU */\n\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\n\n        #if ( configENABLE_TRUSTZONE == 1 )\n        {\n            pxTopOfStack--;\n            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\n        }\n        #endif /* configENABLE_TRUSTZONE */\n    }\n    #else /* portPRELOAD_REGISTERS */\n    {\n        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\n        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04 */\n        pxTopOfStack--;\n        *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN */\n\n        #if ( configENABLE_MPU == 1 )\n        {\n            pxTopOfStack--;\n\n            if( xRunPrivileged == pdTRUE )\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n            else\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n        }\n        #endif /* configENABLE_MPU */\n\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\n\n        #if ( configENABLE_TRUSTZONE == 1 )\n        {\n            pxTopOfStack--;\n            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\n        }\n        #endif /* configENABLE_TRUSTZONE */\n    }\n    #endif /* portPRELOAD_REGISTERS */\n\n    return pxTopOfStack;\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Make PendSV, CallSV and SysTick the same priority as the kernel. */\n    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;\n    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;\n\n    #if ( configENABLE_MPU == 1 )\n    {\n        /* Setup the Memory Protection Unit (MPU). */\n        prvSetupMPU();\n    }\n    #endif /* configENABLE_MPU */\n\n    /* Start the timer that generates the tick ISR. Interrupts are disabled\n     * here already. */\n    vPortSetupTimerInterrupt();\n\n    /* Initialize the critical nesting count ready for the first task. */\n    ulCriticalNesting = 0;\n\n    /* Start the first task. */\n    vStartFirstTask();\n\n    /* Should never get here as the tasks will now be executing. Call the task\n     * exit error function to prevent compiler warnings about a static function\n     * not being called in the case that the application writer overrides this\n     * functionality by defining configTASK_RETURN_ADDRESS. Call\n     * vTaskSwitchContext() so link time optimization does not remove the\n     * symbol. */\n    vTaskSwitchContext();\n    prvTaskExitError();\n\n    /* Should not get here. */\n    return 0;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Not implemented in ports where there is nothing to return to.\n     * Artificially force an assert. */\n    configASSERT( ulCriticalNesting == 1000UL );\n}\n/*-----------------------------------------------------------*/\n\n#if ( configENABLE_MPU == 1 )\n    void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,\n                                    const struct xMEMORY_REGION * const xRegions,\n                                    StackType_t * pxBottomOfStack,\n                                    uint32_t ulStackDepth )\n    {\n        uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;\n        int32_t lIndex = 0;\n\n        #if defined( __ARMCC_VERSION )\n\n            /* Declaration when these variable are defined in code instead of being\n             * exported from linker scripts. */\n            extern uint32_t * __privileged_sram_start__;\n            extern uint32_t * __privileged_sram_end__;\n        #else\n            /* Declaration when these variable are exported from linker scripts. */\n            extern uint32_t __privileged_sram_start__[];\n            extern uint32_t __privileged_sram_end__[];\n        #endif /* defined( __ARMCC_VERSION ) */\n\n        /* Setup MAIR0. */\n        xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\n        xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\n\n        /* This function is called automatically when the task is created - in\n         * which case the stack region parameters will be valid.  At all other\n         * times the stack parameters will not be valid and it is assumed that\n         * the stack region has already been configured. */\n        if( ulStackDepth > 0 )\n        {\n            ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;\n            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;\n\n            /* If the stack is within the privileged SRAM, do not protect it\n             * using a separate MPU region. This is needed because privileged\n             * SRAM is already protected using an MPU region and ARMv8-M does\n             * not allow overlapping MPU regions. */\n            if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) &&\n                ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) )\n            {\n                xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0;\n                xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0;\n            }\n            else\n            {\n                /* Define the region that allows access to the stack. */\n                ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK;\n                ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\n\n                xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |\n                                                             ( portMPU_REGION_NON_SHAREABLE ) |\n                                                             ( portMPU_REGION_READ_WRITE ) |\n                                                             ( portMPU_REGION_EXECUTE_NEVER );\n\n                xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) |\n                                                             ( portMPU_RLAR_ATTR_INDEX0 ) |\n                                                             ( portMPU_RLAR_REGION_ENABLE );\n            }\n        }\n\n        /* User supplied configurable regions. */\n        for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )\n        {\n            /* If xRegions is NULL i.e. the task has not specified any MPU\n             * region, the else part ensures that all the configurable MPU\n             * regions are invalidated. */\n            if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )\n            {\n                /* Translate the generic region definition contained in xRegions\n                 * into the ARMv8 specific MPU settings that are then stored in\n                 * xMPUSettings. */\n                ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;\n                ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;\n                ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\n\n                /* Start address. */\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |\n                                                                          ( portMPU_REGION_NON_SHAREABLE );\n\n                /* RO/RW. */\n                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )\n                {\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );\n                }\n                else\n                {\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );\n                }\n\n                /* XN. */\n                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )\n                {\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );\n                }\n\n                /* End Address. */\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |\n                                                                          ( portMPU_RLAR_REGION_ENABLE );\n\n                /* Normal memory/ Device memory. */\n                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )\n                {\n                    /* Attr1 in MAIR0 is configured as device memory. */\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;\n                }\n                else\n                {\n                    /* Attr0 in MAIR0 is configured as normal memory. */\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;\n                }\n            }\n            else\n            {\n                /* Invalidate the region. */\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;\n            }\n\n            lIndex++;\n        }\n    }\n#endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\nBaseType_t xPortIsInsideInterrupt( void )\n{\n    uint32_t ulCurrentInterrupt;\n    BaseType_t xReturn;\n\n    /* Obtain the number of the currently executing interrupt. Interrupt Program\n     * Status Register (IPSR) holds the exception number of the currently-executing\n     * exception or zero for Thread mode.*/\n    __asm volatile ( \"mrs %0, ipsr\" : \"=r\" ( ulCurrentInterrupt )::\"memory\" );\n\n    if( ulCurrentInterrupt == 0 )\n    {\n        xReturn = pdFALSE;\n    }\n    else\n    {\n        xReturn = pdTRUE;\n    }\n\n    return xReturn;\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Standard includes. */\n#include <stdint.h>\n\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION\n * is defined correctly and privileged functions are placed in correct sections. */\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/* Portasm includes. */\n#include \"portasm.h\"\n\n/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the\n * header files. */\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\nvoid vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr  r2, pxCurrentTCBConst2\t\t\t\t\t\t\\n\"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n        \"\tldr  r1, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Read pxCurrentTCB. */\n        \"\tldr  r0, [r1]\t\t\t\t\t\t\t\t\t\\n\"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"\tdmb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Complete outstanding transfers before disabling MPU. */\n            \"\tldr r2, xMPUCTRLConst2\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n            \"\tldr r4, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Read the value of MPU_CTRL. */\n            \"\tbic r4, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\n            \"\tstr r4, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Disable MPU. */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tadds r1, #4\t\t\t\t\t\t\t\t\t\t\\n\"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\n            \"\tldr  r3, [r1]\t\t\t\t\t\t\t\t\t\\n\"/* r3 = *r1 i.e. r3 = MAIR0. */\n            \"\tldr  r2, xMAIR0Const2\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000edc0 [Location of MAIR0]. */\n            \"\tstr  r3, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Program MAIR0. */\n            \"\tldr  r2, xRNRConst2\t\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed98 [Location of RNR]. */\n            \"\tmovs r3, #4\t\t\t\t\t\t\t\t\t\t\\n\"/* r3 = 4. */\n            \"\tstr  r3, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 4. */\n            \"\tadds r1, #4\t\t\t\t\t\t\t\t\t\t\\n\"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\n            \"\tldr  r2, xRBARConst2\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed9c [Location of RBAR]. */\n            \"\tldmia r1!, {r4-r11}\t\t\t\t\t\t\t\t\\n\"/* Read 4 set of RBAR/RLAR registers from TCB. */\n            \"\tstmia r2!, {r4-r11}\t\t\t\t\t\t\t\t\\n\"/* Write 4 set of RBAR/RLAR registers using alias registers. */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            #if ( configTOTAL_MPU_REGIONS == 16 )\n            \"\tldr  r2, xRNRConst2\t\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed98 [Location of RNR]. */\n            \"\tmovs r3, #8\t\t\t\t\t\t\t\t\t\t\\n\"/* r3 = 8. */\n            \"\tstr  r3, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 8. */\n            \"\tldr  r2, xRBARConst2\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed9c [Location of RBAR]. */\n            \"\tldmia r1!, {r4-r11}\t\t\t\t\t\t\t\t\\n\"/* Read 4 set of RBAR/RLAR registers from TCB. */\n            \"\tstmia r2!, {r4-r11}\t\t\t\t\t\t\t\t\\n\"/* Write 4 set of RBAR/RLAR registers using alias registers. */\n            \"\tldr  r2, xRNRConst2\t\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed98 [Location of RNR]. */\n            \"\tmovs r3, #12\t\t\t\t\t\t\t\t\t\\n\"/* r3 = 12. */\n            \"\tstr  r3, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 12. */\n            \"\tldr  r2, xRBARConst2\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed9c [Location of RBAR]. */\n            \"\tldmia r1!, {r4-r11}\t\t\t\t\t\t\t\t\\n\"/* Read 4 set of RBAR/RLAR registers from TCB. */\n            \"\tstmia r2!, {r4-r11}\t\t\t\t\t\t\t\t\\n\"/* Write 4 set of RBAR/RLAR registers using alias registers. */\n            #endif /* configTOTAL_MPU_REGIONS == 16 */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tldr r2, xMPUCTRLConst2\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n            \"\tldr r4, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Read the value of MPU_CTRL. */\n            \"\torr r4, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\n            \"\tstr r4, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Enable MPU. */\n            \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Force memory writes before continuing. */\n        #endif /* configENABLE_MPU */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"\tldm  r0!, {r1-r3}\t\t\t\t\t\t\t\t\\n\"/* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */\n            \"\tmsr  psplim, r1\t\t\t\t\t\t\t\t\t\\n\"/* Set this task's PSPLIM value. */\n            \"\tmsr  control, r2\t\t\t\t\t\t\t\t\\n\"/* Set this task's CONTROL value. */\n            \"\tadds r0, #32\t\t\t\t\t\t\t\t\t\\n\"/* Discard everything up to r0. */\n            \"\tmsr  psp, r0\t\t\t\t\t\t\t\t\t\\n\"/* This is now the new top of stack to use in the task. */\n            \"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tmov  r0, #0\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tmsr  basepri, r0\t\t\t\t\t\t\t\t\\n\"/* Ensure that interrupts are enabled when the first task starts. */\n            \"\tbx   r3\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Finally, branch to EXC_RETURN. */\n        #else /* configENABLE_MPU */\n            \"\tldm  r0!, {r1-r2}\t\t\t\t\t\t\t\t\\n\"/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */\n            \"\tmsr  psplim, r1\t\t\t\t\t\t\t\t\t\\n\"/* Set this task's PSPLIM value. */\n            \"\tmovs r1, #2\t\t\t\t\t\t\t\t\t\t\\n\"/* r1 = 2. */\n            \"\tmsr  CONTROL, r1\t\t\t\t\t\t\t\t\\n\"/* Switch to use PSP in the thread mode. */\n            \"\tadds r0, #32\t\t\t\t\t\t\t\t\t\\n\"/* Discard everything up to r0. */\n            \"\tmsr  psp, r0\t\t\t\t\t\t\t\t\t\\n\"/* This is now the new top of stack to use in the task. */\n            \"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tmov  r0, #0\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tmsr  basepri, r0\t\t\t\t\t\t\t\t\\n\"/* Ensure that interrupts are enabled when the first task starts. */\n            \"\tbx   r2\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Finally, branch to EXC_RETURN. */\n        #endif /* configENABLE_MPU */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.align 4\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"pxCurrentTCBConst2: .word pxCurrentTCB\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"xMPUCTRLConst2: .word 0xe000ed94\t\t\t\t\t\\n\"\n            \"xMAIR0Const2: .word 0xe000edc0\t\t\t\t\t\t\\n\"\n            \"xRNRConst2: .word 0xe000ed98\t\t\t\t\t\t\\n\"\n            \"xRBARConst2: .word 0xe000ed9c\t\t\t\t\t\t\\n\"\n        #endif /* configENABLE_MPU */\n    );\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrs r0, control\t\t\t\t\t\t\t\t\t\\n\"/* r0 = CONTROL. */\n        \"\ttst r0, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\n        \"\tite ne\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmovne r0, #0\t\t\t\t\t\t\t\t\t\\n\"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\n        \"\tmoveq r0, #1\t\t\t\t\t\t\t\t\t\\n\"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return. */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.align 4\t\t\t\t\t\t\t\t\t\t\\n\"\n        ::: \"r0\", \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrs  r0, control\t\t\t\t\t\t\t\t\\n\"/* Read the CONTROL register. */\n        \"\tbic r0, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* Clear the bit 0. */\n        \"\tmsr  control, r0\t\t\t\t\t\t\t\t\\n\"/* Write back the new CONTROL value. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return to the caller. */\n        ::: \"r0\", \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vResetPrivilege( void ) /* __attribute__ (( naked )) */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrs r0, control\t\t\t\t\t\t\t\t\t\\n\"/* r0 = CONTROL. */\n        \"\torr r0, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* r0 = r0 | 1. */\n        \"\tmsr control, r0\t\t\t\t\t\t\t\t\t\\n\"/* CONTROL = r0. */\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return to the caller. */\n        ::: \"r0\", \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r0, xVTORConst\t\t\t\t\t\t\t\t\\n\"/* Use the NVIC offset register to locate the stack. */\n        \"\tldr r0, [r0]\t\t\t\t\t\t\t\t\t\\n\"/* Read the VTOR register which gives the address of vector table. */\n        \"\tldr r0, [r0]\t\t\t\t\t\t\t\t\t\\n\"/* The first entry in vector table is stack pointer. */\n        \"\tmsr msp, r0\t\t\t\t\t\t\t\t\t\t\\n\"/* Set the MSP back to the start of the stack. */\n        \"\tcpsie i\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Globally enable interrupts. */\n        \"\tcpsie f\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tsvc %0\t\t\t\t\t\t\t\t\t\t\t\\n\"/* System call to start the first task. */\n        \"\tnop\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"   .align 4\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"xVTORConst: .word 0xe000ed08\t\t\t\t\t\t\\n\"\n        ::\"i\" ( portSVC_START_SCHEDULER ) : \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nuint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrs r0, basepri\t\t\t\t\t\t\t\t\t\\n\"/* r0 = basepri. Return original basepri value. */\n        \"\tmov r1, %0\t\t\t\t\t\t\t\t\t\t\\n\"/* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */\n        \"\tmsr basepri, r1\t\t\t\t\t\t\t\t\t\\n\"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */\n        \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return. */\n        ::\"i\" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmsr basepri, r0\t\t\t\t\t\t\t\t\t\\n\"/* basepri = ulMask. */\n        \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tbx lr\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Return. */\n        ::: \"memory\"\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrs r0, psp\t\t\t\t\t\t\t\t\t\t\\n\"/* Read PSP in r0. */\n        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )\n            \"\ttst lr, #0x10\t\t\t\t\t\t\t\t\t\\n\"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */\n            \"\tit eq\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tvstmdbeq r0!, {s16-s31}\t\t\t\t\t\t\t\\n\"/* Store the additional FP context registers which are not saved automatically. */\n        #endif /* configENABLE_FPU || configENABLE_MVE */\n        #if ( configENABLE_MPU == 1 )\n            \"\tmrs r1, psplim\t\t\t\t\t\t\t\t\t\\n\"/* r1 = PSPLIM. */\n            \"\tmrs r2, control\t\t\t\t\t\t\t\t\t\\n\"/* r2 = CONTROL. */\n            \"\tmov r3, lr\t\t\t\t\t\t\t\t\t\t\\n\"/* r3 = LR/EXC_RETURN. */\n            \"\tstmdb r0!, {r1-r11}\t\t\t\t\t\t\t\t\\n\"/* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */\n        #else /* configENABLE_MPU */\n            \"\tmrs r2, psplim\t\t\t\t\t\t\t\t\t\\n\"/* r2 = PSPLIM. */\n            \"\tmov r3, lr\t\t\t\t\t\t\t\t\t\t\\n\"/* r3 = LR/EXC_RETURN. */\n            \"\tstmdb r0!, {r2-r11}\t\t\t\t\t\t\t\t\\n\"/* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */\n        #endif /* configENABLE_MPU */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r2, pxCurrentTCBConst\t\t\t\t\t\t\\n\"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n        \"\tldr r1, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Read pxCurrentTCB. */\n        \"\tstr r0, [r1]\t\t\t\t\t\t\t\t\t\\n\"/* Save the new top of stack in TCB. */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmov r0, %0\t\t\t\t\t\t\t\t\t\t\\n\"/* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */\n        \"\tmsr basepri, r0\t\t\t\t\t\t\t\t\t\\n\"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */\n        \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tbl vTaskSwitchContext\t\t\t\t\t\t\t\\n\"\n        \"\tmov r0, #0\t\t\t\t\t\t\t\t\t\t\\n\"/* r0 = 0. */\n        \"\tmsr basepri, r0\t\t\t\t\t\t\t\t\t\\n\"/* Enable interrupts. */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r2, pxCurrentTCBConst\t\t\t\t\t\t\\n\"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n        \"\tldr r1, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Read pxCurrentTCB. */\n        \"\tldr r0, [r1]\t\t\t\t\t\t\t\t\t\\n\"/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"\tdmb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Complete outstanding transfers before disabling MPU. */\n            \"\tldr r2, xMPUCTRLConst\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n            \"\tldr r4, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Read the value of MPU_CTRL. */\n            \"\tbic r4, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\n            \"\tstr r4, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Disable MPU. */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tadds r1, #4\t\t\t\t\t\t\t\t\t\t\\n\"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\n            \"\tldr r3, [r1]\t\t\t\t\t\t\t\t\t\\n\"/* r3 = *r1 i.e. r3 = MAIR0. */\n            \"\tldr r2, xMAIR0Const\t\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000edc0 [Location of MAIR0]. */\n            \"\tstr r3, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Program MAIR0. */\n            \"\tldr r2, xRNRConst\t\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed98 [Location of RNR]. */\n            \"\tmovs r3, #4\t\t\t\t\t\t\t\t\t\t\\n\"/* r3 = 4. */\n            \"\tstr r3, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 4. */\n            \"\tadds r1, #4\t\t\t\t\t\t\t\t\t\t\\n\"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\n            \"\tldr r2, xRBARConst\t\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed9c [Location of RBAR]. */\n            \"\tldmia r1!, {r4-r11}\t\t\t\t\t\t\t\t\\n\"/* Read 4 sets of RBAR/RLAR registers from TCB. */\n            \"\tstmia r2!, {r4-r11}\t\t\t\t\t\t\t\t\\n\"/* Write 4 set of RBAR/RLAR registers using alias registers. */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            #if ( configTOTAL_MPU_REGIONS == 16 )\n            \"\tldr r2, xRNRConst\t\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed98 [Location of RNR]. */\n            \"\tmovs r3, #8\t\t\t\t\t\t\t\t\t\t\\n\"/* r3 = 8. */\n            \"\tstr r3, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 8. */\n            \"\tldr r2, xRBARConst\t\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed9c [Location of RBAR]. */\n            \"\tldmia r1!, {r4-r11}\t\t\t\t\t\t\t\t\\n\"/* Read 4 sets of RBAR/RLAR registers from TCB. */\n            \"\tstmia r2!, {r4-r11}\t\t\t\t\t\t\t\t\\n\"/* Write 4 set of RBAR/RLAR registers using alias registers. */\n            \"\tldr r2, xRNRConst\t\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed98 [Location of RNR]. */\n            \"\tmovs r3, #12\t\t\t\t\t\t\t\t\t\\n\"/* r3 = 12. */\n            \"\tstr r3, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Program RNR = 12. */\n            \"\tldr r2, xRBARConst\t\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed9c [Location of RBAR]. */\n            \"\tldmia r1!, {r4-r11}\t\t\t\t\t\t\t\t\\n\"/* Read 4 sets of RBAR/RLAR registers from TCB. */\n            \"\tstmia r2!, {r4-r11}\t\t\t\t\t\t\t\t\\n\"/* Write 4 set of RBAR/RLAR registers using alias registers. */\n            #endif /* configTOTAL_MPU_REGIONS == 16 */\n            \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tldr r2, xMPUCTRLConst\t\t\t\t\t\t\t\\n\"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n            \"\tldr r4, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Read the value of MPU_CTRL. */\n            \"\torr r4, #1\t\t\t\t\t\t\t\t\t\t\\n\"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\n            \"\tstr r4, [r2]\t\t\t\t\t\t\t\t\t\\n\"/* Enable MPU. */\n            \"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\\n\"/* Force memory writes before continuing. */\n        #endif /* configENABLE_MPU */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"\tldmia r0!, {r1-r11}\t\t\t\t\t\t\t\t\\n\"/* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */\n        #else /* configENABLE_MPU */\n            \"\tldmia r0!, {r2-r11}\t\t\t\t\t\t\t\t\\n\"/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */\n        #endif /* configENABLE_MPU */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )\n            \"\ttst r3, #0x10\t\t\t\t\t\t\t\t\t\\n\"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */\n            \"\tit eq\t\t\t\t\t\t\t\t\t\t\t\\n\"\n            \"\tvldmiaeq r0!, {s16-s31}\t\t\t\t\t\t\t\\n\"/* Restore the additional FP context registers which are not restored automatically. */\n        #endif /* configENABLE_FPU || configENABLE_MVE */\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"\tmsr psplim, r1\t\t\t\t\t\t\t\t\t\\n\"/* Restore the PSPLIM register value for the task. */\n            \"\tmsr control, r2\t\t\t\t\t\t\t\t\t\\n\"/* Restore the CONTROL register value for the task. */\n        #else /* configENABLE_MPU */\n            \"\tmsr psplim, r2\t\t\t\t\t\t\t\t\t\\n\"/* Restore the PSPLIM register value for the task. */\n        #endif /* configENABLE_MPU */\n        \"\tmsr psp, r0\t\t\t\t\t\t\t\t\t\t\\n\"/* Remember the new top of stack for the task. */\n        \"\tbx r3\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.align 4\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"pxCurrentTCBConst: .word pxCurrentTCB\t\t\t\t\\n\"\n        #if ( configENABLE_MPU == 1 )\n            \"xMPUCTRLConst: .word 0xe000ed94\t\t\t\t\t\\n\"\n            \"xMAIR0Const: .word 0xe000edc0\t\t\t\t\t\t\\n\"\n            \"xRNRConst: .word 0xe000ed98\t\t\t\t\t\t\\n\"\n            \"xRBARConst: .word 0xe000ed9c\t\t\t\t\t\t\\n\"\n        #endif /* configENABLE_MPU */\n        ::\"i\" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )\n    );\n}\n/*-----------------------------------------------------------*/\n\nvoid SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\n{\n    __asm volatile\n    (\n        \"\t.syntax unified\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\ttst lr, #4\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tite eq\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrseq r0, msp\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tmrsne r0, psp\t\t\t\t\t\t\t\t\t\\n\"\n        \"\tldr r1, svchandler_address_const\t\t\t\t\\n\"\n        \"\tbx r1\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"\t.align 4\t\t\t\t\t\t\t\t\t\t\\n\"\n        \"svchandler_address_const: .word vPortSVCHandler_C\t\\n\"\n    );\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef __PORT_ASM_H__\n#define __PORT_ASM_H__\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n\n/* MPU wrappers includes. */\n#include \"mpu_wrappers.h\"\n\n/**\n * @brief Restore the context of the first task so that the first task starts\n * executing.\n */\nvoid vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Checks whether or not the processor is privileged.\n *\n * @return 1 if the processor is already privileged, 0 otherwise.\n */\nBaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );\n\n/**\n * @brief Raises the privilege level by clearing the bit 0 of the CONTROL\n * register.\n *\n * @note This is a privileged function and should only be called from the kenrel\n * code.\n *\n * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.\n *  Bit[0] = 0 --> The processor is running privileged\n *  Bit[0] = 1 --> The processor is running unprivileged.\n */\nvoid vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\n * register.\n *\n * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.\n *  Bit[0] = 0 --> The processor is running privileged\n *  Bit[0] = 1 --> The processor is running unprivileged.\n */\nvoid vResetPrivilege( void ) __attribute__( ( naked ) );\n\n/**\n * @brief Starts the first task.\n */\nvoid vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Disables interrupts.\n */\nuint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Enables interrupts.\n */\nvoid vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief PendSV Exception handler.\n */\nvoid PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief SVC Handler.\n */\nvoid SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Allocate a Secure context for the calling task.\n *\n * @param[in] ulSecureStackSize The size of the stack to be allocated on the\n * secure side for the calling task.\n */\nvoid vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) );\n\n/**\n * @brief Free the task's secure context.\n *\n * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.\n */\nvoid vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n#endif /* __PORT_ASM_H__ */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM85_NTZ/non_secure/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef PORTMACRO_H\n#define PORTMACRO_H\n\n#ifdef __cplusplus\n    extern \"C\" {\n#endif\n\n#include \"portmacrocommon.h\"\n\n/*------------------------------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the given hardware\n * and compiler.\n *\n * These settings should not be altered.\n *------------------------------------------------------------------------------\n */\n\n#ifndef configENABLE_MVE\n    #error configENABLE_MVE must be defined in FreeRTOSConfig.h. Set configENABLE_MVE to 1 to enable the MVE or 0 to disable the MVE.\n#endif /* configENABLE_MVE */\n/*-----------------------------------------------------------*/\n\n/**\n * Architecture specifics.\n */\n#define portARCH_NAME                       \"Cortex-M85\"\n#define portDONT_DISCARD                    __attribute__( ( used ) )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Critical section management.\n */\n#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()\n#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )\n/*-----------------------------------------------------------*/\n\n#ifdef __cplusplus\n    }\n#endif\n\n#endif /* PORTMACRO_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef PORTMACROCOMMON_H\n    #define PORTMACROCOMMON_H\n\n    #ifdef __cplusplus\n        extern \"C\" {\n    #endif\n\n/*------------------------------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the given hardware\n * and compiler.\n *\n * These settings should not be altered.\n *------------------------------------------------------------------------------\n */\n\n    #ifndef configENABLE_FPU\n        #error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.\n    #endif /* configENABLE_FPU */\n\n    #ifndef configENABLE_MPU\n        #error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.\n    #endif /* configENABLE_MPU */\n\n    #ifndef configENABLE_TRUSTZONE\n        #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.\n    #endif /* configENABLE_TRUSTZONE */\n\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Type definitions.\n */\n    #define portCHAR          char\n    #define portFLOAT         float\n    #define portDOUBLE        double\n    #define portLONG          long\n    #define portSHORT         short\n    #define portSTACK_TYPE    uint32_t\n    #define portBASE_TYPE     long\n\n    typedef portSTACK_TYPE   StackType_t;\n    typedef long             BaseType_t;\n    typedef unsigned long    UBaseType_t;\n\n    #if ( configUSE_16_BIT_TICKS == 1 )\n        typedef uint16_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffff\n    #else\n        typedef uint32_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL\n\n/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\n * not need to be guarded with a critical section. */\n        #define portTICK_TYPE_IS_ATOMIC    1\n    #endif\n/*-----------------------------------------------------------*/\n\n/**\n * Architecture specifics.\n */\n    #define portSTACK_GROWTH                   ( -1 )\n    #define portTICK_PERIOD_MS                 ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\n    #define portBYTE_ALIGNMENT                 8\n    #define portNOP()\n    #define portINLINE                         __inline\n    #ifndef portFORCE_INLINE\n        #define portFORCE_INLINE               inline __attribute__( ( always_inline ) )\n    #endif\n    #define portHAS_STACK_OVERFLOW_CHECKING    1\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Extern declarations.\n */\n    extern BaseType_t xPortIsInsideInterrupt( void );\n\n    extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;\n\n    extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;\n    extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;\n\n    extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\n    extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\n\n    #if ( configENABLE_TRUSTZONE == 1 )\n        extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */\n        extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;\n    #endif /* configENABLE_TRUSTZONE */\n\n    #if ( configENABLE_MPU == 1 )\n        extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;\n        extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;\n    #endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\n/**\n * @brief MPU specific constants.\n */\n    #if ( configENABLE_MPU == 1 )\n        #define portUSING_MPU_WRAPPERS    1\n        #define portPRIVILEGE_BIT         ( 0x80000000UL )\n    #else\n        #define portPRIVILEGE_BIT         ( 0x0UL )\n    #endif /* configENABLE_MPU */\n\n/* MPU settings that can be overriden in FreeRTOSConfig.h. */\n#ifndef configTOTAL_MPU_REGIONS\n    /* Define to 8 for backward compatibility. */\n    #define configTOTAL_MPU_REGIONS       ( 8UL )\n#endif\n\n/* MPU regions. */\n    #define portPRIVILEGED_FLASH_REGION                   ( 0UL )\n    #define portUNPRIVILEGED_FLASH_REGION                 ( 1UL )\n    #define portUNPRIVILEGED_SYSCALLS_REGION              ( 2UL )\n    #define portPRIVILEGED_RAM_REGION                     ( 3UL )\n    #define portSTACK_REGION                              ( 4UL )\n    #define portFIRST_CONFIGURABLE_REGION                 ( 5UL )\n    #define portLAST_CONFIGURABLE_REGION                  ( configTOTAL_MPU_REGIONS - 1UL )\n    #define portNUM_CONFIGURABLE_REGIONS                  ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )\n    #define portTOTAL_NUM_REGIONS                         ( portNUM_CONFIGURABLE_REGIONS + 1 )   /* Plus one to make space for the stack region. */\n\n/* Device memory attributes used in MPU_MAIR registers.\n *\n * 8-bit values encoded as follows:\n *  Bit[7:4] - 0000 - Device Memory\n *  Bit[3:2] - 00 --> Device-nGnRnE\n *\t\t\t\t01 --> Device-nGnRE\n *\t\t\t\t10 --> Device-nGRE\n *\t\t\t\t11 --> Device-GRE\n *  Bit[1:0] - 00, Reserved.\n */\n    #define portMPU_DEVICE_MEMORY_nGnRnE                  ( 0x00 )   /* 0000 0000 */\n    #define portMPU_DEVICE_MEMORY_nGnRE                   ( 0x04 )   /* 0000 0100 */\n    #define portMPU_DEVICE_MEMORY_nGRE                    ( 0x08 )   /* 0000 1000 */\n    #define portMPU_DEVICE_MEMORY_GRE                     ( 0x0C )   /* 0000 1100 */\n\n/* Normal memory attributes used in MPU_MAIR registers. */\n    #define portMPU_NORMAL_MEMORY_NON_CACHEABLE           ( 0x44 )   /* Non-cacheable. */\n    #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE    ( 0xFF )   /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */\n\n/* Attributes used in MPU_RBAR registers. */\n    #define portMPU_REGION_NON_SHAREABLE                  ( 0UL << 3UL )\n    #define portMPU_REGION_INNER_SHAREABLE                ( 1UL << 3UL )\n    #define portMPU_REGION_OUTER_SHAREABLE                ( 2UL << 3UL )\n\n    #define portMPU_REGION_PRIVILEGED_READ_WRITE          ( 0UL << 1UL )\n    #define portMPU_REGION_READ_WRITE                     ( 1UL << 1UL )\n    #define portMPU_REGION_PRIVILEGED_READ_ONLY           ( 2UL << 1UL )\n    #define portMPU_REGION_READ_ONLY                      ( 3UL << 1UL )\n\n    #define portMPU_REGION_EXECUTE_NEVER                  ( 1UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Settings to define an MPU region.\n */\n    typedef struct MPURegionSettings\n    {\n        uint32_t ulRBAR; /**< RBAR for the region. */\n        uint32_t ulRLAR; /**< RLAR for the region. */\n    } MPURegionSettings_t;\n\n/**\n * @brief MPU settings as stored in the TCB.\n */\n    typedef struct MPU_SETTINGS\n    {\n        uint32_t ulMAIR0;                                              /**< MAIR0 for the task containing attributes for all the 4 per task regions. */\n        MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */\n    } xMPU_SETTINGS;\n/*-----------------------------------------------------------*/\n\n/**\n * @brief SVC numbers.\n */\n    #define portSVC_ALLOCATE_SECURE_CONTEXT    0\n    #define portSVC_FREE_SECURE_CONTEXT        1\n    #define portSVC_START_SCHEDULER            2\n    #define portSVC_RAISE_PRIVILEGE            3\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Scheduler utilities.\n */\n    #define portYIELD()                                 vPortYield()\n    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )\n    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )\n    #define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )\n    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Critical section management.\n */\n    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulSetInterruptMask()\n    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vClearInterruptMask( x )\n    #define portENTER_CRITICAL()                      vPortEnterCritical()\n    #define portEXIT_CRITICAL()                       vPortExitCritical()\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Tickless idle/low power functionality.\n */\n    #ifndef portSUPPRESS_TICKS_AND_SLEEP\n        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );\n        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )\n    #endif\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Task function macros as described on the FreeRTOS.org WEB site.\n */\n    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )\n    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )\n/*-----------------------------------------------------------*/\n\n    #if ( configENABLE_TRUSTZONE == 1 )\n\n/**\n * @brief Allocate a secure context for the task.\n *\n * Tasks are not created with a secure context. Any task that is going to call\n * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a\n * secure context before it calls any secure function.\n *\n * @param[in] ulSecureStackSize The size of the secure stack to be allocated.\n */\n        #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )\n\n/**\n * @brief Called when a task is deleted to delete the task's secure context,\n * if it has one.\n *\n * @param[in] pxTCB The TCB of the task being deleted.\n */\n        #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )\n    #endif /* configENABLE_TRUSTZONE */\n/*-----------------------------------------------------------*/\n\n    #if ( configENABLE_MPU == 1 )\n\n/**\n * @brief Checks whether or not the processor is privileged.\n *\n * @return 1 if the processor is already privileged, 0 otherwise.\n */\n        #define portIS_PRIVILEGED()      xIsPrivileged()\n\n/**\n * @brief Raise an SVC request to raise privilege.\n *\n * The SVC handler checks that the SVC was raised from a system call and only\n * then it raises the privilege. If this is called from any other place,\n * the privilege is not raised.\n */\n        #define portRAISE_PRIVILEGE()    __asm volatile ( \"svc %0 \\n\" ::\"i\" ( portSVC_RAISE_PRIVILEGE ) : \"memory\" );\n\n/**\n * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\n * register.\n */\n        #define portRESET_PRIVILEGE()    vResetPrivilege()\n    #else\n        #define portIS_PRIVILEGED()\n        #define portRAISE_PRIVILEGE()\n        #define portRESET_PRIVILEGE()\n    #endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Barriers.\n */\n    #define portMEMORY_BARRIER()    __asm volatile ( \"\" ::: \"memory\" )\n/*-----------------------------------------------------------*/\n\n    #ifdef __cplusplus\n        }\n    #endif\n\n#endif /* PORTMACROCOMMON_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CR5/port.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Standard includes. */\n#include <stdlib.h>\n#include <string.h>\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n#ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS\n    #error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined.  Refer to Cortex-A equivalent: http: /*www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */\n#endif\n\n#ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET\n    #error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined.  Refer to Cortex-A equivalent: http: /*www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */\n#endif\n\n#ifndef configUNIQUE_INTERRUPT_PRIORITIES\n    #error configUNIQUE_INTERRUPT_PRIORITIES must be defined.  Refer to Cortex-A equivalent: http: /*www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */\n#endif\n\n#ifndef configSETUP_TICK_INTERRUPT\n    #error configSETUP_TICK_INTERRUPT() must be defined.  Refer to Cortex-A equivalent: http: /*www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */\n#endif /* configSETUP_TICK_INTERRUPT */\n\n#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY\n    #error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined.  Refer to Cortex-A equivalent: http: /*www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */\n#endif\n\n#if configMAX_API_CALL_INTERRUPT_PRIORITY == 0\n    #error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0\n#endif\n\n#if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES\n    #error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority\n#endif\n\n#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1\n    /* Check the configuration. */\n    #if ( configMAX_PRIORITIES > 32 )\n        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.\n    #endif\n#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */\n\n/* In case security extensions are implemented. */\n#if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )\n    #error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )\n#endif\n\n/* Some vendor specific files default configCLEAR_TICK_INTERRUPT() in\n * portmacro.h. */\n#ifndef configCLEAR_TICK_INTERRUPT\n    #define configCLEAR_TICK_INTERRUPT()\n#endif\n\n/* A critical section is exited when the critical section nesting count reaches\n * this value. */\n#define portNO_CRITICAL_NESTING          ( ( uint32_t ) 0 )\n\n/* In all GICs 255 can be written to the priority mask register to unmask all\n * (but the lowest) interrupt priority. */\n#define portUNMASK_VALUE                 ( 0xFFUL )\n\n/* Tasks are not created with a floating point context, but can be given a\n * floating point context after they have been created.  A variable is stored as\n * part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task\n * does not have an FPU context, or any other value if the task does have an FPU\n * context. */\n#define portNO_FLOATING_POINT_CONTEXT    ( ( StackType_t ) 0 )\n\n/* Constants required to setup the initial task context. */\n#define portINITIAL_SPSR                 ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */\n#define portTHUMB_MODE_BIT               ( ( StackType_t ) 0x20 )\n#define portINTERRUPT_ENABLE_BIT         ( 0x80UL )\n#define portTHUMB_MODE_ADDRESS           ( 0x01UL )\n\n/* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary\n * point is zero. */\n#define portBINARY_POINT_BITS            ( ( uint8_t ) 0x03 )\n\n/* Masks all bits in the APSR other than the mode bits. */\n#define portAPSR_MODE_BITS_MASK          ( 0x1F )\n\n/* The value of the mode bits in the APSR when the CPU is executing in user\n * mode. */\n#define portAPSR_USER_MODE               ( 0x10 )\n\n/* The critical section macros only mask interrupts up to an application\n * determined priority level.  Sometimes it is necessary to turn interrupt off in\n * the CPU itself before modifying certain hardware registers. */\n#define portCPU_IRQ_DISABLE()                  \\\n    __asm volatile ( \"CPSID i\" ::: \"memory\" ); \\\n    __asm volatile ( \"DSB\" );                  \\\n    __asm volatile ( \"ISB\" );\n\n#define portCPU_IRQ_ENABLE()                   \\\n    __asm volatile ( \"CPSIE i\" ::: \"memory\" ); \\\n    __asm volatile ( \"DSB\" );                  \\\n    __asm volatile ( \"ISB\" );\n\n\n/* Macro to unmask all interrupt priorities. */\n#define portCLEAR_INTERRUPT_MASK()                            \\\n    {                                                         \\\n        portCPU_IRQ_DISABLE();                                \\\n        portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \\\n        __asm volatile ( \"DSB\t\t\\n\"                       \\\n                         \"ISB\t\t\\n\");                         \\\n        portCPU_IRQ_ENABLE();                                 \\\n    }\n\n#define portINTERRUPT_PRIORITY_REGISTER_OFFSET    0x400UL\n#define portMAX_8_BIT_VALUE                       ( ( uint8_t ) 0xff )\n#define portBIT_0_SET                             ( ( uint8_t ) 0x01 )\n\n/* Let the user override the pre-loading of the initial LR with the address of\n * prvTaskExitError() in case is messes up unwinding of the stack in the\n * debugger. */\n#ifdef configTASK_RETURN_ADDRESS\n    #define portTASK_RETURN_ADDRESS    configTASK_RETURN_ADDRESS\n#else\n    #define portTASK_RETURN_ADDRESS    prvTaskExitError\n#endif\n\n/*\n * The space on the stack required to hold the FPU registers.\n *\n * The ARM Cortex R5 processor implements the VFPv3-D16 FPU\n * architecture. This includes only 16 double-precision registers,\n * instead of 32 as is in VFPv3. The register bank can be viewed\n * either as sixteen 64-bit double-word registers (D0-D15) or\n * thirty-two 32-bit single-word registers (S0-S31), in both cases\n * the size of the bank remains the same. The FPU has also a 32-bit\n * status register.\n */\n#define portFPU_REGISTER_WORDS    ( ( 16 * 2 ) + 1 )\n\n/*-----------------------------------------------------------*/\n\n/*\n * Starts the first task executing.  This function is necessarily written in\n * assembly code so is implemented in portASM.s.\n */\nextern void vPortRestoreTaskContext( void );\n\n/*\n * Used to catch tasks that attempt to return from their implementing function.\n */\nstatic void prvTaskExitError( void );\n\n/*\n * If the application provides an implementation of vApplicationIRQHandler(),\n * then it will get called directly without saving the FPU registers on\n * interrupt entry, and this weak implementation of\n * vApplicationFPUSafeIRQHandler() is just provided to remove linkage errors -\n * it should never actually get called so its implementation contains a\n * call to configASSERT() that will always fail.\n *\n * If the application provides its own implementation of\n * vApplicationFPUSafeIRQHandler() then the implementation of\n * vApplicationIRQHandler() provided in portASM.S will save the FPU registers\n * before calling it.\n *\n * Therefore, if the application writer wants FPU registers to be saved on\n * interrupt entry their IRQ handler must be called\n * vApplicationFPUSafeIRQHandler(), and if the application writer does not want\n * FPU registers to be saved on interrupt entry their IRQ handler must be\n * called vApplicationIRQHandler().\n */\nvoid vApplicationFPUSafeIRQHandler( uint32_t ulICCIAR ) __attribute__((weak) );\n\n/*-----------------------------------------------------------*/\n\n/* A variable is used to keep track of the critical section nesting.  This\n * variable has to be stored as part of the task context and must be initialised to\n * a non zero value to ensure interrupts don't inadvertently become unmasked before\n * the scheduler starts.  As it is stored as part of the task context it will\n * automatically be set to 0 when the first task is started. */\nvolatile uint32_t ulCriticalNesting = 9999UL;\n\n/* Saved as part of the task context.  If ulPortTaskHasFPUContext is non-zero then\n * a floating point context must be saved and restored for the task. */\nuint32_t ulPortTaskHasFPUContext = pdFALSE;\n\n/* Set to 1 to pend a context switch from an ISR. */\nuint32_t ulPortYieldRequired = pdFALSE;\n\n/* Counts the interrupt nesting depth.  A context switch is only performed if\n * if the nesting depth is 0. */\nuint32_t ulPortInterruptNesting = 0UL;\n\n/* Used in asm code. */\n__attribute__( ( used ) ) const uint32_t ulICCIAR = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS;\n__attribute__( ( used ) ) const uint32_t ulICCEOIR = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS;\n__attribute__( ( used ) ) const uint32_t ulICCPMR = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS;\n__attribute__( ( used ) ) const uint32_t ulMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );\n\n/*-----------------------------------------------------------*/\n\n/*\n * See header file for description.\n */\nStackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,\n                                     TaskFunction_t pxCode,\n                                     void * pvParameters )\n{\n    /* Setup the initial stack of the task.  The stack is set exactly as\n     * expected by the portRESTORE_CONTEXT() macro.\n     *\n     * The fist real value on the stack is the status register, which is set for\n     * system mode, with interrupts enabled.  A few NULLs are added first to ensure\n     * GDB does not try decoding a non-existent return address. */\n    *pxTopOfStack = ( StackType_t ) NULL;\n    pxTopOfStack--;\n    *pxTopOfStack = ( StackType_t ) NULL;\n    pxTopOfStack--;\n    *pxTopOfStack = ( StackType_t ) NULL;\n    pxTopOfStack--;\n    *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;\n\n    if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )\n    {\n        /* The task will start in THUMB mode. */\n        *pxTopOfStack |= portTHUMB_MODE_BIT;\n    }\n\n    pxTopOfStack--;\n\n    /* Next the return address, which in this case is the start of the task. */\n    *pxTopOfStack = ( StackType_t ) pxCode;\n    pxTopOfStack--;\n\n    /* Next all the registers other than the stack pointer. */\n    *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* R14 */\n    pxTopOfStack--;\n    *pxTopOfStack = ( StackType_t ) 0x12121212;              /* R12 */\n    pxTopOfStack--;\n    *pxTopOfStack = ( StackType_t ) 0x11111111;              /* R11 */\n    pxTopOfStack--;\n    *pxTopOfStack = ( StackType_t ) 0x10101010;              /* R10 */\n    pxTopOfStack--;\n    *pxTopOfStack = ( StackType_t ) 0x09090909;              /* R9 */\n    pxTopOfStack--;\n    *pxTopOfStack = ( StackType_t ) 0x08080808;              /* R8 */\n    pxTopOfStack--;\n    *pxTopOfStack = ( StackType_t ) 0x07070707;              /* R7 */\n    pxTopOfStack--;\n    *pxTopOfStack = ( StackType_t ) 0x06060606;              /* R6 */\n    pxTopOfStack--;\n    *pxTopOfStack = ( StackType_t ) 0x05050505;              /* R5 */\n    pxTopOfStack--;\n    *pxTopOfStack = ( StackType_t ) 0x04040404;              /* R4 */\n    pxTopOfStack--;\n    *pxTopOfStack = ( StackType_t ) 0x03030303;              /* R3 */\n    pxTopOfStack--;\n    *pxTopOfStack = ( StackType_t ) 0x02020202;              /* R2 */\n    pxTopOfStack--;\n    *pxTopOfStack = ( StackType_t ) 0x01010101;              /* R1 */\n    pxTopOfStack--;\n    *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */\n    pxTopOfStack--;\n\n    /* The task will start with a critical nesting count of 0 as interrupts are\n     * enabled. */\n    *pxTopOfStack = portNO_CRITICAL_NESTING;\n\n    #if( configUSE_TASK_FPU_SUPPORT == 1 )\n    {\n        /* The task will start without a floating point context.  A task that\n        uses the floating point hardware must call vPortTaskUsesFPU() before\n        executing any floating point instructions. */\n        pxTopOfStack--;\n        *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;\n    }\n    #elif( configUSE_TASK_FPU_SUPPORT == 2 )\n    {\n        /* The task will start with a floating point context.  Leave enough\n        space for the registers - and ensure they are initialized to 0. */\n        pxTopOfStack -= portFPU_REGISTER_WORDS;\n        memset( pxTopOfStack, 0x00, portFPU_REGISTER_WORDS * sizeof( StackType_t ) );\n\n        pxTopOfStack--;\n        *pxTopOfStack = pdTRUE;\n        ulPortTaskHasFPUContext = pdTRUE;\n    }\n    #else\n    {\n        #error Invalid configUSE_TASK_FPU_SUPPORT setting - configUSE_TASK_FPU_SUPPORT must be set to 1, 2, or left undefined.\n    }\n    #endif /* configUSE_TASK_FPU_SUPPORT */\n\n    return pxTopOfStack;\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvTaskExitError( void )\n{\n    /* A function that implements a task must not exit or attempt to return to\n     * its caller as there is nothing to return to.  If a task wants to exit it\n     * should instead call vTaskDelete( NULL ).\n     *\n     * Artificially force an assert() to be triggered if configASSERT() is\n     * defined, then stop here so application writers can catch the error. */\n    configASSERT( ulPortInterruptNesting == ~0UL );\n    portDISABLE_INTERRUPTS();\n\n    for( ; ; )\n    {\n    }\n}\n/*-----------------------------------------------------------*/\n\nvoid vApplicationFPUSafeIRQHandler( uint32_t ulICCIAR )\n{\n    ( void ) ulICCIAR;\n    configASSERT( ( volatile void * ) NULL );\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xPortStartScheduler( void )\n{\n    uint32_t ulAPSR, ulCycles = 8; /* 8 bits per byte. */\n\n    #if ( configASSERT_DEFINED == 1 )\n        {\n            volatile uint32_t ulOriginalPriority;\n            volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + portINTERRUPT_PRIORITY_REGISTER_OFFSET );\n            volatile uint8_t ucMaxPriorityValue;\n\n            /* Determine how many priority bits are implemented in the GIC.\n             *\n             * Save the interrupt priority value that is about to be clobbered. */\n            ulOriginalPriority = *pucFirstUserPriorityRegister;\n\n            /* Determine the number of priority bits available.  First write to\n             * all possible bits. */\n            *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\n\n            /* Read the value back to see how many bits stuck. */\n            ucMaxPriorityValue = *pucFirstUserPriorityRegister;\n\n            /* Shift to the least significant bits. */\n            while( ( ucMaxPriorityValue & portBIT_0_SET ) != portBIT_0_SET )\n            {\n                ucMaxPriorityValue >>= ( uint8_t ) 0x01;\n\n                /* If ulCycles reaches 0 then ucMaxPriorityValue must have been\n                 * read as 0, indicating a misconfiguration. */\n                ulCycles--;\n\n                if( ulCycles == 0 )\n                {\n                    break;\n                }\n            }\n\n            /* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read\n             * value. */\n            configASSERT( ucMaxPriorityValue == portLOWEST_INTERRUPT_PRIORITY );\n\n            /* Restore the clobbered interrupt priority register to its original\n             * value. */\n            *pucFirstUserPriorityRegister = ulOriginalPriority;\n        }\n    #endif /* configASSERT_DEFINED */\n\n    /* Only continue if the CPU is not in User mode.  The CPU must be in a\n     * Privileged mode for the scheduler to start. */\n    __asm volatile ( \"MRS %0, APSR\" : \"=r\" ( ulAPSR )::\"memory\" );\n    ulAPSR &= portAPSR_MODE_BITS_MASK;\n    configASSERT( ulAPSR != portAPSR_USER_MODE );\n\n    if( ulAPSR != portAPSR_USER_MODE )\n    {\n        /* Only continue if the binary point value is set to its lowest possible\n         * setting.  See the comments in vPortValidateInterruptPriority() below for\n         * more information. */\n        configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );\n\n        if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )\n        {\n            /* Interrupts are turned off in the CPU itself to ensure tick does\n             * not execute\twhile the scheduler is being started.  Interrupts are\n             * automatically turned back on in the CPU when the first task starts\n             * executing. */\n            portCPU_IRQ_DISABLE();\n\n            /* Start the timer that generates the tick ISR. */\n            configSETUP_TICK_INTERRUPT();\n\n            /* Start the first task executing. */\n            vPortRestoreTaskContext();\n        }\n    }\n\n    /* Will only get here if vTaskStartScheduler() was called with the CPU in\n     * a non-privileged mode or the binary point register was not set to its lowest\n     * possible value.  prvTaskExitError() is referenced to prevent a compiler\n     * warning about it being defined but not referenced in the case that the user\n     * defines their own exit address. */\n    ( void ) prvTaskExitError;\n    return 0;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEndScheduler( void )\n{\n    /* Not implemented in ports where there is nothing to return to.\n     * Artificially force an assert. */\n    configASSERT( ulCriticalNesting == 1000UL );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEnterCritical( void )\n{\n    /* Mask interrupts up to the max syscall interrupt priority. */\n    ulPortSetInterruptMask();\n\n    /* Now interrupts are disabled ulCriticalNesting can be accessed\n     * directly.  Increment ulCriticalNesting to keep a count of how many times\n     * portENTER_CRITICAL() has been called. */\n    ulCriticalNesting++;\n\n    /* This is not the interrupt safe version of the enter critical function so\n     * assert() if it is being called from an interrupt context.  Only API\n     * functions that end in \"FromISR\" can be used in an interrupt.  Only assert if\n     * the critical nesting count is 1 to protect against recursive calls if the\n     * assert function also uses a critical section. */\n    if( ulCriticalNesting == 1 )\n    {\n        configASSERT( ulPortInterruptNesting == 0 );\n    }\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortExitCritical( void )\n{\n    if( ulCriticalNesting > portNO_CRITICAL_NESTING )\n    {\n        /* Decrement the nesting count as the critical section is being\n         * exited. */\n        ulCriticalNesting--;\n\n        /* If the nesting level has reached zero then all interrupt\n         * priorities must be re-enabled. */\n        if( ulCriticalNesting == portNO_CRITICAL_NESTING )\n        {\n            /* Critical nesting has reached zero so all interrupt priorities\n             * should be unmasked. */\n            portCLEAR_INTERRUPT_MASK();\n        }\n    }\n}\n/*-----------------------------------------------------------*/\n\nvoid FreeRTOS_Tick_Handler( void )\n{\n    /* Set interrupt mask before altering scheduler structures.   The tick\n     * handler runs at the lowest priority, so interrupts cannot already be masked,\n     * so there is no need to save and restore the current mask value.  It is\n     * necessary to turn off interrupts in the CPU itself while the ICCPMR is being\n     * updated. */\n    portCPU_IRQ_DISABLE();\n    portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );\n    __asm volatile ( \"dsb\t\t\\n\"\n                     \"isb\t\t\\n\"::: \"memory\" );\n    portCPU_IRQ_ENABLE();\n\n    /* Increment the RTOS tick. */\n    if( xTaskIncrementTick() != pdFALSE )\n    {\n        ulPortYieldRequired = pdTRUE;\n    }\n\n    /* Ensure all interrupt priorities are active again. */\n    portCLEAR_INTERRUPT_MASK();\n    configCLEAR_TICK_INTERRUPT();\n}\n/*-----------------------------------------------------------*/\n\n#if( configUSE_TASK_FPU_SUPPORT != 2 )\n\n    void vPortTaskUsesFPU( void )\n    {\n        uint32_t ulInitialFPSCR = 0;\n\n        /* A task is registering the fact that it needs an FPU context.  Set the\n         * FPU flag (which is saved as part of the task context). */\n        ulPortTaskHasFPUContext = pdTRUE;\n\n        /* Initialise the floating point status register. */\n        __asm volatile ( \"FMXR \tFPSCR, %0\" ::\"r\" ( ulInitialFPSCR ) : \"memory\" );\n    }\n\n#endif /* configUSE_TASK_FPU_SUPPORT */\n/*-----------------------------------------------------------*/\n\nvoid vPortClearInterruptMask( uint32_t ulNewMaskValue )\n{\n    if( ulNewMaskValue == pdFALSE )\n    {\n        portCLEAR_INTERRUPT_MASK();\n    }\n}\n/*-----------------------------------------------------------*/\n\nuint32_t ulPortSetInterruptMask( void )\n{\n    uint32_t ulReturn;\n\n    /* Interrupt in the CPU must be turned off while the ICCPMR is being\n     * updated. */\n    portCPU_IRQ_DISABLE();\n\n    if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )\n    {\n        /* Interrupts were already masked. */\n        ulReturn = pdTRUE;\n    }\n    else\n    {\n        ulReturn = pdFALSE;\n        portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );\n        __asm volatile ( \"dsb\t\t\\n\"\n                         \"isb\t\t\\n\"::: \"memory\" );\n    }\n\n    portCPU_IRQ_ENABLE();\n\n    return ulReturn;\n}\n/*-----------------------------------------------------------*/\n\n#if ( configASSERT_DEFINED == 1 )\n\n    void vPortValidateInterruptPriority( void )\n    {\n        /* The following assertion will fail if a service routine (ISR) for\n         * an interrupt that has been assigned a priority above\n         * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\n         * function.  ISR safe FreeRTOS API functions must *only* be called\n         * from interrupts that have been assigned a priority at or below\n         * configMAX_SYSCALL_INTERRUPT_PRIORITY.\n         *\n         * Numerically low interrupt priority numbers represent logically high\n         * interrupt priorities, therefore the priority of the interrupt must\n         * be set to a value equal to or numerically *higher* than\n         * configMAX_SYSCALL_INTERRUPT_PRIORITY.\n         *\n         * FreeRTOS maintains separate thread and ISR API functions to ensure\n         * interrupt entry is as fast and simple as possible. */\n\n        configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );\n\n        /* Priority grouping:  The interrupt controller (GIC) allows the bits\n         * that define each interrupt's priority to be split between bits that\n         * define the interrupt's pre-emption priority bits and bits that define\n         * the interrupt's sub-priority.  For simplicity all bits must be defined\n         * to be pre-emption priority bits.  The following assertion will fail if\n         * this is not the case (if some bits represent a sub-priority).\n         *\n         * The priority grouping is configured by the GIC's binary point register\n         * (ICCBPR).  Writing 0 to ICCBPR will ensure it is set to its lowest\n         * possible value (which may be above 0). */\n        configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );\n    }\n\n#endif /* configASSERT_DEFINED */\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CR5/portASM.S",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n\t.text\n\t.arm\n\n\t.set SYS_MODE,\t0x1f\n\t.set SVC_MODE,\t0x13\n\t.set IRQ_MODE,\t0x12\n\n\t/* Hardware registers. */\n\t.extern ulICCIAR\n\t.extern ulICCEOIR\n\t.extern ulICCPMR\n\n\t/* Variables and functions. */\n\t.extern ulMaxAPIPriorityMask\n\t.extern _freertos_vector_table\n\t.extern pxCurrentTCB\n\t.extern vTaskSwitchContext\n\t.extern vApplicationIRQHandler\n\t.extern ulPortInterruptNesting\n\t.extern ulPortTaskHasFPUContext\n\n\t.global FreeRTOS_IRQ_Handler\n\t.global FreeRTOS_SWI_Handler\n\t.global vPortRestoreTaskContext\n\n.macro portSAVE_CONTEXT\n\n\t/* Save the LR and SPSR onto the system mode stack before switching to\n\tsystem mode to save the remaining system mode registers. */\n\tSRSDB\tsp!, #SYS_MODE\n\tCPS\t\t#SYS_MODE\n\tPUSH\t{R0-R12, R14}\n\n\t/* Push the critical nesting count. */\n\tLDR\t\tR2, ulCriticalNestingConst\n\tLDR\t\tR1, [R2]\n\tPUSH\t{R1}\n\n\t/* Does the task have a floating point context that needs saving?  If\n\tulPortTaskHasFPUContext is 0 then no. */\n\tLDR\t\tR2, ulPortTaskHasFPUContextConst\n\tLDR\t\tR3, [R2]\n\tCMP\t\tR3, #0\n\n\t/* Save the floating point context, if any. */\n\tFMRXNE  R1,  FPSCR\n\tVPUSHNE {D0-D15}\n\t/*VPUSHNE\t{D16-D31}*/\n\tPUSHNE\t{R1}\n\n\t/* Save ulPortTaskHasFPUContext itself. */\n\tPUSH\t{R3}\n\n\t/* Save the stack pointer in the TCB. */\n\tLDR\t\tR0, pxCurrentTCBConst\n\tLDR\t\tR1, [R0]\n\tSTR\t\tSP, [R1]\n\n\t.endm\n\n; /**********************************************************************/\n\n.macro portRESTORE_CONTEXT\n\n\t/* Set the SP to point to the stack of the task being restored. */\n\tLDR\t\tR0, pxCurrentTCBConst\n\tLDR\t\tR1, [R0]\n\tLDR\t\tSP, [R1]\n\n\t/* Is there a floating point context to restore?  If the restored\n\tulPortTaskHasFPUContext is zero then no. */\n\tLDR\t\tR0, ulPortTaskHasFPUContextConst\n\tPOP\t\t{R1}\n\tSTR\t\tR1, [R0]\n\tCMP\t\tR1, #0\n\n\t/* Restore the floating point context, if any. */\n\tPOPNE \t{R0}\n\t/*VPOPNE\t{D16-D31}*/\n\tVPOPNE\t{D0-D15}\n\tVMSRNE  FPSCR, R0\n\n\t/* Restore the critical section nesting depth. */\n\tLDR\t\tR0, ulCriticalNestingConst\n\tPOP\t\t{R1}\n\tSTR\t\tR1, [R0]\n\n\t/* Ensure the priority mask is correct for the critical nesting depth. */\n\tLDR\t\tR2, ulICCPMRConst\n\tLDR\t\tR2, [R2]\n\tCMP\t\tR1, #0\n\tMOVEQ\tR4, #255\n\tLDRNE\tR4, ulMaxAPIPriorityMaskConst\n\tLDRNE\tR4, [R4]\n\tSTR\t\tR4, [R2]\n\n\t/* Restore all system mode registers other than the SP (which is already\n\tbeing used). */\n\tPOP\t\t{R0-R12, R14}\n\n\t/* Return to the task code, loading CPSR on the way. */\n\tRFEIA\tsp!\n\n\t.endm\n\n\n\n\n/******************************************************************************\n * SVC handler is used to start the scheduler.\n *****************************************************************************/\n.align 4\n.type FreeRTOS_SWI_Handler, %function\nFreeRTOS_SWI_Handler:\n\t/* Save the context of the current task and select a new task to run. */\n\tportSAVE_CONTEXT\n\tLDR R0, vTaskSwitchContextConst\n\tBLX\tR0\n\tportRESTORE_CONTEXT\n\n\n/******************************************************************************\n * vPortRestoreTaskContext is used to start the scheduler.\n *****************************************************************************/\n.type vPortRestoreTaskContext, %function\nvPortRestoreTaskContext:\n\t/* Switch to system mode. */\n\tCPS\t\t#SYS_MODE\n\tportRESTORE_CONTEXT\n\n.align 4\n.type FreeRTOS_IRQ_Handler, %function\nFreeRTOS_IRQ_Handler:\n\n\t/* Return to the interrupted instruction. */\n\tSUB\t\tlr, lr, #4\n\n\t/* Push the return address and SPSR. */\n\tPUSH\t{lr}\n\tMRS\t\tlr, SPSR\n\tPUSH\t{lr}\n\n\t/* Change to supervisor mode to allow reentry. */\n\tCPS\t\t#SVC_MODE\n\n\t/* Push used registers. */\n\tPUSH\t{r0-r4, r12}\n\n\t/* Increment nesting count.  r3 holds the address of ulPortInterruptNesting\n\tfor future use.  r1 holds the original ulPortInterruptNesting value for\n\tfuture use. */\n\tLDR\t\tr3, ulPortInterruptNestingConst\n\tLDR\t\tr1, [r3]\n\tADD\t\tr4, r1, #1\n\tSTR\t\tr4, [r3]\n\n\t/* Read value from the interrupt acknowledge register, which is stored in r0\n\tfor future parameter and interrupt clearing use. */\n\tLDR \tr2, ulICCIARConst\n\tLDR\t\tr2, [r2]\n\tLDR\t\tr0, [r2]\n\n\t/* Ensure bit 2 of the stack pointer is clear.  r2 holds the bit 2 value for\n\tfuture use.  _RB_ Is this ever needed provided the start of the stack is\n\talligned on an 8-byte boundary? */\n\tMOV\t\tr2, sp\n\tAND\t\tr2, r2, #4\n\tSUB\t\tsp, sp, r2\n\n\t/* Call the interrupt handler. */\n\tPUSH\t{r0-r4, lr}\n\tLDR\t\tr1, vApplicationIRQHandlerConst\n\tBLX\t\tr1\n\tPOP\t\t{r0-r4, lr}\n\tADD\t\tsp, sp, r2\n\n\tCPSID\ti\n\tDSB\n\tISB\n\n\t/* Write the value read from ICCIAR to ICCEOIR. */\n\tLDR \tr4, ulICCEOIRConst\n\tLDR\t\tr4, [r4]\n\tSTR\t\tr0, [r4]\n\n\t/* Restore the old nesting count. */\n\tSTR\t\tr1, [r3]\n\n\t/* A context switch is never performed if the nesting count is not 0. */\n\tCMP\t\tr1, #0\n\tBNE\t\texit_without_switch\n\n\t/* Did the interrupt request a context switch?  r1 holds the address of\n\tulPortYieldRequired and r0 the value of ulPortYieldRequired for future\n\tuse. */\n\tLDR\t\tr1, =ulPortYieldRequired\n\tLDR\t\tr0, [r1]\n\tCMP\t\tr0, #0\n\tBNE\t\tswitch_before_exit\n\nexit_without_switch:\n\t/* No context switch.  Restore used registers, LR_irq and SPSR before\n\treturning. */\n\tPOP\t\t{r0-r4, r12}\n\tCPS\t\t#IRQ_MODE\n\tPOP\t\t{LR}\n\tMSR\t\tSPSR_cxsf, LR\n\tPOP\t\t{LR}\n\tMOVS\tPC, LR\n\nswitch_before_exit:\n\t/* A context swtich is to be performed.  Clear the context switch pending\n\tflag. */\n\tMOV\t\tr0, #0\n\tSTR\t\tr0, [r1]\n\n\t/* Restore used registers, LR-irq and SPSR before saving the context\n\tto the task stack. */\n\tPOP\t\t{r0-r4, r12}\n\tCPS\t\t#IRQ_MODE\n\tPOP\t\t{LR}\n\tMSR\t\tSPSR_cxsf, LR\n\tPOP\t\t{LR}\n\tportSAVE_CONTEXT\n\n\t/* Call the function that selects the new task to execute.\n\tvTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD\n\tinstructions, or 8 byte aligned stack allocated data.  LR does not need\n\tsaving as a new LR will be loaded by portRESTORE_CONTEXT anyway. */\n\tLDR\t\tR0, vTaskSwitchContextConst\n\tBLX\t\tR0\n\n\t/* Restore the context of, and branch to, the task selected to execute\n\tnext. */\n\tportRESTORE_CONTEXT\n\n/******************************************************************************\n * If the application provides an implementation of vApplicationIRQHandler(),\n * then it will get called directly without saving the FPU registers on\n * interrupt entry, and this weak implementation of\n * vApplicationIRQHandler() will not get called.\n *\n * If the application provides its own implementation of\n * vApplicationFPUSafeIRQHandler() then this implementation of\n * vApplicationIRQHandler() will be called, save the FPU registers, and then\n * call vApplicationFPUSafeIRQHandler().\n *\n * Therefore, if the application writer wants FPU registers to be saved on\n * interrupt entry their IRQ handler must be called\n * vApplicationFPUSafeIRQHandler(), and if the application writer does not want\n * FPU registers to be saved on interrupt entry their IRQ handler must be\n * called vApplicationIRQHandler().\n *****************************************************************************/\n\n.align 4\n.weak vApplicationIRQHandler\n.type vApplicationIRQHandler, %function\nvApplicationIRQHandler:\n\tPUSH\t{LR}\n\tFMRX\tR1,  FPSCR\n\tVPUSH\t{D0-D15}\n\tPUSH\t{R1}\n\n\tLDR\t\tr1, vApplicationFPUSafeIRQHandlerConst\n\tBLX\t\tr1\n\n\tPOP\t\t{R0}\n\tVPOP\t{D0-D15}\n\tVMSR\tFPSCR, R0\n\n\tPOP {PC}\n\nulICCIARConst:\t.word ulICCIAR\nulICCEOIRConst:\t.word ulICCEOIR\nulICCPMRConst: .word ulICCPMR\npxCurrentTCBConst: .word pxCurrentTCB\nulCriticalNestingConst: .word ulCriticalNesting\nulPortTaskHasFPUContextConst: .word ulPortTaskHasFPUContext\nulMaxAPIPriorityMaskConst: .word ulMaxAPIPriorityMask\nvTaskSwitchContextConst: .word vTaskSwitchContext\nvApplicationIRQHandlerConst: .word vApplicationIRQHandler\nulPortInterruptNestingConst: .word ulPortInterruptNesting\nvApplicationFPUSafeIRQHandlerConst: .word vApplicationFPUSafeIRQHandler\n\n.end\n\n\n\n\n\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CR5/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef PORTMACRO_H\n    #define PORTMACRO_H\n\n    #ifdef __cplusplus\n        extern \"C\" {\n    #endif\n\n/*-----------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the given hardware\n * and compiler.\n *\n * These settings should not be altered.\n *-----------------------------------------------------------\n */\n\n/* Type definitions. */\n    #define portCHAR          char\n    #define portFLOAT         float\n    #define portDOUBLE        double\n    #define portLONG          long\n    #define portSHORT         short\n    #define portSTACK_TYPE    uint32_t\n    #define portBASE_TYPE     long\n\n    typedef portSTACK_TYPE   StackType_t;\n    typedef long             BaseType_t;\n    typedef unsigned long    UBaseType_t;\n\n    typedef uint32_t         TickType_t;\n    #define portMAX_DELAY    ( TickType_t ) 0xffffffffUL\n\n/*-----------------------------------------------------------*/\n\n/* Hardware specifics. */\n    #define portSTACK_GROWTH      ( -1 )\n    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\n    #define portBYTE_ALIGNMENT    8\n\n/*-----------------------------------------------------------*/\n\n/* Task utilities. */\n\n/* Called at the end of an ISR that can cause a context switch. */\n    #define portEND_SWITCHING_ISR( xSwitchRequired ) \\\n    {                                                \\\n        extern uint32_t ulPortYieldRequired;         \\\n                                                     \\\n        if( xSwitchRequired != pdFALSE )             \\\n        {                                            \\\n            ulPortYieldRequired = pdTRUE;            \\\n        }                                            \\\n    }\n\n    #define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )\n    #define portYIELD()                __asm volatile ( \"SWI 0\" ::: \"memory\" );\n\n\n/*-----------------------------------------------------------\n* Critical section control\n*----------------------------------------------------------*/\n\n    extern void vPortEnterCritical( void );\n    extern void vPortExitCritical( void );\n    extern uint32_t ulPortSetInterruptMask( void );\n    extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );\n    extern void vPortInstallFreeRTOSVectorTable( void );\n\n/* These macros do not globally disable/enable interrupts.  They do mask off\n * interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */\n    #define portENTER_CRITICAL()                      vPortEnterCritical();\n    #define portEXIT_CRITICAL()                       vPortExitCritical();\n    #define portDISABLE_INTERRUPTS()                  ulPortSetInterruptMask()\n    #define portENABLE_INTERRUPTS()                   vPortClearInterruptMask( 0 )\n    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulPortSetInterruptMask()\n    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vPortClearInterruptMask( x )\n\n/*-----------------------------------------------------------*/\n\n/* Task function macros as described on the FreeRTOS.org WEB site.  These are\n * not required for this port but included in case common demo code that uses these\n * macros is used. */\n    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )\n    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )\n\n/* Prototype of the FreeRTOS tick handler.  This must be installed as the\n * handler for whichever peripheral is used to generate the RTOS tick. */\n    void FreeRTOS_Tick_Handler( void );\n\n/* If configUSE_TASK_FPU_SUPPORT is set to 1 (or left undefined) then tasks are\ncreated without an FPU context and must call vPortTaskUsesFPU() to give\nthemselves an FPU context before using any FPU instructions. If\nconfigUSE_TASK_FPU_SUPPORT is set to 2 then all tasks will have an FPU context\nby default. */\n#if( configUSE_TASK_FPU_SUPPORT != 2 )\n    void vPortTaskUsesFPU( void );\n#else\n    /* Each task has an FPU context already, so define this function away to\n    nothing to prevent it being called accidentally. */\n    #define vPortTaskUsesFPU()\n#endif /* configUSE_TASK_FPU_SUPPORT */\n    #define portTASK_USES_FLOATING_POINT()    vPortTaskUsesFPU()\n\n    #define portLOWEST_INTERRUPT_PRIORITY           ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )\n    #define portLOWEST_USABLE_INTERRUPT_PRIORITY    ( portLOWEST_INTERRUPT_PRIORITY - 1UL )\n\n/* Architecture specific optimisations. */\n    #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION\n        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1\n    #endif\n\n    #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1\n\n/* Store/clear the ready priorities in a bit map. */\n        #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )\n        #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )\n\n/*-----------------------------------------------------------*/\n\n        #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31 - __builtin_clz( uxReadyPriorities ) )\n\n    #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */\n\n    #ifdef configASSERT\n        void vPortValidateInterruptPriority( void );\n        #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()\n    #endif /* configASSERT */\n\n    #define portNOP()                                         __asm volatile ( \"NOP\" )\n\n\n    #ifdef __cplusplus\n        } /* extern C */\n    #endif\n\n\n/* The number of bits to shift for an interrupt priority is dependent on the\n * number of bits implemented by the interrupt controller. */\n    #if configUNIQUE_INTERRUPT_PRIORITIES == 16\n        #define portPRIORITY_SHIFT            4\n        #define portMAX_BINARY_POINT_VALUE    3\n    #elif configUNIQUE_INTERRUPT_PRIORITIES == 32\n        #define portPRIORITY_SHIFT            3\n        #define portMAX_BINARY_POINT_VALUE    2\n    #elif configUNIQUE_INTERRUPT_PRIORITIES == 64\n        #define portPRIORITY_SHIFT            2\n        #define portMAX_BINARY_POINT_VALUE    1\n    #elif configUNIQUE_INTERRUPT_PRIORITIES == 128\n        #define portPRIORITY_SHIFT            1\n        #define portMAX_BINARY_POINT_VALUE    0\n    #elif configUNIQUE_INTERRUPT_PRIORITIES == 256\n        #define portPRIORITY_SHIFT            0\n        #define portMAX_BINARY_POINT_VALUE    0\n    #else /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */\n        #error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting.  configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware\n    #endif /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */\n\n/* Interrupt controller access addresses. */\n    #define portICCPMR_PRIORITY_MASK_OFFSET                      ( 0x04 )\n    #define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET              ( 0x0C )\n    #define portICCEOIR_END_OF_INTERRUPT_OFFSET                  ( 0x10 )\n    #define portICCBPR_BINARY_POINT_OFFSET                       ( 0x08 )\n    #define portICCRPR_RUNNING_PRIORITY_OFFSET                   ( 0x14 )\n\n    #define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS       ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )\n    #define portICCPMR_PRIORITY_MASK_REGISTER                    ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )\n    #define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS    ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )\n    #define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS        ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )\n    #define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS            ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )\n    #define portICCBPR_BINARY_POINT_REGISTER                     ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )\n    #define portICCRPR_RUNNING_PRIORITY_REGISTER                 ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )\n\n    #define portMEMORY_BARRIER()    __asm volatile ( \"\" ::: \"memory\" )\n\n#endif /* PORTMACRO_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CRx_No_GIC/port.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Standard includes. */\n#include <stdlib.h>\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1\n\t/* Check the configuration. */\n\t#if( configMAX_PRIORITIES > 32 )\n\t\t#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.\n\t#endif\n#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */\n\n#ifndef configSETUP_TICK_INTERRUPT\n\t#error configSETUP_TICK_INTERRUPT() must be defined in FreeRTOSConfig.h to call the function that sets up the tick interrupt.\n#endif\n\n#ifndef configCLEAR_TICK_INTERRUPT\n\t#error configCLEAR_TICK_INTERRUPT must be defined in FreeRTOSConfig.h to clear which ever interrupt was used to generate the tick interrupt.\n#endif\n\n/* A critical section is exited when the critical section nesting count reaches\nthis value. */\n#define portNO_CRITICAL_NESTING\t\t\t( ( uint32_t ) 0 )\n\n/* Tasks are not created with a floating point context, but can be given a\nfloating point context after they have been created.  A variable is stored as\npart of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task\ndoes not have an FPU context, or any other value if the task does have an FPU\ncontext. */\n#define portNO_FLOATING_POINT_CONTEXT\t( ( StackType_t ) 0 )\n\n/* Constants required to setup the initial task context. */\n#define portINITIAL_SPSR\t\t\t\t( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */\n#define portTHUMB_MODE_BIT\t\t\t\t( ( StackType_t ) 0x20 )\n#define portTHUMB_MODE_ADDRESS\t\t\t( 0x01UL )\n\n/* Masks all bits in the APSR other than the mode bits. */\n#define portAPSR_MODE_BITS_MASK\t\t\t( 0x1F )\n\n/* The value of the mode bits in the APSR when the CPU is executing in user\nmode. */\n#define portAPSR_USER_MODE\t\t\t\t( 0x10 )\n\n/* Let the user override the pre-loading of the initial LR with the address of\nprvTaskExitError() in case it messes up unwinding of the stack in the\ndebugger. */\n#ifdef configTASK_RETURN_ADDRESS\n\t#define portTASK_RETURN_ADDRESS\tconfigTASK_RETURN_ADDRESS\n#else\n\t#define portTASK_RETURN_ADDRESS\tprvTaskExitError\n#endif\n\n/*-----------------------------------------------------------*/\n\n/*\n * Starts the first task executing.  This function is necessarily written in\n * assembly code so is implemented in portASM.s.\n */\nextern void vPortRestoreTaskContext( void );\n\n/*\n * Used to catch tasks that attempt to return from their implementing function.\n */\nstatic void prvTaskExitError( void );\n\n/*-----------------------------------------------------------*/\n\n/* A variable is used to keep track of the critical section nesting.  This\nvariable has to be stored as part of the task context and must be initialised to\na non zero value to ensure interrupts don't inadvertently become unmasked before\nthe scheduler starts.  As it is stored as part of the task context it will\nautomatically be set to 0 when the first task is started. */\nvolatile uint32_t ulCriticalNesting = 9999UL;\n\n/* Saved as part of the task context.  If ulPortTaskHasFPUContext is non-zero then\na floating point context must be saved and restored for the task. */\nvolatile uint32_t ulPortTaskHasFPUContext = pdFALSE;\n\n/* Set to 1 to pend a context switch from an ISR. */\nvolatile uint32_t ulPortYieldRequired = pdFALSE;\n\n/* Counts the interrupt nesting depth.  A context switch is only performed if\nif the nesting depth is 0. */\nvolatile uint32_t ulPortInterruptNesting = 0UL;\n\n/* Used in the asm file to clear an interrupt. */\n__attribute__(( used )) const uint32_t ulICCEOIR = configEOI_ADDRESS;\n\n/*-----------------------------------------------------------*/\n\n/*\n * See header file for description.\n */\nStackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )\n{\n\t/* Setup the initial stack of the task.  The stack is set exactly as\n\texpected by the portRESTORE_CONTEXT() macro.\n\n\tThe fist real value on the stack is the status register, which is set for\n\tsystem mode, with interrupts enabled.  A few NULLs are added first to ensure\n\tGDB does not try decoding a non-existent return address. */\n\t*pxTopOfStack = ( StackType_t ) NULL;\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) NULL;\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) NULL;\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;\n\n\tif( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )\n\t{\n\t\t/* The task will start in THUMB mode. */\n\t\t*pxTopOfStack |= portTHUMB_MODE_BIT;\n\t}\n\n\tpxTopOfStack--;\n\n\t/* Next the return address, which in this case is the start of the task. */\n\t*pxTopOfStack = ( StackType_t ) pxCode;\n\tpxTopOfStack--;\n\n\t/* Next all the registers other than the stack pointer. */\n\t*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;\t/* R14 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x12121212;\t/* R12 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x11111111;\t/* R11 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x10101010;\t/* R10 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x09090909;\t/* R9 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x08080808;\t/* R8 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x07070707;\t/* R7 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x06060606;\t/* R6 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x05050505;\t/* R5 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x04040404;\t/* R4 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x03030303;\t/* R3 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x02020202;\t/* R2 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x01010101;\t/* R1 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\n\tpxTopOfStack--;\n\n\t/* The task will start with a critical nesting count of 0 as interrupts are\n\tenabled. */\n\t*pxTopOfStack = portNO_CRITICAL_NESTING;\n\tpxTopOfStack--;\n\n\t/* The task will start without a floating point context.  A task that uses\n\tthe floating point hardware must call vPortTaskUsesFPU() before executing\n\tany floating point instructions. */\n\t*pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;\n\n\treturn pxTopOfStack;\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvTaskExitError( void )\n{\n\t/* A function that implements a task must not exit or attempt to return to\n\tits caller as there is nothing to return to.  If a task wants to exit it\n\tshould instead call vTaskDelete( NULL ).\n\n\tArtificially force an assert() to be triggered if configASSERT() is\n\tdefined, then stop here so application writers can catch the error. */\n\tconfigASSERT( ulPortInterruptNesting == ~0UL );\n\tportDISABLE_INTERRUPTS();\n\tfor( ;; );\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xPortStartScheduler( void )\n{\nuint32_t ulAPSR;\n\n\t/* Only continue if the CPU is not in User mode.  The CPU must be in a\n\tPrivileged mode for the scheduler to start. */\n\t__asm volatile ( \"MRS %0, APSR\" : \"=r\" ( ulAPSR ) :: \"memory\" );\n\tulAPSR &= portAPSR_MODE_BITS_MASK;\n\tconfigASSERT( ulAPSR != portAPSR_USER_MODE );\n\n\tif( ulAPSR != portAPSR_USER_MODE )\n\t{\n\t\t/* Start the timer that generates the tick ISR. */\n\t\tportDISABLE_INTERRUPTS();\n\t\tconfigSETUP_TICK_INTERRUPT();\n\n\t\t/* Start the first task executing. */\n\t\tvPortRestoreTaskContext();\n\t}\n\n\t/* Will only get here if vTaskStartScheduler() was called with the CPU in\n\ta non-privileged mode or the binary point register was not set to its lowest\n\tpossible value.  prvTaskExitError() is referenced to prevent a compiler\n\twarning about it being defined but not referenced in the case that the user\n\tdefines their own exit address. */\n\t( void ) prvTaskExitError;\n\treturn 0;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEndScheduler( void )\n{\n\t/* Not implemented in ports where there is nothing to return to.\n\tArtificially force an assert. */\n\tconfigASSERT( ulCriticalNesting == 1000UL );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEnterCritical( void )\n{\n\tportDISABLE_INTERRUPTS();\n\n\t/* Now interrupts are disabled ulCriticalNesting can be accessed\n\tdirectly.  Increment ulCriticalNesting to keep a count of how many times\n\tportENTER_CRITICAL() has been called. */\n\tulCriticalNesting++;\n\n\t/* This is not the interrupt safe version of the enter critical function so\n\tassert() if it is being called from an interrupt context.  Only API\n\tfunctions that end in \"FromISR\" can be used in an interrupt.  Only assert if\n\tthe critical nesting count is 1 to protect against recursive calls if the\n\tassert function also uses a critical section. */\n\tif( ulCriticalNesting == 1 )\n\t{\n\t\tconfigASSERT( ulPortInterruptNesting == 0 );\n\t}\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortExitCritical( void )\n{\n\tif( ulCriticalNesting > portNO_CRITICAL_NESTING )\n\t{\n\t\t/* Decrement the nesting count as the critical section is being\n\t\texited. */\n\t\tulCriticalNesting--;\n\n\t\t/* If the nesting level has reached zero then all interrupt\n\t\tpriorities must be re-enabled. */\n\t\tif( ulCriticalNesting == portNO_CRITICAL_NESTING )\n\t\t{\n\t\t\t/* Critical nesting has reached zero so all interrupt priorities\n\t\t\tshould be unmasked. */\n\t\t\tportENABLE_INTERRUPTS();\n\t\t}\n\t}\n}\n/*-----------------------------------------------------------*/\n\nvoid FreeRTOS_Tick_Handler( void )\n{\nuint32_t ulInterruptStatus;\n\n\tulInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();\n\n\t/* Increment the RTOS tick. */\n\tif( xTaskIncrementTick() != pdFALSE )\n\t{\n\t\tulPortYieldRequired = pdTRUE;\n\t}\n\n\tportCLEAR_INTERRUPT_MASK_FROM_ISR( ulInterruptStatus );\n\n\tconfigCLEAR_TICK_INTERRUPT();\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortTaskUsesFPU( void )\n{\nuint32_t ulInitialFPSCR = 0;\n\n\t/* A task is registering the fact that it needs an FPU context.  Set the\n\tFPU flag (which is saved as part of the task context). */\n\tulPortTaskHasFPUContext = pdTRUE;\n\n\t/* Initialise the floating point status register. */\n\t__asm volatile ( \"FMXR \tFPSCR, %0\" :: \"r\" (ulInitialFPSCR) : \"memory\" );\n}\n/*-----------------------------------------------------------*/\n\n\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CRx_No_GIC/portASM.S",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n\t.text\n\t.arm\n\n\t.set SYS_MODE,\t0x1f\n\t.set SVC_MODE,\t0x13\n\t.set IRQ_MODE,\t0x12\n\n\t/* Variables and functions. */\n\t.extern ulMaxAPIPriorityMask\n\t.extern _freertos_vector_table\n\t.extern pxCurrentTCB\n\t.extern vTaskSwitchContext\n\t.extern vApplicationIRQHandler\n\t.extern ulPortInterruptNesting\n\t.extern ulPortTaskHasFPUContext\n\t.extern ulICCEOIR\n\t.extern ulPortYieldRequired\n\n\t.global FreeRTOS_IRQ_Handler\n\t.global FreeRTOS_SVC_Handler\n\t.global vPortRestoreTaskContext\n\n\n.macro portSAVE_CONTEXT\n\n\t/* Save the LR and SPSR onto the system mode stack before switching to\n\tsystem mode to save the remaining system mode registers. */\n\tSRSDB\tsp!, #SYS_MODE\n\tCPS\t\t#SYS_MODE\n\tPUSH\t{R0-R12, R14}\n\n\t/* Push the critical nesting count. */\n\tLDR\t\tR2, ulCriticalNestingConst\n\tLDR\t\tR1, [R2]\n\tPUSH\t{R1}\n\n\t/* Does the task have a floating point context that needs saving?  If\n\tulPortTaskHasFPUContext is 0 then no. */\n\tLDR\t\tR2, ulPortTaskHasFPUContextConst\n\tLDR\t\tR3, [R2]\n\tCMP\t\tR3, #0\n\n\t/* Save the floating point context, if any. */\n\tFMRXNE  R1,  FPSCR\n\tVPUSHNE {D0-D15}\n#if configFPU_D32 == 1\n\tVPUSHNE\t{D16-D31}\n#endif /* configFPU_D32 */\n\tPUSHNE\t{R1}\n\n\t/* Save ulPortTaskHasFPUContext itself. */\n\tPUSH\t{R3}\n\n\t/* Save the stack pointer in the TCB. */\n\tLDR\t\tR0, pxCurrentTCBConst\n\tLDR\t\tR1, [R0]\n\tSTR\t\tSP, [R1]\n\n\t.endm\n\n; /**********************************************************************/\n\n.macro portRESTORE_CONTEXT\n\n\t/* Set the SP to point to the stack of the task being restored. */\n\tLDR\t\tR0, pxCurrentTCBConst\n\tLDR\t\tR1, [R0]\n\tLDR\t\tSP, [R1]\n\n\t/* Is there a floating point context to restore?  If the restored\n\tulPortTaskHasFPUContext is zero then no. */\n\tLDR\t\tR0, ulPortTaskHasFPUContextConst\n\tPOP\t\t{R1}\n\tSTR\t\tR1, [R0]\n\tCMP\t\tR1, #0\n\n\t/* Restore the floating point context, if any. */\n\tPOPNE \t{R0}\n#if configFPU_D32 == 1\n\tVPOPNE\t{D16-D31}\n#endif /* configFPU_D32 */\n\tVPOPNE\t{D0-D15}\n\tVMSRNE  FPSCR, R0\n\n\t/* Restore the critical section nesting depth. */\n\tLDR\t\tR0, ulCriticalNestingConst\n\tPOP\t\t{R1}\n\tSTR\t\tR1, [R0]\n\n\t/* Restore all system mode registers other than the SP (which is already\n\tbeing used). */\n\tPOP\t\t{R0-R12, R14}\n\n\t/* Return to the task code, loading CPSR on the way. */\n\tRFEIA\tsp!\n\n\t.endm\n\n\n\n\n/******************************************************************************\n * SVC handler is used to yield.\n *****************************************************************************/\n.align 4\n.type FreeRTOS_SVC_Handler, %function\nFreeRTOS_SVC_Handler:\n\t/* Save the context of the current task and select a new task to run. */\n\tportSAVE_CONTEXT\n\tLDR R0, vTaskSwitchContextConst\n\tBLX\tR0\n\tportRESTORE_CONTEXT\n\n\n/******************************************************************************\n * vPortRestoreTaskContext is used to start the scheduler.\n *****************************************************************************/\n.align 4\n.type vPortRestoreTaskContext, %function\nvPortRestoreTaskContext:\n\t/* Switch to system mode. */\n\tCPS\t\t#SYS_MODE\n\tportRESTORE_CONTEXT\n\n.align 4\n.type FreeRTOS_IRQ_Handler, %function\nFreeRTOS_IRQ_Handler:\n\t/* Return to the interrupted instruction. */\n\tSUB\t\tlr, lr, #4\n\n\t/* Push the return address and SPSR. */\n\tPUSH\t{lr}\n\tMRS\t\tlr, SPSR\n\tPUSH\t{lr}\n\n\t/* Change to supervisor mode to allow reentry. */\n\tCPS\t\t#0x13\n\n\t/* Push used registers. */\n\tPUSH\t{r0-r3, r12}\n\n\t/* Increment nesting count.  r3 holds the address of ulPortInterruptNesting\n\tfor future use.  r1 holds the original ulPortInterruptNesting value for\n\tfuture use. */\n\tLDR\t\tr3, ulPortInterruptNestingConst\n\tLDR\t\tr1, [r3]\n\tADD\t\tr0, r1, #1\n\tSTR\t\tr0, [r3]\n\n\t/* Ensure bit 2 of the stack pointer is clear.  r2 holds the bit 2 value for\n\tfuture use. */\n\tMOV\t\tr0, sp\n\tAND\t\tr2, r0, #4\n\tSUB\t\tsp, sp, r2\n\n\t/* Call the interrupt handler. */\n\tPUSH\t{r0-r3, lr}\n\tLDR\t\tr1, vApplicationIRQHandlerConst\n\tBLX\t\tr1\n\tPOP\t\t{r0-r3, lr}\n\tADD\t\tsp, sp, r2\n\n\tCPSID\ti\n\tDSB\n\tISB\n\n\t/* Write to the EOI register. */\n\tLDR \tr0, ulICCEOIRConst\n\tLDR\t\tr2, [r0]\n\tSTR\t\tr0, [r2]\n\n\t/* Restore the old nesting count. */\n\tSTR\t\tr1, [r3]\n\n\t/* A context switch is never performed if the nesting count is not 0. */\n\tCMP\t\tr1, #0\n\tBNE\t\texit_without_switch\n\n\t/* Did the interrupt request a context switch?  r1 holds the address of\n\tulPortYieldRequired and r0 the value of ulPortYieldRequired for future\n\tuse. */\n\tLDR\t\tr1, ulPortYieldRequiredConst\n\tLDR\t\tr0, [r1]\n\tCMP\t\tr0, #0\n\tBNE\t\tswitch_before_exit\n\nexit_without_switch:\n\t/* No context switch.  Restore used registers, LR_irq and SPSR before\n\treturning. */\n\tPOP\t\t{r0-r3, r12}\n\tCPS\t\t#IRQ_MODE\n\tPOP\t\t{LR}\n\tMSR\t\tSPSR_cxsf, LR\n\tPOP\t\t{LR}\n\tMOVS\tPC, LR\n\nswitch_before_exit:\n\t/* A context swtich is to be performed.  Clear the context switch pending\n\tflag. */\n\tMOV\t\tr0, #0\n\tSTR\t\tr0, [r1]\n\n\t/* Restore used registers, LR-irq and SPSR before saving the context\n\tto the task stack. */\n\tPOP\t\t{r0-r3, r12}\n\tCPS\t\t#IRQ_MODE\n\tPOP\t\t{LR}\n\tMSR\t\tSPSR_cxsf, LR\n\tPOP\t\t{LR}\n\tportSAVE_CONTEXT\n\n\t/* Call the function that selects the new task to execute.\n\tvTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD\n\tinstructions, or 8 byte aligned stack allocated data.  LR does not need\n\tsaving as a new LR will be loaded by portRESTORE_CONTEXT anyway. */\n\tLDR\t\tR0, vTaskSwitchContextConst\n\tBLX\t\tR0\n\n\t/* Restore the context of, and branch to, the task selected to execute\n\tnext. */\n\tportRESTORE_CONTEXT\n\nulICCEOIRConst:\t.word ulICCEOIR\npxCurrentTCBConst: .word pxCurrentTCB\nulCriticalNestingConst: .word ulCriticalNesting\nulPortTaskHasFPUContextConst: .word ulPortTaskHasFPUContext\nvTaskSwitchContextConst: .word vTaskSwitchContext\nvApplicationIRQHandlerConst: .word vApplicationIRQHandler\nulPortInterruptNestingConst: .word ulPortInterruptNesting\nulPortYieldRequiredConst: .word ulPortYieldRequired\n\n.end\n\n\n\n\n\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/GCC/ARM_CRx_No_GIC/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef PORTMACRO_H\n#define PORTMACRO_H\n\n#ifdef __cplusplus\n\textern \"C\" {\n#endif\n\n/*-----------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the given hardware\n * and compiler.\n *\n * These settings should not be altered.\n *-----------------------------------------------------------\n */\n\n/* Type definitions. */\n#define portCHAR\t\tchar\n#define portFLOAT\t\tfloat\n#define portDOUBLE\t\tdouble\n#define portLONG\t\tlong\n#define portSHORT\t\tshort\n#define portSTACK_TYPE\tuint32_t\n#define portBASE_TYPE\tlong\n\ntypedef portSTACK_TYPE StackType_t;\ntypedef long BaseType_t;\ntypedef unsigned long UBaseType_t;\n\ntypedef uint32_t TickType_t;\n#define portMAX_DELAY ( TickType_t ) 0xffffffffUL\n\n/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\nnot need to be guarded with a critical section. */\n#define portTICK_TYPE_IS_ATOMIC 1\n\n/*-----------------------------------------------------------*/\n\n/* Hardware specifics. */\n#define portSTACK_GROWTH\t\t\t( -1 )\n#define portTICK_PERIOD_MS\t\t\t( ( TickType_t ) 1000 / configTICK_RATE_HZ )\n#define portBYTE_ALIGNMENT\t\t\t8\n\n/*-----------------------------------------------------------*/\n\n/* Task utilities. */\n\n/* Called at the end of an ISR that can cause a context switch. */\n#define portEND_SWITCHING_ISR( xSwitchRequired )\\\n{\t\t\t\t\t\t\t\t\t\t\t\t\\\nextern volatile uint32_t ulPortYieldRequired;\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tif( xSwitchRequired != pdFALSE )\t\t\t\\\n\t{\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tulPortYieldRequired = pdTRUE;\t\t\t\\\n\t}\t\t\t\t\t\t\t\t\t\t\t\\\n}\n\n#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\n#define portYIELD() __asm volatile ( \"SWI 0\t\t\\n\"\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t \"ISB\t\t  \" ::: \"memory\" );\n\n\n/*-----------------------------------------------------------\n * Critical section control\n *----------------------------------------------------------*/\n\nextern void vPortEnterCritical( void );\nextern void vPortExitCritical( void );\nextern uint32_t ulPortSetInterruptMask( void );\nextern void vPortClearInterruptMask( uint32_t ulNewMaskValue );\nextern void vPortInstallFreeRTOSVectorTable( void );\n\n/* The I bit within the CPSR. */\n#define portINTERRUPT_ENABLE_BIT\t( 1 << 7 )\n\n/* In the absence of a priority mask register, these functions and macros\nglobally enable and disable interrupts. */\n#define portENTER_CRITICAL()\t\tvPortEnterCritical();\n#define portEXIT_CRITICAL()\t\t\tvPortExitCritical();\n#define portENABLE_INTERRUPTS()\t\t__asm volatile ( \"CPSIE i \t\\n\"\t::: \"memory\" );\n#define portDISABLE_INTERRUPTS()\t__asm volatile ( \"CPSID i \t\\n\"\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\t \"DSB\t\t\\n\"\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\t \"ISB\t\t  \" ::: \"memory\" );\n\n__attribute__( ( always_inline ) ) static __inline uint32_t portINLINE_SET_INTERRUPT_MASK_FROM_ISR( void )\n{\nvolatile uint32_t ulCPSR;\n\n\t__asm volatile ( \"MRS %0, CPSR\" : \"=r\" (ulCPSR) :: \"memory\" );\n\tulCPSR &= portINTERRUPT_ENABLE_BIT;\n\tportDISABLE_INTERRUPTS();\n\treturn ulCPSR;\n}\n\n#define portSET_INTERRUPT_MASK_FROM_ISR() portINLINE_SET_INTERRUPT_MASK_FROM_ISR()\n#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)\tdo { if( x == 0 ) portENABLE_INTERRUPTS(); } while( 0 )\n\n/*-----------------------------------------------------------*/\n\n/* Task function macros as described on the FreeRTOS.org WEB site.  These are\nnot required for this port but included in case common demo code that uses these\nmacros is used. */\n#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )\tvoid vFunction( void *pvParameters )\n#define portTASK_FUNCTION( vFunction, pvParameters )\tvoid vFunction( void *pvParameters )\n\n/* Tickless idle/low power functionality. */\n#ifndef portSUPPRESS_TICKS_AND_SLEEP\n\textern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );\n\t#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )\n#endif\n\n/* Prototype of the FreeRTOS tick handler.  This must be installed as the\nhandler for whichever peripheral is used to generate the RTOS tick. */\nvoid FreeRTOS_Tick_Handler( void );\n\n/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()\nbefore any floating point instructions are executed. */\nvoid vPortTaskUsesFPU( void );\n#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()\n\n#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )\n#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )\n\n/* Architecture specific optimisations. */\n#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION\n\t#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1\n#endif\n\n#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1\n\n\t/* Store/clear the ready priorities in a bit map. */\n\t#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )\n\t#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )\n\n\t/*-----------------------------------------------------------*/\n\n\t#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __builtin_clz( uxReadyPriorities ) )\n\n#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */\n\n#define portNOP() __asm volatile( \"NOP\" )\n#define portINLINE __inline\n\n#define portMEMORY_BARRIER() __asm volatile( \"\" ::: \"memory\" )\n\n#ifdef __cplusplus\n\t} /* extern C */\n#endif\n\n\n#endif /* PORTMACRO_H */\n\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CA5_No_GIC/port.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* IAR includes. */\n#include <intrinsics.h>\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1\n\t/* Check the configuration. */\n\t#if( configMAX_PRIORITIES > 32 )\n\t\t#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.\n\t#endif\n#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */\n\n#ifndef configSETUP_TICK_INTERRUPT\n\t#error configSETUP_TICK_INTERRUPT() must be defined in FreeRTOSConfig.h to call the function that sets up the tick interrupt.  A default that uses the PIT is provided in the official demo application.\n#endif\n\n#ifndef configCLEAR_TICK_INTERRUPT\n\t#error configCLEAR_TICK_INTERRUPT must be defined in FreeRTOSConfig.h to clear which ever interrupt was used to generate the tick interrupt.  A default that uses the PIT is provided in the official demo application.\n#endif\n\n/* A critical section is exited when the critical section nesting count reaches\nthis value. */\n#define portNO_CRITICAL_NESTING\t\t\t( ( uint32_t ) 0 )\n\n/* Tasks are not created with a floating point context, but can be given a\nfloating point context after they have been created.  A variable is stored as\npart of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task\ndoes not have an FPU context, or any other value if the task does have an FPU\ncontext. */\n#define portNO_FLOATING_POINT_CONTEXT\t( ( StackType_t ) 0 )\n\n/* Constants required to setup the initial task context. */\n#define portINITIAL_SPSR\t\t\t\t( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */\n#define portTHUMB_MODE_BIT\t\t\t\t( ( StackType_t ) 0x20 )\n#define portTHUMB_MODE_ADDRESS\t\t\t( 0x01UL )\n\n/* Masks all bits in the APSR other than the mode bits. */\n#define portAPSR_MODE_BITS_MASK\t\t\t( 0x1F )\n\n/* The value of the mode bits in the APSR when the CPU is executing in user\nmode. */\n#define portAPSR_USER_MODE\t\t\t\t( 0x10 )\n\n/*-----------------------------------------------------------*/\n\n/*\n * Starts the first task executing.  This function is necessarily written in\n * assembly code so is implemented in portASM.s.\n */\nextern void vPortRestoreTaskContext( void );\n\n/*\n * Used to catch tasks that attempt to return from their implementing function.\n */\nstatic void prvTaskExitError( void );\n\n/*-----------------------------------------------------------*/\n\n/* A variable is used to keep track of the critical section nesting.  This\nvariable has to be stored as part of the task context and must be initialised to\na non zero value to ensure interrupts don't inadvertently become unmasked before\nthe scheduler starts.  As it is stored as part of the task context it will\nautomatically be set to 0 when the first task is started. */\nvolatile uint32_t ulCriticalNesting = 9999UL;\n\n/* Saved as part of the task context.  If ulPortTaskHasFPUContext is non-zero\nthen a floating point context must be saved and restored for the task. */\nuint32_t ulPortTaskHasFPUContext = pdFALSE;\n\n/* Set to 1 to pend a context switch from an ISR. */\nuint32_t ulPortYieldRequired = pdFALSE;\n\n/* Counts the interrupt nesting depth.  A context switch is only performed if\nif the nesting depth is 0. */\nuint32_t ulPortInterruptNesting = 0UL;\n\n\n/*-----------------------------------------------------------*/\n\n/*\n * See header file for description.\n */\nStackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )\n{\n\t/* Setup the initial stack of the task.  The stack is set exactly as\n\texpected by the portRESTORE_CONTEXT() macro.\n\n\tThe fist real value on the stack is the status register, which is set for\n\tsystem mode, with interrupts enabled.  A few NULLs are added first to ensure\n\tGDB does not try decoding a non-existent return address. */\n\t*pxTopOfStack = NULL;\n\tpxTopOfStack--;\n\t*pxTopOfStack = NULL;\n\tpxTopOfStack--;\n\t*pxTopOfStack = NULL;\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;\n\n\tif( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )\n\t{\n\t\t/* The task will start in THUMB mode. */\n\t\t*pxTopOfStack |= portTHUMB_MODE_BIT;\n\t}\n\n\tpxTopOfStack--;\n\n\t/* Next the return address, which in this case is the start of the task. */\n\t*pxTopOfStack = ( StackType_t ) pxCode;\n\tpxTopOfStack--;\n\n\t/* Next all the registers other than the stack pointer. */\n\t*pxTopOfStack = ( StackType_t ) prvTaskExitError;\t/* R14 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x12121212;\t/* R12 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x11111111;\t/* R11 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x10101010;\t/* R10 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x09090909;\t/* R9 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x08080808;\t/* R8 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x07070707;\t/* R7 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x06060606;\t/* R6 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x05050505;\t/* R5 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x04040404;\t/* R4 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x03030303;\t/* R3 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x02020202;\t/* R2 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x01010101;\t/* R1 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\n\tpxTopOfStack--;\n\n\t/* The task will start with a critical nesting count of 0 as interrupts are\n\tenabled. */\n\t*pxTopOfStack = portNO_CRITICAL_NESTING;\n\tpxTopOfStack--;\n\n\t/* The task will start without a floating point context.  A task that uses\n\tthe floating point hardware must call vPortTaskUsesFPU() before executing\n\tany floating point instructions. */\n\t*pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;\n\n\treturn pxTopOfStack;\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvTaskExitError( void )\n{\n\t/* A function that implements a task must not exit or attempt to return to\n\tits caller as there is nothing to return to.  If a task wants to exit it\n\tshould instead call vTaskDelete( NULL ).\n\n\tArtificially force an assert() to be triggered if configASSERT() is\n\tdefined, then stop here so application writers can catch the error. */\n\tconfigASSERT( ulPortInterruptNesting == ~0UL );\n\tportDISABLE_INTERRUPTS();\n\tfor( ;; );\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xPortStartScheduler( void )\n{\nuint32_t ulAPSR;\n\n\t/* Only continue if the CPU is not in User mode.  The CPU must be in a\n\tPrivileged mode for the scheduler to start. */\n\t__asm volatile ( \"MRS %0, APSR\" : \"=r\" ( ulAPSR ) );\n\tulAPSR &= portAPSR_MODE_BITS_MASK;\n\tconfigASSERT( ulAPSR != portAPSR_USER_MODE );\n\n\tif( ulAPSR != portAPSR_USER_MODE )\n\t{\n\t\t/* Start the timer that generates the tick ISR. */\n\t\tconfigSETUP_TICK_INTERRUPT();\n\t\tvPortRestoreTaskContext();\n\t}\n\n\t/* Will only get here if vTaskStartScheduler() was called with the CPU in\n\ta non-privileged mode or the binary point register was not set to its lowest\n\tpossible value. */\n\treturn 0;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEndScheduler( void )\n{\n\t/* Not implemented in ports where there is nothing to return to.\n\tArtificially force an assert. */\n\tconfigASSERT( ulCriticalNesting == 1000UL );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEnterCritical( void )\n{\n\tportDISABLE_INTERRUPTS();\n\n\t/* Now interrupts are disabled ulCriticalNesting can be accessed\n\tdirectly.  Increment ulCriticalNesting to keep a count of how many times\n\tportENTER_CRITICAL() has been called. */\n\tulCriticalNesting++;\n\n\t/* This is not the interrupt safe version of the enter critical function so\n\tassert() if it is being called from an interrupt context.  Only API\n\tfunctions that end in \"FromISR\" can be used in an interrupt.  Only assert if\n\tthe critical nesting count is 1 to protect against recursive calls if the\n\tassert function also uses a critical section. */\n\tif( ulCriticalNesting == 1 )\n\t{\n\t\tconfigASSERT( ulPortInterruptNesting == 0 );\n\t}\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortExitCritical( void )\n{\n\tif( ulCriticalNesting > portNO_CRITICAL_NESTING )\n\t{\n\t\t/* Decrement the nesting count as the critical section is being\n\t\texited. */\n\t\tulCriticalNesting--;\n\n\t\t/* If the nesting level has reached zero then all interrupt\n\t\tpriorities must be re-enabled. */\n\t\tif( ulCriticalNesting == portNO_CRITICAL_NESTING )\n\t\t{\n\t\t\t/* Critical nesting has reached zero so all interrupt priorities\n\t\t\tshould be unmasked. */\n\t\t\tportENABLE_INTERRUPTS();\n\t\t}\n\t}\n}\n/*-----------------------------------------------------------*/\n\nvoid FreeRTOS_Tick_Handler( void )\n{\n\tportDISABLE_INTERRUPTS();\n\n\t/* Increment the RTOS tick. */\n\tif( xTaskIncrementTick() != pdFALSE )\n\t{\n\t\tulPortYieldRequired = pdTRUE;\n\t}\n\n\tportENABLE_INTERRUPTS();\n\tconfigCLEAR_TICK_INTERRUPT();\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortTaskUsesFPU( void )\n{\nuint32_t ulInitialFPSCR = 0;\n\n\t/* A task is registering the fact that it needs an FPU context.  Set the\n\tFPU flag (which is saved as part of the task context). */\n\tulPortTaskHasFPUContext = pdTRUE;\n\n\t/* Initialise the floating point status register. */\n\t__asm( \"FMXR \tFPSCR, %0\" :: \"r\" (ulInitialFPSCR) );\n}\n/*-----------------------------------------------------------*/\n\n\n\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CA5_No_GIC/portASM.h",
    "content": ";/*\n; * FreeRTOS Kernel V10.5.1\n; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n; *\n; * SPDX-License-Identifier: MIT\n; *\n; * Permission is hereby granted, free of charge, to any person obtaining a copy of\n; * this software and associated documentation files (the \"Software\"), to deal in\n; * the Software without restriction, including without limitation the rights to\n; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n; * the Software, and to permit persons to whom the Software is furnished to do so,\n; * subject to the following conditions:\n; *\n; * The above copyright notice and this permission notice shall be included in all\n; * copies or substantial portions of the Software.\n; *\n; * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n; *\n; * https://www.FreeRTOS.org\n; * https://github.com/FreeRTOS\n; *\n; */\n\n\tEXTERN\tvTaskSwitchContext\n\tEXTERN  ulCriticalNesting\n\tEXTERN\tpxCurrentTCB\n\tEXTERN\tulPortTaskHasFPUContext\n\tEXTERN  ulAsmAPIPriorityMask\n\nportSAVE_CONTEXT macro\n\n\t; Save the LR and SPSR onto the system mode stack before switching to\n\t; system mode to save the remaining system mode registers\n\tSRSDB\tsp!, #SYS_MODE\n\tCPS\t\t#SYS_MODE\n\tPUSH\t{R0-R12, R14}\n\n\t; Push the critical nesting count\n\tLDR\t\tR2, =ulCriticalNesting\n\tLDR\t\tR1, [R2]\n\tPUSH\t{R1}\n\n\t; Does the task have a floating point context that needs saving?  If\n\t; ulPortTaskHasFPUContext is 0 then no.\n\tLDR\t\tR2, =ulPortTaskHasFPUContext\n\tLDR\t\tR3, [R2]\n\tCMP\t\tR3, #0\n\n\t; Save the floating point context, if any\n\tFMRXNE  R1,  FPSCR\n\tVPUSHNE {D0-D15}\n#if configFPU_D32 == 1\n\tVPUSHNE\t{D16-D31}\n#endif ; configFPU_D32\n\tPUSHNE\t{R1}\n\n\t; Save ulPortTaskHasFPUContext itself\n\tPUSH\t{R3}\n\n\t; Save the stack pointer in the TCB\n\tLDR\t\tR0, =pxCurrentTCB\n\tLDR\t\tR1, [R0]\n\tSTR\t\tSP, [R1]\n\n\tendm\n\n; /**********************************************************************/\n\nportRESTORE_CONTEXT macro\n\n\t; Set the SP to point to the stack of the task being restored.\n\tLDR\t\tR0, =pxCurrentTCB\n\tLDR\t\tR1, [R0]\n\tLDR\t\tSP, [R1]\n\n\t; Is there a floating point context to restore?  If the restored\n\t; ulPortTaskHasFPUContext is zero then no.\n\tLDR\t\tR0, =ulPortTaskHasFPUContext\n\tPOP\t\t{R1}\n\tSTR\t\tR1, [R0]\n\tCMP\t\tR1, #0\n\n\t; Restore the floating point context, if any\n\tPOPNE \t{R0}\n#if configFPU_D32 == 1\n\tVPOPNE\t{D16-D31}\n#endif ; configFPU_D32\n\tVPOPNE\t{D0-D15}\n\tVMSRNE  FPSCR, R0\n\n\t; Restore the critical section nesting depth\n\tLDR\t\tR0, =ulCriticalNesting\n\tPOP\t\t{R1}\n\tSTR\t\tR1, [R0]\n\n\t; Restore all system mode registers other than the SP (which is already\n\t; being used)\n\tPOP\t\t{R0-R12, R14}\n\n\t; Return to the task code, loading CPSR on the way.  CPSR has the interrupt\n\t; enable bit set appropriately for the task about to execute.\n\tRFEIA\tsp!\n\n\tendm\n\n\n\n\n\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CA5_No_GIC/portASM.s",
    "content": ";/*\n; * FreeRTOS Kernel V10.5.1\n; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n; *\n; * SPDX-License-Identifier: MIT\n; *\n; * Permission is hereby granted, free of charge, to any person obtaining a copy of\n; * this software and associated documentation files (the \"Software\"), to deal in\n; * the Software without restriction, including without limitation the rights to\n; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n; * the Software, and to permit persons to whom the Software is furnished to do so,\n; * subject to the following conditions:\n; *\n; * The above copyright notice and this permission notice shall be included in all\n; * copies or substantial portions of the Software.\n; *\n; * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n; *\n; * https://www.FreeRTOS.org\n; * https://github.com/FreeRTOS\n; *\n; */\n\n\tINCLUDE FreeRTOSConfig.h\n\tINCLUDE portmacro.h\n\n\tEXTERN\tvTaskSwitchContext\n\tEXTERN\tulPortYieldRequired\n\tEXTERN\tulPortInterruptNesting\n\tEXTERN\tvApplicationIRQHandler\n\n\tPUBLIC\tFreeRTOS_SWI_Handler\n\tPUBLIC  FreeRTOS_IRQ_Handler\n\tPUBLIC \tvPortRestoreTaskContext\n\nSYS_MODE\t\t\tEQU\t\t0x1f\nSVC_MODE\t\t\tEQU\t\t0x13\nIRQ_MODE\t\t\tEQU\t\t0x12\n\n\tSECTION .text:CODE:ROOT(2)\n\tARM\n\n\tINCLUDE portASM.h\n\n;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n; SVC handler is used to yield a task.\n;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\nFreeRTOS_SWI_Handler\n\n\tPRESERVE8\n\n\t; Save the context of the current task and select a new task to run.\n\tportSAVE_CONTEXT\n\tLDR R0, =vTaskSwitchContext\n\tBLX\tR0\n\tportRESTORE_CONTEXT\n\n;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n; vPortRestoreTaskContext is used to start the scheduler.\n;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\nvPortRestoreTaskContext\n\n\tPRESERVE8\n\n\t; Switch to system mode\n\tCPS\t\t#SYS_MODE\n\tportRESTORE_CONTEXT\n\n;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n; IRQ interrupt handler used when individual priorities cannot be masked\n;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\nFreeRTOS_IRQ_Handler\n\n\tPRESERVE8\n\n\t; Return to the interrupted instruction.\n\tSUB\t\tlr, lr, #4\n\n\t; Push the return address and SPSR\n\tPUSH\t{lr}\n\tMRS\t\tlr, SPSR\n\tPUSH\t{lr}\n\n\t; Change to supervisor mode to allow reentry.\n\tCPS\t\t#SVC_MODE\n\n\t; Push used registers.\n\tPUSH\t{r0-r4, r12}\n\n\t; Increment nesting count.  r3 holds the address of ulPortInterruptNesting\n\t; for future use.  r1 holds the original ulPortInterruptNesting value for\n\t; future use.\n\tLDR\t\tr3, =ulPortInterruptNesting\n\tLDR\t\tr1, [r3]\n\tADD\t\tr4, r1, #1\n\tSTR\t\tr4, [r3]\n\n\t; Ensure bit 2 of the stack pointer is clear.  r2 holds the bit 2 value for\n\t; future use.\n\tMOV\t\tr2, sp\n\tAND\t\tr2, r2, #4\n\tSUB\t\tsp, sp, r2\n\n\tPUSH\t{r0-r4, lr}\n\n\t; Call the port part specific handler.\n\tLDR\t\tr0, =vApplicationIRQHandler\n\tBLX\t\tr0\n\tPOP\t\t{r0-r4, lr}\n\tADD\t\tsp, sp, r2\n\n\tCPSID\ti\n\n\t; Write to the EOI register.\n\tLDR \tr4, =configEOI_ADDRESS\n\tSTR\t\tr0, [r4]\n\n\t; Restore the old nesting count\n\tSTR\t\tr1, [r3]\n\n\t; A context switch is never performed if the nesting count is not 0.\n\tCMP\t\tr1, #0\n\tBNE\t\texit_without_switch\n\n\t; Did the interrupt request a context switch?  r1 holds the address of\n\t; ulPortYieldRequired and r0 the value of ulPortYieldRequired for future\n\t; use.\n\tLDR\t\tr1, =ulPortYieldRequired\n\tLDR\t\tr0, [r1]\n\tCMP\t\tr0, #0\n\tBNE\t\tswitch_before_exit\n\nexit_without_switch\n\t; No context switch.  Restore used registers, LR_irq and SPSR before\n\t; returning.\n\tPOP\t\t{r0-r4, r12}\n\tCPS\t\t#IRQ_MODE\n\tPOP\t\t{LR}\n\tMSR\t\tSPSR_cxsf, LR\n\tPOP\t\t{LR}\n\tMOVS\tPC, LR\n\nswitch_before_exit\n\t; A context switch is to be performed.  Clear the context switch pending\n\t; flag.\n\tMOV\t\tr0, #0\n\tSTR\t\tr0, [r1]\n\n\t; Restore used registers, LR-irq and SPSR before saving the context\n\t; to the task stack.\n\tPOP\t\t{r0-r4, r12}\n\tCPS\t\t#IRQ_MODE\n\tPOP\t\t{LR}\n\tMSR\t\tSPSR_cxsf, LR\n\tPOP\t\t{LR}\n\tportSAVE_CONTEXT\n\n\t; Call the function that selects the new task to execute.\n\t; vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD\n\t; instructions, or 8 byte aligned stack allocated data.  LR does not need\n\t; saving as a new LR will be loaded by portRESTORE_CONTEXT anyway.\n\tLDR\t\tr0, =vTaskSwitchContext\n\tBLX\t\tr0\n\n\t; Restore the context of, and branch to, the task selected to execute next.\n\tportRESTORE_CONTEXT\n\n\tEND\n\n\n\n\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CA5_No_GIC/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef PORTMACRO_H\n#define PORTMACRO_H\n\n/* IAR includes. */\n#ifdef __ICCARM__\n\n\t#include <intrinsics.h>\n\n\t#ifdef __cplusplus\n\t\textern \"C\" {\n\t#endif\n\n\t/*-----------------------------------------------------------\n\t * Port specific definitions.\n\t *\n\t * The settings in this file configure FreeRTOS correctly for the given hardware\n\t * and compiler.\n\t *\n\t * These settings should not be altered.\n\t *-----------------------------------------------------------\n\t */\n\n\t/* Type definitions. */\n\t#define portCHAR\t\tchar\n\t#define portFLOAT\t\tfloat\n\t#define portDOUBLE\t\tdouble\n\t#define portLONG\t\tlong\n\t#define portSHORT\t\tshort\n\t#define portSTACK_TYPE\tuint32_t\n\t#define portBASE_TYPE\tlong\n\n\ttypedef portSTACK_TYPE StackType_t;\n\ttypedef long BaseType_t;\n\ttypedef unsigned long UBaseType_t;\n\n\ttypedef uint32_t TickType_t;\n\t#define portMAX_DELAY ( TickType_t ) 0xffffffffUL\n\n\t/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\n\tnot need to be guarded with a critical section. */\n\t#define portTICK_TYPE_IS_ATOMIC 1\n\n\t/*-----------------------------------------------------------*/\n\n\t/* Hardware specifics. */\n\t#define portSTACK_GROWTH\t\t\t( -1 )\n\t#define portTICK_PERIOD_MS\t\t\t( ( TickType_t ) 1000 / configTICK_RATE_HZ )\n\t#define portBYTE_ALIGNMENT\t\t\t8\n\n\t/*-----------------------------------------------------------*/\n\n\t/* Task utilities. */\n\n\t/* Called at the end of an ISR that can cause a context switch. */\n\t#define portEND_SWITCHING_ISR( xSwitchRequired )\\\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\\\n\textern uint32_t ulPortYieldRequired;\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tif( xSwitchRequired != pdFALSE )\t\t\t\\\n\t\t{\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\tulPortYieldRequired = pdTRUE;\t\t\t\\\n\t\t}\t\t\t\t\t\t\t\t\t\t\t\\\n\t}\n\n\t#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\n\t#define portYIELD() __asm volatile ( \"SWI 0\" ); __ISB()\n\n\n\t/*-----------------------------------------------------------\n\t * Critical section control\n\t *----------------------------------------------------------*/\n\n\textern void vPortEnterCritical( void );\n\textern void vPortExitCritical( void );\n\textern uint32_t ulPortSetInterruptMask( void );\n\textern void vPortClearInterruptMask( uint32_t ulNewMaskValue );\n\n\t#define portENTER_CRITICAL()\t\tvPortEnterCritical();\n\t#define portEXIT_CRITICAL()\t\t\tvPortExitCritical();\n\t#define portDISABLE_INTERRUPTS()\t__disable_irq(); __DSB(); __ISB() /* No priority mask register so global disable is used. */\n\t#define portENABLE_INTERRUPTS()\t\t__enable_irq()\n\t#define portSET_INTERRUPT_MASK_FROM_ISR()\t\t__get_interrupt_state(); __disable_irq() /* No priority mask register so global disable is used. */\n\t#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)\t__set_interrupt_state(x)\n\n\t/*-----------------------------------------------------------*/\n\n\t/* Task function macros as described on the FreeRTOS.org WEB site.  These are\n\tnot required for this port but included in case common demo code that uses these\n\tmacros is used. */\n\t#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )\tvoid vFunction( void *pvParameters )\n\t#define portTASK_FUNCTION( vFunction, pvParameters )\tvoid vFunction( void *pvParameters )\n\n\t/* Prototype of the FreeRTOS tick handler.  This must be installed as the\n\thandler for whichever peripheral is used to generate the RTOS tick. */\n\tvoid FreeRTOS_Tick_Handler( void );\n\n\t/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()\n\tbefore any floating point instructions are executed. */\n\tvoid vPortTaskUsesFPU( void );\n\t#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()\n\n\t/* Architecture specific optimisations. */\n\t#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION\n\t\t#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1\n\t#endif\n\n\t#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1\n\n\t\t/* Store/clear the ready priorities in a bit map. */\n\t\t#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )\n\t\t#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )\n\n\t\t/*-----------------------------------------------------------*/\n\n\t\t#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __CLZ( uxReadyPriorities ) )\n\n\t#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */\n\n\t#define portNOP() __asm volatile( \"NOP\" )\n\n\n\t#ifdef __cplusplus\n\t\t} /* extern C */\n\t#endif\n\n\t/* Suppress warnings that are generated by the IAR tools, but cannot be\n\tfixed in the source code because to do so would cause other compilers to\n\tgenerate warnings. */\n\t#pragma diag_suppress=Pe191\n\t#pragma diag_suppress=Pa082\n\n#endif /* __ICCARM__ */\n\n#endif /* PORTMACRO_H */\n\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CA9/port.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Standard includes. */\n#include <stdlib.h>\n\n/* IAR includes. */\n#include <intrinsics.h>\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n#ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS\n\t#error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html\n#endif\n\n#ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET\n\t#error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html\n#endif\n\n#ifndef configUNIQUE_INTERRUPT_PRIORITIES\n\t#error configUNIQUE_INTERRUPT_PRIORITIES must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html\n#endif\n\n#ifndef configSETUP_TICK_INTERRUPT\n\t#error configSETUP_TICK_INTERRUPT() must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html\n#endif /* configSETUP_TICK_INTERRUPT */\n\n#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY\n\t#error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html\n#endif\n\n#if configMAX_API_CALL_INTERRUPT_PRIORITY == 0\n\t#error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0\n#endif\n\n#if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES\n\t#error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority\n#endif\n\n#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1\n\t/* Check the configuration. */\n\t#if( configMAX_PRIORITIES > 32 )\n\t\t#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.\n\t#endif\n#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */\n\n/* In case security extensions are implemented. */\n#if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )\n\t#error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )\n#endif\n\n#ifndef configCLEAR_TICK_INTERRUPT\n\t#define configCLEAR_TICK_INTERRUPT()\n#endif\n\n/* A critical section is exited when the critical section nesting count reaches\nthis value. */\n#define portNO_CRITICAL_NESTING\t\t\t( ( uint32_t ) 0 )\n\n/* In all GICs 255 can be written to the priority mask register to unmask all\n(but the lowest) interrupt priority. */\n#define portUNMASK_VALUE\t\t\t\t( 0xFFUL )\n\n/* Tasks are not created with a floating point context, but can be given a\nfloating point context after they have been created.  A variable is stored as\npart of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task\ndoes not have an FPU context, or any other value if the task does have an FPU\ncontext. */\n#define portNO_FLOATING_POINT_CONTEXT\t( ( StackType_t ) 0 )\n\n/* Constants required to setup the initial task context. */\n#define portINITIAL_SPSR\t\t\t\t( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */\n#define portTHUMB_MODE_BIT\t\t\t\t( ( StackType_t ) 0x20 )\n#define portTHUMB_MODE_ADDRESS\t\t\t( 0x01UL )\n\n/* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary\npoint is zero. */\n#define portBINARY_POINT_BITS\t\t\t( ( uint8_t ) 0x03 )\n\n/* Masks all bits in the APSR other than the mode bits. */\n#define portAPSR_MODE_BITS_MASK\t\t\t( 0x1F )\n\n/* The value of the mode bits in the APSR when the CPU is executing in user\nmode. */\n#define portAPSR_USER_MODE\t\t\t\t( 0x10 )\n\n/* Macro to unmask all interrupt priorities. */\n#define portCLEAR_INTERRUPT_MASK()\t\t\t\t\t\t\t\t\t\t\t\\\n{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t__disable_irq();\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tportICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE;\t\t\t\t\t\\\n\t__asm(\t\"DSB\t\t\\n\"\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\"ISB\t\t\\n\" );\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t__enable_irq();\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n}\n\n/*-----------------------------------------------------------*/\n\n/*\n * Starts the first task executing.  This function is necessarily written in\n * assembly code so is implemented in portASM.s.\n */\nextern void vPortRestoreTaskContext( void );\n\n/*\n * Used to catch tasks that attempt to return from their implementing function.\n */\nstatic void prvTaskExitError( void );\n\n/*-----------------------------------------------------------*/\n\n/* A variable is used to keep track of the critical section nesting.  This\nvariable has to be stored as part of the task context and must be initialised to\na non zero value to ensure interrupts don't inadvertently become unmasked before\nthe scheduler starts.  As it is stored as part of the task context it will\nautomatically be set to 0 when the first task is started. */\nvolatile uint32_t ulCriticalNesting = 9999UL;\n\n/* Saved as part of the task context.  If ulPortTaskHasFPUContext is non-zero\nthen a floating point context must be saved and restored for the task. */\nuint32_t ulPortTaskHasFPUContext = pdFALSE;\n\n/* Set to 1 to pend a context switch from an ISR. */\nuint32_t ulPortYieldRequired = pdFALSE;\n\n/* Counts the interrupt nesting depth.  A context switch is only performed if\nif the nesting depth is 0. */\nuint32_t ulPortInterruptNesting = 0UL;\n\n\n/*-----------------------------------------------------------*/\n\n/*\n * See header file for description.\n */\nStackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )\n{\n\t/* Setup the initial stack of the task.  The stack is set exactly as\n\texpected by the portRESTORE_CONTEXT() macro.\n\n\tThe fist real value on the stack is the status register, which is set for\n\tsystem mode, with interrupts enabled.  A few NULLs are added first to ensure\n\tGDB does not try decoding a non-existent return address. */\n\t*pxTopOfStack = NULL;\n\tpxTopOfStack--;\n\t*pxTopOfStack = NULL;\n\tpxTopOfStack--;\n\t*pxTopOfStack = NULL;\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;\n\n\tif( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )\n\t{\n\t\t/* The task will start in THUMB mode. */\n\t\t*pxTopOfStack |= portTHUMB_MODE_BIT;\n\t}\n\n\tpxTopOfStack--;\n\n\t/* Next the return address, which in this case is the start of the task. */\n\t*pxTopOfStack = ( StackType_t ) pxCode;\n\tpxTopOfStack--;\n\n\t/* Next all the registers other than the stack pointer. */\n\t*pxTopOfStack = ( StackType_t ) prvTaskExitError;\t/* R14 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x12121212;\t/* R12 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x11111111;\t/* R11 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x10101010;\t/* R10 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x09090909;\t/* R9 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x08080808;\t/* R8 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x07070707;\t/* R7 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x06060606;\t/* R6 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x05050505;\t/* R5 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x04040404;\t/* R4 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x03030303;\t/* R3 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x02020202;\t/* R2 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x01010101;\t/* R1 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\n\tpxTopOfStack--;\n\n\t/* The task will start with a critical nesting count of 0 as interrupts are\n\tenabled. */\n\t*pxTopOfStack = portNO_CRITICAL_NESTING;\n\tpxTopOfStack--;\n\n\t/* The task will start without a floating point context.  A task that uses\n\tthe floating point hardware must call vPortTaskUsesFPU() before executing\n\tany floating point instructions. */\n\t*pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;\n\n\treturn pxTopOfStack;\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvTaskExitError( void )\n{\n\t/* A function that implements a task must not exit or attempt to return to\n\tits caller as there is nothing to return to.  If a task wants to exit it\n\tshould instead call vTaskDelete( NULL ).\n\n\tArtificially force an assert() to be triggered if configASSERT() is\n\tdefined, then stop here so application writers can catch the error. */\n\tconfigASSERT( ulPortInterruptNesting == ~0UL );\n\tportDISABLE_INTERRUPTS();\n\tfor( ;; );\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xPortStartScheduler( void )\n{\nuint32_t ulAPSR;\n\n\t/* Only continue if the CPU is not in User mode.  The CPU must be in a\n\tPrivileged mode for the scheduler to start. */\n\t__asm volatile ( \"MRS %0, APSR\" : \"=r\" ( ulAPSR ) );\n\tulAPSR &= portAPSR_MODE_BITS_MASK;\n\tconfigASSERT( ulAPSR != portAPSR_USER_MODE );\n\n\tif( ulAPSR != portAPSR_USER_MODE )\n\t{\n\t\t/* Only continue if the binary point value is set to its lowest possible\n\t\tsetting.  See the comments in vPortValidateInterruptPriority() below for\n\t\tmore information. */\n\t\tconfigASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );\n\n\t\tif( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )\n\t\t{\n\t\t\t/* Start the timer that generates the tick ISR. */\n\t\t\tconfigSETUP_TICK_INTERRUPT();\n\n\t\t\t__enable_irq();\n\t\t\tvPortRestoreTaskContext();\n\t\t}\n\t}\n\n\t/* Will only get here if vTaskStartScheduler() was called with the CPU in\n\ta non-privileged mode or the binary point register was not set to its lowest\n\tpossible value. */\n\treturn 0;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEndScheduler( void )\n{\n\t/* Not implemented in ports where there is nothing to return to.\n\tArtificially force an assert. */\n\tconfigASSERT( ulCriticalNesting == 1000UL );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEnterCritical( void )\n{\n\t/* Disable interrupts as per portDISABLE_INTERRUPTS(); \t*/\n\tulPortSetInterruptMask();\n\n\t/* Now interrupts are disabled ulCriticalNesting can be accessed\n\tdirectly.  Increment ulCriticalNesting to keep a count of how many times\n\tportENTER_CRITICAL() has been called. */\n\tulCriticalNesting++;\n\t\n\t/* This is not the interrupt safe version of the enter critical function so\n\tassert() if it is being called from an interrupt context.  Only API \n\tfunctions that end in \"FromISR\" can be used in an interrupt.  Only assert if\n\tthe critical nesting count is 1 to protect against recursive calls if the\n\tassert function also uses a critical section. */\n\tif( ulCriticalNesting == 1 )\n\t{\n\t\tconfigASSERT( ulPortInterruptNesting == 0 );\n\t}\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortExitCritical( void )\n{\n\tif( ulCriticalNesting > portNO_CRITICAL_NESTING )\n\t{\n\t\t/* Decrement the nesting count as the critical section is being\n\t\texited. */\n\t\tulCriticalNesting--;\n\n\t\t/* If the nesting level has reached zero then all interrupt\n\t\tpriorities must be re-enabled. */\n\t\tif( ulCriticalNesting == portNO_CRITICAL_NESTING )\n\t\t{\n\t\t\t/* Critical nesting has reached zero so all interrupt priorities\n\t\t\tshould be unmasked. */\n\t\t\tportCLEAR_INTERRUPT_MASK();\n\t\t}\n\t}\n}\n/*-----------------------------------------------------------*/\n\nvoid FreeRTOS_Tick_Handler( void )\n{\n\t/* Set interrupt mask before altering scheduler structures.   The tick\n\thandler runs at the lowest priority, so interrupts cannot already be masked,\n\tso there is no need to save and restore the current mask value. */\n\t__disable_irq();\n\tportICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );\n\t__asm(\t\"DSB\t\t\\n\"\n\t\t\t\"ISB\t\t\\n\" );\n\t__enable_irq();\n\n\t/* Increment the RTOS tick. */\n\tif( xTaskIncrementTick() != pdFALSE )\n\t{\n\t\tulPortYieldRequired = pdTRUE;\n\t}\n\n\t/* Ensure all interrupt priorities are active again. */\n\tportCLEAR_INTERRUPT_MASK();\n\tconfigCLEAR_TICK_INTERRUPT();\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortTaskUsesFPU( void )\n{\nuint32_t ulInitialFPSCR = 0;\n\n\t/* A task is registering the fact that it needs an FPU context.  Set the\n\tFPU flag (which is saved as part of the task context). */\n\tulPortTaskHasFPUContext = pdTRUE;\n\n\t/* Initialise the floating point status register. */\n\t__asm( \"FMXR \tFPSCR, %0\" :: \"r\" (ulInitialFPSCR) );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortClearInterruptMask( uint32_t ulNewMaskValue )\n{\n\tif( ulNewMaskValue == pdFALSE )\n\t{\n\t\tportCLEAR_INTERRUPT_MASK();\n\t}\n}\n/*-----------------------------------------------------------*/\n\nuint32_t ulPortSetInterruptMask( void )\n{\nuint32_t ulReturn;\n\n\t__disable_irq();\n\tif( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )\n\t{\n\t\t/* Interrupts were already masked. */\n\t\tulReturn = pdTRUE;\n\t}\n\telse\n\t{\n\t\tulReturn = pdFALSE;\n\t\tportICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );\n\t\t__asm(\t\"DSB\t\t\\n\"\n\t\t\t\t\"ISB\t\t\\n\" );\n\t}\n\t__enable_irq();\n\n\treturn ulReturn;\n}\n/*-----------------------------------------------------------*/\n\n#if( configASSERT_DEFINED == 1 )\n\n\tvoid vPortValidateInterruptPriority( void )\n\t{\n\t\t/* The following assertion will fail if a service routine (ISR) for\n\t\tan interrupt that has been assigned a priority above\n\t\tconfigMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\n\t\tfunction.  ISR safe FreeRTOS API functions must *only* be called\n\t\tfrom interrupts that have been assigned a priority at or below\n\t\tconfigMAX_SYSCALL_INTERRUPT_PRIORITY.\n\n\t\tNumerically low interrupt priority numbers represent logically high\n\t\tinterrupt priorities, therefore the priority of the interrupt must\n\t\tbe set to a value equal to or numerically *higher* than\n\t\tconfigMAX_SYSCALL_INTERRUPT_PRIORITY.\n\n\t\tFreeRTOS maintains separate thread and ISR API functions to ensure\n\t\tinterrupt entry is as fast and simple as possible.\n\n\t\tThe following links provide detailed information:\n\t\thttps://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html\n\t\thttps://www.FreeRTOS.org/FAQHelp.html */\n\t\tconfigASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );\n\n\t\t/* Priority grouping:  The interrupt controller (GIC) allows the bits\n\t\tthat define each interrupt's priority to be split between bits that\n\t\tdefine the interrupt's pre-emption priority bits and bits that define\n\t\tthe interrupt's sub-priority.  For simplicity all bits must be defined\n\t\tto be pre-emption priority bits.  The following assertion will fail if\n\t\tthis is not the case (if some bits represent a sub-priority).\n\n\t\tThe priority grouping is configured by the GIC's binary point register\n\t\t(ICCBPR).  Writting 0 to ICCBPR will ensure it is set to its lowest\n\t\tpossible value (which may be above 0). */\n\t\tconfigASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );\n\t}\n\n#endif /* configASSERT_DEFINED */\n\n\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CA9/portASM.h",
    "content": ";/*\n; * FreeRTOS Kernel V10.5.1\n; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n; *\n; * SPDX-License-Identifier: MIT\n; *\n; * Permission is hereby granted, free of charge, to any person obtaining a copy of\n; * this software and associated documentation files (the \"Software\"), to deal in\n; * the Software without restriction, including without limitation the rights to\n; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n; * the Software, and to permit persons to whom the Software is furnished to do so,\n; * subject to the following conditions:\n; *\n; * The above copyright notice and this permission notice shall be included in all\n; * copies or substantial portions of the Software.\n; *\n; * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n; *\n; * https://www.FreeRTOS.org\n; * https://github.com/FreeRTOS\n; *\n; */\n\n\tEXTERN\tvTaskSwitchContext\n\tEXTERN  ulCriticalNesting\n\tEXTERN\tpxCurrentTCB\n\tEXTERN\tulPortTaskHasFPUContext\n\tEXTERN  ulAsmAPIPriorityMask\n\nportSAVE_CONTEXT macro\n\n\t; Save the LR and SPSR onto the system mode stack before switching to\n\t; system mode to save the remaining system mode registers\n\tSRSDB\tsp!, #SYS_MODE\n\tCPS\t\t#SYS_MODE\n\tPUSH\t{R0-R12, R14}\n\n\t; Push the critical nesting count\n\tLDR\t\tR2, =ulCriticalNesting\n\tLDR\t\tR1, [R2]\n\tPUSH\t{R1}\n\n\t; Does the task have a floating point context that needs saving?  If\n\t; ulPortTaskHasFPUContext is 0 then no.\n\tLDR\t\tR2, =ulPortTaskHasFPUContext\n\tLDR\t\tR3, [R2]\n\tCMP\t\tR3, #0\n\n\t; Save the floating point context, if any\n\tFMRXNE  R1,  FPSCR\n\tVPUSHNE {D0-D15}\n\tVPUSHNE\t{D16-D31}\n\tPUSHNE\t{R1}\n\n\t; Save ulPortTaskHasFPUContext itself\n\tPUSH\t{R3}\n\n\t; Save the stack pointer in the TCB\n\tLDR\t\tR0, =pxCurrentTCB\n\tLDR\t\tR1, [R0]\n\tSTR\t\tSP, [R1]\n\n\tendm\n\n; /**********************************************************************/\n\nportRESTORE_CONTEXT macro\n\n\t; Set the SP to point to the stack of the task being restored.\n\tLDR\t\tR0, =pxCurrentTCB\n\tLDR\t\tR1, [R0]\n\tLDR\t\tSP, [R1]\n\n\t; Is there a floating point context to restore?  If the restored\n\t; ulPortTaskHasFPUContext is zero then no.\n\tLDR\t\tR0, =ulPortTaskHasFPUContext\n\tPOP\t\t{R1}\n\tSTR\t\tR1, [R0]\n\tCMP\t\tR1, #0\n\n\t; Restore the floating point context, if any\n\tPOPNE \t{R0}\n\tVPOPNE\t{D16-D31}\n\tVPOPNE\t{D0-D15}\n\tVMSRNE  FPSCR, R0\n\n\t; Restore the critical section nesting depth\n\tLDR\t\tR0, =ulCriticalNesting\n\tPOP\t\t{R1}\n\tSTR\t\tR1, [R0]\n\n\t; Ensure the priority mask is correct for the critical nesting depth\n\tLDR\t\tR2, =portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS\n\tCMP\t\tR1, #0\n\tMOVEQ\tR4, #255\n\tLDRNE\tR4, =( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT )\n\tSTR\t\tR4, [r2]\n\n\t; Restore all system mode registers other than the SP (which is already\n\t; being used)\n\tPOP\t\t{R0-R12, R14}\n\n\t; Return to the task code, loading CPSR on the way.\n\tRFEIA\tsp!\n\n\tendm\n\n\n\n\n\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CA9/portASM.s",
    "content": ";/*\n; * FreeRTOS Kernel V10.5.1\n; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n; *\n; * SPDX-License-Identifier: MIT\n; *\n; * Permission is hereby granted, free of charge, to any person obtaining a copy of\n; * this software and associated documentation files (the \"Software\"), to deal in\n; * the Software without restriction, including without limitation the rights to\n; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n; * the Software, and to permit persons to whom the Software is furnished to do so,\n; * subject to the following conditions:\n; *\n; * The above copyright notice and this permission notice shall be included in all\n; * copies or substantial portions of the Software.\n; *\n; * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n; *\n; * https://www.FreeRTOS.org\n; * https://github.com/FreeRTOS\n; *\n; */\n\n\tINCLUDE FreeRTOSConfig.h\n\tINCLUDE portmacro.h\n\n\tEXTERN\tvApplicationIRQHandler\n\tEXTERN\tvTaskSwitchContext\n\tEXTERN\tulPortYieldRequired\n\tEXTERN\tulPortInterruptNesting\n\n\tPUBLIC\tFreeRTOS_SWI_Handler\n\tPUBLIC  FreeRTOS_IRQ_Handler\n\tPUBLIC \tvPortRestoreTaskContext\n\nSYS_MODE\t\t\tEQU\t\t0x1f\nSVC_MODE\t\t\tEQU\t\t0x13\nIRQ_MODE\t\t\tEQU\t\t0x12\n\n\n\tSECTION .text:CODE:ROOT(2)\n\tARM\n\n\tINCLUDE portASM.h\n\n;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n; SVC handler is used to yield a task.\n;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\nFreeRTOS_SWI_Handler\n\n\tPRESERVE8\n\n\t; Save the context of the current task and select a new task to run.\n\tportSAVE_CONTEXT\n\tLDR R0, =vTaskSwitchContext\n\tBLX\tR0\n\tportRESTORE_CONTEXT\n\n;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n; vPortRestoreTaskContext is used to start the scheduler.\n;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\nvPortRestoreTaskContext\n\t; Switch to system mode\n\tCPS\t\t#SYS_MODE\n\tportRESTORE_CONTEXT\n\n;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n; PL390 GIC interrupt handler\n;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\nFreeRTOS_IRQ_Handler\n\n\t; Return to the interrupted instruction.\n\tSUB\t\tlr, lr, #4\n\n\t; Push the return address and SPSR\n\tPUSH\t{lr}\n\tMRS\t\tlr, SPSR\n\tPUSH\t{lr}\n\n\t; Change to supervisor mode to allow reentry.\n\tCPS\t\t#SVC_MODE\n\n\t; Push used registers.\n\tPUSH\t{r0-r4, r12}\n\n\t; Increment nesting count.  r3 holds the address of ulPortInterruptNesting\n\t; for future use.  r1 holds the original ulPortInterruptNesting value for\n\t; future use.\n\tLDR\t\tr3, =ulPortInterruptNesting\n\tLDR\t\tr1, [r3]\n\tADD\t\tr4, r1, #1\n\tSTR\t\tr4, [r3]\n\n\t; Read value from the interrupt acknowledge register, which is stored in r0\n\t; for future parameter and interrupt clearing use.\n\tLDR \tr2, =portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS\n\tLDR\t\tr0, [r2]\n\n\t; Ensure bit 2 of the stack pointer is clear.  r2 holds the bit 2 value for\n\t; future use.  _RB_ Is this ever necessary if start of stack is 8-byte aligned?\n\tMOV\t\tr2, sp\n\tAND\t\tr2, r2, #4\n\tSUB\t\tsp, sp, r2\n\n\t; Call the interrupt handler.  r4 is pushed to maintain alignment.\n\tPUSH\t{r0-r4, lr}\n\tLDR\t\tr1, =vApplicationIRQHandler\n\tBLX\t\tr1\n\tPOP\t\t{r0-r4, lr}\n\tADD\t\tsp, sp, r2\n\n\tCPSID\ti\n\n\t; Write the value read from ICCIAR to ICCEOIR\n\tLDR \tr4, =portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS\n\tSTR\t\tr0, [r4]\n\n\t; Restore the old nesting count\n\tSTR\t\tr1, [r3]\n\n\t; A context switch is never performed if the nesting count is not 0\n\tCMP\t\tr1, #0\n\tBNE\t\texit_without_switch\n\n\t; Did the interrupt request a context switch?  r1 holds the address of\n\t; ulPortYieldRequired and r0 the value of ulPortYieldRequired for future\n\t; use.\n\tLDR\t\tr1, =ulPortYieldRequired\n\tLDR\t\tr0, [r1]\n\tCMP\t\tr0, #0\n\tBNE\t\tswitch_before_exit\n\nexit_without_switch\n\t; No context switch.  Restore used registers, LR_irq and SPSR before\n\t; returning.\n\tPOP\t\t{r0-r4, r12}\n\tCPS\t\t#IRQ_MODE\n\tPOP\t\t{LR}\n\tMSR\t\tSPSR_cxsf, LR\n\tPOP\t\t{LR}\n\tMOVS\tPC, LR\n\nswitch_before_exit\n\t; A context switch is to be performed.  Clear the context switch pending\n\t; flag.\n\tMOV\t\tr0, #0\n\tSTR\t\tr0, [r1]\n\n\t; Restore used registers, LR-irq and SPSR before saving the context\n\t; to the task stack.\n\tPOP\t\t{r0-r4, r12}\n\tCPS\t\t#IRQ_MODE\n\tPOP\t\t{LR}\n\tMSR\t\tSPSR_cxsf, LR\n\tPOP\t\t{LR}\n\tportSAVE_CONTEXT\n\n\t; Call the function that selects the new task to execute.\n\t; vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD\n\t; instructions, or 8 byte aligned stack allocated data.  LR does not need\n\t; saving as a new LR will be loaded by portRESTORE_CONTEXT anyway.\n\tLDR\t\tr0, =vTaskSwitchContext\n\tBLX\t\tr0\n\n\t; Restore the context of, and branch to, the task selected to execute next.\n\tportRESTORE_CONTEXT\n\n\n\tEND\n\n\n\n\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CA9/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef PORTMACRO_H\n#define PORTMACRO_H\n\n/* IAR includes. */\n#ifdef __ICCARM__\n\n\t#include <intrinsics.h>\n\n\t#ifdef __cplusplus\n\t\textern \"C\" {\n\t#endif\n\n\t/*-----------------------------------------------------------\n\t * Port specific definitions.\n\t *\n\t * The settings in this file configure FreeRTOS correctly for the given hardware\n\t * and compiler.\n\t *\n\t * These settings should not be altered.\n\t *-----------------------------------------------------------\n\t */\n\n\t/* Type definitions. */\n\t#define portCHAR\t\tchar\n\t#define portFLOAT\t\tfloat\n\t#define portDOUBLE\t\tdouble\n\t#define portLONG\t\tlong\n\t#define portSHORT\t\tshort\n\t#define portSTACK_TYPE\tuint32_t\n\t#define portBASE_TYPE\tlong\n\n\ttypedef portSTACK_TYPE StackType_t;\n\ttypedef long BaseType_t;\n\ttypedef unsigned long UBaseType_t;\n\n\ttypedef uint32_t TickType_t;\n\t#define portMAX_DELAY ( TickType_t ) 0xffffffffUL\n\n\t/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\n\tnot need to be guarded with a critical section. */\n\t#define portTICK_TYPE_IS_ATOMIC 1\n\n\t/*-----------------------------------------------------------*/\n\n\t/* Hardware specifics. */\n\t#define portSTACK_GROWTH\t\t\t( -1 )\n\t#define portTICK_PERIOD_MS\t\t\t( ( TickType_t ) 1000 / configTICK_RATE_HZ )\n\t#define portBYTE_ALIGNMENT\t\t\t8\n\n\t/*-----------------------------------------------------------*/\n\n\t/* Task utilities. */\n\n\t/* Called at the end of an ISR that can cause a context switch. */\n\t#define portEND_SWITCHING_ISR( xSwitchRequired )\\\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\\\n\textern uint32_t ulPortYieldRequired;\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tif( xSwitchRequired != pdFALSE )\t\t\t\\\n\t\t{\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\tulPortYieldRequired = pdTRUE;\t\t\t\\\n\t\t}\t\t\t\t\t\t\t\t\t\t\t\\\n\t}\n\n\t#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\n\t#define portYIELD() __asm( \"SWI 0\" );\n\n\n\t/*-----------------------------------------------------------\n\t * Critical section control\n\t *----------------------------------------------------------*/\n\n\textern void vPortEnterCritical( void );\n\textern void vPortExitCritical( void );\n\textern uint32_t ulPortSetInterruptMask( void );\n\textern void vPortClearInterruptMask( uint32_t ulNewMaskValue );\n\n\t/* These macros do not globally disable/enable interrupts.  They do mask off\n\tinterrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */\n\t#define portENTER_CRITICAL()\t\tvPortEnterCritical();\n\t#define portEXIT_CRITICAL()\t\t\tvPortExitCritical();\n\t#define portDISABLE_INTERRUPTS()\tulPortSetInterruptMask()\n\t#define portENABLE_INTERRUPTS()\t\tvPortClearInterruptMask( 0 )\n\t#define portSET_INTERRUPT_MASK_FROM_ISR()\t\tulPortSetInterruptMask()\n\t#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)\tvPortClearInterruptMask(x)\n\n\t/*-----------------------------------------------------------*/\n\n\t/* Task function macros as described on the FreeRTOS.org WEB site.  These are\n\tnot required for this port but included in case common demo code that uses these\n\tmacros is used. */\n\t#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )\tvoid vFunction( void *pvParameters )\n\t#define portTASK_FUNCTION( vFunction, pvParameters )\tvoid vFunction( void *pvParameters )\n\n\t/* Prototype of the FreeRTOS tick handler.  This must be installed as the\n\thandler for whichever peripheral is used to generate the RTOS tick. */\n\tvoid FreeRTOS_Tick_Handler( void );\n\n\t/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()\n\tbefore any floating point instructions are executed. */\n\tvoid vPortTaskUsesFPU( void );\n\t#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()\n\n\t#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )\n\t#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )\n\n\t/* Architecture specific optimisations. */\n\t#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION\n\t\t#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1\n\t#endif\n\n\t#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1\n\n\t\t/* Store/clear the ready priorities in a bit map. */\n\t\t#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )\n\t\t#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )\n\n\t\t/*-----------------------------------------------------------*/\n\n\t\t#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __CLZ( uxReadyPriorities ) )\n\n\t#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */\n\n\t#ifdef configASSERT\n\t\tvoid vPortValidateInterruptPriority( void );\n\t\t#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() \tvPortValidateInterruptPriority()\n\t#endif /* configASSERT */\n\n\t#define portNOP() __asm volatile( \"NOP\" )\n\n\n\t#ifdef __cplusplus\n\t\t} /* extern C */\n\t#endif\n\n\t/* Suppress warnings that are generated by the IAR tools, but cannot be\n\tfixed in the source code because to do so would cause other compilers to\n\tgenerate warnings. */\n\t#pragma diag_suppress=Pe191\n\t#pragma diag_suppress=Pa082\n\n#endif /* __ICCARM__ */\n\n\n/* The number of bits to shift for an interrupt priority is dependent on the\nnumber of bits implemented by the interrupt controller. */\n#if configUNIQUE_INTERRUPT_PRIORITIES == 16\n\t#define portPRIORITY_SHIFT 4\n\t#define portMAX_BINARY_POINT_VALUE\t3\n#elif configUNIQUE_INTERRUPT_PRIORITIES == 32\n\t#define portPRIORITY_SHIFT 3\n\t#define portMAX_BINARY_POINT_VALUE\t2\n#elif configUNIQUE_INTERRUPT_PRIORITIES == 64\n\t#define portPRIORITY_SHIFT 2\n\t#define portMAX_BINARY_POINT_VALUE\t1\n#elif configUNIQUE_INTERRUPT_PRIORITIES == 128\n\t#define portPRIORITY_SHIFT 1\n\t#define portMAX_BINARY_POINT_VALUE\t0\n#elif configUNIQUE_INTERRUPT_PRIORITIES == 256\n\t#define portPRIORITY_SHIFT 0\n\t#define portMAX_BINARY_POINT_VALUE\t0\n#else\n\t#error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting.  configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware\n#endif\n\n/* Interrupt controller access addresses. */\n#define portICCPMR_PRIORITY_MASK_OFFSET  \t\t\t\t\t\t( 0x04 )\n#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET \t\t\t\t( 0x0C )\n#define portICCEOIR_END_OF_INTERRUPT_OFFSET \t\t\t\t\t( 0x10 )\n#define portICCBPR_BINARY_POINT_OFFSET\t\t\t\t\t\t\t( 0x08 )\n#define portICCRPR_RUNNING_PRIORITY_OFFSET\t\t\t\t\t\t( 0x14 )\n\n#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS \t\t( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )\n#define portICCPMR_PRIORITY_MASK_REGISTER \t\t\t\t\t( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )\n#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS \t( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )\n#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS \t\t( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )\n#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS \t\t\t( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )\n#define portICCBPR_BINARY_POINT_REGISTER \t\t\t\t\t( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )\n#define portICCRPR_RUNNING_PRIORITY_REGISTER \t\t\t\t( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )\n\n#endif /* PORTMACRO_H */\n\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM0/port.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/*-----------------------------------------------------------\n* Implementation of functions defined in portable.h for the ARM CM0 port.\n*----------------------------------------------------------*/\n\n/* IAR includes. */\n#include \"intrinsics.h\"\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n/* Constants required to manipulate the NVIC. */\n#define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )\n#define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )\n#define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )\n#define portNVIC_INT_CTRL_REG                 ( *( ( volatile uint32_t * ) 0xe000ed04 ) )\n#define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )\n#define portNVIC_SYSTICK_CLK_BIT              ( 1UL << 2UL )\n#define portNVIC_SYSTICK_INT_BIT              ( 1UL << 1UL )\n#define portNVIC_SYSTICK_ENABLE_BIT           ( 1UL << 0UL )\n#define portNVIC_SYSTICK_COUNT_FLAG_BIT       ( 1UL << 16UL )\n#define portNVIC_PEND_SYSTICK_SET_BIT         ( 1UL << 26UL )\n#define portNVIC_PEND_SYSTICK_CLEAR_BIT       ( 1UL << 25UL )\n#define portMIN_INTERRUPT_PRIORITY            ( 255UL )\n#define portNVIC_PENDSV_PRI                   ( portMIN_INTERRUPT_PRIORITY << 16UL )\n#define portNVIC_SYSTICK_PRI                  ( portMIN_INTERRUPT_PRIORITY << 24UL )\n\n/* Constants required to set up the initial stack. */\n#define portINITIAL_XPSR                      ( 0x01000000 )\n\n/* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is\n * defined.  The value 255 should also ensure backward compatibility.\n * FreeRTOS.org versions prior to V4.3.0 did not include this definition. */\n#ifndef configKERNEL_INTERRUPT_PRIORITY\n    #define configKERNEL_INTERRUPT_PRIORITY    0\n#endif\n\n/* Each task maintains its own interrupt status in the critical nesting\n * variable. */\nstatic UBaseType_t uxCriticalNesting = 0xaaaaaaaa;\n\n/* The systick is a 24-bit counter. */\n#define portMAX_24_BIT_NUMBER    ( 0xffffffUL )\n\n/* A fiddle factor to estimate the number of SysTick counts that would have\n * occurred while the SysTick counter is stopped during tickless idle\n * calculations. */\n#ifndef portMISSED_COUNTS_FACTOR\n    #define portMISSED_COUNTS_FACTOR    ( 94UL )\n#endif\n\n/* The number of SysTick increments that make up one tick period. */\n#if ( configUSE_TICKLESS_IDLE == 1 )\n    static uint32_t ulTimerCountsForOneTick = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n\n/* The maximum number of tick periods that can be suppressed is limited by the\n * 24 bit resolution of the SysTick timer. */\n#if ( configUSE_TICKLESS_IDLE == 1 )\n    static uint32_t xMaximumPossibleSuppressedTicks = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n\n/* Compensate for the CPU cycles that pass while the SysTick is stopped (low\n * power functionality only. */\n#if ( configUSE_TICKLESS_IDLE == 1 )\n    static uint32_t ulStoppedTimerCompensation = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n\n/* Let the user override the default SysTick clock rate.  If defined by the\n * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the\n * configuration register. */\n#ifndef configSYSTICK_CLOCK_HZ\n    #define configSYSTICK_CLOCK_HZ             ( configCPU_CLOCK_HZ )\n    /* Ensure the SysTick is clocked at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( portNVIC_SYSTICK_CLK_BIT )\n#else\n    /* Select the option to clock SysTick not at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( 0 )\n#endif\n\n/*\n * Setup the timer to generate the tick interrupts.  The implementation in this\n * file is weak to allow application writers to change the timer used to\n * generate the tick interrupt.\n */\nvoid vPortSetupTimerInterrupt( void );\n\n/*\n * Exception handlers.\n */\nvoid xPortSysTickHandler( void );\n\n/*\n * Start first task is a separate function so it can be tested in isolation.\n */\nextern void vPortStartFirstTask( void );\n\n/*\n * Used to catch tasks that attempt to return from their implementing function.\n */\nstatic void prvTaskExitError( void );\n\n/*-----------------------------------------------------------*/\n\n/*\n * See header file for description.\n */\nStackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,\n                                     TaskFunction_t pxCode,\n                                     void * pvParameters )\n{\n    /* Simulate the stack frame as it would be created by a context switch\n     * interrupt. */\n    pxTopOfStack--;                                   /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\n    *pxTopOfStack = portINITIAL_XPSR;                 /* xPSR */\n    pxTopOfStack--;\n    *pxTopOfStack = ( StackType_t ) pxCode;           /* PC */\n    pxTopOfStack--;\n    *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* LR */\n    pxTopOfStack -= 5;                                /* R12, R3, R2 and R1. */\n    *pxTopOfStack = ( StackType_t ) pvParameters;     /* R0 */\n    pxTopOfStack -= 8;                                /* R11..R4. */\n\n    return pxTopOfStack;\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvTaskExitError( void )\n{\n    /* A function that implements a task must not exit or attempt to return to\n     * its caller as there is nothing to return to.  If a task wants to exit it\n     * should instead call vTaskDelete( NULL ).\n     *\n     * Artificially force an assert() to be triggered if configASSERT() is\n     * defined, then stop here so application writers can catch the error. */\n    configASSERT( uxCriticalNesting == ~0UL );\n    portDISABLE_INTERRUPTS();\n\n    for( ; ; )\n    {\n    }\n}\n/*-----------------------------------------------------------*/\n\n/*\n * See header file for description.\n */\nBaseType_t xPortStartScheduler( void )\n{\n    /* Make PendSV and SysTick the lowest priority interrupts. */\n    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;\n    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;\n\n    /* Start the timer that generates the tick ISR.  Interrupts are disabled\n     * here already. */\n    vPortSetupTimerInterrupt();\n\n    /* Initialise the critical nesting count ready for the first task. */\n    uxCriticalNesting = 0;\n\n    /* Start the first task. */\n    vPortStartFirstTask();\n\n    /* Should not get here! */\n    return 0;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEndScheduler( void )\n{\n    /* Not implemented in ports where there is nothing to return to.\n     * Artificially force an assert. */\n    configASSERT( uxCriticalNesting == 1000UL );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortYield( void )\n{\n    /* Set a PendSV to request a context switch. */\n    portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET;\n\n    /* Barriers are normally not required but do ensure the code is completely\n     * within the specified behaviour for the architecture. */\n    __DSB();\n    __ISB();\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEnterCritical( void )\n{\n    portDISABLE_INTERRUPTS();\n    uxCriticalNesting++;\n    __DSB();\n    __ISB();\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortExitCritical( void )\n{\n    configASSERT( uxCriticalNesting );\n    uxCriticalNesting--;\n\n    if( uxCriticalNesting == 0 )\n    {\n        portENABLE_INTERRUPTS();\n    }\n}\n/*-----------------------------------------------------------*/\n\nvoid xPortSysTickHandler( void )\n{\n    uint32_t ulPreviousMask;\n\n    ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();\n    {\n        /* Increment the RTOS tick. */\n        if( xTaskIncrementTick() != pdFALSE )\n        {\n            /* Pend a context switch. */\n            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET;\n        }\n    }\n    portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );\n}\n/*-----------------------------------------------------------*/\n\n/*\n * Setup the systick timer to generate the tick interrupts at the required\n * frequency.\n */\n__weak void vPortSetupTimerInterrupt( void )\n{\n    /* Calculate the constants required to configure the tick interrupt. */\n    #if ( configUSE_TICKLESS_IDLE == 1 )\n    {\n        ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );\n        xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;\n        ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\n    }\n    #endif /* configUSE_TICKLESS_IDLE */\n\n    /* Stop and reset the SysTick. */\n    portNVIC_SYSTICK_CTRL_REG = 0UL;\n    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n    /* Configure SysTick to interrupt at the requested rate. */\n    portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\n    portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );\n}\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TICKLESS_IDLE == 1 )\n\n    __weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )\n    {\n        uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;\n        TickType_t xModifiableIdleTime;\n\n        /* Make sure the SysTick reload value does not overflow the counter. */\n        if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\n        {\n            xExpectedIdleTime = xMaximumPossibleSuppressedTicks;\n        }\n\n        /* Enter a critical section but don't use the taskENTER_CRITICAL()\n         * method as that will mask interrupts that should exit sleep mode. */\n        __disable_interrupt();\n        __DSB();\n        __ISB();\n\n        /* If a context switch is pending or a task is waiting for the scheduler\n         * to be unsuspended then abandon the low power entry. */\n        if( eTaskConfirmSleepModeStatus() == eAbortSleep )\n        {\n            /* Re-enable interrupts - see comments above the __disable_interrupt()\n             * call above. */\n            __enable_interrupt();\n        }\n        else\n        {\n            /* Stop the SysTick momentarily.  The time the SysTick is stopped for\n             * is accounted for as best it can be, but using the tickless mode will\n             * inevitably result in some tiny drift of the time maintained by the\n             * kernel with respect to calendar time. */\n            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );\n\n            /* Use the SysTick current-value register to determine the number of\n             * SysTick decrements remaining until the next tick interrupt.  If the\n             * current-value register is zero, then there are actually\n             * ulTimerCountsForOneTick decrements remaining, not zero, because the\n             * SysTick requests the interrupt when decrementing from 1 to 0. */\n            ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n\n            if( ulSysTickDecrementsLeft == 0 )\n            {\n                ulSysTickDecrementsLeft = ulTimerCountsForOneTick;\n            }\n\n            /* Calculate the reload value required to wait xExpectedIdleTime\n             * tick periods.  -1 is used because this code normally executes part\n             * way through the first tick period.  But if the SysTick IRQ is now\n             * pending, then clear the IRQ, suppressing the first tick, and correct\n             * the reload value to reflect that the second tick period is already\n             * underway.  The expected idle time is always at least two ticks. */\n            ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );\n\n            if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )\n            {\n                portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;\n                ulReloadValue -= ulTimerCountsForOneTick;\n            }\n\n            if( ulReloadValue > ulStoppedTimerCompensation )\n            {\n                ulReloadValue -= ulStoppedTimerCompensation;\n            }\n\n            /* Set the new reload value. */\n            portNVIC_SYSTICK_LOAD_REG = ulReloadValue;\n\n            /* Clear the SysTick count flag and set the count value back to\n             * zero. */\n            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n            /* Restart SysTick. */\n            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\n\n            /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can\n             * set its parameter to 0 to indicate that its implementation contains\n             * its own wait for interrupt or wait for event instruction, and so wfi\n             * should not be executed again.  However, the original expected idle\n             * time variable must remain unmodified, so a copy is taken. */\n            xModifiableIdleTime = xExpectedIdleTime;\n            configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\n\n            if( xModifiableIdleTime > 0 )\n            {\n                __DSB();\n                __WFI();\n                __ISB();\n            }\n\n            configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\n\n            /* Re-enable interrupts to allow the interrupt that brought the MCU\n             * out of sleep mode to execute immediately.  See comments above\n             * the __disable_interrupt() call above. */\n            __enable_interrupt();\n            __DSB();\n            __ISB();\n\n            /* Disable interrupts again because the clock is about to be stopped\n             * and interrupts that execute while the clock is stopped will increase\n             * any slippage between the time maintained by the RTOS and calendar\n             * time. */\n            __disable_interrupt();\n            __DSB();\n            __ISB();\n\n            /* Disable the SysTick clock without reading the\n             * portNVIC_SYSTICK_CTRL_REG register to ensure the\n             * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,\n             * the time the SysTick is stopped for is accounted for as best it can\n             * be, but using the tickless mode will inevitably result in some tiny\n             * drift of the time maintained by the kernel with respect to calendar\n             * time*/\n            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );\n\n            /* Determine whether the SysTick has already counted to zero. */\n            if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n            {\n                uint32_t ulCalculatedLoadValue;\n\n                /* The tick interrupt ended the sleep (or is now pending), and\n                 * a new tick period has started.  Reset portNVIC_SYSTICK_LOAD_REG\n                 * with whatever remains of the new tick period. */\n                ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\n\n                /* Don't allow a tiny value, or values that have somehow\n                 * underflowed because the post sleep hook did something\n                 * that took too long or because the SysTick current-value register\n                 * is zero. */\n                if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )\n                {\n                    ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );\n                }\n\n                portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;\n\n                /* As the pending tick will be processed as soon as this\n                 * function exits, the tick value maintained by the tick is stepped\n                 * forward by one less than the time spent waiting. */\n                ulCompleteTickPeriods = xExpectedIdleTime - 1UL;\n            }\n            else\n            {\n                /* Something other than the tick interrupt ended the sleep. */\n\n                /* Use the SysTick current-value register to determine the\n                 * number of SysTick decrements remaining until the expected idle\n                 * time would have ended. */\n                ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n                #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )\n                {\n                    /* If the SysTick is not using the core clock, the current-\n                     * value register might still be zero here.  In that case, the\n                     * SysTick didn't load from the reload register, and there are\n                     * ulReloadValue decrements remaining in the expected idle\n                     * time, not zero. */\n                    if( ulSysTickDecrementsLeft == 0 )\n                    {\n                        ulSysTickDecrementsLeft = ulReloadValue;\n                    }\n                }\n                #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */\n\n                /* Work out how long the sleep lasted rounded to complete tick\n                 * periods (not the ulReload value which accounted for part\n                 * ticks). */\n                ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;\n\n                /* How many complete tick periods passed while the processor\n                 * was waiting? */\n                ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;\n\n                /* The reload value is set to whatever fraction of a single tick\n                 * period remains. */\n                portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;\n            }\n\n            /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,\n             * then set portNVIC_SYSTICK_LOAD_REG back to its standard value.  If\n             * the SysTick is not using the core clock, temporarily configure it to\n             * use the core clock.  This configuration forces the SysTick to load\n             * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next\n             * cycle of the other clock.  Then portNVIC_SYSTICK_LOAD_REG is ready\n             * to receive the standard value immediately. */\n            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n            portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n            #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )\n            {\n                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n            }\n            #else\n            {\n                /* The temporary usage of the core clock has served its purpose,\n                 * as described above.  Resume usage of the other clock. */\n                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\n\n                if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n                {\n                    /* The partial tick period already ended.  Be sure the SysTick\n                     * counts it only once. */\n                    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;\n                }\n\n                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n            }\n            #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */\n\n            /* Step the tick to account for any tick periods that elapsed. */\n            vTaskStepTick( ulCompleteTickPeriods );\n\n            /* Exit with interrupts enabled. */\n            __enable_interrupt();\n        }\n    }\n\n#endif /* configUSE_TICKLESS_IDLE */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM0/portasm.s",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#include <FreeRTOSConfig.h>\n\n\tRSEG    CODE:CODE(2)\n\tthumb\n\n\tEXTERN vPortYieldFromISR\n\tEXTERN pxCurrentTCB\n\tEXTERN vTaskSwitchContext\n\n\tPUBLIC vSetMSP\n\tPUBLIC xPortPendSVHandler\n\tPUBLIC vPortSVCHandler\n\tPUBLIC vPortStartFirstTask\n\tPUBLIC ulSetInterruptMaskFromISR\n\tPUBLIC vClearInterruptMaskFromISR\n\n/*-----------------------------------------------------------*/\n\nvSetMSP\n\tmsr msp, r0\n\tbx lr\n\n/*-----------------------------------------------------------*/\n\nxPortPendSVHandler:\n\tmrs r0, psp\n\n\tldr\tr3, =pxCurrentTCB\t/* Get the location of the current TCB. */\n\tldr\tr2, [r3]\n\n\tsubs r0, r0, #32\t\t/* Make space for the remaining low registers. */\n\tstr r0, [r2]\t\t\t/* Save the new top of stack. */\n\tstmia r0!, {r4-r7}\t\t/* Store the low registers that are not saved automatically. */\n\tmov r4, r8\t\t\t\t/* Store the high registers. */\n\tmov r5, r9\n\tmov r6, r10\n\tmov r7, r11\n\tstmia r0!, {r4-r7}\n\n\tpush {r3, r14}\n\tcpsid i\n\tbl vTaskSwitchContext\n\tcpsie i\n\tpop {r2, r3}\t\t\t/* lr goes in r3. r2 now holds tcb pointer. */\n\n\tldr r1, [r2]\n\tldr r0, [r1]\t\t\t/* The first item in pxCurrentTCB is the task top of stack. */\n\tadds r0, r0, #16\t\t/* Move to the high registers. */\n\tldmia r0!, {r4-r7}\t\t/* Pop the high registers. */\n\tmov r8, r4\n\tmov r9, r5\n\tmov r10, r6\n\tmov r11, r7\n\n\tmsr psp, r0\t\t\t\t/* Remember the new top of stack for the task. */\n\n\tsubs r0, r0, #32\t\t/* Go back for the low registers that are not automatically restored. */\n\tldmia r0!, {r4-r7}\t\t/* Pop low registers.  */\n\n\tbx r3\n\n/*-----------------------------------------------------------*/\n\nvPortSVCHandler;\n\t/* This function is no longer used, but retained for backward\n\tcompatibility. */\n\tbx lr\n\n/*-----------------------------------------------------------*/\n\nvPortStartFirstTask\n\t/* The MSP stack is not reset as, unlike on M3/4 parts, there is no vector\n\ttable offset register that can be used to locate the initial stack value.\n\tNot all M0 parts have the application vector table at address 0. */\n\n\tldr\tr3, =pxCurrentTCB\t/* Obtain location of pxCurrentTCB. */\n\tldr r1, [r3]\n\tldr r0, [r1]\t\t\t/* The first item in pxCurrentTCB is the task top of stack. */\n\tadds r0, #32\t\t\t/* Discard everything up to r0. */\n\tmsr psp, r0\t\t\t\t/* This is now the new top of stack to use in the task. */\n\tmovs r0, #2\t\t\t\t/* Switch to the psp stack. */\n\tmsr CONTROL, r0\n\tisb\n\tpop {r0-r5}\t\t\t\t/* Pop the registers that are saved automatically. */\n\tmov lr, r5\t\t\t\t/* lr is now in r5. */\n\tpop {r3}\t\t\t\t/* The return address is now in r3. */\n\tpop {r2}\t\t\t\t/* Pop and discard the XPSR. */\n\tcpsie i\t\t\t\t\t/* The first task has its context and interrupts can be enabled. */\n\tbx r3\t\t\t\t\t/* Jump to the user defined task code. */\n\n/*-----------------------------------------------------------*/\n\nulSetInterruptMaskFromISR\n\tmrs r0, PRIMASK\n\tcpsid i\n\tbx lr\n\n/*-----------------------------------------------------------*/\n\nvClearInterruptMaskFromISR\n\tmsr PRIMASK, r0\n\tbx lr\n\n\tEND\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM0/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef PORTMACRO_H\n    #define PORTMACRO_H\n\n    #ifdef __cplusplus\n        extern \"C\" {\n    #endif\n\n/*-----------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the\n * given hardware and compiler.\n *\n * These settings should not be altered.\n *-----------------------------------------------------------\n */\n\n/* Type definitions. */\n    #define portCHAR          char\n    #define portFLOAT         float\n    #define portDOUBLE        double\n    #define portLONG          long\n    #define portSHORT         short\n    #define portSTACK_TYPE    uint32_t\n    #define portBASE_TYPE     long\n\n    typedef portSTACK_TYPE   StackType_t;\n    typedef long             BaseType_t;\n    typedef unsigned long    UBaseType_t;\n\n\n    #if ( configUSE_16_BIT_TICKS == 1 )\n        typedef uint16_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffff\n    #else\n        typedef uint32_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL\n\n/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\n * not need to be guarded with a critical section. */\n        #define portTICK_TYPE_IS_ATOMIC    1\n    #endif\n/*-----------------------------------------------------------*/\n\n/* Architecture specifics. */\n    #define portSTACK_GROWTH      ( -1 )\n    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\n    #define portBYTE_ALIGNMENT    8\n/*-----------------------------------------------------------*/\n\n\n/* Scheduler utilities. */\n    extern void vPortYield( void );\n    #define portNVIC_INT_CTRL                           ( ( volatile uint32_t * ) 0xe000ed04 )\n    #define portNVIC_PENDSVSET                          0x10000000\n    #define portYIELD()                                 vPortYield()\n    #define portEND_SWITCHING_ISR( xSwitchRequired )    if( xSwitchRequired ) *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET\n    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )\n/*-----------------------------------------------------------*/\n\n\n/* Critical section management. */\n\n    extern void vPortEnterCritical( void );\n    extern void vPortExitCritical( void );\n    extern uint32_t ulSetInterruptMaskFromISR( void );\n    extern void vClearInterruptMaskFromISR( uint32_t ulMask );\n\n    #define portDISABLE_INTERRUPTS()                  __asm volatile ( \"cpsid i\" )\n    #define portENABLE_INTERRUPTS()                   __asm volatile ( \"cpsie i\" )\n    #define portENTER_CRITICAL()                      vPortEnterCritical()\n    #define portEXIT_CRITICAL()                       vPortExitCritical()\n    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulSetInterruptMaskFromISR()\n    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vClearInterruptMaskFromISR( x )\n\n/*-----------------------------------------------------------*/\n\n/* Tickless idle/low power functionality. */\n    #ifndef portSUPPRESS_TICKS_AND_SLEEP\n        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );\n        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )\n    #endif\n/*-----------------------------------------------------------*/\n\n/* Task function macros as described on the FreeRTOS.org WEB site. */\n    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )\n    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )\n\n    #define portNOP()\n\n/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in\n * the source code because to do so would cause other compilers to generate\n * warnings. */\n    #pragma diag_suppress=Pa082\n\n    #ifdef __cplusplus\n        }\n    #endif\n\n#endif /* PORTMACRO_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM23/non_secure/port.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\n * all the API functions to use the MPU wrappers. That should only be done when\n * task.h is included from an application file. */\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n/* MPU wrappers includes. */\n#include \"mpu_wrappers.h\"\n\n/* Portasm includes. */\n#include \"portasm.h\"\n\n#if ( configENABLE_TRUSTZONE == 1 )\n    /* Secure components includes. */\n    #include \"secure_context.h\"\n    #include \"secure_init.h\"\n#endif /* configENABLE_TRUSTZONE */\n\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/**\n * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only\n * i.e. the processor boots as secure and never jumps to the non-secure side.\n * The Trust Zone support in the port must be disabled in order to run FreeRTOS\n * on the secure side. The following are the valid configuration seetings:\n *\n * 1. Run FreeRTOS on the Secure Side:\n *    configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0\n *\n * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:\n *    configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1\n *\n * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:\n *    configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0\n */\n#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )\n    #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.\n#endif\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the NVIC.\n */\n#define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )\n#define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )\n#define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )\n#define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )\n#define portNVIC_SYSTICK_ENABLE_BIT           ( 1UL << 0UL )\n#define portNVIC_SYSTICK_INT_BIT              ( 1UL << 1UL )\n#define portNVIC_SYSTICK_CLK_BIT              ( 1UL << 2UL )\n#define portNVIC_SYSTICK_COUNT_FLAG_BIT       ( 1UL << 16UL )\n#define portNVIC_PEND_SYSTICK_CLEAR_BIT       ( 1UL << 25UL )\n#define portNVIC_PEND_SYSTICK_SET_BIT         ( 1UL << 26UL )\n#define portMIN_INTERRUPT_PRIORITY            ( 255UL )\n#define portNVIC_PENDSV_PRI                   ( portMIN_INTERRUPT_PRIORITY << 16UL )\n#define portNVIC_SYSTICK_PRI                  ( portMIN_INTERRUPT_PRIORITY << 24UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the SCB.\n */\n#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( volatile uint32_t * ) 0xe000ed24 )\n#define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the FPU.\n */\n#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 )              /* Coprocessor Access Control Register. */\n#define portCPACR_CP10_VALUE    ( 3UL )\n#define portCPACR_CP11_VALUE    portCPACR_CP10_VALUE\n#define portCPACR_CP10_POS      ( 20UL )\n#define portCPACR_CP11_POS      ( 22UL )\n\n#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 )              /* Floating Point Context Control Register. */\n#define portFPCCR_ASPEN_POS     ( 31UL )\n#define portFPCCR_ASPEN_MASK    ( 1UL << portFPCCR_ASPEN_POS )\n#define portFPCCR_LSPEN_POS     ( 30UL )\n#define portFPCCR_LSPEN_MASK    ( 1UL << portFPCCR_LSPEN_POS )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the MPU.\n */\n#define portMPU_TYPE_REG                      ( *( ( volatile uint32_t * ) 0xe000ed90 ) )\n#define portMPU_CTRL_REG                      ( *( ( volatile uint32_t * ) 0xe000ed94 ) )\n#define portMPU_RNR_REG                       ( *( ( volatile uint32_t * ) 0xe000ed98 ) )\n\n#define portMPU_RBAR_REG                      ( *( ( volatile uint32_t * ) 0xe000ed9c ) )\n#define portMPU_RLAR_REG                      ( *( ( volatile uint32_t * ) 0xe000eda0 ) )\n\n#define portMPU_RBAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda4 ) )\n#define portMPU_RLAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda8 ) )\n\n#define portMPU_RBAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edac ) )\n#define portMPU_RLAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edb0 ) )\n\n#define portMPU_RBAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb4 ) )\n#define portMPU_RLAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb8 ) )\n\n#define portMPU_MAIR0_REG                     ( *( ( volatile uint32_t * ) 0xe000edc0 ) )\n#define portMPU_MAIR1_REG                     ( *( ( volatile uint32_t * ) 0xe000edc4 ) )\n\n#define portMPU_RBAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */\n#define portMPU_RLAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */\n\n#define portMPU_MAIR_ATTR0_POS                ( 0UL )\n#define portMPU_MAIR_ATTR0_MASK               ( 0x000000ff )\n\n#define portMPU_MAIR_ATTR1_POS                ( 8UL )\n#define portMPU_MAIR_ATTR1_MASK               ( 0x0000ff00 )\n\n#define portMPU_MAIR_ATTR2_POS                ( 16UL )\n#define portMPU_MAIR_ATTR2_MASK               ( 0x00ff0000 )\n\n#define portMPU_MAIR_ATTR3_POS                ( 24UL )\n#define portMPU_MAIR_ATTR3_MASK               ( 0xff000000 )\n\n#define portMPU_MAIR_ATTR4_POS                ( 0UL )\n#define portMPU_MAIR_ATTR4_MASK               ( 0x000000ff )\n\n#define portMPU_MAIR_ATTR5_POS                ( 8UL )\n#define portMPU_MAIR_ATTR5_MASK               ( 0x0000ff00 )\n\n#define portMPU_MAIR_ATTR6_POS                ( 16UL )\n#define portMPU_MAIR_ATTR6_MASK               ( 0x00ff0000 )\n\n#define portMPU_MAIR_ATTR7_POS                ( 24UL )\n#define portMPU_MAIR_ATTR7_MASK               ( 0xff000000 )\n\n#define portMPU_RLAR_ATTR_INDEX0              ( 0UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX1              ( 1UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX2              ( 2UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX3              ( 3UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX4              ( 4UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX5              ( 5UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX6              ( 6UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX7              ( 7UL << 1UL )\n\n#define portMPU_RLAR_REGION_ENABLE            ( 1UL )\n\n/* Enable privileged access to unmapped region. */\n#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )\n\n/* Enable MPU. */\n#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )\n\n/* Expected value of the portMPU_TYPE register. */\n#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief The maximum 24-bit number.\n *\n * It is needed because the systick is a 24-bit counter.\n */\n#define portMAX_24_BIT_NUMBER       ( 0xffffffUL )\n\n/**\n * @brief A fiddle factor to estimate the number of SysTick counts that would\n * have occurred while the SysTick counter is stopped during tickless idle\n * calculations.\n */\n#define portMISSED_COUNTS_FACTOR    ( 94UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to set up the initial stack.\n */\n#define portINITIAL_XPSR    ( 0x01000000 )\n\n#if ( configRUN_FREERTOS_SECURE_ONLY == 1 )\n\n/**\n * @brief Initial EXC_RETURN value.\n *\n *     FF         FF         FF         FD\n * 1111 1111  1111 1111  1111 1111  1111 1101\n *\n * Bit[6] - 1 --> The exception was taken from the Secure state.\n * Bit[5] - 1 --> Do not skip stacking of additional state context.\n * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\n * Bit[3] - 1 --> Return to the Thread mode.\n * Bit[2] - 1 --> Restore registers from the process stack.\n * Bit[1] - 0 --> Reserved, 0.\n * Bit[0] - 1 --> The exception was taken to the Secure state.\n */\n    #define portINITIAL_EXC_RETURN    ( 0xfffffffd )\n#else\n\n/**\n * @brief Initial EXC_RETURN value.\n *\n *     FF         FF         FF         BC\n * 1111 1111  1111 1111  1111 1111  1011 1100\n *\n * Bit[6] - 0 --> The exception was taken from the Non-Secure state.\n * Bit[5] - 1 --> Do not skip stacking of additional state context.\n * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\n * Bit[3] - 1 --> Return to the Thread mode.\n * Bit[2] - 1 --> Restore registers from the process stack.\n * Bit[1] - 0 --> Reserved, 0.\n * Bit[0] - 0 --> The exception was taken to the Non-Secure state.\n */\n    #define portINITIAL_EXC_RETURN    ( 0xffffffbc )\n#endif /* configRUN_FREERTOS_SECURE_ONLY */\n\n/**\n * @brief CONTROL register privileged bit mask.\n *\n * Bit[0] in CONTROL register tells the privilege:\n *  Bit[0] = 0 ==> The task is privileged.\n *  Bit[0] = 1 ==> The task is not privileged.\n */\n#define portCONTROL_PRIVILEGED_MASK         ( 1UL << 0UL )\n\n/**\n * @brief Initial CONTROL register values.\n */\n#define portINITIAL_CONTROL_UNPRIVILEGED    ( 0x3 )\n#define portINITIAL_CONTROL_PRIVILEGED      ( 0x2 )\n\n/**\n * @brief Let the user override the default SysTick clock rate.  If defined by the\n * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the\n * configuration register.\n */\n#ifndef configSYSTICK_CLOCK_HZ\n    #define configSYSTICK_CLOCK_HZ             ( configCPU_CLOCK_HZ )\n    /* Ensure the SysTick is clocked at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( portNVIC_SYSTICK_CLK_BIT )\n#else\n    /* Select the option to clock SysTick not at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( 0 )\n#endif\n\n/**\n * @brief Let the user override the pre-loading of the initial LR with the\n * address of prvTaskExitError() in case it messes up unwinding of the stack\n * in the debugger.\n */\n#ifdef configTASK_RETURN_ADDRESS\n    #define portTASK_RETURN_ADDRESS    configTASK_RETURN_ADDRESS\n#else\n    #define portTASK_RETURN_ADDRESS    prvTaskExitError\n#endif\n\n/**\n * @brief If portPRELOAD_REGISTERS then registers will be given an initial value\n * when a task is created. This helps in debugging at the cost of code size.\n */\n#define portPRELOAD_REGISTERS    1\n\n/**\n * @brief A task is created without a secure context, and must call\n * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes\n * any secure calls.\n */\n#define portNO_SECURE_CONTEXT    0\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Used to catch tasks that attempt to return from their implementing\n * function.\n */\nstatic void prvTaskExitError( void );\n\n#if ( configENABLE_MPU == 1 )\n\n/**\n * @brief Setup the Memory Protection Unit (MPU).\n */\n    static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\n#endif /* configENABLE_MPU */\n\n#if ( configENABLE_FPU == 1 )\n\n/**\n * @brief Setup the Floating Point Unit (FPU).\n */\n    static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;\n#endif /* configENABLE_FPU */\n\n/**\n * @brief Setup the timer to generate the tick interrupts.\n *\n * The implementation in this file is weak to allow application writers to\n * change the timer used to generate the tick interrupt.\n */\nvoid vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Checks whether the current execution context is interrupt.\n *\n * @return pdTRUE if the current execution context is interrupt, pdFALSE\n * otherwise.\n */\nBaseType_t xPortIsInsideInterrupt( void );\n\n/**\n * @brief Yield the processor.\n */\nvoid vPortYield( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Enter critical section.\n */\nvoid vPortEnterCritical( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Exit from critical section.\n */\nvoid vPortExitCritical( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief SysTick handler.\n */\nvoid SysTick_Handler( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief C part of SVC handler.\n */\nportDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION;\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Each task maintains its own interrupt status in the critical nesting\n * variable.\n */\nPRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;\n\n#if ( configENABLE_TRUSTZONE == 1 )\n\n/**\n * @brief Saved as part of the task context to indicate which context the\n * task is using on the secure side.\n */\n    PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;\n#endif /* configENABLE_TRUSTZONE */\n\n#if ( configUSE_TICKLESS_IDLE == 1 )\n\n/**\n * @brief The number of SysTick increments that make up one tick period.\n */\n    PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0;\n\n/**\n * @brief The maximum number of tick periods that can be suppressed is\n * limited by the 24 bit resolution of the SysTick timer.\n */\n    PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0;\n\n/**\n * @brief Compensate for the CPU cycles that pass while the SysTick is\n * stopped (low power functionality only).\n */\n    PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TICKLESS_IDLE == 1 )\n    __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )\n    {\n        uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;\n        TickType_t xModifiableIdleTime;\n\n        /* Make sure the SysTick reload value does not overflow the counter. */\n        if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\n        {\n            xExpectedIdleTime = xMaximumPossibleSuppressedTicks;\n        }\n\n        /* Enter a critical section but don't use the taskENTER_CRITICAL()\n         * method as that will mask interrupts that should exit sleep mode. */\n        __asm volatile ( \"cpsid i\" ::: \"memory\" );\n        __asm volatile ( \"dsb\" );\n        __asm volatile ( \"isb\" );\n\n        /* If a context switch is pending or a task is waiting for the scheduler\n         * to be unsuspended then abandon the low power entry. */\n        if( eTaskConfirmSleepModeStatus() == eAbortSleep )\n        {\n            /* Re-enable interrupts - see comments above the cpsid instruction\n             * above. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n        }\n        else\n        {\n            /* Stop the SysTick momentarily.  The time the SysTick is stopped for\n             * is accounted for as best it can be, but using the tickless mode will\n             * inevitably result in some tiny drift of the time maintained by the\n             * kernel with respect to calendar time. */\n            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );\n\n            /* Use the SysTick current-value register to determine the number of\n             * SysTick decrements remaining until the next tick interrupt.  If the\n             * current-value register is zero, then there are actually\n             * ulTimerCountsForOneTick decrements remaining, not zero, because the\n             * SysTick requests the interrupt when decrementing from 1 to 0. */\n            ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n\n            if( ulSysTickDecrementsLeft == 0 )\n            {\n                ulSysTickDecrementsLeft = ulTimerCountsForOneTick;\n            }\n\n            /* Calculate the reload value required to wait xExpectedIdleTime\n             * tick periods.  -1 is used because this code normally executes part\n             * way through the first tick period.  But if the SysTick IRQ is now\n             * pending, then clear the IRQ, suppressing the first tick, and correct\n             * the reload value to reflect that the second tick period is already\n             * underway.  The expected idle time is always at least two ticks. */\n            ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );\n\n            if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )\n            {\n                portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;\n                ulReloadValue -= ulTimerCountsForOneTick;\n            }\n\n            if( ulReloadValue > ulStoppedTimerCompensation )\n            {\n                ulReloadValue -= ulStoppedTimerCompensation;\n            }\n\n            /* Set the new reload value. */\n            portNVIC_SYSTICK_LOAD_REG = ulReloadValue;\n\n            /* Clear the SysTick count flag and set the count value back to\n             * zero. */\n            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n            /* Restart SysTick. */\n            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\n\n            /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can\n             * set its parameter to 0 to indicate that its implementation contains\n             * its own wait for interrupt or wait for event instruction, and so wfi\n             * should not be executed again.  However, the original expected idle\n             * time variable must remain unmodified, so a copy is taken. */\n            xModifiableIdleTime = xExpectedIdleTime;\n            configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\n\n            if( xModifiableIdleTime > 0 )\n            {\n                __asm volatile ( \"dsb\" ::: \"memory\" );\n                __asm volatile ( \"wfi\" );\n                __asm volatile ( \"isb\" );\n            }\n\n            configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\n\n            /* Re-enable interrupts to allow the interrupt that brought the MCU\n             * out of sleep mode to execute immediately.  See comments above\n             * the cpsid instruction above. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n            __asm volatile ( \"dsb\" );\n            __asm volatile ( \"isb\" );\n\n            /* Disable interrupts again because the clock is about to be stopped\n             * and interrupts that execute while the clock is stopped will increase\n             * any slippage between the time maintained by the RTOS and calendar\n             * time. */\n            __asm volatile ( \"cpsid i\" ::: \"memory\" );\n            __asm volatile ( \"dsb\" );\n            __asm volatile ( \"isb\" );\n\n            /* Disable the SysTick clock without reading the\n             * portNVIC_SYSTICK_CTRL_REG register to ensure the\n             * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,\n             * the time the SysTick is stopped for is accounted for as best it can\n             * be, but using the tickless mode will inevitably result in some tiny\n             * drift of the time maintained by the kernel with respect to calendar\n             * time*/\n            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );\n\n            /* Determine whether the SysTick has already counted to zero. */\n            if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n            {\n                uint32_t ulCalculatedLoadValue;\n\n                /* The tick interrupt ended the sleep (or is now pending), and\n                 * a new tick period has started.  Reset portNVIC_SYSTICK_LOAD_REG\n                 * with whatever remains of the new tick period. */\n                ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\n\n                /* Don't allow a tiny value, or values that have somehow\n                 * underflowed because the post sleep hook did something\n                 * that took too long or because the SysTick current-value register\n                 * is zero. */\n                if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )\n                {\n                    ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );\n                }\n\n                portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;\n\n                /* As the pending tick will be processed as soon as this\n                 * function exits, the tick value maintained by the tick is stepped\n                 * forward by one less than the time spent waiting. */\n                ulCompleteTickPeriods = xExpectedIdleTime - 1UL;\n            }\n            else\n            {\n                /* Something other than the tick interrupt ended the sleep. */\n\n                /* Use the SysTick current-value register to determine the\n                 * number of SysTick decrements remaining until the expected idle\n                 * time would have ended. */\n                ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n                #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )\n                {\n                    /* If the SysTick is not using the core clock, the current-\n                     * value register might still be zero here.  In that case, the\n                     * SysTick didn't load from the reload register, and there are\n                     * ulReloadValue decrements remaining in the expected idle\n                     * time, not zero. */\n                    if( ulSysTickDecrementsLeft == 0 )\n                    {\n                        ulSysTickDecrementsLeft = ulReloadValue;\n                    }\n                }\n                #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */\n\n                /* Work out how long the sleep lasted rounded to complete tick\n                 * periods (not the ulReload value which accounted for part\n                 * ticks). */\n                ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;\n\n                /* How many complete tick periods passed while the processor\n                 * was waiting? */\n                ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;\n\n                /* The reload value is set to whatever fraction of a single tick\n                 * period remains. */\n                portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;\n            }\n\n            /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,\n             * then set portNVIC_SYSTICK_LOAD_REG back to its standard value.  If\n             * the SysTick is not using the core clock, temporarily configure it to\n             * use the core clock.  This configuration forces the SysTick to load\n             * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next\n             * cycle of the other clock.  Then portNVIC_SYSTICK_LOAD_REG is ready\n             * to receive the standard value immediately. */\n            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n            portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n            #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )\n            {\n                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n            }\n            #else\n            {\n                /* The temporary usage of the core clock has served its purpose,\n                 * as described above.  Resume usage of the other clock. */\n                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\n\n                if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n                {\n                    /* The partial tick period already ended.  Be sure the SysTick\n                     * counts it only once. */\n                    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;\n                }\n\n                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n            }\n            #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */\n\n            /* Step the tick to account for any tick periods that elapsed. */\n            vTaskStepTick( ulCompleteTickPeriods );\n\n            /* Exit with interrupts enabled. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n        }\n    }\n#endif /* configUSE_TICKLESS_IDLE */\n/*-----------------------------------------------------------*/\n\n__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Calculate the constants required to configure the tick interrupt. */\n    #if ( configUSE_TICKLESS_IDLE == 1 )\n    {\n        ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );\n        xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;\n        ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\n    }\n    #endif /* configUSE_TICKLESS_IDLE */\n\n    /* Stop and reset the SysTick. */\n    portNVIC_SYSTICK_CTRL_REG = 0UL;\n    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n    /* Configure SysTick to interrupt at the requested rate. */\n    portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\n    portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvTaskExitError( void )\n{\n    volatile uint32_t ulDummy = 0UL;\n\n    /* A function that implements a task must not exit or attempt to return to\n     * its caller as there is nothing to return to. If a task wants to exit it\n     * should instead call vTaskDelete( NULL ). Artificially force an assert()\n     * to be triggered if configASSERT() is defined, then stop here so\n     * application writers can catch the error. */\n    configASSERT( ulCriticalNesting == ~0UL );\n    portDISABLE_INTERRUPTS();\n\n    while( ulDummy == 0 )\n    {\n        /* This file calls prvTaskExitError() after the scheduler has been\n         * started to remove a compiler warning about the function being\n         * defined but never called.  ulDummy is used purely to quieten other\n         * warnings about code appearing after this function is called - making\n         * ulDummy volatile makes the compiler think the function could return\n         * and therefore not output an 'unreachable code' warning for code that\n         * appears after it. */\n    }\n}\n/*-----------------------------------------------------------*/\n\n#if ( configENABLE_MPU == 1 )\n    static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */\n    {\n        #if defined( __ARMCC_VERSION )\n\n            /* Declaration when these variable are defined in code instead of being\n             * exported from linker scripts. */\n            extern uint32_t * __privileged_functions_start__;\n            extern uint32_t * __privileged_functions_end__;\n            extern uint32_t * __syscalls_flash_start__;\n            extern uint32_t * __syscalls_flash_end__;\n            extern uint32_t * __unprivileged_flash_start__;\n            extern uint32_t * __unprivileged_flash_end__;\n            extern uint32_t * __privileged_sram_start__;\n            extern uint32_t * __privileged_sram_end__;\n        #else /* if defined( __ARMCC_VERSION ) */\n            /* Declaration when these variable are exported from linker scripts. */\n            extern uint32_t __privileged_functions_start__[];\n            extern uint32_t __privileged_functions_end__[];\n            extern uint32_t __syscalls_flash_start__[];\n            extern uint32_t __syscalls_flash_end__[];\n            extern uint32_t __unprivileged_flash_start__[];\n            extern uint32_t __unprivileged_flash_end__[];\n            extern uint32_t __privileged_sram_start__[];\n            extern uint32_t __privileged_sram_end__[];\n        #endif /* defined( __ARMCC_VERSION ) */\n\n        /* The only permitted number of regions are 8 or 16. */\n        configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );\n\n        /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */\n        configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );\n\n        /* Check that the MPU is present. */\n        if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )\n        {\n            /* MAIR0 - Index 0. */\n            portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\n            /* MAIR0 - Index 1. */\n            portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\n\n            /* Setup privileged flash as Read Only so that privileged tasks can\n             * read it but not modify. */\n            portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_PRIVILEGED_READ_ONLY );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Setup unprivileged flash as Read Only by both privileged and\n             * unprivileged tasks. All tasks can read it but no-one can modify. */\n            portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_READ_ONLY );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Setup unprivileged syscalls flash as Read Only by both privileged\n             * and unprivileged tasks. All tasks can read it but no-one can modify. */\n            portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_READ_ONLY );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Setup RAM containing kernel data for privileged access only. */\n            portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\n                               ( portMPU_REGION_EXECUTE_NEVER );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Enable mem fault. */\n            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;\n\n            /* Enable MPU with privileged background access i.e. unmapped\n             * regions have privileged access. */\n            portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );\n        }\n    }\n#endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\n#if ( configENABLE_FPU == 1 )\n    static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */\n    {\n        #if ( configENABLE_TRUSTZONE == 1 )\n        {\n            /* Enable non-secure access to the FPU. */\n            SecureInit_EnableNSFPUAccess();\n        }\n        #endif /* configENABLE_TRUSTZONE */\n\n        /* CP10 = 11 ==> Full access to FPU i.e. both privileged and\n         * unprivileged code should be able to access FPU. CP11 should be\n         * programmed to the same value as CP10. */\n        *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |\n                            ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )\n                            );\n\n        /* ASPEN = 1 ==> Hardware should automatically preserve floating point\n         * context on exception entry and restore on exception return.\n         * LSPEN = 1 ==> Enable lazy context save of FP state. */\n        *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );\n    }\n#endif /* configENABLE_FPU */\n/*-----------------------------------------------------------*/\n\nvoid vPortYield( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Set a PendSV to request a context switch. */\n    portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\n\n    /* Barriers are normally not required but do ensure the code is\n     * completely within the specified behaviour for the architecture. */\n    __asm volatile ( \"dsb\" ::: \"memory\" );\n    __asm volatile ( \"isb\" );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */\n{\n    portDISABLE_INTERRUPTS();\n    ulCriticalNesting++;\n\n    /* Barriers are normally not required but do ensure the code is\n     * completely within the specified behaviour for the architecture. */\n    __asm volatile ( \"dsb\" ::: \"memory\" );\n    __asm volatile ( \"isb\" );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */\n{\n    configASSERT( ulCriticalNesting );\n    ulCriticalNesting--;\n\n    if( ulCriticalNesting == 0 )\n    {\n        portENABLE_INTERRUPTS();\n    }\n}\n/*-----------------------------------------------------------*/\n\nvoid SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */\n{\n    uint32_t ulPreviousMask;\n\n    ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();\n    {\n        /* Increment the RTOS tick. */\n        if( xTaskIncrementTick() != pdFALSE )\n        {\n            /* Pend a context switch. */\n            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\n        }\n    }\n    portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */\n{\n    #if ( configENABLE_MPU == 1 )\n        #if defined( __ARMCC_VERSION )\n\n            /* Declaration when these variable are defined in code instead of being\n             * exported from linker scripts. */\n            extern uint32_t * __syscalls_flash_start__;\n            extern uint32_t * __syscalls_flash_end__;\n        #else\n            /* Declaration when these variable are exported from linker scripts. */\n            extern uint32_t __syscalls_flash_start__[];\n            extern uint32_t __syscalls_flash_end__[];\n        #endif /* defined( __ARMCC_VERSION ) */\n    #endif /* configENABLE_MPU */\n\n    uint32_t ulPC;\n\n    #if ( configENABLE_TRUSTZONE == 1 )\n        uint32_t ulR0, ulR1;\n        extern TaskHandle_t pxCurrentTCB;\n        #if ( configENABLE_MPU == 1 )\n            uint32_t ulControl, ulIsTaskPrivileged;\n        #endif /* configENABLE_MPU */\n    #endif /* configENABLE_TRUSTZONE */\n    uint8_t ucSVCNumber;\n\n    /* Register are stored on the stack in the following order - R0, R1, R2, R3,\n     * R12, LR, PC, xPSR. */\n    ulPC = pulCallerStackAddress[ 6 ];\n    ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];\n\n    switch( ucSVCNumber )\n    {\n        #if ( configENABLE_TRUSTZONE == 1 )\n            case portSVC_ALLOCATE_SECURE_CONTEXT:\n\n                /* R0 contains the stack size passed as parameter to the\n                 * vPortAllocateSecureContext function. */\n                ulR0 = pulCallerStackAddress[ 0 ];\n\n                #if ( configENABLE_MPU == 1 )\n                {\n                    /* Read the CONTROL register value. */\n                    __asm volatile ( \"mrs %0, control\"  : \"=r\" ( ulControl ) );\n\n                    /* The task that raised the SVC is privileged if Bit[0]\n                     * in the CONTROL register is 0. */\n                    ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );\n\n                    /* Allocate and load a context for the secure task. */\n                    xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );\n                }\n                #else /* if ( configENABLE_MPU == 1 ) */\n                {\n                    /* Allocate and load a context for the secure task. */\n                    xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );\n                }\n                #endif /* configENABLE_MPU */\n\n                configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );\n                SecureContext_LoadContext( xSecureContext, pxCurrentTCB );\n                break;\n\n            case portSVC_FREE_SECURE_CONTEXT:\n\n                /* R0 contains TCB being freed and R1 contains the secure\n                 * context handle to be freed. */\n                ulR0 = pulCallerStackAddress[ 0 ];\n                ulR1 = pulCallerStackAddress[ 1 ];\n\n                /* Free the secure context. */\n                SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );\n                break;\n        #endif /* configENABLE_TRUSTZONE */\n\n        case portSVC_START_SCHEDULER:\n            #if ( configENABLE_TRUSTZONE == 1 )\n            {\n                /* De-prioritize the non-secure exceptions so that the\n                 * non-secure pendSV runs at the lowest priority. */\n                SecureInit_DePrioritizeNSExceptions();\n\n                /* Initialize the secure context management system. */\n                SecureContext_Init();\n            }\n            #endif /* configENABLE_TRUSTZONE */\n\n            #if ( configENABLE_FPU == 1 )\n            {\n                /* Setup the Floating Point Unit (FPU). */\n                prvSetupFPU();\n            }\n            #endif /* configENABLE_FPU */\n\n            /* Setup the context of the first task so that the first task starts\n             * executing. */\n            vRestoreContextOfFirstTask();\n            break;\n\n            #if ( configENABLE_MPU == 1 )\n                case portSVC_RAISE_PRIVILEGE:\n\n                    /* Only raise the privilege, if the svc was raised from any of\n                     * the system calls. */\n                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&\n                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )\n                    {\n                        vRaisePrivilege();\n                    }\n                    break;\n            #endif /* configENABLE_MPU */\n\n        default:\n            /* Incorrect SVC call. */\n            configASSERT( pdFALSE );\n    }\n}\n/*-----------------------------------------------------------*/\n/* *INDENT-OFF* */\n#if ( configENABLE_MPU == 1 )\n    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,\n                                         StackType_t * pxEndOfStack,\n                                         TaskFunction_t pxCode,\n                                         void * pvParameters,\n                                         BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */\n#else\n    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,\n                                         StackType_t * pxEndOfStack,\n                                         TaskFunction_t pxCode,\n                                         void * pvParameters ) /* PRIVILEGED_FUNCTION */\n#endif /* configENABLE_MPU */\n/* *INDENT-ON* */\n{\n    /* Simulate the stack frame as it would be created by a context switch\n     * interrupt. */\n    #if ( portPRELOAD_REGISTERS == 0 )\n    {\n        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\n        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\n        pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */\n        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */\n        pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */\n        *pxTopOfStack = portINITIAL_EXC_RETURN;\n\n        #if ( configENABLE_MPU == 1 )\n        {\n            pxTopOfStack--;\n\n            if( xRunPrivileged == pdTRUE )\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n            else\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n        }\n        #endif /* configENABLE_MPU */\n\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\n\n        #if ( configENABLE_TRUSTZONE == 1 )\n        {\n            pxTopOfStack--;\n            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\n        }\n        #endif /* configENABLE_TRUSTZONE */\n    }\n    #else /* portPRELOAD_REGISTERS */\n    {\n        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\n        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04 */\n        pxTopOfStack--;\n        *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN */\n\n        #if ( configENABLE_MPU == 1 )\n        {\n            pxTopOfStack--;\n\n            if( xRunPrivileged == pdTRUE )\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n            else\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n        }\n        #endif /* configENABLE_MPU */\n\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\n\n        #if ( configENABLE_TRUSTZONE == 1 )\n        {\n            pxTopOfStack--;\n            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\n        }\n        #endif /* configENABLE_TRUSTZONE */\n    }\n    #endif /* portPRELOAD_REGISTERS */\n\n    return pxTopOfStack;\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Make PendSV, CallSV and SysTick the same priority as the kernel. */\n    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;\n    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;\n\n    #if ( configENABLE_MPU == 1 )\n    {\n        /* Setup the Memory Protection Unit (MPU). */\n        prvSetupMPU();\n    }\n    #endif /* configENABLE_MPU */\n\n    /* Start the timer that generates the tick ISR. Interrupts are disabled\n     * here already. */\n    vPortSetupTimerInterrupt();\n\n    /* Initialize the critical nesting count ready for the first task. */\n    ulCriticalNesting = 0;\n\n    /* Start the first task. */\n    vStartFirstTask();\n\n    /* Should never get here as the tasks will now be executing. Call the task\n     * exit error function to prevent compiler warnings about a static function\n     * not being called in the case that the application writer overrides this\n     * functionality by defining configTASK_RETURN_ADDRESS. Call\n     * vTaskSwitchContext() so link time optimization does not remove the\n     * symbol. */\n    vTaskSwitchContext();\n    prvTaskExitError();\n\n    /* Should not get here. */\n    return 0;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Not implemented in ports where there is nothing to return to.\n     * Artificially force an assert. */\n    configASSERT( ulCriticalNesting == 1000UL );\n}\n/*-----------------------------------------------------------*/\n\n#if ( configENABLE_MPU == 1 )\n    void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,\n                                    const struct xMEMORY_REGION * const xRegions,\n                                    StackType_t * pxBottomOfStack,\n                                    uint32_t ulStackDepth )\n    {\n        uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;\n        int32_t lIndex = 0;\n\n        #if defined( __ARMCC_VERSION )\n\n            /* Declaration when these variable are defined in code instead of being\n             * exported from linker scripts. */\n            extern uint32_t * __privileged_sram_start__;\n            extern uint32_t * __privileged_sram_end__;\n        #else\n            /* Declaration when these variable are exported from linker scripts. */\n            extern uint32_t __privileged_sram_start__[];\n            extern uint32_t __privileged_sram_end__[];\n        #endif /* defined( __ARMCC_VERSION ) */\n\n        /* Setup MAIR0. */\n        xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\n        xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\n\n        /* This function is called automatically when the task is created - in\n         * which case the stack region parameters will be valid.  At all other\n         * times the stack parameters will not be valid and it is assumed that\n         * the stack region has already been configured. */\n        if( ulStackDepth > 0 )\n        {\n            ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;\n            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;\n\n            /* If the stack is within the privileged SRAM, do not protect it\n             * using a separate MPU region. This is needed because privileged\n             * SRAM is already protected using an MPU region and ARMv8-M does\n             * not allow overlapping MPU regions. */\n            if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) &&\n                ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) )\n            {\n                xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0;\n                xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0;\n            }\n            else\n            {\n                /* Define the region that allows access to the stack. */\n                ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK;\n                ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\n\n                xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |\n                                                             ( portMPU_REGION_NON_SHAREABLE ) |\n                                                             ( portMPU_REGION_READ_WRITE ) |\n                                                             ( portMPU_REGION_EXECUTE_NEVER );\n\n                xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) |\n                                                             ( portMPU_RLAR_ATTR_INDEX0 ) |\n                                                             ( portMPU_RLAR_REGION_ENABLE );\n            }\n        }\n\n        /* User supplied configurable regions. */\n        for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )\n        {\n            /* If xRegions is NULL i.e. the task has not specified any MPU\n             * region, the else part ensures that all the configurable MPU\n             * regions are invalidated. */\n            if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )\n            {\n                /* Translate the generic region definition contained in xRegions\n                 * into the ARMv8 specific MPU settings that are then stored in\n                 * xMPUSettings. */\n                ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;\n                ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;\n                ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\n\n                /* Start address. */\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |\n                                                                          ( portMPU_REGION_NON_SHAREABLE );\n\n                /* RO/RW. */\n                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )\n                {\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );\n                }\n                else\n                {\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );\n                }\n\n                /* XN. */\n                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )\n                {\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );\n                }\n\n                /* End Address. */\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |\n                                                                          ( portMPU_RLAR_REGION_ENABLE );\n\n                /* Normal memory/ Device memory. */\n                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )\n                {\n                    /* Attr1 in MAIR0 is configured as device memory. */\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;\n                }\n                else\n                {\n                    /* Attr0 in MAIR0 is configured as normal memory. */\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;\n                }\n            }\n            else\n            {\n                /* Invalidate the region. */\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;\n            }\n\n            lIndex++;\n        }\n    }\n#endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\nBaseType_t xPortIsInsideInterrupt( void )\n{\n    uint32_t ulCurrentInterrupt;\n    BaseType_t xReturn;\n\n    /* Obtain the number of the currently executing interrupt. Interrupt Program\n     * Status Register (IPSR) holds the exception number of the currently-executing\n     * exception or zero for Thread mode.*/\n    __asm volatile ( \"mrs %0, ipsr\" : \"=r\" ( ulCurrentInterrupt )::\"memory\" );\n\n    if( ulCurrentInterrupt == 0 )\n    {\n        xReturn = pdFALSE;\n    }\n    else\n    {\n        xReturn = pdTRUE;\n    }\n\n    return xReturn;\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM23/non_secure/portasm.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef __PORT_ASM_H__\n#define __PORT_ASM_H__\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n\n/* MPU wrappers includes. */\n#include \"mpu_wrappers.h\"\n\n/**\n * @brief Restore the context of the first task so that the first task starts\n * executing.\n */\nvoid vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Checks whether or not the processor is privileged.\n *\n * @return 1 if the processor is already privileged, 0 otherwise.\n */\nBaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );\n\n/**\n * @brief Raises the privilege level by clearing the bit 0 of the CONTROL\n * register.\n *\n * @note This is a privileged function and should only be called from the kenrel\n * code.\n *\n * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.\n *  Bit[0] = 0 --> The processor is running privileged\n *  Bit[0] = 1 --> The processor is running unprivileged.\n */\nvoid vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\n * register.\n *\n * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.\n *  Bit[0] = 0 --> The processor is running privileged\n *  Bit[0] = 1 --> The processor is running unprivileged.\n */\nvoid vResetPrivilege( void ) __attribute__( ( naked ) );\n\n/**\n * @brief Starts the first task.\n */\nvoid vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Disables interrupts.\n */\nuint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Enables interrupts.\n */\nvoid vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief PendSV Exception handler.\n */\nvoid PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief SVC Handler.\n */\nvoid SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Allocate a Secure context for the calling task.\n *\n * @param[in] ulSecureStackSize The size of the stack to be allocated on the\n * secure side for the calling task.\n */\nvoid vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) );\n\n/**\n * @brief Free the task's secure context.\n *\n * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.\n */\nvoid vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n#endif /* __PORT_ASM_H__ */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM23/non_secure/portasm.s",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Including FreeRTOSConfig.h here will cause build errors if the header file\ncontains code not understood by the assembler - for example the 'extern' keyword.\nTo avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so\nthe code is included in C files but excluded by the preprocessor in assembly\nfiles (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */\n#include \"FreeRTOSConfig.h\"\n\n\tEXTERN pxCurrentTCB\n\tEXTERN xSecureContext\n\tEXTERN vTaskSwitchContext\n\tEXTERN vPortSVCHandler_C\n\tEXTERN SecureContext_SaveContext\n\tEXTERN SecureContext_LoadContext\n\n\tPUBLIC xIsPrivileged\n\tPUBLIC vResetPrivilege\n\tPUBLIC vPortAllocateSecureContext\n\tPUBLIC vRestoreContextOfFirstTask\n\tPUBLIC vRaisePrivilege\n\tPUBLIC vStartFirstTask\n\tPUBLIC ulSetInterruptMask\n\tPUBLIC vClearInterruptMask\n\tPUBLIC PendSV_Handler\n\tPUBLIC SVC_Handler\n\tPUBLIC vPortFreeSecureContext\n\n#if ( configENABLE_FPU == 1 )\n\t#error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.\n#endif\n/*-----------------------------------------------------------*/\n\n/*---------------- Unprivileged Functions -------------------*/\n\n/*-----------------------------------------------------------*/\n\n\tSECTION .text:CODE:NOROOT(2)\n\tTHUMB\n/*-----------------------------------------------------------*/\n\nxIsPrivileged:\n\tmrs r0, control\t\t\t\t\t\t\t/* r0 = CONTROL. */\n\tmovs r1, #1\t\t\t\t\t\t\t\t/* r1 = 1. */\n\ttst r0, r1\t\t\t\t\t\t\t\t/* Perform r0 & r1 (bitwise AND) and update the conditions flag. */\n\tbeq running_privileged\t\t\t\t\t/* If the result of previous AND operation was 0, branch. */\n\tmovs r0, #0\t\t\t\t\t\t\t\t/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\n\tbx lr\t\t\t\t\t\t\t\t\t/* Return. */\n\trunning_privileged:\n\t\tmovs r0, #1\t\t\t\t\t\t\t/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */\n\t\tbx lr\t\t\t\t\t\t\t\t/* Return. */\n/*-----------------------------------------------------------*/\n\nvResetPrivilege:\n\tmrs r0, control\t\t\t\t\t\t\t/* r0 = CONTROL. */\n\tmovs r1, #1\t\t\t\t\t\t\t\t/* r1 = 1. */\n\torrs r0, r1\t\t\t\t\t\t\t\t/* r0 = r0 | r1. */\n\tmsr control, r0\t\t\t\t\t\t\t/* CONTROL = r0. */\n\tbx lr\t\t\t\t\t\t\t\t\t/* Return to the caller. */\n/*-----------------------------------------------------------*/\n\nvPortAllocateSecureContext:\n\tsvc 0\t\t\t\t\t\t\t\t\t/* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 0. */\n\tbx lr\t\t\t\t\t\t\t\t\t/* Return. */\n/*-----------------------------------------------------------*/\n\n/*----------------- Privileged Functions --------------------*/\n\n/*-----------------------------------------------------------*/\n\n\tSECTION privileged_functions:CODE:NOROOT(2)\n\tTHUMB\n/*-----------------------------------------------------------*/\n\nvRestoreContextOfFirstTask:\n\tldr  r2, =pxCurrentTCB\t\t\t\t\t/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n\tldr  r3, [r2]\t\t\t\t\t\t\t/* Read pxCurrentTCB. */\n\tldr  r0, [r3]\t\t\t\t\t\t\t/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\n\n#if ( configENABLE_MPU == 1 )\n\tdmb\t\t\t\t\t\t\t\t\t\t/* Complete outstanding transfers before disabling MPU. */\n\tldr r2, =0xe000ed94\t\t\t\t\t\t/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n\tldr r4, [r2]\t\t\t\t\t\t\t/* Read the value of MPU_CTRL. */\n\tmovs r5, #1\t\t\t\t\t\t\t\t/* r5 = 1. */\n\tbics r4, r5\t\t\t\t\t\t\t\t/* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */\n\tstr r4, [r2]\t\t\t\t\t\t\t/* Disable MPU. */\n\n\tadds r3, #4\t\t\t\t\t\t\t\t/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\n\tldr  r4, [r3]\t\t\t\t\t\t\t/* r4 = *r3 i.e. r4 = MAIR0. */\n\tldr  r2, =0xe000edc0\t\t\t\t\t/* r2 = 0xe000edc0 [Location of MAIR0]. */\n\tstr  r4, [r2]\t\t\t\t\t\t\t/* Program MAIR0. */\n\tldr  r2, =0xe000ed98\t\t\t\t\t/* r2 = 0xe000ed98 [Location of RNR]. */\n\tadds r3, #4\t\t\t\t\t\t\t\t/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */\n\tmovs r5, #4\t\t\t\t\t\t\t\t/* r5 = 4. */\n\tstr  r5, [r2]\t\t\t\t\t\t\t/* Program RNR = 4. */\n\tldmia r3!, {r6,r7}\t\t\t\t\t\t/* Read first set of RBAR/RLAR from TCB. */\n\tldr  r4, =0xe000ed9c\t\t\t\t\t/* r4 = 0xe000ed9c [Location of RBAR]. */\n\tstmia r4!, {r6,r7}\t\t\t\t\t\t/* Write first set of RBAR/RLAR registers. */\n\tmovs r5, #5\t\t\t\t\t\t\t\t/* r5 = 5. */\n\tstr  r5, [r2]\t\t\t\t\t\t\t/* Program RNR = 5. */\n\tldmia r3!, {r6,r7}\t\t\t\t\t\t/* Read second set of RBAR/RLAR from TCB. */\n\tldr  r4, =0xe000ed9c\t\t\t\t\t/* r4 = 0xe000ed9c [Location of RBAR]. */\n\tstmia r4!, {r6,r7}\t\t\t\t\t\t/* Write second set of RBAR/RLAR registers. */\n\tmovs r5, #6\t\t\t\t\t\t\t\t/* r5 = 6. */\n\tstr  r5, [r2]\t\t\t\t\t\t\t/* Program RNR = 6. */\n\tldmia r3!, {r6,r7}\t\t\t\t\t\t/* Read third set of RBAR/RLAR from TCB. */\n\tldr  r4, =0xe000ed9c\t\t\t\t\t/* r4 = 0xe000ed9c [Location of RBAR]. */\n\tstmia r4!, {r6,r7}\t\t\t\t\t\t/* Write third set of RBAR/RLAR registers. */\n\tmovs r5, #7\t\t\t\t\t\t\t\t/* r5 = 7. */\n\tstr  r5, [r2]\t\t\t\t\t\t\t/* Program RNR = 7. */\n\tldmia r3!, {r6,r7}\t\t\t\t\t\t/* Read fourth set of RBAR/RLAR from TCB. */\n\tldr  r4, =0xe000ed9c\t\t\t\t\t/* r4 = 0xe000ed9c [Location of RBAR]. */\n\tstmia r4!, {r6,r7}\t\t\t\t\t\t/* Write fourth set of RBAR/RLAR registers. */\n\n\tldr r2, =0xe000ed94\t\t\t\t\t\t/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n\tldr r4, [r2]\t\t\t\t\t\t\t/* Read the value of MPU_CTRL. */\n\tmovs r5, #1\t\t\t\t\t\t\t\t/* r5 = 1. */\n\torrs r4, r5\t\t\t\t\t\t\t\t/* r4 = r4 | r5 i.e. Set the bit 0 in r4. */\n\tstr r4, [r2]\t\t\t\t\t\t\t/* Enable MPU. */\n\tdsb\t\t\t\t\t\t\t\t\t\t/* Force memory writes before continuing. */\n#endif /* configENABLE_MPU */\n\n#if ( configENABLE_MPU == 1 )\n\tldm  r0!, {r1-r4}\t\t\t\t\t\t/* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */\n\tldr  r5, =xSecureContext\n\tstr  r1, [r5]\t\t\t\t\t\t\t/* Set xSecureContext to this task's value for the same. */\n\tmsr  psplim, r2\t\t\t\t\t\t\t/* Set this task's PSPLIM value. */\n\tmsr  control, r3\t\t\t\t\t\t/* Set this task's CONTROL value. */\n\tadds r0, #32\t\t\t\t\t\t\t/* Discard everything up to r0. */\n\tmsr  psp, r0\t\t\t\t\t\t\t/* This is now the new top of stack to use in the task. */\n\tisb\n\tbx   r4\t\t\t\t\t\t\t\t\t/* Finally, branch to EXC_RETURN. */\n#else /* configENABLE_MPU */\n\tldm  r0!, {r1-r3}\t\t\t\t\t\t/* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */\n\tldr  r4, =xSecureContext\n\tstr  r1, [r4]\t\t\t\t\t\t\t/* Set xSecureContext to this task's value for the same. */\n\tmsr  psplim, r2\t\t\t\t\t\t\t/* Set this task's PSPLIM value. */\n\tmovs r1, #2\t\t\t\t\t\t\t\t/* r1 = 2. */\n\tmsr  CONTROL, r1\t\t\t\t\t\t/* Switch to use PSP in the thread mode. */\n\tadds r0, #32\t\t\t\t\t\t\t/* Discard everything up to r0. */\n\tmsr  psp, r0\t\t\t\t\t\t\t/* This is now the new top of stack to use in the task. */\n\tisb\n\tbx   r3\t\t\t\t\t\t\t\t\t/* Finally, branch to EXC_RETURN. */\n#endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\nvRaisePrivilege:\n\tmrs r0, control\t\t\t\t\t\t\t/* Read the CONTROL register. */\n\tmovs r1, #1\t\t\t\t\t\t\t\t/* r1 = 1. */\n\tbics r0, r1\t\t\t\t\t\t\t\t/* Clear the bit 0. */\n\tmsr control, r0\t\t\t\t\t\t\t/* Write back the new CONTROL value. */\n\tbx lr\t\t\t\t\t\t\t\t\t/* Return to the caller. */\n/*-----------------------------------------------------------*/\n\nvStartFirstTask:\n\tldr r0, =0xe000ed08\t\t\t\t\t\t/* Use the NVIC offset register to locate the stack. */\n\tldr r0, [r0]\t\t\t\t\t\t\t/* Read the VTOR register which gives the address of vector table. */\n\tldr r0, [r0]\t\t\t\t\t\t\t/* The first entry in vector table is stack pointer. */\n\tmsr msp, r0\t\t\t\t\t\t\t\t/* Set the MSP back to the start of the stack. */\n\tcpsie i\t\t\t\t\t\t\t\t\t/* Globally enable interrupts. */\n\tdsb\n\tisb\n\tsvc 2\t\t\t\t\t\t\t\t\t/* System call to start the first task. portSVC_START_SCHEDULER = 2. */\n/*-----------------------------------------------------------*/\n\nulSetInterruptMask:\n\tmrs r0, PRIMASK\n\tcpsid i\n\tbx lr\n/*-----------------------------------------------------------*/\n\nvClearInterruptMask:\n\tmsr PRIMASK, r0\n\tbx lr\n/*-----------------------------------------------------------*/\n\nPendSV_Handler:\n\tldr r3, =xSecureContext\t\t\t\t\t/* Read the location of xSecureContext i.e. &( xSecureContext ). */\n\tldr r0, [r3]\t\t\t\t\t\t\t/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */\n\tldr r3, =pxCurrentTCB\t\t\t\t\t/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n\tldr r1, [r3]\t\t\t\t\t\t\t/* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */\n\tmrs r2, psp\t\t\t\t\t\t\t\t/* Read PSP in r2. */\n\n\tcbz r0, save_ns_context\t\t\t\t\t/* No secure context to save. */\n\tpush {r0-r2, r14}\n\tbl SecureContext_SaveContext\t\t\t/* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */\n\tpop {r0-r3}\t\t\t\t\t\t\t\t/* LR is now in r3. */\n\tmov lr, r3\t\t\t\t\t\t\t\t/* LR = r3. */\n\tlsls r1, r3, #25\t\t\t\t\t\t/* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\n\tbpl save_ns_context\t\t\t\t\t\t/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\n\tldr r3, =pxCurrentTCB\t\t\t\t\t/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n\tldr r1, [r3]\t\t\t\t\t\t\t/* Read pxCurrentTCB. */\n#if ( configENABLE_MPU == 1 )\n\tsubs r2, r2, #16\t\t\t\t\t\t/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */\n\tstr r2, [r1]\t\t\t\t\t\t\t/* Save the new top of stack in TCB. */\n\tmrs r1, psplim\t\t\t\t\t\t\t/* r1 = PSPLIM. */\n\tmrs r3, control\t\t\t\t\t\t\t/* r3 = CONTROL. */\n\tmov r4, lr\t\t\t\t\t\t\t\t/* r4 = LR/EXC_RETURN. */\n\tstmia r2!, {r0, r1, r3, r4}\t\t\t\t/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\n#else /* configENABLE_MPU */\n\tsubs r2, r2, #12\t\t\t\t\t\t/* Make space for xSecureContext, PSPLIM and LR on the stack. */\n\tstr r2, [r1]\t\t\t\t\t\t\t/* Save the new top of stack in TCB. */\n\tmrs r1, psplim\t\t\t\t\t\t\t/* r1 = PSPLIM. */\n\tmov r3, lr\t\t\t\t\t\t\t\t/* r3 = LR/EXC_RETURN. */\n\tstmia r2!, {r0, r1, r3}\t\t\t\t\t/* Store xSecureContext, PSPLIM and LR on the stack. */\n#endif /* configENABLE_MPU */\n\tb select_next_task\n\n\tsave_ns_context:\n\t\tldr r3, =pxCurrentTCB\t\t\t\t/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n\t\tldr r1, [r3]\t\t\t\t\t\t/* Read pxCurrentTCB. */\n\t#if ( configENABLE_MPU == 1 )\n\t\tsubs r2, r2, #48\t\t\t\t\t/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */\n\t\tstr r2, [r1]\t\t\t\t\t\t/* Save the new top of stack in TCB. */\n\t\tadds r2, r2, #16\t\t\t\t\t/* r2 = r2 + 16. */\n\t\tstmia r2!, {r4-r7}\t\t\t\t\t/* Store the low registers that are not saved automatically. */\n\t\tmov r4, r8\t\t\t\t\t\t\t/* r4 = r8. */\n\t\tmov r5, r9\t\t\t\t\t\t\t/* r5 = r9. */\n\t\tmov r6, r10\t\t\t\t\t\t\t/* r6 = r10. */\n\t\tmov r7, r11\t\t\t\t\t\t\t/* r7 = r11. */\n\t\tstmia r2!, {r4-r7}\t\t\t\t\t/* Store the high registers that are not saved automatically. */\n\t\tmrs r1, psplim\t\t\t\t\t\t/* r1 = PSPLIM. */\n\t\tmrs r3, control\t\t\t\t\t\t/* r3 = CONTROL. */\n\t\tmov r4, lr\t\t\t\t\t\t\t/* r4 = LR/EXC_RETURN. */\n\t\tsubs r2, r2, #48\t\t\t\t\t/* r2 = r2 - 48. */\n\t\tstmia r2!, {r0, r1, r3, r4}\t\t\t/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\n\t#else /* configENABLE_MPU */\n\t\tsubs r2, r2, #44\t\t\t\t\t/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */\n\t\tstr r2, [r1]\t\t\t\t\t\t/* Save the new top of stack in TCB. */\n\t\tmrs r1, psplim\t\t\t\t\t\t/* r1 = PSPLIM. */\n\t\tmov r3, lr\t\t\t\t\t\t\t/* r3 = LR/EXC_RETURN. */\n\t\tstmia r2!, {r0, r1, r3-r7}\t\t\t/* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */\n\t\tmov r4, r8\t\t\t\t\t\t\t/* r4 = r8. */\n\t\tmov r5, r9\t\t\t\t\t\t\t/* r5 = r9. */\n\t\tmov r6, r10\t\t\t\t\t\t\t/* r6 = r10. */\n\t\tmov r7, r11\t\t\t\t\t\t\t/* r7 = r11. */\n\t\tstmia r2!, {r4-r7}\t\t\t\t\t/* Store the high registers that are not saved automatically. */\n\t#endif /* configENABLE_MPU */\n\n\tselect_next_task:\n\t\tcpsid i\n\t\tbl vTaskSwitchContext\n\t\tcpsie i\n\n\t\tldr r3, =pxCurrentTCB\t\t\t\t/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n\t\tldr r1, [r3]\t\t\t\t\t\t/* Read pxCurrentTCB. */\n\t\tldr r2, [r1]\t\t\t\t\t\t/* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */\n\n\t#if ( configENABLE_MPU == 1 )\n\t\tdmb\t\t\t\t\t\t\t\t\t/* Complete outstanding transfers before disabling MPU. */\n\t\tldr r3, =0xe000ed94\t\t\t\t\t/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */\n\t\tldr r4, [r3]\t\t\t\t\t\t/* Read the value of MPU_CTRL. */\n\t\tmovs r5, #1\t\t\t\t\t\t\t/* r5 = 1. */\n\t\tbics r4, r5\t\t\t\t\t\t\t/* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */\n\t\tstr r4, [r3]\t\t\t\t\t\t/* Disable MPU. */\n\n\t\tadds r1, #4\t\t\t\t\t\t\t/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\n\t\tldr r4, [r1]\t\t\t\t\t\t/* r4 = *r1 i.e. r4 = MAIR0. */\n\t\tldr r3, =0xe000edc0\t\t\t\t\t/* r3 = 0xe000edc0 [Location of MAIR0]. */\n\t\tstr r4, [r3]\t\t\t\t\t\t/* Program MAIR0. */\n\t\tldr r4, =0xe000ed98\t\t\t\t\t/* r4 = 0xe000ed98 [Location of RNR]. */\n\t\tadds r1, #4\t\t\t\t\t\t\t/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\n\t\tmovs r5, #4\t\t\t\t\t\t\t/* r5 = 4. */\n\t\tstr  r5, [r4]\t\t\t\t\t\t/* Program RNR = 4. */\n\t\tldmia r1!, {r6,r7}\t\t\t\t\t/* Read first set of RBAR/RLAR from TCB. */\n\t\tldr  r3, =0xe000ed9c\t\t\t\t/* r3 = 0xe000ed9c [Location of RBAR]. */\n\t\tstmia r3!, {r6,r7}\t\t\t\t\t/* Write first set of RBAR/RLAR registers. */\n\t\tmovs r5, #5\t\t\t\t\t\t\t/* r5 = 5. */\n\t\tstr  r5, [r4]\t\t\t\t\t\t/* Program RNR = 5. */\n\t\tldmia r1!, {r6,r7}\t\t\t\t\t/* Read second set of RBAR/RLAR from TCB. */\n\t\tldr  r3, =0xe000ed9c\t\t\t\t/* r3 = 0xe000ed9c [Location of RBAR]. */\n\t\tstmia r3!, {r6,r7}\t\t\t\t\t/* Write second set of RBAR/RLAR registers. */\n\t\tmovs r5, #6\t\t\t\t\t\t\t/* r5 = 6. */\n\t\tstr  r5, [r4]\t\t\t\t\t\t/* Program RNR = 6. */\n\t\tldmia r1!, {r6,r7}\t\t\t\t\t/* Read third set of RBAR/RLAR from TCB. */\n\t\tldr  r3, =0xe000ed9c\t\t\t\t/* r3 = 0xe000ed9c [Location of RBAR]. */\n\t\tstmia r3!, {r6,r7}\t\t\t\t\t/* Write third set of RBAR/RLAR registers. */\n\t\tmovs r5, #7\t\t\t\t\t\t\t/* r5 = 7. */\n\t\tstr  r5, [r4]\t\t\t\t\t\t/* Program RNR = 7. */\n\t\tldmia r1!, {r6,r7}\t\t\t\t\t/* Read fourth set of RBAR/RLAR from TCB. */\n\t\tldr  r3, =0xe000ed9c\t\t\t\t/* r3 = 0xe000ed9c [Location of RBAR]. */\n\t\tstmia r3!, {r6,r7}\t\t\t\t\t/* Write fourth set of RBAR/RLAR registers. */\n\n\t\tldr r3, =0xe000ed94\t\t\t\t\t/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */\n\t\tldr r4, [r3]\t\t\t\t\t\t/* Read the value of MPU_CTRL. */\n\t\tmovs r5, #1\t\t\t\t\t\t\t/* r5 = 1. */\n\t\torrs r4, r5\t\t\t\t\t\t\t/* r4 = r4 | r5 i.e. Set the bit 0 in r4. */\n\t\tstr r4, [r3]\t\t\t\t\t\t/* Enable MPU. */\n\t\tdsb\t\t\t\t\t\t\t\t\t/* Force memory writes before continuing. */\n\t#endif /* configENABLE_MPU */\n\n\t#if ( configENABLE_MPU == 1 )\n\t\tldmia r2!, {r0, r1, r3, r4}\t\t\t/* Read from stack - r0 = xSecureContext, r1 = PSPLIM, r3 = CONTROL and r4 = LR. */\n\t\tmsr psplim, r1\t\t\t\t\t\t/* Restore the PSPLIM register value for the task. */\n\t\tmsr control, r3\t\t\t\t\t\t/* Restore the CONTROL register value for the task. */\n\t\tmov lr, r4\t\t\t\t\t\t\t/* LR = r4. */\n\t\tldr r3, =xSecureContext\t\t\t\t/* Read the location of xSecureContext i.e. &( xSecureContext ). */\n\t\tstr r0, [r3]\t\t\t\t\t\t/* Restore the task's xSecureContext. */\n\t\tcbz r0, restore_ns_context\t\t\t/* If there is no secure context for the task, restore the non-secure context. */\n\t\tldr r3, =pxCurrentTCB\t\t\t\t/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n\t\tldr r1, [r3]\t\t\t\t\t\t/* Read pxCurrentTCB. */\n\t\tpush {r2, r4}\n\t\tbl SecureContext_LoadContext\t\t/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */\n\t\tpop {r2, r4}\n\t\tmov lr, r4\t\t\t\t\t\t\t/* LR = r4. */\n\t\tlsls r1, r4, #25\t\t\t\t\t/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\n\t\tbpl restore_ns_context\t\t\t\t/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\n\t\tmsr psp, r2\t\t\t\t\t\t\t/* Remember the new top of stack for the task. */\n\t\tbx lr\n\t#else /* configENABLE_MPU */\n\t\tldmia r2!, {r0, r1, r4}\t\t\t\t/* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */\n\t\tmsr psplim, r1\t\t\t\t\t\t/* Restore the PSPLIM register value for the task. */\n\t\tmov lr, r4\t\t\t\t\t\t\t/* LR = r4. */\n\t\tldr r3, =xSecureContext\t\t\t\t/* Read the location of xSecureContext i.e. &( xSecureContext ). */\n\t\tstr r0, [r3]\t\t\t\t\t\t/* Restore the task's xSecureContext. */\n\t\tcbz r0, restore_ns_context\t\t\t/* If there is no secure context for the task, restore the non-secure context. */\n\t\tldr r3, =pxCurrentTCB\t\t\t\t/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n\t\tldr r1, [r3]\t\t\t\t\t\t/* Read pxCurrentTCB. */\n\t\tpush {r2, r4}\n\t\tbl SecureContext_LoadContext\t\t/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */\n\t\tpop {r2, r4}\n\t\tmov lr, r4\t\t\t\t\t\t\t/* LR = r4. */\n\t\tlsls r1, r4, #25\t\t\t\t\t/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\n\t\tbpl restore_ns_context\t\t\t\t/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\n\t\tmsr psp, r2\t\t\t\t\t\t\t/* Remember the new top of stack for the task. */\n\t\tbx lr\n\t#endif /* configENABLE_MPU */\n\n\trestore_ns_context:\n\t\tadds r2, r2, #16\t\t\t\t\t/* Move to the high registers. */\n\t\tldmia r2!, {r4-r7}\t\t\t\t\t/* Restore the high registers that are not automatically restored. */\n\t\tmov r8, r4\t\t\t\t\t\t\t/* r8 = r4. */\n\t\tmov r9, r5\t\t\t\t\t\t\t/* r9 = r5. */\n\t\tmov r10, r6\t\t\t\t\t\t\t/* r10 = r6. */\n\t\tmov r11, r7\t\t\t\t\t\t\t/* r11 = r7. */\n\t\tmsr psp, r2\t\t\t\t\t\t\t/* Remember the new top of stack for the task. */\n\t\tsubs r2, r2, #32\t\t\t\t\t/* Go back to the low registers. */\n\t\tldmia r2!, {r4-r7}\t\t\t\t\t/* Restore the low registers that are not automatically restored. */\n\t\tbx lr\n/*-----------------------------------------------------------*/\n\nSVC_Handler:\n\tmovs r0, #4\n\tmov r1, lr\n\ttst r0, r1\n\tbeq stacking_used_msp\n\tmrs r0, psp\n\tb vPortSVCHandler_C\n\tstacking_used_msp:\n\t\tmrs r0, msp\n\t\tb vPortSVCHandler_C\n/*-----------------------------------------------------------*/\n\nvPortFreeSecureContext:\n\tldr r2, [r0]\t\t\t\t\t\t\t/* The first item in the TCB is the top of the stack. */\n\tldr r1, [r2]\t\t\t\t\t\t\t/* The first item on the stack is the task's xSecureContext. */\n\tcmp r1, #0\t\t\t\t\t\t\t\t/* Raise svc if task's xSecureContext is not NULL. */\n\tbne free_secure_context\t\t\t\t\t/* Branch if r1 != 0. */\n\tbx lr\t\t\t\t\t\t\t\t\t/* There is no secure context (xSecureContext is NULL). */\n\tfree_secure_context:\n\t\tsvc 1\t\t\t\t\t\t\t\t/* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */\n\t\tbx lr\t\t\t\t\t\t\t\t/* Return. */\n/*-----------------------------------------------------------*/\n\n\tEND\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM23/non_secure/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef PORTMACRO_H\n#define PORTMACRO_H\n\n#ifdef __cplusplus\n    extern \"C\" {\n#endif\n\n#include \"portmacrocommon.h\"\n\n/*------------------------------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the given hardware\n * and compiler.\n *\n * These settings should not be altered.\n *------------------------------------------------------------------------------\n */\n\n/**\n * Architecture specifics.\n */\n#define portARCH_NAME                       \"Cortex-M23\"\n#define portDONT_DISCARD                    __root\n/*-----------------------------------------------------------*/\n\n#if( configTOTAL_MPU_REGIONS == 16 )\n    #error 16 MPU regions are not yet supported for this port.\n#endif\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Critical section management.\n */\n#define portDISABLE_INTERRUPTS()            __asm volatile ( \" cpsid i \" ::: \"memory\" )\n#define portENABLE_INTERRUPTS()             __asm volatile ( \" cpsie i \" ::: \"memory\" )\n/*-----------------------------------------------------------*/\n\n/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in\n * the source code because to do so would cause other compilers to generate\n * warnings. */\n#pragma diag_suppress=Be006\n#pragma diag_suppress=Pa082\n/*-----------------------------------------------------------*/\n\n#ifdef __cplusplus\n    }\n#endif\n\n#endif /* PORTMACRO_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef PORTMACROCOMMON_H\n    #define PORTMACROCOMMON_H\n\n    #ifdef __cplusplus\n        extern \"C\" {\n    #endif\n\n/*------------------------------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the given hardware\n * and compiler.\n *\n * These settings should not be altered.\n *------------------------------------------------------------------------------\n */\n\n    #ifndef configENABLE_FPU\n        #error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.\n    #endif /* configENABLE_FPU */\n\n    #ifndef configENABLE_MPU\n        #error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.\n    #endif /* configENABLE_MPU */\n\n    #ifndef configENABLE_TRUSTZONE\n        #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.\n    #endif /* configENABLE_TRUSTZONE */\n\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Type definitions.\n */\n    #define portCHAR          char\n    #define portFLOAT         float\n    #define portDOUBLE        double\n    #define portLONG          long\n    #define portSHORT         short\n    #define portSTACK_TYPE    uint32_t\n    #define portBASE_TYPE     long\n\n    typedef portSTACK_TYPE   StackType_t;\n    typedef long             BaseType_t;\n    typedef unsigned long    UBaseType_t;\n\n    #if ( configUSE_16_BIT_TICKS == 1 )\n        typedef uint16_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffff\n    #else\n        typedef uint32_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL\n\n/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\n * not need to be guarded with a critical section. */\n        #define portTICK_TYPE_IS_ATOMIC    1\n    #endif\n/*-----------------------------------------------------------*/\n\n/**\n * Architecture specifics.\n */\n    #define portSTACK_GROWTH                   ( -1 )\n    #define portTICK_PERIOD_MS                 ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\n    #define portBYTE_ALIGNMENT                 8\n    #define portNOP()\n    #define portINLINE                         __inline\n    #ifndef portFORCE_INLINE\n        #define portFORCE_INLINE               inline __attribute__( ( always_inline ) )\n    #endif\n    #define portHAS_STACK_OVERFLOW_CHECKING    1\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Extern declarations.\n */\n    extern BaseType_t xPortIsInsideInterrupt( void );\n\n    extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;\n\n    extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;\n    extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;\n\n    extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\n    extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\n\n    #if ( configENABLE_TRUSTZONE == 1 )\n        extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */\n        extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;\n    #endif /* configENABLE_TRUSTZONE */\n\n    #if ( configENABLE_MPU == 1 )\n        extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;\n        extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;\n    #endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\n/**\n * @brief MPU specific constants.\n */\n    #if ( configENABLE_MPU == 1 )\n        #define portUSING_MPU_WRAPPERS    1\n        #define portPRIVILEGE_BIT         ( 0x80000000UL )\n    #else\n        #define portPRIVILEGE_BIT         ( 0x0UL )\n    #endif /* configENABLE_MPU */\n\n/* MPU settings that can be overriden in FreeRTOSConfig.h. */\n#ifndef configTOTAL_MPU_REGIONS\n    /* Define to 8 for backward compatibility. */\n    #define configTOTAL_MPU_REGIONS       ( 8UL )\n#endif\n\n/* MPU regions. */\n    #define portPRIVILEGED_FLASH_REGION                   ( 0UL )\n    #define portUNPRIVILEGED_FLASH_REGION                 ( 1UL )\n    #define portUNPRIVILEGED_SYSCALLS_REGION              ( 2UL )\n    #define portPRIVILEGED_RAM_REGION                     ( 3UL )\n    #define portSTACK_REGION                              ( 4UL )\n    #define portFIRST_CONFIGURABLE_REGION                 ( 5UL )\n    #define portLAST_CONFIGURABLE_REGION                  ( configTOTAL_MPU_REGIONS - 1UL )\n    #define portNUM_CONFIGURABLE_REGIONS                  ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )\n    #define portTOTAL_NUM_REGIONS                         ( portNUM_CONFIGURABLE_REGIONS + 1 )   /* Plus one to make space for the stack region. */\n\n/* Device memory attributes used in MPU_MAIR registers.\n *\n * 8-bit values encoded as follows:\n *  Bit[7:4] - 0000 - Device Memory\n *  Bit[3:2] - 00 --> Device-nGnRnE\n *\t\t\t\t01 --> Device-nGnRE\n *\t\t\t\t10 --> Device-nGRE\n *\t\t\t\t11 --> Device-GRE\n *  Bit[1:0] - 00, Reserved.\n */\n    #define portMPU_DEVICE_MEMORY_nGnRnE                  ( 0x00 )   /* 0000 0000 */\n    #define portMPU_DEVICE_MEMORY_nGnRE                   ( 0x04 )   /* 0000 0100 */\n    #define portMPU_DEVICE_MEMORY_nGRE                    ( 0x08 )   /* 0000 1000 */\n    #define portMPU_DEVICE_MEMORY_GRE                     ( 0x0C )   /* 0000 1100 */\n\n/* Normal memory attributes used in MPU_MAIR registers. */\n    #define portMPU_NORMAL_MEMORY_NON_CACHEABLE           ( 0x44 )   /* Non-cacheable. */\n    #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE    ( 0xFF )   /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */\n\n/* Attributes used in MPU_RBAR registers. */\n    #define portMPU_REGION_NON_SHAREABLE                  ( 0UL << 3UL )\n    #define portMPU_REGION_INNER_SHAREABLE                ( 1UL << 3UL )\n    #define portMPU_REGION_OUTER_SHAREABLE                ( 2UL << 3UL )\n\n    #define portMPU_REGION_PRIVILEGED_READ_WRITE          ( 0UL << 1UL )\n    #define portMPU_REGION_READ_WRITE                     ( 1UL << 1UL )\n    #define portMPU_REGION_PRIVILEGED_READ_ONLY           ( 2UL << 1UL )\n    #define portMPU_REGION_READ_ONLY                      ( 3UL << 1UL )\n\n    #define portMPU_REGION_EXECUTE_NEVER                  ( 1UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Settings to define an MPU region.\n */\n    typedef struct MPURegionSettings\n    {\n        uint32_t ulRBAR; /**< RBAR for the region. */\n        uint32_t ulRLAR; /**< RLAR for the region. */\n    } MPURegionSettings_t;\n\n/**\n * @brief MPU settings as stored in the TCB.\n */\n    typedef struct MPU_SETTINGS\n    {\n        uint32_t ulMAIR0;                                              /**< MAIR0 for the task containing attributes for all the 4 per task regions. */\n        MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */\n    } xMPU_SETTINGS;\n/*-----------------------------------------------------------*/\n\n/**\n * @brief SVC numbers.\n */\n    #define portSVC_ALLOCATE_SECURE_CONTEXT    0\n    #define portSVC_FREE_SECURE_CONTEXT        1\n    #define portSVC_START_SCHEDULER            2\n    #define portSVC_RAISE_PRIVILEGE            3\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Scheduler utilities.\n */\n    #define portYIELD()                                 vPortYield()\n    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )\n    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )\n    #define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )\n    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Critical section management.\n */\n    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulSetInterruptMask()\n    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vClearInterruptMask( x )\n    #define portENTER_CRITICAL()                      vPortEnterCritical()\n    #define portEXIT_CRITICAL()                       vPortExitCritical()\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Tickless idle/low power functionality.\n */\n    #ifndef portSUPPRESS_TICKS_AND_SLEEP\n        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );\n        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )\n    #endif\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Task function macros as described on the FreeRTOS.org WEB site.\n */\n    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )\n    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )\n/*-----------------------------------------------------------*/\n\n    #if ( configENABLE_TRUSTZONE == 1 )\n\n/**\n * @brief Allocate a secure context for the task.\n *\n * Tasks are not created with a secure context. Any task that is going to call\n * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a\n * secure context before it calls any secure function.\n *\n * @param[in] ulSecureStackSize The size of the secure stack to be allocated.\n */\n        #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )\n\n/**\n * @brief Called when a task is deleted to delete the task's secure context,\n * if it has one.\n *\n * @param[in] pxTCB The TCB of the task being deleted.\n */\n        #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )\n    #endif /* configENABLE_TRUSTZONE */\n/*-----------------------------------------------------------*/\n\n    #if ( configENABLE_MPU == 1 )\n\n/**\n * @brief Checks whether or not the processor is privileged.\n *\n * @return 1 if the processor is already privileged, 0 otherwise.\n */\n        #define portIS_PRIVILEGED()      xIsPrivileged()\n\n/**\n * @brief Raise an SVC request to raise privilege.\n *\n * The SVC handler checks that the SVC was raised from a system call and only\n * then it raises the privilege. If this is called from any other place,\n * the privilege is not raised.\n */\n        #define portRAISE_PRIVILEGE()    __asm volatile ( \"svc %0 \\n\" ::\"i\" ( portSVC_RAISE_PRIVILEGE ) : \"memory\" );\n\n/**\n * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\n * register.\n */\n        #define portRESET_PRIVILEGE()    vResetPrivilege()\n    #else\n        #define portIS_PRIVILEGED()\n        #define portRAISE_PRIVILEGE()\n        #define portRESET_PRIVILEGE()\n    #endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Barriers.\n */\n    #define portMEMORY_BARRIER()    __asm volatile ( \"\" ::: \"memory\" )\n/*-----------------------------------------------------------*/\n\n    #ifdef __cplusplus\n        }\n    #endif\n\n#endif /* PORTMACROCOMMON_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM23/secure/secure_context.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Secure context includes. */\n#include \"secure_context.h\"\n\n/* Secure heap includes. */\n#include \"secure_heap.h\"\n\n/* Secure port macros. */\n#include \"secure_port_macros.h\"\n\n/**\n * @brief CONTROL value for privileged tasks.\n *\n * Bit[0] - 0 --> Thread mode is privileged.\n * Bit[1] - 1 --> Thread mode uses PSP.\n */\n#define securecontextCONTROL_VALUE_PRIVILEGED      0x02\n\n/**\n * @brief CONTROL value for un-privileged tasks.\n *\n * Bit[0] - 1 --> Thread mode is un-privileged.\n * Bit[1] - 1 --> Thread mode uses PSP.\n */\n#define securecontextCONTROL_VALUE_UNPRIVILEGED    0x03\n\n/**\n * @brief Size of stack seal values in bytes.\n */\n#define securecontextSTACK_SEAL_SIZE               8\n\n/**\n * @brief Stack seal value as recommended by ARM.\n */\n#define securecontextSTACK_SEAL_VALUE              0xFEF5EDA5\n\n/**\n * @brief Maximum number of secure contexts.\n */\n#ifndef secureconfigMAX_SECURE_CONTEXTS\n    #define secureconfigMAX_SECURE_CONTEXTS        8UL\n#endif\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Pre-allocated array of secure contexts.\n */\nSecureContext_t xSecureContexts[ secureconfigMAX_SECURE_CONTEXTS ];\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Get a free secure context for a task from the secure context pool (xSecureContexts).\n *\n * This function ensures that only one secure context is allocated for a task.\n *\n * @param[in] pvTaskHandle The task handle for which the secure context is allocated.\n *\n * @return Index of a free secure context in the xSecureContexts array.\n */\nstatic uint32_t ulGetSecureContext( void * pvTaskHandle );\n\n/**\n * @brief Return the secure context to the secure context pool (xSecureContexts).\n *\n * @param[in] ulSecureContextIndex Index of the context in the xSecureContexts array.\n */\nstatic void vReturnSecureContext( uint32_t ulSecureContextIndex );\n\n/* These are implemented in assembly. */\nextern void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext );\nextern void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext );\n/*-----------------------------------------------------------*/\n\nstatic uint32_t ulGetSecureContext( void * pvTaskHandle )\n{\n    /* Start with invalid index. */\n    uint32_t i, ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS;\n\n    for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ )\n    {\n        if( ( xSecureContexts[ i ].pucCurrentStackPointer == NULL ) &&\n            ( xSecureContexts[ i ].pucStackLimit == NULL ) &&\n            ( xSecureContexts[ i ].pucStackStart == NULL ) &&\n            ( xSecureContexts[ i ].pvTaskHandle == NULL ) &&\n            ( ulSecureContextIndex == secureconfigMAX_SECURE_CONTEXTS ) )\n        {\n            ulSecureContextIndex = i;\n        }\n        else if( xSecureContexts[ i ].pvTaskHandle == pvTaskHandle )\n        {\n            /* A task can only have one secure context. Do not allocate a second\n             * context for the same task. */\n            ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS;\n            break;\n        }\n    }\n\n    return ulSecureContextIndex;\n}\n/*-----------------------------------------------------------*/\n\nstatic void vReturnSecureContext( uint32_t ulSecureContextIndex )\n{\n    xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = NULL;\n    xSecureContexts[ ulSecureContextIndex ].pucStackLimit = NULL;\n    xSecureContexts[ ulSecureContextIndex ].pucStackStart = NULL;\n    xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = NULL;\n}\n/*-----------------------------------------------------------*/\n\nsecureportNON_SECURE_CALLABLE void SecureContext_Init( void )\n{\n    uint32_t ulIPSR, i;\n    static uint32_t ulSecureContextsInitialized = 0;\n\n    /* Read the Interrupt Program Status Register (IPSR) value. */\n    secureportREAD_IPSR( ulIPSR );\n\n    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\n     * when the processor is running in the Thread Mode. */\n    if( ( ulIPSR != 0 ) && ( ulSecureContextsInitialized == 0 ) )\n    {\n        /* Ensure to initialize secure contexts only once. */\n        ulSecureContextsInitialized = 1;\n\n        /* No stack for thread mode until a task's context is loaded. */\n        secureportSET_PSPLIM( securecontextNO_STACK );\n        secureportSET_PSP( securecontextNO_STACK );\n\n        /* Initialize all secure contexts. */\n        for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ )\n        {\n            xSecureContexts[ i ].pucCurrentStackPointer = NULL;\n            xSecureContexts[ i ].pucStackLimit = NULL;\n            xSecureContexts[ i ].pucStackStart = NULL;\n            xSecureContexts[ i ].pvTaskHandle = NULL;\n        }\n\n        #if ( configENABLE_MPU == 1 )\n            {\n                /* Configure thread mode to use PSP and to be unprivileged. */\n                secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );\n            }\n        #else /* configENABLE_MPU */\n            {\n                /* Configure thread mode to use PSP and to be privileged. */\n                secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );\n            }\n        #endif /* configENABLE_MPU */\n    }\n}\n/*-----------------------------------------------------------*/\n\n#if ( configENABLE_MPU == 1 )\n    secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,\n                                                                                       uint32_t ulIsTaskPrivileged,\n                                                                                       void * pvTaskHandle )\n#else /* configENABLE_MPU */\n    secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,\n                                                                                       void * pvTaskHandle )\n#endif /* configENABLE_MPU */\n{\n    uint8_t * pucStackMemory = NULL;\n    uint8_t * pucStackLimit;\n    uint32_t ulIPSR, ulSecureContextIndex;\n    SecureContextHandle_t xSecureContextHandle = securecontextINVALID_CONTEXT_ID;\n\n    #if ( configENABLE_MPU == 1 )\n        uint32_t * pulCurrentStackPointer = NULL;\n    #endif /* configENABLE_MPU */\n\n    /* Read the Interrupt Program Status Register (IPSR) and Process Stack Limit\n     * Register (PSPLIM) value. */\n    secureportREAD_IPSR( ulIPSR );\n    secureportREAD_PSPLIM( pucStackLimit );\n\n    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\n     * when the processor is running in the Thread Mode.\n     * Also do nothing, if a secure context us already loaded. PSPLIM is set to\n     * securecontextNO_STACK when no secure context is loaded. */\n    if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) )\n    {\n        /* Ontain a free secure context. */\n        ulSecureContextIndex = ulGetSecureContext( pvTaskHandle );\n\n        /* Were we able to get a free context? */\n        if( ulSecureContextIndex < secureconfigMAX_SECURE_CONTEXTS )\n        {\n            /* Allocate the stack space. */\n            pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE );\n\n            if( pucStackMemory != NULL )\n            {\n                /* Since stack grows down, the starting point will be the last\n                 * location. Note that this location is next to the last\n                 * allocated byte for stack (excluding the space for seal values)\n                 * because the hardware decrements the stack pointer before\n                 * writing i.e. if stack pointer is 0x2, a push operation will\n                 * decrement the stack pointer to 0x1 and then write at 0x1. */\n                xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize;\n\n                /* Seal the created secure process stack. */\n                *( uint32_t * )( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE;\n                *( uint32_t * )( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE;\n\n                /* The stack cannot go beyond this location. This value is\n                 * programmed in the PSPLIM register on context switch.*/\n                xSecureContexts[ ulSecureContextIndex ].pucStackLimit = pucStackMemory;\n\n                xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle;\n\n                #if ( configENABLE_MPU == 1 )\n                    {\n                        /* Store the correct CONTROL value for the task on the stack.\n                         * This value is programmed in the CONTROL register on\n                         * context switch. */\n                        pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart;\n                        pulCurrentStackPointer--;\n\n                        if( ulIsTaskPrivileged )\n                        {\n                            *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;\n                        }\n                        else\n                        {\n                            *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;\n                        }\n\n                        /* Store the current stack pointer. This value is programmed in\n                         * the PSP register on context switch. */\n                        xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;\n                    }\n                #else /* configENABLE_MPU */\n                    {\n                        /* Current SP is set to the starting of the stack. This\n                         * value programmed in the PSP register on context switch. */\n                        xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart;\n                    }\n                #endif /* configENABLE_MPU */\n\n                /* Ensure to never return 0 as a valid context handle. */\n                xSecureContextHandle = ulSecureContextIndex + 1UL;\n            }\n        }\n    }\n\n    return xSecureContextHandle;\n}\n/*-----------------------------------------------------------*/\n\nsecureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )\n{\n    uint32_t ulIPSR, ulSecureContextIndex;\n\n    /* Read the Interrupt Program Status Register (IPSR) value. */\n    secureportREAD_IPSR( ulIPSR );\n\n    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\n     * when the processor is running in the Thread Mode. */\n    if( ulIPSR != 0 )\n    {\n        /* Only free if a valid context handle is passed. */\n        if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) )\n        {\n            ulSecureContextIndex = xSecureContextHandle - 1UL;\n\n            /* Ensure that the secure context being deleted is associated with\n             * the task. */\n            if( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle )\n            {\n                /* Free the stack space. */\n                vPortFree( xSecureContexts[ ulSecureContextIndex ].pucStackLimit );\n\n                /* Return the secure context back to the free secure contexts pool. */\n                vReturnSecureContext( ulSecureContextIndex );\n            }\n        }\n    }\n}\n/*-----------------------------------------------------------*/\n\nsecureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )\n{\n    uint8_t * pucStackLimit;\n    uint32_t ulSecureContextIndex;\n\n    if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) )\n    {\n        ulSecureContextIndex = xSecureContextHandle - 1UL;\n\n        secureportREAD_PSPLIM( pucStackLimit );\n\n        /* Ensure that no secure context is loaded and the task is loading it's\n         * own context. */\n        if( ( pucStackLimit == securecontextNO_STACK ) &&\n            ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) )\n        {\n            SecureContext_LoadContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) );\n        }\n    }\n}\n/*-----------------------------------------------------------*/\n\nsecureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )\n{\n    uint8_t * pucStackLimit;\n    uint32_t ulSecureContextIndex;\n\n    if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) )\n    {\n        ulSecureContextIndex = xSecureContextHandle - 1UL;\n\n        secureportREAD_PSPLIM( pucStackLimit );\n\n        /* Ensure that task's context is loaded and the task is saving it's own\n         * context. */\n        if( ( xSecureContexts[ ulSecureContextIndex ].pucStackLimit == pucStackLimit ) &&\n            ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) )\n        {\n            SecureContext_SaveContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) );\n        }\n    }\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM23/secure/secure_context.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef __SECURE_CONTEXT_H__\n#define __SECURE_CONTEXT_H__\n\n/* Standard includes. */\n#include <stdint.h>\n\n/* FreeRTOS includes. */\n#include \"FreeRTOSConfig.h\"\n\n/**\n * @brief PSP value when no secure context is loaded.\n */\n#define securecontextNO_STACK               0x0\n\n/**\n * @brief Invalid context ID.\n */\n#define securecontextINVALID_CONTEXT_ID     0UL\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Structure to represent a secure context.\n *\n * @note Since stack grows down, pucStackStart is the highest address while\n * pucStackLimit is the first address of the allocated memory.\n */\ntypedef struct SecureContext\n{\n    uint8_t * pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */\n    uint8_t * pucStackLimit;          /**< Last location of the stack memory (PSPLIM). */\n    uint8_t * pucStackStart;          /**< First location of the stack memory. */\n    void * pvTaskHandle;              /**< Task handle of the task this context is associated with. */\n} SecureContext_t;\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Opaque handle for a secure context.\n */\ntypedef uint32_t SecureContextHandle_t;\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Initializes the secure context management system.\n *\n * PSP is set to NULL and therefore a task must allocate and load a context\n * before calling any secure side function in the thread mode.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n */\nvoid SecureContext_Init( void );\n\n/**\n * @brief Allocates a context on the secure side.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n *\n * @param[in] ulSecureStackSize Size of the stack to allocate on secure side.\n * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise.\n *\n * @return Opaque context handle if context is successfully allocated, NULL\n * otherwise.\n */\n#if ( configENABLE_MPU == 1 )\n    SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,\n                                                         uint32_t ulIsTaskPrivileged,\n                                                         void * pvTaskHandle );\n#else /* configENABLE_MPU */\n    SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,\n                                                         void * pvTaskHandle );\n#endif /* configENABLE_MPU */\n\n/**\n * @brief Frees the given context.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n *\n * @param[in] xSecureContextHandle Context handle corresponding to the\n * context to be freed.\n */\nvoid SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );\n\n/**\n * @brief Loads the given context.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n *\n * @param[in] xSecureContextHandle Context handle corresponding to the context\n * to be loaded.\n */\nvoid SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );\n\n/**\n * @brief Saves the given context.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n *\n * @param[in] xSecureContextHandle Context handle corresponding to the context\n * to be saved.\n */\nvoid SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );\n\n#endif /* __SECURE_CONTEXT_H__ */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM23/secure/secure_context_port_asm.s",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n    SECTION .text:CODE:NOROOT(2)\n    THUMB\n\n/* Including FreeRTOSConfig.h here will cause build errors if the header file\ncontains code not understood by the assembler - for example the 'extern' keyword.\nTo avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so\nthe code is included in C files but excluded by the preprocessor in assembly\nfiles (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */\n#include \"FreeRTOSConfig.h\"\n\n    PUBLIC SecureContext_LoadContextAsm\n    PUBLIC SecureContext_SaveContextAsm\n\n#if ( configENABLE_FPU == 1 )\n    #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.\n#endif\n/*-----------------------------------------------------------*/\n\nSecureContext_LoadContextAsm:\n    /* pxSecureContext value is in r0. */\n    mrs r1, ipsr                    /* r1 = IPSR. */\n    cbz r1, load_ctx_therad_mode    /* Do nothing if the processor is running in the Thread Mode. */\n    ldmia r0!, {r1, r2}             /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */\n\n#if ( configENABLE_MPU == 1 )\n    ldmia r1!, {r3}                 /* Read CONTROL register value from task's stack. r3 = CONTROL. */\n    msr control, r3                 /* CONTROL = r3. */\n#endif /* configENABLE_MPU */\n\n    msr psplim, r2                  /* PSPLIM = r2. */\n    msr psp, r1                     /* PSP = r1. */\n\n    load_ctx_therad_mode:\n        bx lr\n/*-----------------------------------------------------------*/\n\nSecureContext_SaveContextAsm:\n    /* pxSecureContext value is in r0. */\n    mrs r1, ipsr                    /* r1 = IPSR. */\n    cbz r1, save_ctx_therad_mode    /* Do nothing if the processor is running in the Thread Mode. */\n    mrs r1, psp                     /* r1 = PSP. */\n\n#if ( configENABLE_MPU == 1 )\n    mrs r2, control                 /* r2 = CONTROL. */\n    subs r1, r1, #4                 /* Make space for the CONTROL value on the stack. */\n    str r1, [r0]                    /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */\n    stmia r1!, {r2}                 /* Store CONTROL value on the stack. */\n#else /* configENABLE_MPU */\n    str r1, [r0]                    /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */\n#endif /* configENABLE_MPU */\n\n    movs r1, #0                     /* r1 = securecontextNO_STACK. */\n    msr psplim, r1                  /* PSPLIM = securecontextNO_STACK. */\n    msr psp, r1                     /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */\n\n    save_ctx_therad_mode:\n        bx lr\n/*-----------------------------------------------------------*/\n\n    END\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM23/secure/secure_heap.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Standard includes. */\n#include <stdint.h>\n\n/* Secure context heap includes. */\n#include \"secure_heap.h\"\n\n/* Secure port macros. */\n#include \"secure_port_macros.h\"\n\n/**\n * @brief Total heap size.\n */\n#ifndef secureconfigTOTAL_HEAP_SIZE\n    #define secureconfigTOTAL_HEAP_SIZE    ( ( ( size_t ) ( 10 * 1024 ) ) )\n#endif\n\n/* No test marker by default. */\n#ifndef mtCOVERAGE_TEST_MARKER\n    #define mtCOVERAGE_TEST_MARKER()\n#endif\n\n/* No tracing by default. */\n#ifndef traceMALLOC\n    #define traceMALLOC( pvReturn, xWantedSize )\n#endif\n\n/* No tracing by default. */\n#ifndef traceFREE\n    #define traceFREE( pv, xBlockSize )\n#endif\n\n/* Block sizes must not get too small. */\n#define secureheapMINIMUM_BLOCK_SIZE    ( ( size_t ) ( xHeapStructSize << 1 ) )\n\n/* Assumes 8bit bytes! */\n#define secureheapBITS_PER_BYTE         ( ( size_t ) 8 )\n/*-----------------------------------------------------------*/\n\n/* Allocate the memory for the heap. */\n#if ( configAPPLICATION_ALLOCATED_HEAP == 1 )\n\n/* The application writer has already defined the array used for the RTOS\n* heap - probably so it can be placed in a special segment or address. */\n    extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];\n#else /* configAPPLICATION_ALLOCATED_HEAP */\n    static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];\n#endif /* configAPPLICATION_ALLOCATED_HEAP */\n\n/**\n * @brief The linked list structure.\n *\n * This is used to link free blocks in order of their memory address.\n */\ntypedef struct A_BLOCK_LINK\n{\n    struct A_BLOCK_LINK * pxNextFreeBlock; /**< The next free block in the list. */\n    size_t xBlockSize;                     /**< The size of the free block. */\n} BlockLink_t;\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Called automatically to setup the required heap structures the first\n * time pvPortMalloc() is called.\n */\nstatic void prvHeapInit( void );\n\n/**\n * @brief Inserts a block of memory that is being freed into the correct\n * position in the list of free memory blocks.\n *\n * The block being freed will be merged with the block in front it and/or the\n * block behind it if the memory blocks are adjacent to each other.\n *\n * @param[in] pxBlockToInsert The block being freed.\n */\nstatic void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert );\n/*-----------------------------------------------------------*/\n\n/**\n * @brief The size of the structure placed at the beginning of each allocated\n * memory block must by correctly byte aligned.\n */\nstatic const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );\n\n/**\n * @brief Create a couple of list links to mark the start and end of the list.\n */\nstatic BlockLink_t xStart;\nstatic BlockLink_t * pxEnd = NULL;\n\n/**\n * @brief Keeps track of the number of free bytes remaining, but says nothing\n * about fragmentation.\n */\nstatic size_t xFreeBytesRemaining = 0U;\nstatic size_t xMinimumEverFreeBytesRemaining = 0U;\n\n/**\n * @brief Gets set to the top bit of an size_t type.\n *\n * When this bit in the xBlockSize member of an BlockLink_t structure is set\n * then the block belongs to the application. When the bit is free the block is\n * still part of the free heap space.\n */\nstatic size_t xBlockAllocatedBit = 0;\n/*-----------------------------------------------------------*/\n\nstatic void prvHeapInit( void )\n{\n    BlockLink_t * pxFirstFreeBlock;\n    uint8_t * pucAlignedHeap;\n    size_t uxAddress;\n    size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE;\n\n    /* Ensure the heap starts on a correctly aligned boundary. */\n    uxAddress = ( size_t ) ucHeap;\n\n    if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 )\n    {\n        uxAddress += ( secureportBYTE_ALIGNMENT - 1 );\n        uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );\n        xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;\n    }\n\n    pucAlignedHeap = ( uint8_t * ) uxAddress;\n\n    /* xStart is used to hold a pointer to the first item in the list of free\n     * blocks.  The void cast is used to prevent compiler warnings. */\n    xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;\n    xStart.xBlockSize = ( size_t ) 0;\n\n    /* pxEnd is used to mark the end of the list of free blocks and is inserted\n     * at the end of the heap space. */\n    uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;\n    uxAddress -= xHeapStructSize;\n    uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );\n    pxEnd = ( void * ) uxAddress;\n    pxEnd->xBlockSize = 0;\n    pxEnd->pxNextFreeBlock = NULL;\n\n    /* To start with there is a single free block that is sized to take up the\n     * entire heap space, minus the space taken by pxEnd. */\n    pxFirstFreeBlock = ( void * ) pucAlignedHeap;\n    pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;\n    pxFirstFreeBlock->pxNextFreeBlock = pxEnd;\n\n    /* Only one block exists - and it covers the entire usable heap space. */\n    xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;\n    xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;\n\n    /* Work out the position of the top bit in a size_t variable. */\n    xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert )\n{\n    BlockLink_t * pxIterator;\n    uint8_t * puc;\n\n    /* Iterate through the list until a block is found that has a higher address\n     * than the block being inserted. */\n    for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )\n    {\n        /* Nothing to do here, just iterate to the right position. */\n    }\n\n    /* Do the block being inserted, and the block it is being inserted after\n     * make a contiguous block of memory? */\n    puc = ( uint8_t * ) pxIterator;\n\n    if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )\n    {\n        pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;\n        pxBlockToInsert = pxIterator;\n    }\n    else\n    {\n        mtCOVERAGE_TEST_MARKER();\n    }\n\n    /* Do the block being inserted, and the block it is being inserted before\n     * make a contiguous block of memory? */\n    puc = ( uint8_t * ) pxBlockToInsert;\n\n    if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )\n    {\n        if( pxIterator->pxNextFreeBlock != pxEnd )\n        {\n            /* Form one big block from the two blocks. */\n            pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;\n            pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;\n        }\n        else\n        {\n            pxBlockToInsert->pxNextFreeBlock = pxEnd;\n        }\n    }\n    else\n    {\n        pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;\n    }\n\n    /* If the block being inserted plugged a gab, so was merged with the block\n     * before and the block after, then it's pxNextFreeBlock pointer will have\n     * already been set, and should not be set here as that would make it point\n     * to itself. */\n    if( pxIterator != pxBlockToInsert )\n    {\n        pxIterator->pxNextFreeBlock = pxBlockToInsert;\n    }\n    else\n    {\n        mtCOVERAGE_TEST_MARKER();\n    }\n}\n/*-----------------------------------------------------------*/\n\nvoid * pvPortMalloc( size_t xWantedSize )\n{\n    BlockLink_t * pxBlock;\n    BlockLink_t * pxPreviousBlock;\n    BlockLink_t * pxNewBlockLink;\n    void * pvReturn = NULL;\n\n    /* If this is the first call to malloc then the heap will require\n     * initialisation to setup the list of free blocks. */\n    if( pxEnd == NULL )\n    {\n        prvHeapInit();\n    }\n    else\n    {\n        mtCOVERAGE_TEST_MARKER();\n    }\n\n    /* Check the requested block size is not so large that the top bit is set.\n     * The top bit of the block size member of the BlockLink_t structure is used\n     * to determine who owns the block - the application or the kernel, so it\n     * must be free. */\n    if( ( xWantedSize & xBlockAllocatedBit ) == 0 )\n    {\n        /* The wanted size is increased so it can contain a BlockLink_t\n         * structure in addition to the requested amount of bytes. */\n        if( xWantedSize > 0 )\n        {\n            xWantedSize += xHeapStructSize;\n\n            /* Ensure that blocks are always aligned to the required number of\n             * bytes. */\n            if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )\n            {\n                /* Byte alignment required. */\n                xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );\n                secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n\n        if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )\n        {\n            /* Traverse the list from the start (lowest address) block until\n             * one of adequate size is found. */\n            pxPreviousBlock = &xStart;\n            pxBlock = xStart.pxNextFreeBlock;\n\n            while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )\n            {\n                pxPreviousBlock = pxBlock;\n                pxBlock = pxBlock->pxNextFreeBlock;\n            }\n\n            /* If the end marker was reached then a block of adequate size was\n             * not found. */\n            if( pxBlock != pxEnd )\n            {\n                /* Return the memory space pointed to - jumping over the\n                 * BlockLink_t structure at its start. */\n                pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );\n\n                /* This block is being returned for use so must be taken out\n                 * of the list of free blocks. */\n                pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;\n\n                /* If the block is larger than required it can be split into\n                 * two. */\n                if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE )\n                {\n                    /* This block is to be split into two.  Create a new\n                     * block following the number of bytes requested. The void\n                     * cast is used to prevent byte alignment warnings from the\n                     * compiler. */\n                    pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );\n                    secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 );\n\n                    /* Calculate the sizes of two blocks split from the single\n                     * block. */\n                    pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;\n                    pxBlock->xBlockSize = xWantedSize;\n\n                    /* Insert the new block into the list of free blocks. */\n                    prvInsertBlockIntoFreeList( pxNewBlockLink );\n                }\n                else\n                {\n                    mtCOVERAGE_TEST_MARKER();\n                }\n\n                xFreeBytesRemaining -= pxBlock->xBlockSize;\n\n                if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )\n                {\n                    xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;\n                }\n                else\n                {\n                    mtCOVERAGE_TEST_MARKER();\n                }\n\n                /* The block is being returned - it is allocated and owned by\n                 * the application and has no \"next\" block. */\n                pxBlock->xBlockSize |= xBlockAllocatedBit;\n                pxBlock->pxNextFreeBlock = NULL;\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n    }\n    else\n    {\n        mtCOVERAGE_TEST_MARKER();\n    }\n\n    traceMALLOC( pvReturn, xWantedSize );\n\n    #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )\n        {\n            if( pvReturn == NULL )\n            {\n                extern void vApplicationMallocFailedHook( void );\n                vApplicationMallocFailedHook();\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n    #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */\n\n    secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );\n    return pvReturn;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortFree( void * pv )\n{\n    uint8_t * puc = ( uint8_t * ) pv;\n    BlockLink_t * pxLink;\n\n    if( pv != NULL )\n    {\n        /* The memory being freed will have an BlockLink_t structure immediately\n         * before it. */\n        puc -= xHeapStructSize;\n\n        /* This casting is to keep the compiler from issuing warnings. */\n        pxLink = ( void * ) puc;\n\n        /* Check the block is actually allocated. */\n        secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );\n        secureportASSERT( pxLink->pxNextFreeBlock == NULL );\n\n        if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )\n        {\n            if( pxLink->pxNextFreeBlock == NULL )\n            {\n                /* The block is being returned to the heap - it is no longer\n                 * allocated. */\n                pxLink->xBlockSize &= ~xBlockAllocatedBit;\n\n                secureportDISABLE_NON_SECURE_INTERRUPTS();\n                {\n                    /* Add this block to the list of free blocks. */\n                    xFreeBytesRemaining += pxLink->xBlockSize;\n                    traceFREE( pv, pxLink->xBlockSize );\n                    prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );\n                }\n                secureportENABLE_NON_SECURE_INTERRUPTS();\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n    }\n}\n/*-----------------------------------------------------------*/\n\nsize_t xPortGetFreeHeapSize( void )\n{\n    return xFreeBytesRemaining;\n}\n/*-----------------------------------------------------------*/\n\nsize_t xPortGetMinimumEverFreeHeapSize( void )\n{\n    return xMinimumEverFreeBytesRemaining;\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM23/secure/secure_heap.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef __SECURE_HEAP_H__\n#define __SECURE_HEAP_H__\n\n/* Standard includes. */\n#include <stdlib.h>\n\n/**\n * @brief Allocates memory from heap.\n *\n * @param[in] xWantedSize The size of the memory to be allocated.\n *\n * @return Pointer to the memory region if the allocation is successful, NULL\n * otherwise.\n */\nvoid * pvPortMalloc( size_t xWantedSize );\n\n/**\n * @brief Frees the previously allocated memory.\n *\n * @param[in] pv Pointer to the memory to be freed.\n */\nvoid vPortFree( void * pv );\n\n/**\n * @brief Get the free heap size.\n *\n * @return Free heap size.\n */\nsize_t xPortGetFreeHeapSize( void );\n\n/**\n * @brief Get the minimum ever free heap size.\n *\n * @return Minimum ever free heap size.\n */\nsize_t xPortGetMinimumEverFreeHeapSize( void );\n\n#endif /* __SECURE_HEAP_H__ */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM23/secure/secure_init.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Standard includes. */\n#include <stdint.h>\n\n/* Secure init includes. */\n#include \"secure_init.h\"\n\n/* Secure port macros. */\n#include \"secure_port_macros.h\"\n\n/**\n * @brief Constants required to manipulate the SCB.\n */\n#define secureinitSCB_AIRCR                 ( ( volatile uint32_t * ) 0xe000ed0c )  /* Application Interrupt and Reset Control Register. */\n#define secureinitSCB_AIRCR_VECTKEY_POS     ( 16UL )\n#define secureinitSCB_AIRCR_VECTKEY_MASK    ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )\n#define secureinitSCB_AIRCR_PRIS_POS        ( 14UL )\n#define secureinitSCB_AIRCR_PRIS_MASK       ( 1UL << secureinitSCB_AIRCR_PRIS_POS )\n\n/**\n * @brief Constants required to manipulate the FPU.\n */\n#define secureinitFPCCR                     ( ( volatile uint32_t * ) 0xe000ef34 )  /* Floating Point Context Control Register. */\n#define secureinitFPCCR_LSPENS_POS          ( 29UL )\n#define secureinitFPCCR_LSPENS_MASK         ( 1UL << secureinitFPCCR_LSPENS_POS )\n#define secureinitFPCCR_TS_POS              ( 26UL )\n#define secureinitFPCCR_TS_MASK             ( 1UL << secureinitFPCCR_TS_POS )\n\n#define secureinitNSACR                     ( ( volatile uint32_t * ) 0xe000ed8c )  /* Non-secure Access Control Register. */\n#define secureinitNSACR_CP10_POS            ( 10UL )\n#define secureinitNSACR_CP10_MASK           ( 1UL << secureinitNSACR_CP10_POS )\n#define secureinitNSACR_CP11_POS            ( 11UL )\n#define secureinitNSACR_CP11_MASK           ( 1UL << secureinitNSACR_CP11_POS )\n/*-----------------------------------------------------------*/\n\nsecureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void )\n{\n    uint32_t ulIPSR;\n\n    /* Read the Interrupt Program Status Register (IPSR) value. */\n    secureportREAD_IPSR( ulIPSR );\n\n    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\n     * when the processor is running in the Thread Mode. */\n    if( ulIPSR != 0 )\n    {\n        *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |\n                                   ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |\n                                   ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK );\n    }\n}\n/*-----------------------------------------------------------*/\n\nsecureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )\n{\n    uint32_t ulIPSR;\n\n    /* Read the Interrupt Program Status Register (IPSR) value. */\n    secureportREAD_IPSR( ulIPSR );\n\n    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\n     * when the processor is running in the Thread Mode. */\n    if( ulIPSR != 0 )\n    {\n        /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is\n         * permitted. CP11 should be programmed to the same value as CP10. */\n        *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );\n\n        /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures\n         * that we can enable/disable lazy stacking in port.c file. */\n        *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK );\n\n        /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP\n         * registers (S16-S31) are also pushed to stack on exception entry and\n         * restored on exception return. */\n        *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );\n    }\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM23/secure/secure_init.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef __SECURE_INIT_H__\n#define __SECURE_INIT_H__\n\n/**\n * @brief De-prioritizes the non-secure exceptions.\n *\n * This is needed to ensure that the non-secure PendSV runs at the lowest\n * priority. Context switch is done in the non-secure PendSV handler.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n */\nvoid SecureInit_DePrioritizeNSExceptions( void );\n\n/**\n * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access.\n *\n * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point\n * Registers are not leaked to the non-secure side.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n */\nvoid SecureInit_EnableNSFPUAccess( void );\n\n#endif /* __SECURE_INIT_H__ */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM23/secure/secure_port_macros.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef __SECURE_PORT_MACROS_H__\n#define __SECURE_PORT_MACROS_H__\n\n/**\n * @brief Byte alignment requirements.\n */\n#define secureportBYTE_ALIGNMENT         8\n#define secureportBYTE_ALIGNMENT_MASK    ( 0x0007 )\n\n/**\n * @brief Macro to declare a function as non-secure callable.\n */\n#if defined( __IAR_SYSTEMS_ICC__ )\n    #define secureportNON_SECURE_CALLABLE    __cmse_nonsecure_entry __root\n#else\n    #define secureportNON_SECURE_CALLABLE    __attribute__( ( cmse_nonsecure_entry ) ) __attribute__( ( used ) )\n#endif\n\n/**\n * @brief Set the secure PRIMASK value.\n */\n#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \\\n    __asm volatile ( \"msr primask, %0\" : : \"r\" ( ulPrimaskValue ) : \"memory\" )\n\n/**\n * @brief Set the non-secure PRIMASK value.\n */\n#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \\\n    __asm volatile ( \"msr primask_ns, %0\" : : \"r\" ( ulPrimaskValue ) : \"memory\" )\n\n/**\n * @brief Read the PSP value in the given variable.\n */\n#define secureportREAD_PSP( pucOutCurrentStackPointer ) \\\n    __asm volatile ( \"mrs %0, psp\"  : \"=r\" ( pucOutCurrentStackPointer ) )\n\n/**\n * @brief Set the PSP to the given value.\n */\n#define secureportSET_PSP( pucCurrentStackPointer ) \\\n    __asm volatile ( \"msr psp, %0\" : : \"r\" ( pucCurrentStackPointer ) )\n\n/**\n * @brief Read the PSPLIM value in the given variable.\n */\n#define secureportREAD_PSPLIM( pucOutStackLimit ) \\\n    __asm volatile ( \"mrs %0, psplim\"  : \"=r\" ( pucOutStackLimit ) )\n\n/**\n * @brief Set the PSPLIM to the given value.\n */\n#define secureportSET_PSPLIM( pucStackLimit ) \\\n    __asm volatile ( \"msr psplim, %0\" : : \"r\" ( pucStackLimit ) )\n\n/**\n * @brief Set the NonSecure MSP to the given value.\n */\n#define secureportSET_MSP_NS( pucMainStackPointer ) \\\n    __asm volatile ( \"msr msp_ns, %0\" : : \"r\" ( pucMainStackPointer ) )\n\n/**\n * @brief Set the CONTROL register to the given value.\n */\n#define secureportSET_CONTROL( ulControl ) \\\n    __asm volatile ( \"msr control, %0\" : : \"r\" ( ulControl ) : \"memory\" )\n\n/**\n * @brief Read the Interrupt Program Status Register (IPSR) value in the given\n * variable.\n */\n#define secureportREAD_IPSR( ulIPSR ) \\\n    __asm volatile ( \"mrs %0, ipsr\"  : \"=r\" ( ulIPSR ) )\n\n/**\n * @brief PRIMASK value to enable interrupts.\n */\n#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL     0\n\n/**\n * @brief PRIMASK value to disable interrupts.\n */\n#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL    1\n\n/**\n * @brief Disable secure interrupts.\n */\n#define secureportDISABLE_SECURE_INTERRUPTS()        secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )\n\n/**\n * @brief Disable non-secure interrupts.\n *\n * This effectively disables context switches.\n */\n#define secureportDISABLE_NON_SECURE_INTERRUPTS()    secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )\n\n/**\n * @brief Enable non-secure interrupts.\n */\n#define secureportENABLE_NON_SECURE_INTERRUPTS()     secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL )\n\n/**\n * @brief Assert definition.\n */\n#define secureportASSERT( x )                      \\\n    if( ( x ) == 0 )                               \\\n    {                                              \\\n        secureportDISABLE_SECURE_INTERRUPTS();     \\\n        secureportDISABLE_NON_SECURE_INTERRUPTS(); \\\n        for( ; ; ) {; }                            \\\n    }\n\n#endif /* __SECURE_PORT_MACROS_H__ */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM23_NTZ/non_secure/port.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\n * all the API functions to use the MPU wrappers. That should only be done when\n * task.h is included from an application file. */\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n/* MPU wrappers includes. */\n#include \"mpu_wrappers.h\"\n\n/* Portasm includes. */\n#include \"portasm.h\"\n\n#if ( configENABLE_TRUSTZONE == 1 )\n    /* Secure components includes. */\n    #include \"secure_context.h\"\n    #include \"secure_init.h\"\n#endif /* configENABLE_TRUSTZONE */\n\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/**\n * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only\n * i.e. the processor boots as secure and never jumps to the non-secure side.\n * The Trust Zone support in the port must be disabled in order to run FreeRTOS\n * on the secure side. The following are the valid configuration seetings:\n *\n * 1. Run FreeRTOS on the Secure Side:\n *    configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0\n *\n * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:\n *    configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1\n *\n * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:\n *    configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0\n */\n#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )\n    #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.\n#endif\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the NVIC.\n */\n#define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )\n#define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )\n#define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )\n#define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )\n#define portNVIC_SYSTICK_ENABLE_BIT           ( 1UL << 0UL )\n#define portNVIC_SYSTICK_INT_BIT              ( 1UL << 1UL )\n#define portNVIC_SYSTICK_CLK_BIT              ( 1UL << 2UL )\n#define portNVIC_SYSTICK_COUNT_FLAG_BIT       ( 1UL << 16UL )\n#define portNVIC_PEND_SYSTICK_CLEAR_BIT       ( 1UL << 25UL )\n#define portNVIC_PEND_SYSTICK_SET_BIT         ( 1UL << 26UL )\n#define portMIN_INTERRUPT_PRIORITY            ( 255UL )\n#define portNVIC_PENDSV_PRI                   ( portMIN_INTERRUPT_PRIORITY << 16UL )\n#define portNVIC_SYSTICK_PRI                  ( portMIN_INTERRUPT_PRIORITY << 24UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the SCB.\n */\n#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( volatile uint32_t * ) 0xe000ed24 )\n#define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the FPU.\n */\n#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 )              /* Coprocessor Access Control Register. */\n#define portCPACR_CP10_VALUE    ( 3UL )\n#define portCPACR_CP11_VALUE    portCPACR_CP10_VALUE\n#define portCPACR_CP10_POS      ( 20UL )\n#define portCPACR_CP11_POS      ( 22UL )\n\n#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 )              /* Floating Point Context Control Register. */\n#define portFPCCR_ASPEN_POS     ( 31UL )\n#define portFPCCR_ASPEN_MASK    ( 1UL << portFPCCR_ASPEN_POS )\n#define portFPCCR_LSPEN_POS     ( 30UL )\n#define portFPCCR_LSPEN_MASK    ( 1UL << portFPCCR_LSPEN_POS )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the MPU.\n */\n#define portMPU_TYPE_REG                      ( *( ( volatile uint32_t * ) 0xe000ed90 ) )\n#define portMPU_CTRL_REG                      ( *( ( volatile uint32_t * ) 0xe000ed94 ) )\n#define portMPU_RNR_REG                       ( *( ( volatile uint32_t * ) 0xe000ed98 ) )\n\n#define portMPU_RBAR_REG                      ( *( ( volatile uint32_t * ) 0xe000ed9c ) )\n#define portMPU_RLAR_REG                      ( *( ( volatile uint32_t * ) 0xe000eda0 ) )\n\n#define portMPU_RBAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda4 ) )\n#define portMPU_RLAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda8 ) )\n\n#define portMPU_RBAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edac ) )\n#define portMPU_RLAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edb0 ) )\n\n#define portMPU_RBAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb4 ) )\n#define portMPU_RLAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb8 ) )\n\n#define portMPU_MAIR0_REG                     ( *( ( volatile uint32_t * ) 0xe000edc0 ) )\n#define portMPU_MAIR1_REG                     ( *( ( volatile uint32_t * ) 0xe000edc4 ) )\n\n#define portMPU_RBAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */\n#define portMPU_RLAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */\n\n#define portMPU_MAIR_ATTR0_POS                ( 0UL )\n#define portMPU_MAIR_ATTR0_MASK               ( 0x000000ff )\n\n#define portMPU_MAIR_ATTR1_POS                ( 8UL )\n#define portMPU_MAIR_ATTR1_MASK               ( 0x0000ff00 )\n\n#define portMPU_MAIR_ATTR2_POS                ( 16UL )\n#define portMPU_MAIR_ATTR2_MASK               ( 0x00ff0000 )\n\n#define portMPU_MAIR_ATTR3_POS                ( 24UL )\n#define portMPU_MAIR_ATTR3_MASK               ( 0xff000000 )\n\n#define portMPU_MAIR_ATTR4_POS                ( 0UL )\n#define portMPU_MAIR_ATTR4_MASK               ( 0x000000ff )\n\n#define portMPU_MAIR_ATTR5_POS                ( 8UL )\n#define portMPU_MAIR_ATTR5_MASK               ( 0x0000ff00 )\n\n#define portMPU_MAIR_ATTR6_POS                ( 16UL )\n#define portMPU_MAIR_ATTR6_MASK               ( 0x00ff0000 )\n\n#define portMPU_MAIR_ATTR7_POS                ( 24UL )\n#define portMPU_MAIR_ATTR7_MASK               ( 0xff000000 )\n\n#define portMPU_RLAR_ATTR_INDEX0              ( 0UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX1              ( 1UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX2              ( 2UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX3              ( 3UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX4              ( 4UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX5              ( 5UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX6              ( 6UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX7              ( 7UL << 1UL )\n\n#define portMPU_RLAR_REGION_ENABLE            ( 1UL )\n\n/* Enable privileged access to unmapped region. */\n#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )\n\n/* Enable MPU. */\n#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )\n\n/* Expected value of the portMPU_TYPE register. */\n#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief The maximum 24-bit number.\n *\n * It is needed because the systick is a 24-bit counter.\n */\n#define portMAX_24_BIT_NUMBER       ( 0xffffffUL )\n\n/**\n * @brief A fiddle factor to estimate the number of SysTick counts that would\n * have occurred while the SysTick counter is stopped during tickless idle\n * calculations.\n */\n#define portMISSED_COUNTS_FACTOR    ( 94UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to set up the initial stack.\n */\n#define portINITIAL_XPSR    ( 0x01000000 )\n\n#if ( configRUN_FREERTOS_SECURE_ONLY == 1 )\n\n/**\n * @brief Initial EXC_RETURN value.\n *\n *     FF         FF         FF         FD\n * 1111 1111  1111 1111  1111 1111  1111 1101\n *\n * Bit[6] - 1 --> The exception was taken from the Secure state.\n * Bit[5] - 1 --> Do not skip stacking of additional state context.\n * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\n * Bit[3] - 1 --> Return to the Thread mode.\n * Bit[2] - 1 --> Restore registers from the process stack.\n * Bit[1] - 0 --> Reserved, 0.\n * Bit[0] - 1 --> The exception was taken to the Secure state.\n */\n    #define portINITIAL_EXC_RETURN    ( 0xfffffffd )\n#else\n\n/**\n * @brief Initial EXC_RETURN value.\n *\n *     FF         FF         FF         BC\n * 1111 1111  1111 1111  1111 1111  1011 1100\n *\n * Bit[6] - 0 --> The exception was taken from the Non-Secure state.\n * Bit[5] - 1 --> Do not skip stacking of additional state context.\n * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\n * Bit[3] - 1 --> Return to the Thread mode.\n * Bit[2] - 1 --> Restore registers from the process stack.\n * Bit[1] - 0 --> Reserved, 0.\n * Bit[0] - 0 --> The exception was taken to the Non-Secure state.\n */\n    #define portINITIAL_EXC_RETURN    ( 0xffffffbc )\n#endif /* configRUN_FREERTOS_SECURE_ONLY */\n\n/**\n * @brief CONTROL register privileged bit mask.\n *\n * Bit[0] in CONTROL register tells the privilege:\n *  Bit[0] = 0 ==> The task is privileged.\n *  Bit[0] = 1 ==> The task is not privileged.\n */\n#define portCONTROL_PRIVILEGED_MASK         ( 1UL << 0UL )\n\n/**\n * @brief Initial CONTROL register values.\n */\n#define portINITIAL_CONTROL_UNPRIVILEGED    ( 0x3 )\n#define portINITIAL_CONTROL_PRIVILEGED      ( 0x2 )\n\n/**\n * @brief Let the user override the default SysTick clock rate.  If defined by the\n * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the\n * configuration register.\n */\n#ifndef configSYSTICK_CLOCK_HZ\n    #define configSYSTICK_CLOCK_HZ             ( configCPU_CLOCK_HZ )\n    /* Ensure the SysTick is clocked at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( portNVIC_SYSTICK_CLK_BIT )\n#else\n    /* Select the option to clock SysTick not at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( 0 )\n#endif\n\n/**\n * @brief Let the user override the pre-loading of the initial LR with the\n * address of prvTaskExitError() in case it messes up unwinding of the stack\n * in the debugger.\n */\n#ifdef configTASK_RETURN_ADDRESS\n    #define portTASK_RETURN_ADDRESS    configTASK_RETURN_ADDRESS\n#else\n    #define portTASK_RETURN_ADDRESS    prvTaskExitError\n#endif\n\n/**\n * @brief If portPRELOAD_REGISTERS then registers will be given an initial value\n * when a task is created. This helps in debugging at the cost of code size.\n */\n#define portPRELOAD_REGISTERS    1\n\n/**\n * @brief A task is created without a secure context, and must call\n * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes\n * any secure calls.\n */\n#define portNO_SECURE_CONTEXT    0\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Used to catch tasks that attempt to return from their implementing\n * function.\n */\nstatic void prvTaskExitError( void );\n\n#if ( configENABLE_MPU == 1 )\n\n/**\n * @brief Setup the Memory Protection Unit (MPU).\n */\n    static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\n#endif /* configENABLE_MPU */\n\n#if ( configENABLE_FPU == 1 )\n\n/**\n * @brief Setup the Floating Point Unit (FPU).\n */\n    static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;\n#endif /* configENABLE_FPU */\n\n/**\n * @brief Setup the timer to generate the tick interrupts.\n *\n * The implementation in this file is weak to allow application writers to\n * change the timer used to generate the tick interrupt.\n */\nvoid vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Checks whether the current execution context is interrupt.\n *\n * @return pdTRUE if the current execution context is interrupt, pdFALSE\n * otherwise.\n */\nBaseType_t xPortIsInsideInterrupt( void );\n\n/**\n * @brief Yield the processor.\n */\nvoid vPortYield( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Enter critical section.\n */\nvoid vPortEnterCritical( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Exit from critical section.\n */\nvoid vPortExitCritical( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief SysTick handler.\n */\nvoid SysTick_Handler( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief C part of SVC handler.\n */\nportDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION;\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Each task maintains its own interrupt status in the critical nesting\n * variable.\n */\nPRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;\n\n#if ( configENABLE_TRUSTZONE == 1 )\n\n/**\n * @brief Saved as part of the task context to indicate which context the\n * task is using on the secure side.\n */\n    PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;\n#endif /* configENABLE_TRUSTZONE */\n\n#if ( configUSE_TICKLESS_IDLE == 1 )\n\n/**\n * @brief The number of SysTick increments that make up one tick period.\n */\n    PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0;\n\n/**\n * @brief The maximum number of tick periods that can be suppressed is\n * limited by the 24 bit resolution of the SysTick timer.\n */\n    PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0;\n\n/**\n * @brief Compensate for the CPU cycles that pass while the SysTick is\n * stopped (low power functionality only).\n */\n    PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TICKLESS_IDLE == 1 )\n    __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )\n    {\n        uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;\n        TickType_t xModifiableIdleTime;\n\n        /* Make sure the SysTick reload value does not overflow the counter. */\n        if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\n        {\n            xExpectedIdleTime = xMaximumPossibleSuppressedTicks;\n        }\n\n        /* Enter a critical section but don't use the taskENTER_CRITICAL()\n         * method as that will mask interrupts that should exit sleep mode. */\n        __asm volatile ( \"cpsid i\" ::: \"memory\" );\n        __asm volatile ( \"dsb\" );\n        __asm volatile ( \"isb\" );\n\n        /* If a context switch is pending or a task is waiting for the scheduler\n         * to be unsuspended then abandon the low power entry. */\n        if( eTaskConfirmSleepModeStatus() == eAbortSleep )\n        {\n            /* Re-enable interrupts - see comments above the cpsid instruction\n             * above. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n        }\n        else\n        {\n            /* Stop the SysTick momentarily.  The time the SysTick is stopped for\n             * is accounted for as best it can be, but using the tickless mode will\n             * inevitably result in some tiny drift of the time maintained by the\n             * kernel with respect to calendar time. */\n            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );\n\n            /* Use the SysTick current-value register to determine the number of\n             * SysTick decrements remaining until the next tick interrupt.  If the\n             * current-value register is zero, then there are actually\n             * ulTimerCountsForOneTick decrements remaining, not zero, because the\n             * SysTick requests the interrupt when decrementing from 1 to 0. */\n            ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n\n            if( ulSysTickDecrementsLeft == 0 )\n            {\n                ulSysTickDecrementsLeft = ulTimerCountsForOneTick;\n            }\n\n            /* Calculate the reload value required to wait xExpectedIdleTime\n             * tick periods.  -1 is used because this code normally executes part\n             * way through the first tick period.  But if the SysTick IRQ is now\n             * pending, then clear the IRQ, suppressing the first tick, and correct\n             * the reload value to reflect that the second tick period is already\n             * underway.  The expected idle time is always at least two ticks. */\n            ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );\n\n            if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )\n            {\n                portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;\n                ulReloadValue -= ulTimerCountsForOneTick;\n            }\n\n            if( ulReloadValue > ulStoppedTimerCompensation )\n            {\n                ulReloadValue -= ulStoppedTimerCompensation;\n            }\n\n            /* Set the new reload value. */\n            portNVIC_SYSTICK_LOAD_REG = ulReloadValue;\n\n            /* Clear the SysTick count flag and set the count value back to\n             * zero. */\n            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n            /* Restart SysTick. */\n            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\n\n            /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can\n             * set its parameter to 0 to indicate that its implementation contains\n             * its own wait for interrupt or wait for event instruction, and so wfi\n             * should not be executed again.  However, the original expected idle\n             * time variable must remain unmodified, so a copy is taken. */\n            xModifiableIdleTime = xExpectedIdleTime;\n            configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\n\n            if( xModifiableIdleTime > 0 )\n            {\n                __asm volatile ( \"dsb\" ::: \"memory\" );\n                __asm volatile ( \"wfi\" );\n                __asm volatile ( \"isb\" );\n            }\n\n            configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\n\n            /* Re-enable interrupts to allow the interrupt that brought the MCU\n             * out of sleep mode to execute immediately.  See comments above\n             * the cpsid instruction above. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n            __asm volatile ( \"dsb\" );\n            __asm volatile ( \"isb\" );\n\n            /* Disable interrupts again because the clock is about to be stopped\n             * and interrupts that execute while the clock is stopped will increase\n             * any slippage between the time maintained by the RTOS and calendar\n             * time. */\n            __asm volatile ( \"cpsid i\" ::: \"memory\" );\n            __asm volatile ( \"dsb\" );\n            __asm volatile ( \"isb\" );\n\n            /* Disable the SysTick clock without reading the\n             * portNVIC_SYSTICK_CTRL_REG register to ensure the\n             * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,\n             * the time the SysTick is stopped for is accounted for as best it can\n             * be, but using the tickless mode will inevitably result in some tiny\n             * drift of the time maintained by the kernel with respect to calendar\n             * time*/\n            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );\n\n            /* Determine whether the SysTick has already counted to zero. */\n            if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n            {\n                uint32_t ulCalculatedLoadValue;\n\n                /* The tick interrupt ended the sleep (or is now pending), and\n                 * a new tick period has started.  Reset portNVIC_SYSTICK_LOAD_REG\n                 * with whatever remains of the new tick period. */\n                ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\n\n                /* Don't allow a tiny value, or values that have somehow\n                 * underflowed because the post sleep hook did something\n                 * that took too long or because the SysTick current-value register\n                 * is zero. */\n                if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )\n                {\n                    ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );\n                }\n\n                portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;\n\n                /* As the pending tick will be processed as soon as this\n                 * function exits, the tick value maintained by the tick is stepped\n                 * forward by one less than the time spent waiting. */\n                ulCompleteTickPeriods = xExpectedIdleTime - 1UL;\n            }\n            else\n            {\n                /* Something other than the tick interrupt ended the sleep. */\n\n                /* Use the SysTick current-value register to determine the\n                 * number of SysTick decrements remaining until the expected idle\n                 * time would have ended. */\n                ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n                #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )\n                {\n                    /* If the SysTick is not using the core clock, the current-\n                     * value register might still be zero here.  In that case, the\n                     * SysTick didn't load from the reload register, and there are\n                     * ulReloadValue decrements remaining in the expected idle\n                     * time, not zero. */\n                    if( ulSysTickDecrementsLeft == 0 )\n                    {\n                        ulSysTickDecrementsLeft = ulReloadValue;\n                    }\n                }\n                #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */\n\n                /* Work out how long the sleep lasted rounded to complete tick\n                 * periods (not the ulReload value which accounted for part\n                 * ticks). */\n                ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;\n\n                /* How many complete tick periods passed while the processor\n                 * was waiting? */\n                ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;\n\n                /* The reload value is set to whatever fraction of a single tick\n                 * period remains. */\n                portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;\n            }\n\n            /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,\n             * then set portNVIC_SYSTICK_LOAD_REG back to its standard value.  If\n             * the SysTick is not using the core clock, temporarily configure it to\n             * use the core clock.  This configuration forces the SysTick to load\n             * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next\n             * cycle of the other clock.  Then portNVIC_SYSTICK_LOAD_REG is ready\n             * to receive the standard value immediately. */\n            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n            portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n            #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )\n            {\n                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n            }\n            #else\n            {\n                /* The temporary usage of the core clock has served its purpose,\n                 * as described above.  Resume usage of the other clock. */\n                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\n\n                if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n                {\n                    /* The partial tick period already ended.  Be sure the SysTick\n                     * counts it only once. */\n                    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;\n                }\n\n                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n            }\n            #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */\n\n            /* Step the tick to account for any tick periods that elapsed. */\n            vTaskStepTick( ulCompleteTickPeriods );\n\n            /* Exit with interrupts enabled. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n        }\n    }\n#endif /* configUSE_TICKLESS_IDLE */\n/*-----------------------------------------------------------*/\n\n__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Calculate the constants required to configure the tick interrupt. */\n    #if ( configUSE_TICKLESS_IDLE == 1 )\n    {\n        ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );\n        xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;\n        ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\n    }\n    #endif /* configUSE_TICKLESS_IDLE */\n\n    /* Stop and reset the SysTick. */\n    portNVIC_SYSTICK_CTRL_REG = 0UL;\n    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n    /* Configure SysTick to interrupt at the requested rate. */\n    portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\n    portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvTaskExitError( void )\n{\n    volatile uint32_t ulDummy = 0UL;\n\n    /* A function that implements a task must not exit or attempt to return to\n     * its caller as there is nothing to return to. If a task wants to exit it\n     * should instead call vTaskDelete( NULL ). Artificially force an assert()\n     * to be triggered if configASSERT() is defined, then stop here so\n     * application writers can catch the error. */\n    configASSERT( ulCriticalNesting == ~0UL );\n    portDISABLE_INTERRUPTS();\n\n    while( ulDummy == 0 )\n    {\n        /* This file calls prvTaskExitError() after the scheduler has been\n         * started to remove a compiler warning about the function being\n         * defined but never called.  ulDummy is used purely to quieten other\n         * warnings about code appearing after this function is called - making\n         * ulDummy volatile makes the compiler think the function could return\n         * and therefore not output an 'unreachable code' warning for code that\n         * appears after it. */\n    }\n}\n/*-----------------------------------------------------------*/\n\n#if ( configENABLE_MPU == 1 )\n    static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */\n    {\n        #if defined( __ARMCC_VERSION )\n\n            /* Declaration when these variable are defined in code instead of being\n             * exported from linker scripts. */\n            extern uint32_t * __privileged_functions_start__;\n            extern uint32_t * __privileged_functions_end__;\n            extern uint32_t * __syscalls_flash_start__;\n            extern uint32_t * __syscalls_flash_end__;\n            extern uint32_t * __unprivileged_flash_start__;\n            extern uint32_t * __unprivileged_flash_end__;\n            extern uint32_t * __privileged_sram_start__;\n            extern uint32_t * __privileged_sram_end__;\n        #else /* if defined( __ARMCC_VERSION ) */\n            /* Declaration when these variable are exported from linker scripts. */\n            extern uint32_t __privileged_functions_start__[];\n            extern uint32_t __privileged_functions_end__[];\n            extern uint32_t __syscalls_flash_start__[];\n            extern uint32_t __syscalls_flash_end__[];\n            extern uint32_t __unprivileged_flash_start__[];\n            extern uint32_t __unprivileged_flash_end__[];\n            extern uint32_t __privileged_sram_start__[];\n            extern uint32_t __privileged_sram_end__[];\n        #endif /* defined( __ARMCC_VERSION ) */\n\n        /* The only permitted number of regions are 8 or 16. */\n        configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );\n\n        /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */\n        configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );\n\n        /* Check that the MPU is present. */\n        if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )\n        {\n            /* MAIR0 - Index 0. */\n            portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\n            /* MAIR0 - Index 1. */\n            portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\n\n            /* Setup privileged flash as Read Only so that privileged tasks can\n             * read it but not modify. */\n            portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_PRIVILEGED_READ_ONLY );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Setup unprivileged flash as Read Only by both privileged and\n             * unprivileged tasks. All tasks can read it but no-one can modify. */\n            portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_READ_ONLY );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Setup unprivileged syscalls flash as Read Only by both privileged\n             * and unprivileged tasks. All tasks can read it but no-one can modify. */\n            portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_READ_ONLY );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Setup RAM containing kernel data for privileged access only. */\n            portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\n                               ( portMPU_REGION_EXECUTE_NEVER );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Enable mem fault. */\n            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;\n\n            /* Enable MPU with privileged background access i.e. unmapped\n             * regions have privileged access. */\n            portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );\n        }\n    }\n#endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\n#if ( configENABLE_FPU == 1 )\n    static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */\n    {\n        #if ( configENABLE_TRUSTZONE == 1 )\n        {\n            /* Enable non-secure access to the FPU. */\n            SecureInit_EnableNSFPUAccess();\n        }\n        #endif /* configENABLE_TRUSTZONE */\n\n        /* CP10 = 11 ==> Full access to FPU i.e. both privileged and\n         * unprivileged code should be able to access FPU. CP11 should be\n         * programmed to the same value as CP10. */\n        *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |\n                            ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )\n                            );\n\n        /* ASPEN = 1 ==> Hardware should automatically preserve floating point\n         * context on exception entry and restore on exception return.\n         * LSPEN = 1 ==> Enable lazy context save of FP state. */\n        *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );\n    }\n#endif /* configENABLE_FPU */\n/*-----------------------------------------------------------*/\n\nvoid vPortYield( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Set a PendSV to request a context switch. */\n    portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\n\n    /* Barriers are normally not required but do ensure the code is\n     * completely within the specified behaviour for the architecture. */\n    __asm volatile ( \"dsb\" ::: \"memory\" );\n    __asm volatile ( \"isb\" );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */\n{\n    portDISABLE_INTERRUPTS();\n    ulCriticalNesting++;\n\n    /* Barriers are normally not required but do ensure the code is\n     * completely within the specified behaviour for the architecture. */\n    __asm volatile ( \"dsb\" ::: \"memory\" );\n    __asm volatile ( \"isb\" );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */\n{\n    configASSERT( ulCriticalNesting );\n    ulCriticalNesting--;\n\n    if( ulCriticalNesting == 0 )\n    {\n        portENABLE_INTERRUPTS();\n    }\n}\n/*-----------------------------------------------------------*/\n\nvoid SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */\n{\n    uint32_t ulPreviousMask;\n\n    ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();\n    {\n        /* Increment the RTOS tick. */\n        if( xTaskIncrementTick() != pdFALSE )\n        {\n            /* Pend a context switch. */\n            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\n        }\n    }\n    portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */\n{\n    #if ( configENABLE_MPU == 1 )\n        #if defined( __ARMCC_VERSION )\n\n            /* Declaration when these variable are defined in code instead of being\n             * exported from linker scripts. */\n            extern uint32_t * __syscalls_flash_start__;\n            extern uint32_t * __syscalls_flash_end__;\n        #else\n            /* Declaration when these variable are exported from linker scripts. */\n            extern uint32_t __syscalls_flash_start__[];\n            extern uint32_t __syscalls_flash_end__[];\n        #endif /* defined( __ARMCC_VERSION ) */\n    #endif /* configENABLE_MPU */\n\n    uint32_t ulPC;\n\n    #if ( configENABLE_TRUSTZONE == 1 )\n        uint32_t ulR0, ulR1;\n        extern TaskHandle_t pxCurrentTCB;\n        #if ( configENABLE_MPU == 1 )\n            uint32_t ulControl, ulIsTaskPrivileged;\n        #endif /* configENABLE_MPU */\n    #endif /* configENABLE_TRUSTZONE */\n    uint8_t ucSVCNumber;\n\n    /* Register are stored on the stack in the following order - R0, R1, R2, R3,\n     * R12, LR, PC, xPSR. */\n    ulPC = pulCallerStackAddress[ 6 ];\n    ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];\n\n    switch( ucSVCNumber )\n    {\n        #if ( configENABLE_TRUSTZONE == 1 )\n            case portSVC_ALLOCATE_SECURE_CONTEXT:\n\n                /* R0 contains the stack size passed as parameter to the\n                 * vPortAllocateSecureContext function. */\n                ulR0 = pulCallerStackAddress[ 0 ];\n\n                #if ( configENABLE_MPU == 1 )\n                {\n                    /* Read the CONTROL register value. */\n                    __asm volatile ( \"mrs %0, control\"  : \"=r\" ( ulControl ) );\n\n                    /* The task that raised the SVC is privileged if Bit[0]\n                     * in the CONTROL register is 0. */\n                    ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );\n\n                    /* Allocate and load a context for the secure task. */\n                    xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );\n                }\n                #else /* if ( configENABLE_MPU == 1 ) */\n                {\n                    /* Allocate and load a context for the secure task. */\n                    xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );\n                }\n                #endif /* configENABLE_MPU */\n\n                configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );\n                SecureContext_LoadContext( xSecureContext, pxCurrentTCB );\n                break;\n\n            case portSVC_FREE_SECURE_CONTEXT:\n\n                /* R0 contains TCB being freed and R1 contains the secure\n                 * context handle to be freed. */\n                ulR0 = pulCallerStackAddress[ 0 ];\n                ulR1 = pulCallerStackAddress[ 1 ];\n\n                /* Free the secure context. */\n                SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );\n                break;\n        #endif /* configENABLE_TRUSTZONE */\n\n        case portSVC_START_SCHEDULER:\n            #if ( configENABLE_TRUSTZONE == 1 )\n            {\n                /* De-prioritize the non-secure exceptions so that the\n                 * non-secure pendSV runs at the lowest priority. */\n                SecureInit_DePrioritizeNSExceptions();\n\n                /* Initialize the secure context management system. */\n                SecureContext_Init();\n            }\n            #endif /* configENABLE_TRUSTZONE */\n\n            #if ( configENABLE_FPU == 1 )\n            {\n                /* Setup the Floating Point Unit (FPU). */\n                prvSetupFPU();\n            }\n            #endif /* configENABLE_FPU */\n\n            /* Setup the context of the first task so that the first task starts\n             * executing. */\n            vRestoreContextOfFirstTask();\n            break;\n\n            #if ( configENABLE_MPU == 1 )\n                case portSVC_RAISE_PRIVILEGE:\n\n                    /* Only raise the privilege, if the svc was raised from any of\n                     * the system calls. */\n                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&\n                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )\n                    {\n                        vRaisePrivilege();\n                    }\n                    break;\n            #endif /* configENABLE_MPU */\n\n        default:\n            /* Incorrect SVC call. */\n            configASSERT( pdFALSE );\n    }\n}\n/*-----------------------------------------------------------*/\n/* *INDENT-OFF* */\n#if ( configENABLE_MPU == 1 )\n    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,\n                                         StackType_t * pxEndOfStack,\n                                         TaskFunction_t pxCode,\n                                         void * pvParameters,\n                                         BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */\n#else\n    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,\n                                         StackType_t * pxEndOfStack,\n                                         TaskFunction_t pxCode,\n                                         void * pvParameters ) /* PRIVILEGED_FUNCTION */\n#endif /* configENABLE_MPU */\n/* *INDENT-ON* */\n{\n    /* Simulate the stack frame as it would be created by a context switch\n     * interrupt. */\n    #if ( portPRELOAD_REGISTERS == 0 )\n    {\n        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\n        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\n        pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */\n        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */\n        pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */\n        *pxTopOfStack = portINITIAL_EXC_RETURN;\n\n        #if ( configENABLE_MPU == 1 )\n        {\n            pxTopOfStack--;\n\n            if( xRunPrivileged == pdTRUE )\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n            else\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n        }\n        #endif /* configENABLE_MPU */\n\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\n\n        #if ( configENABLE_TRUSTZONE == 1 )\n        {\n            pxTopOfStack--;\n            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\n        }\n        #endif /* configENABLE_TRUSTZONE */\n    }\n    #else /* portPRELOAD_REGISTERS */\n    {\n        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\n        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04 */\n        pxTopOfStack--;\n        *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN */\n\n        #if ( configENABLE_MPU == 1 )\n        {\n            pxTopOfStack--;\n\n            if( xRunPrivileged == pdTRUE )\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n            else\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n        }\n        #endif /* configENABLE_MPU */\n\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\n\n        #if ( configENABLE_TRUSTZONE == 1 )\n        {\n            pxTopOfStack--;\n            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\n        }\n        #endif /* configENABLE_TRUSTZONE */\n    }\n    #endif /* portPRELOAD_REGISTERS */\n\n    return pxTopOfStack;\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Make PendSV, CallSV and SysTick the same priority as the kernel. */\n    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;\n    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;\n\n    #if ( configENABLE_MPU == 1 )\n    {\n        /* Setup the Memory Protection Unit (MPU). */\n        prvSetupMPU();\n    }\n    #endif /* configENABLE_MPU */\n\n    /* Start the timer that generates the tick ISR. Interrupts are disabled\n     * here already. */\n    vPortSetupTimerInterrupt();\n\n    /* Initialize the critical nesting count ready for the first task. */\n    ulCriticalNesting = 0;\n\n    /* Start the first task. */\n    vStartFirstTask();\n\n    /* Should never get here as the tasks will now be executing. Call the task\n     * exit error function to prevent compiler warnings about a static function\n     * not being called in the case that the application writer overrides this\n     * functionality by defining configTASK_RETURN_ADDRESS. Call\n     * vTaskSwitchContext() so link time optimization does not remove the\n     * symbol. */\n    vTaskSwitchContext();\n    prvTaskExitError();\n\n    /* Should not get here. */\n    return 0;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Not implemented in ports where there is nothing to return to.\n     * Artificially force an assert. */\n    configASSERT( ulCriticalNesting == 1000UL );\n}\n/*-----------------------------------------------------------*/\n\n#if ( configENABLE_MPU == 1 )\n    void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,\n                                    const struct xMEMORY_REGION * const xRegions,\n                                    StackType_t * pxBottomOfStack,\n                                    uint32_t ulStackDepth )\n    {\n        uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;\n        int32_t lIndex = 0;\n\n        #if defined( __ARMCC_VERSION )\n\n            /* Declaration when these variable are defined in code instead of being\n             * exported from linker scripts. */\n            extern uint32_t * __privileged_sram_start__;\n            extern uint32_t * __privileged_sram_end__;\n        #else\n            /* Declaration when these variable are exported from linker scripts. */\n            extern uint32_t __privileged_sram_start__[];\n            extern uint32_t __privileged_sram_end__[];\n        #endif /* defined( __ARMCC_VERSION ) */\n\n        /* Setup MAIR0. */\n        xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\n        xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\n\n        /* This function is called automatically when the task is created - in\n         * which case the stack region parameters will be valid.  At all other\n         * times the stack parameters will not be valid and it is assumed that\n         * the stack region has already been configured. */\n        if( ulStackDepth > 0 )\n        {\n            ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;\n            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;\n\n            /* If the stack is within the privileged SRAM, do not protect it\n             * using a separate MPU region. This is needed because privileged\n             * SRAM is already protected using an MPU region and ARMv8-M does\n             * not allow overlapping MPU regions. */\n            if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) &&\n                ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) )\n            {\n                xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0;\n                xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0;\n            }\n            else\n            {\n                /* Define the region that allows access to the stack. */\n                ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK;\n                ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\n\n                xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |\n                                                             ( portMPU_REGION_NON_SHAREABLE ) |\n                                                             ( portMPU_REGION_READ_WRITE ) |\n                                                             ( portMPU_REGION_EXECUTE_NEVER );\n\n                xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) |\n                                                             ( portMPU_RLAR_ATTR_INDEX0 ) |\n                                                             ( portMPU_RLAR_REGION_ENABLE );\n            }\n        }\n\n        /* User supplied configurable regions. */\n        for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )\n        {\n            /* If xRegions is NULL i.e. the task has not specified any MPU\n             * region, the else part ensures that all the configurable MPU\n             * regions are invalidated. */\n            if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )\n            {\n                /* Translate the generic region definition contained in xRegions\n                 * into the ARMv8 specific MPU settings that are then stored in\n                 * xMPUSettings. */\n                ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;\n                ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;\n                ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\n\n                /* Start address. */\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |\n                                                                          ( portMPU_REGION_NON_SHAREABLE );\n\n                /* RO/RW. */\n                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )\n                {\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );\n                }\n                else\n                {\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );\n                }\n\n                /* XN. */\n                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )\n                {\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );\n                }\n\n                /* End Address. */\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |\n                                                                          ( portMPU_RLAR_REGION_ENABLE );\n\n                /* Normal memory/ Device memory. */\n                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )\n                {\n                    /* Attr1 in MAIR0 is configured as device memory. */\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;\n                }\n                else\n                {\n                    /* Attr0 in MAIR0 is configured as normal memory. */\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;\n                }\n            }\n            else\n            {\n                /* Invalidate the region. */\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;\n            }\n\n            lIndex++;\n        }\n    }\n#endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\nBaseType_t xPortIsInsideInterrupt( void )\n{\n    uint32_t ulCurrentInterrupt;\n    BaseType_t xReturn;\n\n    /* Obtain the number of the currently executing interrupt. Interrupt Program\n     * Status Register (IPSR) holds the exception number of the currently-executing\n     * exception or zero for Thread mode.*/\n    __asm volatile ( \"mrs %0, ipsr\" : \"=r\" ( ulCurrentInterrupt )::\"memory\" );\n\n    if( ulCurrentInterrupt == 0 )\n    {\n        xReturn = pdFALSE;\n    }\n    else\n    {\n        xReturn = pdTRUE;\n    }\n\n    return xReturn;\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef __PORT_ASM_H__\n#define __PORT_ASM_H__\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n\n/* MPU wrappers includes. */\n#include \"mpu_wrappers.h\"\n\n/**\n * @brief Restore the context of the first task so that the first task starts\n * executing.\n */\nvoid vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Checks whether or not the processor is privileged.\n *\n * @return 1 if the processor is already privileged, 0 otherwise.\n */\nBaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );\n\n/**\n * @brief Raises the privilege level by clearing the bit 0 of the CONTROL\n * register.\n *\n * @note This is a privileged function and should only be called from the kenrel\n * code.\n *\n * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.\n *  Bit[0] = 0 --> The processor is running privileged\n *  Bit[0] = 1 --> The processor is running unprivileged.\n */\nvoid vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\n * register.\n *\n * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.\n *  Bit[0] = 0 --> The processor is running privileged\n *  Bit[0] = 1 --> The processor is running unprivileged.\n */\nvoid vResetPrivilege( void ) __attribute__( ( naked ) );\n\n/**\n * @brief Starts the first task.\n */\nvoid vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Disables interrupts.\n */\nuint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Enables interrupts.\n */\nvoid vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief PendSV Exception handler.\n */\nvoid PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief SVC Handler.\n */\nvoid SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Allocate a Secure context for the calling task.\n *\n * @param[in] ulSecureStackSize The size of the stack to be allocated on the\n * secure side for the calling task.\n */\nvoid vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) );\n\n/**\n * @brief Free the task's secure context.\n *\n * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.\n */\nvoid vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n#endif /* __PORT_ASM_H__ */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n/* Including FreeRTOSConfig.h here will cause build errors if the header file\ncontains code not understood by the assembler - for example the 'extern' keyword.\nTo avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so\nthe code is included in C files but excluded by the preprocessor in assembly\nfiles (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */\n#include \"FreeRTOSConfig.h\"\n\n\tEXTERN pxCurrentTCB\n\tEXTERN vTaskSwitchContext\n\tEXTERN vPortSVCHandler_C\n\n\tPUBLIC xIsPrivileged\n\tPUBLIC vResetPrivilege\n\tPUBLIC vRestoreContextOfFirstTask\n\tPUBLIC vRaisePrivilege\n\tPUBLIC vStartFirstTask\n\tPUBLIC ulSetInterruptMask\n\tPUBLIC vClearInterruptMask\n\tPUBLIC PendSV_Handler\n\tPUBLIC SVC_Handler\n\n#if ( configENABLE_FPU == 1 )\n\t#error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.\n#endif\n/*-----------------------------------------------------------*/\n\n/*---------------- Unprivileged Functions -------------------*/\n\n/*-----------------------------------------------------------*/\n\n\tSECTION .text:CODE:NOROOT(2)\n\tTHUMB\n/*-----------------------------------------------------------*/\n\nxIsPrivileged:\n\tmrs r0, control\t\t\t\t\t\t\t/* r0 = CONTROL. */\n\tmovs r1, #1\t\t\t\t\t\t\t\t/* r1 = 1. */\n\ttst r0, r1\t\t\t\t\t\t\t\t/* Perform r0 & r1 (bitwise AND) and update the conditions flag. */\n\tbeq running_privileged\t\t\t\t\t/* If the result of previous AND operation was 0, branch. */\n\tmovs r0, #0\t\t\t\t\t\t\t\t/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\n\tbx lr\t\t\t\t\t\t\t\t\t/* Return. */\n\trunning_privileged:\n\t\tmovs r0, #1\t\t\t\t\t\t\t/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */\n\t\tbx lr\t\t\t\t\t\t\t\t/* Return. */\n\n/*-----------------------------------------------------------*/\n\nvResetPrivilege:\n\tmrs r0, control\t\t\t\t\t\t\t/* r0 = CONTROL. */\n\tmovs r1, #1\t\t\t\t\t\t\t\t/* r1 = 1. */\n\torrs r0, r1\t\t\t\t\t\t\t\t/* r0 = r0 | r1. */\n\tmsr control, r0\t\t\t\t\t\t\t/* CONTROL = r0. */\n\tbx lr\t\t\t\t\t\t\t\t\t/* Return to the caller. */\n/*-----------------------------------------------------------*/\n\n/*----------------- Privileged Functions --------------------*/\n\n/*-----------------------------------------------------------*/\n\n\tSECTION privileged_functions:CODE:NOROOT(2)\n\tTHUMB\n/*-----------------------------------------------------------*/\n\nvRestoreContextOfFirstTask:\n\tldr  r2, =pxCurrentTCB\t\t\t\t\t/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n\tldr  r1, [r2]\t\t\t\t\t\t\t/* Read pxCurrentTCB. */\n\tldr  r0, [r1]\t\t\t\t\t\t\t/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\n\n#if ( configENABLE_MPU == 1 )\n\tdmb\t\t\t\t\t\t\t\t\t\t/* Complete outstanding transfers before disabling MPU. */\n\tldr r2, =0xe000ed94\t\t\t\t\t\t/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n\tldr r3, [r2]\t\t\t\t\t\t\t/* Read the value of MPU_CTRL. */\n\tmovs r4, #1\t\t\t\t\t\t\t\t/* r4 = 1. */\n\tbics r3, r4\t\t\t\t\t\t\t\t/* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */\n\tstr r3, [r2]\t\t\t\t\t\t\t/* Disable MPU. */\n\n\tadds r1, #4\t\t\t\t\t\t\t\t/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\n\tldr  r4, [r1]\t\t\t\t\t\t\t/* r4 = *r1 i.e. r4 = MAIR0. */\n\tldr  r2, =0xe000edc0\t\t\t\t\t/* r2 = 0xe000edc0 [Location of MAIR0]. */\n\tstr  r4, [r2]\t\t\t\t\t\t\t/* Program MAIR0. */\n\tldr  r2, =0xe000ed98\t\t\t\t\t/* r2 = 0xe000ed98 [Location of RNR]. */\n\tadds r1, #4\t\t\t\t\t\t\t\t/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\n\tmovs r4, #4\t\t\t\t\t\t\t\t/* r4 = 4. */\n\tstr  r4, [r2]\t\t\t\t\t\t\t/* Program RNR = 4. */\n\tldmia r1!, {r5,r6}\t\t\t\t\t\t/* Read first set of RBAR/RLAR from TCB. */\n\tldr  r3, =0xe000ed9c\t\t\t\t\t/* r3 = 0xe000ed9c [Location of RBAR]. */\n\tstmia r3!, {r5,r6}\t\t\t\t\t\t/* Write first set of RBAR/RLAR registers. */\n\tmovs r4, #5\t\t\t\t\t\t\t\t/* r4 = 5. */\n\tstr  r4, [r2]\t\t\t\t\t\t\t/* Program RNR = 5. */\n\tldmia r1!, {r5,r6}\t\t\t\t\t\t/* Read second set of RBAR/RLAR from TCB. */\n\tldr  r3, =0xe000ed9c\t\t\t\t\t/* r3 = 0xe000ed9c [Location of RBAR]. */\n\tstmia r3!, {r5,r6}\t\t\t\t\t\t/* Write second set of RBAR/RLAR registers. */\n\tmovs r4, #6\t\t\t\t\t\t\t\t/* r4 = 6. */\n\tstr  r4, [r2]\t\t\t\t\t\t\t/* Program RNR = 6. */\n\tldmia r1!, {r5,r6}\t\t\t\t\t\t/* Read third set of RBAR/RLAR from TCB. */\n\tldr  r3, =0xe000ed9c\t\t\t\t\t/* r3 = 0xe000ed9c [Location of RBAR]. */\n\tstmia r3!, {r5,r6}\t\t\t\t\t\t/* Write third set of RBAR/RLAR registers. */\n\tmovs r4, #7\t\t\t\t\t\t\t\t/* r4 = 7. */\n\tstr  r4, [r2]\t\t\t\t\t\t\t/* Program RNR = 7. */\n\tldmia r1!, {r5,r6}\t\t\t\t\t\t/* Read fourth set of RBAR/RLAR from TCB. */\n\tldr  r3, =0xe000ed9c\t\t\t\t\t/* r3 = 0xe000ed9c [Location of RBAR]. */\n\tstmia r3!, {r5,r6}\t\t\t\t\t\t/* Write fourth set of RBAR/RLAR registers. */\n\n\tldr r2, =0xe000ed94\t\t\t\t\t\t/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n\tldr r3, [r2]\t\t\t\t\t\t\t/* Read the value of MPU_CTRL. */\n\tmovs r4, #1\t\t\t\t\t\t\t\t/* r4 = 1. */\n\torrs r3, r4\t\t\t\t\t\t\t\t/* r3 = r3 | r4 i.e. Set the bit 0 in r3. */\n\tstr r3, [r2]\t\t\t\t\t\t\t/* Enable MPU. */\n\tdsb\t\t\t\t\t\t\t\t\t\t/* Force memory writes before continuing. */\n#endif /* configENABLE_MPU */\n\n#if ( configENABLE_MPU == 1 )\n\tldm  r0!, {r1-r3}\t\t\t\t\t\t/* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */\n\tmsr  psplim, r1\t\t\t\t\t\t\t/* Set this task's PSPLIM value. */\n\tmsr  control, r2\t\t\t\t\t\t/* Set this task's CONTROL value. */\n\tadds r0, #32\t\t\t\t\t\t\t/* Discard everything up to r0. */\n\tmsr  psp, r0\t\t\t\t\t\t\t/* This is now the new top of stack to use in the task. */\n\tisb\n\tbx   r3\t\t\t\t\t\t\t\t\t/* Finally, branch to EXC_RETURN. */\n#else /* configENABLE_MPU */\n\tldm  r0!, {r1-r2}\t\t\t\t\t\t/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */\n\tmsr  psplim, r1\t\t\t\t\t\t\t/* Set this task's PSPLIM value. */\n\tmovs r1, #2\t\t\t\t\t\t\t\t/* r1 = 2. */\n\tmsr  CONTROL, r1\t\t\t\t\t\t/* Switch to use PSP in the thread mode. */\n\tadds r0, #32\t\t\t\t\t\t\t/* Discard everything up to r0. */\n\tmsr  psp, r0\t\t\t\t\t\t\t/* This is now the new top of stack to use in the task. */\n\tisb\n\tbx   r2\t\t\t\t\t\t\t\t\t/* Finally, branch to EXC_RETURN. */\n#endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\nvRaisePrivilege:\n\tmrs  r0, control\t\t\t\t\t\t/* Read the CONTROL register. */\n\tmovs r1, #1\t\t\t\t\t\t\t\t/* r1 = 1. */\n\tbics r0, r1\t\t\t\t\t\t\t\t/* Clear the bit 0. */\n\tmsr  control, r0\t\t\t\t\t\t/* Write back the new CONTROL value. */\n\tbx lr\t\t\t\t\t\t\t\t\t/* Return to the caller. */\n/*-----------------------------------------------------------*/\n\nvStartFirstTask:\n\tldr r0, =0xe000ed08\t\t\t\t\t\t/* Use the NVIC offset register to locate the stack. */\n\tldr r0, [r0]\t\t\t\t\t\t\t/* Read the VTOR register which gives the address of vector table. */\n\tldr r0, [r0]\t\t\t\t\t\t\t/* The first entry in vector table is stack pointer. */\n\tmsr msp, r0\t\t\t\t\t\t\t\t/* Set the MSP back to the start of the stack. */\n\tcpsie i\t\t\t\t\t\t\t\t\t/* Globally enable interrupts. */\n\tdsb\n\tisb\n\tsvc 2\t\t\t\t\t\t\t\t\t/* System call to start the first task. portSVC_START_SCHEDULER = 2. */\n\tnop\n/*-----------------------------------------------------------*/\n\nulSetInterruptMask:\n\tmrs r0, PRIMASK\n\tcpsid i\n\tbx lr\n/*-----------------------------------------------------------*/\n\nvClearInterruptMask:\n\tmsr PRIMASK, r0\n\tbx lr\n/*-----------------------------------------------------------*/\n\nPendSV_Handler:\n\tmrs r0, psp\t\t\t\t\t\t\t\t/* Read PSP in r0. */\n\tldr r2, =pxCurrentTCB\t\t\t\t\t/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n\tldr r1, [r2]\t\t\t\t\t\t\t/* Read pxCurrentTCB. */\n#if ( configENABLE_MPU == 1 )\n\tsubs r0, r0, #44\t\t\t\t\t\t/* Make space for PSPLIM, CONTROL, LR and the remaining registers on the stack. */\n\tstr r0, [r1]\t\t\t\t\t\t\t/* Save the new top of stack in TCB. */\n\tmrs r1, psplim\t\t\t\t\t\t\t/* r1 = PSPLIM. */\n\tmrs r2, control\t\t\t\t\t\t\t/* r2 = CONTROL. */\n\tmov r3, lr\t\t\t\t\t\t\t\t/* r3 = LR/EXC_RETURN. */\n\tstmia r0!, {r1-r7}\t\t\t\t\t\t/* Store on the stack - PSPLIM, CONTROL, LR and low registers that are not automatically saved. */\n\tmov r4, r8\t\t\t\t\t\t\t\t/* r4 = r8. */\n\tmov r5, r9\t\t\t\t\t\t\t\t/* r5 = r9. */\n\tmov r6, r10\t\t\t\t\t\t\t\t/* r6 = r10. */\n\tmov r7, r11\t\t\t\t\t\t\t\t/* r7 = r11. */\n\tstmia r0!, {r4-r7}\t\t\t\t\t\t/* Store the high registers that are not saved automatically. */\n#else /* configENABLE_MPU */\n\tsubs r0, r0, #40\t\t\t\t\t\t/* Make space for PSPLIM, LR and the remaining registers on the stack. */\n\tstr r0, [r1]\t\t\t\t\t\t\t/* Save the new top of stack in TCB. */\n\tmrs r2, psplim\t\t\t\t\t\t\t/* r2 = PSPLIM. */\n\tmov r3, lr\t\t\t\t\t\t\t\t/* r3 = LR/EXC_RETURN. */\n\tstmia r0!, {r2-r7}\t\t\t\t\t\t/* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */\n\tmov r4, r8\t\t\t\t\t\t\t\t/* r4 = r8. */\n\tmov r5, r9\t\t\t\t\t\t\t\t/* r5 = r9. */\n\tmov r6, r10\t\t\t\t\t\t\t\t/* r6 = r10. */\n\tmov r7, r11\t\t\t\t\t\t\t\t/* r7 = r11. */\n\tstmia r0!, {r4-r7}\t\t\t\t\t\t/* Store the high registers that are not saved automatically. */\n#endif /* configENABLE_MPU */\n\n\tcpsid i\n\tbl vTaskSwitchContext\n\tcpsie i\n\n\tldr r2, =pxCurrentTCB\t\t\t\t\t/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n\tldr r1, [r2]\t\t\t\t\t\t\t/* Read pxCurrentTCB. */\n\tldr r0, [r1]\t\t\t\t\t\t\t/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */\n\n#if ( configENABLE_MPU == 1 )\n\tdmb\t\t\t\t\t\t\t\t\t\t/* Complete outstanding transfers before disabling MPU. */\n\tldr r2, =0xe000ed94\t\t\t\t\t\t/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n\tldr r3, [r2]\t\t\t\t\t\t\t/* Read the value of MPU_CTRL. */\n\tmovs r4, #1\t\t\t\t\t\t\t\t/* r4 = 1. */\n\tbics r3, r4\t\t\t\t\t\t\t\t/* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */\n\tstr r3, [r2]\t\t\t\t\t\t\t/* Disable MPU. */\n\n\tadds r1, #4\t\t\t\t\t\t\t\t/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\n\tldr  r4, [r1]\t\t\t\t\t\t\t/* r4 = *r1 i.e. r4 = MAIR0. */\n\tldr  r2, =0xe000edc0\t\t\t\t\t/* r2 = 0xe000edc0 [Location of MAIR0]. */\n\tstr  r4, [r2]\t\t\t\t\t\t\t/* Program MAIR0. */\n\tldr  r2, =0xe000ed98\t\t\t\t\t/* r2 = 0xe000ed98 [Location of RNR]. */\n\tadds r1, #4\t\t\t\t\t\t\t\t/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\n\tmovs r4, #4\t\t\t\t\t\t\t\t/* r4 = 4. */\n\tstr  r4, [r2]\t\t\t\t\t\t\t/* Program RNR = 4. */\n\tldmia r1!, {r5,r6}\t\t\t\t\t\t/* Read first set of RBAR/RLAR from TCB. */\n\tldr  r3, =0xe000ed9c\t\t\t\t\t/* r3 = 0xe000ed9c [Location of RBAR]. */\n\tstmia r3!, {r5,r6}\t\t\t\t\t\t/* Write first set of RBAR/RLAR registers. */\n\tmovs r4, #5\t\t\t\t\t\t\t\t/* r4 = 5. */\n\tstr  r4, [r2]\t\t\t\t\t\t\t/* Program RNR = 5. */\n\tldmia r1!, {r5,r6}\t\t\t\t\t\t/* Read second set of RBAR/RLAR from TCB. */\n\tldr  r3, =0xe000ed9c\t\t\t\t\t/* r3 = 0xe000ed9c [Location of RBAR]. */\n\tstmia r3!, {r5,r6}\t\t\t\t\t\t/* Write second set of RBAR/RLAR registers. */\n\tmovs r4, #6\t\t\t\t\t\t\t\t/* r4 = 6. */\n\tstr  r4, [r2]\t\t\t\t\t\t\t/* Program RNR = 6. */\n\tldmia r1!, {r5,r6}\t\t\t\t\t\t/* Read third set of RBAR/RLAR from TCB. */\n\tldr  r3, =0xe000ed9c\t\t\t\t\t/* r3 = 0xe000ed9c [Location of RBAR]. */\n\tstmia r3!, {r5,r6}\t\t\t\t\t\t/* Write third set of RBAR/RLAR registers. */\n\tmovs r4, #7\t\t\t\t\t\t\t\t/* r4 = 7. */\n\tstr  r4, [r2]\t\t\t\t\t\t\t/* Program RNR = 7. */\n\tldmia r1!, {r5,r6}\t\t\t\t\t\t/* Read fourth set of RBAR/RLAR from TCB. */\n\tldr  r3, =0xe000ed9c\t\t\t\t\t/* r3 = 0xe000ed9c [Location of RBAR]. */\n\tstmia r3!, {r5,r6}\t\t\t\t\t\t/* Write fourth set of RBAR/RLAR registers. */\n\n\tldr r2, =0xe000ed94\t\t\t\t\t\t/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n\tldr r3, [r2]\t\t\t\t\t\t\t/* Read the value of MPU_CTRL. */\n\tmovs r4, #1\t\t\t\t\t\t\t\t/* r4 = 1. */\n\torrs r3, r4\t\t\t\t\t\t\t\t/* r3 = r3 | r4 i.e. Set the bit 0 in r3. */\n\tstr r3, [r2]\t\t\t\t\t\t\t/* Enable MPU. */\n\tdsb\t\t\t\t\t\t\t\t\t\t/* Force memory writes before continuing. */\n#endif /* configENABLE_MPU */\n\n#if ( configENABLE_MPU == 1 )\n\tadds r0, r0, #28\t\t\t\t\t\t/* Move to the high registers. */\n\tldmia r0!, {r4-r7}\t\t\t\t\t\t/* Restore the high registers that are not automatically restored. */\n\tmov r8, r4\t\t\t\t\t\t\t\t/* r8 = r4. */\n\tmov r9, r5\t\t\t\t\t\t\t\t/* r9 = r5. */\n\tmov r10, r6\t\t\t\t\t\t\t\t/* r10 = r6. */\n\tmov r11, r7\t\t\t\t\t\t\t\t/* r11 = r7. */\n\tmsr psp, r0\t\t\t\t\t\t\t\t/* Remember the new top of stack for the task. */\n\tsubs r0, r0, #44\t\t\t\t\t\t/* Move to the starting of the saved context. */\n\tldmia r0!, {r1-r7}\t\t\t\t\t\t/* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r7 restored. */\n\tmsr psplim, r1\t\t\t\t\t\t\t/* Restore the PSPLIM register value for the task. */\n\tmsr control, r2\t\t\t\t\t\t\t/* Restore the CONTROL register value for the task. */\n\tbx r3\n#else /* configENABLE_MPU */\n\tadds r0, r0, #24\t\t\t\t\t\t/* Move to the high registers. */\n\tldmia r0!, {r4-r7}\t\t\t\t\t\t/* Restore the high registers that are not automatically restored. */\n\tmov r8, r4\t\t\t\t\t\t\t\t/* r8 = r4. */\n\tmov r9, r5\t\t\t\t\t\t\t\t/* r9 = r5. */\n\tmov r10, r6\t\t\t\t\t\t\t\t/* r10 = r6. */\n\tmov r11, r7\t\t\t\t\t\t\t\t/* r11 = r7. */\n\tmsr psp, r0\t\t\t\t\t\t\t\t/* Remember the new top of stack for the task. */\n\tsubs r0, r0, #40\t\t\t\t\t\t/* Move to the starting of the saved context. */\n\tldmia r0!, {r2-r7}\t\t\t\t\t\t/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */\n\tmsr psplim, r2\t\t\t\t\t\t\t/* Restore the PSPLIM register value for the task. */\n\tbx r3\n#endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\nSVC_Handler:\n\tmovs r0, #4\n\tmov r1, lr\n\ttst r0, r1\n\tbeq stacking_used_msp\n\tmrs r0, psp\n\tb vPortSVCHandler_C\n\tstacking_used_msp:\n\t\tmrs r0, msp\n\t\tb vPortSVCHandler_C\n/*-----------------------------------------------------------*/\n\n\tEND\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef PORTMACRO_H\n#define PORTMACRO_H\n\n#ifdef __cplusplus\n    extern \"C\" {\n#endif\n\n#include \"portmacrocommon.h\"\n\n/*------------------------------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the given hardware\n * and compiler.\n *\n * These settings should not be altered.\n *------------------------------------------------------------------------------\n */\n\n/**\n * Architecture specifics.\n */\n#define portARCH_NAME                       \"Cortex-M23\"\n#define portDONT_DISCARD                    __root\n/*-----------------------------------------------------------*/\n\n#if( configTOTAL_MPU_REGIONS == 16 )\n    #error 16 MPU regions are not yet supported for this port.\n#endif\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Critical section management.\n */\n#define portDISABLE_INTERRUPTS()            __asm volatile ( \" cpsid i \" ::: \"memory\" )\n#define portENABLE_INTERRUPTS()             __asm volatile ( \" cpsie i \" ::: \"memory\" )\n/*-----------------------------------------------------------*/\n\n/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in\n * the source code because to do so would cause other compilers to generate\n * warnings. */\n#pragma diag_suppress=Be006\n#pragma diag_suppress=Pa082\n/*-----------------------------------------------------------*/\n\n#ifdef __cplusplus\n    }\n#endif\n\n#endif /* PORTMACRO_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef PORTMACROCOMMON_H\n    #define PORTMACROCOMMON_H\n\n    #ifdef __cplusplus\n        extern \"C\" {\n    #endif\n\n/*------------------------------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the given hardware\n * and compiler.\n *\n * These settings should not be altered.\n *------------------------------------------------------------------------------\n */\n\n    #ifndef configENABLE_FPU\n        #error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.\n    #endif /* configENABLE_FPU */\n\n    #ifndef configENABLE_MPU\n        #error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.\n    #endif /* configENABLE_MPU */\n\n    #ifndef configENABLE_TRUSTZONE\n        #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.\n    #endif /* configENABLE_TRUSTZONE */\n\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Type definitions.\n */\n    #define portCHAR          char\n    #define portFLOAT         float\n    #define portDOUBLE        double\n    #define portLONG          long\n    #define portSHORT         short\n    #define portSTACK_TYPE    uint32_t\n    #define portBASE_TYPE     long\n\n    typedef portSTACK_TYPE   StackType_t;\n    typedef long             BaseType_t;\n    typedef unsigned long    UBaseType_t;\n\n    #if ( configUSE_16_BIT_TICKS == 1 )\n        typedef uint16_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffff\n    #else\n        typedef uint32_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL\n\n/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\n * not need to be guarded with a critical section. */\n        #define portTICK_TYPE_IS_ATOMIC    1\n    #endif\n/*-----------------------------------------------------------*/\n\n/**\n * Architecture specifics.\n */\n    #define portSTACK_GROWTH                   ( -1 )\n    #define portTICK_PERIOD_MS                 ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\n    #define portBYTE_ALIGNMENT                 8\n    #define portNOP()\n    #define portINLINE                         __inline\n    #ifndef portFORCE_INLINE\n        #define portFORCE_INLINE               inline __attribute__( ( always_inline ) )\n    #endif\n    #define portHAS_STACK_OVERFLOW_CHECKING    1\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Extern declarations.\n */\n    extern BaseType_t xPortIsInsideInterrupt( void );\n\n    extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;\n\n    extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;\n    extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;\n\n    extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\n    extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\n\n    #if ( configENABLE_TRUSTZONE == 1 )\n        extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */\n        extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;\n    #endif /* configENABLE_TRUSTZONE */\n\n    #if ( configENABLE_MPU == 1 )\n        extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;\n        extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;\n    #endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\n/**\n * @brief MPU specific constants.\n */\n    #if ( configENABLE_MPU == 1 )\n        #define portUSING_MPU_WRAPPERS    1\n        #define portPRIVILEGE_BIT         ( 0x80000000UL )\n    #else\n        #define portPRIVILEGE_BIT         ( 0x0UL )\n    #endif /* configENABLE_MPU */\n\n/* MPU settings that can be overriden in FreeRTOSConfig.h. */\n#ifndef configTOTAL_MPU_REGIONS\n    /* Define to 8 for backward compatibility. */\n    #define configTOTAL_MPU_REGIONS       ( 8UL )\n#endif\n\n/* MPU regions. */\n    #define portPRIVILEGED_FLASH_REGION                   ( 0UL )\n    #define portUNPRIVILEGED_FLASH_REGION                 ( 1UL )\n    #define portUNPRIVILEGED_SYSCALLS_REGION              ( 2UL )\n    #define portPRIVILEGED_RAM_REGION                     ( 3UL )\n    #define portSTACK_REGION                              ( 4UL )\n    #define portFIRST_CONFIGURABLE_REGION                 ( 5UL )\n    #define portLAST_CONFIGURABLE_REGION                  ( configTOTAL_MPU_REGIONS - 1UL )\n    #define portNUM_CONFIGURABLE_REGIONS                  ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )\n    #define portTOTAL_NUM_REGIONS                         ( portNUM_CONFIGURABLE_REGIONS + 1 )   /* Plus one to make space for the stack region. */\n\n/* Device memory attributes used in MPU_MAIR registers.\n *\n * 8-bit values encoded as follows:\n *  Bit[7:4] - 0000 - Device Memory\n *  Bit[3:2] - 00 --> Device-nGnRnE\n *\t\t\t\t01 --> Device-nGnRE\n *\t\t\t\t10 --> Device-nGRE\n *\t\t\t\t11 --> Device-GRE\n *  Bit[1:0] - 00, Reserved.\n */\n    #define portMPU_DEVICE_MEMORY_nGnRnE                  ( 0x00 )   /* 0000 0000 */\n    #define portMPU_DEVICE_MEMORY_nGnRE                   ( 0x04 )   /* 0000 0100 */\n    #define portMPU_DEVICE_MEMORY_nGRE                    ( 0x08 )   /* 0000 1000 */\n    #define portMPU_DEVICE_MEMORY_GRE                     ( 0x0C )   /* 0000 1100 */\n\n/* Normal memory attributes used in MPU_MAIR registers. */\n    #define portMPU_NORMAL_MEMORY_NON_CACHEABLE           ( 0x44 )   /* Non-cacheable. */\n    #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE    ( 0xFF )   /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */\n\n/* Attributes used in MPU_RBAR registers. */\n    #define portMPU_REGION_NON_SHAREABLE                  ( 0UL << 3UL )\n    #define portMPU_REGION_INNER_SHAREABLE                ( 1UL << 3UL )\n    #define portMPU_REGION_OUTER_SHAREABLE                ( 2UL << 3UL )\n\n    #define portMPU_REGION_PRIVILEGED_READ_WRITE          ( 0UL << 1UL )\n    #define portMPU_REGION_READ_WRITE                     ( 1UL << 1UL )\n    #define portMPU_REGION_PRIVILEGED_READ_ONLY           ( 2UL << 1UL )\n    #define portMPU_REGION_READ_ONLY                      ( 3UL << 1UL )\n\n    #define portMPU_REGION_EXECUTE_NEVER                  ( 1UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Settings to define an MPU region.\n */\n    typedef struct MPURegionSettings\n    {\n        uint32_t ulRBAR; /**< RBAR for the region. */\n        uint32_t ulRLAR; /**< RLAR for the region. */\n    } MPURegionSettings_t;\n\n/**\n * @brief MPU settings as stored in the TCB.\n */\n    typedef struct MPU_SETTINGS\n    {\n        uint32_t ulMAIR0;                                              /**< MAIR0 for the task containing attributes for all the 4 per task regions. */\n        MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */\n    } xMPU_SETTINGS;\n/*-----------------------------------------------------------*/\n\n/**\n * @brief SVC numbers.\n */\n    #define portSVC_ALLOCATE_SECURE_CONTEXT    0\n    #define portSVC_FREE_SECURE_CONTEXT        1\n    #define portSVC_START_SCHEDULER            2\n    #define portSVC_RAISE_PRIVILEGE            3\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Scheduler utilities.\n */\n    #define portYIELD()                                 vPortYield()\n    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )\n    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )\n    #define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )\n    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Critical section management.\n */\n    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulSetInterruptMask()\n    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vClearInterruptMask( x )\n    #define portENTER_CRITICAL()                      vPortEnterCritical()\n    #define portEXIT_CRITICAL()                       vPortExitCritical()\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Tickless idle/low power functionality.\n */\n    #ifndef portSUPPRESS_TICKS_AND_SLEEP\n        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );\n        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )\n    #endif\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Task function macros as described on the FreeRTOS.org WEB site.\n */\n    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )\n    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )\n/*-----------------------------------------------------------*/\n\n    #if ( configENABLE_TRUSTZONE == 1 )\n\n/**\n * @brief Allocate a secure context for the task.\n *\n * Tasks are not created with a secure context. Any task that is going to call\n * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a\n * secure context before it calls any secure function.\n *\n * @param[in] ulSecureStackSize The size of the secure stack to be allocated.\n */\n        #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )\n\n/**\n * @brief Called when a task is deleted to delete the task's secure context,\n * if it has one.\n *\n * @param[in] pxTCB The TCB of the task being deleted.\n */\n        #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )\n    #endif /* configENABLE_TRUSTZONE */\n/*-----------------------------------------------------------*/\n\n    #if ( configENABLE_MPU == 1 )\n\n/**\n * @brief Checks whether or not the processor is privileged.\n *\n * @return 1 if the processor is already privileged, 0 otherwise.\n */\n        #define portIS_PRIVILEGED()      xIsPrivileged()\n\n/**\n * @brief Raise an SVC request to raise privilege.\n *\n * The SVC handler checks that the SVC was raised from a system call and only\n * then it raises the privilege. If this is called from any other place,\n * the privilege is not raised.\n */\n        #define portRAISE_PRIVILEGE()    __asm volatile ( \"svc %0 \\n\" ::\"i\" ( portSVC_RAISE_PRIVILEGE ) : \"memory\" );\n\n/**\n * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\n * register.\n */\n        #define portRESET_PRIVILEGE()    vResetPrivilege()\n    #else\n        #define portIS_PRIVILEGED()\n        #define portRAISE_PRIVILEGE()\n        #define portRESET_PRIVILEGE()\n    #endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Barriers.\n */\n    #define portMEMORY_BARRIER()    __asm volatile ( \"\" ::: \"memory\" )\n/*-----------------------------------------------------------*/\n\n    #ifdef __cplusplus\n        }\n    #endif\n\n#endif /* PORTMACROCOMMON_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM3/port.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/*-----------------------------------------------------------\n* Implementation of functions defined in portable.h for the ARM CM3 port.\n*----------------------------------------------------------*/\n\n/* IAR includes. */\n#include <intrinsics.h>\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n#if ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 )\n    #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\n#endif\n\n/* Constants required to manipulate the core.  Registers first... */\n#define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )\n#define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )\n#define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )\n#define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )\n/* ...then bits in the registers. */\n#define portNVIC_SYSTICK_CLK_BIT              ( 1UL << 2UL )\n#define portNVIC_SYSTICK_INT_BIT              ( 1UL << 1UL )\n#define portNVIC_SYSTICK_ENABLE_BIT           ( 1UL << 0UL )\n#define portNVIC_SYSTICK_COUNT_FLAG_BIT       ( 1UL << 16UL )\n#define portNVIC_PENDSVCLEAR_BIT              ( 1UL << 27UL )\n#define portNVIC_PEND_SYSTICK_SET_BIT         ( 1UL << 26UL )\n#define portNVIC_PEND_SYSTICK_CLEAR_BIT       ( 1UL << 25UL )\n\n#define portNVIC_PENDSV_PRI                   ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\n#define portNVIC_SYSTICK_PRI                  ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\n\n/* Constants required to check the validity of an interrupt priority. */\n#define portFIRST_USER_INTERRUPT_NUMBER       ( 16 )\n#define portNVIC_IP_REGISTERS_OFFSET_16       ( 0xE000E3F0 )\n#define portAIRCR_REG                         ( *( ( volatile uint32_t * ) 0xE000ED0C ) )\n#define portMAX_8_BIT_VALUE                   ( ( uint8_t ) 0xff )\n#define portTOP_BIT_OF_BYTE                   ( ( uint8_t ) 0x80 )\n#define portMAX_PRIGROUP_BITS                 ( ( uint8_t ) 7 )\n#define portPRIORITY_GROUP_MASK               ( 0x07UL << 8UL )\n#define portPRIGROUP_SHIFT                    ( 8UL )\n\n/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */\n#define portVECTACTIVE_MASK                   ( 0xFFUL )\n\n/* Constants required to set up the initial stack. */\n#define portINITIAL_XPSR                      ( 0x01000000 )\n\n/* The systick is a 24-bit counter. */\n#define portMAX_24_BIT_NUMBER                 ( 0xffffffUL )\n\n/* A fiddle factor to estimate the number of SysTick counts that would have\n * occurred while the SysTick counter is stopped during tickless idle\n * calculations. */\n#define portMISSED_COUNTS_FACTOR              ( 94UL )\n\n/* For strict compliance with the Cortex-M spec the task start address should\n * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */\n#define portSTART_ADDRESS_MASK                ( ( StackType_t ) 0xfffffffeUL )\n\n/* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is\n * defined.  The value 255 should also ensure backward compatibility.\n * FreeRTOS.org versions prior to V4.3.0 did not include this definition. */\n#ifndef configKERNEL_INTERRUPT_PRIORITY\n    #define configKERNEL_INTERRUPT_PRIORITY    255\n#endif\n\n/* Let the user override the default SysTick clock rate.  If defined by the\n * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the\n * configuration register. */\n#ifndef configSYSTICK_CLOCK_HZ\n    #define configSYSTICK_CLOCK_HZ             ( configCPU_CLOCK_HZ )\n    /* Ensure the SysTick is clocked at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( portNVIC_SYSTICK_CLK_BIT )\n#else\n    /* Select the option to clock SysTick not at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( 0 )\n#endif\n\n/*\n * Setup the timer to generate the tick interrupts.  The implementation in this\n * file is weak to allow application writers to change the timer used to\n * generate the tick interrupt.\n */\nvoid vPortSetupTimerInterrupt( void );\n\n/*\n * Exception handlers.\n */\nvoid xPortSysTickHandler( void );\n\n/*\n * Start first task is a separate function so it can be tested in isolation.\n */\nextern void vPortStartFirstTask( void );\n\n/*\n * Used to catch tasks that attempt to return from their implementing function.\n */\nstatic void prvTaskExitError( void );\n\n/*-----------------------------------------------------------*/\n\n/* Each task maintains its own interrupt status in the critical nesting\n * variable. */\nstatic UBaseType_t uxCriticalNesting = 0xaaaaaaaa;\n\n/*\n * The number of SysTick increments that make up one tick period.\n */\n#if ( configUSE_TICKLESS_IDLE == 1 )\n    static uint32_t ulTimerCountsForOneTick = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n\n/*\n * The maximum number of tick periods that can be suppressed is limited by the\n * 24 bit resolution of the SysTick timer.\n */\n#if ( configUSE_TICKLESS_IDLE == 1 )\n    static uint32_t xMaximumPossibleSuppressedTicks = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n\n/*\n * Compensate for the CPU cycles that pass while the SysTick is stopped (low\n * power functionality only.\n */\n#if ( configUSE_TICKLESS_IDLE == 1 )\n    static uint32_t ulStoppedTimerCompensation = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n\n/*\n * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure\n * FreeRTOS API functions are not called from interrupts that have been assigned\n * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.\n */\n#if ( configASSERT_DEFINED == 1 )\n    static uint8_t ucMaxSysCallPriority = 0;\n    static uint32_t ulMaxPRIGROUPValue = 0;\n    static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;\n#endif /* configASSERT_DEFINED */\n\n/*-----------------------------------------------------------*/\n\n/*\n * See header file for description.\n */\nStackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,\n                                     TaskFunction_t pxCode,\n                                     void * pvParameters )\n{\n    /* Simulate the stack frame as it would be created by a context switch\n     * interrupt. */\n    pxTopOfStack--;                                                      /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\n    *pxTopOfStack = portINITIAL_XPSR;                                    /* xPSR */\n    pxTopOfStack--;\n    *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */\n    pxTopOfStack--;\n    *pxTopOfStack = ( StackType_t ) prvTaskExitError;                    /* LR */\n    pxTopOfStack -= 5;                                                   /* R12, R3, R2 and R1. */\n    *pxTopOfStack = ( StackType_t ) pvParameters;                        /* R0 */\n    pxTopOfStack -= 8;                                                   /* R11, R10, R9, R8, R7, R6, R5 and R4. */\n\n    return pxTopOfStack;\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvTaskExitError( void )\n{\n    /* A function that implements a task must not exit or attempt to return to\n     * its caller as there is nothing to return to.  If a task wants to exit it\n     * should instead call vTaskDelete( NULL ).\n     *\n     * Artificially force an assert() to be triggered if configASSERT() is\n     * defined, then stop here so application writers can catch the error. */\n    configASSERT( uxCriticalNesting == ~0UL );\n    portDISABLE_INTERRUPTS();\n\n    for( ; ; )\n    {\n    }\n}\n/*-----------------------------------------------------------*/\n\n/*\n * See header file for description.\n */\nBaseType_t xPortStartScheduler( void )\n{\n    /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.\n     * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\n    configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );\n\n    #if ( configASSERT_DEFINED == 1 )\n    {\n        volatile uint32_t ulOriginalPriority;\n        volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\n        volatile uint8_t ucMaxPriorityValue;\n\n        /* Determine the maximum priority from which ISR safe FreeRTOS API\n         * functions can be called.  ISR safe functions are those that end in\n         * \"FromISR\".  FreeRTOS maintains separate thread and ISR API functions to\n         * ensure interrupt entry is as fast and simple as possible.\n         *\n         * Save the interrupt priority value that is about to be clobbered. */\n        ulOriginalPriority = *pucFirstUserPriorityRegister;\n\n        /* Determine the number of priority bits available.  First write to all\n         * possible bits. */\n        *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\n\n        /* Read the value back to see how many bits stuck. */\n        ucMaxPriorityValue = *pucFirstUserPriorityRegister;\n\n        /* Use the same mask on the maximum system call priority. */\n        ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;\n\n        /* Calculate the maximum acceptable priority group value for the number\n         * of bits read back. */\n        ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;\n\n        while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )\n        {\n            ulMaxPRIGROUPValue--;\n            ucMaxPriorityValue <<= ( uint8_t ) 0x01;\n        }\n\n        #ifdef __NVIC_PRIO_BITS\n        {\n            /* Check the CMSIS configuration that defines the number of\n             * priority bits matches the number of priority bits actually queried\n             * from the hardware. */\n            configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );\n        }\n        #endif\n\n        #ifdef configPRIO_BITS\n        {\n            /* Check the FreeRTOS configuration that defines the number of\n             * priority bits matches the number of priority bits actually queried\n             * from the hardware. */\n            configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );\n        }\n        #endif\n\n        /* Shift the priority group value back to its position within the AIRCR\n         * register. */\n        ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;\n        ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;\n\n        /* Restore the clobbered interrupt priority register to its original\n         * value. */\n        *pucFirstUserPriorityRegister = ulOriginalPriority;\n    }\n    #endif /* configASSERT_DEFINED */\n\n    /* Make PendSV and SysTick the lowest priority interrupts. */\n    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;\n    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;\n\n    /* Start the timer that generates the tick ISR.  Interrupts are disabled\n     * here already. */\n    vPortSetupTimerInterrupt();\n\n    /* Initialise the critical nesting count ready for the first task. */\n    uxCriticalNesting = 0;\n\n    /* Start the first task. */\n    vPortStartFirstTask();\n\n    /* Should not get here! */\n    return 0;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEndScheduler( void )\n{\n    /* Not implemented in ports where there is nothing to return to.\n     * Artificially force an assert. */\n    configASSERT( uxCriticalNesting == 1000UL );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEnterCritical( void )\n{\n    portDISABLE_INTERRUPTS();\n    uxCriticalNesting++;\n\n    /* This is not the interrupt safe version of the enter critical function so\n     * assert() if it is being called from an interrupt context.  Only API\n     * functions that end in \"FromISR\" can be used in an interrupt.  Only assert if\n     * the critical nesting count is 1 to protect against recursive calls if the\n     * assert function also uses a critical section. */\n    if( uxCriticalNesting == 1 )\n    {\n        configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );\n    }\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortExitCritical( void )\n{\n    configASSERT( uxCriticalNesting );\n    uxCriticalNesting--;\n\n    if( uxCriticalNesting == 0 )\n    {\n        portENABLE_INTERRUPTS();\n    }\n}\n/*-----------------------------------------------------------*/\n\nvoid xPortSysTickHandler( void )\n{\n    /* The SysTick runs at the lowest interrupt priority, so when this interrupt\n     * executes all interrupts must be unmasked.  There is therefore no need to\n     * save and then restore the interrupt mask value as its value is already\n     * known. */\n    portDISABLE_INTERRUPTS();\n    {\n        /* Increment the RTOS tick. */\n        if( xTaskIncrementTick() != pdFALSE )\n        {\n            /* A context switch is required.  Context switching is performed in\n             * the PendSV interrupt.  Pend the PendSV interrupt. */\n            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\n        }\n    }\n    portENABLE_INTERRUPTS();\n}\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TICKLESS_IDLE == 1 )\n\n    __weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )\n    {\n        uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;\n        TickType_t xModifiableIdleTime;\n\n        /* Make sure the SysTick reload value does not overflow the counter. */\n        if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\n        {\n            xExpectedIdleTime = xMaximumPossibleSuppressedTicks;\n        }\n\n        /* Enter a critical section but don't use the taskENTER_CRITICAL()\n         * method as that will mask interrupts that should exit sleep mode. */\n        __disable_interrupt();\n        __DSB();\n        __ISB();\n\n        /* If a context switch is pending or a task is waiting for the scheduler\n         * to be unsuspended then abandon the low power entry. */\n        if( eTaskConfirmSleepModeStatus() == eAbortSleep )\n        {\n            /* Re-enable interrupts - see comments above the __disable_interrupt()\n             * call above. */\n            __enable_interrupt();\n        }\n        else\n        {\n            /* Stop the SysTick momentarily.  The time the SysTick is stopped for\n             * is accounted for as best it can be, but using the tickless mode will\n             * inevitably result in some tiny drift of the time maintained by the\n             * kernel with respect to calendar time. */\n            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );\n\n            /* Use the SysTick current-value register to determine the number of\n             * SysTick decrements remaining until the next tick interrupt.  If the\n             * current-value register is zero, then there are actually\n             * ulTimerCountsForOneTick decrements remaining, not zero, because the\n             * SysTick requests the interrupt when decrementing from 1 to 0. */\n            ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n\n            if( ulSysTickDecrementsLeft == 0 )\n            {\n                ulSysTickDecrementsLeft = ulTimerCountsForOneTick;\n            }\n\n            /* Calculate the reload value required to wait xExpectedIdleTime\n             * tick periods.  -1 is used because this code normally executes part\n             * way through the first tick period.  But if the SysTick IRQ is now\n             * pending, then clear the IRQ, suppressing the first tick, and correct\n             * the reload value to reflect that the second tick period is already\n             * underway.  The expected idle time is always at least two ticks. */\n            ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );\n\n            if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )\n            {\n                portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;\n                ulReloadValue -= ulTimerCountsForOneTick;\n            }\n\n            if( ulReloadValue > ulStoppedTimerCompensation )\n            {\n                ulReloadValue -= ulStoppedTimerCompensation;\n            }\n\n            /* Set the new reload value. */\n            portNVIC_SYSTICK_LOAD_REG = ulReloadValue;\n\n            /* Clear the SysTick count flag and set the count value back to\n             * zero. */\n            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n            /* Restart SysTick. */\n            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\n\n            /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can\n             * set its parameter to 0 to indicate that its implementation contains\n             * its own wait for interrupt or wait for event instruction, and so wfi\n             * should not be executed again.  However, the original expected idle\n             * time variable must remain unmodified, so a copy is taken. */\n            xModifiableIdleTime = xExpectedIdleTime;\n            configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\n\n            if( xModifiableIdleTime > 0 )\n            {\n                __DSB();\n                __WFI();\n                __ISB();\n            }\n\n            configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\n\n            /* Re-enable interrupts to allow the interrupt that brought the MCU\n             * out of sleep mode to execute immediately.  See comments above\n             * the __disable_interrupt() call above. */\n            __enable_interrupt();\n            __DSB();\n            __ISB();\n\n            /* Disable interrupts again because the clock is about to be stopped\n             * and interrupts that execute while the clock is stopped will increase\n             * any slippage between the time maintained by the RTOS and calendar\n             * time. */\n            __disable_interrupt();\n            __DSB();\n            __ISB();\n\n            /* Disable the SysTick clock without reading the\n             * portNVIC_SYSTICK_CTRL_REG register to ensure the\n             * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,\n             * the time the SysTick is stopped for is accounted for as best it can\n             * be, but using the tickless mode will inevitably result in some tiny\n             * drift of the time maintained by the kernel with respect to calendar\n             * time*/\n            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );\n\n            /* Determine whether the SysTick has already counted to zero. */\n            if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n            {\n                uint32_t ulCalculatedLoadValue;\n\n                /* The tick interrupt ended the sleep (or is now pending), and\n                 * a new tick period has started.  Reset portNVIC_SYSTICK_LOAD_REG\n                 * with whatever remains of the new tick period. */\n                ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\n\n                /* Don't allow a tiny value, or values that have somehow\n                 * underflowed because the post sleep hook did something\n                 * that took too long or because the SysTick current-value register\n                 * is zero. */\n                if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )\n                {\n                    ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );\n                }\n\n                portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;\n\n                /* As the pending tick will be processed as soon as this\n                 * function exits, the tick value maintained by the tick is stepped\n                 * forward by one less than the time spent waiting. */\n                ulCompleteTickPeriods = xExpectedIdleTime - 1UL;\n            }\n            else\n            {\n                /* Something other than the tick interrupt ended the sleep. */\n\n                /* Use the SysTick current-value register to determine the\n                 * number of SysTick decrements remaining until the expected idle\n                 * time would have ended. */\n                ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n                #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )\n                {\n                    /* If the SysTick is not using the core clock, the current-\n                     * value register might still be zero here.  In that case, the\n                     * SysTick didn't load from the reload register, and there are\n                     * ulReloadValue decrements remaining in the expected idle\n                     * time, not zero. */\n                    if( ulSysTickDecrementsLeft == 0 )\n                    {\n                        ulSysTickDecrementsLeft = ulReloadValue;\n                    }\n                }\n                #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */\n\n                /* Work out how long the sleep lasted rounded to complete tick\n                 * periods (not the ulReload value which accounted for part\n                 * ticks). */\n                ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;\n\n                /* How many complete tick periods passed while the processor\n                 * was waiting? */\n                ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;\n\n                /* The reload value is set to whatever fraction of a single tick\n                 * period remains. */\n                portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;\n            }\n\n            /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,\n             * then set portNVIC_SYSTICK_LOAD_REG back to its standard value.  If\n             * the SysTick is not using the core clock, temporarily configure it to\n             * use the core clock.  This configuration forces the SysTick to load\n             * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next\n             * cycle of the other clock.  Then portNVIC_SYSTICK_LOAD_REG is ready\n             * to receive the standard value immediately. */\n            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n            portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n            #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )\n            {\n                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n            }\n            #else\n            {\n                /* The temporary usage of the core clock has served its purpose,\n                 * as described above.  Resume usage of the other clock. */\n                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\n\n                if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n                {\n                    /* The partial tick period already ended.  Be sure the SysTick\n                     * counts it only once. */\n                    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;\n                }\n\n                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n            }\n            #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */\n\n            /* Step the tick to account for any tick periods that elapsed. */\n            vTaskStepTick( ulCompleteTickPeriods );\n\n            /* Exit with interrupts enabled. */\n            __enable_interrupt();\n        }\n    }\n\n#endif /* configUSE_TICKLESS_IDLE */\n/*-----------------------------------------------------------*/\n\n/*\n * Setup the systick timer to generate the tick interrupts at the required\n * frequency.\n */\n__weak void vPortSetupTimerInterrupt( void )\n{\n    /* Calculate the constants required to configure the tick interrupt. */\n    #if ( configUSE_TICKLESS_IDLE == 1 )\n    {\n        ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );\n        xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;\n        ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\n    }\n    #endif /* configUSE_TICKLESS_IDLE */\n\n    /* Stop and clear the SysTick. */\n    portNVIC_SYSTICK_CTRL_REG = 0UL;\n    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n    /* Configure SysTick to interrupt at the requested rate. */\n    portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\n    portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );\n}\n/*-----------------------------------------------------------*/\n\n#if ( configASSERT_DEFINED == 1 )\n\n    void vPortValidateInterruptPriority( void )\n    {\n        uint32_t ulCurrentInterrupt;\n        uint8_t ucCurrentPriority;\n\n        /* Obtain the number of the currently executing interrupt. */\n        __asm volatile ( \"mrs %0, ipsr\" : \"=r\" ( ulCurrentInterrupt )::\"memory\" );\n\n        /* Is the interrupt number a user defined interrupt? */\n        if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )\n        {\n            /* Look up the interrupt's priority. */\n            ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];\n\n            /* The following assertion will fail if a service routine (ISR) for\n             * an interrupt that has been assigned a priority above\n             * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\n             * function.  ISR safe FreeRTOS API functions must *only* be called\n             * from interrupts that have been assigned a priority at or below\n             * configMAX_SYSCALL_INTERRUPT_PRIORITY.\n             *\n             * Numerically low interrupt priority numbers represent logically high\n             * interrupt priorities, therefore the priority of the interrupt must\n             * be set to a value equal to or numerically *higher* than\n             * configMAX_SYSCALL_INTERRUPT_PRIORITY.\n             *\n             * Interrupts that\tuse the FreeRTOS API must not be left at their\n             * default priority of\tzero as that is the highest possible priority,\n             * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,\n             * and\ttherefore also guaranteed to be invalid.\n             *\n             * FreeRTOS maintains separate thread and ISR API functions to ensure\n             * interrupt entry is as fast and simple as possible.\n             *\n             * The following links provide detailed information:\n             * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html\n             * https://www.FreeRTOS.org/FAQHelp.html */\n            configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );\n        }\n\n        /* Priority grouping:  The interrupt controller (NVIC) allows the bits\n         * that define each interrupt's priority to be split between bits that\n         * define the interrupt's pre-emption priority bits and bits that define\n         * the interrupt's sub-priority.  For simplicity all bits must be defined\n         * to be pre-emption priority bits.  The following assertion will fail if\n         * this is not the case (if some bits represent a sub-priority).\n         *\n         * If the application only uses CMSIS libraries for interrupt\n         * configuration then the correct setting can be achieved on all Cortex-M\n         * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the\n         * scheduler.  Note however that some vendor specific peripheral libraries\n         * assume a non-zero priority group setting, in which cases using a value\n         * of zero will result in unpredictable behaviour. */\n        configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );\n    }\n\n#endif /* configASSERT_DEFINED */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM3/portasm.s",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#include <FreeRTOSConfig.h>\n\n\tRSEG    CODE:CODE(2)\n\tthumb\n\n\tEXTERN pxCurrentTCB\n\tEXTERN vTaskSwitchContext\n\n\tPUBLIC xPortPendSVHandler\n\tPUBLIC vPortSVCHandler\n\tPUBLIC vPortStartFirstTask\n\n\n\n/*-----------------------------------------------------------*/\n\nxPortPendSVHandler:\n\tmrs r0, psp\n\tisb\n\tldr\tr3, =pxCurrentTCB\t\t\t/* Get the location of the current TCB. */\n\tldr\tr2, [r3]\n\n\tstmdb r0!, {r4-r11}\t\t\t\t/* Save the remaining registers. */\n\tstr r0, [r2]\t\t\t\t\t/* Save the new top of stack into the first member of the TCB. */\n\n\tstmdb sp!, {r3, r14}\n\tmov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY\n\tmsr basepri, r0\n\tdsb\n\tisb\n\tbl vTaskSwitchContext\n\tmov r0, #0\n\tmsr basepri, r0\n\tldmia sp!, {r3, r14}\n\n\tldr r1, [r3]\n\tldr r0, [r1]\t\t\t\t\t/* The first item in pxCurrentTCB is the task top of stack. */\n\tldmia r0!, {r4-r11}\t\t\t\t/* Pop the registers. */\n\tmsr psp, r0\n\tisb\n\tbx r14\n\n\n/*-----------------------------------------------------------*/\n\nvPortSVCHandler:\n\t/* Get the location of the current TCB. */\n\tldr\tr3, =pxCurrentTCB\n\tldr r1, [r3]\n\tldr r0, [r1]\n\t/* Pop the core registers. */\n\tldmia r0!, {r4-r11}\n\tmsr psp, r0\n\tisb\n\tmov r0, #0\n\tmsr\tbasepri, r0\n\torr r14, r14, #13\n\tbx r14\n\n/*-----------------------------------------------------------*/\n\nvPortStartFirstTask\n\t/* Use the NVIC offset register to locate the stack. */\n\tldr r0, =0xE000ED08\n\tldr r0, [r0]\n\tldr r0, [r0]\n\t/* Set the msp back to the start of the stack. */\n\tmsr msp, r0\n\t/* Call SVC to start the first task, ensuring interrupts are enabled. */\n\tcpsie i\n\tcpsie f\n\tdsb\n\tisb\n\tsvc 0\n\n\tEND\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM3/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n\n#ifndef PORTMACRO_H\n    #define PORTMACRO_H\n\n    #ifdef __cplusplus\n        extern \"C\" {\n    #endif\n\n/*-----------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the\n * given hardware and compiler.\n *\n * These settings should not be altered.\n *-----------------------------------------------------------\n */\n\n/* IAR includes. */\n    #include <intrinsics.h>\n\n/* Type definitions. */\n    #define portCHAR          char\n    #define portFLOAT         float\n    #define portDOUBLE        double\n    #define portLONG          long\n    #define portSHORT         short\n    #define portSTACK_TYPE    uint32_t\n    #define portBASE_TYPE     long\n\n    typedef portSTACK_TYPE   StackType_t;\n    typedef long             BaseType_t;\n    typedef unsigned long    UBaseType_t;\n\n    #if ( configUSE_16_BIT_TICKS == 1 )\n        typedef uint16_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffff\n    #else\n        typedef uint32_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL\n\n/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\n * not need to be guarded with a critical section. */\n        #define portTICK_TYPE_IS_ATOMIC    1\n    #endif\n/*-----------------------------------------------------------*/\n\n/* Architecture specifics. */\n    #define portSTACK_GROWTH      ( -1 )\n    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\n    #define portBYTE_ALIGNMENT    8\n/*-----------------------------------------------------------*/\n\n/* Compiler directives. */\n    #define portWEAK_SYMBOL    __attribute__( ( weak ) )\n\n/*-----------------------------------------------------------*/\n\n\n/* Scheduler utilities. */\n    #define portYIELD()                                 \\\n    {                                                   \\\n        /* Set a PendSV to request a context switch. */ \\\n        portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \\\n        __DSB();                                        \\\n        __ISB();                                        \\\n    }\n\n    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )\n    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )\n    #define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 )\n    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )\n\n/*-----------------------------------------------------------*/\n\n/* Architecture specific optimisations. */\n    #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION\n        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1\n    #endif\n\n    #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )\n\n/* Check the configuration. */\n        #if ( configMAX_PRIORITIES > 32 )\n            #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.\n        #endif\n\n/* Store/clear the ready priorities in a bit map. */\n        #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )\n        #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )\n\n/*-----------------------------------------------------------*/\n\n        #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ( ( uint32_t ) __CLZ( ( uxReadyPriorities ) ) ) )\n\n    #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */\n/*-----------------------------------------------------------*/\n\n/* Critical section management. */\n    extern void vPortEnterCritical( void );\n    extern void vPortExitCritical( void );\n\n    #define portDISABLE_INTERRUPTS()                           \\\n    {                                                          \\\n        __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \\\n        __DSB();                                               \\\n        __ISB();                                               \\\n    }\n\n    #define portENABLE_INTERRUPTS()                   __set_BASEPRI( 0 )\n    #define portENTER_CRITICAL()                      vPortEnterCritical()\n    #define portEXIT_CRITICAL()                       vPortExitCritical()\n    #define portSET_INTERRUPT_MASK_FROM_ISR()         __get_BASEPRI(); portDISABLE_INTERRUPTS()\n    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    __set_BASEPRI( x )\n/*-----------------------------------------------------------*/\n\n/* Tickless idle/low power functionality. */\n    #ifndef portSUPPRESS_TICKS_AND_SLEEP\n        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );\n        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )\n    #endif\n\n/*-----------------------------------------------------------*/\n\n/* Task function macros as described on the FreeRTOS.org WEB site.  These are\n * not necessary for to use this port.  They are defined so the common demo files\n * (which build with all the ports) will build. */\n    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )\n    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )\n/*-----------------------------------------------------------*/\n\n    #ifdef configASSERT\n        void vPortValidateInterruptPriority( void );\n        #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()\n    #endif\n\n/* portNOP() is not required by this port. */\n    #define portNOP()\n\n    #define portINLINE              __inline\n\n    #ifndef portFORCE_INLINE\n        #define portFORCE_INLINE    inline __attribute__( ( always_inline ) )\n    #endif\n\n/*-----------------------------------------------------------*/\n\n    portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )\n    {\n        uint32_t ulCurrentInterrupt;\n        BaseType_t xReturn;\n\n        /* Obtain the number of the currently executing interrupt. */\n        __asm volatile ( \"mrs %0, ipsr\" : \"=r\" ( ulCurrentInterrupt )::\"memory\" );\n\n        if( ulCurrentInterrupt == 0 )\n        {\n            xReturn = pdFALSE;\n        }\n        else\n        {\n            xReturn = pdTRUE;\n        }\n\n        return xReturn;\n    }\n\n/*-----------------------------------------------------------*/\n\n/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in\n * the source code because to do so would cause other compilers to generate\n * warnings. */\n    #pragma diag_suppress=Pe191\n    #pragma diag_suppress=Pa082\n\n    #ifdef __cplusplus\n        }\n    #endif\n\n#endif /* PORTMACRO_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM33/non_secure/port.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\n * all the API functions to use the MPU wrappers. That should only be done when\n * task.h is included from an application file. */\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n/* MPU wrappers includes. */\n#include \"mpu_wrappers.h\"\n\n/* Portasm includes. */\n#include \"portasm.h\"\n\n#if ( configENABLE_TRUSTZONE == 1 )\n    /* Secure components includes. */\n    #include \"secure_context.h\"\n    #include \"secure_init.h\"\n#endif /* configENABLE_TRUSTZONE */\n\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/**\n * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only\n * i.e. the processor boots as secure and never jumps to the non-secure side.\n * The Trust Zone support in the port must be disabled in order to run FreeRTOS\n * on the secure side. The following are the valid configuration seetings:\n *\n * 1. Run FreeRTOS on the Secure Side:\n *    configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0\n *\n * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:\n *    configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1\n *\n * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:\n *    configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0\n */\n#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )\n    #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.\n#endif\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the NVIC.\n */\n#define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )\n#define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )\n#define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )\n#define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )\n#define portNVIC_SYSTICK_ENABLE_BIT           ( 1UL << 0UL )\n#define portNVIC_SYSTICK_INT_BIT              ( 1UL << 1UL )\n#define portNVIC_SYSTICK_CLK_BIT              ( 1UL << 2UL )\n#define portNVIC_SYSTICK_COUNT_FLAG_BIT       ( 1UL << 16UL )\n#define portNVIC_PEND_SYSTICK_CLEAR_BIT       ( 1UL << 25UL )\n#define portNVIC_PEND_SYSTICK_SET_BIT         ( 1UL << 26UL )\n#define portMIN_INTERRUPT_PRIORITY            ( 255UL )\n#define portNVIC_PENDSV_PRI                   ( portMIN_INTERRUPT_PRIORITY << 16UL )\n#define portNVIC_SYSTICK_PRI                  ( portMIN_INTERRUPT_PRIORITY << 24UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the SCB.\n */\n#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( volatile uint32_t * ) 0xe000ed24 )\n#define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the FPU.\n */\n#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 )              /* Coprocessor Access Control Register. */\n#define portCPACR_CP10_VALUE    ( 3UL )\n#define portCPACR_CP11_VALUE    portCPACR_CP10_VALUE\n#define portCPACR_CP10_POS      ( 20UL )\n#define portCPACR_CP11_POS      ( 22UL )\n\n#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 )              /* Floating Point Context Control Register. */\n#define portFPCCR_ASPEN_POS     ( 31UL )\n#define portFPCCR_ASPEN_MASK    ( 1UL << portFPCCR_ASPEN_POS )\n#define portFPCCR_LSPEN_POS     ( 30UL )\n#define portFPCCR_LSPEN_MASK    ( 1UL << portFPCCR_LSPEN_POS )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the MPU.\n */\n#define portMPU_TYPE_REG                      ( *( ( volatile uint32_t * ) 0xe000ed90 ) )\n#define portMPU_CTRL_REG                      ( *( ( volatile uint32_t * ) 0xe000ed94 ) )\n#define portMPU_RNR_REG                       ( *( ( volatile uint32_t * ) 0xe000ed98 ) )\n\n#define portMPU_RBAR_REG                      ( *( ( volatile uint32_t * ) 0xe000ed9c ) )\n#define portMPU_RLAR_REG                      ( *( ( volatile uint32_t * ) 0xe000eda0 ) )\n\n#define portMPU_RBAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda4 ) )\n#define portMPU_RLAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda8 ) )\n\n#define portMPU_RBAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edac ) )\n#define portMPU_RLAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edb0 ) )\n\n#define portMPU_RBAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb4 ) )\n#define portMPU_RLAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb8 ) )\n\n#define portMPU_MAIR0_REG                     ( *( ( volatile uint32_t * ) 0xe000edc0 ) )\n#define portMPU_MAIR1_REG                     ( *( ( volatile uint32_t * ) 0xe000edc4 ) )\n\n#define portMPU_RBAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */\n#define portMPU_RLAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */\n\n#define portMPU_MAIR_ATTR0_POS                ( 0UL )\n#define portMPU_MAIR_ATTR0_MASK               ( 0x000000ff )\n\n#define portMPU_MAIR_ATTR1_POS                ( 8UL )\n#define portMPU_MAIR_ATTR1_MASK               ( 0x0000ff00 )\n\n#define portMPU_MAIR_ATTR2_POS                ( 16UL )\n#define portMPU_MAIR_ATTR2_MASK               ( 0x00ff0000 )\n\n#define portMPU_MAIR_ATTR3_POS                ( 24UL )\n#define portMPU_MAIR_ATTR3_MASK               ( 0xff000000 )\n\n#define portMPU_MAIR_ATTR4_POS                ( 0UL )\n#define portMPU_MAIR_ATTR4_MASK               ( 0x000000ff )\n\n#define portMPU_MAIR_ATTR5_POS                ( 8UL )\n#define portMPU_MAIR_ATTR5_MASK               ( 0x0000ff00 )\n\n#define portMPU_MAIR_ATTR6_POS                ( 16UL )\n#define portMPU_MAIR_ATTR6_MASK               ( 0x00ff0000 )\n\n#define portMPU_MAIR_ATTR7_POS                ( 24UL )\n#define portMPU_MAIR_ATTR7_MASK               ( 0xff000000 )\n\n#define portMPU_RLAR_ATTR_INDEX0              ( 0UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX1              ( 1UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX2              ( 2UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX3              ( 3UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX4              ( 4UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX5              ( 5UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX6              ( 6UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX7              ( 7UL << 1UL )\n\n#define portMPU_RLAR_REGION_ENABLE            ( 1UL )\n\n/* Enable privileged access to unmapped region. */\n#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )\n\n/* Enable MPU. */\n#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )\n\n/* Expected value of the portMPU_TYPE register. */\n#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief The maximum 24-bit number.\n *\n * It is needed because the systick is a 24-bit counter.\n */\n#define portMAX_24_BIT_NUMBER       ( 0xffffffUL )\n\n/**\n * @brief A fiddle factor to estimate the number of SysTick counts that would\n * have occurred while the SysTick counter is stopped during tickless idle\n * calculations.\n */\n#define portMISSED_COUNTS_FACTOR    ( 94UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to set up the initial stack.\n */\n#define portINITIAL_XPSR    ( 0x01000000 )\n\n#if ( configRUN_FREERTOS_SECURE_ONLY == 1 )\n\n/**\n * @brief Initial EXC_RETURN value.\n *\n *     FF         FF         FF         FD\n * 1111 1111  1111 1111  1111 1111  1111 1101\n *\n * Bit[6] - 1 --> The exception was taken from the Secure state.\n * Bit[5] - 1 --> Do not skip stacking of additional state context.\n * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\n * Bit[3] - 1 --> Return to the Thread mode.\n * Bit[2] - 1 --> Restore registers from the process stack.\n * Bit[1] - 0 --> Reserved, 0.\n * Bit[0] - 1 --> The exception was taken to the Secure state.\n */\n    #define portINITIAL_EXC_RETURN    ( 0xfffffffd )\n#else\n\n/**\n * @brief Initial EXC_RETURN value.\n *\n *     FF         FF         FF         BC\n * 1111 1111  1111 1111  1111 1111  1011 1100\n *\n * Bit[6] - 0 --> The exception was taken from the Non-Secure state.\n * Bit[5] - 1 --> Do not skip stacking of additional state context.\n * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\n * Bit[3] - 1 --> Return to the Thread mode.\n * Bit[2] - 1 --> Restore registers from the process stack.\n * Bit[1] - 0 --> Reserved, 0.\n * Bit[0] - 0 --> The exception was taken to the Non-Secure state.\n */\n    #define portINITIAL_EXC_RETURN    ( 0xffffffbc )\n#endif /* configRUN_FREERTOS_SECURE_ONLY */\n\n/**\n * @brief CONTROL register privileged bit mask.\n *\n * Bit[0] in CONTROL register tells the privilege:\n *  Bit[0] = 0 ==> The task is privileged.\n *  Bit[0] = 1 ==> The task is not privileged.\n */\n#define portCONTROL_PRIVILEGED_MASK         ( 1UL << 0UL )\n\n/**\n * @brief Initial CONTROL register values.\n */\n#define portINITIAL_CONTROL_UNPRIVILEGED    ( 0x3 )\n#define portINITIAL_CONTROL_PRIVILEGED      ( 0x2 )\n\n/**\n * @brief Let the user override the default SysTick clock rate.  If defined by the\n * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the\n * configuration register.\n */\n#ifndef configSYSTICK_CLOCK_HZ\n    #define configSYSTICK_CLOCK_HZ             ( configCPU_CLOCK_HZ )\n    /* Ensure the SysTick is clocked at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( portNVIC_SYSTICK_CLK_BIT )\n#else\n    /* Select the option to clock SysTick not at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( 0 )\n#endif\n\n/**\n * @brief Let the user override the pre-loading of the initial LR with the\n * address of prvTaskExitError() in case it messes up unwinding of the stack\n * in the debugger.\n */\n#ifdef configTASK_RETURN_ADDRESS\n    #define portTASK_RETURN_ADDRESS    configTASK_RETURN_ADDRESS\n#else\n    #define portTASK_RETURN_ADDRESS    prvTaskExitError\n#endif\n\n/**\n * @brief If portPRELOAD_REGISTERS then registers will be given an initial value\n * when a task is created. This helps in debugging at the cost of code size.\n */\n#define portPRELOAD_REGISTERS    1\n\n/**\n * @brief A task is created without a secure context, and must call\n * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes\n * any secure calls.\n */\n#define portNO_SECURE_CONTEXT    0\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Used to catch tasks that attempt to return from their implementing\n * function.\n */\nstatic void prvTaskExitError( void );\n\n#if ( configENABLE_MPU == 1 )\n\n/**\n * @brief Setup the Memory Protection Unit (MPU).\n */\n    static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\n#endif /* configENABLE_MPU */\n\n#if ( configENABLE_FPU == 1 )\n\n/**\n * @brief Setup the Floating Point Unit (FPU).\n */\n    static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;\n#endif /* configENABLE_FPU */\n\n/**\n * @brief Setup the timer to generate the tick interrupts.\n *\n * The implementation in this file is weak to allow application writers to\n * change the timer used to generate the tick interrupt.\n */\nvoid vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Checks whether the current execution context is interrupt.\n *\n * @return pdTRUE if the current execution context is interrupt, pdFALSE\n * otherwise.\n */\nBaseType_t xPortIsInsideInterrupt( void );\n\n/**\n * @brief Yield the processor.\n */\nvoid vPortYield( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Enter critical section.\n */\nvoid vPortEnterCritical( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Exit from critical section.\n */\nvoid vPortExitCritical( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief SysTick handler.\n */\nvoid SysTick_Handler( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief C part of SVC handler.\n */\nportDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION;\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Each task maintains its own interrupt status in the critical nesting\n * variable.\n */\nPRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;\n\n#if ( configENABLE_TRUSTZONE == 1 )\n\n/**\n * @brief Saved as part of the task context to indicate which context the\n * task is using on the secure side.\n */\n    PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;\n#endif /* configENABLE_TRUSTZONE */\n\n#if ( configUSE_TICKLESS_IDLE == 1 )\n\n/**\n * @brief The number of SysTick increments that make up one tick period.\n */\n    PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0;\n\n/**\n * @brief The maximum number of tick periods that can be suppressed is\n * limited by the 24 bit resolution of the SysTick timer.\n */\n    PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0;\n\n/**\n * @brief Compensate for the CPU cycles that pass while the SysTick is\n * stopped (low power functionality only).\n */\n    PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TICKLESS_IDLE == 1 )\n    __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )\n    {\n        uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;\n        TickType_t xModifiableIdleTime;\n\n        /* Make sure the SysTick reload value does not overflow the counter. */\n        if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\n        {\n            xExpectedIdleTime = xMaximumPossibleSuppressedTicks;\n        }\n\n        /* Enter a critical section but don't use the taskENTER_CRITICAL()\n         * method as that will mask interrupts that should exit sleep mode. */\n        __asm volatile ( \"cpsid i\" ::: \"memory\" );\n        __asm volatile ( \"dsb\" );\n        __asm volatile ( \"isb\" );\n\n        /* If a context switch is pending or a task is waiting for the scheduler\n         * to be unsuspended then abandon the low power entry. */\n        if( eTaskConfirmSleepModeStatus() == eAbortSleep )\n        {\n            /* Re-enable interrupts - see comments above the cpsid instruction\n             * above. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n        }\n        else\n        {\n            /* Stop the SysTick momentarily.  The time the SysTick is stopped for\n             * is accounted for as best it can be, but using the tickless mode will\n             * inevitably result in some tiny drift of the time maintained by the\n             * kernel with respect to calendar time. */\n            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );\n\n            /* Use the SysTick current-value register to determine the number of\n             * SysTick decrements remaining until the next tick interrupt.  If the\n             * current-value register is zero, then there are actually\n             * ulTimerCountsForOneTick decrements remaining, not zero, because the\n             * SysTick requests the interrupt when decrementing from 1 to 0. */\n            ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n\n            if( ulSysTickDecrementsLeft == 0 )\n            {\n                ulSysTickDecrementsLeft = ulTimerCountsForOneTick;\n            }\n\n            /* Calculate the reload value required to wait xExpectedIdleTime\n             * tick periods.  -1 is used because this code normally executes part\n             * way through the first tick period.  But if the SysTick IRQ is now\n             * pending, then clear the IRQ, suppressing the first tick, and correct\n             * the reload value to reflect that the second tick period is already\n             * underway.  The expected idle time is always at least two ticks. */\n            ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );\n\n            if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )\n            {\n                portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;\n                ulReloadValue -= ulTimerCountsForOneTick;\n            }\n\n            if( ulReloadValue > ulStoppedTimerCompensation )\n            {\n                ulReloadValue -= ulStoppedTimerCompensation;\n            }\n\n            /* Set the new reload value. */\n            portNVIC_SYSTICK_LOAD_REG = ulReloadValue;\n\n            /* Clear the SysTick count flag and set the count value back to\n             * zero. */\n            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n            /* Restart SysTick. */\n            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\n\n            /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can\n             * set its parameter to 0 to indicate that its implementation contains\n             * its own wait for interrupt or wait for event instruction, and so wfi\n             * should not be executed again.  However, the original expected idle\n             * time variable must remain unmodified, so a copy is taken. */\n            xModifiableIdleTime = xExpectedIdleTime;\n            configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\n\n            if( xModifiableIdleTime > 0 )\n            {\n                __asm volatile ( \"dsb\" ::: \"memory\" );\n                __asm volatile ( \"wfi\" );\n                __asm volatile ( \"isb\" );\n            }\n\n            configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\n\n            /* Re-enable interrupts to allow the interrupt that brought the MCU\n             * out of sleep mode to execute immediately.  See comments above\n             * the cpsid instruction above. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n            __asm volatile ( \"dsb\" );\n            __asm volatile ( \"isb\" );\n\n            /* Disable interrupts again because the clock is about to be stopped\n             * and interrupts that execute while the clock is stopped will increase\n             * any slippage between the time maintained by the RTOS and calendar\n             * time. */\n            __asm volatile ( \"cpsid i\" ::: \"memory\" );\n            __asm volatile ( \"dsb\" );\n            __asm volatile ( \"isb\" );\n\n            /* Disable the SysTick clock without reading the\n             * portNVIC_SYSTICK_CTRL_REG register to ensure the\n             * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,\n             * the time the SysTick is stopped for is accounted for as best it can\n             * be, but using the tickless mode will inevitably result in some tiny\n             * drift of the time maintained by the kernel with respect to calendar\n             * time*/\n            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );\n\n            /* Determine whether the SysTick has already counted to zero. */\n            if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n            {\n                uint32_t ulCalculatedLoadValue;\n\n                /* The tick interrupt ended the sleep (or is now pending), and\n                 * a new tick period has started.  Reset portNVIC_SYSTICK_LOAD_REG\n                 * with whatever remains of the new tick period. */\n                ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\n\n                /* Don't allow a tiny value, or values that have somehow\n                 * underflowed because the post sleep hook did something\n                 * that took too long or because the SysTick current-value register\n                 * is zero. */\n                if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )\n                {\n                    ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );\n                }\n\n                portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;\n\n                /* As the pending tick will be processed as soon as this\n                 * function exits, the tick value maintained by the tick is stepped\n                 * forward by one less than the time spent waiting. */\n                ulCompleteTickPeriods = xExpectedIdleTime - 1UL;\n            }\n            else\n            {\n                /* Something other than the tick interrupt ended the sleep. */\n\n                /* Use the SysTick current-value register to determine the\n                 * number of SysTick decrements remaining until the expected idle\n                 * time would have ended. */\n                ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n                #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )\n                {\n                    /* If the SysTick is not using the core clock, the current-\n                     * value register might still be zero here.  In that case, the\n                     * SysTick didn't load from the reload register, and there are\n                     * ulReloadValue decrements remaining in the expected idle\n                     * time, not zero. */\n                    if( ulSysTickDecrementsLeft == 0 )\n                    {\n                        ulSysTickDecrementsLeft = ulReloadValue;\n                    }\n                }\n                #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */\n\n                /* Work out how long the sleep lasted rounded to complete tick\n                 * periods (not the ulReload value which accounted for part\n                 * ticks). */\n                ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;\n\n                /* How many complete tick periods passed while the processor\n                 * was waiting? */\n                ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;\n\n                /* The reload value is set to whatever fraction of a single tick\n                 * period remains. */\n                portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;\n            }\n\n            /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,\n             * then set portNVIC_SYSTICK_LOAD_REG back to its standard value.  If\n             * the SysTick is not using the core clock, temporarily configure it to\n             * use the core clock.  This configuration forces the SysTick to load\n             * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next\n             * cycle of the other clock.  Then portNVIC_SYSTICK_LOAD_REG is ready\n             * to receive the standard value immediately. */\n            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n            portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n            #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )\n            {\n                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n            }\n            #else\n            {\n                /* The temporary usage of the core clock has served its purpose,\n                 * as described above.  Resume usage of the other clock. */\n                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\n\n                if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n                {\n                    /* The partial tick period already ended.  Be sure the SysTick\n                     * counts it only once. */\n                    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;\n                }\n\n                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n            }\n            #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */\n\n            /* Step the tick to account for any tick periods that elapsed. */\n            vTaskStepTick( ulCompleteTickPeriods );\n\n            /* Exit with interrupts enabled. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n        }\n    }\n#endif /* configUSE_TICKLESS_IDLE */\n/*-----------------------------------------------------------*/\n\n__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Calculate the constants required to configure the tick interrupt. */\n    #if ( configUSE_TICKLESS_IDLE == 1 )\n    {\n        ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );\n        xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;\n        ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\n    }\n    #endif /* configUSE_TICKLESS_IDLE */\n\n    /* Stop and reset the SysTick. */\n    portNVIC_SYSTICK_CTRL_REG = 0UL;\n    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n    /* Configure SysTick to interrupt at the requested rate. */\n    portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\n    portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvTaskExitError( void )\n{\n    volatile uint32_t ulDummy = 0UL;\n\n    /* A function that implements a task must not exit or attempt to return to\n     * its caller as there is nothing to return to. If a task wants to exit it\n     * should instead call vTaskDelete( NULL ). Artificially force an assert()\n     * to be triggered if configASSERT() is defined, then stop here so\n     * application writers can catch the error. */\n    configASSERT( ulCriticalNesting == ~0UL );\n    portDISABLE_INTERRUPTS();\n\n    while( ulDummy == 0 )\n    {\n        /* This file calls prvTaskExitError() after the scheduler has been\n         * started to remove a compiler warning about the function being\n         * defined but never called.  ulDummy is used purely to quieten other\n         * warnings about code appearing after this function is called - making\n         * ulDummy volatile makes the compiler think the function could return\n         * and therefore not output an 'unreachable code' warning for code that\n         * appears after it. */\n    }\n}\n/*-----------------------------------------------------------*/\n\n#if ( configENABLE_MPU == 1 )\n    static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */\n    {\n        #if defined( __ARMCC_VERSION )\n\n            /* Declaration when these variable are defined in code instead of being\n             * exported from linker scripts. */\n            extern uint32_t * __privileged_functions_start__;\n            extern uint32_t * __privileged_functions_end__;\n            extern uint32_t * __syscalls_flash_start__;\n            extern uint32_t * __syscalls_flash_end__;\n            extern uint32_t * __unprivileged_flash_start__;\n            extern uint32_t * __unprivileged_flash_end__;\n            extern uint32_t * __privileged_sram_start__;\n            extern uint32_t * __privileged_sram_end__;\n        #else /* if defined( __ARMCC_VERSION ) */\n            /* Declaration when these variable are exported from linker scripts. */\n            extern uint32_t __privileged_functions_start__[];\n            extern uint32_t __privileged_functions_end__[];\n            extern uint32_t __syscalls_flash_start__[];\n            extern uint32_t __syscalls_flash_end__[];\n            extern uint32_t __unprivileged_flash_start__[];\n            extern uint32_t __unprivileged_flash_end__[];\n            extern uint32_t __privileged_sram_start__[];\n            extern uint32_t __privileged_sram_end__[];\n        #endif /* defined( __ARMCC_VERSION ) */\n\n        /* The only permitted number of regions are 8 or 16. */\n        configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );\n\n        /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */\n        configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );\n\n        /* Check that the MPU is present. */\n        if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )\n        {\n            /* MAIR0 - Index 0. */\n            portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\n            /* MAIR0 - Index 1. */\n            portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\n\n            /* Setup privileged flash as Read Only so that privileged tasks can\n             * read it but not modify. */\n            portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_PRIVILEGED_READ_ONLY );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Setup unprivileged flash as Read Only by both privileged and\n             * unprivileged tasks. All tasks can read it but no-one can modify. */\n            portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_READ_ONLY );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Setup unprivileged syscalls flash as Read Only by both privileged\n             * and unprivileged tasks. All tasks can read it but no-one can modify. */\n            portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_READ_ONLY );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Setup RAM containing kernel data for privileged access only. */\n            portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\n                               ( portMPU_REGION_EXECUTE_NEVER );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Enable mem fault. */\n            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;\n\n            /* Enable MPU with privileged background access i.e. unmapped\n             * regions have privileged access. */\n            portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );\n        }\n    }\n#endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\n#if ( configENABLE_FPU == 1 )\n    static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */\n    {\n        #if ( configENABLE_TRUSTZONE == 1 )\n        {\n            /* Enable non-secure access to the FPU. */\n            SecureInit_EnableNSFPUAccess();\n        }\n        #endif /* configENABLE_TRUSTZONE */\n\n        /* CP10 = 11 ==> Full access to FPU i.e. both privileged and\n         * unprivileged code should be able to access FPU. CP11 should be\n         * programmed to the same value as CP10. */\n        *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |\n                            ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )\n                            );\n\n        /* ASPEN = 1 ==> Hardware should automatically preserve floating point\n         * context on exception entry and restore on exception return.\n         * LSPEN = 1 ==> Enable lazy context save of FP state. */\n        *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );\n    }\n#endif /* configENABLE_FPU */\n/*-----------------------------------------------------------*/\n\nvoid vPortYield( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Set a PendSV to request a context switch. */\n    portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\n\n    /* Barriers are normally not required but do ensure the code is\n     * completely within the specified behaviour for the architecture. */\n    __asm volatile ( \"dsb\" ::: \"memory\" );\n    __asm volatile ( \"isb\" );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */\n{\n    portDISABLE_INTERRUPTS();\n    ulCriticalNesting++;\n\n    /* Barriers are normally not required but do ensure the code is\n     * completely within the specified behaviour for the architecture. */\n    __asm volatile ( \"dsb\" ::: \"memory\" );\n    __asm volatile ( \"isb\" );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */\n{\n    configASSERT( ulCriticalNesting );\n    ulCriticalNesting--;\n\n    if( ulCriticalNesting == 0 )\n    {\n        portENABLE_INTERRUPTS();\n    }\n}\n/*-----------------------------------------------------------*/\n\nvoid SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */\n{\n    uint32_t ulPreviousMask;\n\n    ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();\n    {\n        /* Increment the RTOS tick. */\n        if( xTaskIncrementTick() != pdFALSE )\n        {\n            /* Pend a context switch. */\n            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\n        }\n    }\n    portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */\n{\n    #if ( configENABLE_MPU == 1 )\n        #if defined( __ARMCC_VERSION )\n\n            /* Declaration when these variable are defined in code instead of being\n             * exported from linker scripts. */\n            extern uint32_t * __syscalls_flash_start__;\n            extern uint32_t * __syscalls_flash_end__;\n        #else\n            /* Declaration when these variable are exported from linker scripts. */\n            extern uint32_t __syscalls_flash_start__[];\n            extern uint32_t __syscalls_flash_end__[];\n        #endif /* defined( __ARMCC_VERSION ) */\n    #endif /* configENABLE_MPU */\n\n    uint32_t ulPC;\n\n    #if ( configENABLE_TRUSTZONE == 1 )\n        uint32_t ulR0, ulR1;\n        extern TaskHandle_t pxCurrentTCB;\n        #if ( configENABLE_MPU == 1 )\n            uint32_t ulControl, ulIsTaskPrivileged;\n        #endif /* configENABLE_MPU */\n    #endif /* configENABLE_TRUSTZONE */\n    uint8_t ucSVCNumber;\n\n    /* Register are stored on the stack in the following order - R0, R1, R2, R3,\n     * R12, LR, PC, xPSR. */\n    ulPC = pulCallerStackAddress[ 6 ];\n    ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];\n\n    switch( ucSVCNumber )\n    {\n        #if ( configENABLE_TRUSTZONE == 1 )\n            case portSVC_ALLOCATE_SECURE_CONTEXT:\n\n                /* R0 contains the stack size passed as parameter to the\n                 * vPortAllocateSecureContext function. */\n                ulR0 = pulCallerStackAddress[ 0 ];\n\n                #if ( configENABLE_MPU == 1 )\n                {\n                    /* Read the CONTROL register value. */\n                    __asm volatile ( \"mrs %0, control\"  : \"=r\" ( ulControl ) );\n\n                    /* The task that raised the SVC is privileged if Bit[0]\n                     * in the CONTROL register is 0. */\n                    ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );\n\n                    /* Allocate and load a context for the secure task. */\n                    xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );\n                }\n                #else /* if ( configENABLE_MPU == 1 ) */\n                {\n                    /* Allocate and load a context for the secure task. */\n                    xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );\n                }\n                #endif /* configENABLE_MPU */\n\n                configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );\n                SecureContext_LoadContext( xSecureContext, pxCurrentTCB );\n                break;\n\n            case portSVC_FREE_SECURE_CONTEXT:\n\n                /* R0 contains TCB being freed and R1 contains the secure\n                 * context handle to be freed. */\n                ulR0 = pulCallerStackAddress[ 0 ];\n                ulR1 = pulCallerStackAddress[ 1 ];\n\n                /* Free the secure context. */\n                SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );\n                break;\n        #endif /* configENABLE_TRUSTZONE */\n\n        case portSVC_START_SCHEDULER:\n            #if ( configENABLE_TRUSTZONE == 1 )\n            {\n                /* De-prioritize the non-secure exceptions so that the\n                 * non-secure pendSV runs at the lowest priority. */\n                SecureInit_DePrioritizeNSExceptions();\n\n                /* Initialize the secure context management system. */\n                SecureContext_Init();\n            }\n            #endif /* configENABLE_TRUSTZONE */\n\n            #if ( configENABLE_FPU == 1 )\n            {\n                /* Setup the Floating Point Unit (FPU). */\n                prvSetupFPU();\n            }\n            #endif /* configENABLE_FPU */\n\n            /* Setup the context of the first task so that the first task starts\n             * executing. */\n            vRestoreContextOfFirstTask();\n            break;\n\n            #if ( configENABLE_MPU == 1 )\n                case portSVC_RAISE_PRIVILEGE:\n\n                    /* Only raise the privilege, if the svc was raised from any of\n                     * the system calls. */\n                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&\n                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )\n                    {\n                        vRaisePrivilege();\n                    }\n                    break;\n            #endif /* configENABLE_MPU */\n\n        default:\n            /* Incorrect SVC call. */\n            configASSERT( pdFALSE );\n    }\n}\n/*-----------------------------------------------------------*/\n/* *INDENT-OFF* */\n#if ( configENABLE_MPU == 1 )\n    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,\n                                         StackType_t * pxEndOfStack,\n                                         TaskFunction_t pxCode,\n                                         void * pvParameters,\n                                         BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */\n#else\n    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,\n                                         StackType_t * pxEndOfStack,\n                                         TaskFunction_t pxCode,\n                                         void * pvParameters ) /* PRIVILEGED_FUNCTION */\n#endif /* configENABLE_MPU */\n/* *INDENT-ON* */\n{\n    /* Simulate the stack frame as it would be created by a context switch\n     * interrupt. */\n    #if ( portPRELOAD_REGISTERS == 0 )\n    {\n        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\n        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\n        pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */\n        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */\n        pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */\n        *pxTopOfStack = portINITIAL_EXC_RETURN;\n\n        #if ( configENABLE_MPU == 1 )\n        {\n            pxTopOfStack--;\n\n            if( xRunPrivileged == pdTRUE )\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n            else\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n        }\n        #endif /* configENABLE_MPU */\n\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\n\n        #if ( configENABLE_TRUSTZONE == 1 )\n        {\n            pxTopOfStack--;\n            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\n        }\n        #endif /* configENABLE_TRUSTZONE */\n    }\n    #else /* portPRELOAD_REGISTERS */\n    {\n        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\n        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04 */\n        pxTopOfStack--;\n        *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN */\n\n        #if ( configENABLE_MPU == 1 )\n        {\n            pxTopOfStack--;\n\n            if( xRunPrivileged == pdTRUE )\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n            else\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n        }\n        #endif /* configENABLE_MPU */\n\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\n\n        #if ( configENABLE_TRUSTZONE == 1 )\n        {\n            pxTopOfStack--;\n            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\n        }\n        #endif /* configENABLE_TRUSTZONE */\n    }\n    #endif /* portPRELOAD_REGISTERS */\n\n    return pxTopOfStack;\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Make PendSV, CallSV and SysTick the same priority as the kernel. */\n    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;\n    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;\n\n    #if ( configENABLE_MPU == 1 )\n    {\n        /* Setup the Memory Protection Unit (MPU). */\n        prvSetupMPU();\n    }\n    #endif /* configENABLE_MPU */\n\n    /* Start the timer that generates the tick ISR. Interrupts are disabled\n     * here already. */\n    vPortSetupTimerInterrupt();\n\n    /* Initialize the critical nesting count ready for the first task. */\n    ulCriticalNesting = 0;\n\n    /* Start the first task. */\n    vStartFirstTask();\n\n    /* Should never get here as the tasks will now be executing. Call the task\n     * exit error function to prevent compiler warnings about a static function\n     * not being called in the case that the application writer overrides this\n     * functionality by defining configTASK_RETURN_ADDRESS. Call\n     * vTaskSwitchContext() so link time optimization does not remove the\n     * symbol. */\n    vTaskSwitchContext();\n    prvTaskExitError();\n\n    /* Should not get here. */\n    return 0;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Not implemented in ports where there is nothing to return to.\n     * Artificially force an assert. */\n    configASSERT( ulCriticalNesting == 1000UL );\n}\n/*-----------------------------------------------------------*/\n\n#if ( configENABLE_MPU == 1 )\n    void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,\n                                    const struct xMEMORY_REGION * const xRegions,\n                                    StackType_t * pxBottomOfStack,\n                                    uint32_t ulStackDepth )\n    {\n        uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;\n        int32_t lIndex = 0;\n\n        #if defined( __ARMCC_VERSION )\n\n            /* Declaration when these variable are defined in code instead of being\n             * exported from linker scripts. */\n            extern uint32_t * __privileged_sram_start__;\n            extern uint32_t * __privileged_sram_end__;\n        #else\n            /* Declaration when these variable are exported from linker scripts. */\n            extern uint32_t __privileged_sram_start__[];\n            extern uint32_t __privileged_sram_end__[];\n        #endif /* defined( __ARMCC_VERSION ) */\n\n        /* Setup MAIR0. */\n        xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\n        xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\n\n        /* This function is called automatically when the task is created - in\n         * which case the stack region parameters will be valid.  At all other\n         * times the stack parameters will not be valid and it is assumed that\n         * the stack region has already been configured. */\n        if( ulStackDepth > 0 )\n        {\n            ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;\n            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;\n\n            /* If the stack is within the privileged SRAM, do not protect it\n             * using a separate MPU region. This is needed because privileged\n             * SRAM is already protected using an MPU region and ARMv8-M does\n             * not allow overlapping MPU regions. */\n            if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) &&\n                ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) )\n            {\n                xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0;\n                xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0;\n            }\n            else\n            {\n                /* Define the region that allows access to the stack. */\n                ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK;\n                ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\n\n                xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |\n                                                             ( portMPU_REGION_NON_SHAREABLE ) |\n                                                             ( portMPU_REGION_READ_WRITE ) |\n                                                             ( portMPU_REGION_EXECUTE_NEVER );\n\n                xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) |\n                                                             ( portMPU_RLAR_ATTR_INDEX0 ) |\n                                                             ( portMPU_RLAR_REGION_ENABLE );\n            }\n        }\n\n        /* User supplied configurable regions. */\n        for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )\n        {\n            /* If xRegions is NULL i.e. the task has not specified any MPU\n             * region, the else part ensures that all the configurable MPU\n             * regions are invalidated. */\n            if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )\n            {\n                /* Translate the generic region definition contained in xRegions\n                 * into the ARMv8 specific MPU settings that are then stored in\n                 * xMPUSettings. */\n                ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;\n                ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;\n                ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\n\n                /* Start address. */\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |\n                                                                          ( portMPU_REGION_NON_SHAREABLE );\n\n                /* RO/RW. */\n                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )\n                {\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );\n                }\n                else\n                {\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );\n                }\n\n                /* XN. */\n                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )\n                {\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );\n                }\n\n                /* End Address. */\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |\n                                                                          ( portMPU_RLAR_REGION_ENABLE );\n\n                /* Normal memory/ Device memory. */\n                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )\n                {\n                    /* Attr1 in MAIR0 is configured as device memory. */\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;\n                }\n                else\n                {\n                    /* Attr0 in MAIR0 is configured as normal memory. */\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;\n                }\n            }\n            else\n            {\n                /* Invalidate the region. */\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;\n            }\n\n            lIndex++;\n        }\n    }\n#endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\nBaseType_t xPortIsInsideInterrupt( void )\n{\n    uint32_t ulCurrentInterrupt;\n    BaseType_t xReturn;\n\n    /* Obtain the number of the currently executing interrupt. Interrupt Program\n     * Status Register (IPSR) holds the exception number of the currently-executing\n     * exception or zero for Thread mode.*/\n    __asm volatile ( \"mrs %0, ipsr\" : \"=r\" ( ulCurrentInterrupt )::\"memory\" );\n\n    if( ulCurrentInterrupt == 0 )\n    {\n        xReturn = pdFALSE;\n    }\n    else\n    {\n        xReturn = pdTRUE;\n    }\n\n    return xReturn;\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM33/non_secure/portasm.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef __PORT_ASM_H__\n#define __PORT_ASM_H__\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n\n/* MPU wrappers includes. */\n#include \"mpu_wrappers.h\"\n\n/**\n * @brief Restore the context of the first task so that the first task starts\n * executing.\n */\nvoid vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Checks whether or not the processor is privileged.\n *\n * @return 1 if the processor is already privileged, 0 otherwise.\n */\nBaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );\n\n/**\n * @brief Raises the privilege level by clearing the bit 0 of the CONTROL\n * register.\n *\n * @note This is a privileged function and should only be called from the kenrel\n * code.\n *\n * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.\n *  Bit[0] = 0 --> The processor is running privileged\n *  Bit[0] = 1 --> The processor is running unprivileged.\n */\nvoid vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\n * register.\n *\n * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.\n *  Bit[0] = 0 --> The processor is running privileged\n *  Bit[0] = 1 --> The processor is running unprivileged.\n */\nvoid vResetPrivilege( void ) __attribute__( ( naked ) );\n\n/**\n * @brief Starts the first task.\n */\nvoid vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Disables interrupts.\n */\nuint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Enables interrupts.\n */\nvoid vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief PendSV Exception handler.\n */\nvoid PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief SVC Handler.\n */\nvoid SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Allocate a Secure context for the calling task.\n *\n * @param[in] ulSecureStackSize The size of the stack to be allocated on the\n * secure side for the calling task.\n */\nvoid vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) );\n\n/**\n * @brief Free the task's secure context.\n *\n * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.\n */\nvoid vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n#endif /* __PORT_ASM_H__ */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM33/non_secure/portasm.s",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n/* Including FreeRTOSConfig.h here will cause build errors if the header file\ncontains code not understood by the assembler - for example the 'extern' keyword.\nTo avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so\nthe code is included in C files but excluded by the preprocessor in assembly\nfiles (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */\n#include \"FreeRTOSConfig.h\"\n\n\tEXTERN pxCurrentTCB\n\tEXTERN xSecureContext\n\tEXTERN vTaskSwitchContext\n\tEXTERN vPortSVCHandler_C\n\tEXTERN SecureContext_SaveContext\n\tEXTERN SecureContext_LoadContext\n\n\tPUBLIC xIsPrivileged\n\tPUBLIC vResetPrivilege\n\tPUBLIC vPortAllocateSecureContext\n\tPUBLIC vRestoreContextOfFirstTask\n\tPUBLIC vRaisePrivilege\n\tPUBLIC vStartFirstTask\n\tPUBLIC ulSetInterruptMask\n\tPUBLIC vClearInterruptMask\n\tPUBLIC PendSV_Handler\n\tPUBLIC SVC_Handler\n\tPUBLIC vPortFreeSecureContext\n/*-----------------------------------------------------------*/\n\n/*---------------- Unprivileged Functions -------------------*/\n\n/*-----------------------------------------------------------*/\n\n\tSECTION .text:CODE:NOROOT(2)\n\tTHUMB\n/*-----------------------------------------------------------*/\n\nxIsPrivileged:\n\tmrs r0, control\t\t\t\t\t\t\t/* r0 = CONTROL. */\n\ttst r0, #1\t\t\t\t\t\t\t\t/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\n\tite ne\n\tmovne r0, #0\t\t\t\t\t\t\t/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\n\tmoveq r0, #1\t\t\t\t\t\t\t/* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */\n\tbx lr\t\t\t\t\t\t\t\t\t/* Return. */\n/*-----------------------------------------------------------*/\n\nvResetPrivilege:\n\tmrs r0, control\t\t\t\t\t\t\t/* r0 = CONTROL. */\n\torr r0, r0, #1\t\t\t\t\t\t\t/* r0 = r0 | 1. */\n\tmsr control, r0\t\t\t\t\t\t\t/* CONTROL = r0. */\n\tbx lr\t\t\t\t\t\t\t\t\t/* Return to the caller. */\n/*-----------------------------------------------------------*/\n\nvPortAllocateSecureContext:\n\tsvc 0\t\t\t\t\t\t\t\t\t/* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 0. */\n\tbx lr\t\t\t\t\t\t\t\t\t/* Return. */\n/*-----------------------------------------------------------*/\n\n/*----------------- Privileged Functions --------------------*/\n\n/*-----------------------------------------------------------*/\n\n\tSECTION privileged_functions:CODE:NOROOT(2)\n\tTHUMB\n/*-----------------------------------------------------------*/\n\nvRestoreContextOfFirstTask:\n\tldr  r2, =pxCurrentTCB\t\t\t\t\t/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n\tldr  r3, [r2]\t\t\t\t\t\t\t/* Read pxCurrentTCB. */\n\tldr  r0, [r3]\t\t\t\t\t\t\t/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\n\n#if ( configENABLE_MPU == 1 )\n\tdmb\t\t\t\t\t\t\t\t\t\t/* Complete outstanding transfers before disabling MPU. */\n\tldr r2, =0xe000ed94\t\t\t\t\t\t/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n\tldr r4, [r2]\t\t\t\t\t\t\t/* Read the value of MPU_CTRL. */\n\tbic r4, r4, #1\t\t\t\t\t\t\t/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\n\tstr r4, [r2]\t\t\t\t\t\t\t/* Disable MPU. */\n\n\tadds r3, #4\t\t\t\t\t\t\t\t/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\n\tldr  r4, [r3]\t\t\t\t\t\t\t/* r4 = *r3 i.e. r4 = MAIR0. */\n\tldr  r2, =0xe000edc0\t\t\t\t\t/* r2 = 0xe000edc0 [Location of MAIR0]. */\n\tstr  r4, [r2]\t\t\t\t\t\t\t/* Program MAIR0. */\n\tldr  r2, =0xe000ed98\t\t\t\t\t/* r2 = 0xe000ed98 [Location of RNR]. */\n\tmovs r4, #4\t\t\t\t\t\t\t\t/* r4 = 4. */\n\tstr  r4, [r2]\t\t\t\t\t\t\t/* Program RNR = 4. */\n\tadds r3, #4\t\t\t\t\t\t\t\t/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */\n\tldr  r2, =0xe000ed9c\t\t\t\t\t/* r2 = 0xe000ed9c [Location of RBAR]. */\n\tldmia r3!, {r4-r11}\t\t\t\t\t\t/* Read 4 set of RBAR/RLAR registers from TCB. */\n\tstmia r2!, {r4-r11}\t\t\t\t\t\t/* Write 4 set of RBAR/RLAR registers using alias registers. */\n\n\tldr r2, =0xe000ed94\t\t\t\t\t\t/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n\tldr r4, [r2]\t\t\t\t\t\t\t/* Read the value of MPU_CTRL. */\n\torr r4, r4, #1\t\t\t\t\t\t\t/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\n\tstr r4, [r2]\t\t\t\t\t\t\t/* Enable MPU. */\n\tdsb\t\t\t\t\t\t\t\t\t\t/* Force memory writes before continuing. */\n#endif /* configENABLE_MPU */\n\n#if ( configENABLE_MPU == 1 )\n\tldm  r0!, {r1-r4}\t\t\t\t\t\t/* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */\n\tldr  r5, =xSecureContext\n\tstr  r1, [r5]\t\t\t\t\t\t\t/* Set xSecureContext to this task's value for the same. */\n\tmsr  psplim, r2\t\t\t\t\t\t\t/* Set this task's PSPLIM value. */\n\tmsr  control, r3\t\t\t\t\t\t/* Set this task's CONTROL value. */\n\tadds r0, #32\t\t\t\t\t\t\t/* Discard everything up to r0. */\n\tmsr  psp, r0\t\t\t\t\t\t\t/* This is now the new top of stack to use in the task. */\n\tisb\n\tmov  r0, #0\n\tmsr  basepri, r0\t\t\t\t\t\t/* Ensure that interrupts are enabled when the first task starts. */\n\tbx   r4\t\t\t\t\t\t\t\t\t/* Finally, branch to EXC_RETURN. */\n#else /* configENABLE_MPU */\n\tldm  r0!, {r1-r3}\t\t\t\t\t\t/* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */\n\tldr  r4, =xSecureContext\n\tstr  r1, [r4]\t\t\t\t\t\t\t/* Set xSecureContext to this task's value for the same. */\n\tmsr  psplim, r2\t\t\t\t\t\t\t/* Set this task's PSPLIM value. */\n\tmovs r1, #2\t\t\t\t\t\t\t\t/* r1 = 2. */\n\tmsr  CONTROL, r1\t\t\t\t\t\t/* Switch to use PSP in the thread mode. */\n\tadds r0, #32\t\t\t\t\t\t\t/* Discard everything up to r0. */\n\tmsr  psp, r0\t\t\t\t\t\t\t/* This is now the new top of stack to use in the task. */\n\tisb\n\tmov  r0, #0\n\tmsr  basepri, r0\t\t\t\t\t\t/* Ensure that interrupts are enabled when the first task starts. */\n\tbx   r3\t\t\t\t\t\t\t\t\t/* Finally, branch to EXC_RETURN. */\n#endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\nvRaisePrivilege:\n\tmrs  r0, control\t\t\t\t\t\t/* Read the CONTROL register. */\n\tbic r0, r0, #1\t\t\t\t\t\t\t/* Clear the bit 0. */\n\tmsr  control, r0\t\t\t\t\t\t/* Write back the new CONTROL value. */\n\tbx lr\t\t\t\t\t\t\t\t\t/* Return to the caller. */\n/*-----------------------------------------------------------*/\n\nvStartFirstTask:\n\tldr r0, =0xe000ed08\t\t\t\t\t\t/* Use the NVIC offset register to locate the stack. */\n\tldr r0, [r0]\t\t\t\t\t\t\t/* Read the VTOR register which gives the address of vector table. */\n\tldr r0, [r0]\t\t\t\t\t\t\t/* The first entry in vector table is stack pointer. */\n\tmsr msp, r0\t\t\t\t\t\t\t\t/* Set the MSP back to the start of the stack. */\n\tcpsie i\t\t\t\t\t\t\t\t\t/* Globally enable interrupts. */\n\tcpsie f\n\tdsb\n\tisb\n\tsvc 2\t\t\t\t\t\t\t\t\t/* System call to start the first task. portSVC_START_SCHEDULER = 2. */\n/*-----------------------------------------------------------*/\n\nulSetInterruptMask:\n\tmrs r0, basepri\t\t\t\t\t\t\t/* r0 = basepri. Return original basepri value. */\n\tmov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY\n\tmsr basepri, r1\t\t\t\t\t\t\t/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */\n\tdsb\n\tisb\n\tbx lr\t\t\t\t\t\t\t\t\t/* Return. */\n/*-----------------------------------------------------------*/\n\nvClearInterruptMask:\n\tmsr basepri, r0\t\t\t\t\t\t\t/* basepri = ulMask. */\n\tdsb\n\tisb\n\tbx lr\t\t\t\t\t\t\t\t\t/* Return. */\n/*-----------------------------------------------------------*/\n\nPendSV_Handler:\n\tldr r3, =xSecureContext\t\t\t\t\t/* Read the location of xSecureContext i.e. &( xSecureContext ). */\n\tldr r0, [r3]\t\t\t\t\t\t\t/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */\n\tldr r3, =pxCurrentTCB\t\t\t\t\t/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n\tldr r1, [r3]\t\t\t\t\t\t\t/* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */\n\tmrs r2, psp\t\t\t\t\t\t\t\t/* Read PSP in r2. */\n\n\tcbz r0, save_ns_context\t\t\t\t\t/* No secure context to save. */\n\tpush {r0-r2, r14}\n\tbl SecureContext_SaveContext\t\t\t/* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */\n\tpop {r0-r3}\t\t\t\t\t\t\t\t/* LR is now in r3. */\n\tmov lr, r3\t\t\t\t\t\t\t\t/* LR = r3. */\n\tlsls r1, r3, #25\t\t\t\t\t\t/* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\n\tbpl save_ns_context\t\t\t\t\t\t/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\n\n\tldr r3, =pxCurrentTCB\t\t\t\t\t/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n\tldr r1, [r3]\t\t\t\t\t\t\t/* Read pxCurrentTCB. */\n#if ( configENABLE_MPU == 1 )\n\tsubs r2, r2, #16\t\t\t\t\t\t/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */\n\tstr r2, [r1]\t\t\t\t\t\t\t/* Save the new top of stack in TCB. */\n\tmrs r1, psplim\t\t\t\t\t\t\t/* r1 = PSPLIM. */\n\tmrs r3, control\t\t\t\t\t\t\t/* r3 = CONTROL. */\n\tmov r4, lr\t\t\t\t\t\t\t\t/* r4 = LR/EXC_RETURN. */\n\tstmia r2!, {r0, r1, r3, r4}\t\t\t\t/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\n#else /* configENABLE_MPU */\n\tsubs r2, r2, #12\t\t\t\t\t\t/* Make space for xSecureContext, PSPLIM and LR on the stack. */\n\tstr r2, [r1]\t\t\t\t\t\t\t/* Save the new top of stack in TCB. */\n\tmrs r1, psplim\t\t\t\t\t\t\t/* r1 = PSPLIM. */\n\tmov r3, lr\t\t\t\t\t\t\t\t/* r3 = LR/EXC_RETURN. */\n\tstmia r2!, {r0, r1, r3}\t\t\t\t\t/* Store xSecureContext, PSPLIM and LR on the stack. */\n#endif /* configENABLE_MPU */\n\tb select_next_task\n\n\tsave_ns_context:\n\t\tldr r3, =pxCurrentTCB\t\t\t\t/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n\t\tldr r1, [r3]\t\t\t\t\t\t/* Read pxCurrentTCB. */\n\t#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )\n\t\ttst lr, #0x10\t\t\t\t\t\t/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */\n\t\tit eq\n\t\tvstmdbeq r2!, {s16-s31}\t\t\t\t/* Store the additional FP context registers which are not saved automatically. */\n\t#endif /* configENABLE_FPU || configENABLE_MVE */\n\t#if ( configENABLE_MPU == 1 )\n\t\tsubs r2, r2, #48\t\t\t\t\t/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */\n\t\tstr r2, [r1]\t\t\t\t\t\t/* Save the new top of stack in TCB. */\n\t\tadds r2, r2, #16\t\t\t\t\t/* r2 = r2 + 16. */\n\t\tstm r2, {r4-r11}\t\t\t\t\t/* Store the registers that are not saved automatically. */\n\t\tmrs r1, psplim\t\t\t\t\t\t/* r1 = PSPLIM. */\n\t\tmrs r3, control\t\t\t\t\t\t/* r3 = CONTROL. */\n\t\tmov r4, lr\t\t\t\t\t\t\t/* r4 = LR/EXC_RETURN. */\n\t\tsubs r2, r2, #16\t\t\t\t\t/* r2 = r2 - 16. */\n\t\tstmia r2!, {r0, r1, r3, r4}\t\t\t/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\n\t#else /* configENABLE_MPU */\n\t\tsubs r2, r2, #44\t\t\t\t\t/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */\n\t\tstr r2, [r1]\t\t\t\t\t\t/* Save the new top of stack in TCB. */\n\t\tadds r2, r2, #12\t\t\t\t\t/* r2 = r2 + 12. */\n\t\tstm r2, {r4-r11}\t\t\t\t\t/* Store the registers that are not saved automatically. */\n\t\tmrs r1, psplim\t\t\t\t\t\t/* r1 = PSPLIM. */\n\t\tmov r3, lr\t\t\t\t\t\t\t/* r3 = LR/EXC_RETURN. */\n\t\tsubs r2, r2, #12\t\t\t\t\t/* r2 = r2 - 12. */\n\t\tstmia r2!, {r0, r1, r3}\t\t\t\t/* Store xSecureContext, PSPLIM and LR on the stack. */\n\t#endif /* configENABLE_MPU */\n\n\tselect_next_task:\n\t\tmov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY\n\t\tmsr basepri, r0\t\t\t\t\t\t/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */\n\t\tdsb\n\t\tisb\n\t\tbl vTaskSwitchContext\n\t\tmov r0, #0\t\t\t\t\t\t\t/* r0 = 0. */\n\t\tmsr basepri, r0\t\t\t\t\t\t/* Enable interrupts. */\n\n\t\tldr r3, =pxCurrentTCB\t\t\t\t/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n\t\tldr r1, [r3]\t\t\t\t\t\t/* Read pxCurrentTCB. */\n\t\tldr r2, [r1]\t\t\t\t\t\t/* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */\n\n\t#if ( configENABLE_MPU == 1 )\n\t\tdmb\t\t\t\t\t\t\t\t\t/* Complete outstanding transfers before disabling MPU. */\n\t\tldr r3, =0xe000ed94\t\t\t\t\t/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */\n\t\tldr r4, [r3]\t\t\t\t\t\t/* Read the value of MPU_CTRL. */\n\t\tbic r4, r4, #1\t\t\t\t\t\t/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\n\t\tstr r4, [r3]\t\t\t\t\t\t/* Disable MPU. */\n\n\t\tadds r1, #4\t\t\t\t\t\t\t/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\n\t\tldr r4, [r1]\t\t\t\t\t\t/* r4 = *r1 i.e. r4 = MAIR0. */\n\t\tldr r3, =0xe000edc0\t\t\t\t\t/* r3 = 0xe000edc0 [Location of MAIR0]. */\n\t\tstr r4, [r3]\t\t\t\t\t\t/* Program MAIR0. */\n\t\tldr r3, =0xe000ed98\t\t\t\t\t/* r3 = 0xe000ed98 [Location of RNR]. */\n\t\tmovs r4, #4\t\t\t\t\t\t\t/* r4 = 4. */\n\t\tstr r4, [r3]\t\t\t\t\t\t/* Program RNR = 4. */\n\t\tadds r1, #4\t\t\t\t\t\t\t/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\n\t\tldr  r3, =0xe000ed9c\t\t\t\t/* r3 = 0xe000ed9c [Location of RBAR]. */\n\t\tldmia r1!, {r4-r11}\t\t\t\t\t/* Read 4 sets of RBAR/RLAR registers from TCB. */\n\t\tstmia r3!, {r4-r11}\t\t\t\t\t/* Write 4 set of RBAR/RLAR registers using alias registers. */\n\n\t\tldr r3, =0xe000ed94\t\t\t\t\t/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */\n\t\tldr r4, [r3]\t\t\t\t\t\t/* Read the value of MPU_CTRL. */\n\t\torr r4, r4, #1\t\t\t\t\t\t/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\n\t\tstr r4, [r3]\t\t\t\t\t\t/* Enable MPU. */\n\t\tdsb\t\t\t\t\t\t\t\t\t/* Force memory writes before continuing. */\n\t#endif /* configENABLE_MPU */\n\n\t#if ( configENABLE_MPU == 1 )\n\t\tldmia r2!, {r0, r1, r3, r4}\t\t\t/* Read from stack - r0 = xSecureContext, r1 = PSPLIM, r3 = CONTROL and r4 = LR. */\n\t\tmsr psplim, r1\t\t\t\t\t\t/* Restore the PSPLIM register value for the task. */\n\t\tmsr control, r3\t\t\t\t\t\t/* Restore the CONTROL register value for the task. */\n\t\tmov lr, r4\t\t\t\t\t\t\t/* LR = r4. */\n\t\tldr r3, =xSecureContext\t\t\t\t/* Read the location of xSecureContext i.e. &( xSecureContext ). */\n\t\tstr r0, [r3]\t\t\t\t\t\t/* Restore the task's xSecureContext. */\n\t\tcbz r0, restore_ns_context\t\t\t/* If there is no secure context for the task, restore the non-secure context. */\n\t\tldr r3, =pxCurrentTCB\t\t\t\t/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n\t\tldr r1, [r3]\t\t\t\t\t\t/* Read pxCurrentTCB. */\n\t\tpush {r2, r4}\n\t\tbl SecureContext_LoadContext\t\t/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */\n\t\tpop {r2, r4}\n\t\tmov lr, r4\t\t\t\t\t\t\t/* LR = r4. */\n\t\tlsls r1, r4, #25\t\t\t\t\t/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\n\t\tbpl restore_ns_context\t\t\t\t/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\n\t\tmsr psp, r2\t\t\t\t\t\t\t/* Remember the new top of stack for the task. */\n\t\tbx lr\n\t#else /* configENABLE_MPU */\n\t\tldmia r2!, {r0, r1, r4}\t\t\t\t/* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */\n\t\tmsr psplim, r1\t\t\t\t\t\t/* Restore the PSPLIM register value for the task. */\n\t\tmov lr, r4\t\t\t\t\t\t\t/* LR = r4. */\n\t\tldr r3, =xSecureContext\t\t\t\t/* Read the location of xSecureContext i.e. &( xSecureContext ). */\n\t\tstr r0, [r3]\t\t\t\t\t\t/* Restore the task's xSecureContext. */\n\t\tcbz r0, restore_ns_context\t\t\t/* If there is no secure context for the task, restore the non-secure context. */\n\t\tldr r3, =pxCurrentTCB\t\t\t\t/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n\t\tldr r1, [r3]\t\t\t\t\t\t/* Read pxCurrentTCB. */\n\t\tpush {r2, r4}\n\t\tbl SecureContext_LoadContext\t\t/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */\n\t\tpop {r2, r4}\n\t\tmov lr, r4\t\t\t\t\t\t\t/* LR = r4. */\n\t\tlsls r1, r4, #25\t\t\t\t\t/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\n\t\tbpl restore_ns_context\t\t\t\t/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\n\t\tmsr psp, r2\t\t\t\t\t\t\t/* Remember the new top of stack for the task. */\n\t\tbx lr\n\t#endif /* configENABLE_MPU */\n\n\trestore_ns_context:\n\t\tldmia r2!, {r4-r11}\t\t\t\t\t/* Restore the registers that are not automatically restored. */\n\t#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )\n\t\ttst lr, #0x10\t\t\t\t\t\t/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */\n\t\tit eq\n\t\tvldmiaeq r2!, {s16-s31}\t\t\t\t/* Restore the additional FP context registers which are not restored automatically. */\n\t#endif /* configENABLE_FPU || configENABLE_MVE */\n\t\tmsr psp, r2\t\t\t\t\t\t\t/* Remember the new top of stack for the task. */\n\t\tbx lr\n/*-----------------------------------------------------------*/\n\nSVC_Handler:\n\ttst lr, #4\n\tite eq\n\tmrseq r0, msp\n\tmrsne r0, psp\n\tb vPortSVCHandler_C\n/*-----------------------------------------------------------*/\n\nvPortFreeSecureContext:\n\t/* r0 = uint32_t *pulTCB. */\n\tldr r2, [r0]\t\t\t\t\t\t\t/* The first item in the TCB is the top of the stack. */\n\tldr r1, [r2]\t\t\t\t\t\t\t/* The first item on the stack is the task's xSecureContext. */\n\tcmp r1, #0\t\t\t\t\t\t\t\t/* Raise svc if task's xSecureContext is not NULL. */\n\tit ne\n\tsvcne 1\t\t\t\t\t\t\t\t\t/* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */\n\tbx lr\t\t\t\t\t\t\t\t\t/* Return. */\n/*-----------------------------------------------------------*/\n\n\tEND\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM33/non_secure/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef PORTMACRO_H\n#define PORTMACRO_H\n\n#ifdef __cplusplus\n    extern \"C\" {\n#endif\n\n#include \"portmacrocommon.h\"\n\n/*------------------------------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the given hardware\n * and compiler.\n *\n * These settings should not be altered.\n *------------------------------------------------------------------------------\n */\n\n/**\n * Architecture specifics.\n */\n#define portARCH_NAME                       \"Cortex-M33\"\n#define portDONT_DISCARD                    __root\n/*-----------------------------------------------------------*/\n\n#if( configTOTAL_MPU_REGIONS == 16 )\n    #error 16 MPU regions are not yet supported for this port.\n#endif\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Critical section management.\n */\n#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()\n#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )\n/*-----------------------------------------------------------*/\n\n/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in\n * the source code because to do so would cause other compilers to generate\n * warnings. */\n#pragma diag_suppress=Be006\n#pragma diag_suppress=Pa082\n/*-----------------------------------------------------------*/\n\n#ifdef __cplusplus\n    }\n#endif\n\n#endif /* PORTMACRO_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef PORTMACROCOMMON_H\n    #define PORTMACROCOMMON_H\n\n    #ifdef __cplusplus\n        extern \"C\" {\n    #endif\n\n/*------------------------------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the given hardware\n * and compiler.\n *\n * These settings should not be altered.\n *------------------------------------------------------------------------------\n */\n\n    #ifndef configENABLE_FPU\n        #error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.\n    #endif /* configENABLE_FPU */\n\n    #ifndef configENABLE_MPU\n        #error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.\n    #endif /* configENABLE_MPU */\n\n    #ifndef configENABLE_TRUSTZONE\n        #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.\n    #endif /* configENABLE_TRUSTZONE */\n\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Type definitions.\n */\n    #define portCHAR          char\n    #define portFLOAT         float\n    #define portDOUBLE        double\n    #define portLONG          long\n    #define portSHORT         short\n    #define portSTACK_TYPE    uint32_t\n    #define portBASE_TYPE     long\n\n    typedef portSTACK_TYPE   StackType_t;\n    typedef long             BaseType_t;\n    typedef unsigned long    UBaseType_t;\n\n    #if ( configUSE_16_BIT_TICKS == 1 )\n        typedef uint16_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffff\n    #else\n        typedef uint32_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL\n\n/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\n * not need to be guarded with a critical section. */\n        #define portTICK_TYPE_IS_ATOMIC    1\n    #endif\n/*-----------------------------------------------------------*/\n\n/**\n * Architecture specifics.\n */\n    #define portSTACK_GROWTH                   ( -1 )\n    #define portTICK_PERIOD_MS                 ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\n    #define portBYTE_ALIGNMENT                 8\n    #define portNOP()\n    #define portINLINE                         __inline\n    #ifndef portFORCE_INLINE\n        #define portFORCE_INLINE               inline __attribute__( ( always_inline ) )\n    #endif\n    #define portHAS_STACK_OVERFLOW_CHECKING    1\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Extern declarations.\n */\n    extern BaseType_t xPortIsInsideInterrupt( void );\n\n    extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;\n\n    extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;\n    extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;\n\n    extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\n    extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\n\n    #if ( configENABLE_TRUSTZONE == 1 )\n        extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */\n        extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;\n    #endif /* configENABLE_TRUSTZONE */\n\n    #if ( configENABLE_MPU == 1 )\n        extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;\n        extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;\n    #endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\n/**\n * @brief MPU specific constants.\n */\n    #if ( configENABLE_MPU == 1 )\n        #define portUSING_MPU_WRAPPERS    1\n        #define portPRIVILEGE_BIT         ( 0x80000000UL )\n    #else\n        #define portPRIVILEGE_BIT         ( 0x0UL )\n    #endif /* configENABLE_MPU */\n\n/* MPU settings that can be overriden in FreeRTOSConfig.h. */\n#ifndef configTOTAL_MPU_REGIONS\n    /* Define to 8 for backward compatibility. */\n    #define configTOTAL_MPU_REGIONS       ( 8UL )\n#endif\n\n/* MPU regions. */\n    #define portPRIVILEGED_FLASH_REGION                   ( 0UL )\n    #define portUNPRIVILEGED_FLASH_REGION                 ( 1UL )\n    #define portUNPRIVILEGED_SYSCALLS_REGION              ( 2UL )\n    #define portPRIVILEGED_RAM_REGION                     ( 3UL )\n    #define portSTACK_REGION                              ( 4UL )\n    #define portFIRST_CONFIGURABLE_REGION                 ( 5UL )\n    #define portLAST_CONFIGURABLE_REGION                  ( configTOTAL_MPU_REGIONS - 1UL )\n    #define portNUM_CONFIGURABLE_REGIONS                  ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )\n    #define portTOTAL_NUM_REGIONS                         ( portNUM_CONFIGURABLE_REGIONS + 1 )   /* Plus one to make space for the stack region. */\n\n/* Device memory attributes used in MPU_MAIR registers.\n *\n * 8-bit values encoded as follows:\n *  Bit[7:4] - 0000 - Device Memory\n *  Bit[3:2] - 00 --> Device-nGnRnE\n *\t\t\t\t01 --> Device-nGnRE\n *\t\t\t\t10 --> Device-nGRE\n *\t\t\t\t11 --> Device-GRE\n *  Bit[1:0] - 00, Reserved.\n */\n    #define portMPU_DEVICE_MEMORY_nGnRnE                  ( 0x00 )   /* 0000 0000 */\n    #define portMPU_DEVICE_MEMORY_nGnRE                   ( 0x04 )   /* 0000 0100 */\n    #define portMPU_DEVICE_MEMORY_nGRE                    ( 0x08 )   /* 0000 1000 */\n    #define portMPU_DEVICE_MEMORY_GRE                     ( 0x0C )   /* 0000 1100 */\n\n/* Normal memory attributes used in MPU_MAIR registers. */\n    #define portMPU_NORMAL_MEMORY_NON_CACHEABLE           ( 0x44 )   /* Non-cacheable. */\n    #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE    ( 0xFF )   /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */\n\n/* Attributes used in MPU_RBAR registers. */\n    #define portMPU_REGION_NON_SHAREABLE                  ( 0UL << 3UL )\n    #define portMPU_REGION_INNER_SHAREABLE                ( 1UL << 3UL )\n    #define portMPU_REGION_OUTER_SHAREABLE                ( 2UL << 3UL )\n\n    #define portMPU_REGION_PRIVILEGED_READ_WRITE          ( 0UL << 1UL )\n    #define portMPU_REGION_READ_WRITE                     ( 1UL << 1UL )\n    #define portMPU_REGION_PRIVILEGED_READ_ONLY           ( 2UL << 1UL )\n    #define portMPU_REGION_READ_ONLY                      ( 3UL << 1UL )\n\n    #define portMPU_REGION_EXECUTE_NEVER                  ( 1UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Settings to define an MPU region.\n */\n    typedef struct MPURegionSettings\n    {\n        uint32_t ulRBAR; /**< RBAR for the region. */\n        uint32_t ulRLAR; /**< RLAR for the region. */\n    } MPURegionSettings_t;\n\n/**\n * @brief MPU settings as stored in the TCB.\n */\n    typedef struct MPU_SETTINGS\n    {\n        uint32_t ulMAIR0;                                              /**< MAIR0 for the task containing attributes for all the 4 per task regions. */\n        MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */\n    } xMPU_SETTINGS;\n/*-----------------------------------------------------------*/\n\n/**\n * @brief SVC numbers.\n */\n    #define portSVC_ALLOCATE_SECURE_CONTEXT    0\n    #define portSVC_FREE_SECURE_CONTEXT        1\n    #define portSVC_START_SCHEDULER            2\n    #define portSVC_RAISE_PRIVILEGE            3\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Scheduler utilities.\n */\n    #define portYIELD()                                 vPortYield()\n    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )\n    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )\n    #define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )\n    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Critical section management.\n */\n    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulSetInterruptMask()\n    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vClearInterruptMask( x )\n    #define portENTER_CRITICAL()                      vPortEnterCritical()\n    #define portEXIT_CRITICAL()                       vPortExitCritical()\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Tickless idle/low power functionality.\n */\n    #ifndef portSUPPRESS_TICKS_AND_SLEEP\n        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );\n        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )\n    #endif\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Task function macros as described on the FreeRTOS.org WEB site.\n */\n    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )\n    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )\n/*-----------------------------------------------------------*/\n\n    #if ( configENABLE_TRUSTZONE == 1 )\n\n/**\n * @brief Allocate a secure context for the task.\n *\n * Tasks are not created with a secure context. Any task that is going to call\n * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a\n * secure context before it calls any secure function.\n *\n * @param[in] ulSecureStackSize The size of the secure stack to be allocated.\n */\n        #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )\n\n/**\n * @brief Called when a task is deleted to delete the task's secure context,\n * if it has one.\n *\n * @param[in] pxTCB The TCB of the task being deleted.\n */\n        #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )\n    #endif /* configENABLE_TRUSTZONE */\n/*-----------------------------------------------------------*/\n\n    #if ( configENABLE_MPU == 1 )\n\n/**\n * @brief Checks whether or not the processor is privileged.\n *\n * @return 1 if the processor is already privileged, 0 otherwise.\n */\n        #define portIS_PRIVILEGED()      xIsPrivileged()\n\n/**\n * @brief Raise an SVC request to raise privilege.\n *\n * The SVC handler checks that the SVC was raised from a system call and only\n * then it raises the privilege. If this is called from any other place,\n * the privilege is not raised.\n */\n        #define portRAISE_PRIVILEGE()    __asm volatile ( \"svc %0 \\n\" ::\"i\" ( portSVC_RAISE_PRIVILEGE ) : \"memory\" );\n\n/**\n * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\n * register.\n */\n        #define portRESET_PRIVILEGE()    vResetPrivilege()\n    #else\n        #define portIS_PRIVILEGED()\n        #define portRAISE_PRIVILEGE()\n        #define portRESET_PRIVILEGE()\n    #endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Barriers.\n */\n    #define portMEMORY_BARRIER()    __asm volatile ( \"\" ::: \"memory\" )\n/*-----------------------------------------------------------*/\n\n    #ifdef __cplusplus\n        }\n    #endif\n\n#endif /* PORTMACROCOMMON_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM33/secure/secure_context.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Secure context includes. */\n#include \"secure_context.h\"\n\n/* Secure heap includes. */\n#include \"secure_heap.h\"\n\n/* Secure port macros. */\n#include \"secure_port_macros.h\"\n\n/**\n * @brief CONTROL value for privileged tasks.\n *\n * Bit[0] - 0 --> Thread mode is privileged.\n * Bit[1] - 1 --> Thread mode uses PSP.\n */\n#define securecontextCONTROL_VALUE_PRIVILEGED      0x02\n\n/**\n * @brief CONTROL value for un-privileged tasks.\n *\n * Bit[0] - 1 --> Thread mode is un-privileged.\n * Bit[1] - 1 --> Thread mode uses PSP.\n */\n#define securecontextCONTROL_VALUE_UNPRIVILEGED    0x03\n\n/**\n * @brief Size of stack seal values in bytes.\n */\n#define securecontextSTACK_SEAL_SIZE               8\n\n/**\n * @brief Stack seal value as recommended by ARM.\n */\n#define securecontextSTACK_SEAL_VALUE              0xFEF5EDA5\n\n/**\n * @brief Maximum number of secure contexts.\n */\n#ifndef secureconfigMAX_SECURE_CONTEXTS\n    #define secureconfigMAX_SECURE_CONTEXTS        8UL\n#endif\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Pre-allocated array of secure contexts.\n */\nSecureContext_t xSecureContexts[ secureconfigMAX_SECURE_CONTEXTS ];\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Get a free secure context for a task from the secure context pool (xSecureContexts).\n *\n * This function ensures that only one secure context is allocated for a task.\n *\n * @param[in] pvTaskHandle The task handle for which the secure context is allocated.\n *\n * @return Index of a free secure context in the xSecureContexts array.\n */\nstatic uint32_t ulGetSecureContext( void * pvTaskHandle );\n\n/**\n * @brief Return the secure context to the secure context pool (xSecureContexts).\n *\n * @param[in] ulSecureContextIndex Index of the context in the xSecureContexts array.\n */\nstatic void vReturnSecureContext( uint32_t ulSecureContextIndex );\n\n/* These are implemented in assembly. */\nextern void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext );\nextern void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext );\n/*-----------------------------------------------------------*/\n\nstatic uint32_t ulGetSecureContext( void * pvTaskHandle )\n{\n    /* Start with invalid index. */\n    uint32_t i, ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS;\n\n    for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ )\n    {\n        if( ( xSecureContexts[ i ].pucCurrentStackPointer == NULL ) &&\n            ( xSecureContexts[ i ].pucStackLimit == NULL ) &&\n            ( xSecureContexts[ i ].pucStackStart == NULL ) &&\n            ( xSecureContexts[ i ].pvTaskHandle == NULL ) &&\n            ( ulSecureContextIndex == secureconfigMAX_SECURE_CONTEXTS ) )\n        {\n            ulSecureContextIndex = i;\n        }\n        else if( xSecureContexts[ i ].pvTaskHandle == pvTaskHandle )\n        {\n            /* A task can only have one secure context. Do not allocate a second\n             * context for the same task. */\n            ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS;\n            break;\n        }\n    }\n\n    return ulSecureContextIndex;\n}\n/*-----------------------------------------------------------*/\n\nstatic void vReturnSecureContext( uint32_t ulSecureContextIndex )\n{\n    xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = NULL;\n    xSecureContexts[ ulSecureContextIndex ].pucStackLimit = NULL;\n    xSecureContexts[ ulSecureContextIndex ].pucStackStart = NULL;\n    xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = NULL;\n}\n/*-----------------------------------------------------------*/\n\nsecureportNON_SECURE_CALLABLE void SecureContext_Init( void )\n{\n    uint32_t ulIPSR, i;\n    static uint32_t ulSecureContextsInitialized = 0;\n\n    /* Read the Interrupt Program Status Register (IPSR) value. */\n    secureportREAD_IPSR( ulIPSR );\n\n    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\n     * when the processor is running in the Thread Mode. */\n    if( ( ulIPSR != 0 ) && ( ulSecureContextsInitialized == 0 ) )\n    {\n        /* Ensure to initialize secure contexts only once. */\n        ulSecureContextsInitialized = 1;\n\n        /* No stack for thread mode until a task's context is loaded. */\n        secureportSET_PSPLIM( securecontextNO_STACK );\n        secureportSET_PSP( securecontextNO_STACK );\n\n        /* Initialize all secure contexts. */\n        for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ )\n        {\n            xSecureContexts[ i ].pucCurrentStackPointer = NULL;\n            xSecureContexts[ i ].pucStackLimit = NULL;\n            xSecureContexts[ i ].pucStackStart = NULL;\n            xSecureContexts[ i ].pvTaskHandle = NULL;\n        }\n\n        #if ( configENABLE_MPU == 1 )\n            {\n                /* Configure thread mode to use PSP and to be unprivileged. */\n                secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );\n            }\n        #else /* configENABLE_MPU */\n            {\n                /* Configure thread mode to use PSP and to be privileged. */\n                secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );\n            }\n        #endif /* configENABLE_MPU */\n    }\n}\n/*-----------------------------------------------------------*/\n\n#if ( configENABLE_MPU == 1 )\n    secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,\n                                                                                       uint32_t ulIsTaskPrivileged,\n                                                                                       void * pvTaskHandle )\n#else /* configENABLE_MPU */\n    secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,\n                                                                                       void * pvTaskHandle )\n#endif /* configENABLE_MPU */\n{\n    uint8_t * pucStackMemory = NULL;\n    uint8_t * pucStackLimit;\n    uint32_t ulIPSR, ulSecureContextIndex;\n    SecureContextHandle_t xSecureContextHandle = securecontextINVALID_CONTEXT_ID;\n\n    #if ( configENABLE_MPU == 1 )\n        uint32_t * pulCurrentStackPointer = NULL;\n    #endif /* configENABLE_MPU */\n\n    /* Read the Interrupt Program Status Register (IPSR) and Process Stack Limit\n     * Register (PSPLIM) value. */\n    secureportREAD_IPSR( ulIPSR );\n    secureportREAD_PSPLIM( pucStackLimit );\n\n    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\n     * when the processor is running in the Thread Mode.\n     * Also do nothing, if a secure context us already loaded. PSPLIM is set to\n     * securecontextNO_STACK when no secure context is loaded. */\n    if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) )\n    {\n        /* Ontain a free secure context. */\n        ulSecureContextIndex = ulGetSecureContext( pvTaskHandle );\n\n        /* Were we able to get a free context? */\n        if( ulSecureContextIndex < secureconfigMAX_SECURE_CONTEXTS )\n        {\n            /* Allocate the stack space. */\n            pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE );\n\n            if( pucStackMemory != NULL )\n            {\n                /* Since stack grows down, the starting point will be the last\n                 * location. Note that this location is next to the last\n                 * allocated byte for stack (excluding the space for seal values)\n                 * because the hardware decrements the stack pointer before\n                 * writing i.e. if stack pointer is 0x2, a push operation will\n                 * decrement the stack pointer to 0x1 and then write at 0x1. */\n                xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize;\n\n                /* Seal the created secure process stack. */\n                *( uint32_t * )( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE;\n                *( uint32_t * )( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE;\n\n                /* The stack cannot go beyond this location. This value is\n                 * programmed in the PSPLIM register on context switch.*/\n                xSecureContexts[ ulSecureContextIndex ].pucStackLimit = pucStackMemory;\n\n                xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle;\n\n                #if ( configENABLE_MPU == 1 )\n                    {\n                        /* Store the correct CONTROL value for the task on the stack.\n                         * This value is programmed in the CONTROL register on\n                         * context switch. */\n                        pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart;\n                        pulCurrentStackPointer--;\n\n                        if( ulIsTaskPrivileged )\n                        {\n                            *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;\n                        }\n                        else\n                        {\n                            *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;\n                        }\n\n                        /* Store the current stack pointer. This value is programmed in\n                         * the PSP register on context switch. */\n                        xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;\n                    }\n                #else /* configENABLE_MPU */\n                    {\n                        /* Current SP is set to the starting of the stack. This\n                         * value programmed in the PSP register on context switch. */\n                        xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart;\n                    }\n                #endif /* configENABLE_MPU */\n\n                /* Ensure to never return 0 as a valid context handle. */\n                xSecureContextHandle = ulSecureContextIndex + 1UL;\n            }\n        }\n    }\n\n    return xSecureContextHandle;\n}\n/*-----------------------------------------------------------*/\n\nsecureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )\n{\n    uint32_t ulIPSR, ulSecureContextIndex;\n\n    /* Read the Interrupt Program Status Register (IPSR) value. */\n    secureportREAD_IPSR( ulIPSR );\n\n    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\n     * when the processor is running in the Thread Mode. */\n    if( ulIPSR != 0 )\n    {\n        /* Only free if a valid context handle is passed. */\n        if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) )\n        {\n            ulSecureContextIndex = xSecureContextHandle - 1UL;\n\n            /* Ensure that the secure context being deleted is associated with\n             * the task. */\n            if( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle )\n            {\n                /* Free the stack space. */\n                vPortFree( xSecureContexts[ ulSecureContextIndex ].pucStackLimit );\n\n                /* Return the secure context back to the free secure contexts pool. */\n                vReturnSecureContext( ulSecureContextIndex );\n            }\n        }\n    }\n}\n/*-----------------------------------------------------------*/\n\nsecureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )\n{\n    uint8_t * pucStackLimit;\n    uint32_t ulSecureContextIndex;\n\n    if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) )\n    {\n        ulSecureContextIndex = xSecureContextHandle - 1UL;\n\n        secureportREAD_PSPLIM( pucStackLimit );\n\n        /* Ensure that no secure context is loaded and the task is loading it's\n         * own context. */\n        if( ( pucStackLimit == securecontextNO_STACK ) &&\n            ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) )\n        {\n            SecureContext_LoadContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) );\n        }\n    }\n}\n/*-----------------------------------------------------------*/\n\nsecureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )\n{\n    uint8_t * pucStackLimit;\n    uint32_t ulSecureContextIndex;\n\n    if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) )\n    {\n        ulSecureContextIndex = xSecureContextHandle - 1UL;\n\n        secureportREAD_PSPLIM( pucStackLimit );\n\n        /* Ensure that task's context is loaded and the task is saving it's own\n         * context. */\n        if( ( xSecureContexts[ ulSecureContextIndex ].pucStackLimit == pucStackLimit ) &&\n            ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) )\n        {\n            SecureContext_SaveContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) );\n        }\n    }\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM33/secure/secure_context.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef __SECURE_CONTEXT_H__\n#define __SECURE_CONTEXT_H__\n\n/* Standard includes. */\n#include <stdint.h>\n\n/* FreeRTOS includes. */\n#include \"FreeRTOSConfig.h\"\n\n/**\n * @brief PSP value when no secure context is loaded.\n */\n#define securecontextNO_STACK               0x0\n\n/**\n * @brief Invalid context ID.\n */\n#define securecontextINVALID_CONTEXT_ID     0UL\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Structure to represent a secure context.\n *\n * @note Since stack grows down, pucStackStart is the highest address while\n * pucStackLimit is the first address of the allocated memory.\n */\ntypedef struct SecureContext\n{\n    uint8_t * pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */\n    uint8_t * pucStackLimit;          /**< Last location of the stack memory (PSPLIM). */\n    uint8_t * pucStackStart;          /**< First location of the stack memory. */\n    void * pvTaskHandle;              /**< Task handle of the task this context is associated with. */\n} SecureContext_t;\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Opaque handle for a secure context.\n */\ntypedef uint32_t SecureContextHandle_t;\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Initializes the secure context management system.\n *\n * PSP is set to NULL and therefore a task must allocate and load a context\n * before calling any secure side function in the thread mode.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n */\nvoid SecureContext_Init( void );\n\n/**\n * @brief Allocates a context on the secure side.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n *\n * @param[in] ulSecureStackSize Size of the stack to allocate on secure side.\n * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise.\n *\n * @return Opaque context handle if context is successfully allocated, NULL\n * otherwise.\n */\n#if ( configENABLE_MPU == 1 )\n    SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,\n                                                         uint32_t ulIsTaskPrivileged,\n                                                         void * pvTaskHandle );\n#else /* configENABLE_MPU */\n    SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,\n                                                         void * pvTaskHandle );\n#endif /* configENABLE_MPU */\n\n/**\n * @brief Frees the given context.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n *\n * @param[in] xSecureContextHandle Context handle corresponding to the\n * context to be freed.\n */\nvoid SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );\n\n/**\n * @brief Loads the given context.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n *\n * @param[in] xSecureContextHandle Context handle corresponding to the context\n * to be loaded.\n */\nvoid SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );\n\n/**\n * @brief Saves the given context.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n *\n * @param[in] xSecureContextHandle Context handle corresponding to the context\n * to be saved.\n */\nvoid SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );\n\n#endif /* __SECURE_CONTEXT_H__ */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM33/secure/secure_context_port_asm.s",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n    SECTION .text:CODE:NOROOT(2)\n    THUMB\n\n/* Including FreeRTOSConfig.h here will cause build errors if the header file\ncontains code not understood by the assembler - for example the 'extern' keyword.\nTo avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so\nthe code is included in C files but excluded by the preprocessor in assembly\nfiles (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */\n#include \"FreeRTOSConfig.h\"\n\n    PUBLIC SecureContext_LoadContextAsm\n    PUBLIC SecureContext_SaveContextAsm\n/*-----------------------------------------------------------*/\n\nSecureContext_LoadContextAsm:\n    /* pxSecureContext value is in r0. */\n    mrs r1, ipsr                        /* r1 = IPSR. */\n    cbz r1, load_ctx_therad_mode        /* Do nothing if the processor is running in the Thread Mode. */\n    ldmia r0!, {r1, r2}                 /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */\n\n#if ( configENABLE_MPU == 1 )\n    ldmia r1!, {r3}                     /* Read CONTROL register value from task's stack. r3 = CONTROL. */\n    msr control, r3                     /* CONTROL = r3. */\n#endif /* configENABLE_MPU */\n\n    msr psplim, r2                      /* PSPLIM = r2. */\n    msr psp, r1                         /* PSP = r1. */\n\n    load_ctx_therad_mode:\n        bx lr\n/*-----------------------------------------------------------*/\n\nSecureContext_SaveContextAsm:\n    /* pxSecureContext value is in r0. */\n    mrs r1, ipsr                        /* r1 = IPSR. */\n    cbz r1, save_ctx_therad_mode        /* Do nothing if the processor is running in the Thread Mode. */\n    mrs r1, psp                         /* r1 = PSP. */\n\n#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )\n    vstmdb r1!, {s0}                    /* Trigger the deferred stacking of FPU registers. */\n    vldmia r1!, {s0}                    /* Nullify the effect of the previous statement. */\n#endif /* configENABLE_FPU || configENABLE_MVE */\n\n#if ( configENABLE_MPU == 1 )\n    mrs r2, control                     /* r2 = CONTROL. */\n    stmdb r1!, {r2}                     /* Store CONTROL value on the stack. */\n#endif /* configENABLE_MPU */\n\n    str r1, [r0]                        /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */\n    movs r1, #0                         /* r1 = securecontextNO_STACK. */\n    msr psplim, r1                      /* PSPLIM = securecontextNO_STACK. */\n    msr psp, r1                         /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */\n\n    save_ctx_therad_mode:\n        bx lr\n/*-----------------------------------------------------------*/\n\n    END\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM33/secure/secure_heap.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Standard includes. */\n#include <stdint.h>\n\n/* Secure context heap includes. */\n#include \"secure_heap.h\"\n\n/* Secure port macros. */\n#include \"secure_port_macros.h\"\n\n/**\n * @brief Total heap size.\n */\n#ifndef secureconfigTOTAL_HEAP_SIZE\n    #define secureconfigTOTAL_HEAP_SIZE    ( ( ( size_t ) ( 10 * 1024 ) ) )\n#endif\n\n/* No test marker by default. */\n#ifndef mtCOVERAGE_TEST_MARKER\n    #define mtCOVERAGE_TEST_MARKER()\n#endif\n\n/* No tracing by default. */\n#ifndef traceMALLOC\n    #define traceMALLOC( pvReturn, xWantedSize )\n#endif\n\n/* No tracing by default. */\n#ifndef traceFREE\n    #define traceFREE( pv, xBlockSize )\n#endif\n\n/* Block sizes must not get too small. */\n#define secureheapMINIMUM_BLOCK_SIZE    ( ( size_t ) ( xHeapStructSize << 1 ) )\n\n/* Assumes 8bit bytes! */\n#define secureheapBITS_PER_BYTE         ( ( size_t ) 8 )\n/*-----------------------------------------------------------*/\n\n/* Allocate the memory for the heap. */\n#if ( configAPPLICATION_ALLOCATED_HEAP == 1 )\n\n/* The application writer has already defined the array used for the RTOS\n* heap - probably so it can be placed in a special segment or address. */\n    extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];\n#else /* configAPPLICATION_ALLOCATED_HEAP */\n    static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];\n#endif /* configAPPLICATION_ALLOCATED_HEAP */\n\n/**\n * @brief The linked list structure.\n *\n * This is used to link free blocks in order of their memory address.\n */\ntypedef struct A_BLOCK_LINK\n{\n    struct A_BLOCK_LINK * pxNextFreeBlock; /**< The next free block in the list. */\n    size_t xBlockSize;                     /**< The size of the free block. */\n} BlockLink_t;\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Called automatically to setup the required heap structures the first\n * time pvPortMalloc() is called.\n */\nstatic void prvHeapInit( void );\n\n/**\n * @brief Inserts a block of memory that is being freed into the correct\n * position in the list of free memory blocks.\n *\n * The block being freed will be merged with the block in front it and/or the\n * block behind it if the memory blocks are adjacent to each other.\n *\n * @param[in] pxBlockToInsert The block being freed.\n */\nstatic void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert );\n/*-----------------------------------------------------------*/\n\n/**\n * @brief The size of the structure placed at the beginning of each allocated\n * memory block must by correctly byte aligned.\n */\nstatic const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );\n\n/**\n * @brief Create a couple of list links to mark the start and end of the list.\n */\nstatic BlockLink_t xStart;\nstatic BlockLink_t * pxEnd = NULL;\n\n/**\n * @brief Keeps track of the number of free bytes remaining, but says nothing\n * about fragmentation.\n */\nstatic size_t xFreeBytesRemaining = 0U;\nstatic size_t xMinimumEverFreeBytesRemaining = 0U;\n\n/**\n * @brief Gets set to the top bit of an size_t type.\n *\n * When this bit in the xBlockSize member of an BlockLink_t structure is set\n * then the block belongs to the application. When the bit is free the block is\n * still part of the free heap space.\n */\nstatic size_t xBlockAllocatedBit = 0;\n/*-----------------------------------------------------------*/\n\nstatic void prvHeapInit( void )\n{\n    BlockLink_t * pxFirstFreeBlock;\n    uint8_t * pucAlignedHeap;\n    size_t uxAddress;\n    size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE;\n\n    /* Ensure the heap starts on a correctly aligned boundary. */\n    uxAddress = ( size_t ) ucHeap;\n\n    if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 )\n    {\n        uxAddress += ( secureportBYTE_ALIGNMENT - 1 );\n        uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );\n        xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;\n    }\n\n    pucAlignedHeap = ( uint8_t * ) uxAddress;\n\n    /* xStart is used to hold a pointer to the first item in the list of free\n     * blocks.  The void cast is used to prevent compiler warnings. */\n    xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;\n    xStart.xBlockSize = ( size_t ) 0;\n\n    /* pxEnd is used to mark the end of the list of free blocks and is inserted\n     * at the end of the heap space. */\n    uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;\n    uxAddress -= xHeapStructSize;\n    uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );\n    pxEnd = ( void * ) uxAddress;\n    pxEnd->xBlockSize = 0;\n    pxEnd->pxNextFreeBlock = NULL;\n\n    /* To start with there is a single free block that is sized to take up the\n     * entire heap space, minus the space taken by pxEnd. */\n    pxFirstFreeBlock = ( void * ) pucAlignedHeap;\n    pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;\n    pxFirstFreeBlock->pxNextFreeBlock = pxEnd;\n\n    /* Only one block exists - and it covers the entire usable heap space. */\n    xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;\n    xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;\n\n    /* Work out the position of the top bit in a size_t variable. */\n    xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert )\n{\n    BlockLink_t * pxIterator;\n    uint8_t * puc;\n\n    /* Iterate through the list until a block is found that has a higher address\n     * than the block being inserted. */\n    for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )\n    {\n        /* Nothing to do here, just iterate to the right position. */\n    }\n\n    /* Do the block being inserted, and the block it is being inserted after\n     * make a contiguous block of memory? */\n    puc = ( uint8_t * ) pxIterator;\n\n    if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )\n    {\n        pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;\n        pxBlockToInsert = pxIterator;\n    }\n    else\n    {\n        mtCOVERAGE_TEST_MARKER();\n    }\n\n    /* Do the block being inserted, and the block it is being inserted before\n     * make a contiguous block of memory? */\n    puc = ( uint8_t * ) pxBlockToInsert;\n\n    if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )\n    {\n        if( pxIterator->pxNextFreeBlock != pxEnd )\n        {\n            /* Form one big block from the two blocks. */\n            pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;\n            pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;\n        }\n        else\n        {\n            pxBlockToInsert->pxNextFreeBlock = pxEnd;\n        }\n    }\n    else\n    {\n        pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;\n    }\n\n    /* If the block being inserted plugged a gab, so was merged with the block\n     * before and the block after, then it's pxNextFreeBlock pointer will have\n     * already been set, and should not be set here as that would make it point\n     * to itself. */\n    if( pxIterator != pxBlockToInsert )\n    {\n        pxIterator->pxNextFreeBlock = pxBlockToInsert;\n    }\n    else\n    {\n        mtCOVERAGE_TEST_MARKER();\n    }\n}\n/*-----------------------------------------------------------*/\n\nvoid * pvPortMalloc( size_t xWantedSize )\n{\n    BlockLink_t * pxBlock;\n    BlockLink_t * pxPreviousBlock;\n    BlockLink_t * pxNewBlockLink;\n    void * pvReturn = NULL;\n\n    /* If this is the first call to malloc then the heap will require\n     * initialisation to setup the list of free blocks. */\n    if( pxEnd == NULL )\n    {\n        prvHeapInit();\n    }\n    else\n    {\n        mtCOVERAGE_TEST_MARKER();\n    }\n\n    /* Check the requested block size is not so large that the top bit is set.\n     * The top bit of the block size member of the BlockLink_t structure is used\n     * to determine who owns the block - the application or the kernel, so it\n     * must be free. */\n    if( ( xWantedSize & xBlockAllocatedBit ) == 0 )\n    {\n        /* The wanted size is increased so it can contain a BlockLink_t\n         * structure in addition to the requested amount of bytes. */\n        if( xWantedSize > 0 )\n        {\n            xWantedSize += xHeapStructSize;\n\n            /* Ensure that blocks are always aligned to the required number of\n             * bytes. */\n            if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )\n            {\n                /* Byte alignment required. */\n                xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );\n                secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n\n        if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )\n        {\n            /* Traverse the list from the start (lowest address) block until\n             * one of adequate size is found. */\n            pxPreviousBlock = &xStart;\n            pxBlock = xStart.pxNextFreeBlock;\n\n            while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )\n            {\n                pxPreviousBlock = pxBlock;\n                pxBlock = pxBlock->pxNextFreeBlock;\n            }\n\n            /* If the end marker was reached then a block of adequate size was\n             * not found. */\n            if( pxBlock != pxEnd )\n            {\n                /* Return the memory space pointed to - jumping over the\n                 * BlockLink_t structure at its start. */\n                pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );\n\n                /* This block is being returned for use so must be taken out\n                 * of the list of free blocks. */\n                pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;\n\n                /* If the block is larger than required it can be split into\n                 * two. */\n                if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE )\n                {\n                    /* This block is to be split into two.  Create a new\n                     * block following the number of bytes requested. The void\n                     * cast is used to prevent byte alignment warnings from the\n                     * compiler. */\n                    pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );\n                    secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 );\n\n                    /* Calculate the sizes of two blocks split from the single\n                     * block. */\n                    pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;\n                    pxBlock->xBlockSize = xWantedSize;\n\n                    /* Insert the new block into the list of free blocks. */\n                    prvInsertBlockIntoFreeList( pxNewBlockLink );\n                }\n                else\n                {\n                    mtCOVERAGE_TEST_MARKER();\n                }\n\n                xFreeBytesRemaining -= pxBlock->xBlockSize;\n\n                if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )\n                {\n                    xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;\n                }\n                else\n                {\n                    mtCOVERAGE_TEST_MARKER();\n                }\n\n                /* The block is being returned - it is allocated and owned by\n                 * the application and has no \"next\" block. */\n                pxBlock->xBlockSize |= xBlockAllocatedBit;\n                pxBlock->pxNextFreeBlock = NULL;\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n    }\n    else\n    {\n        mtCOVERAGE_TEST_MARKER();\n    }\n\n    traceMALLOC( pvReturn, xWantedSize );\n\n    #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )\n        {\n            if( pvReturn == NULL )\n            {\n                extern void vApplicationMallocFailedHook( void );\n                vApplicationMallocFailedHook();\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n    #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */\n\n    secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );\n    return pvReturn;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortFree( void * pv )\n{\n    uint8_t * puc = ( uint8_t * ) pv;\n    BlockLink_t * pxLink;\n\n    if( pv != NULL )\n    {\n        /* The memory being freed will have an BlockLink_t structure immediately\n         * before it. */\n        puc -= xHeapStructSize;\n\n        /* This casting is to keep the compiler from issuing warnings. */\n        pxLink = ( void * ) puc;\n\n        /* Check the block is actually allocated. */\n        secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );\n        secureportASSERT( pxLink->pxNextFreeBlock == NULL );\n\n        if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )\n        {\n            if( pxLink->pxNextFreeBlock == NULL )\n            {\n                /* The block is being returned to the heap - it is no longer\n                 * allocated. */\n                pxLink->xBlockSize &= ~xBlockAllocatedBit;\n\n                secureportDISABLE_NON_SECURE_INTERRUPTS();\n                {\n                    /* Add this block to the list of free blocks. */\n                    xFreeBytesRemaining += pxLink->xBlockSize;\n                    traceFREE( pv, pxLink->xBlockSize );\n                    prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );\n                }\n                secureportENABLE_NON_SECURE_INTERRUPTS();\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n    }\n}\n/*-----------------------------------------------------------*/\n\nsize_t xPortGetFreeHeapSize( void )\n{\n    return xFreeBytesRemaining;\n}\n/*-----------------------------------------------------------*/\n\nsize_t xPortGetMinimumEverFreeHeapSize( void )\n{\n    return xMinimumEverFreeBytesRemaining;\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM33/secure/secure_heap.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef __SECURE_HEAP_H__\n#define __SECURE_HEAP_H__\n\n/* Standard includes. */\n#include <stdlib.h>\n\n/**\n * @brief Allocates memory from heap.\n *\n * @param[in] xWantedSize The size of the memory to be allocated.\n *\n * @return Pointer to the memory region if the allocation is successful, NULL\n * otherwise.\n */\nvoid * pvPortMalloc( size_t xWantedSize );\n\n/**\n * @brief Frees the previously allocated memory.\n *\n * @param[in] pv Pointer to the memory to be freed.\n */\nvoid vPortFree( void * pv );\n\n/**\n * @brief Get the free heap size.\n *\n * @return Free heap size.\n */\nsize_t xPortGetFreeHeapSize( void );\n\n/**\n * @brief Get the minimum ever free heap size.\n *\n * @return Minimum ever free heap size.\n */\nsize_t xPortGetMinimumEverFreeHeapSize( void );\n\n#endif /* __SECURE_HEAP_H__ */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM33/secure/secure_init.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Standard includes. */\n#include <stdint.h>\n\n/* Secure init includes. */\n#include \"secure_init.h\"\n\n/* Secure port macros. */\n#include \"secure_port_macros.h\"\n\n/**\n * @brief Constants required to manipulate the SCB.\n */\n#define secureinitSCB_AIRCR                 ( ( volatile uint32_t * ) 0xe000ed0c )  /* Application Interrupt and Reset Control Register. */\n#define secureinitSCB_AIRCR_VECTKEY_POS     ( 16UL )\n#define secureinitSCB_AIRCR_VECTKEY_MASK    ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )\n#define secureinitSCB_AIRCR_PRIS_POS        ( 14UL )\n#define secureinitSCB_AIRCR_PRIS_MASK       ( 1UL << secureinitSCB_AIRCR_PRIS_POS )\n\n/**\n * @brief Constants required to manipulate the FPU.\n */\n#define secureinitFPCCR                     ( ( volatile uint32_t * ) 0xe000ef34 )  /* Floating Point Context Control Register. */\n#define secureinitFPCCR_LSPENS_POS          ( 29UL )\n#define secureinitFPCCR_LSPENS_MASK         ( 1UL << secureinitFPCCR_LSPENS_POS )\n#define secureinitFPCCR_TS_POS              ( 26UL )\n#define secureinitFPCCR_TS_MASK             ( 1UL << secureinitFPCCR_TS_POS )\n\n#define secureinitNSACR                     ( ( volatile uint32_t * ) 0xe000ed8c )  /* Non-secure Access Control Register. */\n#define secureinitNSACR_CP10_POS            ( 10UL )\n#define secureinitNSACR_CP10_MASK           ( 1UL << secureinitNSACR_CP10_POS )\n#define secureinitNSACR_CP11_POS            ( 11UL )\n#define secureinitNSACR_CP11_MASK           ( 1UL << secureinitNSACR_CP11_POS )\n/*-----------------------------------------------------------*/\n\nsecureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void )\n{\n    uint32_t ulIPSR;\n\n    /* Read the Interrupt Program Status Register (IPSR) value. */\n    secureportREAD_IPSR( ulIPSR );\n\n    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\n     * when the processor is running in the Thread Mode. */\n    if( ulIPSR != 0 )\n    {\n        *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |\n                                   ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |\n                                   ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK );\n    }\n}\n/*-----------------------------------------------------------*/\n\nsecureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )\n{\n    uint32_t ulIPSR;\n\n    /* Read the Interrupt Program Status Register (IPSR) value. */\n    secureportREAD_IPSR( ulIPSR );\n\n    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\n     * when the processor is running in the Thread Mode. */\n    if( ulIPSR != 0 )\n    {\n        /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is\n         * permitted. CP11 should be programmed to the same value as CP10. */\n        *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );\n\n        /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures\n         * that we can enable/disable lazy stacking in port.c file. */\n        *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK );\n\n        /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP\n         * registers (S16-S31) are also pushed to stack on exception entry and\n         * restored on exception return. */\n        *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );\n    }\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM33/secure/secure_init.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef __SECURE_INIT_H__\n#define __SECURE_INIT_H__\n\n/**\n * @brief De-prioritizes the non-secure exceptions.\n *\n * This is needed to ensure that the non-secure PendSV runs at the lowest\n * priority. Context switch is done in the non-secure PendSV handler.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n */\nvoid SecureInit_DePrioritizeNSExceptions( void );\n\n/**\n * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access.\n *\n * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point\n * Registers are not leaked to the non-secure side.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n */\nvoid SecureInit_EnableNSFPUAccess( void );\n\n#endif /* __SECURE_INIT_H__ */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM33/secure/secure_port_macros.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef __SECURE_PORT_MACROS_H__\n#define __SECURE_PORT_MACROS_H__\n\n/**\n * @brief Byte alignment requirements.\n */\n#define secureportBYTE_ALIGNMENT         8\n#define secureportBYTE_ALIGNMENT_MASK    ( 0x0007 )\n\n/**\n * @brief Macro to declare a function as non-secure callable.\n */\n#if defined( __IAR_SYSTEMS_ICC__ )\n    #define secureportNON_SECURE_CALLABLE    __cmse_nonsecure_entry __root\n#else\n    #define secureportNON_SECURE_CALLABLE    __attribute__( ( cmse_nonsecure_entry ) ) __attribute__( ( used ) )\n#endif\n\n/**\n * @brief Set the secure PRIMASK value.\n */\n#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \\\n    __asm volatile ( \"msr primask, %0\" : : \"r\" ( ulPrimaskValue ) : \"memory\" )\n\n/**\n * @brief Set the non-secure PRIMASK value.\n */\n#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \\\n    __asm volatile ( \"msr primask_ns, %0\" : : \"r\" ( ulPrimaskValue ) : \"memory\" )\n\n/**\n * @brief Read the PSP value in the given variable.\n */\n#define secureportREAD_PSP( pucOutCurrentStackPointer ) \\\n    __asm volatile ( \"mrs %0, psp\"  : \"=r\" ( pucOutCurrentStackPointer ) )\n\n/**\n * @brief Set the PSP to the given value.\n */\n#define secureportSET_PSP( pucCurrentStackPointer ) \\\n    __asm volatile ( \"msr psp, %0\" : : \"r\" ( pucCurrentStackPointer ) )\n\n/**\n * @brief Read the PSPLIM value in the given variable.\n */\n#define secureportREAD_PSPLIM( pucOutStackLimit ) \\\n    __asm volatile ( \"mrs %0, psplim\"  : \"=r\" ( pucOutStackLimit ) )\n\n/**\n * @brief Set the PSPLIM to the given value.\n */\n#define secureportSET_PSPLIM( pucStackLimit ) \\\n    __asm volatile ( \"msr psplim, %0\" : : \"r\" ( pucStackLimit ) )\n\n/**\n * @brief Set the NonSecure MSP to the given value.\n */\n#define secureportSET_MSP_NS( pucMainStackPointer ) \\\n    __asm volatile ( \"msr msp_ns, %0\" : : \"r\" ( pucMainStackPointer ) )\n\n/**\n * @brief Set the CONTROL register to the given value.\n */\n#define secureportSET_CONTROL( ulControl ) \\\n    __asm volatile ( \"msr control, %0\" : : \"r\" ( ulControl ) : \"memory\" )\n\n/**\n * @brief Read the Interrupt Program Status Register (IPSR) value in the given\n * variable.\n */\n#define secureportREAD_IPSR( ulIPSR ) \\\n    __asm volatile ( \"mrs %0, ipsr\"  : \"=r\" ( ulIPSR ) )\n\n/**\n * @brief PRIMASK value to enable interrupts.\n */\n#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL     0\n\n/**\n * @brief PRIMASK value to disable interrupts.\n */\n#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL    1\n\n/**\n * @brief Disable secure interrupts.\n */\n#define secureportDISABLE_SECURE_INTERRUPTS()        secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )\n\n/**\n * @brief Disable non-secure interrupts.\n *\n * This effectively disables context switches.\n */\n#define secureportDISABLE_NON_SECURE_INTERRUPTS()    secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )\n\n/**\n * @brief Enable non-secure interrupts.\n */\n#define secureportENABLE_NON_SECURE_INTERRUPTS()     secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL )\n\n/**\n * @brief Assert definition.\n */\n#define secureportASSERT( x )                      \\\n    if( ( x ) == 0 )                               \\\n    {                                              \\\n        secureportDISABLE_SECURE_INTERRUPTS();     \\\n        secureportDISABLE_NON_SECURE_INTERRUPTS(); \\\n        for( ; ; ) {; }                            \\\n    }\n\n#endif /* __SECURE_PORT_MACROS_H__ */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM33_NTZ/non_secure/port.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\n * all the API functions to use the MPU wrappers. That should only be done when\n * task.h is included from an application file. */\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n/* MPU wrappers includes. */\n#include \"mpu_wrappers.h\"\n\n/* Portasm includes. */\n#include \"portasm.h\"\n\n#if ( configENABLE_TRUSTZONE == 1 )\n    /* Secure components includes. */\n    #include \"secure_context.h\"\n    #include \"secure_init.h\"\n#endif /* configENABLE_TRUSTZONE */\n\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/**\n * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only\n * i.e. the processor boots as secure and never jumps to the non-secure side.\n * The Trust Zone support in the port must be disabled in order to run FreeRTOS\n * on the secure side. The following are the valid configuration seetings:\n *\n * 1. Run FreeRTOS on the Secure Side:\n *    configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0\n *\n * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:\n *    configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1\n *\n * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:\n *    configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0\n */\n#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )\n    #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.\n#endif\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the NVIC.\n */\n#define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )\n#define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )\n#define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )\n#define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )\n#define portNVIC_SYSTICK_ENABLE_BIT           ( 1UL << 0UL )\n#define portNVIC_SYSTICK_INT_BIT              ( 1UL << 1UL )\n#define portNVIC_SYSTICK_CLK_BIT              ( 1UL << 2UL )\n#define portNVIC_SYSTICK_COUNT_FLAG_BIT       ( 1UL << 16UL )\n#define portNVIC_PEND_SYSTICK_CLEAR_BIT       ( 1UL << 25UL )\n#define portNVIC_PEND_SYSTICK_SET_BIT         ( 1UL << 26UL )\n#define portMIN_INTERRUPT_PRIORITY            ( 255UL )\n#define portNVIC_PENDSV_PRI                   ( portMIN_INTERRUPT_PRIORITY << 16UL )\n#define portNVIC_SYSTICK_PRI                  ( portMIN_INTERRUPT_PRIORITY << 24UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the SCB.\n */\n#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( volatile uint32_t * ) 0xe000ed24 )\n#define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the FPU.\n */\n#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 )              /* Coprocessor Access Control Register. */\n#define portCPACR_CP10_VALUE    ( 3UL )\n#define portCPACR_CP11_VALUE    portCPACR_CP10_VALUE\n#define portCPACR_CP10_POS      ( 20UL )\n#define portCPACR_CP11_POS      ( 22UL )\n\n#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 )              /* Floating Point Context Control Register. */\n#define portFPCCR_ASPEN_POS     ( 31UL )\n#define portFPCCR_ASPEN_MASK    ( 1UL << portFPCCR_ASPEN_POS )\n#define portFPCCR_LSPEN_POS     ( 30UL )\n#define portFPCCR_LSPEN_MASK    ( 1UL << portFPCCR_LSPEN_POS )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the MPU.\n */\n#define portMPU_TYPE_REG                      ( *( ( volatile uint32_t * ) 0xe000ed90 ) )\n#define portMPU_CTRL_REG                      ( *( ( volatile uint32_t * ) 0xe000ed94 ) )\n#define portMPU_RNR_REG                       ( *( ( volatile uint32_t * ) 0xe000ed98 ) )\n\n#define portMPU_RBAR_REG                      ( *( ( volatile uint32_t * ) 0xe000ed9c ) )\n#define portMPU_RLAR_REG                      ( *( ( volatile uint32_t * ) 0xe000eda0 ) )\n\n#define portMPU_RBAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda4 ) )\n#define portMPU_RLAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda8 ) )\n\n#define portMPU_RBAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edac ) )\n#define portMPU_RLAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edb0 ) )\n\n#define portMPU_RBAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb4 ) )\n#define portMPU_RLAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb8 ) )\n\n#define portMPU_MAIR0_REG                     ( *( ( volatile uint32_t * ) 0xe000edc0 ) )\n#define portMPU_MAIR1_REG                     ( *( ( volatile uint32_t * ) 0xe000edc4 ) )\n\n#define portMPU_RBAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */\n#define portMPU_RLAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */\n\n#define portMPU_MAIR_ATTR0_POS                ( 0UL )\n#define portMPU_MAIR_ATTR0_MASK               ( 0x000000ff )\n\n#define portMPU_MAIR_ATTR1_POS                ( 8UL )\n#define portMPU_MAIR_ATTR1_MASK               ( 0x0000ff00 )\n\n#define portMPU_MAIR_ATTR2_POS                ( 16UL )\n#define portMPU_MAIR_ATTR2_MASK               ( 0x00ff0000 )\n\n#define portMPU_MAIR_ATTR3_POS                ( 24UL )\n#define portMPU_MAIR_ATTR3_MASK               ( 0xff000000 )\n\n#define portMPU_MAIR_ATTR4_POS                ( 0UL )\n#define portMPU_MAIR_ATTR4_MASK               ( 0x000000ff )\n\n#define portMPU_MAIR_ATTR5_POS                ( 8UL )\n#define portMPU_MAIR_ATTR5_MASK               ( 0x0000ff00 )\n\n#define portMPU_MAIR_ATTR6_POS                ( 16UL )\n#define portMPU_MAIR_ATTR6_MASK               ( 0x00ff0000 )\n\n#define portMPU_MAIR_ATTR7_POS                ( 24UL )\n#define portMPU_MAIR_ATTR7_MASK               ( 0xff000000 )\n\n#define portMPU_RLAR_ATTR_INDEX0              ( 0UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX1              ( 1UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX2              ( 2UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX3              ( 3UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX4              ( 4UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX5              ( 5UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX6              ( 6UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX7              ( 7UL << 1UL )\n\n#define portMPU_RLAR_REGION_ENABLE            ( 1UL )\n\n/* Enable privileged access to unmapped region. */\n#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )\n\n/* Enable MPU. */\n#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )\n\n/* Expected value of the portMPU_TYPE register. */\n#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief The maximum 24-bit number.\n *\n * It is needed because the systick is a 24-bit counter.\n */\n#define portMAX_24_BIT_NUMBER       ( 0xffffffUL )\n\n/**\n * @brief A fiddle factor to estimate the number of SysTick counts that would\n * have occurred while the SysTick counter is stopped during tickless idle\n * calculations.\n */\n#define portMISSED_COUNTS_FACTOR    ( 94UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to set up the initial stack.\n */\n#define portINITIAL_XPSR    ( 0x01000000 )\n\n#if ( configRUN_FREERTOS_SECURE_ONLY == 1 )\n\n/**\n * @brief Initial EXC_RETURN value.\n *\n *     FF         FF         FF         FD\n * 1111 1111  1111 1111  1111 1111  1111 1101\n *\n * Bit[6] - 1 --> The exception was taken from the Secure state.\n * Bit[5] - 1 --> Do not skip stacking of additional state context.\n * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\n * Bit[3] - 1 --> Return to the Thread mode.\n * Bit[2] - 1 --> Restore registers from the process stack.\n * Bit[1] - 0 --> Reserved, 0.\n * Bit[0] - 1 --> The exception was taken to the Secure state.\n */\n    #define portINITIAL_EXC_RETURN    ( 0xfffffffd )\n#else\n\n/**\n * @brief Initial EXC_RETURN value.\n *\n *     FF         FF         FF         BC\n * 1111 1111  1111 1111  1111 1111  1011 1100\n *\n * Bit[6] - 0 --> The exception was taken from the Non-Secure state.\n * Bit[5] - 1 --> Do not skip stacking of additional state context.\n * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\n * Bit[3] - 1 --> Return to the Thread mode.\n * Bit[2] - 1 --> Restore registers from the process stack.\n * Bit[1] - 0 --> Reserved, 0.\n * Bit[0] - 0 --> The exception was taken to the Non-Secure state.\n */\n    #define portINITIAL_EXC_RETURN    ( 0xffffffbc )\n#endif /* configRUN_FREERTOS_SECURE_ONLY */\n\n/**\n * @brief CONTROL register privileged bit mask.\n *\n * Bit[0] in CONTROL register tells the privilege:\n *  Bit[0] = 0 ==> The task is privileged.\n *  Bit[0] = 1 ==> The task is not privileged.\n */\n#define portCONTROL_PRIVILEGED_MASK         ( 1UL << 0UL )\n\n/**\n * @brief Initial CONTROL register values.\n */\n#define portINITIAL_CONTROL_UNPRIVILEGED    ( 0x3 )\n#define portINITIAL_CONTROL_PRIVILEGED      ( 0x2 )\n\n/**\n * @brief Let the user override the default SysTick clock rate.  If defined by the\n * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the\n * configuration register.\n */\n#ifndef configSYSTICK_CLOCK_HZ\n    #define configSYSTICK_CLOCK_HZ             ( configCPU_CLOCK_HZ )\n    /* Ensure the SysTick is clocked at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( portNVIC_SYSTICK_CLK_BIT )\n#else\n    /* Select the option to clock SysTick not at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( 0 )\n#endif\n\n/**\n * @brief Let the user override the pre-loading of the initial LR with the\n * address of prvTaskExitError() in case it messes up unwinding of the stack\n * in the debugger.\n */\n#ifdef configTASK_RETURN_ADDRESS\n    #define portTASK_RETURN_ADDRESS    configTASK_RETURN_ADDRESS\n#else\n    #define portTASK_RETURN_ADDRESS    prvTaskExitError\n#endif\n\n/**\n * @brief If portPRELOAD_REGISTERS then registers will be given an initial value\n * when a task is created. This helps in debugging at the cost of code size.\n */\n#define portPRELOAD_REGISTERS    1\n\n/**\n * @brief A task is created without a secure context, and must call\n * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes\n * any secure calls.\n */\n#define portNO_SECURE_CONTEXT    0\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Used to catch tasks that attempt to return from their implementing\n * function.\n */\nstatic void prvTaskExitError( void );\n\n#if ( configENABLE_MPU == 1 )\n\n/**\n * @brief Setup the Memory Protection Unit (MPU).\n */\n    static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\n#endif /* configENABLE_MPU */\n\n#if ( configENABLE_FPU == 1 )\n\n/**\n * @brief Setup the Floating Point Unit (FPU).\n */\n    static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;\n#endif /* configENABLE_FPU */\n\n/**\n * @brief Setup the timer to generate the tick interrupts.\n *\n * The implementation in this file is weak to allow application writers to\n * change the timer used to generate the tick interrupt.\n */\nvoid vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Checks whether the current execution context is interrupt.\n *\n * @return pdTRUE if the current execution context is interrupt, pdFALSE\n * otherwise.\n */\nBaseType_t xPortIsInsideInterrupt( void );\n\n/**\n * @brief Yield the processor.\n */\nvoid vPortYield( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Enter critical section.\n */\nvoid vPortEnterCritical( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Exit from critical section.\n */\nvoid vPortExitCritical( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief SysTick handler.\n */\nvoid SysTick_Handler( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief C part of SVC handler.\n */\nportDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION;\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Each task maintains its own interrupt status in the critical nesting\n * variable.\n */\nPRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;\n\n#if ( configENABLE_TRUSTZONE == 1 )\n\n/**\n * @brief Saved as part of the task context to indicate which context the\n * task is using on the secure side.\n */\n    PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;\n#endif /* configENABLE_TRUSTZONE */\n\n#if ( configUSE_TICKLESS_IDLE == 1 )\n\n/**\n * @brief The number of SysTick increments that make up one tick period.\n */\n    PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0;\n\n/**\n * @brief The maximum number of tick periods that can be suppressed is\n * limited by the 24 bit resolution of the SysTick timer.\n */\n    PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0;\n\n/**\n * @brief Compensate for the CPU cycles that pass while the SysTick is\n * stopped (low power functionality only).\n */\n    PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TICKLESS_IDLE == 1 )\n    __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )\n    {\n        uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;\n        TickType_t xModifiableIdleTime;\n\n        /* Make sure the SysTick reload value does not overflow the counter. */\n        if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\n        {\n            xExpectedIdleTime = xMaximumPossibleSuppressedTicks;\n        }\n\n        /* Enter a critical section but don't use the taskENTER_CRITICAL()\n         * method as that will mask interrupts that should exit sleep mode. */\n        __asm volatile ( \"cpsid i\" ::: \"memory\" );\n        __asm volatile ( \"dsb\" );\n        __asm volatile ( \"isb\" );\n\n        /* If a context switch is pending or a task is waiting for the scheduler\n         * to be unsuspended then abandon the low power entry. */\n        if( eTaskConfirmSleepModeStatus() == eAbortSleep )\n        {\n            /* Re-enable interrupts - see comments above the cpsid instruction\n             * above. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n        }\n        else\n        {\n            /* Stop the SysTick momentarily.  The time the SysTick is stopped for\n             * is accounted for as best it can be, but using the tickless mode will\n             * inevitably result in some tiny drift of the time maintained by the\n             * kernel with respect to calendar time. */\n            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );\n\n            /* Use the SysTick current-value register to determine the number of\n             * SysTick decrements remaining until the next tick interrupt.  If the\n             * current-value register is zero, then there are actually\n             * ulTimerCountsForOneTick decrements remaining, not zero, because the\n             * SysTick requests the interrupt when decrementing from 1 to 0. */\n            ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n\n            if( ulSysTickDecrementsLeft == 0 )\n            {\n                ulSysTickDecrementsLeft = ulTimerCountsForOneTick;\n            }\n\n            /* Calculate the reload value required to wait xExpectedIdleTime\n             * tick periods.  -1 is used because this code normally executes part\n             * way through the first tick period.  But if the SysTick IRQ is now\n             * pending, then clear the IRQ, suppressing the first tick, and correct\n             * the reload value to reflect that the second tick period is already\n             * underway.  The expected idle time is always at least two ticks. */\n            ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );\n\n            if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )\n            {\n                portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;\n                ulReloadValue -= ulTimerCountsForOneTick;\n            }\n\n            if( ulReloadValue > ulStoppedTimerCompensation )\n            {\n                ulReloadValue -= ulStoppedTimerCompensation;\n            }\n\n            /* Set the new reload value. */\n            portNVIC_SYSTICK_LOAD_REG = ulReloadValue;\n\n            /* Clear the SysTick count flag and set the count value back to\n             * zero. */\n            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n            /* Restart SysTick. */\n            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\n\n            /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can\n             * set its parameter to 0 to indicate that its implementation contains\n             * its own wait for interrupt or wait for event instruction, and so wfi\n             * should not be executed again.  However, the original expected idle\n             * time variable must remain unmodified, so a copy is taken. */\n            xModifiableIdleTime = xExpectedIdleTime;\n            configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\n\n            if( xModifiableIdleTime > 0 )\n            {\n                __asm volatile ( \"dsb\" ::: \"memory\" );\n                __asm volatile ( \"wfi\" );\n                __asm volatile ( \"isb\" );\n            }\n\n            configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\n\n            /* Re-enable interrupts to allow the interrupt that brought the MCU\n             * out of sleep mode to execute immediately.  See comments above\n             * the cpsid instruction above. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n            __asm volatile ( \"dsb\" );\n            __asm volatile ( \"isb\" );\n\n            /* Disable interrupts again because the clock is about to be stopped\n             * and interrupts that execute while the clock is stopped will increase\n             * any slippage between the time maintained by the RTOS and calendar\n             * time. */\n            __asm volatile ( \"cpsid i\" ::: \"memory\" );\n            __asm volatile ( \"dsb\" );\n            __asm volatile ( \"isb\" );\n\n            /* Disable the SysTick clock without reading the\n             * portNVIC_SYSTICK_CTRL_REG register to ensure the\n             * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,\n             * the time the SysTick is stopped for is accounted for as best it can\n             * be, but using the tickless mode will inevitably result in some tiny\n             * drift of the time maintained by the kernel with respect to calendar\n             * time*/\n            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );\n\n            /* Determine whether the SysTick has already counted to zero. */\n            if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n            {\n                uint32_t ulCalculatedLoadValue;\n\n                /* The tick interrupt ended the sleep (or is now pending), and\n                 * a new tick period has started.  Reset portNVIC_SYSTICK_LOAD_REG\n                 * with whatever remains of the new tick period. */\n                ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\n\n                /* Don't allow a tiny value, or values that have somehow\n                 * underflowed because the post sleep hook did something\n                 * that took too long or because the SysTick current-value register\n                 * is zero. */\n                if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )\n                {\n                    ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );\n                }\n\n                portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;\n\n                /* As the pending tick will be processed as soon as this\n                 * function exits, the tick value maintained by the tick is stepped\n                 * forward by one less than the time spent waiting. */\n                ulCompleteTickPeriods = xExpectedIdleTime - 1UL;\n            }\n            else\n            {\n                /* Something other than the tick interrupt ended the sleep. */\n\n                /* Use the SysTick current-value register to determine the\n                 * number of SysTick decrements remaining until the expected idle\n                 * time would have ended. */\n                ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n                #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )\n                {\n                    /* If the SysTick is not using the core clock, the current-\n                     * value register might still be zero here.  In that case, the\n                     * SysTick didn't load from the reload register, and there are\n                     * ulReloadValue decrements remaining in the expected idle\n                     * time, not zero. */\n                    if( ulSysTickDecrementsLeft == 0 )\n                    {\n                        ulSysTickDecrementsLeft = ulReloadValue;\n                    }\n                }\n                #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */\n\n                /* Work out how long the sleep lasted rounded to complete tick\n                 * periods (not the ulReload value which accounted for part\n                 * ticks). */\n                ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;\n\n                /* How many complete tick periods passed while the processor\n                 * was waiting? */\n                ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;\n\n                /* The reload value is set to whatever fraction of a single tick\n                 * period remains. */\n                portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;\n            }\n\n            /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,\n             * then set portNVIC_SYSTICK_LOAD_REG back to its standard value.  If\n             * the SysTick is not using the core clock, temporarily configure it to\n             * use the core clock.  This configuration forces the SysTick to load\n             * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next\n             * cycle of the other clock.  Then portNVIC_SYSTICK_LOAD_REG is ready\n             * to receive the standard value immediately. */\n            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n            portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n            #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )\n            {\n                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n            }\n            #else\n            {\n                /* The temporary usage of the core clock has served its purpose,\n                 * as described above.  Resume usage of the other clock. */\n                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\n\n                if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n                {\n                    /* The partial tick period already ended.  Be sure the SysTick\n                     * counts it only once. */\n                    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;\n                }\n\n                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n            }\n            #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */\n\n            /* Step the tick to account for any tick periods that elapsed. */\n            vTaskStepTick( ulCompleteTickPeriods );\n\n            /* Exit with interrupts enabled. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n        }\n    }\n#endif /* configUSE_TICKLESS_IDLE */\n/*-----------------------------------------------------------*/\n\n__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Calculate the constants required to configure the tick interrupt. */\n    #if ( configUSE_TICKLESS_IDLE == 1 )\n    {\n        ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );\n        xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;\n        ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\n    }\n    #endif /* configUSE_TICKLESS_IDLE */\n\n    /* Stop and reset the SysTick. */\n    portNVIC_SYSTICK_CTRL_REG = 0UL;\n    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n    /* Configure SysTick to interrupt at the requested rate. */\n    portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\n    portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvTaskExitError( void )\n{\n    volatile uint32_t ulDummy = 0UL;\n\n    /* A function that implements a task must not exit or attempt to return to\n     * its caller as there is nothing to return to. If a task wants to exit it\n     * should instead call vTaskDelete( NULL ). Artificially force an assert()\n     * to be triggered if configASSERT() is defined, then stop here so\n     * application writers can catch the error. */\n    configASSERT( ulCriticalNesting == ~0UL );\n    portDISABLE_INTERRUPTS();\n\n    while( ulDummy == 0 )\n    {\n        /* This file calls prvTaskExitError() after the scheduler has been\n         * started to remove a compiler warning about the function being\n         * defined but never called.  ulDummy is used purely to quieten other\n         * warnings about code appearing after this function is called - making\n         * ulDummy volatile makes the compiler think the function could return\n         * and therefore not output an 'unreachable code' warning for code that\n         * appears after it. */\n    }\n}\n/*-----------------------------------------------------------*/\n\n#if ( configENABLE_MPU == 1 )\n    static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */\n    {\n        #if defined( __ARMCC_VERSION )\n\n            /* Declaration when these variable are defined in code instead of being\n             * exported from linker scripts. */\n            extern uint32_t * __privileged_functions_start__;\n            extern uint32_t * __privileged_functions_end__;\n            extern uint32_t * __syscalls_flash_start__;\n            extern uint32_t * __syscalls_flash_end__;\n            extern uint32_t * __unprivileged_flash_start__;\n            extern uint32_t * __unprivileged_flash_end__;\n            extern uint32_t * __privileged_sram_start__;\n            extern uint32_t * __privileged_sram_end__;\n        #else /* if defined( __ARMCC_VERSION ) */\n            /* Declaration when these variable are exported from linker scripts. */\n            extern uint32_t __privileged_functions_start__[];\n            extern uint32_t __privileged_functions_end__[];\n            extern uint32_t __syscalls_flash_start__[];\n            extern uint32_t __syscalls_flash_end__[];\n            extern uint32_t __unprivileged_flash_start__[];\n            extern uint32_t __unprivileged_flash_end__[];\n            extern uint32_t __privileged_sram_start__[];\n            extern uint32_t __privileged_sram_end__[];\n        #endif /* defined( __ARMCC_VERSION ) */\n\n        /* The only permitted number of regions are 8 or 16. */\n        configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );\n\n        /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */\n        configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );\n\n        /* Check that the MPU is present. */\n        if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )\n        {\n            /* MAIR0 - Index 0. */\n            portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\n            /* MAIR0 - Index 1. */\n            portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\n\n            /* Setup privileged flash as Read Only so that privileged tasks can\n             * read it but not modify. */\n            portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_PRIVILEGED_READ_ONLY );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Setup unprivileged flash as Read Only by both privileged and\n             * unprivileged tasks. All tasks can read it but no-one can modify. */\n            portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_READ_ONLY );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Setup unprivileged syscalls flash as Read Only by both privileged\n             * and unprivileged tasks. All tasks can read it but no-one can modify. */\n            portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_READ_ONLY );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Setup RAM containing kernel data for privileged access only. */\n            portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\n                               ( portMPU_REGION_EXECUTE_NEVER );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Enable mem fault. */\n            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;\n\n            /* Enable MPU with privileged background access i.e. unmapped\n             * regions have privileged access. */\n            portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );\n        }\n    }\n#endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\n#if ( configENABLE_FPU == 1 )\n    static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */\n    {\n        #if ( configENABLE_TRUSTZONE == 1 )\n        {\n            /* Enable non-secure access to the FPU. */\n            SecureInit_EnableNSFPUAccess();\n        }\n        #endif /* configENABLE_TRUSTZONE */\n\n        /* CP10 = 11 ==> Full access to FPU i.e. both privileged and\n         * unprivileged code should be able to access FPU. CP11 should be\n         * programmed to the same value as CP10. */\n        *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |\n                            ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )\n                            );\n\n        /* ASPEN = 1 ==> Hardware should automatically preserve floating point\n         * context on exception entry and restore on exception return.\n         * LSPEN = 1 ==> Enable lazy context save of FP state. */\n        *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );\n    }\n#endif /* configENABLE_FPU */\n/*-----------------------------------------------------------*/\n\nvoid vPortYield( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Set a PendSV to request a context switch. */\n    portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\n\n    /* Barriers are normally not required but do ensure the code is\n     * completely within the specified behaviour for the architecture. */\n    __asm volatile ( \"dsb\" ::: \"memory\" );\n    __asm volatile ( \"isb\" );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */\n{\n    portDISABLE_INTERRUPTS();\n    ulCriticalNesting++;\n\n    /* Barriers are normally not required but do ensure the code is\n     * completely within the specified behaviour for the architecture. */\n    __asm volatile ( \"dsb\" ::: \"memory\" );\n    __asm volatile ( \"isb\" );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */\n{\n    configASSERT( ulCriticalNesting );\n    ulCriticalNesting--;\n\n    if( ulCriticalNesting == 0 )\n    {\n        portENABLE_INTERRUPTS();\n    }\n}\n/*-----------------------------------------------------------*/\n\nvoid SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */\n{\n    uint32_t ulPreviousMask;\n\n    ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();\n    {\n        /* Increment the RTOS tick. */\n        if( xTaskIncrementTick() != pdFALSE )\n        {\n            /* Pend a context switch. */\n            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\n        }\n    }\n    portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */\n{\n    #if ( configENABLE_MPU == 1 )\n        #if defined( __ARMCC_VERSION )\n\n            /* Declaration when these variable are defined in code instead of being\n             * exported from linker scripts. */\n            extern uint32_t * __syscalls_flash_start__;\n            extern uint32_t * __syscalls_flash_end__;\n        #else\n            /* Declaration when these variable are exported from linker scripts. */\n            extern uint32_t __syscalls_flash_start__[];\n            extern uint32_t __syscalls_flash_end__[];\n        #endif /* defined( __ARMCC_VERSION ) */\n    #endif /* configENABLE_MPU */\n\n    uint32_t ulPC;\n\n    #if ( configENABLE_TRUSTZONE == 1 )\n        uint32_t ulR0, ulR1;\n        extern TaskHandle_t pxCurrentTCB;\n        #if ( configENABLE_MPU == 1 )\n            uint32_t ulControl, ulIsTaskPrivileged;\n        #endif /* configENABLE_MPU */\n    #endif /* configENABLE_TRUSTZONE */\n    uint8_t ucSVCNumber;\n\n    /* Register are stored on the stack in the following order - R0, R1, R2, R3,\n     * R12, LR, PC, xPSR. */\n    ulPC = pulCallerStackAddress[ 6 ];\n    ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];\n\n    switch( ucSVCNumber )\n    {\n        #if ( configENABLE_TRUSTZONE == 1 )\n            case portSVC_ALLOCATE_SECURE_CONTEXT:\n\n                /* R0 contains the stack size passed as parameter to the\n                 * vPortAllocateSecureContext function. */\n                ulR0 = pulCallerStackAddress[ 0 ];\n\n                #if ( configENABLE_MPU == 1 )\n                {\n                    /* Read the CONTROL register value. */\n                    __asm volatile ( \"mrs %0, control\"  : \"=r\" ( ulControl ) );\n\n                    /* The task that raised the SVC is privileged if Bit[0]\n                     * in the CONTROL register is 0. */\n                    ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );\n\n                    /* Allocate and load a context for the secure task. */\n                    xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );\n                }\n                #else /* if ( configENABLE_MPU == 1 ) */\n                {\n                    /* Allocate and load a context for the secure task. */\n                    xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );\n                }\n                #endif /* configENABLE_MPU */\n\n                configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );\n                SecureContext_LoadContext( xSecureContext, pxCurrentTCB );\n                break;\n\n            case portSVC_FREE_SECURE_CONTEXT:\n\n                /* R0 contains TCB being freed and R1 contains the secure\n                 * context handle to be freed. */\n                ulR0 = pulCallerStackAddress[ 0 ];\n                ulR1 = pulCallerStackAddress[ 1 ];\n\n                /* Free the secure context. */\n                SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );\n                break;\n        #endif /* configENABLE_TRUSTZONE */\n\n        case portSVC_START_SCHEDULER:\n            #if ( configENABLE_TRUSTZONE == 1 )\n            {\n                /* De-prioritize the non-secure exceptions so that the\n                 * non-secure pendSV runs at the lowest priority. */\n                SecureInit_DePrioritizeNSExceptions();\n\n                /* Initialize the secure context management system. */\n                SecureContext_Init();\n            }\n            #endif /* configENABLE_TRUSTZONE */\n\n            #if ( configENABLE_FPU == 1 )\n            {\n                /* Setup the Floating Point Unit (FPU). */\n                prvSetupFPU();\n            }\n            #endif /* configENABLE_FPU */\n\n            /* Setup the context of the first task so that the first task starts\n             * executing. */\n            vRestoreContextOfFirstTask();\n            break;\n\n            #if ( configENABLE_MPU == 1 )\n                case portSVC_RAISE_PRIVILEGE:\n\n                    /* Only raise the privilege, if the svc was raised from any of\n                     * the system calls. */\n                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&\n                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )\n                    {\n                        vRaisePrivilege();\n                    }\n                    break;\n            #endif /* configENABLE_MPU */\n\n        default:\n            /* Incorrect SVC call. */\n            configASSERT( pdFALSE );\n    }\n}\n/*-----------------------------------------------------------*/\n/* *INDENT-OFF* */\n#if ( configENABLE_MPU == 1 )\n    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,\n                                         StackType_t * pxEndOfStack,\n                                         TaskFunction_t pxCode,\n                                         void * pvParameters,\n                                         BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */\n#else\n    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,\n                                         StackType_t * pxEndOfStack,\n                                         TaskFunction_t pxCode,\n                                         void * pvParameters ) /* PRIVILEGED_FUNCTION */\n#endif /* configENABLE_MPU */\n/* *INDENT-ON* */\n{\n    /* Simulate the stack frame as it would be created by a context switch\n     * interrupt. */\n    #if ( portPRELOAD_REGISTERS == 0 )\n    {\n        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\n        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\n        pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */\n        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */\n        pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */\n        *pxTopOfStack = portINITIAL_EXC_RETURN;\n\n        #if ( configENABLE_MPU == 1 )\n        {\n            pxTopOfStack--;\n\n            if( xRunPrivileged == pdTRUE )\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n            else\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n        }\n        #endif /* configENABLE_MPU */\n\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\n\n        #if ( configENABLE_TRUSTZONE == 1 )\n        {\n            pxTopOfStack--;\n            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\n        }\n        #endif /* configENABLE_TRUSTZONE */\n    }\n    #else /* portPRELOAD_REGISTERS */\n    {\n        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\n        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04 */\n        pxTopOfStack--;\n        *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN */\n\n        #if ( configENABLE_MPU == 1 )\n        {\n            pxTopOfStack--;\n\n            if( xRunPrivileged == pdTRUE )\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n            else\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n        }\n        #endif /* configENABLE_MPU */\n\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\n\n        #if ( configENABLE_TRUSTZONE == 1 )\n        {\n            pxTopOfStack--;\n            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\n        }\n        #endif /* configENABLE_TRUSTZONE */\n    }\n    #endif /* portPRELOAD_REGISTERS */\n\n    return pxTopOfStack;\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Make PendSV, CallSV and SysTick the same priority as the kernel. */\n    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;\n    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;\n\n    #if ( configENABLE_MPU == 1 )\n    {\n        /* Setup the Memory Protection Unit (MPU). */\n        prvSetupMPU();\n    }\n    #endif /* configENABLE_MPU */\n\n    /* Start the timer that generates the tick ISR. Interrupts are disabled\n     * here already. */\n    vPortSetupTimerInterrupt();\n\n    /* Initialize the critical nesting count ready for the first task. */\n    ulCriticalNesting = 0;\n\n    /* Start the first task. */\n    vStartFirstTask();\n\n    /* Should never get here as the tasks will now be executing. Call the task\n     * exit error function to prevent compiler warnings about a static function\n     * not being called in the case that the application writer overrides this\n     * functionality by defining configTASK_RETURN_ADDRESS. Call\n     * vTaskSwitchContext() so link time optimization does not remove the\n     * symbol. */\n    vTaskSwitchContext();\n    prvTaskExitError();\n\n    /* Should not get here. */\n    return 0;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Not implemented in ports where there is nothing to return to.\n     * Artificially force an assert. */\n    configASSERT( ulCriticalNesting == 1000UL );\n}\n/*-----------------------------------------------------------*/\n\n#if ( configENABLE_MPU == 1 )\n    void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,\n                                    const struct xMEMORY_REGION * const xRegions,\n                                    StackType_t * pxBottomOfStack,\n                                    uint32_t ulStackDepth )\n    {\n        uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;\n        int32_t lIndex = 0;\n\n        #if defined( __ARMCC_VERSION )\n\n            /* Declaration when these variable are defined in code instead of being\n             * exported from linker scripts. */\n            extern uint32_t * __privileged_sram_start__;\n            extern uint32_t * __privileged_sram_end__;\n        #else\n            /* Declaration when these variable are exported from linker scripts. */\n            extern uint32_t __privileged_sram_start__[];\n            extern uint32_t __privileged_sram_end__[];\n        #endif /* defined( __ARMCC_VERSION ) */\n\n        /* Setup MAIR0. */\n        xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\n        xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\n\n        /* This function is called automatically when the task is created - in\n         * which case the stack region parameters will be valid.  At all other\n         * times the stack parameters will not be valid and it is assumed that\n         * the stack region has already been configured. */\n        if( ulStackDepth > 0 )\n        {\n            ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;\n            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;\n\n            /* If the stack is within the privileged SRAM, do not protect it\n             * using a separate MPU region. This is needed because privileged\n             * SRAM is already protected using an MPU region and ARMv8-M does\n             * not allow overlapping MPU regions. */\n            if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) &&\n                ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) )\n            {\n                xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0;\n                xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0;\n            }\n            else\n            {\n                /* Define the region that allows access to the stack. */\n                ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK;\n                ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\n\n                xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |\n                                                             ( portMPU_REGION_NON_SHAREABLE ) |\n                                                             ( portMPU_REGION_READ_WRITE ) |\n                                                             ( portMPU_REGION_EXECUTE_NEVER );\n\n                xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) |\n                                                             ( portMPU_RLAR_ATTR_INDEX0 ) |\n                                                             ( portMPU_RLAR_REGION_ENABLE );\n            }\n        }\n\n        /* User supplied configurable regions. */\n        for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )\n        {\n            /* If xRegions is NULL i.e. the task has not specified any MPU\n             * region, the else part ensures that all the configurable MPU\n             * regions are invalidated. */\n            if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )\n            {\n                /* Translate the generic region definition contained in xRegions\n                 * into the ARMv8 specific MPU settings that are then stored in\n                 * xMPUSettings. */\n                ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;\n                ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;\n                ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\n\n                /* Start address. */\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |\n                                                                          ( portMPU_REGION_NON_SHAREABLE );\n\n                /* RO/RW. */\n                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )\n                {\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );\n                }\n                else\n                {\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );\n                }\n\n                /* XN. */\n                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )\n                {\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );\n                }\n\n                /* End Address. */\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |\n                                                                          ( portMPU_RLAR_REGION_ENABLE );\n\n                /* Normal memory/ Device memory. */\n                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )\n                {\n                    /* Attr1 in MAIR0 is configured as device memory. */\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;\n                }\n                else\n                {\n                    /* Attr0 in MAIR0 is configured as normal memory. */\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;\n                }\n            }\n            else\n            {\n                /* Invalidate the region. */\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;\n            }\n\n            lIndex++;\n        }\n    }\n#endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\nBaseType_t xPortIsInsideInterrupt( void )\n{\n    uint32_t ulCurrentInterrupt;\n    BaseType_t xReturn;\n\n    /* Obtain the number of the currently executing interrupt. Interrupt Program\n     * Status Register (IPSR) holds the exception number of the currently-executing\n     * exception or zero for Thread mode.*/\n    __asm volatile ( \"mrs %0, ipsr\" : \"=r\" ( ulCurrentInterrupt )::\"memory\" );\n\n    if( ulCurrentInterrupt == 0 )\n    {\n        xReturn = pdFALSE;\n    }\n    else\n    {\n        xReturn = pdTRUE;\n    }\n\n    return xReturn;\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef __PORT_ASM_H__\n#define __PORT_ASM_H__\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n\n/* MPU wrappers includes. */\n#include \"mpu_wrappers.h\"\n\n/**\n * @brief Restore the context of the first task so that the first task starts\n * executing.\n */\nvoid vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Checks whether or not the processor is privileged.\n *\n * @return 1 if the processor is already privileged, 0 otherwise.\n */\nBaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );\n\n/**\n * @brief Raises the privilege level by clearing the bit 0 of the CONTROL\n * register.\n *\n * @note This is a privileged function and should only be called from the kenrel\n * code.\n *\n * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.\n *  Bit[0] = 0 --> The processor is running privileged\n *  Bit[0] = 1 --> The processor is running unprivileged.\n */\nvoid vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\n * register.\n *\n * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.\n *  Bit[0] = 0 --> The processor is running privileged\n *  Bit[0] = 1 --> The processor is running unprivileged.\n */\nvoid vResetPrivilege( void ) __attribute__( ( naked ) );\n\n/**\n * @brief Starts the first task.\n */\nvoid vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Disables interrupts.\n */\nuint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Enables interrupts.\n */\nvoid vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief PendSV Exception handler.\n */\nvoid PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief SVC Handler.\n */\nvoid SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Allocate a Secure context for the calling task.\n *\n * @param[in] ulSecureStackSize The size of the stack to be allocated on the\n * secure side for the calling task.\n */\nvoid vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) );\n\n/**\n * @brief Free the task's secure context.\n *\n * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.\n */\nvoid vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n#endif /* __PORT_ASM_H__ */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n/* Including FreeRTOSConfig.h here will cause build errors if the header file\ncontains code not understood by the assembler - for example the 'extern' keyword.\nTo avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so\nthe code is included in C files but excluded by the preprocessor in assembly\nfiles (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */\n#include \"FreeRTOSConfig.h\"\n\n\tEXTERN pxCurrentTCB\n\tEXTERN vTaskSwitchContext\n\tEXTERN vPortSVCHandler_C\n\n\tPUBLIC xIsPrivileged\n\tPUBLIC vResetPrivilege\n\tPUBLIC vRestoreContextOfFirstTask\n\tPUBLIC vRaisePrivilege\n\tPUBLIC vStartFirstTask\n\tPUBLIC ulSetInterruptMask\n\tPUBLIC vClearInterruptMask\n\tPUBLIC PendSV_Handler\n\tPUBLIC SVC_Handler\n/*-----------------------------------------------------------*/\n\n/*---------------- Unprivileged Functions -------------------*/\n\n/*-----------------------------------------------------------*/\n\n\tSECTION .text:CODE:NOROOT(2)\n\tTHUMB\n/*-----------------------------------------------------------*/\n\nxIsPrivileged:\n\tmrs r0, control\t\t\t\t\t\t\t/* r0 = CONTROL. */\n\ttst r0, #1\t\t\t\t\t\t\t\t/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\n\tite ne\n\tmovne r0, #0\t\t\t\t\t\t\t/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\n\tmoveq r0, #1\t\t\t\t\t\t\t/* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */\n\tbx lr\t\t\t\t\t\t\t\t\t/* Return. */\n/*-----------------------------------------------------------*/\n\nvResetPrivilege:\n\tmrs r0, control\t\t\t\t\t\t\t/* r0 = CONTROL. */\n\torr r0, r0, #1\t\t\t\t\t\t\t/* r0 = r0 | 1. */\n\tmsr control, r0\t\t\t\t\t\t\t/* CONTROL = r0. */\n\tbx lr\t\t\t\t\t\t\t\t\t/* Return to the caller. */\n/*-----------------------------------------------------------*/\n\n/*----------------- Privileged Functions --------------------*/\n\n/*-----------------------------------------------------------*/\n\n\tSECTION privileged_functions:CODE:NOROOT(2)\n\tTHUMB\n/*-----------------------------------------------------------*/\n\nvRestoreContextOfFirstTask:\n\tldr  r2, =pxCurrentTCB\t\t\t\t\t/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n\tldr  r1, [r2]\t\t\t\t\t\t\t/* Read pxCurrentTCB. */\n\tldr  r0, [r1]\t\t\t\t\t\t\t/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\n\n#if ( configENABLE_MPU == 1 )\n\tdmb\t\t\t\t\t\t\t\t\t\t/* Complete outstanding transfers before disabling MPU. */\n\tldr r2, =0xe000ed94\t\t\t\t\t\t/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n\tldr r4, [r2]\t\t\t\t\t\t\t/* Read the value of MPU_CTRL. */\n\tbic r4, r4, #1\t\t\t\t\t\t\t/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\n\tstr r4, [r2]\t\t\t\t\t\t\t/* Disable MPU. */\n\n\tadds r1, #4\t\t\t\t\t\t\t\t/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\n\tldr r3, [r1]\t\t\t\t\t\t\t/* r3 = *r1 i.e. r3 = MAIR0. */\n\tldr r2, =0xe000edc0\t\t\t\t\t\t/* r2 = 0xe000edc0 [Location of MAIR0]. */\n\tstr r3, [r2]\t\t\t\t\t\t\t/* Program MAIR0. */\n\tldr r2, =0xe000ed98\t\t\t\t\t\t/* r2 = 0xe000ed98 [Location of RNR]. */\n\tmovs r3, #4\t\t\t\t\t\t\t\t/* r3 = 4. */\n\tstr r3, [r2]\t\t\t\t\t\t\t/* Program RNR = 4. */\n\tadds r1, #4\t\t\t\t\t\t\t\t/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\n\tldr r2, =0xe000ed9c\t\t\t\t\t\t/* r2 = 0xe000ed9c [Location of RBAR]. */\n\tldmia r1!, {r4-r11}\t\t\t\t\t\t/* Read 4 sets of RBAR/RLAR registers from TCB. */\n\tstmia r2!, {r4-r11}\t\t\t\t\t\t/* Write 4 set of RBAR/RLAR registers using alias registers. */\n\n\tldr r2, =0xe000ed94\t\t\t\t\t\t/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n\tldr r4, [r2]\t\t\t\t\t\t\t/* Read the value of MPU_CTRL. */\n\torr r4, r4, #1\t\t\t\t\t\t\t/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\n\tstr r4, [r2]\t\t\t\t\t\t\t/* Enable MPU. */\n\tdsb\t\t\t\t\t\t\t\t\t\t/* Force memory writes before continuing. */\n#endif /* configENABLE_MPU */\n\n#if ( configENABLE_MPU == 1 )\n\tldm  r0!, {r1-r3}\t\t\t\t\t\t/* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */\n\tmsr  psplim, r1\t\t\t\t\t\t\t/* Set this task's PSPLIM value. */\n\tmsr  control, r2\t\t\t\t\t\t/* Set this task's CONTROL value. */\n\tadds r0, #32\t\t\t\t\t\t\t/* Discard everything up to r0. */\n\tmsr  psp, r0\t\t\t\t\t\t\t/* This is now the new top of stack to use in the task. */\n\tisb\n\tmov  r0, #0\n\tmsr  basepri, r0\t\t\t\t\t\t/* Ensure that interrupts are enabled when the first task starts. */\n\tbx   r3\t\t\t\t\t\t\t\t\t/* Finally, branch to EXC_RETURN. */\n#else /* configENABLE_MPU */\n\tldm  r0!, {r1-r2}\t\t\t\t\t\t/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */\n\tmsr  psplim, r1\t\t\t\t\t\t\t/* Set this task's PSPLIM value. */\n\tmovs r1, #2\t\t\t\t\t\t\t\t/* r1 = 2. */\n\tmsr  CONTROL, r1\t\t\t\t\t\t/* Switch to use PSP in the thread mode. */\n\tadds r0, #32\t\t\t\t\t\t\t/* Discard everything up to r0. */\n\tmsr  psp, r0\t\t\t\t\t\t\t/* This is now the new top of stack to use in the task. */\n\tisb\n\tmov  r0, #0\n\tmsr  basepri, r0\t\t\t\t\t\t/* Ensure that interrupts are enabled when the first task starts. */\n\tbx   r2\t\t\t\t\t\t\t\t\t/* Finally, branch to EXC_RETURN. */\n#endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\nvRaisePrivilege:\n\tmrs  r0, control\t\t\t\t\t\t/* Read the CONTROL register. */\n\tbic r0, r0, #1\t\t\t\t\t\t\t/* Clear the bit 0. */\n\tmsr  control, r0\t\t\t\t\t\t/* Write back the new CONTROL value. */\n\tbx lr\t\t\t\t\t\t\t\t\t/* Return to the caller. */\n/*-----------------------------------------------------------*/\n\nvStartFirstTask:\n\tldr r0, =0xe000ed08\t\t\t\t\t\t/* Use the NVIC offset register to locate the stack. */\n\tldr r0, [r0]\t\t\t\t\t\t\t/* Read the VTOR register which gives the address of vector table. */\n\tldr r0, [r0]\t\t\t\t\t\t\t/* The first entry in vector table is stack pointer. */\n\tmsr msp, r0\t\t\t\t\t\t\t\t/* Set the MSP back to the start of the stack. */\n\tcpsie i\t\t\t\t\t\t\t\t\t/* Globally enable interrupts. */\n\tcpsie f\n\tdsb\n\tisb\n\tsvc 2\t\t\t\t\t\t\t\t\t/* System call to start the first task. portSVC_START_SCHEDULER = 2. */\n/*-----------------------------------------------------------*/\n\nulSetInterruptMask:\n\tmrs r0, basepri\t\t\t\t\t\t\t/* r0 = basepri. Return original basepri value. */\n\tmov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY\n\tmsr basepri, r1\t\t\t\t\t\t\t/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */\n\tdsb\n\tisb\n\tbx lr\t\t\t\t\t\t\t\t\t/* Return. */\n/*-----------------------------------------------------------*/\n\nvClearInterruptMask:\n\tmsr basepri, r0\t\t\t\t\t\t\t/* basepri = ulMask. */\n\tdsb\n\tisb\n\tbx lr\t\t\t\t\t\t\t\t\t/* Return. */\n/*-----------------------------------------------------------*/\n\nPendSV_Handler:\n\tmrs r0, psp\t\t\t\t\t\t\t\t/* Read PSP in r0. */\n#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )\n\ttst lr, #0x10\t\t\t\t\t\t\t/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */\n\tit eq\n\tvstmdbeq r0!, {s16-s31}\t\t\t\t\t/* Store the additional FP context registers which are not saved automatically. */\n#endif /* configENABLE_FPU || configENABLE_MVE */\n#if ( configENABLE_MPU == 1 )\n\tmrs r1, psplim\t\t\t\t\t\t\t/* r1 = PSPLIM. */\n\tmrs r2, control\t\t\t\t\t\t\t/* r2 = CONTROL. */\n\tmov r3, lr\t\t\t\t\t\t\t\t/* r3 = LR/EXC_RETURN. */\n\tstmdb r0!, {r1-r11}\t\t\t\t\t\t/* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */\n#else /* configENABLE_MPU */\n\tmrs r2, psplim\t\t\t\t\t\t\t/* r2 = PSPLIM. */\n\tmov r3, lr\t\t\t\t\t\t\t\t/* r3 = LR/EXC_RETURN. */\n\tstmdb r0!, {r2-r11}\t\t\t\t\t\t/* Store on the stack - PSPLIM, LR and registers that are not automatically. */\n#endif /* configENABLE_MPU */\n\n\tldr r2, =pxCurrentTCB\t\t\t\t\t/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n\tldr r1, [r2]\t\t\t\t\t\t\t/* Read pxCurrentTCB. */\n\tstr r0, [r1]\t\t\t\t\t\t\t/* Save the new top of stack in TCB. */\n\n\tmov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY\n\tmsr basepri, r0\t\t\t\t\t\t\t/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */\n\tdsb\n\tisb\n\tbl vTaskSwitchContext\n\tmov r0, #0\t\t\t\t\t\t\t\t/* r0 = 0. */\n\tmsr basepri, r0\t\t\t\t\t\t\t/* Enable interrupts. */\n\n\tldr r2, =pxCurrentTCB\t\t\t\t\t/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n\tldr r1, [r2]\t\t\t\t\t\t\t/* Read pxCurrentTCB. */\n\tldr r0, [r1]\t\t\t\t\t\t\t/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */\n\n#if ( configENABLE_MPU == 1 )\n\tdmb\t\t\t\t\t\t\t\t\t\t/* Complete outstanding transfers before disabling MPU. */\n\tldr r2, =0xe000ed94\t\t\t\t\t\t/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n\tldr r4, [r2]\t\t\t\t\t\t\t/* Read the value of MPU_CTRL. */\n\tbic r4, r4, #1\t\t\t\t\t\t\t/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\n\tstr r4, [r2]\t\t\t\t\t\t\t/* Disable MPU. */\n\n\tadds r1, #4\t\t\t\t\t\t\t\t/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\n\tldr r3, [r1]\t\t\t\t\t\t\t/* r3 = *r1 i.e. r3 = MAIR0. */\n\tldr r2, =0xe000edc0\t\t\t\t\t\t/* r2 = 0xe000edc0 [Location of MAIR0]. */\n\tstr r3, [r2]\t\t\t\t\t\t\t/* Program MAIR0. */\n\tldr r2, =0xe000ed98\t\t\t\t\t\t/* r2 = 0xe000ed98 [Location of RNR]. */\n\tmovs r3, #4\t\t\t\t\t\t\t\t/* r3 = 4. */\n\tstr r3, [r2]\t\t\t\t\t\t\t/* Program RNR = 4. */\n\tadds r1, #4\t\t\t\t\t\t\t\t/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\n\tldr r2, =0xe000ed9c\t\t\t\t\t\t/* r2 = 0xe000ed9c [Location of RBAR]. */\n\tldmia r1!, {r4-r11}\t\t\t\t\t\t/* Read 4 sets of RBAR/RLAR registers from TCB. */\n\tstmia r2!, {r4-r11}\t\t\t\t\t\t/* Write 4 set of RBAR/RLAR registers using alias registers. */\n\n\tldr r2, =0xe000ed94\t\t\t\t\t\t/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n\tldr r4, [r2]\t\t\t\t\t\t\t/* Read the value of MPU_CTRL. */\n\torr r4, r4, #1\t\t\t\t\t\t\t/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\n\tstr r4, [r2]\t\t\t\t\t\t\t/* Enable MPU. */\n\tdsb\t\t\t\t\t\t\t\t\t\t/* Force memory writes before continuing. */\n#endif /* configENABLE_MPU */\n\n#if ( configENABLE_MPU == 1 )\n\tldmia r0!, {r1-r11}\t\t\t\t\t\t/* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */\n#else /* configENABLE_MPU */\n\tldmia r0!, {r2-r11}\t\t\t\t\t\t/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */\n#endif /* configENABLE_MPU */\n\n#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )\n\ttst r3, #0x10\t\t\t\t\t\t\t/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */\n\tit eq\n\tvldmiaeq r0!, {s16-s31}\t\t\t\t\t/* Restore the additional FP context registers which are not restored automatically. */\n#endif /* configENABLE_FPU || configENABLE_MVE */\n\n #if ( configENABLE_MPU == 1 )\n\tmsr psplim, r1\t\t\t\t\t\t\t/* Restore the PSPLIM register value for the task. */\n\tmsr control, r2\t\t\t\t\t\t\t/* Restore the CONTROL register value for the task. */\n#else /* configENABLE_MPU */\n\tmsr psplim, r2\t\t\t\t\t\t\t/* Restore the PSPLIM register value for the task. */\n#endif /* configENABLE_MPU */\n\tmsr psp, r0\t\t\t\t\t\t\t\t/* Remember the new top of stack for the task. */\n\tbx r3\n/*-----------------------------------------------------------*/\n\nSVC_Handler:\n\ttst lr, #4\n\tite eq\n\tmrseq r0, msp\n\tmrsne r0, psp\n\tb vPortSVCHandler_C\n/*-----------------------------------------------------------*/\n\n\tEND\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef PORTMACRO_H\n#define PORTMACRO_H\n\n#ifdef __cplusplus\n    extern \"C\" {\n#endif\n\n#include \"portmacrocommon.h\"\n\n/*------------------------------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the given hardware\n * and compiler.\n *\n * These settings should not be altered.\n *------------------------------------------------------------------------------\n */\n\n/**\n * Architecture specifics.\n */\n#define portARCH_NAME                       \"Cortex-M33\"\n#define portDONT_DISCARD                    __root\n/*-----------------------------------------------------------*/\n\n#if( configTOTAL_MPU_REGIONS == 16 )\n    #error 16 MPU regions are not yet supported for this port.\n#endif\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Critical section management.\n */\n#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()\n#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )\n/*-----------------------------------------------------------*/\n\n/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in\n * the source code because to do so would cause other compilers to generate\n * warnings. */\n#pragma diag_suppress=Be006\n#pragma diag_suppress=Pa082\n/*-----------------------------------------------------------*/\n\n#ifdef __cplusplus\n    }\n#endif\n\n#endif /* PORTMACRO_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef PORTMACROCOMMON_H\n    #define PORTMACROCOMMON_H\n\n    #ifdef __cplusplus\n        extern \"C\" {\n    #endif\n\n/*------------------------------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the given hardware\n * and compiler.\n *\n * These settings should not be altered.\n *------------------------------------------------------------------------------\n */\n\n    #ifndef configENABLE_FPU\n        #error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.\n    #endif /* configENABLE_FPU */\n\n    #ifndef configENABLE_MPU\n        #error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.\n    #endif /* configENABLE_MPU */\n\n    #ifndef configENABLE_TRUSTZONE\n        #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.\n    #endif /* configENABLE_TRUSTZONE */\n\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Type definitions.\n */\n    #define portCHAR          char\n    #define portFLOAT         float\n    #define portDOUBLE        double\n    #define portLONG          long\n    #define portSHORT         short\n    #define portSTACK_TYPE    uint32_t\n    #define portBASE_TYPE     long\n\n    typedef portSTACK_TYPE   StackType_t;\n    typedef long             BaseType_t;\n    typedef unsigned long    UBaseType_t;\n\n    #if ( configUSE_16_BIT_TICKS == 1 )\n        typedef uint16_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffff\n    #else\n        typedef uint32_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL\n\n/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\n * not need to be guarded with a critical section. */\n        #define portTICK_TYPE_IS_ATOMIC    1\n    #endif\n/*-----------------------------------------------------------*/\n\n/**\n * Architecture specifics.\n */\n    #define portSTACK_GROWTH                   ( -1 )\n    #define portTICK_PERIOD_MS                 ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\n    #define portBYTE_ALIGNMENT                 8\n    #define portNOP()\n    #define portINLINE                         __inline\n    #ifndef portFORCE_INLINE\n        #define portFORCE_INLINE               inline __attribute__( ( always_inline ) )\n    #endif\n    #define portHAS_STACK_OVERFLOW_CHECKING    1\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Extern declarations.\n */\n    extern BaseType_t xPortIsInsideInterrupt( void );\n\n    extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;\n\n    extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;\n    extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;\n\n    extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\n    extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\n\n    #if ( configENABLE_TRUSTZONE == 1 )\n        extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */\n        extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;\n    #endif /* configENABLE_TRUSTZONE */\n\n    #if ( configENABLE_MPU == 1 )\n        extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;\n        extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;\n    #endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\n/**\n * @brief MPU specific constants.\n */\n    #if ( configENABLE_MPU == 1 )\n        #define portUSING_MPU_WRAPPERS    1\n        #define portPRIVILEGE_BIT         ( 0x80000000UL )\n    #else\n        #define portPRIVILEGE_BIT         ( 0x0UL )\n    #endif /* configENABLE_MPU */\n\n/* MPU settings that can be overriden in FreeRTOSConfig.h. */\n#ifndef configTOTAL_MPU_REGIONS\n    /* Define to 8 for backward compatibility. */\n    #define configTOTAL_MPU_REGIONS       ( 8UL )\n#endif\n\n/* MPU regions. */\n    #define portPRIVILEGED_FLASH_REGION                   ( 0UL )\n    #define portUNPRIVILEGED_FLASH_REGION                 ( 1UL )\n    #define portUNPRIVILEGED_SYSCALLS_REGION              ( 2UL )\n    #define portPRIVILEGED_RAM_REGION                     ( 3UL )\n    #define portSTACK_REGION                              ( 4UL )\n    #define portFIRST_CONFIGURABLE_REGION                 ( 5UL )\n    #define portLAST_CONFIGURABLE_REGION                  ( configTOTAL_MPU_REGIONS - 1UL )\n    #define portNUM_CONFIGURABLE_REGIONS                  ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )\n    #define portTOTAL_NUM_REGIONS                         ( portNUM_CONFIGURABLE_REGIONS + 1 )   /* Plus one to make space for the stack region. */\n\n/* Device memory attributes used in MPU_MAIR registers.\n *\n * 8-bit values encoded as follows:\n *  Bit[7:4] - 0000 - Device Memory\n *  Bit[3:2] - 00 --> Device-nGnRnE\n *\t\t\t\t01 --> Device-nGnRE\n *\t\t\t\t10 --> Device-nGRE\n *\t\t\t\t11 --> Device-GRE\n *  Bit[1:0] - 00, Reserved.\n */\n    #define portMPU_DEVICE_MEMORY_nGnRnE                  ( 0x00 )   /* 0000 0000 */\n    #define portMPU_DEVICE_MEMORY_nGnRE                   ( 0x04 )   /* 0000 0100 */\n    #define portMPU_DEVICE_MEMORY_nGRE                    ( 0x08 )   /* 0000 1000 */\n    #define portMPU_DEVICE_MEMORY_GRE                     ( 0x0C )   /* 0000 1100 */\n\n/* Normal memory attributes used in MPU_MAIR registers. */\n    #define portMPU_NORMAL_MEMORY_NON_CACHEABLE           ( 0x44 )   /* Non-cacheable. */\n    #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE    ( 0xFF )   /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */\n\n/* Attributes used in MPU_RBAR registers. */\n    #define portMPU_REGION_NON_SHAREABLE                  ( 0UL << 3UL )\n    #define portMPU_REGION_INNER_SHAREABLE                ( 1UL << 3UL )\n    #define portMPU_REGION_OUTER_SHAREABLE                ( 2UL << 3UL )\n\n    #define portMPU_REGION_PRIVILEGED_READ_WRITE          ( 0UL << 1UL )\n    #define portMPU_REGION_READ_WRITE                     ( 1UL << 1UL )\n    #define portMPU_REGION_PRIVILEGED_READ_ONLY           ( 2UL << 1UL )\n    #define portMPU_REGION_READ_ONLY                      ( 3UL << 1UL )\n\n    #define portMPU_REGION_EXECUTE_NEVER                  ( 1UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Settings to define an MPU region.\n */\n    typedef struct MPURegionSettings\n    {\n        uint32_t ulRBAR; /**< RBAR for the region. */\n        uint32_t ulRLAR; /**< RLAR for the region. */\n    } MPURegionSettings_t;\n\n/**\n * @brief MPU settings as stored in the TCB.\n */\n    typedef struct MPU_SETTINGS\n    {\n        uint32_t ulMAIR0;                                              /**< MAIR0 for the task containing attributes for all the 4 per task regions. */\n        MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */\n    } xMPU_SETTINGS;\n/*-----------------------------------------------------------*/\n\n/**\n * @brief SVC numbers.\n */\n    #define portSVC_ALLOCATE_SECURE_CONTEXT    0\n    #define portSVC_FREE_SECURE_CONTEXT        1\n    #define portSVC_START_SCHEDULER            2\n    #define portSVC_RAISE_PRIVILEGE            3\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Scheduler utilities.\n */\n    #define portYIELD()                                 vPortYield()\n    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )\n    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )\n    #define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )\n    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Critical section management.\n */\n    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulSetInterruptMask()\n    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vClearInterruptMask( x )\n    #define portENTER_CRITICAL()                      vPortEnterCritical()\n    #define portEXIT_CRITICAL()                       vPortExitCritical()\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Tickless idle/low power functionality.\n */\n    #ifndef portSUPPRESS_TICKS_AND_SLEEP\n        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );\n        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )\n    #endif\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Task function macros as described on the FreeRTOS.org WEB site.\n */\n    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )\n    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )\n/*-----------------------------------------------------------*/\n\n    #if ( configENABLE_TRUSTZONE == 1 )\n\n/**\n * @brief Allocate a secure context for the task.\n *\n * Tasks are not created with a secure context. Any task that is going to call\n * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a\n * secure context before it calls any secure function.\n *\n * @param[in] ulSecureStackSize The size of the secure stack to be allocated.\n */\n        #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )\n\n/**\n * @brief Called when a task is deleted to delete the task's secure context,\n * if it has one.\n *\n * @param[in] pxTCB The TCB of the task being deleted.\n */\n        #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )\n    #endif /* configENABLE_TRUSTZONE */\n/*-----------------------------------------------------------*/\n\n    #if ( configENABLE_MPU == 1 )\n\n/**\n * @brief Checks whether or not the processor is privileged.\n *\n * @return 1 if the processor is already privileged, 0 otherwise.\n */\n        #define portIS_PRIVILEGED()      xIsPrivileged()\n\n/**\n * @brief Raise an SVC request to raise privilege.\n *\n * The SVC handler checks that the SVC was raised from a system call and only\n * then it raises the privilege. If this is called from any other place,\n * the privilege is not raised.\n */\n        #define portRAISE_PRIVILEGE()    __asm volatile ( \"svc %0 \\n\" ::\"i\" ( portSVC_RAISE_PRIVILEGE ) : \"memory\" );\n\n/**\n * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\n * register.\n */\n        #define portRESET_PRIVILEGE()    vResetPrivilege()\n    #else\n        #define portIS_PRIVILEGED()\n        #define portRAISE_PRIVILEGE()\n        #define portRESET_PRIVILEGE()\n    #endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Barriers.\n */\n    #define portMEMORY_BARRIER()    __asm volatile ( \"\" ::: \"memory\" )\n/*-----------------------------------------------------------*/\n\n    #ifdef __cplusplus\n        }\n    #endif\n\n#endif /* PORTMACROCOMMON_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM4F/port.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/*-----------------------------------------------------------\n* Implementation of functions defined in portable.h for the ARM CM4F port.\n*----------------------------------------------------------*/\n\n/* IAR includes. */\n#include <intrinsics.h>\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n#ifndef __ARMVFP__\n    #error This port can only be used when the project options are configured to enable hardware floating point support.\n#endif\n\n#if ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 )\n    #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\n#endif\n\n/* Constants required to manipulate the core.  Registers first... */\n#define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )\n#define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )\n#define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )\n#define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )\n/* ...then bits in the registers. */\n#define portNVIC_SYSTICK_CLK_BIT              ( 1UL << 2UL )\n#define portNVIC_SYSTICK_INT_BIT              ( 1UL << 1UL )\n#define portNVIC_SYSTICK_ENABLE_BIT           ( 1UL << 0UL )\n#define portNVIC_SYSTICK_COUNT_FLAG_BIT       ( 1UL << 16UL )\n#define portNVIC_PENDSVCLEAR_BIT              ( 1UL << 27UL )\n#define portNVIC_PEND_SYSTICK_SET_BIT         ( 1UL << 26UL )\n#define portNVIC_PEND_SYSTICK_CLEAR_BIT       ( 1UL << 25UL )\n\n/* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7\n * r0p1 port. */\n#define portCPUID                             ( *( ( volatile uint32_t * ) 0xE000ed00 ) )\n#define portCORTEX_M7_r0p1_ID                 ( 0x410FC271UL )\n#define portCORTEX_M7_r0p0_ID                 ( 0x410FC270UL )\n\n#define portNVIC_PENDSV_PRI                   ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\n#define portNVIC_SYSTICK_PRI                  ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\n\n/* Constants required to check the validity of an interrupt priority. */\n#define portFIRST_USER_INTERRUPT_NUMBER       ( 16 )\n#define portNVIC_IP_REGISTERS_OFFSET_16       ( 0xE000E3F0 )\n#define portAIRCR_REG                         ( *( ( volatile uint32_t * ) 0xE000ED0C ) )\n#define portMAX_8_BIT_VALUE                   ( ( uint8_t ) 0xff )\n#define portTOP_BIT_OF_BYTE                   ( ( uint8_t ) 0x80 )\n#define portMAX_PRIGROUP_BITS                 ( ( uint8_t ) 7 )\n#define portPRIORITY_GROUP_MASK               ( 0x07UL << 8UL )\n#define portPRIGROUP_SHIFT                    ( 8UL )\n\n/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */\n#define portVECTACTIVE_MASK                   ( 0xFFUL )\n\n/* Constants required to manipulate the VFP. */\n#define portFPCCR                             ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */\n#define portASPEN_AND_LSPEN_BITS              ( 0x3UL << 30UL )\n\n/* Constants required to set up the initial stack. */\n#define portINITIAL_XPSR                      ( 0x01000000 )\n#define portINITIAL_EXC_RETURN                ( 0xfffffffd )\n\n/* The systick is a 24-bit counter. */\n#define portMAX_24_BIT_NUMBER                 ( 0xffffffUL )\n\n/* A fiddle factor to estimate the number of SysTick counts that would have\n * occurred while the SysTick counter is stopped during tickless idle\n * calculations. */\n#define portMISSED_COUNTS_FACTOR              ( 94UL )\n\n/* For strict compliance with the Cortex-M spec the task start address should\n * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */\n#define portSTART_ADDRESS_MASK                ( ( StackType_t ) 0xfffffffeUL )\n\n/* Let the user override the default SysTick clock rate.  If defined by the\n * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the\n * configuration register. */\n#ifndef configSYSTICK_CLOCK_HZ\n    #define configSYSTICK_CLOCK_HZ             ( configCPU_CLOCK_HZ )\n    /* Ensure the SysTick is clocked at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( portNVIC_SYSTICK_CLK_BIT )\n#else\n    /* Select the option to clock SysTick not at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( 0 )\n#endif\n\n/*\n * Setup the timer to generate the tick interrupts.  The implementation in this\n * file is weak to allow application writers to change the timer used to\n * generate the tick interrupt.\n */\nvoid vPortSetupTimerInterrupt( void );\n\n/*\n * Exception handlers.\n */\nvoid xPortSysTickHandler( void );\n\n/*\n * Start first task is a separate function so it can be tested in isolation.\n */\nextern void vPortStartFirstTask( void );\n\n/*\n * Turn the VFP on.\n */\nextern void vPortEnableVFP( void );\n\n/*\n * Used to catch tasks that attempt to return from their implementing function.\n */\nstatic void prvTaskExitError( void );\n\n/*-----------------------------------------------------------*/\n\n/* Each task maintains its own interrupt status in the critical nesting\n * variable. */\nstatic UBaseType_t uxCriticalNesting = 0xaaaaaaaa;\n\n/*\n * The number of SysTick increments that make up one tick period.\n */\n#if ( configUSE_TICKLESS_IDLE == 1 )\n    static uint32_t ulTimerCountsForOneTick = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n\n/*\n * The maximum number of tick periods that can be suppressed is limited by the\n * 24 bit resolution of the SysTick timer.\n */\n#if ( configUSE_TICKLESS_IDLE == 1 )\n    static uint32_t xMaximumPossibleSuppressedTicks = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n\n/*\n * Compensate for the CPU cycles that pass while the SysTick is stopped (low\n * power functionality only.\n */\n#if ( configUSE_TICKLESS_IDLE == 1 )\n    static uint32_t ulStoppedTimerCompensation = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n\n/*\n * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure\n * FreeRTOS API functions are not called from interrupts that have been assigned\n * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.\n */\n#if ( configASSERT_DEFINED == 1 )\n    static uint8_t ucMaxSysCallPriority = 0;\n    static uint32_t ulMaxPRIGROUPValue = 0;\n    static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;\n#endif /* configASSERT_DEFINED */\n\n/*-----------------------------------------------------------*/\n\n/*\n * See header file for description.\n */\nStackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,\n                                     TaskFunction_t pxCode,\n                                     void * pvParameters )\n{\n    /* Simulate the stack frame as it would be created by a context switch\n     * interrupt. */\n\n    /* Offset added to account for the way the MCU uses the stack on entry/exit\n     * of interrupts, and to ensure alignment. */\n    pxTopOfStack--;\n\n    *pxTopOfStack = portINITIAL_XPSR;                                    /* xPSR */\n    pxTopOfStack--;\n    *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */\n    pxTopOfStack--;\n    *pxTopOfStack = ( StackType_t ) prvTaskExitError;                    /* LR */\n\n    /* Save code space by skipping register initialisation. */\n    pxTopOfStack -= 5;                            /* R12, R3, R2 and R1. */\n    *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\n\n    /* A save method is being used that requires each task to maintain its\n     * own exec return value. */\n    pxTopOfStack--;\n    *pxTopOfStack = portINITIAL_EXC_RETURN;\n\n    pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */\n\n    return pxTopOfStack;\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvTaskExitError( void )\n{\n    /* A function that implements a task must not exit or attempt to return to\n     * its caller as there is nothing to return to.  If a task wants to exit it\n     * should instead call vTaskDelete( NULL ).\n     *\n     * Artificially force an assert() to be triggered if configASSERT() is\n     * defined, then stop here so application writers can catch the error. */\n    configASSERT( uxCriticalNesting == ~0UL );\n    portDISABLE_INTERRUPTS();\n\n    for( ; ; )\n    {\n    }\n}\n/*-----------------------------------------------------------*/\n\n/*\n * See header file for description.\n */\nBaseType_t xPortStartScheduler( void )\n{\n    /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.\n     * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\n    configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );\n\n    /* This port can be used on all revisions of the Cortex-M7 core other than\n     * the r0p1 parts.  r0p1 parts should use the port from the\n     * /source/portable/GCC/ARM_CM7/r0p1 directory. */\n    configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );\n    configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );\n\n    #if ( configASSERT_DEFINED == 1 )\n    {\n        volatile uint32_t ulOriginalPriority;\n        volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\n        volatile uint8_t ucMaxPriorityValue;\n\n        /* Determine the maximum priority from which ISR safe FreeRTOS API\n         * functions can be called.  ISR safe functions are those that end in\n         * \"FromISR\".  FreeRTOS maintains separate thread and ISR API functions to\n         * ensure interrupt entry is as fast and simple as possible.\n         *\n         * Save the interrupt priority value that is about to be clobbered. */\n        ulOriginalPriority = *pucFirstUserPriorityRegister;\n\n        /* Determine the number of priority bits available.  First write to all\n         * possible bits. */\n        *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\n\n        /* Read the value back to see how many bits stuck. */\n        ucMaxPriorityValue = *pucFirstUserPriorityRegister;\n\n        /* Use the same mask on the maximum system call priority. */\n        ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;\n\n        /* Calculate the maximum acceptable priority group value for the number\n         * of bits read back. */\n        ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;\n\n        while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )\n        {\n            ulMaxPRIGROUPValue--;\n            ucMaxPriorityValue <<= ( uint8_t ) 0x01;\n        }\n\n        #ifdef __NVIC_PRIO_BITS\n        {\n            /* Check the CMSIS configuration that defines the number of\n             * priority bits matches the number of priority bits actually queried\n             * from the hardware. */\n            configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );\n        }\n        #endif\n\n        #ifdef configPRIO_BITS\n        {\n            /* Check the FreeRTOS configuration that defines the number of\n             * priority bits matches the number of priority bits actually queried\n             * from the hardware. */\n            configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );\n        }\n        #endif\n\n        /* Shift the priority group value back to its position within the AIRCR\n         * register. */\n        ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;\n        ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;\n\n        /* Restore the clobbered interrupt priority register to its original\n         * value. */\n        *pucFirstUserPriorityRegister = ulOriginalPriority;\n    }\n    #endif /* configASSERT_DEFINED */\n\n    /* Make PendSV and SysTick the lowest priority interrupts. */\n    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;\n    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;\n\n    /* Start the timer that generates the tick ISR.  Interrupts are disabled\n     * here already. */\n    vPortSetupTimerInterrupt();\n\n    /* Initialise the critical nesting count ready for the first task. */\n    uxCriticalNesting = 0;\n\n    /* Ensure the VFP is enabled - it should be anyway. */\n    vPortEnableVFP();\n\n    /* Lazy save always. */\n    *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;\n\n    /* Start the first task. */\n    vPortStartFirstTask();\n\n    /* Should not get here! */\n    return 0;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEndScheduler( void )\n{\n    /* Not implemented in ports where there is nothing to return to.\n     * Artificially force an assert. */\n    configASSERT( uxCriticalNesting == 1000UL );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEnterCritical( void )\n{\n    portDISABLE_INTERRUPTS();\n    uxCriticalNesting++;\n\n    /* This is not the interrupt safe version of the enter critical function so\n     * assert() if it is being called from an interrupt context.  Only API\n     * functions that end in \"FromISR\" can be used in an interrupt.  Only assert if\n     * the critical nesting count is 1 to protect against recursive calls if the\n     * assert function also uses a critical section. */\n    if( uxCriticalNesting == 1 )\n    {\n        configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );\n    }\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortExitCritical( void )\n{\n    configASSERT( uxCriticalNesting );\n    uxCriticalNesting--;\n\n    if( uxCriticalNesting == 0 )\n    {\n        portENABLE_INTERRUPTS();\n    }\n}\n/*-----------------------------------------------------------*/\n\nvoid xPortSysTickHandler( void )\n{\n    /* The SysTick runs at the lowest interrupt priority, so when this interrupt\n     * executes all interrupts must be unmasked.  There is therefore no need to\n     * save and then restore the interrupt mask value as its value is already\n     * known. */\n    portDISABLE_INTERRUPTS();\n    {\n        /* Increment the RTOS tick. */\n        if( xTaskIncrementTick() != pdFALSE )\n        {\n            /* A context switch is required.  Context switching is performed in\n             * the PendSV interrupt.  Pend the PendSV interrupt. */\n            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\n        }\n    }\n    portENABLE_INTERRUPTS();\n}\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TICKLESS_IDLE == 1 )\n\n    __weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )\n    {\n        uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;\n        TickType_t xModifiableIdleTime;\n\n        /* Make sure the SysTick reload value does not overflow the counter. */\n        if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\n        {\n            xExpectedIdleTime = xMaximumPossibleSuppressedTicks;\n        }\n\n        /* Enter a critical section but don't use the taskENTER_CRITICAL()\n         * method as that will mask interrupts that should exit sleep mode. */\n        __disable_interrupt();\n        __DSB();\n        __ISB();\n\n        /* If a context switch is pending or a task is waiting for the scheduler\n         * to be unsuspended then abandon the low power entry. */\n        if( eTaskConfirmSleepModeStatus() == eAbortSleep )\n        {\n            /* Re-enable interrupts - see comments above the __disable_interrupt()\n             * call above. */\n            __enable_interrupt();\n        }\n        else\n        {\n            /* Stop the SysTick momentarily.  The time the SysTick is stopped for\n             * is accounted for as best it can be, but using the tickless mode will\n             * inevitably result in some tiny drift of the time maintained by the\n             * kernel with respect to calendar time. */\n            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );\n\n            /* Use the SysTick current-value register to determine the number of\n             * SysTick decrements remaining until the next tick interrupt.  If the\n             * current-value register is zero, then there are actually\n             * ulTimerCountsForOneTick decrements remaining, not zero, because the\n             * SysTick requests the interrupt when decrementing from 1 to 0. */\n            ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n\n            if( ulSysTickDecrementsLeft == 0 )\n            {\n                ulSysTickDecrementsLeft = ulTimerCountsForOneTick;\n            }\n\n            /* Calculate the reload value required to wait xExpectedIdleTime\n             * tick periods.  -1 is used because this code normally executes part\n             * way through the first tick period.  But if the SysTick IRQ is now\n             * pending, then clear the IRQ, suppressing the first tick, and correct\n             * the reload value to reflect that the second tick period is already\n             * underway.  The expected idle time is always at least two ticks. */\n            ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );\n\n            if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )\n            {\n                portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;\n                ulReloadValue -= ulTimerCountsForOneTick;\n            }\n\n            if( ulReloadValue > ulStoppedTimerCompensation )\n            {\n                ulReloadValue -= ulStoppedTimerCompensation;\n            }\n\n            /* Set the new reload value. */\n            portNVIC_SYSTICK_LOAD_REG = ulReloadValue;\n\n            /* Clear the SysTick count flag and set the count value back to\n             * zero. */\n            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n            /* Restart SysTick. */\n            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\n\n            /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can\n             * set its parameter to 0 to indicate that its implementation contains\n             * its own wait for interrupt or wait for event instruction, and so wfi\n             * should not be executed again.  However, the original expected idle\n             * time variable must remain unmodified, so a copy is taken. */\n            xModifiableIdleTime = xExpectedIdleTime;\n            configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\n\n            if( xModifiableIdleTime > 0 )\n            {\n                __DSB();\n                __WFI();\n                __ISB();\n            }\n\n            configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\n\n            /* Re-enable interrupts to allow the interrupt that brought the MCU\n             * out of sleep mode to execute immediately.  See comments above\n             * the __disable_interrupt() call above. */\n            __enable_interrupt();\n            __DSB();\n            __ISB();\n\n            /* Disable interrupts again because the clock is about to be stopped\n             * and interrupts that execute while the clock is stopped will increase\n             * any slippage between the time maintained by the RTOS and calendar\n             * time. */\n            __disable_interrupt();\n            __DSB();\n            __ISB();\n\n            /* Disable the SysTick clock without reading the\n             * portNVIC_SYSTICK_CTRL_REG register to ensure the\n             * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,\n             * the time the SysTick is stopped for is accounted for as best it can\n             * be, but using the tickless mode will inevitably result in some tiny\n             * drift of the time maintained by the kernel with respect to calendar\n             * time*/\n            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );\n\n            /* Determine whether the SysTick has already counted to zero. */\n            if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n            {\n                uint32_t ulCalculatedLoadValue;\n\n                /* The tick interrupt ended the sleep (or is now pending), and\n                 * a new tick period has started.  Reset portNVIC_SYSTICK_LOAD_REG\n                 * with whatever remains of the new tick period. */\n                ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\n\n                /* Don't allow a tiny value, or values that have somehow\n                 * underflowed because the post sleep hook did something\n                 * that took too long or because the SysTick current-value register\n                 * is zero. */\n                if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )\n                {\n                    ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );\n                }\n\n                portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;\n\n                /* As the pending tick will be processed as soon as this\n                 * function exits, the tick value maintained by the tick is stepped\n                 * forward by one less than the time spent waiting. */\n                ulCompleteTickPeriods = xExpectedIdleTime - 1UL;\n            }\n            else\n            {\n                /* Something other than the tick interrupt ended the sleep. */\n\n                /* Use the SysTick current-value register to determine the\n                 * number of SysTick decrements remaining until the expected idle\n                 * time would have ended. */\n                ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n                #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )\n                {\n                    /* If the SysTick is not using the core clock, the current-\n                     * value register might still be zero here.  In that case, the\n                     * SysTick didn't load from the reload register, and there are\n                     * ulReloadValue decrements remaining in the expected idle\n                     * time, not zero. */\n                    if( ulSysTickDecrementsLeft == 0 )\n                    {\n                        ulSysTickDecrementsLeft = ulReloadValue;\n                    }\n                }\n                #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */\n\n                /* Work out how long the sleep lasted rounded to complete tick\n                 * periods (not the ulReload value which accounted for part\n                 * ticks). */\n                ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;\n\n                /* How many complete tick periods passed while the processor\n                 * was waiting? */\n                ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;\n\n                /* The reload value is set to whatever fraction of a single tick\n                 * period remains. */\n                portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;\n            }\n\n            /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,\n             * then set portNVIC_SYSTICK_LOAD_REG back to its standard value.  If\n             * the SysTick is not using the core clock, temporarily configure it to\n             * use the core clock.  This configuration forces the SysTick to load\n             * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next\n             * cycle of the other clock.  Then portNVIC_SYSTICK_LOAD_REG is ready\n             * to receive the standard value immediately. */\n            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n            portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n            #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )\n            {\n                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n            }\n            #else\n            {\n                /* The temporary usage of the core clock has served its purpose,\n                 * as described above.  Resume usage of the other clock. */\n                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\n\n                if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n                {\n                    /* The partial tick period already ended.  Be sure the SysTick\n                     * counts it only once. */\n                    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;\n                }\n\n                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n            }\n            #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */\n\n            /* Step the tick to account for any tick periods that elapsed. */\n            vTaskStepTick( ulCompleteTickPeriods );\n\n            /* Exit with interrupts enabled. */\n            __enable_interrupt();\n        }\n    }\n\n#endif /* configUSE_TICKLESS_IDLE */\n/*-----------------------------------------------------------*/\n\n/*\n * Setup the systick timer to generate the tick interrupts at the required\n * frequency.\n */\n__weak void vPortSetupTimerInterrupt( void )\n{\n    /* Calculate the constants required to configure the tick interrupt. */\n    #if ( configUSE_TICKLESS_IDLE == 1 )\n    {\n        ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );\n        xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;\n        ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\n    }\n    #endif /* configUSE_TICKLESS_IDLE */\n\n    /* Stop and clear the SysTick. */\n    portNVIC_SYSTICK_CTRL_REG = 0UL;\n    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n    /* Configure SysTick to interrupt at the requested rate. */\n    portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\n    portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );\n}\n/*-----------------------------------------------------------*/\n\n#if ( configASSERT_DEFINED == 1 )\n\n    void vPortValidateInterruptPriority( void )\n    {\n        uint32_t ulCurrentInterrupt;\n        uint8_t ucCurrentPriority;\n\n        /* Obtain the number of the currently executing interrupt. */\n        __asm volatile ( \"mrs %0, ipsr\" : \"=r\" ( ulCurrentInterrupt )::\"memory\" );\n\n        /* Is the interrupt number a user defined interrupt? */\n        if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )\n        {\n            /* Look up the interrupt's priority. */\n            ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];\n\n            /* The following assertion will fail if a service routine (ISR) for\n             * an interrupt that has been assigned a priority above\n             * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\n             * function.  ISR safe FreeRTOS API functions must *only* be called\n             * from interrupts that have been assigned a priority at or below\n             * configMAX_SYSCALL_INTERRUPT_PRIORITY.\n             *\n             * Numerically low interrupt priority numbers represent logically high\n             * interrupt priorities, therefore the priority of the interrupt must\n             * be set to a value equal to or numerically *higher* than\n             * configMAX_SYSCALL_INTERRUPT_PRIORITY.\n             *\n             * Interrupts that\tuse the FreeRTOS API must not be left at their\n             * default priority of\tzero as that is the highest possible priority,\n             * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,\n             * and\ttherefore also guaranteed to be invalid.\n             *\n             * FreeRTOS maintains separate thread and ISR API functions to ensure\n             * interrupt entry is as fast and simple as possible.\n             *\n             * The following links provide detailed information:\n             * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html\n             * https://www.FreeRTOS.org/FAQHelp.html */\n            configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );\n        }\n\n        /* Priority grouping:  The interrupt controller (NVIC) allows the bits\n         * that define each interrupt's priority to be split between bits that\n         * define the interrupt's pre-emption priority bits and bits that define\n         * the interrupt's sub-priority.  For simplicity all bits must be defined\n         * to be pre-emption priority bits.  The following assertion will fail if\n         * this is not the case (if some bits represent a sub-priority).\n         *\n         * If the application only uses CMSIS libraries for interrupt\n         * configuration then the correct setting can be achieved on all Cortex-M\n         * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the\n         * scheduler.  Note however that some vendor specific peripheral libraries\n         * assume a non-zero priority group setting, in which cases using a value\n         * of zero will result in unpredictable behaviour. */\n        configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );\n    }\n\n#endif /* configASSERT_DEFINED */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM4F/portasm.s",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#include <FreeRTOSConfig.h>\n\n\tRSEG    CODE:CODE(2)\n\tthumb\n\n\tEXTERN pxCurrentTCB\n\tEXTERN vTaskSwitchContext\n\n\tPUBLIC xPortPendSVHandler\n\tPUBLIC vPortSVCHandler\n\tPUBLIC vPortStartFirstTask\n\tPUBLIC vPortEnableVFP\n\n\n/*-----------------------------------------------------------*/\n\nxPortPendSVHandler:\n\tmrs r0, psp\n\tisb\n\t/* Get the location of the current TCB. */\n\tldr\tr3, =pxCurrentTCB\n\tldr\tr2, [r3]\n\n\t/* Is the task using the FPU context?  If so, push high vfp registers. */\n\ttst r14, #0x10\n\tit eq\n\tvstmdbeq r0!, {s16-s31}\n\n\t/* Save the core registers. */\n\tstmdb r0!, {r4-r11, r14}\n\n\t/* Save the new top of stack into the first member of the TCB. */\n\tstr r0, [r2]\n\n\tstmdb sp!, {r0, r3}\n\tmov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY\n\tmsr basepri, r0\n\tdsb\n\tisb\n\tbl vTaskSwitchContext\n\tmov r0, #0\n\tmsr basepri, r0\n\tldmia sp!, {r0, r3}\n\n\t/* The first item in pxCurrentTCB is the task top of stack. */\n\tldr r1, [r3]\n\tldr r0, [r1]\n\n\t/* Pop the core registers. */\n\tldmia r0!, {r4-r11, r14}\n\n\t/* Is the task using the FPU context?  If so, pop the high vfp registers\n\ttoo. */\n\ttst r14, #0x10\n\tit eq\n\tvldmiaeq r0!, {s16-s31}\n\n\tmsr psp, r0\n\tisb\n\t#ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata */\n\t\t#if WORKAROUND_PMU_CM001 == 1\n\t\t\tpush { r14 }\n\t\t\tpop { pc }\n\t\t#endif\n\t#endif\n\n\tbx r14\n\n\n/*-----------------------------------------------------------*/\n\nvPortSVCHandler:\n\t/* Get the location of the current TCB. */\n\tldr\tr3, =pxCurrentTCB\n\tldr r1, [r3]\n\tldr r0, [r1]\n\t/* Pop the core registers. */\n\tldmia r0!, {r4-r11, r14}\n\tmsr psp, r0\n\tisb\n\tmov r0, #0\n\tmsr\tbasepri, r0\n\tbx r14\n\n/*-----------------------------------------------------------*/\n\nvPortStartFirstTask\n\t/* Use the NVIC offset register to locate the stack. */\n\tldr r0, =0xE000ED08\n\tldr r0, [r0]\n\tldr r0, [r0]\n\t/* Set the msp back to the start of the stack. */\n\tmsr msp, r0\n\t/* Clear the bit that indicates the FPU is in use in case the FPU was used\n\tbefore the scheduler was started - which would otherwise result in the\n\tunnecessary leaving of space in the SVC stack for lazy saving of FPU\n\tregisters. */\n\tmov r0, #0\n\tmsr control, r0\n\t/* Call SVC to start the first task. */\n\tcpsie i\n\tcpsie f\n\tdsb\n\tisb\n\tsvc 0\n\n/*-----------------------------------------------------------*/\n\nvPortEnableVFP:\n\t/* The FPU enable bits are in the CPACR. */\n\tldr.w r0, =0xE000ED88\n\tldr\tr1, [r0]\n\n\t/* Enable CP10 and CP11 coprocessors, then save back. */\n\torr\tr1, r1, #( 0xf << 20 )\n\tstr r1, [r0]\n\tbx\tr14\n\n\n\n\tEND\n\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM4F/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef PORTMACRO_H\n    #define PORTMACRO_H\n\n    #ifdef __cplusplus\n        extern \"C\" {\n    #endif\n\n/*-----------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the\n * given hardware and compiler.\n *\n * These settings should not be altered.\n *-----------------------------------------------------------\n */\n\n/* IAR includes. */\n    #include <intrinsics.h>\n\n/* Type definitions. */\n    #define portCHAR          char\n    #define portFLOAT         float\n    #define portDOUBLE        double\n    #define portLONG          long\n    #define portSHORT         short\n    #define portSTACK_TYPE    uint32_t\n    #define portBASE_TYPE     long\n\n    typedef portSTACK_TYPE   StackType_t;\n    typedef long             BaseType_t;\n    typedef unsigned long    UBaseType_t;\n\n    #if ( configUSE_16_BIT_TICKS == 1 )\n        typedef uint16_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffff\n    #else\n        typedef uint32_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL\n\n/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\n * not need to be guarded with a critical section. */\n        #define portTICK_TYPE_IS_ATOMIC    1\n    #endif\n/*-----------------------------------------------------------*/\n\n/* Architecture specifics. */\n    #define portSTACK_GROWTH      ( -1 )\n    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\n    #define portBYTE_ALIGNMENT    8\n/*-----------------------------------------------------------*/\n\n/* Compiler directives. */\n    #define portWEAK_SYMBOL    __attribute__( ( weak ) )\n\n/*-----------------------------------------------------------*/\n\n\n/* Scheduler utilities. */\n    #define portYIELD()                                 \\\n    {                                                   \\\n        /* Set a PendSV to request a context switch. */ \\\n        portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \\\n        __DSB();                                        \\\n        __ISB();                                        \\\n    }\n\n    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )\n    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )\n    #define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 )\n    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )\n\n/*-----------------------------------------------------------*/\n\n/* Architecture specific optimisations. */\n    #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION\n        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1\n    #endif\n\n    #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )\n\n/* Check the configuration. */\n        #if ( configMAX_PRIORITIES > 32 )\n            #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.\n        #endif\n\n/* Store/clear the ready priorities in a bit map. */\n        #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )\n        #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )\n\n/*-----------------------------------------------------------*/\n\n        #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ( ( uint32_t ) __CLZ( ( uxReadyPriorities ) ) ) )\n\n    #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */\n/*-----------------------------------------------------------*/\n\n/* Critical section management. */\n    extern void vPortEnterCritical( void );\n    extern void vPortExitCritical( void );\n\n    #define portDISABLE_INTERRUPTS()                           \\\n    {                                                          \\\n        __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \\\n        __DSB();                                               \\\n        __ISB();                                               \\\n    }\n\n    #define portENABLE_INTERRUPTS()                   __set_BASEPRI( 0 )\n    #define portENTER_CRITICAL()                      vPortEnterCritical()\n    #define portEXIT_CRITICAL()                       vPortExitCritical()\n    #define portSET_INTERRUPT_MASK_FROM_ISR()         __get_BASEPRI(); portDISABLE_INTERRUPTS()\n    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    __set_BASEPRI( x )\n/*-----------------------------------------------------------*/\n\n/* Tickless idle/low power functionality. */\n    #ifndef portSUPPRESS_TICKS_AND_SLEEP\n        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );\n        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )\n    #endif\n\n/*-----------------------------------------------------------*/\n\n/* Task function macros as described on the FreeRTOS.org WEB site.  These are\n * not necessary for to use this port.  They are defined so the common demo files\n * (which build with all the ports) will build. */\n    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )\n    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )\n/*-----------------------------------------------------------*/\n\n    #ifdef configASSERT\n        void vPortValidateInterruptPriority( void );\n        #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()\n    #endif\n\n/* portNOP() is not required by this port. */\n    #define portNOP()\n\n    #define portINLINE              __inline\n\n    #ifndef portFORCE_INLINE\n        #define portFORCE_INLINE    inline __attribute__( ( always_inline ) )\n    #endif\n\n/*-----------------------------------------------------------*/\n\n    portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )\n    {\n        uint32_t ulCurrentInterrupt;\n        BaseType_t xReturn;\n\n        /* Obtain the number of the currently executing interrupt. */\n        __asm volatile ( \"mrs %0, ipsr\" : \"=r\" ( ulCurrentInterrupt )::\"memory\" );\n\n        if( ulCurrentInterrupt == 0 )\n        {\n            xReturn = pdFALSE;\n        }\n        else\n        {\n            xReturn = pdTRUE;\n        }\n\n        return xReturn;\n    }\n\n/*-----------------------------------------------------------*/\n\n/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in\n * the source code because to do so would cause other compilers to generate\n * warnings. */\n    #pragma diag_suppress=Pe191\n    #pragma diag_suppress=Pa082\n\n    #ifdef __cplusplus\n        }\n    #endif\n\n#endif /* PORTMACRO_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM4F_MPU/port.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/*-----------------------------------------------------------\n* Implementation of functions defined in portable.h for the ARM CM4F MPU port.\n*----------------------------------------------------------*/\n\n/* IAR includes. */\n#include <intrinsics.h>\n\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\n * all the API functions to use the MPU wrappers.  That should only be done when\n * task.h is included from an application file. */\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n#ifndef __ARMVFP__\n    #error This port can only be used when the project options are configured to enable hardware floating point support.\n#endif\n\n#if ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 )\n    #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\n#endif\n\n#ifndef configSYSTICK_CLOCK_HZ\n    #define configSYSTICK_CLOCK_HZ      configCPU_CLOCK_HZ\n    /* Ensure the SysTick is clocked at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT    ( 1UL << 2UL )\n#else\n\n/* The way the SysTick is clocked is not modified in case it is not the same\n * as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT    ( 0 )\n#endif\n\n#ifndef configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS\n    #warning \"configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS is not defined. We recommend defining it to 0 in FreeRTOSConfig.h for better security.\"\n    #define configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS    1\n#endif\n\n/* Constants required to manipulate the core.  Registers first... */\n#define portNVIC_SYSTICK_CTRL_REG                 ( *( ( volatile uint32_t * ) 0xe000e010 ) )\n#define portNVIC_SYSTICK_LOAD_REG                 ( *( ( volatile uint32_t * ) 0xe000e014 ) )\n#define portNVIC_SYSTICK_CURRENT_VALUE_REG        ( *( ( volatile uint32_t * ) 0xe000e018 ) )\n#define portNVIC_SHPR3_REG                        ( *( ( volatile uint32_t * ) 0xe000ed20 ) )\n#define portNVIC_SHPR2_REG                        ( *( ( volatile uint32_t * ) 0xe000ed1c ) )\n#define portNVIC_SYS_CTRL_STATE_REG               ( *( ( volatile uint32_t * ) 0xe000ed24 ) )\n#define portNVIC_MEM_FAULT_ENABLE                 ( 1UL << 16UL )\n\n/* Constants required to access and manipulate the MPU. */\n#define portMPU_TYPE_REG                          ( *( ( volatile uint32_t * ) 0xe000ed90 ) )\n#define portMPU_REGION_BASE_ADDRESS_REG           ( *( ( volatile uint32_t * ) 0xe000ed9C ) )\n#define portMPU_REGION_ATTRIBUTE_REG              ( *( ( volatile uint32_t * ) 0xe000edA0 ) )\n#define portMPU_CTRL_REG                          ( *( ( volatile uint32_t * ) 0xe000ed94 ) )\n#define portEXPECTED_MPU_TYPE_VALUE               ( configTOTAL_MPU_REGIONS << 8UL )\n#define portMPU_ENABLE                            ( 0x01UL )\n#define portMPU_BACKGROUND_ENABLE                 ( 1UL << 2UL )\n#define portPRIVILEGED_EXECUTION_START_ADDRESS    ( 0UL )\n#define portMPU_REGION_VALID                      ( 0x10UL )\n#define portMPU_REGION_ENABLE                     ( 0x01UL )\n#define portPERIPHERALS_START_ADDRESS             0x40000000UL\n#define portPERIPHERALS_END_ADDRESS               0x5FFFFFFFUL\n\n/* ...then bits in the registers. */\n#define portNVIC_SYSTICK_INT_BIT                  ( 1UL << 1UL )\n#define portNVIC_SYSTICK_ENABLE_BIT               ( 1UL << 0UL )\n#define portNVIC_SYSTICK_COUNT_FLAG_BIT           ( 1UL << 16UL )\n#define portNVIC_PENDSVCLEAR_BIT                  ( 1UL << 27UL )\n#define portNVIC_PEND_SYSTICK_CLEAR_BIT           ( 1UL << 25UL )\n\n/* Constants used to detect Cortex-M7 r0p0 and r0p1 cores, and ensure\n * that a work around is active for errata 837070. */\n#define portCPUID                                 ( *( ( volatile uint32_t * ) 0xE000ed00 ) )\n#define portCORTEX_M7_r0p1_ID                     ( 0x410FC271UL )\n#define portCORTEX_M7_r0p0_ID                     ( 0x410FC270UL )\n\n#define portNVIC_PENDSV_PRI                       ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\n#define portNVIC_SYSTICK_PRI                      ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\n#define portNVIC_SVC_PRI                          ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )\n\n/* Constants required to check the validity of an interrupt priority. */\n#define portFIRST_USER_INTERRUPT_NUMBER           ( 16 )\n#define portNVIC_IP_REGISTERS_OFFSET_16           ( 0xE000E3F0 )\n#define portAIRCR_REG                             ( *( ( volatile uint32_t * ) 0xE000ED0C ) )\n#define portMAX_8_BIT_VALUE                       ( ( uint8_t ) 0xff )\n#define portTOP_BIT_OF_BYTE                       ( ( uint8_t ) 0x80 )\n#define portMAX_PRIGROUP_BITS                     ( ( uint8_t ) 7 )\n#define portPRIORITY_GROUP_MASK                   ( 0x07UL << 8UL )\n#define portPRIGROUP_SHIFT                        ( 8UL )\n\n/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */\n#define portVECTACTIVE_MASK                       ( 0xFFUL )\n\n/* Constants required to manipulate the VFP. */\n#define portFPCCR                                 ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */\n#define portASPEN_AND_LSPEN_BITS                  ( 0x3UL << 30UL )\n\n/* Constants required to set up the initial stack. */\n#define portINITIAL_XPSR                          ( 0x01000000 )\n#define portINITIAL_EXC_RETURN                    ( 0xfffffffd )\n#define portINITIAL_CONTROL_IF_UNPRIVILEGED       ( 0x03 )\n#define portINITIAL_CONTROL_IF_PRIVILEGED         ( 0x02 )\n\n/* Offsets in the stack to the parameters when inside the SVC handler. */\n#define portOFFSET_TO_PC                          ( 6 )\n\n/* The systick is a 24-bit counter. */\n#define portMAX_24_BIT_NUMBER                     ( 0xffffffUL )\n\n/* A fiddle factor to estimate the number of SysTick counts that would have\n * occurred while the SysTick counter is stopped during tickless idle\n * calculations. */\n#define portMISSED_COUNTS_FACTOR                  ( 45UL )\n\n/* For strict compliance with the Cortex-M spec the task start address should\n * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */\n#define portSTART_ADDRESS_MASK                    ( ( StackType_t ) 0xfffffffeUL )\n\n/*\n * Configure a number of standard MPU regions that are used by all tasks.\n */\nstatic void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\n\n/*\n * Return the smallest MPU region size that a given number of bytes will fit\n * into.  The region size is returned as the value that should be programmed\n * into the region attribute register for that region.\n */\nstatic uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;\n\n/*\n * Setup the timer to generate the tick interrupts.  The implementation in this\n * file is weak to allow application writers to change the timer used to\n * generate the tick interrupt.\n */\nvoid vPortSetupTimerInterrupt( void );\n\n/*\n * Exception handlers.\n */\nvoid xPortSysTickHandler( void ) PRIVILEGED_FUNCTION;\n\n/*\n * Start first task is a separate function so it can be tested in isolation.\n */\nextern void vPortStartFirstTask( void ) PRIVILEGED_FUNCTION;\n\n/*\n * Turn the VFP on.\n */\nextern void vPortEnableVFP( void );\n\n/*\n * The C portion of the SVC handler.\n */\nvoid vPortSVCHandler_C( uint32_t * pulParam );\n\n/*\n * Called from the SVC handler used to start the scheduler.\n */\nextern void vPortRestoreContextOfFirstTask( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Enter critical section.\n */\n#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )\n    void vPortEnterCritical( void ) FREERTOS_SYSTEM_CALL;\n#else\n    void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;\n#endif\n\n/**\n * @brief Exit from critical section.\n */\n#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )\n    void vPortExitCritical( void ) FREERTOS_SYSTEM_CALL;\n#else\n    void vPortExitCritical( void ) PRIVILEGED_FUNCTION;\n#endif\n/*-----------------------------------------------------------*/\n\n/* Each task maintains its own interrupt status in the critical nesting\n * variable. */\nstatic UBaseType_t uxCriticalNesting = 0xaaaaaaaa;\n\n/*\n * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure\n * FreeRTOS API functions are not called from interrupts that have been assigned\n * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.\n */\n#if ( configASSERT_DEFINED == 1 )\n    static uint8_t ucMaxSysCallPriority = 0;\n    static uint32_t ulMaxPRIGROUPValue = 0;\n    static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;\n#endif /* configASSERT_DEFINED */\n\n/*-----------------------------------------------------------*/\n\n/*\n * See header file for description.\n */\nStackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,\n                                     TaskFunction_t pxCode,\n                                     void * pvParameters,\n                                     BaseType_t xRunPrivileged )\n{\n    /* Simulate the stack frame as it would be created by a context switch\n     * interrupt. */\n\n    /* Offset added to account for the way the MCU uses the stack on entry/exit\n     * of interrupts, and to ensure alignment. */\n    pxTopOfStack--;\n\n    *pxTopOfStack = portINITIAL_XPSR;                                    /* xPSR */\n    pxTopOfStack--;\n    *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */\n    pxTopOfStack--;\n    *pxTopOfStack = ( StackType_t ) 0;                                   /* LR */\n\n    /* Save code space by skipping register initialisation. */\n    pxTopOfStack -= 5;                            /* R12, R3, R2 and R1. */\n    *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\n\n    /* A save method is being used that requires each task to maintain its\n     * own exec return value. */\n    pxTopOfStack--;\n    *pxTopOfStack = portINITIAL_EXC_RETURN;\n\n    pxTopOfStack -= 9; /* R11, R10, R9, R8, R7, R6, R5 and R4. */\n\n    if( xRunPrivileged == pdTRUE )\n    {\n        *pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED;\n    }\n    else\n    {\n        *pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED;\n    }\n\n    return pxTopOfStack;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortSVCHandler_C( uint32_t * pulParam )\n{\n    uint8_t ucSVCNumber;\n    uint32_t ulPC;\n\n    #if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )\n        extern uint32_t __syscalls_flash_start__[];\n        extern uint32_t __syscalls_flash_end__[];\n    #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */\n\n    /* The stack contains: r0, r1, r2, r3, r12, LR, PC and xPSR. The first\n     * argument (r0) is pulParam[ 0 ]. */\n    ulPC = pulParam[ portOFFSET_TO_PC ];\n    ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];\n\n    switch( ucSVCNumber )\n    {\n        case portSVC_START_SCHEDULER:\n            portNVIC_SHPR2_REG |= portNVIC_SVC_PRI;\n            vPortRestoreContextOfFirstTask();\n            break;\n\n        case portSVC_YIELD:\n            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\n\n            /* Barriers are normally not required\n             * but do ensure the code is completely\n             * within the specified behaviour for the\n             * architecture. */\n            __asm volatile ( \"dsb\" ::: \"memory\" );\n            __asm volatile ( \"isb\" );\n\n            break;\n\n            #if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )\n                case portSVC_RAISE_PRIVILEGE: /* Only raise the privilege, if the\n                                               * svc was raised from any of the\n                                               * system calls. */\n\n                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&\n                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )\n                    {\n                        __asm volatile\n                        (\n                            \"\tmrs r1, control\t\t\\n\"/* Obtain current control value. */\n                            \"\tbic r1, r1, #1\t\t\\n\"/* Set privilege bit. */\n                            \"\tmsr control, r1\t\t\\n\"/* Write back new control value. */\n                            ::: \"r1\", \"memory\"\n                        );\n                    }\n\n                    break;\n            #else /* if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */\n                case portSVC_RAISE_PRIVILEGE:\n                    __asm volatile\n                    (\n                        \"\tmrs r1, control\t\t\\n\"/* Obtain current control value. */\n                        \"\tbic r1, r1, #1\t\t\\n\"/* Set privilege bit. */\n                        \"\tmsr control, r1\t\t\\n\"/* Write back new control value. */\n                        ::: \"r1\", \"memory\"\n                    );\n                    break;\n                    #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */\n\n                default: /* Unknown SVC call. */\n                    break;\n    }\n}\n/*-----------------------------------------------------------*/\n\n/*\n * See header file for description.\n */\nBaseType_t xPortStartScheduler( void )\n{\n    /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.\n     * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\n    configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );\n\n    /* Errata 837070 workaround must only be enabled on Cortex-M7 r0p0\n     * and r0p1 cores. */\n    #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )\n        configASSERT( ( portCPUID == portCORTEX_M7_r0p1_ID ) || ( portCPUID == portCORTEX_M7_r0p0_ID ) );\n    #else\n        /* When using this port on a Cortex-M7 r0p0 or r0p1 core, define\n         * configENABLE_ERRATA_837070_WORKAROUND to 1 in your\n         * FreeRTOSConfig.h. */\n        configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );\n        configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );\n    #endif\n\n    #if ( configASSERT_DEFINED == 1 )\n        {\n            volatile uint32_t ulOriginalPriority;\n            volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\n            volatile uint8_t ucMaxPriorityValue;\n\n            /* Determine the maximum priority from which ISR safe FreeRTOS API\n             * functions can be called.  ISR safe functions are those that end in\n             * \"FromISR\".  FreeRTOS maintains separate thread and ISR API functions to\n             * ensure interrupt entry is as fast and simple as possible.\n             *\n             * Save the interrupt priority value that is about to be clobbered. */\n            ulOriginalPriority = *pucFirstUserPriorityRegister;\n\n            /* Determine the number of priority bits available.  First write to all\n             * possible bits. */\n            *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\n\n            /* Read the value back to see how many bits stuck. */\n            ucMaxPriorityValue = *pucFirstUserPriorityRegister;\n\n            /* Use the same mask on the maximum system call priority. */\n            ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;\n\n            /* Calculate the maximum acceptable priority group value for the number\n             * of bits read back. */\n            ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;\n\n            while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )\n            {\n                ulMaxPRIGROUPValue--;\n                ucMaxPriorityValue <<= ( uint8_t ) 0x01;\n            }\n\n            #ifdef __NVIC_PRIO_BITS\n                {\n                    /* Check the CMSIS configuration that defines the number of\n                     * priority bits matches the number of priority bits actually queried\n                     * from the hardware. */\n                    configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );\n                }\n            #endif\n\n            #ifdef configPRIO_BITS\n                {\n                    /* Check the FreeRTOS configuration that defines the number of\n                     * priority bits matches the number of priority bits actually queried\n                     * from the hardware. */\n                    configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );\n                }\n            #endif\n\n            /* Shift the priority group value back to its position within the AIRCR\n             * register. */\n            ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;\n            ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;\n\n            /* Restore the clobbered interrupt priority register to its original\n             * value. */\n            *pucFirstUserPriorityRegister = ulOriginalPriority;\n        }\n    #endif /* configASSERT_DEFINED */\n\n    /* Make PendSV and SysTick the lowest priority interrupts. */\n    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;\n    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;\n\n    /* Configure the regions in the MPU that are common to all tasks. */\n    prvSetupMPU();\n\n    /* Start the timer that generates the tick ISR.  Interrupts are disabled\n     * here already. */\n    vPortSetupTimerInterrupt();\n\n    /* Initialise the critical nesting count ready for the first task. */\n    uxCriticalNesting = 0;\n\n    /* Ensure the VFP is enabled - it should be anyway. */\n    vPortEnableVFP();\n\n    /* Lazy save always. */\n    *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;\n\n    /* Start the first task. */\n    vPortStartFirstTask();\n\n    /* Should not get here! */\n    return 0;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEndScheduler( void )\n{\n    /* Not implemented in ports where there is nothing to return to.\n     * Artificially force an assert. */\n    configASSERT( uxCriticalNesting == 1000UL );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEnterCritical( void )\n{\n#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )\n    if( portIS_PRIVILEGED() == pdFALSE )\n    {\n        portRAISE_PRIVILEGE();\n        portMEMORY_BARRIER();\n\n        portDISABLE_INTERRUPTS();\n        uxCriticalNesting++;\n        /* This is not the interrupt safe version of the enter critical function so\n         * assert() if it is being called from an interrupt context.  Only API\n         * functions that end in \"FromISR\" can be used in an interrupt.  Only assert if\n         * the critical nesting count is 1 to protect against recursive calls if the\n         * assert function also uses a critical section. */\n        if( uxCriticalNesting == 1 )\n        {\n            configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );\n        }\n        portMEMORY_BARRIER();\n\n        portRESET_PRIVILEGE();\n        portMEMORY_BARRIER();\n    }\n    else\n    {\n        portDISABLE_INTERRUPTS();\n        uxCriticalNesting++;\n        /* This is not the interrupt safe version of the enter critical function so\n         * assert() if it is being called from an interrupt context.  Only API\n         * functions that end in \"FromISR\" can be used in an interrupt.  Only assert if\n         * the critical nesting count is 1 to protect against recursive calls if the\n         * assert function also uses a critical section. */\n        if( uxCriticalNesting == 1 )\n        {\n            configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );\n        }\n    }\n#else\n    portDISABLE_INTERRUPTS();\n    uxCriticalNesting++;\n    /* This is not the interrupt safe version of the enter critical function so\n     * assert() if it is being called from an interrupt context.  Only API\n     * functions that end in \"FromISR\" can be used in an interrupt.  Only assert if\n     * the critical nesting count is 1 to protect against recursive calls if the\n     * assert function also uses a critical section. */\n    if( uxCriticalNesting == 1 )\n    {\n        configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );\n    }\n#endif\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortExitCritical( void )\n{\n#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )\n    if( portIS_PRIVILEGED() == pdFALSE )\n    {\n        portRAISE_PRIVILEGE();\n        portMEMORY_BARRIER();\n\n        configASSERT( uxCriticalNesting );\n        uxCriticalNesting--;\n\n        if( uxCriticalNesting == 0 )\n        {\n            portENABLE_INTERRUPTS();\n        }\n        portMEMORY_BARRIER();\n\n        portRESET_PRIVILEGE();\n        portMEMORY_BARRIER();\n    }\n    else\n    {\n        configASSERT( uxCriticalNesting );\n        uxCriticalNesting--;\n\n        if( uxCriticalNesting == 0 )\n        {\n            portENABLE_INTERRUPTS();\n        }\n    }\n#else\n    configASSERT( uxCriticalNesting );\n    uxCriticalNesting--;\n\n    if( uxCriticalNesting == 0 )\n    {\n        portENABLE_INTERRUPTS();\n    }\n#endif\n}\n/*-----------------------------------------------------------*/\n\nvoid xPortSysTickHandler( void )\n{\n    /* The SysTick runs at the lowest interrupt priority, so when this interrupt\n     * executes all interrupts must be unmasked.  There is therefore no need to\n     * save and then restore the interrupt mask value as its value is already\n     * known. */\n    portDISABLE_INTERRUPTS();\n    {\n        /* Increment the RTOS tick. */\n        if( xTaskIncrementTick() != pdFALSE )\n        {\n            /* A context switch is required.  Context switching is performed in\n             * the PendSV interrupt.  Pend the PendSV interrupt. */\n            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\n        }\n    }\n    portENABLE_INTERRUPTS();\n}\n/*-----------------------------------------------------------*/\n\n/*\n * Setup the systick timer to generate the tick interrupts at the required\n * frequency.\n */\n__weak void vPortSetupTimerInterrupt( void )\n{\n    /* Stop and clear the SysTick. */\n    portNVIC_SYSTICK_CTRL_REG = 0UL;\n    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n    /* Configure SysTick to interrupt at the requested rate. */\n    portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\n    portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvSetupMPU( void )\n{\n    extern uint32_t __privileged_functions_start__[];\n    extern uint32_t __privileged_functions_end__[];\n    extern uint32_t __FLASH_segment_start__[];\n    extern uint32_t __FLASH_segment_end__[];\n    extern uint32_t __privileged_data_start__[];\n    extern uint32_t __privileged_data_end__[];\n\n    /* The only permitted number of regions are 8 or 16. */\n    configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );\n\n    /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */\n    configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );\n\n    /* Check the expected MPU is present. */\n    if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )\n    {\n        /* First setup the unprivileged flash for unprivileged read only access. */\n        portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */\n                                          ( portMPU_REGION_VALID ) |\n                                          ( portUNPRIVILEGED_FLASH_REGION );\n\n        portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_ONLY ) |\n                                       ( ( configTEX_S_C_B_FLASH & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |\n                                       ( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |\n                                       ( portMPU_REGION_ENABLE );\n\n        /* Setup the privileged flash for privileged only access.  This is where\n         * the kernel code is placed. */\n        portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_functions_start__ ) | /* Base address. */\n                                          ( portMPU_REGION_VALID ) |\n                                          ( portPRIVILEGED_FLASH_REGION );\n\n        portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_ONLY ) |\n                                       ( ( configTEX_S_C_B_FLASH & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |\n                                       ( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __privileged_functions_start__ ) ) |\n                                       ( portMPU_REGION_ENABLE );\n\n        /* Setup the privileged data RAM region.  This is where the kernel data\n         * is placed. */\n        portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */\n                                          ( portMPU_REGION_VALID ) |\n                                          ( portPRIVILEGED_RAM_REGION );\n\n        portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\n                                       ( portMPU_REGION_EXECUTE_NEVER ) |\n                                       ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |\n                                       prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |\n                                       ( portMPU_REGION_ENABLE );\n\n        /* By default allow everything to access the general peripherals.  The\n         * system peripherals and registers are protected. */\n        portMPU_REGION_BASE_ADDRESS_REG = ( portPERIPHERALS_START_ADDRESS ) |\n                                          ( portMPU_REGION_VALID ) |\n                                          ( portGENERAL_PERIPHERALS_REGION );\n\n        portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |\n                                       ( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |\n                                       ( portMPU_REGION_ENABLE );\n\n        /* Enable the memory fault exception. */\n        portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE;\n\n        /* Enable the MPU with the background region configured. */\n        portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );\n    }\n}\n/*-----------------------------------------------------------*/\n\nstatic uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )\n{\n    uint32_t ulRegionSize, ulReturnValue = 4;\n\n    /* 32 is the smallest region size, 31 is the largest valid value for\n     * ulReturnValue. */\n    for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )\n    {\n        if( ulActualSizeInBytes <= ulRegionSize )\n        {\n            break;\n        }\n        else\n        {\n            ulReturnValue++;\n        }\n    }\n\n    /* Shift the code by one before returning so it can be written directly\n     * into the the correct bit position of the attribute register. */\n    return( ulReturnValue << 1UL );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,\n                                const struct xMEMORY_REGION * const xRegions,\n                                StackType_t * pxBottomOfStack,\n                                uint32_t ulStackDepth )\n{\n    extern uint32_t __SRAM_segment_start__[];\n    extern uint32_t __SRAM_segment_end__[];\n    extern uint32_t __privileged_data_start__[];\n    extern uint32_t __privileged_data_end__[];\n    int32_t lIndex;\n    uint32_t ul;\n\n    if( xRegions == NULL )\n    {\n        /* No MPU regions are specified so allow access to all RAM. */\n        xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =\n            ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */\n            ( portMPU_REGION_VALID ) |\n            ( portSTACK_REGION ); /* Region number. */\n\n        xMPUSettings->xRegion[ 0 ].ulRegionAttribute =\n            ( portMPU_REGION_READ_WRITE ) |\n            ( portMPU_REGION_EXECUTE_NEVER ) |\n            ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |\n            ( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |\n            ( portMPU_REGION_ENABLE );\n\n        /* Invalidate user configurable regions. */\n        for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )\n        {\n            xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( ul - 1UL ) | portMPU_REGION_VALID );\n            xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;\n        }\n    }\n    else\n    {\n        /* This function is called automatically when the task is created - in\n         * which case the stack region parameters will be valid.  At all other\n         * times the stack parameters will not be valid and it is assumed that the\n         * stack region has already been configured. */\n        if( ulStackDepth > 0 )\n        {\n            /* Define the region that allows access to the stack. */\n            xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =\n                ( ( uint32_t ) pxBottomOfStack ) |\n                ( portMPU_REGION_VALID ) |\n                ( portSTACK_REGION ); /* Region number. */\n\n            xMPUSettings->xRegion[ 0 ].ulRegionAttribute =\n                ( portMPU_REGION_READ_WRITE ) |\n                ( portMPU_REGION_EXECUTE_NEVER ) |\n                ( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |\n                ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |\n                ( portMPU_REGION_ENABLE );\n        }\n\n        lIndex = 0;\n\n        for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )\n        {\n            if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )\n            {\n                /* Translate the generic region definition contained in\n                 * xRegions into the CM4 specific MPU settings that are then\n                 * stored in xMPUSettings. */\n                xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =\n                    ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |\n                    ( portMPU_REGION_VALID ) |\n                    ( ul - 1UL ); /* Region number. */\n\n                xMPUSettings->xRegion[ ul ].ulRegionAttribute =\n                    ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |\n                    ( xRegions[ lIndex ].ulParameters ) |\n                    ( portMPU_REGION_ENABLE );\n            }\n            else\n            {\n                /* Invalidate the region. */\n                xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( ul - 1UL ) | portMPU_REGION_VALID );\n                xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;\n            }\n\n            lIndex++;\n        }\n    }\n}\n/*-----------------------------------------------------------*/\n\n#if ( configASSERT_DEFINED == 1 )\n\n    void vPortValidateInterruptPriority( void )\n    {\n        uint32_t ulCurrentInterrupt;\n        uint8_t ucCurrentPriority;\n\n        /* Obtain the number of the currently executing interrupt. */\n        __asm volatile ( \"mrs %0, ipsr\" : \"=r\" ( ulCurrentInterrupt )::\"memory\" );\n\n        /* Is the interrupt number a user defined interrupt? */\n        if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )\n        {\n            /* Look up the interrupt's priority. */\n            ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];\n\n            /* The following assertion will fail if a service routine (ISR) for\n             * an interrupt that has been assigned a priority above\n             * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\n             * function.  ISR safe FreeRTOS API functions must *only* be called\n             * from interrupts that have been assigned a priority at or below\n             * configMAX_SYSCALL_INTERRUPT_PRIORITY.\n             *\n             * Numerically low interrupt priority numbers represent logically high\n             * interrupt priorities, therefore the priority of the interrupt must\n             * be set to a value equal to or numerically *higher* than\n             * configMAX_SYSCALL_INTERRUPT_PRIORITY.\n             *\n             * Interrupts that\tuse the FreeRTOS API must not be left at their\n             * default priority of\tzero as that is the highest possible priority,\n             * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,\n             * and\ttherefore also guaranteed to be invalid.\n             *\n             * FreeRTOS maintains separate thread and ISR API functions to ensure\n             * interrupt entry is as fast and simple as possible.\n             *\n             * The following links provide detailed information:\n             * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html\n             * https://www.FreeRTOS.org/FAQHelp.html */\n            configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );\n        }\n\n        /* Priority grouping:  The interrupt controller (NVIC) allows the bits\n         * that define each interrupt's priority to be split between bits that\n         * define the interrupt's pre-emption priority bits and bits that define\n         * the interrupt's sub-priority.  For simplicity all bits must be defined\n         * to be pre-emption priority bits.  The following assertion will fail if\n         * this is not the case (if some bits represent a sub-priority).\n         *\n         * If the application only uses CMSIS libraries for interrupt\n         * configuration then the correct setting can be achieved on all Cortex-M\n         * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the\n         * scheduler.  Note however that some vendor specific peripheral libraries\n         * assume a non-zero priority group setting, in which cases using a value\n         * of zero will result in unpredictable behaviour. */\n        configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );\n    }\n\n#endif /* configASSERT_DEFINED */\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM4F_MPU/portasm.s",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n/* Including FreeRTOSConfig.h here will cause build errors if the header file\ncontains code not understood by the assembler - for example the 'extern' keyword.\nTo avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so\nthe code is included in C files but excluded by the preprocessor in assembly\nfiles (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */\n#include <FreeRTOSConfig.h>\n\n\tRSEG    CODE:CODE(2)\n\tthumb\n\n\tEXTERN pxCurrentTCB\n\tEXTERN vTaskSwitchContext\n\tEXTERN vPortSVCHandler_C\n\n\tPUBLIC xPortPendSVHandler\n\tPUBLIC vPortSVCHandler\n\tPUBLIC vPortStartFirstTask\n\tPUBLIC vPortEnableVFP\n\tPUBLIC vPortRestoreContextOfFirstTask\n\tPUBLIC xIsPrivileged\n\tPUBLIC vResetPrivilege\n\n/*-----------------------------------------------------------*/\n\nxPortPendSVHandler:\n\tmrs r0, psp\n\tisb\n\t/* Get the location of the current TCB. */\n\tldr\tr3, =pxCurrentTCB\n\tldr\tr2, [r3]\n\n\t/* Is the task using the FPU context?  If so, push high vfp registers. */\n\ttst r14, #0x10\n\tit eq\n\tvstmdbeq r0!, {s16-s31}\n\n\t/* Save the core registers. */\n\tmrs r1, control\n\tstmdb r0!, {r1, r4-r11, r14}\n\n\t/* Save the new top of stack into the first member of the TCB. */\n\tstr r0, [r2]\n\n\tstmdb sp!, {r0, r3}\n\tmov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY\n\t#if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )\n\t\tcpsid i /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */\n\t#endif\n\tmsr basepri, r0\n\tdsb\n\tisb\n\t#if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )\n\t\tcpsie i /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */\n\t#endif\n\tbl vTaskSwitchContext\n\tmov r0, #0\n\tmsr basepri, r0\n\tldmia sp!, {r0, r3}\n\n\t/* The first item in pxCurrentTCB is the task top of stack. */\n\tldr r1, [r3]\n\tldr r0, [r1]\n\t/* Move onto the second item in the TCB... */\n\tadd r1, r1, #4\n\n\tdmb\t\t\t\t\t/* Complete outstanding transfers before disabling MPU. */\n\tldr r2, =0xe000ed94\t/* MPU_CTRL register. */\n\tldr r3, [r2]\t\t/* Read the value of MPU_CTRL. */\n\tbic r3, r3, #1\t\t/* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */\n\tstr r3, [r2]\t\t/* Disable MPU. */\n\n\t/* Region Base Address register. */\n\tldr r2, =0xe000ed9c\n\t/* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */\n\tldmia r1!, {r4-r11}\n\t/* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */\n\tstmia r2, {r4-r11}\n\n\t#ifdef configTOTAL_MPU_REGIONS\n\t\t#if ( configTOTAL_MPU_REGIONS == 16 )\n\t\t\t/* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */\n\t\t\tldmia r1!, {r4-r11}\n\t\t\t/* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */\n\t\t\tstmia r2, {r4-r11}\n\t\t\t/* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */\n\t\t\tldmia r1!, {r4-r11}\n\t\t\t/* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */\n\t\t\tstmia r2, {r4-r11}\n\t\t#endif /* configTOTAL_MPU_REGIONS == 16. */\n\t#endif /* configTOTAL_MPU_REGIONS */\n\n\tldr r2, =0xe000ed94\t/* MPU_CTRL register. */\n\tldr r3, [r2]\t\t/* Read the value of MPU_CTRL. */\n\torr r3, r3, #1\t\t/* r3 = r3 | 1 i.e. Set the bit 0 in r3. */\n\tstr r3, [r2]\t\t/* Enable MPU. */\n\tdsb\t\t\t\t\t/* Force memory writes before continuing. */\n\n\t/* Pop the registers that are not automatically saved on exception entry. */\n\tldmia r0!, {r3-r11, r14}\n\tmsr control, r3\n\n\t/* Is the task using the FPU context?  If so, pop the high vfp registers\n\ttoo. */\n\ttst r14, #0x10\n\tit eq\n\tvldmiaeq r0!, {s16-s31}\n\n\tmsr psp, r0\n\tisb\n\n\tbx r14\n\n\n/*-----------------------------------------------------------*/\n\nvPortSVCHandler:\n\t#ifndef USE_PROCESS_STACK\t/* Code should not be required if a main() is using the process stack. */\n\t\ttst lr, #4\n\t\tite eq\n\t\tmrseq r0, msp\n\t\tmrsne r0, psp\n\t#else\n\t\tmrs r0, psp\n\t#endif\n\t\tb vPortSVCHandler_C\n\n/*-----------------------------------------------------------*/\n\nvPortStartFirstTask:\n\t/* Use the NVIC offset register to locate the stack. */\n\tldr r0, =0xE000ED08\n\tldr r0, [r0]\n\tldr r0, [r0]\n\t/* Set the msp back to the start of the stack. */\n\tmsr msp, r0\n\t/* Clear the bit that indicates the FPU is in use in case the FPU was used\n\tbefore the scheduler was started - which would otherwise result in the\n\tunnecessary leaving of space in the SVC stack for lazy saving of FPU\n\tregisters. */\n\tmov r0, #0\n\tmsr control, r0\n\t/* Call SVC to start the first task. */\n\tcpsie i\n\tcpsie f\n\tdsb\n\tisb\n\tsvc 0\n\n/*-----------------------------------------------------------*/\n\nvPortRestoreContextOfFirstTask:\n\t/* Use the NVIC offset register to locate the stack. */\n\tldr r0, =0xE000ED08\n\tldr r0, [r0]\n\tldr r0, [r0]\n\t/* Set the msp back to the start of the stack. */\n\tmsr msp, r0\n\t/* Restore the context. */\n\tldr\tr3, =pxCurrentTCB\n\tldr r1, [r3]\n\t/* The first item in the TCB is the task top of stack. */\n\tldr r0, [r1]\n\t/* Move onto the second item in the TCB... */\n\tadd r1, r1, #4\n\n\tdmb\t\t\t\t\t/* Complete outstanding transfers before disabling MPU. */\n\tldr r2, =0xe000ed94\t/* MPU_CTRL register. */\n\tldr r3, [r2]\t\t/* Read the value of MPU_CTRL. */\n\tbic r3, r3, #1\t\t/* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */\n\tstr r3, [r2]\t\t/* Disable MPU. */\n\n\t/* Region Base Address register. */\n\tldr r2, =0xe000ed9c\n\t/* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */\n\tldmia r1!, {r4-r11}\n\t/* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */\n\tstmia r2, {r4-r11}\n\n\t#ifdef configTOTAL_MPU_REGIONS\n\t\t#if ( configTOTAL_MPU_REGIONS == 16 )\n\t\t\t/* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */\n\t\t\tldmia r1!, {r4-r11}\n\t\t\t/* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */\n\t\t\tstmia r2, {r4-r11}\n\t\t\t/* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */\n\t\t\tldmia r1!, {r4-r11}\n\t\t\t/* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */\n\t\t\tstmia r2, {r4-r11}\n\t\t#endif /* configTOTAL_MPU_REGIONS == 16. */\n\t#endif /* configTOTAL_MPU_REGIONS */\n\n\tldr r2, =0xe000ed94\t/* MPU_CTRL register. */\n\tldr r3, [r2]\t\t/* Read the value of MPU_CTRL. */\n\torr r3, r3, #1\t\t/* r3 = r3 | 1 i.e. Set the bit 0 in r3. */\n\tstr r3, [r2]\t\t/* Enable MPU. */\n\tdsb\t\t\t\t\t/* Force memory writes before continuing. */\n\n\t/* Pop the registers that are not automatically saved on exception entry. */\n\tldmia r0!, {r3-r11, r14}\n\tmsr control, r3\n\t/* Restore the task stack pointer. */\n\tmsr psp, r0\n\tmov r0, #0\n\tmsr\tbasepri, r0\n\tbx r14\n\n/*-----------------------------------------------------------*/\n\nvPortEnableVFP:\n\t/* The FPU enable bits are in the CPACR. */\n\tldr.w r0, =0xE000ED88\n\tldr\tr1, [r0]\n\n\t/* Enable CP10 and CP11 coprocessors, then save back. */\n\torr\tr1, r1, #( 0xf << 20 )\n\tstr r1, [r0]\n\tbx\tr14\n\n/*-----------------------------------------------------------*/\n\nxIsPrivileged:\n\tmrs r0, control\t\t/* r0 = CONTROL. */\n\ttst r0, #1\t\t\t/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\n\tite ne\n\tmovne r0, #0\t\t/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\n\tmoveq r0, #1\t\t/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */\n\tbx lr\t\t\t\t/* Return. */\n/*-----------------------------------------------------------*/\n\nvResetPrivilege:\n\tmrs r0, control\t\t/* r0 = CONTROL. */\n\torr r0, r0, #1\t\t/* r0 = r0 | 1. */\n\tmsr control, r0\t\t/* CONTROL = r0. */\n\tbx lr\t\t\t\t/* Return to the caller. */\n/*-----------------------------------------------------------*/\n\n\tEND\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM4F_MPU/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n\n#ifndef PORTMACRO_H\n#define PORTMACRO_H\n\n/* *INDENT-OFF* */\n#ifdef __cplusplus\n    extern \"C\" {\n#endif\n/* *INDENT-ON* */\n\n/*-----------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the\n * given hardware and compiler.\n *\n * These settings should not be altered.\n *-----------------------------------------------------------\n */\n\n/* IAR includes. */\n#include <intrinsics.h>\n\n/* Type definitions. */\n#define portCHAR          char\n#define portFLOAT         float\n#define portDOUBLE        double\n#define portLONG          long\n#define portSHORT         short\n#define portSTACK_TYPE    uint32_t\n#define portBASE_TYPE     long\n\ntypedef portSTACK_TYPE   StackType_t;\ntypedef long             BaseType_t;\ntypedef unsigned long    UBaseType_t;\n\n#if ( configUSE_16_BIT_TICKS == 1 )\n    typedef uint16_t     TickType_t;\n    #define portMAX_DELAY              ( TickType_t ) 0xffff\n#else\n    typedef uint32_t     TickType_t;\n    #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL\n\n/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\n * not need to be guarded with a critical section. */\n    #define portTICK_TYPE_IS_ATOMIC    1\n#endif\n\n/*-----------------------------------------------------------*/\n\n/* MPU specific constants. */\n#define portUSING_MPU_WRAPPERS                                   1\n#define portPRIVILEGE_BIT                                        ( 0x80000000UL )\n\n#define portMPU_REGION_READ_WRITE                                ( 0x03UL << 24UL )\n#define portMPU_REGION_PRIVILEGED_READ_ONLY                      ( 0x05UL << 24UL )\n#define portMPU_REGION_READ_ONLY                                 ( 0x06UL << 24UL )\n#define portMPU_REGION_PRIVILEGED_READ_WRITE                     ( 0x01UL << 24UL )\n#define portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY    ( 0x02UL << 24UL )\n#define portMPU_REGION_CACHEABLE_BUFFERABLE                      ( 0x07UL << 16UL )\n#define portMPU_REGION_EXECUTE_NEVER                             ( 0x01UL << 28UL )\n\n/* Location of the TEX,S,C,B bits in the MPU Region Attribute and Size\n * Register (RASR). */\n#define portMPU_RASR_TEX_S_C_B_LOCATION                          ( 16UL )\n#define portMPU_RASR_TEX_S_C_B_MASK                              ( 0x3FUL )\n\n/* MPU settings that can be overriden in FreeRTOSConfig.h. */\n#ifndef configTOTAL_MPU_REGIONS\n    /* Define to 8 for backward compatibility. */\n    #define configTOTAL_MPU_REGIONS    ( 8UL )\n#endif\n\n/*\n * The TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits define the\n * memory type, and where necessary the cacheable and shareable properties\n * of the memory region.\n *\n * The TEX, C, and B bits together indicate the memory type of the region,\n * and:\n * - For Normal memory, the cacheable properties of the region.\n * - For Device memory, whether the region is shareable.\n *\n * For Normal memory regions, the S bit indicates whether the region is\n * shareable. For Strongly-ordered and Device memory, the S bit is ignored.\n *\n * See the following two tables for setting TEX, S, C and B bits for\n * unprivileged flash, privileged flash and privileged RAM regions.\n *\n +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+\n | TEX | C | B | Memory type            |  Description or Normal region cacheability             |  Shareable?             |\n +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+\n | 000 | 0 | 0 | Strongly-ordered       |  Strongly ordered                                      |  Shareable              |\n +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+\n | 000 | 0 | 1 | Device                 |  Shared device                                         |  Shareable              |\n +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+\n | 000 | 1 | 0 | Normal                 |  Outer and inner   write-through; no write allocate    |  S bit                  |\n +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+\n | 000 | 1 | 1 | Normal                 |  Outer and inner   write-back; no write allocate       |  S bit                  |\n +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+\n | 001 | 0 | 0 | Normal                 |  Outer and inner   Non-cacheable                       |  S bit                  |\n +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+\n | 001 | 0 | 1 | Reserved               |  Reserved                                              |  Reserved               |\n +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+\n | 001 | 1 | 0 | IMPLEMENTATION DEFINED |  IMPLEMENTATION DEFINED                                |  IMPLEMENTATION DEFINED |\n +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+\n | 001 | 1 | 1 | Normal                 |  Outer and inner   write-back; write and read allocate |  S bit                  |\n +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+\n | 010 | 0 | 0 | Device                 |  Non-shared device                                     |  Not shareable          |\n +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+\n | 010 | 0 | 1 | Reserved               |  Reserved                                              |  Reserved               |\n +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+\n | 010 | 1 | X | Reserved               |  Reserved                                              |  Reserved               |\n +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+\n | 011 | X | X | Reserved               |  Reserved                                              |  Reserved               |\n +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+\n | 1BB | A | A | Normal                 | Cached memory, with AA and BB indicating the inner and |  Reserved               |\n |     |   |   |                        | outer cacheability rules that must be exported on the  |                         |\n |     |   |   |                        | bus. See the table below for the cacheability policy   |                         |\n |     |   |   |                        | encoding. memory, BB=Outer policy, AA=Inner policy.    |                         |\n +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+\n |\n +-----------------------------------------+----------------------------------------+\n | AA or BB subfield of {TEX,C,B} encoding |  Cacheability policy                   |\n +-----------------------------------------+----------------------------------------+\n | 00                                      |  Non-cacheable                         |\n +-----------------------------------------+----------------------------------------+\n | 01                                      |  Write-back, write and   read allocate |\n +-----------------------------------------+----------------------------------------+\n | 10                                      |  Write-through, no write   allocate    |\n +-----------------------------------------+----------------------------------------+\n | 11                                      |  Write-back, no write   allocate       |\n +-----------------------------------------+----------------------------------------+\n */\n\n/* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for flash\n * region. */\n#ifndef configTEX_S_C_B_FLASH\n    /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */\n    #define configTEX_S_C_B_FLASH    ( 0x07UL )\n#endif\n\n/* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for RAM\n * region. */\n#ifndef configTEX_S_C_B_SRAM\n    /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */\n    #define configTEX_S_C_B_SRAM          ( 0x07UL )\n#endif\n\n#define portGENERAL_PERIPHERALS_REGION    ( configTOTAL_MPU_REGIONS - 5UL )\n#define portSTACK_REGION                  ( configTOTAL_MPU_REGIONS - 4UL )\n#define portUNPRIVILEGED_FLASH_REGION     ( configTOTAL_MPU_REGIONS - 3UL )\n#define portPRIVILEGED_FLASH_REGION       ( configTOTAL_MPU_REGIONS - 2UL )\n#define portPRIVILEGED_RAM_REGION         ( configTOTAL_MPU_REGIONS - 1UL )\n#define portFIRST_CONFIGURABLE_REGION     ( 0UL )\n#define portLAST_CONFIGURABLE_REGION      ( configTOTAL_MPU_REGIONS - 6UL )\n#define portNUM_CONFIGURABLE_REGIONS      ( configTOTAL_MPU_REGIONS - 5UL )\n#define portTOTAL_NUM_REGIONS_IN_TCB      ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus 1 to create space for the stack region. */\n\n#define portSWITCH_TO_USER_MODE()    __asm volatile ( \" mrs r0, control \\n orr r0, r0, #1 \\n msr control, r0 \" ::: \"r0\", \"memory\" )\n\ntypedef struct MPU_REGION_REGISTERS\n{\n    uint32_t ulRegionBaseAddress;\n    uint32_t ulRegionAttribute;\n} xMPU_REGION_REGISTERS;\n\ntypedef struct MPU_SETTINGS\n{\n    xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS_IN_TCB ];\n} xMPU_SETTINGS;\n\n/* Architecture specifics. */\n#define portSTACK_GROWTH      ( -1 )\n#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\n#define portBYTE_ALIGNMENT    8\n/*-----------------------------------------------------------*/\n\n/* SVC numbers for various services. */\n#define portSVC_START_SCHEDULER    0\n#define portSVC_YIELD              1\n#define portSVC_RAISE_PRIVILEGE    2\n\n/* Scheduler utilities. */\n\n#define portYIELD()    __asm volatile ( \"\tSVC\t%0\t\\n\"::\"i\" ( portSVC_YIELD ) : \"memory\" )\n#define portYIELD_WITHIN_API()                          \\\n    {                                                   \\\n        /* Set a PendSV to request a context switch. */ \\\n        portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \\\n        __DSB();                                        \\\n        __ISB();                                        \\\n    }\n\n#define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )\n#define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )\n#define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired != pdFALSE ) portYIELD_WITHIN_API(); } while( 0 )\n#define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )\n/*-----------------------------------------------------------*/\n\n/* Architecture specific optimisations. */\n#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION\n    #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1\n#endif\n\n#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )\n\n/* Check the configuration. */\n    #if ( configMAX_PRIORITIES > 32 )\n        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.\n    #endif\n\n/* Store/clear the ready priorities in a bit map. */\n    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )\n    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )\n\n/*-----------------------------------------------------------*/\n\n    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ( ( uint32_t ) __CLZ( ( uxReadyPriorities ) ) ) )\n\n#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */\n/*-----------------------------------------------------------*/\n\n/* Critical section management. */\nextern void vPortEnterCritical( void );\nextern void vPortExitCritical( void );\n\n#if( configENABLE_ERRATA_837070_WORKAROUND == 1 )\n    #define portDISABLE_INTERRUPTS()                               \\\n        {                                                          \\\n            __disable_interrupt();                                 \\\n            __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \\\n            __DSB();                                               \\\n            __ISB();                                               \\\n            __enable_interrupt();                                  \\\n        }\n#else\n    #define portDISABLE_INTERRUPTS()                               \\\n        {                                                          \\\n            __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \\\n            __DSB();                                               \\\n            __ISB();                                               \\\n        }\n#endif\n\n#define portENABLE_INTERRUPTS()                   __set_BASEPRI( 0 )\n#define portENTER_CRITICAL()                      vPortEnterCritical()\n#define portEXIT_CRITICAL()                       vPortExitCritical()\n#define portSET_INTERRUPT_MASK_FROM_ISR()         __get_BASEPRI(); portDISABLE_INTERRUPTS()\n#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    __set_BASEPRI( x )\n/*-----------------------------------------------------------*/\n\n/* Task function macros as described on the FreeRTOS.org WEB site.  These are\n * not necessary for to use this port.  They are defined so the common demo files\n * (which build with all the ports) will build. */\n#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )\n#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )\n/*-----------------------------------------------------------*/\n\n#ifdef configASSERT\n    void vPortValidateInterruptPriority( void );\n    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()\n#endif\n\n/* portNOP() is not required by this port. */\n#define portNOP()\n\n#define portINLINE              __inline\n\n#ifndef portFORCE_INLINE\n    #define portFORCE_INLINE    inline __attribute__( ( always_inline ) )\n#endif\n\n/*-----------------------------------------------------------*/\n\nportFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )\n{\n    uint32_t ulCurrentInterrupt;\n    BaseType_t xReturn;\n\n    /* Obtain the number of the currently executing interrupt. */\n    __asm volatile ( \"mrs %0, ipsr\" : \"=r\" ( ulCurrentInterrupt )::\"memory\" );\n\n    if( ulCurrentInterrupt == 0 )\n    {\n        xReturn = pdFALSE;\n    }\n    else\n    {\n        xReturn = pdTRUE;\n    }\n\n    return xReturn;\n}\n\n\n/*-----------------------------------------------------------*/\n\nextern BaseType_t xIsPrivileged( void );\nextern void vResetPrivilege( void );\n\n/**\n * @brief Checks whether or not the processor is privileged.\n *\n * @return 1 if the processor is already privileged, 0 otherwise.\n */\n#define portIS_PRIVILEGED()      xIsPrivileged()\n\n/**\n * @brief Raise an SVC request to raise privilege.\n */\n#define portRAISE_PRIVILEGE()    __asm volatile ( \"svc %0 \\n\" ::\"i\" ( portSVC_RAISE_PRIVILEGE ) : \"memory\" );\n\n/**\n * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\n * register.\n */\n#define portRESET_PRIVILEGE()    vResetPrivilege()\n/*-----------------------------------------------------------*/\n\n#ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY\n    #warning \"configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. https://www.FreeRTOS.org/FreeRTOS-V10.3.x.html\"\n    #define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY    0\n#endif\n/*-----------------------------------------------------------*/\n\n/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in\n * the source code because to do so would cause other compilers to generate\n * warnings. */\n#pragma diag_suppress=Pe191\n#pragma diag_suppress=Pa082\n#pragma diag_suppress=Be006\n/*-----------------------------------------------------------*/\n\n/* *INDENT-OFF* */\n#ifdef __cplusplus\n    }\n#endif\n/* *INDENT-ON* */\n\n#endif /* PORTMACRO_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM55/non_secure/port.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\n * all the API functions to use the MPU wrappers. That should only be done when\n * task.h is included from an application file. */\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n/* MPU wrappers includes. */\n#include \"mpu_wrappers.h\"\n\n/* Portasm includes. */\n#include \"portasm.h\"\n\n#if ( configENABLE_TRUSTZONE == 1 )\n    /* Secure components includes. */\n    #include \"secure_context.h\"\n    #include \"secure_init.h\"\n#endif /* configENABLE_TRUSTZONE */\n\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/**\n * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only\n * i.e. the processor boots as secure and never jumps to the non-secure side.\n * The Trust Zone support in the port must be disabled in order to run FreeRTOS\n * on the secure side. The following are the valid configuration seetings:\n *\n * 1. Run FreeRTOS on the Secure Side:\n *    configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0\n *\n * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:\n *    configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1\n *\n * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:\n *    configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0\n */\n#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )\n    #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.\n#endif\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the NVIC.\n */\n#define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )\n#define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )\n#define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )\n#define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )\n#define portNVIC_SYSTICK_ENABLE_BIT           ( 1UL << 0UL )\n#define portNVIC_SYSTICK_INT_BIT              ( 1UL << 1UL )\n#define portNVIC_SYSTICK_CLK_BIT              ( 1UL << 2UL )\n#define portNVIC_SYSTICK_COUNT_FLAG_BIT       ( 1UL << 16UL )\n#define portNVIC_PEND_SYSTICK_CLEAR_BIT       ( 1UL << 25UL )\n#define portNVIC_PEND_SYSTICK_SET_BIT         ( 1UL << 26UL )\n#define portMIN_INTERRUPT_PRIORITY            ( 255UL )\n#define portNVIC_PENDSV_PRI                   ( portMIN_INTERRUPT_PRIORITY << 16UL )\n#define portNVIC_SYSTICK_PRI                  ( portMIN_INTERRUPT_PRIORITY << 24UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the SCB.\n */\n#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( volatile uint32_t * ) 0xe000ed24 )\n#define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the FPU.\n */\n#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 )              /* Coprocessor Access Control Register. */\n#define portCPACR_CP10_VALUE    ( 3UL )\n#define portCPACR_CP11_VALUE    portCPACR_CP10_VALUE\n#define portCPACR_CP10_POS      ( 20UL )\n#define portCPACR_CP11_POS      ( 22UL )\n\n#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 )              /* Floating Point Context Control Register. */\n#define portFPCCR_ASPEN_POS     ( 31UL )\n#define portFPCCR_ASPEN_MASK    ( 1UL << portFPCCR_ASPEN_POS )\n#define portFPCCR_LSPEN_POS     ( 30UL )\n#define portFPCCR_LSPEN_MASK    ( 1UL << portFPCCR_LSPEN_POS )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the MPU.\n */\n#define portMPU_TYPE_REG                      ( *( ( volatile uint32_t * ) 0xe000ed90 ) )\n#define portMPU_CTRL_REG                      ( *( ( volatile uint32_t * ) 0xe000ed94 ) )\n#define portMPU_RNR_REG                       ( *( ( volatile uint32_t * ) 0xe000ed98 ) )\n\n#define portMPU_RBAR_REG                      ( *( ( volatile uint32_t * ) 0xe000ed9c ) )\n#define portMPU_RLAR_REG                      ( *( ( volatile uint32_t * ) 0xe000eda0 ) )\n\n#define portMPU_RBAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda4 ) )\n#define portMPU_RLAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda8 ) )\n\n#define portMPU_RBAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edac ) )\n#define portMPU_RLAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edb0 ) )\n\n#define portMPU_RBAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb4 ) )\n#define portMPU_RLAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb8 ) )\n\n#define portMPU_MAIR0_REG                     ( *( ( volatile uint32_t * ) 0xe000edc0 ) )\n#define portMPU_MAIR1_REG                     ( *( ( volatile uint32_t * ) 0xe000edc4 ) )\n\n#define portMPU_RBAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */\n#define portMPU_RLAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */\n\n#define portMPU_MAIR_ATTR0_POS                ( 0UL )\n#define portMPU_MAIR_ATTR0_MASK               ( 0x000000ff )\n\n#define portMPU_MAIR_ATTR1_POS                ( 8UL )\n#define portMPU_MAIR_ATTR1_MASK               ( 0x0000ff00 )\n\n#define portMPU_MAIR_ATTR2_POS                ( 16UL )\n#define portMPU_MAIR_ATTR2_MASK               ( 0x00ff0000 )\n\n#define portMPU_MAIR_ATTR3_POS                ( 24UL )\n#define portMPU_MAIR_ATTR3_MASK               ( 0xff000000 )\n\n#define portMPU_MAIR_ATTR4_POS                ( 0UL )\n#define portMPU_MAIR_ATTR4_MASK               ( 0x000000ff )\n\n#define portMPU_MAIR_ATTR5_POS                ( 8UL )\n#define portMPU_MAIR_ATTR5_MASK               ( 0x0000ff00 )\n\n#define portMPU_MAIR_ATTR6_POS                ( 16UL )\n#define portMPU_MAIR_ATTR6_MASK               ( 0x00ff0000 )\n\n#define portMPU_MAIR_ATTR7_POS                ( 24UL )\n#define portMPU_MAIR_ATTR7_MASK               ( 0xff000000 )\n\n#define portMPU_RLAR_ATTR_INDEX0              ( 0UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX1              ( 1UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX2              ( 2UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX3              ( 3UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX4              ( 4UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX5              ( 5UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX6              ( 6UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX7              ( 7UL << 1UL )\n\n#define portMPU_RLAR_REGION_ENABLE            ( 1UL )\n\n/* Enable privileged access to unmapped region. */\n#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )\n\n/* Enable MPU. */\n#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )\n\n/* Expected value of the portMPU_TYPE register. */\n#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief The maximum 24-bit number.\n *\n * It is needed because the systick is a 24-bit counter.\n */\n#define portMAX_24_BIT_NUMBER       ( 0xffffffUL )\n\n/**\n * @brief A fiddle factor to estimate the number of SysTick counts that would\n * have occurred while the SysTick counter is stopped during tickless idle\n * calculations.\n */\n#define portMISSED_COUNTS_FACTOR    ( 94UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to set up the initial stack.\n */\n#define portINITIAL_XPSR    ( 0x01000000 )\n\n#if ( configRUN_FREERTOS_SECURE_ONLY == 1 )\n\n/**\n * @brief Initial EXC_RETURN value.\n *\n *     FF         FF         FF         FD\n * 1111 1111  1111 1111  1111 1111  1111 1101\n *\n * Bit[6] - 1 --> The exception was taken from the Secure state.\n * Bit[5] - 1 --> Do not skip stacking of additional state context.\n * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\n * Bit[3] - 1 --> Return to the Thread mode.\n * Bit[2] - 1 --> Restore registers from the process stack.\n * Bit[1] - 0 --> Reserved, 0.\n * Bit[0] - 1 --> The exception was taken to the Secure state.\n */\n    #define portINITIAL_EXC_RETURN    ( 0xfffffffd )\n#else\n\n/**\n * @brief Initial EXC_RETURN value.\n *\n *     FF         FF         FF         BC\n * 1111 1111  1111 1111  1111 1111  1011 1100\n *\n * Bit[6] - 0 --> The exception was taken from the Non-Secure state.\n * Bit[5] - 1 --> Do not skip stacking of additional state context.\n * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\n * Bit[3] - 1 --> Return to the Thread mode.\n * Bit[2] - 1 --> Restore registers from the process stack.\n * Bit[1] - 0 --> Reserved, 0.\n * Bit[0] - 0 --> The exception was taken to the Non-Secure state.\n */\n    #define portINITIAL_EXC_RETURN    ( 0xffffffbc )\n#endif /* configRUN_FREERTOS_SECURE_ONLY */\n\n/**\n * @brief CONTROL register privileged bit mask.\n *\n * Bit[0] in CONTROL register tells the privilege:\n *  Bit[0] = 0 ==> The task is privileged.\n *  Bit[0] = 1 ==> The task is not privileged.\n */\n#define portCONTROL_PRIVILEGED_MASK         ( 1UL << 0UL )\n\n/**\n * @brief Initial CONTROL register values.\n */\n#define portINITIAL_CONTROL_UNPRIVILEGED    ( 0x3 )\n#define portINITIAL_CONTROL_PRIVILEGED      ( 0x2 )\n\n/**\n * @brief Let the user override the default SysTick clock rate.  If defined by the\n * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the\n * configuration register.\n */\n#ifndef configSYSTICK_CLOCK_HZ\n    #define configSYSTICK_CLOCK_HZ             ( configCPU_CLOCK_HZ )\n    /* Ensure the SysTick is clocked at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( portNVIC_SYSTICK_CLK_BIT )\n#else\n    /* Select the option to clock SysTick not at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( 0 )\n#endif\n\n/**\n * @brief Let the user override the pre-loading of the initial LR with the\n * address of prvTaskExitError() in case it messes up unwinding of the stack\n * in the debugger.\n */\n#ifdef configTASK_RETURN_ADDRESS\n    #define portTASK_RETURN_ADDRESS    configTASK_RETURN_ADDRESS\n#else\n    #define portTASK_RETURN_ADDRESS    prvTaskExitError\n#endif\n\n/**\n * @brief If portPRELOAD_REGISTERS then registers will be given an initial value\n * when a task is created. This helps in debugging at the cost of code size.\n */\n#define portPRELOAD_REGISTERS    1\n\n/**\n * @brief A task is created without a secure context, and must call\n * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes\n * any secure calls.\n */\n#define portNO_SECURE_CONTEXT    0\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Used to catch tasks that attempt to return from their implementing\n * function.\n */\nstatic void prvTaskExitError( void );\n\n#if ( configENABLE_MPU == 1 )\n\n/**\n * @brief Setup the Memory Protection Unit (MPU).\n */\n    static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\n#endif /* configENABLE_MPU */\n\n#if ( configENABLE_FPU == 1 )\n\n/**\n * @brief Setup the Floating Point Unit (FPU).\n */\n    static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;\n#endif /* configENABLE_FPU */\n\n/**\n * @brief Setup the timer to generate the tick interrupts.\n *\n * The implementation in this file is weak to allow application writers to\n * change the timer used to generate the tick interrupt.\n */\nvoid vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Checks whether the current execution context is interrupt.\n *\n * @return pdTRUE if the current execution context is interrupt, pdFALSE\n * otherwise.\n */\nBaseType_t xPortIsInsideInterrupt( void );\n\n/**\n * @brief Yield the processor.\n */\nvoid vPortYield( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Enter critical section.\n */\nvoid vPortEnterCritical( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Exit from critical section.\n */\nvoid vPortExitCritical( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief SysTick handler.\n */\nvoid SysTick_Handler( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief C part of SVC handler.\n */\nportDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION;\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Each task maintains its own interrupt status in the critical nesting\n * variable.\n */\nPRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;\n\n#if ( configENABLE_TRUSTZONE == 1 )\n\n/**\n * @brief Saved as part of the task context to indicate which context the\n * task is using on the secure side.\n */\n    PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;\n#endif /* configENABLE_TRUSTZONE */\n\n#if ( configUSE_TICKLESS_IDLE == 1 )\n\n/**\n * @brief The number of SysTick increments that make up one tick period.\n */\n    PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0;\n\n/**\n * @brief The maximum number of tick periods that can be suppressed is\n * limited by the 24 bit resolution of the SysTick timer.\n */\n    PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0;\n\n/**\n * @brief Compensate for the CPU cycles that pass while the SysTick is\n * stopped (low power functionality only).\n */\n    PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TICKLESS_IDLE == 1 )\n    __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )\n    {\n        uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;\n        TickType_t xModifiableIdleTime;\n\n        /* Make sure the SysTick reload value does not overflow the counter. */\n        if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\n        {\n            xExpectedIdleTime = xMaximumPossibleSuppressedTicks;\n        }\n\n        /* Enter a critical section but don't use the taskENTER_CRITICAL()\n         * method as that will mask interrupts that should exit sleep mode. */\n        __asm volatile ( \"cpsid i\" ::: \"memory\" );\n        __asm volatile ( \"dsb\" );\n        __asm volatile ( \"isb\" );\n\n        /* If a context switch is pending or a task is waiting for the scheduler\n         * to be unsuspended then abandon the low power entry. */\n        if( eTaskConfirmSleepModeStatus() == eAbortSleep )\n        {\n            /* Re-enable interrupts - see comments above the cpsid instruction\n             * above. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n        }\n        else\n        {\n            /* Stop the SysTick momentarily.  The time the SysTick is stopped for\n             * is accounted for as best it can be, but using the tickless mode will\n             * inevitably result in some tiny drift of the time maintained by the\n             * kernel with respect to calendar time. */\n            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );\n\n            /* Use the SysTick current-value register to determine the number of\n             * SysTick decrements remaining until the next tick interrupt.  If the\n             * current-value register is zero, then there are actually\n             * ulTimerCountsForOneTick decrements remaining, not zero, because the\n             * SysTick requests the interrupt when decrementing from 1 to 0. */\n            ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n\n            if( ulSysTickDecrementsLeft == 0 )\n            {\n                ulSysTickDecrementsLeft = ulTimerCountsForOneTick;\n            }\n\n            /* Calculate the reload value required to wait xExpectedIdleTime\n             * tick periods.  -1 is used because this code normally executes part\n             * way through the first tick period.  But if the SysTick IRQ is now\n             * pending, then clear the IRQ, suppressing the first tick, and correct\n             * the reload value to reflect that the second tick period is already\n             * underway.  The expected idle time is always at least two ticks. */\n            ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );\n\n            if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )\n            {\n                portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;\n                ulReloadValue -= ulTimerCountsForOneTick;\n            }\n\n            if( ulReloadValue > ulStoppedTimerCompensation )\n            {\n                ulReloadValue -= ulStoppedTimerCompensation;\n            }\n\n            /* Set the new reload value. */\n            portNVIC_SYSTICK_LOAD_REG = ulReloadValue;\n\n            /* Clear the SysTick count flag and set the count value back to\n             * zero. */\n            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n            /* Restart SysTick. */\n            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\n\n            /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can\n             * set its parameter to 0 to indicate that its implementation contains\n             * its own wait for interrupt or wait for event instruction, and so wfi\n             * should not be executed again.  However, the original expected idle\n             * time variable must remain unmodified, so a copy is taken. */\n            xModifiableIdleTime = xExpectedIdleTime;\n            configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\n\n            if( xModifiableIdleTime > 0 )\n            {\n                __asm volatile ( \"dsb\" ::: \"memory\" );\n                __asm volatile ( \"wfi\" );\n                __asm volatile ( \"isb\" );\n            }\n\n            configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\n\n            /* Re-enable interrupts to allow the interrupt that brought the MCU\n             * out of sleep mode to execute immediately.  See comments above\n             * the cpsid instruction above. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n            __asm volatile ( \"dsb\" );\n            __asm volatile ( \"isb\" );\n\n            /* Disable interrupts again because the clock is about to be stopped\n             * and interrupts that execute while the clock is stopped will increase\n             * any slippage between the time maintained by the RTOS and calendar\n             * time. */\n            __asm volatile ( \"cpsid i\" ::: \"memory\" );\n            __asm volatile ( \"dsb\" );\n            __asm volatile ( \"isb\" );\n\n            /* Disable the SysTick clock without reading the\n             * portNVIC_SYSTICK_CTRL_REG register to ensure the\n             * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,\n             * the time the SysTick is stopped for is accounted for as best it can\n             * be, but using the tickless mode will inevitably result in some tiny\n             * drift of the time maintained by the kernel with respect to calendar\n             * time*/\n            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );\n\n            /* Determine whether the SysTick has already counted to zero. */\n            if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n            {\n                uint32_t ulCalculatedLoadValue;\n\n                /* The tick interrupt ended the sleep (or is now pending), and\n                 * a new tick period has started.  Reset portNVIC_SYSTICK_LOAD_REG\n                 * with whatever remains of the new tick period. */\n                ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\n\n                /* Don't allow a tiny value, or values that have somehow\n                 * underflowed because the post sleep hook did something\n                 * that took too long or because the SysTick current-value register\n                 * is zero. */\n                if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )\n                {\n                    ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );\n                }\n\n                portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;\n\n                /* As the pending tick will be processed as soon as this\n                 * function exits, the tick value maintained by the tick is stepped\n                 * forward by one less than the time spent waiting. */\n                ulCompleteTickPeriods = xExpectedIdleTime - 1UL;\n            }\n            else\n            {\n                /* Something other than the tick interrupt ended the sleep. */\n\n                /* Use the SysTick current-value register to determine the\n                 * number of SysTick decrements remaining until the expected idle\n                 * time would have ended. */\n                ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n                #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )\n                {\n                    /* If the SysTick is not using the core clock, the current-\n                     * value register might still be zero here.  In that case, the\n                     * SysTick didn't load from the reload register, and there are\n                     * ulReloadValue decrements remaining in the expected idle\n                     * time, not zero. */\n                    if( ulSysTickDecrementsLeft == 0 )\n                    {\n                        ulSysTickDecrementsLeft = ulReloadValue;\n                    }\n                }\n                #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */\n\n                /* Work out how long the sleep lasted rounded to complete tick\n                 * periods (not the ulReload value which accounted for part\n                 * ticks). */\n                ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;\n\n                /* How many complete tick periods passed while the processor\n                 * was waiting? */\n                ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;\n\n                /* The reload value is set to whatever fraction of a single tick\n                 * period remains. */\n                portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;\n            }\n\n            /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,\n             * then set portNVIC_SYSTICK_LOAD_REG back to its standard value.  If\n             * the SysTick is not using the core clock, temporarily configure it to\n             * use the core clock.  This configuration forces the SysTick to load\n             * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next\n             * cycle of the other clock.  Then portNVIC_SYSTICK_LOAD_REG is ready\n             * to receive the standard value immediately. */\n            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n            portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n            #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )\n            {\n                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n            }\n            #else\n            {\n                /* The temporary usage of the core clock has served its purpose,\n                 * as described above.  Resume usage of the other clock. */\n                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\n\n                if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n                {\n                    /* The partial tick period already ended.  Be sure the SysTick\n                     * counts it only once. */\n                    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;\n                }\n\n                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n            }\n            #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */\n\n            /* Step the tick to account for any tick periods that elapsed. */\n            vTaskStepTick( ulCompleteTickPeriods );\n\n            /* Exit with interrupts enabled. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n        }\n    }\n#endif /* configUSE_TICKLESS_IDLE */\n/*-----------------------------------------------------------*/\n\n__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Calculate the constants required to configure the tick interrupt. */\n    #if ( configUSE_TICKLESS_IDLE == 1 )\n    {\n        ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );\n        xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;\n        ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\n    }\n    #endif /* configUSE_TICKLESS_IDLE */\n\n    /* Stop and reset the SysTick. */\n    portNVIC_SYSTICK_CTRL_REG = 0UL;\n    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n    /* Configure SysTick to interrupt at the requested rate. */\n    portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\n    portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvTaskExitError( void )\n{\n    volatile uint32_t ulDummy = 0UL;\n\n    /* A function that implements a task must not exit or attempt to return to\n     * its caller as there is nothing to return to. If a task wants to exit it\n     * should instead call vTaskDelete( NULL ). Artificially force an assert()\n     * to be triggered if configASSERT() is defined, then stop here so\n     * application writers can catch the error. */\n    configASSERT( ulCriticalNesting == ~0UL );\n    portDISABLE_INTERRUPTS();\n\n    while( ulDummy == 0 )\n    {\n        /* This file calls prvTaskExitError() after the scheduler has been\n         * started to remove a compiler warning about the function being\n         * defined but never called.  ulDummy is used purely to quieten other\n         * warnings about code appearing after this function is called - making\n         * ulDummy volatile makes the compiler think the function could return\n         * and therefore not output an 'unreachable code' warning for code that\n         * appears after it. */\n    }\n}\n/*-----------------------------------------------------------*/\n\n#if ( configENABLE_MPU == 1 )\n    static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */\n    {\n        #if defined( __ARMCC_VERSION )\n\n            /* Declaration when these variable are defined in code instead of being\n             * exported from linker scripts. */\n            extern uint32_t * __privileged_functions_start__;\n            extern uint32_t * __privileged_functions_end__;\n            extern uint32_t * __syscalls_flash_start__;\n            extern uint32_t * __syscalls_flash_end__;\n            extern uint32_t * __unprivileged_flash_start__;\n            extern uint32_t * __unprivileged_flash_end__;\n            extern uint32_t * __privileged_sram_start__;\n            extern uint32_t * __privileged_sram_end__;\n        #else /* if defined( __ARMCC_VERSION ) */\n            /* Declaration when these variable are exported from linker scripts. */\n            extern uint32_t __privileged_functions_start__[];\n            extern uint32_t __privileged_functions_end__[];\n            extern uint32_t __syscalls_flash_start__[];\n            extern uint32_t __syscalls_flash_end__[];\n            extern uint32_t __unprivileged_flash_start__[];\n            extern uint32_t __unprivileged_flash_end__[];\n            extern uint32_t __privileged_sram_start__[];\n            extern uint32_t __privileged_sram_end__[];\n        #endif /* defined( __ARMCC_VERSION ) */\n\n        /* The only permitted number of regions are 8 or 16. */\n        configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );\n\n        /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */\n        configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );\n\n        /* Check that the MPU is present. */\n        if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )\n        {\n            /* MAIR0 - Index 0. */\n            portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\n            /* MAIR0 - Index 1. */\n            portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\n\n            /* Setup privileged flash as Read Only so that privileged tasks can\n             * read it but not modify. */\n            portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_PRIVILEGED_READ_ONLY );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Setup unprivileged flash as Read Only by both privileged and\n             * unprivileged tasks. All tasks can read it but no-one can modify. */\n            portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_READ_ONLY );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Setup unprivileged syscalls flash as Read Only by both privileged\n             * and unprivileged tasks. All tasks can read it but no-one can modify. */\n            portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_READ_ONLY );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Setup RAM containing kernel data for privileged access only. */\n            portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\n                               ( portMPU_REGION_EXECUTE_NEVER );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Enable mem fault. */\n            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;\n\n            /* Enable MPU with privileged background access i.e. unmapped\n             * regions have privileged access. */\n            portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );\n        }\n    }\n#endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\n#if ( configENABLE_FPU == 1 )\n    static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */\n    {\n        #if ( configENABLE_TRUSTZONE == 1 )\n        {\n            /* Enable non-secure access to the FPU. */\n            SecureInit_EnableNSFPUAccess();\n        }\n        #endif /* configENABLE_TRUSTZONE */\n\n        /* CP10 = 11 ==> Full access to FPU i.e. both privileged and\n         * unprivileged code should be able to access FPU. CP11 should be\n         * programmed to the same value as CP10. */\n        *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |\n                            ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )\n                            );\n\n        /* ASPEN = 1 ==> Hardware should automatically preserve floating point\n         * context on exception entry and restore on exception return.\n         * LSPEN = 1 ==> Enable lazy context save of FP state. */\n        *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );\n    }\n#endif /* configENABLE_FPU */\n/*-----------------------------------------------------------*/\n\nvoid vPortYield( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Set a PendSV to request a context switch. */\n    portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\n\n    /* Barriers are normally not required but do ensure the code is\n     * completely within the specified behaviour for the architecture. */\n    __asm volatile ( \"dsb\" ::: \"memory\" );\n    __asm volatile ( \"isb\" );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */\n{\n    portDISABLE_INTERRUPTS();\n    ulCriticalNesting++;\n\n    /* Barriers are normally not required but do ensure the code is\n     * completely within the specified behaviour for the architecture. */\n    __asm volatile ( \"dsb\" ::: \"memory\" );\n    __asm volatile ( \"isb\" );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */\n{\n    configASSERT( ulCriticalNesting );\n    ulCriticalNesting--;\n\n    if( ulCriticalNesting == 0 )\n    {\n        portENABLE_INTERRUPTS();\n    }\n}\n/*-----------------------------------------------------------*/\n\nvoid SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */\n{\n    uint32_t ulPreviousMask;\n\n    ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();\n    {\n        /* Increment the RTOS tick. */\n        if( xTaskIncrementTick() != pdFALSE )\n        {\n            /* Pend a context switch. */\n            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\n        }\n    }\n    portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */\n{\n    #if ( configENABLE_MPU == 1 )\n        #if defined( __ARMCC_VERSION )\n\n            /* Declaration when these variable are defined in code instead of being\n             * exported from linker scripts. */\n            extern uint32_t * __syscalls_flash_start__;\n            extern uint32_t * __syscalls_flash_end__;\n        #else\n            /* Declaration when these variable are exported from linker scripts. */\n            extern uint32_t __syscalls_flash_start__[];\n            extern uint32_t __syscalls_flash_end__[];\n        #endif /* defined( __ARMCC_VERSION ) */\n    #endif /* configENABLE_MPU */\n\n    uint32_t ulPC;\n\n    #if ( configENABLE_TRUSTZONE == 1 )\n        uint32_t ulR0, ulR1;\n        extern TaskHandle_t pxCurrentTCB;\n        #if ( configENABLE_MPU == 1 )\n            uint32_t ulControl, ulIsTaskPrivileged;\n        #endif /* configENABLE_MPU */\n    #endif /* configENABLE_TRUSTZONE */\n    uint8_t ucSVCNumber;\n\n    /* Register are stored on the stack in the following order - R0, R1, R2, R3,\n     * R12, LR, PC, xPSR. */\n    ulPC = pulCallerStackAddress[ 6 ];\n    ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];\n\n    switch( ucSVCNumber )\n    {\n        #if ( configENABLE_TRUSTZONE == 1 )\n            case portSVC_ALLOCATE_SECURE_CONTEXT:\n\n                /* R0 contains the stack size passed as parameter to the\n                 * vPortAllocateSecureContext function. */\n                ulR0 = pulCallerStackAddress[ 0 ];\n\n                #if ( configENABLE_MPU == 1 )\n                {\n                    /* Read the CONTROL register value. */\n                    __asm volatile ( \"mrs %0, control\"  : \"=r\" ( ulControl ) );\n\n                    /* The task that raised the SVC is privileged if Bit[0]\n                     * in the CONTROL register is 0. */\n                    ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );\n\n                    /* Allocate and load a context for the secure task. */\n                    xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );\n                }\n                #else /* if ( configENABLE_MPU == 1 ) */\n                {\n                    /* Allocate and load a context for the secure task. */\n                    xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );\n                }\n                #endif /* configENABLE_MPU */\n\n                configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );\n                SecureContext_LoadContext( xSecureContext, pxCurrentTCB );\n                break;\n\n            case portSVC_FREE_SECURE_CONTEXT:\n\n                /* R0 contains TCB being freed and R1 contains the secure\n                 * context handle to be freed. */\n                ulR0 = pulCallerStackAddress[ 0 ];\n                ulR1 = pulCallerStackAddress[ 1 ];\n\n                /* Free the secure context. */\n                SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );\n                break;\n        #endif /* configENABLE_TRUSTZONE */\n\n        case portSVC_START_SCHEDULER:\n            #if ( configENABLE_TRUSTZONE == 1 )\n            {\n                /* De-prioritize the non-secure exceptions so that the\n                 * non-secure pendSV runs at the lowest priority. */\n                SecureInit_DePrioritizeNSExceptions();\n\n                /* Initialize the secure context management system. */\n                SecureContext_Init();\n            }\n            #endif /* configENABLE_TRUSTZONE */\n\n            #if ( configENABLE_FPU == 1 )\n            {\n                /* Setup the Floating Point Unit (FPU). */\n                prvSetupFPU();\n            }\n            #endif /* configENABLE_FPU */\n\n            /* Setup the context of the first task so that the first task starts\n             * executing. */\n            vRestoreContextOfFirstTask();\n            break;\n\n            #if ( configENABLE_MPU == 1 )\n                case portSVC_RAISE_PRIVILEGE:\n\n                    /* Only raise the privilege, if the svc was raised from any of\n                     * the system calls. */\n                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&\n                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )\n                    {\n                        vRaisePrivilege();\n                    }\n                    break;\n            #endif /* configENABLE_MPU */\n\n        default:\n            /* Incorrect SVC call. */\n            configASSERT( pdFALSE );\n    }\n}\n/*-----------------------------------------------------------*/\n/* *INDENT-OFF* */\n#if ( configENABLE_MPU == 1 )\n    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,\n                                         StackType_t * pxEndOfStack,\n                                         TaskFunction_t pxCode,\n                                         void * pvParameters,\n                                         BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */\n#else\n    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,\n                                         StackType_t * pxEndOfStack,\n                                         TaskFunction_t pxCode,\n                                         void * pvParameters ) /* PRIVILEGED_FUNCTION */\n#endif /* configENABLE_MPU */\n/* *INDENT-ON* */\n{\n    /* Simulate the stack frame as it would be created by a context switch\n     * interrupt. */\n    #if ( portPRELOAD_REGISTERS == 0 )\n    {\n        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\n        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\n        pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */\n        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */\n        pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */\n        *pxTopOfStack = portINITIAL_EXC_RETURN;\n\n        #if ( configENABLE_MPU == 1 )\n        {\n            pxTopOfStack--;\n\n            if( xRunPrivileged == pdTRUE )\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n            else\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n        }\n        #endif /* configENABLE_MPU */\n\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\n\n        #if ( configENABLE_TRUSTZONE == 1 )\n        {\n            pxTopOfStack--;\n            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\n        }\n        #endif /* configENABLE_TRUSTZONE */\n    }\n    #else /* portPRELOAD_REGISTERS */\n    {\n        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\n        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04 */\n        pxTopOfStack--;\n        *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN */\n\n        #if ( configENABLE_MPU == 1 )\n        {\n            pxTopOfStack--;\n\n            if( xRunPrivileged == pdTRUE )\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n            else\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n        }\n        #endif /* configENABLE_MPU */\n\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\n\n        #if ( configENABLE_TRUSTZONE == 1 )\n        {\n            pxTopOfStack--;\n            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\n        }\n        #endif /* configENABLE_TRUSTZONE */\n    }\n    #endif /* portPRELOAD_REGISTERS */\n\n    return pxTopOfStack;\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Make PendSV, CallSV and SysTick the same priority as the kernel. */\n    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;\n    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;\n\n    #if ( configENABLE_MPU == 1 )\n    {\n        /* Setup the Memory Protection Unit (MPU). */\n        prvSetupMPU();\n    }\n    #endif /* configENABLE_MPU */\n\n    /* Start the timer that generates the tick ISR. Interrupts are disabled\n     * here already. */\n    vPortSetupTimerInterrupt();\n\n    /* Initialize the critical nesting count ready for the first task. */\n    ulCriticalNesting = 0;\n\n    /* Start the first task. */\n    vStartFirstTask();\n\n    /* Should never get here as the tasks will now be executing. Call the task\n     * exit error function to prevent compiler warnings about a static function\n     * not being called in the case that the application writer overrides this\n     * functionality by defining configTASK_RETURN_ADDRESS. Call\n     * vTaskSwitchContext() so link time optimization does not remove the\n     * symbol. */\n    vTaskSwitchContext();\n    prvTaskExitError();\n\n    /* Should not get here. */\n    return 0;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Not implemented in ports where there is nothing to return to.\n     * Artificially force an assert. */\n    configASSERT( ulCriticalNesting == 1000UL );\n}\n/*-----------------------------------------------------------*/\n\n#if ( configENABLE_MPU == 1 )\n    void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,\n                                    const struct xMEMORY_REGION * const xRegions,\n                                    StackType_t * pxBottomOfStack,\n                                    uint32_t ulStackDepth )\n    {\n        uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;\n        int32_t lIndex = 0;\n\n        #if defined( __ARMCC_VERSION )\n\n            /* Declaration when these variable are defined in code instead of being\n             * exported from linker scripts. */\n            extern uint32_t * __privileged_sram_start__;\n            extern uint32_t * __privileged_sram_end__;\n        #else\n            /* Declaration when these variable are exported from linker scripts. */\n            extern uint32_t __privileged_sram_start__[];\n            extern uint32_t __privileged_sram_end__[];\n        #endif /* defined( __ARMCC_VERSION ) */\n\n        /* Setup MAIR0. */\n        xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\n        xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\n\n        /* This function is called automatically when the task is created - in\n         * which case the stack region parameters will be valid.  At all other\n         * times the stack parameters will not be valid and it is assumed that\n         * the stack region has already been configured. */\n        if( ulStackDepth > 0 )\n        {\n            ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;\n            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;\n\n            /* If the stack is within the privileged SRAM, do not protect it\n             * using a separate MPU region. This is needed because privileged\n             * SRAM is already protected using an MPU region and ARMv8-M does\n             * not allow overlapping MPU regions. */\n            if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) &&\n                ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) )\n            {\n                xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0;\n                xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0;\n            }\n            else\n            {\n                /* Define the region that allows access to the stack. */\n                ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK;\n                ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\n\n                xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |\n                                                             ( portMPU_REGION_NON_SHAREABLE ) |\n                                                             ( portMPU_REGION_READ_WRITE ) |\n                                                             ( portMPU_REGION_EXECUTE_NEVER );\n\n                xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) |\n                                                             ( portMPU_RLAR_ATTR_INDEX0 ) |\n                                                             ( portMPU_RLAR_REGION_ENABLE );\n            }\n        }\n\n        /* User supplied configurable regions. */\n        for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )\n        {\n            /* If xRegions is NULL i.e. the task has not specified any MPU\n             * region, the else part ensures that all the configurable MPU\n             * regions are invalidated. */\n            if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )\n            {\n                /* Translate the generic region definition contained in xRegions\n                 * into the ARMv8 specific MPU settings that are then stored in\n                 * xMPUSettings. */\n                ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;\n                ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;\n                ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\n\n                /* Start address. */\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |\n                                                                          ( portMPU_REGION_NON_SHAREABLE );\n\n                /* RO/RW. */\n                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )\n                {\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );\n                }\n                else\n                {\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );\n                }\n\n                /* XN. */\n                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )\n                {\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );\n                }\n\n                /* End Address. */\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |\n                                                                          ( portMPU_RLAR_REGION_ENABLE );\n\n                /* Normal memory/ Device memory. */\n                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )\n                {\n                    /* Attr1 in MAIR0 is configured as device memory. */\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;\n                }\n                else\n                {\n                    /* Attr0 in MAIR0 is configured as normal memory. */\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;\n                }\n            }\n            else\n            {\n                /* Invalidate the region. */\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;\n            }\n\n            lIndex++;\n        }\n    }\n#endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\nBaseType_t xPortIsInsideInterrupt( void )\n{\n    uint32_t ulCurrentInterrupt;\n    BaseType_t xReturn;\n\n    /* Obtain the number of the currently executing interrupt. Interrupt Program\n     * Status Register (IPSR) holds the exception number of the currently-executing\n     * exception or zero for Thread mode.*/\n    __asm volatile ( \"mrs %0, ipsr\" : \"=r\" ( ulCurrentInterrupt )::\"memory\" );\n\n    if( ulCurrentInterrupt == 0 )\n    {\n        xReturn = pdFALSE;\n    }\n    else\n    {\n        xReturn = pdTRUE;\n    }\n\n    return xReturn;\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM55/non_secure/portasm.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef __PORT_ASM_H__\n#define __PORT_ASM_H__\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n\n/* MPU wrappers includes. */\n#include \"mpu_wrappers.h\"\n\n/**\n * @brief Restore the context of the first task so that the first task starts\n * executing.\n */\nvoid vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Checks whether or not the processor is privileged.\n *\n * @return 1 if the processor is already privileged, 0 otherwise.\n */\nBaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );\n\n/**\n * @brief Raises the privilege level by clearing the bit 0 of the CONTROL\n * register.\n *\n * @note This is a privileged function and should only be called from the kenrel\n * code.\n *\n * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.\n *  Bit[0] = 0 --> The processor is running privileged\n *  Bit[0] = 1 --> The processor is running unprivileged.\n */\nvoid vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\n * register.\n *\n * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.\n *  Bit[0] = 0 --> The processor is running privileged\n *  Bit[0] = 1 --> The processor is running unprivileged.\n */\nvoid vResetPrivilege( void ) __attribute__( ( naked ) );\n\n/**\n * @brief Starts the first task.\n */\nvoid vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Disables interrupts.\n */\nuint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Enables interrupts.\n */\nvoid vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief PendSV Exception handler.\n */\nvoid PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief SVC Handler.\n */\nvoid SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Allocate a Secure context for the calling task.\n *\n * @param[in] ulSecureStackSize The size of the stack to be allocated on the\n * secure side for the calling task.\n */\nvoid vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) );\n\n/**\n * @brief Free the task's secure context.\n *\n * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.\n */\nvoid vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n#endif /* __PORT_ASM_H__ */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM55/non_secure/portasm.s",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n/* Including FreeRTOSConfig.h here will cause build errors if the header file\ncontains code not understood by the assembler - for example the 'extern' keyword.\nTo avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so\nthe code is included in C files but excluded by the preprocessor in assembly\nfiles (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */\n#include \"FreeRTOSConfig.h\"\n\n\tEXTERN pxCurrentTCB\n\tEXTERN xSecureContext\n\tEXTERN vTaskSwitchContext\n\tEXTERN vPortSVCHandler_C\n\tEXTERN SecureContext_SaveContext\n\tEXTERN SecureContext_LoadContext\n\n\tPUBLIC xIsPrivileged\n\tPUBLIC vResetPrivilege\n\tPUBLIC vPortAllocateSecureContext\n\tPUBLIC vRestoreContextOfFirstTask\n\tPUBLIC vRaisePrivilege\n\tPUBLIC vStartFirstTask\n\tPUBLIC ulSetInterruptMask\n\tPUBLIC vClearInterruptMask\n\tPUBLIC PendSV_Handler\n\tPUBLIC SVC_Handler\n\tPUBLIC vPortFreeSecureContext\n/*-----------------------------------------------------------*/\n\n/*---------------- Unprivileged Functions -------------------*/\n\n/*-----------------------------------------------------------*/\n\n\tSECTION .text:CODE:NOROOT(2)\n\tTHUMB\n/*-----------------------------------------------------------*/\n\nxIsPrivileged:\n\tmrs r0, control\t\t\t\t\t\t\t/* r0 = CONTROL. */\n\ttst r0, #1\t\t\t\t\t\t\t\t/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\n\tite ne\n\tmovne r0, #0\t\t\t\t\t\t\t/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\n\tmoveq r0, #1\t\t\t\t\t\t\t/* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */\n\tbx lr\t\t\t\t\t\t\t\t\t/* Return. */\n/*-----------------------------------------------------------*/\n\nvResetPrivilege:\n\tmrs r0, control\t\t\t\t\t\t\t/* r0 = CONTROL. */\n\torr r0, r0, #1\t\t\t\t\t\t\t/* r0 = r0 | 1. */\n\tmsr control, r0\t\t\t\t\t\t\t/* CONTROL = r0. */\n\tbx lr\t\t\t\t\t\t\t\t\t/* Return to the caller. */\n/*-----------------------------------------------------------*/\n\nvPortAllocateSecureContext:\n\tsvc 0\t\t\t\t\t\t\t\t\t/* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 0. */\n\tbx lr\t\t\t\t\t\t\t\t\t/* Return. */\n/*-----------------------------------------------------------*/\n\n/*----------------- Privileged Functions --------------------*/\n\n/*-----------------------------------------------------------*/\n\n\tSECTION privileged_functions:CODE:NOROOT(2)\n\tTHUMB\n/*-----------------------------------------------------------*/\n\nvRestoreContextOfFirstTask:\n\tldr  r2, =pxCurrentTCB\t\t\t\t\t/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n\tldr  r3, [r2]\t\t\t\t\t\t\t/* Read pxCurrentTCB. */\n\tldr  r0, [r3]\t\t\t\t\t\t\t/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\n\n#if ( configENABLE_MPU == 1 )\n\tdmb\t\t\t\t\t\t\t\t\t\t/* Complete outstanding transfers before disabling MPU. */\n\tldr r2, =0xe000ed94\t\t\t\t\t\t/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n\tldr r4, [r2]\t\t\t\t\t\t\t/* Read the value of MPU_CTRL. */\n\tbic r4, r4, #1\t\t\t\t\t\t\t/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\n\tstr r4, [r2]\t\t\t\t\t\t\t/* Disable MPU. */\n\n\tadds r3, #4\t\t\t\t\t\t\t\t/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\n\tldr  r4, [r3]\t\t\t\t\t\t\t/* r4 = *r3 i.e. r4 = MAIR0. */\n\tldr  r2, =0xe000edc0\t\t\t\t\t/* r2 = 0xe000edc0 [Location of MAIR0]. */\n\tstr  r4, [r2]\t\t\t\t\t\t\t/* Program MAIR0. */\n\tldr  r2, =0xe000ed98\t\t\t\t\t/* r2 = 0xe000ed98 [Location of RNR]. */\n\tmovs r4, #4\t\t\t\t\t\t\t\t/* r4 = 4. */\n\tstr  r4, [r2]\t\t\t\t\t\t\t/* Program RNR = 4. */\n\tadds r3, #4\t\t\t\t\t\t\t\t/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */\n\tldr  r2, =0xe000ed9c\t\t\t\t\t/* r2 = 0xe000ed9c [Location of RBAR]. */\n\tldmia r3!, {r4-r11}\t\t\t\t\t\t/* Read 4 set of RBAR/RLAR registers from TCB. */\n\tstmia r2!, {r4-r11}\t\t\t\t\t\t/* Write 4 set of RBAR/RLAR registers using alias registers. */\n\n\tldr r2, =0xe000ed94\t\t\t\t\t\t/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n\tldr r4, [r2]\t\t\t\t\t\t\t/* Read the value of MPU_CTRL. */\n\torr r4, r4, #1\t\t\t\t\t\t\t/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\n\tstr r4, [r2]\t\t\t\t\t\t\t/* Enable MPU. */\n\tdsb\t\t\t\t\t\t\t\t\t\t/* Force memory writes before continuing. */\n#endif /* configENABLE_MPU */\n\n#if ( configENABLE_MPU == 1 )\n\tldm  r0!, {r1-r4}\t\t\t\t\t\t/* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */\n\tldr  r5, =xSecureContext\n\tstr  r1, [r5]\t\t\t\t\t\t\t/* Set xSecureContext to this task's value for the same. */\n\tmsr  psplim, r2\t\t\t\t\t\t\t/* Set this task's PSPLIM value. */\n\tmsr  control, r3\t\t\t\t\t\t/* Set this task's CONTROL value. */\n\tadds r0, #32\t\t\t\t\t\t\t/* Discard everything up to r0. */\n\tmsr  psp, r0\t\t\t\t\t\t\t/* This is now the new top of stack to use in the task. */\n\tisb\n\tmov  r0, #0\n\tmsr  basepri, r0\t\t\t\t\t\t/* Ensure that interrupts are enabled when the first task starts. */\n\tbx   r4\t\t\t\t\t\t\t\t\t/* Finally, branch to EXC_RETURN. */\n#else /* configENABLE_MPU */\n\tldm  r0!, {r1-r3}\t\t\t\t\t\t/* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */\n\tldr  r4, =xSecureContext\n\tstr  r1, [r4]\t\t\t\t\t\t\t/* Set xSecureContext to this task's value for the same. */\n\tmsr  psplim, r2\t\t\t\t\t\t\t/* Set this task's PSPLIM value. */\n\tmovs r1, #2\t\t\t\t\t\t\t\t/* r1 = 2. */\n\tmsr  CONTROL, r1\t\t\t\t\t\t/* Switch to use PSP in the thread mode. */\n\tadds r0, #32\t\t\t\t\t\t\t/* Discard everything up to r0. */\n\tmsr  psp, r0\t\t\t\t\t\t\t/* This is now the new top of stack to use in the task. */\n\tisb\n\tmov  r0, #0\n\tmsr  basepri, r0\t\t\t\t\t\t/* Ensure that interrupts are enabled when the first task starts. */\n\tbx   r3\t\t\t\t\t\t\t\t\t/* Finally, branch to EXC_RETURN. */\n#endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\nvRaisePrivilege:\n\tmrs  r0, control\t\t\t\t\t\t/* Read the CONTROL register. */\n\tbic r0, r0, #1\t\t\t\t\t\t\t/* Clear the bit 0. */\n\tmsr  control, r0\t\t\t\t\t\t/* Write back the new CONTROL value. */\n\tbx lr\t\t\t\t\t\t\t\t\t/* Return to the caller. */\n/*-----------------------------------------------------------*/\n\nvStartFirstTask:\n\tldr r0, =0xe000ed08\t\t\t\t\t\t/* Use the NVIC offset register to locate the stack. */\n\tldr r0, [r0]\t\t\t\t\t\t\t/* Read the VTOR register which gives the address of vector table. */\n\tldr r0, [r0]\t\t\t\t\t\t\t/* The first entry in vector table is stack pointer. */\n\tmsr msp, r0\t\t\t\t\t\t\t\t/* Set the MSP back to the start of the stack. */\n\tcpsie i\t\t\t\t\t\t\t\t\t/* Globally enable interrupts. */\n\tcpsie f\n\tdsb\n\tisb\n\tsvc 2\t\t\t\t\t\t\t\t\t/* System call to start the first task. portSVC_START_SCHEDULER = 2. */\n/*-----------------------------------------------------------*/\n\nulSetInterruptMask:\n\tmrs r0, basepri\t\t\t\t\t\t\t/* r0 = basepri. Return original basepri value. */\n\tmov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY\n\tmsr basepri, r1\t\t\t\t\t\t\t/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */\n\tdsb\n\tisb\n\tbx lr\t\t\t\t\t\t\t\t\t/* Return. */\n/*-----------------------------------------------------------*/\n\nvClearInterruptMask:\n\tmsr basepri, r0\t\t\t\t\t\t\t/* basepri = ulMask. */\n\tdsb\n\tisb\n\tbx lr\t\t\t\t\t\t\t\t\t/* Return. */\n/*-----------------------------------------------------------*/\n\nPendSV_Handler:\n\tldr r3, =xSecureContext\t\t\t\t\t/* Read the location of xSecureContext i.e. &( xSecureContext ). */\n\tldr r0, [r3]\t\t\t\t\t\t\t/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */\n\tldr r3, =pxCurrentTCB\t\t\t\t\t/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n\tldr r1, [r3]\t\t\t\t\t\t\t/* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */\n\tmrs r2, psp\t\t\t\t\t\t\t\t/* Read PSP in r2. */\n\n\tcbz r0, save_ns_context\t\t\t\t\t/* No secure context to save. */\n\tpush {r0-r2, r14}\n\tbl SecureContext_SaveContext\t\t\t/* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */\n\tpop {r0-r3}\t\t\t\t\t\t\t\t/* LR is now in r3. */\n\tmov lr, r3\t\t\t\t\t\t\t\t/* LR = r3. */\n\tlsls r1, r3, #25\t\t\t\t\t\t/* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\n\tbpl save_ns_context\t\t\t\t\t\t/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\n\n\tldr r3, =pxCurrentTCB\t\t\t\t\t/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n\tldr r1, [r3]\t\t\t\t\t\t\t/* Read pxCurrentTCB. */\n#if ( configENABLE_MPU == 1 )\n\tsubs r2, r2, #16\t\t\t\t\t\t/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */\n\tstr r2, [r1]\t\t\t\t\t\t\t/* Save the new top of stack in TCB. */\n\tmrs r1, psplim\t\t\t\t\t\t\t/* r1 = PSPLIM. */\n\tmrs r3, control\t\t\t\t\t\t\t/* r3 = CONTROL. */\n\tmov r4, lr\t\t\t\t\t\t\t\t/* r4 = LR/EXC_RETURN. */\n\tstmia r2!, {r0, r1, r3, r4}\t\t\t\t/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\n#else /* configENABLE_MPU */\n\tsubs r2, r2, #12\t\t\t\t\t\t/* Make space for xSecureContext, PSPLIM and LR on the stack. */\n\tstr r2, [r1]\t\t\t\t\t\t\t/* Save the new top of stack in TCB. */\n\tmrs r1, psplim\t\t\t\t\t\t\t/* r1 = PSPLIM. */\n\tmov r3, lr\t\t\t\t\t\t\t\t/* r3 = LR/EXC_RETURN. */\n\tstmia r2!, {r0, r1, r3}\t\t\t\t\t/* Store xSecureContext, PSPLIM and LR on the stack. */\n#endif /* configENABLE_MPU */\n\tb select_next_task\n\n\tsave_ns_context:\n\t\tldr r3, =pxCurrentTCB\t\t\t\t/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n\t\tldr r1, [r3]\t\t\t\t\t\t/* Read pxCurrentTCB. */\n\t#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )\n\t\ttst lr, #0x10\t\t\t\t\t\t/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */\n\t\tit eq\n\t\tvstmdbeq r2!, {s16-s31}\t\t\t\t/* Store the additional FP context registers which are not saved automatically. */\n\t#endif /* configENABLE_FPU || configENABLE_MVE */\n\t#if ( configENABLE_MPU == 1 )\n\t\tsubs r2, r2, #48\t\t\t\t\t/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */\n\t\tstr r2, [r1]\t\t\t\t\t\t/* Save the new top of stack in TCB. */\n\t\tadds r2, r2, #16\t\t\t\t\t/* r2 = r2 + 16. */\n\t\tstm r2, {r4-r11}\t\t\t\t\t/* Store the registers that are not saved automatically. */\n\t\tmrs r1, psplim\t\t\t\t\t\t/* r1 = PSPLIM. */\n\t\tmrs r3, control\t\t\t\t\t\t/* r3 = CONTROL. */\n\t\tmov r4, lr\t\t\t\t\t\t\t/* r4 = LR/EXC_RETURN. */\n\t\tsubs r2, r2, #16\t\t\t\t\t/* r2 = r2 - 16. */\n\t\tstmia r2!, {r0, r1, r3, r4}\t\t\t/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\n\t#else /* configENABLE_MPU */\n\t\tsubs r2, r2, #44\t\t\t\t\t/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */\n\t\tstr r2, [r1]\t\t\t\t\t\t/* Save the new top of stack in TCB. */\n\t\tadds r2, r2, #12\t\t\t\t\t/* r2 = r2 + 12. */\n\t\tstm r2, {r4-r11}\t\t\t\t\t/* Store the registers that are not saved automatically. */\n\t\tmrs r1, psplim\t\t\t\t\t\t/* r1 = PSPLIM. */\n\t\tmov r3, lr\t\t\t\t\t\t\t/* r3 = LR/EXC_RETURN. */\n\t\tsubs r2, r2, #12\t\t\t\t\t/* r2 = r2 - 12. */\n\t\tstmia r2!, {r0, r1, r3}\t\t\t\t/* Store xSecureContext, PSPLIM and LR on the stack. */\n\t#endif /* configENABLE_MPU */\n\n\tselect_next_task:\n\t\tmov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY\n\t\tmsr basepri, r0\t\t\t\t\t\t/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */\n\t\tdsb\n\t\tisb\n\t\tbl vTaskSwitchContext\n\t\tmov r0, #0\t\t\t\t\t\t\t/* r0 = 0. */\n\t\tmsr basepri, r0\t\t\t\t\t\t/* Enable interrupts. */\n\n\t\tldr r3, =pxCurrentTCB\t\t\t\t/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n\t\tldr r1, [r3]\t\t\t\t\t\t/* Read pxCurrentTCB. */\n\t\tldr r2, [r1]\t\t\t\t\t\t/* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */\n\n\t#if ( configENABLE_MPU == 1 )\n\t\tdmb\t\t\t\t\t\t\t\t\t/* Complete outstanding transfers before disabling MPU. */\n\t\tldr r3, =0xe000ed94\t\t\t\t\t/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */\n\t\tldr r4, [r3]\t\t\t\t\t\t/* Read the value of MPU_CTRL. */\n\t\tbic r4, r4, #1\t\t\t\t\t\t/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\n\t\tstr r4, [r3]\t\t\t\t\t\t/* Disable MPU. */\n\n\t\tadds r1, #4\t\t\t\t\t\t\t/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\n\t\tldr r4, [r1]\t\t\t\t\t\t/* r4 = *r1 i.e. r4 = MAIR0. */\n\t\tldr r3, =0xe000edc0\t\t\t\t\t/* r3 = 0xe000edc0 [Location of MAIR0]. */\n\t\tstr r4, [r3]\t\t\t\t\t\t/* Program MAIR0. */\n\t\tldr r3, =0xe000ed98\t\t\t\t\t/* r3 = 0xe000ed98 [Location of RNR]. */\n\t\tmovs r4, #4\t\t\t\t\t\t\t/* r4 = 4. */\n\t\tstr r4, [r3]\t\t\t\t\t\t/* Program RNR = 4. */\n\t\tadds r1, #4\t\t\t\t\t\t\t/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\n\t\tldr  r3, =0xe000ed9c\t\t\t\t/* r3 = 0xe000ed9c [Location of RBAR]. */\n\t\tldmia r1!, {r4-r11}\t\t\t\t\t/* Read 4 sets of RBAR/RLAR registers from TCB. */\n\t\tstmia r3!, {r4-r11}\t\t\t\t\t/* Write 4 set of RBAR/RLAR registers using alias registers. */\n\n\t\tldr r3, =0xe000ed94\t\t\t\t\t/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */\n\t\tldr r4, [r3]\t\t\t\t\t\t/* Read the value of MPU_CTRL. */\n\t\torr r4, r4, #1\t\t\t\t\t\t/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\n\t\tstr r4, [r3]\t\t\t\t\t\t/* Enable MPU. */\n\t\tdsb\t\t\t\t\t\t\t\t\t/* Force memory writes before continuing. */\n\t#endif /* configENABLE_MPU */\n\n\t#if ( configENABLE_MPU == 1 )\n\t\tldmia r2!, {r0, r1, r3, r4}\t\t\t/* Read from stack - r0 = xSecureContext, r1 = PSPLIM, r3 = CONTROL and r4 = LR. */\n\t\tmsr psplim, r1\t\t\t\t\t\t/* Restore the PSPLIM register value for the task. */\n\t\tmsr control, r3\t\t\t\t\t\t/* Restore the CONTROL register value for the task. */\n\t\tmov lr, r4\t\t\t\t\t\t\t/* LR = r4. */\n\t\tldr r3, =xSecureContext\t\t\t\t/* Read the location of xSecureContext i.e. &( xSecureContext ). */\n\t\tstr r0, [r3]\t\t\t\t\t\t/* Restore the task's xSecureContext. */\n\t\tcbz r0, restore_ns_context\t\t\t/* If there is no secure context for the task, restore the non-secure context. */\n\t\tldr r3, =pxCurrentTCB\t\t\t\t/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n\t\tldr r1, [r3]\t\t\t\t\t\t/* Read pxCurrentTCB. */\n\t\tpush {r2, r4}\n\t\tbl SecureContext_LoadContext\t\t/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */\n\t\tpop {r2, r4}\n\t\tmov lr, r4\t\t\t\t\t\t\t/* LR = r4. */\n\t\tlsls r1, r4, #25\t\t\t\t\t/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\n\t\tbpl restore_ns_context\t\t\t\t/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\n\t\tmsr psp, r2\t\t\t\t\t\t\t/* Remember the new top of stack for the task. */\n\t\tbx lr\n\t#else /* configENABLE_MPU */\n\t\tldmia r2!, {r0, r1, r4}\t\t\t\t/* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */\n\t\tmsr psplim, r1\t\t\t\t\t\t/* Restore the PSPLIM register value for the task. */\n\t\tmov lr, r4\t\t\t\t\t\t\t/* LR = r4. */\n\t\tldr r3, =xSecureContext\t\t\t\t/* Read the location of xSecureContext i.e. &( xSecureContext ). */\n\t\tstr r0, [r3]\t\t\t\t\t\t/* Restore the task's xSecureContext. */\n\t\tcbz r0, restore_ns_context\t\t\t/* If there is no secure context for the task, restore the non-secure context. */\n\t\tldr r3, =pxCurrentTCB\t\t\t\t/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n\t\tldr r1, [r3]\t\t\t\t\t\t/* Read pxCurrentTCB. */\n\t\tpush {r2, r4}\n\t\tbl SecureContext_LoadContext\t\t/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */\n\t\tpop {r2, r4}\n\t\tmov lr, r4\t\t\t\t\t\t\t/* LR = r4. */\n\t\tlsls r1, r4, #25\t\t\t\t\t/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\n\t\tbpl restore_ns_context\t\t\t\t/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\n\t\tmsr psp, r2\t\t\t\t\t\t\t/* Remember the new top of stack for the task. */\n\t\tbx lr\n\t#endif /* configENABLE_MPU */\n\n\trestore_ns_context:\n\t\tldmia r2!, {r4-r11}\t\t\t\t\t/* Restore the registers that are not automatically restored. */\n\t#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )\n\t\ttst lr, #0x10\t\t\t\t\t\t/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */\n\t\tit eq\n\t\tvldmiaeq r2!, {s16-s31}\t\t\t\t/* Restore the additional FP context registers which are not restored automatically. */\n\t#endif /* configENABLE_FPU || configENABLE_MVE */\n\t\tmsr psp, r2\t\t\t\t\t\t\t/* Remember the new top of stack for the task. */\n\t\tbx lr\n/*-----------------------------------------------------------*/\n\nSVC_Handler:\n\ttst lr, #4\n\tite eq\n\tmrseq r0, msp\n\tmrsne r0, psp\n\tb vPortSVCHandler_C\n/*-----------------------------------------------------------*/\n\nvPortFreeSecureContext:\n\t/* r0 = uint32_t *pulTCB. */\n\tldr r2, [r0]\t\t\t\t\t\t\t/* The first item in the TCB is the top of the stack. */\n\tldr r1, [r2]\t\t\t\t\t\t\t/* The first item on the stack is the task's xSecureContext. */\n\tcmp r1, #0\t\t\t\t\t\t\t\t/* Raise svc if task's xSecureContext is not NULL. */\n\tit ne\n\tsvcne 1\t\t\t\t\t\t\t\t\t/* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */\n\tbx lr\t\t\t\t\t\t\t\t\t/* Return. */\n/*-----------------------------------------------------------*/\n\n\tEND\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM55/non_secure/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef PORTMACRO_H\n#define PORTMACRO_H\n\n#ifdef __cplusplus\n    extern \"C\" {\n#endif\n\n#include \"portmacrocommon.h\"\n\n/*------------------------------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the given hardware\n * and compiler.\n *\n * These settings should not be altered.\n *------------------------------------------------------------------------------\n */\n\n#ifndef configENABLE_MVE\n    #error configENABLE_MVE must be defined in FreeRTOSConfig.h. Set configENABLE_MVE to 1 to enable the MVE or 0 to disable the MVE.\n#endif /* configENABLE_MVE */\n/*-----------------------------------------------------------*/\n\n/**\n * Architecture specifics.\n */\n#define portARCH_NAME                       \"Cortex-M55\"\n#define portDONT_DISCARD                    __root\n/*-----------------------------------------------------------*/\n\n#if( configTOTAL_MPU_REGIONS == 16 )\n    #error 16 MPU regions are not yet supported for this port.\n#endif\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Critical section management.\n */\n#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()\n#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )\n/*-----------------------------------------------------------*/\n\n/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in\n * the source code because to do so would cause other compilers to generate\n * warnings. */\n#pragma diag_suppress=Be006\n#pragma diag_suppress=Pa082\n/*-----------------------------------------------------------*/\n\n#ifdef __cplusplus\n    }\n#endif\n\n#endif /* PORTMACRO_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef PORTMACROCOMMON_H\n    #define PORTMACROCOMMON_H\n\n    #ifdef __cplusplus\n        extern \"C\" {\n    #endif\n\n/*------------------------------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the given hardware\n * and compiler.\n *\n * These settings should not be altered.\n *------------------------------------------------------------------------------\n */\n\n    #ifndef configENABLE_FPU\n        #error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.\n    #endif /* configENABLE_FPU */\n\n    #ifndef configENABLE_MPU\n        #error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.\n    #endif /* configENABLE_MPU */\n\n    #ifndef configENABLE_TRUSTZONE\n        #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.\n    #endif /* configENABLE_TRUSTZONE */\n\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Type definitions.\n */\n    #define portCHAR          char\n    #define portFLOAT         float\n    #define portDOUBLE        double\n    #define portLONG          long\n    #define portSHORT         short\n    #define portSTACK_TYPE    uint32_t\n    #define portBASE_TYPE     long\n\n    typedef portSTACK_TYPE   StackType_t;\n    typedef long             BaseType_t;\n    typedef unsigned long    UBaseType_t;\n\n    #if ( configUSE_16_BIT_TICKS == 1 )\n        typedef uint16_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffff\n    #else\n        typedef uint32_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL\n\n/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\n * not need to be guarded with a critical section. */\n        #define portTICK_TYPE_IS_ATOMIC    1\n    #endif\n/*-----------------------------------------------------------*/\n\n/**\n * Architecture specifics.\n */\n    #define portSTACK_GROWTH                   ( -1 )\n    #define portTICK_PERIOD_MS                 ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\n    #define portBYTE_ALIGNMENT                 8\n    #define portNOP()\n    #define portINLINE                         __inline\n    #ifndef portFORCE_INLINE\n        #define portFORCE_INLINE               inline __attribute__( ( always_inline ) )\n    #endif\n    #define portHAS_STACK_OVERFLOW_CHECKING    1\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Extern declarations.\n */\n    extern BaseType_t xPortIsInsideInterrupt( void );\n\n    extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;\n\n    extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;\n    extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;\n\n    extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\n    extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\n\n    #if ( configENABLE_TRUSTZONE == 1 )\n        extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */\n        extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;\n    #endif /* configENABLE_TRUSTZONE */\n\n    #if ( configENABLE_MPU == 1 )\n        extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;\n        extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;\n    #endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\n/**\n * @brief MPU specific constants.\n */\n    #if ( configENABLE_MPU == 1 )\n        #define portUSING_MPU_WRAPPERS    1\n        #define portPRIVILEGE_BIT         ( 0x80000000UL )\n    #else\n        #define portPRIVILEGE_BIT         ( 0x0UL )\n    #endif /* configENABLE_MPU */\n\n/* MPU settings that can be overriden in FreeRTOSConfig.h. */\n#ifndef configTOTAL_MPU_REGIONS\n    /* Define to 8 for backward compatibility. */\n    #define configTOTAL_MPU_REGIONS       ( 8UL )\n#endif\n\n/* MPU regions. */\n    #define portPRIVILEGED_FLASH_REGION                   ( 0UL )\n    #define portUNPRIVILEGED_FLASH_REGION                 ( 1UL )\n    #define portUNPRIVILEGED_SYSCALLS_REGION              ( 2UL )\n    #define portPRIVILEGED_RAM_REGION                     ( 3UL )\n    #define portSTACK_REGION                              ( 4UL )\n    #define portFIRST_CONFIGURABLE_REGION                 ( 5UL )\n    #define portLAST_CONFIGURABLE_REGION                  ( configTOTAL_MPU_REGIONS - 1UL )\n    #define portNUM_CONFIGURABLE_REGIONS                  ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )\n    #define portTOTAL_NUM_REGIONS                         ( portNUM_CONFIGURABLE_REGIONS + 1 )   /* Plus one to make space for the stack region. */\n\n/* Device memory attributes used in MPU_MAIR registers.\n *\n * 8-bit values encoded as follows:\n *  Bit[7:4] - 0000 - Device Memory\n *  Bit[3:2] - 00 --> Device-nGnRnE\n *\t\t\t\t01 --> Device-nGnRE\n *\t\t\t\t10 --> Device-nGRE\n *\t\t\t\t11 --> Device-GRE\n *  Bit[1:0] - 00, Reserved.\n */\n    #define portMPU_DEVICE_MEMORY_nGnRnE                  ( 0x00 )   /* 0000 0000 */\n    #define portMPU_DEVICE_MEMORY_nGnRE                   ( 0x04 )   /* 0000 0100 */\n    #define portMPU_DEVICE_MEMORY_nGRE                    ( 0x08 )   /* 0000 1000 */\n    #define portMPU_DEVICE_MEMORY_GRE                     ( 0x0C )   /* 0000 1100 */\n\n/* Normal memory attributes used in MPU_MAIR registers. */\n    #define portMPU_NORMAL_MEMORY_NON_CACHEABLE           ( 0x44 )   /* Non-cacheable. */\n    #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE    ( 0xFF )   /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */\n\n/* Attributes used in MPU_RBAR registers. */\n    #define portMPU_REGION_NON_SHAREABLE                  ( 0UL << 3UL )\n    #define portMPU_REGION_INNER_SHAREABLE                ( 1UL << 3UL )\n    #define portMPU_REGION_OUTER_SHAREABLE                ( 2UL << 3UL )\n\n    #define portMPU_REGION_PRIVILEGED_READ_WRITE          ( 0UL << 1UL )\n    #define portMPU_REGION_READ_WRITE                     ( 1UL << 1UL )\n    #define portMPU_REGION_PRIVILEGED_READ_ONLY           ( 2UL << 1UL )\n    #define portMPU_REGION_READ_ONLY                      ( 3UL << 1UL )\n\n    #define portMPU_REGION_EXECUTE_NEVER                  ( 1UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Settings to define an MPU region.\n */\n    typedef struct MPURegionSettings\n    {\n        uint32_t ulRBAR; /**< RBAR for the region. */\n        uint32_t ulRLAR; /**< RLAR for the region. */\n    } MPURegionSettings_t;\n\n/**\n * @brief MPU settings as stored in the TCB.\n */\n    typedef struct MPU_SETTINGS\n    {\n        uint32_t ulMAIR0;                                              /**< MAIR0 for the task containing attributes for all the 4 per task regions. */\n        MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */\n    } xMPU_SETTINGS;\n/*-----------------------------------------------------------*/\n\n/**\n * @brief SVC numbers.\n */\n    #define portSVC_ALLOCATE_SECURE_CONTEXT    0\n    #define portSVC_FREE_SECURE_CONTEXT        1\n    #define portSVC_START_SCHEDULER            2\n    #define portSVC_RAISE_PRIVILEGE            3\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Scheduler utilities.\n */\n    #define portYIELD()                                 vPortYield()\n    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )\n    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )\n    #define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )\n    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Critical section management.\n */\n    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulSetInterruptMask()\n    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vClearInterruptMask( x )\n    #define portENTER_CRITICAL()                      vPortEnterCritical()\n    #define portEXIT_CRITICAL()                       vPortExitCritical()\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Tickless idle/low power functionality.\n */\n    #ifndef portSUPPRESS_TICKS_AND_SLEEP\n        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );\n        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )\n    #endif\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Task function macros as described on the FreeRTOS.org WEB site.\n */\n    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )\n    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )\n/*-----------------------------------------------------------*/\n\n    #if ( configENABLE_TRUSTZONE == 1 )\n\n/**\n * @brief Allocate a secure context for the task.\n *\n * Tasks are not created with a secure context. Any task that is going to call\n * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a\n * secure context before it calls any secure function.\n *\n * @param[in] ulSecureStackSize The size of the secure stack to be allocated.\n */\n        #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )\n\n/**\n * @brief Called when a task is deleted to delete the task's secure context,\n * if it has one.\n *\n * @param[in] pxTCB The TCB of the task being deleted.\n */\n        #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )\n    #endif /* configENABLE_TRUSTZONE */\n/*-----------------------------------------------------------*/\n\n    #if ( configENABLE_MPU == 1 )\n\n/**\n * @brief Checks whether or not the processor is privileged.\n *\n * @return 1 if the processor is already privileged, 0 otherwise.\n */\n        #define portIS_PRIVILEGED()      xIsPrivileged()\n\n/**\n * @brief Raise an SVC request to raise privilege.\n *\n * The SVC handler checks that the SVC was raised from a system call and only\n * then it raises the privilege. If this is called from any other place,\n * the privilege is not raised.\n */\n        #define portRAISE_PRIVILEGE()    __asm volatile ( \"svc %0 \\n\" ::\"i\" ( portSVC_RAISE_PRIVILEGE ) : \"memory\" );\n\n/**\n * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\n * register.\n */\n        #define portRESET_PRIVILEGE()    vResetPrivilege()\n    #else\n        #define portIS_PRIVILEGED()\n        #define portRAISE_PRIVILEGE()\n        #define portRESET_PRIVILEGE()\n    #endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Barriers.\n */\n    #define portMEMORY_BARRIER()    __asm volatile ( \"\" ::: \"memory\" )\n/*-----------------------------------------------------------*/\n\n    #ifdef __cplusplus\n        }\n    #endif\n\n#endif /* PORTMACROCOMMON_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM55/secure/secure_context.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Secure context includes. */\n#include \"secure_context.h\"\n\n/* Secure heap includes. */\n#include \"secure_heap.h\"\n\n/* Secure port macros. */\n#include \"secure_port_macros.h\"\n\n/**\n * @brief CONTROL value for privileged tasks.\n *\n * Bit[0] - 0 --> Thread mode is privileged.\n * Bit[1] - 1 --> Thread mode uses PSP.\n */\n#define securecontextCONTROL_VALUE_PRIVILEGED      0x02\n\n/**\n * @brief CONTROL value for un-privileged tasks.\n *\n * Bit[0] - 1 --> Thread mode is un-privileged.\n * Bit[1] - 1 --> Thread mode uses PSP.\n */\n#define securecontextCONTROL_VALUE_UNPRIVILEGED    0x03\n\n/**\n * @brief Size of stack seal values in bytes.\n */\n#define securecontextSTACK_SEAL_SIZE               8\n\n/**\n * @brief Stack seal value as recommended by ARM.\n */\n#define securecontextSTACK_SEAL_VALUE              0xFEF5EDA5\n\n/**\n * @brief Maximum number of secure contexts.\n */\n#ifndef secureconfigMAX_SECURE_CONTEXTS\n    #define secureconfigMAX_SECURE_CONTEXTS        8UL\n#endif\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Pre-allocated array of secure contexts.\n */\nSecureContext_t xSecureContexts[ secureconfigMAX_SECURE_CONTEXTS ];\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Get a free secure context for a task from the secure context pool (xSecureContexts).\n *\n * This function ensures that only one secure context is allocated for a task.\n *\n * @param[in] pvTaskHandle The task handle for which the secure context is allocated.\n *\n * @return Index of a free secure context in the xSecureContexts array.\n */\nstatic uint32_t ulGetSecureContext( void * pvTaskHandle );\n\n/**\n * @brief Return the secure context to the secure context pool (xSecureContexts).\n *\n * @param[in] ulSecureContextIndex Index of the context in the xSecureContexts array.\n */\nstatic void vReturnSecureContext( uint32_t ulSecureContextIndex );\n\n/* These are implemented in assembly. */\nextern void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext );\nextern void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext );\n/*-----------------------------------------------------------*/\n\nstatic uint32_t ulGetSecureContext( void * pvTaskHandle )\n{\n    /* Start with invalid index. */\n    uint32_t i, ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS;\n\n    for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ )\n    {\n        if( ( xSecureContexts[ i ].pucCurrentStackPointer == NULL ) &&\n            ( xSecureContexts[ i ].pucStackLimit == NULL ) &&\n            ( xSecureContexts[ i ].pucStackStart == NULL ) &&\n            ( xSecureContexts[ i ].pvTaskHandle == NULL ) &&\n            ( ulSecureContextIndex == secureconfigMAX_SECURE_CONTEXTS ) )\n        {\n            ulSecureContextIndex = i;\n        }\n        else if( xSecureContexts[ i ].pvTaskHandle == pvTaskHandle )\n        {\n            /* A task can only have one secure context. Do not allocate a second\n             * context for the same task. */\n            ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS;\n            break;\n        }\n    }\n\n    return ulSecureContextIndex;\n}\n/*-----------------------------------------------------------*/\n\nstatic void vReturnSecureContext( uint32_t ulSecureContextIndex )\n{\n    xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = NULL;\n    xSecureContexts[ ulSecureContextIndex ].pucStackLimit = NULL;\n    xSecureContexts[ ulSecureContextIndex ].pucStackStart = NULL;\n    xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = NULL;\n}\n/*-----------------------------------------------------------*/\n\nsecureportNON_SECURE_CALLABLE void SecureContext_Init( void )\n{\n    uint32_t ulIPSR, i;\n    static uint32_t ulSecureContextsInitialized = 0;\n\n    /* Read the Interrupt Program Status Register (IPSR) value. */\n    secureportREAD_IPSR( ulIPSR );\n\n    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\n     * when the processor is running in the Thread Mode. */\n    if( ( ulIPSR != 0 ) && ( ulSecureContextsInitialized == 0 ) )\n    {\n        /* Ensure to initialize secure contexts only once. */\n        ulSecureContextsInitialized = 1;\n\n        /* No stack for thread mode until a task's context is loaded. */\n        secureportSET_PSPLIM( securecontextNO_STACK );\n        secureportSET_PSP( securecontextNO_STACK );\n\n        /* Initialize all secure contexts. */\n        for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ )\n        {\n            xSecureContexts[ i ].pucCurrentStackPointer = NULL;\n            xSecureContexts[ i ].pucStackLimit = NULL;\n            xSecureContexts[ i ].pucStackStart = NULL;\n            xSecureContexts[ i ].pvTaskHandle = NULL;\n        }\n\n        #if ( configENABLE_MPU == 1 )\n            {\n                /* Configure thread mode to use PSP and to be unprivileged. */\n                secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );\n            }\n        #else /* configENABLE_MPU */\n            {\n                /* Configure thread mode to use PSP and to be privileged. */\n                secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );\n            }\n        #endif /* configENABLE_MPU */\n    }\n}\n/*-----------------------------------------------------------*/\n\n#if ( configENABLE_MPU == 1 )\n    secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,\n                                                                                       uint32_t ulIsTaskPrivileged,\n                                                                                       void * pvTaskHandle )\n#else /* configENABLE_MPU */\n    secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,\n                                                                                       void * pvTaskHandle )\n#endif /* configENABLE_MPU */\n{\n    uint8_t * pucStackMemory = NULL;\n    uint8_t * pucStackLimit;\n    uint32_t ulIPSR, ulSecureContextIndex;\n    SecureContextHandle_t xSecureContextHandle = securecontextINVALID_CONTEXT_ID;\n\n    #if ( configENABLE_MPU == 1 )\n        uint32_t * pulCurrentStackPointer = NULL;\n    #endif /* configENABLE_MPU */\n\n    /* Read the Interrupt Program Status Register (IPSR) and Process Stack Limit\n     * Register (PSPLIM) value. */\n    secureportREAD_IPSR( ulIPSR );\n    secureportREAD_PSPLIM( pucStackLimit );\n\n    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\n     * when the processor is running in the Thread Mode.\n     * Also do nothing, if a secure context us already loaded. PSPLIM is set to\n     * securecontextNO_STACK when no secure context is loaded. */\n    if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) )\n    {\n        /* Ontain a free secure context. */\n        ulSecureContextIndex = ulGetSecureContext( pvTaskHandle );\n\n        /* Were we able to get a free context? */\n        if( ulSecureContextIndex < secureconfigMAX_SECURE_CONTEXTS )\n        {\n            /* Allocate the stack space. */\n            pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE );\n\n            if( pucStackMemory != NULL )\n            {\n                /* Since stack grows down, the starting point will be the last\n                 * location. Note that this location is next to the last\n                 * allocated byte for stack (excluding the space for seal values)\n                 * because the hardware decrements the stack pointer before\n                 * writing i.e. if stack pointer is 0x2, a push operation will\n                 * decrement the stack pointer to 0x1 and then write at 0x1. */\n                xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize;\n\n                /* Seal the created secure process stack. */\n                *( uint32_t * )( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE;\n                *( uint32_t * )( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE;\n\n                /* The stack cannot go beyond this location. This value is\n                 * programmed in the PSPLIM register on context switch.*/\n                xSecureContexts[ ulSecureContextIndex ].pucStackLimit = pucStackMemory;\n\n                xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle;\n\n                #if ( configENABLE_MPU == 1 )\n                    {\n                        /* Store the correct CONTROL value for the task on the stack.\n                         * This value is programmed in the CONTROL register on\n                         * context switch. */\n                        pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart;\n                        pulCurrentStackPointer--;\n\n                        if( ulIsTaskPrivileged )\n                        {\n                            *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;\n                        }\n                        else\n                        {\n                            *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;\n                        }\n\n                        /* Store the current stack pointer. This value is programmed in\n                         * the PSP register on context switch. */\n                        xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;\n                    }\n                #else /* configENABLE_MPU */\n                    {\n                        /* Current SP is set to the starting of the stack. This\n                         * value programmed in the PSP register on context switch. */\n                        xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart;\n                    }\n                #endif /* configENABLE_MPU */\n\n                /* Ensure to never return 0 as a valid context handle. */\n                xSecureContextHandle = ulSecureContextIndex + 1UL;\n            }\n        }\n    }\n\n    return xSecureContextHandle;\n}\n/*-----------------------------------------------------------*/\n\nsecureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )\n{\n    uint32_t ulIPSR, ulSecureContextIndex;\n\n    /* Read the Interrupt Program Status Register (IPSR) value. */\n    secureportREAD_IPSR( ulIPSR );\n\n    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\n     * when the processor is running in the Thread Mode. */\n    if( ulIPSR != 0 )\n    {\n        /* Only free if a valid context handle is passed. */\n        if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) )\n        {\n            ulSecureContextIndex = xSecureContextHandle - 1UL;\n\n            /* Ensure that the secure context being deleted is associated with\n             * the task. */\n            if( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle )\n            {\n                /* Free the stack space. */\n                vPortFree( xSecureContexts[ ulSecureContextIndex ].pucStackLimit );\n\n                /* Return the secure context back to the free secure contexts pool. */\n                vReturnSecureContext( ulSecureContextIndex );\n            }\n        }\n    }\n}\n/*-----------------------------------------------------------*/\n\nsecureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )\n{\n    uint8_t * pucStackLimit;\n    uint32_t ulSecureContextIndex;\n\n    if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) )\n    {\n        ulSecureContextIndex = xSecureContextHandle - 1UL;\n\n        secureportREAD_PSPLIM( pucStackLimit );\n\n        /* Ensure that no secure context is loaded and the task is loading it's\n         * own context. */\n        if( ( pucStackLimit == securecontextNO_STACK ) &&\n            ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) )\n        {\n            SecureContext_LoadContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) );\n        }\n    }\n}\n/*-----------------------------------------------------------*/\n\nsecureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )\n{\n    uint8_t * pucStackLimit;\n    uint32_t ulSecureContextIndex;\n\n    if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) )\n    {\n        ulSecureContextIndex = xSecureContextHandle - 1UL;\n\n        secureportREAD_PSPLIM( pucStackLimit );\n\n        /* Ensure that task's context is loaded and the task is saving it's own\n         * context. */\n        if( ( xSecureContexts[ ulSecureContextIndex ].pucStackLimit == pucStackLimit ) &&\n            ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) )\n        {\n            SecureContext_SaveContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) );\n        }\n    }\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM55/secure/secure_context.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef __SECURE_CONTEXT_H__\n#define __SECURE_CONTEXT_H__\n\n/* Standard includes. */\n#include <stdint.h>\n\n/* FreeRTOS includes. */\n#include \"FreeRTOSConfig.h\"\n\n/**\n * @brief PSP value when no secure context is loaded.\n */\n#define securecontextNO_STACK               0x0\n\n/**\n * @brief Invalid context ID.\n */\n#define securecontextINVALID_CONTEXT_ID     0UL\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Structure to represent a secure context.\n *\n * @note Since stack grows down, pucStackStart is the highest address while\n * pucStackLimit is the first address of the allocated memory.\n */\ntypedef struct SecureContext\n{\n    uint8_t * pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */\n    uint8_t * pucStackLimit;          /**< Last location of the stack memory (PSPLIM). */\n    uint8_t * pucStackStart;          /**< First location of the stack memory. */\n    void * pvTaskHandle;              /**< Task handle of the task this context is associated with. */\n} SecureContext_t;\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Opaque handle for a secure context.\n */\ntypedef uint32_t SecureContextHandle_t;\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Initializes the secure context management system.\n *\n * PSP is set to NULL and therefore a task must allocate and load a context\n * before calling any secure side function in the thread mode.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n */\nvoid SecureContext_Init( void );\n\n/**\n * @brief Allocates a context on the secure side.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n *\n * @param[in] ulSecureStackSize Size of the stack to allocate on secure side.\n * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise.\n *\n * @return Opaque context handle if context is successfully allocated, NULL\n * otherwise.\n */\n#if ( configENABLE_MPU == 1 )\n    SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,\n                                                         uint32_t ulIsTaskPrivileged,\n                                                         void * pvTaskHandle );\n#else /* configENABLE_MPU */\n    SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,\n                                                         void * pvTaskHandle );\n#endif /* configENABLE_MPU */\n\n/**\n * @brief Frees the given context.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n *\n * @param[in] xSecureContextHandle Context handle corresponding to the\n * context to be freed.\n */\nvoid SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );\n\n/**\n * @brief Loads the given context.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n *\n * @param[in] xSecureContextHandle Context handle corresponding to the context\n * to be loaded.\n */\nvoid SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );\n\n/**\n * @brief Saves the given context.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n *\n * @param[in] xSecureContextHandle Context handle corresponding to the context\n * to be saved.\n */\nvoid SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );\n\n#endif /* __SECURE_CONTEXT_H__ */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM55/secure/secure_context_port_asm.s",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n    SECTION .text:CODE:NOROOT(2)\n    THUMB\n\n/* Including FreeRTOSConfig.h here will cause build errors if the header file\ncontains code not understood by the assembler - for example the 'extern' keyword.\nTo avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so\nthe code is included in C files but excluded by the preprocessor in assembly\nfiles (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */\n#include \"FreeRTOSConfig.h\"\n\n    PUBLIC SecureContext_LoadContextAsm\n    PUBLIC SecureContext_SaveContextAsm\n/*-----------------------------------------------------------*/\n\nSecureContext_LoadContextAsm:\n    /* pxSecureContext value is in r0. */\n    mrs r1, ipsr                        /* r1 = IPSR. */\n    cbz r1, load_ctx_therad_mode        /* Do nothing if the processor is running in the Thread Mode. */\n    ldmia r0!, {r1, r2}                 /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */\n\n#if ( configENABLE_MPU == 1 )\n    ldmia r1!, {r3}                     /* Read CONTROL register value from task's stack. r3 = CONTROL. */\n    msr control, r3                     /* CONTROL = r3. */\n#endif /* configENABLE_MPU */\n\n    msr psplim, r2                      /* PSPLIM = r2. */\n    msr psp, r1                         /* PSP = r1. */\n\n    load_ctx_therad_mode:\n        bx lr\n/*-----------------------------------------------------------*/\n\nSecureContext_SaveContextAsm:\n    /* pxSecureContext value is in r0. */\n    mrs r1, ipsr                        /* r1 = IPSR. */\n    cbz r1, save_ctx_therad_mode        /* Do nothing if the processor is running in the Thread Mode. */\n    mrs r1, psp                         /* r1 = PSP. */\n\n#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )\n    vstmdb r1!, {s0}                    /* Trigger the deferred stacking of FPU registers. */\n    vldmia r1!, {s0}                    /* Nullify the effect of the previous statement. */\n#endif /* configENABLE_FPU || configENABLE_MVE */\n\n#if ( configENABLE_MPU == 1 )\n    mrs r2, control                     /* r2 = CONTROL. */\n    stmdb r1!, {r2}                     /* Store CONTROL value on the stack. */\n#endif /* configENABLE_MPU */\n\n    str r1, [r0]                        /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */\n    movs r1, #0                         /* r1 = securecontextNO_STACK. */\n    msr psplim, r1                      /* PSPLIM = securecontextNO_STACK. */\n    msr psp, r1                         /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */\n\n    save_ctx_therad_mode:\n        bx lr\n/*-----------------------------------------------------------*/\n\n    END\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM55/secure/secure_heap.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Standard includes. */\n#include <stdint.h>\n\n/* Secure context heap includes. */\n#include \"secure_heap.h\"\n\n/* Secure port macros. */\n#include \"secure_port_macros.h\"\n\n/**\n * @brief Total heap size.\n */\n#ifndef secureconfigTOTAL_HEAP_SIZE\n    #define secureconfigTOTAL_HEAP_SIZE    ( ( ( size_t ) ( 10 * 1024 ) ) )\n#endif\n\n/* No test marker by default. */\n#ifndef mtCOVERAGE_TEST_MARKER\n    #define mtCOVERAGE_TEST_MARKER()\n#endif\n\n/* No tracing by default. */\n#ifndef traceMALLOC\n    #define traceMALLOC( pvReturn, xWantedSize )\n#endif\n\n/* No tracing by default. */\n#ifndef traceFREE\n    #define traceFREE( pv, xBlockSize )\n#endif\n\n/* Block sizes must not get too small. */\n#define secureheapMINIMUM_BLOCK_SIZE    ( ( size_t ) ( xHeapStructSize << 1 ) )\n\n/* Assumes 8bit bytes! */\n#define secureheapBITS_PER_BYTE         ( ( size_t ) 8 )\n/*-----------------------------------------------------------*/\n\n/* Allocate the memory for the heap. */\n#if ( configAPPLICATION_ALLOCATED_HEAP == 1 )\n\n/* The application writer has already defined the array used for the RTOS\n* heap - probably so it can be placed in a special segment or address. */\n    extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];\n#else /* configAPPLICATION_ALLOCATED_HEAP */\n    static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];\n#endif /* configAPPLICATION_ALLOCATED_HEAP */\n\n/**\n * @brief The linked list structure.\n *\n * This is used to link free blocks in order of their memory address.\n */\ntypedef struct A_BLOCK_LINK\n{\n    struct A_BLOCK_LINK * pxNextFreeBlock; /**< The next free block in the list. */\n    size_t xBlockSize;                     /**< The size of the free block. */\n} BlockLink_t;\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Called automatically to setup the required heap structures the first\n * time pvPortMalloc() is called.\n */\nstatic void prvHeapInit( void );\n\n/**\n * @brief Inserts a block of memory that is being freed into the correct\n * position in the list of free memory blocks.\n *\n * The block being freed will be merged with the block in front it and/or the\n * block behind it if the memory blocks are adjacent to each other.\n *\n * @param[in] pxBlockToInsert The block being freed.\n */\nstatic void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert );\n/*-----------------------------------------------------------*/\n\n/**\n * @brief The size of the structure placed at the beginning of each allocated\n * memory block must by correctly byte aligned.\n */\nstatic const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );\n\n/**\n * @brief Create a couple of list links to mark the start and end of the list.\n */\nstatic BlockLink_t xStart;\nstatic BlockLink_t * pxEnd = NULL;\n\n/**\n * @brief Keeps track of the number of free bytes remaining, but says nothing\n * about fragmentation.\n */\nstatic size_t xFreeBytesRemaining = 0U;\nstatic size_t xMinimumEverFreeBytesRemaining = 0U;\n\n/**\n * @brief Gets set to the top bit of an size_t type.\n *\n * When this bit in the xBlockSize member of an BlockLink_t structure is set\n * then the block belongs to the application. When the bit is free the block is\n * still part of the free heap space.\n */\nstatic size_t xBlockAllocatedBit = 0;\n/*-----------------------------------------------------------*/\n\nstatic void prvHeapInit( void )\n{\n    BlockLink_t * pxFirstFreeBlock;\n    uint8_t * pucAlignedHeap;\n    size_t uxAddress;\n    size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE;\n\n    /* Ensure the heap starts on a correctly aligned boundary. */\n    uxAddress = ( size_t ) ucHeap;\n\n    if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 )\n    {\n        uxAddress += ( secureportBYTE_ALIGNMENT - 1 );\n        uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );\n        xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;\n    }\n\n    pucAlignedHeap = ( uint8_t * ) uxAddress;\n\n    /* xStart is used to hold a pointer to the first item in the list of free\n     * blocks.  The void cast is used to prevent compiler warnings. */\n    xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;\n    xStart.xBlockSize = ( size_t ) 0;\n\n    /* pxEnd is used to mark the end of the list of free blocks and is inserted\n     * at the end of the heap space. */\n    uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;\n    uxAddress -= xHeapStructSize;\n    uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );\n    pxEnd = ( void * ) uxAddress;\n    pxEnd->xBlockSize = 0;\n    pxEnd->pxNextFreeBlock = NULL;\n\n    /* To start with there is a single free block that is sized to take up the\n     * entire heap space, minus the space taken by pxEnd. */\n    pxFirstFreeBlock = ( void * ) pucAlignedHeap;\n    pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;\n    pxFirstFreeBlock->pxNextFreeBlock = pxEnd;\n\n    /* Only one block exists - and it covers the entire usable heap space. */\n    xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;\n    xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;\n\n    /* Work out the position of the top bit in a size_t variable. */\n    xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert )\n{\n    BlockLink_t * pxIterator;\n    uint8_t * puc;\n\n    /* Iterate through the list until a block is found that has a higher address\n     * than the block being inserted. */\n    for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )\n    {\n        /* Nothing to do here, just iterate to the right position. */\n    }\n\n    /* Do the block being inserted, and the block it is being inserted after\n     * make a contiguous block of memory? */\n    puc = ( uint8_t * ) pxIterator;\n\n    if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )\n    {\n        pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;\n        pxBlockToInsert = pxIterator;\n    }\n    else\n    {\n        mtCOVERAGE_TEST_MARKER();\n    }\n\n    /* Do the block being inserted, and the block it is being inserted before\n     * make a contiguous block of memory? */\n    puc = ( uint8_t * ) pxBlockToInsert;\n\n    if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )\n    {\n        if( pxIterator->pxNextFreeBlock != pxEnd )\n        {\n            /* Form one big block from the two blocks. */\n            pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;\n            pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;\n        }\n        else\n        {\n            pxBlockToInsert->pxNextFreeBlock = pxEnd;\n        }\n    }\n    else\n    {\n        pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;\n    }\n\n    /* If the block being inserted plugged a gab, so was merged with the block\n     * before and the block after, then it's pxNextFreeBlock pointer will have\n     * already been set, and should not be set here as that would make it point\n     * to itself. */\n    if( pxIterator != pxBlockToInsert )\n    {\n        pxIterator->pxNextFreeBlock = pxBlockToInsert;\n    }\n    else\n    {\n        mtCOVERAGE_TEST_MARKER();\n    }\n}\n/*-----------------------------------------------------------*/\n\nvoid * pvPortMalloc( size_t xWantedSize )\n{\n    BlockLink_t * pxBlock;\n    BlockLink_t * pxPreviousBlock;\n    BlockLink_t * pxNewBlockLink;\n    void * pvReturn = NULL;\n\n    /* If this is the first call to malloc then the heap will require\n     * initialisation to setup the list of free blocks. */\n    if( pxEnd == NULL )\n    {\n        prvHeapInit();\n    }\n    else\n    {\n        mtCOVERAGE_TEST_MARKER();\n    }\n\n    /* Check the requested block size is not so large that the top bit is set.\n     * The top bit of the block size member of the BlockLink_t structure is used\n     * to determine who owns the block - the application or the kernel, so it\n     * must be free. */\n    if( ( xWantedSize & xBlockAllocatedBit ) == 0 )\n    {\n        /* The wanted size is increased so it can contain a BlockLink_t\n         * structure in addition to the requested amount of bytes. */\n        if( xWantedSize > 0 )\n        {\n            xWantedSize += xHeapStructSize;\n\n            /* Ensure that blocks are always aligned to the required number of\n             * bytes. */\n            if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )\n            {\n                /* Byte alignment required. */\n                xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );\n                secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n\n        if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )\n        {\n            /* Traverse the list from the start (lowest address) block until\n             * one of adequate size is found. */\n            pxPreviousBlock = &xStart;\n            pxBlock = xStart.pxNextFreeBlock;\n\n            while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )\n            {\n                pxPreviousBlock = pxBlock;\n                pxBlock = pxBlock->pxNextFreeBlock;\n            }\n\n            /* If the end marker was reached then a block of adequate size was\n             * not found. */\n            if( pxBlock != pxEnd )\n            {\n                /* Return the memory space pointed to - jumping over the\n                 * BlockLink_t structure at its start. */\n                pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );\n\n                /* This block is being returned for use so must be taken out\n                 * of the list of free blocks. */\n                pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;\n\n                /* If the block is larger than required it can be split into\n                 * two. */\n                if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE )\n                {\n                    /* This block is to be split into two.  Create a new\n                     * block following the number of bytes requested. The void\n                     * cast is used to prevent byte alignment warnings from the\n                     * compiler. */\n                    pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );\n                    secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 );\n\n                    /* Calculate the sizes of two blocks split from the single\n                     * block. */\n                    pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;\n                    pxBlock->xBlockSize = xWantedSize;\n\n                    /* Insert the new block into the list of free blocks. */\n                    prvInsertBlockIntoFreeList( pxNewBlockLink );\n                }\n                else\n                {\n                    mtCOVERAGE_TEST_MARKER();\n                }\n\n                xFreeBytesRemaining -= pxBlock->xBlockSize;\n\n                if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )\n                {\n                    xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;\n                }\n                else\n                {\n                    mtCOVERAGE_TEST_MARKER();\n                }\n\n                /* The block is being returned - it is allocated and owned by\n                 * the application and has no \"next\" block. */\n                pxBlock->xBlockSize |= xBlockAllocatedBit;\n                pxBlock->pxNextFreeBlock = NULL;\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n    }\n    else\n    {\n        mtCOVERAGE_TEST_MARKER();\n    }\n\n    traceMALLOC( pvReturn, xWantedSize );\n\n    #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )\n        {\n            if( pvReturn == NULL )\n            {\n                extern void vApplicationMallocFailedHook( void );\n                vApplicationMallocFailedHook();\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n    #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */\n\n    secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );\n    return pvReturn;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortFree( void * pv )\n{\n    uint8_t * puc = ( uint8_t * ) pv;\n    BlockLink_t * pxLink;\n\n    if( pv != NULL )\n    {\n        /* The memory being freed will have an BlockLink_t structure immediately\n         * before it. */\n        puc -= xHeapStructSize;\n\n        /* This casting is to keep the compiler from issuing warnings. */\n        pxLink = ( void * ) puc;\n\n        /* Check the block is actually allocated. */\n        secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );\n        secureportASSERT( pxLink->pxNextFreeBlock == NULL );\n\n        if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )\n        {\n            if( pxLink->pxNextFreeBlock == NULL )\n            {\n                /* The block is being returned to the heap - it is no longer\n                 * allocated. */\n                pxLink->xBlockSize &= ~xBlockAllocatedBit;\n\n                secureportDISABLE_NON_SECURE_INTERRUPTS();\n                {\n                    /* Add this block to the list of free blocks. */\n                    xFreeBytesRemaining += pxLink->xBlockSize;\n                    traceFREE( pv, pxLink->xBlockSize );\n                    prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );\n                }\n                secureportENABLE_NON_SECURE_INTERRUPTS();\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n    }\n}\n/*-----------------------------------------------------------*/\n\nsize_t xPortGetFreeHeapSize( void )\n{\n    return xFreeBytesRemaining;\n}\n/*-----------------------------------------------------------*/\n\nsize_t xPortGetMinimumEverFreeHeapSize( void )\n{\n    return xMinimumEverFreeBytesRemaining;\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM55/secure/secure_heap.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef __SECURE_HEAP_H__\n#define __SECURE_HEAP_H__\n\n/* Standard includes. */\n#include <stdlib.h>\n\n/**\n * @brief Allocates memory from heap.\n *\n * @param[in] xWantedSize The size of the memory to be allocated.\n *\n * @return Pointer to the memory region if the allocation is successful, NULL\n * otherwise.\n */\nvoid * pvPortMalloc( size_t xWantedSize );\n\n/**\n * @brief Frees the previously allocated memory.\n *\n * @param[in] pv Pointer to the memory to be freed.\n */\nvoid vPortFree( void * pv );\n\n/**\n * @brief Get the free heap size.\n *\n * @return Free heap size.\n */\nsize_t xPortGetFreeHeapSize( void );\n\n/**\n * @brief Get the minimum ever free heap size.\n *\n * @return Minimum ever free heap size.\n */\nsize_t xPortGetMinimumEverFreeHeapSize( void );\n\n#endif /* __SECURE_HEAP_H__ */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM55/secure/secure_init.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Standard includes. */\n#include <stdint.h>\n\n/* Secure init includes. */\n#include \"secure_init.h\"\n\n/* Secure port macros. */\n#include \"secure_port_macros.h\"\n\n/**\n * @brief Constants required to manipulate the SCB.\n */\n#define secureinitSCB_AIRCR                 ( ( volatile uint32_t * ) 0xe000ed0c )  /* Application Interrupt and Reset Control Register. */\n#define secureinitSCB_AIRCR_VECTKEY_POS     ( 16UL )\n#define secureinitSCB_AIRCR_VECTKEY_MASK    ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )\n#define secureinitSCB_AIRCR_PRIS_POS        ( 14UL )\n#define secureinitSCB_AIRCR_PRIS_MASK       ( 1UL << secureinitSCB_AIRCR_PRIS_POS )\n\n/**\n * @brief Constants required to manipulate the FPU.\n */\n#define secureinitFPCCR                     ( ( volatile uint32_t * ) 0xe000ef34 )  /* Floating Point Context Control Register. */\n#define secureinitFPCCR_LSPENS_POS          ( 29UL )\n#define secureinitFPCCR_LSPENS_MASK         ( 1UL << secureinitFPCCR_LSPENS_POS )\n#define secureinitFPCCR_TS_POS              ( 26UL )\n#define secureinitFPCCR_TS_MASK             ( 1UL << secureinitFPCCR_TS_POS )\n\n#define secureinitNSACR                     ( ( volatile uint32_t * ) 0xe000ed8c )  /* Non-secure Access Control Register. */\n#define secureinitNSACR_CP10_POS            ( 10UL )\n#define secureinitNSACR_CP10_MASK           ( 1UL << secureinitNSACR_CP10_POS )\n#define secureinitNSACR_CP11_POS            ( 11UL )\n#define secureinitNSACR_CP11_MASK           ( 1UL << secureinitNSACR_CP11_POS )\n/*-----------------------------------------------------------*/\n\nsecureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void )\n{\n    uint32_t ulIPSR;\n\n    /* Read the Interrupt Program Status Register (IPSR) value. */\n    secureportREAD_IPSR( ulIPSR );\n\n    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\n     * when the processor is running in the Thread Mode. */\n    if( ulIPSR != 0 )\n    {\n        *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |\n                                   ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |\n                                   ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK );\n    }\n}\n/*-----------------------------------------------------------*/\n\nsecureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )\n{\n    uint32_t ulIPSR;\n\n    /* Read the Interrupt Program Status Register (IPSR) value. */\n    secureportREAD_IPSR( ulIPSR );\n\n    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\n     * when the processor is running in the Thread Mode. */\n    if( ulIPSR != 0 )\n    {\n        /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is\n         * permitted. CP11 should be programmed to the same value as CP10. */\n        *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );\n\n        /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures\n         * that we can enable/disable lazy stacking in port.c file. */\n        *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK );\n\n        /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP\n         * registers (S16-S31) are also pushed to stack on exception entry and\n         * restored on exception return. */\n        *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );\n    }\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM55/secure/secure_init.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef __SECURE_INIT_H__\n#define __SECURE_INIT_H__\n\n/**\n * @brief De-prioritizes the non-secure exceptions.\n *\n * This is needed to ensure that the non-secure PendSV runs at the lowest\n * priority. Context switch is done in the non-secure PendSV handler.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n */\nvoid SecureInit_DePrioritizeNSExceptions( void );\n\n/**\n * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access.\n *\n * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point\n * Registers are not leaked to the non-secure side.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n */\nvoid SecureInit_EnableNSFPUAccess( void );\n\n#endif /* __SECURE_INIT_H__ */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM55/secure/secure_port_macros.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef __SECURE_PORT_MACROS_H__\n#define __SECURE_PORT_MACROS_H__\n\n/**\n * @brief Byte alignment requirements.\n */\n#define secureportBYTE_ALIGNMENT         8\n#define secureportBYTE_ALIGNMENT_MASK    ( 0x0007 )\n\n/**\n * @brief Macro to declare a function as non-secure callable.\n */\n#if defined( __IAR_SYSTEMS_ICC__ )\n    #define secureportNON_SECURE_CALLABLE    __cmse_nonsecure_entry __root\n#else\n    #define secureportNON_SECURE_CALLABLE    __attribute__( ( cmse_nonsecure_entry ) ) __attribute__( ( used ) )\n#endif\n\n/**\n * @brief Set the secure PRIMASK value.\n */\n#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \\\n    __asm volatile ( \"msr primask, %0\" : : \"r\" ( ulPrimaskValue ) : \"memory\" )\n\n/**\n * @brief Set the non-secure PRIMASK value.\n */\n#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \\\n    __asm volatile ( \"msr primask_ns, %0\" : : \"r\" ( ulPrimaskValue ) : \"memory\" )\n\n/**\n * @brief Read the PSP value in the given variable.\n */\n#define secureportREAD_PSP( pucOutCurrentStackPointer ) \\\n    __asm volatile ( \"mrs %0, psp\"  : \"=r\" ( pucOutCurrentStackPointer ) )\n\n/**\n * @brief Set the PSP to the given value.\n */\n#define secureportSET_PSP( pucCurrentStackPointer ) \\\n    __asm volatile ( \"msr psp, %0\" : : \"r\" ( pucCurrentStackPointer ) )\n\n/**\n * @brief Read the PSPLIM value in the given variable.\n */\n#define secureportREAD_PSPLIM( pucOutStackLimit ) \\\n    __asm volatile ( \"mrs %0, psplim\"  : \"=r\" ( pucOutStackLimit ) )\n\n/**\n * @brief Set the PSPLIM to the given value.\n */\n#define secureportSET_PSPLIM( pucStackLimit ) \\\n    __asm volatile ( \"msr psplim, %0\" : : \"r\" ( pucStackLimit ) )\n\n/**\n * @brief Set the NonSecure MSP to the given value.\n */\n#define secureportSET_MSP_NS( pucMainStackPointer ) \\\n    __asm volatile ( \"msr msp_ns, %0\" : : \"r\" ( pucMainStackPointer ) )\n\n/**\n * @brief Set the CONTROL register to the given value.\n */\n#define secureportSET_CONTROL( ulControl ) \\\n    __asm volatile ( \"msr control, %0\" : : \"r\" ( ulControl ) : \"memory\" )\n\n/**\n * @brief Read the Interrupt Program Status Register (IPSR) value in the given\n * variable.\n */\n#define secureportREAD_IPSR( ulIPSR ) \\\n    __asm volatile ( \"mrs %0, ipsr\"  : \"=r\" ( ulIPSR ) )\n\n/**\n * @brief PRIMASK value to enable interrupts.\n */\n#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL     0\n\n/**\n * @brief PRIMASK value to disable interrupts.\n */\n#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL    1\n\n/**\n * @brief Disable secure interrupts.\n */\n#define secureportDISABLE_SECURE_INTERRUPTS()        secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )\n\n/**\n * @brief Disable non-secure interrupts.\n *\n * This effectively disables context switches.\n */\n#define secureportDISABLE_NON_SECURE_INTERRUPTS()    secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )\n\n/**\n * @brief Enable non-secure interrupts.\n */\n#define secureportENABLE_NON_SECURE_INTERRUPTS()     secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL )\n\n/**\n * @brief Assert definition.\n */\n#define secureportASSERT( x )                      \\\n    if( ( x ) == 0 )                               \\\n    {                                              \\\n        secureportDISABLE_SECURE_INTERRUPTS();     \\\n        secureportDISABLE_NON_SECURE_INTERRUPTS(); \\\n        for( ; ; ) {; }                            \\\n    }\n\n#endif /* __SECURE_PORT_MACROS_H__ */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM55_NTZ/non_secure/port.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\n * all the API functions to use the MPU wrappers. That should only be done when\n * task.h is included from an application file. */\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n/* MPU wrappers includes. */\n#include \"mpu_wrappers.h\"\n\n/* Portasm includes. */\n#include \"portasm.h\"\n\n#if ( configENABLE_TRUSTZONE == 1 )\n    /* Secure components includes. */\n    #include \"secure_context.h\"\n    #include \"secure_init.h\"\n#endif /* configENABLE_TRUSTZONE */\n\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/**\n * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only\n * i.e. the processor boots as secure and never jumps to the non-secure side.\n * The Trust Zone support in the port must be disabled in order to run FreeRTOS\n * on the secure side. The following are the valid configuration seetings:\n *\n * 1. Run FreeRTOS on the Secure Side:\n *    configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0\n *\n * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:\n *    configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1\n *\n * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:\n *    configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0\n */\n#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )\n    #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.\n#endif\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the NVIC.\n */\n#define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )\n#define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )\n#define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )\n#define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )\n#define portNVIC_SYSTICK_ENABLE_BIT           ( 1UL << 0UL )\n#define portNVIC_SYSTICK_INT_BIT              ( 1UL << 1UL )\n#define portNVIC_SYSTICK_CLK_BIT              ( 1UL << 2UL )\n#define portNVIC_SYSTICK_COUNT_FLAG_BIT       ( 1UL << 16UL )\n#define portNVIC_PEND_SYSTICK_CLEAR_BIT       ( 1UL << 25UL )\n#define portNVIC_PEND_SYSTICK_SET_BIT         ( 1UL << 26UL )\n#define portMIN_INTERRUPT_PRIORITY            ( 255UL )\n#define portNVIC_PENDSV_PRI                   ( portMIN_INTERRUPT_PRIORITY << 16UL )\n#define portNVIC_SYSTICK_PRI                  ( portMIN_INTERRUPT_PRIORITY << 24UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the SCB.\n */\n#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( volatile uint32_t * ) 0xe000ed24 )\n#define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the FPU.\n */\n#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 )              /* Coprocessor Access Control Register. */\n#define portCPACR_CP10_VALUE    ( 3UL )\n#define portCPACR_CP11_VALUE    portCPACR_CP10_VALUE\n#define portCPACR_CP10_POS      ( 20UL )\n#define portCPACR_CP11_POS      ( 22UL )\n\n#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 )              /* Floating Point Context Control Register. */\n#define portFPCCR_ASPEN_POS     ( 31UL )\n#define portFPCCR_ASPEN_MASK    ( 1UL << portFPCCR_ASPEN_POS )\n#define portFPCCR_LSPEN_POS     ( 30UL )\n#define portFPCCR_LSPEN_MASK    ( 1UL << portFPCCR_LSPEN_POS )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the MPU.\n */\n#define portMPU_TYPE_REG                      ( *( ( volatile uint32_t * ) 0xe000ed90 ) )\n#define portMPU_CTRL_REG                      ( *( ( volatile uint32_t * ) 0xe000ed94 ) )\n#define portMPU_RNR_REG                       ( *( ( volatile uint32_t * ) 0xe000ed98 ) )\n\n#define portMPU_RBAR_REG                      ( *( ( volatile uint32_t * ) 0xe000ed9c ) )\n#define portMPU_RLAR_REG                      ( *( ( volatile uint32_t * ) 0xe000eda0 ) )\n\n#define portMPU_RBAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda4 ) )\n#define portMPU_RLAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda8 ) )\n\n#define portMPU_RBAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edac ) )\n#define portMPU_RLAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edb0 ) )\n\n#define portMPU_RBAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb4 ) )\n#define portMPU_RLAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb8 ) )\n\n#define portMPU_MAIR0_REG                     ( *( ( volatile uint32_t * ) 0xe000edc0 ) )\n#define portMPU_MAIR1_REG                     ( *( ( volatile uint32_t * ) 0xe000edc4 ) )\n\n#define portMPU_RBAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */\n#define portMPU_RLAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */\n\n#define portMPU_MAIR_ATTR0_POS                ( 0UL )\n#define portMPU_MAIR_ATTR0_MASK               ( 0x000000ff )\n\n#define portMPU_MAIR_ATTR1_POS                ( 8UL )\n#define portMPU_MAIR_ATTR1_MASK               ( 0x0000ff00 )\n\n#define portMPU_MAIR_ATTR2_POS                ( 16UL )\n#define portMPU_MAIR_ATTR2_MASK               ( 0x00ff0000 )\n\n#define portMPU_MAIR_ATTR3_POS                ( 24UL )\n#define portMPU_MAIR_ATTR3_MASK               ( 0xff000000 )\n\n#define portMPU_MAIR_ATTR4_POS                ( 0UL )\n#define portMPU_MAIR_ATTR4_MASK               ( 0x000000ff )\n\n#define portMPU_MAIR_ATTR5_POS                ( 8UL )\n#define portMPU_MAIR_ATTR5_MASK               ( 0x0000ff00 )\n\n#define portMPU_MAIR_ATTR6_POS                ( 16UL )\n#define portMPU_MAIR_ATTR6_MASK               ( 0x00ff0000 )\n\n#define portMPU_MAIR_ATTR7_POS                ( 24UL )\n#define portMPU_MAIR_ATTR7_MASK               ( 0xff000000 )\n\n#define portMPU_RLAR_ATTR_INDEX0              ( 0UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX1              ( 1UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX2              ( 2UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX3              ( 3UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX4              ( 4UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX5              ( 5UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX6              ( 6UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX7              ( 7UL << 1UL )\n\n#define portMPU_RLAR_REGION_ENABLE            ( 1UL )\n\n/* Enable privileged access to unmapped region. */\n#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )\n\n/* Enable MPU. */\n#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )\n\n/* Expected value of the portMPU_TYPE register. */\n#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief The maximum 24-bit number.\n *\n * It is needed because the systick is a 24-bit counter.\n */\n#define portMAX_24_BIT_NUMBER       ( 0xffffffUL )\n\n/**\n * @brief A fiddle factor to estimate the number of SysTick counts that would\n * have occurred while the SysTick counter is stopped during tickless idle\n * calculations.\n */\n#define portMISSED_COUNTS_FACTOR    ( 94UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to set up the initial stack.\n */\n#define portINITIAL_XPSR    ( 0x01000000 )\n\n#if ( configRUN_FREERTOS_SECURE_ONLY == 1 )\n\n/**\n * @brief Initial EXC_RETURN value.\n *\n *     FF         FF         FF         FD\n * 1111 1111  1111 1111  1111 1111  1111 1101\n *\n * Bit[6] - 1 --> The exception was taken from the Secure state.\n * Bit[5] - 1 --> Do not skip stacking of additional state context.\n * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\n * Bit[3] - 1 --> Return to the Thread mode.\n * Bit[2] - 1 --> Restore registers from the process stack.\n * Bit[1] - 0 --> Reserved, 0.\n * Bit[0] - 1 --> The exception was taken to the Secure state.\n */\n    #define portINITIAL_EXC_RETURN    ( 0xfffffffd )\n#else\n\n/**\n * @brief Initial EXC_RETURN value.\n *\n *     FF         FF         FF         BC\n * 1111 1111  1111 1111  1111 1111  1011 1100\n *\n * Bit[6] - 0 --> The exception was taken from the Non-Secure state.\n * Bit[5] - 1 --> Do not skip stacking of additional state context.\n * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\n * Bit[3] - 1 --> Return to the Thread mode.\n * Bit[2] - 1 --> Restore registers from the process stack.\n * Bit[1] - 0 --> Reserved, 0.\n * Bit[0] - 0 --> The exception was taken to the Non-Secure state.\n */\n    #define portINITIAL_EXC_RETURN    ( 0xffffffbc )\n#endif /* configRUN_FREERTOS_SECURE_ONLY */\n\n/**\n * @brief CONTROL register privileged bit mask.\n *\n * Bit[0] in CONTROL register tells the privilege:\n *  Bit[0] = 0 ==> The task is privileged.\n *  Bit[0] = 1 ==> The task is not privileged.\n */\n#define portCONTROL_PRIVILEGED_MASK         ( 1UL << 0UL )\n\n/**\n * @brief Initial CONTROL register values.\n */\n#define portINITIAL_CONTROL_UNPRIVILEGED    ( 0x3 )\n#define portINITIAL_CONTROL_PRIVILEGED      ( 0x2 )\n\n/**\n * @brief Let the user override the default SysTick clock rate.  If defined by the\n * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the\n * configuration register.\n */\n#ifndef configSYSTICK_CLOCK_HZ\n    #define configSYSTICK_CLOCK_HZ             ( configCPU_CLOCK_HZ )\n    /* Ensure the SysTick is clocked at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( portNVIC_SYSTICK_CLK_BIT )\n#else\n    /* Select the option to clock SysTick not at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( 0 )\n#endif\n\n/**\n * @brief Let the user override the pre-loading of the initial LR with the\n * address of prvTaskExitError() in case it messes up unwinding of the stack\n * in the debugger.\n */\n#ifdef configTASK_RETURN_ADDRESS\n    #define portTASK_RETURN_ADDRESS    configTASK_RETURN_ADDRESS\n#else\n    #define portTASK_RETURN_ADDRESS    prvTaskExitError\n#endif\n\n/**\n * @brief If portPRELOAD_REGISTERS then registers will be given an initial value\n * when a task is created. This helps in debugging at the cost of code size.\n */\n#define portPRELOAD_REGISTERS    1\n\n/**\n * @brief A task is created without a secure context, and must call\n * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes\n * any secure calls.\n */\n#define portNO_SECURE_CONTEXT    0\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Used to catch tasks that attempt to return from their implementing\n * function.\n */\nstatic void prvTaskExitError( void );\n\n#if ( configENABLE_MPU == 1 )\n\n/**\n * @brief Setup the Memory Protection Unit (MPU).\n */\n    static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\n#endif /* configENABLE_MPU */\n\n#if ( configENABLE_FPU == 1 )\n\n/**\n * @brief Setup the Floating Point Unit (FPU).\n */\n    static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;\n#endif /* configENABLE_FPU */\n\n/**\n * @brief Setup the timer to generate the tick interrupts.\n *\n * The implementation in this file is weak to allow application writers to\n * change the timer used to generate the tick interrupt.\n */\nvoid vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Checks whether the current execution context is interrupt.\n *\n * @return pdTRUE if the current execution context is interrupt, pdFALSE\n * otherwise.\n */\nBaseType_t xPortIsInsideInterrupt( void );\n\n/**\n * @brief Yield the processor.\n */\nvoid vPortYield( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Enter critical section.\n */\nvoid vPortEnterCritical( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Exit from critical section.\n */\nvoid vPortExitCritical( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief SysTick handler.\n */\nvoid SysTick_Handler( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief C part of SVC handler.\n */\nportDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION;\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Each task maintains its own interrupt status in the critical nesting\n * variable.\n */\nPRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;\n\n#if ( configENABLE_TRUSTZONE == 1 )\n\n/**\n * @brief Saved as part of the task context to indicate which context the\n * task is using on the secure side.\n */\n    PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;\n#endif /* configENABLE_TRUSTZONE */\n\n#if ( configUSE_TICKLESS_IDLE == 1 )\n\n/**\n * @brief The number of SysTick increments that make up one tick period.\n */\n    PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0;\n\n/**\n * @brief The maximum number of tick periods that can be suppressed is\n * limited by the 24 bit resolution of the SysTick timer.\n */\n    PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0;\n\n/**\n * @brief Compensate for the CPU cycles that pass while the SysTick is\n * stopped (low power functionality only).\n */\n    PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TICKLESS_IDLE == 1 )\n    __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )\n    {\n        uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;\n        TickType_t xModifiableIdleTime;\n\n        /* Make sure the SysTick reload value does not overflow the counter. */\n        if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\n        {\n            xExpectedIdleTime = xMaximumPossibleSuppressedTicks;\n        }\n\n        /* Enter a critical section but don't use the taskENTER_CRITICAL()\n         * method as that will mask interrupts that should exit sleep mode. */\n        __asm volatile ( \"cpsid i\" ::: \"memory\" );\n        __asm volatile ( \"dsb\" );\n        __asm volatile ( \"isb\" );\n\n        /* If a context switch is pending or a task is waiting for the scheduler\n         * to be unsuspended then abandon the low power entry. */\n        if( eTaskConfirmSleepModeStatus() == eAbortSleep )\n        {\n            /* Re-enable interrupts - see comments above the cpsid instruction\n             * above. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n        }\n        else\n        {\n            /* Stop the SysTick momentarily.  The time the SysTick is stopped for\n             * is accounted for as best it can be, but using the tickless mode will\n             * inevitably result in some tiny drift of the time maintained by the\n             * kernel with respect to calendar time. */\n            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );\n\n            /* Use the SysTick current-value register to determine the number of\n             * SysTick decrements remaining until the next tick interrupt.  If the\n             * current-value register is zero, then there are actually\n             * ulTimerCountsForOneTick decrements remaining, not zero, because the\n             * SysTick requests the interrupt when decrementing from 1 to 0. */\n            ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n\n            if( ulSysTickDecrementsLeft == 0 )\n            {\n                ulSysTickDecrementsLeft = ulTimerCountsForOneTick;\n            }\n\n            /* Calculate the reload value required to wait xExpectedIdleTime\n             * tick periods.  -1 is used because this code normally executes part\n             * way through the first tick period.  But if the SysTick IRQ is now\n             * pending, then clear the IRQ, suppressing the first tick, and correct\n             * the reload value to reflect that the second tick period is already\n             * underway.  The expected idle time is always at least two ticks. */\n            ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );\n\n            if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )\n            {\n                portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;\n                ulReloadValue -= ulTimerCountsForOneTick;\n            }\n\n            if( ulReloadValue > ulStoppedTimerCompensation )\n            {\n                ulReloadValue -= ulStoppedTimerCompensation;\n            }\n\n            /* Set the new reload value. */\n            portNVIC_SYSTICK_LOAD_REG = ulReloadValue;\n\n            /* Clear the SysTick count flag and set the count value back to\n             * zero. */\n            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n            /* Restart SysTick. */\n            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\n\n            /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can\n             * set its parameter to 0 to indicate that its implementation contains\n             * its own wait for interrupt or wait for event instruction, and so wfi\n             * should not be executed again.  However, the original expected idle\n             * time variable must remain unmodified, so a copy is taken. */\n            xModifiableIdleTime = xExpectedIdleTime;\n            configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\n\n            if( xModifiableIdleTime > 0 )\n            {\n                __asm volatile ( \"dsb\" ::: \"memory\" );\n                __asm volatile ( \"wfi\" );\n                __asm volatile ( \"isb\" );\n            }\n\n            configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\n\n            /* Re-enable interrupts to allow the interrupt that brought the MCU\n             * out of sleep mode to execute immediately.  See comments above\n             * the cpsid instruction above. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n            __asm volatile ( \"dsb\" );\n            __asm volatile ( \"isb\" );\n\n            /* Disable interrupts again because the clock is about to be stopped\n             * and interrupts that execute while the clock is stopped will increase\n             * any slippage between the time maintained by the RTOS and calendar\n             * time. */\n            __asm volatile ( \"cpsid i\" ::: \"memory\" );\n            __asm volatile ( \"dsb\" );\n            __asm volatile ( \"isb\" );\n\n            /* Disable the SysTick clock without reading the\n             * portNVIC_SYSTICK_CTRL_REG register to ensure the\n             * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,\n             * the time the SysTick is stopped for is accounted for as best it can\n             * be, but using the tickless mode will inevitably result in some tiny\n             * drift of the time maintained by the kernel with respect to calendar\n             * time*/\n            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );\n\n            /* Determine whether the SysTick has already counted to zero. */\n            if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n            {\n                uint32_t ulCalculatedLoadValue;\n\n                /* The tick interrupt ended the sleep (or is now pending), and\n                 * a new tick period has started.  Reset portNVIC_SYSTICK_LOAD_REG\n                 * with whatever remains of the new tick period. */\n                ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\n\n                /* Don't allow a tiny value, or values that have somehow\n                 * underflowed because the post sleep hook did something\n                 * that took too long or because the SysTick current-value register\n                 * is zero. */\n                if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )\n                {\n                    ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );\n                }\n\n                portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;\n\n                /* As the pending tick will be processed as soon as this\n                 * function exits, the tick value maintained by the tick is stepped\n                 * forward by one less than the time spent waiting. */\n                ulCompleteTickPeriods = xExpectedIdleTime - 1UL;\n            }\n            else\n            {\n                /* Something other than the tick interrupt ended the sleep. */\n\n                /* Use the SysTick current-value register to determine the\n                 * number of SysTick decrements remaining until the expected idle\n                 * time would have ended. */\n                ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n                #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )\n                {\n                    /* If the SysTick is not using the core clock, the current-\n                     * value register might still be zero here.  In that case, the\n                     * SysTick didn't load from the reload register, and there are\n                     * ulReloadValue decrements remaining in the expected idle\n                     * time, not zero. */\n                    if( ulSysTickDecrementsLeft == 0 )\n                    {\n                        ulSysTickDecrementsLeft = ulReloadValue;\n                    }\n                }\n                #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */\n\n                /* Work out how long the sleep lasted rounded to complete tick\n                 * periods (not the ulReload value which accounted for part\n                 * ticks). */\n                ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;\n\n                /* How many complete tick periods passed while the processor\n                 * was waiting? */\n                ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;\n\n                /* The reload value is set to whatever fraction of a single tick\n                 * period remains. */\n                portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;\n            }\n\n            /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,\n             * then set portNVIC_SYSTICK_LOAD_REG back to its standard value.  If\n             * the SysTick is not using the core clock, temporarily configure it to\n             * use the core clock.  This configuration forces the SysTick to load\n             * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next\n             * cycle of the other clock.  Then portNVIC_SYSTICK_LOAD_REG is ready\n             * to receive the standard value immediately. */\n            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n            portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n            #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )\n            {\n                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n            }\n            #else\n            {\n                /* The temporary usage of the core clock has served its purpose,\n                 * as described above.  Resume usage of the other clock. */\n                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\n\n                if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n                {\n                    /* The partial tick period already ended.  Be sure the SysTick\n                     * counts it only once. */\n                    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;\n                }\n\n                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n            }\n            #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */\n\n            /* Step the tick to account for any tick periods that elapsed. */\n            vTaskStepTick( ulCompleteTickPeriods );\n\n            /* Exit with interrupts enabled. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n        }\n    }\n#endif /* configUSE_TICKLESS_IDLE */\n/*-----------------------------------------------------------*/\n\n__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Calculate the constants required to configure the tick interrupt. */\n    #if ( configUSE_TICKLESS_IDLE == 1 )\n    {\n        ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );\n        xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;\n        ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\n    }\n    #endif /* configUSE_TICKLESS_IDLE */\n\n    /* Stop and reset the SysTick. */\n    portNVIC_SYSTICK_CTRL_REG = 0UL;\n    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n    /* Configure SysTick to interrupt at the requested rate. */\n    portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\n    portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvTaskExitError( void )\n{\n    volatile uint32_t ulDummy = 0UL;\n\n    /* A function that implements a task must not exit or attempt to return to\n     * its caller as there is nothing to return to. If a task wants to exit it\n     * should instead call vTaskDelete( NULL ). Artificially force an assert()\n     * to be triggered if configASSERT() is defined, then stop here so\n     * application writers can catch the error. */\n    configASSERT( ulCriticalNesting == ~0UL );\n    portDISABLE_INTERRUPTS();\n\n    while( ulDummy == 0 )\n    {\n        /* This file calls prvTaskExitError() after the scheduler has been\n         * started to remove a compiler warning about the function being\n         * defined but never called.  ulDummy is used purely to quieten other\n         * warnings about code appearing after this function is called - making\n         * ulDummy volatile makes the compiler think the function could return\n         * and therefore not output an 'unreachable code' warning for code that\n         * appears after it. */\n    }\n}\n/*-----------------------------------------------------------*/\n\n#if ( configENABLE_MPU == 1 )\n    static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */\n    {\n        #if defined( __ARMCC_VERSION )\n\n            /* Declaration when these variable are defined in code instead of being\n             * exported from linker scripts. */\n            extern uint32_t * __privileged_functions_start__;\n            extern uint32_t * __privileged_functions_end__;\n            extern uint32_t * __syscalls_flash_start__;\n            extern uint32_t * __syscalls_flash_end__;\n            extern uint32_t * __unprivileged_flash_start__;\n            extern uint32_t * __unprivileged_flash_end__;\n            extern uint32_t * __privileged_sram_start__;\n            extern uint32_t * __privileged_sram_end__;\n        #else /* if defined( __ARMCC_VERSION ) */\n            /* Declaration when these variable are exported from linker scripts. */\n            extern uint32_t __privileged_functions_start__[];\n            extern uint32_t __privileged_functions_end__[];\n            extern uint32_t __syscalls_flash_start__[];\n            extern uint32_t __syscalls_flash_end__[];\n            extern uint32_t __unprivileged_flash_start__[];\n            extern uint32_t __unprivileged_flash_end__[];\n            extern uint32_t __privileged_sram_start__[];\n            extern uint32_t __privileged_sram_end__[];\n        #endif /* defined( __ARMCC_VERSION ) */\n\n        /* The only permitted number of regions are 8 or 16. */\n        configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );\n\n        /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */\n        configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );\n\n        /* Check that the MPU is present. */\n        if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )\n        {\n            /* MAIR0 - Index 0. */\n            portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\n            /* MAIR0 - Index 1. */\n            portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\n\n            /* Setup privileged flash as Read Only so that privileged tasks can\n             * read it but not modify. */\n            portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_PRIVILEGED_READ_ONLY );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Setup unprivileged flash as Read Only by both privileged and\n             * unprivileged tasks. All tasks can read it but no-one can modify. */\n            portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_READ_ONLY );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Setup unprivileged syscalls flash as Read Only by both privileged\n             * and unprivileged tasks. All tasks can read it but no-one can modify. */\n            portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_READ_ONLY );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Setup RAM containing kernel data for privileged access only. */\n            portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\n                               ( portMPU_REGION_EXECUTE_NEVER );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Enable mem fault. */\n            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;\n\n            /* Enable MPU with privileged background access i.e. unmapped\n             * regions have privileged access. */\n            portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );\n        }\n    }\n#endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\n#if ( configENABLE_FPU == 1 )\n    static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */\n    {\n        #if ( configENABLE_TRUSTZONE == 1 )\n        {\n            /* Enable non-secure access to the FPU. */\n            SecureInit_EnableNSFPUAccess();\n        }\n        #endif /* configENABLE_TRUSTZONE */\n\n        /* CP10 = 11 ==> Full access to FPU i.e. both privileged and\n         * unprivileged code should be able to access FPU. CP11 should be\n         * programmed to the same value as CP10. */\n        *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |\n                            ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )\n                            );\n\n        /* ASPEN = 1 ==> Hardware should automatically preserve floating point\n         * context on exception entry and restore on exception return.\n         * LSPEN = 1 ==> Enable lazy context save of FP state. */\n        *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );\n    }\n#endif /* configENABLE_FPU */\n/*-----------------------------------------------------------*/\n\nvoid vPortYield( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Set a PendSV to request a context switch. */\n    portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\n\n    /* Barriers are normally not required but do ensure the code is\n     * completely within the specified behaviour for the architecture. */\n    __asm volatile ( \"dsb\" ::: \"memory\" );\n    __asm volatile ( \"isb\" );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */\n{\n    portDISABLE_INTERRUPTS();\n    ulCriticalNesting++;\n\n    /* Barriers are normally not required but do ensure the code is\n     * completely within the specified behaviour for the architecture. */\n    __asm volatile ( \"dsb\" ::: \"memory\" );\n    __asm volatile ( \"isb\" );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */\n{\n    configASSERT( ulCriticalNesting );\n    ulCriticalNesting--;\n\n    if( ulCriticalNesting == 0 )\n    {\n        portENABLE_INTERRUPTS();\n    }\n}\n/*-----------------------------------------------------------*/\n\nvoid SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */\n{\n    uint32_t ulPreviousMask;\n\n    ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();\n    {\n        /* Increment the RTOS tick. */\n        if( xTaskIncrementTick() != pdFALSE )\n        {\n            /* Pend a context switch. */\n            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\n        }\n    }\n    portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */\n{\n    #if ( configENABLE_MPU == 1 )\n        #if defined( __ARMCC_VERSION )\n\n            /* Declaration when these variable are defined in code instead of being\n             * exported from linker scripts. */\n            extern uint32_t * __syscalls_flash_start__;\n            extern uint32_t * __syscalls_flash_end__;\n        #else\n            /* Declaration when these variable are exported from linker scripts. */\n            extern uint32_t __syscalls_flash_start__[];\n            extern uint32_t __syscalls_flash_end__[];\n        #endif /* defined( __ARMCC_VERSION ) */\n    #endif /* configENABLE_MPU */\n\n    uint32_t ulPC;\n\n    #if ( configENABLE_TRUSTZONE == 1 )\n        uint32_t ulR0, ulR1;\n        extern TaskHandle_t pxCurrentTCB;\n        #if ( configENABLE_MPU == 1 )\n            uint32_t ulControl, ulIsTaskPrivileged;\n        #endif /* configENABLE_MPU */\n    #endif /* configENABLE_TRUSTZONE */\n    uint8_t ucSVCNumber;\n\n    /* Register are stored on the stack in the following order - R0, R1, R2, R3,\n     * R12, LR, PC, xPSR. */\n    ulPC = pulCallerStackAddress[ 6 ];\n    ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];\n\n    switch( ucSVCNumber )\n    {\n        #if ( configENABLE_TRUSTZONE == 1 )\n            case portSVC_ALLOCATE_SECURE_CONTEXT:\n\n                /* R0 contains the stack size passed as parameter to the\n                 * vPortAllocateSecureContext function. */\n                ulR0 = pulCallerStackAddress[ 0 ];\n\n                #if ( configENABLE_MPU == 1 )\n                {\n                    /* Read the CONTROL register value. */\n                    __asm volatile ( \"mrs %0, control\"  : \"=r\" ( ulControl ) );\n\n                    /* The task that raised the SVC is privileged if Bit[0]\n                     * in the CONTROL register is 0. */\n                    ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );\n\n                    /* Allocate and load a context for the secure task. */\n                    xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );\n                }\n                #else /* if ( configENABLE_MPU == 1 ) */\n                {\n                    /* Allocate and load a context for the secure task. */\n                    xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );\n                }\n                #endif /* configENABLE_MPU */\n\n                configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );\n                SecureContext_LoadContext( xSecureContext, pxCurrentTCB );\n                break;\n\n            case portSVC_FREE_SECURE_CONTEXT:\n\n                /* R0 contains TCB being freed and R1 contains the secure\n                 * context handle to be freed. */\n                ulR0 = pulCallerStackAddress[ 0 ];\n                ulR1 = pulCallerStackAddress[ 1 ];\n\n                /* Free the secure context. */\n                SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );\n                break;\n        #endif /* configENABLE_TRUSTZONE */\n\n        case portSVC_START_SCHEDULER:\n            #if ( configENABLE_TRUSTZONE == 1 )\n            {\n                /* De-prioritize the non-secure exceptions so that the\n                 * non-secure pendSV runs at the lowest priority. */\n                SecureInit_DePrioritizeNSExceptions();\n\n                /* Initialize the secure context management system. */\n                SecureContext_Init();\n            }\n            #endif /* configENABLE_TRUSTZONE */\n\n            #if ( configENABLE_FPU == 1 )\n            {\n                /* Setup the Floating Point Unit (FPU). */\n                prvSetupFPU();\n            }\n            #endif /* configENABLE_FPU */\n\n            /* Setup the context of the first task so that the first task starts\n             * executing. */\n            vRestoreContextOfFirstTask();\n            break;\n\n            #if ( configENABLE_MPU == 1 )\n                case portSVC_RAISE_PRIVILEGE:\n\n                    /* Only raise the privilege, if the svc was raised from any of\n                     * the system calls. */\n                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&\n                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )\n                    {\n                        vRaisePrivilege();\n                    }\n                    break;\n            #endif /* configENABLE_MPU */\n\n        default:\n            /* Incorrect SVC call. */\n            configASSERT( pdFALSE );\n    }\n}\n/*-----------------------------------------------------------*/\n/* *INDENT-OFF* */\n#if ( configENABLE_MPU == 1 )\n    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,\n                                         StackType_t * pxEndOfStack,\n                                         TaskFunction_t pxCode,\n                                         void * pvParameters,\n                                         BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */\n#else\n    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,\n                                         StackType_t * pxEndOfStack,\n                                         TaskFunction_t pxCode,\n                                         void * pvParameters ) /* PRIVILEGED_FUNCTION */\n#endif /* configENABLE_MPU */\n/* *INDENT-ON* */\n{\n    /* Simulate the stack frame as it would be created by a context switch\n     * interrupt. */\n    #if ( portPRELOAD_REGISTERS == 0 )\n    {\n        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\n        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\n        pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */\n        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */\n        pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */\n        *pxTopOfStack = portINITIAL_EXC_RETURN;\n\n        #if ( configENABLE_MPU == 1 )\n        {\n            pxTopOfStack--;\n\n            if( xRunPrivileged == pdTRUE )\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n            else\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n        }\n        #endif /* configENABLE_MPU */\n\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\n\n        #if ( configENABLE_TRUSTZONE == 1 )\n        {\n            pxTopOfStack--;\n            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\n        }\n        #endif /* configENABLE_TRUSTZONE */\n    }\n    #else /* portPRELOAD_REGISTERS */\n    {\n        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\n        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04 */\n        pxTopOfStack--;\n        *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN */\n\n        #if ( configENABLE_MPU == 1 )\n        {\n            pxTopOfStack--;\n\n            if( xRunPrivileged == pdTRUE )\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n            else\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n        }\n        #endif /* configENABLE_MPU */\n\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\n\n        #if ( configENABLE_TRUSTZONE == 1 )\n        {\n            pxTopOfStack--;\n            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\n        }\n        #endif /* configENABLE_TRUSTZONE */\n    }\n    #endif /* portPRELOAD_REGISTERS */\n\n    return pxTopOfStack;\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Make PendSV, CallSV and SysTick the same priority as the kernel. */\n    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;\n    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;\n\n    #if ( configENABLE_MPU == 1 )\n    {\n        /* Setup the Memory Protection Unit (MPU). */\n        prvSetupMPU();\n    }\n    #endif /* configENABLE_MPU */\n\n    /* Start the timer that generates the tick ISR. Interrupts are disabled\n     * here already. */\n    vPortSetupTimerInterrupt();\n\n    /* Initialize the critical nesting count ready for the first task. */\n    ulCriticalNesting = 0;\n\n    /* Start the first task. */\n    vStartFirstTask();\n\n    /* Should never get here as the tasks will now be executing. Call the task\n     * exit error function to prevent compiler warnings about a static function\n     * not being called in the case that the application writer overrides this\n     * functionality by defining configTASK_RETURN_ADDRESS. Call\n     * vTaskSwitchContext() so link time optimization does not remove the\n     * symbol. */\n    vTaskSwitchContext();\n    prvTaskExitError();\n\n    /* Should not get here. */\n    return 0;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Not implemented in ports where there is nothing to return to.\n     * Artificially force an assert. */\n    configASSERT( ulCriticalNesting == 1000UL );\n}\n/*-----------------------------------------------------------*/\n\n#if ( configENABLE_MPU == 1 )\n    void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,\n                                    const struct xMEMORY_REGION * const xRegions,\n                                    StackType_t * pxBottomOfStack,\n                                    uint32_t ulStackDepth )\n    {\n        uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;\n        int32_t lIndex = 0;\n\n        #if defined( __ARMCC_VERSION )\n\n            /* Declaration when these variable are defined in code instead of being\n             * exported from linker scripts. */\n            extern uint32_t * __privileged_sram_start__;\n            extern uint32_t * __privileged_sram_end__;\n        #else\n            /* Declaration when these variable are exported from linker scripts. */\n            extern uint32_t __privileged_sram_start__[];\n            extern uint32_t __privileged_sram_end__[];\n        #endif /* defined( __ARMCC_VERSION ) */\n\n        /* Setup MAIR0. */\n        xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\n        xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\n\n        /* This function is called automatically when the task is created - in\n         * which case the stack region parameters will be valid.  At all other\n         * times the stack parameters will not be valid and it is assumed that\n         * the stack region has already been configured. */\n        if( ulStackDepth > 0 )\n        {\n            ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;\n            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;\n\n            /* If the stack is within the privileged SRAM, do not protect it\n             * using a separate MPU region. This is needed because privileged\n             * SRAM is already protected using an MPU region and ARMv8-M does\n             * not allow overlapping MPU regions. */\n            if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) &&\n                ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) )\n            {\n                xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0;\n                xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0;\n            }\n            else\n            {\n                /* Define the region that allows access to the stack. */\n                ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK;\n                ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\n\n                xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |\n                                                             ( portMPU_REGION_NON_SHAREABLE ) |\n                                                             ( portMPU_REGION_READ_WRITE ) |\n                                                             ( portMPU_REGION_EXECUTE_NEVER );\n\n                xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) |\n                                                             ( portMPU_RLAR_ATTR_INDEX0 ) |\n                                                             ( portMPU_RLAR_REGION_ENABLE );\n            }\n        }\n\n        /* User supplied configurable regions. */\n        for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )\n        {\n            /* If xRegions is NULL i.e. the task has not specified any MPU\n             * region, the else part ensures that all the configurable MPU\n             * regions are invalidated. */\n            if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )\n            {\n                /* Translate the generic region definition contained in xRegions\n                 * into the ARMv8 specific MPU settings that are then stored in\n                 * xMPUSettings. */\n                ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;\n                ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;\n                ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\n\n                /* Start address. */\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |\n                                                                          ( portMPU_REGION_NON_SHAREABLE );\n\n                /* RO/RW. */\n                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )\n                {\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );\n                }\n                else\n                {\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );\n                }\n\n                /* XN. */\n                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )\n                {\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );\n                }\n\n                /* End Address. */\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |\n                                                                          ( portMPU_RLAR_REGION_ENABLE );\n\n                /* Normal memory/ Device memory. */\n                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )\n                {\n                    /* Attr1 in MAIR0 is configured as device memory. */\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;\n                }\n                else\n                {\n                    /* Attr0 in MAIR0 is configured as normal memory. */\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;\n                }\n            }\n            else\n            {\n                /* Invalidate the region. */\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;\n            }\n\n            lIndex++;\n        }\n    }\n#endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\nBaseType_t xPortIsInsideInterrupt( void )\n{\n    uint32_t ulCurrentInterrupt;\n    BaseType_t xReturn;\n\n    /* Obtain the number of the currently executing interrupt. Interrupt Program\n     * Status Register (IPSR) holds the exception number of the currently-executing\n     * exception or zero for Thread mode.*/\n    __asm volatile ( \"mrs %0, ipsr\" : \"=r\" ( ulCurrentInterrupt )::\"memory\" );\n\n    if( ulCurrentInterrupt == 0 )\n    {\n        xReturn = pdFALSE;\n    }\n    else\n    {\n        xReturn = pdTRUE;\n    }\n\n    return xReturn;\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef __PORT_ASM_H__\n#define __PORT_ASM_H__\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n\n/* MPU wrappers includes. */\n#include \"mpu_wrappers.h\"\n\n/**\n * @brief Restore the context of the first task so that the first task starts\n * executing.\n */\nvoid vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Checks whether or not the processor is privileged.\n *\n * @return 1 if the processor is already privileged, 0 otherwise.\n */\nBaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );\n\n/**\n * @brief Raises the privilege level by clearing the bit 0 of the CONTROL\n * register.\n *\n * @note This is a privileged function and should only be called from the kenrel\n * code.\n *\n * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.\n *  Bit[0] = 0 --> The processor is running privileged\n *  Bit[0] = 1 --> The processor is running unprivileged.\n */\nvoid vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\n * register.\n *\n * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.\n *  Bit[0] = 0 --> The processor is running privileged\n *  Bit[0] = 1 --> The processor is running unprivileged.\n */\nvoid vResetPrivilege( void ) __attribute__( ( naked ) );\n\n/**\n * @brief Starts the first task.\n */\nvoid vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Disables interrupts.\n */\nuint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Enables interrupts.\n */\nvoid vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief PendSV Exception handler.\n */\nvoid PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief SVC Handler.\n */\nvoid SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Allocate a Secure context for the calling task.\n *\n * @param[in] ulSecureStackSize The size of the stack to be allocated on the\n * secure side for the calling task.\n */\nvoid vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) );\n\n/**\n * @brief Free the task's secure context.\n *\n * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.\n */\nvoid vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n#endif /* __PORT_ASM_H__ */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.s",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n/* Including FreeRTOSConfig.h here will cause build errors if the header file\ncontains code not understood by the assembler - for example the 'extern' keyword.\nTo avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so\nthe code is included in C files but excluded by the preprocessor in assembly\nfiles (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */\n#include \"FreeRTOSConfig.h\"\n\n\tEXTERN pxCurrentTCB\n\tEXTERN vTaskSwitchContext\n\tEXTERN vPortSVCHandler_C\n\n\tPUBLIC xIsPrivileged\n\tPUBLIC vResetPrivilege\n\tPUBLIC vRestoreContextOfFirstTask\n\tPUBLIC vRaisePrivilege\n\tPUBLIC vStartFirstTask\n\tPUBLIC ulSetInterruptMask\n\tPUBLIC vClearInterruptMask\n\tPUBLIC PendSV_Handler\n\tPUBLIC SVC_Handler\n/*-----------------------------------------------------------*/\n\n/*---------------- Unprivileged Functions -------------------*/\n\n/*-----------------------------------------------------------*/\n\n\tSECTION .text:CODE:NOROOT(2)\n\tTHUMB\n/*-----------------------------------------------------------*/\n\nxIsPrivileged:\n\tmrs r0, control\t\t\t\t\t\t\t/* r0 = CONTROL. */\n\ttst r0, #1\t\t\t\t\t\t\t\t/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\n\tite ne\n\tmovne r0, #0\t\t\t\t\t\t\t/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\n\tmoveq r0, #1\t\t\t\t\t\t\t/* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */\n\tbx lr\t\t\t\t\t\t\t\t\t/* Return. */\n/*-----------------------------------------------------------*/\n\nvResetPrivilege:\n\tmrs r0, control\t\t\t\t\t\t\t/* r0 = CONTROL. */\n\torr r0, r0, #1\t\t\t\t\t\t\t/* r0 = r0 | 1. */\n\tmsr control, r0\t\t\t\t\t\t\t/* CONTROL = r0. */\n\tbx lr\t\t\t\t\t\t\t\t\t/* Return to the caller. */\n/*-----------------------------------------------------------*/\n\n/*----------------- Privileged Functions --------------------*/\n\n/*-----------------------------------------------------------*/\n\n\tSECTION privileged_functions:CODE:NOROOT(2)\n\tTHUMB\n/*-----------------------------------------------------------*/\n\nvRestoreContextOfFirstTask:\n\tldr  r2, =pxCurrentTCB\t\t\t\t\t/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n\tldr  r1, [r2]\t\t\t\t\t\t\t/* Read pxCurrentTCB. */\n\tldr  r0, [r1]\t\t\t\t\t\t\t/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\n\n#if ( configENABLE_MPU == 1 )\n\tdmb\t\t\t\t\t\t\t\t\t\t/* Complete outstanding transfers before disabling MPU. */\n\tldr r2, =0xe000ed94\t\t\t\t\t\t/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n\tldr r4, [r2]\t\t\t\t\t\t\t/* Read the value of MPU_CTRL. */\n\tbic r4, r4, #1\t\t\t\t\t\t\t/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\n\tstr r4, [r2]\t\t\t\t\t\t\t/* Disable MPU. */\n\n\tadds r1, #4\t\t\t\t\t\t\t\t/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\n\tldr r3, [r1]\t\t\t\t\t\t\t/* r3 = *r1 i.e. r3 = MAIR0. */\n\tldr r2, =0xe000edc0\t\t\t\t\t\t/* r2 = 0xe000edc0 [Location of MAIR0]. */\n\tstr r3, [r2]\t\t\t\t\t\t\t/* Program MAIR0. */\n\tldr r2, =0xe000ed98\t\t\t\t\t\t/* r2 = 0xe000ed98 [Location of RNR]. */\n\tmovs r3, #4\t\t\t\t\t\t\t\t/* r3 = 4. */\n\tstr r3, [r2]\t\t\t\t\t\t\t/* Program RNR = 4. */\n\tadds r1, #4\t\t\t\t\t\t\t\t/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\n\tldr r2, =0xe000ed9c\t\t\t\t\t\t/* r2 = 0xe000ed9c [Location of RBAR]. */\n\tldmia r1!, {r4-r11}\t\t\t\t\t\t/* Read 4 sets of RBAR/RLAR registers from TCB. */\n\tstmia r2!, {r4-r11}\t\t\t\t\t\t/* Write 4 set of RBAR/RLAR registers using alias registers. */\n\n\tldr r2, =0xe000ed94\t\t\t\t\t\t/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n\tldr r4, [r2]\t\t\t\t\t\t\t/* Read the value of MPU_CTRL. */\n\torr r4, r4, #1\t\t\t\t\t\t\t/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\n\tstr r4, [r2]\t\t\t\t\t\t\t/* Enable MPU. */\n\tdsb\t\t\t\t\t\t\t\t\t\t/* Force memory writes before continuing. */\n#endif /* configENABLE_MPU */\n\n#if ( configENABLE_MPU == 1 )\n\tldm  r0!, {r1-r3}\t\t\t\t\t\t/* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */\n\tmsr  psplim, r1\t\t\t\t\t\t\t/* Set this task's PSPLIM value. */\n\tmsr  control, r2\t\t\t\t\t\t/* Set this task's CONTROL value. */\n\tadds r0, #32\t\t\t\t\t\t\t/* Discard everything up to r0. */\n\tmsr  psp, r0\t\t\t\t\t\t\t/* This is now the new top of stack to use in the task. */\n\tisb\n\tmov  r0, #0\n\tmsr  basepri, r0\t\t\t\t\t\t/* Ensure that interrupts are enabled when the first task starts. */\n\tbx   r3\t\t\t\t\t\t\t\t\t/* Finally, branch to EXC_RETURN. */\n#else /* configENABLE_MPU */\n\tldm  r0!, {r1-r2}\t\t\t\t\t\t/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */\n\tmsr  psplim, r1\t\t\t\t\t\t\t/* Set this task's PSPLIM value. */\n\tmovs r1, #2\t\t\t\t\t\t\t\t/* r1 = 2. */\n\tmsr  CONTROL, r1\t\t\t\t\t\t/* Switch to use PSP in the thread mode. */\n\tadds r0, #32\t\t\t\t\t\t\t/* Discard everything up to r0. */\n\tmsr  psp, r0\t\t\t\t\t\t\t/* This is now the new top of stack to use in the task. */\n\tisb\n\tmov  r0, #0\n\tmsr  basepri, r0\t\t\t\t\t\t/* Ensure that interrupts are enabled when the first task starts. */\n\tbx   r2\t\t\t\t\t\t\t\t\t/* Finally, branch to EXC_RETURN. */\n#endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\nvRaisePrivilege:\n\tmrs  r0, control\t\t\t\t\t\t/* Read the CONTROL register. */\n\tbic r0, r0, #1\t\t\t\t\t\t\t/* Clear the bit 0. */\n\tmsr  control, r0\t\t\t\t\t\t/* Write back the new CONTROL value. */\n\tbx lr\t\t\t\t\t\t\t\t\t/* Return to the caller. */\n/*-----------------------------------------------------------*/\n\nvStartFirstTask:\n\tldr r0, =0xe000ed08\t\t\t\t\t\t/* Use the NVIC offset register to locate the stack. */\n\tldr r0, [r0]\t\t\t\t\t\t\t/* Read the VTOR register which gives the address of vector table. */\n\tldr r0, [r0]\t\t\t\t\t\t\t/* The first entry in vector table is stack pointer. */\n\tmsr msp, r0\t\t\t\t\t\t\t\t/* Set the MSP back to the start of the stack. */\n\tcpsie i\t\t\t\t\t\t\t\t\t/* Globally enable interrupts. */\n\tcpsie f\n\tdsb\n\tisb\n\tsvc 2\t\t\t\t\t\t\t\t\t/* System call to start the first task. portSVC_START_SCHEDULER = 2. */\n/*-----------------------------------------------------------*/\n\nulSetInterruptMask:\n\tmrs r0, basepri\t\t\t\t\t\t\t/* r0 = basepri. Return original basepri value. */\n\tmov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY\n\tmsr basepri, r1\t\t\t\t\t\t\t/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */\n\tdsb\n\tisb\n\tbx lr\t\t\t\t\t\t\t\t\t/* Return. */\n/*-----------------------------------------------------------*/\n\nvClearInterruptMask:\n\tmsr basepri, r0\t\t\t\t\t\t\t/* basepri = ulMask. */\n\tdsb\n\tisb\n\tbx lr\t\t\t\t\t\t\t\t\t/* Return. */\n/*-----------------------------------------------------------*/\n\nPendSV_Handler:\n\tmrs r0, psp\t\t\t\t\t\t\t\t/* Read PSP in r0. */\n#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )\n\ttst lr, #0x10\t\t\t\t\t\t\t/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */\n\tit eq\n\tvstmdbeq r0!, {s16-s31}\t\t\t\t\t/* Store the additional FP context registers which are not saved automatically. */\n#endif /* configENABLE_FPU || configENABLE_MVE */\n#if ( configENABLE_MPU == 1 )\n\tmrs r1, psplim\t\t\t\t\t\t\t/* r1 = PSPLIM. */\n\tmrs r2, control\t\t\t\t\t\t\t/* r2 = CONTROL. */\n\tmov r3, lr\t\t\t\t\t\t\t\t/* r3 = LR/EXC_RETURN. */\n\tstmdb r0!, {r1-r11}\t\t\t\t\t\t/* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */\n#else /* configENABLE_MPU */\n\tmrs r2, psplim\t\t\t\t\t\t\t/* r2 = PSPLIM. */\n\tmov r3, lr\t\t\t\t\t\t\t\t/* r3 = LR/EXC_RETURN. */\n\tstmdb r0!, {r2-r11}\t\t\t\t\t\t/* Store on the stack - PSPLIM, LR and registers that are not automatically. */\n#endif /* configENABLE_MPU */\n\n\tldr r2, =pxCurrentTCB\t\t\t\t\t/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n\tldr r1, [r2]\t\t\t\t\t\t\t/* Read pxCurrentTCB. */\n\tstr r0, [r1]\t\t\t\t\t\t\t/* Save the new top of stack in TCB. */\n\n\tmov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY\n\tmsr basepri, r0\t\t\t\t\t\t\t/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */\n\tdsb\n\tisb\n\tbl vTaskSwitchContext\n\tmov r0, #0\t\t\t\t\t\t\t\t/* r0 = 0. */\n\tmsr basepri, r0\t\t\t\t\t\t\t/* Enable interrupts. */\n\n\tldr r2, =pxCurrentTCB\t\t\t\t\t/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n\tldr r1, [r2]\t\t\t\t\t\t\t/* Read pxCurrentTCB. */\n\tldr r0, [r1]\t\t\t\t\t\t\t/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */\n\n#if ( configENABLE_MPU == 1 )\n\tdmb\t\t\t\t\t\t\t\t\t\t/* Complete outstanding transfers before disabling MPU. */\n\tldr r2, =0xe000ed94\t\t\t\t\t\t/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n\tldr r4, [r2]\t\t\t\t\t\t\t/* Read the value of MPU_CTRL. */\n\tbic r4, r4, #1\t\t\t\t\t\t\t/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\n\tstr r4, [r2]\t\t\t\t\t\t\t/* Disable MPU. */\n\n\tadds r1, #4\t\t\t\t\t\t\t\t/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\n\tldr r3, [r1]\t\t\t\t\t\t\t/* r3 = *r1 i.e. r3 = MAIR0. */\n\tldr r2, =0xe000edc0\t\t\t\t\t\t/* r2 = 0xe000edc0 [Location of MAIR0]. */\n\tstr r3, [r2]\t\t\t\t\t\t\t/* Program MAIR0. */\n\tldr r2, =0xe000ed98\t\t\t\t\t\t/* r2 = 0xe000ed98 [Location of RNR]. */\n\tmovs r3, #4\t\t\t\t\t\t\t\t/* r3 = 4. */\n\tstr r3, [r2]\t\t\t\t\t\t\t/* Program RNR = 4. */\n\tadds r1, #4\t\t\t\t\t\t\t\t/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\n\tldr r2, =0xe000ed9c\t\t\t\t\t\t/* r2 = 0xe000ed9c [Location of RBAR]. */\n\tldmia r1!, {r4-r11}\t\t\t\t\t\t/* Read 4 sets of RBAR/RLAR registers from TCB. */\n\tstmia r2!, {r4-r11}\t\t\t\t\t\t/* Write 4 set of RBAR/RLAR registers using alias registers. */\n\n\tldr r2, =0xe000ed94\t\t\t\t\t\t/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n\tldr r4, [r2]\t\t\t\t\t\t\t/* Read the value of MPU_CTRL. */\n\torr r4, r4, #1\t\t\t\t\t\t\t/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\n\tstr r4, [r2]\t\t\t\t\t\t\t/* Enable MPU. */\n\tdsb\t\t\t\t\t\t\t\t\t\t/* Force memory writes before continuing. */\n#endif /* configENABLE_MPU */\n\n#if ( configENABLE_MPU == 1 )\n\tldmia r0!, {r1-r11}\t\t\t\t\t\t/* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */\n#else /* configENABLE_MPU */\n\tldmia r0!, {r2-r11}\t\t\t\t\t\t/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */\n#endif /* configENABLE_MPU */\n\n#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )\n\ttst r3, #0x10\t\t\t\t\t\t\t/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */\n\tit eq\n\tvldmiaeq r0!, {s16-s31}\t\t\t\t\t/* Restore the additional FP context registers which are not restored automatically. */\n#endif /* configENABLE_FPU || configENABLE_MVE */\n\n #if ( configENABLE_MPU == 1 )\n\tmsr psplim, r1\t\t\t\t\t\t\t/* Restore the PSPLIM register value for the task. */\n\tmsr control, r2\t\t\t\t\t\t\t/* Restore the CONTROL register value for the task. */\n#else /* configENABLE_MPU */\n\tmsr psplim, r2\t\t\t\t\t\t\t/* Restore the PSPLIM register value for the task. */\n#endif /* configENABLE_MPU */\n\tmsr psp, r0\t\t\t\t\t\t\t\t/* Remember the new top of stack for the task. */\n\tbx r3\n/*-----------------------------------------------------------*/\n\nSVC_Handler:\n\ttst lr, #4\n\tite eq\n\tmrseq r0, msp\n\tmrsne r0, psp\n\tb vPortSVCHandler_C\n/*-----------------------------------------------------------*/\n\n\tEND\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM55_NTZ/non_secure/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef PORTMACRO_H\n#define PORTMACRO_H\n\n#ifdef __cplusplus\n    extern \"C\" {\n#endif\n\n#include \"portmacrocommon.h\"\n\n/*------------------------------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the given hardware\n * and compiler.\n *\n * These settings should not be altered.\n *------------------------------------------------------------------------------\n */\n\n#ifndef configENABLE_MVE\n    #error configENABLE_MVE must be defined in FreeRTOSConfig.h. Set configENABLE_MVE to 1 to enable the MVE or 0 to disable the MVE.\n#endif /* configENABLE_MVE */\n/*-----------------------------------------------------------*/\n\n/**\n * Architecture specifics.\n */\n#define portARCH_NAME                       \"Cortex-M55\"\n#define portDONT_DISCARD                    __root\n/*-----------------------------------------------------------*/\n\n#if( configTOTAL_MPU_REGIONS == 16 )\n    #error 16 MPU regions are not yet supported for this port.\n#endif\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Critical section management.\n */\n#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()\n#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )\n/*-----------------------------------------------------------*/\n\n/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in\n * the source code because to do so would cause other compilers to generate\n * warnings. */\n#pragma diag_suppress=Be006\n#pragma diag_suppress=Pa082\n/*-----------------------------------------------------------*/\n\n#ifdef __cplusplus\n    }\n#endif\n\n#endif /* PORTMACRO_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef PORTMACROCOMMON_H\n    #define PORTMACROCOMMON_H\n\n    #ifdef __cplusplus\n        extern \"C\" {\n    #endif\n\n/*------------------------------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the given hardware\n * and compiler.\n *\n * These settings should not be altered.\n *------------------------------------------------------------------------------\n */\n\n    #ifndef configENABLE_FPU\n        #error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.\n    #endif /* configENABLE_FPU */\n\n    #ifndef configENABLE_MPU\n        #error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.\n    #endif /* configENABLE_MPU */\n\n    #ifndef configENABLE_TRUSTZONE\n        #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.\n    #endif /* configENABLE_TRUSTZONE */\n\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Type definitions.\n */\n    #define portCHAR          char\n    #define portFLOAT         float\n    #define portDOUBLE        double\n    #define portLONG          long\n    #define portSHORT         short\n    #define portSTACK_TYPE    uint32_t\n    #define portBASE_TYPE     long\n\n    typedef portSTACK_TYPE   StackType_t;\n    typedef long             BaseType_t;\n    typedef unsigned long    UBaseType_t;\n\n    #if ( configUSE_16_BIT_TICKS == 1 )\n        typedef uint16_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffff\n    #else\n        typedef uint32_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL\n\n/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\n * not need to be guarded with a critical section. */\n        #define portTICK_TYPE_IS_ATOMIC    1\n    #endif\n/*-----------------------------------------------------------*/\n\n/**\n * Architecture specifics.\n */\n    #define portSTACK_GROWTH                   ( -1 )\n    #define portTICK_PERIOD_MS                 ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\n    #define portBYTE_ALIGNMENT                 8\n    #define portNOP()\n    #define portINLINE                         __inline\n    #ifndef portFORCE_INLINE\n        #define portFORCE_INLINE               inline __attribute__( ( always_inline ) )\n    #endif\n    #define portHAS_STACK_OVERFLOW_CHECKING    1\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Extern declarations.\n */\n    extern BaseType_t xPortIsInsideInterrupt( void );\n\n    extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;\n\n    extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;\n    extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;\n\n    extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\n    extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\n\n    #if ( configENABLE_TRUSTZONE == 1 )\n        extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */\n        extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;\n    #endif /* configENABLE_TRUSTZONE */\n\n    #if ( configENABLE_MPU == 1 )\n        extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;\n        extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;\n    #endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\n/**\n * @brief MPU specific constants.\n */\n    #if ( configENABLE_MPU == 1 )\n        #define portUSING_MPU_WRAPPERS    1\n        #define portPRIVILEGE_BIT         ( 0x80000000UL )\n    #else\n        #define portPRIVILEGE_BIT         ( 0x0UL )\n    #endif /* configENABLE_MPU */\n\n/* MPU settings that can be overriden in FreeRTOSConfig.h. */\n#ifndef configTOTAL_MPU_REGIONS\n    /* Define to 8 for backward compatibility. */\n    #define configTOTAL_MPU_REGIONS       ( 8UL )\n#endif\n\n/* MPU regions. */\n    #define portPRIVILEGED_FLASH_REGION                   ( 0UL )\n    #define portUNPRIVILEGED_FLASH_REGION                 ( 1UL )\n    #define portUNPRIVILEGED_SYSCALLS_REGION              ( 2UL )\n    #define portPRIVILEGED_RAM_REGION                     ( 3UL )\n    #define portSTACK_REGION                              ( 4UL )\n    #define portFIRST_CONFIGURABLE_REGION                 ( 5UL )\n    #define portLAST_CONFIGURABLE_REGION                  ( configTOTAL_MPU_REGIONS - 1UL )\n    #define portNUM_CONFIGURABLE_REGIONS                  ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )\n    #define portTOTAL_NUM_REGIONS                         ( portNUM_CONFIGURABLE_REGIONS + 1 )   /* Plus one to make space for the stack region. */\n\n/* Device memory attributes used in MPU_MAIR registers.\n *\n * 8-bit values encoded as follows:\n *  Bit[7:4] - 0000 - Device Memory\n *  Bit[3:2] - 00 --> Device-nGnRnE\n *\t\t\t\t01 --> Device-nGnRE\n *\t\t\t\t10 --> Device-nGRE\n *\t\t\t\t11 --> Device-GRE\n *  Bit[1:0] - 00, Reserved.\n */\n    #define portMPU_DEVICE_MEMORY_nGnRnE                  ( 0x00 )   /* 0000 0000 */\n    #define portMPU_DEVICE_MEMORY_nGnRE                   ( 0x04 )   /* 0000 0100 */\n    #define portMPU_DEVICE_MEMORY_nGRE                    ( 0x08 )   /* 0000 1000 */\n    #define portMPU_DEVICE_MEMORY_GRE                     ( 0x0C )   /* 0000 1100 */\n\n/* Normal memory attributes used in MPU_MAIR registers. */\n    #define portMPU_NORMAL_MEMORY_NON_CACHEABLE           ( 0x44 )   /* Non-cacheable. */\n    #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE    ( 0xFF )   /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */\n\n/* Attributes used in MPU_RBAR registers. */\n    #define portMPU_REGION_NON_SHAREABLE                  ( 0UL << 3UL )\n    #define portMPU_REGION_INNER_SHAREABLE                ( 1UL << 3UL )\n    #define portMPU_REGION_OUTER_SHAREABLE                ( 2UL << 3UL )\n\n    #define portMPU_REGION_PRIVILEGED_READ_WRITE          ( 0UL << 1UL )\n    #define portMPU_REGION_READ_WRITE                     ( 1UL << 1UL )\n    #define portMPU_REGION_PRIVILEGED_READ_ONLY           ( 2UL << 1UL )\n    #define portMPU_REGION_READ_ONLY                      ( 3UL << 1UL )\n\n    #define portMPU_REGION_EXECUTE_NEVER                  ( 1UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Settings to define an MPU region.\n */\n    typedef struct MPURegionSettings\n    {\n        uint32_t ulRBAR; /**< RBAR for the region. */\n        uint32_t ulRLAR; /**< RLAR for the region. */\n    } MPURegionSettings_t;\n\n/**\n * @brief MPU settings as stored in the TCB.\n */\n    typedef struct MPU_SETTINGS\n    {\n        uint32_t ulMAIR0;                                              /**< MAIR0 for the task containing attributes for all the 4 per task regions. */\n        MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */\n    } xMPU_SETTINGS;\n/*-----------------------------------------------------------*/\n\n/**\n * @brief SVC numbers.\n */\n    #define portSVC_ALLOCATE_SECURE_CONTEXT    0\n    #define portSVC_FREE_SECURE_CONTEXT        1\n    #define portSVC_START_SCHEDULER            2\n    #define portSVC_RAISE_PRIVILEGE            3\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Scheduler utilities.\n */\n    #define portYIELD()                                 vPortYield()\n    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )\n    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )\n    #define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )\n    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Critical section management.\n */\n    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulSetInterruptMask()\n    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vClearInterruptMask( x )\n    #define portENTER_CRITICAL()                      vPortEnterCritical()\n    #define portEXIT_CRITICAL()                       vPortExitCritical()\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Tickless idle/low power functionality.\n */\n    #ifndef portSUPPRESS_TICKS_AND_SLEEP\n        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );\n        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )\n    #endif\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Task function macros as described on the FreeRTOS.org WEB site.\n */\n    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )\n    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )\n/*-----------------------------------------------------------*/\n\n    #if ( configENABLE_TRUSTZONE == 1 )\n\n/**\n * @brief Allocate a secure context for the task.\n *\n * Tasks are not created with a secure context. Any task that is going to call\n * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a\n * secure context before it calls any secure function.\n *\n * @param[in] ulSecureStackSize The size of the secure stack to be allocated.\n */\n        #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )\n\n/**\n * @brief Called when a task is deleted to delete the task's secure context,\n * if it has one.\n *\n * @param[in] pxTCB The TCB of the task being deleted.\n */\n        #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )\n    #endif /* configENABLE_TRUSTZONE */\n/*-----------------------------------------------------------*/\n\n    #if ( configENABLE_MPU == 1 )\n\n/**\n * @brief Checks whether or not the processor is privileged.\n *\n * @return 1 if the processor is already privileged, 0 otherwise.\n */\n        #define portIS_PRIVILEGED()      xIsPrivileged()\n\n/**\n * @brief Raise an SVC request to raise privilege.\n *\n * The SVC handler checks that the SVC was raised from a system call and only\n * then it raises the privilege. If this is called from any other place,\n * the privilege is not raised.\n */\n        #define portRAISE_PRIVILEGE()    __asm volatile ( \"svc %0 \\n\" ::\"i\" ( portSVC_RAISE_PRIVILEGE ) : \"memory\" );\n\n/**\n * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\n * register.\n */\n        #define portRESET_PRIVILEGE()    vResetPrivilege()\n    #else\n        #define portIS_PRIVILEGED()\n        #define portRAISE_PRIVILEGE()\n        #define portRESET_PRIVILEGE()\n    #endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Barriers.\n */\n    #define portMEMORY_BARRIER()    __asm volatile ( \"\" ::: \"memory\" )\n/*-----------------------------------------------------------*/\n\n    #ifdef __cplusplus\n        }\n    #endif\n\n#endif /* PORTMACROCOMMON_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM7/ReadMe.txt",
    "content": "There are two options for running FreeRTOS on ARM Cortex-M7 microcontrollers.\nThe best option depends on the revision of the ARM Cortex-M7 core in use.  The\nrevision is specified by an 'r' number, and a 'p' number, so will look something\nlike 'r0p1'.  Check the documentation for the microcontroller in use to find the \nrevision of the Cortex-M7 core used in that microcontroller.  If in doubt, use \nthe FreeRTOS port provided specifically for r0p1 revisions, as that can be used\nwith all core revisions.\n\nThe first option is to use the ARM Cortex-M4F port, and the second option is to\nuse the Cortex-M7 r0p1 port - the latter containing a minor errata workaround.\n\nIf the revision of the ARM Cortex-M7 core is not r0p1 then either option can be\nused, but it is recommended to use the FreeRTOS ARM Cortex-M4F port located in \nthe /FreeRTOS/Source/portable/IAR/ARM_CM4F directory.\n\nIf the revision of the ARM Cortex-M7 core is r0p1 then use the FreeRTOS ARM\nCortex-M7 r0p1 port located in the /FreeRTOS/Source/portable/IAR/ARM_CM7/r0p1\ndirectory."
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM7/r0p1/port.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/*-----------------------------------------------------------\n* Implementation of functions defined in portable.h for the ARM CM7 port.\n*----------------------------------------------------------*/\n\n/* IAR includes. */\n#include <intrinsics.h>\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n#ifndef __ARMVFP__\n    #error This port can only be used when the project options are configured to enable hardware floating point support.\n#endif\n\n#if ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 )\n    #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\n#endif\n\n/* Constants required to manipulate the core.  Registers first... */\n#define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )\n#define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )\n#define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )\n#define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )\n/* ...then bits in the registers. */\n#define portNVIC_SYSTICK_CLK_BIT              ( 1UL << 2UL )\n#define portNVIC_SYSTICK_INT_BIT              ( 1UL << 1UL )\n#define portNVIC_SYSTICK_ENABLE_BIT           ( 1UL << 0UL )\n#define portNVIC_SYSTICK_COUNT_FLAG_BIT       ( 1UL << 16UL )\n#define portNVIC_PENDSVCLEAR_BIT              ( 1UL << 27UL )\n#define portNVIC_PEND_SYSTICK_SET_BIT         ( 1UL << 26UL )\n#define portNVIC_PEND_SYSTICK_CLEAR_BIT       ( 1UL << 25UL )\n\n#define portNVIC_PENDSV_PRI                   ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\n#define portNVIC_SYSTICK_PRI                  ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\n\n/* Constants required to check the validity of an interrupt priority. */\n#define portFIRST_USER_INTERRUPT_NUMBER       ( 16 )\n#define portNVIC_IP_REGISTERS_OFFSET_16       ( 0xE000E3F0 )\n#define portAIRCR_REG                         ( *( ( volatile uint32_t * ) 0xE000ED0C ) )\n#define portMAX_8_BIT_VALUE                   ( ( uint8_t ) 0xff )\n#define portTOP_BIT_OF_BYTE                   ( ( uint8_t ) 0x80 )\n#define portMAX_PRIGROUP_BITS                 ( ( uint8_t ) 7 )\n#define portPRIORITY_GROUP_MASK               ( 0x07UL << 8UL )\n#define portPRIGROUP_SHIFT                    ( 8UL )\n\n/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */\n#define portVECTACTIVE_MASK                   ( 0xFFUL )\n\n/* Constants required to manipulate the VFP. */\n#define portFPCCR                             ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */\n#define portASPEN_AND_LSPEN_BITS              ( 0x3UL << 30UL )\n\n/* Constants required to set up the initial stack. */\n#define portINITIAL_XPSR                      ( 0x01000000 )\n#define portINITIAL_EXC_RETURN                ( 0xfffffffd )\n\n/* The systick is a 24-bit counter. */\n#define portMAX_24_BIT_NUMBER                 ( 0xffffffUL )\n\n/* A fiddle factor to estimate the number of SysTick counts that would have\n * occurred while the SysTick counter is stopped during tickless idle\n * calculations. */\n#define portMISSED_COUNTS_FACTOR              ( 94UL )\n\n/* For strict compliance with the Cortex-M spec the task start address should\n * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */\n#define portSTART_ADDRESS_MASK                ( ( StackType_t ) 0xfffffffeUL )\n\n/* Let the user override the default SysTick clock rate.  If defined by the\n * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the\n * configuration register. */\n#ifndef configSYSTICK_CLOCK_HZ\n    #define configSYSTICK_CLOCK_HZ             ( configCPU_CLOCK_HZ )\n    /* Ensure the SysTick is clocked at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( portNVIC_SYSTICK_CLK_BIT )\n#else\n    /* Select the option to clock SysTick not at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( 0 )\n#endif\n\n/*\n * Setup the timer to generate the tick interrupts.  The implementation in this\n * file is weak to allow application writers to change the timer used to\n * generate the tick interrupt.\n */\nvoid vPortSetupTimerInterrupt( void );\n\n/*\n * Exception handlers.\n */\nvoid xPortSysTickHandler( void );\n\n/*\n * Start first task is a separate function so it can be tested in isolation.\n */\nextern void vPortStartFirstTask( void );\n\n/*\n * Turn the VFP on.\n */\nextern void vPortEnableVFP( void );\n\n/*\n * Used to catch tasks that attempt to return from their implementing function.\n */\nstatic void prvTaskExitError( void );\n\n/*-----------------------------------------------------------*/\n\n/* Each task maintains its own interrupt status in the critical nesting\n * variable. */\nstatic UBaseType_t uxCriticalNesting = 0xaaaaaaaa;\n\n/*\n * The number of SysTick increments that make up one tick period.\n */\n#if ( configUSE_TICKLESS_IDLE == 1 )\n    static uint32_t ulTimerCountsForOneTick = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n\n/*\n * The maximum number of tick periods that can be suppressed is limited by the\n * 24 bit resolution of the SysTick timer.\n */\n#if ( configUSE_TICKLESS_IDLE == 1 )\n    static uint32_t xMaximumPossibleSuppressedTicks = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n\n/*\n * Compensate for the CPU cycles that pass while the SysTick is stopped (low\n * power functionality only.\n */\n#if ( configUSE_TICKLESS_IDLE == 1 )\n    static uint32_t ulStoppedTimerCompensation = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n\n/*\n * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure\n * FreeRTOS API functions are not called from interrupts that have been assigned\n * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.\n */\n#if ( configASSERT_DEFINED == 1 )\n    static uint8_t ucMaxSysCallPriority = 0;\n    static uint32_t ulMaxPRIGROUPValue = 0;\n    static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;\n#endif /* configASSERT_DEFINED */\n\n/*-----------------------------------------------------------*/\n\n/*\n * See header file for description.\n */\nStackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,\n                                     TaskFunction_t pxCode,\n                                     void * pvParameters )\n{\n    /* Simulate the stack frame as it would be created by a context switch\n     * interrupt. */\n\n    /* Offset added to account for the way the MCU uses the stack on entry/exit\n     * of interrupts, and to ensure alignment. */\n    pxTopOfStack--;\n\n    *pxTopOfStack = portINITIAL_XPSR;                                    /* xPSR */\n    pxTopOfStack--;\n    *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */\n    pxTopOfStack--;\n    *pxTopOfStack = ( StackType_t ) prvTaskExitError;                    /* LR */\n\n    /* Save code space by skipping register initialisation. */\n    pxTopOfStack -= 5;                            /* R12, R3, R2 and R1. */\n    *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\n\n    /* A save method is being used that requires each task to maintain its\n     * own exec return value. */\n    pxTopOfStack--;\n    *pxTopOfStack = portINITIAL_EXC_RETURN;\n\n    pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */\n\n    return pxTopOfStack;\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvTaskExitError( void )\n{\n    /* A function that implements a task must not exit or attempt to return to\n     * its caller as there is nothing to return to.  If a task wants to exit it\n     * should instead call vTaskDelete( NULL ).\n     *\n     * Artificially force an assert() to be triggered if configASSERT() is\n     * defined, then stop here so application writers can catch the error. */\n    configASSERT( uxCriticalNesting == ~0UL );\n    portDISABLE_INTERRUPTS();\n\n    for( ; ; )\n    {\n    }\n}\n/*-----------------------------------------------------------*/\n\n/*\n * See header file for description.\n */\nBaseType_t xPortStartScheduler( void )\n{\n    /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.\n     * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\n    configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );\n\n    #if ( configASSERT_DEFINED == 1 )\n    {\n        volatile uint32_t ulOriginalPriority;\n        volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\n        volatile uint8_t ucMaxPriorityValue;\n\n        /* Determine the maximum priority from which ISR safe FreeRTOS API\n         * functions can be called.  ISR safe functions are those that end in\n         * \"FromISR\".  FreeRTOS maintains separate thread and ISR API functions to\n         * ensure interrupt entry is as fast and simple as possible.\n         *\n         * Save the interrupt priority value that is about to be clobbered. */\n        ulOriginalPriority = *pucFirstUserPriorityRegister;\n\n        /* Determine the number of priority bits available.  First write to all\n         * possible bits. */\n        *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\n\n        /* Read the value back to see how many bits stuck. */\n        ucMaxPriorityValue = *pucFirstUserPriorityRegister;\n\n        /* Use the same mask on the maximum system call priority. */\n        ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;\n\n        /* Calculate the maximum acceptable priority group value for the number\n         * of bits read back. */\n        ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;\n\n        while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )\n        {\n            ulMaxPRIGROUPValue--;\n            ucMaxPriorityValue <<= ( uint8_t ) 0x01;\n        }\n\n        #ifdef __NVIC_PRIO_BITS\n        {\n            /* Check the CMSIS configuration that defines the number of\n             * priority bits matches the number of priority bits actually queried\n             * from the hardware. */\n            configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );\n        }\n        #endif\n\n        #ifdef configPRIO_BITS\n        {\n            /* Check the FreeRTOS configuration that defines the number of\n             * priority bits matches the number of priority bits actually queried\n             * from the hardware. */\n            configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );\n        }\n        #endif\n\n        /* Shift the priority group value back to its position within the AIRCR\n         * register. */\n        ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;\n        ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;\n\n        /* Restore the clobbered interrupt priority register to its original\n         * value. */\n        *pucFirstUserPriorityRegister = ulOriginalPriority;\n    }\n    #endif /* configASSERT_DEFINED */\n\n    /* Make PendSV and SysTick the lowest priority interrupts. */\n    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;\n    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;\n\n    /* Start the timer that generates the tick ISR.  Interrupts are disabled\n     * here already. */\n    vPortSetupTimerInterrupt();\n\n    /* Initialise the critical nesting count ready for the first task. */\n    uxCriticalNesting = 0;\n\n    /* Ensure the VFP is enabled - it should be anyway. */\n    vPortEnableVFP();\n\n    /* Lazy save always. */\n    *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;\n\n    /* Start the first task. */\n    vPortStartFirstTask();\n\n    /* Should not get here! */\n    return 0;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEndScheduler( void )\n{\n    /* Not implemented in ports where there is nothing to return to.\n     * Artificially force an assert. */\n    configASSERT( uxCriticalNesting == 1000UL );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEnterCritical( void )\n{\n    portDISABLE_INTERRUPTS();\n    uxCriticalNesting++;\n\n    /* This is not the interrupt safe version of the enter critical function so\n     * assert() if it is being called from an interrupt context.  Only API\n     * functions that end in \"FromISR\" can be used in an interrupt.  Only assert if\n     * the critical nesting count is 1 to protect against recursive calls if the\n     * assert function also uses a critical section. */\n    if( uxCriticalNesting == 1 )\n    {\n        configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );\n    }\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortExitCritical( void )\n{\n    configASSERT( uxCriticalNesting );\n    uxCriticalNesting--;\n\n    if( uxCriticalNesting == 0 )\n    {\n        portENABLE_INTERRUPTS();\n    }\n}\n/*-----------------------------------------------------------*/\n\nvoid xPortSysTickHandler( void )\n{\n    /* The SysTick runs at the lowest interrupt priority, so when this interrupt\n     * executes all interrupts must be unmasked.  There is therefore no need to\n     * save and then restore the interrupt mask value as its value is already\n     * known. */\n    portDISABLE_INTERRUPTS();\n    {\n        /* Increment the RTOS tick. */\n        if( xTaskIncrementTick() != pdFALSE )\n        {\n            /* A context switch is required.  Context switching is performed in\n             * the PendSV interrupt.  Pend the PendSV interrupt. */\n            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\n        }\n    }\n    portENABLE_INTERRUPTS();\n}\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TICKLESS_IDLE == 1 )\n\n    __weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )\n    {\n        uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;\n        TickType_t xModifiableIdleTime;\n\n        /* Make sure the SysTick reload value does not overflow the counter. */\n        if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\n        {\n            xExpectedIdleTime = xMaximumPossibleSuppressedTicks;\n        }\n\n        /* Enter a critical section but don't use the taskENTER_CRITICAL()\n         * method as that will mask interrupts that should exit sleep mode. */\n        __disable_interrupt();\n        __DSB();\n        __ISB();\n\n        /* If a context switch is pending or a task is waiting for the scheduler\n         * to be unsuspended then abandon the low power entry. */\n        if( eTaskConfirmSleepModeStatus() == eAbortSleep )\n        {\n            /* Re-enable interrupts - see comments above the __disable_interrupt()\n             * call above. */\n            __enable_interrupt();\n        }\n        else\n        {\n            /* Stop the SysTick momentarily.  The time the SysTick is stopped for\n             * is accounted for as best it can be, but using the tickless mode will\n             * inevitably result in some tiny drift of the time maintained by the\n             * kernel with respect to calendar time. */\n            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );\n\n            /* Use the SysTick current-value register to determine the number of\n             * SysTick decrements remaining until the next tick interrupt.  If the\n             * current-value register is zero, then there are actually\n             * ulTimerCountsForOneTick decrements remaining, not zero, because the\n             * SysTick requests the interrupt when decrementing from 1 to 0. */\n            ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n\n            if( ulSysTickDecrementsLeft == 0 )\n            {\n                ulSysTickDecrementsLeft = ulTimerCountsForOneTick;\n            }\n\n            /* Calculate the reload value required to wait xExpectedIdleTime\n             * tick periods.  -1 is used because this code normally executes part\n             * way through the first tick period.  But if the SysTick IRQ is now\n             * pending, then clear the IRQ, suppressing the first tick, and correct\n             * the reload value to reflect that the second tick period is already\n             * underway.  The expected idle time is always at least two ticks. */\n            ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );\n\n            if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )\n            {\n                portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;\n                ulReloadValue -= ulTimerCountsForOneTick;\n            }\n\n            if( ulReloadValue > ulStoppedTimerCompensation )\n            {\n                ulReloadValue -= ulStoppedTimerCompensation;\n            }\n\n            /* Set the new reload value. */\n            portNVIC_SYSTICK_LOAD_REG = ulReloadValue;\n\n            /* Clear the SysTick count flag and set the count value back to\n             * zero. */\n            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n            /* Restart SysTick. */\n            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\n\n            /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can\n             * set its parameter to 0 to indicate that its implementation contains\n             * its own wait for interrupt or wait for event instruction, and so wfi\n             * should not be executed again.  However, the original expected idle\n             * time variable must remain unmodified, so a copy is taken. */\n            xModifiableIdleTime = xExpectedIdleTime;\n            configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\n\n            if( xModifiableIdleTime > 0 )\n            {\n                __DSB();\n                __WFI();\n                __ISB();\n            }\n\n            configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\n\n            /* Re-enable interrupts to allow the interrupt that brought the MCU\n             * out of sleep mode to execute immediately.  See comments above\n             * the __disable_interrupt() call above. */\n            __enable_interrupt();\n            __DSB();\n            __ISB();\n\n            /* Disable interrupts again because the clock is about to be stopped\n             * and interrupts that execute while the clock is stopped will increase\n             * any slippage between the time maintained by the RTOS and calendar\n             * time. */\n            __disable_interrupt();\n            __DSB();\n            __ISB();\n\n            /* Disable the SysTick clock without reading the\n             * portNVIC_SYSTICK_CTRL_REG register to ensure the\n             * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,\n             * the time the SysTick is stopped for is accounted for as best it can\n             * be, but using the tickless mode will inevitably result in some tiny\n             * drift of the time maintained by the kernel with respect to calendar\n             * time*/\n            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );\n\n            /* Determine whether the SysTick has already counted to zero. */\n            if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n            {\n                uint32_t ulCalculatedLoadValue;\n\n                /* The tick interrupt ended the sleep (or is now pending), and\n                 * a new tick period has started.  Reset portNVIC_SYSTICK_LOAD_REG\n                 * with whatever remains of the new tick period. */\n                ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\n\n                /* Don't allow a tiny value, or values that have somehow\n                 * underflowed because the post sleep hook did something\n                 * that took too long or because the SysTick current-value register\n                 * is zero. */\n                if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )\n                {\n                    ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );\n                }\n\n                portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;\n\n                /* As the pending tick will be processed as soon as this\n                 * function exits, the tick value maintained by the tick is stepped\n                 * forward by one less than the time spent waiting. */\n                ulCompleteTickPeriods = xExpectedIdleTime - 1UL;\n            }\n            else\n            {\n                /* Something other than the tick interrupt ended the sleep. */\n\n                /* Use the SysTick current-value register to determine the\n                 * number of SysTick decrements remaining until the expected idle\n                 * time would have ended. */\n                ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n                #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )\n                {\n                    /* If the SysTick is not using the core clock, the current-\n                     * value register might still be zero here.  In that case, the\n                     * SysTick didn't load from the reload register, and there are\n                     * ulReloadValue decrements remaining in the expected idle\n                     * time, not zero. */\n                    if( ulSysTickDecrementsLeft == 0 )\n                    {\n                        ulSysTickDecrementsLeft = ulReloadValue;\n                    }\n                }\n                #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */\n\n                /* Work out how long the sleep lasted rounded to complete tick\n                 * periods (not the ulReload value which accounted for part\n                 * ticks). */\n                ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;\n\n                /* How many complete tick periods passed while the processor\n                 * was waiting? */\n                ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;\n\n                /* The reload value is set to whatever fraction of a single tick\n                 * period remains. */\n                portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;\n            }\n\n            /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,\n             * then set portNVIC_SYSTICK_LOAD_REG back to its standard value.  If\n             * the SysTick is not using the core clock, temporarily configure it to\n             * use the core clock.  This configuration forces the SysTick to load\n             * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next\n             * cycle of the other clock.  Then portNVIC_SYSTICK_LOAD_REG is ready\n             * to receive the standard value immediately. */\n            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n            portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n            #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )\n            {\n                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n            }\n            #else\n            {\n                /* The temporary usage of the core clock has served its purpose,\n                 * as described above.  Resume usage of the other clock. */\n                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\n\n                if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n                {\n                    /* The partial tick period already ended.  Be sure the SysTick\n                     * counts it only once. */\n                    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;\n                }\n\n                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n            }\n            #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */\n\n            /* Step the tick to account for any tick periods that elapsed. */\n            vTaskStepTick( ulCompleteTickPeriods );\n\n            /* Exit with interrupts enabled. */\n            __enable_interrupt();\n        }\n    }\n\n#endif /* configUSE_TICKLESS_IDLE */\n/*-----------------------------------------------------------*/\n\n/*\n * Setup the systick timer to generate the tick interrupts at the required\n * frequency.\n */\n__weak void vPortSetupTimerInterrupt( void )\n{\n    /* Calculate the constants required to configure the tick interrupt. */\n    #if ( configUSE_TICKLESS_IDLE == 1 )\n    {\n        ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );\n        xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;\n        ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\n    }\n    #endif /* configUSE_TICKLESS_IDLE */\n\n    /* Stop and clear the SysTick. */\n    portNVIC_SYSTICK_CTRL_REG = 0UL;\n    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n    /* Configure SysTick to interrupt at the requested rate. */\n    portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\n    portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );\n}\n/*-----------------------------------------------------------*/\n\n#if ( configASSERT_DEFINED == 1 )\n\n    void vPortValidateInterruptPriority( void )\n    {\n        uint32_t ulCurrentInterrupt;\n        uint8_t ucCurrentPriority;\n\n        /* Obtain the number of the currently executing interrupt. */\n        __asm volatile ( \"mrs %0, ipsr\" : \"=r\" ( ulCurrentInterrupt )::\"memory\" );\n\n        /* Is the interrupt number a user defined interrupt? */\n        if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )\n        {\n            /* Look up the interrupt's priority. */\n            ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];\n\n            /* The following assertion will fail if a service routine (ISR) for\n             * an interrupt that has been assigned a priority above\n             * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\n             * function.  ISR safe FreeRTOS API functions must *only* be called\n             * from interrupts that have been assigned a priority at or below\n             * configMAX_SYSCALL_INTERRUPT_PRIORITY.\n             *\n             * Numerically low interrupt priority numbers represent logically high\n             * interrupt priorities, therefore the priority of the interrupt must\n             * be set to a value equal to or numerically *higher* than\n             * configMAX_SYSCALL_INTERRUPT_PRIORITY.\n             *\n             * Interrupts that\tuse the FreeRTOS API must not be left at their\n             * default priority of\tzero as that is the highest possible priority,\n             * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,\n             * and\ttherefore also guaranteed to be invalid.\n             *\n             * FreeRTOS maintains separate thread and ISR API functions to ensure\n             * interrupt entry is as fast and simple as possible.\n             *\n             * The following links provide detailed information:\n             * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html\n             * https://www.FreeRTOS.org/FAQHelp.html */\n            configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );\n        }\n\n        /* Priority grouping:  The interrupt controller (NVIC) allows the bits\n         * that define each interrupt's priority to be split between bits that\n         * define the interrupt's pre-emption priority bits and bits that define\n         * the interrupt's sub-priority.  For simplicity all bits must be defined\n         * to be pre-emption priority bits.  The following assertion will fail if\n         * this is not the case (if some bits represent a sub-priority).\n         *\n         * If the application only uses CMSIS libraries for interrupt\n         * configuration then the correct setting can be achieved on all Cortex-M\n         * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the\n         * scheduler.  Note however that some vendor specific peripheral libraries\n         * assume a non-zero priority group setting, in which cases using a value\n         * of zero will result in unpredictable behaviour. */\n        configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );\n    }\n\n#endif /* configASSERT_DEFINED */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM7/r0p1/portasm.s",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#include <FreeRTOSConfig.h>\n\n\tRSEG    CODE:CODE(2)\n\tthumb\n\n\tEXTERN pxCurrentTCB\n\tEXTERN vTaskSwitchContext\n\n\tPUBLIC xPortPendSVHandler\n\tPUBLIC vPortSVCHandler\n\tPUBLIC vPortStartFirstTask\n\tPUBLIC vPortEnableVFP\n\n\n/*-----------------------------------------------------------*/\n\nxPortPendSVHandler:\n\tmrs r0, psp\n\tisb\n\t/* Get the location of the current TCB. */\n\tldr\tr3, =pxCurrentTCB\n\tldr\tr2, [r3]\n\n\t/* Is the task using the FPU context?  If so, push high vfp registers. */\n\ttst r14, #0x10\n\tit eq\n\tvstmdbeq r0!, {s16-s31}\n\n\t/* Save the core registers. */\n\tstmdb r0!, {r4-r11, r14}\n\n\t/* Save the new top of stack into the first member of the TCB. */\n\tstr r0, [r2]\n\n\tstmdb sp!, {r0, r3}\n\tmov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY\n\tcpsid i\n\tmsr basepri, r0\n\tdsb\n\tisb\n\tcpsie i\n\tbl vTaskSwitchContext\n\tmov r0, #0\n\tmsr basepri, r0\n\tldmia sp!, {r0, r3}\n\n\t/* The first item in pxCurrentTCB is the task top of stack. */\n\tldr r1, [r3]\n\tldr r0, [r1]\n\n\t/* Pop the core registers. */\n\tldmia r0!, {r4-r11, r14}\n\n\t/* Is the task using the FPU context?  If so, pop the high vfp registers\n\ttoo. */\n\ttst r14, #0x10\n\tit eq\n\tvldmiaeq r0!, {s16-s31}\n\n\tmsr psp, r0\n\tisb\n\t#ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata */\n\t\t#if WORKAROUND_PMU_CM001 == 1\n\t\t\tpush { r14 }\n\t\t\tpop { pc }\n\t\t#endif\n\t#endif\n\n\tbx r14\n\n\n/*-----------------------------------------------------------*/\n\nvPortSVCHandler:\n\t/* Get the location of the current TCB. */\n\tldr\tr3, =pxCurrentTCB\n\tldr r1, [r3]\n\tldr r0, [r1]\n\t/* Pop the core registers. */\n\tldmia r0!, {r4-r11, r14}\n\tmsr psp, r0\n\tisb\n\tmov r0, #0\n\tmsr\tbasepri, r0\n\tbx r14\n\n/*-----------------------------------------------------------*/\n\nvPortStartFirstTask\n\t/* Use the NVIC offset register to locate the stack. */\n\tldr r0, =0xE000ED08\n\tldr r0, [r0]\n\tldr r0, [r0]\n\t/* Set the msp back to the start of the stack. */\n\tmsr msp, r0\n\t/* Clear the bit that indicates the FPU is in use in case the FPU was used\n\tbefore the scheduler was started - which would otherwise result in the\n\tunnecessary leaving of space in the SVC stack for lazy saving of FPU\n\tregisters. */\n\tmov r0, #0\n\tmsr control, r0\n\t/* Call SVC to start the first task. */\n\tcpsie i\n\tcpsie f\n\tdsb\n\tisb\n\tsvc 0\n\n/*-----------------------------------------------------------*/\n\nvPortEnableVFP:\n\t/* The FPU enable bits are in the CPACR. */\n\tldr.w r0, =0xE000ED88\n\tldr\tr1, [r0]\n\n\t/* Enable CP10 and CP11 coprocessors, then save back. */\n\torr\tr1, r1, #( 0xf << 20 )\n\tstr r1, [r0]\n\tbx\tr14\n\n\n\n\tEND\n\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM7/r0p1/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef PORTMACRO_H\n    #define PORTMACRO_H\n\n    #ifdef __cplusplus\n        extern \"C\" {\n    #endif\n\n/*-----------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the\n * given hardware and compiler.\n *\n * These settings should not be altered.\n *-----------------------------------------------------------\n */\n\n/* IAR includes. */\n    #include <intrinsics.h>\n\n/* Type definitions. */\n    #define portCHAR          char\n    #define portFLOAT         float\n    #define portDOUBLE        double\n    #define portLONG          long\n    #define portSHORT         short\n    #define portSTACK_TYPE    uint32_t\n    #define portBASE_TYPE     long\n\n    typedef portSTACK_TYPE   StackType_t;\n    typedef long             BaseType_t;\n    typedef unsigned long    UBaseType_t;\n\n    #if ( configUSE_16_BIT_TICKS == 1 )\n        typedef uint16_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffff\n    #else\n        typedef uint32_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL\n\n/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\n * not need to be guarded with a critical section. */\n        #define portTICK_TYPE_IS_ATOMIC    1\n    #endif\n/*-----------------------------------------------------------*/\n\n/* Architecture specifics. */\n    #define portSTACK_GROWTH      ( -1 )\n    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\n    #define portBYTE_ALIGNMENT    8\n/*-----------------------------------------------------------*/\n\n/* Compiler directives. */\n    #define portWEAK_SYMBOL    __attribute__( ( weak ) )\n\n/*-----------------------------------------------------------*/\n\n\n/* Scheduler utilities. */\n    #define portYIELD()                                 \\\n    {                                                   \\\n        /* Set a PendSV to request a context switch. */ \\\n        portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \\\n        __DSB();                                        \\\n        __ISB();                                        \\\n    }\n\n    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )\n    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )\n    #define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 )\n    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )\n\n/*-----------------------------------------------------------*/\n\n/* Architecture specific optimisations. */\n    #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION\n        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1\n    #endif\n\n    #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )\n\n/* Check the configuration. */\n        #if ( configMAX_PRIORITIES > 32 )\n            #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.\n        #endif\n\n/* Store/clear the ready priorities in a bit map. */\n        #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )\n        #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )\n\n/*-----------------------------------------------------------*/\n\n        #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ( ( uint32_t ) __CLZ( ( uxReadyPriorities ) ) ) )\n\n    #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */\n/*-----------------------------------------------------------*/\n\n/* Critical section management. */\n    extern void vPortEnterCritical( void );\n    extern void vPortExitCritical( void );\n\n    #define portDISABLE_INTERRUPTS()                           \\\n    {                                                          \\\n        /* Errata work around. */                              \\\n        __disable_interrupt();                                 \\\n        __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \\\n        __DSB();                                               \\\n        __ISB();                                               \\\n        __enable_interrupt();                                  \\\n    }\n\n    #define portENABLE_INTERRUPTS()                   __set_BASEPRI( 0 )\n    #define portENTER_CRITICAL()                      vPortEnterCritical()\n    #define portEXIT_CRITICAL()                       vPortExitCritical()\n    #define portSET_INTERRUPT_MASK_FROM_ISR()         __get_BASEPRI(); portDISABLE_INTERRUPTS()\n    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    __set_BASEPRI( x )\n/*-----------------------------------------------------------*/\n\n/* Tickless idle/low power functionality. */\n    #ifndef portSUPPRESS_TICKS_AND_SLEEP\n        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );\n        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )\n    #endif\n\n/*-----------------------------------------------------------*/\n\n/* Task function macros as described on the FreeRTOS.org WEB site.  These are\n * not necessary for to use this port.  They are defined so the common demo files\n * (which build with all the ports) will build. */\n    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )\n    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )\n/*-----------------------------------------------------------*/\n\n    #ifdef configASSERT\n        void vPortValidateInterruptPriority( void );\n        #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()\n    #endif\n\n/* portNOP() is not required by this port. */\n    #define portNOP()\n\n    #define portINLINE              __inline\n\n    #ifndef portFORCE_INLINE\n        #define portFORCE_INLINE    inline __attribute__( ( always_inline ) )\n    #endif\n\n/*-----------------------------------------------------------*/\n\n    portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )\n    {\n        uint32_t ulCurrentInterrupt;\n        BaseType_t xReturn;\n\n        /* Obtain the number of the currently executing interrupt. */\n        __asm volatile ( \"mrs %0, ipsr\" : \"=r\" ( ulCurrentInterrupt )::\"memory\" );\n\n        if( ulCurrentInterrupt == 0 )\n        {\n            xReturn = pdFALSE;\n        }\n        else\n        {\n            xReturn = pdTRUE;\n        }\n\n        return xReturn;\n    }\n\n/*-----------------------------------------------------------*/\n\n/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in\n * the source code because to do so would cause other compilers to generate\n * warnings. */\n    #pragma diag_suppress=Pe191\n    #pragma diag_suppress=Pa082\n\n    #ifdef __cplusplus\n        }\n    #endif\n\n#endif /* PORTMACRO_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM85/non_secure/port.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\n * all the API functions to use the MPU wrappers. That should only be done when\n * task.h is included from an application file. */\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n/* MPU wrappers includes. */\n#include \"mpu_wrappers.h\"\n\n/* Portasm includes. */\n#include \"portasm.h\"\n\n#if ( configENABLE_TRUSTZONE == 1 )\n    /* Secure components includes. */\n    #include \"secure_context.h\"\n    #include \"secure_init.h\"\n#endif /* configENABLE_TRUSTZONE */\n\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/**\n * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only\n * i.e. the processor boots as secure and never jumps to the non-secure side.\n * The Trust Zone support in the port must be disabled in order to run FreeRTOS\n * on the secure side. The following are the valid configuration seetings:\n *\n * 1. Run FreeRTOS on the Secure Side:\n *    configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0\n *\n * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:\n *    configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1\n *\n * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:\n *    configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0\n */\n#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )\n    #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.\n#endif\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the NVIC.\n */\n#define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )\n#define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )\n#define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )\n#define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )\n#define portNVIC_SYSTICK_ENABLE_BIT           ( 1UL << 0UL )\n#define portNVIC_SYSTICK_INT_BIT              ( 1UL << 1UL )\n#define portNVIC_SYSTICK_CLK_BIT              ( 1UL << 2UL )\n#define portNVIC_SYSTICK_COUNT_FLAG_BIT       ( 1UL << 16UL )\n#define portNVIC_PEND_SYSTICK_CLEAR_BIT       ( 1UL << 25UL )\n#define portNVIC_PEND_SYSTICK_SET_BIT         ( 1UL << 26UL )\n#define portMIN_INTERRUPT_PRIORITY            ( 255UL )\n#define portNVIC_PENDSV_PRI                   ( portMIN_INTERRUPT_PRIORITY << 16UL )\n#define portNVIC_SYSTICK_PRI                  ( portMIN_INTERRUPT_PRIORITY << 24UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the SCB.\n */\n#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( volatile uint32_t * ) 0xe000ed24 )\n#define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the FPU.\n */\n#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 )              /* Coprocessor Access Control Register. */\n#define portCPACR_CP10_VALUE    ( 3UL )\n#define portCPACR_CP11_VALUE    portCPACR_CP10_VALUE\n#define portCPACR_CP10_POS      ( 20UL )\n#define portCPACR_CP11_POS      ( 22UL )\n\n#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 )              /* Floating Point Context Control Register. */\n#define portFPCCR_ASPEN_POS     ( 31UL )\n#define portFPCCR_ASPEN_MASK    ( 1UL << portFPCCR_ASPEN_POS )\n#define portFPCCR_LSPEN_POS     ( 30UL )\n#define portFPCCR_LSPEN_MASK    ( 1UL << portFPCCR_LSPEN_POS )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the MPU.\n */\n#define portMPU_TYPE_REG                      ( *( ( volatile uint32_t * ) 0xe000ed90 ) )\n#define portMPU_CTRL_REG                      ( *( ( volatile uint32_t * ) 0xe000ed94 ) )\n#define portMPU_RNR_REG                       ( *( ( volatile uint32_t * ) 0xe000ed98 ) )\n\n#define portMPU_RBAR_REG                      ( *( ( volatile uint32_t * ) 0xe000ed9c ) )\n#define portMPU_RLAR_REG                      ( *( ( volatile uint32_t * ) 0xe000eda0 ) )\n\n#define portMPU_RBAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda4 ) )\n#define portMPU_RLAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda8 ) )\n\n#define portMPU_RBAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edac ) )\n#define portMPU_RLAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edb0 ) )\n\n#define portMPU_RBAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb4 ) )\n#define portMPU_RLAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb8 ) )\n\n#define portMPU_MAIR0_REG                     ( *( ( volatile uint32_t * ) 0xe000edc0 ) )\n#define portMPU_MAIR1_REG                     ( *( ( volatile uint32_t * ) 0xe000edc4 ) )\n\n#define portMPU_RBAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */\n#define portMPU_RLAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */\n\n#define portMPU_MAIR_ATTR0_POS                ( 0UL )\n#define portMPU_MAIR_ATTR0_MASK               ( 0x000000ff )\n\n#define portMPU_MAIR_ATTR1_POS                ( 8UL )\n#define portMPU_MAIR_ATTR1_MASK               ( 0x0000ff00 )\n\n#define portMPU_MAIR_ATTR2_POS                ( 16UL )\n#define portMPU_MAIR_ATTR2_MASK               ( 0x00ff0000 )\n\n#define portMPU_MAIR_ATTR3_POS                ( 24UL )\n#define portMPU_MAIR_ATTR3_MASK               ( 0xff000000 )\n\n#define portMPU_MAIR_ATTR4_POS                ( 0UL )\n#define portMPU_MAIR_ATTR4_MASK               ( 0x000000ff )\n\n#define portMPU_MAIR_ATTR5_POS                ( 8UL )\n#define portMPU_MAIR_ATTR5_MASK               ( 0x0000ff00 )\n\n#define portMPU_MAIR_ATTR6_POS                ( 16UL )\n#define portMPU_MAIR_ATTR6_MASK               ( 0x00ff0000 )\n\n#define portMPU_MAIR_ATTR7_POS                ( 24UL )\n#define portMPU_MAIR_ATTR7_MASK               ( 0xff000000 )\n\n#define portMPU_RLAR_ATTR_INDEX0              ( 0UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX1              ( 1UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX2              ( 2UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX3              ( 3UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX4              ( 4UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX5              ( 5UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX6              ( 6UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX7              ( 7UL << 1UL )\n\n#define portMPU_RLAR_REGION_ENABLE            ( 1UL )\n\n/* Enable privileged access to unmapped region. */\n#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )\n\n/* Enable MPU. */\n#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )\n\n/* Expected value of the portMPU_TYPE register. */\n#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief The maximum 24-bit number.\n *\n * It is needed because the systick is a 24-bit counter.\n */\n#define portMAX_24_BIT_NUMBER       ( 0xffffffUL )\n\n/**\n * @brief A fiddle factor to estimate the number of SysTick counts that would\n * have occurred while the SysTick counter is stopped during tickless idle\n * calculations.\n */\n#define portMISSED_COUNTS_FACTOR    ( 94UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to set up the initial stack.\n */\n#define portINITIAL_XPSR    ( 0x01000000 )\n\n#if ( configRUN_FREERTOS_SECURE_ONLY == 1 )\n\n/**\n * @brief Initial EXC_RETURN value.\n *\n *     FF         FF         FF         FD\n * 1111 1111  1111 1111  1111 1111  1111 1101\n *\n * Bit[6] - 1 --> The exception was taken from the Secure state.\n * Bit[5] - 1 --> Do not skip stacking of additional state context.\n * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\n * Bit[3] - 1 --> Return to the Thread mode.\n * Bit[2] - 1 --> Restore registers from the process stack.\n * Bit[1] - 0 --> Reserved, 0.\n * Bit[0] - 1 --> The exception was taken to the Secure state.\n */\n    #define portINITIAL_EXC_RETURN    ( 0xfffffffd )\n#else\n\n/**\n * @brief Initial EXC_RETURN value.\n *\n *     FF         FF         FF         BC\n * 1111 1111  1111 1111  1111 1111  1011 1100\n *\n * Bit[6] - 0 --> The exception was taken from the Non-Secure state.\n * Bit[5] - 1 --> Do not skip stacking of additional state context.\n * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\n * Bit[3] - 1 --> Return to the Thread mode.\n * Bit[2] - 1 --> Restore registers from the process stack.\n * Bit[1] - 0 --> Reserved, 0.\n * Bit[0] - 0 --> The exception was taken to the Non-Secure state.\n */\n    #define portINITIAL_EXC_RETURN    ( 0xffffffbc )\n#endif /* configRUN_FREERTOS_SECURE_ONLY */\n\n/**\n * @brief CONTROL register privileged bit mask.\n *\n * Bit[0] in CONTROL register tells the privilege:\n *  Bit[0] = 0 ==> The task is privileged.\n *  Bit[0] = 1 ==> The task is not privileged.\n */\n#define portCONTROL_PRIVILEGED_MASK         ( 1UL << 0UL )\n\n/**\n * @brief Initial CONTROL register values.\n */\n#define portINITIAL_CONTROL_UNPRIVILEGED    ( 0x3 )\n#define portINITIAL_CONTROL_PRIVILEGED      ( 0x2 )\n\n/**\n * @brief Let the user override the default SysTick clock rate.  If defined by the\n * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the\n * configuration register.\n */\n#ifndef configSYSTICK_CLOCK_HZ\n    #define configSYSTICK_CLOCK_HZ             ( configCPU_CLOCK_HZ )\n    /* Ensure the SysTick is clocked at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( portNVIC_SYSTICK_CLK_BIT )\n#else\n    /* Select the option to clock SysTick not at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( 0 )\n#endif\n\n/**\n * @brief Let the user override the pre-loading of the initial LR with the\n * address of prvTaskExitError() in case it messes up unwinding of the stack\n * in the debugger.\n */\n#ifdef configTASK_RETURN_ADDRESS\n    #define portTASK_RETURN_ADDRESS    configTASK_RETURN_ADDRESS\n#else\n    #define portTASK_RETURN_ADDRESS    prvTaskExitError\n#endif\n\n/**\n * @brief If portPRELOAD_REGISTERS then registers will be given an initial value\n * when a task is created. This helps in debugging at the cost of code size.\n */\n#define portPRELOAD_REGISTERS    1\n\n/**\n * @brief A task is created without a secure context, and must call\n * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes\n * any secure calls.\n */\n#define portNO_SECURE_CONTEXT    0\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Used to catch tasks that attempt to return from their implementing\n * function.\n */\nstatic void prvTaskExitError( void );\n\n#if ( configENABLE_MPU == 1 )\n\n/**\n * @brief Setup the Memory Protection Unit (MPU).\n */\n    static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\n#endif /* configENABLE_MPU */\n\n#if ( configENABLE_FPU == 1 )\n\n/**\n * @brief Setup the Floating Point Unit (FPU).\n */\n    static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;\n#endif /* configENABLE_FPU */\n\n/**\n * @brief Setup the timer to generate the tick interrupts.\n *\n * The implementation in this file is weak to allow application writers to\n * change the timer used to generate the tick interrupt.\n */\nvoid vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Checks whether the current execution context is interrupt.\n *\n * @return pdTRUE if the current execution context is interrupt, pdFALSE\n * otherwise.\n */\nBaseType_t xPortIsInsideInterrupt( void );\n\n/**\n * @brief Yield the processor.\n */\nvoid vPortYield( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Enter critical section.\n */\nvoid vPortEnterCritical( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Exit from critical section.\n */\nvoid vPortExitCritical( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief SysTick handler.\n */\nvoid SysTick_Handler( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief C part of SVC handler.\n */\nportDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION;\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Each task maintains its own interrupt status in the critical nesting\n * variable.\n */\nPRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;\n\n#if ( configENABLE_TRUSTZONE == 1 )\n\n/**\n * @brief Saved as part of the task context to indicate which context the\n * task is using on the secure side.\n */\n    PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;\n#endif /* configENABLE_TRUSTZONE */\n\n#if ( configUSE_TICKLESS_IDLE == 1 )\n\n/**\n * @brief The number of SysTick increments that make up one tick period.\n */\n    PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0;\n\n/**\n * @brief The maximum number of tick periods that can be suppressed is\n * limited by the 24 bit resolution of the SysTick timer.\n */\n    PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0;\n\n/**\n * @brief Compensate for the CPU cycles that pass while the SysTick is\n * stopped (low power functionality only).\n */\n    PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TICKLESS_IDLE == 1 )\n    __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )\n    {\n        uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;\n        TickType_t xModifiableIdleTime;\n\n        /* Make sure the SysTick reload value does not overflow the counter. */\n        if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\n        {\n            xExpectedIdleTime = xMaximumPossibleSuppressedTicks;\n        }\n\n        /* Enter a critical section but don't use the taskENTER_CRITICAL()\n         * method as that will mask interrupts that should exit sleep mode. */\n        __asm volatile ( \"cpsid i\" ::: \"memory\" );\n        __asm volatile ( \"dsb\" );\n        __asm volatile ( \"isb\" );\n\n        /* If a context switch is pending or a task is waiting for the scheduler\n         * to be unsuspended then abandon the low power entry. */\n        if( eTaskConfirmSleepModeStatus() == eAbortSleep )\n        {\n            /* Re-enable interrupts - see comments above the cpsid instruction\n             * above. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n        }\n        else\n        {\n            /* Stop the SysTick momentarily.  The time the SysTick is stopped for\n             * is accounted for as best it can be, but using the tickless mode will\n             * inevitably result in some tiny drift of the time maintained by the\n             * kernel with respect to calendar time. */\n            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );\n\n            /* Use the SysTick current-value register to determine the number of\n             * SysTick decrements remaining until the next tick interrupt.  If the\n             * current-value register is zero, then there are actually\n             * ulTimerCountsForOneTick decrements remaining, not zero, because the\n             * SysTick requests the interrupt when decrementing from 1 to 0. */\n            ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n\n            if( ulSysTickDecrementsLeft == 0 )\n            {\n                ulSysTickDecrementsLeft = ulTimerCountsForOneTick;\n            }\n\n            /* Calculate the reload value required to wait xExpectedIdleTime\n             * tick periods.  -1 is used because this code normally executes part\n             * way through the first tick period.  But if the SysTick IRQ is now\n             * pending, then clear the IRQ, suppressing the first tick, and correct\n             * the reload value to reflect that the second tick period is already\n             * underway.  The expected idle time is always at least two ticks. */\n            ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );\n\n            if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )\n            {\n                portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;\n                ulReloadValue -= ulTimerCountsForOneTick;\n            }\n\n            if( ulReloadValue > ulStoppedTimerCompensation )\n            {\n                ulReloadValue -= ulStoppedTimerCompensation;\n            }\n\n            /* Set the new reload value. */\n            portNVIC_SYSTICK_LOAD_REG = ulReloadValue;\n\n            /* Clear the SysTick count flag and set the count value back to\n             * zero. */\n            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n            /* Restart SysTick. */\n            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\n\n            /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can\n             * set its parameter to 0 to indicate that its implementation contains\n             * its own wait for interrupt or wait for event instruction, and so wfi\n             * should not be executed again.  However, the original expected idle\n             * time variable must remain unmodified, so a copy is taken. */\n            xModifiableIdleTime = xExpectedIdleTime;\n            configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\n\n            if( xModifiableIdleTime > 0 )\n            {\n                __asm volatile ( \"dsb\" ::: \"memory\" );\n                __asm volatile ( \"wfi\" );\n                __asm volatile ( \"isb\" );\n            }\n\n            configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\n\n            /* Re-enable interrupts to allow the interrupt that brought the MCU\n             * out of sleep mode to execute immediately.  See comments above\n             * the cpsid instruction above. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n            __asm volatile ( \"dsb\" );\n            __asm volatile ( \"isb\" );\n\n            /* Disable interrupts again because the clock is about to be stopped\n             * and interrupts that execute while the clock is stopped will increase\n             * any slippage between the time maintained by the RTOS and calendar\n             * time. */\n            __asm volatile ( \"cpsid i\" ::: \"memory\" );\n            __asm volatile ( \"dsb\" );\n            __asm volatile ( \"isb\" );\n\n            /* Disable the SysTick clock without reading the\n             * portNVIC_SYSTICK_CTRL_REG register to ensure the\n             * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,\n             * the time the SysTick is stopped for is accounted for as best it can\n             * be, but using the tickless mode will inevitably result in some tiny\n             * drift of the time maintained by the kernel with respect to calendar\n             * time*/\n            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );\n\n            /* Determine whether the SysTick has already counted to zero. */\n            if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n            {\n                uint32_t ulCalculatedLoadValue;\n\n                /* The tick interrupt ended the sleep (or is now pending), and\n                 * a new tick period has started.  Reset portNVIC_SYSTICK_LOAD_REG\n                 * with whatever remains of the new tick period. */\n                ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\n\n                /* Don't allow a tiny value, or values that have somehow\n                 * underflowed because the post sleep hook did something\n                 * that took too long or because the SysTick current-value register\n                 * is zero. */\n                if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )\n                {\n                    ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );\n                }\n\n                portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;\n\n                /* As the pending tick will be processed as soon as this\n                 * function exits, the tick value maintained by the tick is stepped\n                 * forward by one less than the time spent waiting. */\n                ulCompleteTickPeriods = xExpectedIdleTime - 1UL;\n            }\n            else\n            {\n                /* Something other than the tick interrupt ended the sleep. */\n\n                /* Use the SysTick current-value register to determine the\n                 * number of SysTick decrements remaining until the expected idle\n                 * time would have ended. */\n                ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n                #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )\n                {\n                    /* If the SysTick is not using the core clock, the current-\n                     * value register might still be zero here.  In that case, the\n                     * SysTick didn't load from the reload register, and there are\n                     * ulReloadValue decrements remaining in the expected idle\n                     * time, not zero. */\n                    if( ulSysTickDecrementsLeft == 0 )\n                    {\n                        ulSysTickDecrementsLeft = ulReloadValue;\n                    }\n                }\n                #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */\n\n                /* Work out how long the sleep lasted rounded to complete tick\n                 * periods (not the ulReload value which accounted for part\n                 * ticks). */\n                ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;\n\n                /* How many complete tick periods passed while the processor\n                 * was waiting? */\n                ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;\n\n                /* The reload value is set to whatever fraction of a single tick\n                 * period remains. */\n                portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;\n            }\n\n            /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,\n             * then set portNVIC_SYSTICK_LOAD_REG back to its standard value.  If\n             * the SysTick is not using the core clock, temporarily configure it to\n             * use the core clock.  This configuration forces the SysTick to load\n             * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next\n             * cycle of the other clock.  Then portNVIC_SYSTICK_LOAD_REG is ready\n             * to receive the standard value immediately. */\n            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n            portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n            #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )\n            {\n                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n            }\n            #else\n            {\n                /* The temporary usage of the core clock has served its purpose,\n                 * as described above.  Resume usage of the other clock. */\n                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\n\n                if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n                {\n                    /* The partial tick period already ended.  Be sure the SysTick\n                     * counts it only once. */\n                    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;\n                }\n\n                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n            }\n            #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */\n\n            /* Step the tick to account for any tick periods that elapsed. */\n            vTaskStepTick( ulCompleteTickPeriods );\n\n            /* Exit with interrupts enabled. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n        }\n    }\n#endif /* configUSE_TICKLESS_IDLE */\n/*-----------------------------------------------------------*/\n\n__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Calculate the constants required to configure the tick interrupt. */\n    #if ( configUSE_TICKLESS_IDLE == 1 )\n    {\n        ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );\n        xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;\n        ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\n    }\n    #endif /* configUSE_TICKLESS_IDLE */\n\n    /* Stop and reset the SysTick. */\n    portNVIC_SYSTICK_CTRL_REG = 0UL;\n    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n    /* Configure SysTick to interrupt at the requested rate. */\n    portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\n    portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvTaskExitError( void )\n{\n    volatile uint32_t ulDummy = 0UL;\n\n    /* A function that implements a task must not exit or attempt to return to\n     * its caller as there is nothing to return to. If a task wants to exit it\n     * should instead call vTaskDelete( NULL ). Artificially force an assert()\n     * to be triggered if configASSERT() is defined, then stop here so\n     * application writers can catch the error. */\n    configASSERT( ulCriticalNesting == ~0UL );\n    portDISABLE_INTERRUPTS();\n\n    while( ulDummy == 0 )\n    {\n        /* This file calls prvTaskExitError() after the scheduler has been\n         * started to remove a compiler warning about the function being\n         * defined but never called.  ulDummy is used purely to quieten other\n         * warnings about code appearing after this function is called - making\n         * ulDummy volatile makes the compiler think the function could return\n         * and therefore not output an 'unreachable code' warning for code that\n         * appears after it. */\n    }\n}\n/*-----------------------------------------------------------*/\n\n#if ( configENABLE_MPU == 1 )\n    static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */\n    {\n        #if defined( __ARMCC_VERSION )\n\n            /* Declaration when these variable are defined in code instead of being\n             * exported from linker scripts. */\n            extern uint32_t * __privileged_functions_start__;\n            extern uint32_t * __privileged_functions_end__;\n            extern uint32_t * __syscalls_flash_start__;\n            extern uint32_t * __syscalls_flash_end__;\n            extern uint32_t * __unprivileged_flash_start__;\n            extern uint32_t * __unprivileged_flash_end__;\n            extern uint32_t * __privileged_sram_start__;\n            extern uint32_t * __privileged_sram_end__;\n        #else /* if defined( __ARMCC_VERSION ) */\n            /* Declaration when these variable are exported from linker scripts. */\n            extern uint32_t __privileged_functions_start__[];\n            extern uint32_t __privileged_functions_end__[];\n            extern uint32_t __syscalls_flash_start__[];\n            extern uint32_t __syscalls_flash_end__[];\n            extern uint32_t __unprivileged_flash_start__[];\n            extern uint32_t __unprivileged_flash_end__[];\n            extern uint32_t __privileged_sram_start__[];\n            extern uint32_t __privileged_sram_end__[];\n        #endif /* defined( __ARMCC_VERSION ) */\n\n        /* The only permitted number of regions are 8 or 16. */\n        configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );\n\n        /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */\n        configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );\n\n        /* Check that the MPU is present. */\n        if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )\n        {\n            /* MAIR0 - Index 0. */\n            portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\n            /* MAIR0 - Index 1. */\n            portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\n\n            /* Setup privileged flash as Read Only so that privileged tasks can\n             * read it but not modify. */\n            portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_PRIVILEGED_READ_ONLY );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Setup unprivileged flash as Read Only by both privileged and\n             * unprivileged tasks. All tasks can read it but no-one can modify. */\n            portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_READ_ONLY );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Setup unprivileged syscalls flash as Read Only by both privileged\n             * and unprivileged tasks. All tasks can read it but no-one can modify. */\n            portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_READ_ONLY );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Setup RAM containing kernel data for privileged access only. */\n            portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\n                               ( portMPU_REGION_EXECUTE_NEVER );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Enable mem fault. */\n            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;\n\n            /* Enable MPU with privileged background access i.e. unmapped\n             * regions have privileged access. */\n            portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );\n        }\n    }\n#endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\n#if ( configENABLE_FPU == 1 )\n    static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */\n    {\n        #if ( configENABLE_TRUSTZONE == 1 )\n        {\n            /* Enable non-secure access to the FPU. */\n            SecureInit_EnableNSFPUAccess();\n        }\n        #endif /* configENABLE_TRUSTZONE */\n\n        /* CP10 = 11 ==> Full access to FPU i.e. both privileged and\n         * unprivileged code should be able to access FPU. CP11 should be\n         * programmed to the same value as CP10. */\n        *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |\n                            ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )\n                            );\n\n        /* ASPEN = 1 ==> Hardware should automatically preserve floating point\n         * context on exception entry and restore on exception return.\n         * LSPEN = 1 ==> Enable lazy context save of FP state. */\n        *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );\n    }\n#endif /* configENABLE_FPU */\n/*-----------------------------------------------------------*/\n\nvoid vPortYield( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Set a PendSV to request a context switch. */\n    portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\n\n    /* Barriers are normally not required but do ensure the code is\n     * completely within the specified behaviour for the architecture. */\n    __asm volatile ( \"dsb\" ::: \"memory\" );\n    __asm volatile ( \"isb\" );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */\n{\n    portDISABLE_INTERRUPTS();\n    ulCriticalNesting++;\n\n    /* Barriers are normally not required but do ensure the code is\n     * completely within the specified behaviour for the architecture. */\n    __asm volatile ( \"dsb\" ::: \"memory\" );\n    __asm volatile ( \"isb\" );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */\n{\n    configASSERT( ulCriticalNesting );\n    ulCriticalNesting--;\n\n    if( ulCriticalNesting == 0 )\n    {\n        portENABLE_INTERRUPTS();\n    }\n}\n/*-----------------------------------------------------------*/\n\nvoid SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */\n{\n    uint32_t ulPreviousMask;\n\n    ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();\n    {\n        /* Increment the RTOS tick. */\n        if( xTaskIncrementTick() != pdFALSE )\n        {\n            /* Pend a context switch. */\n            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\n        }\n    }\n    portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */\n{\n    #if ( configENABLE_MPU == 1 )\n        #if defined( __ARMCC_VERSION )\n\n            /* Declaration when these variable are defined in code instead of being\n             * exported from linker scripts. */\n            extern uint32_t * __syscalls_flash_start__;\n            extern uint32_t * __syscalls_flash_end__;\n        #else\n            /* Declaration when these variable are exported from linker scripts. */\n            extern uint32_t __syscalls_flash_start__[];\n            extern uint32_t __syscalls_flash_end__[];\n        #endif /* defined( __ARMCC_VERSION ) */\n    #endif /* configENABLE_MPU */\n\n    uint32_t ulPC;\n\n    #if ( configENABLE_TRUSTZONE == 1 )\n        uint32_t ulR0, ulR1;\n        extern TaskHandle_t pxCurrentTCB;\n        #if ( configENABLE_MPU == 1 )\n            uint32_t ulControl, ulIsTaskPrivileged;\n        #endif /* configENABLE_MPU */\n    #endif /* configENABLE_TRUSTZONE */\n    uint8_t ucSVCNumber;\n\n    /* Register are stored on the stack in the following order - R0, R1, R2, R3,\n     * R12, LR, PC, xPSR. */\n    ulPC = pulCallerStackAddress[ 6 ];\n    ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];\n\n    switch( ucSVCNumber )\n    {\n        #if ( configENABLE_TRUSTZONE == 1 )\n            case portSVC_ALLOCATE_SECURE_CONTEXT:\n\n                /* R0 contains the stack size passed as parameter to the\n                 * vPortAllocateSecureContext function. */\n                ulR0 = pulCallerStackAddress[ 0 ];\n\n                #if ( configENABLE_MPU == 1 )\n                {\n                    /* Read the CONTROL register value. */\n                    __asm volatile ( \"mrs %0, control\"  : \"=r\" ( ulControl ) );\n\n                    /* The task that raised the SVC is privileged if Bit[0]\n                     * in the CONTROL register is 0. */\n                    ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );\n\n                    /* Allocate and load a context for the secure task. */\n                    xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );\n                }\n                #else /* if ( configENABLE_MPU == 1 ) */\n                {\n                    /* Allocate and load a context for the secure task. */\n                    xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );\n                }\n                #endif /* configENABLE_MPU */\n\n                configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );\n                SecureContext_LoadContext( xSecureContext, pxCurrentTCB );\n                break;\n\n            case portSVC_FREE_SECURE_CONTEXT:\n\n                /* R0 contains TCB being freed and R1 contains the secure\n                 * context handle to be freed. */\n                ulR0 = pulCallerStackAddress[ 0 ];\n                ulR1 = pulCallerStackAddress[ 1 ];\n\n                /* Free the secure context. */\n                SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );\n                break;\n        #endif /* configENABLE_TRUSTZONE */\n\n        case portSVC_START_SCHEDULER:\n            #if ( configENABLE_TRUSTZONE == 1 )\n            {\n                /* De-prioritize the non-secure exceptions so that the\n                 * non-secure pendSV runs at the lowest priority. */\n                SecureInit_DePrioritizeNSExceptions();\n\n                /* Initialize the secure context management system. */\n                SecureContext_Init();\n            }\n            #endif /* configENABLE_TRUSTZONE */\n\n            #if ( configENABLE_FPU == 1 )\n            {\n                /* Setup the Floating Point Unit (FPU). */\n                prvSetupFPU();\n            }\n            #endif /* configENABLE_FPU */\n\n            /* Setup the context of the first task so that the first task starts\n             * executing. */\n            vRestoreContextOfFirstTask();\n            break;\n\n            #if ( configENABLE_MPU == 1 )\n                case portSVC_RAISE_PRIVILEGE:\n\n                    /* Only raise the privilege, if the svc was raised from any of\n                     * the system calls. */\n                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&\n                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )\n                    {\n                        vRaisePrivilege();\n                    }\n                    break;\n            #endif /* configENABLE_MPU */\n\n        default:\n            /* Incorrect SVC call. */\n            configASSERT( pdFALSE );\n    }\n}\n/*-----------------------------------------------------------*/\n/* *INDENT-OFF* */\n#if ( configENABLE_MPU == 1 )\n    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,\n                                         StackType_t * pxEndOfStack,\n                                         TaskFunction_t pxCode,\n                                         void * pvParameters,\n                                         BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */\n#else\n    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,\n                                         StackType_t * pxEndOfStack,\n                                         TaskFunction_t pxCode,\n                                         void * pvParameters ) /* PRIVILEGED_FUNCTION */\n#endif /* configENABLE_MPU */\n/* *INDENT-ON* */\n{\n    /* Simulate the stack frame as it would be created by a context switch\n     * interrupt. */\n    #if ( portPRELOAD_REGISTERS == 0 )\n    {\n        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\n        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\n        pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */\n        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */\n        pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */\n        *pxTopOfStack = portINITIAL_EXC_RETURN;\n\n        #if ( configENABLE_MPU == 1 )\n        {\n            pxTopOfStack--;\n\n            if( xRunPrivileged == pdTRUE )\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n            else\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n        }\n        #endif /* configENABLE_MPU */\n\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\n\n        #if ( configENABLE_TRUSTZONE == 1 )\n        {\n            pxTopOfStack--;\n            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\n        }\n        #endif /* configENABLE_TRUSTZONE */\n    }\n    #else /* portPRELOAD_REGISTERS */\n    {\n        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\n        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04 */\n        pxTopOfStack--;\n        *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN */\n\n        #if ( configENABLE_MPU == 1 )\n        {\n            pxTopOfStack--;\n\n            if( xRunPrivileged == pdTRUE )\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n            else\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n        }\n        #endif /* configENABLE_MPU */\n\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\n\n        #if ( configENABLE_TRUSTZONE == 1 )\n        {\n            pxTopOfStack--;\n            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\n        }\n        #endif /* configENABLE_TRUSTZONE */\n    }\n    #endif /* portPRELOAD_REGISTERS */\n\n    return pxTopOfStack;\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Make PendSV, CallSV and SysTick the same priority as the kernel. */\n    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;\n    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;\n\n    #if ( configENABLE_MPU == 1 )\n    {\n        /* Setup the Memory Protection Unit (MPU). */\n        prvSetupMPU();\n    }\n    #endif /* configENABLE_MPU */\n\n    /* Start the timer that generates the tick ISR. Interrupts are disabled\n     * here already. */\n    vPortSetupTimerInterrupt();\n\n    /* Initialize the critical nesting count ready for the first task. */\n    ulCriticalNesting = 0;\n\n    /* Start the first task. */\n    vStartFirstTask();\n\n    /* Should never get here as the tasks will now be executing. Call the task\n     * exit error function to prevent compiler warnings about a static function\n     * not being called in the case that the application writer overrides this\n     * functionality by defining configTASK_RETURN_ADDRESS. Call\n     * vTaskSwitchContext() so link time optimization does not remove the\n     * symbol. */\n    vTaskSwitchContext();\n    prvTaskExitError();\n\n    /* Should not get here. */\n    return 0;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Not implemented in ports where there is nothing to return to.\n     * Artificially force an assert. */\n    configASSERT( ulCriticalNesting == 1000UL );\n}\n/*-----------------------------------------------------------*/\n\n#if ( configENABLE_MPU == 1 )\n    void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,\n                                    const struct xMEMORY_REGION * const xRegions,\n                                    StackType_t * pxBottomOfStack,\n                                    uint32_t ulStackDepth )\n    {\n        uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;\n        int32_t lIndex = 0;\n\n        #if defined( __ARMCC_VERSION )\n\n            /* Declaration when these variable are defined in code instead of being\n             * exported from linker scripts. */\n            extern uint32_t * __privileged_sram_start__;\n            extern uint32_t * __privileged_sram_end__;\n        #else\n            /* Declaration when these variable are exported from linker scripts. */\n            extern uint32_t __privileged_sram_start__[];\n            extern uint32_t __privileged_sram_end__[];\n        #endif /* defined( __ARMCC_VERSION ) */\n\n        /* Setup MAIR0. */\n        xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\n        xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\n\n        /* This function is called automatically when the task is created - in\n         * which case the stack region parameters will be valid.  At all other\n         * times the stack parameters will not be valid and it is assumed that\n         * the stack region has already been configured. */\n        if( ulStackDepth > 0 )\n        {\n            ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;\n            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;\n\n            /* If the stack is within the privileged SRAM, do not protect it\n             * using a separate MPU region. This is needed because privileged\n             * SRAM is already protected using an MPU region and ARMv8-M does\n             * not allow overlapping MPU regions. */\n            if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) &&\n                ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) )\n            {\n                xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0;\n                xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0;\n            }\n            else\n            {\n                /* Define the region that allows access to the stack. */\n                ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK;\n                ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\n\n                xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |\n                                                             ( portMPU_REGION_NON_SHAREABLE ) |\n                                                             ( portMPU_REGION_READ_WRITE ) |\n                                                             ( portMPU_REGION_EXECUTE_NEVER );\n\n                xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) |\n                                                             ( portMPU_RLAR_ATTR_INDEX0 ) |\n                                                             ( portMPU_RLAR_REGION_ENABLE );\n            }\n        }\n\n        /* User supplied configurable regions. */\n        for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )\n        {\n            /* If xRegions is NULL i.e. the task has not specified any MPU\n             * region, the else part ensures that all the configurable MPU\n             * regions are invalidated. */\n            if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )\n            {\n                /* Translate the generic region definition contained in xRegions\n                 * into the ARMv8 specific MPU settings that are then stored in\n                 * xMPUSettings. */\n                ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;\n                ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;\n                ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\n\n                /* Start address. */\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |\n                                                                          ( portMPU_REGION_NON_SHAREABLE );\n\n                /* RO/RW. */\n                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )\n                {\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );\n                }\n                else\n                {\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );\n                }\n\n                /* XN. */\n                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )\n                {\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );\n                }\n\n                /* End Address. */\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |\n                                                                          ( portMPU_RLAR_REGION_ENABLE );\n\n                /* Normal memory/ Device memory. */\n                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )\n                {\n                    /* Attr1 in MAIR0 is configured as device memory. */\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;\n                }\n                else\n                {\n                    /* Attr0 in MAIR0 is configured as normal memory. */\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;\n                }\n            }\n            else\n            {\n                /* Invalidate the region. */\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;\n            }\n\n            lIndex++;\n        }\n    }\n#endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\nBaseType_t xPortIsInsideInterrupt( void )\n{\n    uint32_t ulCurrentInterrupt;\n    BaseType_t xReturn;\n\n    /* Obtain the number of the currently executing interrupt. Interrupt Program\n     * Status Register (IPSR) holds the exception number of the currently-executing\n     * exception or zero for Thread mode.*/\n    __asm volatile ( \"mrs %0, ipsr\" : \"=r\" ( ulCurrentInterrupt )::\"memory\" );\n\n    if( ulCurrentInterrupt == 0 )\n    {\n        xReturn = pdFALSE;\n    }\n    else\n    {\n        xReturn = pdTRUE;\n    }\n\n    return xReturn;\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM85/non_secure/portasm.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef __PORT_ASM_H__\n#define __PORT_ASM_H__\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n\n/* MPU wrappers includes. */\n#include \"mpu_wrappers.h\"\n\n/**\n * @brief Restore the context of the first task so that the first task starts\n * executing.\n */\nvoid vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Checks whether or not the processor is privileged.\n *\n * @return 1 if the processor is already privileged, 0 otherwise.\n */\nBaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );\n\n/**\n * @brief Raises the privilege level by clearing the bit 0 of the CONTROL\n * register.\n *\n * @note This is a privileged function and should only be called from the kenrel\n * code.\n *\n * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.\n *  Bit[0] = 0 --> The processor is running privileged\n *  Bit[0] = 1 --> The processor is running unprivileged.\n */\nvoid vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\n * register.\n *\n * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.\n *  Bit[0] = 0 --> The processor is running privileged\n *  Bit[0] = 1 --> The processor is running unprivileged.\n */\nvoid vResetPrivilege( void ) __attribute__( ( naked ) );\n\n/**\n * @brief Starts the first task.\n */\nvoid vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Disables interrupts.\n */\nuint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Enables interrupts.\n */\nvoid vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief PendSV Exception handler.\n */\nvoid PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief SVC Handler.\n */\nvoid SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Allocate a Secure context for the calling task.\n *\n * @param[in] ulSecureStackSize The size of the stack to be allocated on the\n * secure side for the calling task.\n */\nvoid vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) );\n\n/**\n * @brief Free the task's secure context.\n *\n * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.\n */\nvoid vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n#endif /* __PORT_ASM_H__ */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM85/non_secure/portasm.s",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n/* Including FreeRTOSConfig.h here will cause build errors if the header file\ncontains code not understood by the assembler - for example the 'extern' keyword.\nTo avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so\nthe code is included in C files but excluded by the preprocessor in assembly\nfiles (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */\n#include \"FreeRTOSConfig.h\"\n\n\tEXTERN pxCurrentTCB\n\tEXTERN xSecureContext\n\tEXTERN vTaskSwitchContext\n\tEXTERN vPortSVCHandler_C\n\tEXTERN SecureContext_SaveContext\n\tEXTERN SecureContext_LoadContext\n\n\tPUBLIC xIsPrivileged\n\tPUBLIC vResetPrivilege\n\tPUBLIC vPortAllocateSecureContext\n\tPUBLIC vRestoreContextOfFirstTask\n\tPUBLIC vRaisePrivilege\n\tPUBLIC vStartFirstTask\n\tPUBLIC ulSetInterruptMask\n\tPUBLIC vClearInterruptMask\n\tPUBLIC PendSV_Handler\n\tPUBLIC SVC_Handler\n\tPUBLIC vPortFreeSecureContext\n/*-----------------------------------------------------------*/\n\n/*---------------- Unprivileged Functions -------------------*/\n\n/*-----------------------------------------------------------*/\n\n\tSECTION .text:CODE:NOROOT(2)\n\tTHUMB\n/*-----------------------------------------------------------*/\n\nxIsPrivileged:\n\tmrs r0, control\t\t\t\t\t\t\t/* r0 = CONTROL. */\n\ttst r0, #1\t\t\t\t\t\t\t\t/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\n\tite ne\n\tmovne r0, #0\t\t\t\t\t\t\t/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\n\tmoveq r0, #1\t\t\t\t\t\t\t/* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */\n\tbx lr\t\t\t\t\t\t\t\t\t/* Return. */\n/*-----------------------------------------------------------*/\n\nvResetPrivilege:\n\tmrs r0, control\t\t\t\t\t\t\t/* r0 = CONTROL. */\n\torr r0, r0, #1\t\t\t\t\t\t\t/* r0 = r0 | 1. */\n\tmsr control, r0\t\t\t\t\t\t\t/* CONTROL = r0. */\n\tbx lr\t\t\t\t\t\t\t\t\t/* Return to the caller. */\n/*-----------------------------------------------------------*/\n\nvPortAllocateSecureContext:\n\tsvc 0\t\t\t\t\t\t\t\t\t/* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 0. */\n\tbx lr\t\t\t\t\t\t\t\t\t/* Return. */\n/*-----------------------------------------------------------*/\n\n/*----------------- Privileged Functions --------------------*/\n\n/*-----------------------------------------------------------*/\n\n\tSECTION privileged_functions:CODE:NOROOT(2)\n\tTHUMB\n/*-----------------------------------------------------------*/\n\nvRestoreContextOfFirstTask:\n\tldr  r2, =pxCurrentTCB\t\t\t\t\t/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n\tldr  r3, [r2]\t\t\t\t\t\t\t/* Read pxCurrentTCB. */\n\tldr  r0, [r3]\t\t\t\t\t\t\t/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\n\n#if ( configENABLE_MPU == 1 )\n\tdmb\t\t\t\t\t\t\t\t\t\t/* Complete outstanding transfers before disabling MPU. */\n\tldr r2, =0xe000ed94\t\t\t\t\t\t/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n\tldr r4, [r2]\t\t\t\t\t\t\t/* Read the value of MPU_CTRL. */\n\tbic r4, r4, #1\t\t\t\t\t\t\t/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\n\tstr r4, [r2]\t\t\t\t\t\t\t/* Disable MPU. */\n\n\tadds r3, #4\t\t\t\t\t\t\t\t/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\n\tldr  r4, [r3]\t\t\t\t\t\t\t/* r4 = *r3 i.e. r4 = MAIR0. */\n\tldr  r2, =0xe000edc0\t\t\t\t\t/* r2 = 0xe000edc0 [Location of MAIR0]. */\n\tstr  r4, [r2]\t\t\t\t\t\t\t/* Program MAIR0. */\n\tldr  r2, =0xe000ed98\t\t\t\t\t/* r2 = 0xe000ed98 [Location of RNR]. */\n\tmovs r4, #4\t\t\t\t\t\t\t\t/* r4 = 4. */\n\tstr  r4, [r2]\t\t\t\t\t\t\t/* Program RNR = 4. */\n\tadds r3, #4\t\t\t\t\t\t\t\t/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */\n\tldr  r2, =0xe000ed9c\t\t\t\t\t/* r2 = 0xe000ed9c [Location of RBAR]. */\n\tldmia r3!, {r4-r11}\t\t\t\t\t\t/* Read 4 set of RBAR/RLAR registers from TCB. */\n\tstmia r2!, {r4-r11}\t\t\t\t\t\t/* Write 4 set of RBAR/RLAR registers using alias registers. */\n\n\tldr r2, =0xe000ed94\t\t\t\t\t\t/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n\tldr r4, [r2]\t\t\t\t\t\t\t/* Read the value of MPU_CTRL. */\n\torr r4, r4, #1\t\t\t\t\t\t\t/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\n\tstr r4, [r2]\t\t\t\t\t\t\t/* Enable MPU. */\n\tdsb\t\t\t\t\t\t\t\t\t\t/* Force memory writes before continuing. */\n#endif /* configENABLE_MPU */\n\n#if ( configENABLE_MPU == 1 )\n\tldm  r0!, {r1-r4}\t\t\t\t\t\t/* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */\n\tldr  r5, =xSecureContext\n\tstr  r1, [r5]\t\t\t\t\t\t\t/* Set xSecureContext to this task's value for the same. */\n\tmsr  psplim, r2\t\t\t\t\t\t\t/* Set this task's PSPLIM value. */\n\tmsr  control, r3\t\t\t\t\t\t/* Set this task's CONTROL value. */\n\tadds r0, #32\t\t\t\t\t\t\t/* Discard everything up to r0. */\n\tmsr  psp, r0\t\t\t\t\t\t\t/* This is now the new top of stack to use in the task. */\n\tisb\n\tmov  r0, #0\n\tmsr  basepri, r0\t\t\t\t\t\t/* Ensure that interrupts are enabled when the first task starts. */\n\tbx   r4\t\t\t\t\t\t\t\t\t/* Finally, branch to EXC_RETURN. */\n#else /* configENABLE_MPU */\n\tldm  r0!, {r1-r3}\t\t\t\t\t\t/* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */\n\tldr  r4, =xSecureContext\n\tstr  r1, [r4]\t\t\t\t\t\t\t/* Set xSecureContext to this task's value for the same. */\n\tmsr  psplim, r2\t\t\t\t\t\t\t/* Set this task's PSPLIM value. */\n\tmovs r1, #2\t\t\t\t\t\t\t\t/* r1 = 2. */\n\tmsr  CONTROL, r1\t\t\t\t\t\t/* Switch to use PSP in the thread mode. */\n\tadds r0, #32\t\t\t\t\t\t\t/* Discard everything up to r0. */\n\tmsr  psp, r0\t\t\t\t\t\t\t/* This is now the new top of stack to use in the task. */\n\tisb\n\tmov  r0, #0\n\tmsr  basepri, r0\t\t\t\t\t\t/* Ensure that interrupts are enabled when the first task starts. */\n\tbx   r3\t\t\t\t\t\t\t\t\t/* Finally, branch to EXC_RETURN. */\n#endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\nvRaisePrivilege:\n\tmrs  r0, control\t\t\t\t\t\t/* Read the CONTROL register. */\n\tbic r0, r0, #1\t\t\t\t\t\t\t/* Clear the bit 0. */\n\tmsr  control, r0\t\t\t\t\t\t/* Write back the new CONTROL value. */\n\tbx lr\t\t\t\t\t\t\t\t\t/* Return to the caller. */\n/*-----------------------------------------------------------*/\n\nvStartFirstTask:\n\tldr r0, =0xe000ed08\t\t\t\t\t\t/* Use the NVIC offset register to locate the stack. */\n\tldr r0, [r0]\t\t\t\t\t\t\t/* Read the VTOR register which gives the address of vector table. */\n\tldr r0, [r0]\t\t\t\t\t\t\t/* The first entry in vector table is stack pointer. */\n\tmsr msp, r0\t\t\t\t\t\t\t\t/* Set the MSP back to the start of the stack. */\n\tcpsie i\t\t\t\t\t\t\t\t\t/* Globally enable interrupts. */\n\tcpsie f\n\tdsb\n\tisb\n\tsvc 2\t\t\t\t\t\t\t\t\t/* System call to start the first task. portSVC_START_SCHEDULER = 2. */\n/*-----------------------------------------------------------*/\n\nulSetInterruptMask:\n\tmrs r0, basepri\t\t\t\t\t\t\t/* r0 = basepri. Return original basepri value. */\n\tmov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY\n\tmsr basepri, r1\t\t\t\t\t\t\t/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */\n\tdsb\n\tisb\n\tbx lr\t\t\t\t\t\t\t\t\t/* Return. */\n/*-----------------------------------------------------------*/\n\nvClearInterruptMask:\n\tmsr basepri, r0\t\t\t\t\t\t\t/* basepri = ulMask. */\n\tdsb\n\tisb\n\tbx lr\t\t\t\t\t\t\t\t\t/* Return. */\n/*-----------------------------------------------------------*/\n\nPendSV_Handler:\n\tldr r3, =xSecureContext\t\t\t\t\t/* Read the location of xSecureContext i.e. &( xSecureContext ). */\n\tldr r0, [r3]\t\t\t\t\t\t\t/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */\n\tldr r3, =pxCurrentTCB\t\t\t\t\t/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n\tldr r1, [r3]\t\t\t\t\t\t\t/* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */\n\tmrs r2, psp\t\t\t\t\t\t\t\t/* Read PSP in r2. */\n\n\tcbz r0, save_ns_context\t\t\t\t\t/* No secure context to save. */\n\tpush {r0-r2, r14}\n\tbl SecureContext_SaveContext\t\t\t/* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */\n\tpop {r0-r3}\t\t\t\t\t\t\t\t/* LR is now in r3. */\n\tmov lr, r3\t\t\t\t\t\t\t\t/* LR = r3. */\n\tlsls r1, r3, #25\t\t\t\t\t\t/* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\n\tbpl save_ns_context\t\t\t\t\t\t/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\n\n\tldr r3, =pxCurrentTCB\t\t\t\t\t/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n\tldr r1, [r3]\t\t\t\t\t\t\t/* Read pxCurrentTCB. */\n#if ( configENABLE_MPU == 1 )\n\tsubs r2, r2, #16\t\t\t\t\t\t/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */\n\tstr r2, [r1]\t\t\t\t\t\t\t/* Save the new top of stack in TCB. */\n\tmrs r1, psplim\t\t\t\t\t\t\t/* r1 = PSPLIM. */\n\tmrs r3, control\t\t\t\t\t\t\t/* r3 = CONTROL. */\n\tmov r4, lr\t\t\t\t\t\t\t\t/* r4 = LR/EXC_RETURN. */\n\tstmia r2!, {r0, r1, r3, r4}\t\t\t\t/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\n#else /* configENABLE_MPU */\n\tsubs r2, r2, #12\t\t\t\t\t\t/* Make space for xSecureContext, PSPLIM and LR on the stack. */\n\tstr r2, [r1]\t\t\t\t\t\t\t/* Save the new top of stack in TCB. */\n\tmrs r1, psplim\t\t\t\t\t\t\t/* r1 = PSPLIM. */\n\tmov r3, lr\t\t\t\t\t\t\t\t/* r3 = LR/EXC_RETURN. */\n\tstmia r2!, {r0, r1, r3}\t\t\t\t\t/* Store xSecureContext, PSPLIM and LR on the stack. */\n#endif /* configENABLE_MPU */\n\tb select_next_task\n\n\tsave_ns_context:\n\t\tldr r3, =pxCurrentTCB\t\t\t\t/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n\t\tldr r1, [r3]\t\t\t\t\t\t/* Read pxCurrentTCB. */\n\t#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )\n\t\ttst lr, #0x10\t\t\t\t\t\t/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */\n\t\tit eq\n\t\tvstmdbeq r2!, {s16-s31}\t\t\t\t/* Store the additional FP context registers which are not saved automatically. */\n\t#endif /* configENABLE_FPU || configENABLE_MVE */\n\t#if ( configENABLE_MPU == 1 )\n\t\tsubs r2, r2, #48\t\t\t\t\t/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */\n\t\tstr r2, [r1]\t\t\t\t\t\t/* Save the new top of stack in TCB. */\n\t\tadds r2, r2, #16\t\t\t\t\t/* r2 = r2 + 16. */\n\t\tstm r2, {r4-r11}\t\t\t\t\t/* Store the registers that are not saved automatically. */\n\t\tmrs r1, psplim\t\t\t\t\t\t/* r1 = PSPLIM. */\n\t\tmrs r3, control\t\t\t\t\t\t/* r3 = CONTROL. */\n\t\tmov r4, lr\t\t\t\t\t\t\t/* r4 = LR/EXC_RETURN. */\n\t\tsubs r2, r2, #16\t\t\t\t\t/* r2 = r2 - 16. */\n\t\tstmia r2!, {r0, r1, r3, r4}\t\t\t/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\n\t#else /* configENABLE_MPU */\n\t\tsubs r2, r2, #44\t\t\t\t\t/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */\n\t\tstr r2, [r1]\t\t\t\t\t\t/* Save the new top of stack in TCB. */\n\t\tadds r2, r2, #12\t\t\t\t\t/* r2 = r2 + 12. */\n\t\tstm r2, {r4-r11}\t\t\t\t\t/* Store the registers that are not saved automatically. */\n\t\tmrs r1, psplim\t\t\t\t\t\t/* r1 = PSPLIM. */\n\t\tmov r3, lr\t\t\t\t\t\t\t/* r3 = LR/EXC_RETURN. */\n\t\tsubs r2, r2, #12\t\t\t\t\t/* r2 = r2 - 12. */\n\t\tstmia r2!, {r0, r1, r3}\t\t\t\t/* Store xSecureContext, PSPLIM and LR on the stack. */\n\t#endif /* configENABLE_MPU */\n\n\tselect_next_task:\n\t\tmov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY\n\t\tmsr basepri, r0\t\t\t\t\t\t/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */\n\t\tdsb\n\t\tisb\n\t\tbl vTaskSwitchContext\n\t\tmov r0, #0\t\t\t\t\t\t\t/* r0 = 0. */\n\t\tmsr basepri, r0\t\t\t\t\t\t/* Enable interrupts. */\n\n\t\tldr r3, =pxCurrentTCB\t\t\t\t/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n\t\tldr r1, [r3]\t\t\t\t\t\t/* Read pxCurrentTCB. */\n\t\tldr r2, [r1]\t\t\t\t\t\t/* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */\n\n\t#if ( configENABLE_MPU == 1 )\n\t\tdmb\t\t\t\t\t\t\t\t\t/* Complete outstanding transfers before disabling MPU. */\n\t\tldr r3, =0xe000ed94\t\t\t\t\t/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */\n\t\tldr r4, [r3]\t\t\t\t\t\t/* Read the value of MPU_CTRL. */\n\t\tbic r4, r4, #1\t\t\t\t\t\t/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\n\t\tstr r4, [r3]\t\t\t\t\t\t/* Disable MPU. */\n\n\t\tadds r1, #4\t\t\t\t\t\t\t/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\n\t\tldr r4, [r1]\t\t\t\t\t\t/* r4 = *r1 i.e. r4 = MAIR0. */\n\t\tldr r3, =0xe000edc0\t\t\t\t\t/* r3 = 0xe000edc0 [Location of MAIR0]. */\n\t\tstr r4, [r3]\t\t\t\t\t\t/* Program MAIR0. */\n\t\tldr r3, =0xe000ed98\t\t\t\t\t/* r3 = 0xe000ed98 [Location of RNR]. */\n\t\tmovs r4, #4\t\t\t\t\t\t\t/* r4 = 4. */\n\t\tstr r4, [r3]\t\t\t\t\t\t/* Program RNR = 4. */\n\t\tadds r1, #4\t\t\t\t\t\t\t/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\n\t\tldr  r3, =0xe000ed9c\t\t\t\t/* r3 = 0xe000ed9c [Location of RBAR]. */\n\t\tldmia r1!, {r4-r11}\t\t\t\t\t/* Read 4 sets of RBAR/RLAR registers from TCB. */\n\t\tstmia r3!, {r4-r11}\t\t\t\t\t/* Write 4 set of RBAR/RLAR registers using alias registers. */\n\n\t\tldr r3, =0xe000ed94\t\t\t\t\t/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */\n\t\tldr r4, [r3]\t\t\t\t\t\t/* Read the value of MPU_CTRL. */\n\t\torr r4, r4, #1\t\t\t\t\t\t/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\n\t\tstr r4, [r3]\t\t\t\t\t\t/* Enable MPU. */\n\t\tdsb\t\t\t\t\t\t\t\t\t/* Force memory writes before continuing. */\n\t#endif /* configENABLE_MPU */\n\n\t#if ( configENABLE_MPU == 1 )\n\t\tldmia r2!, {r0, r1, r3, r4}\t\t\t/* Read from stack - r0 = xSecureContext, r1 = PSPLIM, r3 = CONTROL and r4 = LR. */\n\t\tmsr psplim, r1\t\t\t\t\t\t/* Restore the PSPLIM register value for the task. */\n\t\tmsr control, r3\t\t\t\t\t\t/* Restore the CONTROL register value for the task. */\n\t\tmov lr, r4\t\t\t\t\t\t\t/* LR = r4. */\n\t\tldr r3, =xSecureContext\t\t\t\t/* Read the location of xSecureContext i.e. &( xSecureContext ). */\n\t\tstr r0, [r3]\t\t\t\t\t\t/* Restore the task's xSecureContext. */\n\t\tcbz r0, restore_ns_context\t\t\t/* If there is no secure context for the task, restore the non-secure context. */\n\t\tldr r3, =pxCurrentTCB\t\t\t\t/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n\t\tldr r1, [r3]\t\t\t\t\t\t/* Read pxCurrentTCB. */\n\t\tpush {r2, r4}\n\t\tbl SecureContext_LoadContext\t\t/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */\n\t\tpop {r2, r4}\n\t\tmov lr, r4\t\t\t\t\t\t\t/* LR = r4. */\n\t\tlsls r1, r4, #25\t\t\t\t\t/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\n\t\tbpl restore_ns_context\t\t\t\t/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\n\t\tmsr psp, r2\t\t\t\t\t\t\t/* Remember the new top of stack for the task. */\n\t\tbx lr\n\t#else /* configENABLE_MPU */\n\t\tldmia r2!, {r0, r1, r4}\t\t\t\t/* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */\n\t\tmsr psplim, r1\t\t\t\t\t\t/* Restore the PSPLIM register value for the task. */\n\t\tmov lr, r4\t\t\t\t\t\t\t/* LR = r4. */\n\t\tldr r3, =xSecureContext\t\t\t\t/* Read the location of xSecureContext i.e. &( xSecureContext ). */\n\t\tstr r0, [r3]\t\t\t\t\t\t/* Restore the task's xSecureContext. */\n\t\tcbz r0, restore_ns_context\t\t\t/* If there is no secure context for the task, restore the non-secure context. */\n\t\tldr r3, =pxCurrentTCB\t\t\t\t/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n\t\tldr r1, [r3]\t\t\t\t\t\t/* Read pxCurrentTCB. */\n\t\tpush {r2, r4}\n\t\tbl SecureContext_LoadContext\t\t/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */\n\t\tpop {r2, r4}\n\t\tmov lr, r4\t\t\t\t\t\t\t/* LR = r4. */\n\t\tlsls r1, r4, #25\t\t\t\t\t/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\n\t\tbpl restore_ns_context\t\t\t\t/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\n\t\tmsr psp, r2\t\t\t\t\t\t\t/* Remember the new top of stack for the task. */\n\t\tbx lr\n\t#endif /* configENABLE_MPU */\n\n\trestore_ns_context:\n\t\tldmia r2!, {r4-r11}\t\t\t\t\t/* Restore the registers that are not automatically restored. */\n\t#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )\n\t\ttst lr, #0x10\t\t\t\t\t\t/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */\n\t\tit eq\n\t\tvldmiaeq r2!, {s16-s31}\t\t\t\t/* Restore the additional FP context registers which are not restored automatically. */\n\t#endif /* configENABLE_FPU || configENABLE_MVE */\n\t\tmsr psp, r2\t\t\t\t\t\t\t/* Remember the new top of stack for the task. */\n\t\tbx lr\n/*-----------------------------------------------------------*/\n\nSVC_Handler:\n\ttst lr, #4\n\tite eq\n\tmrseq r0, msp\n\tmrsne r0, psp\n\tb vPortSVCHandler_C\n/*-----------------------------------------------------------*/\n\nvPortFreeSecureContext:\n\t/* r0 = uint32_t *pulTCB. */\n\tldr r2, [r0]\t\t\t\t\t\t\t/* The first item in the TCB is the top of the stack. */\n\tldr r1, [r2]\t\t\t\t\t\t\t/* The first item on the stack is the task's xSecureContext. */\n\tcmp r1, #0\t\t\t\t\t\t\t\t/* Raise svc if task's xSecureContext is not NULL. */\n\tit ne\n\tsvcne 1\t\t\t\t\t\t\t\t\t/* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */\n\tbx lr\t\t\t\t\t\t\t\t\t/* Return. */\n/*-----------------------------------------------------------*/\n\n\tEND\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM85/non_secure/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef PORTMACRO_H\n#define PORTMACRO_H\n\n#ifdef __cplusplus\n    extern \"C\" {\n#endif\n\n#include \"portmacrocommon.h\"\n\n/*------------------------------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the given hardware\n * and compiler.\n *\n * These settings should not be altered.\n *------------------------------------------------------------------------------\n */\n\n#ifndef configENABLE_MVE\n    #error configENABLE_MVE must be defined in FreeRTOSConfig.h. Set configENABLE_MVE to 1 to enable the MVE or 0 to disable the MVE.\n#endif /* configENABLE_MVE */\n/*-----------------------------------------------------------*/\n\n/**\n * Architecture specifics.\n */\n#define portARCH_NAME                       \"Cortex-M85\"\n#define portDONT_DISCARD                    __root\n/*-----------------------------------------------------------*/\n\n#if( configTOTAL_MPU_REGIONS == 16 )\n    #error 16 MPU regions are not yet supported for this port.\n#endif\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Critical section management.\n */\n#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()\n#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )\n/*-----------------------------------------------------------*/\n\n/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in\n * the source code because to do so would cause other compilers to generate\n * warnings. */\n#pragma diag_suppress=Be006\n#pragma diag_suppress=Pa082\n/*-----------------------------------------------------------*/\n\n#ifdef __cplusplus\n    }\n#endif\n\n#endif /* PORTMACRO_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef PORTMACROCOMMON_H\n    #define PORTMACROCOMMON_H\n\n    #ifdef __cplusplus\n        extern \"C\" {\n    #endif\n\n/*------------------------------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the given hardware\n * and compiler.\n *\n * These settings should not be altered.\n *------------------------------------------------------------------------------\n */\n\n    #ifndef configENABLE_FPU\n        #error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.\n    #endif /* configENABLE_FPU */\n\n    #ifndef configENABLE_MPU\n        #error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.\n    #endif /* configENABLE_MPU */\n\n    #ifndef configENABLE_TRUSTZONE\n        #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.\n    #endif /* configENABLE_TRUSTZONE */\n\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Type definitions.\n */\n    #define portCHAR          char\n    #define portFLOAT         float\n    #define portDOUBLE        double\n    #define portLONG          long\n    #define portSHORT         short\n    #define portSTACK_TYPE    uint32_t\n    #define portBASE_TYPE     long\n\n    typedef portSTACK_TYPE   StackType_t;\n    typedef long             BaseType_t;\n    typedef unsigned long    UBaseType_t;\n\n    #if ( configUSE_16_BIT_TICKS == 1 )\n        typedef uint16_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffff\n    #else\n        typedef uint32_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL\n\n/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\n * not need to be guarded with a critical section. */\n        #define portTICK_TYPE_IS_ATOMIC    1\n    #endif\n/*-----------------------------------------------------------*/\n\n/**\n * Architecture specifics.\n */\n    #define portSTACK_GROWTH                   ( -1 )\n    #define portTICK_PERIOD_MS                 ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\n    #define portBYTE_ALIGNMENT                 8\n    #define portNOP()\n    #define portINLINE                         __inline\n    #ifndef portFORCE_INLINE\n        #define portFORCE_INLINE               inline __attribute__( ( always_inline ) )\n    #endif\n    #define portHAS_STACK_OVERFLOW_CHECKING    1\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Extern declarations.\n */\n    extern BaseType_t xPortIsInsideInterrupt( void );\n\n    extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;\n\n    extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;\n    extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;\n\n    extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\n    extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\n\n    #if ( configENABLE_TRUSTZONE == 1 )\n        extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */\n        extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;\n    #endif /* configENABLE_TRUSTZONE */\n\n    #if ( configENABLE_MPU == 1 )\n        extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;\n        extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;\n    #endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\n/**\n * @brief MPU specific constants.\n */\n    #if ( configENABLE_MPU == 1 )\n        #define portUSING_MPU_WRAPPERS    1\n        #define portPRIVILEGE_BIT         ( 0x80000000UL )\n    #else\n        #define portPRIVILEGE_BIT         ( 0x0UL )\n    #endif /* configENABLE_MPU */\n\n/* MPU settings that can be overriden in FreeRTOSConfig.h. */\n#ifndef configTOTAL_MPU_REGIONS\n    /* Define to 8 for backward compatibility. */\n    #define configTOTAL_MPU_REGIONS       ( 8UL )\n#endif\n\n/* MPU regions. */\n    #define portPRIVILEGED_FLASH_REGION                   ( 0UL )\n    #define portUNPRIVILEGED_FLASH_REGION                 ( 1UL )\n    #define portUNPRIVILEGED_SYSCALLS_REGION              ( 2UL )\n    #define portPRIVILEGED_RAM_REGION                     ( 3UL )\n    #define portSTACK_REGION                              ( 4UL )\n    #define portFIRST_CONFIGURABLE_REGION                 ( 5UL )\n    #define portLAST_CONFIGURABLE_REGION                  ( configTOTAL_MPU_REGIONS - 1UL )\n    #define portNUM_CONFIGURABLE_REGIONS                  ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )\n    #define portTOTAL_NUM_REGIONS                         ( portNUM_CONFIGURABLE_REGIONS + 1 )   /* Plus one to make space for the stack region. */\n\n/* Device memory attributes used in MPU_MAIR registers.\n *\n * 8-bit values encoded as follows:\n *  Bit[7:4] - 0000 - Device Memory\n *  Bit[3:2] - 00 --> Device-nGnRnE\n *\t\t\t\t01 --> Device-nGnRE\n *\t\t\t\t10 --> Device-nGRE\n *\t\t\t\t11 --> Device-GRE\n *  Bit[1:0] - 00, Reserved.\n */\n    #define portMPU_DEVICE_MEMORY_nGnRnE                  ( 0x00 )   /* 0000 0000 */\n    #define portMPU_DEVICE_MEMORY_nGnRE                   ( 0x04 )   /* 0000 0100 */\n    #define portMPU_DEVICE_MEMORY_nGRE                    ( 0x08 )   /* 0000 1000 */\n    #define portMPU_DEVICE_MEMORY_GRE                     ( 0x0C )   /* 0000 1100 */\n\n/* Normal memory attributes used in MPU_MAIR registers. */\n    #define portMPU_NORMAL_MEMORY_NON_CACHEABLE           ( 0x44 )   /* Non-cacheable. */\n    #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE    ( 0xFF )   /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */\n\n/* Attributes used in MPU_RBAR registers. */\n    #define portMPU_REGION_NON_SHAREABLE                  ( 0UL << 3UL )\n    #define portMPU_REGION_INNER_SHAREABLE                ( 1UL << 3UL )\n    #define portMPU_REGION_OUTER_SHAREABLE                ( 2UL << 3UL )\n\n    #define portMPU_REGION_PRIVILEGED_READ_WRITE          ( 0UL << 1UL )\n    #define portMPU_REGION_READ_WRITE                     ( 1UL << 1UL )\n    #define portMPU_REGION_PRIVILEGED_READ_ONLY           ( 2UL << 1UL )\n    #define portMPU_REGION_READ_ONLY                      ( 3UL << 1UL )\n\n    #define portMPU_REGION_EXECUTE_NEVER                  ( 1UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Settings to define an MPU region.\n */\n    typedef struct MPURegionSettings\n    {\n        uint32_t ulRBAR; /**< RBAR for the region. */\n        uint32_t ulRLAR; /**< RLAR for the region. */\n    } MPURegionSettings_t;\n\n/**\n * @brief MPU settings as stored in the TCB.\n */\n    typedef struct MPU_SETTINGS\n    {\n        uint32_t ulMAIR0;                                              /**< MAIR0 for the task containing attributes for all the 4 per task regions. */\n        MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */\n    } xMPU_SETTINGS;\n/*-----------------------------------------------------------*/\n\n/**\n * @brief SVC numbers.\n */\n    #define portSVC_ALLOCATE_SECURE_CONTEXT    0\n    #define portSVC_FREE_SECURE_CONTEXT        1\n    #define portSVC_START_SCHEDULER            2\n    #define portSVC_RAISE_PRIVILEGE            3\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Scheduler utilities.\n */\n    #define portYIELD()                                 vPortYield()\n    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )\n    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )\n    #define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )\n    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Critical section management.\n */\n    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulSetInterruptMask()\n    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vClearInterruptMask( x )\n    #define portENTER_CRITICAL()                      vPortEnterCritical()\n    #define portEXIT_CRITICAL()                       vPortExitCritical()\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Tickless idle/low power functionality.\n */\n    #ifndef portSUPPRESS_TICKS_AND_SLEEP\n        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );\n        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )\n    #endif\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Task function macros as described on the FreeRTOS.org WEB site.\n */\n    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )\n    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )\n/*-----------------------------------------------------------*/\n\n    #if ( configENABLE_TRUSTZONE == 1 )\n\n/**\n * @brief Allocate a secure context for the task.\n *\n * Tasks are not created with a secure context. Any task that is going to call\n * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a\n * secure context before it calls any secure function.\n *\n * @param[in] ulSecureStackSize The size of the secure stack to be allocated.\n */\n        #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )\n\n/**\n * @brief Called when a task is deleted to delete the task's secure context,\n * if it has one.\n *\n * @param[in] pxTCB The TCB of the task being deleted.\n */\n        #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )\n    #endif /* configENABLE_TRUSTZONE */\n/*-----------------------------------------------------------*/\n\n    #if ( configENABLE_MPU == 1 )\n\n/**\n * @brief Checks whether or not the processor is privileged.\n *\n * @return 1 if the processor is already privileged, 0 otherwise.\n */\n        #define portIS_PRIVILEGED()      xIsPrivileged()\n\n/**\n * @brief Raise an SVC request to raise privilege.\n *\n * The SVC handler checks that the SVC was raised from a system call and only\n * then it raises the privilege. If this is called from any other place,\n * the privilege is not raised.\n */\n        #define portRAISE_PRIVILEGE()    __asm volatile ( \"svc %0 \\n\" ::\"i\" ( portSVC_RAISE_PRIVILEGE ) : \"memory\" );\n\n/**\n * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\n * register.\n */\n        #define portRESET_PRIVILEGE()    vResetPrivilege()\n    #else\n        #define portIS_PRIVILEGED()\n        #define portRAISE_PRIVILEGE()\n        #define portRESET_PRIVILEGE()\n    #endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Barriers.\n */\n    #define portMEMORY_BARRIER()    __asm volatile ( \"\" ::: \"memory\" )\n/*-----------------------------------------------------------*/\n\n    #ifdef __cplusplus\n        }\n    #endif\n\n#endif /* PORTMACROCOMMON_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM85/secure/secure_context.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Secure context includes. */\n#include \"secure_context.h\"\n\n/* Secure heap includes. */\n#include \"secure_heap.h\"\n\n/* Secure port macros. */\n#include \"secure_port_macros.h\"\n\n/**\n * @brief CONTROL value for privileged tasks.\n *\n * Bit[0] - 0 --> Thread mode is privileged.\n * Bit[1] - 1 --> Thread mode uses PSP.\n */\n#define securecontextCONTROL_VALUE_PRIVILEGED      0x02\n\n/**\n * @brief CONTROL value for un-privileged tasks.\n *\n * Bit[0] - 1 --> Thread mode is un-privileged.\n * Bit[1] - 1 --> Thread mode uses PSP.\n */\n#define securecontextCONTROL_VALUE_UNPRIVILEGED    0x03\n\n/**\n * @brief Size of stack seal values in bytes.\n */\n#define securecontextSTACK_SEAL_SIZE               8\n\n/**\n * @brief Stack seal value as recommended by ARM.\n */\n#define securecontextSTACK_SEAL_VALUE              0xFEF5EDA5\n\n/**\n * @brief Maximum number of secure contexts.\n */\n#ifndef secureconfigMAX_SECURE_CONTEXTS\n    #define secureconfigMAX_SECURE_CONTEXTS        8UL\n#endif\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Pre-allocated array of secure contexts.\n */\nSecureContext_t xSecureContexts[ secureconfigMAX_SECURE_CONTEXTS ];\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Get a free secure context for a task from the secure context pool (xSecureContexts).\n *\n * This function ensures that only one secure context is allocated for a task.\n *\n * @param[in] pvTaskHandle The task handle for which the secure context is allocated.\n *\n * @return Index of a free secure context in the xSecureContexts array.\n */\nstatic uint32_t ulGetSecureContext( void * pvTaskHandle );\n\n/**\n * @brief Return the secure context to the secure context pool (xSecureContexts).\n *\n * @param[in] ulSecureContextIndex Index of the context in the xSecureContexts array.\n */\nstatic void vReturnSecureContext( uint32_t ulSecureContextIndex );\n\n/* These are implemented in assembly. */\nextern void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext );\nextern void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext );\n/*-----------------------------------------------------------*/\n\nstatic uint32_t ulGetSecureContext( void * pvTaskHandle )\n{\n    /* Start with invalid index. */\n    uint32_t i, ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS;\n\n    for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ )\n    {\n        if( ( xSecureContexts[ i ].pucCurrentStackPointer == NULL ) &&\n            ( xSecureContexts[ i ].pucStackLimit == NULL ) &&\n            ( xSecureContexts[ i ].pucStackStart == NULL ) &&\n            ( xSecureContexts[ i ].pvTaskHandle == NULL ) &&\n            ( ulSecureContextIndex == secureconfigMAX_SECURE_CONTEXTS ) )\n        {\n            ulSecureContextIndex = i;\n        }\n        else if( xSecureContexts[ i ].pvTaskHandle == pvTaskHandle )\n        {\n            /* A task can only have one secure context. Do not allocate a second\n             * context for the same task. */\n            ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS;\n            break;\n        }\n    }\n\n    return ulSecureContextIndex;\n}\n/*-----------------------------------------------------------*/\n\nstatic void vReturnSecureContext( uint32_t ulSecureContextIndex )\n{\n    xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = NULL;\n    xSecureContexts[ ulSecureContextIndex ].pucStackLimit = NULL;\n    xSecureContexts[ ulSecureContextIndex ].pucStackStart = NULL;\n    xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = NULL;\n}\n/*-----------------------------------------------------------*/\n\nsecureportNON_SECURE_CALLABLE void SecureContext_Init( void )\n{\n    uint32_t ulIPSR, i;\n    static uint32_t ulSecureContextsInitialized = 0;\n\n    /* Read the Interrupt Program Status Register (IPSR) value. */\n    secureportREAD_IPSR( ulIPSR );\n\n    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\n     * when the processor is running in the Thread Mode. */\n    if( ( ulIPSR != 0 ) && ( ulSecureContextsInitialized == 0 ) )\n    {\n        /* Ensure to initialize secure contexts only once. */\n        ulSecureContextsInitialized = 1;\n\n        /* No stack for thread mode until a task's context is loaded. */\n        secureportSET_PSPLIM( securecontextNO_STACK );\n        secureportSET_PSP( securecontextNO_STACK );\n\n        /* Initialize all secure contexts. */\n        for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ )\n        {\n            xSecureContexts[ i ].pucCurrentStackPointer = NULL;\n            xSecureContexts[ i ].pucStackLimit = NULL;\n            xSecureContexts[ i ].pucStackStart = NULL;\n            xSecureContexts[ i ].pvTaskHandle = NULL;\n        }\n\n        #if ( configENABLE_MPU == 1 )\n            {\n                /* Configure thread mode to use PSP and to be unprivileged. */\n                secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );\n            }\n        #else /* configENABLE_MPU */\n            {\n                /* Configure thread mode to use PSP and to be privileged. */\n                secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );\n            }\n        #endif /* configENABLE_MPU */\n    }\n}\n/*-----------------------------------------------------------*/\n\n#if ( configENABLE_MPU == 1 )\n    secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,\n                                                                                       uint32_t ulIsTaskPrivileged,\n                                                                                       void * pvTaskHandle )\n#else /* configENABLE_MPU */\n    secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,\n                                                                                       void * pvTaskHandle )\n#endif /* configENABLE_MPU */\n{\n    uint8_t * pucStackMemory = NULL;\n    uint8_t * pucStackLimit;\n    uint32_t ulIPSR, ulSecureContextIndex;\n    SecureContextHandle_t xSecureContextHandle = securecontextINVALID_CONTEXT_ID;\n\n    #if ( configENABLE_MPU == 1 )\n        uint32_t * pulCurrentStackPointer = NULL;\n    #endif /* configENABLE_MPU */\n\n    /* Read the Interrupt Program Status Register (IPSR) and Process Stack Limit\n     * Register (PSPLIM) value. */\n    secureportREAD_IPSR( ulIPSR );\n    secureportREAD_PSPLIM( pucStackLimit );\n\n    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\n     * when the processor is running in the Thread Mode.\n     * Also do nothing, if a secure context us already loaded. PSPLIM is set to\n     * securecontextNO_STACK when no secure context is loaded. */\n    if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) )\n    {\n        /* Ontain a free secure context. */\n        ulSecureContextIndex = ulGetSecureContext( pvTaskHandle );\n\n        /* Were we able to get a free context? */\n        if( ulSecureContextIndex < secureconfigMAX_SECURE_CONTEXTS )\n        {\n            /* Allocate the stack space. */\n            pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE );\n\n            if( pucStackMemory != NULL )\n            {\n                /* Since stack grows down, the starting point will be the last\n                 * location. Note that this location is next to the last\n                 * allocated byte for stack (excluding the space for seal values)\n                 * because the hardware decrements the stack pointer before\n                 * writing i.e. if stack pointer is 0x2, a push operation will\n                 * decrement the stack pointer to 0x1 and then write at 0x1. */\n                xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize;\n\n                /* Seal the created secure process stack. */\n                *( uint32_t * )( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE;\n                *( uint32_t * )( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE;\n\n                /* The stack cannot go beyond this location. This value is\n                 * programmed in the PSPLIM register on context switch.*/\n                xSecureContexts[ ulSecureContextIndex ].pucStackLimit = pucStackMemory;\n\n                xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle;\n\n                #if ( configENABLE_MPU == 1 )\n                    {\n                        /* Store the correct CONTROL value for the task on the stack.\n                         * This value is programmed in the CONTROL register on\n                         * context switch. */\n                        pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart;\n                        pulCurrentStackPointer--;\n\n                        if( ulIsTaskPrivileged )\n                        {\n                            *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;\n                        }\n                        else\n                        {\n                            *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;\n                        }\n\n                        /* Store the current stack pointer. This value is programmed in\n                         * the PSP register on context switch. */\n                        xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;\n                    }\n                #else /* configENABLE_MPU */\n                    {\n                        /* Current SP is set to the starting of the stack. This\n                         * value programmed in the PSP register on context switch. */\n                        xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart;\n                    }\n                #endif /* configENABLE_MPU */\n\n                /* Ensure to never return 0 as a valid context handle. */\n                xSecureContextHandle = ulSecureContextIndex + 1UL;\n            }\n        }\n    }\n\n    return xSecureContextHandle;\n}\n/*-----------------------------------------------------------*/\n\nsecureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )\n{\n    uint32_t ulIPSR, ulSecureContextIndex;\n\n    /* Read the Interrupt Program Status Register (IPSR) value. */\n    secureportREAD_IPSR( ulIPSR );\n\n    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\n     * when the processor is running in the Thread Mode. */\n    if( ulIPSR != 0 )\n    {\n        /* Only free if a valid context handle is passed. */\n        if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) )\n        {\n            ulSecureContextIndex = xSecureContextHandle - 1UL;\n\n            /* Ensure that the secure context being deleted is associated with\n             * the task. */\n            if( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle )\n            {\n                /* Free the stack space. */\n                vPortFree( xSecureContexts[ ulSecureContextIndex ].pucStackLimit );\n\n                /* Return the secure context back to the free secure contexts pool. */\n                vReturnSecureContext( ulSecureContextIndex );\n            }\n        }\n    }\n}\n/*-----------------------------------------------------------*/\n\nsecureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )\n{\n    uint8_t * pucStackLimit;\n    uint32_t ulSecureContextIndex;\n\n    if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) )\n    {\n        ulSecureContextIndex = xSecureContextHandle - 1UL;\n\n        secureportREAD_PSPLIM( pucStackLimit );\n\n        /* Ensure that no secure context is loaded and the task is loading it's\n         * own context. */\n        if( ( pucStackLimit == securecontextNO_STACK ) &&\n            ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) )\n        {\n            SecureContext_LoadContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) );\n        }\n    }\n}\n/*-----------------------------------------------------------*/\n\nsecureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )\n{\n    uint8_t * pucStackLimit;\n    uint32_t ulSecureContextIndex;\n\n    if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) )\n    {\n        ulSecureContextIndex = xSecureContextHandle - 1UL;\n\n        secureportREAD_PSPLIM( pucStackLimit );\n\n        /* Ensure that task's context is loaded and the task is saving it's own\n         * context. */\n        if( ( xSecureContexts[ ulSecureContextIndex ].pucStackLimit == pucStackLimit ) &&\n            ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) )\n        {\n            SecureContext_SaveContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) );\n        }\n    }\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM85/secure/secure_context.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef __SECURE_CONTEXT_H__\n#define __SECURE_CONTEXT_H__\n\n/* Standard includes. */\n#include <stdint.h>\n\n/* FreeRTOS includes. */\n#include \"FreeRTOSConfig.h\"\n\n/**\n * @brief PSP value when no secure context is loaded.\n */\n#define securecontextNO_STACK               0x0\n\n/**\n * @brief Invalid context ID.\n */\n#define securecontextINVALID_CONTEXT_ID     0UL\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Structure to represent a secure context.\n *\n * @note Since stack grows down, pucStackStart is the highest address while\n * pucStackLimit is the first address of the allocated memory.\n */\ntypedef struct SecureContext\n{\n    uint8_t * pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */\n    uint8_t * pucStackLimit;          /**< Last location of the stack memory (PSPLIM). */\n    uint8_t * pucStackStart;          /**< First location of the stack memory. */\n    void * pvTaskHandle;              /**< Task handle of the task this context is associated with. */\n} SecureContext_t;\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Opaque handle for a secure context.\n */\ntypedef uint32_t SecureContextHandle_t;\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Initializes the secure context management system.\n *\n * PSP is set to NULL and therefore a task must allocate and load a context\n * before calling any secure side function in the thread mode.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n */\nvoid SecureContext_Init( void );\n\n/**\n * @brief Allocates a context on the secure side.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n *\n * @param[in] ulSecureStackSize Size of the stack to allocate on secure side.\n * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise.\n *\n * @return Opaque context handle if context is successfully allocated, NULL\n * otherwise.\n */\n#if ( configENABLE_MPU == 1 )\n    SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,\n                                                         uint32_t ulIsTaskPrivileged,\n                                                         void * pvTaskHandle );\n#else /* configENABLE_MPU */\n    SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,\n                                                         void * pvTaskHandle );\n#endif /* configENABLE_MPU */\n\n/**\n * @brief Frees the given context.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n *\n * @param[in] xSecureContextHandle Context handle corresponding to the\n * context to be freed.\n */\nvoid SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );\n\n/**\n * @brief Loads the given context.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n *\n * @param[in] xSecureContextHandle Context handle corresponding to the context\n * to be loaded.\n */\nvoid SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );\n\n/**\n * @brief Saves the given context.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n *\n * @param[in] xSecureContextHandle Context handle corresponding to the context\n * to be saved.\n */\nvoid SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );\n\n#endif /* __SECURE_CONTEXT_H__ */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM85/secure/secure_context_port_asm.s",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n    SECTION .text:CODE:NOROOT(2)\n    THUMB\n\n/* Including FreeRTOSConfig.h here will cause build errors if the header file\ncontains code not understood by the assembler - for example the 'extern' keyword.\nTo avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so\nthe code is included in C files but excluded by the preprocessor in assembly\nfiles (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */\n#include \"FreeRTOSConfig.h\"\n\n    PUBLIC SecureContext_LoadContextAsm\n    PUBLIC SecureContext_SaveContextAsm\n/*-----------------------------------------------------------*/\n\nSecureContext_LoadContextAsm:\n    /* pxSecureContext value is in r0. */\n    mrs r1, ipsr                        /* r1 = IPSR. */\n    cbz r1, load_ctx_therad_mode        /* Do nothing if the processor is running in the Thread Mode. */\n    ldmia r0!, {r1, r2}                 /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */\n\n#if ( configENABLE_MPU == 1 )\n    ldmia r1!, {r3}                     /* Read CONTROL register value from task's stack. r3 = CONTROL. */\n    msr control, r3                     /* CONTROL = r3. */\n#endif /* configENABLE_MPU */\n\n    msr psplim, r2                      /* PSPLIM = r2. */\n    msr psp, r1                         /* PSP = r1. */\n\n    load_ctx_therad_mode:\n        bx lr\n/*-----------------------------------------------------------*/\n\nSecureContext_SaveContextAsm:\n    /* pxSecureContext value is in r0. */\n    mrs r1, ipsr                        /* r1 = IPSR. */\n    cbz r1, save_ctx_therad_mode        /* Do nothing if the processor is running in the Thread Mode. */\n    mrs r1, psp                         /* r1 = PSP. */\n\n#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )\n    vstmdb r1!, {s0}                    /* Trigger the deferred stacking of FPU registers. */\n    vldmia r1!, {s0}                    /* Nullify the effect of the previous statement. */\n#endif /* configENABLE_FPU || configENABLE_MVE */\n\n#if ( configENABLE_MPU == 1 )\n    mrs r2, control                     /* r2 = CONTROL. */\n    stmdb r1!, {r2}                     /* Store CONTROL value on the stack. */\n#endif /* configENABLE_MPU */\n\n    str r1, [r0]                        /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */\n    movs r1, #0                         /* r1 = securecontextNO_STACK. */\n    msr psplim, r1                      /* PSPLIM = securecontextNO_STACK. */\n    msr psp, r1                         /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */\n\n    save_ctx_therad_mode:\n        bx lr\n/*-----------------------------------------------------------*/\n\n    END\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM85/secure/secure_heap.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Standard includes. */\n#include <stdint.h>\n\n/* Secure context heap includes. */\n#include \"secure_heap.h\"\n\n/* Secure port macros. */\n#include \"secure_port_macros.h\"\n\n/**\n * @brief Total heap size.\n */\n#ifndef secureconfigTOTAL_HEAP_SIZE\n    #define secureconfigTOTAL_HEAP_SIZE    ( ( ( size_t ) ( 10 * 1024 ) ) )\n#endif\n\n/* No test marker by default. */\n#ifndef mtCOVERAGE_TEST_MARKER\n    #define mtCOVERAGE_TEST_MARKER()\n#endif\n\n/* No tracing by default. */\n#ifndef traceMALLOC\n    #define traceMALLOC( pvReturn, xWantedSize )\n#endif\n\n/* No tracing by default. */\n#ifndef traceFREE\n    #define traceFREE( pv, xBlockSize )\n#endif\n\n/* Block sizes must not get too small. */\n#define secureheapMINIMUM_BLOCK_SIZE    ( ( size_t ) ( xHeapStructSize << 1 ) )\n\n/* Assumes 8bit bytes! */\n#define secureheapBITS_PER_BYTE         ( ( size_t ) 8 )\n/*-----------------------------------------------------------*/\n\n/* Allocate the memory for the heap. */\n#if ( configAPPLICATION_ALLOCATED_HEAP == 1 )\n\n/* The application writer has already defined the array used for the RTOS\n* heap - probably so it can be placed in a special segment or address. */\n    extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];\n#else /* configAPPLICATION_ALLOCATED_HEAP */\n    static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];\n#endif /* configAPPLICATION_ALLOCATED_HEAP */\n\n/**\n * @brief The linked list structure.\n *\n * This is used to link free blocks in order of their memory address.\n */\ntypedef struct A_BLOCK_LINK\n{\n    struct A_BLOCK_LINK * pxNextFreeBlock; /**< The next free block in the list. */\n    size_t xBlockSize;                     /**< The size of the free block. */\n} BlockLink_t;\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Called automatically to setup the required heap structures the first\n * time pvPortMalloc() is called.\n */\nstatic void prvHeapInit( void );\n\n/**\n * @brief Inserts a block of memory that is being freed into the correct\n * position in the list of free memory blocks.\n *\n * The block being freed will be merged with the block in front it and/or the\n * block behind it if the memory blocks are adjacent to each other.\n *\n * @param[in] pxBlockToInsert The block being freed.\n */\nstatic void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert );\n/*-----------------------------------------------------------*/\n\n/**\n * @brief The size of the structure placed at the beginning of each allocated\n * memory block must by correctly byte aligned.\n */\nstatic const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );\n\n/**\n * @brief Create a couple of list links to mark the start and end of the list.\n */\nstatic BlockLink_t xStart;\nstatic BlockLink_t * pxEnd = NULL;\n\n/**\n * @brief Keeps track of the number of free bytes remaining, but says nothing\n * about fragmentation.\n */\nstatic size_t xFreeBytesRemaining = 0U;\nstatic size_t xMinimumEverFreeBytesRemaining = 0U;\n\n/**\n * @brief Gets set to the top bit of an size_t type.\n *\n * When this bit in the xBlockSize member of an BlockLink_t structure is set\n * then the block belongs to the application. When the bit is free the block is\n * still part of the free heap space.\n */\nstatic size_t xBlockAllocatedBit = 0;\n/*-----------------------------------------------------------*/\n\nstatic void prvHeapInit( void )\n{\n    BlockLink_t * pxFirstFreeBlock;\n    uint8_t * pucAlignedHeap;\n    size_t uxAddress;\n    size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE;\n\n    /* Ensure the heap starts on a correctly aligned boundary. */\n    uxAddress = ( size_t ) ucHeap;\n\n    if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 )\n    {\n        uxAddress += ( secureportBYTE_ALIGNMENT - 1 );\n        uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );\n        xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;\n    }\n\n    pucAlignedHeap = ( uint8_t * ) uxAddress;\n\n    /* xStart is used to hold a pointer to the first item in the list of free\n     * blocks.  The void cast is used to prevent compiler warnings. */\n    xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;\n    xStart.xBlockSize = ( size_t ) 0;\n\n    /* pxEnd is used to mark the end of the list of free blocks and is inserted\n     * at the end of the heap space. */\n    uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;\n    uxAddress -= xHeapStructSize;\n    uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );\n    pxEnd = ( void * ) uxAddress;\n    pxEnd->xBlockSize = 0;\n    pxEnd->pxNextFreeBlock = NULL;\n\n    /* To start with there is a single free block that is sized to take up the\n     * entire heap space, minus the space taken by pxEnd. */\n    pxFirstFreeBlock = ( void * ) pucAlignedHeap;\n    pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;\n    pxFirstFreeBlock->pxNextFreeBlock = pxEnd;\n\n    /* Only one block exists - and it covers the entire usable heap space. */\n    xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;\n    xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;\n\n    /* Work out the position of the top bit in a size_t variable. */\n    xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert )\n{\n    BlockLink_t * pxIterator;\n    uint8_t * puc;\n\n    /* Iterate through the list until a block is found that has a higher address\n     * than the block being inserted. */\n    for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )\n    {\n        /* Nothing to do here, just iterate to the right position. */\n    }\n\n    /* Do the block being inserted, and the block it is being inserted after\n     * make a contiguous block of memory? */\n    puc = ( uint8_t * ) pxIterator;\n\n    if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )\n    {\n        pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;\n        pxBlockToInsert = pxIterator;\n    }\n    else\n    {\n        mtCOVERAGE_TEST_MARKER();\n    }\n\n    /* Do the block being inserted, and the block it is being inserted before\n     * make a contiguous block of memory? */\n    puc = ( uint8_t * ) pxBlockToInsert;\n\n    if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )\n    {\n        if( pxIterator->pxNextFreeBlock != pxEnd )\n        {\n            /* Form one big block from the two blocks. */\n            pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;\n            pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;\n        }\n        else\n        {\n            pxBlockToInsert->pxNextFreeBlock = pxEnd;\n        }\n    }\n    else\n    {\n        pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;\n    }\n\n    /* If the block being inserted plugged a gab, so was merged with the block\n     * before and the block after, then it's pxNextFreeBlock pointer will have\n     * already been set, and should not be set here as that would make it point\n     * to itself. */\n    if( pxIterator != pxBlockToInsert )\n    {\n        pxIterator->pxNextFreeBlock = pxBlockToInsert;\n    }\n    else\n    {\n        mtCOVERAGE_TEST_MARKER();\n    }\n}\n/*-----------------------------------------------------------*/\n\nvoid * pvPortMalloc( size_t xWantedSize )\n{\n    BlockLink_t * pxBlock;\n    BlockLink_t * pxPreviousBlock;\n    BlockLink_t * pxNewBlockLink;\n    void * pvReturn = NULL;\n\n    /* If this is the first call to malloc then the heap will require\n     * initialisation to setup the list of free blocks. */\n    if( pxEnd == NULL )\n    {\n        prvHeapInit();\n    }\n    else\n    {\n        mtCOVERAGE_TEST_MARKER();\n    }\n\n    /* Check the requested block size is not so large that the top bit is set.\n     * The top bit of the block size member of the BlockLink_t structure is used\n     * to determine who owns the block - the application or the kernel, so it\n     * must be free. */\n    if( ( xWantedSize & xBlockAllocatedBit ) == 0 )\n    {\n        /* The wanted size is increased so it can contain a BlockLink_t\n         * structure in addition to the requested amount of bytes. */\n        if( xWantedSize > 0 )\n        {\n            xWantedSize += xHeapStructSize;\n\n            /* Ensure that blocks are always aligned to the required number of\n             * bytes. */\n            if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )\n            {\n                /* Byte alignment required. */\n                xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );\n                secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n\n        if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )\n        {\n            /* Traverse the list from the start (lowest address) block until\n             * one of adequate size is found. */\n            pxPreviousBlock = &xStart;\n            pxBlock = xStart.pxNextFreeBlock;\n\n            while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )\n            {\n                pxPreviousBlock = pxBlock;\n                pxBlock = pxBlock->pxNextFreeBlock;\n            }\n\n            /* If the end marker was reached then a block of adequate size was\n             * not found. */\n            if( pxBlock != pxEnd )\n            {\n                /* Return the memory space pointed to - jumping over the\n                 * BlockLink_t structure at its start. */\n                pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );\n\n                /* This block is being returned for use so must be taken out\n                 * of the list of free blocks. */\n                pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;\n\n                /* If the block is larger than required it can be split into\n                 * two. */\n                if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE )\n                {\n                    /* This block is to be split into two.  Create a new\n                     * block following the number of bytes requested. The void\n                     * cast is used to prevent byte alignment warnings from the\n                     * compiler. */\n                    pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );\n                    secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 );\n\n                    /* Calculate the sizes of two blocks split from the single\n                     * block. */\n                    pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;\n                    pxBlock->xBlockSize = xWantedSize;\n\n                    /* Insert the new block into the list of free blocks. */\n                    prvInsertBlockIntoFreeList( pxNewBlockLink );\n                }\n                else\n                {\n                    mtCOVERAGE_TEST_MARKER();\n                }\n\n                xFreeBytesRemaining -= pxBlock->xBlockSize;\n\n                if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )\n                {\n                    xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;\n                }\n                else\n                {\n                    mtCOVERAGE_TEST_MARKER();\n                }\n\n                /* The block is being returned - it is allocated and owned by\n                 * the application and has no \"next\" block. */\n                pxBlock->xBlockSize |= xBlockAllocatedBit;\n                pxBlock->pxNextFreeBlock = NULL;\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n    }\n    else\n    {\n        mtCOVERAGE_TEST_MARKER();\n    }\n\n    traceMALLOC( pvReturn, xWantedSize );\n\n    #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )\n        {\n            if( pvReturn == NULL )\n            {\n                extern void vApplicationMallocFailedHook( void );\n                vApplicationMallocFailedHook();\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n    #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */\n\n    secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );\n    return pvReturn;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortFree( void * pv )\n{\n    uint8_t * puc = ( uint8_t * ) pv;\n    BlockLink_t * pxLink;\n\n    if( pv != NULL )\n    {\n        /* The memory being freed will have an BlockLink_t structure immediately\n         * before it. */\n        puc -= xHeapStructSize;\n\n        /* This casting is to keep the compiler from issuing warnings. */\n        pxLink = ( void * ) puc;\n\n        /* Check the block is actually allocated. */\n        secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );\n        secureportASSERT( pxLink->pxNextFreeBlock == NULL );\n\n        if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )\n        {\n            if( pxLink->pxNextFreeBlock == NULL )\n            {\n                /* The block is being returned to the heap - it is no longer\n                 * allocated. */\n                pxLink->xBlockSize &= ~xBlockAllocatedBit;\n\n                secureportDISABLE_NON_SECURE_INTERRUPTS();\n                {\n                    /* Add this block to the list of free blocks. */\n                    xFreeBytesRemaining += pxLink->xBlockSize;\n                    traceFREE( pv, pxLink->xBlockSize );\n                    prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );\n                }\n                secureportENABLE_NON_SECURE_INTERRUPTS();\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n    }\n}\n/*-----------------------------------------------------------*/\n\nsize_t xPortGetFreeHeapSize( void )\n{\n    return xFreeBytesRemaining;\n}\n/*-----------------------------------------------------------*/\n\nsize_t xPortGetMinimumEverFreeHeapSize( void )\n{\n    return xMinimumEverFreeBytesRemaining;\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM85/secure/secure_heap.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef __SECURE_HEAP_H__\n#define __SECURE_HEAP_H__\n\n/* Standard includes. */\n#include <stdlib.h>\n\n/**\n * @brief Allocates memory from heap.\n *\n * @param[in] xWantedSize The size of the memory to be allocated.\n *\n * @return Pointer to the memory region if the allocation is successful, NULL\n * otherwise.\n */\nvoid * pvPortMalloc( size_t xWantedSize );\n\n/**\n * @brief Frees the previously allocated memory.\n *\n * @param[in] pv Pointer to the memory to be freed.\n */\nvoid vPortFree( void * pv );\n\n/**\n * @brief Get the free heap size.\n *\n * @return Free heap size.\n */\nsize_t xPortGetFreeHeapSize( void );\n\n/**\n * @brief Get the minimum ever free heap size.\n *\n * @return Minimum ever free heap size.\n */\nsize_t xPortGetMinimumEverFreeHeapSize( void );\n\n#endif /* __SECURE_HEAP_H__ */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM85/secure/secure_init.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Standard includes. */\n#include <stdint.h>\n\n/* Secure init includes. */\n#include \"secure_init.h\"\n\n/* Secure port macros. */\n#include \"secure_port_macros.h\"\n\n/**\n * @brief Constants required to manipulate the SCB.\n */\n#define secureinitSCB_AIRCR                 ( ( volatile uint32_t * ) 0xe000ed0c )  /* Application Interrupt and Reset Control Register. */\n#define secureinitSCB_AIRCR_VECTKEY_POS     ( 16UL )\n#define secureinitSCB_AIRCR_VECTKEY_MASK    ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )\n#define secureinitSCB_AIRCR_PRIS_POS        ( 14UL )\n#define secureinitSCB_AIRCR_PRIS_MASK       ( 1UL << secureinitSCB_AIRCR_PRIS_POS )\n\n/**\n * @brief Constants required to manipulate the FPU.\n */\n#define secureinitFPCCR                     ( ( volatile uint32_t * ) 0xe000ef34 )  /* Floating Point Context Control Register. */\n#define secureinitFPCCR_LSPENS_POS          ( 29UL )\n#define secureinitFPCCR_LSPENS_MASK         ( 1UL << secureinitFPCCR_LSPENS_POS )\n#define secureinitFPCCR_TS_POS              ( 26UL )\n#define secureinitFPCCR_TS_MASK             ( 1UL << secureinitFPCCR_TS_POS )\n\n#define secureinitNSACR                     ( ( volatile uint32_t * ) 0xe000ed8c )  /* Non-secure Access Control Register. */\n#define secureinitNSACR_CP10_POS            ( 10UL )\n#define secureinitNSACR_CP10_MASK           ( 1UL << secureinitNSACR_CP10_POS )\n#define secureinitNSACR_CP11_POS            ( 11UL )\n#define secureinitNSACR_CP11_MASK           ( 1UL << secureinitNSACR_CP11_POS )\n/*-----------------------------------------------------------*/\n\nsecureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void )\n{\n    uint32_t ulIPSR;\n\n    /* Read the Interrupt Program Status Register (IPSR) value. */\n    secureportREAD_IPSR( ulIPSR );\n\n    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\n     * when the processor is running in the Thread Mode. */\n    if( ulIPSR != 0 )\n    {\n        *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |\n                                   ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |\n                                   ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK );\n    }\n}\n/*-----------------------------------------------------------*/\n\nsecureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )\n{\n    uint32_t ulIPSR;\n\n    /* Read the Interrupt Program Status Register (IPSR) value. */\n    secureportREAD_IPSR( ulIPSR );\n\n    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\n     * when the processor is running in the Thread Mode. */\n    if( ulIPSR != 0 )\n    {\n        /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is\n         * permitted. CP11 should be programmed to the same value as CP10. */\n        *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );\n\n        /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures\n         * that we can enable/disable lazy stacking in port.c file. */\n        *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK );\n\n        /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP\n         * registers (S16-S31) are also pushed to stack on exception entry and\n         * restored on exception return. */\n        *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );\n    }\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM85/secure/secure_init.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef __SECURE_INIT_H__\n#define __SECURE_INIT_H__\n\n/**\n * @brief De-prioritizes the non-secure exceptions.\n *\n * This is needed to ensure that the non-secure PendSV runs at the lowest\n * priority. Context switch is done in the non-secure PendSV handler.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n */\nvoid SecureInit_DePrioritizeNSExceptions( void );\n\n/**\n * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access.\n *\n * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point\n * Registers are not leaked to the non-secure side.\n *\n * @note This function must be called in the handler mode. It is no-op if called\n * in the thread mode.\n */\nvoid SecureInit_EnableNSFPUAccess( void );\n\n#endif /* __SECURE_INIT_H__ */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM85/secure/secure_port_macros.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef __SECURE_PORT_MACROS_H__\n#define __SECURE_PORT_MACROS_H__\n\n/**\n * @brief Byte alignment requirements.\n */\n#define secureportBYTE_ALIGNMENT         8\n#define secureportBYTE_ALIGNMENT_MASK    ( 0x0007 )\n\n/**\n * @brief Macro to declare a function as non-secure callable.\n */\n#if defined( __IAR_SYSTEMS_ICC__ )\n    #define secureportNON_SECURE_CALLABLE    __cmse_nonsecure_entry __root\n#else\n    #define secureportNON_SECURE_CALLABLE    __attribute__( ( cmse_nonsecure_entry ) ) __attribute__( ( used ) )\n#endif\n\n/**\n * @brief Set the secure PRIMASK value.\n */\n#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \\\n    __asm volatile ( \"msr primask, %0\" : : \"r\" ( ulPrimaskValue ) : \"memory\" )\n\n/**\n * @brief Set the non-secure PRIMASK value.\n */\n#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \\\n    __asm volatile ( \"msr primask_ns, %0\" : : \"r\" ( ulPrimaskValue ) : \"memory\" )\n\n/**\n * @brief Read the PSP value in the given variable.\n */\n#define secureportREAD_PSP( pucOutCurrentStackPointer ) \\\n    __asm volatile ( \"mrs %0, psp\"  : \"=r\" ( pucOutCurrentStackPointer ) )\n\n/**\n * @brief Set the PSP to the given value.\n */\n#define secureportSET_PSP( pucCurrentStackPointer ) \\\n    __asm volatile ( \"msr psp, %0\" : : \"r\" ( pucCurrentStackPointer ) )\n\n/**\n * @brief Read the PSPLIM value in the given variable.\n */\n#define secureportREAD_PSPLIM( pucOutStackLimit ) \\\n    __asm volatile ( \"mrs %0, psplim\"  : \"=r\" ( pucOutStackLimit ) )\n\n/**\n * @brief Set the PSPLIM to the given value.\n */\n#define secureportSET_PSPLIM( pucStackLimit ) \\\n    __asm volatile ( \"msr psplim, %0\" : : \"r\" ( pucStackLimit ) )\n\n/**\n * @brief Set the NonSecure MSP to the given value.\n */\n#define secureportSET_MSP_NS( pucMainStackPointer ) \\\n    __asm volatile ( \"msr msp_ns, %0\" : : \"r\" ( pucMainStackPointer ) )\n\n/**\n * @brief Set the CONTROL register to the given value.\n */\n#define secureportSET_CONTROL( ulControl ) \\\n    __asm volatile ( \"msr control, %0\" : : \"r\" ( ulControl ) : \"memory\" )\n\n/**\n * @brief Read the Interrupt Program Status Register (IPSR) value in the given\n * variable.\n */\n#define secureportREAD_IPSR( ulIPSR ) \\\n    __asm volatile ( \"mrs %0, ipsr\"  : \"=r\" ( ulIPSR ) )\n\n/**\n * @brief PRIMASK value to enable interrupts.\n */\n#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL     0\n\n/**\n * @brief PRIMASK value to disable interrupts.\n */\n#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL    1\n\n/**\n * @brief Disable secure interrupts.\n */\n#define secureportDISABLE_SECURE_INTERRUPTS()        secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )\n\n/**\n * @brief Disable non-secure interrupts.\n *\n * This effectively disables context switches.\n */\n#define secureportDISABLE_NON_SECURE_INTERRUPTS()    secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )\n\n/**\n * @brief Enable non-secure interrupts.\n */\n#define secureportENABLE_NON_SECURE_INTERRUPTS()     secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL )\n\n/**\n * @brief Assert definition.\n */\n#define secureportASSERT( x )                      \\\n    if( ( x ) == 0 )                               \\\n    {                                              \\\n        secureportDISABLE_SECURE_INTERRUPTS();     \\\n        secureportDISABLE_NON_SECURE_INTERRUPTS(); \\\n        for( ; ; ) {; }                            \\\n    }\n\n#endif /* __SECURE_PORT_MACROS_H__ */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM85_NTZ/non_secure/port.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\n * all the API functions to use the MPU wrappers. That should only be done when\n * task.h is included from an application file. */\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n/* MPU wrappers includes. */\n#include \"mpu_wrappers.h\"\n\n/* Portasm includes. */\n#include \"portasm.h\"\n\n#if ( configENABLE_TRUSTZONE == 1 )\n    /* Secure components includes. */\n    #include \"secure_context.h\"\n    #include \"secure_init.h\"\n#endif /* configENABLE_TRUSTZONE */\n\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/**\n * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only\n * i.e. the processor boots as secure and never jumps to the non-secure side.\n * The Trust Zone support in the port must be disabled in order to run FreeRTOS\n * on the secure side. The following are the valid configuration seetings:\n *\n * 1. Run FreeRTOS on the Secure Side:\n *    configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0\n *\n * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:\n *    configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1\n *\n * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:\n *    configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0\n */\n#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )\n    #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.\n#endif\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the NVIC.\n */\n#define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )\n#define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )\n#define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )\n#define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )\n#define portNVIC_SYSTICK_ENABLE_BIT           ( 1UL << 0UL )\n#define portNVIC_SYSTICK_INT_BIT              ( 1UL << 1UL )\n#define portNVIC_SYSTICK_CLK_BIT              ( 1UL << 2UL )\n#define portNVIC_SYSTICK_COUNT_FLAG_BIT       ( 1UL << 16UL )\n#define portNVIC_PEND_SYSTICK_CLEAR_BIT       ( 1UL << 25UL )\n#define portNVIC_PEND_SYSTICK_SET_BIT         ( 1UL << 26UL )\n#define portMIN_INTERRUPT_PRIORITY            ( 255UL )\n#define portNVIC_PENDSV_PRI                   ( portMIN_INTERRUPT_PRIORITY << 16UL )\n#define portNVIC_SYSTICK_PRI                  ( portMIN_INTERRUPT_PRIORITY << 24UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the SCB.\n */\n#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( volatile uint32_t * ) 0xe000ed24 )\n#define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the FPU.\n */\n#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 )              /* Coprocessor Access Control Register. */\n#define portCPACR_CP10_VALUE    ( 3UL )\n#define portCPACR_CP11_VALUE    portCPACR_CP10_VALUE\n#define portCPACR_CP10_POS      ( 20UL )\n#define portCPACR_CP11_POS      ( 22UL )\n\n#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 )              /* Floating Point Context Control Register. */\n#define portFPCCR_ASPEN_POS     ( 31UL )\n#define portFPCCR_ASPEN_MASK    ( 1UL << portFPCCR_ASPEN_POS )\n#define portFPCCR_LSPEN_POS     ( 30UL )\n#define portFPCCR_LSPEN_MASK    ( 1UL << portFPCCR_LSPEN_POS )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to manipulate the MPU.\n */\n#define portMPU_TYPE_REG                      ( *( ( volatile uint32_t * ) 0xe000ed90 ) )\n#define portMPU_CTRL_REG                      ( *( ( volatile uint32_t * ) 0xe000ed94 ) )\n#define portMPU_RNR_REG                       ( *( ( volatile uint32_t * ) 0xe000ed98 ) )\n\n#define portMPU_RBAR_REG                      ( *( ( volatile uint32_t * ) 0xe000ed9c ) )\n#define portMPU_RLAR_REG                      ( *( ( volatile uint32_t * ) 0xe000eda0 ) )\n\n#define portMPU_RBAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda4 ) )\n#define portMPU_RLAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda8 ) )\n\n#define portMPU_RBAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edac ) )\n#define portMPU_RLAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edb0 ) )\n\n#define portMPU_RBAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb4 ) )\n#define portMPU_RLAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb8 ) )\n\n#define portMPU_MAIR0_REG                     ( *( ( volatile uint32_t * ) 0xe000edc0 ) )\n#define portMPU_MAIR1_REG                     ( *( ( volatile uint32_t * ) 0xe000edc4 ) )\n\n#define portMPU_RBAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */\n#define portMPU_RLAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */\n\n#define portMPU_MAIR_ATTR0_POS                ( 0UL )\n#define portMPU_MAIR_ATTR0_MASK               ( 0x000000ff )\n\n#define portMPU_MAIR_ATTR1_POS                ( 8UL )\n#define portMPU_MAIR_ATTR1_MASK               ( 0x0000ff00 )\n\n#define portMPU_MAIR_ATTR2_POS                ( 16UL )\n#define portMPU_MAIR_ATTR2_MASK               ( 0x00ff0000 )\n\n#define portMPU_MAIR_ATTR3_POS                ( 24UL )\n#define portMPU_MAIR_ATTR3_MASK               ( 0xff000000 )\n\n#define portMPU_MAIR_ATTR4_POS                ( 0UL )\n#define portMPU_MAIR_ATTR4_MASK               ( 0x000000ff )\n\n#define portMPU_MAIR_ATTR5_POS                ( 8UL )\n#define portMPU_MAIR_ATTR5_MASK               ( 0x0000ff00 )\n\n#define portMPU_MAIR_ATTR6_POS                ( 16UL )\n#define portMPU_MAIR_ATTR6_MASK               ( 0x00ff0000 )\n\n#define portMPU_MAIR_ATTR7_POS                ( 24UL )\n#define portMPU_MAIR_ATTR7_MASK               ( 0xff000000 )\n\n#define portMPU_RLAR_ATTR_INDEX0              ( 0UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX1              ( 1UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX2              ( 2UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX3              ( 3UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX4              ( 4UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX5              ( 5UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX6              ( 6UL << 1UL )\n#define portMPU_RLAR_ATTR_INDEX7              ( 7UL << 1UL )\n\n#define portMPU_RLAR_REGION_ENABLE            ( 1UL )\n\n/* Enable privileged access to unmapped region. */\n#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )\n\n/* Enable MPU. */\n#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )\n\n/* Expected value of the portMPU_TYPE register. */\n#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief The maximum 24-bit number.\n *\n * It is needed because the systick is a 24-bit counter.\n */\n#define portMAX_24_BIT_NUMBER       ( 0xffffffUL )\n\n/**\n * @brief A fiddle factor to estimate the number of SysTick counts that would\n * have occurred while the SysTick counter is stopped during tickless idle\n * calculations.\n */\n#define portMISSED_COUNTS_FACTOR    ( 94UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Constants required to set up the initial stack.\n */\n#define portINITIAL_XPSR    ( 0x01000000 )\n\n#if ( configRUN_FREERTOS_SECURE_ONLY == 1 )\n\n/**\n * @brief Initial EXC_RETURN value.\n *\n *     FF         FF         FF         FD\n * 1111 1111  1111 1111  1111 1111  1111 1101\n *\n * Bit[6] - 1 --> The exception was taken from the Secure state.\n * Bit[5] - 1 --> Do not skip stacking of additional state context.\n * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\n * Bit[3] - 1 --> Return to the Thread mode.\n * Bit[2] - 1 --> Restore registers from the process stack.\n * Bit[1] - 0 --> Reserved, 0.\n * Bit[0] - 1 --> The exception was taken to the Secure state.\n */\n    #define portINITIAL_EXC_RETURN    ( 0xfffffffd )\n#else\n\n/**\n * @brief Initial EXC_RETURN value.\n *\n *     FF         FF         FF         BC\n * 1111 1111  1111 1111  1111 1111  1011 1100\n *\n * Bit[6] - 0 --> The exception was taken from the Non-Secure state.\n * Bit[5] - 1 --> Do not skip stacking of additional state context.\n * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\n * Bit[3] - 1 --> Return to the Thread mode.\n * Bit[2] - 1 --> Restore registers from the process stack.\n * Bit[1] - 0 --> Reserved, 0.\n * Bit[0] - 0 --> The exception was taken to the Non-Secure state.\n */\n    #define portINITIAL_EXC_RETURN    ( 0xffffffbc )\n#endif /* configRUN_FREERTOS_SECURE_ONLY */\n\n/**\n * @brief CONTROL register privileged bit mask.\n *\n * Bit[0] in CONTROL register tells the privilege:\n *  Bit[0] = 0 ==> The task is privileged.\n *  Bit[0] = 1 ==> The task is not privileged.\n */\n#define portCONTROL_PRIVILEGED_MASK         ( 1UL << 0UL )\n\n/**\n * @brief Initial CONTROL register values.\n */\n#define portINITIAL_CONTROL_UNPRIVILEGED    ( 0x3 )\n#define portINITIAL_CONTROL_PRIVILEGED      ( 0x2 )\n\n/**\n * @brief Let the user override the default SysTick clock rate.  If defined by the\n * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the\n * configuration register.\n */\n#ifndef configSYSTICK_CLOCK_HZ\n    #define configSYSTICK_CLOCK_HZ             ( configCPU_CLOCK_HZ )\n    /* Ensure the SysTick is clocked at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( portNVIC_SYSTICK_CLK_BIT )\n#else\n    /* Select the option to clock SysTick not at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( 0 )\n#endif\n\n/**\n * @brief Let the user override the pre-loading of the initial LR with the\n * address of prvTaskExitError() in case it messes up unwinding of the stack\n * in the debugger.\n */\n#ifdef configTASK_RETURN_ADDRESS\n    #define portTASK_RETURN_ADDRESS    configTASK_RETURN_ADDRESS\n#else\n    #define portTASK_RETURN_ADDRESS    prvTaskExitError\n#endif\n\n/**\n * @brief If portPRELOAD_REGISTERS then registers will be given an initial value\n * when a task is created. This helps in debugging at the cost of code size.\n */\n#define portPRELOAD_REGISTERS    1\n\n/**\n * @brief A task is created without a secure context, and must call\n * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes\n * any secure calls.\n */\n#define portNO_SECURE_CONTEXT    0\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Used to catch tasks that attempt to return from their implementing\n * function.\n */\nstatic void prvTaskExitError( void );\n\n#if ( configENABLE_MPU == 1 )\n\n/**\n * @brief Setup the Memory Protection Unit (MPU).\n */\n    static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\n#endif /* configENABLE_MPU */\n\n#if ( configENABLE_FPU == 1 )\n\n/**\n * @brief Setup the Floating Point Unit (FPU).\n */\n    static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;\n#endif /* configENABLE_FPU */\n\n/**\n * @brief Setup the timer to generate the tick interrupts.\n *\n * The implementation in this file is weak to allow application writers to\n * change the timer used to generate the tick interrupt.\n */\nvoid vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Checks whether the current execution context is interrupt.\n *\n * @return pdTRUE if the current execution context is interrupt, pdFALSE\n * otherwise.\n */\nBaseType_t xPortIsInsideInterrupt( void );\n\n/**\n * @brief Yield the processor.\n */\nvoid vPortYield( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Enter critical section.\n */\nvoid vPortEnterCritical( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Exit from critical section.\n */\nvoid vPortExitCritical( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief SysTick handler.\n */\nvoid SysTick_Handler( void ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief C part of SVC handler.\n */\nportDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION;\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Each task maintains its own interrupt status in the critical nesting\n * variable.\n */\nPRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;\n\n#if ( configENABLE_TRUSTZONE == 1 )\n\n/**\n * @brief Saved as part of the task context to indicate which context the\n * task is using on the secure side.\n */\n    PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;\n#endif /* configENABLE_TRUSTZONE */\n\n#if ( configUSE_TICKLESS_IDLE == 1 )\n\n/**\n * @brief The number of SysTick increments that make up one tick period.\n */\n    PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0;\n\n/**\n * @brief The maximum number of tick periods that can be suppressed is\n * limited by the 24 bit resolution of the SysTick timer.\n */\n    PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0;\n\n/**\n * @brief Compensate for the CPU cycles that pass while the SysTick is\n * stopped (low power functionality only).\n */\n    PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TICKLESS_IDLE == 1 )\n    __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )\n    {\n        uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;\n        TickType_t xModifiableIdleTime;\n\n        /* Make sure the SysTick reload value does not overflow the counter. */\n        if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\n        {\n            xExpectedIdleTime = xMaximumPossibleSuppressedTicks;\n        }\n\n        /* Enter a critical section but don't use the taskENTER_CRITICAL()\n         * method as that will mask interrupts that should exit sleep mode. */\n        __asm volatile ( \"cpsid i\" ::: \"memory\" );\n        __asm volatile ( \"dsb\" );\n        __asm volatile ( \"isb\" );\n\n        /* If a context switch is pending or a task is waiting for the scheduler\n         * to be unsuspended then abandon the low power entry. */\n        if( eTaskConfirmSleepModeStatus() == eAbortSleep )\n        {\n            /* Re-enable interrupts - see comments above the cpsid instruction\n             * above. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n        }\n        else\n        {\n            /* Stop the SysTick momentarily.  The time the SysTick is stopped for\n             * is accounted for as best it can be, but using the tickless mode will\n             * inevitably result in some tiny drift of the time maintained by the\n             * kernel with respect to calendar time. */\n            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );\n\n            /* Use the SysTick current-value register to determine the number of\n             * SysTick decrements remaining until the next tick interrupt.  If the\n             * current-value register is zero, then there are actually\n             * ulTimerCountsForOneTick decrements remaining, not zero, because the\n             * SysTick requests the interrupt when decrementing from 1 to 0. */\n            ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n\n            if( ulSysTickDecrementsLeft == 0 )\n            {\n                ulSysTickDecrementsLeft = ulTimerCountsForOneTick;\n            }\n\n            /* Calculate the reload value required to wait xExpectedIdleTime\n             * tick periods.  -1 is used because this code normally executes part\n             * way through the first tick period.  But if the SysTick IRQ is now\n             * pending, then clear the IRQ, suppressing the first tick, and correct\n             * the reload value to reflect that the second tick period is already\n             * underway.  The expected idle time is always at least two ticks. */\n            ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );\n\n            if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )\n            {\n                portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;\n                ulReloadValue -= ulTimerCountsForOneTick;\n            }\n\n            if( ulReloadValue > ulStoppedTimerCompensation )\n            {\n                ulReloadValue -= ulStoppedTimerCompensation;\n            }\n\n            /* Set the new reload value. */\n            portNVIC_SYSTICK_LOAD_REG = ulReloadValue;\n\n            /* Clear the SysTick count flag and set the count value back to\n             * zero. */\n            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n            /* Restart SysTick. */\n            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\n\n            /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can\n             * set its parameter to 0 to indicate that its implementation contains\n             * its own wait for interrupt or wait for event instruction, and so wfi\n             * should not be executed again.  However, the original expected idle\n             * time variable must remain unmodified, so a copy is taken. */\n            xModifiableIdleTime = xExpectedIdleTime;\n            configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\n\n            if( xModifiableIdleTime > 0 )\n            {\n                __asm volatile ( \"dsb\" ::: \"memory\" );\n                __asm volatile ( \"wfi\" );\n                __asm volatile ( \"isb\" );\n            }\n\n            configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\n\n            /* Re-enable interrupts to allow the interrupt that brought the MCU\n             * out of sleep mode to execute immediately.  See comments above\n             * the cpsid instruction above. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n            __asm volatile ( \"dsb\" );\n            __asm volatile ( \"isb\" );\n\n            /* Disable interrupts again because the clock is about to be stopped\n             * and interrupts that execute while the clock is stopped will increase\n             * any slippage between the time maintained by the RTOS and calendar\n             * time. */\n            __asm volatile ( \"cpsid i\" ::: \"memory\" );\n            __asm volatile ( \"dsb\" );\n            __asm volatile ( \"isb\" );\n\n            /* Disable the SysTick clock without reading the\n             * portNVIC_SYSTICK_CTRL_REG register to ensure the\n             * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,\n             * the time the SysTick is stopped for is accounted for as best it can\n             * be, but using the tickless mode will inevitably result in some tiny\n             * drift of the time maintained by the kernel with respect to calendar\n             * time*/\n            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );\n\n            /* Determine whether the SysTick has already counted to zero. */\n            if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n            {\n                uint32_t ulCalculatedLoadValue;\n\n                /* The tick interrupt ended the sleep (or is now pending), and\n                 * a new tick period has started.  Reset portNVIC_SYSTICK_LOAD_REG\n                 * with whatever remains of the new tick period. */\n                ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\n\n                /* Don't allow a tiny value, or values that have somehow\n                 * underflowed because the post sleep hook did something\n                 * that took too long or because the SysTick current-value register\n                 * is zero. */\n                if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )\n                {\n                    ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );\n                }\n\n                portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;\n\n                /* As the pending tick will be processed as soon as this\n                 * function exits, the tick value maintained by the tick is stepped\n                 * forward by one less than the time spent waiting. */\n                ulCompleteTickPeriods = xExpectedIdleTime - 1UL;\n            }\n            else\n            {\n                /* Something other than the tick interrupt ended the sleep. */\n\n                /* Use the SysTick current-value register to determine the\n                 * number of SysTick decrements remaining until the expected idle\n                 * time would have ended. */\n                ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n                #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )\n                {\n                    /* If the SysTick is not using the core clock, the current-\n                     * value register might still be zero here.  In that case, the\n                     * SysTick didn't load from the reload register, and there are\n                     * ulReloadValue decrements remaining in the expected idle\n                     * time, not zero. */\n                    if( ulSysTickDecrementsLeft == 0 )\n                    {\n                        ulSysTickDecrementsLeft = ulReloadValue;\n                    }\n                }\n                #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */\n\n                /* Work out how long the sleep lasted rounded to complete tick\n                 * periods (not the ulReload value which accounted for part\n                 * ticks). */\n                ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;\n\n                /* How many complete tick periods passed while the processor\n                 * was waiting? */\n                ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;\n\n                /* The reload value is set to whatever fraction of a single tick\n                 * period remains. */\n                portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;\n            }\n\n            /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,\n             * then set portNVIC_SYSTICK_LOAD_REG back to its standard value.  If\n             * the SysTick is not using the core clock, temporarily configure it to\n             * use the core clock.  This configuration forces the SysTick to load\n             * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next\n             * cycle of the other clock.  Then portNVIC_SYSTICK_LOAD_REG is ready\n             * to receive the standard value immediately. */\n            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n            portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n            #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )\n            {\n                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n            }\n            #else\n            {\n                /* The temporary usage of the core clock has served its purpose,\n                 * as described above.  Resume usage of the other clock. */\n                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\n\n                if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n                {\n                    /* The partial tick period already ended.  Be sure the SysTick\n                     * counts it only once. */\n                    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;\n                }\n\n                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n            }\n            #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */\n\n            /* Step the tick to account for any tick periods that elapsed. */\n            vTaskStepTick( ulCompleteTickPeriods );\n\n            /* Exit with interrupts enabled. */\n            __asm volatile ( \"cpsie i\" ::: \"memory\" );\n        }\n    }\n#endif /* configUSE_TICKLESS_IDLE */\n/*-----------------------------------------------------------*/\n\n__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Calculate the constants required to configure the tick interrupt. */\n    #if ( configUSE_TICKLESS_IDLE == 1 )\n    {\n        ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );\n        xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;\n        ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\n    }\n    #endif /* configUSE_TICKLESS_IDLE */\n\n    /* Stop and reset the SysTick. */\n    portNVIC_SYSTICK_CTRL_REG = 0UL;\n    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n    /* Configure SysTick to interrupt at the requested rate. */\n    portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\n    portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvTaskExitError( void )\n{\n    volatile uint32_t ulDummy = 0UL;\n\n    /* A function that implements a task must not exit or attempt to return to\n     * its caller as there is nothing to return to. If a task wants to exit it\n     * should instead call vTaskDelete( NULL ). Artificially force an assert()\n     * to be triggered if configASSERT() is defined, then stop here so\n     * application writers can catch the error. */\n    configASSERT( ulCriticalNesting == ~0UL );\n    portDISABLE_INTERRUPTS();\n\n    while( ulDummy == 0 )\n    {\n        /* This file calls prvTaskExitError() after the scheduler has been\n         * started to remove a compiler warning about the function being\n         * defined but never called.  ulDummy is used purely to quieten other\n         * warnings about code appearing after this function is called - making\n         * ulDummy volatile makes the compiler think the function could return\n         * and therefore not output an 'unreachable code' warning for code that\n         * appears after it. */\n    }\n}\n/*-----------------------------------------------------------*/\n\n#if ( configENABLE_MPU == 1 )\n    static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */\n    {\n        #if defined( __ARMCC_VERSION )\n\n            /* Declaration when these variable are defined in code instead of being\n             * exported from linker scripts. */\n            extern uint32_t * __privileged_functions_start__;\n            extern uint32_t * __privileged_functions_end__;\n            extern uint32_t * __syscalls_flash_start__;\n            extern uint32_t * __syscalls_flash_end__;\n            extern uint32_t * __unprivileged_flash_start__;\n            extern uint32_t * __unprivileged_flash_end__;\n            extern uint32_t * __privileged_sram_start__;\n            extern uint32_t * __privileged_sram_end__;\n        #else /* if defined( __ARMCC_VERSION ) */\n            /* Declaration when these variable are exported from linker scripts. */\n            extern uint32_t __privileged_functions_start__[];\n            extern uint32_t __privileged_functions_end__[];\n            extern uint32_t __syscalls_flash_start__[];\n            extern uint32_t __syscalls_flash_end__[];\n            extern uint32_t __unprivileged_flash_start__[];\n            extern uint32_t __unprivileged_flash_end__[];\n            extern uint32_t __privileged_sram_start__[];\n            extern uint32_t __privileged_sram_end__[];\n        #endif /* defined( __ARMCC_VERSION ) */\n\n        /* The only permitted number of regions are 8 or 16. */\n        configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );\n\n        /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */\n        configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );\n\n        /* Check that the MPU is present. */\n        if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )\n        {\n            /* MAIR0 - Index 0. */\n            portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\n            /* MAIR0 - Index 1. */\n            portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\n\n            /* Setup privileged flash as Read Only so that privileged tasks can\n             * read it but not modify. */\n            portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_PRIVILEGED_READ_ONLY );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Setup unprivileged flash as Read Only by both privileged and\n             * unprivileged tasks. All tasks can read it but no-one can modify. */\n            portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_READ_ONLY );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Setup unprivileged syscalls flash as Read Only by both privileged\n             * and unprivileged tasks. All tasks can read it but no-one can modify. */\n            portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_READ_ONLY );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Setup RAM containing kernel data for privileged access only. */\n            portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;\n            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\n                               ( portMPU_REGION_NON_SHAREABLE ) |\n                               ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\n                               ( portMPU_REGION_EXECUTE_NEVER );\n            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\n                               ( portMPU_RLAR_ATTR_INDEX0 ) |\n                               ( portMPU_RLAR_REGION_ENABLE );\n\n            /* Enable mem fault. */\n            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;\n\n            /* Enable MPU with privileged background access i.e. unmapped\n             * regions have privileged access. */\n            portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );\n        }\n    }\n#endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\n#if ( configENABLE_FPU == 1 )\n    static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */\n    {\n        #if ( configENABLE_TRUSTZONE == 1 )\n        {\n            /* Enable non-secure access to the FPU. */\n            SecureInit_EnableNSFPUAccess();\n        }\n        #endif /* configENABLE_TRUSTZONE */\n\n        /* CP10 = 11 ==> Full access to FPU i.e. both privileged and\n         * unprivileged code should be able to access FPU. CP11 should be\n         * programmed to the same value as CP10. */\n        *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |\n                            ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )\n                            );\n\n        /* ASPEN = 1 ==> Hardware should automatically preserve floating point\n         * context on exception entry and restore on exception return.\n         * LSPEN = 1 ==> Enable lazy context save of FP state. */\n        *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );\n    }\n#endif /* configENABLE_FPU */\n/*-----------------------------------------------------------*/\n\nvoid vPortYield( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Set a PendSV to request a context switch. */\n    portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\n\n    /* Barriers are normally not required but do ensure the code is\n     * completely within the specified behaviour for the architecture. */\n    __asm volatile ( \"dsb\" ::: \"memory\" );\n    __asm volatile ( \"isb\" );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */\n{\n    portDISABLE_INTERRUPTS();\n    ulCriticalNesting++;\n\n    /* Barriers are normally not required but do ensure the code is\n     * completely within the specified behaviour for the architecture. */\n    __asm volatile ( \"dsb\" ::: \"memory\" );\n    __asm volatile ( \"isb\" );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */\n{\n    configASSERT( ulCriticalNesting );\n    ulCriticalNesting--;\n\n    if( ulCriticalNesting == 0 )\n    {\n        portENABLE_INTERRUPTS();\n    }\n}\n/*-----------------------------------------------------------*/\n\nvoid SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */\n{\n    uint32_t ulPreviousMask;\n\n    ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();\n    {\n        /* Increment the RTOS tick. */\n        if( xTaskIncrementTick() != pdFALSE )\n        {\n            /* Pend a context switch. */\n            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\n        }\n    }\n    portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */\n{\n    #if ( configENABLE_MPU == 1 )\n        #if defined( __ARMCC_VERSION )\n\n            /* Declaration when these variable are defined in code instead of being\n             * exported from linker scripts. */\n            extern uint32_t * __syscalls_flash_start__;\n            extern uint32_t * __syscalls_flash_end__;\n        #else\n            /* Declaration when these variable are exported from linker scripts. */\n            extern uint32_t __syscalls_flash_start__[];\n            extern uint32_t __syscalls_flash_end__[];\n        #endif /* defined( __ARMCC_VERSION ) */\n    #endif /* configENABLE_MPU */\n\n    uint32_t ulPC;\n\n    #if ( configENABLE_TRUSTZONE == 1 )\n        uint32_t ulR0, ulR1;\n        extern TaskHandle_t pxCurrentTCB;\n        #if ( configENABLE_MPU == 1 )\n            uint32_t ulControl, ulIsTaskPrivileged;\n        #endif /* configENABLE_MPU */\n    #endif /* configENABLE_TRUSTZONE */\n    uint8_t ucSVCNumber;\n\n    /* Register are stored on the stack in the following order - R0, R1, R2, R3,\n     * R12, LR, PC, xPSR. */\n    ulPC = pulCallerStackAddress[ 6 ];\n    ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];\n\n    switch( ucSVCNumber )\n    {\n        #if ( configENABLE_TRUSTZONE == 1 )\n            case portSVC_ALLOCATE_SECURE_CONTEXT:\n\n                /* R0 contains the stack size passed as parameter to the\n                 * vPortAllocateSecureContext function. */\n                ulR0 = pulCallerStackAddress[ 0 ];\n\n                #if ( configENABLE_MPU == 1 )\n                {\n                    /* Read the CONTROL register value. */\n                    __asm volatile ( \"mrs %0, control\"  : \"=r\" ( ulControl ) );\n\n                    /* The task that raised the SVC is privileged if Bit[0]\n                     * in the CONTROL register is 0. */\n                    ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );\n\n                    /* Allocate and load a context for the secure task. */\n                    xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );\n                }\n                #else /* if ( configENABLE_MPU == 1 ) */\n                {\n                    /* Allocate and load a context for the secure task. */\n                    xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );\n                }\n                #endif /* configENABLE_MPU */\n\n                configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );\n                SecureContext_LoadContext( xSecureContext, pxCurrentTCB );\n                break;\n\n            case portSVC_FREE_SECURE_CONTEXT:\n\n                /* R0 contains TCB being freed and R1 contains the secure\n                 * context handle to be freed. */\n                ulR0 = pulCallerStackAddress[ 0 ];\n                ulR1 = pulCallerStackAddress[ 1 ];\n\n                /* Free the secure context. */\n                SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );\n                break;\n        #endif /* configENABLE_TRUSTZONE */\n\n        case portSVC_START_SCHEDULER:\n            #if ( configENABLE_TRUSTZONE == 1 )\n            {\n                /* De-prioritize the non-secure exceptions so that the\n                 * non-secure pendSV runs at the lowest priority. */\n                SecureInit_DePrioritizeNSExceptions();\n\n                /* Initialize the secure context management system. */\n                SecureContext_Init();\n            }\n            #endif /* configENABLE_TRUSTZONE */\n\n            #if ( configENABLE_FPU == 1 )\n            {\n                /* Setup the Floating Point Unit (FPU). */\n                prvSetupFPU();\n            }\n            #endif /* configENABLE_FPU */\n\n            /* Setup the context of the first task so that the first task starts\n             * executing. */\n            vRestoreContextOfFirstTask();\n            break;\n\n            #if ( configENABLE_MPU == 1 )\n                case portSVC_RAISE_PRIVILEGE:\n\n                    /* Only raise the privilege, if the svc was raised from any of\n                     * the system calls. */\n                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&\n                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )\n                    {\n                        vRaisePrivilege();\n                    }\n                    break;\n            #endif /* configENABLE_MPU */\n\n        default:\n            /* Incorrect SVC call. */\n            configASSERT( pdFALSE );\n    }\n}\n/*-----------------------------------------------------------*/\n/* *INDENT-OFF* */\n#if ( configENABLE_MPU == 1 )\n    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,\n                                         StackType_t * pxEndOfStack,\n                                         TaskFunction_t pxCode,\n                                         void * pvParameters,\n                                         BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */\n#else\n    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,\n                                         StackType_t * pxEndOfStack,\n                                         TaskFunction_t pxCode,\n                                         void * pvParameters ) /* PRIVILEGED_FUNCTION */\n#endif /* configENABLE_MPU */\n/* *INDENT-ON* */\n{\n    /* Simulate the stack frame as it would be created by a context switch\n     * interrupt. */\n    #if ( portPRELOAD_REGISTERS == 0 )\n    {\n        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\n        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\n        pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */\n        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */\n        pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */\n        *pxTopOfStack = portINITIAL_EXC_RETURN;\n\n        #if ( configENABLE_MPU == 1 )\n        {\n            pxTopOfStack--;\n\n            if( xRunPrivileged == pdTRUE )\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n            else\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n        }\n        #endif /* configENABLE_MPU */\n\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\n\n        #if ( configENABLE_TRUSTZONE == 1 )\n        {\n            pxTopOfStack--;\n            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\n        }\n        #endif /* configENABLE_TRUSTZONE */\n    }\n    #else /* portPRELOAD_REGISTERS */\n    {\n        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\n        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05 */\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04 */\n        pxTopOfStack--;\n        *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN */\n\n        #if ( configENABLE_MPU == 1 )\n        {\n            pxTopOfStack--;\n\n            if( xRunPrivileged == pdTRUE )\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n            else\n            {\n                *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\n            }\n        }\n        #endif /* configENABLE_MPU */\n\n        pxTopOfStack--;\n        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\n\n        #if ( configENABLE_TRUSTZONE == 1 )\n        {\n            pxTopOfStack--;\n            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\n        }\n        #endif /* configENABLE_TRUSTZONE */\n    }\n    #endif /* portPRELOAD_REGISTERS */\n\n    return pxTopOfStack;\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Make PendSV, CallSV and SysTick the same priority as the kernel. */\n    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;\n    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;\n\n    #if ( configENABLE_MPU == 1 )\n    {\n        /* Setup the Memory Protection Unit (MPU). */\n        prvSetupMPU();\n    }\n    #endif /* configENABLE_MPU */\n\n    /* Start the timer that generates the tick ISR. Interrupts are disabled\n     * here already. */\n    vPortSetupTimerInterrupt();\n\n    /* Initialize the critical nesting count ready for the first task. */\n    ulCriticalNesting = 0;\n\n    /* Start the first task. */\n    vStartFirstTask();\n\n    /* Should never get here as the tasks will now be executing. Call the task\n     * exit error function to prevent compiler warnings about a static function\n     * not being called in the case that the application writer overrides this\n     * functionality by defining configTASK_RETURN_ADDRESS. Call\n     * vTaskSwitchContext() so link time optimization does not remove the\n     * symbol. */\n    vTaskSwitchContext();\n    prvTaskExitError();\n\n    /* Should not get here. */\n    return 0;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */\n{\n    /* Not implemented in ports where there is nothing to return to.\n     * Artificially force an assert. */\n    configASSERT( ulCriticalNesting == 1000UL );\n}\n/*-----------------------------------------------------------*/\n\n#if ( configENABLE_MPU == 1 )\n    void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,\n                                    const struct xMEMORY_REGION * const xRegions,\n                                    StackType_t * pxBottomOfStack,\n                                    uint32_t ulStackDepth )\n    {\n        uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;\n        int32_t lIndex = 0;\n\n        #if defined( __ARMCC_VERSION )\n\n            /* Declaration when these variable are defined in code instead of being\n             * exported from linker scripts. */\n            extern uint32_t * __privileged_sram_start__;\n            extern uint32_t * __privileged_sram_end__;\n        #else\n            /* Declaration when these variable are exported from linker scripts. */\n            extern uint32_t __privileged_sram_start__[];\n            extern uint32_t __privileged_sram_end__[];\n        #endif /* defined( __ARMCC_VERSION ) */\n\n        /* Setup MAIR0. */\n        xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\n        xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\n\n        /* This function is called automatically when the task is created - in\n         * which case the stack region parameters will be valid.  At all other\n         * times the stack parameters will not be valid and it is assumed that\n         * the stack region has already been configured. */\n        if( ulStackDepth > 0 )\n        {\n            ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;\n            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;\n\n            /* If the stack is within the privileged SRAM, do not protect it\n             * using a separate MPU region. This is needed because privileged\n             * SRAM is already protected using an MPU region and ARMv8-M does\n             * not allow overlapping MPU regions. */\n            if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) &&\n                ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) )\n            {\n                xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0;\n                xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0;\n            }\n            else\n            {\n                /* Define the region that allows access to the stack. */\n                ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK;\n                ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\n\n                xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |\n                                                             ( portMPU_REGION_NON_SHAREABLE ) |\n                                                             ( portMPU_REGION_READ_WRITE ) |\n                                                             ( portMPU_REGION_EXECUTE_NEVER );\n\n                xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) |\n                                                             ( portMPU_RLAR_ATTR_INDEX0 ) |\n                                                             ( portMPU_RLAR_REGION_ENABLE );\n            }\n        }\n\n        /* User supplied configurable regions. */\n        for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )\n        {\n            /* If xRegions is NULL i.e. the task has not specified any MPU\n             * region, the else part ensures that all the configurable MPU\n             * regions are invalidated. */\n            if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )\n            {\n                /* Translate the generic region definition contained in xRegions\n                 * into the ARMv8 specific MPU settings that are then stored in\n                 * xMPUSettings. */\n                ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;\n                ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;\n                ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\n\n                /* Start address. */\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |\n                                                                          ( portMPU_REGION_NON_SHAREABLE );\n\n                /* RO/RW. */\n                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )\n                {\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );\n                }\n                else\n                {\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );\n                }\n\n                /* XN. */\n                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )\n                {\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );\n                }\n\n                /* End Address. */\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |\n                                                                          ( portMPU_RLAR_REGION_ENABLE );\n\n                /* Normal memory/ Device memory. */\n                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )\n                {\n                    /* Attr1 in MAIR0 is configured as device memory. */\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;\n                }\n                else\n                {\n                    /* Attr0 in MAIR0 is configured as normal memory. */\n                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;\n                }\n            }\n            else\n            {\n                /* Invalidate the region. */\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;\n                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;\n            }\n\n            lIndex++;\n        }\n    }\n#endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\nBaseType_t xPortIsInsideInterrupt( void )\n{\n    uint32_t ulCurrentInterrupt;\n    BaseType_t xReturn;\n\n    /* Obtain the number of the currently executing interrupt. Interrupt Program\n     * Status Register (IPSR) holds the exception number of the currently-executing\n     * exception or zero for Thread mode.*/\n    __asm volatile ( \"mrs %0, ipsr\" : \"=r\" ( ulCurrentInterrupt )::\"memory\" );\n\n    if( ulCurrentInterrupt == 0 )\n    {\n        xReturn = pdFALSE;\n    }\n    else\n    {\n        xReturn = pdTRUE;\n    }\n\n    return xReturn;\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef __PORT_ASM_H__\n#define __PORT_ASM_H__\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n\n/* MPU wrappers includes. */\n#include \"mpu_wrappers.h\"\n\n/**\n * @brief Restore the context of the first task so that the first task starts\n * executing.\n */\nvoid vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Checks whether or not the processor is privileged.\n *\n * @return 1 if the processor is already privileged, 0 otherwise.\n */\nBaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );\n\n/**\n * @brief Raises the privilege level by clearing the bit 0 of the CONTROL\n * register.\n *\n * @note This is a privileged function and should only be called from the kenrel\n * code.\n *\n * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.\n *  Bit[0] = 0 --> The processor is running privileged\n *  Bit[0] = 1 --> The processor is running unprivileged.\n */\nvoid vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\n * register.\n *\n * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.\n *  Bit[0] = 0 --> The processor is running privileged\n *  Bit[0] = 1 --> The processor is running unprivileged.\n */\nvoid vResetPrivilege( void ) __attribute__( ( naked ) );\n\n/**\n * @brief Starts the first task.\n */\nvoid vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Disables interrupts.\n */\nuint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Enables interrupts.\n */\nvoid vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief PendSV Exception handler.\n */\nvoid PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief SVC Handler.\n */\nvoid SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n/**\n * @brief Allocate a Secure context for the calling task.\n *\n * @param[in] ulSecureStackSize The size of the stack to be allocated on the\n * secure side for the calling task.\n */\nvoid vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) );\n\n/**\n * @brief Free the task's secure context.\n *\n * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.\n */\nvoid vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;\n\n#endif /* __PORT_ASM_H__ */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.s",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n/* Including FreeRTOSConfig.h here will cause build errors if the header file\ncontains code not understood by the assembler - for example the 'extern' keyword.\nTo avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so\nthe code is included in C files but excluded by the preprocessor in assembly\nfiles (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */\n#include \"FreeRTOSConfig.h\"\n\n\tEXTERN pxCurrentTCB\n\tEXTERN vTaskSwitchContext\n\tEXTERN vPortSVCHandler_C\n\n\tPUBLIC xIsPrivileged\n\tPUBLIC vResetPrivilege\n\tPUBLIC vRestoreContextOfFirstTask\n\tPUBLIC vRaisePrivilege\n\tPUBLIC vStartFirstTask\n\tPUBLIC ulSetInterruptMask\n\tPUBLIC vClearInterruptMask\n\tPUBLIC PendSV_Handler\n\tPUBLIC SVC_Handler\n/*-----------------------------------------------------------*/\n\n/*---------------- Unprivileged Functions -------------------*/\n\n/*-----------------------------------------------------------*/\n\n\tSECTION .text:CODE:NOROOT(2)\n\tTHUMB\n/*-----------------------------------------------------------*/\n\nxIsPrivileged:\n\tmrs r0, control\t\t\t\t\t\t\t/* r0 = CONTROL. */\n\ttst r0, #1\t\t\t\t\t\t\t\t/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\n\tite ne\n\tmovne r0, #0\t\t\t\t\t\t\t/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\n\tmoveq r0, #1\t\t\t\t\t\t\t/* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */\n\tbx lr\t\t\t\t\t\t\t\t\t/* Return. */\n/*-----------------------------------------------------------*/\n\nvResetPrivilege:\n\tmrs r0, control\t\t\t\t\t\t\t/* r0 = CONTROL. */\n\torr r0, r0, #1\t\t\t\t\t\t\t/* r0 = r0 | 1. */\n\tmsr control, r0\t\t\t\t\t\t\t/* CONTROL = r0. */\n\tbx lr\t\t\t\t\t\t\t\t\t/* Return to the caller. */\n/*-----------------------------------------------------------*/\n\n/*----------------- Privileged Functions --------------------*/\n\n/*-----------------------------------------------------------*/\n\n\tSECTION privileged_functions:CODE:NOROOT(2)\n\tTHUMB\n/*-----------------------------------------------------------*/\n\nvRestoreContextOfFirstTask:\n\tldr  r2, =pxCurrentTCB\t\t\t\t\t/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n\tldr  r1, [r2]\t\t\t\t\t\t\t/* Read pxCurrentTCB. */\n\tldr  r0, [r1]\t\t\t\t\t\t\t/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\n\n#if ( configENABLE_MPU == 1 )\n\tdmb\t\t\t\t\t\t\t\t\t\t/* Complete outstanding transfers before disabling MPU. */\n\tldr r2, =0xe000ed94\t\t\t\t\t\t/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n\tldr r4, [r2]\t\t\t\t\t\t\t/* Read the value of MPU_CTRL. */\n\tbic r4, r4, #1\t\t\t\t\t\t\t/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\n\tstr r4, [r2]\t\t\t\t\t\t\t/* Disable MPU. */\n\n\tadds r1, #4\t\t\t\t\t\t\t\t/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\n\tldr r3, [r1]\t\t\t\t\t\t\t/* r3 = *r1 i.e. r3 = MAIR0. */\n\tldr r2, =0xe000edc0\t\t\t\t\t\t/* r2 = 0xe000edc0 [Location of MAIR0]. */\n\tstr r3, [r2]\t\t\t\t\t\t\t/* Program MAIR0. */\n\tldr r2, =0xe000ed98\t\t\t\t\t\t/* r2 = 0xe000ed98 [Location of RNR]. */\n\tmovs r3, #4\t\t\t\t\t\t\t\t/* r3 = 4. */\n\tstr r3, [r2]\t\t\t\t\t\t\t/* Program RNR = 4. */\n\tadds r1, #4\t\t\t\t\t\t\t\t/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\n\tldr r2, =0xe000ed9c\t\t\t\t\t\t/* r2 = 0xe000ed9c [Location of RBAR]. */\n\tldmia r1!, {r4-r11}\t\t\t\t\t\t/* Read 4 sets of RBAR/RLAR registers from TCB. */\n\tstmia r2!, {r4-r11}\t\t\t\t\t\t/* Write 4 set of RBAR/RLAR registers using alias registers. */\n\n\tldr r2, =0xe000ed94\t\t\t\t\t\t/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n\tldr r4, [r2]\t\t\t\t\t\t\t/* Read the value of MPU_CTRL. */\n\torr r4, r4, #1\t\t\t\t\t\t\t/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\n\tstr r4, [r2]\t\t\t\t\t\t\t/* Enable MPU. */\n\tdsb\t\t\t\t\t\t\t\t\t\t/* Force memory writes before continuing. */\n#endif /* configENABLE_MPU */\n\n#if ( configENABLE_MPU == 1 )\n\tldm  r0!, {r1-r3}\t\t\t\t\t\t/* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */\n\tmsr  psplim, r1\t\t\t\t\t\t\t/* Set this task's PSPLIM value. */\n\tmsr  control, r2\t\t\t\t\t\t/* Set this task's CONTROL value. */\n\tadds r0, #32\t\t\t\t\t\t\t/* Discard everything up to r0. */\n\tmsr  psp, r0\t\t\t\t\t\t\t/* This is now the new top of stack to use in the task. */\n\tisb\n\tmov  r0, #0\n\tmsr  basepri, r0\t\t\t\t\t\t/* Ensure that interrupts are enabled when the first task starts. */\n\tbx   r3\t\t\t\t\t\t\t\t\t/* Finally, branch to EXC_RETURN. */\n#else /* configENABLE_MPU */\n\tldm  r0!, {r1-r2}\t\t\t\t\t\t/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */\n\tmsr  psplim, r1\t\t\t\t\t\t\t/* Set this task's PSPLIM value. */\n\tmovs r1, #2\t\t\t\t\t\t\t\t/* r1 = 2. */\n\tmsr  CONTROL, r1\t\t\t\t\t\t/* Switch to use PSP in the thread mode. */\n\tadds r0, #32\t\t\t\t\t\t\t/* Discard everything up to r0. */\n\tmsr  psp, r0\t\t\t\t\t\t\t/* This is now the new top of stack to use in the task. */\n\tisb\n\tmov  r0, #0\n\tmsr  basepri, r0\t\t\t\t\t\t/* Ensure that interrupts are enabled when the first task starts. */\n\tbx   r2\t\t\t\t\t\t\t\t\t/* Finally, branch to EXC_RETURN. */\n#endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\nvRaisePrivilege:\n\tmrs  r0, control\t\t\t\t\t\t/* Read the CONTROL register. */\n\tbic r0, r0, #1\t\t\t\t\t\t\t/* Clear the bit 0. */\n\tmsr  control, r0\t\t\t\t\t\t/* Write back the new CONTROL value. */\n\tbx lr\t\t\t\t\t\t\t\t\t/* Return to the caller. */\n/*-----------------------------------------------------------*/\n\nvStartFirstTask:\n\tldr r0, =0xe000ed08\t\t\t\t\t\t/* Use the NVIC offset register to locate the stack. */\n\tldr r0, [r0]\t\t\t\t\t\t\t/* Read the VTOR register which gives the address of vector table. */\n\tldr r0, [r0]\t\t\t\t\t\t\t/* The first entry in vector table is stack pointer. */\n\tmsr msp, r0\t\t\t\t\t\t\t\t/* Set the MSP back to the start of the stack. */\n\tcpsie i\t\t\t\t\t\t\t\t\t/* Globally enable interrupts. */\n\tcpsie f\n\tdsb\n\tisb\n\tsvc 2\t\t\t\t\t\t\t\t\t/* System call to start the first task. portSVC_START_SCHEDULER = 2. */\n/*-----------------------------------------------------------*/\n\nulSetInterruptMask:\n\tmrs r0, basepri\t\t\t\t\t\t\t/* r0 = basepri. Return original basepri value. */\n\tmov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY\n\tmsr basepri, r1\t\t\t\t\t\t\t/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */\n\tdsb\n\tisb\n\tbx lr\t\t\t\t\t\t\t\t\t/* Return. */\n/*-----------------------------------------------------------*/\n\nvClearInterruptMask:\n\tmsr basepri, r0\t\t\t\t\t\t\t/* basepri = ulMask. */\n\tdsb\n\tisb\n\tbx lr\t\t\t\t\t\t\t\t\t/* Return. */\n/*-----------------------------------------------------------*/\n\nPendSV_Handler:\n\tmrs r0, psp\t\t\t\t\t\t\t\t/* Read PSP in r0. */\n#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )\n\ttst lr, #0x10\t\t\t\t\t\t\t/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */\n\tit eq\n\tvstmdbeq r0!, {s16-s31}\t\t\t\t\t/* Store the additional FP context registers which are not saved automatically. */\n#endif /* configENABLE_FPU || configENABLE_MVE */\n#if ( configENABLE_MPU == 1 )\n\tmrs r1, psplim\t\t\t\t\t\t\t/* r1 = PSPLIM. */\n\tmrs r2, control\t\t\t\t\t\t\t/* r2 = CONTROL. */\n\tmov r3, lr\t\t\t\t\t\t\t\t/* r3 = LR/EXC_RETURN. */\n\tstmdb r0!, {r1-r11}\t\t\t\t\t\t/* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */\n#else /* configENABLE_MPU */\n\tmrs r2, psplim\t\t\t\t\t\t\t/* r2 = PSPLIM. */\n\tmov r3, lr\t\t\t\t\t\t\t\t/* r3 = LR/EXC_RETURN. */\n\tstmdb r0!, {r2-r11}\t\t\t\t\t\t/* Store on the stack - PSPLIM, LR and registers that are not automatically. */\n#endif /* configENABLE_MPU */\n\n\tldr r2, =pxCurrentTCB\t\t\t\t\t/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n\tldr r1, [r2]\t\t\t\t\t\t\t/* Read pxCurrentTCB. */\n\tstr r0, [r1]\t\t\t\t\t\t\t/* Save the new top of stack in TCB. */\n\n\tmov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY\n\tmsr basepri, r0\t\t\t\t\t\t\t/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */\n\tdsb\n\tisb\n\tbl vTaskSwitchContext\n\tmov r0, #0\t\t\t\t\t\t\t\t/* r0 = 0. */\n\tmsr basepri, r0\t\t\t\t\t\t\t/* Enable interrupts. */\n\n\tldr r2, =pxCurrentTCB\t\t\t\t\t/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\n\tldr r1, [r2]\t\t\t\t\t\t\t/* Read pxCurrentTCB. */\n\tldr r0, [r1]\t\t\t\t\t\t\t/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */\n\n#if ( configENABLE_MPU == 1 )\n\tdmb\t\t\t\t\t\t\t\t\t\t/* Complete outstanding transfers before disabling MPU. */\n\tldr r2, =0xe000ed94\t\t\t\t\t\t/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n\tldr r4, [r2]\t\t\t\t\t\t\t/* Read the value of MPU_CTRL. */\n\tbic r4, r4, #1\t\t\t\t\t\t\t/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\n\tstr r4, [r2]\t\t\t\t\t\t\t/* Disable MPU. */\n\n\tadds r1, #4\t\t\t\t\t\t\t\t/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\n\tldr r3, [r1]\t\t\t\t\t\t\t/* r3 = *r1 i.e. r3 = MAIR0. */\n\tldr r2, =0xe000edc0\t\t\t\t\t\t/* r2 = 0xe000edc0 [Location of MAIR0]. */\n\tstr r3, [r2]\t\t\t\t\t\t\t/* Program MAIR0. */\n\tldr r2, =0xe000ed98\t\t\t\t\t\t/* r2 = 0xe000ed98 [Location of RNR]. */\n\tmovs r3, #4\t\t\t\t\t\t\t\t/* r3 = 4. */\n\tstr r3, [r2]\t\t\t\t\t\t\t/* Program RNR = 4. */\n\tadds r1, #4\t\t\t\t\t\t\t\t/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\n\tldr r2, =0xe000ed9c\t\t\t\t\t\t/* r2 = 0xe000ed9c [Location of RBAR]. */\n\tldmia r1!, {r4-r11}\t\t\t\t\t\t/* Read 4 sets of RBAR/RLAR registers from TCB. */\n\tstmia r2!, {r4-r11}\t\t\t\t\t\t/* Write 4 set of RBAR/RLAR registers using alias registers. */\n\n\tldr r2, =0xe000ed94\t\t\t\t\t\t/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\n\tldr r4, [r2]\t\t\t\t\t\t\t/* Read the value of MPU_CTRL. */\n\torr r4, r4, #1\t\t\t\t\t\t\t/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\n\tstr r4, [r2]\t\t\t\t\t\t\t/* Enable MPU. */\n\tdsb\t\t\t\t\t\t\t\t\t\t/* Force memory writes before continuing. */\n#endif /* configENABLE_MPU */\n\n#if ( configENABLE_MPU == 1 )\n\tldmia r0!, {r1-r11}\t\t\t\t\t\t/* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */\n#else /* configENABLE_MPU */\n\tldmia r0!, {r2-r11}\t\t\t\t\t\t/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */\n#endif /* configENABLE_MPU */\n\n#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )\n\ttst r3, #0x10\t\t\t\t\t\t\t/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */\n\tit eq\n\tvldmiaeq r0!, {s16-s31}\t\t\t\t\t/* Restore the additional FP context registers which are not restored automatically. */\n#endif /* configENABLE_FPU || configENABLE_MVE */\n\n #if ( configENABLE_MPU == 1 )\n\tmsr psplim, r1\t\t\t\t\t\t\t/* Restore the PSPLIM register value for the task. */\n\tmsr control, r2\t\t\t\t\t\t\t/* Restore the CONTROL register value for the task. */\n#else /* configENABLE_MPU */\n\tmsr psplim, r2\t\t\t\t\t\t\t/* Restore the PSPLIM register value for the task. */\n#endif /* configENABLE_MPU */\n\tmsr psp, r0\t\t\t\t\t\t\t\t/* Remember the new top of stack for the task. */\n\tbx r3\n/*-----------------------------------------------------------*/\n\nSVC_Handler:\n\ttst lr, #4\n\tite eq\n\tmrseq r0, msp\n\tmrsne r0, psp\n\tb vPortSVCHandler_C\n/*-----------------------------------------------------------*/\n\n\tEND\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM85_NTZ/non_secure/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef PORTMACRO_H\n#define PORTMACRO_H\n\n#ifdef __cplusplus\n    extern \"C\" {\n#endif\n\n#include \"portmacrocommon.h\"\n\n/*------------------------------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the given hardware\n * and compiler.\n *\n * These settings should not be altered.\n *------------------------------------------------------------------------------\n */\n\n#ifndef configENABLE_MVE\n    #error configENABLE_MVE must be defined in FreeRTOSConfig.h. Set configENABLE_MVE to 1 to enable the MVE or 0 to disable the MVE.\n#endif /* configENABLE_MVE */\n/*-----------------------------------------------------------*/\n\n/**\n * Architecture specifics.\n */\n#define portARCH_NAME                       \"Cortex-M85\"\n#define portDONT_DISCARD                    __root\n/*-----------------------------------------------------------*/\n\n#if( configTOTAL_MPU_REGIONS == 16 )\n    #error 16 MPU regions are not yet supported for this port.\n#endif\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Critical section management.\n */\n#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()\n#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )\n/*-----------------------------------------------------------*/\n\n/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in\n * the source code because to do so would cause other compilers to generate\n * warnings. */\n#pragma diag_suppress=Be006\n#pragma diag_suppress=Pa082\n/*-----------------------------------------------------------*/\n\n#ifdef __cplusplus\n    }\n#endif\n\n#endif /* PORTMACRO_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef PORTMACROCOMMON_H\n    #define PORTMACROCOMMON_H\n\n    #ifdef __cplusplus\n        extern \"C\" {\n    #endif\n\n/*------------------------------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the given hardware\n * and compiler.\n *\n * These settings should not be altered.\n *------------------------------------------------------------------------------\n */\n\n    #ifndef configENABLE_FPU\n        #error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.\n    #endif /* configENABLE_FPU */\n\n    #ifndef configENABLE_MPU\n        #error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.\n    #endif /* configENABLE_MPU */\n\n    #ifndef configENABLE_TRUSTZONE\n        #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.\n    #endif /* configENABLE_TRUSTZONE */\n\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Type definitions.\n */\n    #define portCHAR          char\n    #define portFLOAT         float\n    #define portDOUBLE        double\n    #define portLONG          long\n    #define portSHORT         short\n    #define portSTACK_TYPE    uint32_t\n    #define portBASE_TYPE     long\n\n    typedef portSTACK_TYPE   StackType_t;\n    typedef long             BaseType_t;\n    typedef unsigned long    UBaseType_t;\n\n    #if ( configUSE_16_BIT_TICKS == 1 )\n        typedef uint16_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffff\n    #else\n        typedef uint32_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL\n\n/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\n * not need to be guarded with a critical section. */\n        #define portTICK_TYPE_IS_ATOMIC    1\n    #endif\n/*-----------------------------------------------------------*/\n\n/**\n * Architecture specifics.\n */\n    #define portSTACK_GROWTH                   ( -1 )\n    #define portTICK_PERIOD_MS                 ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\n    #define portBYTE_ALIGNMENT                 8\n    #define portNOP()\n    #define portINLINE                         __inline\n    #ifndef portFORCE_INLINE\n        #define portFORCE_INLINE               inline __attribute__( ( always_inline ) )\n    #endif\n    #define portHAS_STACK_OVERFLOW_CHECKING    1\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Extern declarations.\n */\n    extern BaseType_t xPortIsInsideInterrupt( void );\n\n    extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;\n\n    extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;\n    extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;\n\n    extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\n    extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\n\n    #if ( configENABLE_TRUSTZONE == 1 )\n        extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */\n        extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;\n    #endif /* configENABLE_TRUSTZONE */\n\n    #if ( configENABLE_MPU == 1 )\n        extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;\n        extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;\n    #endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\n/**\n * @brief MPU specific constants.\n */\n    #if ( configENABLE_MPU == 1 )\n        #define portUSING_MPU_WRAPPERS    1\n        #define portPRIVILEGE_BIT         ( 0x80000000UL )\n    #else\n        #define portPRIVILEGE_BIT         ( 0x0UL )\n    #endif /* configENABLE_MPU */\n\n/* MPU settings that can be overriden in FreeRTOSConfig.h. */\n#ifndef configTOTAL_MPU_REGIONS\n    /* Define to 8 for backward compatibility. */\n    #define configTOTAL_MPU_REGIONS       ( 8UL )\n#endif\n\n/* MPU regions. */\n    #define portPRIVILEGED_FLASH_REGION                   ( 0UL )\n    #define portUNPRIVILEGED_FLASH_REGION                 ( 1UL )\n    #define portUNPRIVILEGED_SYSCALLS_REGION              ( 2UL )\n    #define portPRIVILEGED_RAM_REGION                     ( 3UL )\n    #define portSTACK_REGION                              ( 4UL )\n    #define portFIRST_CONFIGURABLE_REGION                 ( 5UL )\n    #define portLAST_CONFIGURABLE_REGION                  ( configTOTAL_MPU_REGIONS - 1UL )\n    #define portNUM_CONFIGURABLE_REGIONS                  ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )\n    #define portTOTAL_NUM_REGIONS                         ( portNUM_CONFIGURABLE_REGIONS + 1 )   /* Plus one to make space for the stack region. */\n\n/* Device memory attributes used in MPU_MAIR registers.\n *\n * 8-bit values encoded as follows:\n *  Bit[7:4] - 0000 - Device Memory\n *  Bit[3:2] - 00 --> Device-nGnRnE\n *\t\t\t\t01 --> Device-nGnRE\n *\t\t\t\t10 --> Device-nGRE\n *\t\t\t\t11 --> Device-GRE\n *  Bit[1:0] - 00, Reserved.\n */\n    #define portMPU_DEVICE_MEMORY_nGnRnE                  ( 0x00 )   /* 0000 0000 */\n    #define portMPU_DEVICE_MEMORY_nGnRE                   ( 0x04 )   /* 0000 0100 */\n    #define portMPU_DEVICE_MEMORY_nGRE                    ( 0x08 )   /* 0000 1000 */\n    #define portMPU_DEVICE_MEMORY_GRE                     ( 0x0C )   /* 0000 1100 */\n\n/* Normal memory attributes used in MPU_MAIR registers. */\n    #define portMPU_NORMAL_MEMORY_NON_CACHEABLE           ( 0x44 )   /* Non-cacheable. */\n    #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE    ( 0xFF )   /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */\n\n/* Attributes used in MPU_RBAR registers. */\n    #define portMPU_REGION_NON_SHAREABLE                  ( 0UL << 3UL )\n    #define portMPU_REGION_INNER_SHAREABLE                ( 1UL << 3UL )\n    #define portMPU_REGION_OUTER_SHAREABLE                ( 2UL << 3UL )\n\n    #define portMPU_REGION_PRIVILEGED_READ_WRITE          ( 0UL << 1UL )\n    #define portMPU_REGION_READ_WRITE                     ( 1UL << 1UL )\n    #define portMPU_REGION_PRIVILEGED_READ_ONLY           ( 2UL << 1UL )\n    #define portMPU_REGION_READ_ONLY                      ( 3UL << 1UL )\n\n    #define portMPU_REGION_EXECUTE_NEVER                  ( 1UL )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Settings to define an MPU region.\n */\n    typedef struct MPURegionSettings\n    {\n        uint32_t ulRBAR; /**< RBAR for the region. */\n        uint32_t ulRLAR; /**< RLAR for the region. */\n    } MPURegionSettings_t;\n\n/**\n * @brief MPU settings as stored in the TCB.\n */\n    typedef struct MPU_SETTINGS\n    {\n        uint32_t ulMAIR0;                                              /**< MAIR0 for the task containing attributes for all the 4 per task regions. */\n        MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */\n    } xMPU_SETTINGS;\n/*-----------------------------------------------------------*/\n\n/**\n * @brief SVC numbers.\n */\n    #define portSVC_ALLOCATE_SECURE_CONTEXT    0\n    #define portSVC_FREE_SECURE_CONTEXT        1\n    #define portSVC_START_SCHEDULER            2\n    #define portSVC_RAISE_PRIVILEGE            3\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Scheduler utilities.\n */\n    #define portYIELD()                                 vPortYield()\n    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )\n    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )\n    #define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )\n    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Critical section management.\n */\n    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulSetInterruptMask()\n    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vClearInterruptMask( x )\n    #define portENTER_CRITICAL()                      vPortEnterCritical()\n    #define portEXIT_CRITICAL()                       vPortExitCritical()\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Tickless idle/low power functionality.\n */\n    #ifndef portSUPPRESS_TICKS_AND_SLEEP\n        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );\n        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )\n    #endif\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Task function macros as described on the FreeRTOS.org WEB site.\n */\n    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )\n    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )\n/*-----------------------------------------------------------*/\n\n    #if ( configENABLE_TRUSTZONE == 1 )\n\n/**\n * @brief Allocate a secure context for the task.\n *\n * Tasks are not created with a secure context. Any task that is going to call\n * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a\n * secure context before it calls any secure function.\n *\n * @param[in] ulSecureStackSize The size of the secure stack to be allocated.\n */\n        #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )\n\n/**\n * @brief Called when a task is deleted to delete the task's secure context,\n * if it has one.\n *\n * @param[in] pxTCB The TCB of the task being deleted.\n */\n        #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )\n    #endif /* configENABLE_TRUSTZONE */\n/*-----------------------------------------------------------*/\n\n    #if ( configENABLE_MPU == 1 )\n\n/**\n * @brief Checks whether or not the processor is privileged.\n *\n * @return 1 if the processor is already privileged, 0 otherwise.\n */\n        #define portIS_PRIVILEGED()      xIsPrivileged()\n\n/**\n * @brief Raise an SVC request to raise privilege.\n *\n * The SVC handler checks that the SVC was raised from a system call and only\n * then it raises the privilege. If this is called from any other place,\n * the privilege is not raised.\n */\n        #define portRAISE_PRIVILEGE()    __asm volatile ( \"svc %0 \\n\" ::\"i\" ( portSVC_RAISE_PRIVILEGE ) : \"memory\" );\n\n/**\n * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\n * register.\n */\n        #define portRESET_PRIVILEGE()    vResetPrivilege()\n    #else\n        #define portIS_PRIVILEGED()\n        #define portRAISE_PRIVILEGE()\n        #define portRESET_PRIVILEGE()\n    #endif /* configENABLE_MPU */\n/*-----------------------------------------------------------*/\n\n/**\n * @brief Barriers.\n */\n    #define portMEMORY_BARRIER()    __asm volatile ( \"\" ::: \"memory\" )\n/*-----------------------------------------------------------*/\n\n    #ifdef __cplusplus\n        }\n    #endif\n\n#endif /* PORTMACROCOMMON_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CRx_No_GIC/port.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Standard includes. */\n#include <stdlib.h>\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1\n\t/* Check the configuration. */\n\t#if( configMAX_PRIORITIES > 32 )\n\t\t#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.\n\t#endif\n#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */\n\n#ifndef configSETUP_TICK_INTERRUPT\n\t#error configSETUP_TICK_INTERRUPT() must be defined in FreeRTOSConfig.h to call the function that sets up the tick interrupt.\n#endif\n\n#ifndef configCLEAR_TICK_INTERRUPT\n\t#error configCLEAR_TICK_INTERRUPT must be defined in FreeRTOSConfig.h to clear which ever interrupt was used to generate the tick interrupt.\n#endif\n\n/* A critical section is exited when the critical section nesting count reaches\nthis value. */\n#define portNO_CRITICAL_NESTING\t\t\t( ( uint32_t ) 0 )\n\n/* Tasks are not created with a floating point context, but can be given a\nfloating point context after they have been created.  A variable is stored as\npart of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task\ndoes not have an FPU context, or any other value if the task does have an FPU\ncontext. */\n#define portNO_FLOATING_POINT_CONTEXT\t( ( StackType_t ) 0 )\n\n/* Constants required to setup the initial task context. */\n#define portINITIAL_SPSR\t\t\t\t( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */\n#define portTHUMB_MODE_BIT\t\t\t\t( ( StackType_t ) 0x20 )\n#define portTHUMB_MODE_ADDRESS\t\t\t( 0x01UL )\n\n/* Masks all bits in the APSR other than the mode bits. */\n#define portAPSR_MODE_BITS_MASK\t\t\t( 0x1F )\n\n/* The value of the mode bits in the APSR when the CPU is executing in user\nmode. */\n#define portAPSR_USER_MODE\t\t\t\t( 0x10 )\n\n/* Let the user override the pre-loading of the initial LR with the address of\nprvTaskExitError() in case it messes up unwinding of the stack in the\ndebugger. */\n#ifdef configTASK_RETURN_ADDRESS\n\t#define portTASK_RETURN_ADDRESS\tconfigTASK_RETURN_ADDRESS\n#else\n\t#define portTASK_RETURN_ADDRESS\tprvTaskExitError\n#endif\n\n/*-----------------------------------------------------------*/\n\n/*\n * Starts the first task executing.  This function is necessarily written in\n * assembly code so is implemented in portASM.s.\n */\nextern void vPortRestoreTaskContext( void );\n\n/*\n * Used to catch tasks that attempt to return from their implementing function.\n */\nstatic void prvTaskExitError( void );\n\n/*-----------------------------------------------------------*/\n\n/* A variable is used to keep track of the critical section nesting.  This\nvariable has to be stored as part of the task context and must be initialised to\na non zero value to ensure interrupts don't inadvertently become unmasked before\nthe scheduler starts.  As it is stored as part of the task context it will\nautomatically be set to 0 when the first task is started. */\nvolatile uint32_t ulCriticalNesting = 9999UL;\n\n/* Saved as part of the task context.  If ulPortTaskHasFPUContext is non-zero then\na floating point context must be saved and restored for the task. */\nvolatile uint32_t ulPortTaskHasFPUContext = pdFALSE;\n\n/* Set to 1 to pend a context switch from an ISR. */\nvolatile uint32_t ulPortYieldRequired = pdFALSE;\n\n/* Counts the interrupt nesting depth.  A context switch is only performed if\nif the nesting depth is 0. */\nvolatile uint32_t ulPortInterruptNesting = 0UL;\n\n/*-----------------------------------------------------------*/\n\n/*\n * See header file for description.\n */\nStackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )\n{\n\t/* Setup the initial stack of the task.  The stack is set exactly as\n\texpected by the portRESTORE_CONTEXT() macro.\n\n\tThe fist real value on the stack is the status register, which is set for\n\tsystem mode, with interrupts enabled.  A few NULLs are added first to ensure\n\tGDB does not try decoding a non-existent return address. */\n\t*pxTopOfStack = ( StackType_t ) NULL;\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) NULL;\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) NULL;\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;\n\n\tif( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )\n\t{\n\t\t/* The task will start in THUMB mode. */\n\t\t*pxTopOfStack |= portTHUMB_MODE_BIT;\n\t}\n\n\tpxTopOfStack--;\n\n\t/* Next the return address, which in this case is the start of the task. */\n\t*pxTopOfStack = ( StackType_t ) pxCode;\n\tpxTopOfStack--;\n\n\t/* Next all the registers other than the stack pointer. */\n\t*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;\t/* R14 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x12121212;\t/* R12 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x11111111;\t/* R11 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x10101010;\t/* R10 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x09090909;\t/* R9 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x08080808;\t/* R8 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x07070707;\t/* R7 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x06060606;\t/* R6 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x05050505;\t/* R5 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x04040404;\t/* R4 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x03030303;\t/* R3 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x02020202;\t/* R2 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x01010101;\t/* R1 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\n\tpxTopOfStack--;\n\n\t/* The task will start with a critical nesting count of 0 as interrupts are\n\tenabled. */\n\t*pxTopOfStack = portNO_CRITICAL_NESTING;\n\tpxTopOfStack--;\n\n\t/* The task will start without a floating point context.  A task that uses\n\tthe floating point hardware must call vPortTaskUsesFPU() before executing\n\tany floating point instructions. */\n\t*pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;\n\n\treturn pxTopOfStack;\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvTaskExitError( void )\n{\n\t/* A function that implements a task must not exit or attempt to return to\n\tits caller as there is nothing to return to.  If a task wants to exit it\n\tshould instead call vTaskDelete( NULL ).\n\n\tArtificially force an assert() to be triggered if configASSERT() is\n\tdefined, then stop here so application writers can catch the error. */\n\tconfigASSERT( ulPortInterruptNesting == ~0UL );\n\tportDISABLE_INTERRUPTS();\n\tfor( ;; );\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xPortStartScheduler( void )\n{\nuint32_t ulAPSR;\n\n\t/* Only continue if the CPU is not in User mode.  The CPU must be in a\n\tPrivileged mode for the scheduler to start. */\n\t__asm volatile ( \"MRS %0, APSR\" : \"=r\" ( ulAPSR ) );\n\tulAPSR &= portAPSR_MODE_BITS_MASK;\n\tconfigASSERT( ulAPSR != portAPSR_USER_MODE );\n\n\tif( ulAPSR != portAPSR_USER_MODE )\n\t{\n\t\t/* Start the timer that generates the tick ISR. */\n\t\tportDISABLE_INTERRUPTS();\n\t\tconfigSETUP_TICK_INTERRUPT();\n\n\t\t/* Start the first task executing. */\n\t\tvPortRestoreTaskContext();\n\t}\n\n\t/* Will only get here if vTaskStartScheduler() was called with the CPU in\n\ta non-privileged mode or the binary point register was not set to its lowest\n\tpossible value.  prvTaskExitError() is referenced to prevent a compiler\n\twarning about it being defined but not referenced in the case that the user\n\tdefines their own exit address. */\n\t( void ) prvTaskExitError;\n\treturn 0;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEndScheduler( void )\n{\n\t/* Not implemented in ports where there is nothing to return to.\n\tArtificially force an assert. */\n\tconfigASSERT( ulCriticalNesting == 1000UL );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEnterCritical( void )\n{\n\tportDISABLE_INTERRUPTS();\n\n\t/* Now interrupts are disabled ulCriticalNesting can be accessed\n\tdirectly.  Increment ulCriticalNesting to keep a count of how many times\n\tportENTER_CRITICAL() has been called. */\n\tulCriticalNesting++;\n\n\t/* This is not the interrupt safe version of the enter critical function so\n\tassert() if it is being called from an interrupt context.  Only API\n\tfunctions that end in \"FromISR\" can be used in an interrupt.  Only assert if\n\tthe critical nesting count is 1 to protect against recursive calls if the\n\tassert function also uses a critical section. */\n\tif( ulCriticalNesting == 1 )\n\t{\n\t\tconfigASSERT( ulPortInterruptNesting == 0 );\n\t}\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortExitCritical( void )\n{\n\tif( ulCriticalNesting > portNO_CRITICAL_NESTING )\n\t{\n\t\t/* Decrement the nesting count as the critical section is being\n\t\texited. */\n\t\tulCriticalNesting--;\n\n\t\t/* If the nesting level has reached zero then all interrupt\n\t\tpriorities must be re-enabled. */\n\t\tif( ulCriticalNesting == portNO_CRITICAL_NESTING )\n\t\t{\n\t\t\t/* Critical nesting has reached zero so all interrupt priorities\n\t\t\tshould be unmasked. */\n\t\t\tportENABLE_INTERRUPTS();\n\t\t}\n\t}\n}\n/*-----------------------------------------------------------*/\n\nvoid FreeRTOS_Tick_Handler( void )\n{\nuint32_t ulInterruptStatus;\n\n\tulInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();\n\n\t/* Increment the RTOS tick. */\n\tif( xTaskIncrementTick() != pdFALSE )\n\t{\n\t\tulPortYieldRequired = pdTRUE;\n\t}\n\n\tportCLEAR_INTERRUPT_MASK_FROM_ISR( ulInterruptStatus );\n\n\tconfigCLEAR_TICK_INTERRUPT();\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortTaskUsesFPU( void )\n{\nuint32_t ulInitialFPSCR = 0;\n\n\t/* A task is registering the fact that it needs an FPU context.  Set the\n\tFPU flag (which is saved as part of the task context). */\n\tulPortTaskHasFPUContext = pdTRUE;\n\n\t/* Initialise the floating point status register. */\n\t__asm volatile ( \"FMXR \tFPSCR, %0\" :: \"r\" (ulInitialFPSCR) );\n}\n/*-----------------------------------------------------------*/\n\n\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CRx_No_GIC/portASM.s",
    "content": ";/*\n; * FreeRTOS Kernel V10.5.1\n; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n; *\n; * SPDX-License-Identifier: MIT\n; *\n; * Permission is hereby granted, free of charge, to any person obtaining a copy of\n; * this software and associated documentation files (the \"Software\"), to deal in\n; * the Software without restriction, including without limitation the rights to\n; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n; * the Software, and to permit persons to whom the Software is furnished to do so,\n; * subject to the following conditions:\n; *\n; * The above copyright notice and this permission notice shall be included in all\n; * copies or substantial portions of the Software.\n; *\n; * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n; *\n; * https://www.FreeRTOS.org\n; * https://github.com/FreeRTOS\n; *\n; */\n\n#include \"FreeRTOSConfig.h\"\n\n\tSECTION .text:CODE:ROOT(2)\n\tarm\n\n\t/* Variables and functions. */\n\tEXTERN pxCurrentTCB\n\tEXTERN vTaskSwitchContext\n\tEXTERN vApplicationIRQHandler\n\tEXTERN ulPortInterruptNesting\n\tEXTERN ulPortTaskHasFPUContext\n\tEXTERN ulPortYieldRequired\n\tEXTERN ulCriticalNesting\n\n\tPUBLIC FreeRTOS_IRQ_Handler\n\tPUBLIC FreeRTOS_SVC_Handler\n\tPUBLIC vPortRestoreTaskContext\n\nSYS_MODE\t\t\tEQU\t\t0x1f\nSVC_MODE\t\t\tEQU\t\t0x13\nIRQ_MODE\t\t\tEQU\t\t0x12\n\nportSAVE_CONTEXT MACRO\n\n\t/* Save the LR and SPSR onto the system mode stack before switching to\n\tsystem mode to save the remaining system mode registers. */\n\tSRSDB\tsp!, #SYS_MODE\n\tCPS\t\t#SYS_MODE\n\tPUSH\t{R0-R12, R14}\n\n\t/* Push the critical nesting count. */\n\tLDR\t\tR2, =ulCriticalNesting\n\tLDR\t\tR1, [R2]\n\tPUSH\t{R1}\n\n\t/* Does the task have a floating point context that needs saving?  If\n\tulPortTaskHasFPUContext is 0 then no. */\n\tLDR\t\tR2, =ulPortTaskHasFPUContext\n\tLDR\t\tR3, [R2]\n\tCMP\t\tR3, #0\n\n\t/* Save the floating point context, if any. */\n\tFMRXNE  R1,  FPSCR\n\tVPUSHNE {D0-D15}\n#if configFPU_D32 == 1\n\tVPUSHNE\t{D16-D31}\n#endif /* configFPU_D32 */\n\tPUSHNE\t{R1}\n\n\t/* Save ulPortTaskHasFPUContext itself. */\n\tPUSH\t{R3}\n\n\t/* Save the stack pointer in the TCB. */\n\tLDR\t\tR0, =pxCurrentTCB\n\tLDR\t\tR1, [R0]\n\tSTR\t\tSP, [R1]\n\n\tENDM\n\n; /**********************************************************************/\n\nportRESTORE_CONTEXT MACRO\n\n\t/* Set the SP to point to the stack of the task being restored. */\n\tLDR\t\tR0, =pxCurrentTCB\n\tLDR\t\tR1, [R0]\n\tLDR\t\tSP, [R1]\n\n\t/* Is there a floating point context to restore?  If the restored\n\tulPortTaskHasFPUContext is zero then no. */\n\tLDR\t\tR0, =ulPortTaskHasFPUContext\n\tPOP\t\t{R1}\n\tSTR\t\tR1, [R0]\n\tCMP\t\tR1, #0\n\n\t/* Restore the floating point context, if any. */\n\tPOPNE \t{R0}\n#if configFPU_D32 == 1\n\tVPOPNE\t{D16-D31}\n#endif /* configFPU_D32 */\n\tVPOPNE\t{D0-D15}\n\tVMSRNE  FPSCR, R0\n\n\t/* Restore the critical section nesting depth. */\n\tLDR\t\tR0, =ulCriticalNesting\n\tPOP\t\t{R1}\n\tSTR\t\tR1, [R0]\n\n\t/* Restore all system mode registers other than the SP (which is already\n\tbeing used). */\n\tPOP\t\t{R0-R12, R14}\n\n\t/* Return to the task code, loading CPSR on the way. */\n\tRFEIA\tsp!\n\n\tENDM\n\n\n\n\n/******************************************************************************\n * SVC handler is used to yield.\n *****************************************************************************/\nFreeRTOS_SVC_Handler:\n\t/* Save the context of the current task and select a new task to run. */\n\tportSAVE_CONTEXT\n\tLDR R0, =vTaskSwitchContext\n\tBLX\tR0\n\tportRESTORE_CONTEXT\n\n\n/******************************************************************************\n * vPortRestoreTaskContext is used to start the scheduler.\n *****************************************************************************/\nvPortRestoreTaskContext:\n\t/* Switch to system mode. */\n\tCPS\t\t#SYS_MODE\n\tportRESTORE_CONTEXT\n\nFreeRTOS_IRQ_Handler:\n\t/* Return to the interrupted instruction. */\n\tSUB\t\tlr, lr, #4\n\n\t/* Push the return address and SPSR. */\n\tPUSH\t{lr}\n\tMRS\t\tlr, SPSR\n\tPUSH\t{lr}\n\n\t/* Change to supervisor mode to allow reentry. */\n\tCPS\t\t#SVC_MODE\n\n\t/* Push used registers. */\n\tPUSH\t{r0-r3, r12}\n\n\t/* Increment nesting count.  r3 holds the address of ulPortInterruptNesting\n\tfor future use.  r1 holds the original ulPortInterruptNesting value for\n\tfuture use. */\n\tLDR\t\tr3, =ulPortInterruptNesting\n\tLDR\t\tr1, [r3]\n\tADD\t\tr0, r1, #1\n\tSTR\t\tr0, [r3]\n\n\t/* Ensure bit 2 of the stack pointer is clear.  r2 holds the bit 2 value for\n\tfuture use. */\n\tMOV\t\tr0, sp\n\tAND\t\tr2, r0, #4\n\tSUB\t\tsp, sp, r2\n\n\t/* Call the interrupt handler. */\n\tPUSH\t{r0-r3, lr}\n\tLDR\t\tr1, =vApplicationIRQHandler\n\tBLX\t\tr1\n\tPOP\t\t{r0-r3, lr}\n\tADD\t\tsp, sp, r2\n\n\tCPSID\ti\n\tDSB\n\tISB\n\n\t/* Write to the EOI register. */\n\tLDR \tr2, =configEOI_ADDRESS\n\tSTR\t\tr0, [r2]\n\n\t/* Restore the old nesting count. */\n\tSTR\t\tr1, [r3]\n\n\t/* A context switch is never performed if the nesting count is not 0. */\n\tCMP\t\tr1, #0\n\tBNE\t\texit_without_switch\n\n\t/* Did the interrupt request a context switch?  r1 holds the address of\n\tulPortYieldRequired and r0 the value of ulPortYieldRequired for future\n\tuse. */\n\tLDR\t\tr1, =ulPortYieldRequired\n\tLDR\t\tr0, [r1]\n\tCMP\t\tr0, #0\n\tBNE\t\tswitch_before_exit\n\nexit_without_switch:\n\t/* No context switch.  Restore used registers, LR_irq and SPSR before\n\treturning. */\n\tPOP\t\t{r0-r3, r12}\n\tCPS\t\t#IRQ_MODE\n\tPOP\t\t{LR}\n\tMSR\t\tSPSR_cxsf, LR\n\tPOP\t\t{LR}\n\tMOVS\tPC, LR\n\nswitch_before_exit:\n\t/* A context swtich is to be performed.  Clear the context switch pending\n\tflag. */\n\tMOV\t\tr0, #0\n\tSTR\t\tr0, [r1]\n\n\t/* Restore used registers, LR-irq and SPSR before saving the context\n\tto the task stack. */\n\tPOP\t\t{r0-r3, r12}\n\tCPS\t\t#IRQ_MODE\n\tPOP\t\t{LR}\n\tMSR\t\tSPSR_cxsf, LR\n\tPOP\t\t{LR}\n\tportSAVE_CONTEXT\n\n\t/* Call the function that selects the new task to execute.\n\tvTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD\n\tinstructions, or 8 byte aligned stack allocated data.  LR does not need\n\tsaving as a new LR will be loaded by portRESTORE_CONTEXT anyway. */\n\tLDR\t\tR0, =vTaskSwitchContext\n\tBLX\t\tR0\n\n\t/* Restore the context of, and branch to, the task selected to execute\n\tnext. */\n\tportRESTORE_CONTEXT\n\n\tEND\n\n\n\n\n\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/ARM_CRx_No_GIC/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef PORTMACRO_H\n#define PORTMACRO_H\n\n#include <intrinsics.h>\n\n#ifdef __cplusplus\n\textern \"C\" {\n#endif\n\n/*-----------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the given hardware\n * and compiler.\n *\n * These settings should not be altered.\n *-----------------------------------------------------------\n */\n\n/* Type definitions. */\n#define portCHAR\t\tchar\n#define portFLOAT\t\tfloat\n#define portDOUBLE\t\tdouble\n#define portLONG\t\tlong\n#define portSHORT\t\tshort\n#define portSTACK_TYPE\tuint32_t\n#define portBASE_TYPE\tlong\n\ntypedef portSTACK_TYPE StackType_t;\ntypedef long BaseType_t;\ntypedef unsigned long UBaseType_t;\n\ntypedef uint32_t TickType_t;\n#define portMAX_DELAY ( TickType_t ) 0xffffffffUL\n\n/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\nnot need to be guarded with a critical section. */\n#define portTICK_TYPE_IS_ATOMIC 1\n\n/*-----------------------------------------------------------*/\n\n/* Hardware specifics. */\n#define portSTACK_GROWTH\t\t\t( -1 )\n#define portTICK_PERIOD_MS\t\t\t( ( TickType_t ) 1000 / configTICK_RATE_HZ )\n#define portBYTE_ALIGNMENT\t\t\t8\n\n/*-----------------------------------------------------------*/\n\n/* Task utilities. */\n\n/* Called at the end of an ISR that can cause a context switch. */\n#define portEND_SWITCHING_ISR( xSwitchRequired )\\\n{\t\t\t\t\t\t\t\t\t\t\t\t\\\nextern volatile uint32_t ulPortYieldRequired;\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tif( xSwitchRequired != pdFALSE )\t\t\t\\\n\t{\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tulPortYieldRequired = pdTRUE;\t\t\t\\\n\t}\t\t\t\t\t\t\t\t\t\t\t\\\n}\n\n#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\n#define portYIELD() __asm volatile ( \"SWI 0\t\t\\n\"\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t \"ISB\t\t  \" );\n\n\n/*-----------------------------------------------------------\n * Critical section control\n *----------------------------------------------------------*/\n\nextern void vPortEnterCritical( void );\nextern void vPortExitCritical( void );\nextern uint32_t ulPortSetInterruptMask( void );\nextern void vPortClearInterruptMask( uint32_t ulNewMaskValue );\nextern void vPortInstallFreeRTOSVectorTable( void );\n\n/* The I bit within the CPSR. */\n#define portINTERRUPT_ENABLE_BIT\t( 1 << 7 )\n\n/* In the absence of a priority mask register, these functions and macros\nglobally enable and disable interrupts. */\n#define portENTER_CRITICAL()\t\tvPortEnterCritical();\n#define portEXIT_CRITICAL()\t\t\tvPortExitCritical();\n#define portENABLE_INTERRUPTS()\t\t__asm volatile ( \"CPSIE i \t\\n\"\t);\n#define portDISABLE_INTERRUPTS()\t__asm volatile ( \"CPSID i \t\\n\"\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\t \"DSB\t\t\\n\"\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\t \"ISB\t\t  \" );\n#pragma inline\nstatic inline uint32_t portINLINE_SET_INTERRUPT_MASK_FROM_ISR( void )\n{\nvolatile uint32_t ulCPSR;\n\n\t__asm volatile ( \"MRS %0, CPSR\" : \"=r\" (ulCPSR) );\n\tulCPSR &= portINTERRUPT_ENABLE_BIT;\n\tportDISABLE_INTERRUPTS();\n\treturn ulCPSR;\n}\n\n#define portSET_INTERRUPT_MASK_FROM_ISR() portINLINE_SET_INTERRUPT_MASK_FROM_ISR()\n#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)\tdo { if( x == 0 ) portENABLE_INTERRUPTS(); } while( 0 )\n\n/*-----------------------------------------------------------*/\n\n/* Task function macros as described on the FreeRTOS.org WEB site.  These are\nnot required for this port but included in case common demo code that uses these\nmacros is used. */\n#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )\tvoid vFunction( void *pvParameters )\n#define portTASK_FUNCTION( vFunction, pvParameters )\tvoid vFunction( void *pvParameters )\n\n/* Prototype of the FreeRTOS tick handler.  This must be installed as the\nhandler for whichever peripheral is used to generate the RTOS tick. */\nvoid FreeRTOS_Tick_Handler( void );\n\n/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()\nbefore any floating point instructions are executed. */\nvoid vPortTaskUsesFPU( void );\n#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()\n\n#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )\n#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )\n\n/* Architecture specific optimisations. */\n#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION\n\t#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1\n#endif\n\n#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1\n\n\t/* Store/clear the ready priorities in a bit map. */\n\t#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )\n\t#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )\n\n\t/*-----------------------------------------------------------*/\n\n\t#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __CLZ( uxReadyPriorities ) )\n\n#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */\n\n#define portNOP() __asm volatile( \"NOP\" )\n#define portINLINE inline\n\n/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in\nthe source code because to do so would cause other compilers to generate\nwarnings. */\n#pragma diag_suppress=Pe191\n#pragma diag_suppress=Pa082\n\n#ifdef __cplusplus\n\t} /* extern C */\n#endif\n\n\n#endif /* PORTMACRO_H */\n\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/LPC2000/ISR_Support.h",
    "content": ";/*\n; * FreeRTOS Kernel V10.5.1\n; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n; *\n; * SPDX-License-Identifier: MIT\n; *\n; * Permission is hereby granted, free of charge, to any person obtaining a copy of\n; * this software and associated documentation files (the \"Software\"), to deal in\n; * the Software without restriction, including without limitation the rights to\n; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n; * the Software, and to permit persons to whom the Software is furnished to do so,\n; * subject to the following conditions:\n; *\n; * The above copyright notice and this permission notice shall be included in all\n; * copies or substantial portions of the Software.\n; *\n; * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n; *\n; * https://www.FreeRTOS.org\n; * https://github.com/FreeRTOS\n; *\n; */\n\n\tEXTERN pxCurrentTCB\n\tEXTERN ulCriticalNesting\n\n;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n; Context save and restore macro definitions\n;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n\nportSAVE_CONTEXT MACRO\n\n\t; Push R0 as we are going to use the register.\n\tSTMDB\tSP!, {R0}\n\n\t; Set R0 to point to the task stack pointer.\n\tSTMDB\tSP, {SP}^\n\tNOP\n\tSUB\t\tSP, SP, #4\n\tLDMIA\tSP!, {R0}\n\n\t; Push the return address onto the stack.\n\tSTMDB\tR0!, {LR}\n\n\t; Now we have saved LR we can use it instead of R0.\n\tMOV\t\tLR, R0\n\n\t; Pop R0 so we can save it onto the system mode stack.\n\tLDMIA\tSP!, {R0}\n\n\t; Push all the system mode registers onto the task stack.\n\tSTMDB\tLR, {R0-LR}^\n\tNOP\n\tSUB\t\tLR, LR, #60\n\n\t; Push the SPSR onto the task stack.\n\tMRS\t\tR0, SPSR\n\tSTMDB\tLR!, {R0}\n\n\tLDR\t\tR0, =ulCriticalNesting\n\tLDR\t\tR0, [R0]\n\tSTMDB\tLR!, {R0}\n\n\t; Store the new top of stack for the task.\n\tLDR\t\tR1, =pxCurrentTCB\n\tLDR\t\tR0, [R1]\n\tSTR\t\tLR, [R0]\n\n\tENDM\n\n\nportRESTORE_CONTEXT MACRO\n\n\t; Set the LR to the task stack.\n\tLDR\t\tR1, =pxCurrentTCB\n\tLDR\t\tR0, [R1]\n\tLDR\t\tLR, [R0]\n\n\t; The critical nesting depth is the first item on the stack.\n\t; Load it into the ulCriticalNesting variable.\n\tLDR\t\tR0, =ulCriticalNesting\n\tLDMFD\tLR!, {R1}\n\tSTR\t\tR1, [R0]\n\n\t; Get the SPSR from the stack.\n\tLDMFD\tLR!, {R0}\n\tMSR\t\tSPSR_cxsf, R0\n\n\t; Restore all system mode registers for the task.\n\tLDMFD\tLR, {R0-R14}^\n\tNOP\n\n\t; Restore the return address.\n\tLDR\t\tLR, [LR, #+60]\n\n\t; And return - correcting the offset in the LR to obtain the\n\t; correct address.\n\tSUBS\tPC, LR, #4\n\n\tENDM\n\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/LPC2000/port.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/*-----------------------------------------------------------\n * Implementation of functions defined in portable.h for the Philips ARM7 port.\n *----------------------------------------------------------*/\n\n/*\n\tChanges from V3.2.2\n\n\t+ Bug fix - The prescale value for the timer setup is now written to T0PR\n\t  instead of T0PC.  This bug would have had no effect unless a prescale\n\t  value was actually used.\n*/\n\n/* Standard includes. */\n#include <stdlib.h>\n#include <intrinsics.h>\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n/* Constants required to setup the tick ISR. */\n#define portENABLE_TIMER\t\t\t( ( uint8_t ) 0x01 )\n#define portPRESCALE_VALUE\t\t\t0x00\n#define portINTERRUPT_ON_MATCH\t\t( ( uint32_t ) 0x01 )\n#define portRESET_COUNT_ON_MATCH\t( ( uint32_t ) 0x02 )\n\n/* Constants required to setup the initial stack. */\n#define portINITIAL_SPSR\t\t\t\t( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */\n#define portTHUMB_MODE_BIT\t\t\t\t( ( StackType_t ) 0x20 )\n#define portINSTRUCTION_SIZE\t\t\t( ( StackType_t ) 4 )\n\n/* Constants required to setup the PIT. */\n#define portPIT_CLOCK_DIVISOR\t\t\t( ( uint32_t ) 16 )\n#define portPIT_COUNTER_VALUE\t\t\t( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) * portTICK_PERIOD_MS )\n\n/* Constants required to handle interrupts. */\n#define portTIMER_MATCH_ISR_BIT\t\t( ( uint8_t ) 0x01 )\n#define portCLEAR_VIC_INTERRUPT\t\t( ( uint32_t ) 0 )\n\n/* Constants required to handle critical sections. */\n#define portNO_CRITICAL_NESTING \t\t( ( uint32_t ) 0 )\n\n\n#define portINT_LEVEL_SENSITIVE  0\n#define portPIT_ENABLE      \t( ( uint16_t ) 0x1 << 24 )\n#define portPIT_INT_ENABLE     \t( ( uint16_t ) 0x1 << 25 )\n\n/* Constants required to setup the VIC for the tick ISR. */\n#define portTIMER_VIC_CHANNEL\t\t( ( uint32_t ) 0x0004 )\n#define portTIMER_VIC_CHANNEL_BIT\t( ( uint32_t ) 0x0010 )\n#define portTIMER_VIC_ENABLE\t\t( ( uint32_t ) 0x0020 )\n\n/*-----------------------------------------------------------*/\n\n/* Setup the PIT to generate the tick interrupts. */\nstatic void prvSetupTimerInterrupt( void );\n\n/* ulCriticalNesting will get set to zero when the first task starts.  It\ncannot be initialised to 0 as this will cause interrupts to be enabled\nduring the kernel initialisation process. */\nuint32_t ulCriticalNesting = ( uint32_t ) 9999;\n\n/*-----------------------------------------------------------*/\n\n/*\n * Initialise the stack of a task to look exactly as if a call to\n * portSAVE_CONTEXT had been called.\n *\n * See header file for description.\n */\nStackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )\n{\nStackType_t *pxOriginalTOS;\n\n\tpxOriginalTOS = pxTopOfStack;\n\n\t/* Setup the initial stack of the task.  The stack is set exactly as\n\texpected by the portRESTORE_CONTEXT() macro. */\n\n\t/* First on the stack is the return address - which in this case is the\n\tstart of the task.  The offset is added to make the return address appear\n\tas it would within an IRQ ISR. */\n\t*pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;\t\t\n\tpxTopOfStack--;\n\n\t*pxTopOfStack = ( StackType_t ) 0xaaaaaaaa;\t/* R14 */\n\tpxTopOfStack--;\t\n\t*pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x12121212;\t/* R12 */\n\tpxTopOfStack--;\t\n\t*pxTopOfStack = ( StackType_t ) 0x11111111;\t/* R11 */\n\tpxTopOfStack--;\t\n\t*pxTopOfStack = ( StackType_t ) 0x10101010;\t/* R10 */\n\tpxTopOfStack--;\t\n\t*pxTopOfStack = ( StackType_t ) 0x09090909;\t/* R9 */\n\tpxTopOfStack--;\t\n\t*pxTopOfStack = ( StackType_t ) 0x08080808;\t/* R8 */\n\tpxTopOfStack--;\t\n\t*pxTopOfStack = ( StackType_t ) 0x07070707;\t/* R7 */\n\tpxTopOfStack--;\t\n\t*pxTopOfStack = ( StackType_t ) 0x06060606;\t/* R6 */\n\tpxTopOfStack--;\t\n\t*pxTopOfStack = ( StackType_t ) 0x05050505;\t/* R5 */\n\tpxTopOfStack--;\t\n\t*pxTopOfStack = ( StackType_t ) 0x04040404;\t/* R4 */\n\tpxTopOfStack--;\t\n\t*pxTopOfStack = ( StackType_t ) 0x03030303;\t/* R3 */\n\tpxTopOfStack--;\t\n\t*pxTopOfStack = ( StackType_t ) 0x02020202;\t/* R2 */\n\tpxTopOfStack--;\t\n\t*pxTopOfStack = ( StackType_t ) 0x01010101;\t/* R1 */\n\tpxTopOfStack--;\t\n\n\t/* When the task starts is will expect to find the function parameter in\n\tR0. */\n\t*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\n\tpxTopOfStack--;\n\n\t/* The status register is set for system mode, with interrupts enabled. */\n\t*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;\n\t\n\tif( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00UL )\n\t{\n\t\t/* We want the task to start in thumb mode. */\n\t\t*pxTopOfStack |= portTHUMB_MODE_BIT;\n\t}\n\t\n\tpxTopOfStack--;\n\n\t/* Interrupt flags cannot always be stored on the stack and will\n\tinstead be stored in a variable, which is then saved as part of the\n\ttasks context. */\n\t*pxTopOfStack = portNO_CRITICAL_NESTING;\n\n\treturn pxTopOfStack;\t\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xPortStartScheduler( void )\n{\nextern void vPortStartFirstTask( void );\n\n\t/* Start the timer that generates the tick ISR.  Interrupts are disabled\n\there already. */\n\tprvSetupTimerInterrupt();\n\n\t/* Start the first task. */\n\tvPortStartFirstTask();\t\n\n\t/* Should not get here! */\n\treturn 0;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEndScheduler( void )\n{\n\t/* It is unlikely that the ARM port will require this function as there\n\tis nothing to return to.  */\n}\n/*-----------------------------------------------------------*/\n\n#if configUSE_PREEMPTION == 0\n\n\t/* The cooperative scheduler requires a normal IRQ service routine to\n\tsimply increment the system tick. */\n\tstatic __arm __irq void vPortNonPreemptiveTick( void );\n\tstatic __arm __irq void vPortNonPreemptiveTick( void )\n\t{\n\t\t/* Increment the tick count - which may wake some tasks but as the\n\t\tpreemptive scheduler is not being used any woken task is not given\n\t\tprocessor time no matter what its priority. */\n\t\txTaskIncrementTick();\n\t\t\n\t\t/* Ready for the next interrupt. */\n\t\tT0IR = portTIMER_MATCH_ISR_BIT;\n\t\tVICVectAddr = portCLEAR_VIC_INTERRUPT;\n\t}\n\n#else\n\n\t/* This function is called from an asm wrapper, so does not require the __irq\n\tkeyword. */\n\tvoid vPortPreemptiveTick( void );\n\tvoid vPortPreemptiveTick( void )\n\t{\n\t\t/* Increment the tick counter. */\n\t\tif( xTaskIncrementTick() != pdFALSE )\n\t\t{\t\n\t\t\t/* The new tick value might unblock a task.  Ensure the highest task that\n\t\t\tis ready to execute is the task that will execute when the tick ISR\n\t\t\texits. */\n\t\t\tvTaskSwitchContext();\n\t\t}\n\t\n\t\t/* Ready for the next interrupt. */\n\t\tT0IR = portTIMER_MATCH_ISR_BIT;\n\t\tVICVectAddr = portCLEAR_VIC_INTERRUPT;\n\t}\n\n#endif\n\n/*-----------------------------------------------------------*/\n\nstatic void prvSetupTimerInterrupt( void )\n{\nuint32_t ulCompareMatch;\n\n\t/* A 1ms tick does not require the use of the timer prescale.  This is\n\tdefaulted to zero but can be used if necessary. */\n\tT0PR = portPRESCALE_VALUE;\n\n\t/* Calculate the match value required for our wanted tick rate. */\n\tulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;\n\n\t/* Protect against divide by zero.  Using an if() statement still results\n\tin a warning - hence the #if. */\n\t#if portPRESCALE_VALUE != 0\n\t{\n\t\tulCompareMatch /= ( portPRESCALE_VALUE + 1 );\n\t}\n\t#endif\n\n\tT0MR0 = ulCompareMatch;\n\n\t/* Generate tick with timer 0 compare match. */\n\tT0MCR = portRESET_COUNT_ON_MATCH | portINTERRUPT_ON_MATCH;\n\n\t/* Setup the VIC for the timer. */\n\tVICIntSelect &= ~( portTIMER_VIC_CHANNEL_BIT );\n\tVICIntEnable |= portTIMER_VIC_CHANNEL_BIT;\n\t\n\t/* The ISR installed depends on whether the preemptive or cooperative\n\tscheduler is being used. */\n\t#if configUSE_PREEMPTION == 1\n\t{\t\n\t\textern void ( vPortPreemptiveTickEntry )( void );\n\n\t\tVICVectAddr0 = ( uint32_t ) vPortPreemptiveTickEntry;\n\t}\n\t#else\n\t{\n\t\textern void ( vNonPreemptiveTick )( void );\n\n\t\tVICVectAddr0 = ( int32_t ) vPortNonPreemptiveTick;\n\t}\n\t#endif\n\n\tVICVectCntl0 = portTIMER_VIC_CHANNEL | portTIMER_VIC_ENABLE;\n\n\t/* Start the timer - interrupts are disabled when this function is called\n\tso it is okay to do this here. */\n\tT0TCR = portENABLE_TIMER;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEnterCritical( void )\n{\n\t/* Disable interrupts first! */\n\t__disable_interrupt();\n\n\t/* Now interrupts are disabled ulCriticalNesting can be accessed\n\tdirectly.  Increment ulCriticalNesting to keep a count of how many times\n\tportENTER_CRITICAL() has been called. */\n\tulCriticalNesting++;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortExitCritical( void )\n{\n\tif( ulCriticalNesting > portNO_CRITICAL_NESTING )\n\t{\n\t\t/* Decrement the nesting count as we are leaving a critical section. */\n\t\tulCriticalNesting--;\n\n\t\t/* If the nesting level has reached zero then interrupts should be\n\t\tre-enabled. */\n\t\tif( ulCriticalNesting == portNO_CRITICAL_NESTING )\n\t\t{\n\t\t\t__enable_interrupt();\n\t\t}\n\t}\n}\n/*-----------------------------------------------------------*/\n\n\n\n\n\n\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/LPC2000/portasm.s79",
    "content": ";/*\n; * FreeRTOS Kernel V10.5.1\n; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n; *\n; * SPDX-License-Identifier: MIT\n; *\n; * Permission is hereby granted, free of charge, to any person obtaining a copy of\n; * this software and associated documentation files (the \"Software\"), to deal in\n; * the Software without restriction, including without limitation the rights to\n; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n; * the Software, and to permit persons to whom the Software is furnished to do so,\n; * subject to the following conditions:\n; *\n; * The above copyright notice and this permission notice shall be included in all\n; * copies or substantial portions of the Software.\n; *\n; * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n; *\n; * https://www.FreeRTOS.org\n; * https://github.com/FreeRTOS\n; *\n; */\n\n\t\tRSEG ICODE:CODE\n\t\tCODE32\n\n\tEXTERN vTaskSwitchContext\n\tEXTERN vPortPreemptiveTick\n\n\tPUBLIC vPortPreemptiveTickEntry\n\tPUBLIC vPortYieldProcessor\n\tPUBLIC vPortStartFirstTask\n\n#include \"FreeRTOSConfig.h\"\n#include \"ISR_Support.h\"\n\n;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n; Starting the first task is just a matter of restoring the context that\n; was created by pxPortInitialiseStack().\n;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\nvPortStartFirstTask:\n\tportRESTORE_CONTEXT\n\n;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n; Manual context switch function.  This is the SWI hander.\n;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\nvPortYieldProcessor:\n\tADD\t\tLR, LR, #4\t\t\t; Add 4 to the LR to make the LR appear exactly\n\t\t\t\t\t\t\t\t; as if the context was saved during and IRQ\n\t\t\t\t\t\t\t\t; handler.\n\n\tportSAVE_CONTEXT\t\t\t; Save the context of the current task...\n\tLDR R0, =vTaskSwitchContext\t; before selecting the next task to execute.\n\tmov     lr, pc\n\tBX R0\n\tportRESTORE_CONTEXT\t\t\t; Restore the context of the selected task.\n\n;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n; Preemptive context switch function.  This will only ever get installed if\n; portUSE_PREEMPTION is set to 1 in portmacro.h.\n;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\nvPortPreemptiveTickEntry:\n#if configUSE_PREEMPTION == 1\n\tportSAVE_CONTEXT\t\t\t; Save the context of the current task...\n\tLDR R0, =vPortPreemptiveTick; before selecting the next task to execute.\n\tmov     lr, pc\n\tBX R0\n\tportRESTORE_CONTEXT\t\t\t; Restore the context of the selected task.\n#endif\n\n\tEND\n\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/LPC2000/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n\n#ifndef PORTMACRO_H\n#define PORTMACRO_H\n\n#include <intrinsics.h>\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/*-----------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the\n * given hardware and compiler.\n *\n * These settings should not be altered.\n *-----------------------------------------------------------\n */\n\n/* Type definitions. */\n#define portCHAR\t\tchar\n#define portFLOAT\t\tfloat\n#define portDOUBLE\t\tdouble\n#define portLONG\t\tlong\n#define portSHORT\t\tshort\n#define portSTACK_TYPE\tuint32_t\n#define portBASE_TYPE\tlong\n\ntypedef portSTACK_TYPE StackType_t;\ntypedef long BaseType_t;\ntypedef unsigned long UBaseType_t;\n\n\n#if( configUSE_16_BIT_TICKS == 1 )\n\ttypedef uint16_t TickType_t;\n\t#define portMAX_DELAY ( TickType_t ) 0xffff\n#else\n\ttypedef uint32_t TickType_t;\n\t#define portMAX_DELAY ( TickType_t ) 0xffffffffUL\n#endif\n/*-----------------------------------------------------------*/\n\n/* Hardware specifics. */\n#define portSTACK_GROWTH\t\t\t( -1 )\n#define portTICK_PERIOD_MS\t\t\t( ( TickType_t ) 1000 / configTICK_RATE_HZ )\n#define portBYTE_ALIGNMENT\t\t\t8\n#define portYIELD()\t\t\t\t\tasm ( \"SWI 0\" )\n#define portNOP()\t\t\t\t\tasm ( \"NOP\" )\n/*-----------------------------------------------------------*/\n\n/* Critical section handling. */\n__arm __interwork void vPortDisableInterruptsFromThumb( void );\n__arm __interwork void vPortEnableInterruptsFromThumb( void );\n__arm __interwork void vPortEnterCritical( void );\n__arm __interwork void vPortExitCritical( void );\n\n#define portDISABLE_INTERRUPTS()\t__disable_interrupt()\n#define portENABLE_INTERRUPTS()\t\t__enable_interrupt()\n#define portENTER_CRITICAL()\t\tvPortEnterCritical()\n#define portEXIT_CRITICAL()\t\t\tvPortExitCritical()\n/*-----------------------------------------------------------*/\n\n/* Task utilities. */\n#define portEND_SWITCHING_ISR( xSwitchRequired ) \t\\\n{\t\t\t\t\t\t\t\t\t\t\t\t\t\\\nextern void vTaskSwitchContext( void );\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tif( xSwitchRequired ) \t\t\t\t\t\t\t\\\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tvTaskSwitchContext();\t\t\t\t\t\t\\\n\t}\t\t\t\t\t\t\t\t\t\t\t\t\\\n}\n/*-----------------------------------------------------------*/\n\n/* Task function macros as described on the FreeRTOS.org WEB site. */\n#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )\n#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* PORTMACRO_H */\n\n\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/MSP430/port.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n/*-----------------------------------------------------------\n * Implementation of functions defined in portable.h for the MSP430 port.\n *----------------------------------------------------------*/\n\n/* Constants required for hardware setup.  The tick ISR runs off the ACLK,\nnot the MCLK. */\n#define portACLK_FREQUENCY_HZ\t\t\t( ( TickType_t ) 32768 )\n#define portINITIAL_CRITICAL_NESTING\t( ( uint16_t ) 10 )\n#define portFLAGS_INT_ENABLED\t\t\t( ( StackType_t ) 0x08 )\n\n/* We require the address of the pxCurrentTCB variable, but don't want to know\nany details of its type. */\ntypedef void TCB_t;\nextern volatile TCB_t * volatile pxCurrentTCB;\n\n/* Each task maintains a count of the critical section nesting depth.  Each\ntime a critical section is entered the count is incremented.  Each time a\ncritical section is exited the count is decremented - with interrupts only\nbeing re-enabled if the count is zero.\n\nusCriticalNesting will get set to zero when the scheduler starts, but must\nnot be initialised to zero as this will cause problems during the startup\nsequence. */\nvolatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;\n/*-----------------------------------------------------------*/\n\n\n/*\n * Sets up the periodic ISR used for the RTOS tick.  This uses timer 0, but\n * could have alternatively used the watchdog timer or timer 1.\n */\nvoid vPortSetupTimerInterrupt( void );\n/*-----------------------------------------------------------*/\n\n/*\n * Initialise the stack of a task to look exactly as if a call to\n * portSAVE_CONTEXT had been called.\n *\n * See the header file portable.h.\n */\nStackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )\n{\n\t/*\n\t\tPlace a few bytes of known values on the bottom of the stack.\n\t\tThis is just useful for debugging and can be included if required.\n\n\t\t*pxTopOfStack = ( StackType_t ) 0x1111;\n\t\tpxTopOfStack--;\n\t\t*pxTopOfStack = ( StackType_t ) 0x2222;\n\t\tpxTopOfStack--;\n\t\t*pxTopOfStack = ( StackType_t ) 0x3333;\n\t\tpxTopOfStack--;\n\t*/\n\n\t/* The msp430 automatically pushes the PC then SR onto the stack before\n\texecuting an ISR.  We want the stack to look just as if this has happened\n\tso place a pointer to the start of the task on the stack first - followed\n\tby the flags we want the task to use when it starts up. */\n\t*pxTopOfStack = ( StackType_t ) pxCode;\n\tpxTopOfStack--;\n\t*pxTopOfStack = portFLAGS_INT_ENABLED;\n\tpxTopOfStack--;\n\n\t/* Next the general purpose registers. */\n\t*pxTopOfStack = ( StackType_t ) 0x4444;\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x5555;\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x6666;\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x7777;\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x8888;\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x9999;\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0xaaaa;\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0xbbbb;\n\tpxTopOfStack--;\t\n\t\n\t/* When the task starts is will expect to find the function parameter in\n\tR15. */\n\t*pxTopOfStack = ( StackType_t ) pvParameters;\n\tpxTopOfStack--;\n\t\n\t*pxTopOfStack = ( StackType_t ) 0xdddd;\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0xeeee;\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0xffff;\n\tpxTopOfStack--;\n\n\t/* A variable is used to keep track of the critical section nesting.\n\tThis variable has to be stored as part of the task context and is\n\tinitially set to zero. */\n\t*pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;\t\n\n\t/* Return a pointer to the top of the stack we have generated so this can\n\tbe stored in the task control block for the task. */\n\treturn pxTopOfStack;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEndScheduler( void )\n{\n\t/* It is unlikely that the MSP430 port will get stopped.  If required simply\n\tdisable the tick interrupt here. */\n}\n/*-----------------------------------------------------------*/\n\n/*\n * Hardware initialisation to generate the RTOS tick.  This uses timer 0\n * but could alternatively use the watchdog timer or timer 1.\n */\nvoid vPortSetupTimerInterrupt( void )\n{\n\t/* Ensure the timer is stopped. */\n\tTACTL = 0;\n\n\t/* Run the timer of the ACLK. */\n\tTACTL = TASSEL_1;\n\n\t/* Clear everything to start with. */\n\tTACTL |= TACLR;\n\n\t/* Set the compare match value according to the tick rate we want. */\n\tTACCR0 = portACLK_FREQUENCY_HZ / configTICK_RATE_HZ;\n\n\t/* Enable the interrupts. */\n\tTACCTL0 = CCIE;\n\n\t/* Start up clean. */\n\tTACTL |= TACLR;\n\n\t/* Up mode. */\n\tTACTL |= MC_1;\n}\n/*-----------------------------------------------------------*/\n\n\n\t\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/MSP430/portasm.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef PORTASM_H\n#define PORTASM_H\n\nportSAVE_CONTEXT macro\n\n\t\tIMPORT pxCurrentTCB\n\t\tIMPORT usCriticalNesting\n\n\t\t/* Save the remaining registers. */\n\t\tpush\tr4\n\t\tpush\tr5\n\t\tpush\tr6\n\t\tpush\tr7\n\t\tpush\tr8\n\t\tpush\tr9\n\t\tpush\tr10\n\t\tpush\tr11\n\t\tpush\tr12\n\t\tpush\tr13\n\t\tpush\tr14\n\t\tpush\tr15\n\t\tmov.w\t&usCriticalNesting, r14\n\t\tpush\tr14\n\t\tmov.w\t&pxCurrentTCB, r12\n\t\tmov.w\tr1, 0(r12)\n\t\tendm\n/*-----------------------------------------------------------*/\n\t\t\nportRESTORE_CONTEXT macro\n\t\tmov.w\t&pxCurrentTCB, r12\n\t\tmov.w\t@r12, r1\n\t\tpop\t\tr15\n\t\tmov.w\tr15, &usCriticalNesting\n\t\tpop\t\tr15\n\t\tpop\t\tr14\n\t\tpop\t\tr13\n\t\tpop\t\tr12\n\t\tpop\t\tr11\n\t\tpop\t\tr10\n\t\tpop\t\tr9\n\t\tpop\t\tr8\n\t\tpop\t\tr7\n\t\tpop\t\tr6\n\t\tpop\t\tr5\n\t\tpop\t\tr4\n\n\t\t/* The last thing on the stack will be the status register.\n        Ensure the power down bits are clear ready for the next\n        time this power down register is popped from the stack. */\n\t\tbic.w   #0xf0,0(SP)\n\n\t\treti\n\t\tendm\n/*-----------------------------------------------------------*/\n\n#endif\n\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/MSP430/portext.s43",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n#include \"FreeRTOSConfig.h\"\n#include \"portasm.h\"\n\n\tIMPORT xTaskIncrementTick\n\tIMPORT vTaskSwitchContext\n\tIMPORT vPortSetupTimerInterrupt\n\n\tEXPORT vTickISR\n\tEXPORT vPortYield\n\tEXPORT xPortStartScheduler\n\n\tRSEG CODE\n\n/*\n * The RTOS tick ISR.\n *\n * If the cooperative scheduler is in use this simply increments the tick\n * count.\n *\n * If the preemptive scheduler is in use a context switch can also occur.\n */\nvTickISR:\n\tportSAVE_CONTEXT\n\n\tcall\t#xTaskIncrementTick\n\tcmp.w\t#0x0, R12\n    jeq\t\tSkipContextSwitch\n\tcall\t#vTaskSwitchContext\nSkipContextSwitch:\n\n\tportRESTORE_CONTEXT\n/*-----------------------------------------------------------*/\n\n\n/*\n * Manual context switch called by the portYIELD() macro.\n */\nvPortYield:\n\n\t/* Mimic an interrupt by pushing the SR. */\n\tpush\tSR\n\n\t/* Now the SR is stacked we can disable interrupts. */\n\tdint\n\n\t/* Save the context of the current task. */\n\tportSAVE_CONTEXT\n\n\t/* Switch to the highest priority task that is ready to run. */\n\tcall\t#vTaskSwitchContext\n\n\t/* Restore the context of the new task. */\n\tportRESTORE_CONTEXT\n/*-----------------------------------------------------------*/\n\n\n/*\n * Start off the scheduler by initialising the RTOS tick timer, then restoring\n * the context of the first task.\n */\nxPortStartScheduler:\n\n\t/* Setup the hardware to generate the tick.  Interrupts are disabled\n\twhen this function is called. */\n\tcall\t#vPortSetupTimerInterrupt\n\n\t/* Restore the context of the first task that is going to run. */\n\tportRESTORE_CONTEXT\n/*-----------------------------------------------------------*/\n\n\n\t/* Install vTickISR as the timer A0 interrupt. */\n\tASEG\n\tORG 0xFFE0 + TIMERA0_VECTOR\n\n\t_vTickISR_: DC16 vTickISR\n\n\n\tEND\n\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/MSP430/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef PORTMACRO_H\n#define PORTMACRO_H\n\n/*-----------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the\n * given hardware and compiler.\n *\n * These settings should not be altered.\n *-----------------------------------------------------------\n */\n\n/* Type definitions. */\n#define portCHAR\t\tchar\n#define portFLOAT\t\tfloat\n#define portDOUBLE\t\tdouble\n#define portLONG\t\tlong\n#define portSHORT\t\tint\n#define portSTACK_TYPE\tuint16_t\n#define portBASE_TYPE\tshort\n\ntypedef portSTACK_TYPE StackType_t;\ntypedef short BaseType_t;\ntypedef unsigned short UBaseType_t;\n\n\n#if( configUSE_16_BIT_TICKS == 1 )\n\ttypedef uint16_t TickType_t;\n\t#define portMAX_DELAY ( TickType_t ) 0xffff\n#else\n\ttypedef uint32_t TickType_t;\n\t#define portMAX_DELAY ( TickType_t ) 0xffffffffUL\n#endif\n\n/*-----------------------------------------------------------*/\n\n/* Interrupt control macros. */\n#define portDISABLE_INTERRUPTS()\t_DINT(); _NOP()\n#define portENABLE_INTERRUPTS()\t\t_EINT(); _NOP()\n/*-----------------------------------------------------------*/\n\n/* Critical section control macros. */\n#define portNO_CRITICAL_SECTION_NESTING\t\t( ( uint16_t ) 0 )\n\n#define portENTER_CRITICAL()\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\nextern volatile uint16_t usCriticalNesting;\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tportDISABLE_INTERRUPTS();\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* Now interrupts are disabled usCriticalNesting can be accessed */\t\t\t\\\n\t/* directly.  Increment ulCriticalNesting to keep a count of how many */\t\\\n\t/* times portENTER_CRITICAL() has been called. */\t\t\t\t\t\t\t\\\n\tusCriticalNesting++;\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n}\n\n#define portEXIT_CRITICAL()\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\nextern volatile uint16_t usCriticalNesting;\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tif( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING )\t\t\t\t\t\\\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t/* Decrement the nesting count as we are leaving a critical section. */\t\\\n\t\tusCriticalNesting--;\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t/* If the nesting level has reached zero then interrupts should be */\t\\\n\t\t/* re-enabled. */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tif( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING )\t\t\t\t\\\n\t\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\tportENABLE_INTERRUPTS();\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n}\n/*-----------------------------------------------------------*/\n\n/* Task utilities. */\n\n/*\n * Manual context switch called by portYIELD or taskYIELD.\n */\nextern void vPortYield( void );\n#define portYIELD() vPortYield()\n/*-----------------------------------------------------------*/\n\n/* Hardware specifics. */\n#define portBYTE_ALIGNMENT\t\t\t2\n#define portSTACK_GROWTH\t\t\t( -1 )\n#define portTICK_PERIOD_MS\t\t\t( ( TickType_t ) 1000 / configTICK_RATE_HZ )\n#define portNOP()\n#define portPOINTER_SIZE_TYPE\t\tuint16_t\n/*-----------------------------------------------------------*/\n\n/* Task function macros as described on the FreeRTOS.org WEB site. */\n#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\n#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\n\n#if configINTERRUPT_EXAMPLE_METHOD == 2\n\nextern void vTaskSwitchContext( void );\n#define portYIELD_FROM_ISR( x ) do { if( x ) vTaskSwitchContext(); } while( 0 )\n\n#endif\n\n#endif /* PORTMACRO_H */\n\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/MSP430X/data_model.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef DATA_MODEL_H\n#define DATA_MODEL_H\n\n#if __DATA_MODEL__ == __DATA_MODEL_SMALL__\n\t#define pushm_x pushm.w\n\t#define popm_x popm.w\n\t#define push_x push.w\n\t#define pop_x pop.w\n\t#define mov_x mov.w\n\t#define cmp_x cmp.w\n#endif\n\n#if __DATA_MODEL__ == __DATA_MODEL_MEDIUM__\n\t#define pushm_x pushm.a\n\t#define popm_x popm.a\n\t#define push_x pushx.a\n\t#define pop_x popx.a\n\t#define mov_x mov.w\n\t#define cmp_x cmp.w\n#endif\n\n#if __DATA_MODEL__ == __DATA_MODEL_LARGE__\n\t#define pushm_x pushm.a\n\t#define popm_x popm.a\n\t#define push_x pushx.a\n\t#define pop_x popx.a\n\t#define mov_x movx.a\n\t#define cmp_x cmpx.a\n#endif\n\n#ifndef pushm_x\n\t#error The assembler options must define one of the following symbols: __DATA_MODEL_SMALL__, __DATA_MODEL_MEDIUM__, or __DATA_MODEL_LARGE__\n#endif\n\n#endif /* DATA_MODEL_H */\n\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/MSP430X/port.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n/*-----------------------------------------------------------\n * Implementation of functions defined in portable.h for the MSP430X port.\n *----------------------------------------------------------*/\n\n/* Constants required for hardware setup.  The tick ISR runs off the ACLK,\nnot the MCLK. */\n#define portACLK_FREQUENCY_HZ\t\t\t( ( TickType_t ) 32768 )\n#define portINITIAL_CRITICAL_NESTING\t( ( uint16_t ) 10 )\n#define portFLAGS_INT_ENABLED\t\t\t( ( StackType_t ) 0x08 )\n\n/* We require the address of the pxCurrentTCB variable, but don't want to know\nany details of its type. */\ntypedef void TCB_t;\nextern volatile TCB_t * volatile pxCurrentTCB;\n\n/* Each task maintains a count of the critical section nesting depth.  Each\ntime a critical section is entered the count is incremented.  Each time a\ncritical section is exited the count is decremented - with interrupts only\nbeing re-enabled if the count is zero.\n\nusCriticalNesting will get set to zero when the scheduler starts, but must\nnot be initialised to zero as this will cause problems during the startup\nsequence. */\nvolatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;\n/*-----------------------------------------------------------*/\n\n\n/*\n * Sets up the periodic ISR used for the RTOS tick.  This uses timer 0, but\n * could have alternatively used the watchdog timer or timer 1.\n */\nvoid vPortSetupTimerInterrupt( void );\n/*-----------------------------------------------------------*/\n\n/*\n * Initialise the stack of a task to look exactly as if a call to\n * portSAVE_CONTEXT had been called.\n *\n * See the header file portable.h.\n */\nStackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )\n{\nuint16_t *pusTopOfStack;\nuint32_t *pulTopOfStack;\n\n\t/*\n\t\tPlace a few bytes of known values on the bottom of the stack.\n\t\tThis is just useful for debugging and can be included if required.\n\t\n\t\t*pxTopOfStack = ( StackType_t ) 0x1111;\n\t\tpxTopOfStack--;\n\t\t*pxTopOfStack = ( StackType_t ) 0x2222;\n\t\tpxTopOfStack--;\n\t\t*pxTopOfStack = ( StackType_t ) 0x3333;\n\t*/\n\n\t/* StackType_t is either 16 bits or 32 bits depending on the data model.\n\tSome stacked items do not change size depending on the data model so have\n\tto be explicitly cast to the correct size so this function will work\n\twhichever data model is being used. */\n\tif( sizeof( StackType_t ) == sizeof( uint16_t ) )\n\t{\n\t\t/* Make room for a 20 bit value stored as a 32 bit value. */\n\t\tpusTopOfStack = ( uint16_t * ) pxTopOfStack;\n\t\tpusTopOfStack--;\n\t\tpulTopOfStack = ( uint32_t * ) pusTopOfStack;\n\t}\n\telse\n\t{\n\t\tpulTopOfStack = ( uint32_t * ) pxTopOfStack;\n\t}\n\t*pulTopOfStack = ( uint32_t ) pxCode;\n\t\n\tpusTopOfStack = ( uint16_t * ) pulTopOfStack;\n\tpusTopOfStack--;\n\t*pusTopOfStack = portFLAGS_INT_ENABLED;\n\tpusTopOfStack -= ( sizeof( StackType_t ) / 2 );\n\t\n\t/* From here on the size of stacked items depends on the memory model. */\n\tpxTopOfStack = ( StackType_t * ) pusTopOfStack;\n\n\t/* Next the general purpose registers. */\n\t#ifdef PRELOAD_REGISTER_VALUES\n\t\t*pxTopOfStack = ( StackType_t ) 0xffff;\n\t\tpxTopOfStack--;\n\t\t*pxTopOfStack = ( StackType_t ) 0xeeee;\n\t\tpxTopOfStack--;\n\t\t*pxTopOfStack = ( StackType_t ) 0xdddd;\n\t\tpxTopOfStack--;\n\t\t*pxTopOfStack = ( StackType_t ) pvParameters;\n\t\tpxTopOfStack--;\n\t\t*pxTopOfStack = ( StackType_t ) 0xbbbb;\n\t\tpxTopOfStack--;\n\t\t*pxTopOfStack = ( StackType_t ) 0xaaaa;\n\t\tpxTopOfStack--;\n\t\t*pxTopOfStack = ( StackType_t ) 0x9999;\n\t\tpxTopOfStack--;\n\t\t*pxTopOfStack = ( StackType_t ) 0x8888;\n\t\tpxTopOfStack--;\t\n\t\t*pxTopOfStack = ( StackType_t ) 0x5555;\n\t\tpxTopOfStack--;\n\t\t*pxTopOfStack = ( StackType_t ) 0x6666;\n\t\tpxTopOfStack--;\n\t\t*pxTopOfStack = ( StackType_t ) 0x5555;\n\t\tpxTopOfStack--;\n\t\t*pxTopOfStack = ( StackType_t ) 0x4444;\n\t\tpxTopOfStack--;\n\t#else\n\t\tpxTopOfStack -= 3;\n\t\t*pxTopOfStack = ( StackType_t ) pvParameters;\n\t\tpxTopOfStack -= 9;\n\t#endif\n\n\n\t/* A variable is used to keep track of the critical section nesting.\n\tThis variable has to be stored as part of the task context and is\n\tinitially set to zero. */\n\t*pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;\t\n\n\t/* Return a pointer to the top of the stack we have generated so this can\n\tbe stored in the task control block for the task. */\n\treturn pxTopOfStack;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEndScheduler( void )\n{\n\t/* It is unlikely that the MSP430 port will get stopped.  If required simply\n\tdisable the tick interrupt here. */\n}\n/*-----------------------------------------------------------*/\n\n/*\n * Hardware initialisation to generate the RTOS tick.\n */\nvoid vPortSetupTimerInterrupt( void )\n{\n\tvApplicationSetupTimerInterrupt();\n}\n/*-----------------------------------------------------------*/\n\n#pragma vector=configTICK_VECTOR\n__interrupt __raw void vTickISREntry( void )\n{\nextern void vPortTickISR( void );\n\n\t__bic_SR_register_on_exit( SCG1 + SCG0 + OSCOFF + CPUOFF );\n\tvPortTickISR();\n}\n\n\t\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/MSP430X/portext.s43",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n#include \"msp430.h\"\n#include \"FreeRTOSConfig.h\"\n#include \"data_model.h\"\n\n\tIMPORT xTaskIncrementTick\n\tIMPORT vTaskSwitchContext\n\tIMPORT vPortSetupTimerInterrupt\n\tIMPORT pxCurrentTCB\n\tIMPORT usCriticalNesting\n\n\tEXPORT vPortTickISR\n\tEXPORT vPortYield\n\tEXPORT xPortStartScheduler\n\nportSAVE_CONTEXT macro\n\n\t/* Save the remaining registers. */\n\tpushm_x\t#12, r15\n\tmov.w\t&usCriticalNesting, r14\n\tpush_x r14\n\tmov_x\t&pxCurrentTCB, r12\n\tmov_x\tsp, 0( r12 )\n\tendm\n/*-----------------------------------------------------------*/\n\nportRESTORE_CONTEXT macro\n\n\tmov_x\t&pxCurrentTCB, r12\n\tmov_x\t@r12, sp\n\tpop_x\tr15\n\tmov.w\tr15, &usCriticalNesting\n\tpopm_x\t#12, r15\n\tnop\n\tpop.w\tsr\n\tnop\n\treta\n\tendm\n/*-----------------------------------------------------------*/\n\n\n/*\n * The RTOS tick ISR.\n *\n * If the cooperative scheduler is in use this simply increments the tick\n * count.\n *\n * If the preemptive scheduler is in use a context switch can also occur.\n */\n\n\tRSEG CODE\n\tEVEN\n\nvPortTickISR:\n\n\t/* The sr is not saved in portSAVE_CONTEXT() because vPortYield() needs\n\tto save it manually before it gets modified (interrupts get disabled).\n\tEntering through this interrupt means the SR is already on the stack, but\n\tthis keeps the stack frames identical. */\n\tpush.w sr\n\tportSAVE_CONTEXT\n\n\tcalla\t#xTaskIncrementTick\n\tcmp.w   #0x0, R12\n    jeq     SkipContextSwitch\n    calla   #vTaskSwitchContext\nSkipContextSwitch:\n\tportRESTORE_CONTEXT\n/*-----------------------------------------------------------*/\n\n/*\n * Manual context switch called by the portYIELD() macro.\n */\n \tEVEN\n\nvPortYield:\n\n\t/* The sr needs saving before it is modified. */\n\tpush.w\tsr\n\n\t/* Now the SR is stacked interrupts can be disabled. */\n\tdint\n\tnop\n\n\t/* Save the context of the current task. */\n\tportSAVE_CONTEXT\n\n\t/* Select the next task to run. */\n\tcalla\t#vTaskSwitchContext\n\n\t/* Restore the context of the new task. */\n\tportRESTORE_CONTEXT\n/*-----------------------------------------------------------*/\n\n\n/*\n * Start off the scheduler by initialising the RTOS tick timer, then restoring\n * the context of the first task.\n */\n \tEVEN\n\nxPortStartScheduler:\n\n\t/* Setup the hardware to generate the tick.  Interrupts are disabled\n\twhen this function is called. */\n\tcalla\t#vPortSetupTimerInterrupt\n\n\t/* Restore the context of the first task that is going to run. */\n\tportRESTORE_CONTEXT\n/*-----------------------------------------------------------*/\n\n\tEND\n\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/IAR/MSP430X/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef PORTMACRO_H\n#define PORTMACRO_H\n\n/*-----------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the\n * given hardware and compiler.\n *\n * These settings should not be altered.\n *-----------------------------------------------------------\n */\n\n/* Hardware includes. */\n#include \"msp430.h\"\n\n/* Type definitions. */\n#define portCHAR\t\tchar\n#define portFLOAT\t\tfloat\n#define portDOUBLE\t\tdouble\n#define portLONG\t\tlong\n#define portSHORT\t\tint\n#define portBASE_TYPE\tshort\n\n/* The stack type changes depending on the data model. */\n#if( __DATA_MODEL__ == __DATA_MODEL_SMALL__ )\n\t#define portSTACK_TYPE uint16_t\n\t#define portPOINTER_SIZE_TYPE uint16_t\n#else\n\t#define portSTACK_TYPE uint32_t\n#endif\n\ntypedef portSTACK_TYPE StackType_t;\ntypedef short BaseType_t;\ntypedef unsigned short UBaseType_t;\n\n#if( configUSE_16_BIT_TICKS == 1 )\n\ttypedef uint16_t TickType_t;\n\t#define portMAX_DELAY ( TickType_t ) 0xffff\n#else\n\ttypedef uint32_t TickType_t;\n\t#define portMAX_DELAY ( TickType_t ) 0xffffffffUL\n#endif\n\n/*-----------------------------------------------------------*/\n\n/* Interrupt control macros. */\n#define portDISABLE_INTERRUPTS()\t_DINT(); _NOP()\n#define portENABLE_INTERRUPTS()\t\t_EINT(); _NOP()\n/*-----------------------------------------------------------*/\n\n/* Critical section control macros. */\n#define portNO_CRITICAL_SECTION_NESTING\t\t( ( uint16_t ) 0 )\n\n#define portENTER_CRITICAL()\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\nextern volatile uint16_t usCriticalNesting;\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tportDISABLE_INTERRUPTS();\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* Now interrupts are disabled usCriticalNesting can be accessed */\t\t\t\\\n\t/* directly.  Increment ulCriticalNesting to keep a count of how many */\t\\\n\t/* times portENTER_CRITICAL() has been called. */\t\t\t\t\t\t\t\\\n\tusCriticalNesting++;\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n}\n\n#define portEXIT_CRITICAL()\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\nextern volatile uint16_t usCriticalNesting;\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tif( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING )\t\t\t\t\t\\\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t/* Decrement the nesting count as we are leaving a critical section. */\t\\\n\t\tusCriticalNesting--;\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t/* If the nesting level has reached zero then interrupts should be */\t\\\n\t\t/* re-enabled. */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tif( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING )\t\t\t\t\\\n\t\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\tportENABLE_INTERRUPTS();\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n}\n/*-----------------------------------------------------------*/\n\n/* Task utilities. */\n\n/*\n * Manual context switch called by portYIELD or taskYIELD.\n */\nextern void vPortYield( void );\n#define portYIELD() vPortYield()\n/*-----------------------------------------------------------*/\n\n/* Hardware specifics. */\n#define portBYTE_ALIGNMENT\t\t\t2\n#define portSTACK_GROWTH\t\t\t( -1 )\n#define portTICK_PERIOD_MS\t\t\t( ( TickType_t ) 1000 / configTICK_RATE_HZ )\n#define portNOP()\t\t\t\t\t__no_operation()\n/*-----------------------------------------------------------*/\n\n/* Task function macros as described on the FreeRTOS.org WEB site. */\n#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\n#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\n\n#define portYIELD_FROM_ISR( x ) do { if( x ) vPortYield(); } while( 0 )\n\nvoid vApplicationSetupTimerInterrupt( void );\n\n/* sizeof( int ) != sizeof( long ) so a full printf() library is required if\nrun time stats information is to be displayed. */\n#define portLU_PRINTF_SPECIFIER_REQUIRED\n\n#endif /* PORTMACRO_H */\n\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/Keil/See-also-the-RVDS-directory.txt",
    "content": "Nothing to see here."
  },
  {
    "path": "FreeRTOS-comparison/portable/MemMang/ReadMe.url",
    "content": "[{000214A0-0000-0000-C000-000000000046}]\nProp3=19,2\n[InternetShortcut]\nURL=https://www.FreeRTOS.org/a00111.html\nIDList=\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/MemMang/heap_1.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n\n/*\n * The simplest possible implementation of pvPortMalloc().  Note that this\n * implementation does NOT allow allocated memory to be freed again.\n *\n * See heap_2.c, heap_3.c and heap_4.c for alternative implementations, and the\n * memory management pages of https://www.FreeRTOS.org for more information.\n */\n#include <stdlib.h>\n\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\n * all the API functions to use the MPU wrappers.  That should only be done when\n * task.h is included from an application file. */\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n#if ( configSUPPORT_DYNAMIC_ALLOCATION == 0 )\n    #error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0\n#endif\n\n/* A few bytes might be lost to byte aligning the heap start address. */\n#define configADJUSTED_HEAP_SIZE    ( configTOTAL_HEAP_SIZE - portBYTE_ALIGNMENT )\n\n/* Allocate the memory for the heap. */\n#if ( configAPPLICATION_ALLOCATED_HEAP == 1 )\n\n/* The application writer has already defined the array used for the RTOS\n* heap - probably so it can be placed in a special segment or address. */\n    extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];\n#else\n    static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];\n#endif /* configAPPLICATION_ALLOCATED_HEAP */\n\n/* Index into the ucHeap array. */\nstatic size_t xNextFreeByte = ( size_t ) 0;\n\n/*-----------------------------------------------------------*/\n\nvoid * pvPortMalloc( size_t xWantedSize )\n{\n    void * pvReturn = NULL;\n    static uint8_t * pucAlignedHeap = NULL;\n\n    /* Ensure that blocks are always aligned. */\n    #if ( portBYTE_ALIGNMENT != 1 )\n    {\n        if( xWantedSize & portBYTE_ALIGNMENT_MASK )\n        {\n            /* Byte alignment required. Check for overflow. */\n            if( ( xWantedSize + ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) ) ) > xWantedSize )\n            {\n                xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );\n            }\n            else\n            {\n                xWantedSize = 0;\n            }\n        }\n    }\n    #endif /* if ( portBYTE_ALIGNMENT != 1 ) */\n\n    vTaskSuspendAll();\n    {\n        if( pucAlignedHeap == NULL )\n        {\n            /* Ensure the heap starts on a correctly aligned boundary. */\n            pucAlignedHeap = ( uint8_t * ) ( ( ( portPOINTER_SIZE_TYPE ) & ucHeap[ portBYTE_ALIGNMENT - 1 ] ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) );\n        }\n\n        /* Check there is enough room left for the allocation and. */\n        if( ( xWantedSize > 0 ) &&                                /* valid size */\n            ( ( xNextFreeByte + xWantedSize ) < configADJUSTED_HEAP_SIZE ) &&\n            ( ( xNextFreeByte + xWantedSize ) > xNextFreeByte ) ) /* Check for overflow. */\n        {\n            /* Return the next free byte then increment the index past this\n             * block. */\n            pvReturn = pucAlignedHeap + xNextFreeByte;\n            xNextFreeByte += xWantedSize;\n        }\n\n        traceMALLOC( pvReturn, xWantedSize );\n    }\n    ( void ) xTaskResumeAll();\n\n    #if ( configUSE_MALLOC_FAILED_HOOK == 1 )\n    {\n        if( pvReturn == NULL )\n        {\n            vApplicationMallocFailedHook();\n        }\n    }\n    #endif\n\n    return pvReturn;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortFree( void * pv )\n{\n    /* Memory cannot be freed using this scheme.  See heap_2.c, heap_3.c and\n     * heap_4.c for alternative implementations, and the memory management pages of\n     * https://www.FreeRTOS.org for more information. */\n    ( void ) pv;\n\n    /* Force an assert as it is invalid to call this function. */\n    configASSERT( pv == NULL );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortInitialiseBlocks( void )\n{\n    /* Only required when static memory is not cleared. */\n    xNextFreeByte = ( size_t ) 0;\n}\n/*-----------------------------------------------------------*/\n\nsize_t xPortGetFreeHeapSize( void )\n{\n    return( configADJUSTED_HEAP_SIZE - xNextFreeByte );\n}\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/MemMang/heap_2.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/*\n * A sample implementation of pvPortMalloc() and vPortFree() that permits\n * allocated blocks to be freed, but does not combine adjacent free blocks\n * into a single larger block (and so will fragment memory).  See heap_4.c for\n * an equivalent that does combine adjacent blocks into single larger blocks.\n *\n * See heap_1.c, heap_3.c and heap_4.c for alternative implementations, and the\n * memory management pages of https://www.FreeRTOS.org for more information.\n */\n#include <stdlib.h>\n#include <string.h>\n\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\n * all the API functions to use the MPU wrappers.  That should only be done when\n * task.h is included from an application file. */\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n#if ( configSUPPORT_DYNAMIC_ALLOCATION == 0 )\n    #error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0\n#endif\n\n#ifndef configHEAP_CLEAR_MEMORY_ON_FREE\n    #define configHEAP_CLEAR_MEMORY_ON_FREE    0\n#endif\n\n/* A few bytes might be lost to byte aligning the heap start address. */\n#define configADJUSTED_HEAP_SIZE    ( configTOTAL_HEAP_SIZE - portBYTE_ALIGNMENT )\n\n/* Assumes 8bit bytes! */\n#define heapBITS_PER_BYTE           ( ( size_t ) 8 )\n\n/* Max value that fits in a size_t type. */\n#define heapSIZE_MAX                ( ~( ( size_t ) 0 ) )\n\n/* Check if multiplying a and b will result in overflow. */\n#define heapMULTIPLY_WILL_OVERFLOW( a, b )    ( ( ( a ) > 0 ) && ( ( b ) > ( heapSIZE_MAX / ( a ) ) ) )\n\n/* Check if adding a and b will result in overflow. */\n#define heapADD_WILL_OVERFLOW( a, b )         ( ( a ) > ( heapSIZE_MAX - ( b ) ) )\n\n/* MSB of the xBlockSize member of an BlockLink_t structure is used to track\n * the allocation status of a block.  When MSB of the xBlockSize member of\n * an BlockLink_t structure is set then the block belongs to the application.\n * When the bit is free the block is still part of the free heap space. */\n#define heapBLOCK_ALLOCATED_BITMASK    ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 ) )\n#define heapBLOCK_SIZE_IS_VALID( xBlockSize )    ( ( ( xBlockSize ) & heapBLOCK_ALLOCATED_BITMASK ) == 0 )\n#define heapBLOCK_IS_ALLOCATED( pxBlock )        ( ( ( pxBlock->xBlockSize ) & heapBLOCK_ALLOCATED_BITMASK ) != 0 )\n#define heapALLOCATE_BLOCK( pxBlock )            ( ( pxBlock->xBlockSize ) |= heapBLOCK_ALLOCATED_BITMASK )\n#define heapFREE_BLOCK( pxBlock )                ( ( pxBlock->xBlockSize ) &= ~heapBLOCK_ALLOCATED_BITMASK )\n\n/*-----------------------------------------------------------*/\n\n/* Allocate the memory for the heap. */\n#if ( configAPPLICATION_ALLOCATED_HEAP == 1 )\n\n/* The application writer has already defined the array used for the RTOS\n* heap - probably so it can be placed in a special segment or address. */\n    extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];\n#else\n    PRIVILEGED_DATA static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];\n#endif /* configAPPLICATION_ALLOCATED_HEAP */\n\n\n/* Define the linked list structure.  This is used to link free blocks in order\n * of their size. */\ntypedef struct A_BLOCK_LINK\n{\n    struct A_BLOCK_LINK * pxNextFreeBlock; /*<< The next free block in the list. */\n    size_t xBlockSize;                     /*<< The size of the free block. */\n} BlockLink_t;\n\n\nstatic const uint16_t heapSTRUCT_SIZE = ( ( sizeof( BlockLink_t ) + ( portBYTE_ALIGNMENT - 1 ) ) & ~( ( size_t ) portBYTE_ALIGNMENT_MASK ) );\n#define heapMINIMUM_BLOCK_SIZE    ( ( size_t ) ( heapSTRUCT_SIZE * 2 ) )\n\n/* Create a couple of list links to mark the start and end of the list. */\nPRIVILEGED_DATA static BlockLink_t xStart, xEnd;\n\n/* Keeps track of the number of free bytes remaining, but says nothing about\n * fragmentation. */\nPRIVILEGED_DATA static size_t xFreeBytesRemaining = configADJUSTED_HEAP_SIZE;\n\n/*-----------------------------------------------------------*/\n\n/*\n * Initialises the heap structures before their first use.\n */\nstatic void prvHeapInit( void ) PRIVILEGED_FUNCTION;\n\n/*-----------------------------------------------------------*/\n\n/* STATIC FUNCTIONS ARE DEFINED AS MACROS TO MINIMIZE THE FUNCTION CALL DEPTH. */\n\n/*\n * Insert a block into the list of free blocks - which is ordered by size of\n * the block.  Small blocks at the start of the list and large blocks at the end\n * of the list.\n */\n#define prvInsertBlockIntoFreeList( pxBlockToInsert )                                                                               \\\n    {                                                                                                                               \\\n        BlockLink_t * pxIterator;                                                                                                   \\\n        size_t xBlockSize;                                                                                                          \\\n                                                                                                                                    \\\n        xBlockSize = pxBlockToInsert->xBlockSize;                                                                                   \\\n                                                                                                                                    \\\n        /* Iterate through the list until a block is found that has a larger size */                                                \\\n        /* than the block we are inserting. */                                                                                      \\\n        for( pxIterator = &xStart; pxIterator->pxNextFreeBlock->xBlockSize < xBlockSize; pxIterator = pxIterator->pxNextFreeBlock ) \\\n        {                                                                                                                           \\\n            /* There is nothing to do here - just iterate to the correct position. */                                               \\\n        }                                                                                                                           \\\n                                                                                                                                    \\\n        /* Update the list to include the block being inserted in the correct */                                                    \\\n        /* position. */                                                                                                             \\\n        pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;                                                             \\\n        pxIterator->pxNextFreeBlock = pxBlockToInsert;                                                                              \\\n    }\n/*-----------------------------------------------------------*/\n\nvoid * pvPortMalloc( size_t xWantedSize )\n{\n    BlockLink_t * pxBlock;\n    BlockLink_t * pxPreviousBlock;\n    BlockLink_t * pxNewBlockLink;\n    PRIVILEGED_DATA static BaseType_t xHeapHasBeenInitialised = pdFALSE;\n    void * pvReturn = NULL;\n    size_t xAdditionalRequiredSize;\n\n    vTaskSuspendAll();\n    {\n        /* If this is the first call to malloc then the heap will require\n         * initialisation to setup the list of free blocks. */\n        if( xHeapHasBeenInitialised == pdFALSE )\n        {\n            prvHeapInit();\n            xHeapHasBeenInitialised = pdTRUE;\n        }\n\n        if( xWantedSize > 0 )\n        {\n            /* The wanted size must be increased so it can contain a BlockLink_t\n             * structure in addition to the requested amount of bytes. Some\n             * additional increment may also be needed for alignment. */\n            xAdditionalRequiredSize = heapSTRUCT_SIZE + portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK );\n\n            if( heapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 )\n            {\n                xWantedSize += xAdditionalRequiredSize;\n            }\n            else\n            {\n                xWantedSize = 0;\n            }\n        }\n\n        /* Check the block size we are trying to allocate is not so large that the\n         * top bit is set.  The top bit of the block size member of the BlockLink_t\n         * structure is used to determine who owns the block - the application or\n         * the kernel, so it must be free. */\n        if( heapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 )\n        {\n            if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )\n            {\n                /* Blocks are stored in byte order - traverse the list from the start\n                 * (smallest) block until one of adequate size is found. */\n                pxPreviousBlock = &xStart;\n                pxBlock = xStart.pxNextFreeBlock;\n\n                while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )\n                {\n                    pxPreviousBlock = pxBlock;\n                    pxBlock = pxBlock->pxNextFreeBlock;\n                }\n\n                /* If we found the end marker then a block of adequate size was not found. */\n                if( pxBlock != &xEnd )\n                {\n                    /* Return the memory space - jumping over the BlockLink_t structure\n                     * at its start. */\n                    pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + heapSTRUCT_SIZE );\n\n                    /* This block is being returned for use so must be taken out of the\n                     * list of free blocks. */\n                    pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;\n\n                    /* If the block is larger than required it can be split into two. */\n                    if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )\n                    {\n                        /* This block is to be split into two.  Create a new block\n                         * following the number of bytes requested. The void cast is\n                         * used to prevent byte alignment warnings from the compiler. */\n                        pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );\n\n                        /* Calculate the sizes of two blocks split from the single\n                         * block. */\n                        pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;\n                        pxBlock->xBlockSize = xWantedSize;\n\n                        /* Insert the new block into the list of free blocks. */\n                        prvInsertBlockIntoFreeList( ( pxNewBlockLink ) );\n                    }\n\n                    xFreeBytesRemaining -= pxBlock->xBlockSize;\n\n                    /* The block is being returned - it is allocated and owned\n                     * by the application and has no \"next\" block. */\n                    heapALLOCATE_BLOCK( pxBlock );\n                    pxBlock->pxNextFreeBlock = NULL;\n                }\n            }\n        }\n\n        traceMALLOC( pvReturn, xWantedSize );\n    }\n    ( void ) xTaskResumeAll();\n\n    #if ( configUSE_MALLOC_FAILED_HOOK == 1 )\n    {\n        if( pvReturn == NULL )\n        {\n            vApplicationMallocFailedHook();\n        }\n    }\n    #endif\n\n    return pvReturn;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortFree( void * pv )\n{\n    uint8_t * puc = ( uint8_t * ) pv;\n    BlockLink_t * pxLink;\n\n    if( pv != NULL )\n    {\n        /* The memory being freed will have an BlockLink_t structure immediately\n         * before it. */\n        puc -= heapSTRUCT_SIZE;\n\n        /* This unexpected casting is to keep some compilers from issuing\n         * byte alignment warnings. */\n        pxLink = ( void * ) puc;\n\n        configASSERT( heapBLOCK_IS_ALLOCATED( pxLink ) != 0 );\n        configASSERT( pxLink->pxNextFreeBlock == NULL );\n\n        if( heapBLOCK_IS_ALLOCATED( pxLink ) != 0 )\n        {\n            if( pxLink->pxNextFreeBlock == NULL )\n            {\n                /* The block is being returned to the heap - it is no longer\n                 * allocated. */\n                heapFREE_BLOCK( pxLink );\n                #if ( configHEAP_CLEAR_MEMORY_ON_FREE == 1 )\n                {\n                    ( void ) memset( puc + heapSTRUCT_SIZE, 0, pxLink->xBlockSize - heapSTRUCT_SIZE );\n                }\n                #endif\n\n                vTaskSuspendAll();\n                {\n                    /* Add this block to the list of free blocks. */\n                    prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );\n                    xFreeBytesRemaining += pxLink->xBlockSize;\n                    traceFREE( pv, pxLink->xBlockSize );\n                }\n                ( void ) xTaskResumeAll();\n            }\n        }\n    }\n}\n/*-----------------------------------------------------------*/\n\nsize_t xPortGetFreeHeapSize( void )\n{\n    return xFreeBytesRemaining;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortInitialiseBlocks( void )\n{\n    /* This just exists to keep the linker quiet. */\n}\n/*-----------------------------------------------------------*/\n\nvoid * pvPortCalloc( size_t xNum,\n                     size_t xSize )\n{\n    void * pv = NULL;\n\n    if( heapMULTIPLY_WILL_OVERFLOW( xNum, xSize ) == 0 )\n    {\n        pv = pvPortMalloc( xNum * xSize );\n\n        if( pv != NULL )\n        {\n            ( void ) memset( pv, 0, xNum * xSize );\n        }\n    }\n\n    return pv;\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvHeapInit( void ) /* PRIVILEGED_FUNCTION */\n{\n    BlockLink_t * pxFirstFreeBlock;\n    uint8_t * pucAlignedHeap;\n\n    /* Ensure the heap starts on a correctly aligned boundary. */\n    pucAlignedHeap = ( uint8_t * ) ( ( ( portPOINTER_SIZE_TYPE ) & ucHeap[ portBYTE_ALIGNMENT - 1 ] ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) );\n\n    /* xStart is used to hold a pointer to the first item in the list of free\n     * blocks.  The void cast is used to prevent compiler warnings. */\n    xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;\n    xStart.xBlockSize = ( size_t ) 0;\n\n    /* xEnd is used to mark the end of the list of free blocks. */\n    xEnd.xBlockSize = configADJUSTED_HEAP_SIZE;\n    xEnd.pxNextFreeBlock = NULL;\n\n    /* To start with there is a single free block that is sized to take up the\n     * entire heap space. */\n    pxFirstFreeBlock = ( BlockLink_t * ) pucAlignedHeap;\n    pxFirstFreeBlock->xBlockSize = configADJUSTED_HEAP_SIZE;\n    pxFirstFreeBlock->pxNextFreeBlock = &xEnd;\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/MemMang/heap_3.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n\n/*\n * Implementation of pvPortMalloc() and vPortFree() that relies on the\n * compilers own malloc() and free() implementations.\n *\n * This file can only be used if the linker is configured to to generate\n * a heap memory area.\n *\n * See heap_1.c, heap_2.c and heap_4.c for alternative implementations, and the\n * memory management pages of https://www.FreeRTOS.org for more information.\n */\n\n#include <stdlib.h>\n\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\n * all the API functions to use the MPU wrappers.  That should only be done when\n * task.h is included from an application file. */\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n#if ( configSUPPORT_DYNAMIC_ALLOCATION == 0 )\n    #error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0\n#endif\n\n/*-----------------------------------------------------------*/\n\nvoid * pvPortMalloc( size_t xWantedSize )\n{\n    void * pvReturn;\n\n    vTaskSuspendAll();\n    {\n        pvReturn = malloc( xWantedSize );\n        traceMALLOC( pvReturn, xWantedSize );\n    }\n    ( void ) xTaskResumeAll();\n\n    #if ( configUSE_MALLOC_FAILED_HOOK == 1 )\n    {\n        if( pvReturn == NULL )\n        {\n            vApplicationMallocFailedHook();\n        }\n    }\n    #endif\n\n    return pvReturn;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortFree( void * pv )\n{\n    if( pv != NULL )\n    {\n        vTaskSuspendAll();\n        {\n            free( pv );\n            traceFREE( pv, 0 );\n        }\n        ( void ) xTaskResumeAll();\n    }\n}\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/MemMang/heap_4.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/*\n * A sample implementation of pvPortMalloc() and vPortFree() that combines\n * (coalescences) adjacent memory blocks as they are freed, and in so doing\n * limits memory fragmentation.\n *\n * See heap_1.c, heap_2.c and heap_3.c for alternative implementations, and the\n * memory management pages of https://www.FreeRTOS.org for more information.\n */\n#include <stdlib.h>\n#include <string.h>\n\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\n * all the API functions to use the MPU wrappers.  That should only be done when\n * task.h is included from an application file. */\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n#if ( configSUPPORT_DYNAMIC_ALLOCATION == 0 )\n    #error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0\n#endif\n\n#ifndef configHEAP_CLEAR_MEMORY_ON_FREE\n    #define configHEAP_CLEAR_MEMORY_ON_FREE    0\n#endif\n\n/* Block sizes must not get too small. */\n#define heapMINIMUM_BLOCK_SIZE    ( ( size_t ) ( xHeapStructSize << 1 ) )\n\n/* Assumes 8bit bytes! */\n#define heapBITS_PER_BYTE         ( ( size_t ) 8 )\n\n/* Max value that fits in a size_t type. */\n#define heapSIZE_MAX              ( ~( ( size_t ) 0 ) )\n\n/* Check if multiplying a and b will result in overflow. */\n#define heapMULTIPLY_WILL_OVERFLOW( a, b )    ( ( ( a ) > 0 ) && ( ( b ) > ( heapSIZE_MAX / ( a ) ) ) )\n\n/* Check if adding a and b will result in overflow. */\n#define heapADD_WILL_OVERFLOW( a, b )         ( ( a ) > ( heapSIZE_MAX - ( b ) ) )\n\n/* MSB of the xBlockSize member of an BlockLink_t structure is used to track\n * the allocation status of a block.  When MSB of the xBlockSize member of\n * an BlockLink_t structure is set then the block belongs to the application.\n * When the bit is free the block is still part of the free heap space. */\n#define heapBLOCK_ALLOCATED_BITMASK    ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 ) )\n#define heapBLOCK_SIZE_IS_VALID( xBlockSize )    ( ( ( xBlockSize ) & heapBLOCK_ALLOCATED_BITMASK ) == 0 )\n#define heapBLOCK_IS_ALLOCATED( pxBlock )        ( ( ( pxBlock->xBlockSize ) & heapBLOCK_ALLOCATED_BITMASK ) != 0 )\n#define heapALLOCATE_BLOCK( pxBlock )            ( ( pxBlock->xBlockSize ) |= heapBLOCK_ALLOCATED_BITMASK )\n#define heapFREE_BLOCK( pxBlock )                ( ( pxBlock->xBlockSize ) &= ~heapBLOCK_ALLOCATED_BITMASK )\n\n/*-----------------------------------------------------------*/\n\n/* Allocate the memory for the heap. */\n#if ( configAPPLICATION_ALLOCATED_HEAP == 1 )\n\n/* The application writer has already defined the array used for the RTOS\n* heap - probably so it can be placed in a special segment or address. */\n    extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];\n#else\n    PRIVILEGED_DATA static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];\n#endif /* configAPPLICATION_ALLOCATED_HEAP */\n\n/* Define the linked list structure.  This is used to link free blocks in order\n * of their memory address. */\ntypedef struct A_BLOCK_LINK\n{\n    struct A_BLOCK_LINK * pxNextFreeBlock; /*<< The next free block in the list. */\n    size_t xBlockSize;                     /*<< The size of the free block. */\n} BlockLink_t;\n\n/*-----------------------------------------------------------*/\n\n/*\n * Inserts a block of memory that is being freed into the correct position in\n * the list of free memory blocks.  The block being freed will be merged with\n * the block in front it and/or the block behind it if the memory blocks are\n * adjacent to each other.\n */\nstatic void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) PRIVILEGED_FUNCTION;\n\n/*\n * Called automatically to setup the required heap structures the first time\n * pvPortMalloc() is called.\n */\nstatic void prvHeapInit( void ) PRIVILEGED_FUNCTION;\n\n/*-----------------------------------------------------------*/\n\n/* The size of the structure placed at the beginning of each allocated memory\n * block must by correctly byte aligned. */\nstatic const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( portBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) portBYTE_ALIGNMENT_MASK );\n\n/* Create a couple of list links to mark the start and end of the list. */\nPRIVILEGED_DATA static BlockLink_t xStart;\nPRIVILEGED_DATA static BlockLink_t * pxEnd = NULL;\n\n/* Keeps track of the number of calls to allocate and free memory as well as the\n * number of free bytes remaining, but says nothing about fragmentation. */\nPRIVILEGED_DATA static size_t xFreeBytesRemaining = 0U;\nPRIVILEGED_DATA static size_t xMinimumEverFreeBytesRemaining = 0U;\nPRIVILEGED_DATA static size_t xNumberOfSuccessfulAllocations = 0;\nPRIVILEGED_DATA static size_t xNumberOfSuccessfulFrees = 0;\n\n/*-----------------------------------------------------------*/\n\nvoid * pvPortMalloc( size_t xWantedSize )\n{\n    BlockLink_t * pxBlock;\n    BlockLink_t * pxPreviousBlock;\n    BlockLink_t * pxNewBlockLink;\n    void * pvReturn = NULL;\n    size_t xAdditionalRequiredSize;\n\n    vTaskSuspendAll();\n    {\n        /* If this is the first call to malloc then the heap will require\n         * initialisation to setup the list of free blocks. */\n        if( pxEnd == NULL )\n        {\n            prvHeapInit();\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n\n        if( xWantedSize > 0 )\n        {\n            /* The wanted size must be increased so it can contain a BlockLink_t\n             * structure in addition to the requested amount of bytes. Some\n             * additional increment may also be needed for alignment. */\n            xAdditionalRequiredSize = xHeapStructSize + portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK );\n\n            if( heapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 )\n            {\n                xWantedSize += xAdditionalRequiredSize;\n            }\n            else\n            {\n                xWantedSize = 0;\n            }\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n\n        /* Check the block size we are trying to allocate is not so large that the\n         * top bit is set.  The top bit of the block size member of the BlockLink_t\n         * structure is used to determine who owns the block - the application or\n         * the kernel, so it must be free. */\n        if( heapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 )\n        {\n            if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )\n            {\n                /* Traverse the list from the start (lowest address) block until\n                 * one of adequate size is found. */\n                pxPreviousBlock = &xStart;\n                pxBlock = xStart.pxNextFreeBlock;\n\n                while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )\n                {\n                    pxPreviousBlock = pxBlock;\n                    pxBlock = pxBlock->pxNextFreeBlock;\n                }\n\n                /* If the end marker was reached then a block of adequate size\n                 * was not found. */\n                if( pxBlock != pxEnd )\n                {\n                    /* Return the memory space pointed to - jumping over the\n                     * BlockLink_t structure at its start. */\n                    pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );\n\n                    /* This block is being returned for use so must be taken out\n                     * of the list of free blocks. */\n                    pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;\n\n                    /* If the block is larger than required it can be split into\n                     * two. */\n                    if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )\n                    {\n                        /* This block is to be split into two.  Create a new\n                         * block following the number of bytes requested. The void\n                         * cast is used to prevent byte alignment warnings from the\n                         * compiler. */\n                        pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );\n                        configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 );\n\n                        /* Calculate the sizes of two blocks split from the\n                         * single block. */\n                        pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;\n                        pxBlock->xBlockSize = xWantedSize;\n\n                        /* Insert the new block into the list of free blocks. */\n                        prvInsertBlockIntoFreeList( pxNewBlockLink );\n                    }\n                    else\n                    {\n                        mtCOVERAGE_TEST_MARKER();\n                    }\n\n                    xFreeBytesRemaining -= pxBlock->xBlockSize;\n\n                    if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )\n                    {\n                        xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;\n                    }\n                    else\n                    {\n                        mtCOVERAGE_TEST_MARKER();\n                    }\n\n                    /* The block is being returned - it is allocated and owned\n                     * by the application and has no \"next\" block. */\n                    heapALLOCATE_BLOCK( pxBlock );\n                    pxBlock->pxNextFreeBlock = NULL;\n                    xNumberOfSuccessfulAllocations++;\n                }\n                else\n                {\n                    mtCOVERAGE_TEST_MARKER();\n                }\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n\n        traceMALLOC( pvReturn, xWantedSize );\n    }\n    ( void ) xTaskResumeAll();\n\n    #if ( configUSE_MALLOC_FAILED_HOOK == 1 )\n    {\n        if( pvReturn == NULL )\n        {\n            vApplicationMallocFailedHook();\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n    }\n    #endif /* if ( configUSE_MALLOC_FAILED_HOOK == 1 ) */\n\n    configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 );\n    return pvReturn;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortFree( void * pv )\n{\n    uint8_t * puc = ( uint8_t * ) pv;\n    BlockLink_t * pxLink;\n\n    if( pv != NULL )\n    {\n        /* The memory being freed will have an BlockLink_t structure immediately\n         * before it. */\n        puc -= xHeapStructSize;\n\n        /* This casting is to keep the compiler from issuing warnings. */\n        pxLink = ( void * ) puc;\n\n        configASSERT( heapBLOCK_IS_ALLOCATED( pxLink ) != 0 );\n        configASSERT( pxLink->pxNextFreeBlock == NULL );\n\n        if( heapBLOCK_IS_ALLOCATED( pxLink ) != 0 )\n        {\n            if( pxLink->pxNextFreeBlock == NULL )\n            {\n                /* The block is being returned to the heap - it is no longer\n                 * allocated. */\n                heapFREE_BLOCK( pxLink );\n                #if ( configHEAP_CLEAR_MEMORY_ON_FREE == 1 )\n                {\n                    ( void ) memset( puc + xHeapStructSize, 0, pxLink->xBlockSize - xHeapStructSize );\n                }\n                #endif\n\n                vTaskSuspendAll();\n                {\n                    /* Add this block to the list of free blocks. */\n                    xFreeBytesRemaining += pxLink->xBlockSize;\n                    traceFREE( pv, pxLink->xBlockSize );\n                    prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );\n                    xNumberOfSuccessfulFrees++;\n                }\n                ( void ) xTaskResumeAll();\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n    }\n}\n/*-----------------------------------------------------------*/\n\nsize_t xPortGetFreeHeapSize( void )\n{\n    return xFreeBytesRemaining;\n}\n/*-----------------------------------------------------------*/\n\nsize_t xPortGetMinimumEverFreeHeapSize( void )\n{\n    return xMinimumEverFreeBytesRemaining;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortInitialiseBlocks( void )\n{\n    /* This just exists to keep the linker quiet. */\n}\n/*-----------------------------------------------------------*/\n\nvoid * pvPortCalloc( size_t xNum,\n                     size_t xSize )\n{\n    void * pv = NULL;\n\n    if( heapMULTIPLY_WILL_OVERFLOW( xNum, xSize ) == 0 )\n    {\n        pv = pvPortMalloc( xNum * xSize );\n\n        if( pv != NULL )\n        {\n            ( void ) memset( pv, 0, xNum * xSize );\n        }\n    }\n\n    return pv;\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvHeapInit( void ) /* PRIVILEGED_FUNCTION */\n{\n    BlockLink_t * pxFirstFreeBlock;\n    uint8_t * pucAlignedHeap;\n    portPOINTER_SIZE_TYPE uxAddress;\n    size_t xTotalHeapSize = configTOTAL_HEAP_SIZE;\n\n    /* Ensure the heap starts on a correctly aligned boundary. */\n    uxAddress = ( portPOINTER_SIZE_TYPE ) ucHeap;\n\n    if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 )\n    {\n        uxAddress += ( portBYTE_ALIGNMENT - 1 );\n        uxAddress &= ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK );\n        xTotalHeapSize -= uxAddress - ( portPOINTER_SIZE_TYPE ) ucHeap;\n    }\n\n    pucAlignedHeap = ( uint8_t * ) uxAddress;\n\n    /* xStart is used to hold a pointer to the first item in the list of free\n     * blocks.  The void cast is used to prevent compiler warnings. */\n    xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;\n    xStart.xBlockSize = ( size_t ) 0;\n\n    /* pxEnd is used to mark the end of the list of free blocks and is inserted\n     * at the end of the heap space. */\n    uxAddress = ( ( portPOINTER_SIZE_TYPE ) pucAlignedHeap ) + xTotalHeapSize;\n    uxAddress -= xHeapStructSize;\n    uxAddress &= ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK );\n    pxEnd = ( BlockLink_t * ) uxAddress;\n    pxEnd->xBlockSize = 0;\n    pxEnd->pxNextFreeBlock = NULL;\n\n    /* To start with there is a single free block that is sized to take up the\n     * entire heap space, minus the space taken by pxEnd. */\n    pxFirstFreeBlock = ( BlockLink_t * ) pucAlignedHeap;\n    pxFirstFreeBlock->xBlockSize = ( size_t ) ( uxAddress - ( portPOINTER_SIZE_TYPE ) pxFirstFreeBlock );\n    pxFirstFreeBlock->pxNextFreeBlock = pxEnd;\n\n    /* Only one block exists - and it covers the entire usable heap space. */\n    xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;\n    xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) /* PRIVILEGED_FUNCTION */\n{\n    BlockLink_t * pxIterator;\n    uint8_t * puc;\n\n    /* Iterate through the list until a block is found that has a higher address\n     * than the block being inserted. */\n    for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )\n    {\n        /* Nothing to do here, just iterate to the right position. */\n    }\n\n    /* Do the block being inserted, and the block it is being inserted after\n     * make a contiguous block of memory? */\n    puc = ( uint8_t * ) pxIterator;\n\n    if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )\n    {\n        pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;\n        pxBlockToInsert = pxIterator;\n    }\n    else\n    {\n        mtCOVERAGE_TEST_MARKER();\n    }\n\n    /* Do the block being inserted, and the block it is being inserted before\n     * make a contiguous block of memory? */\n    puc = ( uint8_t * ) pxBlockToInsert;\n\n    if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )\n    {\n        if( pxIterator->pxNextFreeBlock != pxEnd )\n        {\n            /* Form one big block from the two blocks. */\n            pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;\n            pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;\n        }\n        else\n        {\n            pxBlockToInsert->pxNextFreeBlock = pxEnd;\n        }\n    }\n    else\n    {\n        pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;\n    }\n\n    /* If the block being inserted plugged a gab, so was merged with the block\n     * before and the block after, then it's pxNextFreeBlock pointer will have\n     * already been set, and should not be set here as that would make it point\n     * to itself. */\n    if( pxIterator != pxBlockToInsert )\n    {\n        pxIterator->pxNextFreeBlock = pxBlockToInsert;\n    }\n    else\n    {\n        mtCOVERAGE_TEST_MARKER();\n    }\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortGetHeapStats( HeapStats_t * pxHeapStats )\n{\n    BlockLink_t * pxBlock;\n    size_t xBlocks = 0, xMaxSize = 0, xMinSize = portMAX_DELAY; /* portMAX_DELAY used as a portable way of getting the maximum value. */\n\n    vTaskSuspendAll();\n    {\n        pxBlock = xStart.pxNextFreeBlock;\n\n        /* pxBlock will be NULL if the heap has not been initialised.  The heap\n         * is initialised automatically when the first allocation is made. */\n        if( pxBlock != NULL )\n        {\n            while( pxBlock != pxEnd )\n            {\n                /* Increment the number of blocks and record the largest block seen\n                 * so far. */\n                xBlocks++;\n\n                if( pxBlock->xBlockSize > xMaxSize )\n                {\n                    xMaxSize = pxBlock->xBlockSize;\n                }\n\n                if( pxBlock->xBlockSize < xMinSize )\n                {\n                    xMinSize = pxBlock->xBlockSize;\n                }\n\n                /* Move to the next block in the chain until the last block is\n                 * reached. */\n                pxBlock = pxBlock->pxNextFreeBlock;\n            }\n        }\n    }\n    ( void ) xTaskResumeAll();\n\n    pxHeapStats->xSizeOfLargestFreeBlockInBytes = xMaxSize;\n    pxHeapStats->xSizeOfSmallestFreeBlockInBytes = xMinSize;\n    pxHeapStats->xNumberOfFreeBlocks = xBlocks;\n\n    taskENTER_CRITICAL();\n    {\n        pxHeapStats->xAvailableHeapSpaceInBytes = xFreeBytesRemaining;\n        pxHeapStats->xNumberOfSuccessfulAllocations = xNumberOfSuccessfulAllocations;\n        pxHeapStats->xNumberOfSuccessfulFrees = xNumberOfSuccessfulFrees;\n        pxHeapStats->xMinimumEverFreeBytesRemaining = xMinimumEverFreeBytesRemaining;\n    }\n    taskEXIT_CRITICAL();\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/MemMang/heap_5.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/*\n * A sample implementation of pvPortMalloc() that allows the heap to be defined\n * across multiple non-contigous blocks and combines (coalescences) adjacent\n * memory blocks as they are freed.\n *\n * See heap_1.c, heap_2.c, heap_3.c and heap_4.c for alternative\n * implementations, and the memory management pages of https://www.FreeRTOS.org\n * for more information.\n *\n * Usage notes:\n *\n * vPortDefineHeapRegions() ***must*** be called before pvPortMalloc().\n * pvPortMalloc() will be called if any task objects (tasks, queues, event\n * groups, etc.) are created, therefore vPortDefineHeapRegions() ***must*** be\n * called before any other objects are defined.\n *\n * vPortDefineHeapRegions() takes a single parameter.  The parameter is an array\n * of HeapRegion_t structures.  HeapRegion_t is defined in portable.h as\n *\n * typedef struct HeapRegion\n * {\n *  uint8_t *pucStartAddress; << Start address of a block of memory that will be part of the heap.\n *  size_t xSizeInBytes;      << Size of the block of memory.\n * } HeapRegion_t;\n *\n * The array is terminated using a NULL zero sized region definition, and the\n * memory regions defined in the array ***must*** appear in address order from\n * low address to high address.  So the following is a valid example of how\n * to use the function.\n *\n * HeapRegion_t xHeapRegions[] =\n * {\n *  { ( uint8_t * ) 0x80000000UL, 0x10000 }, << Defines a block of 0x10000 bytes starting at address 0x80000000\n *  { ( uint8_t * ) 0x90000000UL, 0xa0000 }, << Defines a block of 0xa0000 bytes starting at address of 0x90000000\n *  { NULL, 0 }                << Terminates the array.\n * };\n *\n * vPortDefineHeapRegions( xHeapRegions ); << Pass the array into vPortDefineHeapRegions().\n *\n * Note 0x80000000 is the lower address so appears in the array first.\n *\n */\n#include <stdlib.h>\n#include <string.h>\n\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\n * all the API functions to use the MPU wrappers.  That should only be done when\n * task.h is included from an application file. */\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n#if ( configSUPPORT_DYNAMIC_ALLOCATION == 0 )\n    #error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0\n#endif\n\n#ifndef configHEAP_CLEAR_MEMORY_ON_FREE\n    #define configHEAP_CLEAR_MEMORY_ON_FREE    0\n#endif\n\n/* Block sizes must not get too small. */\n#define heapMINIMUM_BLOCK_SIZE    ( ( size_t ) ( xHeapStructSize << 1 ) )\n\n/* Assumes 8bit bytes! */\n#define heapBITS_PER_BYTE         ( ( size_t ) 8 )\n\n/* Max value that fits in a size_t type. */\n#define heapSIZE_MAX              ( ~( ( size_t ) 0 ) )\n\n/* Check if multiplying a and b will result in overflow. */\n#define heapMULTIPLY_WILL_OVERFLOW( a, b )    ( ( ( a ) > 0 ) && ( ( b ) > ( heapSIZE_MAX / ( a ) ) ) )\n\n/* Check if adding a and b will result in overflow. */\n#define heapADD_WILL_OVERFLOW( a, b )         ( ( a ) > ( heapSIZE_MAX - ( b ) ) )\n\n/* MSB of the xBlockSize member of an BlockLink_t structure is used to track\n * the allocation status of a block.  When MSB of the xBlockSize member of\n * an BlockLink_t structure is set then the block belongs to the application.\n * When the bit is free the block is still part of the free heap space. */\n#define heapBLOCK_ALLOCATED_BITMASK    ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 ) )\n#define heapBLOCK_SIZE_IS_VALID( xBlockSize )    ( ( ( xBlockSize ) & heapBLOCK_ALLOCATED_BITMASK ) == 0 )\n#define heapBLOCK_IS_ALLOCATED( pxBlock )        ( ( ( pxBlock->xBlockSize ) & heapBLOCK_ALLOCATED_BITMASK ) != 0 )\n#define heapALLOCATE_BLOCK( pxBlock )            ( ( pxBlock->xBlockSize ) |= heapBLOCK_ALLOCATED_BITMASK )\n#define heapFREE_BLOCK( pxBlock )                ( ( pxBlock->xBlockSize ) &= ~heapBLOCK_ALLOCATED_BITMASK )\n\n/*-----------------------------------------------------------*/\n\n/* Define the linked list structure.  This is used to link free blocks in order\n * of their memory address. */\ntypedef struct A_BLOCK_LINK\n{\n    struct A_BLOCK_LINK * pxNextFreeBlock; /*<< The next free block in the list. */\n    size_t xBlockSize;                     /*<< The size of the free block. */\n} BlockLink_t;\n\n/*-----------------------------------------------------------*/\n\n/*\n * Inserts a block of memory that is being freed into the correct position in\n * the list of free memory blocks.  The block being freed will be merged with\n * the block in front it and/or the block behind it if the memory blocks are\n * adjacent to each other.\n */\nstatic void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert );\n\n/*-----------------------------------------------------------*/\n\n/* The size of the structure placed at the beginning of each allocated memory\n * block must by correctly byte aligned. */\nstatic const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( portBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) portBYTE_ALIGNMENT_MASK );\n\n/* Create a couple of list links to mark the start and end of the list. */\nstatic BlockLink_t xStart;\nstatic BlockLink_t * pxEnd = NULL;\n\n/* Keeps track of the number of calls to allocate and free memory as well as the\n * number of free bytes remaining, but says nothing about fragmentation. */\nstatic size_t xFreeBytesRemaining = 0U;\nstatic size_t xMinimumEverFreeBytesRemaining = 0U;\nstatic size_t xNumberOfSuccessfulAllocations = 0;\nstatic size_t xNumberOfSuccessfulFrees = 0;\n\n/*-----------------------------------------------------------*/\n\nvoid * pvPortMalloc( size_t xWantedSize )\n{\n    BlockLink_t * pxBlock;\n    BlockLink_t * pxPreviousBlock;\n    BlockLink_t * pxNewBlockLink;\n    void * pvReturn = NULL;\n    size_t xAdditionalRequiredSize;\n\n    /* The heap must be initialised before the first call to\n     * prvPortMalloc(). */\n    configASSERT( pxEnd );\n\n    vTaskSuspendAll();\n    {\n        if( xWantedSize > 0 )\n        {\n            /* The wanted size must be increased so it can contain a BlockLink_t\n             * structure in addition to the requested amount of bytes. Some\n             * additional increment may also be needed for alignment. */\n            xAdditionalRequiredSize = xHeapStructSize + portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK );\n\n            if( heapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 )\n            {\n                xWantedSize += xAdditionalRequiredSize;\n            }\n            else\n            {\n                xWantedSize = 0;\n            }\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n\n        /* Check the block size we are trying to allocate is not so large that the\n         * top bit is set.  The top bit of the block size member of the BlockLink_t\n         * structure is used to determine who owns the block - the application or\n         * the kernel, so it must be free. */\n        if( heapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 )\n        {\n            if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )\n            {\n                /* Traverse the list from the start (lowest address) block until\n                 * one of adequate size is found. */\n                pxPreviousBlock = &xStart;\n                pxBlock = xStart.pxNextFreeBlock;\n\n                while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )\n                {\n                    pxPreviousBlock = pxBlock;\n                    pxBlock = pxBlock->pxNextFreeBlock;\n                }\n\n                /* If the end marker was reached then a block of adequate size\n                 * was not found. */\n                if( pxBlock != pxEnd )\n                {\n                    /* Return the memory space pointed to - jumping over the\n                     * BlockLink_t structure at its start. */\n                    pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );\n\n                    /* This block is being returned for use so must be taken out\n                     * of the list of free blocks. */\n                    pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;\n\n                    /* If the block is larger than required it can be split into\n                     * two. */\n                    if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )\n                    {\n                        /* This block is to be split into two.  Create a new\n                         * block following the number of bytes requested. The void\n                         * cast is used to prevent byte alignment warnings from the\n                         * compiler. */\n                        pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );\n\n                        /* Calculate the sizes of two blocks split from the\n                         * single block. */\n                        pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;\n                        pxBlock->xBlockSize = xWantedSize;\n\n                        /* Insert the new block into the list of free blocks. */\n                        prvInsertBlockIntoFreeList( ( pxNewBlockLink ) );\n                    }\n                    else\n                    {\n                        mtCOVERAGE_TEST_MARKER();\n                    }\n\n                    xFreeBytesRemaining -= pxBlock->xBlockSize;\n\n                    if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )\n                    {\n                        xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;\n                    }\n                    else\n                    {\n                        mtCOVERAGE_TEST_MARKER();\n                    }\n\n                    /* The block is being returned - it is allocated and owned\n                     * by the application and has no \"next\" block. */\n                    heapALLOCATE_BLOCK( pxBlock );\n                    pxBlock->pxNextFreeBlock = NULL;\n                    xNumberOfSuccessfulAllocations++;\n                }\n                else\n                {\n                    mtCOVERAGE_TEST_MARKER();\n                }\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n\n        traceMALLOC( pvReturn, xWantedSize );\n    }\n    ( void ) xTaskResumeAll();\n\n    #if ( configUSE_MALLOC_FAILED_HOOK == 1 )\n    {\n        if( pvReturn == NULL )\n        {\n            vApplicationMallocFailedHook();\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n    }\n    #endif /* if ( configUSE_MALLOC_FAILED_HOOK == 1 ) */\n\n    return pvReturn;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortFree( void * pv )\n{\n    uint8_t * puc = ( uint8_t * ) pv;\n    BlockLink_t * pxLink;\n\n    if( pv != NULL )\n    {\n        /* The memory being freed will have an BlockLink_t structure immediately\n         * before it. */\n        puc -= xHeapStructSize;\n\n        /* This casting is to keep the compiler from issuing warnings. */\n        pxLink = ( void * ) puc;\n\n        configASSERT( heapBLOCK_IS_ALLOCATED( pxLink ) != 0 );\n        configASSERT( pxLink->pxNextFreeBlock == NULL );\n\n        if( heapBLOCK_IS_ALLOCATED( pxLink ) != 0 )\n        {\n            if( pxLink->pxNextFreeBlock == NULL )\n            {\n                /* The block is being returned to the heap - it is no longer\n                 * allocated. */\n                heapFREE_BLOCK( pxLink );\n                #if ( configHEAP_CLEAR_MEMORY_ON_FREE == 1 )\n                {\n                    ( void ) memset( puc + xHeapStructSize, 0, pxLink->xBlockSize - xHeapStructSize );\n                }\n                #endif\n\n                vTaskSuspendAll();\n                {\n                    /* Add this block to the list of free blocks. */\n                    xFreeBytesRemaining += pxLink->xBlockSize;\n                    traceFREE( pv, pxLink->xBlockSize );\n                    prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );\n                    xNumberOfSuccessfulFrees++;\n                }\n                ( void ) xTaskResumeAll();\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n    }\n}\n/*-----------------------------------------------------------*/\n\nsize_t xPortGetFreeHeapSize( void )\n{\n    return xFreeBytesRemaining;\n}\n/*-----------------------------------------------------------*/\n\nsize_t xPortGetMinimumEverFreeHeapSize( void )\n{\n    return xMinimumEverFreeBytesRemaining;\n}\n/*-----------------------------------------------------------*/\n\nvoid * pvPortCalloc( size_t xNum,\n                     size_t xSize )\n{\n    void * pv = NULL;\n\n    if( heapMULTIPLY_WILL_OVERFLOW( xNum, xSize ) == 0 )\n    {\n        pv = pvPortMalloc( xNum * xSize );\n\n        if( pv != NULL )\n        {\n            ( void ) memset( pv, 0, xNum * xSize );\n        }\n    }\n\n    return pv;\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert )\n{\n    BlockLink_t * pxIterator;\n    uint8_t * puc;\n\n    /* Iterate through the list until a block is found that has a higher address\n     * than the block being inserted. */\n    for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )\n    {\n        /* Nothing to do here, just iterate to the right position. */\n    }\n\n    /* Do the block being inserted, and the block it is being inserted after\n     * make a contiguous block of memory? */\n    puc = ( uint8_t * ) pxIterator;\n\n    if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )\n    {\n        pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;\n        pxBlockToInsert = pxIterator;\n    }\n    else\n    {\n        mtCOVERAGE_TEST_MARKER();\n    }\n\n    /* Do the block being inserted, and the block it is being inserted before\n     * make a contiguous block of memory? */\n    puc = ( uint8_t * ) pxBlockToInsert;\n\n    if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )\n    {\n        if( pxIterator->pxNextFreeBlock != pxEnd )\n        {\n            /* Form one big block from the two blocks. */\n            pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;\n            pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;\n        }\n        else\n        {\n            pxBlockToInsert->pxNextFreeBlock = pxEnd;\n        }\n    }\n    else\n    {\n        pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;\n    }\n\n    /* If the block being inserted plugged a gab, so was merged with the block\n     * before and the block after, then it's pxNextFreeBlock pointer will have\n     * already been set, and should not be set here as that would make it point\n     * to itself. */\n    if( pxIterator != pxBlockToInsert )\n    {\n        pxIterator->pxNextFreeBlock = pxBlockToInsert;\n    }\n    else\n    {\n        mtCOVERAGE_TEST_MARKER();\n    }\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions )\n{\n    BlockLink_t * pxFirstFreeBlockInRegion = NULL;\n    BlockLink_t * pxPreviousFreeBlock;\n    portPOINTER_SIZE_TYPE xAlignedHeap;\n    size_t xTotalRegionSize, xTotalHeapSize = 0;\n    BaseType_t xDefinedRegions = 0;\n    portPOINTER_SIZE_TYPE xAddress;\n    const HeapRegion_t * pxHeapRegion;\n\n    /* Can only call once! */\n    configASSERT( pxEnd == NULL );\n\n    pxHeapRegion = &( pxHeapRegions[ xDefinedRegions ] );\n\n    while( pxHeapRegion->xSizeInBytes > 0 )\n    {\n        xTotalRegionSize = pxHeapRegion->xSizeInBytes;\n\n        /* Ensure the heap region starts on a correctly aligned boundary. */\n        xAddress = ( portPOINTER_SIZE_TYPE ) pxHeapRegion->pucStartAddress;\n\n        if( ( xAddress & portBYTE_ALIGNMENT_MASK ) != 0 )\n        {\n            xAddress += ( portBYTE_ALIGNMENT - 1 );\n            xAddress &= ~portBYTE_ALIGNMENT_MASK;\n\n            /* Adjust the size for the bytes lost to alignment. */\n            xTotalRegionSize -= ( size_t ) ( xAddress - ( portPOINTER_SIZE_TYPE ) pxHeapRegion->pucStartAddress );\n        }\n\n        xAlignedHeap = xAddress;\n\n        /* Set xStart if it has not already been set. */\n        if( xDefinedRegions == 0 )\n        {\n            /* xStart is used to hold a pointer to the first item in the list of\n             *  free blocks.  The void cast is used to prevent compiler warnings. */\n            xStart.pxNextFreeBlock = ( BlockLink_t * ) xAlignedHeap;\n            xStart.xBlockSize = ( size_t ) 0;\n        }\n        else\n        {\n            /* Should only get here if one region has already been added to the\n             * heap. */\n            configASSERT( pxEnd != NULL );\n\n            /* Check blocks are passed in with increasing start addresses. */\n            configASSERT( xAddress > ( size_t ) pxEnd );\n        }\n\n        /* Remember the location of the end marker in the previous region, if\n         * any. */\n        pxPreviousFreeBlock = pxEnd;\n\n        /* pxEnd is used to mark the end of the list of free blocks and is\n         * inserted at the end of the region space. */\n        xAddress = xAlignedHeap + xTotalRegionSize;\n        xAddress -= xHeapStructSize;\n        xAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );\n        pxEnd = ( BlockLink_t * ) xAddress;\n        pxEnd->xBlockSize = 0;\n        pxEnd->pxNextFreeBlock = NULL;\n\n        /* To start with there is a single free block in this region that is\n         * sized to take up the entire heap region minus the space taken by the\n         * free block structure. */\n        pxFirstFreeBlockInRegion = ( BlockLink_t * ) xAlignedHeap;\n        pxFirstFreeBlockInRegion->xBlockSize = ( size_t ) ( xAddress - ( portPOINTER_SIZE_TYPE ) pxFirstFreeBlockInRegion );\n        pxFirstFreeBlockInRegion->pxNextFreeBlock = pxEnd;\n\n        /* If this is not the first region that makes up the entire heap space\n         * then link the previous region to this region. */\n        if( pxPreviousFreeBlock != NULL )\n        {\n            pxPreviousFreeBlock->pxNextFreeBlock = pxFirstFreeBlockInRegion;\n        }\n\n        xTotalHeapSize += pxFirstFreeBlockInRegion->xBlockSize;\n\n        /* Move onto the next HeapRegion_t structure. */\n        xDefinedRegions++;\n        pxHeapRegion = &( pxHeapRegions[ xDefinedRegions ] );\n    }\n\n    xMinimumEverFreeBytesRemaining = xTotalHeapSize;\n    xFreeBytesRemaining = xTotalHeapSize;\n\n    /* Check something was actually defined before it is accessed. */\n    configASSERT( xTotalHeapSize );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortGetHeapStats( HeapStats_t * pxHeapStats )\n{\n    BlockLink_t * pxBlock;\n    size_t xBlocks = 0, xMaxSize = 0, xMinSize = portMAX_DELAY; /* portMAX_DELAY used as a portable way of getting the maximum value. */\n\n    vTaskSuspendAll();\n    {\n        pxBlock = xStart.pxNextFreeBlock;\n\n        /* pxBlock will be NULL if the heap has not been initialised.  The heap\n         * is initialised automatically when the first allocation is made. */\n        if( pxBlock != NULL )\n        {\n            while( pxBlock != pxEnd )\n            {\n                /* Increment the number of blocks and record the largest block seen\n                 * so far. */\n                xBlocks++;\n\n                if( pxBlock->xBlockSize > xMaxSize )\n                {\n                    xMaxSize = pxBlock->xBlockSize;\n                }\n\n                /* Heap five will have a zero sized block at the end of each\n                 * each region - the block is only used to link to the next\n                 * heap region so it not a real block. */\n                if( pxBlock->xBlockSize != 0 )\n                {\n                    if( pxBlock->xBlockSize < xMinSize )\n                    {\n                        xMinSize = pxBlock->xBlockSize;\n                    }\n                }\n\n                /* Move to the next block in the chain until the last block is\n                 * reached. */\n                pxBlock = pxBlock->pxNextFreeBlock;\n            }\n        }\n    }\n    ( void ) xTaskResumeAll();\n\n    pxHeapStats->xSizeOfLargestFreeBlockInBytes = xMaxSize;\n    pxHeapStats->xSizeOfSmallestFreeBlockInBytes = xMinSize;\n    pxHeapStats->xNumberOfFreeBlocks = xBlocks;\n\n    taskENTER_CRITICAL();\n    {\n        pxHeapStats->xAvailableHeapSpaceInBytes = xFreeBytesRemaining;\n        pxHeapStats->xNumberOfSuccessfulAllocations = xNumberOfSuccessfulAllocations;\n        pxHeapStats->xNumberOfSuccessfulFrees = xNumberOfSuccessfulFrees;\n        pxHeapStats->xMinimumEverFreeBytesRemaining = xMinimumEverFreeBytesRemaining;\n    }\n    taskEXIT_CRITICAL();\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/RVDS/ARM7_LPC21xx/port.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n\n/* Standard includes. */\n#include <stdlib.h>\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n/* Constants required to setup the initial task context. */\n#define portINITIAL_SPSR\t\t\t\t( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */\n#define portTHUMB_MODE_BIT\t\t\t\t( ( StackType_t ) 0x20 )\n#define portINSTRUCTION_SIZE\t\t\t( ( StackType_t ) 4 )\n#define portNO_CRITICAL_SECTION_NESTING\t( ( StackType_t ) 0 )\n\n/* Constants required to setup the tick ISR. */\n#define portENABLE_TIMER\t\t\t( ( uint8_t ) 0x01 )\n#define portPRESCALE_VALUE\t\t\t0x00\n#define portINTERRUPT_ON_MATCH\t\t( ( uint32_t ) 0x01 )\n#define portRESET_COUNT_ON_MATCH\t( ( uint32_t ) 0x02 )\n\n/* Constants required to setup the VIC for the tick ISR. */\n#define portTIMER_VIC_CHANNEL\t\t( ( uint32_t ) 0x0004 )\n#define portTIMER_VIC_CHANNEL_BIT\t( ( uint32_t ) 0x0010 )\n#define portTIMER_VIC_ENABLE\t\t( ( uint32_t ) 0x0020 )\n\n/* Constants required to handle interrupts. */\n#define portTIMER_MATCH_ISR_BIT\t\t( ( uint8_t ) 0x01 )\n#define portCLEAR_VIC_INTERRUPT\t\t( ( uint32_t ) 0 )\n\n/*-----------------------------------------------------------*/\n\n/* The code generated by the Keil compiler does not maintain separate\nstack and frame pointers. The portENTER_CRITICAL macro cannot therefore\nuse the stack as per other ports.  Instead a variable is used to keep\ntrack of the critical section nesting.  This variable has to be stored\nas part of the task context and must be initialised to a non zero value. */\n\n#define portNO_CRITICAL_NESTING\t\t( ( uint32_t ) 0 )\nvolatile uint32_t ulCriticalNesting = 9999UL;\n\n/*-----------------------------------------------------------*/\n\n/* Setup the timer to generate the tick interrupts. */\nstatic void prvSetupTimerInterrupt( void );\n\n/* \n * The scheduler can only be started from ARM mode, so \n * vPortStartFirstSTask() is defined in portISR.c. \n */\nextern __asm void vPortStartFirstTask( void );\n\n/*-----------------------------------------------------------*/\n\n/* \n * See header file for description. \n */\nStackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )\n{\nStackType_t *pxOriginalTOS;\n\n\t/* Setup the initial stack of the task.  The stack is set exactly as \n\texpected by the portRESTORE_CONTEXT() macro.\n\n\tRemember where the top of the (simulated) stack is before we place \n\tanything on it. */\n\tpxOriginalTOS = pxTopOfStack;\n\t\n\t/* To ensure asserts in tasks.c don't fail, although in this case the assert\n\tis not really required. */\n\tpxTopOfStack--;\n\n\t/* First on the stack is the return address - which in this case is the\n\tstart of the task.  The offset is added to make the return address appear\n\tas it would within an IRQ ISR. */\n\t*pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;\t\t\n\tpxTopOfStack--;\n\n\t*pxTopOfStack = ( StackType_t ) 0xaaaaaaaa;\t/* R14 */\n\tpxTopOfStack--;\t\n\t*pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x12121212;\t/* R12 */\n\tpxTopOfStack--;\t\n\t*pxTopOfStack = ( StackType_t ) 0x11111111;\t/* R11 */\n\tpxTopOfStack--;\t\n\t*pxTopOfStack = ( StackType_t ) 0x10101010;\t/* R10 */\n\tpxTopOfStack--;\t\n\t*pxTopOfStack = ( StackType_t ) 0x09090909;\t/* R9 */\n\tpxTopOfStack--;\t\n\t*pxTopOfStack = ( StackType_t ) 0x08080808;\t/* R8 */\n\tpxTopOfStack--;\t\n\t*pxTopOfStack = ( StackType_t ) 0x07070707;\t/* R7 */\n\tpxTopOfStack--;\t\n\t*pxTopOfStack = ( StackType_t ) 0x06060606;\t/* R6 */\n\tpxTopOfStack--;\t\n\t*pxTopOfStack = ( StackType_t ) 0x05050505;\t/* R5 */\n\tpxTopOfStack--;\t\n\t*pxTopOfStack = ( StackType_t ) 0x04040404;\t/* R4 */\n\tpxTopOfStack--;\t\n\t*pxTopOfStack = ( StackType_t ) 0x03030303;\t/* R3 */\n\tpxTopOfStack--;\t\n\t*pxTopOfStack = ( StackType_t ) 0x02020202;\t/* R2 */\n\tpxTopOfStack--;\t\n\t*pxTopOfStack = ( StackType_t ) 0x01010101;\t/* R1 */\n\tpxTopOfStack--;\t\n\t*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\n\tpxTopOfStack--;\n\n\t/* The last thing onto the stack is the status register, which is set for\n\tsystem mode, with interrupts enabled. */\n\t*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;\n\n\tif( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00UL )\n\t{\n\t\t/* We want the task to start in thumb mode. */\n\t\t*pxTopOfStack |= portTHUMB_MODE_BIT;\n\t}\n\n\tpxTopOfStack--;\n\n\t/* The code generated by the Keil compiler does not maintain separate\n\tstack and frame pointers. The portENTER_CRITICAL macro cannot therefore\n\tuse the stack as per other ports.  Instead a variable is used to keep\n\ttrack of the critical section nesting.  This variable has to be stored\n\tas part of the task context and is initially set to zero. */\n\t*pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;\n\n\treturn pxTopOfStack;\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xPortStartScheduler( void )\n{\n\t/* Start the timer that generates the tick ISR. */\n\tprvSetupTimerInterrupt();\n\n\t/* Start the first task.  This is done from portISR.c as ARM mode must be\n\tused. */\n\tvPortStartFirstTask();\n\n\t/* Should not get here! */\n\treturn 0;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEndScheduler( void )\n{\n\t/* It is unlikely that the ARM port will require this function as there\n\tis nothing to return to.  If this is required - stop the tick ISR then\n\treturn back to main. */\n}\n/*-----------------------------------------------------------*/\n\n#if configUSE_PREEMPTION == 0\n\n\t/* \n\t * The cooperative scheduler requires a normal IRQ service routine to \n\t * simply increment the system tick. \n\t */\n\tvoid vNonPreemptiveTick( void ) __irq;\n\tvoid vNonPreemptiveTick( void ) __irq\n\t{\n\t\t/* Increment the tick count - this may make a delaying task ready\n\t\tto run - but a context switch is not performed. */\t\t\n\t\txTaskIncrementTick();\n\n\t\tT0IR = portTIMER_MATCH_ISR_BIT;\t\t\t\t/* Clear the timer event */\n\t\tVICVectAddr = portCLEAR_VIC_INTERRUPT;\t\t/* Acknowledge the Interrupt */\n\t}\n\n #else\n\n\t/*\n\t **************************************************************************\n\t * The preemptive scheduler ISR is written in assembler and can be found   \n\t * in the portASM.s file. This will only get used if portUSE_PREEMPTION\n\t * is set to 1 in portmacro.h\n\t ************************************************************************** \n\t */\n\n\t  void vPreemptiveTick( void );\n\n#endif\n/*-----------------------------------------------------------*/\n\nstatic void prvSetupTimerInterrupt( void )\n{\nuint32_t ulCompareMatch;\n\n\t/* A 1ms tick does not require the use of the timer prescale.  This is\n\tdefaulted to zero but can be used if necessary. */\n\tT0PR = portPRESCALE_VALUE;\n\n\t/* Calculate the match value required for our wanted tick rate. */\n\tulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;\n\n\t/* Protect against divide by zero.  Using an if() statement still results\n\tin a warning - hence the #if. */\n\t#if portPRESCALE_VALUE != 0\n\t{\n\t\tulCompareMatch /= ( portPRESCALE_VALUE + 1 );\n\t}\n\t#endif\n\n\tT0MR0 = ulCompareMatch;\n\n\t/* Generate tick with timer 0 compare match. */\n\tT0MCR = portRESET_COUNT_ON_MATCH | portINTERRUPT_ON_MATCH;\n\n\t/* Setup the VIC for the timer. */\n\tVICIntSelect &= ~( portTIMER_VIC_CHANNEL_BIT );\n\tVICIntEnable |= portTIMER_VIC_CHANNEL_BIT;\n\t\n\t/* The ISR installed depends on whether the preemptive or cooperative\n\tscheduler is being used. */\n\t#if configUSE_PREEMPTION == 1\n\t{\t\n\t\tVICVectAddr0 = ( uint32_t ) vPreemptiveTick;\n\t}\n\t#else\n\t{\n\t\tVICVectAddr0 = ( uint32_t ) vNonPreemptiveTick;\n\t}\n\t#endif\n\n\tVICVectCntl0 = portTIMER_VIC_CHANNEL | portTIMER_VIC_ENABLE;\n\n\t/* Start the timer - interrupts are disabled when this function is called\n\tso it is okay to do this here. */\n\tT0TCR = portENABLE_TIMER;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEnterCritical( void )\n{\n\t/* Disable interrupts as per portDISABLE_INTERRUPTS(); \t\t\t\t\t\t\t*/\n\t__disable_irq();\n\n\t/* Now interrupts are disabled ulCriticalNesting can be accessed \n\tdirectly.  Increment ulCriticalNesting to keep a count of how many times\n\tportENTER_CRITICAL() has been called. */\n\tulCriticalNesting++;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortExitCritical( void )\n{\n\tif( ulCriticalNesting > portNO_CRITICAL_NESTING )\n\t{\n\t\t/* Decrement the nesting count as we are leaving a critical section. */\n\t\tulCriticalNesting--;\n\n\t\t/* If the nesting level has reached zero then interrupts should be\n\t\tre-enabled. */\n\t\tif( ulCriticalNesting == portNO_CRITICAL_NESTING )\n\t\t{\n\t\t\t/* Enable interrupts as per portEXIT_CRITICAL(). */\n\t\t\t__enable_irq();\n\t\t}\n\t}\n}\n/*-----------------------------------------------------------*/\n\n\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/RVDS/ARM7_LPC21xx/portASM.s",
    "content": ";/*\n; * FreeRTOS Kernel V10.5.1\n; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n; *\n; * SPDX-License-Identifier: MIT\n; *\n; * Permission is hereby granted, free of charge, to any person obtaining a copy of\n; * this software and associated documentation files (the \"Software\"), to deal in\n; * the Software without restriction, including without limitation the rights to\n; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n; * the Software, and to permit persons to whom the Software is furnished to do so,\n; * subject to the following conditions:\n; *\n; * The above copyright notice and this permission notice shall be included in all\n; * copies or substantial portions of the Software.\n; *\n; * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n; *\n; * https://www.FreeRTOS.org\n; * https://github.com/FreeRTOS\n; *\n; */\n\n\tINCLUDE portmacro.inc\n\n\tIMPORT\tvTaskSwitchContext\n\tIMPORT\txTaskIncrementTick\n\n\tEXPORT\tvPortYieldProcessor\n\tEXPORT\tvPortStartFirstTask\n\tEXPORT\tvPreemptiveTick\n\tEXPORT\tvPortYield\n\n\nVICVECTADDR\tEQU\t0xFFFFF030\nT0IR\t\tEQU\t0xE0004000\nT0MATCHBIT\tEQU\t0x00000001\n\n\tARM\n\tAREA\tPORT_ASM, CODE, READONLY\n\n\n\n;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n; Starting the first task is done by just restoring the context\n; setup by pxPortInitialiseStack\n;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\nvPortStartFirstTask\n\n\tPRESERVE8\n\n\tportRESTORE_CONTEXT\n\nvPortYield\n\n\tPRESERVE8\n\n\tSVC 0\n\tbx lr\n\n;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n; Interrupt service routine for the SWI interrupt.  The vector table is\n; configured in the startup.s file.\n;\n; vPortYieldProcessor() is used to manually force a context switch.  The\n; SWI interrupt is generated by a call to taskYIELD() or portYIELD().\n;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n\nvPortYieldProcessor\n\n\tPRESERVE8\n\n\t; Within an IRQ ISR the link register has an offset from the true return\n\t; address, but an SWI ISR does not.  Add the offset manually so the same\n\t; ISR return code can be used in both cases.\n\tADD\tLR, LR, #4\n\n\t; Perform the context switch.\n\tportSAVE_CONTEXT\t\t\t\t\t; Save current task context\n\tLDR R0, =vTaskSwitchContext\t\t\t; Get the address of the context switch function\n\tMOV LR, PC\t\t\t\t\t\t\t; Store the return address\n\tBX\tR0\t\t\t\t\t\t\t\t; Call the contedxt switch function\n\tportRESTORE_CONTEXT\t\t\t\t\t; restore the context of the selected task\n\n\n\n;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n; Interrupt service routine for preemptive scheduler tick timer\n; Only used if portUSE_PREEMPTION is set to 1 in portmacro.h\n;\n; Uses timer 0 of LPC21XX Family\n;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n\nvPreemptiveTick\n\n\tPRESERVE8\n\n\tportSAVE_CONTEXT\t\t\t\t\t; Save the context of the current task.\n\n\tLDR R0, =xTaskIncrementTick\t\t\t; Increment the tick count.\n\tMOV LR, PC\t\t\t\t\t\t\t; This may make a delayed task ready\n\tBX R0\t\t\t\t\t\t\t\t; to run.\n\n\tCMP R0, #0\n\tBEQ SkipContextSwitch\n\tLDR R0, =vTaskSwitchContext\t\t\t; Find the highest priority task that\n\tMOV LR, PC\t\t\t\t\t\t\t; is ready to run.\n\tBX R0\nSkipContextSwitch\n\tMOV R0, #T0MATCHBIT\t\t\t\t\t; Clear the timer event\n\tLDR R1, =T0IR\n\tSTR R0, [R1]\n\n\tLDR\tR0, =VICVECTADDR\t\t\t\t; Acknowledge the interrupt\n\tSTR\tR0,[R0]\n\n\tportRESTORE_CONTEXT\t\t\t\t\t; Restore the context of the highest\n\t\t\t\t\t\t\t\t\t\t; priority task that is ready to run.\n\tEND\n\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/RVDS/ARM7_LPC21xx/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n\n#ifndef PORTMACRO_H\n#define PORTMACRO_H\n\n/* *INDENT-OFF* */\n#ifdef __cplusplus\n    extern \"C\" {\n#endif\n/* *INDENT-ON* */\n\n/*-----------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the\n * given hardware and compiler.\n *\n * These settings should not be altered.\n *-----------------------------------------------------------\n */\n\n/* Type definitions. */\n#define portCHAR\t\tchar\n#define portFLOAT\t\tfloat\n#define portDOUBLE\t\tdouble\n#define portLONG\t\tlong\n#define portSHORT\t\tshort\n#define portSTACK_TYPE\tuint32_t\n#define portBASE_TYPE\tlong\n\ntypedef portSTACK_TYPE StackType_t;\ntypedef long BaseType_t;\ntypedef unsigned long UBaseType_t;\n\n\n#if( configUSE_16_BIT_TICKS == 1 )\n\ttypedef uint16_t TickType_t;\n\t#define portMAX_DELAY ( TickType_t ) 0xffff\n#else\n\ttypedef uint32_t TickType_t;\n\t#define portMAX_DELAY ( TickType_t ) 0xffffffffUL\n#endif\n/*-----------------------------------------------------------*/\n\n/* Hardware specifics. */\n#define portSTACK_GROWTH\t\t\t( -1 )\n#define portTICK_PERIOD_MS\t\t\t( ( TickType_t ) 1000 / configTICK_RATE_HZ )\n#define portBYTE_ALIGNMENT\t\t\t8\n/*-----------------------------------------------------------*/\n\n/* Task utilities. */\n\n/*-----------------------------------------------------------\n * ISR entry and exit macros.  These are only required if a task switch\n * is required from an ISR.\n *----------------------------------------------------------*/\n\n/* If a switch is required then we just need to call */\n/* vTaskSwitchContext() as the context has already been */\n/* saved. */\n\n#define portEXIT_SWITCHING_ISR(SwitchRequired)\t\t\t\t \\\n{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t \\\nextern void vTaskSwitchContext(void);\t\t\t\t\t\t \\\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t \\\n\t\tif(SwitchRequired)\t\t\t\t\t\t\t\t\t \\\n\t\t{\t\t\t\t\t\t\t\t\t\t\t\t\t \\\n\t\t\tvTaskSwitchContext();\t\t\t\t\t\t\t \\\n\t\t}\t\t\t\t\t\t\t\t\t\t\t\t\t \\\n}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t \\\n\nextern void vPortYield( void );\n#define portYIELD() vPortYield()\n\n\n/* Critical section management. */\n\n/*\n ******************************************************************\n * We don't need to worry about whether we're in ARM or\n * THUMB mode with the Keil Real View compiler when enabling\n * or disabling interrupts as the compiler's intrinsic functions\n * take care of that for us.\n *******************************************************************\n */\n#define portDISABLE_INTERRUPTS()\t__disable_irq()\n#define portENABLE_INTERRUPTS()\t\t__enable_irq()\n\n\n/*-----------------------------------------------------------\n * Critical section control\n *\n * The code generated by the Keil compiler does not maintain separate\n * stack and frame pointers. The portENTER_CRITICAL macro cannot therefore\n * use the stack as per other ports.  Instead a variable is used to keep\n * track of the critical section nesting.  This necessitates the use of a\n * function in place of the macro.\n *----------------------------------------------------------*/\n\nextern void vPortEnterCritical( void );\nextern void vPortExitCritical( void );\n\n#define portENTER_CRITICAL()\t\tvPortEnterCritical();\n#define portEXIT_CRITICAL()\t\t\tvPortExitCritical();\n/*-----------------------------------------------------------*/\n\n/* Compiler specifics. */\n#define inline\n#define register\n#define portNOP()\t__asm{ NOP }\n/*-----------------------------------------------------------*/\n\n/* Task function macros as described on the FreeRTOS.org WEB site. */\n#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )\tvoid vFunction( void *pvParameters )\n#define portTASK_FUNCTION( vFunction, pvParameters )\tvoid vFunction( void *pvParameters )\n\n/* *INDENT-OFF* */\n#ifdef __cplusplus\n    }\n#endif\n/* *INDENT-ON* */\n\n#endif /* PORTMACRO_H */\n\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/RVDS/ARM7_LPC21xx/portmacro.inc",
    "content": ";/*\n; * FreeRTOS Kernel V10.5.1\n; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n; *\n; * SPDX-License-Identifier: MIT\n; *\n; * Permission is hereby granted, free of charge, to any person obtaining a copy of\n; * this software and associated documentation files (the \"Software\"), to deal in\n; * the Software without restriction, including without limitation the rights to\n; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n; * the Software, and to permit persons to whom the Software is furnished to do so,\n; * subject to the following conditions:\n; *\n; * The above copyright notice and this permission notice shall be included in all\n; * copies or substantial portions of the Software.\n; *\n; * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n; *\n; * https://www.FreeRTOS.org\n; * https://github.com/FreeRTOS\n; *\n; */\n\n\tIMPORT  ulCriticalNesting\t\t;\n\tIMPORT\tpxCurrentTCB\t\t\t;\n\n\n\tMACRO\n\tportRESTORE_CONTEXT\n\n\n\tLDR\t\tR0, =pxCurrentTCB\t\t; Set the LR to the task stack.  The location was...\n\tLDR\t\tR0, [R0]\t\t\t\t; ... stored in pxCurrentTCB\n\tLDR\t\tLR, [R0]\n\n\tLDR\t\tR0, =ulCriticalNesting\t; The critical nesting depth is the first item on...\n\tLDMFD\tLR!, {R1}\t\t\t\t; ...the stack.  Load it into the ulCriticalNesting var.\n\tSTR\t\tR1, [R0]\t\t\t\t;\n\n\tLDMFD\tLR!, {R0}\t\t\t\t; Get the SPSR from the stack.\n\tMSR\t\tSPSR_cxsf, R0\t\t\t;\n\n\tLDMFD\tLR, {R0-R14}^\t\t\t; Restore all system mode registers for the task.\n\tNOP\t\t\t\t\t\t\t\t;\n\n\tLDR\t\tLR, [LR, #+60]\t\t\t; Restore the return address\n\n\t\t\t\t\t\t\t\t\t; And return - correcting the offset in the LR to obtain ...\n\tSUBS\tPC, LR, #4\t\t\t\t; ...the correct address.\n\n\tMEND\n\n; /**********************************************************************/\n\n\tMACRO\n\tportSAVE_CONTEXT\n\n\n\tSTMDB \tSP!, {R0}\t\t\t\t; Store R0 first as we need to use it.\n\n\tSTMDB\tSP,{SP}^\t\t\t\t; Set R0 to point to the task stack pointer.\n\tNOP\t\t\t\t\t\t\t\t;\n\tSUB\t\tSP, SP, #4\t\t\t\t;\n\tLDMIA\tSP!,{R0}\t\t\t\t;\n\n\tSTMDB\tR0!, {LR}\t\t\t\t; Push the return address onto the stack.\n\tMOV\t\tLR, R0\t\t\t\t\t; Now we have saved LR we can use it instead of R0.\n\tLDMIA\tSP!, {R0}\t\t\t\t; Pop R0 so we can save it onto the system mode stack.\n\n\tSTMDB\tLR,{R0-LR}^\t\t\t\t; Push all the system mode registers onto the task stack.\n\tNOP\t\t\t\t\t\t\t\t;\n\tSUB\t\tLR, LR, #60\t\t\t\t;\n\n\tMRS\t\tR0, SPSR\t\t\t\t; Push the SPSR onto the task stack.\n\tSTMDB\tLR!, {R0}\t\t\t\t;\n\n\tLDR\t\tR0, =ulCriticalNesting\t;\n\tLDR\t\tR0, [R0]\t\t\t\t;\n\tSTMDB\tLR!, {R0}\t\t\t\t;\n\n\tLDR\t\tR0, =pxCurrentTCB\t\t; Store the new top of stack for the task.\n\tLDR\t\tR1, [R0]\t\t\t\t;\n\tSTR\t\tLR, [R1]\t\t\t\t;\n\n\tMEND\n\n\tEND\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/RVDS/ARM_CA9/port.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Standard includes. */\n#include <stdlib.h>\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n#ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS\n\t#error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html\n#endif\n\n#ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET\n\t#error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html\n#endif\n\n#ifndef configUNIQUE_INTERRUPT_PRIORITIES\n\t#error configUNIQUE_INTERRUPT_PRIORITIES must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html\n#endif\n\n#ifndef configSETUP_TICK_INTERRUPT\n\t#error configSETUP_TICK_INTERRUPT() must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html\n#endif /* configSETUP_TICK_INTERRUPT */\n\n#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY\n\t#error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html\n#endif\n\n#if configMAX_API_CALL_INTERRUPT_PRIORITY == 0\n\t#error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0\n#endif\n\n#if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES\n\t#error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority\n#endif\n\n#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1\n\t/* Check the configuration. */\n\t#if( configMAX_PRIORITIES > 32 )\n\t\t#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.\n\t#endif\n#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */\n\n/* In case security extensions are implemented. */\n#if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )\n\t#error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )\n#endif\n\n#ifndef configCLEAR_TICK_INTERRUPT\n\t#define configCLEAR_TICK_INTERRUPT()\n#endif\n\n/* The number of bits to shift for an interrupt priority is dependent on the\nnumber of bits implemented by the interrupt controller. */\n#if configUNIQUE_INTERRUPT_PRIORITIES == 16\n\t#define portPRIORITY_SHIFT 4\n\t#define portMAX_BINARY_POINT_VALUE\t3\n#elif configUNIQUE_INTERRUPT_PRIORITIES == 32\n\t#define portPRIORITY_SHIFT 3\n\t#define portMAX_BINARY_POINT_VALUE\t2\n#elif configUNIQUE_INTERRUPT_PRIORITIES == 64\n\t#define portPRIORITY_SHIFT 2\n\t#define portMAX_BINARY_POINT_VALUE\t1\n#elif configUNIQUE_INTERRUPT_PRIORITIES == 128\n\t#define portPRIORITY_SHIFT 1\n\t#define portMAX_BINARY_POINT_VALUE\t0\n#elif configUNIQUE_INTERRUPT_PRIORITIES == 256\n\t#define portPRIORITY_SHIFT 0\n\t#define portMAX_BINARY_POINT_VALUE\t0\n#else\n\t#error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting.  configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware\n#endif\n\n/* A critical section is exited when the critical section nesting count reaches\nthis value. */\n#define portNO_CRITICAL_NESTING\t\t\t( ( uint32_t ) 0 )\n\n/* In all GICs 255 can be written to the priority mask register to unmask all\n(but the lowest) interrupt priority. */\n#define portUNMASK_VALUE\t\t\t\t( 0xFFUL )\n\n/* Tasks are not created with a floating point context, but can be given a\nfloating point context after they have been created.  A variable is stored as\npart of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task\ndoes not have an FPU context, or any other value if the task does have an FPU\ncontext. */\n#define portNO_FLOATING_POINT_CONTEXT\t( ( StackType_t ) 0 )\n\n/* Interrupt controller access addresses. */\n#define portICCPMR_PRIORITY_MASK_OFFSET  \t\t( 0x04 )\n#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ( 0x0C )\n#define portICCEOIR_END_OF_INTERRUPT_OFFSET \t( 0x10 )\n#define portICCBPR_BINARY_POINT_OFFSET\t\t\t( 0x08 )\n#define portICCRPR_RUNNING_PRIORITY_OFFSET\t\t( 0x14 )\n#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS \t\t( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )\n#define portICCPMR_PRIORITY_MASK_REGISTER \t\t\t\t\t( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )\n#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS \t( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )\n#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS \t\t( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )\n#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS \t\t\t( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )\n#define portICCBPR_BINARY_POINT_REGISTER \t\t\t\t\t( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )\n#define portICCRPR_RUNNING_PRIORITY_REGISTER \t\t\t\t( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )\n\n/* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary\npoint is zero. */\n#define portBINARY_POINT_BITS\t\t\t( ( uint8_t ) 0x03 )\n\n/* Constants required to setup the initial task context. */\n#define portINITIAL_SPSR\t\t\t\t( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */\n#define portTHUMB_MODE_BIT\t\t\t\t( ( StackType_t ) 0x20 )\n#define portTHUMB_MODE_ADDRESS\t\t\t( 0x01UL )\n\n/* Masks all bits in the APSR other than the mode bits. */\n#define portAPSR_MODE_BITS_MASK\t\t\t( 0x1F )\n\n/* The value of the mode bits in the APSR when the CPU is executing in user\nmode. */\n#define portAPSR_USER_MODE\t\t\t\t( 0x10 )\n\n/* Macro to unmask all interrupt priorities. */\n#define portCLEAR_INTERRUPT_MASK()\t\t\t\t\t\t\t\t\t\t\t\\\n{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t__disable_irq();\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tportICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE;\t\t\t\t\t\\\n\t__asm(\t\"DSB\t\t\\n\"\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\"ISB\t\t\\n\" );\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t__enable_irq();\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n}\n\n/*-----------------------------------------------------------*/\n\n/*\n * Starts the first task executing.  This function is necessarily written in\n * assembly code so is implemented in portASM.s.\n */\nextern void vPortRestoreTaskContext( void );\n\n/*\n * Used to catch tasks that attempt to return from their implementing function.\n */\nstatic void prvTaskExitError( void );\n\n/*-----------------------------------------------------------*/\n\n/* A variable is used to keep track of the critical section nesting.  This\nvariable has to be stored as part of the task context and must be initialised to\na non zero value to ensure interrupts don't inadvertently become unmasked before\nthe scheduler starts.  As it is stored as part of the task context it will\nautomatically be set to 0 when the first task is started. */\nvolatile uint32_t ulCriticalNesting = 9999UL;\n\n/* Used to pass constants into the ASM code.  The address at which variables are\nplaced is the constant value so indirect loads in the asm code are not\nrequired. */\nuint32_t ulICCIAR __attribute__( ( at( portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ) ) );\nuint32_t ulICCEOIR __attribute__( ( at( portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ) ) );\nuint32_t ulICCPMR __attribute__( ( at( portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ) ) );\nuint32_t ulAsmAPIPriorityMask __attribute__( ( at( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) ) );\n\n/* Saved as part of the task context.  If ulPortTaskHasFPUContext is non-zero then\na floating point context must be saved and restored for the task. */\nuint32_t ulPortTaskHasFPUContext = pdFALSE;\n\n/* Set to 1 to pend a context switch from an ISR. */\nuint32_t ulPortYieldRequired = pdFALSE;\n\n/* Counts the interrupt nesting depth.  A context switch is only performed if\nif the nesting depth is 0. */\nuint32_t ulPortInterruptNesting = 0UL;\n\n/*-----------------------------------------------------------*/\n\n/*\n * See header file for description.\n */\nStackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )\n{\n\t/* Setup the initial stack of the task.  The stack is set exactly as\n\texpected by the portRESTORE_CONTEXT() macro.\n\n\tThe fist real value on the stack is the status register, which is set for\n\tsystem mode, with interrupts enabled.  A few NULLs are added first to ensure\n\tGDB does not try decoding a non-existent return address. */\n\t*pxTopOfStack = NULL;\n\tpxTopOfStack--;\n\t*pxTopOfStack = NULL;\n\tpxTopOfStack--;\n\t*pxTopOfStack = NULL;\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;\n\n\tif( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )\n\t{\n\t\t/* The task will start in THUMB mode. */\n\t\t*pxTopOfStack |= portTHUMB_MODE_BIT;\n\t}\n\n\tpxTopOfStack--;\n\n\t/* Next the return address, which in this case is the start of the task. */\n\t*pxTopOfStack = ( StackType_t ) pxCode;\n\tpxTopOfStack--;\n\n\t/* Next all the registers other than the stack pointer. */\n\t*pxTopOfStack = ( StackType_t ) prvTaskExitError;\t/* R14 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x12121212;\t/* R12 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x11111111;\t/* R11 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x10101010;\t/* R10 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x09090909;\t/* R9 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x08080808;\t/* R8 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x07070707;\t/* R7 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x06060606;\t/* R6 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x05050505;\t/* R5 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x04040404;\t/* R4 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x03030303;\t/* R3 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x02020202;\t/* R2 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) 0x01010101;\t/* R1 */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\n\tpxTopOfStack--;\n\n\t/* The task will start with a critical nesting count of 0 as interrupts are\n\tenabled. */\n\t*pxTopOfStack = portNO_CRITICAL_NESTING;\n\tpxTopOfStack--;\n\n\t/* The task will start without a floating point context.  A task that uses\n\tthe floating point hardware must call vPortTaskUsesFPU() before executing\n\tany floating point instructions. */\n\t*pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;\n\n\treturn pxTopOfStack;\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvTaskExitError( void )\n{\n\t/* A function that implements a task must not exit or attempt to return to\n\tits caller as there is nothing to return to.  If a task wants to exit it\n\tshould instead call vTaskDelete( NULL ).\n\n\tArtificially force an assert() to be triggered if configASSERT() is\n\tdefined, then stop here so application writers can catch the error. */\n\tconfigASSERT( ulPortInterruptNesting == ~0UL );\n\tportDISABLE_INTERRUPTS();\n\tfor( ;; );\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xPortStartScheduler( void )\n{\nuint32_t ulAPSR;\n\n\t/* Only continue if the CPU is not in User mode.  The CPU must be in a\n\tPrivileged mode for the scheduler to start. */\n\t__asm( \"MRS ulAPSR, APSR\" );\n\tulAPSR &= portAPSR_MODE_BITS_MASK;\n\tconfigASSERT( ulAPSR != portAPSR_USER_MODE );\n\n\tif( ulAPSR != portAPSR_USER_MODE )\n\t{\n\t\t/* Only continue if the binary point value is set to its lowest possible\n\t\tsetting.  See the comments in vPortValidateInterruptPriority() below for\n\t\tmore information. */\n\t\tconfigASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );\n\n\t\tif( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )\n\t\t{\n\t\t\t/* Start the timer that generates the tick ISR. */\n\t\t\tconfigSETUP_TICK_INTERRUPT();\n\n\t\t\t__enable_irq();\n\t\t\tvPortRestoreTaskContext();\n\t\t}\n\t}\n\n\t/* Will only get here if vTaskStartScheduler() was called with the CPU in\n\ta non-privileged mode or the binary point register was not set to its lowest\n\tpossible value. */\n\treturn 0;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEndScheduler( void )\n{\n\t/* Not implemented in ports where there is nothing to return to.\n\tArtificially force an assert. */\n\tconfigASSERT( ulCriticalNesting == 1000UL );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEnterCritical( void )\n{\n\t/* Disable interrupts as per portDISABLE_INTERRUPTS(); \t*/\n\tulPortSetInterruptMask();\n\n\t/* Now interrupts are disabled ulCriticalNesting can be accessed\n\tdirectly.  Increment ulCriticalNesting to keep a count of how many times\n\tportENTER_CRITICAL() has been called. */\n\tulCriticalNesting++;\n\n\t/* This is not the interrupt safe version of the enter critical function so\n\tassert() if it is being called from an interrupt context.  Only API\n\tfunctions that end in \"FromISR\" can be used in an interrupt.  Only assert if\n\tthe critical nesting count is 1 to protect against recursive calls if the\n\tassert function also uses a critical section. */\n\tif( ulCriticalNesting == 1 )\n\t{\n\t\tconfigASSERT( ulPortInterruptNesting == 0 );\n\t}\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortExitCritical( void )\n{\n\tif( ulCriticalNesting > portNO_CRITICAL_NESTING )\n\t{\n\t\t/* Decrement the nesting count as the critical section is being\n\t\texited. */\n\t\tulCriticalNesting--;\n\n\t\t/* If the nesting level has reached zero then all interrupt\n\t\tpriorities must be re-enabled. */\n\t\tif( ulCriticalNesting == portNO_CRITICAL_NESTING )\n\t\t{\n\t\t\t/* Critical nesting has reached zero so all interrupt priorities\n\t\t\tshould be unmasked. */\n\t\t\tportCLEAR_INTERRUPT_MASK();\n\t\t}\n\t}\n}\n/*-----------------------------------------------------------*/\n\nvoid FreeRTOS_Tick_Handler( void )\n{\n\t/* Set interrupt mask before altering scheduler structures.   The tick\n\thandler runs at the lowest priority, so interrupts cannot already be masked,\n\tso there is no need to save and restore the current mask value. */\n\t__disable_irq();\n\tportICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );\n\t__asm(\t\"DSB\t\t\\n\"\n\t\t\t\"ISB\t\t\\n\" );\n\t__enable_irq();\n\n\t/* Increment the RTOS tick. */\n\tif( xTaskIncrementTick() != pdFALSE )\n\t{\n\t\tulPortYieldRequired = pdTRUE;\n\t}\n\n\t/* Ensure all interrupt priorities are active again. */\n\tportCLEAR_INTERRUPT_MASK();\n\tconfigCLEAR_TICK_INTERRUPT();\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortTaskUsesFPU( void )\n{\nuint32_t ulInitialFPSCR = 0;\n\n\t/* A task is registering the fact that it needs an FPU context.  Set the\n\tFPU flag (which is saved as part of the task context). */\n\tulPortTaskHasFPUContext = pdTRUE;\n\n\t/* Initialise the floating point status register. */\n\t__asm( \"FMXR \tFPSCR, ulInitialFPSCR\" );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortClearInterruptMask( uint32_t ulNewMaskValue )\n{\n\tif( ulNewMaskValue == pdFALSE )\n\t{\n\t\tportCLEAR_INTERRUPT_MASK();\n\t}\n}\n/*-----------------------------------------------------------*/\n\nuint32_t ulPortSetInterruptMask( void )\n{\nuint32_t ulReturn;\n\n\t__disable_irq();\n\tif( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )\n\t{\n\t\t/* Interrupts were already masked. */\n\t\tulReturn = pdTRUE;\n\t}\n\telse\n\t{\n\t\tulReturn = pdFALSE;\n\t\tportICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );\n\t\t__asm(\t\"DSB\t\t\\n\"\n\t\t\t\t\"ISB\t\t\\n\" );\n\t}\n\t__enable_irq();\n\n\treturn ulReturn;\n}\n/*-----------------------------------------------------------*/\n\n#if( configASSERT_DEFINED == 1 )\n\n\tvoid vPortValidateInterruptPriority( void )\n\t{\n\t\t/* The following assertion will fail if a service routine (ISR) for\n\t\tan interrupt that has been assigned a priority above\n\t\tconfigMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\n\t\tfunction.  ISR safe FreeRTOS API functions must *only* be called\n\t\tfrom interrupts that have been assigned a priority at or below\n\t\tconfigMAX_SYSCALL_INTERRUPT_PRIORITY.\n\n\t\tNumerically low interrupt priority numbers represent logically high\n\t\tinterrupt priorities, therefore the priority of the interrupt must\n\t\tbe set to a value equal to or numerically *higher* than\n\t\tconfigMAX_SYSCALL_INTERRUPT_PRIORITY.\n\n\t\tFreeRTOS maintains separate thread and ISR API functions to ensure\n\t\tinterrupt entry is as fast and simple as possible.\n\n\t\tThe following links provide detailed information:\n\t\thttps://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html\n\t\thttps://www.FreeRTOS.org/FAQHelp.html */\n\t\tconfigASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );\n\n\t\t/* Priority grouping:  The interrupt controller (GIC) allows the bits\n\t\tthat define each interrupt's priority to be split between bits that\n\t\tdefine the interrupt's pre-emption priority bits and bits that define\n\t\tthe interrupt's sub-priority.  For simplicity all bits must be defined\n\t\tto be pre-emption priority bits.  The following assertion will fail if\n\t\tthis is not the case (if some bits represent a sub-priority).\n\n\t\tThe priority grouping is configured by the GIC's binary point register\n\t\t(ICCBPR).  Writting 0 to ICCBPR will ensure it is set to its lowest\n\t\tpossible value (which may be above 0). */\n\t\tconfigASSERT( portICCBPR_BINARY_POINT_REGISTER <= portMAX_BINARY_POINT_VALUE );\n\t}\n\n#endif /* configASSERT_DEFINED */\n\n\n\n\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/RVDS/ARM_CA9/portASM.s",
    "content": ";/*\n; * FreeRTOS Kernel V10.5.1\n; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n; *\n; * SPDX-License-Identifier: MIT\n; *\n; * Permission is hereby granted, free of charge, to any person obtaining a copy of\n; * this software and associated documentation files (the \"Software\"), to deal in\n; * the Software without restriction, including without limitation the rights to\n; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n; * the Software, and to permit persons to whom the Software is furnished to do so,\n; * subject to the following conditions:\n; *\n; * The above copyright notice and this permission notice shall be included in all\n; * copies or substantial portions of the Software.\n; *\n; * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n; *\n; * https://www.FreeRTOS.org\n; * https://github.com/FreeRTOS\n; *\n; */\n\n\tINCLUDE portmacro.inc\n\n\tIMPORT\tvApplicationIRQHandler\n\tIMPORT\tvTaskSwitchContext\n\tIMPORT\tulPortYieldRequired\n\tIMPORT\tulPortInterruptNesting\n\tIMPORT\tvTaskSwitchContext\n\tIMPORT\tulICCIAR\n\tIMPORT\tulICCEOIR\n\n\tEXPORT\tFreeRTOS_SWI_Handler\n\tEXPORT  FreeRTOS_IRQ_Handler\n\tEXPORT \tvPortRestoreTaskContext\n\n\tARM\n\tAREA\tPORT_ASM, CODE, READONLY\n\n\n;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n; SVC handler is used to yield a task.\n;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\nFreeRTOS_SWI_Handler\n\n\tPRESERVE8\n\n\t; Save the context of the current task and select a new task to run.\n\tportSAVE_CONTEXT\n\tLDR R0, =vTaskSwitchContext\n\tBLX\tR0\n\tportRESTORE_CONTEXT\n\n;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n; vPortRestoreTaskContext is used to start the scheduler.\n;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\nvPortRestoreTaskContext\n\t; Switch to system mode\n\tCPS\t\t#SYS_MODE\n\tportRESTORE_CONTEXT\n\n;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n; PL390 GIC interrupt handler\n;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\nFreeRTOS_IRQ_Handler\n\n\t; Return to the interrupted instruction.\n\tSUB\t\tlr, lr, #4\n\n\t; Push the return address and SPSR\n\tPUSH\t{lr}\n\tMRS\t\tlr, SPSR\n\tPUSH\t{lr}\n\n\t; Change to supervisor mode to allow reentry.\n\tCPS\t\t#SVC_MODE\n\n\t; Push used registers.\n\tPUSH\t{r0-r4, r12}\n\n\t; Increment nesting count.  r3 holds the address of ulPortInterruptNesting\n\t; for future use.  r1 holds the original ulPortInterruptNesting value for\n\t; future use.\n\tLDR\t\tr3, =ulPortInterruptNesting\n\tLDR\t\tr1, [r3]\n\tADD\t\tr4, r1, #1\n\tSTR\t\tr4, [r3]\n\n\t; Read value from the interrupt acknowledge register, which is stored in r0\n\t; for future parameter and interrupt clearing use.\n\tLDR \tr2, =ulICCIAR\n\tLDR\t\tr0, [r2]\n\n\t; Ensure bit 2 of the stack pointer is clear.  r2 holds the bit 2 value for\n\t; future use.  _RB_ Does this ever actually need to be done provided the\n\t; start of the stack is 8-byte aligned?\n\tMOV\t\tr2, sp\n\tAND\t\tr2, r2, #4\n\tSUB\t\tsp, sp, r2\n\n\t; Call the interrupt handler.  r4 is pushed to maintain alignment.\n\tPUSH\t{r0-r4, lr}\n\tLDR\t\tr1, =vApplicationIRQHandler\n\tBLX\t\tr1\n\tPOP\t\t{r0-r4, lr}\n\tADD\t\tsp, sp, r2\n\n\tCPSID \ti\n\n\t; Write the value read from ICCIAR to ICCEOIR\n\tLDR \tr4, =ulICCEOIR\n\tSTR\t\tr0, [r4]\n\n\t; Restore the old nesting count\n\tSTR\t\tr1, [r3]\n\n\t; A context switch is never performed if the nesting count is not 0\n\tCMP\t\tr1, #0\n\tBNE\t\texit_without_switch\n\n\t; Did the interrupt request a context switch?  r1 holds the address of\n\t; ulPortYieldRequired and r0 the value of ulPortYieldRequired for future\n\t; use.\n\tLDR\t\tr1, =ulPortYieldRequired\n\tLDR\t\tr0, [r1]\n\tCMP\t\tr0, #0\n\tBNE\t\tswitch_before_exit\n\nexit_without_switch\n\t; No context switch.  Restore used registers, LR_irq and SPSR before\n\t; returning.\n\tPOP\t\t{r0-r4, r12}\n\tCPS\t\t#IRQ_MODE\n\tPOP\t\t{LR}\n\tMSR\t\tSPSR_cxsf, LR\n\tPOP\t\t{LR}\n\tMOVS\tPC, LR\n\nswitch_before_exit\n\t; A context swtich is to be performed.  Clear the context switch pending\n\t; flag.\n\tMOV\t\tr0, #0\n\tSTR\t\tr0, [r1]\n\n\t; Restore used registers, LR-irq and SPSR before saving the context\n\t; to the task stack.\n\tPOP\t\t{r0-r4, r12}\n\tCPS\t\t#IRQ_MODE\n\tPOP\t\t{LR}\n\tMSR\t\tSPSR_cxsf, LR\n\tPOP\t\t{LR}\n\tportSAVE_CONTEXT\n\n\t; Call the function that selects the new task to execute.\n\t; vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD\n\t; instructions, or 8 byte aligned stack allocated data.  LR does not need\n\t; saving as a new LR will be loaded by portRESTORE_CONTEXT anyway.\n\tLDR\t\tr0, =vTaskSwitchContext\n\tBLX\t\tr0\n\n\t; Restore the context of, and branch to, the task selected to execute next.\n\tportRESTORE_CONTEXT\n\n\n\tEND\n\n\n\n\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/RVDS/ARM_CA9/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#ifndef PORTMACRO_H\n#define PORTMACRO_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/*-----------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the given hardware\n * and compiler.\n *\n * These settings should not be altered.\n *-----------------------------------------------------------\n */\n\n/* Type definitions. */\n#define portCHAR\t\tchar\n#define portFLOAT\t\tfloat\n#define portDOUBLE\t\tdouble\n#define portLONG\t\tlong\n#define portSHORT\t\tshort\n#define portSTACK_TYPE\tuint32_t\n#define portBASE_TYPE\tlong\n\ntypedef portSTACK_TYPE StackType_t;\ntypedef long BaseType_t;\ntypedef unsigned long UBaseType_t;\n\n\n#if( configUSE_16_BIT_TICKS == 1 )\n\ttypedef uint16_t TickType_t;\n\t#define portMAX_DELAY ( TickType_t ) 0xffff\n#else\n\ttypedef uint32_t TickType_t;\n\t#define portMAX_DELAY ( TickType_t ) 0xffffffffUL\n\n\t/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\n\tnot need to be guarded with a critical section. */\n\t#define portTICK_TYPE_IS_ATOMIC 1\n#endif\n/*-----------------------------------------------------------*/\n\n/* Hardware specifics. */\n#define portSTACK_GROWTH\t\t\t( -1 )\n#define portTICK_PERIOD_MS\t\t\t( ( TickType_t ) 1000 / configTICK_RATE_HZ )\n#define portBYTE_ALIGNMENT\t\t\t8\n\n/*-----------------------------------------------------------*/\n\n/* Task utilities. */\n\n/* Called at the end of an ISR that can cause a context switch. */\n#define portEND_SWITCHING_ISR( xSwitchRequired )\\\n{\t\t\t\t\t\t\t\t\t\t\t\t\\\nextern uint32_t ulPortYieldRequired;\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tif( xSwitchRequired != pdFALSE )\t\t\t\\\n\t{\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tulPortYieldRequired = pdTRUE;\t\t\t\\\n\t}\t\t\t\t\t\t\t\t\t\t\t\\\n}\n\n#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\n#define portYIELD() __asm( \"SWI 0\" );\n\n\n/*-----------------------------------------------------------\n * Critical section control\n *----------------------------------------------------------*/\n\nextern void vPortEnterCritical( void );\nextern void vPortExitCritical( void );\nextern uint32_t ulPortSetInterruptMask( void );\nextern void vPortClearInterruptMask( uint32_t ulNewMaskValue );\n\n/* These macros do not globally disable/enable interrupts.  They do mask off\ninterrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */\n#define portENTER_CRITICAL()\t\tvPortEnterCritical();\n#define portEXIT_CRITICAL()\t\t\tvPortExitCritical();\n#define portDISABLE_INTERRUPTS()\tulPortSetInterruptMask()\n#define portENABLE_INTERRUPTS()\t\tvPortClearInterruptMask( 0 )\n#define portSET_INTERRUPT_MASK_FROM_ISR()\t\tulPortSetInterruptMask()\n#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)\tvPortClearInterruptMask(x)\n\n/*-----------------------------------------------------------*/\n\n/* Task function macros as described on the FreeRTOS.org WEB site.  These are\nnot required for this port but included in case common demo code that uses these\nmacros is used. */\n#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )\tvoid vFunction( void *pvParameters )\n#define portTASK_FUNCTION( vFunction, pvParameters )\tvoid vFunction( void *pvParameters )\n\n/* Prototype of the FreeRTOS tick handler.  This must be installed as the\nhandler for whichever peripheral is used to generate the RTOS tick. */\nvoid FreeRTOS_Tick_Handler( void );\n\n/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()\nbefore any floating point instructions are executed. */\nvoid vPortTaskUsesFPU( void );\n#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()\n\n#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )\n#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )\n\n/* Architecture specific optimisations. */\n#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION\n\t#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1\n#endif\n\n#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1\n\n\t/* Store/clear the ready priorities in a bit map. */\n\t#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )\n\t#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )\n\n\t/*-----------------------------------------------------------*/\n\n\t#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __clz( uxReadyPriorities ) )\n\n#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */\n\n#ifdef configASSERT\n\tvoid vPortValidateInterruptPriority( void );\n\t#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() \tvPortValidateInterruptPriority()\n#endif\n\n#define portNOP() __nop()\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* PORTMACRO_H */\n\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/RVDS/ARM_CA9/portmacro.inc",
    "content": ";/*\n; * FreeRTOS Kernel V10.5.1\n; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n; *\n; * SPDX-License-Identifier: MIT\n; *\n; * Permission is hereby granted, free of charge, to any person obtaining a copy of\n; * this software and associated documentation files (the \"Software\"), to deal in\n; * the Software without restriction, including without limitation the rights to\n; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n; * the Software, and to permit persons to whom the Software is furnished to do so,\n; * subject to the following conditions:\n; *\n; * The above copyright notice and this permission notice shall be included in all\n; * copies or substantial portions of the Software.\n; *\n; * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n; *\n; * https://www.FreeRTOS.org\n; * https://github.com/FreeRTOS\n; *\n; */\n\nSYS_MODE\t\t\tEQU\t\t0x1f\nSVC_MODE\t\t\tEQU\t\t0x13\nIRQ_MODE\t\t\tEQU\t\t0x12\n\n\tIMPORT  ulCriticalNesting\n\tIMPORT\tpxCurrentTCB\n\tIMPORT\tulPortTaskHasFPUContext\n\tIMPORT  ulAsmAPIPriorityMask\n\tIMPORT\tulICCPMR\n\n\n\tMACRO\n\tportSAVE_CONTEXT\n\n\t; Save the LR and SPSR onto the system mode stack before switching to\n\t; system mode to save the remaining system mode registers\n\tSRSDB\tsp!, #SYS_MODE\n\tCPS\t\t#SYS_MODE\n\tPUSH\t{R0-R12, R14}\n\n\t; Push the critical nesting count\n\tLDR\t\tR2, =ulCriticalNesting\n\tLDR\t\tR1, [R2]\n\tPUSH\t{R1}\n\n\t; Does the task have a floating point context that needs saving?  If\n\t; ulPortTaskHasFPUContext is 0 then no.\n\tLDR\t\tR2, =ulPortTaskHasFPUContext\n\tLDR\t\tR3, [R2]\n\tCMP\t\tR3, #0\n\n\t; Save the floating point context, if any\n\tFMRXNE  R1,  FPSCR\n\tVPUSHNE {D0-D15}\n\tVPUSHNE\t{D16-D31}\n\tPUSHNE\t{R1}\n\n\t; Save ulPortTaskHasFPUContext itself\n\tPUSH\t{R3}\n\n\t; Save the stack pointer in the TCB\n\tLDR\t\tR0, =pxCurrentTCB\n\tLDR\t\tR1, [R0]\n\tSTR\t\tSP, [R1]\n\n\tMEND\n\n; /**********************************************************************/\n\n\tMACRO\n\tportRESTORE_CONTEXT\n\n\t; Set the SP to point to the stack of the task being restored.\n\tLDR\t\tR0, =pxCurrentTCB\n\tLDR\t\tR1, [R0]\n\tLDR\t\tSP, [R1]\n\n\t; Is there a floating point context to restore?  If the restored\n\t; ulPortTaskHasFPUContext is zero then no.\n\tLDR\t\tR0, =ulPortTaskHasFPUContext\n\tPOP\t\t{R1}\n\tSTR\t\tR1, [R0]\n\tCMP\t\tR1, #0\n\n\t; Restore the floating point context, if any\n\tPOPNE\t{R0}\n\tVPOPNE\t{D16-D31}\n\tVPOPNE\t{D0-D15}\n\tVMSRNE  FPSCR, R0\n\n\t; Restore the critical section nesting depth\n\tLDR\t\tR0, =ulCriticalNesting\n\tPOP\t\t{R1}\n\tSTR\t\tR1, [R0]\n\n\t; Ensure the priority mask is correct for the critical nesting depth\n\tLDR\t\tR2, =ulICCPMR\n\tCMP\t\tR1, #0\n\tMOVEQ\tR4, #255\n\tLDRNE\tR4, =ulAsmAPIPriorityMask\n\tSTR\t\tR4, [r2]\n\n\t; Restore all system mode registers other than the SP (which is already\n\t; being used)\n\tPOP\t\t{R0-R12, R14}\n\n\t; Return to the task code, loading CPSR on the way.\n\tRFEIA\tsp!\n\n\tMEND\n\n\tEND\n\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/RVDS/ARM_CM0/port.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/*-----------------------------------------------------------\n* Implementation of functions defined in portable.h for the ARM CM0 port.\n*----------------------------------------------------------*/\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n/* Constants required to manipulate the NVIC. */\n#define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )\n#define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )\n#define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )\n#define portNVIC_INT_CTRL_REG                 ( *( ( volatile uint32_t * ) 0xe000ed04 ) )\n#define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )\n#define portNVIC_SYSTICK_CLK_BIT              ( 1UL << 2UL )\n#define portNVIC_SYSTICK_INT_BIT              ( 1UL << 1UL )\n#define portNVIC_SYSTICK_ENABLE_BIT           ( 1UL << 0UL )\n#define portNVIC_SYSTICK_COUNT_FLAG_BIT       ( 1UL << 16UL )\n#define portNVIC_PENDSVSET_BIT                ( 1UL << 28UL )\n#define portNVIC_PEND_SYSTICK_SET_BIT         ( 1UL << 26UL )\n#define portNVIC_PEND_SYSTICK_CLEAR_BIT       ( 1UL << 25UL )\n#define portMIN_INTERRUPT_PRIORITY            ( 255UL )\n#define portNVIC_PENDSV_PRI                   ( portMIN_INTERRUPT_PRIORITY << 16UL )\n#define portNVIC_SYSTICK_PRI                  ( portMIN_INTERRUPT_PRIORITY << 24UL )\n\n/* Constants required to set up the initial stack. */\n#define portINITIAL_XPSR                      ( 0x01000000 )\n\n/* The systick is a 24-bit counter. */\n#define portMAX_24_BIT_NUMBER                 ( 0xffffffUL )\n\n/* A fiddle factor to estimate the number of SysTick counts that would have\n * occurred while the SysTick counter is stopped during tickless idle\n * calculations. */\n#ifndef portMISSED_COUNTS_FACTOR\n    #define portMISSED_COUNTS_FACTOR    ( 94UL )\n#endif\n\n/* Constants used with memory barrier intrinsics. */\n#define portSY_FULL_READ_WRITE    ( 15 )\n\n/* Let the user override the default SysTick clock rate.  If defined by the\n * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the\n * configuration register. */\n#ifndef configSYSTICK_CLOCK_HZ\n    #define configSYSTICK_CLOCK_HZ             ( configCPU_CLOCK_HZ )\n    /* Ensure the SysTick is clocked at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( portNVIC_SYSTICK_CLK_BIT )\n#else\n    /* Select the option to clock SysTick not at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( 0 )\n#endif\n\n/* Legacy macro for backward compatibility only.  This macro used to be used to\n * replace the function that configures the clock used to generate the tick\n * interrupt (prvSetupTimerInterrupt()), but now the function is declared weak so\n * the application writer can override it by simply defining a function of the\n * same name (vApplicationSetupTickInterrupt()). */\n#ifndef configOVERRIDE_DEFAULT_TICK_CONFIGURATION\n    #define configOVERRIDE_DEFAULT_TICK_CONFIGURATION    0\n#endif\n\n/* Each task maintains its own interrupt status in the critical nesting\n * variable. */\nstatic UBaseType_t uxCriticalNesting = 0xaaaaaaaa;\n\n/* The number of SysTick increments that make up one tick period. */\n#if ( configUSE_TICKLESS_IDLE == 1 )\n    static uint32_t ulTimerCountsForOneTick = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n\n/* The maximum number of tick periods that can be suppressed is limited by the\n * 24 bit resolution of the SysTick timer. */\n#if ( configUSE_TICKLESS_IDLE == 1 )\n    static uint32_t xMaximumPossibleSuppressedTicks = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n\n/* Compensate for the CPU cycles that pass while the SysTick is stopped (low\n * power functionality only.\n */\n#if ( configUSE_TICKLESS_IDLE == 1 )\n    static uint32_t ulStoppedTimerCompensation = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n\n/*\n * Setup the timer to generate the tick interrupts.  The implementation in this\n * file is weak to allow application writers to change the timer used to\n * generate the tick interrupt.\n */\nvoid vPortSetupTimerInterrupt( void );\n\n/*\n * Exception handlers.\n */\nvoid xPortPendSVHandler( void );\nvoid xPortSysTickHandler( void );\nvoid vPortSVCHandler( void );\n\n/*\n * Start first task is a separate function so it can be tested in isolation.\n */\nstatic void prvPortStartFirstTask( void );\n\n/*\n * Used to catch tasks that attempt to return from their implementing function.\n */\nstatic void prvTaskExitError( void );\n\n/*-----------------------------------------------------------*/\n\n/*\n * See header file for description.\n */\nStackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,\n                                     TaskFunction_t pxCode,\n                                     void * pvParameters )\n{\n    /* Simulate the stack frame as it would be created by a context switch\n     * interrupt. */\n    pxTopOfStack--;                                   /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\n    *pxTopOfStack = portINITIAL_XPSR;                 /* xPSR */\n    pxTopOfStack--;\n    *pxTopOfStack = ( StackType_t ) pxCode;           /* PC */\n    pxTopOfStack--;\n    *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* LR */\n    pxTopOfStack -= 5;                                /* R12, R3, R2 and R1. */\n    *pxTopOfStack = ( StackType_t ) pvParameters;     /* R0 */\n    pxTopOfStack -= 8;                                /* R11..R4. */\n\n    return pxTopOfStack;\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvTaskExitError( void )\n{\n    /* A function that implements a task must not exit or attempt to return to\n     * its caller as there is nothing to return to.  If a task wants to exit it\n     * should instead call vTaskDelete( NULL ).\n     *\n     * Artificially force an assert() to be triggered if configASSERT() is\n     * defined, then stop here so application writers can catch the error. */\n    configASSERT( uxCriticalNesting == ~0UL );\n    portDISABLE_INTERRUPTS();\n\n    for( ; ; )\n    {\n    }\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortSVCHandler( void )\n{\n    /* This function is no longer used, but retained for backward\n     * compatibility. */\n}\n/*-----------------------------------------------------------*/\n\n__asm void prvPortStartFirstTask( void )\n{\n    extern pxCurrentTCB;\n\n    PRESERVE8\n\n    /* The MSP stack is not reset as, unlike on M3/4 parts, there is no vector\n     * table offset register that can be used to locate the initial stack value.\n     * Not all M0 parts have the application vector table at address 0. */\n/* *INDENT-OFF* */\n\n    ldr r3, = pxCurrentTCB /* Obtain location of pxCurrentTCB. */\n    ldr r1, [ r3 ]\n    ldr r0, [ r1 ]         /* The first item in pxCurrentTCB is the task top of stack. */\n    adds r0, # 32          /* Discard everything up to r0. */\n    msr psp, r0            /* This is now the new top of stack to use in the task. */\n    movs r0, # 2           /* Switch to the psp stack. */\n    msr CONTROL, r0\n    isb\n    pop { r0 - r5 } /* Pop the registers that are saved automatically. */\n    mov lr, r5 /* lr is now in r5. */\n    pop { r3 } /* The return address is now in r3. */\n    pop { r2 } /* Pop and discard the XPSR. */\n    cpsie i /* The first task has its context and interrupts can be enabled. */\n    bx r3 /* Finally, jump to the user defined task code. */\n\n    ALIGN\n/* *INDENT-ON* */\n}\n/*-----------------------------------------------------------*/\n\n/*\n * See header file for description.\n */\nBaseType_t xPortStartScheduler( void )\n{\n    /* Make PendSV, CallSV and SysTick the same priority as the kernel. */\n    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;\n\n    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;\n\n    /* Start the timer that generates the tick ISR.  Interrupts are disabled\n     * here already. */\n    vPortSetupTimerInterrupt();\n\n    /* Initialise the critical nesting count ready for the first task. */\n    uxCriticalNesting = 0;\n\n    /* Start the first task. */\n    prvPortStartFirstTask();\n\n    /* Should not get here! */\n    return 0;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEndScheduler( void )\n{\n    /* Not implemented in ports where there is nothing to return to.\n     * Artificially force an assert. */\n    configASSERT( uxCriticalNesting == 1000UL );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortYield( void )\n{\n    /* Set a PendSV to request a context switch. */\n    portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\n\n    /* Barriers are normally not required but do ensure the code is completely\n     * within the specified behaviour for the architecture. */\n    __dsb( portSY_FULL_READ_WRITE );\n    __isb( portSY_FULL_READ_WRITE );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEnterCritical( void )\n{\n    portDISABLE_INTERRUPTS();\n    uxCriticalNesting++;\n    __dsb( portSY_FULL_READ_WRITE );\n    __isb( portSY_FULL_READ_WRITE );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortExitCritical( void )\n{\n    configASSERT( uxCriticalNesting );\n    uxCriticalNesting--;\n\n    if( uxCriticalNesting == 0 )\n    {\n        portENABLE_INTERRUPTS();\n    }\n}\n/*-----------------------------------------------------------*/\n\n__asm uint32_t ulSetInterruptMaskFromISR( void )\n{\n/* *INDENT-OFF* */\n    mrs r0, PRIMASK\n    cpsid i\n    bx lr\n/* *INDENT-ON* */\n}\n/*-----------------------------------------------------------*/\n\n__asm void vClearInterruptMaskFromISR( uint32_t ulMask )\n{\n/* *INDENT-OFF* */\n    msr PRIMASK, r0\n    bx lr\n/* *INDENT-ON* */\n}\n/*-----------------------------------------------------------*/\n\n__asm void xPortPendSVHandler( void )\n{\n    extern vTaskSwitchContext\n    extern pxCurrentTCB\n\n/* *INDENT-OFF* */\n    PRESERVE8\n\n    mrs r0, psp\n\n    ldr r3, = pxCurrentTCB /* Get the location of the current TCB. */\n    ldr r2, [ r3 ]\n\n    subs r0, # 32  /* Make space for the remaining low registers. */\n    str r0, [ r2 ] /* Save the new top of stack. */\n    stmia r0 !, { r4 - r7 } /* Store the low registers that are not saved automatically. */\n    mov r4, r8 /* Store the high registers. */\n    mov r5, r9\n    mov r6, r10\n    mov r7, r11\n    stmia r0 !, { r4 - r7 }\n\n    push { r3, r14 }\n    cpsid i\n    bl vTaskSwitchContext\n    cpsie i\n    pop { r2, r3 } /* lr goes in r3. r2 now holds tcb pointer. */\n\n    ldr r1, [ r2 ]\n    ldr r0, [ r1 ] /* The first item in pxCurrentTCB is the task top of stack. */\n    adds r0, # 16  /* Move to the high registers. */\n    ldmia r0 !, { r4 - r7 } /* Pop the high registers. */\n    mov r8, r4\n    mov r9, r5\n    mov r10, r6\n    mov r11, r7\n\n    msr psp, r0   /* Remember the new top of stack for the task. */\n\n    subs r0, # 32 /* Go back for the low registers that are not automatically restored. */\n    ldmia r0 !, { r4 - r7 } /* Pop low registers.  */\n\n    bx r3\n    ALIGN\n/* *INDENT-ON* */\n}\n/*-----------------------------------------------------------*/\n\nvoid xPortSysTickHandler( void )\n{\n    uint32_t ulPreviousMask;\n\n    ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();\n    {\n        /* Increment the RTOS tick. */\n        if( xTaskIncrementTick() != pdFALSE )\n        {\n            /* Pend a context switch. */\n            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\n        }\n    }\n    portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );\n}\n/*-----------------------------------------------------------*/\n\n/*\n * Setup the systick timer to generate the tick interrupts at the required\n * frequency.\n */\n#if ( configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0 )\n\n    __weak void vPortSetupTimerInterrupt( void )\n    {\n        /* Calculate the constants required to configure the tick interrupt. */\n        #if ( configUSE_TICKLESS_IDLE == 1 )\n        {\n            ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );\n            xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;\n            ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\n        }\n        #endif /* configUSE_TICKLESS_IDLE */\n\n        /* Stop and clear the SysTick. */\n        portNVIC_SYSTICK_CTRL_REG = 0UL;\n        portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n        /* Configure SysTick to interrupt at the requested rate. */\n        portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\n        portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );\n    }\n\n#endif /* configOVERRIDE_DEFAULT_TICK_CONFIGURATION */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TICKLESS_IDLE == 1 )\n\n    __weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )\n    {\n        uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;\n        TickType_t xModifiableIdleTime;\n\n        /* Make sure the SysTick reload value does not overflow the counter. */\n        if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\n        {\n            xExpectedIdleTime = xMaximumPossibleSuppressedTicks;\n        }\n\n        /* Enter a critical section but don't use the taskENTER_CRITICAL()\n         * method as that will mask interrupts that should exit sleep mode. */\n        __disable_irq();\n        __dsb( portSY_FULL_READ_WRITE );\n        __isb( portSY_FULL_READ_WRITE );\n\n        /* If a context switch is pending or a task is waiting for the scheduler\n         * to be unsuspended then abandon the low power entry. */\n        if( eTaskConfirmSleepModeStatus() == eAbortSleep )\n        {\n            /* Re-enable interrupts - see comments above the __disable_irq()\n             * call above. */\n            __enable_irq();\n        }\n        else\n        {\n            /* Stop the SysTick momentarily.  The time the SysTick is stopped for\n             * is accounted for as best it can be, but using the tickless mode will\n             * inevitably result in some tiny drift of the time maintained by the\n             * kernel with respect to calendar time. */\n            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );\n\n            /* Use the SysTick current-value register to determine the number of\n             * SysTick decrements remaining until the next tick interrupt.  If the\n             * current-value register is zero, then there are actually\n             * ulTimerCountsForOneTick decrements remaining, not zero, because the\n             * SysTick requests the interrupt when decrementing from 1 to 0. */\n            ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n\n            if( ulSysTickDecrementsLeft == 0 )\n            {\n                ulSysTickDecrementsLeft = ulTimerCountsForOneTick;\n            }\n\n            /* Calculate the reload value required to wait xExpectedIdleTime\n             * tick periods.  -1 is used because this code normally executes part\n             * way through the first tick period.  But if the SysTick IRQ is now\n             * pending, then clear the IRQ, suppressing the first tick, and correct\n             * the reload value to reflect that the second tick period is already\n             * underway.  The expected idle time is always at least two ticks. */\n            ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );\n\n            if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )\n            {\n                portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;\n                ulReloadValue -= ulTimerCountsForOneTick;\n            }\n\n            if( ulReloadValue > ulStoppedTimerCompensation )\n            {\n                ulReloadValue -= ulStoppedTimerCompensation;\n            }\n\n            /* Set the new reload value. */\n            portNVIC_SYSTICK_LOAD_REG = ulReloadValue;\n\n            /* Clear the SysTick count flag and set the count value back to\n             * zero. */\n            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n            /* Restart SysTick. */\n            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\n\n            /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can\n             * set its parameter to 0 to indicate that its implementation contains\n             * its own wait for interrupt or wait for event instruction, and so wfi\n             * should not be executed again.  However, the original expected idle\n             * time variable must remain unmodified, so a copy is taken. */\n            xModifiableIdleTime = xExpectedIdleTime;\n            configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\n\n            if( xModifiableIdleTime > 0 )\n            {\n                __dsb( portSY_FULL_READ_WRITE );\n                __wfi();\n                __isb( portSY_FULL_READ_WRITE );\n            }\n\n            configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\n\n            /* Re-enable interrupts to allow the interrupt that brought the MCU\n             * out of sleep mode to execute immediately.  See comments above\n             * the __disable_irq() call above. */\n            __enable_irq();\n            __dsb( portSY_FULL_READ_WRITE );\n            __isb( portSY_FULL_READ_WRITE );\n\n            /* Disable interrupts again because the clock is about to be stopped\n             * and interrupts that execute while the clock is stopped will increase\n             * any slippage between the time maintained by the RTOS and calendar\n             * time. */\n            __disable_irq();\n            __dsb( portSY_FULL_READ_WRITE );\n            __isb( portSY_FULL_READ_WRITE );\n\n            /* Disable the SysTick clock without reading the\n             * portNVIC_SYSTICK_CTRL_REG register to ensure the\n             * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,\n             * the time the SysTick is stopped for is accounted for as best it can\n             * be, but using the tickless mode will inevitably result in some tiny\n             * drift of the time maintained by the kernel with respect to calendar\n             * time*/\n            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );\n\n            /* Determine whether the SysTick has already counted to zero. */\n            if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n            {\n                uint32_t ulCalculatedLoadValue;\n\n                /* The tick interrupt ended the sleep (or is now pending), and\n                 * a new tick period has started.  Reset portNVIC_SYSTICK_LOAD_REG\n                 * with whatever remains of the new tick period. */\n                ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\n\n                /* Don't allow a tiny value, or values that have somehow\n                 * underflowed because the post sleep hook did something\n                 * that took too long or because the SysTick current-value register\n                 * is zero. */\n                if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )\n                {\n                    ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );\n                }\n\n                portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;\n\n                /* As the pending tick will be processed as soon as this\n                 * function exits, the tick value maintained by the tick is stepped\n                 * forward by one less than the time spent waiting. */\n                ulCompleteTickPeriods = xExpectedIdleTime - 1UL;\n            }\n            else\n            {\n                /* Something other than the tick interrupt ended the sleep. */\n\n                /* Use the SysTick current-value register to determine the\n                 * number of SysTick decrements remaining until the expected idle\n                 * time would have ended. */\n                ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n                #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )\n                {\n                    /* If the SysTick is not using the core clock, the current-\n                     * value register might still be zero here.  In that case, the\n                     * SysTick didn't load from the reload register, and there are\n                     * ulReloadValue decrements remaining in the expected idle\n                     * time, not zero. */\n                    if( ulSysTickDecrementsLeft == 0 )\n                    {\n                        ulSysTickDecrementsLeft = ulReloadValue;\n                    }\n                }\n                #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */\n\n                /* Work out how long the sleep lasted rounded to complete tick\n                 * periods (not the ulReload value which accounted for part\n                 * ticks). */\n                ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;\n\n                /* How many complete tick periods passed while the processor\n                 * was waiting? */\n                ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;\n\n                /* The reload value is set to whatever fraction of a single tick\n                 * period remains. */\n                portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;\n            }\n\n            /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,\n             * then set portNVIC_SYSTICK_LOAD_REG back to its standard value.  If\n             * the SysTick is not using the core clock, temporarily configure it to\n             * use the core clock.  This configuration forces the SysTick to load\n             * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next\n             * cycle of the other clock.  Then portNVIC_SYSTICK_LOAD_REG is ready\n             * to receive the standard value immediately. */\n            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n            portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n            #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )\n            {\n                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n            }\n            #else\n            {\n                /* The temporary usage of the core clock has served its purpose,\n                 * as described above.  Resume usage of the other clock. */\n                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\n\n                if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n                {\n                    /* The partial tick period already ended.  Be sure the SysTick\n                     * counts it only once. */\n                    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;\n                }\n\n                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n            }\n            #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */\n\n            /* Step the tick to account for any tick periods that elapsed. */\n            vTaskStepTick( ulCompleteTickPeriods );\n\n            /* Exit with interrupts enabled. */\n            __enable_irq();\n        }\n    }\n\n#endif /* #if configUSE_TICKLESS_IDLE */\n\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/RVDS/ARM_CM0/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n\n#ifndef PORTMACRO_H\n#define PORTMACRO_H\n\n/* *INDENT-OFF* */\n#ifdef __cplusplus\n    extern \"C\" {\n#endif\n/* *INDENT-ON* */\n\n/*-----------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the\n * given hardware and compiler.\n *\n * These settings should not be altered.\n *-----------------------------------------------------------\n */\n\n/* Type definitions. */\n    #define portCHAR          char\n    #define portFLOAT         float\n    #define portDOUBLE        double\n    #define portLONG          long\n    #define portSHORT         short\n    #define portSTACK_TYPE    uint32_t\n    #define portBASE_TYPE     long\n\n    typedef portSTACK_TYPE   StackType_t;\n    typedef long             BaseType_t;\n    typedef unsigned long    UBaseType_t;\n\n    #if ( configUSE_16_BIT_TICKS == 1 )\n        typedef uint16_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffff\n    #else\n        typedef uint32_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL\n\n/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\n * not need to be guarded with a critical section. */\n        #define portTICK_TYPE_IS_ATOMIC    1\n    #endif\n/*-----------------------------------------------------------*/\n\n/* Architecture specifics. */\n    #define portSTACK_GROWTH      ( -1 )\n    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\n    #define portBYTE_ALIGNMENT    8\n/*-----------------------------------------------------------*/\n\n\n/* Scheduler utilities. */\n    extern void vPortYield( void );\n    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )\n    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )\n    #define portYIELD()                                 vPortYield()\n    #define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )\n    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )\n/*-----------------------------------------------------------*/\n\n/* Critical section management. */\n    extern void vPortEnterCritical( void );\n    extern void vPortExitCritical( void );\n    extern uint32_t ulSetInterruptMaskFromISR( void );\n    extern void vClearInterruptMaskFromISR( uint32_t ulMask );\n\n    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulSetInterruptMaskFromISR()\n    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vClearInterruptMaskFromISR( x )\n    #define portDISABLE_INTERRUPTS()                  __disable_irq()\n    #define portENABLE_INTERRUPTS()                   __enable_irq()\n    #define portENTER_CRITICAL()                      vPortEnterCritical()\n    #define portEXIT_CRITICAL()                       vPortExitCritical()\n\n/*-----------------------------------------------------------*/\n\n/* Tickless idle/low power functionality. */\n    #ifndef portSUPPRESS_TICKS_AND_SLEEP\n        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );\n        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )\n    #endif\n/*-----------------------------------------------------------*/\n\n/* Task function macros as described on the FreeRTOS.org WEB site. */\n    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )\n    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )\n\n    #define portNOP()\n\n/* *INDENT-OFF* */\n#ifdef __cplusplus\n    }\n#endif\n/* *INDENT-ON* */\n\n#endif /* PORTMACRO_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/RVDS/ARM_CM3/port.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/*-----------------------------------------------------------\n* Implementation of functions defined in portable.h for the ARM CM3 port.\n*----------------------------------------------------------*/\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n#ifndef configKERNEL_INTERRUPT_PRIORITY\n    #define configKERNEL_INTERRUPT_PRIORITY    255\n#endif\n\n#if configMAX_SYSCALL_INTERRUPT_PRIORITY == 0\n    #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\n#endif\n\n/* Legacy macro for backward compatibility only.  This macro used to be used to\n * replace the function that configures the clock used to generate the tick\n * interrupt (prvSetupTimerInterrupt()), but now the function is declared weak so\n * the application writer can override it by simply defining a function of the\n * same name (vApplicationSetupTickInterrupt()). */\n#ifndef configOVERRIDE_DEFAULT_TICK_CONFIGURATION\n    #define configOVERRIDE_DEFAULT_TICK_CONFIGURATION    0\n#endif\n\n/* Constants required to manipulate the core.  Registers first... */\n#define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )\n#define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )\n#define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )\n#define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )\n/* ...then bits in the registers. */\n#define portNVIC_SYSTICK_CLK_BIT              ( 1UL << 2UL )\n#define portNVIC_SYSTICK_INT_BIT              ( 1UL << 1UL )\n#define portNVIC_SYSTICK_ENABLE_BIT           ( 1UL << 0UL )\n#define portNVIC_SYSTICK_COUNT_FLAG_BIT       ( 1UL << 16UL )\n#define portNVIC_PENDSVCLEAR_BIT              ( 1UL << 27UL )\n#define portNVIC_PEND_SYSTICK_SET_BIT         ( 1UL << 26UL )\n#define portNVIC_PEND_SYSTICK_CLEAR_BIT       ( 1UL << 25UL )\n\n#define portNVIC_PENDSV_PRI                   ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\n#define portNVIC_SYSTICK_PRI                  ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\n\n/* Constants required to check the validity of an interrupt priority. */\n#define portFIRST_USER_INTERRUPT_NUMBER       ( 16 )\n#define portNVIC_IP_REGISTERS_OFFSET_16       ( 0xE000E3F0 )\n#define portAIRCR_REG                         ( *( ( volatile uint32_t * ) 0xE000ED0C ) )\n#define portMAX_8_BIT_VALUE                   ( ( uint8_t ) 0xff )\n#define portTOP_BIT_OF_BYTE                   ( ( uint8_t ) 0x80 )\n#define portMAX_PRIGROUP_BITS                 ( ( uint8_t ) 7 )\n#define portPRIORITY_GROUP_MASK               ( 0x07UL << 8UL )\n#define portPRIGROUP_SHIFT                    ( 8UL )\n\n/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */\n#define portVECTACTIVE_MASK                   ( 0xFFUL )\n\n/* Constants required to set up the initial stack. */\n#define portINITIAL_XPSR                      ( 0x01000000 )\n\n/* The systick is a 24-bit counter. */\n#define portMAX_24_BIT_NUMBER                 ( 0xffffffUL )\n\n/* A fiddle factor to estimate the number of SysTick counts that would have\n * occurred while the SysTick counter is stopped during tickless idle\n * calculations. */\n#define portMISSED_COUNTS_FACTOR              ( 94UL )\n\n/* For strict compliance with the Cortex-M spec the task start address should\n * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */\n#define portSTART_ADDRESS_MASK                ( ( StackType_t ) 0xfffffffeUL )\n\n/* Let the user override the default SysTick clock rate.  If defined by the\n * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the\n * configuration register. */\n#ifndef configSYSTICK_CLOCK_HZ\n    #define configSYSTICK_CLOCK_HZ             ( configCPU_CLOCK_HZ )\n    /* Ensure the SysTick is clocked at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( portNVIC_SYSTICK_CLK_BIT )\n#else\n    /* Select the option to clock SysTick not at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( 0 )\n#endif\n\n/*\n * Setup the timer to generate the tick interrupts.  The implementation in this\n * file is weak to allow application writers to change the timer used to\n * generate the tick interrupt.\n */\nvoid vPortSetupTimerInterrupt( void );\n\n/*\n * Exception handlers.\n */\nvoid xPortPendSVHandler( void );\nvoid xPortSysTickHandler( void );\nvoid vPortSVCHandler( void );\n\n/*\n * Start first task is a separate function so it can be tested in isolation.\n */\nstatic void prvStartFirstTask( void );\n\n/*\n * Used to catch tasks that attempt to return from their implementing function.\n */\nstatic void prvTaskExitError( void );\n\n/*-----------------------------------------------------------*/\n\n/* Each task maintains its own interrupt status in the critical nesting\n * variable. */\nstatic UBaseType_t uxCriticalNesting = 0xaaaaaaaa;\n\n/*\n * The number of SysTick increments that make up one tick period.\n */\n#if ( configUSE_TICKLESS_IDLE == 1 )\n    static uint32_t ulTimerCountsForOneTick = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n\n/*\n * The maximum number of tick periods that can be suppressed is limited by the\n * 24 bit resolution of the SysTick timer.\n */\n#if ( configUSE_TICKLESS_IDLE == 1 )\n    static uint32_t xMaximumPossibleSuppressedTicks = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n\n/*\n * Compensate for the CPU cycles that pass while the SysTick is stopped (low\n * power functionality only.\n */\n#if ( configUSE_TICKLESS_IDLE == 1 )\n    static uint32_t ulStoppedTimerCompensation = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n\n/*\n * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure\n * FreeRTOS API functions are not called from interrupts that have been assigned\n * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.\n */\n#if ( configASSERT_DEFINED == 1 )\n    static uint8_t ucMaxSysCallPriority = 0;\n    static uint32_t ulMaxPRIGROUPValue = 0;\n    static const volatile uint8_t * const pcInterruptPriorityRegisters = ( uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;\n#endif /* configASSERT_DEFINED */\n\n/*-----------------------------------------------------------*/\n\n/*\n * See header file for description.\n */\nStackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,\n                                     TaskFunction_t pxCode,\n                                     void * pvParameters )\n{\n    /* Simulate the stack frame as it would be created by a context switch\n     * interrupt. */\n    pxTopOfStack--;                                                      /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\n    *pxTopOfStack = portINITIAL_XPSR;                                    /* xPSR */\n    pxTopOfStack--;\n    *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */\n    pxTopOfStack--;\n    *pxTopOfStack = ( StackType_t ) prvTaskExitError;                    /* LR */\n\n    pxTopOfStack -= 5;                                                   /* R12, R3, R2 and R1. */\n    *pxTopOfStack = ( StackType_t ) pvParameters;                        /* R0 */\n    pxTopOfStack -= 8;                                                   /* R11, R10, R9, R8, R7, R6, R5 and R4. */\n\n    return pxTopOfStack;\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvTaskExitError( void )\n{\n    /* A function that implements a task must not exit or attempt to return to\n     * its caller as there is nothing to return to.  If a task wants to exit it\n     * should instead call vTaskDelete( NULL ).\n     *\n     * Artificially force an assert() to be triggered if configASSERT() is\n     * defined, then stop here so application writers can catch the error. */\n    configASSERT( uxCriticalNesting == ~0UL );\n    portDISABLE_INTERRUPTS();\n\n    for( ; ; )\n    {\n    }\n}\n/*-----------------------------------------------------------*/\n\n__asm void vPortSVCHandler( void )\n{\n/* *INDENT-OFF* */\n    PRESERVE8\n\n    ldr r3, = pxCurrentTCB   /* Restore the context. */\n    ldr r1, [ r3 ] /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */\n    ldr r0, [ r1 ]           /* The first item in pxCurrentTCB is the task top of stack. */\n    ldmia r0 !, { r4 - r11 } /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */\n    msr psp, r0 /* Restore the task stack pointer. */\n    isb\n    mov r0, # 0\n    msr basepri, r0\n    orr r14, # 0xd\n    bx r14\n/* *INDENT-ON* */\n}\n/*-----------------------------------------------------------*/\n\n__asm void prvStartFirstTask( void )\n{\n/* *INDENT-OFF* */\n    PRESERVE8\n\n    /* Use the NVIC offset register to locate the stack. */\n    ldr r0, =0xE000ED08\n    ldr r0, [ r0 ]\n    ldr r0, [ r0 ]\n\n    /* Set the msp back to the start of the stack. */\n    msr msp, r0\n    /* Globally enable interrupts. */\n    cpsie i\n    cpsie f\n    dsb\n    isb\n    /* Call SVC to start the first task. */\n    svc 0\n    nop\n    nop\n/* *INDENT-ON* */\n}\n/*-----------------------------------------------------------*/\n\n/*\n * See header file for description.\n */\nBaseType_t xPortStartScheduler( void )\n{\n    #if ( configASSERT_DEFINED == 1 )\n    {\n        volatile uint32_t ulOriginalPriority;\n        volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\n        volatile uint8_t ucMaxPriorityValue;\n\n        /* Determine the maximum priority from which ISR safe FreeRTOS API\n         * functions can be called.  ISR safe functions are those that end in\n         * \"FromISR\".  FreeRTOS maintains separate thread and ISR API functions to\n         * ensure interrupt entry is as fast and simple as possible.\n         *\n         * Save the interrupt priority value that is about to be clobbered. */\n        ulOriginalPriority = *pucFirstUserPriorityRegister;\n\n        /* Determine the number of priority bits available.  First write to all\n         * possible bits. */\n        *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\n\n        /* Read the value back to see how many bits stuck. */\n        ucMaxPriorityValue = *pucFirstUserPriorityRegister;\n\n        /* The kernel interrupt priority should be set to the lowest\n         * priority. */\n        configASSERT( ucMaxPriorityValue == ( configKERNEL_INTERRUPT_PRIORITY & ucMaxPriorityValue ) );\n\n        /* Use the same mask on the maximum system call priority. */\n        ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;\n\n        /* Calculate the maximum acceptable priority group value for the number\n         * of bits read back. */\n        ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;\n\n        while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )\n        {\n            ulMaxPRIGROUPValue--;\n            ucMaxPriorityValue <<= ( uint8_t ) 0x01;\n        }\n\n        #ifdef __NVIC_PRIO_BITS\n        {\n            /* Check the CMSIS configuration that defines the number of\n             * priority bits matches the number of priority bits actually queried\n             * from the hardware. */\n            configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );\n        }\n        #endif\n\n        #ifdef configPRIO_BITS\n        {\n            /* Check the FreeRTOS configuration that defines the number of\n             * priority bits matches the number of priority bits actually queried\n             * from the hardware. */\n            configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );\n        }\n        #endif\n\n        /* Shift the priority group value back to its position within the AIRCR\n         * register. */\n        ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;\n        ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;\n\n        /* Restore the clobbered interrupt priority register to its original\n         * value. */\n        *pucFirstUserPriorityRegister = ulOriginalPriority;\n    }\n    #endif /* configASSERT_DEFINED */\n\n    /* Make PendSV and SysTick the lowest priority interrupts. */\n    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;\n\n    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;\n\n    /* Start the timer that generates the tick ISR.  Interrupts are disabled\n     * here already. */\n    vPortSetupTimerInterrupt();\n\n    /* Initialise the critical nesting count ready for the first task. */\n    uxCriticalNesting = 0;\n\n    /* Start the first task. */\n    prvStartFirstTask();\n\n    /* Should not get here! */\n    return 0;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEndScheduler( void )\n{\n    /* Not implemented in ports where there is nothing to return to.\n     * Artificially force an assert. */\n    configASSERT( uxCriticalNesting == 1000UL );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEnterCritical( void )\n{\n    portDISABLE_INTERRUPTS();\n    uxCriticalNesting++;\n\n    /* This is not the interrupt safe version of the enter critical function so\n     * assert() if it is being called from an interrupt context.  Only API\n     * functions that end in \"FromISR\" can be used in an interrupt.  Only assert if\n     * the critical nesting count is 1 to protect against recursive calls if the\n     * assert function also uses a critical section. */\n    if( uxCriticalNesting == 1 )\n    {\n        configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );\n    }\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortExitCritical( void )\n{\n    configASSERT( uxCriticalNesting );\n    uxCriticalNesting--;\n\n    if( uxCriticalNesting == 0 )\n    {\n        portENABLE_INTERRUPTS();\n    }\n}\n/*-----------------------------------------------------------*/\n\n__asm void xPortPendSVHandler( void )\n{\n    extern uxCriticalNesting;\n    extern pxCurrentTCB;\n    extern vTaskSwitchContext;\n\n/* *INDENT-OFF* */\n    PRESERVE8\n\n    mrs r0, psp\n    isb\n\n    ldr r3, =pxCurrentTCB /* Get the location of the current TCB. */\n    ldr r2, [ r3 ]\n\n    stmdb r0 !, { r4 - r11 } /* Save the remaining registers. */\n    str r0, [ r2 ] /* Save the new top of stack into the first member of the TCB. */\n\n    stmdb sp !, { r3, r14 }\n    mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY\n    msr basepri, r0\n    dsb\n    isb\n    bl vTaskSwitchContext\n    mov r0, #0\n    msr basepri, r0\n    ldmia sp !, { r3, r14 }\n\n    ldr r1, [ r3 ]\n    ldr r0, [ r1 ] /* The first item in pxCurrentTCB is the task top of stack. */\n    ldmia r0 !, { r4 - r11 } /* Pop the registers and the critical nesting count. */\n    msr psp, r0\n    isb\n    bx r14\n    nop\n/* *INDENT-ON* */\n}\n/*-----------------------------------------------------------*/\n\nvoid xPortSysTickHandler( void )\n{\n    /* The SysTick runs at the lowest interrupt priority, so when this interrupt\n     * executes all interrupts must be unmasked.  There is therefore no need to\n     * save and then restore the interrupt mask value as its value is already\n     * known - therefore the slightly faster vPortRaiseBASEPRI() function is used\n     * in place of portSET_INTERRUPT_MASK_FROM_ISR(). */\n    vPortRaiseBASEPRI();\n    {\n        /* Increment the RTOS tick. */\n        if( xTaskIncrementTick() != pdFALSE )\n        {\n            /* A context switch is required.  Context switching is performed in\n             * the PendSV interrupt.  Pend the PendSV interrupt. */\n            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\n        }\n    }\n\n    vPortClearBASEPRIFromISR();\n}\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TICKLESS_IDLE == 1 )\n\n    __weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )\n    {\n        uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;\n        TickType_t xModifiableIdleTime;\n\n        /* Make sure the SysTick reload value does not overflow the counter. */\n        if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\n        {\n            xExpectedIdleTime = xMaximumPossibleSuppressedTicks;\n        }\n\n        /* Enter a critical section but don't use the taskENTER_CRITICAL()\n         * method as that will mask interrupts that should exit sleep mode. */\n        __disable_irq();\n        __dsb( portSY_FULL_READ_WRITE );\n        __isb( portSY_FULL_READ_WRITE );\n\n        /* If a context switch is pending or a task is waiting for the scheduler\n         * to be unsuspended then abandon the low power entry. */\n        if( eTaskConfirmSleepModeStatus() == eAbortSleep )\n        {\n            /* Re-enable interrupts - see comments above the __disable_irq()\n             * call above. */\n            __enable_irq();\n        }\n        else\n        {\n            /* Stop the SysTick momentarily.  The time the SysTick is stopped for\n             * is accounted for as best it can be, but using the tickless mode will\n             * inevitably result in some tiny drift of the time maintained by the\n             * kernel with respect to calendar time. */\n            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );\n\n            /* Use the SysTick current-value register to determine the number of\n             * SysTick decrements remaining until the next tick interrupt.  If the\n             * current-value register is zero, then there are actually\n             * ulTimerCountsForOneTick decrements remaining, not zero, because the\n             * SysTick requests the interrupt when decrementing from 1 to 0. */\n            ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n\n            if( ulSysTickDecrementsLeft == 0 )\n            {\n                ulSysTickDecrementsLeft = ulTimerCountsForOneTick;\n            }\n\n            /* Calculate the reload value required to wait xExpectedIdleTime\n             * tick periods.  -1 is used because this code normally executes part\n             * way through the first tick period.  But if the SysTick IRQ is now\n             * pending, then clear the IRQ, suppressing the first tick, and correct\n             * the reload value to reflect that the second tick period is already\n             * underway.  The expected idle time is always at least two ticks. */\n            ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );\n\n            if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )\n            {\n                portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;\n                ulReloadValue -= ulTimerCountsForOneTick;\n            }\n\n            if( ulReloadValue > ulStoppedTimerCompensation )\n            {\n                ulReloadValue -= ulStoppedTimerCompensation;\n            }\n\n            /* Set the new reload value. */\n            portNVIC_SYSTICK_LOAD_REG = ulReloadValue;\n\n            /* Clear the SysTick count flag and set the count value back to\n             * zero. */\n            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n            /* Restart SysTick. */\n            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\n\n            /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can\n             * set its parameter to 0 to indicate that its implementation contains\n             * its own wait for interrupt or wait for event instruction, and so wfi\n             * should not be executed again.  However, the original expected idle\n             * time variable must remain unmodified, so a copy is taken. */\n            xModifiableIdleTime = xExpectedIdleTime;\n            configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\n\n            if( xModifiableIdleTime > 0 )\n            {\n                __dsb( portSY_FULL_READ_WRITE );\n                __wfi();\n                __isb( portSY_FULL_READ_WRITE );\n            }\n\n            configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\n\n            /* Re-enable interrupts to allow the interrupt that brought the MCU\n             * out of sleep mode to execute immediately.  See comments above\n             * the __disable_irq() call above. */\n            __enable_irq();\n            __dsb( portSY_FULL_READ_WRITE );\n            __isb( portSY_FULL_READ_WRITE );\n\n            /* Disable interrupts again because the clock is about to be stopped\n             * and interrupts that execute while the clock is stopped will increase\n             * any slippage between the time maintained by the RTOS and calendar\n             * time. */\n            __disable_irq();\n            __dsb( portSY_FULL_READ_WRITE );\n            __isb( portSY_FULL_READ_WRITE );\n\n            /* Disable the SysTick clock without reading the\n             * portNVIC_SYSTICK_CTRL_REG register to ensure the\n             * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,\n             * the time the SysTick is stopped for is accounted for as best it can\n             * be, but using the tickless mode will inevitably result in some tiny\n             * drift of the time maintained by the kernel with respect to calendar\n             * time*/\n            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );\n\n            /* Determine whether the SysTick has already counted to zero. */\n            if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n            {\n                uint32_t ulCalculatedLoadValue;\n\n                /* The tick interrupt ended the sleep (or is now pending), and\n                 * a new tick period has started.  Reset portNVIC_SYSTICK_LOAD_REG\n                 * with whatever remains of the new tick period. */\n                ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\n\n                /* Don't allow a tiny value, or values that have somehow\n                 * underflowed because the post sleep hook did something\n                 * that took too long or because the SysTick current-value register\n                 * is zero. */\n                if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )\n                {\n                    ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );\n                }\n\n                portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;\n\n                /* As the pending tick will be processed as soon as this\n                 * function exits, the tick value maintained by the tick is stepped\n                 * forward by one less than the time spent waiting. */\n                ulCompleteTickPeriods = xExpectedIdleTime - 1UL;\n            }\n            else\n            {\n                /* Something other than the tick interrupt ended the sleep. */\n\n                /* Use the SysTick current-value register to determine the\n                 * number of SysTick decrements remaining until the expected idle\n                 * time would have ended. */\n                ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n                #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )\n                {\n                    /* If the SysTick is not using the core clock, the current-\n                     * value register might still be zero here.  In that case, the\n                     * SysTick didn't load from the reload register, and there are\n                     * ulReloadValue decrements remaining in the expected idle\n                     * time, not zero. */\n                    if( ulSysTickDecrementsLeft == 0 )\n                    {\n                        ulSysTickDecrementsLeft = ulReloadValue;\n                    }\n                }\n                #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */\n\n                /* Work out how long the sleep lasted rounded to complete tick\n                 * periods (not the ulReload value which accounted for part\n                 * ticks). */\n                ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;\n\n                /* How many complete tick periods passed while the processor\n                 * was waiting? */\n                ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;\n\n                /* The reload value is set to whatever fraction of a single tick\n                 * period remains. */\n                portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;\n            }\n\n            /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,\n             * then set portNVIC_SYSTICK_LOAD_REG back to its standard value.  If\n             * the SysTick is not using the core clock, temporarily configure it to\n             * use the core clock.  This configuration forces the SysTick to load\n             * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next\n             * cycle of the other clock.  Then portNVIC_SYSTICK_LOAD_REG is ready\n             * to receive the standard value immediately. */\n            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n            portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n            #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )\n            {\n                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n            }\n            #else\n            {\n                /* The temporary usage of the core clock has served its purpose,\n                 * as described above.  Resume usage of the other clock. */\n                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\n\n                if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n                {\n                    /* The partial tick period already ended.  Be sure the SysTick\n                     * counts it only once. */\n                    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;\n                }\n\n                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n            }\n            #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */\n\n            /* Step the tick to account for any tick periods that elapsed. */\n            vTaskStepTick( ulCompleteTickPeriods );\n\n            /* Exit with interrupts enabled. */\n            __enable_irq();\n        }\n    }\n\n#endif /* #if configUSE_TICKLESS_IDLE */\n\n/*-----------------------------------------------------------*/\n\n/*\n * Setup the SysTick timer to generate the tick interrupts at the required\n * frequency.\n */\n#if ( configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0 )\n\n    __weak void vPortSetupTimerInterrupt( void )\n    {\n        /* Calculate the constants required to configure the tick interrupt. */\n        #if ( configUSE_TICKLESS_IDLE == 1 )\n        {\n            ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );\n            xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;\n            ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\n        }\n        #endif /* configUSE_TICKLESS_IDLE */\n\n        /* Stop and clear the SysTick. */\n        portNVIC_SYSTICK_CTRL_REG = 0UL;\n        portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n        /* Configure SysTick to interrupt at the requested rate. */\n        portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\n        portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );\n    }\n\n#endif /* configOVERRIDE_DEFAULT_TICK_CONFIGURATION */\n/*-----------------------------------------------------------*/\n\n__asm uint32_t vPortGetIPSR( void )\n{\n/* *INDENT-OFF* */\n    PRESERVE8\n\n    mrs r0, ipsr\n    bx r14\n/* *INDENT-ON* */\n}\n/*-----------------------------------------------------------*/\n\n#if ( configASSERT_DEFINED == 1 )\n\n    void vPortValidateInterruptPriority( void )\n    {\n        uint32_t ulCurrentInterrupt;\n        uint8_t ucCurrentPriority;\n\n        /* Obtain the number of the currently executing interrupt. */\n        ulCurrentInterrupt = vPortGetIPSR();\n\n        /* Is the interrupt number a user defined interrupt? */\n        if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )\n        {\n            /* Look up the interrupt's priority. */\n            ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];\n\n            /* The following assertion will fail if a service routine (ISR) for\n             * an interrupt that has been assigned a priority above\n             * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\n             * function.  ISR safe FreeRTOS API functions must *only* be called\n             * from interrupts that have been assigned a priority at or below\n             * configMAX_SYSCALL_INTERRUPT_PRIORITY.\n             *\n             * Numerically low interrupt priority numbers represent logically high\n             * interrupt priorities, therefore the priority of the interrupt must\n             * be set to a value equal to or numerically *higher* than\n             * configMAX_SYSCALL_INTERRUPT_PRIORITY.\n             *\n             * Interrupts that\tuse the FreeRTOS API must not be left at their\n             * default priority of\tzero as that is the highest possible priority,\n             * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,\n             * and\ttherefore also guaranteed to be invalid.\n             *\n             * FreeRTOS maintains separate thread and ISR API functions to ensure\n             * interrupt entry is as fast and simple as possible.\n             *\n             * The following links provide detailed information:\n             * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html\n             * https://www.FreeRTOS.org/FAQHelp.html */\n            configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );\n        }\n\n        /* Priority grouping:  The interrupt controller (NVIC) allows the bits\n         * that define each interrupt's priority to be split between bits that\n         * define the interrupt's pre-emption priority bits and bits that define\n         * the interrupt's sub-priority.  For simplicity all bits must be defined\n         * to be pre-emption priority bits.  The following assertion will fail if\n         * this is not the case (if some bits represent a sub-priority).\n         *\n         * If the application only uses CMSIS libraries for interrupt\n         * configuration then the correct setting can be achieved on all Cortex-M\n         * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the\n         * scheduler.  Note however that some vendor specific peripheral libraries\n         * assume a non-zero priority group setting, in which cases using a value\n         * of zero will result in unpredictable behaviour. */\n        configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );\n    }\n\n#endif /* configASSERT_DEFINED */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/RVDS/ARM_CM3/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n\n#ifndef PORTMACRO_H\n#define PORTMACRO_H\n\n/* *INDENT-OFF* */\n#ifdef __cplusplus\n    extern \"C\" {\n#endif\n/* *INDENT-ON* */\n\n/*-----------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the\n * given hardware and compiler.\n *\n * These settings should not be altered.\n *-----------------------------------------------------------\n */\n\n/* Type definitions. */\n    #define portCHAR          char\n    #define portFLOAT         float\n    #define portDOUBLE        double\n    #define portLONG          long\n    #define portSHORT         short\n    #define portSTACK_TYPE    uint32_t\n    #define portBASE_TYPE     long\n\n    typedef portSTACK_TYPE   StackType_t;\n    typedef long             BaseType_t;\n    typedef unsigned long    UBaseType_t;\n\n    #if ( configUSE_16_BIT_TICKS == 1 )\n        typedef uint16_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffff\n    #else\n        typedef uint32_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL\n\n/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\n * not need to be guarded with a critical section. */\n        #define portTICK_TYPE_IS_ATOMIC    1\n    #endif\n/*-----------------------------------------------------------*/\n\n/* Architecture specifics. */\n    #define portSTACK_GROWTH          ( -1 )\n    #define portTICK_PERIOD_MS        ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\n    #define portBYTE_ALIGNMENT        8\n\n/* Constants used with memory barrier intrinsics. */\n    #define portSY_FULL_READ_WRITE    ( 15 )\n\n/*-----------------------------------------------------------*/\n\n/* Scheduler utilities. */\n    #define portYIELD()                                 \\\n    {                                                   \\\n        /* Set a PendSV to request a context switch. */ \\\n        portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \\\n                                                        \\\n        /* Barriers are normally not required but do ensure the code is completely \\\n         * within the specified behaviour for the architecture. */ \\\n        __dsb( portSY_FULL_READ_WRITE );                           \\\n        __isb( portSY_FULL_READ_WRITE );                           \\\n    }\n/*-----------------------------------------------------------*/\n\n    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )\n    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )\n    #define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 )\n    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )\n/*-----------------------------------------------------------*/\n\n/* Critical section management. */\n    extern void vPortEnterCritical( void );\n    extern void vPortExitCritical( void );\n\n    #define portDISABLE_INTERRUPTS()                  vPortRaiseBASEPRI()\n    #define portENABLE_INTERRUPTS()                   vPortSetBASEPRI( 0 )\n    #define portENTER_CRITICAL()                      vPortEnterCritical()\n    #define portEXIT_CRITICAL()                       vPortExitCritical()\n    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulPortRaiseBASEPRI()\n    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vPortSetBASEPRI( x )\n\n/*-----------------------------------------------------------*/\n\n/* Tickless idle/low power functionality. */\n    #ifndef portSUPPRESS_TICKS_AND_SLEEP\n        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );\n        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )\n    #endif\n/*-----------------------------------------------------------*/\n\n/* Port specific optimisations. */\n    #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION\n        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1\n    #endif\n\n    #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1\n\n/* Check the configuration. */\n        #if ( configMAX_PRIORITIES > 32 )\n            #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.\n        #endif\n\n/* Store/clear the ready priorities in a bit map. */\n        #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )\n        #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )\n\n/*-----------------------------------------------------------*/\n\n        #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ( uint32_t ) __clz( ( uxReadyPriorities ) ) )\n\n    #endif /* taskRECORD_READY_PRIORITY */\n/*-----------------------------------------------------------*/\n\n/* Task function macros as described on the FreeRTOS.org WEB site.  These are\n * not necessary for to use this port.  They are defined so the common demo files\n * (which build with all the ports) will build. */\n    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )\n    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )\n/*-----------------------------------------------------------*/\n\n    #ifdef configASSERT\n        void vPortValidateInterruptPriority( void );\n        #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()\n    #endif\n\n/* portNOP() is not required by this port. */\n    #define portNOP()\n\n    #define portINLINE              __inline\n\n    #ifndef portFORCE_INLINE\n        #define portFORCE_INLINE    __forceinline\n    #endif\n\n/*-----------------------------------------------------------*/\n\n    static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI )\n    {\n        __asm\n        {\n            /* Barrier instructions are not used as this function is only used to\n             * lower the BASEPRI value. */\n/* *INDENT-OFF* */\n            msr basepri, ulBASEPRI\n/* *INDENT-ON* */\n        }\n    }\n/*-----------------------------------------------------------*/\n\n    static portFORCE_INLINE void vPortRaiseBASEPRI( void )\n    {\n        uint32_t ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;\n\n        __asm\n        {\n            /* Set BASEPRI to the max syscall priority to effect a critical\n             * section. */\n/* *INDENT-OFF* */\n            msr basepri, ulNewBASEPRI\n            dsb\n            isb\n/* *INDENT-ON* */\n        }\n    }\n/*-----------------------------------------------------------*/\n\n    static portFORCE_INLINE void vPortClearBASEPRIFromISR( void )\n    {\n        __asm\n        {\n            /* Set BASEPRI to 0 so no interrupts are masked.  This function is only\n             * used to lower the mask in an interrupt, so memory barriers are not\n             * used. */\n/* *INDENT-OFF* */\n            msr basepri, # 0\n/* *INDENT-ON* */\n        }\n    }\n/*-----------------------------------------------------------*/\n\n    static portFORCE_INLINE uint32_t ulPortRaiseBASEPRI( void )\n    {\n        uint32_t ulReturn, ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;\n\n        __asm\n        {\n            /* Set BASEPRI to the max syscall priority to effect a critical\n             * section. */\n/* *INDENT-OFF* */\n            mrs ulReturn, basepri\n            msr basepri, ulNewBASEPRI\n            dsb\n            isb\n/* *INDENT-ON* */\n        }\n\n        return ulReturn;\n    }\n/*-----------------------------------------------------------*/\n\n    static portFORCE_INLINE BaseType_t xPortIsInsideInterrupt( void )\n    {\n        uint32_t ulCurrentInterrupt;\n        BaseType_t xReturn;\n\n        /* Obtain the number of the currently executing interrupt. */\n        __asm\n        {\n/* *INDENT-OFF* */\n            mrs ulCurrentInterrupt, ipsr\n/* *INDENT-ON* */\n        }\n\n        if( ulCurrentInterrupt == 0 )\n        {\n            xReturn = pdFALSE;\n        }\n        else\n        {\n            xReturn = pdTRUE;\n        }\n\n        return xReturn;\n    }\n\n\n/* *INDENT-OFF* */\n#ifdef __cplusplus\n    }\n#endif\n/* *INDENT-ON* */\n\n#endif /* PORTMACRO_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/RVDS/ARM_CM4F/port.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/*-----------------------------------------------------------\n* Implementation of functions defined in portable.h for the ARM CM4F port.\n*----------------------------------------------------------*/\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n#ifndef __TARGET_FPU_VFP\n    #error This port can only be used when the project options are configured to enable hardware floating point support.\n#endif\n\n#if configMAX_SYSCALL_INTERRUPT_PRIORITY == 0\n    #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\n#endif\n\n/* Legacy macro for backward compatibility only.  This macro used to be used to\n * replace the function that configures the clock used to generate the tick\n * interrupt (prvSetupTimerInterrupt()), but now the function is declared weak so\n * the application writer can override it by simply defining a function of the\n * same name (vApplicationSetupTickInterrupt()). */\n#ifndef configOVERRIDE_DEFAULT_TICK_CONFIGURATION\n    #define configOVERRIDE_DEFAULT_TICK_CONFIGURATION    0\n#endif\n\n/* Constants required to manipulate the core.  Registers first... */\n#define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )\n#define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )\n#define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )\n#define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )\n/* ...then bits in the registers. */\n#define portNVIC_SYSTICK_CLK_BIT              ( 1UL << 2UL )\n#define portNVIC_SYSTICK_INT_BIT              ( 1UL << 1UL )\n#define portNVIC_SYSTICK_ENABLE_BIT           ( 1UL << 0UL )\n#define portNVIC_SYSTICK_COUNT_FLAG_BIT       ( 1UL << 16UL )\n#define portNVIC_PENDSVCLEAR_BIT              ( 1UL << 27UL )\n#define portNVIC_PEND_SYSTICK_SET_BIT         ( 1UL << 26UL )\n#define portNVIC_PEND_SYSTICK_CLEAR_BIT       ( 1UL << 25UL )\n\n/* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7\n * r0p1 port. */\n#define portCPUID                             ( *( ( volatile uint32_t * ) 0xE000ed00 ) )\n#define portCORTEX_M7_r0p1_ID                 ( 0x410FC271UL )\n#define portCORTEX_M7_r0p0_ID                 ( 0x410FC270UL )\n\n#define portNVIC_PENDSV_PRI                   ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\n#define portNVIC_SYSTICK_PRI                  ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\n\n/* Constants required to check the validity of an interrupt priority. */\n#define portFIRST_USER_INTERRUPT_NUMBER       ( 16 )\n#define portNVIC_IP_REGISTERS_OFFSET_16       ( 0xE000E3F0 )\n#define portAIRCR_REG                         ( *( ( volatile uint32_t * ) 0xE000ED0C ) )\n#define portMAX_8_BIT_VALUE                   ( ( uint8_t ) 0xff )\n#define portTOP_BIT_OF_BYTE                   ( ( uint8_t ) 0x80 )\n#define portMAX_PRIGROUP_BITS                 ( ( uint8_t ) 7 )\n#define portPRIORITY_GROUP_MASK               ( 0x07UL << 8UL )\n#define portPRIGROUP_SHIFT                    ( 8UL )\n\n/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */\n#define portVECTACTIVE_MASK                   ( 0xFFUL )\n\n/* Constants required to manipulate the VFP. */\n#define portFPCCR                             ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */\n#define portASPEN_AND_LSPEN_BITS              ( 0x3UL << 30UL )\n\n/* Constants required to set up the initial stack. */\n#define portINITIAL_XPSR                      ( 0x01000000 )\n#define portINITIAL_EXC_RETURN                ( 0xfffffffd )\n\n/* The systick is a 24-bit counter. */\n#define portMAX_24_BIT_NUMBER                 ( 0xffffffUL )\n\n/* A fiddle factor to estimate the number of SysTick counts that would have\n * occurred while the SysTick counter is stopped during tickless idle\n * calculations. */\n#define portMISSED_COUNTS_FACTOR              ( 94UL )\n\n/* For strict compliance with the Cortex-M spec the task start address should\n * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */\n#define portSTART_ADDRESS_MASK                ( ( StackType_t ) 0xfffffffeUL )\n\n/* Let the user override the default SysTick clock rate.  If defined by the\n * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the\n * configuration register. */\n#ifndef configSYSTICK_CLOCK_HZ\n    #define configSYSTICK_CLOCK_HZ             ( configCPU_CLOCK_HZ )\n    /* Ensure the SysTick is clocked at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( portNVIC_SYSTICK_CLK_BIT )\n#else\n    /* Select the option to clock SysTick not at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( 0 )\n#endif\n\n/*\n * Setup the timer to generate the tick interrupts.  The implementation in this\n * file is weak to allow application writers to change the timer used to\n * generate the tick interrupt.\n */\nvoid vPortSetupTimerInterrupt( void );\n\n/*\n * Exception handlers.\n */\nvoid xPortPendSVHandler( void );\nvoid xPortSysTickHandler( void );\nvoid vPortSVCHandler( void );\n\n/*\n * Start first task is a separate function so it can be tested in isolation.\n */\nstatic void prvStartFirstTask( void );\n\n/*\n * Functions defined in portasm.s to enable the VFP.\n */\nstatic void prvEnableVFP( void );\n\n/*\n * Used to catch tasks that attempt to return from their implementing function.\n */\nstatic void prvTaskExitError( void );\n\n/*-----------------------------------------------------------*/\n\n/* Each task maintains its own interrupt status in the critical nesting\n * variable. */\nstatic UBaseType_t uxCriticalNesting = 0xaaaaaaaa;\n\n/*\n * The number of SysTick increments that make up one tick period.\n */\n#if ( configUSE_TICKLESS_IDLE == 1 )\n    static uint32_t ulTimerCountsForOneTick = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n\n/*\n * The maximum number of tick periods that can be suppressed is limited by the\n * 24 bit resolution of the SysTick timer.\n */\n#if ( configUSE_TICKLESS_IDLE == 1 )\n    static uint32_t xMaximumPossibleSuppressedTicks = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n\n/*\n * Compensate for the CPU cycles that pass while the SysTick is stopped (low\n * power functionality only.\n */\n#if ( configUSE_TICKLESS_IDLE == 1 )\n    static uint32_t ulStoppedTimerCompensation = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n\n/*\n * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure\n * FreeRTOS API functions are not called from interrupts that have been assigned\n * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.\n */\n#if ( configASSERT_DEFINED == 1 )\n    static uint8_t ucMaxSysCallPriority = 0;\n    static uint32_t ulMaxPRIGROUPValue = 0;\n    static const volatile uint8_t * const pcInterruptPriorityRegisters = ( uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;\n#endif /* configASSERT_DEFINED */\n\n/*-----------------------------------------------------------*/\n\n/*\n * See header file for description.\n */\nStackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,\n                                     TaskFunction_t pxCode,\n                                     void * pvParameters )\n{\n    /* Simulate the stack frame as it would be created by a context switch\n     * interrupt. */\n\n    /* Offset added to account for the way the MCU uses the stack on entry/exit\n     * of interrupts, and to ensure alignment. */\n    pxTopOfStack--;\n\n    *pxTopOfStack = portINITIAL_XPSR;                                    /* xPSR */\n    pxTopOfStack--;\n    *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */\n    pxTopOfStack--;\n    *pxTopOfStack = ( StackType_t ) prvTaskExitError;                    /* LR */\n\n    /* Save code space by skipping register initialisation. */\n    pxTopOfStack -= 5;                            /* R12, R3, R2 and R1. */\n    *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\n\n    /* A save method is being used that requires each task to maintain its\n     * own exec return value. */\n    pxTopOfStack--;\n    *pxTopOfStack = portINITIAL_EXC_RETURN;\n\n    pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */\n\n    return pxTopOfStack;\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvTaskExitError( void )\n{\n    /* A function that implements a task must not exit or attempt to return to\n     * its caller as there is nothing to return to.  If a task wants to exit it\n     * should instead call vTaskDelete( NULL ).\n     *\n     * Artificially force an assert() to be triggered if configASSERT() is\n     * defined, then stop here so application writers can catch the error. */\n    configASSERT( uxCriticalNesting == ~0UL );\n    portDISABLE_INTERRUPTS();\n\n    for( ; ; )\n    {\n    }\n}\n/*-----------------------------------------------------------*/\n\n__asm void vPortSVCHandler( void )\n{\n/* *INDENT-OFF* */\n    PRESERVE8\n\n    /* Get the location of the current TCB. */\n    ldr r3, =pxCurrentTCB\n    ldr r1, [ r3 ]\n    ldr r0, [ r1 ]\n    /* Pop the core registers. */\n    ldmia r0!, {r4-r11,r14}\n    msr psp, r0\n    isb\n    mov r0, #0\n    msr basepri, r0\n    bx r14\n/* *INDENT-ON* */\n}\n/*-----------------------------------------------------------*/\n\n__asm void prvStartFirstTask( void )\n{\n/* *INDENT-OFF* */\n    PRESERVE8\n\n    /* Use the NVIC offset register to locate the stack. */\n    ldr r0, =0xE000ED08\n    ldr r0, [ r0 ]\n    ldr r0, [ r0 ]\n    /* Set the msp back to the start of the stack. */\n    msr msp, r0\n\n    /* Clear the bit that indicates the FPU is in use in case the FPU was used\n     * before the scheduler was started - which would otherwise result in the\n     * unnecessary leaving of space in the SVC stack for lazy saving of FPU\n     * registers. */\n    mov r0, #0\n    msr control, r0\n    /* Globally enable interrupts. */\n    cpsie i\n    cpsie f\n    dsb\n    isb\n    /* Call SVC to start the first task. */\n    svc 0\n    nop\n    nop\n/* *INDENT-ON* */\n}\n/*-----------------------------------------------------------*/\n\n__asm void prvEnableVFP( void )\n{\n/* *INDENT-OFF* */\n    PRESERVE8\n\n    /* The FPU enable bits are in the CPACR. */\n    ldr.w r0, =0xE000ED88\n    ldr r1, [ r0 ]\n\n    /* Enable CP10 and CP11 coprocessors, then save back. */\n    orr r1, r1, #( 0xf << 20 )\n    str r1, [ r0 ]\n    bx r14\n    nop\n/* *INDENT-ON* */\n}\n/*-----------------------------------------------------------*/\n\n/*\n * See header file for description.\n */\nBaseType_t xPortStartScheduler( void )\n{\n    /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.\n     * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\n    configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );\n\n    /* This port can be used on all revisions of the Cortex-M7 core other than\n     * the r0p1 parts.  r0p1 parts should use the port from the\n     * /source/portable/GCC/ARM_CM7/r0p1 directory. */\n    configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );\n    configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );\n\n    #if ( configASSERT_DEFINED == 1 )\n    {\n        volatile uint32_t ulOriginalPriority;\n        volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\n        volatile uint8_t ucMaxPriorityValue;\n\n        /* Determine the maximum priority from which ISR safe FreeRTOS API\n         * functions can be called.  ISR safe functions are those that end in\n         * \"FromISR\".  FreeRTOS maintains separate thread and ISR API functions to\n         * ensure interrupt entry is as fast and simple as possible.\n         *\n         * Save the interrupt priority value that is about to be clobbered. */\n        ulOriginalPriority = *pucFirstUserPriorityRegister;\n\n        /* Determine the number of priority bits available.  First write to all\n         * possible bits. */\n        *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\n\n        /* Read the value back to see how many bits stuck. */\n        ucMaxPriorityValue = *pucFirstUserPriorityRegister;\n\n        /* The kernel interrupt priority should be set to the lowest\n         * priority. */\n        configASSERT( ucMaxPriorityValue == ( configKERNEL_INTERRUPT_PRIORITY & ucMaxPriorityValue ) );\n\n        /* Use the same mask on the maximum system call priority. */\n        ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;\n\n        /* Calculate the maximum acceptable priority group value for the number\n         * of bits read back. */\n        ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;\n\n        while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )\n        {\n            ulMaxPRIGROUPValue--;\n            ucMaxPriorityValue <<= ( uint8_t ) 0x01;\n        }\n\n        #ifdef __NVIC_PRIO_BITS\n        {\n            /* Check the CMSIS configuration that defines the number of\n             * priority bits matches the number of priority bits actually queried\n             * from the hardware. */\n            configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );\n        }\n        #endif\n\n        #ifdef configPRIO_BITS\n        {\n            /* Check the FreeRTOS configuration that defines the number of\n             * priority bits matches the number of priority bits actually queried\n             * from the hardware. */\n            configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );\n        }\n        #endif\n\n        /* Shift the priority group value back to its position within the AIRCR\n         * register. */\n        ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;\n        ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;\n\n        /* Restore the clobbered interrupt priority register to its original\n         * value. */\n        *pucFirstUserPriorityRegister = ulOriginalPriority;\n    }\n    #endif /* configASSERT_DEFINED */\n\n    /* Make PendSV and SysTick the lowest priority interrupts. */\n    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;\n    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;\n\n    /* Start the timer that generates the tick ISR.  Interrupts are disabled\n     * here already. */\n    vPortSetupTimerInterrupt();\n\n    /* Initialise the critical nesting count ready for the first task. */\n    uxCriticalNesting = 0;\n\n    /* Ensure the VFP is enabled - it should be anyway. */\n    prvEnableVFP();\n\n    /* Lazy save always. */\n    *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;\n\n    /* Start the first task. */\n    prvStartFirstTask();\n\n    /* Should not get here! */\n    return 0;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEndScheduler( void )\n{\n    /* Not implemented in ports where there is nothing to return to.\n     * Artificially force an assert. */\n    configASSERT( uxCriticalNesting == 1000UL );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEnterCritical( void )\n{\n    portDISABLE_INTERRUPTS();\n    uxCriticalNesting++;\n\n    /* This is not the interrupt safe version of the enter critical function so\n     * assert() if it is being called from an interrupt context.  Only API\n     * functions that end in \"FromISR\" can be used in an interrupt.  Only assert if\n     * the critical nesting count is 1 to protect against recursive calls if the\n     * assert function also uses a critical section. */\n    if( uxCriticalNesting == 1 )\n    {\n        configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );\n    }\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortExitCritical( void )\n{\n    configASSERT( uxCriticalNesting );\n    uxCriticalNesting--;\n\n    if( uxCriticalNesting == 0 )\n    {\n        portENABLE_INTERRUPTS();\n    }\n}\n/*-----------------------------------------------------------*/\n\n__asm void xPortPendSVHandler( void )\n{\n    extern uxCriticalNesting;\n    extern pxCurrentTCB;\n    extern vTaskSwitchContext;\n\n/* *INDENT-OFF* */\n    PRESERVE8\n\n    mrs r0, psp\n    isb\n    /* Get the location of the current TCB. */\n    ldr r3, =pxCurrentTCB\n    ldr r2, [ r3 ]\n\n    /* Is the task using the FPU context?  If so, push high vfp registers. */\n    tst r14, #0x10\n    it eq\n    vstmdbeq r0!, {s16-s31}\n\n    /* Save the core registers. */\n    stmdb r0!, {r4-r11, r14}\n\n    /* Save the new top of stack into the first member of the TCB. */\n    str r0, [ r2 ]\n\n    stmdb sp!, {r0, r3}\n    mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY\n    msr basepri, r0\n    dsb\n    isb\n    bl vTaskSwitchContext\n    mov r0, #0\n    msr basepri, r0\n    ldmia sp!, {r0, r3}\n\n    /* The first item in pxCurrentTCB is the task top of stack. */\n    ldr r1, [ r3 ]\n    ldr r0, [ r1 ]\n\n    /* Pop the core registers. */\n    ldmia r0!, {r4-r11, r14}\n\n    /* Is the task using the FPU context?  If so, pop the high vfp registers\n     * too. */\n    tst r14, #0x10\n    it eq\n    vldmiaeq r0!, {s16-s31}\n\n    msr psp, r0\n    isb\n    #ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata */\n        #if WORKAROUND_PMU_CM001 == 1\n            push { r14 }\n            pop { pc }\n            nop\n        #endif\n    #endif\n\n    bx r14\n/* *INDENT-ON* */\n}\n/*-----------------------------------------------------------*/\n\nvoid xPortSysTickHandler( void )\n{\n    /* The SysTick runs at the lowest interrupt priority, so when this interrupt\n     * executes all interrupts must be unmasked.  There is therefore no need to\n     * save and then restore the interrupt mask value as its value is already\n     * known - therefore the slightly faster vPortRaiseBASEPRI() function is used\n     * in place of portSET_INTERRUPT_MASK_FROM_ISR(). */\n    vPortRaiseBASEPRI();\n    {\n        /* Increment the RTOS tick. */\n        if( xTaskIncrementTick() != pdFALSE )\n        {\n            /* A context switch is required.  Context switching is performed in\n             * the PendSV interrupt.  Pend the PendSV interrupt. */\n            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\n        }\n    }\n\n    vPortClearBASEPRIFromISR();\n}\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TICKLESS_IDLE == 1 )\n\n    __weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )\n    {\n        uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;\n        TickType_t xModifiableIdleTime;\n\n        /* Make sure the SysTick reload value does not overflow the counter. */\n        if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\n        {\n            xExpectedIdleTime = xMaximumPossibleSuppressedTicks;\n        }\n\n        /* Enter a critical section but don't use the taskENTER_CRITICAL()\n         * method as that will mask interrupts that should exit sleep mode. */\n        __disable_irq();\n        __dsb( portSY_FULL_READ_WRITE );\n        __isb( portSY_FULL_READ_WRITE );\n\n        /* If a context switch is pending or a task is waiting for the scheduler\n         * to be unsuspended then abandon the low power entry. */\n        if( eTaskConfirmSleepModeStatus() == eAbortSleep )\n        {\n            /* Re-enable interrupts - see comments above the __disable_irq()\n             * call above. */\n            __enable_irq();\n        }\n        else\n        {\n            /* Stop the SysTick momentarily.  The time the SysTick is stopped for\n             * is accounted for as best it can be, but using the tickless mode will\n             * inevitably result in some tiny drift of the time maintained by the\n             * kernel with respect to calendar time. */\n            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );\n\n            /* Use the SysTick current-value register to determine the number of\n             * SysTick decrements remaining until the next tick interrupt.  If the\n             * current-value register is zero, then there are actually\n             * ulTimerCountsForOneTick decrements remaining, not zero, because the\n             * SysTick requests the interrupt when decrementing from 1 to 0. */\n            ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n\n            if( ulSysTickDecrementsLeft == 0 )\n            {\n                ulSysTickDecrementsLeft = ulTimerCountsForOneTick;\n            }\n\n            /* Calculate the reload value required to wait xExpectedIdleTime\n             * tick periods.  -1 is used because this code normally executes part\n             * way through the first tick period.  But if the SysTick IRQ is now\n             * pending, then clear the IRQ, suppressing the first tick, and correct\n             * the reload value to reflect that the second tick period is already\n             * underway.  The expected idle time is always at least two ticks. */\n            ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );\n\n            if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )\n            {\n                portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;\n                ulReloadValue -= ulTimerCountsForOneTick;\n            }\n\n            if( ulReloadValue > ulStoppedTimerCompensation )\n            {\n                ulReloadValue -= ulStoppedTimerCompensation;\n            }\n\n            /* Set the new reload value. */\n            portNVIC_SYSTICK_LOAD_REG = ulReloadValue;\n\n            /* Clear the SysTick count flag and set the count value back to\n             * zero. */\n            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n            /* Restart SysTick. */\n            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\n\n            /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can\n             * set its parameter to 0 to indicate that its implementation contains\n             * its own wait for interrupt or wait for event instruction, and so wfi\n             * should not be executed again.  However, the original expected idle\n             * time variable must remain unmodified, so a copy is taken. */\n            xModifiableIdleTime = xExpectedIdleTime;\n            configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\n\n            if( xModifiableIdleTime > 0 )\n            {\n                __dsb( portSY_FULL_READ_WRITE );\n                __wfi();\n                __isb( portSY_FULL_READ_WRITE );\n            }\n\n            configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\n\n            /* Re-enable interrupts to allow the interrupt that brought the MCU\n             * out of sleep mode to execute immediately.  See comments above\n             * the __disable_irq() call above. */\n            __enable_irq();\n            __dsb( portSY_FULL_READ_WRITE );\n            __isb( portSY_FULL_READ_WRITE );\n\n            /* Disable interrupts again because the clock is about to be stopped\n             * and interrupts that execute while the clock is stopped will increase\n             * any slippage between the time maintained by the RTOS and calendar\n             * time. */\n            __disable_irq();\n            __dsb( portSY_FULL_READ_WRITE );\n            __isb( portSY_FULL_READ_WRITE );\n\n            /* Disable the SysTick clock without reading the\n             * portNVIC_SYSTICK_CTRL_REG register to ensure the\n             * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,\n             * the time the SysTick is stopped for is accounted for as best it can\n             * be, but using the tickless mode will inevitably result in some tiny\n             * drift of the time maintained by the kernel with respect to calendar\n             * time*/\n            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );\n\n            /* Determine whether the SysTick has already counted to zero. */\n            if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n            {\n                uint32_t ulCalculatedLoadValue;\n\n                /* The tick interrupt ended the sleep (or is now pending), and\n                 * a new tick period has started.  Reset portNVIC_SYSTICK_LOAD_REG\n                 * with whatever remains of the new tick period. */\n                ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\n\n                /* Don't allow a tiny value, or values that have somehow\n                 * underflowed because the post sleep hook did something\n                 * that took too long or because the SysTick current-value register\n                 * is zero. */\n                if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )\n                {\n                    ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );\n                }\n\n                portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;\n\n                /* As the pending tick will be processed as soon as this\n                 * function exits, the tick value maintained by the tick is stepped\n                 * forward by one less than the time spent waiting. */\n                ulCompleteTickPeriods = xExpectedIdleTime - 1UL;\n            }\n            else\n            {\n                /* Something other than the tick interrupt ended the sleep. */\n\n                /* Use the SysTick current-value register to determine the\n                 * number of SysTick decrements remaining until the expected idle\n                 * time would have ended. */\n                ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n                #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )\n                {\n                    /* If the SysTick is not using the core clock, the current-\n                     * value register might still be zero here.  In that case, the\n                     * SysTick didn't load from the reload register, and there are\n                     * ulReloadValue decrements remaining in the expected idle\n                     * time, not zero. */\n                    if( ulSysTickDecrementsLeft == 0 )\n                    {\n                        ulSysTickDecrementsLeft = ulReloadValue;\n                    }\n                }\n                #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */\n\n                /* Work out how long the sleep lasted rounded to complete tick\n                 * periods (not the ulReload value which accounted for part\n                 * ticks). */\n                ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;\n\n                /* How many complete tick periods passed while the processor\n                 * was waiting? */\n                ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;\n\n                /* The reload value is set to whatever fraction of a single tick\n                 * period remains. */\n                portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;\n            }\n\n            /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,\n             * then set portNVIC_SYSTICK_LOAD_REG back to its standard value.  If\n             * the SysTick is not using the core clock, temporarily configure it to\n             * use the core clock.  This configuration forces the SysTick to load\n             * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next\n             * cycle of the other clock.  Then portNVIC_SYSTICK_LOAD_REG is ready\n             * to receive the standard value immediately. */\n            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n            portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n            #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )\n            {\n                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n            }\n            #else\n            {\n                /* The temporary usage of the core clock has served its purpose,\n                 * as described above.  Resume usage of the other clock. */\n                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\n\n                if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n                {\n                    /* The partial tick period already ended.  Be sure the SysTick\n                     * counts it only once. */\n                    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;\n                }\n\n                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n            }\n            #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */\n\n            /* Step the tick to account for any tick periods that elapsed. */\n            vTaskStepTick( ulCompleteTickPeriods );\n\n            /* Exit with interrupts enabled. */\n            __enable_irq();\n        }\n    }\n\n#endif /* #if configUSE_TICKLESS_IDLE */\n\n/*-----------------------------------------------------------*/\n\n/*\n * Setup the SysTick timer to generate the tick interrupts at the required\n * frequency.\n */\n#if ( configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0 )\n\n    __weak void vPortSetupTimerInterrupt( void )\n    {\n        /* Calculate the constants required to configure the tick interrupt. */\n        #if ( configUSE_TICKLESS_IDLE == 1 )\n        {\n            ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );\n            xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;\n            ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\n        }\n        #endif /* configUSE_TICKLESS_IDLE */\n\n        /* Stop and clear the SysTick. */\n        portNVIC_SYSTICK_CTRL_REG = 0UL;\n        portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n        /* Configure SysTick to interrupt at the requested rate. */\n        portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\n        portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );\n    }\n\n#endif /* configOVERRIDE_DEFAULT_TICK_CONFIGURATION */\n/*-----------------------------------------------------------*/\n\n__asm uint32_t vPortGetIPSR( void )\n{\n/* *INDENT-OFF* */\n    PRESERVE8\n\n    mrs r0, ipsr\n    bx r14\n/* *INDENT-ON* */\n}\n/*-----------------------------------------------------------*/\n\n#if ( configASSERT_DEFINED == 1 )\n\n    void vPortValidateInterruptPriority( void )\n    {\n        uint32_t ulCurrentInterrupt;\n        uint8_t ucCurrentPriority;\n\n        /* Obtain the number of the currently executing interrupt. */\n        ulCurrentInterrupt = vPortGetIPSR();\n\n        /* Is the interrupt number a user defined interrupt? */\n        if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )\n        {\n            /* Look up the interrupt's priority. */\n            ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];\n\n            /* The following assertion will fail if a service routine (ISR) for\n             * an interrupt that has been assigned a priority above\n             * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\n             * function.  ISR safe FreeRTOS API functions must *only* be called\n             * from interrupts that have been assigned a priority at or below\n             * configMAX_SYSCALL_INTERRUPT_PRIORITY.\n             *\n             * Numerically low interrupt priority numbers represent logically high\n             * interrupt priorities, therefore the priority of the interrupt must\n             * be set to a value equal to or numerically *higher* than\n             * configMAX_SYSCALL_INTERRUPT_PRIORITY.\n             *\n             * Interrupts that use the FreeRTOS API must not be left at their\n             * default priority of zero as that is the highest possible priority,\n             * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,\n             * and therefore also guaranteed to be invalid.\n             *\n             * FreeRTOS maintains separate thread and ISR API functions to ensure\n             * interrupt entry is as fast and simple as possible.\n             *\n             * The following links provide detailed information:\n             * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html\n             * https://www.FreeRTOS.org/FAQHelp.html */\n            configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );\n        }\n\n        /* Priority grouping:  The interrupt controller (NVIC) allows the bits\n         * that define each interrupt's priority to be split between bits that\n         * define the interrupt's pre-emption priority bits and bits that define\n         * the interrupt's sub-priority.  For simplicity all bits must be defined\n         * to be pre-emption priority bits.  The following assertion will fail if\n         * this is not the case (if some bits represent a sub-priority).\n         *\n         * If the application only uses CMSIS libraries for interrupt\n         * configuration then the correct setting can be achieved on all Cortex-M\n         * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the\n         * scheduler.  Note however that some vendor specific peripheral libraries\n         * assume a non-zero priority group setting, in which cases using a value\n         * of zero will result in unpredictable behaviour. */\n        configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );\n    }\n\n#endif /* configASSERT_DEFINED */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/RVDS/ARM_CM4F/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n\n#ifndef PORTMACRO_H\n#define PORTMACRO_H\n\n/* *INDENT-OFF* */\n#ifdef __cplusplus\n    extern \"C\" {\n#endif\n/* *INDENT-ON* */\n\n/*-----------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the\n * given hardware and compiler.\n *\n * These settings should not be altered.\n *-----------------------------------------------------------\n */\n\n/* Type definitions. */\n    #define portCHAR          char\n    #define portFLOAT         float\n    #define portDOUBLE        double\n    #define portLONG          long\n    #define portSHORT         short\n    #define portSTACK_TYPE    uint32_t\n    #define portBASE_TYPE     long\n\n    typedef portSTACK_TYPE   StackType_t;\n    typedef long             BaseType_t;\n    typedef unsigned long    UBaseType_t;\n\n    #if ( configUSE_16_BIT_TICKS == 1 )\n        typedef uint16_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffff\n    #else\n        typedef uint32_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL\n\n/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\n * not need to be guarded with a critical section. */\n        #define portTICK_TYPE_IS_ATOMIC    1\n    #endif\n/*-----------------------------------------------------------*/\n\n/* Architecture specifics. */\n    #define portSTACK_GROWTH          ( -1 )\n    #define portTICK_PERIOD_MS        ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\n    #define portBYTE_ALIGNMENT        8\n\n/* Constants used with memory barrier intrinsics. */\n    #define portSY_FULL_READ_WRITE    ( 15 )\n\n/*-----------------------------------------------------------*/\n\n/* Scheduler utilities. */\n    #define portYIELD()                                 \\\n    {                                                   \\\n        /* Set a PendSV to request a context switch. */ \\\n        portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \\\n                                                        \\\n        /* Barriers are normally not required but do ensure the code is completely \\\n         * within the specified behaviour for the architecture. */ \\\n        __dsb( portSY_FULL_READ_WRITE );                           \\\n        __isb( portSY_FULL_READ_WRITE );                           \\\n    }\n/*-----------------------------------------------------------*/\n\n    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )\n    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )\n    #define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 )\n    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )\n/*-----------------------------------------------------------*/\n\n/* Critical section management. */\n    extern void vPortEnterCritical( void );\n    extern void vPortExitCritical( void );\n\n    #define portDISABLE_INTERRUPTS()                  vPortRaiseBASEPRI()\n    #define portENABLE_INTERRUPTS()                   vPortSetBASEPRI( 0 )\n    #define portENTER_CRITICAL()                      vPortEnterCritical()\n    #define portEXIT_CRITICAL()                       vPortExitCritical()\n    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulPortRaiseBASEPRI()\n    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vPortSetBASEPRI( x )\n\n/*-----------------------------------------------------------*/\n\n/* Tickless idle/low power functionality. */\n    #ifndef portSUPPRESS_TICKS_AND_SLEEP\n        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );\n        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )\n    #endif\n/*-----------------------------------------------------------*/\n\n/* Port specific optimisations. */\n    #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION\n        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1\n    #endif\n\n    #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1\n\n/* Check the configuration. */\n        #if ( configMAX_PRIORITIES > 32 )\n            #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.\n        #endif\n\n/* Store/clear the ready priorities in a bit map. */\n        #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )\n        #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )\n\n/*-----------------------------------------------------------*/\n\n        #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ( uint32_t ) __clz( ( uxReadyPriorities ) ) )\n\n    #endif /* taskRECORD_READY_PRIORITY */\n/*-----------------------------------------------------------*/\n\n/* Task function macros as described on the FreeRTOS.org WEB site.  These are\n * not necessary for to use this port.  They are defined so the common demo files\n * (which build with all the ports) will build. */\n    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )\n    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )\n/*-----------------------------------------------------------*/\n\n    #ifdef configASSERT\n        void vPortValidateInterruptPriority( void );\n        #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()\n    #endif\n\n/* portNOP() is not required by this port. */\n    #define portNOP()\n\n    #define portINLINE              __inline\n\n    #ifndef portFORCE_INLINE\n        #define portFORCE_INLINE    __forceinline\n    #endif\n\n/*-----------------------------------------------------------*/\n\n    static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI )\n    {\n        __asm\n        {\n            /* Barrier instructions are not used as this function is only used to\n             * lower the BASEPRI value. */\n/* *INDENT-OFF* */\n            msr basepri, ulBASEPRI\n/* *INDENT-ON* */\n        }\n    }\n/*-----------------------------------------------------------*/\n\n    static portFORCE_INLINE void vPortRaiseBASEPRI( void )\n    {\n        uint32_t ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;\n\n        __asm\n        {\n            /* Set BASEPRI to the max syscall priority to effect a critical\n             * section. */\n/* *INDENT-OFF* */\n            msr basepri, ulNewBASEPRI\n            dsb\n            isb\n/* *INDENT-ON* */\n        }\n    }\n/*-----------------------------------------------------------*/\n\n    static portFORCE_INLINE void vPortClearBASEPRIFromISR( void )\n    {\n        __asm\n        {\n            /* Set BASEPRI to 0 so no interrupts are masked.  This function is only\n             * used to lower the mask in an interrupt, so memory barriers are not\n             * used. */\n/* *INDENT-OFF* */\n            msr basepri, # 0\n/* *INDENT-ON* */\n        }\n    }\n/*-----------------------------------------------------------*/\n\n    static portFORCE_INLINE uint32_t ulPortRaiseBASEPRI( void )\n    {\n        uint32_t ulReturn, ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;\n\n        __asm\n        {\n            /* Set BASEPRI to the max syscall priority to effect a critical\n             * section. */\n/* *INDENT-OFF* */\n            mrs ulReturn, basepri\n            msr basepri, ulNewBASEPRI\n            dsb\n            isb\n/* *INDENT-ON* */\n        }\n\n        return ulReturn;\n    }\n/*-----------------------------------------------------------*/\n\n    static portFORCE_INLINE BaseType_t xPortIsInsideInterrupt( void )\n    {\n        uint32_t ulCurrentInterrupt;\n        BaseType_t xReturn;\n\n        /* Obtain the number of the currently executing interrupt. */\n        __asm\n        {\n/* *INDENT-OFF* */\n            mrs ulCurrentInterrupt, ipsr\n/* *INDENT-ON* */\n        }\n\n        if( ulCurrentInterrupt == 0 )\n        {\n            xReturn = pdFALSE;\n        }\n        else\n        {\n            xReturn = pdTRUE;\n        }\n\n        return xReturn;\n    }\n\n/* *INDENT-OFF* */\n#ifdef __cplusplus\n    }\n#endif\n/* *INDENT-ON* */\n\n#endif /* PORTMACRO_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/RVDS/ARM_CM4_MPU/port.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/*-----------------------------------------------------------\n* Implementation of functions defined in portable.h for the ARM CM4 MPU port.\n*----------------------------------------------------------*/\n\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\n * all the API functions to use the MPU wrappers.  That should only be done when\n * task.h is included from an application file. */\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n#ifndef __TARGET_FPU_VFP\n    #error This port can only be used when the project options are configured to enable hardware floating point support.\n#endif\n\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n#ifndef configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS\n    #warning \"configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS is not defined. We recommend defining it to 0 in FreeRTOSConfig.h for better security.\"\n    #define configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS    1\n#endif\n\n/* Constants required to access and manipulate the NVIC. */\n#define portNVIC_SYSTICK_CTRL_REG                 ( *( ( volatile uint32_t * ) 0xe000e010 ) )\n#define portNVIC_SYSTICK_LOAD_REG                 ( *( ( volatile uint32_t * ) 0xe000e014 ) )\n#define portNVIC_SYSTICK_CURRENT_VALUE_REG        ( *( ( volatile uint32_t * ) 0xe000e018 ) )\n#define portNVIC_SHPR3_REG                        ( *( ( volatile uint32_t * ) 0xe000ed20 ) )\n#define portNVIC_SHPR2_REG                        ( *( ( volatile uint32_t * ) 0xe000ed1c ) )\n#define portNVIC_SYS_CTRL_STATE_REG               ( *( ( volatile uint32_t * ) 0xe000ed24 ) )\n#define portNVIC_MEM_FAULT_ENABLE                 ( 1UL << 16UL )\n\n/* Constants used to detect Cortex-M7 r0p0 and r0p1 cores, and ensure\n * that a work around is active for errata 837070. */\n#define portCPUID                                 ( *( ( volatile uint32_t * ) 0xE000ed00 ) )\n#define portCORTEX_M7_r0p1_ID                     ( 0x410FC271UL )\n#define portCORTEX_M7_r0p0_ID                     ( 0x410FC270UL )\n\n/* Constants required to access and manipulate the MPU. */\n#define portMPU_TYPE_REG                          ( *( ( volatile uint32_t * ) 0xe000ed90 ) )\n#define portMPU_REGION_BASE_ADDRESS_REG           ( *( ( volatile uint32_t * ) 0xe000ed9C ) )\n#define portMPU_REGION_ATTRIBUTE_REG              ( *( ( volatile uint32_t * ) 0xe000edA0 ) )\n#define portMPU_CTRL_REG                          ( *( ( volatile uint32_t * ) 0xe000ed94 ) )\n#define portEXPECTED_MPU_TYPE_VALUE               ( configTOTAL_MPU_REGIONS << 8UL )\n#define portMPU_ENABLE                            ( 0x01UL )\n#define portMPU_BACKGROUND_ENABLE                 ( 1UL << 2UL )\n#define portPRIVILEGED_EXECUTION_START_ADDRESS    ( 0UL )\n#define portMPU_REGION_VALID                      ( 0x10UL )\n#define portMPU_REGION_ENABLE                     ( 0x01UL )\n#define portPERIPHERALS_START_ADDRESS             0x40000000UL\n#define portPERIPHERALS_END_ADDRESS               0x5FFFFFFFUL\n\n/* Constants required to access and manipulate the SysTick. */\n#define portNVIC_SYSTICK_CLK                      ( 0x00000004UL )\n#define portNVIC_SYSTICK_INT                      ( 0x00000002UL )\n#define portNVIC_SYSTICK_ENABLE                   ( 0x00000001UL )\n#define portNVIC_PENDSV_PRI                       ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\n#define portNVIC_SYSTICK_PRI                      ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\n#define portNVIC_SVC_PRI                          ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )\n\n/* Constants required to manipulate the VFP. */\n#define portFPCCR                                 ( ( volatile uint32_t * ) 0xe000ef34UL ) /* Floating point context control register. */\n#define portASPEN_AND_LSPEN_BITS                  ( 0x3UL << 30UL )\n\n/* Constants required to set up the initial stack. */\n#define portINITIAL_XPSR                          ( 0x01000000UL )\n#define portINITIAL_EXC_RETURN                    ( 0xfffffffdUL )\n#define portINITIAL_CONTROL_IF_UNPRIVILEGED       ( 0x03 )\n#define portINITIAL_CONTROL_IF_PRIVILEGED         ( 0x02 )\n\n/* Constants required to check the validity of an interrupt priority. */\n#define portFIRST_USER_INTERRUPT_NUMBER           ( 16 )\n#define portNVIC_IP_REGISTERS_OFFSET_16           ( 0xE000E3F0 )\n#define portAIRCR_REG                             ( *( ( volatile uint32_t * ) 0xE000ED0C ) )\n#define portMAX_8_BIT_VALUE                       ( ( uint8_t ) 0xff )\n#define portTOP_BIT_OF_BYTE                       ( ( uint8_t ) 0x80 )\n#define portMAX_PRIGROUP_BITS                     ( ( uint8_t ) 7 )\n#define portPRIORITY_GROUP_MASK                   ( 0x07UL << 8UL )\n#define portPRIGROUP_SHIFT                        ( 8UL )\n\n/* Offsets in the stack to the parameters when inside the SVC handler. */\n#define portOFFSET_TO_PC                          ( 6 )\n\n/* For strict compliance with the Cortex-M spec the task start address should\n * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */\n#define portSTART_ADDRESS_MASK                    ( ( StackType_t ) 0xfffffffeUL )\n\n/* Each task maintains its own interrupt status in the critical nesting\n * variable.  Note this is not saved as part of the task context as context\n * switches can only occur when uxCriticalNesting is zero. */\nstatic UBaseType_t uxCriticalNesting = 0xaaaaaaaa;\n\n/*\n * Setup the timer to generate the tick interrupts.\n */\nvoid vSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\n\n/*\n * Configure a number of standard MPU regions that are used by all tasks.\n */\nstatic void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\n\n/*\n * Start first task is a separate function so it can be tested in isolation.\n */\nstatic void prvStartFirstTask( void ) PRIVILEGED_FUNCTION;\n\n/*\n * Return the smallest MPU region size that a given number of bytes will fit\n * into.  The region size is returned as the value that should be programmed\n * into the region attribute register for that region.\n */\nstatic uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;\n\n/*\n * Standard FreeRTOS exception handlers.\n */\nvoid xPortPendSVHandler( void ) PRIVILEGED_FUNCTION;\nvoid xPortSysTickHandler( void ) PRIVILEGED_FUNCTION;\nvoid vPortSVCHandler( void ) PRIVILEGED_FUNCTION;\n\n/*\n * Starts the scheduler by restoring the context of the first task to run.\n */\nstatic void prvRestoreContextOfFirstTask( void ) PRIVILEGED_FUNCTION;\n\n/*\n * C portion of the SVC handler.  The SVC handler is split between an asm entry\n * and a C wrapper for simplicity of coding and maintenance.\n */\nvoid prvSVCHandler( uint32_t * pulRegisters ) __attribute__( ( used ) ) PRIVILEGED_FUNCTION;\n\n/*\n * Function to enable the VFP.\n */\nstatic void vPortEnableVFP( void );\n\n/*\n * Utility function.\n */\nstatic uint32_t prvPortGetIPSR( void );\n\n/*\n * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure\n * FreeRTOS API functions are not called from interrupts that have been assigned\n * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.\n */\n#if ( configASSERT_DEFINED == 1 )\n    static uint8_t ucMaxSysCallPriority = 0;\n    static uint32_t ulMaxPRIGROUPValue = 0;\n    static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;\n#endif /* configASSERT_DEFINED */\n\n/**\n * @brief Checks whether or not the processor is privileged.\n *\n * @return 1 if the processor is already privileged, 0 otherwise.\n */\nBaseType_t xIsPrivileged( void );\n\n/**\n * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\n * register.\n *\n * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.\n *  Bit[0] = 0 --> The processor is running privileged\n *  Bit[0] = 1 --> The processor is running unprivileged.\n */\nvoid vResetPrivilege( void );\n\n/**\n * @brief Enter critical section.\n */\n#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )\n    void vPortEnterCritical( void ) FREERTOS_SYSTEM_CALL;\n#else\n    void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;\n#endif\n\n/**\n * @brief Exit from critical section.\n */\n#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )\n    void vPortExitCritical( void ) FREERTOS_SYSTEM_CALL;\n#else\n    void vPortExitCritical( void ) PRIVILEGED_FUNCTION;\n#endif\n/*-----------------------------------------------------------*/\n\n/*\n * See header file for description.\n */\nStackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,\n                                     TaskFunction_t pxCode,\n                                     void * pvParameters,\n                                     BaseType_t xRunPrivileged )\n{\n    /* Simulate the stack frame as it would be created by a context switch\n     * interrupt. */\n    pxTopOfStack--;                                                      /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\n    *pxTopOfStack = portINITIAL_XPSR;                                    /* xPSR */\n    pxTopOfStack--;\n    *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */\n    pxTopOfStack--;\n    *pxTopOfStack = 0;                                                   /* LR */\n    pxTopOfStack -= 5;                                                   /* R12, R3, R2 and R1. */\n    *pxTopOfStack = ( StackType_t ) pvParameters;                        /* R0 */\n\n    /* A save method is being used that requires each task to maintain its\n     * own exec return value. */\n    pxTopOfStack--;\n    *pxTopOfStack = portINITIAL_EXC_RETURN;\n\n    pxTopOfStack -= 9; /* R11, R10, R9, R8, R7, R6, R5 and R4. */\n\n    if( xRunPrivileged == pdTRUE )\n    {\n        *pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED;\n    }\n    else\n    {\n        *pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED;\n    }\n\n    return pxTopOfStack;\n}\n/*-----------------------------------------------------------*/\n\nvoid prvSVCHandler( uint32_t * pulParam )\n{\n    uint8_t ucSVCNumber;\n    uint32_t ulReg, ulPC;\n\n    #if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )\n        extern uint32_t __syscalls_flash_start__;\n        extern uint32_t __syscalls_flash_end__;\n    #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */\n\n    /* The stack contains: r0, r1, r2, r3, r12, LR, PC and xPSR. The first\n     * argument (r0) is pulParam[ 0 ]. */\n    ulPC = pulParam[ portOFFSET_TO_PC ];\n    ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];\n\n    switch( ucSVCNumber )\n    {\n        case portSVC_START_SCHEDULER:\n            portNVIC_SHPR2_REG |= portNVIC_SVC_PRI;\n            prvRestoreContextOfFirstTask();\n            break;\n\n        case portSVC_YIELD:\n            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\n\n            /* Barriers are normally not required\n             * but do ensure the code is completely\n             * within the specified behaviour for the\n             * architecture. */\n            __asm volatile ( \"dsb\" );\n            __asm volatile ( \"isb\" );\n\n            break;\n\n            #if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )\n                case portSVC_RAISE_PRIVILEGE: /* Only raise the privilege, if the\n                                               * svc was raised from any of the\n                                               * system calls. */\n\n                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&\n                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )\n                    {\n                        __asm\n                        {\n/* *INDENT-OFF* */\n                            mrs ulReg, control /* Obtain current control value. */\n                            bic ulReg, # 1     /* Set privilege bit. */\n                            msr control, ulReg /* Write back new control value. */\n/* *INDENT-ON* */\n                        }\n                    }\n\n                    break;\n            #else /* if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */\n                case portSVC_RAISE_PRIVILEGE:\n                    __asm\n                    {\n/* *INDENT-OFF* */\n                        mrs ulReg, control /* Obtain current control value. */\n                        bic ulReg, # 1     /* Set privilege bit. */\n                        msr control, ulReg /* Write back new control value. */\n/* *INDENT-ON* */\n                    }\n                    break;\n                    #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */\n\n                default: /* Unknown SVC call. */\n                    break;\n    }\n}\n/*-----------------------------------------------------------*/\n\n__asm void vPortSVCHandler( void )\n{\n    extern prvSVCHandler\n\n/* *INDENT-OFF* */\n        PRESERVE8\n\n    /* Assumes psp was in use. */\n    #ifndef USE_PROCESS_STACK   /* Code should not be required if a main() is using the process stack. */\n        tst lr, # 4\n        ite eq\n        mrseq r0, msp\n        mrsne r0, psp\n    #else\n        mrs r0, psp\n    #endif\n\n    b prvSVCHandler\n/* *INDENT-ON* */\n}\n/*-----------------------------------------------------------*/\n\n__asm void prvRestoreContextOfFirstTask( void )\n{\n/* *INDENT-OFF* */\n    PRESERVE8\n\n    ldr r0, =0xE000ED08 /* Use the NVIC offset register to locate the stack. */\n    ldr r0, [ r0 ]\n    ldr r0, [ r0 ]\n    msr msp, r0              /* Set the msp back to the start of the stack. */\n    ldr r3, =pxCurrentTCB   /* Restore the context. */\n    ldr r1, [ r3 ]\n    ldr r0, [ r1 ]    /* The first item in the TCB is the task top of stack. */\n    add r1, r1, #4          /* Move onto the second item in the TCB... */\n\n    dmb               /* Complete outstanding transfers before disabling MPU. */\n    ldr r2, =0xe000ed94     /* MPU_CTRL register. */\n    ldr r3, [ r2 ] /* Read the value of MPU_CTRL. */\n    bic r3, r3, # 1          /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */\n    str r3, [ r2 ]           /* Disable MPU. */\n\n    ldr r2, =0xe000ed9c     /* Region Base Address register. */\n    ldmia r1 !, { r4 - r11 } /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */\n    stmia r2, { r4 - r11 }  /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */\n\n    #if ( configTOTAL_MPU_REGIONS == 16 )\n        ldmia r1 !, { r4 - r11 } /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */\n        stmia r2, { r4 - r11 } /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */\n        ldmia r1 !, { r4 - r11 } /* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */\n        stmia r2, { r4 - r11 }  /* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */\n    #endif /* configTOTAL_MPU_REGIONS == 16. */\n\n    ldr r2, =0xe000ed94     /* MPU_CTRL register. */\n    ldr r3, [ r2 ] /* Read the value of MPU_CTRL. */\n    orr r3, r3, #1          /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */\n    str r3, [ r2 ]           /* Enable MPU. */\n    dsb                      /* Force memory writes before continuing. */\n\n    ldmia r0 !, { r3 - r11, r14 } /* Pop the registers that are not automatically saved on exception entry. */\n    msr control, r3\n    msr psp, r0 /* Restore the task stack pointer. */\n    mov r0, #0\n    msr basepri, r0\n    bx r14\n    nop\n/* *INDENT-ON* */\n}\n/*-----------------------------------------------------------*/\n\n/*\n * See header file for description.\n */\nBaseType_t xPortStartScheduler( void )\n{\n    /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.\n     * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\n    configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );\n\n    /* Errata 837070 workaround must only be enabled on Cortex-M7 r0p0\n     * and r0p1 cores. */\n    #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )\n        configASSERT( ( portCPUID == portCORTEX_M7_r0p1_ID ) || ( portCPUID == portCORTEX_M7_r0p0_ID ) );\n    #else\n        /* When using this port on a Cortex-M7 r0p0 or r0p1 core, define\n         * configENABLE_ERRATA_837070_WORKAROUND to 1 in your\n         * FreeRTOSConfig.h. */\n        configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );\n        configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );\n    #endif\n\n    #if ( configASSERT_DEFINED == 1 )\n        {\n            volatile uint32_t ulOriginalPriority;\n            volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\n            volatile uint8_t ucMaxPriorityValue;\n\n            /* Determine the maximum priority from which ISR safe FreeRTOS API\n             * functions can be called.  ISR safe functions are those that end in\n             * \"FromISR\".  FreeRTOS maintains separate thread and ISR API functions to\n             * ensure interrupt entry is as fast and simple as possible.\n             *\n             * Save the interrupt priority value that is about to be clobbered. */\n            ulOriginalPriority = *pucFirstUserPriorityRegister;\n\n            /* Determine the number of priority bits available.  First write to all\n             * possible bits. */\n            *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\n\n            /* Read the value back to see how many bits stuck. */\n            ucMaxPriorityValue = *pucFirstUserPriorityRegister;\n\n            /* Use the same mask on the maximum system call priority. */\n            ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;\n\n            /* Calculate the maximum acceptable priority group value for the number\n             * of bits read back. */\n            ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;\n\n            while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )\n            {\n                ulMaxPRIGROUPValue--;\n                ucMaxPriorityValue <<= ( uint8_t ) 0x01;\n            }\n\n            #ifdef __NVIC_PRIO_BITS\n                {\n                    /* Check the CMSIS configuration that defines the number of\n                     * priority bits matches the number of priority bits actually queried\n                     * from the hardware. */\n                    configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );\n                }\n            #endif\n\n            #ifdef configPRIO_BITS\n                {\n                    /* Check the FreeRTOS configuration that defines the number of\n                     * priority bits matches the number of priority bits actually queried\n                     * from the hardware. */\n                    configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );\n                }\n            #endif\n\n            /* Shift the priority group value back to its position within the AIRCR\n             * register. */\n            ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;\n            ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;\n\n            /* Restore the clobbered interrupt priority register to its original\n             * value. */\n            *pucFirstUserPriorityRegister = ulOriginalPriority;\n        }\n    #endif /* configASSERT_DEFINED */\n\n    /* Make PendSV and SysTick the same priority as the kernel, and the SVC\n     * handler higher priority so it can be used to exit a critical section (where\n     * lower priorities are masked). */\n    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;\n    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;\n\n    /* Configure the regions in the MPU that are common to all tasks. */\n    prvSetupMPU();\n\n    /* Start the timer that generates the tick ISR.  Interrupts are disabled\n     * here already. */\n    vSetupTimerInterrupt();\n\n    /* Initialise the critical nesting count ready for the first task. */\n    uxCriticalNesting = 0;\n\n    /* Ensure the VFP is enabled - it should be anyway. */\n    vPortEnableVFP();\n\n    /* Lazy save always. */\n    *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;\n\n    /* Start the first task. */\n    prvStartFirstTask();\n\n    /* Should not get here! */\n    return 0;\n}\n/*-----------------------------------------------------------*/\n\n__asm void prvStartFirstTask( void )\n{\n/* *INDENT-OFF* */\n    PRESERVE8\n\n    /* Use the NVIC offset register to locate the stack. */\n    ldr r0, =0xE000ED08\n    ldr r0, [ r0 ]\n    ldr r0, [ r0 ]\n    /* Set the msp back to the start of the stack. */\n    msr msp, r0\n\n    /* Clear the bit that indicates the FPU is in use in case the FPU was used\n     * before the scheduler was started - which would otherwise result in the\n     * unnecessary leaving of space in the SVC stack for lazy saving of FPU\n     * registers. */\n    mov r0, #0\n    msr control, r0\n    /* Globally enable interrupts. */\n    cpsie i\n    cpsie f\n    dsb\n    isb\n    svc portSVC_START_SCHEDULER /* System call to start first task. */\n    nop\n    nop\n/* *INDENT-ON* */\n}\n\nvoid vPortEndScheduler( void )\n{\n    /* Not implemented in ports where there is nothing to return to.\n     * Artificially force an assert. */\n    configASSERT( uxCriticalNesting == 1000UL );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEnterCritical( void )\n{\n#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )\n    if( portIS_PRIVILEGED() == pdFALSE )\n    {\n        portRAISE_PRIVILEGE();\n        portMEMORY_BARRIER();\n\n        portDISABLE_INTERRUPTS();\n        uxCriticalNesting++;\n        portMEMORY_BARRIER();\n\n        portRESET_PRIVILEGE();\n        portMEMORY_BARRIER();\n    }\n    else\n    {\n        portDISABLE_INTERRUPTS();\n        uxCriticalNesting++;\n    }\n#else\n    portDISABLE_INTERRUPTS();\n    uxCriticalNesting++;\n#endif\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortExitCritical( void )\n{\n#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )\n    if( portIS_PRIVILEGED() == pdFALSE )\n    {\n        portRAISE_PRIVILEGE();\n        portMEMORY_BARRIER();\n\n        configASSERT( uxCriticalNesting );\n        uxCriticalNesting--;\n\n        if( uxCriticalNesting == 0 )\n        {\n            portENABLE_INTERRUPTS();\n        }\n        portMEMORY_BARRIER();\n\n        portRESET_PRIVILEGE();\n        portMEMORY_BARRIER();\n    }\n    else\n    {\n        configASSERT( uxCriticalNesting );\n        uxCriticalNesting--;\n\n        if( uxCriticalNesting == 0 )\n        {\n            portENABLE_INTERRUPTS();\n        }\n    }\n#else\n    configASSERT( uxCriticalNesting );\n    uxCriticalNesting--;\n\n    if( uxCriticalNesting == 0 )\n    {\n        portENABLE_INTERRUPTS();\n    }\n#endif\n}\n/*-----------------------------------------------------------*/\n\n__asm void xPortPendSVHandler( void )\n{\n    extern uxCriticalNesting;\n    extern pxCurrentTCB;\n    extern vTaskSwitchContext;\n\n/* *INDENT-OFF* */\n    PRESERVE8\n\n    mrs r0, psp\n\n    ldr r3, =pxCurrentTCB /* Get the location of the current TCB. */\n    ldr r2, [ r3 ]\n\n    tst r14, #0x10 /* Is the task using the FPU context?  If so, push high vfp registers. */\n    it eq\n    vstmdbeq r0 !, { s16 - s31 }\n\n    mrs r1, control\n    stmdb r0 !, { r1, r4 - r11, r14 }   /* Save the remaining registers. */\n    str r0, [ r2 ] /* Save the new top of stack into the first member of the TCB. */\n\n    stmdb sp !, { r0, r3 }\n    mov r0, # configMAX_SYSCALL_INTERRUPT_PRIORITY\n    #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )\n        cpsid i             /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */\n    #endif\n    msr basepri, r0\n    dsb\n    isb\n    #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )\n        cpsie i             /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */\n    #endif\n    bl vTaskSwitchContext\n    mov r0, #0\n    msr basepri, r0\n    ldmia sp !, { r0, r3 }\n    /* Restore the context. */\n    ldr r1, [ r3 ]\n    ldr r0, [ r1 ]           /* The first item in the TCB is the task top of stack. */\n    add r1, r1, #4          /* Move onto the second item in the TCB... */\n\n    dmb                      /* Complete outstanding transfers before disabling MPU. */\n    ldr r2, =0xe000ed94     /* MPU_CTRL register. */\n    ldr r3, [ r2 ] /* Read the value of MPU_CTRL. */\n    bic r3, r3, #1          /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */\n    str r3, [ r2 ]           /* Disable MPU. */\n\n    ldr r2, =0xe000ed9c     /* Region Base Address register. */\n    ldmia r1 !, { r4 - r11 } /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */\n    stmia r2, { r4 - r11 }   /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */\n\n    #if ( configTOTAL_MPU_REGIONS == 16 )\n        ldmia r1 !, { r4 - r11 } /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */\n        stmia r2, { r4 - r11 }  /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */\n        ldmia r1 !, { r4 - r11 } /* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */\n        stmia r2, { r4 - r11 } /* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */\n    #endif /* configTOTAL_MPU_REGIONS == 16. */\n\n    ldr r2, =0xe000ed94     /* MPU_CTRL register. */\n    ldr r3, [ r2 ] /* Read the value of MPU_CTRL. */\n    orr r3, r3, #1          /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */\n    str r3, [ r2 ]           /* Enable MPU. */\n    dsb                      /* Force memory writes before continuing. */\n\n    ldmia r0 !, { r3 - r11, r14 }                               /* Pop the registers that are not automatically saved on exception entry. */\n    msr control, r3\n\n    tst r14, #0x10 /* Is the task using the FPU context?  If so, pop the high vfp registers too. */\n    it eq\n    vldmiaeq r0 !, { s16 - s31 }\n\n    msr psp, r0\n    bx r14\n    nop\n/* *INDENT-ON* */\n}\n/*-----------------------------------------------------------*/\n\nvoid xPortSysTickHandler( void )\n{\n    uint32_t ulDummy;\n\n    ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();\n    {\n        /* Increment the RTOS tick. */\n        if( xTaskIncrementTick() != pdFALSE )\n        {\n            /* Pend a context switch. */\n            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\n        }\n    }\n    portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );\n}\n/*-----------------------------------------------------------*/\n\n/*\n * Setup the systick timer to generate the tick interrupts at the required\n * frequency.\n */\n__weak void vSetupTimerInterrupt( void )\n{\n    /* Reset the SysTick. */\n    portNVIC_SYSTICK_CTRL_REG = 0UL;\n    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n    /* Configure SysTick to interrupt at the requested rate. */\n    portNVIC_SYSTICK_LOAD_REG = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\n    portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;\n}\n/*-----------------------------------------------------------*/\n\n__asm void vPortSwitchToUserMode( void )\n{\n/* *INDENT-OFF* */\n    PRESERVE8\n\n    mrs r0, control\n    orr r0, #1\n    msr control, r0\n    bx r14\n/* *INDENT-ON* */\n}\n/*-----------------------------------------------------------*/\n\n__asm void vPortEnableVFP( void )\n{\n/* *INDENT-OFF* */\n    PRESERVE8\n\n    ldr.w r0, =0xE000ED88 /* The FPU enable bits are in the CPACR. */\n    ldr r1, [ r0 ]\n\n    orr r1, r1, #( 0xf << 20 ) /* Enable CP10 and CP11 coprocessors, then save back. */\n    str r1, [ r0 ]\n    bx r14\n    nop\n    nop\n/* *INDENT-ON* */\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvSetupMPU( void )\n{\n    extern uint32_t __privileged_functions_start__;\n    extern uint32_t __privileged_functions_end__;\n    extern uint32_t __FLASH_segment_start__;\n    extern uint32_t __FLASH_segment_end__;\n    extern uint32_t __privileged_data_start__;\n    extern uint32_t __privileged_data_end__;\n\n    /* The only permitted number of regions are 8 or 16. */\n    configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );\n\n    /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */\n    configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );\n\n    /* Check the expected MPU is present. */\n    if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )\n    {\n        /* First setup the unprivileged flash for unprivileged read only access. */\n        portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */\n                                          ( portMPU_REGION_VALID ) |\n                                          ( portUNPRIVILEGED_FLASH_REGION );\n\n        portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_ONLY ) |\n                                       ( ( configTEX_S_C_B_FLASH & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |\n                                       ( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |\n                                       ( portMPU_REGION_ENABLE );\n\n        /* Setup the privileged flash for privileged only access.  This is where\n         * the kernel code is placed. */\n        portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_functions_start__ ) | /* Base address. */\n                                          ( portMPU_REGION_VALID ) |\n                                          ( portPRIVILEGED_FLASH_REGION );\n\n        portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_ONLY ) |\n                                       ( ( configTEX_S_C_B_FLASH & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |\n                                       ( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __privileged_functions_start__ ) ) |\n                                       ( portMPU_REGION_ENABLE );\n\n        /* Setup the privileged data RAM region.  This is where the kernel data\n         * is placed. */\n        portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */\n                                          ( portMPU_REGION_VALID ) |\n                                          ( portPRIVILEGED_RAM_REGION );\n\n        portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\n                                       ( portMPU_REGION_EXECUTE_NEVER ) |\n                                       ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |\n                                       prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |\n                                       ( portMPU_REGION_ENABLE );\n\n        /* By default allow everything to access the general peripherals.  The\n         * system peripherals and registers are protected. */\n        portMPU_REGION_BASE_ADDRESS_REG = ( portPERIPHERALS_START_ADDRESS ) |\n                                          ( portMPU_REGION_VALID ) |\n                                          ( portGENERAL_PERIPHERALS_REGION );\n\n        portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |\n                                       ( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |\n                                       ( portMPU_REGION_ENABLE );\n\n        /* Enable the memory fault exception. */\n        portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE;\n\n        /* Enable the MPU with the background region configured. */\n        portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );\n    }\n}\n/*-----------------------------------------------------------*/\n\nstatic uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )\n{\n    uint32_t ulRegionSize, ulReturnValue = 4;\n\n    /* 32 is the smallest region size, 31 is the largest valid value for\n     * ulReturnValue. */\n    for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )\n    {\n        if( ulActualSizeInBytes <= ulRegionSize )\n        {\n            break;\n        }\n        else\n        {\n            ulReturnValue++;\n        }\n    }\n\n    /* Shift the code by one before returning so it can be written directly\n     * into the the correct bit position of the attribute register. */\n    return( ulReturnValue << 1UL );\n}\n/*-----------------------------------------------------------*/\n\n__asm BaseType_t xIsPrivileged( void )\n{\n/* *INDENT-OFF* */\n    PRESERVE8\n\n    mrs r0, control /* r0 = CONTROL. */\n    tst r0, #1     /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\n    ite ne\n    movne r0, #0   /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\n    moveq r0, #1   /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */\n    bx lr           /* Return. */\n/* *INDENT-ON* */\n}\n/*-----------------------------------------------------------*/\n\n__asm void vResetPrivilege( void )\n{\n/* *INDENT-OFF* */\n    PRESERVE8\n\n    mrs r0, control /* r0 = CONTROL. */\n    orrs r0, #1    /* r0 = r0 | 1. */\n    msr control, r0 /* CONTROL = r0. */\n    bx lr           /* Return. */\n/* *INDENT-ON* */\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,\n                                const struct xMEMORY_REGION * const xRegions,\n                                StackType_t * pxBottomOfStack,\n                                uint32_t ulStackDepth )\n{\n    extern uint32_t __SRAM_segment_start__;\n    extern uint32_t __SRAM_segment_end__;\n    extern uint32_t __privileged_data_start__;\n    extern uint32_t __privileged_data_end__;\n\n\n    int32_t lIndex;\n    uint32_t ul;\n\n    if( xRegions == NULL )\n    {\n        /* No MPU regions are specified so allow access to all RAM. */\n        xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =\n            ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */\n            ( portMPU_REGION_VALID ) |\n            ( portSTACK_REGION ); /* Region number. */\n\n        xMPUSettings->xRegion[ 0 ].ulRegionAttribute =\n            ( portMPU_REGION_READ_WRITE ) |\n            ( portMPU_REGION_EXECUTE_NEVER ) |\n            ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |\n            ( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |\n            ( portMPU_REGION_ENABLE );\n\n        /* Invalidate user configurable regions. */\n        for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )\n        {\n            xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( ul - 1UL ) | portMPU_REGION_VALID );\n            xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;\n        }\n    }\n    else\n    {\n        /* This function is called automatically when the task is created - in\n         * which case the stack region parameters will be valid.  At all other\n         * times the stack parameters will not be valid and it is assumed that the\n         * stack region has already been configured. */\n        if( ulStackDepth > 0 )\n        {\n            /* Define the region that allows access to the stack. */\n            xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =\n                ( ( uint32_t ) pxBottomOfStack ) |\n                ( portMPU_REGION_VALID ) |\n                ( portSTACK_REGION ); /* Region number. */\n\n            xMPUSettings->xRegion[ 0 ].ulRegionAttribute =\n                ( portMPU_REGION_READ_WRITE ) |\n                ( portMPU_REGION_EXECUTE_NEVER ) |\n                ( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |\n                ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |\n                ( portMPU_REGION_ENABLE );\n        }\n\n        lIndex = 0;\n\n        for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )\n        {\n            if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )\n            {\n                /* Translate the generic region definition contained in\n                 * xRegions into the CM4 specific MPU settings that are then\n                 * stored in xMPUSettings. */\n                xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =\n                    ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |\n                    ( portMPU_REGION_VALID ) |\n                    ( ul - 1UL ); /* Region number. */\n\n                xMPUSettings->xRegion[ ul ].ulRegionAttribute =\n                    ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |\n                    ( xRegions[ lIndex ].ulParameters ) |\n                    ( portMPU_REGION_ENABLE );\n            }\n            else\n            {\n                /* Invalidate the region. */\n                xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( ul - 1UL ) | portMPU_REGION_VALID );\n                xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;\n            }\n\n            lIndex++;\n        }\n    }\n}\n/*-----------------------------------------------------------*/\n\n__asm uint32_t prvPortGetIPSR( void )\n{\n/* *INDENT-OFF* */\n    PRESERVE8\n\n    mrs r0, ipsr\n    bx r14\n/* *INDENT-ON* */\n}\n/*-----------------------------------------------------------*/\n\n#if ( configASSERT_DEFINED == 1 )\n\n    void vPortValidateInterruptPriority( void )\n    {\n        uint32_t ulCurrentInterrupt;\n        uint8_t ucCurrentPriority;\n\n        /* Obtain the number of the currently executing interrupt. */\n        ulCurrentInterrupt = prvPortGetIPSR();\n\n        /* Is the interrupt number a user defined interrupt? */\n        if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )\n        {\n            /* Look up the interrupt's priority. */\n            ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];\n\n            /* The following assertion will fail if a service routine (ISR) for\n             * an interrupt that has been assigned a priority above\n             * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\n             * function.  ISR safe FreeRTOS API functions must *only* be called\n             * from interrupts that have been assigned a priority at or below\n             * configMAX_SYSCALL_INTERRUPT_PRIORITY.\n             *\n             * Numerically low interrupt priority numbers represent logically high\n             * interrupt priorities, therefore the priority of the interrupt must\n             * be set to a value equal to or numerically *higher* than\n             * configMAX_SYSCALL_INTERRUPT_PRIORITY.\n             *\n             * Interrupts that use the FreeRTOS API must not be left at their\n             * default priority of zero as that is the highest possible priority,\n             * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,\n             * and therefore also guaranteed to be invalid.\n             *\n             * FreeRTOS maintains separate thread and ISR API functions to ensure\n             * interrupt entry is as fast and simple as possible.\n             *\n             * The following links provide detailed information:\n             * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html\n             * https://www.FreeRTOS.org/FAQHelp.html */\n            configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );\n        }\n\n        /* Priority grouping:  The interrupt controller (NVIC) allows the bits\n         * that define each interrupt's priority to be split between bits that\n         * define the interrupt's pre-emption priority bits and bits that define\n         * the interrupt's sub-priority.  For simplicity all bits must be defined\n         * to be pre-emption priority bits.  The following assertion will fail if\n         * this is not the case (if some bits represent a sub-priority).\n         *\n         * If the application only uses CMSIS libraries for interrupt\n         * configuration then the correct setting can be achieved on all Cortex-M\n         * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the\n         * scheduler.  Note however that some vendor specific peripheral libraries\n         * assume a non-zero priority group setting, in which cases using a value\n         * of zero will result in unpredictable behaviour. */\n        configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );\n    }\n\n#endif /* configASSERT_DEFINED */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/RVDS/ARM_CM4_MPU/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n\n#ifndef PORTMACRO_H\n#define PORTMACRO_H\n\n/* *INDENT-OFF* */\n#ifdef __cplusplus\n    extern \"C\" {\n#endif\n/* *INDENT-ON* */\n\n/*-----------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the\n * given hardware and compiler.\n *\n * These settings should not be altered.\n *-----------------------------------------------------------\n */\n\n/* Type definitions. */\n#define portCHAR          char\n#define portFLOAT         float\n#define portDOUBLE        double\n#define portLONG          long\n#define portSHORT         short\n#define portSTACK_TYPE    uint32_t\n#define portBASE_TYPE     long\n\ntypedef portSTACK_TYPE   StackType_t;\ntypedef long             BaseType_t;\ntypedef unsigned long    UBaseType_t;\n\n#if ( configUSE_16_BIT_TICKS == 1 )\n    typedef uint16_t     TickType_t;\n    #define portMAX_DELAY              ( TickType_t ) 0xffff\n#else\n    typedef uint32_t     TickType_t;\n    #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL\n\n/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\n * not need to be guarded with a critical section. */\n    #define portTICK_TYPE_IS_ATOMIC    1\n#endif\n\n/*-----------------------------------------------------------*/\n\n/* MPU specific constants. */\n#define portUSING_MPU_WRAPPERS                                   1\n#define portPRIVILEGE_BIT                                        ( 0x80000000UL )\n\n#define portMPU_REGION_READ_WRITE                                ( 0x03UL << 24UL )\n#define portMPU_REGION_PRIVILEGED_READ_ONLY                      ( 0x05UL << 24UL )\n#define portMPU_REGION_READ_ONLY                                 ( 0x06UL << 24UL )\n#define portMPU_REGION_PRIVILEGED_READ_WRITE                     ( 0x01UL << 24UL )\n#define portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY    ( 0x02UL << 24UL )\n#define portMPU_REGION_CACHEABLE_BUFFERABLE                      ( 0x07UL << 16UL )\n#define portMPU_REGION_EXECUTE_NEVER                             ( 0x01UL << 28UL )\n\n/* Location of the TEX,S,C,B bits in the MPU Region Attribute and Size\n * Register (RASR). */\n#define portMPU_RASR_TEX_S_C_B_LOCATION                          ( 16UL )\n#define portMPU_RASR_TEX_S_C_B_MASK                              ( 0x3FUL )\n\n/* MPU settings that can be overriden in FreeRTOSConfig.h. */\n#ifndef configTOTAL_MPU_REGIONS\n    /* Define to 8 for backward compatibility. */\n    #define configTOTAL_MPU_REGIONS    ( 8UL )\n#endif\n\n/*\n * The TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits define the\n * memory type, and where necessary the cacheable and shareable properties\n * of the memory region.\n *\n * The TEX, C, and B bits together indicate the memory type of the region,\n * and:\n * - For Normal memory, the cacheable properties of the region.\n * - For Device memory, whether the region is shareable.\n *\n * For Normal memory regions, the S bit indicates whether the region is\n * shareable. For Strongly-ordered and Device memory, the S bit is ignored.\n *\n * See the following two tables for setting TEX, S, C and B bits for\n * unprivileged flash, privileged flash and privileged RAM regions.\n *\n +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+\n | TEX | C | B | Memory type            |  Description or Normal region cacheability             |  Shareable?             |\n +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+\n | 000 | 0 | 0 | Strongly-ordered       |  Strongly ordered                                      |  Shareable              |\n +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+\n | 000 | 0 | 1 | Device                 |  Shared device                                         |  Shareable              |\n +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+\n | 000 | 1 | 0 | Normal                 |  Outer and inner   write-through; no write allocate    |  S bit                  |\n +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+\n | 000 | 1 | 1 | Normal                 |  Outer and inner   write-back; no write allocate       |  S bit                  |\n +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+\n | 001 | 0 | 0 | Normal                 |  Outer and inner   Non-cacheable                       |  S bit                  |\n +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+\n | 001 | 0 | 1 | Reserved               |  Reserved                                              |  Reserved               |\n +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+\n | 001 | 1 | 0 | IMPLEMENTATION DEFINED |  IMPLEMENTATION DEFINED                                |  IMPLEMENTATION DEFINED |\n +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+\n | 001 | 1 | 1 | Normal                 |  Outer and inner   write-back; write and read allocate |  S bit                  |\n +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+\n | 010 | 0 | 0 | Device                 |  Non-shared device                                     |  Not shareable          |\n +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+\n | 010 | 0 | 1 | Reserved               |  Reserved                                              |  Reserved               |\n +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+\n | 010 | 1 | X | Reserved               |  Reserved                                              |  Reserved               |\n +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+\n | 011 | X | X | Reserved               |  Reserved                                              |  Reserved               |\n +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+\n | 1BB | A | A | Normal                 | Cached memory, with AA and BB indicating the inner and |  Reserved               |\n |     |   |   |                        | outer cacheability rules that must be exported on the  |                         |\n |     |   |   |                        | bus. See the table below for the cacheability policy   |                         |\n |     |   |   |                        | encoding. memory, BB=Outer policy, AA=Inner policy.    |                         |\n +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+\n |\n +-----------------------------------------+----------------------------------------+\n | AA or BB subfield of {TEX,C,B} encoding |  Cacheability policy                   |\n +-----------------------------------------+----------------------------------------+\n | 00                                      |  Non-cacheable                         |\n +-----------------------------------------+----------------------------------------+\n | 01                                      |  Write-back, write and   read allocate |\n +-----------------------------------------+----------------------------------------+\n | 10                                      |  Write-through, no write   allocate    |\n +-----------------------------------------+----------------------------------------+\n | 11                                      |  Write-back, no write   allocate       |\n +-----------------------------------------+----------------------------------------+\n */\n\n/* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for Flash\n * region. */\n#ifndef configTEX_S_C_B_FLASH\n    /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */\n    #define configTEX_S_C_B_FLASH    ( 0x07UL )\n#endif\n\n/* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for SRAM\n * region. */\n#ifndef configTEX_S_C_B_SRAM\n    /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */\n    #define configTEX_S_C_B_SRAM          ( 0x07UL )\n#endif\n\n#define portGENERAL_PERIPHERALS_REGION    ( configTOTAL_MPU_REGIONS - 5UL )\n#define portSTACK_REGION                  ( configTOTAL_MPU_REGIONS - 4UL )\n#define portUNPRIVILEGED_FLASH_REGION     ( configTOTAL_MPU_REGIONS - 3UL )\n#define portPRIVILEGED_FLASH_REGION       ( configTOTAL_MPU_REGIONS - 2UL )\n#define portPRIVILEGED_RAM_REGION         ( configTOTAL_MPU_REGIONS - 1UL )\n#define portFIRST_CONFIGURABLE_REGION     ( 0UL )\n#define portLAST_CONFIGURABLE_REGION      ( configTOTAL_MPU_REGIONS - 6UL )\n#define portNUM_CONFIGURABLE_REGIONS      ( configTOTAL_MPU_REGIONS - 5UL )\n#define portTOTAL_NUM_REGIONS_IN_TCB      ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus 1 to create space for the stack region. */\n\nvoid vPortSwitchToUserMode( void );\n#define portSWITCH_TO_USER_MODE()    vPortSwitchToUserMode()\n\ntypedef struct MPU_REGION_REGISTERS\n{\n    uint32_t ulRegionBaseAddress;\n    uint32_t ulRegionAttribute;\n} xMPU_REGION_REGISTERS;\n\ntypedef struct MPU_SETTINGS\n{\n    xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS_IN_TCB ];\n} xMPU_SETTINGS;\n\n/* Architecture specifics. */\n#define portSTACK_GROWTH          ( -1 )\n#define portTICK_PERIOD_MS        ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\n#define portBYTE_ALIGNMENT        8\n\n/* Constants used with memory barrier intrinsics. */\n#define portSY_FULL_READ_WRITE    ( 15 )\n\n/*-----------------------------------------------------------*/\n\n/* SVC numbers for various services. */\n#define portSVC_START_SCHEDULER    0\n#define portSVC_YIELD              1\n#define portSVC_RAISE_PRIVILEGE    2\n\n/* Scheduler utilities. */\n\n#define portYIELD()    __asm{ SVC portSVC_YIELD }\n#define portYIELD_WITHIN_API()                          \\\n    {                                                   \\\n        /* Set a PendSV to request a context switch. */ \\\n        portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \\\n                                                        \\\n        /* Barriers are normally not required but do ensure the code is completely \\\n         * within the specified behaviour for the architecture. */ \\\n        __dsb( portSY_FULL_READ_WRITE );                           \\\n        __isb( portSY_FULL_READ_WRITE );                           \\\n    }\n/*-----------------------------------------------------------*/\n\n#define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )\n#define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )\n#define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )\n#define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )\n/*-----------------------------------------------------------*/\n\n/* Critical section management. */\nextern void vPortEnterCritical( void );\nextern void vPortExitCritical( void );\n\n#define portDISABLE_INTERRUPTS()                  vPortRaiseBASEPRI()\n#define portENABLE_INTERRUPTS()                   vPortSetBASEPRI( 0 )\n#define portENTER_CRITICAL()                      vPortEnterCritical()\n#define portEXIT_CRITICAL()                       vPortExitCritical()\n#define portSET_INTERRUPT_MASK_FROM_ISR()         ulPortRaiseBASEPRI()\n#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vPortSetBASEPRI( x )\n\n/*-----------------------------------------------------------*/\n\n/* Architecture specific optimisations. */\n#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION\n    #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1\n#endif\n\n#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1\n\n/* Check the configuration. */\n    #if ( configMAX_PRIORITIES > 32 )\n        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.\n    #endif\n\n/* Store/clear the ready priorities in a bit map. */\n    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )\n    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )\n\n/*-----------------------------------------------------------*/\n\n    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ( uint32_t ) __clz( ( uxReadyPriorities ) ) )\n\n#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */\n/*-----------------------------------------------------------*/\n\n/* Task function macros as described on the FreeRTOS.org WEB site.  These are\n * not necessary for to use this port.  They are defined so the common demo files\n * (which build with all the ports) will build. */\n#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )\n#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )\n/*-----------------------------------------------------------*/\n\n#ifdef configASSERT\n    void vPortValidateInterruptPriority( void );\n    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()\n#endif\n\n/* portNOP() is not required by this port. */\n#define portNOP()\n\n#define portINLINE              __inline\n\n#ifndef portFORCE_INLINE\n    #define portFORCE_INLINE    __forceinline\n#endif\n/*-----------------------------------------------------------*/\n\nextern BaseType_t xIsPrivileged( void );\nextern void vResetPrivilege( void );\n\n/**\n * @brief Checks whether or not the processor is privileged.\n *\n * @return 1 if the processor is already privileged, 0 otherwise.\n */\n#define portIS_PRIVILEGED()      xIsPrivileged()\n\n/**\n * @brief Raise an SVC request to raise privilege.\n */\n#define portRAISE_PRIVILEGE()    __asm { svc portSVC_RAISE_PRIVILEGE }\n\n/**\n * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\n * register.\n */\n#define portRESET_PRIVILEGE()    vResetPrivilege()\n/*-----------------------------------------------------------*/\n\nstatic portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI )\n{\n    __asm\n    {\n        /* Barrier instructions are not used as this function is only used to\n         * lower the BASEPRI value. */\n/* *INDENT-OFF* */\n        msr basepri, ulBASEPRI\n/* *INDENT-ON* */\n    }\n}\n/*-----------------------------------------------------------*/\n\nstatic portFORCE_INLINE void vPortRaiseBASEPRI( void )\n{\n    uint32_t ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;\n\n    __asm\n    {\n        /* Set BASEPRI to the max syscall priority to effect a critical\n         * section. */\n/* *INDENT-OFF* */\n    #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )\n        cpsid i\n    #endif\n        msr basepri, ulNewBASEPRI\n        dsb\n        isb\n    #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )\n        cpsie i\n    #endif\n/* *INDENT-ON* */\n    }\n}\n/*-----------------------------------------------------------*/\n\nstatic portFORCE_INLINE void vPortClearBASEPRIFromISR( void )\n{\n    __asm\n    {\n        /* Set BASEPRI to 0 so no interrupts are masked.  This function is only\n         * used to lower the mask in an interrupt, so memory barriers are not\n         * used. */\n/* *INDENT-OFF* */\n        msr basepri, # 0\n/* *INDENT-ON* */\n    }\n}\n/*-----------------------------------------------------------*/\n\nstatic portFORCE_INLINE uint32_t ulPortRaiseBASEPRI( void )\n{\n    uint32_t ulReturn, ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;\n\n    __asm\n    {\n        /* Set BASEPRI to the max syscall priority to effect a critical\n         * section. */\n/* *INDENT-OFF* */\n        mrs ulReturn, basepri\n    #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )\n        cpsid i\n    #endif\n        msr basepri, ulNewBASEPRI\n        dsb\n        isb\n    #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )\n        cpsie i\n    #endif\n/* *INDENT-ON* */\n    }\n\n    return ulReturn;\n}\n/*-----------------------------------------------------------*/\n\nstatic portFORCE_INLINE BaseType_t xPortIsInsideInterrupt( void )\n{\n    uint32_t ulCurrentInterrupt;\n    BaseType_t xReturn;\n\n    /* Obtain the number of the currently executing interrupt. */\n    __asm\n    {\n        mrs ulCurrentInterrupt, ipsr\n    }\n\n    if( ulCurrentInterrupt == 0 )\n    {\n        xReturn = pdFALSE;\n    }\n    else\n    {\n        xReturn = pdTRUE;\n    }\n\n    return xReturn;\n}\n/*-----------------------------------------------------------*/\n\n#ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY\n    #warning \"configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. https://www.FreeRTOS.org/FreeRTOS-V10.3.x.html\"\n    #define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY    0\n#endif\n/*-----------------------------------------------------------*/\n\n/* *INDENT-OFF* */\n#ifdef __cplusplus\n    }\n#endif\n/* *INDENT-ON* */\n\n#endif /* PORTMACRO_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/RVDS/ARM_CM7/ReadMe.txt",
    "content": "There are two options for running FreeRTOS on ARM Cortex-M7 microcontrollers.\nThe best option depends on the revision of the ARM Cortex-M7 core in use.  The\nrevision is specified by an 'r' number, and a 'p' number, so will look something\nlike 'r0p1'.  Check the documentation for the microcontroller in use to find the \nrevision of the Cortex-M7 core used in that microcontroller.  If in doubt, use \nthe FreeRTOS port provided specifically for r0p1 revisions, as that can be used\nwith all core revisions.\n\nThe first option is to use the ARM Cortex-M4F port, and the second option is to\nuse the Cortex-M7 r0p1 port - the latter containing a minor errata workaround.\n\nIf the revision of the ARM Cortex-M7 core is not r0p1 then either option can be\nused, but it is recommended to use the FreeRTOS ARM Cortex-M4F port located in \nthe /FreeRTOS/Source/portable/RVDS/ARM_CM4F directory.\n\nIf the revision of the ARM Cortex-M7 core is r0p1 then use the FreeRTOS ARM\nCortex-M7 r0p1 port located in the /FreeRTOS/Source/portable/RVDS/ARM_CM7/r0p1\ndirectory."
  },
  {
    "path": "FreeRTOS-comparison/portable/RVDS/ARM_CM7/r0p1/port.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/*-----------------------------------------------------------\n* Implementation of functions defined in portable.h for the ARM CM7 port.\n*----------------------------------------------------------*/\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n#ifndef __TARGET_FPU_VFP\n    #error This port can only be used when the project options are configured to enable hardware floating point support.\n#endif\n\n#if configMAX_SYSCALL_INTERRUPT_PRIORITY == 0\n    #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\n#endif\n\n/* The __weak attribute does not work as you might expect with the Keil tools\n * so the configOVERRIDE_DEFAULT_TICK_CONFIGURATION constant must be set to 1 if\n * the application writer wants to provide their own implementation of\n * vPortSetupTimerInterrupt().  Ensure configOVERRIDE_DEFAULT_TICK_CONFIGURATION\n * is defined. */\n#ifndef configOVERRIDE_DEFAULT_TICK_CONFIGURATION\n    #define configOVERRIDE_DEFAULT_TICK_CONFIGURATION    0\n#endif\n\n/* Constants required to manipulate the core.  Registers first... */\n#define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )\n#define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )\n#define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )\n#define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )\n/* ...then bits in the registers. */\n#define portNVIC_SYSTICK_CLK_BIT              ( 1UL << 2UL )\n#define portNVIC_SYSTICK_INT_BIT              ( 1UL << 1UL )\n#define portNVIC_SYSTICK_ENABLE_BIT           ( 1UL << 0UL )\n#define portNVIC_SYSTICK_COUNT_FLAG_BIT       ( 1UL << 16UL )\n#define portNVIC_PENDSVCLEAR_BIT              ( 1UL << 27UL )\n#define portNVIC_PEND_SYSTICK_SET_BIT         ( 1UL << 26UL )\n#define portNVIC_PEND_SYSTICK_CLEAR_BIT       ( 1UL << 25UL )\n\n#define portNVIC_PENDSV_PRI                   ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\n#define portNVIC_SYSTICK_PRI                  ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\n\n/* Constants required to check the validity of an interrupt priority. */\n#define portFIRST_USER_INTERRUPT_NUMBER       ( 16 )\n#define portNVIC_IP_REGISTERS_OFFSET_16       ( 0xE000E3F0 )\n#define portAIRCR_REG                         ( *( ( volatile uint32_t * ) 0xE000ED0C ) )\n#define portMAX_8_BIT_VALUE                   ( ( uint8_t ) 0xff )\n#define portTOP_BIT_OF_BYTE                   ( ( uint8_t ) 0x80 )\n#define portMAX_PRIGROUP_BITS                 ( ( uint8_t ) 7 )\n#define portPRIORITY_GROUP_MASK               ( 0x07UL << 8UL )\n#define portPRIGROUP_SHIFT                    ( 8UL )\n\n/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */\n#define portVECTACTIVE_MASK                   ( 0xFFUL )\n\n/* Constants required to manipulate the VFP. */\n#define portFPCCR                             ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */\n#define portASPEN_AND_LSPEN_BITS              ( 0x3UL << 30UL )\n\n/* Constants required to set up the initial stack. */\n#define portINITIAL_XPSR                      ( 0x01000000 )\n#define portINITIAL_EXC_RETURN                ( 0xfffffffd )\n\n/* The systick is a 24-bit counter. */\n#define portMAX_24_BIT_NUMBER                 ( 0xffffffUL )\n\n/* A fiddle factor to estimate the number of SysTick counts that would have\n * occurred while the SysTick counter is stopped during tickless idle\n * calculations. */\n#define portMISSED_COUNTS_FACTOR              ( 94UL )\n\n/* For strict compliance with the Cortex-M spec the task start address should\n * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */\n#define portSTART_ADDRESS_MASK                ( ( StackType_t ) 0xfffffffeUL )\n\n/* Let the user override the default SysTick clock rate.  If defined by the\n * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the\n * configuration register. */\n#ifndef configSYSTICK_CLOCK_HZ\n    #define configSYSTICK_CLOCK_HZ             ( configCPU_CLOCK_HZ )\n    /* Ensure the SysTick is clocked at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( portNVIC_SYSTICK_CLK_BIT )\n#else\n    /* Select the option to clock SysTick not at the same frequency as the core. */\n    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( 0 )\n#endif\n\n/*\n * Setup the timer to generate the tick interrupts.  The implementation in this\n * file is weak to allow application writers to change the timer used to\n * generate the tick interrupt.\n */\nvoid vPortSetupTimerInterrupt( void );\n\n/*\n * Exception handlers.\n */\nvoid xPortPendSVHandler( void );\nvoid xPortSysTickHandler( void );\nvoid vPortSVCHandler( void );\n\n/*\n * Start first task is a separate function so it can be tested in isolation.\n */\nstatic void prvStartFirstTask( void );\n\n/*\n * Functions defined in portasm.s to enable the VFP.\n */\nstatic void prvEnableVFP( void );\n\n/*\n * Used to catch tasks that attempt to return from their implementing function.\n */\nstatic void prvTaskExitError( void );\n\n/*-----------------------------------------------------------*/\n\n/* Each task maintains its own interrupt status in the critical nesting\n * variable. */\nstatic UBaseType_t uxCriticalNesting = 0xaaaaaaaa;\n\n/*\n * The number of SysTick increments that make up one tick period.\n */\n#if ( configUSE_TICKLESS_IDLE == 1 )\n    static uint32_t ulTimerCountsForOneTick = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n\n/*\n * The maximum number of tick periods that can be suppressed is limited by the\n * 24 bit resolution of the SysTick timer.\n */\n#if ( configUSE_TICKLESS_IDLE == 1 )\n    static uint32_t xMaximumPossibleSuppressedTicks = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n\n/*\n * Compensate for the CPU cycles that pass while the SysTick is stopped (low\n * power functionality only.\n */\n#if ( configUSE_TICKLESS_IDLE == 1 )\n    static uint32_t ulStoppedTimerCompensation = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n\n/*\n * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure\n * FreeRTOS API functions are not called from interrupts that have been assigned\n * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.\n */\n#if ( configASSERT_DEFINED == 1 )\n    static uint8_t ucMaxSysCallPriority = 0;\n    static uint32_t ulMaxPRIGROUPValue = 0;\n    static const volatile uint8_t * const pcInterruptPriorityRegisters = ( uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;\n#endif /* configASSERT_DEFINED */\n\n/*-----------------------------------------------------------*/\n\n/*\n * See header file for description.\n */\nStackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,\n                                     TaskFunction_t pxCode,\n                                     void * pvParameters )\n{\n    /* Simulate the stack frame as it would be created by a context switch\n     * interrupt. */\n\n    /* Offset added to account for the way the MCU uses the stack on entry/exit\n     * of interrupts, and to ensure alignment. */\n    pxTopOfStack--;\n\n    *pxTopOfStack = portINITIAL_XPSR;                                    /* xPSR */\n    pxTopOfStack--;\n    *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */\n    pxTopOfStack--;\n    *pxTopOfStack = ( StackType_t ) prvTaskExitError;                    /* LR */\n\n    /* Save code space by skipping register initialisation. */\n    pxTopOfStack -= 5;                            /* R12, R3, R2 and R1. */\n    *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\n\n    /* A save method is being used that requires each task to maintain its\n     * own exec return value. */\n    pxTopOfStack--;\n    *pxTopOfStack = portINITIAL_EXC_RETURN;\n\n    pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */\n\n    return pxTopOfStack;\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvTaskExitError( void )\n{\n    /* A function that implements a task must not exit or attempt to return to\n     * its caller as there is nothing to return to.  If a task wants to exit it\n     * should instead call vTaskDelete( NULL ).\n     *\n     * Artificially force an assert() to be triggered if configASSERT() is\n     * defined, then stop here so application writers can catch the error. */\n    configASSERT( uxCriticalNesting == ~0UL );\n    portDISABLE_INTERRUPTS();\n\n    for( ; ; )\n    {\n    }\n}\n/*-----------------------------------------------------------*/\n\n__asm void vPortSVCHandler( void )\n{\n/* *INDENT-OFF* */\n    PRESERVE8\n\n    /* Get the location of the current TCB. */\n    ldr r3, =pxCurrentTCB\n    ldr r1, [ r3 ]\n    ldr r0, [ r1 ]\n    /* Pop the core registers. */\n    ldmia r0!, { r4-r11, r14 }\n    msr psp, r0\n    isb\n    mov r0, #0\n    msr basepri, r0\n    bx r14\n/* *INDENT-ON* */\n}\n/*-----------------------------------------------------------*/\n\n__asm void prvStartFirstTask( void )\n{\n/* *INDENT-OFF* */\n    PRESERVE8\n\n    /* Use the NVIC offset register to locate the stack. */\n    ldr r0, =0xE000ED08\n    ldr r0, [ r0 ]\n    ldr r0, [ r0 ]\n    /* Set the msp back to the start of the stack. */\n    msr msp, r0\n\n    /* Clear the bit that indicates the FPU is in use in case the FPU was used\n     * before the scheduler was started - which would otherwise result in the\n     * unnecessary leaving of space in the SVC stack for lazy saving of FPU\n     * registers. */\n    mov r0, #0\n    msr control, r0\n    /* Globally enable interrupts. */\n    cpsie i\n    cpsie f\n    dsb\n    isb\n    /* Call SVC to start the first task. */\n    svc 0\n    nop\n    nop\n/* *INDENT-ON* */\n}\n/*-----------------------------------------------------------*/\n\n__asm void prvEnableVFP( void )\n{\n/* *INDENT-OFF* */\n    PRESERVE8\n\n    /* The FPU enable bits are in the CPACR. */\n    ldr.w r0, =0xE000ED88\n    ldr r1, [ r0 ]\n\n    /* Enable CP10 and CP11 coprocessors, then save back. */\n    orr r1, r1, #( 0xf << 20 )\n    str r1, [ r0 ]\n    bx r14\n    nop\n/* *INDENT-ON* */\n}\n/*-----------------------------------------------------------*/\n\n/*\n * See header file for description.\n */\nBaseType_t xPortStartScheduler( void )\n{\n    #if ( configASSERT_DEFINED == 1 )\n    {\n        volatile uint32_t ulOriginalPriority;\n        volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\n        volatile uint8_t ucMaxPriorityValue;\n\n        /* Determine the maximum priority from which ISR safe FreeRTOS API\n         * functions can be called.  ISR safe functions are those that end in\n         * \"FromISR\".  FreeRTOS maintains separate thread and ISR API functions to\n         * ensure interrupt entry is as fast and simple as possible.\n         *\n         * Save the interrupt priority value that is about to be clobbered. */\n        ulOriginalPriority = *pucFirstUserPriorityRegister;\n\n        /* Determine the number of priority bits available.  First write to all\n         * possible bits. */\n        *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\n\n        /* Read the value back to see how many bits stuck. */\n        ucMaxPriorityValue = *pucFirstUserPriorityRegister;\n\n        /* The kernel interrupt priority should be set to the lowest\n         * priority. */\n        configASSERT( ucMaxPriorityValue == ( configKERNEL_INTERRUPT_PRIORITY & ucMaxPriorityValue ) );\n\n        /* Use the same mask on the maximum system call priority. */\n        ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;\n\n        /* Calculate the maximum acceptable priority group value for the number\n         * of bits read back. */\n        ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;\n\n        while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )\n        {\n            ulMaxPRIGROUPValue--;\n            ucMaxPriorityValue <<= ( uint8_t ) 0x01;\n        }\n\n        #ifdef __NVIC_PRIO_BITS\n        {\n            /* Check the CMSIS configuration that defines the number of\n             * priority bits matches the number of priority bits actually queried\n             * from the hardware. */\n            configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );\n        }\n        #endif\n\n        #ifdef configPRIO_BITS\n        {\n            /* Check the FreeRTOS configuration that defines the number of\n             * priority bits matches the number of priority bits actually queried\n             * from the hardware. */\n            configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );\n        }\n        #endif\n\n        /* Shift the priority group value back to its position within the AIRCR\n         * register. */\n        ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;\n        ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;\n\n        /* Restore the clobbered interrupt priority register to its original\n         * value. */\n        *pucFirstUserPriorityRegister = ulOriginalPriority;\n    }\n    #endif /* configASSERT_DEFINED */\n\n    /* Make PendSV and SysTick the lowest priority interrupts. */\n    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;\n    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;\n\n    /* Start the timer that generates the tick ISR.  Interrupts are disabled\n     * here already. */\n    vPortSetupTimerInterrupt();\n\n    /* Initialise the critical nesting count ready for the first task. */\n    uxCriticalNesting = 0;\n\n    /* Ensure the VFP is enabled - it should be anyway. */\n    prvEnableVFP();\n\n    /* Lazy save always. */\n    *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;\n\n    /* Start the first task. */\n    prvStartFirstTask();\n\n    /* Should not get here! */\n    return 0;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEndScheduler( void )\n{\n    /* Not implemented in ports where there is nothing to return to.\n     * Artificially force an assert. */\n    configASSERT( uxCriticalNesting == 1000UL );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEnterCritical( void )\n{\n    portDISABLE_INTERRUPTS();\n    uxCriticalNesting++;\n\n    /* This is not the interrupt safe version of the enter critical function so\n     * assert() if it is being called from an interrupt context.  Only API\n     * functions that end in \"FromISR\" can be used in an interrupt.  Only assert if\n     * the critical nesting count is 1 to protect against recursive calls if the\n     * assert function also uses a critical section. */\n    if( uxCriticalNesting == 1 )\n    {\n        configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );\n    }\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortExitCritical( void )\n{\n    configASSERT( uxCriticalNesting );\n    uxCriticalNesting--;\n\n    if( uxCriticalNesting == 0 )\n    {\n        portENABLE_INTERRUPTS();\n    }\n}\n/*-----------------------------------------------------------*/\n\n__asm void xPortPendSVHandler( void )\n{\n    extern uxCriticalNesting;\n    extern pxCurrentTCB;\n    extern vTaskSwitchContext;\n\n/* *INDENT-OFF* */\n    PRESERVE8\n\n    mrs r0, psp\n    isb\n    /* Get the location of the current TCB. */\n    ldr r3, =pxCurrentTCB\n    ldr r2, [ r3 ]\n\n    /* Is the task using the FPU context?  If so, push high vfp registers. */\n    tst r14, #0x10\n    it eq\n    vstmdbeq r0!, {s16-s31}\n\n    /* Save the core registers. */\n    stmdb r0!, {r4-r11, r14 }\n\n    /* Save the new top of stack into the first member of the TCB. */\n    str r0, [ r2 ]\n\n    stmdb sp!, { r0, r3 }\n    mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY\n    cpsid i\n    msr basepri, r0\n    dsb\n    isb\n    cpsie i\n    bl vTaskSwitchContext\n    mov r0, #0\n    msr basepri, r0\n    ldmia sp!, { r0, r3 }\n\n    /* The first item in pxCurrentTCB is the task top of stack. */\n    ldr r1, [ r3 ]\n    ldr r0, [ r1 ]\n\n    /* Pop the core registers. */\n    ldmia r0!, { r4-r11, r14 }\n\n    /* Is the task using the FPU context?  If so, pop the high vfp registers\n     * too. */\n    tst r14, #0x10\n    it eq\n    vldmiaeq r0!, { s16-s31 }\n\n    msr psp, r0\n    isb\n    #ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata */\n        #if WORKAROUND_PMU_CM001 == 1\n            push { r14 }\n            pop { pc }\n            nop\n        #endif\n    #endif\n\n    bx r14\n/* *INDENT-ON* */\n}\n/*-----------------------------------------------------------*/\n\nvoid xPortSysTickHandler( void )\n{\n    /* The SysTick runs at the lowest interrupt priority, so when this interrupt\n     * executes all interrupts must be unmasked.  There is therefore no need to\n     * save and then restore the interrupt mask value as its value is already\n     * known - therefore the slightly faster vPortRaiseBASEPRI() function is used\n     * in place of portSET_INTERRUPT_MASK_FROM_ISR(). */\n    vPortRaiseBASEPRI();\n    {\n        /* Increment the RTOS tick. */\n        if( xTaskIncrementTick() != pdFALSE )\n        {\n            /* A context switch is required.  Context switching is performed in\n             * the PendSV interrupt.  Pend the PendSV interrupt. */\n            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\n        }\n    }\n\n    vPortClearBASEPRIFromISR();\n}\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TICKLESS_IDLE == 1 )\n\n    __weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )\n    {\n        uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;\n        TickType_t xModifiableIdleTime;\n\n        /* Make sure the SysTick reload value does not overflow the counter. */\n        if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\n        {\n            xExpectedIdleTime = xMaximumPossibleSuppressedTicks;\n        }\n\n        /* Enter a critical section but don't use the taskENTER_CRITICAL()\n         * method as that will mask interrupts that should exit sleep mode. */\n        __disable_irq();\n        __dsb( portSY_FULL_READ_WRITE );\n        __isb( portSY_FULL_READ_WRITE );\n\n        /* If a context switch is pending or a task is waiting for the scheduler\n         * to be unsuspended then abandon the low power entry. */\n        if( eTaskConfirmSleepModeStatus() == eAbortSleep )\n        {\n            /* Re-enable interrupts - see comments above the __disable_irq()\n             * call above. */\n            __enable_irq();\n        }\n        else\n        {\n            /* Stop the SysTick momentarily.  The time the SysTick is stopped for\n             * is accounted for as best it can be, but using the tickless mode will\n             * inevitably result in some tiny drift of the time maintained by the\n             * kernel with respect to calendar time. */\n            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );\n\n            /* Use the SysTick current-value register to determine the number of\n             * SysTick decrements remaining until the next tick interrupt.  If the\n             * current-value register is zero, then there are actually\n             * ulTimerCountsForOneTick decrements remaining, not zero, because the\n             * SysTick requests the interrupt when decrementing from 1 to 0. */\n            ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n\n            if( ulSysTickDecrementsLeft == 0 )\n            {\n                ulSysTickDecrementsLeft = ulTimerCountsForOneTick;\n            }\n\n            /* Calculate the reload value required to wait xExpectedIdleTime\n             * tick periods.  -1 is used because this code normally executes part\n             * way through the first tick period.  But if the SysTick IRQ is now\n             * pending, then clear the IRQ, suppressing the first tick, and correct\n             * the reload value to reflect that the second tick period is already\n             * underway.  The expected idle time is always at least two ticks. */\n            ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );\n\n            if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )\n            {\n                portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;\n                ulReloadValue -= ulTimerCountsForOneTick;\n            }\n\n            if( ulReloadValue > ulStoppedTimerCompensation )\n            {\n                ulReloadValue -= ulStoppedTimerCompensation;\n            }\n\n            /* Set the new reload value. */\n            portNVIC_SYSTICK_LOAD_REG = ulReloadValue;\n\n            /* Clear the SysTick count flag and set the count value back to\n             * zero. */\n            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n            /* Restart SysTick. */\n            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\n\n            /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can\n             * set its parameter to 0 to indicate that its implementation contains\n             * its own wait for interrupt or wait for event instruction, and so wfi\n             * should not be executed again.  However, the original expected idle\n             * time variable must remain unmodified, so a copy is taken. */\n            xModifiableIdleTime = xExpectedIdleTime;\n            configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\n\n            if( xModifiableIdleTime > 0 )\n            {\n                __dsb( portSY_FULL_READ_WRITE );\n                __wfi();\n                __isb( portSY_FULL_READ_WRITE );\n            }\n\n            configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\n\n            /* Re-enable interrupts to allow the interrupt that brought the MCU\n             * out of sleep mode to execute immediately.  See comments above\n             * the __disable_irq() call above. */\n            __enable_irq();\n            __dsb( portSY_FULL_READ_WRITE );\n            __isb( portSY_FULL_READ_WRITE );\n\n            /* Disable interrupts again because the clock is about to be stopped\n             * and interrupts that execute while the clock is stopped will increase\n             * any slippage between the time maintained by the RTOS and calendar\n             * time. */\n            __disable_irq();\n            __dsb( portSY_FULL_READ_WRITE );\n            __isb( portSY_FULL_READ_WRITE );\n\n            /* Disable the SysTick clock without reading the\n             * portNVIC_SYSTICK_CTRL_REG register to ensure the\n             * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,\n             * the time the SysTick is stopped for is accounted for as best it can\n             * be, but using the tickless mode will inevitably result in some tiny\n             * drift of the time maintained by the kernel with respect to calendar\n             * time*/\n            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );\n\n            /* Determine whether the SysTick has already counted to zero. */\n            if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n            {\n                uint32_t ulCalculatedLoadValue;\n\n                /* The tick interrupt ended the sleep (or is now pending), and\n                 * a new tick period has started.  Reset portNVIC_SYSTICK_LOAD_REG\n                 * with whatever remains of the new tick period. */\n                ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\n\n                /* Don't allow a tiny value, or values that have somehow\n                 * underflowed because the post sleep hook did something\n                 * that took too long or because the SysTick current-value register\n                 * is zero. */\n                if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )\n                {\n                    ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );\n                }\n\n                portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;\n\n                /* As the pending tick will be processed as soon as this\n                 * function exits, the tick value maintained by the tick is stepped\n                 * forward by one less than the time spent waiting. */\n                ulCompleteTickPeriods = xExpectedIdleTime - 1UL;\n            }\n            else\n            {\n                /* Something other than the tick interrupt ended the sleep. */\n\n                /* Use the SysTick current-value register to determine the\n                 * number of SysTick decrements remaining until the expected idle\n                 * time would have ended. */\n                ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n                #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )\n                {\n                    /* If the SysTick is not using the core clock, the current-\n                     * value register might still be zero here.  In that case, the\n                     * SysTick didn't load from the reload register, and there are\n                     * ulReloadValue decrements remaining in the expected idle\n                     * time, not zero. */\n                    if( ulSysTickDecrementsLeft == 0 )\n                    {\n                        ulSysTickDecrementsLeft = ulReloadValue;\n                    }\n                }\n                #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */\n\n                /* Work out how long the sleep lasted rounded to complete tick\n                 * periods (not the ulReload value which accounted for part\n                 * ticks). */\n                ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;\n\n                /* How many complete tick periods passed while the processor\n                 * was waiting? */\n                ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;\n\n                /* The reload value is set to whatever fraction of a single tick\n                 * period remains. */\n                portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;\n            }\n\n            /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,\n             * then set portNVIC_SYSTICK_LOAD_REG back to its standard value.  If\n             * the SysTick is not using the core clock, temporarily configure it to\n             * use the core clock.  This configuration forces the SysTick to load\n             * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next\n             * cycle of the other clock.  Then portNVIC_SYSTICK_LOAD_REG is ready\n             * to receive the standard value immediately. */\n            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n            portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n            #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )\n            {\n                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n            }\n            #else\n            {\n                /* The temporary usage of the core clock has served its purpose,\n                 * as described above.  Resume usage of the other clock. */\n                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\n\n                if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n                {\n                    /* The partial tick period already ended.  Be sure the SysTick\n                     * counts it only once. */\n                    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;\n                }\n\n                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\n            }\n            #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */\n\n            /* Step the tick to account for any tick periods that elapsed. */\n            vTaskStepTick( ulCompleteTickPeriods );\n\n            /* Exit with interrupts enabled. */\n            __enable_irq();\n        }\n    }\n\n#endif /* #if configUSE_TICKLESS_IDLE */\n\n/*-----------------------------------------------------------*/\n\n/*\n * Setup the SysTick timer to generate the tick interrupts at the required\n * frequency.\n */\n#if ( configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0 )\n\n    __weak void vPortSetupTimerInterrupt( void )\n    {\n        /* Calculate the constants required to configure the tick interrupt. */\n        #if ( configUSE_TICKLESS_IDLE == 1 )\n        {\n            ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );\n            xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;\n            ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\n        }\n        #endif /* configUSE_TICKLESS_IDLE */\n\n        /* Stop and clear the SysTick. */\n        portNVIC_SYSTICK_CTRL_REG = 0UL;\n        portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n        /* Configure SysTick to interrupt at the requested rate. */\n        portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\n        portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );\n    }\n\n#endif /* configOVERRIDE_DEFAULT_TICK_CONFIGURATION */\n/*-----------------------------------------------------------*/\n\n__asm uint32_t vPortGetIPSR( void )\n{\n/* *INDENT-OFF* */\n    PRESERVE8\n\n    mrs r0, ipsr\n    bx r14\n/* *INDENT-ON* */\n}\n/*-----------------------------------------------------------*/\n\n#if ( configASSERT_DEFINED == 1 )\n\n    void vPortValidateInterruptPriority( void )\n    {\n        uint32_t ulCurrentInterrupt;\n        uint8_t ucCurrentPriority;\n\n        /* Obtain the number of the currently executing interrupt. */\n        ulCurrentInterrupt = vPortGetIPSR();\n\n        /* Is the interrupt number a user defined interrupt? */\n        if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )\n        {\n            /* Look up the interrupt's priority. */\n            ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];\n\n            /* The following assertion will fail if a service routine (ISR) for\n             * an interrupt that has been assigned a priority above\n             * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\n             * function.  ISR safe FreeRTOS API functions must *only* be called\n             * from interrupts that have been assigned a priority at or below\n             * configMAX_SYSCALL_INTERRUPT_PRIORITY.\n             *\n             * Numerically low interrupt priority numbers represent logically high\n             * interrupt priorities, therefore the priority of the interrupt must\n             * be set to a value equal to or numerically *higher* than\n             * configMAX_SYSCALL_INTERRUPT_PRIORITY.\n             *\n             * Interrupts that use the FreeRTOS API must not be left at their\n             * default priority of zero as that is the highest possible priority,\n             * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,\n             * and therefore also guaranteed to be invalid.\n             *\n             * FreeRTOS maintains separate thread and ISR API functions to ensure\n             * interrupt entry is as fast and simple as possible.\n             *\n             * The following links provide detailed information:\n             * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html\n             * https://www.FreeRTOS.org/FAQHelp.html */\n            configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );\n        }\n\n        /* Priority grouping:  The interrupt controller (NVIC) allows the bits\n         * that define each interrupt's priority to be split between bits that\n         * define the interrupt's pre-emption priority bits and bits that define\n         * the interrupt's sub-priority.  For simplicity all bits must be defined\n         * to be pre-emption priority bits.  The following assertion will fail if\n         * this is not the case (if some bits represent a sub-priority).\n         *\n         * If the application only uses CMSIS libraries for interrupt\n         * configuration then the correct setting can be achieved on all Cortex-M\n         * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the\n         * scheduler.  Note however that some vendor specific peripheral libraries\n         * assume a non-zero priority group setting, in which cases using a value\n         * of zero will result in unpredictable behaviour. */\n        configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );\n    }\n\n#endif /* configASSERT_DEFINED */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/RVDS/ARM_CM7/r0p1/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n\n#ifndef PORTMACRO_H\n#define PORTMACRO_H\n\n/* *INDENT-OFF* */\n#ifdef __cplusplus\n    extern \"C\" {\n#endif\n/* *INDENT-ON* */\n\n/*-----------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the\n * given hardware and compiler.\n *\n * These settings should not be altered.\n *-----------------------------------------------------------\n */\n\n/* Type definitions. */\n    #define portCHAR          char\n    #define portFLOAT         float\n    #define portDOUBLE        double\n    #define portLONG          long\n    #define portSHORT         short\n    #define portSTACK_TYPE    uint32_t\n    #define portBASE_TYPE     long\n\n    typedef portSTACK_TYPE   StackType_t;\n    typedef long             BaseType_t;\n    typedef unsigned long    UBaseType_t;\n\n    #if ( configUSE_16_BIT_TICKS == 1 )\n        typedef uint16_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffff\n    #else\n        typedef uint32_t     TickType_t;\n        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL\n\n/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\n * not need to be guarded with a critical section. */\n        #define portTICK_TYPE_IS_ATOMIC    1\n    #endif\n/*-----------------------------------------------------------*/\n\n/* Architecture specifics. */\n    #define portSTACK_GROWTH          ( -1 )\n    #define portTICK_PERIOD_MS        ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\n    #define portBYTE_ALIGNMENT        8\n\n/* Constants used with memory barrier intrinsics. */\n    #define portSY_FULL_READ_WRITE    ( 15 )\n\n/*-----------------------------------------------------------*/\n\n/* Scheduler utilities. */\n    #define portYIELD()                                 \\\n    {                                                   \\\n        /* Set a PendSV to request a context switch. */ \\\n        portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \\\n                                                        \\\n        /* Barriers are normally not required but do ensure the code is completely \\\n         * within the specified behaviour for the architecture. */ \\\n        __dsb( portSY_FULL_READ_WRITE );                           \\\n        __isb( portSY_FULL_READ_WRITE );                           \\\n    }\n/*-----------------------------------------------------------*/\n\n    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )\n    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )\n    #define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 )\n    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )\n/*-----------------------------------------------------------*/\n\n/* Critical section management. */\n    extern void vPortEnterCritical( void );\n    extern void vPortExitCritical( void );\n\n    #define portDISABLE_INTERRUPTS()                  vPortRaiseBASEPRI()\n    #define portENABLE_INTERRUPTS()                   vPortSetBASEPRI( 0 )\n    #define portENTER_CRITICAL()                      vPortEnterCritical()\n    #define portEXIT_CRITICAL()                       vPortExitCritical()\n    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulPortRaiseBASEPRI()\n    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vPortSetBASEPRI( x )\n\n/*-----------------------------------------------------------*/\n\n/* Tickless idle/low power functionality. */\n    #ifndef portSUPPRESS_TICKS_AND_SLEEP\n        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );\n        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )\n    #endif\n/*-----------------------------------------------------------*/\n\n/* Port specific optimisations. */\n    #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION\n        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1\n    #endif\n\n    #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1\n\n/* Check the configuration. */\n        #if ( configMAX_PRIORITIES > 32 )\n            #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.\n        #endif\n\n/* Store/clear the ready priorities in a bit map. */\n        #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )\n        #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )\n\n/*-----------------------------------------------------------*/\n\n        #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ( uint32_t ) __clz( ( uxReadyPriorities ) ) )\n\n    #endif /* taskRECORD_READY_PRIORITY */\n/*-----------------------------------------------------------*/\n\n/* Task function macros as described on the FreeRTOS.org WEB site.  These are\n * not necessary for to use this port.  They are defined so the common demo files\n * (which build with all the ports) will build. */\n    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )\n    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )\n/*-----------------------------------------------------------*/\n\n    #ifdef configASSERT\n        void vPortValidateInterruptPriority( void );\n        #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()\n    #endif\n\n/* portNOP() is not required by this port. */\n    #define portNOP()\n\n    #define portINLINE              __inline\n\n    #ifndef portFORCE_INLINE\n        #define portFORCE_INLINE    __forceinline\n    #endif\n\n/*-----------------------------------------------------------*/\n\n    static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI )\n    {\n        __asm\n        {\n            /* Barrier instructions are not used as this function is only used to\n             * lower the BASEPRI value. */\n/* *INDENT-OFF* */\n            msr basepri, ulBASEPRI\n/* *INDENT-ON* */\n        }\n    }\n/*-----------------------------------------------------------*/\n\n    static portFORCE_INLINE void vPortRaiseBASEPRI( void )\n    {\n        uint32_t ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;\n\n        __asm\n        {\n            /* Set BASEPRI to the max syscall priority to effect a critical\n             * section. */\n/* *INDENT-OFF* */\n            cpsid i\n            msr basepri, ulNewBASEPRI\n            dsb\n            isb\n            cpsie i\n/* *INDENT-ON* */\n        }\n    }\n/*-----------------------------------------------------------*/\n\n    static portFORCE_INLINE void vPortClearBASEPRIFromISR( void )\n    {\n        __asm\n        {\n            /* Set BASEPRI to 0 so no interrupts are masked.  This function is only\n             * used to lower the mask in an interrupt, so memory barriers are not\n             * used. */\n/* *INDENT-OFF* */\n            msr basepri, # 0\n/* *INDENT-ON* */\n        }\n    }\n/*-----------------------------------------------------------*/\n\n    static portFORCE_INLINE uint32_t ulPortRaiseBASEPRI( void )\n    {\n        uint32_t ulReturn, ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;\n\n        __asm\n        {\n            /* Set BASEPRI to the max syscall priority to effect a critical\n             * section. */\n/* *INDENT-OFF* */\n            mrs ulReturn, basepri\n            cpsid i\n            msr basepri, ulNewBASEPRI\n            dsb\n            isb\n            cpsie i\n/* *INDENT-ON* */\n        }\n\n        return ulReturn;\n    }\n/*-----------------------------------------------------------*/\n\n    static portFORCE_INLINE BaseType_t xPortIsInsideInterrupt( void )\n    {\n        uint32_t ulCurrentInterrupt;\n        BaseType_t xReturn;\n\n        /* Obtain the number of the currently executing interrupt. */\n        __asm\n        {\n/* *INDENT-OFF* */\n            mrs ulCurrentInterrupt, ipsr\n/* *INDENT-ON* */\n        }\n\n        if( ulCurrentInterrupt == 0 )\n        {\n            xReturn = pdFALSE;\n        }\n        else\n        {\n            xReturn = pdTRUE;\n        }\n\n        return xReturn;\n    }\n\n/* *INDENT-OFF* */\n#ifdef __cplusplus\n    }\n#endif\n/* *INDENT-ON* */\n\n#endif /* PORTMACRO_H */\n"
  },
  {
    "path": "FreeRTOS-comparison/portable/readme.txt",
    "content": "Each real time kernel port consists of three files that contain the core kernel\ncomponents and are common to every port, and one or more files that are\nspecific to a particular microcontroller and/or compiler.\n\n\n+ The FreeRTOS/Source/Portable/MemMang directory contains the five sample\nmemory allocators as described on the https://www.FreeRTOS.org WEB site.\n\n+ The other directories each contain files specific to a particular\nmicrocontroller or compiler, where the directory name denotes the compiler\nspecific files the directory contains.\n\n\n\nFor example, if you are interested in the [compiler] port for the [architecture]\nmicrocontroller, then the port specific files are contained in\nFreeRTOS/Source/Portable/[compiler]/[architecture] directory.  If this is the\nonly port you are interested in then all the other directories can be\nignored.\n\n"
  },
  {
    "path": "FreeRTOS-comparison/queue.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n#include <stdlib.h>\n#include <string.h>\n\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\n * all the API functions to use the MPU wrappers.  That should only be done when\n * task.h is included from an application file. */\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n#include \"queue.h\"\n\n#if ( configUSE_CO_ROUTINES == 1 )\n    #include \"croutine.h\"\n#endif\n\n/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified\n * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined\n * for the header files above, but not in this file, in order to generate the\n * correct privileged Vs unprivileged linkage and placement. */\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */\n\n\n/* Constants used with the cRxLock and cTxLock structure members. */\n#define queueUNLOCKED             ( ( int8_t ) -1 )\n#define queueLOCKED_UNMODIFIED    ( ( int8_t ) 0 )\n#define queueINT8_MAX             ( ( int8_t ) 127 )\n\n/* When the Queue_t structure is used to represent a base queue its pcHead and\n * pcTail members are used as pointers into the queue storage area.  When the\n * Queue_t structure is used to represent a mutex pcHead and pcTail pointers are\n * not necessary, and the pcHead pointer is set to NULL to indicate that the\n * structure instead holds a pointer to the mutex holder (if any).  Map alternative\n * names to the pcHead and structure member to ensure the readability of the code\n * is maintained.  The QueuePointers_t and SemaphoreData_t types are used to form\n * a union as their usage is mutually exclusive dependent on what the queue is\n * being used for. */\n#define uxQueueType               pcHead\n#define queueQUEUE_IS_MUTEX       NULL\n\ntypedef struct QueuePointers\n{\n    int8_t * pcTail;     /*< Points to the byte at the end of the queue storage area.  Once more byte is allocated than necessary to store the queue items, this is used as a marker. */\n    int8_t * pcReadFrom; /*< Points to the last place that a queued item was read from when the structure is used as a queue. */\n} QueuePointers_t;\n\ntypedef struct SemaphoreData\n{\n    TaskHandle_t xMutexHolder;        /*< The handle of the task that holds the mutex. */\n    UBaseType_t uxRecursiveCallCount; /*< Maintains a count of the number of times a recursive mutex has been recursively 'taken' when the structure is used as a mutex. */\n} SemaphoreData_t;\n\n/* Semaphores do not actually store or copy data, so have an item size of\n * zero. */\n#define queueSEMAPHORE_QUEUE_ITEM_LENGTH    ( ( UBaseType_t ) 0 )\n#define queueMUTEX_GIVE_BLOCK_TIME          ( ( TickType_t ) 0U )\n\n#if ( configUSE_PREEMPTION == 0 )\n\n/* If the cooperative scheduler is being used then a yield should not be\n * performed just because a higher priority task has been woken. */\n    #define queueYIELD_IF_USING_PREEMPTION()\n#else\n    #define queueYIELD_IF_USING_PREEMPTION()    portYIELD_WITHIN_API()\n#endif\n\n/*\n * Definition of the queue used by the scheduler.\n * Items are queued by copy, not reference.  See the following link for the\n * rationale: https://www.FreeRTOS.org/Embedded-RTOS-Queues.html\n */\ntypedef struct QueueDefinition /* The old naming convention is used to prevent breaking kernel aware debuggers. */\n{\n    int8_t * pcHead;           /*< Points to the beginning of the queue storage area. */\n    int8_t * pcWriteTo;        /*< Points to the free next place in the storage area. */\n\n    union\n    {\n        QueuePointers_t xQueue;     /*< Data required exclusively when this structure is used as a queue. */\n        SemaphoreData_t xSemaphore; /*< Data required exclusively when this structure is used as a semaphore. */\n    } u;\n\n    List_t xTasksWaitingToSend;             /*< List of tasks that are blocked waiting to post onto this queue.  Stored in priority order. */\n    List_t xTasksWaitingToReceive;          /*< List of tasks that are blocked waiting to read from this queue.  Stored in priority order. */\n\n    volatile UBaseType_t uxMessagesWaiting; /*< The number of items currently in the queue. */\n    UBaseType_t uxLength;                   /*< The length of the queue defined as the number of items it will hold, not the number of bytes. */\n    UBaseType_t uxItemSize;                 /*< The size of each items that the queue will hold. */\n\n    volatile int8_t cRxLock;                /*< Stores the number of items received from the queue (removed from the queue) while the queue was locked.  Set to queueUNLOCKED when the queue is not locked. */\n    volatile int8_t cTxLock;                /*< Stores the number of items transmitted to the queue (added to the queue) while the queue was locked.  Set to queueUNLOCKED when the queue is not locked. */\n\n    #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )\n        uint8_t ucStaticallyAllocated; /*< Set to pdTRUE if the memory used by the queue was statically allocated to ensure no attempt is made to free the memory. */\n    #endif\n\n    #if ( configUSE_QUEUE_SETS == 1 )\n        struct QueueDefinition * pxQueueSetContainer;\n    #endif\n\n    #if ( configUSE_TRACE_FACILITY == 1 )\n        UBaseType_t uxQueueNumber;\n        uint8_t ucQueueType;\n    #endif\n} xQUEUE;\n\n/* The old xQUEUE name is maintained above then typedefed to the new Queue_t\n * name below to enable the use of older kernel aware debuggers. */\ntypedef xQUEUE Queue_t;\n\n/*-----------------------------------------------------------*/\n\n/*\n * The queue registry is just a means for kernel aware debuggers to locate\n * queue structures.  It has no other purpose so is an optional component.\n */\n#if ( configQUEUE_REGISTRY_SIZE > 0 )\n\n/* The type stored within the queue registry array.  This allows a name\n * to be assigned to each queue making kernel aware debugging a little\n * more user friendly. */\n    typedef struct QUEUE_REGISTRY_ITEM\n    {\n        const char * pcQueueName; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n        QueueHandle_t xHandle;\n    } xQueueRegistryItem;\n\n/* The old xQueueRegistryItem name is maintained above then typedefed to the\n * new xQueueRegistryItem name below to enable the use of older kernel aware\n * debuggers. */\n    typedef xQueueRegistryItem QueueRegistryItem_t;\n\n/* The queue registry is simply an array of QueueRegistryItem_t structures.\n * The pcQueueName member of a structure being NULL is indicative of the\n * array position being vacant. */\n    PRIVILEGED_DATA QueueRegistryItem_t xQueueRegistry[ configQUEUE_REGISTRY_SIZE ];\n\n#endif /* configQUEUE_REGISTRY_SIZE */\n\n/*\n * Unlocks a queue locked by a call to prvLockQueue.  Locking a queue does not\n * prevent an ISR from adding or removing items to the queue, but does prevent\n * an ISR from removing tasks from the queue event lists.  If an ISR finds a\n * queue is locked it will instead increment the appropriate queue lock count\n * to indicate that a task may require unblocking.  When the queue in unlocked\n * these lock counts are inspected, and the appropriate action taken.\n */\nstatic void prvUnlockQueue( Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;\n\n/*\n * Uses a critical section to determine if there is any data in a queue.\n *\n * @return pdTRUE if the queue contains no items, otherwise pdFALSE.\n */\nstatic BaseType_t prvIsQueueEmpty( const Queue_t * pxQueue ) PRIVILEGED_FUNCTION;\n\n/*\n * Uses a critical section to determine if there is any space in a queue.\n *\n * @return pdTRUE if there is no space, otherwise pdFALSE;\n */\nstatic BaseType_t prvIsQueueFull( const Queue_t * pxQueue ) PRIVILEGED_FUNCTION;\n\n/*\n * Copies an item into the queue, either at the front of the queue or the\n * back of the queue.\n */\nstatic BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue,\n                                      const void * pvItemToQueue,\n                                      const BaseType_t xPosition ) PRIVILEGED_FUNCTION;\n\n/*\n * Copies an item out of a queue.\n */\nstatic void prvCopyDataFromQueue( Queue_t * const pxQueue,\n                                  void * const pvBuffer ) PRIVILEGED_FUNCTION;\n\n#if ( configUSE_QUEUE_SETS == 1 )\n\n/*\n * Checks to see if a queue is a member of a queue set, and if so, notifies\n * the queue set that the queue contains data.\n */\n    static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;\n#endif\n\n/*\n * Called after a Queue_t structure has been allocated either statically or\n * dynamically to fill in the structure's members.\n */\nstatic void prvInitialiseNewQueue( const UBaseType_t uxQueueLength,\n                                   const UBaseType_t uxItemSize,\n                                   uint8_t * pucQueueStorage,\n                                   const uint8_t ucQueueType,\n                                   Queue_t * pxNewQueue ) PRIVILEGED_FUNCTION;\n\n/*\n * Mutexes are a special type of queue.  When a mutex is created, first the\n * queue is created, then prvInitialiseMutex() is called to configure the queue\n * as a mutex.\n */\n#if ( configUSE_MUTEXES == 1 )\n    static void prvInitialiseMutex( Queue_t * pxNewQueue ) PRIVILEGED_FUNCTION;\n#endif\n\n#if ( configUSE_MUTEXES == 1 )\n\n/*\n * If a task waiting for a mutex causes the mutex holder to inherit a\n * priority, but the waiting task times out, then the holder should\n * disinherit the priority - but only down to the highest priority of any\n * other tasks that are waiting for the same mutex.  This function returns\n * that priority.\n */\n    static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;\n#endif\n/*-----------------------------------------------------------*/\n\n/*\n * Macro to mark a queue as locked.  Locking a queue prevents an ISR from\n * accessing the queue event lists.\n */\n#define prvLockQueue( pxQueue )                            \\\n    taskENTER_CRITICAL();                                  \\\n    {                                                      \\\n        if( ( pxQueue )->cRxLock == queueUNLOCKED )        \\\n        {                                                  \\\n            ( pxQueue )->cRxLock = queueLOCKED_UNMODIFIED; \\\n        }                                                  \\\n        if( ( pxQueue )->cTxLock == queueUNLOCKED )        \\\n        {                                                  \\\n            ( pxQueue )->cTxLock = queueLOCKED_UNMODIFIED; \\\n        }                                                  \\\n    }                                                      \\\n    taskEXIT_CRITICAL()\n\n/*\n * Macro to increment cTxLock member of the queue data structure. It is\n * capped at the number of tasks in the system as we cannot unblock more\n * tasks than the number of tasks in the system.\n */\n#define prvIncrementQueueTxLock( pxQueue, cTxLock )                           \\\n    {                                                                         \\\n        const UBaseType_t uxNumberOfTasks = uxTaskGetNumberOfTasks();         \\\n        if( ( UBaseType_t ) ( cTxLock ) < uxNumberOfTasks )                   \\\n        {                                                                     \\\n            configASSERT( ( cTxLock ) != queueINT8_MAX );                     \\\n            ( pxQueue )->cTxLock = ( int8_t ) ( ( cTxLock ) + ( int8_t ) 1 ); \\\n        }                                                                     \\\n    }\n\n/*\n * Macro to increment cRxLock member of the queue data structure. It is\n * capped at the number of tasks in the system as we cannot unblock more\n * tasks than the number of tasks in the system.\n */\n#define prvIncrementQueueRxLock( pxQueue, cRxLock )                           \\\n    {                                                                         \\\n        const UBaseType_t uxNumberOfTasks = uxTaskGetNumberOfTasks();         \\\n        if( ( UBaseType_t ) ( cRxLock ) < uxNumberOfTasks )                   \\\n        {                                                                     \\\n            configASSERT( ( cRxLock ) != queueINT8_MAX );                     \\\n            ( pxQueue )->cRxLock = ( int8_t ) ( ( cRxLock ) + ( int8_t ) 1 ); \\\n        }                                                                     \\\n    }\n/*-----------------------------------------------------------*/\n\nBaseType_t xQueueGenericReset( QueueHandle_t xQueue,\n                               BaseType_t xNewQueue )\n{\n    BaseType_t xReturn = pdPASS;\n    Queue_t * const pxQueue = xQueue;\n\n    configASSERT( pxQueue );\n\n    if( ( pxQueue != NULL ) &&\n        ( pxQueue->uxLength >= 1U ) &&\n        /* Check for multiplication overflow. */\n        ( ( SIZE_MAX / pxQueue->uxLength ) >= pxQueue->uxItemSize ) )\n    {\n        taskENTER_CRITICAL();\n        {\n            pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */\n            pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;\n            pxQueue->pcWriteTo = pxQueue->pcHead;\n            pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */\n            pxQueue->cRxLock = queueUNLOCKED;\n            pxQueue->cTxLock = queueUNLOCKED;\n\n            if( xNewQueue == pdFALSE )\n            {\n                /* If there are tasks blocked waiting to read from the queue, then\n                 * the tasks will remain blocked as after this function exits the queue\n                 * will still be empty.  If there are tasks blocked waiting to write to\n                 * the queue, then one should be unblocked as after this function exits\n                 * it will be possible to write to it. */\n                if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )\n                {\n                    if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )\n                    {\n                        queueYIELD_IF_USING_PREEMPTION();\n                    }\n                    else\n                    {\n                        mtCOVERAGE_TEST_MARKER();\n                    }\n                }\n                else\n                {\n                    mtCOVERAGE_TEST_MARKER();\n                }\n            }\n            else\n            {\n                /* Ensure the event queues start in the correct state. */\n                vListInitialise( &( pxQueue->xTasksWaitingToSend ) );\n                vListInitialise( &( pxQueue->xTasksWaitingToReceive ) );\n            }\n        }\n        taskEXIT_CRITICAL();\n    }\n    else\n    {\n        xReturn = pdFAIL;\n    }\n\n    configASSERT( xReturn != pdFAIL );\n\n    /* A value is returned for calling semantic consistency with previous\n     * versions. */\n    return xReturn;\n}\n/*-----------------------------------------------------------*/\n\n#if ( configSUPPORT_STATIC_ALLOCATION == 1 )\n\n    QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength,\n                                             const UBaseType_t uxItemSize,\n                                             uint8_t * pucQueueStorage,\n                                             StaticQueue_t * pxStaticQueue,\n                                             const uint8_t ucQueueType )\n    {\n        Queue_t * pxNewQueue = NULL;\n\n        /* The StaticQueue_t structure and the queue storage area must be\n         * supplied. */\n        configASSERT( pxStaticQueue );\n\n        if( ( uxQueueLength > ( UBaseType_t ) 0 ) &&\n            ( pxStaticQueue != NULL ) &&\n\n            /* A queue storage area should be provided if the item size is not 0, and\n             * should not be provided if the item size is 0. */\n            ( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) ) &&\n            ( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) ) )\n        {\n            #if ( configASSERT_DEFINED == 1 )\n            {\n                /* Sanity check that the size of the structure used to declare a\n                 * variable of type StaticQueue_t or StaticSemaphore_t equals the size of\n                 * the real queue and semaphore structures. */\n                volatile size_t xSize = sizeof( StaticQueue_t );\n\n                /* This assertion cannot be branch covered in unit tests */\n                configASSERT( xSize == sizeof( Queue_t ) ); /* LCOV_EXCL_BR_LINE */\n                ( void ) xSize;                             /* Keeps lint quiet when configASSERT() is not defined. */\n            }\n            #endif /* configASSERT_DEFINED */\n\n            /* The address of a statically allocated queue was passed in, use it.\n             * The address of a statically allocated storage area was also passed in\n             * but is already set. */\n            pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */\n\n            #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n            {\n                /* Queues can be allocated wither statically or dynamically, so\n                 * note this queue was allocated statically in case the queue is\n                 * later deleted. */\n                pxNewQueue->ucStaticallyAllocated = pdTRUE;\n            }\n            #endif /* configSUPPORT_DYNAMIC_ALLOCATION */\n\n            prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );\n        }\n        else\n        {\n            configASSERT( pxNewQueue );\n            mtCOVERAGE_TEST_MARKER();\n        }\n\n        return pxNewQueue;\n    }\n\n#endif /* configSUPPORT_STATIC_ALLOCATION */\n/*-----------------------------------------------------------*/\n\n#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n\n    QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength,\n                                       const UBaseType_t uxItemSize,\n                                       const uint8_t ucQueueType )\n    {\n        Queue_t * pxNewQueue = NULL;\n        size_t xQueueSizeInBytes;\n        uint8_t * pucQueueStorage;\n\n        if( ( uxQueueLength > ( UBaseType_t ) 0 ) &&\n            /* Check for multiplication overflow. */\n            ( ( SIZE_MAX / uxQueueLength ) >= uxItemSize ) &&\n            /* Check for addition overflow. */\n            ( ( SIZE_MAX - sizeof( Queue_t ) ) >= ( uxQueueLength * uxItemSize ) ) )\n        {\n            /* Allocate enough space to hold the maximum number of items that\n             * can be in the queue at any time.  It is valid for uxItemSize to be\n             * zero in the case the queue is used as a semaphore. */\n            xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\n\n            /* Allocate the queue and storage area.  Justification for MISRA\n             * deviation as follows:  pvPortMalloc() always ensures returned memory\n             * blocks are aligned per the requirements of the MCU stack.  In this case\n             * pvPortMalloc() must return a pointer that is guaranteed to meet the\n             * alignment requirements of the Queue_t structure - which in this case\n             * is an int8_t *.  Therefore, whenever the stack alignment requirements\n             * are greater than or equal to the pointer to char requirements the cast\n             * is safe.  In other cases alignment requirements are not strict (one or\n             * two bytes). */\n            pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); /*lint !e9087 !e9079 see comment above. */\n\n            if( pxNewQueue != NULL )\n            {\n                /* Jump past the queue structure to find the location of the queue\n                 * storage area. */\n                pucQueueStorage = ( uint8_t * ) pxNewQueue;\n                pucQueueStorage += sizeof( Queue_t ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */\n\n                #if ( configSUPPORT_STATIC_ALLOCATION == 1 )\n                {\n                    /* Queues can be created either statically or dynamically, so\n                     * note this task was created dynamically in case it is later\n                     * deleted. */\n                    pxNewQueue->ucStaticallyAllocated = pdFALSE;\n                }\n                #endif /* configSUPPORT_STATIC_ALLOCATION */\n\n                prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );\n            }\n            else\n            {\n                traceQUEUE_CREATE_FAILED( ucQueueType );\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n        else\n        {\n            configASSERT( pxNewQueue );\n            mtCOVERAGE_TEST_MARKER();\n        }\n\n        return pxNewQueue;\n    }\n\n#endif /* configSUPPORT_STATIC_ALLOCATION */\n/*-----------------------------------------------------------*/\n\nstatic void prvInitialiseNewQueue( const UBaseType_t uxQueueLength,\n                                   const UBaseType_t uxItemSize,\n                                   uint8_t * pucQueueStorage,\n                                   const uint8_t ucQueueType,\n                                   Queue_t * pxNewQueue )\n{\n    /* Remove compiler warnings about unused parameters should\n     * configUSE_TRACE_FACILITY not be set to 1. */\n    ( void ) ucQueueType;\n\n    if( uxItemSize == ( UBaseType_t ) 0 )\n    {\n        /* No RAM was allocated for the queue storage area, but PC head cannot\n         * be set to NULL because NULL is used as a key to say the queue is used as\n         * a mutex.  Therefore just set pcHead to point to the queue as a benign\n         * value that is known to be within the memory map. */\n        pxNewQueue->pcHead = ( int8_t * ) pxNewQueue;\n    }\n    else\n    {\n        /* Set the head to the start of the queue storage area. */\n        pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage;\n    }\n\n    /* Initialise the queue members as described where the queue type is\n     * defined. */\n    pxNewQueue->uxLength = uxQueueLength;\n    pxNewQueue->uxItemSize = uxItemSize;\n    ( void ) xQueueGenericReset( pxNewQueue, pdTRUE );\n\n    #if ( configUSE_TRACE_FACILITY == 1 )\n    {\n        pxNewQueue->ucQueueType = ucQueueType;\n    }\n    #endif /* configUSE_TRACE_FACILITY */\n\n    #if ( configUSE_QUEUE_SETS == 1 )\n    {\n        pxNewQueue->pxQueueSetContainer = NULL;\n    }\n    #endif /* configUSE_QUEUE_SETS */\n\n    traceQUEUE_CREATE( pxNewQueue );\n}\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_MUTEXES == 1 )\n\n    static void prvInitialiseMutex( Queue_t * pxNewQueue )\n    {\n        if( pxNewQueue != NULL )\n        {\n            /* The queue create function will set all the queue structure members\n            * correctly for a generic queue, but this function is creating a\n            * mutex.  Overwrite those members that need to be set differently -\n            * in particular the information required for priority inheritance. */\n            pxNewQueue->u.xSemaphore.xMutexHolder = NULL;\n            pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX;\n\n            /* In case this is a recursive mutex. */\n            pxNewQueue->u.xSemaphore.uxRecursiveCallCount = 0;\n\n            traceCREATE_MUTEX( pxNewQueue );\n\n            /* Start with the semaphore in the expected state. */\n            ( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK );\n        }\n        else\n        {\n            traceCREATE_MUTEX_FAILED();\n        }\n    }\n\n#endif /* configUSE_MUTEXES */\n/*-----------------------------------------------------------*/\n\n#if ( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )\n\n    QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType )\n    {\n        QueueHandle_t xNewQueue;\n        const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;\n\n        xNewQueue = xQueueGenericCreate( uxMutexLength, uxMutexSize, ucQueueType );\n        prvInitialiseMutex( ( Queue_t * ) xNewQueue );\n\n        return xNewQueue;\n    }\n\n#endif /* configUSE_MUTEXES */\n/*-----------------------------------------------------------*/\n\n#if ( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )\n\n    QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType,\n                                           StaticQueue_t * pxStaticQueue )\n    {\n        QueueHandle_t xNewQueue;\n        const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;\n\n        /* Prevent compiler warnings about unused parameters if\n         * configUSE_TRACE_FACILITY does not equal 1. */\n        ( void ) ucQueueType;\n\n        xNewQueue = xQueueGenericCreateStatic( uxMutexLength, uxMutexSize, NULL, pxStaticQueue, ucQueueType );\n        prvInitialiseMutex( ( Queue_t * ) xNewQueue );\n\n        return xNewQueue;\n    }\n\n#endif /* configUSE_MUTEXES */\n/*-----------------------------------------------------------*/\n\n#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )\n\n    TaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore )\n    {\n        TaskHandle_t pxReturn;\n        Queue_t * const pxSemaphore = ( Queue_t * ) xSemaphore;\n\n        configASSERT( xSemaphore );\n\n        /* This function is called by xSemaphoreGetMutexHolder(), and should not\n         * be called directly.  Note:  This is a good way of determining if the\n         * calling task is the mutex holder, but not a good way of determining the\n         * identity of the mutex holder, as the holder may change between the\n         * following critical section exiting and the function returning. */\n        taskENTER_CRITICAL();\n        {\n            if( pxSemaphore->uxQueueType == queueQUEUE_IS_MUTEX )\n            {\n                pxReturn = pxSemaphore->u.xSemaphore.xMutexHolder;\n            }\n            else\n            {\n                pxReturn = NULL;\n            }\n        }\n        taskEXIT_CRITICAL();\n\n        return pxReturn;\n    } /*lint !e818 xSemaphore cannot be a pointer to const because it is a typedef. */\n\n#endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */\n/*-----------------------------------------------------------*/\n\n#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )\n\n    TaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore )\n    {\n        TaskHandle_t pxReturn;\n\n        configASSERT( xSemaphore );\n\n        /* Mutexes cannot be used in interrupt service routines, so the mutex\n         * holder should not change in an ISR, and therefore a critical section is\n         * not required here. */\n        if( ( ( Queue_t * ) xSemaphore )->uxQueueType == queueQUEUE_IS_MUTEX )\n        {\n            pxReturn = ( ( Queue_t * ) xSemaphore )->u.xSemaphore.xMutexHolder;\n        }\n        else\n        {\n            pxReturn = NULL;\n        }\n\n        return pxReturn;\n    } /*lint !e818 xSemaphore cannot be a pointer to const because it is a typedef. */\n\n#endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_RECURSIVE_MUTEXES == 1 )\n\n    BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex )\n    {\n        BaseType_t xReturn;\n        Queue_t * const pxMutex = ( Queue_t * ) xMutex;\n\n        configASSERT( pxMutex );\n\n        /* If this is the task that holds the mutex then xMutexHolder will not\n         * change outside of this task.  If this task does not hold the mutex then\n         * pxMutexHolder can never coincidentally equal the tasks handle, and as\n         * this is the only condition we are interested in it does not matter if\n         * pxMutexHolder is accessed simultaneously by another task.  Therefore no\n         * mutual exclusion is required to test the pxMutexHolder variable. */\n        if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() )\n        {\n            traceGIVE_MUTEX_RECURSIVE( pxMutex );\n\n            /* uxRecursiveCallCount cannot be zero if xMutexHolder is equal to\n             * the task handle, therefore no underflow check is required.  Also,\n             * uxRecursiveCallCount is only modified by the mutex holder, and as\n             * there can only be one, no mutual exclusion is required to modify the\n             * uxRecursiveCallCount member. */\n            ( pxMutex->u.xSemaphore.uxRecursiveCallCount )--;\n\n            /* Has the recursive call count unwound to 0? */\n            if( pxMutex->u.xSemaphore.uxRecursiveCallCount == ( UBaseType_t ) 0 )\n            {\n                /* Return the mutex.  This will automatically unblock any other\n                 * task that might be waiting to access the mutex. */\n                ( void ) xQueueGenericSend( pxMutex, NULL, queueMUTEX_GIVE_BLOCK_TIME, queueSEND_TO_BACK );\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n\n            xReturn = pdPASS;\n        }\n        else\n        {\n            /* The mutex cannot be given because the calling task is not the\n             * holder. */\n            xReturn = pdFAIL;\n\n            traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex );\n        }\n\n        return xReturn;\n    }\n\n#endif /* configUSE_RECURSIVE_MUTEXES */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_RECURSIVE_MUTEXES == 1 )\n\n    BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex,\n                                         TickType_t xTicksToWait )\n    {\n        BaseType_t xReturn;\n        Queue_t * const pxMutex = ( Queue_t * ) xMutex;\n\n        configASSERT( pxMutex );\n\n        /* Comments regarding mutual exclusion as per those within\n         * xQueueGiveMutexRecursive(). */\n\n        traceTAKE_MUTEX_RECURSIVE( pxMutex );\n\n        if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() )\n        {\n            ( pxMutex->u.xSemaphore.uxRecursiveCallCount )++;\n            xReturn = pdPASS;\n        }\n        else\n        {\n            xReturn = xQueueSemaphoreTake( pxMutex, xTicksToWait );\n\n            /* pdPASS will only be returned if the mutex was successfully\n             * obtained.  The calling task may have entered the Blocked state\n             * before reaching here. */\n            if( xReturn != pdFAIL )\n            {\n                ( pxMutex->u.xSemaphore.uxRecursiveCallCount )++;\n            }\n            else\n            {\n                traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex );\n            }\n        }\n\n        return xReturn;\n    }\n\n#endif /* configUSE_RECURSIVE_MUTEXES */\n/*-----------------------------------------------------------*/\n\n#if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )\n\n    QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount,\n                                                       const UBaseType_t uxInitialCount,\n                                                       StaticQueue_t * pxStaticQueue )\n    {\n        QueueHandle_t xHandle = NULL;\n\n        if( ( uxMaxCount != 0 ) &&\n            ( uxInitialCount <= uxMaxCount ) )\n        {\n            xHandle = xQueueGenericCreateStatic( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticQueue, queueQUEUE_TYPE_COUNTING_SEMAPHORE );\n\n            if( xHandle != NULL )\n            {\n                ( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount;\n\n                traceCREATE_COUNTING_SEMAPHORE();\n            }\n            else\n            {\n                traceCREATE_COUNTING_SEMAPHORE_FAILED();\n            }\n        }\n        else\n        {\n            configASSERT( xHandle );\n            mtCOVERAGE_TEST_MARKER();\n        }\n\n        return xHandle;\n    }\n\n#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */\n/*-----------------------------------------------------------*/\n\n#if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )\n\n    QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount,\n                                                 const UBaseType_t uxInitialCount )\n    {\n        QueueHandle_t xHandle = NULL;\n\n        if( ( uxMaxCount != 0 ) &&\n            ( uxInitialCount <= uxMaxCount ) )\n        {\n            xHandle = xQueueGenericCreate( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_COUNTING_SEMAPHORE );\n\n            if( xHandle != NULL )\n            {\n                ( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount;\n\n                traceCREATE_COUNTING_SEMAPHORE();\n            }\n            else\n            {\n                traceCREATE_COUNTING_SEMAPHORE_FAILED();\n            }\n        }\n        else\n        {\n            configASSERT( xHandle );\n            mtCOVERAGE_TEST_MARKER();\n        }\n\n        return xHandle;\n    }\n\n#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */\n/*-----------------------------------------------------------*/\n\nBaseType_t xQueueGenericSend( QueueHandle_t xQueue,\n                              const void * const pvItemToQueue,\n                              TickType_t xTicksToWait,\n                              const BaseType_t xCopyPosition )\n{\n    BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired;\n    TimeOut_t xTimeOut;\n    Queue_t * const pxQueue = xQueue;\n\n    configASSERT( pxQueue );\n    configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );\n    configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );\n    #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )\n    {\n        configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );\n    }\n    #endif\n\n    /*lint -save -e904 This function relaxes the coding standard somewhat to\n     * allow return statements within the function itself.  This is done in the\n     * interest of execution time efficiency. */\n    for( ; ; )\n    {\n        taskENTER_CRITICAL();\n        {\n            /* Is there room on the queue now?  The running task must be the\n             * highest priority task wanting to access the queue.  If the head item\n             * in the queue is to be overwritten then it does not matter if the\n             * queue is full. */\n            if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )\n            {\n                traceQUEUE_SEND( pxQueue );\n\n                #if ( configUSE_QUEUE_SETS == 1 )\n                {\n                    const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting;\n\n                    xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );\n\n                    if( pxQueue->pxQueueSetContainer != NULL )\n                    {\n                        if( ( xCopyPosition == queueOVERWRITE ) && ( uxPreviousMessagesWaiting != ( UBaseType_t ) 0 ) )\n                        {\n                            /* Do not notify the queue set as an existing item\n                             * was overwritten in the queue so the number of items\n                             * in the queue has not changed. */\n                            mtCOVERAGE_TEST_MARKER();\n                        }\n                        else if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE )\n                        {\n                            /* The queue is a member of a queue set, and posting\n                             * to the queue set caused a higher priority task to\n                             * unblock. A context switch is required. */\n                            queueYIELD_IF_USING_PREEMPTION();\n                        }\n                        else\n                        {\n                            mtCOVERAGE_TEST_MARKER();\n                        }\n                    }\n                    else\n                    {\n                        /* If there was a task waiting for data to arrive on the\n                         * queue then unblock it now. */\n                        if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\n                        {\n                            if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\n                            {\n                                /* The unblocked task has a priority higher than\n                                 * our own so yield immediately.  Yes it is ok to\n                                 * do this from within the critical section - the\n                                 * kernel takes care of that. */\n                                queueYIELD_IF_USING_PREEMPTION();\n                            }\n                            else\n                            {\n                                mtCOVERAGE_TEST_MARKER();\n                            }\n                        }\n                        else if( xYieldRequired != pdFALSE )\n                        {\n                            /* This path is a special case that will only get\n                             * executed if the task was holding multiple mutexes\n                             * and the mutexes were given back in an order that is\n                             * different to that in which they were taken. */\n                            queueYIELD_IF_USING_PREEMPTION();\n                        }\n                        else\n                        {\n                            mtCOVERAGE_TEST_MARKER();\n                        }\n                    }\n                }\n                #else /* configUSE_QUEUE_SETS */\n                {\n                    xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );\n\n                    /* If there was a task waiting for data to arrive on the\n                     * queue then unblock it now. */\n                    if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\n                    {\n                        if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\n                        {\n                            /* The unblocked task has a priority higher than\n                             * our own so yield immediately.  Yes it is ok to do\n                             * this from within the critical section - the kernel\n                             * takes care of that. */\n                            queueYIELD_IF_USING_PREEMPTION();\n                        }\n                        else\n                        {\n                            mtCOVERAGE_TEST_MARKER();\n                        }\n                    }\n                    else if( xYieldRequired != pdFALSE )\n                    {\n                        /* This path is a special case that will only get\n                         * executed if the task was holding multiple mutexes and\n                         * the mutexes were given back in an order that is\n                         * different to that in which they were taken. */\n                        queueYIELD_IF_USING_PREEMPTION();\n                    }\n                    else\n                    {\n                        mtCOVERAGE_TEST_MARKER();\n                    }\n                }\n                #endif /* configUSE_QUEUE_SETS */\n\n                taskEXIT_CRITICAL();\n                return pdPASS;\n            }\n            else\n            {\n                if( xTicksToWait == ( TickType_t ) 0 )\n                {\n                    /* The queue was full and no block time is specified (or\n                     * the block time has expired) so leave now. */\n                    taskEXIT_CRITICAL();\n\n                    /* Return to the original privilege level before exiting\n                     * the function. */\n                    traceQUEUE_SEND_FAILED( pxQueue );\n                    return errQUEUE_FULL;\n                }\n                else if( xEntryTimeSet == pdFALSE )\n                {\n                    /* The queue was full and a block time was specified so\n                     * configure the timeout structure. */\n                    vTaskInternalSetTimeOutState( &xTimeOut );\n                    xEntryTimeSet = pdTRUE;\n                }\n                else\n                {\n                    /* Entry time was already set. */\n                    mtCOVERAGE_TEST_MARKER();\n                }\n            }\n        }\n        taskEXIT_CRITICAL();\n\n        /* Interrupts and other tasks can send to and receive from the queue\n         * now the critical section has been exited. */\n\n        vTaskSuspendAll();\n        prvLockQueue( pxQueue );\n\n        /* Update the timeout state to see if it has expired yet. */\n        if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )\n        {\n            if( prvIsQueueFull( pxQueue ) != pdFALSE )\n            {\n                traceBLOCKING_ON_QUEUE_SEND( pxQueue );\n                vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );\n\n                /* Unlocking the queue means queue events can effect the\n                 * event list. It is possible that interrupts occurring now\n                 * remove this task from the event list again - but as the\n                 * scheduler is suspended the task will go onto the pending\n                 * ready list instead of the actual ready list. */\n                prvUnlockQueue( pxQueue );\n\n                /* Resuming the scheduler will move tasks from the pending\n                 * ready list into the ready list - so it is feasible that this\n                 * task is already in the ready list before it yields - in which\n                 * case the yield will not cause a context switch unless there\n                 * is also a higher priority task in the pending ready list. */\n                if( xTaskResumeAll() == pdFALSE )\n                {\n                    portYIELD_WITHIN_API();\n                }\n            }\n            else\n            {\n                /* Try again. */\n                prvUnlockQueue( pxQueue );\n                ( void ) xTaskResumeAll();\n            }\n        }\n        else\n        {\n            /* The timeout has expired. */\n            prvUnlockQueue( pxQueue );\n            ( void ) xTaskResumeAll();\n\n            traceQUEUE_SEND_FAILED( pxQueue );\n            return errQUEUE_FULL;\n        }\n    } /*lint -restore */\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue,\n                                     const void * const pvItemToQueue,\n                                     BaseType_t * const pxHigherPriorityTaskWoken,\n                                     const BaseType_t xCopyPosition )\n{\n    BaseType_t xReturn;\n    UBaseType_t uxSavedInterruptStatus;\n    Queue_t * const pxQueue = xQueue;\n\n    configASSERT( pxQueue );\n    configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );\n    configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );\n\n    /* RTOS ports that support interrupt nesting have the concept of a maximum\n     * system call (or maximum API call) interrupt priority.  Interrupts that are\n     * above the maximum system call priority are kept permanently enabled, even\n     * when the RTOS kernel is in a critical section, but cannot make any calls to\n     * FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h\n     * then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion\n     * failure if a FreeRTOS API function is called from an interrupt that has been\n     * assigned a priority above the configured maximum system call priority.\n     * Only FreeRTOS functions that end in FromISR can be called from interrupts\n     * that have been assigned a priority at or (logically) below the maximum\n     * system call interrupt priority.  FreeRTOS maintains a separate interrupt\n     * safe API to ensure interrupt entry is as fast and as simple as possible.\n     * More information (albeit Cortex-M specific) is provided on the following\n     * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\n    portASSERT_IF_INTERRUPT_PRIORITY_INVALID();\n\n    /* Similar to xQueueGenericSend, except without blocking if there is no room\n     * in the queue.  Also don't directly wake a task that was blocked on a queue\n     * read, instead return a flag to say whether a context switch is required or\n     * not (i.e. has a task with a higher priority than us been woken by this\n     * post). */\n    uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();\n    {\n        if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )\n        {\n            const int8_t cTxLock = pxQueue->cTxLock;\n            const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting;\n\n            traceQUEUE_SEND_FROM_ISR( pxQueue );\n\n            /* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a\n             *  semaphore or mutex.  That means prvCopyDataToQueue() cannot result\n             *  in a task disinheriting a priority and prvCopyDataToQueue() can be\n             *  called here even though the disinherit function does not check if\n             *  the scheduler is suspended before accessing the ready lists. */\n            ( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );\n\n            /* The event list is not altered if the queue is locked.  This will\n             * be done when the queue is unlocked later. */\n            if( cTxLock == queueUNLOCKED )\n            {\n                #if ( configUSE_QUEUE_SETS == 1 )\n                {\n                    if( pxQueue->pxQueueSetContainer != NULL )\n                    {\n                        if( ( xCopyPosition == queueOVERWRITE ) && ( uxPreviousMessagesWaiting != ( UBaseType_t ) 0 ) )\n                        {\n                            /* Do not notify the queue set as an existing item\n                             * was overwritten in the queue so the number of items\n                             * in the queue has not changed. */\n                            mtCOVERAGE_TEST_MARKER();\n                        }\n                        else if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE )\n                        {\n                            /* The queue is a member of a queue set, and posting\n                             * to the queue set caused a higher priority task to\n                             * unblock.  A context switch is required. */\n                            if( pxHigherPriorityTaskWoken != NULL )\n                            {\n                                *pxHigherPriorityTaskWoken = pdTRUE;\n                            }\n                            else\n                            {\n                                mtCOVERAGE_TEST_MARKER();\n                            }\n                        }\n                        else\n                        {\n                            mtCOVERAGE_TEST_MARKER();\n                        }\n                    }\n                    else\n                    {\n                        if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\n                        {\n                            if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\n                            {\n                                /* The task waiting has a higher priority so\n                                 *  record that a context switch is required. */\n                                if( pxHigherPriorityTaskWoken != NULL )\n                                {\n                                    *pxHigherPriorityTaskWoken = pdTRUE;\n                                }\n                                else\n                                {\n                                    mtCOVERAGE_TEST_MARKER();\n                                }\n                            }\n                            else\n                            {\n                                mtCOVERAGE_TEST_MARKER();\n                            }\n                        }\n                        else\n                        {\n                            mtCOVERAGE_TEST_MARKER();\n                        }\n                    }\n                }\n                #else /* configUSE_QUEUE_SETS */\n                {\n                    if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\n                    {\n                        if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\n                        {\n                            /* The task waiting has a higher priority so record that a\n                             * context switch is required. */\n                            if( pxHigherPriorityTaskWoken != NULL )\n                            {\n                                *pxHigherPriorityTaskWoken = pdTRUE;\n                            }\n                            else\n                            {\n                                mtCOVERAGE_TEST_MARKER();\n                            }\n                        }\n                        else\n                        {\n                            mtCOVERAGE_TEST_MARKER();\n                        }\n                    }\n                    else\n                    {\n                        mtCOVERAGE_TEST_MARKER();\n                    }\n\n                    /* Not used in this path. */\n                    ( void ) uxPreviousMessagesWaiting;\n                }\n                #endif /* configUSE_QUEUE_SETS */\n            }\n            else\n            {\n                /* Increment the lock count so the task that unlocks the queue\n                 * knows that data was posted while it was locked. */\n                prvIncrementQueueTxLock( pxQueue, cTxLock );\n            }\n\n            xReturn = pdPASS;\n        }\n        else\n        {\n            traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );\n            xReturn = errQUEUE_FULL;\n        }\n    }\n    portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\n\n    return xReturn;\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xQueueGiveFromISR( QueueHandle_t xQueue,\n                              BaseType_t * const pxHigherPriorityTaskWoken )\n{\n    BaseType_t xReturn;\n    UBaseType_t uxSavedInterruptStatus;\n    Queue_t * const pxQueue = xQueue;\n\n    /* Similar to xQueueGenericSendFromISR() but used with semaphores where the\n     * item size is 0.  Don't directly wake a task that was blocked on a queue\n     * read, instead return a flag to say whether a context switch is required or\n     * not (i.e. has a task with a higher priority than us been woken by this\n     * post). */\n\n    configASSERT( pxQueue );\n\n    /* xQueueGenericSendFromISR() should be used instead of xQueueGiveFromISR()\n     * if the item size is not 0. */\n    configASSERT( pxQueue->uxItemSize == 0 );\n\n    /* Normally a mutex would not be given from an interrupt, especially if\n     * there is a mutex holder, as priority inheritance makes no sense for an\n     * interrupts, only tasks. */\n    configASSERT( !( ( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) && ( pxQueue->u.xSemaphore.xMutexHolder != NULL ) ) );\n\n    /* RTOS ports that support interrupt nesting have the concept of a maximum\n     * system call (or maximum API call) interrupt priority.  Interrupts that are\n     * above the maximum system call priority are kept permanently enabled, even\n     * when the RTOS kernel is in a critical section, but cannot make any calls to\n     * FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h\n     * then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion\n     * failure if a FreeRTOS API function is called from an interrupt that has been\n     * assigned a priority above the configured maximum system call priority.\n     * Only FreeRTOS functions that end in FromISR can be called from interrupts\n     * that have been assigned a priority at or (logically) below the maximum\n     * system call interrupt priority.  FreeRTOS maintains a separate interrupt\n     * safe API to ensure interrupt entry is as fast and as simple as possible.\n     * More information (albeit Cortex-M specific) is provided on the following\n     * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\n    portASSERT_IF_INTERRUPT_PRIORITY_INVALID();\n\n    uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();\n    {\n        const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;\n\n        /* When the queue is used to implement a semaphore no data is ever\n         * moved through the queue but it is still valid to see if the queue 'has\n         * space'. */\n        if( uxMessagesWaiting < pxQueue->uxLength )\n        {\n            const int8_t cTxLock = pxQueue->cTxLock;\n\n            traceQUEUE_SEND_FROM_ISR( pxQueue );\n\n            /* A task can only have an inherited priority if it is a mutex\n             * holder - and if there is a mutex holder then the mutex cannot be\n             * given from an ISR.  As this is the ISR version of the function it\n             * can be assumed there is no mutex holder and no need to determine if\n             * priority disinheritance is needed.  Simply increase the count of\n             * messages (semaphores) available. */\n            pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;\n\n            /* The event list is not altered if the queue is locked.  This will\n             * be done when the queue is unlocked later. */\n            if( cTxLock == queueUNLOCKED )\n            {\n                #if ( configUSE_QUEUE_SETS == 1 )\n                {\n                    if( pxQueue->pxQueueSetContainer != NULL )\n                    {\n                        if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE )\n                        {\n                            /* The semaphore is a member of a queue set, and\n                             * posting to the queue set caused a higher priority\n                             * task to unblock.  A context switch is required. */\n                            if( pxHigherPriorityTaskWoken != NULL )\n                            {\n                                *pxHigherPriorityTaskWoken = pdTRUE;\n                            }\n                            else\n                            {\n                                mtCOVERAGE_TEST_MARKER();\n                            }\n                        }\n                        else\n                        {\n                            mtCOVERAGE_TEST_MARKER();\n                        }\n                    }\n                    else\n                    {\n                        if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\n                        {\n                            if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\n                            {\n                                /* The task waiting has a higher priority so\n                                 *  record that a context switch is required. */\n                                if( pxHigherPriorityTaskWoken != NULL )\n                                {\n                                    *pxHigherPriorityTaskWoken = pdTRUE;\n                                }\n                                else\n                                {\n                                    mtCOVERAGE_TEST_MARKER();\n                                }\n                            }\n                            else\n                            {\n                                mtCOVERAGE_TEST_MARKER();\n                            }\n                        }\n                        else\n                        {\n                            mtCOVERAGE_TEST_MARKER();\n                        }\n                    }\n                }\n                #else /* configUSE_QUEUE_SETS */\n                {\n                    if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\n                    {\n                        if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\n                        {\n                            /* The task waiting has a higher priority so record that a\n                             * context switch is required. */\n                            if( pxHigherPriorityTaskWoken != NULL )\n                            {\n                                *pxHigherPriorityTaskWoken = pdTRUE;\n                            }\n                            else\n                            {\n                                mtCOVERAGE_TEST_MARKER();\n                            }\n                        }\n                        else\n                        {\n                            mtCOVERAGE_TEST_MARKER();\n                        }\n                    }\n                    else\n                    {\n                        mtCOVERAGE_TEST_MARKER();\n                    }\n                }\n                #endif /* configUSE_QUEUE_SETS */\n            }\n            else\n            {\n                /* Increment the lock count so the task that unlocks the queue\n                 * knows that data was posted while it was locked. */\n                prvIncrementQueueTxLock( pxQueue, cTxLock );\n            }\n\n            xReturn = pdPASS;\n        }\n        else\n        {\n            traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );\n            xReturn = errQUEUE_FULL;\n        }\n    }\n    portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\n\n    return xReturn;\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xQueueReceive( QueueHandle_t xQueue,\n                          void * const pvBuffer,\n                          TickType_t xTicksToWait )\n{\n    BaseType_t xEntryTimeSet = pdFALSE;\n    TimeOut_t xTimeOut;\n    Queue_t * const pxQueue = xQueue;\n\n    /* Check the pointer is not NULL. */\n    configASSERT( ( pxQueue ) );\n\n    /* The buffer into which data is received can only be NULL if the data size\n     * is zero (so no data is copied into the buffer). */\n    configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );\n\n    /* Cannot block if the scheduler is suspended. */\n    #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )\n    {\n        configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );\n    }\n    #endif\n\n    /*lint -save -e904  This function relaxes the coding standard somewhat to\n     * allow return statements within the function itself.  This is done in the\n     * interest of execution time efficiency. */\n    for( ; ; )\n    {\n        taskENTER_CRITICAL();\n        {\n            const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;\n\n            /* Is there data in the queue now?  To be running the calling task\n             * must be the highest priority task wanting to access the queue. */\n            if( uxMessagesWaiting > ( UBaseType_t ) 0 )\n            {\n                /* Data available, remove one item. */\n                prvCopyDataFromQueue( pxQueue, pvBuffer );\n                traceQUEUE_RECEIVE( pxQueue );\n                pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;\n\n                /* There is now space in the queue, were any tasks waiting to\n                 * post to the queue?  If so, unblock the highest priority waiting\n                 * task. */\n                if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )\n                {\n                    if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )\n                    {\n                        queueYIELD_IF_USING_PREEMPTION();\n                    }\n                    else\n                    {\n                        mtCOVERAGE_TEST_MARKER();\n                    }\n                }\n                else\n                {\n                    mtCOVERAGE_TEST_MARKER();\n                }\n\n                taskEXIT_CRITICAL();\n                return pdPASS;\n            }\n            else\n            {\n                if( xTicksToWait == ( TickType_t ) 0 )\n                {\n                    /* The queue was empty and no block time is specified (or\n                     * the block time has expired) so leave now. */\n                    taskEXIT_CRITICAL();\n                    traceQUEUE_RECEIVE_FAILED( pxQueue );\n                    return errQUEUE_EMPTY;\n                }\n                else if( xEntryTimeSet == pdFALSE )\n                {\n                    /* The queue was empty and a block time was specified so\n                     * configure the timeout structure. */\n                    vTaskInternalSetTimeOutState( &xTimeOut );\n                    xEntryTimeSet = pdTRUE;\n                }\n                else\n                {\n                    /* Entry time was already set. */\n                    mtCOVERAGE_TEST_MARKER();\n                }\n            }\n        }\n        taskEXIT_CRITICAL();\n\n        /* Interrupts and other tasks can send to and receive from the queue\n         * now the critical section has been exited. */\n\n        vTaskSuspendAll();\n        prvLockQueue( pxQueue );\n\n        /* Update the timeout state to see if it has expired yet. */\n        if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )\n        {\n            /* The timeout has not expired.  If the queue is still empty place\n             * the task on the list of tasks waiting to receive from the queue. */\n            if( prvIsQueueEmpty( pxQueue ) != pdFALSE )\n            {\n                traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );\n                vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );\n                prvUnlockQueue( pxQueue );\n\n                if( xTaskResumeAll() == pdFALSE )\n                {\n                    portYIELD_WITHIN_API();\n                }\n                else\n                {\n                    mtCOVERAGE_TEST_MARKER();\n                }\n            }\n            else\n            {\n                /* The queue contains data again.  Loop back to try and read the\n                 * data. */\n                prvUnlockQueue( pxQueue );\n                ( void ) xTaskResumeAll();\n            }\n        }\n        else\n        {\n            /* Timed out.  If there is no data in the queue exit, otherwise loop\n             * back and attempt to read the data. */\n            prvUnlockQueue( pxQueue );\n            ( void ) xTaskResumeAll();\n\n            if( prvIsQueueEmpty( pxQueue ) != pdFALSE )\n            {\n                traceQUEUE_RECEIVE_FAILED( pxQueue );\n                return errQUEUE_EMPTY;\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n    } /*lint -restore */\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue,\n                                TickType_t xTicksToWait )\n{\n    BaseType_t xEntryTimeSet = pdFALSE;\n    TimeOut_t xTimeOut;\n    Queue_t * const pxQueue = xQueue;\n\n    #if ( configUSE_MUTEXES == 1 )\n        BaseType_t xInheritanceOccurred = pdFALSE;\n    #endif\n\n    /* Check the queue pointer is not NULL. */\n    configASSERT( ( pxQueue ) );\n\n    /* Check this really is a semaphore, in which case the item size will be\n     * 0. */\n    configASSERT( pxQueue->uxItemSize == 0 );\n\n    /* Cannot block if the scheduler is suspended. */\n    #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )\n    {\n        configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );\n    }\n    #endif\n\n    /*lint -save -e904 This function relaxes the coding standard somewhat to allow return\n     * statements within the function itself.  This is done in the interest\n     * of execution time efficiency. */\n    for( ; ; )\n    {\n        taskENTER_CRITICAL();\n        {\n            /* Semaphores are queues with an item size of 0, and where the\n             * number of messages in the queue is the semaphore's count value. */\n            const UBaseType_t uxSemaphoreCount = pxQueue->uxMessagesWaiting;\n\n            /* Is there data in the queue now?  To be running the calling task\n             * must be the highest priority task wanting to access the queue. */\n            if( uxSemaphoreCount > ( UBaseType_t ) 0 )\n            {\n                traceQUEUE_RECEIVE( pxQueue );\n\n                /* Semaphores are queues with a data size of zero and where the\n                 * messages waiting is the semaphore's count.  Reduce the count. */\n                pxQueue->uxMessagesWaiting = uxSemaphoreCount - ( UBaseType_t ) 1;\n\n                #if ( configUSE_MUTEXES == 1 )\n                {\n                    if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )\n                    {\n                        /* Record the information required to implement\n                         * priority inheritance should it become necessary. */\n                        pxQueue->u.xSemaphore.xMutexHolder = pvTaskIncrementMutexHeldCount();\n                    }\n                    else\n                    {\n                        mtCOVERAGE_TEST_MARKER();\n                    }\n                }\n                #endif /* configUSE_MUTEXES */\n\n                /* Check to see if other tasks are blocked waiting to give the\n                 * semaphore, and if so, unblock the highest priority such task. */\n                if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )\n                {\n                    if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )\n                    {\n                        queueYIELD_IF_USING_PREEMPTION();\n                    }\n                    else\n                    {\n                        mtCOVERAGE_TEST_MARKER();\n                    }\n                }\n                else\n                {\n                    mtCOVERAGE_TEST_MARKER();\n                }\n\n                taskEXIT_CRITICAL();\n                return pdPASS;\n            }\n            else\n            {\n                if( xTicksToWait == ( TickType_t ) 0 )\n                {\n                    /* The semaphore count was 0 and no block time is specified\n                     * (or the block time has expired) so exit now. */\n                    taskEXIT_CRITICAL();\n                    traceQUEUE_RECEIVE_FAILED( pxQueue );\n                    return errQUEUE_EMPTY;\n                }\n                else if( xEntryTimeSet == pdFALSE )\n                {\n                    /* The semaphore count was 0 and a block time was specified\n                     * so configure the timeout structure ready to block. */\n                    vTaskInternalSetTimeOutState( &xTimeOut );\n                    xEntryTimeSet = pdTRUE;\n                }\n                else\n                {\n                    /* Entry time was already set. */\n                    mtCOVERAGE_TEST_MARKER();\n                }\n            }\n        }\n        taskEXIT_CRITICAL();\n\n        /* Interrupts and other tasks can give to and take from the semaphore\n         * now the critical section has been exited. */\n\n        vTaskSuspendAll();\n        prvLockQueue( pxQueue );\n\n        /* Update the timeout state to see if it has expired yet. */\n        if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )\n        {\n            /* A block time is specified and not expired.  If the semaphore\n             * count is 0 then enter the Blocked state to wait for a semaphore to\n             * become available.  As semaphores are implemented with queues the\n             * queue being empty is equivalent to the semaphore count being 0. */\n            if( prvIsQueueEmpty( pxQueue ) != pdFALSE )\n            {\n                traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );\n\n                #if ( configUSE_MUTEXES == 1 )\n                {\n                    if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )\n                    {\n                        taskENTER_CRITICAL();\n                        {\n                            xInheritanceOccurred = xTaskPriorityInherit( pxQueue->u.xSemaphore.xMutexHolder );\n                        }\n                        taskEXIT_CRITICAL();\n                    }\n                    else\n                    {\n                        mtCOVERAGE_TEST_MARKER();\n                    }\n                }\n                #endif /* if ( configUSE_MUTEXES == 1 ) */\n\n                vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );\n                prvUnlockQueue( pxQueue );\n\n                if( xTaskResumeAll() == pdFALSE )\n                {\n                    portYIELD_WITHIN_API();\n                }\n                else\n                {\n                    mtCOVERAGE_TEST_MARKER();\n                }\n            }\n            else\n            {\n                /* There was no timeout and the semaphore count was not 0, so\n                 * attempt to take the semaphore again. */\n                prvUnlockQueue( pxQueue );\n                ( void ) xTaskResumeAll();\n            }\n        }\n        else\n        {\n            /* Timed out. */\n            prvUnlockQueue( pxQueue );\n            ( void ) xTaskResumeAll();\n\n            /* If the semaphore count is 0 exit now as the timeout has\n             * expired.  Otherwise return to attempt to take the semaphore that is\n             * known to be available.  As semaphores are implemented by queues the\n             * queue being empty is equivalent to the semaphore count being 0. */\n            if( prvIsQueueEmpty( pxQueue ) != pdFALSE )\n            {\n                #if ( configUSE_MUTEXES == 1 )\n                {\n                    /* xInheritanceOccurred could only have be set if\n                     * pxQueue->uxQueueType == queueQUEUE_IS_MUTEX so no need to\n                     * test the mutex type again to check it is actually a mutex. */\n                    if( xInheritanceOccurred != pdFALSE )\n                    {\n                        taskENTER_CRITICAL();\n                        {\n                            UBaseType_t uxHighestWaitingPriority;\n\n                            /* This task blocking on the mutex caused another\n                             * task to inherit this task's priority.  Now this task\n                             * has timed out the priority should be disinherited\n                             * again, but only as low as the next highest priority\n                             * task that is waiting for the same mutex. */\n                            uxHighestWaitingPriority = prvGetDisinheritPriorityAfterTimeout( pxQueue );\n                            vTaskPriorityDisinheritAfterTimeout( pxQueue->u.xSemaphore.xMutexHolder, uxHighestWaitingPriority );\n                        }\n                        taskEXIT_CRITICAL();\n                    }\n                }\n                #endif /* configUSE_MUTEXES */\n\n                traceQUEUE_RECEIVE_FAILED( pxQueue );\n                return errQUEUE_EMPTY;\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n    } /*lint -restore */\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xQueuePeek( QueueHandle_t xQueue,\n                       void * const pvBuffer,\n                       TickType_t xTicksToWait )\n{\n    BaseType_t xEntryTimeSet = pdFALSE;\n    TimeOut_t xTimeOut;\n    int8_t * pcOriginalReadPosition;\n    Queue_t * const pxQueue = xQueue;\n\n    /* Check the pointer is not NULL. */\n    configASSERT( ( pxQueue ) );\n\n    /* The buffer into which data is received can only be NULL if the data size\n     * is zero (so no data is copied into the buffer. */\n    configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );\n\n    /* Cannot block if the scheduler is suspended. */\n    #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )\n    {\n        configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );\n    }\n    #endif\n\n    /*lint -save -e904  This function relaxes the coding standard somewhat to\n     * allow return statements within the function itself.  This is done in the\n     * interest of execution time efficiency. */\n    for( ; ; )\n    {\n        taskENTER_CRITICAL();\n        {\n            const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;\n\n            /* Is there data in the queue now?  To be running the calling task\n             * must be the highest priority task wanting to access the queue. */\n            if( uxMessagesWaiting > ( UBaseType_t ) 0 )\n            {\n                /* Remember the read position so it can be reset after the data\n                 * is read from the queue as this function is only peeking the\n                 * data, not removing it. */\n                pcOriginalReadPosition = pxQueue->u.xQueue.pcReadFrom;\n\n                prvCopyDataFromQueue( pxQueue, pvBuffer );\n                traceQUEUE_PEEK( pxQueue );\n\n                /* The data is not being removed, so reset the read pointer. */\n                pxQueue->u.xQueue.pcReadFrom = pcOriginalReadPosition;\n\n                /* The data is being left in the queue, so see if there are\n                 * any other tasks waiting for the data. */\n                if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\n                {\n                    if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\n                    {\n                        /* The task waiting has a higher priority than this task. */\n                        queueYIELD_IF_USING_PREEMPTION();\n                    }\n                    else\n                    {\n                        mtCOVERAGE_TEST_MARKER();\n                    }\n                }\n                else\n                {\n                    mtCOVERAGE_TEST_MARKER();\n                }\n\n                taskEXIT_CRITICAL();\n                return pdPASS;\n            }\n            else\n            {\n                if( xTicksToWait == ( TickType_t ) 0 )\n                {\n                    /* The queue was empty and no block time is specified (or\n                     * the block time has expired) so leave now. */\n                    taskEXIT_CRITICAL();\n                    traceQUEUE_PEEK_FAILED( pxQueue );\n                    return errQUEUE_EMPTY;\n                }\n                else if( xEntryTimeSet == pdFALSE )\n                {\n                    /* The queue was empty and a block time was specified so\n                     * configure the timeout structure ready to enter the blocked\n                     * state. */\n                    vTaskInternalSetTimeOutState( &xTimeOut );\n                    xEntryTimeSet = pdTRUE;\n                }\n                else\n                {\n                    /* Entry time was already set. */\n                    mtCOVERAGE_TEST_MARKER();\n                }\n            }\n        }\n        taskEXIT_CRITICAL();\n\n        /* Interrupts and other tasks can send to and receive from the queue\n         * now that the critical section has been exited. */\n\n        vTaskSuspendAll();\n        prvLockQueue( pxQueue );\n\n        /* Update the timeout state to see if it has expired yet. */\n        if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )\n        {\n            /* Timeout has not expired yet, check to see if there is data in the\n            * queue now, and if not enter the Blocked state to wait for data. */\n            if( prvIsQueueEmpty( pxQueue ) != pdFALSE )\n            {\n                traceBLOCKING_ON_QUEUE_PEEK( pxQueue );\n                vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );\n                prvUnlockQueue( pxQueue );\n\n                if( xTaskResumeAll() == pdFALSE )\n                {\n                    portYIELD_WITHIN_API();\n                }\n                else\n                {\n                    mtCOVERAGE_TEST_MARKER();\n                }\n            }\n            else\n            {\n                /* There is data in the queue now, so don't enter the blocked\n                 * state, instead return to try and obtain the data. */\n                prvUnlockQueue( pxQueue );\n                ( void ) xTaskResumeAll();\n            }\n        }\n        else\n        {\n            /* The timeout has expired.  If there is still no data in the queue\n             * exit, otherwise go back and try to read the data again. */\n            prvUnlockQueue( pxQueue );\n            ( void ) xTaskResumeAll();\n\n            if( prvIsQueueEmpty( pxQueue ) != pdFALSE )\n            {\n                traceQUEUE_PEEK_FAILED( pxQueue );\n                return errQUEUE_EMPTY;\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n    } /*lint -restore */\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue,\n                                 void * const pvBuffer,\n                                 BaseType_t * const pxHigherPriorityTaskWoken )\n{\n    BaseType_t xReturn;\n    UBaseType_t uxSavedInterruptStatus;\n    Queue_t * const pxQueue = xQueue;\n\n    configASSERT( pxQueue );\n    configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );\n\n    /* RTOS ports that support interrupt nesting have the concept of a maximum\n     * system call (or maximum API call) interrupt priority.  Interrupts that are\n     * above the maximum system call priority are kept permanently enabled, even\n     * when the RTOS kernel is in a critical section, but cannot make any calls to\n     * FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h\n     * then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion\n     * failure if a FreeRTOS API function is called from an interrupt that has been\n     * assigned a priority above the configured maximum system call priority.\n     * Only FreeRTOS functions that end in FromISR can be called from interrupts\n     * that have been assigned a priority at or (logically) below the maximum\n     * system call interrupt priority.  FreeRTOS maintains a separate interrupt\n     * safe API to ensure interrupt entry is as fast and as simple as possible.\n     * More information (albeit Cortex-M specific) is provided on the following\n     * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\n    portASSERT_IF_INTERRUPT_PRIORITY_INVALID();\n\n    uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();\n    {\n        const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;\n\n        /* Cannot block in an ISR, so check there is data available. */\n        if( uxMessagesWaiting > ( UBaseType_t ) 0 )\n        {\n            const int8_t cRxLock = pxQueue->cRxLock;\n\n            traceQUEUE_RECEIVE_FROM_ISR( pxQueue );\n\n            prvCopyDataFromQueue( pxQueue, pvBuffer );\n            pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;\n\n            /* If the queue is locked the event list will not be modified.\n             * Instead update the lock count so the task that unlocks the queue\n             * will know that an ISR has removed data while the queue was\n             * locked. */\n            if( cRxLock == queueUNLOCKED )\n            {\n                if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )\n                {\n                    if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )\n                    {\n                        /* The task waiting has a higher priority than us so\n                         * force a context switch. */\n                        if( pxHigherPriorityTaskWoken != NULL )\n                        {\n                            *pxHigherPriorityTaskWoken = pdTRUE;\n                        }\n                        else\n                        {\n                            mtCOVERAGE_TEST_MARKER();\n                        }\n                    }\n                    else\n                    {\n                        mtCOVERAGE_TEST_MARKER();\n                    }\n                }\n                else\n                {\n                    mtCOVERAGE_TEST_MARKER();\n                }\n            }\n            else\n            {\n                /* Increment the lock count so the task that unlocks the queue\n                 * knows that data was removed while it was locked. */\n                prvIncrementQueueRxLock( pxQueue, cRxLock );\n            }\n\n            xReturn = pdPASS;\n        }\n        else\n        {\n            xReturn = pdFAIL;\n            traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue );\n        }\n    }\n    portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\n\n    return xReturn;\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xQueuePeekFromISR( QueueHandle_t xQueue,\n                              void * const pvBuffer )\n{\n    BaseType_t xReturn;\n    UBaseType_t uxSavedInterruptStatus;\n    int8_t * pcOriginalReadPosition;\n    Queue_t * const pxQueue = xQueue;\n\n    configASSERT( pxQueue );\n    configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );\n    configASSERT( pxQueue->uxItemSize != 0 ); /* Can't peek a semaphore. */\n\n    /* RTOS ports that support interrupt nesting have the concept of a maximum\n     * system call (or maximum API call) interrupt priority.  Interrupts that are\n     * above the maximum system call priority are kept permanently enabled, even\n     * when the RTOS kernel is in a critical section, but cannot make any calls to\n     * FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h\n     * then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion\n     * failure if a FreeRTOS API function is called from an interrupt that has been\n     * assigned a priority above the configured maximum system call priority.\n     * Only FreeRTOS functions that end in FromISR can be called from interrupts\n     * that have been assigned a priority at or (logically) below the maximum\n     * system call interrupt priority.  FreeRTOS maintains a separate interrupt\n     * safe API to ensure interrupt entry is as fast and as simple as possible.\n     * More information (albeit Cortex-M specific) is provided on the following\n     * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\n    portASSERT_IF_INTERRUPT_PRIORITY_INVALID();\n\n    uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();\n    {\n        /* Cannot block in an ISR, so check there is data available. */\n        if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )\n        {\n            traceQUEUE_PEEK_FROM_ISR( pxQueue );\n\n            /* Remember the read position so it can be reset as nothing is\n             * actually being removed from the queue. */\n            pcOriginalReadPosition = pxQueue->u.xQueue.pcReadFrom;\n            prvCopyDataFromQueue( pxQueue, pvBuffer );\n            pxQueue->u.xQueue.pcReadFrom = pcOriginalReadPosition;\n\n            xReturn = pdPASS;\n        }\n        else\n        {\n            xReturn = pdFAIL;\n            traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue );\n        }\n    }\n    portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\n\n    return xReturn;\n}\n/*-----------------------------------------------------------*/\n\nUBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue )\n{\n    UBaseType_t uxReturn;\n\n    configASSERT( xQueue );\n\n    taskENTER_CRITICAL();\n    {\n        uxReturn = ( ( Queue_t * ) xQueue )->uxMessagesWaiting;\n    }\n    taskEXIT_CRITICAL();\n\n    return uxReturn;\n} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */\n/*-----------------------------------------------------------*/\n\nUBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue )\n{\n    UBaseType_t uxReturn;\n    Queue_t * const pxQueue = xQueue;\n\n    configASSERT( pxQueue );\n\n    taskENTER_CRITICAL();\n    {\n        uxReturn = pxQueue->uxLength - pxQueue->uxMessagesWaiting;\n    }\n    taskEXIT_CRITICAL();\n\n    return uxReturn;\n} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */\n/*-----------------------------------------------------------*/\n\nUBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue )\n{\n    UBaseType_t uxReturn;\n    Queue_t * const pxQueue = xQueue;\n\n    configASSERT( pxQueue );\n    uxReturn = pxQueue->uxMessagesWaiting;\n\n    return uxReturn;\n} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */\n/*-----------------------------------------------------------*/\n\nvoid vQueueDelete( QueueHandle_t xQueue )\n{\n    Queue_t * const pxQueue = xQueue;\n\n    configASSERT( pxQueue );\n    traceQUEUE_DELETE( pxQueue );\n\n    #if ( configQUEUE_REGISTRY_SIZE > 0 )\n    {\n        vQueueUnregisterQueue( pxQueue );\n    }\n    #endif\n\n    #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) )\n    {\n        /* The queue can only have been allocated dynamically - free it\n         * again. */\n        vPortFree( pxQueue );\n    }\n    #elif ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )\n    {\n        /* The queue could have been allocated statically or dynamically, so\n         * check before attempting to free the memory. */\n        if( pxQueue->ucStaticallyAllocated == ( uint8_t ) pdFALSE )\n        {\n            vPortFree( pxQueue );\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n    }\n    #else /* if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) ) */\n    {\n        /* The queue must have been statically allocated, so is not going to be\n         * deleted.  Avoid compiler warnings about the unused parameter. */\n        ( void ) pxQueue;\n    }\n    #endif /* configSUPPORT_DYNAMIC_ALLOCATION */\n}\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TRACE_FACILITY == 1 )\n\n    UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue )\n    {\n        return ( ( Queue_t * ) xQueue )->uxQueueNumber;\n    }\n\n#endif /* configUSE_TRACE_FACILITY */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TRACE_FACILITY == 1 )\n\n    void vQueueSetQueueNumber( QueueHandle_t xQueue,\n                               UBaseType_t uxQueueNumber )\n    {\n        ( ( Queue_t * ) xQueue )->uxQueueNumber = uxQueueNumber;\n    }\n\n#endif /* configUSE_TRACE_FACILITY */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TRACE_FACILITY == 1 )\n\n    uint8_t ucQueueGetQueueType( QueueHandle_t xQueue )\n    {\n        return ( ( Queue_t * ) xQueue )->ucQueueType;\n    }\n\n#endif /* configUSE_TRACE_FACILITY */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_MUTEXES == 1 )\n\n    static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue )\n    {\n        UBaseType_t uxHighestPriorityOfWaitingTasks;\n\n        /* If a task waiting for a mutex causes the mutex holder to inherit a\n         * priority, but the waiting task times out, then the holder should\n         * disinherit the priority - but only down to the highest priority of any\n         * other tasks that are waiting for the same mutex.  For this purpose,\n         * return the priority of the highest priority task that is waiting for the\n         * mutex. */\n        if( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0U )\n        {\n            uxHighestPriorityOfWaitingTasks = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) );\n        }\n        else\n        {\n            uxHighestPriorityOfWaitingTasks = tskIDLE_PRIORITY;\n        }\n\n        return uxHighestPriorityOfWaitingTasks;\n    }\n\n#endif /* configUSE_MUTEXES */\n/*-----------------------------------------------------------*/\n\nstatic BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue,\n                                      const void * pvItemToQueue,\n                                      const BaseType_t xPosition )\n{\n    BaseType_t xReturn = pdFALSE;\n    UBaseType_t uxMessagesWaiting;\n\n    /* This function is called from a critical section. */\n\n    uxMessagesWaiting = pxQueue->uxMessagesWaiting;\n\n    if( pxQueue->uxItemSize == ( UBaseType_t ) 0 )\n    {\n        #if ( configUSE_MUTEXES == 1 )\n        {\n            if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )\n            {\n                /* The mutex is no longer being held. */\n                xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder );\n                pxQueue->u.xSemaphore.xMutexHolder = NULL;\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n        #endif /* configUSE_MUTEXES */\n    }\n    else if( xPosition == queueSEND_TO_BACK )\n    {\n        ( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */\n        pxQueue->pcWriteTo += pxQueue->uxItemSize;                                                       /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */\n\n        if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail )                                             /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */\n        {\n            pxQueue->pcWriteTo = pxQueue->pcHead;\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n    }\n    else\n    {\n        ( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes.  Assert checks null pointer only used when length is 0. */\n        pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize;\n\n        if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */\n        {\n            pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize );\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n\n        if( xPosition == queueOVERWRITE )\n        {\n            if( uxMessagesWaiting > ( UBaseType_t ) 0 )\n            {\n                /* An item is not being added but overwritten, so subtract\n                 * one from the recorded number of items in the queue so when\n                 * one is added again below the number of recorded items remains\n                 * correct. */\n                --uxMessagesWaiting;\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n    }\n\n    pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;\n\n    return xReturn;\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvCopyDataFromQueue( Queue_t * const pxQueue,\n                                  void * const pvBuffer )\n{\n    if( pxQueue->uxItemSize != ( UBaseType_t ) 0 )\n    {\n        pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize;           /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */\n\n        if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */\n        {\n            pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n\n        ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports.  Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */\n    }\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvUnlockQueue( Queue_t * const pxQueue )\n{\n    /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. */\n\n    /* The lock counts contains the number of extra data items placed or\n     * removed from the queue while the queue was locked.  When a queue is\n     * locked items can be added or removed, but the event lists cannot be\n     * updated. */\n    taskENTER_CRITICAL();\n    {\n        int8_t cTxLock = pxQueue->cTxLock;\n\n        /* See if data was added to the queue while it was locked. */\n        while( cTxLock > queueLOCKED_UNMODIFIED )\n        {\n            /* Data was posted while the queue was locked.  Are any tasks\n             * blocked waiting for data to become available? */\n            #if ( configUSE_QUEUE_SETS == 1 )\n            {\n                if( pxQueue->pxQueueSetContainer != NULL )\n                {\n                    if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE )\n                    {\n                        /* The queue is a member of a queue set, and posting to\n                         * the queue set caused a higher priority task to unblock.\n                         * A context switch is required. */\n                        vTaskMissedYield();\n                    }\n                    else\n                    {\n                        mtCOVERAGE_TEST_MARKER();\n                    }\n                }\n                else\n                {\n                    /* Tasks that are removed from the event list will get\n                     * added to the pending ready list as the scheduler is still\n                     * suspended. */\n                    if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\n                    {\n                        if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\n                        {\n                            /* The task waiting has a higher priority so record that a\n                             * context switch is required. */\n                            vTaskMissedYield();\n                        }\n                        else\n                        {\n                            mtCOVERAGE_TEST_MARKER();\n                        }\n                    }\n                    else\n                    {\n                        break;\n                    }\n                }\n            }\n            #else /* configUSE_QUEUE_SETS */\n            {\n                /* Tasks that are removed from the event list will get added to\n                 * the pending ready list as the scheduler is still suspended. */\n                if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\n                {\n                    if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\n                    {\n                        /* The task waiting has a higher priority so record that\n                         * a context switch is required. */\n                        vTaskMissedYield();\n                    }\n                    else\n                    {\n                        mtCOVERAGE_TEST_MARKER();\n                    }\n                }\n                else\n                {\n                    break;\n                }\n            }\n            #endif /* configUSE_QUEUE_SETS */\n\n            --cTxLock;\n        }\n\n        pxQueue->cTxLock = queueUNLOCKED;\n    }\n    taskEXIT_CRITICAL();\n\n    /* Do the same for the Rx lock. */\n    taskENTER_CRITICAL();\n    {\n        int8_t cRxLock = pxQueue->cRxLock;\n\n        while( cRxLock > queueLOCKED_UNMODIFIED )\n        {\n            if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )\n            {\n                if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )\n                {\n                    vTaskMissedYield();\n                }\n                else\n                {\n                    mtCOVERAGE_TEST_MARKER();\n                }\n\n                --cRxLock;\n            }\n            else\n            {\n                break;\n            }\n        }\n\n        pxQueue->cRxLock = queueUNLOCKED;\n    }\n    taskEXIT_CRITICAL();\n}\n/*-----------------------------------------------------------*/\n\nstatic BaseType_t prvIsQueueEmpty( const Queue_t * pxQueue )\n{\n    BaseType_t xReturn;\n\n    taskENTER_CRITICAL();\n    {\n        if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )\n        {\n            xReturn = pdTRUE;\n        }\n        else\n        {\n            xReturn = pdFALSE;\n        }\n    }\n    taskEXIT_CRITICAL();\n\n    return xReturn;\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue )\n{\n    BaseType_t xReturn;\n    Queue_t * const pxQueue = xQueue;\n\n    configASSERT( pxQueue );\n\n    if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )\n    {\n        xReturn = pdTRUE;\n    }\n    else\n    {\n        xReturn = pdFALSE;\n    }\n\n    return xReturn;\n} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */\n/*-----------------------------------------------------------*/\n\nstatic BaseType_t prvIsQueueFull( const Queue_t * pxQueue )\n{\n    BaseType_t xReturn;\n\n    taskENTER_CRITICAL();\n    {\n        if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )\n        {\n            xReturn = pdTRUE;\n        }\n        else\n        {\n            xReturn = pdFALSE;\n        }\n    }\n    taskEXIT_CRITICAL();\n\n    return xReturn;\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )\n{\n    BaseType_t xReturn;\n    Queue_t * const pxQueue = xQueue;\n\n    configASSERT( pxQueue );\n\n    if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )\n    {\n        xReturn = pdTRUE;\n    }\n    else\n    {\n        xReturn = pdFALSE;\n    }\n\n    return xReturn;\n} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_CO_ROUTINES == 1 )\n\n    BaseType_t xQueueCRSend( QueueHandle_t xQueue,\n                             const void * pvItemToQueue,\n                             TickType_t xTicksToWait )\n    {\n        BaseType_t xReturn;\n        Queue_t * const pxQueue = xQueue;\n\n        /* If the queue is already full we may have to block.  A critical section\n         * is required to prevent an interrupt removing something from the queue\n         * between the check to see if the queue is full and blocking on the queue. */\n        portDISABLE_INTERRUPTS();\n        {\n            if( prvIsQueueFull( pxQueue ) != pdFALSE )\n            {\n                /* The queue is full - do we want to block or just leave without\n                 * posting? */\n                if( xTicksToWait > ( TickType_t ) 0 )\n                {\n                    /* As this is called from a coroutine we cannot block directly, but\n                     * return indicating that we need to block. */\n                    vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToSend ) );\n                    portENABLE_INTERRUPTS();\n                    return errQUEUE_BLOCKED;\n                }\n                else\n                {\n                    portENABLE_INTERRUPTS();\n                    return errQUEUE_FULL;\n                }\n            }\n        }\n        portENABLE_INTERRUPTS();\n\n        portDISABLE_INTERRUPTS();\n        {\n            if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )\n            {\n                /* There is room in the queue, copy the data into the queue. */\n                prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK );\n                xReturn = pdPASS;\n\n                /* Were any co-routines waiting for data to become available? */\n                if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\n                {\n                    /* In this instance the co-routine could be placed directly\n                     * into the ready list as we are within a critical section.\n                     * Instead the same pending ready list mechanism is used as if\n                     * the event were caused from within an interrupt. */\n                    if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\n                    {\n                        /* The co-routine waiting has a higher priority so record\n                         * that a yield might be appropriate. */\n                        xReturn = errQUEUE_YIELD;\n                    }\n                    else\n                    {\n                        mtCOVERAGE_TEST_MARKER();\n                    }\n                }\n                else\n                {\n                    mtCOVERAGE_TEST_MARKER();\n                }\n            }\n            else\n            {\n                xReturn = errQUEUE_FULL;\n            }\n        }\n        portENABLE_INTERRUPTS();\n\n        return xReturn;\n    }\n\n#endif /* configUSE_CO_ROUTINES */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_CO_ROUTINES == 1 )\n\n    BaseType_t xQueueCRReceive( QueueHandle_t xQueue,\n                                void * pvBuffer,\n                                TickType_t xTicksToWait )\n    {\n        BaseType_t xReturn;\n        Queue_t * const pxQueue = xQueue;\n\n        /* If the queue is already empty we may have to block.  A critical section\n         * is required to prevent an interrupt adding something to the queue\n         * between the check to see if the queue is empty and blocking on the queue. */\n        portDISABLE_INTERRUPTS();\n        {\n            if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )\n            {\n                /* There are no messages in the queue, do we want to block or just\n                 * leave with nothing? */\n                if( xTicksToWait > ( TickType_t ) 0 )\n                {\n                    /* As this is a co-routine we cannot block directly, but return\n                     * indicating that we need to block. */\n                    vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToReceive ) );\n                    portENABLE_INTERRUPTS();\n                    return errQUEUE_BLOCKED;\n                }\n                else\n                {\n                    portENABLE_INTERRUPTS();\n                    return errQUEUE_FULL;\n                }\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n        portENABLE_INTERRUPTS();\n\n        portDISABLE_INTERRUPTS();\n        {\n            if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )\n            {\n                /* Data is available from the queue. */\n                pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize;\n\n                if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail )\n                {\n                    pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;\n                }\n                else\n                {\n                    mtCOVERAGE_TEST_MARKER();\n                }\n\n                --( pxQueue->uxMessagesWaiting );\n                ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );\n\n                xReturn = pdPASS;\n\n                /* Were any co-routines waiting for space to become available? */\n                if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )\n                {\n                    /* In this instance the co-routine could be placed directly\n                     * into the ready list as we are within a critical section.\n                     * Instead the same pending ready list mechanism is used as if\n                     * the event were caused from within an interrupt. */\n                    if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )\n                    {\n                        xReturn = errQUEUE_YIELD;\n                    }\n                    else\n                    {\n                        mtCOVERAGE_TEST_MARKER();\n                    }\n                }\n                else\n                {\n                    mtCOVERAGE_TEST_MARKER();\n                }\n            }\n            else\n            {\n                xReturn = pdFAIL;\n            }\n        }\n        portENABLE_INTERRUPTS();\n\n        return xReturn;\n    }\n\n#endif /* configUSE_CO_ROUTINES */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_CO_ROUTINES == 1 )\n\n    BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue,\n                                    const void * pvItemToQueue,\n                                    BaseType_t xCoRoutinePreviouslyWoken )\n    {\n        Queue_t * const pxQueue = xQueue;\n\n        /* Cannot block within an ISR so if there is no space on the queue then\n         * exit without doing anything. */\n        if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )\n        {\n            prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK );\n\n            /* We only want to wake one co-routine per ISR, so check that a\n             * co-routine has not already been woken. */\n            if( xCoRoutinePreviouslyWoken == pdFALSE )\n            {\n                if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\n                {\n                    if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\n                    {\n                        return pdTRUE;\n                    }\n                    else\n                    {\n                        mtCOVERAGE_TEST_MARKER();\n                    }\n                }\n                else\n                {\n                    mtCOVERAGE_TEST_MARKER();\n                }\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n\n        return xCoRoutinePreviouslyWoken;\n    }\n\n#endif /* configUSE_CO_ROUTINES */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_CO_ROUTINES == 1 )\n\n    BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue,\n                                       void * pvBuffer,\n                                       BaseType_t * pxCoRoutineWoken )\n    {\n        BaseType_t xReturn;\n        Queue_t * const pxQueue = xQueue;\n\n        /* We cannot block from an ISR, so check there is data available. If\n         * not then just leave without doing anything. */\n        if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )\n        {\n            /* Copy the data from the queue. */\n            pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize;\n\n            if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail )\n            {\n                pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n\n            --( pxQueue->uxMessagesWaiting );\n            ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );\n\n            if( ( *pxCoRoutineWoken ) == pdFALSE )\n            {\n                if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )\n                {\n                    if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )\n                    {\n                        *pxCoRoutineWoken = pdTRUE;\n                    }\n                    else\n                    {\n                        mtCOVERAGE_TEST_MARKER();\n                    }\n                }\n                else\n                {\n                    mtCOVERAGE_TEST_MARKER();\n                }\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n\n            xReturn = pdPASS;\n        }\n        else\n        {\n            xReturn = pdFAIL;\n        }\n\n        return xReturn;\n    }\n\n#endif /* configUSE_CO_ROUTINES */\n/*-----------------------------------------------------------*/\n\n#if ( configQUEUE_REGISTRY_SIZE > 0 )\n\n    void vQueueAddToRegistry( QueueHandle_t xQueue,\n                              const char * pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n    {\n        UBaseType_t ux;\n        QueueRegistryItem_t * pxEntryToWrite = NULL;\n\n        configASSERT( xQueue );\n\n        if( pcQueueName != NULL )\n        {\n            /* See if there is an empty space in the registry.  A NULL name denotes\n             * a free slot. */\n            for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )\n            {\n                /* Replace an existing entry if the queue is already in the registry. */\n                if( xQueue == xQueueRegistry[ ux ].xHandle )\n                {\n                    pxEntryToWrite = &( xQueueRegistry[ ux ] );\n                    break;\n                }\n                /* Otherwise, store in the next empty location */\n                else if( ( pxEntryToWrite == NULL ) && ( xQueueRegistry[ ux ].pcQueueName == NULL ) )\n                {\n                    pxEntryToWrite = &( xQueueRegistry[ ux ] );\n                }\n                else\n                {\n                    mtCOVERAGE_TEST_MARKER();\n                }\n            }\n        }\n\n        if( pxEntryToWrite != NULL )\n        {\n            /* Store the information on this queue. */\n            pxEntryToWrite->pcQueueName = pcQueueName;\n            pxEntryToWrite->xHandle = xQueue;\n\n            traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName );\n        }\n    }\n\n#endif /* configQUEUE_REGISTRY_SIZE */\n/*-----------------------------------------------------------*/\n\n#if ( configQUEUE_REGISTRY_SIZE > 0 )\n\n    const char * pcQueueGetName( QueueHandle_t xQueue ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n    {\n        UBaseType_t ux;\n        const char * pcReturn = NULL; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n\n        configASSERT( xQueue );\n\n        /* Note there is nothing here to protect against another task adding or\n         * removing entries from the registry while it is being searched. */\n\n        for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )\n        {\n            if( xQueueRegistry[ ux ].xHandle == xQueue )\n            {\n                pcReturn = xQueueRegistry[ ux ].pcQueueName;\n                break;\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n\n        return pcReturn;\n    } /*lint !e818 xQueue cannot be a pointer to const because it is a typedef. */\n\n#endif /* configQUEUE_REGISTRY_SIZE */\n/*-----------------------------------------------------------*/\n\n#if ( configQUEUE_REGISTRY_SIZE > 0 )\n\n    void vQueueUnregisterQueue( QueueHandle_t xQueue )\n    {\n        UBaseType_t ux;\n\n        configASSERT( xQueue );\n\n        /* See if the handle of the queue being unregistered in actually in the\n         * registry. */\n        for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )\n        {\n            if( xQueueRegistry[ ux ].xHandle == xQueue )\n            {\n                /* Set the name to NULL to show that this slot if free again. */\n                xQueueRegistry[ ux ].pcQueueName = NULL;\n\n                /* Set the handle to NULL to ensure the same queue handle cannot\n                 * appear in the registry twice if it is added, removed, then\n                 * added again. */\n                xQueueRegistry[ ux ].xHandle = ( QueueHandle_t ) 0;\n                break;\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n    } /*lint !e818 xQueue could not be pointer to const because it is a typedef. */\n\n#endif /* configQUEUE_REGISTRY_SIZE */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TIMERS == 1 )\n\n    void vQueueWaitForMessageRestricted( QueueHandle_t xQueue,\n                                         TickType_t xTicksToWait,\n                                         const BaseType_t xWaitIndefinitely )\n    {\n        Queue_t * const pxQueue = xQueue;\n\n        /* This function should not be called by application code hence the\n         * 'Restricted' in its name.  It is not part of the public API.  It is\n         * designed for use by kernel code, and has special calling requirements.\n         * It can result in vListInsert() being called on a list that can only\n         * possibly ever have one item in it, so the list will be fast, but even\n         * so it should be called with the scheduler locked and not from a critical\n         * section. */\n\n        /* Only do anything if there are no messages in the queue.  This function\n         *  will not actually cause the task to block, just place it on a blocked\n         *  list.  It will not block until the scheduler is unlocked - at which\n         *  time a yield will be performed.  If an item is added to the queue while\n         *  the queue is locked, and the calling task blocks on the queue, then the\n         *  calling task will be immediately unblocked when the queue is unlocked. */\n        prvLockQueue( pxQueue );\n\n        if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U )\n        {\n            /* There is nothing in the queue, block for the specified period. */\n            vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely );\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n\n        prvUnlockQueue( pxQueue );\n    }\n\n#endif /* configUSE_TIMERS */\n/*-----------------------------------------------------------*/\n\n#if ( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )\n\n    QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength )\n    {\n        QueueSetHandle_t pxQueue;\n\n        pxQueue = xQueueGenericCreate( uxEventQueueLength, ( UBaseType_t ) sizeof( Queue_t * ), queueQUEUE_TYPE_SET );\n\n        return pxQueue;\n    }\n\n#endif /* configUSE_QUEUE_SETS */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_QUEUE_SETS == 1 )\n\n    BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,\n                               QueueSetHandle_t xQueueSet )\n    {\n        BaseType_t xReturn;\n\n        taskENTER_CRITICAL();\n        {\n            if( ( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer != NULL )\n            {\n                /* Cannot add a queue/semaphore to more than one queue set. */\n                xReturn = pdFAIL;\n            }\n            else if( ( ( Queue_t * ) xQueueOrSemaphore )->uxMessagesWaiting != ( UBaseType_t ) 0 )\n            {\n                /* Cannot add a queue/semaphore to a queue set if there are already\n                 * items in the queue/semaphore. */\n                xReturn = pdFAIL;\n            }\n            else\n            {\n                ( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer = xQueueSet;\n                xReturn = pdPASS;\n            }\n        }\n        taskEXIT_CRITICAL();\n\n        return xReturn;\n    }\n\n#endif /* configUSE_QUEUE_SETS */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_QUEUE_SETS == 1 )\n\n    BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore,\n                                    QueueSetHandle_t xQueueSet )\n    {\n        BaseType_t xReturn;\n        Queue_t * const pxQueueOrSemaphore = ( Queue_t * ) xQueueOrSemaphore;\n\n        if( pxQueueOrSemaphore->pxQueueSetContainer != xQueueSet )\n        {\n            /* The queue was not a member of the set. */\n            xReturn = pdFAIL;\n        }\n        else if( pxQueueOrSemaphore->uxMessagesWaiting != ( UBaseType_t ) 0 )\n        {\n            /* It is dangerous to remove a queue from a set when the queue is\n             * not empty because the queue set will still hold pending events for\n             * the queue. */\n            xReturn = pdFAIL;\n        }\n        else\n        {\n            taskENTER_CRITICAL();\n            {\n                /* The queue is no longer contained in the set. */\n                pxQueueOrSemaphore->pxQueueSetContainer = NULL;\n            }\n            taskEXIT_CRITICAL();\n            xReturn = pdPASS;\n        }\n\n        return xReturn;\n    } /*lint !e818 xQueueSet could not be declared as pointing to const as it is a typedef. */\n\n#endif /* configUSE_QUEUE_SETS */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_QUEUE_SETS == 1 )\n\n    QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet,\n                                                TickType_t const xTicksToWait )\n    {\n        QueueSetMemberHandle_t xReturn = NULL;\n\n        ( void ) xQueueReceive( ( QueueHandle_t ) xQueueSet, &xReturn, xTicksToWait ); /*lint !e961 Casting from one typedef to another is not redundant. */\n        return xReturn;\n    }\n\n#endif /* configUSE_QUEUE_SETS */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_QUEUE_SETS == 1 )\n\n    QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet )\n    {\n        QueueSetMemberHandle_t xReturn = NULL;\n\n        ( void ) xQueueReceiveFromISR( ( QueueHandle_t ) xQueueSet, &xReturn, NULL ); /*lint !e961 Casting from one typedef to another is not redundant. */\n        return xReturn;\n    }\n\n#endif /* configUSE_QUEUE_SETS */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_QUEUE_SETS == 1 )\n\n    static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue )\n    {\n        Queue_t * pxQueueSetContainer = pxQueue->pxQueueSetContainer;\n        BaseType_t xReturn = pdFALSE;\n\n        /* This function must be called form a critical section. */\n\n        /* The following line is not reachable in unit tests because every call\n         * to prvNotifyQueueSetContainer is preceded by a check that\n         * pxQueueSetContainer != NULL */\n        configASSERT( pxQueueSetContainer ); /* LCOV_EXCL_BR_LINE */\n        configASSERT( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength );\n\n        if( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength )\n        {\n            const int8_t cTxLock = pxQueueSetContainer->cTxLock;\n\n            traceQUEUE_SET_SEND( pxQueueSetContainer );\n\n            /* The data copied is the handle of the queue that contains data. */\n            xReturn = prvCopyDataToQueue( pxQueueSetContainer, &pxQueue, queueSEND_TO_BACK );\n\n            if( cTxLock == queueUNLOCKED )\n            {\n                if( listLIST_IS_EMPTY( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) == pdFALSE )\n                {\n                    if( xTaskRemoveFromEventList( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) != pdFALSE )\n                    {\n                        /* The task waiting has a higher priority. */\n                        xReturn = pdTRUE;\n                    }\n                    else\n                    {\n                        mtCOVERAGE_TEST_MARKER();\n                    }\n                }\n                else\n                {\n                    mtCOVERAGE_TEST_MARKER();\n                }\n            }\n            else\n            {\n                prvIncrementQueueTxLock( pxQueueSetContainer, cTxLock );\n            }\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n\n        return xReturn;\n    }\n\n#endif /* configUSE_QUEUE_SETS */\n"
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    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Standard includes. */\n#include <stdint.h>\n#include <string.h>\n\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\n * all the API functions to use the MPU wrappers.  That should only be done when\n * task.h is included from an application file. */\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/* FreeRTOS includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n#include \"stream_buffer.h\"\n\n#if ( configUSE_TASK_NOTIFICATIONS != 1 )\n    #error configUSE_TASK_NOTIFICATIONS must be set to 1 to build stream_buffer.c\n#endif\n\n#if ( INCLUDE_xTaskGetCurrentTaskHandle != 1 )\n    #error INCLUDE_xTaskGetCurrentTaskHandle must be set to 1 to build stream_buffer.c\n#endif\n\n/* Lint e961, e9021 and e750 are suppressed as a MISRA exception justified\n * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined\n * for the header files above, but not in this file, in order to generate the\n * correct privileged Vs unprivileged linkage and placement. */\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */\n\n/* If the user has not provided application specific Rx notification macros,\n * or #defined the notification macros away, then provide default implementations\n * that uses task notifications. */\n/*lint -save -e9026 Function like macros allowed and needed here so they can be overridden. */\n#ifndef sbRECEIVE_COMPLETED\n    #define sbRECEIVE_COMPLETED( pxStreamBuffer )                         \\\n    vTaskSuspendAll();                                                    \\\n    {                                                                     \\\n        if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )              \\\n        {                                                                 \\\n            ( void ) xTaskNotify( ( pxStreamBuffer )->xTaskWaitingToSend, \\\n                                  ( uint32_t ) 0,                         \\\n                                  eNoAction );                            \\\n            ( pxStreamBuffer )->xTaskWaitingToSend = NULL;                \\\n        }                                                                 \\\n    }                                                                     \\\n    ( void ) xTaskResumeAll();\n#endif /* sbRECEIVE_COMPLETED */\n\n/* If user has provided a per-instance receive complete callback, then\n * invoke the callback else use the receive complete macro which is provided by default for all instances.\n */\n#if ( configUSE_SB_COMPLETED_CALLBACK == 1 )\n    #define prvRECEIVE_COMPLETED( pxStreamBuffer )                                               \\\n    {                                                                                            \\\n        if( ( pxStreamBuffer )->pxReceiveCompletedCallback != NULL )                             \\\n        {                                                                                        \\\n            ( pxStreamBuffer )->pxReceiveCompletedCallback( ( pxStreamBuffer ), pdFALSE, NULL ); \\\n        }                                                                                        \\\n        else                                                                                     \\\n        {                                                                                        \\\n            sbRECEIVE_COMPLETED( ( pxStreamBuffer ) );                                           \\\n        }                                                                                        \\\n    }\n#else /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */\n    #define prvRECEIVE_COMPLETED( pxStreamBuffer )    sbRECEIVE_COMPLETED( ( pxStreamBuffer ) )\n#endif /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */\n\n#ifndef sbRECEIVE_COMPLETED_FROM_ISR\n    #define sbRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer,                            \\\n                                          pxHigherPriorityTaskWoken )                \\\n    {                                                                                \\\n        UBaseType_t uxSavedInterruptStatus;                                          \\\n                                                                                     \\\n        uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();  \\\n        {                                                                            \\\n            if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )                     \\\n            {                                                                        \\\n                ( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToSend, \\\n                                             ( uint32_t ) 0,                         \\\n                                             eNoAction,                              \\\n                                             ( pxHigherPriorityTaskWoken ) );        \\\n                ( pxStreamBuffer )->xTaskWaitingToSend = NULL;                       \\\n            }                                                                        \\\n        }                                                                            \\\n        portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );                 \\\n    }\n#endif /* sbRECEIVE_COMPLETED_FROM_ISR */\n\n#if ( configUSE_SB_COMPLETED_CALLBACK == 1 )\n    #define prvRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer,                                                               \\\n                                           pxHigherPriorityTaskWoken )                                                   \\\n    {                                                                                                                    \\\n        if( ( pxStreamBuffer )->pxReceiveCompletedCallback != NULL )                                                     \\\n        {                                                                                                                \\\n            ( pxStreamBuffer )->pxReceiveCompletedCallback( ( pxStreamBuffer ), pdTRUE, ( pxHigherPriorityTaskWoken ) ); \\\n        }                                                                                                                \\\n        else                                                                                                             \\\n        {                                                                                                                \\\n            sbRECEIVE_COMPLETED_FROM_ISR( ( pxStreamBuffer ), ( pxHigherPriorityTaskWoken ) );                           \\\n        }                                                                                                                \\\n    }\n#else /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */\n    #define prvRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken ) \\\n    sbRECEIVE_COMPLETED_FROM_ISR( ( pxStreamBuffer ), ( pxHigherPriorityTaskWoken ) )\n#endif /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */\n\n/* If the user has not provided an application specific Tx notification macro,\n * or #defined the notification macro away, then provide a default\n * implementation that uses task notifications.\n */\n#ifndef sbSEND_COMPLETED\n    #define sbSEND_COMPLETED( pxStreamBuffer )                               \\\n    vTaskSuspendAll();                                                       \\\n    {                                                                        \\\n        if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )              \\\n        {                                                                    \\\n            ( void ) xTaskNotify( ( pxStreamBuffer )->xTaskWaitingToReceive, \\\n                                  ( uint32_t ) 0,                            \\\n                                  eNoAction );                               \\\n            ( pxStreamBuffer )->xTaskWaitingToReceive = NULL;                \\\n        }                                                                    \\\n    }                                                                        \\\n    ( void ) xTaskResumeAll();\n#endif /* sbSEND_COMPLETED */\n\n/* If user has provided a per-instance send completed callback, then\n * invoke the callback else use the send complete macro which is provided by default for all instances.\n */\n#if ( configUSE_SB_COMPLETED_CALLBACK == 1 )\n    #define prvSEND_COMPLETED( pxStreamBuffer )                                           \\\n    {                                                                                     \\\n        if( ( pxStreamBuffer )->pxSendCompletedCallback != NULL )                         \\\n        {                                                                                 \\\n            pxStreamBuffer->pxSendCompletedCallback( ( pxStreamBuffer ), pdFALSE, NULL ); \\\n        }                                                                                 \\\n        else                                                                              \\\n        {                                                                                 \\\n            sbSEND_COMPLETED( ( pxStreamBuffer ) );                                       \\\n        }                                                                                 \\\n    }\n#else /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */\n    #define prvSEND_COMPLETED( pxStreamBuffer )    sbSEND_COMPLETED( ( pxStreamBuffer ) )\n#endif /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */\n\n\n#ifndef sbSEND_COMPLETE_FROM_ISR\n    #define sbSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken )       \\\n    {                                                                                   \\\n        UBaseType_t uxSavedInterruptStatus;                                             \\\n                                                                                        \\\n        uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();     \\\n        {                                                                               \\\n            if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )                     \\\n            {                                                                           \\\n                ( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToReceive, \\\n                                             ( uint32_t ) 0,                            \\\n                                             eNoAction,                                 \\\n                                             ( pxHigherPriorityTaskWoken ) );           \\\n                ( pxStreamBuffer )->xTaskWaitingToReceive = NULL;                       \\\n            }                                                                           \\\n        }                                                                               \\\n        portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );                    \\\n    }\n#endif /* sbSEND_COMPLETE_FROM_ISR */\n\n\n#if ( configUSE_SB_COMPLETED_CALLBACK == 1 )\n    #define prvSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken )                                    \\\n    {                                                                                                                 \\\n        if( ( pxStreamBuffer )->pxSendCompletedCallback != NULL )                                                     \\\n        {                                                                                                             \\\n            ( pxStreamBuffer )->pxSendCompletedCallback( ( pxStreamBuffer ), pdTRUE, ( pxHigherPriorityTaskWoken ) ); \\\n        }                                                                                                             \\\n        else                                                                                                          \\\n        {                                                                                                             \\\n            sbSEND_COMPLETE_FROM_ISR( ( pxStreamBuffer ), ( pxHigherPriorityTaskWoken ) );                            \\\n        }                                                                                                             \\\n    }\n#else /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */\n    #define prvSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken ) \\\n    sbSEND_COMPLETE_FROM_ISR( ( pxStreamBuffer ), ( pxHigherPriorityTaskWoken ) )\n#endif /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */\n\n/*lint -restore (9026) */\n\n/* The number of bytes used to hold the length of a message in the buffer. */\n#define sbBYTES_TO_STORE_MESSAGE_LENGTH    ( sizeof( configMESSAGE_BUFFER_LENGTH_TYPE ) )\n\n/* Bits stored in the ucFlags field of the stream buffer. */\n#define sbFLAGS_IS_MESSAGE_BUFFER          ( ( uint8_t ) 1 ) /* Set if the stream buffer was created as a message buffer, in which case it holds discrete messages rather than a stream. */\n#define sbFLAGS_IS_STATICALLY_ALLOCATED    ( ( uint8_t ) 2 ) /* Set if the stream buffer was created using statically allocated memory. */\n\n/*-----------------------------------------------------------*/\n\n/* Structure that hold state information on the buffer. */\ntypedef struct StreamBufferDef_t                 /*lint !e9058 Style convention uses tag. */\n{\n    volatile size_t xTail;                       /* Index to the next item to read within the buffer. */\n    volatile size_t xHead;                       /* Index to the next item to write within the buffer. */\n    size_t xLength;                              /* The length of the buffer pointed to by pucBuffer. */\n    size_t xTriggerLevelBytes;                   /* The number of bytes that must be in the stream buffer before a task that is waiting for data is unblocked. */\n    volatile TaskHandle_t xTaskWaitingToReceive; /* Holds the handle of a task waiting for data, or NULL if no tasks are waiting. */\n    volatile TaskHandle_t xTaskWaitingToSend;    /* Holds the handle of a task waiting to send data to a message buffer that is full. */\n    uint8_t * pucBuffer;                         /* Points to the buffer itself - that is - the RAM that stores the data passed through the buffer. */\n    uint8_t ucFlags;\n\n    #if ( configUSE_TRACE_FACILITY == 1 )\n        UBaseType_t uxStreamBufferNumber; /* Used for tracing purposes. */\n    #endif\n\n    #if ( configUSE_SB_COMPLETED_CALLBACK == 1 )\n        StreamBufferCallbackFunction_t pxSendCompletedCallback;    /* Optional callback called on send complete. sbSEND_COMPLETED is called if this is NULL. */\n        StreamBufferCallbackFunction_t pxReceiveCompletedCallback; /* Optional callback called on receive complete.  sbRECEIVE_COMPLETED is called if this is NULL. */\n    #endif\n} StreamBuffer_t;\n\n/*\n * The number of bytes available to be read from the buffer.\n */\nstatic size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer ) PRIVILEGED_FUNCTION;\n\n/*\n * Add xCount bytes from pucData into the pxStreamBuffer's data storage area.\n * This function does not update the buffer's xHead pointer, so multiple writes\n * may be chained together \"atomically\". This is useful for Message Buffers where\n * the length and data bytes are written in two separate chunks, and we don't want\n * the reader to see the buffer as having grown until after all data is copied over.\n * This function takes a custom xHead value to indicate where to write to (necessary\n * for chaining) and returns the the resulting xHead position.\n * To mark the write as complete, manually set the buffer's xHead field with the\n * returned xHead from this function.\n */\nstatic size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer,\n                                     const uint8_t * pucData,\n                                     size_t xCount,\n                                     size_t xHead ) PRIVILEGED_FUNCTION;\n\n/*\n * If the stream buffer is being used as a message buffer, then reads an entire\n * message out of the buffer.  If the stream buffer is being used as a stream\n * buffer then read as many bytes as possible from the buffer.\n * prvReadBytesFromBuffer() is called to actually extract the bytes from the\n * buffer's data storage area.\n */\nstatic size_t prvReadMessageFromBuffer( StreamBuffer_t * pxStreamBuffer,\n                                        void * pvRxData,\n                                        size_t xBufferLengthBytes,\n                                        size_t xBytesAvailable ) PRIVILEGED_FUNCTION;\n\n/*\n * If the stream buffer is being used as a message buffer, then writes an entire\n * message to the buffer.  If the stream buffer is being used as a stream\n * buffer then write as many bytes as possible to the buffer.\n * prvWriteBytestoBuffer() is called to actually send the bytes to the buffer's\n * data storage area.\n */\nstatic size_t prvWriteMessageToBuffer( StreamBuffer_t * const pxStreamBuffer,\n                                       const void * pvTxData,\n                                       size_t xDataLengthBytes,\n                                       size_t xSpace,\n                                       size_t xRequiredSpace ) PRIVILEGED_FUNCTION;\n\n/*\n * Copies xCount bytes from the pxStreamBuffer's data storage area to pucData.\n * This function does not update the buffer's xTail pointer, so multiple reads\n * may be chained together \"atomically\". This is useful for Message Buffers where\n * the length and data bytes are read in two separate chunks, and we don't want\n * the writer to see the buffer as having more free space until after all data is\n * copied over, especially if we have to abort the read due to insufficient receiving space.\n * This function takes a custom xTail value to indicate where to read from (necessary\n * for chaining) and returns the the resulting xTail position.\n * To mark the read as complete, manually set the buffer's xTail field with the\n * returned xTail from this function.\n */\nstatic size_t prvReadBytesFromBuffer( StreamBuffer_t * pxStreamBuffer,\n                                      uint8_t * pucData,\n                                      size_t xCount,\n                                      size_t xTail ) PRIVILEGED_FUNCTION;\n\n/*\n * Called by both pxStreamBufferCreate() and pxStreamBufferCreateStatic() to\n * initialise the members of the newly created stream buffer structure.\n */\nstatic void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,\n                                          uint8_t * const pucBuffer,\n                                          size_t xBufferSizeBytes,\n                                          size_t xTriggerLevelBytes,\n                                          uint8_t ucFlags,\n                                          StreamBufferCallbackFunction_t pxSendCompletedCallback,\n                                          StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) PRIVILEGED_FUNCTION;\n\n/*-----------------------------------------------------------*/\n#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n    StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes,\n                                                     size_t xTriggerLevelBytes,\n                                                     BaseType_t xIsMessageBuffer,\n                                                     StreamBufferCallbackFunction_t pxSendCompletedCallback,\n                                                     StreamBufferCallbackFunction_t pxReceiveCompletedCallback )\n    {\n        uint8_t * pucAllocatedMemory;\n        uint8_t ucFlags;\n\n        /* In case the stream buffer is going to be used as a message buffer\n         * (that is, it will hold discrete messages with a little meta data that\n         * says how big the next message is) check the buffer will be large enough\n         * to hold at least one message. */\n        if( xIsMessageBuffer == pdTRUE )\n        {\n            /* Is a message buffer but not statically allocated. */\n            ucFlags = sbFLAGS_IS_MESSAGE_BUFFER;\n            configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH );\n        }\n        else\n        {\n            /* Not a message buffer and not statically allocated. */\n            ucFlags = 0;\n            configASSERT( xBufferSizeBytes > 0 );\n        }\n\n        configASSERT( xTriggerLevelBytes <= xBufferSizeBytes );\n\n        /* A trigger level of 0 would cause a waiting task to unblock even when\n         * the buffer was empty. */\n        if( xTriggerLevelBytes == ( size_t ) 0 )\n        {\n            xTriggerLevelBytes = ( size_t ) 1;\n        }\n\n        /* A stream buffer requires a StreamBuffer_t structure and a buffer.\n         * Both are allocated in a single call to pvPortMalloc().  The\n         * StreamBuffer_t structure is placed at the start of the allocated memory\n         * and the buffer follows immediately after.  The requested size is\n         * incremented so the free space is returned as the user would expect -\n         * this is a quirk of the implementation that means otherwise the free\n         * space would be reported as one byte smaller than would be logically\n         * expected. */\n        if( xBufferSizeBytes < ( xBufferSizeBytes + 1 + sizeof( StreamBuffer_t ) ) )\n        {\n            xBufferSizeBytes++;\n            pucAllocatedMemory = ( uint8_t * ) pvPortMalloc( xBufferSizeBytes + sizeof( StreamBuffer_t ) ); /*lint !e9079 malloc() only returns void*. */\n        }\n        else\n        {\n            pucAllocatedMemory = NULL;\n        }\n\n        if( pucAllocatedMemory != NULL )\n        {\n            prvInitialiseNewStreamBuffer( ( StreamBuffer_t * ) pucAllocatedMemory,       /* Structure at the start of the allocated memory. */ /*lint !e9087 Safe cast as allocated memory is aligned. */ /*lint !e826 Area is not too small and alignment is guaranteed provided malloc() behaves as expected and returns aligned buffer. */\n                                          pucAllocatedMemory + sizeof( StreamBuffer_t ), /* Storage area follows. */ /*lint !e9016 Indexing past structure valid for uint8_t pointer, also storage area has no alignment requirement. */\n                                          xBufferSizeBytes,\n                                          xTriggerLevelBytes,\n                                          ucFlags,\n                                          pxSendCompletedCallback,\n                                          pxReceiveCompletedCallback );\n\n            traceSTREAM_BUFFER_CREATE( ( ( StreamBuffer_t * ) pucAllocatedMemory ), xIsMessageBuffer );\n        }\n        else\n        {\n            traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer );\n        }\n\n        return ( StreamBufferHandle_t ) pucAllocatedMemory; /*lint !e9087 !e826 Safe cast as allocated memory is aligned. */\n    }\n#endif /* configSUPPORT_DYNAMIC_ALLOCATION */\n/*-----------------------------------------------------------*/\n\n#if ( configSUPPORT_STATIC_ALLOCATION == 1 )\n\n    StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,\n                                                           size_t xTriggerLevelBytes,\n                                                           BaseType_t xIsMessageBuffer,\n                                                           uint8_t * const pucStreamBufferStorageArea,\n                                                           StaticStreamBuffer_t * const pxStaticStreamBuffer,\n                                                           StreamBufferCallbackFunction_t pxSendCompletedCallback,\n                                                           StreamBufferCallbackFunction_t pxReceiveCompletedCallback )\n    {\n        StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) pxStaticStreamBuffer; /*lint !e740 !e9087 Safe cast as StaticStreamBuffer_t is opaque Streambuffer_t. */\n        StreamBufferHandle_t xReturn;\n        uint8_t ucFlags;\n\n        configASSERT( pucStreamBufferStorageArea );\n        configASSERT( pxStaticStreamBuffer );\n        configASSERT( xTriggerLevelBytes <= xBufferSizeBytes );\n\n        /* A trigger level of 0 would cause a waiting task to unblock even when\n         * the buffer was empty. */\n        if( xTriggerLevelBytes == ( size_t ) 0 )\n        {\n            xTriggerLevelBytes = ( size_t ) 1;\n        }\n\n        if( xIsMessageBuffer != pdFALSE )\n        {\n            /* Statically allocated message buffer. */\n            ucFlags = sbFLAGS_IS_MESSAGE_BUFFER | sbFLAGS_IS_STATICALLY_ALLOCATED;\n        }\n        else\n        {\n            /* Statically allocated stream buffer. */\n            ucFlags = sbFLAGS_IS_STATICALLY_ALLOCATED;\n        }\n\n        /* In case the stream buffer is going to be used as a message buffer\n         * (that is, it will hold discrete messages with a little meta data that\n         * says how big the next message is) check the buffer will be large enough\n         * to hold at least one message. */\n        configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH );\n\n        #if ( configASSERT_DEFINED == 1 )\n        {\n            /* Sanity check that the size of the structure used to declare a\n             * variable of type StaticStreamBuffer_t equals the size of the real\n             * message buffer structure. */\n            volatile size_t xSize = sizeof( StaticStreamBuffer_t );\n            configASSERT( xSize == sizeof( StreamBuffer_t ) );\n        } /*lint !e529 xSize is referenced is configASSERT() is defined. */\n        #endif /* configASSERT_DEFINED */\n\n        if( ( pucStreamBufferStorageArea != NULL ) && ( pxStaticStreamBuffer != NULL ) )\n        {\n            prvInitialiseNewStreamBuffer( pxStreamBuffer,\n                                          pucStreamBufferStorageArea,\n                                          xBufferSizeBytes,\n                                          xTriggerLevelBytes,\n                                          ucFlags,\n                                          pxSendCompletedCallback,\n                                          pxReceiveCompletedCallback );\n\n            /* Remember this was statically allocated in case it is ever deleted\n             * again. */\n            pxStreamBuffer->ucFlags |= sbFLAGS_IS_STATICALLY_ALLOCATED;\n\n            traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xIsMessageBuffer );\n\n            xReturn = ( StreamBufferHandle_t ) pxStaticStreamBuffer; /*lint !e9087 Data hiding requires cast to opaque type. */\n        }\n        else\n        {\n            xReturn = NULL;\n            traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer );\n        }\n\n        return xReturn;\n    }\n#endif /* ( configSUPPORT_STATIC_ALLOCATION == 1 ) */\n/*-----------------------------------------------------------*/\n\nvoid vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer )\n{\n    StreamBuffer_t * pxStreamBuffer = xStreamBuffer;\n\n    configASSERT( pxStreamBuffer );\n\n    traceSTREAM_BUFFER_DELETE( xStreamBuffer );\n\n    if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) pdFALSE )\n    {\n        #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n        {\n            /* Both the structure and the buffer were allocated using a single call\n            * to pvPortMalloc(), hence only one call to vPortFree() is required. */\n            vPortFree( ( void * ) pxStreamBuffer ); /*lint !e9087 Standard free() semantics require void *, plus pxStreamBuffer was allocated by pvPortMalloc(). */\n        }\n        #else\n        {\n            /* Should not be possible to get here, ucFlags must be corrupt.\n             * Force an assert. */\n            configASSERT( xStreamBuffer == ( StreamBufferHandle_t ) ~0 );\n        }\n        #endif\n    }\n    else\n    {\n        /* The structure and buffer were not allocated dynamically and cannot be\n         * freed - just scrub the structure so future use will assert. */\n        ( void ) memset( pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) );\n    }\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer )\n{\n    StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;\n    BaseType_t xReturn = pdFAIL;\n    StreamBufferCallbackFunction_t pxSendCallback = NULL, pxReceiveCallback = NULL;\n\n    #if ( configUSE_TRACE_FACILITY == 1 )\n        UBaseType_t uxStreamBufferNumber;\n    #endif\n\n    configASSERT( pxStreamBuffer );\n\n    #if ( configUSE_TRACE_FACILITY == 1 )\n    {\n        /* Store the stream buffer number so it can be restored after the\n         * reset. */\n        uxStreamBufferNumber = pxStreamBuffer->uxStreamBufferNumber;\n    }\n    #endif\n\n    /* Can only reset a message buffer if there are no tasks blocked on it. */\n    taskENTER_CRITICAL();\n    {\n        if( ( pxStreamBuffer->xTaskWaitingToReceive == NULL ) && ( pxStreamBuffer->xTaskWaitingToSend == NULL ) )\n        {\n            #if ( configUSE_SB_COMPLETED_CALLBACK == 1 )\n            {\n                pxSendCallback = pxStreamBuffer->pxSendCompletedCallback;\n                pxReceiveCallback = pxStreamBuffer->pxReceiveCompletedCallback;\n            }\n            #endif\n\n            prvInitialiseNewStreamBuffer( pxStreamBuffer,\n                                          pxStreamBuffer->pucBuffer,\n                                          pxStreamBuffer->xLength,\n                                          pxStreamBuffer->xTriggerLevelBytes,\n                                          pxStreamBuffer->ucFlags,\n                                          pxSendCallback,\n                                          pxReceiveCallback );\n\n            #if ( configUSE_TRACE_FACILITY == 1 )\n            {\n                pxStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber;\n            }\n            #endif\n\n            traceSTREAM_BUFFER_RESET( xStreamBuffer );\n\n            xReturn = pdPASS;\n        }\n    }\n    taskEXIT_CRITICAL();\n\n    return xReturn;\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,\n                                         size_t xTriggerLevel )\n{\n    StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;\n    BaseType_t xReturn;\n\n    configASSERT( pxStreamBuffer );\n\n    /* It is not valid for the trigger level to be 0. */\n    if( xTriggerLevel == ( size_t ) 0 )\n    {\n        xTriggerLevel = ( size_t ) 1;\n    }\n\n    /* The trigger level is the number of bytes that must be in the stream\n     * buffer before a task that is waiting for data is unblocked. */\n    if( xTriggerLevel < pxStreamBuffer->xLength )\n    {\n        pxStreamBuffer->xTriggerLevelBytes = xTriggerLevel;\n        xReturn = pdPASS;\n    }\n    else\n    {\n        xReturn = pdFALSE;\n    }\n\n    return xReturn;\n}\n/*-----------------------------------------------------------*/\n\nsize_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer )\n{\n    const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;\n    size_t xSpace;\n    size_t xOriginalTail;\n\n    configASSERT( pxStreamBuffer );\n\n    /* The code below reads xTail and then xHead.  This is safe if the stream\n     * buffer is updated once between the two reads - but not if the stream buffer\n     * is updated more than once between the two reads - hence the loop. */\n    do\n    {\n        xOriginalTail = pxStreamBuffer->xTail;\n        xSpace = pxStreamBuffer->xLength + pxStreamBuffer->xTail;\n        xSpace -= pxStreamBuffer->xHead;\n    } while( xOriginalTail != pxStreamBuffer->xTail );\n\n    xSpace -= ( size_t ) 1;\n\n    if( xSpace >= pxStreamBuffer->xLength )\n    {\n        xSpace -= pxStreamBuffer->xLength;\n    }\n    else\n    {\n        mtCOVERAGE_TEST_MARKER();\n    }\n\n    return xSpace;\n}\n/*-----------------------------------------------------------*/\n\nsize_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer )\n{\n    const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;\n    size_t xReturn;\n\n    configASSERT( pxStreamBuffer );\n\n    xReturn = prvBytesInBuffer( pxStreamBuffer );\n    return xReturn;\n}\n/*-----------------------------------------------------------*/\n\nsize_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,\n                          const void * pvTxData,\n                          size_t xDataLengthBytes,\n                          TickType_t xTicksToWait )\n{\n    StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;\n    size_t xReturn, xSpace = 0;\n    size_t xRequiredSpace = xDataLengthBytes;\n    TimeOut_t xTimeOut;\n    size_t xMaxReportedSpace = 0;\n\n    configASSERT( pvTxData );\n    configASSERT( pxStreamBuffer );\n\n    /* The maximum amount of space a stream buffer will ever report is its length\n     * minus 1. */\n    xMaxReportedSpace = pxStreamBuffer->xLength - ( size_t ) 1;\n\n    /* This send function is used to write to both message buffers and stream\n     * buffers.  If this is a message buffer then the space needed must be\n     * increased by the amount of bytes needed to store the length of the\n     * message. */\n    if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )\n    {\n        xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH;\n\n        /* Overflow? */\n        configASSERT( xRequiredSpace > xDataLengthBytes );\n\n        /* If this is a message buffer then it must be possible to write the\n         * whole message. */\n        if( xRequiredSpace > xMaxReportedSpace )\n        {\n            /* The message would not fit even if the entire buffer was empty,\n             * so don't wait for space. */\n            xTicksToWait = ( TickType_t ) 0;\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n    }\n    else\n    {\n        /* If this is a stream buffer then it is acceptable to write only part\n         * of the message to the buffer.  Cap the length to the total length of\n         * the buffer. */\n        if( xRequiredSpace > xMaxReportedSpace )\n        {\n            xRequiredSpace = xMaxReportedSpace;\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n    }\n\n    if( xTicksToWait != ( TickType_t ) 0 )\n    {\n        vTaskSetTimeOutState( &xTimeOut );\n\n        do\n        {\n            /* Wait until the required number of bytes are free in the message\n             * buffer. */\n            taskENTER_CRITICAL();\n            {\n                xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );\n\n                if( xSpace < xRequiredSpace )\n                {\n                    /* Clear notification state as going to wait for space. */\n                    ( void ) xTaskNotifyStateClear( NULL );\n\n                    /* Should only be one writer. */\n                    configASSERT( pxStreamBuffer->xTaskWaitingToSend == NULL );\n                    pxStreamBuffer->xTaskWaitingToSend = xTaskGetCurrentTaskHandle();\n                }\n                else\n                {\n                    taskEXIT_CRITICAL();\n                    break;\n                }\n            }\n            taskEXIT_CRITICAL();\n\n            traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer );\n            ( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait );\n            pxStreamBuffer->xTaskWaitingToSend = NULL;\n        } while( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE );\n    }\n    else\n    {\n        mtCOVERAGE_TEST_MARKER();\n    }\n\n    if( xSpace == ( size_t ) 0 )\n    {\n        xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );\n    }\n    else\n    {\n        mtCOVERAGE_TEST_MARKER();\n    }\n\n    xReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace );\n\n    if( xReturn > ( size_t ) 0 )\n    {\n        traceSTREAM_BUFFER_SEND( xStreamBuffer, xReturn );\n\n        /* Was a task waiting for the data? */\n        if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes )\n        {\n            prvSEND_COMPLETED( pxStreamBuffer );\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n    }\n    else\n    {\n        mtCOVERAGE_TEST_MARKER();\n        traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer );\n    }\n\n    return xReturn;\n}\n/*-----------------------------------------------------------*/\n\nsize_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,\n                                 const void * pvTxData,\n                                 size_t xDataLengthBytes,\n                                 BaseType_t * const pxHigherPriorityTaskWoken )\n{\n    StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;\n    size_t xReturn, xSpace;\n    size_t xRequiredSpace = xDataLengthBytes;\n\n    configASSERT( pvTxData );\n    configASSERT( pxStreamBuffer );\n\n    /* This send function is used to write to both message buffers and stream\n     * buffers.  If this is a message buffer then the space needed must be\n     * increased by the amount of bytes needed to store the length of the\n     * message. */\n    if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )\n    {\n        xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH;\n    }\n    else\n    {\n        mtCOVERAGE_TEST_MARKER();\n    }\n\n    xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );\n    xReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace );\n\n    if( xReturn > ( size_t ) 0 )\n    {\n        /* Was a task waiting for the data? */\n        if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes )\n        {\n            prvSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken );\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n    }\n    else\n    {\n        mtCOVERAGE_TEST_MARKER();\n    }\n\n    traceSTREAM_BUFFER_SEND_FROM_ISR( xStreamBuffer, xReturn );\n\n    return xReturn;\n}\n/*-----------------------------------------------------------*/\n\nstatic size_t prvWriteMessageToBuffer( StreamBuffer_t * const pxStreamBuffer,\n                                       const void * pvTxData,\n                                       size_t xDataLengthBytes,\n                                       size_t xSpace,\n                                       size_t xRequiredSpace )\n{\n    size_t xNextHead = pxStreamBuffer->xHead;\n    configMESSAGE_BUFFER_LENGTH_TYPE xMessageLength;\n\n    if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )\n    {\n        /* This is a message buffer, as opposed to a stream buffer. */\n\n        /* Convert xDataLengthBytes to the message length type. */\n        xMessageLength = ( configMESSAGE_BUFFER_LENGTH_TYPE ) xDataLengthBytes;\n\n        /* Ensure the data length given fits within configMESSAGE_BUFFER_LENGTH_TYPE. */\n        configASSERT( ( size_t ) xMessageLength == xDataLengthBytes );\n\n        if( xSpace >= xRequiredSpace )\n        {\n            /* There is enough space to write both the message length and the message\n             * itself into the buffer.  Start by writing the length of the data, the data\n             * itself will be written later in this function. */\n            xNextHead = prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) &( xMessageLength ), sbBYTES_TO_STORE_MESSAGE_LENGTH, xNextHead );\n        }\n        else\n        {\n            /* Not enough space, so do not write data to the buffer. */\n            xDataLengthBytes = 0;\n        }\n    }\n    else\n    {\n        /* This is a stream buffer, as opposed to a message buffer, so writing a\n         * stream of bytes rather than discrete messages.  Plan to write as many\n         * bytes as possible. */\n        xDataLengthBytes = configMIN( xDataLengthBytes, xSpace );\n    }\n\n    if( xDataLengthBytes != ( size_t ) 0 )\n    {\n        /* Write the data to the buffer. */\n        pxStreamBuffer->xHead = prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) pvTxData, xDataLengthBytes, xNextHead ); /*lint !e9079 Storage buffer is implemented as uint8_t for ease of sizing, alignment and access. */\n    }\n\n    return xDataLengthBytes;\n}\n/*-----------------------------------------------------------*/\n\nsize_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,\n                             void * pvRxData,\n                             size_t xBufferLengthBytes,\n                             TickType_t xTicksToWait )\n{\n    StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;\n    size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength;\n\n    configASSERT( pvRxData );\n    configASSERT( pxStreamBuffer );\n\n    /* This receive function is used by both message buffers, which store\n     * discrete messages, and stream buffers, which store a continuous stream of\n     * bytes.  Discrete messages include an additional\n     * sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the\n     * message. */\n    if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )\n    {\n        xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;\n    }\n    else\n    {\n        xBytesToStoreMessageLength = 0;\n    }\n\n    if( xTicksToWait != ( TickType_t ) 0 )\n    {\n        /* Checking if there is data and clearing the notification state must be\n         * performed atomically. */\n        taskENTER_CRITICAL();\n        {\n            xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );\n\n            /* If this function was invoked by a message buffer read then\n             * xBytesToStoreMessageLength holds the number of bytes used to hold\n             * the length of the next discrete message.  If this function was\n             * invoked by a stream buffer read then xBytesToStoreMessageLength will\n             * be 0. */\n            if( xBytesAvailable <= xBytesToStoreMessageLength )\n            {\n                /* Clear notification state as going to wait for data. */\n                ( void ) xTaskNotifyStateClear( NULL );\n\n                /* Should only be one reader. */\n                configASSERT( pxStreamBuffer->xTaskWaitingToReceive == NULL );\n                pxStreamBuffer->xTaskWaitingToReceive = xTaskGetCurrentTaskHandle();\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n        taskEXIT_CRITICAL();\n\n        if( xBytesAvailable <= xBytesToStoreMessageLength )\n        {\n            /* Wait for data to be available. */\n            traceBLOCKING_ON_STREAM_BUFFER_RECEIVE( xStreamBuffer );\n            ( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait );\n            pxStreamBuffer->xTaskWaitingToReceive = NULL;\n\n            /* Recheck the data available after blocking. */\n            xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n    }\n    else\n    {\n        xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );\n    }\n\n    /* Whether receiving a discrete message (where xBytesToStoreMessageLength\n     * holds the number of bytes used to store the message length) or a stream of\n     * bytes (where xBytesToStoreMessageLength is zero), the number of bytes\n     * available must be greater than xBytesToStoreMessageLength to be able to\n     * read bytes from the buffer. */\n    if( xBytesAvailable > xBytesToStoreMessageLength )\n    {\n        xReceivedLength = prvReadMessageFromBuffer( pxStreamBuffer, pvRxData, xBufferLengthBytes, xBytesAvailable );\n\n        /* Was a task waiting for space in the buffer? */\n        if( xReceivedLength != ( size_t ) 0 )\n        {\n            traceSTREAM_BUFFER_RECEIVE( xStreamBuffer, xReceivedLength );\n            prvRECEIVE_COMPLETED( xStreamBuffer );\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n    }\n    else\n    {\n        traceSTREAM_BUFFER_RECEIVE_FAILED( xStreamBuffer );\n        mtCOVERAGE_TEST_MARKER();\n    }\n\n    return xReceivedLength;\n}\n/*-----------------------------------------------------------*/\n\nsize_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer )\n{\n    StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;\n    size_t xReturn, xBytesAvailable;\n    configMESSAGE_BUFFER_LENGTH_TYPE xTempReturn;\n\n    configASSERT( pxStreamBuffer );\n\n    /* Ensure the stream buffer is being used as a message buffer. */\n    if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )\n    {\n        xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );\n\n        if( xBytesAvailable > sbBYTES_TO_STORE_MESSAGE_LENGTH )\n        {\n            /* The number of bytes available is greater than the number of bytes\n             * required to hold the length of the next message, so another message\n             * is available. */\n            ( void ) prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) &xTempReturn, sbBYTES_TO_STORE_MESSAGE_LENGTH, pxStreamBuffer->xTail );\n            xReturn = ( size_t ) xTempReturn;\n        }\n        else\n        {\n            /* The minimum amount of bytes in a message buffer is\n             * ( sbBYTES_TO_STORE_MESSAGE_LENGTH + 1 ), so if xBytesAvailable is\n             * less than sbBYTES_TO_STORE_MESSAGE_LENGTH the only other valid\n             * value is 0. */\n            configASSERT( xBytesAvailable == 0 );\n            xReturn = 0;\n        }\n    }\n    else\n    {\n        xReturn = 0;\n    }\n\n    return xReturn;\n}\n/*-----------------------------------------------------------*/\n\nsize_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,\n                                    void * pvRxData,\n                                    size_t xBufferLengthBytes,\n                                    BaseType_t * const pxHigherPriorityTaskWoken )\n{\n    StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;\n    size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength;\n\n    configASSERT( pvRxData );\n    configASSERT( pxStreamBuffer );\n\n    /* This receive function is used by both message buffers, which store\n     * discrete messages, and stream buffers, which store a continuous stream of\n     * bytes.  Discrete messages include an additional\n     * sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the\n     * message. */\n    if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )\n    {\n        xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;\n    }\n    else\n    {\n        xBytesToStoreMessageLength = 0;\n    }\n\n    xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );\n\n    /* Whether receiving a discrete message (where xBytesToStoreMessageLength\n     * holds the number of bytes used to store the message length) or a stream of\n     * bytes (where xBytesToStoreMessageLength is zero), the number of bytes\n     * available must be greater than xBytesToStoreMessageLength to be able to\n     * read bytes from the buffer. */\n    if( xBytesAvailable > xBytesToStoreMessageLength )\n    {\n        xReceivedLength = prvReadMessageFromBuffer( pxStreamBuffer, pvRxData, xBufferLengthBytes, xBytesAvailable );\n\n        /* Was a task waiting for space in the buffer? */\n        if( xReceivedLength != ( size_t ) 0 )\n        {\n            prvRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken );\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n    }\n    else\n    {\n        mtCOVERAGE_TEST_MARKER();\n    }\n\n    traceSTREAM_BUFFER_RECEIVE_FROM_ISR( xStreamBuffer, xReceivedLength );\n\n    return xReceivedLength;\n}\n/*-----------------------------------------------------------*/\n\nstatic size_t prvReadMessageFromBuffer( StreamBuffer_t * pxStreamBuffer,\n                                        void * pvRxData,\n                                        size_t xBufferLengthBytes,\n                                        size_t xBytesAvailable )\n{\n    size_t xCount, xNextMessageLength;\n    configMESSAGE_BUFFER_LENGTH_TYPE xTempNextMessageLength;\n    size_t xNextTail = pxStreamBuffer->xTail;\n\n    if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )\n    {\n        /* A discrete message is being received.  First receive the length\n         * of the message. */\n        xNextTail = prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) &xTempNextMessageLength, sbBYTES_TO_STORE_MESSAGE_LENGTH, xNextTail );\n        xNextMessageLength = ( size_t ) xTempNextMessageLength;\n\n        /* Reduce the number of bytes available by the number of bytes just\n         * read out. */\n        xBytesAvailable -= sbBYTES_TO_STORE_MESSAGE_LENGTH;\n\n        /* Check there is enough space in the buffer provided by the\n         * user. */\n        if( xNextMessageLength > xBufferLengthBytes )\n        {\n            /* The user has provided insufficient space to read the message. */\n            xNextMessageLength = 0;\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n    }\n    else\n    {\n        /* A stream of bytes is being received (as opposed to a discrete\n         * message), so read as many bytes as possible. */\n        xNextMessageLength = xBufferLengthBytes;\n    }\n\n    /* Use the minimum of the wanted bytes and the available bytes. */\n    xCount = configMIN( xNextMessageLength, xBytesAvailable );\n\n    if( xCount != ( size_t ) 0 )\n    {\n        /* Read the actual data and update the tail to mark the data as officially consumed. */\n        pxStreamBuffer->xTail = prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) pvRxData, xCount, xNextTail ); /*lint !e9079 Data storage area is implemented as uint8_t array for ease of sizing, indexing and alignment. */\n    }\n\n    return xCount;\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer )\n{\n    const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;\n    BaseType_t xReturn;\n    size_t xTail;\n\n    configASSERT( pxStreamBuffer );\n\n    /* True if no bytes are available. */\n    xTail = pxStreamBuffer->xTail;\n\n    if( pxStreamBuffer->xHead == xTail )\n    {\n        xReturn = pdTRUE;\n    }\n    else\n    {\n        xReturn = pdFALSE;\n    }\n\n    return xReturn;\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer )\n{\n    BaseType_t xReturn;\n    size_t xBytesToStoreMessageLength;\n    const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;\n\n    configASSERT( pxStreamBuffer );\n\n    /* This generic version of the receive function is used by both message\n     * buffers, which store discrete messages, and stream buffers, which store a\n     * continuous stream of bytes.  Discrete messages include an additional\n     * sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the message. */\n    if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )\n    {\n        xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;\n    }\n    else\n    {\n        xBytesToStoreMessageLength = 0;\n    }\n\n    /* True if the available space equals zero. */\n    if( xStreamBufferSpacesAvailable( xStreamBuffer ) <= xBytesToStoreMessageLength )\n    {\n        xReturn = pdTRUE;\n    }\n    else\n    {\n        xReturn = pdFALSE;\n    }\n\n    return xReturn;\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer,\n                                              BaseType_t * pxHigherPriorityTaskWoken )\n{\n    StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;\n    BaseType_t xReturn;\n    UBaseType_t uxSavedInterruptStatus;\n\n    configASSERT( pxStreamBuffer );\n\n    uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();\n    {\n        if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )\n        {\n            ( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToReceive,\n                                         ( uint32_t ) 0,\n                                         eNoAction,\n                                         pxHigherPriorityTaskWoken );\n            ( pxStreamBuffer )->xTaskWaitingToReceive = NULL;\n            xReturn = pdTRUE;\n        }\n        else\n        {\n            xReturn = pdFALSE;\n        }\n    }\n    portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\n\n    return xReturn;\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer,\n                                                 BaseType_t * pxHigherPriorityTaskWoken )\n{\n    StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;\n    BaseType_t xReturn;\n    UBaseType_t uxSavedInterruptStatus;\n\n    configASSERT( pxStreamBuffer );\n\n    uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();\n    {\n        if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )\n        {\n            ( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToSend,\n                                         ( uint32_t ) 0,\n                                         eNoAction,\n                                         pxHigherPriorityTaskWoken );\n            ( pxStreamBuffer )->xTaskWaitingToSend = NULL;\n            xReturn = pdTRUE;\n        }\n        else\n        {\n            xReturn = pdFALSE;\n        }\n    }\n    portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\n\n    return xReturn;\n}\n/*-----------------------------------------------------------*/\n\nstatic size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer,\n                                     const uint8_t * pucData,\n                                     size_t xCount,\n                                     size_t xHead )\n{\n    size_t xFirstLength;\n\n    configASSERT( xCount > ( size_t ) 0 );\n\n    /* Calculate the number of bytes that can be added in the first write -\n     * which may be less than the total number of bytes that need to be added if\n     * the buffer will wrap back to the beginning. */\n    xFirstLength = configMIN( pxStreamBuffer->xLength - xHead, xCount );\n\n    /* Write as many bytes as can be written in the first write. */\n    configASSERT( ( xHead + xFirstLength ) <= pxStreamBuffer->xLength );\n    ( void ) memcpy( ( void * ) ( &( pxStreamBuffer->pucBuffer[ xHead ] ) ), ( const void * ) pucData, xFirstLength ); /*lint !e9087 memcpy() requires void *. */\n\n    /* If the number of bytes written was less than the number that could be\n     * written in the first write... */\n    if( xCount > xFirstLength )\n    {\n        /* ...then write the remaining bytes to the start of the buffer. */\n        configASSERT( ( xCount - xFirstLength ) <= pxStreamBuffer->xLength );\n        ( void ) memcpy( ( void * ) pxStreamBuffer->pucBuffer, ( const void * ) &( pucData[ xFirstLength ] ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */\n    }\n    else\n    {\n        mtCOVERAGE_TEST_MARKER();\n    }\n\n    xHead += xCount;\n\n    if( xHead >= pxStreamBuffer->xLength )\n    {\n        xHead -= pxStreamBuffer->xLength;\n    }\n    else\n    {\n        mtCOVERAGE_TEST_MARKER();\n    }\n\n    return xHead;\n}\n/*-----------------------------------------------------------*/\n\nstatic size_t prvReadBytesFromBuffer( StreamBuffer_t * pxStreamBuffer,\n                                      uint8_t * pucData,\n                                      size_t xCount,\n                                      size_t xTail )\n{\n    size_t xFirstLength;\n\n    configASSERT( xCount != ( size_t ) 0 );\n\n    /* Calculate the number of bytes that can be read - which may be\n     * less than the number wanted if the data wraps around to the start of\n     * the buffer. */\n    xFirstLength = configMIN( pxStreamBuffer->xLength - xTail, xCount );\n\n    /* Obtain the number of bytes it is possible to obtain in the first\n     * read.  Asserts check bounds of read and write. */\n    configASSERT( xFirstLength <= xCount );\n    configASSERT( ( xTail + xFirstLength ) <= pxStreamBuffer->xLength );\n    ( void ) memcpy( ( void * ) pucData, ( const void * ) &( pxStreamBuffer->pucBuffer[ xTail ] ), xFirstLength ); /*lint !e9087 memcpy() requires void *. */\n\n    /* If the total number of wanted bytes is greater than the number\n     * that could be read in the first read... */\n    if( xCount > xFirstLength )\n    {\n        /* ...then read the remaining bytes from the start of the buffer. */\n        ( void ) memcpy( ( void * ) &( pucData[ xFirstLength ] ), ( void * ) ( pxStreamBuffer->pucBuffer ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */\n    }\n    else\n    {\n        mtCOVERAGE_TEST_MARKER();\n    }\n\n    /* Move the tail pointer to effectively remove the data read from the buffer. */\n    xTail += xCount;\n\n    if( xTail >= pxStreamBuffer->xLength )\n    {\n        xTail -= pxStreamBuffer->xLength;\n    }\n\n    return xTail;\n}\n/*-----------------------------------------------------------*/\n\nstatic size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer )\n{\n/* Returns the distance between xTail and xHead. */\n    size_t xCount;\n\n    xCount = pxStreamBuffer->xLength + pxStreamBuffer->xHead;\n    xCount -= pxStreamBuffer->xTail;\n\n    if( xCount >= pxStreamBuffer->xLength )\n    {\n        xCount -= pxStreamBuffer->xLength;\n    }\n    else\n    {\n        mtCOVERAGE_TEST_MARKER();\n    }\n\n    return xCount;\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,\n                                          uint8_t * const pucBuffer,\n                                          size_t xBufferSizeBytes,\n                                          size_t xTriggerLevelBytes,\n                                          uint8_t ucFlags,\n                                          StreamBufferCallbackFunction_t pxSendCompletedCallback,\n                                          StreamBufferCallbackFunction_t pxReceiveCompletedCallback )\n{\n    /* Assert here is deliberately writing to the entire buffer to ensure it can\n     * be written to without generating exceptions, and is setting the buffer to a\n     * known value to assist in development/debugging. */\n    #if ( configASSERT_DEFINED == 1 )\n    {\n        /* The value written just has to be identifiable when looking at the\n         * memory.  Don't use 0xA5 as that is the stack fill value and could\n         * result in confusion as to what is actually being observed. */\n        const BaseType_t xWriteValue = 0x55;\n        configASSERT( memset( pucBuffer, ( int ) xWriteValue, xBufferSizeBytes ) == pucBuffer );\n    } /*lint !e529 !e438 xWriteValue is only used if configASSERT() is defined. */\n    #endif\n\n    ( void ) memset( ( void * ) pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) ); /*lint !e9087 memset() requires void *. */\n    pxStreamBuffer->pucBuffer = pucBuffer;\n    pxStreamBuffer->xLength = xBufferSizeBytes;\n    pxStreamBuffer->xTriggerLevelBytes = xTriggerLevelBytes;\n    pxStreamBuffer->ucFlags = ucFlags;\n    #if ( configUSE_SB_COMPLETED_CALLBACK == 1 )\n    {\n        pxStreamBuffer->pxSendCompletedCallback = pxSendCompletedCallback;\n        pxStreamBuffer->pxReceiveCompletedCallback = pxReceiveCompletedCallback;\n    }\n    #else\n    {\n        ( void ) pxSendCompletedCallback;\n        ( void ) pxReceiveCompletedCallback;\n    }\n    #endif\n}\n\n#if ( configUSE_TRACE_FACILITY == 1 )\n\n    UBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer )\n    {\n        return xStreamBuffer->uxStreamBufferNumber;\n    }\n\n#endif /* configUSE_TRACE_FACILITY */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TRACE_FACILITY == 1 )\n\n    void vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer,\n                                             UBaseType_t uxStreamBufferNumber )\n    {\n        xStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber;\n    }\n\n#endif /* configUSE_TRACE_FACILITY */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TRACE_FACILITY == 1 )\n\n    uint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer )\n    {\n        return( xStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER );\n    }\n\n#endif /* configUSE_TRACE_FACILITY */\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "FreeRTOS-comparison/tasks.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Standard includes. */\n#include <stdlib.h>\n#include <string.h>\n\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\n * all the API functions to use the MPU wrappers.  That should only be done when\n * task.h is included from an application file. */\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/* FreeRTOS includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n#include \"timers.h\"\n#include \"stack_macros.h\"\n\n/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified\n * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined\n * for the header files above, but not in this file, in order to generate the\n * correct privileged Vs unprivileged linkage and placement. */\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */\n\n/* Set configUSE_STATS_FORMATTING_FUNCTIONS to 2 to include the stats formatting\n * functions but without including stdio.h here. */\n#if ( configUSE_STATS_FORMATTING_FUNCTIONS == 1 )\n\n/* At the bottom of this file are two optional functions that can be used\n * to generate human readable text from the raw data generated by the\n * uxTaskGetSystemState() function.  Note the formatting functions are provided\n * for convenience only, and are NOT considered part of the kernel. */\n    #include <stdio.h>\n#endif /* configUSE_STATS_FORMATTING_FUNCTIONS == 1 ) */\n\n#if ( configUSE_PREEMPTION == 0 )\n\n/* If the cooperative scheduler is being used then a yield should not be\n * performed just because a higher priority task has been woken. */\n    #define taskYIELD_IF_USING_PREEMPTION()\n#else\n    #define taskYIELD_IF_USING_PREEMPTION()    portYIELD_WITHIN_API()\n#endif\n\n/* Values that can be assigned to the ucNotifyState member of the TCB. */\n#define taskNOT_WAITING_NOTIFICATION              ( ( uint8_t ) 0 ) /* Must be zero as it is the initialised value. */\n#define taskWAITING_NOTIFICATION                  ( ( uint8_t ) 1 )\n#define taskNOTIFICATION_RECEIVED                 ( ( uint8_t ) 2 )\n\n/*\n * The value used to fill the stack of a task when the task is created.  This\n * is used purely for checking the high water mark for tasks.\n */\n#define tskSTACK_FILL_BYTE                        ( 0xa5U )\n\n/* Bits used to record how a task's stack and TCB were allocated. */\n#define tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB    ( ( uint8_t ) 0 )\n#define tskSTATICALLY_ALLOCATED_STACK_ONLY        ( ( uint8_t ) 1 )\n#define tskSTATICALLY_ALLOCATED_STACK_AND_TCB     ( ( uint8_t ) 2 )\n\n/* If any of the following are set then task stacks are filled with a known\n * value so the high water mark can be determined.  If none of the following are\n * set then don't fill the stack so there is no unnecessary dependency on memset. */\n#if ( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) )\n    #define tskSET_NEW_STACKS_TO_KNOWN_VALUE    1\n#else\n    #define tskSET_NEW_STACKS_TO_KNOWN_VALUE    0\n#endif\n\n/*\n * Macros used by vListTask to indicate which state a task is in.\n */\n#define tskRUNNING_CHAR      ( 'X' )\n#define tskBLOCKED_CHAR      ( 'B' )\n#define tskREADY_CHAR        ( 'R' )\n#define tskDELETED_CHAR      ( 'D' )\n#define tskSUSPENDED_CHAR    ( 'S' )\n\n/*\n * Some kernel aware debuggers require the data the debugger needs access to to\n * be global, rather than file scope.\n */\n#ifdef portREMOVE_STATIC_QUALIFIER\n    #define static\n#endif\n\n/* The name allocated to the Idle task.  This can be overridden by defining\n * configIDLE_TASK_NAME in FreeRTOSConfig.h. */\n#ifndef configIDLE_TASK_NAME\n    #define configIDLE_TASK_NAME    \"IDLE\"\n#endif\n\n#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 )\n\n/* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 0 then task selection is\n * performed in a generic way that is not optimised to any particular\n * microcontroller architecture. */\n\n/* uxTopReadyPriority holds the priority of the highest priority ready\n * state task. */\n    #define taskRECORD_READY_PRIORITY( uxPriority ) \\\n    {                                               \\\n        if( ( uxPriority ) > uxTopReadyPriority )   \\\n        {                                           \\\n            uxTopReadyPriority = ( uxPriority );    \\\n        }                                           \\\n    } /* taskRECORD_READY_PRIORITY */\n\n/*-----------------------------------------------------------*/\n\n    #define taskSELECT_HIGHEST_PRIORITY_TASK()                                \\\n    {                                                                         \\\n        UBaseType_t uxTopPriority = uxTopReadyPriority;                       \\\n                                                                              \\\n        /* Find the highest priority queue that contains ready tasks. */      \\\n        while( listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxTopPriority ] ) ) ) \\\n        {                                                                     \\\n            configASSERT( uxTopPriority );                                    \\\n            --uxTopPriority;                                                  \\\n        }                                                                     \\\n                                                                              \\\n        /* listGET_OWNER_OF_NEXT_ENTRY indexes through the list, so the tasks of \\\n         * the  same priority get an equal share of the processor time. */                    \\\n        listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) ); \\\n        uxTopReadyPriority = uxTopPriority;                                                   \\\n    } /* taskSELECT_HIGHEST_PRIORITY_TASK */\n\n/*-----------------------------------------------------------*/\n\n/* Define away taskRESET_READY_PRIORITY() and portRESET_READY_PRIORITY() as\n * they are only required when a port optimised method of task selection is\n * being used. */\n    #define taskRESET_READY_PRIORITY( uxPriority )\n    #define portRESET_READY_PRIORITY( uxPriority, uxTopReadyPriority )\n\n#else /* configUSE_PORT_OPTIMISED_TASK_SELECTION */\n\n/* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 1 then task selection is\n * performed in a way that is tailored to the particular microcontroller\n * architecture being used. */\n\n/* A port optimised version is provided.  Call the port defined macros. */\n    #define taskRECORD_READY_PRIORITY( uxPriority )    portRECORD_READY_PRIORITY( ( uxPriority ), uxTopReadyPriority )\n\n/*-----------------------------------------------------------*/\n\n    #define taskSELECT_HIGHEST_PRIORITY_TASK()                                                  \\\n    {                                                                                           \\\n        UBaseType_t uxTopPriority;                                                              \\\n                                                                                                \\\n        /* Find the highest priority list that contains ready tasks. */                         \\\n        portGET_HIGHEST_PRIORITY( uxTopPriority, uxTopReadyPriority );                          \\\n        configASSERT( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ uxTopPriority ] ) ) > 0 ); \\\n        listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) );   \\\n    } /* taskSELECT_HIGHEST_PRIORITY_TASK() */\n\n/*-----------------------------------------------------------*/\n\n/* A port optimised version is provided, call it only if the TCB being reset\n * is being referenced from a ready list.  If it is referenced from a delayed\n * or suspended list then it won't be in a ready list. */\n    #define taskRESET_READY_PRIORITY( uxPriority )                                                     \\\n    {                                                                                                  \\\n        if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ ( uxPriority ) ] ) ) == ( UBaseType_t ) 0 ) \\\n        {                                                                                              \\\n            portRESET_READY_PRIORITY( ( uxPriority ), ( uxTopReadyPriority ) );                        \\\n        }                                                                                              \\\n    }\n\n#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */\n\n/*-----------------------------------------------------------*/\n\n/* pxDelayedTaskList and pxOverflowDelayedTaskList are switched when the tick\n * count overflows. */\n#define taskSWITCH_DELAYED_LISTS()                                                \\\n    {                                                                             \\\n        List_t * pxTemp;                                                          \\\n                                                                                  \\\n        /* The delayed tasks list should be empty when the lists are switched. */ \\\n        configASSERT( ( listLIST_IS_EMPTY( pxDelayedTaskList ) ) );               \\\n                                                                                  \\\n        pxTemp = pxDelayedTaskList;                                               \\\n        pxDelayedTaskList = pxOverflowDelayedTaskList;                            \\\n        pxOverflowDelayedTaskList = pxTemp;                                       \\\n        xNumOfOverflows++;                                                        \\\n        prvResetNextTaskUnblockTime();                                            \\\n    }\n\n/*-----------------------------------------------------------*/\n\n/*\n * Place the task represented by pxTCB into the appropriate ready list for\n * the task.  It is inserted at the end of the list.\n */\n#define prvAddTaskToReadyList( pxTCB )                                                                 \\\n    traceMOVED_TASK_TO_READY_STATE( pxTCB );                                                           \\\n    taskRECORD_READY_PRIORITY( ( pxTCB )->uxPriority );                                                \\\n    listINSERT_END( &( pxReadyTasksLists[ ( pxTCB )->uxPriority ] ), &( ( pxTCB )->xStateListItem ) ); \\\n    tracePOST_MOVED_TASK_TO_READY_STATE( pxTCB )\n/*-----------------------------------------------------------*/\n\n/*\n * Several functions take a TaskHandle_t parameter that can optionally be NULL,\n * where NULL is used to indicate that the handle of the currently executing\n * task should be used in place of the parameter.  This macro simply checks to\n * see if the parameter is NULL and returns a pointer to the appropriate TCB.\n */\n#define prvGetTCBFromHandle( pxHandle )    ( ( ( pxHandle ) == NULL ) ? pxCurrentTCB : ( pxHandle ) )\n\n/* The item value of the event list item is normally used to hold the priority\n * of the task to which it belongs (coded to allow it to be held in reverse\n * priority order).  However, it is occasionally borrowed for other purposes.  It\n * is important its value is not updated due to a task priority change while it is\n * being used for another purpose.  The following bit definition is used to inform\n * the scheduler that the value should not be changed - in which case it is the\n * responsibility of whichever module is using the value to ensure it gets set back\n * to its original value when it is released. */\n#if ( configUSE_16_BIT_TICKS == 1 )\n    #define taskEVENT_LIST_ITEM_VALUE_IN_USE    0x8000U\n#else\n    #define taskEVENT_LIST_ITEM_VALUE_IN_USE    0x80000000UL\n#endif\n\n/*\n * Task control block.  A task control block (TCB) is allocated for each task,\n * and stores task state information, including a pointer to the task's context\n * (the task's run time environment, including register values)\n */\ntypedef struct tskTaskControlBlock       /* The old naming convention is used to prevent breaking kernel aware debuggers. */\n{\n    volatile StackType_t * pxTopOfStack; /*< Points to the location of the last item placed on the tasks stack.  THIS MUST BE THE FIRST MEMBER OF THE TCB STRUCT. */\n\n    #if ( portUSING_MPU_WRAPPERS == 1 )\n        xMPU_SETTINGS xMPUSettings; /*< The MPU settings are defined as part of the port layer.  THIS MUST BE THE SECOND MEMBER OF THE TCB STRUCT. */\n    #endif\n\n    ListItem_t xStateListItem;                  /*< The list that the state list item of a task is reference from denotes the state of that task (Ready, Blocked, Suspended ). */\n    ListItem_t xEventListItem;                  /*< Used to reference a task from an event list. */\n    UBaseType_t uxPriority;                     /*< The priority of the task.  0 is the lowest priority. */\n    StackType_t * pxStack;                      /*< Points to the start of the stack. */\n    char pcTaskName[ configMAX_TASK_NAME_LEN ]; /*< Descriptive name given to the task when created.  Facilitates debugging only. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n\n    #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) )\n        StackType_t * pxEndOfStack; /*< Points to the highest valid address for the stack. */\n    #endif\n\n    #if ( portCRITICAL_NESTING_IN_TCB == 1 )\n        UBaseType_t uxCriticalNesting; /*< Holds the critical section nesting depth for ports that do not maintain their own count in the port layer. */\n    #endif\n\n    #if ( configUSE_TRACE_FACILITY == 1 )\n        UBaseType_t uxTCBNumber;  /*< Stores a number that increments each time a TCB is created.  It allows debuggers to determine when a task has been deleted and then recreated. */\n        UBaseType_t uxTaskNumber; /*< Stores a number specifically for use by third party trace code. */\n    #endif\n\n    #if ( configUSE_MUTEXES == 1 )\n        UBaseType_t uxBasePriority; /*< The priority last assigned to the task - used by the priority inheritance mechanism. */\n        UBaseType_t uxMutexesHeld;\n    #endif\n\n    #if ( configUSE_APPLICATION_TASK_TAG == 1 )\n        TaskHookFunction_t pxTaskTag;\n    #endif\n\n    #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )\n        void * pvThreadLocalStoragePointers[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ];\n    #endif\n\n    #if ( configGENERATE_RUN_TIME_STATS == 1 )\n        configRUN_TIME_COUNTER_TYPE ulRunTimeCounter; /*< Stores the amount of time the task has spent in the Running state. */\n    #endif\n\n    #if ( ( configUSE_NEWLIB_REENTRANT == 1 ) || ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 ) )\n        configTLS_BLOCK_TYPE xTLSBlock; /*< Memory block used as Thread Local Storage (TLS) Block for the task. */\n    #endif\n\n    #if ( configUSE_TASK_NOTIFICATIONS == 1 )\n        volatile uint32_t ulNotifiedValue[ configTASK_NOTIFICATION_ARRAY_ENTRIES ];\n        volatile uint8_t ucNotifyState[ configTASK_NOTIFICATION_ARRAY_ENTRIES ];\n    #endif\n\n    /* See the comments in FreeRTOS.h with the definition of\n     * tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE. */\n    #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */\n        uint8_t ucStaticallyAllocated;                     /*< Set to pdTRUE if the task is a statically allocated to ensure no attempt is made to free the memory. */\n    #endif\n\n    #if ( INCLUDE_xTaskAbortDelay == 1 )\n        uint8_t ucDelayAborted;\n    #endif\n\n    #if ( configUSE_POSIX_ERRNO == 1 )\n        int iTaskErrno;\n    #endif\n} tskTCB;\n\n/* The old tskTCB name is maintained above then typedefed to the new TCB_t name\n * below to enable the use of older kernel aware debuggers. */\ntypedef tskTCB TCB_t;\n\n/*lint -save -e956 A manual analysis and inspection has been used to determine\n * which static variables must be declared volatile. */\nportDONT_DISCARD PRIVILEGED_DATA TCB_t * volatile pxCurrentTCB = NULL;\n\n/* Lists for ready and blocked tasks. --------------------\n * xDelayedTaskList1 and xDelayedTaskList2 could be moved to function scope but\n * doing so breaks some kernel aware debuggers and debuggers that rely on removing\n * the static qualifier. */\nPRIVILEGED_DATA static List_t pxReadyTasksLists[ configMAX_PRIORITIES ]; /*< Prioritised ready tasks. */\nPRIVILEGED_DATA static List_t xDelayedTaskList1;                         /*< Delayed tasks. */\nPRIVILEGED_DATA static List_t xDelayedTaskList2;                         /*< Delayed tasks (two lists are used - one for delays that have overflowed the current tick count. */\nPRIVILEGED_DATA static List_t * volatile pxDelayedTaskList;              /*< Points to the delayed task list currently being used. */\nPRIVILEGED_DATA static List_t * volatile pxOverflowDelayedTaskList;      /*< Points to the delayed task list currently being used to hold tasks that have overflowed the current tick count. */\nPRIVILEGED_DATA static List_t xPendingReadyList;                         /*< Tasks that have been readied while the scheduler was suspended.  They will be moved to the ready list when the scheduler is resumed. */\n\n#if ( INCLUDE_vTaskDelete == 1 )\n\n    PRIVILEGED_DATA static List_t xTasksWaitingTermination; /*< Tasks that have been deleted - but their memory not yet freed. */\n    PRIVILEGED_DATA static volatile UBaseType_t uxDeletedTasksWaitingCleanUp = ( UBaseType_t ) 0U;\n\n#endif\n\n#if ( INCLUDE_vTaskSuspend == 1 )\n\n    PRIVILEGED_DATA static List_t xSuspendedTaskList; /*< Tasks that are currently suspended. */\n\n#endif\n\n/* Global POSIX errno. Its value is changed upon context switching to match\n * the errno of the currently running task. */\n#if ( configUSE_POSIX_ERRNO == 1 )\n    int FreeRTOS_errno = 0;\n#endif\n\n/* Other file private variables. --------------------------------*/\nPRIVILEGED_DATA static volatile UBaseType_t uxCurrentNumberOfTasks = ( UBaseType_t ) 0U;\nPRIVILEGED_DATA static volatile TickType_t xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT;\nPRIVILEGED_DATA static volatile UBaseType_t uxTopReadyPriority = tskIDLE_PRIORITY;\nPRIVILEGED_DATA static volatile BaseType_t xSchedulerRunning = pdFALSE;\nPRIVILEGED_DATA static volatile TickType_t xPendedTicks = ( TickType_t ) 0U;\nPRIVILEGED_DATA static volatile BaseType_t xYieldPending = pdFALSE;\nPRIVILEGED_DATA static volatile BaseType_t xNumOfOverflows = ( BaseType_t ) 0;\nPRIVILEGED_DATA static UBaseType_t uxTaskNumber = ( UBaseType_t ) 0U;\nPRIVILEGED_DATA static volatile TickType_t xNextTaskUnblockTime = ( TickType_t ) 0U; /* Initialised to portMAX_DELAY before the scheduler starts. */\nPRIVILEGED_DATA static TaskHandle_t xIdleTaskHandle = NULL;                          /*< Holds the handle of the idle task.  The idle task is created automatically when the scheduler is started. */\n\n/* Improve support for OpenOCD. The kernel tracks Ready tasks via priority lists.\n * For tracking the state of remote threads, OpenOCD uses uxTopUsedPriority\n * to determine the number of priority lists to read back from the remote target. */\nconst volatile UBaseType_t uxTopUsedPriority = configMAX_PRIORITIES - 1U;\n\n/* Context switches are held pending while the scheduler is suspended.  Also,\n * interrupts must not manipulate the xStateListItem of a TCB, or any of the\n * lists the xStateListItem can be referenced from, if the scheduler is suspended.\n * If an interrupt needs to unblock a task while the scheduler is suspended then it\n * moves the task's event list item into the xPendingReadyList, ready for the\n * kernel to move the task from the pending ready list into the real ready list\n * when the scheduler is unsuspended.  The pending ready list itself can only be\n * accessed from a critical section. */\nPRIVILEGED_DATA static volatile UBaseType_t uxSchedulerSuspended = ( UBaseType_t ) pdFALSE;\n\n#if ( configGENERATE_RUN_TIME_STATS == 1 )\n\n/* Do not move these variables to function scope as doing so prevents the\n * code working with debuggers that need to remove the static qualifier. */\n    PRIVILEGED_DATA static configRUN_TIME_COUNTER_TYPE ulTaskSwitchedInTime = 0UL;    /*< Holds the value of a timer/counter the last time a task was switched in. */\n    PRIVILEGED_DATA static volatile configRUN_TIME_COUNTER_TYPE ulTotalRunTime = 0UL; /*< Holds the total amount of execution time as defined by the run time counter clock. */\n\n#endif\n\n/*lint -restore */\n\n/*-----------------------------------------------------------*/\n\n/* File private functions. --------------------------------*/\n\n/**\n * Utility task that simply returns pdTRUE if the task referenced by xTask is\n * currently in the Suspended state, or pdFALSE if the task referenced by xTask\n * is in any other state.\n */\n#if ( INCLUDE_vTaskSuspend == 1 )\n\n    static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;\n\n#endif /* INCLUDE_vTaskSuspend */\n\n/*\n * Utility to ready all the lists used by the scheduler.  This is called\n * automatically upon the creation of the first task.\n */\nstatic void prvInitialiseTaskLists( void ) PRIVILEGED_FUNCTION;\n\n/*\n * The idle task, which as all tasks is implemented as a never ending loop.\n * The idle task is automatically created and added to the ready lists upon\n * creation of the first user task.\n *\n * The portTASK_FUNCTION_PROTO() macro is used to allow port/compiler specific\n * language extensions.  The equivalent prototype for this function is:\n *\n * void prvIdleTask( void *pvParameters );\n *\n */\nstatic portTASK_FUNCTION_PROTO( prvIdleTask, pvParameters ) PRIVILEGED_FUNCTION;\n\n/*\n * Utility to free all memory allocated by the scheduler to hold a TCB,\n * including the stack pointed to by the TCB.\n *\n * This does not free memory allocated by the task itself (i.e. memory\n * allocated by calls to pvPortMalloc from within the tasks application code).\n */\n#if ( INCLUDE_vTaskDelete == 1 )\n\n    static void prvDeleteTCB( TCB_t * pxTCB ) PRIVILEGED_FUNCTION;\n\n#endif\n\n/*\n * Used only by the idle task.  This checks to see if anything has been placed\n * in the list of tasks waiting to be deleted.  If so the task is cleaned up\n * and its TCB deleted.\n */\nstatic void prvCheckTasksWaitingTermination( void ) PRIVILEGED_FUNCTION;\n\n/*\n * The currently executing task is entering the Blocked state.  Add the task to\n * either the current or the overflow delayed task list.\n */\nstatic void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait,\n                                            const BaseType_t xCanBlockIndefinitely ) PRIVILEGED_FUNCTION;\n\n/*\n * Fills an TaskStatus_t structure with information on each task that is\n * referenced from the pxList list (which may be a ready list, a delayed list,\n * a suspended list, etc.).\n *\n * THIS FUNCTION IS INTENDED FOR DEBUGGING ONLY, AND SHOULD NOT BE CALLED FROM\n * NORMAL APPLICATION CODE.\n */\n#if ( configUSE_TRACE_FACILITY == 1 )\n\n    static UBaseType_t prvListTasksWithinSingleList( TaskStatus_t * pxTaskStatusArray,\n                                                     List_t * pxList,\n                                                     eTaskState eState ) PRIVILEGED_FUNCTION;\n\n#endif\n\n/*\n * Searches pxList for a task with name pcNameToQuery - returning a handle to\n * the task if it is found, or NULL if the task is not found.\n */\n#if ( INCLUDE_xTaskGetHandle == 1 )\n\n    static TCB_t * prvSearchForNameWithinSingleList( List_t * pxList,\n                                                     const char pcNameToQuery[] ) PRIVILEGED_FUNCTION;\n\n#endif\n\n/*\n * When a task is created, the stack of the task is filled with a known value.\n * This function determines the 'high water mark' of the task stack by\n * determining how much of the stack remains at the original preset value.\n */\n#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) )\n\n    static configSTACK_DEPTH_TYPE prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte ) PRIVILEGED_FUNCTION;\n\n#endif\n\n/*\n * Return the amount of time, in ticks, that will pass before the kernel will\n * next move a task from the Blocked state to the Running state.\n *\n * This conditional compilation should use inequality to 0, not equality to 1.\n * This is to ensure portSUPPRESS_TICKS_AND_SLEEP() can be called when user\n * defined low power mode implementations require configUSE_TICKLESS_IDLE to be\n * set to a value other than 1.\n */\n#if ( configUSE_TICKLESS_IDLE != 0 )\n\n    static TickType_t prvGetExpectedIdleTime( void ) PRIVILEGED_FUNCTION;\n\n#endif\n\n/*\n * Set xNextTaskUnblockTime to the time at which the next Blocked state task\n * will exit the Blocked state.\n */\nstatic void prvResetNextTaskUnblockTime( void ) PRIVILEGED_FUNCTION;\n\n#if ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 )\n\n/*\n * Helper function used to pad task names with spaces when printing out\n * human readable tables of task information.\n */\n    static char * prvWriteNameToBuffer( char * pcBuffer,\n                                        const char * pcTaskName ) PRIVILEGED_FUNCTION;\n\n#endif\n\n/*\n * Called after a Task_t structure has been allocated either statically or\n * dynamically to fill in the structure's members.\n */\nstatic void prvInitialiseNewTask( TaskFunction_t pxTaskCode,\n                                  const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n                                  const uint32_t ulStackDepth,\n                                  void * const pvParameters,\n                                  UBaseType_t uxPriority,\n                                  TaskHandle_t * const pxCreatedTask,\n                                  TCB_t * pxNewTCB,\n                                  const MemoryRegion_t * const xRegions ) PRIVILEGED_FUNCTION;\n\n/*\n * Called after a new task has been created and initialised to place the task\n * under the control of the scheduler.\n */\nstatic void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;\n\n/*\n * freertos_tasks_c_additions_init() should only be called if the user definable\n * macro FREERTOS_TASKS_C_ADDITIONS_INIT() is defined, as that is the only macro\n * called by the function.\n */\n#ifdef FREERTOS_TASKS_C_ADDITIONS_INIT\n\n    static void freertos_tasks_c_additions_init( void ) PRIVILEGED_FUNCTION;\n\n#endif\n\n/*-----------------------------------------------------------*/\n\n#if ( configSUPPORT_STATIC_ALLOCATION == 1 )\n\n    TaskHandle_t xTaskCreateStatic( TaskFunction_t pxTaskCode,\n                                    const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n                                    const uint32_t ulStackDepth,\n                                    void * const pvParameters,\n                                    UBaseType_t uxPriority,\n                                    StackType_t * const puxStackBuffer,\n                                    StaticTask_t * const pxTaskBuffer )\n    {\n        TCB_t * pxNewTCB;\n        TaskHandle_t xReturn;\n\n        configASSERT( puxStackBuffer != NULL );\n        configASSERT( pxTaskBuffer != NULL );\n\n        #if ( configASSERT_DEFINED == 1 )\n        {\n            /* Sanity check that the size of the structure used to declare a\n             * variable of type StaticTask_t equals the size of the real task\n             * structure. */\n            volatile size_t xSize = sizeof( StaticTask_t );\n            configASSERT( xSize == sizeof( TCB_t ) );\n            ( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */\n        }\n        #endif /* configASSERT_DEFINED */\n\n        if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) )\n        {\n            /* The memory used for the task's TCB and stack are passed into this\n             * function - use them. */\n            pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */\n            memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) );\n            pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer;\n\n            #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */\n            {\n                /* Tasks can be created statically or dynamically, so note this\n                 * task was created statically in case the task is later deleted. */\n                pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;\n            }\n            #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */\n\n            prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL );\n            prvAddNewTaskToReadyList( pxNewTCB );\n        }\n        else\n        {\n            xReturn = NULL;\n        }\n\n        return xReturn;\n    }\n\n#endif /* SUPPORT_STATIC_ALLOCATION */\n/*-----------------------------------------------------------*/\n\n#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )\n\n    BaseType_t xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition,\n                                            TaskHandle_t * pxCreatedTask )\n    {\n        TCB_t * pxNewTCB;\n        BaseType_t xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;\n\n        configASSERT( pxTaskDefinition->puxStackBuffer != NULL );\n        configASSERT( pxTaskDefinition->pxTaskBuffer != NULL );\n\n        if( ( pxTaskDefinition->puxStackBuffer != NULL ) && ( pxTaskDefinition->pxTaskBuffer != NULL ) )\n        {\n            /* Allocate space for the TCB.  Where the memory comes from depends\n             * on the implementation of the port malloc function and whether or\n             * not static allocation is being used. */\n            pxNewTCB = ( TCB_t * ) pxTaskDefinition->pxTaskBuffer;\n            memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) );\n\n            /* Store the stack location in the TCB. */\n            pxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer;\n\n            #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )\n            {\n                /* Tasks can be created statically or dynamically, so note this\n                 * task was created statically in case the task is later deleted. */\n                pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;\n            }\n            #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */\n\n            prvInitialiseNewTask( pxTaskDefinition->pvTaskCode,\n                                  pxTaskDefinition->pcName,\n                                  ( uint32_t ) pxTaskDefinition->usStackDepth,\n                                  pxTaskDefinition->pvParameters,\n                                  pxTaskDefinition->uxPriority,\n                                  pxCreatedTask, pxNewTCB,\n                                  pxTaskDefinition->xRegions );\n\n            prvAddNewTaskToReadyList( pxNewTCB );\n            xReturn = pdPASS;\n        }\n\n        return xReturn;\n    }\n\n#endif /* ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) */\n/*-----------------------------------------------------------*/\n\n#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )\n\n    BaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition,\n                                      TaskHandle_t * pxCreatedTask )\n    {\n        TCB_t * pxNewTCB;\n        BaseType_t xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;\n\n        configASSERT( pxTaskDefinition->puxStackBuffer );\n\n        if( pxTaskDefinition->puxStackBuffer != NULL )\n        {\n            /* Allocate space for the TCB.  Where the memory comes from depends\n             * on the implementation of the port malloc function and whether or\n             * not static allocation is being used. */\n            pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) );\n\n            if( pxNewTCB != NULL )\n            {\n                memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) );\n\n                /* Store the stack location in the TCB. */\n                pxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer;\n\n                #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )\n                {\n                    /* Tasks can be created statically or dynamically, so note\n                     * this task had a statically allocated stack in case it is\n                     * later deleted.  The TCB was allocated dynamically. */\n                    pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_ONLY;\n                }\n                #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */\n\n                prvInitialiseNewTask( pxTaskDefinition->pvTaskCode,\n                                      pxTaskDefinition->pcName,\n                                      ( uint32_t ) pxTaskDefinition->usStackDepth,\n                                      pxTaskDefinition->pvParameters,\n                                      pxTaskDefinition->uxPriority,\n                                      pxCreatedTask, pxNewTCB,\n                                      pxTaskDefinition->xRegions );\n\n                prvAddNewTaskToReadyList( pxNewTCB );\n                xReturn = pdPASS;\n            }\n        }\n\n        return xReturn;\n    }\n\n#endif /* portUSING_MPU_WRAPPERS */\n/*-----------------------------------------------------------*/\n\n#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n\n    BaseType_t xTaskCreate( TaskFunction_t pxTaskCode,\n                            const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n                            const configSTACK_DEPTH_TYPE usStackDepth,\n                            void * const pvParameters,\n                            UBaseType_t uxPriority,\n                            TaskHandle_t * const pxCreatedTask )\n    {\n        TCB_t * pxNewTCB;\n        BaseType_t xReturn;\n\n        /* If the stack grows down then allocate the stack then the TCB so the stack\n         * does not grow into the TCB.  Likewise if the stack grows up then allocate\n         * the TCB then the stack. */\n        #if ( portSTACK_GROWTH > 0 )\n        {\n            /* Allocate space for the TCB.  Where the memory comes from depends on\n             * the implementation of the port malloc function and whether or not static\n             * allocation is being used. */\n            pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) );\n\n            if( pxNewTCB != NULL )\n            {\n                memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) );\n\n                /* Allocate space for the stack used by the task being created.\n                 * The base of the stack memory stored in the TCB so the task can\n                 * be deleted later if required. */\n                pxNewTCB->pxStack = ( StackType_t * ) pvPortMallocStack( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\n\n                if( pxNewTCB->pxStack == NULL )\n                {\n                    /* Could not allocate the stack.  Delete the allocated TCB. */\n                    vPortFree( pxNewTCB );\n                    pxNewTCB = NULL;\n                }\n            }\n        }\n        #else /* portSTACK_GROWTH */\n        {\n            StackType_t * pxStack;\n\n            /* Allocate space for the stack used by the task being created. */\n            pxStack = pvPortMallocStack( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */\n\n            if( pxStack != NULL )\n            {\n                /* Allocate space for the TCB. */\n                pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */\n\n                if( pxNewTCB != NULL )\n                {\n                    memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) );\n\n                    /* Store the stack location in the TCB. */\n                    pxNewTCB->pxStack = pxStack;\n                }\n                else\n                {\n                    /* The stack cannot be used as the TCB was not created.  Free\n                     * it again. */\n                    vPortFreeStack( pxStack );\n                }\n            }\n            else\n            {\n                pxNewTCB = NULL;\n            }\n        }\n        #endif /* portSTACK_GROWTH */\n\n        if( pxNewTCB != NULL )\n        {\n            #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */\n            {\n                /* Tasks can be created statically or dynamically, so note this\n                 * task was created dynamically in case it is later deleted. */\n                pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB;\n            }\n            #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */\n\n            prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL );\n            prvAddNewTaskToReadyList( pxNewTCB );\n            xReturn = pdPASS;\n        }\n        else\n        {\n            xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;\n        }\n\n        return xReturn;\n    }\n\n#endif /* configSUPPORT_DYNAMIC_ALLOCATION */\n/*-----------------------------------------------------------*/\n\nstatic void prvInitialiseNewTask( TaskFunction_t pxTaskCode,\n                                  const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n                                  const uint32_t ulStackDepth,\n                                  void * const pvParameters,\n                                  UBaseType_t uxPriority,\n                                  TaskHandle_t * const pxCreatedTask,\n                                  TCB_t * pxNewTCB,\n                                  const MemoryRegion_t * const xRegions )\n{\n    StackType_t * pxTopOfStack;\n    UBaseType_t x;\n\n    #if ( portUSING_MPU_WRAPPERS == 1 )\n        /* Should the task be created in privileged mode? */\n        BaseType_t xRunPrivileged;\n\n        if( ( uxPriority & portPRIVILEGE_BIT ) != 0U )\n        {\n            xRunPrivileged = pdTRUE;\n        }\n        else\n        {\n            xRunPrivileged = pdFALSE;\n        }\n        uxPriority &= ~portPRIVILEGE_BIT;\n    #endif /* portUSING_MPU_WRAPPERS == 1 */\n\n    /* Avoid dependency on memset() if it is not required. */\n    #if ( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 )\n    {\n        /* Fill the stack with a known value to assist debugging. */\n        ( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) );\n    }\n    #endif /* tskSET_NEW_STACKS_TO_KNOWN_VALUE */\n\n    /* Calculate the top of stack address.  This depends on whether the stack\n     * grows from high memory to low (as per the 80x86) or vice versa.\n     * portSTACK_GROWTH is used to make the result positive or negative as required\n     * by the port. */\n    #if ( portSTACK_GROWTH < 0 )\n    {\n        pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] );\n        pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception.  Avoiding casts between pointers and integers is not practical.  Size differences accounted for using portPOINTER_SIZE_TYPE type.  Checked by assert(). */\n\n        /* Check the alignment of the calculated top of stack is correct. */\n        configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );\n\n        #if ( configRECORD_STACK_HIGH_ADDRESS == 1 )\n        {\n            /* Also record the stack's high address, which may assist\n             * debugging. */\n            pxNewTCB->pxEndOfStack = pxTopOfStack;\n        }\n        #endif /* configRECORD_STACK_HIGH_ADDRESS */\n    }\n    #else /* portSTACK_GROWTH */\n    {\n        pxTopOfStack = pxNewTCB->pxStack;\n\n        /* Check the alignment of the stack buffer is correct. */\n        configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxNewTCB->pxStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );\n\n        /* The other extreme of the stack space is required if stack checking is\n         * performed. */\n        pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 );\n    }\n    #endif /* portSTACK_GROWTH */\n\n    /* Store the task name in the TCB. */\n    if( pcName != NULL )\n    {\n        for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )\n        {\n            pxNewTCB->pcTaskName[ x ] = pcName[ x ];\n\n            /* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than\n             * configMAX_TASK_NAME_LEN characters just in case the memory after the\n             * string is not accessible (extremely unlikely). */\n            if( pcName[ x ] == ( char ) 0x00 )\n            {\n                break;\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n\n        /* Ensure the name string is terminated in the case that the string length\n         * was greater or equal to configMAX_TASK_NAME_LEN. */\n        pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\\0';\n    }\n    else\n    {\n        mtCOVERAGE_TEST_MARKER();\n    }\n\n    /* This is used as an array index so must ensure it's not too large. */\n    configASSERT( uxPriority < configMAX_PRIORITIES );\n\n    if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES )\n    {\n        uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;\n    }\n    else\n    {\n        mtCOVERAGE_TEST_MARKER();\n    }\n\n    pxNewTCB->uxPriority = uxPriority;\n    #if ( configUSE_MUTEXES == 1 )\n    {\n        pxNewTCB->uxBasePriority = uxPriority;\n    }\n    #endif /* configUSE_MUTEXES */\n\n    vListInitialiseItem( &( pxNewTCB->xStateListItem ) );\n    vListInitialiseItem( &( pxNewTCB->xEventListItem ) );\n\n    /* Set the pxNewTCB as a link back from the ListItem_t.  This is so we can get\n     * back to  the containing TCB from a generic item in a list. */\n    listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB );\n\n    /* Event lists are always in priority order. */\n    listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\n    listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB );\n\n    #if ( portUSING_MPU_WRAPPERS == 1 )\n    {\n        vPortStoreTaskMPUSettings( &( pxNewTCB->xMPUSettings ), xRegions, pxNewTCB->pxStack, ulStackDepth );\n    }\n    #else\n    {\n        /* Avoid compiler warning about unreferenced parameter. */\n        ( void ) xRegions;\n    }\n    #endif\n\n    #if ( ( configUSE_NEWLIB_REENTRANT == 1 ) || ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 ) )\n    {\n        /* Allocate and initialize memory for the task's TLS Block. */\n        configINIT_TLS_BLOCK( pxNewTCB->xTLSBlock );\n    }\n    #endif\n\n    /* Initialize the TCB stack to look as if the task was already running,\n     * but had been interrupted by the scheduler.  The return address is set\n     * to the start of the task function. Once the stack has been initialised\n     * the top of stack variable is updated. */\n    #if ( portUSING_MPU_WRAPPERS == 1 )\n    {\n        /* If the port has capability to detect stack overflow,\n         * pass the stack end address to the stack initialization\n         * function as well. */\n        #if ( portHAS_STACK_OVERFLOW_CHECKING == 1 )\n        {\n            #if ( portSTACK_GROWTH < 0 )\n            {\n                pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxStack, pxTaskCode, pvParameters, xRunPrivileged );\n            }\n            #else /* portSTACK_GROWTH */\n            {\n                pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxEndOfStack, pxTaskCode, pvParameters, xRunPrivileged );\n            }\n            #endif /* portSTACK_GROWTH */\n        }\n        #else /* portHAS_STACK_OVERFLOW_CHECKING */\n        {\n            pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters, xRunPrivileged );\n        }\n        #endif /* portHAS_STACK_OVERFLOW_CHECKING */\n    }\n    #else /* portUSING_MPU_WRAPPERS */\n    {\n        /* If the port has capability to detect stack overflow,\n         * pass the stack end address to the stack initialization\n         * function as well. */\n        #if ( portHAS_STACK_OVERFLOW_CHECKING == 1 )\n        {\n            #if ( portSTACK_GROWTH < 0 )\n            {\n                pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxStack, pxTaskCode, pvParameters );\n            }\n            #else /* portSTACK_GROWTH */\n            {\n                pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxEndOfStack, pxTaskCode, pvParameters );\n            }\n            #endif /* portSTACK_GROWTH */\n        }\n        #else /* portHAS_STACK_OVERFLOW_CHECKING */\n        {\n            pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );\n        }\n        #endif /* portHAS_STACK_OVERFLOW_CHECKING */\n    }\n    #endif /* portUSING_MPU_WRAPPERS */\n\n    if( pxCreatedTask != NULL )\n    {\n        /* Pass the handle out in an anonymous way.  The handle can be used to\n         * change the created task's priority, delete the created task, etc.*/\n        *pxCreatedTask = ( TaskHandle_t ) pxNewTCB;\n    }\n    else\n    {\n        mtCOVERAGE_TEST_MARKER();\n    }\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvAddNewTaskToReadyList( TCB_t * pxNewTCB )\n{\n    /* Ensure interrupts don't access the task lists while the lists are being\n     * updated. */\n    taskENTER_CRITICAL();\n    {\n        uxCurrentNumberOfTasks++;\n\n        if( pxCurrentTCB == NULL )\n        {\n            /* There are no other tasks, or all the other tasks are in\n             * the suspended state - make this the current task. */\n            pxCurrentTCB = pxNewTCB;\n\n            if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 )\n            {\n                /* This is the first task to be created so do the preliminary\n                 * initialisation required.  We will not recover if this call\n                 * fails, but we will report the failure. */\n                prvInitialiseTaskLists();\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n        else\n        {\n            /* If the scheduler is not already running, make this task the\n             * current task if it is the highest priority task to be created\n             * so far. */\n            if( xSchedulerRunning == pdFALSE )\n            {\n                if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority )\n                {\n                    pxCurrentTCB = pxNewTCB;\n                }\n                else\n                {\n                    mtCOVERAGE_TEST_MARKER();\n                }\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n\n        uxTaskNumber++;\n\n        #if ( configUSE_TRACE_FACILITY == 1 )\n        {\n            /* Add a counter into the TCB for tracing only. */\n            pxNewTCB->uxTCBNumber = uxTaskNumber;\n        }\n        #endif /* configUSE_TRACE_FACILITY */\n        traceTASK_CREATE( pxNewTCB );\n\n        prvAddTaskToReadyList( pxNewTCB );\n\n        portSETUP_TCB( pxNewTCB );\n    }\n    taskEXIT_CRITICAL();\n\n    if( xSchedulerRunning != pdFALSE )\n    {\n        /* If the created task is of a higher priority than the current task\n         * then it should run now. */\n        if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority )\n        {\n            taskYIELD_IF_USING_PREEMPTION();\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n    }\n    else\n    {\n        mtCOVERAGE_TEST_MARKER();\n    }\n}\n/*-----------------------------------------------------------*/\n\n#if ( INCLUDE_vTaskDelete == 1 )\n\n    void vTaskDelete( TaskHandle_t xTaskToDelete )\n    {\n        TCB_t * pxTCB;\n\n        taskENTER_CRITICAL();\n        {\n            /* If null is passed in here then it is the calling task that is\n             * being deleted. */\n            pxTCB = prvGetTCBFromHandle( xTaskToDelete );\n\n            /* Remove task from the ready/delayed list. */\n            if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )\n            {\n                taskRESET_READY_PRIORITY( pxTCB->uxPriority );\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n\n            /* Is the task waiting on an event also? */\n            if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )\n            {\n                ( void ) uxListRemove( &( pxTCB->xEventListItem ) );\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n\n            /* Increment the uxTaskNumber also so kernel aware debuggers can\n             * detect that the task lists need re-generating.  This is done before\n             * portPRE_TASK_DELETE_HOOK() as in the Windows port that macro will\n             * not return. */\n            uxTaskNumber++;\n\n            if( pxTCB == pxCurrentTCB )\n            {\n                /* A task is deleting itself.  This cannot complete within the\n                 * task itself, as a context switch to another task is required.\n                 * Place the task in the termination list.  The idle task will\n                 * check the termination list and free up any memory allocated by\n                 * the scheduler for the TCB and stack of the deleted task. */\n                vListInsertEnd( &xTasksWaitingTermination, &( pxTCB->xStateListItem ) );\n\n                /* Increment the ucTasksDeleted variable so the idle task knows\n                 * there is a task that has been deleted and that it should therefore\n                 * check the xTasksWaitingTermination list. */\n                ++uxDeletedTasksWaitingCleanUp;\n\n                /* Call the delete hook before portPRE_TASK_DELETE_HOOK() as\n                 * portPRE_TASK_DELETE_HOOK() does not return in the Win32 port. */\n                traceTASK_DELETE( pxTCB );\n\n                /* The pre-delete hook is primarily for the Windows simulator,\n                 * in which Windows specific clean up operations are performed,\n                 * after which it is not possible to yield away from this task -\n                 * hence xYieldPending is used to latch that a context switch is\n                 * required. */\n                portPRE_TASK_DELETE_HOOK( pxTCB, &xYieldPending );\n            }\n            else\n            {\n                --uxCurrentNumberOfTasks;\n                traceTASK_DELETE( pxTCB );\n\n                /* Reset the next expected unblock time in case it referred to\n                 * the task that has just been deleted. */\n                prvResetNextTaskUnblockTime();\n            }\n        }\n        taskEXIT_CRITICAL();\n\n        /* If the task is not deleting itself, call prvDeleteTCB from outside of\n         * critical section. If a task deletes itself, prvDeleteTCB is called\n         * from prvCheckTasksWaitingTermination which is called from Idle task. */\n        if( pxTCB != pxCurrentTCB )\n        {\n            prvDeleteTCB( pxTCB );\n        }\n\n        /* Force a reschedule if it is the currently running task that has just\n         * been deleted. */\n        if( xSchedulerRunning != pdFALSE )\n        {\n            if( pxTCB == pxCurrentTCB )\n            {\n                configASSERT( uxSchedulerSuspended == 0 );\n                portYIELD_WITHIN_API();\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n    }\n\n#endif /* INCLUDE_vTaskDelete */\n/*-----------------------------------------------------------*/\n\n#if ( INCLUDE_xTaskDelayUntil == 1 )\n\n    BaseType_t xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,\n                                const TickType_t xTimeIncrement )\n    {\n        TickType_t xTimeToWake;\n        BaseType_t xAlreadyYielded, xShouldDelay = pdFALSE;\n\n        configASSERT( pxPreviousWakeTime );\n        configASSERT( ( xTimeIncrement > 0U ) );\n        configASSERT( uxSchedulerSuspended == 0 );\n\n        vTaskSuspendAll();\n        {\n            /* Minor optimisation.  The tick count cannot change in this\n             * block. */\n            const TickType_t xConstTickCount = xTickCount;\n\n            /* Generate the tick time at which the task wants to wake. */\n            xTimeToWake = *pxPreviousWakeTime + xTimeIncrement;\n\n            if( xConstTickCount < *pxPreviousWakeTime )\n            {\n                /* The tick count has overflowed since this function was\n                 * lasted called.  In this case the only time we should ever\n                 * actually delay is if the wake time has also  overflowed,\n                 * and the wake time is greater than the tick time.  When this\n                 * is the case it is as if neither time had overflowed. */\n                if( ( xTimeToWake < *pxPreviousWakeTime ) && ( xTimeToWake > xConstTickCount ) )\n                {\n                    xShouldDelay = pdTRUE;\n                }\n                else\n                {\n                    mtCOVERAGE_TEST_MARKER();\n                }\n            }\n            else\n            {\n                /* The tick time has not overflowed.  In this case we will\n                 * delay if either the wake time has overflowed, and/or the\n                 * tick time is less than the wake time. */\n                if( ( xTimeToWake < *pxPreviousWakeTime ) || ( xTimeToWake > xConstTickCount ) )\n                {\n                    xShouldDelay = pdTRUE;\n                }\n                else\n                {\n                    mtCOVERAGE_TEST_MARKER();\n                }\n            }\n\n            /* Update the wake time ready for the next call. */\n            *pxPreviousWakeTime = xTimeToWake;\n\n            if( xShouldDelay != pdFALSE )\n            {\n                traceTASK_DELAY_UNTIL( xTimeToWake );\n\n                /* prvAddCurrentTaskToDelayedList() needs the block time, not\n                 * the time to wake, so subtract the current tick count. */\n                prvAddCurrentTaskToDelayedList( xTimeToWake - xConstTickCount, pdFALSE );\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n        xAlreadyYielded = xTaskResumeAll();\n\n        /* Force a reschedule if xTaskResumeAll has not already done so, we may\n         * have put ourselves to sleep. */\n        if( xAlreadyYielded == pdFALSE )\n        {\n            portYIELD_WITHIN_API();\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n\n        return xShouldDelay;\n    }\n\n#endif /* INCLUDE_xTaskDelayUntil */\n/*-----------------------------------------------------------*/\n\n#if ( INCLUDE_vTaskDelay == 1 )\n\n    void vTaskDelay( const TickType_t xTicksToDelay )\n    {\n        BaseType_t xAlreadyYielded = pdFALSE;\n\n        /* A delay time of zero just forces a reschedule. */\n        if( xTicksToDelay > ( TickType_t ) 0U )\n        {\n            configASSERT( uxSchedulerSuspended == 0 );\n            vTaskSuspendAll();\n            {\n                traceTASK_DELAY();\n\n                /* A task that is removed from the event list while the\n                 * scheduler is suspended will not get placed in the ready\n                 * list or removed from the blocked list until the scheduler\n                 * is resumed.\n                 *\n                 * This task cannot be in an event list as it is the currently\n                 * executing task. */\n                prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE );\n            }\n            xAlreadyYielded = xTaskResumeAll();\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n\n        /* Force a reschedule if xTaskResumeAll has not already done so, we may\n         * have put ourselves to sleep. */\n        if( xAlreadyYielded == pdFALSE )\n        {\n            portYIELD_WITHIN_API();\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n    }\n\n#endif /* INCLUDE_vTaskDelay */\n/*-----------------------------------------------------------*/\n\n#if ( ( INCLUDE_eTaskGetState == 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_xTaskAbortDelay == 1 ) )\n\n    eTaskState eTaskGetState( TaskHandle_t xTask )\n    {\n        eTaskState eReturn;\n        List_t const * pxStateList;\n        List_t const * pxDelayedList;\n        List_t const * pxOverflowedDelayedList;\n        const TCB_t * const pxTCB = xTask;\n\n        configASSERT( pxTCB );\n\n        if( pxTCB == pxCurrentTCB )\n        {\n            /* The task calling this function is querying its own state. */\n            eReturn = eRunning;\n        }\n        else\n        {\n            taskENTER_CRITICAL();\n            {\n                pxStateList = listLIST_ITEM_CONTAINER( &( pxTCB->xStateListItem ) );\n                pxDelayedList = pxDelayedTaskList;\n                pxOverflowedDelayedList = pxOverflowDelayedTaskList;\n            }\n            taskEXIT_CRITICAL();\n\n            if( ( pxStateList == pxDelayedList ) || ( pxStateList == pxOverflowedDelayedList ) )\n            {\n                /* The task being queried is referenced from one of the Blocked\n                 * lists. */\n                eReturn = eBlocked;\n            }\n\n            #if ( INCLUDE_vTaskSuspend == 1 )\n                else if( pxStateList == &xSuspendedTaskList )\n                {\n                    /* The task being queried is referenced from the suspended\n                     * list.  Is it genuinely suspended or is it blocked\n                     * indefinitely? */\n                    if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL )\n                    {\n                        #if ( configUSE_TASK_NOTIFICATIONS == 1 )\n                        {\n                            BaseType_t x;\n\n                            /* The task does not appear on the event list item of\n                             * and of the RTOS objects, but could still be in the\n                             * blocked state if it is waiting on its notification\n                             * rather than waiting on an object.  If not, is\n                             * suspended. */\n                            eReturn = eSuspended;\n\n                            for( x = 0; x < configTASK_NOTIFICATION_ARRAY_ENTRIES; x++ )\n                            {\n                                if( pxTCB->ucNotifyState[ x ] == taskWAITING_NOTIFICATION )\n                                {\n                                    eReturn = eBlocked;\n                                    break;\n                                }\n                            }\n                        }\n                        #else /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */\n                        {\n                            eReturn = eSuspended;\n                        }\n                        #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */\n                    }\n                    else\n                    {\n                        eReturn = eBlocked;\n                    }\n                }\n            #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */\n\n            #if ( INCLUDE_vTaskDelete == 1 )\n                else if( ( pxStateList == &xTasksWaitingTermination ) || ( pxStateList == NULL ) )\n                {\n                    /* The task being queried is referenced from the deleted\n                     * tasks list, or it is not referenced from any lists at\n                     * all. */\n                    eReturn = eDeleted;\n                }\n            #endif\n\n            else /*lint !e525 Negative indentation is intended to make use of pre-processor clearer. */\n            {\n                /* If the task is not in any other state, it must be in the\n                 * Ready (including pending ready) state. */\n                eReturn = eReady;\n            }\n        }\n\n        return eReturn;\n    } /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */\n\n#endif /* INCLUDE_eTaskGetState */\n/*-----------------------------------------------------------*/\n\n#if ( INCLUDE_uxTaskPriorityGet == 1 )\n\n    UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask )\n    {\n        TCB_t const * pxTCB;\n        UBaseType_t uxReturn;\n\n        taskENTER_CRITICAL();\n        {\n            /* If null is passed in here then it is the priority of the task\n             * that called uxTaskPriorityGet() that is being queried. */\n            pxTCB = prvGetTCBFromHandle( xTask );\n            uxReturn = pxTCB->uxPriority;\n        }\n        taskEXIT_CRITICAL();\n\n        return uxReturn;\n    }\n\n#endif /* INCLUDE_uxTaskPriorityGet */\n/*-----------------------------------------------------------*/\n\n#if ( INCLUDE_uxTaskPriorityGet == 1 )\n\n    UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask )\n    {\n        TCB_t const * pxTCB;\n        UBaseType_t uxReturn, uxSavedInterruptState;\n\n        /* RTOS ports that support interrupt nesting have the concept of a\n         * maximum  system call (or maximum API call) interrupt priority.\n         * Interrupts that are  above the maximum system call priority are keep\n         * permanently enabled, even when the RTOS kernel is in a critical section,\n         * but cannot make any calls to FreeRTOS API functions.  If configASSERT()\n         * is defined in FreeRTOSConfig.h then\n         * portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion\n         * failure if a FreeRTOS API function is called from an interrupt that has\n         * been assigned a priority above the configured maximum system call\n         * priority.  Only FreeRTOS functions that end in FromISR can be called\n         * from interrupts  that have been assigned a priority at or (logically)\n         * below the maximum system call interrupt priority.  FreeRTOS maintains a\n         * separate interrupt safe API to ensure interrupt entry is as fast and as\n         * simple as possible.  More information (albeit Cortex-M specific) is\n         * provided on the following link:\n         * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\n        portASSERT_IF_INTERRUPT_PRIORITY_INVALID();\n\n        uxSavedInterruptState = portSET_INTERRUPT_MASK_FROM_ISR();\n        {\n            /* If null is passed in here then it is the priority of the calling\n             * task that is being queried. */\n            pxTCB = prvGetTCBFromHandle( xTask );\n            uxReturn = pxTCB->uxPriority;\n        }\n        portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptState );\n\n        return uxReturn;\n    }\n\n#endif /* INCLUDE_uxTaskPriorityGet */\n/*-----------------------------------------------------------*/\n\n#if ( INCLUDE_vTaskPrioritySet == 1 )\n\n    void vTaskPrioritySet( TaskHandle_t xTask,\n                           UBaseType_t uxNewPriority )\n    {\n        TCB_t * pxTCB;\n        UBaseType_t uxCurrentBasePriority, uxPriorityUsedOnEntry;\n        BaseType_t xYieldRequired = pdFALSE;\n\n        configASSERT( uxNewPriority < configMAX_PRIORITIES );\n\n        /* Ensure the new priority is valid. */\n        if( uxNewPriority >= ( UBaseType_t ) configMAX_PRIORITIES )\n        {\n            uxNewPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n\n        taskENTER_CRITICAL();\n        {\n            /* If null is passed in here then it is the priority of the calling\n             * task that is being changed. */\n            pxTCB = prvGetTCBFromHandle( xTask );\n\n            traceTASK_PRIORITY_SET( pxTCB, uxNewPriority );\n\n            #if ( configUSE_MUTEXES == 1 )\n            {\n                uxCurrentBasePriority = pxTCB->uxBasePriority;\n            }\n            #else\n            {\n                uxCurrentBasePriority = pxTCB->uxPriority;\n            }\n            #endif\n\n            if( uxCurrentBasePriority != uxNewPriority )\n            {\n                /* The priority change may have readied a task of higher\n                 * priority than the calling task. */\n                if( uxNewPriority > uxCurrentBasePriority )\n                {\n                    if( pxTCB != pxCurrentTCB )\n                    {\n                        /* The priority of a task other than the currently\n                         * running task is being raised.  Is the priority being\n                         * raised above that of the running task? */\n                        if( uxNewPriority >= pxCurrentTCB->uxPriority )\n                        {\n                            xYieldRequired = pdTRUE;\n                        }\n                        else\n                        {\n                            mtCOVERAGE_TEST_MARKER();\n                        }\n                    }\n                    else\n                    {\n                        /* The priority of the running task is being raised,\n                         * but the running task must already be the highest\n                         * priority task able to run so no yield is required. */\n                    }\n                }\n                else if( pxTCB == pxCurrentTCB )\n                {\n                    /* Setting the priority of the running task down means\n                     * there may now be another task of higher priority that\n                     * is ready to execute. */\n                    xYieldRequired = pdTRUE;\n                }\n                else\n                {\n                    /* Setting the priority of any other task down does not\n                     * require a yield as the running task must be above the\n                     * new priority of the task being modified. */\n                }\n\n                /* Remember the ready list the task might be referenced from\n                 * before its uxPriority member is changed so the\n                 * taskRESET_READY_PRIORITY() macro can function correctly. */\n                uxPriorityUsedOnEntry = pxTCB->uxPriority;\n\n                #if ( configUSE_MUTEXES == 1 )\n                {\n                    /* Only change the priority being used if the task is not\n                     * currently using an inherited priority. */\n                    if( pxTCB->uxBasePriority == pxTCB->uxPriority )\n                    {\n                        pxTCB->uxPriority = uxNewPriority;\n                    }\n                    else\n                    {\n                        mtCOVERAGE_TEST_MARKER();\n                    }\n\n                    /* The base priority gets set whatever. */\n                    pxTCB->uxBasePriority = uxNewPriority;\n                }\n                #else /* if ( configUSE_MUTEXES == 1 ) */\n                {\n                    pxTCB->uxPriority = uxNewPriority;\n                }\n                #endif /* if ( configUSE_MUTEXES == 1 ) */\n\n                /* Only reset the event list item value if the value is not\n                 * being used for anything else. */\n                if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )\n                {\n                    listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxNewPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\n                }\n                else\n                {\n                    mtCOVERAGE_TEST_MARKER();\n                }\n\n                /* If the task is in the blocked or suspended list we need do\n                 * nothing more than change its priority variable. However, if\n                 * the task is in a ready list it needs to be removed and placed\n                 * in the list appropriate to its new priority. */\n                if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE )\n                {\n                    /* The task is currently in its ready list - remove before\n                     * adding it to its new ready list.  As we are in a critical\n                     * section we can do this even if the scheduler is suspended. */\n                    if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )\n                    {\n                        /* It is known that the task is in its ready list so\n                         * there is no need to check again and the port level\n                         * reset macro can be called directly. */\n                        portRESET_READY_PRIORITY( uxPriorityUsedOnEntry, uxTopReadyPriority );\n                    }\n                    else\n                    {\n                        mtCOVERAGE_TEST_MARKER();\n                    }\n\n                    prvAddTaskToReadyList( pxTCB );\n                }\n                else\n                {\n                    mtCOVERAGE_TEST_MARKER();\n                }\n\n                if( xYieldRequired != pdFALSE )\n                {\n                    taskYIELD_IF_USING_PREEMPTION();\n                }\n                else\n                {\n                    mtCOVERAGE_TEST_MARKER();\n                }\n\n                /* Remove compiler warning about unused variables when the port\n                 * optimised task selection is not being used. */\n                ( void ) uxPriorityUsedOnEntry;\n            }\n        }\n        taskEXIT_CRITICAL();\n    }\n\n#endif /* INCLUDE_vTaskPrioritySet */\n/*-----------------------------------------------------------*/\n\n#if ( INCLUDE_vTaskSuspend == 1 )\n\n    void vTaskSuspend( TaskHandle_t xTaskToSuspend )\n    {\n        TCB_t * pxTCB;\n\n        taskENTER_CRITICAL();\n        {\n            /* If null is passed in here then it is the running task that is\n             * being suspended. */\n            pxTCB = prvGetTCBFromHandle( xTaskToSuspend );\n\n            traceTASK_SUSPEND( pxTCB );\n\n            /* Remove task from the ready/delayed list and place in the\n             * suspended list. */\n            if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )\n            {\n                taskRESET_READY_PRIORITY( pxTCB->uxPriority );\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n\n            /* Is the task waiting on an event also? */\n            if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )\n            {\n                ( void ) uxListRemove( &( pxTCB->xEventListItem ) );\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n\n            vListInsertEnd( &xSuspendedTaskList, &( pxTCB->xStateListItem ) );\n\n            #if ( configUSE_TASK_NOTIFICATIONS == 1 )\n            {\n                BaseType_t x;\n\n                for( x = 0; x < configTASK_NOTIFICATION_ARRAY_ENTRIES; x++ )\n                {\n                    if( pxTCB->ucNotifyState[ x ] == taskWAITING_NOTIFICATION )\n                    {\n                        /* The task was blocked to wait for a notification, but is\n                         * now suspended, so no notification was received. */\n                        pxTCB->ucNotifyState[ x ] = taskNOT_WAITING_NOTIFICATION;\n                    }\n                }\n            }\n            #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */\n        }\n        taskEXIT_CRITICAL();\n\n        if( xSchedulerRunning != pdFALSE )\n        {\n            /* Reset the next expected unblock time in case it referred to the\n             * task that is now in the Suspended state. */\n            taskENTER_CRITICAL();\n            {\n                prvResetNextTaskUnblockTime();\n            }\n            taskEXIT_CRITICAL();\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n\n        if( pxTCB == pxCurrentTCB )\n        {\n            if( xSchedulerRunning != pdFALSE )\n            {\n                /* The current task has just been suspended. */\n                configASSERT( uxSchedulerSuspended == 0 );\n                portYIELD_WITHIN_API();\n            }\n            else\n            {\n                /* The scheduler is not running, but the task that was pointed\n                 * to by pxCurrentTCB has just been suspended and pxCurrentTCB\n                 * must be adjusted to point to a different task. */\n                if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == uxCurrentNumberOfTasks ) /*lint !e931 Right has no side effect, just volatile. */\n                {\n                    /* No other tasks are ready, so set pxCurrentTCB back to\n                     * NULL so when the next task is created pxCurrentTCB will\n                     * be set to point to it no matter what its relative priority\n                     * is. */\n                    pxCurrentTCB = NULL;\n                }\n                else\n                {\n                    vTaskSwitchContext();\n                }\n            }\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n    }\n\n#endif /* INCLUDE_vTaskSuspend */\n/*-----------------------------------------------------------*/\n\n#if ( INCLUDE_vTaskSuspend == 1 )\n\n    static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask )\n    {\n        BaseType_t xReturn = pdFALSE;\n        const TCB_t * const pxTCB = xTask;\n\n        /* Accesses xPendingReadyList so must be called from a critical\n         * section. */\n\n        /* It does not make sense to check if the calling task is suspended. */\n        configASSERT( xTask );\n\n        /* Is the task being resumed actually in the suspended list? */\n        if( listIS_CONTAINED_WITHIN( &xSuspendedTaskList, &( pxTCB->xStateListItem ) ) != pdFALSE )\n        {\n            /* Has the task already been resumed from within an ISR? */\n            if( listIS_CONTAINED_WITHIN( &xPendingReadyList, &( pxTCB->xEventListItem ) ) == pdFALSE )\n            {\n                /* Is it in the suspended list because it is in the Suspended\n                 * state, or because is is blocked with no timeout? */\n                if( listIS_CONTAINED_WITHIN( NULL, &( pxTCB->xEventListItem ) ) != pdFALSE ) /*lint !e961.  The cast is only redundant when NULL is used. */\n                {\n                    xReturn = pdTRUE;\n                }\n                else\n                {\n                    mtCOVERAGE_TEST_MARKER();\n                }\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n\n        return xReturn;\n    } /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */\n\n#endif /* INCLUDE_vTaskSuspend */\n/*-----------------------------------------------------------*/\n\n#if ( INCLUDE_vTaskSuspend == 1 )\n\n    void vTaskResume( TaskHandle_t xTaskToResume )\n    {\n        TCB_t * const pxTCB = xTaskToResume;\n\n        /* It does not make sense to resume the calling task. */\n        configASSERT( xTaskToResume );\n\n        /* The parameter cannot be NULL as it is impossible to resume the\n         * currently executing task. */\n        if( ( pxTCB != pxCurrentTCB ) && ( pxTCB != NULL ) )\n        {\n            taskENTER_CRITICAL();\n            {\n                if( prvTaskIsTaskSuspended( pxTCB ) != pdFALSE )\n                {\n                    traceTASK_RESUME( pxTCB );\n\n                    /* The ready list can be accessed even if the scheduler is\n                     * suspended because this is inside a critical section. */\n                    ( void ) uxListRemove( &( pxTCB->xStateListItem ) );\n                    prvAddTaskToReadyList( pxTCB );\n\n                    /* A higher priority task may have just been resumed. */\n                    if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )\n                    {\n                        /* This yield may not cause the task just resumed to run,\n                         * but will leave the lists in the correct state for the\n                         * next yield. */\n                        taskYIELD_IF_USING_PREEMPTION();\n                    }\n                    else\n                    {\n                        mtCOVERAGE_TEST_MARKER();\n                    }\n                }\n                else\n                {\n                    mtCOVERAGE_TEST_MARKER();\n                }\n            }\n            taskEXIT_CRITICAL();\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n    }\n\n#endif /* INCLUDE_vTaskSuspend */\n\n/*-----------------------------------------------------------*/\n\n#if ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) )\n\n    BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume )\n    {\n        BaseType_t xYieldRequired = pdFALSE;\n        TCB_t * const pxTCB = xTaskToResume;\n        UBaseType_t uxSavedInterruptStatus;\n\n        configASSERT( xTaskToResume );\n\n        /* RTOS ports that support interrupt nesting have the concept of a\n         * maximum  system call (or maximum API call) interrupt priority.\n         * Interrupts that are  above the maximum system call priority are keep\n         * permanently enabled, even when the RTOS kernel is in a critical section,\n         * but cannot make any calls to FreeRTOS API functions.  If configASSERT()\n         * is defined in FreeRTOSConfig.h then\n         * portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion\n         * failure if a FreeRTOS API function is called from an interrupt that has\n         * been assigned a priority above the configured maximum system call\n         * priority.  Only FreeRTOS functions that end in FromISR can be called\n         * from interrupts  that have been assigned a priority at or (logically)\n         * below the maximum system call interrupt priority.  FreeRTOS maintains a\n         * separate interrupt safe API to ensure interrupt entry is as fast and as\n         * simple as possible.  More information (albeit Cortex-M specific) is\n         * provided on the following link:\n         * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\n        portASSERT_IF_INTERRUPT_PRIORITY_INVALID();\n\n        uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();\n        {\n            if( prvTaskIsTaskSuspended( pxTCB ) != pdFALSE )\n            {\n                traceTASK_RESUME_FROM_ISR( pxTCB );\n\n                /* Check the ready lists can be accessed. */\n                if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )\n                {\n                    /* Ready lists can be accessed so move the task from the\n                     * suspended list to the ready list directly. */\n                    if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )\n                    {\n                        xYieldRequired = pdTRUE;\n\n                        /* Mark that a yield is pending in case the user is not\n                         * using the return value to initiate a context switch\n                         * from the ISR using portYIELD_FROM_ISR. */\n                        xYieldPending = pdTRUE;\n                    }\n                    else\n                    {\n                        mtCOVERAGE_TEST_MARKER();\n                    }\n\n                    ( void ) uxListRemove( &( pxTCB->xStateListItem ) );\n                    prvAddTaskToReadyList( pxTCB );\n                }\n                else\n                {\n                    /* The delayed or ready lists cannot be accessed so the task\n                     * is held in the pending ready list until the scheduler is\n                     * unsuspended. */\n                    vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );\n                }\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n        portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\n\n        return xYieldRequired;\n    }\n\n#endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */\n/*-----------------------------------------------------------*/\n\nvoid vTaskStartScheduler( void )\n{\n    BaseType_t xReturn;\n\n    /* Add the idle task at the lowest priority. */\n    #if ( configSUPPORT_STATIC_ALLOCATION == 1 )\n    {\n        StaticTask_t * pxIdleTaskTCBBuffer = NULL;\n        StackType_t * pxIdleTaskStackBuffer = NULL;\n        uint32_t ulIdleTaskStackSize;\n\n        /* The Idle task is created using user provided RAM - obtain the\n         * address of the RAM then create the idle task. */\n        vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize );\n        xIdleTaskHandle = xTaskCreateStatic( prvIdleTask,\n                                             configIDLE_TASK_NAME,\n                                             ulIdleTaskStackSize,\n                                             ( void * ) NULL,       /*lint !e961.  The cast is not redundant for all compilers. */\n                                             portPRIVILEGE_BIT,     /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */\n                                             pxIdleTaskStackBuffer,\n                                             pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */\n\n        if( xIdleTaskHandle != NULL )\n        {\n            xReturn = pdPASS;\n        }\n        else\n        {\n            xReturn = pdFAIL;\n        }\n    }\n    #else /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */\n    {\n        /* The Idle task is being created using dynamically allocated RAM. */\n        xReturn = xTaskCreate( prvIdleTask,\n                               configIDLE_TASK_NAME,\n                               configMINIMAL_STACK_SIZE,\n                               ( void * ) NULL,\n                               portPRIVILEGE_BIT,  /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */\n                               &xIdleTaskHandle ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */\n    }\n    #endif /* configSUPPORT_STATIC_ALLOCATION */\n\n    #if ( configUSE_TIMERS == 1 )\n    {\n        if( xReturn == pdPASS )\n        {\n            xReturn = xTimerCreateTimerTask();\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n    }\n    #endif /* configUSE_TIMERS */\n\n    if( xReturn == pdPASS )\n    {\n        /* freertos_tasks_c_additions_init() should only be called if the user\n         * definable macro FREERTOS_TASKS_C_ADDITIONS_INIT() is defined, as that is\n         * the only macro called by the function. */\n        #ifdef FREERTOS_TASKS_C_ADDITIONS_INIT\n        {\n            freertos_tasks_c_additions_init();\n        }\n        #endif\n\n        /* Interrupts are turned off here, to ensure a tick does not occur\n         * before or during the call to xPortStartScheduler().  The stacks of\n         * the created tasks contain a status word with interrupts switched on\n         * so interrupts will automatically get re-enabled when the first task\n         * starts to run. */\n        portDISABLE_INTERRUPTS();\n\n        #if ( ( configUSE_NEWLIB_REENTRANT == 1 ) || ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 ) )\n        {\n            /* Switch C-Runtime's TLS Block to point to the TLS\n             * block specific to the task that will run first. */\n            configSET_TLS_BLOCK( pxCurrentTCB->xTLSBlock );\n        }\n        #endif\n\n        xNextTaskUnblockTime = portMAX_DELAY;\n        xSchedulerRunning = pdTRUE;\n        xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT;\n\n        /* If configGENERATE_RUN_TIME_STATS is defined then the following\n         * macro must be defined to configure the timer/counter used to generate\n         * the run time counter time base.   NOTE:  If configGENERATE_RUN_TIME_STATS\n         * is set to 0 and the following line fails to build then ensure you do not\n         * have portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() defined in your\n         * FreeRTOSConfig.h file. */\n        portCONFIGURE_TIMER_FOR_RUN_TIME_STATS();\n\n        traceTASK_SWITCHED_IN();\n\n        /* Setting up the timer tick is hardware specific and thus in the\n         * portable interface. */\n        xPortStartScheduler();\n\n        /* In most cases, xPortStartScheduler() will not return. If it\n         * returns pdTRUE then there was not enough heap memory available\n         * to create either the Idle or the Timer task. If it returned\n         * pdFALSE, then the application called xTaskEndScheduler().\n         * Most ports don't implement xTaskEndScheduler() as there is\n         * nothing to return to. */\n    }\n    else\n    {\n        /* This line will only be reached if the kernel could not be started,\n         * because there was not enough FreeRTOS heap to create the idle task\n         * or the timer task. */\n        configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY );\n    }\n\n    /* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0,\n     * meaning xIdleTaskHandle is not used anywhere else. */\n    ( void ) xIdleTaskHandle;\n\n    /* OpenOCD makes use of uxTopUsedPriority for thread debugging. Prevent uxTopUsedPriority\n     * from getting optimized out as it is no longer used by the kernel. */\n    ( void ) uxTopUsedPriority;\n}\n/*-----------------------------------------------------------*/\n\nvoid vTaskEndScheduler( void )\n{\n    /* Stop the scheduler interrupts and call the portable scheduler end\n     * routine so the original ISRs can be restored if necessary.  The port\n     * layer must ensure interrupts enable  bit is left in the correct state. */\n    portDISABLE_INTERRUPTS();\n    xSchedulerRunning = pdFALSE;\n    vPortEndScheduler();\n}\n/*----------------------------------------------------------*/\n\nvoid vTaskSuspendAll( void )\n{\n    /* A critical section is not required as the variable is of type\n     * BaseType_t.  Please read Richard Barry's reply in the following link to a\n     * post in the FreeRTOS support forum before reporting this as a bug! -\n     * https://goo.gl/wu4acr */\n\n    /* portSOFTWARE_BARRIER() is only implemented for emulated/simulated ports that\n     * do not otherwise exhibit real time behaviour. */\n    portSOFTWARE_BARRIER();\n\n    /* The scheduler is suspended if uxSchedulerSuspended is non-zero.  An increment\n     * is used to allow calls to vTaskSuspendAll() to nest. */\n    ++uxSchedulerSuspended;\n\n    /* Enforces ordering for ports and optimised compilers that may otherwise place\n     * the above increment elsewhere. */\n    portMEMORY_BARRIER();\n}\n/*----------------------------------------------------------*/\n\n#if ( configUSE_TICKLESS_IDLE != 0 )\n\n    static TickType_t prvGetExpectedIdleTime( void )\n    {\n        TickType_t xReturn;\n        UBaseType_t uxHigherPriorityReadyTasks = pdFALSE;\n\n        /* uxHigherPriorityReadyTasks takes care of the case where\n         * configUSE_PREEMPTION is 0, so there may be tasks above the idle priority\n         * task that are in the Ready state, even though the idle task is\n         * running. */\n        #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 )\n        {\n            if( uxTopReadyPriority > tskIDLE_PRIORITY )\n            {\n                uxHigherPriorityReadyTasks = pdTRUE;\n            }\n        }\n        #else\n        {\n            const UBaseType_t uxLeastSignificantBit = ( UBaseType_t ) 0x01;\n\n            /* When port optimised task selection is used the uxTopReadyPriority\n             * variable is used as a bit map.  If bits other than the least\n             * significant bit are set then there are tasks that have a priority\n             * above the idle priority that are in the Ready state.  This takes\n             * care of the case where the co-operative scheduler is in use. */\n            if( uxTopReadyPriority > uxLeastSignificantBit )\n            {\n                uxHigherPriorityReadyTasks = pdTRUE;\n            }\n        }\n        #endif /* if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 ) */\n\n        if( pxCurrentTCB->uxPriority > tskIDLE_PRIORITY )\n        {\n            xReturn = 0;\n        }\n        else if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > 1 )\n        {\n            /* There are other idle priority tasks in the ready state.  If\n             * time slicing is used then the very next tick interrupt must be\n             * processed. */\n            xReturn = 0;\n        }\n        else if( uxHigherPriorityReadyTasks != pdFALSE )\n        {\n            /* There are tasks in the Ready state that have a priority above the\n             * idle priority.  This path can only be reached if\n             * configUSE_PREEMPTION is 0. */\n            xReturn = 0;\n        }\n        else\n        {\n            xReturn = xNextTaskUnblockTime - xTickCount;\n        }\n\n        return xReturn;\n    }\n\n#endif /* configUSE_TICKLESS_IDLE */\n/*----------------------------------------------------------*/\n\nBaseType_t xTaskResumeAll( void )\n{\n    TCB_t * pxTCB = NULL;\n    BaseType_t xAlreadyYielded = pdFALSE;\n\n    /* If uxSchedulerSuspended is zero then this function does not match a\n     * previous call to vTaskSuspendAll(). */\n    configASSERT( uxSchedulerSuspended );\n\n    /* It is possible that an ISR caused a task to be removed from an event\n     * list while the scheduler was suspended.  If this was the case then the\n     * removed task will have been added to the xPendingReadyList.  Once the\n     * scheduler has been resumed it is safe to move all the pending ready\n     * tasks from this list into their appropriate ready list. */\n    taskENTER_CRITICAL();\n    {\n        --uxSchedulerSuspended;\n\n        if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )\n        {\n            if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U )\n            {\n                /* Move any readied tasks from the pending list into the\n                 * appropriate ready list. */\n                while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )\n                {\n                    pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */\n                    listREMOVE_ITEM( &( pxTCB->xEventListItem ) );\n                    portMEMORY_BARRIER();\n                    listREMOVE_ITEM( &( pxTCB->xStateListItem ) );\n                    prvAddTaskToReadyList( pxTCB );\n\n                    /* If the moved task has a priority higher than or equal to\n                     * the current task then a yield must be performed. */\n                    if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )\n                    {\n                        xYieldPending = pdTRUE;\n                    }\n                    else\n                    {\n                        mtCOVERAGE_TEST_MARKER();\n                    }\n                }\n\n                if( pxTCB != NULL )\n                {\n                    /* A task was unblocked while the scheduler was suspended,\n                     * which may have prevented the next unblock time from being\n                     * re-calculated, in which case re-calculate it now.  Mainly\n                     * important for low power tickless implementations, where\n                     * this can prevent an unnecessary exit from low power\n                     * state. */\n                    prvResetNextTaskUnblockTime();\n                }\n\n                /* If any ticks occurred while the scheduler was suspended then\n                 * they should be processed now.  This ensures the tick count does\n                 * not  slip, and that any delayed tasks are resumed at the correct\n                 * time. */\n                {\n                    TickType_t xPendedCounts = xPendedTicks; /* Non-volatile copy. */\n\n                    if( xPendedCounts > ( TickType_t ) 0U )\n                    {\n                        do\n                        {\n                            if( xTaskIncrementTick() != pdFALSE )\n                            {\n                                xYieldPending = pdTRUE;\n                            }\n                            else\n                            {\n                                mtCOVERAGE_TEST_MARKER();\n                            }\n\n                            --xPendedCounts;\n                        } while( xPendedCounts > ( TickType_t ) 0U );\n\n                        xPendedTicks = 0;\n                    }\n                    else\n                    {\n                        mtCOVERAGE_TEST_MARKER();\n                    }\n                }\n\n                if( xYieldPending != pdFALSE )\n                {\n                    #if ( configUSE_PREEMPTION != 0 )\n                    {\n                        xAlreadyYielded = pdTRUE;\n                    }\n                    #endif\n                    taskYIELD_IF_USING_PREEMPTION();\n                }\n                else\n                {\n                    mtCOVERAGE_TEST_MARKER();\n                }\n            }\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n    }\n    taskEXIT_CRITICAL();\n\n    return xAlreadyYielded;\n}\n/*-----------------------------------------------------------*/\n\nTickType_t xTaskGetTickCount( void )\n{\n    TickType_t xTicks;\n\n    /* Critical section required if running on a 16 bit processor. */\n    portTICK_TYPE_ENTER_CRITICAL();\n    {\n        xTicks = xTickCount;\n    }\n    portTICK_TYPE_EXIT_CRITICAL();\n\n    return xTicks;\n}\n/*-----------------------------------------------------------*/\n\nTickType_t xTaskGetTickCountFromISR( void )\n{\n    TickType_t xReturn;\n    UBaseType_t uxSavedInterruptStatus;\n\n    /* RTOS ports that support interrupt nesting have the concept of a maximum\n     * system call (or maximum API call) interrupt priority.  Interrupts that are\n     * above the maximum system call priority are kept permanently enabled, even\n     * when the RTOS kernel is in a critical section, but cannot make any calls to\n     * FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h\n     * then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion\n     * failure if a FreeRTOS API function is called from an interrupt that has been\n     * assigned a priority above the configured maximum system call priority.\n     * Only FreeRTOS functions that end in FromISR can be called from interrupts\n     * that have been assigned a priority at or (logically) below the maximum\n     * system call  interrupt priority.  FreeRTOS maintains a separate interrupt\n     * safe API to ensure interrupt entry is as fast and as simple as possible.\n     * More information (albeit Cortex-M specific) is provided on the following\n     * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\n    portASSERT_IF_INTERRUPT_PRIORITY_INVALID();\n\n    uxSavedInterruptStatus = portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR();\n    {\n        xReturn = xTickCount;\n    }\n    portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\n\n    return xReturn;\n}\n/*-----------------------------------------------------------*/\n\nUBaseType_t uxTaskGetNumberOfTasks( void )\n{\n    /* A critical section is not required because the variables are of type\n     * BaseType_t. */\n    return uxCurrentNumberOfTasks;\n}\n/*-----------------------------------------------------------*/\n\nchar * pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n{\n    TCB_t * pxTCB;\n\n    /* If null is passed in here then the name of the calling task is being\n     * queried. */\n    pxTCB = prvGetTCBFromHandle( xTaskToQuery );\n    configASSERT( pxTCB );\n    return &( pxTCB->pcTaskName[ 0 ] );\n}\n/*-----------------------------------------------------------*/\n\n#if ( INCLUDE_xTaskGetHandle == 1 )\n\n    static TCB_t * prvSearchForNameWithinSingleList( List_t * pxList,\n                                                     const char pcNameToQuery[] )\n    {\n        TCB_t * pxNextTCB;\n        TCB_t * pxFirstTCB;\n        TCB_t * pxReturn = NULL;\n        UBaseType_t x;\n        char cNextChar;\n        BaseType_t xBreakLoop;\n\n        /* This function is called with the scheduler suspended. */\n\n        if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )\n        {\n            listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */\n\n            do\n            {\n                listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */\n\n                /* Check each character in the name looking for a match or\n                 * mismatch. */\n                xBreakLoop = pdFALSE;\n\n                for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )\n                {\n                    cNextChar = pxNextTCB->pcTaskName[ x ];\n\n                    if( cNextChar != pcNameToQuery[ x ] )\n                    {\n                        /* Characters didn't match. */\n                        xBreakLoop = pdTRUE;\n                    }\n                    else if( cNextChar == ( char ) 0x00 )\n                    {\n                        /* Both strings terminated, a match must have been\n                         * found. */\n                        pxReturn = pxNextTCB;\n                        xBreakLoop = pdTRUE;\n                    }\n                    else\n                    {\n                        mtCOVERAGE_TEST_MARKER();\n                    }\n\n                    if( xBreakLoop != pdFALSE )\n                    {\n                        break;\n                    }\n                }\n\n                if( pxReturn != NULL )\n                {\n                    /* The handle has been found. */\n                    break;\n                }\n            } while( pxNextTCB != pxFirstTCB );\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n\n        return pxReturn;\n    }\n\n#endif /* INCLUDE_xTaskGetHandle */\n/*-----------------------------------------------------------*/\n\n#if ( INCLUDE_xTaskGetHandle == 1 )\n\n    TaskHandle_t xTaskGetHandle( const char * pcNameToQuery ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n    {\n        UBaseType_t uxQueue = configMAX_PRIORITIES;\n        TCB_t * pxTCB;\n\n        /* Task names will be truncated to configMAX_TASK_NAME_LEN - 1 bytes. */\n        configASSERT( strlen( pcNameToQuery ) < configMAX_TASK_NAME_LEN );\n\n        vTaskSuspendAll();\n        {\n            /* Search the ready lists. */\n            do\n            {\n                uxQueue--;\n                pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) &( pxReadyTasksLists[ uxQueue ] ), pcNameToQuery );\n\n                if( pxTCB != NULL )\n                {\n                    /* Found the handle. */\n                    break;\n                }\n            } while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\n\n            /* Search the delayed lists. */\n            if( pxTCB == NULL )\n            {\n                pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) pxDelayedTaskList, pcNameToQuery );\n            }\n\n            if( pxTCB == NULL )\n            {\n                pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) pxOverflowDelayedTaskList, pcNameToQuery );\n            }\n\n            #if ( INCLUDE_vTaskSuspend == 1 )\n            {\n                if( pxTCB == NULL )\n                {\n                    /* Search the suspended list. */\n                    pxTCB = prvSearchForNameWithinSingleList( &xSuspendedTaskList, pcNameToQuery );\n                }\n            }\n            #endif\n\n            #if ( INCLUDE_vTaskDelete == 1 )\n            {\n                if( pxTCB == NULL )\n                {\n                    /* Search the deleted list. */\n                    pxTCB = prvSearchForNameWithinSingleList( &xTasksWaitingTermination, pcNameToQuery );\n                }\n            }\n            #endif\n        }\n        ( void ) xTaskResumeAll();\n\n        return pxTCB;\n    }\n\n#endif /* INCLUDE_xTaskGetHandle */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TRACE_FACILITY == 1 )\n\n    UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,\n                                      const UBaseType_t uxArraySize,\n                                      configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime )\n    {\n        UBaseType_t uxTask = 0, uxQueue = configMAX_PRIORITIES;\n\n        vTaskSuspendAll();\n        {\n            /* Is there a space in the array for each task in the system? */\n            if( uxArraySize >= uxCurrentNumberOfTasks )\n            {\n                /* Fill in an TaskStatus_t structure with information on each\n                 * task in the Ready state. */\n                do\n                {\n                    uxQueue--;\n                    uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &( pxReadyTasksLists[ uxQueue ] ), eReady );\n                } while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\n\n                /* Fill in an TaskStatus_t structure with information on each\n                 * task in the Blocked state. */\n                uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxDelayedTaskList, eBlocked );\n                uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxOverflowDelayedTaskList, eBlocked );\n\n                #if ( INCLUDE_vTaskDelete == 1 )\n                {\n                    /* Fill in an TaskStatus_t structure with information on\n                     * each task that has been deleted but not yet cleaned up. */\n                    uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xTasksWaitingTermination, eDeleted );\n                }\n                #endif\n\n                #if ( INCLUDE_vTaskSuspend == 1 )\n                {\n                    /* Fill in an TaskStatus_t structure with information on\n                     * each task in the Suspended state. */\n                    uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xSuspendedTaskList, eSuspended );\n                }\n                #endif\n\n                #if ( configGENERATE_RUN_TIME_STATS == 1 )\n                {\n                    if( pulTotalRunTime != NULL )\n                    {\n                        #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE\n                            portALT_GET_RUN_TIME_COUNTER_VALUE( ( *pulTotalRunTime ) );\n                        #else\n                            *pulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE();\n                        #endif\n                    }\n                }\n                #else /* if ( configGENERATE_RUN_TIME_STATS == 1 ) */\n                {\n                    if( pulTotalRunTime != NULL )\n                    {\n                        *pulTotalRunTime = 0;\n                    }\n                }\n                #endif /* if ( configGENERATE_RUN_TIME_STATS == 1 ) */\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n        ( void ) xTaskResumeAll();\n\n        return uxTask;\n    }\n\n#endif /* configUSE_TRACE_FACILITY */\n/*----------------------------------------------------------*/\n\n#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )\n\n    TaskHandle_t xTaskGetIdleTaskHandle( void )\n    {\n        /* If xTaskGetIdleTaskHandle() is called before the scheduler has been\n         * started, then xIdleTaskHandle will be NULL. */\n        configASSERT( ( xIdleTaskHandle != NULL ) );\n        return xIdleTaskHandle;\n    }\n\n#endif /* INCLUDE_xTaskGetIdleTaskHandle */\n/*----------------------------------------------------------*/\n\n/* This conditional compilation should use inequality to 0, not equality to 1.\n * This is to ensure vTaskStepTick() is available when user defined low power mode\n * implementations require configUSE_TICKLESS_IDLE to be set to a value other than\n * 1. */\n#if ( configUSE_TICKLESS_IDLE != 0 )\n\n    void vTaskStepTick( TickType_t xTicksToJump )\n    {\n        /* Correct the tick count value after a period during which the tick\n         * was suppressed.  Note this does *not* call the tick hook function for\n         * each stepped tick. */\n        configASSERT( ( xTickCount + xTicksToJump ) <= xNextTaskUnblockTime );\n\n        if( ( xTickCount + xTicksToJump ) == xNextTaskUnblockTime )\n        {\n            /* Arrange for xTickCount to reach xNextTaskUnblockTime in\n             * xTaskIncrementTick() when the scheduler resumes.  This ensures\n             * that any delayed tasks are resumed at the correct time. */\n            configASSERT( uxSchedulerSuspended );\n            configASSERT( xTicksToJump != ( TickType_t ) 0 );\n\n            /* Prevent the tick interrupt modifying xPendedTicks simultaneously. */\n            taskENTER_CRITICAL();\n            {\n                xPendedTicks++;\n            }\n            taskEXIT_CRITICAL();\n            xTicksToJump--;\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n\n        xTickCount += xTicksToJump;\n        traceINCREASE_TICK_COUNT( xTicksToJump );\n    }\n\n#endif /* configUSE_TICKLESS_IDLE */\n/*----------------------------------------------------------*/\n\nBaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp )\n{\n    BaseType_t xYieldOccurred;\n\n    /* Must not be called with the scheduler suspended as the implementation\n     * relies on xPendedTicks being wound down to 0 in xTaskResumeAll(). */\n    configASSERT( uxSchedulerSuspended == 0 );\n\n    /* Use xPendedTicks to mimic xTicksToCatchUp number of ticks occurring when\n     * the scheduler is suspended so the ticks are executed in xTaskResumeAll(). */\n    vTaskSuspendAll();\n\n    /* Prevent the tick interrupt modifying xPendedTicks simultaneously. */\n    taskENTER_CRITICAL();\n    {\n        xPendedTicks += xTicksToCatchUp;\n    }\n    taskEXIT_CRITICAL();\n    xYieldOccurred = xTaskResumeAll();\n\n    return xYieldOccurred;\n}\n/*----------------------------------------------------------*/\n\n#if ( INCLUDE_xTaskAbortDelay == 1 )\n\n    BaseType_t xTaskAbortDelay( TaskHandle_t xTask )\n    {\n        TCB_t * pxTCB = xTask;\n        BaseType_t xReturn;\n\n        configASSERT( pxTCB );\n\n        vTaskSuspendAll();\n        {\n            /* A task can only be prematurely removed from the Blocked state if\n             * it is actually in the Blocked state. */\n            if( eTaskGetState( xTask ) == eBlocked )\n            {\n                xReturn = pdPASS;\n\n                /* Remove the reference to the task from the blocked list.  An\n                 * interrupt won't touch the xStateListItem because the\n                 * scheduler is suspended. */\n                ( void ) uxListRemove( &( pxTCB->xStateListItem ) );\n\n                /* Is the task waiting on an event also?  If so remove it from\n                 * the event list too.  Interrupts can touch the event list item,\n                 * even though the scheduler is suspended, so a critical section\n                 * is used. */\n                taskENTER_CRITICAL();\n                {\n                    if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )\n                    {\n                        ( void ) uxListRemove( &( pxTCB->xEventListItem ) );\n\n                        /* This lets the task know it was forcibly removed from the\n                         * blocked state so it should not re-evaluate its block time and\n                         * then block again. */\n                        pxTCB->ucDelayAborted = pdTRUE;\n                    }\n                    else\n                    {\n                        mtCOVERAGE_TEST_MARKER();\n                    }\n                }\n                taskEXIT_CRITICAL();\n\n                /* Place the unblocked task into the appropriate ready list. */\n                prvAddTaskToReadyList( pxTCB );\n\n                /* A task being unblocked cannot cause an immediate context\n                 * switch if preemption is turned off. */\n                #if ( configUSE_PREEMPTION == 1 )\n                {\n                    /* Preemption is on, but a context switch should only be\n                     * performed if the unblocked task has a priority that is\n                     * higher than the currently executing task. */\n                    if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )\n                    {\n                        /* Pend the yield to be performed when the scheduler\n                         * is unsuspended. */\n                        xYieldPending = pdTRUE;\n                    }\n                    else\n                    {\n                        mtCOVERAGE_TEST_MARKER();\n                    }\n                }\n                #endif /* configUSE_PREEMPTION */\n            }\n            else\n            {\n                xReturn = pdFAIL;\n            }\n        }\n        ( void ) xTaskResumeAll();\n\n        return xReturn;\n    }\n\n#endif /* INCLUDE_xTaskAbortDelay */\n/*----------------------------------------------------------*/\n\nBaseType_t xTaskIncrementTick( void )\n{\n    TCB_t * pxTCB;\n    TickType_t xItemValue;\n    BaseType_t xSwitchRequired = pdFALSE;\n\n    /* Called by the portable layer each time a tick interrupt occurs.\n     * Increments the tick then checks to see if the new tick value will cause any\n     * tasks to be unblocked. */\n    traceTASK_INCREMENT_TICK( xTickCount );\n\n    if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )\n    {\n        /* Minor optimisation.  The tick count cannot change in this\n         * block. */\n        const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;\n\n        /* Increment the RTOS tick, switching the delayed and overflowed\n         * delayed lists if it wraps to 0. */\n        xTickCount = xConstTickCount;\n\n        if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */\n        {\n            taskSWITCH_DELAYED_LISTS();\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n\n        /* See if this tick has made a timeout expire.  Tasks are stored in\n         * the  queue in the order of their wake time - meaning once one task\n         * has been found whose block time has not expired there is no need to\n         * look any further down the list. */\n        if( xConstTickCount >= xNextTaskUnblockTime )\n        {\n            for( ; ; )\n            {\n                if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )\n                {\n                    /* The delayed list is empty.  Set xNextTaskUnblockTime\n                     * to the maximum possible value so it is extremely\n                     * unlikely that the\n                     * if( xTickCount >= xNextTaskUnblockTime ) test will pass\n                     * next time through. */\n                    xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\n                    break;\n                }\n                else\n                {\n                    /* The delayed list is not empty, get the value of the\n                     * item at the head of the delayed list.  This is the time\n                     * at which the task at the head of the delayed list must\n                     * be removed from the Blocked state. */\n                    pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */\n                    xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) );\n\n                    if( xConstTickCount < xItemValue )\n                    {\n                        /* It is not time to unblock this item yet, but the\n                         * item value is the time at which the task at the head\n                         * of the blocked list must be removed from the Blocked\n                         * state -  so record the item value in\n                         * xNextTaskUnblockTime. */\n                        xNextTaskUnblockTime = xItemValue;\n                        break; /*lint !e9011 Code structure here is deemed easier to understand with multiple breaks. */\n                    }\n                    else\n                    {\n                        mtCOVERAGE_TEST_MARKER();\n                    }\n\n                    /* It is time to remove the item from the Blocked state. */\n                    listREMOVE_ITEM( &( pxTCB->xStateListItem ) );\n\n                    /* Is the task waiting on an event also?  If so remove\n                     * it from the event list. */\n                    if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )\n                    {\n                        listREMOVE_ITEM( &( pxTCB->xEventListItem ) );\n                    }\n                    else\n                    {\n                        mtCOVERAGE_TEST_MARKER();\n                    }\n\n                    /* Place the unblocked task into the appropriate ready\n                     * list. */\n                    prvAddTaskToReadyList( pxTCB );\n\n                    /* A task being unblocked cannot cause an immediate\n                     * context switch if preemption is turned off. */\n                    #if ( configUSE_PREEMPTION == 1 )\n                    {\n                        /* Preemption is on, but a context switch should\n                         * only be performed if the unblocked task's\n                         * priority is higher than the currently executing\n                         * task.\n                         * The case of equal priority tasks sharing\n                         * processing time (which happens when both\n                         * preemption and time slicing are on) is\n                         * handled below.*/\n                        if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )\n                        {\n                            xSwitchRequired = pdTRUE;\n                        }\n                        else\n                        {\n                            mtCOVERAGE_TEST_MARKER();\n                        }\n                    }\n                    #endif /* configUSE_PREEMPTION */\n                }\n            }\n        }\n\n        /* Tasks of equal priority to the currently running task will share\n         * processing time (time slice) if preemption is on, and the application\n         * writer has not explicitly turned time slicing off. */\n        #if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) )\n        {\n            if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 )\n            {\n                xSwitchRequired = pdTRUE;\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n        #endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) */\n\n        #if ( configUSE_TICK_HOOK == 1 )\n        {\n            /* Guard against the tick hook being called when the pended tick\n             * count is being unwound (when the scheduler is being unlocked). */\n            if( xPendedTicks == ( TickType_t ) 0 )\n            {\n                vApplicationTickHook();\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n        #endif /* configUSE_TICK_HOOK */\n\n        #if ( configUSE_PREEMPTION == 1 )\n        {\n            if( xYieldPending != pdFALSE )\n            {\n                xSwitchRequired = pdTRUE;\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n        #endif /* configUSE_PREEMPTION */\n    }\n    else\n    {\n        ++xPendedTicks;\n\n        /* The tick hook gets called at regular intervals, even if the\n         * scheduler is locked. */\n        #if ( configUSE_TICK_HOOK == 1 )\n        {\n            vApplicationTickHook();\n        }\n        #endif\n    }\n\n    return xSwitchRequired;\n}\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_APPLICATION_TASK_TAG == 1 )\n\n    void vTaskSetApplicationTaskTag( TaskHandle_t xTask,\n                                     TaskHookFunction_t pxHookFunction )\n    {\n        TCB_t * xTCB;\n\n        /* If xTask is NULL then it is the task hook of the calling task that is\n         * getting set. */\n        if( xTask == NULL )\n        {\n            xTCB = ( TCB_t * ) pxCurrentTCB;\n        }\n        else\n        {\n            xTCB = xTask;\n        }\n\n        /* Save the hook function in the TCB.  A critical section is required as\n         * the value can be accessed from an interrupt. */\n        taskENTER_CRITICAL();\n        {\n            xTCB->pxTaskTag = pxHookFunction;\n        }\n        taskEXIT_CRITICAL();\n    }\n\n#endif /* configUSE_APPLICATION_TASK_TAG */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_APPLICATION_TASK_TAG == 1 )\n\n    TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask )\n    {\n        TCB_t * pxTCB;\n        TaskHookFunction_t xReturn;\n\n        /* If xTask is NULL then set the calling task's hook. */\n        pxTCB = prvGetTCBFromHandle( xTask );\n\n        /* Save the hook function in the TCB.  A critical section is required as\n         * the value can be accessed from an interrupt. */\n        taskENTER_CRITICAL();\n        {\n            xReturn = pxTCB->pxTaskTag;\n        }\n        taskEXIT_CRITICAL();\n\n        return xReturn;\n    }\n\n#endif /* configUSE_APPLICATION_TASK_TAG */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_APPLICATION_TASK_TAG == 1 )\n\n    TaskHookFunction_t xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask )\n    {\n        TCB_t * pxTCB;\n        TaskHookFunction_t xReturn;\n        UBaseType_t uxSavedInterruptStatus;\n\n        /* If xTask is NULL then set the calling task's hook. */\n        pxTCB = prvGetTCBFromHandle( xTask );\n\n        /* Save the hook function in the TCB.  A critical section is required as\n         * the value can be accessed from an interrupt. */\n        uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();\n        {\n            xReturn = pxTCB->pxTaskTag;\n        }\n        portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\n\n        return xReturn;\n    }\n\n#endif /* configUSE_APPLICATION_TASK_TAG */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_APPLICATION_TASK_TAG == 1 )\n\n    BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask,\n                                             void * pvParameter )\n    {\n        TCB_t * xTCB;\n        BaseType_t xReturn;\n\n        /* If xTask is NULL then we are calling our own task hook. */\n        if( xTask == NULL )\n        {\n            xTCB = pxCurrentTCB;\n        }\n        else\n        {\n            xTCB = xTask;\n        }\n\n        if( xTCB->pxTaskTag != NULL )\n        {\n            xReturn = xTCB->pxTaskTag( pvParameter );\n        }\n        else\n        {\n            xReturn = pdFAIL;\n        }\n\n        return xReturn;\n    }\n\n#endif /* configUSE_APPLICATION_TASK_TAG */\n/*-----------------------------------------------------------*/\n\nvoid vTaskSwitchContext( void )\n{\n    if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE )\n    {\n        /* The scheduler is currently suspended - do not allow a context\n         * switch. */\n        xYieldPending = pdTRUE;\n    }\n    else\n    {\n        xYieldPending = pdFALSE;\n        traceTASK_SWITCHED_OUT();\n\n        #if ( configGENERATE_RUN_TIME_STATS == 1 )\n        {\n            #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE\n                portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalRunTime );\n            #else\n                ulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE();\n            #endif\n\n            /* Add the amount of time the task has been running to the\n             * accumulated time so far.  The time the task started running was\n             * stored in ulTaskSwitchedInTime.  Note that there is no overflow\n             * protection here so count values are only valid until the timer\n             * overflows.  The guard against negative values is to protect\n             * against suspect run time stat counter implementations - which\n             * are provided by the application, not the kernel. */\n            if( ulTotalRunTime > ulTaskSwitchedInTime )\n            {\n                pxCurrentTCB->ulRunTimeCounter += ( ulTotalRunTime - ulTaskSwitchedInTime );\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n\n            ulTaskSwitchedInTime = ulTotalRunTime;\n        }\n        #endif /* configGENERATE_RUN_TIME_STATS */\n\n        /* Check for stack overflow, if configured. */\n        taskCHECK_FOR_STACK_OVERFLOW();\n\n        /* Before the currently running task is switched out, save its errno. */\n        #if ( configUSE_POSIX_ERRNO == 1 )\n        {\n            pxCurrentTCB->iTaskErrno = FreeRTOS_errno;\n        }\n        #endif\n\n        /* Select a new task to run using either the generic C or port\n         * optimised asm code. */\n        taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */\n        traceTASK_SWITCHED_IN();\n\n        /* After the new task is switched in, update the global errno. */\n        #if ( configUSE_POSIX_ERRNO == 1 )\n        {\n            FreeRTOS_errno = pxCurrentTCB->iTaskErrno;\n        }\n        #endif\n\n        #if ( ( configUSE_NEWLIB_REENTRANT == 1 ) || ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 ) )\n        {\n            /* Switch C-Runtime's TLS Block to point to the TLS\n             * Block specific to this task. */\n            configSET_TLS_BLOCK( pxCurrentTCB->xTLSBlock );\n        }\n        #endif\n    }\n}\n/*-----------------------------------------------------------*/\n\nvoid vTaskPlaceOnEventList( List_t * const pxEventList,\n                            const TickType_t xTicksToWait )\n{\n    configASSERT( pxEventList );\n\n    /* THIS FUNCTION MUST BE CALLED WITH EITHER INTERRUPTS DISABLED OR THE\n     * SCHEDULER SUSPENDED AND THE QUEUE BEING ACCESSED LOCKED. */\n\n    /* Place the event list item of the TCB in the appropriate event list.\n     * This is placed in the list in priority order so the highest priority task\n     * is the first to be woken by the event.\n     *\n     * Note: Lists are sorted in ascending order by ListItem_t.xItemValue.\n     * Normally, the xItemValue of a TCB's ListItem_t members is:\n     *      xItemValue = ( configMAX_PRIORITIES - uxPriority )\n     * Therefore, the event list is sorted in descending priority order.\n     *\n     * The queue that contains the event list is locked, preventing\n     * simultaneous access from interrupts. */\n    vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) );\n\n    prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );\n}\n/*-----------------------------------------------------------*/\n\nvoid vTaskPlaceOnUnorderedEventList( List_t * pxEventList,\n                                     const TickType_t xItemValue,\n                                     const TickType_t xTicksToWait )\n{\n    configASSERT( pxEventList );\n\n    /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED.  It is used by\n     * the event groups implementation. */\n    configASSERT( uxSchedulerSuspended != 0 );\n\n    /* Store the item value in the event list item.  It is safe to access the\n     * event list item here as interrupts won't access the event list item of a\n     * task that is not in the Blocked state. */\n    listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE );\n\n    /* Place the event list item of the TCB at the end of the appropriate event\n     * list.  It is safe to access the event list here because it is part of an\n     * event group implementation - and interrupts don't access event groups\n     * directly (instead they access them indirectly by pending function calls to\n     * the task level). */\n    listINSERT_END( pxEventList, &( pxCurrentTCB->xEventListItem ) );\n\n    prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );\n}\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TIMERS == 1 )\n\n    void vTaskPlaceOnEventListRestricted( List_t * const pxEventList,\n                                          TickType_t xTicksToWait,\n                                          const BaseType_t xWaitIndefinitely )\n    {\n        configASSERT( pxEventList );\n\n        /* This function should not be called by application code hence the\n         * 'Restricted' in its name.  It is not part of the public API.  It is\n         * designed for use by kernel code, and has special calling requirements -\n         * it should be called with the scheduler suspended. */\n\n\n        /* Place the event list item of the TCB in the appropriate event list.\n         * In this case it is assume that this is the only task that is going to\n         * be waiting on this event list, so the faster vListInsertEnd() function\n         * can be used in place of vListInsert. */\n        listINSERT_END( pxEventList, &( pxCurrentTCB->xEventListItem ) );\n\n        /* If the task should block indefinitely then set the block time to a\n         * value that will be recognised as an indefinite delay inside the\n         * prvAddCurrentTaskToDelayedList() function. */\n        if( xWaitIndefinitely != pdFALSE )\n        {\n            xTicksToWait = portMAX_DELAY;\n        }\n\n        traceTASK_DELAY_UNTIL( ( xTickCount + xTicksToWait ) );\n        prvAddCurrentTaskToDelayedList( xTicksToWait, xWaitIndefinitely );\n    }\n\n#endif /* configUSE_TIMERS */\n/*-----------------------------------------------------------*/\n\nBaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList )\n{\n    TCB_t * pxUnblockedTCB;\n    BaseType_t xReturn;\n\n    /* THIS FUNCTION MUST BE CALLED FROM A CRITICAL SECTION.  It can also be\n     * called from a critical section within an ISR. */\n\n    /* The event list is sorted in priority order, so the first in the list can\n     * be removed as it is known to be the highest priority.  Remove the TCB from\n     * the delayed list, and add it to the ready list.\n     *\n     * If an event is for a queue that is locked then this function will never\n     * get called - the lock count on the queue will get modified instead.  This\n     * means exclusive access to the event list is guaranteed here.\n     *\n     * This function assumes that a check has already been made to ensure that\n     * pxEventList is not empty. */\n    pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */\n    configASSERT( pxUnblockedTCB );\n    listREMOVE_ITEM( &( pxUnblockedTCB->xEventListItem ) );\n\n    if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )\n    {\n        listREMOVE_ITEM( &( pxUnblockedTCB->xStateListItem ) );\n        prvAddTaskToReadyList( pxUnblockedTCB );\n\n        #if ( configUSE_TICKLESS_IDLE != 0 )\n        {\n            /* If a task is blocked on a kernel object then xNextTaskUnblockTime\n             * might be set to the blocked task's time out time.  If the task is\n             * unblocked for a reason other than a timeout xNextTaskUnblockTime is\n             * normally left unchanged, because it is automatically reset to a new\n             * value when the tick count equals xNextTaskUnblockTime.  However if\n             * tickless idling is used it might be more important to enter sleep mode\n             * at the earliest possible time - so reset xNextTaskUnblockTime here to\n             * ensure it is updated at the earliest possible time. */\n            prvResetNextTaskUnblockTime();\n        }\n        #endif\n    }\n    else\n    {\n        /* The delayed and ready lists cannot be accessed, so hold this task\n         * pending until the scheduler is resumed. */\n        listINSERT_END( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) );\n    }\n\n    if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )\n    {\n        /* Return true if the task removed from the event list has a higher\n         * priority than the calling task.  This allows the calling task to know if\n         * it should force a context switch now. */\n        xReturn = pdTRUE;\n\n        /* Mark that a yield is pending in case the user is not using the\n         * \"xHigherPriorityTaskWoken\" parameter to an ISR safe FreeRTOS function. */\n        xYieldPending = pdTRUE;\n    }\n    else\n    {\n        xReturn = pdFALSE;\n    }\n\n    return xReturn;\n}\n/*-----------------------------------------------------------*/\n\nvoid vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem,\n                                        const TickType_t xItemValue )\n{\n    TCB_t * pxUnblockedTCB;\n\n    /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED.  It is used by\n     * the event flags implementation. */\n    configASSERT( uxSchedulerSuspended != pdFALSE );\n\n    /* Store the new item value in the event list. */\n    listSET_LIST_ITEM_VALUE( pxEventListItem, xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE );\n\n    /* Remove the event list form the event flag.  Interrupts do not access\n     * event flags. */\n    pxUnblockedTCB = listGET_LIST_ITEM_OWNER( pxEventListItem ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */\n    configASSERT( pxUnblockedTCB );\n    listREMOVE_ITEM( pxEventListItem );\n\n    #if ( configUSE_TICKLESS_IDLE != 0 )\n    {\n        /* If a task is blocked on a kernel object then xNextTaskUnblockTime\n         * might be set to the blocked task's time out time.  If the task is\n         * unblocked for a reason other than a timeout xNextTaskUnblockTime is\n         * normally left unchanged, because it is automatically reset to a new\n         * value when the tick count equals xNextTaskUnblockTime.  However if\n         * tickless idling is used it might be more important to enter sleep mode\n         * at the earliest possible time - so reset xNextTaskUnblockTime here to\n         * ensure it is updated at the earliest possible time. */\n        prvResetNextTaskUnblockTime();\n    }\n    #endif\n\n    /* Remove the task from the delayed list and add it to the ready list.  The\n     * scheduler is suspended so interrupts will not be accessing the ready\n     * lists. */\n    listREMOVE_ITEM( &( pxUnblockedTCB->xStateListItem ) );\n    prvAddTaskToReadyList( pxUnblockedTCB );\n\n    if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )\n    {\n        /* The unblocked task has a priority above that of the calling task, so\n         * a context switch is required.  This function is called with the\n         * scheduler suspended so xYieldPending is set so the context switch\n         * occurs immediately that the scheduler is resumed (unsuspended). */\n        xYieldPending = pdTRUE;\n    }\n}\n/*-----------------------------------------------------------*/\n\nvoid vTaskSetTimeOutState( TimeOut_t * const pxTimeOut )\n{\n    configASSERT( pxTimeOut );\n    taskENTER_CRITICAL();\n    {\n        pxTimeOut->xOverflowCount = xNumOfOverflows;\n        pxTimeOut->xTimeOnEntering = xTickCount;\n    }\n    taskEXIT_CRITICAL();\n}\n/*-----------------------------------------------------------*/\n\nvoid vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut )\n{\n    /* For internal use only as it does not use a critical section. */\n    pxTimeOut->xOverflowCount = xNumOfOverflows;\n    pxTimeOut->xTimeOnEntering = xTickCount;\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,\n                                 TickType_t * const pxTicksToWait )\n{\n    BaseType_t xReturn;\n\n    configASSERT( pxTimeOut );\n    configASSERT( pxTicksToWait );\n\n    taskENTER_CRITICAL();\n    {\n        /* Minor optimisation.  The tick count cannot change in this block. */\n        const TickType_t xConstTickCount = xTickCount;\n        const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering;\n\n        #if ( INCLUDE_xTaskAbortDelay == 1 )\n            if( pxCurrentTCB->ucDelayAborted != ( uint8_t ) pdFALSE )\n            {\n                /* The delay was aborted, which is not the same as a time out,\n                 * but has the same result. */\n                pxCurrentTCB->ucDelayAborted = pdFALSE;\n                xReturn = pdTRUE;\n            }\n            else\n        #endif\n\n        #if ( INCLUDE_vTaskSuspend == 1 )\n            if( *pxTicksToWait == portMAX_DELAY )\n            {\n                /* If INCLUDE_vTaskSuspend is set to 1 and the block time\n                 * specified is the maximum block time then the task should block\n                 * indefinitely, and therefore never time out. */\n                xReturn = pdFALSE;\n            }\n            else\n        #endif\n\n        if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */\n        {\n            /* The tick count is greater than the time at which\n             * vTaskSetTimeout() was called, but has also overflowed since\n             * vTaskSetTimeOut() was called.  It must have wrapped all the way\n             * around and gone past again. This passed since vTaskSetTimeout()\n             * was called. */\n            xReturn = pdTRUE;\n            *pxTicksToWait = ( TickType_t ) 0;\n        }\n        else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */\n        {\n            /* Not a genuine timeout. Adjust parameters for time remaining. */\n            *pxTicksToWait -= xElapsedTime;\n            vTaskInternalSetTimeOutState( pxTimeOut );\n            xReturn = pdFALSE;\n        }\n        else\n        {\n            *pxTicksToWait = ( TickType_t ) 0;\n            xReturn = pdTRUE;\n        }\n    }\n    taskEXIT_CRITICAL();\n\n    return xReturn;\n}\n/*-----------------------------------------------------------*/\n\nvoid vTaskMissedYield( void )\n{\n    xYieldPending = pdTRUE;\n}\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TRACE_FACILITY == 1 )\n\n    UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask )\n    {\n        UBaseType_t uxReturn;\n        TCB_t const * pxTCB;\n\n        if( xTask != NULL )\n        {\n            pxTCB = xTask;\n            uxReturn = pxTCB->uxTaskNumber;\n        }\n        else\n        {\n            uxReturn = 0U;\n        }\n\n        return uxReturn;\n    }\n\n#endif /* configUSE_TRACE_FACILITY */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TRACE_FACILITY == 1 )\n\n    void vTaskSetTaskNumber( TaskHandle_t xTask,\n                             const UBaseType_t uxHandle )\n    {\n        TCB_t * pxTCB;\n\n        if( xTask != NULL )\n        {\n            pxTCB = xTask;\n            pxTCB->uxTaskNumber = uxHandle;\n        }\n    }\n\n#endif /* configUSE_TRACE_FACILITY */\n\n/*\n * -----------------------------------------------------------\n * The Idle task.\n * ----------------------------------------------------------\n *\n * The portTASK_FUNCTION() macro is used to allow port/compiler specific\n * language extensions.  The equivalent prototype for this function is:\n *\n * void prvIdleTask( void *pvParameters );\n *\n */\nstatic portTASK_FUNCTION( prvIdleTask, pvParameters )\n{\n    /* Stop warnings. */\n    ( void ) pvParameters;\n\n    /** THIS IS THE RTOS IDLE TASK - WHICH IS CREATED AUTOMATICALLY WHEN THE\n     * SCHEDULER IS STARTED. **/\n\n    /* In case a task that has a secure context deletes itself, in which case\n     * the idle task is responsible for deleting the task's secure context, if\n     * any. */\n    portALLOCATE_SECURE_CONTEXT( configMINIMAL_SECURE_STACK_SIZE );\n\n    for( ; ; )\n    {\n        /* See if any tasks have deleted themselves - if so then the idle task\n         * is responsible for freeing the deleted task's TCB and stack. */\n        prvCheckTasksWaitingTermination();\n\n        #if ( configUSE_PREEMPTION == 0 )\n        {\n            /* If we are not using preemption we keep forcing a task switch to\n             * see if any other task has become available.  If we are using\n             * preemption we don't need to do this as any task becoming available\n             * will automatically get the processor anyway. */\n            taskYIELD();\n        }\n        #endif /* configUSE_PREEMPTION */\n\n        #if ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) )\n        {\n            /* When using preemption tasks of equal priority will be\n             * timesliced.  If a task that is sharing the idle priority is ready\n             * to run then the idle task should yield before the end of the\n             * timeslice.\n             *\n             * A critical region is not required here as we are just reading from\n             * the list, and an occasional incorrect value will not matter.  If\n             * the ready list at the idle priority contains more than one task\n             * then a task other than the idle task is ready to execute. */\n            if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 )\n            {\n                taskYIELD();\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n        #endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) ) */\n\n        #if ( configUSE_IDLE_HOOK == 1 )\n        {\n            extern void vApplicationIdleHook( void );\n\n            /* Call the user defined function from within the idle task.  This\n             * allows the application designer to add background functionality\n             * without the overhead of a separate task.\n             * NOTE: vApplicationIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES,\n             * CALL A FUNCTION THAT MIGHT BLOCK. */\n            vApplicationIdleHook();\n        }\n        #endif /* configUSE_IDLE_HOOK */\n\n        /* This conditional compilation should use inequality to 0, not equality\n         * to 1.  This is to ensure portSUPPRESS_TICKS_AND_SLEEP() is called when\n         * user defined low power mode  implementations require\n         * configUSE_TICKLESS_IDLE to be set to a value other than 1. */\n        #if ( configUSE_TICKLESS_IDLE != 0 )\n        {\n            TickType_t xExpectedIdleTime;\n\n            /* It is not desirable to suspend then resume the scheduler on\n             * each iteration of the idle task.  Therefore, a preliminary\n             * test of the expected idle time is performed without the\n             * scheduler suspended.  The result here is not necessarily\n             * valid. */\n            xExpectedIdleTime = prvGetExpectedIdleTime();\n\n            if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP )\n            {\n                vTaskSuspendAll();\n                {\n                    /* Now the scheduler is suspended, the expected idle\n                     * time can be sampled again, and this time its value can\n                     * be used. */\n                    configASSERT( xNextTaskUnblockTime >= xTickCount );\n                    xExpectedIdleTime = prvGetExpectedIdleTime();\n\n                    /* Define the following macro to set xExpectedIdleTime to 0\n                     * if the application does not want\n                     * portSUPPRESS_TICKS_AND_SLEEP() to be called. */\n                    configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( xExpectedIdleTime );\n\n                    if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP )\n                    {\n                        traceLOW_POWER_IDLE_BEGIN();\n                        portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime );\n                        traceLOW_POWER_IDLE_END();\n                    }\n                    else\n                    {\n                        mtCOVERAGE_TEST_MARKER();\n                    }\n                }\n                ( void ) xTaskResumeAll();\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n        #endif /* configUSE_TICKLESS_IDLE */\n    }\n}\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TICKLESS_IDLE != 0 )\n\n    eSleepModeStatus eTaskConfirmSleepModeStatus( void )\n    {\n        #if ( INCLUDE_vTaskSuspend == 1 )\n            /* The idle task exists in addition to the application tasks. */\n            const UBaseType_t uxNonApplicationTasks = 1;\n        #endif /* INCLUDE_vTaskSuspend */\n\n        eSleepModeStatus eReturn = eStandardSleep;\n\n        /* This function must be called from a critical section. */\n\n        if( listCURRENT_LIST_LENGTH( &xPendingReadyList ) != 0 )\n        {\n            /* A task was made ready while the scheduler was suspended. */\n            eReturn = eAbortSleep;\n        }\n        else if( xYieldPending != pdFALSE )\n        {\n            /* A yield was pended while the scheduler was suspended. */\n            eReturn = eAbortSleep;\n        }\n        else if( xPendedTicks != 0 )\n        {\n            /* A tick interrupt has already occurred but was held pending\n             * because the scheduler is suspended. */\n            eReturn = eAbortSleep;\n        }\n\n        #if ( INCLUDE_vTaskSuspend == 1 )\n            else if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == ( uxCurrentNumberOfTasks - uxNonApplicationTasks ) )\n            {\n                /* If all the tasks are in the suspended list (which might mean they\n                 * have an infinite block time rather than actually being suspended)\n                 * then it is safe to turn all clocks off and just wait for external\n                 * interrupts. */\n                eReturn = eNoTasksWaitingTimeout;\n            }\n        #endif /* INCLUDE_vTaskSuspend */\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n\n        return eReturn;\n    }\n\n#endif /* configUSE_TICKLESS_IDLE */\n/*-----------------------------------------------------------*/\n\n#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )\n\n    void vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,\n                                            BaseType_t xIndex,\n                                            void * pvValue )\n    {\n        TCB_t * pxTCB;\n\n        if( ( xIndex >= 0 ) &&\n            ( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS ) )\n        {\n            pxTCB = prvGetTCBFromHandle( xTaskToSet );\n            configASSERT( pxTCB != NULL );\n            pxTCB->pvThreadLocalStoragePointers[ xIndex ] = pvValue;\n        }\n    }\n\n#endif /* configNUM_THREAD_LOCAL_STORAGE_POINTERS */\n/*-----------------------------------------------------------*/\n\n#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )\n\n    void * pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,\n                                               BaseType_t xIndex )\n    {\n        void * pvReturn = NULL;\n        TCB_t * pxTCB;\n\n        if( ( xIndex >= 0 ) &&\n            ( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS ) )\n        {\n            pxTCB = prvGetTCBFromHandle( xTaskToQuery );\n            pvReturn = pxTCB->pvThreadLocalStoragePointers[ xIndex ];\n        }\n        else\n        {\n            pvReturn = NULL;\n        }\n\n        return pvReturn;\n    }\n\n#endif /* configNUM_THREAD_LOCAL_STORAGE_POINTERS */\n/*-----------------------------------------------------------*/\n\n#if ( portUSING_MPU_WRAPPERS == 1 )\n\n    void vTaskAllocateMPURegions( TaskHandle_t xTaskToModify,\n                                  const MemoryRegion_t * const xRegions )\n    {\n        TCB_t * pxTCB;\n\n        /* If null is passed in here then we are modifying the MPU settings of\n         * the calling task. */\n        pxTCB = prvGetTCBFromHandle( xTaskToModify );\n\n        vPortStoreTaskMPUSettings( &( pxTCB->xMPUSettings ), xRegions, NULL, 0 );\n    }\n\n#endif /* portUSING_MPU_WRAPPERS */\n/*-----------------------------------------------------------*/\n\nstatic void prvInitialiseTaskLists( void )\n{\n    UBaseType_t uxPriority;\n\n    for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )\n    {\n        vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) );\n    }\n\n    vListInitialise( &xDelayedTaskList1 );\n    vListInitialise( &xDelayedTaskList2 );\n    vListInitialise( &xPendingReadyList );\n\n    #if ( INCLUDE_vTaskDelete == 1 )\n    {\n        vListInitialise( &xTasksWaitingTermination );\n    }\n    #endif /* INCLUDE_vTaskDelete */\n\n    #if ( INCLUDE_vTaskSuspend == 1 )\n    {\n        vListInitialise( &xSuspendedTaskList );\n    }\n    #endif /* INCLUDE_vTaskSuspend */\n\n    /* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList\n     * using list2. */\n    pxDelayedTaskList = &xDelayedTaskList1;\n    pxOverflowDelayedTaskList = &xDelayedTaskList2;\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvCheckTasksWaitingTermination( void )\n{\n    /** THIS FUNCTION IS CALLED FROM THE RTOS IDLE TASK **/\n\n    #if ( INCLUDE_vTaskDelete == 1 )\n    {\n        TCB_t * pxTCB;\n\n        /* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL()\n         * being called too often in the idle task. */\n        while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )\n        {\n            taskENTER_CRITICAL();\n            {\n                pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */\n                ( void ) uxListRemove( &( pxTCB->xStateListItem ) );\n                --uxCurrentNumberOfTasks;\n                --uxDeletedTasksWaitingCleanUp;\n            }\n            taskEXIT_CRITICAL();\n\n            prvDeleteTCB( pxTCB );\n        }\n    }\n    #endif /* INCLUDE_vTaskDelete */\n}\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TRACE_FACILITY == 1 )\n\n    void vTaskGetInfo( TaskHandle_t xTask,\n                       TaskStatus_t * pxTaskStatus,\n                       BaseType_t xGetFreeStackSpace,\n                       eTaskState eState )\n    {\n        TCB_t * pxTCB;\n\n        /* xTask is NULL then get the state of the calling task. */\n        pxTCB = prvGetTCBFromHandle( xTask );\n\n        pxTaskStatus->xHandle = ( TaskHandle_t ) pxTCB;\n        pxTaskStatus->pcTaskName = ( const char * ) &( pxTCB->pcTaskName[ 0 ] );\n        pxTaskStatus->uxCurrentPriority = pxTCB->uxPriority;\n        pxTaskStatus->pxStackBase = pxTCB->pxStack;\n        #if ( ( portSTACK_GROWTH > 0 ) && ( configRECORD_STACK_HIGH_ADDRESS == 1 ) )\n            pxTaskStatus->pxTopOfStack = pxTCB->pxTopOfStack;\n            pxTaskStatus->pxEndOfStack = pxTCB->pxEndOfStack;\n        #endif\n        pxTaskStatus->xTaskNumber = pxTCB->uxTCBNumber;\n\n        #if ( configUSE_MUTEXES == 1 )\n        {\n            pxTaskStatus->uxBasePriority = pxTCB->uxBasePriority;\n        }\n        #else\n        {\n            pxTaskStatus->uxBasePriority = 0;\n        }\n        #endif\n\n        #if ( configGENERATE_RUN_TIME_STATS == 1 )\n        {\n            pxTaskStatus->ulRunTimeCounter = pxTCB->ulRunTimeCounter;\n        }\n        #else\n        {\n            pxTaskStatus->ulRunTimeCounter = ( configRUN_TIME_COUNTER_TYPE ) 0;\n        }\n        #endif\n\n        /* Obtaining the task state is a little fiddly, so is only done if the\n         * value of eState passed into this function is eInvalid - otherwise the\n         * state is just set to whatever is passed in. */\n        if( eState != eInvalid )\n        {\n            if( pxTCB == pxCurrentTCB )\n            {\n                pxTaskStatus->eCurrentState = eRunning;\n            }\n            else\n            {\n                pxTaskStatus->eCurrentState = eState;\n\n                #if ( INCLUDE_vTaskSuspend == 1 )\n                {\n                    /* If the task is in the suspended list then there is a\n                     *  chance it is actually just blocked indefinitely - so really\n                     *  it should be reported as being in the Blocked state. */\n                    if( eState == eSuspended )\n                    {\n                        vTaskSuspendAll();\n                        {\n                            if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )\n                            {\n                                pxTaskStatus->eCurrentState = eBlocked;\n                            }\n                        }\n                        ( void ) xTaskResumeAll();\n                    }\n                }\n                #endif /* INCLUDE_vTaskSuspend */\n            }\n        }\n        else\n        {\n            pxTaskStatus->eCurrentState = eTaskGetState( pxTCB );\n        }\n\n        /* Obtaining the stack space takes some time, so the xGetFreeStackSpace\n         * parameter is provided to allow it to be skipped. */\n        if( xGetFreeStackSpace != pdFALSE )\n        {\n            #if ( portSTACK_GROWTH > 0 )\n            {\n                pxTaskStatus->usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxTCB->pxEndOfStack );\n            }\n            #else\n            {\n                pxTaskStatus->usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxTCB->pxStack );\n            }\n            #endif\n        }\n        else\n        {\n            pxTaskStatus->usStackHighWaterMark = 0;\n        }\n    }\n\n#endif /* configUSE_TRACE_FACILITY */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TRACE_FACILITY == 1 )\n\n    static UBaseType_t prvListTasksWithinSingleList( TaskStatus_t * pxTaskStatusArray,\n                                                     List_t * pxList,\n                                                     eTaskState eState )\n    {\n        configLIST_VOLATILE TCB_t * pxNextTCB;\n        configLIST_VOLATILE TCB_t * pxFirstTCB;\n        UBaseType_t uxTask = 0;\n\n        if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )\n        {\n            listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */\n\n            /* Populate an TaskStatus_t structure within the\n             * pxTaskStatusArray array for each task that is referenced from\n             * pxList.  See the definition of TaskStatus_t in task.h for the\n             * meaning of each TaskStatus_t structure member. */\n            do\n            {\n                listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */\n                vTaskGetInfo( ( TaskHandle_t ) pxNextTCB, &( pxTaskStatusArray[ uxTask ] ), pdTRUE, eState );\n                uxTask++;\n            } while( pxNextTCB != pxFirstTCB );\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n\n        return uxTask;\n    }\n\n#endif /* configUSE_TRACE_FACILITY */\n/*-----------------------------------------------------------*/\n\n#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) )\n\n    static configSTACK_DEPTH_TYPE prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte )\n    {\n        uint32_t ulCount = 0U;\n\n        while( *pucStackByte == ( uint8_t ) tskSTACK_FILL_BYTE )\n        {\n            pucStackByte -= portSTACK_GROWTH;\n            ulCount++;\n        }\n\n        ulCount /= ( uint32_t ) sizeof( StackType_t ); /*lint !e961 Casting is not redundant on smaller architectures. */\n\n        return ( configSTACK_DEPTH_TYPE ) ulCount;\n    }\n\n#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) ) */\n/*-----------------------------------------------------------*/\n\n#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )\n\n/* uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the\n * same except for their return type.  Using configSTACK_DEPTH_TYPE allows the\n * user to determine the return type.  It gets around the problem of the value\n * overflowing on 8-bit types without breaking backward compatibility for\n * applications that expect an 8-bit return type. */\n    configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask )\n    {\n        TCB_t * pxTCB;\n        uint8_t * pucEndOfStack;\n        configSTACK_DEPTH_TYPE uxReturn;\n\n        /* uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are\n         * the same except for their return type.  Using configSTACK_DEPTH_TYPE\n         * allows the user to determine the return type.  It gets around the\n         * problem of the value overflowing on 8-bit types without breaking\n         * backward compatibility for applications that expect an 8-bit return\n         * type. */\n\n        pxTCB = prvGetTCBFromHandle( xTask );\n\n        #if portSTACK_GROWTH < 0\n        {\n            pucEndOfStack = ( uint8_t * ) pxTCB->pxStack;\n        }\n        #else\n        {\n            pucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack;\n        }\n        #endif\n\n        uxReturn = prvTaskCheckFreeStackSpace( pucEndOfStack );\n\n        return uxReturn;\n    }\n\n#endif /* INCLUDE_uxTaskGetStackHighWaterMark2 */\n/*-----------------------------------------------------------*/\n\n#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )\n\n    UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask )\n    {\n        TCB_t * pxTCB;\n        uint8_t * pucEndOfStack;\n        UBaseType_t uxReturn;\n\n        pxTCB = prvGetTCBFromHandle( xTask );\n\n        #if portSTACK_GROWTH < 0\n        {\n            pucEndOfStack = ( uint8_t * ) pxTCB->pxStack;\n        }\n        #else\n        {\n            pucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack;\n        }\n        #endif\n\n        uxReturn = ( UBaseType_t ) prvTaskCheckFreeStackSpace( pucEndOfStack );\n\n        return uxReturn;\n    }\n\n#endif /* INCLUDE_uxTaskGetStackHighWaterMark */\n/*-----------------------------------------------------------*/\n\n#if ( INCLUDE_vTaskDelete == 1 )\n\n    static void prvDeleteTCB( TCB_t * pxTCB )\n    {\n        /* This call is required specifically for the TriCore port.  It must be\n         * above the vPortFree() calls.  The call is also used by ports/demos that\n         * want to allocate and clean RAM statically. */\n        portCLEAN_UP_TCB( pxTCB );\n\n        #if ( ( configUSE_NEWLIB_REENTRANT == 1 ) || ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 ) )\n        {\n            /* Free up the memory allocated for the task's TLS Block. */\n            configDEINIT_TLS_BLOCK( pxCurrentTCB->xTLSBlock );\n        }\n        #endif\n\n        #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) && ( portUSING_MPU_WRAPPERS == 0 ) )\n        {\n            /* The task can only have been allocated dynamically - free both\n             * the stack and TCB. */\n            vPortFreeStack( pxTCB->pxStack );\n            vPortFree( pxTCB );\n        }\n        #elif ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */\n        {\n            /* The task could have been allocated statically or dynamically, so\n             * check what was statically allocated before trying to free the\n             * memory. */\n            if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB )\n            {\n                /* Both the stack and TCB were allocated dynamically, so both\n                 * must be freed. */\n                vPortFreeStack( pxTCB->pxStack );\n                vPortFree( pxTCB );\n            }\n            else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY )\n            {\n                /* Only the stack was statically allocated, so the TCB is the\n                 * only memory that must be freed. */\n                vPortFree( pxTCB );\n            }\n            else\n            {\n                /* Neither the stack nor the TCB were allocated dynamically, so\n                 * nothing needs to be freed. */\n                configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB );\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n        #endif /* configSUPPORT_DYNAMIC_ALLOCATION */\n    }\n\n#endif /* INCLUDE_vTaskDelete */\n/*-----------------------------------------------------------*/\n\nstatic void prvResetNextTaskUnblockTime( void )\n{\n    if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )\n    {\n        /* The new current delayed list is empty.  Set xNextTaskUnblockTime to\n         * the maximum possible value so it is  extremely unlikely that the\n         * if( xTickCount >= xNextTaskUnblockTime ) test will pass until\n         * there is an item in the delayed list. */\n        xNextTaskUnblockTime = portMAX_DELAY;\n    }\n    else\n    {\n        /* The new current delayed list is not empty, get the value of\n         * the item at the head of the delayed list.  This is the time at\n         * which the task at the head of the delayed list should be removed\n         * from the Blocked state. */\n        xNextTaskUnblockTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxDelayedTaskList );\n    }\n}\n/*-----------------------------------------------------------*/\n\n#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )\n\n    TaskHandle_t xTaskGetCurrentTaskHandle( void )\n    {\n        TaskHandle_t xReturn;\n\n        /* A critical section is not required as this is not called from\n         * an interrupt and the current TCB will always be the same for any\n         * individual execution thread. */\n        xReturn = pxCurrentTCB;\n\n        return xReturn;\n    }\n\n#endif /* ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */\n/*-----------------------------------------------------------*/\n\n#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )\n\n    BaseType_t xTaskGetSchedulerState( void )\n    {\n        BaseType_t xReturn;\n\n        if( xSchedulerRunning == pdFALSE )\n        {\n            xReturn = taskSCHEDULER_NOT_STARTED;\n        }\n        else\n        {\n            if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )\n            {\n                xReturn = taskSCHEDULER_RUNNING;\n            }\n            else\n            {\n                xReturn = taskSCHEDULER_SUSPENDED;\n            }\n        }\n\n        return xReturn;\n    }\n\n#endif /* ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_MUTEXES == 1 )\n\n    BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder )\n    {\n        TCB_t * const pxMutexHolderTCB = pxMutexHolder;\n        BaseType_t xReturn = pdFALSE;\n\n        /* If the mutex was given back by an interrupt while the queue was\n         * locked then the mutex holder might now be NULL.  _RB_ Is this still\n         * needed as interrupts can no longer use mutexes? */\n        if( pxMutexHolder != NULL )\n        {\n            /* If the holder of the mutex has a priority below the priority of\n             * the task attempting to obtain the mutex then it will temporarily\n             * inherit the priority of the task attempting to obtain the mutex. */\n            if( pxMutexHolderTCB->uxPriority < pxCurrentTCB->uxPriority )\n            {\n                /* Adjust the mutex holder state to account for its new\n                 * priority.  Only reset the event list item value if the value is\n                 * not being used for anything else. */\n                if( ( listGET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )\n                {\n                    listSET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\n                }\n                else\n                {\n                    mtCOVERAGE_TEST_MARKER();\n                }\n\n                /* If the task being modified is in the ready state it will need\n                 * to be moved into a new list. */\n                if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxMutexHolderTCB->uxPriority ] ), &( pxMutexHolderTCB->xStateListItem ) ) != pdFALSE )\n                {\n                    if( uxListRemove( &( pxMutexHolderTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )\n                    {\n                        /* It is known that the task is in its ready list so\n                         * there is no need to check again and the port level\n                         * reset macro can be called directly. */\n                        portRESET_READY_PRIORITY( pxMutexHolderTCB->uxPriority, uxTopReadyPriority );\n                    }\n                    else\n                    {\n                        mtCOVERAGE_TEST_MARKER();\n                    }\n\n                    /* Inherit the priority before being moved into the new list. */\n                    pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;\n                    prvAddTaskToReadyList( pxMutexHolderTCB );\n                }\n                else\n                {\n                    /* Just inherit the priority. */\n                    pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;\n                }\n\n                traceTASK_PRIORITY_INHERIT( pxMutexHolderTCB, pxCurrentTCB->uxPriority );\n\n                /* Inheritance occurred. */\n                xReturn = pdTRUE;\n            }\n            else\n            {\n                if( pxMutexHolderTCB->uxBasePriority < pxCurrentTCB->uxPriority )\n                {\n                    /* The base priority of the mutex holder is lower than the\n                     * priority of the task attempting to take the mutex, but the\n                     * current priority of the mutex holder is not lower than the\n                     * priority of the task attempting to take the mutex.\n                     * Therefore the mutex holder must have already inherited a\n                     * priority, but inheritance would have occurred if that had\n                     * not been the case. */\n                    xReturn = pdTRUE;\n                }\n                else\n                {\n                    mtCOVERAGE_TEST_MARKER();\n                }\n            }\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n\n        return xReturn;\n    }\n\n#endif /* configUSE_MUTEXES */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_MUTEXES == 1 )\n\n    BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder )\n    {\n        TCB_t * const pxTCB = pxMutexHolder;\n        BaseType_t xReturn = pdFALSE;\n\n        if( pxMutexHolder != NULL )\n        {\n            /* A task can only have an inherited priority if it holds the mutex.\n             * If the mutex is held by a task then it cannot be given from an\n             * interrupt, and if a mutex is given by the holding task then it must\n             * be the running state task. */\n            configASSERT( pxTCB == pxCurrentTCB );\n            configASSERT( pxTCB->uxMutexesHeld );\n            ( pxTCB->uxMutexesHeld )--;\n\n            /* Has the holder of the mutex inherited the priority of another\n             * task? */\n            if( pxTCB->uxPriority != pxTCB->uxBasePriority )\n            {\n                /* Only disinherit if no other mutexes are held. */\n                if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 )\n                {\n                    /* A task can only have an inherited priority if it holds\n                     * the mutex.  If the mutex is held by a task then it cannot be\n                     * given from an interrupt, and if a mutex is given by the\n                     * holding task then it must be the running state task.  Remove\n                     * the holding task from the ready list. */\n                    if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )\n                    {\n                        portRESET_READY_PRIORITY( pxTCB->uxPriority, uxTopReadyPriority );\n                    }\n                    else\n                    {\n                        mtCOVERAGE_TEST_MARKER();\n                    }\n\n                    /* Disinherit the priority before adding the task into the\n                     * new  ready list. */\n                    traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );\n                    pxTCB->uxPriority = pxTCB->uxBasePriority;\n\n                    /* Reset the event list item value.  It cannot be in use for\n                     * any other purpose if this task is running, and it must be\n                     * running to give back the mutex. */\n                    listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\n                    prvAddTaskToReadyList( pxTCB );\n\n                    /* Return true to indicate that a context switch is required.\n                     * This is only actually required in the corner case whereby\n                     * multiple mutexes were held and the mutexes were given back\n                     * in an order different to that in which they were taken.\n                     * If a context switch did not occur when the first mutex was\n                     * returned, even if a task was waiting on it, then a context\n                     * switch should occur when the last mutex is returned whether\n                     * a task is waiting on it or not. */\n                    xReturn = pdTRUE;\n                }\n                else\n                {\n                    mtCOVERAGE_TEST_MARKER();\n                }\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n\n        return xReturn;\n    }\n\n#endif /* configUSE_MUTEXES */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_MUTEXES == 1 )\n\n    void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder,\n                                              UBaseType_t uxHighestPriorityWaitingTask )\n    {\n        TCB_t * const pxTCB = pxMutexHolder;\n        UBaseType_t uxPriorityUsedOnEntry, uxPriorityToUse;\n        const UBaseType_t uxOnlyOneMutexHeld = ( UBaseType_t ) 1;\n\n        if( pxMutexHolder != NULL )\n        {\n            /* If pxMutexHolder is not NULL then the holder must hold at least\n             * one mutex. */\n            configASSERT( pxTCB->uxMutexesHeld );\n\n            /* Determine the priority to which the priority of the task that\n             * holds the mutex should be set.  This will be the greater of the\n             * holding task's base priority and the priority of the highest\n             * priority task that is waiting to obtain the mutex. */\n            if( pxTCB->uxBasePriority < uxHighestPriorityWaitingTask )\n            {\n                uxPriorityToUse = uxHighestPriorityWaitingTask;\n            }\n            else\n            {\n                uxPriorityToUse = pxTCB->uxBasePriority;\n            }\n\n            /* Does the priority need to change? */\n            if( pxTCB->uxPriority != uxPriorityToUse )\n            {\n                /* Only disinherit if no other mutexes are held.  This is a\n                 * simplification in the priority inheritance implementation.  If\n                 * the task that holds the mutex is also holding other mutexes then\n                 * the other mutexes may have caused the priority inheritance. */\n                if( pxTCB->uxMutexesHeld == uxOnlyOneMutexHeld )\n                {\n                    /* If a task has timed out because it already holds the\n                     * mutex it was trying to obtain then it cannot of inherited\n                     * its own priority. */\n                    configASSERT( pxTCB != pxCurrentTCB );\n\n                    /* Disinherit the priority, remembering the previous\n                     * priority to facilitate determining the subject task's\n                     * state. */\n                    traceTASK_PRIORITY_DISINHERIT( pxTCB, uxPriorityToUse );\n                    uxPriorityUsedOnEntry = pxTCB->uxPriority;\n                    pxTCB->uxPriority = uxPriorityToUse;\n\n                    /* Only reset the event list item value if the value is not\n                     * being used for anything else. */\n                    if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )\n                    {\n                        listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriorityToUse ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\n                    }\n                    else\n                    {\n                        mtCOVERAGE_TEST_MARKER();\n                    }\n\n                    /* If the running task is not the task that holds the mutex\n                     * then the task that holds the mutex could be in either the\n                     * Ready, Blocked or Suspended states.  Only remove the task\n                     * from its current state list if it is in the Ready state as\n                     * the task's priority is going to change and there is one\n                     * Ready list per priority. */\n                    if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE )\n                    {\n                        if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )\n                        {\n                            /* It is known that the task is in its ready list so\n                             * there is no need to check again and the port level\n                             * reset macro can be called directly. */\n                            portRESET_READY_PRIORITY( pxTCB->uxPriority, uxTopReadyPriority );\n                        }\n                        else\n                        {\n                            mtCOVERAGE_TEST_MARKER();\n                        }\n\n                        prvAddTaskToReadyList( pxTCB );\n                    }\n                    else\n                    {\n                        mtCOVERAGE_TEST_MARKER();\n                    }\n                }\n                else\n                {\n                    mtCOVERAGE_TEST_MARKER();\n                }\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n    }\n\n#endif /* configUSE_MUTEXES */\n/*-----------------------------------------------------------*/\n\n#if ( portCRITICAL_NESTING_IN_TCB == 1 )\n\n    void vTaskEnterCritical( void )\n    {\n        portDISABLE_INTERRUPTS();\n\n        if( xSchedulerRunning != pdFALSE )\n        {\n            ( pxCurrentTCB->uxCriticalNesting )++;\n\n            /* This is not the interrupt safe version of the enter critical\n             * function so  assert() if it is being called from an interrupt\n             * context.  Only API functions that end in \"FromISR\" can be used in an\n             * interrupt.  Only assert if the critical nesting count is 1 to\n             * protect against recursive calls if the assert function also uses a\n             * critical section. */\n            if( pxCurrentTCB->uxCriticalNesting == 1 )\n            {\n                portASSERT_IF_IN_ISR();\n            }\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n    }\n\n#endif /* portCRITICAL_NESTING_IN_TCB */\n/*-----------------------------------------------------------*/\n\n#if ( portCRITICAL_NESTING_IN_TCB == 1 )\n\n    void vTaskExitCritical( void )\n    {\n        if( xSchedulerRunning != pdFALSE )\n        {\n            if( pxCurrentTCB->uxCriticalNesting > 0U )\n            {\n                ( pxCurrentTCB->uxCriticalNesting )--;\n\n                if( pxCurrentTCB->uxCriticalNesting == 0U )\n                {\n                    portENABLE_INTERRUPTS();\n                }\n                else\n                {\n                    mtCOVERAGE_TEST_MARKER();\n                }\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n    }\n\n#endif /* portCRITICAL_NESTING_IN_TCB */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 )\n\n    static char * prvWriteNameToBuffer( char * pcBuffer,\n                                        const char * pcTaskName )\n    {\n        size_t x;\n\n        /* Start by copying the entire string. */\n        strcpy( pcBuffer, pcTaskName );\n\n        /* Pad the end of the string with spaces to ensure columns line up when\n         * printed out. */\n        for( x = strlen( pcBuffer ); x < ( size_t ) ( configMAX_TASK_NAME_LEN - 1 ); x++ )\n        {\n            pcBuffer[ x ] = ' ';\n        }\n\n        /* Terminate. */\n        pcBuffer[ x ] = ( char ) 0x00;\n\n        /* Return the new end of string. */\n        return &( pcBuffer[ x ] );\n    }\n\n#endif /* ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) */\n/*-----------------------------------------------------------*/\n\n#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )\n\n    void vTaskList( char * pcWriteBuffer )\n    {\n        TaskStatus_t * pxTaskStatusArray;\n        UBaseType_t uxArraySize, x;\n        char cStatus;\n\n        /*\n         * PLEASE NOTE:\n         *\n         * This function is provided for convenience only, and is used by many\n         * of the demo applications.  Do not consider it to be part of the\n         * scheduler.\n         *\n         * vTaskList() calls uxTaskGetSystemState(), then formats part of the\n         * uxTaskGetSystemState() output into a human readable table that\n         * displays task: names, states, priority, stack usage and task number.\n         * Stack usage specified as the number of unused StackType_t words stack can hold\n         * on top of stack - not the number of bytes.\n         *\n         * vTaskList() has a dependency on the sprintf() C library function that\n         * might bloat the code size, use a lot of stack, and provide different\n         * results on different platforms.  An alternative, tiny, third party,\n         * and limited functionality implementation of sprintf() is provided in\n         * many of the FreeRTOS/Demo sub-directories in a file called\n         * printf-stdarg.c (note printf-stdarg.c does not provide a full\n         * snprintf() implementation!).\n         *\n         * It is recommended that production systems call uxTaskGetSystemState()\n         * directly to get access to raw stats data, rather than indirectly\n         * through a call to vTaskList().\n         */\n\n\n        /* Make sure the write buffer does not contain a string. */\n        *pcWriteBuffer = ( char ) 0x00;\n\n        /* Take a snapshot of the number of tasks in case it changes while this\n         * function is executing. */\n        uxArraySize = uxCurrentNumberOfTasks;\n\n        /* Allocate an array index for each task.  NOTE!  if\n         * configSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will\n         * equate to NULL. */\n        pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation allocates a struct that has the alignment requirements of a pointer. */\n\n        if( pxTaskStatusArray != NULL )\n        {\n            /* Generate the (binary) data. */\n            uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, NULL );\n\n            /* Create a human readable table from the binary data. */\n            for( x = 0; x < uxArraySize; x++ )\n            {\n                switch( pxTaskStatusArray[ x ].eCurrentState )\n                {\n                    case eRunning:\n                        cStatus = tskRUNNING_CHAR;\n                        break;\n\n                    case eReady:\n                        cStatus = tskREADY_CHAR;\n                        break;\n\n                    case eBlocked:\n                        cStatus = tskBLOCKED_CHAR;\n                        break;\n\n                    case eSuspended:\n                        cStatus = tskSUSPENDED_CHAR;\n                        break;\n\n                    case eDeleted:\n                        cStatus = tskDELETED_CHAR;\n                        break;\n\n                    case eInvalid: /* Fall through. */\n                    default:       /* Should not get here, but it is included\n                                    * to prevent static checking errors. */\n                        cStatus = ( char ) 0x00;\n                        break;\n                }\n\n                /* Write the task name to the string, padding with spaces so it\n                 * can be printed in tabular form more easily. */\n                pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName );\n\n                /* Write the rest of the string. */\n                sprintf( pcWriteBuffer, \"\\t%c\\t%u\\t%u\\t%u\\r\\n\", cStatus, ( unsigned int ) pxTaskStatusArray[ x ].uxCurrentPriority, ( unsigned int ) pxTaskStatusArray[ x ].usStackHighWaterMark, ( unsigned int ) pxTaskStatusArray[ x ].xTaskNumber ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */\n                pcWriteBuffer += strlen( pcWriteBuffer );                                                                                                                                                                                                /*lint !e9016 Pointer arithmetic ok on char pointers especially as in this case where it best denotes the intent of the code. */\n            }\n\n            /* Free the array again.  NOTE!  If configSUPPORT_DYNAMIC_ALLOCATION\n             * is 0 then vPortFree() will be #defined to nothing. */\n            vPortFree( pxTaskStatusArray );\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n    }\n\n#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) ) */\n/*----------------------------------------------------------*/\n\n#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configUSE_TRACE_FACILITY == 1 ) )\n\n    void vTaskGetRunTimeStats( char * pcWriteBuffer )\n    {\n        TaskStatus_t * pxTaskStatusArray;\n        UBaseType_t uxArraySize, x;\n        configRUN_TIME_COUNTER_TYPE ulTotalTime, ulStatsAsPercentage;\n\n        /*\n         * PLEASE NOTE:\n         *\n         * This function is provided for convenience only, and is used by many\n         * of the demo applications.  Do not consider it to be part of the\n         * scheduler.\n         *\n         * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part\n         * of the uxTaskGetSystemState() output into a human readable table that\n         * displays the amount of time each task has spent in the Running state\n         * in both absolute and percentage terms.\n         *\n         * vTaskGetRunTimeStats() has a dependency on the sprintf() C library\n         * function that might bloat the code size, use a lot of stack, and\n         * provide different results on different platforms.  An alternative,\n         * tiny, third party, and limited functionality implementation of\n         * sprintf() is provided in many of the FreeRTOS/Demo sub-directories in\n         * a file called printf-stdarg.c (note printf-stdarg.c does not provide\n         * a full snprintf() implementation!).\n         *\n         * It is recommended that production systems call uxTaskGetSystemState()\n         * directly to get access to raw stats data, rather than indirectly\n         * through a call to vTaskGetRunTimeStats().\n         */\n\n        /* Make sure the write buffer does not contain a string. */\n        *pcWriteBuffer = ( char ) 0x00;\n\n        /* Take a snapshot of the number of tasks in case it changes while this\n         * function is executing. */\n        uxArraySize = uxCurrentNumberOfTasks;\n\n        /* Allocate an array index for each task.  NOTE!  If\n         * configSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will\n         * equate to NULL. */\n        pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation allocates a struct that has the alignment requirements of a pointer. */\n\n        if( pxTaskStatusArray != NULL )\n        {\n            /* Generate the (binary) data. */\n            uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalTime );\n\n            /* For percentage calculations. */\n            ulTotalTime /= 100UL;\n\n            /* Avoid divide by zero errors. */\n            if( ulTotalTime > 0UL )\n            {\n                /* Create a human readable table from the binary data. */\n                for( x = 0; x < uxArraySize; x++ )\n                {\n                    /* What percentage of the total run time has the task used?\n                     * This will always be rounded down to the nearest integer.\n                     * ulTotalRunTime has already been divided by 100. */\n                    ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalTime;\n\n                    /* Write the task name to the string, padding with\n                     * spaces so it can be printed in tabular form more\n                     * easily. */\n                    pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName );\n\n                    if( ulStatsAsPercentage > 0UL )\n                    {\n                        #ifdef portLU_PRINTF_SPECIFIER_REQUIRED\n                        {\n                            sprintf( pcWriteBuffer, \"\\t%lu\\t\\t%lu%%\\r\\n\", pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage );\n                        }\n                        #else\n                        {\n                            /* sizeof( int ) == sizeof( long ) so a smaller\n                             * printf() library can be used. */\n                            sprintf( pcWriteBuffer, \"\\t%u\\t\\t%u%%\\r\\n\", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter, ( unsigned int ) ulStatsAsPercentage ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */\n                        }\n                        #endif\n                    }\n                    else\n                    {\n                        /* If the percentage is zero here then the task has\n                         * consumed less than 1% of the total run time. */\n                        #ifdef portLU_PRINTF_SPECIFIER_REQUIRED\n                        {\n                            sprintf( pcWriteBuffer, \"\\t%lu\\t\\t<1%%\\r\\n\", pxTaskStatusArray[ x ].ulRunTimeCounter );\n                        }\n                        #else\n                        {\n                            /* sizeof( int ) == sizeof( long ) so a smaller\n                             * printf() library can be used. */\n                            sprintf( pcWriteBuffer, \"\\t%u\\t\\t<1%%\\r\\n\", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */\n                        }\n                        #endif\n                    }\n\n                    pcWriteBuffer += strlen( pcWriteBuffer ); /*lint !e9016 Pointer arithmetic ok on char pointers especially as in this case where it best denotes the intent of the code. */\n                }\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n\n            /* Free the array again.  NOTE!  If configSUPPORT_DYNAMIC_ALLOCATION\n             * is 0 then vPortFree() will be #defined to nothing. */\n            vPortFree( pxTaskStatusArray );\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n    }\n\n#endif /* ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) ) */\n/*-----------------------------------------------------------*/\n\nTickType_t uxTaskResetEventItemValue( void )\n{\n    TickType_t uxReturn;\n\n    uxReturn = listGET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ) );\n\n    /* Reset the event list item to its normal value - so it can be used with\n     * queues and semaphores. */\n    listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\n\n    return uxReturn;\n}\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_MUTEXES == 1 )\n\n    TaskHandle_t pvTaskIncrementMutexHeldCount( void )\n    {\n        /* If xSemaphoreCreateMutex() is called before any tasks have been created\n         * then pxCurrentTCB will be NULL. */\n        if( pxCurrentTCB != NULL )\n        {\n            ( pxCurrentTCB->uxMutexesHeld )++;\n        }\n\n        return pxCurrentTCB;\n    }\n\n#endif /* configUSE_MUTEXES */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TASK_NOTIFICATIONS == 1 )\n\n    uint32_t ulTaskGenericNotifyTake( UBaseType_t uxIndexToWait,\n                                      BaseType_t xClearCountOnExit,\n                                      TickType_t xTicksToWait )\n    {\n        uint32_t ulReturn;\n\n        configASSERT( uxIndexToWait < configTASK_NOTIFICATION_ARRAY_ENTRIES );\n\n        taskENTER_CRITICAL();\n        {\n            /* Only block if the notification count is not already non-zero. */\n            if( pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] == 0UL )\n            {\n                /* Mark this task as waiting for a notification. */\n                pxCurrentTCB->ucNotifyState[ uxIndexToWait ] = taskWAITING_NOTIFICATION;\n\n                if( xTicksToWait > ( TickType_t ) 0 )\n                {\n                    prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );\n                    traceTASK_NOTIFY_TAKE_BLOCK( uxIndexToWait );\n\n                    /* All ports are written to allow a yield in a critical\n                     * section (some will yield immediately, others wait until the\n                     * critical section exits) - but it is not something that\n                     * application code should ever do. */\n                    portYIELD_WITHIN_API();\n                }\n                else\n                {\n                    mtCOVERAGE_TEST_MARKER();\n                }\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n        taskEXIT_CRITICAL();\n\n        taskENTER_CRITICAL();\n        {\n            traceTASK_NOTIFY_TAKE( uxIndexToWait );\n            ulReturn = pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ];\n\n            if( ulReturn != 0UL )\n            {\n                if( xClearCountOnExit != pdFALSE )\n                {\n                    pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] = 0UL;\n                }\n                else\n                {\n                    pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] = ulReturn - ( uint32_t ) 1;\n                }\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n\n            pxCurrentTCB->ucNotifyState[ uxIndexToWait ] = taskNOT_WAITING_NOTIFICATION;\n        }\n        taskEXIT_CRITICAL();\n\n        return ulReturn;\n    }\n\n#endif /* configUSE_TASK_NOTIFICATIONS */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TASK_NOTIFICATIONS == 1 )\n\n    BaseType_t xTaskGenericNotifyWait( UBaseType_t uxIndexToWait,\n                                       uint32_t ulBitsToClearOnEntry,\n                                       uint32_t ulBitsToClearOnExit,\n                                       uint32_t * pulNotificationValue,\n                                       TickType_t xTicksToWait )\n    {\n        BaseType_t xReturn;\n\n        configASSERT( uxIndexToWait < configTASK_NOTIFICATION_ARRAY_ENTRIES );\n\n        taskENTER_CRITICAL();\n        {\n            /* Only block if a notification is not already pending. */\n            if( pxCurrentTCB->ucNotifyState[ uxIndexToWait ] != taskNOTIFICATION_RECEIVED )\n            {\n                /* Clear bits in the task's notification value as bits may get\n                 * set  by the notifying task or interrupt.  This can be used to\n                 * clear the value to zero. */\n                pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] &= ~ulBitsToClearOnEntry;\n\n                /* Mark this task as waiting for a notification. */\n                pxCurrentTCB->ucNotifyState[ uxIndexToWait ] = taskWAITING_NOTIFICATION;\n\n                if( xTicksToWait > ( TickType_t ) 0 )\n                {\n                    prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );\n                    traceTASK_NOTIFY_WAIT_BLOCK( uxIndexToWait );\n\n                    /* All ports are written to allow a yield in a critical\n                     * section (some will yield immediately, others wait until the\n                     * critical section exits) - but it is not something that\n                     * application code should ever do. */\n                    portYIELD_WITHIN_API();\n                }\n                else\n                {\n                    mtCOVERAGE_TEST_MARKER();\n                }\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n        taskEXIT_CRITICAL();\n\n        taskENTER_CRITICAL();\n        {\n            traceTASK_NOTIFY_WAIT( uxIndexToWait );\n\n            if( pulNotificationValue != NULL )\n            {\n                /* Output the current notification value, which may or may not\n                 * have changed. */\n                *pulNotificationValue = pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ];\n            }\n\n            /* If ucNotifyValue is set then either the task never entered the\n             * blocked state (because a notification was already pending) or the\n             * task unblocked because of a notification.  Otherwise the task\n             * unblocked because of a timeout. */\n            if( pxCurrentTCB->ucNotifyState[ uxIndexToWait ] != taskNOTIFICATION_RECEIVED )\n            {\n                /* A notification was not received. */\n                xReturn = pdFALSE;\n            }\n            else\n            {\n                /* A notification was already pending or a notification was\n                 * received while the task was waiting. */\n                pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] &= ~ulBitsToClearOnExit;\n                xReturn = pdTRUE;\n            }\n\n            pxCurrentTCB->ucNotifyState[ uxIndexToWait ] = taskNOT_WAITING_NOTIFICATION;\n        }\n        taskEXIT_CRITICAL();\n\n        return xReturn;\n    }\n\n#endif /* configUSE_TASK_NOTIFICATIONS */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TASK_NOTIFICATIONS == 1 )\n\n    BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify,\n                                   UBaseType_t uxIndexToNotify,\n                                   uint32_t ulValue,\n                                   eNotifyAction eAction,\n                                   uint32_t * pulPreviousNotificationValue )\n    {\n        TCB_t * pxTCB;\n        BaseType_t xReturn = pdPASS;\n        uint8_t ucOriginalNotifyState;\n\n        configASSERT( uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES );\n        configASSERT( xTaskToNotify );\n        pxTCB = xTaskToNotify;\n\n        taskENTER_CRITICAL();\n        {\n            if( pulPreviousNotificationValue != NULL )\n            {\n                *pulPreviousNotificationValue = pxTCB->ulNotifiedValue[ uxIndexToNotify ];\n            }\n\n            ucOriginalNotifyState = pxTCB->ucNotifyState[ uxIndexToNotify ];\n\n            pxTCB->ucNotifyState[ uxIndexToNotify ] = taskNOTIFICATION_RECEIVED;\n\n            switch( eAction )\n            {\n                case eSetBits:\n                    pxTCB->ulNotifiedValue[ uxIndexToNotify ] |= ulValue;\n                    break;\n\n                case eIncrement:\n                    ( pxTCB->ulNotifiedValue[ uxIndexToNotify ] )++;\n                    break;\n\n                case eSetValueWithOverwrite:\n                    pxTCB->ulNotifiedValue[ uxIndexToNotify ] = ulValue;\n                    break;\n\n                case eSetValueWithoutOverwrite:\n\n                    if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED )\n                    {\n                        pxTCB->ulNotifiedValue[ uxIndexToNotify ] = ulValue;\n                    }\n                    else\n                    {\n                        /* The value could not be written to the task. */\n                        xReturn = pdFAIL;\n                    }\n\n                    break;\n\n                case eNoAction:\n\n                    /* The task is being notified without its notify value being\n                     * updated. */\n                    break;\n\n                default:\n\n                    /* Should not get here if all enums are handled.\n                     * Artificially force an assert by testing a value the\n                     * compiler can't assume is const. */\n                    configASSERT( xTickCount == ( TickType_t ) 0 );\n\n                    break;\n            }\n\n            traceTASK_NOTIFY( uxIndexToNotify );\n\n            /* If the task is in the blocked state specifically to wait for a\n             * notification then unblock it now. */\n            if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )\n            {\n                listREMOVE_ITEM( &( pxTCB->xStateListItem ) );\n                prvAddTaskToReadyList( pxTCB );\n\n                /* The task should not have been on an event list. */\n                configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );\n\n                #if ( configUSE_TICKLESS_IDLE != 0 )\n                {\n                    /* If a task is blocked waiting for a notification then\n                     * xNextTaskUnblockTime might be set to the blocked task's time\n                     * out time.  If the task is unblocked for a reason other than\n                     * a timeout xNextTaskUnblockTime is normally left unchanged,\n                     * because it will automatically get reset to a new value when\n                     * the tick count equals xNextTaskUnblockTime.  However if\n                     * tickless idling is used it might be more important to enter\n                     * sleep mode at the earliest possible time - so reset\n                     * xNextTaskUnblockTime here to ensure it is updated at the\n                     * earliest possible time. */\n                    prvResetNextTaskUnblockTime();\n                }\n                #endif\n\n                if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )\n                {\n                    /* The notified task has a priority above the currently\n                     * executing task so a yield is required. */\n                    taskYIELD_IF_USING_PREEMPTION();\n                }\n                else\n                {\n                    mtCOVERAGE_TEST_MARKER();\n                }\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n        taskEXIT_CRITICAL();\n\n        return xReturn;\n    }\n\n#endif /* configUSE_TASK_NOTIFICATIONS */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TASK_NOTIFICATIONS == 1 )\n\n    BaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify,\n                                          UBaseType_t uxIndexToNotify,\n                                          uint32_t ulValue,\n                                          eNotifyAction eAction,\n                                          uint32_t * pulPreviousNotificationValue,\n                                          BaseType_t * pxHigherPriorityTaskWoken )\n    {\n        TCB_t * pxTCB;\n        uint8_t ucOriginalNotifyState;\n        BaseType_t xReturn = pdPASS;\n        UBaseType_t uxSavedInterruptStatus;\n\n        configASSERT( xTaskToNotify );\n        configASSERT( uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES );\n\n        /* RTOS ports that support interrupt nesting have the concept of a\n         * maximum  system call (or maximum API call) interrupt priority.\n         * Interrupts that are  above the maximum system call priority are keep\n         * permanently enabled, even when the RTOS kernel is in a critical section,\n         * but cannot make any calls to FreeRTOS API functions.  If configASSERT()\n         * is defined in FreeRTOSConfig.h then\n         * portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion\n         * failure if a FreeRTOS API function is called from an interrupt that has\n         * been assigned a priority above the configured maximum system call\n         * priority.  Only FreeRTOS functions that end in FromISR can be called\n         * from interrupts  that have been assigned a priority at or (logically)\n         * below the maximum system call interrupt priority.  FreeRTOS maintains a\n         * separate interrupt safe API to ensure interrupt entry is as fast and as\n         * simple as possible.  More information (albeit Cortex-M specific) is\n         * provided on the following link:\n         * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\n        portASSERT_IF_INTERRUPT_PRIORITY_INVALID();\n\n        pxTCB = xTaskToNotify;\n\n        uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();\n        {\n            if( pulPreviousNotificationValue != NULL )\n            {\n                *pulPreviousNotificationValue = pxTCB->ulNotifiedValue[ uxIndexToNotify ];\n            }\n\n            ucOriginalNotifyState = pxTCB->ucNotifyState[ uxIndexToNotify ];\n            pxTCB->ucNotifyState[ uxIndexToNotify ] = taskNOTIFICATION_RECEIVED;\n\n            switch( eAction )\n            {\n                case eSetBits:\n                    pxTCB->ulNotifiedValue[ uxIndexToNotify ] |= ulValue;\n                    break;\n\n                case eIncrement:\n                    ( pxTCB->ulNotifiedValue[ uxIndexToNotify ] )++;\n                    break;\n\n                case eSetValueWithOverwrite:\n                    pxTCB->ulNotifiedValue[ uxIndexToNotify ] = ulValue;\n                    break;\n\n                case eSetValueWithoutOverwrite:\n\n                    if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED )\n                    {\n                        pxTCB->ulNotifiedValue[ uxIndexToNotify ] = ulValue;\n                    }\n                    else\n                    {\n                        /* The value could not be written to the task. */\n                        xReturn = pdFAIL;\n                    }\n\n                    break;\n\n                case eNoAction:\n\n                    /* The task is being notified without its notify value being\n                     * updated. */\n                    break;\n\n                default:\n\n                    /* Should not get here if all enums are handled.\n                     * Artificially force an assert by testing a value the\n                     * compiler can't assume is const. */\n                    configASSERT( xTickCount == ( TickType_t ) 0 );\n                    break;\n            }\n\n            traceTASK_NOTIFY_FROM_ISR( uxIndexToNotify );\n\n            /* If the task is in the blocked state specifically to wait for a\n             * notification then unblock it now. */\n            if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )\n            {\n                /* The task should not have been on an event list. */\n                configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );\n\n                if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )\n                {\n                    listREMOVE_ITEM( &( pxTCB->xStateListItem ) );\n                    prvAddTaskToReadyList( pxTCB );\n                }\n                else\n                {\n                    /* The delayed and ready lists cannot be accessed, so hold\n                     * this task pending until the scheduler is resumed. */\n                    listINSERT_END( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );\n                }\n\n                if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )\n                {\n                    /* The notified task has a priority above the currently\n                     * executing task so a yield is required. */\n                    if( pxHigherPriorityTaskWoken != NULL )\n                    {\n                        *pxHigherPriorityTaskWoken = pdTRUE;\n                    }\n\n                    /* Mark that a yield is pending in case the user is not\n                     * using the \"xHigherPriorityTaskWoken\" parameter to an ISR\n                     * safe FreeRTOS function. */\n                    xYieldPending = pdTRUE;\n                }\n                else\n                {\n                    mtCOVERAGE_TEST_MARKER();\n                }\n            }\n        }\n        portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\n\n        return xReturn;\n    }\n\n#endif /* configUSE_TASK_NOTIFICATIONS */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TASK_NOTIFICATIONS == 1 )\n\n    void vTaskGenericNotifyGiveFromISR( TaskHandle_t xTaskToNotify,\n                                        UBaseType_t uxIndexToNotify,\n                                        BaseType_t * pxHigherPriorityTaskWoken )\n    {\n        TCB_t * pxTCB;\n        uint8_t ucOriginalNotifyState;\n        UBaseType_t uxSavedInterruptStatus;\n\n        configASSERT( xTaskToNotify );\n        configASSERT( uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES );\n\n        /* RTOS ports that support interrupt nesting have the concept of a\n         * maximum  system call (or maximum API call) interrupt priority.\n         * Interrupts that are  above the maximum system call priority are keep\n         * permanently enabled, even when the RTOS kernel is in a critical section,\n         * but cannot make any calls to FreeRTOS API functions.  If configASSERT()\n         * is defined in FreeRTOSConfig.h then\n         * portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion\n         * failure if a FreeRTOS API function is called from an interrupt that has\n         * been assigned a priority above the configured maximum system call\n         * priority.  Only FreeRTOS functions that end in FromISR can be called\n         * from interrupts  that have been assigned a priority at or (logically)\n         * below the maximum system call interrupt priority.  FreeRTOS maintains a\n         * separate interrupt safe API to ensure interrupt entry is as fast and as\n         * simple as possible.  More information (albeit Cortex-M specific) is\n         * provided on the following link:\n         * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\n        portASSERT_IF_INTERRUPT_PRIORITY_INVALID();\n\n        pxTCB = xTaskToNotify;\n\n        uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();\n        {\n            ucOriginalNotifyState = pxTCB->ucNotifyState[ uxIndexToNotify ];\n            pxTCB->ucNotifyState[ uxIndexToNotify ] = taskNOTIFICATION_RECEIVED;\n\n            /* 'Giving' is equivalent to incrementing a count in a counting\n             * semaphore. */\n            ( pxTCB->ulNotifiedValue[ uxIndexToNotify ] )++;\n\n            traceTASK_NOTIFY_GIVE_FROM_ISR( uxIndexToNotify );\n\n            /* If the task is in the blocked state specifically to wait for a\n             * notification then unblock it now. */\n            if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )\n            {\n                /* The task should not have been on an event list. */\n                configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );\n\n                if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )\n                {\n                    listREMOVE_ITEM( &( pxTCB->xStateListItem ) );\n                    prvAddTaskToReadyList( pxTCB );\n                }\n                else\n                {\n                    /* The delayed and ready lists cannot be accessed, so hold\n                     * this task pending until the scheduler is resumed. */\n                    listINSERT_END( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );\n                }\n\n                if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )\n                {\n                    /* The notified task has a priority above the currently\n                     * executing task so a yield is required. */\n                    if( pxHigherPriorityTaskWoken != NULL )\n                    {\n                        *pxHigherPriorityTaskWoken = pdTRUE;\n                    }\n\n                    /* Mark that a yield is pending in case the user is not\n                     * using the \"xHigherPriorityTaskWoken\" parameter in an ISR\n                     * safe FreeRTOS function. */\n                    xYieldPending = pdTRUE;\n                }\n                else\n                {\n                    mtCOVERAGE_TEST_MARKER();\n                }\n            }\n        }\n        portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\n    }\n\n#endif /* configUSE_TASK_NOTIFICATIONS */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TASK_NOTIFICATIONS == 1 )\n\n    BaseType_t xTaskGenericNotifyStateClear( TaskHandle_t xTask,\n                                             UBaseType_t uxIndexToClear )\n    {\n        TCB_t * pxTCB;\n        BaseType_t xReturn;\n\n        configASSERT( uxIndexToClear < configTASK_NOTIFICATION_ARRAY_ENTRIES );\n\n        /* If null is passed in here then it is the calling task that is having\n         * its notification state cleared. */\n        pxTCB = prvGetTCBFromHandle( xTask );\n\n        taskENTER_CRITICAL();\n        {\n            if( pxTCB->ucNotifyState[ uxIndexToClear ] == taskNOTIFICATION_RECEIVED )\n            {\n                pxTCB->ucNotifyState[ uxIndexToClear ] = taskNOT_WAITING_NOTIFICATION;\n                xReturn = pdPASS;\n            }\n            else\n            {\n                xReturn = pdFAIL;\n            }\n        }\n        taskEXIT_CRITICAL();\n\n        return xReturn;\n    }\n\n#endif /* configUSE_TASK_NOTIFICATIONS */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TASK_NOTIFICATIONS == 1 )\n\n    uint32_t ulTaskGenericNotifyValueClear( TaskHandle_t xTask,\n                                            UBaseType_t uxIndexToClear,\n                                            uint32_t ulBitsToClear )\n    {\n        TCB_t * pxTCB;\n        uint32_t ulReturn;\n\n        /* If null is passed in here then it is the calling task that is having\n         * its notification state cleared. */\n        pxTCB = prvGetTCBFromHandle( xTask );\n\n        taskENTER_CRITICAL();\n        {\n            /* Return the notification as it was before the bits were cleared,\n             * then clear the bit mask. */\n            ulReturn = pxTCB->ulNotifiedValue[ uxIndexToClear ];\n            pxTCB->ulNotifiedValue[ uxIndexToClear ] &= ~ulBitsToClear;\n        }\n        taskEXIT_CRITICAL();\n\n        return ulReturn;\n    }\n\n#endif /* configUSE_TASK_NOTIFICATIONS */\n/*-----------------------------------------------------------*/\n\n#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )\n\n    configRUN_TIME_COUNTER_TYPE ulTaskGetIdleRunTimeCounter( void )\n    {\n        return xIdleTaskHandle->ulRunTimeCounter;\n    }\n\n#endif\n/*-----------------------------------------------------------*/\n\n#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )\n\n    configRUN_TIME_COUNTER_TYPE ulTaskGetIdleRunTimePercent( void )\n    {\n        configRUN_TIME_COUNTER_TYPE ulTotalTime, ulReturn;\n\n        ulTotalTime = portGET_RUN_TIME_COUNTER_VALUE();\n\n        /* For percentage calculations. */\n        ulTotalTime /= ( configRUN_TIME_COUNTER_TYPE ) 100;\n\n        /* Avoid divide by zero errors. */\n        if( ulTotalTime > ( configRUN_TIME_COUNTER_TYPE ) 0 )\n        {\n            ulReturn = xIdleTaskHandle->ulRunTimeCounter / ulTotalTime;\n        }\n        else\n        {\n            ulReturn = 0;\n        }\n\n        return ulReturn;\n    }\n\n#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */\n/*-----------------------------------------------------------*/\n\nstatic void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait,\n                                            const BaseType_t xCanBlockIndefinitely )\n{\n    TickType_t xTimeToWake;\n    const TickType_t xConstTickCount = xTickCount;\n\n    #if ( INCLUDE_xTaskAbortDelay == 1 )\n    {\n        /* About to enter a delayed list, so ensure the ucDelayAborted flag is\n         * reset to pdFALSE so it can be detected as having been set to pdTRUE\n         * when the task leaves the Blocked state. */\n        pxCurrentTCB->ucDelayAborted = pdFALSE;\n    }\n    #endif\n\n    /* Remove the task from the ready list before adding it to the blocked list\n     * as the same list item is used for both lists. */\n    if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )\n    {\n        /* The current task must be in a ready list, so there is no need to\n         * check, and the port reset macro can be called directly. */\n        portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority ); /*lint !e931 pxCurrentTCB cannot change as it is the calling task.  pxCurrentTCB->uxPriority and uxTopReadyPriority cannot change as called with scheduler suspended or in a critical section. */\n    }\n    else\n    {\n        mtCOVERAGE_TEST_MARKER();\n    }\n\n    #if ( INCLUDE_vTaskSuspend == 1 )\n    {\n        if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) )\n        {\n            /* Add the task to the suspended task list instead of a delayed task\n             * list to ensure it is not woken by a timing event.  It will block\n             * indefinitely. */\n            listINSERT_END( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) );\n        }\n        else\n        {\n            /* Calculate the time at which the task should be woken if the event\n             * does not occur.  This may overflow but this doesn't matter, the\n             * kernel will manage it correctly. */\n            xTimeToWake = xConstTickCount + xTicksToWait;\n\n            /* The list item will be inserted in wake time order. */\n            listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );\n\n            if( xTimeToWake < xConstTickCount )\n            {\n                /* Wake time has overflowed.  Place this item in the overflow\n                 * list. */\n                vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );\n            }\n            else\n            {\n                /* The wake time has not overflowed, so the current block list\n                 * is used. */\n                vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );\n\n                /* If the task entering the blocked state was placed at the\n                 * head of the list of blocked tasks then xNextTaskUnblockTime\n                 * needs to be updated too. */\n                if( xTimeToWake < xNextTaskUnblockTime )\n                {\n                    xNextTaskUnblockTime = xTimeToWake;\n                }\n                else\n                {\n                    mtCOVERAGE_TEST_MARKER();\n                }\n            }\n        }\n    }\n    #else /* INCLUDE_vTaskSuspend */\n    {\n        /* Calculate the time at which the task should be woken if the event\n         * does not occur.  This may overflow but this doesn't matter, the kernel\n         * will manage it correctly. */\n        xTimeToWake = xConstTickCount + xTicksToWait;\n\n        /* The list item will be inserted in wake time order. */\n        listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );\n\n        if( xTimeToWake < xConstTickCount )\n        {\n            /* Wake time has overflowed.  Place this item in the overflow list. */\n            vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );\n        }\n        else\n        {\n            /* The wake time has not overflowed, so the current block list is used. */\n            vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );\n\n            /* If the task entering the blocked state was placed at the head of the\n             * list of blocked tasks then xNextTaskUnblockTime needs to be updated\n             * too. */\n            if( xTimeToWake < xNextTaskUnblockTime )\n            {\n                xNextTaskUnblockTime = xTimeToWake;\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n\n        /* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */\n        ( void ) xCanBlockIndefinitely;\n    }\n    #endif /* INCLUDE_vTaskSuspend */\n}\n\n/* Code below here allows additional code to be inserted into this source file,\n * especially where access to file scope functions and data is needed (for example\n * when performing module tests). */\n\n#ifdef FREERTOS_MODULE_TEST\n    #include \"tasks_test_access_functions.h\"\n#endif\n\n\n#if ( configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H == 1 )\n\n    #include \"freertos_tasks_c_additions.h\"\n\n    #ifdef FREERTOS_TASKS_C_ADDITIONS_INIT\n        static void freertos_tasks_c_additions_init( void )\n        {\n            FREERTOS_TASKS_C_ADDITIONS_INIT();\n        }\n    #endif\n\n#endif /* if ( configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H == 1 ) */\n"
  },
  {
    "path": "FreeRTOS-comparison/timers.c",
    "content": "/*\n * FreeRTOS Kernel V10.5.1\n * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * SPDX-License-Identifier: MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * https://www.FreeRTOS.org\n * https://github.com/FreeRTOS\n *\n */\n\n/* Standard includes. */\n#include <stdlib.h>\n\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\n * all the API functions to use the MPU wrappers.  That should only be done when\n * task.h is included from an application file. */\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n#include \"queue.h\"\n#include \"timers.h\"\n\n#if ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 0 )\n    #error configUSE_TIMERS must be set to 1 to make the xTimerPendFunctionCall() function available.\n#endif\n\n/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified\n * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined\n * for the header files above, but not in this file, in order to generate the\n * correct privileged Vs unprivileged linkage and placement. */\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e9021 !e961 !e750. */\n\n\n/* This entire source file will be skipped if the application is not configured\n * to include software timer functionality.  This #if is closed at the very bottom\n * of this file.  If you want to include software timer functionality then ensure\n * configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */\n#if ( configUSE_TIMERS == 1 )\n\n/* Misc definitions. */\n    #define tmrNO_DELAY                    ( ( TickType_t ) 0U )\n    #define tmrMAX_TIME_BEFORE_OVERFLOW    ( ( TickType_t ) -1 )\n\n/* The name assigned to the timer service task.  This can be overridden by\n * defining trmTIMER_SERVICE_TASK_NAME in FreeRTOSConfig.h. */\n    #ifndef configTIMER_SERVICE_TASK_NAME\n        #define configTIMER_SERVICE_TASK_NAME    \"Tmr Svc\"\n    #endif\n\n/* Bit definitions used in the ucStatus member of a timer structure. */\n    #define tmrSTATUS_IS_ACTIVE                  ( ( uint8_t ) 0x01 )\n    #define tmrSTATUS_IS_STATICALLY_ALLOCATED    ( ( uint8_t ) 0x02 )\n    #define tmrSTATUS_IS_AUTORELOAD              ( ( uint8_t ) 0x04 )\n\n/* The definition of the timers themselves. */\n    typedef struct tmrTimerControl                  /* The old naming convention is used to prevent breaking kernel aware debuggers. */\n    {\n        const char * pcTimerName;                   /*<< Text name.  This is not used by the kernel, it is included simply to make debugging easier. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n        ListItem_t xTimerListItem;                  /*<< Standard linked list item as used by all kernel features for event management. */\n        TickType_t xTimerPeriodInTicks;             /*<< How quickly and often the timer expires. */\n        void * pvTimerID;                           /*<< An ID to identify the timer.  This allows the timer to be identified when the same callback is used for multiple timers. */\n        TimerCallbackFunction_t pxCallbackFunction; /*<< The function that will be called when the timer expires. */\n        #if ( configUSE_TRACE_FACILITY == 1 )\n            UBaseType_t uxTimerNumber;              /*<< An ID assigned by trace tools such as FreeRTOS+Trace */\n        #endif\n        uint8_t ucStatus;                           /*<< Holds bits to say if the timer was statically allocated or not, and if it is active or not. */\n    } xTIMER;\n\n/* The old xTIMER name is maintained above then typedefed to the new Timer_t\n * name below to enable the use of older kernel aware debuggers. */\n    typedef xTIMER Timer_t;\n\n/* The definition of messages that can be sent and received on the timer queue.\n * Two types of message can be queued - messages that manipulate a software timer,\n * and messages that request the execution of a non-timer related callback.  The\n * two message types are defined in two separate structures, xTimerParametersType\n * and xCallbackParametersType respectively. */\n    typedef struct tmrTimerParameters\n    {\n        TickType_t xMessageValue; /*<< An optional value used by a subset of commands, for example, when changing the period of a timer. */\n        Timer_t * pxTimer;        /*<< The timer to which the command will be applied. */\n    } TimerParameter_t;\n\n\n    typedef struct tmrCallbackParameters\n    {\n        PendedFunction_t pxCallbackFunction; /* << The callback function to execute. */\n        void * pvParameter1;                 /* << The value that will be used as the callback functions first parameter. */\n        uint32_t ulParameter2;               /* << The value that will be used as the callback functions second parameter. */\n    } CallbackParameters_t;\n\n/* The structure that contains the two message types, along with an identifier\n * that is used to determine which message type is valid. */\n    typedef struct tmrTimerQueueMessage\n    {\n        BaseType_t xMessageID; /*<< The command being sent to the timer service task. */\n        union\n        {\n            TimerParameter_t xTimerParameters;\n\n            /* Don't include xCallbackParameters if it is not going to be used as\n             * it makes the structure (and therefore the timer queue) larger. */\n            #if ( INCLUDE_xTimerPendFunctionCall == 1 )\n                CallbackParameters_t xCallbackParameters;\n            #endif /* INCLUDE_xTimerPendFunctionCall */\n        } u;\n    } DaemonTaskMessage_t;\n\n/*lint -save -e956 A manual analysis and inspection has been used to determine\n * which static variables must be declared volatile. */\n\n/* The list in which active timers are stored.  Timers are referenced in expire\n * time order, with the nearest expiry time at the front of the list.  Only the\n * timer service task is allowed to access these lists.\n * xActiveTimerList1 and xActiveTimerList2 could be at function scope but that\n * breaks some kernel aware debuggers, and debuggers that reply on removing the\n * static qualifier. */\n    PRIVILEGED_DATA static List_t xActiveTimerList1;\n    PRIVILEGED_DATA static List_t xActiveTimerList2;\n    PRIVILEGED_DATA static List_t * pxCurrentTimerList;\n    PRIVILEGED_DATA static List_t * pxOverflowTimerList;\n\n/* A queue that is used to send commands to the timer service task. */\n    PRIVILEGED_DATA static QueueHandle_t xTimerQueue = NULL;\n    PRIVILEGED_DATA static TaskHandle_t xTimerTaskHandle = NULL;\n\n/*lint -restore */\n\n/*-----------------------------------------------------------*/\n\n/*\n * Initialise the infrastructure used by the timer service task if it has not\n * been initialised already.\n */\n    static void prvCheckForValidListAndQueue( void ) PRIVILEGED_FUNCTION;\n\n/*\n * The timer service task (daemon).  Timer functionality is controlled by this\n * task.  Other tasks communicate with the timer service task using the\n * xTimerQueue queue.\n */\n    static portTASK_FUNCTION_PROTO( prvTimerTask, pvParameters ) PRIVILEGED_FUNCTION;\n\n/*\n * Called by the timer service task to interpret and process a command it\n * received on the timer queue.\n */\n    static void prvProcessReceivedCommands( void ) PRIVILEGED_FUNCTION;\n\n/*\n * Insert the timer into either xActiveTimerList1, or xActiveTimerList2,\n * depending on if the expire time causes a timer counter overflow.\n */\n    static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer,\n                                                  const TickType_t xNextExpiryTime,\n                                                  const TickType_t xTimeNow,\n                                                  const TickType_t xCommandTime ) PRIVILEGED_FUNCTION;\n\n/*\n * Reload the specified auto-reload timer.  If the reloading is backlogged,\n * clear the backlog, calling the callback for each additional reload.  When\n * this function returns, the next expiry time is after xTimeNow.\n */\n    static void prvReloadTimer( Timer_t * const pxTimer,\n                                TickType_t xExpiredTime,\n                                const TickType_t xTimeNow ) PRIVILEGED_FUNCTION;\n\n/*\n * An active timer has reached its expire time.  Reload the timer if it is an\n * auto-reload timer, then call its callback.\n */\n    static void prvProcessExpiredTimer( const TickType_t xNextExpireTime,\n                                        const TickType_t xTimeNow ) PRIVILEGED_FUNCTION;\n\n/*\n * The tick count has overflowed.  Switch the timer lists after ensuring the\n * current timer list does not still reference some timers.\n */\n    static void prvSwitchTimerLists( void ) PRIVILEGED_FUNCTION;\n\n/*\n * Obtain the current tick count, setting *pxTimerListsWereSwitched to pdTRUE\n * if a tick count overflow occurred since prvSampleTimeNow() was last called.\n */\n    static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched ) PRIVILEGED_FUNCTION;\n\n/*\n * If the timer list contains any active timers then return the expire time of\n * the timer that will expire first and set *pxListWasEmpty to false.  If the\n * timer list does not contain any timers then return 0 and set *pxListWasEmpty\n * to pdTRUE.\n */\n    static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty ) PRIVILEGED_FUNCTION;\n\n/*\n * If a timer has expired, process it.  Otherwise, block the timer service task\n * until either a timer does expire or a command is received.\n */\n    static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime,\n                                            BaseType_t xListWasEmpty ) PRIVILEGED_FUNCTION;\n\n/*\n * Called after a Timer_t structure has been allocated either statically or\n * dynamically to fill in the structure's members.\n */\n    static void prvInitialiseNewTimer( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n                                       const TickType_t xTimerPeriodInTicks,\n                                       const BaseType_t xAutoReload,\n                                       void * const pvTimerID,\n                                       TimerCallbackFunction_t pxCallbackFunction,\n                                       Timer_t * pxNewTimer ) PRIVILEGED_FUNCTION;\n/*-----------------------------------------------------------*/\n\n    BaseType_t xTimerCreateTimerTask( void )\n    {\n        BaseType_t xReturn = pdFAIL;\n\n        /* This function is called when the scheduler is started if\n         * configUSE_TIMERS is set to 1.  Check that the infrastructure used by the\n         * timer service task has been created/initialised.  If timers have already\n         * been created then the initialisation will already have been performed. */\n        prvCheckForValidListAndQueue();\n\n        if( xTimerQueue != NULL )\n        {\n            #if ( configSUPPORT_STATIC_ALLOCATION == 1 )\n            {\n                StaticTask_t * pxTimerTaskTCBBuffer = NULL;\n                StackType_t * pxTimerTaskStackBuffer = NULL;\n                uint32_t ulTimerTaskStackSize;\n\n                vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize );\n                xTimerTaskHandle = xTaskCreateStatic( prvTimerTask,\n                                                      configTIMER_SERVICE_TASK_NAME,\n                                                      ulTimerTaskStackSize,\n                                                      NULL,\n                                                      ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,\n                                                      pxTimerTaskStackBuffer,\n                                                      pxTimerTaskTCBBuffer );\n\n                if( xTimerTaskHandle != NULL )\n                {\n                    xReturn = pdPASS;\n                }\n            }\n            #else /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */\n            {\n                xReturn = xTaskCreate( prvTimerTask,\n                                       configTIMER_SERVICE_TASK_NAME,\n                                       configTIMER_TASK_STACK_DEPTH,\n                                       NULL,\n                                       ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,\n                                       &xTimerTaskHandle );\n            }\n            #endif /* configSUPPORT_STATIC_ALLOCATION */\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n\n        configASSERT( xReturn );\n        return xReturn;\n    }\n/*-----------------------------------------------------------*/\n\n    #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n\n        TimerHandle_t xTimerCreate( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n                                    const TickType_t xTimerPeriodInTicks,\n                                    const BaseType_t xAutoReload,\n                                    void * const pvTimerID,\n                                    TimerCallbackFunction_t pxCallbackFunction )\n        {\n            Timer_t * pxNewTimer;\n\n            pxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of Timer_t is always a pointer to the timer's mame. */\n\n            if( pxNewTimer != NULL )\n            {\n                /* Status is thus far zero as the timer is not created statically\n                 * and has not been started.  The auto-reload bit may get set in\n                 * prvInitialiseNewTimer. */\n                pxNewTimer->ucStatus = 0x00;\n                prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, xAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer );\n            }\n\n            return pxNewTimer;\n        }\n\n    #endif /* configSUPPORT_DYNAMIC_ALLOCATION */\n/*-----------------------------------------------------------*/\n\n    #if ( configSUPPORT_STATIC_ALLOCATION == 1 )\n\n        TimerHandle_t xTimerCreateStatic( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n                                          const TickType_t xTimerPeriodInTicks,\n                                          const BaseType_t xAutoReload,\n                                          void * const pvTimerID,\n                                          TimerCallbackFunction_t pxCallbackFunction,\n                                          StaticTimer_t * pxTimerBuffer )\n        {\n            Timer_t * pxNewTimer;\n\n            #if ( configASSERT_DEFINED == 1 )\n            {\n                /* Sanity check that the size of the structure used to declare a\n                 * variable of type StaticTimer_t equals the size of the real timer\n                 * structure. */\n                volatile size_t xSize = sizeof( StaticTimer_t );\n                configASSERT( xSize == sizeof( Timer_t ) );\n                ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */\n            }\n            #endif /* configASSERT_DEFINED */\n\n            /* A pointer to a StaticTimer_t structure MUST be provided, use it. */\n            configASSERT( pxTimerBuffer );\n            pxNewTimer = ( Timer_t * ) pxTimerBuffer; /*lint !e740 !e9087 StaticTimer_t is a pointer to a Timer_t, so guaranteed to be aligned and sized correctly (checked by an assert()), so this is safe. */\n\n            if( pxNewTimer != NULL )\n            {\n                /* Timers can be created statically or dynamically so note this\n                 * timer was created statically in case it is later deleted.  The\n                 * auto-reload bit may get set in prvInitialiseNewTimer(). */\n                pxNewTimer->ucStatus = tmrSTATUS_IS_STATICALLY_ALLOCATED;\n\n                prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, xAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer );\n            }\n\n            return pxNewTimer;\n        }\n\n    #endif /* configSUPPORT_STATIC_ALLOCATION */\n/*-----------------------------------------------------------*/\n\n    static void prvInitialiseNewTimer( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n                                       const TickType_t xTimerPeriodInTicks,\n                                       const BaseType_t xAutoReload,\n                                       void * const pvTimerID,\n                                       TimerCallbackFunction_t pxCallbackFunction,\n                                       Timer_t * pxNewTimer )\n    {\n        /* 0 is not a valid value for xTimerPeriodInTicks. */\n        configASSERT( ( xTimerPeriodInTicks > 0 ) );\n\n        /* Ensure the infrastructure used by the timer service task has been\n         * created/initialised. */\n        prvCheckForValidListAndQueue();\n\n        /* Initialise the timer structure members using the function\n         * parameters. */\n        pxNewTimer->pcTimerName = pcTimerName;\n        pxNewTimer->xTimerPeriodInTicks = xTimerPeriodInTicks;\n        pxNewTimer->pvTimerID = pvTimerID;\n        pxNewTimer->pxCallbackFunction = pxCallbackFunction;\n        vListInitialiseItem( &( pxNewTimer->xTimerListItem ) );\n\n        if( xAutoReload != pdFALSE )\n        {\n            pxNewTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD;\n        }\n\n        traceTIMER_CREATE( pxNewTimer );\n    }\n/*-----------------------------------------------------------*/\n\n    BaseType_t xTimerGenericCommand( TimerHandle_t xTimer,\n                                     const BaseType_t xCommandID,\n                                     const TickType_t xOptionalValue,\n                                     BaseType_t * const pxHigherPriorityTaskWoken,\n                                     const TickType_t xTicksToWait )\n    {\n        BaseType_t xReturn = pdFAIL;\n        DaemonTaskMessage_t xMessage;\n\n        configASSERT( xTimer );\n\n        /* Send a message to the timer service task to perform a particular action\n         * on a particular timer definition. */\n        if( xTimerQueue != NULL )\n        {\n            /* Send a command to the timer service task to start the xTimer timer. */\n            xMessage.xMessageID = xCommandID;\n            xMessage.u.xTimerParameters.xMessageValue = xOptionalValue;\n            xMessage.u.xTimerParameters.pxTimer = xTimer;\n\n            if( xCommandID < tmrFIRST_FROM_ISR_COMMAND )\n            {\n                if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING )\n                {\n                    xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );\n                }\n                else\n                {\n                    xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY );\n                }\n            }\n            else\n            {\n                xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );\n            }\n\n            traceTIMER_COMMAND_SEND( xTimer, xCommandID, xOptionalValue, xReturn );\n        }\n        else\n        {\n            mtCOVERAGE_TEST_MARKER();\n        }\n\n        return xReturn;\n    }\n/*-----------------------------------------------------------*/\n\n    TaskHandle_t xTimerGetTimerDaemonTaskHandle( void )\n    {\n        /* If xTimerGetTimerDaemonTaskHandle() is called before the scheduler has been\n         * started, then xTimerTaskHandle will be NULL. */\n        configASSERT( ( xTimerTaskHandle != NULL ) );\n        return xTimerTaskHandle;\n    }\n/*-----------------------------------------------------------*/\n\n    TickType_t xTimerGetPeriod( TimerHandle_t xTimer )\n    {\n        Timer_t * pxTimer = xTimer;\n\n        configASSERT( xTimer );\n        return pxTimer->xTimerPeriodInTicks;\n    }\n/*-----------------------------------------------------------*/\n\n    void vTimerSetReloadMode( TimerHandle_t xTimer,\n                              const BaseType_t xAutoReload )\n    {\n        Timer_t * pxTimer = xTimer;\n\n        configASSERT( xTimer );\n        taskENTER_CRITICAL();\n        {\n            if( xAutoReload != pdFALSE )\n            {\n                pxTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD;\n            }\n            else\n            {\n                pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_AUTORELOAD );\n            }\n        }\n        taskEXIT_CRITICAL();\n    }\n/*-----------------------------------------------------------*/\n\n    BaseType_t xTimerGetReloadMode( TimerHandle_t xTimer )\n    {\n        Timer_t * pxTimer = xTimer;\n        BaseType_t xReturn;\n\n        configASSERT( xTimer );\n        taskENTER_CRITICAL();\n        {\n            if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) == 0 )\n            {\n                /* Not an auto-reload timer. */\n                xReturn = pdFALSE;\n            }\n            else\n            {\n                /* Is an auto-reload timer. */\n                xReturn = pdTRUE;\n            }\n        }\n        taskEXIT_CRITICAL();\n\n        return xReturn;\n    }\n\n    UBaseType_t uxTimerGetReloadMode( TimerHandle_t xTimer )\n    {\n        return ( UBaseType_t ) xTimerGetReloadMode( xTimer );\n    }\n/*-----------------------------------------------------------*/\n\n    TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer )\n    {\n        Timer_t * pxTimer = xTimer;\n        TickType_t xReturn;\n\n        configASSERT( xTimer );\n        xReturn = listGET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ) );\n        return xReturn;\n    }\n/*-----------------------------------------------------------*/\n\n    const char * pcTimerGetName( TimerHandle_t xTimer ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n    {\n        Timer_t * pxTimer = xTimer;\n\n        configASSERT( xTimer );\n        return pxTimer->pcTimerName;\n    }\n/*-----------------------------------------------------------*/\n\n    static void prvReloadTimer( Timer_t * const pxTimer,\n                                TickType_t xExpiredTime,\n                                const TickType_t xTimeNow )\n    {\n        /* Insert the timer into the appropriate list for the next expiry time.\n         * If the next expiry time has already passed, advance the expiry time,\n         * call the callback function, and try again. */\n        while( prvInsertTimerInActiveList( pxTimer, ( xExpiredTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xExpiredTime ) != pdFALSE )\n        {\n            /* Advance the expiry time. */\n            xExpiredTime += pxTimer->xTimerPeriodInTicks;\n\n            /* Call the timer callback. */\n            traceTIMER_EXPIRED( pxTimer );\n            pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );\n        }\n    }\n/*-----------------------------------------------------------*/\n\n    static void prvProcessExpiredTimer( const TickType_t xNextExpireTime,\n                                        const TickType_t xTimeNow )\n    {\n        Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */\n\n        /* Remove the timer from the list of active timers.  A check has already\n         * been performed to ensure the list is not empty. */\n\n        ( void ) uxListRemove( &( pxTimer->xTimerListItem ) );\n\n        /* If the timer is an auto-reload timer then calculate the next\n         * expiry time and re-insert the timer in the list of active timers. */\n        if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )\n        {\n            prvReloadTimer( pxTimer, xNextExpireTime, xTimeNow );\n        }\n        else\n        {\n            pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE );\n        }\n\n        /* Call the timer callback. */\n        traceTIMER_EXPIRED( pxTimer );\n        pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );\n    }\n/*-----------------------------------------------------------*/\n\n    static portTASK_FUNCTION( prvTimerTask, pvParameters )\n    {\n        TickType_t xNextExpireTime;\n        BaseType_t xListWasEmpty;\n\n        /* Just to avoid compiler warnings. */\n        ( void ) pvParameters;\n\n        #if ( configUSE_DAEMON_TASK_STARTUP_HOOK == 1 )\n        {\n            extern void vApplicationDaemonTaskStartupHook( void );\n\n            /* Allow the application writer to execute some code in the context of\n             * this task at the point the task starts executing.  This is useful if the\n             * application includes initialisation code that would benefit from\n             * executing after the scheduler has been started. */\n            vApplicationDaemonTaskStartupHook();\n        }\n        #endif /* configUSE_DAEMON_TASK_STARTUP_HOOK */\n\n        for( ; ; )\n        {\n            /* Query the timers list to see if it contains any timers, and if so,\n             * obtain the time at which the next timer will expire. */\n            xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty );\n\n            /* If a timer has expired, process it.  Otherwise, block this task\n             * until either a timer does expire, or a command is received. */\n            prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty );\n\n            /* Empty the command queue. */\n            prvProcessReceivedCommands();\n        }\n    }\n/*-----------------------------------------------------------*/\n\n    static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime,\n                                            BaseType_t xListWasEmpty )\n    {\n        TickType_t xTimeNow;\n        BaseType_t xTimerListsWereSwitched;\n\n        vTaskSuspendAll();\n        {\n            /* Obtain the time now to make an assessment as to whether the timer\n             * has expired or not.  If obtaining the time causes the lists to switch\n             * then don't process this timer as any timers that remained in the list\n             * when the lists were switched will have been processed within the\n             * prvSampleTimeNow() function. */\n            xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );\n\n            if( xTimerListsWereSwitched == pdFALSE )\n            {\n                /* The tick count has not overflowed, has the timer expired? */\n                if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) )\n                {\n                    ( void ) xTaskResumeAll();\n                    prvProcessExpiredTimer( xNextExpireTime, xTimeNow );\n                }\n                else\n                {\n                    /* The tick count has not overflowed, and the next expire\n                     * time has not been reached yet.  This task should therefore\n                     * block to wait for the next expire time or a command to be\n                     * received - whichever comes first.  The following line cannot\n                     * be reached unless xNextExpireTime > xTimeNow, except in the\n                     * case when the current timer list is empty. */\n                    if( xListWasEmpty != pdFALSE )\n                    {\n                        /* The current timer list is empty - is the overflow list\n                         * also empty? */\n                        xListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList );\n                    }\n\n                    vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty );\n\n                    if( xTaskResumeAll() == pdFALSE )\n                    {\n                        /* Yield to wait for either a command to arrive, or the\n                         * block time to expire.  If a command arrived between the\n                         * critical section being exited and this yield then the yield\n                         * will not cause the task to block. */\n                        portYIELD_WITHIN_API();\n                    }\n                    else\n                    {\n                        mtCOVERAGE_TEST_MARKER();\n                    }\n                }\n            }\n            else\n            {\n                ( void ) xTaskResumeAll();\n            }\n        }\n    }\n/*-----------------------------------------------------------*/\n\n    static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty )\n    {\n        TickType_t xNextExpireTime;\n\n        /* Timers are listed in expiry time order, with the head of the list\n         * referencing the task that will expire first.  Obtain the time at which\n         * the timer with the nearest expiry time will expire.  If there are no\n         * active timers then just set the next expire time to 0.  That will cause\n         * this task to unblock when the tick count overflows, at which point the\n         * timer lists will be switched and the next expiry time can be\n         * re-assessed.  */\n        *pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList );\n\n        if( *pxListWasEmpty == pdFALSE )\n        {\n            xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );\n        }\n        else\n        {\n            /* Ensure the task unblocks when the tick count rolls over. */\n            xNextExpireTime = ( TickType_t ) 0U;\n        }\n\n        return xNextExpireTime;\n    }\n/*-----------------------------------------------------------*/\n\n    static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched )\n    {\n        TickType_t xTimeNow;\n        PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */\n\n        xTimeNow = xTaskGetTickCount();\n\n        if( xTimeNow < xLastTime )\n        {\n            prvSwitchTimerLists();\n            *pxTimerListsWereSwitched = pdTRUE;\n        }\n        else\n        {\n            *pxTimerListsWereSwitched = pdFALSE;\n        }\n\n        xLastTime = xTimeNow;\n\n        return xTimeNow;\n    }\n/*-----------------------------------------------------------*/\n\n    static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer,\n                                                  const TickType_t xNextExpiryTime,\n                                                  const TickType_t xTimeNow,\n                                                  const TickType_t xCommandTime )\n    {\n        BaseType_t xProcessTimerNow = pdFALSE;\n\n        listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime );\n        listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );\n\n        if( xNextExpiryTime <= xTimeNow )\n        {\n            /* Has the expiry time elapsed between the command to start/reset a\n             * timer was issued, and the time the command was processed? */\n            if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\n            {\n                /* The time between a command being issued and the command being\n                 * processed actually exceeds the timers period.  */\n                xProcessTimerNow = pdTRUE;\n            }\n            else\n            {\n                vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) );\n            }\n        }\n        else\n        {\n            if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) )\n            {\n                /* If, since the command was issued, the tick count has overflowed\n                 * but the expiry time has not, then the timer must have already passed\n                 * its expiry time and should be processed immediately. */\n                xProcessTimerNow = pdTRUE;\n            }\n            else\n            {\n                vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );\n            }\n        }\n\n        return xProcessTimerNow;\n    }\n/*-----------------------------------------------------------*/\n\n    static void prvProcessReceivedCommands( void )\n    {\n        DaemonTaskMessage_t xMessage;\n        Timer_t * pxTimer;\n        BaseType_t xTimerListsWereSwitched;\n        TickType_t xTimeNow;\n\n        while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */\n        {\n            #if ( INCLUDE_xTimerPendFunctionCall == 1 )\n            {\n                /* Negative commands are pended function calls rather than timer\n                 * commands. */\n                if( xMessage.xMessageID < ( BaseType_t ) 0 )\n                {\n                    const CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters );\n\n                    /* The timer uses the xCallbackParameters member to request a\n                     * callback be executed.  Check the callback is not NULL. */\n                    configASSERT( pxCallback );\n\n                    /* Call the function. */\n                    pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 );\n                }\n                else\n                {\n                    mtCOVERAGE_TEST_MARKER();\n                }\n            }\n            #endif /* INCLUDE_xTimerPendFunctionCall */\n\n            /* Commands that are positive are timer commands rather than pended\n             * function calls. */\n            if( xMessage.xMessageID >= ( BaseType_t ) 0 )\n            {\n                /* The messages uses the xTimerParameters member to work on a\n                 * software timer. */\n                pxTimer = xMessage.u.xTimerParameters.pxTimer;\n\n                if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE ) /*lint !e961. The cast is only redundant when NULL is passed into the macro. */\n                {\n                    /* The timer is in a list, remove it. */\n                    ( void ) uxListRemove( &( pxTimer->xTimerListItem ) );\n                }\n                else\n                {\n                    mtCOVERAGE_TEST_MARKER();\n                }\n\n                traceTIMER_COMMAND_RECEIVED( pxTimer, xMessage.xMessageID, xMessage.u.xTimerParameters.xMessageValue );\n\n                /* In this case the xTimerListsWereSwitched parameter is not used, but\n                 *  it must be present in the function call.  prvSampleTimeNow() must be\n                 *  called after the message is received from xTimerQueue so there is no\n                 *  possibility of a higher priority task adding a message to the message\n                 *  queue with a time that is ahead of the timer daemon task (because it\n                 *  pre-empted the timer daemon task after the xTimeNow value was set). */\n                xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );\n\n                switch( xMessage.xMessageID )\n                {\n                    case tmrCOMMAND_START:\n                    case tmrCOMMAND_START_FROM_ISR:\n                    case tmrCOMMAND_RESET:\n                    case tmrCOMMAND_RESET_FROM_ISR:\n                        /* Start or restart a timer. */\n                        pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;\n\n                        if( prvInsertTimerInActiveList( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE )\n                        {\n                            /* The timer expired before it was added to the active\n                             * timer list.  Process it now. */\n                            if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )\n                            {\n                                prvReloadTimer( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow );\n                            }\n                            else\n                            {\n                                pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE );\n                            }\n\n                            /* Call the timer callback. */\n                            traceTIMER_EXPIRED( pxTimer );\n                            pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );\n                        }\n                        else\n                        {\n                            mtCOVERAGE_TEST_MARKER();\n                        }\n\n                        break;\n\n                    case tmrCOMMAND_STOP:\n                    case tmrCOMMAND_STOP_FROM_ISR:\n                        /* The timer has already been removed from the active list. */\n                        pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE );\n                        break;\n\n                    case tmrCOMMAND_CHANGE_PERIOD:\n                    case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR:\n                        pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;\n                        pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue;\n                        configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) );\n\n                        /* The new period does not really have a reference, and can\n                         * be longer or shorter than the old one.  The command time is\n                         * therefore set to the current time, and as the period cannot\n                         * be zero the next expiry time can only be in the future,\n                         * meaning (unlike for the xTimerStart() case above) there is\n                         * no fail case that needs to be handled here. */\n                        ( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow );\n                        break;\n\n                    case tmrCOMMAND_DELETE:\n                        #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n                        {\n                            /* The timer has already been removed from the active list,\n                             * just free up the memory if the memory was dynamically\n                             * allocated. */\n                            if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 )\n                            {\n                                vPortFree( pxTimer );\n                            }\n                            else\n                            {\n                                pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE );\n                            }\n                        }\n                        #else /* if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) */\n                        {\n                            /* If dynamic allocation is not enabled, the memory\n                             * could not have been dynamically allocated. So there is\n                             * no need to free the memory - just mark the timer as\n                             * \"not active\". */\n                            pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE );\n                        }\n                        #endif /* configSUPPORT_DYNAMIC_ALLOCATION */\n                        break;\n\n                    default:\n                        /* Don't expect to get here. */\n                        break;\n                }\n            }\n        }\n    }\n/*-----------------------------------------------------------*/\n\n    static void prvSwitchTimerLists( void )\n    {\n        TickType_t xNextExpireTime;\n        List_t * pxTemp;\n\n        /* The tick count has overflowed.  The timer lists must be switched.\n         * If there are any timers still referenced from the current timer list\n         * then they must have expired and should be processed before the lists\n         * are switched. */\n        while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE )\n        {\n            xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );\n\n            /* Process the expired timer.  For auto-reload timers, be careful to\n             * process only expirations that occur on the current list.  Further\n             * expirations must wait until after the lists are switched. */\n            prvProcessExpiredTimer( xNextExpireTime, tmrMAX_TIME_BEFORE_OVERFLOW );\n        }\n\n        pxTemp = pxCurrentTimerList;\n        pxCurrentTimerList = pxOverflowTimerList;\n        pxOverflowTimerList = pxTemp;\n    }\n/*-----------------------------------------------------------*/\n\n    static void prvCheckForValidListAndQueue( void )\n    {\n        /* Check that the list from which active timers are referenced, and the\n         * queue used to communicate with the timer service, have been\n         * initialised. */\n        taskENTER_CRITICAL();\n        {\n            if( xTimerQueue == NULL )\n            {\n                vListInitialise( &xActiveTimerList1 );\n                vListInitialise( &xActiveTimerList2 );\n                pxCurrentTimerList = &xActiveTimerList1;\n                pxOverflowTimerList = &xActiveTimerList2;\n\n                #if ( configSUPPORT_STATIC_ALLOCATION == 1 )\n                {\n                    /* The timer queue is allocated statically in case\n                     * configSUPPORT_DYNAMIC_ALLOCATION is 0. */\n                    PRIVILEGED_DATA static StaticQueue_t xStaticTimerQueue;                                                                          /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */\n                    PRIVILEGED_DATA static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ]; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */\n\n                    xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue );\n                }\n                #else\n                {\n                    xTimerQueue = xQueueCreate( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, sizeof( DaemonTaskMessage_t ) );\n                }\n                #endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */\n\n                #if ( configQUEUE_REGISTRY_SIZE > 0 )\n                {\n                    if( xTimerQueue != NULL )\n                    {\n                        vQueueAddToRegistry( xTimerQueue, \"TmrQ\" );\n                    }\n                    else\n                    {\n                        mtCOVERAGE_TEST_MARKER();\n                    }\n                }\n                #endif /* configQUEUE_REGISTRY_SIZE */\n            }\n            else\n            {\n                mtCOVERAGE_TEST_MARKER();\n            }\n        }\n        taskEXIT_CRITICAL();\n    }\n/*-----------------------------------------------------------*/\n\n    BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer )\n    {\n        BaseType_t xReturn;\n        Timer_t * pxTimer = xTimer;\n\n        configASSERT( xTimer );\n\n        /* Is the timer in the list of active timers? */\n        taskENTER_CRITICAL();\n        {\n            if( ( pxTimer->ucStatus & tmrSTATUS_IS_ACTIVE ) == 0 )\n            {\n                xReturn = pdFALSE;\n            }\n            else\n            {\n                xReturn = pdTRUE;\n            }\n        }\n        taskEXIT_CRITICAL();\n\n        return xReturn;\n    } /*lint !e818 Can't be pointer to const due to the typedef. */\n/*-----------------------------------------------------------*/\n\n    void * pvTimerGetTimerID( const TimerHandle_t xTimer )\n    {\n        Timer_t * const pxTimer = xTimer;\n        void * pvReturn;\n\n        configASSERT( xTimer );\n\n        taskENTER_CRITICAL();\n        {\n            pvReturn = pxTimer->pvTimerID;\n        }\n        taskEXIT_CRITICAL();\n\n        return pvReturn;\n    }\n/*-----------------------------------------------------------*/\n\n    void vTimerSetTimerID( TimerHandle_t xTimer,\n                           void * pvNewID )\n    {\n        Timer_t * const pxTimer = xTimer;\n\n        configASSERT( xTimer );\n\n        taskENTER_CRITICAL();\n        {\n            pxTimer->pvTimerID = pvNewID;\n        }\n        taskEXIT_CRITICAL();\n    }\n/*-----------------------------------------------------------*/\n\n    #if ( INCLUDE_xTimerPendFunctionCall == 1 )\n\n        BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend,\n                                                  void * pvParameter1,\n                                                  uint32_t ulParameter2,\n                                                  BaseType_t * pxHigherPriorityTaskWoken )\n        {\n            DaemonTaskMessage_t xMessage;\n            BaseType_t xReturn;\n\n            /* Complete the message with the function parameters and post it to the\n             * daemon task. */\n            xMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR;\n            xMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend;\n            xMessage.u.xCallbackParameters.pvParameter1 = pvParameter1;\n            xMessage.u.xCallbackParameters.ulParameter2 = ulParameter2;\n\n            xReturn = xQueueSendFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );\n\n            tracePEND_FUNC_CALL_FROM_ISR( xFunctionToPend, pvParameter1, ulParameter2, xReturn );\n\n            return xReturn;\n        }\n\n    #endif /* INCLUDE_xTimerPendFunctionCall */\n/*-----------------------------------------------------------*/\n\n    #if ( INCLUDE_xTimerPendFunctionCall == 1 )\n\n        BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend,\n                                           void * pvParameter1,\n                                           uint32_t ulParameter2,\n                                           TickType_t xTicksToWait )\n        {\n            DaemonTaskMessage_t xMessage;\n            BaseType_t xReturn;\n\n            /* This function can only be called after a timer has been created or\n             * after the scheduler has been started because, until then, the timer\n             * queue does not exist. */\n            configASSERT( xTimerQueue );\n\n            /* Complete the message with the function parameters and post it to the\n             * daemon task. */\n            xMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK;\n            xMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend;\n            xMessage.u.xCallbackParameters.pvParameter1 = pvParameter1;\n            xMessage.u.xCallbackParameters.ulParameter2 = ulParameter2;\n\n            xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );\n\n            tracePEND_FUNC_CALL( xFunctionToPend, pvParameter1, ulParameter2, xReturn );\n\n            return xReturn;\n        }\n\n    #endif /* INCLUDE_xTimerPendFunctionCall */\n/*-----------------------------------------------------------*/\n\n    #if ( configUSE_TRACE_FACILITY == 1 )\n\n        UBaseType_t uxTimerGetTimerNumber( TimerHandle_t xTimer )\n        {\n            return ( ( Timer_t * ) xTimer )->uxTimerNumber;\n        }\n\n    #endif /* configUSE_TRACE_FACILITY */\n/*-----------------------------------------------------------*/\n\n    #if ( configUSE_TRACE_FACILITY == 1 )\n\n        void vTimerSetTimerNumber( TimerHandle_t xTimer,\n                                   UBaseType_t uxTimerNumber )\n        {\n            ( ( Timer_t * ) xTimer )->uxTimerNumber = uxTimerNumber;\n        }\n\n    #endif /* configUSE_TRACE_FACILITY */\n/*-----------------------------------------------------------*/\n\n/* This entire source file will be skipped if the application is not configured\n * to include software timer functionality.  If you want to include software timer\n * functionality then ensure configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */\n#endif /* configUSE_TIMERS == 1 */\n"
  },
  {
    "path": "FreeRTOS-comparison/version_FeeRTOS-202210-LTS.txt",
    "content": "This directory is the FreeRTOS Kernel part of the FreeRTOS 202210 LTS.\nTo reduce the size, the portable sub-directory has been pruned and\nseveral FreeRTOS ports have been removed."
  },
  {
    "path": "LICENSE",
    "content": "MIT License\n\nCopyright (c) 2021 Quantum Leaps, <state-machine.com>.\n\nPermission is hereby granted, free of charge, to any person obtaining a copy\nof this software and associated documentation files (the \"Software\"), to deal\nin the Software without restriction, including without limitation the rights\nto use, copy, modify, merge, publish, distribute, sublicense, and/or sell\ncopies of the Software, and to permit persons to whom the Software is\nfurnished to do so, subject to the following conditions:\n\nThe above copyright notice and this permission notice shall be included in all\ncopies or substantial portions of the Software.\n\nTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\nIMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\nFITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\nAUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\nLIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\nOUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\nSOFTWARE.\n"
  },
  {
    "path": "README.md",
    "content": "## Brought to you by:\n[![Quantum Leaps](https://www.state-machine.com/attachments/logo_ql_400.png)](https://www.state-machine.com)\n<hr>\n\n[![GitHub release (latest by date)](https://img.shields.io/github/v/release/QuantumLeaps/Super-Simple-Tasker)](https://github.com/QuantumLeaps/Super-Simple-Tasker/releases/latest)\n[![GitHub](https://img.shields.io/github/license/QuantumLeaps/Super-Simple-Tasker)](https://github.com/QuantumLeaps/Super-Simple-Tasker/blob/master/LICENSE)\n\n# Super-Simple Tasker (SST)\nSuper-Simple Tasker (SST) is an event-driven, preemptive, priority-based\nreal-time operating system (RTOS) kernel that is fully compatible with\nthe requirements of\n[Rate Monotonic Analysis/Scheduling (RMA/RMS)](https://youtu.be/kLxxXNCrY60).\n\n<p align=\"center\">\n<a href=\"https://youtu.be/PTcauYl994A\" target=\"_blank\" title=\"SST video\">\n<img src=\"img/logo_sst_c-cpp.png\"/></p>\n</a></p>\n\nThe tasks in SST are non-blocking and run-to-completion, which are also known\nas **basic tasks** in the\n[OSEK/VDX Operating System Specification](https://www.irisa.fr/alf/downloads/puaut/TPNXT/images/os223.pdf). SST corresponds to the BCC2 conformance class in OSEK/VDX.\nSST provides the following features:\n- basic tasks (non-blocking, run-to-completion)\n- preemptive, priority-based scheduling\n- multiple tasks per priority level\n- multiple \"activations\" per task (event queues)\n- selective scheduler locking according to \"Stack Resource Policy\" (SRP)<br>\n  (a non-blocking mutual exclusion mechanism for protecting shared resources)\n\n> **NOTE**<br>\nThe execution profile of SST tasks perfectly matches the non-blocking and\nrun-to-completion semantics of event-driven state machines\n(a.k.a. [\"Active Objects\" or \"Actors](https://www.state-machine.com/active-object)).\n\nThis repository contains the SST following implementations:\n- [preemptive SST in C](sst_c)\n- [preemptive SST in C++](sst_cpp)\n\nAdditionally, this repository contains the even simpler, *non-preemptive*\nimplementation of basic tasks called [SST0](#non-preemptive-sst0):\n- [non-preemptive SST0 in C](sst0_c)\n- [non-preemptive SST0 in C++](sst0_cpp)\n\n\n> **NOTE**<br>\nThe preemptive SST and non-preemptive SST0 implement actually *the same*\n[SST API](https://github.com/QuantumLeaps/Super-Simple-Tasker/tree/main/include)\n(either in C or C++).\n\n\n## Related Approaches\nThe SST RTOS kernel is related to, although *not* based on, the following\napproaches:\n\n- [Operating System - OSEK VDX](https://www.osek-vdx.org/mirror/os21r1.pdf)\n- [A Stack-Based Resource Allocation Policy for Realtime Processes](https://ieeexplore.ieee.org/document/128747)\n- [Real-Time For the Masses](https://www.diva-portal.org/smash/get/diva2:1005680/FULLTEXT01.pdf)\n- [crect: A C++, compile-time, reactive RTOS](https://github.com/korken89/crect)\n- [Rust's Real Time For the Masses (RTFM)](https://lonesometraveler.github.io/2020/05/22/RTFM.html)\n- [Real-Time Interrupt-driven Concurrency (RTIC)](https://rtic.rs/1/book/en)\n\n\n# Hardware RTOS for ARM Cortex-M\n[SST for ARM Cortex-M](sst_c/ports/arm-cm) provides a unique\n**hardware implementation** of the SST API for ARM Cortex-M (M0, M0+, M3,\nM4, M7, M23, M33). The SST \"hardware RTOS\" for ARM Cortex-M is fully\ncompatible with the requirements of\n[Rate Monotonic Analysis/Scheduling (RMA/RMS)](https://youtu.be/kLxxXNCrY60).\n\n<p align=\"center\"><img src=\"img/logo_sst-arm-cm.png\"/></p>\n\n> **NOTE**<br>\nThe SST hardware implementation is likely the most performant and efficient\n**hard-real time RTOS** kernel for ARM Cortex-M.\n\n\n# Hardware RTOS for Microchip dsPIC\nThe contributed [SST port for dsPIC](sst_c/ports/dspic) provides a unique\n**hardware implementation** of the SST API for\n[Microchip dsPIC](https://www.microchip.com/en-us/products/microcontrollers-and-microprocessors/dspic-dscs).\nThe SST \"hardware RTOS\" for dsPIC is fully compatible with the requirements of\n[Rate Monotonic Analysis/Scheduling (RMA/RMS)](https://youtu.be/kLxxXNCrY60).\n\n<p align=\"center\"><img src=\"img/dsPIC.png\"/></p>\n\n\n# SST Videos\nSST has been presented at the Embedded Online Conference 2023 and the videos\nare available on YouTube:\n\n<p align=\"center\">\n<a href=\"https://youtu.be/PTcauYl994A\" target=\"_blank\" title=\"SST video\">\n<img src=\"img/sst-video.jpg\"/>\n</a></p>\n\n\n# SST History\nSST has been originally published as a cover-story article\n[\"Build a Super-Simple Tasker\"](legacy/Super-Simple-Tasker.pdf) in the\nEmbedded Systems Design magazine in\n[July 2006](https://www.embedded.com/embedded-systems-design-july-2006).\nThat original version of SST (now called \"Legacy SST\") is\n[still available](legacy) and is provided for historical reference.\n\nOver the years, more complete SST-like kernels have been developed\nfor a number of embedded processors, such as: ARM7TDMI, ARM Cortex-M (M0-M7),\nARM Cortex-R, MSP430, PIC24/dsPIC, PIC32, etc. All these kernels are now\nincluded in the\n[QP/C and QP/C++ Real-Time Embedded Frameworks](https://www.state-machine.com/products/qp):\n\n- [QK preemptive, priority-based, non-blocking kernel](https://www.state-machine.com/qpc/srs_qk.html)\nworks like SST and is available as one of the built-in kernels in the\n[QP Real-Time Embedded Frameworks (RTEFs)](https://www.state-machine.com/products/qp).\n\n- [QXK preemptive, dual-mode kernel](https://www.state-machine.com/qpc/srs_qxk.html)\ncombines the basic-tasks of SST with traditional blocking tasks (a.k.a.\n**extended tasks** in OSEK/VDX) and is available as one of the\nbuilt-in kernels in the\n[QP Real-Time Embedded Frameworks (RTEFs)](https://www.state-machine.com/products/qp)\n\n- [QV priority-based, cooperative kernel](https://www.state-machine.com/qpc/srs_qv.html)\nworks like [SST0](#non-preemptive-sst0) and is available as one of the built-in\nkernels in the\n[QP Real-Time Embedded Frameworks (RTEFs)](https://www.state-machine.com/products)\n\n\n# Non-Preemptive SST0\nThis repository contains also the non-preemptive implementation of the\nSST API, called **SST0**. SST0 is also a **priority-based RTOS kernel**,\nbut the scheduling is non-preemptive. SST0 scheduler always executes the\nhighest-priority basic task ready to run, but the scheduling is performed\nonly after voluntary completion of each task (run-to-completion execution).\n\n<p align=\"center\"><img src=\"img/logo_sst0-chip.png\"/></p>\n\nSST0 provides the following features:\n- basic tasks (non-blocking, run-to-completion)\n- priority-based, non-preemptive (cooperative) scheduling\n- only one task per priority level\n- multiple \"activations\" per task (event queues)\n\n\n# Getting Started / Examples\nThe best way to get started with SST is to build and run the provided\n**examples**. This repository contains several versions of the\n**\"blinky-button\" example**, which contains several SST tasks running\nconcurrently and communicating with each other. The \"blinky-button\" example\ndemonstrates **real-time** capabilities of SST and uses a logic analyzer.\n(REMARK: Logic analyzer is not necessary to build and run the examples.)\n\n<p align=\"center\"><img src=\"img/blinky_button.png\"/></p>\n\nThe \"blinky-button\" example is provided for:\n```c\nSuper-Simple-Tasker/\n|\n+---sst_c/                     // preemptive SST/C\n|   +----examples/             // examples for SST/C\n|   |    +----blinky_button/   // \"blinky-button\" example\n|   |    |    +----armclang/   // project for ARM/KEIL\n|   |    |    +----gnu/        // makefile for GNU-ARM\n|   |    |    +----iar/        // project for IAR EWARM\n|\n+---sst_cpp/                   // preemptive SST/C++\n|   +----examples/             // examples for SST/C++\n|   |    +----blinky_button/   // \"blinky-button\" example\n|   |    |    +----armclang/   // project for ARM/KEIL\n|   |    |    +----gnu/        // makefile for GNU-ARM\n|   |    |    +----iar/        // project for IAR EWARM\n|\n+---sst0_c/                    // non-preemptive SST0/C\n|   +----examples/             // examples for SST0/C\n|   |    +----blinky_button/   // \"blinky-button\" example\n|   |    |    +----armclang/   // project for ARM/KEIL\n|   |    |    +----gnu/        // makefile for GNU-ARM\n|   |    |    +----iar/        // project for IAR EWARM\n|\n+---sst0_cpp/                  // non-preemptive SST0/C++\n|   +----examples/             // examples for SST0/C++\n|   |    +----blinky_button/   // \"blinky-button\" example\n|   |    |    +----armclang/   // project for ARM/KEIL\n|   |    |    +----gnu/        // makefile for GNU-ARM\n|   |    |    +----iar/        // project for IAR EWARM\n|\n```\nFor **every** of these cases the projects to build the examples are provided\nfor the following embedded boards:\n\n<p align=\"center\">\n<img src=\"img/bd-nucleos.png\"/>\n<img src=\"img/bd_EK-TM4C123GXL.jpg\"/>\n</p>\n\n- **STM32 NUCLEO-C031C6** (ARM Cortex-M0+)\n- **STM32 NUCLEO-L053R8** (ARM Cortex-M0+)\n- **STM32 NUCLEO-H743ZI** (ARM Cortex-M7 with double-precision FPU)\n- **TivaC LaunchPad (EK-TM4C123GXL)** (ARM Cortex-M4 with single-precision FPU)\n\n# Licensing\nThe SST source code and examples are released under the terms of the\npermissive [MIT open source license](LICENSE). Please note that the\nattribution clause in the MIT license requires you to preserve the\noriginal copyright notice in all changes and derivate works.\n\n\n# Invitation to Collaborate\n**This project welcomes collaboration!** Please help to improve SST,\nport it to other processors, integrate it with other embedded software,\nadd interesting examples, etc. To avoid fragmentation, this repository is\nintended to remain the home of SST. To contribute, please clone, fork,\nand submit **pull requests** to incorporate your changes.\n\n\n# How to Help this Project?\nIf you like this project, please **spread the word** about SST on various\nforums, social media, and other venues frequented by embedded folks!\n\n<p align=\"center\"><img src=\"img/spread-the-word.jpg\"/></p>\n\nAlso, please give [this repository](https://github.com/QuantumLeaps/Super-Simple-Tasker)\na star (in the upper-right corner of your browser window)\n\n<p align=\"center\"><img src=\"img/github-star.jpg\"/></p>\n"
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  },
  {
    "path": "include/README.txt",
    "content": "This directory contains the following SST API definitions:\n- sst.h   -- SST API in C\n- sst.hpp -- SST API in C++\n\nNOTE:\nThe SST API is the same for various SST implementatinons, such as\nthe preemptive SST and the non-preemptive SST0.\n"
  },
  {
    "path": "include/dbc_assert.h",
    "content": "/*============================================================================\n* Design By Contract (DBC) for embedded C and C++\n* GitHub: https://github.com/QuantumLeaps/DBC-for-embedded-C\n*\n*                    Q u a n t u m  L e a P s\n*                    ------------------------\n*                    Modern Embedded Software\n*\n* Copyright (C) 2005 Quantum Leaps, <state-machine.com>.\n*\n* SPDX-License-Identifier: MIT\n*\n* Permission is hereby granted, free of charge, to any person obtaining a\n* copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included in\n* all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n============================================================================*/\n#ifndef DBC_ASSERT_H_\n#define DBC_ASSERT_H_\n\n/*! @file\n* @brief Memory-efficient Design by Contract (DBC) for embedded C and C++.\n*\n* @note\n* The runtime checking of the DBC assertions can be disabled by defining\n* the macro #DBC_DISABLE. However, it is generally **not** advisable to\n* disable assertions, *especially* in the production code. Instead, the\n* assertion fault handler DBC_fault_handler() should be very carefully\n* designed and tested under all fault conditions.\n*/\n\n/* Active DbC macros -------------------------------------------------------*/\n#ifndef DBC_DISABLE\n\n/*! Define the user-specified module name for assertions in this file.\n*\n* @details\n* Macro to be placed at the top of each C/C++ module to define the\n* single instance of the module name string to be used in reporting\n* assertions in this module. This macro takes the user-supplied parameter\n* `name_`.\n*\n* @param[in] name_ string constant representing the module name\n*\n* @note\n* This macro should **not** be terminated by a semicolon.\n*/\n#define DBC_MODULE_NAME(name_) \\\n    static char const DBC_module_name_[] = name_;\n\n/*! General purpose assertion with user-specified ID number.\n*\n* @details\n* Makes sure the `expr_` parameter is TRUE. Calls the DBC_fault_handler()\n* callback if the `expr_` evaluates to FALSE. This assertion takes the\n* user-supplied parameter `label_` to identify the location of this\n* assertion within the module. This avoids the volatility of using line\n* numbers, which change whenever a line of code is added or removed\n* upstream from the assertion.\n*\n* @param[in] label_ numeric label of the assertion (unique within the module)\n* @param[in] expr_  Boolean expression to check\n*\n* @note\n* The `expr_` expression is **not** evaluated if assertions are\n* disabled with the ::DBC_DISABLE switch.\n*/\n#define DBC_ASSERT(label_, expr_) ((expr_) \\\n    ? ((void)0) : DBC_fault_handler(&DBC_module_name_[0], (label_)))\n\n/*! General purpose assertion with user-specified ID number that\n* evaluates the `expr_` expression even when assertions are disabled.\n*\n* @details\n* Like the DBC_ASSERT() macro, except it **always** evaluates the\n* `expr_` expression even when DBC assertions are disabled with the\n* #DBC_DISABLE macro.\n*\n* @param[in] label_ numeric label of the assertion (unique within the module)\n* @param[in] expr_  Boolean expression to check\n*/\n#define DBC_ALLEGE(label_, expr_) DBC_ASSERT(label_, expr_)\n\n/*! Assertion for a wrong path through the code\n*\n* @details\n* Calls the DBC_fault_handler() callback if ever executed. This assertion\n* takes the user-supplied parameter `id_` to identify the location of\n* this assertion within the file. This avoids the volatility of using\n* line numbers, which change whenever a line of code is added or removed\n* upstream from the assertion.\n*\n* @param[in] label_ numeric label of the assertion (unique within the module)\n*/\n#define DBC_ERROR(label_) DBC_fault_handler(&DBC_module_name_[0], (label_))\n\n/*! Assertion for checking preconditions.\n*\n* @details\n* Equivalent to DBC_ASSERT(), except the name provides a better\n* documentation of the intention of this assertion.\n*\n* @param[in] label_ numeric label of the assertion (unique within the module)\n* @param[in] expr_  Boolean expression to check\n*\n* @note\n* The `expr_` expression is **not** evaluated if assertions are\n* disabled with the ::DBC_DISABLE switch.\n*/\n#define DBC_REQUIRE(label_, expr_)  DBC_ASSERT((label_), (expr_))\n\n/*! Assertion for checking postconditions.\n*\n* @details\n* Equivalent to DBC_ASSERT(), except the name provides a better\n* documentation of the intention of this assertion.\n*\n* @param[in] label_ numeric label of the assertion (unique within the module)\n* @param[in] expr_  Boolean expression to check\n*\n* @note\n* The `expr_` expression is **not** evaluated if assertions are\n* disabled with the ::DBC_DISABLE switch.\n*/\n#define DBC_ENSURE(label_, expr_) DBC_ASSERT((label_), (expr_))\n\n/*! Assertion for checking invariants.\n*\n* @details\n* Equivalent to DBC_ASSERT(), except the name provides a better\n* documentation of the intention of this assertion.\n*\n* @param[in] label_ numeric label of the assertion (unique within the module)\n* @param[in] expr_  Boolean expression to check\n*\n* @note\n* The `expr_` expression is **not** evaluated if assertions are\n* disabled with the ::DBC_DISABLE switch.\n*/\n#define DBC_INVARIANT(label_, expr_)  DBC_ASSERT((label_), (expr_))\n\n#ifndef DBC_NORETURN\n#define DBC_NORETURN\n#endif\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/*! DBC assertion fault handler.\n*\n* @details\n* This is an application-specific callback function needs to be defined in\n* the application to perform the clean system shutdown and perhaps a reset.\n* The DBC_fault_handler() function is the last line of defense after the\n* system failure and its implementation should be very **carefully**\n* designed and **tested** under various fault conditions, including but\n* not limited to: stack overflow, stack corruption, or calling\n* DBC_fault_handler() from ISRs.\n\n* @param[in] module name of the file/module in which the assertion failed\n*                   (constant, zero-terminated C string)\n* @param[in] label  unique label of the assertion within the module.\n*                   This could be a line number or a user-defined label.\n*\n* @returns\n* This callback function should **not return** (see #NORETURN),\n* as continuation after an assertion failure does not make sense.\n*\n* @note\n* It is typically a **bad idea** to implement DBC_fault_handler() as an\n* endless loop that ties up the CPU. During debugging, DBC_fault_handler()\n* is an ideal place to put a breakpoint.\n*/\nDBC_NORETURN void DBC_fault_handler(char const * module, int label);\n\n#ifdef __cplusplus\n}\n#endif\n\n/* Inactive DbC macros -----------------------------------------------------*/\n#else\n\n#define DBC_MODULE_NAME(dummy_)\n#define DBC_ASSERT(label_, expr_)      ((void)0)\n#define DBC_ERROR(label_)              ((void)0)\n#define DBC_REQUIRE(label_, expr_)  ((void)0)\n#define DBC_ENSURE(label_, expr_) ((void)0)\n#define DBC_INVARIANT(label_, expr_)  ((void)0)\n#define DBC_ALLEGE(label_, expr_)      ((void)(expr_))\n\n#endif /* Inactive DBC macros */\n\n#endif /* DBC_ASSERT_ */\n"
  },
  {
    "path": "include/sst.h",
    "content": "/*===========================================================================\n* Super-Simple Tasker (SST/C) API\n*\n* Copyright (C) 2005-2023 Quantum Leaps, <state-machine.com>.\n*\n* SPDX-License-Identifier: MIT\n*\n* Permission is hereby granted, free of charge, to any person obtaining a\n* copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included in\n* all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n===========================================================================*/\n#ifndef SST_H_\n#define SST_H_\n\n#include <stdint.h>   /* standard C99 integers */\n#include <stdbool.h>  /* standard C99 Boolean */\n#include \"sst_port.h\" /* SST port for specific CPU */\n\n/* SST Event facilities ----------------------------------------------------*/\n/*! signal of SST event */\ntypedef uint16_t SST_Signal;\n\n/*! SST event class */\ntypedef struct {\n    SST_Signal sig;\n} SST_Evt;\n\n/*! macro for downcasting SST events to specific Evt \"subclasses\" */\n#define SST_EVT_DOWNCAST(EVT_, e_) ((EVT_ const *)(e_))\n\n/* SST Task facilities -----------------------------------------------------*/\ntypedef struct SST_Task SST_Task; /* forward declaration */\n\n/*! SST Task priority */\ntypedef uint8_t SST_TaskPrio;\n\n/*! SST internal event-queue counter */\ntypedef uint8_t SST_QCtr;\n\n/*! generic handler signature */\ntypedef void (*SST_Handler)(SST_Task * const me, SST_Evt const * const e);\n\n/*! SST task (a.k.a. \"Active Object\") */\nstruct SST_Task {\n    SST_Handler init;\n    SST_Handler dispatch;\n\n    SST_Evt const **qBuf; /*!< ring buffer for the queue */\n    SST_QCtr end;   /*!< last index into the ring buffer */\n    SST_QCtr head;  /*!< index for inserting events */\n    SST_QCtr tail;  /*!< index for removing events */\n    SST_QCtr nUsed; /*!< # used entries currently in the queue */\n\n#ifdef SST_PORT_TASK_ATTR\n    SST_PORT_TASK_ATTR\n#endif\n};\n\nvoid SST_Task_ctor(\n    SST_Task * const me,\n    SST_Handler init,\n    SST_Handler dispatch);\n\nvoid SST_Task_start(\n    SST_Task * const me,\n    SST_TaskPrio prio,\n    SST_Evt const **qBuf, SST_QCtr qLen,\n    SST_Evt const * const ie);\n\nvoid SST_Task_post(SST_Task * const me, SST_Evt const * const e);\n\nint  SST_Task_run(void); /* run SST tasks static */\n\n#ifdef SST_PORT_TASK_OPER\n    /* additional Task operations needed by the specific SST port */\n    SST_PORT_TASK_OPER\n#endif\n\n/* lock the SST task scheduler up to the provided priority ceiling (SRP) */\nSST_LockKey SST_Task_lock(SST_TaskPrio ceiling);\n\n/* unlock the SST task scheduler with the provided lock key */\nvoid SST_Task_unlock(SST_LockKey lock_key);\n\n/* SST Time Event facilities -----------------------------------------------*/\n/*! SST internal time-event tick counter */\ntypedef uint16_t SST_TCtr;\n\n/*! SST time event class */\ntypedef struct SST_TimeEvt SST_TimeEvt;\nstruct SST_TimeEvt {\n    SST_Evt super;\n\n    SST_TimeEvt *next; /*! link to next time event in a link-list */\n    SST_Task *task;    /*! the owner task to post time event to */\n    SST_TCtr ctr;      /*! time event down-counter */\n    SST_TCtr interval; /*! interval for periodic time event */\n};\n\nvoid SST_TimeEvt_ctor(\n    SST_TimeEvt * const me,\n    SST_Signal sig,\n    SST_Task *task);\n\nvoid SST_TimeEvt_arm(\n    SST_TimeEvt * const me,\n    SST_TCtr ctr,\n    SST_TCtr interval);\n\nbool SST_TimeEvt_disarm(\n    SST_TimeEvt * const me);\n\nvoid SST_TimeEvt_tick(void); /* static handle all instantiated time events */\n\n/* SST Kernel facilities ---------------------------------------------------*/\nvoid SST_init(void);\nvoid SST_start(void);\nvoid SST_onStart(void);\n\n/* general convenience utilities -------------------------------------------*/\n#ifndef ARRAY_NELEM\n/*! convenience macro to provide the number of elements in the array a_ */\n#define ARRAY_NELEM(a_)  (sizeof(a_) / sizeof((a_)[0]))\n#endif /* ARRAY_NELEM */\n\n#endif /* SST_H_ */\n"
  },
  {
    "path": "include/sst.hpp",
    "content": "//============================================================================\n// Super-Simple Tasker (SST/C++)\n//\n// Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n//\n// SPDX-License-Identifier: MIT\n//\n// Permission is hereby granted, free of charge, to any person obtaining a\n// copy of this software and associated documentation files (the \"Software\"),\n// to deal in the Software without restriction, including without limitation\n// the rights to use, copy, modify, merge, publish, distribute, sublicense,\n// and/or sell copies of the Software, and to permit persons to whom the\n// Software is furnished to do so, subject to the following conditions:\n//\n// The above copyright notice and this permission notice shall be included in\n// all copies or substantial portions of the Software.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n// DEALINGS IN THE SOFTWARE.\n//============================================================================\n#ifndef SST_HPP_\n#define SST_HPP_\n\n#include <cstdint>      // standard integer types\n#include \"sst_port.hpp\" // SST port for specific CPU\n\nnamespace SST {\n\n// SST Event facilities ------------------------------------------------------\n//! signal of SST event\nusing Signal = std::uint16_t;\n\nstruct Evt {\n    Signal sig;\n};\n\n// template for downcasting SST events to specific Evt \"subclasses\"\ntemplate<typename EVT_>\nEVT_ const *evt_downcast(Evt const *e) {\n    return reinterpret_cast<EVT_ const *>(e);\n}\n\n// SST Task facilities -------------------------------------------------------\n\n//! SST Task priority\nusing TaskPrio = std::uint8_t;\n\n//! SST internal event-queue counter\nusing QCtr = std::uint8_t;\n\n//! SST Task (a.k.a. \"Active Object\")\nclass Task {\nprivate:\n    Evt const **m_qBuf; //!< ring buffer for the queue\n    QCtr m_end;   //!< last index in the ring buffer\n    QCtr m_head;  //!< index for inserting events\n    QCtr m_tail;  //!< index for removing events\n    QCtr m_nUsed; //!< # used entries currently in the queue\n\n#ifdef SST_PORT_TASK_ATTR\n    SST_PORT_TASK_ATTR\n#endif\n\npublic:\n    void start(\n        TaskPrio prio,\n        Evt const **qBuf, QCtr qLen,\n        Evt const * const ie);\n\n    void post(Evt const * const e) noexcept;\n\n    virtual void init(Evt const * const ie) = 0;\n    virtual void dispatch(Evt const * const e) = 0;\n\n    static LockKey lock(TaskPrio ceiling);\n    static void unlock(LockKey key);\n\n    static int run(void);\n\n#ifdef SST_PORT_TASK_OPER\n    // additional Task operations needed by the specific SST port\n    SST_PORT_TASK_OPER\n#endif\n};\n\n// SST Time Event facilities -------------------------------------------------\n//! SST internal time-event tick counter\nusing TCtr = std::uint16_t;\n\n//! SST time event class\nclass TimeEvt : public Evt {\nprivate:\n    TimeEvt *m_next; //! link to next time event in a link-list\n    Task *m_task;    //! the owner task to post time event to\n    TCtr m_ctr;      //! time event down-counter\n    TCtr m_interval; //! interval for periodic time event\n\npublic:\n    TimeEvt(Signal sig, Task *task);\n    void arm(TCtr ctr, TCtr interval);\n    bool disarm(void);\n\n    static void tick(void);\n};\n\n// SST Kernel facilities -----------------------------------------------------\nvoid init(void);\nvoid start(void);\nvoid onStart(void);\nvoid onIdle(void);\n\n} // namespace SST\n\n// general convenience utilities ---------------------------------------------\n#ifndef ARRAY_NELEM\n//! convenience macro to provide the number of elements in the array a_\n#define ARRAY_NELEM(a_)  (sizeof(a_) / sizeof((a_)[0]))\n#endif /* ARRAY_NELEM */\n\n#endif // SST_HPP_\n"
  },
  {
    "path": "legacy/README.md",
    "content": "## Brought to you by:\n[![Quantum Leaps](https://www.state-machine.com/attachments/logo_ql_400.png)](https://www.state-machine.com)\n\n---------------------------------------------------------------------\n# Super-Simple Tasker version 1.0, July 2006\n\nSuper-Simple Tasker (SST) is a **preemptive, priority-based RTOS kernel**\nfully compatible with the requirements of Rate Monotonic Analysis/Scheduling\n(RMA/RMS). This sub-directory contains the origianl, historic SST article\nand code, as published in 2006.\n\n[![Build a Super-Simple Tasker Article](img/sst1_2006.png)](Super-Simple-Tasker.pdf)\n\n# Build a Super Simple Tasker\n## Miro Samek and Robert Ward (July, 2006)\n\n[\"Build a Super-Simple Tasker\"](Super-Simple-Tasker.pdf) was\na cover story article published originally in\n[Embedded Systems Design](https://www.embedded.com/embedded-systems-design-july-2006)\nmagazine in July 2006.\n\n\n# Licensing\nThe SST source code and examples are released under the terms of the\npermissive [MIT open source license](../LICENSE). Please note that the\nattribution clause in the MIT license requires you to preserve the\noriginal copyright notice in all changes and derivate works.\n\n\n# Files and Directories\nThe <sst> code repository the following subdirectories and files:\n\n```\n<sst>\\\n  |\n  +-README.md        - this file\n  |\n  +-LICENSE          - the GNU General Public License\n  |\n  +-example\\         - subdirectory containing the SST example files\n  | |\n  | +-bin\\           - contains .OBJ, .EXE, and .MAP files\n  | +-bsp.c          - Board Support Package for DOS/Turbo C++ 1.01\n  | +-bsp.h          - BSP header file\n  | +-kbd_task.c     - The keyboard task function\n  | +-main.c         - The main function\n  | +-sst_exa.h      - The header file for the SST example application\n  | +-sst_exa.prj    - The Turbo C++ project file for building and\n  | |                  debugging the SST example application from the\n  | |                  Turbo C++ IDE\n  | +-sst_port.h     - SST port to DOS/Turbo C++ 1.01\n  | +-stdint.h       - The C99 standard exact-width integer types\n  | |                  for the Turbo C++ 1.01, which is a pre-standard\n  | |                  compiler. You could copy this file to the\n  | |                  Turbo C++ include directory.\n  | +-tick_tsk.c     - The two tick tasks (tickTaskA and tickTaskB)\n  |\n  +-include\\         - subdirectory containing the SST public interface\n  | +-sst.h          - The platform-independent SST header file\n  |\n  +-source\\          - subdirectory containing the SST implementation\n    +-sst.c          - platform-independent SST implementation\n```\n\n\n# Running the SST Example\n![SST Running in DOS Window](img/sst1_fig05.png)\n\nThe executable file for the SST example is provided in\n<sst>\\example\\bin\\sst_exa.exe. You can run this executable on a\nWindows-based PC in a DOS emulator (e.g. DOSBox DOS emulator).\n\n> NOTE: The legacy DOS platform has been chosen for demonstrating SST, because\nit still allows programming with interrupts, directly manipulating CPU registers,\nand directly accessing I/O space of the processor (required for writing the EOI\ncommand to the 8259A interrupt controller). No other modern desktop development\nenvironment for the commodity PC allows this much so easily. The ubiquitous PC\nrunning under DOS (or a DOS emulator within any variant of Windows) is capable\nof demonstrating most key embedded features of SST.\n\nThe example program takes one command-line argument, which is the number of\niterations through a delay loop peppered throughout the application code.\nThe purpose of this delay is to extend the run-to-completion processing\n(which is really short on the fast modern PCs), and thus increase the probability\nof asynchronous preemptions. We’ve been using a typical value of this delay\naround 10000 on a modern 2GHz PC, which corresponds to the following invocation\nof the SST example application:\n\n`sst_exa.exe 10000`\n\nAs described in the article, you should not go overboard with this parameter\nbecause you can eventually overload the machine, and the SST will start losing\nevents (the queues will overflow and won’t accept new events).\n\nOnce the application starts running, you can generate asynchronous preemptions\nby typing on the keyboard. The keyboard interrupt is asynchronous with respect\nto the periodic time-tick interrupt and consequently the keyboard interrupt\ncan preempt the time tick tasks (that run just after the tick interrupt), and\nthe time tick interrupt can preempt the keyboard task (that runs just after\nthe keyboard interrupt). Moreover, the interrupts can also preempt each other.\nPlease note, however, that the tick ISR has the highest priority, and\nconsequently the Programmable Interrupt Controller (the 8259A chip) will not\nallow in hardware that the lower-priority keyboard ISR preempts the\nhighest-priority tick ISR. The only allowed interrupt preemption is that tick\nISR preempts the keyboard ISR. You should verify this by observing the\n“Preemptions” column of the application display.\n\nAfter typing for a while on the keyboard, you should see some cases of the\nasynchronous preemption in the “Preemptions” column. The synchronous\npreemptions are not displayed, but they occur every time a keyboard task posts\nan event to the higher-priority tickTaskB(). On the other hand, the\nsynchronous preemption does not occur when the keyboard task posts an event to\nthe lower-priority tickTaskA().\n\n\n# Legacy DOS Compiler\nIn order to modify and recompile the example, you need to download and install\na legacy DOS compiler, such as Turbo C++ 1.01, which is available for a free download\nfrom the Borland Museum at\nhttp://bdn.borland.com/article/0,1410,21751,00.html.\n\nTo install Borland Turbo C++ 1.01, download the file TCPP101.ZIP from the\nBorland Museum and unzip it into a temporary directory. Run the INSTALL.EXE\nprogram and follow the installation instructions.\n\nMiro Samek<br>\nApril 24, 2006\n\n\n# Updates and Support for Modern Microcontrollers\nAs described in the article, SST-type kernel is ideal for deterministic\nRun-To-Completion (RTC) execution of concurrent state machines. The website\nhttps://www.state-machine.com provides an implementation of the RTC kernel, called\n**QK** (\"Quantum Kernel\") that works exactly like SST and only differs in the way it\nis integrated with the [QP Real-Time Embedded Frameworks (RTEFs)](https://www.state-machine.com/products).\nQK has been ported to many embedded CPUs, such as: **ARM Cortex-M** (M0-M7), MSP430, PIC24/dsPIC, PIC32, etc.\n\n<br>\nOctober 14, 2011\n"
  },
  {
    "path": "legacy/example/STDINT.H",
    "content": "/*      stdint.h\n\n        WG14/N843 C99 Standard, Section 7.18\n\n        This header is part of the ANSI C99 standard library.\n        It describes a number of useful integer types.\n        This file is not part of the original Borland Turbo C++ 1.01\n        distribution, which preceded the C99 standard.\n \n        Currently, this file contains only the exact-width integer\n        types and constants (see C99 Section 7.18.1.1)\n*/\n\n#ifndef __STDINT_H\n#define __STDINT_H\n\n#ifdef  __cplusplus\nextern \"C\" {\n#endif\n\n/* Exact-width types. WG14/N843 C99 Standard, Section 7.18.1.1 */\ntypedef signed   char  int8_t;\ntypedef signed   int   int16_t;\ntypedef signed   long  int32_t;\ntypedef unsigned char  uint8_t;\ntypedef unsigned int   uint16_t;\ntypedef unsigned long  uint32_t;\n\n#ifdef  __cplusplus\n}\n#endif\n\n#endif\n"
  },
  {
    "path": "legacy/example/bsp.c",
    "content": "/*****************************************************************************\n* Product: SST example, 80x86, Turbo C++ 1.01\n*\n* Copyright (C) 2006 Miro Samek and Robert Ward. All rights reserved.\n*\n* MIT License\n*\n* Permission is hereby granted, free of charge, to any person obtaining\n* a copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included\n* in all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n*****************************************************************************/\n#include \"sst_port.h\"\n#include \"sst_exa.h\"\n#include \"bsp.h\"\n\n#include <stdlib.h>                                          /* for _exit() */\n\n/* Local-scope objects -----------------------------------------------------*/\nstatic void interrupt (*l_dosTickISR)();\nstatic void interrupt (*l_dosKbdISR)();\n\n#define TICKS_PER_SEC   200\n\n#define TICK_VECTOR     0x08\n#define KBD_VECTOR      0x09\n\nstatic void displayPreemptions(uint8_t pprev, uint8_t pnext);\n\n/*..........................................................................*/\nstatic void interrupt tickISR() {\n    uint8_t pin;\n    displayPreemptions(SST_currPrio_, TICK_ISR_PRIO);/* for testing, NOTE01 */\n    SST_ISR_ENTRY(pin, TICK_ISR_PRIO);\n\n    SST_post(TICK_TASK_A_PRIO, TICK_SIG, 0);     /* post the Tick to Task A */\n    SST_post(TICK_TASK_B_PRIO, TICK_SIG, 0);     /* post the Tick to Task B */\n\n    busyDelay();                                 /* for testing, see NOTE02 */\n    SST_ISR_EXIT(pin, outportb(0x20, 0x20));\n}\n/*..........................................................................*/\nstatic void interrupt kbdISR() {\n    uint8_t pin;\n    uint8_t key = inport(0x60);/*get scan code from the 8042 kbd controller */\n\n    displayPreemptions(SST_currPrio_, KBD_ISR_PRIO); /* for testing, NOTE01 */\n    SST_ISR_ENTRY(pin, KBD_ISR_PRIO);\n\n    SST_post(KBD_TASK_PRIO, KBD_SIG, key);   /* post the Key to the KbdTask */\n\n    busyDelay();                                 /* for testing, see NOTE02 */\n    SST_ISR_EXIT(pin, outportb(0x20, 0x20));\n}\n/*..........................................................................*/\nvoid SST_init(void) {\n}\n/*..........................................................................*/\nvoid SST_start(void) {\n                                      /* divisor for the 8254 timer/counter */\n    uint16_t count = (uint16_t)(((1193180 * 2) / TICKS_PER_SEC + 1) >> 1);\n\n                                       /* save the original DOS vectors ... */\n    l_dosTickISR = getvect(TICK_VECTOR);\n    l_dosKbdISR  = getvect(KBD_VECTOR);\n\n    SST_INT_LOCK();                                  /* lock the interrupts */\n    outportb(0x43, 0x36);             /* use mode-3 for timer 0 in the 8254 */\n    outportb(0x40, count & 0xFF);              /* load low  byte of timer 0 */\n    outportb(0x40, (count >> 8) & 0xFF);       /* load high byte of timer 0 */\n    setvect(TICK_VECTOR, &tickISR);\n    setvect(KBD_VECTOR, &kbdISR);\n    SST_INT_UNLOCK();                              /* unlock the interrupts */\n}\n/*..........................................................................*/\nvoid SST_onIdle(void) {\n    static uint32_t onIdleCtr;\n    Video_printNumAt(22,  19, VIDEO_FGND_YELLOW, ++onIdleCtr);\n}\n/*..........................................................................*/\nvoid SST_exit(void) {\n    SST_INT_LOCK();                                  /* lock the interrupts */\n    outportb(0x43, 0x36);             /* use mode-3 for timer 0 in the 8254 */\n    outportb(0x40, 0);                         /* load low  byte of timer 0 */\n    outportb(0x40, 0);                         /* load high byte of timer 0 */\n                                    /* restore the original DOS vectors ... */\n    setvect(TICK_VECTOR, l_dosTickISR);\n    setvect(KBD_VECTOR, l_dosKbdISR);\n    SST_INT_UNLOCK();                              /* unlock the interrupts */\n    _exit(0);                                                /* exit to DOS */\n}\n\n/*--------------------------------------------------------------------------*/\nvoid displayPreemptions(uint8_t pprev, uint8_t pnext) {\n    if (pnext == TICK_ISR_PRIO) {\n        static uint32_t tmrIsrCtr;               /* timer interrupt counter */\n        Video_printNumAt(22,  7, VIDEO_FGND_YELLOW, ++tmrIsrCtr);\n    }\n    else if (pnext == KBD_ISR_PRIO) {\n        static uint32_t kbdIsrCtr;                 /* kbd interrupt counter */\n        Video_printNumAt(22,  8, VIDEO_FGND_YELLOW, ++kbdIsrCtr);\n    }\n\n    if (pprev == TICK_ISR_PRIO) {           /* is this Tick ISR preemption? */\n        static uint32_t tickPreCtr;          /* Tick ISR preemption counter */\n        Video_printNumAt(30,  7, VIDEO_FGND_YELLOW, ++tickPreCtr);\n    }\n    else if (pprev == KBD_ISR_PRIO) {        /* is this kbd ISR preemption? */\n        static uint32_t kbdPreCtr;            /* kbd ISR preemption counter */\n        Video_printNumAt(30,  8, VIDEO_FGND_YELLOW, ++kbdPreCtr);\n    }\n    else {                                     /* must be a task preemption */\n        static uint32_t preCtr[SST_MAX_PRIO + 2];\n        Video_printNumAt(30, 19 - pprev, VIDEO_FGND_YELLOW,\n                         ++preCtr[pprev]);\n    }\n}\n/*--------------------------------------------------------------------------*/\nvoid Video_clearScreen(uint8_t bgColor) {\n    clrscr();\n    Video_clearRect(0,  0, 80, 25, bgColor);\n}\n/*..........................................................................*/\nvoid Video_clearRect(uint8_t x1, uint8_t y1, uint8_t x2, uint8_t y2,\n                     uint8_t bgColor)\n{\n    for ( ; y1 < y2; ++y1) {\n        uint8_t x;\n        uint8_t far *pscr = (uint8_t far *)MK_FP(0xB800,\n                                           (uint16_t)(((y1 * 80) + x1) * 2));\n        for (x = x1; x < x2; ++x) {\n            pscr[0] = ' ';                    /* Put space in the video RAM */\n            pscr[1] = bgColor;      /* Put video attribute in the video RAM */\n            pscr += 2;\n        }\n    }\n}\n/*..........................................................................*/\nvoid Video_printChAt(uint8_t x, uint8_t y, uint8_t color, char ch) {\n                               /* calculate position on the video RAM (VGA) */\n    uint8_t far *pscr = (uint8_t far *)MK_FP(0xB800,\n                                             (uint16_t)(((y * 80) + x) * 2));\n    pscr[0] = ch;\n    pscr[1] = color;\n}\n/*..........................................................................*/\nvoid Video_printStrAt(uint8_t x, uint8_t y, uint8_t color,\n                      char const *str)\n{\n                               /* calculate position on the video RAM (VGA) */\n    uint8_t far *pscr = (uint8_t far *)MK_FP(0xB800,\n                                             (uint16_t)(((y * 80) + x) * 2));\n    while (*str != (uint8_t)0) {\n        pscr[0] = *str++;                     /* Put character in video RAM */\n        pscr[1] |= color;               /* Put video attribute in video RAM */\n        pscr += 2;\n    }\n}\n/*..........................................................................*/\nvoid Video_printNumAt(uint8_t x, uint8_t y, uint8_t color, uint32_t num) {\n    char buf[4];\n    buf[3] = (char)0;\n    buf[2] = (char)('0' + num % 10);\n    num /= 10;\n    buf[1] = (char)('0' + num % 10);\n    num /= 10;\n    buf[0] = (char)('0' + num % 10);\n    if (buf[0] == '0') {\n        buf[0] = ' ';\n    }\n    Video_printStrAt(x, y, color, buf);\n}\n\n/*****************************************************************************\n* NOTE01:\n* The function call to displayPreemptions() is added only to monitor the\n* \"asynchronous\" preemptions within the SST.\n*\n* NOTE02:\n* The call to busyDelay() is added only to extend the execution time\n* to increase the chance of an \"asynchronous\" preemption.\n*/\n"
  },
  {
    "path": "legacy/example/bsp.h",
    "content": "/*****************************************************************************\n* Product: SST example, 80x86, Turbo C++ 1.01\n*\n* Copyright (C) 2006 Miro Samek and Robert Ward. All rights reserved.\n*\n* MIT License\n*\n* Permission is hereby granted, free of charge, to any person obtaining\n* a copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included\n* in all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n*****************************************************************************/\n#ifndef bsp_h\n#define bsp_h\n\n/* Direct Video Access .....................................................*/\nenum VideoColor {\n    /* foreground */\n    VIDEO_FGND_BLACK        = 0x00,\n    VIDEO_FGND_BLUE         = 0x01,\n    VIDEO_FGND_GREEN        = 0x02,\n    VIDEO_FGND_CYAN         = 0x03,\n    VIDEO_FGND_RED          = 0x04,\n    VIDEO_FGND_PURPLE       = 0x05,\n    VIDEO_FGND_BROWN        = 0x06,\n    VIDEO_FGND_LIGHT_GRAY   = 0x07,\n    VIDEO_FGND_DARK_GRAY    = 0x08,\n    VIDEO_FGND_LIGHT_BLUE   = 0x09,\n    VIDEO_FGND_LIGHT_GREEN  = 0x0A,\n    VIDEO_FGND_LIGHT_CYAN   = 0x0B,\n    VIDEO_FGND_LIGHT_RED    = 0x0C,\n    VIDEO_FGND_LIGHT_PURPLE = 0x0D,\n    VIDEO_FGND_YELLOW       = 0x0E,\n    VIDEO_FGND_WHITE        = 0x0F,\n    /* background */\n    VIDEO_BGND_BLACK        = 0x00,\n    VIDEO_BGND_BLUE         = 0x10,\n    VIDEO_BGND_GREEN        = 0x20,\n    VIDEO_BGND_CYAN         = 0x30,\n    VIDEO_BGND_RED          = 0x40,\n    VIDEO_BGND_PURPLE       = 0x50,\n    VIDEO_BGND_BROWN        = 0x60,\n    VIDEO_BGND_LIGHT_GRAY   = 0x70,\n\n    VIDEO_BGND_BLINK        = 0x80\n};\n/*..........................................................................*/\nvoid Video_clearScreen(uint8_t bgColor);\nvoid Video_clearRect(uint8_t x1, uint8_t y1, uint8_t x2, uint8_t y2,\n                     uint8_t bgColor);\nvoid Video_printChAt(uint8_t x, uint8_t y, uint8_t color, char ch);\nvoid Video_printStrAt(uint8_t x, uint8_t y, uint8_t color,\n                      char const *str);\nvoid Video_printNumAt(uint8_t x, uint8_t y, uint8_t color, uint32_t num);\n\n#endif                                                             /* bsp_h */\n\n"
  },
  {
    "path": "legacy/example/kbd_tsk.c",
    "content": "/*****************************************************************************\n* Product: SST example, 80x86, Turbo C++ 1.01\n*\n* Copyright (C) 2006 Miro Samek and Robert Ward. All rights reserved.\n*\n* MIT License\n*\n* Permission is hereby granted, free of charge, to any person obtaining\n* a copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included\n* in all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n*****************************************************************************/\n#include \"sst_port.h\"\n#include \"sst_exa.h\"\n#include \"bsp.h\"\n\n/*..........................................................................*/\nvoid kbdTask(SSTEvent e) {\n    static uint32_t kbdTaskCtr;\n\n    Video_printNumAt(22, 19 - KBD_TASK_PRIO, VIDEO_FGND_YELLOW, ++kbdTaskCtr);\n    busyDelay();                                     /* for testing, NOTE01 */\n\n    switch (e.sig) {\n        case INIT_SIG: {\n            Video_printStrAt( 1, 19 - KBD_TASK_PRIO,\n                             VIDEO_FGND_WHITE, \"kbdTask\");\n            break;\n        }\n        case KBD_SIG: {\n            if (e.par == (SSTParam)0x81) {          /* is this the ESC key? */\n                SST_exit();\n            }\n            else if ((e.par & 1) != 0) {      /* pick one of the Tick Tasks */\n                SST_post(TICK_TASK_A_PRIO,     /* no synchronous preemption */\n                         COLOR_SIG, e.par & 0xF);\n            }\n            else {\n                SST_post(TICK_TASK_B_PRIO,        /* synchronous preemption */\n                         COLOR_SIG, (e.par & 0xF));\n            }\n            break;\n        }\n    }\n}\n\n/*****************************************************************************\n* NOTE01:\n* The call to busyDelay() is added only to extend the execution time\n* to increase the chance of an \"asynchronous\" preemption.\n*/\n"
  },
  {
    "path": "legacy/example/main.c",
    "content": "/*****************************************************************************\n* Product: SST example, 80x86, Turbo C++ 1.01\n*\n* Copyright (C) 2006 Miro Samek and Robert Ward. All rights reserved.\n*\n* MIT License\n*\n* Permission is hereby granted, free of charge, to any person obtaining\n* a copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included\n* in all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n*****************************************************************************/\n#include \"sst_port.h\"\n#include \"sst_exa.h\"\n#include \"bsp.h\"\n\n#include <stdlib.h>                                           /* for atol() */\n\nstatic void setupScreen(void);\nstatic SSTEvent tickTaskAQueue[2];\nstatic SSTEvent tickTaskBQueue[2];\nstatic SSTEvent kbdTaskQueue[2];\n\nstatic uint32_t l_delayCtr = 0UL;\n\n/*..........................................................................*/\nint main(int argc, char *argv[]) {\n\n    if (argc > 1) {                                     /* delay specified? */\n        l_delayCtr = atol(argv[1]);\n    }\n\n    setupScreen();                                      /* setup the screen */\n\n    SST_init();                                       /* initialize the SST */\n\n    SST_task(&tickTaskA, TICK_TASK_A_PRIO,\n            tickTaskAQueue, sizeof(tickTaskAQueue)/sizeof(tickTaskAQueue[0]),\n            INIT_SIG, 0);\n\n    SST_task(&tickTaskB, TICK_TASK_B_PRIO,\n            tickTaskBQueue, sizeof(tickTaskBQueue)/sizeof(tickTaskBQueue[0]),\n            INIT_SIG, 0);\n\n    SST_task(&kbdTask, KBD_TASK_PRIO,\n             kbdTaskQueue, sizeof(kbdTaskQueue)/sizeof(kbdTaskQueue[0]),\n             INIT_SIG, 0);\n\n    SST_run();                                   /* run the SST application */\n    return 0;\n}\n/*..........................................................................*/\nstatic void setupScreen(void) {\n    Video_clearScreen(VIDEO_BGND_BLACK);\n    Video_clearRect( 0,  5, 80,  6, VIDEO_BGND_LIGHT_GRAY);\n    Video_clearRect( 0,  6, 40, 23, VIDEO_BGND_BLUE);\n    Video_clearRect(40,  6, 80, 23, VIDEO_BGND_RED);\n    Video_clearRect(43,  8, 77, 21, VIDEO_BGND_BLACK);\n    Video_clearRect( 0, 23, 80, 24, VIDEO_BGND_LIGHT_GRAY);\n\n    Video_printStrAt(31,  2, VIDEO_FGND_YELLOW,\n                     \"Super Simple Tasker\");\n\n    Video_printStrAt( 0,  5, VIDEO_FGND_BLUE,\n                     \" Task      Priority  Calls  Preemptions\");\n    Video_printStrAt( 1,  7, VIDEO_FGND_WHITE,  \"tickISR   255\");\n    Video_printStrAt( 1,  8, VIDEO_FGND_WHITE,  \"kbdISR    254\");\n\n    Video_printStrAt( 1, 10, VIDEO_FGND_WHITE,  \"schedLock   9\");\n    Video_printStrAt( 1, 11, VIDEO_FGND_WHITE,  \"task8       8\");\n    Video_printStrAt( 1, 12, VIDEO_FGND_WHITE,  \"task7       7\");\n    Video_printStrAt( 1, 13, VIDEO_FGND_WHITE,  \"task6       6\");\n    Video_printStrAt( 1, 14, VIDEO_FGND_WHITE,  \"task5       5\");\n    Video_printStrAt( 1, 15, VIDEO_FGND_WHITE,  \"task4       4\");\n    Video_printStrAt( 1, 16, VIDEO_FGND_WHITE,  \"task3       3\");\n    Video_printStrAt( 1, 17, VIDEO_FGND_WHITE,  \"task2       2\");\n    Video_printStrAt( 1, 18, VIDEO_FGND_WHITE,  \"task1       1\");\n    Video_printStrAt( 1, 19, VIDEO_FGND_WHITE,  \"idle Loop   0\");\n\n    Video_printStrAt(4, 23, VIDEO_FGND_BLUE,\n         \"* Copyright (c) 2006 Quantum Leaps, LLC \"\n         \"* www.quantum-leaps.com *\");\n    Video_printStrAt(28, 24, VIDEO_FGND_LIGHT_RED,\n         \"<< Press Esc to quit >>\");\n}\n/*..........................................................................*/\nvoid busyDelay(void) {\n    volatile uint32_t i = l_delayCtr;\n    while (i-- > 0) {\n    }\n}\n"
  },
  {
    "path": "legacy/example/sst_exa.h",
    "content": "/*****************************************************************************\n* Product: SST example, 80x86, Turbo C++ 1.01\n*\n* Copyright (C) 2006 Miro Samek and Robert Ward. All rights reserved.\n*\n* MIT License\n*\n* Permission is hereby granted, free of charge, to any person obtaining\n* a copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included\n* in all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n*****************************************************************************/\n#ifndef sst_exa_h\n#define sst_exa_h\n\nvoid tickTaskA(SSTEvent e);\nvoid tickTaskB(SSTEvent e);\nvoid kbdTask(SSTEvent e);\n\nenum Events {                         /* the events used in the application */\n    INIT_SIG,                                       /* initialization event */\n    TICK_SIG,\n    KBD_SIG,\n    COLOR_SIG\n};\n\nenum SSTPriorities {     /* the SST priorities don't need to be consecutive */\n    /* task priorities... */\n    TICK_TASK_A_PRIO = 2,\n    KBD_TASK_PRIO    = 5,\n    TICK_TASK_B_PRIO = 7,\n\n    /* ISR priorities... */\n    KBD_ISR_PRIO     = 0xFF - 1,\n    TICK_ISR_PRIO    = 0xFF\n};\n\n#endif                                                         /* sst_exa_h */\n\n"
  },
  {
    "path": "legacy/example/sst_port.h",
    "content": "/*****************************************************************************\n* Product: SST example, 80x86, Turbo C++ 1.01\n*\n* Copyright (C) 2006 Miro Samek and Robert Ward. All rights reserved.\n*\n* MIT License\n*\n* Permission is hereby granted, free of charge, to any person obtaining\n* a copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included\n* in all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n*****************************************************************************/\n#ifndef sst_port_h\n#define sst_port_h\n\n                                         /* SST interrupt locking/unlocking */\n#define SST_INT_LOCK()   disable()\n#define SST_INT_UNLOCK() enable()\n                                               /* maximum SST task priority */\n#define SST_MAX_PRIO     8\n\n#include <dos.h>                  /* for declarations of disable()/enable() */\n#undef outportb /*don't use the macro because it has a bug in Turbo C++ 1.01*/\n\n#include \"sst.h\"                      /* SST platform-independent interface */\n\n#endif                                                        /* sst_port_h */\n\n"
  },
  {
    "path": "legacy/example/tick_tsk.c",
    "content": "/*****************************************************************************\n* Product: SST example, 80x86, Turbo C++ 1.01\n*\n* Copyright (C) 2006 Miro Samek and Robert Ward. All rights reserved.\n*\n* MIT License\n*\n* Permission is hereby granted, free of charge, to any person obtaining\n* a copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included\n* in all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n*****************************************************************************/\n#include \"sst_port.h\"\n#include \"sst_exa.h\"\n#include \"bsp.h\"\n\n#include <stdlib.h>                                         /* for random() */\n\n/*..........................................................................*/\nvoid tickTaskA(SSTEvent e) {\n    static uint32_t tickTaskACtr;\n    static uint8_t colorA = VIDEO_BGND_LIGHT_GRAY;\n\n    Video_printNumAt(22, 19 - TICK_TASK_A_PRIO,\n                     VIDEO_FGND_YELLOW, ++tickTaskACtr);\n    busyDelay();                                     /* for testing, NOTE01 */\n\n    switch (e.sig) {\n        case INIT_SIG: {\n            Video_printStrAt( 1, 19 - TICK_TASK_A_PRIO,\n                              VIDEO_FGND_WHITE, \"tickTaskA\");\n            break;\n        }\n        case TICK_SIG: {\n            uint8_t x, y;\n            uint8_t mutex;\n\n            mutex = SST_mutexLock(TICK_TASK_B_PRIO); /* the other tick task */\n            x = random(34);\n            y = random(13);\n            SST_mutexUnlock(mutex);\n\n            Video_printChAt(x + 43, y + 8, colorA, 'A');\n            break;\n        }\n        case COLOR_SIG: {\n            colorA = e.par;          /* color is delivered in the parameter */\n            break;\n        }\n    }\n}\n/*..........................................................................*/\nvoid tickTaskB(SSTEvent e) {\n    static uint32_t tickTaskBCtr;\n    static uint8_t colorB = VIDEO_BGND_LIGHT_GRAY;\n\n    Video_printNumAt(22, 19 - TICK_TASK_B_PRIO,\n                     VIDEO_FGND_YELLOW, ++tickTaskBCtr);\n    busyDelay();                                     /* for testing, NOTE01 */\n\n    switch (e.sig) {\n        case INIT_SIG: {\n            Video_printStrAt( 1, 19 - TICK_TASK_B_PRIO,\n                              VIDEO_FGND_WHITE, \"tickTaskB\");\n            break;\n        }\n        case TICK_SIG: {\n            uint8_t x, y;\n            uint8_t mutex;\n\n            mutex = SST_mutexLock(TICK_TASK_A_PRIO); /* the other tick task */\n            x = random(34);\n            y = random(13);\n            SST_mutexUnlock(mutex);\n\n            Video_printChAt(x + 43, y + 8, colorB, 'B');\n            break;\n        }\n        case COLOR_SIG: {\n            colorB = e.par;          /* color is delivered in the parameter */\n            break;\n        }\n    }\n}\n\n/*****************************************************************************\n* NOTE01:\n* The call to busyDelay() is added only to extend the execution time\n* to increase the chance of an \"asynchronous\" preemption.\n*/\n"
  },
  {
    "path": "legacy/include/sst.h",
    "content": "/*****************************************************************************\n* SST platform-independent public interface\n*\n* Copyright (C) 2006 Miro Samek and Robert Ward. All rights reserved.\n*\n* MIT License\n*\n* Permission is hereby granted, free of charge, to any person obtaining\n* a copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included\n* in all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n*****************************************************************************/\n#ifndef sst_h\n#define sst_h\n\n#include <stdint.h>                 /* exact-width integer types, ANSI C'99 */\n\ntypedef uint8_t SSTSignal;\ntypedef uint8_t SSTParam;\n\ntypedef struct SSTEventTag SSTEvent;\nstruct SSTEventTag {\n    SSTSignal sig;\n    SSTParam  par;\n};\n\ntypedef void (*SSTTask)(SSTEvent e);\n\nvoid SST_init(void);\nvoid SST_task(SSTTask task, uint8_t prio, SSTEvent *queue, uint8_t qlen,\n              SSTSignal sig, SSTParam  par);\nvoid SST_start(void);\nvoid SST_run(void);\nvoid SST_onIdle(void);\nvoid SST_exit(void);\n\nuint8_t SST_post(uint8_t prio, SSTSignal sig, SSTParam  par);\n\nuint8_t SST_mutexLock(uint8_t prioCeiling);\nvoid SST_mutexUnlock(uint8_t orgPrio);\n\nvoid SST_schedule_(void);\n\n                                            /* SST interrupt entry and exit */\n#define SST_ISR_ENTRY(pin_, isrPrio_) do { \\\n    (pin_) = SST_currPrio_; \\\n    SST_currPrio_ = (isrPrio_); \\\n    SST_INT_UNLOCK(); \\\n} while (0)\n\n#define SST_ISR_EXIT(pin_, EOI_command_) do { \\\n    SST_INT_LOCK(); \\\n    (EOI_command_); \\\n    SST_currPrio_ = (pin_); \\\n    SST_schedule_(); \\\n} while (0)\n\n\n/* public-scope objects */\nextern uint8_t SST_currPrio_;     /* current priority of the executing task */\nextern uint8_t SST_readySet_;                              /* SST ready-set */\n\n#endif                                                             /* sst_h */\n"
  },
  {
    "path": "legacy/source/sst.c",
    "content": "/*****************************************************************************\n* SST platform-independent implementation\n*\n* Copyright (C) 2006 Miro Samek and Robert Ward. All rights reserved.\n*\n* MIT License\n*\n* Permission is hereby granted, free of charge, to any person obtaining\n* a copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included\n* in all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n*****************************************************************************/\n#include \"sst_port.h\"\n\n/* Public-scope objects ----------------------------------------------------*/\nuint8_t SST_currPrio_ = (uint8_t)0xFF;              /* current SST priority */\nuint8_t SST_readySet_ = (uint8_t)0;                        /* SST ready-set */\n\ntypedef struct TaskCBTag TaskCB;\nstruct TaskCBTag {\n    SSTTask task__;\n    SSTEvent *queue__;\n    uint8_t end__;\n    uint8_t head__;\n    uint8_t tail__;\n    uint8_t nUsed__;\n    uint8_t mask__;\n};\n\n/* Local-scope objects -----------------------------------------------------*/\nstatic TaskCB l_taskCB[SST_MAX_PRIO];\n\n/*..........................................................................*/\nvoid SST_task(SSTTask task, uint8_t prio, SSTEvent *queue, uint8_t qlen,\n              SSTSignal sig, SSTParam par)\n{\n    SSTEvent ie;                                    /* initialization event */\n    TaskCB *tcb  = &l_taskCB[prio - 1];\n    tcb->task__  = task;\n    tcb->queue__ = queue;\n    tcb->end__   = qlen;\n    tcb->head__  = (uint8_t)0;\n    tcb->tail__  = (uint8_t)0;\n    tcb->nUsed__ = (uint8_t)0;\n    tcb->mask__  = (1 << (prio - 1));\n    ie.sig = sig;\n    ie.par = par;\n    tcb->task__(ie);                                 /* initialize the task */\n}\n/*..........................................................................*/\nvoid SST_run(void) {\n    SST_start();                                              /* start ISRs */\n\n    SST_INT_LOCK();\n    SST_currPrio_ = (uint8_t)0;   /* set the priority for the SST idle loop */\n    SST_schedule_();                  /* process all events produced so far */\n    SST_INT_UNLOCK();\n\n    for (;;) {                                         /* the SST idle loop */\n        SST_onIdle();                        /* invoke the on-idle callback */\n    }\n}\n/*..........................................................................*/\nuint8_t SST_post(uint8_t prio, SSTSignal sig, SSTParam par) {\n    TaskCB *tcb = &l_taskCB[prio - 1];\n    SST_INT_LOCK();\n    if (tcb->nUsed__ < tcb->end__) {\n        tcb->queue__[tcb->head__].sig = sig;/* insert the event at the head */\n        tcb->queue__[tcb->head__].par = par;\n        if ((++tcb->head__) == tcb->end__) {\n            tcb->head__ = (uint8_t)0;                      /* wrap the head */\n        }\n        if ((++tcb->nUsed__) == (uint8_t)1) {           /* the first event? */\n            SST_readySet_ |= tcb->mask__;   /* insert task to the ready set */\n            SST_schedule_();            /* check for synchronous preemption */\n        }\n        SST_INT_UNLOCK();\n        return (uint8_t)1;                     /* event successfully posted */\n    }\n    else {\n        SST_INT_UNLOCK();\n        return (uint8_t)0;              /* queue full, event posting failed */\n    }\n}\n/*..........................................................................*/\nuint8_t SST_mutexLock(uint8_t prioCeiling) {\n    uint8_t p;\n    SST_INT_LOCK();\n    p = SST_currPrio_;               /* the original SST priority to return */\n    if (prioCeiling > SST_currPrio_) {\n        SST_currPrio_ = prioCeiling;              /* raise the SST priority */\n    }\n    SST_INT_UNLOCK();\n    return p;\n}\n/*..........................................................................*/\nvoid SST_mutexUnlock(uint8_t orgPrio) {\n    SST_INT_LOCK();\n    if (orgPrio < SST_currPrio_) {\n        SST_currPrio_ = orgPrio;    /* restore the saved priority to unlock */\n        SST_schedule_(); /* the scheduler unlocks the interrupts internally */\n    }\n    SST_INT_UNLOCK();\n}\n/*..........................................................................*/\n/* NOTE: the SST scheduler is entered and exited with interrupts LOCKED */\nvoid SST_schedule_(void) {\n    static uint8_t const log2Lkup[] = {\n        0, 1, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4,\n        5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,\n        6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,\n        6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,\n        7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,\n        7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,\n        7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,\n        7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,\n        8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,\n        8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,\n        8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,\n        8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,\n        8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,\n        8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,\n        8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,\n        8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8\n    };\n    uint8_t pin = SST_currPrio_;               /* save the initial priority */\n    uint8_t p;                                          /* the new priority */\n                            /* is the new priority higher than the initial? */\n    while ((p = log2Lkup[SST_readySet_]) > pin) {\n        TaskCB *tcb  = &l_taskCB[p - 1];\n                                          /* get the event out of the queue */\n        SSTEvent e = tcb->queue__[tcb->tail__];\n        if ((++tcb->tail__) == tcb->end__) {\n            tcb->tail__ = (uint8_t)0;\n        }\n        if ((--tcb->nUsed__) == (uint8_t)0) {/* is the queue becoming empty?*/\n            SST_readySet_ &= ~tcb->mask__;     /* remove from the ready set */\n        }\n        SST_currPrio_ = p;        /* this becomes the current task priority */\n        SST_INT_UNLOCK();                          /* unlock the interrupts */\n\n        (*tcb->task__)(e);                             /* call the SST task */\n\n        SST_INT_LOCK();            /* lock the interrupts for the next pass */\n    }\n    SST_currPrio_ = pin;                    /* restore the initial priority */\n}\n"
  },
  {
    "path": "sst0_c/README.txt",
    "content": "This directory contains the non-preemptive SST implementation in C,\nreferred to as \"SST0/C\".\n\n- \"basic tasks\" (non-blocking)\n- preemptive scheduling\n- multiple tasks per prioriy level\n- multiple \"activations\" per task (event queues)\n"
  },
  {
    "path": "sst0_c/examples/README.txt",
    "content": "This directory contains examples for the non-preemptive SST0/C kernel.\n"
  },
  {
    "path": "sst0_c/examples/blinky/armclang/nucleo-l053r8.uvoptx",
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<noStLib>0</noStLib>\n            <RepFail>1</RepFail>\n            <useFile>0</useFile>\n            <TextAddressRange>0x00000000</TextAddressRange>\n            <DataAddressRange>0x20000000</DataAddressRange>\n            <pXoBase></pXoBase>\n            <ScatterFile></ScatterFile>\n            <IncludeLibs></IncludeLibs>\n            <IncludeLibsPath></IncludeLibsPath>\n            <Misc>--entry Reset_Handler</Misc>\n            <LinkerInputFile></LinkerInputFile>\n            <DisabledWarnings></DisabledWarnings>\n          </LDads>\n        </TargetArmAds>\n      </TargetOption>\n      <Groups>\n        <Group>\n          <GroupName>Application</GroupName>\n          <Files>\n            <File>\n              <FileName>bsp.h</FileName>\n              <FileType>5</FileType>\n              <FilePath>..\\bsp.h</FilePath>\n            </File>\n            <File>\n              <FileName>bsp_nucleo-l053r8.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\bsp_nucleo-l053r8.c</FilePath>\n            </File>\n            <File>\n              <FileName>main.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\main.c</FilePath>\n            </File>\n            <File>\n              <FileName>blinky.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\blinky.c</FilePath>\n            </File>\n            <File>\n              <FileName>blinky.h</FileName>\n              <FileType>5</FileType>\n              <FilePath>..\\blinky.h</FilePath>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>nucleo-l053r8</GroupName>\n          <Files>\n            <File>\n              <FileName>startup_stm32l053xx.s</FileName>\n              <FileType>2</FileType>\n              <FilePath>..\\..\\..\\..\\3rd_party\\nucleo-l053r8\\arm\\startup_stm32l053xx.s</FilePath>\n            </File>\n            <File>\n              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<GroupName>sst_port</GroupName>\n          <Files>\n            <File>\n              <FileName>sst_port.h</FileName>\n              <FileType>5</FileType>\n              <FilePath>..\\..\\..\\ports\\arm-cm\\sst_port.h</FilePath>\n            </File>\n          </Files>\n        </Group>\n      </Groups>\n    </Target>\n  </Targets>\n\n  <RTE>\n    <apis/>\n    <components/>\n    <files/>\n  </RTE>\n\n  <LayerInfo>\n    <Layers>\n      <Layer>\n        <LayName>nucleo-l053r8</LayName>\n        <LayPrjMark>1</LayPrjMark>\n      </Layer>\n    </Layers>\n  </LayerInfo>\n\n</Project>\n"
  },
  {
    "path": "sst0_c/examples/blinky/blinky.c",
    "content": "/*============================================================================\n* Super-Simple Tasker (SST/C) Example\n*\n* Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n*\n* SPDX-License-Identifier: MIT\n*\n* Permission is hereby granted, free of charge, to any person obtaining a\n* copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included in\n* all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n============================================================================*/\n#include \"sst.h\"           /* SST framework */\n#include \"bsp.h\"           /* Board Support Package interface */\n#include \"blinky.h\"        /* application shared interface */\n\nDBC_MODULE_NAME(\"blinky\")  /* for DBC assertions in this module */\n\n/* Blinky event-driven task ------------------------------------------------*/\ntypedef struct {\n    SST_Task super; /* inherit SST_Task */\n\n    SST_TimeEvt te1;\n    SST_TimeEvt te2;\n} Blinky;\n\nstatic void Blinky_ctor(Blinky * const me);\nstatic void Blinky_init(Blinky * const me, SST_Evt const * const ie);\nstatic void Blinky_dispatch(Blinky * const me, SST_Evt const * const e);\n\n/*..........................................................................*/\nstatic Blinky Blinky_inst; /* the Blinky instance */\nSST_Task * const AO_Blinky = &Blinky_inst.super; /* opaque AO pointer */\n\n/*..........................................................................*/\nvoid Blinky_instantiate(void) {\n    Blinky_ctor(&Blinky_inst);\n}\n/*..........................................................................*/\nvoid Blinky_ctor(Blinky * const me) {\n    SST_Task_ctor(\n       &me->super,\n       (SST_Handler)&Blinky_init,\n       (SST_Handler)&Blinky_dispatch);\n    SST_TimeEvt_ctor(&me->te1, TIMEOUT1_SIG, &me->super);\n    SST_TimeEvt_ctor(&me->te2, TIMEOUT2_SIG, &me->super);\n}\n\n/* macro to select the Blinky implementation */\n#define BLINKY_IMPL 2\n\n/*--------------------------------------------------------------------------*/\n#if BLINKY_IMPL == 1\n/* Blinky implementation closest matching the traditional blocking approach */\n\nstatic void Blinky_init(Blinky * const me, SST_Evt const * const ie) {\n    (void)ie; /* unused parameter */\n\n    SST_TimeEvt_arm(&me->te1, 1U, 0U);\n}\n/*..........................................................................*/\nstatic void Blinky_dispatch(Blinky * const me, SST_Evt const * const e) {\n    switch (e->sig) {\n        case TIMEOUT1_SIG: {\n            BSP_ledOn();\n            SST_TimeEvt_arm(&me->te2, BSP_TICKS_PER_SEC / 4U, 0U);\n            break;\n        }\n        case TIMEOUT2_SIG: {\n            BSP_ledOff();\n            SST_TimeEvt_arm(&me->te1, BSP_TICKS_PER_SEC * 3U/4U, 0U);\n            break;\n        }\n        default: {\n            DBC_ERROR(200);\n            break;\n        }\n    }\n}\n\n/*--------------------------------------------------------------------------*/\n#elif BLINKY_IMPL == 2\n/* Blinky implementation with two periodic time events with offset */\n\nstatic void Blinky_init(Blinky * const me, SST_Evt const * const ie) {\n    (void)ie; /* unused parameter */\n    SST_TimeEvt_arm(&me->te1, 1U,                          BSP_TICKS_PER_SEC);\n    SST_TimeEvt_arm(&me->te2, 1U + (BSP_TICKS_PER_SEC/4U), BSP_TICKS_PER_SEC);\n}\n/*..........................................................................*/\nstatic void Blinky_dispatch(Blinky * const me, SST_Evt const * const e) {\n    switch (e->sig) {\n        case TIMEOUT1_SIG: {\n            BSP_ledOn();\n            break;\n        }\n        case TIMEOUT2_SIG: {\n            BSP_ledOff();\n            break;\n        }\n        default: {\n            DBC_ERROR(200);\n            break;\n        }\n    }\n}\n\n/*--------------------------------------------------------------------------*/\n#else\n    #error \"Wrong definition of the macro BLINKY_VERSION\"\n#endif\n"
  },
  {
    "path": "sst0_c/examples/blinky/blinky.h",
    "content": "/*============================================================================\n* Super-Simple Tasker (SST/C) Example\n*\n* Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n*\n* SPDX-License-Identifier: MIT\n*\n* Permission is hereby granted, free of charge, to any person obtaining a\n* copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included in\n* all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n============================================================================*/\n#ifndef BLINKY_H_\n#define BLINKY_H_\n\n#include \"dbc_assert.h\" /* Design By Contract (DBC) assertions */\n\nenum Signals {\n    TIMEOUT1_SIG,\n    TIMEOUT2_SIG,\n    /* ... */\n    MAX_SIG  /* the last signal */\n};\n\nvoid Blinky_instantiate(void);\nextern SST_Task * const AO_Blinky;  /* opaque task pointer */\n\n#endif /* BLINKY_H_ */\n"
  },
  {
    "path": "sst0_c/examples/blinky/bsp.h",
    "content": "/*============================================================================\n* Super-Simple Tasker (SST/C) Example\n*\n* Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n*\n* SPDX-License-Identifier: MIT\n*\n* Permission is hereby granted, free of charge, to any person obtaining a\n* copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included in\n* all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n============================================================================*/\n#ifndef BSP_H_\n#define BSP_H_\n\n#define BSP_TICKS_PER_SEC 1000U\n\nvoid BSP_init(void);\n\nvoid BSP_ledOn(void);\nvoid BSP_ledOff(void);\n\n#endif /* BSP_H_ */\n"
  },
  {
    "path": "sst0_c/examples/blinky/bsp_nucleo-l053r8.c",
    "content": "/*============================================================================\n* Super-Simple Tasker (SST0/C) Example for STM32 NUCLEO-L053R8\n*\n*                    Q u a n t u m  L e a P s\n*                    ------------------------\n*                    Modern Embedded Software\n*\n* Copyright (C) 2005 Quantum Leaps, <state-machine.com>.\n*\n* SPDX-License-Identifier: MIT\n*\n* Permission is hereby granted, free of charge, to any person obtaining a\n* copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included in\n* all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n============================================================================*/\n#include \"sst.h\"\n#include \"bsp.h\"\n#include \"blinky.h\"\n\n#include \"stm32l0xx.h\"  /* CMSIS-compliant header file for the MCU used */\n/* add other drivers if necessary... */\n\n//DBC_MODULE_NAME(\"bsp_nucleo-l053r8\") /* for DBC assertions in this module */\n\n/* Local-scope defines -----------------------------------------------------*/\n\n/* test pins on GPIO PA */\n#define LED_PIN   5U /* LED LD2-Green */\n\n/* ISRs used in the application ============================================*/\nvoid SysTick_Handler(void);  /* prototype */\n\nvoid SysTick_Handler(void) { /* system clock tick ISR */\n    SST_TimeEvt_tick(); /* process all SST time events */\n}\n\n/* Assertion handler ======================================================*/\nDBC_NORETURN\nvoid DBC_fault_handler(char const * const module, int const label) {\n    /*\n    * NOTE: add here your application-specific error handling\n    */\n    (void)module;\n    (void)label;\n\n    /* set PRIMASK to disable interrupts and stop SST right here */\n    __asm volatile (\"cpsid i\");\n\n#ifndef NDEBUG\n    for (;;) { /* keep blinking LED2 */\n        BSP_ledOn();  /* turn LED2 on */\n        uint32_t volatile ctr;\n        for (ctr = 10000U; ctr > 0U; --ctr) {\n        }\n        BSP_ledOff(); /* turn LED2 off */\n        for (ctr = 10000U; ctr > 0U; --ctr) {\n        }\n    }\n#endif\n    NVIC_SystemReset();\n}\n/*..........................................................................*/\nvoid assert_failed(char const * const module, int const label);/* prototype */\nvoid assert_failed(char const * const module, int const label) {\n    DBC_fault_handler(module, label);\n}\n\n/* BSP functions ===========================================================*/\nvoid BSP_init(void) {\n    /* Configure the MPU to prevent NULL-pointer dereferencing\n    * see: www.state-machine.com/null-pointer-protection-with-arm-cortex-m-mpu\n    */\n    MPU->RBAR = 0x0U                          /* base address (NULL) */\n                | MPU_RBAR_VALID_Msk          /* valid region */\n                | (MPU_RBAR_REGION_Msk & 7U); /* region #7 */\n    MPU->RASR = (7U << MPU_RASR_SIZE_Pos)     /* 2^(7+1) region */\n                | (0x0U << MPU_RASR_AP_Pos)   /* no-access region */\n                | MPU_RASR_ENABLE_Msk;        /* region enable */\n\n    MPU->CTRL = MPU_CTRL_PRIVDEFENA_Msk       /* enable background region */\n                | MPU_CTRL_ENABLE_Msk;        /* enable the MPU */\n    __ISB();\n    __DSB();\n\n\n    /* enable GPIO port PA clock */\n    RCC->IOPENR |= (1U << 0U);\n\n    /* set all used GPIOA pins as push-pull output, no pull-up, pull-down */\n    GPIOA->MODER  &= ~(3U << 2U*LED_PIN);\n    GPIOA->MODER  |=  (1U << 2U*LED_PIN);\n    GPIOA->OTYPER &= ~(1U <<    LED_PIN);\n    GPIOA->PUPDR  &= ~(3U << 2U*LED_PIN);\n}\n\n/*..........................................................................*/\nvoid BSP_ledOn(void)  { GPIOA->BSRR = (1U << LED_PIN);         } /* LED2 */\nvoid BSP_ledOff(void) { GPIOA->BSRR = (1U << (LED_PIN + 16U)); }\n\n/* SST callbacks ===========================================================*/\nvoid SST_onStart(void) {\n    SystemCoreClockUpdate();\n\n    /* set up the SysTick timer to fire at BSP_TICKS_PER_SEC rate */\n    SysTick_Config((SystemCoreClock / BSP_TICKS_PER_SEC) + 1U);\n\n    /* set priorities of ISRs used in the system */\n    NVIC_SetPriority(SysTick_IRQn, 0U);\n    /* ... */\n}\n/*..........................................................................*/\nvoid SST_onIdleCond(void) { /* NOTE: called with interrupts DISABLED */\n#ifdef NDEBUG\n    /* Put the CPU and peripherals to the low-power mode.\n    * you might need to customize the clock management for your application,\n    * see the datasheet for your particular Cortex-M MCU.\n    */\n    __WFI(); /* Wait-For-Interrupt */\n#endif\n    SST_PORT_INT_ENABLE(); /* NOTE: enable interrupts for SS0 */\n}\n\n"
  },
  {
    "path": "sst0_c/examples/blinky/gnu/nucleo-l053r8.mak",
    "content": "##############################################################################\n# Makefile for Super-Simple Tasker (SST0/C) on NUCLEO-L053R8, GNU-ARM\n# Last Updated for Version: 2.0.0\n# Date of the Last Update:  2023-01-22\n#\n#                    Q u a n t u m  L e a P s\n#                    ------------------------\n#                    Modern Embedded Software\n#\n# Copyright (C) 2005 Quantum Leaps, LLC. All rights reserved.\n#\n# SPDX-License-Identifier: MIT\n#\n# Permission is hereby granted, free of charge, to any person obtaining a copy\n# of this software and associated documentation files (the \"Software\"), to\n# deal in the Software without restriction, including without limitation the\n# rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n# sell copies of the Software, and to permit persons to whom the Software is\n# furnished to do so, subject to the following conditions:\n#\n# The above copyright notice and this permission notice shall be included in\n# all copies or substantial portions of the Software.\n#\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS\n# IN THE SOFTWARE.\n##############################################################################\n# examples of invoking this Makefile:\n# make -f nucleo-l053r8.mak\n# make -f nucleo-l053r8.mak clean\n#\n# NOTE:\n# To use this Makefile on Windows, you will need the GNU make utility, which\n# is included in the QTools collection for Windows, see:\n#    https://github.com/QuantumLeaps/qtools\n#\n\n#-----------------------------------------------------------------------------\n# project and target names\n#\nPROJECT := blinky\nTARGET  := nucleo-l053r8\n\n#-----------------------------------------------------------------------------\n# project directories\n#\nSST_DIR      := ../../..\nSST_PORT_DIR := $(SST_DIR)/ports/arm-cm\nCMSIS_DIR    := ../../../../3rd_party/CMSIS\nTARGET_DIR   := ../../../../3rd_party/$(TARGET)\n\n# list of all source directories used by this project\nVPATH = .. \\\n\t$(SST_DIR)/src \\\n\t$(SST_PORT_DIR) \\\n\t$(TARGET_DIR) \\\n\t$(TARGET_DIR)/gnu \\\n\n# list of all include directories needed by this project\nINCLUDES  = -I. \\\n\t-I$(SST_DIR)/../include \\\n\t-I$(SST_PORT_DIR) \\\n\t-I$(CMSIS_DIR)/Include \\\n\t-I$(TARGET_DIR)\n\n#-----------------------------------------------------------------------------\n# project files\n#\n\n# assembler source files\nASM_SRCS :=\n\n# C source files\nC_SRCS := \\\n\tsst0.c \\\n\tmain.c \\\n\tblinky.c \\\n\tbsp_nucleo-l053r8.c \\\n\tsystem_stm32l0xx.c \\\n\tstartup_stm32l053xx.c\n\n# C++ source files\nCPP_SRCS :=\n\nLD_SCRIPT  := $(TARGET_DIR)/gnu/$(TARGET).ld\n\nOUTPUT    := $(PROJECT)\n\nLIB_DIRS  :=\nLIBS      :=\n\n# defines\nDEFINES   :=\n\n# ARM CPU, ARCH, FPU, and Float-ABI types...\n# ARM_CPU:   [cortex-m0 | cortex-m0plus | cortex-m1 | cortex-m3 | cortex-m4]\n# ARM_FPU:   [ | vfp]\n# FLOAT_ABI: [ | soft | softfp | hard]\n#\nARM_CPU   := -mcpu=cortex-m0plus\nARM_FPU   :=\nFLOAT_ABI :=\n\n#-----------------------------------------------------------------------------\n# GNU-ARM toolset (NOTE: You need to adjust to your machine)\n# see https://developer.arm.com/open-source/gnu-toolchain/gnu-rm/downloads\n#\nifeq ($(GNU_ARM),)\nGNU_ARM := $(QTOOLS)/gnu_arm-none-eabi\nendif\n\n# make sure that the GNU-ARM toolset exists...\nifeq (\"$(wildcard $(GNU_ARM))\",\"\")\n$(error GNU_ARM toolset not found. Please adjust the Makefile)\nendif\n\nCC    := $(GNU_ARM)/bin/arm-none-eabi-gcc\nCPP   := $(GNU_ARM)/bin/arm-none-eabi-g++\nAS    := $(GNU_ARM)/bin/arm-none-eabi-as\nLINK  := $(GNU_ARM)/bin/arm-none-eabi-gcc\nBIN   := $(GNU_ARM)/bin/arm-none-eabi-objcopy\n\n##############################################################################\n# Typically you should not need to change anything below this line\n\n# basic utilities (included in QTools for Windows), see:\n#     https://www.state-machine.com/qtools\n\nMKDIR := mkdir\nRM    := rm\n\n#-----------------------------------------------------------------------------\n# build options\n#\n\n# combine all the soruces...\nC_SRCS += $(QP_SRCS)\nASM_SRCS += $(QP_ASMS)\n\nBIN_DIR := build_$(TARGET)\n\nASFLAGS = -g $(ARM_CPU) $(ARM_FPU) $(ASM_CPU) $(ASM_FPU)\n\nCFLAGS = -c -g $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -std=c99 -mthumb -Wall \\\n\t-ffunction-sections -fdata-sections \\\n\t-O $(INCLUDES) $(DEFINES)\n\nCPPFLAGS = -c -g $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -std=c++11 -mthumb -Wall \\\n\t-ffunction-sections -fdata-sections -fno-rtti -fno-exceptions \\\n\t-O $(INCLUDES) $(DEFINES)\n\nLINKFLAGS = -T$(LD_SCRIPT) $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -mthumb \\\n\t-specs=nosys.specs -specs=nano.specs \\\n\t-Wl,-Map,$(BIN_DIR)/$(OUTPUT).map,--cref,--gc-sections $(LIB_DIRS)\n\nASM_OBJS     := $(patsubst %.s,%.o,  $(notdir $(ASM_SRCS)))\nC_OBJS       := $(patsubst %.c,%.o,  $(notdir $(C_SRCS)))\nCPP_OBJS     := $(patsubst %.cpp,%.o,$(notdir $(CPP_SRCS)))\n\nTARGET_BIN   := $(BIN_DIR)/$(OUTPUT).bin\nTARGET_ELF   := $(BIN_DIR)/$(OUTPUT).elf\nASM_OBJS_EXT := $(addprefix $(BIN_DIR)/, $(ASM_OBJS))\nC_OBJS_EXT   := $(addprefix $(BIN_DIR)/, $(C_OBJS))\nC_DEPS_EXT   := $(patsubst %.o, %.d, $(C_OBJS_EXT))\nCPP_OBJS_EXT := $(addprefix $(BIN_DIR)/, $(CPP_OBJS))\nCPP_DEPS_EXT := $(patsubst %.o, %.d, $(CPP_OBJS_EXT))\n\n# create $(BIN_DIR) if it does not exist\nifeq (\"$(wildcard $(BIN_DIR))\",\"\")\n$(shell $(MKDIR) $(BIN_DIR))\nendif\n\n#-----------------------------------------------------------------------------\n# rules\n#\n\n.PHONY : run norun flash\n\nifeq ($(MAKECMDGOALS),norun)\nall : $(TARGET_BIN)\nnorun : all\nelse\nall : $(TARGET_BIN) run\nendif\n\n$(TARGET_BIN): $(TARGET_ELF)\n\t$(BIN) -O binary $< $@\n\n$(TARGET_ELF) : $(ASM_OBJS_EXT) $(C_OBJS_EXT) $(CPP_OBJS_EXT)\n\t$(LINK) $(LINKFLAGS) -o $@ $^ $(LIBS)\n\n$(BIN_DIR)/%.d : %.c\n\t$(CC) -MM -MT $(@:.d=.o) $(CFLAGS) $< > $@\n\n$(BIN_DIR)/%.d : %.cpp\n\t$(CPP) -MM -MT $(@:.d=.o) $(CPPFLAGS) $< > $@\n\n$(BIN_DIR)/%.o : %.s\n\t$(AS) $(ASFLAGS) $< -o $@\n\n$(BIN_DIR)/%.o : %.c\n\t$(CC) $(CFLAGS) $< -o $@\n\n$(BIN_DIR)/%.o : %.cpp\n\t$(CPP) $(CPPFLAGS) $< -o $@\n\n.PHONY : clean show\n\n# include dependency files only if our goal depends on their existence\nifneq ($(MAKECMDGOALS),clean)\n  ifneq ($(MAKECMDGOALS),show)\n-include $(C_DEPS_EXT) $(CPP_DEPS_EXT)\n  endif\nendif\n\n\nclean :\n\t-$(RM) $(BIN_DIR)/*.o \\\n\t$(BIN_DIR)/*.d \\\n\t$(BIN_DIR)/*.bin \\\n\t$(BIN_DIR)/*.elf \\\n\t$(BIN_DIR)/*.map\n\t\nshow:\n\t@echo PROJECT = $(PROJECT)\n\t@echo CONF = $(CONF)\n\t@echo DEFINES = $(DEFINES)\n\t@echo ASM_FPU = $(ASM_FPU)\n\t@echo ASM_SRCS = $(ASM_SRCS)\n\t@echo C_SRCS = $(C_SRCS)\n\t@echo CPP_SRCS = $(CPP_SRCS)\n\t@echo ASM_OBJS_EXT = $(ASM_OBJS_EXT)\n\t@echo C_OBJS_EXT = $(C_OBJS_EXT)\n\t@echo C_DEPS_EXT = $(C_DEPS_EXT)\n\t@echo CPP_DEPS_EXT = $(CPP_DEPS_EXT)\n\t@echo TARGET_ELF = $(TARGET_ELF)\n"
  },
  {
    "path": "sst0_c/examples/blinky/iar/nucleo-l053r8.ewd",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<project>\n    <fileVersion>3</fileVersion>\n    <configuration>\n        <name>Debug</name>\n        <toolchain>\n            <name>ARM</name>\n        </toolchain>\n        <debug>1</debug>\n        <settings>\n            <name>C-SPY</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>32</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CInput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CEndian</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCVariant</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>MemOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MemFile</name>\n                    <state>$TOOLKIT_DIR$\\CONFIG\\debugger\\ST\\STM32L053R8.ddf</state>\n                </option>\n                <option>\n                    <name>RunToEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RunToName</name>\n                    <state>main</state>\n                </option>\n                <option>\n                    <name>CExtraOptionsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCDDFArgumentProducer</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCDownloadSuppressDownload</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCDownloadVerifyAll</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProductVersion</name>\n                    <state>9.10.2.39304</state>\n                </option>\n                <option>\n                    <name>OCDynDriverList</name>\n                    <state>STLINK_ID</state>\n                </option>\n                <option>\n                    <name>OCLastSavedByProductVersion</name>\n                    <state>9.32.1.54977</state>\n                </option>\n                <option>\n                    <name>UseFlashLoader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CLowLevel</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCBE8Slave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacFile2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CDevice</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>FlashLoadersV3</name>\n                    <state>$TOOLKIT_DIR$/config/flashloader/ST/FlashSTM32L0xxx8.board</state>\n                </option>\n                <option>\n                    <name>OCImagesSuppressCheck1</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesPath1</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCImagesSuppressCheck2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesPath2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCImagesSuppressCheck3</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesPath3</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OverrideDefFlashBoard</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesOffset1</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCImagesOffset2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCImagesOffset3</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCImagesUse1</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesUse2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesUse3</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCDeviceConfigMacroFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCDebuggerExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCAllMTBOptions</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCMulticoreNrOfCores</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCMulticoreWorkspace</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCMulticoreSlaveProject</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCMulticoreSlaveConfiguration</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCDownloadExtraImage</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCAttachSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MassEraseBeforeFlashing</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCMulticoreNrOfCoresSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCMulticoreAMPConfigType</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCMulticoreSessionFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCTpiuBaseOption</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>ARMSIM_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>1</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCSimDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCSimEnablePSP</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCSimPspOverrideConfig</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCSimPspConfigFile</name>\n                    <state></state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CADI_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CCadiMemory</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>Fast Model</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCADILogFileCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCADILogFileEditB</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CMSISDAP_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>4</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCIarProbeScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CMSISDAPResetList</name>\n                    <version>1</version>\n                    <state>10</state>\n                </option>\n                <option>\n                    <name>CMSISDAPHWResetDuration</name>\n                    <state>300</state>\n                </option>\n                <option>\n                    <name>CMSISDAPHWResetDelay</name>\n                    <state>200</state>\n                </option>\n                <option>\n                    <name>CMSISDAPDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CMSISDAPInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CMSISDAPInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiTargetEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPJtagSpeedList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPRestoreBreakpointsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPUpdateBreakpointsEdit</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>RDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchUndef</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchData</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchPrefetch</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchMMERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchNOCPERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchCHKERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSTATERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchBUSERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchINTERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSFERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchHARDERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiCPUEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiCPUNumber</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeCfgOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeConfig</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CMSISDAPProbeConfigRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPSelectedCPUBehaviour</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ICpuName</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCJetEmuParams</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCCMSISDAPUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCCMSISDAPUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>GDBSERVER_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>TCPIP</name>\n                    <state>aaa.bbb.ccc.ddd</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCJTagBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJTagDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJTagUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>IJET_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>9</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCIarProbeScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetResetList</name>\n                    <version>1</version>\n                    <state>10</state>\n                </option>\n                <option>\n                    <name>IjetHWResetDuration</name>\n                    <state>300</state>\n                </option>\n                <option>\n                    <name>IjetHWResetDelay</name>\n                    <state>200</state>\n                </option>\n                <option>\n                    <name>IjetPowerFromProbe</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetPowerRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>IjetInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiTargetEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetScanChainNonARMDevices</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetIRLength</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetJtagSpeedList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetProtocolRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetSwoPin</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IjetSwoPrescalerList</name>\n                    <version>1</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetRestoreBreakpointsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetUpdateBreakpointsEdit</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>RDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchUndef</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchData</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchPrefetch</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchMMERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchNOCPERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchCHKERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSTATERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchBUSERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchINTERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSFERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchHARDERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeCfgOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeConfig</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IjetProbeConfigRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiCPUEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiCPUNumber</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetSelectedCPUBehaviour</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ICpuName</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCJetEmuParams</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetPreferETB</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetTraceSettingsList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetTraceSizeList</name>\n                    <version>0</version>\n                    <state>4</state>\n                </option>\n                <option>\n                    <name>FlashBoardPathSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCIjetUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCIjetUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL3S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL3S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL3S</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>JLINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>16</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>JLinkSpeed</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCJLinkDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCJLinkHWResetDelay</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>JLinkInitialSpeed</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCDoJlinkMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCScanChainNonARMDevices</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkIRLength</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkCommRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkTCPIP</name>\n                    <state>aaa.bbb.ccc.ddd</state>\n                </option>\n                <option>\n                    <name>CCJLinkSpeedRadioV2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCUSBDevice</name>\n                    <version>1</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCRDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchUndef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchData</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchPrefetch</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCJLinkInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJLinkResetList</name>\n                    <version>6</version>\n                    <state>5</state>\n                </option>\n                <option>\n                    <name>CCJLinkInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJLinkUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCTcpIpAlt</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkTcpIpSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSwoClockAuto</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSwoClockEdit</name>\n                    <state>2000</state>\n                </option>\n                <option>\n                    <name>OCJLinkTraceSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkTraceSourceDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkDeviceName</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>LMIFTDI_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>3</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>LmiftdiSpeed</name>\n                    <state>500</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCLmiFtdiInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCLmiFtdiInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCLmiftdiUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiResetList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>NULINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>PEMICRO_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>3</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJPEMicroShowSettings</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>STLINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>8</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSTLinkInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSTLinkInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkResetList</name>\n                    <version>3</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSwoClockAuto</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSwoClockEdit</name>\n                    <state>2000</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCSTLinkDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSTLinkUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkJtagSpeedList</name>\n                    <version>2</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkDAPNumber</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSTLinkDebugAccessPortRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUseServerSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkProbeList</name>\n                    <version>1</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkTargetVccEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSTLinkTargetVoltage</name>\n                    <state>3.3</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>THIRDPARTY_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CThirdPartyDriverDll</name>\n                    <state>###Uninitialized###</state>\n                </option>\n                <option>\n                    <name>CThirdPartyLogFileCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CThirdPartyLogFileEditB</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>TIFET_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>1</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCMSPFetResetList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetInterfaceRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetTargetVccTypeDefault</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetTargetVoltage</name>\n                    <state>###Uninitialized###</state>\n                </option>\n                <option>\n                    <name>CCMSPFetVCCDefault</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCMSPFetTargetSettlingtime</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetRadioJtagSpeedType</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCMSPFetConnection</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetUsbComPort</name>\n                    <state>Automatic</state>\n                </option>\n                <option>\n                    <name>CCMSPFetAllowAccessToBSL</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCMSPFetRadioEraseFlash</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>XDS100_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>9</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>TIPackageOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TIPackage</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>BoardFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCXds100BreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100DoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100UpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchUndef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchData</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchPrefetch</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCXds100SwoClockAuto</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100SwoClockEdit</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCXds100HWResetDelay</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100ResetList</name>\n                    <version>1</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100UsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCXds100UsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100JtagSpeedList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100InterfaceRadio</name>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCXds100InterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100ProbeList</name>\n                    <version>0</version>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>CCXds100SWOPortRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100SWOPort</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCXDSTargetVccEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXDSTargetVoltage</name>\n                    <state>###Uninitialized###</state>\n                </option>\n                <option>\n                    <name>OCXDSDigitalStatesConfigFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCSelectedCoreName</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <debuggerPlugins>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\CMX\\CmxArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\CMX\\CmxTinyArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\embOS\\embOSPlugin.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\FreeRtos\\FreeRtosArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\Mbed\\MbedArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\Mbed\\MbedArmPlugin2.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\OpenRTOS\\OpenRTOSPlugin.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\SafeRTOS\\SafeRTOSPlugin.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\SMX\\smxAwareIarArm9.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\SMX\\smxAwareIarArm9BE.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\ThreadX\\ThreadXArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\uCOS-II\\uCOS-II-286-KA-CSpy.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\uCOS-II\\uCOS-II-KA-CSpy.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\uCOS-III\\uCOS-III-KA-CSpy.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$EW_DIR$\\common\\plugins\\Orti\\Orti.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$EW_DIR$\\common\\plugins\\TargetAccessServer\\TargetAccessServer.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$EW_DIR$\\common\\plugins\\uCProbe\\uCProbePlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n        </debuggerPlugins>\n    </configuration>\n</project>\n"
  },
  {
    "path": "sst0_c/examples/blinky/iar/nucleo-l053r8.ewp",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<project>\n    <fileVersion>3</fileVersion>\n    <configuration>\n        <name>Debug</name>\n        <toolchain>\n            <name>ARM</name>\n        </toolchain>\n        <debug>1</debug>\n        <settings>\n            <name>General</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <version>35</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>BrowseInfoPath</name>\n                    <state>build_nucleo-l053r8</state>\n                </option>\n                <option>\n                    <name>ExePath</name>\n                    <state>build_nucleo-l053r8</state>\n                </option>\n                <option>\n                    <name>ObjPath</name>\n                    <state>build_nucleo-l053r8</state>\n                </option>\n                <option>\n                    <name>ListPath</name>\n                    <state>build_nucleo-l053r8</state>\n                </option>\n                <option>\n                    <name>GEndianMode</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>Input description</name>\n                    <state>No specifier n, no float nor long long, no scan set, no assignment suppressing, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>Output description</name>\n                    <state>No specifier a, A, no specifier n, no float nor long long, no flags, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>GOutputBinary</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGCoreOrChip</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelect</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelectSlave</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RTDescription</name>\n                    <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\n                </option>\n                <option>\n                    <name>OGProductVersion</name>\n                    <state>5.11.0.50579</state>\n                </option>\n                <option>\n                    <name>OGLastSavedByProductVersion</name>\n                    <state>9.32.1.54977</state>\n                </option>\n                <option>\n                    <name>OGChipSelectEditMenu</name>\n                    <state>STM32L053R8\tST STM32L053R8</state>\n                </option>\n                <option>\n                    <name>GenLowLevelInterface</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GEndianModeBE</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OGBufferedTerminalOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GenStdoutInterface</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RTConfigPath2</name>\n                    <state>$TOOLKIT_DIR$\\inc\\c\\DLib_Config_Normal.h</state>\n                </option>\n                <option>\n                    <name>GBECoreSlave</name>\n                    <version>32</version>\n                    <state>35</state>\n                </option>\n                <option>\n                    <name>OGUseCmsis</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGUseCmsisDspLib</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibThreads</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CoreVariant</name>\n                    <version>32</version>\n                    <state>35</state>\n                </option>\n                <option>\n                    <name>GFPUDeviceSlave</name>\n                    <state>STM32L053R8\tST STM32L053R8</state>\n                </option>\n                <option>\n                    <name>FPU2</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>NrRegs</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>NEON</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GFPUCoreSlave2</name>\n                    <version>32</version>\n                    <state>35</state>\n                </option>\n                <option>\n                    <name>OGCMSISPackSelectDevice</name>\n                </option>\n                <option>\n                    <name>OgLibHeap</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGLibAdditionalLocale</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGPrintfVariant</name>\n                    <version>0</version>\n                    <state>4</state>\n                </option>\n                <option>\n                    <name>OGPrintfMultibyteSupport</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGScanfVariant</name>\n                    <version>0</version>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>OGScanfMultibyteSupport</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GenLocaleTags</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>GenLocaleDisplayOnly</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DSPExtension</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TrustZone</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TrustZoneModes</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGAarch64Abi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OG_32_64Device</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>BuildFilesPath</name>\n                    <state>Debug</state>\n                </option>\n                <option>\n                    <name>PointerAuthentication</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>FPU64</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>ICCARM</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>37</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CCOptimizationNoSizeConstraints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCDefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCPreprocFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPreprocComments</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPreprocLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCMnemonics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCMessages</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListAssFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListAssSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEnableRemarks</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCDiagSuppress</name>\n                    <state>Pa050</state>\n                </option>\n                <option>\n                    <name>CCDiagRemark</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagWarning</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagError</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCObjPrefix</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCAllowList</name>\n                    <version>1</version>\n                    <state>10010100</state>\n                </option>\n                <option>\n                    <name>CCDebugInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IEndianMode</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IExtraOptionsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCLangConformance</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSignedPlainChar</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCRequirePrototypes</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCDiagWarnAreErr</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCompilerRuntimeInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OutputFile</name>\n                    <state>$FILE_BNAME$.o</state>\n                </option>\n                <option>\n                    <name>CCLibConfigHeader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>PreInclude</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCIncludePath2</name>\n                    <state>$PROJ_DIR$\\..</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\include</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\ports\\arm-cm</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\CMSIS\\Include</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\nucleo-l053r8</state>\n                </option>\n                <option>\n                    <name>CCStdIncCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCodeSection</name>\n                    <state>.text</state>\n                </option>\n                <option>\n                    <name>IProcessorMode2</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCOptLevel</name>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCOptStrategy</name>\n                    <version>0</version>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCOptLevelSlave</name>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCPosIndRopi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPosIndRwpi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPosIndNoDynInit</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccLang</name>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>IccCDialect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccAllowVLA</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccStaticDestr</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccCppInlineSemantics</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccCmsis</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccFloatSemantics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCNoLiteralPool</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCOptStrategySlave</name>\n                    <version>0</version>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCGuardCalls</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCEncSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEncOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEncOutputBom</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCEncInput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccExceptions2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccRTTI2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OICompilerExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCStackProtection</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>AARM</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>11</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>AObjPrefix</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AEndian</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>ACaseSensitivity</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacroChars</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnWhat</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnOne</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AWarnRange1</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AWarnRange2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>ADebug</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AltRegisterNames</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ADefines</name>\n                    <state>ewarm</state>\n                </option>\n                <option>\n                    <name>AList</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AListHeader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AListing</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>Includes</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacDefs</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacExps</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacExec</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OnlyAssed</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MultiLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PageLengthCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PageLength</name>\n                    <state>80</state>\n                </option>\n                <option>\n                    <name>TabSpacing</name>\n                    <state>8</state>\n                </option>\n                <option>\n                    <name>AXRef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefDefines</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefInternal</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefDual</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AOutputFile</name>\n                    <state>$FILE_BNAME$.o</state>\n                </option>\n                <option>\n                    <name>ALimitErrorsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ALimitErrorsEdit</name>\n                    <state>100</state>\n                </option>\n                <option>\n                    <name>AIgnoreStdInclude</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AUserIncludes</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AExtraOptionsCheckV2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AExtraOptionsV2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AsmNoLiteralPool</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PreInclude</name>\n                    <state></state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>OBJCOPY</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>1</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OOCOutputFormat</name>\n                    <version>3</version>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>OCOutputOverride</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OOCOutputFile</name>\n                    <state>blinky.bin</state>\n                </option>\n                <option>\n                    <name>OOCCommandLineProducer</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OOCObjCopyEnable</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CUSTOM</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <extensions></extensions>\n                <cmdline></cmdline>\n                <hasPrio>1</hasPrio>\n                <buildSequence>inputOutputBased</buildSequence>\n            </data>\n        </settings>\n        <settings>\n            <name>BUILDACTION</name>\n            <archiveVersion>1</archiveVersion>\n            <data>\n                <prebuild></prebuild>\n                <postbuild></postbuild>\n            </data>\n        </settings>\n        <settings>\n            <name>ILINK</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>27</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>IlinkLibIOConfig</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkInputFileSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOutputFile</name>\n                    <state>blinky.out</state>\n                </option>\n                <option>\n                    <name>IlinkDebugInfoEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkKeepSymbols</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySymbol</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySegment</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryAlign</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkDefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkConfigDefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkMapFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLogFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogInitialization</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogModule</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogSection</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogVeneer</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFile</name>\n                    <state>$TOOLKIT_DIR$\\config\\linker\\ST\\stm32l053x8.icf</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFileSlave</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkEnableRemarks</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkSuppressDiags</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsRem</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsWarn</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsErr</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkWarningsAreErrors</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkUseExtraOptions</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkLowLevelInterfaceSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkAutoLibEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkAdditionalLibs</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkOverrideProgramEntryLabel</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkProgramEntryLabelSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkProgramEntryLabel</name>\n                    <state>__iar_program_start</state>\n                </option>\n                <option>\n                    <name>DoFill</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>FillerByte</name>\n                    <state>0xFF</state>\n                </option>\n                <option>\n                    <name>FillerStart</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>FillerEnd</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>CrcSize</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcAlign</name>\n                    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  <option>\n                    <name>IlinkCrcReverseByteOrder</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCrcUseAsInput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptInline</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOptExceptionsAllow</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOptExceptionsForce</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCmsis</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptMergeDuplSections</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOptUseVfe</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptForceVfe</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkStackAnalysisEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkStackControlFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkStackCallGraphFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CrcAlgorithm</name>\n                    <version>1</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcUnitSize</name>\n            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             </option>\n                <option>\n                    <name>IlinkWrapperFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkFpuProcessor</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>IARCHIVE</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>IarchiveInputs</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IarchiveOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IarchiveOutput</name>\n                    <state>###Unitialized###</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>Coder</name>\n            <archiveVersion>0</archiveVersion>\n            <data />\n        </settings>\n    </configuration>\n    <mfc>\n        <configuration>Debug</configuration>\n    </mfc>\n    <group>\n        <name>Application</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\blinky.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\blinky.h</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\bsp.h</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\bsp_nucleo-l053r8.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\main.c</name>\n        </file>\n    </group>\n    <group>\n        <name>nucleo-l053r8</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\nucleo-l053r8\\iar\\startup_stm32l053xx.s</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\nucleo-l053r8\\stm32l053xx.h</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\nucleo-l053r8\\system_stm32l0xx.c</name>\n        </file>\n    </group>\n    <group>\n        <name>sst</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\src\\sst0.c</name>\n        </file>\n    </group>\n    <group>\n        <name>sst_port</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\ports\\arm-cm\\sst_port.h</name>\n        </file>\n    </group>\n</project>\n"
  },
  {
    "path": "sst0_c/examples/blinky/iar/nucleo-l053r8.eww",
    "content": "<?xml version=\"1.0\" encoding=\"iso-8859-1\"?>\n\n<workspace>\n  <project>\n    <path>$WS_DIR$\\nucleo-l053r8.ewp</path>\n  </project>\n  <batchBuild/>\n</workspace>\n\n\n"
  },
  {
    "path": "sst0_c/examples/blinky/main.c",
    "content": "/*============================================================================\n* Super-Simple Tasker (SST/C) Example\n*\n* Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n*\n* SPDX-License-Identifier: MIT\n*\n* Permission is hereby granted, free of charge, to any person obtaining a\n* copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included in\n* all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n============================================================================*/\n#include \"sst.h\"           /* SST framework */\n#include \"bsp.h\"           /* Board Support Package interface */\n#include \"blinky.h\"        /* application shared interface */\n\n/*..........................................................................*/\nint main() {\n    SST_init(); /* initialize the SST kernel */\n    BSP_init(); /* initialize the Board Support Package */\n\n    /* instantiate and start all SST tasks... */\n    Blinky_instantiate();\n    static SST_Evt const *blinkyQSto[10]; /* Event queue storage */\n    SST_Task_start(\n        AO_Blinky,     /* AO pointer to start */\n        1U,            /* SST-priority */\n        blinkyQSto,    /* storage for the AO's queue */\n        ARRAY_NELEM(blinkyQSto),   /* queue length */\n        (void *)0);    /* initialization event (not used) */\n\n    return SST_Task_run(); /* run the SST tasks */\n    /* NOTE; in embedded systems SST_Task_run() should not return */\n}\n\n"
  },
  {
    "path": "sst0_c/examples/blinky_button/armclang/ek-tm4c123gxl.uvoptx",
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  },
  {
    "path": "sst0_c/examples/blinky_button/blinky1.c",
    "content": "/*============================================================================\n* Super-Simple Tasker (SST0/C) Example\n*\n* Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n*\n* SPDX-License-Identifier: MIT\n*\n* Permission is hereby granted, free of charge, to any person obtaining a\n* copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included in\n* all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n============================================================================*/\n#include \"sst.h\"           /* SST framework */\n#include \"bsp.h\"           /* Board Support Package interface */\n#include \"blinky_button.h\" /* application shared interface */\n\nDBC_MODULE_NAME(\"blinky1\") /* for DBC assertions in this module */\n\n/*..........................................................................*/\ntypedef struct {      /* Blinky1 task */\n    SST_Task super;   /* inherit SST_Task */\n    SST_TimeEvt te;   /* time event for generating TIMEOUT events */\n    uint16_t toggles; /* number of toggles to perform for TIMEOUT event */\n} Blinky1;\n\nstatic void Blinky1_ctor(Blinky1 * const me);\nstatic void Blinky1_init(Blinky1 * const me, SST_Evt const * const ie);\nstatic void Blinky1_dispatch(Blinky1 * const me, SST_Evt const * const e);\n\n/*..........................................................................*/\nstatic Blinky1 Blinky1_inst; /* the Blinky instance */\nSST_Task * const AO_Blinky1 = &Blinky1_inst.super; /* opaque AO pointer */\n\nvoid Blinky1_instantiate(void) {\n    Blinky1_ctor(&Blinky1_inst);\n}\n\n/*..........................................................................*/\nstatic void Blinky1_ctor(Blinky1 * const me) {\n    SST_Task_ctor(\n       &me->super,\n       (SST_Handler)&Blinky1_init,\n       (SST_Handler)&Blinky1_dispatch);\n    SST_TimeEvt_ctor(&me->te, TIMEOUT_SIG, &me->super);\n}\n/*..........................................................................*/\nstatic void Blinky1_init(Blinky1 * const me, SST_Evt const * const ie) {\n    /* the initial event must be provided and must be WORKLOAD_SIG */\n    DBC_REQUIRE(300,\n        (ie != (SST_Evt const *)0) && (ie->sig == BLINKY_WORK_SIG));\n\n    SST_TimeEvt_arm(&me->te,\n        SST_EVT_DOWNCAST(BlinkyWorkEvt, ie)->ticks,\n        SST_EVT_DOWNCAST(BlinkyWorkEvt, ie)->ticks);\n    me->toggles = SST_EVT_DOWNCAST(BlinkyWorkEvt, ie)->toggles;\n}\n/*..........................................................................*/\nstatic void Blinky1_dispatch(Blinky1 * const me, SST_Evt const * const e) {\n    switch (e->sig) {\n        case TIMEOUT_SIG: {\n            for (uint16_t i = me->toggles; i > 0U; --i) {\n                /* SST scheduler lock is not needed in non-preemptive SST0 */\n                //SST_LockKey key = SST_Task_lock(3U);\n                BSP_d5on();\n                BSP_d5off();\n                //SST_Task_unlock(key);\n            }\n            break;\n        }\n        case BLINKY_WORK_SIG: {\n            BSP_d5on();\n            SST_TimeEvt_arm(&me->te,\n                SST_EVT_DOWNCAST(BlinkyWorkEvt, e)->ticks,\n                SST_EVT_DOWNCAST(BlinkyWorkEvt, e)->ticks);\n            me->toggles = SST_EVT_DOWNCAST(BlinkyWorkEvt, e)->toggles;\n            BSP_d5off();\n            break;\n        }\n        default: {\n            DBC_ERROR(500); /* unexpected event */\n            break;\n        }\n    }\n}\n"
  },
  {
    "path": "sst0_c/examples/blinky_button/blinky3.c",
    "content": "/*============================================================================\n* Super-Simple Tasker (SST/C) Example\n*\n* Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n*\n* SPDX-License-Identifier: MIT\n*\n* Permission is hereby granted, free of charge, to any person obtaining a\n* copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included in\n* all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n============================================================================*/\n#include \"sst.h\"           /* SST framework */\n#include \"bsp.h\"           /* Board Support Package interface */\n#include \"blinky_button.h\" /* application shared interface */\n\nDBC_MODULE_NAME(\"blinky3\") /* for DBC assertions in this module */\n\n/*..........................................................................*/\ntypedef struct {      /* Blinky3 task */\n    SST_Task super;   /* inherit SST_Task */\n    SST_TimeEvt te;   /* time event for generating TIMEOUT events */\n    uint16_t toggles; /* number of toggles to perform for TIMEOUT event */\n} Blinky3;\n\nstatic void Blinky3_ctor(Blinky3 * const me);\nstatic void Blinky3_init(Blinky3 * const me, SST_Evt const * const ie);\nstatic void Blinky3_dispatch(Blinky3 * const me, SST_Evt const * const e);\n\n/*..........................................................................*/\nstatic Blinky3 Blinky3_inst; /* the Blinky3 instance */\nSST_Task * const AO_Blinky3 = &Blinky3_inst.super; /* opaque AO pointer */\n\nvoid Blinky3_instantiate(void) {\n    Blinky3_ctor(&Blinky3_inst);\n}\n\n/*..........................................................................*/\nstatic void Blinky3_ctor(Blinky3 * const me) {\n    SST_Task_ctor(\n       &me->super,\n       (SST_Handler)&Blinky3_init,\n       (SST_Handler)&Blinky3_dispatch);\n    SST_TimeEvt_ctor(&me->te, TIMEOUT_SIG, &me->super);\n}\n/*..........................................................................*/\nstatic void Blinky3_init(Blinky3 * const me, SST_Evt const * const ie) {\n    /* the initial event must be provided and must be WORKLOAD_SIG */\n    DBC_REQUIRE(300,\n        (ie != (SST_Evt const *)0) && (ie->sig == BLINKY_WORK_SIG));\n\n    SST_TimeEvt_arm(&me->te,\n        SST_EVT_DOWNCAST(BlinkyWorkEvt, ie)->ticks,\n        SST_EVT_DOWNCAST(BlinkyWorkEvt, ie)->ticks);\n    me->toggles = SST_EVT_DOWNCAST(BlinkyWorkEvt, ie)->toggles;\n}\n/*..........................................................................*/\nstatic void Blinky3_dispatch(Blinky3 * const me, SST_Evt const * const e) {\n    switch (e->sig) {\n        case TIMEOUT_SIG: {\n            for (uint16_t i = me->toggles; i > 0U; --i) {\n                BSP_d2on();\n                BSP_d2off();\n            }\n            break;\n        }\n        case BLINKY_WORK_SIG: {\n            BSP_d2on();\n            SST_TimeEvt_arm(&me->te,\n                SST_EVT_DOWNCAST(BlinkyWorkEvt, e)->ticks,\n                SST_EVT_DOWNCAST(BlinkyWorkEvt, e)->ticks);\n            me->toggles = SST_EVT_DOWNCAST(BlinkyWorkEvt, e)->toggles;\n            BSP_d2off();\n            break;\n        }\n        default: {\n            DBC_ERROR(500); /* unexpected event */\n            break;\n        }\n    }\n}\n"
  },
  {
    "path": "sst0_c/examples/blinky_button/blinky_button.h",
    "content": "/*============================================================================\n* Super-Simple Tasker (SST/C) Example\n*\n* Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n*\n* SPDX-License-Identifier: MIT\n*\n* Permission is hereby granted, free of charge, to any person obtaining a\n* copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included in\n* all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n============================================================================*/\n#ifndef BLINKY_BUTTON_H_\n#define BLINKY_BUTTON_H_\n\n#include \"dbc_assert.h\" /* Design By Contract (DBC) assertions */\n\nenum Signals {\n    TIMEOUT_SIG,\n    BUTTON_PRESSED_SIG,\n    BUTTON_RELEASED_SIG,\n    BLINKY_WORK_SIG,\n    FORWARD_PRESSED_SIG,\n    FORWARD_RELEASED_SIG,\n    /* ... */\n    MAX_SIG  /* the last signal */\n};\n\ntypedef struct {\n    SST_Evt super;    /* inherit SST_Evt */\n    uint16_t toggles; /* number of toggles of the signal */\n    uint8_t ticks;    /* number of clock ticks between */\n} BlinkyWorkEvt;\n\ntypedef struct {\n    SST_Evt super;    /* inherit SST_Evt */\n    uint16_t toggles; /* number of toggles of the signal */\n} ButtonWorkEvt;\n\nvoid Blinky1_instantiate(void);\nextern SST_Task * const AO_Blinky1;  /* opaque task pointer */\n\nvoid Blinky3_instantiate(void);\nextern SST_Task * const AO_Blinky3;  /* opaque task pointer */\n\nvoid Button2a_instantiate(void);\nextern SST_Task * const AO_Button2a; /* opaque task pointer */\n\nvoid Button2b_instantiate(void);\nextern SST_Task * const AO_Button2b; /* opaque task pointer */\n\n#endif /* BLINKY_BUTTON_H_ */\n"
  },
  {
    "path": "sst0_c/examples/blinky_button/bsp.h",
    "content": "/*============================================================================\n* Super-Simple Tasker (SST/C) Example\n*\n* Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n*\n* SPDX-License-Identifier: MIT\n*\n* Permission is hereby granted, free of charge, to any person obtaining a\n* copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included in\n* all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n============================================================================*/\n#ifndef BSP_H_\n#define BSP_H_\n\n#define BSP_TICKS_PER_SEC 1000U\n\nvoid BSP_init(void);\n\nvoid BSP_d1on(void);\nvoid BSP_d1off(void);\n\nvoid BSP_d2on(void);\nvoid BSP_d2off(void);\n\nvoid BSP_d3on(void);\nvoid BSP_d3off(void);\n\nvoid BSP_d4on(void);\nvoid BSP_d4off(void);\n\nvoid BSP_d5on(void);\nvoid BSP_d5off(void);\n\nvoid BSP_d6on(void);\nvoid BSP_d6off(void);\n\n/* immutable events for Blinky tasks */\nSST_Evt const *BSP_getWorkEvtBlinky1(uint8_t num);\nSST_Evt const *BSP_getWorkEvtBlinky3(uint8_t num);\n\n#endif /* BSP_H_ */\n"
  },
  {
    "path": "sst0_c/examples/blinky_button/bsp_ek-tm4c123gxl.c",
    "content": "/*============================================================================\n* Super-Simple Tasker (SST0/C) Example for TivaC TM4C123GXL\n*\n*                    Q u a n t u m  L e a P s\n*                    ------------------------\n*                    Modern Embedded Software\n*\n* Copyright (C) 2005 Quantum Leaps, <state-machine.com>.\n*\n* SPDX-License-Identifier: MIT\n*\n* Permission is hereby granted, free of charge, to any person obtaining a\n* copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included in\n* all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n============================================================================*/\n#include \"sst.h\"\n#include \"bsp.h\"\n#include \"blinky_button.h\"\n\n#include \"TM4C123GH6PM.h\"  /* the device specific header (TI) */\n#include <math.h>          /* to exercise the FPU */\n/* add other drivers if necessary... */\n\nDBC_MODULE_NAME(\"bsp_ek-tm4c123gxl\") /* for DBC assertions in this module */\n\n/* Local-scope defines -----------------------------------------------------*/\n\n/* test pins on GPIOF */\n#define TST1_PIN  (1U << 1U) /* LED Red */\n#define TST2_PIN  (1U << 2U) /* LED Blue */\n\n/* test pins on GPIOD */\n#define TST3_PIN  (1U << 0U)\n#define TST4_PIN  (1U << 1U)\n#define TST5_PIN  (1U << 2U)\n\n/* test pins on GPIOF */\n#define TST6_PIN  (1U << 3U) /* LED Green */\n\n/* Button on the board on GPIOF */\n#define BTN_SW1      (1U << 4)\n\n/* ISRs used in the application ============================================*/\nvoid SysTick_Handler(void);  /* prototype */\n\nvoid SysTick_Handler(void) { /* system clock tick ISR */\n    BSP_d1on();\n\n    SST_TimeEvt_tick(); /* process all SST time events */\n\n    /* Perform the debouncing of buttons. The algorithm for debouncing\n    * adapted from the book \"Embedded Systems Dictionary\" by Jack Ganssle\n    * and Michael Barr, page 71.\n    */\n    static struct ButtonsDebouncing {\n        uint32_t depressed;\n        uint32_t previous;\n    } buttons = { 0U, 0U };\n    uint32_t current = ~GPIOF_AHB->DATA_Bits[BTN_SW1];\n    uint32_t tmp = buttons.depressed; /* save the debounced depressed */\n    buttons.depressed |= (buttons.previous & current); /* set depressed */\n    buttons.depressed &= (buttons.previous | current); /* clear released */\n    buttons.previous   = current; /* update the history */\n    tmp ^= buttons.depressed;     /* changed debounced depressed */\n    if ((tmp & BTN_SW1) != 0U) {  /* debounced SW1 state changed? */\n        if ((buttons.depressed & BTN_SW1) != 0U) { /* is SW1 depressed? */\n            /* immutable button-press event */\n            static ButtonWorkEvt const pressEvt = {\n                .super.sig = BUTTON_PRESSED_SIG,\n                .toggles = 60U\n            };\n            /* immutable forward-press event */\n            static ButtonWorkEvt const fPressEvt = {\n                .super.sig = FORWARD_PRESSED_SIG,\n                .toggles = 60U\n            };\n            SST_Task_post(AO_Button2a, &fPressEvt.super);\n            SST_Task_post(AO_Button2a, &pressEvt.super);\n        }\n        else { /* B1 is released */\n            /* immutable button-release event */\n            static ButtonWorkEvt const releaseEvt = {\n                .super.sig = BUTTON_RELEASED_SIG,\n                .toggles = 80U\n            };\n            /* immutable forward-release event */\n            static ButtonWorkEvt const fReleaseEvt = {\n                .super.sig = FORWARD_RELEASED_SIG,\n                .toggles = 80U\n            };\n            SST_Task_post(AO_Button2a, &fReleaseEvt.super);\n            SST_Task_post(AO_Button2a, &releaseEvt.super);\n        }\n    }\n\n    BSP_d1off();\n}\n\n/* Assertion handler ======================================================*/\nDBC_NORETURN\nvoid DBC_fault_handler(char const * const module, int const label) {\n    /*\n    * NOTE: add here your application-specific error handling\n    */\n    (void)module;\n    (void)label;\n\n    /* set PRIMASK to disable interrupts and stop SST right here */\n    __asm volatile (\"cpsid i\");\n\n#ifndef NDEBUG\n    for (;;) { /* keep blinking LED2 */\n        BSP_d6on();  /* turn LED2 on */\n        uint32_t volatile ctr;\n        for (ctr = 1000000U; ctr > 0U; --ctr) {\n        }\n        BSP_d6off(); /* turn LED2 off */\n        for (ctr = 1000000U; ctr > 0U; --ctr) {\n        }\n    }\n#endif\n    NVIC_SystemReset();\n}\n/*..........................................................................*/\nvoid assert_failed(char const * const module, int const label);/* prototype */\nvoid assert_failed(char const * const module, int const label) {\n    DBC_fault_handler(module, label);\n}\n\n/* BSP functions ===========================================================*/\nvoid BSP_init(void) {\n    /* Configure the MPU to prevent NULL-pointer dereferencing\n    * see: www.state-machine.com/null-pointer-protection-with-arm-cortex-m-mpu\n    */\n    MPU->RBAR = 0x0U                          /* base address (NULL) */\n                | MPU_RBAR_VALID_Msk          /* valid region */\n                | (MPU_RBAR_REGION_Msk & 7U); /* region #7 */\n    MPU->RASR = (7U << MPU_RASR_SIZE_Pos)     /* 2^(7+1) region */\n                | (0x0U << MPU_RASR_AP_Pos)   /* no-access region */\n                | MPU_RASR_ENABLE_Msk;        /* region enable */\n\n    MPU->CTRL = MPU_CTRL_PRIVDEFENA_Msk       /* enable background region */\n                | MPU_CTRL_ENABLE_Msk;        /* enable the MPU */\n    __ISB();\n    __DSB();\n\n\n    SYSCTL->RCGCGPIO  |= (1U << 5U); /* enable Run mode for GPIOF */\n    SYSCTL->RCGCGPIO  |= (1U << 3U); /* enable Run mode for GPIOD */\n    __ISB();\n    __DSB();\n\n    SYSCTL->GPIOHBCTL |= (1U << 5); /* enable AHB for GPIOF */\n    SYSCTL->GPIOHBCTL |= (1U << 3); /* enable AHB for GPIOD */\n    __ISB();\n    __DSB();\n\n    /* configure test pins on GPIOF (digital output) */\n    GPIOF_AHB->DIR |= (TST1_PIN | TST2_PIN | TST6_PIN);\n    GPIOF_AHB->DEN |= (TST1_PIN | TST2_PIN | TST6_PIN);\n\n    /* configure button on GPIOF (digital input) */\n    GPIOF_AHB->DIR &= ~(BTN_SW1); /* input */\n    GPIOF_AHB->DEN |= (BTN_SW1); /* digital enable */\n    GPIOF_AHB->PUR |= (BTN_SW1); /* pull-up resistor enable */\n\n    /* configure test pins on GPIOD (digital output) */\n    GPIOD_AHB->DIR |= (TST3_PIN | TST4_PIN | TST5_PIN);\n    GPIOD_AHB->DEN |= (TST3_PIN | TST4_PIN | TST5_PIN);\n}\n\n/*..........................................................................*/\n#if defined __ARMCC_VERSION\n#elif defined __GNUC__\nuint32_t __errno; /* GNU-ARM needs this to link sqrtf() */\n#endif\n\nstatic void exerciseFPU(float x) {\n    /* exercise the single-precision FPU by calculating the identity:\n    *  sqrt(x) == x / sqrt(x) for x > 0\n    */\n    float tmp1 = sqrtf(x); /* single-precision sqrt() */\n    float tmp2 = x / tmp1;\n    DBC_ENSURE(200, (tmp1 - 1e-4f <= tmp2) && (tmp2 <= tmp1 + 1e-4f));\n}\n\n/*..........................................................................*/\nvoid BSP_d1on(void) { /* LED-Red */\n    GPIOF_AHB->DATA_Bits[TST1_PIN] = 0xFFU;\n    /* don't use the FPU in the ISR */\n}\nvoid BSP_d1off(void) {\n    GPIOF_AHB->DATA_Bits[TST1_PIN] = 0x00U;\n}\n/*..........................................................................*/\nvoid BSP_d2on(void) { /* LED-Blue */\n    GPIOF_AHB->DATA_Bits[TST2_PIN] = 0xFFU;\n    exerciseFPU(1.2345f);\n}\nvoid BSP_d2off(void) {\n    GPIOF_AHB->DATA_Bits[TST2_PIN] = 0x00U;\n}\n/*..........................................................................*/\nvoid BSP_d3on(void) {\n    GPIOD_AHB->DATA_Bits[TST3_PIN] = 0xFFU;\n    exerciseFPU(0.345f);\n}\nvoid BSP_d3off(void) {\n    GPIOD_AHB->DATA_Bits[TST3_PIN] = 0x00U;\n}\n/*..........................................................................*/\nvoid BSP_d4on(void) {\n    GPIOD_AHB->DATA_Bits[TST4_PIN] = 0xFFU;\n    exerciseFPU(0.456f);\n}\nvoid BSP_d4off(void) {\n    GPIOD_AHB->DATA_Bits[TST4_PIN] = 0x00U;\n}\n/*..........................................................................*/\nvoid BSP_d5on(void) {\n    GPIOD_AHB->DATA_Bits[TST5_PIN] = 0xFFU;\n    exerciseFPU(1.567f);\n}\nvoid BSP_d5off(void) {\n    GPIOD_AHB->DATA_Bits[TST5_PIN] = 0x00U;\n}\n/*..........................................................................*/\nvoid BSP_d6on(void) {  /* LED2-Green */\n    GPIOF_AHB->DATA_Bits[TST6_PIN] = 0xFFU;\n    exerciseFPU(1.2345f);\n}\nvoid BSP_d6off(void) {\n    GPIOF_AHB->DATA_Bits[TST6_PIN] = 0x00U;\n}\n\n/*..........................................................................*/\nSST_Evt const *BSP_getWorkEvtBlinky1(uint8_t num) {\n    /* immutable work events for Blinky1 */\n    static BlinkyWorkEvt const workBlinky1[] = {\n        {\n            .super.sig = BLINKY_WORK_SIG,\n            .toggles = 40U,\n            .ticks = 5U,\n        },\n        {\n            .super.sig = BLINKY_WORK_SIG,\n            .toggles = 30U,\n            .ticks = 7U,\n        }\n    };\n    DBC_REQUIRE(500, num < ARRAY_NELEM(workBlinky1)); /* must be in range */\n    return &workBlinky1[num].super;\n}\n/*..........................................................................*/\nSST_Evt const *BSP_getWorkEvtBlinky3(uint8_t num) {\n    /* immutable work events for Blinky3 */\n    static BlinkyWorkEvt const workBlinky3[] = {\n        {\n            .super.sig = BLINKY_WORK_SIG,\n            .toggles = 20U,\n            .ticks = 5U,\n        },\n        {\n            .super.sig = BLINKY_WORK_SIG,\n            .toggles = 10U,\n            .ticks = 3U,\n        }\n    };\n    DBC_REQUIRE(600, num < ARRAY_NELEM(workBlinky3)); /* must be in range */\n    return &workBlinky3[num].super;\n}\n\n/* SST callbacks ===========================================================*/\nvoid SST_onStart(void) {\n    SystemCoreClockUpdate();\n\n    /* set up the SysTick timer to fire at BSP_TICKS_PER_SEC rate */\n    SysTick_Config((SystemCoreClock / BSP_TICKS_PER_SEC) + 1U);\n\n    /* set priorities of ISRs used in the system */\n    NVIC_SetPriority(SysTick_IRQn, 0U);\n    /* ... */\n}\n/*..........................................................................*/\nvoid SST_onIdleCond(void) { /* NOTE: called with interrupts DISABLED */\n    BSP_d6on();  /* turn LED-Green on */\n#ifdef NDEBUG\n    /* Put the CPU and peripherals to the low-power mode.\n    * you might need to customize the clock management for your application,\n    * see the datasheet for your particular Cortex-M MCU.\n    */\n    BSP_d6off(); /* turn LED-Green off */\n    __WFI(); /* Wait-For-Interrupt */\n    BSP_d6on();  /* turn LED-Green on */\n#endif\n    BSP_d6off(); /* turn LED-Green off */\n    SST_PORT_INT_ENABLE(); /* NOTE: enable interrupts for SS0 */\n}\n\n"
  },
  {
    "path": "sst0_c/examples/blinky_button/bsp_nucleo-c031c6.c",
    "content": "/*============================================================================\n* Super-Simple Tasker (SST0/C) Example for STM32 NUCLEO-C031C6\n*\n*                    Q u a n t u m  L e a P s\n*                    ------------------------\n*                    Modern Embedded Software\n*\n* Copyright (C) 2005 Quantum Leaps, <state-machine.com>.\n*\n* SPDX-License-Identifier: MIT\n*\n* Permission is hereby granted, free of charge, to any person obtaining a\n* copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included in\n* all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n============================================================================*/\n#include \"sst.h\"\n#include \"bsp.h\"\n#include \"blinky_button.h\"\n\n#include \"stm32c0xx.h\"  /* CMSIS-compliant header file for the MCU used */\n/* add other drivers if necessary... */\n\nDBC_MODULE_NAME(\"bsp_nucleo-c031c6\")\n\n/* Local-scope defines -----------------------------------------------------*/\n/* test pins on GPIO PA */\n#define TST1_PIN  7U\n#define TST2_PIN  6U\n#define TST3_PIN  4U\n#define TST4_PIN  1U\n#define TST5_PIN  0U\n#define TST6_PIN  5U /* LED L4-Green */\n\n/* buttons on GPIO PC */\n#define B1_PIN    13U\n\n/* ISRs used in the application ============================================*/\nvoid SysTick_Handler(void);  /* prototype */\n\nvoid SysTick_Handler(void) { /* system clock tick ISR */\n    BSP_d1on();\n\n    SST_TimeEvt_tick(); /* process all SST time events */\n\n    /* Perform the debouncing of buttons. The algorithm for debouncing\n    * adapted from the book \"Embedded Systems Dictionary\" by Jack Ganssle\n    * and Michael Barr, page 71.\n    */\n    static struct ButtonsDebouncing {\n        uint32_t depressed;\n        uint32_t previous;\n    } buttons = { 0U, 0U };\n    uint32_t current = ~GPIOC->IDR; /* read GPIO PortC */\n    uint32_t tmp = buttons.depressed; /* save the debounced depressed */\n    buttons.depressed |= (buttons.previous & current); /* set depressed */\n    buttons.depressed &= (buttons.previous | current); /* clear released */\n    buttons.previous   = current; /* update the history */\n    tmp ^= buttons.depressed;     /* changed debounced depressed */\n    if ((tmp & (1U << B1_PIN)) != 0U) { /* debounced B1 state changed? */\n        if ((buttons.depressed & (1U << B1_PIN)) != 0U) { /* depressed? */\n            /* immutable button-press event */\n            static ButtonWorkEvt const pressEvt = {\n                .super.sig = BUTTON_PRESSED_SIG,\n                .toggles = 60U\n            };\n            /* immutable forward-press event */\n            static ButtonWorkEvt const fPressEvt = {\n                .super.sig = FORWARD_PRESSED_SIG,\n                .toggles = 60U\n            };\n            SST_Task_post(AO_Button2a, &fPressEvt.super);\n            SST_Task_post(AO_Button2a, &pressEvt.super);\n        }\n        else { /* B1 is released */\n            /* immutable button-release event */\n            static ButtonWorkEvt const releaseEvt = {\n                .super.sig = BUTTON_RELEASED_SIG,\n                .toggles = 80U\n            };\n            /* immutable forward-release event */\n            static ButtonWorkEvt const fReleaseEvt = {\n                .super.sig = FORWARD_RELEASED_SIG,\n                .toggles = 80U\n            };\n            SST_Task_post(AO_Button2a, &fReleaseEvt.super);\n            SST_Task_post(AO_Button2a, &releaseEvt.super);\n        }\n    }\n\n    BSP_d1off();\n}\n\n/* Assertion handler ======================================================*/\nDBC_NORETURN\nvoid DBC_fault_handler(char const * const module, int const label) {\n    /*\n    * NOTE: add here your application-specific error handling\n    */\n    (void)module;\n    (void)label;\n\n    /* set PRIMASK to disable interrupts and stop SST right here */\n    __asm volatile (\"cpsid i\");\n\n#ifndef NDEBUG\n    for (;;) { /* keep blinking LED2 */\n        BSP_d6on();  /* turn LD4 on */\n        uint32_t volatile ctr;\n        for (ctr = 100000U; ctr > 0U; --ctr) {\n        }\n        BSP_d6off(); /* turn LD4 off */\n        for (ctr = 100000U; ctr > 0U; --ctr) {\n        }\n    }\n#endif\n    NVIC_SystemReset();\n}\n/*..........................................................................*/\nvoid assert_failed(char const * const module, int const label);/* prototype */\nvoid assert_failed(char const * const module, int const label) {\n    DBC_fault_handler(module, label);\n}\n\n/* BSP functions ===========================================================*/\nvoid BSP_init(void) {\n    /* Configure the MPU to prevent NULL-pointer dereferencing\n    * see: www.state-machine.com/null-pointer-protection-with-arm-cortex-m-mpu\n    */\n    MPU->RBAR = 0x0U                          /* base address (NULL) */\n                | MPU_RBAR_VALID_Msk          /* valid region */\n                | (MPU_RBAR_REGION_Msk & 7U); /* region #7 */\n    MPU->RASR = (7U << MPU_RASR_SIZE_Pos)     /* 2^(7+1) region */\n                | (0x0U << MPU_RASR_AP_Pos)   /* no-access region */\n                | MPU_RASR_ENABLE_Msk;        /* region enable */\n\n    MPU->CTRL = MPU_CTRL_PRIVDEFENA_Msk       /* enable background region */\n                | MPU_CTRL_ENABLE_Msk;        /* enable the MPU */\n    __ISB();\n    __DSB();\n\n    /* enable GPIO port PA clock */\n    RCC->IOPENR |= (1U << 0U);\n\n    /* set all used GPIOA pins as push-pull output, no pull-up, pull-down */\n    GPIOA->MODER &=\n        ~((3U << 2U*TST1_PIN) | (3U << 2U*TST2_PIN) | (3U << 2U*TST3_PIN) |\n          (3U << 2U*TST4_PIN) | (3U << 2U*TST5_PIN) | (3U << 2U*TST6_PIN));\n    GPIOA->MODER |=\n         ((1U << 2U*TST1_PIN) | (1U << 2U*TST2_PIN) | (1U << 2U*TST3_PIN) |\n          (1U << 2U*TST4_PIN) | (1U << 2U*TST5_PIN) | (1U << 2U*TST6_PIN));\n    GPIOA->OTYPER &=\n        ~((1U <<    TST1_PIN) | (1U <<    TST2_PIN) | (1U <<    TST3_PIN) |\n          (1U <<    TST4_PIN) | (1U <<    TST5_PIN) | (1U <<    TST6_PIN));\n    GPIOA->OSPEEDR &=\n        ~((3U << 2U*TST1_PIN) | (3U << 2U*TST2_PIN) | (3U << 2U*TST3_PIN) |\n          (3U << 2U*TST4_PIN) | (3U << 2U*TST5_PIN) | (3U << 2U*TST6_PIN));\n    GPIOA->OSPEEDR |=\n         ((1U << 2U*TST1_PIN) | (1U << 2U*TST2_PIN) | (1U << 2U*TST3_PIN) |\n          (1U << 2U*TST4_PIN) | (1U << 2U*TST5_PIN) | (1U << 2U*TST6_PIN));\n   GPIOA->PUPDR &=\n        ~((3U << 2U*TST1_PIN) | (3U << 2U*TST2_PIN) | (3U << 2U*TST3_PIN) |\n          (3U << 2U*TST4_PIN) | (3U << 2U*TST5_PIN) | (3U << 2U*TST6_PIN));\n\n    /* enable GPIOC clock port for the Button B1 */\n    RCC->IOPENR |=  (1U << 2U);\n\n    /* configure Button B1 pin on GPIOC as input, no pull-up, pull-down */\n    GPIOC->MODER &= ~(3U << 2U*B1_PIN);\n    GPIOC->PUPDR &= ~(3U << 2U*B1_PIN);\n}\n\n/*..........................................................................*/\nvoid BSP_d1on(void)  { GPIOA->BSRR = (1U << TST1_PIN);         }\nvoid BSP_d1off(void) { GPIOA->BSRR = (1U << (TST1_PIN + 16U)); }\n/*..........................................................................*/\nvoid BSP_d2on(void)  { GPIOA->BSRR = (1U << TST2_PIN);         }\nvoid BSP_d2off(void) { GPIOA->BSRR = (1U << (TST2_PIN + 16U)); }\n/*..........................................................................*/\nvoid BSP_d3on(void)  { GPIOA->BSRR = (1U << TST3_PIN);         }\nvoid BSP_d3off(void) { GPIOA->BSRR = (1U << (TST3_PIN + 16U)); }\n/*..........................................................................*/\nvoid BSP_d4on(void)  { GPIOA->BSRR = (1U << TST4_PIN);         }\nvoid BSP_d4off(void) { GPIOA->BSRR = (1U << (TST4_PIN + 16U)); }\n/*..........................................................................*/\nvoid BSP_d5on(void)  { GPIOA->BSRR = (1U << TST5_PIN);         }\nvoid BSP_d5off(void) { GPIOA->BSRR = (1U << (TST5_PIN + 16U)); }\n/*..........................................................................*/\nvoid BSP_d6on(void)  { GPIOA->BSRR = (1U << TST6_PIN);         } /* LD4 */\nvoid BSP_d6off(void) { GPIOA->BSRR = (1U << (TST6_PIN + 16U)); }\n\n/*..........................................................................*/\nSST_Evt const *BSP_getWorkEvtBlinky1(uint8_t num) {\n    /* immutable work events for Blinky1 */\n    static BlinkyWorkEvt const workBlinky1[] = {\n        {\n            .super.sig = BLINKY_WORK_SIG,\n            .toggles = 40U,\n            .ticks = 5U,\n        },\n        {\n            .super.sig = BLINKY_WORK_SIG,\n            .toggles = 30U,\n            .ticks = 7U,\n        }\n    };\n    DBC_REQUIRE(500, num < ARRAY_NELEM(workBlinky1)); /* must be in range */\n    return &workBlinky1[num].super;\n}\n/*..........................................................................*/\nSST_Evt const *BSP_getWorkEvtBlinky3(uint8_t num) {\n    /* immutable work events for Blinky3 */\n    static BlinkyWorkEvt const workBlinky3[] = {\n        {\n            .super.sig = BLINKY_WORK_SIG,\n            .toggles = 20U,\n            .ticks = 5U,\n        },\n        {\n            .super.sig = BLINKY_WORK_SIG,\n            .toggles = 10U,\n            .ticks = 3U,\n        }\n    };\n    DBC_REQUIRE(600, num < ARRAY_NELEM(workBlinky3)); /* must be in range */\n    return &workBlinky3[num].super;\n}\n\n/* SST callbacks ===========================================================*/\nvoid SST_onStart(void) {\n    SystemCoreClockUpdate();\n\n    /* set up the SysTick timer to fire at BSP_TICKS_PER_SEC rate */\n    SysTick_Config((SystemCoreClock / BSP_TICKS_PER_SEC) + 1U);\n\n    /* set priorities of ISRs used in the system */\n    NVIC_SetPriority(SysTick_IRQn, 0U);\n    /* ... */\n}\n/*..........................................................................*/\nvoid SST_onIdleCond(void) { /* NOTE: called with interrupts DISABLED */\n    BSP_d6on();  /* turn LED2 on */\n#ifdef NDEBUG\n    /* Put the CPU and peripherals to the low-power mode.\n    * you might need to customize the clock management for your application,\n    * see the datasheet for your particular Cortex-M MCU.\n    */\n    BSP_d6off(); /* turn LED2 off */\n    __WFI(); /* Wait-For-Interrupt */\n    BSP_d6on();  /* turn LED2 on */\n#endif\n    BSP_d6off(); /* turn LED2 off */\n    SST_PORT_INT_ENABLE(); /* NOTE: enable interrupts for SS0 */\n}\n\n"
  },
  {
    "path": "sst0_c/examples/blinky_button/bsp_nucleo-h743zi.c",
    "content": "/*============================================================================\n* Super-Simple Tasker (SST0/C) Example for STM32 NUCLEO-H743ZI\n*\n*                    Q u a n t u m  L e a P s\n*                    ------------------------\n*                    Modern Embedded Software\n*\n* Copyright (C) 2005 Quantum Leaps, <state-machine.com>.\n*\n* SPDX-License-Identifier: MIT\n*\n* Permission is hereby granted, free of charge, to any person obtaining a\n* copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included in\n* all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n============================================================================*/\n#include \"sst.h\"\n#include \"bsp.h\"\n#include \"blinky_button.h\"\n\n#include \"stm32h743xx.h\"  /* CMSIS-compliant header file for the MCU used */\n#include <math.h>         /* to exercise the FPU */\n/* add other drivers if necessary... */\n\nDBC_MODULE_NAME(\"bsp_nucleo-h743zi\") /* for DBC assertions in this module */\n\n/* Local-scope defines -----------------------------------------------------*/\n\n/* test pins on GPIO PB */\n#define TST1_PIN  0U  /* PB.0  LED1-Green */\n#define TST2_PIN  14U /* PB.14 LED3-Red   */\n#define TST3_PIN  4U\n#define TST4_PIN  5U\n#define TST5_PIN  6U\n#define TST6_PIN  7U  /* PB.7  LED2-Blue  */\n\n/* buttons on GPIO PC */\n#define B1_PIN    13U\n\n/* ISRs used in the application ============================================*/\nvoid SysTick_Handler(void);  /* prototype */\n\nvoid SysTick_Handler(void) { /* system clock tick ISR */\n    BSP_d1on();\n\n    SST_TimeEvt_tick(); /* process all SST time events */\n\n    /* Perform the debouncing of buttons. The algorithm for debouncing\n    * adapted from the book \"Embedded Systems Dictionary\" by Jack Ganssle\n    * and Michael Barr, page 71.\n    */\n    static struct ButtonsDebouncing {\n        uint32_t depressed;\n        uint32_t previous;\n    } buttons = { 0U, 0U };\n    uint32_t current = GPIOC->IDR; /* read GPIO PortC */\n    uint32_t tmp = buttons.depressed; /* save the debounced depressed */\n    buttons.depressed |= (buttons.previous & current); /* set depressed */\n    buttons.depressed &= (buttons.previous | current); /* clear released */\n    buttons.previous   = current; /* update the history */\n    tmp ^= buttons.depressed;     /* changed debounced depressed */\n    if ((tmp & (1U << B1_PIN)) != 0U) { /* debounced B1 state changed? */\n        if ((buttons.depressed & (1U << B1_PIN)) != 0U) { /* depressed? */\n            /* immutable button-press event */\n            static ButtonWorkEvt const pressEvt = {\n                .super.sig = BUTTON_PRESSED_SIG,\n                .toggles = 60U\n            };\n            /* immutable forward-press event */\n            static ButtonWorkEvt const fPressEvt = {\n                .super.sig = FORWARD_PRESSED_SIG,\n                .toggles = 60U\n            };\n            SST_Task_post(AO_Button2a, &fPressEvt.super);\n            SST_Task_post(AO_Button2a, &pressEvt.super);\n        }\n        else { /* B1 is released */\n            /* immutable button-release event */\n            static ButtonWorkEvt const releaseEvt = {\n                .super.sig = BUTTON_RELEASED_SIG,\n                .toggles = 80U\n            };\n            /* immutable forward-release event */\n            static ButtonWorkEvt const fReleaseEvt = {\n                .super.sig = FORWARD_RELEASED_SIG,\n                .toggles = 80U\n            };\n            SST_Task_post(AO_Button2a, &fReleaseEvt.super);\n            SST_Task_post(AO_Button2a, &releaseEvt.super);\n        }\n    }\n\n    BSP_d1off();\n}\n\n/* Assertion handler ======================================================*/\nDBC_NORETURN\nvoid DBC_fault_handler(char const * const module, int const label) {\n    /*\n    * NOTE: add here your application-specific error handling\n    */\n    (void)module;\n    (void)label;\n\n    /* set PRIMASK to disable interrupts and stop SST right here */\n    __asm volatile (\"cpsid i\");\n\n#ifndef NDEBUG\n    for (;;) { /* keep blinking LED2 */\n        BSP_d6on();  /* turn LED2 on */\n        uint32_t volatile ctr;\n        for (ctr = 1000000U; ctr > 0U; --ctr) {\n        }\n        BSP_d6off(); /* turn LED2 off */\n        for (ctr = 1000000U; ctr > 0U; --ctr) {\n        }\n    }\n#endif\n    NVIC_SystemReset();\n}\n/*..........................................................................*/\nvoid assert_failed(char const * const module, int const label);/* prototype */\nvoid assert_failed(char const * const module, int const label) {\n    DBC_fault_handler(module, label);\n}\n\n/* BSP functions ===========================================================*/\nvoid BSP_init(void) {\n    /* Configure the MPU to prevent NULL-pointer dereferencing\n    * see: www.state-machine.com/null-pointer-protection-with-arm-cortex-m-mpu\n    */\n    MPU->RBAR = 0x0U                          /* base address (NULL) */\n                | MPU_RBAR_VALID_Msk          /* valid region */\n                | (MPU_RBAR_REGION_Msk & 7U); /* region #7 */\n    MPU->RASR = (7U << MPU_RASR_SIZE_Pos)     /* 2^(7+1) region */\n                | (0x0U << MPU_RASR_AP_Pos)   /* no-access region */\n                | MPU_RASR_ENABLE_Msk;        /* region enable */\n\n    MPU->CTRL = MPU_CTRL_PRIVDEFENA_Msk       /* enable background region */\n                | MPU_CTRL_ENABLE_Msk;        /* enable the MPU */\n    __ISB();\n    __DSB();\n\n    SCB_EnableICache(); /* Enable I-Cache */\n    SCB_EnableDCache(); /* Enable D-Cache */\n\n    /* enable GPIOB port clock for LEds and test pins */\n    RCC->AHB4ENR |= RCC_AHB4ENR_GPIOBEN;\n\n    /* set all used GPIOB pins as push-pull output, no pull-up, pull-down */\n    GPIOB->MODER &=\n        ~((3U << 2U*TST1_PIN) | (3U << 2U*TST2_PIN) | (3U << 2U*TST3_PIN) |\n          (3U << 2U*TST4_PIN) | (3U << 2U*TST5_PIN) | (3U << 2U*TST6_PIN));\n    GPIOB->MODER |=\n         ((1U << 2U*TST1_PIN) | (1U << 2U*TST2_PIN) | (1U << 2U*TST3_PIN) |\n          (1U << 2U*TST4_PIN) | (1U << 2U*TST5_PIN) | (1U << 2U*TST6_PIN));\n    GPIOB->OTYPER &=\n        ~((1U <<    TST1_PIN) | (1U <<    TST2_PIN) | (1U <<    TST3_PIN) |\n          (1U <<    TST4_PIN) | (1U <<    TST5_PIN) | (1U <<    TST6_PIN));\n    GPIOB->PUPDR &=\n        ~((3U << 2U*TST1_PIN) | (3U << 2U*TST2_PIN) | (3U << 2U*TST3_PIN) |\n          (3U << 2U*TST4_PIN) | (3U << 2U*TST5_PIN) | (3U << 2U*TST6_PIN));\n\n    /* enable GPIOC clock port for the Button B1 */\n    RCC->AHB4ENR |= RCC_AHB4ENR_GPIOCEN;\n\n    /* configure Button B1 pin on GPIOC as input, no pull-up, pull-down */\n    GPIOC->MODER   &= ~(3U << 2U*B1_PIN);\n    GPIOC->PUPDR   &= ~(GPIO_PUPDR_PUPD0 << 2U*B1_PIN);\n    GPIOC->PUPDR   |=  (2U << 2U*B1_PIN);\n}\n\n/*..........................................................................*/\nstatic void exerciseFPU(double x) {\n    /* exercise the double-precision FPU by calculating the identity:\n    *  sin(x)^2 + cos(x)^2 == 1.0 for any x\n    */\n    double tmp = pow(sin(x), 2.0) + pow(cos(x), 2.0);\n    DBC_ENSURE(200, (1.0 - 1e-4 < tmp) && (tmp < 1.0 + 1e-4));\n}\n\n/*..........................................................................*/\nvoid BSP_d1on(void) {  /* LED1-Green */\n    GPIOB->BSRR = (1U << TST1_PIN);\n    /* don't use the FPU in the ISR */\n}\nvoid BSP_d1off(void) {\n    GPIOB->BSRR = (1U << (TST1_PIN + 16U));\n}\n/*..........................................................................*/\nvoid BSP_d2on(void) {  /* LED3-Red */\n    GPIOB->BSRR = (1U << TST2_PIN);\n    exerciseFPU(-1.2345);\n}\nvoid BSP_d2off(void) {\n    GPIOB->BSRR = (1U << (TST2_PIN + 16U));\n}\n/*..........................................................................*/\nvoid BSP_d3on(void) {\n    GPIOB->BSRR = (1U << TST3_PIN);\n    exerciseFPU(-12.345);\n}\nvoid BSP_d3off(void) {\n    GPIOB->BSRR = (1U << (TST3_PIN + 16U));\n}\n/*..........................................................................*/\nvoid BSP_d4on(void) {\n    GPIOB->BSRR = (1U << TST4_PIN);\n    exerciseFPU(3.456);\n}\nvoid BSP_d4off(void) {\n    GPIOB->BSRR = (1U << (TST4_PIN + 16U));\n}\n/*..........................................................................*/\nvoid BSP_d5on(void) {\n    GPIOB->BSRR = (1U << TST5_PIN);\n    exerciseFPU(4.567);\n}\nvoid BSP_d5off(void) {\n    GPIOB->BSRR = (1U << (TST5_PIN + 16U));\n}\n/*..........................................................................*/\nvoid BSP_d6on(void) {  /* LED2-Blue */\n    GPIOB->BSRR = (1U << TST6_PIN);\n    exerciseFPU(1.2345);\n}\nvoid BSP_d6off(void) {\n    GPIOB->BSRR = (1U << (TST6_PIN + 16U));\n}\n\n/*..........................................................................*/\nSST_Evt const *BSP_getWorkEvtBlinky1(uint8_t num) {\n    /* immutable work events for Blinky1 */\n    static BlinkyWorkEvt const workBlinky1[] = {\n        {\n            .super.sig = BLINKY_WORK_SIG,\n            .toggles = 40U,\n            .ticks = 5U,\n        },\n        {\n            .super.sig = BLINKY_WORK_SIG,\n            .toggles = 30U,\n            .ticks = 7U,\n        }\n    };\n    DBC_REQUIRE(500, num < ARRAY_NELEM(workBlinky1)); /* must be in range */\n    return &workBlinky1[num].super;\n}\n/*..........................................................................*/\nSST_Evt const *BSP_getWorkEvtBlinky3(uint8_t num) {\n    /* immutable work events for Blinky3 */\n    static BlinkyWorkEvt const workBlinky3[] = {\n        {\n            .super.sig = BLINKY_WORK_SIG,\n            .toggles = 20U,\n            .ticks = 5U,\n        },\n        {\n            .super.sig = BLINKY_WORK_SIG,\n            .toggles = 10U,\n            .ticks = 3U,\n        }\n    };\n    DBC_REQUIRE(600, num < ARRAY_NELEM(workBlinky3)); /* must be in range */\n    return &workBlinky3[num].super;\n}\n\n/* SST callbacks ===========================================================*/\nvoid SST_onStart(void) {\n    SystemCoreClockUpdate();\n\n    /* set up the SysTick timer to fire at BSP_TICKS_PER_SEC rate */\n    SysTick_Config((SystemCoreClock / BSP_TICKS_PER_SEC) + 1U);\n\n    /* set priorities of ISRs used in the system */\n    NVIC_SetPriority(SysTick_IRQn, 0U);\n    /* ... */\n}\n/*..........................................................................*/\nvoid SST_onIdleCond(void) { /* NOTE: called with interrupts DISABLED */\n    BSP_d6on();  /* turn LED2 on */\n#ifdef NDEBUG\n    /* Put the CPU and peripherals to the low-power mode.\n    * you might need to customize the clock management for your application,\n    * see the datasheet for your particular Cortex-M MCU.\n    */\n    BSP_d6off(); /* turn LED2 off */\n    __WFI(); /* Wait-For-Interrupt */\n    BSP_d6on();  /* turn LED2 on */\n#endif\n    BSP_d6off(); /* turn LED2 off */\n    SST_PORT_INT_ENABLE(); /* NOTE: enable interrupts for SS0 */\n}\n\n"
  },
  {
    "path": "sst0_c/examples/blinky_button/bsp_nucleo-l053r8.c",
    "content": "/*============================================================================\n* Super-Simple Tasker (SST0/C) Example for STM32 NUCLEO-L053R8\n*\n*                    Q u a n t u m  L e a P s\n*                    ------------------------\n*                    Modern Embedded Software\n*\n* Copyright (C) 2005 Quantum Leaps, <state-machine.com>.\n*\n* SPDX-License-Identifier: MIT\n*\n* Permission is hereby granted, free of charge, to any person obtaining a\n* copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included in\n* all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n============================================================================*/\n#include \"sst.h\"\n#include \"bsp.h\"\n#include \"blinky_button.h\"\n\n#include \"stm32l0xx.h\"  /* CMSIS-compliant header file for the MCU used */\n/* add other drivers if necessary... */\n\nDBC_MODULE_NAME(\"bsp_nucleo-l053r8\") /* for DBC assertions in this module */\n\n/* Local-scope defines -----------------------------------------------------*/\n\n/* test pins on GPIO PA */\n#define TST1_PIN  7U\n#define TST2_PIN  6U\n#define TST3_PIN  4U\n#define TST4_PIN  1U\n#define TST5_PIN  0U\n#define TST6_PIN  5U /* LED LD2-Green */\n\n/* buttons on GPIO PC */\n#define B1_PIN    13U\n\n/* ISRs used in the application ============================================*/\nvoid SysTick_Handler(void);  /* prototype */\n\nvoid SysTick_Handler(void) { /* system clock tick ISR */\n    BSP_d1on();\n\n    SST_TimeEvt_tick(); /* process all SST time events */\n\n    /* Perform the debouncing of buttons. The algorithm for debouncing\n    * adapted from the book \"Embedded Systems Dictionary\" by Jack Ganssle\n    * and Michael Barr, page 71.\n    */\n    static struct ButtonsDebouncing {\n        uint32_t depressed;\n        uint32_t previous;\n    } buttons = { 0U, 0U };\n    uint32_t current = ~GPIOC->IDR; /* read GPIO PortC */\n    uint32_t tmp = buttons.depressed; /* save the debounced depressed */\n    buttons.depressed |= (buttons.previous & current); /* set depressed */\n    buttons.depressed &= (buttons.previous | current); /* clear released */\n    buttons.previous   = current; /* update the history */\n    tmp ^= buttons.depressed;     /* changed debounced depressed */\n    if ((tmp & (1U << B1_PIN)) != 0U) { /* debounced B1 state changed? */\n        if ((buttons.depressed & (1U << B1_PIN)) != 0U) { /* depressed? */\n            /* immutable button-press event */\n            static ButtonWorkEvt const pressEvt = {\n                .super.sig = BUTTON_PRESSED_SIG,\n                .toggles = 60U\n            };\n            /* immutable forward-press event */\n            static ButtonWorkEvt const fPressEvt = {\n                .super.sig = FORWARD_PRESSED_SIG,\n                .toggles = 60U\n            };\n            SST_Task_post(AO_Button2a, &fPressEvt.super);\n            SST_Task_post(AO_Button2a, &pressEvt.super);\n        }\n        else { /* B1 is released */\n            /* immutable button-release event */\n            static ButtonWorkEvt const releaseEvt = {\n                .super.sig = BUTTON_RELEASED_SIG,\n                .toggles = 80U\n            };\n            /* immutable forward-release event */\n            static ButtonWorkEvt const fReleaseEvt = {\n                .super.sig = FORWARD_RELEASED_SIG,\n                .toggles = 80U\n            };\n            SST_Task_post(AO_Button2a, &fReleaseEvt.super);\n            SST_Task_post(AO_Button2a, &releaseEvt.super);\n        }\n    }\n\n    BSP_d1off();\n}\n\n/* Assertion handler ======================================================*/\nDBC_NORETURN\nvoid DBC_fault_handler(char const * const module, int const label) {\n    /*\n    * NOTE: add here your application-specific error handling\n    */\n    (void)module;\n    (void)label;\n\n    /* set PRIMASK to disable interrupts and stop SST right here */\n    __asm volatile (\"cpsid i\");\n\n#ifndef NDEBUG\n    for (;;) { /* keep blinking LED2 */\n        BSP_d6on();  /* turn LED2 on */\n        uint32_t volatile ctr;\n        for (ctr = 10000U; ctr > 0U; --ctr) {\n        }\n        BSP_d6off(); /* turn LED2 off */\n        for (ctr = 10000U; ctr > 0U; --ctr) {\n        }\n    }\n#endif\n    NVIC_SystemReset();\n}\n/*..........................................................................*/\nvoid assert_failed(char const * const module, int const label);/* prototype */\nvoid assert_failed(char const * const module, int const label) {\n    DBC_fault_handler(module, label);\n}\n\n/* BSP functions ===========================================================*/\nvoid BSP_init(void) {\n    /* Configure the MPU to prevent NULL-pointer dereferencing\n    * see: www.state-machine.com/null-pointer-protection-with-arm-cortex-m-mpu\n    */\n    MPU->RBAR = 0x0U                          /* base address (NULL) */\n                | MPU_RBAR_VALID_Msk          /* valid region */\n                | (MPU_RBAR_REGION_Msk & 7U); /* region #7 */\n    MPU->RASR = (7U << MPU_RASR_SIZE_Pos)     /* 2^(7+1) region */\n                | (0x0U << MPU_RASR_AP_Pos)   /* no-access region */\n                | MPU_RASR_ENABLE_Msk;        /* region enable */\n\n    MPU->CTRL = MPU_CTRL_PRIVDEFENA_Msk       /* enable background region */\n                | MPU_CTRL_ENABLE_Msk;        /* enable the MPU */\n    __ISB();\n    __DSB();\n\n\n    /* enable GPIO port PA clock */\n    RCC->IOPENR |= (1U << 0U);\n\n    /* set all used GPIOA pins as push-pull output, no pull-up, pull-down */\n    GPIOA->MODER &=\n        ~((3U << 2U*TST1_PIN) | (3U << 2U*TST2_PIN) | (3U << 2U*TST3_PIN) |\n          (3U << 2U*TST4_PIN) | (3U << 2U*TST5_PIN) | (3U << 2U*TST6_PIN));\n    GPIOA->MODER |=\n         ((1U << 2U*TST1_PIN) | (1U << 2U*TST2_PIN) | (1U << 2U*TST3_PIN) |\n          (1U << 2U*TST4_PIN) | (1U << 2U*TST5_PIN) | (1U << 2U*TST6_PIN));\n    GPIOA->OTYPER &=\n        ~((1U <<    TST1_PIN) | (1U <<    TST2_PIN) | (1U <<    TST3_PIN) |\n          (1U <<    TST4_PIN) | (1U <<    TST5_PIN) | (1U <<    TST6_PIN));\n    GPIOA->PUPDR &=\n        ~((3U << 2U*TST1_PIN) | (3U << 2U*TST2_PIN) | (3U << 2U*TST3_PIN) |\n          (3U << 2U*TST4_PIN) | (3U << 2U*TST5_PIN) | (3U << 2U*TST6_PIN));\n\n    /* enable GPIOC clock port for the Button B1 */\n    RCC->IOPENR |=  (1U << 2U);\n\n    /* configure Button B1 pin on GPIOC as input, no pull-up, pull-down */\n    GPIOC->MODER &= ~(3U << 2U*B1_PIN);\n    GPIOC->PUPDR &= ~(3U << 2U*B1_PIN);\n}\n\n/*..........................................................................*/\nvoid BSP_d1on(void)  { GPIOA->BSRR = (1U << TST1_PIN);         }\nvoid BSP_d1off(void) { GPIOA->BSRR = (1U << (TST1_PIN + 16U)); }\n/*..........................................................................*/\nvoid BSP_d2on(void)  { GPIOA->BSRR = (1U << TST2_PIN);         }\nvoid BSP_d2off(void) { GPIOA->BSRR = (1U << (TST2_PIN + 16U)); }\n/*..........................................................................*/\nvoid BSP_d3on(void)  { GPIOA->BSRR = (1U << TST3_PIN);         }\nvoid BSP_d3off(void) { GPIOA->BSRR = (1U << (TST3_PIN + 16U)); }\n/*..........................................................................*/\nvoid BSP_d4on(void)  { GPIOA->BSRR = (1U << TST4_PIN);         }\nvoid BSP_d4off(void) { GPIOA->BSRR = (1U << (TST4_PIN + 16U)); }\n/*..........................................................................*/\nvoid BSP_d5on(void)  { GPIOA->BSRR = (1U << TST5_PIN);         }\nvoid BSP_d5off(void) { GPIOA->BSRR = (1U << (TST5_PIN + 16U)); }\n/*..........................................................................*/\nvoid BSP_d6on(void)  { GPIOA->BSRR = (1U << TST6_PIN);         } /* LED2 */\nvoid BSP_d6off(void) { GPIOA->BSRR = (1U << (TST6_PIN + 16U)); }\n\n/*..........................................................................*/\nSST_Evt const *BSP_getWorkEvtBlinky1(uint8_t num) {\n    /* immutable work events for Blinky1 */\n    static BlinkyWorkEvt const workBlinky1[] = {\n        {\n            .super.sig = BLINKY_WORK_SIG,\n            .toggles = 40U,\n            .ticks = 5U,\n        },\n        {\n            .super.sig = BLINKY_WORK_SIG,\n            .toggles = 30U,\n            .ticks = 7U,\n        }\n    };\n    DBC_REQUIRE(500, num < ARRAY_NELEM(workBlinky1)); /* must be in range */\n    return &workBlinky1[num].super;\n}\n/*..........................................................................*/\nSST_Evt const *BSP_getWorkEvtBlinky3(uint8_t num) {\n    /* immutable work events for Blinky3 */\n    static BlinkyWorkEvt const workBlinky3[] = {\n        {\n            .super.sig = BLINKY_WORK_SIG,\n            .toggles = 20U,\n            .ticks = 5U,\n        },\n        {\n            .super.sig = BLINKY_WORK_SIG,\n            .toggles = 10U,\n            .ticks = 3U,\n        }\n    };\n    DBC_REQUIRE(600, num < ARRAY_NELEM(workBlinky3)); /* must be in range */\n    return &workBlinky3[num].super;\n}\n\n/* SST callbacks ===========================================================*/\nvoid SST_onStart(void) {\n    SystemCoreClockUpdate();\n\n    /* set up the SysTick timer to fire at BSP_TICKS_PER_SEC rate */\n    SysTick_Config((SystemCoreClock / BSP_TICKS_PER_SEC) + 1U);\n\n    /* set priorities of ISRs used in the system */\n    NVIC_SetPriority(SysTick_IRQn, 0U);\n    /* ... */\n}\n/*..........................................................................*/\nvoid SST_onIdleCond(void) { /* NOTE: called with interrupts DISABLED */\n    BSP_d6on();  /* turn LED2 on */\n#ifdef NDEBUG\n    /* Put the CPU and peripherals to the low-power mode.\n    * you might need to customize the clock management for your application,\n    * see the datasheet for your particular Cortex-M MCU.\n    */\n    BSP_d6off(); /* turn LED2 off */\n    __WFI(); /* Wait-For-Interrupt */\n    BSP_d6on();  /* turn LED2 on */\n#endif\n    BSP_d6off(); /* turn LED2 off */\n    SST_PORT_INT_ENABLE(); /* NOTE: enable interrupts for SS0 */\n}\n\n"
  },
  {
    "path": "sst0_c/examples/blinky_button/button2a.c",
    "content": "/*============================================================================\n* Super-Simple Tasker (SST/C) Example\n*\n* Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n*\n* SPDX-License-Identifier: MIT\n*\n* Permission is hereby granted, free of charge, to any person obtaining a\n* copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included in\n* all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n============================================================================*/\n#include \"sst.h\"           /* SST framework */\n#include \"bsp.h\"           /* Board Support Package interface */\n#include \"blinky_button.h\" /* application shared interface */\n\nDBC_MODULE_NAME(\"button2a\") /* for DBC assertions in this module */\n\n/*..........................................................................*/\ntypedef struct {    /* Button2a task */\n    SST_Task super; /* inherit SST_Task */\n    /* add internal variables for this AO... */\n} Button2a;\n\nstatic void Button2a_ctor(Button2a * const me);\nstatic void Button2a_init(Button2a * const me, SST_Evt const * const ie);\nstatic void Button2a_dispatch(Button2a * const me, SST_Evt const * const e);\n\n/*..........................................................................*/\nstatic Button2a Button2a_inst; /* the Button2a instance */\nSST_Task * const AO_Button2a = &Button2a_inst.super; /* opaque AO pointer */\n\nvoid Button2a_instantiate(void) {\n    Button2a_ctor(&Button2a_inst);\n}\n\n/*..........................................................................*/\nstatic void Button2a_ctor(Button2a * const me) {\n    SST_Task_ctor(\n       &me->super,\n       (SST_Handler)&Button2a_init,\n       (SST_Handler)&Button2a_dispatch);\n}\n/*..........................................................................*/\nstatic void Button2a_init(Button2a * const me, SST_Evt const * const ie) {\n    (void)me;\n    (void)ie;\n}\n/*..........................................................................*/\nstatic void Button2a_dispatch(Button2a * const me, SST_Evt const * const e) {\n    (void)me;\n    switch (e->sig) {\n        case BUTTON_PRESSED_SIG: {\n            BSP_d4on();\n            /* Button2a --> Blinky1 */\n            SST_Task_post(AO_Blinky1, BSP_getWorkEvtBlinky1(1U));\n            BSP_d4off();\n\n            for (uint16_t i = SST_EVT_DOWNCAST(ButtonWorkEvt, e)->toggles;\n                 i > 0U; --i)\n            {\n                BSP_d4on();\n                BSP_d4off();\n            }\n            break;\n        }\n        case FORWARD_PRESSED_SIG: {\n            BSP_d4on();\n            /* immutable event can be forwarded to another Task */\n            SST_Task_post(AO_Button2b, e); /* Button2a --> Button2b */\n            BSP_d4off();\n            break;\n        }\n        case BUTTON_RELEASED_SIG: {\n            BSP_d4on();\n            /* Button2a --> Blinky1 */\n            SST_Task_post(AO_Blinky1, BSP_getWorkEvtBlinky1(0U));\n            BSP_d4off();\n\n            for (uint16_t i = SST_EVT_DOWNCAST(ButtonWorkEvt, e)->toggles;\n                 i > 0U; --i)\n            {\n                BSP_d4on();\n                BSP_d4off();\n            }\n            break;\n        }\n        case FORWARD_RELEASED_SIG: {\n            BSP_d4on();\n            /* immutable event can be forwarded to another Task */\n            SST_Task_post(AO_Button2b, e); /* Button2a --> Button2b */\n            BSP_d4off();\n            break;\n        }\n        default: {\n            DBC_ERROR(500); /* unexpected event */\n            break;\n        }\n    }\n}\n"
  },
  {
    "path": "sst0_c/examples/blinky_button/button2b.c",
    "content": "/*============================================================================\n* Super-Simple Tasker (SST/C) Example\n*\n* Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n*\n* SPDX-License-Identifier: MIT\n*\n* Permission is hereby granted, free of charge, to any person obtaining a\n* copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included in\n* all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n============================================================================*/\n#include \"sst.h\"           /* SST framework */\n#include \"bsp.h\"           /* Board Support Package interface */\n#include \"blinky_button.h\" /* application shared interface */\n\nDBC_MODULE_NAME(\"button2b\") /* for DBC assertions in this module */\n\n/*..........................................................................*/\ntypedef struct {    /* Button2b task */\n    SST_Task super; /* inherit SST_Task */\n    /* add internal variables for this AO... */\n} Button2b;\n\nstatic void Button2b_ctor(Button2b * const me);\nstatic void Button2b_init(Button2b * const me, SST_Evt const * const e);\nstatic void Button2b_dispatch(Button2b * const me, SST_Evt const * const e);\n\n/*..........................................................................*/\nstatic Button2b Button2b_inst; /* the Button2b instance */\nSST_Task * const AO_Button2b = &Button2b_inst.super; /* opaque AO pointer */\n\nvoid Button2b_instantiate(void) {\n    Button2b_ctor(&Button2b_inst);\n}\n\n/*..........................................................................*/\nstatic void Button2b_ctor(Button2b * const me) {\n    SST_Task_ctor(\n       &me->super,\n       (SST_Handler)&Button2b_init,\n       (SST_Handler)&Button2b_dispatch);\n}\n/*..........................................................................*/\nstatic void Button2b_init(Button2b * const me, SST_Evt const * const ie) {\n    (void)me;\n    (void)ie;\n}\n/*..........................................................................*/\nstatic void Button2b_dispatch(Button2b * const me, SST_Evt const * const e) {\n    switch (e->sig) {\n        case FORWARD_PRESSED_SIG: {\n            BSP_d3on();\n            /* Button2b --> Blinky3 */\n            SST_Task_post(AO_Blinky3, BSP_getWorkEvtBlinky3(1U));\n            BSP_d3off();\n\n            for (uint16_t i = SST_EVT_DOWNCAST(ButtonWorkEvt, e)->toggles;\n                 i > 0U; --i)\n            {\n                BSP_d3on();\n                BSP_d3off();\n            }\n            break;\n        }\n        case FORWARD_RELEASED_SIG: {\n            BSP_d3on();\n            /* Button2b --> Blinky3 */\n            SST_Task_post(AO_Blinky3, BSP_getWorkEvtBlinky3(0U));\n            BSP_d3off();\n\n            for (uint16_t i = SST_EVT_DOWNCAST(ButtonWorkEvt, e)->toggles;\n                 i > 0U; --i)\n            {\n                BSP_d3on();\n                BSP_d3off();\n            }\n            break;\n        }\n        default: {\n            DBC_ERROR(500); /* unexpected event */\n            break;\n        }\n    }\n}\n"
  },
  {
    "path": "sst0_c/examples/blinky_button/gnu/ek-tm4c123gxl.mak",
    "content": "##############################################################################\n# Makefile for Super-Simple Tasker (SST/C) on TM4C123GXL, GNU-ARM\n# Last Updated for Version: 2.0.0\n# Date of the Last Update:  2023-01-25\n#\n#                    Q u a n t u m  L e a P s\n#                    ------------------------\n#                    Modern Embedded Software\n#\n# Copyright (C) 2005 Quantum Leaps, LLC. All rights reserved.\n#\n# SPDX-License-Identifier: MIT\n#\n# Permission is hereby granted, free of charge, to any person obtaining a copy\n# of this software and associated documentation files (the \"Software\"), to\n# deal in the Software without restriction, including without limitation the\n# rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n# sell copies of the Software, and to permit persons to whom the Software is\n# furnished to do so, subject to the following conditions:\n#\n# The above copyright notice and this permission notice shall be included in\n# all copies or substantial portions of the Software.\n#\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS\n# IN THE SOFTWARE.\n##############################################################################\n# examples of invoking this Makefile:\n# make -f ek-tm4c123gxl.mak\n# make -f ek-tm4c123gxl.mak clean\n#\n# NOTE:\n# To use this Makefile on Windows, you will need the GNU make utility, which\n# is included in the QTools collection for Windows, see:\n#    https://github.com/QuantumLeaps/qtools\n#\n\n#-----------------------------------------------------------------------------\n# project and target names\n#\nPROJECT := blinky_button\nTARGET  := ek-tm4c123gxl\n\n#-----------------------------------------------------------------------------\n# project directories\n#\nSST_DIR      := ../../..\nSST_PORT_DIR := $(SST_DIR)/ports/arm-cm\nCMSIS_DIR    := ../../../../3rd_party/CMSIS\nTARGET_DIR   := ../../../../3rd_party/$(TARGET)\n\n# list of all source directories used by this project\nVPATH = .. \\\n\t$(SST_DIR)/src \\\n\t$(SST_PORT_DIR) \\\n\t$(TARGET_DIR) \\\n\t$(TARGET_DIR)/gnu \\\n\n# list of all include directories needed by this project\nINCLUDES  = -I. \\\n\t-I$(SST_DIR)/../include \\\n\t-I$(SST_PORT_DIR) \\\n\t-I$(CMSIS_DIR)/Include \\\n\t-I$(TARGET_DIR)\n\n#-----------------------------------------------------------------------------\n# project files\n#\n\n# assembler source files\nASM_SRCS :=\n\n# C source files\nC_SRCS := \\\n\tsst0.c \\\n\tmain.c \\\n\tblinky1.c \\\n\tblinky3.c \\\n\tbutton2a.c \\\n\tbutton2b.c \\\n\tbsp_ek-tm4c123gxl.c \\\n\tsystem_TM4C123GH6PM.c \\\n\tstartup_TM4C123GH6PM.c\n\n# C++ source files\nCPP_SRCS :=\n\nLD_SCRIPT  := $(TARGET_DIR)/gnu/$(TARGET).ld\n\nOUTPUT    := $(PROJECT)\n\nLIB_DIRS  :=\nLIBS      :=\n\n# defines\nDEFINES   := -DTARGET_IS_TM4C123_RB1\n\n# ARM CPU, ARCH, FPU, and Float-ABI types...\n# ARM_CPU:   [cortex-m0 | cortex-m0plus | cortex-m1 | cortex-m3 | cortex-m4]\n# ARM_FPU:   [ | vfp]\n# FLOAT_ABI: [ | soft | softfp | hard]\n#\nARM_CPU   := -mcpu=cortex-m4\nARM_FPU   := -mfpu=vfp\nFLOAT_ABI := -mfloat-abi=softfp\n\n#-----------------------------------------------------------------------------\n# GNU-ARM toolset (NOTE: You need to adjust to your machine)\n# see https://developer.arm.com/open-source/gnu-toolchain/gnu-rm/downloads\n#\nifeq ($(GNU_ARM),)\nGNU_ARM := $(QTOOLS)/gnu_arm-none-eabi\nendif\n\n# make sure that the GNU-ARM toolset exists...\nifeq (\"$(wildcard $(GNU_ARM))\",\"\")\n$(error GNU_ARM toolset not found. Please adjust the Makefile)\nendif\n\nCC    := $(GNU_ARM)/bin/arm-none-eabi-gcc\nCPP   := $(GNU_ARM)/bin/arm-none-eabi-g++\nAS    := $(GNU_ARM)/bin/arm-none-eabi-as\nLINK  := $(GNU_ARM)/bin/arm-none-eabi-gcc\nBIN   := $(GNU_ARM)/bin/arm-none-eabi-objcopy\n\n##############################################################################\n# Typically you should not need to change anything below this line\n\n# basic utilities (included in QTools for Windows), see:\n#     https://www.state-machine.com/qtools\n\nMKDIR := mkdir\nRM    := rm\n\n#-----------------------------------------------------------------------------\n# build options\n#\n\n# combine all the soruces...\nC_SRCS += $(QP_SRCS)\nASM_SRCS += $(QP_ASMS)\n\nBIN_DIR := build_$(TARGET)\n\nASFLAGS = -g $(ARM_CPU) $(ARM_FPU) $(ASM_CPU) $(ASM_FPU)\n\nCFLAGS = -c -g $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -std=c99 -mthumb -Wall \\\n\t-ffunction-sections -fdata-sections \\\n\t-O $(INCLUDES) $(DEFINES)\n\nCPPFLAGS = -c -g $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -std=c++11 -mthumb -Wall \\\n\t-ffunction-sections -fdata-sections -fno-rtti -fno-exceptions \\\n\t-O $(INCLUDES) $(DEFINES)\n\nLINKFLAGS = -T$(LD_SCRIPT) $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -mthumb \\\n\t-specs=nosys.specs -specs=nano.specs \\\n\t-Wl,-Map,$(BIN_DIR)/$(OUTPUT).map,--cref,--gc-sections $(LIB_DIRS)\n\nASM_OBJS     := $(patsubst %.s,%.o,  $(notdir $(ASM_SRCS)))\nC_OBJS       := $(patsubst %.c,%.o,  $(notdir $(C_SRCS)))\nCPP_OBJS     := $(patsubst %.cpp,%.o,$(notdir $(CPP_SRCS)))\n\nTARGET_BIN   := $(BIN_DIR)/$(OUTPUT).bin\nTARGET_ELF   := $(BIN_DIR)/$(OUTPUT).elf\nASM_OBJS_EXT := $(addprefix $(BIN_DIR)/, $(ASM_OBJS))\nC_OBJS_EXT   := $(addprefix $(BIN_DIR)/, $(C_OBJS))\nC_DEPS_EXT   := $(patsubst %.o, %.d, $(C_OBJS_EXT))\nCPP_OBJS_EXT := $(addprefix $(BIN_DIR)/, $(CPP_OBJS))\nCPP_DEPS_EXT := $(patsubst %.o, %.d, $(CPP_OBJS_EXT))\n\n# create $(BIN_DIR) if it does not exist\nifeq (\"$(wildcard $(BIN_DIR))\",\"\")\n$(shell $(MKDIR) $(BIN_DIR))\nendif\n\n#-----------------------------------------------------------------------------\n# rules\n#\n\n.PHONY : run norun flash\n\nifeq ($(MAKECMDGOALS),norun)\nall : $(TARGET_BIN)\nnorun : all\nelse\nall : $(TARGET_BIN) run\nendif\n\n$(TARGET_BIN): $(TARGET_ELF)\n\t$(BIN) -O binary $< $@\n\n$(TARGET_ELF) : $(ASM_OBJS_EXT) $(C_OBJS_EXT) $(CPP_OBJS_EXT)\n\t$(LINK) $(LINKFLAGS) -o $@ $^ $(LIBS)\n\n$(BIN_DIR)/%.d : %.c\n\t$(CC) -MM -MT $(@:.d=.o) $(CFLAGS) $< > $@\n\n$(BIN_DIR)/%.d : %.cpp\n\t$(CPP) -MM -MT $(@:.d=.o) $(CPPFLAGS) $< > $@\n\n$(BIN_DIR)/%.o : %.s\n\t$(AS) $(ASFLAGS) $< -o $@\n\n$(BIN_DIR)/%.o : %.c\n\t$(CC) $(CFLAGS) $< -o $@\n\n$(BIN_DIR)/%.o : %.cpp\n\t$(CPP) $(CPPFLAGS) $< -o $@\n\n.PHONY : clean show\n\n# include dependency files only if our goal depends on their existence\nifneq ($(MAKECMDGOALS),clean)\n  ifneq ($(MAKECMDGOALS),show)\n-include $(C_DEPS_EXT) $(CPP_DEPS_EXT)\n  endif\nendif\n\n\nclean :\n\t-$(RM) $(BIN_DIR)/*.o \\\n\t$(BIN_DIR)/*.d \\\n\t$(BIN_DIR)/*.bin \\\n\t$(BIN_DIR)/*.elf \\\n\t$(BIN_DIR)/*.map\n\t\nshow:\n\t@echo PROJECT = $(PROJECT)\n\t@echo CONF = $(CONF)\n\t@echo DEFINES = $(DEFINES)\n\t@echo ASM_FPU = $(ASM_FPU)\n\t@echo ASM_SRCS = $(ASM_SRCS)\n\t@echo C_SRCS = $(C_SRCS)\n\t@echo CPP_SRCS = $(CPP_SRCS)\n\t@echo ASM_OBJS_EXT = $(ASM_OBJS_EXT)\n\t@echo C_OBJS_EXT = $(C_OBJS_EXT)\n\t@echo C_DEPS_EXT = $(C_DEPS_EXT)\n\t@echo CPP_DEPS_EXT = $(CPP_DEPS_EXT)\n\t@echo TARGET_ELF = $(TARGET_ELF)\n"
  },
  {
    "path": "sst0_c/examples/blinky_button/gnu/flash_ek-tm4c123gxl.bat",
    "content": "::============================================================================\n:: Batch file to program the flash of EK-TM4C123GXL\n::\n:: NOTE: requires the LMFlash programmer (included in QTools for Windows)\n::\n@echo off\nsetlocal\n\n@echo Load a given binary file to the flash of EK-TM4C123GXL\n@echo usage:   flash binary-file\n@echo example: flash dbg\\blinky-qk.bin\n\n::----------------------------------------------------------------------------\n:: NOTE: The following symbol LMFLASH assumes that LMFlash.exe can\n:: be found on the PATH. You might need to adjust this symbol to the\n:: location of the LMFlash utility on your machine\n::\nset LMFLASH=LMFlash.exe\n\nif [\"%~1\"]==[\"\"] (\n    @echo The binary file missing\n    @goto end\n)\nif not exist %~s1 (\n    @echo The binary file '%1' does not exist\n    @goto end\n)\n\n%LMFLASH% -q ek-tm4c123gxl -e -v -r %1\n\n:end\n\nendlocal"
  },
  {
    "path": "sst0_c/examples/blinky_button/gnu/nucleo-c031c6.mak",
    "content": "##############################################################################\n# Makefile for Super-Simple Tasker (SST0/C) on NUCLEO-C031C6, GNU-ARM\n# Last Updated for Version: 2.0.0\n# Date of the Last Update:  2023-02-02\n#\n#                    Q u a n t u m  L e a P s\n#                    ------------------------\n#                    Modern Embedded Software\n#\n# Copyright (C) 2005 Quantum Leaps, LLC. All rights reserved.\n#\n# SPDX-License-Identifier: MIT\n#\n# Permission is hereby granted, free of charge, to any person obtaining a copy\n# of this software and associated documentation files (the \"Software\"), to\n# deal in the Software without restriction, including without limitation the\n# rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n# sell copies of the Software, and to permit persons to whom the Software is\n# furnished to do so, subject to the following conditions:\n#\n# The above copyright notice and this permission notice shall be included in\n# all copies or substantial portions of the Software.\n#\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS\n# IN THE SOFTWARE.\n##############################################################################\n# examples of invoking this Makefile:\n# make -f nucleo-c031c6.mak\n# make -f nucleo-c031c6.mak clean\n#\n# NOTE:\n# To use this Makefile on Windows, you will need the GNU make utility, which\n# is included in the QTools collection for Windows, see:\n#    https://github.com/QuantumLeaps/qtools\n#\n\n#-----------------------------------------------------------------------------\n# project and target names\n#\nPROJECT := blinky_button\nTARGET  := nucleo-c031c6\n\n#-----------------------------------------------------------------------------\n# project directories\n#\nSST_DIR      := ../../..\nSST_PORT_DIR := $(SST_DIR)/ports/arm-cm\nCMSIS_DIR    := ../../../../3rd_party/CMSIS\nTARGET_DIR   := ../../../../3rd_party/$(TARGET)\n\n# list of all source directories used by this project\nVPATH = .. \\\n\t$(SST_DIR)/src \\\n\t$(SST_PORT_DIR) \\\n\t$(TARGET_DIR) \\\n\t$(TARGET_DIR)/gnu \\\n\n# list of all include directories needed by this project\nINCLUDES  = -I. \\\n\t-I$(SST_DIR)/../include \\\n\t-I$(SST_PORT_DIR) \\\n\t-I$(CMSIS_DIR)/Include \\\n\t-I$(TARGET_DIR)\n\n#-----------------------------------------------------------------------------\n# project files\n#\n\n# assembler source files\nASM_SRCS :=\n\n# C source files\nC_SRCS := \\\n\tsst0.c \\\n\tmain.c \\\n\tblinky1.c \\\n\tblinky3.c \\\n\tbutton2a.c \\\n\tbutton2b.c \\\n\tbsp_nucleo-c031c6.c \\\n\tsystem_stm32c0xx.c \\\n\tstartup_stm32c031xx.c\n\n# C++ source files\nCPP_SRCS :=\n\nLD_SCRIPT  := $(TARGET_DIR)/gnu/$(TARGET).ld\n\nOUTPUT    := $(PROJECT)\n\nLIB_DIRS  :=\nLIBS      :=\n\n# defines\nDEFINES   := -DSTM32C031xx\n\n# ARM CPU, ARCH, FPU, and Float-ABI types...\n# ARM_CPU:   [cortex-m0 | cortex-m0plus | cortex-m1 | cortex-m3 | cortex-m4]\n# ARM_FPU:   [ | vfp]\n# FLOAT_ABI: [ | soft | softfp | hard]\n#\nARM_CPU   := -mcpu=cortex-m0plus\nARM_FPU   :=\nFLOAT_ABI :=\n\n#-----------------------------------------------------------------------------\n# GNU-ARM toolset (NOTE: You need to adjust to your machine)\n# see https://developer.arm.com/open-source/gnu-toolchain/gnu-rm/downloads\n#\nifeq ($(GNU_ARM),)\nGNU_ARM := $(QTOOLS)/gnu_arm-none-eabi\nendif\n\n# make sure that the GNU-ARM toolset exists...\nifeq (\"$(wildcard $(GNU_ARM))\",\"\")\n$(error GNU_ARM toolset not found. Please adjust the Makefile)\nendif\n\nCC    := $(GNU_ARM)/bin/arm-none-eabi-gcc\nCPP   := $(GNU_ARM)/bin/arm-none-eabi-g++\nAS    := $(GNU_ARM)/bin/arm-none-eabi-as\nLINK  := $(GNU_ARM)/bin/arm-none-eabi-gcc\nBIN   := $(GNU_ARM)/bin/arm-none-eabi-objcopy\n\n##############################################################################\n# Typically you should not need to change anything below this line\n\n# basic utilities (included in QTools for Windows), see:\n#     https://www.state-machine.com/qtools\n\nMKDIR := mkdir\nRM    := rm\n\n#-----------------------------------------------------------------------------\n# build options\n#\n\n# combine all the soruces...\nC_SRCS += $(QP_SRCS)\nASM_SRCS += $(QP_ASMS)\n\nBIN_DIR := build_$(TARGET)\n\nASFLAGS = -g $(ARM_CPU) $(ARM_FPU) $(ASM_CPU) $(ASM_FPU)\n\nCFLAGS = -c -g $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -std=c99 -mthumb -Wall \\\n\t-ffunction-sections -fdata-sections \\\n\t-O $(INCLUDES) $(DEFINES)\n\nCPPFLAGS = -c -g $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -std=c++11 -mthumb -Wall \\\n\t-ffunction-sections -fdata-sections -fno-rtti -fno-exceptions \\\n\t-O $(INCLUDES) $(DEFINES)\n\nLINKFLAGS = -T$(LD_SCRIPT) $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -mthumb \\\n\t-specs=nosys.specs -specs=nano.specs \\\n\t-Wl,-Map,$(BIN_DIR)/$(OUTPUT).map,--cref,--gc-sections $(LIB_DIRS)\n\nASM_OBJS     := $(patsubst %.s,%.o,  $(notdir $(ASM_SRCS)))\nC_OBJS       := $(patsubst %.c,%.o,  $(notdir $(C_SRCS)))\nCPP_OBJS     := $(patsubst %.cpp,%.o,$(notdir $(CPP_SRCS)))\n\nTARGET_BIN   := $(BIN_DIR)/$(OUTPUT).bin\nTARGET_ELF   := $(BIN_DIR)/$(OUTPUT).elf\nASM_OBJS_EXT := $(addprefix $(BIN_DIR)/, $(ASM_OBJS))\nC_OBJS_EXT   := $(addprefix $(BIN_DIR)/, $(C_OBJS))\nC_DEPS_EXT   := $(patsubst %.o, %.d, $(C_OBJS_EXT))\nCPP_OBJS_EXT := $(addprefix $(BIN_DIR)/, $(CPP_OBJS))\nCPP_DEPS_EXT := $(patsubst %.o, %.d, $(CPP_OBJS_EXT))\n\n# create $(BIN_DIR) if it does not exist\nifeq (\"$(wildcard $(BIN_DIR))\",\"\")\n$(shell $(MKDIR) $(BIN_DIR))\nendif\n\n#-----------------------------------------------------------------------------\n# rules\n#\n\n.PHONY : run norun flash\n\nifeq ($(MAKECMDGOALS),norun)\nall : $(TARGET_BIN)\nnorun : all\nelse\nall : $(TARGET_BIN) run\nendif\n\n$(TARGET_BIN): $(TARGET_ELF)\n\t$(BIN) -O binary $< $@\n\n$(TARGET_ELF) : $(ASM_OBJS_EXT) $(C_OBJS_EXT) $(CPP_OBJS_EXT)\n\t$(LINK) $(LINKFLAGS) -o $@ $^ $(LIBS)\n\n$(BIN_DIR)/%.d : %.c\n\t$(CC) -MM -MT $(@:.d=.o) $(CFLAGS) $< > $@\n\n$(BIN_DIR)/%.d : %.cpp\n\t$(CPP) -MM -MT $(@:.d=.o) $(CPPFLAGS) $< > $@\n\n$(BIN_DIR)/%.o : %.s\n\t$(AS) $(ASFLAGS) $< -o $@\n\n$(BIN_DIR)/%.o : %.c\n\t$(CC) $(CFLAGS) $< -o $@\n\n$(BIN_DIR)/%.o : %.cpp\n\t$(CPP) $(CPPFLAGS) $< -o $@\n\n.PHONY : clean show\n\n# include dependency files only if our goal depends on their existence\nifneq ($(MAKECMDGOALS),clean)\n  ifneq ($(MAKECMDGOALS),show)\n-include $(C_DEPS_EXT) $(CPP_DEPS_EXT)\n  endif\nendif\n\n\nclean :\n\t-$(RM) $(BIN_DIR)/*.o \\\n\t$(BIN_DIR)/*.d \\\n\t$(BIN_DIR)/*.bin \\\n\t$(BIN_DIR)/*.elf \\\n\t$(BIN_DIR)/*.map\n\t\nshow:\n\t@echo PROJECT = $(PROJECT)\n\t@echo CONF = $(CONF)\n\t@echo DEFINES = $(DEFINES)\n\t@echo ASM_FPU = $(ASM_FPU)\n\t@echo ASM_SRCS = $(ASM_SRCS)\n\t@echo C_SRCS = $(C_SRCS)\n\t@echo CPP_SRCS = $(CPP_SRCS)\n\t@echo ASM_OBJS_EXT = $(ASM_OBJS_EXT)\n\t@echo C_OBJS_EXT = $(C_OBJS_EXT)\n\t@echo C_DEPS_EXT = $(C_DEPS_EXT)\n\t@echo CPP_DEPS_EXT = $(CPP_DEPS_EXT)\n\t@echo TARGET_ELF = $(TARGET_ELF)\n"
  },
  {
    "path": "sst0_c/examples/blinky_button/gnu/nucleo-h743zi.mak",
    "content": "##############################################################################\n# Makefile for Super-Simple Tasker (SST0/C) on NUCLEO-H743ZI, GNU-ARM\n# Last Updated for Version: 2.0.0\n# Date of the Last Update:  2023-01-22\n#\n#                    Q u a n t u m  L e a P s\n#                    ------------------------\n#                    Modern Embedded Software\n#\n# Copyright (C) 2005 Quantum Leaps, LLC. All rights reserved.\n#\n# SPDX-License-Identifier: MIT\n#\n# Permission is hereby granted, free of charge, to any person obtaining a copy\n# of this software and associated documentation files (the \"Software\"), to\n# deal in the Software without restriction, including without limitation the\n# rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n# sell copies of the Software, and to permit persons to whom the Software is\n# furnished to do so, subject to the following conditions:\n#\n# The above copyright notice and this permission notice shall be included in\n# all copies or substantial portions of the Software.\n#\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS\n# IN THE SOFTWARE.\n##############################################################################\n# examples of invoking this Makefile:\n# make -f nucleo-h743zi.mak\n# make -f nucleo-h743zi.mak clean\n#\n# NOTE:\n# To use this Makefile on Windows, you will need the GNU make utility, which\n# is included in the QTools collection for Windows, see:\n#    https://github.com/QuantumLeaps/qtools\n#\n\n#-----------------------------------------------------------------------------\n# project and target names\n#\nPROJECT := blinky_button\nTARGET  := nucleo-h743zi\n\n#-----------------------------------------------------------------------------\n# project directories\n#\nSST_DIR      := ../../..\nSST_PORT_DIR := $(SST_DIR)/ports/arm-cm\nCMSIS_DIR    := ../../../../3rd_party/CMSIS\nTARGET_DIR   := ../../../../3rd_party/$(TARGET)\n\n# list of all source directories used by this project\nVPATH = .. \\\n\t$(SST_DIR)/src \\\n\t$(SST_PORT_DIR) \\\n\t$(TARGET_DIR) \\\n\t$(TARGET_DIR)/gnu \\\n\n# list of all include directories needed by this project\nINCLUDES  = -I. \\\n\t-I$(SST_DIR)/../include \\\n\t-I$(SST_PORT_DIR) \\\n\t-I$(CMSIS_DIR)/Include \\\n\t-I$(TARGET_DIR)\n\n#-----------------------------------------------------------------------------\n# project files\n#\n\n# assembler source files\nASM_SRCS :=\n\n# C source files\nC_SRCS := \\\n\tsst0.c \\\n\tmain.c \\\n\tblinky1.c \\\n\tblinky3.c \\\n\tbutton2a.c \\\n\tbutton2b.c \\\n\tbsp_nucleo-h743zi.c \\\n\tstartup_stm32h743xx.c \\\n\tsystem_stm32h7xx.c\n\n# C++ source files\nCPP_SRCS :=\n\nLD_SCRIPT  := $(TARGET_DIR)/gnu/$(TARGET).ld\n\nOUTPUT    := $(PROJECT)\n\nLIB_DIRS  :=\nLIBS      :=\n\n# defines\nDEFINES   := -DSTM32H743xx\n\n# ARM CPU, ARCH, FPU, and Float-ABI types...\n# ARM_CPU:   [cortex-m0 | cortex-m0plus | cortex-m1 | cortex-m3 | cortex-m4]\n# ARM_FPU:   [ | vfp]\n# FLOAT_ABI: [ | soft | softfp | hard]\n#\nARM_CPU   := -mcpu=cortex-m7\nARM_FPU   := -mfpu=fpv5-d16\nFLOAT_ABI := -mfloat-abi=softfp\n\n#-----------------------------------------------------------------------------\n# GNU-ARM toolset (NOTE: You need to adjust to your machine)\n# see https://developer.arm.com/open-source/gnu-toolchain/gnu-rm/downloads\n#\nifeq ($(GNU_ARM),)\nGNU_ARM := $(QTOOLS)/gnu_arm-none-eabi\nendif\n\n# make sure that the GNU-ARM toolset exists...\nifeq (\"$(wildcard $(GNU_ARM))\",\"\")\n$(error GNU_ARM toolset not found. Please adjust the Makefile)\nendif\n\nCC    := $(GNU_ARM)/bin/arm-none-eabi-gcc\nCPP   := $(GNU_ARM)/bin/arm-none-eabi-g++\nAS    := $(GNU_ARM)/bin/arm-none-eabi-as\nLINK  := $(GNU_ARM)/bin/arm-none-eabi-gcc\nBIN   := $(GNU_ARM)/bin/arm-none-eabi-objcopy\n\n##############################################################################\n# Typically you should not need to change anything below this line\n\n# basic utilities (included in QTools for Windows), see:\n#     https://www.state-machine.com/qtools\n\nMKDIR := mkdir\nRM    := rm\n\n#-----------------------------------------------------------------------------\n# build options\n#\n\n# combine all the soruces...\nC_SRCS += $(QP_SRCS)\nASM_SRCS += $(QP_ASMS)\n\nBIN_DIR := build_$(TARGET)\n\nASFLAGS = -g $(ARM_CPU) $(ARM_FPU) $(ASM_CPU) $(ASM_FPU)\n\nCFLAGS = -c -g $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -std=c99 -mthumb -Wall \\\n\t-ffunction-sections -fdata-sections \\\n\t-O $(INCLUDES) $(DEFINES)\n\nCPPFLAGS = -c -g $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -std=c++11 -mthumb -Wall \\\n\t-ffunction-sections -fdata-sections -fno-rtti -fno-exceptions \\\n\t-O $(INCLUDES) $(DEFINES)\n\nLINKFLAGS = -T$(LD_SCRIPT) $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -mthumb \\\n\t-specs=nosys.specs -specs=nano.specs \\\n\t-Wl,-Map,$(BIN_DIR)/$(OUTPUT).map,--cref,--gc-sections $(LIB_DIRS)\n\nASM_OBJS     := $(patsubst %.s,%.o,  $(notdir $(ASM_SRCS)))\nC_OBJS       := $(patsubst %.c,%.o,  $(notdir $(C_SRCS)))\nCPP_OBJS     := $(patsubst %.cpp,%.o,$(notdir $(CPP_SRCS)))\n\nTARGET_BIN   := $(BIN_DIR)/$(OUTPUT).bin\nTARGET_ELF   := $(BIN_DIR)/$(OUTPUT).elf\nASM_OBJS_EXT := $(addprefix $(BIN_DIR)/, $(ASM_OBJS))\nC_OBJS_EXT   := $(addprefix $(BIN_DIR)/, $(C_OBJS))\nC_DEPS_EXT   := $(patsubst %.o, %.d, $(C_OBJS_EXT))\nCPP_OBJS_EXT := $(addprefix $(BIN_DIR)/, $(CPP_OBJS))\nCPP_DEPS_EXT := $(patsubst %.o, %.d, $(CPP_OBJS_EXT))\n\n# create $(BIN_DIR) if it does not exist\nifeq (\"$(wildcard $(BIN_DIR))\",\"\")\n$(shell $(MKDIR) $(BIN_DIR))\nendif\n\n#-----------------------------------------------------------------------------\n# rules\n#\n\n.PHONY : run norun flash\n\nifeq ($(MAKECMDGOALS),norun)\nall : $(TARGET_BIN)\nnorun : all\nelse\nall : $(TARGET_BIN) run\nendif\n\n$(TARGET_BIN): $(TARGET_ELF)\n\t$(BIN) -O binary $< $@\n\n$(TARGET_ELF) : $(ASM_OBJS_EXT) $(C_OBJS_EXT) $(CPP_OBJS_EXT)\n\t$(LINK) $(LINKFLAGS) -o $@ $^ $(LIBS)\n\n$(BIN_DIR)/%.d : %.c\n\t$(CC) -MM -MT $(@:.d=.o) $(CFLAGS) $< > $@\n\n$(BIN_DIR)/%.d : %.cpp\n\t$(CPP) -MM -MT $(@:.d=.o) $(CPPFLAGS) $< > $@\n\n$(BIN_DIR)/%.o : %.s\n\t$(AS) $(ASFLAGS) $< -o $@\n\n$(BIN_DIR)/%.o : %.c\n\t$(CC) $(CFLAGS) $< -o $@\n\n$(BIN_DIR)/%.o : %.cpp\n\t$(CPP) $(CPPFLAGS) $< -o $@\n\n.PHONY : clean show\n\n# include dependency files only if our goal depends on their existence\nifneq ($(MAKECMDGOALS),clean)\n  ifneq ($(MAKECMDGOALS),show)\n-include $(C_DEPS_EXT) $(CPP_DEPS_EXT)\n  endif\nendif\n\n\nclean :\n\t-$(RM) $(BIN_DIR)/*.o \\\n\t$(BIN_DIR)/*.d \\\n\t$(BIN_DIR)/*.bin \\\n\t$(BIN_DIR)/*.elf \\\n\t$(BIN_DIR)/*.map\n\t\nshow:\n\t@echo PROJECT = $(PROJECT)\n\t@echo CONF = $(CONF)\n\t@echo DEFINES = $(DEFINES)\n\t@echo ASM_FPU = $(ASM_FPU)\n\t@echo ASM_SRCS = $(ASM_SRCS)\n\t@echo C_SRCS = $(C_SRCS)\n\t@echo CPP_SRCS = $(CPP_SRCS)\n\t@echo ASM_OBJS_EXT = $(ASM_OBJS_EXT)\n\t@echo C_OBJS_EXT = $(C_OBJS_EXT)\n\t@echo C_DEPS_EXT = $(C_DEPS_EXT)\n\t@echo CPP_DEPS_EXT = $(CPP_DEPS_EXT)\n\t@echo TARGET_ELF = $(TARGET_ELF)\n"
  },
  {
    "path": "sst0_c/examples/blinky_button/gnu/nucleo-l053r8.mak",
    "content": "##############################################################################\n# Makefile for Super-Simple Tasker (SST0/C) on NUCLEO-L053R8, GNU-ARM\n# Last Updated for Version: 2.0.0\n# Date of the Last Update:  2023-01-22\n#\n#                    Q u a n t u m  L e a P s\n#                    ------------------------\n#                    Modern Embedded Software\n#\n# Copyright (C) 2005 Quantum Leaps, LLC. All rights reserved.\n#\n# SPDX-License-Identifier: MIT\n#\n# Permission is hereby granted, free of charge, to any person obtaining a copy\n# of this software and associated documentation files (the \"Software\"), to\n# deal in the Software without restriction, including without limitation the\n# rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n# sell copies of the Software, and to permit persons to whom the Software is\n# furnished to do so, subject to the following conditions:\n#\n# The above copyright notice and this permission notice shall be included in\n# all copies or substantial portions of the Software.\n#\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS\n# IN THE SOFTWARE.\n##############################################################################\n# examples of invoking this Makefile:\n# make -f nucleo-l053r8.mak\n# make -f nucleo-l053r8.mak clean\n#\n# NOTE:\n# To use this Makefile on Windows, you will need the GNU make utility, which\n# is included in the QTools collection for Windows, see:\n#    https://github.com/QuantumLeaps/qtools\n#\n\n#-----------------------------------------------------------------------------\n# project and target names\n#\nPROJECT := blinky_button\nTARGET  := nucleo-l053r8\n\n#-----------------------------------------------------------------------------\n# project directories\n#\nSST_DIR      := ../../..\nSST_PORT_DIR := $(SST_DIR)/ports/arm-cm\nCMSIS_DIR    := ../../../../3rd_party/CMSIS\nTARGET_DIR   := ../../../../3rd_party/$(TARGET)\n\n# list of all source directories used by this project\nVPATH = .. \\\n\t$(SST_DIR)/src \\\n\t$(SST_PORT_DIR) \\\n\t$(TARGET_DIR) \\\n\t$(TARGET_DIR)/gnu \\\n\n# list of all include directories needed by this project\nINCLUDES  = -I. \\\n\t-I$(SST_DIR)/../include \\\n\t-I$(SST_PORT_DIR) \\\n\t-I$(CMSIS_DIR)/Include \\\n\t-I$(TARGET_DIR)\n\n#-----------------------------------------------------------------------------\n# project files\n#\n\n# assembler source files\nASM_SRCS :=\n\n# C source files\nC_SRCS := \\\n\tsst0.c \\\n\tmain.c \\\n\tblinky1.c \\\n\tblinky3.c \\\n\tbutton2a.c \\\n\tbutton2b.c \\\n\tbsp_nucleo-l053r8.c \\\n\tsystem_stm32l0xx.c \\\n\tstartup_stm32l053xx.c\n\n# C++ source files\nCPP_SRCS :=\n\nLD_SCRIPT  := $(TARGET_DIR)/gnu/$(TARGET).ld\n\nOUTPUT    := $(PROJECT)\n\nLIB_DIRS  :=\nLIBS      :=\n\n# defines\nDEFINES   :=\n\n# ARM CPU, ARCH, FPU, and Float-ABI types...\n# ARM_CPU:   [cortex-m0 | cortex-m0plus | cortex-m1 | cortex-m3 | cortex-m4]\n# ARM_FPU:   [ | vfp]\n# FLOAT_ABI: [ | soft | softfp | hard]\n#\nARM_CPU   := -mcpu=cortex-m0plus\nARM_FPU   :=\nFLOAT_ABI :=\n\n#-----------------------------------------------------------------------------\n# GNU-ARM toolset (NOTE: You need to adjust to your machine)\n# see https://developer.arm.com/open-source/gnu-toolchain/gnu-rm/downloads\n#\nifeq ($(GNU_ARM),)\nGNU_ARM := $(QTOOLS)/gnu_arm-none-eabi\nendif\n\n# make sure that the GNU-ARM toolset exists...\nifeq (\"$(wildcard $(GNU_ARM))\",\"\")\n$(error GNU_ARM toolset not found. Please adjust the Makefile)\nendif\n\nCC    := $(GNU_ARM)/bin/arm-none-eabi-gcc\nCPP   := $(GNU_ARM)/bin/arm-none-eabi-g++\nAS    := $(GNU_ARM)/bin/arm-none-eabi-as\nLINK  := $(GNU_ARM)/bin/arm-none-eabi-gcc\nBIN   := $(GNU_ARM)/bin/arm-none-eabi-objcopy\n\n##############################################################################\n# Typically you should not need to change anything below this line\n\n# basic utilities (included in QTools for Windows), see:\n#     https://www.state-machine.com/qtools\n\nMKDIR := mkdir\nRM    := rm\n\n#-----------------------------------------------------------------------------\n# build options\n#\n\n# combine all the soruces...\nC_SRCS += $(QP_SRCS)\nASM_SRCS += $(QP_ASMS)\n\nBIN_DIR := build_$(TARGET)\n\nASFLAGS = -g $(ARM_CPU) $(ARM_FPU) $(ASM_CPU) $(ASM_FPU)\n\nCFLAGS = -c -g $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -std=c99 -mthumb -Wall \\\n\t-ffunction-sections -fdata-sections \\\n\t-O $(INCLUDES) $(DEFINES)\n\nCPPFLAGS = -c -g $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -std=c++11 -mthumb -Wall \\\n\t-ffunction-sections -fdata-sections -fno-rtti -fno-exceptions \\\n\t-O $(INCLUDES) $(DEFINES)\n\nLINKFLAGS = -T$(LD_SCRIPT) $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -mthumb \\\n\t-specs=nosys.specs -specs=nano.specs \\\n\t-Wl,-Map,$(BIN_DIR)/$(OUTPUT).map,--cref,--gc-sections $(LIB_DIRS)\n\nASM_OBJS     := $(patsubst %.s,%.o,  $(notdir $(ASM_SRCS)))\nC_OBJS       := $(patsubst %.c,%.o,  $(notdir $(C_SRCS)))\nCPP_OBJS     := $(patsubst %.cpp,%.o,$(notdir $(CPP_SRCS)))\n\nTARGET_BIN   := $(BIN_DIR)/$(OUTPUT).bin\nTARGET_ELF   := $(BIN_DIR)/$(OUTPUT).elf\nASM_OBJS_EXT := $(addprefix $(BIN_DIR)/, $(ASM_OBJS))\nC_OBJS_EXT   := $(addprefix $(BIN_DIR)/, $(C_OBJS))\nC_DEPS_EXT   := $(patsubst %.o, %.d, $(C_OBJS_EXT))\nCPP_OBJS_EXT := $(addprefix $(BIN_DIR)/, $(CPP_OBJS))\nCPP_DEPS_EXT := $(patsubst %.o, %.d, $(CPP_OBJS_EXT))\n\n# create $(BIN_DIR) if it does not exist\nifeq (\"$(wildcard $(BIN_DIR))\",\"\")\n$(shell $(MKDIR) $(BIN_DIR))\nendif\n\n#-----------------------------------------------------------------------------\n# rules\n#\n\n.PHONY : run norun flash\n\nifeq ($(MAKECMDGOALS),norun)\nall : $(TARGET_BIN)\nnorun : all\nelse\nall : $(TARGET_BIN) run\nendif\n\n$(TARGET_BIN): $(TARGET_ELF)\n\t$(BIN) -O binary $< $@\n\n$(TARGET_ELF) : $(ASM_OBJS_EXT) $(C_OBJS_EXT) $(CPP_OBJS_EXT)\n\t$(LINK) $(LINKFLAGS) -o $@ $^ $(LIBS)\n\n$(BIN_DIR)/%.d : %.c\n\t$(CC) -MM -MT $(@:.d=.o) $(CFLAGS) $< > $@\n\n$(BIN_DIR)/%.d : %.cpp\n\t$(CPP) -MM -MT $(@:.d=.o) $(CPPFLAGS) $< > $@\n\n$(BIN_DIR)/%.o : %.s\n\t$(AS) $(ASFLAGS) $< -o $@\n\n$(BIN_DIR)/%.o : %.c\n\t$(CC) $(CFLAGS) $< -o $@\n\n$(BIN_DIR)/%.o : %.cpp\n\t$(CPP) $(CPPFLAGS) $< -o $@\n\n.PHONY : clean show\n\n# include dependency files only if our goal depends on their existence\nifneq ($(MAKECMDGOALS),clean)\n  ifneq ($(MAKECMDGOALS),show)\n-include $(C_DEPS_EXT) $(CPP_DEPS_EXT)\n  endif\nendif\n\n\nclean :\n\t-$(RM) $(BIN_DIR)/*.o \\\n\t$(BIN_DIR)/*.d \\\n\t$(BIN_DIR)/*.bin \\\n\t$(BIN_DIR)/*.elf \\\n\t$(BIN_DIR)/*.map\n\t\nshow:\n\t@echo PROJECT = $(PROJECT)\n\t@echo CONF = $(CONF)\n\t@echo DEFINES = $(DEFINES)\n\t@echo ASM_FPU = $(ASM_FPU)\n\t@echo ASM_SRCS = $(ASM_SRCS)\n\t@echo C_SRCS = $(C_SRCS)\n\t@echo CPP_SRCS = $(CPP_SRCS)\n\t@echo ASM_OBJS_EXT = $(ASM_OBJS_EXT)\n\t@echo C_OBJS_EXT = $(C_OBJS_EXT)\n\t@echo C_DEPS_EXT = $(C_DEPS_EXT)\n\t@echo CPP_DEPS_EXT = $(CPP_DEPS_EXT)\n\t@echo TARGET_ELF = $(TARGET_ELF)\n"
  },
  {
    "path": "sst0_c/examples/blinky_button/iar/ek-tm4c123gxl.ewd",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<project>\n    <fileVersion>3</fileVersion>\n    <configuration>\n        <name>Debug</name>\n        <toolchain>\n            <name>ARM</name>\n        </toolchain>\n        <debug>1</debug>\n        <settings>\n            <name>C-SPY</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>32</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CInput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CEndian</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCVariant</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>MemOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MemFile</name>\n                    <state>$TOOLKIT_DIR$\\CONFIG\\debugger\\TexasInstruments\\TM4C123GH6PM.ddf</state>\n                </option>\n                <option>\n                    <name>RunToEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RunToName</name>\n                    <state>main</state>\n                </option>\n                <option>\n                    <name>CExtraOptionsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCDDFArgumentProducer</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCDownloadSuppressDownload</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCDownloadVerifyAll</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProductVersion</name>\n                    <state>9.10.2.39304</state>\n                </option>\n                <option>\n                    <name>OCDynDriverList</name>\n                    <state>LMIFTDI_ID</state>\n                </option>\n                <option>\n                    <name>OCLastSavedByProductVersion</name>\n                    <state>9.32.1.54977</state>\n                </option>\n                <option>\n                    <name>UseFlashLoader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CLowLevel</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCBE8Slave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacFile2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CDevice</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>FlashLoadersV3</name>\n                    <state>$TOOLKIT_DIR$/config/flashloader/TexasInstruments/FlashTC4_H6_o.board</state>\n                </option>\n                <option>\n                    <name>OCImagesSuppressCheck1</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesPath1</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCImagesSuppressCheck2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesPath2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCImagesSuppressCheck3</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesPath3</name>\n                    <state></state>\n  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</option>\n                <option>\n                    <name>OCDeviceConfigMacroFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCDebuggerExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCAllMTBOptions</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCMulticoreNrOfCores</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCMulticoreWorkspace</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCMulticoreSlaveProject</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCMulticoreSlaveConfiguration</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCDownloadExtraImage</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCAttachSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MassEraseBeforeFlashing</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCMulticoreNrOfCoresSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCMulticoreAMPConfigType</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCMulticoreSessionFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCTpiuBaseOption</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>ARMSIM_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>1</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCSimDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCSimEnablePSP</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCSimPspOverrideConfig</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCSimPspConfigFile</name>\n                    <state></state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CADI_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CCadiMemory</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>Fast Model</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCADILogFileCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCADILogFileEditB</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CMSISDAP_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>4</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCIarProbeScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CMSISDAPResetList</name>\n                    <version>1</version>\n                    <state>10</state>\n                </option>\n                <option>\n                    <name>CMSISDAPHWResetDuration</name>\n                    <state>300</state>\n                </option>\n                <option>\n                    <name>CMSISDAPHWResetDelay</name>\n                    <state>200</state>\n                </option>\n                <option>\n                    <name>CMSISDAPDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CMSISDAPInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CMSISDAPInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiTargetEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPJtagSpeedList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPRestoreBreakpointsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPUpdateBreakpointsEdit</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>RDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchUndef</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchData</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchPrefetch</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchMMERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchNOCPERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchCHKERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSTATERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchBUSERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchINTERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSFERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchHARDERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiCPUEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiCPUNumber</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeCfgOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeConfig</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CMSISDAPProbeConfigRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPSelectedCPUBehaviour</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ICpuName</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCJetEmuParams</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCCMSISDAPUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCCMSISDAPUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>GDBSERVER_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>TCPIP</name>\n                    <state>aaa.bbb.ccc.ddd</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCJTagBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJTagDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJTagUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>IJET_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>9</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCIarProbeScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetResetList</name>\n                    <version>1</version>\n                    <state>10</state>\n                </option>\n                <option>\n                    <name>IjetHWResetDuration</name>\n                    <state>300</state>\n                </option>\n                <option>\n                    <name>IjetHWResetDelay</name>\n                    <state>200</state>\n                </option>\n                <option>\n                    <name>IjetPowerFromProbe</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetPowerRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>IjetInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiTargetEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetScanChainNonARMDevices</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetIRLength</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetJtagSpeedList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetProtocolRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetSwoPin</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IjetSwoPrescalerList</name>\n                    <version>1</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetRestoreBreakpointsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetUpdateBreakpointsEdit</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>RDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchUndef</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchData</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchPrefetch</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchMMERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchNOCPERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchCHKERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSTATERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchBUSERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchINTERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSFERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchHARDERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeCfgOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeConfig</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IjetProbeConfigRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiCPUEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiCPUNumber</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetSelectedCPUBehaviour</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ICpuName</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCJetEmuParams</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetPreferETB</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetTraceSettingsList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetTraceSizeList</name>\n                    <version>0</version>\n                    <state>4</state>\n                </option>\n                <option>\n                    <name>FlashBoardPathSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCIjetUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCIjetUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL3S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL3S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL3S</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>JLINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>16</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>JLinkSpeed</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCJLinkDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCJLinkHWResetDelay</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>JLinkInitialSpeed</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCDoJlinkMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCScanChainNonARMDevices</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkIRLength</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkCommRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkTCPIP</name>\n                    <state>aaa.bbb.ccc.ddd</state>\n                </option>\n                <option>\n                    <name>CCJLinkSpeedRadioV2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCUSBDevice</name>\n                    <version>1</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCRDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchUndef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchData</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchPrefetch</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCJLinkInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJLinkResetList</name>\n                    <version>6</version>\n                    <state>5</state>\n                </option>\n                <option>\n                    <name>CCJLinkInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJLinkUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCTcpIpAlt</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkTcpIpSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSwoClockAuto</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSwoClockEdit</name>\n                    <state>2000</state>\n                </option>\n                <option>\n                    <name>OCJLinkTraceSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkTraceSourceDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkDeviceName</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>LMIFTDI_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>3</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>LmiftdiSpeed</name>\n                    <state>500</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCLmiFtdiInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCLmiFtdiInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCLmiftdiUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiResetList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>NULINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>PEMICRO_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>3</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJPEMicroShowSettings</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>STLINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>8</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSTLinkInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSTLinkInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkResetList</name>\n                    <version>3</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSwoClockAuto</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSwoClockEdit</name>\n                    <state>2000</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCSTLinkDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSTLinkUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkJtagSpeedList</name>\n                    <version>2</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkDAPNumber</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSTLinkDebugAccessPortRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUseServerSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkProbeList</name>\n                    <version>1</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkTargetVccEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSTLinkTargetVoltage</name>\n                    <state>###Uninitialized###</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>THIRDPARTY_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CThirdPartyDriverDll</name>\n                    <state>###Uninitialized###</state>\n                </option>\n                <option>\n                    <name>CThirdPartyLogFileCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CThirdPartyLogFileEditB</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>OCDriverInfo</name>\n                    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<name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>TIPackageOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TIPackage</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>BoardFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCXds100BreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100DoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100UpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchUndef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchData</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchPrefetch</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCXds100SwoClockAuto</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100SwoClockEdit</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCXds100HWResetDelay</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100ResetList</name>\n                    <version>1</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100UsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCXds100UsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100JtagSpeedList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100InterfaceRadio</name>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCXds100InterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100ProbeList</name>\n                    <version>0</version>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>CCXds100SWOPortRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100SWOPort</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCXDSTargetVccEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXDSTargetVoltage</name>\n                    <state>###Uninitialized###</state>\n                </option>\n                <option>\n                    <name>OCXDSDigitalStatesConfigFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCSelectedCoreName</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <debuggerPlugins>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\CMX\\CmxArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\CMX\\CmxTinyArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\embOS\\embOSPlugin.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\FreeRtos\\FreeRtosArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\Mbed\\MbedArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\Mbed\\MbedArmPlugin2.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\OpenRTOS\\OpenRTOSPlugin.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\SafeRTOS\\SafeRTOSPlugin.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\SMX\\smxAwareIarArm9.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\SMX\\smxAwareIarArm9BE.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\ThreadX\\ThreadXArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\uCOS-II\\uCOS-II-286-KA-CSpy.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\uCOS-II\\uCOS-II-KA-CSpy.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\uCOS-III\\uCOS-III-KA-CSpy.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$EW_DIR$\\common\\plugins\\Orti\\Orti.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$EW_DIR$\\common\\plugins\\TargetAccessServer\\TargetAccessServer.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$EW_DIR$\\common\\plugins\\uCProbe\\uCProbePlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n        </debuggerPlugins>\n    </configuration>\n</project>\n"
  },
  {
    "path": "sst0_c/examples/blinky_button/iar/ek-tm4c123gxl.ewp",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<project>\n    <fileVersion>3</fileVersion>\n    <configuration>\n        <name>Debug</name>\n        <toolchain>\n            <name>ARM</name>\n        </toolchain>\n        <debug>1</debug>\n        <settings>\n            <name>General</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <version>35</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>BrowseInfoPath</name>\n                    <state>build_ek-tm4c123gxl</state>\n                </option>\n                <option>\n                    <name>ExePath</name>\n                    <state>build_ek-tm4c123gxl</state>\n                </option>\n                <option>\n                    <name>ObjPath</name>\n                    <state>build_ek-tm4c123gxl</state>\n                </option>\n                <option>\n                    <name>ListPath</name>\n                    <state>build_ek-tm4c123gxl</state>\n                </option>\n                <option>\n                    <name>GEndianMode</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>Input description</name>\n                    <state>No specifier n, no float nor long long, no scan set, no assignment suppressing, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>Output description</name>\n                    <state>No specifier a, A, no specifier n, no float nor long long, no flags, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>GOutputBinary</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGCoreOrChip</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelect</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelectSlave</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RTDescription</name>\n                    <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\n                </option>\n                <option>\n                    <name>OGProductVersion</name>\n                    <state>5.11.0.50579</state>\n                </option>\n                <option>\n                    <name>OGLastSavedByProductVersion</name>\n                    <state>9.32.1.54977</state>\n                </option>\n                <option>\n                    <name>OGChipSelectEditMenu</name>\n                    <state>TM4C123GH6PM\tTexasInstruments TM4C123GH6PM</state>\n                </option>\n                <option>\n                    <name>GenLowLevelInterface</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GEndianModeBE</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OGBufferedTerminalOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GenStdoutInterface</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RTConfigPath2</name>\n                    <state>$TOOLKIT_DIR$\\inc\\c\\DLib_Config_Normal.h</state>\n                </option>\n                <option>\n                    <name>GBECoreSlave</name>\n                    <version>32</version>\n                    <state>39</state>\n                </option>\n                <option>\n                    <name>OGUseCmsis</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGUseCmsisDspLib</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibThreads</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CoreVariant</name>\n                    <version>32</version>\n                    <state>39</state>\n                </option>\n                <option>\n                    <name>GFPUDeviceSlave</name>\n                    <state>TM4C123GH6PM\tTexasInstruments TM4C123GH6PM</state>\n                </option>\n                <option>\n                    <name>FPU2</name>\n                    <version>0</version>\n                    <state>4</state>\n                </option>\n                <option>\n                    <name>NrRegs</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>NEON</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GFPUCoreSlave2</name>\n                    <version>32</version>\n                    <state>39</state>\n                </option>\n                <option>\n                    <name>OGCMSISPackSelectDevice</name>\n                </option>\n                <option>\n                    <name>OgLibHeap</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGLibAdditionalLocale</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGPrintfVariant</name>\n                    <version>0</version>\n                    <state>4</state>\n                </option>\n                <option>\n                    <name>OGPrintfMultibyteSupport</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGScanfVariant</name>\n                    <version>0</version>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>OGScanfMultibyteSupport</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GenLocaleTags</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>GenLocaleDisplayOnly</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DSPExtension</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>TrustZone</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TrustZoneModes</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGAarch64Abi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OG_32_64Device</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>BuildFilesPath</name>\n                    <state>Debug</state>\n                </option>\n                <option>\n                    <name>PointerAuthentication</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>FPU64</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>ICCARM</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>37</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CCOptimizationNoSizeConstraints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCDefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCPreprocFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPreprocComments</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPreprocLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCMnemonics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCMessages</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListAssFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListAssSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEnableRemarks</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCDiagSuppress</name>\n                    <state>Pa050</state>\n                </option>\n                <option>\n                    <name>CCDiagRemark</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagWarning</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagError</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCObjPrefix</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCAllowList</name>\n                    <version>1</version>\n                    <state>10010100</state>\n                </option>\n                <option>\n                    <name>CCDebugInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IEndianMode</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IExtraOptionsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCLangConformance</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSignedPlainChar</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCRequirePrototypes</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCDiagWarnAreErr</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCompilerRuntimeInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OutputFile</name>\n                    <state>$FILE_BNAME$.o</state>\n                </option>\n                <option>\n                    <name>CCLibConfigHeader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>PreInclude</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCIncludePath2</name>\n                    <state>$PROJ_DIR$\\..</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\include</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\ports\\arm-cm</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\CMSIS\\Include</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\ek-tm4c123gxl</state>\n                </option>\n                <option>\n                    <name>CCStdIncCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCodeSection</name>\n                    <state>.text</state>\n                </option>\n                <option>\n                    <name>IProcessorMode2</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCOptLevel</name>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCOptStrategy</name>\n                    <version>0</version>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCOptLevelSlave</name>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCPosIndRopi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPosIndRwpi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPosIndNoDynInit</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccLang</name>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>IccCDialect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccAllowVLA</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccStaticDestr</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccCppInlineSemantics</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccCmsis</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccFloatSemantics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCNoLiteralPool</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCOptStrategySlave</name>\n                    <version>0</version>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCGuardCalls</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCEncSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEncOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEncOutputBom</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCEncInput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccExceptions2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccRTTI2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OICompilerExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCStackProtection</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>AARM</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>11</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>AObjPrefix</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AEndian</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>ACaseSensitivity</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacroChars</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnWhat</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnOne</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AWarnRange1</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AWarnRange2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>ADebug</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AltRegisterNames</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ADefines</name>\n                    <state>ewarm</state>\n                </option>\n                <option>\n                    <name>AList</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AListHeader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AListing</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>Includes</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacDefs</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacExps</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacExec</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OnlyAssed</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MultiLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PageLengthCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PageLength</name>\n                    <state>80</state>\n                </option>\n                <option>\n                    <name>TabSpacing</name>\n                    <state>8</state>\n                </option>\n                <option>\n                    <name>AXRef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefDefines</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefInternal</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefDual</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AOutputFile</name>\n                    <state>$FILE_BNAME$.o</state>\n                </option>\n                <option>\n                    <name>ALimitErrorsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ALimitErrorsEdit</name>\n                    <state>100</state>\n                </option>\n                <option>\n                    <name>AIgnoreStdInclude</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AUserIncludes</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AExtraOptionsCheckV2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AExtraOptionsV2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AsmNoLiteralPool</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PreInclude</name>\n                    <state></state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>OBJCOPY</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>1</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OOCOutputFormat</name>\n                    <version>3</version>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>OCOutputOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OOCOutputFile</name>\n                    <state>ek-tm4c123gxl.bin</state>\n                </option>\n                <option>\n                    <name>OOCCommandLineProducer</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OOCObjCopyEnable</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CUSTOM</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <extensions></extensions>\n                <cmdline></cmdline>\n                <hasPrio>1</hasPrio>\n                <buildSequence>inputOutputBased</buildSequence>\n            </data>\n        </settings>\n        <settings>\n            <name>BUILDACTION</name>\n            <archiveVersion>1</archiveVersion>\n            <data>\n                <prebuild></prebuild>\n                <postbuild></postbuild>\n            </data>\n        </settings>\n        <settings>\n            <name>ILINK</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>27</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>IlinkLibIOConfig</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkInputFileSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOutputFile</name>\n                    <state>blinky_button.out</state>\n                </option>\n                <option>\n                    <name>IlinkDebugInfoEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkKeepSymbols</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySymbol</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySegment</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryAlign</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkDefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkConfigDefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkMapFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLogFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogInitialization</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogModule</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogSection</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogVeneer</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFile</name>\n                    <state>$TOOLKIT_DIR$\\config\\linker\\TexasInstruments\\TM4C123GH6.icf</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFileSlave</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkEnableRemarks</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkSuppressDiags</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsRem</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsWarn</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsErr</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkWarningsAreErrors</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkUseExtraOptions</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkLowLevelInterfaceSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkAutoLibEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkAdditionalLibs</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkOverrideProgramEntryLabel</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkProgramEntryLabelSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkProgramEntryLabel</name>\n                    <state>__iar_program_start</state>\n                </option>\n                <option>\n                    <name>DoFill</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>FillerByte</name>\n                    <state>0xFF</state>\n                </option>\n                <option>\n                    <name>FillerStart</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>FillerEnd</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>CrcSize</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcAlign</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcPoly</name>\n                    <state>0x11021</state>\n                </option>\n                <option>\n                    <name>CrcCompl</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CrcBitOrder</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CrcInitialValue</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>DoCrc</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkBE8Slave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkBufferedTerminalOutput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkStdoutInterfaceSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcFullSize</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIElfToolPostProcess</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogAutoLibSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogRedirSymbols</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogUnusedFragments</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCrcReverseByteOrder</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCrcUseAsInput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptInline</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOptExceptionsAllow</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOptExceptionsForce</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCmsis</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptMergeDuplSections</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOptUseVfe</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptForceVfe</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkStackAnalysisEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkStackControlFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkStackCallGraphFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CrcAlgorithm</name>\n                    <version>1</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcUnitSize</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkThreadsSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLogCallGraph</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFile_AltDefault</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkEncInput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutputBom</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkHeapSelect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLocaleSelect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkTrustzoneImportLibraryOut</name>\n                    <state>iar_ek-tm4c123gxl_import_lib.o</state>\n                </option>\n                <option>\n                    <name>OILinkExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryFile2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySymbol2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySegment2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryAlign2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkLogCrtRoutineSelection</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogFragmentInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogInlining</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogMerging</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkDemangle</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkWrapperFileEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkWrapperFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkFpuProcessor</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>IARCHIVE</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>IarchiveInputs</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IarchiveOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IarchiveOutput</name>\n                    <state>###Unitialized###</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>Coder</name>\n            <archiveVersion>0</archiveVersion>\n            <data />\n        </settings>\n    </configuration>\n    <group>\n        <name>Application</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\blinky1.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\blinky3.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\blinky_button.h</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\bsp.h</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\bsp_ek-tm4c123gxl.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\button2a.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\button2b.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\main.c</name>\n        </file>\n    </group>\n    <group>\n        <name>ek-tm4c123gxl</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\ek-tm4c123gxl\\iar\\startup_TM4C123GH6PM.s</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\ek-tm4c123gxl\\system_TM4C123GH6PM.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\ek-tm4c123gxl\\TM4C123GH6PM.h</name>\n        </file>\n    </group>\n    <group>\n        <name>sst</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\src\\sst0.c</name>\n        </file>\n    </group>\n    <group>\n        <name>sst_port</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\ports\\arm-cm\\sst_port.h</name>\n        </file>\n    </group>\n</project>\n"
  },
  {
    "path": "sst0_c/examples/blinky_button/iar/ek-tm4c123gxl.eww",
    "content": "<?xml version=\"1.0\" encoding=\"iso-8859-1\"?>\n\n<workspace>\n  <project>\n    <path>$WS_DIR$\\ek-tm4c123gxl.ewp</path>\n  </project>\n  <batchBuild/>\n</workspace>\n\n\n"
  },
  {
    "path": "sst0_c/examples/blinky_button/iar/nucleo-c031c6.ewd",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<project>\n    <fileVersion>3</fileVersion>\n    <configuration>\n        <name>Debug</name>\n        <toolchain>\n            <name>ARM</name>\n        </toolchain>\n        <debug>1</debug>\n        <settings>\n            <name>C-SPY</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>32</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CInput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CEndian</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCVariant</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>MemOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MemFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>RunToEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RunToName</name>\n                    <state>main</state>\n                </option>\n                <option>\n                    <name>CExtraOptionsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCDDFArgumentProducer</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCDownloadSuppressDownload</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCDownloadVerifyAll</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProductVersion</name>\n                    <state>9.32.1.54977</state>\n                </option>\n                <option>\n                    <name>OCDynDriverList</name>\n                    <state>STLINK_ID</state>\n                </option>\n                <option>\n                    <name>OCLastSavedByProductVersion</name>\n                    <state>9.32.1.54977</state>\n                </option>\n                <option>\n                    <name>UseFlashLoader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CLowLevel</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCBE8Slave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacFile2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CDevice</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>FlashLoadersV3</name>\n                    <state>$TOOLKIT_DIR$\\config\\flashloader\\</state>\n                </option>\n                <option>\n                    <name>OCImagesSuppressCheck1</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesPath1</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCImagesSuppressCheck2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesPath2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCImagesSuppressCheck3</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesPath3</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OverrideDefFlashBoard</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesOffset1</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCImagesOffset2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCImagesOffset3</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCImagesUse1</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesUse2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesUse3</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCDeviceConfigMacroFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCDebuggerExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCAllMTBOptions</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCMulticoreNrOfCores</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCMulticoreWorkspace</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCMulticoreSlaveProject</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCMulticoreSlaveConfiguration</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCDownloadExtraImage</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCAttachSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MassEraseBeforeFlashing</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCMulticoreNrOfCoresSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCMulticoreAMPConfigType</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCMulticoreSessionFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCTpiuBaseOption</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>ARMSIM_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>1</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCSimDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCSimEnablePSP</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCSimPspOverrideConfig</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCSimPspConfigFile</name>\n                    <state></state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CADI_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CCadiMemory</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>Fast Model</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCADILogFileCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCADILogFileEditB</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CMSISDAP_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>4</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCIarProbeScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CMSISDAPResetList</name>\n                    <version>1</version>\n                    <state>10</state>\n                </option>\n                <option>\n                    <name>CMSISDAPHWResetDuration</name>\n                    <state>300</state>\n                </option>\n                <option>\n                    <name>CMSISDAPHWResetDelay</name>\n                    <state>200</state>\n                </option>\n                <option>\n                    <name>CMSISDAPDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CMSISDAPInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CMSISDAPInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiTargetEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPJtagSpeedList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPRestoreBreakpointsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPUpdateBreakpointsEdit</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>RDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchUndef</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchData</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchPrefetch</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchMMERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchNOCPERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchCHKERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSTATERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchBUSERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchINTERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSFERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchHARDERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiCPUEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiCPUNumber</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeCfgOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeConfig</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CMSISDAPProbeConfigRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPSelectedCPUBehaviour</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ICpuName</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCJetEmuParams</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCCMSISDAPUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCCMSISDAPUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>GDBSERVER_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>TCPIP</name>\n                    <state>aaa.bbb.ccc.ddd</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCJTagBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJTagDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJTagUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>IJET_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>9</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCIarProbeScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetResetList</name>\n                    <version>1</version>\n                    <state>10</state>\n                </option>\n                <option>\n                    <name>IjetHWResetDuration</name>\n                    <state>300</state>\n                </option>\n                <option>\n                    <name>IjetHWResetDelay</name>\n                    <state>200</state>\n                </option>\n                <option>\n                    <name>IjetPowerFromProbe</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetPowerRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>IjetInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiTargetEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetScanChainNonARMDevices</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetIRLength</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetJtagSpeedList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetProtocolRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetSwoPin</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IjetSwoPrescalerList</name>\n                    <version>1</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetRestoreBreakpointsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetUpdateBreakpointsEdit</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>RDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchUndef</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchData</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchPrefetch</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchMMERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchNOCPERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchCHKERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSTATERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchBUSERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchINTERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSFERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchHARDERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeCfgOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeConfig</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IjetProbeConfigRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiCPUEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiCPUNumber</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetSelectedCPUBehaviour</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ICpuName</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCJetEmuParams</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetPreferETB</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetTraceSettingsList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetTraceSizeList</name>\n                    <version>0</version>\n                    <state>4</state>\n                </option>\n                <option>\n                    <name>FlashBoardPathSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCIjetUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCIjetUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL3S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL3S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL3S</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>JLINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>16</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>JLinkSpeed</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCJLinkDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCJLinkHWResetDelay</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>JLinkInitialSpeed</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCDoJlinkMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCScanChainNonARMDevices</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkIRLength</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkCommRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkTCPIP</name>\n                    <state>aaa.bbb.ccc.ddd</state>\n                </option>\n                <option>\n                    <name>CCJLinkSpeedRadioV2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCUSBDevice</name>\n                    <version>1</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCRDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchUndef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchData</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchPrefetch</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCJLinkInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJLinkResetList</name>\n                    <version>6</version>\n                    <state>5</state>\n                </option>\n                <option>\n                    <name>CCJLinkInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJLinkUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCTcpIpAlt</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkTcpIpSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSwoClockAuto</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSwoClockEdit</name>\n                    <state>2000</state>\n                </option>\n                <option>\n                    <name>OCJLinkTraceSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkTraceSourceDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkDeviceName</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>LMIFTDI_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>3</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>LmiftdiSpeed</name>\n                    <state>500</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCLmiFtdiInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCLmiFtdiInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCLmiftdiUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiResetList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>NULINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>PEMICRO_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>3</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJPEMicroShowSettings</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>STLINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>8</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSTLinkInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSTLinkInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkResetList</name>\n                    <version>3</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSwoClockAuto</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSwoClockEdit</name>\n                    <state>2000</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCSTLinkDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSTLinkUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkJtagSpeedList</name>\n                    <version>2</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkDAPNumber</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSTLinkDebugAccessPortRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUseServerSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkProbeList</name>\n                    <version>1</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkTargetVccEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSTLinkTargetVoltage</name>\n                    <state>3.3</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>THIRDPARTY_ID</name>\n         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              <option>\n                    <name>CCMSPFetDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCMSPFetRadioEraseFlash</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>XDS100_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>9</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>TIPackageOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TIPackage</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>BoardFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCXds100BreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100DoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100UpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchUndef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchData</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchPrefetch</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCXds100SwoClockAuto</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100SwoClockEdit</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCXds100HWResetDelay</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100ResetList</name>\n                    <version>1</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100UsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCXds100UsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100JtagSpeedList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100InterfaceRadio</name>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCXds100InterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100ProbeList</name>\n                    <version>0</version>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>CCXds100SWOPortRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100SWOPort</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCXDSTargetVccEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXDSTargetVoltage</name>\n                    <state>###Uninitialized###</state>\n                </option>\n                <option>\n                    <name>OCXDSDigitalStatesConfigFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCSelectedCoreName</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <debuggerPlugins>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\CMX\\CmxArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\CMX\\CmxTinyArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\embOS\\embOSPlugin.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\FreeRtos\\FreeRtosArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\Mbed\\MbedArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\Mbed\\MbedArmPlugin2.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\OpenRTOS\\OpenRTOSPlugin.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\SafeRTOS\\SafeRTOSPlugin.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\SMX\\smxAwareIarArm9.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\SMX\\smxAwareIarArm9BE.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\ThreadX\\ThreadXArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\uCOS-II\\uCOS-II-286-KA-CSpy.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\uCOS-II\\uCOS-II-KA-CSpy.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\uCOS-III\\uCOS-III-KA-CSpy.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$EW_DIR$\\common\\plugins\\Orti\\Orti.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$EW_DIR$\\common\\plugins\\TargetAccessServer\\TargetAccessServer.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$EW_DIR$\\common\\plugins\\uCProbe\\uCProbePlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n        </debuggerPlugins>\n    </configuration>\n</project>\n"
  },
  {
    "path": "sst0_c/examples/blinky_button/iar/nucleo-c031c6.ewp",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<project>\n    <fileVersion>3</fileVersion>\n    <configuration>\n        <name>Debug</name>\n        <toolchain>\n            <name>ARM</name>\n        </toolchain>\n        <debug>1</debug>\n        <settings>\n            <name>General</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <version>35</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>BrowseInfoPath</name>\n                    <state>build_nucleo-c031c6</state>\n                </option>\n                <option>\n                    <name>ExePath</name>\n                    <state>build_nucleo-c031c6</state>\n                </option>\n                <option>\n                    <name>ObjPath</name>\n                    <state>build_nucleo-c031c6</state>\n                </option>\n                <option>\n                    <name>ListPath</name>\n                    <state>build_nucleo-c031c6</state>\n                </option>\n                <option>\n                    <name>GEndianMode</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>Input description</name>\n                    <state>No specifier n, no float nor long long, no scan set, no assignment suppressing, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>Output description</name>\n                    <state>No specifier a, A, no specifier n, no float nor long long, no flags, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>GOutputBinary</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGCoreOrChip</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelect</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelectSlave</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RTDescription</name>\n                    <state>A compact configuration of the C/C++14 runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\n                </option>\n                <option>\n                    <name>OGProductVersion</name>\n                    <state>5.11.0.50579</state>\n                </option>\n                <option>\n                    <name>OGLastSavedByProductVersion</name>\n                    <state>9.32.1.54977</state>\n                </option>\n                <option>\n                    <name>OGChipSelectEditMenu</name>\n                    <state>STM32C031C6\tST STM32C031C6</state>\n                </option>\n                <option>\n                    <name>GenLowLevelInterface</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GEndianModeBE</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OGBufferedTerminalOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GenStdoutInterface</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RTConfigPath2</name>\n                    <state>$TOOLKIT_DIR$\\inc\\c\\DLib_Config_Normal.h</state>\n                </option>\n                <option>\n                    <name>GBECoreSlave</name>\n                    <version>32</version>\n                    <state>35</state>\n                </option>\n                <option>\n                    <name>OGUseCmsis</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGUseCmsisDspLib</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibThreads</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CoreVariant</name>\n                    <version>32</version>\n                    <state>35</state>\n                </option>\n                <option>\n                    <name>GFPUDeviceSlave</name>\n                    <state>STM32C031C6\tST STM32C031C6</state>\n                </option>\n                <option>\n                    <name>FPU2</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>NrRegs</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>NEON</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GFPUCoreSlave2</name>\n                    <version>32</version>\n                    <state>35</state>\n                </option>\n                <option>\n                    <name>OGCMSISPackSelectDevice</name>\n                </option>\n                <option>\n                    <name>OgLibHeap</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGLibAdditionalLocale</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGPrintfVariant</name>\n                    <version>0</version>\n                    <state>4</state>\n                </option>\n                <option>\n                    <name>OGPrintfMultibyteSupport</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGScanfVariant</name>\n                    <version>0</version>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>OGScanfMultibyteSupport</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GenLocaleTags</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>GenLocaleDisplayOnly</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DSPExtension</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TrustZone</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TrustZoneModes</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGAarch64Abi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OG_32_64Device</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>BuildFilesPath</name>\n                    <state>Debug</state>\n                </option>\n                <option>\n                    <name>PointerAuthentication</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>FPU64</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>ICCARM</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>37</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CCOptimizationNoSizeConstraints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCDefines</name>\n                    <state>STM32C031xx</state>\n                </option>\n                <option>\n                    <name>CCPreprocFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPreprocComments</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPreprocLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCMnemonics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCMessages</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListAssFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListAssSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEnableRemarks</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCDiagSuppress</name>\n                    <state>Pa050</state>\n                </option>\n                <option>\n                    <name>CCDiagRemark</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagWarning</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagError</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCObjPrefix</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCAllowList</name>\n                    <version>1</version>\n                    <state>10010100</state>\n                </option>\n                <option>\n                    <name>CCDebugInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IEndianMode</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IExtraOptionsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCLangConformance</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSignedPlainChar</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCRequirePrototypes</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCDiagWarnAreErr</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCompilerRuntimeInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OutputFile</name>\n                    <state>$FILE_BNAME$.o</state>\n                </option>\n                <option>\n                    <name>CCLibConfigHeader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>PreInclude</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCIncludePath2</name>\n                    <state>$PROJ_DIR$\\..</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\include</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\ports\\arm-cm</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\CMSIS\\Include</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\nucleo-c031c6</state>\n                </option>\n                <option>\n                    <name>CCStdIncCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCodeSection</name>\n                    <state>.text</state>\n                </option>\n                <option>\n                    <name>IProcessorMode2</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCOptLevel</name>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCOptStrategy</name>\n                    <version>0</version>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCOptLevelSlave</name>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCPosIndRopi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPosIndRwpi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPosIndNoDynInit</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccLang</name>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>IccCDialect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccAllowVLA</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccStaticDestr</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccCppInlineSemantics</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccCmsis</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccFloatSemantics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCNoLiteralPool</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCOptStrategySlave</name>\n                    <version>0</version>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCGuardCalls</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCEncSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEncOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEncOutputBom</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCEncInput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccExceptions2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccRTTI2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OICompilerExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCStackProtection</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>AARM</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>11</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>AObjPrefix</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AEndian</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>ACaseSensitivity</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacroChars</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnWhat</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnOne</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AWarnRange1</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AWarnRange2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>ADebug</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AltRegisterNames</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ADefines</name>\n                    <state>ewarm</state>\n                </option>\n                <option>\n                    <name>AList</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AListHeader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AListing</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>Includes</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacDefs</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacExps</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacExec</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OnlyAssed</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MultiLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PageLengthCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PageLength</name>\n                    <state>80</state>\n                </option>\n                <option>\n                    <name>TabSpacing</name>\n                    <state>8</state>\n                </option>\n                <option>\n                    <name>AXRef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefDefines</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefInternal</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefDual</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AOutputFile</name>\n                    <state>$FILE_BNAME$.o</state>\n                </option>\n                <option>\n                    <name>ALimitErrorsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ALimitErrorsEdit</name>\n                    <state>100</state>\n                </option>\n                <option>\n                    <name>AIgnoreStdInclude</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AUserIncludes</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AExtraOptionsCheckV2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AExtraOptionsV2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AsmNoLiteralPool</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PreInclude</name>\n                    <state></state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>OBJCOPY</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>1</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OOCOutputFormat</name>\n                    <version>3</version>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>OCOutputOverride</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OOCOutputFile</name>\n                    <state>blinky_button.bin</state>\n                </option>\n                <option>\n                    <name>OOCCommandLineProducer</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OOCObjCopyEnable</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CUSTOM</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <extensions></extensions>\n                <cmdline></cmdline>\n                <hasPrio>1</hasPrio>\n                <buildSequence>inputOutputBased</buildSequence>\n            </data>\n        </settings>\n        <settings>\n            <name>BUILDACTION</name>\n            <archiveVersion>1</archiveVersion>\n            <data>\n                <prebuild></prebuild>\n                <postbuild></postbuild>\n            </data>\n        </settings>\n        <settings>\n            <name>ILINK</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>27</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>IlinkLibIOConfig</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkInputFileSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOutputFile</name>\n                    <state>blinky_button.out</state>\n                </option>\n                <option>\n                    <name>IlinkDebugInfoEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkKeepSymbols</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySymbol</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySegment</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryAlign</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkDefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkConfigDefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkMapFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLogFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogInitialization</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogModule</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogSection</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogVeneer</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFile</name>\n                    <state>$TOOLKIT_DIR$/config/linker/ST/stm32c03xx6.icf</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFileSlave</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkEnableRemarks</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkSuppressDiags</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsRem</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsWarn</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsErr</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkWarningsAreErrors</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkUseExtraOptions</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkLowLevelInterfaceSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkAutoLibEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkAdditionalLibs</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkOverrideProgramEntryLabel</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkProgramEntryLabelSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkProgramEntryLabel</name>\n                    <state>__iar_program_start</state>\n                </option>\n                <option>\n                    <name>DoFill</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>FillerByte</name>\n                    <state>0xFF</state>\n                </option>\n                <option>\n                    <name>FillerStart</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>FillerEnd</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>CrcSize</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcAlign</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcPoly</name>\n                    <state>0x11021</state>\n                </option>\n                <option>\n                    <name>CrcCompl</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CrcBitOrder</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CrcInitialValue</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>DoCrc</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkBE8Slave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkBufferedTerminalOutput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkStdoutInterfaceSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcFullSize</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIElfToolPostProcess</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogAutoLibSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogRedirSymbols</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogUnusedFragments</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCrcReverseByteOrder</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCrcUseAsInput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptInline</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOptExceptionsAllow</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOptExceptionsForce</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCmsis</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptMergeDuplSections</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOptUseVfe</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptForceVfe</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkStackAnalysisEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkStackControlFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkStackCallGraphFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CrcAlgorithm</name>\n                    <version>1</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcUnitSize</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkThreadsSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLogCallGraph</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFile_AltDefault</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkEncInput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutputBom</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkHeapSelect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLocaleSelect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkTrustzoneImportLibraryOut</name>\n                    <state>iar_nucleo-c031c6_import_lib.o</state>\n                </option>\n                <option>\n                    <name>OILinkExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryFile2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySymbol2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySegment2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryAlign2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkLogCrtRoutineSelection</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogFragmentInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogInlining</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogMerging</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkDemangle</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkWrapperFileEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkWrapperFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkFpuProcessor</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>IARCHIVE</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>IarchiveInputs</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IarchiveOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IarchiveOutput</name>\n                    <state>###Unitialized###</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>Coder</name>\n            <archiveVersion>0</archiveVersion>\n            <data />\n        </settings>\n    </configuration>\n    <mfc>\n        <configuration>Debug</configuration>\n    </mfc>\n    <group>\n        <name>Application</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\blinky1.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\blinky3.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\blinky_button.h</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\bsp.h</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\bsp_nucleo-c031c6.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\button2a.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\button2b.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\main.c</name>\n        </file>\n    </group>\n    <group>\n        <name>nucleo-c031c6</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\nucleo-c031c6\\iar\\startup_stm32c031xx.s</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\nucleo-c031c6\\stm32c031xx.h</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\nucleo-c031c6\\system_stm32c0xx.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\nucleo-c031c6\\system_stm32c0xx.h</name>\n        </file>\n    </group>\n    <group>\n        <name>sst</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\src\\sst0.c</name>\n        </file>\n    </group>\n    <group>\n        <name>sst_port</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\ports\\arm-cm\\sst_port.h</name>\n        </file>\n    </group>\n</project>\n"
  },
  {
    "path": "sst0_c/examples/blinky_button/iar/nucleo-c031c6.eww",
    "content": "<?xml version=\"1.0\" encoding=\"iso-8859-1\"?>\n\n<workspace>\n  <project>\n    <path>$WS_DIR$\\nucleo-c031c6.ewp</path>\n  </project>\n  <batchBuild/>\n</workspace>\n\n\n"
  },
  {
    "path": "sst0_c/examples/blinky_button/iar/nucleo-h743zi.ewd",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<project>\n    <fileVersion>3</fileVersion>\n    <configuration>\n        <name>Debug</name>\n        <toolchain>\n            <name>ARM</name>\n        </toolchain>\n        <debug>1</debug>\n        <settings>\n            <name>C-SPY</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>32</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CInput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CEndian</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCVariant</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>MemOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MemFile</name>\n                    <state>$TOOLKIT_DIR$\\CONFIG\\debugger\\ST\\STM32H743ZI.ddf</state>\n                </option>\n                <option>\n                    <name>RunToEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RunToName</name>\n                    <state>main</state>\n                </option>\n                <option>\n                    <name>CExtraOptionsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCDDFArgumentProducer</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCDownloadSuppressDownload</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCDownloadVerifyAll</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProductVersion</name>\n                    <state>9.10.2.39304</state>\n                </option>\n                <option>\n                    <name>OCDynDriverList</name>\n                    <state>STLINK_ID</state>\n                </option>\n                <option>\n                    <name>OCLastSavedByProductVersion</name>\n                    <state>9.32.1.54977</state>\n                </option>\n                <option>\n                    <name>UseFlashLoader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CLowLevel</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCBE8Slave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacFile2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CDevice</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>FlashLoadersV3</name>\n                    <state>$TOOLKIT_DIR$/config/flashloader/ST/FlashSTM32H7xxxI.board</state>\n                </option>\n                <option>\n                    <name>OCImagesSuppressCheck1</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesPath1</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCImagesSuppressCheck2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesPath2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCImagesSuppressCheck3</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesPath3</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OverrideDefFlashBoard</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesOffset1</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCImagesOffset2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCImagesOffset3</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCImagesUse1</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesUse2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesUse3</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCDeviceConfigMacroFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCDebuggerExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCAllMTBOptions</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCMulticoreNrOfCores</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCMulticoreWorkspace</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCMulticoreSlaveProject</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCMulticoreSlaveConfiguration</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCDownloadExtraImage</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCAttachSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MassEraseBeforeFlashing</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCMulticoreNrOfCoresSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCMulticoreAMPConfigType</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCMulticoreSessionFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCTpiuBaseOption</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>ARMSIM_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>1</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCSimDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCSimEnablePSP</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCSimPspOverrideConfig</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCSimPspConfigFile</name>\n                    <state></state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CADI_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CCadiMemory</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>Fast Model</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCADILogFileCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCADILogFileEditB</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CMSISDAP_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>4</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCIarProbeScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CMSISDAPResetList</name>\n                    <version>1</version>\n                    <state>10</state>\n                </option>\n                <option>\n                    <name>CMSISDAPHWResetDuration</name>\n                    <state>300</state>\n                </option>\n                <option>\n                    <name>CMSISDAPHWResetDelay</name>\n                    <state>200</state>\n                </option>\n                <option>\n                    <name>CMSISDAPDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CMSISDAPInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CMSISDAPInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiTargetEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPJtagSpeedList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPRestoreBreakpointsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPUpdateBreakpointsEdit</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>RDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchUndef</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchData</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchPrefetch</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchMMERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchNOCPERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchCHKERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSTATERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchBUSERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchINTERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSFERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchHARDERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiCPUEnable</name>\n     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<name>OCJetEmuParams</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCCMSISDAPUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCCMSISDAPUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>GDBSERVER_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>TCPIP</name>\n                    <state>aaa.bbb.ccc.ddd</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCJTagBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJTagDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJTagUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>IJET_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>9</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n      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<state>0</state>\n                </option>\n                <option>\n                    <name>IjetDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>IjetInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiTargetEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetScanChainNonARMDevices</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetIRLength</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetJtagSpeedList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetProtocolRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetSwoPin</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IjetSwoPrescalerList</name>\n                    <version>1</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetRestoreBreakpointsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetUpdateBreakpointsEdit</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>RDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchUndef</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchData</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchPrefetch</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchMMERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchNOCPERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchCHKERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSTATERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchBUSERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchINTERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSFERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchHARDERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeCfgOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeConfig</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IjetProbeConfigRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiCPUEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiCPUNumber</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetSelectedCPUBehaviour</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ICpuName</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCJetEmuParams</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetPreferETB</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetTraceSettingsList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetTraceSizeList</name>\n                    <version>0</version>\n                    <state>4</state>\n                </option>\n                <option>\n                    <name>FlashBoardPathSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCIjetUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCIjetUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL3S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL3S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL3S</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>JLINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>16</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>JLinkSpeed</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCJLinkDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCJLinkHWResetDelay</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>JLinkInitialSpeed</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCDoJlinkMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCScanChainNonARMDevices</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkIRLength</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkCommRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkTCPIP</name>\n                    <state>aaa.bbb.ccc.ddd</state>\n                </option>\n                <option>\n                    <name>CCJLinkSpeedRadioV2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCUSBDevice</name>\n                    <version>1</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCRDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchUndef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchData</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchPrefetch</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCJLinkInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJLinkResetList</name>\n                    <version>6</version>\n                    <state>5</state>\n                </option>\n                <option>\n                    <name>CCJLinkInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJLinkUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCTcpIpAlt</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkTcpIpSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSwoClockAuto</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSwoClockEdit</name>\n                    <state>2000</state>\n                </option>\n                <option>\n                    <name>OCJLinkTraceSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkTraceSourceDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkDeviceName</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>LMIFTDI_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>3</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>LmiftdiSpeed</name>\n                    <state>500</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCLmiFtdiInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCLmiFtdiInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCLmiftdiUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiResetList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>NULINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>PEMICRO_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>3</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJPEMicroShowSettings</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>STLINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>8</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSTLinkInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSTLinkInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkResetList</name>\n                    <version>3</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCpuClockEdit</name>\n                    <state>480</state>\n                </option>\n                <option>\n                    <name>CCSwoClockAuto</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSwoClockEdit</name>\n                    <state>2000</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCSTLinkDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSTLinkUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkJtagSpeedList</name>\n                    <version>2</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkDAPNumber</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSTLinkDebugAccessPortRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUseServerSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkProbeList</name>\n                    <version>1</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkTargetVccEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSTLinkTargetVoltage</name>\n                    <state>3.3</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>THIRDPARTY_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CThirdPartyDriverDll</name>\n                    <state>###Uninitialized###</state>\n                </option>\n                <option>\n                    <name>CThirdPartyLogFileCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CThirdPartyLogFileEditB</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n            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<name>CCMSPFetTargetVccTypeDefault</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetTargetVoltage</name>\n                    <state>###Uninitialized###</state>\n                </option>\n                <option>\n                    <name>CCMSPFetVCCDefault</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCMSPFetTargetSettlingtime</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetRadioJtagSpeedType</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCMSPFetConnection</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetUsbComPort</name>\n                    <state>Automatic</state>\n                </option>\n                <option>\n                    <name>CCMSPFetAllowAccessToBSL</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCMSPFetRadioEraseFlash</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>XDS100_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>9</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>TIPackageOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TIPackage</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>BoardFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCXds100BreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100DoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100UpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchUndef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchData</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchPrefetch</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCXds100SwoClockAuto</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100SwoClockEdit</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCXds100HWResetDelay</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100ResetList</name>\n                    <version>1</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100UsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCXds100UsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100JtagSpeedList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100InterfaceRadio</name>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCXds100InterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100ProbeList</name>\n                    <version>0</version>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>CCXds100SWOPortRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100SWOPort</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCXDSTargetVccEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXDSTargetVoltage</name>\n                    <state>###Uninitialized###</state>\n                </option>\n                <option>\n                    <name>OCXDSDigitalStatesConfigFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCSelectedCoreName</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <debuggerPlugins>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\CMX\\CmxArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\CMX\\CmxTinyArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\embOS\\embOSPlugin.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\FreeRtos\\FreeRtosArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\Mbed\\MbedArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\Mbed\\MbedArmPlugin2.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\OpenRTOS\\OpenRTOSPlugin.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\SafeRTOS\\SafeRTOSPlugin.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\SMX\\smxAwareIarArm9.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\SMX\\smxAwareIarArm9BE.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\ThreadX\\ThreadXArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\uCOS-II\\uCOS-II-286-KA-CSpy.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\uCOS-II\\uCOS-II-KA-CSpy.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\uCOS-III\\uCOS-III-KA-CSpy.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$EW_DIR$\\common\\plugins\\Orti\\Orti.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$EW_DIR$\\common\\plugins\\TargetAccessServer\\TargetAccessServer.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$EW_DIR$\\common\\plugins\\uCProbe\\uCProbePlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n        </debuggerPlugins>\n    </configuration>\n</project>\n"
  },
  {
    "path": "sst0_c/examples/blinky_button/iar/nucleo-h743zi.ewp",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<project>\n    <fileVersion>3</fileVersion>\n    <configuration>\n        <name>Debug</name>\n        <toolchain>\n            <name>ARM</name>\n        </toolchain>\n        <debug>1</debug>\n        <settings>\n            <name>General</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <version>35</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>BrowseInfoPath</name>\n                    <state>build_nucleo-h743zi</state>\n                </option>\n                <option>\n                    <name>ExePath</name>\n                    <state>build_nucleo-h743zi</state>\n                </option>\n                <option>\n                    <name>ObjPath</name>\n                    <state>build_nucleo-h743zi</state>\n                </option>\n                <option>\n                    <name>ListPath</name>\n                    <state>build_nucleo-h743zi</state>\n                </option>\n                <option>\n                    <name>GEndianMode</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>Input description</name>\n                    <state>No specifier n, no float nor long long, no scan set, no assignment suppressing, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>Output description</name>\n                    <state>No specifier a, A, no specifier n, no float nor long long, no flags, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>GOutputBinary</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGCoreOrChip</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelect</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelectSlave</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RTDescription</name>\n                    <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\n                </option>\n                <option>\n                    <name>OGProductVersion</name>\n                    <state>5.11.0.50579</state>\n                </option>\n                <option>\n                    <name>OGLastSavedByProductVersion</name>\n                    <state>9.32.1.54977</state>\n                </option>\n                <option>\n                    <name>OGChipSelectEditMenu</name>\n                    <state>STM32H743ZI\tST STM32H743ZI</state>\n                </option>\n                <option>\n                    <name>GenLowLevelInterface</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GEndianModeBE</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OGBufferedTerminalOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GenStdoutInterface</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RTConfigPath2</name>\n                    <state>$TOOLKIT_DIR$\\inc\\c\\DLib_Config_Normal.h</state>\n                </option>\n                <option>\n                    <name>GBECoreSlave</name>\n                    <version>32</version>\n                    <state>41</state>\n                </option>\n                <option>\n                    <name>OGUseCmsis</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGUseCmsisDspLib</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibThreads</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CoreVariant</name>\n                    <version>32</version>\n                    <state>41</state>\n                </option>\n                <option>\n                    <name>GFPUDeviceSlave</name>\n                    <state>STM32H743ZI\tST STM32H743ZI</state>\n                </option>\n                <option>\n                    <name>FPU2</name>\n                    <version>0</version>\n                    <state>7</state>\n                </option>\n                <option>\n                    <name>NrRegs</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>NEON</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GFPUCoreSlave2</name>\n                    <version>32</version>\n                    <state>41</state>\n                </option>\n                <option>\n                    <name>OGCMSISPackSelectDevice</name>\n                </option>\n                <option>\n                    <name>OgLibHeap</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGLibAdditionalLocale</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGPrintfVariant</name>\n                    <version>0</version>\n                    <state>4</state>\n                </option>\n                <option>\n                    <name>OGPrintfMultibyteSupport</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGScanfVariant</name>\n                    <version>0</version>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>OGScanfMultibyteSupport</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GenLocaleTags</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>GenLocaleDisplayOnly</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DSPExtension</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>TrustZone</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TrustZoneModes</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGAarch64Abi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OG_32_64Device</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>BuildFilesPath</name>\n                    <state>Debug</state>\n                </option>\n                <option>\n                    <name>PointerAuthentication</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>FPU64</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>ICCARM</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>37</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CCOptimizationNoSizeConstraints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCDefines</name>\n                    <state>STM32H743xx</state>\n                </option>\n                <option>\n                    <name>CCPreprocFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPreprocComments</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPreprocLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCMnemonics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCMessages</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListAssFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListAssSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEnableRemarks</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCDiagSuppress</name>\n                    <state>Pa050</state>\n                </option>\n                <option>\n                    <name>CCDiagRemark</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagWarning</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagError</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCObjPrefix</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCAllowList</name>\n                    <version>1</version>\n                    <state>10010100</state>\n                </option>\n                <option>\n                    <name>CCDebugInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IEndianMode</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IExtraOptionsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCLangConformance</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSignedPlainChar</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCRequirePrototypes</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCDiagWarnAreErr</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCompilerRuntimeInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OutputFile</name>\n                    <state>$FILE_BNAME$.o</state>\n                </option>\n                <option>\n                    <name>CCLibConfigHeader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>PreInclude</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCIncludePath2</name>\n                    <state>$PROJ_DIR$\\..</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\include</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\ports\\arm-cm</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\CMSIS\\Include</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\nucleo-h743zi</state>\n                </option>\n                <option>\n                    <name>CCStdIncCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCodeSection</name>\n                    <state>.text</state>\n                </option>\n                <option>\n                    <name>IProcessorMode2</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCOptLevel</name>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCOptStrategy</name>\n                    <version>0</version>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCOptLevelSlave</name>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCPosIndRopi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPosIndRwpi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPosIndNoDynInit</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccLang</name>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>IccCDialect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccAllowVLA</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccStaticDestr</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccCppInlineSemantics</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccCmsis</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccFloatSemantics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCNoLiteralPool</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCOptStrategySlave</name>\n                    <version>0</version>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCGuardCalls</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCEncSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEncOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEncOutputBom</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCEncInput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccExceptions2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccRTTI2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OICompilerExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCStackProtection</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>AARM</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>11</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>AObjPrefix</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AEndian</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>ACaseSensitivity</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacroChars</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnWhat</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnOne</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AWarnRange1</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AWarnRange2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>ADebug</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AltRegisterNames</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ADefines</name>\n                    <state>ewarm</state>\n                </option>\n                <option>\n                    <name>AList</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AListHeader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AListing</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>Includes</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacDefs</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacExps</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacExec</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OnlyAssed</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MultiLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PageLengthCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PageLength</name>\n                    <state>80</state>\n                </option>\n                <option>\n                    <name>TabSpacing</name>\n                    <state>8</state>\n                </option>\n                <option>\n                    <name>AXRef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefDefines</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefInternal</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefDual</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AOutputFile</name>\n                    <state>$FILE_BNAME$.o</state>\n                </option>\n                <option>\n                    <name>ALimitErrorsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ALimitErrorsEdit</name>\n                    <state>100</state>\n                </option>\n                <option>\n                    <name>AIgnoreStdInclude</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AUserIncludes</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AExtraOptionsCheckV2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AExtraOptionsV2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AsmNoLiteralPool</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PreInclude</name>\n                    <state></state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>OBJCOPY</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>1</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OOCOutputFormat</name>\n                    <version>3</version>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>OCOutputOverride</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OOCOutputFile</name>\n                    <state>blinky_button.bin</state>\n                </option>\n                <option>\n                    <name>OOCCommandLineProducer</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OOCObjCopyEnable</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CUSTOM</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <extensions></extensions>\n                <cmdline></cmdline>\n                <hasPrio>1</hasPrio>\n                <buildSequence>inputOutputBased</buildSequence>\n            </data>\n        </settings>\n        <settings>\n            <name>BUILDACTION</name>\n            <archiveVersion>1</archiveVersion>\n            <data>\n                <prebuild></prebuild>\n                <postbuild></postbuild>\n            </data>\n        </settings>\n        <settings>\n            <name>ILINK</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>27</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>IlinkLibIOConfig</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkInputFileSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOutputFile</name>\n                    <state>blinky_button.out</state>\n                </option>\n                <option>\n                    <name>IlinkDebugInfoEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkKeepSymbols</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySymbol</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySegment</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryAlign</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkDefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkConfigDefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkMapFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLogFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogInitialization</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogModule</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogSection</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogVeneer</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFile</name>\n                    <state>$TOOLKIT_DIR$\\config\\linker\\ST\\stm32h743xI.icf</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFileSlave</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkEnableRemarks</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkSuppressDiags</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsRem</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsWarn</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsErr</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkWarningsAreErrors</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkUseExtraOptions</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkLowLevelInterfaceSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkAutoLibEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkAdditionalLibs</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkOverrideProgramEntryLabel</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkProgramEntryLabelSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkProgramEntryLabel</name>\n                    <state>__iar_program_start</state>\n                </option>\n                <option>\n                    <name>DoFill</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>FillerByte</name>\n                    <state>0xFF</state>\n                </option>\n                <option>\n                    <name>FillerStart</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>FillerEnd</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>CrcSize</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcAlign</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcPoly</name>\n                    <state>0x11021</state>\n                </option>\n                <option>\n                    <name>CrcCompl</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CrcBitOrder</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CrcInitialValue</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>DoCrc</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkBE8Slave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkBufferedTerminalOutput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkStdoutInterfaceSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcFullSize</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIElfToolPostProcess</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogAutoLibSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogRedirSymbols</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogUnusedFragments</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCrcReverseByteOrder</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCrcUseAsInput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptInline</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOptExceptionsAllow</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOptExceptionsForce</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCmsis</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptMergeDuplSections</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOptUseVfe</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptForceVfe</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkStackAnalysisEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkStackControlFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkStackCallGraphFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CrcAlgorithm</name>\n                    <version>1</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcUnitSize</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkThreadsSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLogCallGraph</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFile_AltDefault</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkEncInput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutputBom</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkHeapSelect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLocaleSelect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkTrustzoneImportLibraryOut</name>\n                    <state>iar_nucleo-h743zi_import_lib.o</state>\n                </option>\n                <option>\n                    <name>OILinkExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryFile2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySymbol2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySegment2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryAlign2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkLogCrtRoutineSelection</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogFragmentInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogInlining</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogMerging</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkDemangle</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkWrapperFileEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkWrapperFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkFpuProcessor</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>IARCHIVE</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>IarchiveInputs</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IarchiveOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IarchiveOutput</name>\n                    <state>###Unitialized###</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>Coder</name>\n            <archiveVersion>0</archiveVersion>\n            <data />\n        </settings>\n    </configuration>\n    <group>\n        <name>Application</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\blinky1.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\blinky3.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\blinky_button.h</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\bsp.h</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\bsp_nucleo-h743zi.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\button2a.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\button2b.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\main.c</name>\n        </file>\n    </group>\n    <group>\n        <name>nucleo-h743zi</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\nucleo-h743zi\\iar\\startup_stm32h743xx.s</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\nucleo-h743zi\\stm32h743xx.h</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\nucleo-h743zi\\system_stm32h7xx.c</name>\n        </file>\n    </group>\n    <group>\n        <name>sst</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\src\\sst0.c</name>\n        </file>\n    </group>\n    <group>\n        <name>sst_port</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\ports\\arm-cm\\sst_port.h</name>\n        </file>\n    </group>\n</project>\n"
  },
  {
    "path": "sst0_c/examples/blinky_button/iar/nucleo-h743zi.eww",
    "content": "<?xml version=\"1.0\" encoding=\"iso-8859-1\"?>\n\n<workspace>\n  <project>\n    <path>$WS_DIR$\\nucleo-h743zi.ewp</path>\n  </project>\n  <batchBuild/>\n</workspace>\n\n\n"
  },
  {
    "path": "sst0_c/examples/blinky_button/iar/nucleo-l053r8.ewd",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<project>\n    <fileVersion>3</fileVersion>\n    <configuration>\n        <name>Debug</name>\n        <toolchain>\n            <name>ARM</name>\n        </toolchain>\n        <debug>1</debug>\n        <settings>\n            <name>C-SPY</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>32</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CInput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CEndian</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCVariant</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>MemOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MemFile</name>\n                    <state>$TOOLKIT_DIR$\\CONFIG\\debugger\\ST\\STM32L053R8.ddf</state>\n                </option>\n                <option>\n                    <name>RunToEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RunToName</name>\n                    <state>main</state>\n                </option>\n                <option>\n                    <name>CExtraOptionsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCDDFArgumentProducer</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCDownloadSuppressDownload</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCDownloadVerifyAll</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProductVersion</name>\n                    <state>9.10.2.39304</state>\n                </option>\n                <option>\n                    <name>OCDynDriverList</name>\n                    <state>STLINK_ID</state>\n                </option>\n                <option>\n                    <name>OCLastSavedByProductVersion</name>\n                    <state>9.32.1.54977</state>\n                </option>\n                <option>\n                    <name>UseFlashLoader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CLowLevel</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCBE8Slave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacFile2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CDevice</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>FlashLoadersV3</name>\n                    <state>$TOOLKIT_DIR$/config/flashloader/ST/FlashSTM32L0xxx8.board</state>\n                </option>\n                <option>\n                    <name>OCImagesSuppressCheck1</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesPath1</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCImagesSuppressCheck2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesPath2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCImagesSuppressCheck3</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesPath3</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OverrideDefFlashBoard</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesOffset1</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCImagesOffset2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCImagesOffset3</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCImagesUse1</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesUse2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesUse3</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCDeviceConfigMacroFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCDebuggerExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCAllMTBOptions</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCMulticoreNrOfCores</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCMulticoreWorkspace</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCMulticoreSlaveProject</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCMulticoreSlaveConfiguration</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCDownloadExtraImage</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCAttachSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MassEraseBeforeFlashing</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCMulticoreNrOfCoresSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCMulticoreAMPConfigType</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCMulticoreSessionFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCTpiuBaseOption</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>ARMSIM_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>1</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCSimDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCSimEnablePSP</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCSimPspOverrideConfig</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCSimPspConfigFile</name>\n                    <state></state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CADI_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CCadiMemory</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>Fast Model</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCADILogFileCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCADILogFileEditB</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CMSISDAP_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>4</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCIarProbeScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CMSISDAPResetList</name>\n                    <version>1</version>\n                    <state>10</state>\n                </option>\n                <option>\n                    <name>CMSISDAPHWResetDuration</name>\n                    <state>300</state>\n                </option>\n                <option>\n                    <name>CMSISDAPHWResetDelay</name>\n                    <state>200</state>\n                </option>\n                <option>\n                    <name>CMSISDAPDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CMSISDAPInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CMSISDAPInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiTargetEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPJtagSpeedList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPRestoreBreakpointsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPUpdateBreakpointsEdit</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>RDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchUndef</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchData</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchPrefetch</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchMMERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchNOCPERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchCHKERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSTATERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchBUSERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchINTERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSFERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchHARDERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiCPUEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiCPUNumber</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeCfgOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeConfig</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CMSISDAPProbeConfigRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPSelectedCPUBehaviour</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ICpuName</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCJetEmuParams</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCCMSISDAPUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCCMSISDAPUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>GDBSERVER_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>TCPIP</name>\n                    <state>aaa.bbb.ccc.ddd</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCJTagBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJTagDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJTagUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>IJET_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>9</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCIarProbeScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetResetList</name>\n                    <version>1</version>\n                    <state>10</state>\n                </option>\n                <option>\n                    <name>IjetHWResetDuration</name>\n                    <state>300</state>\n                </option>\n                <option>\n                    <name>IjetHWResetDelay</name>\n                    <state>200</state>\n                </option>\n                <option>\n                    <name>IjetPowerFromProbe</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetPowerRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>IjetInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiTargetEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetScanChainNonARMDevices</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetIRLength</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetJtagSpeedList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetProtocolRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetSwoPin</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IjetSwoPrescalerList</name>\n                    <version>1</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetRestoreBreakpointsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetUpdateBreakpointsEdit</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>RDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchUndef</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchData</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchPrefetch</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchMMERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchNOCPERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchCHKERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSTATERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchBUSERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchINTERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSFERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchHARDERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeCfgOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeConfig</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IjetProbeConfigRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiCPUEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiCPUNumber</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetSelectedCPUBehaviour</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ICpuName</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCJetEmuParams</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetPreferETB</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetTraceSettingsList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetTraceSizeList</name>\n                    <version>0</version>\n                    <state>4</state>\n                </option>\n                <option>\n                    <name>FlashBoardPathSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCIjetUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCIjetUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL3S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL3S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL3S</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>JLINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>16</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>JLinkSpeed</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCJLinkDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCJLinkHWResetDelay</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>JLinkInitialSpeed</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCDoJlinkMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCScanChainNonARMDevices</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkIRLength</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkCommRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkTCPIP</name>\n                    <state>aaa.bbb.ccc.ddd</state>\n                </option>\n                <option>\n                    <name>CCJLinkSpeedRadioV2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCUSBDevice</name>\n                    <version>1</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCRDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchUndef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchData</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchPrefetch</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCJLinkInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJLinkResetList</name>\n                    <version>6</version>\n                    <state>5</state>\n                </option>\n                <option>\n                    <name>CCJLinkInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJLinkUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCTcpIpAlt</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkTcpIpSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSwoClockAuto</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSwoClockEdit</name>\n                    <state>2000</state>\n                </option>\n                <option>\n                    <name>OCJLinkTraceSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkTraceSourceDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkDeviceName</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>LMIFTDI_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>3</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>LmiftdiSpeed</name>\n                    <state>500</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCLmiFtdiInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCLmiFtdiInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCLmiftdiUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiResetList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>NULINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>PEMICRO_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>3</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJPEMicroShowSettings</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>STLINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>8</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSTLinkInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSTLinkInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkResetList</name>\n                    <version>3</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSwoClockAuto</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSwoClockEdit</name>\n                    <state>2000</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCSTLinkDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSTLinkUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkJtagSpeedList</name>\n                    <version>2</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkDAPNumber</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSTLinkDebugAccessPortRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUseServerSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkProbeList</name>\n                    <version>1</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkTargetVccEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSTLinkTargetVoltage</name>\n                    <state>3.3</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>THIRDPARTY_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CThirdPartyDriverDll</name>\n                    <state>###Uninitialized###</state>\n                </option>\n                <option>\n                    <name>CThirdPartyLogFileCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CThirdPartyLogFileEditB</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>TIFET_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>1</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCMSPFetResetList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetInterfaceRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetTargetVccTypeDefault</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetTargetVoltage</name>\n                    <state>###Uninitialized###</state>\n                </option>\n                <option>\n                    <name>CCMSPFetVCCDefault</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCMSPFetTargetSettlingtime</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetRadioJtagSpeedType</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCMSPFetConnection</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetUsbComPort</name>\n                    <state>Automatic</state>\n                </option>\n                <option>\n                    <name>CCMSPFetAllowAccessToBSL</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCMSPFetRadioEraseFlash</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>XDS100_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>9</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>TIPackageOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TIPackage</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>BoardFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCXds100BreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100DoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100UpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchUndef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchData</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchPrefetch</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCXds100SwoClockAuto</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100SwoClockEdit</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCXds100HWResetDelay</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100ResetList</name>\n                    <version>1</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100UsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCXds100UsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100JtagSpeedList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100InterfaceRadio</name>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCXds100InterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100ProbeList</name>\n                    <version>0</version>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>CCXds100SWOPortRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100SWOPort</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCXDSTargetVccEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXDSTargetVoltage</name>\n                    <state>###Uninitialized###</state>\n                </option>\n                <option>\n                    <name>OCXDSDigitalStatesConfigFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCSelectedCoreName</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <debuggerPlugins>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\CMX\\CmxArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\CMX\\CmxTinyArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\embOS\\embOSPlugin.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\FreeRtos\\FreeRtosArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\Mbed\\MbedArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\Mbed\\MbedArmPlugin2.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\OpenRTOS\\OpenRTOSPlugin.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\SafeRTOS\\SafeRTOSPlugin.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\SMX\\smxAwareIarArm9.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\SMX\\smxAwareIarArm9BE.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\ThreadX\\ThreadXArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\uCOS-II\\uCOS-II-286-KA-CSpy.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\uCOS-II\\uCOS-II-KA-CSpy.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\uCOS-III\\uCOS-III-KA-CSpy.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$EW_DIR$\\common\\plugins\\Orti\\Orti.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$EW_DIR$\\common\\plugins\\TargetAccessServer\\TargetAccessServer.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$EW_DIR$\\common\\plugins\\uCProbe\\uCProbePlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n        </debuggerPlugins>\n    </configuration>\n</project>\n"
  },
  {
    "path": "sst0_c/examples/blinky_button/iar/nucleo-l053r8.ewp",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<project>\n    <fileVersion>3</fileVersion>\n    <configuration>\n        <name>Debug</name>\n        <toolchain>\n            <name>ARM</name>\n        </toolchain>\n        <debug>1</debug>\n        <settings>\n            <name>General</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <version>35</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>BrowseInfoPath</name>\n                    <state>build_nucleo-l053r8</state>\n                </option>\n                <option>\n                    <name>ExePath</name>\n                    <state>build_nucleo-l053r8</state>\n                </option>\n                <option>\n                    <name>ObjPath</name>\n                    <state>build_nucleo-l053r8</state>\n                </option>\n                <option>\n                    <name>ListPath</name>\n                    <state>build_nucleo-l053r8</state>\n                </option>\n                <option>\n                    <name>GEndianMode</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>Input description</name>\n                    <state>No specifier n, no float nor long long, no scan set, no assignment suppressing, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>Output description</name>\n                    <state>No specifier a, A, no specifier n, no float nor long long, no flags, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>GOutputBinary</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGCoreOrChip</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelect</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelectSlave</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RTDescription</name>\n                    <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\n                </option>\n                <option>\n                    <name>OGProductVersion</name>\n                    <state>5.11.0.50579</state>\n                </option>\n                <option>\n                    <name>OGLastSavedByProductVersion</name>\n                    <state>9.32.1.54977</state>\n                </option>\n                <option>\n                    <name>OGChipSelectEditMenu</name>\n                    <state>STM32L053R8\tST STM32L053R8</state>\n                </option>\n                <option>\n                    <name>GenLowLevelInterface</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GEndianModeBE</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OGBufferedTerminalOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GenStdoutInterface</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RTConfigPath2</name>\n                    <state>$TOOLKIT_DIR$\\inc\\c\\DLib_Config_Normal.h</state>\n                </option>\n                <option>\n                    <name>GBECoreSlave</name>\n                    <version>32</version>\n                    <state>35</state>\n                </option>\n                <option>\n                    <name>OGUseCmsis</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGUseCmsisDspLib</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibThreads</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CoreVariant</name>\n                    <version>32</version>\n                    <state>35</state>\n                </option>\n                <option>\n                    <name>GFPUDeviceSlave</name>\n                    <state>STM32L053R8\tST STM32L053R8</state>\n                </option>\n                <option>\n                    <name>FPU2</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>NrRegs</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>NEON</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GFPUCoreSlave2</name>\n                    <version>32</version>\n                    <state>35</state>\n                </option>\n                <option>\n                    <name>OGCMSISPackSelectDevice</name>\n                </option>\n                <option>\n                    <name>OgLibHeap</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGLibAdditionalLocale</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGPrintfVariant</name>\n                    <version>0</version>\n                    <state>4</state>\n                </option>\n                <option>\n                    <name>OGPrintfMultibyteSupport</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGScanfVariant</name>\n                    <version>0</version>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>OGScanfMultibyteSupport</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GenLocaleTags</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>GenLocaleDisplayOnly</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DSPExtension</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TrustZone</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TrustZoneModes</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGAarch64Abi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OG_32_64Device</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>BuildFilesPath</name>\n                    <state>Debug</state>\n                </option>\n                <option>\n                    <name>PointerAuthentication</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>FPU64</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>ICCARM</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>37</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CCOptimizationNoSizeConstraints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCDefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCPreprocFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPreprocComments</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPreprocLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCMnemonics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCMessages</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListAssFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListAssSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEnableRemarks</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCDiagSuppress</name>\n                    <state>Pa050</state>\n                </option>\n                <option>\n                    <name>CCDiagRemark</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagWarning</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagError</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCObjPrefix</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCAllowList</name>\n                    <version>1</version>\n                    <state>10010100</state>\n                </option>\n                <option>\n                    <name>CCDebugInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IEndianMode</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IExtraOptionsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCLangConformance</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSignedPlainChar</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCRequirePrototypes</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCDiagWarnAreErr</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCompilerRuntimeInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OutputFile</name>\n                    <state>$FILE_BNAME$.o</state>\n                </option>\n                <option>\n                    <name>CCLibConfigHeader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>PreInclude</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCIncludePath2</name>\n                    <state>$PROJ_DIR$\\..</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\include</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\ports\\arm-cm</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\CMSIS\\Include</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\nucleo-l053r8</state>\n                </option>\n                <option>\n                    <name>CCStdIncCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCodeSection</name>\n                    <state>.text</state>\n                </option>\n                <option>\n                    <name>IProcessorMode2</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCOptLevel</name>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCOptStrategy</name>\n                    <version>0</version>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCOptLevelSlave</name>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCPosIndRopi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPosIndRwpi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPosIndNoDynInit</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccLang</name>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>IccCDialect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccAllowVLA</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccStaticDestr</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccCppInlineSemantics</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccCmsis</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccFloatSemantics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCNoLiteralPool</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCOptStrategySlave</name>\n                    <version>0</version>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCGuardCalls</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCEncSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEncOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEncOutputBom</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCEncInput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccExceptions2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccRTTI2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OICompilerExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCStackProtection</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>AARM</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>11</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>AObjPrefix</name>\n                    <state>1</state>\n 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</option>\n                <option>\n                    <name>AOutputFile</name>\n                    <state>$FILE_BNAME$.o</state>\n                </option>\n                <option>\n                    <name>ALimitErrorsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ALimitErrorsEdit</name>\n                    <state>100</state>\n                </option>\n                <option>\n                    <name>AIgnoreStdInclude</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AUserIncludes</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AExtraOptionsCheckV2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AExtraOptionsV2</name>\n                    <state></state>\n             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<state>blinky_button.bin</state>\n                </option>\n                <option>\n                    <name>OOCCommandLineProducer</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OOCObjCopyEnable</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CUSTOM</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <extensions></extensions>\n                <cmdline></cmdline>\n                <hasPrio>1</hasPrio>\n                <buildSequence>inputOutputBased</buildSequence>\n            </data>\n        </settings>\n        <settings>\n            <name>BUILDACTION</name>\n            <archiveVersion>1</archiveVersion>\n            <data>\n                <prebuild></prebuild>\n                <postbuild></postbuild>\n            </data>\n        </settings>\n        <settings>\n            <name>ILINK</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>27</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>IlinkLibIOConfig</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkInputFileSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOutputFile</name>\n                    <state>blinky_button.out</state>\n                </option>\n                <option>\n                    <name>IlinkDebugInfoEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkKeepSymbols</name>\n                    <state></state>\n                </option>\n                <option>\n           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<state>0</state>\n                </option>\n                <option>\n                    <name>IlinkProgramEntryLabel</name>\n                    <state>__iar_program_start</state>\n                </option>\n                <option>\n                    <name>DoFill</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>FillerByte</name>\n                    <state>0xFF</state>\n                </option>\n                <option>\n                    <name>FillerStart</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>FillerEnd</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>CrcSize</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcAlign</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcPoly</name>\n                    <state>0x11021</state>\n                </option>\n                <option>\n                    <name>CrcCompl</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CrcBitOrder</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CrcInitialValue</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>DoCrc</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkBE8Slave</name>\n                    <state>1</state>\n                </option>\n      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               </option>\n                <option>\n                    <name>IlinkCrcReverseByteOrder</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCrcUseAsInput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptInline</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOptExceptionsAllow</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOptExceptionsForce</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCmsis</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptMergeDuplSections</name>\n                    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<name>CrcUnitSize</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkThreadsSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLogCallGraph</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFile_AltDefault</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkEncInput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutputBom</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkHeapSelect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLocaleSelect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkTrustzoneImportLibraryOut</name>\n                    <state>iar_nucleo-l053r8_import_lib.o</state>\n                </option>\n                <option>\n                    <name>OILinkExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryFile2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySymbol2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySegment2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryAlign2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkLogCrtRoutineSelection</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogFragmentInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogInlining</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogMerging</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkDemangle</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkWrapperFileEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkWrapperFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkFpuProcessor</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>IARCHIVE</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>IarchiveInputs</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IarchiveOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IarchiveOutput</name>\n                    <state>###Unitialized###</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>Coder</name>\n            <archiveVersion>0</archiveVersion>\n            <data />\n        </settings>\n    </configuration>\n    <mfc>\n        <configuration>Debug</configuration>\n    </mfc>\n    <group>\n        <name>Application</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\blinky1.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\blinky3.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\blinky_button.h</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\bsp.h</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\bsp_nucleo-l053r8.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\button2a.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\button2b.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\main.c</name>\n        </file>\n    </group>\n    <group>\n        <name>nucleo-l053r8</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\nucleo-l053r8\\iar\\startup_stm32l053xx.s</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\nucleo-l053r8\\stm32l053xx.h</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\nucleo-l053r8\\system_stm32l0xx.c</name>\n        </file>\n    </group>\n    <group>\n        <name>sst</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\src\\sst0.c</name>\n        </file>\n    </group>\n    <group>\n        <name>sst_port</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\ports\\arm-cm\\sst_port.h</name>\n        </file>\n    </group>\n</project>\n"
  },
  {
    "path": "sst0_c/examples/blinky_button/iar/nucleo-l053r8.eww",
    "content": "<?xml version=\"1.0\" encoding=\"iso-8859-1\"?>\n\n<workspace>\n  <project>\n    <path>$WS_DIR$\\nucleo-l053r8.ewp</path>\n  </project>\n  <batchBuild/>\n</workspace>\n\n\n"
  },
  {
    "path": "sst0_c/examples/blinky_button/main.c",
    "content": "/*============================================================================\n* Super-Simple Tasker (SST0/C) Example\n*\n* Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n*\n* SPDX-License-Identifier: MIT\n*\n* Permission is hereby granted, free of charge, to any person obtaining a\n* copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included in\n* all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n============================================================================*/\n#include \"sst.h\"           /* SST framework */\n#include \"bsp.h\"           /* Board Support Package interface */\n#include \"blinky_button.h\" /* application shared interface */\n\n/*..........................................................................*/\nint main() {\n    SST_init(); /* initialize the SST kernel */\n    BSP_init(); /* initialize the Board Support Package */\n\n    /* instantiate and start all SST tasks... */\n    Blinky1_instantiate();\n    static SST_Evt const *blinky1QSto[10]; /* Event queue storage */\n    SST_Task_start(\n        AO_Blinky1,     /* AO pointer to start */\n        1U,             /* SST-priority */\n        blinky1QSto,    /* storage for the AO's queue */\n        ARRAY_NELEM(blinky1QSto),   /* queue length */\n        BSP_getWorkEvtBlinky1(0U)); /* initialization event */\n\n    Button2a_instantiate();\n    static SST_Evt const *button2aQSto[8]; /* Event queue storage */\n    SST_Task_start(\n        AO_Button2a,    /* AO pointer to start */\n        2U,             /* SST-priority */\n        button2aQSto,   /* storage for the AO's queue */\n        ARRAY_NELEM(button2aQSto), /* queue length */\n        (SST_Evt const *)0); /* initialization event -- not used */\n\n    Button2b_instantiate();\n    static SST_Evt const *button2bQSto[6]; /* Event queue storage */\n    SST_Task_start(\n        AO_Button2b,    /* AO pointer to start */\n        3U,             /* SST-priority */\n        button2bQSto,   /* storage for the AO's queue */\n        ARRAY_NELEM(button2bQSto), /* queue length */\n        (SST_Evt const *)0); /* initialization event -- not used */\n\n    Blinky3_instantiate();\n    static SST_Evt const *blinky3QSto[4]; /* Event queue storage */\n    SST_Task_start(\n        AO_Blinky3,     /* AO pointer to start */\n        4U,             /* SST-priority */\n        blinky3QSto,    /* storage for the AO's queue */\n        ARRAY_NELEM(blinky3QSto),   /* queue length */\n        BSP_getWorkEvtBlinky3(0U)); /* initialization event */\n\n    return SST_Task_run(); /* run the SST tasks */\n    /* NOTE; in embedded systems SST_Task_run() should not return */\n}\n\n"
  },
  {
    "path": "sst0_c/ports/arm-cm/sst_port.h",
    "content": "/*============================================================================\n* Super-Simple Tasker (SST0/C) port to ARM Cortex-M\n*\n* Copyright (C) 2005-2023 Quantum Leaps, <state-machine.com>.\n*\n* SPDX-License-Identifier: MIT\n*\n* Permission is hereby granted, free of charge, to any person obtaining a\n* copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included in\n* all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n============================================================================*/\n#ifndef SST_PORT_H_\n#define SST_PORT_H_\n\n#define SST_PORT_TASK_ATTR SST_TaskPrio prio;\n\n#define SST_PORT_MAX_TASK 32U\n\n/* SST-PORT disabling/enabling interrupts */\n#define SST_PORT_INT_DISABLE() __asm volatile (\"cpsid i\")\n#define SST_PORT_INT_ENABLE()  __asm volatile (\"cpsie i\")\n\n/* SST-PORT critical section */\n#define SST_PORT_CRIT_STAT\n#define SST_PORT_CRIT_ENTRY() SST_PORT_INT_DISABLE()\n#define SST_PORT_CRIT_EXIT()  SST_PORT_INT_ENABLE()\n\ntypedef uint32_t SST_ReadySet;\n\n/* special idle callback to handle the \"idle condition\" in SST0 */\nvoid SST_onIdleCond(void);\n\n/* the SST scheduler lock key type */\ntypedef uint32_t SST_LockKey;\n\n#if (__ARM_ARCH == 6) /* ARMv6-M? */\n\n/* SST_LOG2() implementation for ARMv6-M (no CLZ instruction) */\nstatic inline uint_fast8_t SST_LOG2(uint32_t x) {\n    static uint8_t const log2LUT[16] = {\n        0U, 1U, 2U, 2U, 3U, 3U, 3U, 3U,\n        4U, 4U, 4U, 4U, 4U, 4U, 4U, 4U\n    };\n    uint_fast8_t n = 0U;\n    SST_ReadySet tmp;\n\n    #if (SST_PORT_MAX_TASK > 16U)\n    tmp = (SST_ReadySet)(x >> 16U);\n    if (tmp != 0U) {\n        n += 16U;\n        x = tmp;\n    }\n    #endif\n    #if (SST_PORT_MAX_TASK > 8U)\n    tmp = (x >> 8U);\n    if (tmp != 0U) {\n        n += 8U;\n        x = tmp;\n    }\n    #endif\n    tmp = (x >> 4U);\n    if (tmp != 0U) {\n        n += 4U;\n        x = tmp;\n    }\n    return n + log2LUT[x];\n}\n\n#else /* ARMv7-M+ have CLZ instruction for fast LOG2 computations */\n\n#if defined __ARMCC_VERSION\n    #define SST_LOG2(x_) ((uint_fast8_t)(32U - __builtin_clz((unsigned)(x_))))\n#elif defined __GNUC__\n    #define SST_LOG2(x_) ((uint_fast8_t)(32U - __builtin_clz((unsigned)(x_))))\n#elif defined __ICCARM__\n    #include <intrinsics.h>\n    #define SST_LOG2(x_) ((uint_fast8_t)(32U - __CLZ((unsigned long)(x_))))\n#endif /* compiler type */\n\n#endif\n\n#endif /* SST_PORT_H_ */\n"
  },
  {
    "path": "sst0_c/src/sst0.c",
    "content": "/*===========================================================================\n* Super-Simple Tasker (SST0/C)\n*\n* Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n*\n* SPDX-License-Identifier: MIT\n*\n* Permission is hereby granted, free of charge, to any person obtaining a\n* copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included in\n* all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n===========================================================================*/\n#include \"sst.h\"        /* Super-Simple Tasker (SST) */\n#include \"dbc_assert.h\" /* Design By Contract (DBC) assertions */\n\nDBC_MODULE_NAME(\"sst0\") /* for DBC assertions in this module */\n\n/* bitmask of all SST tasks in the system */\nstatic SST_ReadySet task_readySet;\n\n/* array of all SST task pointers in the system */\nstatic SST_Task *task_registry[SST_PORT_MAX_TASK + 1U];\n\n/*..........................................................................*/\nvoid SST_init(void) {\n}\n/*..........................................................................*/\nint SST_Task_run(void) {\n    SST_onStart(); /* configure and start the interrupts */\n\n    SST_PORT_INT_DISABLE();\n    for (;;) { /* event loop of the SST0 kernel */\n\n        if (task_readySet != 0U) { /* any SST tasks ready to run? */\n            uint_fast8_t const p = SST_LOG2(task_readySet);\n            SST_Task * const task = task_registry[p];\n            SST_PORT_INT_ENABLE();\n\n            /* the task must have some events in the queue */\n            DBC_ASSERT(100, task->nUsed > 0U);\n\n            /* get the event out of the queue */\n            /* NOTE: no critical section because task->tail is accessed only\n            * from this task\n            */\n            SST_Evt const *e = task->qBuf[task->tail];\n            if (task->tail == 0U) { /* need to wrap the tail? */\n                task->tail = task->end; /* wrap around */\n            }\n            else {\n                --task->tail;\n            }\n            SST_PORT_INT_DISABLE();\n            if ((--task->nUsed) == 0U) { /* no more events in the queue? */\n                task_readySet &= ~(1U << (p - 1U));\n            }\n            SST_PORT_INT_ENABLE();\n\n            /* dispatch the received event to the task */\n            (*task->dispatch)(task, e); /* NOTE: virtual call */\n            /* TBD: implement event recycling */\n        }\n        else { /* no SST tasks are ready to run --> idle */\n\n            /* SST_onIdleCond() must be called with interrupts DISABLED\n            * because the determination of the idle condition (all event\n            * queues empty) can change at any time by an interrupt posting\n            * events to a queue.\n            *\n            * NOTE: SST_onIdleCond() MUST enable interrupts internally,\n            * ideally at the same time as putting the CPU into a power-\n            * saving mode.\n            */\n            SST_onIdleCond();\n\n            SST_PORT_INT_DISABLE(); /* disable before looping back */\n        }\n    }\n#ifdef __GNUC__ /* GNU compiler? */\n    return 0;\n#endif\n}\n/*..........................................................................*/\nvoid SST_Task_ctor(\n    SST_Task * const me,\n    SST_Handler init,\n    SST_Handler dispatch)\n{\n    me->init = init;\n    me->dispatch = dispatch;\n}\n/*..........................................................................*/\nvoid SST_Task_start(\n    SST_Task * const me,\n    SST_TaskPrio prio,\n    SST_Evt const **qBuf, SST_QCtr qLen,\n    SST_Evt const * const ie)\n{\n    /*! @pre\n    * - the priority must be in range\n    * - the queue storage must be provided\n    * - the queue length must not be zero\n    * - the priority must not be in use\n    */\n    DBC_REQUIRE(200,\n        (0U < prio) && (prio <= SST_PORT_MAX_TASK)\n        && (qBuf != (SST_Evt const **)0) && (qLen > 0U)\n        && (task_registry[prio] == (SST_Task *)0));\n\n    me->prio  = prio;\n    me->qBuf  = qBuf;\n    me->end   = qLen - 1U;\n    me->head  = 0U;\n    me->tail  = 0U;\n    me->nUsed = 0U;\n\n    task_registry[prio] = me;\n\n    /* initialize this task with the initialization event */\n    (*me->init)(me, ie); /* NOTE: virtual call */\n    /* TBD: implement event recycling */\n}\n/*..........................................................................*/\nvoid SST_Task_post(SST_Task * const me, SST_Evt const * const e) {\n    /*! @pre the queue must be sized adequately and cannot overflow */\n    DBC_REQUIRE(300, me->nUsed <= me->end);\n\n    SST_PORT_CRIT_STAT\n    SST_PORT_CRIT_ENTRY();\n    me->qBuf[me->head] = e; /* insert event into the queue */\n    if (me->head == 0U) {   /* need to wrap the head? */\n        me->head = me->end; /* wrap around */\n    }\n    else {\n        --me->head;\n    }\n    ++me->nUsed;\n    task_readySet |= (1U << (me->prio - 1U));\n    SST_PORT_CRIT_EXIT();\n}\n\n/*--------------------------------------------------------------------------*/\nstatic SST_TimeEvt *timeEvt_head = (SST_TimeEvt *)0;\n\n/*..........................................................................*/\nvoid SST_TimeEvt_ctor(\n    SST_TimeEvt * const me,\n    SST_Signal sig,\n    SST_Task *task)\n{\n    me->super.sig = sig;\n    me->task = task;\n    me->ctr = 0U;\n    me->interval = 0U;\n\n    /* insert time event \"me\" into the linked-list */\n    me->next = timeEvt_head;\n    timeEvt_head = me;\n}\n/*..........................................................................*/\nvoid SST_TimeEvt_arm(\n    SST_TimeEvt * const me,\n    SST_TCtr ctr,\n    SST_TCtr interval)\n{\n    SST_PORT_CRIT_STAT\n    SST_PORT_CRIT_ENTRY();\n    me->ctr = ctr;\n    me->interval = interval;\n    SST_PORT_CRIT_EXIT();\n}\n/*..........................................................................*/\nbool SST_TimeEvt_disarm(SST_TimeEvt * const me) {\n    SST_PORT_CRIT_STAT\n    SST_PORT_CRIT_ENTRY();\n    bool status = (me->ctr != 0U);\n    me->ctr = 0U;\n    me->interval = 0U;\n    SST_PORT_CRIT_EXIT();\n    return status;\n}\n/*..........................................................................*/\nvoid SST_TimeEvt_tick(void) {\n    for (SST_TimeEvt *t = timeEvt_head;\n         t != (SST_TimeEvt *)0;\n         t = t->next)\n    {\n        SST_PORT_CRIT_STAT\n        SST_PORT_CRIT_ENTRY();\n        if (t->ctr == 0U) { /* disarmed? (most frequent case) */\n            SST_PORT_CRIT_EXIT();\n        }\n        else if (t->ctr == 1U) { /* expiring? */\n            t->ctr = t->interval;\n            SST_PORT_CRIT_EXIT();\n\n            SST_Task_post(t->task, &t->super);\n        }\n        else { /* timing out */\n            --t->ctr;\n            SST_PORT_CRIT_EXIT();\n        }\n    }\n}\n"
  },
  {
    "path": "sst0_cpp/README.txt",
    "content": "This directory contains the non-preemptive SST implementation in C++,\nreferred to as \"SST0/C++\".\n\n- \"basic tasks\" (non-blocking)\n- preemptive scheduling\n- multiple tasks per prioriy level\n- multiple \"activations\" per task (event queues)\n"
  },
  {
    "path": "sst0_cpp/examples/README.txt",
    "content": "This directory contains examples for the non-preemptive SST0/C++ kernel.\n"
  },
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    "content": "//============================================================================\n// Super-Simple Tasker (SST/C++) Example\n//\n// Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n//\n// SPDX-License-Identifier: MIT\n//\n// Permission is hereby granted, free of charge, to any person obtaining a\n// copy of this software and associated documentation files (the \"Software\"),\n// to deal in the Software without restriction, including without limitation\n// the rights to use, copy, modify, merge, publish, distribute, sublicense,\n// and/or sell copies of the Software, and to permit persons to whom the\n// Software is furnished to do so, subject to the following conditions:\n//\n// The above copyright notice and this permission notice shall be included in\n// all copies or substantial portions of the Software.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n// DEALINGS IN THE SOFTWARE.\n//============================================================================\n#include \"sst.hpp\"           // SST framework\n#include \"bsp.hpp\"           // Board Support Package interface\n#include \"blinky.hpp\"        // application shared interface\n\nnamespace {\n\nDBC_MODULE_NAME(\"blinky\")   // for DBC assertions in this module */\n\n} // unnamed namespace\n\nnamespace App {\n\n//............................................................................\nclass Blinky : public SST::Task {\n    SST::TimeEvt m_te1;\n    SST::TimeEvt m_te2;\n\npublic:\n    Blinky(void);\n    void init(SST::Evt const * const ie) override;\n    void dispatch(SST::Evt const * const e) override;\n    static Blinky inst;\n};\n\n//............................................................................\nBlinky Blinky::inst; // the Blinky instance\nSST::Task * const AO_Blinky = &Blinky::inst; // opaque AO pointer\n\n//............................................................................\nBlinky::Blinky(void)\n  : m_te1(TIMEOUT1_SIG, this),\n    m_te2(TIMEOUT2_SIG, this)\n{}\n//............................................................................\nvoid Blinky::init(SST::Evt const * const ie) {\n    static_cast<void>(ie); // unused parameter\n\n    m_te2.arm(1U, 0U);\n}\n//............................................................................\nvoid Blinky::dispatch(SST::Evt const * const e) {\n    switch (e->sig) {\n        case TIMEOUT1_SIG: {\n            BSP::ledOff();\n            m_te2.arm(BSP::TICKS_PER_SEC*3U/4U, 0U);\n            break;\n        }\n        case TIMEOUT2_SIG: {\n            BSP::ledOn();\n            m_te1.arm(BSP::TICKS_PER_SEC/4U, 0U);\n            break;\n        }\n        default: {\n            DBC_ERROR(500); // unexpected event\n            break;\n        }\n    }\n}\n\n} // namespace App\n"
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  {
    "path": "sst0_cpp/examples/blinky/blinky.hpp",
    "content": "//============================================================================\n// Super-Simple Tasker (SST/C++) Example\n//\n// Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n//\n// SPDX-License-Identifier: MIT\n//\n// Permission is hereby granted, free of charge, to any person obtaining a\n// copy of this software and associated documentation files (the \"Software\"),\n// to deal in the Software without restriction, including without limitation\n// the rights to use, copy, modify, merge, publish, distribute, sublicense,\n// and/or sell copies of the Software, and to permit persons to whom the\n// Software is furnished to do so, subject to the following conditions:\n//\n// The above copyright notice and this permission notice shall be included in\n// all copies or substantial portions of the Software.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n// DEALINGS IN THE SOFTWARE.\n//============================================================================\n#ifndef BLINKY_HPP_\n#define BLINKY_HPP_\n\n#include \"dbc_assert.h\" // Design By Contract (DBC) assertions\n\nnamespace App {\n\nenum Signals {\n    TIMEOUT1_SIG,\n    TIMEOUT2_SIG,\n    // ...\n    MAX_SIG  // the last signal\n};\n\nextern SST::Task * const AO_Blinky;  // opaque task pointer\n\n} // namespace App\n\n#endif // BLINKY_HPP_\n"
  },
  {
    "path": "sst0_cpp/examples/blinky/bsp.hpp",
    "content": "//============================================================================\n// Super-Simple Tasker (SST/C++) Example\n//\n// Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n//\n/// SPDX-License-Identifier: MIT\n//\n// Permission is hereby granted, free of charge, to any person obtaining a\n// copy of this software and associated documentation files (the \"Software\"),\n// to deal in the Software without restriction, including without limitation\n// the rights to use, copy, modify, merge, publish, distribute, sublicense,\n// and/or sell copies of the Software, and to permit persons to whom the\n// Software is furnished to do so, subject to the following conditions:\n//\n// The above copyright notice and this permission notice shall be included in\n// all copies or substantial portions of the Software.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n// DEALINGS IN THE SOFTWARE.\n//============================================================================\n#ifndef BSP_HPP_\n#define BSP_HPP_\n\nnamespace BSP {\n\nconstexpr std::uint32_t TICKS_PER_SEC = 1000U;\n\nvoid init(void);\n\nvoid ledOn(void);\nvoid ledOff(void);\n\n} // namespace BSP\n\n#endif // BSP_HPP_\n"
  },
  {
    "path": "sst0_cpp/examples/blinky/bsp_nucleo-l053r8.cpp",
    "content": "//============================================================================\n// Super-Simple Tasker (SST0/C++) Example for STM32 NUCLEO-L053R8\n//\n//                    Q u a n t u m  L e a P s\n//                    ------------------------\n//                    Modern Embedded Software\n//\n// Copyright (C) 2005 Quantum Leaps, <state-machine.com>.\n//\n// SPDX-License-Identifier: MIT\n//\n// Permission is hereby granted, free of charge, to any person obtaining a\n// copy of this software and associated documentation files (the \"Software\"),\n// to deal in the Software without restriction, including without limitation\n// the rights to use, copy, modify, merge, publish, distribute, sublicense,\n// and/or sell copies of the Software, and to permit persons to whom the\n// Software is furnished to do so, subject to the following conditions:\n//\n// The above copyright notice and this permission notice shall be included in\n// all copies or substantial portions of the Software.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n// DEALINGS IN THE SOFTWARE.\n//============================================================================\n#include \"sst.hpp\"           // SST framework\n#include \"bsp.hpp\"           // Board Support Package interface\n#include \"blinky.hpp\"        // application shared interface\n\n#include \"stm32l0xx.h\"  // CMSIS-compliant header file for the MCU used\n// add other drivers if necessary...\n\n// Local-scope defines -------------------------------------------------------\nnamespace {\n\n//DBC_MODULE_NAME(\"bsp_nucleo-l053r8\") // for DBC assertions in this module\n\n} // unnamed workspace\n\n// test pins on GPIO PA\n#define LED_PIN  5U\n\n// ISRs used in the application ==============================================\nextern \"C\" {\n\nvoid SysTick_Handler(void);  // prototype\nvoid SysTick_Handler(void) { // system clock tick ISR\n    SST::TimeEvt::tick();\n}\n\n// Assertion handler =========================================================\nvoid DBC_fault_handler(char const * const module, int const label) {\n    //\n    // NOTE: add here your application-specific error handling\n    //\n    (void)module;\n    (void)label;\n\n    // set PRIMASK to disable interrupts and stop SST right here\n    __asm volatile (\"cpsid i\");\n\n#ifndef NDEBUG\n    for (;;) { // keep blinking LED2\n        BSP::ledOn();  // turn LED2 on\n        uint32_t volatile ctr;\n        for (ctr = 10000U; ctr > 0U; --ctr) {\n        }\n        BSP::ledOff(); // turn LED2 off\n        for (ctr = 10000U; ctr > 0U; --ctr) {\n        }\n    }\n#endif\n    NVIC_SystemReset();\n}\n//............................................................................\nvoid assert_failed(char const * const module, int const label);// prototype\nvoid assert_failed(char const * const module, int const label) {\n    DBC_fault_handler(module, label);\n}\n\n} // extern \"C\"\n\nnamespace BSP {\n\n// BSP functions =============================================================\nvoid init(void) {\n    // Configure the MPU to prevent NULL-pointer dereferencing\n    // see: www.state-machine.com/null-pointer-protection-with-arm-cortex-m-mpu\n    //\n    MPU->RBAR = 0x0U                          // base address (NULL)\n                | MPU_RBAR_VALID_Msk          // valid region\n                | (MPU_RBAR_REGION_Msk & 7U); // region #7\n    MPU->RASR = (7U << MPU_RASR_SIZE_Pos)     // 2^(7+1) region\n                | (0x0U << MPU_RASR_AP_Pos)   // no-access region\n                | MPU_RASR_ENABLE_Msk;        // region enable\n\n    MPU->CTRL = MPU_CTRL_PRIVDEFENA_Msk       // enable background region\n                | MPU_CTRL_ENABLE_Msk;        // enable the MPU\n    __ISB();\n    __DSB();\n\n    // enable GPIO port PA clock\n    RCC->IOPENR |= (1U << 0U);\n\n    // set all used GPIOA pins as push-pull output, no pull-up, pull-down\n    GPIOA->MODER  &= ~(3U << 2U*LED_PIN);\n    GPIOA->MODER  |=  (1U << 2U*LED_PIN);\n    GPIOA->OTYPER &= ~(1U <<    LED_PIN);\n    GPIOA->PUPDR  &= ~(3U << 2U*LED_PIN);\n}\n//............................................................................\nvoid ledOn(void)  { GPIOA->BSRR = (1U << LED_PIN);         }\nvoid ledOff(void) { GPIOA->BSRR = (1U << (LED_PIN + 16U)); }\n\n} // namespace BSP\n\n// SST callbacks =============================================================\nnamespace SST {\n\nvoid onStart(void) {\n    SystemCoreClockUpdate();\n\n    // set up the SysTick timer to fire at BSP::TICKS_PER_SEC rate\n    SysTick_Config((SystemCoreClock / BSP::TICKS_PER_SEC) + 1U);\n\n    // set priorities of ISRs used in the system\n    NVIC_SetPriority(SysTick_IRQn, 0U);\n    // ...\n}\n//............................................................................\nvoid onIdleCond(void) { // NOTE: called with interrupts DISABLED\n#ifdef NDEBUG\n    // Put the CPU and peripherals to the low-power mode.\n    // you might need to customize the clock management for your application,\n    // see the datasheet for your particular Cortex-M MCU.\n    //\n    __WFI(); // Wait-For-Interrupt\n#endif\n    SST_PORT_INT_ENABLE(); // NOTE: enable interrupts for SS0\n}\n\n} // namespace SST\n\n"
  },
  {
    "path": "sst0_cpp/examples/blinky/gnu/nucleo-l053r8.mak",
    "content": "##############################################################################\n# Makefile for Super-Simple Tasker (SST/C++) on NUCLEO-L053R8, GNU-ARM\n# Last Updated for Version: 2.0.0\n# Date of the Last Update:  2023-01-22\n#\n#                    Q u a n t u m  L e a P s\n#                    ------------------------\n#                    Modern Embedded Software\n#\n# Copyright (C) 2005 Quantum Leaps, LLC. All rights reserved.\n#\n# SPDX-License-Identifier: MIT\n#\n# Permission is hereby granted, free of charge, to any person obtaining a copy\n# of this software and associated documentation files (the \"Software\"), to\n# deal in the Software without restriction, including without limitation the\n# rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n# sell copies of the Software, and to permit persons to whom the Software is\n# furnished to do so, subject to the following conditions:\n#\n# The above copyright notice and this permission notice shall be included in\n# all copies or substantial portions of the Software.\n#\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS\n# IN THE SOFTWARE.\n##############################################################################\n# examples of invoking this Makefile:\n# make -f nucleo-l053r8.mak\n# make -f nucleo-l053r8.mak clean\n#\n# NOTE:\n# To use this Makefile on Windows, you will need the GNU make utility, which\n# is included in the QTools collection for Windows, see:\n#    https://github.com/QuantumLeaps/qtools\n#\n\n#-----------------------------------------------------------------------------\n# project and target names\n#\nPROJECT := blinky\nTARGET  := nucleo-l053r8\n\n#-----------------------------------------------------------------------------\n# project directories\n#\nSST_DIR      := ../../..\nSST_PORT_DIR := $(SST_DIR)/ports/arm-cm\nCMSIS_DIR    := ../../../../3rd_party/CMSIS\nTARGET_DIR   := ../../../../3rd_party/$(TARGET)\n\n# list of all source directories used by this project\nVPATH = .. \\\n\t$(SST_DIR)/src \\\n\t$(SST_PORT_DIR) \\\n\t$(TARGET_DIR) \\\n\t$(TARGET_DIR)/gnu \\\n\n# list of all include directories needed by this project\nINCLUDES  = -I. \\\n\t-I$(SST_DIR)/../include \\\n\t-I$(SST_PORT_DIR) \\\n\t-I$(CMSIS_DIR)/Include \\\n\t-I$(TARGET_DIR)\n\n#-----------------------------------------------------------------------------\n# project files\n#\n\n# assembler source files\nASM_SRCS :=\n\n# C source files\nC_SRCS := \\\n\tsystem_stm32l0xx.c \\\n\tstartup_stm32l053xx.c\n\n# C++ source files\nCPP_SRCS := \\\n\tsst0.cpp \\\n\tmain.cpp \\\n\tblinky.cpp \\\n\tbsp_nucleo-l053r8.cpp\n\nLD_SCRIPT  := $(TARGET_DIR)/gnu/$(TARGET).ld\n\nOUTPUT    := $(PROJECT)\n\nLIB_DIRS  :=\nLIBS      :=\n\n# defines\nDEFINES   :=\n\n# ARM CPU, ARCH, FPU, and Float-ABI types...\n# ARM_CPU:   [cortex-m0 | cortex-m0plus | cortex-m1 | cortex-m3 | cortex-m4]\n# ARM_FPU:   [ | vfp]\n# FLOAT_ABI: [ | soft | softfp | hard]\n#\nARM_CPU   := -mcpu=cortex-m0plus\nARM_FPU   :=\nFLOAT_ABI :=\n\n#-----------------------------------------------------------------------------\n# GNU-ARM toolset (NOTE: You need to adjust to your machine)\n# see https://developer.arm.com/open-source/gnu-toolchain/gnu-rm/downloads\n#\nifeq ($(GNU_ARM),)\nGNU_ARM := $(QTOOLS)/gnu_arm-none-eabi\nendif\n\n# make sure that the GNU-ARM toolset exists...\nifeq (\"$(wildcard $(GNU_ARM))\",\"\")\n$(error GNU_ARM toolset not found. Please adjust the Makefile)\nendif\n\nCC    := $(GNU_ARM)/bin/arm-none-eabi-gcc\nCPP   := $(GNU_ARM)/bin/arm-none-eabi-g++\nAS    := $(GNU_ARM)/bin/arm-none-eabi-as\nLINK  := $(GNU_ARM)/bin/arm-none-eabi-g++\nBIN   := $(GNU_ARM)/bin/arm-none-eabi-objcopy\n\n##############################################################################\n# Typically you should not need to change anything below this line\n\n# basic utilities (included in QTools for Windows), see:\n#     https://www.state-machine.com/qtools\n\nMKDIR := mkdir\nRM    := rm\n\n#-----------------------------------------------------------------------------\n# build options\n#\n\n# combine all the soruces...\nC_SRCS += $(QP_SRCS)\nASM_SRCS += $(QP_ASMS)\n\nBIN_DIR := build_$(TARGET)\n\nASFLAGS = -g $(ARM_CPU) $(ARM_FPU) $(ASM_CPU) $(ASM_FPU)\n\nCFLAGS = -c -g $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -std=c99 -mthumb -Wall \\\n\t-ffunction-sections -fdata-sections \\\n\t-O $(INCLUDES) $(DEFINES)\n\nCPPFLAGS = -c -g $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -std=c++11 -mthumb -Wall \\\n\t-ffunction-sections -fdata-sections -fno-rtti -fno-exceptions \\\n\t-O $(INCLUDES) $(DEFINES)\n\nLINKFLAGS = -T$(LD_SCRIPT) $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -mthumb \\\n\t-specs=nosys.specs -specs=nano.specs \\\n\t-Wl,-Map,$(BIN_DIR)/$(OUTPUT).map,--cref,--gc-sections $(LIB_DIRS)\n\nASM_OBJS     := $(patsubst %.s,%.o,  $(notdir $(ASM_SRCS)))\nC_OBJS       := $(patsubst %.c,%.o,  $(notdir $(C_SRCS)))\nCPP_OBJS     := $(patsubst %.cpp,%.o,$(notdir $(CPP_SRCS)))\n\nTARGET_BIN   := $(BIN_DIR)/$(OUTPUT).bin\nTARGET_ELF   := $(BIN_DIR)/$(OUTPUT).elf\nASM_OBJS_EXT := $(addprefix $(BIN_DIR)/, $(ASM_OBJS))\nC_OBJS_EXT   := $(addprefix $(BIN_DIR)/, $(C_OBJS))\nC_DEPS_EXT   := $(patsubst %.o, %.d, $(C_OBJS_EXT))\nCPP_OBJS_EXT := $(addprefix $(BIN_DIR)/, $(CPP_OBJS))\nCPP_DEPS_EXT := $(patsubst %.o, %.d, $(CPP_OBJS_EXT))\n\n# create $(BIN_DIR) if it does not exist\nifeq (\"$(wildcard $(BIN_DIR))\",\"\")\n$(shell $(MKDIR) $(BIN_DIR))\nendif\n\n#-----------------------------------------------------------------------------\n# rules\n#\n\n.PHONY : run norun flash\n\nifeq ($(MAKECMDGOALS),norun)\nall : $(TARGET_BIN)\nnorun : all\nelse\nall : $(TARGET_BIN) run\nendif\n\n$(TARGET_BIN): $(TARGET_ELF)\n\t$(BIN) -O binary $< $@\n\n$(TARGET_ELF) : $(ASM_OBJS_EXT) $(C_OBJS_EXT) $(CPP_OBJS_EXT)\n\t$(LINK) $(LINKFLAGS) -o $@ $^ $(LIBS)\n\n$(BIN_DIR)/%.d : %.c\n\t$(CC) -MM -MT $(@:.d=.o) $(CFLAGS) $< > $@\n\n$(BIN_DIR)/%.d : %.cpp\n\t$(CPP) -MM -MT $(@:.d=.o) $(CPPFLAGS) $< > $@\n\n$(BIN_DIR)/%.o : %.s\n\t$(AS) $(ASFLAGS) $< -o $@\n\n$(BIN_DIR)/%.o : %.c\n\t$(CC) $(CFLAGS) $< -o $@\n\n$(BIN_DIR)/%.o : %.cpp\n\t$(CPP) $(CPPFLAGS) $< -o $@\n\n.PHONY : clean show\n\n# include dependency files only if our goal depends on their existence\nifneq ($(MAKECMDGOALS),clean)\n  ifneq ($(MAKECMDGOALS),show)\n-include $(C_DEPS_EXT) $(CPP_DEPS_EXT)\n  endif\nendif\n\n\nclean :\n\t-$(RM) $(BIN_DIR)/*.o \\\n\t$(BIN_DIR)/*.d \\\n\t$(BIN_DIR)/*.bin \\\n\t$(BIN_DIR)/*.elf \\\n\t$(BIN_DIR)/*.map\n\t\nshow:\n\t@echo PROJECT = $(PROJECT)\n\t@echo CONF = $(CONF)\n\t@echo DEFINES = $(DEFINES)\n\t@echo ASM_FPU = $(ASM_FPU)\n\t@echo ASM_SRCS = $(ASM_SRCS)\n\t@echo C_SRCS = $(C_SRCS)\n\t@echo CPP_SRCS = $(CPP_SRCS)\n\t@echo ASM_OBJS_EXT = $(ASM_OBJS_EXT)\n\t@echo C_OBJS_EXT = $(C_OBJS_EXT)\n\t@echo C_DEPS_EXT = $(C_DEPS_EXT)\n\t@echo CPP_DEPS_EXT = $(CPP_DEPS_EXT)\n\t@echo TARGET_ELF = $(TARGET_ELF)\n"
  },
  {
    "path": "sst0_cpp/examples/blinky/iar/nucleo-l053r8.ewd",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<project>\n    <fileVersion>3</fileVersion>\n    <configuration>\n        <name>Debug</name>\n        <toolchain>\n            <name>ARM</name>\n        </toolchain>\n        <debug>1</debug>\n        <settings>\n            <name>C-SPY</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>32</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CInput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CEndian</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCVariant</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>MemOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MemFile</name>\n                    <state>$TOOLKIT_DIR$\\CONFIG\\debugger\\ST\\STM32L053R8.ddf</state>\n                </option>\n                <option>\n                    <name>RunToEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RunToName</name>\n                    <state>main</state>\n                </option>\n                <option>\n                    <name>CExtraOptionsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCDDFArgumentProducer</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCDownloadSuppressDownload</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCDownloadVerifyAll</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProductVersion</name>\n                    <state>9.10.2.39304</state>\n                </option>\n                <option>\n                    <name>OCDynDriverList</name>\n                    <state>STLINK_ID</state>\n                </option>\n                <option>\n                    <name>OCLastSavedByProductVersion</name>\n                    <state>9.32.1.54977</state>\n                </option>\n                <option>\n                    <name>UseFlashLoader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CLowLevel</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCBE8Slave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacFile2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CDevice</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>FlashLoadersV3</name>\n                    <state>$TOOLKIT_DIR$/config/flashloader/ST/FlashSTM32L0xxx8.board</state>\n                </option>\n                <option>\n                    <name>OCImagesSuppressCheck1</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesPath1</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCImagesSuppressCheck2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesPath2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCImagesSuppressCheck3</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesPath3</name>\n                    <state></state>\n                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       <option>\n                    <name>OCDeviceConfigMacroFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCDebuggerExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCAllMTBOptions</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCMulticoreNrOfCores</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCMulticoreWorkspace</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCMulticoreSlaveProject</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCMulticoreSlaveConfiguration</name>\n                    <state></state>\n       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          <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CCadiMemory</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>Fast Model</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCADILogFileCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCADILogFileEditB</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CMSISDAP_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>4</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCIarProbeScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CMSISDAPResetList</name>\n                    <version>1</version>\n                    <state>10</state>\n                </option>\n                <option>\n                    <name>CMSISDAPHWResetDuration</name>\n                    <state>300</state>\n                </option>\n                <option>\n                    <name>CMSISDAPHWResetDelay</name>\n                    <state>200</state>\n                </option>\n                <option>\n                    <name>CMSISDAPDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CMSISDAPInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CMSISDAPInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiTargetEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPJtagSpeedList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPRestoreBreakpointsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPUpdateBreakpointsEdit</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>RDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchUndef</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchData</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchPrefetch</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchMMERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchNOCPERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchCHKERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSTATERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchBUSERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchINTERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSFERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchHARDERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiCPUEnable</name>\n     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<name>OCJetEmuParams</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCCMSISDAPUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCCMSISDAPUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>GDBSERVER_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>TCPIP</name>\n                    <state>aaa.bbb.ccc.ddd</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCJTagBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJTagDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJTagUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>IJET_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>9</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCIarProbeScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetResetList</name>\n                    <version>1</version>\n                    <state>10</state>\n                </option>\n                <option>\n                    <name>IjetHWResetDuration</name>\n                    <state>300</state>\n                </option>\n                <option>\n                    <name>IjetHWResetDelay</name>\n                    <state>200</state>\n                </option>\n                <option>\n                    <name>IjetPowerFromProbe</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetPowerRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>IjetInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiTargetEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetScanChainNonARMDevices</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetIRLength</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetJtagSpeedList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetProtocolRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetSwoPin</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IjetSwoPrescalerList</name>\n                    <version>1</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetRestoreBreakpointsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetUpdateBreakpointsEdit</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>RDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchUndef</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchData</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchPrefetch</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchMMERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchNOCPERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchCHKERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSTATERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchBUSERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchINTERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSFERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchHARDERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeCfgOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeConfig</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IjetProbeConfigRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiCPUEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiCPUNumber</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetSelectedCPUBehaviour</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ICpuName</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCJetEmuParams</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetPreferETB</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetTraceSettingsList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetTraceSizeList</name>\n                    <version>0</version>\n                    <state>4</state>\n                </option>\n                <option>\n                    <name>FlashBoardPathSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCIjetUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCIjetUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL3S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL3S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL3S</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>JLINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>16</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>JLinkSpeed</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCJLinkDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCJLinkHWResetDelay</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>JLinkInitialSpeed</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCDoJlinkMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCScanChainNonARMDevices</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkIRLength</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkCommRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkTCPIP</name>\n                    <state>aaa.bbb.ccc.ddd</state>\n                </option>\n                <option>\n                    <name>CCJLinkSpeedRadioV2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCUSBDevice</name>\n                    <version>1</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCRDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchUndef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchData</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchPrefetch</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCJLinkInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJLinkResetList</name>\n                    <version>6</version>\n                    <state>5</state>\n                </option>\n                <option>\n                    <name>CCJLinkInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJLinkUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCTcpIpAlt</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkTcpIpSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSwoClockAuto</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSwoClockEdit</name>\n                    <state>2000</state>\n                </option>\n                <option>\n                    <name>OCJLinkTraceSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkTraceSourceDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkDeviceName</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>LMIFTDI_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>3</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>LmiftdiSpeed</name>\n                    <state>500</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCLmiFtdiInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCLmiFtdiInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCLmiftdiUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiResetList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>NULINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>PEMICRO_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>3</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJPEMicroShowSettings</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>STLINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>8</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSTLinkInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSTLinkInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkResetList</name>\n                    <version>3</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSwoClockAuto</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSwoClockEdit</name>\n                    <state>2000</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCSTLinkDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSTLinkUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkJtagSpeedList</name>\n                    <version>2</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkDAPNumber</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSTLinkDebugAccessPortRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUseServerSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkProbeList</name>\n                    <version>1</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkTargetVccEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    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    </option>\n            </data>\n        </settings>\n        <settings>\n            <name>TIFET_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>1</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCMSPFetResetList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetInterfaceRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    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<name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>TIPackageOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TIPackage</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>BoardFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCXds100BreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100DoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100UpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchUndef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchData</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchPrefetch</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchSTATERR</name>\n                    <state>0</state>\n                </option>\n  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 </option>\n                <option>\n                    <name>CCXds100SwoClockEdit</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCXds100HWResetDelay</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100ResetList</name>\n                    <version>1</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100UsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCXds100UsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100JtagSpeedList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100InterfaceRadio</name>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCXds100InterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100ProbeList</name>\n                    <version>0</version>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>CCXds100SWOPortRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100SWOPort</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCXDSTargetVccEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXDSTargetVoltage</name>\n                    <state>###Uninitialized###</state>\n                </option>\n                <option>\n                    <name>OCXDSDigitalStatesConfigFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCSelectedCoreName</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <debuggerPlugins>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\CMX\\CmxArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\CMX\\CmxTinyArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\embOS\\embOSPlugin.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\FreeRtos\\FreeRtosArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\Mbed\\MbedArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\Mbed\\MbedArmPlugin2.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\OpenRTOS\\OpenRTOSPlugin.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\SafeRTOS\\SafeRTOSPlugin.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\SMX\\smxAwareIarArm9.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\SMX\\smxAwareIarArm9BE.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\ThreadX\\ThreadXArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\uCOS-II\\uCOS-II-286-KA-CSpy.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\uCOS-II\\uCOS-II-KA-CSpy.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\uCOS-III\\uCOS-III-KA-CSpy.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                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  },
  {
    "path": "sst0_cpp/examples/blinky/iar/nucleo-l053r8.ewp",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<project>\n    <fileVersion>3</fileVersion>\n    <configuration>\n        <name>Debug</name>\n        <toolchain>\n            <name>ARM</name>\n        </toolchain>\n        <debug>1</debug>\n        <settings>\n            <name>General</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <version>35</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>BrowseInfoPath</name>\n                    <state>build_nucleo-l053r8</state>\n                </option>\n                <option>\n                    <name>ExePath</name>\n                    <state>build_nucleo-l053r8</state>\n                </option>\n                <option>\n                    <name>ObjPath</name>\n                    <state>build_nucleo-l053r8</state>\n                </option>\n                <option>\n                    <name>ListPath</name>\n                    <state>build_nucleo-l053r8</state>\n                </option>\n                <option>\n                    <name>GEndianMode</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>Input description</name>\n                    <state>No specifier n, no float nor long long, no scan set, no assignment suppressing, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>Output description</name>\n                    <state>No specifier a, A, no specifier n, no float nor long long, no flags, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>GOutputBinary</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGCoreOrChip</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelect</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelectSlave</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RTDescription</name>\n                    <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\n                </option>\n                <option>\n                    <name>OGProductVersion</name>\n                    <state>5.11.0.50579</state>\n                </option>\n                <option>\n                    <name>OGLastSavedByProductVersion</name>\n                    <state>9.32.1.54977</state>\n                </option>\n                <option>\n                    <name>OGChipSelectEditMenu</name>\n                    <state>STM32L053R8\tST STM32L053R8</state>\n                </option>\n                <option>\n                    <name>GenLowLevelInterface</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GEndianModeBE</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OGBufferedTerminalOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GenStdoutInterface</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RTConfigPath2</name>\n                    <state>$TOOLKIT_DIR$\\inc\\c\\DLib_Config_Normal.h</state>\n                </option>\n                <option>\n                    <name>GBECoreSlave</name>\n                    <version>32</version>\n                    <state>35</state>\n                </option>\n                <option>\n                    <name>OGUseCmsis</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGUseCmsisDspLib</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibThreads</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CoreVariant</name>\n                    <version>32</version>\n                    <state>35</state>\n                </option>\n                <option>\n                    <name>GFPUDeviceSlave</name>\n                    <state>STM32L053R8\tST STM32L053R8</state>\n                </option>\n                <option>\n                    <name>FPU2</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>NrRegs</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>NEON</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GFPUCoreSlave2</name>\n                    <version>32</version>\n                    <state>35</state>\n                </option>\n                <option>\n                    <name>OGCMSISPackSelectDevice</name>\n                </option>\n                <option>\n                    <name>OgLibHeap</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGLibAdditionalLocale</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGPrintfVariant</name>\n                    <version>0</version>\n                    <state>4</state>\n                </option>\n                <option>\n                    <name>OGPrintfMultibyteSupport</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGScanfVariant</name>\n                    <version>0</version>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>OGScanfMultibyteSupport</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GenLocaleTags</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>GenLocaleDisplayOnly</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DSPExtension</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TrustZone</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TrustZoneModes</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGAarch64Abi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OG_32_64Device</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>BuildFilesPath</name>\n                    <state>Debug</state>\n                </option>\n                <option>\n                    <name>PointerAuthentication</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>FPU64</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>ICCARM</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>37</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CCOptimizationNoSizeConstraints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCDefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCPreprocFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPreprocComments</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPreprocLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCMnemonics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCMessages</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListAssFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListAssSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEnableRemarks</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCDiagSuppress</name>\n                    <state>Pa050</state>\n                </option>\n                <option>\n                    <name>CCDiagRemark</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagWarning</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagError</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCObjPrefix</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCAllowList</name>\n                    <version>1</version>\n                    <state>10010100</state>\n                </option>\n                <option>\n                    <name>CCDebugInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IEndianMode</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IExtraOptionsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n      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<option>\n                    <name>CCLibConfigHeader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>PreInclude</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCIncludePath2</name>\n                    <state>$PROJ_DIR$\\..</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\include</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\ports\\arm-cm</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\CMSIS\\Include</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\nucleo-l053r8</state>\n                </option>\n                <option>\n                    <name>CCStdIncCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCodeSection</name>\n                    <state>.text</state>\n      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<state>0</state>\n                </option>\n                <option>\n                    <name>IccLang</name>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>IccCDialect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccAllowVLA</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccStaticDestr</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccCppInlineSemantics</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccCmsis</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccFloatSemantics</name>\n                    <state>0</state>\n            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<state>0</state>\n                </option>\n                <option>\n                    <name>IccExceptions2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccRTTI2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OICompilerExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCStackProtection</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>AARM</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>11</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>AObjPrefix</name>\n                    <state>1</state>\n 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<state>blinky.bin</state>\n                </option>\n                <option>\n                    <name>OOCCommandLineProducer</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OOCObjCopyEnable</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CUSTOM</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <extensions></extensions>\n                <cmdline></cmdline>\n                <hasPrio>1</hasPrio>\n                <buildSequence>inputOutputBased</buildSequence>\n            </data>\n        </settings>\n        <settings>\n            <name>BUILDACTION</name>\n            <archiveVersion>1</archiveVersion>\n            <data>\n                <prebuild></prebuild>\n                <postbuild></postbuild>\n            </data>\n        </settings>\n        <settings>\n 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             </option>\n                <option>\n                    <name>IlinkWrapperFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkFpuProcessor</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>IARCHIVE</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>IarchiveInputs</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IarchiveOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IarchiveOutput</name>\n                    <state>###Unitialized###</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>Coder</name>\n            <archiveVersion>0</archiveVersion>\n            <data />\n        </settings>\n    </configuration>\n    <mfc>\n        <configuration>Debug</configuration>\n    </mfc>\n    <group>\n        <name>Application</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\blinky.cpp</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\blinky.hpp</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\bsp.hpp</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\bsp_nucleo-l053r8.cpp</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\main.cpp</name>\n        </file>\n    </group>\n    <group>\n        <name>nucleo-l053r8</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\nucleo-l053r8\\iar\\startup_stm32l053xx.s</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\nucleo-l053r8\\stm32l053xx.h</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\nucleo-l053r8\\system_stm32l0xx.c</name>\n        </file>\n    </group>\n    <group>\n        <name>sst</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\src\\sst0.cpp</name>\n        </file>\n    </group>\n    <group>\n        <name>sst_port</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\ports\\arm-cm\\sst_port.hpp</name>\n        </file>\n    </group>\n</project>\n"
  },
  {
    "path": "sst0_cpp/examples/blinky/iar/nucleo-l053r8.eww",
    "content": "<?xml version=\"1.0\" encoding=\"iso-8859-1\"?>\n\n<workspace>\n  <project>\n    <path>$WS_DIR$\\nucleo-l053r8.ewp</path>\n  </project>\n  <batchBuild/>\n</workspace>\n\n\n"
  },
  {
    "path": "sst0_cpp/examples/blinky/main.cpp",
    "content": "//============================================================================\n// Super-Simple Tasker (SST0/C++) Example\n//\n// Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n//\n// SPDX-License-Identifier: MIT\n//\n// Permission is hereby granted, free of charge, to any person obtaining a\n// copy of this software and associated documentation files (the \"Software\"),\n// to deal in the Software without restriction, including without limitation\n// the rights to use, copy, modify, merge, publish, distribute, sublicense,\n// and/or sell copies of the Software, and to permit persons to whom the\n// Software is furnished to do so, subject to the following conditions:\n//\n// The above copyright notice and this permission notice shall be included in\n// all copies or substantial portions of the Software.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n// DEALINGS IN THE SOFTWARE.\n//============================================================================\n#include \"sst.hpp\"           // SST framework\n#include \"bsp.hpp\"           // Board Support Package interface\n#include \"blinky.hpp\"        // application shared interface\n\n//............................................................................\nint main() {\n    SST::init(); // initialize the SST kernel\n    BSP::init(); // initialize the Board Support Package\n\n    // instantiate and start all SST tasks...\n    static SST::Evt const *blinkyQSto[10]; // Event queue storage\n    App::AO_Blinky->start(\n        1U,           // SST-priority\n        blinkyQSto,   // storage for the AO's queue\n        ARRAY_NELEM(blinkyQSto), // queue length\n        nullptr);     // initialization event (not used)\n\n    return SST::Task::run(); // run the SST tasks\n    // NOTE: in embedded systems SST::Task::run() should not return\n}\n\n"
  },
  {
    "path": "sst0_cpp/examples/blinky_button/armclang/ek-tm4c123gxl.uvoptx",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\" standalone=\"no\" ?>\n<ProjectOpt xmlns:xsi=\"http://www.w3.org/2001/XMLSchema-instance\" xsi:noNamespaceSchemaLocation=\"project_optx.xsd\">\n\n  <SchemaVersion>1.0</SchemaVersion>\n\n  <Header>### uVision Project, (C) Keil Software</Header>\n\n  <Extensions>\n    <cExt>*.c</cExt>\n    <aExt>*.s*; *.src; *.a*</aExt>\n    <oExt>*.obj; *.o</oExt>\n    <lExt>*.lib</lExt>\n    <tExt>*.txt; *.h; *.inc; *.md</tExt>\n    <pExt>*.plm</pExt>\n    <CppX>*.cpp</CppX>\n    <nMigrate>0</nMigrate>\n  </Extensions>\n\n  <DaveTm>\n    <dwLowDateTime>0</dwLowDateTime>\n    <dwHighDateTime>0</dwHighDateTime>\n  </DaveTm>\n\n  <Target>\n    <TargetName>ek-tm4c123gxl</TargetName>\n    <ToolsetNumber>0x4</ToolsetNumber>\n    <ToolsetName>ARM-ADS</ToolsetName>\n    <TargetOption>\n      <CLKADS>12000000</CLKADS>\n      <OPTTT>\n        <gFlags>1</gFlags>\n        <BeepAtEnd>1</BeepAtEnd>\n        <RunSim>1</RunSim>\n        <RunTarget>0</RunTarget>\n        <RunAbUc>0</RunAbUc>\n      </OPTTT>\n      <OPTHX>\n        <HexSelection>1</HexSelection>\n        <FlashByte>65535</FlashByte>\n        <HexRangeLowAddress>0</HexRangeLowAddress>\n        <HexRangeHighAddress>0</HexRangeHighAddress>\n        <HexOffset>0</HexOffset>\n      </OPTHX>\n      <OPTLEX>\n        <PageWidth>79</PageWidth>\n        <PageLength>66</PageLength>\n        <TabStop>8</TabStop>\n        <ListingPath>.\\build_ek-tm4c123gxl\\</ListingPath>\n      </OPTLEX>\n      <ListingPage>\n        <CreateCListing>1</CreateCListing>\n        <CreateAListing>1</CreateAListing>\n        <CreateLListing>1</CreateLListing>\n        <CreateIListing>0</CreateIListing>\n        <AsmCond>1</AsmCond>\n        <AsmSymb>1</AsmSymb>\n        <AsmXref>0</AsmXref>\n        <CCond>1</CCond>\n        <CCode>0</CCode>\n        <CListInc>0</CListInc>\n        <CSymb>0</CSymb>\n        <LinkerCodeListing>0</LinkerCodeListing>\n      </ListingPage>\n      <OPTXL>\n        <LMap>1</LMap>\n        <LComments>1</LComments>\n        <LGenerateSymbols>1</LGenerateSymbols>\n        <LLibSym>1</LLibSym>\n        <LLines>1</LLines>\n        <LLocSym>1</LLocSym>\n        <LPubSym>1</LPubSym>\n        <LXref>0</LXref>\n        <LExpSel>0</LExpSel>\n      </OPTXL>\n      <OPTFL>\n        <tvExp>1</tvExp>\n        <tvExpOptDlg>0</tvExpOptDlg>\n        <IsCurrentTarget>1</IsCurrentTarget>\n      </OPTFL>\n      <CpuCode>4</CpuCode>\n      <DebugOpt>\n        <uSim>0</uSim>\n        <uTrg>1</uTrg>\n        <sLdApp>1</sLdApp>\n        <sGomain>1</sGomain>\n        <sRbreak>1</sRbreak>\n        <sRwatch>1</sRwatch>\n        <sRmem>1</sRmem>\n        <sRfunc>1</sRfunc>\n        <sRbox>1</sRbox>\n        <tLdApp>1</tLdApp>\n        <tGomain>1</tGomain>\n        <tRbreak>1</tRbreak>\n        <tRwatch>1</tRwatch>\n        <tRmem>1</tRmem>\n        <tRfunc>0</tRfunc>\n        <tRbox>1</tRbox>\n        <tRtrace>0</tRtrace>\n        <sRSysVw>1</sRSysVw>\n        <tRSysVw>1</tRSysVw>\n        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    "path": "sst0_cpp/examples/blinky_button/blinky1.cpp",
    "content": "//============================================================================\n// Super-Simple Tasker (SST0/C++) Example\n//\n// Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n//\n// SPDX-License-Identifier: MIT\n//\n// Permission is hereby granted, free of charge, to any person obtaining a\n// copy of this software and associated documentation files (the \"Software\"),\n// to deal in the Software without restriction, including without limitation\n// the rights to use, copy, modify, merge, publish, distribute, sublicense,\n// and/or sell copies of the Software, and to permit persons to whom the\n// Software is furnished to do so, subject to the following conditions:\n//\n// The above copyright notice and this permission notice shall be included in\n// all copies or substantial portions of the Software.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n// DEALINGS IN THE SOFTWARE.\n//============================================================================\n#include \"sst.hpp\"           // SST framework\n#include \"bsp.hpp\"           // Board Support Package interface\n#include \"blinky_button.hpp\" // application shared interface\n\nnamespace {\n\nDBC_MODULE_NAME(\"blinky1\")   // for DBC assertions in this module */\n\n} // unnamed namespace\n\nnamespace App {\n\n//............................................................................\nclass Blinky1 : public SST::Task {\n    SST::TimeEvt m_te;\n    std::uint16_t m_toggles;\n\npublic:\n    Blinky1(void);\n    void init(SST::Evt const * const ie) override;\n    void dispatch(SST::Evt const * const e) override;\n    static Blinky1 inst;\n};\n\n//............................................................................\nBlinky1 Blinky1::inst; // the Blinky1 instance\nSST::Task * const AO_Blinky1 = &Blinky1::inst; // opaque AO pointer\n\n//............................................................................\nBlinky1::Blinky1(void)\n  : m_te(TIMEOUT_SIG, this)\n{}\n//............................................................................\nvoid Blinky1::init(SST::Evt const * const ie) {\n    /* the initial event must be provided and must be WORKLOAD_SIG */\n    DBC_REQUIRE(300,\n        (ie != nullptr) && (ie->sig == BLINKY_WORK_SIG));\n\n    m_te.arm(\n        SST::evt_downcast<BlinkyWorkEvt>(ie)->ticks,\n        SST::evt_downcast<BlinkyWorkEvt>(ie)->ticks);\n    m_toggles = SST::evt_downcast<BlinkyWorkEvt>(ie)->toggles;\n}\n//............................................................................\nvoid Blinky1::dispatch(SST::Evt const * const e) {\n    switch (e->sig) {\n        case TIMEOUT_SIG: {\n            for (std::uint16_t i = m_toggles; i > 0U; --i) {\n                // SST scheduler lock is not needed in non-preemptive SST0\n                //SST::LockKey key = lock(3U);\n                BSP::d5on();\n                BSP::d5off();\n                //unlock(key);\n            }\n            break;\n        }\n        case BLINKY_WORK_SIG: {\n            BSP::d5on();\n            m_te.arm(\n                SST::evt_downcast<BlinkyWorkEvt>(e)->ticks,\n                SST::evt_downcast<BlinkyWorkEvt>(e)->ticks);\n            m_toggles = SST::evt_downcast<BlinkyWorkEvt>(e)->toggles;\n            BSP::d5off();\n            break;\n        }\n        default: {\n            DBC_ERROR(500); // unexpected event\n            break;\n        }\n    }\n}\n\n} // namespace App\n"
  },
  {
    "path": "sst0_cpp/examples/blinky_button/blinky3.cpp",
    "content": "//============================================================================\n// Super-Simple Tasker (SST/C++) Example\n//\n// Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n//\n// SPDX-License-Identifier: MIT\n//\n// Permission is hereby granted, free of charge, to any person obtaining a\n// copy of this software and associated documentation files (the \"Software\"),\n// to deal in the Software without restriction, including without limitation\n// the rights to use, copy, modify, merge, publish, distribute, sublicense,\n// and/or sell copies of the Software, and to permit persons to whom the\n// Software is furnished to do so, subject to the following conditions:\n//\n// The above copyright notice and this permission notice shall be included in\n// all copies or substantial portions of the Software.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n// DEALINGS IN THE SOFTWARE.\n//============================================================================\n#include \"sst.hpp\"           // SST framework\n#include \"bsp.hpp\"           // Board Support Package interface\n#include \"blinky_button.hpp\" // application shared interface\n\nnamespace {\n\nDBC_MODULE_NAME(\"blinky3\")   // for DBC assertions in this module\n\n} // unnamed namespace\n\nnamespace App {\n\n//............................................................................\nclass Blinky3 : public SST::Task {\n    SST::TimeEvt m_te;\n    std::uint16_t m_toggles;\n\npublic:\n    Blinky3(void);\n    void init(SST::Evt const * const ie) override;\n    void dispatch(SST::Evt const * const e) override;\n    static Blinky3 inst;\n};\n\n//............................................................................\nBlinky3 Blinky3::inst; // the Blinky3 instance\nSST::Task * const AO_Blinky3 = &Blinky3::inst; // opaque AO pointer\n\n//............................................................................\nBlinky3::Blinky3(void)\n  : m_te(TIMEOUT_SIG, this)\n{}\n//............................................................................\nvoid Blinky3::init(SST::Evt const * const ie) {\n    // the initial event must be provided and must be WORKLOAD_SIG\n    DBC_REQUIRE(300,\n        (ie != nullptr) && (ie->sig == BLINKY_WORK_SIG));\n\n    m_te.arm(\n        SST::evt_downcast<BlinkyWorkEvt>(ie)->ticks,\n        SST::evt_downcast<BlinkyWorkEvt>(ie)->ticks);\n    m_toggles = SST::evt_downcast<BlinkyWorkEvt>(ie)->toggles;\n}\n//............................................................................\nvoid Blinky3::dispatch(SST::Evt const * const e) {\n    switch (e->sig) {\n        case TIMEOUT_SIG: {\n            for (std::uint16_t i = m_toggles; i > 0U; --i) {\n                BSP::d2on();\n                BSP::d2off();\n            }\n            break;\n        }\n        case BLINKY_WORK_SIG: {\n            BSP::d2on();\n            m_te.arm(\n                SST::evt_downcast<BlinkyWorkEvt>(e)->ticks,\n                SST::evt_downcast<BlinkyWorkEvt>(e)->ticks);\n            m_toggles = SST::evt_downcast<BlinkyWorkEvt>(e)->toggles;\n            BSP::d2off();\n            break;\n        }\n        default: {\n            DBC_ERROR(500); // unexpected event\n            break;\n        }\n    }\n}\n\n} // namespace App\n"
  },
  {
    "path": "sst0_cpp/examples/blinky_button/blinky_button.hpp",
    "content": "//============================================================================\n// Super-Simple Tasker (SST/C++) Example\n//\n// Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n//\n// SPDX-License-Identifier: MIT\n//\n// Permission is hereby granted, free of charge, to any person obtaining a\n// copy of this software and associated documentation files (the \"Software\"),\n// to deal in the Software without restriction, including without limitation\n// the rights to use, copy, modify, merge, publish, distribute, sublicense,\n// and/or sell copies of the Software, and to permit persons to whom the\n// Software is furnished to do so, subject to the following conditions:\n//\n// The above copyright notice and this permission notice shall be included in\n// all copies or substantial portions of the Software.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n// DEALINGS IN THE SOFTWARE.\n//============================================================================\n#ifndef BLINKY_BUTTON_HPP_\n#define BLINKY_BUTTON_HPP_\n\n#include \"dbc_assert.h\" // Design By Contract (DBC) assertions\n\nnamespace App {\n\nenum Signals {\n    TIMEOUT_SIG,\n    BUTTON_PRESSED_SIG,\n    BUTTON_RELEASED_SIG,\n    BLINKY_WORK_SIG,\n    FORWARD_PRESSED_SIG,\n    FORWARD_RELEASED_SIG,\n    // ...\n    MAX_SIG  // the last signal\n};\n\n// event with parameters\nstruct BlinkyWorkEvt {\n    SST::Evt super;\n    std::uint16_t toggles; // number of toggles of the signal\n    std::uint8_t ticks;    // number of clock ticks between\n};\n\n// event with parameters\nstruct ButtonWorkEvt {\n    SST::Evt super;\n    std::uint16_t toggles; // number of toggles of the signal\n};\n\nextern SST::Task * const AO_Blinky1;  // opaque task pointer\nextern SST::Task * const AO_Blinky3;  // opaque task pointer\nextern SST::Task * const AO_Button2a; // opaque task pointer\nextern SST::Task * const AO_Button2b; // opaque task pointer\n\n} // namespace App\n\n#endif // BLINKY_BUTTON_HPP_\n"
  },
  {
    "path": "sst0_cpp/examples/blinky_button/bsp.hpp",
    "content": "//============================================================================\n// Super-Simple Tasker (SST/C++) Example\n//\n// Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n//\n/// SPDX-License-Identifier: MIT\n//\n// Permission is hereby granted, free of charge, to any person obtaining a\n// copy of this software and associated documentation files (the \"Software\"),\n// to deal in the Software without restriction, including without limitation\n// the rights to use, copy, modify, merge, publish, distribute, sublicense,\n// and/or sell copies of the Software, and to permit persons to whom the\n// Software is furnished to do so, subject to the following conditions:\n//\n// The above copyright notice and this permission notice shall be included in\n// all copies or substantial portions of the Software.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n// DEALINGS IN THE SOFTWARE.\n//============================================================================\n#ifndef BSP_HPP_\n#define BSP_HPP_\n\nnamespace BSP {\n\nconstexpr std::uint32_t TICKS_PER_SEC = 1000U;\n\nvoid init(void);\n\nvoid d1on(void);\nvoid d1off(void);\n\nvoid d2on(void);\nvoid d2off(void);\n\nvoid d3on(void);\nvoid d3off(void);\n\nvoid d4on(void);\nvoid d4off(void);\n\nvoid d5on(void);\nvoid d5off(void);\n\nvoid d6on(void);\nvoid d6off(void);\n\n// immutable events for Blinky tasks\nSST::Evt const *getWorkEvtBlinky1(std::uint8_t num);\nSST::Evt const *getWorkEvtBlinky3(std::uint8_t num);\n\n} // namespace BSP\n\n#endif // BSP_HPP_\n"
  },
  {
    "path": "sst0_cpp/examples/blinky_button/bsp_ek-tm4c123gxl.cpp",
    "content": "//============================================================================\n// Super-Simple Tasker (SST0/C++) Example for TivaC TM4C123GXL\n//\n//                    Q u a n t u m  L e a P s\n//                    ------------------------\n//                    Modern Embedded Software\n//\n// Copyright (C) 2005 Quantum Leaps, <state-machine.com>.\n//\n// SPDX-License-Identifier: MIT\n//\n// Permission is hereby granted, free of charge, to any person obtaining a\n// copy of this software and associated documentation files (the \"Software\"),\n// to deal in the Software without restriction, including without limitation\n// the rights to use, copy, modify, merge, publish, distribute, sublicense,\n// and/or sell copies of the Software, and to permit persons to whom the\n// Software is furnished to do so, subject to the following conditions:\n//\n// The above copyright notice and this permission notice shall be included in\n// all copies or substantial portions of the Software.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n// DEALINGS IN THE SOFTWARE.\n//============================================================================\n#include \"sst.hpp\"           // SST framework\n#include \"bsp.hpp\"           // Board Support Package interface\n#include \"blinky_button.hpp\" // application shared interface\n\n#include \"TM4C123GH6PM.h\"    // the device specific header (TI)\n#include <cmath>             // to exercise the FPU\n// add other drivers if necessary...\n\n// Local-scope defines -------------------------------------------------------\nnamespace {\n\nDBC_MODULE_NAME(\"bsp_ek-tm4c123gxl\") // for DBC assertions in this module\n\n} // unnamed workspace\n\n/* test pins on GPIOF */\n#define TST1_PIN  (1U << 1U) /* LED Red */\n#define TST2_PIN  (1U << 2U) /* LED Blue */\n\n/* test pins on GPIOD */\n#define TST3_PIN  (1U << 0U)\n#define TST4_PIN  (1U << 1U)\n#define TST5_PIN  (1U << 2U)\n\n/* test pins on GPIOF */\n#define TST6_PIN  (1U << 3U) /* LED Green */\n\n/* Button on the board on GPIOF */\n#define BTN_SW1      (1U << 4)\n\n// ISRs used in the application ==============================================\nextern \"C\" {\n\nvoid SysTick_Handler(void) {   // system clock tick ISR\n    BSP::d1on();\n\n    SST::TimeEvt::tick();\n\n    // get state of the user button\n    // Perform the debouncing of buttons. The algorithm for debouncing\n    // adapted from the book \"Embedded Systems Dictionary\" by Jack Ganssle\n    // and Michael Barr, page 71.\n    //\n    static struct ButtonsDebouncing {\n        uint32_t depressed;\n        uint32_t previous;\n    } buttons = { 0U, 0U };\n    uint32_t current = ~GPIOF_AHB->DATA_Bits[BTN_SW1];\n    uint32_t tmp = buttons.depressed; // save the debounced depressed\n    buttons.depressed |= (buttons.previous & current); // set depressed\n    buttons.depressed &= (buttons.previous | current); // clear released\n    buttons.previous   = current; // update the history\n    tmp ^= buttons.depressed;     // changed debounced depressed\n    if ((tmp & BTN_SW1) != 0U) {  /* debounced SW1 state changed? */\n        if ((buttons.depressed & BTN_SW1) != 0U) { /* is SW1 depressed? */\n            // immutable button-press event\n            static App::ButtonWorkEvt const pressEvt = {\n                { App::BUTTON_PRESSED_SIG }, 60U\n            };\n            // immutable forward-press event\n            static App::ButtonWorkEvt const fPressEvt = {\n                { App::FORWARD_PRESSED_SIG }, 60U\n            };\n            App::AO_Button2a->post(&fPressEvt.super);\n            App::AO_Button2a->post(&pressEvt.super);\n        }\n        else { // B1 is released\n            // immutable button-release event\n            static App::ButtonWorkEvt const releaseEvt = {\n                { App::BUTTON_RELEASED_SIG }, 80U\n            };\n            // immutable forward-release event\n            static App::ButtonWorkEvt const fReleaseEvt = {\n                { App::FORWARD_RELEASED_SIG }, 80U\n            };\n            App::AO_Button2a->post(&fReleaseEvt.super);\n            App::AO_Button2a->post(&releaseEvt.super);\n        }\n    }\n\n    BSP::d1off();\n}\n\n// Assertion handler =========================================================\nvoid DBC_fault_handler(char const * const module, int const label) {\n    //\n    // NOTE: add here your application-specific error handling\n    //\n    (void)module;\n    (void)label;\n\n    // set PRIMASK to disable interrupts and stop SST right here\n    __asm volatile (\"cpsid i\");\n\n#ifndef NDEBUG\n    for (;;) { // keep blinking LED2\n        BSP::d6on();  // turn LED2 on\n        uint32_t volatile ctr;\n        for (ctr = 1000000U; ctr > 0U; --ctr) {\n        }\n        BSP::d6off(); // turn LED2 off\n        for (ctr = 1000000U; ctr > 0U; --ctr) {\n        }\n    }\n#endif\n    NVIC_SystemReset();\n}\n//............................................................................\nvoid assert_failed(char const * const module, int const label);// prototype\nvoid assert_failed(char const * const module, int const label) {\n    DBC_fault_handler(module, label);\n}\n\n} // extern \"C\"\n\nnamespace BSP {\n\n// BSP functions =============================================================\nvoid init(void) {\n    // Configure the MPU to prevent NULL-pointer dereferencing\n    // see: www.state-machine.com/null-pointer-protection-with-arm-cortex-m-mpu\n    //\n    MPU->RBAR = 0x0U                          // base address (NULL)\n                | MPU_RBAR_VALID_Msk          // valid region\n                | (MPU_RBAR_REGION_Msk & 7U); // region #7\n    MPU->RASR = (7U << MPU_RASR_SIZE_Pos)     // 2^(7+1) region\n                | (0x0U << MPU_RASR_AP_Pos)   // no-access region\n                | MPU_RASR_ENABLE_Msk;        // region enable\n\n    MPU->CTRL = MPU_CTRL_PRIVDEFENA_Msk       // enable background region\n                | MPU_CTRL_ENABLE_Msk;        // enable the MPU\n    __ISB();\n    __DSB();\n\n\n    SYSCTL->RCGCGPIO  |= (1U << 5U); /* enable Run mode for GPIOF */\n    SYSCTL->RCGCGPIO  |= (1U << 3U); /* enable Run mode for GPIOD */\n    __ISB();\n    __DSB();\n\n    SYSCTL->GPIOHBCTL |= (1U << 5); /* enable AHB for GPIOF */\n    SYSCTL->GPIOHBCTL |= (1U << 3); /* enable AHB for GPIOD */\n    __ISB();\n    __DSB();\n\n    /* configure test pins on GPIOF (digital output) */\n    GPIOF_AHB->DIR |= (TST1_PIN | TST2_PIN | TST6_PIN);\n    GPIOF_AHB->DEN |= (TST1_PIN | TST2_PIN | TST6_PIN);\n\n    /* configure button on GPIOF (digital input) */\n    GPIOF_AHB->DIR &= ~(BTN_SW1); /* input */\n    GPIOF_AHB->DEN |= (BTN_SW1); /* digital enable */\n    GPIOF_AHB->PUR |= (BTN_SW1); /* pull-up resistor enable */\n\n    /* configure test pins on GPIOD (digital output) */\n    GPIOD_AHB->DIR |= (TST3_PIN | TST4_PIN | TST5_PIN);\n    GPIOD_AHB->DEN |= (TST3_PIN | TST4_PIN | TST5_PIN);\n}\n\n//............................................................................\n#if defined __ARMCC_VERSION\n#elif defined __GNUC__\nstd::uint32_t __errno; // GNU-ARM needs this to link sqrtf()\n#endif\n\nstatic void exerciseFPU(float x) {\n    // exercise the single-precision FPU by calculating the identity:\n    //  sqrt(x) == x / sqrt(x) for x > 0\n    //\n    float tmp1 = sqrtf(x); // single-precision sqrt()\n    float tmp2 = x / tmp1;\n    DBC_ENSURE(200, (tmp1 - 1e-4f <= tmp2) && (tmp2 <= tmp1 + 1e-4f));\n}\n\n//............................................................................\nvoid d1on(void) { // LED-Red */\n    GPIOF_AHB->DATA_Bits[TST1_PIN] = 0xFFU;\n    // don't use the FPU in the ISR\n}\nvoid d1off(void) {\n    GPIOF_AHB->DATA_Bits[TST1_PIN] = 0x00U;\n}\n//............................................................................\nvoid d2on(void) { /* LED-Blue */\n    GPIOF_AHB->DATA_Bits[TST2_PIN] = 0xFFU;\n    exerciseFPU(1.2345f);\n}\nvoid d2off(void) {\n    GPIOF_AHB->DATA_Bits[TST2_PIN] = 0x00U;\n}\n//............................................................................\nvoid d3on(void) {\n    GPIOD_AHB->DATA_Bits[TST3_PIN] = 0xFFU;\n    exerciseFPU(0.345f);\n}\nvoid d3off(void) {\n    GPIOD_AHB->DATA_Bits[TST3_PIN] = 0x00U;\n}\n//............................................................................\nvoid d4on(void) {\n    GPIOD_AHB->DATA_Bits[TST4_PIN] = 0xFFU;\n    exerciseFPU(0.456f);\n}\nvoid d4off(void) {\n    GPIOD_AHB->DATA_Bits[TST4_PIN] = 0x00U;\n}\n//............................................................................\nvoid d5on(void) {\n    GPIOD_AHB->DATA_Bits[TST5_PIN] = 0xFFU;\n    exerciseFPU(1.567f);\n}\nvoid d5off(void) {\n    GPIOD_AHB->DATA_Bits[TST5_PIN] = 0x00U;\n}\n//............................................................................\nvoid d6on(void) {  /* LED2-Green */\n    GPIOF_AHB->DATA_Bits[TST6_PIN] = 0xFFU;\n    exerciseFPU(1.2345f);\n}\nvoid d6off(void) {\n    GPIOF_AHB->DATA_Bits[TST6_PIN] = 0x00U;\n}\n\n//............................................................................\nSST::Evt const *getWorkEvtBlinky1(uint8_t num) {\n    // immutable work events for Blinky1\n    static App::BlinkyWorkEvt const workBlinky1[] = {\n        { { App::BLINKY_WORK_SIG }, 40U, 5U },\n        { { App::BLINKY_WORK_SIG }, 30U, 7U }\n    };\n    DBC_REQUIRE(500, num < ARRAY_NELEM(workBlinky1)); // num must be in range\n    return &workBlinky1[num].super;\n}\n//............................................................................\nSST::Evt const *getWorkEvtBlinky3(uint8_t num) {\n    // immutable work events for Blinky3\n    static App::BlinkyWorkEvt const workBlinky3[] = {\n        { { App::BLINKY_WORK_SIG }, 20U, 5U },\n        { { App::BLINKY_WORK_SIG }, 10U, 3U   }\n    };\n    DBC_REQUIRE(600, num < ARRAY_NELEM(workBlinky3)); // num must be in range\n    return &workBlinky3[num].super;\n}\n\n} // namespace BSP\n\n// SST callbacks =============================================================\nnamespace SST {\n\nvoid onStart(void) {\n    SystemCoreClockUpdate();\n\n    // set up the SysTick timer to fire at BSP::TICKS_PER_SEC rate\n    SysTick_Config((SystemCoreClock / BSP::TICKS_PER_SEC) + 1U);\n\n    // set priorities of ISRs used in the system\n    NVIC_SetPriority(SysTick_IRQn, 0U);\n    // ...\n}\n//............................................................................\nvoid onIdleCond(void) { // NOTE: called with interrupts DISABLED\n    BSP::d6on();  // turn LED-Green on\n#ifdef NDEBUG\n    // Put the CPU and peripherals to the low-power mode.\n    // you might need to customize the clock management for your application,\n    // see the datasheet for your particular Cortex-M MCU.\n    //\n    BSP::d6off(); // turn LED-Green off\n    __WFI(); // Wait-For-Interrupt\n    BSP::d6on();  // turn LED-Green on\n#else\n#endif\n    BSP::d6off(); // turn LED-Green off\n    SST_PORT_INT_ENABLE(); // NOTE: enable interrupts for SS0\n}\n\n} // namespace SST\n"
  },
  {
    "path": "sst0_cpp/examples/blinky_button/bsp_nucleo-c031c6.cpp",
    "content": "//============================================================================\n// Super-Simple Tasker (SST0/C++) Example for STM32 NUCLEO-C031C6\n//\n//\n//                    Q u a n t u m  L e a P s\n//                    ------------------------\n//                    Modern Embedded Software\n//\n// Copyright (C) 2005 Quantum Leaps, <state-machine.com>.\n//\n// SPDX-License-Identifier: MIT\n//\n// Permission is hereby granted, free of charge, to any person obtaining a\n// copy of this software and associated documentation files (the \"Software\"),\n// to deal in the Software without restriction, including without limitation\n// the rights to use, copy, modify, merge, publish, distribute, sublicense,\n// and/or sell copies of the Software, and to permit persons to whom the\n// Software is furnished to do so, subject to the following conditions:\n//\n// The above copyright notice and this permission notice shall be included in\n// all copies or substantial portions of the Software.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n// DEALINGS IN THE SOFTWARE.\n//============================================================================\n#include \"sst.hpp\"           // SST framework\n#include \"bsp.hpp\"           // Board Support Package interface\n#include \"blinky_button.hpp\" // application shared interface\n\n#include \"stm32c0xx.h\"  // CMSIS-compliant header file for the MCU used\n// add other drivers if necessary...\n\n// Local-scope defines -------------------------------------------------------\nnamespace {\n\nDBC_MODULE_NAME(\"bsp_nucleo-c031c6\") // for DBC assertions in this module\n\n} // unnamed workspace\n\n// test pins on GPIO PA\n#define TST1_PIN  7U\n#define TST2_PIN  6U\n#define TST3_PIN  4U\n#define TST4_PIN  1U\n#define TST5_PIN  0U\n#define TST6_PIN  5U /* LED L4-Green */\n\n// buttons on GPIO PC\n#define B1_PIN    13U\n\n// ISRs used in the application ==============================================\nextern \"C\" {\n\nvoid SysTick_Handler(void);  // prototype\nvoid SysTick_Handler(void) { // system clock tick ISR\n    BSP::d1on();\n\n    SST::TimeEvt::tick();\n\n    // get state of the user button\n    // Perform the debouncing of buttons. The algorithm for debouncing\n    // adapted from the book \"Embedded Systems Dictionary\" by Jack Ganssle\n    // and Michael Barr, page 71.\n    //\n    static struct ButtonsDebouncing {\n        uint32_t depressed;\n        uint32_t previous;\n    } buttons = { 0U, 0U };\n    uint32_t current = ~GPIOC->IDR; // read GPIO PortC\n    uint32_t tmp = buttons.depressed; // save the debounced depressed\n    buttons.depressed |= (buttons.previous & current); // set depressed\n    buttons.depressed &= (buttons.previous | current); // clear released\n    buttons.previous   = current; // update the history\n    tmp ^= buttons.depressed;     // changed debounced depressed\n    if ((tmp & (1U << B1_PIN)) != 0U) { // debounced B1 state changed?\n        if ((buttons.depressed & (1U << B1_PIN)) != 0U) { // depressed?\n            // immutable button-press event\n            static App::ButtonWorkEvt const pressEvt = {\n                { App::BUTTON_PRESSED_SIG }, 60U\n            };\n            // immutable forward-press event\n            static App::ButtonWorkEvt const fPressEvt = {\n                { App::FORWARD_PRESSED_SIG }, 60U\n            };\n            App::AO_Button2a->post(&fPressEvt.super);\n            App::AO_Button2a->post(&pressEvt.super);\n        }\n        else { // B1 is released\n            // immutable button-release event\n            static App::ButtonWorkEvt const releaseEvt = {\n                { App::BUTTON_RELEASED_SIG }, 80U\n            };\n            // immutable forward-release event\n            static App::ButtonWorkEvt const fReleaseEvt = {\n                { App::FORWARD_RELEASED_SIG }, 80U\n            };\n            App::AO_Button2a->post(&fReleaseEvt.super);\n            App::AO_Button2a->post(&releaseEvt.super);\n        }\n    }\n\n    BSP::d1off();\n}\n\n// Assertion handler =========================================================\nvoid DBC_fault_handler(char const * const module, int const label) {\n    //\n    // NOTE: add here your application-specific error handling\n    //\n    (void)module;\n    (void)label;\n\n    // set PRIMASK to disable interrupts and stop SST right here\n    __asm volatile (\"cpsid i\");\n\n#ifndef NDEBUG\n    for (;;) { // keep blinking LED2\n        BSP::d6on();  // turn LED2 on\n        uint32_t volatile ctr;\n        for (ctr = 10000U; ctr > 0U; --ctr) {\n        }\n        BSP::d6off(); // turn LED2 off\n        for (ctr = 10000U; ctr > 0U; --ctr) {\n        }\n    }\n#endif\n    NVIC_SystemReset();\n}\n//............................................................................\nvoid assert_failed(char const * const module, int const label);// prototype\nvoid assert_failed(char const * const module, int const label) {\n    DBC_fault_handler(module, label);\n}\n\n} // extern \"C\"\n\nnamespace BSP {\n\n// BSP functions =============================================================\nvoid init(void) {\n    // Configure the MPU to prevent NULL-pointer dereferencing\n    // see: www.state-machine.com/null-pointer-protection-with-arm-cortex-m-mpu\n    //\n    MPU->RBAR = 0x0U                          // base address (NULL)\n                | MPU_RBAR_VALID_Msk          // valid region\n                | (MPU_RBAR_REGION_Msk & 7U); // region #7\n    MPU->RASR = (7U << MPU_RASR_SIZE_Pos)     // 2^(7+1) region\n                | (0x0U << MPU_RASR_AP_Pos)   // no-access region\n                | MPU_RASR_ENABLE_Msk;        // region enable\n\n    MPU->CTRL = MPU_CTRL_PRIVDEFENA_Msk       // enable background region\n                | MPU_CTRL_ENABLE_Msk;        // enable the MPU\n    __ISB();\n    __DSB();\n\n    // enable GPIO port PA clock\n    RCC->IOPENR |= (1U << 0U);\n\n    // set all used GPIOA pins as push-pull output, no pull-up, pull-down\n    GPIOA->MODER &=\n        ~((3U << 2U*TST1_PIN) | (3U << 2U*TST2_PIN) | (3U << 2U*TST3_PIN) |\n          (3U << 2U*TST4_PIN) | (3U << 2U*TST5_PIN) | (3U << 2U*TST6_PIN));\n    GPIOA->MODER |=\n         ((1U << 2U*TST1_PIN) | (1U << 2U*TST2_PIN) | (1U << 2U*TST3_PIN) |\n          (1U << 2U*TST4_PIN) | (1U << 2U*TST5_PIN) | (1U << 2U*TST6_PIN));\n    GPIOA->OTYPER &=\n        ~((1U <<    TST1_PIN) | (1U <<    TST2_PIN) | (1U <<    TST3_PIN) |\n          (1U <<    TST4_PIN) | (1U <<    TST5_PIN) | (1U <<    TST6_PIN));\n    GPIOA->OSPEEDR &=\n        ~((3U << 2U*TST1_PIN) | (3U << 2U*TST2_PIN) | (3U << 2U*TST3_PIN) |\n          (3U << 2U*TST4_PIN) | (3U << 2U*TST5_PIN) | (3U << 2U*TST6_PIN));\n    GPIOA->OSPEEDR |=\n         ((1U << 2U*TST1_PIN) | (1U << 2U*TST2_PIN) | (1U << 2U*TST3_PIN) |\n          (1U << 2U*TST4_PIN) | (1U << 2U*TST5_PIN) | (1U << 2U*TST6_PIN));\n   GPIOA->PUPDR &=\n        ~((3U << 2U*TST1_PIN) | (3U << 2U*TST2_PIN) | (3U << 2U*TST3_PIN) |\n          (3U << 2U*TST4_PIN) | (3U << 2U*TST5_PIN) | (3U << 2U*TST6_PIN));\n\n    // enable GPIOC clock port for the Button B1\n    RCC->IOPENR |=  (1U << 2U);\n\n    // configure Button B1 pin on GPIOC as input, no pull-up, pull-down\n    GPIOC->MODER &= ~(3U << 2U*B1_PIN);\n    GPIOC->PUPDR &= ~(3U << 2U*B1_PIN);\n}\n//............................................................................\nvoid d1on(void)  { GPIOA->BSRR = (1U << TST1_PIN);         }\nvoid d1off(void) { GPIOA->BSRR = (1U << (TST1_PIN + 16U)); }\n//............................................................................\nvoid d2on(void)  { GPIOA->BSRR = (1U << TST2_PIN);         }\nvoid d2off(void) { GPIOA->BSRR = (1U << (TST2_PIN + 16U)); }\n//............................................................................\nvoid d3on(void)  { GPIOA->BSRR = (1U << TST3_PIN);         }\nvoid d3off(void) { GPIOA->BSRR = (1U << (TST3_PIN + 16U)); }\n//............................................................................\nvoid d4on(void)  { GPIOA->BSRR = (1U << TST4_PIN);         }\nvoid d4off(void) { GPIOA->BSRR = (1U << (TST4_PIN + 16U)); }\n//............................................................................\nvoid d5on(void)  { GPIOA->BSRR = (1U << TST5_PIN);         }\nvoid d5off(void) { GPIOA->BSRR = (1U << (TST5_PIN + 16U)); }\n//............................................................................\nvoid d6on(void)  { GPIOA->BSRR = (1U << TST6_PIN);         } // LD4\nvoid d6off(void) { GPIOA->BSRR = (1U << (TST6_PIN + 16U)); }\n\n//............................................................................\nSST::Evt const *getWorkEvtBlinky1(uint8_t num) {\n    // immutable work events for Blinky1\n    static App::BlinkyWorkEvt const workBlinky1[] = {\n        { { App::BLINKY_WORK_SIG }, 40U, 5U },\n        { { App::BLINKY_WORK_SIG }, 30U, 7U }\n    };\n    DBC_REQUIRE(500, num < ARRAY_NELEM(workBlinky1)); // num must be in range\n    return &workBlinky1[num].super;\n}\n//............................................................................\nSST::Evt const *getWorkEvtBlinky3(uint8_t num) {\n    // immutable work events for Blinky3\n    static App::BlinkyWorkEvt const workBlinky3[] = {\n        { { App::BLINKY_WORK_SIG }, 20U, 5U },\n        { { App::BLINKY_WORK_SIG }, 10U, 3U   }\n    };\n    DBC_REQUIRE(600, num < ARRAY_NELEM(workBlinky3)); // num must be in range\n    return &workBlinky3[num].super;\n}\n\n} // namespace BSP\n\n// SST callbacks =============================================================\nnamespace SST {\n\nvoid onStart(void) {\n    SystemCoreClockUpdate();\n\n    // set up the SysTick timer to fire at BSP::TICKS_PER_SEC rate\n    SysTick_Config((SystemCoreClock / BSP::TICKS_PER_SEC) + 1U);\n\n    // set priorities of ISRs used in the system\n    NVIC_SetPriority(SysTick_IRQn, 0U);\n    // ...\n}\n//............................................................................\nvoid onIdleCond(void) { // NOTE: called with interrupts DISABLED\n    BSP::d6on();  // turn LED2 on\n#ifdef NDEBUG\n    // Put the CPU and peripherals to the low-power mode.\n    // you might need to customize the clock management for your application,\n    // see the datasheet for your particular Cortex-M MCU.\n    //\n    BSP::d6off(); // turn LED2 off\n    __WFI(); // Wait-For-Interrupt\n    BSP::d6on();  // turn LED2 on\n#endif\n    BSP::d6off(); // turn LED2 off\n    SST_PORT_INT_ENABLE(); // NOTE: enable interrupts for SS0\n}\n\n} // namespace SST\n\n"
  },
  {
    "path": "sst0_cpp/examples/blinky_button/bsp_nucleo-h743zi.cpp",
    "content": "//============================================================================\n// Super-Simple Tasker (SST0/C++) Example for STM32 NUCLEO-H74cZI\n//\n//\n//                    Q u a n t u m  L e a P s\n//                    ------------------------\n//                    Modern Embedded Software\n//\n// Copyright (C) 2005 Quantum Leaps, <state-machine.com>.\n//\n// SPDX-License-Identifier: MIT\n//\n// Permission is hereby granted, free of charge, to any person obtaining a\n// copy of this software and associated documentation files (the \"Software\"),\n// to deal in the Software without restriction, including without limitation\n// the rights to use, copy, modify, merge, publish, distribute, sublicense,\n// and/or sell copies of the Software, and to permit persons to whom the\n// Software is furnished to do so, subject to the following conditions:\n//\n// The above copyright notice and this permission notice shall be included in\n// all copies or substantial portions of the Software.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n// DEALINGS IN THE SOFTWARE.\n//============================================================================\n#include \"sst.hpp\"           // SST framework\n#include \"bsp.hpp\"           // Board Support Package interface\n#include \"blinky_button.hpp\" // application shared interface\n\n#include \"stm32h743xx.h\"  // CMSIS-compliant header file for the MCU used\n#include <cmath>          // to exercise the FPU\n// add other drivers if necessary...\n\n// Local-scope defines -------------------------------------------------------\nnamespace {\n\nDBC_MODULE_NAME(\"bsp_nucleo-h743zi\") // for DBC assertions in this module\n\n} // unnamed workspace\n\n// test pins on GPIO PB\n#define TST1_PIN  0U  /* PB.0  LED1-Green */\n#define TST2_PIN  14U /* PB.14 LED3-Red   */\n#define TST3_PIN  4U\n#define TST4_PIN  5U\n#define TST5_PIN  6U\n#define TST6_PIN  7U  /* PB.7  LED2-Blue  */\n\n// buttons on GPIO PC\n#define B1_PIN    13U\n\n// ISRs used in the application ==============================================\nextern \"C\" {\n\nvoid SysTick_Handler(void) {   // system clock tick ISR\n    BSP::d1on();\n\n    SST::TimeEvt::tick();\n\n    // get state of the user button\n    // Perform the debouncing of buttons. The algorithm for debouncing\n    // adapted from the book \"Embedded Systems Dictionary\" by Jack Ganssle\n    // and Michael Barr, page 71.\n    //\n    static struct ButtonsDebouncing {\n        uint32_t depressed;\n        uint32_t previous;\n    } buttons = { 0U, 0U };\n    uint32_t current = GPIOC->IDR; // read GPIO PortC\n    uint32_t tmp = buttons.depressed; // save the debounced depressed\n    buttons.depressed |= (buttons.previous & current); // set depressed\n    buttons.depressed &= (buttons.previous | current); // clear released\n    buttons.previous   = current; // update the history\n    tmp ^= buttons.depressed;     // changed debounced depressed\n    if ((tmp & (1U << B1_PIN)) != 0U) { // debounced B1 state changed?\n        if ((buttons.depressed & (1U << B1_PIN)) != 0U) { // depressed?\n            // immutable button-press event\n            static App::ButtonWorkEvt const pressEvt = {\n                { App::BUTTON_PRESSED_SIG }, 60U\n            };\n            // immutable forward-press event\n            static App::ButtonWorkEvt const fPressEvt = {\n                { App::FORWARD_PRESSED_SIG }, 60U\n            };\n            App::AO_Button2a->post(&fPressEvt.super);\n            App::AO_Button2a->post(&pressEvt.super);\n        }\n        else { // B1 is released\n            // immutable button-release event\n            static App::ButtonWorkEvt const releaseEvt = {\n                { App::BUTTON_RELEASED_SIG }, 80U\n            };\n            // immutable forward-release event\n            static App::ButtonWorkEvt const fReleaseEvt = {\n                { App::FORWARD_RELEASED_SIG }, 80U\n            };\n            App::AO_Button2a->post(&fReleaseEvt.super);\n            App::AO_Button2a->post(&releaseEvt.super);\n        }\n    }\n\n    BSP::d1off();\n}\n\n// Assertion handler =========================================================\nvoid DBC_fault_handler(char const * const module, int const label) {\n    //\n    // NOTE: add here your application-specific error handling\n    //\n    (void)module;\n    (void)label;\n\n    // set PRIMASK to disable interrupts and stop SST right here\n    __asm volatile (\"cpsid i\");\n\n#ifndef NDEBUG\n    for (;;) { // keep blinking LED2\n        BSP::d6on();  // turn LED2 on\n        uint32_t volatile ctr;\n        for (ctr = 1000000U; ctr > 0U; --ctr) {\n        }\n        BSP::d6off(); // turn LED2 off\n        for (ctr = 1000000U; ctr > 0U; --ctr) {\n        }\n    }\n#endif\n    NVIC_SystemReset();\n}\n//............................................................................\nvoid assert_failed(char const * const module, int const label);// prototype\nvoid assert_failed(char const * const module, int const label) {\n    DBC_fault_handler(module, label);\n}\n\n} // extern \"C\"\n\nnamespace BSP {\n\n// BSP functions =============================================================\nvoid init(void) {\n    // Configure the MPU to prevent NULL-pointer dereferencing\n    // see: www.state-machine.com/null-pointer-protection-with-arm-cortex-m-mpu\n    //\n    MPU->RBAR = 0x0U                          // base address (NULL)\n                | MPU_RBAR_VALID_Msk          // valid region\n                | (MPU_RBAR_REGION_Msk & 7U); // region #7\n    MPU->RASR = (7U << MPU_RASR_SIZE_Pos)     // 2^(7+1) region\n                | (0x0U << MPU_RASR_AP_Pos)   // no-access region\n                | MPU_RASR_ENABLE_Msk;        // region enable\n\n    MPU->CTRL = MPU_CTRL_PRIVDEFENA_Msk       // enable background region\n                | MPU_CTRL_ENABLE_Msk;        // enable the MPU\n    __ISB();\n    __DSB();\n\n    SCB_EnableICache(); // Enable I-Cache\n    SCB_EnableDCache(); // Enable D-Cache\n\n    // enable GPIOB port clock for LEds and test pins\n    RCC->AHB4ENR |= RCC_AHB4ENR_GPIOBEN;\n\n    // set all used GPIOB pins as push-pull output, no pull-up, pull-down\n    GPIOB->MODER &=\n        ~((3U << 2U*TST1_PIN) | (3U << 2U*TST2_PIN) | (3U << 2U*TST3_PIN) |\n          (3U << 2U*TST4_PIN) | (3U << 2U*TST5_PIN) | (3U << 2U*TST6_PIN));\n    GPIOB->MODER |=\n         ((1U << 2U*TST1_PIN) | (1U << 2U*TST2_PIN) | (1U << 2U*TST3_PIN) |\n          (1U << 2U*TST4_PIN) | (1U << 2U*TST5_PIN) | (1U << 2U*TST6_PIN));\n    GPIOB->OTYPER &=\n        ~((1U <<    TST1_PIN) | (1U <<    TST2_PIN) | (1U <<    TST3_PIN) |\n          (1U <<    TST4_PIN) | (1U <<    TST5_PIN) | (1U <<    TST6_PIN));\n    GPIOB->PUPDR &=\n        ~((3U << 2U*TST1_PIN) | (3U << 2U*TST2_PIN) | (3U << 2U*TST3_PIN) |\n          (3U << 2U*TST4_PIN) | (3U << 2U*TST5_PIN) | (3U << 2U*TST6_PIN));\n\n    // enable GPIOC clock port for the Button B1\n    RCC->AHB4ENR |= RCC_AHB4ENR_GPIOCEN;\n\n    // configure Button B1 pin on GPIOC as input, no pull-up, pull-down\n    GPIOC->MODER &= ~(3U << 2U*B1_PIN);\n    GPIOC->PUPDR &= ~(GPIO_PUPDR_PUPD0 << 2U*B1_PIN);\n    GPIOC->PUPDR |=  (2U << 2U*B1_PIN);\n}\n\n//............................................................................\nstatic void exerciseFPU(double x) {\n    // exercise the double-precision FPU by calculating the identity:\n    //  sin(x)^2 + cos(x)^2 == 1.0 for any x\n    //\n    double tmp = pow(sin(x), 2.0) + pow(cos(x), 2.0);\n    DBC_ENSURE(200, ((1.0 - 1e-4) < tmp) && (tmp < (1.0 + 1e-4)));\n}\n\n//............................................................................\nvoid d1on(void) {  // LED1-Green\n    GPIOB->BSRR = (1U << TST1_PIN);\n    // don't use the FPU in the ISR\n}\nvoid d1off(void) {\n    GPIOB->BSRR = (1U << (TST1_PIN + 16U));\n}\n//............................................................................\nvoid d2on(void) {  // LED3-Red\n    GPIOB->BSRR = (1U << TST2_PIN);\n    exerciseFPU(-1.2345);\n}\nvoid d2off(void) {\n    GPIOB->BSRR = (1U << (TST2_PIN + 16U));\n}\n//............................................................................\nvoid d3on(void) {\n    GPIOB->BSRR = (1U << TST3_PIN);\n    exerciseFPU(-12.345);\n}\nvoid d3off(void) {\n    GPIOB->BSRR = (1U << (TST3_PIN + 16U));\n}\n//............................................................................\nvoid d4on(void) {\n    GPIOB->BSRR = (1U << TST4_PIN);\n    exerciseFPU(3.456);\n}\nvoid d4off(void) {\n    GPIOB->BSRR = (1U << (TST4_PIN + 16U));\n}\n//............................................................................\nvoid d5on(void) {\n    GPIOB->BSRR = (1U << TST5_PIN);\n    exerciseFPU(4.567);\n}\nvoid d5off(void) {\n    GPIOB->BSRR = (1U << (TST5_PIN + 16U));\n}\n//............................................................................\nvoid d6on(void) {  // LED2-Blue\n    GPIOB->BSRR = (1U << TST6_PIN);\n    exerciseFPU(1.2345);\n}\nvoid d6off(void) {\n    GPIOB->BSRR = (1U << (TST6_PIN + 16U));\n}\n\n//............................................................................\nSST::Evt const *getWorkEvtBlinky1(uint8_t num) {\n    // immutable work events for Blinky1\n    static App::BlinkyWorkEvt const workBlinky1[] = {\n        { { App::BLINKY_WORK_SIG }, 40U, 5U },\n        { { App::BLINKY_WORK_SIG }, 30U, 7U }\n    };\n    DBC_REQUIRE(500, num < ARRAY_NELEM(workBlinky1)); // num must be in range\n    return &workBlinky1[num].super;\n}\n//............................................................................\nSST::Evt const *getWorkEvtBlinky3(uint8_t num) {\n    // immutable work events for Blinky3\n    static App::BlinkyWorkEvt const workBlinky3[] = {\n        { { App::BLINKY_WORK_SIG }, 20U, 5U },\n        { { App::BLINKY_WORK_SIG }, 10U, 3U   }\n    };\n    DBC_REQUIRE(600, num < ARRAY_NELEM(workBlinky3)); // num must be in range\n    return &workBlinky3[num].super;\n}\n\n} // namespace BSP\n\n// SST callbacks =============================================================\nnamespace SST {\n\nvoid onStart(void) {\n    SystemCoreClockUpdate();\n\n    // set up the SysTick timer to fire at BSP::TICKS_PER_SEC rate\n    SysTick_Config((SystemCoreClock / BSP::TICKS_PER_SEC) + 1U);\n\n    // set priorities of ISRs used in the system\n    NVIC_SetPriority(SysTick_IRQn, 0U);\n    // ...\n}\n//............................................................................\nvoid onIdleCond(void) { // NOTE: called with interrupts DISABLED\n    BSP::d6on();  // turn LED2 on\n#ifdef NDEBUG\n    // Put the CPU and peripherals to the low-power mode.\n    // you might need to customize the clock management for your application,\n    // see the datasheet for your particular Cortex-M MCU.\n    //\n    BSP::d6off(); // turn LED2 off\n    __WFI(); // Wait-For-Interrupt\n    BSP::d6on();  // turn LED2 on\n#endif\n    BSP::d6off(); // turn LED2 off\n    SST_PORT_INT_ENABLE(); // NOTE: enable interrupts for SS0\n}\n\n} // namespace SST\n\n"
  },
  {
    "path": "sst0_cpp/examples/blinky_button/bsp_nucleo-l053r8.cpp",
    "content": "//============================================================================\n// Super-Simple Tasker (SST0/C++) Example for STM32 NUCLEO-L053R8\n//\n//\n//                    Q u a n t u m  L e a P s\n//                    ------------------------\n//                    Modern Embedded Software\n//\n// Copyright (C) 2005 Quantum Leaps, <state-machine.com>.\n//\n// SPDX-License-Identifier: MIT\n//\n// Permission is hereby granted, free of charge, to any person obtaining a\n// copy of this software and associated documentation files (the \"Software\"),\n// to deal in the Software without restriction, including without limitation\n// the rights to use, copy, modify, merge, publish, distribute, sublicense,\n// and/or sell copies of the Software, and to permit persons to whom the\n// Software is furnished to do so, subject to the following conditions:\n//\n// The above copyright notice and this permission notice shall be included in\n// all copies or substantial portions of the Software.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n// DEALINGS IN THE SOFTWARE.\n//============================================================================\n#include \"sst.hpp\"           // SST framework\n#include \"bsp.hpp\"           // Board Support Package interface\n#include \"blinky_button.hpp\" // application shared interface\n\n#include \"stm32l0xx.h\"  // CMSIS-compliant header file for the MCU used\n// add other drivers if necessary...\n\n// Local-scope defines -------------------------------------------------------\nnamespace {\n\nDBC_MODULE_NAME(\"bsp_nucleo-l053r8\") // for DBC assertions in this module\n\n} // unnamed workspace\n\n// test pins on GPIO PA\n#define TST1_PIN  7U\n#define TST2_PIN  6U\n#define TST3_PIN  4U\n#define TST4_PIN  1U\n#define TST5_PIN  0U\n#define TST6_PIN  5U /* LED LD2-Green */\n\n// buttons on GPIO PC\n#define B1_PIN    13U\n\n// ISRs used in the application ==============================================\nextern \"C\" {\n\nvoid SysTick_Handler(void);  // prototype\nvoid SysTick_Handler(void) { // system clock tick ISR\n    BSP::d1on();\n\n    SST::TimeEvt::tick();\n\n    // get state of the user button\n    // Perform the debouncing of buttons. The algorithm for debouncing\n    // adapted from the book \"Embedded Systems Dictionary\" by Jack Ganssle\n    // and Michael Barr, page 71.\n    //\n    static struct ButtonsDebouncing {\n        uint32_t depressed;\n        uint32_t previous;\n    } buttons = { 0U, 0U };\n    uint32_t current = ~GPIOC->IDR; // read GPIO PortC\n    uint32_t tmp = buttons.depressed; // save the debounced depressed\n    buttons.depressed |= (buttons.previous & current); // set depressed\n    buttons.depressed &= (buttons.previous | current); // clear released\n    buttons.previous   = current; // update the history\n    tmp ^= buttons.depressed;     // changed debounced depressed\n    if ((tmp & (1U << B1_PIN)) != 0U) { // debounced B1 state changed?\n        if ((buttons.depressed & (1U << B1_PIN)) != 0U) { // depressed?\n            // immutable button-press event\n            static App::ButtonWorkEvt const pressEvt = {\n                { App::BUTTON_PRESSED_SIG }, 60U\n            };\n            // immutable forward-press event\n            static App::ButtonWorkEvt const fPressEvt = {\n                { App::FORWARD_PRESSED_SIG }, 60U\n            };\n            App::AO_Button2a->post(&fPressEvt.super);\n            App::AO_Button2a->post(&pressEvt.super);\n        }\n        else { // B1 is released\n            // immutable button-release event\n            static App::ButtonWorkEvt const releaseEvt = {\n                { App::BUTTON_RELEASED_SIG }, 80U\n            };\n            // immutable forward-release event\n            static App::ButtonWorkEvt const fReleaseEvt = {\n                { App::FORWARD_RELEASED_SIG }, 80U\n            };\n            App::AO_Button2a->post(&fReleaseEvt.super);\n            App::AO_Button2a->post(&releaseEvt.super);\n        }\n    }\n\n    BSP::d1off();\n}\n\n// Assertion handler =========================================================\nvoid DBC_fault_handler(char const * const module, int const label) {\n    //\n    // NOTE: add here your application-specific error handling\n    //\n    (void)module;\n    (void)label;\n\n    // set PRIMASK to disable interrupts and stop SST right here\n    __asm volatile (\"cpsid i\");\n\n#ifndef NDEBUG\n    for (;;) { // keep blinking LED2\n        BSP::d6on();  // turn LED2 on\n        uint32_t volatile ctr;\n        for (ctr = 10000U; ctr > 0U; --ctr) {\n        }\n        BSP::d6off(); // turn LED2 off\n        for (ctr = 10000U; ctr > 0U; --ctr) {\n        }\n    }\n#endif\n    NVIC_SystemReset();\n}\n//............................................................................\nvoid assert_failed(char const * const module, int const label);// prototype\nvoid assert_failed(char const * const module, int const label) {\n    DBC_fault_handler(module, label);\n}\n\n} // extern \"C\"\n\nnamespace BSP {\n\n// BSP functions =============================================================\nvoid init(void) {\n    // Configure the MPU to prevent NULL-pointer dereferencing\n    // see: www.state-machine.com/null-pointer-protection-with-arm-cortex-m-mpu\n    //\n    MPU->RBAR = 0x0U                          // base address (NULL)\n                | MPU_RBAR_VALID_Msk          // valid region\n                | (MPU_RBAR_REGION_Msk & 7U); // region #7\n    MPU->RASR = (7U << MPU_RASR_SIZE_Pos)     // 2^(7+1) region\n                | (0x0U << MPU_RASR_AP_Pos)   // no-access region\n                | MPU_RASR_ENABLE_Msk;        // region enable\n\n    MPU->CTRL = MPU_CTRL_PRIVDEFENA_Msk       // enable background region\n                | MPU_CTRL_ENABLE_Msk;        // enable the MPU\n    __ISB();\n    __DSB();\n\n\n    // enable GPIO port PA clock\n    RCC->IOPENR |= (1U << 0U);\n\n    // set all used GPIOA pins as push-pull output, no pull-up, pull-down\n    GPIOA->MODER &=\n        ~((3U << 2U*TST1_PIN) | (3U << 2U*TST2_PIN) | (3U << 2U*TST3_PIN) |\n          (3U << 2U*TST4_PIN) | (3U << 2U*TST5_PIN) | (3U << 2U*TST6_PIN));\n    GPIOA->MODER |=\n         ((1U << 2U*TST1_PIN) | (1U << 2U*TST2_PIN) | (1U << 2U*TST3_PIN) |\n          (1U << 2U*TST4_PIN) | (1U << 2U*TST5_PIN) | (1U << 2U*TST6_PIN));\n    GPIOA->OTYPER &=\n        ~((1U <<    TST1_PIN) | (1U <<    TST2_PIN) | (1U <<    TST3_PIN) |\n          (1U <<    TST4_PIN) | (1U <<    TST5_PIN) | (1U <<    TST6_PIN));\n    GPIOA->PUPDR &=\n        ~((3U << 2U*TST1_PIN) | (3U << 2U*TST2_PIN) | (3U << 2U*TST3_PIN) |\n          (3U << 2U*TST4_PIN) | (3U << 2U*TST5_PIN) | (3U << 2U*TST6_PIN));\n\n    // enable GPIOC clock port for the Button B1\n    RCC->IOPENR |=  (1U << 2U);\n\n    // configure Button B1 pin on GPIOC as input, no pull-up, pull-down\n    GPIOC->MODER &= ~(3U << 2U*B1_PIN);\n    GPIOC->PUPDR &= ~(3U << 2U*B1_PIN);\n}\n//............................................................................\nvoid d1on(void)  { GPIOA->BSRR = (1U << TST1_PIN);         }\nvoid d1off(void) { GPIOA->BSRR = (1U << (TST1_PIN + 16U)); }\n//............................................................................\nvoid d2on(void)  { GPIOA->BSRR = (1U << TST2_PIN);         }\nvoid d2off(void) { GPIOA->BSRR = (1U << (TST2_PIN + 16U)); }\n//............................................................................\nvoid d3on(void)  { GPIOA->BSRR = (1U << TST3_PIN);         }\nvoid d3off(void) { GPIOA->BSRR = (1U << (TST3_PIN + 16U)); }\n//............................................................................\nvoid d4on(void)  { GPIOA->BSRR = (1U << TST4_PIN);         }\nvoid d4off(void) { GPIOA->BSRR = (1U << (TST4_PIN + 16U)); }\n//............................................................................\nvoid d5on(void)  { GPIOA->BSRR = (1U << TST5_PIN);         }\nvoid d5off(void) { GPIOA->BSRR = (1U << (TST5_PIN + 16U)); }\n//............................................................................\nvoid d6on(void)  { GPIOA->BSRR = (1U << TST6_PIN);         } // LED2\nvoid d6off(void) { GPIOA->BSRR = (1U << (TST6_PIN + 16U)); }\n\n//............................................................................\nSST::Evt const *getWorkEvtBlinky1(uint8_t num) {\n    // immutable work events for Blinky1\n    static App::BlinkyWorkEvt const workBlinky1[] = {\n        { { App::BLINKY_WORK_SIG }, 40U, 5U },\n        { { App::BLINKY_WORK_SIG }, 30U, 7U }\n    };\n    DBC_REQUIRE(500, num < ARRAY_NELEM(workBlinky1)); // num must be in range\n    return &workBlinky1[num].super;\n}\n//............................................................................\nSST::Evt const *getWorkEvtBlinky3(uint8_t num) {\n    // immutable work events for Blinky3\n    static App::BlinkyWorkEvt const workBlinky3[] = {\n        { { App::BLINKY_WORK_SIG }, 20U, 5U },\n        { { App::BLINKY_WORK_SIG }, 10U, 3U   }\n    };\n    DBC_REQUIRE(600, num < ARRAY_NELEM(workBlinky3)); // num must be in range\n    return &workBlinky3[num].super;\n}\n\n} // namespace BSP\n\n// SST callbacks =============================================================\nnamespace SST {\n\nvoid onStart(void) {\n    SystemCoreClockUpdate();\n\n    // set up the SysTick timer to fire at BSP::TICKS_PER_SEC rate\n    SysTick_Config((SystemCoreClock / BSP::TICKS_PER_SEC) + 1U);\n\n    // set priorities of ISRs used in the system\n    NVIC_SetPriority(SysTick_IRQn, 0U);\n    // ...\n}\n//............................................................................\nvoid onIdleCond(void) { // NOTE: called with interrupts DISABLED\n    BSP::d6on();  // turn LED2 on\n#ifdef NDEBUG\n    // Put the CPU and peripherals to the low-power mode.\n    // you might need to customize the clock management for your application,\n    // see the datasheet for your particular Cortex-M MCU.\n    //\n    BSP::d6off(); // turn LED2 off\n    __WFI(); // Wait-For-Interrupt\n    BSP::d6on();  // turn LED2 on\n#endif\n    BSP::d6off(); // turn LED2 off\n    SST_PORT_INT_ENABLE(); // NOTE: enable interrupts for SS0\n}\n\n} // namespace SST\n\n"
  },
  {
    "path": "sst0_cpp/examples/blinky_button/button2a.cpp",
    "content": "//============================================================================\n// Super-Simple Tasker (SST/C++) Example\n//\n// Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n//\n// SPDX-License-Identifier: MIT\n//\n// Permission is hereby granted, free of charge, to any person obtaining a\n// copy of this software and associated documentation files (the \"Software\"),\n// to deal in the Software without restriction, including without limitation\n// the rights to use, copy, modify, merge, publish, distribute, sublicense,\n// and/or sell copies of the Software, and to permit persons to whom the\n// Software is furnished to do so, subject to the following conditions:\n//\n// The above copyright notice and this permission notice shall be included in\n// all copies or substantial portions of the Software.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n// DEALINGS IN THE SOFTWARE.\n//============================================================================\n#include \"sst.hpp\"           // SST framework\n#include \"bsp.hpp\"           // Board Support Package interface\n#include \"blinky_button.hpp\" // application shared interface\n\nnamespace {\n\nDBC_MODULE_NAME(\"button2a\")  // for DBC assertions in this module\n\n} // unnamed namespace\n\nnamespace App {\n\n//............................................................................\nclass Button2a : public SST::Task {\n    // add internal variables for this AO...\n\npublic:\n    static Button2a inst;\n    void init(SST::Evt const * const ie) override;\n    void dispatch(SST::Evt const * const e) override;\n};\n\n//............................................................................\nButton2a Button2a::inst; // the Button2a instance\nSST::Task * const AO_Button2a = &Button2a::inst; // opaque AO pointer\n\n//............................................................................\nvoid Button2a::init(SST::Evt const * const /*ie*/) {\n}\n//............................................................................\nvoid Button2a::dispatch(SST::Evt const * const e) {\n    switch (e->sig) {\n        case BUTTON_PRESSED_SIG: {\n            BSP::d4on();\n            // Button2a --> Blinky1\n            AO_Blinky1->post(BSP::getWorkEvtBlinky1(1U));\n            BSP::d4off();\n\n            for (std::uint16_t i = SST::evt_downcast<ButtonWorkEvt>(e)->toggles;\n                 i > 0U; --i)\n            {\n                BSP::d4on();\n                BSP::d4off();\n            }\n            break;\n        }\n        case FORWARD_PRESSED_SIG: {\n            BSP::d4on();\n            // immutable event can be forwarded to another Task\n            AO_Button2b->post(e); // Button2a --> Button2b\n            BSP::d4off();\n            break;\n        }\n        case BUTTON_RELEASED_SIG: {\n            static BlinkyWorkEvt const bw2evt = {\n                { BLINKY_WORK_SIG }, 30U, 7U\n            };\n            AO_Blinky1->post(&bw2evt.super); // Button2b --> Blinky1\n\n            for (uint16_t i = SST::evt_downcast<ButtonWorkEvt>(e)->toggles;\n                 i > 0U; --i)\n            {\n                BSP::d4on();\n                BSP::d4off();\n            }\n            break;\n        }\n        case FORWARD_RELEASED_SIG: {\n            BSP::d4on();\n            // immutable event can be forwarded to another Task\n            AO_Button2b->post(e); // Button2a --> Button2b\n            BSP::d4off();\n            break;\n        }\n        default: {\n            DBC_ERROR(500); // unexpected event\n            break;\n        }\n    }\n}\n\n} // namespace App\n"
  },
  {
    "path": "sst0_cpp/examples/blinky_button/button2b.cpp",
    "content": "//============================================================================\n// Super-Simple Tasker (SST/C++) Example\n//\n// Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n//\n// SPDX-License-Identifier: MIT\n//\n// Permission is hereby granted, free of charge, to any person obtaining a\n// copy of this software and associated documentation files (the \"Software\"),\n// to deal in the Software without restriction, including without limitation\n// the rights to use, copy, modify, merge, publish, distribute, sublicense,\n// and/or sell copies of the Software, and to permit persons to whom the\n// Software is furnished to do so, subject to the following conditions:\n//\n// The above copyright notice and this permission notice shall be included in\n// all copies or substantial portions of the Software.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n// DEALINGS IN THE SOFTWARE.\n//============================================================================\n#include \"sst.hpp\"           // SST framework\n#include \"bsp.hpp\"           // Board Support Package interface\n#include \"blinky_button.hpp\" // application shared interface\n\nnamespace {\n\nDBC_MODULE_NAME(\"button2b\")  // for DBC assertions in this module\n\n} // unnamed namespace\n\nnamespace App {\n\n//............................................................................\nclass Button2b : public SST::Task {\n    // add internal variables for this AO...\n\npublic:\n    static Button2b inst;\n    void init(SST::Evt const * const ie) override;\n    void dispatch(SST::Evt const * const e) override;\n};\n\n//............................................................................\nButton2b Button2b::inst; // the Button2b instance\nSST::Task * const AO_Button2b = &Button2b::inst; // opaque AO pointer\n\n//............................................................................\nvoid Button2b::init(SST::Evt const * const /*ie*/) {\n}\n//............................................................................\nvoid Button2b::dispatch(SST::Evt const * const e) {\n    switch (e->sig) {\n        case FORWARD_PRESSED_SIG: {\n            BSP::d3on();\n            // Button2b --> Blinky3\n            AO_Blinky3->post(BSP::getWorkEvtBlinky3(1U));\n            BSP::d3off();\n\n            for (std::uint16_t i = SST::evt_downcast<ButtonWorkEvt>(e)->toggles;\n                 i > 0U; --i)\n            {\n                BSP::d3on();\n                BSP::d3off();\n            }\n            break;\n        }\n        case FORWARD_RELEASED_SIG: {\n            BSP::d3on();\n            // Button2b --> Blinky3\n            AO_Blinky3->post(BSP::getWorkEvtBlinky3(0U));\n            BSP::d3off();\n\n            for (uint16_t i = SST::evt_downcast<ButtonWorkEvt>(e)->toggles;\n                 i > 0U; --i)\n            {\n                BSP::d3on();\n                BSP::d3off();\n            }\n            break;\n        }\n        default: {\n            DBC_ERROR(500); /* unexpected event */\n            break;\n        }\n    }\n}\n\n} // namespace App\n"
  },
  {
    "path": "sst0_cpp/examples/blinky_button/gnu/ek-tm4c123gxl.mak",
    "content": "##############################################################################\n# Makefile for Super-Simple Tasker (SST0/C++) on TM4C123GXL, GNU-ARM\n# Last Updated for Version: 2.0.0\n# Date of the Last Update:  2023-01-25\n#\n#                    Q u a n t u m  L e a P s\n#                    ------------------------\n#                    Modern Embedded Software\n#\n# Copyright (C) 2005 Quantum Leaps, LLC. All rights reserved.\n#\n# SPDX-License-Identifier: MIT\n#\n# Permission is hereby granted, free of charge, to any person obtaining a copy\n# of this software and associated documentation files (the \"Software\"), to\n# deal in the Software without restriction, including without limitation the\n# rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n# sell copies of the Software, and to permit persons to whom the Software is\n# furnished to do so, subject to the following conditions:\n#\n# The above copyright notice and this permission notice shall be included in\n# all copies or substantial portions of the Software.\n#\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS\n# IN THE SOFTWARE.\n##############################################################################\n# examples of invoking this Makefile:\n# make -f ek-tm4c123gxl.mak\n# make -f ek-tm4c123gxl.mak clean\n#\n# NOTE:\n# To use this Makefile on Windows, you will need the GNU make utility, which\n# is included in the QTools collection for Windows, see:\n#    https://github.com/QuantumLeaps/qtools\n#\n\n#-----------------------------------------------------------------------------\n# project and target names\n#\nPROJECT := blinky_button\nTARGET  := ek-tm4c123gxl\n\n#-----------------------------------------------------------------------------\n# project directories\n#\nSST_DIR      := ../../..\nSST_PORT_DIR := $(SST_DIR)/ports/arm-cm\nCMSIS_DIR    := ../../../../3rd_party/CMSIS\nTARGET_DIR   := ../../../../3rd_party/$(TARGET)\n\n# list of all source directories used by this project\nVPATH = .. \\\n\t$(SST_DIR)/src \\\n\t$(SST_PORT_DIR) \\\n\t$(TARGET_DIR) \\\n\t$(TARGET_DIR)/gnu \\\n\n# list of all include directories needed by this project\nINCLUDES  = -I. \\\n\t-I$(SST_DIR)/../include \\\n\t-I$(SST_PORT_DIR) \\\n\t-I$(CMSIS_DIR)/Include \\\n\t-I$(TARGET_DIR)\n\n#-----------------------------------------------------------------------------\n# project files\n#\n\n# assembler source files\nASM_SRCS :=\n\n# C source files\nC_SRCS := \\\n\tsystem_TM4C123GH6PM.c \\\n\tstartup_TM4C123GH6PM.c\n\n# C++ source files\nCPP_SRCS := \\\n\tsst0.cpp \\\n\tmain.cpp \\\n\tblinky1.cpp \\\n\tblinky3.cpp \\\n\tbutton2a.cpp \\\n\tbutton2b.cpp \\\n\tbsp_ek-tm4c123gxl.cpp\n\nLD_SCRIPT  := $(TARGET_DIR)/gnu/$(TARGET).ld\n\nOUTPUT    := $(PROJECT)\n\nLIB_DIRS  :=\nLIBS      :=\n\n# defines\nDEFINES   := -DTARGET_IS_TM4C123_RB1\n\n# ARM CPU, ARCH, FPU, and Float-ABI types...\n# ARM_CPU:   [cortex-m0 | cortex-m0plus | cortex-m1 | cortex-m3 | cortex-m4]\n# ARM_FPU:   [ | vfp]\n# FLOAT_ABI: [ | soft | softfp | hard]\n#\nARM_CPU   := -mcpu=cortex-m4\nARM_FPU   := -mfpu=vfp\nFLOAT_ABI := -mfloat-abi=softfp\n\n#-----------------------------------------------------------------------------\n# GNU-ARM toolset (NOTE: You need to adjust to your machine)\n# see https://developer.arm.com/open-source/gnu-toolchain/gnu-rm/downloads\n#\nifeq ($(GNU_ARM),)\nGNU_ARM := $(QTOOLS)/gnu_arm-none-eabi\nendif\n\n# make sure that the GNU-ARM toolset exists...\nifeq (\"$(wildcard $(GNU_ARM))\",\"\")\n$(error GNU_ARM toolset not found. Please adjust the Makefile)\nendif\n\nCC    := $(GNU_ARM)/bin/arm-none-eabi-gcc\nCPP   := $(GNU_ARM)/bin/arm-none-eabi-g++\nAS    := $(GNU_ARM)/bin/arm-none-eabi-as\nLINK  := $(GNU_ARM)/bin/arm-none-eabi-g++\nBIN   := $(GNU_ARM)/bin/arm-none-eabi-objcopy\n\n##############################################################################\n# Typically you should not need to change anything below this line\n\n# basic utilities (included in QTools for Windows), see:\n#     https://www.state-machine.com/qtools\n\nMKDIR := mkdir\nRM    := rm\n\n#-----------------------------------------------------------------------------\n# build options\n#\n\n# combine all the soruces...\nC_SRCS += $(QP_SRCS)\nASM_SRCS += $(QP_ASMS)\n\nBIN_DIR := build_$(TARGET)\n\nASFLAGS = -g $(ARM_CPU) $(ARM_FPU) $(ASM_CPU) $(ASM_FPU)\n\nCFLAGS = -c -g $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -std=c99 -mthumb -Wall \\\n\t-ffunction-sections -fdata-sections \\\n\t-O $(INCLUDES) $(DEFINES)\n\nCPPFLAGS = -c -g $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -std=c++11 -mthumb -Wall \\\n\t-ffunction-sections -fdata-sections -fno-rtti -fno-exceptions \\\n\t-O $(INCLUDES) $(DEFINES)\n\nLINKFLAGS = -T$(LD_SCRIPT) $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -mthumb \\\n\t-specs=nosys.specs -specs=nano.specs \\\n\t-Wl,-Map,$(BIN_DIR)/$(OUTPUT).map,--cref,--gc-sections $(LIB_DIRS)\n\nASM_OBJS     := $(patsubst %.s,%.o,  $(notdir $(ASM_SRCS)))\nC_OBJS       := $(patsubst %.c,%.o,  $(notdir $(C_SRCS)))\nCPP_OBJS     := $(patsubst %.cpp,%.o,$(notdir $(CPP_SRCS)))\n\nTARGET_BIN   := $(BIN_DIR)/$(OUTPUT).bin\nTARGET_ELF   := $(BIN_DIR)/$(OUTPUT).elf\nASM_OBJS_EXT := $(addprefix $(BIN_DIR)/, $(ASM_OBJS))\nC_OBJS_EXT   := $(addprefix $(BIN_DIR)/, $(C_OBJS))\nC_DEPS_EXT   := $(patsubst %.o, %.d, $(C_OBJS_EXT))\nCPP_OBJS_EXT := $(addprefix $(BIN_DIR)/, $(CPP_OBJS))\nCPP_DEPS_EXT := $(patsubst %.o, %.d, $(CPP_OBJS_EXT))\n\n# create $(BIN_DIR) if it does not exist\nifeq (\"$(wildcard $(BIN_DIR))\",\"\")\n$(shell $(MKDIR) $(BIN_DIR))\nendif\n\n#-----------------------------------------------------------------------------\n# rules\n#\n\n.PHONY : run norun flash\n\nifeq ($(MAKECMDGOALS),norun)\nall : $(TARGET_BIN)\nnorun : all\nelse\nall : $(TARGET_BIN) run\nendif\n\n$(TARGET_BIN): $(TARGET_ELF)\n\t$(BIN) -O binary $< $@\n\n$(TARGET_ELF) : $(ASM_OBJS_EXT) $(C_OBJS_EXT) $(CPP_OBJS_EXT)\n\t$(LINK) $(LINKFLAGS) -o $@ $^ $(LIBS)\n\n$(BIN_DIR)/%.d : %.c\n\t$(CC) -MM -MT $(@:.d=.o) $(CFLAGS) $< > $@\n\n$(BIN_DIR)/%.d : %.cpp\n\t$(CPP) -MM -MT $(@:.d=.o) $(CPPFLAGS) $< > $@\n\n$(BIN_DIR)/%.o : %.s\n\t$(AS) $(ASFLAGS) $< -o $@\n\n$(BIN_DIR)/%.o : %.c\n\t$(CC) $(CFLAGS) $< -o $@\n\n$(BIN_DIR)/%.o : %.cpp\n\t$(CPP) $(CPPFLAGS) $< -o $@\n\n.PHONY : clean show\n\n# include dependency files only if our goal depends on their existence\nifneq ($(MAKECMDGOALS),clean)\n  ifneq ($(MAKECMDGOALS),show)\n-include $(C_DEPS_EXT) $(CPP_DEPS_EXT)\n  endif\nendif\n\n\nclean :\n\t-$(RM) $(BIN_DIR)/*.o \\\n\t$(BIN_DIR)/*.d \\\n\t$(BIN_DIR)/*.bin \\\n\t$(BIN_DIR)/*.elf \\\n\t$(BIN_DIR)/*.map\n\t\nshow:\n\t@echo PROJECT = $(PROJECT)\n\t@echo CONF = $(CONF)\n\t@echo DEFINES = $(DEFINES)\n\t@echo ASM_FPU = $(ASM_FPU)\n\t@echo ASM_SRCS = $(ASM_SRCS)\n\t@echo C_SRCS = $(C_SRCS)\n\t@echo CPP_SRCS = $(CPP_SRCS)\n\t@echo ASM_OBJS_EXT = $(ASM_OBJS_EXT)\n\t@echo C_OBJS_EXT = $(C_OBJS_EXT)\n\t@echo C_DEPS_EXT = $(C_DEPS_EXT)\n\t@echo CPP_DEPS_EXT = $(CPP_DEPS_EXT)\n\t@echo TARGET_ELF = $(TARGET_ELF)\n"
  },
  {
    "path": "sst0_cpp/examples/blinky_button/gnu/flash_ek-tm4c123gxl.bat",
    "content": "::============================================================================\n:: Batch file to program the flash of EK-TM4C123GXL\n::\n:: NOTE: requires the LMFlash programmer (included in QTools for Windows)\n::\n@echo off\nsetlocal\n\n@echo Load a given binary file to the flash of EK-TM4C123GXL\n@echo usage:   flash binary-file\n@echo example: flash dbg\\blinky-qk.bin\n\n::----------------------------------------------------------------------------\n:: NOTE: The following symbol LMFLASH assumes that LMFlash.exe can\n:: be found on the PATH. You might need to adjust this symbol to the\n:: location of the LMFlash utility on your machine\n::\nset LMFLASH=LMFlash.exe\n\nif [\"%~1\"]==[\"\"] (\n    @echo The binary file missing\n    @goto end\n)\nif not exist %~s1 (\n    @echo The binary file '%1' does not exist\n    @goto end\n)\n\n%LMFLASH% -q ek-tm4c123gxl -e -v -r %1\n\n:end\n\nendlocal"
  },
  {
    "path": "sst0_cpp/examples/blinky_button/gnu/nucleo-c031c6.mak",
    "content": "##############################################################################\n# Makefile for Super-Simple Tasker (SST0/C++) on NUCLEO-C031C6, GNU-ARM\n# Last Updated for Version: 2.0.0\n# Date of the Last Update:  2023-02-01\n#\n#                    Q u a n t u m  L e a P s\n#                    ------------------------\n#                    Modern Embedded Software\n#\n# Copyright (C) 2005 Quantum Leaps, LLC. All rights reserved.\n#\n# SPDX-License-Identifier: MIT\n#\n# Permission is hereby granted, free of charge, to any person obtaining a copy\n# of this software and associated documentation files (the \"Software\"), to\n# deal in the Software without restriction, including without limitation the\n# rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n# sell copies of the Software, and to permit persons to whom the Software is\n# furnished to do so, subject to the following conditions:\n#\n# The above copyright notice and this permission notice shall be included in\n# all copies or substantial portions of the Software.\n#\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS\n# IN THE SOFTWARE.\n##############################################################################\n# examples of invoking this Makefile:\n# make -f nucleo-c031c6.mak\n# make -f nucleo-c031c6.mak clean\n#\n# NOTE:\n# To use this Makefile on Windows, you will need the GNU make utility, which\n# is included in the QTools collection for Windows, see:\n#    https://github.com/QuantumLeaps/qtools\n#\n\n#-----------------------------------------------------------------------------\n# project and target names\n#\nPROJECT := blinky_button\nTARGET  := nucleo-c031c6\n\n#-----------------------------------------------------------------------------\n# project directories\n#\nSST_DIR      := ../../..\nSST_PORT_DIR := $(SST_DIR)/ports/arm-cm\nCMSIS_DIR    := ../../../../3rd_party/CMSIS\nTARGET_DIR   := ../../../../3rd_party/$(TARGET)\n\n# list of all source directories used by this project\nVPATH = .. \\\n\t$(SST_DIR)/src \\\n\t$(SST_PORT_DIR) \\\n\t$(TARGET_DIR) \\\n\t$(TARGET_DIR)/gnu \\\n\n# list of all include directories needed by this project\nINCLUDES  = -I. \\\n\t-I$(SST_DIR)/../include \\\n\t-I$(SST_PORT_DIR) \\\n\t-I$(CMSIS_DIR)/Include \\\n\t-I$(TARGET_DIR)\n\n#-----------------------------------------------------------------------------\n# project files\n#\n\n# assembler source files\nASM_SRCS :=\n\n# C source files\nC_SRCS := \\\n\tsystem_stm32c0xx.c \\\n\tstartup_stm32c031xx.c\n\n# C++ source files\nCPP_SRCS := \\\n\tsst0.cpp \\\n\tmain.cpp \\\n\tblinky1.cpp \\\n\tblinky3.cpp \\\n\tbutton2a.cpp \\\n\tbutton2b.cpp \\\n\tbsp_nucleo-c031c6.cpp\n\nLD_SCRIPT  := $(TARGET_DIR)/gnu/$(TARGET).ld\n\nOUTPUT    := $(PROJECT)\n\nLIB_DIRS  :=\nLIBS      :=\n\n# defines\nDEFINES   := -DSTM32C031xx\n\n# ARM CPU, ARCH, FPU, and Float-ABI types...\n# ARM_CPU:   [cortex-m0 | cortex-m0plus | cortex-m1 | cortex-m3 | cortex-m4]\n# ARM_FPU:   [ | vfp]\n# FLOAT_ABI: [ | soft | softfp | hard]\n#\nARM_CPU   := -mcpu=cortex-m0plus\nARM_FPU   :=\nFLOAT_ABI :=\n\n#-----------------------------------------------------------------------------\n# GNU-ARM toolset (NOTE: You need to adjust to your machine)\n# see https://developer.arm.com/open-source/gnu-toolchain/gnu-rm/downloads\n#\nifeq ($(GNU_ARM),)\nGNU_ARM := $(QTOOLS)/gnu_arm-none-eabi\nendif\n\n# make sure that the GNU-ARM toolset exists...\nifeq (\"$(wildcard $(GNU_ARM))\",\"\")\n$(error GNU_ARM toolset not found. Please adjust the Makefile)\nendif\n\nCC    := $(GNU_ARM)/bin/arm-none-eabi-gcc\nCPP   := $(GNU_ARM)/bin/arm-none-eabi-g++\nAS    := $(GNU_ARM)/bin/arm-none-eabi-as\nLINK  := $(GNU_ARM)/bin/arm-none-eabi-g++\nBIN   := $(GNU_ARM)/bin/arm-none-eabi-objcopy\n\n##############################################################################\n# Typically you should not need to change anything below this line\n\n# basic utilities (included in QTools for Windows), see:\n#     https://www.state-machine.com/qtools\n\nMKDIR := mkdir\nRM    := rm\n\n#-----------------------------------------------------------------------------\n# build options\n#\n\n# combine all the soruces...\nC_SRCS += $(QP_SRCS)\nASM_SRCS += $(QP_ASMS)\n\nBIN_DIR := build_$(TARGET)\n\nASFLAGS = -g $(ARM_CPU) $(ARM_FPU) $(ASM_CPU) $(ASM_FPU)\n\nCFLAGS = -c -g $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -std=c99 -mthumb -Wall \\\n\t-ffunction-sections -fdata-sections \\\n\t-O $(INCLUDES) $(DEFINES)\n\nCPPFLAGS = -c -g $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -std=c++11 -mthumb -Wall \\\n\t-ffunction-sections -fdata-sections -fno-rtti -fno-exceptions \\\n\t-O $(INCLUDES) $(DEFINES)\n\nLINKFLAGS = -T$(LD_SCRIPT) $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -mthumb \\\n\t-specs=nosys.specs -specs=nano.specs \\\n\t-Wl,-Map,$(BIN_DIR)/$(OUTPUT).map,--cref,--gc-sections $(LIB_DIRS)\n\nASM_OBJS     := $(patsubst %.s,%.o,  $(notdir $(ASM_SRCS)))\nC_OBJS       := $(patsubst %.c,%.o,  $(notdir $(C_SRCS)))\nCPP_OBJS     := $(patsubst %.cpp,%.o,$(notdir $(CPP_SRCS)))\n\nTARGET_BIN   := $(BIN_DIR)/$(OUTPUT).bin\nTARGET_ELF   := $(BIN_DIR)/$(OUTPUT).elf\nASM_OBJS_EXT := $(addprefix $(BIN_DIR)/, $(ASM_OBJS))\nC_OBJS_EXT   := $(addprefix $(BIN_DIR)/, $(C_OBJS))\nC_DEPS_EXT   := $(patsubst %.o, %.d, $(C_OBJS_EXT))\nCPP_OBJS_EXT := $(addprefix $(BIN_DIR)/, $(CPP_OBJS))\nCPP_DEPS_EXT := $(patsubst %.o, %.d, $(CPP_OBJS_EXT))\n\n# create $(BIN_DIR) if it does not exist\nifeq (\"$(wildcard $(BIN_DIR))\",\"\")\n$(shell $(MKDIR) $(BIN_DIR))\nendif\n\n#-----------------------------------------------------------------------------\n# rules\n#\n\n.PHONY : run norun flash\n\nifeq ($(MAKECMDGOALS),norun)\nall : $(TARGET_BIN)\nnorun : all\nelse\nall : $(TARGET_BIN) run\nendif\n\n$(TARGET_BIN): $(TARGET_ELF)\n\t$(BIN) -O binary $< $@\n\n$(TARGET_ELF) : $(ASM_OBJS_EXT) $(C_OBJS_EXT) $(CPP_OBJS_EXT)\n\t$(LINK) $(LINKFLAGS) -o $@ $^ $(LIBS)\n\n$(BIN_DIR)/%.d : %.c\n\t$(CC) -MM -MT $(@:.d=.o) $(CFLAGS) $< > $@\n\n$(BIN_DIR)/%.d : %.cpp\n\t$(CPP) -MM -MT $(@:.d=.o) $(CPPFLAGS) $< > $@\n\n$(BIN_DIR)/%.o : %.s\n\t$(AS) $(ASFLAGS) $< -o $@\n\n$(BIN_DIR)/%.o : %.c\n\t$(CC) $(CFLAGS) $< -o $@\n\n$(BIN_DIR)/%.o : %.cpp\n\t$(CPP) $(CPPFLAGS) $< -o $@\n\n.PHONY : clean show\n\n# include dependency files only if our goal depends on their existence\nifneq ($(MAKECMDGOALS),clean)\n  ifneq ($(MAKECMDGOALS),show)\n-include $(C_DEPS_EXT) $(CPP_DEPS_EXT)\n  endif\nendif\n\n\nclean :\n\t-$(RM) $(BIN_DIR)/*.o \\\n\t$(BIN_DIR)/*.d \\\n\t$(BIN_DIR)/*.bin \\\n\t$(BIN_DIR)/*.elf \\\n\t$(BIN_DIR)/*.map\n\t\nshow:\n\t@echo PROJECT = $(PROJECT)\n\t@echo CONF = $(CONF)\n\t@echo DEFINES = $(DEFINES)\n\t@echo ASM_FPU = $(ASM_FPU)\n\t@echo ASM_SRCS = $(ASM_SRCS)\n\t@echo C_SRCS = $(C_SRCS)\n\t@echo CPP_SRCS = $(CPP_SRCS)\n\t@echo ASM_OBJS_EXT = $(ASM_OBJS_EXT)\n\t@echo C_OBJS_EXT = $(C_OBJS_EXT)\n\t@echo C_DEPS_EXT = $(C_DEPS_EXT)\n\t@echo CPP_DEPS_EXT = $(CPP_DEPS_EXT)\n\t@echo TARGET_ELF = $(TARGET_ELF)\n"
  },
  {
    "path": "sst0_cpp/examples/blinky_button/gnu/nucleo-h743zi.mak",
    "content": "##############################################################################\n# Makefile for Super-Simple Tasker (SST/C++) on NUCLEO-H743ZI, GNU-ARM\n# Last Updated for Version: 2.0.0\n# Date of the Last Update:  2023-01-22\n#\n#                    Q u a n t u m  L e a P s\n#                    ------------------------\n#                    Modern Embedded Software\n#\n# Copyright (C) 2005 Quantum Leaps, LLC. All rights reserved.\n#\n# SPDX-License-Identifier: MIT\n#\n# Permission is hereby granted, free of charge, to any person obtaining a copy\n# of this software and associated documentation files (the \"Software\"), to\n# deal in the Software without restriction, including without limitation the\n# rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n# sell copies of the Software, and to permit persons to whom the Software is\n# furnished to do so, subject to the following conditions:\n#\n# The above copyright notice and this permission notice shall be included in\n# all copies or substantial portions of the Software.\n#\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS\n# IN THE SOFTWARE.\n##############################################################################\n# examples of invoking this Makefile:\n# make -f nucleo-h743zi.mak\n# make -f nucleo-h743zi.mak clean\n#\n# NOTE:\n# To use this Makefile on Windows, you will need the GNU make utility, which\n# is included in the QTools collection for Windows, see:\n#    https://github.com/QuantumLeaps/qtools\n#\n\n#-----------------------------------------------------------------------------\n# project and target names\n#\nPROJECT := blinky_button\nTARGET  := nucleo-h743zi\n\n#-----------------------------------------------------------------------------\n# project directories\n#\nSST_DIR      := ../../..\nSST_PORT_DIR := $(SST_DIR)/ports/arm-cm\nCMSIS_DIR    := ../../../../3rd_party/CMSIS\nTARGET_DIR   := ../../../../3rd_party/$(TARGET)\n\n# list of all source directories used by this project\nVPATH = .. \\\n\t$(SST_DIR)/src \\\n\t$(SST_PORT_DIR) \\\n\t$(TARGET_DIR) \\\n\t$(TARGET_DIR)/gnu \\\n\n# list of all include directories needed by this project\nINCLUDES  = -I. \\\n\t-I$(SST_DIR)/../include \\\n\t-I$(SST_PORT_DIR) \\\n\t-I$(CMSIS_DIR)/Include \\\n\t-I$(TARGET_DIR)\n\n#-----------------------------------------------------------------------------\n# project files\n#\n\n# assembler source files\nASM_SRCS :=\n\n# C source files\nC_SRCS := \\\n\tstartup_stm32h743xx.c \\\n\tsystem_stm32h7xx.c\n\n# C++ source files\nCPP_SRCS := \\\n\tsst0.cpp \\\n\tmain.cpp \\\n\tblinky1.cpp \\\n\tblinky3.cpp \\\n\tbutton2a.cpp \\\n\tbutton2b.cpp \\\n\tbsp_nucleo-h743zi.cpp\n\nLD_SCRIPT  := $(TARGET_DIR)/gnu/$(TARGET).ld\n\nOUTPUT    := $(PROJECT)\n\nLIB_DIRS  :=\nLIBS      :=\n\n# defines\nDEFINES   := -DSTM32H743xx\n\n# ARM CPU, ARCH, FPU, and Float-ABI types...\n# ARM_CPU:   [cortex-m0 | cortex-m0plus | cortex-m1 | cortex-m3 | cortex-m4]\n# ARM_FPU:   [ | vfp]\n# FLOAT_ABI: [ | soft | softfp | hard]\n#\nARM_CPU   := -mcpu=cortex-m7\nARM_FPU   := -mfpu=fpv5-d16\nFLOAT_ABI := -mfloat-abi=softfp\n\n#-----------------------------------------------------------------------------\n# GNU-ARM toolset (NOTE: You need to adjust to your machine)\n# see https://developer.arm.com/open-source/gnu-toolchain/gnu-rm/downloads\n#\nifeq ($(GNU_ARM),)\nGNU_ARM := $(QTOOLS)/gnu_arm-none-eabi\nendif\n\n# make sure that the GNU-ARM toolset exists...\nifeq (\"$(wildcard $(GNU_ARM))\",\"\")\n$(error GNU_ARM toolset not found. Please adjust the Makefile)\nendif\n\nCC    := $(GNU_ARM)/bin/arm-none-eabi-gcc\nCPP   := $(GNU_ARM)/bin/arm-none-eabi-g++\nAS    := $(GNU_ARM)/bin/arm-none-eabi-as\nLINK  := $(GNU_ARM)/bin/arm-none-eabi-g++\nBIN   := $(GNU_ARM)/bin/arm-none-eabi-objcopy\n\n##############################################################################\n# Typically you should not need to change anything below this line\n\n# basic utilities (included in QTools for Windows), see:\n#     https://www.state-machine.com/qtools\n\nMKDIR := mkdir\nRM    := rm\n\n#-----------------------------------------------------------------------------\n# build options\n#\n\n# combine all the soruces...\nC_SRCS += $(QP_SRCS)\nASM_SRCS += $(QP_ASMS)\n\nBIN_DIR := build_$(TARGET)\n\nASFLAGS = -g $(ARM_CPU) $(ARM_FPU) $(ASM_CPU) $(ASM_FPU)\n\nCFLAGS = -c -g $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -std=c99 -mthumb -Wall \\\n\t-ffunction-sections -fdata-sections \\\n\t-O $(INCLUDES) $(DEFINES)\n\nCPPFLAGS = -c -g $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -std=c++11 -mthumb -Wall \\\n\t-ffunction-sections -fdata-sections -fno-rtti -fno-exceptions \\\n\t-O $(INCLUDES) $(DEFINES)\n\nLINKFLAGS = -T$(LD_SCRIPT) $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -mthumb \\\n\t-specs=nosys.specs -specs=nano.specs \\\n\t-Wl,-Map,$(BIN_DIR)/$(OUTPUT).map,--cref,--gc-sections $(LIB_DIRS)\n\nASM_OBJS     := $(patsubst %.s,%.o,  $(notdir $(ASM_SRCS)))\nC_OBJS       := $(patsubst %.c,%.o,  $(notdir $(C_SRCS)))\nCPP_OBJS     := $(patsubst %.cpp,%.o,$(notdir $(CPP_SRCS)))\n\nTARGET_BIN   := $(BIN_DIR)/$(OUTPUT).bin\nTARGET_ELF   := $(BIN_DIR)/$(OUTPUT).elf\nASM_OBJS_EXT := $(addprefix $(BIN_DIR)/, $(ASM_OBJS))\nC_OBJS_EXT   := $(addprefix $(BIN_DIR)/, $(C_OBJS))\nC_DEPS_EXT   := $(patsubst %.o, %.d, $(C_OBJS_EXT))\nCPP_OBJS_EXT := $(addprefix $(BIN_DIR)/, $(CPP_OBJS))\nCPP_DEPS_EXT := $(patsubst %.o, %.d, $(CPP_OBJS_EXT))\n\n# create $(BIN_DIR) if it does not exist\nifeq (\"$(wildcard $(BIN_DIR))\",\"\")\n$(shell $(MKDIR) $(BIN_DIR))\nendif\n\n#-----------------------------------------------------------------------------\n# rules\n#\n\n.PHONY : run norun flash\n\nifeq ($(MAKECMDGOALS),norun)\nall : $(TARGET_BIN)\nnorun : all\nelse\nall : $(TARGET_BIN) run\nendif\n\n$(TARGET_BIN): $(TARGET_ELF)\n\t$(BIN) -O binary $< $@\n\n$(TARGET_ELF) : $(ASM_OBJS_EXT) $(C_OBJS_EXT) $(CPP_OBJS_EXT)\n\t$(LINK) $(LINKFLAGS) -o $@ $^ $(LIBS)\n\n$(BIN_DIR)/%.d : %.c\n\t$(CC) -MM -MT $(@:.d=.o) $(CFLAGS) $< > $@\n\n$(BIN_DIR)/%.d : %.cpp\n\t$(CPP) -MM -MT $(@:.d=.o) $(CPPFLAGS) $< > $@\n\n$(BIN_DIR)/%.o : %.s\n\t$(AS) $(ASFLAGS) $< -o $@\n\n$(BIN_DIR)/%.o : %.c\n\t$(CC) $(CFLAGS) $< -o $@\n\n$(BIN_DIR)/%.o : %.cpp\n\t$(CPP) $(CPPFLAGS) $< -o $@\n\n.PHONY : clean show\n\n# include dependency files only if our goal depends on their existence\nifneq ($(MAKECMDGOALS),clean)\n  ifneq ($(MAKECMDGOALS),show)\n-include $(C_DEPS_EXT) $(CPP_DEPS_EXT)\n  endif\nendif\n\n\nclean :\n\t-$(RM) $(BIN_DIR)/*.o \\\n\t$(BIN_DIR)/*.d \\\n\t$(BIN_DIR)/*.bin \\\n\t$(BIN_DIR)/*.elf \\\n\t$(BIN_DIR)/*.map\n\t\nshow:\n\t@echo PROJECT = $(PROJECT)\n\t@echo CONF = $(CONF)\n\t@echo DEFINES = $(DEFINES)\n\t@echo ASM_FPU = $(ASM_FPU)\n\t@echo ASM_SRCS = $(ASM_SRCS)\n\t@echo C_SRCS = $(C_SRCS)\n\t@echo CPP_SRCS = $(CPP_SRCS)\n\t@echo ASM_OBJS_EXT = $(ASM_OBJS_EXT)\n\t@echo C_OBJS_EXT = $(C_OBJS_EXT)\n\t@echo C_DEPS_EXT = $(C_DEPS_EXT)\n\t@echo CPP_DEPS_EXT = $(CPP_DEPS_EXT)\n\t@echo TARGET_ELF = $(TARGET_ELF)\n"
  },
  {
    "path": "sst0_cpp/examples/blinky_button/gnu/nucleo-l053r8.mak",
    "content": "##############################################################################\n# Makefile for Super-Simple Tasker (SST/C++) on NUCLEO-L053R8, GNU-ARM\n# Last Updated for Version: 2.0.0\n# Date of the Last Update:  2023-01-22\n#\n#                    Q u a n t u m  L e a P s\n#                    ------------------------\n#                    Modern Embedded Software\n#\n# Copyright (C) 2005 Quantum Leaps, LLC. All rights reserved.\n#\n# SPDX-License-Identifier: MIT\n#\n# Permission is hereby granted, free of charge, to any person obtaining a copy\n# of this software and associated documentation files (the \"Software\"), to\n# deal in the Software without restriction, including without limitation the\n# rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n# sell copies of the Software, and to permit persons to whom the Software is\n# furnished to do so, subject to the following conditions:\n#\n# The above copyright notice and this permission notice shall be included in\n# all copies or substantial portions of the Software.\n#\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS\n# IN THE SOFTWARE.\n##############################################################################\n# examples of invoking this Makefile:\n# make -f nucleo-l053r8.mak\n# make -f nucleo-l053r8.mak clean\n#\n# NOTE:\n# To use this Makefile on Windows, you will need the GNU make utility, which\n# is included in the QTools collection for Windows, see:\n#    https://github.com/QuantumLeaps/qtools\n#\n\n#-----------------------------------------------------------------------------\n# project and target names\n#\nPROJECT := blinky_button\nTARGET  := nucleo-l053r8\n\n#-----------------------------------------------------------------------------\n# project directories\n#\nSST_DIR      := ../../..\nSST_PORT_DIR := $(SST_DIR)/ports/arm-cm\nCMSIS_DIR    := ../../../../3rd_party/CMSIS\nTARGET_DIR   := ../../../../3rd_party/$(TARGET)\n\n# list of all source directories used by this project\nVPATH = .. \\\n\t$(SST_DIR)/src \\\n\t$(SST_PORT_DIR) \\\n\t$(TARGET_DIR) \\\n\t$(TARGET_DIR)/gnu \\\n\n# list of all include directories needed by this project\nINCLUDES  = -I. \\\n\t-I$(SST_DIR)/../include \\\n\t-I$(SST_PORT_DIR) \\\n\t-I$(CMSIS_DIR)/Include \\\n\t-I$(TARGET_DIR)\n\n#-----------------------------------------------------------------------------\n# project files\n#\n\n# assembler source files\nASM_SRCS :=\n\n# C source files\nC_SRCS := \\\n\tsystem_stm32l0xx.c \\\n\tstartup_stm32l053xx.c\n\n# C++ source files\nCPP_SRCS := \\\n\tsst0.cpp \\\n\tmain.cpp \\\n\tblinky1.cpp \\\n\tblinky3.cpp \\\n\tbutton2a.cpp \\\n\tbutton2b.cpp \\\n\tbsp_nucleo-l053r8.cpp\n\nLD_SCRIPT  := $(TARGET_DIR)/gnu/$(TARGET).ld\n\nOUTPUT    := $(PROJECT)\n\nLIB_DIRS  :=\nLIBS      :=\n\n# defines\nDEFINES   :=\n\n# ARM CPU, ARCH, FPU, and Float-ABI types...\n# ARM_CPU:   [cortex-m0 | cortex-m0plus | cortex-m1 | cortex-m3 | cortex-m4]\n# ARM_FPU:   [ | vfp]\n# FLOAT_ABI: [ | soft | softfp | hard]\n#\nARM_CPU   := -mcpu=cortex-m0plus\nARM_FPU   :=\nFLOAT_ABI :=\n\n#-----------------------------------------------------------------------------\n# GNU-ARM toolset (NOTE: You need to adjust to your machine)\n# see https://developer.arm.com/open-source/gnu-toolchain/gnu-rm/downloads\n#\nifeq ($(GNU_ARM),)\nGNU_ARM := $(QTOOLS)/gnu_arm-none-eabi\nendif\n\n# make sure that the GNU-ARM toolset exists...\nifeq (\"$(wildcard $(GNU_ARM))\",\"\")\n$(error GNU_ARM toolset not found. Please adjust the Makefile)\nendif\n\nCC    := $(GNU_ARM)/bin/arm-none-eabi-gcc\nCPP   := $(GNU_ARM)/bin/arm-none-eabi-g++\nAS    := $(GNU_ARM)/bin/arm-none-eabi-as\nLINK  := $(GNU_ARM)/bin/arm-none-eabi-g++\nBIN   := $(GNU_ARM)/bin/arm-none-eabi-objcopy\n\n##############################################################################\n# Typically you should not need to change anything below this line\n\n# basic utilities (included in QTools for Windows), see:\n#     https://www.state-machine.com/qtools\n\nMKDIR := mkdir\nRM    := rm\n\n#-----------------------------------------------------------------------------\n# build options\n#\n\n# combine all the soruces...\nC_SRCS += $(QP_SRCS)\nASM_SRCS += $(QP_ASMS)\n\nBIN_DIR := build_$(TARGET)\n\nASFLAGS = -g $(ARM_CPU) $(ARM_FPU) $(ASM_CPU) $(ASM_FPU)\n\nCFLAGS = -c -g $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -std=c99 -mthumb -Wall \\\n\t-ffunction-sections -fdata-sections \\\n\t-O $(INCLUDES) $(DEFINES)\n\nCPPFLAGS = -c -g $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -std=c++11 -mthumb -Wall \\\n\t-ffunction-sections -fdata-sections -fno-rtti -fno-exceptions \\\n\t-O $(INCLUDES) $(DEFINES)\n\nLINKFLAGS = -T$(LD_SCRIPT) $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -mthumb \\\n\t-specs=nosys.specs -specs=nano.specs \\\n\t-Wl,-Map,$(BIN_DIR)/$(OUTPUT).map,--cref,--gc-sections $(LIB_DIRS)\n\nASM_OBJS     := $(patsubst %.s,%.o,  $(notdir $(ASM_SRCS)))\nC_OBJS       := $(patsubst %.c,%.o,  $(notdir $(C_SRCS)))\nCPP_OBJS     := $(patsubst %.cpp,%.o,$(notdir $(CPP_SRCS)))\n\nTARGET_BIN   := $(BIN_DIR)/$(OUTPUT).bin\nTARGET_ELF   := $(BIN_DIR)/$(OUTPUT).elf\nASM_OBJS_EXT := $(addprefix $(BIN_DIR)/, $(ASM_OBJS))\nC_OBJS_EXT   := $(addprefix $(BIN_DIR)/, $(C_OBJS))\nC_DEPS_EXT   := $(patsubst %.o, %.d, $(C_OBJS_EXT))\nCPP_OBJS_EXT := $(addprefix $(BIN_DIR)/, $(CPP_OBJS))\nCPP_DEPS_EXT := $(patsubst %.o, %.d, $(CPP_OBJS_EXT))\n\n# create $(BIN_DIR) if it does not exist\nifeq (\"$(wildcard $(BIN_DIR))\",\"\")\n$(shell $(MKDIR) $(BIN_DIR))\nendif\n\n#-----------------------------------------------------------------------------\n# rules\n#\n\n.PHONY : run norun flash\n\nifeq ($(MAKECMDGOALS),norun)\nall : $(TARGET_BIN)\nnorun : all\nelse\nall : $(TARGET_BIN) run\nendif\n\n$(TARGET_BIN): $(TARGET_ELF)\n\t$(BIN) -O binary $< $@\n\n$(TARGET_ELF) : $(ASM_OBJS_EXT) $(C_OBJS_EXT) $(CPP_OBJS_EXT)\n\t$(LINK) $(LINKFLAGS) -o $@ $^ $(LIBS)\n\n$(BIN_DIR)/%.d : %.c\n\t$(CC) -MM -MT $(@:.d=.o) $(CFLAGS) $< > $@\n\n$(BIN_DIR)/%.d : %.cpp\n\t$(CPP) -MM -MT $(@:.d=.o) $(CPPFLAGS) $< > $@\n\n$(BIN_DIR)/%.o : %.s\n\t$(AS) $(ASFLAGS) $< -o $@\n\n$(BIN_DIR)/%.o : %.c\n\t$(CC) $(CFLAGS) $< -o $@\n\n$(BIN_DIR)/%.o : %.cpp\n\t$(CPP) $(CPPFLAGS) $< -o $@\n\n.PHONY : clean show\n\n# include dependency files only if our goal depends on their existence\nifneq ($(MAKECMDGOALS),clean)\n  ifneq ($(MAKECMDGOALS),show)\n-include $(C_DEPS_EXT) $(CPP_DEPS_EXT)\n  endif\nendif\n\n\nclean :\n\t-$(RM) $(BIN_DIR)/*.o \\\n\t$(BIN_DIR)/*.d \\\n\t$(BIN_DIR)/*.bin \\\n\t$(BIN_DIR)/*.elf \\\n\t$(BIN_DIR)/*.map\n\t\nshow:\n\t@echo PROJECT = $(PROJECT)\n\t@echo CONF = $(CONF)\n\t@echo DEFINES = $(DEFINES)\n\t@echo ASM_FPU = $(ASM_FPU)\n\t@echo ASM_SRCS = $(ASM_SRCS)\n\t@echo C_SRCS = $(C_SRCS)\n\t@echo CPP_SRCS = $(CPP_SRCS)\n\t@echo ASM_OBJS_EXT = $(ASM_OBJS_EXT)\n\t@echo C_OBJS_EXT = $(C_OBJS_EXT)\n\t@echo C_DEPS_EXT = $(C_DEPS_EXT)\n\t@echo CPP_DEPS_EXT = $(CPP_DEPS_EXT)\n\t@echo TARGET_ELF = $(TARGET_ELF)\n"
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    "path": "sst0_cpp/examples/blinky_button/iar/ek-tm4c123gxl.ewd",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<project>\n    <fileVersion>3</fileVersion>\n    <configuration>\n        <name>Debug</name>\n        <toolchain>\n            <name>ARM</name>\n        </toolchain>\n        <debug>1</debug>\n        <settings>\n            <name>C-SPY</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>32</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CInput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CEndian</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCVariant</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>MemOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MemFile</name>\n                    <state>$TOOLKIT_DIR$\\CONFIG\\debugger\\TexasInstruments\\TM4C123GH6PM.ddf</state>\n                </option>\n                <option>\n                    <name>RunToEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RunToName</name>\n                    <state>main</state>\n                </option>\n                <option>\n                    <name>CExtraOptionsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCDDFArgumentProducer</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCDownloadSuppressDownload</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCDownloadVerifyAll</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProductVersion</name>\n                    <state>9.10.2.39304</state>\n                </option>\n                <option>\n    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</option>\n                <option>\n                    <name>OCDeviceConfigMacroFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCDebuggerExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCAllMTBOptions</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCMulticoreNrOfCores</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCMulticoreWorkspace</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCMulticoreSlaveProject</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCMulticoreSlaveConfiguration</name>\n                    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<name>OCTpiuBaseOption</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>ARMSIM_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>1</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCSimDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCSimEnablePSP</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCSimPspOverrideConfig</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCSimPspConfigFile</name>\n                    <state></state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CADI_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CCadiMemory</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>Fast Model</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCADILogFileCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCADILogFileEditB</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CMSISDAP_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>4</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCIarProbeScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CMSISDAPResetList</name>\n                    <version>1</version>\n                    <state>10</state>\n                </option>\n                <option>\n                    <name>CMSISDAPHWResetDuration</name>\n                    <state>300</state>\n                </option>\n                <option>\n                    <name>CMSISDAPHWResetDelay</name>\n                    <state>200</state>\n                </option>\n                <option>\n                    <name>CMSISDAPDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CMSISDAPInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CMSISDAPInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiTargetEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPJtagSpeedList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPRestoreBreakpointsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPUpdateBreakpointsEdit</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>RDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchUndef</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchData</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchPrefetch</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchMMERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchNOCPERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchCHKERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSTATERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchBUSERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchINTERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSFERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchHARDERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiCPUEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiCPUNumber</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeCfgOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeConfig</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CMSISDAPProbeConfigRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPSelectedCPUBehaviour</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ICpuName</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCJetEmuParams</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCCMSISDAPUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCCMSISDAPUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>GDBSERVER_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>TCPIP</name>\n                    <state>aaa.bbb.ccc.ddd</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCJTagBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJTagDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJTagUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>IJET_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>9</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCIarProbeScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetResetList</name>\n                    <version>1</version>\n                    <state>10</state>\n                </option>\n                <option>\n                    <name>IjetHWResetDuration</name>\n                    <state>300</state>\n                </option>\n                <option>\n                    <name>IjetHWResetDelay</name>\n                    <state>200</state>\n                </option>\n                <option>\n                    <name>IjetPowerFromProbe</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetPowerRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>IjetInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiTargetEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetScanChainNonARMDevices</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetIRLength</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetJtagSpeedList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetProtocolRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetSwoPin</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IjetSwoPrescalerList</name>\n                    <version>1</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetRestoreBreakpointsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetUpdateBreakpointsEdit</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>RDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchUndef</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchData</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchPrefetch</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchMMERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchNOCPERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchCHKERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSTATERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchBUSERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchINTERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSFERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchHARDERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeCfgOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeConfig</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IjetProbeConfigRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiCPUEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiCPUNumber</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetSelectedCPUBehaviour</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ICpuName</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCJetEmuParams</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetPreferETB</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetTraceSettingsList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetTraceSizeList</name>\n                    <version>0</version>\n                    <state>4</state>\n                </option>\n                <option>\n                    <name>FlashBoardPathSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCIjetUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCIjetUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL3S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL3S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL3S</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>JLINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>16</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>JLinkSpeed</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCJLinkDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCJLinkHWResetDelay</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>JLinkInitialSpeed</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCDoJlinkMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCScanChainNonARMDevices</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkIRLength</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkCommRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkTCPIP</name>\n                    <state>aaa.bbb.ccc.ddd</state>\n                </option>\n                <option>\n                    <name>CCJLinkSpeedRadioV2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCUSBDevice</name>\n                    <version>1</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCRDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchUndef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchData</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchPrefetch</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCJLinkInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJLinkResetList</name>\n                    <version>6</version>\n                    <state>5</state>\n                </option>\n                <option>\n                    <name>CCJLinkInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJLinkUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCTcpIpAlt</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkTcpIpSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSwoClockAuto</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSwoClockEdit</name>\n                    <state>2000</state>\n                </option>\n                <option>\n                    <name>OCJLinkTraceSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkTraceSourceDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkDeviceName</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>LMIFTDI_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>3</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>LmiftdiSpeed</name>\n                    <state>500</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCLmiFtdiInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCLmiFtdiInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCLmiftdiUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiResetList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>NULINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>PEMICRO_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>3</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJPEMicroShowSettings</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>STLINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>8</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSTLinkInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSTLinkInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkResetList</name>\n                    <version>3</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSwoClockAuto</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSwoClockEdit</name>\n                    <state>2000</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCSTLinkDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSTLinkUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkJtagSpeedList</name>\n                    <version>2</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkDAPNumber</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSTLinkDebugAccessPortRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUseServerSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkProbeList</name>\n                    <version>1</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkTargetVccEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSTLinkTargetVoltage</name>\n                    <state>###Uninitialized###</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>THIRDPARTY_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CThirdPartyDriverDll</name>\n                    <state>###Uninitialized###</state>\n                </option>\n                <option>\n                    <name>CThirdPartyLogFileCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CThirdPartyLogFileEditB</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>OCDriverInfo</name>\n                    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  },
  {
    "path": "sst0_cpp/examples/blinky_button/iar/ek-tm4c123gxl.ewp",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<project>\n    <fileVersion>3</fileVersion>\n    <configuration>\n        <name>Debug</name>\n        <toolchain>\n            <name>ARM</name>\n        </toolchain>\n        <debug>1</debug>\n        <settings>\n            <name>General</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <version>35</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>BrowseInfoPath</name>\n                    <state>build_ek-tm4c123gxl</state>\n                </option>\n                <option>\n                    <name>ExePath</name>\n                    <state>build_ek-tm4c123gxl</state>\n                </option>\n                <option>\n                    <name>ObjPath</name>\n                    <state>build_ek-tm4c123gxl</state>\n                </option>\n                <option>\n                    <name>ListPath</name>\n                    <state>build_ek-tm4c123gxl</state>\n                </option>\n                <option>\n                    <name>GEndianMode</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>Input description</name>\n                    <state>No specifier n, no float nor long long, no scan set, no assignment suppressing, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>Output description</name>\n                    <state>No specifier a, A, no specifier n, no float nor long long, no flags, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>GOutputBinary</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGCoreOrChip</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelect</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelectSlave</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RTDescription</name>\n                    <state>Use the normal configuration of the C/C++ runtime library. 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    <option>\n                    <name>PageLength</name>\n                    <state>80</state>\n                </option>\n                <option>\n                    <name>TabSpacing</name>\n                    <state>8</state>\n                </option>\n                <option>\n                    <name>AXRef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefDefines</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefInternal</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefDual</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AOutputFile</name>\n                    <state>$FILE_BNAME$.o</state>\n                </option>\n                <option>\n                    <name>ALimitErrorsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ALimitErrorsEdit</name>\n                    <state>100</state>\n                </option>\n                <option>\n                    <name>AIgnoreStdInclude</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AUserIncludes</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AExtraOptionsCheckV2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AExtraOptionsV2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AsmNoLiteralPool</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PreInclude</name>\n                    <state></state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>OBJCOPY</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>1</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OOCOutputFormat</name>\n                    <version>3</version>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>OCOutputOverride</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OOCOutputFile</name>\n                    <state>blinky_button.bin</state>\n                </option>\n                <option>\n                    <name>OOCCommandLineProducer</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OOCObjCopyEnable</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CUSTOM</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <extensions></extensions>\n                <cmdline></cmdline>\n                <hasPrio>1</hasPrio>\n                <buildSequence>inputOutputBased</buildSequence>\n            </data>\n        </settings>\n        <settings>\n            <name>BUILDACTION</name>\n            <archiveVersion>1</archiveVersion>\n            <data>\n                <prebuild></prebuild>\n                <postbuild></postbuild>\n            </data>\n        </settings>\n        <settings>\n            <name>ILINK</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>27</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>IlinkLibIOConfig</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkInputFileSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOutputFile</name>\n                    <state>blinky_button.out</state>\n                </option>\n                <option>\n                    <name>IlinkDebugInfoEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkKeepSymbols</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySymbol</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySegment</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryAlign</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkDefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkConfigDefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkMapFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLogFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogInitialization</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogModule</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogSection</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogVeneer</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFile</name>\n                    <state>$TOOLKIT_DIR$\\config\\linker\\TexasInstruments\\TM4C123GH6.icf</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFileSlave</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkEnableRemarks</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkSuppressDiags</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsRem</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsWarn</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsErr</name>\n                    <state></state>\n                </option>\n                <option>\n                  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    <option>\n                    <name>IlinkProgramEntryLabelSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkProgramEntryLabel</name>\n                    <state>__iar_program_start</state>\n                </option>\n                <option>\n                    <name>DoFill</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>FillerByte</name>\n                    <state>0xFF</state>\n                </option>\n                <option>\n                    <name>FillerStart</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>FillerEnd</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>CrcSize</name>\n                    <version>0</version>\n                    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<name>IlinkBE8Slave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkBufferedTerminalOutput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkStdoutInterfaceSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcFullSize</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIElfToolPostProcess</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogAutoLibSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogRedirSymbols</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogUnusedFragments</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCrcReverseByteOrder</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCrcUseAsInput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptInline</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOptExceptionsAllow</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOptExceptionsForce</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCmsis</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptMergeDuplSections</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOptUseVfe</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptForceVfe</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkStackAnalysisEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkStackControlFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkStackCallGraphFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CrcAlgorithm</name>\n                    <version>1</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcUnitSize</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkThreadsSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLogCallGraph</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFile_AltDefault</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkEncInput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutputBom</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkHeapSelect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLocaleSelect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkTrustzoneImportLibraryOut</name>\n                    <state>iar_ek-tm4c123gxl_import_lib.o</state>\n                </option>\n                <option>\n                    <name>OILinkExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryFile2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySymbol2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySegment2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryAlign2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkLogCrtRoutineSelection</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogFragmentInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogInlining</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogMerging</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkDemangle</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkWrapperFileEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkWrapperFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkFpuProcessor</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>IARCHIVE</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>IarchiveInputs</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IarchiveOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IarchiveOutput</name>\n                    <state>###Unitialized###</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>Coder</name>\n            <archiveVersion>0</archiveVersion>\n            <data />\n        </settings>\n    </configuration>\n    <group>\n        <name>Application</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\blinky1.cpp</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\blinky3.cpp</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\bsp.hpp</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\bsp_ek-tm4c123gxl.cpp</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\button2a.cpp</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\button2b.cpp</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\main.cpp</name>\n        </file>\n    </group>\n    <group>\n        <name>ek-tm4c123gxl</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\ek-tm4c123gxl\\iar\\startup_TM4C123GH6PM.s</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\ek-tm4c123gxl\\system_TM4C123GH6PM.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\ek-tm4c123gxl\\TM4C123GH6PM.h</name>\n        </file>\n    </group>\n    <group>\n        <name>sst</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\src\\sst0.cpp</name>\n        </file>\n    </group>\n    <group>\n        <name>sst_port</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\ports\\arm-cm\\sst_port.hpp</name>\n        </file>\n    </group>\n</project>\n"
  },
  {
    "path": "sst0_cpp/examples/blinky_button/iar/ek-tm4c123gxl.eww",
    "content": "<?xml version=\"1.0\" encoding=\"iso-8859-1\"?>\n\n<workspace>\n  <project>\n    <path>$WS_DIR$\\ek-tm4c123gxl.ewp</path>\n  </project>\n  <batchBuild/>\n</workspace>\n\n\n"
  },
  {
    "path": "sst0_cpp/examples/blinky_button/iar/nucleo-c031c6.ewd",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<project>\n    <fileVersion>3</fileVersion>\n    <configuration>\n        <name>Debug</name>\n        <toolchain>\n            <name>ARM</name>\n        </toolchain>\n        <debug>1</debug>\n        <settings>\n            <name>C-SPY</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>32</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CInput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CEndian</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCVariant</name>\n                    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</option>\n                <option>\n                    <name>CExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCDDFArgumentProducer</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCDownloadSuppressDownload</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCDownloadVerifyAll</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProductVersion</name>\n                    <state>9.32.1.54977</state>\n                </option>\n                <option>\n                    <name>OCDynDriverList</name>\n                    <state>STLINK_ID</state>\n                </option>\n                <option>\n                    <name>OCLastSavedByProductVersion</name>\n                    <state>9.32.1.54977</state>\n                </option>\n                <option>\n                    <name>UseFlashLoader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CLowLevel</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCBE8Slave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacFile2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CDevice</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>FlashLoadersV3</name>\n                    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<name>OCDeviceConfigMacroFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCDebuggerExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCAllMTBOptions</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCMulticoreNrOfCores</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCMulticoreWorkspace</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCMulticoreSlaveProject</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCMulticoreSlaveConfiguration</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCDownloadExtraImage</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCAttachSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MassEraseBeforeFlashing</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCMulticoreNrOfCoresSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCMulticoreAMPConfigType</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCMulticoreSessionFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCTpiuBaseOption</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>ARMSIM_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>1</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCSimDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCSimEnablePSP</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCSimPspOverrideConfig</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCSimPspConfigFile</name>\n                    <state></state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CADI_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CCadiMemory</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>Fast Model</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCADILogFileCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCADILogFileEditB</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CMSISDAP_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>4</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCIarProbeScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CMSISDAPResetList</name>\n                    <version>1</version>\n                    <state>10</state>\n                </option>\n                <option>\n                    <name>CMSISDAPHWResetDuration</name>\n                    <state>300</state>\n                </option>\n                <option>\n                    <name>CMSISDAPHWResetDelay</name>\n                    <state>200</state>\n                </option>\n                <option>\n                    <name>CMSISDAPDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CMSISDAPInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CMSISDAPInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiTargetEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPJtagSpeedList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPRestoreBreakpointsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPUpdateBreakpointsEdit</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>RDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchUndef</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchData</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchPrefetch</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchMMERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchNOCPERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchCHKERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSTATERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchBUSERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchINTERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSFERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchHARDERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiCPUEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiCPUNumber</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeCfgOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeConfig</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CMSISDAPProbeConfigRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPSelectedCPUBehaviour</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ICpuName</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCJetEmuParams</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCCMSISDAPUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCCMSISDAPUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>GDBSERVER_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>TCPIP</name>\n                    <state>aaa.bbb.ccc.ddd</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCJTagBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJTagDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJTagUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>IJET_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>9</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCIarProbeScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetResetList</name>\n                    <version>1</version>\n                    <state>10</state>\n                </option>\n                <option>\n                    <name>IjetHWResetDuration</name>\n                    <state>300</state>\n                </option>\n                <option>\n                    <name>IjetHWResetDelay</name>\n                    <state>200</state>\n                </option>\n                <option>\n                    <name>IjetPowerFromProbe</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetPowerRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>IjetInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiTargetEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetScanChainNonARMDevices</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetIRLength</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetJtagSpeedList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetProtocolRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetSwoPin</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IjetSwoPrescalerList</name>\n                    <version>1</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetRestoreBreakpointsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetUpdateBreakpointsEdit</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>RDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchUndef</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchData</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchPrefetch</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchMMERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchNOCPERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchCHKERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSTATERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchBUSERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchINTERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSFERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchHARDERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeCfgOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeConfig</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IjetProbeConfigRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiCPUEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiCPUNumber</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetSelectedCPUBehaviour</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ICpuName</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCJetEmuParams</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetPreferETB</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetTraceSettingsList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetTraceSizeList</name>\n                    <version>0</version>\n                    <state>4</state>\n                </option>\n                <option>\n                    <name>FlashBoardPathSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCIjetUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCIjetUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL3S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL3S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL3S</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>JLINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>16</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>JLinkSpeed</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCJLinkDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCJLinkHWResetDelay</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>JLinkInitialSpeed</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCDoJlinkMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCScanChainNonARMDevices</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkIRLength</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkCommRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkTCPIP</name>\n                    <state>aaa.bbb.ccc.ddd</state>\n                </option>\n                <option>\n                    <name>CCJLinkSpeedRadioV2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCUSBDevice</name>\n                    <version>1</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCRDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchUndef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchData</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchPrefetch</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCJLinkInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJLinkResetList</name>\n                    <version>6</version>\n                    <state>5</state>\n                </option>\n                <option>\n                    <name>CCJLinkInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJLinkUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCTcpIpAlt</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkTcpIpSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSwoClockAuto</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSwoClockEdit</name>\n                    <state>2000</state>\n                </option>\n                <option>\n                    <name>OCJLinkTraceSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkTraceSourceDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkDeviceName</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>LMIFTDI_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>3</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>LmiftdiSpeed</name>\n                    <state>500</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCLmiFtdiInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCLmiFtdiInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCLmiftdiUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiResetList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>NULINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>PEMICRO_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>3</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJPEMicroShowSettings</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>STLINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>8</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSTLinkInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSTLinkInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkResetList</name>\n                    <version>3</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSwoClockAuto</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSwoClockEdit</name>\n                    <state>2000</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCSTLinkDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSTLinkUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkJtagSpeedList</name>\n                    <version>2</version>\n                    <state>0</state>\n                </option>\n                <option>\n            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  },
  {
    "path": "sst0_cpp/examples/blinky_button/iar/nucleo-c031c6.ewp",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<project>\n    <fileVersion>3</fileVersion>\n    <configuration>\n        <name>Debug</name>\n        <toolchain>\n            <name>ARM</name>\n        </toolchain>\n        <debug>1</debug>\n        <settings>\n            <name>General</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <version>35</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>BrowseInfoPath</name>\n                    <state>build_nucleo-c031c6</state>\n                </option>\n                <option>\n                    <name>ExePath</name>\n                    <state>build_nucleo-c031c6</state>\n                </option>\n                <option>\n                    <name>ObjPath</name>\n                    <state>build_nucleo-c031c6</state>\n                </option>\n                <option>\n                    <name>ListPath</name>\n                    <state>build_nucleo-c031c6</state>\n                </option>\n                <option>\n                    <name>GEndianMode</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>Input description</name>\n                    <state>No specifier n, no float nor long long, no scan set, no assignment suppressing, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>Output description</name>\n                    <state>No specifier a, A, no specifier n, no float nor long long, no flags, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>GOutputBinary</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGCoreOrChip</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelect</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelectSlave</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RTDescription</name>\n                    <state>A compact configuration of the C/C++14 runtime library. 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<state>blinky_button.bin</state>\n                </option>\n                <option>\n                    <name>OOCCommandLineProducer</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OOCObjCopyEnable</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CUSTOM</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <extensions></extensions>\n                <cmdline></cmdline>\n                <hasPrio>1</hasPrio>\n                <buildSequence>inputOutputBased</buildSequence>\n            </data>\n        </settings>\n        <settings>\n            <name>BUILDACTION</name>\n            <archiveVersion>1</archiveVersion>\n            <data>\n                <prebuild></prebuild>\n                <postbuild></postbuild>\n            </data>\n        </settings>\n        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  </option>\n                <option>\n                    <name>IarchiveOutput</name>\n                    <state>###Unitialized###</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>Coder</name>\n            <archiveVersion>0</archiveVersion>\n            <data />\n        </settings>\n    </configuration>\n    <mfc>\n        <configuration>Debug</configuration>\n    </mfc>\n    <group>\n        <name>Application</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\blinky1.cpp</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\blinky3.cpp</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\blinky_button.hpp</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\bsp.hpp</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\bsp_nucleo-c031c6.cpp</name>\n        </file>\n        <file>\n            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<group>\n        <name>sst_port</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\ports\\arm-cm\\sst_port.hpp</name>\n        </file>\n    </group>\n</project>\n"
  },
  {
    "path": "sst0_cpp/examples/blinky_button/iar/nucleo-c031c6.eww",
    "content": "<?xml version=\"1.0\" encoding=\"iso-8859-1\"?>\n\n<workspace>\n  <project>\n    <path>$WS_DIR$\\nucleo-c031c6.ewp</path>\n  </project>\n  <batchBuild/>\n</workspace>\n\n\n"
  },
  {
    "path": "sst0_cpp/examples/blinky_button/iar/nucleo-h743zi.ewd",
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          <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CCadiMemory</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>Fast Model</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCADILogFileCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCADILogFileEditB</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CMSISDAP_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>4</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCIarProbeScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CMSISDAPResetList</name>\n                    <version>1</version>\n                    <state>10</state>\n                </option>\n                <option>\n                    <name>CMSISDAPHWResetDuration</name>\n                    <state>300</state>\n                </option>\n                <option>\n                    <name>CMSISDAPHWResetDelay</name>\n                    <state>200</state>\n                </option>\n                <option>\n                    <name>CMSISDAPDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CMSISDAPInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CMSISDAPInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiTargetEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPJtagSpeedList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPRestoreBreakpointsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPUpdateBreakpointsEdit</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>RDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchUndef</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchData</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchPrefetch</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchMMERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchNOCPERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchCHKERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSTATERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchBUSERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchINTERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSFERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchHARDERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiCPUEnable</name>\n     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<name>OCJetEmuParams</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCCMSISDAPUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCCMSISDAPUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>GDBSERVER_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>TCPIP</name>\n                    <state>aaa.bbb.ccc.ddd</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCJTagBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJTagDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJTagUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>IJET_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>9</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n      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<state>0</state>\n                </option>\n                <option>\n                    <name>IjetDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>IjetInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiTargetEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetScanChainNonARMDevices</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetIRLength</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetJtagSpeedList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetProtocolRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetSwoPin</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IjetSwoPrescalerList</name>\n                    <version>1</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetRestoreBreakpointsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetUpdateBreakpointsEdit</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>RDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchUndef</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchData</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchPrefetch</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchMMERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchNOCPERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchCHKERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSTATERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchBUSERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchINTERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSFERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchHARDERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeCfgOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeConfig</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IjetProbeConfigRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiCPUEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiCPUNumber</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetSelectedCPUBehaviour</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ICpuName</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCJetEmuParams</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetPreferETB</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetTraceSettingsList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetTraceSizeList</name>\n                    <version>0</version>\n                    <state>4</state>\n                </option>\n                <option>\n                    <name>FlashBoardPathSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCIjetUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCIjetUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL3S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL3S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL3S</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>JLINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>16</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>JLinkSpeed</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCJLinkDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCJLinkHWResetDelay</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>JLinkInitialSpeed</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCDoJlinkMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCScanChainNonARMDevices</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkIRLength</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkCommRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkTCPIP</name>\n                    <state>aaa.bbb.ccc.ddd</state>\n                </option>\n                <option>\n                    <name>CCJLinkSpeedRadioV2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCUSBDevice</name>\n                    <version>1</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCRDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchUndef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchData</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchPrefetch</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCJLinkInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJLinkResetList</name>\n                    <version>6</version>\n                    <state>5</state>\n                </option>\n                <option>\n                    <name>CCJLinkInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJLinkUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCTcpIpAlt</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkTcpIpSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSwoClockAuto</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSwoClockEdit</name>\n                    <state>2000</state>\n                </option>\n                <option>\n                    <name>OCJLinkTraceSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkTraceSourceDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkDeviceName</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>LMIFTDI_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>3</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>LmiftdiSpeed</name>\n                    <state>500</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCLmiFtdiInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCLmiFtdiInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCLmiftdiUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiResetList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>NULINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>PEMICRO_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>3</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJPEMicroShowSettings</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>STLINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>8</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSTLinkInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSTLinkInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkResetList</name>\n                    <version>3</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCpuClockEdit</name>\n                    <state>480</state>\n                </option>\n                <option>\n                    <name>CCSwoClockAuto</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSwoClockEdit</name>\n                    <state>2000</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCSTLinkDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSTLinkUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    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  },
  {
    "path": "sst0_cpp/examples/blinky_button/iar/nucleo-h743zi.ewp",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<project>\n    <fileVersion>3</fileVersion>\n    <configuration>\n        <name>Debug</name>\n        <toolchain>\n            <name>ARM</name>\n        </toolchain>\n        <debug>1</debug>\n        <settings>\n            <name>General</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <version>35</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>BrowseInfoPath</name>\n                    <state>build_nucleo-h743zi</state>\n                </option>\n                <option>\n                    <name>ExePath</name>\n                    <state>build_nucleo-h743zi</state>\n                </option>\n                <option>\n                    <name>ObjPath</name>\n                    <state>build_nucleo-h743zi</state>\n                </option>\n                <option>\n                    <name>ListPath</name>\n                    <state>build_nucleo-h743zi</state>\n                </option>\n                <option>\n                    <name>GEndianMode</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>Input description</name>\n                    <state>No specifier n, no float nor long long, no scan set, no assignment suppressing, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>Output description</name>\n                    <state>No specifier a, A, no specifier n, no float nor long long, no flags, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>GOutputBinary</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGCoreOrChip</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelect</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelectSlave</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RTDescription</name>\n                    <state>Use the normal configuration of the C/C++ runtime library. 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<option>\n                    <name>OG_32_64Device</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>BuildFilesPath</name>\n                    <state>Debug</state>\n                </option>\n                <option>\n                    <name>PointerAuthentication</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>FPU64</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>ICCARM</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>37</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CCOptimizationNoSizeConstraints</name>\n                    <state>0</state>\n                </option>\n              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                 <name>CCListAssFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListAssSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEnableRemarks</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCDiagSuppress</name>\n                    <state>Pa050</state>\n                </option>\n                <option>\n                    <name>CCDiagRemark</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagWarning</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagError</name>\n                    <state></state>\n                </option>\n                <option>\n                    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  <state>80</state>\n                </option>\n                <option>\n                    <name>TabSpacing</name>\n                    <state>8</state>\n                </option>\n                <option>\n                    <name>AXRef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefDefines</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefInternal</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefDual</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AOutputFile</name>\n                    <state>$FILE_BNAME$.o</state>\n                </option>\n                <option>\n                    <name>ALimitErrorsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ALimitErrorsEdit</name>\n                    <state>100</state>\n                </option>\n                <option>\n                    <name>AIgnoreStdInclude</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AUserIncludes</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AExtraOptionsCheckV2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AExtraOptionsV2</name>\n                    <state></state>\n             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<state>blinky_button.bin</state>\n                </option>\n                <option>\n                    <name>OOCCommandLineProducer</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OOCObjCopyEnable</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CUSTOM</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <extensions></extensions>\n                <cmdline></cmdline>\n                <hasPrio>1</hasPrio>\n                <buildSequence>inputOutputBased</buildSequence>\n            </data>\n        </settings>\n        <settings>\n            <name>BUILDACTION</name>\n            <archiveVersion>1</archiveVersion>\n            <data>\n                <prebuild></prebuild>\n                <postbuild></postbuild>\n            </data>\n        </settings>\n        <settings>\n            <name>ILINK</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>27</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>IlinkLibIOConfig</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkInputFileSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOutputFile</name>\n                    <state>blinky_button.out</state>\n                </option>\n                <option>\n                    <name>IlinkDebugInfoEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkKeepSymbols</name>\n                    <state></state>\n                </option>\n                <option>\n           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    <name>IlinkLogFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogInitialization</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogModule</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogSection</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogVeneer</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFile</name>\n                    <state>$TOOLKIT_DIR$\\config\\linker\\ST\\stm32h743xI.icf</state>\n                </option>\n       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<name>CrcUnitSize</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkThreadsSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLogCallGraph</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFile_AltDefault</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkEncInput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutputBom</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkHeapSelect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLocaleSelect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkTrustzoneImportLibraryOut</name>\n                    <state>iar_nucleo-h743zi_import_lib.o</state>\n                </option>\n                <option>\n                    <name>OILinkExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryFile2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySymbol2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySegment2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryAlign2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkLogCrtRoutineSelection</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogFragmentInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogInlining</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogMerging</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkDemangle</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkWrapperFileEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkWrapperFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkFpuProcessor</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>IARCHIVE</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>IarchiveInputs</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IarchiveOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IarchiveOutput</name>\n                    <state>###Unitialized###</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>Coder</name>\n            <archiveVersion>0</archiveVersion>\n            <data />\n        </settings>\n    </configuration>\n    <mfc>\n        <configuration>Debug</configuration>\n    </mfc>\n    <group>\n        <name>Application</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\blinky1.cpp</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\blinky3.cpp</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\blinky_button.hpp</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\bsp.hpp</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\bsp_nucleo-h743zi.cpp</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\button2a.cpp</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\button2b.cpp</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\main.cpp</name>\n        </file>\n    </group>\n    <group>\n        <name>nucleo-h743zi</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\nucleo-h743zi\\iar\\startup_stm32h743xx.s</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\nucleo-h743zi\\stm32h743xx.h</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\nucleo-h743zi\\system_stm32h7xx.c</name>\n        </file>\n    </group>\n    <group>\n        <name>sst</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\src\\sst0.cpp</name>\n        </file>\n    </group>\n    <group>\n        <name>sst_port</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\ports\\arm-cm\\sst_port.hpp</name>\n        </file>\n    </group>\n</project>\n"
  },
  {
    "path": "sst0_cpp/examples/blinky_button/iar/nucleo-h743zi.eww",
    "content": "<?xml version=\"1.0\" encoding=\"iso-8859-1\"?>\n\n<workspace>\n  <project>\n    <path>$WS_DIR$\\nucleo-h743zi.ewp</path>\n  </project>\n  <batchBuild/>\n</workspace>\n\n\n"
  },
  {
    "path": "sst0_cpp/examples/blinky_button/iar/nucleo-l053r8.ewd",
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<name>OCDynDriverList</name>\n                    <state>STLINK_ID</state>\n                </option>\n                <option>\n                    <name>OCLastSavedByProductVersion</name>\n                    <state>9.32.1.54977</state>\n                </option>\n                <option>\n                    <name>UseFlashLoader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CLowLevel</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCBE8Slave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacFile2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CDevice</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    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<state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>ARMSIM_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>1</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCSimDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCSimEnablePSP</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCSimPspOverrideConfig</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCSimPspConfigFile</name>\n                    <state></state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CADI_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CCadiMemory</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>Fast Model</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCADILogFileCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCADILogFileEditB</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CMSISDAP_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>4</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCIarProbeScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CMSISDAPResetList</name>\n                    <version>1</version>\n                    <state>10</state>\n                </option>\n                <option>\n                    <name>CMSISDAPHWResetDuration</name>\n                    <state>300</state>\n                </option>\n                <option>\n                    <name>CMSISDAPHWResetDelay</name>\n                    <state>200</state>\n                </option>\n                <option>\n                    <name>CMSISDAPDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CMSISDAPInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CMSISDAPInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiTargetEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPJtagSpeedList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPRestoreBreakpointsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPUpdateBreakpointsEdit</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>RDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchUndef</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchData</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchPrefetch</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchMMERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchNOCPERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchCHKERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSTATERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchBUSERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchINTERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSFERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchHARDERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiCPUEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiCPUNumber</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeCfgOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeConfig</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CMSISDAPProbeConfigRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPSelectedCPUBehaviour</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ICpuName</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCJetEmuParams</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCCMSISDAPUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCCMSISDAPUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>GDBSERVER_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>TCPIP</name>\n                    <state>aaa.bbb.ccc.ddd</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCJTagBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJTagDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJTagUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>IJET_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>9</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCIarProbeScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetResetList</name>\n                    <version>1</version>\n                    <state>10</state>\n                </option>\n                <option>\n                    <name>IjetHWResetDuration</name>\n                    <state>300</state>\n                </option>\n                <option>\n                    <name>IjetHWResetDelay</name>\n                    <state>200</state>\n                </option>\n                <option>\n                    <name>IjetPowerFromProbe</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetPowerRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>IjetInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiTargetEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetScanChainNonARMDevices</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetIRLength</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetJtagSpeedList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetProtocolRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetSwoPin</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IjetSwoPrescalerList</name>\n                    <version>1</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetRestoreBreakpointsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetUpdateBreakpointsEdit</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>RDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchUndef</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchData</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchPrefetch</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchMMERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchNOCPERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchCHKERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSTATERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchBUSERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchINTERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSFERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchHARDERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeCfgOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeConfig</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IjetProbeConfigRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiCPUEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiCPUNumber</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetSelectedCPUBehaviour</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ICpuName</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCJetEmuParams</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetPreferETB</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetTraceSettingsList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetTraceSizeList</name>\n                    <version>0</version>\n                    <state>4</state>\n                </option>\n                <option>\n                    <name>FlashBoardPathSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCIjetUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCIjetUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL3S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL3S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL3S</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>JLINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>16</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>JLinkSpeed</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCJLinkDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCJLinkHWResetDelay</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>JLinkInitialSpeed</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCDoJlinkMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCScanChainNonARMDevices</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkIRLength</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkCommRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkTCPIP</name>\n                    <state>aaa.bbb.ccc.ddd</state>\n                </option>\n                <option>\n                    <name>CCJLinkSpeedRadioV2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCUSBDevice</name>\n                    <version>1</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCRDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchUndef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchData</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchPrefetch</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCJLinkInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJLinkResetList</name>\n                    <version>6</version>\n                    <state>5</state>\n                </option>\n                <option>\n                    <name>CCJLinkInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJLinkUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCTcpIpAlt</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkTcpIpSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSwoClockAuto</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSwoClockEdit</name>\n                    <state>2000</state>\n                </option>\n                <option>\n                    <name>OCJLinkTraceSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkTraceSourceDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkDeviceName</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>LMIFTDI_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>3</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>LmiftdiSpeed</name>\n                    <state>500</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCLmiFtdiInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCLmiFtdiInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCLmiftdiUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiResetList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>NULINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>PEMICRO_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>3</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJPEMicroShowSettings</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>STLINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>8</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSTLinkInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSTLinkInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkResetList</name>\n                    <version>3</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSwoClockAuto</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSwoClockEdit</name>\n                    <state>2000</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCSTLinkDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSTLinkUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkJtagSpeedList</name>\n                    <version>2</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkDAPNumber</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSTLinkDebugAccessPortRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUseServerSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkProbeList</name>\n                    <version>1</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkTargetVccEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    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<name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>TIPackageOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TIPackage</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>BoardFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCXds100BreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100DoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100UpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchUndef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchData</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchPrefetch</name>\n                    <state>0</state>\n                </option>\n              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 </option>\n                <option>\n                    <name>CCXds100SwoClockEdit</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCXds100HWResetDelay</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100ResetList</name>\n                    <version>1</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100UsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCXds100UsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100JtagSpeedList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100InterfaceRadio</name>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCXds100InterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100ProbeList</name>\n                    <version>0</version>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>CCXds100SWOPortRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100SWOPort</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCXDSTargetVccEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXDSTargetVoltage</name>\n                    <state>###Uninitialized###</state>\n                </option>\n                <option>\n                    <name>OCXDSDigitalStatesConfigFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCSelectedCoreName</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <debuggerPlugins>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\CMX\\CmxArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\CMX\\CmxTinyArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\embOS\\embOSPlugin.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\FreeRtos\\FreeRtosArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\Mbed\\MbedArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\Mbed\\MbedArmPlugin2.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\OpenRTOS\\OpenRTOSPlugin.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\SafeRTOS\\SafeRTOSPlugin.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\SMX\\smxAwareIarArm9.ewplugin</file>\n                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  },
  {
    "path": "sst0_cpp/examples/blinky_button/iar/nucleo-l053r8.ewp",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<project>\n    <fileVersion>3</fileVersion>\n    <configuration>\n        <name>Debug</name>\n        <toolchain>\n            <name>ARM</name>\n        </toolchain>\n        <debug>1</debug>\n        <settings>\n            <name>General</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <version>35</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>BrowseInfoPath</name>\n                    <state>build_nucleo-l053r8</state>\n                </option>\n                <option>\n                    <name>ExePath</name>\n                    <state>build_nucleo-l053r8</state>\n                </option>\n                <option>\n                    <name>ObjPath</name>\n                    <state>build_nucleo-l053r8</state>\n                </option>\n                <option>\n                    <name>ListPath</name>\n                    <state>build_nucleo-l053r8</state>\n                </option>\n                <option>\n                    <name>GEndianMode</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>Input description</name>\n                    <state>No specifier n, no float nor long long, no scan set, no assignment suppressing, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>Output description</name>\n                    <state>No specifier a, A, no specifier n, no float nor long long, no flags, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>GOutputBinary</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGCoreOrChip</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelect</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelectSlave</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RTDescription</name>\n                    <state>Use the normal configuration of the C/C++ runtime library. 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     <name>OGScanfMultibyteSupport</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GenLocaleTags</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>GenLocaleDisplayOnly</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DSPExtension</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TrustZone</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TrustZoneModes</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGAarch64Abi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OG_32_64Device</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>BuildFilesPath</name>\n                    <state>Debug</state>\n                </option>\n                <option>\n                    <name>PointerAuthentication</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>FPU64</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>ICCARM</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>37</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CCOptimizationNoSizeConstraints</name>\n                    <state>0</state>\n                </option>\n              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      <name>CCListAssFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListAssSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEnableRemarks</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCDiagSuppress</name>\n                    <state>Pa050</state>\n                </option>\n                <option>\n                    <name>CCDiagRemark</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagWarning</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagError</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCObjPrefix</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCAllowList</name>\n                    <version>1</version>\n                    <state>10010100</state>\n                </option>\n                <option>\n                    <name>CCDebugInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IEndianMode</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IExtraOptionsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n      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            <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkWrapperFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkFpuProcessor</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>IARCHIVE</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>IarchiveInputs</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IarchiveOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IarchiveOutput</name>\n                    <state>###Unitialized###</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>Coder</name>\n            <archiveVersion>0</archiveVersion>\n            <data />\n        </settings>\n    </configuration>\n    <mfc>\n        <configuration>Debug</configuration>\n    </mfc>\n    <group>\n        <name>Application</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\blinky1.cpp</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\blinky3.cpp</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\blinky_button.hpp</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\bsp.hpp</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\bsp_nucleo-l053r8.cpp</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\button2a.cpp</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\button2b.cpp</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\main.cpp</name>\n        </file>\n    </group>\n    <group>\n        <name>nucleo-l053r8</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\nucleo-l053r8\\iar\\startup_stm32l053xx.s</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\nucleo-l053r8\\stm32l053xx.h</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\nucleo-l053r8\\system_stm32l0xx.c</name>\n        </file>\n    </group>\n    <group>\n        <name>sst</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\src\\sst0.cpp</name>\n        </file>\n    </group>\n    <group>\n        <name>sst_port</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\ports\\arm-cm\\sst_port.hpp</name>\n        </file>\n    </group>\n</project>\n"
  },
  {
    "path": "sst0_cpp/examples/blinky_button/iar/nucleo-l053r8.eww",
    "content": "<?xml version=\"1.0\" encoding=\"iso-8859-1\"?>\n\n<workspace>\n  <project>\n    <path>$WS_DIR$\\nucleo-l053r8.ewp</path>\n  </project>\n  <batchBuild/>\n</workspace>\n\n\n"
  },
  {
    "path": "sst0_cpp/examples/blinky_button/main.cpp",
    "content": "//============================================================================\n// Super-Simple Tasker (SST0/C++) Example\n//\n// Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n//\n// SPDX-License-Identifier: MIT\n//\n// Permission is hereby granted, free of charge, to any person obtaining a\n// copy of this software and associated documentation files (the \"Software\"),\n// to deal in the Software without restriction, including without limitation\n// the rights to use, copy, modify, merge, publish, distribute, sublicense,\n// and/or sell copies of the Software, and to permit persons to whom the\n// Software is furnished to do so, subject to the following conditions:\n//\n// The above copyright notice and this permission notice shall be included in\n// all copies or substantial portions of the Software.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n// DEALINGS IN THE SOFTWARE.\n//============================================================================\n#include \"sst.hpp\"           // SST framework\n#include \"bsp.hpp\"           // Board Support Package interface\n#include \"blinky_button.hpp\" // application shared interface\n\n//............................................................................\nint main() {\n    SST::init(); // initialize the SST kernel\n    BSP::init(); // initialize the Board Support Package\n\n    // instantiate and start all SST tasks...\n    static SST::Evt const *blinky1QSto[10]; // Event queue storage\n    App::AO_Blinky1->start(\n        1U,           // SST-priority\n        blinky1QSto,  // storage for the AO's queue\n        ARRAY_NELEM(blinky1QSto), // queue length\n        BSP::getWorkEvtBlinky1(0U)); // initialization event\n\n    static SST::Evt const *button2aQSto[8]; // Event queue storage\n    App::AO_Button2a->start(\n        2U,           // SST-priority\n        button2aQSto, // storage for the AO's queue\n        ARRAY_NELEM(button2aQSto), // queue length\n        nullptr);     // initialization event\n\n    static SST::Evt const *button2bQSto[6]; // Event queue storage\n    App::AO_Button2b->start(\n        3U,           // SST-priority\n        button2bQSto, // storage for the AO's queue\n        ARRAY_NELEM(button2bQSto), // queue length\n        nullptr);     // initialization event\n\n    static SST::Evt const *blinky3QSto[4]; // Event queue storage\n    App::AO_Blinky3->start(\n        4U,           // SST-priority\n        blinky3QSto,  // storage for the AO's queue\n        ARRAY_NELEM(blinky3QSto), // queue length\n        BSP::getWorkEvtBlinky3(0U)); // initialization event\n\n    return SST::Task::run(); // run the SST tasks\n    // NOTE: in embedded systems SST::Task::run() should not return\n}\n\n"
  },
  {
    "path": "sst0_cpp/ports/arm-cm/sst_port.hpp",
    "content": "//============================================================================\n// Super-Simple Tasker (SST0/C++) port\n//\n// Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n//\n// SPDX-License-Identifier: MIT\n//\n// Permission is hereby granted, free of charge, to any person obtaining a\n// copy of this software and associated documentation files (the \"Software\"),\n// to deal in the Software without restriction, including without limitation\n// the rights to use, copy, modify, merge, publish, distribute, sublicense,\n// and/or sell copies of the Software, and to permit persons to whom the\n// Software is furnished to do so, subject to the following conditions:\n//\n// The above copyright notice and this permission notice shall be included in\n// all copies or substantial portions of the Software.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n// DEALINGS IN THE SOFTWARE.\n//============================================================================\n#ifndef SST_PORT_HPP_\n#define SST_PORT_HPP_\n\n#define SST_PORT_MAX_TASK 32U\n\n// additional SST-PORT task attributes for ARM Cortex-M\n#define SST_PORT_TASK_ATTR \\\n    SST::TaskPrio m_prio;\n\n// SST-PORT disabling/enabling interrupts\n#define SST_PORT_INT_DISABLE() __asm volatile (\"cpsid i\")\n#define SST_PORT_INT_ENABLE()  __asm volatile (\"cpsie i\")\n\n// SST-PORT critical section\n#define SST_PORT_CRIT_STAT\n#define SST_PORT_CRIT_ENTRY() SST_PORT_INT_DISABLE()\n#define SST_PORT_CRIT_EXIT()  SST_PORT_INT_ENABLE()\n\nnamespace SST {\n    using ReadySet = std::uint32_t;\n\n    //! SST lock key\n    using LockKey = std::uint32_t;\n\n    // special idle callback to handle the \"idle condition\" in SST0\n    void onIdleCond(void);\n}\n\n#if (__ARM_ARCH == 6) // ARMv6-M?\n\n// SST_LOG2() implementation for ARMv6-M (no CLZ instruction)\ninline std::uint_fast8_t SST_LOG2(std::uint32_t x) {\n    static std::uint8_t const log2LUT[16] = {\n        0U, 1U, 2U, 2U, 3U, 3U, 3U, 3U,\n        4U, 4U, 4U, 4U, 4U, 4U, 4U, 4U\n    };\n    std::uint_fast8_t n = 0U;\n    SST::ReadySet tmp;\n\n    #if (SST_PORT_MAX_TASK > 16U)\n    tmp = static_cast<std::uint32_t>(x >> 16U);\n    if (tmp != 0U) {\n        n += 16U;\n        x = tmp;\n    }\n    #endif\n    #if (SST_PORT_MAX_TASK > 8U)\n    tmp = (x >> 8U);\n    if (tmp != 0U) {\n        n += 8U;\n        x = tmp;\n    }\n    #endif\n    tmp = (x >> 4U);\n    if (tmp != 0U) {\n        n += 4U;\n        x = tmp;\n    }\n    return n + log2LUT[x];\n}\n\n#else // ARMv7-M+ have CLZ instruction for fast LOG2 computations\n\n// ARMv7-M+ have CLZ instruction for fast LOG2 computations\n#if defined __ARMCC_VERSION\n    #define SST_LOG2(x_) \\\n        (static_cast<std::uint_fast8_t>(32U - __builtin_clz((unsigned)(x_))))\n#elif defined __GNUC__\n    #define SST_LOG2(x_) \\\n        (static_cast<std::uint_fast8_t>(32U - __builtin_clz((unsigned)(x_))))\n#elif defined __ICCARM__\n    #include <intrinsics.h>\n    #define SST_LOG2(x_) \\\n        (static_cast<std::uint_fast8_t>(32U - __CLZ((unsigned long)(x_))))\n#endif /* compiler type */\n\n#endif\n\n#endif // SST_PORT_HPP_\n"
  },
  {
    "path": "sst0_cpp/src/sst0.cpp",
    "content": "//============================================================================\n// Super-Simple Tasker (SST0/C++) port\n//\n// Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n//\n// SPDX-License-Identifier: MIT\n//\n// Permission is hereby granted, free of charge, to any person obtaining a\n// copy of this software and associated documentation files (the \"Software\"),\n// to deal in the Software without restriction, including without limitation\n// the rights to use, copy, modify, merge, publish, distribute, sublicense,\n// and/or sell copies of the Software, and to permit persons to whom the\n// Software is furnished to do so, subject to the following conditions:\n//\n// The above copyright notice and this permission notice shall be included in\n// all copies or substantial portions of the Software.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n// DEALINGS IN THE SOFTWARE.\n//============================================================================\n#include \"sst.hpp\"      // Super-Simple Tasker (SST) in C++\n#include \"dbc_assert.h\" // Design By Contract (DBC) assertions\n\n//............................................................................\nnamespace { // unnamed namespace\n\nDBC_MODULE_NAME(\"sst0\") // for DBC assertions in this module\n\nstatic SST::ReadySet task_readySet;\n\n// array of all SST task pointers in the system\nstatic SST::Task *task_registry[SST_PORT_MAX_TASK + 1U];\n\n} // unnamed namespace\n\nnamespace SST {\n\n// SST kernel facilities -----------------------------------------------------\nvoid init(void) {\n}\n//............................................................................\nint Task::run(void) { // static\n    onStart(); // configure and start the interrupts\n\n    SST_PORT_INT_DISABLE();\n    for (;;) { // event loop of the SST0 kernel\n\n        if (task_readySet != 0U) { // any SST tasks ready to run?\n            std::uint_fast8_t const p = SST_LOG2(task_readySet);\n            Task * const task = task_registry[p];\n            SST_PORT_INT_ENABLE();\n\n            // the task must have some events in the queue\n            DBC_ASSERT(100, task->m_nUsed > 0U);\n\n            // get the event out of the queue\n            // NOTE: no critical section because task->m_tail is accessed\n            // only from this task\n            //\n            Evt const *e = task->m_qBuf[task->m_tail];\n            if (task->m_tail == 0U) { /* need to wrap the tail? */\n                task->m_tail = task->m_end; /* wrap around */\n            }\n            else {\n                --task->m_tail;\n            }\n            SST_PORT_INT_DISABLE();\n            if ((--task->m_nUsed) == 0U) { /* no more events in the queue? */\n                task_readySet &= ~(1U << (p - 1U));\n            }\n            SST_PORT_INT_ENABLE();\n\n            // dispatch the received event to this task\n            task->dispatch(e); // virtual call\n            // TBD: implement event recycling\n        }\n        else { // no SST tasks are ready to run --> idle\n\n            // SST::onIdleCond() must be called with interrupts DISABLED\n            // because the determination of the idle condition (all event\n            // queues empty) can change at any time by an interrupt posting\n            // events to a queue.\n            //\n            // NOTE: SST::onIdleCond() MUST enable interrupts internally,\n            // ideally at the same time as putting the CPU into a power-\n            // saving mode.\n            //\n            onIdleCond();\n\n            SST_PORT_INT_DISABLE(); /* disable before looping back */\n        }\n    }\n#ifdef __GNUC__ // GNU compiler? */\n    return 0;\n#endif\n}\n\n// SST Task facilities -------------------------------------------------------\nvoid Task::start(\n    TaskPrio prio,\n    Evt const **qBuf, QCtr qLen,\n    Evt const * const ie)\n{\n    //! @pre\n    // - the priority must be in range\n    // - the queue storage must be provided\n    // - the queue length must not be zero\n    // - the priority must not be in use\n    //\n    DBC_REQUIRE(200,\n        (0U < prio) && (prio <= SST_PORT_MAX_TASK)\n        && (qBuf != nullptr) && (qLen > 0U)\n        && (task_registry[prio] == nullptr));\n\n    m_prio  = prio;\n    m_qBuf  = qBuf;\n    m_end   = qLen - 1U;\n    m_head  = 0U;\n    m_tail  = 0U;\n    m_nUsed = 0U;\n\n    task_registry[prio] = this;\n\n    // initialize this task with the initialization event\n    init(ie); // virtual call\n    // TBD: implement event recycling\n}\n//............................................................................\nvoid Task::post(Evt const * const e) noexcept {\n    //! @pre the queue must be sized adequately and cannot overflow\n    DBC_REQUIRE(300, m_nUsed <= m_end);\n\n    SST_PORT_CRIT_STAT\n    SST_PORT_CRIT_ENTRY();\n    m_qBuf[m_head] = e; // insert event into the queue\n    // need to wrap the head?\n    if (m_head == 0U) {\n        m_head = m_end; // wrap around\n    }\n    else {\n        --m_head;\n    }\n    ++m_nUsed;\n    task_readySet |= (1U << (m_prio - 1U));\n    SST_PORT_CRIT_EXIT();\n}\n\n//----------------------------------------------------------------------------\nstatic TimeEvt *timeEvt_head = nullptr;\n\n//............................................................................\nTimeEvt::TimeEvt(Signal sig, Task *task) {\n    this->sig  = sig;\n    m_task     = task;\n    m_ctr      = 0U;\n    m_interval = 0U;\n\n    // insert this time event into the linked-list\n    m_next = timeEvt_head;\n    timeEvt_head = this;\n}\n//............................................................................\nvoid TimeEvt::arm(TCtr ctr, TCtr interval) {\n    SST_PORT_CRIT_STAT\n    SST_PORT_CRIT_ENTRY();\n    m_ctr      = ctr;\n    m_interval = interval;\n    SST_PORT_CRIT_EXIT();\n}\n//............................................................................\nbool TimeEvt::disarm(void) {\n    SST_PORT_CRIT_STAT\n    SST_PORT_CRIT_ENTRY();\n    bool status = (m_ctr != 0U);\n    m_ctr       = 0U;\n    m_interval  = 0U;\n    SST_PORT_CRIT_EXIT();\n    return status;\n}\n//............................................................................\nvoid TimeEvt::tick(void) {\n    for (TimeEvt *t = timeEvt_head; t != nullptr; t = t->m_next) {\n        SST_PORT_CRIT_STAT\n        SST_PORT_CRIT_ENTRY();\n        if (t->m_ctr == 0U) { // disarmed? (most frequent case)\n            SST_PORT_CRIT_EXIT();\n        }\n        else if (t->m_ctr == 1U) { // expiring?\n            t->m_ctr = t->m_interval;\n            SST_PORT_CRIT_EXIT();\n\n            t->m_task->post(t);\n        }\n        else { // timing out\n            --t->m_ctr;\n            SST_PORT_CRIT_EXIT();\n        }\n    }\n}\n\n} // namespace SST\n"
  },
  {
    "path": "sst_c/README.txt",
    "content": "This directory contains the SST implementation in C roughly\ncorresponding to the BCC2 conformance class in the OSEK/VDX\nOperating System specification. This SST implementation is\nreferred to as \"SST/C\".\n\n- \"basic tasks\" (non-blocking)\n- preemptive scheduling\n- multiple tasks per prioriy level\n- multiple \"activations\" per task (event queues)\n"
  },
  {
    "path": "sst_c/examples/README.txt",
    "content": "This directory contains examples for the preemptive SST/C kernel.\n"
  },
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  },
  {
    "path": "sst_c/examples/blinky/blinky.c",
    "content": "/*============================================================================\n* Super-Simple Tasker (SST/C) Example\n*\n* Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n*\n* SPDX-License-Identifier: MIT\n*\n* Permission is hereby granted, free of charge, to any person obtaining a\n* copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included in\n* all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n============================================================================*/\n#include \"sst.h\"           /* SST framework */\n#include \"bsp.h\"           /* Board Support Package interface */\n#include \"blinky.h\"        /* application shared interface */\n\nDBC_MODULE_NAME(\"blinky\")  /* for DBC assertions in this module */\n\n/* Blinky event-driven task ------------------------------------------------*/\ntypedef struct {\n    SST_Task super; /* inherit SST_Task */\n\n    SST_TimeEvt te1;\n    SST_TimeEvt te2;\n} Blinky;\n\nstatic void Blinky_ctor(Blinky * const me);\nstatic void Blinky_init(Blinky * const me, SST_Evt const * const ie);\nstatic void Blinky_dispatch(Blinky * const me, SST_Evt const * const e);\n\n/*..........................................................................*/\nstatic Blinky Blinky_inst; /* the Blinky instance */\nSST_Task * const AO_Blinky = &Blinky_inst.super; /* opaque AO pointer */\n\n/*..........................................................................*/\nvoid Blinky_instantiate(void) {\n    Blinky_ctor(&Blinky_inst);\n}\n/*..........................................................................*/\nvoid Blinky_ctor(Blinky * const me) {\n    SST_Task_ctor(\n       &me->super,\n       (SST_Handler)&Blinky_init,\n       (SST_Handler)&Blinky_dispatch);\n    SST_TimeEvt_ctor(&me->te1, TIMEOUT1_SIG, &me->super);\n    SST_TimeEvt_ctor(&me->te2, TIMEOUT2_SIG, &me->super);\n}\n\n/* macro to select the Blinky implementation */\n#define BLINKY_IMPL 2\n\n/*--------------------------------------------------------------------------*/\n#if BLINKY_IMPL == 1\n/* Blinky implementation closest matching the traditional blocking approach */\n\nstatic void Blinky_init(Blinky * const me, SST_Evt const * const ie) {\n    (void)ie; /* unused parameter */\n\n    SST_TimeEvt_arm(&me->te1, 1U, 0U);\n}\n/*..........................................................................*/\nstatic void Blinky_dispatch(Blinky * const me, SST_Evt const * const e) {\n    switch (e->sig) {\n        case TIMEOUT1_SIG: {\n            BSP_ledOn();\n            SST_TimeEvt_arm(&me->te2, BSP_TICKS_PER_SEC / 4U, 0U);\n            break;\n        }\n        case TIMEOUT2_SIG: {\n            BSP_ledOff();\n            SST_TimeEvt_arm(&me->te1, BSP_TICKS_PER_SEC * 3U/4U, 0U);\n            break;\n        }\n        default: {\n            DBC_ERROR(200);\n            break;\n        }\n    }\n}\n\n/*--------------------------------------------------------------------------*/\n#elif BLINKY_IMPL == 2\n/* Blinky implementation with two periodic time events with offset */\n\nstatic void Blinky_init(Blinky * const me, SST_Evt const * const ie) {\n    (void)ie; /* unused parameter */\n    SST_TimeEvt_arm(&me->te1, 1U,                          BSP_TICKS_PER_SEC);\n    SST_TimeEvt_arm(&me->te2, 1U + (BSP_TICKS_PER_SEC/4U), BSP_TICKS_PER_SEC);\n}\n/*..........................................................................*/\nstatic void Blinky_dispatch(Blinky * const me, SST_Evt const * const e) {\n    switch (e->sig) {\n        case TIMEOUT1_SIG: {\n            BSP_ledOn();\n            break;\n        }\n        case TIMEOUT2_SIG: {\n            BSP_ledOff();\n            break;\n        }\n        default: {\n            DBC_ERROR(200);\n            break;\n        }\n    }\n}\n\n/*--------------------------------------------------------------------------*/\n#else\n    #error \"Wrong definition of the macro BLINKY_VERSION\"\n#endif\n"
  },
  {
    "path": "sst_c/examples/blinky/blinky.h",
    "content": "/*============================================================================\n* Super-Simple Tasker (SST/C) Example\n*\n* Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n*\n* SPDX-License-Identifier: MIT\n*\n* Permission is hereby granted, free of charge, to any person obtaining a\n* copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included in\n* all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n============================================================================*/\n#ifndef BLINKY_H_\n#define BLINKY_H_\n\n#include \"dbc_assert.h\" /* Design By Contract (DBC) assertions */\n\nenum Signals {\n    TIMEOUT1_SIG,\n    TIMEOUT2_SIG,\n    /* ... */\n    MAX_SIG  /* the last signal */\n};\n\nvoid Blinky_instantiate(void);\nextern SST_Task * const AO_Blinky;  /* opaque task pointer */\n\n#endif /* BLINKY_H_ */\n"
  },
  {
    "path": "sst_c/examples/blinky/bsp.h",
    "content": "/*============================================================================\n* Super-Simple Tasker (SST/C) Example\n*\n* Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n*\n* SPDX-License-Identifier: MIT\n*\n* Permission is hereby granted, free of charge, to any person obtaining a\n* copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included in\n* all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n============================================================================*/\n#ifndef BSP_H_\n#define BSP_H_\n\n#define BSP_TICKS_PER_SEC 1000U\n\nvoid BSP_init(void);\n\nvoid BSP_ledOn(void);\nvoid BSP_ledOff(void);\n\n#endif /* BSP_H_ */\n"
  },
  {
    "path": "sst_c/examples/blinky/bsp_nucleo-l053r8.c",
    "content": "/*============================================================================\n* Super-Simple Tasker (SST/C) Example for STM32 NUCLEO-L053R8\n*\n*                    Q u a n t u m  L e a P s\n*                    ------------------------\n*                    Modern Embedded Software\n*\n* Copyright (C) 2005 Quantum Leaps, <state-machine.com>.\n*\n* SPDX-License-Identifier: MIT\n*\n* Permission is hereby granted, free of charge, to any person obtaining a\n* copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included in\n* all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n============================================================================*/\n#include \"sst.h\"\n#include \"bsp.h\"\n#include \"blinky.h\"\n\n#include \"stm32l0xx.h\"  /* CMSIS-compliant header file for the MCU used */\n/* add other drivers if necessary... */\n\n//DBC_MODULE_NAME(\"bsp_nucleo-l053r8\") /* for DBC assertions in this module */\n\n/* Local-scope defines -----------------------------------------------------*/\n\n/* test pins on GPIO PA */\n#define LED_PIN   5U /* LED LD2-Green */\n\n/* ISRs used in the application ============================================*/\nvoid SysTick_Handler(void);  /* prototype */\n\nvoid SysTick_Handler(void) { /* system clock tick ISR */\n    SST_TimeEvt_tick(); /* process all SST time events */\n}\n\n/* Assertion handler ======================================================*/\nDBC_NORETURN\nvoid DBC_fault_handler(char const * const module, int const label) {\n    /*\n    * NOTE: add here your application-specific error handling\n    */\n    (void)module;\n    (void)label;\n\n    /* set PRIMASK to disable interrupts and stop SST right here */\n    __asm volatile (\"cpsid i\");\n\n#ifndef NDEBUG\n    for (;;) { /* keep blinking LED2 */\n        BSP_ledOn();  /* turn LED2 on */\n        uint32_t volatile ctr;\n        for (ctr = 10000U; ctr > 0U; --ctr) {\n        }\n        BSP_ledOff(); /* turn LED2 off */\n        for (ctr = 10000U; ctr > 0U; --ctr) {\n        }\n    }\n#endif\n    NVIC_SystemReset();\n}\n/*..........................................................................*/\nvoid assert_failed(char const * const module, int const label);/* prototype */\nvoid assert_failed(char const * const module, int const label) {\n    DBC_fault_handler(module, label);\n}\n\n/* SST task activations ====================================================*/\n/* preprocessor switch to choose between regular and reserved IRQs */\n#define REGULAR_IRQS\n\n#ifdef REGULAR_IRQS\n/* repurpose regular IRQs for SST Tasks */\n/* prototypes */\nvoid PVD_IRQHandler(void);\n\nvoid PVD_IRQHandler(void)  { SST_Task_activate(AO_Blinky);  }\n\n#else /* use reserved IRQs for SST Tasks */\n/* prototypes */\nvoid Reserved14_IRQHandler(void);\n\nvoid Reserved14_IRQHandler(void) { SST_Task_activate(AO_Blinky);  }\n#endif\n\n/* BSP functions ===========================================================*/\nvoid BSP_init(void) {\n    /* Configure the MPU to prevent NULL-pointer dereferencing\n    * see: www.state-machine.com/null-pointer-protection-with-arm-cortex-m-mpu\n    */\n    MPU->RBAR = 0x0U                          /* base address (NULL) */\n                | MPU_RBAR_VALID_Msk          /* valid region */\n                | (MPU_RBAR_REGION_Msk & 7U); /* region #7 */\n    MPU->RASR = (7U << MPU_RASR_SIZE_Pos)     /* 2^(7+1) region */\n                | (0x0U << MPU_RASR_AP_Pos)   /* no-access region */\n                | MPU_RASR_ENABLE_Msk;        /* region enable */\n\n    MPU->CTRL = MPU_CTRL_PRIVDEFENA_Msk       /* enable background region */\n                | MPU_CTRL_ENABLE_Msk;        /* enable the MPU */\n    __ISB();\n    __DSB();\n\n    /* assign IRQs to tasks. NOTE: critical for SST... */\n#ifdef REGULAR_IRQS\n    /* repurpose regular IRQs for SST Tasks */\n    SST_Task_setIRQ(AO_Blinky,  PVD_IRQn);\n#else\n    /* use reserved IRQs for SST Tasks */\n    SST_Task_setIRQ(AO_Blinky,  14U);\n#endif\n\n    /* enable GPIO port PA clock */\n    RCC->IOPENR |= (1U << 0U);\n\n    /* set all used GPIOA pins as push-pull output, no pull-up, pull-down */\n    GPIOA->MODER  &= ~(3U << 2U*LED_PIN);\n    GPIOA->MODER  |=  (1U << 2U*LED_PIN);\n    GPIOA->OTYPER &= ~(1U <<    LED_PIN);\n    GPIOA->PUPDR  &= ~(3U << 2U*LED_PIN);\n}\n\n/*..........................................................................*/\nvoid BSP_ledOn(void)  { GPIOA->BSRR = (1U << LED_PIN);         } /* LED2 */\nvoid BSP_ledOff(void) { GPIOA->BSRR = (1U << (LED_PIN + 16U)); }\n\n/* SST callbacks ===========================================================*/\nvoid SST_onStart(void) {\n    SystemCoreClockUpdate();\n\n    /* set up the SysTick timer to fire at BSP_TICKS_PER_SEC rate */\n    SysTick_Config((SystemCoreClock / BSP_TICKS_PER_SEC) + 1U);\n\n    /* set priorities of ISRs used in the system */\n    NVIC_SetPriority(SysTick_IRQn, 0U);\n    /* ... */\n}\n/*..........................................................................*/\nvoid SST_onIdle(void) {\n#ifdef NDEBUG\n    /* Put the CPU and peripherals to the low-power mode.\n    * you might need to customize the clock management for your application,\n    * see the datasheet for your particular Cortex-M MCU.\n    */\n    __WFI(); /* Wait-For-Interrupt */\n#endif\n}\n\n"
  },
  {
    "path": "sst_c/examples/blinky/gnu/nucleo-l053r8.mak",
    "content": "##############################################################################\n# Makefile for Super-Simple Tasker (SST/C) on NUCLEO-L053R8, GNU-ARM\n# Last Updated for Version: 2.0.0\n# Date of the Last Update:  2023-01-22\n#\n#                    Q u a n t u m  L e a P s\n#                    ------------------------\n#                    Modern Embedded Software\n#\n# Copyright (C) 2005 Quantum Leaps, LLC. All rights reserved.\n#\n# SPDX-License-Identifier: MIT\n#\n# Permission is hereby granted, free of charge, to any person obtaining a copy\n# of this software and associated documentation files (the \"Software\"), to\n# deal in the Software without restriction, including without limitation the\n# rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n# sell copies of the Software, and to permit persons to whom the Software is\n# furnished to do so, subject to the following conditions:\n#\n# The above copyright notice and this permission notice shall be included in\n# all copies or substantial portions of the Software.\n#\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS\n# IN THE SOFTWARE.\n##############################################################################\n# examples of invoking this Makefile:\n# make -f nucleo-l053r8.mak\n# make -f nucleo-l053r8.mak clean\n#\n# NOTE:\n# To use this Makefile on Windows, you will need the GNU make utility, which\n# is included in the QTools collection for Windows, see:\n#    https://github.com/QuantumLeaps/qtools\n#\n\n#-----------------------------------------------------------------------------\n# project and target names\n#\nPROJECT := blinky\nTARGET  := nucleo-l053r8\n\n#-----------------------------------------------------------------------------\n# project directories\n#\nSST_DIR      := ../../..\nSST_PORT_DIR := $(SST_DIR)/ports/arm-cm\nCMSIS_DIR    := ../../../../3rd_party/CMSIS\nTARGET_DIR   := ../../../../3rd_party/$(TARGET)\n\n# list of all source directories used by this project\nVPATH = .. \\\n\t$(SST_DIR)/src \\\n\t$(SST_PORT_DIR) \\\n\t$(TARGET_DIR) \\\n\t$(TARGET_DIR)/gnu \\\n\n# list of all include directories needed by this project\nINCLUDES  = -I. \\\n\t-I$(SST_DIR)/../include \\\n\t-I$(SST_PORT_DIR) \\\n\t-I$(CMSIS_DIR)/Include \\\n\t-I$(TARGET_DIR)\n\n#-----------------------------------------------------------------------------\n# project files\n#\n\n# assembler source files\nASM_SRCS :=\n\n# C source files\nC_SRCS := \\\n\tsst.c \\\n\tsst_port.c \\\n\tmain.c \\\n\tblinky.c \\\n\tbsp_nucleo-l053r8.c \\\n\tsystem_stm32l0xx.c \\\n\tstartup_stm32l053xx.c\n\n# C++ source files\nCPP_SRCS :=\n\nLD_SCRIPT  := $(TARGET_DIR)/gnu/$(TARGET).ld\n\nOUTPUT    := $(PROJECT)\n\nLIB_DIRS  :=\nLIBS      :=\n\n# defines\nDEFINES   :=\n\n# ARM CPU, ARCH, FPU, and Float-ABI types...\n# ARM_CPU:   [cortex-m0 | cortex-m0plus | cortex-m1 | cortex-m3 | cortex-m4]\n# ARM_FPU:   [ | vfp]\n# FLOAT_ABI: [ | soft | softfp | hard]\n#\nARM_CPU   := -mcpu=cortex-m0plus\nARM_FPU   :=\nFLOAT_ABI :=\n\n#-----------------------------------------------------------------------------\n# GNU-ARM toolset (NOTE: You need to adjust to your machine)\n# see https://developer.arm.com/open-source/gnu-toolchain/gnu-rm/downloads\n#\nifeq ($(GNU_ARM),)\nGNU_ARM := $(QTOOLS)/gnu_arm-none-eabi\nendif\n\n# make sure that the GNU-ARM toolset exists...\nifeq (\"$(wildcard $(GNU_ARM))\",\"\")\n$(error GNU_ARM toolset not found. Please adjust the Makefile)\nendif\n\nCC    := $(GNU_ARM)/bin/arm-none-eabi-gcc\nCPP   := $(GNU_ARM)/bin/arm-none-eabi-g++\nAS    := $(GNU_ARM)/bin/arm-none-eabi-as\nLINK  := $(GNU_ARM)/bin/arm-none-eabi-gcc\nBIN   := $(GNU_ARM)/bin/arm-none-eabi-objcopy\n\n##############################################################################\n# Typically you should not need to change anything below this line\n\n# basic utilities (included in QTools for Windows), see:\n#     https://www.state-machine.com/qtools\n\nMKDIR := mkdir\nRM    := rm\n\n#-----------------------------------------------------------------------------\n# build options\n#\n\n# combine all the soruces...\nC_SRCS += $(QP_SRCS)\nASM_SRCS += $(QP_ASMS)\n\nBIN_DIR := build_$(TARGET)\n\nASFLAGS = -g $(ARM_CPU) $(ARM_FPU) $(ASM_CPU) $(ASM_FPU)\n\nCFLAGS = -c -g $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -std=c99 -mthumb -Wall \\\n\t-ffunction-sections -fdata-sections \\\n\t-O $(INCLUDES) $(DEFINES)\n\nCPPFLAGS = -c -g $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -std=c++11 -mthumb -Wall \\\n\t-ffunction-sections -fdata-sections -fno-rtti -fno-exceptions \\\n\t-O $(INCLUDES) $(DEFINES)\n\nLINKFLAGS = -T$(LD_SCRIPT) $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -mthumb \\\n\t-specs=nosys.specs -specs=nano.specs \\\n\t-Wl,-Map,$(BIN_DIR)/$(OUTPUT).map,--cref,--gc-sections $(LIB_DIRS)\n\nASM_OBJS     := $(patsubst %.s,%.o,  $(notdir $(ASM_SRCS)))\nC_OBJS       := $(patsubst %.c,%.o,  $(notdir $(C_SRCS)))\nCPP_OBJS     := $(patsubst %.cpp,%.o,$(notdir $(CPP_SRCS)))\n\nTARGET_BIN   := $(BIN_DIR)/$(OUTPUT).bin\nTARGET_ELF   := $(BIN_DIR)/$(OUTPUT).elf\nASM_OBJS_EXT := $(addprefix $(BIN_DIR)/, $(ASM_OBJS))\nC_OBJS_EXT   := $(addprefix $(BIN_DIR)/, $(C_OBJS))\nC_DEPS_EXT   := $(patsubst %.o, %.d, $(C_OBJS_EXT))\nCPP_OBJS_EXT := $(addprefix $(BIN_DIR)/, $(CPP_OBJS))\nCPP_DEPS_EXT := $(patsubst %.o, %.d, $(CPP_OBJS_EXT))\n\n# create $(BIN_DIR) if it does not exist\nifeq (\"$(wildcard $(BIN_DIR))\",\"\")\n$(shell $(MKDIR) $(BIN_DIR))\nendif\n\n#-----------------------------------------------------------------------------\n# rules\n#\n\n.PHONY : run norun flash\n\nifeq ($(MAKECMDGOALS),norun)\nall : $(TARGET_BIN)\nnorun : all\nelse\nall : $(TARGET_BIN) run\nendif\n\n$(TARGET_BIN): $(TARGET_ELF)\n\t$(BIN) -O binary $< $@\n\n$(TARGET_ELF) : $(ASM_OBJS_EXT) $(C_OBJS_EXT) $(CPP_OBJS_EXT)\n\t$(LINK) $(LINKFLAGS) -o $@ $^ $(LIBS)\n\n$(BIN_DIR)/%.d : %.c\n\t$(CC) -MM -MT $(@:.d=.o) $(CFLAGS) $< > $@\n\n$(BIN_DIR)/%.d : %.cpp\n\t$(CPP) -MM -MT $(@:.d=.o) $(CPPFLAGS) $< > $@\n\n$(BIN_DIR)/%.o : %.s\n\t$(AS) $(ASFLAGS) $< -o $@\n\n$(BIN_DIR)/%.o : %.c\n\t$(CC) $(CFLAGS) $< -o $@\n\n$(BIN_DIR)/%.o : %.cpp\n\t$(CPP) $(CPPFLAGS) $< -o $@\n\n.PHONY : clean show\n\n# include dependency files only if our goal depends on their existence\nifneq ($(MAKECMDGOALS),clean)\n  ifneq ($(MAKECMDGOALS),show)\n-include $(C_DEPS_EXT) $(CPP_DEPS_EXT)\n  endif\nendif\n\n\nclean :\n\t-$(RM) $(BIN_DIR)/*.o \\\n\t$(BIN_DIR)/*.d \\\n\t$(BIN_DIR)/*.bin \\\n\t$(BIN_DIR)/*.elf \\\n\t$(BIN_DIR)/*.map\n\t\nshow:\n\t@echo PROJECT = $(PROJECT)\n\t@echo CONF = $(CONF)\n\t@echo DEFINES = $(DEFINES)\n\t@echo ASM_FPU = $(ASM_FPU)\n\t@echo ASM_SRCS = $(ASM_SRCS)\n\t@echo C_SRCS = $(C_SRCS)\n\t@echo CPP_SRCS = $(CPP_SRCS)\n\t@echo ASM_OBJS_EXT = $(ASM_OBJS_EXT)\n\t@echo C_OBJS_EXT = $(C_OBJS_EXT)\n\t@echo C_DEPS_EXT = $(C_DEPS_EXT)\n\t@echo CPP_DEPS_EXT = $(CPP_DEPS_EXT)\n\t@echo TARGET_ELF = $(TARGET_ELF)\n"
  },
  {
    "path": "sst_c/examples/blinky/iar/nucleo-l053r8.ewd",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<project>\n    <fileVersion>3</fileVersion>\n    <configuration>\n        <name>Debug</name>\n        <toolchain>\n            <name>ARM</name>\n        </toolchain>\n        <debug>1</debug>\n        <settings>\n            <name>C-SPY</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>32</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CInput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CEndian</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCVariant</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>MemOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MemFile</name>\n                    <state>$TOOLKIT_DIR$\\CONFIG\\debugger\\ST\\STM32L053R8.ddf</state>\n                </option>\n                <option>\n                    <name>RunToEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RunToName</name>\n                    <state>main</state>\n                </option>\n                <option>\n                    <name>CExtraOptionsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCDDFArgumentProducer</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCDownloadSuppressDownload</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCDownloadVerifyAll</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProductVersion</name>\n                    <state>9.10.2.39304</state>\n                </option>\n                <option>\n                    <name>OCDynDriverList</name>\n                    <state>STLINK_ID</state>\n                </option>\n                <option>\n                    <name>OCLastSavedByProductVersion</name>\n                    <state>9.32.1.54977</state>\n                </option>\n                <option>\n                    <name>UseFlashLoader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CLowLevel</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCBE8Slave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacFile2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CDevice</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>FlashLoadersV3</name>\n                    <state>$TOOLKIT_DIR$/config/flashloader/ST/FlashSTM32L0xxx8.board</state>\n                </option>\n                <option>\n                    <name>OCImagesSuppressCheck1</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesPath1</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCImagesSuppressCheck2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesPath2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCImagesSuppressCheck3</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesPath3</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OverrideDefFlashBoard</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesOffset1</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCImagesOffset2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCImagesOffset3</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCImagesUse1</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesUse2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesUse3</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCDeviceConfigMacroFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCDebuggerExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCAllMTBOptions</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCMulticoreNrOfCores</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCMulticoreWorkspace</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCMulticoreSlaveProject</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCMulticoreSlaveConfiguration</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCDownloadExtraImage</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCAttachSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MassEraseBeforeFlashing</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCMulticoreNrOfCoresSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCMulticoreAMPConfigType</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCMulticoreSessionFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCTpiuBaseOption</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>ARMSIM_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>1</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCSimDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCSimEnablePSP</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCSimPspOverrideConfig</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCSimPspConfigFile</name>\n                    <state></state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CADI_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CCadiMemory</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>Fast Model</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCADILogFileCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCADILogFileEditB</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CMSISDAP_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>4</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCIarProbeScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CMSISDAPResetList</name>\n                    <version>1</version>\n                    <state>10</state>\n                </option>\n                <option>\n                    <name>CMSISDAPHWResetDuration</name>\n                    <state>300</state>\n                </option>\n                <option>\n                    <name>CMSISDAPHWResetDelay</name>\n                    <state>200</state>\n                </option>\n                <option>\n                    <name>CMSISDAPDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CMSISDAPInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CMSISDAPInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiTargetEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPJtagSpeedList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPRestoreBreakpointsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPUpdateBreakpointsEdit</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>RDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchUndef</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchData</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchPrefetch</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchMMERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchNOCPERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchCHKERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSTATERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchBUSERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchINTERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSFERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchHARDERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiCPUEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiCPUNumber</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeCfgOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeConfig</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CMSISDAPProbeConfigRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPSelectedCPUBehaviour</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ICpuName</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCJetEmuParams</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCCMSISDAPUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCCMSISDAPUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>GDBSERVER_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>TCPIP</name>\n                    <state>aaa.bbb.ccc.ddd</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCJTagBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJTagDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJTagUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>IJET_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>9</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCIarProbeScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetResetList</name>\n                    <version>1</version>\n                    <state>10</state>\n                </option>\n                <option>\n                    <name>IjetHWResetDuration</name>\n                    <state>300</state>\n                </option>\n                <option>\n                    <name>IjetHWResetDelay</name>\n                    <state>200</state>\n                </option>\n                <option>\n                    <name>IjetPowerFromProbe</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetPowerRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>IjetInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiTargetEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetScanChainNonARMDevices</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetIRLength</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetJtagSpeedList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetProtocolRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetSwoPin</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IjetSwoPrescalerList</name>\n                    <version>1</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetRestoreBreakpointsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetUpdateBreakpointsEdit</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>RDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchUndef</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchData</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchPrefetch</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchMMERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchNOCPERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchCHKERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSTATERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchBUSERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchINTERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSFERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchHARDERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeCfgOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeConfig</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IjetProbeConfigRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiCPUEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiCPUNumber</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetSelectedCPUBehaviour</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ICpuName</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCJetEmuParams</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetPreferETB</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetTraceSettingsList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetTraceSizeList</name>\n                    <version>0</version>\n                    <state>4</state>\n                </option>\n                <option>\n                    <name>FlashBoardPathSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCIjetUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCIjetUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL3S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL3S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL3S</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>JLINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>16</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>JLinkSpeed</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCJLinkDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCJLinkHWResetDelay</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>JLinkInitialSpeed</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCDoJlinkMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCScanChainNonARMDevices</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkIRLength</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkCommRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkTCPIP</name>\n                    <state>aaa.bbb.ccc.ddd</state>\n                </option>\n                <option>\n                    <name>CCJLinkSpeedRadioV2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCUSBDevice</name>\n                    <version>1</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCRDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchUndef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchData</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchPrefetch</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCJLinkInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJLinkResetList</name>\n                    <version>6</version>\n                    <state>5</state>\n                </option>\n                <option>\n                    <name>CCJLinkInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJLinkUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCTcpIpAlt</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkTcpIpSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSwoClockAuto</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSwoClockEdit</name>\n                    <state>2000</state>\n                </option>\n                <option>\n                    <name>OCJLinkTraceSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkTraceSourceDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkDeviceName</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>LMIFTDI_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>3</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>LmiftdiSpeed</name>\n                    <state>500</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCLmiFtdiInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCLmiFtdiInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCLmiftdiUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiResetList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>NULINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>PEMICRO_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>3</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJPEMicroShowSettings</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>STLINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>8</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSTLinkInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSTLinkInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkResetList</name>\n                    <version>3</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSwoClockAuto</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSwoClockEdit</name>\n                    <state>2000</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCSTLinkDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSTLinkUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkJtagSpeedList</name>\n                    <version>2</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkDAPNumber</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSTLinkDebugAccessPortRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUseServerSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkProbeList</name>\n                    <version>1</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkTargetVccEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSTLinkTargetVoltage</name>\n                    <state>3.3</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>THIRDPARTY_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CThirdPartyDriverDll</name>\n                    <state>###Uninitialized###</state>\n                </option>\n                <option>\n                    <name>CThirdPartyLogFileCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CThirdPartyLogFileEditB</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>TIFET_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>1</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCMSPFetResetList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetInterfaceRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetTargetVccTypeDefault</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetTargetVoltage</name>\n                    <state>###Uninitialized###</state>\n                </option>\n                <option>\n                    <name>CCMSPFetVCCDefault</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCMSPFetTargetSettlingtime</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetRadioJtagSpeedType</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCMSPFetConnection</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetUsbComPort</name>\n                    <state>Automatic</state>\n                </option>\n                <option>\n                    <name>CCMSPFetAllowAccessToBSL</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCMSPFetRadioEraseFlash</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>XDS100_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>9</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>TIPackageOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TIPackage</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>BoardFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCXds100BreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100DoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100UpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchUndef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchData</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchPrefetch</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCXds100SwoClockAuto</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100SwoClockEdit</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCXds100HWResetDelay</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100ResetList</name>\n                    <version>1</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100UsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCXds100UsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100JtagSpeedList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100InterfaceRadio</name>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCXds100InterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100ProbeList</name>\n                    <version>0</version>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>CCXds100SWOPortRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100SWOPort</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCXDSTargetVccEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXDSTargetVoltage</name>\n                    <state>###Uninitialized###</state>\n                </option>\n                <option>\n                    <name>OCXDSDigitalStatesConfigFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCSelectedCoreName</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <debuggerPlugins>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\CMX\\CmxArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\CMX\\CmxTinyArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\embOS\\embOSPlugin.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\FreeRtos\\FreeRtosArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\Mbed\\MbedArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\Mbed\\MbedArmPlugin2.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\OpenRTOS\\OpenRTOSPlugin.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\SafeRTOS\\SafeRTOSPlugin.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\SMX\\smxAwareIarArm9.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\SMX\\smxAwareIarArm9BE.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\ThreadX\\ThreadXArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\uCOS-II\\uCOS-II-286-KA-CSpy.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\uCOS-II\\uCOS-II-KA-CSpy.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\uCOS-III\\uCOS-III-KA-CSpy.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$EW_DIR$\\common\\plugins\\Orti\\Orti.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$EW_DIR$\\common\\plugins\\TargetAccessServer\\TargetAccessServer.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$EW_DIR$\\common\\plugins\\uCProbe\\uCProbePlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n        </debuggerPlugins>\n    </configuration>\n</project>\n"
  },
  {
    "path": "sst_c/examples/blinky/iar/nucleo-l053r8.ewp",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<project>\n    <fileVersion>3</fileVersion>\n    <configuration>\n        <name>Debug</name>\n        <toolchain>\n            <name>ARM</name>\n        </toolchain>\n        <debug>1</debug>\n        <settings>\n            <name>General</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <version>35</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>BrowseInfoPath</name>\n                    <state>build_nucleo-l053r8</state>\n                </option>\n                <option>\n                    <name>ExePath</name>\n                    <state>build_nucleo-l053r8</state>\n                </option>\n                <option>\n                    <name>ObjPath</name>\n                    <state>build_nucleo-l053r8</state>\n                </option>\n                <option>\n                    <name>ListPath</name>\n                    <state>build_nucleo-l053r8</state>\n                </option>\n                <option>\n                    <name>GEndianMode</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>Input description</name>\n                    <state>No specifier n, no float nor long long, no scan set, no assignment suppressing, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>Output description</name>\n                    <state>No specifier a, A, no specifier n, no float nor long long, no flags, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>GOutputBinary</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGCoreOrChip</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelect</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelectSlave</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RTDescription</name>\n                    <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\n                </option>\n                <option>\n                    <name>OGProductVersion</name>\n                    <state>5.11.0.50579</state>\n                </option>\n                <option>\n                    <name>OGLastSavedByProductVersion</name>\n                    <state>9.32.1.54977</state>\n                </option>\n                <option>\n                    <name>OGChipSelectEditMenu</name>\n                    <state>STM32L053R8\tST STM32L053R8</state>\n                </option>\n                <option>\n                    <name>GenLowLevelInterface</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GEndianModeBE</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OGBufferedTerminalOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GenStdoutInterface</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RTConfigPath2</name>\n                    <state>$TOOLKIT_DIR$\\inc\\c\\DLib_Config_Normal.h</state>\n                </option>\n                <option>\n                    <name>GBECoreSlave</name>\n                    <version>32</version>\n                    <state>35</state>\n                </option>\n                <option>\n                    <name>OGUseCmsis</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGUseCmsisDspLib</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibThreads</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CoreVariant</name>\n                    <version>32</version>\n                    <state>35</state>\n                </option>\n                <option>\n                    <name>GFPUDeviceSlave</name>\n                    <state>STM32L053R8\tST STM32L053R8</state>\n                </option>\n                <option>\n                    <name>FPU2</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>NrRegs</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>NEON</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GFPUCoreSlave2</name>\n                    <version>32</version>\n                    <state>35</state>\n                </option>\n                <option>\n                    <name>OGCMSISPackSelectDevice</name>\n                </option>\n                <option>\n                    <name>OgLibHeap</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGLibAdditionalLocale</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGPrintfVariant</name>\n                    <version>0</version>\n                    <state>4</state>\n                </option>\n                <option>\n                    <name>OGPrintfMultibyteSupport</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGScanfVariant</name>\n                    <version>0</version>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>OGScanfMultibyteSupport</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GenLocaleTags</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>GenLocaleDisplayOnly</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DSPExtension</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TrustZone</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TrustZoneModes</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGAarch64Abi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OG_32_64Device</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>BuildFilesPath</name>\n                    <state>Debug</state>\n                </option>\n                <option>\n                    <name>PointerAuthentication</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>FPU64</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>ICCARM</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>37</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CCOptimizationNoSizeConstraints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCDefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCPreprocFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPreprocComments</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPreprocLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCMnemonics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCMessages</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListAssFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListAssSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEnableRemarks</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCDiagSuppress</name>\n                    <state>Pa050</state>\n                </option>\n                <option>\n                    <name>CCDiagRemark</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagWarning</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagError</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCObjPrefix</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCAllowList</name>\n                    <version>1</version>\n                    <state>10010100</state>\n                </option>\n                <option>\n                    <name>CCDebugInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IEndianMode</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IExtraOptionsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCLangConformance</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSignedPlainChar</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCRequirePrototypes</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCDiagWarnAreErr</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCompilerRuntimeInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OutputFile</name>\n                    <state>$FILE_BNAME$.o</state>\n                </option>\n                <option>\n                    <name>CCLibConfigHeader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>PreInclude</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCIncludePath2</name>\n                    <state>$PROJ_DIR$\\..</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\include</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\ports\\arm-cm</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\CMSIS\\Include</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\nucleo-l053r8</state>\n                </option>\n                <option>\n                    <name>CCStdIncCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCodeSection</name>\n                    <state>.text</state>\n                </option>\n                <option>\n                    <name>IProcessorMode2</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCOptLevel</name>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCOptStrategy</name>\n                    <version>0</version>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCOptLevelSlave</name>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCPosIndRopi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPosIndRwpi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPosIndNoDynInit</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccLang</name>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>IccCDialect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccAllowVLA</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccStaticDestr</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccCppInlineSemantics</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccCmsis</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccFloatSemantics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCNoLiteralPool</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCOptStrategySlave</name>\n                    <version>0</version>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCGuardCalls</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCEncSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEncOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEncOutputBom</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCEncInput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccExceptions2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccRTTI2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OICompilerExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCStackProtection</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>AARM</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>11</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>AObjPrefix</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AEndian</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>ACaseSensitivity</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacroChars</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnWhat</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnOne</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AWarnRange1</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AWarnRange2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>ADebug</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AltRegisterNames</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ADefines</name>\n                    <state>ewarm</state>\n                </option>\n                <option>\n                    <name>AList</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AListHeader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AListing</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>Includes</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacDefs</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacExps</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacExec</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OnlyAssed</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MultiLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PageLengthCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PageLength</name>\n                    <state>80</state>\n                </option>\n                <option>\n                    <name>TabSpacing</name>\n                    <state>8</state>\n                </option>\n                <option>\n                    <name>AXRef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefDefines</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefInternal</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefDual</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AOutputFile</name>\n                    <state>$FILE_BNAME$.o</state>\n                </option>\n                <option>\n                    <name>ALimitErrorsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ALimitErrorsEdit</name>\n                    <state>100</state>\n                </option>\n                <option>\n                    <name>AIgnoreStdInclude</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AUserIncludes</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AExtraOptionsCheckV2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AExtraOptionsV2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AsmNoLiteralPool</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PreInclude</name>\n                    <state></state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>OBJCOPY</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>1</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OOCOutputFormat</name>\n                    <version>3</version>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>OCOutputOverride</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OOCOutputFile</name>\n                    <state>blinky.bin</state>\n                </option>\n                <option>\n                    <name>OOCCommandLineProducer</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OOCObjCopyEnable</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CUSTOM</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <extensions></extensions>\n                <cmdline></cmdline>\n                <hasPrio>1</hasPrio>\n                <buildSequence>inputOutputBased</buildSequence>\n            </data>\n        </settings>\n        <settings>\n            <name>BUILDACTION</name>\n            <archiveVersion>1</archiveVersion>\n            <data>\n                <prebuild></prebuild>\n                <postbuild></postbuild>\n            </data>\n        </settings>\n        <settings>\n            <name>ILINK</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>27</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>IlinkLibIOConfig</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkInputFileSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOutputFile</name>\n                    <state>blinky.out</state>\n                </option>\n                <option>\n                    <name>IlinkDebugInfoEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkKeepSymbols</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySymbol</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySegment</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryAlign</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkDefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkConfigDefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkMapFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLogFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogInitialization</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogModule</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogSection</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogVeneer</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFile</name>\n                    <state>$TOOLKIT_DIR$/config/linker/ST/stm32l053x8.icf</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFileSlave</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkEnableRemarks</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkSuppressDiags</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsRem</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsWarn</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsErr</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkWarningsAreErrors</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkUseExtraOptions</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkLowLevelInterfaceSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkAutoLibEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkAdditionalLibs</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkOverrideProgramEntryLabel</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkProgramEntryLabelSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkProgramEntryLabel</name>\n                    <state>__iar_program_start</state>\n                </option>\n                <option>\n                    <name>DoFill</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>FillerByte</name>\n                    <state>0xFF</state>\n                </option>\n                <option>\n                    <name>FillerStart</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>FillerEnd</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>CrcSize</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcAlign</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcPoly</name>\n                    <state>0x11021</state>\n                </option>\n                <option>\n                    <name>CrcCompl</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CrcBitOrder</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CrcInitialValue</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>DoCrc</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkBE8Slave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkBufferedTerminalOutput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkStdoutInterfaceSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcFullSize</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIElfToolPostProcess</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogAutoLibSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogRedirSymbols</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogUnusedFragments</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCrcReverseByteOrder</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCrcUseAsInput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptInline</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOptExceptionsAllow</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOptExceptionsForce</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCmsis</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptMergeDuplSections</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOptUseVfe</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptForceVfe</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkStackAnalysisEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkStackControlFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkStackCallGraphFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CrcAlgorithm</name>\n                    <version>1</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcUnitSize</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkThreadsSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLogCallGraph</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFile_AltDefault</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkEncInput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutputBom</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkHeapSelect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLocaleSelect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkTrustzoneImportLibraryOut</name>\n                    <state>iar_nucleo-l053r8_import_lib.o</state>\n                </option>\n                <option>\n                    <name>OILinkExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryFile2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySymbol2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySegment2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryAlign2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkLogCrtRoutineSelection</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogFragmentInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogInlining</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogMerging</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkDemangle</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkWrapperFileEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkWrapperFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkFpuProcessor</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>IARCHIVE</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>IarchiveInputs</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IarchiveOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IarchiveOutput</name>\n                    <state>###Unitialized###</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>Coder</name>\n            <archiveVersion>0</archiveVersion>\n            <data />\n        </settings>\n    </configuration>\n    <mfc>\n        <configuration>Debug</configuration>\n    </mfc>\n    <group>\n        <name>Application</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\blinky.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\blinky.h</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\bsp.h</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\bsp_nucleo-l053r8.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\main.c</name>\n        </file>\n    </group>\n    <group>\n        <name>nucleo-l053r8</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\nucleo-l053r8\\iar\\startup_stm32l053xx.s</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\nucleo-l053r8\\stm32l053xx.h</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\nucleo-l053r8\\system_stm32l0xx.c</name>\n        </file>\n    </group>\n    <group>\n        <name>sst</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\src\\sst.c</name>\n        </file>\n    </group>\n    <group>\n        <name>sst_port</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\ports\\arm-cm\\sst_port.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\ports\\arm-cm\\sst_port.h</name>\n        </file>\n    </group>\n</project>\n"
  },
  {
    "path": "sst_c/examples/blinky/iar/nucleo-l053r8.eww",
    "content": "<?xml version=\"1.0\" encoding=\"iso-8859-1\"?>\n\n<workspace>\n  <project>\n    <path>$WS_DIR$\\nucleo-l053r8.ewp</path>\n  </project>\n  <batchBuild/>\n</workspace>\n\n\n"
  },
  {
    "path": "sst_c/examples/blinky/main.c",
    "content": "/*============================================================================\n* Super-Simple Tasker (SST/C) Example\n*\n* Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n*\n* SPDX-License-Identifier: MIT\n*\n* Permission is hereby granted, free of charge, to any person obtaining a\n* copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included in\n* all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n============================================================================*/\n#include \"sst.h\"           /* SST framework */\n#include \"bsp.h\"           /* Board Support Package interface */\n#include \"blinky.h\"        /* application shared interface */\n\n/*..........................................................................*/\nint main() {\n    SST_init(); /* initialize the SST kernel */\n    BSP_init(); /* initialize the Board Support Package */\n\n    /* instantiate and start all SST tasks... */\n    Blinky_instantiate();\n    static SST_Evt const *blinkyQSto[10]; /* Event queue storage */\n    SST_Task_start(\n        AO_Blinky,     /* AO pointer to start */\n        1U,            /* SST-priority */\n        blinkyQSto,    /* storage for the AO's queue */\n        ARRAY_NELEM(blinkyQSto),   /* queue length */\n        (void *)0);    /* initialization event (not used) */\n\n    return SST_Task_run(); /* run the SST tasks */\n    /* NOTE; in embedded systems SST_Task_run() should not return */\n}\n\n"
  },
  {
    "path": "sst_c/examples/blinky_button/armclang/ek-tm4c123gxl.uvoptx",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\" standalone=\"no\" ?>\n<ProjectOpt xmlns:xsi=\"http://www.w3.org/2001/XMLSchema-instance\" xsi:noNamespaceSchemaLocation=\"project_optx.xsd\">\n\n  <SchemaVersion>1.0</SchemaVersion>\n\n  <Header>### uVision Project, (C) Keil Software</Header>\n\n  <Extensions>\n    <cExt>*.c</cExt>\n    <aExt>*.s*; *.src; *.a*</aExt>\n    <oExt>*.obj; *.o</oExt>\n    <lExt>*.lib</lExt>\n    <tExt>*.txt; *.h; *.inc; *.md</tExt>\n    <pExt>*.plm</pExt>\n    <CppX>*.cpp</CppX>\n    <nMigrate>0</nMigrate>\n  </Extensions>\n\n  <DaveTm>\n    <dwLowDateTime>0</dwLowDateTime>\n    <dwHighDateTime>0</dwHighDateTime>\n  </DaveTm>\n\n  <Target>\n    <TargetName>ek-tm4c123gxl</TargetName>\n    <ToolsetNumber>0x4</ToolsetNumber>\n    <ToolsetName>ARM-ADS</ToolsetName>\n    <TargetOption>\n      <CLKADS>12000000</CLKADS>\n      <OPTTT>\n        <gFlags>1</gFlags>\n        <BeepAtEnd>1</BeepAtEnd>\n        <RunSim>1</RunSim>\n        <RunTarget>0</RunTarget>\n        <RunAbUc>0</RunAbUc>\n      </OPTTT>\n      <OPTHX>\n        <HexSelection>1</HexSelection>\n        <FlashByte>65535</FlashByte>\n        <HexRangeLowAddress>0</HexRangeLowAddress>\n        <HexRangeHighAddress>0</HexRangeHighAddress>\n        <HexOffset>0</HexOffset>\n      </OPTHX>\n      <OPTLEX>\n        <PageWidth>79</PageWidth>\n        <PageLength>66</PageLength>\n        <TabStop>8</TabStop>\n        <ListingPath>.\\build_ek-tm4c123gxl\\</ListingPath>\n      </OPTLEX>\n      <ListingPage>\n        <CreateCListing>1</CreateCListing>\n        <CreateAListing>1</CreateAListing>\n        <CreateLListing>1</CreateLListing>\n        <CreateIListing>0</CreateIListing>\n        <AsmCond>1</AsmCond>\n        <AsmSymb>1</AsmSymb>\n        <AsmXref>0</AsmXref>\n        <CCond>1</CCond>\n        <CCode>0</CCode>\n        <CListInc>0</CListInc>\n        <CSymb>0</CSymb>\n        <LinkerCodeListing>0</LinkerCodeListing>\n      </ListingPage>\n      <OPTXL>\n        <LMap>1</LMap>\n        <LComments>1</LComments>\n        <LGenerateSymbols>1</LGenerateSymbols>\n        <LLibSym>1</LLibSym>\n        <LLines>1</LLines>\n        <LLocSym>1</LLocSym>\n        <LPubSym>1</LPubSym>\n        <LXref>0</LXref>\n        <LExpSel>0</LExpSel>\n      </OPTXL>\n      <OPTFL>\n        <tvExp>1</tvExp>\n        <tvExpOptDlg>0</tvExpOptDlg>\n        <IsCurrentTarget>1</IsCurrentTarget>\n      </OPTFL>\n      <CpuCode>4</CpuCode>\n      <DebugOpt>\n        <uSim>0</uSim>\n        <uTrg>1</uTrg>\n        <sLdApp>1</sLdApp>\n        <sGomain>1</sGomain>\n        <sRbreak>1</sRbreak>\n        <sRwatch>1</sRwatch>\n        <sRmem>1</sRmem>\n        <sRfunc>1</sRfunc>\n        <sRbox>1</sRbox>\n        <tLdApp>1</tLdApp>\n        <tGomain>1</tGomain>\n        <tRbreak>1</tRbreak>\n        <tRwatch>1</tRwatch>\n        <tRmem>1</tRmem>\n        <tRfunc>0</tRfunc>\n        <tRbox>1</tRbox>\n        <tRtrace>0</tRtrace>\n        <sRSysVw>1</sRSysVw>\n        <tRSysVw>1</tRSysVw>\n        <sRunDeb>0</sRunDeb>\n        <sLrtime>0</sLrtime>\n        <bEvRecOn>1</bEvRecOn>\n        <bSchkAxf>0</bSchkAxf>\n        <bTchkAxf>0</bTchkAxf>\n        <nTsel>19</nTsel>\n        <sDll></sDll>\n        <sDllPa></sDllPa>\n        <sDlgDll></sDlgDll>\n        <sDlgPa></sDlgPa>\n        <sIfile></sIfile>\n        <tDll></tDll>\n        <tDllPa></tDllPa>\n        <tDlgDll></tDlgDll>\n        <tDlgPa></tDlgPa>\n        <tIfile></tIfile>\n        <pMon>BIN\\lmidk-agdi.dll</pMon>\n      </DebugOpt>\n      <TargetDriverDllRegistry>\n        <SetRegEntry>\n          <Number>0</Number>\n          <Key>DLGUARM</Key>\n        </SetRegEntry>\n        <SetRegEntry>\n          <Number>0</Number>\n          <Key>ARMRTXEVENTFLAGS</Key>\n          <Name>-L70 -Z18 -C0 -M0 -T1</Name>\n        </SetRegEntry>\n        <SetRegEntry>\n          <Number>0</Number>\n          <Key>UL2CM3</Key>\n          <Name>UL2CM3(-O207 -S0 -C0 -FO7  -FN1 -FC1000 -FD20000000 -FF0TM4C123_256 -FL040000 -FS00 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  {
    "path": "sst_c/examples/blinky_button/blinky1.c",
    "content": "/*============================================================================\n* Super-Simple Tasker (SST/C) Example\n*\n* Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n*\n* SPDX-License-Identifier: MIT\n*\n* Permission is hereby granted, free of charge, to any person obtaining a\n* copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included in\n* all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n============================================================================*/\n#include \"sst.h\"           /* SST framework */\n#include \"bsp.h\"           /* Board Support Package interface */\n#include \"blinky_button.h\" /* application shared interface */\n\nDBC_MODULE_NAME(\"blinky1\") /* for DBC assertions in this module */\n\n/*..........................................................................*/\ntypedef struct {      /* Blinky1 task */\n    SST_Task super;   /* inherit SST_Task */\n    SST_TimeEvt te;   /* time event for generating TIMEOUT events */\n    uint16_t toggles; /* number of toggles to perform for TIMEOUT event */\n} Blinky1;\n\nstatic void Blinky1_ctor(Blinky1 * const me);\nstatic void Blinky1_init(Blinky1 * const me, SST_Evt const * const ie);\nstatic void Blinky1_dispatch(Blinky1 * const me, SST_Evt const * const e);\n\n/*..........................................................................*/\nstatic Blinky1 Blinky1_inst; /* the Blinky instance */\nSST_Task * const AO_Blinky1 = &Blinky1_inst.super; /* opaque AO pointer */\n\nvoid Blinky1_instantiate(void) {\n    Blinky1_ctor(&Blinky1_inst);\n}\n\n/*..........................................................................*/\nstatic void Blinky1_ctor(Blinky1 * const me) {\n    SST_Task_ctor(\n       &me->super,\n       (SST_Handler)&Blinky1_init,\n       (SST_Handler)&Blinky1_dispatch);\n    SST_TimeEvt_ctor(&me->te, TIMEOUT_SIG, &me->super);\n}\n/*..........................................................................*/\nstatic void Blinky1_init(Blinky1 * const me, SST_Evt const * const ie) {\n    /* the initial event must be provided and must be WORKLOAD_SIG */\n    DBC_REQUIRE(300,\n        (ie != (SST_Evt const *)0) && (ie->sig == BLINKY_WORK_SIG));\n\n    SST_TimeEvt_arm(&me->te,\n        SST_EVT_DOWNCAST(BlinkyWorkEvt, ie)->ticks,\n        SST_EVT_DOWNCAST(BlinkyWorkEvt, ie)->ticks);\n    me->toggles = SST_EVT_DOWNCAST(BlinkyWorkEvt, ie)->toggles;\n}\n/*..........................................................................*/\nstatic void Blinky1_dispatch(Blinky1 * const me, SST_Evt const * const e) {\n    switch (e->sig) {\n        case TIMEOUT_SIG: {\n            for (uint16_t i = me->toggles; i > 0U; --i) {\n                /* just to exercise SST task scheduler lock... */\n                SST_LockKey key = SST_Task_lock(3U);\n                BSP_d5on();\n                BSP_d5off();\n                SST_Task_unlock(key);\n            }\n            break;\n        }\n        case BLINKY_WORK_SIG: {\n            BSP_d5on();\n            SST_TimeEvt_arm(&me->te,\n                SST_EVT_DOWNCAST(BlinkyWorkEvt, e)->ticks,\n                SST_EVT_DOWNCAST(BlinkyWorkEvt, e)->ticks);\n            me->toggles = SST_EVT_DOWNCAST(BlinkyWorkEvt, e)->toggles;\n            BSP_d5off();\n            break;\n        }\n        default: {\n            DBC_ERROR(500); /* unexpected event */\n            break;\n        }\n    }\n}\n"
  },
  {
    "path": "sst_c/examples/blinky_button/blinky3.c",
    "content": "/*============================================================================\n* Super-Simple Tasker (SST/C) Example\n*\n* Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n*\n* SPDX-License-Identifier: MIT\n*\n* Permission is hereby granted, free of charge, to any person obtaining a\n* copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included in\n* all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n============================================================================*/\n#include \"sst.h\"           /* SST framework */\n#include \"bsp.h\"           /* Board Support Package interface */\n#include \"blinky_button.h\" /* application shared interface */\n\nDBC_MODULE_NAME(\"blinky3\") /* for DBC assertions in this module */\n\n/*..........................................................................*/\ntypedef struct {      /* Blinky3 task */\n    SST_Task super;   /* inherit SST_Task */\n    SST_TimeEvt te;   /* time event for generating TIMEOUT events */\n    uint16_t toggles; /* number of toggles to perform for TIMEOUT event */\n} Blinky3;\n\nstatic void Blinky3_ctor(Blinky3 * const me);\nstatic void Blinky3_init(Blinky3 * const me, SST_Evt const * const ie);\nstatic void Blinky3_dispatch(Blinky3 * const me, SST_Evt const * const e);\n\n/*..........................................................................*/\nstatic Blinky3 Blinky3_inst; /* the Blinky3 instance */\nSST_Task * const AO_Blinky3 = &Blinky3_inst.super; /* opaque AO pointer */\n\nvoid Blinky3_instantiate(void) {\n    Blinky3_ctor(&Blinky3_inst);\n}\n\n/*..........................................................................*/\nstatic void Blinky3_ctor(Blinky3 * const me) {\n    SST_Task_ctor(\n       &me->super,\n       (SST_Handler)&Blinky3_init,\n       (SST_Handler)&Blinky3_dispatch);\n    SST_TimeEvt_ctor(&me->te, TIMEOUT_SIG, &me->super);\n}\n/*..........................................................................*/\nstatic void Blinky3_init(Blinky3 * const me, SST_Evt const * const ie) {\n    /* the initial event must be provided and must be WORKLOAD_SIG */\n    DBC_REQUIRE(300,\n        (ie != (SST_Evt const *)0) && (ie->sig == BLINKY_WORK_SIG));\n\n    SST_TimeEvt_arm(&me->te,\n        SST_EVT_DOWNCAST(BlinkyWorkEvt, ie)->ticks,\n        SST_EVT_DOWNCAST(BlinkyWorkEvt, ie)->ticks);\n    me->toggles = SST_EVT_DOWNCAST(BlinkyWorkEvt, ie)->toggles;\n}\n/*..........................................................................*/\nstatic void Blinky3_dispatch(Blinky3 * const me, SST_Evt const * const e) {\n    switch (e->sig) {\n        case TIMEOUT_SIG: {\n            for (uint16_t i = me->toggles; i > 0U; --i) {\n                BSP_d2on();\n                BSP_d2off();\n            }\n            break;\n        }\n        case BLINKY_WORK_SIG: {\n            BSP_d2on();\n            SST_TimeEvt_arm(&me->te,\n                SST_EVT_DOWNCAST(BlinkyWorkEvt, e)->ticks,\n                SST_EVT_DOWNCAST(BlinkyWorkEvt, e)->ticks);\n            me->toggles = SST_EVT_DOWNCAST(BlinkyWorkEvt, e)->toggles;\n            BSP_d2off();\n            break;\n        }\n        default: {\n            DBC_ERROR(500); /* unexpected event */\n            break;\n        }\n    }\n}\n"
  },
  {
    "path": "sst_c/examples/blinky_button/blinky_button.h",
    "content": "/*============================================================================\n* Super-Simple Tasker (SST/C) Example\n*\n* Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n*\n* SPDX-License-Identifier: MIT\n*\n* Permission is hereby granted, free of charge, to any person obtaining a\n* copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included in\n* all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n============================================================================*/\n#ifndef BLINKY_BUTTON_H_\n#define BLINKY_BUTTON_H_\n\n#include \"dbc_assert.h\" /* Design By Contract (DBC) assertions */\n\nenum Signals {\n    TIMEOUT_SIG,\n    BUTTON_PRESSED_SIG,\n    BUTTON_RELEASED_SIG,\n    BLINKY_WORK_SIG,\n    FORWARD_PRESSED_SIG,\n    FORWARD_RELEASED_SIG,\n    /* ... */\n    MAX_SIG  /* the last signal */\n};\n\ntypedef struct {\n    SST_Evt super;    /* inherit SST_Evt */\n    uint16_t toggles; /* number of toggles of the signal */\n    uint8_t ticks;    /* number of clock ticks between */\n} BlinkyWorkEvt;\n\ntypedef struct {\n    SST_Evt super;    /* inherit SST_Evt */\n    uint16_t toggles; /* number of toggles of the signal */\n} ButtonWorkEvt;\n\nvoid Blinky1_instantiate(void);\nextern SST_Task * const AO_Blinky1;  /* opaque task pointer */\n\nvoid Blinky3_instantiate(void);\nextern SST_Task * const AO_Blinky3;  /* opaque task pointer */\n\nvoid Button2a_instantiate(void);\nextern SST_Task * const AO_Button2a; /* opaque task pointer */\n\nvoid Button2b_instantiate(void);\nextern SST_Task * const AO_Button2b; /* opaque task pointer */\n\n#endif /* BLINKY_BUTTON_H_ */\n"
  },
  {
    "path": "sst_c/examples/blinky_button/bsp.h",
    "content": "/*============================================================================\n* Super-Simple Tasker (SST/C) Example\n*\n* Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n*\n* SPDX-License-Identifier: MIT\n*\n* Permission is hereby granted, free of charge, to any person obtaining a\n* copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included in\n* all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n============================================================================*/\n#ifndef BSP_H_\n#define BSP_H_\n\n#define BSP_TICKS_PER_SEC 1000U\n\nvoid BSP_init(void);\n\nvoid BSP_d1on(void);\nvoid BSP_d1off(void);\n\nvoid BSP_d2on(void);\nvoid BSP_d2off(void);\n\nvoid BSP_d3on(void);\nvoid BSP_d3off(void);\n\nvoid BSP_d4on(void);\nvoid BSP_d4off(void);\n\nvoid BSP_d5on(void);\nvoid BSP_d5off(void);\n\nvoid BSP_d6on(void);\nvoid BSP_d6off(void);\n\n/* immutable events for Blinky tasks */\nSST_Evt const *BSP_getWorkEvtBlinky1(uint8_t num);\nSST_Evt const *BSP_getWorkEvtBlinky3(uint8_t num);\n\n#endif /* BSP_H_ */\n"
  },
  {
    "path": "sst_c/examples/blinky_button/bsp_ek-tm4c123gxl.c",
    "content": "/*============================================================================\n* Super-Simple Tasker (SST/C) Example for TivaC TM4C123GXL\n*\n*                    Q u a n t u m  L e a P s\n*                    ------------------------\n*                    Modern Embedded Software\n*\n* Copyright (C) 2005 Quantum Leaps, <state-machine.com>.\n*\n* SPDX-License-Identifier: MIT\n*\n* Permission is hereby granted, free of charge, to any person obtaining a\n* copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included in\n* all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n============================================================================*/\n#include \"sst.h\"\n#include \"bsp.h\"\n#include \"blinky_button.h\"\n\n#include \"TM4C123GH6PM.h\"  /* the device specific header (TI) */\n#include <math.h>          /* to exercise the FPU */\n/* add other drivers if necessary... */\n\nDBC_MODULE_NAME(\"bsp_ek-tm4c123gxl\") /* for DBC assertions in this module */\n\n/* Local-scope defines -----------------------------------------------------*/\n\n/* test pins on GPIOF */\n#define TST1_PIN  (1U << 1U) /* LED Red */\n#define TST2_PIN  (1U << 2U) /* LED Blue */\n\n/* test pins on GPIOD */\n#define TST3_PIN  (1U << 0U)\n#define TST4_PIN  (1U << 1U)\n#define TST5_PIN  (1U << 2U)\n\n/* test pins on GPIOF */\n#define TST6_PIN  (1U << 3U) /* LED Green */\n\n/* Button on the board on GPIOF */\n#define BTN_SW1      (1U << 4)\n\n/* ISRs used in the application ============================================*/\nvoid SysTick_Handler(void);  /* prototype */\n\nvoid SysTick_Handler(void) { /* system clock tick ISR */\n    BSP_d1on();\n\n    SST_TimeEvt_tick(); /* process all SST time events */\n\n    /* Perform the debouncing of buttons. The algorithm for debouncing\n    * adapted from the book \"Embedded Systems Dictionary\" by Jack Ganssle\n    * and Michael Barr, page 71.\n    */\n    static struct ButtonsDebouncing {\n        uint32_t depressed;\n        uint32_t previous;\n    } buttons = { 0U, 0U };\n    uint32_t current = ~GPIOF_AHB->DATA_Bits[BTN_SW1];\n    uint32_t tmp = buttons.depressed; /* save the debounced depressed */\n    buttons.depressed |= (buttons.previous & current); /* set depressed */\n    buttons.depressed &= (buttons.previous | current); /* clear released */\n    buttons.previous   = current; /* update the history */\n    tmp ^= buttons.depressed;     /* changed debounced depressed */\n    if ((tmp & BTN_SW1) != 0U) {  /* debounced SW1 state changed? */\n        if ((buttons.depressed & BTN_SW1) != 0U) { /* is SW1 depressed? */\n            /* immutable button-press event */\n            static ButtonWorkEvt const pressEvt = {\n                .super.sig = BUTTON_PRESSED_SIG,\n                .toggles = 60U\n            };\n            /* immutable forward-press event */\n            static ButtonWorkEvt const fPressEvt = {\n                .super.sig = FORWARD_PRESSED_SIG,\n                .toggles = 60U\n            };\n            SST_Task_post(AO_Button2a, &fPressEvt.super);\n            SST_Task_post(AO_Button2a, &pressEvt.super);\n        }\n        else { /* B1 is released */\n            /* immutable button-release event */\n            static ButtonWorkEvt const releaseEvt = {\n                .super.sig = BUTTON_RELEASED_SIG,\n                .toggles = 80U\n            };\n            /* immutable forward-release event */\n            static ButtonWorkEvt const fReleaseEvt = {\n                .super.sig = FORWARD_RELEASED_SIG,\n                .toggles = 80U\n            };\n            SST_Task_post(AO_Button2a, &fReleaseEvt.super);\n            SST_Task_post(AO_Button2a, &releaseEvt.super);\n        }\n    }\n\n    BSP_d1off();\n}\n\n/* Assertion handler ======================================================*/\nDBC_NORETURN\nvoid DBC_fault_handler(char const * const module, int const label) {\n    /*\n    * NOTE: add here your application-specific error handling\n    */\n    (void)module;\n    (void)label;\n\n    /* set PRIMASK to disable interrupts and stop SST right here */\n    __asm volatile (\"cpsid i\");\n\n#ifndef NDEBUG\n    for (;;) { /* keep blinking LED2 */\n        BSP_d6on();  /* turn LED2 on */\n        uint32_t volatile ctr;\n        for (ctr = 1000000U; ctr > 0U; --ctr) {\n        }\n        BSP_d6off(); /* turn LED2 off */\n        for (ctr = 1000000U; ctr > 0U; --ctr) {\n        }\n    }\n#endif\n    NVIC_SystemReset();\n}\n/*..........................................................................*/\nvoid assert_failed(char const * const module, int const label);/* prototype */\nvoid assert_failed(char const * const module, int const label) {\n    DBC_fault_handler(module, label);\n}\n\n/* SST task activations ====================================================*/\n/* repurpose regular IRQs for SST Tasks */\n/* prototypes */\nvoid PWM1Gen0_IRQHandler(void);\nvoid PWM1Gen1_IRQHandler(void);\nvoid PWM1Gen2_IRQHandler(void);\nvoid PWM1Gen3_IRQHandler(void);\n\nvoid PWM1Gen0_IRQHandler(void) { SST_Task_activate(AO_Blinky3);  }\nvoid PWM1Gen1_IRQHandler(void) { SST_Task_activate(AO_Button2b); }\nvoid PWM1Gen2_IRQHandler(void) { SST_Task_activate(AO_Button2a); }\nvoid PWM1Gen3_IRQHandler(void) { SST_Task_activate(AO_Blinky1);  }\n\n/* BSP functions ===========================================================*/\nvoid BSP_init(void) {\n    /* Configure the MPU to prevent NULL-pointer dereferencing\n    * see: www.state-machine.com/null-pointer-protection-with-arm-cortex-m-mpu\n    */\n    MPU->RBAR = 0x0U                          /* base address (NULL) */\n                | MPU_RBAR_VALID_Msk          /* valid region */\n                | (MPU_RBAR_REGION_Msk & 7U); /* region #7 */\n    MPU->RASR = (7U << MPU_RASR_SIZE_Pos)     /* 2^(7+1) region */\n                | (0x0U << MPU_RASR_AP_Pos)   /* no-access region */\n                | MPU_RASR_ENABLE_Msk;        /* region enable */\n\n    MPU->CTRL = MPU_CTRL_PRIVDEFENA_Msk       /* enable background region */\n                | MPU_CTRL_ENABLE_Msk;        /* enable the MPU */\n    __ISB();\n    __DSB();\n\n    /* assign IRQs to tasks. NOTE: critical for SST... */\n    SST_Task_setIRQ(AO_Blinky3,  PWM1_0_IRQn);\n    SST_Task_setIRQ(AO_Button2b, PWM1_1_IRQn);\n    SST_Task_setIRQ(AO_Button2a, PWM1_2_IRQn);\n    SST_Task_setIRQ(AO_Blinky1,  PWM1_3_IRQn);\n\n    SYSCTL->RCGCGPIO  |= (1U << 5U); /* enable Run mode for GPIOF */\n    SYSCTL->RCGCGPIO  |= (1U << 3U); /* enable Run mode for GPIOD */\n    __ISB();\n    __DSB();\n\n    SYSCTL->GPIOHBCTL |= (1U << 5); /* enable AHB for GPIOF */\n    SYSCTL->GPIOHBCTL |= (1U << 3); /* enable AHB for GPIOD */\n    __ISB();\n    __DSB();\n\n    /* configure test pins on GPIOF (digital output) */\n    GPIOF_AHB->DIR |= (TST1_PIN | TST2_PIN | TST6_PIN);\n    GPIOF_AHB->DEN |= (TST1_PIN | TST2_PIN | TST6_PIN);\n\n    /* configure button on GPIOF (digital input) */\n    GPIOF_AHB->DIR &= ~(BTN_SW1); /* input */\n    GPIOF_AHB->DEN |= (BTN_SW1); /* digital enable */\n    GPIOF_AHB->PUR |= (BTN_SW1); /* pull-up resistor enable */\n\n    /* configure test pins on GPIOD (digital output) */\n    GPIOD_AHB->DIR |= (TST3_PIN | TST4_PIN | TST5_PIN);\n    GPIOD_AHB->DEN |= (TST3_PIN | TST4_PIN | TST5_PIN);\n}\n\n/*..........................................................................*/\n#if defined __ARMCC_VERSION\n#elif defined __GNUC__\nuint32_t __errno; /* GNU-ARM needs this to link sqrtf() */\n#endif\n\nstatic void exerciseFPU(float x) {\n    /* exercise the single-precision FPU by calculating the identity:\n    *  sqrt(x) == x / sqrt(x) for x > 0\n    */\n    float tmp1 = sqrtf(x); /* single-precision sqrt() */\n    float tmp2 = x / tmp1;\n    DBC_ENSURE(200, (tmp1 - 1e-4f <= tmp2) && (tmp2 <= tmp1 + 1e-4f));\n}\n\n/*..........................................................................*/\nvoid BSP_d1on(void) { /* LED-Red */\n    GPIOF_AHB->DATA_Bits[TST1_PIN] = 0xFFU;\n    /* don't use the FPU in the ISR */\n}\nvoid BSP_d1off(void) {\n    GPIOF_AHB->DATA_Bits[TST1_PIN] = 0x00U;\n}\n/*..........................................................................*/\nvoid BSP_d2on(void) { /* LED-Blue */\n    GPIOF_AHB->DATA_Bits[TST2_PIN] = 0xFFU;\n    exerciseFPU(1.2345f);\n}\nvoid BSP_d2off(void) {\n    GPIOF_AHB->DATA_Bits[TST2_PIN] = 0x00U;\n}\n/*..........................................................................*/\nvoid BSP_d3on(void) {\n    GPIOD_AHB->DATA_Bits[TST3_PIN] = 0xFFU;\n    exerciseFPU(0.345f);\n}\nvoid BSP_d3off(void) {\n    GPIOD_AHB->DATA_Bits[TST3_PIN] = 0x00U;\n}\n/*..........................................................................*/\nvoid BSP_d4on(void) {\n    GPIOD_AHB->DATA_Bits[TST4_PIN] = 0xFFU;\n    exerciseFPU(0.456f);\n}\nvoid BSP_d4off(void) {\n    GPIOD_AHB->DATA_Bits[TST4_PIN] = 0x00U;\n}\n/*..........................................................................*/\nvoid BSP_d5on(void) {\n    GPIOD_AHB->DATA_Bits[TST5_PIN] = 0xFFU;\n    exerciseFPU(1.567f);\n}\nvoid BSP_d5off(void) {\n    GPIOD_AHB->DATA_Bits[TST5_PIN] = 0x00U;\n}\n/*..........................................................................*/\nvoid BSP_d6on(void) {  /* LED2-Green */\n    GPIOF_AHB->DATA_Bits[TST6_PIN] = 0xFFU;\n    exerciseFPU(1.2345f);\n}\nvoid BSP_d6off(void) {\n    GPIOF_AHB->DATA_Bits[TST6_PIN] = 0x00U;\n}\n\n/*..........................................................................*/\nSST_Evt const *BSP_getWorkEvtBlinky1(uint8_t num) {\n    /* immutable work events for Blinky1 */\n    static BlinkyWorkEvt const workBlinky1[] = {\n        {\n            .super.sig = BLINKY_WORK_SIG,\n            .toggles = 40U,\n            .ticks = 5U,\n        },\n        {\n            .super.sig = BLINKY_WORK_SIG,\n            .toggles = 30U,\n            .ticks = 7U,\n        }\n    };\n    DBC_REQUIRE(500, num < ARRAY_NELEM(workBlinky1)); /* must be in range */\n    return &workBlinky1[num].super;\n}\n/*..........................................................................*/\nSST_Evt const *BSP_getWorkEvtBlinky3(uint8_t num) {\n    /* immutable work events for Blinky3 */\n    static BlinkyWorkEvt const workBlinky3[] = {\n        {\n            .super.sig = BLINKY_WORK_SIG,\n            .toggles = 20U,\n            .ticks = 5U,\n        },\n        {\n            .super.sig = BLINKY_WORK_SIG,\n            .toggles = 10U,\n            .ticks = 3U,\n        }\n    };\n    DBC_REQUIRE(600, num < ARRAY_NELEM(workBlinky3)); /* must be in range */\n    return &workBlinky3[num].super;\n}\n\n/* SST callbacks ===========================================================*/\nvoid SST_onStart(void) {\n    SystemCoreClockUpdate();\n\n    /* set up the SysTick timer to fire at BSP_TICKS_PER_SEC rate */\n    SysTick_Config((SystemCoreClock / BSP_TICKS_PER_SEC) + 1U);\n\n    /* set priorities of ISRs used in the system */\n    NVIC_SetPriority(SysTick_IRQn, 0U);\n    /* ... */\n}\n/*..........................................................................*/\nvoid SST_onIdle(void) {\n    BSP_d6on();  /* turn LED-Green on */\n#ifdef NDEBUG\n    /* Put the CPU and peripherals to the low-power mode.\n    * you might need to customize the clock management for your application,\n    * see the datasheet for your particular Cortex-M MCU.\n    */\n    BSP_d6off(); /* turn LED-Green off */\n    __WFI(); /* Wait-For-Interrupt */\n    BSP_d6on();  /* turn LED-Green on */\n#endif\n    BSP_d6off(); /* turn LED-Green off */\n}\n\n"
  },
  {
    "path": "sst_c/examples/blinky_button/bsp_nucleo-c031c6.c",
    "content": "/*============================================================================\n* Super-Simple Tasker (SST/C) Example for STM32 NUCLEO-C031C6\n*\n*                    Q u a n t u m  L e a P s\n*                    ------------------------\n*                    Modern Embedded Software\n*\n* Copyright (C) 2005 Quantum Leaps, <state-machine.com>.\n*\n* SPDX-License-Identifier: MIT\n*\n* Permission is hereby granted, free of charge, to any person obtaining a\n* copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included in\n* all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n============================================================================*/\n#include \"sst.h\"\n#include \"bsp.h\"\n#include \"blinky_button.h\"\n\n#include \"stm32c0xx.h\"  /* CMSIS-compliant header file for the MCU used */\n/* add other drivers if necessary... */\n\nDBC_MODULE_NAME(\"bsp_nucleo-c031c6\")\n\n/* Local-scope defines -----------------------------------------------------*/\n/* test pins on GPIO PA */\n#define TST1_PIN  7U\n#define TST2_PIN  6U\n#define TST3_PIN  4U\n#define TST4_PIN  1U\n#define TST5_PIN  0U\n#define TST6_PIN  5U /* LED L4-Green */\n\n/* buttons on GPIO PC */\n#define B1_PIN    13U\n\n/* ISRs used in the application ============================================*/\nvoid SysTick_Handler(void);  /* prototype */\n\nvoid SysTick_Handler(void) { /* system clock tick ISR */\n    BSP_d1on();\n\n    SST_TimeEvt_tick(); /* process all SST time events */\n\n    /* Perform the debouncing of buttons. The algorithm for debouncing\n    * adapted from the book \"Embedded Systems Dictionary\" by Jack Ganssle\n    * and Michael Barr, page 71.\n    */\n    static struct ButtonsDebouncing {\n        uint32_t depressed;\n        uint32_t previous;\n    } buttons = { 0U, 0U };\n    uint32_t current = ~GPIOC->IDR; /* read GPIO PortC */\n    uint32_t tmp = buttons.depressed; /* save the debounced depressed */\n    buttons.depressed |= (buttons.previous & current); /* set depressed */\n    buttons.depressed &= (buttons.previous | current); /* clear released */\n    buttons.previous   = current; /* update the history */\n    tmp ^= buttons.depressed;     /* changed debounced depressed */\n    if ((tmp & (1U << B1_PIN)) != 0U) { /* debounced B1 state changed? */\n        if ((buttons.depressed & (1U << B1_PIN)) != 0U) { /* depressed? */\n            /* immutable button-press event */\n            static ButtonWorkEvt const pressEvt = {\n                .super.sig = BUTTON_PRESSED_SIG,\n                .toggles = 60U\n            };\n            /* immutable forward-press event */\n            static ButtonWorkEvt const fPressEvt = {\n                .super.sig = FORWARD_PRESSED_SIG,\n                .toggles = 60U\n            };\n            SST_Task_post(AO_Button2a, &fPressEvt.super);\n            SST_Task_post(AO_Button2a, &pressEvt.super);\n        }\n        else { /* B1 is released */\n            /* immutable button-release event */\n            static ButtonWorkEvt const releaseEvt = {\n                .super.sig = BUTTON_RELEASED_SIG,\n                .toggles = 80U\n            };\n            /* immutable forward-release event */\n            static ButtonWorkEvt const fReleaseEvt = {\n                .super.sig = FORWARD_RELEASED_SIG,\n                .toggles = 80U\n            };\n            SST_Task_post(AO_Button2a, &fReleaseEvt.super);\n            SST_Task_post(AO_Button2a, &releaseEvt.super);\n        }\n    }\n\n    BSP_d1off();\n}\n\n/* Assertion handler ======================================================*/\nDBC_NORETURN\nvoid DBC_fault_handler(char const * const module, int const label) {\n    /*\n    * NOTE: add here your application-specific error handling\n    */\n    (void)module;\n    (void)label;\n\n    /* set PRIMASK to disable interrupts and stop SST right here */\n    __asm volatile (\"cpsid i\");\n\n#ifndef NDEBUG\n    for (;;) { /* keep blinking LED2 */\n        BSP_d6on();  /* turn LD4 on */\n        uint32_t volatile ctr;\n        for (ctr = 100000U; ctr > 0U; --ctr) {\n        }\n        BSP_d6off(); /* turn LD4 off */\n        for (ctr = 100000U; ctr > 0U; --ctr) {\n        }\n    }\n#endif\n    NVIC_SystemReset();\n}\n/*..........................................................................*/\nvoid assert_failed(char const * const module, int const label);/* prototype */\nvoid assert_failed(char const * const module, int const label) {\n    DBC_fault_handler(module, label);\n}\n\n/* SST task activations ====================================================*/\n/* preprocessor switch to choose between regular and reserved IRQs */\n#define REGULAR_IRQS\n\n#ifdef REGULAR_IRQS\n/* repurpose regular IRQs for SST Tasks */\n/* prototypes */\nvoid TIM3_IRQHandler(void);\nvoid TIM14_IRQHandler(void);\nvoid TIM16_IRQHandler(void);\nvoid TIM17_IRQHandler(void);\n\nvoid TIM3_IRQHandler(void)  { SST_Task_activate(AO_Blinky3);  }\nvoid TIM14_IRQHandler(void) { SST_Task_activate(AO_Button2b); }\nvoid TIM16_IRQHandler(void) { SST_Task_activate(AO_Button2a); }\nvoid TIM17_IRQHandler(void) { SST_Task_activate(AO_Blinky1);  }\n\n#else /* use reserved IRQs for SST Tasks */\n/* prototypes */\nvoid Reserved1_IRQHandler(void);\nvoid Reserved8_IRQHandler(void);\nvoid Reserved15_IRQHandler(void);\nvoid Reserved17_IRQHandler(void);\n\nvoid Reserved1_IRQHandler(void)  { SST_Task_activate(AO_Blinky3);  }\nvoid Reserved8_IRQHandler(void)  { SST_Task_activate(AO_Button2b); }\nvoid Reserved15_IRQHandler(void) { SST_Task_activate(AO_Button2a); }\nvoid Reserved17_IRQHandler(void) { SST_Task_activate(AO_Blinky1);  }\n#endif\n\n/* BSP functions ===========================================================*/\nvoid BSP_init(void) {\n    /* Configure the MPU to prevent NULL-pointer dereferencing\n    * see: www.state-machine.com/null-pointer-protection-with-arm-cortex-m-mpu\n    */\n    MPU->RBAR = 0x0U                          /* base address (NULL) */\n                | MPU_RBAR_VALID_Msk          /* valid region */\n                | (MPU_RBAR_REGION_Msk & 7U); /* region #7 */\n    MPU->RASR = (7U << MPU_RASR_SIZE_Pos)     /* 2^(7+1) region */\n                | (0x0U << MPU_RASR_AP_Pos)   /* no-access region */\n                | MPU_RASR_ENABLE_Msk;        /* region enable */\n\n    MPU->CTRL = MPU_CTRL_PRIVDEFENA_Msk       /* enable background region */\n                | MPU_CTRL_ENABLE_Msk;        /* enable the MPU */\n    __ISB();\n    __DSB();\n\n    /* assign IRQs to tasks. NOTE: critical for SST... */\n#ifdef REGULAR_IRQS\n    /* repurpose regular IRQs for SST Tasks */\n    SST_Task_setIRQ(AO_Blinky3,  TIM3_IRQn);\n    SST_Task_setIRQ(AO_Button2b, TIM14_IRQn);\n    SST_Task_setIRQ(AO_Button2a, TIM16_IRQn);\n    SST_Task_setIRQ(AO_Blinky1,  TIM17_IRQn);\n#else\n    /* use reserved IRQs for SST Tasks */\n    SST_Task_setIRQ(AO_Blinky3,  1U);\n    SST_Task_setIRQ(AO_Button2b, 8U);\n    SST_Task_setIRQ(AO_Button2a, 15U);\n    SST_Task_setIRQ(AO_Blinky1,  17U);\n#endif\n\n    /* enable GPIO port PA clock */\n    RCC->IOPENR |= (1U << 0U);\n\n    /* set all used GPIOA pins as push-pull output, no pull-up, pull-down */\n    GPIOA->MODER &=\n        ~((3U << 2U*TST1_PIN) | (3U << 2U*TST2_PIN) | (3U << 2U*TST3_PIN) |\n          (3U << 2U*TST4_PIN) | (3U << 2U*TST5_PIN) | (3U << 2U*TST6_PIN));\n    GPIOA->MODER |=\n         ((1U << 2U*TST1_PIN) | (1U << 2U*TST2_PIN) | (1U << 2U*TST3_PIN) |\n          (1U << 2U*TST4_PIN) | (1U << 2U*TST5_PIN) | (1U << 2U*TST6_PIN));\n    GPIOA->OTYPER &=\n        ~((1U <<    TST1_PIN) | (1U <<    TST2_PIN) | (1U <<    TST3_PIN) |\n          (1U <<    TST4_PIN) | (1U <<    TST5_PIN) | (1U <<    TST6_PIN));\n    GPIOA->OSPEEDR &=\n        ~((3U << 2U*TST1_PIN) | (3U << 2U*TST2_PIN) | (3U << 2U*TST3_PIN) |\n          (3U << 2U*TST4_PIN) | (3U << 2U*TST5_PIN) | (3U << 2U*TST6_PIN));\n    GPIOA->OSPEEDR |=\n         ((1U << 2U*TST1_PIN) | (1U << 2U*TST2_PIN) | (1U << 2U*TST3_PIN) |\n          (1U << 2U*TST4_PIN) | (1U << 2U*TST5_PIN) | (1U << 2U*TST6_PIN));\n   GPIOA->PUPDR &=\n        ~((3U << 2U*TST1_PIN) | (3U << 2U*TST2_PIN) | (3U << 2U*TST3_PIN) |\n          (3U << 2U*TST4_PIN) | (3U << 2U*TST5_PIN) | (3U << 2U*TST6_PIN));\n\n    /* enable GPIOC clock port for the Button B1 */\n    RCC->IOPENR |=  (1U << 2U);\n\n    /* configure Button B1 pin on GPIOC as input, no pull-up, pull-down */\n    GPIOC->MODER &= ~(3U << 2U*B1_PIN);\n    GPIOC->PUPDR &= ~(3U << 2U*B1_PIN);\n}\n\n/*..........................................................................*/\nvoid BSP_d1on(void)  { GPIOA->BSRR = (1U << TST1_PIN);         }\nvoid BSP_d1off(void) { GPIOA->BSRR = (1U << (TST1_PIN + 16U)); }\n/*..........................................................................*/\nvoid BSP_d2on(void)  { GPIOA->BSRR = (1U << TST2_PIN);         }\nvoid BSP_d2off(void) { GPIOA->BSRR = (1U << (TST2_PIN + 16U)); }\n/*..........................................................................*/\nvoid BSP_d3on(void)  { GPIOA->BSRR = (1U << TST3_PIN);         }\nvoid BSP_d3off(void) { GPIOA->BSRR = (1U << (TST3_PIN + 16U)); }\n/*..........................................................................*/\nvoid BSP_d4on(void)  { GPIOA->BSRR = (1U << TST4_PIN);         }\nvoid BSP_d4off(void) { GPIOA->BSRR = (1U << (TST4_PIN + 16U)); }\n/*..........................................................................*/\nvoid BSP_d5on(void)  { GPIOA->BSRR = (1U << TST5_PIN);         }\nvoid BSP_d5off(void) { GPIOA->BSRR = (1U << (TST5_PIN + 16U)); }\n/*..........................................................................*/\nvoid BSP_d6on(void)  { GPIOA->BSRR = (1U << TST6_PIN);         } /* LD4 */\nvoid BSP_d6off(void) { GPIOA->BSRR = (1U << (TST6_PIN + 16U)); }\n\n/*..........................................................................*/\nSST_Evt const *BSP_getWorkEvtBlinky1(uint8_t num) {\n    /* immutable work events for Blinky1 */\n    static BlinkyWorkEvt const workBlinky1[] = {\n        {\n            .super.sig = BLINKY_WORK_SIG,\n            .toggles = 40U,\n            .ticks = 5U,\n        },\n        {\n            .super.sig = BLINKY_WORK_SIG,\n            .toggles = 30U,\n            .ticks = 7U,\n        }\n    };\n    DBC_REQUIRE(500, num < ARRAY_NELEM(workBlinky1)); /* must be in range */\n    return &workBlinky1[num].super;\n}\n/*..........................................................................*/\nSST_Evt const *BSP_getWorkEvtBlinky3(uint8_t num) {\n    /* immutable work events for Blinky3 */\n    static BlinkyWorkEvt const workBlinky3[] = {\n        {\n            .super.sig = BLINKY_WORK_SIG,\n            .toggles = 20U,\n            .ticks = 5U,\n        },\n        {\n            .super.sig = BLINKY_WORK_SIG,\n            .toggles = 10U,\n            .ticks = 3U,\n        }\n    };\n    DBC_REQUIRE(600, num < ARRAY_NELEM(workBlinky3)); /* must be in range */\n    return &workBlinky3[num].super;\n}\n\n/* SST callbacks ===========================================================*/\nvoid SST_onStart(void) {\n    SystemCoreClockUpdate();\n\n    /* set up the SysTick timer to fire at BSP_TICKS_PER_SEC rate */\n    SysTick_Config((SystemCoreClock / BSP_TICKS_PER_SEC) + 1U);\n\n    /* set priorities of ISRs used in the system */\n    NVIC_SetPriority(SysTick_IRQn, 0U);\n    /* ... */\n}\n/*..........................................................................*/\nvoid SST_onIdle(void) {\n    BSP_d6on();  /* turn LED2 on */\n#ifdef NDEBUG\n    /* Put the CPU and peripherals to the low-power mode.\n    * you might need to customize the clock management for your application,\n    * see the datasheet for your particular Cortex-M MCU.\n    */\n    BSP_d6off(); /* turn LED2 off */\n    __WFI(); /* Wait-For-Interrupt */\n    BSP_d6on();  /* turn LED2 on */\n#endif\n    BSP_d6off(); /* turn LED2 off */\n}\n\n"
  },
  {
    "path": "sst_c/examples/blinky_button/bsp_nucleo-h743zi.c",
    "content": "/*============================================================================\n* Super-Simple Tasker (SST/C) Example for STM32 NUCLEO-H743ZI\n*\n*                    Q u a n t u m  L e a P s\n*                    ------------------------\n*                    Modern Embedded Software\n*\n* Copyright (C) 2005 Quantum Leaps, <state-machine.com>.\n*\n* SPDX-License-Identifier: MIT\n*\n* Permission is hereby granted, free of charge, to any person obtaining a\n* copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included in\n* all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n============================================================================*/\n#include \"sst.h\"\n#include \"bsp.h\"\n#include \"blinky_button.h\"\n\n#include \"stm32h743xx.h\"  /* CMSIS-compliant header file for the MCU used */\n#include <math.h>         /* to exercise the FPU */\n/* add other drivers if necessary... */\n\nDBC_MODULE_NAME(\"bsp_nucleo-h743zi\") /* for DBC assertions in this module */\n\n/* Local-scope defines -----------------------------------------------------*/\n\n/* test pins on GPIO PB */\n#define TST1_PIN  0U  /* PB.0  LED1-Green */\n#define TST2_PIN  14U /* PB.14 LED3-Red   */\n#define TST3_PIN  4U\n#define TST4_PIN  5U\n#define TST5_PIN  6U\n#define TST6_PIN  7U  /* PB.7  LED2-Blue  */\n\n/* buttons on GPIO PC */\n#define B1_PIN    13U\n\n/* ISRs used in the application ============================================*/\nvoid SysTick_Handler(void);  /* prototype */\n\nvoid SysTick_Handler(void) { /* system clock tick ISR */\n    BSP_d1on();\n\n    SST_TimeEvt_tick(); /* process all SST time events */\n\n    /* Perform the debouncing of buttons. The algorithm for debouncing\n    * adapted from the book \"Embedded Systems Dictionary\" by Jack Ganssle\n    * and Michael Barr, page 71.\n    */\n    static struct ButtonsDebouncing {\n        uint32_t depressed;\n        uint32_t previous;\n    } buttons = { 0U, 0U };\n    uint32_t current = GPIOC->IDR; /* read GPIO PortC */\n    uint32_t tmp = buttons.depressed; /* save the debounced depressed */\n    buttons.depressed |= (buttons.previous & current); /* set depressed */\n    buttons.depressed &= (buttons.previous | current); /* clear released */\n    buttons.previous   = current; /* update the history */\n    tmp ^= buttons.depressed;     /* changed debounced depressed */\n    if ((tmp & (1U << B1_PIN)) != 0U) { /* debounced B1 state changed? */\n        if ((buttons.depressed & (1U << B1_PIN)) != 0U) { /* depressed? */\n            /* immutable button-press event */\n            static ButtonWorkEvt const pressEvt = {\n                .super.sig = BUTTON_PRESSED_SIG,\n                .toggles = 60U\n            };\n            /* immutable forward-press event */\n            static ButtonWorkEvt const fPressEvt = {\n                .super.sig = FORWARD_PRESSED_SIG,\n                .toggles = 60U\n            };\n            SST_Task_post(AO_Button2a, &fPressEvt.super);\n            SST_Task_post(AO_Button2a, &pressEvt.super);\n        }\n        else { /* B1 is released */\n            /* immutable button-release event */\n            static ButtonWorkEvt const releaseEvt = {\n                .super.sig = BUTTON_RELEASED_SIG,\n                .toggles = 80U\n            };\n            /* immutable forward-release event */\n            static ButtonWorkEvt const fReleaseEvt = {\n                .super.sig = FORWARD_RELEASED_SIG,\n                .toggles = 80U\n            };\n            SST_Task_post(AO_Button2a, &fReleaseEvt.super);\n            SST_Task_post(AO_Button2a, &releaseEvt.super);\n        }\n    }\n\n    BSP_d1off();\n}\n\n/* Assertion handler ======================================================*/\nDBC_NORETURN\nvoid DBC_fault_handler(char const * const module, int const label) {\n    /*\n    * NOTE: add here your application-specific error handling\n    */\n    (void)module;\n    (void)label;\n\n    /* set PRIMASK to disable interrupts and stop SST right here */\n    __asm volatile (\"cpsid i\");\n\n#ifndef NDEBUG\n    for (;;) { /* keep blinking LED2 */\n        BSP_d6on();  /* turn LED2 on */\n        uint32_t volatile ctr;\n        for (ctr = 1000000U; ctr > 0U; --ctr) {\n        }\n        BSP_d6off(); /* turn LED2 off */\n        for (ctr = 1000000U; ctr > 0U; --ctr) {\n        }\n    }\n#endif\n    NVIC_SystemReset();\n}\n/*..........................................................................*/\nvoid assert_failed(char const * const module, int const label);/* prototype */\nvoid assert_failed(char const * const module, int const label) {\n    DBC_fault_handler(module, label);\n}\n\n/* SST task activations ====================================================*/\n/* preprocessor switch to choose between regular and reserved IRQs */\n#define REGULAR_IRQS\n\n#ifdef REGULAR_IRQS\n/* repurpose regular IRQs for SST Tasks */\n/* prototypes */\nvoid OTG_FS_EP1_OUT_IRQHandler(void);\nvoid OTG_FS_EP1_IN_IRQHandler(void);\nvoid OTG_FS_WKUP_IRQHandler(void);\nvoid OTG_FS_IRQHandler(void);\n\nvoid OTG_FS_EP1_OUT_IRQHandler(void) { SST_Task_activate(AO_Blinky3);  }\nvoid OTG_FS_EP1_IN_IRQHandler(void)  { SST_Task_activate(AO_Button2b); }\nvoid OTG_FS_WKUP_IRQHandler(void)    { SST_Task_activate(AO_Button2a); }\nvoid OTG_FS_IRQHandler(void)         { SST_Task_activate(AO_Blinky1);  }\n\n#else /* use reserved IRQs for SST Tasks */\n/* prototypes */\nvoid Reserved42_IRQHandler(void);\nvoid Reserved64_IRQHandler(void);\nvoid Reserved65_IRQHandler(void);\nvoid Reserved66_IRQHandler(void);\n\nvoid Reserved42_IRQHandler(void) { SST_Task_activate(AO_Blinky3);  }\nvoid Reserved64_IRQHandler(void) { SST_Task_activate(AO_Button2b); }\nvoid Reserved65_IRQHandler(void) { SST_Task_activate(AO_Button2a); }\nvoid Reserved66_IRQHandler(void) { SST_Task_activate(AO_Blinky1);  }\n#endif\n\n/* BSP functions ===========================================================*/\nvoid BSP_init(void) {\n    /* Configure the MPU to prevent NULL-pointer dereferencing\n    * see: www.state-machine.com/null-pointer-protection-with-arm-cortex-m-mpu\n    */\n    MPU->RBAR = 0x0U                          /* base address (NULL) */\n                | MPU_RBAR_VALID_Msk          /* valid region */\n                | (MPU_RBAR_REGION_Msk & 7U); /* region #7 */\n    MPU->RASR = (7U << MPU_RASR_SIZE_Pos)     /* 2^(7+1) region */\n                | (0x0U << MPU_RASR_AP_Pos)   /* no-access region */\n                | MPU_RASR_ENABLE_Msk;        /* region enable */\n\n    MPU->CTRL = MPU_CTRL_PRIVDEFENA_Msk       /* enable background region */\n                | MPU_CTRL_ENABLE_Msk;        /* enable the MPU */\n    __ISB();\n    __DSB();\n\n    SCB_EnableICache(); /* Enable I-Cache */\n    SCB_EnableDCache(); /* Enable D-Cache */\n\n    /* assign IRQs to tasks. NOTE: critical for SST... */\n#ifdef REGULAR_IRQS\n    /* repurpose regular IRQs for SST Tasks */\n    SST_Task_setIRQ(AO_Blinky3,  OTG_FS_EP1_OUT_IRQn);\n    SST_Task_setIRQ(AO_Button2b, OTG_FS_EP1_IN_IRQn);\n    SST_Task_setIRQ(AO_Button2a, OTG_FS_WKUP_IRQn);\n    SST_Task_setIRQ(AO_Blinky1,  OTG_FS_IRQn);\n#else\n    /* use reserved IRQs for SST Tasks */\n    SST_Task_setIRQ(AO_Blinky3,  42U);\n    SST_Task_setIRQ(AO_Button2b, 64U);\n    SST_Task_setIRQ(AO_Button2a, 65U);\n    SST_Task_setIRQ(AO_Blinky1,  66U);\n#endif\n\n    /* enable GPIOB port clock for LEds and test pins */\n    RCC->AHB4ENR |= RCC_AHB4ENR_GPIOBEN;\n\n    /* set all used GPIOB pins as push-pull output, no pull-up, pull-down */\n    GPIOB->MODER &=\n        ~((3U << 2U*TST1_PIN) | (3U << 2U*TST2_PIN) | (3U << 2U*TST3_PIN) |\n          (3U << 2U*TST4_PIN) | (3U << 2U*TST5_PIN) | (3U << 2U*TST6_PIN));\n    GPIOB->MODER |=\n         ((1U << 2U*TST1_PIN) | (1U << 2U*TST2_PIN) | (1U << 2U*TST3_PIN) |\n          (1U << 2U*TST4_PIN) | (1U << 2U*TST5_PIN) | (1U << 2U*TST6_PIN));\n    GPIOB->OTYPER &=\n        ~((1U <<    TST1_PIN) | (1U <<    TST2_PIN) | (1U <<    TST3_PIN) |\n          (1U <<    TST4_PIN) | (1U <<    TST5_PIN) | (1U <<    TST6_PIN));\n    GPIOB->PUPDR &=\n        ~((3U << 2U*TST1_PIN) | (3U << 2U*TST2_PIN) | (3U << 2U*TST3_PIN) |\n          (3U << 2U*TST4_PIN) | (3U << 2U*TST5_PIN) | (3U << 2U*TST6_PIN));\n\n    /* enable GPIOC clock port for the Button B1 */\n    RCC->AHB4ENR |= RCC_AHB4ENR_GPIOCEN;\n\n    /* configure Button B1 pin on GPIOC as input, no pull-up, pull-down */\n    GPIOC->MODER   &= ~(3U << 2U*B1_PIN);\n    GPIOC->PUPDR   &= ~(GPIO_PUPDR_PUPD0 << 2U*B1_PIN);\n    GPIOC->PUPDR   |=  (2U << 2U*B1_PIN);\n}\n\n/*..........................................................................*/\nstatic void exerciseFPU(double x) {\n    /* exercise the double-precision FPU by calculating the identity:\n    *  sin(x)^2 + cos(x)^2 == 1.0 for any x\n    */\n    double tmp = pow(sin(x), 2.0) + pow(cos(x), 2.0);\n    DBC_ENSURE(200, (1.0 - 1e-4 < tmp) && (tmp < 1.0 + 1e-4));\n}\n\n/*..........................................................................*/\nvoid BSP_d1on(void) {  /* LED1-Green */\n    GPIOB->BSRR = (1U << TST1_PIN);\n    /* don't use the FPU in the ISR */\n}\nvoid BSP_d1off(void) {\n    GPIOB->BSRR = (1U << (TST1_PIN + 16U));\n}\n/*..........................................................................*/\nvoid BSP_d2on(void) {  /* LED3-Red */\n    GPIOB->BSRR = (1U << TST2_PIN);\n    exerciseFPU(-1.2345);\n}\nvoid BSP_d2off(void) {\n    GPIOB->BSRR = (1U << (TST2_PIN + 16U));\n}\n/*..........................................................................*/\nvoid BSP_d3on(void) {\n    GPIOB->BSRR = (1U << TST3_PIN);\n    exerciseFPU(-12.345);\n}\nvoid BSP_d3off(void) {\n    GPIOB->BSRR = (1U << (TST3_PIN + 16U));\n}\n/*..........................................................................*/\nvoid BSP_d4on(void) {\n    GPIOB->BSRR = (1U << TST4_PIN);\n    exerciseFPU(3.456);\n}\nvoid BSP_d4off(void) {\n    GPIOB->BSRR = (1U << (TST4_PIN + 16U));\n}\n/*..........................................................................*/\nvoid BSP_d5on(void) {\n    GPIOB->BSRR = (1U << TST5_PIN);\n    exerciseFPU(4.567);\n}\nvoid BSP_d5off(void) {\n    GPIOB->BSRR = (1U << (TST5_PIN + 16U));\n}\n/*..........................................................................*/\nvoid BSP_d6on(void) {  /* LED2-Blue */\n    GPIOB->BSRR = (1U << TST6_PIN);\n    exerciseFPU(1.2345);\n}\nvoid BSP_d6off(void) {\n    GPIOB->BSRR = (1U << (TST6_PIN + 16U));\n}\n\n/*..........................................................................*/\nSST_Evt const *BSP_getWorkEvtBlinky1(uint8_t num) {\n    /* immutable work events for Blinky1 */\n    static BlinkyWorkEvt const workBlinky1[] = {\n        {\n            .super.sig = BLINKY_WORK_SIG,\n            .toggles = 40U,\n            .ticks = 5U,\n        },\n        {\n            .super.sig = BLINKY_WORK_SIG,\n            .toggles = 30U,\n            .ticks = 7U,\n        }\n    };\n    DBC_REQUIRE(500, num < ARRAY_NELEM(workBlinky1)); /* must be in range */\n    return &workBlinky1[num].super;\n}\n/*..........................................................................*/\nSST_Evt const *BSP_getWorkEvtBlinky3(uint8_t num) {\n    /* immutable work events for Blinky3 */\n    static BlinkyWorkEvt const workBlinky3[] = {\n        {\n            .super.sig = BLINKY_WORK_SIG,\n            .toggles = 20U,\n            .ticks = 5U,\n        },\n        {\n            .super.sig = BLINKY_WORK_SIG,\n            .toggles = 10U,\n            .ticks = 3U,\n        }\n    };\n    DBC_REQUIRE(600, num < ARRAY_NELEM(workBlinky3)); /* must be in range */\n    return &workBlinky3[num].super;\n}\n\n/* SST callbacks ===========================================================*/\nvoid SST_onStart(void) {\n    SystemCoreClockUpdate();\n\n    /* set up the SysTick timer to fire at BSP_TICKS_PER_SEC rate */\n    SysTick_Config((SystemCoreClock / BSP_TICKS_PER_SEC) + 1U);\n\n    /* set priorities of ISRs used in the system */\n    NVIC_SetPriority(SysTick_IRQn, 0U);\n    /* ... */\n}\n/*..........................................................................*/\nvoid SST_onIdle(void) {\n    BSP_d6on();  /* turn LED2 on */\n#ifdef NDEBUG\n    /* Put the CPU and peripherals to the low-power mode.\n    * you might need to customize the clock management for your application,\n    * see the datasheet for your particular Cortex-M MCU.\n    */\n    BSP_d6off(); /* turn LED2 off */\n    __WFI(); /* Wait-For-Interrupt */\n    BSP_d6on();  /* turn LED2 on */\n#endif\n    BSP_d6off(); /* turn LED2 off */\n}\n\n"
  },
  {
    "path": "sst_c/examples/blinky_button/bsp_nucleo-l053r8.c",
    "content": "/*============================================================================\n* Super-Simple Tasker (SST/C) Example for STM32 NUCLEO-L053R8\n*\n*                    Q u a n t u m  L e a P s\n*                    ------------------------\n*                    Modern Embedded Software\n*\n* Copyright (C) 2005 Quantum Leaps, <state-machine.com>.\n*\n* SPDX-License-Identifier: MIT\n*\n* Permission is hereby granted, free of charge, to any person obtaining a\n* copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included in\n* all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n============================================================================*/\n#include \"sst.h\"\n#include \"bsp.h\"\n#include \"blinky_button.h\"\n\n#include \"stm32l0xx.h\"  /* CMSIS-compliant header file for the MCU used */\n/* add other drivers if necessary... */\n\nDBC_MODULE_NAME(\"bsp_nucleo-l053r8\") /* for DBC assertions in this module */\n\n/* Local-scope defines -----------------------------------------------------*/\n\n/* test pins on GPIO PA */\n#define TST1_PIN  7U\n#define TST2_PIN  6U\n#define TST3_PIN  4U\n#define TST4_PIN  1U\n#define TST5_PIN  0U\n#define TST6_PIN  5U /* LED LD2-Green */\n\n/* buttons on GPIO PC */\n#define B1_PIN    13U\n\n/* ISRs used in the application ============================================*/\nvoid SysTick_Handler(void);  /* prototype */\n\nvoid SysTick_Handler(void) { /* system clock tick ISR */\n    BSP_d1on();\n\n    SST_TimeEvt_tick(); /* process all SST time events */\n\n    /* Perform the debouncing of buttons. The algorithm for debouncing\n    * adapted from the book \"Embedded Systems Dictionary\" by Jack Ganssle\n    * and Michael Barr, page 71.\n    */\n    static struct ButtonsDebouncing {\n        uint32_t depressed;\n        uint32_t previous;\n    } buttons = { 0U, 0U };\n    uint32_t current = ~GPIOC->IDR; /* read GPIO PortC */\n    uint32_t tmp = buttons.depressed; /* save the debounced depressed */\n    buttons.depressed |= (buttons.previous & current); /* set depressed */\n    buttons.depressed &= (buttons.previous | current); /* clear released */\n    buttons.previous   = current; /* update the history */\n    tmp ^= buttons.depressed;     /* changed debounced depressed */\n    if ((tmp & (1U << B1_PIN)) != 0U) { /* debounced B1 state changed? */\n        if ((buttons.depressed & (1U << B1_PIN)) != 0U) { /* depressed? */\n            /* immutable button-press event */\n            static ButtonWorkEvt const pressEvt = {\n                .super.sig = BUTTON_PRESSED_SIG,\n                .toggles = 60U\n            };\n            /* immutable forward-press event */\n            static ButtonWorkEvt const fPressEvt = {\n                .super.sig = FORWARD_PRESSED_SIG,\n                .toggles = 60U\n            };\n            SST_Task_post(AO_Button2a, &fPressEvt.super);\n            SST_Task_post(AO_Button2a, &pressEvt.super);\n        }\n        else { /* B1 is released */\n            /* immutable button-release event */\n            static ButtonWorkEvt const releaseEvt = {\n                .super.sig = BUTTON_RELEASED_SIG,\n                .toggles = 80U\n            };\n            /* immutable forward-release event */\n            static ButtonWorkEvt const fReleaseEvt = {\n                .super.sig = FORWARD_RELEASED_SIG,\n                .toggles = 80U\n            };\n            SST_Task_post(AO_Button2a, &fReleaseEvt.super);\n            SST_Task_post(AO_Button2a, &releaseEvt.super);\n        }\n    }\n\n    BSP_d1off();\n}\n\n/* Assertion handler ======================================================*/\nDBC_NORETURN\nvoid DBC_fault_handler(char const * const module, int const label) {\n    /*\n    * NOTE: add here your application-specific error handling\n    */\n    (void)module;\n    (void)label;\n\n    /* set PRIMASK to disable interrupts and stop SST right here */\n    __asm volatile (\"cpsid i\");\n\n#ifndef NDEBUG\n    for (;;) { /* keep blinking LED2 */\n        BSP_d6on();  /* turn LED2 on */\n        uint32_t volatile ctr;\n        for (ctr = 10000U; ctr > 0U; --ctr) {\n        }\n        BSP_d6off(); /* turn LED2 off */\n        for (ctr = 10000U; ctr > 0U; --ctr) {\n        }\n    }\n#endif\n    NVIC_SystemReset();\n}\n/*..........................................................................*/\nvoid assert_failed(char const * const module, int const label);/* prototype */\nvoid assert_failed(char const * const module, int const label) {\n    DBC_fault_handler(module, label);\n}\n\n/* SST task activations ====================================================*/\n/* preprocessor switch to choose between regular and reserved IRQs */\n#define REGULAR_IRQS\n\n#ifdef REGULAR_IRQS\n/* repurpose regular IRQs for SST Tasks */\n/* prototypes */\nvoid PVD_IRQHandler(void);\nvoid RTC_IRQHandler(void);\nvoid TSC_IRQHandler(void);\nvoid I2C2_IRQHandler(void);\n\nvoid PVD_IRQHandler(void)  { SST_Task_activate(AO_Blinky3);  }\nvoid RTC_IRQHandler(void)  { SST_Task_activate(AO_Button2b); }\nvoid TSC_IRQHandler(void)  { SST_Task_activate(AO_Button2a); }\nvoid I2C2_IRQHandler(void) { SST_Task_activate(AO_Blinky1);  }\n\n#else /* use reserved IRQs for SST Tasks */\n/* prototypes */\nvoid Reserved14_IRQHandler(void);\nvoid Reserved16_IRQHandler(void);\nvoid Reserved18_IRQHandler(void);\nvoid Reserved19_IRQHandler(void);\n\nvoid Reserved14_IRQHandler(void) { SST_Task_activate(AO_Blinky3);  }\nvoid Reserved16_IRQHandler(void) { SST_Task_activate(AO_Button2b); }\nvoid Reserved18_IRQHandler(void) { SST_Task_activate(AO_Button2a); }\nvoid Reserved19_IRQHandler(void) { SST_Task_activate(AO_Blinky1);  }\n#endif\n\n/* BSP functions ===========================================================*/\nvoid BSP_init(void) {\n    /* Configure the MPU to prevent NULL-pointer dereferencing\n    * see: www.state-machine.com/null-pointer-protection-with-arm-cortex-m-mpu\n    */\n    MPU->RBAR = 0x0U                          /* base address (NULL) */\n                | MPU_RBAR_VALID_Msk          /* valid region */\n                | (MPU_RBAR_REGION_Msk & 7U); /* region #7 */\n    MPU->RASR = (7U << MPU_RASR_SIZE_Pos)     /* 2^(7+1) region */\n                | (0x0U << MPU_RASR_AP_Pos)   /* no-access region */\n                | MPU_RASR_ENABLE_Msk;        /* region enable */\n\n    MPU->CTRL = MPU_CTRL_PRIVDEFENA_Msk       /* enable background region */\n                | MPU_CTRL_ENABLE_Msk;        /* enable the MPU */\n    __ISB();\n    __DSB();\n\n    /* assign IRQs to tasks. NOTE: critical for SST... */\n#ifdef REGULAR_IRQS\n    /* repurpose regular IRQs for SST Tasks */\n    SST_Task_setIRQ(AO_Blinky3,  PVD_IRQn);\n    SST_Task_setIRQ(AO_Button2b, RTC_IRQn);\n    SST_Task_setIRQ(AO_Button2a, TSC_IRQn);\n    SST_Task_setIRQ(AO_Blinky1,  I2C2_IRQn);\n#else\n    /* use reserved IRQs for SST Tasks */\n    SST_Task_setIRQ(AO_Blinky3,  14U);\n    SST_Task_setIRQ(AO_Button2b, 16U);\n    SST_Task_setIRQ(AO_Button2a, 18U);\n    SST_Task_setIRQ(AO_Blinky1,  19U);\n#endif\n\n    /* enable GPIO port PA clock */\n    RCC->IOPENR |= (1U << 0U);\n\n    /* set all used GPIOA pins as push-pull output, no pull-up, pull-down */\n    GPIOA->MODER &=\n        ~((3U << 2U*TST1_PIN) | (3U << 2U*TST2_PIN) | (3U << 2U*TST3_PIN) |\n          (3U << 2U*TST4_PIN) | (3U << 2U*TST5_PIN) | (3U << 2U*TST6_PIN));\n    GPIOA->MODER |=\n         ((1U << 2U*TST1_PIN) | (1U << 2U*TST2_PIN) | (1U << 2U*TST3_PIN) |\n          (1U << 2U*TST4_PIN) | (1U << 2U*TST5_PIN) | (1U << 2U*TST6_PIN));\n    GPIOA->OTYPER &=\n        ~((1U <<    TST1_PIN) | (1U <<    TST2_PIN) | (1U <<    TST3_PIN) |\n          (1U <<    TST4_PIN) | (1U <<    TST5_PIN) | (1U <<    TST6_PIN));\n    GPIOA->PUPDR &=\n        ~((3U << 2U*TST1_PIN) | (3U << 2U*TST2_PIN) | (3U << 2U*TST3_PIN) |\n          (3U << 2U*TST4_PIN) | (3U << 2U*TST5_PIN) | (3U << 2U*TST6_PIN));\n\n    /* enable GPIOC clock port for the Button B1 */\n    RCC->IOPENR |=  (1U << 2U);\n\n    /* configure Button B1 pin on GPIOC as input, no pull-up, pull-down */\n    GPIOC->MODER &= ~(3U << 2U*B1_PIN);\n    GPIOC->PUPDR &= ~(3U << 2U*B1_PIN);\n}\n\n/*..........................................................................*/\nvoid BSP_d1on(void)  { GPIOA->BSRR = (1U << TST1_PIN);         }\nvoid BSP_d1off(void) { GPIOA->BSRR = (1U << (TST1_PIN + 16U)); }\n/*..........................................................................*/\nvoid BSP_d2on(void)  { GPIOA->BSRR = (1U << TST2_PIN);         }\nvoid BSP_d2off(void) { GPIOA->BSRR = (1U << (TST2_PIN + 16U)); }\n/*..........................................................................*/\nvoid BSP_d3on(void)  { GPIOA->BSRR = (1U << TST3_PIN);         }\nvoid BSP_d3off(void) { GPIOA->BSRR = (1U << (TST3_PIN + 16U)); }\n/*..........................................................................*/\nvoid BSP_d4on(void)  { GPIOA->BSRR = (1U << TST4_PIN);         }\nvoid BSP_d4off(void) { GPIOA->BSRR = (1U << (TST4_PIN + 16U)); }\n/*..........................................................................*/\nvoid BSP_d5on(void)  { GPIOA->BSRR = (1U << TST5_PIN);         }\nvoid BSP_d5off(void) { GPIOA->BSRR = (1U << (TST5_PIN + 16U)); }\n/*..........................................................................*/\nvoid BSP_d6on(void)  { GPIOA->BSRR = (1U << TST6_PIN);         } /* LED2 */\nvoid BSP_d6off(void) { GPIOA->BSRR = (1U << (TST6_PIN + 16U)); }\n\n/*..........................................................................*/\nSST_Evt const *BSP_getWorkEvtBlinky1(uint8_t num) {\n    /* immutable work events for Blinky1 */\n    static BlinkyWorkEvt const workBlinky1[] = {\n        {\n            .super.sig = BLINKY_WORK_SIG,\n            .toggles = 40U,\n            .ticks = 5U,\n        },\n        {\n            .super.sig = BLINKY_WORK_SIG,\n            .toggles = 30U,\n            .ticks = 7U,\n        }\n    };\n    DBC_REQUIRE(500, num < ARRAY_NELEM(workBlinky1)); /* must be in range */\n    return &workBlinky1[num].super;\n}\n/*..........................................................................*/\nSST_Evt const *BSP_getWorkEvtBlinky3(uint8_t num) {\n    /* immutable work events for Blinky3 */\n    static BlinkyWorkEvt const workBlinky3[] = {\n        {\n            .super.sig = BLINKY_WORK_SIG,\n            .toggles = 20U,\n            .ticks = 5U,\n        },\n        {\n            .super.sig = BLINKY_WORK_SIG,\n            .toggles = 10U,\n            .ticks = 3U,\n        }\n    };\n    DBC_REQUIRE(600, num < ARRAY_NELEM(workBlinky3)); /* must be in range */\n    return &workBlinky3[num].super;\n}\n\n/* SST callbacks ===========================================================*/\nvoid SST_onStart(void) {\n    SystemCoreClockUpdate();\n\n    /* set up the SysTick timer to fire at BSP_TICKS_PER_SEC rate */\n    SysTick_Config((SystemCoreClock / BSP_TICKS_PER_SEC) + 1U);\n\n    /* set priorities of ISRs used in the system */\n    NVIC_SetPriority(SysTick_IRQn, 0U);\n    /* ... */\n}\n/*..........................................................................*/\nvoid SST_onIdle(void) {\n    BSP_d6on();  /* turn LED2 on */\n#ifdef NDEBUG\n    /* Put the CPU and peripherals to the low-power mode.\n    * you might need to customize the clock management for your application,\n    * see the datasheet for your particular Cortex-M MCU.\n    */\n    BSP_d6off(); /* turn LED2 off */\n    __WFI(); /* Wait-For-Interrupt */\n    BSP_d6on();  /* turn LED2 on */\n#endif\n    BSP_d6off(); /* turn LED2 off */\n}\n\n"
  },
  {
    "path": "sst_c/examples/blinky_button/button2a.c",
    "content": "/*============================================================================\n* Super-Simple Tasker (SST/C) Example\n*\n* Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n*\n* SPDX-License-Identifier: MIT\n*\n* Permission is hereby granted, free of charge, to any person obtaining a\n* copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included in\n* all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n============================================================================*/\n#include \"sst.h\"           /* SST framework */\n#include \"bsp.h\"           /* Board Support Package interface */\n#include \"blinky_button.h\" /* application shared interface */\n\nDBC_MODULE_NAME(\"button2a\") /* for DBC assertions in this module */\n\n/*..........................................................................*/\ntypedef struct {    /* Button2a task */\n    SST_Task super; /* inherit SST_Task */\n    /* add internal variables for this AO... */\n} Button2a;\n\nstatic void Button2a_ctor(Button2a * const me);\nstatic void Button2a_init(Button2a * const me, SST_Evt const * const ie);\nstatic void Button2a_dispatch(Button2a * const me, SST_Evt const * const e);\n\n/*..........................................................................*/\nstatic Button2a Button2a_inst; /* the Button2a instance */\nSST_Task * const AO_Button2a = &Button2a_inst.super; /* opaque AO pointer */\n\nvoid Button2a_instantiate(void) {\n    Button2a_ctor(&Button2a_inst);\n}\n\n/*..........................................................................*/\nstatic void Button2a_ctor(Button2a * const me) {\n    SST_Task_ctor(\n       &me->super,\n       (SST_Handler)&Button2a_init,\n       (SST_Handler)&Button2a_dispatch);\n}\n/*..........................................................................*/\nstatic void Button2a_init(Button2a * const me, SST_Evt const * const ie) {\n    (void)me;\n    (void)ie;\n}\n/*..........................................................................*/\nstatic void Button2a_dispatch(Button2a * const me, SST_Evt const * const e) {\n    (void)me;\n    switch (e->sig) {\n        case BUTTON_PRESSED_SIG: {\n            BSP_d4on();\n            /* Button2a --> Blinky1 */\n            SST_Task_post(AO_Blinky1, BSP_getWorkEvtBlinky1(1U));\n            BSP_d4off();\n\n            for (uint16_t i = SST_EVT_DOWNCAST(ButtonWorkEvt, e)->toggles;\n                 i > 0U; --i)\n            {\n                BSP_d4on();\n                BSP_d4off();\n            }\n            break;\n        }\n        case FORWARD_PRESSED_SIG: {\n            BSP_d4on();\n            /* immutable event can be forwarded to another Task */\n            SST_Task_post(AO_Button2b, e); /* Button2a --> Button2b */\n            BSP_d4off();\n            break;\n        }\n        case BUTTON_RELEASED_SIG: {\n            BSP_d4on();\n            /* Button2a --> Blinky1 */\n            SST_Task_post(AO_Blinky1, BSP_getWorkEvtBlinky1(0U));\n            BSP_d4off();\n\n            for (uint16_t i = SST_EVT_DOWNCAST(ButtonWorkEvt, e)->toggles;\n                 i > 0U; --i)\n            {\n                BSP_d4on();\n                BSP_d4off();\n            }\n            break;\n        }\n        case FORWARD_RELEASED_SIG: {\n            BSP_d4on();\n            /* immutable event can be forwarded to another Task */\n            SST_Task_post(AO_Button2b, e); /* Button2a --> Button2b */\n            BSP_d4off();\n            break;\n        }\n        default: {\n            DBC_ERROR(500); /* unexpected event */\n            break;\n        }\n    }\n}\n"
  },
  {
    "path": "sst_c/examples/blinky_button/button2b.c",
    "content": "/*============================================================================\n* Super-Simple Tasker (SST/C) Example\n*\n* Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n*\n* SPDX-License-Identifier: MIT\n*\n* Permission is hereby granted, free of charge, to any person obtaining a\n* copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included in\n* all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n============================================================================*/\n#include \"sst.h\"           /* SST framework */\n#include \"bsp.h\"           /* Board Support Package interface */\n#include \"blinky_button.h\" /* application shared interface */\n\nDBC_MODULE_NAME(\"button2b\") /* for DBC assertions in this module */\n\n/*..........................................................................*/\ntypedef struct {    /* Button2b task */\n    SST_Task super; /* inherit SST_Task */\n    /* add internal variables for this AO... */\n} Button2b;\n\nstatic void Button2b_ctor(Button2b * const me);\nstatic void Button2b_init(Button2b * const me, SST_Evt const * const e);\nstatic void Button2b_dispatch(Button2b * const me, SST_Evt const * const e);\n\n/*..........................................................................*/\nstatic Button2b Button2b_inst; /* the Button2b instance */\nSST_Task * const AO_Button2b = &Button2b_inst.super; /* opaque AO pointer */\n\nvoid Button2b_instantiate(void) {\n    Button2b_ctor(&Button2b_inst);\n}\n\n/*..........................................................................*/\nstatic void Button2b_ctor(Button2b * const me) {\n    SST_Task_ctor(\n       &me->super,\n       (SST_Handler)&Button2b_init,\n       (SST_Handler)&Button2b_dispatch);\n}\n/*..........................................................................*/\nstatic void Button2b_init(Button2b * const me, SST_Evt const * const ie) {\n    (void)me;\n    (void)ie;\n}\n/*..........................................................................*/\nstatic void Button2b_dispatch(Button2b * const me, SST_Evt const * const e) {\n    switch (e->sig) {\n        case FORWARD_PRESSED_SIG: {\n            BSP_d3on();\n            /* Button2b --> Blinky3 */\n            SST_Task_post(AO_Blinky3, BSP_getWorkEvtBlinky3(1U));\n            BSP_d3off();\n\n            for (uint16_t i = SST_EVT_DOWNCAST(ButtonWorkEvt, e)->toggles;\n                 i > 0U; --i)\n            {\n                BSP_d3on();\n                BSP_d3off();\n            }\n            break;\n        }\n        case FORWARD_RELEASED_SIG: {\n            BSP_d3on();\n            /* Button2b --> Blinky3 */\n            SST_Task_post(AO_Blinky3, BSP_getWorkEvtBlinky3(0U));\n            BSP_d3off();\n\n            for (uint16_t i = SST_EVT_DOWNCAST(ButtonWorkEvt, e)->toggles;\n                 i > 0U; --i)\n            {\n                BSP_d3on();\n                BSP_d3off();\n            }\n            break;\n        }\n        default: {\n            DBC_ERROR(500); /* unexpected event */\n            break;\n        }\n    }\n}\n"
  },
  {
    "path": "sst_c/examples/blinky_button/gnu/ek-tm4c123gxl.mak",
    "content": "##############################################################################\n# Makefile for Super-Simple Tasker (SST/C) on TM4C123GXL, GNU-ARM\n# Last Updated for Version: 2.0.0\n# Date of the Last Update:  2023-01-25\n#\n#                    Q u a n t u m  L e a P s\n#                    ------------------------\n#                    Modern Embedded Software\n#\n# Copyright (C) 2005 Quantum Leaps, LLC. All rights reserved.\n#\n# SPDX-License-Identifier: MIT\n#\n# Permission is hereby granted, free of charge, to any person obtaining a copy\n# of this software and associated documentation files (the \"Software\"), to\n# deal in the Software without restriction, including without limitation the\n# rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n# sell copies of the Software, and to permit persons to whom the Software is\n# furnished to do so, subject to the following conditions:\n#\n# The above copyright notice and this permission notice shall be included in\n# all copies or substantial portions of the Software.\n#\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS\n# IN THE SOFTWARE.\n##############################################################################\n# examples of invoking this Makefile:\n# make -f ek-tm4c123gxl.mak\n# make -f ek-tm4c123gxl.mak clean\n#\n# NOTE:\n# To use this Makefile on Windows, you will need the GNU make utility, which\n# is included in the QTools collection for Windows, see:\n#    https://github.com/QuantumLeaps/qtools\n#\n\n#-----------------------------------------------------------------------------\n# project and target names\n#\nPROJECT := blinky_button\nTARGET  := ek-tm4c123gxl\n\n#-----------------------------------------------------------------------------\n# project directories\n#\nSST_DIR      := ../../..\nSST_PORT_DIR := $(SST_DIR)/ports/arm-cm\nCMSIS_DIR    := ../../../../3rd_party/CMSIS\nTARGET_DIR   := ../../../../3rd_party/$(TARGET)\n\n# list of all source directories used by this project\nVPATH = .. \\\n\t$(SST_DIR)/src \\\n\t$(SST_PORT_DIR) \\\n\t$(TARGET_DIR) \\\n\t$(TARGET_DIR)/gnu \\\n\n# list of all include directories needed by this project\nINCLUDES  = -I. \\\n\t-I$(SST_DIR)/../include \\\n\t-I$(SST_PORT_DIR) \\\n\t-I$(CMSIS_DIR)/Include \\\n\t-I$(TARGET_DIR)\n\n#-----------------------------------------------------------------------------\n# project files\n#\n\n# assembler source files\nASM_SRCS :=\n\n# C source files\nC_SRCS := \\\n\tsst.c \\\n\tsst_port.c \\\n\tmain.c \\\n\tblinky1.c \\\n\tblinky3.c \\\n\tbutton2a.c \\\n\tbutton2b.c \\\n\tbsp_ek-tm4c123gxl.c \\\n\tsystem_TM4C123GH6PM.c \\\n\tstartup_TM4C123GH6PM.c\n\n# C++ source files\nCPP_SRCS :=\n\nLD_SCRIPT  := $(TARGET_DIR)/gnu/$(TARGET).ld\n\nOUTPUT    := $(PROJECT)\n\nLIB_DIRS  :=\nLIBS      :=\n\n# defines\nDEFINES   := -DTARGET_IS_TM4C123_RB1\n\n# ARM CPU, ARCH, FPU, and Float-ABI types...\n# ARM_CPU:   [cortex-m0 | cortex-m0plus | cortex-m1 | cortex-m3 | cortex-m4]\n# ARM_FPU:   [ | vfp]\n# FLOAT_ABI: [ | soft | softfp | hard]\n#\nARM_CPU   := -mcpu=cortex-m4\nARM_FPU   := -mfpu=vfp\nFLOAT_ABI := -mfloat-abi=softfp\n\n#-----------------------------------------------------------------------------\n# GNU-ARM toolset (NOTE: You need to adjust to your machine)\n# see https://developer.arm.com/open-source/gnu-toolchain/gnu-rm/downloads\n#\nifeq ($(GNU_ARM),)\nGNU_ARM := $(QTOOLS)/gnu_arm-none-eabi\nendif\n\n# make sure that the GNU-ARM toolset exists...\nifeq (\"$(wildcard $(GNU_ARM))\",\"\")\n$(error GNU_ARM toolset not found. Please adjust the Makefile)\nendif\n\nCC    := $(GNU_ARM)/bin/arm-none-eabi-gcc\nCPP   := $(GNU_ARM)/bin/arm-none-eabi-g++\nAS    := $(GNU_ARM)/bin/arm-none-eabi-as\nLINK  := $(GNU_ARM)/bin/arm-none-eabi-gcc\nBIN   := $(GNU_ARM)/bin/arm-none-eabi-objcopy\n\n##############################################################################\n# Typically you should not need to change anything below this line\n\n# basic utilities (included in QTools for Windows), see:\n#     https://www.state-machine.com/qtools\n\nMKDIR := mkdir\nRM    := rm\n\n#-----------------------------------------------------------------------------\n# build options\n#\n\n# combine all the soruces...\nC_SRCS += $(QP_SRCS)\nASM_SRCS += $(QP_ASMS)\n\nBIN_DIR := build_$(TARGET)\n\nASFLAGS = -g $(ARM_CPU) $(ARM_FPU) $(ASM_CPU) $(ASM_FPU)\n\nCFLAGS = -c -g $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -std=c99 -mthumb -Wall \\\n\t-ffunction-sections -fdata-sections \\\n\t-O $(INCLUDES) $(DEFINES)\n\nCPPFLAGS = -c -g $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -std=c++11 -mthumb -Wall \\\n\t-ffunction-sections -fdata-sections -fno-rtti -fno-exceptions \\\n\t-O $(INCLUDES) $(DEFINES)\n\nLINKFLAGS = -T$(LD_SCRIPT) $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -mthumb \\\n\t-specs=nosys.specs -specs=nano.specs \\\n\t-Wl,-Map,$(BIN_DIR)/$(OUTPUT).map,--cref,--gc-sections $(LIB_DIRS)\n\nASM_OBJS     := $(patsubst %.s,%.o,  $(notdir $(ASM_SRCS)))\nC_OBJS       := $(patsubst %.c,%.o,  $(notdir $(C_SRCS)))\nCPP_OBJS     := $(patsubst %.cpp,%.o,$(notdir $(CPP_SRCS)))\n\nTARGET_BIN   := $(BIN_DIR)/$(OUTPUT).bin\nTARGET_ELF   := $(BIN_DIR)/$(OUTPUT).elf\nASM_OBJS_EXT := $(addprefix $(BIN_DIR)/, $(ASM_OBJS))\nC_OBJS_EXT   := $(addprefix $(BIN_DIR)/, $(C_OBJS))\nC_DEPS_EXT   := $(patsubst %.o, %.d, $(C_OBJS_EXT))\nCPP_OBJS_EXT := $(addprefix $(BIN_DIR)/, $(CPP_OBJS))\nCPP_DEPS_EXT := $(patsubst %.o, %.d, $(CPP_OBJS_EXT))\n\n# create $(BIN_DIR) if it does not exist\nifeq (\"$(wildcard $(BIN_DIR))\",\"\")\n$(shell $(MKDIR) $(BIN_DIR))\nendif\n\n#-----------------------------------------------------------------------------\n# rules\n#\n\n.PHONY : run norun flash\n\nifeq ($(MAKECMDGOALS),norun)\nall : $(TARGET_BIN)\nnorun : all\nelse\nall : $(TARGET_BIN) run\nendif\n\n$(TARGET_BIN): $(TARGET_ELF)\n\t$(BIN) -O binary $< $@\n\n$(TARGET_ELF) : $(ASM_OBJS_EXT) $(C_OBJS_EXT) $(CPP_OBJS_EXT)\n\t$(LINK) $(LINKFLAGS) -o $@ $^ $(LIBS)\n\n$(BIN_DIR)/%.d : %.c\n\t$(CC) -MM -MT $(@:.d=.o) $(CFLAGS) $< > $@\n\n$(BIN_DIR)/%.d : %.cpp\n\t$(CPP) -MM -MT $(@:.d=.o) $(CPPFLAGS) $< > $@\n\n$(BIN_DIR)/%.o : %.s\n\t$(AS) $(ASFLAGS) $< -o $@\n\n$(BIN_DIR)/%.o : %.c\n\t$(CC) $(CFLAGS) $< -o $@\n\n$(BIN_DIR)/%.o : %.cpp\n\t$(CPP) $(CPPFLAGS) $< -o $@\n\n.PHONY : clean show\n\n# include dependency files only if our goal depends on their existence\nifneq ($(MAKECMDGOALS),clean)\n  ifneq ($(MAKECMDGOALS),show)\n-include $(C_DEPS_EXT) $(CPP_DEPS_EXT)\n  endif\nendif\n\n\nclean :\n\t-$(RM) $(BIN_DIR)/*.o \\\n\t$(BIN_DIR)/*.d \\\n\t$(BIN_DIR)/*.bin \\\n\t$(BIN_DIR)/*.elf \\\n\t$(BIN_DIR)/*.map\n\t\nshow:\n\t@echo PROJECT = $(PROJECT)\n\t@echo CONF = $(CONF)\n\t@echo DEFINES = $(DEFINES)\n\t@echo ASM_FPU = $(ASM_FPU)\n\t@echo ASM_SRCS = $(ASM_SRCS)\n\t@echo C_SRCS = $(C_SRCS)\n\t@echo CPP_SRCS = $(CPP_SRCS)\n\t@echo ASM_OBJS_EXT = $(ASM_OBJS_EXT)\n\t@echo C_OBJS_EXT = $(C_OBJS_EXT)\n\t@echo C_DEPS_EXT = $(C_DEPS_EXT)\n\t@echo CPP_DEPS_EXT = $(CPP_DEPS_EXT)\n\t@echo TARGET_ELF = $(TARGET_ELF)\n"
  },
  {
    "path": "sst_c/examples/blinky_button/gnu/flash_ek-tm4c123gxl.bat",
    "content": "::============================================================================\n:: Batch file to program the flash of EK-TM4C123GXL\n::\n:: NOTE: requires the LMFlash programmer (included in QTools for Windows)\n::\n@echo off\nsetlocal\n\n@echo Load a given binary file to the flash of EK-TM4C123GXL\n@echo usage:   flash binary-file\n@echo example: flash dbg\\blinky-qk.bin\n\n::----------------------------------------------------------------------------\n:: NOTE: The following symbol LMFLASH assumes that LMFlash.exe can\n:: be found on the PATH. You might need to adjust this symbol to the\n:: location of the LMFlash utility on your machine\n::\nset LMFLASH=LMFlash.exe\n\nif [\"%~1\"]==[\"\"] (\n    @echo The binary file missing\n    @goto end\n)\nif not exist %~s1 (\n    @echo The binary file '%1' does not exist\n    @goto end\n)\n\n%LMFLASH% -q ek-tm4c123gxl -e -v -r %1\n\n:end\n\nendlocal"
  },
  {
    "path": "sst_c/examples/blinky_button/gnu/nucleo-c031c6.mak",
    "content": "##############################################################################\n# Makefile for Super-Simple Tasker (SST/C) on NUCLEO-C031C6, GNU-ARM\n# Last Updated for Version: 2.0.0\n# Date of the Last Update:  2023-02-01\n#\n#                    Q u a n t u m  L e a P s\n#                    ------------------------\n#                    Modern Embedded Software\n#\n# Copyright (C) 2005 Quantum Leaps, LLC. All rights reserved.\n#\n# SPDX-License-Identifier: MIT\n#\n# Permission is hereby granted, free of charge, to any person obtaining a copy\n# of this software and associated documentation files (the \"Software\"), to\n# deal in the Software without restriction, including without limitation the\n# rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n# sell copies of the Software, and to permit persons to whom the Software is\n# furnished to do so, subject to the following conditions:\n#\n# The above copyright notice and this permission notice shall be included in\n# all copies or substantial portions of the Software.\n#\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS\n# IN THE SOFTWARE.\n##############################################################################\n# examples of invoking this Makefile:\n# make -f nucleo-c031c6.mak\n# make -f nucleo-c031c6.mak clean\n#\n# NOTE:\n# To use this Makefile on Windows, you will need the GNU make utility, which\n# is included in the QTools collection for Windows, see:\n#    https://github.com/QuantumLeaps/qtools\n#\n\n#-----------------------------------------------------------------------------\n# project and target names\n#\nPROJECT := blinky_button\nTARGET  := nucleo-c031c6\n\n#-----------------------------------------------------------------------------\n# project directories\n#\nSST_DIR      := ../../..\nSST_PORT_DIR := $(SST_DIR)/ports/arm-cm\nCMSIS_DIR    := ../../../../3rd_party/CMSIS\nTARGET_DIR   := ../../../../3rd_party/$(TARGET)\n\n# list of all source directories used by this project\nVPATH = .. \\\n\t$(SST_DIR)/src \\\n\t$(SST_PORT_DIR) \\\n\t$(TARGET_DIR) \\\n\t$(TARGET_DIR)/gnu \\\n\n# list of all include directories needed by this project\nINCLUDES  = -I. \\\n\t-I$(SST_DIR)/../include \\\n\t-I$(SST_PORT_DIR) \\\n\t-I$(CMSIS_DIR)/Include \\\n\t-I$(TARGET_DIR)\n\n#-----------------------------------------------------------------------------\n# project files\n#\n\n# assembler source files\nASM_SRCS :=\n\n# C source files\nC_SRCS := \\\n\tsst.c \\\n\tsst_port.c \\\n\tmain.c \\\n\tblinky1.c \\\n\tblinky3.c \\\n\tbutton2a.c \\\n\tbutton2b.c \\\n\tbsp_nucleo-c031c6.c \\\n\tsystem_stm32c0xx.c \\\n\tstartup_stm32c031xx.c\n\n# C++ source files\nCPP_SRCS :=\n\nLD_SCRIPT  := $(TARGET_DIR)/gnu/$(TARGET).ld\n\nOUTPUT    := $(PROJECT)\n\nLIB_DIRS  :=\nLIBS      :=\n\n# defines\nDEFINES   := -DSTM32C031xx\n\n# ARM CPU, ARCH, FPU, and Float-ABI types...\n# ARM_CPU:   [cortex-m0 | cortex-m0plus | cortex-m1 | cortex-m3 | cortex-m4]\n# ARM_FPU:   [ | vfp]\n# FLOAT_ABI: [ | soft | softfp | hard]\n#\nARM_CPU   := -mcpu=cortex-m0plus\nARM_FPU   :=\nFLOAT_ABI :=\n\n#-----------------------------------------------------------------------------\n# GNU-ARM toolset (NOTE: You need to adjust to your machine)\n# see https://developer.arm.com/open-source/gnu-toolchain/gnu-rm/downloads\n#\nifeq ($(GNU_ARM),)\nGNU_ARM := $(QTOOLS)/gnu_arm-none-eabi\nendif\n\n# make sure that the GNU-ARM toolset exists...\nifeq (\"$(wildcard $(GNU_ARM))\",\"\")\n$(error GNU_ARM toolset not found. Please adjust the Makefile)\nendif\n\nCC    := $(GNU_ARM)/bin/arm-none-eabi-gcc\nCPP   := $(GNU_ARM)/bin/arm-none-eabi-g++\nAS    := $(GNU_ARM)/bin/arm-none-eabi-as\nLINK  := $(GNU_ARM)/bin/arm-none-eabi-gcc\nBIN   := $(GNU_ARM)/bin/arm-none-eabi-objcopy\n\n##############################################################################\n# Typically you should not need to change anything below this line\n\n# basic utilities (included in QTools for Windows), see:\n#     https://www.state-machine.com/qtools\n\nMKDIR := mkdir\nRM    := rm\n\n#-----------------------------------------------------------------------------\n# build options\n#\n\n# combine all the soruces...\nC_SRCS += $(QP_SRCS)\nASM_SRCS += $(QP_ASMS)\n\nBIN_DIR := build_$(TARGET)\n\nASFLAGS = -g $(ARM_CPU) $(ARM_FPU) $(ASM_CPU) $(ASM_FPU)\n\nCFLAGS = -c -g $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -std=c99 -mthumb -Wall \\\n\t-ffunction-sections -fdata-sections \\\n\t-O $(INCLUDES) $(DEFINES)\n\nCPPFLAGS = -c -g $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -std=c++11 -mthumb -Wall \\\n\t-ffunction-sections -fdata-sections -fno-rtti -fno-exceptions \\\n\t-O $(INCLUDES) $(DEFINES)\n\nLINKFLAGS = -T$(LD_SCRIPT) $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -mthumb \\\n\t-specs=nosys.specs -specs=nano.specs \\\n\t-Wl,-Map,$(BIN_DIR)/$(OUTPUT).map,--cref,--gc-sections $(LIB_DIRS)\n\nASM_OBJS     := $(patsubst %.s,%.o,  $(notdir $(ASM_SRCS)))\nC_OBJS       := $(patsubst %.c,%.o,  $(notdir $(C_SRCS)))\nCPP_OBJS     := $(patsubst %.cpp,%.o,$(notdir $(CPP_SRCS)))\n\nTARGET_BIN   := $(BIN_DIR)/$(OUTPUT).bin\nTARGET_ELF   := $(BIN_DIR)/$(OUTPUT).elf\nASM_OBJS_EXT := $(addprefix $(BIN_DIR)/, $(ASM_OBJS))\nC_OBJS_EXT   := $(addprefix $(BIN_DIR)/, $(C_OBJS))\nC_DEPS_EXT   := $(patsubst %.o, %.d, $(C_OBJS_EXT))\nCPP_OBJS_EXT := $(addprefix $(BIN_DIR)/, $(CPP_OBJS))\nCPP_DEPS_EXT := $(patsubst %.o, %.d, $(CPP_OBJS_EXT))\n\n# create $(BIN_DIR) if it does not exist\nifeq (\"$(wildcard $(BIN_DIR))\",\"\")\n$(shell $(MKDIR) $(BIN_DIR))\nendif\n\n#-----------------------------------------------------------------------------\n# rules\n#\n\n.PHONY : run norun flash\n\nifeq ($(MAKECMDGOALS),norun)\nall : $(TARGET_BIN)\nnorun : all\nelse\nall : $(TARGET_BIN) run\nendif\n\n$(TARGET_BIN): $(TARGET_ELF)\n\t$(BIN) -O binary $< $@\n\n$(TARGET_ELF) : $(ASM_OBJS_EXT) $(C_OBJS_EXT) $(CPP_OBJS_EXT)\n\t$(LINK) $(LINKFLAGS) -o $@ $^ $(LIBS)\n\n$(BIN_DIR)/%.d : %.c\n\t$(CC) -MM -MT $(@:.d=.o) $(CFLAGS) $< > $@\n\n$(BIN_DIR)/%.d : %.cpp\n\t$(CPP) -MM -MT $(@:.d=.o) $(CPPFLAGS) $< > $@\n\n$(BIN_DIR)/%.o : %.s\n\t$(AS) $(ASFLAGS) $< -o $@\n\n$(BIN_DIR)/%.o : %.c\n\t$(CC) $(CFLAGS) $< -o $@\n\n$(BIN_DIR)/%.o : %.cpp\n\t$(CPP) $(CPPFLAGS) $< -o $@\n\n.PHONY : clean show\n\n# include dependency files only if our goal depends on their existence\nifneq ($(MAKECMDGOALS),clean)\n  ifneq ($(MAKECMDGOALS),show)\n-include $(C_DEPS_EXT) $(CPP_DEPS_EXT)\n  endif\nendif\n\n\nclean:\n\t-$(RM) $(BIN_DIR)/*.o \\\n\t$(BIN_DIR)/*.d \\\n\t$(BIN_DIR)/*.bin \\\n\t$(BIN_DIR)/*.elf \\\n\t$(BIN_DIR)/*.map\n\t\nshow:\n\t@echo PROJECT = $(PROJECT)\n\t@echo CONF = $(CONF)\n\t@echo DEFINES = $(DEFINES)\n\t@echo ASM_FPU = $(ASM_FPU)\n\t@echo ASM_SRCS = $(ASM_SRCS)\n\t@echo C_SRCS = $(C_SRCS)\n\t@echo CPP_SRCS = $(CPP_SRCS)\n\t@echo ASM_OBJS_EXT = $(ASM_OBJS_EXT)\n\t@echo C_OBJS_EXT = $(C_OBJS_EXT)\n\t@echo C_DEPS_EXT = $(C_DEPS_EXT)\n\t@echo CPP_DEPS_EXT = $(CPP_DEPS_EXT)\n\t@echo TARGET_ELF = $(TARGET_ELF)\n"
  },
  {
    "path": "sst_c/examples/blinky_button/gnu/nucleo-h743zi.mak",
    "content": "##############################################################################\n# Makefile for Super-Simple Tasker (SST/C) on NUCLEO-H743ZI, GNU-ARM\n# Last Updated for Version: 2.0.0\n# Date of the Last Update:  2023-01-22\n#\n#                    Q u a n t u m  L e a P s\n#                    ------------------------\n#                    Modern Embedded Software\n#\n# Copyright (C) 2005 Quantum Leaps, LLC. All rights reserved.\n#\n# SPDX-License-Identifier: MIT\n#\n# Permission is hereby granted, free of charge, to any person obtaining a copy\n# of this software and associated documentation files (the \"Software\"), to\n# deal in the Software without restriction, including without limitation the\n# rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n# sell copies of the Software, and to permit persons to whom the Software is\n# furnished to do so, subject to the following conditions:\n#\n# The above copyright notice and this permission notice shall be included in\n# all copies or substantial portions of the Software.\n#\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS\n# IN THE SOFTWARE.\n##############################################################################\n# examples of invoking this Makefile:\n# make -f nucleo-h743zi.mak\n# make -f nucleo-h743zi.mak clean\n#\n# NOTE:\n# To use this Makefile on Windows, you will need the GNU make utility, which\n# is included in the QTools collection for Windows, see:\n#    https://github.com/QuantumLeaps/qtools\n#\n\n#-----------------------------------------------------------------------------\n# project and target names\n#\nPROJECT := blinky_button\nTARGET  := nucleo-h743zi\n\n#-----------------------------------------------------------------------------\n# project directories\n#\nSST_DIR      := ../../..\nSST_PORT_DIR := $(SST_DIR)/ports/arm-cm\nCMSIS_DIR    := ../../../../3rd_party/CMSIS\nTARGET_DIR   := ../../../../3rd_party/$(TARGET)\n\n# list of all source directories used by this project\nVPATH = .. \\\n\t$(SST_DIR)/src \\\n\t$(SST_PORT_DIR) \\\n\t$(TARGET_DIR) \\\n\t$(TARGET_DIR)/gnu \\\n\n# list of all include directories needed by this project\nINCLUDES  = -I. \\\n\t-I$(SST_DIR)/../include \\\n\t-I$(SST_PORT_DIR) \\\n\t-I$(CMSIS_DIR)/Include \\\n\t-I$(TARGET_DIR)\n\n#-----------------------------------------------------------------------------\n# project files\n#\n\n# assembler source files\nASM_SRCS :=\n\n# C source files\nC_SRCS := \\\n\tsst.c \\\n\tsst_port.c \\\n\tmain.c \\\n\tblinky1.c \\\n\tblinky3.c \\\n\tbutton2a.c \\\n\tbutton2b.c \\\n\tbsp_nucleo-h743zi.c \\\n\tstartup_stm32h743xx.c \\\n\tsystem_stm32h7xx.c\n\n# C++ source files\nCPP_SRCS :=\n\nLD_SCRIPT  := $(TARGET_DIR)/gnu/$(TARGET).ld\n\nOUTPUT    := $(PROJECT)\n\nLIB_DIRS  :=\nLIBS      :=\n\n# defines\nDEFINES   := -DSTM32H743xx\n\n# ARM CPU, ARCH, FPU, and Float-ABI types...\n# ARM_CPU:   [cortex-m0 | cortex-m0plus | cortex-m1 | cortex-m3 | cortex-m4]\n# ARM_FPU:   [ | vfp]\n# FLOAT_ABI: [ | soft | softfp | hard]\n#\nARM_CPU   := -mcpu=cortex-m7\nARM_FPU   := -mfpu=fpv5-d16\nFLOAT_ABI := -mfloat-abi=softfp\n\n#-----------------------------------------------------------------------------\n# GNU-ARM toolset (NOTE: You need to adjust to your machine)\n# see https://developer.arm.com/open-source/gnu-toolchain/gnu-rm/downloads\n#\nifeq ($(GNU_ARM),)\nGNU_ARM := $(QTOOLS)/gnu_arm-none-eabi\nendif\n\n# make sure that the GNU-ARM toolset exists...\nifeq (\"$(wildcard $(GNU_ARM))\",\"\")\n$(error GNU_ARM toolset not found. Please adjust the Makefile)\nendif\n\nCC    := $(GNU_ARM)/bin/arm-none-eabi-gcc\nCPP   := $(GNU_ARM)/bin/arm-none-eabi-g++\nAS    := $(GNU_ARM)/bin/arm-none-eabi-as\nLINK  := $(GNU_ARM)/bin/arm-none-eabi-gcc\nBIN   := $(GNU_ARM)/bin/arm-none-eabi-objcopy\n\n##############################################################################\n# Typically you should not need to change anything below this line\n\n# basic utilities (included in QTools for Windows), see:\n#     https://www.state-machine.com/qtools\n\nMKDIR := mkdir\nRM    := rm\n\n#-----------------------------------------------------------------------------\n# build options\n#\n\n# combine all the soruces...\nC_SRCS += $(QP_SRCS)\nASM_SRCS += $(QP_ASMS)\n\nBIN_DIR := build_$(TARGET)\n\nASFLAGS = -g $(ARM_CPU) $(ARM_FPU) $(ASM_CPU) $(ASM_FPU)\n\nCFLAGS = -c -g $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -std=c99 -mthumb -Wall \\\n\t-ffunction-sections -fdata-sections \\\n\t-O $(INCLUDES) $(DEFINES)\n\nCPPFLAGS = -c -g $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -std=c++11 -mthumb -Wall \\\n\t-ffunction-sections -fdata-sections -fno-rtti -fno-exceptions \\\n\t-O $(INCLUDES) $(DEFINES)\n\nLINKFLAGS = -T$(LD_SCRIPT) $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -mthumb \\\n\t-specs=nosys.specs -specs=nano.specs \\\n\t-Wl,-Map,$(BIN_DIR)/$(OUTPUT).map,--cref,--gc-sections $(LIB_DIRS)\n\nASM_OBJS     := $(patsubst %.s,%.o,  $(notdir $(ASM_SRCS)))\nC_OBJS       := $(patsubst %.c,%.o,  $(notdir $(C_SRCS)))\nCPP_OBJS     := $(patsubst %.cpp,%.o,$(notdir $(CPP_SRCS)))\n\nTARGET_BIN   := $(BIN_DIR)/$(OUTPUT).bin\nTARGET_ELF   := $(BIN_DIR)/$(OUTPUT).elf\nASM_OBJS_EXT := $(addprefix $(BIN_DIR)/, $(ASM_OBJS))\nC_OBJS_EXT   := $(addprefix $(BIN_DIR)/, $(C_OBJS))\nC_DEPS_EXT   := $(patsubst %.o, %.d, $(C_OBJS_EXT))\nCPP_OBJS_EXT := $(addprefix $(BIN_DIR)/, $(CPP_OBJS))\nCPP_DEPS_EXT := $(patsubst %.o, %.d, $(CPP_OBJS_EXT))\n\n# create $(BIN_DIR) if it does not exist\nifeq (\"$(wildcard $(BIN_DIR))\",\"\")\n$(shell $(MKDIR) $(BIN_DIR))\nendif\n\n#-----------------------------------------------------------------------------\n# rules\n#\n\n.PHONY : run norun flash\n\nifeq ($(MAKECMDGOALS),norun)\nall : $(TARGET_BIN)\nnorun : all\nelse\nall : $(TARGET_BIN) run\nendif\n\n$(TARGET_BIN): $(TARGET_ELF)\n\t$(BIN) -O binary $< $@\n\n$(TARGET_ELF) : $(ASM_OBJS_EXT) $(C_OBJS_EXT) $(CPP_OBJS_EXT)\n\t$(LINK) $(LINKFLAGS) -o $@ $^ $(LIBS)\n\n$(BIN_DIR)/%.d : %.c\n\t$(CC) -MM -MT $(@:.d=.o) $(CFLAGS) $< > $@\n\n$(BIN_DIR)/%.d : %.cpp\n\t$(CPP) -MM -MT $(@:.d=.o) $(CPPFLAGS) $< > $@\n\n$(BIN_DIR)/%.o : %.s\n\t$(AS) $(ASFLAGS) $< -o $@\n\n$(BIN_DIR)/%.o : %.c\n\t$(CC) $(CFLAGS) $< -o $@\n\n$(BIN_DIR)/%.o : %.cpp\n\t$(CPP) $(CPPFLAGS) $< -o $@\n\n.PHONY : clean show\n\n# include dependency files only if our goal depends on their existence\nifneq ($(MAKECMDGOALS),clean)\n  ifneq ($(MAKECMDGOALS),show)\n-include $(C_DEPS_EXT) $(CPP_DEPS_EXT)\n  endif\nendif\n\n\nclean :\n\t-$(RM) $(BIN_DIR)/*.o \\\n\t$(BIN_DIR)/*.d \\\n\t$(BIN_DIR)/*.bin \\\n\t$(BIN_DIR)/*.elf \\\n\t$(BIN_DIR)/*.map\n\t\nshow:\n\t@echo PROJECT = $(PROJECT)\n\t@echo CONF = $(CONF)\n\t@echo DEFINES = $(DEFINES)\n\t@echo ASM_FPU = $(ASM_FPU)\n\t@echo ASM_SRCS = $(ASM_SRCS)\n\t@echo C_SRCS = $(C_SRCS)\n\t@echo CPP_SRCS = $(CPP_SRCS)\n\t@echo ASM_OBJS_EXT = $(ASM_OBJS_EXT)\n\t@echo C_OBJS_EXT = $(C_OBJS_EXT)\n\t@echo C_DEPS_EXT = $(C_DEPS_EXT)\n\t@echo CPP_DEPS_EXT = $(CPP_DEPS_EXT)\n\t@echo TARGET_ELF = $(TARGET_ELF)\n"
  },
  {
    "path": "sst_c/examples/blinky_button/gnu/nucleo-l053r8.mak",
    "content": "##############################################################################\n# Makefile for Super-Simple Tasker (SST/C) on NUCLEO-L053R8, GNU-ARM\n# Last Updated for Version: 2.0.0\n# Date of the Last Update:  2023-01-22\n#\n#                    Q u a n t u m  L e a P s\n#                    ------------------------\n#                    Modern Embedded Software\n#\n# Copyright (C) 2005 Quantum Leaps, LLC. All rights reserved.\n#\n# SPDX-License-Identifier: MIT\n#\n# Permission is hereby granted, free of charge, to any person obtaining a copy\n# of this software and associated documentation files (the \"Software\"), to\n# deal in the Software without restriction, including without limitation the\n# rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n# sell copies of the Software, and to permit persons to whom the Software is\n# furnished to do so, subject to the following conditions:\n#\n# The above copyright notice and this permission notice shall be included in\n# all copies or substantial portions of the Software.\n#\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS\n# IN THE SOFTWARE.\n##############################################################################\n# examples of invoking this Makefile:\n# make -f nucleo-l053r8.mak\n# make -f nucleo-l053r8.mak clean\n#\n# NOTE:\n# To use this Makefile on Windows, you will need the GNU make utility, which\n# is included in the QTools collection for Windows, see:\n#    https://github.com/QuantumLeaps/qtools\n#\n\n#-----------------------------------------------------------------------------\n# project and target names\n#\nPROJECT := blinky_button\nTARGET  := nucleo-l053r8\n\n#-----------------------------------------------------------------------------\n# project directories\n#\nSST_DIR      := ../../..\nSST_PORT_DIR := $(SST_DIR)/ports/arm-cm\nCMSIS_DIR    := ../../../../3rd_party/CMSIS\nTARGET_DIR   := ../../../../3rd_party/$(TARGET)\n\n# list of all source directories used by this project\nVPATH = .. \\\n\t$(SST_DIR)/src \\\n\t$(SST_PORT_DIR) \\\n\t$(TARGET_DIR) \\\n\t$(TARGET_DIR)/gnu \\\n\n# list of all include directories needed by this project\nINCLUDES  = -I. \\\n\t-I$(SST_DIR)/../include \\\n\t-I$(SST_PORT_DIR) \\\n\t-I$(CMSIS_DIR)/Include \\\n\t-I$(TARGET_DIR)\n\n#-----------------------------------------------------------------------------\n# project files\n#\n\n# assembler source files\nASM_SRCS :=\n\n# C source files\nC_SRCS := \\\n\tsst.c \\\n\tsst_port.c \\\n\tmain.c \\\n\tblinky1.c \\\n\tblinky3.c \\\n\tbutton2a.c \\\n\tbutton2b.c \\\n\tbsp_nucleo-l053r8.c \\\n\tsystem_stm32l0xx.c \\\n\tstartup_stm32l053xx.c\n\n# C++ source files\nCPP_SRCS :=\n\nLD_SCRIPT  := $(TARGET_DIR)/gnu/$(TARGET).ld\n\nOUTPUT    := $(PROJECT)\n\nLIB_DIRS  :=\nLIBS      :=\n\n# defines\nDEFINES   :=\n\n# ARM CPU, ARCH, FPU, and Float-ABI types...\n# ARM_CPU:   [cortex-m0 | cortex-m0plus | cortex-m1 | cortex-m3 | cortex-m4]\n# ARM_FPU:   [ | vfp]\n# FLOAT_ABI: [ | soft | softfp | hard]\n#\nARM_CPU   := -mcpu=cortex-m0plus\nARM_FPU   :=\nFLOAT_ABI :=\n\n#-----------------------------------------------------------------------------\n# GNU-ARM toolset (NOTE: You need to adjust to your machine)\n# see https://developer.arm.com/open-source/gnu-toolchain/gnu-rm/downloads\n#\nifeq ($(GNU_ARM),)\nGNU_ARM := $(QTOOLS)/gnu_arm-none-eabi\nendif\n\n# make sure that the GNU-ARM toolset exists...\nifeq (\"$(wildcard $(GNU_ARM))\",\"\")\n$(error GNU_ARM toolset not found. Please adjust the Makefile)\nendif\n\nCC    := $(GNU_ARM)/bin/arm-none-eabi-gcc\nCPP   := $(GNU_ARM)/bin/arm-none-eabi-g++\nAS    := $(GNU_ARM)/bin/arm-none-eabi-as\nLINK  := $(GNU_ARM)/bin/arm-none-eabi-gcc\nBIN   := $(GNU_ARM)/bin/arm-none-eabi-objcopy\n\n##############################################################################\n# Typically you should not need to change anything below this line\n\n# basic utilities (included in QTools for Windows), see:\n#     https://www.state-machine.com/qtools\n\nMKDIR := mkdir\nRM    := rm\n\n#-----------------------------------------------------------------------------\n# build options\n#\n\n# combine all the soruces...\nC_SRCS += $(QP_SRCS)\nASM_SRCS += $(QP_ASMS)\n\nBIN_DIR := build_$(TARGET)\n\nASFLAGS = -g $(ARM_CPU) $(ARM_FPU) $(ASM_CPU) $(ASM_FPU)\n\nCFLAGS = -c -g $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -std=c99 -mthumb -Wall \\\n\t-ffunction-sections -fdata-sections \\\n\t-O $(INCLUDES) $(DEFINES)\n\nCPPFLAGS = -c -g $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -std=c++11 -mthumb -Wall \\\n\t-ffunction-sections -fdata-sections -fno-rtti -fno-exceptions \\\n\t-O $(INCLUDES) $(DEFINES)\n\nLINKFLAGS = -T$(LD_SCRIPT) $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -mthumb \\\n\t-specs=nosys.specs -specs=nano.specs \\\n\t-Wl,-Map,$(BIN_DIR)/$(OUTPUT).map,--cref,--gc-sections $(LIB_DIRS)\n\nASM_OBJS     := $(patsubst %.s,%.o,  $(notdir $(ASM_SRCS)))\nC_OBJS       := $(patsubst %.c,%.o,  $(notdir $(C_SRCS)))\nCPP_OBJS     := $(patsubst %.cpp,%.o,$(notdir $(CPP_SRCS)))\n\nTARGET_BIN   := $(BIN_DIR)/$(OUTPUT).bin\nTARGET_ELF   := $(BIN_DIR)/$(OUTPUT).elf\nASM_OBJS_EXT := $(addprefix $(BIN_DIR)/, $(ASM_OBJS))\nC_OBJS_EXT   := $(addprefix $(BIN_DIR)/, $(C_OBJS))\nC_DEPS_EXT   := $(patsubst %.o, %.d, $(C_OBJS_EXT))\nCPP_OBJS_EXT := $(addprefix $(BIN_DIR)/, $(CPP_OBJS))\nCPP_DEPS_EXT := $(patsubst %.o, %.d, $(CPP_OBJS_EXT))\n\n# create $(BIN_DIR) if it does not exist\nifeq (\"$(wildcard $(BIN_DIR))\",\"\")\n$(shell $(MKDIR) $(BIN_DIR))\nendif\n\n#-----------------------------------------------------------------------------\n# rules\n#\n\n.PHONY : run norun flash\n\nifeq ($(MAKECMDGOALS),norun)\nall : $(TARGET_BIN)\nnorun : all\nelse\nall : $(TARGET_BIN) run\nendif\n\n$(TARGET_BIN): $(TARGET_ELF)\n\t$(BIN) -O binary $< $@\n\n$(TARGET_ELF) : $(ASM_OBJS_EXT) $(C_OBJS_EXT) $(CPP_OBJS_EXT)\n\t$(LINK) $(LINKFLAGS) -o $@ $^ $(LIBS)\n\n$(BIN_DIR)/%.d : %.c\n\t$(CC) -MM -MT $(@:.d=.o) $(CFLAGS) $< > $@\n\n$(BIN_DIR)/%.d : %.cpp\n\t$(CPP) -MM -MT $(@:.d=.o) $(CPPFLAGS) $< > $@\n\n$(BIN_DIR)/%.o : %.s\n\t$(AS) $(ASFLAGS) $< -o $@\n\n$(BIN_DIR)/%.o : %.c\n\t$(CC) $(CFLAGS) $< -o $@\n\n$(BIN_DIR)/%.o : %.cpp\n\t$(CPP) $(CPPFLAGS) $< -o $@\n\n.PHONY : clean show\n\n# include dependency files only if our goal depends on their existence\nifneq ($(MAKECMDGOALS),clean)\n  ifneq ($(MAKECMDGOALS),show)\n-include $(C_DEPS_EXT) $(CPP_DEPS_EXT)\n  endif\nendif\n\n\nclean :\n\t-$(RM) $(BIN_DIR)/*.o \\\n\t$(BIN_DIR)/*.d \\\n\t$(BIN_DIR)/*.bin \\\n\t$(BIN_DIR)/*.elf \\\n\t$(BIN_DIR)/*.map\n\t\nshow:\n\t@echo PROJECT = $(PROJECT)\n\t@echo CONF = $(CONF)\n\t@echo DEFINES = $(DEFINES)\n\t@echo ASM_FPU = $(ASM_FPU)\n\t@echo ASM_SRCS = $(ASM_SRCS)\n\t@echo C_SRCS = $(C_SRCS)\n\t@echo CPP_SRCS = $(CPP_SRCS)\n\t@echo ASM_OBJS_EXT = $(ASM_OBJS_EXT)\n\t@echo C_OBJS_EXT = $(C_OBJS_EXT)\n\t@echo C_DEPS_EXT = $(C_DEPS_EXT)\n\t@echo CPP_DEPS_EXT = $(CPP_DEPS_EXT)\n\t@echo TARGET_ELF = $(TARGET_ELF)\n"
  },
  {
    "path": "sst_c/examples/blinky_button/iar/ek-tm4c123gxl.ewd",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<project>\n    <fileVersion>3</fileVersion>\n    <configuration>\n        <name>Debug</name>\n        <toolchain>\n            <name>ARM</name>\n        </toolchain>\n        <debug>1</debug>\n        <settings>\n            <name>C-SPY</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>32</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CInput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CEndian</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCVariant</name>\n                    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<name>OCJetEmuParams</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCCMSISDAPUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCCMSISDAPUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>GDBSERVER_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>TCPIP</name>\n                    <state>aaa.bbb.ccc.ddd</state>\n                </option>\n                <option>\n          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<state>0</state>\n                </option>\n                <option>\n                    <name>IjetDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>IjetInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiTargetEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    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<option>\n                    <name>IjetPreferETB</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetTraceSettingsList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetTraceSizeList</name>\n                    <version>0</version>\n                    <state>4</state>\n                </option>\n                <option>\n                    <name>FlashBoardPathSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCIjetUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCIjetUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL3S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    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               <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>JLinkSpeed</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCJLinkDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCJLinkHWResetDelay</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>JLinkInitialSpeed</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCDoJlinkMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCScanChainNonARMDevices</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkIRLength</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkCommRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkTCPIP</name>\n                    <state>aaa.bbb.ccc.ddd</state>\n                </option>\n                <option>\n                    <name>CCJLinkSpeedRadioV2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCUSBDevice</name>\n                    <version>1</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCRDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchUndef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchData</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchPrefetch</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n     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<name>CCJLinkInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJLinkUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCTcpIpAlt</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkTcpIpSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSwoClockAuto</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSwoClockEdit</name>\n                    <state>2000</state>\n                </option>\n                <option>\n                    <name>OCJLinkTraceSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkTraceSourceDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkDeviceName</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>LMIFTDI_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>3</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>LmiftdiSpeed</name>\n                    <state>500</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCLmiFtdiInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCLmiFtdiInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCLmiftdiUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiResetList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>NULINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>PEMICRO_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>3</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJPEMicroShowSettings</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>STLINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>8</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSTLinkInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSTLinkInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkResetList</name>\n                    <version>3</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSwoClockAuto</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSwoClockEdit</name>\n                    <state>2000</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCSTLinkDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSTLinkUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkJtagSpeedList</name>\n                    <version>2</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkDAPNumber</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSTLinkDebugAccessPortRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUseServerSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkProbeList</name>\n                    <version>1</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkTargetVccEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSTLinkTargetVoltage</name>\n                    <state>###Uninitialized###</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>THIRDPARTY_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CThirdPartyDriverDll</name>\n                    <state>###Uninitialized###</state>\n                </option>\n                <option>\n                    <name>CThirdPartyLogFileCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CThirdPartyLogFileEditB</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>TIFET_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>1</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCMSPFetResetList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetInterfaceRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetTargetVccTypeDefault</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetTargetVoltage</name>\n                    <state>###Uninitialized###</state>\n                </option>\n                <option>\n                    <name>CCMSPFetVCCDefault</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCMSPFetTargetSettlingtime</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetRadioJtagSpeedType</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCMSPFetConnection</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetUsbComPort</name>\n                    <state>Automatic</state>\n                </option>\n                <option>\n                    <name>CCMSPFetAllowAccessToBSL</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCMSPFetRadioEraseFlash</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>XDS100_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>9</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>TIPackageOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TIPackage</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>BoardFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCXds100BreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100DoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100UpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchUndef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchData</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchPrefetch</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCXds100SwoClockAuto</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100SwoClockEdit</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCXds100HWResetDelay</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100ResetList</name>\n                    <version>1</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100UsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCXds100UsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100JtagSpeedList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100InterfaceRadio</name>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCXds100InterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100ProbeList</name>\n                    <version>0</version>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>CCXds100SWOPortRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100SWOPort</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCXDSTargetVccEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXDSTargetVoltage</name>\n                    <state>###Uninitialized###</state>\n                </option>\n                <option>\n                    <name>OCXDSDigitalStatesConfigFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCSelectedCoreName</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <debuggerPlugins>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\CMX\\CmxArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\CMX\\CmxTinyArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\embOS\\embOSPlugin.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\FreeRtos\\FreeRtosArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\Mbed\\MbedArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\Mbed\\MbedArmPlugin2.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\OpenRTOS\\OpenRTOSPlugin.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\SafeRTOS\\SafeRTOSPlugin.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\SMX\\smxAwareIarArm9.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\SMX\\smxAwareIarArm9BE.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\ThreadX\\ThreadXArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\uCOS-II\\uCOS-II-286-KA-CSpy.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\uCOS-II\\uCOS-II-KA-CSpy.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\uCOS-III\\uCOS-III-KA-CSpy.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$EW_DIR$\\common\\plugins\\Orti\\Orti.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$EW_DIR$\\common\\plugins\\TargetAccessServer\\TargetAccessServer.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$EW_DIR$\\common\\plugins\\uCProbe\\uCProbePlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n        </debuggerPlugins>\n    </configuration>\n</project>\n"
  },
  {
    "path": "sst_c/examples/blinky_button/iar/ek-tm4c123gxl.ewp",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<project>\n    <fileVersion>3</fileVersion>\n    <configuration>\n        <name>Debug</name>\n        <toolchain>\n            <name>ARM</name>\n        </toolchain>\n        <debug>1</debug>\n        <settings>\n            <name>General</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <version>35</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>BrowseInfoPath</name>\n                    <state>build_ek-tm4c123gxl</state>\n                </option>\n                <option>\n                    <name>ExePath</name>\n                    <state>build_ek-tm4c123gxl</state>\n                </option>\n                <option>\n                    <name>ObjPath</name>\n                    <state>build_ek-tm4c123gxl</state>\n                </option>\n                <option>\n                    <name>ListPath</name>\n                    <state>build_ek-tm4c123gxl</state>\n                </option>\n                <option>\n                    <name>GEndianMode</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>Input description</name>\n                    <state>No specifier n, no float nor long long, no scan set, no assignment suppressing, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>Output description</name>\n                    <state>No specifier a, A, no specifier n, no float nor long long, no flags, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>GOutputBinary</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGCoreOrChip</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelect</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelectSlave</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RTDescription</name>\n                    <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\n                </option>\n                <option>\n                    <name>OGProductVersion</name>\n                    <state>5.11.0.50579</state>\n                </option>\n                <option>\n                    <name>OGLastSavedByProductVersion</name>\n                    <state>9.32.1.54977</state>\n                </option>\n                <option>\n                    <name>OGChipSelectEditMenu</name>\n                    <state>TM4C123GH6PM\tTexasInstruments TM4C123GH6PM</state>\n                </option>\n                <option>\n                    <name>GenLowLevelInterface</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GEndianModeBE</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OGBufferedTerminalOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GenStdoutInterface</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RTConfigPath2</name>\n                    <state>$TOOLKIT_DIR$\\inc\\c\\DLib_Config_Normal.h</state>\n                </option>\n                <option>\n                    <name>GBECoreSlave</name>\n                    <version>32</version>\n                    <state>39</state>\n                </option>\n                <option>\n                    <name>OGUseCmsis</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGUseCmsisDspLib</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibThreads</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CoreVariant</name>\n                    <version>32</version>\n                    <state>39</state>\n                </option>\n                <option>\n                    <name>GFPUDeviceSlave</name>\n                    <state>TM4C123GH6PM\tTexasInstruments TM4C123GH6PM</state>\n                </option>\n                <option>\n                    <name>FPU2</name>\n                    <version>0</version>\n                    <state>4</state>\n                </option>\n                <option>\n                    <name>NrRegs</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>NEON</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GFPUCoreSlave2</name>\n                    <version>32</version>\n                    <state>39</state>\n                </option>\n                <option>\n                    <name>OGCMSISPackSelectDevice</name>\n                </option>\n                <option>\n                    <name>OgLibHeap</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGLibAdditionalLocale</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGPrintfVariant</name>\n                    <version>0</version>\n                    <state>4</state>\n                </option>\n                <option>\n                    <name>OGPrintfMultibyteSupport</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGScanfVariant</name>\n                    <version>0</version>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>OGScanfMultibyteSupport</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GenLocaleTags</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>GenLocaleDisplayOnly</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DSPExtension</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>TrustZone</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TrustZoneModes</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGAarch64Abi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OG_32_64Device</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>BuildFilesPath</name>\n                    <state>Debug</state>\n                </option>\n                <option>\n                    <name>PointerAuthentication</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>FPU64</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>ICCARM</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>37</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CCOptimizationNoSizeConstraints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCDefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCPreprocFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPreprocComments</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPreprocLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCMnemonics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCMessages</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListAssFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListAssSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEnableRemarks</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCDiagSuppress</name>\n                    <state>Pa050</state>\n                </option>\n                <option>\n                    <name>CCDiagRemark</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagWarning</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagError</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCObjPrefix</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCAllowList</name>\n                    <version>1</version>\n                    <state>10010100</state>\n                </option>\n                <option>\n                    <name>CCDebugInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IEndianMode</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IExtraOptionsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCLangConformance</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSignedPlainChar</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCRequirePrototypes</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCDiagWarnAreErr</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCompilerRuntimeInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OutputFile</name>\n                    <state>$FILE_BNAME$.o</state>\n                </option>\n                <option>\n                    <name>CCLibConfigHeader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>PreInclude</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCIncludePath2</name>\n                    <state>$PROJ_DIR$\\..</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\include</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\ports\\arm-cm</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\CMSIS\\Include</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\ek-tm4c123gxl</state>\n                </option>\n                <option>\n                    <name>CCStdIncCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCodeSection</name>\n                    <state>.text</state>\n                </option>\n                <option>\n                    <name>IProcessorMode2</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCOptLevel</name>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCOptStrategy</name>\n                    <version>0</version>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCOptLevelSlave</name>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCPosIndRopi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPosIndRwpi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPosIndNoDynInit</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccLang</name>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>IccCDialect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccAllowVLA</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccStaticDestr</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccCppInlineSemantics</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccCmsis</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccFloatSemantics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCNoLiteralPool</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCOptStrategySlave</name>\n                    <version>0</version>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCGuardCalls</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCEncSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEncOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEncOutputBom</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCEncInput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccExceptions2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccRTTI2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OICompilerExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCStackProtection</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>AARM</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>11</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>AObjPrefix</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AEndian</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>ACaseSensitivity</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacroChars</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnWhat</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnOne</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AWarnRange1</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AWarnRange2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>ADebug</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AltRegisterNames</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ADefines</name>\n                    <state>ewarm</state>\n                </option>\n                <option>\n                    <name>AList</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AListHeader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AListing</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>Includes</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacDefs</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacExps</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacExec</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OnlyAssed</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MultiLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PageLengthCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PageLength</name>\n                    <state>80</state>\n                </option>\n                <option>\n                    <name>TabSpacing</name>\n                    <state>8</state>\n                </option>\n                <option>\n                    <name>AXRef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefDefines</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefInternal</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefDual</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AOutputFile</name>\n                    <state>$FILE_BNAME$.o</state>\n                </option>\n                <option>\n                    <name>ALimitErrorsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ALimitErrorsEdit</name>\n                    <state>100</state>\n                </option>\n                <option>\n                    <name>AIgnoreStdInclude</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AUserIncludes</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AExtraOptionsCheckV2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AExtraOptionsV2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AsmNoLiteralPool</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PreInclude</name>\n                    <state></state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>OBJCOPY</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>1</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OOCOutputFormat</name>\n                    <version>3</version>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>OCOutputOverride</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OOCOutputFile</name>\n                    <state>blinky_button.bin</state>\n                </option>\n                <option>\n                    <name>OOCCommandLineProducer</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OOCObjCopyEnable</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CUSTOM</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <extensions></extensions>\n                <cmdline></cmdline>\n                <hasPrio>1</hasPrio>\n                <buildSequence>inputOutputBased</buildSequence>\n            </data>\n        </settings>\n        <settings>\n            <name>BUILDACTION</name>\n            <archiveVersion>1</archiveVersion>\n            <data>\n                <prebuild></prebuild>\n                <postbuild></postbuild>\n            </data>\n        </settings>\n        <settings>\n            <name>ILINK</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>27</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>IlinkLibIOConfig</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkInputFileSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOutputFile</name>\n                    <state>blinky_button.out</state>\n                </option>\n                <option>\n                    <name>IlinkDebugInfoEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkKeepSymbols</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySymbol</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySegment</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryAlign</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkDefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkConfigDefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkMapFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLogFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogInitialization</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogModule</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogSection</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogVeneer</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFile</name>\n                    <state>$TOOLKIT_DIR$\\config\\linker\\TexasInstruments\\TM4C123GH6.icf</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFileSlave</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkEnableRemarks</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkSuppressDiags</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsRem</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsWarn</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsErr</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkWarningsAreErrors</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkUseExtraOptions</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkLowLevelInterfaceSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkAutoLibEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkAdditionalLibs</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkOverrideProgramEntryLabel</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkProgramEntryLabelSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkProgramEntryLabel</name>\n                    <state>__iar_program_start</state>\n                </option>\n                <option>\n                    <name>DoFill</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>FillerByte</name>\n                    <state>0xFF</state>\n                </option>\n                <option>\n                    <name>FillerStart</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>FillerEnd</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>CrcSize</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcAlign</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcPoly</name>\n                    <state>0x11021</state>\n                </option>\n                <option>\n                    <name>CrcCompl</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CrcBitOrder</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CrcInitialValue</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>DoCrc</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkBE8Slave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkBufferedTerminalOutput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkStdoutInterfaceSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcFullSize</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIElfToolPostProcess</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogAutoLibSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogRedirSymbols</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogUnusedFragments</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCrcReverseByteOrder</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCrcUseAsInput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptInline</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOptExceptionsAllow</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOptExceptionsForce</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCmsis</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptMergeDuplSections</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOptUseVfe</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptForceVfe</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkStackAnalysisEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkStackControlFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkStackCallGraphFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CrcAlgorithm</name>\n                    <version>1</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcUnitSize</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkThreadsSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLogCallGraph</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFile_AltDefault</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkEncInput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutputBom</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkHeapSelect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLocaleSelect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkTrustzoneImportLibraryOut</name>\n                    <state>iar_ek-tm4c123gxl_import_lib.o</state>\n                </option>\n                <option>\n                    <name>OILinkExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryFile2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySymbol2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySegment2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryAlign2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkLogCrtRoutineSelection</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogFragmentInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogInlining</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogMerging</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkDemangle</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkWrapperFileEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkWrapperFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkFpuProcessor</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>IARCHIVE</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>IarchiveInputs</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IarchiveOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IarchiveOutput</name>\n                    <state>###Unitialized###</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>Coder</name>\n            <archiveVersion>0</archiveVersion>\n            <data />\n        </settings>\n    </configuration>\n    <group>\n        <name>Application</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\blinky1.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\blinky3.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\blinky_button.h</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\bsp.h</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\bsp_ek-tm4c123gxl.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\button2a.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\button2b.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\main.c</name>\n        </file>\n    </group>\n    <group>\n        <name>ek-tm4c123gxl</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\ek-tm4c123gxl\\iar\\startup_TM4C123GH6PM.s</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\ek-tm4c123gxl\\system_TM4C123GH6PM.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\ek-tm4c123gxl\\TM4C123GH6PM.h</name>\n        </file>\n    </group>\n    <group>\n        <name>sst</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\src\\sst.c</name>\n        </file>\n    </group>\n    <group>\n        <name>sst_port</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\ports\\arm-cm\\sst_port.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\ports\\arm-cm\\sst_port.h</name>\n        </file>\n    </group>\n</project>\n"
  },
  {
    "path": "sst_c/examples/blinky_button/iar/ek-tm4c123gxl.eww",
    "content": "<?xml version=\"1.0\" encoding=\"iso-8859-1\"?>\n\n<workspace>\n  <project>\n    <path>$WS_DIR$\\ek-tm4c123gxl.ewp</path>\n  </project>\n  <batchBuild/>\n</workspace>\n\n\n"
  },
  {
    "path": "sst_c/examples/blinky_button/iar/nucleo-c031c6.ewd",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<project>\n    <fileVersion>3</fileVersion>\n    <configuration>\n        <name>Debug</name>\n        <toolchain>\n            <name>ARM</name>\n        </toolchain>\n        <debug>1</debug>\n        <settings>\n            <name>C-SPY</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>32</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CInput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CEndian</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCVariant</name>\n                    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</option>\n                <option>\n                    <name>CExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCDDFArgumentProducer</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCDownloadSuppressDownload</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCDownloadVerifyAll</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProductVersion</name>\n                    <state>9.32.1.54977</state>\n                </option>\n                <option>\n                    <name>OCDynDriverList</name>\n                    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</option>\n            </data>\n        </settings>\n        <settings>\n            <name>ARMSIM_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>1</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCSimDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCSimEnablePSP</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCSimPspOverrideConfig</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCSimPspConfigFile</name>\n                    <state></state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CADI_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CCadiMemory</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>Fast Model</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCADILogFileCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCADILogFileEditB</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CMSISDAP_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>4</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCIarProbeScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CMSISDAPResetList</name>\n                    <version>1</version>\n                    <state>10</state>\n                </option>\n                <option>\n                    <name>CMSISDAPHWResetDuration</name>\n                    <state>300</state>\n                </option>\n                <option>\n                    <name>CMSISDAPHWResetDelay</name>\n                    <state>200</state>\n                </option>\n                <option>\n                    <name>CMSISDAPDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CMSISDAPInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CMSISDAPInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiTargetEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPJtagSpeedList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPRestoreBreakpointsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPUpdateBreakpointsEdit</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>RDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchUndef</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchData</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchPrefetch</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchMMERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchNOCPERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchCHKERR</name>\n       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<state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiCPUNumber</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeCfgOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeConfig</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CMSISDAPProbeConfigRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPSelectedCPUBehaviour</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ICpuName</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCJetEmuParams</name>\n              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<name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCIarProbeScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetResetList</name>\n                    <version>1</version>\n                    <state>10</state>\n                </option>\n                <option>\n                    <name>IjetHWResetDuration</name>\n                    <state>300</state>\n                </option>\n                <option>\n                    <name>IjetHWResetDelay</name>\n                    <state>200</state>\n                </option>\n                <option>\n                    <name>IjetPowerFromProbe</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetPowerRadio</name>\n                    <state>0</state>\n                </option>\n      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<name>CatchSTATERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchBUSERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchINTERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSFERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchHARDERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeCfgOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeConfig</name>\n       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       <state>1</state>\n                </option>\n                <option>\n                    <name>IjetTraceSettingsList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetTraceSizeList</name>\n                    <version>0</version>\n                    <state>4</state>\n                </option>\n                <option>\n                    <name>FlashBoardPathSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCIjetUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCIjetUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL3S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL3S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL3S</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>JLINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>16</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>JLinkSpeed</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCJLinkDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCJLinkHWResetDelay</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>JLinkInitialSpeed</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCDoJlinkMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCScanChainNonARMDevices</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkIRLength</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkCommRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkTCPIP</name>\n                    <state>aaa.bbb.ccc.ddd</state>\n                </option>\n                <option>\n                    <name>CCJLinkSpeedRadioV2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCUSBDevice</name>\n                    <version>1</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCRDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchUndef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchData</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchPrefetch</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCJLinkInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJLinkResetList</name>\n                    <version>6</version>\n                    <state>5</state>\n                </option>\n                <option>\n                    <name>CCJLinkInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJLinkUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCTcpIpAlt</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkTcpIpSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSwoClockAuto</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSwoClockEdit</name>\n                    <state>2000</state>\n                </option>\n                <option>\n                    <name>OCJLinkTraceSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkTraceSourceDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkDeviceName</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>LMIFTDI_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>3</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>LmiftdiSpeed</name>\n                    <state>500</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCLmiFtdiInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCLmiFtdiInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCLmiftdiUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiResetList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>NULINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>PEMICRO_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>3</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJPEMicroShowSettings</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>STLINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>8</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSTLinkInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSTLinkInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkResetList</name>\n                    <version>3</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSwoClockAuto</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSwoClockEdit</name>\n                    <state>2000</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCSTLinkDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSTLinkUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkJtagSpeedList</name>\n                    <version>2</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkDAPNumber</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSTLinkDebugAccessPortRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUseServerSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkProbeList</name>\n                    <version>1</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkTargetVccEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSTLinkTargetVoltage</name>\n                    <state>3.3</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>THIRDPARTY_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CThirdPartyDriverDll</name>\n                    <state>###Uninitialized###</state>\n                </option>\n                <option>\n                    <name>CThirdPartyLogFileCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CThirdPartyLogFileEditB</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>TIFET_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>1</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCMSPFetResetList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetInterfaceRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetTargetVccTypeDefault</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetTargetVoltage</name>\n                    <state>###Uninitialized###</state>\n                </option>\n                <option>\n                    <name>CCMSPFetVCCDefault</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCMSPFetTargetSettlingtime</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetRadioJtagSpeedType</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCMSPFetConnection</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetUsbComPort</name>\n                    <state>Automatic</state>\n                </option>\n                <option>\n                    <name>CCMSPFetAllowAccessToBSL</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCMSPFetRadioEraseFlash</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>XDS100_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>9</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>TIPackageOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TIPackage</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>BoardFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCXds100BreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100DoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100UpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchUndef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchData</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchPrefetch</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCXds100SwoClockAuto</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100SwoClockEdit</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCXds100HWResetDelay</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100ResetList</name>\n                    <version>1</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100UsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCXds100UsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100JtagSpeedList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100InterfaceRadio</name>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCXds100InterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100ProbeList</name>\n                    <version>0</version>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>CCXds100SWOPortRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100SWOPort</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCXDSTargetVccEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXDSTargetVoltage</name>\n                    <state>###Uninitialized###</state>\n                </option>\n                <option>\n                    <name>OCXDSDigitalStatesConfigFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCSelectedCoreName</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <debuggerPlugins>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\CMX\\CmxArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\CMX\\CmxTinyArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\embOS\\embOSPlugin.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\FreeRtos\\FreeRtosArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\Mbed\\MbedArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\Mbed\\MbedArmPlugin2.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\OpenRTOS\\OpenRTOSPlugin.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\SafeRTOS\\SafeRTOSPlugin.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\SMX\\smxAwareIarArm9.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\SMX\\smxAwareIarArm9BE.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\ThreadX\\ThreadXArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\uCOS-II\\uCOS-II-286-KA-CSpy.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\uCOS-II\\uCOS-II-KA-CSpy.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\uCOS-III\\uCOS-III-KA-CSpy.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$EW_DIR$\\common\\plugins\\Orti\\Orti.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$EW_DIR$\\common\\plugins\\TargetAccessServer\\TargetAccessServer.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$EW_DIR$\\common\\plugins\\uCProbe\\uCProbePlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n        </debuggerPlugins>\n    </configuration>\n</project>\n"
  },
  {
    "path": "sst_c/examples/blinky_button/iar/nucleo-c031c6.ewp",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<project>\n    <fileVersion>3</fileVersion>\n    <configuration>\n        <name>Debug</name>\n        <toolchain>\n            <name>ARM</name>\n        </toolchain>\n        <debug>1</debug>\n        <settings>\n            <name>General</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <version>35</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>BrowseInfoPath</name>\n                    <state>build_nucleo-c031c6</state>\n                </option>\n                <option>\n                    <name>ExePath</name>\n                    <state>build_nucleo-c031c6</state>\n                </option>\n                <option>\n                    <name>ObjPath</name>\n                    <state>build_nucleo-c031c6</state>\n                </option>\n                <option>\n                    <name>ListPath</name>\n                    <state>build_nucleo-c031c6</state>\n                </option>\n                <option>\n                    <name>GEndianMode</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>Input description</name>\n                    <state>No specifier n, no float nor long long, no scan set, no assignment suppressing, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>Output description</name>\n                    <state>No specifier a, A, no specifier n, no float nor long long, no flags, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>GOutputBinary</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGCoreOrChip</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelect</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelectSlave</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RTDescription</name>\n                    <state>A compact configuration of the C/C++14 runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\n                </option>\n                <option>\n                    <name>OGProductVersion</name>\n                    <state>5.11.0.50579</state>\n                </option>\n                <option>\n                    <name>OGLastSavedByProductVersion</name>\n                    <state>9.32.1.54977</state>\n                </option>\n                <option>\n                    <name>OGChipSelectEditMenu</name>\n                    <state>STM32C031C6\tST STM32C031C6</state>\n                </option>\n                <option>\n                    <name>GenLowLevelInterface</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GEndianModeBE</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OGBufferedTerminalOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GenStdoutInterface</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RTConfigPath2</name>\n                    <state>$TOOLKIT_DIR$\\inc\\c\\DLib_Config_Normal.h</state>\n                </option>\n                <option>\n                    <name>GBECoreSlave</name>\n                    <version>32</version>\n                    <state>35</state>\n                </option>\n                <option>\n                    <name>OGUseCmsis</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGUseCmsisDspLib</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibThreads</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CoreVariant</name>\n                    <version>32</version>\n                    <state>35</state>\n                </option>\n                <option>\n                    <name>GFPUDeviceSlave</name>\n                    <state>STM32C031C6\tST STM32C031C6</state>\n                </option>\n                <option>\n                    <name>FPU2</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>NrRegs</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>NEON</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GFPUCoreSlave2</name>\n                    <version>32</version>\n                    <state>35</state>\n                </option>\n                <option>\n                    <name>OGCMSISPackSelectDevice</name>\n                </option>\n                <option>\n                    <name>OgLibHeap</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGLibAdditionalLocale</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGPrintfVariant</name>\n                    <version>0</version>\n                    <state>4</state>\n                </option>\n                <option>\n                    <name>OGPrintfMultibyteSupport</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGScanfVariant</name>\n                    <version>0</version>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>OGScanfMultibyteSupport</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GenLocaleTags</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>GenLocaleDisplayOnly</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DSPExtension</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TrustZone</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TrustZoneModes</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGAarch64Abi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OG_32_64Device</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>BuildFilesPath</name>\n                    <state>Debug</state>\n                </option>\n                <option>\n                    <name>PointerAuthentication</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>FPU64</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>ICCARM</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>37</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CCOptimizationNoSizeConstraints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCDefines</name>\n                    <state>STM32C031xx</state>\n                </option>\n                <option>\n                    <name>CCPreprocFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPreprocComments</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPreprocLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCMnemonics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCMessages</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListAssFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListAssSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEnableRemarks</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCDiagSuppress</name>\n                    <state>Pa050</state>\n                </option>\n                <option>\n                    <name>CCDiagRemark</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagWarning</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagError</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCObjPrefix</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCAllowList</name>\n                    <version>1</version>\n                    <state>10010100</state>\n                </option>\n                <option>\n                    <name>CCDebugInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IEndianMode</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IExtraOptionsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCLangConformance</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSignedPlainChar</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCRequirePrototypes</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCDiagWarnAreErr</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCompilerRuntimeInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OutputFile</name>\n                    <state>$FILE_BNAME$.o</state>\n                </option>\n                <option>\n                    <name>CCLibConfigHeader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>PreInclude</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCIncludePath2</name>\n                    <state>$PROJ_DIR$\\..</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\include</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\ports\\arm-cm</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\CMSIS\\Include</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\nucleo-c031c6</state>\n                </option>\n                <option>\n                    <name>CCStdIncCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCodeSection</name>\n                    <state>.text</state>\n                </option>\n                <option>\n                    <name>IProcessorMode2</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCOptLevel</name>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCOptStrategy</name>\n                    <version>0</version>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCOptLevelSlave</name>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCPosIndRopi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPosIndRwpi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPosIndNoDynInit</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccLang</name>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>IccCDialect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccAllowVLA</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccStaticDestr</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccCppInlineSemantics</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccCmsis</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccFloatSemantics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCNoLiteralPool</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCOptStrategySlave</name>\n                    <version>0</version>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCGuardCalls</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCEncSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEncOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEncOutputBom</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCEncInput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccExceptions2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccRTTI2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OICompilerExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCStackProtection</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>AARM</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>11</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>AObjPrefix</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AEndian</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>ACaseSensitivity</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacroChars</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnWhat</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnOne</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AWarnRange1</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AWarnRange2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>ADebug</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AltRegisterNames</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ADefines</name>\n                    <state>ewarm</state>\n                </option>\n                <option>\n                    <name>AList</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AListHeader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AListing</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>Includes</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacDefs</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacExps</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacExec</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OnlyAssed</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MultiLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PageLengthCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PageLength</name>\n                    <state>80</state>\n                </option>\n                <option>\n                    <name>TabSpacing</name>\n                    <state>8</state>\n                </option>\n                <option>\n                    <name>AXRef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefDefines</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefInternal</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefDual</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AOutputFile</name>\n                    <state>$FILE_BNAME$.o</state>\n                </option>\n                <option>\n                    <name>ALimitErrorsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ALimitErrorsEdit</name>\n                    <state>100</state>\n                </option>\n                <option>\n                    <name>AIgnoreStdInclude</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AUserIncludes</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AExtraOptionsCheckV2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AExtraOptionsV2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AsmNoLiteralPool</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PreInclude</name>\n                    <state></state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>OBJCOPY</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>1</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OOCOutputFormat</name>\n                    <version>3</version>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>OCOutputOverride</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OOCOutputFile</name>\n                    <state>blinky_button.bin</state>\n                </option>\n                <option>\n                    <name>OOCCommandLineProducer</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OOCObjCopyEnable</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CUSTOM</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <extensions></extensions>\n                <cmdline></cmdline>\n                <hasPrio>1</hasPrio>\n                <buildSequence>inputOutputBased</buildSequence>\n            </data>\n        </settings>\n        <settings>\n            <name>BUILDACTION</name>\n            <archiveVersion>1</archiveVersion>\n            <data>\n                <prebuild></prebuild>\n                <postbuild></postbuild>\n            </data>\n        </settings>\n        <settings>\n            <name>ILINK</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>27</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>IlinkLibIOConfig</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkInputFileSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOutputFile</name>\n                    <state>blinky_button.out</state>\n                </option>\n                <option>\n                    <name>IlinkDebugInfoEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkKeepSymbols</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySymbol</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySegment</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryAlign</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkDefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkConfigDefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkMapFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLogFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogInitialization</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogModule</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogSection</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogVeneer</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFile</name>\n                    <state>$TOOLKIT_DIR$/config/linker/ST/stm32c03xx6.icf</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFileSlave</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkEnableRemarks</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkSuppressDiags</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsRem</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsWarn</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsErr</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkWarningsAreErrors</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkUseExtraOptions</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkLowLevelInterfaceSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkAutoLibEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkAdditionalLibs</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkOverrideProgramEntryLabel</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkProgramEntryLabelSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkProgramEntryLabel</name>\n                    <state>__iar_program_start</state>\n                </option>\n                <option>\n                    <name>DoFill</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>FillerByte</name>\n                    <state>0xFF</state>\n                </option>\n                <option>\n                    <name>FillerStart</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>FillerEnd</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>CrcSize</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcAlign</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcPoly</name>\n                    <state>0x11021</state>\n                </option>\n                <option>\n                    <name>CrcCompl</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CrcBitOrder</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CrcInitialValue</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>DoCrc</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkBE8Slave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkBufferedTerminalOutput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkStdoutInterfaceSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcFullSize</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIElfToolPostProcess</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogAutoLibSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogRedirSymbols</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogUnusedFragments</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCrcReverseByteOrder</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCrcUseAsInput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptInline</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOptExceptionsAllow</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOptExceptionsForce</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCmsis</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptMergeDuplSections</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOptUseVfe</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptForceVfe</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkStackAnalysisEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkStackControlFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkStackCallGraphFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CrcAlgorithm</name>\n                    <version>1</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcUnitSize</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkThreadsSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLogCallGraph</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFile_AltDefault</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkEncInput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutputBom</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkHeapSelect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLocaleSelect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkTrustzoneImportLibraryOut</name>\n                    <state>iar_nucleo-c031c6_import_lib.o</state>\n                </option>\n                <option>\n                    <name>OILinkExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryFile2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySymbol2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySegment2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryAlign2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkLogCrtRoutineSelection</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogFragmentInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogInlining</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogMerging</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkDemangle</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkWrapperFileEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkWrapperFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkFpuProcessor</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>IARCHIVE</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>IarchiveInputs</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IarchiveOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IarchiveOutput</name>\n                    <state>###Unitialized###</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>Coder</name>\n            <archiveVersion>0</archiveVersion>\n            <data />\n        </settings>\n    </configuration>\n    <mfc>\n        <configuration>Debug</configuration>\n    </mfc>\n    <group>\n        <name>Application</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\blinky1.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\blinky3.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\blinky_button.h</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\bsp.h</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\bsp_nucleo-c031c6.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\button2a.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\button2b.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\main.c</name>\n        </file>\n    </group>\n    <group>\n        <name>nucleo-c031c6</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\nucleo-c031c6\\iar\\startup_stm32c031xx.s</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\nucleo-c031c6\\stm32c031xx.h</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\nucleo-c031c6\\system_stm32c0xx.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\nucleo-c031c6\\system_stm32c0xx.h</name>\n        </file>\n    </group>\n    <group>\n        <name>sst</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\src\\sst.c</name>\n        </file>\n    </group>\n    <group>\n        <name>sst_port</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\ports\\arm-cm\\sst_port.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\ports\\arm-cm\\sst_port.h</name>\n        </file>\n    </group>\n</project>\n"
  },
  {
    "path": "sst_c/examples/blinky_button/iar/nucleo-c031c6.eww",
    "content": "<?xml version=\"1.0\" encoding=\"iso-8859-1\"?>\n\n<workspace>\n  <project>\n    <path>$WS_DIR$\\nucleo-c031c6.ewp</path>\n  </project>\n  <batchBuild/>\n</workspace>\n\n\n"
  },
  {
    "path": "sst_c/examples/blinky_button/iar/nucleo-h743zi.ewd",
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<name>CMSISDAP_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>4</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCIarProbeScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CMSISDAPResetList</name>\n                    <version>1</version>\n                    <state>10</state>\n                </option>\n                <option>\n                    <name>CMSISDAPHWResetDuration</name>\n                    <state>300</state>\n                </option>\n                <option>\n                    <name>CMSISDAPHWResetDelay</name>\n                    <state>200</state>\n                </option>\n                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<name>OCJetEmuParams</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCCMSISDAPUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCCMSISDAPUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>GDBSERVER_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>TCPIP</name>\n                    <state>aaa.bbb.ccc.ddd</state>\n                </option>\n                <option>\n          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<state>0</state>\n                </option>\n                <option>\n                    <name>IjetDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>IjetInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiTargetEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    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<option>\n                    <name>IjetPreferETB</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetTraceSettingsList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetTraceSizeList</name>\n                    <version>0</version>\n                    <state>4</state>\n                </option>\n                <option>\n                    <name>FlashBoardPathSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCIjetUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCIjetUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL3S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    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               <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>JLinkSpeed</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCJLinkDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCJLinkHWResetDelay</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>JLinkInitialSpeed</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCDoJlinkMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCScanChainNonARMDevices</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkIRLength</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkCommRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkTCPIP</name>\n                    <state>aaa.bbb.ccc.ddd</state>\n                </option>\n                <option>\n                    <name>CCJLinkSpeedRadioV2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCUSBDevice</name>\n                    <version>1</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCRDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchUndef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchData</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchPrefetch</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n     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<name>CCJLinkInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJLinkUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCTcpIpAlt</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkTcpIpSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSwoClockAuto</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSwoClockEdit</name>\n                    <state>2000</state>\n                </option>\n                <option>\n                    <name>OCJLinkTraceSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkTraceSourceDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkDeviceName</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>LMIFTDI_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>3</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>LmiftdiSpeed</name>\n                    <state>500</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCLmiFtdiInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCLmiFtdiInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCLmiftdiUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiResetList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>NULINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>PEMICRO_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>3</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJPEMicroShowSettings</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>STLINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>8</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSTLinkInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSTLinkInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkResetList</name>\n                    <version>3</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCpuClockEdit</name>\n                    <state>480</state>\n                </option>\n                <option>\n                    <name>CCSwoClockAuto</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSwoClockEdit</name>\n                    <state>2000</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCSTLinkDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSTLinkUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkJtagSpeedList</name>\n                    <version>2</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkDAPNumber</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSTLinkDebugAccessPortRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUseServerSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkProbeList</name>\n                    <version>1</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkTargetVccEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSTLinkTargetVoltage</name>\n                    <state>3.3</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>THIRDPARTY_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CThirdPartyDriverDll</name>\n                    <state>###Uninitialized###</state>\n                </option>\n                <option>\n                    <name>CThirdPartyLogFileCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CThirdPartyLogFileEditB</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>TIFET_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>1</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCMSPFetResetList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetInterfaceRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetTargetVccTypeDefault</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetTargetVoltage</name>\n                    <state>###Uninitialized###</state>\n                </option>\n                <option>\n                    <name>CCMSPFetVCCDefault</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCMSPFetTargetSettlingtime</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetRadioJtagSpeedType</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCMSPFetConnection</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetUsbComPort</name>\n                    <state>Automatic</state>\n                </option>\n                <option>\n                    <name>CCMSPFetAllowAccessToBSL</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCMSPFetRadioEraseFlash</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>XDS100_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>9</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>TIPackageOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TIPackage</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>BoardFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCXds100BreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100DoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100UpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchUndef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchData</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchPrefetch</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCXds100SwoClockAuto</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100SwoClockEdit</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCXds100HWResetDelay</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100ResetList</name>\n                    <version>1</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100UsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCXds100UsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100JtagSpeedList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100InterfaceRadio</name>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCXds100InterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100ProbeList</name>\n                    <version>0</version>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>CCXds100SWOPortRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100SWOPort</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCXDSTargetVccEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXDSTargetVoltage</name>\n                    <state>###Uninitialized###</state>\n                </option>\n                <option>\n                    <name>OCXDSDigitalStatesConfigFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCSelectedCoreName</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <debuggerPlugins>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\CMX\\CmxArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\CMX\\CmxTinyArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\embOS\\embOSPlugin.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\FreeRtos\\FreeRtosArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\Mbed\\MbedArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\Mbed\\MbedArmPlugin2.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\OpenRTOS\\OpenRTOSPlugin.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\SafeRTOS\\SafeRTOSPlugin.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\SMX\\smxAwareIarArm9.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\SMX\\smxAwareIarArm9BE.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\ThreadX\\ThreadXArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\uCOS-II\\uCOS-II-286-KA-CSpy.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\uCOS-II\\uCOS-II-KA-CSpy.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\uCOS-III\\uCOS-III-KA-CSpy.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$EW_DIR$\\common\\plugins\\Orti\\Orti.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$EW_DIR$\\common\\plugins\\TargetAccessServer\\TargetAccessServer.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$EW_DIR$\\common\\plugins\\uCProbe\\uCProbePlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n        </debuggerPlugins>\n    </configuration>\n</project>\n"
  },
  {
    "path": "sst_c/examples/blinky_button/iar/nucleo-h743zi.ewp",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<project>\n    <fileVersion>3</fileVersion>\n    <configuration>\n        <name>Debug</name>\n        <toolchain>\n            <name>ARM</name>\n        </toolchain>\n        <debug>1</debug>\n        <settings>\n            <name>General</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <version>35</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>BrowseInfoPath</name>\n                    <state>build_nucleo-h743zi</state>\n                </option>\n                <option>\n                    <name>ExePath</name>\n                    <state>build_nucleo-h743zi</state>\n                </option>\n                <option>\n                    <name>ObjPath</name>\n                    <state>build_nucleo-h743zi</state>\n                </option>\n                <option>\n                    <name>ListPath</name>\n                    <state>build_nucleo-h743zi</state>\n                </option>\n                <option>\n                    <name>GEndianMode</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>Input description</name>\n                    <state>No specifier n, no float nor long long, no scan set, no assignment suppressing, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>Output description</name>\n                    <state>No specifier a, A, no specifier n, no float nor long long, no flags, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>GOutputBinary</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGCoreOrChip</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelect</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelectSlave</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RTDescription</name>\n                    <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\n                </option>\n                <option>\n                    <name>OGProductVersion</name>\n                    <state>5.11.0.50579</state>\n                </option>\n                <option>\n                    <name>OGLastSavedByProductVersion</name>\n                    <state>9.32.1.54977</state>\n                </option>\n                <option>\n                    <name>OGChipSelectEditMenu</name>\n                    <state>STM32H743ZI\tST STM32H743ZI</state>\n                </option>\n                <option>\n                    <name>GenLowLevelInterface</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GEndianModeBE</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OGBufferedTerminalOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GenStdoutInterface</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RTConfigPath2</name>\n                    <state>$TOOLKIT_DIR$\\inc\\c\\DLib_Config_Normal.h</state>\n                </option>\n                <option>\n                    <name>GBECoreSlave</name>\n                    <version>32</version>\n                    <state>41</state>\n                </option>\n                <option>\n                    <name>OGUseCmsis</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGUseCmsisDspLib</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibThreads</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CoreVariant</name>\n                    <version>32</version>\n                    <state>41</state>\n                </option>\n                <option>\n                    <name>GFPUDeviceSlave</name>\n                    <state>STM32H743ZI\tST STM32H743ZI</state>\n                </option>\n                <option>\n                    <name>FPU2</name>\n                    <version>0</version>\n                    <state>7</state>\n                </option>\n                <option>\n                    <name>NrRegs</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>NEON</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GFPUCoreSlave2</name>\n                    <version>32</version>\n                    <state>41</state>\n                </option>\n                <option>\n                    <name>OGCMSISPackSelectDevice</name>\n                </option>\n                <option>\n                    <name>OgLibHeap</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGLibAdditionalLocale</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGPrintfVariant</name>\n                    <version>0</version>\n                    <state>4</state>\n                </option>\n                <option>\n                    <name>OGPrintfMultibyteSupport</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGScanfVariant</name>\n                    <version>0</version>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>OGScanfMultibyteSupport</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GenLocaleTags</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>GenLocaleDisplayOnly</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DSPExtension</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>TrustZone</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TrustZoneModes</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGAarch64Abi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OG_32_64Device</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>BuildFilesPath</name>\n                    <state>Debug</state>\n                </option>\n                <option>\n                    <name>PointerAuthentication</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>FPU64</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>ICCARM</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>37</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CCOptimizationNoSizeConstraints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCDefines</name>\n                    <state>STM32H743xx</state>\n                </option>\n                <option>\n                    <name>CCPreprocFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPreprocComments</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPreprocLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCMnemonics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCMessages</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListAssFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListAssSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEnableRemarks</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCDiagSuppress</name>\n                    <state>Pa050</state>\n                </option>\n                <option>\n                    <name>CCDiagRemark</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagWarning</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagError</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCObjPrefix</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCAllowList</name>\n                    <version>1</version>\n                    <state>10010100</state>\n                </option>\n                <option>\n                    <name>CCDebugInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IEndianMode</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IExtraOptionsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCLangConformance</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSignedPlainChar</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCRequirePrototypes</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCDiagWarnAreErr</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCompilerRuntimeInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OutputFile</name>\n                    <state>$FILE_BNAME$.o</state>\n                </option>\n                <option>\n                    <name>CCLibConfigHeader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>PreInclude</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCIncludePath2</name>\n                    <state>$PROJ_DIR$\\..</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\include</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\ports\\arm-cm</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\CMSIS\\Include</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\nucleo-h743zi</state>\n                </option>\n                <option>\n                    <name>CCStdIncCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCodeSection</name>\n                    <state>.text</state>\n                </option>\n                <option>\n                    <name>IProcessorMode2</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCOptLevel</name>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCOptStrategy</name>\n                    <version>0</version>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCOptLevelSlave</name>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCPosIndRopi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPosIndRwpi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPosIndNoDynInit</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccLang</name>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>IccCDialect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccAllowVLA</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccStaticDestr</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccCppInlineSemantics</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccCmsis</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccFloatSemantics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCNoLiteralPool</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCOptStrategySlave</name>\n                    <version>0</version>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCGuardCalls</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCEncSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEncOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEncOutputBom</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCEncInput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccExceptions2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccRTTI2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OICompilerExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCStackProtection</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>AARM</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>11</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>AObjPrefix</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AEndian</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>ACaseSensitivity</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacroChars</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnWhat</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnOne</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AWarnRange1</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AWarnRange2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>ADebug</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AltRegisterNames</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ADefines</name>\n                    <state>ewarm</state>\n                </option>\n                <option>\n                    <name>AList</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AListHeader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AListing</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>Includes</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacDefs</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacExps</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacExec</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OnlyAssed</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MultiLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PageLengthCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PageLength</name>\n                    <state>80</state>\n                </option>\n                <option>\n                    <name>TabSpacing</name>\n                    <state>8</state>\n                </option>\n                <option>\n                    <name>AXRef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefDefines</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefInternal</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefDual</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AOutputFile</name>\n                    <state>$FILE_BNAME$.o</state>\n                </option>\n                <option>\n                    <name>ALimitErrorsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ALimitErrorsEdit</name>\n                    <state>100</state>\n                </option>\n                <option>\n                    <name>AIgnoreStdInclude</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AUserIncludes</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AExtraOptionsCheckV2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AExtraOptionsV2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AsmNoLiteralPool</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PreInclude</name>\n                    <state></state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>OBJCOPY</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>1</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OOCOutputFormat</name>\n                    <version>3</version>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>OCOutputOverride</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OOCOutputFile</name>\n                    <state>blinky_button.bin</state>\n                </option>\n                <option>\n                    <name>OOCCommandLineProducer</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OOCObjCopyEnable</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CUSTOM</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <extensions></extensions>\n                <cmdline></cmdline>\n                <hasPrio>1</hasPrio>\n                <buildSequence>inputOutputBased</buildSequence>\n            </data>\n        </settings>\n        <settings>\n            <name>BUILDACTION</name>\n            <archiveVersion>1</archiveVersion>\n            <data>\n                <prebuild></prebuild>\n                <postbuild></postbuild>\n            </data>\n        </settings>\n        <settings>\n            <name>ILINK</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>27</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>IlinkLibIOConfig</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkInputFileSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOutputFile</name>\n                    <state>blinky_button.out</state>\n                </option>\n                <option>\n                    <name>IlinkDebugInfoEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkKeepSymbols</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySymbol</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySegment</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryAlign</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkDefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkConfigDefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkMapFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLogFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogInitialization</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogModule</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogSection</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogVeneer</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFile</name>\n                    <state>$TOOLKIT_DIR$\\config\\linker\\ST\\stm32h743xI.icf</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFileSlave</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkEnableRemarks</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkSuppressDiags</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsRem</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsWarn</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsErr</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkWarningsAreErrors</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkUseExtraOptions</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkLowLevelInterfaceSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkAutoLibEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkAdditionalLibs</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkOverrideProgramEntryLabel</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkProgramEntryLabelSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkProgramEntryLabel</name>\n                    <state>__iar_program_start</state>\n                </option>\n                <option>\n                    <name>DoFill</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>FillerByte</name>\n                    <state>0xFF</state>\n                </option>\n                <option>\n                    <name>FillerStart</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>FillerEnd</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>CrcSize</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcAlign</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcPoly</name>\n                    <state>0x11021</state>\n                </option>\n                <option>\n                    <name>CrcCompl</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CrcBitOrder</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CrcInitialValue</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>DoCrc</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkBE8Slave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkBufferedTerminalOutput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkStdoutInterfaceSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcFullSize</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIElfToolPostProcess</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogAutoLibSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogRedirSymbols</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogUnusedFragments</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCrcReverseByteOrder</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCrcUseAsInput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptInline</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOptExceptionsAllow</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOptExceptionsForce</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCmsis</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptMergeDuplSections</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOptUseVfe</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptForceVfe</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkStackAnalysisEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkStackControlFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkStackCallGraphFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CrcAlgorithm</name>\n                    <version>1</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcUnitSize</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkThreadsSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLogCallGraph</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFile_AltDefault</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkEncInput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutputBom</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkHeapSelect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLocaleSelect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkTrustzoneImportLibraryOut</name>\n                    <state>iar_nucleo-h743zi_import_lib.o</state>\n                </option>\n                <option>\n                    <name>OILinkExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryFile2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySymbol2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySegment2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryAlign2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkLogCrtRoutineSelection</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogFragmentInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogInlining</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogMerging</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkDemangle</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkWrapperFileEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkWrapperFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkFpuProcessor</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>IARCHIVE</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>IarchiveInputs</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IarchiveOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IarchiveOutput</name>\n                    <state>###Unitialized###</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>Coder</name>\n            <archiveVersion>0</archiveVersion>\n            <data />\n        </settings>\n    </configuration>\n    <mfc>\n        <configuration>Debug</configuration>\n    </mfc>\n    <group>\n        <name>Application</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\blinky1.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\blinky3.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\blinky_button.h</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\bsp.h</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\bsp_nucleo-h743zi.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\button2a.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\button2b.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\main.c</name>\n        </file>\n    </group>\n    <group>\n        <name>nucleo-h743zi</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\nucleo-h743zi\\iar\\startup_stm32h743xx.s</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\nucleo-h743zi\\stm32h743xx.h</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\nucleo-h743zi\\system_stm32h7xx.c</name>\n        </file>\n    </group>\n    <group>\n        <name>sst</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\src\\sst.c</name>\n        </file>\n    </group>\n    <group>\n        <name>sst_port</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\ports\\arm-cm\\sst_port.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\ports\\arm-cm\\sst_port.h</name>\n        </file>\n    </group>\n</project>\n"
  },
  {
    "path": "sst_c/examples/blinky_button/iar/nucleo-h743zi.eww",
    "content": "<?xml version=\"1.0\" encoding=\"iso-8859-1\"?>\n\n<workspace>\n  <project>\n    <path>$WS_DIR$\\nucleo-h743zi.ewp</path>\n  </project>\n  <batchBuild/>\n</workspace>\n\n\n"
  },
  {
    "path": "sst_c/examples/blinky_button/iar/nucleo-l053r8.ewd",
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<name>CMSISDAP_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>4</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCIarProbeScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CMSISDAPResetList</name>\n                    <version>1</version>\n                    <state>10</state>\n                </option>\n                <option>\n                    <name>CMSISDAPHWResetDuration</name>\n                    <state>300</state>\n                </option>\n                <option>\n                    <name>CMSISDAPHWResetDelay</name>\n                    <state>200</state>\n                </option>\n                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<name>OCJetEmuParams</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCCMSISDAPUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCCMSISDAPUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>GDBSERVER_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>TCPIP</name>\n                    <state>aaa.bbb.ccc.ddd</state>\n                </option>\n                <option>\n          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<state>0</state>\n                </option>\n                <option>\n                    <name>IjetDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>IjetInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiTargetEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    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<option>\n                    <name>IjetPreferETB</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetTraceSettingsList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetTraceSizeList</name>\n                    <version>0</version>\n                    <state>4</state>\n                </option>\n                <option>\n                    <name>FlashBoardPathSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCIjetUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCIjetUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    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               <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>JLinkSpeed</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCJLinkDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCJLinkHWResetDelay</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>JLinkInitialSpeed</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCDoJlinkMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCScanChainNonARMDevices</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkIRLength</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkCommRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkTCPIP</name>\n                    <state>aaa.bbb.ccc.ddd</state>\n                </option>\n                <option>\n                    <name>CCJLinkSpeedRadioV2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCUSBDevice</name>\n                    <version>1</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCRDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchUndef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchData</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchPrefetch</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n     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<name>CCJLinkInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJLinkUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCTcpIpAlt</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkTcpIpSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSwoClockAuto</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSwoClockEdit</name>\n                    <state>2000</state>\n                </option>\n                <option>\n                    <name>OCJLinkTraceSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkTraceSourceDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkDeviceName</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>LMIFTDI_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>3</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>LmiftdiSpeed</name>\n                    <state>500</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCLmiFtdiInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCLmiFtdiInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCLmiftdiUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiResetList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>NULINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>PEMICRO_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>3</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJPEMicroShowSettings</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>STLINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>8</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSTLinkInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSTLinkInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkResetList</name>\n                    <version>3</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSwoClockAuto</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSwoClockEdit</name>\n                    <state>2000</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCSTLinkDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSTLinkUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkJtagSpeedList</name>\n                    <version>2</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkDAPNumber</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSTLinkDebugAccessPortRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUseServerSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkProbeList</name>\n                    <version>1</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkTargetVccEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSTLinkTargetVoltage</name>\n                    <state>3.3</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>THIRDPARTY_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CThirdPartyDriverDll</name>\n                    <state>###Uninitialized###</state>\n                </option>\n                <option>\n                    <name>CThirdPartyLogFileCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CThirdPartyLogFileEditB</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>TIFET_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>1</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCMSPFetResetList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetInterfaceRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetTargetVccTypeDefault</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetTargetVoltage</name>\n                    <state>###Uninitialized###</state>\n                </option>\n                <option>\n                    <name>CCMSPFetVCCDefault</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCMSPFetTargetSettlingtime</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetRadioJtagSpeedType</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCMSPFetConnection</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetUsbComPort</name>\n                    <state>Automatic</state>\n                </option>\n                <option>\n                    <name>CCMSPFetAllowAccessToBSL</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCMSPFetRadioEraseFlash</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>XDS100_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>9</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>TIPackageOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TIPackage</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>BoardFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCXds100BreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100DoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100UpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchUndef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchData</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchPrefetch</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCXds100SwoClockAuto</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100SwoClockEdit</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCXds100HWResetDelay</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100ResetList</name>\n                    <version>1</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100UsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCXds100UsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100JtagSpeedList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100InterfaceRadio</name>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCXds100InterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100ProbeList</name>\n                    <version>0</version>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>CCXds100SWOPortRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100SWOPort</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCXDSTargetVccEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXDSTargetVoltage</name>\n                    <state>###Uninitialized###</state>\n                </option>\n                <option>\n                    <name>OCXDSDigitalStatesConfigFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCSelectedCoreName</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <debuggerPlugins>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\CMX\\CmxArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\CMX\\CmxTinyArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\embOS\\embOSPlugin.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\FreeRtos\\FreeRtosArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\Mbed\\MbedArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\Mbed\\MbedArmPlugin2.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\OpenRTOS\\OpenRTOSPlugin.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\SafeRTOS\\SafeRTOSPlugin.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\SMX\\smxAwareIarArm9.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\SMX\\smxAwareIarArm9BE.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\ThreadX\\ThreadXArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\uCOS-II\\uCOS-II-286-KA-CSpy.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\uCOS-II\\uCOS-II-KA-CSpy.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\uCOS-III\\uCOS-III-KA-CSpy.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$EW_DIR$\\common\\plugins\\Orti\\Orti.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$EW_DIR$\\common\\plugins\\TargetAccessServer\\TargetAccessServer.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$EW_DIR$\\common\\plugins\\uCProbe\\uCProbePlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n        </debuggerPlugins>\n    </configuration>\n</project>\n"
  },
  {
    "path": "sst_c/examples/blinky_button/iar/nucleo-l053r8.ewp",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<project>\n    <fileVersion>3</fileVersion>\n    <configuration>\n        <name>Debug</name>\n        <toolchain>\n            <name>ARM</name>\n        </toolchain>\n        <debug>1</debug>\n        <settings>\n            <name>General</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <version>35</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>BrowseInfoPath</name>\n                    <state>build_nucleo-l053r8</state>\n                </option>\n                <option>\n                    <name>ExePath</name>\n                    <state>build_nucleo-l053r8</state>\n                </option>\n                <option>\n                    <name>ObjPath</name>\n                    <state>build_nucleo-l053r8</state>\n                </option>\n                <option>\n                    <name>ListPath</name>\n                    <state>build_nucleo-l053r8</state>\n                </option>\n                <option>\n                    <name>GEndianMode</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>Input description</name>\n                    <state>No specifier n, no float nor long long, no scan set, no assignment suppressing, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>Output description</name>\n                    <state>No specifier a, A, no specifier n, no float nor long long, no flags, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>GOutputBinary</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGCoreOrChip</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelect</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelectSlave</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RTDescription</name>\n                    <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\n                </option>\n                <option>\n                    <name>OGProductVersion</name>\n                    <state>5.11.0.50579</state>\n                </option>\n                <option>\n                    <name>OGLastSavedByProductVersion</name>\n                    <state>9.32.1.54977</state>\n                </option>\n                <option>\n                    <name>OGChipSelectEditMenu</name>\n                    <state>STM32L053R8\tST STM32L053R8</state>\n                </option>\n                <option>\n                    <name>GenLowLevelInterface</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GEndianModeBE</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OGBufferedTerminalOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GenStdoutInterface</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RTConfigPath2</name>\n                    <state>$TOOLKIT_DIR$\\inc\\c\\DLib_Config_Normal.h</state>\n                </option>\n                <option>\n                    <name>GBECoreSlave</name>\n                    <version>32</version>\n                    <state>35</state>\n                </option>\n                <option>\n                    <name>OGUseCmsis</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGUseCmsisDspLib</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibThreads</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CoreVariant</name>\n                    <version>32</version>\n                    <state>35</state>\n                </option>\n                <option>\n                    <name>GFPUDeviceSlave</name>\n                    <state>STM32L053R8\tST STM32L053R8</state>\n                </option>\n                <option>\n                    <name>FPU2</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>NrRegs</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>NEON</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GFPUCoreSlave2</name>\n                    <version>32</version>\n                    <state>35</state>\n                </option>\n                <option>\n                    <name>OGCMSISPackSelectDevice</name>\n                </option>\n                <option>\n                    <name>OgLibHeap</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGLibAdditionalLocale</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGPrintfVariant</name>\n                    <version>0</version>\n                    <state>4</state>\n                </option>\n                <option>\n                    <name>OGPrintfMultibyteSupport</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGScanfVariant</name>\n                    <version>0</version>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>OGScanfMultibyteSupport</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GenLocaleTags</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>GenLocaleDisplayOnly</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DSPExtension</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TrustZone</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TrustZoneModes</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGAarch64Abi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OG_32_64Device</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>BuildFilesPath</name>\n                    <state>Debug</state>\n                </option>\n                <option>\n                    <name>PointerAuthentication</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>FPU64</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>ICCARM</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>37</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CCOptimizationNoSizeConstraints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCDefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCPreprocFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPreprocComments</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPreprocLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCMnemonics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCMessages</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListAssFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListAssSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEnableRemarks</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCDiagSuppress</name>\n                    <state>Pa050</state>\n                </option>\n                <option>\n                    <name>CCDiagRemark</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagWarning</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagError</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCObjPrefix</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCAllowList</name>\n                    <version>1</version>\n                    <state>10010100</state>\n                </option>\n                <option>\n                    <name>CCDebugInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IEndianMode</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IExtraOptionsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCLangConformance</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSignedPlainChar</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCRequirePrototypes</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCDiagWarnAreErr</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCompilerRuntimeInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OutputFile</name>\n                    <state>$FILE_BNAME$.o</state>\n                </option>\n                <option>\n                    <name>CCLibConfigHeader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>PreInclude</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCIncludePath2</name>\n                    <state>$PROJ_DIR$\\..</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\include</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\ports\\arm-cm</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\CMSIS\\Include</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\nucleo-l053r8</state>\n                </option>\n                <option>\n                    <name>CCStdIncCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCodeSection</name>\n                    <state>.text</state>\n                </option>\n                <option>\n                    <name>IProcessorMode2</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCOptLevel</name>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCOptStrategy</name>\n                    <version>0</version>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCOptLevelSlave</name>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCPosIndRopi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPosIndRwpi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPosIndNoDynInit</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccLang</name>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>IccCDialect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccAllowVLA</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccStaticDestr</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccCppInlineSemantics</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccCmsis</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccFloatSemantics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCNoLiteralPool</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCOptStrategySlave</name>\n                    <version>0</version>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCGuardCalls</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCEncSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEncOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEncOutputBom</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCEncInput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccExceptions2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccRTTI2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OICompilerExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCStackProtection</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>AARM</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>11</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>AObjPrefix</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AEndian</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>ACaseSensitivity</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacroChars</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnWhat</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnOne</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AWarnRange1</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AWarnRange2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>ADebug</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AltRegisterNames</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ADefines</name>\n                    <state>ewarm</state>\n                </option>\n                <option>\n                    <name>AList</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AListHeader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AListing</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>Includes</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacDefs</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacExps</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacExec</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OnlyAssed</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MultiLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PageLengthCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PageLength</name>\n                    <state>80</state>\n                </option>\n                <option>\n                    <name>TabSpacing</name>\n                    <state>8</state>\n                </option>\n                <option>\n                    <name>AXRef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefDefines</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefInternal</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefDual</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AOutputFile</name>\n                    <state>$FILE_BNAME$.o</state>\n                </option>\n                <option>\n                    <name>ALimitErrorsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ALimitErrorsEdit</name>\n                    <state>100</state>\n                </option>\n                <option>\n                    <name>AIgnoreStdInclude</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AUserIncludes</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AExtraOptionsCheckV2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AExtraOptionsV2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AsmNoLiteralPool</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PreInclude</name>\n                    <state></state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>OBJCOPY</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>1</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OOCOutputFormat</name>\n                    <version>3</version>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>OCOutputOverride</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OOCOutputFile</name>\n                    <state>blinky_button.bin</state>\n                </option>\n                <option>\n                    <name>OOCCommandLineProducer</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OOCObjCopyEnable</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CUSTOM</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <extensions></extensions>\n                <cmdline></cmdline>\n                <hasPrio>1</hasPrio>\n                <buildSequence>inputOutputBased</buildSequence>\n            </data>\n        </settings>\n        <settings>\n            <name>BUILDACTION</name>\n            <archiveVersion>1</archiveVersion>\n            <data>\n                <prebuild></prebuild>\n                <postbuild></postbuild>\n            </data>\n        </settings>\n        <settings>\n            <name>ILINK</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>27</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>IlinkLibIOConfig</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkInputFileSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOutputFile</name>\n                    <state>blinky_button.out</state>\n                </option>\n                <option>\n                    <name>IlinkDebugInfoEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkKeepSymbols</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySymbol</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySegment</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryAlign</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkDefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkConfigDefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkMapFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLogFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogInitialization</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogModule</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogSection</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogVeneer</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFile</name>\n                    <state>$TOOLKIT_DIR$\\config\\linker\\ST\\stm32l053x8.icf</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFileSlave</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkEnableRemarks</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkSuppressDiags</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsRem</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsWarn</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsErr</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkWarningsAreErrors</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkUseExtraOptions</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkLowLevelInterfaceSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkAutoLibEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkAdditionalLibs</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkOverrideProgramEntryLabel</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkProgramEntryLabelSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkProgramEntryLabel</name>\n                    <state>__iar_program_start</state>\n                </option>\n                <option>\n                    <name>DoFill</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>FillerByte</name>\n                    <state>0xFF</state>\n                </option>\n                <option>\n                    <name>FillerStart</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>FillerEnd</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>CrcSize</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcAlign</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcPoly</name>\n                    <state>0x11021</state>\n                </option>\n                <option>\n                    <name>CrcCompl</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CrcBitOrder</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CrcInitialValue</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>DoCrc</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkBE8Slave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkBufferedTerminalOutput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkStdoutInterfaceSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcFullSize</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIElfToolPostProcess</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogAutoLibSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogRedirSymbols</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogUnusedFragments</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCrcReverseByteOrder</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCrcUseAsInput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptInline</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOptExceptionsAllow</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOptExceptionsForce</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCmsis</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptMergeDuplSections</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOptUseVfe</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptForceVfe</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkStackAnalysisEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkStackControlFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkStackCallGraphFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CrcAlgorithm</name>\n                    <version>1</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcUnitSize</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkThreadsSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLogCallGraph</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFile_AltDefault</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkEncInput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutputBom</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkHeapSelect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLocaleSelect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkTrustzoneImportLibraryOut</name>\n                    <state>iar_nucleo-l053r8_import_lib.o</state>\n                </option>\n                <option>\n                    <name>OILinkExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryFile2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySymbol2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySegment2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryAlign2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkLogCrtRoutineSelection</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogFragmentInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogInlining</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogMerging</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkDemangle</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkWrapperFileEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkWrapperFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkFpuProcessor</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>IARCHIVE</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>IarchiveInputs</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IarchiveOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IarchiveOutput</name>\n                    <state>###Unitialized###</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>Coder</name>\n            <archiveVersion>0</archiveVersion>\n            <data />\n        </settings>\n    </configuration>\n    <mfc>\n        <configuration>Debug</configuration>\n    </mfc>\n    <group>\n        <name>Application</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\blinky1.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\blinky3.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\blinky_button.h</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\bsp.h</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\bsp_nucleo-l053r8.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\button2a.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\button2b.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\main.c</name>\n        </file>\n    </group>\n    <group>\n        <name>nucleo-l053r8</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\nucleo-l053r8\\iar\\startup_stm32l053xx.s</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\nucleo-l053r8\\stm32l053xx.h</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\nucleo-l053r8\\system_stm32l0xx.c</name>\n        </file>\n    </group>\n    <group>\n        <name>sst</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\src\\sst.c</name>\n        </file>\n    </group>\n    <group>\n        <name>sst_port</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\ports\\arm-cm\\sst_port.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\ports\\arm-cm\\sst_port.h</name>\n        </file>\n    </group>\n</project>\n"
  },
  {
    "path": "sst_c/examples/blinky_button/iar/nucleo-l053r8.eww",
    "content": "<?xml version=\"1.0\" encoding=\"iso-8859-1\"?>\n\n<workspace>\n  <project>\n    <path>$WS_DIR$\\nucleo-l053r8.ewp</path>\n  </project>\n  <batchBuild/>\n</workspace>\n\n\n"
  },
  {
    "path": "sst_c/examples/blinky_button/main.c",
    "content": "/*============================================================================\n* Super-Simple Tasker (SST/C) Example\n*\n* Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n*\n* SPDX-License-Identifier: MIT\n*\n* Permission is hereby granted, free of charge, to any person obtaining a\n* copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included in\n* all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n============================================================================*/\n#include \"sst.h\"           /* SST framework */\n#include \"bsp.h\"           /* Board Support Package interface */\n#include \"blinky_button.h\" /* application shared interface */\n\n/*..........................................................................*/\nint main() {\n    SST_init(); /* initialize the SST kernel */\n    BSP_init(); /* initialize the Board Support Package */\n\n    /* instantiate and start all SST tasks... */\n    Blinky1_instantiate();\n    static SST_Evt const *blinky1QSto[10]; /* Event queue storage */\n    SST_Task_start(\n        AO_Blinky1,     /* AO pointer to start */\n        1U,             /* SST-priority */\n        blinky1QSto,    /* storage for the AO's queue */\n        ARRAY_NELEM(blinky1QSto),   /* queue length */\n        BSP_getWorkEvtBlinky1(0U)); /* initialization event */\n\n    Button2a_instantiate();\n    static SST_Evt const *button2aQSto[8]; /* Event queue storage */\n    SST_Task_start(\n        AO_Button2a,    /* AO pointer to start */\n        2U,             /* SST-priority */\n        button2aQSto,   /* storage for the AO's queue */\n        ARRAY_NELEM(button2aQSto), /* queue length */\n        (SST_Evt const *)0); /* initialization event -- not used */\n\n    Button2b_instantiate();\n    static SST_Evt const *button2bQSto[6]; /* Event queue storage */\n    SST_Task_start(\n        AO_Button2b,    /* AO pointer to start */\n        2U,             /* SST-priority */\n        button2bQSto,   /* storage for the AO's queue */\n        ARRAY_NELEM(button2bQSto), /* queue length */\n        (SST_Evt const *)0); /* initialization event -- not used */\n\n    Blinky3_instantiate();\n    static SST_Evt const *blinky3QSto[4]; /* Event queue storage */\n    SST_Task_start(\n        AO_Blinky3,     /* AO pointer to start */\n        3U,             /* SST-priority */\n        blinky3QSto,    /* storage for the AO's queue */\n        ARRAY_NELEM(blinky3QSto),   /* queue length */\n        BSP_getWorkEvtBlinky3(0U)); /* initialization event */\n\n    return SST_Task_run(); /* run the SST tasks */\n    /* NOTE; in embedded systems SST_Task_run() should not return */\n}\n\n"
  },
  {
    "path": "sst_c/examples/blinky_button.X/.gitignore",
    "content": "# .gitignore file\n\n# MPLAB X IDE (Netbeans) specific\n**/*.X/~*.*\n**/*.X/build/\n**/*.X/debug/\n**/*.X/dist/\n**/*.X/disassembly/\n**/*.X/.generated_files/\n**/*.X/nbproject/private/\n**/*.X/nbproject/*.mk\n**/*.X/nbproject/*.bash\n**/*.X/nbproject/Makefile-genesis.properties\n\n# Object files\n*.o\n*.ko\n*.obj\n*.elf\n\n# Executables\n*.exe\n\n/.generated_files\n/build\n# KDE specific\n.directory\n\n# Misc\n.svn\n*.bak"
  },
  {
    "path": "sst_c/examples/blinky_button.X/Makefile",
    "content": "#\n#  There exist several targets which are by default empty and which can be\n#  used for execution of your targets. These targets are usually executed\n#  before and after some main targets. They are:\n#\n#     .build-pre:              called before 'build' target\n#     .build-post:             called after 'build' target\n#     .clean-pre:              called before 'clean' target\n#     .clean-post:             called after 'clean' target\n#     .clobber-pre:            called before 'clobber' target\n#     .clobber-post:           called after 'clobber' target\n#     .all-pre:                called before 'all' target\n#     .all-post:               called after 'all' target\n#     .help-pre:               called before 'help' target\n#     .help-post:              called after 'help' target\n#\n#  Targets beginning with '.' are not intended to be called on their own.\n#\n#  Main targets can be executed directly, and they are:\n#\n#     build                    build a specific configuration\n#     clean                    remove built files from a configuration\n#     clobber                  remove all built files\n#     all                      build all configurations\n#     help                     print help mesage\n#\n#  Targets .build-impl, .clean-impl, .clobber-impl, .all-impl, and\n#  .help-impl are implemented in nbproject/makefile-impl.mk.\n#\n#  Available make variables:\n#\n#     CND_BASEDIR                base directory for relative paths\n#     CND_DISTDIR                default top distribution directory (build artifacts)\n#     CND_BUILDDIR               default top build directory (object files, ...)\n#     CONF                       name of current configuration\n#     CND_ARTIFACT_DIR_${CONF}   directory of build artifact (current configuration)\n#     CND_ARTIFACT_NAME_${CONF}  name of build artifact (current configuration)\n#     CND_ARTIFACT_PATH_${CONF}  path to build artifact (current configuration)\n#     CND_PACKAGE_DIR_${CONF}    directory of package (current configuration)\n#     CND_PACKAGE_NAME_${CONF}   name of package (current configuration)\n#     CND_PACKAGE_PATH_${CONF}   path to package (current configuration)\n#\n# NOCDDL\n\n\n# Environment\nMKDIR=mkdir\nCP=cp\nCCADMIN=CCadmin\nRANLIB=ranlib\n\n\n# build\nbuild: .build-post\n\n.build-pre:\n# Add your pre 'build' code here...\n\n.build-post: .build-impl\n# Add your post 'build' code here...\n\n\n# clean\nclean: .clean-post\n\n.clean-pre:\n# Add your pre 'clean' code here...\n# WARNING: the IDE does not call this target since it takes a long time to\n# simply run make. Instead, the IDE removes the configuration directories\n# under build and dist directly without calling make.\n# This target is left here so people can do a clean when running a clean\n# outside the IDE.\n\n.clean-post: .clean-impl\n# Add your post 'clean' code here...\n\n\n# clobber\nclobber: .clobber-post\n\n.clobber-pre:\n# Add your pre 'clobber' code here...\n\n.clobber-post: .clobber-impl\n# Add your post 'clobber' code here...\n\n\n# all\nall: .all-post\n\n.all-pre:\n# Add your pre 'all' code here...\n\n.all-post: .all-impl\n# Add your post 'all' code here...\n\n\n# help\nhelp: .help-post\n\n.help-pre:\n# Add your pre 'help' code here...\n\n.help-post: .help-impl\n# Add your post 'help' code here...\n\n\n\n# include project implementation makefile\ninclude nbproject/Makefile-impl.mk\n\n# include project make variables\ninclude nbproject/Makefile-variables.mk\n"
  },
  {
    "path": "sst_c/examples/blinky_button.X/blinky1.c",
    "content": "/*============================================================================\n* Super-Simple Tasker (SST/C) Example\n*\n* Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n*\n* SPDX-License-Identifier: MIT\n*\n* Permission is hereby granted, free of charge, to any person obtaining a\n* copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included in\n* all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n============================================================================*/\n#include \"sst.h\"           /* SST framework */\n#include \"bsp.h\"           /* Board Support Package interface */\n#include \"blinky_button.h\" /* application shared interface */\n\nDBC_MODULE_NAME(\"blinky1\") /* for DBC assertions in this module */\n\n/*..........................................................................*/\ntypedef struct {      /* Blinky1 task */\n    SST_Task super;   /* inherit SST_Task */\n    SST_TimeEvt te;   /* time event for generating TIMEOUT events */\n    uint16_t toggles; /* number of toggles to perform for TIMEOUT event */\n} Blinky1;\n\nstatic void Blinky1_ctor(Blinky1 * const me);\nstatic void Blinky1_init(Blinky1 * const me, SST_Evt const * const ie);\nstatic void Blinky1_dispatch(Blinky1 * const me, SST_Evt const * const e);\n\n/*..........................................................................*/\nstatic Blinky1 Blinky1_inst; /* the Blinky instance */\nSST_Task * const AO_Blinky1 = &Blinky1_inst.super; /* opaque AO pointer */\n\nvoid Blinky1_instantiate(void) {\n    Blinky1_ctor(&Blinky1_inst);\n}\n\n/*..........................................................................*/\nstatic void Blinky1_ctor(Blinky1 * const me) {\n    SST_Task_ctor(\n       &me->super,\n       (SST_Handler)&Blinky1_init,\n       (SST_Handler)&Blinky1_dispatch);\n    SST_TimeEvt_ctor(&me->te, TIMEOUT_SIG, &me->super);\n}\n/*..........................................................................*/\nstatic void Blinky1_init(Blinky1 * const me, SST_Evt const * const ie) {\n    /* the initial event must be provided and must be WORKLOAD_SIG */\n    DBC_REQUIRE(300,\n        (ie != (SST_Evt const *)0) && (ie->sig == BLINKY_WORK_SIG));\n\n    SST_TimeEvt_arm(&me->te,\n        SST_EVT_DOWNCAST(BlinkyWorkEvt, ie)->ticks,\n        SST_EVT_DOWNCAST(BlinkyWorkEvt, ie)->ticks);\n    me->toggles = SST_EVT_DOWNCAST(BlinkyWorkEvt, ie)->toggles;\n}\n/*..........................................................................*/\nstatic void Blinky1_dispatch(Blinky1 * const me, SST_Evt const * const e) {\n    switch (e->sig) {\n        case TIMEOUT_SIG: {\n            for (uint16_t i = me->toggles; i > 0U; --i) {\n                /* just to exercise SST task scheduler lock... */\n                SST_LockKey key = SST_Task_lock(3U);\n                BSP_d5on();\n                BSP_d5off();\n                SST_Task_unlock(key);\n            }\n            break;\n        }\n        case BLINKY_WORK_SIG: {\n            BSP_d5on();\n            SST_TimeEvt_arm(&me->te,\n                SST_EVT_DOWNCAST(BlinkyWorkEvt, e)->ticks,\n                SST_EVT_DOWNCAST(BlinkyWorkEvt, e)->ticks);\n            me->toggles = SST_EVT_DOWNCAST(BlinkyWorkEvt, e)->toggles;\n            BSP_d5off();\n            break;\n        }\n        default: {\n            DBC_ERROR(500); /* unexpected event */\n            break;\n        }\n    }\n}\n"
  },
  {
    "path": "sst_c/examples/blinky_button.X/blinky3.c",
    "content": "/*============================================================================\n* Super-Simple Tasker (SST/C) Example\n*\n* Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n*\n* SPDX-License-Identifier: MIT\n*\n* Permission is hereby granted, free of charge, to any person obtaining a\n* copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included in\n* all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n============================================================================*/\n#include \"sst.h\"           /* SST framework */\n#include \"bsp.h\"           /* Board Support Package interface */\n#include \"blinky_button.h\" /* application shared interface */\n\nDBC_MODULE_NAME(\"blinky3\") /* for DBC assertions in this module */\n\n/*..........................................................................*/\ntypedef struct {      /* Blinky3 task */\n    SST_Task super;   /* inherit SST_Task */\n    SST_TimeEvt te;   /* time event for generating TIMEOUT events */\n    uint16_t toggles; /* number of toggles to perform for TIMEOUT event */\n} Blinky3;\n\nstatic void Blinky3_ctor(Blinky3 * const me);\nstatic void Blinky3_init(Blinky3 * const me, SST_Evt const * const ie);\nstatic void Blinky3_dispatch(Blinky3 * const me, SST_Evt const * const e);\n\n/*..........................................................................*/\nstatic Blinky3 Blinky3_inst; /* the Blinky3 instance */\nSST_Task * const AO_Blinky3 = &Blinky3_inst.super; /* opaque AO pointer */\n\nvoid Blinky3_instantiate(void) {\n    Blinky3_ctor(&Blinky3_inst);\n}\n\n/*..........................................................................*/\nstatic void Blinky3_ctor(Blinky3 * const me) {\n    SST_Task_ctor(\n       &me->super,\n       (SST_Handler)&Blinky3_init,\n       (SST_Handler)&Blinky3_dispatch);\n    SST_TimeEvt_ctor(&me->te, TIMEOUT_SIG, &me->super);\n}\n/*..........................................................................*/\nstatic void Blinky3_init(Blinky3 * const me, SST_Evt const * const ie) {\n    /* the initial event must be provided and must be WORKLOAD_SIG */\n    DBC_REQUIRE(300,\n        (ie != (SST_Evt const *)0) && (ie->sig == BLINKY_WORK_SIG));\n\n    SST_TimeEvt_arm(&me->te,\n        SST_EVT_DOWNCAST(BlinkyWorkEvt, ie)->ticks,\n        SST_EVT_DOWNCAST(BlinkyWorkEvt, ie)->ticks);\n    me->toggles = SST_EVT_DOWNCAST(BlinkyWorkEvt, ie)->toggles;\n}\n/*..........................................................................*/\nstatic void Blinky3_dispatch(Blinky3 * const me, SST_Evt const * const e) {\n    switch (e->sig) {\n        case TIMEOUT_SIG: {\n            for (uint16_t i = me->toggles; i > 0U; --i) {\n                BSP_d2on();\n                BSP_d2off();\n            }\n            break;\n        }\n        case BLINKY_WORK_SIG: {\n            BSP_d2on();\n            SST_TimeEvt_arm(&me->te,\n                SST_EVT_DOWNCAST(BlinkyWorkEvt, e)->ticks,\n                SST_EVT_DOWNCAST(BlinkyWorkEvt, e)->ticks);\n            me->toggles = SST_EVT_DOWNCAST(BlinkyWorkEvt, e)->toggles;\n            BSP_d2off();\n            break;\n        }\n        default: {\n            DBC_ERROR(500); /* unexpected event */\n            break;\n        }\n    }\n}\n"
  },
  {
    "path": "sst_c/examples/blinky_button.X/blinky_button.h",
    "content": "/*============================================================================\n* Super-Simple Tasker (SST/C) Example\n*\n* Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n*\n* SPDX-License-Identifier: MIT\n*\n* Permission is hereby granted, free of charge, to any person obtaining a\n* copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included in\n* all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n============================================================================*/\n#ifndef BLINKY_BUTTON_H_\n#define BLINKY_BUTTON_H_\n\n#include \"dbc_assert.h\" /* Design By Contract (DBC) assertions */\n\nenum Signals {\n    TIMEOUT_SIG,\n    BUTTON_PRESSED_SIG,\n    BUTTON_RELEASED_SIG,\n    BLINKY_WORK_SIG,\n    FORWARD_PRESSED_SIG,\n    FORWARD_RELEASED_SIG,\n    /* ... */\n    MAX_SIG  /* the last signal */\n};\n\ntypedef struct {\n    SST_Evt super;    /* inherit SST_Evt */\n    uint16_t toggles; /* number of toggles of the signal */\n    uint8_t ticks;    /* number of clock ticks between */\n} BlinkyWorkEvt;\n\ntypedef struct {\n    SST_Evt super;    /* inherit SST_Evt */\n    uint16_t toggles; /* number of toggles of the signal */\n} ButtonWorkEvt;\n\nvoid Blinky1_instantiate(void);\nextern SST_Task * const AO_Blinky1;  /* opaque task pointer */\n\nvoid Blinky3_instantiate(void);\nextern SST_Task * const AO_Blinky3;  /* opaque task pointer */\n\nvoid Button2a_instantiate(void);\nextern SST_Task * const AO_Button2a; /* opaque task pointer */\n\nvoid Button2b_instantiate(void);\nextern SST_Task * const AO_Button2b; /* opaque task pointer */\n\n#endif /* BLINKY_BUTTON_H_ */\n"
  },
  {
    "path": "sst_c/examples/blinky_button.X/bsp.h",
    "content": "/*============================================================================\n* Super-Simple Tasker (SST/C) Example\n*\n* Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n*\n* SPDX-License-Identifier: MIT\n*\n* Permission is hereby granted, free of charge, to any person obtaining a\n* copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included in\n* all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n============================================================================*/\n#ifndef BSP_H_\n#define BSP_H_\n\n#define BSP_TICKS_PER_SEC 20U\n\nvoid BSP_init(void);\n\nvoid BSP_d1on(void);\nvoid BSP_d1off(void);\n\nvoid BSP_d2on(void);\nvoid BSP_d2off(void);\n\nvoid BSP_d3on(void);\nvoid BSP_d3off(void);\n\nvoid BSP_d4on(void);\nvoid BSP_d4off(void);\n\nvoid BSP_d5on(void);\nvoid BSP_d5off(void);\n\nvoid BSP_d6on(void);\nvoid BSP_d6off(void);\n\n/* immutable events for Blinky tasks */\nSST_Evt const *BSP_getWorkEvtBlinky1(uint8_t num);\nSST_Evt const *BSP_getWorkEvtBlinky3(uint8_t num);\n\n#endif /* BSP_H_ */\n"
  },
  {
    "path": "sst_c/examples/blinky_button.X/bsp_dspic33ep128gs804.c",
    "content": "/**\n * @file bsp_dspic33ep128gs804.c\n * @author ASHRAF (ashrafkamel491@gmail.com)\n * @version 1.0\n * @date 2023-06-20\n */\n\n/*============================================================================\n* Super-Simple Tasker (SST/C) Example for dsPIC33ep33ep128gs804\n*\n*                    Q u a n t u m  L e a P s\n*                    ------------------------\n*                    Modern Embedded Software\n*\n* Copyright (C) 2005 Quantum Leaps, <state-machine.com>.\n*\n* SPDX-License-Identifier: MIT\n*\n* Permission is hereby granted, free of charge, to any person obtaining a\n* copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included in\n* all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n============================================================================*/\n#include \"sst.h\"\n#include \"bsp.h\"\n#include \"blinky_button.h\"\n#include \"system_dspic33ep128gs804.h\"       /* dspic33ep drivers and register map*/\n#include <math.h>          /* to exercise the FPU */\n/* add other drivers if necessary... */\n\nDBC_MODULE_NAME(\"bsp_dspic\") /* for DBC assertions in this module */\n\n/* Local-scope defines -----------------------------------------------------*/\n\n\n/* test pins on GPIOA */\n#define TST1_PORT GPIOA\n#define TST1_PIN  PIN_4 /* LED Red */\n#define TST2_PORT GPIOA\n#define TST2_PIN  PIN_3 /* LED Blue */\n\n/* test pins on GPIOD */\n#define TST3_PORT GPIOB\n#define TST3_PIN  PIN_11\n#define TST4_PORT GPIOB\n#define TST4_PIN  PIN_12\n#define TST5_PORT GPIOB\n#define TST5_PIN  PIN_13\n\n/* test pins on GPIOA */\n#define TST6_PORT GPIOB\n#define TST6_PIN  PIN_14 /* LED Green */\n\n/* Button on the board on GPIOF */\n#define BTN_SW1_PORT GPIOC\n#define BTN_SW1      PIN_3\n\n/* ISRs used in the application ============================================*/\nvoid SysTick_Handler(void);  /* prototype */\n\n/* Timer1 ISR */\nvoid __attribute__((__interrupt__, no_auto_psv)) _T1Interrupt(void)\n{\n    IFS0bits.T1IF = 0; //Clear Timer1 interrupt flag\n    SysTick_Handler();\n}\n\nvoid SysTick_Handler(void) { /* system clock tick ISR */\n    BSP_d1on();\n\n    /* immutable timeout event */\n    static SST_Evt const tickEvt = { TIMEOUT_SIG };\n    SST_Task_post(AO_Blinky1, &tickEvt); /* every tick is fast for Blinky1 */\n    SST_Task_post(AO_Blinky3, &tickEvt);\n\n    /* Perform the debouncing of buttons. The algorithm for debouncing\n    * adapted from the book \"Embedded Systems Dictionary\" by Jack Ganssle\n    * and Michael Barr, page 71.\n    */\n    static struct ButtonsDebouncing {\n        uint32_t depressed;\n        uint32_t previous;\n    } buttons = { 0U, 0U };\n    uint32_t current = ~((BTN_SW1_PORT->PORT) & (BTN_SW1));\n    uint32_t tmp = buttons.depressed; /* save the debounced depressed */\n    buttons.depressed |= (buttons.previous & current); /* set depressed */\n    buttons.depressed &= (buttons.previous | current); /* clear released */\n    buttons.previous   = current; /* update the history */\n    tmp ^= buttons.depressed;     /* changed debounced depressed */\n    if ((tmp & BTN_SW1) != 0U) {  /* debounced SW1 state changed? */\n        if ((buttons.depressed & BTN_SW1) != 0U) { /* is SW1 depressed? */\n            /* immutable button-press event */\n            static ButtonWorkEvt const pressEvt = {\n                .super.sig = BUTTON_PRESSED_SIG,\n                .toggles = 60U\n            };\n            /* immutable forward-press event */\n            static ButtonWorkEvt const fPressEvt = {\n                .super.sig = FORWARD_PRESSED_SIG,\n                .toggles = 60U\n            };\n            SST_Task_post(AO_Button2a, &fPressEvt.super);\n            SST_Task_post(AO_Button2a, &pressEvt.super);\n        }\n        else { /* B1 is released */\n            /* immutable button-release event */\n            static ButtonWorkEvt const releaseEvt = {\n                .super.sig = BUTTON_RELEASED_SIG,\n                .toggles = 80U\n            };\n            /* immutable forward-release event */\n            static ButtonWorkEvt const fReleaseEvt = {\n                .super.sig = FORWARD_RELEASED_SIG,\n                .toggles = 80U\n            };\n            SST_Task_post(AO_Button2a, &fReleaseEvt.super);\n            SST_Task_post(AO_Button2a, &releaseEvt.super);\n        }\n    }\n\n    BSP_d1off();\n}\n\n/* Assertion handler ======================================================*/\nDBC_NORETURN\nvoid DBC_fault_handler(char const * const module, int const label) {\n    /*\n    * NOTE: add here your application-specific error handling\n    */\n    (void)module;\n    (void)label;\n\n    /* set PRIMASK to disable interrupts and stop SST right here */\n    SST_PORT_CRIT_ENTRY();\n\n#ifndef NDEBUG\n    for (;;) { /* keep blinking LED2 */\n        BSP_d6on();  /* turn LED2 on */\n        uint32_t volatile ctr;\n        for (ctr = 1000000U; ctr > 0U; --ctr) {\n        }\n        BSP_d6off(); /* turn LED2 off */\n        for (ctr = 1000000U; ctr > 0U; --ctr) {\n        }\n    }\n#endif\n    dspic_SystemReset();\n}\n/*..........................................................................*/\nvoid assert_failed(char const * const module, int const label);/* prototype */\nvoid assert_failed(char const * const module, int const label) {\n    DBC_fault_handler(module, label);\n}\n\n/* SST task activations ====================================================*/\n\n/* repurpose regular IRQs for SST Tasks */\nvoid __attribute__((__interrupt__, no_auto_psv)) _PTG0Interrupt(void) {\n    IFS9bits.PTG0IF = 0;\n    SST_Task_activate(AO_Blinky3);\n}\n\nvoid __attribute__((__interrupt__, no_auto_psv)) _PTG1Interrupt(void) {\n    IFS9bits.PTG1IF = 0;\n    SST_Task_activate(AO_Button2b);\n}\n\nvoid __attribute__((__interrupt__, no_auto_psv)) _PTG2Interrupt(void) {\n    IFS9bits.PTG2IF = 0;\n    SST_Task_activate(AO_Button2a);\n}\n\nvoid __attribute__((__interrupt__, no_auto_psv)) _PTG3Interrupt(void) {\n    IFS9bits.PTG3IF = 0;\n    SST_Task_activate(AO_Blinky1);\n}\n\n/* BSP functions ===========================================================*/\nvoid BSP_init(void) {\n\n    /* assign IRQs to tasks. NOTE: critical for SST... */\n    SST_Task_setIRQ(AO_Blinky3,  _PTG0Interrupt_n);\n    SST_Task_setIRQ(AO_Button2b, _PTG1Interrupt_n);\n    SST_Task_setIRQ(AO_Button2a, _PTG2Interrupt_n);\n    SST_Task_setIRQ(AO_Blinky1,  _PTG3Interrupt_n);\n\n\n    gpio_set_direction(TST1_PORT, TST1_PIN, GPIO_OUTPUT);\n    gpio_set_direction(TST2_PORT, TST2_PIN, GPIO_OUTPUT);\n    gpio_set_direction(TST3_PORT, TST3_PIN, GPIO_OUTPUT);\n    gpio_set_direction(TST4_PORT, TST4_PIN, GPIO_OUTPUT);\n    gpio_set_direction(TST5_PORT, TST5_PIN, GPIO_OUTPUT);\n    gpio_set_direction(TST6_PORT, TST6_PIN, GPIO_OUTPUT);\n    gpio_set_direction(BTN_SW1_PORT, BTN_SW1, GPIO_INPUT_PU);\n}\n\n/*..........................................................................*/\nstatic void exerciseFPU(float x) {\n    /* exercise the single-precision FPU by calculating the identity:\n    *  sqrt(x) == x / sqrt(x) for x > 0\n    */\n    float tmp1 = sqrtf(x); /* single-precision sqrt() */\n    float tmp2 = x / tmp1;\n    DBC_ENSURE(200, (tmp1 - 1e-4f <= tmp2) && (tmp2 <= tmp1 + 1e-4f));\n}\n\n/*..........................................................................*/\nvoid BSP_d1on(void) { /* LED-Red */\n    gpio_set_level(TST1_PORT ,TST1_PIN, 1);\n    /* don't use the FPU in the ISR */\n}\nvoid BSP_d1off(void) {\n    gpio_set_level(TST1_PORT ,TST1_PIN, 0);\n}\n/*..........................................................................*/\nvoid BSP_d2on(void) { /* LED-Blue */\n    gpio_set_level(TST2_PORT ,TST2_PIN, 1);\n    exerciseFPU(1.2345f);\n}\nvoid BSP_d2off(void) {\n    gpio_set_level(TST2_PORT ,TST2_PIN, 0);\n}\n/*..........................................................................*/\nvoid BSP_d3on(void) {\n    gpio_set_level(TST3_PORT ,TST3_PIN, 1);\n    exerciseFPU(0.345f);\n}\nvoid BSP_d3off(void) {\n    gpio_set_level(TST3_PORT ,TST3_PIN, 0);\n}\n/*..........................................................................*/\nvoid BSP_d4on(void) {\n    gpio_set_level(TST4_PORT ,TST4_PIN, 1);\n    exerciseFPU(0.456f);\n}\nvoid BSP_d4off(void) {\n    gpio_set_level(TST4_PORT ,TST4_PIN, 0);\n}\n/*..........................................................................*/\nvoid BSP_d5on(void) {\n    gpio_set_level(TST5_PORT ,TST5_PIN, 1);\n    exerciseFPU(1.567f);\n}\nvoid BSP_d5off(void) {\n    gpio_set_level(TST5_PORT ,TST5_PIN, 0);\n}\n/*..........................................................................*/\nvoid BSP_d6on(void) {  /* LED2-Green */\n    gpio_set_level(TST6_PORT ,TST6_PIN, 1);\n    exerciseFPU(1.2345f);\n}\nvoid BSP_d6off(void) {\n    gpio_set_level(TST6_PORT ,TST6_PIN, 0);\n}\n\n/*..........................................................................*/\nSST_Evt const *BSP_getWorkEvtBlinky1(uint8_t num) {\n    /* immutable work events for Blinky1 */\n    static BlinkyWorkEvt const workBlinky1[] = {\n        {\n            .super.sig = BLINKY_WORK_SIG,\n            .toggles = 40U,\n            .ticks = 5U,\n        },\n        {\n            .super.sig = BLINKY_WORK_SIG,\n            .toggles = 30U,\n            .ticks = 7U,\n        }\n    };\n    DBC_REQUIRE(500, num < ARRAY_NELEM(workBlinky1)); /* must be in range */\n    return &workBlinky1[num].super;\n}\n/*..........................................................................*/\nSST_Evt const *BSP_getWorkEvtBlinky3(uint8_t num) {\n    /* immutable work events for Blinky3 */\n    static BlinkyWorkEvt const workBlinky3[] = {\n        {\n            .super.sig = BLINKY_WORK_SIG,\n            .toggles = 20U,\n            .ticks = 5U,\n        },\n        {\n            .super.sig = BLINKY_WORK_SIG,\n            .toggles = 10U,\n            .ticks = 3U,\n        }\n    };\n    DBC_REQUIRE(600, num < ARRAY_NELEM(workBlinky3)); /* must be in range */\n    return &workBlinky3[num].super;\n}\n\n/* SST callbacks ===========================================================*/\nvoid SST_onStart(void) {\n    SystemCoreClockUpdate();\n\n    /* set up the SysTick timer \"timer1\" to fire at BSP_TICKS_PER_SEC rate */\n    volatile uint16_t temp = BSP_TICKS_PER_SEC;\n    SysTick_Config(temp);\n\n    /* set priorities of ISRs used in the system */\n    interrupt_SetPriority(_T1Interrupt_n, 7U);  // tick timer highest priority\n    /* ... */\n}\n/*..........................................................................*/\nvoid SST_onIdle(void) {\n    BSP_d6on();  /* turn LED-Green on */\n#ifdef NDEBUG\n    /* Put the CPU and peripherals to the low-power mode.\n    * you might need to customize the clock management for your application,\n    * see the datasheet for your particular MCU.\n    */\n    BSP_d6off(); /* turn LED-Green off */\n    Idle(); /* Wait-For-Interrupt */\n    BSP_d6on();  /* turn LED-Green on */\n#endif\n    BSP_d6off(); /* turn LED-Green off */\n}\n\n"
  },
  {
    "path": "sst_c/examples/blinky_button.X/button2a.c",
    "content": "/*============================================================================\n* Super-Simple Tasker (SST/C) Example\n*\n* Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n*\n* SPDX-License-Identifier: MIT\n*\n* Permission is hereby granted, free of charge, to any person obtaining a\n* copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included in\n* all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n============================================================================*/\n#include \"sst.h\"           /* SST framework */\n#include \"bsp.h\"           /* Board Support Package interface */\n#include \"blinky_button.h\" /* application shared interface */\n\nDBC_MODULE_NAME(\"button2a\") /* for DBC assertions in this module */\n\n/*..........................................................................*/\ntypedef struct {    /* Button2a task */\n    SST_Task super; /* inherit SST_Task */\n    /* add internal variables for this AO... */\n} Button2a;\n\nstatic void Button2a_ctor(Button2a * const me);\nstatic void Button2a_init(Button2a * const me, SST_Evt const * const ie);\nstatic void Button2a_dispatch(Button2a * const me, SST_Evt const * const e);\n\n/*..........................................................................*/\nstatic Button2a Button2a_inst; /* the Button2a instance */\nSST_Task * const AO_Button2a = &Button2a_inst.super; /* opaque AO pointer */\n\nvoid Button2a_instantiate(void) {\n    Button2a_ctor(&Button2a_inst);\n}\n\n/*..........................................................................*/\nstatic void Button2a_ctor(Button2a * const me) {\n    SST_Task_ctor(\n       &me->super,\n       (SST_Handler)&Button2a_init,\n       (SST_Handler)&Button2a_dispatch);\n}\n/*..........................................................................*/\nstatic void Button2a_init(Button2a * const me, SST_Evt const * const ie) {\n    (void)me;\n    (void)ie;\n}\n/*..........................................................................*/\nstatic void Button2a_dispatch(Button2a * const me, SST_Evt const * const e) {\n    (void)me;\n    switch (e->sig) {\n        case BUTTON_PRESSED_SIG: {\n            BSP_d4on();\n            /* Button2a --> Blinky1 */\n            SST_Task_post(AO_Blinky1, BSP_getWorkEvtBlinky1(1U));\n            BSP_d4off();\n\n            for (uint16_t i = SST_EVT_DOWNCAST(ButtonWorkEvt, e)->toggles;\n                 i > 0U; --i)\n            {\n                BSP_d4on();\n                BSP_d4off();\n            }\n            break;\n        }\n        case FORWARD_PRESSED_SIG: {\n            BSP_d4on();\n            /* immutable event can be forwarded to another Task */\n            SST_Task_post(AO_Button2b, e); /* Button2a --> Button2b */\n            BSP_d4off();\n            break;\n        }\n        case BUTTON_RELEASED_SIG: {\n            BSP_d4on();\n            /* Button2a --> Blinky1 */\n            SST_Task_post(AO_Blinky1, BSP_getWorkEvtBlinky1(0U));\n            BSP_d4off();\n\n            for (uint16_t i = SST_EVT_DOWNCAST(ButtonWorkEvt, e)->toggles;\n                 i > 0U; --i)\n            {\n                BSP_d4on();\n                BSP_d4off();\n            }\n            break;\n        }\n        case FORWARD_RELEASED_SIG: {\n            BSP_d4on();\n            /* immutable event can be forwarded to another Task */\n            SST_Task_post(AO_Button2b, e); /* Button2a --> Button2b */\n            BSP_d4off();\n            break;\n        }\n        default: {\n            DBC_ERROR(500); /* unexpected event */\n            break;\n        }\n    }\n}\n"
  },
  {
    "path": "sst_c/examples/blinky_button.X/button2b.c",
    "content": "/*============================================================================\n* Super-Simple Tasker (SST/C) Example\n*\n* Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n*\n* SPDX-License-Identifier: MIT\n*\n* Permission is hereby granted, free of charge, to any person obtaining a\n* copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included in\n* all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n============================================================================*/\n#include \"sst.h\"           /* SST framework */\n#include \"bsp.h\"           /* Board Support Package interface */\n#include \"blinky_button.h\" /* application shared interface */\n\nDBC_MODULE_NAME(\"button2b\") /* for DBC assertions in this module */\n\n/*..........................................................................*/\ntypedef struct {    /* Button2b task */\n    SST_Task super; /* inherit SST_Task */\n    /* add internal variables for this AO... */\n} Button2b;\n\nstatic void Button2b_ctor(Button2b * const me);\nstatic void Button2b_init(Button2b * const me, SST_Evt const * const e);\nstatic void Button2b_dispatch(Button2b * const me, SST_Evt const * const e);\n\n/*..........................................................................*/\nstatic Button2b Button2b_inst; /* the Button2b instance */\nSST_Task * const AO_Button2b = &Button2b_inst.super; /* opaque AO pointer */\n\nvoid Button2b_instantiate(void) {\n    Button2b_ctor(&Button2b_inst);\n}\n\n/*..........................................................................*/\nstatic void Button2b_ctor(Button2b * const me) {\n    SST_Task_ctor(\n       &me->super,\n       (SST_Handler)&Button2b_init,\n       (SST_Handler)&Button2b_dispatch);\n}\n/*..........................................................................*/\nstatic void Button2b_init(Button2b * const me, SST_Evt const * const ie) {\n    (void)me;\n    (void)ie;\n}\n/*..........................................................................*/\nstatic void Button2b_dispatch(Button2b * const me, SST_Evt const * const e) {\n    switch (e->sig) {\n        case FORWARD_PRESSED_SIG: {\n            BSP_d3on();\n            /* Button2b --> Blinky3 */\n            SST_Task_post(AO_Blinky3, BSP_getWorkEvtBlinky3(1U));\n            BSP_d3off();\n\n            for (uint16_t i = SST_EVT_DOWNCAST(ButtonWorkEvt, e)->toggles;\n                 i > 0U; --i)\n            {\n                BSP_d3on();\n                BSP_d3off();\n            }\n            break;\n        }\n        case FORWARD_RELEASED_SIG: {\n            BSP_d3on();\n            /* Button2b --> Blinky3 */\n            SST_Task_post(AO_Blinky3, BSP_getWorkEvtBlinky3(0U));\n            BSP_d3off();\n\n            for (uint16_t i = SST_EVT_DOWNCAST(ButtonWorkEvt, e)->toggles;\n                 i > 0U; --i)\n            {\n                BSP_d3on();\n                BSP_d3off();\n            }\n            break;\n        }\n        default: {\n            DBC_ERROR(500); /* unexpected event */\n            break;\n        }\n    }\n}\n"
  },
  {
    "path": "sst_c/examples/blinky_button.X/configuration_bits.h",
    "content": "/*\n * File:   configuration_bits.h\n * Author: AMASOU02\n *\n * Created on June 19, 2023, 7:13 AM\n */\n\n#ifndef CONFIGURATION_BITS_H\n#define    CONFIGURATION_BITS_H\n\n#ifdef    __cplusplus\nextern \"C\" {\n#endif\n\n\n// DSPIC33EP128GS804 Configuration Bit Settings\n\n// 'C' source line config statements\n\n// FSEC\n#pragma config BWRP = OFF               // Boot Segment Write-Protect bit (Boot Segment may be written)\n#pragma config BSS = DISABLED           // Boot Segment Code-Protect Level bits (No Protection (other than BWRP))\n#pragma config BSEN = OFF               // Boot Segment Control bit (No Boot Segment)\n#pragma config GWRP = OFF               // General Segment Write-Protect bit (General Segment may be written)\n#pragma config GSS = DISABLED           // General Segment Code-Protect Level bits (No Protection (other than GWRP))\n#pragma config CWRP = OFF               // Configuration Segment Write-Protect bit (Configuration Segment may be written)\n#pragma config CSS = DISABLED           // Configuration Segment Code-Protect Level bits (No Protection (other than CWRP))\n#pragma config AIVTDIS = OFF            // Alternate Interrupt Vector Table bit (Disabled AIVT)\n\n// FBSLIM\n#pragma config BSLIM = 0x1FFF           // Boot Segment Flash Page Address Limit bits (Enter Hexadecimal value)\n\n// FSIGN\n\n// FOSCSEL\n#pragma config FNOSC = FRC              // Oscillator Source Selection (Internal Fast RC (FRC))\n#pragma config IESO = OFF               // Two-speed Oscillator Start-up Enable bit (Start up with user-selected oscillator source)\n\n// FOSC\n#pragma config POSCMD = NONE            // Primary Oscillator Mode Select bits (Primary Oscillator disabled)\n#pragma config OSCIOFNC = ON            // OSC2 Pin Function bit (OSC2 is general purpose digital I/O pin)\n#pragma config IOL1WAY = ON             // Peripheral pin select configuration bit (Allow only one reconfiguration)\n#pragma config FCKSM = CSDCMD           // Clock Switching Mode bits (Both Clock switching and Fail-safe Clock Monitor are disabled)\n#pragma config PLLKEN = ON              // PLL Lock Enable Bit (Clock switch to PLL source will wait until the PLL lock signal is valid)\n\n// FWDT\n#pragma config WDTPOST = PS32768        // Watchdog Timer Postscaler bits (1:32,768)\n#pragma config WDTPRE = PR128           // Watchdog Timer Prescaler bit (1:128)\n#pragma config WDTEN = OFF              // Watchdog Timer Enable bits (WDT and SWDTEN disabled)\n#pragma config WINDIS = OFF             // Watchdog Timer Window Enable bit (Watchdog Timer in Non-Window mode)\n#pragma config WDTWIN = WIN25           // Watchdog Timer Window Select bits (WDT Window is 25% of WDT period)\n\n// FPOR\n\n// FICD\n#pragma config ICS = PGD1               // ICD Communication Channel Select bits (Communicate on PGEC1 and PGED1)\n#pragma config JTAGEN = OFF             // JTAG Enable bit (JTAG is disabled)\n#pragma config BTSWP = OFF              // BOOTSWP Instruction Enable/Disable bit (BOOTSWP instruction is disabled)\n\n// FDEVOPT\n#pragma config PWMLOCK = ON             // PWMx Lock Enable bit (Certain PWM registers may only be written after key sequency)\n#pragma config ALTI2C1 = OFF            // Alternate I2C1 Pin bit (I2C1 mapped to SDA1/SCL1 pins)\n#pragma config ALTI2C2 = OFF            // Alternate I2C2 Pin bit (I2C2 mapped to SDA2/SCL2 pins)\n#pragma config DBCC = OFF               // DACx Output Cross Connection bit (No Cross Connection between DAC outputs)\n\n// FALTREG\n#pragma config CTXT1 = OFF              // Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 1 bits (Not Assigned)\n#pragma config CTXT2 = OFF              // Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 2 bits (Not Assigned)\n#pragma config CTXT3 = OFF              // Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 2 bits (Not Assigned)\n#pragma config CTXT4 = OFF              // Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 2 bits (Not Assigned)\n\n// FBTSEQ\n#pragma config BSEQ = 0xFFF             // Relative value defining which partition will be active after device Reset; the partition containing a lower boot number will be active (Enter Hexadecimal value)\n#pragma config IBSEQ = 0xFFF            // The one's complement of BSEQ; must be calculated by the user and written during device programming. (Enter Hexadecimal value)\n\n// #pragma config statements should precede project file includes.\n// Use project enums instead of #define for ON and OFF.\n\n#include <xc.h>\n\n\n\n\n#ifdef    __cplusplus\n}\n#endif\n\n#endif    /* CONFIGURATION_BITS_H */\n\n"
  },
  {
    "path": "sst_c/examples/blinky_button.X/main.c",
    "content": "/*============================================================================\n* Super-Simple Tasker (SST/C) Example\n*\n* Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n*\n* SPDX-License-Identifier: MIT\n*\n* Permission is hereby granted, free of charge, to any person obtaining a\n* copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included in\n* all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n============================================================================*/\n#include \"configuration_bits.h\"\n#include \"sst.h\"           /* SST framework */\n#include \"bsp.h\"           /* Board Support Package interface */\n#include \"blinky_button.h\" /* application shared interface */\n\n/*..........................................................................*/\nint main() {\n    SST_init(); /* initialize the SST kernel */\n    BSP_init(); /* initialize the Board Support Package */\n\n    /* instantiate and start all SST tasks... */\n    Blinky1_instantiate();\n    static SST_Evt const *blinky1QSto[10]; /* Event queue storage */\n    SST_Task_start(\n        AO_Blinky1,     /* AO pointer to start */\n        1U,             /* SST-priority */\n        blinky1QSto,    /* storage for the AO's queue */\n        ARRAY_NELEM(blinky1QSto),   /* queue length */\n        BSP_getWorkEvtBlinky1(0U)); /* initialization event */\n\n    Button2a_instantiate();\n    static SST_Evt const *button2aQSto[8]; /* Event queue storage */\n    SST_Task_start(\n        AO_Button2a,    /* AO pointer to start */\n        2U,             /* SST-priority */\n        button2aQSto,   /* storage for the AO's queue */\n        ARRAY_NELEM(button2aQSto), /* queue length */\n        (SST_Evt const *)0); /* initialization event -- not used */\n\n    Button2b_instantiate();\n    static SST_Evt const *button2bQSto[6]; /* Event queue storage */\n    SST_Task_start(\n        AO_Button2b,    /* AO pointer to start */\n        2U,             /* SST-priority */\n        button2bQSto,   /* storage for the AO's queue */\n        ARRAY_NELEM(button2bQSto), /* queue length */\n        (SST_Evt const *)0); /* initialization event -- not used */\n\n    Blinky3_instantiate();\n    static SST_Evt const *blinky3QSto[4]; /* Event queue storage */\n    SST_Task_start(\n        AO_Blinky3,     /* AO pointer to start */\n        3U,             /* SST-priority */\n        blinky3QSto,    /* storage for the AO's queue */\n        ARRAY_NELEM(blinky3QSto),   /* queue length */\n        BSP_getWorkEvtBlinky3(0U)); /* initialization event */\n\n    return SST_Task_run(); /* run the SST tasks */\n    /* NOTE; in embedded systems SST_Task_run() should not return */\n}\n\n"
  },
  {
    "path": "sst_c/examples/blinky_button.X/nbproject/configurations.xml",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<configurationDescriptor version=\"65\">\n  <logicalFolder name=\"root\" displayName=\"root\" projectFiles=\"true\">\n    <logicalFolder name=\"HeaderFiles\"\n                   displayName=\"Header Files\"\n                   projectFiles=\"true\">\n      <itemPath>blinky_button.h</itemPath>\n      <itemPath>bsp.h</itemPath>\n      <itemPath>configuration_bits.h</itemPath>\n    </logicalFolder>\n    <logicalFolder name=\"LinkerScript\"\n                   displayName=\"Linker Files\"\n                   projectFiles=\"true\">\n    </logicalFolder>\n    <logicalFolder name=\"SourceFiles\"\n                   displayName=\"Source Files\"\n                   projectFiles=\"true\">\n      <itemPath>blinky1.c</itemPath>\n      <itemPath>blinky3.c</itemPath>\n      <itemPath>bsp_dspic33ep128gs804.c</itemPath>\n      <itemPath>button2a.c</itemPath>\n      <itemPath>button2b.c</itemPath>\n    </logicalFolder>\n    <logicalFolder name=\"include\" displayName=\"sst_include\" projectFiles=\"true\">\n      <itemPath>../../../include/dbc_assert.h</itemPath>\n      <itemPath>../../../include/sst.h</itemPath>\n    </logicalFolder>\n    <logicalFolder name=\"dspic\" displayName=\"sst_port_dspic\" projectFiles=\"true\">\n      <itemPath>../../ports/dspic/sst_port.c</itemPath>\n      <itemPath>../../ports/dspic/sst_port.h</itemPath>\n    </logicalFolder>\n    <logicalFolder name=\"src\" displayName=\"sst_src\" projectFiles=\"true\">\n      <itemPath>../../src/sst.c</itemPath>\n    </logicalFolder>\n    <logicalFolder name=\"ExternalFiles\"\n                   displayName=\"Important Files\"\n                   projectFiles=\"false\">\n      <itemPath>Makefile</itemPath>\n    </logicalFolder>\n    <itemPath>main.c</itemPath>\n    <itemPath>system_dspic33ep128gs804.c</itemPath>\n    <itemPath>system_dspic33ep128gs804.h</itemPath>\n  </logicalFolder>\n  <sourceRootList>\n    <Elem>D:\\projs\\blinky_button.X</Elem>\n    <Elem>D:\\projs\\Super-Simple-Tasker\\include</Elem>\n    <Elem>D:\\projs\\Super-Simple-Tasker\\sst_c\\src</Elem>\n    <Elem>D:\\projs\\Super-Simple-Tasker\\sst_c\\ports\\dspic</Elem>\n    <Elem>../../src</Elem>\n    <Elem>../../ports/dspic</Elem>\n    <Elem>../../../include</Elem>\n    <Elem>.</Elem>\n  </sourceRootList>\n  <projectmakefile>Makefile</projectmakefile>\n  <confs>\n    <conf name=\"default\" type=\"2\">\n      <toolsSet>\n        <developmentServer>localhost</developmentServer>\n        <targetDevice>dsPIC33EP128GS804</targetDevice>\n        <targetHeader></targetHeader>\n        <targetPluginBoard></targetPluginBoard>\n        <platformTool>PICkit3PlatformTool</platformTool>\n        <languageToolchain>XC16</languageToolchain>\n        <languageToolchainVersion>2.10</languageToolchainVersion>\n        <platform>3</platform>\n      </toolsSet>\n      <packs>\n        <pack name=\"dsPIC33E-GS_DFP\" vendor=\"Microchip\" version=\"1.3.91\"/>\n      </packs>\n      <ScriptingSettings>\n      </ScriptingSettings>\n      <compileType>\n        <linkerTool>\n          <linkerLibItems>\n          </linkerLibItems>\n        </linkerTool>\n        <archiverTool>\n        </archiverTool>\n        <loading>\n          <useAlternateLoadableFile>false</useAlternateLoadableFile>\n          <parseOnProdLoad>false</parseOnProdLoad>\n          <alternateLoadableFile></alternateLoadableFile>\n        </loading>\n        <subordinates>\n        </subordinates>\n      </compileType>\n      <makeCustomizationType>\n        <makeCustomizationPreStepEnabled>false</makeCustomizationPreStepEnabled>\n        <makeUseCleanTarget>false</makeUseCleanTarget>\n        <makeCustomizationPreStep></makeCustomizationPreStep>\n        <makeCustomizationPostStepEnabled>false</makeCustomizationPostStepEnabled>\n        <makeCustomizationPostStep></makeCustomizationPostStep>\n        <makeCustomizationPutChecksumInUserID>false</makeCustomizationPutChecksumInUserID>\n        <makeCustomizationEnableLongLines>false</makeCustomizationEnableLongLines>\n        <makeCustomizationNormalizeHexFile>false</makeCustomizationNormalizeHexFile>\n      </makeCustomizationType>\n      <C30>\n        <property key=\"cast-align\" value=\"false\"/>\n        <property key=\"code-model\" value=\"default\"/>\n        <property key=\"const-model\" value=\"default\"/>\n        <property key=\"data-model\" value=\"default\"/>\n        <property key=\"disable-instruction-scheduling\" value=\"false\"/>\n        <property key=\"enable-all-warnings\" value=\"true\"/>\n        <property key=\"enable-ansi-std\" value=\"false\"/>\n        <property key=\"enable-ansi-warnings\" value=\"false\"/>\n        <property key=\"enable-fatal-warnings\" value=\"false\"/>\n        <property key=\"enable-large-arrays\" value=\"false\"/>\n        <property key=\"enable-omit-frame-pointer\" value=\"false\"/>\n        <property key=\"enable-procedural-abstraction\" value=\"false\"/>\n        <property key=\"enable-short-double\" value=\"false\"/>\n        <property key=\"enable-symbols\" value=\"true\"/>\n        <property key=\"enable-unroll-loops\" value=\"false\"/>\n        <property key=\"expand-pragma-config\" value=\"false\"/>\n        <property key=\"extra-include-directories\"\n                  value=\"..\\..\\..\\include;..\\..\\ports\\dspic\"/>\n        <property key=\"isolate-each-function\" value=\"false\"/>\n        <property key=\"keep-inline\" value=\"false\"/>\n        <property key=\"oXC16gcc-align-arr\" value=\"false\"/>\n        <property key=\"oXC16gcc-cnsts-mauxflash\" value=\"false\"/>\n        <property key=\"oXC16gcc-data-sects\" value=\"false\"/>\n        <property key=\"oXC16gcc-errata\" value=\"\"/>\n        <property key=\"oXC16gcc-fillupper\" value=\"\"/>\n        <property key=\"oXC16gcc-large-aggregate\" value=\"false\"/>\n        <property key=\"oXC16gcc-mauxflash\" value=\"false\"/>\n        <property key=\"oXC16gcc-mpa-lvl\" value=\"\"/>\n        <property key=\"oXC16gcc-name-text-sec\" value=\"\"/>\n        <property key=\"oXC16gcc-near-chars\" value=\"false\"/>\n        <property key=\"oXC16gcc-no-isr-warn\" value=\"false\"/>\n        <property key=\"oXC16gcc-sfr-warn\" value=\"false\"/>\n        <property key=\"oXC16gcc-smar-io-lvl\" value=\"1\"/>\n        <property key=\"oXC16gcc-smart-io-fmt\" value=\"\"/>\n        <property key=\"optimization-level\" value=\"0\"/>\n        <property key=\"post-instruction-scheduling\" value=\"default\"/>\n        <property key=\"pre-instruction-scheduling\" value=\"default\"/>\n        <property key=\"preprocessor-macros\" value=\"\"/>\n        <property key=\"scalar-model\" value=\"default\"/>\n        <property key=\"use-cci\" value=\"false\"/>\n        <property key=\"use-iar\" value=\"false\"/>\n      </C30>\n      <C30-AR>\n        <property key=\"additional-options-chop-files\" value=\"false\"/>\n      </C30-AR>\n      <C30-AS>\n        <property key=\"assembler-symbols\" value=\"\"/>\n        <property key=\"expand-macros\" value=\"false\"/>\n        <property key=\"extra-include-directories-for-assembler\" value=\"\"/>\n        <property key=\"extra-include-directories-for-preprocessor\" value=\"\"/>\n        <property key=\"false-conditionals\" value=\"false\"/>\n        <property key=\"keep-locals\" value=\"false\"/>\n        <property key=\"list-assembly\" value=\"false\"/>\n        <property key=\"list-section-info\" value=\"false\"/>\n        <property key=\"list-source\" value=\"false\"/>\n        <property key=\"list-symbols\" value=\"false\"/>\n        <property key=\"oXC16asm-extra-opts\" value=\"\"/>\n        <property key=\"oXC16asm-list-to-file\" value=\"false\"/>\n        <property key=\"omit-debug-dirs\" value=\"false\"/>\n        <property key=\"omit-forms\" value=\"false\"/>\n        <property key=\"preprocessor-macros\" value=\"\"/>\n        <property key=\"relax\" value=\"false\"/>\n        <property key=\"warning-level\" value=\"emit-warnings\"/>\n      </C30-AS>\n      <C30-CO>\n        <property key=\"coverage-enable\" value=\"\"/>\n        <property key=\"stack-guidance\" value=\"false\"/>\n      </C30-CO>\n      <C30-LD>\n        <property key=\"additional-options-use-response-files\" value=\"false\"/>\n        <property key=\"boot-eeprom\" value=\"no_eeprom\"/>\n        <property key=\"boot-flash\" value=\"no_flash\"/>\n        <property key=\"boot-ram\" value=\"no_ram\"/>\n        <property key=\"boot-write-protect\" value=\"no_write_protect\"/>\n        <property key=\"enable-check-sections\" value=\"false\"/>\n        <property key=\"enable-data-init\" value=\"true\"/>\n        <property key=\"enable-default-isr\" value=\"true\"/>\n        <property key=\"enable-handles\" value=\"true\"/>\n        <property key=\"enable-pack-data\" value=\"true\"/>\n        <property key=\"extra-lib-directories\" value=\"\"/>\n        <property key=\"fill-flash-options-addr\" value=\"\"/>\n        <property key=\"fill-flash-options-const\" value=\"\"/>\n        <property key=\"fill-flash-options-how\" value=\"0\"/>\n        <property key=\"fill-flash-options-inc-const\" value=\"1\"/>\n        <property key=\"fill-flash-options-increment\" value=\"\"/>\n        <property key=\"fill-flash-options-seq\" value=\"\"/>\n        <property key=\"fill-flash-options-what\" value=\"0\"/>\n        <property key=\"general-code-protect\" value=\"no_code_protect\"/>\n        <property key=\"general-write-protect\" value=\"no_write_protect\"/>\n        <property key=\"generate-cross-reference-file\" value=\"false\"/>\n        <property key=\"heap-size\" value=\"\"/>\n        <property key=\"input-libraries\" value=\"\"/>\n        <property key=\"linker-stack\" value=\"true\"/>\n        <property key=\"linker-symbols\" value=\"\"/>\n        <property key=\"map-file\" value=\"${DISTDIR}/${PROJECTNAME}.${IMAGE_TYPE}.map\"/>\n        <property key=\"no-ivt\" value=\"false\"/>\n        <property key=\"oXC16ld-extra-opts\" value=\"\"/>\n        <property key=\"oXC16ld-fill-upper\" value=\"0\"/>\n        <property key=\"oXC16ld-force-link\" value=\"false\"/>\n        <property key=\"oXC16ld-no-smart-io\" value=\"false\"/>\n        <property key=\"oXC16ld-nostdlib\" value=\"false\"/>\n        <property key=\"oXC16ld-stackguard\" value=\"16\"/>\n        <property key=\"preprocessor-macros\" value=\"\"/>\n        <property key=\"remove-unused-sections\" value=\"false\"/>\n        <property key=\"report-memory-usage\" value=\"true\"/>\n        <property key=\"secure-eeprom\" value=\"no_eeprom\"/>\n        <property key=\"secure-flash\" value=\"no_flash\"/>\n        <property key=\"secure-ram\" value=\"no_ram\"/>\n        <property key=\"secure-write-protect\" value=\"no_write_protect\"/>\n        <property key=\"stack-size\" value=\"16\"/>\n        <property key=\"symbol-stripping\" value=\"\"/>\n        <property key=\"trace-symbols\" value=\"\"/>\n        <property key=\"warn-section-align\" value=\"false\"/>\n      </C30-LD>\n      <C30Global>\n        <property key=\"combine-sourcefiles\" value=\"false\"/>\n        <property key=\"common-include-directories\" value=\"\"/>\n        <property key=\"dual-boot-partition\" value=\"0\"/>\n        <property key=\"fast-math\" value=\"false\"/>\n        <property key=\"generic-16-bit\" value=\"false\"/>\n        <property key=\"legacy-libc\" value=\"true\"/>\n        <property key=\"mpreserve-all\" value=\"false\"/>\n        <property key=\"oXC16glb-macros\" value=\"\"/>\n        <property key=\"omit-pack-options\" value=\"1\"/>\n        <property key=\"output-file-format\" value=\"elf\"/>\n        <property key=\"preserve-all\" value=\"false\"/>\n        <property key=\"preserve-file\" value=\"\"/>\n        <property key=\"relaxed-math\" value=\"false\"/>\n        <property key=\"save-temps\" value=\"false\"/>\n      </C30Global>\n      <PICkit3PlatformTool>\n        <property key=\"ADFRZ\" value=\"true\"/>\n        <property key=\"AutoSelectMemRanges\" value=\"auto\"/>\n        <property key=\"CLC 1\" value=\"true\"/>\n        <property key=\"CLC 2\" value=\"true\"/>\n        <property key=\"CLC 3\" value=\"true\"/>\n        <property key=\"CLC 4\" value=\"true\"/>\n        <property key=\"Comparator 1\" value=\"true\"/>\n        <property key=\"Comparator 2\" value=\"true\"/>\n        <property key=\"Comparator 3\" value=\"true\"/>\n        <property key=\"Comparator 4\" value=\"true\"/>\n        <property key=\"Freeze All Other Peripherals\" value=\"true\"/>\n        <property key=\"I2C 1\" value=\"true\"/>\n        <property key=\"I2C 2\" value=\"true\"/>\n        <property key=\"INPUT CAPTURE 1\" value=\"true\"/>\n        <property key=\"INPUT CAPTURE 2\" value=\"true\"/>\n        <property key=\"INPUT CAPTURE 3\" value=\"true\"/>\n        <property key=\"INPUT CAPTURE 4\" value=\"true\"/>\n        <property key=\"OUTPUT COMPARE 1\" value=\"true\"/>\n        <property key=\"OUTPUT COMPARE 2\" value=\"true\"/>\n        <property key=\"OUTPUT COMPARE 3\" value=\"true\"/>\n        <property key=\"OUTPUT COMPARE 4\" value=\"true\"/>\n        <property key=\"PTG\" value=\"true\"/>\n        <property key=\"PWM\" value=\"true\"/>\n        <property key=\"SPI 1\" value=\"true\"/>\n        <property key=\"SPI 2\" value=\"true\"/>\n        <property key=\"SPI 3\" value=\"true\"/>\n        <property key=\"SecureSegment.SegmentProgramming\" value=\"FullChipProgramming\"/>\n        <property key=\"TIMER1\" value=\"true\"/>\n        <property key=\"TIMER2\" value=\"true\"/>\n        <property key=\"TIMER3\" value=\"true\"/>\n        <property key=\"TIMER4\" value=\"true\"/>\n        <property key=\"TIMER5\" value=\"true\"/>\n        <property key=\"ToolFirmwareFilePath\"\n                  value=\"Press to browse for a specific firmware version\"/>\n        <property key=\"ToolFirmwareOption.UseLatestFirmware\" value=\"true\"/>\n        <property key=\"UART 1\" value=\"true\"/>\n        <property key=\"UART 2\" value=\"true\"/>\n        <property key=\"debugoptions.debug-startup\" value=\"Use system settings\"/>\n        <property key=\"debugoptions.reset-behaviour\" value=\"Use system settings\"/>\n        <property key=\"debugoptions.useswbreakpoints\" value=\"false\"/>\n        <property key=\"hwtoolclock.frcindebug\" value=\"false\"/>\n        <property key=\"memories.aux\" value=\"false\"/>\n        <property key=\"memories.bootflash\" value=\"true\"/>\n        <property key=\"memories.configurationmemory\" value=\"true\"/>\n        <property key=\"memories.configurationmemory2\" value=\"true\"/>\n        <property key=\"memories.dataflash\" value=\"true\"/>\n        <property key=\"memories.eeprom\" value=\"true\"/>\n        <property key=\"memories.flashdata\" value=\"true\"/>\n        <property key=\"memories.id\" value=\"true\"/>\n        <property key=\"memories.instruction.ram\" value=\"true\"/>\n        <property key=\"memories.instruction.ram.ranges\"\n                  value=\"${memories.instruction.ram.ranges}\"/>\n        <property key=\"memories.programmemory\" value=\"true\"/>\n        <property key=\"memories.programmemory.ranges\" value=\"0-1577f\"/>\n        <property key=\"poweroptions.powerenable\" value=\"true\"/>\n        <property key=\"programmertogo.imagename\" value=\"\"/>\n        <property key=\"programoptions.donoteraseauxmem\" value=\"false\"/>\n        <property key=\"programoptions.eraseb4program\" value=\"true\"/>\n        <property key=\"programoptions.pgmspeed\" value=\"2\"/>\n        <property key=\"programoptions.preservedataflash\" value=\"false\"/>\n        <property key=\"programoptions.preservedataflash.ranges\"\n                  value=\"${programoptions.preservedataflash.ranges}\"/>\n        <property key=\"programoptions.preserveeeprom\" value=\"false\"/>\n        <property key=\"programoptions.preserveeeprom.ranges\" value=\"\"/>\n        <property key=\"programoptions.preserveprogram.ranges\" value=\"\"/>\n        <property key=\"programoptions.preserveprogramrange\" value=\"false\"/>\n        <property key=\"programoptions.preserveuserid\" value=\"false\"/>\n        <property key=\"programoptions.programcalmem\" value=\"false\"/>\n        <property key=\"programoptions.programuserotp\" value=\"false\"/>\n        <property key=\"programoptions.testmodeentrymethod\" value=\"VDDFirst\"/>\n        <property key=\"programoptions.usehighvoltageonmclr\" value=\"false\"/>\n        <property key=\"programoptions.uselvpprogramming\" value=\"false\"/>\n        <property key=\"voltagevalue\" value=\"3.5\"/>\n      </PICkit3PlatformTool>\n      <Tool>\n        <property key=\"ADFRZ\" value=\"true\"/>\n        <property key=\"AutoSelectMemRanges\" value=\"auto\"/>\n        <property key=\"CLC 1\" value=\"true\"/>\n        <property key=\"CLC 2\" value=\"true\"/>\n        <property key=\"CLC 3\" value=\"true\"/>\n        <property key=\"CLC 4\" value=\"true\"/>\n        <property key=\"Comparator 1\" value=\"true\"/>\n        <property key=\"Comparator 2\" value=\"true\"/>\n        <property key=\"Comparator 3\" value=\"true\"/>\n        <property key=\"Comparator 4\" value=\"true\"/>\n        <property key=\"Freeze All Other Peripherals\" value=\"true\"/>\n        <property key=\"I2C 1\" value=\"true\"/>\n        <property key=\"I2C 2\" value=\"true\"/>\n        <property key=\"INPUT CAPTURE 1\" value=\"true\"/>\n        <property key=\"INPUT CAPTURE 2\" value=\"true\"/>\n        <property key=\"INPUT CAPTURE 3\" value=\"true\"/>\n        <property key=\"INPUT CAPTURE 4\" value=\"true\"/>\n        <property key=\"OUTPUT COMPARE 1\" value=\"true\"/>\n        <property key=\"OUTPUT COMPARE 2\" value=\"true\"/>\n        <property key=\"OUTPUT COMPARE 3\" value=\"true\"/>\n        <property key=\"OUTPUT COMPARE 4\" value=\"true\"/>\n        <property key=\"PTG\" value=\"true\"/>\n        <property key=\"PWM\" value=\"true\"/>\n        <property key=\"SPI 1\" value=\"true\"/>\n        <property key=\"SPI 2\" value=\"true\"/>\n        <property key=\"SPI 3\" value=\"true\"/>\n        <property key=\"SecureSegment.SegmentProgramming\" value=\"FullChipProgramming\"/>\n        <property key=\"TIMER1\" value=\"true\"/>\n        <property key=\"TIMER2\" value=\"true\"/>\n        <property key=\"TIMER3\" value=\"true\"/>\n        <property key=\"TIMER4\" value=\"true\"/>\n        <property key=\"TIMER5\" value=\"true\"/>\n        <property key=\"ToolFirmwareFilePath\"\n                  value=\"Press to browse for a specific firmware version\"/>\n        <property key=\"ToolFirmwareOption.UseLatestFirmware\" value=\"true\"/>\n        <property key=\"UART 1\" value=\"true\"/>\n        <property key=\"UART 2\" value=\"true\"/>\n        <property key=\"debugoptions.debug-startup\" value=\"Use system settings\"/>\n        <property key=\"debugoptions.reset-behaviour\" value=\"Use system settings\"/>\n        <property key=\"debugoptions.useswbreakpoints\" value=\"false\"/>\n        <property key=\"firmware.download.all\" value=\"false\"/>\n        <property key=\"hwtoolclock.frcindebug\" value=\"false\"/>\n        <property key=\"memories.aux\" value=\"false\"/>\n        <property key=\"memories.bootflash\" value=\"true\"/>\n        <property key=\"memories.configurationmemory\" value=\"true\"/>\n        <property key=\"memories.configurationmemory2\" value=\"true\"/>\n        <property key=\"memories.dataflash\" value=\"true\"/>\n        <property key=\"memories.eeprom\" value=\"true\"/>\n        <property key=\"memories.flashdata\" value=\"true\"/>\n        <property key=\"memories.id\" value=\"true\"/>\n        <property key=\"memories.instruction.ram\" value=\"true\"/>\n        <property key=\"memories.instruction.ram.ranges\"\n                  value=\"${memories.instruction.ram.ranges}\"/>\n        <property key=\"memories.programmemory\" value=\"true\"/>\n        <property key=\"memories.programmemory.ranges\" value=\"0-1577f\"/>\n        <property key=\"poweroptions.powerenable\" value=\"true\"/>\n        <property key=\"programmertogo.imagename\" value=\"\"/>\n        <property key=\"programoptions.donoteraseauxmem\" value=\"false\"/>\n        <property key=\"programoptions.eraseb4program\" value=\"true\"/>\n        <property key=\"programoptions.pgmspeed\" value=\"2\"/>\n        <property key=\"programoptions.preservedataflash\" value=\"false\"/>\n        <property key=\"programoptions.preservedataflash.ranges\"\n                  value=\"${programoptions.preservedataflash.ranges}\"/>\n        <property key=\"programoptions.preserveeeprom\" value=\"false\"/>\n        <property key=\"programoptions.preserveeeprom.ranges\" value=\"\"/>\n        <property key=\"programoptions.preserveprogram.ranges\" value=\"\"/>\n        <property key=\"programoptions.preserveprogramrange\" value=\"false\"/>\n        <property key=\"programoptions.preserveuserid\" value=\"false\"/>\n        <property key=\"programoptions.programcalmem\" value=\"false\"/>\n        <property key=\"programoptions.programuserotp\" value=\"false\"/>\n        <property key=\"programoptions.testmodeentrymethod\" value=\"VDDFirst\"/>\n        <property key=\"programoptions.usehighvoltageonmclr\" value=\"false\"/>\n        <property key=\"programoptions.uselvpprogramming\" value=\"false\"/>\n        <property key=\"voltagevalue\" value=\"3.5\"/>\n      </Tool>\n    </conf>\n  </confs>\n</configurationDescriptor>\n"
  },
  {
    "path": "sst_c/examples/blinky_button.X/nbproject/project.xml",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<project xmlns=\"http://www.netbeans.org/ns/project/1\">\n    <type>com.microchip.mplab.nbide.embedded.makeproject</type>\n    <configuration>\n        <data xmlns=\"http://www.netbeans.org/ns/make-project/1\">\n            <name>blinky_button</name>\n            <creation-uuid>cafad642-ac00-400f-b645-1e39503e8bdc</creation-uuid>\n            <make-project-type>0</make-project-type>\n            <sourceEncoding>ISO-8859-1</sourceEncoding>\n            <make-dep-projects/>\n            <sourceRootList>\n                <sourceRootElem>D:\\projs\\blinky_button.X</sourceRootElem>\n                <sourceRootElem>D:\\projs\\Super-Simple-Tasker\\include</sourceRootElem>\n                <sourceRootElem>D:\\projs\\Super-Simple-Tasker\\sst_c\\src</sourceRootElem>\n                <sourceRootElem>D:\\projs\\Super-Simple-Tasker\\sst_c\\ports\\dspic</sourceRootElem>\n                <sourceRootElem>../../src</sourceRootElem>\n                <sourceRootElem>../../ports/dspic</sourceRootElem>\n                <sourceRootElem>../../../include</sourceRootElem>\n                <sourceRootElem>.</sourceRootElem>\n            </sourceRootList>\n            <confList>\n                <confElem>\n                    <name>default</name>\n                    <type>2</type>\n                </confElem>\n            </confList>\n            <formatting>\n                <project-formatting-style>false</project-formatting-style>\n            </formatting>\n        </data>\n    </configuration>\n</project>\n"
  },
  {
    "path": "sst_c/examples/blinky_button.X/system_dspic33ep128gs804.c",
    "content": "/**\n * @file system_dspic33ep128gs804.c\n * @author ASHRAF (ashrafkamel491@gmail.com)\n * @version 1\n */\n\n#include \"system_dspic33ep128gs804.h\"\n#include \"xc.h\"\n\n/**\n * Sets the output of a GPIO pin .\n * @param[in] GPIOx: where x can be (A,B,C) to select the GPIO peripheral.\n * @param pin_no: The port pin to be set to a certain output level.\n *                This parameter can be one of PIN_X where x can be (0..15) or ALL.\n * @param level: the new output state of the pin\n */\nvoid gpio_set_level(gpio_t gpio, gpio_pin_t pin_num, int8_t state)\n{\n    if (state)\n        gpio->PORT |= pin_num;\n    else\n        gpio->PORT &= ~pin_num;\n}\n\n/**\n  * Gets the input of a GPIO pin .\n  * @param[in] GPIOx: where x can be (A,B,C) to select the GPIO peripheral.\n  * @param  pin_no: The port pin to be read.\n  * This parameter can be one of PIN_X where x can be (0..15) or ALL.\n  * @return -HIGH 1\n  *         -LOW  0\n  */\nint8_t gpio_get_level(gpio_t gpio,gpio_pin_t pin_num)\n{\n    return (gpio->PORT & pin_num) ? HIGH : LOW;\n}\n\n/**\n * Sets the direction of a specific pin\n * @param[in] GPIOx: where x can be (A,B,C) to select the GPIO peripheral.\n * @param pin: The port pin to be assigned a direction.\n * This parameter can be one of PIN_X where x can be (0..15) or ALL.\n * @param direction: is the new direction of the pin\n *\n * \\b Example:\n * @code\n * gpio_set_direction(GPIOA, PIN_8, GPIO_INPUT_PU);\n * @endcode\n */\nvoid gpio_set_direction(gpio_t GPIOx, gpio_pin_t pin_no, gpio_direction_t direction)\n{\n    if(direction == GPIO_INPUT_AN)\n    {\n        GPIOx->TRIS  |= pin_no;   //set direction input\n        GPIOx->CNEN &= ~pin_no;    //disable change int\n        GPIOx->CNPU &= ~pin_no;    //disable pull up\n        GPIOx->CNPD &= ~pin_no;    //disable pull down\n        GPIOx->ANSEL |= pin_no;\n    }\n    else if (direction == GPIO_OPEN_DRAIN)\n    {\n        GPIOx->ODC |= pin_no;\n        GPIOx->ANSEL &= ~pin_no;\n    }\n    else\n    {\n        GPIOx->ODC &= ~pin_no;\n        GPIOx->ANSEL &= ~pin_no;\n        if (direction == GPIO_OUTPUT)\n        {\n            GPIOx->CNEN &= ~pin_no;    //disable change int\n            GPIOx->CNPU &= ~pin_no;    //disable pull up\n            GPIOx->CNPD &= ~pin_no;    //disable pull down\n            GPIOx->TRIS &= ~pin_no;    //set direction output\n        }\n        else\n        {\n            GPIOx->TRIS  |= pin_no;   //set direction input\n\n            if (direction == (GPIO_INPUT_PU))\n            {\n                GPIOx->CNPD  &= ~pin_no;\n                GPIOx->CNPU  |= pin_no;\n            }\n            else if (direction == (GPIO_INPUT_PD))\n            {\n                GPIOx->CNPU  &= ~pin_no;\n                GPIOx->CNPD  |= pin_no;\n            }\n        }\n    }\n\n}\n\n#define F_CPU_MHZ   7.37F\n\nvoid SysTick_Config(uint16_t Freq_hz)\n{\n\n    float period_us = 1.0/(float)Freq_hz;\n    period_us *= 1000;\n    period_us *= 1000;\n    T1CONbits.TON = 0; // Disable Timer\n    T1CONbits.TCS = 0; // Select internal instruction cycle clock\n    T1CONbits.TGATE = 0; // Disable Gated Timer mode\n    T1CONbits.TCKPS = 0b01; // Select 1:8 Prescaler\n    TMR1 = 0x00; // Clear timer register\n    volatile uint16_t temp = F_CPU_MHZ * period_us / 16; // Load the period value\n    PR1 = temp;\n    IFS0bits.T1IF = 0; // Clear Timer 1 Interrupt Flag\n    IEC0bits.T1IE = 1; // Enable Timer1 interrupt\n    T1CONbits.TON = 1; // Start Timer\n}\n\n\nvoid SystemCoreClockUpdate(void)\n{\n    /*doze divider configure*/\n    CLKDIVbits.DOZE = 0b010;\n    // use default internal Fast RC oscillator\n    // 7.37 MHz\n}\n\nvoid dspic_SystemReset(void)\n{\n    __builtin_software_breakpoint();\n}\n\n#define IFS_BASE     ((uint16_t volatile *)0x800U)  //interrupt flag Status (pend)\n#define IEC_BASE     ((uint16_t volatile *)0x820U)  //interrupt enable control\n#define IPC_BASE     ((uint16_t volatile *)0x840U)  //interrupt priority control\n\nvoid interrupt_SetPriority(IRQn_Type IRQn, uint8_t priority)\n{\n    //CLR\n    IPC_BASE[IRQn/4] &= ~(0X7<< ((IRQn%4)*4));\n    //SET\n    IPC_BASE[IRQn/4] |= priority << ((IRQn%4)*4);\n}\n\nvoid interrupt_Enable(IRQn_Type IRQn)\n{\n    IEC_BASE[IRQn/16] |= 1 << (IRQn%16);\n}\n\n"
  },
  {
    "path": "sst_c/examples/blinky_button.X/system_dspic33ep128gs804.h",
    "content": "/*\n * File:   drivers.h\n * Author: ASHRAF\n *\n * Created on June 12, 2023, 3:17 PM\n */\n\n#ifndef DRIVERS_H\n#define    DRIVERS_H\n\n#ifdef    __cplusplus\nextern \"C\" {\n#endif\n#include <stdint.h>\n#include \"xc.h\"  /* the device specific header */\n\n\n    /********* GPIO REGISTERS ********/\n\ntypedef volatile struct { // GPIO Structure\n  uint16_t TRIS;\n  uint16_t PORT;\n  uint16_t LAT;\n  uint16_t ODC;\n\n  uint16_t CNEN;\n  uint16_t CNPU;\n  uint16_t CNPD;\n  uint16_t ANSEL;\n} *const gpio_t;\n\n#define GPIOA_BASE 0xE00\n#define GPIOB_BASE 0xE10\n#define GPIOC_BASE 0xE20\n#define GPIO_CHANGE_BASE 0xE08\n\ntypedef enum {\n  _INT0Interrupt_n = 0,\n  _IC1Interrupt_n = 1,\n  _OC1Interrupt_n = 2,\n  _T1Interrupt_n = 3,\n  _DMA0Interrupt_n = 4,\n  _IC2Interrupt_n = 5,\n  _OC2Interrupt_n = 6,\n  _T2Interrupt_n = 7,\n  _T3Interrupt_n = 8,\n  _SPI1TXInterrupt_n = 9,\n  _SPI1RXInterrupt_n = 10,\n  _U1RXInterrupt_n = 11,\n  _U1TXInterrupt_n = 12,\n  _AD1Interrupt_n = 13,\n  _DMA1Interrupt_n = 14,\n  _NVMInterrupt_n = 15,\n  _SI2C1Interrupt_n = 16,\n  _MI2C1Interrupt_n = 17,\n  _CMP1Interrupt_n = 18,\n  _CNInterrupt_n = 19,\n  _INT1Interrupt_n = 20,\n  _DMA2Interrupt_n = 24,\n  _OC3Interrupt_n = 25,\n  _OC4Interrupt_n = 26,\n  _T4Interrupt_n = 27,\n  _T5Interrupt_n = 28,\n  _INT2Interrupt_n = 29,\n  _U2RXInterrupt_n = 30,\n  _U2TXInterrupt_n = 31,\n  _SPI2TXInterrupt_n = 32,\n  _SPI2RXInterrupt_n = 33,\n  _C1RxInterrupt_n = 34,\n  _C1Interrupt_n = 35,\n  _DMA3Interrupt_n = 36,\n  _IC3Interrupt_n = 37,\n  _IC4Interrupt_n = 38,\n  _SI2C2Interrupt_n = 49,\n  _MI2C2Interrupt_n = 50,\n  _INT4Interrupt_n = 54,\n  _C2RxInterrupt_n = 55,\n  _C2Interrupt_n = 56,\n  _PWMSpEventMatchInterrupt_n = 57,\n  _U1ErrInterrupt_n = 65,\n  _U2ErrInterrupt_n = 66,\n  _C1TxInterrupt_n = 70,\n  _C2TxInterrupt_n = 71,\n  _PWMSecSpEventMatchInterrupt_n = 73,\n  _SPI3TXInterrupt_n = 90,\n  _SPI3RXInterrupt_n = 91,\n  _PWM1Interrupt_n = 94,\n  _PWM2Interrupt_n = 95,\n  _PWM3Interrupt_n = 96,\n  _PWM4Interrupt_n = 97,\n  _PWM5Interrupt_n = 98,\n  _PWM6Interrupt_n = 99,\n  _PWM7Interrupt_n = 100,\n  _PWM8Interrupt_n = 101,\n  _CMP2Interrupt_n = 103,\n  _CMP3Interrupt_n = 104,\n  _CMP4Interrupt_n = 105,\n  _ADCAN0Interrupt_n = 110,\n  _ADCAN1Interrupt_n = 111,\n  _ADCAN2Interrupt_n = 112,\n  _ADCAN3Interrupt_n = 113,\n  _ADCAN4Interrupt_n = 114,\n  _ADCAN5Interrupt_n = 115,\n  _ADCAN6Interrupt_n = 116,\n  _ADCAN7Interrupt_n = 117,\n  _SPI1GInterrupt_n = 124,\n  _SPI2GInterrupt_n = 125,\n  _SPI3GInterrupt_n = 126,\n  _CLC1Interrupt_n = 138,\n  _CLC2Interrupt_n = 139,\n  _CLC3Interrupt_n = 140,\n  _CLC4Interrupt_n = 141,\n  _ICDInterrupt_n = 142,\n  _JTAGInterrupt_n = 143,\n  _PTGStepInterrupt_n = 145,\n  _PTGWDTInterrupt_n = 146,\n  _PTG0Interrupt_n = 147,\n  _PTG1Interrupt_n = 148,\n  _PTG2Interrupt_n = 149,\n  _PTG3Interrupt_n = 150,\n  _ADCAN8Interrupt_n = 151,\n  _ADCAN9Interrupt_n = 152,\n  _ADCAN10Interrupt_n = 153,\n  _ADCAN11Interrupt_n = 154,\n  _ADCAN12Interrupt_n = 155,\n  _ADCAN13Interrupt_n = 156,\n  _ADCAN14Interrupt_n = 157,\n  _ADCAN15Interrupt_n = 158,\n  _ADCAN16Interrupt_n = 159,\n  _ADCAN17Interrupt_n = 160,\n  _ADCAN18Interrupt_n = 161,\n  _ADCAN19Interrupt_n = 162,\n  _ADCAN20Interrupt_n = 163,\n  _ADCAN21Interrupt_n = 164,\n  _I2C1BCInterrupt_n = 173,\n  _I2C2BCInterrupt_n = 174,\n  _ADCMP0Interrupt_n = 177,\n  _ADCMP1Interrupt_n = 178,\n  _ADFLTR0Interrupt_n = 179,\n  _ADFLTR1Interrupt_n = 180,\n  _ADCCore0Interrupt_n = 187,\n  _ADCCore1Interrupt_n = 188,\n  _ADCCore2Interrupt_n = 189,\n  _ADCCore3Interrupt_n = 190\n}IRQn_Type;\n\n#define GPIOA      ((gpio_t)GPIOA_BASE)\n#define GPIOB      ((gpio_t)GPIOB_BASE)\n#define GPIOC      ((gpio_t)GPIOC_BASE)\n\ntypedef uint16_t gpio_pin_t;\n#define PIN_0       0x0001   //0b0000 0000 0000 0001\n#define PIN_1       0x0002   //0b0000 0000 0000 0010\n#define PIN_2       0x0004   //0b0000 0000 0000 0100\n#define PIN_3       0x0008   //0b0000 0000 0000 1000\n#define PIN_4       0x0010   //0b0000 0000 0001 0000\n#define PIN_5       0x0020   //0b0000 0000 0010 0000\n#define PIN_6       0x0040   //0b0000 0000 0100 0000\n#define PIN_7       0x0080   //0b0000 0000 1000 0000\n#define PIN_8       0x0100   //0b0000 0001 0000 0000\n#define PIN_9       0x0200   //0b0000 0010 0000 0000\n#define PIN_10      0x0400   //0b0000 0100 0000 0000\n#define PIN_11      0x0800   //0b0000 1000 0000 0000\n#define PIN_12      0x1000   //0b0001 0000 0000 0000\n#define PIN_13      0x2000   //0b0010 0000 0000 0000\n#define PIN_14      0x4000   //0b0100 0000 0000 0000\n#define PIN_15      0x8000   //0b1000 0000 0000 0000\n#define PIN_ALL     0xffff   //0b1111 1111 1111 1111\n\n\n#define HIGH 1\n#define LOW 0\n\ntypedef uint8_t gpio_direction_t;\n\n#define GPIO_INPUT          0     //\n#define GPIO_OUTPUT         1     //\n#define GPIO_INPUT_PU       2     // Pull Up\n#define GPIO_INPUT_PD       3     // Pull Down\n#define GPIO_OPEN_DRAIN     4     //\n#define GPIO_INPUT_AN       5     //\ntypedef uint8_t gpio_level_t;\n\nvoid gpio_set_direction (gpio_t GPIOx, gpio_pin_t pin_no,\n                            gpio_direction_t direction);\nvoid gpio_set_level(gpio_t gpio, gpio_pin_t pin_num, int8_t state);\nint8_t gpio_get_level(gpio_t gpio, gpio_pin_t pin_num);\n\n\nvoid dspic_SystemReset(void);\nvoid SystemCoreClockUpdate(void);\nvoid interrupt_SetPriority(IRQn_Type IRQn, uint8_t priority);\nvoid interrupt_Enable(IRQn_Type IRQn);\nvoid SysTick_Config(uint16_t freq_hz);\n\n\n#ifdef    __cplusplus\n}\n#endif\n\n#endif    /* DRIVERS_H */\n\n"
  },
  {
    "path": "sst_c/ports/arm-cm/sst_port.c",
    "content": "/*===========================================================================\n* Super-Simple Tasker (SST/C) port to ARM Cortex-M\n*\n* Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n*\n* SPDX-License-Identifier: MIT\n*\n* Permission is hereby granted, free of charge, to any person obtaining a\n* copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included in\n* all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n===========================================================================*/\n#include \"sst.h\"        /* Super-Simple Tasker (SST/C) */\n#include \"dbc_assert.h\" /* Design By Contract (DBC) assertions */\n\nDBC_MODULE_NAME(\"sst_port\") /* for DBC assertions in this module */\n\n#define NVIC_PEND    ((uint32_t volatile *)0xE000E200U)\n#define NVIC_EN      ((uint32_t volatile *)0xE000E100U)\n#define NVIC_IP      ((uint32_t volatile *)0xE000E400U)\n#define SCB_SYSPRI   ((uint32_t volatile *)0xE000ED14U)\n#define SCB_AIRCR   *((uint32_t volatile *)0xE000ED0CU)\n#define FPU_FPCCR   *((uint32_t volatile *)0xE000EF34U)\n\n/*..........................................................................*/\n/* # of unused interrupt priority bits in NVIC */\nstatic uint32_t nvic_prio_shift;\n\n/* SST kernel facilities ---------------------------------------------------*/\nvoid SST_init(void) {\n    /* determine number of NVIC priority bits by writing 0xFF to the\n    * NIVIC IP register for PendSV and then reading back the result,\n    * which has only the implemented bits set.\n    */\n    uint32_t tmp = SCB_SYSPRI[3];\n    SCB_SYSPRI[3] |= (0xFFU << 16U); /* write 0xFF to PendSV prio */\n    uint32_t prio = ((SCB_SYSPRI[3] >> 16U) & 0xFFU); /* read back */\n    SCB_SYSPRI[3] = tmp; /* restore the original PendSV prio */\n\n    for (tmp = 0U; tmp < 8U; ++tmp) {\n        if ((prio & (1U << tmp)) != 0U) {\n            break;\n        }\n    }\n    nvic_prio_shift = tmp;\n\n#if (__ARM_FP != 0)\n    /* configure the FPU for SST */\n    FPU_FPCCR |= (1U << 30U)    /* automatic FPU state preservation (ASPEN) */\n                 | (1U << 31U); /* lazy stacking (LSPEN) */\n#endif\n}\n/*..........................................................................*/\nvoid SST_start(void) {\n    /* Set the NVIC priority grouping to default 0\n    *\n    * NOTE:\n    * Typically the SST port to ARM Cortex-M should waste no NVIC priority\n    * bits for grouping. This code ensures this setting, but priority\n    * grouping can be still overridden in the application-specific\n    * callback SST_onStart().\n    */\n    uint32_t tmp = SCB_AIRCR;\n    /* clear the key bits 31:16 and priority grouping bits 10:8 */\n    tmp &= ~((0xFFFFU << 16U) | (0x7U << 8U));\n    SCB_AIRCR = (0x05FAU << 16U) | tmp;\n}\n\n/* SST Task facilities -----------------------------------------------------*/\nvoid SST_Task_setPrio(SST_Task * const me, SST_TaskPrio prio) {\n\n    /*! @pre\n    * - the IRQ number must be already set\n    * - the priority must fit in the NVIC\n    */\n    DBC_REQUIRE(200,\n                (me->nvic_irq != 0U)\n                && (prio <= (0xFFU >> nvic_prio_shift)));\n\n    /* convert the SST direct priority (1,2,..) to NVIC priority... */\n    uint32_t nvic_prio = ((0xFFU >> nvic_prio_shift) + 1U - prio)\n                         << nvic_prio_shift;\n\n    SST_PORT_CRIT_STAT\n    SST_PORT_CRIT_ENTRY();\n    /* set the Task priority of the associated IRQ */\n    uint32_t tmp = NVIC_IP[me->nvic_irq >> 2U];\n    tmp &= ~(0xFFU << ((me->nvic_irq & 3U) << 3U));\n    tmp |= (nvic_prio << ((me->nvic_irq & 3U) << 3U));\n    NVIC_IP[me->nvic_irq >> 2U] = tmp;\n\n    /* enable the IRQ associated with the Task */\n    NVIC_EN[me->nvic_irq >> 5U] = (1U << (me->nvic_irq & 0x1FU));\n    SST_PORT_CRIT_EXIT();\n\n    /* store the address of NVIC_PEND address and the IRQ bit */\n    me->nvic_pend = &NVIC_PEND[me->nvic_irq >> 5U];\n    me->nvic_irq  = (1U << (me->nvic_irq & 0x1FU));\n}\n/*..........................................................................*/\nvoid SST_Task_activate(SST_Task * const me) {\n    /*! @pre the queue must have some events */\n    DBC_REQUIRE(300, me->nUsed > 0U);\n\n    /* get the event out of the queue */\n    /* NOTE: no critical section because me->tail is accessed only\n    * from this task\n    */\n    SST_Evt const *e = me->qBuf[me->tail];\n    if (me->tail == 0U) { /* need to wrap the tail? */\n        me->tail = me->end; /* wrap around */\n    }\n    else {\n        --me->tail;\n    }\n    SST_PORT_CRIT_STAT\n    SST_PORT_CRIT_ENTRY();\n    if ((--me->nUsed) > 0U) { /* some events still present in the queue? */\n        *me->nvic_pend = me->nvic_irq; /* <=== pend the associated IRQ */\n    }\n    SST_PORT_CRIT_EXIT();\n\n    /* dispatch the received event to this task */\n    (*me->dispatch)(me, e); /* NOTE: virtual call */\n    /* TBD: implement event recycling */\n}\n/*..........................................................................*/\nvoid SST_Task_setIRQ(SST_Task * const me, uint8_t irq) {\n    me->nvic_irq = irq;\n}\n\n/*..........................................................................*/\nSST_LockKey SST_Task_lock(SST_TaskPrio ceiling) {\n#if (__ARM_ARCH == 6) /* ARMv6-M? */\n    /* NOTE:\n    * ARMv6-M (Cortex-M0/M0+/M1) do NOT support the BASEPRI register\n    * and simple selective scheduler locking is not possible.\n    * Instead, on this architectures, SST scheduler lock can be\n    * implemented by temporarily raising the current task priority\n    * to the ceiling level.\n    */\n    /* TBD... */\n    (void)ceiling; /* unused param for now */\n    return 0U;\n#else  /* ARMv7-M+ */\n    /* NOTE:\n    * ARMv7-M+ support the BASEPRI register and the selective SST scheduler\n    * locking is implemented by setting BASEPRI to the ceiling level.\n    */\n    uint32_t nvic_prio = ((0xFFU >> nvic_prio_shift) + 1U - ceiling)\n                         << nvic_prio_shift;\n    SST_LockKey basepri_; /* initialized in the following asm() instruction */\n    __asm volatile (\"mrs %0,BASEPRI\" : \"=r\" (basepri_) :: );\n    if (basepri_ > nvic_prio) { /* current priority lower than the ceiling? */\n        __asm volatile (\"cpsid i\\n msr BASEPRI,%0\\n cpsie i\"\n                        :: \"r\" (nvic_prio) : );\n    }\n    return basepri_;\n#endif\n}\n/*..........................................................................*/\nvoid SST_Task_unlock(SST_LockKey lock_key) {\n#if (__ARM_ARCH == 6) /* ARMv6-M? */\n    /* TBD... */\n    (void)lock_key; /* unused param for now */\n#else  /* ARMv7-M+ */\n    /* NOTE:\n    * ARMv7-M+ support the BASEPRI register and the selective SST scheduler\n    * unlocking is implemented by restoring BASEPRI to the lock_key level.\n    */\n    __asm volatile (\"msr BASEPRI,%0\" :: \"r\" (lock_key) : );\n#endif\n}\n"
  },
  {
    "path": "sst_c/ports/arm-cm/sst_port.h",
    "content": "/*===========================================================================\n* Super-Simple Tasker (SST/C) port to ARM Cortex-M\n*\n* Copyright (C) 2005-2023 Quantum Leaps, <state-machine.com>.\n*\n* SPDX-License-Identifier: MIT\n*\n* Permission is hereby granted, free of charge, to any person obtaining a\n* copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included in\n* all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n===========================================================================*/\n#ifndef SST_PORT_H_\n#define SST_PORT_H_\n\n/* additional SST-PORT task attributes for ARM Cortex-M */\n#define SST_PORT_TASK_ATTR \\\n    uint32_t volatile *nvic_pend; \\\n    uint32_t nvic_irq;\n\n/* additional SST-PORT task operations for ARM Cortex-M */\n#define SST_PORT_TASK_OPER \\\n    void SST_Task_activate(SST_Task * const me); \\\n    void SST_Task_setIRQ(SST_Task * const me, uint8_t irq); \\\n    void SST_Task_setPrio(SST_Task * const me, SST_TaskPrio prio);\n\n/* SST-PORT critical section */\n#define SST_PORT_CRIT_STAT\n#define SST_PORT_CRIT_ENTRY() __asm volatile (\"cpsid i\")\n#define SST_PORT_CRIT_EXIT()  __asm volatile (\"cpsie i\")\n\n/* SST-PORT pend the Task after posting an event\n* NOTE: executed inside SST critical section.\n*/\n#define SST_PORT_TASK_PEND()  (*me->nvic_pend = me->nvic_irq)\n\n/* the idle SST callback for this SST port */\nvoid SST_onIdle(void);\n\n/* the SST scheduler lock key type */\ntypedef uint32_t SST_LockKey;\n\n#endif /* SST_PORT_H_ */\n"
  },
  {
    "path": "sst_c/ports/dspic/sst_port.c",
    "content": "/**\n * @file sst_port.c\n * @author ASHRAF (ashraf-masoud@elarabygroup.com)\n * @version 0.1\n * @date 2023-06-20\n */\n\n/*===========================================================================\n* Super-Simple Tasker (SST/C) port to dsPIC33ep\n*\n* Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n*\n* SPDX-License-Identifier: MIT\n*\n* Permission is hereby granted, free of charge, to any person obtaining a\n* copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included in\n* all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n===========================================================================*/\n#include \"sst.h\"     /* Super-Simple Tasker (SST/C) */\n#include \"dbc_assert.h\" /* Design By Contract (DBC) assertions */\n#include \"sst_port.h\"\n\nDBC_MODULE_NAME(\"sst_port\") /* for DBC assertions in this module */\n\n#define IFS_BASE     ((uint16_t volatile *)0x800U)  //interrupt flag status (pend)\n#define IEC_BASE     ((uint16_t volatile *)0x820U)  //interrupt enable control\n#define IPC_BASE     ((uint16_t volatile *)0x840U)  //interrupt priority control\n\nstatic void interrupt_SetPriority(uint16_t IRQn, uint8_t priority)\n{\n    //CLR\n    IPC_BASE[IRQn/4] &= ~(0X7<< ((IRQn%4)*4));\n    //SET\n    IPC_BASE[IRQn/4] |= priority << ((IRQn%4)*4);\n}\n\nstatic void interrupt_Enable(uint16_t IRQn)\n{\n    IEC_BASE[IRQn/16] |= 1 << (IRQn%16);\n}\n/*..........................................................................*/\n//critical section counter\nuint8_t g_crit_counter = 0;\n/* SST kernel facilities ---------------------------------------------------*/\nvoid SST_init(void) {\n}\n/*..........................................................................*/\nvoid SST_start(void) {\n}\n\n/* SST Task facilities -----------------------------------------------------*/\nvoid SST_Task_setPrio(SST_Task * const me, SST_TaskPrio prio) {\n\n    /*! @pre\n    * - the IRQ number must be already set\n    * - the priority must fit in the NVIC\n    */\n    DBC_REQUIRE(200,\n                (me->interrupt_num >= 0U)\n                && (prio <= 0b111 && prio > 0));\n\n    /* convert the SST direct priority (1,2,..) to NVIC priority... */\n    //no need for dspic -> 1 lowest -> 7 highest\n\n    SST_PORT_CRIT_STAT\n    SST_PORT_CRIT_ENTRY();\n    /* set the Task priority of the associated IRQ */\n    interrupt_SetPriority(me->interrupt_num, prio);\n\n    /* enable the IRQ associated with the Task */\n    interrupt_Enable(me->interrupt_num);\n    SST_PORT_CRIT_EXIT();\n\n    /* store the address of NVIC_PEND address and the IRQ bit */\n    me->interrupt_pend = &IFS_BASE[me->interrupt_num/16 ];\n    me->interrupt_num  = 1<<(me->interrupt_num%16);\n}\n/*..........................................................................*/\nvoid SST_Task_activate(SST_Task * const me) {\n    /*! @pre the queue must have some events */\n    DBC_REQUIRE(300, me->nUsed > 0U);\n\n    /* get the event out of the queue */\n    /* NOTE: no critical section because me->tail is accessed only\n    * from this task\n    */\n    SST_Evt const *e = me->qBuf[me->tail];\n    if (me->tail == 0U) { /* need to wrap the tail? */\n        me->tail = me->end; /* wrap around */\n    }\n    else {\n        --me->tail;\n    }\n    SST_PORT_CRIT_STAT\n    SST_PORT_CRIT_ENTRY();\n    if ((--me->nUsed) > 0U) { /* some events still present in the queue? */\n        *me->interrupt_pend |= me->interrupt_num; /* <=== pend the associated IRQ */\n    }\n    SST_PORT_CRIT_EXIT();\n\n    /* dispatch the received event to this task */\n    (*me->dispatch)(me, e); /* NOTE: virtual call */\n    /* TBD: implement event recycling */\n}\n/*..........................................................................*/\nvoid SST_Task_setIRQ(SST_Task * const me, uint8_t irq)\n{\n    me->interrupt_num = irq;\n}\n\n\n/*..........................................................................*/\nSST_LockKey SST_Task_lock(SST_TaskPrio ceiling) {\n    /* NOTE:\n    * dsPIC support the Interrupt Priority Level -IPL- bits in Status Reg -SR-\n    * and the selective SST scheduler locking\n    * is implemented by setting IPL bits to the ceiling level.\n    */\n    // save current Priority\n    SST_LockKey basepri_ = SRbits.IPL;\n    // Current base priority is lower than the ceiling\n    if(basepri_ < ceiling)\n    {\n        // update the Processor Priority\n        SRbits.IPL = ceiling;\n    }\n    else\n    {\n        //do nothing\n    }\n\n    return basepri_;\n}\n\n/*..........................................................................*/\nvoid SST_Task_unlock(SST_LockKey lock_key)\n{\n    SRbits.IPL = lock_key;\n}\n"
  },
  {
    "path": "sst_c/ports/dspic/sst_port.h",
    "content": "/**\n * @file sst_port.h\n * @author ASHRAF (ashrafkamel491@gmail.com)\n * @version 0.1\n * @date 2023-06-20\n */\n\n/*===========================================================================\n* Super-Simple Tasker (SST/C) port to DSPIC33ep\n*\n* Copyright (C) 2005-2023 Quantum Leaps, <state-machine.com>.\n*\n* SPDX-License-Identifier: MIT\n*\n* Permission is hereby granted, free of charge, to any person obtaining a\n* copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included in\n* all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n===========================================================================*/\n#ifndef SST_PORT_H_\n#define SST_PORT_H_\n#include \"xc.h\"\n\n/* additional SST-PORT task attributes for ARM Cortex-M */\n#define SST_PORT_TASK_ATTR \\\n    uint16_t volatile *interrupt_pend; \\\n    uint16_t interrupt_num;\n\n/* additional SST-PORT task operations for ARM Cortex-M */\n#define SST_PORT_TASK_OPER \\\n    void SST_Task_activate(SST_Task * const me); \\\n    void SST_Task_setIRQ(SST_Task * const me, uint8_t irq); \\\n    void SST_Task_setPrio(SST_Task * const me, SST_TaskPrio prio);\n\n/* SST-PORT critical section */\n#define SST_PORT_CRIT_STAT\n#define SST_PORT_CRIT_ENTRY()           \\\n    do                                  \\\n    {                                   \\\n        extern uint8_t g_crit_counter;  \\\n        INTCON2bits.GIE = 0;            \\\n        g_crit_counter++;               \\\n    } while (0);\n\n#define SST_PORT_CRIT_EXIT()            \\\n    do                                  \\\n    {                                   \\\n        extern uint8_t g_crit_counter;  \\\n        g_crit_counter--;               \\\n        if (g_crit_counter == 0)        \\\n        {                               \\\n            INTCON2bits.GIE = 1;        \\\n        }                               \\\n    } while (0);\n\n/* SST-PORT pend the Task after posting an event\n* NOTE: executed inside SST critical section.\n*/\n#define SST_PORT_TASK_PEND()  *me->interrupt_pend |= me->interrupt_num\n\n/* the idle SST callback for this SST port */\nvoid SST_onIdle(void);\n\n/* the SST scheduler lock key type */\ntypedef uint16_t SST_LockKey;\n\n#endif /* SST_PORT_H_ */\n"
  },
  {
    "path": "sst_c/src/sst.c",
    "content": "/*===========================================================================\n* Super-Simple Tasker (SST/C)\n*\n* Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n*\n* SPDX-License-Identifier: MIT\n*\n* Permission is hereby granted, free of charge, to any person obtaining a\n* copy of this software and associated documentation files (the \"Software\"),\n* to deal in the Software without restriction, including without limitation\n* the rights to use, copy, modify, merge, publish, distribute, sublicense,\n* and/or sell copies of the Software, and to permit persons to whom the\n* Software is furnished to do so, subject to the following conditions:\n*\n* The above copyright notice and this permission notice shall be included in\n* all copies or substantial portions of the Software.\n*\n* THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n* DEALINGS IN THE SOFTWARE.\n===========================================================================*/\n#include \"sst.h\"        /* Super-Simple Tasker (SST) */\n#include \"dbc_assert.h\" /* Design By Contract (DBC) assertions */\n\nDBC_MODULE_NAME(\"sst\")  /* for DBC assertions in this module */\n\n/*..........................................................................*/\nint SST_Task_run(void) {\n    SST_start();   /* port-specific start of multitasking */\n    SST_onStart(); /* application callback to config & start interrupts */\n\n    for (;;) { /* idle loop of the SST kernel */\n        SST_onIdle();\n    }\n}\n\n/*--------------------------------------------------------------------------*/\nvoid SST_Task_ctor(\n    SST_Task * const me,\n    SST_Handler init,\n    SST_Handler dispatch)\n{\n    me->init = init;\n    me->dispatch = dispatch;\n}\n/*..........................................................................*/\nvoid SST_Task_start(\n    SST_Task * const me,\n    SST_TaskPrio prio,\n    SST_Evt const **qBuf, SST_QCtr qLen,\n    SST_Evt const * const ie)\n{\n    /*! @pre\n    * - the priority must be greater than zero\n    * - the queue storage and length must be provided\n    */\n    DBC_REQUIRE(200,\n        (0U < prio)\n        && (qBuf != (SST_Evt const **)0) && (qLen > 0U));\n\n    me->qBuf  = qBuf;\n    me->end   = qLen - 1U;\n    me->head  = 0U;\n    me->tail  = 0U;\n    me->nUsed = 0U;\n\n    SST_Task_setPrio(me, prio);\n\n    /* initialize this task with the initialization event */\n    (*me->init)(me, ie); /* NOTE: virtual call */\n    /* TBD: implement event recycling */\n}\n/*..........................................................................*/\nvoid SST_Task_post(SST_Task * const me, SST_Evt const * const e) {\n    /*! @pre the queue must be sized adequately and cannot overflow */\n    DBC_REQUIRE(300, me->nUsed <= me->end);\n\n    SST_PORT_CRIT_STAT\n    SST_PORT_CRIT_ENTRY();\n    me->qBuf[me->head] = e; /* insert event into the queue */\n    if (me->head == 0U) {   /* need to wrap the head? */\n        me->head = me->end; /* wrap around */\n    }\n    else {\n        --me->head;\n    }\n    ++me->nUsed;\n    SST_PORT_TASK_PEND();\n    SST_PORT_CRIT_EXIT();\n}\n\n/*--------------------------------------------------------------------------*/\nstatic SST_TimeEvt *timeEvt_head = (SST_TimeEvt *)0;\n\n/*..........................................................................*/\nvoid SST_TimeEvt_ctor(\n    SST_TimeEvt * const me,\n    SST_Signal sig,\n    SST_Task *task)\n{\n    me->super.sig = sig;\n    me->task = task;\n    me->ctr = 0U;\n    me->interval = 0U;\n\n    /* insert time event \"me\" into the linked-list */\n    me->next = timeEvt_head;\n    timeEvt_head = me;\n}\n/*..........................................................................*/\nvoid SST_TimeEvt_arm(\n    SST_TimeEvt * const me,\n    SST_TCtr ctr,\n    SST_TCtr interval)\n{\n    SST_PORT_CRIT_STAT\n    SST_PORT_CRIT_ENTRY();\n    me->ctr = ctr;\n    me->interval = interval;\n    SST_PORT_CRIT_EXIT();\n}\n/*..........................................................................*/\nbool SST_TimeEvt_disarm(SST_TimeEvt * const me) {\n    SST_PORT_CRIT_STAT\n    SST_PORT_CRIT_ENTRY();\n    bool status = (me->ctr != 0U);\n    me->ctr = 0U;\n    me->interval = 0U;\n    SST_PORT_CRIT_EXIT();\n    return status;\n}\n/*..........................................................................*/\nvoid SST_TimeEvt_tick(void) {\n    for (SST_TimeEvt *t = timeEvt_head;\n         t != (SST_TimeEvt *)0;\n         t = t->next)\n    {\n        SST_PORT_CRIT_STAT\n        SST_PORT_CRIT_ENTRY();\n        if (t->ctr == 0U) { /* disarmed? (most frequent case) */\n            SST_PORT_CRIT_EXIT();\n        }\n        else if (t->ctr == 1U) { /* expiring? */\n            t->ctr = t->interval;\n            SST_PORT_CRIT_EXIT();\n\n            SST_Task_post(t->task, &t->super);\n        }\n        else { /* timing out */\n            --t->ctr;\n            SST_PORT_CRIT_EXIT();\n        }\n    }\n}\n"
  },
  {
    "path": "sst_cpp/README.txt",
    "content": "This directory contains the SST implementation in C++ roughly\ncorresponding to the BCC2 conformance class in the OSEK/VDX\nOperating System specification. This SST implementation is\nreferred to as \"SST/C++\".\n\n- \"basic tasks\" (non-blocking)\n- preemptive scheduling\n- multiple tasks per prioriy level\n- multiple \"activations\" per task (event queues)\n"
  },
  {
    "path": "sst_cpp/examples/README.txt",
    "content": "This directory contains examples for the preemptive SST/C++ kernel.\n"
  },
  {
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    "path": "sst_cpp/examples/blinky/blinky.cpp",
    "content": "//============================================================================\n// Super-Simple Tasker (SST/C++) Example\n//\n// Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n//\n// SPDX-License-Identifier: MIT\n//\n// Permission is hereby granted, free of charge, to any person obtaining a\n// copy of this software and associated documentation files (the \"Software\"),\n// to deal in the Software without restriction, including without limitation\n// the rights to use, copy, modify, merge, publish, distribute, sublicense,\n// and/or sell copies of the Software, and to permit persons to whom the\n// Software is furnished to do so, subject to the following conditions:\n//\n// The above copyright notice and this permission notice shall be included in\n// all copies or substantial portions of the Software.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n// DEALINGS IN THE SOFTWARE.\n//============================================================================\n#include \"sst.hpp\"           // SST framework\n#include \"bsp.hpp\"           // Board Support Package interface\n#include \"blinky.hpp\"        // application shared interface\n\nnamespace {\n\nDBC_MODULE_NAME(\"blinky\")   // for DBC assertions in this module */\n\n} // unnamed namespace\n\nnamespace App {\n\n//............................................................................\nclass Blinky : public SST::Task {\n    SST::TimeEvt m_te1;\n    SST::TimeEvt m_te2;\n\npublic:\n    Blinky(void);\n    void init(SST::Evt const * const ie) override;\n    void dispatch(SST::Evt const * const e) override;\n    static Blinky inst;\n};\n\n//............................................................................\nBlinky Blinky::inst; // the Blinky instance\nSST::Task * const AO_Blinky = &Blinky::inst; // opaque AO pointer\n\n//............................................................................\nBlinky::Blinky(void)\n  : m_te1(TIMEOUT1_SIG, this),\n    m_te2(TIMEOUT2_SIG, this)\n{}\n//............................................................................\nvoid Blinky::init(SST::Evt const * const ie) {\n    static_cast<void>(ie); // unused parameter\n\n    m_te2.arm(1U, 0U);\n}\n//............................................................................\nvoid Blinky::dispatch(SST::Evt const * const e) {\n    switch (e->sig) {\n        case TIMEOUT1_SIG: {\n            BSP::ledOff();\n            m_te2.arm(BSP::TICKS_PER_SEC*3U/4U, 0U);\n            break;\n        }\n        case TIMEOUT2_SIG: {\n            BSP::ledOn();\n            m_te1.arm(BSP::TICKS_PER_SEC/4U, 0U);\n            break;\n        }\n        default: {\n            DBC_ERROR(500); // unexpected event\n            break;\n        }\n    }\n}\n\n} // namespace App\n"
  },
  {
    "path": "sst_cpp/examples/blinky/blinky.hpp",
    "content": "//============================================================================\n// Super-Simple Tasker (SST/C++) Example\n//\n// Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n//\n// SPDX-License-Identifier: MIT\n//\n// Permission is hereby granted, free of charge, to any person obtaining a\n// copy of this software and associated documentation files (the \"Software\"),\n// to deal in the Software without restriction, including without limitation\n// the rights to use, copy, modify, merge, publish, distribute, sublicense,\n// and/or sell copies of the Software, and to permit persons to whom the\n// Software is furnished to do so, subject to the following conditions:\n//\n// The above copyright notice and this permission notice shall be included in\n// all copies or substantial portions of the Software.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n// DEALINGS IN THE SOFTWARE.\n//============================================================================\n#ifndef BLINKY_HPP_\n#define BLINKY_HPP_\n\n#include \"dbc_assert.h\" // Design By Contract (DBC) assertions\n\nnamespace App {\n\nenum Signals {\n    TIMEOUT1_SIG,\n    TIMEOUT2_SIG,\n    // ...\n    MAX_SIG  // the last signal\n};\n\nextern SST::Task * const AO_Blinky;  // opaque task pointer\n\n} // namespace App\n\n#endif // BLINKY_HPP_\n"
  },
  {
    "path": "sst_cpp/examples/blinky/bsp.hpp",
    "content": "//============================================================================\n// Super-Simple Tasker (SST/C++) Example\n//\n// Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n//\n/// SPDX-License-Identifier: MIT\n//\n// Permission is hereby granted, free of charge, to any person obtaining a\n// copy of this software and associated documentation files (the \"Software\"),\n// to deal in the Software without restriction, including without limitation\n// the rights to use, copy, modify, merge, publish, distribute, sublicense,\n// and/or sell copies of the Software, and to permit persons to whom the\n// Software is furnished to do so, subject to the following conditions:\n//\n// The above copyright notice and this permission notice shall be included in\n// all copies or substantial portions of the Software.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n// DEALINGS IN THE SOFTWARE.\n//============================================================================\n#ifndef BSP_HPP_\n#define BSP_HPP_\n\nnamespace BSP {\n\nconstexpr std::uint32_t TICKS_PER_SEC = 1000U;\n\nvoid init(void);\n\nvoid ledOn(void);\nvoid ledOff(void);\n\n} // namespace BSP\n\n#endif // BSP_HPP_\n"
  },
  {
    "path": "sst_cpp/examples/blinky/bsp_nucleo-l053r8.cpp",
    "content": "//============================================================================\n// Super-Simple Tasker (SST/C++) Example for STM32 NUCLEO-L053R8\n//\n//                    Q u a n t u m  L e a P s\n//                    ------------------------\n//                    Modern Embedded Software\n//\n// Copyright (C) 2005 Quantum Leaps, <state-machine.com>.\n//\n// SPDX-License-Identifier: MIT\n//\n// Permission is hereby granted, free of charge, to any person obtaining a\n// copy of this software and associated documentation files (the \"Software\"),\n// to deal in the Software without restriction, including without limitation\n// the rights to use, copy, modify, merge, publish, distribute, sublicense,\n// and/or sell copies of the Software, and to permit persons to whom the\n// Software is furnished to do so, subject to the following conditions:\n//\n// The above copyright notice and this permission notice shall be included in\n// all copies or substantial portions of the Software.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n// DEALINGS IN THE SOFTWARE.\n//============================================================================\n#include \"sst.hpp\"           // SST framework\n#include \"bsp.hpp\"           // Board Support Package interface\n#include \"blinky.hpp\"        // application shared interface\n\n#include \"stm32l0xx.h\"  // CMSIS-compliant header file for the MCU used\n// add other drivers if necessary...\n\n// Local-scope defines -------------------------------------------------------\nnamespace {\n\n//DBC_MODULE_NAME(\"bsp_nucleo-l053r8\") // for DBC assertions in this module\n\n} // unnamed workspace\n\n// test pins on GPIO PA\n#define LED_PIN  5U\n\n// ISRs used in the application ==============================================\nextern \"C\" {\n\nvoid SysTick_Handler(void);  // prototype\nvoid SysTick_Handler(void) { // system clock tick ISR\n    SST::TimeEvt::tick();\n}\n\n// Assertion handler =========================================================\nvoid DBC_fault_handler(char const * const module, int const label) {\n    //\n    // NOTE: add here your application-specific error handling\n    //\n    (void)module;\n    (void)label;\n\n    // set PRIMASK to disable interrupts and stop SST right here\n    __asm volatile (\"cpsid i\");\n\n#ifndef NDEBUG\n    for (;;) { // keep blinking LED2\n        BSP::ledOn();  // turn LED2 on\n        uint32_t volatile ctr;\n        for (ctr = 10000U; ctr > 0U; --ctr) {\n        }\n        BSP::ledOff(); // turn LED2 off\n        for (ctr = 10000U; ctr > 0U; --ctr) {\n        }\n    }\n#endif\n    NVIC_SystemReset();\n}\n//............................................................................\nvoid assert_failed(char const * const module, int const label);// prototype\nvoid assert_failed(char const * const module, int const label) {\n    DBC_fault_handler(module, label);\n}\n\n// SST task activations ======================================================\n// preprocessor switch to choose between regular and reserved IRQs\n#define REGULAR_IRQS\n\n#ifdef REGULAR_IRQS\n// repurpose regular IRQs for SST Tasks\n// prototypes\nvoid PVD_IRQHandler(void);\n\nvoid PVD_IRQHandler(void)  { App::AO_Blinky->activate();  }\n\n#else // use reserved IRQs for SST Tasks\n// prototypes\nvoid Reserved14_IRQHandler(void); // prototype\n// use reserved IRQs for SST Tasks\nvoid Reserved14_IRQHandler(void) { App::AO_Blinky->activate();  }\n#endif\n\n} // extern \"C\"\n\nnamespace BSP {\n\n// BSP functions =============================================================\nvoid init(void) {\n    // Configure the MPU to prevent NULL-pointer dereferencing\n    // see: www.state-machine.com/null-pointer-protection-with-arm-cortex-m-mpu\n    //\n    MPU->RBAR = 0x0U                          // base address (NULL)\n                | MPU_RBAR_VALID_Msk          // valid region\n                | (MPU_RBAR_REGION_Msk & 7U); // region #7\n    MPU->RASR = (7U << MPU_RASR_SIZE_Pos)     // 2^(7+1) region\n                | (0x0U << MPU_RASR_AP_Pos)   // no-access region\n                | MPU_RASR_ENABLE_Msk;        // region enable\n\n    MPU->CTRL = MPU_CTRL_PRIVDEFENA_Msk       // enable background region\n                | MPU_CTRL_ENABLE_Msk;        // enable the MPU\n    __ISB();\n    __DSB();\n\n    // assign IRQs to tasks. NOTE: critical for SST...\n#ifdef REGULAR_IRQS\n    // repurpose regular IRQs for SST Tasks\n    App::AO_Blinky->setIRQ (PVD_IRQn);\n#else\n    // use reserved IRQs for SST Tasks\n    App::AO_Blinky->setIRQ (14U);\n#endif\n\n    // enable GPIO port PA clock\n    RCC->IOPENR |= (1U << 0U);\n\n    // set all used GPIOA pins as push-pull output, no pull-up, pull-down\n    GPIOA->MODER  &= ~(3U << 2U*LED_PIN);\n    GPIOA->MODER  |=  (1U << 2U*LED_PIN);\n    GPIOA->OTYPER &= ~(1U <<    LED_PIN);\n    GPIOA->PUPDR  &= ~(3U << 2U*LED_PIN);\n}\n//............................................................................\nvoid ledOn(void)  { GPIOA->BSRR = (1U << LED_PIN);         }\nvoid ledOff(void) { GPIOA->BSRR = (1U << (LED_PIN + 16U)); }\n\n} // namespace BSP\n\n// SST callbacks =============================================================\nnamespace SST {\n\nvoid onStart(void) {\n    SystemCoreClockUpdate();\n\n    // set up the SysTick timer to fire at BSP::TICKS_PER_SEC rate\n    SysTick_Config((SystemCoreClock / BSP::TICKS_PER_SEC) + 1U);\n\n    // set priorities of ISRs used in the system\n    NVIC_SetPriority(SysTick_IRQn, 0U);\n    // ...\n}\n//............................................................................\nvoid onIdle(void) {\n#ifdef NDEBUG\n    // Put the CPU and peripherals to the low-power mode.\n    // you might need to customize the clock management for your application,\n    // see the datasheet for your particular Cortex-M MCU.\n    //\n    __WFI(); // Wait-For-Interrupt\n#endif\n}\n\n} // namespace SST\n\n"
  },
  {
    "path": "sst_cpp/examples/blinky/gnu/nucleo-l053r8.mak",
    "content": "##############################################################################\n# Makefile for Super-Simple Tasker (SST/C++) on NUCLEO-L053R8, GNU-ARM\n# Last Updated for Version: 2.0.0\n# Date of the Last Update:  2023-01-22\n#\n#                    Q u a n t u m  L e a P s\n#                    ------------------------\n#                    Modern Embedded Software\n#\n# Copyright (C) 2005 Quantum Leaps, LLC. All rights reserved.\n#\n# SPDX-License-Identifier: MIT\n#\n# Permission is hereby granted, free of charge, to any person obtaining a copy\n# of this software and associated documentation files (the \"Software\"), to\n# deal in the Software without restriction, including without limitation the\n# rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n# sell copies of the Software, and to permit persons to whom the Software is\n# furnished to do so, subject to the following conditions:\n#\n# The above copyright notice and this permission notice shall be included in\n# all copies or substantial portions of the Software.\n#\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS\n# IN THE SOFTWARE.\n##############################################################################\n# examples of invoking this Makefile:\n# make -f nucleo-l053r8.mak\n# make -f nucleo-l053r8.mak clean\n#\n# NOTE:\n# To use this Makefile on Windows, you will need the GNU make utility, which\n# is included in the QTools collection for Windows, see:\n#    https://github.com/QuantumLeaps/qtools\n#\n\n#-----------------------------------------------------------------------------\n# project and target names\n#\nPROJECT := blinky\nTARGET  := nucleo-l053r8\n\n#-----------------------------------------------------------------------------\n# project directories\n#\nSST_DIR      := ../../..\nSST_PORT_DIR := $(SST_DIR)/ports/arm-cm\nCMSIS_DIR    := ../../../../3rd_party/CMSIS\nTARGET_DIR   := ../../../../3rd_party/$(TARGET)\n\n# list of all source directories used by this project\nVPATH = .. \\\n\t$(SST_DIR)/src \\\n\t$(SST_PORT_DIR) \\\n\t$(TARGET_DIR) \\\n\t$(TARGET_DIR)/gnu \\\n\n# list of all include directories needed by this project\nINCLUDES  = -I. \\\n\t-I$(SST_DIR)/../include \\\n\t-I$(SST_PORT_DIR) \\\n\t-I$(CMSIS_DIR)/Include \\\n\t-I$(TARGET_DIR)\n\n#-----------------------------------------------------------------------------\n# project files\n#\n\n# assembler source files\nASM_SRCS :=\n\n# C source files\nC_SRCS := \\\n\tsystem_stm32l0xx.c \\\n\tstartup_stm32l053xx.c\n\n# C++ source files\nCPP_SRCS := \\\n\tsst.cpp \\\n\tsst_port.cpp \\\n\tmain.cpp \\\n\tblinky.cpp \\\n\tbsp_nucleo-l053r8.cpp\n\nLD_SCRIPT  := $(TARGET_DIR)/gnu/$(TARGET).ld\n\nOUTPUT    := $(PROJECT)\n\nLIB_DIRS  :=\nLIBS      :=\n\n# defines\nDEFINES   :=\n\n# ARM CPU, ARCH, FPU, and Float-ABI types...\n# ARM_CPU:   [cortex-m0 | cortex-m0plus | cortex-m1 | cortex-m3 | cortex-m4]\n# ARM_FPU:   [ | vfp]\n# FLOAT_ABI: [ | soft | softfp | hard]\n#\nARM_CPU   := -mcpu=cortex-m0plus\nARM_FPU   :=\nFLOAT_ABI :=\n\n#-----------------------------------------------------------------------------\n# GNU-ARM toolset (NOTE: You need to adjust to your machine)\n# see https://developer.arm.com/open-source/gnu-toolchain/gnu-rm/downloads\n#\nifeq ($(GNU_ARM),)\nGNU_ARM := $(QTOOLS)/gnu_arm-none-eabi\nendif\n\n# make sure that the GNU-ARM toolset exists...\nifeq (\"$(wildcard $(GNU_ARM))\",\"\")\n$(error GNU_ARM toolset not found. Please adjust the Makefile)\nendif\n\nCC    := $(GNU_ARM)/bin/arm-none-eabi-gcc\nCPP   := $(GNU_ARM)/bin/arm-none-eabi-g++\nAS    := $(GNU_ARM)/bin/arm-none-eabi-as\nLINK  := $(GNU_ARM)/bin/arm-none-eabi-g++\nBIN   := $(GNU_ARM)/bin/arm-none-eabi-objcopy\n\n##############################################################################\n# Typically you should not need to change anything below this line\n\n# basic utilities (included in QTools for Windows), see:\n#     https://www.state-machine.com/qtools\n\nMKDIR := mkdir\nRM    := rm\n\n#-----------------------------------------------------------------------------\n# build options\n#\n\n# combine all the soruces...\nC_SRCS += $(QP_SRCS)\nASM_SRCS += $(QP_ASMS)\n\nBIN_DIR := build_$(TARGET)\n\nASFLAGS = -g $(ARM_CPU) $(ARM_FPU) $(ASM_CPU) $(ASM_FPU)\n\nCFLAGS = -c -g $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -std=c99 -mthumb -Wall \\\n\t-ffunction-sections -fdata-sections \\\n\t-O $(INCLUDES) $(DEFINES)\n\nCPPFLAGS = -c -g $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -std=c++11 -mthumb -Wall \\\n\t-ffunction-sections -fdata-sections -fno-rtti -fno-exceptions \\\n\t-O $(INCLUDES) $(DEFINES)\n\nLINKFLAGS = -T$(LD_SCRIPT) $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -mthumb \\\n\t-specs=nosys.specs -specs=nano.specs \\\n\t-Wl,-Map,$(BIN_DIR)/$(OUTPUT).map,--cref,--gc-sections $(LIB_DIRS)\n\nASM_OBJS     := $(patsubst %.s,%.o,  $(notdir $(ASM_SRCS)))\nC_OBJS       := $(patsubst %.c,%.o,  $(notdir $(C_SRCS)))\nCPP_OBJS     := $(patsubst %.cpp,%.o,$(notdir $(CPP_SRCS)))\n\nTARGET_BIN   := $(BIN_DIR)/$(OUTPUT).bin\nTARGET_ELF   := $(BIN_DIR)/$(OUTPUT).elf\nASM_OBJS_EXT := $(addprefix $(BIN_DIR)/, $(ASM_OBJS))\nC_OBJS_EXT   := $(addprefix $(BIN_DIR)/, $(C_OBJS))\nC_DEPS_EXT   := $(patsubst %.o, %.d, $(C_OBJS_EXT))\nCPP_OBJS_EXT := $(addprefix $(BIN_DIR)/, $(CPP_OBJS))\nCPP_DEPS_EXT := $(patsubst %.o, %.d, $(CPP_OBJS_EXT))\n\n# create $(BIN_DIR) if it does not exist\nifeq (\"$(wildcard $(BIN_DIR))\",\"\")\n$(shell $(MKDIR) $(BIN_DIR))\nendif\n\n#-----------------------------------------------------------------------------\n# rules\n#\n\n.PHONY : run norun flash\n\nifeq ($(MAKECMDGOALS),norun)\nall : $(TARGET_BIN)\nnorun : all\nelse\nall : $(TARGET_BIN) run\nendif\n\n$(TARGET_BIN): $(TARGET_ELF)\n\t$(BIN) -O binary $< $@\n\n$(TARGET_ELF) : $(ASM_OBJS_EXT) $(C_OBJS_EXT) $(CPP_OBJS_EXT)\n\t$(LINK) $(LINKFLAGS) -o $@ $^ $(LIBS)\n\n$(BIN_DIR)/%.d : %.c\n\t$(CC) -MM -MT $(@:.d=.o) $(CFLAGS) $< > $@\n\n$(BIN_DIR)/%.d : %.cpp\n\t$(CPP) -MM -MT $(@:.d=.o) $(CPPFLAGS) $< > $@\n\n$(BIN_DIR)/%.o : %.s\n\t$(AS) $(ASFLAGS) $< -o $@\n\n$(BIN_DIR)/%.o : %.c\n\t$(CC) $(CFLAGS) $< -o $@\n\n$(BIN_DIR)/%.o : %.cpp\n\t$(CPP) $(CPPFLAGS) $< -o $@\n\n.PHONY : clean show\n\n# include dependency files only if our goal depends on their existence\nifneq ($(MAKECMDGOALS),clean)\n  ifneq ($(MAKECMDGOALS),show)\n-include $(C_DEPS_EXT) $(CPP_DEPS_EXT)\n  endif\nendif\n\n\nclean :\n\t-$(RM) $(BIN_DIR)/*.o \\\n\t$(BIN_DIR)/*.d \\\n\t$(BIN_DIR)/*.bin \\\n\t$(BIN_DIR)/*.elf \\\n\t$(BIN_DIR)/*.map\n\t\nshow:\n\t@echo PROJECT = $(PROJECT)\n\t@echo CONF = $(CONF)\n\t@echo DEFINES = $(DEFINES)\n\t@echo ASM_FPU = $(ASM_FPU)\n\t@echo ASM_SRCS = $(ASM_SRCS)\n\t@echo C_SRCS = $(C_SRCS)\n\t@echo CPP_SRCS = $(CPP_SRCS)\n\t@echo ASM_OBJS_EXT = $(ASM_OBJS_EXT)\n\t@echo C_OBJS_EXT = $(C_OBJS_EXT)\n\t@echo C_DEPS_EXT = $(C_DEPS_EXT)\n\t@echo CPP_DEPS_EXT = $(CPP_DEPS_EXT)\n\t@echo TARGET_ELF = $(TARGET_ELF)\n"
  },
  {
    "path": "sst_cpp/examples/blinky/iar/nucleo-l053r8.ewd",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<project>\n    <fileVersion>3</fileVersion>\n    <configuration>\n        <name>Debug</name>\n        <toolchain>\n            <name>ARM</name>\n        </toolchain>\n        <debug>1</debug>\n        <settings>\n            <name>C-SPY</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>32</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CInput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CEndian</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCVariant</name>\n                    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        <state>0</state>\n                </option>\n                <option>\n                    <name>CExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCDDFArgumentProducer</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCDownloadSuppressDownload</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCDownloadVerifyAll</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProductVersion</name>\n                    <state>9.10.2.39304</state>\n                </option>\n                <option>\n                    <name>OCDynDriverList</name>\n                    <state>STLINK_ID</state>\n                </option>\n                <option>\n                    <name>OCLastSavedByProductVersion</name>\n                    <state>9.32.1.54977</state>\n                </option>\n                <option>\n                    <name>UseFlashLoader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CLowLevel</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCBE8Slave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacFile2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CDevice</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>FlashLoadersV3</name>\n                    <state>$TOOLKIT_DIR$/config/flashloader/ST/FlashSTM32L0xxx8.board</state>\n                </option>\n                <option>\n                    <name>OCImagesSuppressCheck1</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesPath1</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCImagesSuppressCheck2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesPath2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCImagesSuppressCheck3</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesPath3</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OverrideDefFlashBoard</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesOffset1</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCImagesOffset2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCImagesOffset3</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCImagesUse1</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesUse2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesUse3</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCDeviceConfigMacroFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCDebuggerExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCAllMTBOptions</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCMulticoreNrOfCores</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCMulticoreWorkspace</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCMulticoreSlaveProject</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCMulticoreSlaveConfiguration</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCDownloadExtraImage</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCAttachSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MassEraseBeforeFlashing</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCMulticoreNrOfCoresSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCMulticoreAMPConfigType</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCMulticoreSessionFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCTpiuBaseOption</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>ARMSIM_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>1</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCSimDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCSimEnablePSP</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCSimPspOverrideConfig</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCSimPspConfigFile</name>\n                    <state></state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CADI_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CCadiMemory</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>Fast Model</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCADILogFileCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCADILogFileEditB</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CMSISDAP_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>4</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCIarProbeScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CMSISDAPResetList</name>\n                    <version>1</version>\n                    <state>10</state>\n                </option>\n                <option>\n                    <name>CMSISDAPHWResetDuration</name>\n                    <state>300</state>\n                </option>\n                <option>\n                    <name>CMSISDAPHWResetDelay</name>\n                    <state>200</state>\n                </option>\n                <option>\n                    <name>CMSISDAPDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CMSISDAPInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CMSISDAPInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiTargetEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPJtagSpeedList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPRestoreBreakpointsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPUpdateBreakpointsEdit</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>RDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchUndef</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchData</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchPrefetch</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchMMERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchNOCPERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchCHKERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSTATERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchBUSERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchINTERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSFERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchHARDERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiCPUEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiCPUNumber</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeCfgOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeConfig</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CMSISDAPProbeConfigRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPSelectedCPUBehaviour</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ICpuName</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCJetEmuParams</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCCMSISDAPUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCCMSISDAPUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>GDBSERVER_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>TCPIP</name>\n                    <state>aaa.bbb.ccc.ddd</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCJTagBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJTagDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJTagUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>IJET_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>9</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCIarProbeScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetResetList</name>\n                    <version>1</version>\n                    <state>10</state>\n                </option>\n                <option>\n                    <name>IjetHWResetDuration</name>\n                    <state>300</state>\n                </option>\n                <option>\n                    <name>IjetHWResetDelay</name>\n                    <state>200</state>\n                </option>\n                <option>\n                    <name>IjetPowerFromProbe</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetPowerRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>IjetInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiTargetEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetScanChainNonARMDevices</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetIRLength</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetJtagSpeedList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetProtocolRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetSwoPin</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IjetSwoPrescalerList</name>\n                    <version>1</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetRestoreBreakpointsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetUpdateBreakpointsEdit</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>RDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchUndef</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchData</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchPrefetch</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchMMERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchNOCPERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchCHKERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSTATERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchBUSERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchINTERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSFERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchHARDERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeCfgOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeConfig</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IjetProbeConfigRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiCPUEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiCPUNumber</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetSelectedCPUBehaviour</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ICpuName</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCJetEmuParams</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetPreferETB</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetTraceSettingsList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetTraceSizeList</name>\n                    <version>0</version>\n                    <state>4</state>\n                </option>\n                <option>\n                    <name>FlashBoardPathSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCIjetUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCIjetUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL3S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL3S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL3S</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>JLINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>16</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>JLinkSpeed</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCJLinkDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCJLinkHWResetDelay</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>JLinkInitialSpeed</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCDoJlinkMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCScanChainNonARMDevices</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkIRLength</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkCommRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkTCPIP</name>\n                    <state>aaa.bbb.ccc.ddd</state>\n                </option>\n                <option>\n                    <name>CCJLinkSpeedRadioV2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCUSBDevice</name>\n                    <version>1</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCRDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchUndef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchData</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchPrefetch</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCJLinkInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJLinkResetList</name>\n                    <version>6</version>\n                    <state>5</state>\n                </option>\n                <option>\n                    <name>CCJLinkInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJLinkUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCTcpIpAlt</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkTcpIpSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSwoClockAuto</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSwoClockEdit</name>\n                    <state>2000</state>\n                </option>\n                <option>\n                    <name>OCJLinkTraceSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkTraceSourceDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkDeviceName</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>LMIFTDI_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>3</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>LmiftdiSpeed</name>\n                    <state>500</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCLmiFtdiInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCLmiFtdiInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCLmiftdiUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiResetList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>NULINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>PEMICRO_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>3</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJPEMicroShowSettings</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>STLINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>8</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSTLinkInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSTLinkInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkResetList</name>\n                    <version>3</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSwoClockAuto</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSwoClockEdit</name>\n                    <state>2000</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCSTLinkDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSTLinkUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkJtagSpeedList</name>\n                    <version>2</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkDAPNumber</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSTLinkDebugAccessPortRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUseServerSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkProbeList</name>\n                    <version>1</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkTargetVccEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSTLinkTargetVoltage</name>\n                    <state>3.3</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>THIRDPARTY_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CThirdPartyDriverDll</name>\n                    <state>###Uninitialized###</state>\n                </option>\n                <option>\n                    <name>CThirdPartyLogFileCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CThirdPartyLogFileEditB</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>TIFET_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>1</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCMSPFetResetList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetInterfaceRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetTargetVccTypeDefault</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetTargetVoltage</name>\n                    <state>###Uninitialized###</state>\n                </option>\n                <option>\n                    <name>CCMSPFetVCCDefault</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCMSPFetTargetSettlingtime</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetRadioJtagSpeedType</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCMSPFetConnection</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetUsbComPort</name>\n                    <state>Automatic</state>\n                </option>\n                <option>\n                    <name>CCMSPFetAllowAccessToBSL</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCMSPFetRadioEraseFlash</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>XDS100_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>9</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>TIPackageOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TIPackage</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>BoardFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCXds100BreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100DoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100UpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchUndef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchData</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchPrefetch</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCXds100SwoClockAuto</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100SwoClockEdit</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCXds100HWResetDelay</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100ResetList</name>\n                    <version>1</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100UsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCXds100UsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100JtagSpeedList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100InterfaceRadio</name>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCXds100InterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100ProbeList</name>\n                    <version>0</version>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>CCXds100SWOPortRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100SWOPort</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCXDSTargetVccEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXDSTargetVoltage</name>\n                    <state>###Uninitialized###</state>\n                </option>\n                <option>\n                    <name>OCXDSDigitalStatesConfigFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCSelectedCoreName</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <debuggerPlugins>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\CMX\\CmxArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\CMX\\CmxTinyArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\embOS\\embOSPlugin.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\FreeRtos\\FreeRtosArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\Mbed\\MbedArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\Mbed\\MbedArmPlugin2.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\OpenRTOS\\OpenRTOSPlugin.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\SafeRTOS\\SafeRTOSPlugin.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\SMX\\smxAwareIarArm9.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\SMX\\smxAwareIarArm9BE.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\ThreadX\\ThreadXArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\uCOS-II\\uCOS-II-286-KA-CSpy.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\uCOS-II\\uCOS-II-KA-CSpy.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\uCOS-III\\uCOS-III-KA-CSpy.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$EW_DIR$\\common\\plugins\\Orti\\Orti.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$EW_DIR$\\common\\plugins\\TargetAccessServer\\TargetAccessServer.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$EW_DIR$\\common\\plugins\\uCProbe\\uCProbePlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n        </debuggerPlugins>\n    </configuration>\n</project>\n"
  },
  {
    "path": "sst_cpp/examples/blinky/iar/nucleo-l053r8.ewp",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<project>\n    <fileVersion>3</fileVersion>\n    <configuration>\n        <name>Debug</name>\n        <toolchain>\n            <name>ARM</name>\n        </toolchain>\n        <debug>1</debug>\n        <settings>\n            <name>General</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <version>35</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>BrowseInfoPath</name>\n                    <state>build_nucleo-l053r8</state>\n                </option>\n                <option>\n                    <name>ExePath</name>\n                    <state>build_nucleo-l053r8</state>\n                </option>\n                <option>\n                    <name>ObjPath</name>\n                    <state>build_nucleo-l053r8</state>\n                </option>\n                <option>\n                    <name>ListPath</name>\n                    <state>build_nucleo-l053r8</state>\n                </option>\n                <option>\n                    <name>GEndianMode</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>Input description</name>\n                    <state>No specifier n, no float nor long long, no scan set, no assignment suppressing, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>Output description</name>\n                    <state>No specifier a, A, no specifier n, no float nor long long, no flags, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>GOutputBinary</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGCoreOrChip</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelect</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelectSlave</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RTDescription</name>\n                    <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\n                </option>\n                <option>\n                    <name>OGProductVersion</name>\n                    <state>5.11.0.50579</state>\n                </option>\n                <option>\n                    <name>OGLastSavedByProductVersion</name>\n                    <state>9.32.1.54977</state>\n                </option>\n                <option>\n                    <name>OGChipSelectEditMenu</name>\n                    <state>STM32L053R8\tST STM32L053R8</state>\n                </option>\n                <option>\n                    <name>GenLowLevelInterface</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GEndianModeBE</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OGBufferedTerminalOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GenStdoutInterface</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RTConfigPath2</name>\n                    <state>$TOOLKIT_DIR$\\inc\\c\\DLib_Config_Normal.h</state>\n                </option>\n                <option>\n                    <name>GBECoreSlave</name>\n                    <version>32</version>\n                    <state>35</state>\n                </option>\n                <option>\n                    <name>OGUseCmsis</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGUseCmsisDspLib</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibThreads</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CoreVariant</name>\n                    <version>32</version>\n                    <state>35</state>\n                </option>\n                <option>\n                    <name>GFPUDeviceSlave</name>\n                    <state>STM32L053R8\tST STM32L053R8</state>\n                </option>\n                <option>\n                    <name>FPU2</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>NrRegs</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>NEON</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GFPUCoreSlave2</name>\n                    <version>32</version>\n                    <state>35</state>\n                </option>\n                <option>\n                    <name>OGCMSISPackSelectDevice</name>\n                </option>\n                <option>\n                    <name>OgLibHeap</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGLibAdditionalLocale</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGPrintfVariant</name>\n                    <version>0</version>\n                    <state>4</state>\n                </option>\n                <option>\n                    <name>OGPrintfMultibyteSupport</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGScanfVariant</name>\n                    <version>0</version>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>OGScanfMultibyteSupport</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GenLocaleTags</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>GenLocaleDisplayOnly</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DSPExtension</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TrustZone</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TrustZoneModes</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGAarch64Abi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OG_32_64Device</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>BuildFilesPath</name>\n                    <state>Debug</state>\n                </option>\n                <option>\n                    <name>PointerAuthentication</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>FPU64</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>ICCARM</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>37</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CCOptimizationNoSizeConstraints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCDefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCPreprocFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPreprocComments</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPreprocLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCMnemonics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCMessages</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListAssFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListAssSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEnableRemarks</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCDiagSuppress</name>\n                    <state>Pa050</state>\n                </option>\n                <option>\n                    <name>CCDiagRemark</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagWarning</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagError</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCObjPrefix</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCAllowList</name>\n                    <version>1</version>\n                    <state>10010100</state>\n                </option>\n                <option>\n                    <name>CCDebugInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IEndianMode</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IExtraOptionsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCLangConformance</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSignedPlainChar</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCRequirePrototypes</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCDiagWarnAreErr</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCompilerRuntimeInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OutputFile</name>\n                    <state>$FILE_BNAME$.o</state>\n                </option>\n                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<file>\n            <name>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\nucleo-l053r8\\iar\\startup_stm32l053xx.s</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\nucleo-l053r8\\stm32l053xx.h</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\nucleo-l053r8\\system_stm32l0xx.c</name>\n        </file>\n    </group>\n    <group>\n        <name>sst</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\src\\sst.cpp</name>\n        </file>\n    </group>\n    <group>\n        <name>sst_port</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\ports\\arm-cm\\sst_port.cpp</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\ports\\arm-cm\\sst_port.hpp</name>\n        </file>\n    </group>\n</project>\n"
  },
  {
    "path": "sst_cpp/examples/blinky/iar/nucleo-l053r8.eww",
    "content": "<?xml version=\"1.0\" encoding=\"iso-8859-1\"?>\n\n<workspace>\n  <project>\n    <path>$WS_DIR$\\nucleo-l053r8.ewp</path>\n  </project>\n  <batchBuild/>\n</workspace>\n\n\n"
  },
  {
    "path": "sst_cpp/examples/blinky/main.cpp",
    "content": "//============================================================================\n// Super-Simple Tasker (SST/C++) Example\n//\n// Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n//\n// SPDX-License-Identifier: MIT\n//\n// Permission is hereby granted, free of charge, to any person obtaining a\n// copy of this software and associated documentation files (the \"Software\"),\n// to deal in the Software without restriction, including without limitation\n// the rights to use, copy, modify, merge, publish, distribute, sublicense,\n// and/or sell copies of the Software, and to permit persons to whom the\n// Software is furnished to do so, subject to the following conditions:\n//\n// The above copyright notice and this permission notice shall be included in\n// all copies or substantial portions of the Software.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n// DEALINGS IN THE SOFTWARE.\n//============================================================================\n#include \"sst.hpp\"           // SST framework\n#include \"bsp.hpp\"           // Board Support Package interface\n#include \"blinky.hpp\"        // application shared interface\n\n//............................................................................\nint main() {\n    SST::init(); // initialize the SST kernel\n    BSP::init(); // initialize the Board Support Package\n\n    // instantiate and start all SST tasks...\n    static SST::Evt const *blinkyQSto[10]; // Event queue storage\n    App::AO_Blinky->start(\n        1U,           // SST-priority\n        blinkyQSto,   // storage for the AO's queue\n        ARRAY_NELEM(blinkyQSto), // queue length\n        nullptr);     // initialization event (not used)\n\n    return SST::Task::run(); // run the SST tasks\n    // NOTE: in embedded systems SST::Task::run() should not return\n}\n\n"
  },
  {
    "path": "sst_cpp/examples/blinky_button/armclang/ek-tm4c123gxl.uvoptx",
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  {
    "path": "sst_cpp/examples/blinky_button/blinky1.cpp",
    "content": "//============================================================================\n// Super-Simple Tasker (SST/C++) Example\n//\n// Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n//\n// SPDX-License-Identifier: MIT\n//\n// Permission is hereby granted, free of charge, to any person obtaining a\n// copy of this software and associated documentation files (the \"Software\"),\n// to deal in the Software without restriction, including without limitation\n// the rights to use, copy, modify, merge, publish, distribute, sublicense,\n// and/or sell copies of the Software, and to permit persons to whom the\n// Software is furnished to do so, subject to the following conditions:\n//\n// The above copyright notice and this permission notice shall be included in\n// all copies or substantial portions of the Software.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n// DEALINGS IN THE SOFTWARE.\n//============================================================================\n#include \"sst.hpp\"           // SST framework\n#include \"bsp.hpp\"           // Board Support Package interface\n#include \"blinky_button.hpp\" // application shared interface\n\nnamespace {\n\nDBC_MODULE_NAME(\"blinky1\")   // for DBC assertions in this module */\n\n} // unnamed namespace\n\nnamespace App {\n\n//............................................................................\nclass Blinky1 : public SST::Task {\n    SST::TimeEvt m_te;\n    std::uint16_t m_toggles;\n\npublic:\n    Blinky1(void);\n    void init(SST::Evt const * const ie) override;\n    void dispatch(SST::Evt const * const e) override;\n    static Blinky1 inst;\n};\n\n//............................................................................\nBlinky1 Blinky1::inst; // the Blinky1 instance\nSST::Task * const AO_Blinky1 = &Blinky1::inst; // opaque AO pointer\n\n//............................................................................\nBlinky1::Blinky1(void)\n  : m_te(TIMEOUT_SIG, this)\n{}\n//............................................................................\nvoid Blinky1::init(SST::Evt const * const ie) {\n    /* the initial event must be provided and must be WORKLOAD_SIG */\n    DBC_REQUIRE(300,\n        (ie != nullptr) && (ie->sig == BLINKY_WORK_SIG));\n\n    m_te.arm(\n        SST::evt_downcast<BlinkyWorkEvt>(ie)->ticks,\n        SST::evt_downcast<BlinkyWorkEvt>(ie)->ticks);\n    m_toggles = SST::evt_downcast<BlinkyWorkEvt>(ie)->toggles;\n}\n//............................................................................\nvoid Blinky1::dispatch(SST::Evt const * const e) {\n    switch (e->sig) {\n        case TIMEOUT_SIG: {\n            for (std::uint16_t i = m_toggles; i > 0U; --i) {\n                // just to exercise SST task scheduler lock...\n                SST::LockKey key = lock(3U);\n                BSP::d5on();\n                BSP::d5off();\n                unlock(key);\n            }\n            break;\n        }\n        case BLINKY_WORK_SIG: {\n            BSP::d5on();\n            m_te.arm(\n                SST::evt_downcast<BlinkyWorkEvt>(e)->ticks,\n                SST::evt_downcast<BlinkyWorkEvt>(e)->ticks);\n            m_toggles = SST::evt_downcast<BlinkyWorkEvt>(e)->toggles;\n            BSP::d5off();\n            break;\n        }\n        default: {\n            DBC_ERROR(500); // unexpected event\n            break;\n        }\n    }\n}\n\n} // namespace App\n"
  },
  {
    "path": "sst_cpp/examples/blinky_button/blinky3.cpp",
    "content": "//============================================================================\n// Super-Simple Tasker (SST/C++) Example\n//\n// Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n//\n// SPDX-License-Identifier: MIT\n//\n// Permission is hereby granted, free of charge, to any person obtaining a\n// copy of this software and associated documentation files (the \"Software\"),\n// to deal in the Software without restriction, including without limitation\n// the rights to use, copy, modify, merge, publish, distribute, sublicense,\n// and/or sell copies of the Software, and to permit persons to whom the\n// Software is furnished to do so, subject to the following conditions:\n//\n// The above copyright notice and this permission notice shall be included in\n// all copies or substantial portions of the Software.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n// DEALINGS IN THE SOFTWARE.\n//============================================================================\n#include \"sst.hpp\"           // SST framework\n#include \"bsp.hpp\"           // Board Support Package interface\n#include \"blinky_button.hpp\" // application shared interface\n\nnamespace {\n\nDBC_MODULE_NAME(\"blinky3\")   // for DBC assertions in this module\n\n} // unnamed namespace\n\nnamespace App {\n\n//............................................................................\nclass Blinky3 : public SST::Task {\n    SST::TimeEvt m_te;\n    std::uint16_t m_toggles;\n\npublic:\n    Blinky3(void);\n    void init(SST::Evt const * const ie) override;\n    void dispatch(SST::Evt const * const e) override;\n    static Blinky3 inst;\n};\n\n//............................................................................\nBlinky3 Blinky3::inst; // the Blinky3 instance\nSST::Task * const AO_Blinky3 = &Blinky3::inst; // opaque AO pointer\n\n//............................................................................\nBlinky3::Blinky3(void)\n  : m_te(TIMEOUT_SIG, this)\n{}\n//............................................................................\nvoid Blinky3::init(SST::Evt const * const ie) {\n    // the initial event must be provided and must be WORKLOAD_SIG\n    DBC_REQUIRE(300,\n        (ie != nullptr) && (ie->sig == BLINKY_WORK_SIG));\n\n    m_te.arm(\n        SST::evt_downcast<BlinkyWorkEvt>(ie)->ticks,\n        SST::evt_downcast<BlinkyWorkEvt>(ie)->ticks);\n    m_toggles = SST::evt_downcast<BlinkyWorkEvt>(ie)->toggles;\n}\n//............................................................................\nvoid Blinky3::dispatch(SST::Evt const * const e) {\n    switch (e->sig) {\n        case TIMEOUT_SIG: {\n            for (std::uint16_t i = m_toggles; i > 0U; --i) {\n                BSP::d2on();\n                BSP::d2off();\n            }\n            break;\n        }\n        case BLINKY_WORK_SIG: {\n            BSP::d2on();\n            m_te.arm(\n                SST::evt_downcast<BlinkyWorkEvt>(e)->ticks,\n                SST::evt_downcast<BlinkyWorkEvt>(e)->ticks);\n            m_toggles = SST::evt_downcast<BlinkyWorkEvt>(e)->toggles;\n            BSP::d2off();\n            break;\n        }\n        default: {\n            DBC_ERROR(500); // unexpected event\n            break;\n        }\n    }\n}\n\n} // namespace App\n"
  },
  {
    "path": "sst_cpp/examples/blinky_button/blinky_button.hpp",
    "content": "//============================================================================\n// Super-Simple Tasker (SST/C++) Example\n//\n// Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n//\n// SPDX-License-Identifier: MIT\n//\n// Permission is hereby granted, free of charge, to any person obtaining a\n// copy of this software and associated documentation files (the \"Software\"),\n// to deal in the Software without restriction, including without limitation\n// the rights to use, copy, modify, merge, publish, distribute, sublicense,\n// and/or sell copies of the Software, and to permit persons to whom the\n// Software is furnished to do so, subject to the following conditions:\n//\n// The above copyright notice and this permission notice shall be included in\n// all copies or substantial portions of the Software.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n// DEALINGS IN THE SOFTWARE.\n//============================================================================\n#ifndef BLINKY_BUTTON_HPP_\n#define BLINKY_BUTTON_HPP_\n\n#include \"dbc_assert.h\" // Design By Contract (DBC) assertions\n\nnamespace App {\n\nenum Signals {\n    TIMEOUT_SIG,\n    BUTTON_PRESSED_SIG,\n    BUTTON_RELEASED_SIG,\n    BLINKY_WORK_SIG,\n    FORWARD_PRESSED_SIG,\n    FORWARD_RELEASED_SIG,\n    // ...\n    MAX_SIG  // the last signal\n};\n\n// event with parameters\nstruct BlinkyWorkEvt {\n    SST::Evt super;\n    std::uint16_t toggles; // number of toggles of the signal\n    std::uint8_t ticks;    // number of clock ticks between\n};\n\n// event with parameters\nstruct ButtonWorkEvt {\n    SST::Evt super;\n    std::uint16_t toggles; // number of toggles of the signal\n};\n\nextern SST::Task * const AO_Blinky1;  // opaque task pointer\nextern SST::Task * const AO_Blinky3;  // opaque task pointer\nextern SST::Task * const AO_Button2a; // opaque task pointer\nextern SST::Task * const AO_Button2b; // opaque task pointer\n\n} // namespace App\n\n#endif // BLINKY_BUTTON_HPP_\n"
  },
  {
    "path": "sst_cpp/examples/blinky_button/bsp.hpp",
    "content": "//============================================================================\n// Super-Simple Tasker (SST/C++) Example\n//\n// Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n//\n/// SPDX-License-Identifier: MIT\n//\n// Permission is hereby granted, free of charge, to any person obtaining a\n// copy of this software and associated documentation files (the \"Software\"),\n// to deal in the Software without restriction, including without limitation\n// the rights to use, copy, modify, merge, publish, distribute, sublicense,\n// and/or sell copies of the Software, and to permit persons to whom the\n// Software is furnished to do so, subject to the following conditions:\n//\n// The above copyright notice and this permission notice shall be included in\n// all copies or substantial portions of the Software.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n// DEALINGS IN THE SOFTWARE.\n//============================================================================\n#ifndef BSP_HPP_\n#define BSP_HPP_\n\nnamespace BSP {\n\nconstexpr std::uint32_t TICKS_PER_SEC = 1000U;\n\nvoid init(void);\n\nvoid d1on(void);\nvoid d1off(void);\n\nvoid d2on(void);\nvoid d2off(void);\n\nvoid d3on(void);\nvoid d3off(void);\n\nvoid d4on(void);\nvoid d4off(void);\n\nvoid d5on(void);\nvoid d5off(void);\n\nvoid d6on(void);\nvoid d6off(void);\n\n// immutable events for Blinky tasks\nSST::Evt const *getWorkEvtBlinky1(std::uint8_t num);\nSST::Evt const *getWorkEvtBlinky3(std::uint8_t num);\n\n} // namespace BSP\n\n#endif // BSP_HPP_\n"
  },
  {
    "path": "sst_cpp/examples/blinky_button/bsp_ek-tm4c123gxl.cpp",
    "content": "//============================================================================\n// Super-Simple Tasker (SST/C++) Example for TivaC TM4C123GXL\n//\n//                    Q u a n t u m  L e a P s\n//                    ------------------------\n//                    Modern Embedded Software\n//\n// Copyright (C) 2005 Quantum Leaps, <state-machine.com>.\n//\n// SPDX-License-Identifier: MIT\n//\n// Permission is hereby granted, free of charge, to any person obtaining a\n// copy of this software and associated documentation files (the \"Software\"),\n// to deal in the Software without restriction, including without limitation\n// the rights to use, copy, modify, merge, publish, distribute, sublicense,\n// and/or sell copies of the Software, and to permit persons to whom the\n// Software is furnished to do so, subject to the following conditions:\n//\n// The above copyright notice and this permission notice shall be included in\n// all copies or substantial portions of the Software.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n// DEALINGS IN THE SOFTWARE.\n//============================================================================\n#include \"sst.hpp\"           // SST framework\n#include \"bsp.hpp\"           // Board Support Package interface\n#include \"blinky_button.hpp\" // application shared interface\n\n#include \"TM4C123GH6PM.h\"    // the device specific header (TI)\n#include <cmath>             // to exercise the FPU\n// add other drivers if necessary...\n\n// Local-scope defines -------------------------------------------------------\nnamespace {\n\nDBC_MODULE_NAME(\"bsp_ek-tm4c123gxl\") // for DBC assertions in this module\n\n} // unnamed workspace\n\n/* test pins on GPIOF */\n#define TST1_PIN  (1U << 1U) /* LED Red */\n#define TST2_PIN  (1U << 2U) /* LED Blue */\n\n/* test pins on GPIOD */\n#define TST3_PIN  (1U << 0U)\n#define TST4_PIN  (1U << 1U)\n#define TST5_PIN  (1U << 2U)\n\n/* test pins on GPIOF */\n#define TST6_PIN  (1U << 3U) /* LED Green */\n\n/* Button on the board on GPIOF */\n#define BTN_SW1      (1U << 4)\n\n// ISRs used in the application ==============================================\nextern \"C\" {\n\nvoid SysTick_Handler(void) {   // system clock tick ISR\n    BSP::d1on();\n\n    SST::TimeEvt::tick();\n\n    // get state of the user button\n    // Perform the debouncing of buttons. The algorithm for debouncing\n    // adapted from the book \"Embedded Systems Dictionary\" by Jack Ganssle\n    // and Michael Barr, page 71.\n    //\n    static struct ButtonsDebouncing {\n        uint32_t depressed;\n        uint32_t previous;\n    } buttons = { 0U, 0U };\n    uint32_t current = ~GPIOF_AHB->DATA_Bits[BTN_SW1];\n    uint32_t tmp = buttons.depressed; // save the debounced depressed\n    buttons.depressed |= (buttons.previous & current); // set depressed\n    buttons.depressed &= (buttons.previous | current); // clear released\n    buttons.previous   = current; // update the history\n    tmp ^= buttons.depressed;     // changed debounced depressed\n    if ((tmp & BTN_SW1) != 0U) {  /* debounced SW1 state changed? */\n        if ((buttons.depressed & BTN_SW1) != 0U) { /* is SW1 depressed? */\n            // immutable button-press event\n            static App::ButtonWorkEvt const pressEvt = {\n                { App::BUTTON_PRESSED_SIG }, 60U\n            };\n            // immutable forward-press event\n            static App::ButtonWorkEvt const fPressEvt = {\n                { App::FORWARD_PRESSED_SIG }, 60U\n            };\n            App::AO_Button2a->post(&fPressEvt.super);\n            App::AO_Button2a->post(&pressEvt.super);\n        }\n        else { // B1 is released\n            // immutable button-release event\n            static App::ButtonWorkEvt const releaseEvt = {\n                { App::BUTTON_RELEASED_SIG }, 80U\n            };\n            // immutable forward-release event\n            static App::ButtonWorkEvt const fReleaseEvt = {\n                { App::FORWARD_RELEASED_SIG }, 80U\n            };\n            App::AO_Button2a->post(&fReleaseEvt.super);\n            App::AO_Button2a->post(&releaseEvt.super);\n        }\n    }\n\n    BSP::d1off();\n}\n\n// Assertion handler =========================================================\nvoid DBC_fault_handler(char const * const module, int const label) {\n    //\n    // NOTE: add here your application-specific error handling\n    //\n    (void)module;\n    (void)label;\n\n    // set PRIMASK to disable interrupts and stop SST right here\n    __asm volatile (\"cpsid i\");\n\n#ifndef NDEBUG\n    for (;;) { // keep blinking LED2\n        BSP::d6on();  // turn LED2 on\n        uint32_t volatile ctr;\n        for (ctr = 1000000U; ctr > 0U; --ctr) {\n        }\n        BSP::d6off(); // turn LED2 off\n        for (ctr = 1000000U; ctr > 0U; --ctr) {\n        }\n    }\n#endif\n    NVIC_SystemReset();\n}\n//............................................................................\nvoid assert_failed(char const * const module, int const label);// prototype\nvoid assert_failed(char const * const module, int const label) {\n    DBC_fault_handler(module, label);\n}\n\n// SST task activations ======================================================\n// repurpose regular IRQs for SST Tasks\n// prototypes\nvoid PWM1Gen0_IRQHandler(void);\nvoid PWM1Gen1_IRQHandler(void);\nvoid PWM1Gen2_IRQHandler(void);\nvoid PWM1Gen3_IRQHandler(void);\n\nvoid PWM1Gen0_IRQHandler(void) { App::AO_Blinky3->activate();  }\nvoid PWM1Gen1_IRQHandler(void) { App::AO_Button2b->activate(); }\nvoid PWM1Gen2_IRQHandler(void) { App::AO_Button2a->activate(); }\nvoid PWM1Gen3_IRQHandler(void) { App::AO_Blinky1->activate();  }\n\n} // extern \"C\"\n\nnamespace BSP {\n\n// BSP functions =============================================================\nvoid init(void) {\n    // Configure the MPU to prevent NULL-pointer dereferencing\n    // see: www.state-machine.com/null-pointer-protection-with-arm-cortex-m-mpu\n    //\n    MPU->RBAR = 0x0U                          // base address (NULL)\n                | MPU_RBAR_VALID_Msk          // valid region\n                | (MPU_RBAR_REGION_Msk & 7U); // region #7\n    MPU->RASR = (7U << MPU_RASR_SIZE_Pos)     // 2^(7+1) region\n                | (0x0U << MPU_RASR_AP_Pos)   // no-access region\n                | MPU_RASR_ENABLE_Msk;        // region enable\n\n    MPU->CTRL = MPU_CTRL_PRIVDEFENA_Msk       // enable background region\n                | MPU_CTRL_ENABLE_Msk;        // enable the MPU\n    __ISB();\n    __DSB();\n\n    // assign IRQs to tasks. NOTE: critical for SST...\n    App::AO_Blinky3->setIRQ(PWM1_0_IRQn);\n    App::AO_Button2b->setIRQ(PWM1_1_IRQn);\n    App::AO_Button2a->setIRQ(PWM1_2_IRQn);\n    App::AO_Blinky1->setIRQ(PWM1_3_IRQn);\n\n    SYSCTL->RCGCGPIO  |= (1U << 5U); /* enable Run mode for GPIOF */\n    SYSCTL->RCGCGPIO  |= (1U << 3U); /* enable Run mode for GPIOD */\n    __ISB();\n    __DSB();\n\n    SYSCTL->GPIOHBCTL |= (1U << 5); /* enable AHB for GPIOF */\n    SYSCTL->GPIOHBCTL |= (1U << 3); /* enable AHB for GPIOD */\n    __ISB();\n    __DSB();\n\n    /* configure test pins on GPIOF (digital output) */\n    GPIOF_AHB->DIR |= (TST1_PIN | TST2_PIN | TST6_PIN);\n    GPIOF_AHB->DEN |= (TST1_PIN | TST2_PIN | TST6_PIN);\n\n    /* configure button on GPIOF (digital input) */\n    GPIOF_AHB->DIR &= ~(BTN_SW1); /* input */\n    GPIOF_AHB->DEN |= (BTN_SW1); /* digital enable */\n    GPIOF_AHB->PUR |= (BTN_SW1); /* pull-up resistor enable */\n\n    /* configure test pins on GPIOD (digital output) */\n    GPIOD_AHB->DIR |= (TST3_PIN | TST4_PIN | TST5_PIN);\n    GPIOD_AHB->DEN |= (TST3_PIN | TST4_PIN | TST5_PIN);\n}\n\n//............................................................................\n#if defined __ARMCC_VERSION\n#elif defined __GNUC__\nstd::uint32_t __errno; // GNU-ARM needs this to link sqrtf()\n#endif\n\nstatic void exerciseFPU(float x) {\n    // exercise the single-precision FPU by calculating the identity:\n    //  sqrt(x) == x / sqrt(x) for x > 0\n    //\n    float tmp1 = sqrtf(x); // single-precision sqrt()\n    float tmp2 = x / tmp1;\n    DBC_ENSURE(200, (tmp1 - 1e-4f <= tmp2) && (tmp2 <= tmp1 + 1e-4f));\n}\n\n//............................................................................\nvoid d1on(void) { // LED-Red */\n    GPIOF_AHB->DATA_Bits[TST1_PIN] = 0xFFU;\n    // don't use the FPU in the ISR\n}\nvoid d1off(void) {\n    GPIOF_AHB->DATA_Bits[TST1_PIN] = 0x00U;\n}\n//............................................................................\nvoid d2on(void) { /* LED-Blue */\n    GPIOF_AHB->DATA_Bits[TST2_PIN] = 0xFFU;\n    exerciseFPU(1.2345f);\n}\nvoid d2off(void) {\n    GPIOF_AHB->DATA_Bits[TST2_PIN] = 0x00U;\n}\n//............................................................................\nvoid d3on(void) {\n    GPIOD_AHB->DATA_Bits[TST3_PIN] = 0xFFU;\n    exerciseFPU(0.345f);\n}\nvoid d3off(void) {\n    GPIOD_AHB->DATA_Bits[TST3_PIN] = 0x00U;\n}\n//............................................................................\nvoid d4on(void) {\n    GPIOD_AHB->DATA_Bits[TST4_PIN] = 0xFFU;\n    exerciseFPU(0.456f);\n}\nvoid d4off(void) {\n    GPIOD_AHB->DATA_Bits[TST4_PIN] = 0x00U;\n}\n//............................................................................\nvoid d5on(void) {\n    GPIOD_AHB->DATA_Bits[TST5_PIN] = 0xFFU;\n    exerciseFPU(1.567f);\n}\nvoid d5off(void) {\n    GPIOD_AHB->DATA_Bits[TST5_PIN] = 0x00U;\n}\n//............................................................................\nvoid d6on(void) {  /* LED2-Green */\n    GPIOF_AHB->DATA_Bits[TST6_PIN] = 0xFFU;\n    exerciseFPU(1.2345f);\n}\nvoid d6off(void) {\n    GPIOF_AHB->DATA_Bits[TST6_PIN] = 0x00U;\n}\n\n//............................................................................\nSST::Evt const *getWorkEvtBlinky1(uint8_t num) {\n    // immutable work events for Blinky1\n    static App::BlinkyWorkEvt const workBlinky1[] = {\n        { { App::BLINKY_WORK_SIG }, 40U, 5U },\n        { { App::BLINKY_WORK_SIG }, 30U, 7U }\n    };\n    DBC_REQUIRE(500, num < ARRAY_NELEM(workBlinky1)); // num must be in range\n    return &workBlinky1[num].super;\n}\n//............................................................................\nSST::Evt const *getWorkEvtBlinky3(uint8_t num) {\n    // immutable work events for Blinky3\n    static App::BlinkyWorkEvt const workBlinky3[] = {\n        { { App::BLINKY_WORK_SIG }, 20U, 5U },\n        { { App::BLINKY_WORK_SIG }, 10U, 3U   }\n    };\n    DBC_REQUIRE(600, num < ARRAY_NELEM(workBlinky3)); // num must be in range\n    return &workBlinky3[num].super;\n}\n\n} // namespace BSP\n\n// SST callbacks =============================================================\nnamespace SST {\n\nvoid onStart(void) {\n    SystemCoreClockUpdate();\n\n    // set up the SysTick timer to fire at BSP::TICKS_PER_SEC rate\n    SysTick_Config((SystemCoreClock / BSP::TICKS_PER_SEC) + 1U);\n\n    // set priorities of ISRs used in the system\n    NVIC_SetPriority(SysTick_IRQn, 0U);\n    // ...\n}\n//............................................................................\nvoid onIdle(void) {\n    BSP::d6on();  // turn LED-Green on\n#ifdef NDEBUG\n    // Put the CPU and peripherals to the low-power mode.\n    // you might need to customize the clock management for your application,\n    // see the datasheet for your particular Cortex-M MCU.\n    //\n    BSP::d6off(); // turn LED-Green off\n    __WFI(); // Wait-For-Interrupt\n    BSP::d6on();  // turn LED-Green on\n#else\n#endif\n    BSP::d6off(); // turn LED-Green off\n}\n\n} // namespace SST\n"
  },
  {
    "path": "sst_cpp/examples/blinky_button/bsp_nucleo-c031c6.cpp",
    "content": "//============================================================================\n// Super-Simple Tasker (SST/C++) Example for STM32 NUCLEO-C031C6\n//\n//\n//                    Q u a n t u m  L e a P s\n//                    ------------------------\n//                    Modern Embedded Software\n//\n// Copyright (C) 2005 Quantum Leaps, <state-machine.com>.\n//\n// SPDX-License-Identifier: MIT\n//\n// Permission is hereby granted, free of charge, to any person obtaining a\n// copy of this software and associated documentation files (the \"Software\"),\n// to deal in the Software without restriction, including without limitation\n// the rights to use, copy, modify, merge, publish, distribute, sublicense,\n// and/or sell copies of the Software, and to permit persons to whom the\n// Software is furnished to do so, subject to the following conditions:\n//\n// The above copyright notice and this permission notice shall be included in\n// all copies or substantial portions of the Software.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n// DEALINGS IN THE SOFTWARE.\n//============================================================================\n#include \"sst.hpp\"           // SST framework\n#include \"bsp.hpp\"           // Board Support Package interface\n#include \"blinky_button.hpp\" // application shared interface\n\n#include \"stm32c0xx.h\"  // CMSIS-compliant header file for the MCU used\n// add other drivers if necessary...\n\n// Local-scope defines -------------------------------------------------------\nnamespace {\n\nDBC_MODULE_NAME(\"bsp_nucleo-c031c6\") // for DBC assertions in this module\n\n} // unnamed workspace\n\n// test pins on GPIO PA\n#define TST1_PIN  7U\n#define TST2_PIN  6U\n#define TST3_PIN  4U\n#define TST4_PIN  1U\n#define TST5_PIN  0U\n#define TST6_PIN  5U /* LED L4-Green */\n\n// buttons on GPIO PC\n#define B1_PIN    13U\n\n// ISRs used in the application ==============================================\nextern \"C\" {\n\nvoid SysTick_Handler(void);  // prototype\nvoid SysTick_Handler(void) { // system clock tick ISR\n    BSP::d1on();\n\n    SST::TimeEvt::tick();\n\n    // get state of the user button\n    // Perform the debouncing of buttons. The algorithm for debouncing\n    // adapted from the book \"Embedded Systems Dictionary\" by Jack Ganssle\n    // and Michael Barr, page 71.\n    //\n    static struct ButtonsDebouncing {\n        uint32_t depressed;\n        uint32_t previous;\n    } buttons = { 0U, 0U };\n    uint32_t current = ~GPIOC->IDR; // read GPIO PortC\n    uint32_t tmp = buttons.depressed; // save the debounced depressed\n    buttons.depressed |= (buttons.previous & current); // set depressed\n    buttons.depressed &= (buttons.previous | current); // clear released\n    buttons.previous   = current; // update the history\n    tmp ^= buttons.depressed;     // changed debounced depressed\n    if ((tmp & (1U << B1_PIN)) != 0U) { // debounced B1 state changed?\n        if ((buttons.depressed & (1U << B1_PIN)) != 0U) { // depressed?\n            // immutable button-press event\n            static App::ButtonWorkEvt const pressEvt = {\n                { App::BUTTON_PRESSED_SIG }, 60U\n            };\n            // immutable forward-press event\n            static App::ButtonWorkEvt const fPressEvt = {\n                { App::FORWARD_PRESSED_SIG }, 60U\n            };\n            App::AO_Button2a->post(&fPressEvt.super);\n            App::AO_Button2a->post(&pressEvt.super);\n        }\n        else { // B1 is released\n            // immutable button-release event\n            static App::ButtonWorkEvt const releaseEvt = {\n                { App::BUTTON_RELEASED_SIG }, 80U\n            };\n            // immutable forward-release event\n            static App::ButtonWorkEvt const fReleaseEvt = {\n                { App::FORWARD_RELEASED_SIG }, 80U\n            };\n            App::AO_Button2a->post(&fReleaseEvt.super);\n            App::AO_Button2a->post(&releaseEvt.super);\n        }\n    }\n\n    BSP::d1off();\n}\n\n// Assertion handler =========================================================\nvoid DBC_fault_handler(char const * const module, int const label) {\n    //\n    // NOTE: add here your application-specific error handling\n    //\n    (void)module;\n    (void)label;\n\n    // set PRIMASK to disable interrupts and stop SST right here\n    __asm volatile (\"cpsid i\");\n\n#ifndef NDEBUG\n    for (;;) { // keep blinking LED2\n        BSP::d6on();  // turn LED2 on\n        uint32_t volatile ctr;\n        for (ctr = 10000U; ctr > 0U; --ctr) {\n        }\n        BSP::d6off(); // turn LED2 off\n        for (ctr = 10000U; ctr > 0U; --ctr) {\n        }\n    }\n#endif\n    NVIC_SystemReset();\n}\n//............................................................................\nvoid assert_failed(char const * const module, int const label);// prototype\nvoid assert_failed(char const * const module, int const label) {\n    DBC_fault_handler(module, label);\n}\n\n// SST task activations ======================================================\n// preprocessor switch to choose between regular and reserved IRQs\n#define REGULAR_IRQS\n\n#ifdef REGULAR_IRQS\n// repurpose regular IRQs for SST Tasks\n// prototypes\nvoid TIM3_IRQHandler(void);\nvoid TIM14_IRQHandler(void);\nvoid TIM16_IRQHandler(void);\nvoid TIM17_IRQHandler(void);\n\nvoid TIM3_IRQHandler(void)  { App::AO_Blinky3->activate();  }\nvoid TIM14_IRQHandler(void) { App::AO_Button2b->activate(); }\nvoid TIM16_IRQHandler(void) { App::AO_Button2a->activate(); }\nvoid TIM17_IRQHandler(void) { App::AO_Blinky1->activate();  }\n\n\n#else // use reserved IRQs for SST Tasks\n// prototypes\nvoid Reserved1_IRQHandler(void);\nvoid Reserved8_IRQHandler(void);\nvoid Reserved15_IRQHandler(void);\nvoid Reserved17_IRQHandler(void);\n\n// use reserved IRQs for SST Tasks\nvoid Reserved1_IRQHandler(void)  { App::AO_Blinky3->activate();  }\nvoid Reserved8_IRQHandler(void)  { App::AO_Button2b->activate(); }\nvoid Reserved15_IRQHandler(void) { App::AO_Button2a->activate(); }\nvoid Reserved17_IRQHandler(void) { App::AO_Blinky1->activate();  }\n#endif\n\n} // extern \"C\"\n\nnamespace BSP {\n\n// BSP functions =============================================================\nvoid init(void) {\n    // Configure the MPU to prevent NULL-pointer dereferencing\n    // see: www.state-machine.com/null-pointer-protection-with-arm-cortex-m-mpu\n    //\n    MPU->RBAR = 0x0U                          // base address (NULL)\n                | MPU_RBAR_VALID_Msk          // valid region\n                | (MPU_RBAR_REGION_Msk & 7U); // region #7\n    MPU->RASR = (7U << MPU_RASR_SIZE_Pos)     // 2^(7+1) region\n                | (0x0U << MPU_RASR_AP_Pos)   // no-access region\n                | MPU_RASR_ENABLE_Msk;        // region enable\n\n    MPU->CTRL = MPU_CTRL_PRIVDEFENA_Msk       // enable background region\n                | MPU_CTRL_ENABLE_Msk;        // enable the MPU\n    __ISB();\n    __DSB();\n\n    // assign IRQs to tasks. NOTE: critical for SST...\n#ifdef REGULAR_IRQS\n    // repurpose regular IRQs for SST Tasks\n    App::AO_Blinky3->setIRQ (TIM3_IRQn);\n    App::AO_Button2b->setIRQ(TIM14_IRQn);\n    App::AO_Button2a->setIRQ(TIM16_IRQn);\n    App::AO_Blinky1->setIRQ (TIM17_IRQn);\n#else\n    // use reserved IRQs for SST Tasks\n    App::AO_Blinky3->setIRQ (1U);\n    App::AO_Button2b->setIRQ(8U);\n    App::AO_Button2a->setIRQ(15U);\n    App::AO_Blinky1->setIRQ (17U);\n#endif\n\n    // enable GPIO port PA clock\n    RCC->IOPENR |= (1U << 0U);\n\n    // set all used GPIOA pins as push-pull output, no pull-up, pull-down\n    GPIOA->MODER &=\n        ~((3U << 2U*TST1_PIN) | (3U << 2U*TST2_PIN) | (3U << 2U*TST3_PIN) |\n          (3U << 2U*TST4_PIN) | (3U << 2U*TST5_PIN) | (3U << 2U*TST6_PIN));\n    GPIOA->MODER |=\n         ((1U << 2U*TST1_PIN) | (1U << 2U*TST2_PIN) | (1U << 2U*TST3_PIN) |\n          (1U << 2U*TST4_PIN) | (1U << 2U*TST5_PIN) | (1U << 2U*TST6_PIN));\n    GPIOA->OTYPER &=\n        ~((1U <<    TST1_PIN) | (1U <<    TST2_PIN) | (1U <<    TST3_PIN) |\n          (1U <<    TST4_PIN) | (1U <<    TST5_PIN) | (1U <<    TST6_PIN));\n    GPIOA->OSPEEDR &=\n        ~((3U << 2U*TST1_PIN) | (3U << 2U*TST2_PIN) | (3U << 2U*TST3_PIN) |\n          (3U << 2U*TST4_PIN) | (3U << 2U*TST5_PIN) | (3U << 2U*TST6_PIN));\n    GPIOA->OSPEEDR |=\n         ((1U << 2U*TST1_PIN) | (1U << 2U*TST2_PIN) | (1U << 2U*TST3_PIN) |\n          (1U << 2U*TST4_PIN) | (1U << 2U*TST5_PIN) | (1U << 2U*TST6_PIN));\n   GPIOA->PUPDR &=\n        ~((3U << 2U*TST1_PIN) | (3U << 2U*TST2_PIN) | (3U << 2U*TST3_PIN) |\n          (3U << 2U*TST4_PIN) | (3U << 2U*TST5_PIN) | (3U << 2U*TST6_PIN));\n\n    // enable GPIOC clock port for the Button B1\n    RCC->IOPENR |=  (1U << 2U);\n\n    // configure Button B1 pin on GPIOC as input, no pull-up, pull-down\n    GPIOC->MODER &= ~(3U << 2U*B1_PIN);\n    GPIOC->PUPDR &= ~(3U << 2U*B1_PIN);\n}\n//............................................................................\nvoid d1on(void)  { GPIOA->BSRR = (1U << TST1_PIN);         }\nvoid d1off(void) { GPIOA->BSRR = (1U << (TST1_PIN + 16U)); }\n//............................................................................\nvoid d2on(void)  { GPIOA->BSRR = (1U << TST2_PIN);         }\nvoid d2off(void) { GPIOA->BSRR = (1U << (TST2_PIN + 16U)); }\n//............................................................................\nvoid d3on(void)  { GPIOA->BSRR = (1U << TST3_PIN);         }\nvoid d3off(void) { GPIOA->BSRR = (1U << (TST3_PIN + 16U)); }\n//............................................................................\nvoid d4on(void)  { GPIOA->BSRR = (1U << TST4_PIN);         }\nvoid d4off(void) { GPIOA->BSRR = (1U << (TST4_PIN + 16U)); }\n//............................................................................\nvoid d5on(void)  { GPIOA->BSRR = (1U << TST5_PIN);         }\nvoid d5off(void) { GPIOA->BSRR = (1U << (TST5_PIN + 16U)); }\n//............................................................................\nvoid d6on(void)  { GPIOA->BSRR = (1U << TST6_PIN);         } // LD4\nvoid d6off(void) { GPIOA->BSRR = (1U << (TST6_PIN + 16U)); }\n\n//............................................................................\nSST::Evt const *getWorkEvtBlinky1(uint8_t num) {\n    // immutable work events for Blinky1\n    static App::BlinkyWorkEvt const workBlinky1[] = {\n        { { App::BLINKY_WORK_SIG }, 40U, 5U },\n        { { App::BLINKY_WORK_SIG }, 30U, 7U }\n    };\n    DBC_REQUIRE(500, num < ARRAY_NELEM(workBlinky1)); // num must be in range\n    return &workBlinky1[num].super;\n}\n//............................................................................\nSST::Evt const *getWorkEvtBlinky3(uint8_t num) {\n    // immutable work events for Blinky3\n    static App::BlinkyWorkEvt const workBlinky3[] = {\n        { { App::BLINKY_WORK_SIG }, 20U, 5U },\n        { { App::BLINKY_WORK_SIG }, 10U, 3U   }\n    };\n    DBC_REQUIRE(600, num < ARRAY_NELEM(workBlinky3)); // num must be in range\n    return &workBlinky3[num].super;\n}\n\n} // namespace BSP\n\n// SST callbacks =============================================================\nnamespace SST {\n\nvoid onStart(void) {\n    SystemCoreClockUpdate();\n\n    // set up the SysTick timer to fire at BSP::TICKS_PER_SEC rate\n    SysTick_Config((SystemCoreClock / BSP::TICKS_PER_SEC) + 1U);\n\n    // set priorities of ISRs used in the system\n    NVIC_SetPriority(SysTick_IRQn, 0U);\n    // ...\n}\n//............................................................................\nvoid onIdle(void) {\n    BSP::d6on();  // turn LED2 on\n#ifdef NDEBUG\n    // Put the CPU and peripherals to the low-power mode.\n    // you might need to customize the clock management for your application,\n    // see the datasheet for your particular Cortex-M MCU.\n    //\n    BSP::d6off(); // turn LED2 off\n    __WFI(); // Wait-For-Interrupt\n    BSP::d6on();  // turn LED2 on\n#endif\n    BSP::d6off(); // turn LED2 off\n}\n\n} // namespace SST\n\n"
  },
  {
    "path": "sst_cpp/examples/blinky_button/bsp_nucleo-h743zi.cpp",
    "content": "//============================================================================\n// Super-Simple Tasker (SST/C++) Example for STM32 NUCLEO-H74cZI\n//\n//\n//                    Q u a n t u m  L e a P s\n//                    ------------------------\n//                    Modern Embedded Software\n//\n// Copyright (C) 2005 Quantum Leaps, <state-machine.com>.\n//\n// SPDX-License-Identifier: MIT\n//\n// Permission is hereby granted, free of charge, to any person obtaining a\n// copy of this software and associated documentation files (the \"Software\"),\n// to deal in the Software without restriction, including without limitation\n// the rights to use, copy, modify, merge, publish, distribute, sublicense,\n// and/or sell copies of the Software, and to permit persons to whom the\n// Software is furnished to do so, subject to the following conditions:\n//\n// The above copyright notice and this permission notice shall be included in\n// all copies or substantial portions of the Software.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n// DEALINGS IN THE SOFTWARE.\n//============================================================================\n#include \"sst.hpp\"           // SST framework\n#include \"bsp.hpp\"           // Board Support Package interface\n#include \"blinky_button.hpp\" // application shared interface\n\n#include \"stm32h743xx.h\"  // CMSIS-compliant header file for the MCU used\n#include <cmath>          // to exercise the FPU\n// add other drivers if necessary...\n\n// Local-scope defines -------------------------------------------------------\nnamespace {\n\nDBC_MODULE_NAME(\"bsp_nucleo-h743zi\") // for DBC assertions in this module\n\n} // unnamed workspace\n\n// test pins on GPIO PB\n#define TST1_PIN  0U  /* PB.0  LED1-Green */\n#define TST2_PIN  14U /* PB.14 LED3-Red   */\n#define TST3_PIN  4U\n#define TST4_PIN  5U\n#define TST5_PIN  6U\n#define TST6_PIN  7U  /* PB.7  LED2-Blue  */\n\n// buttons on GPIO PC\n#define B1_PIN    13U\n\n// ISRs used in the application ==============================================\nextern \"C\" {\n\nvoid SysTick_Handler(void) {   // system clock tick ISR\n    BSP::d1on();\n\n    SST::TimeEvt::tick();\n\n    // get state of the user button\n    // Perform the debouncing of buttons. The algorithm for debouncing\n    // adapted from the book \"Embedded Systems Dictionary\" by Jack Ganssle\n    // and Michael Barr, page 71.\n    //\n    static struct ButtonsDebouncing {\n        uint32_t depressed;\n        uint32_t previous;\n    } buttons = { 0U, 0U };\n    uint32_t current = GPIOC->IDR; // read GPIO PortC\n    uint32_t tmp = buttons.depressed; // save the debounced depressed\n    buttons.depressed |= (buttons.previous & current); // set depressed\n    buttons.depressed &= (buttons.previous | current); // clear released\n    buttons.previous   = current; // update the history\n    tmp ^= buttons.depressed;     // changed debounced depressed\n    if ((tmp & (1U << B1_PIN)) != 0U) { // debounced B1 state changed?\n        if ((buttons.depressed & (1U << B1_PIN)) != 0U) { // depressed?\n            // immutable button-press event\n            static App::ButtonWorkEvt const pressEvt = {\n                { App::BUTTON_PRESSED_SIG }, 60U\n            };\n            // immutable forward-press event\n            static App::ButtonWorkEvt const fPressEvt = {\n                { App::FORWARD_PRESSED_SIG }, 60U\n            };\n            App::AO_Button2a->post(&fPressEvt.super);\n            App::AO_Button2a->post(&pressEvt.super);\n        }\n        else { // B1 is released\n            // immutable button-release event\n            static App::ButtonWorkEvt const releaseEvt = {\n                { App::BUTTON_RELEASED_SIG }, 80U\n            };\n            // immutable forward-release event\n            static App::ButtonWorkEvt const fReleaseEvt = {\n                { App::FORWARD_RELEASED_SIG }, 80U\n            };\n            App::AO_Button2a->post(&fReleaseEvt.super);\n            App::AO_Button2a->post(&releaseEvt.super);\n        }\n    }\n\n    BSP::d1off();\n}\n\n// Assertion handler =========================================================\nvoid DBC_fault_handler(char const * const module, int const label) {\n    //\n    // NOTE: add here your application-specific error handling\n    //\n    (void)module;\n    (void)label;\n\n    // set PRIMASK to disable interrupts and stop SST right here\n    __asm volatile (\"cpsid i\");\n\n#ifndef NDEBUG\n    for (;;) { // keep blinking LED2\n        BSP::d6on();  // turn LED2 on\n        uint32_t volatile ctr;\n        for (ctr = 1000000U; ctr > 0U; --ctr) {\n        }\n        BSP::d6off(); // turn LED2 off\n        for (ctr = 1000000U; ctr > 0U; --ctr) {\n        }\n    }\n#endif\n    NVIC_SystemReset();\n}\n//............................................................................\nvoid assert_failed(char const * const module, int const label);// prototype\nvoid assert_failed(char const * const module, int const label) {\n    DBC_fault_handler(module, label);\n}\n\n// SST task activations ======================================================\n// preprocessor switch to choose between regular and reserved IRQs\n#define REGULAR_IRQS\n\n#ifdef REGULAR_IRQS\n// repurpose regular IRQs for SST Tasks\n// prototypes\nvoid OTG_FS_EP1_OUT_IRQHandler(void);\nvoid OTG_FS_EP1_IN_IRQHandler(void);\nvoid OTG_FS_WKUP_IRQHandler(void);\nvoid OTG_FS_IRQHandler(void);\n\nvoid OTG_FS_EP1_OUT_IRQHandler(void) { App::AO_Blinky3->activate();  }\nvoid OTG_FS_EP1_IN_IRQHandler(void)  { App::AO_Button2b->activate(); }\nvoid OTG_FS_WKUP_IRQHandler(void)    { App::AO_Button2a->activate(); }\nvoid OTG_FS_IRQHandler(void)         { App::AO_Blinky1->activate();  }\n\n#else // use reserved IRQs for SST Tasks\n// prototypes\nvoid Reserved42_IRQHandler(void);  // prototype\nvoid Reserved64_IRQHandler(void);  // prototype\nvoid Reserved65_IRQHandler(void);  // prototype\nvoid Reserved66_IRQHandler(void);  // prototype\n\nvoid Reserved42_IRQHandler(void) { App::AO_Blinky3->activate();  }\nvoid Reserved64_IRQHandler(void) { App::AO_Button2b->activate(); }\nvoid Reserved65_IRQHandler(void) { App::AO_Button2a->activate(); }\nvoid Reserved66_IRQHandler(void) { App::AO_Blinky1->activate();  }\n#endif\n\n} // extern \"C\"\n\nnamespace BSP {\n\n// BSP functions =============================================================\nvoid init(void) {\n    // Configure the MPU to prevent NULL-pointer dereferencing\n    // see: www.state-machine.com/null-pointer-protection-with-arm-cortex-m-mpu\n    //\n    MPU->RBAR = 0x0U                          // base address (NULL)\n                | MPU_RBAR_VALID_Msk          // valid region\n                | (MPU_RBAR_REGION_Msk & 7U); // region #7\n    MPU->RASR = (7U << MPU_RASR_SIZE_Pos)     // 2^(7+1) region\n                | (0x0U << MPU_RASR_AP_Pos)   // no-access region\n                | MPU_RASR_ENABLE_Msk;        // region enable\n\n    MPU->CTRL = MPU_CTRL_PRIVDEFENA_Msk       // enable background region\n                | MPU_CTRL_ENABLE_Msk;        // enable the MPU\n    __ISB();\n    __DSB();\n\n    SCB_EnableICache(); // Enable I-Cache\n    SCB_EnableDCache(); // Enable D-Cache\n\n    // assign IRQs to tasks. NOTE: critical for SST...\n#ifdef REGULAR_IRQS\n    // repurpose regular IRQs for SST Tasks\n    App::AO_Blinky3->setIRQ(OTG_FS_EP1_OUT_IRQn);\n    App::AO_Button2b->setIRQ(OTG_FS_EP1_IN_IRQn);\n    App::AO_Button2a->setIRQ(OTG_FS_WKUP_IRQn);\n    App::AO_Blinky1->setIRQ(OTG_FS_IRQn);\n#else\n    // use reserved IRQs for SST Tasks\n    App::AO_Blinky3->setIRQ(42U);\n    App::AO_Button2b->setIRQ(64U);\n    App::AO_Button2a->setIRQ(65U);\n    App::AO_Blinky1->setIRQ(66U);\n#endif\n\n    // enable GPIOB port clock for LEds and test pins\n    RCC->AHB4ENR |= RCC_AHB4ENR_GPIOBEN;\n\n    // set all used GPIOB pins as push-pull output, no pull-up, pull-down\n    GPIOB->MODER &=\n        ~((3U << 2U*TST1_PIN) | (3U << 2U*TST2_PIN) | (3U << 2U*TST3_PIN) |\n          (3U << 2U*TST4_PIN) | (3U << 2U*TST5_PIN) | (3U << 2U*TST6_PIN));\n    GPIOB->MODER |=\n         ((1U << 2U*TST1_PIN) | (1U << 2U*TST2_PIN) | (1U << 2U*TST3_PIN) |\n          (1U << 2U*TST4_PIN) | (1U << 2U*TST5_PIN) | (1U << 2U*TST6_PIN));\n    GPIOB->OTYPER &=\n        ~((1U <<    TST1_PIN) | (1U <<    TST2_PIN) | (1U <<    TST3_PIN) |\n          (1U <<    TST4_PIN) | (1U <<    TST5_PIN) | (1U <<    TST6_PIN));\n    GPIOB->PUPDR &=\n        ~((3U << 2U*TST1_PIN) | (3U << 2U*TST2_PIN) | (3U << 2U*TST3_PIN) |\n          (3U << 2U*TST4_PIN) | (3U << 2U*TST5_PIN) | (3U << 2U*TST6_PIN));\n\n    // enable GPIOC clock port for the Button B1\n    RCC->AHB4ENR |= RCC_AHB4ENR_GPIOCEN;\n\n    // configure Button B1 pin on GPIOC as input, no pull-up, pull-down\n    GPIOC->MODER &= ~(3U << 2U*B1_PIN);\n    GPIOC->PUPDR &= ~(GPIO_PUPDR_PUPD0 << 2U*B1_PIN);\n    GPIOC->PUPDR |=  (2U << 2U*B1_PIN);\n}\n\n//............................................................................\nstatic void exerciseFPU(double x) {\n    // exercise the double-precision FPU by calculating the identity:\n    //  sin(x)^2 + cos(x)^2 == 1.0 for any x\n    //\n    double tmp = pow(sin(x), 2.0) + pow(cos(x), 2.0);\n    DBC_ENSURE(200, ((1.0 - 1e-4) < tmp) && (tmp < (1.0 + 1e-4)));\n}\n\n//............................................................................\nvoid d1on(void) {  // LED1-Green\n    GPIOB->BSRR = (1U << TST1_PIN);\n    // don't use the FPU in the ISR\n}\nvoid d1off(void) {\n    GPIOB->BSRR = (1U << (TST1_PIN + 16U));\n}\n//............................................................................\nvoid d2on(void) {  // LED3-Red\n    GPIOB->BSRR = (1U << TST2_PIN);\n    exerciseFPU(-1.2345);\n}\nvoid d2off(void) {\n    GPIOB->BSRR = (1U << (TST2_PIN + 16U));\n}\n//............................................................................\nvoid d3on(void) {\n    GPIOB->BSRR = (1U << TST3_PIN);\n    exerciseFPU(-12.345);\n}\nvoid d3off(void) {\n    GPIOB->BSRR = (1U << (TST3_PIN + 16U));\n}\n//............................................................................\nvoid d4on(void) {\n    GPIOB->BSRR = (1U << TST4_PIN);\n    exerciseFPU(3.456);\n}\nvoid d4off(void) {\n    GPIOB->BSRR = (1U << (TST4_PIN + 16U));\n}\n//............................................................................\nvoid d5on(void) {\n    GPIOB->BSRR = (1U << TST5_PIN);\n    exerciseFPU(4.567);\n}\nvoid d5off(void) {\n    GPIOB->BSRR = (1U << (TST5_PIN + 16U));\n}\n//............................................................................\nvoid d6on(void) {  // LED2-Blue\n    GPIOB->BSRR = (1U << TST6_PIN);\n    exerciseFPU(1.2345);\n}\nvoid d6off(void) {\n    GPIOB->BSRR = (1U << (TST6_PIN + 16U));\n}\n\n//............................................................................\nSST::Evt const *getWorkEvtBlinky1(uint8_t num) {\n    // immutable work events for Blinky1\n    static App::BlinkyWorkEvt const workBlinky1[] = {\n        { { App::BLINKY_WORK_SIG }, 40U, 5U },\n        { { App::BLINKY_WORK_SIG }, 30U, 7U }\n    };\n    DBC_REQUIRE(500, num < ARRAY_NELEM(workBlinky1)); // num must be in range\n    return &workBlinky1[num].super;\n}\n//............................................................................\nSST::Evt const *getWorkEvtBlinky3(uint8_t num) {\n    // immutable work events for Blinky3\n    static App::BlinkyWorkEvt const workBlinky3[] = {\n        { { App::BLINKY_WORK_SIG }, 20U, 5U },\n        { { App::BLINKY_WORK_SIG }, 10U, 3U   }\n    };\n    DBC_REQUIRE(600, num < ARRAY_NELEM(workBlinky3)); // num must be in range\n    return &workBlinky3[num].super;\n}\n\n} // namespace BSP\n\n// SST callbacks =============================================================\nnamespace SST {\n\nvoid onStart(void) {\n    SystemCoreClockUpdate();\n\n    // set up the SysTick timer to fire at BSP::TICKS_PER_SEC rate\n    SysTick_Config((SystemCoreClock / BSP::TICKS_PER_SEC) + 1U);\n\n    // set priorities of ISRs used in the system\n    NVIC_SetPriority(SysTick_IRQn, 0U);\n    // ...\n}\n//............................................................................\nvoid onIdle(void) {\n    BSP::d6on();  // turn LED2 on\n#ifdef NDEBUG\n    // Put the CPU and peripherals to the low-power mode.\n    // you might need to customize the clock management for your application,\n    // see the datasheet for your particular Cortex-M MCU.\n    //\n    BSP::d6off(); // turn LED2 off\n    __WFI(); // Wait-For-Interrupt\n    BSP::d6on();  // turn LED2 on\n#endif\n    BSP::d6off(); // turn LED2 off\n}\n\n} // namespace SST\n\n"
  },
  {
    "path": "sst_cpp/examples/blinky_button/bsp_nucleo-l053r8.cpp",
    "content": "//============================================================================\n// Super-Simple Tasker (SST/C++) Example for STM32 NUCLEO-L053R8\n//\n//\n//                    Q u a n t u m  L e a P s\n//                    ------------------------\n//                    Modern Embedded Software\n//\n// Copyright (C) 2005 Quantum Leaps, <state-machine.com>.\n//\n// SPDX-License-Identifier: MIT\n//\n// Permission is hereby granted, free of charge, to any person obtaining a\n// copy of this software and associated documentation files (the \"Software\"),\n// to deal in the Software without restriction, including without limitation\n// the rights to use, copy, modify, merge, publish, distribute, sublicense,\n// and/or sell copies of the Software, and to permit persons to whom the\n// Software is furnished to do so, subject to the following conditions:\n//\n// The above copyright notice and this permission notice shall be included in\n// all copies or substantial portions of the Software.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n// DEALINGS IN THE SOFTWARE.\n//============================================================================\n#include \"sst.hpp\"           // SST framework\n#include \"bsp.hpp\"           // Board Support Package interface\n#include \"blinky_button.hpp\" // application shared interface\n\n#include \"stm32l0xx.h\"  // CMSIS-compliant header file for the MCU used\n// add other drivers if necessary...\n\n// Local-scope defines -------------------------------------------------------\nnamespace {\n\nDBC_MODULE_NAME(\"bsp_nucleo-l053r8\") // for DBC assertions in this module\n\n} // unnamed workspace\n\n// test pins on GPIO PA\n#define TST1_PIN  7U\n#define TST2_PIN  6U\n#define TST3_PIN  4U\n#define TST4_PIN  1U\n#define TST5_PIN  0U\n#define TST6_PIN  5U /* LED LD2-Green */\n\n// buttons on GPIO PC\n#define B1_PIN    13U\n\n// ISRs used in the application ==============================================\nextern \"C\" {\n\nvoid SysTick_Handler(void);  // prototype\nvoid SysTick_Handler(void) { // system clock tick ISR\n    BSP::d1on();\n\n    SST::TimeEvt::tick();\n\n    // get state of the user button\n    // Perform the debouncing of buttons. The algorithm for debouncing\n    // adapted from the book \"Embedded Systems Dictionary\" by Jack Ganssle\n    // and Michael Barr, page 71.\n    //\n    static struct ButtonsDebouncing {\n        uint32_t depressed;\n        uint32_t previous;\n    } buttons = { 0U, 0U };\n    uint32_t current = ~GPIOC->IDR; // read GPIO PortC\n    uint32_t tmp = buttons.depressed; // save the debounced depressed\n    buttons.depressed |= (buttons.previous & current); // set depressed\n    buttons.depressed &= (buttons.previous | current); // clear released\n    buttons.previous   = current; // update the history\n    tmp ^= buttons.depressed;     // changed debounced depressed\n    if ((tmp & (1U << B1_PIN)) != 0U) { // debounced B1 state changed?\n        if ((buttons.depressed & (1U << B1_PIN)) != 0U) { // depressed?\n            // immutable button-press event\n            static App::ButtonWorkEvt const pressEvt = {\n                { App::BUTTON_PRESSED_SIG }, 60U\n            };\n            // immutable forward-press event\n            static App::ButtonWorkEvt const fPressEvt = {\n                { App::FORWARD_PRESSED_SIG }, 60U\n            };\n            App::AO_Button2a->post(&fPressEvt.super);\n            App::AO_Button2a->post(&pressEvt.super);\n        }\n        else { // B1 is released\n            // immutable button-release event\n            static App::ButtonWorkEvt const releaseEvt = {\n                { App::BUTTON_RELEASED_SIG }, 80U\n            };\n            // immutable forward-release event\n            static App::ButtonWorkEvt const fReleaseEvt = {\n                { App::FORWARD_RELEASED_SIG }, 80U\n            };\n            App::AO_Button2a->post(&fReleaseEvt.super);\n            App::AO_Button2a->post(&releaseEvt.super);\n        }\n    }\n\n    BSP::d1off();\n}\n\n// Assertion handler =========================================================\nvoid DBC_fault_handler(char const * const module, int const label) {\n    //\n    // NOTE: add here your application-specific error handling\n    //\n    (void)module;\n    (void)label;\n\n    // set PRIMASK to disable interrupts and stop SST right here\n    __asm volatile (\"cpsid i\");\n\n#ifndef NDEBUG\n    for (;;) { // keep blinking LED2\n        BSP::d6on();  // turn LED2 on\n        uint32_t volatile ctr;\n        for (ctr = 10000U; ctr > 0U; --ctr) {\n        }\n        BSP::d6off(); // turn LED2 off\n        for (ctr = 10000U; ctr > 0U; --ctr) {\n        }\n    }\n#endif\n    NVIC_SystemReset();\n}\n//............................................................................\nvoid assert_failed(char const * const module, int const label);// prototype\nvoid assert_failed(char const * const module, int const label) {\n    DBC_fault_handler(module, label);\n}\n\n// SST task activations ======================================================\n// preprocessor switch to choose between regular and reserved IRQs\n#define REGULAR_IRQS\n\n#ifdef REGULAR_IRQS\n// repurpose regular IRQs for SST Tasks\n// prototypes\nvoid PVD_IRQHandler(void);\nvoid RTC_IRQHandler(void);\nvoid TSC_IRQHandler(void);\nvoid I2C2_IRQHandler(void);\n\nvoid PVD_IRQHandler(void)  { App::AO_Blinky3->activate();  }\nvoid RTC_IRQHandler(void)  { App::AO_Button2b->activate(); }\nvoid TSC_IRQHandler(void)  { App::AO_Button2a->activate(); }\nvoid I2C2_IRQHandler(void) { App::AO_Blinky1->activate();  }\n\n#else // use reserved IRQs for SST Tasks\n// prototypes\nvoid Reserved14_IRQHandler(void); // prototype\nvoid Reserved16_IRQHandler(void); // prototype\nvoid Reserved18_IRQHandler(void); // prototype\nvoid Reserved19_IRQHandler(void); // prototype\n\n// use reserved IRQs for SST Tasks\nvoid Reserved14_IRQHandler(void) { App::AO_Blinky3->activate();  }\nvoid Reserved16_IRQHandler(void) { App::AO_Button2b->activate(); }\nvoid Reserved18_IRQHandler(void) { App::AO_Button2a->activate(); }\nvoid Reserved19_IRQHandler(void) { App::AO_Blinky1->activate();  }\n#endif\n\n} // extern \"C\"\n\nnamespace BSP {\n\n// BSP functions =============================================================\nvoid init(void) {\n    // Configure the MPU to prevent NULL-pointer dereferencing\n    // see: www.state-machine.com/null-pointer-protection-with-arm-cortex-m-mpu\n    //\n    MPU->RBAR = 0x0U                          // base address (NULL)\n                | MPU_RBAR_VALID_Msk          // valid region\n                | (MPU_RBAR_REGION_Msk & 7U); // region #7\n    MPU->RASR = (7U << MPU_RASR_SIZE_Pos)     // 2^(7+1) region\n                | (0x0U << MPU_RASR_AP_Pos)   // no-access region\n                | MPU_RASR_ENABLE_Msk;        // region enable\n\n    MPU->CTRL = MPU_CTRL_PRIVDEFENA_Msk       // enable background region\n                | MPU_CTRL_ENABLE_Msk;        // enable the MPU\n    __ISB();\n    __DSB();\n\n    // assign IRQs to tasks. NOTE: critical for SST...\n#ifdef REGULAR_IRQS\n    // repurpose regular IRQs for SST Tasks\n    App::AO_Blinky3->setIRQ (PVD_IRQn);\n    App::AO_Button2b->setIRQ(RTC_IRQn);\n    App::AO_Button2a->setIRQ(TSC_IRQn);\n    App::AO_Blinky1->setIRQ (I2C2_IRQn);\n#else\n    // use reserved IRQs for SST Tasks\n    App::AO_Blinky3->setIRQ (14U);\n    App::AO_Button2b->setIRQ(16U);\n    App::AO_Button2a->setIRQ(18U);\n    App::AO_Blinky1->setIRQ (19U);\n#endif\n\n    // enable GPIO port PA clock\n    RCC->IOPENR |= (1U << 0U);\n\n    // set all used GPIOA pins as push-pull output, no pull-up, pull-down\n    GPIOA->MODER &=\n        ~((3U << 2U*TST1_PIN) | (3U << 2U*TST2_PIN) | (3U << 2U*TST3_PIN) |\n          (3U << 2U*TST4_PIN) | (3U << 2U*TST5_PIN) | (3U << 2U*TST6_PIN));\n    GPIOA->MODER |=\n         ((1U << 2U*TST1_PIN) | (1U << 2U*TST2_PIN) | (1U << 2U*TST3_PIN) |\n          (1U << 2U*TST4_PIN) | (1U << 2U*TST5_PIN) | (1U << 2U*TST6_PIN));\n    GPIOA->OTYPER &=\n        ~((1U <<    TST1_PIN) | (1U <<    TST2_PIN) | (1U <<    TST3_PIN) |\n          (1U <<    TST4_PIN) | (1U <<    TST5_PIN) | (1U <<    TST6_PIN));\n    GPIOA->PUPDR &=\n        ~((3U << 2U*TST1_PIN) | (3U << 2U*TST2_PIN) | (3U << 2U*TST3_PIN) |\n          (3U << 2U*TST4_PIN) | (3U << 2U*TST5_PIN) | (3U << 2U*TST6_PIN));\n\n    // enable GPIOC clock port for the Button B1\n    RCC->IOPENR |=  (1U << 2U);\n\n    // configure Button B1 pin on GPIOC as input, no pull-up, pull-down\n    GPIOC->MODER &= ~(3U << 2U*B1_PIN);\n    GPIOC->PUPDR &= ~(3U << 2U*B1_PIN);\n}\n//............................................................................\nvoid d1on(void)  { GPIOA->BSRR = (1U << TST1_PIN);         }\nvoid d1off(void) { GPIOA->BSRR = (1U << (TST1_PIN + 16U)); }\n//............................................................................\nvoid d2on(void)  { GPIOA->BSRR = (1U << TST2_PIN);         }\nvoid d2off(void) { GPIOA->BSRR = (1U << (TST2_PIN + 16U)); }\n//............................................................................\nvoid d3on(void)  { GPIOA->BSRR = (1U << TST3_PIN);         }\nvoid d3off(void) { GPIOA->BSRR = (1U << (TST3_PIN + 16U)); }\n//............................................................................\nvoid d4on(void)  { GPIOA->BSRR = (1U << TST4_PIN);         }\nvoid d4off(void) { GPIOA->BSRR = (1U << (TST4_PIN + 16U)); }\n//............................................................................\nvoid d5on(void)  { GPIOA->BSRR = (1U << TST5_PIN);         }\nvoid d5off(void) { GPIOA->BSRR = (1U << (TST5_PIN + 16U)); }\n//............................................................................\nvoid d6on(void)  { GPIOA->BSRR = (1U << TST6_PIN);         } // LED2\nvoid d6off(void) { GPIOA->BSRR = (1U << (TST6_PIN + 16U)); }\n\n//............................................................................\nSST::Evt const *getWorkEvtBlinky1(uint8_t num) {\n    // immutable work events for Blinky1\n    static App::BlinkyWorkEvt const workBlinky1[] = {\n        { { App::BLINKY_WORK_SIG }, 40U, 5U },\n        { { App::BLINKY_WORK_SIG }, 30U, 7U }\n    };\n    DBC_REQUIRE(500, num < ARRAY_NELEM(workBlinky1)); // num must be in range\n    return &workBlinky1[num].super;\n}\n//............................................................................\nSST::Evt const *getWorkEvtBlinky3(uint8_t num) {\n    // immutable work events for Blinky3\n    static App::BlinkyWorkEvt const workBlinky3[] = {\n        { { App::BLINKY_WORK_SIG }, 20U, 5U },\n        { { App::BLINKY_WORK_SIG }, 10U, 3U   }\n    };\n    DBC_REQUIRE(600, num < ARRAY_NELEM(workBlinky3)); // num must be in range\n    return &workBlinky3[num].super;\n}\n\n} // namespace BSP\n\n// SST callbacks =============================================================\nnamespace SST {\n\nvoid onStart(void) {\n    SystemCoreClockUpdate();\n\n    // set up the SysTick timer to fire at BSP::TICKS_PER_SEC rate\n    SysTick_Config((SystemCoreClock / BSP::TICKS_PER_SEC) + 1U);\n\n    // set priorities of ISRs used in the system\n    NVIC_SetPriority(SysTick_IRQn, 0U);\n    // ...\n}\n//............................................................................\nvoid onIdle(void) {\n    BSP::d6on();  // turn LED2 on\n#ifdef NDEBUG\n    // Put the CPU and peripherals to the low-power mode.\n    // you might need to customize the clock management for your application,\n    // see the datasheet for your particular Cortex-M MCU.\n    //\n    BSP::d6off(); // turn LED2 off\n    __WFI(); // Wait-For-Interrupt\n    BSP::d6on();  // turn LED2 on\n#endif\n    BSP::d6off(); // turn LED2 off\n}\n\n} // namespace SST\n\n"
  },
  {
    "path": "sst_cpp/examples/blinky_button/button2a.cpp",
    "content": "//============================================================================\n// Super-Simple Tasker (SST/C++) Example\n//\n// Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n//\n// SPDX-License-Identifier: MIT\n//\n// Permission is hereby granted, free of charge, to any person obtaining a\n// copy of this software and associated documentation files (the \"Software\"),\n// to deal in the Software without restriction, including without limitation\n// the rights to use, copy, modify, merge, publish, distribute, sublicense,\n// and/or sell copies of the Software, and to permit persons to whom the\n// Software is furnished to do so, subject to the following conditions:\n//\n// The above copyright notice and this permission notice shall be included in\n// all copies or substantial portions of the Software.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n// DEALINGS IN THE SOFTWARE.\n//============================================================================\n#include \"sst.hpp\"           // SST framework\n#include \"bsp.hpp\"           // Board Support Package interface\n#include \"blinky_button.hpp\" // application shared interface\n\nnamespace {\n\nDBC_MODULE_NAME(\"button2a\")  // for DBC assertions in this module\n\n} // unnamed namespace\n\nnamespace App {\n\n//............................................................................\nclass Button2a : public SST::Task {\n    // add internal variables for this AO...\n\npublic:\n    static Button2a inst;\n    void init(SST::Evt const * const ie) override;\n    void dispatch(SST::Evt const * const e) override;\n};\n\n//............................................................................\nButton2a Button2a::inst; // the Button2a instance\nSST::Task * const AO_Button2a = &Button2a::inst; // opaque AO pointer\n\n//............................................................................\nvoid Button2a::init(SST::Evt const * const /*ie*/) {\n}\n//............................................................................\nvoid Button2a::dispatch(SST::Evt const * const e) {\n    switch (e->sig) {\n        case BUTTON_PRESSED_SIG: {\n            BSP::d4on();\n            // Button2a --> Blinky1\n            AO_Blinky1->post(BSP::getWorkEvtBlinky1(1U));\n            BSP::d4off();\n\n            for (std::uint16_t i = SST::evt_downcast<ButtonWorkEvt>(e)->toggles;\n                 i > 0U; --i)\n            {\n                BSP::d4on();\n                BSP::d4off();\n            }\n            break;\n        }\n        case FORWARD_PRESSED_SIG: {\n            BSP::d4on();\n            // immutable event can be forwarded to another Task\n            AO_Button2b->post(e); // Button2a --> Button2b\n            BSP::d4off();\n            break;\n        }\n        case BUTTON_RELEASED_SIG: {\n            static BlinkyWorkEvt const bw2evt = {\n                { BLINKY_WORK_SIG }, 30U, 7U\n            };\n            AO_Blinky1->post(&bw2evt.super); // Button2b --> Blinky1\n\n            for (uint16_t i = SST::evt_downcast<ButtonWorkEvt>(e)->toggles;\n                 i > 0U; --i)\n            {\n                BSP::d4on();\n                BSP::d4off();\n            }\n            break;\n        }\n        case FORWARD_RELEASED_SIG: {\n            BSP::d4on();\n            // immutable event can be forwarded to another Task\n            AO_Button2b->post(e); // Button2a --> Button2b\n            BSP::d4off();\n            break;\n        }\n        default: {\n            DBC_ERROR(500); // unexpected event\n            break;\n        }\n    }\n}\n\n} // namespace App\n"
  },
  {
    "path": "sst_cpp/examples/blinky_button/button2b.cpp",
    "content": "//============================================================================\n// Super-Simple Tasker (SST/C++) Example\n//\n// Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n//\n// SPDX-License-Identifier: MIT\n//\n// Permission is hereby granted, free of charge, to any person obtaining a\n// copy of this software and associated documentation files (the \"Software\"),\n// to deal in the Software without restriction, including without limitation\n// the rights to use, copy, modify, merge, publish, distribute, sublicense,\n// and/or sell copies of the Software, and to permit persons to whom the\n// Software is furnished to do so, subject to the following conditions:\n//\n// The above copyright notice and this permission notice shall be included in\n// all copies or substantial portions of the Software.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n// DEALINGS IN THE SOFTWARE.\n//============================================================================\n#include \"sst.hpp\"           // SST framework\n#include \"bsp.hpp\"           // Board Support Package interface\n#include \"blinky_button.hpp\" // application shared interface\n\nnamespace {\n\nDBC_MODULE_NAME(\"button2b\")  // for DBC assertions in this module\n\n} // unnamed namespace\n\nnamespace App {\n\n//............................................................................\nclass Button2b : public SST::Task {\n    // add internal variables for this AO...\n\npublic:\n    static Button2b inst;\n    void init(SST::Evt const * const ie) override;\n    void dispatch(SST::Evt const * const e) override;\n};\n\n//............................................................................\nButton2b Button2b::inst; // the Button2b instance\nSST::Task * const AO_Button2b = &Button2b::inst; // opaque AO pointer\n\n//............................................................................\nvoid Button2b::init(SST::Evt const * const /*ie*/) {\n}\n//............................................................................\nvoid Button2b::dispatch(SST::Evt const * const e) {\n    switch (e->sig) {\n        case FORWARD_PRESSED_SIG: {\n            BSP::d3on();\n            // Button2b --> Blinky3\n            AO_Blinky3->post(BSP::getWorkEvtBlinky3(1U));\n            BSP::d3off();\n\n            for (std::uint16_t i = SST::evt_downcast<ButtonWorkEvt>(e)->toggles;\n                 i > 0U; --i)\n            {\n                BSP::d3on();\n                BSP::d3off();\n            }\n            break;\n        }\n        case FORWARD_RELEASED_SIG: {\n            BSP::d3on();\n            // Button2b --> Blinky3\n            AO_Blinky3->post(BSP::getWorkEvtBlinky3(0U));\n            BSP::d3off();\n\n            for (uint16_t i = SST::evt_downcast<ButtonWorkEvt>(e)->toggles;\n                 i > 0U; --i)\n            {\n                BSP::d3on();\n                BSP::d3off();\n            }\n            break;\n        }\n        default: {\n            DBC_ERROR(500); /* unexpected event */\n            break;\n        }\n    }\n}\n\n} // namespace App\n"
  },
  {
    "path": "sst_cpp/examples/blinky_button/gnu/ek-tm4c123gxl.mak",
    "content": "##############################################################################\n# Makefile for Super-Simple Tasker (SST/C++) on TM4C123GXL, GNU-ARM\n# Last Updated for Version: 2.0.0\n# Date of the Last Update:  2023-01-25\n#\n#                    Q u a n t u m  L e a P s\n#                    ------------------------\n#                    Modern Embedded Software\n#\n# Copyright (C) 2005 Quantum Leaps, LLC. All rights reserved.\n#\n# SPDX-License-Identifier: MIT\n#\n# Permission is hereby granted, free of charge, to any person obtaining a copy\n# of this software and associated documentation files (the \"Software\"), to\n# deal in the Software without restriction, including without limitation the\n# rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n# sell copies of the Software, and to permit persons to whom the Software is\n# furnished to do so, subject to the following conditions:\n#\n# The above copyright notice and this permission notice shall be included in\n# all copies or substantial portions of the Software.\n#\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS\n# IN THE SOFTWARE.\n##############################################################################\n# examples of invoking this Makefile:\n# make -f ek-tm4c123gxl.mak\n# make -f ek-tm4c123gxl.mak clean\n#\n# NOTE:\n# To use this Makefile on Windows, you will need the GNU make utility, which\n# is included in the QTools collection for Windows, see:\n#    https://github.com/QuantumLeaps/qtools\n#\n\n#-----------------------------------------------------------------------------\n# project and target names\n#\nPROJECT := blinky_button\nTARGET  := ek-tm4c123gxl\n\n#-----------------------------------------------------------------------------\n# project directories\n#\nSST_DIR      := ../../..\nSST_PORT_DIR := $(SST_DIR)/ports/arm-cm\nCMSIS_DIR    := ../../../../3rd_party/CMSIS\nTARGET_DIR   := ../../../../3rd_party/$(TARGET)\n\n# list of all source directories used by this project\nVPATH = .. \\\n\t$(SST_DIR)/src \\\n\t$(SST_PORT_DIR) \\\n\t$(TARGET_DIR) \\\n\t$(TARGET_DIR)/gnu \\\n\n# list of all include directories needed by this project\nINCLUDES  = -I. \\\n\t-I$(SST_DIR)/../include \\\n\t-I$(SST_PORT_DIR) \\\n\t-I$(CMSIS_DIR)/Include \\\n\t-I$(TARGET_DIR)\n\n#-----------------------------------------------------------------------------\n# project files\n#\n\n# assembler source files\nASM_SRCS :=\n\n# C source files\nC_SRCS := \\\n\tsystem_TM4C123GH6PM.c \\\n\tstartup_TM4C123GH6PM.c\n\n# C++ source files\nCPP_SRCS := \\\n\tsst.cpp \\\n\tsst_port.cpp \\\n\tmain.cpp \\\n\tblinky1.cpp \\\n\tblinky3.cpp \\\n\tbutton2a.cpp \\\n\tbutton2b.cpp \\\n\tbsp_ek-tm4c123gxl.cpp\n\nLD_SCRIPT  := $(TARGET_DIR)/gnu/$(TARGET).ld\n\nOUTPUT    := $(PROJECT)\n\nLIB_DIRS  :=\nLIBS      :=\n\n# defines\nDEFINES   := -DTARGET_IS_TM4C123_RB1\n\n# ARM CPU, ARCH, FPU, and Float-ABI types...\n# ARM_CPU:   [cortex-m0 | cortex-m0plus | cortex-m1 | cortex-m3 | cortex-m4]\n# ARM_FPU:   [ | vfp]\n# FLOAT_ABI: [ | soft | softfp | hard]\n#\nARM_CPU   := -mcpu=cortex-m4\nARM_FPU   := -mfpu=vfp\nFLOAT_ABI := -mfloat-abi=softfp\n\n#-----------------------------------------------------------------------------\n# GNU-ARM toolset (NOTE: You need to adjust to your machine)\n# see https://developer.arm.com/open-source/gnu-toolchain/gnu-rm/downloads\n#\nifeq ($(GNU_ARM),)\nGNU_ARM := $(QTOOLS)/gnu_arm-none-eabi\nendif\n\n# make sure that the GNU-ARM toolset exists...\nifeq (\"$(wildcard $(GNU_ARM))\",\"\")\n$(error GNU_ARM toolset not found. Please adjust the Makefile)\nendif\n\nCC    := $(GNU_ARM)/bin/arm-none-eabi-gcc\nCPP   := $(GNU_ARM)/bin/arm-none-eabi-g++\nAS    := $(GNU_ARM)/bin/arm-none-eabi-as\nLINK  := $(GNU_ARM)/bin/arm-none-eabi-g++\nBIN   := $(GNU_ARM)/bin/arm-none-eabi-objcopy\n\n##############################################################################\n# Typically you should not need to change anything below this line\n\n# basic utilities (included in QTools for Windows), see:\n#     https://www.state-machine.com/qtools\n\nMKDIR := mkdir\nRM    := rm\n\n#-----------------------------------------------------------------------------\n# build options\n#\n\n# combine all the soruces...\nC_SRCS += $(QP_SRCS)\nASM_SRCS += $(QP_ASMS)\n\nBIN_DIR := build_$(TARGET)\n\nASFLAGS = -g $(ARM_CPU) $(ARM_FPU) $(ASM_CPU) $(ASM_FPU)\n\nCFLAGS = -c -g $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -std=c99 -mthumb -Wall \\\n\t-ffunction-sections -fdata-sections \\\n\t-O $(INCLUDES) $(DEFINES)\n\nCPPFLAGS = -c -g $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -std=c++11 -mthumb -Wall \\\n\t-ffunction-sections -fdata-sections -fno-rtti -fno-exceptions \\\n\t-O $(INCLUDES) $(DEFINES)\n\nLINKFLAGS = -T$(LD_SCRIPT) $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -mthumb \\\n\t-specs=nosys.specs -specs=nano.specs \\\n\t-Wl,-Map,$(BIN_DIR)/$(OUTPUT).map,--cref,--gc-sections $(LIB_DIRS)\n\nASM_OBJS     := $(patsubst %.s,%.o,  $(notdir $(ASM_SRCS)))\nC_OBJS       := $(patsubst %.c,%.o,  $(notdir $(C_SRCS)))\nCPP_OBJS     := $(patsubst %.cpp,%.o,$(notdir $(CPP_SRCS)))\n\nTARGET_BIN   := $(BIN_DIR)/$(OUTPUT).bin\nTARGET_ELF   := $(BIN_DIR)/$(OUTPUT).elf\nASM_OBJS_EXT := $(addprefix $(BIN_DIR)/, $(ASM_OBJS))\nC_OBJS_EXT   := $(addprefix $(BIN_DIR)/, $(C_OBJS))\nC_DEPS_EXT   := $(patsubst %.o, %.d, $(C_OBJS_EXT))\nCPP_OBJS_EXT := $(addprefix $(BIN_DIR)/, $(CPP_OBJS))\nCPP_DEPS_EXT := $(patsubst %.o, %.d, $(CPP_OBJS_EXT))\n\n# create $(BIN_DIR) if it does not exist\nifeq (\"$(wildcard $(BIN_DIR))\",\"\")\n$(shell $(MKDIR) $(BIN_DIR))\nendif\n\n#-----------------------------------------------------------------------------\n# rules\n#\n\n.PHONY : run norun flash\n\nifeq ($(MAKECMDGOALS),norun)\nall : $(TARGET_BIN)\nnorun : all\nelse\nall : $(TARGET_BIN) run\nendif\n\n$(TARGET_BIN): $(TARGET_ELF)\n\t$(BIN) -O binary $< $@\n\n$(TARGET_ELF) : $(ASM_OBJS_EXT) $(C_OBJS_EXT) $(CPP_OBJS_EXT)\n\t$(LINK) $(LINKFLAGS) -o $@ $^ $(LIBS)\n\n$(BIN_DIR)/%.d : %.c\n\t$(CC) -MM -MT $(@:.d=.o) $(CFLAGS) $< > $@\n\n$(BIN_DIR)/%.d : %.cpp\n\t$(CPP) -MM -MT $(@:.d=.o) $(CPPFLAGS) $< > $@\n\n$(BIN_DIR)/%.o : %.s\n\t$(AS) $(ASFLAGS) $< -o $@\n\n$(BIN_DIR)/%.o : %.c\n\t$(CC) $(CFLAGS) $< -o $@\n\n$(BIN_DIR)/%.o : %.cpp\n\t$(CPP) $(CPPFLAGS) $< -o $@\n\n.PHONY : clean show\n\n# include dependency files only if our goal depends on their existence\nifneq ($(MAKECMDGOALS),clean)\n  ifneq ($(MAKECMDGOALS),show)\n-include $(C_DEPS_EXT) $(CPP_DEPS_EXT)\n  endif\nendif\n\n\nclean :\n\t-$(RM) $(BIN_DIR)/*.o \\\n\t$(BIN_DIR)/*.d \\\n\t$(BIN_DIR)/*.bin \\\n\t$(BIN_DIR)/*.elf \\\n\t$(BIN_DIR)/*.map\n\t\nshow:\n\t@echo PROJECT = $(PROJECT)\n\t@echo CONF = $(CONF)\n\t@echo DEFINES = $(DEFINES)\n\t@echo ASM_FPU = $(ASM_FPU)\n\t@echo ASM_SRCS = $(ASM_SRCS)\n\t@echo C_SRCS = $(C_SRCS)\n\t@echo CPP_SRCS = $(CPP_SRCS)\n\t@echo ASM_OBJS_EXT = $(ASM_OBJS_EXT)\n\t@echo C_OBJS_EXT = $(C_OBJS_EXT)\n\t@echo C_DEPS_EXT = $(C_DEPS_EXT)\n\t@echo CPP_DEPS_EXT = $(CPP_DEPS_EXT)\n\t@echo TARGET_ELF = $(TARGET_ELF)\n"
  },
  {
    "path": "sst_cpp/examples/blinky_button/gnu/flash_ek-tm4c123gxl.bat",
    "content": "::============================================================================\n:: Batch file to program the flash of EK-TM4C123GXL\n::\n:: NOTE: requires the LMFlash programmer (included in QTools for Windows)\n::\n@echo off\nsetlocal\n\n@echo Load a given binary file to the flash of EK-TM4C123GXL\n@echo usage:   flash binary-file\n@echo example: flash dbg\\blinky-qk.bin\n\n::----------------------------------------------------------------------------\n:: NOTE: The following symbol LMFLASH assumes that LMFlash.exe can\n:: be found on the PATH. You might need to adjust this symbol to the\n:: location of the LMFlash utility on your machine\n::\nset LMFLASH=LMFlash.exe\n\nif [\"%~1\"]==[\"\"] (\n    @echo The binary file missing\n    @goto end\n)\nif not exist %~s1 (\n    @echo The binary file '%1' does not exist\n    @goto end\n)\n\n%LMFLASH% -q ek-tm4c123gxl -e -v -r %1\n\n:end\n\nendlocal"
  },
  {
    "path": "sst_cpp/examples/blinky_button/gnu/nucleo-c031c6.mak",
    "content": "##############################################################################\n# Makefile for Super-Simple Tasker (SST/C) on NUCLEO-C031C6, GNU-ARM\n# Last Updated for Version: 2.0.0\n# Date of the Last Update:  2023-02-01\n#\n#                    Q u a n t u m  L e a P s\n#                    ------------------------\n#                    Modern Embedded Software\n#\n# Copyright (C) 2005 Quantum Leaps, LLC. All rights reserved.\n#\n# SPDX-License-Identifier: MIT\n#\n# Permission is hereby granted, free of charge, to any person obtaining a copy\n# of this software and associated documentation files (the \"Software\"), to\n# deal in the Software without restriction, including without limitation the\n# rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n# sell copies of the Software, and to permit persons to whom the Software is\n# furnished to do so, subject to the following conditions:\n#\n# The above copyright notice and this permission notice shall be included in\n# all copies or substantial portions of the Software.\n#\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS\n# IN THE SOFTWARE.\n##############################################################################\n# examples of invoking this Makefile:\n# make -f nucleo-c031c6.mak\n# make -f nucleo-c031c6.mak clean\n#\n# NOTE:\n# To use this Makefile on Windows, you will need the GNU make utility, which\n# is included in the QTools collection for Windows, see:\n#    https://github.com/QuantumLeaps/qtools\n#\n\n#-----------------------------------------------------------------------------\n# project and target names\n#\nPROJECT := blinky_button\nTARGET  := nucleo-c031c6\n\n#-----------------------------------------------------------------------------\n# project directories\n#\nSST_DIR      := ../../..\nSST_PORT_DIR := $(SST_DIR)/ports/arm-cm\nCMSIS_DIR    := ../../../../3rd_party/CMSIS\nTARGET_DIR   := ../../../../3rd_party/$(TARGET)\n\n# list of all source directories used by this project\nVPATH = .. \\\n\t$(SST_DIR)/src \\\n\t$(SST_PORT_DIR) \\\n\t$(TARGET_DIR) \\\n\t$(TARGET_DIR)/gnu \\\n\n# list of all include directories needed by this project\nINCLUDES  = -I. \\\n\t-I$(SST_DIR)/../include \\\n\t-I$(SST_PORT_DIR) \\\n\t-I$(CMSIS_DIR)/Include \\\n\t-I$(TARGET_DIR)\n\n#-----------------------------------------------------------------------------\n# project files\n#\n\n# assembler source files\nASM_SRCS :=\n\n# C source files\nC_SRCS := \\\n\tsystem_stm32c0xx.c \\\n\tstartup_stm32c031xx.c\n\n# C++ source files\nCPP_SRCS := \\\n\tsst.cpp \\\n\tsst_port.cpp \\\n\tmain.cpp \\\n\tblinky1.cpp \\\n\tblinky3.cpp \\\n\tbutton2a.cpp \\\n\tbutton2b.cpp \\\n\tbsp_nucleo-c031c6.cpp\n\nLD_SCRIPT  := $(TARGET_DIR)/gnu/$(TARGET).ld\n\nOUTPUT    := $(PROJECT)\n\nLIB_DIRS  :=\nLIBS      :=\n\n# defines\nDEFINES   := -DSTM32C031xx\n\n# ARM CPU, ARCH, FPU, and Float-ABI types...\n# ARM_CPU:   [cortex-m0 | cortex-m0plus | cortex-m1 | cortex-m3 | cortex-m4]\n# ARM_FPU:   [ | vfp]\n# FLOAT_ABI: [ | soft | softfp | hard]\n#\nARM_CPU   := -mcpu=cortex-m0plus\nARM_FPU   :=\nFLOAT_ABI :=\n\n#-----------------------------------------------------------------------------\n# GNU-ARM toolset (NOTE: You need to adjust to your machine)\n# see https://developer.arm.com/open-source/gnu-toolchain/gnu-rm/downloads\n#\nifeq ($(GNU_ARM),)\nGNU_ARM := $(QTOOLS)/gnu_arm-none-eabi\nendif\n\n# make sure that the GNU-ARM toolset exists...\nifeq (\"$(wildcard $(GNU_ARM))\",\"\")\n$(error GNU_ARM toolset not found. Please adjust the Makefile)\nendif\n\nCC    := $(GNU_ARM)/bin/arm-none-eabi-gcc\nCPP   := $(GNU_ARM)/bin/arm-none-eabi-g++\nAS    := $(GNU_ARM)/bin/arm-none-eabi-as\nLINK  := $(GNU_ARM)/bin/arm-none-eabi-g++\nBIN   := $(GNU_ARM)/bin/arm-none-eabi-objcopy\n\n##############################################################################\n# Typically you should not need to change anything below this line\n\n# basic utilities (included in QTools for Windows), see:\n#     https://www.state-machine.com/qtools\n\nMKDIR := mkdir\nRM    := rm\n\n#-----------------------------------------------------------------------------\n# build options\n#\n\n# combine all the soruces...\nC_SRCS += $(QP_SRCS)\nASM_SRCS += $(QP_ASMS)\n\nBIN_DIR := build_$(TARGET)\n\nASFLAGS = -g $(ARM_CPU) $(ARM_FPU) $(ASM_CPU) $(ASM_FPU)\n\nCFLAGS = -c -g $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -std=c99 -mthumb -Wall \\\n\t-ffunction-sections -fdata-sections \\\n\t-O $(INCLUDES) $(DEFINES)\n\nCPPFLAGS = -c -g $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -std=c++11 -mthumb -Wall \\\n\t-ffunction-sections -fdata-sections -fno-rtti -fno-exceptions \\\n\t-O $(INCLUDES) $(DEFINES)\n\nLINKFLAGS = -T$(LD_SCRIPT) $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -mthumb \\\n\t-specs=nosys.specs -specs=nano.specs \\\n\t-Wl,-Map,$(BIN_DIR)/$(OUTPUT).map,--cref,--gc-sections $(LIB_DIRS)\n\nASM_OBJS     := $(patsubst %.s,%.o,  $(notdir $(ASM_SRCS)))\nC_OBJS       := $(patsubst %.c,%.o,  $(notdir $(C_SRCS)))\nCPP_OBJS     := $(patsubst %.cpp,%.o,$(notdir $(CPP_SRCS)))\n\nTARGET_BIN   := $(BIN_DIR)/$(OUTPUT).bin\nTARGET_ELF   := $(BIN_DIR)/$(OUTPUT).elf\nASM_OBJS_EXT := $(addprefix $(BIN_DIR)/, $(ASM_OBJS))\nC_OBJS_EXT   := $(addprefix $(BIN_DIR)/, $(C_OBJS))\nC_DEPS_EXT   := $(patsubst %.o, %.d, $(C_OBJS_EXT))\nCPP_OBJS_EXT := $(addprefix $(BIN_DIR)/, $(CPP_OBJS))\nCPP_DEPS_EXT := $(patsubst %.o, %.d, $(CPP_OBJS_EXT))\n\n# create $(BIN_DIR) if it does not exist\nifeq (\"$(wildcard $(BIN_DIR))\",\"\")\n$(shell $(MKDIR) $(BIN_DIR))\nendif\n\n#-----------------------------------------------------------------------------\n# rules\n#\n\n.PHONY : run norun flash\n\nifeq ($(MAKECMDGOALS),norun)\nall : $(TARGET_BIN)\nnorun : all\nelse\nall : $(TARGET_BIN) run\nendif\n\n$(TARGET_BIN): $(TARGET_ELF)\n\t$(BIN) -O binary $< $@\n\n$(TARGET_ELF) : $(ASM_OBJS_EXT) $(C_OBJS_EXT) $(CPP_OBJS_EXT)\n\t$(LINK) $(LINKFLAGS) -o $@ $^ $(LIBS)\n\n$(BIN_DIR)/%.d : %.c\n\t$(CC) -MM -MT $(@:.d=.o) $(CFLAGS) $< > $@\n\n$(BIN_DIR)/%.d : %.cpp\n\t$(CPP) -MM -MT $(@:.d=.o) $(CPPFLAGS) $< > $@\n\n$(BIN_DIR)/%.o : %.s\n\t$(AS) $(ASFLAGS) $< -o $@\n\n$(BIN_DIR)/%.o : %.c\n\t$(CC) $(CFLAGS) $< -o $@\n\n$(BIN_DIR)/%.o : %.cpp\n\t$(CPP) $(CPPFLAGS) $< -o $@\n\n.PHONY : clean show\n\n# include dependency files only if our goal depends on their existence\nifneq ($(MAKECMDGOALS),clean)\n  ifneq ($(MAKECMDGOALS),show)\n-include $(C_DEPS_EXT) $(CPP_DEPS_EXT)\n  endif\nendif\n\n\nclean :\n\t-$(RM) $(BIN_DIR)/*.o \\\n\t$(BIN_DIR)/*.d \\\n\t$(BIN_DIR)/*.bin \\\n\t$(BIN_DIR)/*.elf \\\n\t$(BIN_DIR)/*.map\n\t\nshow:\n\t@echo PROJECT = $(PROJECT)\n\t@echo CONF = $(CONF)\n\t@echo DEFINES = $(DEFINES)\n\t@echo ASM_FPU = $(ASM_FPU)\n\t@echo ASM_SRCS = $(ASM_SRCS)\n\t@echo C_SRCS = $(C_SRCS)\n\t@echo CPP_SRCS = $(CPP_SRCS)\n\t@echo ASM_OBJS_EXT = $(ASM_OBJS_EXT)\n\t@echo C_OBJS_EXT = $(C_OBJS_EXT)\n\t@echo C_DEPS_EXT = $(C_DEPS_EXT)\n\t@echo CPP_DEPS_EXT = $(CPP_DEPS_EXT)\n\t@echo TARGET_ELF = $(TARGET_ELF)\n"
  },
  {
    "path": "sst_cpp/examples/blinky_button/gnu/nucleo-h743zi.mak",
    "content": "##############################################################################\n# Makefile for Super-Simple Tasker (SST/C++) on NUCLEO-H743ZI, GNU-ARM\n# Last Updated for Version: 2.0.0\n# Date of the Last Update:  2023-01-22\n#\n#                    Q u a n t u m  L e a P s\n#                    ------------------------\n#                    Modern Embedded Software\n#\n# Copyright (C) 2005 Quantum Leaps, LLC. All rights reserved.\n#\n# SPDX-License-Identifier: MIT\n#\n# Permission is hereby granted, free of charge, to any person obtaining a copy\n# of this software and associated documentation files (the \"Software\"), to\n# deal in the Software without restriction, including without limitation the\n# rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n# sell copies of the Software, and to permit persons to whom the Software is\n# furnished to do so, subject to the following conditions:\n#\n# The above copyright notice and this permission notice shall be included in\n# all copies or substantial portions of the Software.\n#\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS\n# IN THE SOFTWARE.\n##############################################################################\n# examples of invoking this Makefile:\n# make -f nucleo-h743zi.mak\n# make -f nucleo-h743zi.mak clean\n#\n# NOTE:\n# To use this Makefile on Windows, you will need the GNU make utility, which\n# is included in the QTools collection for Windows, see:\n#    https://github.com/QuantumLeaps/qtools\n#\n\n#-----------------------------------------------------------------------------\n# project and target names\n#\nPROJECT := blinky_button\nTARGET  := nucleo-h743zi\n\n#-----------------------------------------------------------------------------\n# project directories\n#\nSST_DIR      := ../../..\nSST_PORT_DIR := $(SST_DIR)/ports/arm-cm\nCMSIS_DIR    := ../../../../3rd_party/CMSIS\nTARGET_DIR   := ../../../../3rd_party/$(TARGET)\n\n# list of all source directories used by this project\nVPATH = .. \\\n\t$(SST_DIR)/src \\\n\t$(SST_PORT_DIR) \\\n\t$(TARGET_DIR) \\\n\t$(TARGET_DIR)/gnu \\\n\n# list of all include directories needed by this project\nINCLUDES  = -I. \\\n\t-I$(SST_DIR)/../include \\\n\t-I$(SST_PORT_DIR) \\\n\t-I$(CMSIS_DIR)/Include \\\n\t-I$(TARGET_DIR)\n\n#-----------------------------------------------------------------------------\n# project files\n#\n\n# assembler source files\nASM_SRCS :=\n\n# C source files\nC_SRCS := \\\n\tstartup_stm32h743xx.c \\\n\tsystem_stm32h7xx.c\n\n# C++ source files\nCPP_SRCS := \\\n\tsst.cpp \\\n\tsst_port.cpp \\\n\tmain.cpp \\\n\tblinky1.cpp \\\n\tblinky3.cpp \\\n\tbutton2a.cpp \\\n\tbutton2b.cpp \\\n\tbsp_nucleo-h743zi.cpp\n\nLD_SCRIPT  := $(TARGET_DIR)/gnu/$(TARGET).ld\n\nOUTPUT    := $(PROJECT)\n\nLIB_DIRS  :=\nLIBS      :=\n\n# defines\nDEFINES   := -DSTM32H743xx\n\n# ARM CPU, ARCH, FPU, and Float-ABI types...\n# ARM_CPU:   [cortex-m0 | cortex-m0plus | cortex-m1 | cortex-m3 | cortex-m4]\n# ARM_FPU:   [ | vfp]\n# FLOAT_ABI: [ | soft | softfp | hard]\n#\nARM_CPU   := -mcpu=cortex-m7\nARM_FPU   := -mfpu=fpv5-d16\nFLOAT_ABI := -mfloat-abi=softfp\n\n#-----------------------------------------------------------------------------\n# GNU-ARM toolset (NOTE: You need to adjust to your machine)\n# see https://developer.arm.com/open-source/gnu-toolchain/gnu-rm/downloads\n#\nifeq ($(GNU_ARM),)\nGNU_ARM := $(QTOOLS)/gnu_arm-none-eabi\nendif\n\n# make sure that the GNU-ARM toolset exists...\nifeq (\"$(wildcard $(GNU_ARM))\",\"\")\n$(error GNU_ARM toolset not found. Please adjust the Makefile)\nendif\n\nCC    := $(GNU_ARM)/bin/arm-none-eabi-gcc\nCPP   := $(GNU_ARM)/bin/arm-none-eabi-g++\nAS    := $(GNU_ARM)/bin/arm-none-eabi-as\nLINK  := $(GNU_ARM)/bin/arm-none-eabi-g++\nBIN   := $(GNU_ARM)/bin/arm-none-eabi-objcopy\n\n##############################################################################\n# Typically you should not need to change anything below this line\n\n# basic utilities (included in QTools for Windows), see:\n#     https://www.state-machine.com/qtools\n\nMKDIR := mkdir\nRM    := rm\n\n#-----------------------------------------------------------------------------\n# build options\n#\n\n# combine all the soruces...\nC_SRCS += $(QP_SRCS)\nASM_SRCS += $(QP_ASMS)\n\nBIN_DIR := build_$(TARGET)\n\nASFLAGS = -g $(ARM_CPU) $(ARM_FPU) $(ASM_CPU) $(ASM_FPU)\n\nCFLAGS = -c -g $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -std=c99 -mthumb -Wall \\\n\t-ffunction-sections -fdata-sections \\\n\t-O $(INCLUDES) $(DEFINES)\n\nCPPFLAGS = -c -g $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -std=c++11 -mthumb -Wall \\\n\t-ffunction-sections -fdata-sections -fno-rtti -fno-exceptions \\\n\t-O $(INCLUDES) $(DEFINES)\n\nLINKFLAGS = -T$(LD_SCRIPT) $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -mthumb \\\n\t-specs=nosys.specs -specs=nano.specs \\\n\t-Wl,-Map,$(BIN_DIR)/$(OUTPUT).map,--cref,--gc-sections $(LIB_DIRS)\n\nASM_OBJS     := $(patsubst %.s,%.o,  $(notdir $(ASM_SRCS)))\nC_OBJS       := $(patsubst %.c,%.o,  $(notdir $(C_SRCS)))\nCPP_OBJS     := $(patsubst %.cpp,%.o,$(notdir $(CPP_SRCS)))\n\nTARGET_BIN   := $(BIN_DIR)/$(OUTPUT).bin\nTARGET_ELF   := $(BIN_DIR)/$(OUTPUT).elf\nASM_OBJS_EXT := $(addprefix $(BIN_DIR)/, $(ASM_OBJS))\nC_OBJS_EXT   := $(addprefix $(BIN_DIR)/, $(C_OBJS))\nC_DEPS_EXT   := $(patsubst %.o, %.d, $(C_OBJS_EXT))\nCPP_OBJS_EXT := $(addprefix $(BIN_DIR)/, $(CPP_OBJS))\nCPP_DEPS_EXT := $(patsubst %.o, %.d, $(CPP_OBJS_EXT))\n\n# create $(BIN_DIR) if it does not exist\nifeq (\"$(wildcard $(BIN_DIR))\",\"\")\n$(shell $(MKDIR) $(BIN_DIR))\nendif\n\n#-----------------------------------------------------------------------------\n# rules\n#\n\n.PHONY : run norun flash\n\nifeq ($(MAKECMDGOALS),norun)\nall : $(TARGET_BIN)\nnorun : all\nelse\nall : $(TARGET_BIN) run\nendif\n\n$(TARGET_BIN): $(TARGET_ELF)\n\t$(BIN) -O binary $< $@\n\n$(TARGET_ELF) : $(ASM_OBJS_EXT) $(C_OBJS_EXT) $(CPP_OBJS_EXT)\n\t$(LINK) $(LINKFLAGS) -o $@ $^ $(LIBS)\n\n$(BIN_DIR)/%.d : %.c\n\t$(CC) -MM -MT $(@:.d=.o) $(CFLAGS) $< > $@\n\n$(BIN_DIR)/%.d : %.cpp\n\t$(CPP) -MM -MT $(@:.d=.o) $(CPPFLAGS) $< > $@\n\n$(BIN_DIR)/%.o : %.s\n\t$(AS) $(ASFLAGS) $< -o $@\n\n$(BIN_DIR)/%.o : %.c\n\t$(CC) $(CFLAGS) $< -o $@\n\n$(BIN_DIR)/%.o : %.cpp\n\t$(CPP) $(CPPFLAGS) $< -o $@\n\n.PHONY : clean show\n\n# include dependency files only if our goal depends on their existence\nifneq ($(MAKECMDGOALS),clean)\n  ifneq ($(MAKECMDGOALS),show)\n-include $(C_DEPS_EXT) $(CPP_DEPS_EXT)\n  endif\nendif\n\n\nclean :\n\t-$(RM) $(BIN_DIR)/*.o \\\n\t$(BIN_DIR)/*.d \\\n\t$(BIN_DIR)/*.bin \\\n\t$(BIN_DIR)/*.elf \\\n\t$(BIN_DIR)/*.map\n\t\nshow:\n\t@echo PROJECT = $(PROJECT)\n\t@echo CONF = $(CONF)\n\t@echo DEFINES = $(DEFINES)\n\t@echo ASM_FPU = $(ASM_FPU)\n\t@echo ASM_SRCS = $(ASM_SRCS)\n\t@echo C_SRCS = $(C_SRCS)\n\t@echo CPP_SRCS = $(CPP_SRCS)\n\t@echo ASM_OBJS_EXT = $(ASM_OBJS_EXT)\n\t@echo C_OBJS_EXT = $(C_OBJS_EXT)\n\t@echo C_DEPS_EXT = $(C_DEPS_EXT)\n\t@echo CPP_DEPS_EXT = $(CPP_DEPS_EXT)\n\t@echo TARGET_ELF = $(TARGET_ELF)\n"
  },
  {
    "path": "sst_cpp/examples/blinky_button/gnu/nucleo-l053r8.mak",
    "content": "##############################################################################\n# Makefile for Super-Simple Tasker (SST/C++) on NUCLEO-L053R8, GNU-ARM\n# Last Updated for Version: 2.0.0\n# Date of the Last Update:  2023-01-22\n#\n#                    Q u a n t u m  L e a P s\n#                    ------------------------\n#                    Modern Embedded Software\n#\n# Copyright (C) 2005 Quantum Leaps, LLC. All rights reserved.\n#\n# SPDX-License-Identifier: MIT\n#\n# Permission is hereby granted, free of charge, to any person obtaining a copy\n# of this software and associated documentation files (the \"Software\"), to\n# deal in the Software without restriction, including without limitation the\n# rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n# sell copies of the Software, and to permit persons to whom the Software is\n# furnished to do so, subject to the following conditions:\n#\n# The above copyright notice and this permission notice shall be included in\n# all copies or substantial portions of the Software.\n#\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS\n# IN THE SOFTWARE.\n##############################################################################\n# examples of invoking this Makefile:\n# make -f nucleo-l053r8.mak\n# make -f nucleo-l053r8.mak clean\n#\n# NOTE:\n# To use this Makefile on Windows, you will need the GNU make utility, which\n# is included in the QTools collection for Windows, see:\n#    https://github.com/QuantumLeaps/qtools\n#\n\n#-----------------------------------------------------------------------------\n# project and target names\n#\nPROJECT := blinky_button\nTARGET  := nucleo-l053r8\n\n#-----------------------------------------------------------------------------\n# project directories\n#\nSST_DIR      := ../../..\nSST_PORT_DIR := $(SST_DIR)/ports/arm-cm\nCMSIS_DIR    := ../../../../3rd_party/CMSIS\nTARGET_DIR   := ../../../../3rd_party/$(TARGET)\n\n# list of all source directories used by this project\nVPATH = .. \\\n\t$(SST_DIR)/src \\\n\t$(SST_PORT_DIR) \\\n\t$(TARGET_DIR) \\\n\t$(TARGET_DIR)/gnu \\\n\n# list of all include directories needed by this project\nINCLUDES  = -I. \\\n\t-I$(SST_DIR)/../include \\\n\t-I$(SST_PORT_DIR) \\\n\t-I$(CMSIS_DIR)/Include \\\n\t-I$(TARGET_DIR)\n\n#-----------------------------------------------------------------------------\n# project files\n#\n\n# assembler source files\nASM_SRCS :=\n\n# C source files\nC_SRCS := \\\n\tsystem_stm32l0xx.c \\\n\tstartup_stm32l053xx.c\n\n# C++ source files\nCPP_SRCS := \\\n\tsst.cpp \\\n\tsst_port.cpp \\\n\tmain.cpp \\\n\tblinky1.cpp \\\n\tblinky3.cpp \\\n\tbutton2a.cpp \\\n\tbutton2b.cpp \\\n\tbsp_nucleo-l053r8.cpp\n\nLD_SCRIPT  := $(TARGET_DIR)/gnu/$(TARGET).ld\n\nOUTPUT    := $(PROJECT)\n\nLIB_DIRS  :=\nLIBS      :=\n\n# defines\nDEFINES   :=\n\n# ARM CPU, ARCH, FPU, and Float-ABI types...\n# ARM_CPU:   [cortex-m0 | cortex-m0plus | cortex-m1 | cortex-m3 | cortex-m4]\n# ARM_FPU:   [ | vfp]\n# FLOAT_ABI: [ | soft | softfp | hard]\n#\nARM_CPU   := -mcpu=cortex-m0plus\nARM_FPU   :=\nFLOAT_ABI :=\n\n#-----------------------------------------------------------------------------\n# GNU-ARM toolset (NOTE: You need to adjust to your machine)\n# see https://developer.arm.com/open-source/gnu-toolchain/gnu-rm/downloads\n#\nifeq ($(GNU_ARM),)\nGNU_ARM := $(QTOOLS)/gnu_arm-none-eabi\nendif\n\n# make sure that the GNU-ARM toolset exists...\nifeq (\"$(wildcard $(GNU_ARM))\",\"\")\n$(error GNU_ARM toolset not found. Please adjust the Makefile)\nendif\n\nCC    := $(GNU_ARM)/bin/arm-none-eabi-gcc\nCPP   := $(GNU_ARM)/bin/arm-none-eabi-g++\nAS    := $(GNU_ARM)/bin/arm-none-eabi-as\nLINK  := $(GNU_ARM)/bin/arm-none-eabi-g++\nBIN   := $(GNU_ARM)/bin/arm-none-eabi-objcopy\n\n##############################################################################\n# Typically you should not need to change anything below this line\n\n# basic utilities (included in QTools for Windows), see:\n#     https://www.state-machine.com/qtools\n\nMKDIR := mkdir\nRM    := rm\n\n#-----------------------------------------------------------------------------\n# build options\n#\n\n# combine all the soruces...\nC_SRCS += $(QP_SRCS)\nASM_SRCS += $(QP_ASMS)\n\nBIN_DIR := build_$(TARGET)\n\nASFLAGS = -g $(ARM_CPU) $(ARM_FPU) $(ASM_CPU) $(ASM_FPU)\n\nCFLAGS = -c -g $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -std=c99 -mthumb -Wall \\\n\t-ffunction-sections -fdata-sections \\\n\t-O $(INCLUDES) $(DEFINES)\n\nCPPFLAGS = -c -g $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -std=c++11 -mthumb -Wall \\\n\t-ffunction-sections -fdata-sections -fno-rtti -fno-exceptions \\\n\t-O $(INCLUDES) $(DEFINES)\n\nLINKFLAGS = -T$(LD_SCRIPT) $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -mthumb \\\n\t-specs=nosys.specs -specs=nano.specs \\\n\t-Wl,-Map,$(BIN_DIR)/$(OUTPUT).map,--cref,--gc-sections $(LIB_DIRS)\n\nASM_OBJS     := $(patsubst %.s,%.o,  $(notdir $(ASM_SRCS)))\nC_OBJS       := $(patsubst %.c,%.o,  $(notdir $(C_SRCS)))\nCPP_OBJS     := $(patsubst %.cpp,%.o,$(notdir $(CPP_SRCS)))\n\nTARGET_BIN   := $(BIN_DIR)/$(OUTPUT).bin\nTARGET_ELF   := $(BIN_DIR)/$(OUTPUT).elf\nASM_OBJS_EXT := $(addprefix $(BIN_DIR)/, $(ASM_OBJS))\nC_OBJS_EXT   := $(addprefix $(BIN_DIR)/, $(C_OBJS))\nC_DEPS_EXT   := $(patsubst %.o, %.d, $(C_OBJS_EXT))\nCPP_OBJS_EXT := $(addprefix $(BIN_DIR)/, $(CPP_OBJS))\nCPP_DEPS_EXT := $(patsubst %.o, %.d, $(CPP_OBJS_EXT))\n\n# create $(BIN_DIR) if it does not exist\nifeq (\"$(wildcard $(BIN_DIR))\",\"\")\n$(shell $(MKDIR) $(BIN_DIR))\nendif\n\n#-----------------------------------------------------------------------------\n# rules\n#\n\n.PHONY : run norun flash\n\nifeq ($(MAKECMDGOALS),norun)\nall : $(TARGET_BIN)\nnorun : all\nelse\nall : $(TARGET_BIN) run\nendif\n\n$(TARGET_BIN): $(TARGET_ELF)\n\t$(BIN) -O binary $< $@\n\n$(TARGET_ELF) : $(ASM_OBJS_EXT) $(C_OBJS_EXT) $(CPP_OBJS_EXT)\n\t$(LINK) $(LINKFLAGS) -o $@ $^ $(LIBS)\n\n$(BIN_DIR)/%.d : %.c\n\t$(CC) -MM -MT $(@:.d=.o) $(CFLAGS) $< > $@\n\n$(BIN_DIR)/%.d : %.cpp\n\t$(CPP) -MM -MT $(@:.d=.o) $(CPPFLAGS) $< > $@\n\n$(BIN_DIR)/%.o : %.s\n\t$(AS) $(ASFLAGS) $< -o $@\n\n$(BIN_DIR)/%.o : %.c\n\t$(CC) $(CFLAGS) $< -o $@\n\n$(BIN_DIR)/%.o : %.cpp\n\t$(CPP) $(CPPFLAGS) $< -o $@\n\n.PHONY : clean show\n\n# include dependency files only if our goal depends on their existence\nifneq ($(MAKECMDGOALS),clean)\n  ifneq ($(MAKECMDGOALS),show)\n-include $(C_DEPS_EXT) $(CPP_DEPS_EXT)\n  endif\nendif\n\n\nclean :\n\t-$(RM) $(BIN_DIR)/*.o \\\n\t$(BIN_DIR)/*.d \\\n\t$(BIN_DIR)/*.bin \\\n\t$(BIN_DIR)/*.elf \\\n\t$(BIN_DIR)/*.map\n\t\nshow:\n\t@echo PROJECT = $(PROJECT)\n\t@echo CONF = $(CONF)\n\t@echo DEFINES = $(DEFINES)\n\t@echo ASM_FPU = $(ASM_FPU)\n\t@echo ASM_SRCS = $(ASM_SRCS)\n\t@echo C_SRCS = $(C_SRCS)\n\t@echo CPP_SRCS = $(CPP_SRCS)\n\t@echo ASM_OBJS_EXT = $(ASM_OBJS_EXT)\n\t@echo C_OBJS_EXT = $(C_OBJS_EXT)\n\t@echo C_DEPS_EXT = $(C_DEPS_EXT)\n\t@echo CPP_DEPS_EXT = $(CPP_DEPS_EXT)\n\t@echo TARGET_ELF = $(TARGET_ELF)\n"
  },
  {
    "path": "sst_cpp/examples/blinky_button/iar/ek-tm4c123gxl.ewd",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<project>\n    <fileVersion>3</fileVersion>\n    <configuration>\n        <name>Debug</name>\n        <toolchain>\n            <name>ARM</name>\n        </toolchain>\n        <debug>1</debug>\n        <settings>\n            <name>C-SPY</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>32</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CInput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CEndian</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCVariant</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>MemOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MemFile</name>\n                    <state>$TOOLKIT_DIR$\\CONFIG\\debugger\\TexasInstruments\\TM4C123GH6PM.ddf</state>\n                </option>\n                <option>\n                    <name>RunToEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RunToName</name>\n                    <state>main</state>\n                </option>\n                <option>\n                    <name>CExtraOptionsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCDDFArgumentProducer</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCDownloadSuppressDownload</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCDownloadVerifyAll</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProductVersion</name>\n                    <state>9.10.2.39304</state>\n                </option>\n                <option>\n                    <name>OCDynDriverList</name>\n                    <state>LMIFTDI_ID</state>\n                </option>\n                <option>\n                    <name>OCLastSavedByProductVersion</name>\n                    <state>9.32.1.54977</state>\n                </option>\n                <option>\n                    <name>UseFlashLoader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CLowLevel</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCBE8Slave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacFile2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CDevice</name>\n                    <state>1</state>\n                </option>\n                <option>\n              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</option>\n                <option>\n                    <name>OCDeviceConfigMacroFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCDebuggerExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCAllMTBOptions</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCMulticoreNrOfCores</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCMulticoreWorkspace</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCMulticoreSlaveProject</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCMulticoreSlaveConfiguration</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCDownloadExtraImage</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCAttachSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MassEraseBeforeFlashing</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCMulticoreNrOfCoresSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCMulticoreAMPConfigType</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCMulticoreSessionFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCTpiuBaseOption</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>ARMSIM_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>1</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCSimDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCSimEnablePSP</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCSimPspOverrideConfig</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCSimPspConfigFile</name>\n                    <state></state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CADI_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CCadiMemory</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>Fast Model</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCADILogFileCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCADILogFileEditB</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CMSISDAP_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>4</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCIarProbeScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CMSISDAPResetList</name>\n                    <version>1</version>\n                    <state>10</state>\n                </option>\n                <option>\n                    <name>CMSISDAPHWResetDuration</name>\n                    <state>300</state>\n                </option>\n                <option>\n                    <name>CMSISDAPHWResetDelay</name>\n                    <state>200</state>\n                </option>\n                <option>\n                    <name>CMSISDAPDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CMSISDAPInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CMSISDAPInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiTargetEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPJtagSpeedList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPRestoreBreakpointsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPUpdateBreakpointsEdit</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>RDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchUndef</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchData</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchPrefetch</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchMMERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchNOCPERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchCHKERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSTATERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchBUSERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchINTERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSFERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchHARDERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiCPUEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiCPUNumber</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeCfgOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeConfig</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CMSISDAPProbeConfigRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPSelectedCPUBehaviour</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ICpuName</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCJetEmuParams</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCCMSISDAPUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCCMSISDAPUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>GDBSERVER_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>TCPIP</name>\n                    <state>aaa.bbb.ccc.ddd</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCJTagBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJTagDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJTagUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>IJET_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>9</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCIarProbeScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetResetList</name>\n                    <version>1</version>\n                    <state>10</state>\n                </option>\n                <option>\n                    <name>IjetHWResetDuration</name>\n                    <state>300</state>\n                </option>\n                <option>\n                    <name>IjetHWResetDelay</name>\n                    <state>200</state>\n                </option>\n                <option>\n                    <name>IjetPowerFromProbe</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetPowerRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>IjetInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiTargetEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetScanChainNonARMDevices</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetIRLength</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetJtagSpeedList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetProtocolRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetSwoPin</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IjetSwoPrescalerList</name>\n                    <version>1</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetRestoreBreakpointsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetUpdateBreakpointsEdit</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>RDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchUndef</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchData</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchPrefetch</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchMMERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchNOCPERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchCHKERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSTATERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchBUSERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchINTERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSFERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchHARDERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeCfgOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeConfig</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IjetProbeConfigRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiCPUEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiCPUNumber</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetSelectedCPUBehaviour</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ICpuName</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCJetEmuParams</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetPreferETB</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetTraceSettingsList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetTraceSizeList</name>\n                    <version>0</version>\n                    <state>4</state>\n                </option>\n                <option>\n                    <name>FlashBoardPathSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCIjetUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCIjetUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL3S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL3S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL3S</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>JLINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>16</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>JLinkSpeed</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCJLinkDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCJLinkHWResetDelay</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>JLinkInitialSpeed</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCDoJlinkMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCScanChainNonARMDevices</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkIRLength</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkCommRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkTCPIP</name>\n                    <state>aaa.bbb.ccc.ddd</state>\n                </option>\n                <option>\n                    <name>CCJLinkSpeedRadioV2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCUSBDevice</name>\n                    <version>1</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCRDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchUndef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchData</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchPrefetch</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCJLinkInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJLinkResetList</name>\n                    <version>6</version>\n                    <state>5</state>\n                </option>\n                <option>\n                    <name>CCJLinkInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJLinkUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCTcpIpAlt</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkTcpIpSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSwoClockAuto</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSwoClockEdit</name>\n                    <state>2000</state>\n                </option>\n                <option>\n                    <name>OCJLinkTraceSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkTraceSourceDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkDeviceName</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>LMIFTDI_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>3</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>LmiftdiSpeed</name>\n                    <state>500</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCLmiFtdiInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCLmiFtdiInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCLmiftdiUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiResetList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>NULINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>PEMICRO_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>3</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJPEMicroShowSettings</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>STLINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>8</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSTLinkInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSTLinkInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkResetList</name>\n                    <version>3</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSwoClockAuto</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSwoClockEdit</name>\n                    <state>2000</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCSTLinkDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSTLinkUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkJtagSpeedList</name>\n                    <version>2</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkDAPNumber</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSTLinkDebugAccessPortRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUseServerSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkProbeList</name>\n                    <version>1</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkTargetVccEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSTLinkTargetVoltage</name>\n                    <state>###Uninitialized###</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>THIRDPARTY_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CThirdPartyDriverDll</name>\n                    <state>###Uninitialized###</state>\n                </option>\n                <option>\n                    <name>CThirdPartyLogFileCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CThirdPartyLogFileEditB</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>OCDriverInfo</name>\n                    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<name>CCXds100DoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100UpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchUndef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchData</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchPrefetch</name>\n                    <state>0</state>\n                </option>\n              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 </option>\n                <option>\n                    <name>CCXds100SwoClockEdit</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCXds100HWResetDelay</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100ResetList</name>\n                    <version>1</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100UsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCXds100UsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100JtagSpeedList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100InterfaceRadio</name>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCXds100InterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100ProbeList</name>\n                    <version>0</version>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>CCXds100SWOPortRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100SWOPort</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCXDSTargetVccEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXDSTargetVoltage</name>\n                    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  },
  {
    "path": "sst_cpp/examples/blinky_button/iar/ek-tm4c123gxl.ewp",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<project>\n    <fileVersion>3</fileVersion>\n    <configuration>\n        <name>Debug</name>\n        <toolchain>\n            <name>ARM</name>\n        </toolchain>\n        <debug>1</debug>\n        <settings>\n            <name>General</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <version>35</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>BrowseInfoPath</name>\n                    <state>build_ek-tm4c123gxl</state>\n                </option>\n                <option>\n                    <name>ExePath</name>\n                    <state>build_ek-tm4c123gxl</state>\n                </option>\n                <option>\n                    <name>ObjPath</name>\n                    <state>build_ek-tm4c123gxl</state>\n                </option>\n                <option>\n                    <name>ListPath</name>\n                    <state>build_ek-tm4c123gxl</state>\n                </option>\n                <option>\n                    <name>GEndianMode</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>Input description</name>\n                    <state>No specifier n, no float nor long long, no scan set, no assignment suppressing, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>Output description</name>\n                    <state>No specifier a, A, no specifier n, no float nor long long, no flags, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>GOutputBinary</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGCoreOrChip</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelect</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelectSlave</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RTDescription</name>\n                    <state>Use the normal configuration of the C/C++ runtime library. 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                 <name>CCObjPrefix</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCAllowList</name>\n                    <version>1</version>\n                    <state>10010100</state>\n                </option>\n                <option>\n                    <name>CCDebugInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IEndianMode</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IExtraOptionsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IExtraOptions</name>\n                    <state></state>\n                </option>\n               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<name>CCPosIndNoDynInit</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccLang</name>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>IccCDialect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccAllowVLA</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccStaticDestr</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccCppInlineSemantics</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccCmsis</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    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<state>1</state>\n                </option>\n                <option>\n                    <name>Includes</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacDefs</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacExps</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacExec</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OnlyAssed</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MultiLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PageLengthCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PageLength</name>\n                    <state>80</state>\n                </option>\n                <option>\n                    <name>TabSpacing</name>\n                    <state>8</state>\n                </option>\n                <option>\n                    <name>AXRef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefDefines</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefInternal</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefDual</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AOutputFile</name>\n                    <state>$FILE_BNAME$.o</state>\n                </option>\n                <option>\n                    <name>ALimitErrorsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ALimitErrorsEdit</name>\n                    <state>100</state>\n                </option>\n                <option>\n                    <name>AIgnoreStdInclude</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AUserIncludes</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AExtraOptionsCheckV2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AExtraOptionsV2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AsmNoLiteralPool</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PreInclude</name>\n                    <state></state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>OBJCOPY</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>1</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OOCOutputFormat</name>\n                    <version>3</version>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>OCOutputOverride</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OOCOutputFile</name>\n                    <state>blinky_button.bin</state>\n                </option>\n                <option>\n                    <name>OOCCommandLineProducer</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OOCObjCopyEnable</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CUSTOM</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <extensions></extensions>\n                <cmdline></cmdline>\n                <hasPrio>1</hasPrio>\n                <buildSequence>inputOutputBased</buildSequence>\n            </data>\n        </settings>\n        <settings>\n            <name>BUILDACTION</name>\n            <archiveVersion>1</archiveVersion>\n            <data>\n                <prebuild></prebuild>\n                <postbuild></postbuild>\n            </data>\n        </settings>\n        <settings>\n            <name>ILINK</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>27</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>IlinkLibIOConfig</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkInputFileSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOutputFile</name>\n                    <state>blinky_button.out</state>\n                </option>\n                <option>\n                    <name>IlinkDebugInfoEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkKeepSymbols</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySymbol</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySegment</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryAlign</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkDefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkConfigDefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkMapFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLogFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogInitialization</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogModule</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogSection</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogVeneer</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFile</name>\n                    <state>$TOOLKIT_DIR$\\config\\linker\\TexasInstruments\\TM4C123GH6.icf</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFileSlave</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkEnableRemarks</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkSuppressDiags</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsRem</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsWarn</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsErr</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkWarningsAreErrors</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkUseExtraOptions</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkLowLevelInterfaceSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkAutoLibEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkAdditionalLibs</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkOverrideProgramEntryLabel</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkProgramEntryLabelSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkProgramEntryLabel</name>\n                    <state>__iar_program_start</state>\n                </option>\n                <option>\n                    <name>DoFill</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>FillerByte</name>\n                    <state>0xFF</state>\n                </option>\n                <option>\n                    <name>FillerStart</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>FillerEnd</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>CrcSize</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcAlign</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcPoly</name>\n                    <state>0x11021</state>\n                </option>\n                <option>\n                    <name>CrcCompl</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CrcBitOrder</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CrcInitialValue</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>DoCrc</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkBE8Slave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkBufferedTerminalOutput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkStdoutInterfaceSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcFullSize</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIElfToolPostProcess</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogAutoLibSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogRedirSymbols</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogUnusedFragments</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCrcReverseByteOrder</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCrcUseAsInput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptInline</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOptExceptionsAllow</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOptExceptionsForce</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCmsis</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptMergeDuplSections</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOptUseVfe</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptForceVfe</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkStackAnalysisEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkStackControlFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkStackCallGraphFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CrcAlgorithm</name>\n                    <version>1</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcUnitSize</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkThreadsSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLogCallGraph</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFile_AltDefault</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkEncInput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutputBom</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkHeapSelect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLocaleSelect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkTrustzoneImportLibraryOut</name>\n                    <state>iar_ek-tm4c123gxl_import_lib.o</state>\n                </option>\n                <option>\n                    <name>OILinkExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryFile2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySymbol2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySegment2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryAlign2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkLogCrtRoutineSelection</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogFragmentInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogInlining</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogMerging</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkDemangle</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkWrapperFileEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkWrapperFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkFpuProcessor</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>IARCHIVE</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>IarchiveInputs</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IarchiveOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IarchiveOutput</name>\n                    <state>###Unitialized###</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>Coder</name>\n            <archiveVersion>0</archiveVersion>\n            <data />\n        </settings>\n    </configuration>\n    <group>\n        <name>Application</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\blinky1.cpp</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\blinky3.cpp</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\bsp.hpp</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\bsp_ek-tm4c123gxl.cpp</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\button2a.cpp</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\button2b.cpp</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\main.cpp</name>\n        </file>\n    </group>\n    <group>\n        <name>ek-tm4c123gxl</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\ek-tm4c123gxl\\iar\\startup_TM4C123GH6PM.s</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\ek-tm4c123gxl\\system_TM4C123GH6PM.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\ek-tm4c123gxl\\TM4C123GH6PM.h</name>\n        </file>\n    </group>\n    <group>\n        <name>sst</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\src\\sst.cpp</name>\n        </file>\n    </group>\n    <group>\n        <name>sst_port</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\ports\\arm-cm\\sst_port.cpp</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\ports\\arm-cm\\sst_port.hpp</name>\n        </file>\n    </group>\n</project>\n"
  },
  {
    "path": "sst_cpp/examples/blinky_button/iar/ek-tm4c123gxl.eww",
    "content": "<?xml version=\"1.0\" encoding=\"iso-8859-1\"?>\n\n<workspace>\n  <project>\n    <path>$WS_DIR$\\ek-tm4c123gxl.ewp</path>\n  </project>\n  <batchBuild/>\n</workspace>\n\n\n"
  },
  {
    "path": "sst_cpp/examples/blinky_button/iar/nucleo-c031c6.ewd",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<project>\n    <fileVersion>3</fileVersion>\n    <configuration>\n        <name>Debug</name>\n        <toolchain>\n            <name>ARM</name>\n        </toolchain>\n        <debug>1</debug>\n        <settings>\n            <name>C-SPY</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>32</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CInput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CEndian</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCVariant</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>MemOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MemFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>RunToEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RunToName</name>\n                    <state>main</state>\n                </option>\n                <option>\n                    <name>CExtraOptionsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCDDFArgumentProducer</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCDownloadSuppressDownload</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCDownloadVerifyAll</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProductVersion</name>\n                    <state>9.32.1.54977</state>\n                </option>\n                <option>\n                    <name>OCDynDriverList</name>\n                    <state>STLINK_ID</state>\n                </option>\n                <option>\n                    <name>OCLastSavedByProductVersion</name>\n                    <state>9.32.1.54977</state>\n                </option>\n                <option>\n                    <name>UseFlashLoader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CLowLevel</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCBE8Slave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacFile2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CDevice</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>FlashLoadersV3</name>\n                    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<name>OCDeviceConfigMacroFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCDebuggerExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCAllMTBOptions</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCMulticoreNrOfCores</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCMulticoreWorkspace</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCMulticoreSlaveProject</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCMulticoreSlaveConfiguration</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCDownloadExtraImage</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCAttachSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MassEraseBeforeFlashing</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCMulticoreNrOfCoresSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCMulticoreAMPConfigType</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCMulticoreSessionFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCTpiuBaseOption</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>ARMSIM_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>1</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCSimDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCSimEnablePSP</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCSimPspOverrideConfig</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCSimPspConfigFile</name>\n                    <state></state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CADI_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CCadiMemory</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>Fast Model</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCADILogFileCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCADILogFileEditB</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CMSISDAP_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>4</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCIarProbeScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CMSISDAPResetList</name>\n                    <version>1</version>\n                    <state>10</state>\n                </option>\n                <option>\n                    <name>CMSISDAPHWResetDuration</name>\n                    <state>300</state>\n                </option>\n                <option>\n                    <name>CMSISDAPHWResetDelay</name>\n                    <state>200</state>\n                </option>\n                <option>\n                    <name>CMSISDAPDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CMSISDAPInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CMSISDAPInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiTargetEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPJtagSpeedList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPRestoreBreakpointsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPUpdateBreakpointsEdit</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>RDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchUndef</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchData</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchPrefetch</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchMMERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchNOCPERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchCHKERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSTATERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchBUSERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchINTERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSFERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchHARDERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiCPUEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiCPUNumber</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeCfgOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeConfig</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CMSISDAPProbeConfigRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPSelectedCPUBehaviour</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ICpuName</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCJetEmuParams</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCCMSISDAPUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCCMSISDAPUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>GDBSERVER_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>TCPIP</name>\n                    <state>aaa.bbb.ccc.ddd</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCJTagBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJTagDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJTagUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>IJET_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>9</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCIarProbeScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetResetList</name>\n                    <version>1</version>\n                    <state>10</state>\n                </option>\n                <option>\n                    <name>IjetHWResetDuration</name>\n                    <state>300</state>\n                </option>\n                <option>\n                    <name>IjetHWResetDelay</name>\n                    <state>200</state>\n                </option>\n                <option>\n                    <name>IjetPowerFromProbe</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetPowerRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>IjetInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiTargetEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetScanChainNonARMDevices</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetIRLength</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetJtagSpeedList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetProtocolRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetSwoPin</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IjetSwoPrescalerList</name>\n                    <version>1</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetRestoreBreakpointsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetUpdateBreakpointsEdit</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>RDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchUndef</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchData</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchPrefetch</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchMMERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchNOCPERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchCHKERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSTATERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchBUSERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchINTERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSFERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchHARDERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeCfgOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeConfig</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IjetProbeConfigRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiCPUEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiCPUNumber</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetSelectedCPUBehaviour</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ICpuName</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCJetEmuParams</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetPreferETB</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetTraceSettingsList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetTraceSizeList</name>\n                    <version>0</version>\n                    <state>4</state>\n                </option>\n                <option>\n                    <name>FlashBoardPathSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCIjetUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCIjetUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL3S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL3S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL3S</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>JLINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>16</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>JLinkSpeed</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCJLinkDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCJLinkHWResetDelay</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>JLinkInitialSpeed</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCDoJlinkMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCScanChainNonARMDevices</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkIRLength</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkCommRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkTCPIP</name>\n                    <state>aaa.bbb.ccc.ddd</state>\n                </option>\n                <option>\n                    <name>CCJLinkSpeedRadioV2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCUSBDevice</name>\n                    <version>1</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCRDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchUndef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchData</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchPrefetch</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCJLinkInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJLinkResetList</name>\n                    <version>6</version>\n                    <state>5</state>\n                </option>\n                <option>\n                    <name>CCJLinkInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJLinkUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCTcpIpAlt</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkTcpIpSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSwoClockAuto</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSwoClockEdit</name>\n                    <state>2000</state>\n                </option>\n                <option>\n                    <name>OCJLinkTraceSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkTraceSourceDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkDeviceName</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>LMIFTDI_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>3</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>LmiftdiSpeed</name>\n                    <state>500</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCLmiFtdiInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCLmiFtdiInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCLmiftdiUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiResetList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>NULINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>PEMICRO_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>3</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJPEMicroShowSettings</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>STLINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>8</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSTLinkInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSTLinkInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkResetList</name>\n                    <version>3</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSwoClockAuto</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSwoClockEdit</name>\n                    <state>2000</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCSTLinkDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSTLinkUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkJtagSpeedList</name>\n                    <version>2</version>\n                    <state>0</state>\n                </option>\n                <option>\n            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<state>1</state>\n                </option>\n                <option>\n                    <name>OCSelectedCoreName</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <debuggerPlugins>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\CMX\\CmxArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\CMX\\CmxTinyArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\embOS\\embOSPlugin.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\FreeRtos\\FreeRtosArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n      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  },
  {
    "path": "sst_cpp/examples/blinky_button/iar/nucleo-c031c6.ewp",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<project>\n    <fileVersion>3</fileVersion>\n    <configuration>\n        <name>Debug</name>\n        <toolchain>\n            <name>ARM</name>\n        </toolchain>\n        <debug>1</debug>\n        <settings>\n            <name>General</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <version>35</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>BrowseInfoPath</name>\n                    <state>build_nucleo-c031c6</state>\n                </option>\n                <option>\n                    <name>ExePath</name>\n                    <state>build_nucleo-c031c6</state>\n                </option>\n                <option>\n                    <name>ObjPath</name>\n                    <state>build_nucleo-c031c6</state>\n                </option>\n                <option>\n                    <name>ListPath</name>\n                    <state>build_nucleo-c031c6</state>\n                </option>\n                <option>\n                    <name>GEndianMode</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>Input description</name>\n                    <state>No specifier n, no float nor long long, no scan set, no assignment suppressing, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>Output description</name>\n                    <state>No specifier a, A, no specifier n, no float nor long long, no flags, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>GOutputBinary</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGCoreOrChip</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelect</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelectSlave</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RTDescription</name>\n                    <state>A compact configuration of the C/C++14 runtime library. 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<option>\n                    <name>OG_32_64Device</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>BuildFilesPath</name>\n                    <state>Debug</state>\n                </option>\n                <option>\n                    <name>PointerAuthentication</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>FPU64</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>ICCARM</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>37</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CCOptimizationNoSizeConstraints</name>\n                    <state>0</state>\n                </option>\n              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</option>\n                <option>\n                    <name>AOutputFile</name>\n                    <state>$FILE_BNAME$.o</state>\n                </option>\n                <option>\n                    <name>ALimitErrorsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ALimitErrorsEdit</name>\n                    <state>100</state>\n                </option>\n                <option>\n                    <name>AIgnoreStdInclude</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AUserIncludes</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AExtraOptionsCheckV2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AExtraOptionsV2</name>\n                    <state></state>\n             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<state>blinky_button.bin</state>\n                </option>\n                <option>\n                    <name>OOCCommandLineProducer</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OOCObjCopyEnable</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CUSTOM</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <extensions></extensions>\n                <cmdline></cmdline>\n                <hasPrio>1</hasPrio>\n                <buildSequence>inputOutputBased</buildSequence>\n            </data>\n        </settings>\n        <settings>\n            <name>BUILDACTION</name>\n            <archiveVersion>1</archiveVersion>\n            <data>\n                <prebuild></prebuild>\n                <postbuild></postbuild>\n            </data>\n        </settings>\n        <settings>\n            <name>ILINK</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>27</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>IlinkLibIOConfig</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkInputFileSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOutputFile</name>\n                    <state>blinky_button.out</state>\n                </option>\n                <option>\n                    <name>IlinkDebugInfoEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkKeepSymbols</name>\n                    <state></state>\n                </option>\n                <option>\n           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<state>1</state>\n                </option>\n                <option>\n                    <name>CrcPoly</name>\n                    <state>0x11021</state>\n                </option>\n                <option>\n                    <name>CrcCompl</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CrcBitOrder</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CrcInitialValue</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>DoCrc</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkBE8Slave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    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</option>\n                <option>\n                    <name>IlinkOptUseVfe</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptForceVfe</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkStackAnalysisEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkStackControlFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkStackCallGraphFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CrcAlgorithm</name>\n                    <version>1</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcUnitSize</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkThreadsSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLogCallGraph</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFile_AltDefault</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkEncInput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutputBom</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    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</option>\n                <option>\n                    <name>IlinkRawBinaryAlign2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkLogCrtRoutineSelection</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogFragmentInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogInlining</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogMerging</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkDemangle</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkWrapperFileEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkWrapperFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkFpuProcessor</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>IARCHIVE</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>IarchiveInputs</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IarchiveOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IarchiveOutput</name>\n                    <state>###Unitialized###</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>Coder</name>\n            <archiveVersion>0</archiveVersion>\n            <data />\n        </settings>\n    </configuration>\n    <mfc>\n        <configuration>Debug</configuration>\n    </mfc>\n    <group>\n        <name>Application</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\blinky1.cpp</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\blinky3.cpp</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\blinky_button.hpp</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\bsp.hpp</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\bsp_nucleo-c031c6.cpp</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\button2a.cpp</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\button2b.cpp</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\main.cpp</name>\n        </file>\n    </group>\n    <group>\n        <name>nucleo-c031c6</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\nucleo-c031c6\\iar\\startup_stm32c031xx.s</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\nucleo-c031c6\\stm32c031xx.h</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\nucleo-c031c6\\system_stm32c0xx.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\nucleo-c031c6\\system_stm32c0xx.h</name>\n        </file>\n    </group>\n    <group>\n        <name>sst</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\src\\sst.cpp</name>\n        </file>\n    </group>\n    <group>\n        <name>sst_port</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\ports\\arm-cm\\sst_port.cpp</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\ports\\arm-cm\\sst_port.hpp</name>\n        </file>\n    </group>\n</project>\n"
  },
  {
    "path": "sst_cpp/examples/blinky_button/iar/nucleo-c031c6.eww",
    "content": "<?xml version=\"1.0\" encoding=\"iso-8859-1\"?>\n\n<workspace>\n  <project>\n    <path>$WS_DIR$\\nucleo-c031c6.ewp</path>\n  </project>\n  <batchBuild/>\n</workspace>\n\n\n"
  },
  {
    "path": "sst_cpp/examples/blinky_button/iar/nucleo-h743zi.ewd",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<project>\n    <fileVersion>3</fileVersion>\n    <configuration>\n        <name>Debug</name>\n        <toolchain>\n            <name>ARM</name>\n        </toolchain>\n        <debug>1</debug>\n        <settings>\n            <name>C-SPY</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>32</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CInput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CEndian</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCVariant</name>\n                    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<name>OCDynDriverList</name>\n                    <state>STLINK_ID</state>\n                </option>\n                <option>\n                    <name>OCLastSavedByProductVersion</name>\n                    <state>9.32.1.54977</state>\n                </option>\n                <option>\n                    <name>UseFlashLoader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CLowLevel</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCBE8Slave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacFile2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CDevice</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    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       <option>\n                    <name>OCDeviceConfigMacroFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCDebuggerExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCAllMTBOptions</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCMulticoreNrOfCores</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCMulticoreWorkspace</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCMulticoreSlaveProject</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCMulticoreSlaveConfiguration</name>\n                    <state></state>\n       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<state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>ARMSIM_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>1</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCSimDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCSimEnablePSP</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCSimPspOverrideConfig</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCSimPspConfigFile</name>\n                    <state></state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CADI_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CCadiMemory</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>Fast Model</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCADILogFileCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCADILogFileEditB</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CMSISDAP_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>4</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCIarProbeScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CMSISDAPResetList</name>\n                    <version>1</version>\n                    <state>10</state>\n                </option>\n                <option>\n                    <name>CMSISDAPHWResetDuration</name>\n                    <state>300</state>\n                </option>\n                <option>\n                    <name>CMSISDAPHWResetDelay</name>\n                    <state>200</state>\n                </option>\n                <option>\n                    <name>CMSISDAPDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CMSISDAPInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CMSISDAPInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiTargetEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPJtagSpeedList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPRestoreBreakpointsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPUpdateBreakpointsEdit</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>RDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchUndef</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchData</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchPrefetch</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchMMERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchNOCPERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchCHKERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSTATERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchBUSERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchINTERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSFERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchHARDERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiCPUEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiCPUNumber</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeCfgOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeConfig</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CMSISDAPProbeConfigRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPSelectedCPUBehaviour</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ICpuName</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCJetEmuParams</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCCMSISDAPUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCCMSISDAPUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>GDBSERVER_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>TCPIP</name>\n                    <state>aaa.bbb.ccc.ddd</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCJTagBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJTagDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJTagUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>IJET_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>9</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCIarProbeScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetResetList</name>\n                    <version>1</version>\n                    <state>10</state>\n                </option>\n                <option>\n                    <name>IjetHWResetDuration</name>\n                    <state>300</state>\n                </option>\n                <option>\n                    <name>IjetHWResetDelay</name>\n                    <state>200</state>\n                </option>\n                <option>\n                    <name>IjetPowerFromProbe</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetPowerRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>IjetInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiTargetEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetScanChainNonARMDevices</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetIRLength</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetJtagSpeedList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetProtocolRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetSwoPin</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IjetSwoPrescalerList</name>\n                    <version>1</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetRestoreBreakpointsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetUpdateBreakpointsEdit</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>RDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchUndef</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchData</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchPrefetch</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchMMERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchNOCPERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchCHKERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSTATERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchBUSERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchINTERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSFERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchHARDERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeCfgOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeConfig</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IjetProbeConfigRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiCPUEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiCPUNumber</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetSelectedCPUBehaviour</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ICpuName</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCJetEmuParams</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetPreferETB</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetTraceSettingsList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetTraceSizeList</name>\n                    <version>0</version>\n                    <state>4</state>\n                </option>\n                <option>\n                    <name>FlashBoardPathSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCIjetUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCIjetUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL3S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL3S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL3S</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>JLINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>16</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>JLinkSpeed</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCJLinkDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCJLinkHWResetDelay</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>JLinkInitialSpeed</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCDoJlinkMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCScanChainNonARMDevices</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkIRLength</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkCommRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkTCPIP</name>\n                    <state>aaa.bbb.ccc.ddd</state>\n                </option>\n                <option>\n                    <name>CCJLinkSpeedRadioV2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCUSBDevice</name>\n                    <version>1</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCRDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchUndef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchData</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchPrefetch</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCJLinkInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJLinkResetList</name>\n                    <version>6</version>\n                    <state>5</state>\n                </option>\n                <option>\n                    <name>CCJLinkInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJLinkUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCTcpIpAlt</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkTcpIpSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSwoClockAuto</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSwoClockEdit</name>\n                    <state>2000</state>\n                </option>\n                <option>\n                    <name>OCJLinkTraceSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkTraceSourceDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkDeviceName</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>LMIFTDI_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>3</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>LmiftdiSpeed</name>\n                    <state>500</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCLmiFtdiInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCLmiFtdiInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCLmiftdiUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiResetList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>NULINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>PEMICRO_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>3</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJPEMicroShowSettings</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>STLINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>8</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSTLinkInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSTLinkInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkResetList</name>\n                    <version>3</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCpuClockEdit</name>\n                    <state>480</state>\n                </option>\n                <option>\n                    <name>CCSwoClockAuto</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSwoClockEdit</name>\n                    <state>2000</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCSTLinkDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSTLinkUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkJtagSpeedList</name>\n                    <version>2</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkDAPNumber</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSTLinkDebugAccessPortRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUseServerSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkProbeList</name>\n                    <version>1</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkTargetVccEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    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<name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>TIPackageOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TIPackage</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>BoardFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCXds100BreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100DoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100UpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchUndef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchData</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchPrefetch</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchSTATERR</name>\n                    <state>0</state>\n                </option>\n  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 </option>\n                <option>\n                    <name>CCXds100SwoClockEdit</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCXds100HWResetDelay</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100ResetList</name>\n                    <version>1</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100UsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCXds100UsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100JtagSpeedList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100InterfaceRadio</name>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCXds100InterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100ProbeList</name>\n                    <version>0</version>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>CCXds100SWOPortRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100SWOPort</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCXDSTargetVccEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXDSTargetVoltage</name>\n                    <state>###Uninitialized###</state>\n                </option>\n                <option>\n                    <name>OCXDSDigitalStatesConfigFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCSelectedCoreName</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <debuggerPlugins>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\CMX\\CmxArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\CMX\\CmxTinyArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\embOS\\embOSPlugin.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\FreeRtos\\FreeRtosArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\Mbed\\MbedArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\Mbed\\MbedArmPlugin2.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\OpenRTOS\\OpenRTOSPlugin.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\SafeRTOS\\SafeRTOSPlugin.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\SMX\\smxAwareIarArm9.ewplugin</file>\n                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  },
  {
    "path": "sst_cpp/examples/blinky_button/iar/nucleo-h743zi.ewp",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<project>\n    <fileVersion>3</fileVersion>\n    <configuration>\n        <name>Debug</name>\n        <toolchain>\n            <name>ARM</name>\n        </toolchain>\n        <debug>1</debug>\n        <settings>\n            <name>General</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <version>35</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>BrowseInfoPath</name>\n                    <state>build_nucleo-h743zi</state>\n                </option>\n                <option>\n                    <name>ExePath</name>\n                    <state>build_nucleo-h743zi</state>\n                </option>\n                <option>\n                    <name>ObjPath</name>\n                    <state>build_nucleo-h743zi</state>\n                </option>\n                <option>\n                    <name>ListPath</name>\n                    <state>build_nucleo-h743zi</state>\n                </option>\n                <option>\n                    <name>GEndianMode</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>Input description</name>\n                    <state>No specifier n, no float nor long long, no scan set, no assignment suppressing, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>Output description</name>\n                    <state>No specifier a, A, no specifier n, no float nor long long, no flags, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>GOutputBinary</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGCoreOrChip</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelect</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelectSlave</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RTDescription</name>\n                    <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\n                </option>\n                <option>\n                    <name>OGProductVersion</name>\n                    <state>5.11.0.50579</state>\n                </option>\n                <option>\n                    <name>OGLastSavedByProductVersion</name>\n                    <state>9.32.1.54977</state>\n                </option>\n                <option>\n                    <name>OGChipSelectEditMenu</name>\n                    <state>STM32H743ZI\tST STM32H743ZI</state>\n                </option>\n                <option>\n                    <name>GenLowLevelInterface</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GEndianModeBE</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    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<option>\n                    <name>OG_32_64Device</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>BuildFilesPath</name>\n                    <state>Debug</state>\n                </option>\n                <option>\n                    <name>PointerAuthentication</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>FPU64</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>ICCARM</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>37</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CCOptimizationNoSizeConstraints</name>\n                    <state>0</state>\n                </option>\n              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                 <name>CCListAssFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListAssSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEnableRemarks</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCDiagSuppress</name>\n                    <state>Pa050</state>\n                </option>\n                <option>\n                    <name>CCDiagRemark</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagWarning</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagError</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCObjPrefix</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCAllowList</name>\n                    <version>1</version>\n                    <state>10010100</state>\n                </option>\n                <option>\n                    <name>CCDebugInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IEndianMode</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IExtraOptionsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n      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<option>\n                    <name>CCLibConfigHeader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>PreInclude</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCIncludePath2</name>\n                    <state>$PROJ_DIR$\\..</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\include</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\ports\\arm-cm</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\CMSIS\\Include</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\nucleo-h743zi</state>\n                </option>\n                <option>\n                    <name>CCStdIncCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCodeSection</name>\n                    <state>.text</state>\n      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        </option>\n                <option>\n                    <name>AWarnRange2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>ADebug</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AltRegisterNames</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ADefines</name>\n                    <state>ewarm</state>\n                </option>\n                <option>\n                    <name>AList</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AListHeader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AListing</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>Includes</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacDefs</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacExps</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacExec</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OnlyAssed</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MultiLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PageLengthCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PageLength</name>\n                    <state>80</state>\n                </option>\n                <option>\n                    <name>TabSpacing</name>\n                    <state>8</state>\n                </option>\n                <option>\n                    <name>AXRef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefDefines</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefInternal</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefDual</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AOutputFile</name>\n                    <state>$FILE_BNAME$.o</state>\n                </option>\n                <option>\n                    <name>ALimitErrorsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ALimitErrorsEdit</name>\n                    <state>100</state>\n                </option>\n                <option>\n                    <name>AIgnoreStdInclude</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AUserIncludes</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AExtraOptionsCheckV2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AExtraOptionsV2</name>\n                    <state></state>\n             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<state>blinky_button.bin</state>\n                </option>\n                <option>\n                    <name>OOCCommandLineProducer</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OOCObjCopyEnable</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CUSTOM</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <extensions></extensions>\n                <cmdline></cmdline>\n                <hasPrio>1</hasPrio>\n                <buildSequence>inputOutputBased</buildSequence>\n            </data>\n        </settings>\n        <settings>\n            <name>BUILDACTION</name>\n            <archiveVersion>1</archiveVersion>\n            <data>\n                <prebuild></prebuild>\n                <postbuild></postbuild>\n            </data>\n        </settings>\n        <settings>\n            <name>ILINK</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>27</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>IlinkLibIOConfig</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkInputFileSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOutputFile</name>\n                    <state>blinky_button.out</state>\n                </option>\n                <option>\n                    <name>IlinkDebugInfoEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkKeepSymbols</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySymbol</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySegment</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryAlign</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkDefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkConfigDefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkMapFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLogFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogInitialization</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogModule</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogSection</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogVeneer</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFile</name>\n                    <state>$TOOLKIT_DIR$\\config\\linker\\ST\\stm32h743xI.icf</state>\n                </option>\n       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      <option>\n                    <name>IlinkUseExtraOptions</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkLowLevelInterfaceSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkAutoLibEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkAdditionalLibs</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkOverrideProgramEntryLabel</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkProgramEntryLabelSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkProgramEntryLabel</name>\n                    <state>__iar_program_start</state>\n                </option>\n                <option>\n                    <name>DoFill</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>FillerByte</name>\n                    <state>0xFF</state>\n                </option>\n                <option>\n                    <name>FillerStart</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>FillerEnd</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>CrcSize</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcAlign</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcPoly</name>\n                    <state>0x11021</state>\n                </option>\n                <option>\n                    <name>CrcCompl</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CrcBitOrder</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CrcInitialValue</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>DoCrc</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkBE8Slave</name>\n                    <state>1</state>\n                </option>\n      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               </option>\n                <option>\n                    <name>IlinkCrcReverseByteOrder</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCrcUseAsInput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptInline</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOptExceptionsAllow</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOptExceptionsForce</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCmsis</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptMergeDuplSections</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOptUseVfe</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptForceVfe</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkStackAnalysisEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkStackControlFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkStackCallGraphFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CrcAlgorithm</name>\n                    <version>1</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcUnitSize</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkThreadsSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLogCallGraph</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFile_AltDefault</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkEncInput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutputBom</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkHeapSelect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLocaleSelect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkTrustzoneImportLibraryOut</name>\n                    <state>iar_nucleo-h743zi_import_lib.o</state>\n                </option>\n                <option>\n                    <name>OILinkExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryFile2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySymbol2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySegment2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryAlign2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkLogCrtRoutineSelection</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogFragmentInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogInlining</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogMerging</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkDemangle</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkWrapperFileEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkWrapperFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkFpuProcessor</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>IARCHIVE</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>IarchiveInputs</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IarchiveOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IarchiveOutput</name>\n                    <state>###Unitialized###</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>Coder</name>\n            <archiveVersion>0</archiveVersion>\n            <data />\n        </settings>\n    </configuration>\n    <mfc>\n        <configuration>Debug</configuration>\n    </mfc>\n    <group>\n        <name>Application</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\blinky1.cpp</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\blinky3.cpp</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\blinky_button.hpp</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\bsp.hpp</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\bsp_nucleo-h743zi.cpp</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\button2a.cpp</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\button2b.cpp</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\main.cpp</name>\n        </file>\n    </group>\n    <group>\n        <name>nucleo-h743zi</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\nucleo-h743zi\\iar\\startup_stm32h743xx.s</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\nucleo-h743zi\\stm32h743xx.h</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\nucleo-h743zi\\system_stm32h7xx.c</name>\n        </file>\n    </group>\n    <group>\n        <name>sst</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\src\\sst.cpp</name>\n        </file>\n    </group>\n    <group>\n        <name>sst_port</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\ports\\arm-cm\\sst_port.cpp</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\ports\\arm-cm\\sst_port.hpp</name>\n        </file>\n    </group>\n</project>\n"
  },
  {
    "path": "sst_cpp/examples/blinky_button/iar/nucleo-h743zi.eww",
    "content": "<?xml version=\"1.0\" encoding=\"iso-8859-1\"?>\n\n<workspace>\n  <project>\n    <path>$WS_DIR$\\nucleo-h743zi.ewp</path>\n  </project>\n  <batchBuild/>\n</workspace>\n\n\n"
  },
  {
    "path": "sst_cpp/examples/blinky_button/iar/nucleo-l053r8.ewd",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<project>\n    <fileVersion>3</fileVersion>\n    <configuration>\n        <name>Debug</name>\n        <toolchain>\n            <name>ARM</name>\n        </toolchain>\n        <debug>1</debug>\n        <settings>\n            <name>C-SPY</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>32</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CInput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CEndian</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCVariant</name>\n                    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<name>OCDynDriverList</name>\n                    <state>STLINK_ID</state>\n                </option>\n                <option>\n                    <name>OCLastSavedByProductVersion</name>\n                    <state>9.32.1.54977</state>\n                </option>\n                <option>\n                    <name>UseFlashLoader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CLowLevel</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCBE8Slave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacFile2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CDevice</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    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       <option>\n                    <name>OCDeviceConfigMacroFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCDebuggerExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCAllMTBOptions</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCMulticoreNrOfCores</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCMulticoreWorkspace</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCMulticoreSlaveProject</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCMulticoreSlaveConfiguration</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCDownloadExtraImage</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCAttachSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MassEraseBeforeFlashing</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCMulticoreNrOfCoresSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCMulticoreAMPConfigType</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCMulticoreSessionFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCTpiuBaseOption</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>ARMSIM_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>1</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCSimDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCSimEnablePSP</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCSimPspOverrideConfig</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCSimPspConfigFile</name>\n                    <state></state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CADI_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CCadiMemory</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>Fast Model</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCADILogFileCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCADILogFileEditB</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CMSISDAP_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>4</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCIarProbeScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CMSISDAPResetList</name>\n                    <version>1</version>\n                    <state>10</state>\n                </option>\n                <option>\n                    <name>CMSISDAPHWResetDuration</name>\n                    <state>300</state>\n                </option>\n                <option>\n                    <name>CMSISDAPHWResetDelay</name>\n                    <state>200</state>\n                </option>\n                <option>\n                    <name>CMSISDAPDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CMSISDAPInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CMSISDAPInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiTargetEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPJtagSpeedList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPRestoreBreakpointsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPUpdateBreakpointsEdit</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>RDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchUndef</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchData</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchPrefetch</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchMMERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchNOCPERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchCHKERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSTATERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchBUSERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchINTERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSFERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchHARDERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiCPUEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiCPUNumber</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeCfgOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeConfig</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CMSISDAPProbeConfigRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPSelectedCPUBehaviour</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ICpuName</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCJetEmuParams</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCCMSISDAPUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCCMSISDAPUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>GDBSERVER_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>TCPIP</name>\n                    <state>aaa.bbb.ccc.ddd</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCJTagBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJTagDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJTagUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>IJET_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>9</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCIarProbeScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetResetList</name>\n                    <version>1</version>\n                    <state>10</state>\n                </option>\n                <option>\n                    <name>IjetHWResetDuration</name>\n                    <state>300</state>\n                </option>\n                <option>\n                    <name>IjetHWResetDelay</name>\n                    <state>200</state>\n                </option>\n                <option>\n                    <name>IjetPowerFromProbe</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetPowerRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>IjetInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiTargetEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetScanChainNonARMDevices</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetIRLength</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetJtagSpeedList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetProtocolRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetSwoPin</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IjetSwoPrescalerList</name>\n                    <version>1</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetRestoreBreakpointsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetUpdateBreakpointsEdit</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>RDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchUndef</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchData</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchPrefetch</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchMMERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchNOCPERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchCHKERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSTATERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchBUSERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchINTERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSFERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchHARDERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeCfgOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeConfig</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IjetProbeConfigRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiCPUEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiCPUNumber</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetSelectedCPUBehaviour</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ICpuName</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCJetEmuParams</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetPreferETB</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetTraceSettingsList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetTraceSizeList</name>\n                    <version>0</version>\n                    <state>4</state>\n                </option>\n                <option>\n                    <name>FlashBoardPathSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCIjetUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCIjetUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL3S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL3S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL3S</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>JLINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>16</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>JLinkSpeed</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCJLinkDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCJLinkHWResetDelay</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>JLinkInitialSpeed</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCDoJlinkMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCScanChainNonARMDevices</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkIRLength</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkCommRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkTCPIP</name>\n                    <state>aaa.bbb.ccc.ddd</state>\n                </option>\n                <option>\n                    <name>CCJLinkSpeedRadioV2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCUSBDevice</name>\n                    <version>1</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCRDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchUndef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchData</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchPrefetch</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCJLinkInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJLinkResetList</name>\n                    <version>6</version>\n                    <state>5</state>\n                </option>\n                <option>\n                    <name>CCJLinkInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJLinkUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCTcpIpAlt</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkTcpIpSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSwoClockAuto</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSwoClockEdit</name>\n                    <state>2000</state>\n                </option>\n                <option>\n                    <name>OCJLinkTraceSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkTraceSourceDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkDeviceName</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>LMIFTDI_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>3</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>LmiftdiSpeed</name>\n                    <state>500</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCLmiFtdiInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCLmiFtdiInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCLmiftdiUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiResetList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>NULINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>PEMICRO_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>3</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJPEMicroShowSettings</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>STLINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>8</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSTLinkInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSTLinkInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkResetList</name>\n                    <version>3</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSwoClockAuto</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSwoClockEdit</name>\n                    <state>2000</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCSTLinkDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSTLinkUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    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<name>CCSTLinkTargetVoltage</name>\n                    <state>3.3</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>THIRDPARTY_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CThirdPartyDriverDll</name>\n                    <state>###Uninitialized###</state>\n                </option>\n                <option>\n                    <name>CThirdPartyLogFileCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CThirdPartyLogFileEditB</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n            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<name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>TIPackageOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TIPackage</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>BoardFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCXds100BreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100DoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100UpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchUndef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchData</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchPrefetch</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCXds100SwoClockAuto</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100SwoClockEdit</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCXds100HWResetDelay</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100ResetList</name>\n                    <version>1</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100UsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCXds100UsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100JtagSpeedList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100InterfaceRadio</name>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCXds100InterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100ProbeList</name>\n                    <version>0</version>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>CCXds100SWOPortRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100SWOPort</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCXDSTargetVccEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXDSTargetVoltage</name>\n                    <state>###Uninitialized###</state>\n                </option>\n                <option>\n                    <name>OCXDSDigitalStatesConfigFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCSelectedCoreName</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <debuggerPlugins>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\CMX\\CmxArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\CMX\\CmxTinyArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\embOS\\embOSPlugin.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\FreeRtos\\FreeRtosArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\Mbed\\MbedArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\Mbed\\MbedArmPlugin2.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\OpenRTOS\\OpenRTOSPlugin.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\SafeRTOS\\SafeRTOSPlugin.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\SMX\\smxAwareIarArm9.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\SMX\\smxAwareIarArm9BE.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\ThreadX\\ThreadXArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\uCOS-II\\uCOS-II-286-KA-CSpy.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\uCOS-II\\uCOS-II-KA-CSpy.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\uCOS-III\\uCOS-III-KA-CSpy.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                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  },
  {
    "path": "sst_cpp/examples/blinky_button/iar/nucleo-l053r8.ewp",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<project>\n    <fileVersion>3</fileVersion>\n    <configuration>\n        <name>Debug</name>\n        <toolchain>\n            <name>ARM</name>\n        </toolchain>\n        <debug>1</debug>\n        <settings>\n            <name>General</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <version>35</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>BrowseInfoPath</name>\n                    <state>build_nucleo-l053r8</state>\n                </option>\n                <option>\n                    <name>ExePath</name>\n                    <state>build_nucleo-l053r8</state>\n                </option>\n                <option>\n                    <name>ObjPath</name>\n                    <state>build_nucleo-l053r8</state>\n                </option>\n                <option>\n                    <name>ListPath</name>\n                    <state>build_nucleo-l053r8</state>\n                </option>\n                <option>\n                    <name>GEndianMode</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>Input description</name>\n                    <state>No specifier n, no float nor long long, no scan set, no assignment suppressing, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>Output description</name>\n                    <state>No specifier a, A, no specifier n, no float nor long long, no flags, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>GOutputBinary</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGCoreOrChip</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelect</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelectSlave</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RTDescription</name>\n                    <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\n                </option>\n                <option>\n                    <name>OGProductVersion</name>\n                    <state>5.11.0.50579</state>\n                </option>\n                <option>\n                    <name>OGLastSavedByProductVersion</name>\n                    <state>9.32.1.54977</state>\n                </option>\n                <option>\n                    <name>OGChipSelectEditMenu</name>\n                    <state>STM32L053R8\tST STM32L053R8</state>\n                </option>\n                <option>\n                    <name>GenLowLevelInterface</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GEndianModeBE</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OGBufferedTerminalOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GenStdoutInterface</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RTConfigPath2</name>\n                    <state>$TOOLKIT_DIR$\\inc\\c\\DLib_Config_Normal.h</state>\n                </option>\n                <option>\n                    <name>GBECoreSlave</name>\n                    <version>32</version>\n                    <state>35</state>\n                </option>\n                <option>\n                    <name>OGUseCmsis</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGUseCmsisDspLib</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibThreads</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CoreVariant</name>\n                    <version>32</version>\n                    <state>35</state>\n                </option>\n                <option>\n                    <name>GFPUDeviceSlave</name>\n                    <state>STM32L053R8\tST STM32L053R8</state>\n                </option>\n                <option>\n                    <name>FPU2</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>NrRegs</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>NEON</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GFPUCoreSlave2</name>\n                    <version>32</version>\n                    <state>35</state>\n                </option>\n                <option>\n                    <name>OGCMSISPackSelectDevice</name>\n                </option>\n                <option>\n                    <name>OgLibHeap</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGLibAdditionalLocale</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGPrintfVariant</name>\n                    <version>0</version>\n                    <state>4</state>\n                </option>\n                <option>\n                    <name>OGPrintfMultibyteSupport</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGScanfVariant</name>\n                    <version>0</version>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>OGScanfMultibyteSupport</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GenLocaleTags</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>GenLocaleDisplayOnly</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DSPExtension</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TrustZone</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TrustZoneModes</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGAarch64Abi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OG_32_64Device</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>BuildFilesPath</name>\n                    <state>Debug</state>\n                </option>\n                <option>\n                    <name>PointerAuthentication</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>FPU64</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>ICCARM</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>37</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CCOptimizationNoSizeConstraints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCDefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCPreprocFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPreprocComments</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPreprocLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCMnemonics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCMessages</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListAssFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListAssSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEnableRemarks</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCDiagSuppress</name>\n                    <state>Pa050</state>\n                </option>\n                <option>\n                    <name>CCDiagRemark</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagWarning</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagError</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCObjPrefix</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCAllowList</name>\n                    <version>1</version>\n                    <state>10010100</state>\n                </option>\n                <option>\n                    <name>CCDebugInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IEndianMode</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IExtraOptionsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n      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<option>\n                    <name>CCLibConfigHeader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>PreInclude</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCIncludePath2</name>\n                    <state>$PROJ_DIR$\\..</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\include</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\ports\\arm-cm</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\CMSIS\\Include</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\nucleo-l053r8</state>\n                </option>\n                <option>\n                    <name>CCStdIncCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCodeSection</name>\n                    <state>.text</state>\n                </option>\n                <option>\n                    <name>IProcessorMode2</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCOptLevel</name>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCOptStrategy</name>\n                    <version>0</version>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCOptLevelSlave</name>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCPosIndRopi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPosIndRwpi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPosIndNoDynInit</name>\n                    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 <state>0</state>\n                </option>\n                <option>\n                    <name>IarchiveOutput</name>\n                    <state>###Unitialized###</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>Coder</name>\n            <archiveVersion>0</archiveVersion>\n            <data />\n        </settings>\n    </configuration>\n    <mfc>\n        <configuration>Debug</configuration>\n    </mfc>\n    <group>\n        <name>Application</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\blinky1.cpp</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\blinky3.cpp</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\blinky_button.hpp</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\bsp.hpp</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\bsp_nucleo-l053r8.cpp</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\button2a.cpp</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\button2b.cpp</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\main.cpp</name>\n        </file>\n    </group>\n    <group>\n        <name>nucleo-l053r8</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\nucleo-l053r8\\iar\\startup_stm32l053xx.s</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\nucleo-l053r8\\stm32l053xx.h</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\..\\3rd_party\\nucleo-l053r8\\system_stm32l0xx.c</name>\n        </file>\n    </group>\n    <group>\n        <name>sst</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\src\\sst.cpp</name>\n        </file>\n    </group>\n    <group>\n        <name>sst_port</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\ports\\arm-cm\\sst_port.cpp</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\ports\\arm-cm\\sst_port.hpp</name>\n        </file>\n    </group>\n</project>\n"
  },
  {
    "path": "sst_cpp/examples/blinky_button/iar/nucleo-l053r8.eww",
    "content": "<?xml version=\"1.0\" encoding=\"iso-8859-1\"?>\n\n<workspace>\n  <project>\n    <path>$WS_DIR$\\nucleo-l053r8.ewp</path>\n  </project>\n  <batchBuild/>\n</workspace>\n\n\n"
  },
  {
    "path": "sst_cpp/examples/blinky_button/main.cpp",
    "content": "//============================================================================\n// Super-Simple Tasker (SST/C++) Example\n//\n// Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n//\n// SPDX-License-Identifier: MIT\n//\n// Permission is hereby granted, free of charge, to any person obtaining a\n// copy of this software and associated documentation files (the \"Software\"),\n// to deal in the Software without restriction, including without limitation\n// the rights to use, copy, modify, merge, publish, distribute, sublicense,\n// and/or sell copies of the Software, and to permit persons to whom the\n// Software is furnished to do so, subject to the following conditions:\n//\n// The above copyright notice and this permission notice shall be included in\n// all copies or substantial portions of the Software.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n// DEALINGS IN THE SOFTWARE.\n//============================================================================\n#include \"sst.hpp\"           // SST framework\n#include \"bsp.hpp\"           // Board Support Package interface\n#include \"blinky_button.hpp\" // application shared interface\n\n//............................................................................\nint main() {\n    SST::init(); // initialize the SST kernel\n    BSP::init(); // initialize the Board Support Package\n\n    // instantiate and start all SST tasks...\n    static SST::Evt const *blinky1QSto[10]; // Event queue storage\n    App::AO_Blinky1->start(\n        1U,           // SST-priority\n        blinky1QSto,  // storage for the AO's queue\n        ARRAY_NELEM(blinky1QSto), // queue length\n        BSP::getWorkEvtBlinky1(0U)); // initialization event\n\n    static SST::Evt const *button2aQSto[8]; // Event queue storage\n    App::AO_Button2a->start(\n        2U,           // SST-priority\n        button2aQSto, // storage for the AO's queue\n        ARRAY_NELEM(button2aQSto), // queue length\n        nullptr);     // initialization event\n\n    static SST::Evt const *button2bQSto[6]; // Event queue storage\n    App::AO_Button2b->start(\n        2U,           // SST-priority\n        button2bQSto, // storage for the AO's queue\n        ARRAY_NELEM(button2bQSto), // queue length\n        nullptr);     // initialization event\n\n    static SST::Evt const *blinky3QSto[4]; // Event queue storage\n    App::AO_Blinky3->start(\n        3U,           // SST-priority\n        blinky3QSto,  // storage for the AO's queue\n        ARRAY_NELEM(blinky3QSto), // queue length\n        BSP::getWorkEvtBlinky3(0U)); // initialization event\n\n    return SST::Task::run(); // run the SST tasks\n    // NOTE: in embedded systems SST::Task::run() should not return\n}\n\n"
  },
  {
    "path": "sst_cpp/ports/arm-cm/sst_port.cpp",
    "content": "//============================================================================\n// Super-Simple Tasker (SST/C++) port to ARM Cortex-M\n//\n// Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n//\n// SPDX-License-Identifier: MIT\n//\n// Permission is hereby granted, free of charge, to any person obtaining a\n// copy of this software and associated documentation files (the \"Software\"),\n// to deal in the Software without restriction, including without limitation\n// the rights to use, copy, modify, merge, publish, distribute, sublicense,\n// and/or sell copies of the Software, and to permit persons to whom the\n// Software is furnished to do so, subject to the following conditions:\n//\n// The above copyright notice and this permission notice shall be included in\n// all copies or substantial portions of the Software.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n// DEALINGS IN THE SOFTWARE.\n//============================================================================\n#include \"sst.hpp\"      // Super-Simple Tasker (SST/C++)\n#include \"dbc_assert.h\" // Design By Contract (DBC) assertions\n\n#define NVIC_PEND    ((uint32_t volatile *)0xE000E200U)\n#define NVIC_EN      ((uint32_t volatile *)0xE000E100U)\n#define NVIC_IP      ((uint32_t volatile *)0xE000E400U)\n#define SCB_SYSPRI   ((uint32_t volatile *)0xE000ED14U)\n#define SCB_AIRCR   *((uint32_t volatile *)0xE000ED0CU)\n#define FPU_FPCCR   *((uint32_t volatile *)0xE000EF34U)\n\n//............................................................................\nnamespace { // unnamed namespace\n\nDBC_MODULE_NAME(\"sst_port\") // for DBC assertions in this module\n\n// # of unused interrupt priority bits in NVIC\nstatic std::uint32_t nvic_prio_shift;\n\n} // unnamed namespace\n\nnamespace SST {\n\n// SST kernel facilities -----------------------------------------------------\nvoid init(void) {\n    // determine number of NVIC priority bits by writing 0xFF to the\n    // NIVIC IP register for PendSV and then reading back the result,\n    // which has only the implemented bits set.\n    std::uint32_t tmp = SCB_SYSPRI[3];\n    SCB_SYSPRI[3] |= (0xFFU << 16U); // write 0xFF to PendSV prio\n    uint32_t prio = ((SCB_SYSPRI[3] >> 16U) & 0xFFU); // read back\n    SCB_SYSPRI[3] = tmp; // restore the original PendSV prio\n\n    for (tmp = 0U; tmp < 8U; ++tmp) {\n        if ((prio & (1U << tmp)) != 0U) {\n            break;\n        }\n    }\n    nvic_prio_shift = tmp;\n\n#if (__ARM_FP != 0)\n    // configure the FPU for SST\n    FPU_FPCCR |= (1U << 30U)    // automatic FPU state preservation (ASPEN)\n                 | (1U << 31U); // lazy stacking (LSPEN)\n#endif\n}\n//............................................................................\nvoid start(void) {\n    // Set the NVIC priority grouping to default 0\n    //\n    // NOTE:\n    // Typically the SST port to ARM Cortex-M should waste no NVIC priority\n    // bits for grouping. This code ensures this setting, but priority\n    // grouping can be still overridden in the application-specific\n    // callback SST_onStart().\n    //\n    std::uint32_t tmp = SCB_AIRCR;\n    // clear the key bits 31:16 and priority grouping bits 10:8\n    tmp &= ~((0xFFFFU << 16U) | (0x7U << 8U));\n    SCB_AIRCR = (0x05FAU << 16U) | tmp;\n}\n\n// SST Task facilities -------------------------------------------------------\nvoid Task::setPrio(TaskPrio prio) noexcept {\n    //! @pre\n    //! - the IRQ number must be already set\n    //! - the priority must fit in the NVIC\n    DBC_REQUIRE(200,\n                (m_nvic_irq != 0U)\n                && (prio <= (0xFFU >> nvic_prio_shift)));\n\n    // convert the SST direct priority (1,2,..) to NVIC priority...\n    std::uint32_t irq_prio = ((0xFFU >> nvic_prio_shift) + 1U - prio)\n                              << nvic_prio_shift;\n\n    SST_PORT_CRIT_STAT\n    SST_PORT_CRIT_ENTRY();\n    // set the Task priority of the associated IRQ\n    uint32_t tmp = NVIC_IP[m_nvic_irq >> 2U];\n    tmp &= ~(0xFFU << ((m_nvic_irq & 3U) << 3U));\n    tmp |= (irq_prio << ((m_nvic_irq & 3U) << 3U));\n    NVIC_IP[m_nvic_irq >> 2U] = tmp;\n\n    // enable the IRQ associated with the Task\n    NVIC_EN[m_nvic_irq >> 5U] = (1U << (m_nvic_irq & 0x1FU));\n    SST_PORT_CRIT_EXIT();\n\n    // store the address of NVIC_PEND address and the IRQ bit\n    m_nvic_pend = &NVIC_PEND[m_nvic_irq >> 5U];\n    m_nvic_irq  = (1U << (m_nvic_irq & 0x1FU));\n}\n//............................................................................\nvoid Task::activate(void) {\n    //! @pre the queue must have some events\n    DBC_REQUIRE(300, m_nUsed > 0U);\n\n    // get the event out of the queue\n    // NOTE: no critical section because me->tail is accessed only\n    // from this task\n    Evt const *e = m_qBuf[m_tail];\n    if (m_tail == 0U) { // need to wrap the tail?\n        m_tail = m_end; // wrap around\n    }\n    else {\n        --m_tail;\n    }\n    SST_PORT_CRIT_STAT\n    SST_PORT_CRIT_ENTRY();\n    // some events still present in the queue?\n    if ((--m_nUsed) > 0U) {\n        *m_nvic_pend = m_nvic_irq; // <=== pend the associated IRQ\n    }\n    SST_PORT_CRIT_EXIT();\n\n    // dispatch the received event to this task\n    dispatch(e); // virtual call\n    // TBD: implement event recycling\n}\n//............................................................................\nvoid Task::setIRQ(std::uint32_t irq) noexcept {\n    m_nvic_irq = irq;\n}\n\n//............................................................................\nLockKey Task::lock(TaskPrio ceiling) {\n#if (__ARM_ARCH == 6) // ARMv6-M?\n    // NOTE:\n    // ARMv6-M (Cortex-M0/M0+/M1) do NOT support the BASEPRI register\n    // and simple selective scheduler locking is not possible.\n    // Instead, on this architectures, SST scheduler lock can be\n    // implemented by temporarily raising the current task priority\n    // to the ceiling level.\n    //\n    /// TBD...\n    static_cast<void>(ceiling); // unused param for now\n    return 0U;\n#else  // ARMv7-M+\n    // NOTE:\n    // ARMv7-M+ support the BASEPRI register and the selective SST scheduler\n    // locking is implemented by setting BASEPRI to the ceiling level.\n    //\n    uint32_t nvic_prio = ((0xFFU >> nvic_prio_shift) + 1U - ceiling)\n                         << nvic_prio_shift;\n    LockKey basepri_; // initialized in the following asm() instruction\n    __asm volatile (\"mrs %0,BASEPRI\" : \"=r\" (basepri_) :: );\n    if (basepri_ > nvic_prio) { // current priority lower than the ceiling?\n        __asm volatile (\"cpsid i\\n msr BASEPRI,%0\\n cpsie i\"\n                        :: \"r\" (nvic_prio) : );\n    }\n    return basepri_;\n#endif\n}\n//............................................................................\nvoid Task::unlock(LockKey lock_key) {\n#if (__ARM_ARCH == 6) // ARMv6-M?\n    // TBD...\n    static_cast<void>(lock_key); // unused param for now\n#else  // ARMv7-M+\n    // NOTE:\n    // ARMv7-M+ support the BASEPRI register and the selective SST scheduler\n    // unlocking is implemented by restoring BASEPRI to the lock_key level.\n    //\n    __asm volatile (\"msr BASEPRI,%0\" :: \"r\" (lock_key) : );\n#endif\n}\n\n} // namespace SST\n"
  },
  {
    "path": "sst_cpp/ports/arm-cm/sst_port.hpp",
    "content": "//============================================================================\n// Super-Simple Tasker (SST/C++) port to ARM Cortex-M\n//\n// Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n//\n// SPDX-License-Identifier: MIT\n//\n// Permission is hereby granted, free of charge, to any person obtaining a\n// copy of this software and associated documentation files (the \"Software\"),\n// to deal in the Software without restriction, including without limitation\n// the rights to use, copy, modify, merge, publish, distribute, sublicense,\n// and/or sell copies of the Software, and to permit persons to whom the\n// Software is furnished to do so, subject to the following conditions:\n//\n// The above copyright notice and this permission notice shall be included in\n// all copies or substantial portions of the Software.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n// DEALINGS IN THE SOFTWARE.\n//============================================================================\n#ifndef SST_PORT_HPP_\n#define SST_PORT_HPP_\n\n// additional SST-PORT task attributes for ARM Cortex-M\n#define SST_PORT_TASK_ATTR \\\n    std::uint32_t volatile *m_nvic_pend; \\\n    std::uint32_t m_nvic_irq;\n\n// additional SST-PORT task operations for ARM Cortex-M\n#define SST_PORT_TASK_OPER \\\n    void activate(void); \\\n    void setPrio(TaskPrio prio) noexcept; \\\n    void setIRQ(std::uint32_t irq) noexcept;\n\n// SST-PORT critical section\n#define SST_PORT_CRIT_STAT\n#define SST_PORT_CRIT_ENTRY() __asm volatile (\"cpsid i\")\n#define SST_PORT_CRIT_EXIT()  __asm volatile (\"cpsie i\")\n\n// SST-PORT pend the Task after posting an event\n// NOTE: executed inside SST critical section.\n//\n#define SST_PORT_TASK_PEND()  *m_nvic_pend = m_nvic_irq\n\nnamespace SST {\n    void onIdle(void);\n\n    //! SST lock key\n    using LockKey = std::uint32_t;\n}\n\n#endif // SST_PORT_HPP_\n"
  },
  {
    "path": "sst_cpp/src/sst.cpp",
    "content": "//============================================================================\n// Super-Simple Tasker (SST/C++)\n//\n// Copyright (C) 2006-2023 Quantum Leaps, <state-machine.com>.\n//\n// SPDX-License-Identifier: MIT\n//\n// Permission is hereby granted, free of charge, to any person obtaining a\n// copy of this software and associated documentation files (the \"Software\"),\n// to deal in the Software without restriction, including without limitation\n// the rights to use, copy, modify, merge, publish, distribute, sublicense,\n// and/or sell copies of the Software, and to permit persons to whom the\n// Software is furnished to do so, subject to the following conditions:\n//\n// The above copyright notice and this permission notice shall be included in\n// all copies or substantial portions of the Software.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n// DEALINGS IN THE SOFTWARE.\n//============================================================================\n#include \"sst.hpp\"      // Super-Simple Tasker (SST) in C++\n#include \"dbc_assert.h\" // Design By Contract (DBC) assertions\n\n//............................................................................\nnamespace { // unnamed namespace\n\nDBC_MODULE_NAME(\"sst\")  // for DBC assertions in this module\n\n} // unnamed namespace\n\nnamespace SST {\n\n// SST kernel facilities -----------------------------------------------------\nint Task::run(void) {\n    SST::start(); // port-specific start of multitasking\n    onStart(); // configure and start the interrupts\n\n    for (;;) { // idle loop of the SST kernel\n        onIdle();\n    }\n}\n\n// SST Task facilities -------------------------------------------------------\nvoid Task::start(\n    TaskPrio prio,\n    Evt const **qBuf, QCtr qLen,\n    Evt const * const ie)\n{\n    //! @pre\n    //! - the priority must be greater than zero\n    //! - the queue storage and length must be provided\n    DBC_REQUIRE(200,\n        (0U < prio)\n        && (qBuf != nullptr) && (qLen > 0U));\n\n    m_qBuf  = qBuf;\n    m_end   = qLen - 1U;\n    m_head  = 0U;\n    m_tail  = 0U;\n    m_nUsed = 0U;\n\n    setPrio(prio);\n\n    // initialize this task with the initialization event\n    init(ie); // virtual call\n    // TBD: implement event recycling\n}\n//............................................................................\nvoid Task::post(Evt const * const e) noexcept {\n    //! @pre the queue must be sized adequately and cannot overflow\n    DBC_REQUIRE(300, m_nUsed <= m_end);\n\n    SST_PORT_CRIT_STAT\n    SST_PORT_CRIT_ENTRY();\n    m_qBuf[m_head] = e; // insert event into the queue\n    // need to wrap the head?\n    if (m_head == 0U) {\n        m_head = m_end; // wrap around\n    }\n    else {\n        --m_head;\n    }\n    ++m_nUsed;\n    SST_PORT_TASK_PEND();\n    SST_PORT_CRIT_EXIT();\n}\n\n//----------------------------------------------------------------------------\nstatic TimeEvt *timeEvt_head = nullptr;\n\n//............................................................................\nTimeEvt::TimeEvt(Signal sig, Task *task) {\n    this->sig  = sig;\n    m_task     = task;\n    m_ctr      = 0U;\n    m_interval = 0U;\n\n    // insert this time event into the linked-list\n    m_next = timeEvt_head;\n    timeEvt_head = this;\n}\n//............................................................................\nvoid TimeEvt::arm(TCtr ctr, TCtr interval) {\n    SST_PORT_CRIT_STAT\n    SST_PORT_CRIT_ENTRY();\n    m_ctr      = ctr;\n    m_interval = interval;\n    SST_PORT_CRIT_EXIT();\n}\n//............................................................................\nbool TimeEvt::disarm(void) {\n    SST_PORT_CRIT_STAT\n    SST_PORT_CRIT_ENTRY();\n    bool status = (m_ctr != 0U);\n    m_ctr       = 0U;\n    m_interval  = 0U;\n    SST_PORT_CRIT_EXIT();\n    return status;\n}\n//............................................................................\nvoid TimeEvt::tick(void) {\n    for (TimeEvt *t = timeEvt_head; t != nullptr; t = t->m_next) {\n        SST_PORT_CRIT_STAT\n        SST_PORT_CRIT_ENTRY();\n        if (t->m_ctr == 0U) { // disarmed? (most frequent case)\n            SST_PORT_CRIT_EXIT();\n        }\n        else if (t->m_ctr == 1U) { // expiring?\n            t->m_ctr = t->m_interval;\n            SST_PORT_CRIT_EXIT();\n\n            t->m_task->post(t);\n        }\n        else { // timing out\n            --t->m_ctr;\n            SST_PORT_CRIT_EXIT();\n        }\n    }\n}\n\n} // namespace SST\n"
  }
]